From evan.cheng at apple.com Mon Apr 10 02:21:44 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 10 Apr 2006 02:21:44 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp Message-ID: <200604100721.CAA15144@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86RegisterInfo.cpp updated: 1.135 -> 1.136 --- Log message: Use movaps to do VR128 reg-to-reg copies for now. It's shorter and available for SSE1. --- Diffs of the changes: (+1 -1) X86RegisterInfo.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/X86/X86RegisterInfo.cpp diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.135 llvm/lib/Target/X86/X86RegisterInfo.cpp:1.136 --- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.135 Fri Apr 7 11:34:46 2006 +++ llvm/lib/Target/X86/X86RegisterInfo.cpp Mon Apr 10 02:21:31 2006 @@ -115,7 +115,7 @@ } else if (RC == &X86::FR64RegClass) { Opc = X86::FsMOVAPDrr; } else if (RC == &X86::VR128RegClass) { - Opc = X86::MOVAPDrr; + Opc = X86::MOVAPSrr; } else { assert(0 && "Unknown regclass"); abort(); From evan.cheng at apple.com Mon Apr 10 02:22:15 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 10 Apr 2006 02:22:15 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/README.txt Message-ID: <200604100722.CAA15366@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: README.txt updated: 1.81 -> 1.82 --- Log message: New entries --- Diffs of the changes: (+19 -0) README.txt | 19 +++++++++++++++++++ 1 files changed, 19 insertions(+) Index: llvm/lib/Target/X86/README.txt diff -u llvm/lib/Target/X86/README.txt:1.81 llvm/lib/Target/X86/README.txt:1.82 --- llvm/lib/Target/X86/README.txt:1.81 Fri Apr 7 16:19:53 2006 +++ llvm/lib/Target/X86/README.txt Mon Apr 10 02:22:03 2006 @@ -765,3 +765,22 @@ A Mac OS X IA-32 specific ABI bug wrt returning value > 8 bytes: http://llvm.org/bugs/show_bug.cgi?id=729 + +//===---------------------------------------------------------------------===// + +#include + +void test(__m128 *res, __m128 *A) { + *res = _mm_shuffle_ps(*A, *A, 0xF0); +} + +We should emit + shufps $240, (%eax), %xmm0 +instead of + pshufd $240, (%eax), %xmm0 + +//===---------------------------------------------------------------------===// + +X86RegisterInfo::copyRegToReg() returns X86::MOVAPSrr for VR128. Is it possible +to choose between movaps, movapd, and movdqa based on types of source and +destination? From evan.cheng at apple.com Mon Apr 10 02:23:27 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 10 Apr 2006 02:23:27 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86InstrSSE.td Message-ID: <200604100723.CAA15795@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.160 -> 1.161 X86InstrSSE.td updated: 1.68 -> 1.69 --- Log message: Conditional move of vector types. --- Diffs of the changes: (+63 -37) X86ISelLowering.cpp | 85 +++++++++++++++++++++++++++++----------------------- X86InstrSSE.td | 15 +++++++++ 2 files changed, 63 insertions(+), 37 deletions(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.160 llvm/lib/Target/X86/X86ISelLowering.cpp:1.161 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.160 Fri Apr 7 16:53:05 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Apr 10 02:23:14 2006 @@ -275,13 +275,14 @@ if (Subtarget->hasSSE1()) { addRegisterClass(MVT::v4f32, X86::VR128RegisterClass); - setOperationAction(ISD::ADD, MVT::v4f32, Legal); - setOperationAction(ISD::SUB, MVT::v4f32, Legal); - setOperationAction(ISD::MUL, MVT::v4f32, Legal); - setOperationAction(ISD::LOAD, MVT::v4f32, Legal); - setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); - setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); + setOperationAction(ISD::ADD, MVT::v4f32, Legal); + setOperationAction(ISD::SUB, MVT::v4f32, Legal); + setOperationAction(ISD::MUL, MVT::v4f32, Legal); + setOperationAction(ISD::LOAD, MVT::v4f32, Legal); + setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); + setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); + setOperationAction(ISD::SELECT, MVT::v4f32, Custom); } if (Subtarget->hasSSE2()) { @@ -291,37 +292,46 @@ addRegisterClass(MVT::v4i32, X86::VR128RegisterClass); addRegisterClass(MVT::v2i64, X86::VR128RegisterClass); - - setOperationAction(ISD::ADD, MVT::v2f64, Legal); - setOperationAction(ISD::ADD, MVT::v16i8, Legal); - setOperationAction(ISD::ADD, MVT::v8i16, Legal); - setOperationAction(ISD::ADD, MVT::v4i32, Legal); - setOperationAction(ISD::SUB, MVT::v2f64, Legal); - setOperationAction(ISD::SUB, MVT::v16i8, Legal); - setOperationAction(ISD::SUB, MVT::v8i16, Legal); - setOperationAction(ISD::SUB, MVT::v4i32, Legal); - setOperationAction(ISD::MUL, MVT::v2f64, Legal); - setOperationAction(ISD::LOAD, MVT::v2f64, Legal); - setOperationAction(ISD::LOAD, MVT::v16i8, Legal); - setOperationAction(ISD::LOAD, MVT::v8i16, Legal); - setOperationAction(ISD::LOAD, MVT::v4i32, Legal); - setOperationAction(ISD::LOAD, MVT::v2i64, Legal); - setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); - setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); - setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); - setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom); - setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom); - setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom); - setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); - setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); - setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); - setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i16, Custom); - setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i32, Custom); - setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); + setOperationAction(ISD::ADD, MVT::v2f64, Legal); + setOperationAction(ISD::ADD, MVT::v16i8, Legal); + setOperationAction(ISD::ADD, MVT::v8i16, Legal); + setOperationAction(ISD::ADD, MVT::v4i32, Legal); + setOperationAction(ISD::SUB, MVT::v2f64, Legal); + setOperationAction(ISD::SUB, MVT::v16i8, Legal); + setOperationAction(ISD::SUB, MVT::v8i16, Legal); + setOperationAction(ISD::SUB, MVT::v4i32, Legal); + setOperationAction(ISD::MUL, MVT::v2f64, Legal); + setOperationAction(ISD::LOAD, MVT::v2f64, Legal); + setOperationAction(ISD::LOAD, MVT::v16i8, Legal); + setOperationAction(ISD::LOAD, MVT::v8i16, Legal); + setOperationAction(ISD::LOAD, MVT::v4i32, Legal); + setOperationAction(ISD::LOAD, MVT::v2i64, Legal); + setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); + setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); + setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); + setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom); + setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom); + setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom); + setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); + setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); + setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); + setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i16, Custom); + setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i32, Custom); + setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom); setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); + + // Promote v16i8, v8i16, v4i32 selects to v2i64. Custom lower v2i64, v2f64, + // and v4f32 selects. + for (unsigned VT = (unsigned)MVT::v16i8; + VT != (unsigned)MVT::v2i64; VT++) { + setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote); + AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v2i64); + } + setOperationAction(ISD::SELECT, MVT::v2i64, Custom); + setOperationAction(ISD::SELECT, MVT::v2f64, Custom); } // We want to custom lower some of our intrinsics. @@ -1270,7 +1280,10 @@ switch (MI->getOpcode()) { default: assert(false && "Unexpected instr type to insert"); case X86::CMOV_FR32: - case X86::CMOV_FR64: { + case X86::CMOV_FR64: + case X86::CMOV_V4F32: + case X86::CMOV_V2F64: + case X86::CMOV_V2I64: { // To "insert" a SELECT_CC instruction, we actually have to insert the // diamond control-flow pattern. The incoming instruction knows the // destination vreg to set, the condition code register to branch on, the @@ -2146,9 +2159,7 @@ } case ISD::SELECT: { MVT::ValueType VT = Op.getValueType(); - bool isFP = MVT::isFloatingPoint(VT); - bool isFPStack = isFP && !X86ScalarSSE; - bool isFPSSE = isFP && X86ScalarSSE; + bool isFPStack = MVT::isFloatingPoint(VT) && !X86ScalarSSE; bool addTest = false; SDOperand Op0 = Op.getOperand(0); SDOperand Cond, CC; Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.68 llvm/lib/Target/X86/X86InstrSSE.td:1.69 --- llvm/lib/Target/X86/X86InstrSSE.td:1.68 Fri Apr 7 19:47:44 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Mon Apr 10 02:23:14 2006 @@ -278,6 +278,21 @@ (ops FR64:$dst, FR64:$t, FR64:$f, i8imm:$cond), "#CMOV_FR64 PSEUDO!", [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond))]>; + def CMOV_V4F32 : I<0, Pseudo, + (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond), + "#CMOV_V4F32 PSEUDO!", + [(set VR128:$dst, + (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>; + def CMOV_V2F64 : I<0, Pseudo, + (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond), + "#CMOV_V2F64 PSEUDO!", + [(set VR128:$dst, + (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>; + def CMOV_V2I64 : I<0, Pseudo, + (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond), + "#CMOV_V2I64 PSEUDO!", + [(set VR128:$dst, + (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>; } // Move Instructions From evan.cheng at apple.com Mon Apr 10 02:30:26 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 10 Apr 2006 02:30:26 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/X86/vec_select.ll Message-ID: <200604100730.CAA18440@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/X86: vec_select.ll added (r1.1) --- Log message: Add a vselect test case. --- Diffs of the changes: (+11 -0) vec_select.ll | 11 +++++++++++ 1 files changed, 11 insertions(+) Index: llvm/test/Regression/CodeGen/X86/vec_select.ll diff -c /dev/null llvm/test/Regression/CodeGen/X86/vec_select.ll:1.1 *** /dev/null Mon Apr 10 02:30:23 2006 --- llvm/test/Regression/CodeGen/X86/vec_select.ll Mon Apr 10 02:30:13 2006 *************** *** 0 **** --- 1,11 ---- + ; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse + + void %test(int %C, <4 x float>* %A, <4 x float>* %B) { + %tmp = load <4 x float>* %A + %tmp3 = load <4 x float>* %B + %tmp9 = mul <4 x float> %tmp3, %tmp3 + %tmp = seteq int %C, 0 + %iftmp.38.0 = select bool %tmp, <4 x float> %tmp9, <4 x float> %tmp + store <4 x float> %iftmp.38.0, <4 x float>* %A + ret void + } From reid at x10sys.com Mon Apr 10 11:46:17 2006 From: reid at x10sys.com (Reid Spencer) Date: Mon, 10 Apr 2006 11:46:17 -0500 Subject: [llvm-commits] CVS: llvm/Makefile.rules Message-ID: <200604101646.LAA23131@zion.cs.uiuc.edu> Changes in directory llvm: Makefile.rules updated: 1.359 -> 1.360 --- Log message: ENABLE_ASSERTIONS -> DISABLE_ASSERTIONS --- Diffs of the changes: (+4 -4) Makefile.rules | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) Index: llvm/Makefile.rules diff -u llvm/Makefile.rules:1.359 llvm/Makefile.rules:1.360 --- llvm/Makefile.rules:1.359 Sun Apr 9 18:41:14 2006 +++ llvm/Makefile.rules Mon Apr 10 11:46:04 2006 @@ -222,8 +222,8 @@ endif endif -# If ENABLE_ASSERTIONS=1 is specified (make command line or configured), -# then enable assertions by defining the appropriate preprocessor symbols. +# If DISABLE_ASSERTIONS=1 is specified (make command line or configured), +# then disable assertions by defining the appropriate preprocessor symbols. ifdef DISABLE_ASSERTIONS BuildMode := $(BuildMode)-Asserts CXX.Flags += -DNDEBUG @@ -1527,7 +1527,7 @@ $(EchoCmd) Removing old $(DistDir) ; \ $(RM) -rf $(DistDir); \ $(EchoCmd) Making 'all' to verify build ; \ - $(MAKE) ENABLE_OPTIMIZED=1 ENABLE_ASSERTIONS=1 all ; \ + $(MAKE) ENABLE_OPTIMIZED=1 all ; \ fi $(Echo) Building Distribution Directory $(DistDir) $(Verb) $(MKDIR) $(DistDir) @@ -1588,7 +1588,7 @@ if test "$$subdir" \!= "." ; then \ new_distdir="$(DistDir)/$$subdir" ; \ test -d "$$new_distdir" || $(MKDIR) "$$new_distdir" || exit 1; \ - ( cd $$subdir && $(MAKE) ENABLE_OPTIMIZED=1 ENABLE_ASSERTIONS=1 \ + ( cd $$subdir && $(MAKE) ENABLE_OPTIMIZED=1 \ DistDir="$$new_distdir" distdir ) || exit 1; \ fi; \ done From evan.cheng at apple.com Mon Apr 10 13:54:48 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 10 Apr 2006 13:54:48 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <200604101854.NAA19620@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.357 -> 1.358 --- Log message: Missing break --- Diffs of the changes: (+1 -0) LegalizeDAG.cpp | 1 + 1 files changed, 1 insertion(+) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.357 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.358 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.357 Sat Apr 8 17:22:57 2006 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Apr 10 13:54:36 2006 @@ -4773,6 +4773,7 @@ assert(0 && "Cast from unsupported vector type not implemented yet!"); } } + break; case ISD::VSELECT: Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0), PackVectorOp(Op.getOperand(1), NewVT), From alenhar2 at cs.uiuc.edu Mon Apr 10 14:26:22 2006 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Mon, 10 Apr 2006 14:26:22 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/IPO/IndMemRemoval.cpp Message-ID: <200604101926.OAA27036@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/IPO: IndMemRemoval.cpp added (r1.1) --- Log message: Add a simple pass to make sure that all (non-library) calls to malloc and free are visible to analysis as intrinsics. That is, make sure someone doesn't pass free around by address in some struct (as happens in say 176.gcc). This doesn't get rid of any indirect calls, just ensure calls to free and malloc are always direct. --- Diffs of the changes: (+92 -0) IndMemRemoval.cpp | 92 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 92 insertions(+) Index: llvm/lib/Transforms/IPO/IndMemRemoval.cpp diff -c /dev/null llvm/lib/Transforms/IPO/IndMemRemoval.cpp:1.1 *** /dev/null Mon Apr 10 14:26:10 2006 --- llvm/lib/Transforms/IPO/IndMemRemoval.cpp Mon Apr 10 14:25:59 2006 *************** *** 0 **** --- 1,92 ---- + //===-- IndMemRemoval.cpp - Remove indirect allocations and frees ----------===// + // + // The LLVM Compiler Infrastructure + // + // This file was developed by the LLVM research group and is distributed under + // the University of Illinois Open Source License. See LICENSE.TXT for details. + // + //===----------------------------------------------------------------------===// + // + // This pass finds places where memory allocation functions may escape into + // indirect land. Some transforms are much easier (aka possible) only if free + // or malloc are not called indirectly. + // Thus find places where the address of memory functions are taken and construct + // bounce functions with direct calls of those functions. + // + //===----------------------------------------------------------------------===// + + #include "llvm/Transforms/IPO.h" + #include "llvm/Pass.h" + #include "llvm/Module.h" + #include "llvm/Function.h" + #include "llvm/Instructions.h" + #include "llvm/Type.h" + #include "llvm/Support/Debug.h" + #include "llvm/ADT/Statistic.h" + #include + #include + #include + using namespace llvm; + + namespace { + Statistic<> NumBounceSites("indmemrem", "Number of sites modified"); + Statistic<> NumBounce ("indmemrem", "Number of bounce functions created"); + + class IndMemRemPass : public ModulePass { + + public: + IndMemRemPass(); + virtual bool runOnModule(Module &M); + }; + RegisterOpt X("indmemrem", "Indirect Malloc and Free Removal"); + } // end anonymous namespace + + + IndMemRemPass::IndMemRemPass() + { + } + + bool IndMemRemPass::runOnModule(Module &M) { + //in Theory, all direct calls of malloc and free should be promoted + //to intrinsics. Therefor, this goes through and finds where the + //address of free or malloc are taken and replaces those with bounce + //functions, ensuring that all malloc and free that might happen + //happens through intrinsics. + bool changed = false; + if (Function* F = M.getNamedFunction("free")) { + assert(F->isExternal() && "free not external?"); + if (F->getNumUses()) { + Function* FN = new Function(F->getFunctionType(), + GlobalValue::LinkOnceLinkage, + "free_llvm_bounce", &M); + BasicBlock* bb = new BasicBlock("entry",FN); + Instruction* R = new ReturnInst(bb); + new FreeInst(FN->arg_begin(), R); + ++NumBounce; + NumBounceSites += F->getNumUses(); + F->replaceAllUsesWith(FN); + changed = true; + } + } + if (Function* F = M.getNamedFunction("malloc")) { + assert(F->isExternal() && "malloc not external?"); + if (F->getNumUses()) { + Function* FN = new Function(F->getFunctionType(), + GlobalValue::LinkOnceLinkage, + "malloc_llvm_bounce", &M); + BasicBlock* bb = new BasicBlock("entry",FN); + Instruction* c = new CastInst(FN->arg_begin(), Type::UIntTy, "c", bb); + Instruction* a = new MallocInst(Type::SByteTy, c, "m", bb); + Instruction* R = new ReturnInst(a, bb); + ++NumBounce; + NumBounceSites += F->getNumUses(); + F->replaceAllUsesWith(FN); + changed = true; + } + } + return changed; + } + + ModulePass *llvm::createIndMemRemPass() { + return new IndMemRemPass(); + } From alenhar2 at cs.uiuc.edu Mon Apr 10 14:26:27 2006 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Mon, 10 Apr 2006 14:26:27 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Transforms/IPO.h LinkAllPasses.h Message-ID: <200604101926.OAA27042@apoc.cs.uiuc.edu> Changes in directory llvm/include/llvm/Transforms: IPO.h updated: 1.44 -> 1.45 LinkAllPasses.h updated: 1.29 -> 1.30 --- Log message: Add a simple pass to make sure that all (non-library) calls to malloc and free are visible to analysis as intrinsics. That is, make sure someone doesn't pass free around by address in some struct (as happens in say 176.gcc). This doesn't get rid of any indirect calls, just ensure calls to free and malloc are always direct. --- Diffs of the changes: (+6 -1) IPO.h | 5 +++++ LinkAllPasses.h | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) Index: llvm/include/llvm/Transforms/IPO.h diff -u llvm/include/llvm/Transforms/IPO.h:1.44 llvm/include/llvm/Transforms/IPO.h:1.45 --- llvm/include/llvm/Transforms/IPO.h:1.44 Tue Oct 18 01:28:16 2005 +++ llvm/include/llvm/Transforms/IPO.h Mon Apr 10 14:26:09 2006 @@ -169,6 +169,11 @@ // specific well-known (library) functions. ModulePass *createSimplifyLibCallsPass(); + +// createIndMemRemPass - This pass removes potential indirect calls of +// malloc and free +ModulePass *createIndMemRemPass(); + } // End llvm namespace #endif Index: llvm/include/llvm/Transforms/LinkAllPasses.h diff -u llvm/include/llvm/Transforms/LinkAllPasses.h:1.29 llvm/include/llvm/Transforms/LinkAllPasses.h:1.30 --- llvm/include/llvm/Transforms/LinkAllPasses.h:1.29 Wed Feb 22 10:23:43 2006 +++ llvm/include/llvm/Transforms/LinkAllPasses.h Mon Apr 10 14:26:09 2006 @@ -107,7 +107,7 @@ (void) llvm::createCondPropagationPass(); (void) llvm::createNullProfilerRSPass(); (void) llvm::createRSProfilingPass(); - + (void) llvm::createIndMemRemPass(); } } ForcePassLinking; } From evan.cheng at apple.com Mon Apr 10 16:10:12 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 10 Apr 2006 16:10:12 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/IntrinsicsX86.td Message-ID: <200604102110.QAA20103@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm: IntrinsicsX86.td updated: 1.13 -> 1.14 --- Log message: __builtin_ia32_loadup{s|d}, __builtin_ia32_storeup{s|d} --- Diffs of the changes: (+15 -1) IntrinsicsX86.td | 16 +++++++++++++++- 1 files changed, 15 insertions(+), 1 deletion(-) Index: llvm/include/llvm/IntrinsicsX86.td diff -u llvm/include/llvm/IntrinsicsX86.td:1.13 llvm/include/llvm/IntrinsicsX86.td:1.14 --- llvm/include/llvm/IntrinsicsX86.td:1.13 Fri Apr 7 19:47:01 2006 +++ llvm/include/llvm/IntrinsicsX86.td Mon Apr 10 16:09:59 2006 @@ -133,7 +133,8 @@ // SIMD store ops let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse_storeu_ps : GCCBuiltin<"__builtin_ia32_storeups">, - Intrinsic<[llvm_ptr_ty, llvm_v4f32_ty], [IntrWriteMem]>; + Intrinsic<[llvm_void_ty, llvm_ptr_ty, + llvm_v4f32_ty], [IntrWriteMem]>; } // Cacheability support ops @@ -267,6 +268,19 @@ llvm_int_ty], [InstrNoMem]>; } +// SIMD load ops +let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". + def int_x86_sse2_loadu_pd : GCCBuiltin<"__builtin_ia32_loadupd">, + Intrinsic<[llvm_v2f64_ty, llvm_ptr_ty], [IntrReadMem]>; +} + +// SIMD store ops +let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". + def int_x86_sse2_storeu_pd : GCCBuiltin<"__builtin_ia32_storeupd">, + Intrinsic<[llvm_void_ty, llvm_ptr_ty, + llvm_v2f64_ty], [IntrWriteMem]>; +} + // Misc. let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse2_packsswb_128 : GCCBuiltin<"__builtin_ia32_packsswb128">, From evan.cheng at apple.com Mon Apr 10 16:11:19 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 10 Apr 2006 16:11:19 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td Message-ID: <200604102111.QAA20115@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrSSE.td updated: 1.69 -> 1.70 --- Log message: movups / movupd --- Diffs of the changes: (+10 -6) X86InstrSSE.td | 16 ++++++++++------ 1 files changed, 10 insertions(+), 6 deletions(-) Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.69 llvm/lib/Target/X86/X86InstrSSE.td:1.70 --- llvm/lib/Target/X86/X86InstrSSE.td:1.69 Mon Apr 10 02:23:14 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Mon Apr 10 16:11:06 2006 @@ -722,16 +722,20 @@ def MOVUPSrr : PSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src), "movups {$src, $dst|$dst, $src}", []>; -def MOVUPSrm : PSI<0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src), - "movups {$src, $dst|$dst, $src}", []>; -def MOVUPSmr : PSI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src), - "movups {$src, $dst|$dst, $src}", []>; +def MOVUPSrm : PDI<0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src), + "movups {$src, $dst|$dst, $src}", + [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>; +def MOVUPSmr : PDI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src), + "movups {$src, $dst|$dst, $src}", + [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>; def MOVUPDrr : PDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src), "movupd {$src, $dst|$dst, $src}", []>; def MOVUPDrm : PDI<0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src), - "movupd {$src, $dst|$dst, $src}", []>; + "movupd {$src, $dst|$dst, $src}", + [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>; def MOVUPDmr : PDI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src), - "movupd {$src, $dst|$dst, $src}", []>; + "movupd {$src, $dst|$dst, $src}", + [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>; let isTwoAddress = 1 in { def MOVLPSrm : PSI<0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2), From evan.cheng at apple.com Mon Apr 10 16:41:52 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 10 Apr 2006 16:41:52 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/README.txt Message-ID: <200604102141.QAA20297@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: README.txt updated: 1.82 -> 1.83 --- Log message: Correct an entry --- Diffs of the changes: (+2 -2) README.txt | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/Target/X86/README.txt diff -u llvm/lib/Target/X86/README.txt:1.82 llvm/lib/Target/X86/README.txt:1.83 --- llvm/lib/Target/X86/README.txt:1.82 Mon Apr 10 02:22:03 2006 +++ llvm/lib/Target/X86/README.txt Mon Apr 10 16:41:39 2006 @@ -770,8 +770,8 @@ #include -void test(__m128 *res, __m128 *A) { - *res = _mm_shuffle_ps(*A, *A, 0xF0); +void test(__m128 *res, __m128 *A, __m128 *B) { + *res = _mm_shuffle_ps(*A, *B, 0xF0); } We should emit From evan.cheng at apple.com Mon Apr 10 16:42:32 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 10 Apr 2006 16:42:32 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td Message-ID: <200604102142.QAA20320@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrSSE.td updated: 1.70 -> 1.71 --- Log message: Added some missing shuffle patterns. --- Diffs of the changes: (+22 -5) X86InstrSSE.td | 27 ++++++++++++++++++++++----- 1 files changed, 22 insertions(+), 5 deletions(-) Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.70 llvm/lib/Target/X86/X86InstrSSE.td:1.71 --- llvm/lib/Target/X86/X86InstrSSE.td:1.70 Mon Apr 10 16:11:06 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Mon Apr 10 16:42:19 2006 @@ -1365,7 +1365,7 @@ (ops VR128:$dst, i128mem:$src1, i8imm:$src2), "pshufhw {$src2, $src1, $dst|$dst, $src1, $src2}", [(set VR128:$dst, (v8i16 (vector_shuffle - (bc_v8i16 (loadv2i64 addr:$src1)), (undef), + (load addr:$src1), (undef), PSHUFHW_shuffle_mask:$src2)))]>, XS, Requires<[HasSSE2]>; @@ -1381,7 +1381,7 @@ (ops VR128:$dst, i128mem:$src1, i32i8imm:$src2), "pshuflw {$src2, $src1, $dst|$dst, $src1, $src2}", [(set VR128:$dst, (v8i16 (vector_shuffle - (bc_v8i16 (loadv2i64 addr:$src1)), (undef), + (load addr:$src1), (undef), PSHUFLW_shuffle_mask:$src2)))]>, XD, Requires<[HasSSE2]>; @@ -1823,11 +1823,28 @@ (v4i32 (SHUFPSrm VR128:$src1, addr:$src2, SHUFP_int_shuffle_mask:$sm))>, Requires<[HasSSE2]>; -// Shuffle v4f32 with PSHUF* if others do not match. +// Special pshuf* cases: folding (bit_convert (loadv2i64 addr)). +def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (loadv2i64 addr:$src1)), (undef), + PSHUFD_shuffle_mask:$src2)), + (PSHUFDmi addr:$src1, PSHUFD_shuffle_mask:$src2)>, + Requires<[HasSSE2]>; +def : Pat<(v8i16 (vector_shuffle (bc_v8i16 (loadv2i64 addr:$src1)), (undef), + PSHUFHW_shuffle_mask:$src2)), + (PSHUFHWmi addr:$src1, PSHUFHW_shuffle_mask:$src2)>, + Requires<[HasSSE2]>; +def : Pat<(v8i16 (vector_shuffle (bc_v8i16 (loadv2i64 addr:$src1)), (undef), + PSHUFLW_shuffle_mask:$src2)), + (PSHUFLWmi addr:$src1, PSHUFHW_shuffle_mask:$src2)>, + Requires<[HasSSE2]>; + + +// Special SHUFPSrr case: looks like a PSHUFD, like make both operands src1. +// FIXME: when we want non two-address code, then we should use PSHUFD! def : Pat<(vector_shuffle (v4f32 VR128:$src1), (undef), PSHUFD_fp_shuffle_mask:$sm), - (v4f32 (PSHUFDri VR128:$src1, PSHUFD_fp_shuffle_mask:$sm))>, - Requires<[HasSSE2]>; + (v4f32 (SHUFPSrr VR128:$src1, VR128:$src1, PSHUFD_fp_shuffle_mask:$sm))>, + Requires<[HasSSE1]>; +// Shuffle v4f32 with PSHUF* if others do not match. def : Pat<(vector_shuffle (loadv4f32 addr:$src1), (undef), PSHUFD_fp_shuffle_mask:$sm), (v4f32 (PSHUFDmi addr:$src1, PSHUFD_fp_shuffle_mask:$sm))>, From evan.cheng at apple.com Mon Apr 10 16:43:10 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 10 Apr 2006 16:43:10 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/README.txt Message-ID: <200604102143.QAA20453@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: README.txt updated: 1.83 -> 1.84 --- Log message: Remove an entry that is now done. --- Diffs of the changes: (+0 -13) README.txt | 13 ------------- 1 files changed, 13 deletions(-) Index: llvm/lib/Target/X86/README.txt diff -u llvm/lib/Target/X86/README.txt:1.83 llvm/lib/Target/X86/README.txt:1.84 --- llvm/lib/Target/X86/README.txt:1.83 Mon Apr 10 16:41:39 2006 +++ llvm/lib/Target/X86/README.txt Mon Apr 10 16:42:57 2006 @@ -768,19 +768,6 @@ //===---------------------------------------------------------------------===// -#include - -void test(__m128 *res, __m128 *A, __m128 *B) { - *res = _mm_shuffle_ps(*A, *B, 0xF0); -} - -We should emit - shufps $240, (%eax), %xmm0 -instead of - pshufd $240, (%eax), %xmm0 - -//===---------------------------------------------------------------------===// - X86RegisterInfo::copyRegToReg() returns X86::MOVAPSrr for VR128. Is it possible to choose between movaps, movapd, and movdqa based on types of source and destination? From brukman at cs.uiuc.edu Mon Apr 10 16:43:17 2006 From: brukman at cs.uiuc.edu (Misha Brukman) Date: Mon, 10 Apr 2006 16:43:17 -0500 Subject: [llvm-commits] CVS: llvm/docs/HowToReleaseLLVM.html Message-ID: <200604102143.QAA20464@zion.cs.uiuc.edu> Changes in directory llvm/docs: HowToReleaseLLVM.html updated: 1.2 -> 1.3 --- Log message: * Remove duplicated table of contents for a section and at the top level * Fix relative links within the file * Add tags around command names and literal file names and directories --- Diffs of the changes: (+15 -26) HowToReleaseLLVM.html | 41 +++++++++++++++-------------------------- 1 files changed, 15 insertions(+), 26 deletions(-) Index: llvm/docs/HowToReleaseLLVM.html diff -u llvm/docs/HowToReleaseLLVM.html:1.2 llvm/docs/HowToReleaseLLVM.html:1.3 --- llvm/docs/HowToReleaseLLVM.html:1.2 Fri Mar 24 00:42:09 2006 +++ llvm/docs/HowToReleaseLLVM.html Mon Apr 10 16:43:05 2006 @@ -11,18 +11,7 @@

NOTE: THIS DOCUMENT IS A WORK IN PROGRESS!

  1. Introduction
    2. -
  2. Release Process -
      -
    1. Overview
      2. -
    2. Merge Branches
      3. -
    3. Build LLVM
      4. -
    4. Run 'make check'
      5. -
    5. Run LLVM Test Suite
      6. -
    6. make LibDeps.txt
      7. -
    7. cvs tag
      8. -
    8. make dist
      9. -
    9. Release
      10. -
    3. +
  3. Release Process

Written by Reid Spencer

@@ -48,14 +37,14 @@
Process Overview
    -
  1. Merge Branches
    2. -
  2. Build LLVM
    3. -
  3. Run 'make check'
    4. -
  4. Run LLVM Test Suite
    5. -
  5. make LibDeps.txt
    6. -
  6. cvs tag
    7. -
  7. make dist
    8. -
  8. release
    9. +
  9. Merge Branches
    10. +
  10. Build LLVM
    11. +
  11. Run 'make check'
    12. +
  12. Run LLVM Test Suite
    13. +
  13. make LibDeps.txt
    14. +
  14. cvs tag
    15. +
  15. make dist
    16. +
  16. release
@@ -74,8 +63,8 @@
Run 'make check'
-

Run "make check" and ensure there are no unexpected failures. If there - are, resolve the failures and go back to step 2.

+

Run make check and ensure there are no unexpected failures. If + there are, resolve the failures and go back to step 2.

@@ -88,9 +77,9 @@
Make LibDeps.txt
-

Rebuild the LibDeps.txt target in utils/llvm-config. This makes sure that - the llvm-config utility remains relevant for the release, reflecting any - changes in the library dependencies.

+

Rebuild the LibDeps.txt target in utils/llvm-config. This + makes sure that the llvm-config utility remains relevant for the + release, reflecting any changes in the library dependencies.

@@ -122,7 +111,7 @@ Reid Spencer
The LLVM Compiler Infrastructure
- Last modified: $Date: 2006/03/24 06:42:09 $ + Last modified: $Date: 2006/04/10 21:43:05 $ From lattner at cs.uiuc.edu Mon Apr 10 16:51:16 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 10 Apr 2006 16:51:16 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/README.txt Message-ID: <200604102151.QAA20582@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: README.txt updated: 1.84 -> 1.85 --- Log message: add a note --- Diffs of the changes: (+23 -0) README.txt | 23 +++++++++++++++++++++++ 1 files changed, 23 insertions(+) Index: llvm/lib/Target/X86/README.txt diff -u llvm/lib/Target/X86/README.txt:1.84 llvm/lib/Target/X86/README.txt:1.85 --- llvm/lib/Target/X86/README.txt:1.84 Mon Apr 10 16:42:57 2006 +++ llvm/lib/Target/X86/README.txt Mon Apr 10 16:51:03 2006 @@ -675,6 +675,29 @@ //===---------------------------------------------------------------------===// +Better codegen for: + +void f(float a, float b, vector float * out) { *out = (vector float){ a, 0.0, 0.0, b}; } +void f(float a, float b, vector float * out) { *out = (vector float){ a, b, 0.0, 0}; } + +For the later we generate: + +_f: + pxor %xmm0, %xmm0 + movss 8(%esp), %xmm1 + movaps %xmm0, %xmm2 + unpcklps %xmm1, %xmm2 + movss 4(%esp), %xmm1 + unpcklps %xmm0, %xmm1 + unpcklps %xmm2, %xmm1 + movl 12(%esp), %eax + movaps %xmm1, (%eax) + ret + +This seems like it should use shufps, one for each of a & b. + +//===---------------------------------------------------------------------===// + Adding to the list of cmp / test poor codegen issues: int test(__m128 *A, __m128 *B) { From lattner at cs.uiuc.edu Mon Apr 10 17:02:51 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 10 Apr 2006 17:02:51 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Intrinsics.td IntrinsicsPowerPC.td IntrinsicsX86.td Message-ID: <200604102202.RAA20751@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm: Intrinsics.td updated: 1.32 -> 1.33 IntrinsicsPowerPC.td updated: 1.23 -> 1.24 IntrinsicsX86.td updated: 1.14 -> 1.15 --- Log message: Fix a typo: Instr* -> Intr* --- Diffs of the changes: (+170 -170) Intrinsics.td | 26 +++---- IntrinsicsPowerPC.td | 166 +++++++++++++++++++++++++-------------------------- IntrinsicsX86.td | 148 ++++++++++++++++++++++----------------------- 3 files changed, 170 insertions(+), 170 deletions(-) Index: llvm/include/llvm/Intrinsics.td diff -u llvm/include/llvm/Intrinsics.td:1.32 llvm/include/llvm/Intrinsics.td:1.33 --- llvm/include/llvm/Intrinsics.td:1.32 Tue Apr 4 16:48:31 2006 +++ llvm/include/llvm/Intrinsics.td Mon Apr 10 17:02:38 2006 @@ -24,24 +24,24 @@ // if correct) to the least aggressive. If no property is set, the worst case // is assumed (IntrWriteMem). -// InstrNoMem - The intrinsic does not access memory or have any other side +// IntrNoMem - The intrinsic does not access memory or have any other side // effects. It may be CSE'd deleted if dead, etc. -def InstrNoMem : IntrinsicProperty; +def IntrNoMem : IntrinsicProperty; -// InstrReadArgMem - This intrinsic reads only from memory that one of its +// IntrReadArgMem - This intrinsic reads only from memory that one of its // arguments points to, but may read an unspecified amount. -def InstrReadArgMem : IntrinsicProperty; +def IntrReadArgMem : IntrinsicProperty; // IntrReadMem - This intrinsic reads from unspecified memory, so it cannot be // moved across stores. However, it can be reordered otherwise and can be // deleted if dead. def IntrReadMem : IntrinsicProperty; -// InstrWriteArgMem - This intrinsic reads and writes only from memory that one +// IntrWriteArgMem - This intrinsic reads and writes only from memory that one // of its arguments points to, but may access an unspecified amount. It has no // other side effects. This may only be used if the intrinsic doesn't "capture" // the argument pointer (e.g. storing it someplace). -def InstrWriteArgMem : IntrinsicProperty; +def IntrWriteArgMem : IntrinsicProperty; // IntrWriteMem - This intrinsic may read or modify unspecified memory or has // other side effects. It cannot be modified by the optimizer. This is the @@ -130,14 +130,14 @@ // def int_gcroot : Intrinsic<[llvm_void_ty, llvm_ptrptr_ty, llvm_ptr_ty]>; def int_gcread : Intrinsic<[llvm_ptr_ty, llvm_ptr_ty, llvm_ptrptr_ty], - [InstrReadArgMem]>; + [IntrReadArgMem]>; def int_gcwrite : Intrinsic<[llvm_void_ty, llvm_ptr_ty, llvm_ptr_ty, - llvm_ptrptr_ty], [InstrWriteArgMem]>; + llvm_ptrptr_ty], [IntrWriteArgMem]>; //===--------------------- Code Generator Intrinsics ----------------------===// // -def int_returnaddress : Intrinsic<[llvm_ptr_ty, llvm_uint_ty], [InstrNoMem]>; -def int_frameaddress : Intrinsic<[llvm_ptr_ty, llvm_uint_ty], [InstrNoMem]>; +def int_returnaddress : Intrinsic<[llvm_ptr_ty, llvm_uint_ty], [IntrNoMem]>; +def int_frameaddress : Intrinsic<[llvm_ptr_ty, llvm_uint_ty], [IntrNoMem]>; def int_stacksave : Intrinsic<[llvm_ptr_ty], [IntrReadMem]>; def int_stackrestore : Intrinsic<[llvm_void_ty, llvm_ptr_ty]>; def int_prefetch : Intrinsic<[llvm_void_ty, llvm_ptr_ty, @@ -149,7 +149,7 @@ //===------------------- Standard C Library Intrinsics --------------------===// // -let Properties = [InstrWriteArgMem] in { +let Properties = [IntrWriteArgMem] in { def int_memcpy_i32 : Intrinsic<[llvm_void_ty, llvm_ptr_ty, llvm_ptr_ty, llvm_uint_ty, llvm_uint_ty]>; def int_memcpy_i64 : Intrinsic<[llvm_void_ty, llvm_ptr_ty, llvm_ptr_ty, @@ -164,7 +164,7 @@ llvm_ulong_ty, llvm_uint_ty]>; } -let Properties = [InstrNoMem] in { +let Properties = [IntrNoMem] in { def int_isunordered_f32 : Intrinsic<[llvm_bool_ty, llvm_float_ty, llvm_float_ty]>; def int_isunordered_f64 : Intrinsic<[llvm_bool_ty, @@ -183,7 +183,7 @@ // // None of these intrinsics accesses memory at all. -let Properties = [InstrNoMem] in { +let Properties = [IntrNoMem] in { def int_bswap_i16 : Intrinsic<[llvm_ushort_ty, llvm_ushort_ty]>; def int_bswap_i32 : Intrinsic<[llvm_uint_ty, llvm_uint_ty]>; def int_bswap_i64 : Intrinsic<[llvm_ulong_ty, llvm_ulong_ty]>; Index: llvm/include/llvm/IntrinsicsPowerPC.td diff -u llvm/include/llvm/IntrinsicsPowerPC.td:1.23 llvm/include/llvm/IntrinsicsPowerPC.td:1.24 --- llvm/include/llvm/IntrinsicsPowerPC.td:1.23 Thu Apr 6 16:12:48 2006 +++ llvm/include/llvm/IntrinsicsPowerPC.td Mon Apr 10 17:02:38 2006 @@ -31,35 +31,35 @@ /// vector and returns one. These intrinsics have no side effects. class PowerPC_Vec_FF_Intrinsic : PowerPC_Vec_Intrinsic; + [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>; /// PowerPC_Vec_FFF_Intrinsic - A PowerPC intrinsic that takes two v4f32 /// vectors and returns one. These intrinsics have no side effects. class PowerPC_Vec_FFF_Intrinsic : PowerPC_Vec_Intrinsic; + [IntrNoMem]>; /// PowerPC_Vec_BBB_Intrinsic - A PowerPC intrinsic that takes two v16f8 /// vectors and returns one. These intrinsics have no side effects. class PowerPC_Vec_BBB_Intrinsic : PowerPC_Vec_Intrinsic; + [IntrNoMem]>; /// PowerPC_Vec_HHH_Intrinsic - A PowerPC intrinsic that takes two v8i16 /// vectors and returns one. These intrinsics have no side effects. class PowerPC_Vec_HHH_Intrinsic : PowerPC_Vec_Intrinsic; + [IntrNoMem]>; /// PowerPC_Vec_WWW_Intrinsic - A PowerPC intrinsic that takes two v4i32 /// vectors and returns one. These intrinsics have no side effects. class PowerPC_Vec_WWW_Intrinsic : PowerPC_Vec_Intrinsic; + [IntrNoMem]>; //===----------------------------------------------------------------------===// @@ -125,90 +125,90 @@ // Comparisons setting a vector. def int_ppc_altivec_vcmpbfp : GCCBuiltin<"__builtin_altivec_vcmpbfp">, Intrinsic<[llvm_v4i32_ty, llvm_v4f32_ty, llvm_v4f32_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_ppc_altivec_vcmpeqfp : GCCBuiltin<"__builtin_altivec_vcmpeqfp">, Intrinsic<[llvm_v4i32_ty, llvm_v4f32_ty, llvm_v4f32_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_ppc_altivec_vcmpgefp : GCCBuiltin<"__builtin_altivec_vcmpgefp">, Intrinsic<[llvm_v4i32_ty, llvm_v4f32_ty, llvm_v4f32_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_ppc_altivec_vcmpgtfp : GCCBuiltin<"__builtin_altivec_vcmpgtfp">, Intrinsic<[llvm_v4i32_ty, llvm_v4f32_ty, llvm_v4f32_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_ppc_altivec_vcmpequw : GCCBuiltin<"__builtin_altivec_vcmpequw">, Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_ppc_altivec_vcmpgtsw : GCCBuiltin<"__builtin_altivec_vcmpgtsw">, Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_ppc_altivec_vcmpgtuw : GCCBuiltin<"__builtin_altivec_vcmpgtuw">, Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_ppc_altivec_vcmpequh : GCCBuiltin<"__builtin_altivec_vcmpequh">, Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_ppc_altivec_vcmpgtsh : GCCBuiltin<"__builtin_altivec_vcmpgtsh">, Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_ppc_altivec_vcmpgtuh : GCCBuiltin<"__builtin_altivec_vcmpgtuh">, Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_ppc_altivec_vcmpequb : GCCBuiltin<"__builtin_altivec_vcmpequb">, Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_ppc_altivec_vcmpgtsb : GCCBuiltin<"__builtin_altivec_vcmpgtsb">, Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_ppc_altivec_vcmpgtub : GCCBuiltin<"__builtin_altivec_vcmpgtub">, Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty], - [InstrNoMem]>; + [IntrNoMem]>; // Predicate Comparisons. The first operand specifies interpretation of CR6. def int_ppc_altivec_vcmpbfp_p : GCCBuiltin<"__builtin_altivec_vcmpbfp_p">, Intrinsic<[llvm_int_ty, llvm_int_ty, llvm_v4f32_ty,llvm_v4f32_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_ppc_altivec_vcmpeqfp_p : GCCBuiltin<"__builtin_altivec_vcmpeqfp_p">, Intrinsic<[llvm_int_ty, llvm_int_ty, llvm_v4f32_ty,llvm_v4f32_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_ppc_altivec_vcmpgefp_p : GCCBuiltin<"__builtin_altivec_vcmpgefp_p">, Intrinsic<[llvm_int_ty, llvm_int_ty, llvm_v4f32_ty,llvm_v4f32_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_ppc_altivec_vcmpgtfp_p : GCCBuiltin<"__builtin_altivec_vcmpgtfp_p">, Intrinsic<[llvm_int_ty, llvm_int_ty, llvm_v4f32_ty,llvm_v4f32_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_ppc_altivec_vcmpequw_p : GCCBuiltin<"__builtin_altivec_vcmpequw_p">, Intrinsic<[llvm_int_ty, llvm_int_ty, llvm_v4i32_ty,llvm_v4i32_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_ppc_altivec_vcmpgtsw_p : GCCBuiltin<"__builtin_altivec_vcmpgtsw_p">, Intrinsic<[llvm_int_ty, llvm_int_ty, llvm_v4i32_ty,llvm_v4i32_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_ppc_altivec_vcmpgtuw_p : GCCBuiltin<"__builtin_altivec_vcmpgtuw_p">, Intrinsic<[llvm_int_ty, llvm_int_ty, llvm_v4i32_ty,llvm_v4i32_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_ppc_altivec_vcmpequh_p : GCCBuiltin<"__builtin_altivec_vcmpequh_p">, Intrinsic<[llvm_int_ty, llvm_int_ty, llvm_v8i16_ty,llvm_v8i16_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_ppc_altivec_vcmpgtsh_p : GCCBuiltin<"__builtin_altivec_vcmpgtsh_p">, Intrinsic<[llvm_int_ty, llvm_int_ty, llvm_v8i16_ty,llvm_v8i16_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_ppc_altivec_vcmpgtuh_p : GCCBuiltin<"__builtin_altivec_vcmpgtuh_p">, Intrinsic<[llvm_int_ty, llvm_int_ty, llvm_v8i16_ty,llvm_v8i16_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_ppc_altivec_vcmpequb_p : GCCBuiltin<"__builtin_altivec_vcmpequb_p">, Intrinsic<[llvm_int_ty, llvm_int_ty, llvm_v16i8_ty,llvm_v16i8_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_ppc_altivec_vcmpgtsb_p : GCCBuiltin<"__builtin_altivec_vcmpgtsb_p">, Intrinsic<[llvm_int_ty, llvm_int_ty, llvm_v16i8_ty,llvm_v16i8_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_ppc_altivec_vcmpgtub_p : GCCBuiltin<"__builtin_altivec_vcmpgtub_p">, Intrinsic<[llvm_int_ty, llvm_int_ty, llvm_v16i8_ty,llvm_v16i8_ty], - [InstrNoMem]>; + [IntrNoMem]>; } // Vector average. @@ -259,149 +259,149 @@ // Saturating multiply-adds. def int_ppc_altivec_vmhaddshs : GCCBuiltin<"__builtin_altivec_vmhaddshs">, Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, - llvm_v8i16_ty, llvm_v8i16_ty], [InstrNoMem]>; + llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; def int_ppc_altivec_vmhraddshs : GCCBuiltin<"__builtin_altivec_vmhraddshs">, Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, - llvm_v8i16_ty, llvm_v8i16_ty], [InstrNoMem]>; + llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; def int_ppc_altivec_vmaddfp : GCCBuiltin<"__builtin_altivec_vmaddfp">, Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, - llvm_v4f32_ty, llvm_v4f32_ty], [InstrNoMem]>; + llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>; def int_ppc_altivec_vnmsubfp : GCCBuiltin<"__builtin_altivec_vnmsubfp">, Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, - llvm_v4f32_ty, llvm_v4f32_ty], [InstrNoMem]>; + llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>; - // Vector Multiply Sum Instructions. + // Vector Multiply Sum Intructions. def int_ppc_altivec_vmsummbm : GCCBuiltin<"__builtin_altivec_vmsummbm">, Intrinsic<[llvm_v4i32_ty, llvm_v16i8_ty, llvm_v16i8_ty, - llvm_v4i32_ty], [InstrNoMem]>; + llvm_v4i32_ty], [IntrNoMem]>; def int_ppc_altivec_vmsumshm : GCCBuiltin<"__builtin_altivec_vmsumshm">, Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty, - llvm_v4i32_ty], [InstrNoMem]>; + llvm_v4i32_ty], [IntrNoMem]>; def int_ppc_altivec_vmsumshs : GCCBuiltin<"__builtin_altivec_vmsumshs">, Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty, - llvm_v4i32_ty], [InstrNoMem]>; + llvm_v4i32_ty], [IntrNoMem]>; def int_ppc_altivec_vmsumubm : GCCBuiltin<"__builtin_altivec_vmsumubm">, Intrinsic<[llvm_v4i32_ty, llvm_v16i8_ty, llvm_v16i8_ty, - llvm_v4i32_ty], [InstrNoMem]>; + llvm_v4i32_ty], [IntrNoMem]>; def int_ppc_altivec_vmsumuhm : GCCBuiltin<"__builtin_altivec_vmsumuhm">, Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty, - llvm_v4i32_ty], [InstrNoMem]>; + llvm_v4i32_ty], [IntrNoMem]>; def int_ppc_altivec_vmsumuhs : GCCBuiltin<"__builtin_altivec_vmsumuhs">, Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty, - llvm_v4i32_ty], [InstrNoMem]>; + llvm_v4i32_ty], [IntrNoMem]>; - // Vector Multiply Instructions. + // Vector Multiply Intructions. def int_ppc_altivec_vmulesb : GCCBuiltin<"__builtin_altivec_vmulesb">, Intrinsic<[llvm_v8i16_ty, llvm_v16i8_ty, llvm_v16i8_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_ppc_altivec_vmulesh : GCCBuiltin<"__builtin_altivec_vmulesh">, Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_ppc_altivec_vmuleub : GCCBuiltin<"__builtin_altivec_vmuleub">, Intrinsic<[llvm_v8i16_ty, llvm_v16i8_ty, llvm_v16i8_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_ppc_altivec_vmuleuh : GCCBuiltin<"__builtin_altivec_vmuleuh">, Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_ppc_altivec_vmulosb : GCCBuiltin<"__builtin_altivec_vmulosb">, Intrinsic<[llvm_v8i16_ty, llvm_v16i8_ty, llvm_v16i8_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_ppc_altivec_vmulosh : GCCBuiltin<"__builtin_altivec_vmulosh">, Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_ppc_altivec_vmuloub : GCCBuiltin<"__builtin_altivec_vmuloub">, Intrinsic<[llvm_v8i16_ty, llvm_v16i8_ty, llvm_v16i8_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_ppc_altivec_vmulouh : GCCBuiltin<"__builtin_altivec_vmulouh">, Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty], - [InstrNoMem]>; + [IntrNoMem]>; - // Vector Sum Instructions. + // Vector Sum Intructions. def int_ppc_altivec_vsumsws : GCCBuiltin<"__builtin_altivec_vsumsws">, Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_ppc_altivec_vsum2sws : GCCBuiltin<"__builtin_altivec_vsum2sws">, Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_ppc_altivec_vsum4sbs : GCCBuiltin<"__builtin_altivec_vsum4sbs">, Intrinsic<[llvm_v4i32_ty, llvm_v16i8_ty, llvm_v4i32_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_ppc_altivec_vsum4shs : GCCBuiltin<"__builtin_altivec_vsum4shs">, Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v4i32_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_ppc_altivec_vsum4ubs : GCCBuiltin<"__builtin_altivec_vsum4ubs">, Intrinsic<[llvm_v4i32_ty, llvm_v16i8_ty, llvm_v4i32_ty], - [InstrNoMem]>; + [IntrNoMem]>; // Other multiplies. def int_ppc_altivec_vmladduhm : GCCBuiltin<"__builtin_altivec_vmladduhm">, Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty, - llvm_v8i16_ty], [InstrNoMem]>; + llvm_v8i16_ty], [IntrNoMem]>; // Packs. def int_ppc_altivec_vpkpx : GCCBuiltin<"__builtin_altivec_vpkpx">, Intrinsic<[llvm_v8i16_ty, llvm_v4i32_ty, llvm_v4i32_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_ppc_altivec_vpkshss : GCCBuiltin<"__builtin_altivec_vpkshss">, Intrinsic<[llvm_v16i8_ty, llvm_v8i16_ty, llvm_v8i16_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_ppc_altivec_vpkshus : GCCBuiltin<"__builtin_altivec_vpkshus">, Intrinsic<[llvm_v16i8_ty, llvm_v8i16_ty, llvm_v8i16_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_ppc_altivec_vpkswss : GCCBuiltin<"__builtin_altivec_vpkswss">, Intrinsic<[llvm_v16i8_ty, llvm_v4i32_ty, llvm_v4i32_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_ppc_altivec_vpkswus : GCCBuiltin<"__builtin_altivec_vpkswus">, Intrinsic<[llvm_v8i16_ty, llvm_v4i32_ty, llvm_v4i32_ty], - [InstrNoMem]>; + [IntrNoMem]>; // vpkuhum is lowered to a shuffle. def int_ppc_altivec_vpkuhus : GCCBuiltin<"__builtin_altivec_vpkuhus">, Intrinsic<[llvm_v16i8_ty, llvm_v8i16_ty, llvm_v8i16_ty], - [InstrNoMem]>; + [IntrNoMem]>; // vpkuwum is lowered to a shuffle. def int_ppc_altivec_vpkuwus : GCCBuiltin<"__builtin_altivec_vpkuwus">, Intrinsic<[llvm_v16i8_ty, llvm_v4i32_ty, llvm_v4i32_ty], - [InstrNoMem]>; + [IntrNoMem]>; // Unpacks. def int_ppc_altivec_vupkhpx : GCCBuiltin<"__builtin_altivec_vupkhpx">, - Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty], [InstrNoMem]>; + Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty], [IntrNoMem]>; def int_ppc_altivec_vupkhsb : GCCBuiltin<"__builtin_altivec_vupkhsb">, - Intrinsic<[llvm_v8i16_ty, llvm_v16i8_ty], [InstrNoMem]>; + Intrinsic<[llvm_v8i16_ty, llvm_v16i8_ty], [IntrNoMem]>; def int_ppc_altivec_vupkhsh : GCCBuiltin<"__builtin_altivec_vupkhsh">, - Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty], [InstrNoMem]>; + Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty], [IntrNoMem]>; def int_ppc_altivec_vupklpx : GCCBuiltin<"__builtin_altivec_vupklpx">, - Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty], [InstrNoMem]>; + Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty], [IntrNoMem]>; def int_ppc_altivec_vupklsb : GCCBuiltin<"__builtin_altivec_vupklsb">, - Intrinsic<[llvm_v8i16_ty, llvm_v16i8_ty], [InstrNoMem]>; + Intrinsic<[llvm_v8i16_ty, llvm_v16i8_ty], [IntrNoMem]>; def int_ppc_altivec_vupklsh : GCCBuiltin<"__builtin_altivec_vupklsh">, - Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty], [InstrNoMem]>; + Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty], [IntrNoMem]>; // FP <-> integer conversion. def int_ppc_altivec_vcfsx : GCCBuiltin<"__builtin_altivec_vcfsx">, Intrinsic<[llvm_v4f32_ty, llvm_v4i32_ty, llvm_int_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_ppc_altivec_vcfux : GCCBuiltin<"__builtin_altivec_vcfux">, Intrinsic<[llvm_v4f32_ty, llvm_v4i32_ty, llvm_int_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_ppc_altivec_vctsxs : GCCBuiltin<"__builtin_altivec_vctsxs">, Intrinsic<[llvm_v4i32_ty, llvm_v4f32_ty, llvm_int_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_ppc_altivec_vctuxs : GCCBuiltin<"__builtin_altivec_vctuxs">, Intrinsic<[llvm_v4i32_ty, llvm_v4f32_ty, llvm_int_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_ppc_altivec_vrfim : GCCBuiltin<"__builtin_altivec_vrfim">, - Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty], [InstrNoMem]>; + Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>; def int_ppc_altivec_vrfin : GCCBuiltin<"__builtin_altivec_vrfin">, - Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty], [InstrNoMem]>; + Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>; def int_ppc_altivec_vrfip : GCCBuiltin<"__builtin_altivec_vrfip">, - Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty], [InstrNoMem]>; + Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>; def int_ppc_altivec_vrfiz : GCCBuiltin<"__builtin_altivec_vrfiz">, - Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty], [InstrNoMem]>; + Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>; } def int_ppc_altivec_vsl : PowerPC_Vec_WWW_Intrinsic<"vsl">; @@ -430,16 +430,16 @@ let TargetPrefix = "ppc" in { // All PPC intrinsics start with "llvm.ppc.". // Miscellaneous. def int_ppc_altivec_lvsl : - Intrinsic<[llvm_v16i8_ty, llvm_ptr_ty], [InstrNoMem]>; + Intrinsic<[llvm_v16i8_ty, llvm_ptr_ty], [IntrNoMem]>; def int_ppc_altivec_lvsr : - Intrinsic<[llvm_v16i8_ty, llvm_ptr_ty], [InstrNoMem]>; + Intrinsic<[llvm_v16i8_ty, llvm_ptr_ty], [IntrNoMem]>; def int_ppc_altivec_vperm : GCCBuiltin<"__builtin_altivec_vperm_4si">, Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, - llvm_v4i32_ty, llvm_v16i8_ty], [InstrNoMem]>; + llvm_v4i32_ty, llvm_v16i8_ty], [IntrNoMem]>; def int_ppc_altivec_vsel : GCCBuiltin<"__builtin_altivec_vsel_4si">, Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, - llvm_v4i32_ty, llvm_v4i32_ty], [InstrNoMem]>; + llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>; } def int_ppc_altivec_vexptefp : PowerPC_Vec_FF_Intrinsic<"vexptefp">; Index: llvm/include/llvm/IntrinsicsX86.td diff -u llvm/include/llvm/IntrinsicsX86.td:1.14 llvm/include/llvm/IntrinsicsX86.td:1.15 --- llvm/include/llvm/IntrinsicsX86.td:1.14 Mon Apr 10 16:09:59 2006 +++ llvm/include/llvm/IntrinsicsX86.td Mon Apr 10 17:02:38 2006 @@ -19,109 +19,109 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse_add_ss : GCCBuiltin<"__builtin_ia32_addss">, Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, - llvm_v4f32_ty], [InstrNoMem]>; + llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse_sub_ss : GCCBuiltin<"__builtin_ia32_subss">, Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, - llvm_v4f32_ty], [InstrNoMem]>; + llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse_mul_ss : GCCBuiltin<"__builtin_ia32_mulss">, Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, - llvm_v4f32_ty], [InstrNoMem]>; + llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse_div_ss : GCCBuiltin<"__builtin_ia32_divss">, Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, - llvm_v4f32_ty], [InstrNoMem]>; + llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse_sqrt_ss : GCCBuiltin<"__builtin_ia32_sqrtss">, Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_x86_sse_sqrt_ps : GCCBuiltin<"__builtin_ia32_sqrtps">, Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_x86_sse_rcp_ss : GCCBuiltin<"__builtin_ia32_rcpss">, Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_x86_sse_rcp_ps : GCCBuiltin<"__builtin_ia32_rcpps">, Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_x86_sse_rsqrt_ss : GCCBuiltin<"__builtin_ia32_rsqrtss">, Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_x86_sse_rsqrt_ps : GCCBuiltin<"__builtin_ia32_rsqrtps">, Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_x86_sse_min_ss : GCCBuiltin<"__builtin_ia32_minss">, Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, - llvm_v4f32_ty], [InstrNoMem]>; + llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse_min_ps : GCCBuiltin<"__builtin_ia32_minps">, Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, - llvm_v4f32_ty], [InstrNoMem]>; + llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse_max_ss : GCCBuiltin<"__builtin_ia32_maxss">, Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, - llvm_v4f32_ty], [InstrNoMem]>; + llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse_max_ps : GCCBuiltin<"__builtin_ia32_maxps">, Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, - llvm_v4f32_ty], [InstrNoMem]>; + llvm_v4f32_ty], [IntrNoMem]>; } // Comparison ops let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse_cmp_ss : Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, - llvm_v4f32_ty, llvm_sbyte_ty], [InstrNoMem]>; + llvm_v4f32_ty, llvm_sbyte_ty], [IntrNoMem]>; def int_x86_sse_cmp_ps : Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, - llvm_v4f32_ty, llvm_sbyte_ty], [InstrNoMem]>; + llvm_v4f32_ty, llvm_sbyte_ty], [IntrNoMem]>; def int_x86_sse_comieq_ss : GCCBuiltin<"__builtin_ia32_comieq">, Intrinsic<[llvm_int_ty, llvm_v4f32_ty, - llvm_v4f32_ty], [InstrNoMem]>; + llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse_comilt_ss : GCCBuiltin<"__builtin_ia32_comilt">, Intrinsic<[llvm_int_ty, llvm_v4f32_ty, - llvm_v4f32_ty], [InstrNoMem]>; + llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse_comile_ss : GCCBuiltin<"__builtin_ia32_comile">, Intrinsic<[llvm_int_ty, llvm_v4f32_ty, - llvm_v4f32_ty], [InstrNoMem]>; + llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse_comigt_ss : GCCBuiltin<"__builtin_ia32_comigt">, Intrinsic<[llvm_int_ty, llvm_v4f32_ty, - llvm_v4f32_ty], [InstrNoMem]>; + llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse_comige_ss : GCCBuiltin<"__builtin_ia32_comige">, Intrinsic<[llvm_int_ty, llvm_v4f32_ty, - llvm_v4f32_ty], [InstrNoMem]>; + llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse_comineq_ss : GCCBuiltin<"__builtin_ia32_comineq">, Intrinsic<[llvm_int_ty, llvm_v4f32_ty, - llvm_v4f32_ty], [InstrNoMem]>; + llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse_ucomieq_ss : GCCBuiltin<"__builtin_ia32_ucomieq">, Intrinsic<[llvm_int_ty, llvm_v4f32_ty, - llvm_v4f32_ty], [InstrNoMem]>; + llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse_ucomilt_ss : GCCBuiltin<"__builtin_ia32_ucomilt">, Intrinsic<[llvm_int_ty, llvm_v4f32_ty, - llvm_v4f32_ty], [InstrNoMem]>; + llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse_ucomile_ss : GCCBuiltin<"__builtin_ia32_ucomile">, Intrinsic<[llvm_int_ty, llvm_v4f32_ty, - llvm_v4f32_ty], [InstrNoMem]>; + llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse_ucomigt_ss : GCCBuiltin<"__builtin_ia32_ucomigt">, Intrinsic<[llvm_int_ty, llvm_v4f32_ty, - llvm_v4f32_ty], [InstrNoMem]>; + llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse_ucomige_ss : GCCBuiltin<"__builtin_ia32_ucomige">, Intrinsic<[llvm_int_ty, llvm_v4f32_ty, - llvm_v4f32_ty], [InstrNoMem]>; + llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse_ucomineq_ss : GCCBuiltin<"__builtin_ia32_ucomineq">, Intrinsic<[llvm_int_ty, llvm_v4f32_ty, - llvm_v4f32_ty], [InstrNoMem]>; + llvm_v4f32_ty], [IntrNoMem]>; } // Conversion ops let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse_cvtss2si : GCCBuiltin<"__builtin_ia32_cvtss2si">, - Intrinsic<[llvm_int_ty, llvm_v4f32_ty], [InstrNoMem]>; + Intrinsic<[llvm_int_ty, llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse_cvtps2pi : GCCBuiltin<"__builtin_ia32_cvtps2pi">, - Intrinsic<[llvm_v2i32_ty, llvm_v4i32_ty], [InstrNoMem]>; + Intrinsic<[llvm_v2i32_ty, llvm_v4i32_ty], [IntrNoMem]>; def int_x86_sse_cvttss2si : GCCBuiltin<"__builtin_ia32_cvttss2si">, - Intrinsic<[llvm_int_ty, llvm_v4f32_ty], [InstrNoMem]>; + Intrinsic<[llvm_int_ty, llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse_cvttps2pi : GCCBuiltin<"__builtin_ia32_cvttps2pi">, - Intrinsic<[llvm_v2i32_ty, llvm_v4i32_ty], [InstrNoMem]>; + Intrinsic<[llvm_v2i32_ty, llvm_v4i32_ty], [IntrNoMem]>; def int_x86_sse_cvtsi2ss : GCCBuiltin<"__builtin_ia32_cvtsi2ss">, - Intrinsic<[llvm_v4f32_ty, llvm_int_ty], [InstrNoMem]>; + Intrinsic<[llvm_v4f32_ty, llvm_int_ty], [IntrNoMem]>; def int_x86_sse_cvtpi2ps : GCCBuiltin<"__builtin_ia32_cvtpi2ps">, - Intrinsic<[llvm_v4f32_ty, llvm_v2i32_ty], [InstrNoMem]>; + Intrinsic<[llvm_v4f32_ty, llvm_v2i32_ty], [IntrNoMem]>; } // SIMD load ops @@ -160,7 +160,7 @@ // Misc. let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse_movmsk_ps : GCCBuiltin<"__builtin_ia32_movmskps">, - Intrinsic<[llvm_int_ty, llvm_v4f32_ty], [InstrNoMem]>; + Intrinsic<[llvm_int_ty, llvm_v4f32_ty], [IntrNoMem]>; } //===----------------------------------------------------------------------===// @@ -170,102 +170,102 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse2_add_sd : GCCBuiltin<"__builtin_ia32_addsd">, Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty, - llvm_v2f64_ty], [InstrNoMem]>; + llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_sub_sd : GCCBuiltin<"__builtin_ia32_subsd">, Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty, - llvm_v2f64_ty], [InstrNoMem]>; + llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_mul_sd : GCCBuiltin<"__builtin_ia32_mulsd">, Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty, - llvm_v2f64_ty], [InstrNoMem]>; + llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_div_sd : GCCBuiltin<"__builtin_ia32_divsd">, Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty, - llvm_v2f64_ty], [InstrNoMem]>; + llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_sqrt_sd : GCCBuiltin<"__builtin_ia32_sqrtsd">, Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_x86_sse2_sqrt_pd : GCCBuiltin<"__builtin_ia32_sqrtpd">, Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_x86_sse2_rcp_sd : GCCBuiltin<"__builtin_ia32_rcpsd">, Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_x86_sse2_rcp_pd : GCCBuiltin<"__builtin_ia32_rcppd">, Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_x86_sse2_rsqrt_sd : GCCBuiltin<"__builtin_ia32_rsqrtsd">, Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_x86_sse2_rsqrt_pd : GCCBuiltin<"__builtin_ia32_rsqrtpd">, Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty], - [InstrNoMem]>; + [IntrNoMem]>; def int_x86_sse2_min_sd : GCCBuiltin<"__builtin_ia32_minsd">, Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty, - llvm_v2f64_ty], [InstrNoMem]>; + llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_min_pd : GCCBuiltin<"__builtin_ia32_minpd">, Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty, - llvm_v2f64_ty], [InstrNoMem]>; + llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_max_sd : GCCBuiltin<"__builtin_ia32_maxsd">, Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty, - llvm_v2f64_ty], [InstrNoMem]>; + llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_max_pd : GCCBuiltin<"__builtin_ia32_maxpd">, Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty, - llvm_v2f64_ty], [InstrNoMem]>; + llvm_v2f64_ty], [IntrNoMem]>; } // FP comparison ops let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse2_cmp_sd : Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty, - llvm_v2f64_ty, llvm_sbyte_ty], [InstrNoMem]>; + llvm_v2f64_ty, llvm_sbyte_ty], [IntrNoMem]>; def int_x86_sse2_cmp_pd : Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty, - llvm_v2f64_ty, llvm_sbyte_ty], [InstrNoMem]>; + llvm_v2f64_ty, llvm_sbyte_ty], [IntrNoMem]>; def int_x86_sse2_comieq_sd : GCCBuiltin<"__builtin_ia32_comisdeq">, Intrinsic<[llvm_int_ty, llvm_v2f64_ty, - llvm_v2f64_ty], [InstrNoMem]>; + llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_comilt_sd : GCCBuiltin<"__builtin_ia32_comisdlt">, Intrinsic<[llvm_int_ty, llvm_v2f64_ty, - llvm_v2f64_ty], [InstrNoMem]>; + llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_comile_sd : GCCBuiltin<"__builtin_ia32_comisdle">, Intrinsic<[llvm_int_ty, llvm_v2f64_ty, - llvm_v2f64_ty], [InstrNoMem]>; + llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_comigt_sd : GCCBuiltin<"__builtin_ia32_comisdgt">, Intrinsic<[llvm_int_ty, llvm_v2f64_ty, - llvm_v2f64_ty], [InstrNoMem]>; + llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_comige_sd : GCCBuiltin<"__builtin_ia32_comisdge">, Intrinsic<[llvm_int_ty, llvm_v2f64_ty, - llvm_v2f64_ty], [InstrNoMem]>; + llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_comineq_sd : GCCBuiltin<"__builtin_ia32_comisdneq">, Intrinsic<[llvm_int_ty, llvm_v2f64_ty, - llvm_v2f64_ty], [InstrNoMem]>; + llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_ucomieq_sd : GCCBuiltin<"__builtin_ia32_ucomisdeq">, Intrinsic<[llvm_int_ty, llvm_v2f64_ty, - llvm_v2f64_ty], [InstrNoMem]>; + llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_ucomilt_sd : GCCBuiltin<"__builtin_ia32_ucomisdlt">, Intrinsic<[llvm_int_ty, llvm_v2f64_ty, - llvm_v2f64_ty], [InstrNoMem]>; + llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_ucomile_sd : GCCBuiltin<"__builtin_ia32_ucomisdle">, Intrinsic<[llvm_int_ty, llvm_v2f64_ty, - llvm_v2f64_ty], [InstrNoMem]>; + llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_ucomigt_sd : GCCBuiltin<"__builtin_ia32_ucomisdgt">, Intrinsic<[llvm_int_ty, llvm_v2f64_ty, - llvm_v2f64_ty], [InstrNoMem]>; + llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_ucomige_sd : GCCBuiltin<"__builtin_ia32_ucomisdge">, Intrinsic<[llvm_int_ty, llvm_v2f64_ty, - llvm_v2f64_ty], [InstrNoMem]>; + llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_ucomineq_sd : GCCBuiltin<"__builtin_ia32_ucomisdneq">, Intrinsic<[llvm_int_ty, llvm_v2f64_ty, - llvm_v2f64_ty], [InstrNoMem]>; + llvm_v2f64_ty], [IntrNoMem]>; } // Integer shift ops. let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse2_psll_dq : GCCBuiltin<"__builtin_ia32_pslldqi128">, Intrinsic<[llvm_v2i64_ty, llvm_v2i64_ty, - llvm_int_ty], [InstrNoMem]>; + llvm_int_ty], [IntrNoMem]>; def int_x86_sse2_psrl_dq : GCCBuiltin<"__builtin_ia32_psrldqi128">, Intrinsic<[llvm_v2i64_ty, llvm_v2i64_ty, - llvm_int_ty], [InstrNoMem]>; + llvm_int_ty], [IntrNoMem]>; } // SIMD load ops @@ -285,17 +285,17 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse2_packsswb_128 : GCCBuiltin<"__builtin_ia32_packsswb128">, Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, - llvm_v8i16_ty], [InstrNoMem]>; + llvm_v8i16_ty], [IntrNoMem]>; def int_x86_sse2_packssdw_128 : GCCBuiltin<"__builtin_ia32_packssdw128">, Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, - llvm_v4i32_ty], [InstrNoMem]>; + llvm_v4i32_ty], [IntrNoMem]>; def int_x86_sse2_packuswb_128 : GCCBuiltin<"__builtin_ia32_packuswb128">, Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, - llvm_v8i16_ty], [InstrNoMem]>; + llvm_v8i16_ty], [IntrNoMem]>; def int_x86_sse2_movmskpd : GCCBuiltin<"__builtin_ia32_movmskpd">, - Intrinsic<[llvm_int_ty, llvm_v2f64_ty], [InstrNoMem]>; + Intrinsic<[llvm_int_ty, llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_pmovmskb_128 : GCCBuiltin<"__builtin_ia32_pmovmskb128">, - Intrinsic<[llvm_int_ty, llvm_v16i8_ty], [InstrNoMem]>; + Intrinsic<[llvm_int_ty, llvm_v16i8_ty], [IntrNoMem]>; } //===----------------------------------------------------------------------===// @@ -305,14 +305,14 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse3_hadd_ps : GCCBuiltin<"__builtin_ia32_haddps">, Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, - llvm_v4f32_ty], [InstrNoMem]>; + llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse3_hadd_pd : GCCBuiltin<"__builtin_ia32_haddpd">, Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty, - llvm_v2f64_ty], [InstrNoMem]>; + llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse3_hsub_ps : GCCBuiltin<"__builtin_ia32_hsubps">, Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, - llvm_v4f32_ty], [InstrNoMem]>; + llvm_v4f32_ty], [IntrNoMem]>; def int_x86_sse3_hsub_pd : GCCBuiltin<"__builtin_ia32_hsubpd">, Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty, - llvm_v2f64_ty], [InstrNoMem]>; + llvm_v2f64_ty], [IntrNoMem]>; } From lattner at cs.uiuc.edu Mon Apr 10 17:03:11 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 10 Apr 2006 17:03:11 -0500 Subject: [llvm-commits] CVS: llvm/utils/TableGen/CodeGenTarget.cpp Message-ID: <200604102203.RAA20783@zion.cs.uiuc.edu> Changes in directory llvm/utils/TableGen: CodeGenTarget.cpp updated: 1.62 -> 1.63 --- Log message: Fix a typo: Instr* -> Intr* --- Diffs of the changes: (+3 -3) CodeGenTarget.cpp | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) Index: llvm/utils/TableGen/CodeGenTarget.cpp diff -u llvm/utils/TableGen/CodeGenTarget.cpp:1.62 llvm/utils/TableGen/CodeGenTarget.cpp:1.63 --- llvm/utils/TableGen/CodeGenTarget.cpp:1.62 Mon Mar 27 18:15:00 2006 +++ llvm/utils/TableGen/CodeGenTarget.cpp Mon Apr 10 17:02:59 2006 @@ -439,13 +439,13 @@ assert(Property->isSubClassOf("IntrinsicProperty") && "Expected a property!"); - if (Property->getName() == "InstrNoMem") + if (Property->getName() == "IntrNoMem") ModRef = NoMem; - else if (Property->getName() == "InstrReadArgMem") + else if (Property->getName() == "IntrReadArgMem") ModRef = ReadArgMem; else if (Property->getName() == "IntrReadMem") ModRef = ReadMem; - else if (Property->getName() == "InstrWriteArgMem") + else if (Property->getName() == "IntrWriteArgMem") ModRef = WriteArgMem; else if (Property->getName() == "IntrWriteMem") ModRef = WriteMem; From evan.cheng at apple.com Mon Apr 10 17:35:28 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 10 Apr 2006 17:35:28 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td Message-ID: <200604102235.RAA20878@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrSSE.td updated: 1.71 -> 1.72 --- Log message: Remove some bogus patterns; clean up. --- Diffs of the changes: (+20 -53) X86InstrSSE.td | 73 +++++++++++++++------------------------------------------ 1 files changed, 20 insertions(+), 53 deletions(-) Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.71 llvm/lib/Target/X86/X86InstrSSE.td:1.72 --- llvm/lib/Target/X86/X86InstrSSE.td:1.71 Mon Apr 10 16:42:19 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Mon Apr 10 17:35:16 2006 @@ -128,32 +128,16 @@ return X86::isPSHUFLWMask(N); }], SHUFFLE_get_pshuflw_imm>; -// Only use PSHUF* for v4f32 if SHUFP does not match. -def PSHUFD_fp_shuffle_mask : PatLeaf<(build_vector), [{ - return !X86::isSHUFPMask(N) && - X86::isPSHUFDMask(N); +def SHUFP_unary_shuffle_mask : PatLeaf<(build_vector), [{ + return X86::isPSHUFDMask(N); }], SHUFFLE_get_shuf_imm>; -def PSHUFHW_fp_shuffle_mask : PatLeaf<(build_vector), [{ - return !X86::isSHUFPMask(N) && - X86::isPSHUFHWMask(N); -}], SHUFFLE_get_pshufhw_imm>; - -def PSHUFLW_fp_shuffle_mask : PatLeaf<(build_vector), [{ - return !X86::isSHUFPMask(N) && - X86::isPSHUFLWMask(N); -}], SHUFFLE_get_pshuflw_imm>; - def SHUFP_shuffle_mask : PatLeaf<(build_vector), [{ return X86::isSHUFPMask(N); }], SHUFFLE_get_shuf_imm>; -// Only use SHUFP for v4i32 if PSHUF* do not match. -def SHUFP_int_shuffle_mask : PatLeaf<(build_vector), [{ - return !X86::isPSHUFDMask(N) && - !X86::isPSHUFHWMask(N) && - !X86::isPSHUFLWMask(N) && - X86::isSHUFPMask(N); +def PSHUFD_binary_shuffle_mask : PatLeaf<(build_vector), [{ + return X86::isSHUFPMask(N); }], SHUFFLE_get_shuf_imm>; //===----------------------------------------------------------------------===// @@ -1813,16 +1797,6 @@ (v4f32 (SHUFPSrr VR128:$src, VR128:$src, SSE_splat_mask:$sm))>, Requires<[HasSSE1]>; -// Shuffle v4i32 with SHUFP* if others do not match. -def : Pat<(vector_shuffle (v4i32 VR128:$src1), (v4i32 VR128:$src2), - SHUFP_int_shuffle_mask:$sm), - (v4i32 (SHUFPSrr VR128:$src1, VR128:$src2, - SHUFP_int_shuffle_mask:$sm))>, Requires<[HasSSE2]>; -def : Pat<(vector_shuffle (v4i32 VR128:$src1), (load addr:$src2), - SHUFP_int_shuffle_mask:$sm), - (v4i32 (SHUFPSrm VR128:$src1, addr:$src2, - SHUFP_int_shuffle_mask:$sm))>, Requires<[HasSSE2]>; - // Special pshuf* cases: folding (bit_convert (loadv2i64 addr)). def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (loadv2i64 addr:$src1)), (undef), PSHUFD_shuffle_mask:$src2)), @@ -1838,33 +1812,26 @@ Requires<[HasSSE2]>; -// Special SHUFPSrr case: looks like a PSHUFD, like make both operands src1. -// FIXME: when we want non two-address code, then we should use PSHUFD! +// Special unary SHUFPSrr case. +// FIXME: when we want non two-address code, then we should use PSHUFD? def : Pat<(vector_shuffle (v4f32 VR128:$src1), (undef), - PSHUFD_fp_shuffle_mask:$sm), - (v4f32 (SHUFPSrr VR128:$src1, VR128:$src1, PSHUFD_fp_shuffle_mask:$sm))>, + SHUFP_unary_shuffle_mask:$sm), + (v4f32 (SHUFPSrr VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm))>, Requires<[HasSSE1]>; -// Shuffle v4f32 with PSHUF* if others do not match. +// Unary v4f32 shuffle with PSHUF* in order to fold a load. def : Pat<(vector_shuffle (loadv4f32 addr:$src1), (undef), - PSHUFD_fp_shuffle_mask:$sm), - (v4f32 (PSHUFDmi addr:$src1, PSHUFD_fp_shuffle_mask:$sm))>, - Requires<[HasSSE2]>; -def : Pat<(vector_shuffle (v4f32 VR128:$src1), (undef), - PSHUFHW_fp_shuffle_mask:$sm), - (v4f32 (PSHUFHWri VR128:$src1, PSHUFHW_fp_shuffle_mask:$sm))>, - Requires<[HasSSE2]>; -def : Pat<(vector_shuffle (loadv4f32 addr:$src1), (undef), - PSHUFHW_fp_shuffle_mask:$sm), - (v4f32 (PSHUFHWmi addr:$src1, PSHUFHW_fp_shuffle_mask:$sm))>, - Requires<[HasSSE2]>; -def : Pat<(vector_shuffle (v4f32 VR128:$src1), (undef), - PSHUFLW_fp_shuffle_mask:$sm), - (v4f32 (PSHUFLWri VR128:$src1, PSHUFLW_fp_shuffle_mask:$sm))>, - Requires<[HasSSE2]>; -def : Pat<(vector_shuffle (loadv4f32 addr:$src1), (undef), - PSHUFLW_fp_shuffle_mask:$sm), - (v4f32 (PSHUFLWmi addr:$src1, PSHUFLW_fp_shuffle_mask:$sm))>, + SHUFP_unary_shuffle_mask:$sm), + (v4f32 (PSHUFDmi addr:$src1, SHUFP_unary_shuffle_mask:$sm))>, Requires<[HasSSE2]>; +// Special binary v4i32 shuffle cases with SHUFPS. +def : Pat<(vector_shuffle (v4i32 VR128:$src1), (v4i32 VR128:$src2), + PSHUFD_binary_shuffle_mask:$sm), + (v4i32 (SHUFPSrr VR128:$src1, VR128:$src2, + PSHUFD_binary_shuffle_mask:$sm))>, Requires<[HasSSE2]>; +def : Pat<(vector_shuffle (v4i32 VR128:$src1), (load addr:$src2), + PSHUFD_binary_shuffle_mask:$sm), + (v4i32 (SHUFPSrm VR128:$src1, addr:$src2, + PSHUFD_binary_shuffle_mask:$sm))>, Requires<[HasSSE2]>; // vector_shuffle v1, , <0, 0, 1, 1, ...> def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef), From lattner at cs.uiuc.edu Mon Apr 10 17:45:50 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 10 Apr 2006 17:45:50 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/InstCombine/vec_shuffle.ll Message-ID: <200604102245.RAA20993@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/InstCombine: vec_shuffle.ll added (r1.1) --- Log message: New testcase --- Diffs of the changes: (+17 -0) vec_shuffle.ll | 17 +++++++++++++++++ 1 files changed, 17 insertions(+) Index: llvm/test/Regression/Transforms/InstCombine/vec_shuffle.ll diff -c /dev/null llvm/test/Regression/Transforms/InstCombine/vec_shuffle.ll:1.1 *** /dev/null Mon Apr 10 17:45:47 2006 --- llvm/test/Regression/Transforms/InstCombine/vec_shuffle.ll Mon Apr 10 17:45:37 2006 *************** *** 0 **** --- 1,17 ---- + ; RUN: llvm-as < %s | opt -instcombine -disable-output && + ; RUN: llvm-as < %s | opt -instcombine | llvm-dis | not grep vector_shuffle + + %T = type <4 x float> + + implementation + + %T %test1(%T %v1) { + %v2 = shufflevector %T %v1, %T undef, <4 x uint> + ret %T %v2 + } + + %T %test2(%T %v1) { + %v2 = shufflevector %T %v1, %T %v1, <4 x uint> + ret %T %v2 + } + From lattner at cs.uiuc.edu Mon Apr 10 17:46:05 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 10 Apr 2006 17:46:05 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp Message-ID: <200604102246.RAA21004@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: InstructionCombining.cpp updated: 1.462 -> 1.463 --- Log message: Implement InstCombine/vec_shuffle.ll:test[12] --- Diffs of the changes: (+62 -0) InstructionCombining.cpp | 62 +++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 62 insertions(+) Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.462 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.463 --- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.462 Thu Apr 6 14:19:17 2006 +++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Mon Apr 10 17:45:52 2006 @@ -138,6 +138,7 @@ Instruction *visitBranchInst(BranchInst &BI); Instruction *visitSwitchInst(SwitchInst &SI); Instruction *visitExtractElementInst(ExtractElementInst &EI); + Instruction *visitShuffleVectorInst(ShuffleVectorInst &SVI); // visitInstruction - Specify what to return for unhandled instructions... Instruction *visitInstruction(Instruction &I) { return 0; } @@ -6876,6 +6877,67 @@ return 0; } +Instruction *InstCombiner::visitShuffleVectorInst(ShuffleVectorInst &SVI) { + Value *LHS = SVI.getOperand(0); + Value *RHS = SVI.getOperand(1); + Constant *Mask = cast(SVI.getOperand(2)); + + bool MadeChange = false; + + if (isa(Mask)) + return ReplaceInstUsesWith(SVI, UndefValue::get(SVI.getType())); + + // Canonicalize shuffle(x,x) -> shuffle(x,undef) + if (LHS == RHS) { + if (isa(LHS)) { + // shuffle(undef,undef,mask) -> undef. + return ReplaceInstUsesWith(SVI, LHS); + } + + if (!isa(Mask)) { + // Remap any references to RHS to use LHS. + ConstantPacked *CP = cast(Mask); + std::vector Elts; + for (unsigned i = 0, e = CP->getNumOperands(); i != e; ++i) { + Elts.push_back(CP->getOperand(i)); + if (isa(CP->getOperand(i))) + continue; + unsigned MV = cast(CP->getOperand(i))->getRawValue(); + if (MV >= e) + Elts.back() = ConstantUInt::get(Type::UIntTy, MV & (e-1)); + } + Mask = ConstantPacked::get(Elts); + } + SVI.setOperand(1, UndefValue::get(RHS->getType())); + SVI.setOperand(2, Mask); + MadeChange = true; + } + + if (ConstantPacked *CP = dyn_cast(Mask)) { + bool isLHSID = true, isRHSID = true; + + // Analyze the shuffle. + for (unsigned i = 0, e = CP->getNumOperands(); i != e; ++i) { + if (isa(CP->getOperand(i))) + continue; + unsigned MV = cast(CP->getOperand(i))->getRawValue(); + + // Is this an identity shuffle of the LHS value? + isLHSID &= (MV == i); + + // Is this an identity shuffle of the RHS value? + isRHSID &= (MV-e == i); + } + + // Eliminate identity shuffles. + if (isLHSID) return ReplaceInstUsesWith(SVI, LHS); + if (isRHSID) return ReplaceInstUsesWith(SVI, RHS); + } + + return MadeChange ? &SVI : 0; +} + + void InstCombiner::removeFromWorkList(Instruction *I) { WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), I), From lattner at cs.uiuc.edu Mon Apr 10 18:06:31 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 10 Apr 2006 18:06:31 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/InstCombine/vec_shuffle.ll Message-ID: <200604102306.SAA21183@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/InstCombine: vec_shuffle.ll updated: 1.1 -> 1.2 --- Log message: new testcase --- Diffs of the changes: (+7 -0) vec_shuffle.ll | 7 +++++++ 1 files changed, 7 insertions(+) Index: llvm/test/Regression/Transforms/InstCombine/vec_shuffle.ll diff -u llvm/test/Regression/Transforms/InstCombine/vec_shuffle.ll:1.1 llvm/test/Regression/Transforms/InstCombine/vec_shuffle.ll:1.2 --- llvm/test/Regression/Transforms/InstCombine/vec_shuffle.ll:1.1 Mon Apr 10 17:45:37 2006 +++ llvm/test/Regression/Transforms/InstCombine/vec_shuffle.ll Mon Apr 10 18:06:18 2006 @@ -15,3 +15,10 @@ ret %T %v2 } +float %test3(%T %A, %T %B, float %f) { + %C = insertelement %T %A, float %f, uint 0 + %D = shufflevector %T %C, %T %B, <4 x uint> + %E = extractelement %T %D, uint 1 + ret float %E +} + From lattner at cs.uiuc.edu Mon Apr 10 18:06:48 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 10 Apr 2006 18:06:48 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp Message-ID: <200604102306.SAA21193@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: InstructionCombining.cpp updated: 1.463 -> 1.464 --- Log message: Implement vec_shuffle.ll:test3 --- Diffs of the changes: (+17 -2) InstructionCombining.cpp | 19 +++++++++++++++++-- 1 files changed, 17 insertions(+), 2 deletions(-) Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.463 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.464 --- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.463 Mon Apr 10 17:45:52 2006 +++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Mon Apr 10 18:06:36 2006 @@ -6779,7 +6779,8 @@ static Value *FindScalarElement(Value *V, unsigned EltNo) { assert(isa(V->getType()) && "Not looking at a vector?"); const PackedType *PTy = cast(V->getType()); - if (EltNo >= PTy->getNumElements()) // Out of range access. + unsigned Width = PTy->getNumElements(); + if (EltNo >= Width) // Out of range access. return UndefValue::get(PTy->getElementType()); if (isa(V)) @@ -6800,6 +6801,19 @@ // Otherwise, the insertelement doesn't modify the value, recurse on its // vector input. return FindScalarElement(III->getOperand(0), EltNo); + } else if (ShuffleVectorInst *SVI = dyn_cast(V)) { + if (isa(SVI->getOperand(2))) { + return FindScalarElement(SVI->getOperand(0), 0); + } else if (ConstantPacked *CP = + dyn_cast(SVI->getOperand(2))) { + if (isa(CP->getOperand(EltNo))) + return UndefValue::get(PTy->getElementType()); + unsigned InEl = cast(CP->getOperand(EltNo))->getValue(); + if (InEl < Width) + return FindScalarElement(SVI->getOperand(0), InEl); + else + return FindScalarElement(SVI->getOperand(1), InEl - Width); + } } // Otherwise, we don't know. @@ -6831,9 +6845,10 @@ // If extracting a specified index from the vector, see if we can recursively // find a previously computed scalar that was inserted into the vector. - if (ConstantUInt *IdxC = dyn_cast(EI.getOperand(1))) + if (ConstantUInt *IdxC = dyn_cast(EI.getOperand(1))) { if (Value *Elt = FindScalarElement(EI.getOperand(0), IdxC->getValue())) return ReplaceInstUsesWith(EI, Elt); + } if (Instruction *I = dyn_cast(EI.getOperand(0))) if (I->hasOneUse()) { From jlaskey at apple.com Mon Apr 10 18:09:33 2006 From: jlaskey at apple.com (Jim Laskey) Date: Mon, 10 Apr 2006 18:09:33 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/DwarfWriter.cpp Message-ID: <200604102309.SAA21250@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: DwarfWriter.cpp updated: 1.56 -> 1.57 --- Log message: Use existing information. --- Diffs of the changes: (+14 -3) DwarfWriter.cpp | 17 ++++++++++++++--- 1 files changed, 14 insertions(+), 3 deletions(-) Index: llvm/lib/CodeGen/DwarfWriter.cpp diff -u llvm/lib/CodeGen/DwarfWriter.cpp:1.56 llvm/lib/CodeGen/DwarfWriter.cpp:1.57 --- llvm/lib/CodeGen/DwarfWriter.cpp:1.56 Fri Apr 7 19:35:59 2006 +++ llvm/lib/CodeGen/DwarfWriter.cpp Mon Apr 10 18:09:19 2006 @@ -25,6 +25,7 @@ #include "llvm/Support/Mangler.h" #include "llvm/Target/MRegisterInfo.h" #include "llvm/Target/TargetMachine.h" +#include "llvm/Target/TargetFrameInfo.h" #include @@ -1829,8 +1830,13 @@ EmitULEB128Bytes(RI->getDwarfRegNum(Src.getRegister())); EOL("Register"); } - - EmitULEB128Bytes(Src.getOffset() / RI->getStackDirection()); + + int stackGrowth = + Asm->TM.getFrameInfo()->getStackGrowthDirection() == + TargetFrameInfo::StackGrowsUp ? + AddressSize : -AddressSize; + + EmitULEB128Bytes(Src.getOffset() / stackGrowth); EOL("Offset"); } else { } @@ -2049,6 +2055,11 @@ /// EmitInitialDebugFrame - Emit common frame info into a debug frame section. /// void DwarfWriter::EmitInitialDebugFrame() { + int stackGrowth = + Asm->TM.getFrameInfo()->getStackGrowthDirection() == + TargetFrameInfo::StackGrowsUp ? + AddressSize : -AddressSize; + // Start the dwarf frame section. Asm->SwitchSection(DwarfFrameSection, 0); @@ -2061,7 +2072,7 @@ EmitInt8(DW_CIE_VERSION); EOL("CIE Version"); EmitString(""); EOL("CIE Augmentation"); EmitULEB128Bytes(1); EOL("CIE Code Alignment Factor"); - EmitSLEB128Bytes(RI->getStackDirection()); EOL("CIE Data Alignment Factor"); + EmitSLEB128Bytes(stackGrowth); EOL("CIE Data Alignment Factor"); EmitInt8(RI->getDwarfRegNum(RI->getRARegister())); EOL("CIE RA Column"); std::vector Moves; From jlaskey at apple.com Mon Apr 10 18:09:33 2006 From: jlaskey at apple.com (Jim Laskey) Date: Mon, 10 Apr 2006 18:09:33 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/MRegisterInfo.cpp Message-ID: <200604102309.SAA21258@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target: MRegisterInfo.cpp updated: 1.14 -> 1.15 --- Log message: Use existing information. --- Diffs of the changes: (+0 -7) MRegisterInfo.cpp | 7 ------- 1 files changed, 7 deletions(-) Index: llvm/lib/Target/MRegisterInfo.cpp diff -u llvm/lib/Target/MRegisterInfo.cpp:1.14 llvm/lib/Target/MRegisterInfo.cpp:1.15 --- llvm/lib/Target/MRegisterInfo.cpp:1.14 Fri Apr 7 11:34:45 2006 +++ llvm/lib/Target/MRegisterInfo.cpp Mon Apr 10 18:09:19 2006 @@ -44,13 +44,6 @@ return Allocatable; } -/// getStackDirection - This method should return the factor by which stacks -/// grow. The tyical value is -4 which is the grows negatively in 4 byte -/// increments. -int MRegisterInfo::getStackDirection() const { - return -sizeof(int32_t); -} - /// getLocation - This method should return the actual location of a frame /// variable given the frame index. The location is returned in ML. /// Subclasses should override this method for special handling of frame From jlaskey at apple.com Mon Apr 10 18:09:33 2006 From: jlaskey at apple.com (Jim Laskey) Date: Mon, 10 Apr 2006 18:09:33 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h Message-ID: <200604102309.SAA21252@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/Target: MRegisterInfo.h updated: 1.74 -> 1.75 --- Log message: Use existing information. --- Diffs of the changes: (+0 -5) MRegisterInfo.h | 5 ----- 1 files changed, 5 deletions(-) Index: llvm/include/llvm/Target/MRegisterInfo.h diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.74 llvm/include/llvm/Target/MRegisterInfo.h:1.75 --- llvm/include/llvm/Target/MRegisterInfo.h:1.74 Fri Apr 7 11:34:45 2006 +++ llvm/include/llvm/Target/MRegisterInfo.h Mon Apr 10 18:09:19 2006 @@ -359,11 +359,6 @@ /// address can be found. virtual unsigned getRARegister() const = 0; - /// getStackDirection - This method should return the factor by which stacks - /// grow. The tyical value is -4 which is the grows negatively in 4 byte - /// increments. - virtual int getStackDirection() const; - /// getLocation - This method should return the actual location of a frame /// variable given the frame index. The location is returned in ML. /// Subclasses should override this method for special handling of frame From evan.cheng at apple.com Mon Apr 10 19:19:17 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 10 Apr 2006 19:19:17 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h X86InstrSSE.td Message-ID: <200604110019.TAA21511@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.161 -> 1.162 X86ISelLowering.h updated: 1.53 -> 1.54 X86InstrSSE.td updated: 1.72 -> 1.73 --- Log message: Added support for _mm_move_ss and _mm_move_sd. --- Diffs of the changes: (+46 -2) X86ISelLowering.cpp | 29 +++++++++++++++++++++++++++-- X86ISelLowering.h | 4 ++++ X86InstrSSE.td | 15 +++++++++++++++ 3 files changed, 46 insertions(+), 2 deletions(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.161 llvm/lib/Target/X86/X86ISelLowering.cpp:1.162 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.161 Mon Apr 10 02:23:14 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Apr 10 19:19:04 2006 @@ -1684,6 +1684,26 @@ return true; } +/// isMOVSMask - Return true if the specified VECTOR_SHUFFLE operand +/// specifies a shuffle of elements that is suitable for input to MOVS{S|D}. +bool X86::isMOVSMask(SDNode *N) { + assert(N->getOpcode() == ISD::BUILD_VECTOR); + + unsigned NumElems = N->getNumOperands(); + if (NumElems != 2 && NumElems != 4) + return false; + + if (!isUndefOrEqual(N->getOperand(0), NumElems)) + return false; + + for (unsigned i = 1; i < NumElems; ++i) { + SDOperand Arg = N->getOperand(i); + if (!isUndefOrEqual(Arg, i)) + return false; + } + + return true; +} /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies /// a splat of a single element. @@ -2680,6 +2700,10 @@ if (NumElems == 2) return Op; + if (X86::isMOVSMask(PermMask.Val)) + // Leave the VECTOR_SHUFFLE alone. It matches MOVS{S|D}. + return Op; + if (X86::isUNPCKLMask(PermMask.Val) || X86::isUNPCKL_v_undef_Mask(PermMask.Val) || X86::isUNPCKHMask(PermMask.Val)) @@ -3106,10 +3130,11 @@ // Only do shuffles on 128-bit vector types for now. if (MVT::getSizeInBits(VT) == 64) return false; return (Mask.Val->getNumOperands() == 2 || - X86::isSplatMask(Mask.Val) || + X86::isSplatMask(Mask.Val) || + X86::isMOVSMask(Mask.Val) || X86::isPSHUFDMask(Mask.Val) || isPSHUFHW_PSHUFLWMask(Mask.Val) || - X86::isSHUFPMask(Mask.Val) || + X86::isSHUFPMask(Mask.Val) || X86::isUNPCKLMask(Mask.Val) || X86::isUNPCKL_v_undef_Mask(Mask.Val) || X86::isUNPCKHMask(Mask.Val)); Index: llvm/lib/Target/X86/X86ISelLowering.h diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.53 llvm/lib/Target/X86/X86ISelLowering.h:1.54 --- llvm/lib/Target/X86/X86ISelLowering.h:1.53 Thu Apr 6 18:23:56 2006 +++ llvm/lib/Target/X86/X86ISelLowering.h Mon Apr 10 19:19:04 2006 @@ -233,6 +233,10 @@ /// <0, 0, 1, 1> bool isUNPCKL_v_undef_Mask(SDNode *N); + /// isMOVSMask - Return true if the specified VECTOR_SHUFFLE operand + /// specifies a shuffle of elements that is suitable for input to MOVS{S|D}. + bool isMOVSMask(SDNode *N); + /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand /// specifies a splat of a single element. bool isSplatMask(SDNode *N); Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.72 llvm/lib/Target/X86/X86InstrSSE.td:1.73 --- llvm/lib/Target/X86/X86InstrSSE.td:1.72 Mon Apr 10 17:35:16 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Mon Apr 10 19:19:04 2006 @@ -104,6 +104,10 @@ return X86::isMOVLPMask(N); }]>; +def MOVS_shuffle_mask : PatLeaf<(build_vector), [{ + return X86::isMOVSMask(N); +}]>; + def UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{ return X86::isUNPCKLMask(N); }]>; @@ -1641,6 +1645,17 @@ "movsd {$src2, $dst|$dst, $src2}", []>; def MOVLDI2PDIrr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, VR128:$src1, R32:$src2), "movd {$src2, $dst|$dst, $src2}", []>; + +def MOVLPSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), + "movss {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, + (v4f32 (vector_shuffle VR128:$src1, VR128:$src2, + MOVS_shuffle_mask)))]>; +def MOVLPDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), + "movsd {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, + (v2f64 (vector_shuffle VR128:$src1, VR128:$src2, + MOVS_shuffle_mask)))]>; } // Move to lower bits of a VR128 and zeroing upper bits. From lattner at cs.uiuc.edu Mon Apr 10 20:09:38 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 10 Apr 2006 20:09:38 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineFunction.h Message-ID: <200604110109.UAA21729@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineFunction.h updated: 1.57 -> 1.58 --- Log message: Add helper methods. --- Diffs of the changes: (+2 -0) MachineFunction.h | 2 ++ 1 files changed, 2 insertions(+) Index: llvm/include/llvm/CodeGen/MachineFunction.h diff -u llvm/include/llvm/CodeGen/MachineFunction.h:1.57 llvm/include/llvm/CodeGen/MachineFunction.h:1.58 --- llvm/include/llvm/CodeGen/MachineFunction.h:1.57 Wed Jan 4 07:44:43 2006 +++ llvm/include/llvm/CodeGen/MachineFunction.h Mon Apr 10 20:09:25 2006 @@ -192,8 +192,10 @@ typedef std::vector::const_iterator liveout_iterator; livein_iterator livein_begin() const { return LiveIns.begin(); } livein_iterator livein_end() const { return LiveIns.end(); } + bool livein_empty() const { return LiveIns.empty(); } liveout_iterator liveout_begin() const { return LiveOuts.begin(); } liveout_iterator liveout_end() const { return LiveOuts.end(); } + bool liveout_empty() const { return LiveOuts.empty(); } /// getBlockNumbered - MachineBasicBlocks are automatically numbered when they /// are inserted into the machine function. The block number for a machine From lattner at cs.uiuc.edu Mon Apr 10 20:21:56 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 10 Apr 2006 20:21:56 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp Message-ID: <200604110121.UAA21819@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.142 -> 1.143 --- Log message: Move some return-handling code from lowerarguments to the ISD::RET handling stuff. No functionality change. --- Diffs of the changes: (+9 -20) PPCISelLowering.cpp | 29 +++++++++-------------------- 1 files changed, 9 insertions(+), 20 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.142 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.143 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.142 Sat Apr 8 17:59:15 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Mon Apr 10 20:21:43 2006 @@ -880,12 +880,21 @@ unsigned ArgReg = MVT::isInteger(ArgVT) ? PPC::R3 : PPC::F1; Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1), SDOperand()); + + // If we haven't noted the R3/F1 are live out, do so now. + if (DAG.getMachineFunction().liveout_empty()) + DAG.getMachineFunction().addLiveOut(ArgReg); break; } case 3: Copy = DAG.getCopyToReg(Op.getOperand(0), PPC::R3, Op.getOperand(2), SDOperand()); Copy = DAG.getCopyToReg(Copy, PPC::R4, Op.getOperand(1),Copy.getValue(1)); + // If we haven't noted the R3+R4 are live out, do so now. + if (DAG.getMachineFunction().liveout_empty()) { + DAG.getMachineFunction().addLiveOut(PPC::R3); + DAG.getMachineFunction().addLiveOut(PPC::R4); + } break; } return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); @@ -1249,26 +1258,6 @@ } } - // Finally, inform the code generator which regs we return values in. - switch (getValueType(F.getReturnType())) { - default: assert(0 && "Unknown type!"); - case MVT::isVoid: break; - case MVT::i1: - case MVT::i8: - case MVT::i16: - case MVT::i32: - MF.addLiveOut(PPC::R3); - break; - case MVT::i64: - MF.addLiveOut(PPC::R3); - MF.addLiveOut(PPC::R4); - break; - case MVT::f32: - case MVT::f64: - MF.addLiveOut(PPC::F1); - break; - } - return ArgValues; } From lattner at cs.uiuc.edu Mon Apr 10 20:32:03 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 10 Apr 2006 20:32:03 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <200604110132.UAA21901@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.358 -> 1.359 --- Log message: Add basic support for legalizing returns of vectors --- Diffs of the changes: (+36 -9) LegalizeDAG.cpp | 45 ++++++++++++++++++++++++++++++++++++--------- 1 files changed, 36 insertions(+), 9 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.358 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.359 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.358 Mon Apr 10 13:54:36 2006 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Apr 10 20:31:51 2006 @@ -1397,20 +1397,47 @@ Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); Tmp1 = LegalizeOp(Tmp1); LastCALLSEQ_END = DAG.getEntryNode(); - + Tmp2 = Node->getOperand(1); + switch (Node->getNumOperands()) { case 2: // ret val - switch (getTypeAction(Node->getOperand(1).getValueType())) { + switch (getTypeAction(Tmp2.getValueType())) { case Legal: - Tmp2 = LegalizeOp(Node->getOperand(1)); - Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); + Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2)); break; - case Expand: { - SDOperand Lo, Hi; - ExpandOp(Node->getOperand(1), Lo, Hi); - Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi); + case Expand: + if (Tmp2.getValueType() != MVT::Vector) { + SDOperand Lo, Hi; + ExpandOp(Tmp2, Lo, Hi); + Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi); + } else { + SDNode *InVal = Tmp2.Val; + unsigned NumElems = + cast(*(InVal->op_end()-2))->getValue(); + MVT::ValueType EVT = cast(*(InVal->op_end()-1))->getVT(); + + // Figure out if there is a Packed type corresponding to this Vector + // type. If so, convert to the packed type. + MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); + if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) { + // Turn this into a return of the packed type. + Tmp2 = PackVectorOp(Tmp2, TVT); + Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); + } else if (NumElems == 1) { + // Turn this into a return of the scalar type. + Tmp2 = PackVectorOp(Tmp2, EVT); + Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); + // The scalarized value type may not be legal, e.g. it might require + // promotion or expansion. Relegalize the return. + Result = LegalizeOp(Result); + } else { + SDOperand Lo, Hi; + SplitVectorOp(Tmp2, Lo, Hi); + Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi); + Result = LegalizeOp(Result); + } + } break; - } case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); From lattner at cs.uiuc.edu Mon Apr 10 20:38:50 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 10 Apr 2006 20:38:50 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp Message-ID: <200604110138.UAA21977@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.143 -> 1.144 --- Log message: Vector function results go into V2 according to GCC. The darwin ABI doc doesn't say where they go :-/ --- Diffs of the changes: (+10 -1) PPCISelLowering.cpp | 11 ++++++++++- 1 files changed, 10 insertions(+), 1 deletion(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.143 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.144 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.143 Mon Apr 10 20:21:43 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Mon Apr 10 20:38:39 2006 @@ -877,7 +877,16 @@ return SDOperand(); // ret void is legal case 2: { MVT::ValueType ArgVT = Op.getOperand(1).getValueType(); - unsigned ArgReg = MVT::isInteger(ArgVT) ? PPC::R3 : PPC::F1; + unsigned ArgReg; + if (MVT::isVector(ArgVT)) + ArgReg = PPC::V2; + else if (MVT::isInteger(ArgVT)) + ArgReg = PPC::R3; + else { + assert(MVT::isFloatingPoint(ArgVT)); + ArgReg = PPC::F1; + } + Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1), SDOperand()); From lattner at cs.uiuc.edu Mon Apr 10 21:00:21 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 10 Apr 2006 21:00:21 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <200604110200.VAA22139@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.359 -> 1.360 --- Log message: add some todos --- Diffs of the changes: (+8 -0) LegalizeDAG.cpp | 8 ++++++++ 1 files changed, 8 insertions(+) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.359 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.360 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.359 Mon Apr 10 20:31:51 2006 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Apr 10 21:00:08 2006 @@ -1427,10 +1427,16 @@ // Turn this into a return of the scalar type. Tmp2 = PackVectorOp(Tmp2, EVT); Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); + + // FIXME: Returns of gcc generic vectors smaller than a legal type + // should be returned in integer registers! + // The scalarized value type may not be legal, e.g. it might require // promotion or expansion. Relegalize the return. Result = LegalizeOp(Result); } else { + // FIXME: Returns of gcc generic vectors larger than a legal vector + // type should be returned by reference! SDOperand Lo, Hi; SplitVectorOp(Tmp2, Lo, Hi); Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi); @@ -1458,6 +1464,8 @@ break; case Expand: { SDOperand Lo, Hi; + assert(Node->getOperand(i).getValueType() != MVT::Vector && + "FIXME: TODO: implement returning non-legal vector types!"); ExpandOp(Node->getOperand(i), Lo, Hi); NewValues.push_back(Lo); NewValues.push_back(Hi); From jeffc at jolt-lang.org Mon Apr 10 21:01:35 2006 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Mon, 10 Apr 2006 21:01:35 -0500 Subject: [llvm-commits] CVS: llvm/win32/Transforms/Transforms.vcproj Message-ID: <200604110201.VAA22161@zion.cs.uiuc.edu> Changes in directory llvm/win32/Transforms: Transforms.vcproj updated: 1.21 -> 1.22 --- Log message: Keep Visual Studio happy. --- Diffs of the changes: (+3 -0) Transforms.vcproj | 3 +++ 1 files changed, 3 insertions(+) Index: llvm/win32/Transforms/Transforms.vcproj diff -u llvm/win32/Transforms/Transforms.vcproj:1.21 llvm/win32/Transforms/Transforms.vcproj:1.22 --- llvm/win32/Transforms/Transforms.vcproj:1.21 Sun Jan 29 22:07:07 2006 +++ llvm/win32/Transforms/Transforms.vcproj Mon Apr 10 21:01:22 2006 @@ -179,6 +179,9 @@ RelativePath="..\..\lib\Transforms\Ipo\GlobalOpt.cpp"> + + Changes in directory llvm: CREDITS.TXT updated: 1.46 -> 1.47 --- Log message: update my credits entry per clattner's request! --- Diffs of the changes: (+2 -1) CREDITS.TXT | 3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index: llvm/CREDITS.TXT diff -u llvm/CREDITS.TXT:1.46 llvm/CREDITS.TXT:1.47 --- llvm/CREDITS.TXT:1.46 Thu Mar 23 17:21:29 2006 +++ llvm/CREDITS.TXT Tue Apr 11 00:47:45 2006 @@ -18,7 +18,8 @@ N: Nate Begeman E: natebegeman at mac.com -D: Primary PowerPC backend developer +D: PowerPC backend developer +D: Target-independent code generator and analysis improvements N: Daniel Berlin E: dberlin at dberlin.org From reid at x10sys.com Tue Apr 11 00:48:52 2006 From: reid at x10sys.com (Reid Spencer) Date: Tue, 11 Apr 2006 00:48:52 -0500 Subject: [llvm-commits] CVS: llvm/CREDITS.TXT Message-ID: <200604110548.AAA22893@zion.cs.uiuc.edu> Changes in directory llvm: CREDITS.TXT updated: 1.47 -> 1.48 --- Log message: Update my entry. --- Diffs of the changes: (+3 -1) CREDITS.TXT | 4 +++- 1 files changed, 3 insertions(+), 1 deletion(-) Index: llvm/CREDITS.TXT diff -u llvm/CREDITS.TXT:1.47 llvm/CREDITS.TXT:1.48 --- llvm/CREDITS.TXT:1.47 Tue Apr 11 00:47:45 2006 +++ llvm/CREDITS.TXT Tue Apr 11 00:48:40 2006 @@ -138,7 +138,9 @@ N: Reid Spencer E: rspencer at x10sys.com W: http://llvm.x10sys.com/rspencer -D: Stacker, llvmc, bytecode, other. See web page for current notes. +D: Stacker, llvmc, llvm-ld, llvm-ar, lib/Archive, lib/Linker, lib/System, +D: bytecode enhancements, symtab hacking, unoverloading of intrinsics, makefile +D: and configuration system, documentation. N: Adam Treat E: manyoso at yahoo.com From reid at x10sys.com Tue Apr 11 01:21:37 2006 From: reid at x10sys.com (Reid Spencer) Date: Tue, 11 Apr 2006 01:21:37 -0500 Subject: [llvm-commits] CVS: llvm/docs/HowToReleaseLLVM.html Message-ID: <200604110621.BAA28776@zion.cs.uiuc.edu> Changes in directory llvm/docs: HowToReleaseLLVM.html updated: 1.3 -> 1.4 --- Log message: Flesh out the documentation a little bit more. --- Diffs of the changes: (+55 -9) HowToReleaseLLVM.html | 64 ++++++++++++++++++++++++++++++++++++++++++-------- 1 files changed, 55 insertions(+), 9 deletions(-) Index: llvm/docs/HowToReleaseLLVM.html diff -u llvm/docs/HowToReleaseLLVM.html:1.3 llvm/docs/HowToReleaseLLVM.html:1.4 --- llvm/docs/HowToReleaseLLVM.html:1.3 Mon Apr 10 16:43:05 2006 +++ llvm/docs/HowToReleaseLLVM.html Tue Apr 11 01:21:25 2006 @@ -38,6 +38,7 @@
  1. Merge Branches
    2. +
  2. Settle LLVM HEAD
  3. Build LLVM
  4. Run 'make check'
  5. Run LLVM Test Suite
    6. @@ -51,27 +52,45 @@
    Merge Branches
    -

    Merge any work done on branches intended for release into mainline.

    +

    Merge any work done on branches intended for release into mainline. Work that +is not to be incorporated into the release should not be merged from the branch. +

    +
    + + +
    Settle CVS HEAD
    +
    +

    Use the nightly test reports, and 'make check' (deja-gnu based tests) to + increase the quality of LLVM and ensure that merged branches have not + destabilized LLVM.

    Build LLVM
    -

    Build LLVM

    +

    Build both debug and release versions of LLVM on all platforms. Ensure + build is warning and error free on each platform.

    Run 'make check'

    Run make check and ensure there are no unexpected failures. If - there are, resolve the failures and go back to step 2.

    + there are, resolve the failures and go back to step 2. + Ensure that 'make check' passes on all platforms for all targets. If certain + failures cannot be resolved before release time, determine if marking them + XFAIL is appropriate. If not, fix the bug and go back. The test suite must + complete with "0 unexpected failures" for release. +

    LLVM Test Suite

    Run the llvm-test suite and ensure there are no unacceptable failures. - If there are, resolve the failures and go back to step 2.

    + If there are, resolve the failures and go back to step 2. The test suite + should be run in Nightly Test mode. All tests must pass. If they do not, + investigate and go back to settling CVS HEAD.

    @@ -83,21 +102,48 @@
-
CVS Tag
+
CVS Tag And Branch
-

Tag the release.

+

Tag and branch the CVS HEAD using the following procedure:

+
    +
  1. Request all developers to refrain from committing. Offenders get commit + rights taken away (temporarily).
    2. +
  2. Tag the cvs HEAD with "ROOT_RELEASE_XX" where XX is the major and minor + release numbers (you can't have . in a cvs tag name). So, for Release 1.2, + XX=12 and for Release 1.10, XX=110.
    3. +
  3. Immediately create a cvs branch based on the ROOT_RELEASE tag. This is + where the release distribution will be created.
    4. +
  4. Advise developers they can work on CVS HEAD again.
    5. +
  5. Ensure all subsequent building and fixing is done on this branch.
Run 'make dist'
-

Build the distribution, ensuring it is installable and working

+

Build the distribution, ensuring it is installable and working. This is a + two step process. First, use "make dist" to simply build the distribution. Any + failures need to be corrected (on the branch). Once "make dist" can be + successful, do "make dist-check". This target will do the same thing as the + 'dist' target but also test that distribution to make sure it works. This + ensures that needed files are not missing and that the src tarball can be + successfully unbacked, built, installed, and cleaned. This two-level testing + needs to be done on each target platform.

Release
-

Release the distribution tarball to the public.

+

Release the distribution tarball to the public. This consists of generating + several tarballs. The first set, the source distributions, are automatically + generated by the "make dist" and "make dist-check". There are gzip, bzip2, and + zip versions of these bundles.

+

The second set of tarballs is the binary release. When "make dist-check" + succeeds, it will have created an _install directory into which it installed + the binary release. You need to rename that directory as "llvm" and then + create tarballs from the contents of that "llvm" directory.

+

Finally, use rpm to make an rpm package based on the llvm.spec file. Don't + forget to update the version number, documentation, etc. in the llvm.spec + file.

@@ -111,7 +157,7 @@ Reid Spencer
The LLVM Compiler Infrastructure
- Last modified: $Date: 2006/04/10 21:43:05 $ + Last modified: $Date: 2006/04/11 06:21:25 $ From reid at x10sys.com Tue Apr 11 01:22:27 2006 From: reid at x10sys.com (Reid Spencer) Date: Tue, 11 Apr 2006 01:22:27 -0500 Subject: [llvm-commits] CVS: llvm/docs/HowToReleaseLLVM.html Message-ID: <200604110622.BAA28826@zion.cs.uiuc.edu> Changes in directory llvm/docs: HowToReleaseLLVM.html updated: 1.4 -> 1.5 --- Log message: Fix an anchor. --- Diffs of the changes: (+2 -2) HowToReleaseLLVM.html | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/docs/HowToReleaseLLVM.html diff -u llvm/docs/HowToReleaseLLVM.html:1.4 llvm/docs/HowToReleaseLLVM.html:1.5 --- llvm/docs/HowToReleaseLLVM.html:1.4 Tue Apr 11 01:21:25 2006 +++ llvm/docs/HowToReleaseLLVM.html Tue Apr 11 01:22:15 2006 @@ -58,7 +58,7 @@
-
Settle CVS HEAD
+
Settle CVS HEAD

Use the nightly test reports, and 'make check' (deja-gnu based tests) to increase the quality of LLVM and ensure that merged branches have not @@ -157,7 +157,7 @@ Reid Spencer
The LLVM Compiler Infrastructure
- Last modified: $Date: 2006/04/11 06:21:25 $ + Last modified: $Date: 2006/04/11 06:22:15 $ From evan.cheng at apple.com Tue Apr 11 01:33:51 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 11 Apr 2006 01:33:51 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <200604110633.BAA28878@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.360 -> 1.361 --- Log message: Only get Tmp2 for cases where number of operands is > 1. Fixed return void. --- Diffs of the changes: (+1 -1) LegalizeDAG.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.360 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.361 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.360 Mon Apr 10 21:00:08 2006 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Apr 11 01:33:39 2006 @@ -1397,10 +1397,10 @@ Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); Tmp1 = LegalizeOp(Tmp1); LastCALLSEQ_END = DAG.getEntryNode(); - Tmp2 = Node->getOperand(1); switch (Node->getNumOperands()) { case 2: // ret val + Tmp2 = Node->getOperand(1); switch (getTypeAction(Tmp2.getValueType())) { case Legal: Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2)); From evan.cheng at apple.com Tue Apr 11 01:56:39 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 11 Apr 2006 01:56:39 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/IntrinsicsX86.td Message-ID: <200604110656.BAA29013@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm: IntrinsicsX86.td updated: 1.15 -> 1.16 --- Log message: movnt* and maskmovdqu intrinsics --- Diffs of the changes: (+19 -4) IntrinsicsX86.td | 23 +++++++++++++++++++---- 1 files changed, 19 insertions(+), 4 deletions(-) Index: llvm/include/llvm/IntrinsicsX86.td diff -u llvm/include/llvm/IntrinsicsX86.td:1.15 llvm/include/llvm/IntrinsicsX86.td:1.16 --- llvm/include/llvm/IntrinsicsX86.td:1.15 Mon Apr 10 17:02:38 2006 +++ llvm/include/llvm/IntrinsicsX86.td Tue Apr 11 01:56:27 2006 @@ -141,10 +141,9 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse_prefetch : GCCBuiltin<"__builtin_ia32_prefetch">, Intrinsic<[llvm_ptr_ty, llvm_int_ty], [IntrWriteMem]>; - def int_x86_sse_movntq : GCCBuiltin<"__builtin_ia32_movntq">, - Intrinsic<[llvm_ptr_ty, llvm_v2i32_ty], [IntrWriteMem]>; - def int_x86_sse_movntps : GCCBuiltin<"__builtin_ia32_movntps">, - Intrinsic<[llvm_ptr_ty, llvm_v4f32_ty], [IntrWriteMem]>; + def int_x86_sse_movnt_ps : GCCBuiltin<"__builtin_ia32_movntps">, + Intrinsic<[llvm_void_ty, llvm_ptr_ty, + llvm_v4f32_ty], [IntrWriteMem]>; def int_x86_sse_sfence : GCCBuiltin<"__builtin_ia32_sfence">, Intrinsic<[llvm_void_ty], [IntrWriteMem]>; } @@ -281,6 +280,19 @@ llvm_v2f64_ty], [IntrWriteMem]>; } +// Cacheability support ops +let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". + def int_x86_sse2_movnt_dq : GCCBuiltin<"__builtin_ia32_movntdq">, + Intrinsic<[llvm_void_ty, llvm_ptr_ty, + llvm_v2i64_ty], [IntrWriteMem]>; + def int_x86_sse2_movnt_pd : GCCBuiltin<"__builtin_ia32_movntpd">, + Intrinsic<[llvm_void_ty, llvm_ptr_ty, + llvm_v2f64_ty], [IntrWriteMem]>; + def int_x86_sse2_movnt_i : GCCBuiltin<"__builtin_ia32_movnti">, + Intrinsic<[llvm_void_ty, llvm_ptr_ty, + llvm_int_ty], [IntrWriteMem]>; +} + // Misc. let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse2_packsswb_128 : GCCBuiltin<"__builtin_ia32_packsswb128">, @@ -296,6 +308,9 @@ Intrinsic<[llvm_int_ty, llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_pmovmskb_128 : GCCBuiltin<"__builtin_ia32_pmovmskb128">, Intrinsic<[llvm_int_ty, llvm_v16i8_ty], [IntrNoMem]>; + def int_x86_sse2_maskmov_dqu : GCCBuiltin<"__builtin_ia32_maskmovdqu">, + Intrinsic<[llvm_void_ty, llvm_v16i8_ty, + llvm_v16i8_ty, llvm_ptr_ty], [IntrWriteMem]>; } //===----------------------------------------------------------------------===// From evan.cheng at apple.com Tue Apr 11 01:57:42 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 11 Apr 2006 01:57:42 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrMMX.td X86InstrSSE.td Message-ID: <200604110657.BAA29027@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrMMX.td updated: 1.9 -> 1.10 X86InstrSSE.td updated: 1.73 -> 1.74 --- Log message: movnt* and maskmovdqu intrinsics --- Diffs of the changes: (+44 -16) X86InstrMMX.td | 25 +++++++++++++++++++++++++ X86InstrSSE.td | 35 +++++++++++++++++++---------------- 2 files changed, 44 insertions(+), 16 deletions(-) Index: llvm/lib/Target/X86/X86InstrMMX.td diff -u llvm/lib/Target/X86/X86InstrMMX.td:1.9 llvm/lib/Target/X86/X86InstrMMX.td:1.10 --- llvm/lib/Target/X86/X86InstrMMX.td:1.9 Sat Mar 25 00:00:03 2006 +++ llvm/lib/Target/X86/X86InstrMMX.td Tue Apr 11 01:57:30 2006 @@ -13,6 +13,13 @@ // //===----------------------------------------------------------------------===// +// Instruction templates +// MMXi8 - MMX instructions with ImmT == Imm8 and TB prefix. +class MMXIi8 o, Format F, dag ops, string asm, list pattern> + : X86Inst, TB, Requires<[HasMMX]> { + let Pattern = pattern; +} + // Some 'special' instructions def IMPLICIT_DEF_VR64 : I<0, Pseudo, (ops VR64:$dst), "#IMPLICIT_DEF $dst", @@ -50,3 +57,21 @@ def CVTTPS2PIrm: I<0x2C, MRMSrcMem, (ops VR64:$dst, f64mem:$src), "cvttps2pi {$src, $dst|$dst, $src}", []>, TB, Requires<[HasMMX]>; + +// Shuffle and unpack instructions +def PSHUFWri : MMXIi8<0x70, MRMSrcReg, + (ops VR64:$dst, VR64:$src1, i8imm:$src2), + "pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>; +def PSHUFWmi : MMXIi8<0x70, MRMSrcMem, + (ops VR64:$dst, i64mem:$src1, i8imm:$src2), + "pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>; + +// Misc. +def MOVNTQ : I<0xE7, MRMDestMem, (ops i64mem:$dst, VR64:$src), + "movntq {$src, $dst|$dst, $src}", []>, TB, + Requires<[HasMMX]>; + +def MASKMOVQ : I<0xF7, MRMDestMem, (ops VR64:$src, VR64:$mask), + "maskmovq {$mask, $src|$src, $mask}", []>, TB, + Requires<[HasMMX]>; + Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.73 llvm/lib/Target/X86/X86InstrSSE.td:1.74 --- llvm/lib/Target/X86/X86InstrSSE.td:1.73 Mon Apr 10 19:19:04 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Tue Apr 11 01:57:30 2006 @@ -1321,13 +1321,6 @@ } // Shuffle and unpack instructions -def PSHUFWri : PSIi8<0x70, MRMSrcReg, - (ops VR64:$dst, VR64:$src1, i8imm:$src2), - "pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>; -def PSHUFWmi : PSIi8<0x70, MRMSrcMem, - (ops VR64:$dst, i64mem:$src1, i8imm:$src2), - "pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>; - def PSHUFDri : PDIi8<0x70, MRMSrcReg, (ops VR128:$dst, VR128:$src1, i8imm:$src2), "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}", @@ -1516,6 +1509,12 @@ "pmovmskb {$src, $dst|$dst, $src}", [(set R32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>; +// Conditional store +def MASKMOVDQU : PDI<0xF7, RawFrm, (ops VR128:$src, VR128:$mask), + "maskmovdqu {$mask, $src|$src, $mask}", + [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>, + Imp<[EDI],[]>; + // Prefetching loads def PREFETCHT0 : I<0x18, MRM1m, (ops i8mem:$src), "prefetcht0 $src", []>, TB, @@ -1531,15 +1530,19 @@ Requires<[HasSSE1]>; // Non-temporal stores -def MOVNTQ : I<0xE7, MRMDestMem, (ops i64mem:$dst, VR64:$src), - "movntq {$src, $dst|$dst, $src}", []>, TB, - Requires<[HasSSE1]>; -def MOVNTPS : I<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src), - "movntps {$src, $dst|$dst, $src}", []>, TB, - Requires<[HasSSE1]>; -def MASKMOVQ : I<0xF7, MRMDestMem, (ops i64mem:$dst, VR64:$src), - "maskmovq {$src, $dst|$dst, $src}", []>, TB, - Requires<[HasSSE1]>; +def MOVNTPSmr : PSI<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src), + "movntps {$src, $dst|$dst, $src}", + [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>; +def MOVNTPDmr : PDI<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src), + "movntpd {$src, $dst|$dst, $src}", + [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>; +def MOVNTDQmr : PDI<0xE7, MRMDestMem, (ops f128mem:$dst, VR128:$src), + "movntdq {$src, $dst|$dst, $src}", + [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>; +def MOVNTImr : I<0xC3, MRMDestMem, (ops i32mem:$dst, R32:$src), + "movnti {$src, $dst|$dst, $src}", + [(int_x86_sse2_movnt_i addr:$dst, R32:$src)]>, + TB, Requires<[HasSSE2]>; // Store fence def SFENCE : I<0xAE, MRM7m, (ops), From jlaskey at apple.com Tue Apr 11 03:12:55 2006 From: jlaskey at apple.com (Jim Laskey) Date: Tue, 11 Apr 2006 03:12:55 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Message-ID: <200604110812.DAA28910@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCRegisterInfo.cpp updated: 1.54 -> 1.55 --- Log message: Suppress debug label when not debug. --- Diffs of the changes: (+1 -1) PPCRegisterInfo.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.54 llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.55 --- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.54 Fri Apr 7 11:34:45 2006 +++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Tue Apr 11 03:11:53 2006 @@ -407,7 +407,7 @@ .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0); } - if (DebugInfo) { + if (DebugInfo && DebugInfo->hasInfo()) { std::vector &Moves = DebugInfo->getFrameMoves(); unsigned LabelID = DebugInfo->NextLabelID(); From jlaskey at apple.com Tue Apr 11 03:17:50 2006 From: jlaskey at apple.com (Jim Laskey) Date: Tue, 11 Apr 2006 03:17:50 -0500 Subject: [llvm-commits] CVS: llvm/CREDITS.TXT Message-ID: <200604110817.DAA06285@zion.cs.uiuc.edu> Changes in directory llvm: CREDITS.TXT updated: 1.48 -> 1.49 --- Log message: Update credibility. --- Diffs of the changes: (+1 -0) CREDITS.TXT | 1 + 1 files changed, 1 insertion(+) Index: llvm/CREDITS.TXT diff -u llvm/CREDITS.TXT:1.48 llvm/CREDITS.TXT:1.49 --- llvm/CREDITS.TXT:1.48 Tue Apr 11 00:48:40 2006 +++ llvm/CREDITS.TXT Tue Apr 11 03:16:45 2006 @@ -89,6 +89,7 @@ N: Jim Laskey E: jlaskey at apple.com D: Improvements to the PPC backend, instruction scheduling +D: Debug implementation, Dwarf implementation N: Chris Lattner E: sabre at nondot.org From evan.cheng at apple.com Tue Apr 11 12:36:20 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 11 Apr 2006 12:36:20 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/IntrinsicsX86.td Message-ID: <200604111736.MAA13329@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm: IntrinsicsX86.td updated: 1.16 -> 1.17 --- Log message: Misc. intrinsics. --- Diffs of the changes: (+2 -1) IntrinsicsX86.td | 3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index: llvm/include/llvm/IntrinsicsX86.td diff -u llvm/include/llvm/IntrinsicsX86.td:1.16 llvm/include/llvm/IntrinsicsX86.td:1.17 --- llvm/include/llvm/IntrinsicsX86.td:1.16 Tue Apr 11 01:56:27 2006 +++ llvm/include/llvm/IntrinsicsX86.td Tue Apr 11 12:35:57 2006 @@ -140,7 +140,8 @@ // Cacheability support ops let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse_prefetch : GCCBuiltin<"__builtin_ia32_prefetch">, - Intrinsic<[llvm_ptr_ty, llvm_int_ty], [IntrWriteMem]>; + Intrinsic<[llvm_void_ty, llvm_ptr_ty, + llvm_int_ty], [IntrWriteMem]>; def int_x86_sse_movnt_ps : GCCBuiltin<"__builtin_ia32_movntps">, Intrinsic<[llvm_void_ty, llvm_ptr_ty, llvm_v4f32_ty], [IntrWriteMem]>; From evan.cheng at apple.com Tue Apr 11 12:36:20 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 11 Apr 2006 12:36:20 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td Message-ID: <200604111736.MAA13330@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrSSE.td updated: 1.74 -> 1.75 --- Log message: Misc. intrinsics. --- Diffs of the changes: (+13 -13) X86InstrSSE.td | 26 +++++++++++++------------- 1 files changed, 13 insertions(+), 13 deletions(-) Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.74 llvm/lib/Target/X86/X86InstrSSE.td:1.75 --- llvm/lib/Target/X86/X86InstrSSE.td:1.74 Tue Apr 11 01:57:30 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Tue Apr 11 12:35:57 2006 @@ -1516,18 +1516,18 @@ Imp<[EDI],[]>; // Prefetching loads -def PREFETCHT0 : I<0x18, MRM1m, (ops i8mem:$src), - "prefetcht0 $src", []>, TB, - Requires<[HasSSE1]>; -def PREFETCHT1 : I<0x18, MRM2m, (ops i8mem:$src), - "prefetcht0 $src", []>, TB, - Requires<[HasSSE1]>; -def PREFETCHT2 : I<0x18, MRM3m, (ops i8mem:$src), - "prefetcht0 $src", []>, TB, - Requires<[HasSSE1]>; -def PREFETCHTNTA : I<0x18, MRM0m, (ops i8mem:$src), - "prefetcht0 $src", []>, TB, - Requires<[HasSSE1]>; +def PREFETCHT0 : PSI<0x18, MRM1m, (ops i8mem:$src), + "prefetcht0 $src", + [(int_x86_sse_prefetch addr:$src, 1)]>; +def PREFETCHT1 : PSI<0x18, MRM2m, (ops i8mem:$src), + "prefetcht1 $src", + [(int_x86_sse_prefetch addr:$src, 2)]>; +def PREFETCHT2 : PSI<0x18, MRM3m, (ops i8mem:$src), + "prefetcht2 $src", + [(int_x86_sse_prefetch addr:$src, 3)]>; +def PREFETCHTNTA : PSI<0x18, MRM0m, (ops i8mem:$src), + "prefetchtnta $src", + [(int_x86_sse_prefetch addr:$src, 0)]>; // Non-temporal stores def MOVNTPSmr : PSI<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src), @@ -1546,7 +1546,7 @@ // Store fence def SFENCE : I<0xAE, MRM7m, (ops), - "sfence", []>, TB, Requires<[HasSSE1]>; + "sfence", [(int_x86_sse_sfence)]>, TB, Requires<[HasSSE1]>; // MXCSR register def LDMXCSR : I<0xAE, MRM2m, (ops i32mem:$src), From evan.cheng at apple.com Tue Apr 11 13:05:09 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 11 Apr 2006 13:05:09 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td Message-ID: <200604111805.NAA13553@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrSSE.td updated: 1.75 -> 1.76 --- Log message: gcc lower SSE prefetch into generic prefetch intrinsic. Need to add support later. --- Diffs of the changes: (+4 -8) X86InstrSSE.td | 12 ++++-------- 1 files changed, 4 insertions(+), 8 deletions(-) Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.75 llvm/lib/Target/X86/X86InstrSSE.td:1.76 --- llvm/lib/Target/X86/X86InstrSSE.td:1.75 Tue Apr 11 12:35:57 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Tue Apr 11 13:04:57 2006 @@ -1517,17 +1517,13 @@ // Prefetching loads def PREFETCHT0 : PSI<0x18, MRM1m, (ops i8mem:$src), - "prefetcht0 $src", - [(int_x86_sse_prefetch addr:$src, 1)]>; + "prefetcht0 $src", []>; def PREFETCHT1 : PSI<0x18, MRM2m, (ops i8mem:$src), - "prefetcht1 $src", - [(int_x86_sse_prefetch addr:$src, 2)]>; + "prefetcht1 $src", []>; def PREFETCHT2 : PSI<0x18, MRM3m, (ops i8mem:$src), - "prefetcht2 $src", - [(int_x86_sse_prefetch addr:$src, 3)]>; + "prefetcht2 $src", []>; def PREFETCHTNTA : PSI<0x18, MRM0m, (ops i8mem:$src), - "prefetchtnta $src", - [(int_x86_sse_prefetch addr:$src, 0)]>; + "prefetchtnta $src", []>; // Non-temporal stores def MOVNTPSmr : PSI<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src), From evan.cheng at apple.com Tue Apr 11 13:05:10 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 11 Apr 2006 13:05:10 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/IntrinsicsX86.td Message-ID: <200604111805.NAA13557@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm: IntrinsicsX86.td updated: 1.17 -> 1.18 --- Log message: gcc lower SSE prefetch into generic prefetch intrinsic. Need to add support later. --- Diffs of the changes: (+0 -3) IntrinsicsX86.td | 3 --- 1 files changed, 3 deletions(-) Index: llvm/include/llvm/IntrinsicsX86.td diff -u llvm/include/llvm/IntrinsicsX86.td:1.17 llvm/include/llvm/IntrinsicsX86.td:1.18 --- llvm/include/llvm/IntrinsicsX86.td:1.17 Tue Apr 11 12:35:57 2006 +++ llvm/include/llvm/IntrinsicsX86.td Tue Apr 11 13:04:57 2006 @@ -139,9 +139,6 @@ // Cacheability support ops let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". - def int_x86_sse_prefetch : GCCBuiltin<"__builtin_ia32_prefetch">, - Intrinsic<[llvm_void_ty, llvm_ptr_ty, - llvm_int_ty], [IntrWriteMem]>; def int_x86_sse_movnt_ps : GCCBuiltin<"__builtin_ia32_movntps">, Intrinsic<[llvm_void_ty, llvm_ptr_ty, llvm_v4f32_ty], [IntrWriteMem]>; From lattner at cs.uiuc.edu Tue Apr 11 13:47:16 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 11 Apr 2006 13:47:16 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/README_ALTIVEC.txt Message-ID: <200604111847.NAA13921@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: README_ALTIVEC.txt updated: 1.19 -> 1.20 --- Log message: we have a shuffle instr, add an example. --- Diffs of the changes: (+6 -5) README_ALTIVEC.txt | 11 ++++++----- 1 files changed, 6 insertions(+), 5 deletions(-) Index: llvm/lib/Target/PowerPC/README_ALTIVEC.txt diff -u llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.19 llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.20 --- llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.19 Thu Apr 6 18:16:19 2006 +++ llvm/lib/Target/PowerPC/README_ALTIVEC.txt Tue Apr 11 13:47:03 2006 @@ -96,11 +96,6 @@ //===----------------------------------------------------------------------===// -We need an LLVM 'shuffle' instruction, that corresponds to the VECTOR_SHUFFLE -node. - -//===----------------------------------------------------------------------===// - We need a way to teach tblgen that some operands of an intrinsic are required to be constants. The verifier should enforce this constraint. @@ -133,4 +128,10 @@ of instructions (e.g. a vsldoi + vpkuhum). We should pattern match these, but there are a huge number of these. +Specific examples: + +C = vector_shuffle A, B, <0, 1, 2, 4> +-> t = vsldoi A, A, 12 +-> C = vsldoi A, B, 4 + //===----------------------------------------------------------------------===// From natebegeman at mac.com Tue Apr 11 14:29:33 2006 From: natebegeman at mac.com (Nate Begeman) Date: Tue, 11 Apr 2006 14:29:33 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Message-ID: <200604111929.OAA14135@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCRegisterInfo.cpp updated: 1.55 -> 1.56 --- Log message: Fix PR727: http://llvm.cs.uiuc.edu/PR727 , correctly handling large stack aligments on ppc --- Diffs of the changes: (+28 -32) PPCRegisterInfo.cpp | 60 ++++++++++++++++++++++++---------------------------- 1 files changed, 28 insertions(+), 32 deletions(-) Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.55 llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.56 --- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.55 Tue Apr 11 03:11:53 2006 +++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Tue Apr 11 14:29:21 2006 @@ -202,12 +202,10 @@ const MachineFrameInfo *MFI = MF.getFrameInfo(); unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); - // If frame pointers are forced, if there are variable sized stack objects, - // or if there is an object on the stack that requires more alignment than is - // normally provided, use a frame pointer. + // If frame pointers are forced, or if there are variable sized stack objects, + // use a frame pointer. // - return NoFramePointerElim || MFI->hasVarSizedObjects() || - MFI->getMaxAlignment() > TargetAlign; + return NoFramePointerElim || MFI->hasVarSizedObjects(); } void PPCRegisterInfo:: @@ -396,15 +394,26 @@ int NegNumbytes = -NumBytes; // Adjust stack pointer: r1 -= numbytes. - if (NumBytes <= 32768) { - BuildMI(MBB, MBBI, PPC::STWU, 3) - .addReg(PPC::R1).addSImm(-NumBytes).addReg(PPC::R1); + // If there is a preferred stack alignment, align R1 now + if (MaxAlign > TargetAlign) { + assert(isPowerOf2_32(MaxAlign) && MaxAlign < 32767 && "Invalid alignment!"); + assert(NumBytes <= 32768 && "Unhandled stack size and alignment combo!"); + BuildMI(MBB, MBBI, PPC::RLWINM, 4, PPC::R0) + .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31); + BuildMI(MBB, MBBI, PPC::SUBFIC,2,PPC::R0).addReg(PPC::R0).addSImm(MaxAlign); + BuildMI(MBB, MBBI, PPC::ADDI, 2, PPC::R0).addReg(PPC::R0) + .addSImm(NegNumbytes); + BuildMI(MBB, MBBI, PPC::STWUX, 3) + .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0); + } else if (NumBytes <= 32768) { + BuildMI(MBB, MBBI, PPC::STWU, 3).addReg(PPC::R1).addSImm(NegNumbytes) + .addReg(PPC::R1); } else { BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addSImm(NegNumbytes >> 16); - BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0) - .addReg(PPC::R0).addImm(NegNumbytes & 0xFFFF); - BuildMI(MBB, MBBI, PPC::STWUX, 3) - .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0); + BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0).addReg(PPC::R0) + .addImm(NegNumbytes & 0xFFFF); + BuildMI(MBB, MBBI, PPC::STWUX, 3).addReg(PPC::R1).addReg(PPC::R1) + .addReg(PPC::R0); } if (DebugInfo && DebugInfo->hasInfo()) { @@ -419,19 +428,6 @@ BuildMI(MBB, MBBI, PPC::DWARF_LABEL, 1).addSImm(LabelID); } - // If there is a preferred stack alignment, align R1 now - // FIXME: If this ever matters, this could be made more efficient by folding - // this into the code above, so that we don't issue two store+update - // instructions. - if (MaxAlign > TargetAlign) { - assert(isPowerOf2_32(MaxAlign) && MaxAlign < 32767 && "Invalid alignment!"); - BuildMI(MBB, MBBI, PPC::RLWINM, 4, PPC::R0) - .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31); - BuildMI(MBB, MBBI, PPC::SUBFIC, 2,PPC::R0).addReg(PPC::R0).addImm(MaxAlign); - BuildMI(MBB, MBBI, PPC::STWUX, 3) - .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0); - } - // If there is a frame pointer, copy R1 (SP) into R31 (FP) if (HasFP) { BuildMI(MBB, MBBI, PPC::STW, 3) @@ -446,8 +442,12 @@ assert(MBBI->getOpcode() == PPC::BLR && "Can only insert epilog into returning blocks"); + // Get alignment info so we know how to restore r1 + const MachineFrameInfo *MFI = MF.getFrameInfo(); + unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); + // Get the number of bytes allocated from the FrameInfo. - unsigned NumBytes = MF.getFrameInfo()->getStackSize(); + unsigned NumBytes = MFI->getStackSize(); unsigned GPRSize = 4; if (NumBytes != 0) { @@ -460,15 +460,11 @@ // The loaded (or persistent) stack pointer value is offseted by the 'stwu' // on entry to the function. Add this offset back now. - if (NumBytes < 32768) { + if (NumBytes < 32768 && TargetAlign >= MFI->getMaxAlignment()) { BuildMI(MBB, MBBI, PPC::ADDI, 2, PPC::R1) .addReg(PPC::R1).addSImm(NumBytes); } else { - BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addSImm(NumBytes >> 16); - BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0) - .addReg(PPC::R0).addImm(NumBytes & 0xFFFF); - BuildMI(MBB, MBBI, PPC::ADD4, 2, PPC::R1) - .addReg(PPC::R0).addReg(PPC::R1); + BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R1).addSImm(0).addReg(PPC::R1); } } } From natebegeman at mac.com Tue Apr 11 14:44:56 2006 From: natebegeman at mac.com (Nate Begeman) Date: Tue, 11 Apr 2006 14:44:56 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Message-ID: <200604111944.OAA14194@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCRegisterInfo.cpp updated: 1.56 -> 1.57 --- Log message: Fix SingleSource/UnitTests/Vector/sumarray-dbl --- Diffs of the changes: (+3 -4) PPCRegisterInfo.cpp | 7 +++---- 1 files changed, 3 insertions(+), 4 deletions(-) Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.56 llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.57 --- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.56 Tue Apr 11 14:29:21 2006 +++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Tue Apr 11 14:44:43 2006 @@ -397,12 +397,11 @@ // If there is a preferred stack alignment, align R1 now if (MaxAlign > TargetAlign) { assert(isPowerOf2_32(MaxAlign) && MaxAlign < 32767 && "Invalid alignment!"); - assert(NumBytes <= 32768 && "Unhandled stack size and alignment combo!"); + assert(isInt16(MaxAlign-NumBytes) && "Unhandled stack size and alignment!"); BuildMI(MBB, MBBI, PPC::RLWINM, 4, PPC::R0) .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31); - BuildMI(MBB, MBBI, PPC::SUBFIC,2,PPC::R0).addReg(PPC::R0).addSImm(MaxAlign); - BuildMI(MBB, MBBI, PPC::ADDI, 2, PPC::R0).addReg(PPC::R0) - .addSImm(NegNumbytes); + BuildMI(MBB, MBBI, PPC::SUBFIC,2,PPC::R0).addReg(PPC::R0) + .addSImm(MaxAlign-NumBytes); BuildMI(MBB, MBBI, PPC::STWUX, 3) .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0); } else if (NumBytes <= 32768) { From criswell at cs.uiuc.edu Tue Apr 11 15:24:51 2006 From: criswell at cs.uiuc.edu (John Criswell) Date: Tue, 11 Apr 2006 15:24:51 -0500 Subject: [llvm-commits] CVS: llvm/docs/HowToReleaseLLVM.html Message-ID: <200604112024.PAA19070@choi.cs.uiuc.edu> Changes in directory llvm/docs: HowToReleaseLLVM.html updated: 1.5 -> 1.6 --- Log message: First pass over Reid's document. Changed the order of operations so that more of the fine tuning is performed in the release branch. This should free up mainline sooner to resume development. Removed information on the special release Makefile targets as I've never used them for a release; Tanya is investigating their integration, and they can be re-added if she uses them. Added an outline for building the LLVM GCC binary distributions. I will be filling that section out later (but before the 1.7 release). --- Diffs of the changes: (+186 -42) HowToReleaseLLVM.html | 228 ++++++++++++++++++++++++++++++++++++++++---------- 1 files changed, 186 insertions(+), 42 deletions(-) Index: llvm/docs/HowToReleaseLLVM.html diff -u llvm/docs/HowToReleaseLLVM.html:1.5 llvm/docs/HowToReleaseLLVM.html:1.6 --- llvm/docs/HowToReleaseLLVM.html:1.5 Tue Apr 11 01:22:15 2006 +++ llvm/docs/HowToReleaseLLVM.html Tue Apr 11 15:24:28 2006 @@ -24,9 +24,21 @@

This document collects information about successfully releasing LLVM to the public. It is the release manager's guide to ensuring that a high quality build -of LLVM is released. Mostly, its just a bunch of reminders of things to do at +of LLVM is released. Mostly, it's just a bunch of reminders of things to do at release time so we don't inadvertently ship something that is utility deficient.

+ +

+There are three main tasks for building a release of LLVM: +

    +
  1. Create the LLVM source distribution.
    2. +
  2. Create the LLVM GCC source distribtuion.
    3. +
  3. Create a set of LLVM GCC binary distribtuions for each supported + platform. These binary distributions must include compiled versions + of the libraries found in llvm/runtime from the LLVM + source distribution created in Step 1.
    4. +
+

@@ -37,46 +49,143 @@
Process Overview
    +
  1. Update Documentation
  2. Merge Branches
    3. +
  3. Make LibDeps.txt
  4. Settle LLVM HEAD
    5. +
  5. Tag LLVM and Create the Release Branch
  6. Build LLVM
  7. Run 'make check'
  8. Run LLVM Test Suite
    9. -
  9. make LibDeps.txt
    10. -
  10. cvs tag
    11. -
  11. make dist
    12. -
  12. release
    13. +
  13. Build the LLVM Source Distributions
    14. +
  14. Build the LLVM GCC Binary Distribution
+
Update Documentation
+
+

+ Review the documentation and ensure that it is up to date. The Release Notes + must be updated to reflect bug fixes, new known issues, and changes in the + list of supported platforms. The Getting Started Guide should be updated to + reflect the new release version number tag avaiable from CVS and changes in + basic system requirements. +

+
+ +
Merge Branches
-

Merge any work done on branches intended for release into mainline. Work that -is not to be incorporated into the release should not be merged from the branch. +

+Merge any work done on branches intended for release into mainline. Finish and +commit all new features or bug fixes that are scheduled to go into the release. +Work that is not to be incorporated into the release should not be merged from +branchs or commited from developer's working directories. +

+ +

+From this point until the release branch is created, developers should +not +commit changes to the llvm and llvm-gcc CVS repositories unless it is a bug +fix for the release.

+
Make LibDeps.txt
+
+

Rebuild the LibDeps.txt target in utils/llvm-config. This + makes sure that the llvm-config utility remains relevant for the + release, reflecting any changes in the library dependencies.

+
+ + +
Settle CVS HEAD
-

Use the nightly test reports, and 'make check' (deja-gnu based tests) to - increase the quality of LLVM and ensure that merged branches have not - destabilized LLVM.

+

+ Use the nightly test reports and 'make check' (deja-gnu based tests) to + ensure that recent changes and merged branches have not destabilized LLVM. + Platforms which are used less often should be given special attention as they + are the most likely to break from commits from the previous step. +

+
+ + +
CVS Tag And Branch
+
+

Tag and branch the CVS HEAD using the following procedure:

+
    +
  1. + Request all developers to refrain from committing. Offenders get commit + rights taken away (temporarily). +
    2. + +
  2. + The Release Manager updates his/her llvm, llvm-test, and llvm-gcc source + trees with the + latest sources from mainline CVS. The Release Manage may want to consider + using a new working directory for this to keep current uncommitted work + separate from release work. +
    3. + +
  3. + The Release Manager tags his/her llvm, llvm-test, and llvm-gcc working + directories with + "ROOT_RELEASE_XX" where XX is the major and minor + release numbers (you can't have . in a cvs tag name). So, for Release 1.2, + XX=12 and for Release 1.10, XX=110. +
    4. + +
  4. + Immediately create cvs branches based on the ROOT_RELEASE_XX tag. The tag + should be "release_XX" (where XX matches that used for the ROOT_RELEASE_XX + tag). This is where the release distribution will be created. +
    5. + +
  5. + Advise developers they can work on CVS HEAD again. +
    6. + +
  6. + The Release Manager and any developers working on the release should switch + to the release branch (as all changes to the release will now be done in + the branch). The easiest way to do this is to grab another working copy + using the following commands: + +

    + cvs -d <CVS Repository> co -r release_XX llvm
    + cvs -d <CVS Repository> co -r release_XX llvm-test
    + cvs -d <CVS Repository> co -r release_XX llvm-gcc
    +

    +
Build LLVM
-

Build both debug and release versions of LLVM on all platforms. Ensure - build is warning and error free on each platform.

+

+ Build both debug and release (optimized) versions of LLVM on all + platforms. Ensure the build is warning and error free on each platform. +

+ +

+ Build a new version of the LLVM GCC front-end after building the LLVM tools. + Once that is complete, go back to the LLVM source tree and build and install + the llvm/runtime libraries. +

Run 'make check'

Run make check and ensure there are no unexpected failures. If - there are, resolve the failures and go back to step 2. + there are, resolve the failures, commit them back into the release branch, + and restart testing by re-building LLVM. +

+ +

Ensure that 'make check' passes on all platforms for all targets. If certain failures cannot be resolved before release time, determine if marking them XFAIL is appropriate. If not, fix the bug and go back. The test suite must @@ -88,48 +197,82 @@

LLVM Test Suite

Run the llvm-test suite and ensure there are no unacceptable failures. - If there are, resolve the failures and go back to step 2. The test suite - should be run in Nightly Test mode. All tests must pass. If they do not, - investigate and go back to settling CVS HEAD.

+ If there are, resolve the failures and go back to + re-building LLVM. The test suite + should be run in Nightly Test mode. All tests must pass.
-
Make LibDeps.txt
+
Build the LLVM Source Distributions
-

Rebuild the LibDeps.txt target in utils/llvm-config. This - makes sure that the llvm-config utility remains relevant for the - release, reflecting any changes in the library dependencies.

-
+

+ Create source distributions for LLVM, LLVM GCC, and the LLVM Test Suite by + exporting the source + from CVS and archiving it. This can be done with the following commands: +

- -
CVS Tag And Branch
-
-

Tag and branch the CVS HEAD using the following procedure:

-
    -
  1. Request all developers to refrain from committing. Offenders get commit - rights taken away (temporarily).
    2. -
  2. Tag the cvs HEAD with "ROOT_RELEASE_XX" where XX is the major and minor - release numbers (you can't have . in a cvs tag name). So, for Release 1.2, - XX=12 and for Release 1.10, XX=110.
    3. -
  3. Immediately create a cvs branch based on the ROOT_RELEASE tag. This is - where the release distribution will be created.
    4. -
  4. Advise developers they can work on CVS HEAD again.
    5. -
  5. Ensure all subsequent building and fixing is done on this branch.
    6. -
+

+ cvs -d <CVS Repository> export -r release_XX llvm
+ cvs -d <CVS Repository> export -r release_XX llvm-test
+ cvs -d <CVS Repository> export -r release_XX llvm-gcc
+ mkdir cfrontend; mv llvm-gcc cfrontend/src
+ tar -cvf - llvm | gzip > llvm-X.X.tar.gz
+ tar -cvf - llvm-test | gzip > llvm-test-X.X.tar.gz
+ tar -cvf - cfrontend/src | gzip > cfrontend-X.X.source.tar.gz
+

- -
Run 'make dist'
-
-

Build the distribution, ensuring it is installable and working. This is a + +

+ + +
Build the LLVM GCC Binary Distribution
+
+

+ Creating the LLVM GCC binary distribution requires performing the following + steps for each supported platform: +

+ +
    +
  1. + Build the LLVM GCC front-end. The LLVM GCC front-end must be installed in + a directory named cfrontend/<platform>/llvm-gcc. For + example, the Sparc/Solaris directory is named + cfrontend/sparc/llvm-gcc. +
    2. + +
  2. + Build the libraries in llvm/runtime and install them into the + created LLVM GCC installation directory. +
    3. + +
  3. + For systems with non-distributable header files (e.g. Solaris), manually + remove header files that the GCC build process has "fixed." This process + is admittedly painful, but not as bad as it looks; these header files are + almost always easily identifiable with simple grep expressions and are + installed in only a few directories in the GCC installation directory. +
    4. + +
  4. + Add the copyright files and header file fix script. +
    5. + +
  5. + Archive and compress the installation directory. These can be found in + previous releases of the LLVM-GCC front-end. +
    6. +
+
Release
@@ -145,6 +288,7 @@ forget to update the version number, documentation, etc. in the llvm.spec file.

+-->
@@ -157,7 +301,7 @@ Reid Spencer
The LLVM Compiler Infrastructure
- Last modified: $Date: 2006/04/11 06:22:15 $ + Last modified: $Date: 2006/04/11 20:24:28 $ From lattner at cs.uiuc.edu Tue Apr 11 16:30:54 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 11 Apr 2006 16:30:54 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGNodes.h Message-ID: <200604112130.QAA14755@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: SelectionDAGNodes.h updated: 1.127 -> 1.128 --- Log message: new dag node --- Diffs of the changes: (+8 -0) SelectionDAGNodes.h | 8 ++++++++ 1 files changed, 8 insertions(+) Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.127 llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.128 --- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.127 Sat Apr 8 17:16:01 2006 +++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h Tue Apr 11 16:30:42 2006 @@ -113,6 +113,14 @@ // UNDEF - An undefined node UNDEF, + + /// FORMAL_ARGUMENTS(CC#, ISVARARG) - This node represents the formal + /// arguments for a function. CC# is a Constant value indicating the + /// calling convention of the function, and ISVARARG is a flag that + /// indicates whether the function is varargs or not. This node has one + /// result value for each incoming argument, and is typically custom + /// legalized. + FORMAL_ARGUMENTS, // EXTRACT_ELEMENT - This is used to get the first or second (determined by // a Constant, which is required to be operand #1), element of the aggregate From reid at x10sys.com Tue Apr 11 16:59:49 2006 From: reid at x10sys.com (Reid Spencer) Date: Tue, 11 Apr 2006 16:59:49 -0500 Subject: [llvm-commits] CVS: llvm/docs/HowToReleaseLLVM.html Message-ID: <200604112159.QAA15041@zion.cs.uiuc.edu> Changes in directory llvm/docs: HowToReleaseLLVM.html updated: 1.6 -> 1.7 --- Log message: Add the contents of my email about distribution targets as a new section. Attribute John as an author. --- Diffs of the changes: (+170 -3) HowToReleaseLLVM.html | 173 +++++++++++++++++++++++++++++++++++++++++++++++++- 1 files changed, 170 insertions(+), 3 deletions(-) Index: llvm/docs/HowToReleaseLLVM.html diff -u llvm/docs/HowToReleaseLLVM.html:1.6 llvm/docs/HowToReleaseLLVM.html:1.7 --- llvm/docs/HowToReleaseLLVM.html:1.6 Tue Apr 11 15:24:28 2006 +++ llvm/docs/HowToReleaseLLVM.html Tue Apr 11 16:59:37 2006 @@ -12,9 +12,11 @@
  1. Introduction
  2. Release Process
    3. +
  3. Distribution Make Targets
-

Written by Reid Spencer

+

Written by Reid Spencer, + John Criswell

@@ -273,7 +275,6 @@
Release

Release the distribution tarball to the public. This consists of generating @@ -291,6 +292,172 @@ --> +

Distribution Make Targets
+ + +
Overview
+
+

The first thing you need to understand is that there are multiple make +targets to support this feature. Here's an overview, we'll delve into the +details later.

+
    +
  • distdir - builds the distribution directory from which the + distribution will be packaged
    • +
  • dist - builds each of the distribution tarballs (tar.gz, + tar.bzip2, .zip). These can be built individually as well, with separate + targets.
    • +
  • dist-check - this is identical to dist but includes a + check on the distribution that ensures the tarball can: unpack successfully, + compile correctly, pass 'make check', and pass 'make clean'.
    • +
  • dist-clean- this just does a normal clean but also cleans up the + stuff generated by the other three dist targets (above).
    • +
+

Okay, that's the basic functionality. When making a release, we want to +ensure that the tree you build the distribution from passes +dist-check. Beyond fixing the usual bugs, there is generally one +impediment to making the release in this fashion: missing files. The +dist-check process guards against that possibility. It will either +fail and that failure will indicate what's missing, or it will succeed +meaning that it has proved that the tarballs can actually succeed in +building LLVM correctly and that it passes make check.

+ +
distdir
+

This target builds the distribution directory which is the directory from +which the tarballs are generated. The distribution directory has the same +name as the release, e.g. LLVM-1.7). This target goes through the following +process: +

    +
  1. First, if there was an old distribution directory (for the current + release), it is removed in its entirety and you see Removing old + LLVM-1.7
    2. +
  2. Second, it issues a make all ENABLE_OPTIMIZED=3D1 to ensure + that the everything in your tree can be built in release mode. Often times + there are discrepancies in building between debug and release modes so it + enforces release mode first. If that fails, the distdir target + fails too. This is preceded by the message Making 'all' to verify + build.
    3. +
  3. Next, it traverses your source tree and copies it to a new directory + that has the name of the release (LLVM-M.m in our current case). + This is the directory that will get tar'd. It contains all the software + that needs to be in the distribution. During the copying process, it omits + generated files, CVS directories, and any other "cruft" that's in your + build tree. This is done to eliminate the possibility of huge distribution + tarballs that include useless or irrelevant stuff in them. This is the + trickiest part of making the distribution. Done manually you will either + include stuff that shouldn't be in the distribution or exclude stuff that + should. This step is preceded by the message Building Distribution + Directory LLVM-1.7
    4. +
  4. The distribution directory is then traversed and all CVS or + .svn directories are removed. You see: Eliminating CVS/.svn + directories from distribution
    5. +
  5. The recursive dist-hook target is executed. This gives each + directory a chance to modify the distribution in some way (more on this + below).
    6. +
  6. The distribution directory is traversed and the correct file + permissions and modes are set based on the type of file.
    7. +
+

To control the process of making the distribution directory correctly, +each Makefile can utilize two features:

+
    +
  1. EXTRA_DIST - this make variable specifies which files + it should distribute. By default, all source files are automatically + included for distribution as well as certain well known files + (see DistAlways variable in Makefile.rules for details). Each Makefile + specifies, via the EXTRA_DIST variable, which additional files + need to be distributed. Only those files that are needed to build LLVM + should be added to EXTRA_DIST. EXTRA_DIST contains a + list of file or directory names that should be distributed. For example, + the top level Makefile contains + EXTRA_DIST := test llvm.spec include. + This means that in addition to regular things that are distributed at the + top level (CREDITS.txt, LICENSE.txt, etc.) the distribution should + contain the entire test and include directories as well + as the llvm.spec file.
    2. +
  2. dist-hook - this make target can be used to alter the + content of the distribution directory. For example, in the top level + Makefile there is some logic to eliminate files in the include + subtree that are generated by the configure script. These should not be + distributed. Similarly, any dist-hook target found in any + directory can add or remove or modify things just before it gets packaged. + Any transformation is permitted. Generally, not much is needed. +
+

You will see various messages if things go wrong:

+
    +
  1. During the copying process, any files that are missing will be flagged + with: ===== WARNING: Distribution Source 'dir/file' Not Found! + These must be corrected by either adding the file or removing it from + EXTRA_DIST. +
  2. If you build the distribution with VERBOSE=1, then you might + also see: Skipping non-existent 'dir/file' in certain cases where + its okay to skip the file.
    3. +
  3. The target can fail if any of the things it does fail. Error messages + should indicate what went wrong.
    4. +
+ +
dist
+

This target does exactly what distdir target does, but also +includes assembling the tarballs. There are actually four related targets +here:

+

    +
  • dist-gzip: package the gzipped distribution tar + file. The distribution directory is packaged into a single file ending in + .tar.gz which is gzip compressed.
    • +
  • dist-bzip2: package the bzip2 distribution tar file. + The distribution directory is packaged into a single file ending in + .tar.bzip2 which is bzip2 compressed.
    • +
  • dist-zip: package the zip distribution file. The + distribution directory is packaged into a single file ending in + .zip which is zip compressed.
    • +
  • dist: does all three, dist-gzip, dist-bzip2, + dist-zip
    • +
+ +
dist-check
+

This target checks the distribution. The basic idea is that it unpacks the +distribution tarball and ensures that it can build. It takes the following +actions:

+
    +
  1. It depends on the dist-gzip target which, if it hasn't already + been built, builds the gzip tar bundle (see dist and distdir above).
    2. +
  2. removes any pre-existing _distcheckdir at the top level.
    3. +
  3. creates a new _distcheckdir directory at the top level.
    4. +
  4. creates a build subdirectory and an install + subdirectory under _distcheckdir.
    5. +
  5. unzips and untars the release tarball into _distcheckdir, + creating LLVM-1.7 directory (from the tarball).
    6. +
  6. in the build subdirectory, it configures with appropriate options to build + from the unpacked source tarball into the build directory with + installation in the install directory.
    7. +
  7. runs make all
    8. +
  8. runs make check
    9. +
  9. runs make install
    10. +
  10. runs make uninstall
    11. +
  11. runs make dist
    12. +
  12. runs make clean
    13. +
  13. runs make dist-clean
    14. +
+

If it can pass all that, the distribution will be deemed distribution +worth y and you will see:

+

===== LLVM-1.7.tar.gz Ready For Distribution =====
+

This means the tarball should then be tested on other platforms and have the +nightly test run against it. If those all pass, THEN it is ready for +distribution.

+

+A note about disk space: using dist-check will easily triple the +amount of disk space your build tree is using. You might want to check +available space before you begin.

+ +
dist-clean
+

dist-clean

+

In addition to doing a normal clean, this target will clean up the +files and directories created by the distribution targets. In particular the +distribution directory (LLVM-X.X), check directory +(_distcheckdir), and the various tarballs will be removed. You do +this after the release has shipped and you no longer need this stuff in your +build tree.

+
+ +
Reid Spencer
The LLVM Compiler Infrastructure
- Last modified: $Date: 2006/04/11 20:24:28 $ + Last modified: $Date: 2006/04/11 21:59:37 $
From reid at x10sys.com Tue Apr 11 17:02:29 2006 From: reid at x10sys.com (Reid Spencer) Date: Tue, 11 Apr 2006 17:02:29 -0500 Subject: [llvm-commits] CVS: llvm/docs/HowToReleaseLLVM.html Message-ID: <200604112202.RAA15162@zion.cs.uiuc.edu> Changes in directory llvm/docs: HowToReleaseLLVM.html updated: 1.7 -> 1.8 --- Log message: Don't overload anchor names, silly browser's can't handle it. --- Diffs of the changes: (+3 -3) HowToReleaseLLVM.html | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) Index: llvm/docs/HowToReleaseLLVM.html diff -u llvm/docs/HowToReleaseLLVM.html:1.7 llvm/docs/HowToReleaseLLVM.html:1.8 --- llvm/docs/HowToReleaseLLVM.html:1.7 Tue Apr 11 16:59:37 2006 +++ llvm/docs/HowToReleaseLLVM.html Tue Apr 11 17:02:18 2006 @@ -12,7 +12,7 @@
  1. Introduction
  2. Release Process
    3. -
  3. Distribution Make Targets
    4. +
  4. Distribution Targets

Written by Reid Spencer, @@ -292,7 +292,7 @@ --> -

Distribution Make Targets
+
Distribution Targets
Overview
@@ -468,7 +468,7 @@ Reid Spencer
The LLVM Compiler Infrastructure
- Last modified: $Date: 2006/04/11 21:59:37 $ + Last modified: $Date: 2006/04/11 22:02:18 $ From evan.cheng at apple.com Tue Apr 11 17:28:37 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 11 Apr 2006 17:28:37 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/IntrinsicsX86.td Message-ID: <200604112228.RAA15307@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm: IntrinsicsX86.td updated: 1.18 -> 1.19 --- Log message: Added __builtin_ia32_storelv4si, __builtin_ia32_movqv4si, __builtin_ia32_loadlv4si, __builtin_ia32_loaddqu, __builtin_ia32_storedqu. --- Diffs of the changes: (+11 -0) IntrinsicsX86.td | 11 +++++++++++ 1 files changed, 11 insertions(+) Index: llvm/include/llvm/IntrinsicsX86.td diff -u llvm/include/llvm/IntrinsicsX86.td:1.18 llvm/include/llvm/IntrinsicsX86.td:1.19 --- llvm/include/llvm/IntrinsicsX86.td:1.18 Tue Apr 11 13:04:57 2006 +++ llvm/include/llvm/IntrinsicsX86.td Tue Apr 11 17:28:25 2006 @@ -269,6 +269,8 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse2_loadu_pd : GCCBuiltin<"__builtin_ia32_loadupd">, Intrinsic<[llvm_v2f64_ty, llvm_ptr_ty], [IntrReadMem]>; + def int_x86_sse2_loadu_dq : GCCBuiltin<"__builtin_ia32_loaddqu">, + Intrinsic<[llvm_v16i8_ty, llvm_ptr_ty], [IntrReadMem]>; } // SIMD store ops @@ -276,6 +278,12 @@ def int_x86_sse2_storeu_pd : GCCBuiltin<"__builtin_ia32_storeupd">, Intrinsic<[llvm_void_ty, llvm_ptr_ty, llvm_v2f64_ty], [IntrWriteMem]>; + def int_x86_sse2_storeu_dq : GCCBuiltin<"__builtin_ia32_storedqu">, + Intrinsic<[llvm_void_ty, llvm_ptr_ty, + llvm_v16i8_ty], [IntrWriteMem]>; + def int_x86_sse2_storel_dq : GCCBuiltin<"__builtin_ia32_storelv4si">, + Intrinsic<[llvm_void_ty, llvm_ptr_ty, + llvm_v4i32_ty], [IntrWriteMem]>; } // Cacheability support ops @@ -302,6 +310,9 @@ def int_x86_sse2_packuswb_128 : GCCBuiltin<"__builtin_ia32_packuswb128">, Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; + // FIXME: Temporary workaround since 2-wide shuffle is broken. + def int_x86_sse2_movl_dq : GCCBuiltin<"__builtin_ia32_movqv4si">, + Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>; def int_x86_sse2_movmskpd : GCCBuiltin<"__builtin_ia32_movmskpd">, Intrinsic<[llvm_int_ty, llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_pmovmskb_128 : GCCBuiltin<"__builtin_ia32_pmovmskb128">, From evan.cheng at apple.com Tue Apr 11 17:28:38 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 11 Apr 2006 17:28:38 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td Message-ID: <200604112228.RAA15311@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrSSE.td updated: 1.76 -> 1.77 --- Log message: Added __builtin_ia32_storelv4si, __builtin_ia32_movqv4si, __builtin_ia32_loadlv4si, __builtin_ia32_loaddqu, __builtin_ia32_storedqu. --- Diffs of the changes: (+21 -2) X86InstrSSE.td | 23 +++++++++++++++++++++-- 1 files changed, 21 insertions(+), 2 deletions(-) Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.76 llvm/lib/Target/X86/X86InstrSSE.td:1.77 --- llvm/lib/Target/X86/X86InstrSSE.td:1.76 Tue Apr 11 13:04:57 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Tue Apr 11 17:28:25 2006 @@ -724,6 +724,14 @@ def MOVUPDmr : PDI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src), "movupd {$src, $dst|$dst, $src}", [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>; +def MOVDQUrm : I<0x6F, MRMSrcMem, (ops VR128:$dst, i128mem:$src), + "movdqu {$src, $dst|$dst, $src}", + [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>, + XS, Requires<[HasSSE2]>; +def MOVDQUmr : I<0x7F, MRMDestMem, (ops i128mem:$dst, VR128:$src), + "movdqu {$src, $dst|$dst, $src}", + [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>, + XS, Requires<[HasSSE2]>; let isTwoAddress = 1 in { def MOVLPSrm : PSI<0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2), @@ -1657,6 +1665,16 @@ MOVS_shuffle_mask)))]>; } +// Store / copy lower 64-bits of a XMM register. +def MOVLQ128mr : PDI<0xD6, MRMDestMem, (ops i64mem:$dst, VR128:$src), + "movq {$src, $dst|$dst, $src}", + [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>; + +// FIXME: Temporary workaround since 2-wide shuffle is broken. +def MOVLQ128rr : PDI<0xD6, MRMSrcReg, (ops VR128:$dst, VR128:$src), + "movq {$src, $dst|$dst, $src}", + [(set VR128:$dst, (int_x86_sse2_movl_dq VR128:$src))]>; + // Move to lower bits of a VR128 and zeroing upper bits. // Loading from memory automatically zeroing upper bits. def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (ops VR128:$dst, f32mem:$src), @@ -1672,9 +1690,10 @@ [(set VR128:$dst, (v4i32 (X86zexts2vec (loadi32 addr:$src))))]>; def MOVZQI2PQIrm : PDI<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src), - "movd {$src, $dst|$dst, $src}", + "movq {$src, $dst|$dst, $src}", [(set VR128:$dst, - (v2i64 (X86zexts2vec (loadi64 addr:$src))))]>; + (bc_v2i64 (v2f64 (X86zexts2vec + (loadf64 addr:$src)))))]>; //===----------------------------------------------------------------------===// // Non-Instruction Patterns From reid at x10sys.com Tue Apr 11 22:07:14 2006 From: reid at x10sys.com (Reid Spencer) Date: Tue, 11 Apr 2006 22:07:14 -0500 Subject: [llvm-commits] CVS: llvm/Makefile.rules Message-ID: <200604120307.WAA16958@zion.cs.uiuc.edu> Changes in directory llvm: Makefile.rules updated: 1.360 -> 1.361 --- Log message: Remove extraneous building in target dist-check. There is no reason that a distribution should need to be able to make a distribution so eliminate the "make dist" from the list of targets attempted. --- Diffs of the changes: (+0 -2) Makefile.rules | 2 -- 1 files changed, 2 deletions(-) Index: llvm/Makefile.rules diff -u llvm/Makefile.rules:1.360 llvm/Makefile.rules:1.361 --- llvm/Makefile.rules:1.360 Mon Apr 10 11:46:04 2006 +++ llvm/Makefile.rules Tue Apr 11 22:07:02 2006 @@ -1502,8 +1502,6 @@ $(MAKE) check && \ $(MAKE) install && \ $(MAKE) uninstall && \ - $(MAKE) dist && \ - $(MAKE) clean && \ $(MAKE) dist-clean && \ $(EchoCmd) ===== $(DistTarGZip) Ready For Distribution ===== From lattner at cs.uiuc.edu Tue Apr 11 22:24:58 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 11 Apr 2006 22:24:58 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/Generic/2006-04-11-vecload.ll Message-ID: <200604120324.WAA17282@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/Generic: 2006-04-11-vecload.ll added (r1.1) --- Log message: new testcase --- Diffs of the changes: (+12 -0) 2006-04-11-vecload.ll | 12 ++++++++++++ 1 files changed, 12 insertions(+) Index: llvm/test/Regression/CodeGen/Generic/2006-04-11-vecload.ll diff -c /dev/null llvm/test/Regression/CodeGen/Generic/2006-04-11-vecload.ll:1.1 *** /dev/null Tue Apr 11 22:24:56 2006 --- llvm/test/Regression/CodeGen/Generic/2006-04-11-vecload.ll Tue Apr 11 22:24:46 2006 *************** *** 0 **** --- 1,12 ---- + ; RUN: llvm-as < %s | llc + + ; The vload was getting memoized to the previous scalar load! + + void %VertexProgram2() { + %xFloat0.688 = load float* null ; [#uses=0] + %loadVector37.712 = load <4 x float>* null ; <<4 x float>> [#uses=1] + %inFloat3.713 = insertelement <4 x float> %loadVector37.712, float 0.000000e+00, uint 3 ; <<4 x float>> [#uses=1] + store <4 x float> %inFloat3.713, <4 x float>* null + unreachable + } + From lattner at cs.uiuc.edu Tue Apr 11 22:25:53 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 11 Apr 2006 22:25:53 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Message-ID: <200604120325.WAA17367@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAG.cpp updated: 1.297 -> 1.298 --- Log message: Don't memoize vloads in the load map! Don't memoize them anywhere here, let getNode do it. This fixes CodeGen/Generic/2006-04-11-vecload.ll --- Diffs of the changes: (+0 -2) SelectionDAG.cpp | 2 -- 1 files changed, 2 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.297 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.298 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.297 Sat Apr 8 17:22:57 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue Apr 11 22:25:41 2006 @@ -1508,8 +1508,6 @@ SDOperand SelectionDAG::getVecLoad(unsigned Count, MVT::ValueType EVT, SDOperand Chain, SDOperand Ptr, SDOperand SV) { - SDNode *&N = Loads[std::make_pair(Ptr, std::make_pair(Chain, EVT))]; - if (N) return SDOperand(N, 0); std::vector Ops; Ops.reserve(5); Ops.push_back(Chain); From lattner at cs.uiuc.edu Tue Apr 11 23:18:48 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 11 Apr 2006 23:18:48 -0500 Subject: [llvm-commits] CVS: llvm-www/OpenProjects.html Message-ID: <200604120418.XAA17847@zion.cs.uiuc.edu> Changes in directory llvm-www: OpenProjects.html updated: 1.12 -> 1.13 --- Log message: Nate went and did one of the projects, so remove it. The skeleton backend is no more. --- Diffs of the changes: (+1 -17) OpenProjects.html | 18 +----------------- 1 files changed, 1 insertion(+), 17 deletions(-) Index: llvm-www/OpenProjects.html diff -u llvm-www/OpenProjects.html:1.12 llvm-www/OpenProjects.html:1.13 --- llvm-www/OpenProjects.html:1.12 Thu Mar 16 13:02:22 2006 +++ llvm-www/OpenProjects.html Tue Apr 11 23:18:36 2006 @@ -304,8 +304,6 @@
  1. Improve the instruction selectors.
    2. -
  2. Implement support for the "switch" instruction without requiring the - lower-switches pass.
  3. Implement interprocedural register allocation. The CallGraphSCCPass can be used to implement a bottom-up analysis that will determine the *actual* registers clobbered by a function. Use the pass to fine tune register usage @@ -314,20 +312,6 @@ (ARM? MIPS? MMIX?)
    4. -
  4. Improve the usefulness and utility of the Skeleton target backend: -
      -
    • Convert the non-functional Skeleton target to become an abstract machine - target (choose some simple instructions, a register set, etc). This will - become a much more useful example of a backend since it would be a simple - but functional backend. Examples of such architectures include MIX, - MMIX, DLX, - or come up with your own!
      • -
    • Use the new Skeleton backend in the Interpreter: compile LLVM to Skeleton - target, and then interpret that code instead of LLVM. Performance win would - be the primary goal, as the number of registers would be a small constant - instead of unbounded, for example.
      • -
@@ -381,7 +365,7 @@ src="http://www.w3.org/Icons/valid-html401" alt="Valid HTML 4.01!"> LLVM Compiler Infrastructure
- Last modified: $Date: 2006/03/16 19:02:22 $ + Last modified: $Date: 2006/04/12 04:18:36 $ From evan.cheng at apple.com Wed Apr 12 00:20:37 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 12 Apr 2006 00:20:37 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/IntrinsicsX86.td Message-ID: <200604120520.AAA18233@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm: IntrinsicsX86.td updated: 1.19 -> 1.20 --- Log message: Various SSE2 conversion intrinsics --- Diffs of the changes: (+24 -0) IntrinsicsX86.td | 24 ++++++++++++++++++++++++ 1 files changed, 24 insertions(+) Index: llvm/include/llvm/IntrinsicsX86.td diff -u llvm/include/llvm/IntrinsicsX86.td:1.19 llvm/include/llvm/IntrinsicsX86.td:1.20 --- llvm/include/llvm/IntrinsicsX86.td:1.19 Tue Apr 11 17:28:25 2006 +++ llvm/include/llvm/IntrinsicsX86.td Wed Apr 12 00:20:24 2006 @@ -265,6 +265,30 @@ llvm_int_ty], [IntrNoMem]>; } +// Conversion ops +let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". + def int_x86_sse2_cvtdq2pd : GCCBuiltin<"__builtin_ia32_cvtdq2pd">, + Intrinsic<[llvm_v2f64_ty, llvm_v4i32_ty], [IntrNoMem]>; + def int_x86_sse2_cvtdq2ps : GCCBuiltin<"__builtin_ia32_cvtdq2ps">, + Intrinsic<[llvm_v4f32_ty, llvm_v4i32_ty], [IntrNoMem]>; + def int_x86_sse2_cvtpd2dq : GCCBuiltin<"__builtin_ia32_cvtpd2dq">, + Intrinsic<[llvm_v4i32_ty, llvm_v2f64_ty], [IntrNoMem]>; + def int_x86_sse2_cvttpd2dq : GCCBuiltin<"__builtin_ia32_cvttpd2dq">, + Intrinsic<[llvm_v4i32_ty, llvm_v2f64_ty], [IntrNoMem]>; + def int_x86_sse2_cvtpd2ps : GCCBuiltin<"__builtin_ia32_cvtpd2ps">, + Intrinsic<[llvm_v4f32_ty, llvm_v2f64_ty], [IntrNoMem]>; + def int_x86_sse2_cvtps2dq : GCCBuiltin<"__builtin_ia32_cvtps2dq">, + Intrinsic<[llvm_v4i32_ty, llvm_v4f32_ty], [IntrNoMem]>; + def int_x86_sse2_cvttps2dq : GCCBuiltin<"__builtin_ia32_cvttps2dq">, + Intrinsic<[llvm_v4i32_ty, llvm_v4f32_ty], [IntrNoMem]>; + def int_x86_sse2_cvtps2pd : GCCBuiltin<"__builtin_ia32_cvtps2pd">, + Intrinsic<[llvm_v2f64_ty, llvm_v4f32_ty], [IntrNoMem]>; + def int_x86_sse2_cvtsd2si : GCCBuiltin<"__builtin_ia32_cvtsd2si">, + Intrinsic<[llvm_int_ty, llvm_v2f64_ty], [IntrNoMem]>; + def int_x86_sse2_cvttsd2si : GCCBuiltin<"__builtin_ia32_cvttsd2si">, + Intrinsic<[llvm_int_ty, llvm_v2f64_ty], [IntrNoMem]>; +} + // SIMD load ops let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse2_loadu_pd : GCCBuiltin<"__builtin_ia32_loadupd">, From evan.cheng at apple.com Wed Apr 12 00:20:36 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 12 Apr 2006 00:20:36 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td Message-ID: <200604120520.AAA18229@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrSSE.td updated: 1.77 -> 1.78 --- Log message: Various SSE2 conversion intrinsics --- Diffs of the changes: (+94 -39) X86InstrSSE.td | 133 ++++++++++++++++++++++++++++++++++++++++----------------- 1 files changed, 94 insertions(+), 39 deletions(-) Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.77 llvm/lib/Target/X86/X86InstrSSE.td:1.78 --- llvm/lib/Target/X86/X86InstrSSE.td:1.77 Tue Apr 11 17:28:25 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Wed Apr 12 00:20:24 2006 @@ -524,6 +524,23 @@ [(set FR64:$dst, (fextend (loadf32 addr:$src)))]>, XS, Requires<[HasSSE2]>; +// Aliases to match intrinsics which expect XMM operand(s). +def Int_CVTTSD2SIrr: SDI<0x2C, MRMSrcReg, (ops R32:$dst, VR128:$src), + "cvttsd2si {$src, $dst|$dst, $src}", + [(set R32:$dst, (int_x86_sse2_cvttsd2si VR128:$src))]>; +def Int_CVTTSD2SIrm: SDI<0x2C, MRMSrcMem, (ops R32:$dst, f128mem:$src), + "cvttsd2si {$src, $dst|$dst, $src}", + [(set R32:$dst, (int_x86_sse2_cvttsd2si + (load addr:$src)))]>; + +def CVTSD2SIrr: SDI<0x2D, MRMSrcReg, (ops R32:$dst, VR128:$src), + "cvtsd2si {$src, $dst|$dst, $src}", + [(set R32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>; +def CVTSD2SIrm: SDI<0x2D, MRMSrcMem, (ops R32:$dst, f128mem:$src), + "cvtsd2si {$src, $dst|$dst, $src}", + [(set R32:$dst, (int_x86_sse2_cvtsd2si + (load addr:$src)))]>; + // Comparison instructions let isTwoAddress = 1 in { def CMPSSrr : SSI<0xC2, MRMSrcReg, @@ -800,62 +817,100 @@ } // Conversion instructions -def CVTPI2PSr : PSI<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src), +def CVTPI2PSrr : PSI<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src), "cvtpi2ps {$src, $dst|$dst, $src}", []>; -def CVTPI2PSm : PSI<0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src), +def CVTPI2PSrm : PSI<0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src), "cvtpi2ps {$src, $dst|$dst, $src}", []>; -def CVTPI2PDr : PDI<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src), +def CVTPI2PDrr : PDI<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src), "cvtpi2pd {$src, $dst|$dst, $src}", []>; -def CVTPI2PDm : PDI<0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src), +def CVTPI2PDrm : PDI<0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src), "cvtpi2pd {$src, $dst|$dst, $src}", []>; // SSE2 instructions without OpSize prefix -def CVTDQ2PSr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src), - "cvtdq2ps {$src, $dst|$dst, $src}", []>, TB, - Requires<[HasSSE2]>; -def CVTDQ2PSm : I<0x5B, MRMSrcMem, (ops VR128:$dst, i128mem:$src), - "cvtdq2ps {$src, $dst|$dst, $src}", []>, TB, - Requires<[HasSSE2]>; +def CVTDQ2PSrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src), + "cvtdq2ps {$src, $dst|$dst, $src}", + [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>, + TB, Requires<[HasSSE2]>; +def CVTDQ2PSrm : I<0x5B, MRMSrcMem, (ops VR128:$dst, i128mem:$src), + "cvtdq2ps {$src, $dst|$dst, $src}", + [(set VR128:$dst, (int_x86_sse2_cvtdq2ps + (load addr:$src)))]>, + TB, Requires<[HasSSE2]>; // SSE2 instructions with XS prefix -def CVTDQ2PDr : I<0xE6, MRMSrcReg, (ops VR128:$dst, VR64:$src), - "cvtdq2pd {$src, $dst|$dst, $src}", []>, - XS, Requires<[HasSSE2]>; -def CVTDQ2PDm : I<0xE6, MRMSrcMem, (ops VR128:$dst, i64mem:$src), - "cvtdq2pd {$src, $dst|$dst, $src}", []>, - XS, Requires<[HasSSE2]>; +def CVTDQ2PDrr : I<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src), + "cvtdq2pd {$src, $dst|$dst, $src}", + [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>, + XS, Requires<[HasSSE2]>; +def CVTDQ2PDrm : I<0xE6, MRMSrcMem, (ops VR128:$dst, i64mem:$src), + "cvtdq2pd {$src, $dst|$dst, $src}", + [(set VR128:$dst, (int_x86_sse2_cvtdq2pd + (load addr:$src)))]>, + XS, Requires<[HasSSE2]>; -def CVTPS2PIr : PSI<0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src), +def CVTPS2PIrr : PSI<0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src), "cvtps2pi {$src, $dst|$dst, $src}", []>; -def CVTPS2PIm : PSI<0x2D, MRMSrcMem, (ops VR64:$dst, f64mem:$src), +def CVTPS2PIrm : PSI<0x2D, MRMSrcMem, (ops VR64:$dst, f64mem:$src), "cvtps2pi {$src, $dst|$dst, $src}", []>; -def CVTPD2PIr : PDI<0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src), +def CVTPD2PIrr : PDI<0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src), "cvtpd2pi {$src, $dst|$dst, $src}", []>; -def CVTPD2PIm : PDI<0x2D, MRMSrcMem, (ops VR64:$dst, f128mem:$src), +def CVTPD2PIrm : PDI<0x2D, MRMSrcMem, (ops VR64:$dst, f128mem:$src), "cvtpd2pi {$src, $dst|$dst, $src}", []>; -def CVTPS2DQr : PDI<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src), - "cvtps2dq {$src, $dst|$dst, $src}", []>; -def CVTPS2DQm : PDI<0x5B, MRMSrcMem, (ops VR128:$dst, f128mem:$src), - "cvtps2dq {$src, $dst|$dst, $src}", []>; +def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src), + "cvtps2dq {$src, $dst|$dst, $src}", + [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>; +def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (ops VR128:$dst, f128mem:$src), + "cvtps2dq {$src, $dst|$dst, $src}", + [(set VR128:$dst, (int_x86_sse2_cvtps2dq + (load addr:$src)))]>; +// SSE2 packed instructions with XS prefix +def CVTTPS2DQrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src), + "cvttps2dq {$src, $dst|$dst, $src}", + [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))]>, + XS, Requires<[HasSSE2]>; +def CVTTPS2DQrm : I<0x5B, MRMSrcMem, (ops VR128:$dst, f128mem:$src), + "cvttps2dq {$src, $dst|$dst, $src}", + [(set VR128:$dst, (int_x86_sse2_cvttps2dq + (load addr:$src)))]>, + XS, Requires<[HasSSE2]>; + // SSE2 packed instructions with XD prefix -def CVTPD2DQr : SDI<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src), - "cvtpd2dq {$src, $dst|$dst, $src}", []>; -def CVTPD2DQm : SDI<0xE6, MRMSrcMem, (ops VR128:$dst, f128mem:$src), - "cvtpd2dq {$src, $dst|$dst, $src}", []>; +def CVTPD2DQrr : I<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src), + "cvtpd2dq {$src, $dst|$dst, $src}", + [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>, + XD, Requires<[HasSSE2]>; +def CVTPD2DQrm : I<0xE6, MRMSrcMem, (ops VR128:$dst, f128mem:$src), + "cvtpd2dq {$src, $dst|$dst, $src}", + [(set VR128:$dst, (int_x86_sse2_cvtpd2dq + (load addr:$src)))]>, + XD, Requires<[HasSSE2]>; +def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src), + "cvttpd2dq {$src, $dst|$dst, $src}", + [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>; +def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (ops VR128:$dst, f128mem:$src), + "cvttpd2dq {$src, $dst|$dst, $src}", + [(set VR128:$dst, (int_x86_sse2_cvttpd2dq + (load addr:$src)))]>; // SSE2 instructions without OpSize prefix -def CVTPS2PDr : I<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src), - "cvtps2pd {$src, $dst|$dst, $src}", []>, TB, - Requires<[HasSSE2]>; -def CVTPS2PDm : I<0x5A, MRMSrcReg, (ops VR128:$dst, f64mem:$src), - "cvtps2pd {$src, $dst|$dst, $src}", []>, TB, - Requires<[HasSSE2]>; - -def CVTPD2PSr : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src), - "cvtpd2ps {$src, $dst|$dst, $src}", []>; -def CVTPD2PSm : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, f128mem:$src), - "cvtpd2ps {$src, $dst|$dst, $src}", []>; +def CVTPS2PDrr : I<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src), + "cvtps2pd {$src, $dst|$dst, $src}", + [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>, + TB, Requires<[HasSSE2]>; +def CVTPS2PDrm : I<0x5A, MRMSrcReg, (ops VR128:$dst, f64mem:$src), + "cvtps2pd {$src, $dst|$dst, $src}", + [(set VR128:$dst, (int_x86_sse2_cvtps2pd + (load addr:$src)))]>, + TB, Requires<[HasSSE2]>; + +def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src), + "cvtpd2ps {$src, $dst|$dst, $src}", + [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>; +def CVTPD2PSrm : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, f128mem:$src), + "cvtpd2ps {$src, $dst|$dst, $src}", + [(set VR128:$dst, (int_x86_sse2_cvtpd2ps + (load addr:$src)))]>; // Arithmetic let isTwoAddress = 1 in { From lattner at cs.uiuc.edu Wed Apr 12 11:21:07 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 12 Apr 2006 11:21:07 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp Message-ID: <200604121621.LAA00988@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.361 -> 1.362 SelectionDAG.cpp updated: 1.298 -> 1.299 SelectionDAGISel.cpp updated: 1.221 -> 1.222 --- Log message: Implement support for the formal_arguments node. To get this, targets shouldcustom legalize it and remove their XXXTargetLowering::LowerArguments overload --- Diffs of the changes: (+128 -3) LegalizeDAG.cpp | 11 +++- SelectionDAG.cpp | 1 SelectionDAGISel.cpp | 119 +++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 128 insertions(+), 3 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.361 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.362 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.361 Tue Apr 11 01:33:39 2006 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Apr 12 11:20:43 2006 @@ -826,7 +826,13 @@ Result = DAG.UpdateNodeOperands(Result, Ops); } break; - + + case ISD::FORMAL_ARGUMENTS: + // The only option for this is to custom lower it. + Result = TLI.LowerOperation(Result, DAG); + assert(Result.Val && "Target didn't custom lower ISD::FORMAL_ARGUMENTS!"); + break; + case ISD::BUILD_VECTOR: switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { default: assert(0 && "This action is not supported yet!"); @@ -2782,7 +2788,7 @@ Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0), Node->getOperand(1), Node->getOperand(2)); break; - + case ISD::TRUNCATE: switch (getTypeAction(Node->getOperand(0).getValueType())) { case Legal: @@ -4057,7 +4063,6 @@ } } - /// ExpandOp - Expand the specified SDOperand into its two component pieces /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the /// LegalizeNodes map is filled in for any results that are not expanded, the Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.298 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.299 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.298 Tue Apr 11 22:25:41 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Apr 12 11:20:43 2006 @@ -2714,6 +2714,7 @@ case ISD::MERGE_VALUES: return "mergevalues"; case ISD::INLINEASM: return "inlineasm"; case ISD::HANDLENODE: return "handlenode"; + case ISD::FORMAL_ARGUMENTS: return "formal_arguments"; // Unary operators case ISD::FABS: return "fabs"; Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.221 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.222 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.221 Sat Apr 8 17:22:57 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Apr 12 11:20:43 2006 @@ -2230,6 +2230,125 @@ DAG.getSrcValue(I.getOperand(2)))); } +/// TargetLowering::LowerArguments - This is the default LowerArguments +/// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all +/// targets are migrated to using FORMAL_ARGUMENTS, this hook should be removed. +std::vector +TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { + // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node. + std::vector Ops; + Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy())); + Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy())); + + // Add one result value for each formal argument. + std::vector RetVals; + for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { + MVT::ValueType VT = getValueType(I->getType()); + + switch (getTypeAction(VT)) { + default: assert(0 && "Unknown type action!"); + case Legal: + RetVals.push_back(VT); + break; + case Promote: + RetVals.push_back(getTypeToTransformTo(VT)); + break; + case Expand: + if (VT != MVT::Vector) { + // If this is a large integer, it needs to be broken up into small + // integers. Figure out what the destination type is and how many small + // integers it turns into. + MVT::ValueType NVT = getTypeToTransformTo(VT); + unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT); + for (unsigned i = 0; i != NumVals; ++i) + RetVals.push_back(NVT); + } else { + // Otherwise, this is a vector type. We only support legal vectors + // right now. + unsigned NumElems = cast(I->getType())->getNumElements(); + const Type *EltTy = cast(I->getType())->getElementType(); + + // Figure out if there is a Packed type corresponding to this Vector + // type. If so, convert to the packed type. + MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems); + if (TVT != MVT::Other && isTypeLegal(TVT)) { + RetVals.push_back(TVT); + } else { + assert(0 && "Don't support illegal by-val vector arguments yet!"); + } + } + break; + } + } + + // Create the node. + SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, RetVals, Ops).Val; + + // Set up the return result vector. + Ops.clear(); + unsigned i = 0; + for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { + MVT::ValueType VT = getValueType(I->getType()); + + switch (getTypeAction(VT)) { + default: assert(0 && "Unknown type action!"); + case Legal: + Ops.push_back(SDOperand(Result, i++)); + break; + case Promote: { + SDOperand Op(Result, i++); + if (MVT::isInteger(VT)) { + unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext + : ISD::AssertZext; + Op = DAG.getNode(AssertOp, Op.getValueType(), Op, DAG.getValueType(VT)); + Op = DAG.getNode(ISD::TRUNCATE, VT, Op); + } else { + assert(MVT::isFloatingPoint(VT) && "Not int or FP?"); + Op = DAG.getNode(ISD::FP_ROUND, VT, Op); + } + Ops.push_back(Op); + break; + } + case Expand: + if (VT != MVT::Vector) { + // If this is a large integer, it needs to be reassembled from small + // integers. Figure out what the source elt type is and how many small + // integers it is. + MVT::ValueType NVT = getTypeToTransformTo(VT); + unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT); + if (NumVals == 2) { + SDOperand Lo = SDOperand(Result, i++); + SDOperand Hi = SDOperand(Result, i++); + + if (!isLittleEndian()) + std::swap(Lo, Hi); + + Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi)); + } else { + // Value scalarized into many values. Unimp for now. + assert(0 && "Cannot expand i64 -> i16 yet!"); + } + } else { + // Otherwise, this is a vector type. We only support legal vectors + // right now. + unsigned NumElems = cast(I->getType())->getNumElements(); + const Type *EltTy = cast(I->getType())->getElementType(); + + // Figure out if there is a Packed type corresponding to this Vector + // type. If so, convert to the packed type. + MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems); + if (TVT != MVT::Other && isTypeLegal(TVT)) { + Ops.push_back(SDOperand(Result, i++)); + } else { + assert(0 && "Don't support illegal by-val vector arguments yet!"); + } + } + break; + } + } + return Ops; +} + // It is always conservatively correct for llvm.returnaddress and // llvm.frameaddress to return 0. std::pair From lattner at cs.uiuc.edu Wed Apr 12 11:21:24 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 12 Apr 2006 11:21:24 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetLowering.h Message-ID: <200604121621.LAA00999@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/Target: TargetLowering.h updated: 1.67 -> 1.68 --- Log message: Provide a default impl of LowerArguments --- Diffs of the changes: (+1 -1) TargetLowering.h | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/include/llvm/Target/TargetLowering.h diff -u llvm/include/llvm/Target/TargetLowering.h:1.67 llvm/include/llvm/Target/TargetLowering.h:1.68 --- llvm/include/llvm/Target/TargetLowering.h:1.67 Tue Apr 4 12:21:22 2006 +++ llvm/include/llvm/Target/TargetLowering.h Wed Apr 12 11:21:12 2006 @@ -524,7 +524,7 @@ /// LowerArguments - This hook must be implemented to indicate how we should /// lower the arguments for the specified function, into the specified DAG. virtual std::vector - LowerArguments(Function &F, SelectionDAG &DAG) = 0; + LowerArguments(Function &F, SelectionDAG &DAG); /// LowerCallTo - This hook lowers an abstract call to a function into an /// actual call. This returns a pair of operands. The first element is the From evan.cheng at apple.com Wed Apr 12 11:33:30 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 12 Apr 2006 11:33:30 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <200604121633.LAA01334@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.362 -> 1.363 --- Log message: Vector type promotion for ISD::LOAD and ISD::SELECT --- Diffs of the changes: (+23 -9) LegalizeDAG.cpp | 32 +++++++++++++++++++++++--------- 1 files changed, 23 insertions(+), 9 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.362 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.363 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.362 Wed Apr 12 11:20:43 2006 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Apr 12 11:33:18 2006 @@ -1256,25 +1256,36 @@ MVT::ValueType VT = Node->getValueType(0); Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); - Tmp2 = Result.getValue(0); - Tmp3 = Result.getValue(1); + Tmp3 = Result.getValue(0); + Tmp4 = Result.getValue(1); switch (TLI.getOperationAction(Node->getOpcode(), VT)) { default: assert(0 && "This action is not supported yet!"); case TargetLowering::Legal: break; case TargetLowering::Custom: - Tmp1 = TLI.LowerOperation(Tmp2, DAG); + Tmp1 = TLI.LowerOperation(Tmp3, DAG); if (Tmp1.Val) { - Tmp2 = LegalizeOp(Tmp1); - Tmp3 = LegalizeOp(Tmp1.getValue(1)); + Tmp3 = LegalizeOp(Tmp1); + Tmp4 = LegalizeOp(Tmp1.getValue(1)); } break; + case TargetLowering::Promote: { + // Only promote a load of vector type to another. + assert(MVT::isVector(VT) && "Cannot promote this load!"); + // Change base type to a different vector type. + MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); + + Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, Node->getOperand(2)); + Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1)); + Tmp4 = LegalizeOp(Tmp1.getValue(1)); + break; + } } // Since loads produce two values, make sure to remember that we // legalized both of them. - AddLegalizedOperand(SDOperand(Node, 0), Tmp2); - AddLegalizedOperand(SDOperand(Node, 1), Tmp3); - return Op.ResNo ? Tmp3 : Tmp2; + AddLegalizedOperand(SDOperand(Node, 0), Tmp3); + AddLegalizedOperand(SDOperand(Node, 1), Tmp4); + return Op.ResNo ? Tmp4 : Tmp3; } case ISD::EXTLOAD: case ISD::SEXTLOAD: @@ -1755,7 +1766,10 @@ MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); unsigned ExtOp, TruncOp; - if (MVT::isInteger(Tmp2.getValueType())) { + if (MVT::isVector(Tmp2.getValueType())) { + ExtOp = ISD::BIT_CONVERT; + TruncOp = ISD::BIT_CONVERT; + } else if (MVT::isInteger(Tmp2.getValueType())) { ExtOp = ISD::ANY_EXTEND; TruncOp = ISD::TRUNCATE; } else { From reid at x10sys.com Wed Apr 12 11:44:27 2006 From: reid at x10sys.com (Reid Spencer) Date: Wed, 12 Apr 2006 11:44:27 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGNodes.h Message-ID: <200604121644.LAA01443@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: SelectionDAGNodes.h updated: 1.128 -> 1.129 --- Log message: Make sure both member variables are initialized in the default constructor for SDOperand. This gets rid of numerous warnings in lib/CodeGen and lib/Target when compiled with GCC 4.0.2 --- Diffs of the changes: (+1 -1) SelectionDAGNodes.h | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.128 llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.129 --- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.128 Tue Apr 11 16:30:42 2006 +++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h Wed Apr 12 11:44:15 2006 @@ -609,7 +609,7 @@ SDNode *Val; // The node defining the value we are using. unsigned ResNo; // Which return value of the node we are using. - SDOperand() : Val(0) {} + SDOperand() : Val(0), ResNo(0) {} SDOperand(SDNode *val, unsigned resno) : Val(val), ResNo(resno) {} bool operator==(const SDOperand &O) const { From sabre at nondot.org Wed Apr 12 11:46:19 2006 From: sabre at nondot.org (Chris Lattner) Date: Wed, 12 Apr 2006 11:46:19 -0500 (CDT) Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGNodes.h In-Reply-To: <200604121644.LAA01443@zion.cs.uiuc.edu> References: <200604121644.LAA01443@zion.cs.uiuc.edu> Message-ID: On Wed, 12 Apr 2006, Reid Spencer wrote: > Make sure both member variables are initialized in the default constructor > for SDOperand. This gets rid of numerous warnings in lib/CodeGen and > lib/Target when compiled with GCC 4.0.2 It's lame when we have to sacrifice (even small amounts of) performance to work around buggy compiler warnings. :( -Chris > Diffs of the changes: (+1 -1) > > SelectionDAGNodes.h | 2 +- > 1 files changed, 1 insertion(+), 1 deletion(-) > > > Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h > diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.128 llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.129 > --- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.128 Tue Apr 11 16:30:42 2006 > +++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h Wed Apr 12 11:44:15 2006 > @@ -609,7 +609,7 @@ > SDNode *Val; // The node defining the value we are using. > unsigned ResNo; // Which return value of the node we are using. > > - SDOperand() : Val(0) {} > + SDOperand() : Val(0), ResNo(0) {} > SDOperand(SDNode *val, unsigned resno) : Val(val), ResNo(resno) {} > > bool operator==(const SDOperand &O) const { > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > -Chris -- http://nondot.org/sabre/ http://llvm.org/ From lattner at cs.uiuc.edu Wed Apr 12 11:49:27 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 12 Apr 2006 11:49:27 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/vxor-canonicalize.ll Message-ID: <200604121649.LAA01542@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/PowerPC: vxor-canonicalize.ll added (r1.1) --- Log message: new testcase --- Diffs of the changes: (+9 -0) vxor-canonicalize.ll | 9 +++++++++ 1 files changed, 9 insertions(+) Index: llvm/test/Regression/CodeGen/PowerPC/vxor-canonicalize.ll diff -c /dev/null llvm/test/Regression/CodeGen/PowerPC/vxor-canonicalize.ll:1.1 *** /dev/null Wed Apr 12 11:49:26 2006 --- llvm/test/Regression/CodeGen/PowerPC/vxor-canonicalize.ll Wed Apr 12 11:49:16 2006 *************** *** 0 **** --- 1,9 ---- + ; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vxor | wc -l | grep 1 + ; There should be exactly one vxor here, not two. + + void %test(<4 x float>* %P1, <4 x int>* %P2) { + store <4 x float> zeroinitializer, <4 x float>* %P1 + store <4 x int> zeroinitializer, <4 x int>* %P2 + ret void + } + From lattner at cs.uiuc.edu Wed Apr 12 11:53:40 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 12 Apr 2006 11:53:40 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCInstrAltivec.td Message-ID: <200604121653.LAA01620@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.144 -> 1.145 PPCInstrAltivec.td updated: 1.47 -> 1.48 --- Log message: Ensure that zero vectors are always v4i32, which forces them to CSE with each other. This implements CodeGen/PowerPC/vxor-canonicalize.ll --- Diffs of the changes: (+13 -8) PPCISelLowering.cpp | 14 +++++++++++--- PPCInstrAltivec.td | 7 ++----- 2 files changed, 13 insertions(+), 8 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.144 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.145 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.144 Mon Apr 10 20:38:39 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Wed Apr 12 11:53:28 2006 @@ -923,11 +923,19 @@ case ISD::BUILD_VECTOR: // If this is a case we can't handle, return null and let the default // expansion code take care of it. If we CAN select this case, return Op. - - // See if this is all zeros. + // FIXME: We should handle splat(-0.0), and other cases here. - if (ISD::isBuildVectorAllZeros(Op.Val)) + + // See if this is all zeros. + if (ISD::isBuildVectorAllZeros(Op.Val)) { + // Canonicalize all zero vectors to be v4i32. + if (Op.getValueType() != MVT::v4i32) { + SDOperand Z = DAG.getConstant(0, MVT::i32); + Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z); + Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z); + } return Op; + } if (PPC::get_VSPLI_elt(Op.Val, 1, DAG).Val || // vspltisb PPC::get_VSPLI_elt(Op.Val, 2, DAG).Val || // vspltish Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.47 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.48 --- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.47 Sat Apr 8 01:46:53 2006 +++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td Wed Apr 12 11:53:28 2006 @@ -521,7 +521,7 @@ def V_SET0 : VXForm_setzero<1220, (ops VRRC:$vD), "vxor $vD, $vD, $vD", VecFP, - [(set VRRC:$vD, (v4f32 immAllZerosV))]>; + [(set VRRC:$vD, (v4i32 immAllZerosV))]>; } //===----------------------------------------------------------------------===// @@ -544,9 +544,6 @@ def : Pat<(v16i8 (undef)), (v16i8 (IMPLICIT_DEF_VRRC))>; def : Pat<(v8i16 (undef)), (v8i16 (IMPLICIT_DEF_VRRC))>; def : Pat<(v4i32 (undef)), (v4i32 (IMPLICIT_DEF_VRRC))>; -def : Pat<(v16i8 immAllZerosV), (v16i8 (V_SET0))>; -def : Pat<(v8i16 immAllZerosV), (v8i16 (V_SET0))>; -def : Pat<(v4i32 immAllZerosV), (v4i32 (V_SET0))>; // Loads. def : Pat<(v16i8 (load xoaddr:$src)), (v16i8 (LVX xoaddr:$src))>; @@ -637,7 +634,7 @@ (v8i16 (VANDC VRRC:$A, VRRC:$B))>; def : Pat<(fmul VRRC:$vA, VRRC:$vB), - (VMADDFP VRRC:$vA, VRRC:$vB, (V_SET0))>; + (VMADDFP VRRC:$vA, VRRC:$vB, (v4i32 (V_SET0)))>; // Fused multiply add and multiply sub for packed float. These are represented // separately from the real instructions above, for operations that must have From lattner at cs.uiuc.edu Wed Apr 12 11:57:51 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 12 Apr 2006 11:57:51 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/vxor-canonicalize.ll Message-ID: <200604121657.LAA01664@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/PowerPC: vxor-canonicalize.ll updated: 1.1 -> 1.2 --- Log message: Make this test more interesting by checking that the 0.0 used to implement vector fmul gets cse'd also. --- Diffs of the changes: (+7 -3) vxor-canonicalize.ll | 10 +++++++--- 1 files changed, 7 insertions(+), 3 deletions(-) Index: llvm/test/Regression/CodeGen/PowerPC/vxor-canonicalize.ll diff -u llvm/test/Regression/CodeGen/PowerPC/vxor-canonicalize.ll:1.1 llvm/test/Regression/CodeGen/PowerPC/vxor-canonicalize.ll:1.2 --- llvm/test/Regression/CodeGen/PowerPC/vxor-canonicalize.ll:1.1 Wed Apr 12 11:49:16 2006 +++ llvm/test/Regression/CodeGen/PowerPC/vxor-canonicalize.ll Wed Apr 12 11:57:39 2006 @@ -1,7 +1,11 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vxor | wc -l | grep 1 -; There should be exactly one vxor here, not two. +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 --enable-unsafe-fp-math | grep vxor | wc -l | grep 1 +; There should be exactly one vxor here. -void %test(<4 x float>* %P1, <4 x int>* %P2) { +void %test(<4 x float>* %P1, <4 x int>* %P2, <4 x float>* %P3) { + %tmp = load <4 x float>* %P3 + %tmp3 = load <4 x float>* %P1 + %tmp4 = mul <4 x float> %tmp, %tmp3 + store <4 x float> %tmp4, <4 x float>* %P3 store <4 x float> zeroinitializer, <4 x float>* %P1 store <4 x int> zeroinitializer, <4 x int>* %P2 ret void From lattner at cs.uiuc.edu Wed Apr 12 12:01:24 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 12 Apr 2006 12:01:24 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/buildvec_canonicalize.ll vxor-canonicalize.ll Message-ID: <200604121701.MAA01804@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/PowerPC: buildvec_canonicalize.ll added (r1.1) vxor-canonicalize.ll (r1.2) removed --- Log message: Rename this file --- Diffs of the changes: (+13 -0) buildvec_canonicalize.ll | 13 +++++++++++++ 1 files changed, 13 insertions(+) Index: llvm/test/Regression/CodeGen/PowerPC/buildvec_canonicalize.ll diff -c /dev/null llvm/test/Regression/CodeGen/PowerPC/buildvec_canonicalize.ll:1.1 *** /dev/null Wed Apr 12 12:01:21 2006 --- llvm/test/Regression/CodeGen/PowerPC/buildvec_canonicalize.ll Wed Apr 12 12:01:11 2006 *************** *** 0 **** --- 1,13 ---- + ; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 --enable-unsafe-fp-math | grep vxor | wc -l | grep 1 + ; There should be exactly one vxor here. + + void %test(<4 x float>* %P1, <4 x int>* %P2, <4 x float>* %P3) { + %tmp = load <4 x float>* %P3 + %tmp3 = load <4 x float>* %P1 + %tmp4 = mul <4 x float> %tmp, %tmp3 + store <4 x float> %tmp4, <4 x float>* %P3 + store <4 x float> zeroinitializer, <4 x float>* %P1 + store <4 x int> zeroinitializer, <4 x int>* %P2 + ret void + } + From evan.cheng at apple.com Wed Apr 12 12:12:47 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 12 Apr 2006 12:12:47 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86InstrSSE.td Message-ID: <200604121712.MAA01944@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.162 -> 1.163 X86InstrSSE.td updated: 1.78 -> 1.79 --- Log message: Promote v4i32, v8i16, v16i8 load to v2i64 load. --- Diffs of the changes: (+41 -57) X86ISelLowering.cpp | 7 +--- X86InstrSSE.td | 91 +++++++++++++++++++++------------------------------- 2 files changed, 41 insertions(+), 57 deletions(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.162 llvm/lib/Target/X86/X86ISelLowering.cpp:1.163 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.162 Mon Apr 10 19:19:04 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Wed Apr 12 12:12:36 2006 @@ -302,10 +302,6 @@ setOperationAction(ISD::SUB, MVT::v4i32, Legal); setOperationAction(ISD::MUL, MVT::v2f64, Legal); setOperationAction(ISD::LOAD, MVT::v2f64, Legal); - setOperationAction(ISD::LOAD, MVT::v16i8, Legal); - setOperationAction(ISD::LOAD, MVT::v8i16, Legal); - setOperationAction(ISD::LOAD, MVT::v4i32, Legal); - setOperationAction(ISD::LOAD, MVT::v2i64, Legal); setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); @@ -329,7 +325,10 @@ VT != (unsigned)MVT::v2i64; VT++) { setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote); AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v2i64); + setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Promote); + AddPromotedToType (ISD::LOAD, (MVT::ValueType)VT, MVT::v2i64); } + setOperationAction(ISD::LOAD, MVT::v2i64, Legal); setOperationAction(ISD::SELECT, MVT::v2i64, Custom); setOperationAction(ISD::SELECT, MVT::v2f64, Custom); } Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.78 llvm/lib/Target/X86/X86InstrSSE.td:1.79 --- llvm/lib/Target/X86/X86InstrSSE.td:1.78 Wed Apr 12 00:20:24 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Wed Apr 12 12:12:36 2006 @@ -531,7 +531,7 @@ def Int_CVTTSD2SIrm: SDI<0x2C, MRMSrcMem, (ops R32:$dst, f128mem:$src), "cvttsd2si {$src, $dst|$dst, $src}", [(set R32:$dst, (int_x86_sse2_cvttsd2si - (load addr:$src)))]>; + (loadv2f64 addr:$src)))]>; def CVTSD2SIrr: SDI<0x2D, MRMSrcReg, (ops R32:$dst, VR128:$src), "cvtsd2si {$src, $dst|$dst, $src}", @@ -539,7 +539,7 @@ def CVTSD2SIrm: SDI<0x2D, MRMSrcMem, (ops R32:$dst, f128mem:$src), "cvtsd2si {$src, $dst|$dst, $src}", [(set R32:$dst, (int_x86_sse2_cvtsd2si - (load addr:$src)))]>; + (loadv2f64 addr:$src)))]>; // Comparison instructions let isTwoAddress = 1 in { @@ -834,7 +834,7 @@ def CVTDQ2PSrm : I<0x5B, MRMSrcMem, (ops VR128:$dst, i128mem:$src), "cvtdq2ps {$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_cvtdq2ps - (load addr:$src)))]>, + (bc_v4i32 (loadv2i64 addr:$src))))]>, TB, Requires<[HasSSE2]>; // SSE2 instructions with XS prefix @@ -845,7 +845,7 @@ def CVTDQ2PDrm : I<0xE6, MRMSrcMem, (ops VR128:$dst, i64mem:$src), "cvtdq2pd {$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_cvtdq2pd - (load addr:$src)))]>, + (bc_v4i32 (loadv2i64 addr:$src))))]>, XS, Requires<[HasSSE2]>; def CVTPS2PIrr : PSI<0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src), @@ -863,7 +863,7 @@ def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (ops VR128:$dst, f128mem:$src), "cvtps2dq {$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_cvtps2dq - (load addr:$src)))]>; + (loadv4f32 addr:$src)))]>; // SSE2 packed instructions with XS prefix def CVTTPS2DQrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src), "cvttps2dq {$src, $dst|$dst, $src}", @@ -872,7 +872,7 @@ def CVTTPS2DQrm : I<0x5B, MRMSrcMem, (ops VR128:$dst, f128mem:$src), "cvttps2dq {$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_cvttps2dq - (load addr:$src)))]>, + (loadv4f32 addr:$src)))]>, XS, Requires<[HasSSE2]>; // SSE2 packed instructions with XD prefix @@ -883,7 +883,7 @@ def CVTPD2DQrm : I<0xE6, MRMSrcMem, (ops VR128:$dst, f128mem:$src), "cvtpd2dq {$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_cvtpd2dq - (load addr:$src)))]>, + (loadv2f64 addr:$src)))]>, XD, Requires<[HasSSE2]>; def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src), "cvttpd2dq {$src, $dst|$dst, $src}", @@ -891,7 +891,7 @@ def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (ops VR128:$dst, f128mem:$src), "cvttpd2dq {$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_cvttpd2dq - (load addr:$src)))]>; + (loadv2f64 addr:$src)))]>; // SSE2 instructions without OpSize prefix def CVTPS2PDrr : I<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src), @@ -901,7 +901,7 @@ def CVTPS2PDrm : I<0x5A, MRMSrcReg, (ops VR128:$dst, f64mem:$src), "cvtps2pd {$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_cvtps2pd - (load addr:$src)))]>, + (loadv4f32 addr:$src)))]>, TB, Requires<[HasSSE2]>; def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src), @@ -910,7 +910,7 @@ def CVTPD2PSrm : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, f128mem:$src), "cvtpd2ps {$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_cvtpd2ps - (load addr:$src)))]>; + (loadv2f64 addr:$src)))]>; // Arithmetic let isTwoAddress = 1 in { @@ -1226,10 +1226,10 @@ "movdqa {$src, $dst|$dst, $src}", []>; def MOVDQArm : PDI<0x6F, MRMSrcMem, (ops VR128:$dst, i128mem:$src), "movdqa {$src, $dst|$dst, $src}", - [(set VR128:$dst, (loadv4i32 addr:$src))]>; + [(set VR128:$dst, (loadv2i64 addr:$src))]>; def MOVDQAmr : PDI<0x7F, MRMDestMem, (ops i128mem:$dst, VR128:$src), "movdqa {$src, $dst|$dst, $src}", - [(store (v4i32 VR128:$src), addr:$dst)]>; + [(store (v2i64 VR128:$src), addr:$dst)]>; // 128-bit Integer Arithmetic let isTwoAddress = 1 in { @@ -1394,7 +1394,8 @@ (ops VR128:$dst, i128mem:$src1, i8imm:$src2), "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}", [(set VR128:$dst, (v4i32 (vector_shuffle - (load addr:$src1), (undef), + (bc_v4i32 (loadv2i64 addr:$src1)), + (undef), PSHUFD_shuffle_mask:$src2)))]>; // SSE2 with ImmT == Imm8 and XS prefix. @@ -1409,7 +1410,8 @@ (ops VR128:$dst, i128mem:$src1, i8imm:$src2), "pshufhw {$src2, $src1, $dst|$dst, $src1, $src2}", [(set VR128:$dst, (v8i16 (vector_shuffle - (load addr:$src1), (undef), + (bc_v8i16 (loadv2i64 addr:$src1)), + (undef), PSHUFHW_shuffle_mask:$src2)))]>, XS, Requires<[HasSSE2]>; @@ -1425,7 +1427,8 @@ (ops VR128:$dst, i128mem:$src1, i32i8imm:$src2), "pshuflw {$src2, $src1, $dst|$dst, $src1, $src2}", [(set VR128:$dst, (v8i16 (vector_shuffle - (load addr:$src1), (undef), + (bc_v8i16 (loadv2i64 addr:$src1)), + (undef), PSHUFLW_shuffle_mask:$src2)))]>, XD, Requires<[HasSSE2]>; @@ -1440,7 +1443,8 @@ (ops VR128:$dst, VR128:$src1, i128mem:$src2), "punpcklbw {$src2, $dst|$dst, $src2}", [(set VR128:$dst, - (v16i8 (vector_shuffle VR128:$src1, (load addr:$src2), + (v16i8 (vector_shuffle VR128:$src1, + (bc_v16i8 (loadv2i64 addr:$src2)), UNPCKL_shuffle_mask)))]>; def PUNPCKLWDrr : PDI<0x61, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), @@ -1452,7 +1456,8 @@ (ops VR128:$dst, VR128:$src1, i128mem:$src2), "punpcklwd {$src2, $dst|$dst, $src2}", [(set VR128:$dst, - (v8i16 (vector_shuffle VR128:$src1, (load addr:$src2), + (v8i16 (vector_shuffle VR128:$src1, + (bc_v8i16 (loadv2i64 addr:$src2)), UNPCKL_shuffle_mask)))]>; def PUNPCKLDQrr : PDI<0x62, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), @@ -1464,7 +1469,8 @@ (ops VR128:$dst, VR128:$src1, i128mem:$src2), "punpckldq {$src2, $dst|$dst, $src2}", [(set VR128:$dst, - (v4i32 (vector_shuffle VR128:$src1, (load addr:$src2), + (v4i32 (vector_shuffle VR128:$src1, + (bc_v4i32 (loadv2i64 addr:$src2)), UNPCKL_shuffle_mask)))]>; def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), @@ -1476,7 +1482,8 @@ (ops VR128:$dst, VR128:$src1, i128mem:$src2), "punpcklqdq {$src2, $dst|$dst, $src2}", [(set VR128:$dst, - (v2i64 (vector_shuffle VR128:$src1, (load addr:$src2), + (v2i64 (vector_shuffle VR128:$src1, + (loadv2i64 addr:$src2), UNPCKL_shuffle_mask)))]>; def PUNPCKHBWrr : PDI<0x68, MRMSrcReg, @@ -1489,7 +1496,8 @@ (ops VR128:$dst, VR128:$src1, i128mem:$src2), "punpckhbw {$src2, $dst|$dst, $src2}", [(set VR128:$dst, - (v16i8 (vector_shuffle VR128:$src1, (load addr:$src2), + (v16i8 (vector_shuffle VR128:$src1, + (bc_v16i8 (loadv2i64 addr:$src2)), UNPCKH_shuffle_mask)))]>; def PUNPCKHWDrr : PDI<0x69, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), @@ -1501,7 +1509,8 @@ (ops VR128:$dst, VR128:$src1, i128mem:$src2), "punpckhwd {$src2, $dst|$dst, $src2}", [(set VR128:$dst, - (v8i16 (vector_shuffle VR128:$src1, (load addr:$src2), + (v8i16 (vector_shuffle VR128:$src1, + (bc_v8i16 (loadv2i64 addr:$src2)), UNPCKH_shuffle_mask)))]>; def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), @@ -1513,7 +1522,8 @@ (ops VR128:$dst, VR128:$src1, i128mem:$src2), "punpckhdq {$src2, $dst|$dst, $src2}", [(set VR128:$dst, - (v4i32 (vector_shuffle VR128:$src1, (load addr:$src2), + (v4i32 (vector_shuffle VR128:$src1, + (bc_v4i32 (loadv2i64 addr:$src2)), UNPCKH_shuffle_mask)))]>; def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), @@ -1525,7 +1535,8 @@ (ops VR128:$dst, VR128:$src1, i128mem:$src2), "punpckhqdq {$src2, $dst|$dst, $src2}", [(set VR128:$dst, - (v2i64 (vector_shuffle VR128:$src1, (load addr:$src2), + (v2i64 (vector_shuffle VR128:$src1, + (loadv2i64 addr:$src2), UNPCKH_shuffle_mask)))]>; } @@ -1538,7 +1549,8 @@ def PEXTRWm : PDIi8<0xC5, MRMSrcMem, (ops R32:$dst, i128mem:$src1, i32i8imm:$src2), "pextrw {$src2, $src1, $dst|$dst, $src1, $src2}", - [(set R32:$dst, (X86pextrw (loadv8i16 addr:$src1), + [(set R32:$dst, (X86pextrw + (bc_v8i16 (loadv2i64 addr:$src1)), (i32 imm:$src2)))]>; let isTwoAddress = 1 in { @@ -1773,16 +1785,6 @@ def : Pat<(v2i64 immAllOnesV), (v2i64 (V_SETALLONES))>, Requires<[HasSSE2]>; def : Pat<(v4f32 immAllOnesV), (v4f32 (V_SETALLONES))>, Requires<[HasSSE1]>; -// Load 128-bit integer vector values. -def : Pat<(v16i8 (load addr:$src)), (MOVDQArm addr:$src)>, - Requires<[HasSSE2]>; -def : Pat<(v8i16 (load addr:$src)), (MOVDQArm addr:$src)>, - Requires<[HasSSE2]>; -def : Pat<(v4i32 (load addr:$src)), (MOVDQArm addr:$src)>, - Requires<[HasSSE2]>; -def : Pat<(v2i64 (load addr:$src)), (MOVDQArm addr:$src)>, - Requires<[HasSSE2]>; - // Store 128-bit integer vector values. def : Pat<(store (v16i8 VR128:$src), addr:$dst), (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>; @@ -1790,8 +1792,6 @@ (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>; def : Pat<(store (v4i32 VR128:$src), addr:$dst), (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>; -def : Pat<(store (v2i64 VR128:$src), addr:$dst), - (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>; // Scalar to v8i16 / v16i8. The source may be a R32, but only the lower 8 or // 16-bits matter. @@ -1885,21 +1885,6 @@ (v4f32 (SHUFPSrr VR128:$src, VR128:$src, SSE_splat_mask:$sm))>, Requires<[HasSSE1]>; -// Special pshuf* cases: folding (bit_convert (loadv2i64 addr)). -def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (loadv2i64 addr:$src1)), (undef), - PSHUFD_shuffle_mask:$src2)), - (PSHUFDmi addr:$src1, PSHUFD_shuffle_mask:$src2)>, - Requires<[HasSSE2]>; -def : Pat<(v8i16 (vector_shuffle (bc_v8i16 (loadv2i64 addr:$src1)), (undef), - PSHUFHW_shuffle_mask:$src2)), - (PSHUFHWmi addr:$src1, PSHUFHW_shuffle_mask:$src2)>, - Requires<[HasSSE2]>; -def : Pat<(v8i16 (vector_shuffle (bc_v8i16 (loadv2i64 addr:$src1)), (undef), - PSHUFLW_shuffle_mask:$src2)), - (PSHUFLWmi addr:$src1, PSHUFHW_shuffle_mask:$src2)>, - Requires<[HasSSE2]>; - - // Special unary SHUFPSrr case. // FIXME: when we want non two-address code, then we should use PSHUFD? def : Pat<(vector_shuffle (v4f32 VR128:$src1), (undef), @@ -1916,8 +1901,8 @@ PSHUFD_binary_shuffle_mask:$sm), (v4i32 (SHUFPSrr VR128:$src1, VR128:$src2, PSHUFD_binary_shuffle_mask:$sm))>, Requires<[HasSSE2]>; -def : Pat<(vector_shuffle (v4i32 VR128:$src1), (load addr:$src2), - PSHUFD_binary_shuffle_mask:$sm), +def : Pat<(vector_shuffle (v4i32 VR128:$src1), + (bc_v4i32 (loadv2i64 addr:$src2)), PSHUFD_binary_shuffle_mask:$sm), (v4i32 (SHUFPSrm VR128:$src1, addr:$src2, PSHUFD_binary_shuffle_mask:$sm))>, Requires<[HasSSE2]>; From lattner at cs.uiuc.edu Wed Apr 12 12:36:16 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 12 Apr 2006 12:36:16 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/buildvec_canonicalize.ll Message-ID: <200604121736.MAA02227@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/PowerPC: buildvec_canonicalize.ll updated: 1.1 -> 1.2 --- Log message: two equivalent vsplti*s in different types should be CSEd. --- Diffs of the changes: (+12 -2) buildvec_canonicalize.ll | 14 ++++++++++++-- 1 files changed, 12 insertions(+), 2 deletions(-) Index: llvm/test/Regression/CodeGen/PowerPC/buildvec_canonicalize.ll diff -u llvm/test/Regression/CodeGen/PowerPC/buildvec_canonicalize.ll:1.1 llvm/test/Regression/CodeGen/PowerPC/buildvec_canonicalize.ll:1.2 --- llvm/test/Regression/CodeGen/PowerPC/buildvec_canonicalize.ll:1.1 Wed Apr 12 12:01:11 2006 +++ llvm/test/Regression/CodeGen/PowerPC/buildvec_canonicalize.ll Wed Apr 12 12:36:04 2006 @@ -1,7 +1,11 @@ -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 --enable-unsafe-fp-math | grep vxor | wc -l | grep 1 ; There should be exactly one vxor here. +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 --enable-unsafe-fp-math | grep vxor | wc -l | grep 1 && -void %test(<4 x float>* %P1, <4 x int>* %P2, <4 x float>* %P3) { +; There should be exactly one vsplti here. +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 --enable-unsafe-fp-math | grep vsplti | wc -l | grep 1 + + +void %VXOR(<4 x float>* %P1, <4 x int>* %P2, <4 x float>* %P3) { %tmp = load <4 x float>* %P3 %tmp3 = load <4 x float>* %P1 %tmp4 = mul <4 x float> %tmp, %tmp3 @@ -11,3 +15,9 @@ ret void } +void %VSPLTI(<4 x int>* %P2, <8 x short>* %P3) { + store <4 x int> cast (<16 x sbyte> < sbyte -1, sbyte -1, sbyte -1, sbyte -1, sbyte -1, sbyte -1, sbyte -1, sbyte -1, sbyte -1, sbyte -1, sbyte -1, sbyte -1, sbyte -1, sbyte -1, sbyte -1, sbyte -1 > to <4 x int>), <4 x int>* %P2 + store <8 x short> < short -1, short -1, short -1, short -1, short -1, short -1, short -1, short -1 >, <8 x short>* %P3 + ret void +} + From lattner at cs.uiuc.edu Wed Apr 12 12:37:32 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 12 Apr 2006 12:37:32 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCISelLowering.h PPCInstrAltivec.td Message-ID: <200604121737.MAA02374@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.145 -> 1.146 PPCISelLowering.h updated: 1.45 -> 1.46 PPCInstrAltivec.td updated: 1.48 -> 1.49 --- Log message: Rename get_VSPLI_elt -> get_VSPLTI_elt Canonicalize BUILD_VECTOR's that match VSPLTI's into a single type for each form, eliminating a bunch of Pat patterns in the .td file and allowing us to CSE stuff more aggressively. This implements PowerPC/buildvec_canonicalize.ll:VSPLTI --- Diffs of the changes: (+40 -32) PPCISelLowering.cpp | 35 ++++++++++++++++++++++++++++------- PPCISelLowering.h | 4 ++-- PPCInstrAltivec.td | 33 ++++++++++----------------------- 3 files changed, 40 insertions(+), 32 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.145 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.146 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.145 Wed Apr 12 11:53:28 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Wed Apr 12 12:37:20 2006 @@ -429,11 +429,11 @@ return cast(N->getOperand(0))->getValue() / EltSize; } -/// get_VSPLI_elt - If this is a build_vector of constants which can be formed +/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed /// by using a vspltis[bhw] instruction of the specified element size, return /// the constant being splatted. The ByteSize field indicates the number of /// bytes of each element [124] -> [bhw]. -SDOperand PPC::get_VSPLI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { +SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { SDOperand OpVal(0, 0); // If ByteSize of the splat is bigger than the element size of the @@ -920,7 +920,7 @@ // Load it out. return DAG.getLoad(Op.getValueType(), Store, FIdx, DAG.getSrcValue(NULL)); } - case ISD::BUILD_VECTOR: + case ISD::BUILD_VECTOR: { // If this is a case we can't handle, return null and let the default // expansion code take care of it. If we CAN select this case, return Op. @@ -937,13 +937,34 @@ return Op; } - if (PPC::get_VSPLI_elt(Op.Val, 1, DAG).Val || // vspltisb - PPC::get_VSPLI_elt(Op.Val, 2, DAG).Val || // vspltish - PPC::get_VSPLI_elt(Op.Val, 4, DAG).Val) // vspltisw + // Check to see if this is something we can use VSPLTI* to form. + MVT::ValueType CanonicalVT = MVT::Other; + SDNode *CST = 0; + + if ((CST = PPC::get_VSPLTI_elt(Op.Val, 4, DAG).Val)) // vspltisw + CanonicalVT = MVT::v4i32; + else if ((CST = PPC::get_VSPLTI_elt(Op.Val, 2, DAG).Val)) // vspltish + CanonicalVT = MVT::v8i16; + else if ((CST = PPC::get_VSPLTI_elt(Op.Val, 1, DAG).Val)) // vspltisb + CanonicalVT = MVT::v16i8; + + // If this matches one of the vsplti* patterns, force it to the canonical + // type for the pattern. + if (CST) { + if (Op.getValueType() != CanonicalVT) { + // Convert the splatted element to the right element type. + SDOperand Elt = DAG.getNode(ISD::TRUNCATE, + MVT::getVectorBaseType(CanonicalVT), + SDOperand(CST, 0)); + std::vector Ops(MVT::getVectorNumElements(CanonicalVT), Elt); + SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT, Ops); + Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); + } return Op; + } return SDOperand(); - + } case ISD::VECTOR_SHUFFLE: { SDOperand V1 = Op.getOperand(0); SDOperand V2 = Op.getOperand(1); Index: llvm/lib/Target/PowerPC/PPCISelLowering.h diff -u llvm/lib/Target/PowerPC/PPCISelLowering.h:1.45 llvm/lib/Target/PowerPC/PPCISelLowering.h:1.46 --- llvm/lib/Target/PowerPC/PPCISelLowering.h:1.45 Sat Apr 8 01:46:53 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.h Wed Apr 12 12:37:20 2006 @@ -131,11 +131,11 @@ /// specified isSplatShuffleMask VECTOR_SHUFFLE mask. unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize); - /// get_VSPLI_elt - If this is a build_vector of constants which can be + /// get_VSPLTI_elt - If this is a build_vector of constants which can be /// formed by using a vspltis[bhw] instruction of the specified element /// size, return the constant being splatted. The ByteSize field indicates /// the number of bytes of each element [124] -> [bhw]. - SDOperand get_VSPLI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG); + SDOperand get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG); } class PPCTargetLowering : public TargetLowering { Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.48 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.49 --- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.48 Wed Apr 12 11:53:28 2006 +++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td Wed Apr 12 12:37:20 2006 @@ -111,26 +111,26 @@ // VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm. def VSPLTISB_get_imm : SDNodeXForm; def vecspltisb : PatLeaf<(build_vector), [{ - return PPC::get_VSPLI_elt(N, 1, *CurDAG).Val != 0; + return PPC::get_VSPLTI_elt(N, 1, *CurDAG).Val != 0; }], VSPLTISB_get_imm>; // VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm. def VSPLTISH_get_imm : SDNodeXForm; def vecspltish : PatLeaf<(build_vector), [{ - return PPC::get_VSPLI_elt(N, 2, *CurDAG).Val != 0; + return PPC::get_VSPLTI_elt(N, 2, *CurDAG).Val != 0; }], VSPLTISH_get_imm>; // VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm. def VSPLTISW_get_imm : SDNodeXForm; def vecspltisw : PatLeaf<(build_vector), [{ - return PPC::get_VSPLI_elt(N, 4, *CurDAG).Val != 0; + return PPC::get_VSPLTI_elt(N, 4, *CurDAG).Val != 0; }], VSPLTISW_get_imm>; //===----------------------------------------------------------------------===// @@ -439,13 +439,13 @@ def VSPLTISB : VXForm_3<780, (ops VRRC:$vD, s5imm:$SIMM), "vspltisb $vD, $SIMM", VecPerm, - [(set VRRC:$vD, (v4f32 vecspltisb:$SIMM))]>; + [(set VRRC:$vD, (v16i8 vecspltisb:$SIMM))]>; def VSPLTISH : VXForm_3<844, (ops VRRC:$vD, s5imm:$SIMM), "vspltish $vD, $SIMM", VecPerm, - [(set VRRC:$vD, (v4f32 vecspltish:$SIMM))]>; + [(set VRRC:$vD, (v8i16 vecspltish:$SIMM))]>; def VSPLTISW : VXForm_3<908, (ops VRRC:$vD, s5imm:$SIMM), "vspltisw $vD, $SIMM", VecPerm, - [(set VRRC:$vD, (v4f32 vecspltisw:$SIMM))]>; + [(set VRRC:$vD, (v4i32 vecspltisw:$SIMM))]>; // Vector Pack. def VPKPX : VX1_Int<782, "vpkpx", int_ppc_altivec_vpkpx>; @@ -540,7 +540,7 @@ def : Pat<(int_ppc_altivec_dststt GPRC:$rA, GPRC:$rB, imm:$STRM), (DSTST 1, imm:$STRM, GPRC:$rA, GPRC:$rB)>; -// Undef/Zero. +// Undef. def : Pat<(v16i8 (undef)), (v16i8 (IMPLICIT_DEF_VRRC))>; def : Pat<(v8i16 (undef)), (v8i16 (IMPLICIT_DEF_VRRC))>; def : Pat<(v4i32 (undef)), (v4i32 (IMPLICIT_DEF_VRRC))>; @@ -602,19 +602,6 @@ def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGHW_unary_shuffle_mask:$in), (VMRGHW VRRC:$vA, VRRC:$vA)>; -// Immediate vector formation with vsplti*. -def : Pat<(v16i8 vecspltisb:$invec), (v16i8 (VSPLTISB vecspltisb:$invec))>; -def : Pat<(v16i8 vecspltish:$invec), (v16i8 (VSPLTISH vecspltish:$invec))>; -def : Pat<(v16i8 vecspltisw:$invec), (v16i8 (VSPLTISW vecspltisw:$invec))>; - -def : Pat<(v8i16 vecspltisb:$invec), (v8i16 (VSPLTISB vecspltisb:$invec))>; -def : Pat<(v8i16 vecspltish:$invec), (v8i16 (VSPLTISH vecspltish:$invec))>; -def : Pat<(v8i16 vecspltisw:$invec), (v8i16 (VSPLTISW vecspltisw:$invec))>; - -def : Pat<(v4i32 vecspltisb:$invec), (v4i32 (VSPLTISB vecspltisb:$invec))>; -def : Pat<(v4i32 vecspltish:$invec), (v4i32 (VSPLTISH vecspltish:$invec))>; -def : Pat<(v4i32 vecspltisw:$invec), (v4i32 (VSPLTISW vecspltisw:$invec))>; - // Logical Operations def : Pat<(v16i8 (vnot VRRC:$vA)), (v16i8 (VNOR VRRC:$vA, VRRC:$vA))>; def : Pat<(v8i16 (vnot VRRC:$vA)), (v8i16 (VNOR VRRC:$vA, VRRC:$vA))>; From alenhar2 at cs.uiuc.edu Wed Apr 12 12:41:31 2006 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Wed, 12 Apr 2006 12:41:31 -0500 Subject: [llvm-commits] CVS: llvm/utils/OldenDataRecover.pl Message-ID: <200604121741.MAA02542@zion.cs.uiuc.edu> Changes in directory llvm/utils: OldenDataRecover.pl added (r1.1) --- Log message: make recovering running_Olden data easier when the nightly tester eats the graphs --- Diffs of the changes: (+37 -0) OldenDataRecover.pl | 37 +++++++++++++++++++++++++++++++++++++ 1 files changed, 37 insertions(+) Index: llvm/utils/OldenDataRecover.pl diff -c /dev/null llvm/utils/OldenDataRecover.pl:1.1 *** /dev/null Wed Apr 12 12:41:29 2006 --- llvm/utils/OldenDataRecover.pl Wed Apr 12 12:41:19 2006 *************** *** 0 **** --- 1,37 ---- + #this script is intended to help recover the running graphs when + #the nightly tester decides to eat them. + + #zgrep -E "(=========)|(TEST-RESULT-llc-time)" *-Olden-tests.txt* |perl this > file + #zgrep -E "(=========)|(TEST-RESULT-compile.*bc)" *-Olden-tests.tx* |perl this >file + + while (<>) { + if (/(\d*-\d*-\d*)-.*=========.*\/(.*)\' Program/) { + # print "$1 $2\n"; + $curP = $2; + $curD = $1; + $dates{$1} = 1; + } elsif (/(\d*-\d*-\d*)-.*TEST-RESULT-.*: program (\d*\.\d*)/) { + # print "$1 $2\n"; + if ($curD eq $1) { + $$data{$curD}{$curP} = $2; + } + } elsif (/(\d*-\d*-\d*)-.*TEST-RESULT-.*: (\d*)/) { + # print "$1 $2\n"; + if ($curD eq $1) { + $$data{$curD}{$curP} = $2; + } + } + } + @progs = ("bh", "em3d", "mst", "power", "tsp", "bisort", "health", "perimeter", "treeadd", "voronoi"); + + foreach $date (sort keys %dates) { + print "$date: "; + foreach $prog (@progs) { + if ($$data{$date}{$prog}) { + print " $$data{$date}{$prog}"; + } else { + print " 0"; + } + } + print "\n"; + } From lattner at cs.uiuc.edu Wed Apr 12 12:42:51 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 12 Apr 2006 12:42:51 -0500 Subject: [llvm-commits] CVS: llvm/docs/ExtendingLLVM.html Message-ID: <200604121742.MAA02614@zion.cs.uiuc.edu> Changes in directory llvm/docs: ExtendingLLVM.html updated: 1.26 -> 1.27 --- Log message: Update adding an intrinsic to describe that you can now just plop it into the target .td file instead of adding SDNodes etc. --- Diffs of the changes: (+13 -21) ExtendingLLVM.html | 34 +++++++++++++--------------------- 1 files changed, 13 insertions(+), 21 deletions(-) Index: llvm/docs/ExtendingLLVM.html diff -u llvm/docs/ExtendingLLVM.html:1.26 llvm/docs/ExtendingLLVM.html:1.27 --- llvm/docs/ExtendingLLVM.html:1.26 Mon Mar 13 23:39:39 2006 +++ llvm/docs/ExtendingLLVM.html Wed Apr 12 12:42:39 2006 @@ -53,9 +53,9 @@ many LLVM analyses and transformations, so it may be quite a bit of work.

-

Adding an intrinsic function is easier than adding -an instruction, and is transparent to optimization passes which treat it as an -unanalyzable function. If your added functionality can be expressed as a +

Adding an intrinsic function is far easier than +adding an instruction, and is transparent to optimization passes. If your added +functionality can be expressed as a function call, an intrinsic function is the method of choice for LLVM extension.

@@ -85,8 +85,9 @@ what the restrictions are. Talk to other people about it so that you are sure it's a good idea. -
  • llvm/include/llvm/Intrinsics.td: - Add an entry for your intrinsic.
    • +
  • llvm/include/llvm/Intrinsics*.td: + Add an entry for your intrinsic. Describe its memory access characteristics + for optimization (this controls whether it will be DCE'd, CSE'd, etc).
  • llvm/lib/Analysis/ConstantFolding.cpp: If it is possible to constant fold your intrinsic, add support to it in the @@ -116,22 +117,13 @@
    -
    Add support to the SelectionDAG Instruction Selector in -lib/CodeGen/SelectionDAG/
    +
    Add support to the .td file for the target(s) of your choice in + lib/Target/*/*.td.
    -
    Since most targets in LLVM use the SelectionDAG framework for generating -code, you will likely need to add support for your intrinsic there as well. -This is usually accomplished by adding a new node, and then teaching the -SelectionDAG code how to handle that node. To do this, follow the steps in -the Adding a new SelectionDAG node section.
    - -
    -
    Once you have added the new node, add code to -SelectionDAG/SelectionDAGISel.cpp to recognize the intrinsic. In most -cases, the intrinsic will just be turned into the node you just added. For an -example of this, see how visitIntrinsicCall handles -Intrinsic::ctpop_*. -
    +
    This is usually a matter of adding a pattern to the .td file that matches + the intrinsic, though it may obviously require adding the instructions you + want to generate as well. There are lots of examples in the PowerPC and X86 + backend to follow.
    • @@ -390,7 +382,7 @@ The LLVM Compiler Infrastructure
    - Last modified: $Date: 2006/03/14 05:39:39 $ + Last modified: $Date: 2006/04/12 17:42:39 $ From reid at x10sys.com Wed Apr 12 12:56:28 2006 From: reid at x10sys.com (Reid Spencer) Date: Wed, 12 Apr 2006 12:56:28 -0500 Subject: [llvm-commits] CVS: llvm/lib/VMCore/AutoUpgrade.cpp Message-ID: <200604121756.MAA02731@zion.cs.uiuc.edu> Changes in directory llvm/lib/VMCore: AutoUpgrade.cpp updated: 1.17 -> 1.18 --- Log message: Don't emit useless warning messages. --- Diffs of the changes: (+3 -2) AutoUpgrade.cpp | 5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) Index: llvm/lib/VMCore/AutoUpgrade.cpp diff -u llvm/lib/VMCore/AutoUpgrade.cpp:1.17 llvm/lib/VMCore/AutoUpgrade.cpp:1.18 --- llvm/lib/VMCore/AutoUpgrade.cpp:1.17 Sat Mar 25 12:40:47 2006 +++ llvm/lib/VMCore/AutoUpgrade.cpp Wed Apr 12 12:56:16 2006 @@ -192,8 +192,9 @@ Function *llvm::UpgradeIntrinsicFunction(Function* F) { // See if its one of the name's we're interested in. if (Function *R = getUpgradedIntrinsic(F)) { - std::cerr << "WARNING: change " << F->getName() << " to " - << R->getName() << "\n"; + if (R->getName() != F->getName()) + std::cerr << "WARNING: change " << F->getName() << " to " + << R->getName() << "\n"; return R; } return 0; From lattner at cs.uiuc.edu Wed Apr 12 13:07:53 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 12 Apr 2006 13:07:53 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/InstCombine/cast.ll Message-ID: <200604121807.NAA02992@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/InstCombine: cast.ll updated: 1.26 -> 1.27 --- Log message: These casts should turn into gep instructions --- Diffs of the changes: (+12 -1) cast.ll | 13 ++++++++++++- 1 files changed, 12 insertions(+), 1 deletion(-) Index: llvm/test/Regression/Transforms/InstCombine/cast.ll diff -u llvm/test/Regression/Transforms/InstCombine/cast.ll:1.26 llvm/test/Regression/Transforms/InstCombine/cast.ll:1.27 --- llvm/test/Regression/Transforms/InstCombine/cast.ll:1.26 Thu Jan 19 01:39:20 2006 +++ llvm/test/Regression/Transforms/InstCombine/cast.ll Wed Apr 12 13:07:41 2006 @@ -1,5 +1,5 @@ ; Tests to make sure elimination of casts is working correctly - +; RUN: llvm-as < %s | opt -instcombine -disable-output && ; RUN: llvm-as < %s | opt -instcombine | llvm-dis | grep '%c' | not grep cast %inbuf = external global [32832 x ubyte] @@ -166,3 +166,14 @@ %D = cast double %c to int ret int %D } + +[4 x float]* %test27([9 x [4 x float]]* %A) { + %c = cast [9 x [4 x float]]* %A to [4 x float]* + ret [4 x float]* %c +} + +float* %test28([4 x float]* %A) { + %c = cast [4 x float]* %A to float* + ret float* %c +} + From tbrethou at cs.uiuc.edu Wed Apr 12 13:08:37 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 13:08:37 -0500 Subject: [llvm-commits] CVS: llvm/test/Makefile Message-ID: <200604121808.NAA03004@zion.cs.uiuc.edu> Changes in directory llvm/test: Makefile updated: 1.85 -> 1.86 --- Log message: Added llvmgcc version to allow tests to be xfailed by frontend version. --- Diffs of the changes: (+1 -0) Makefile | 1 + 1 files changed, 1 insertion(+) Index: llvm/test/Makefile diff -u llvm/test/Makefile:1.85 llvm/test/Makefile:1.86 --- llvm/test/Makefile:1.85 Thu Apr 6 17:22:08 2006 +++ llvm/test/Makefile Wed Apr 12 13:08:25 2006 @@ -41,6 +41,7 @@ @echo '# Do not edit here. If you wish to override these values' >>site.tmp @echo '# edit the last section' >>site.tmp @echo "set target_triplet $(TARGET_TRIPLE)" >> site.tmp + @echo "set llvmgcc_version $(LLVMGCC_VERSION)" >> site.tmp @echo 'set prcontext "$(TCLSH) $(LLVM_SRC_ROOT)/test/Scripts/prcontext.tcl"' >> site.tmp @echo 'set srcdir $(LLVM_SRC_ROOT)/test' >>site.tmp @echo "set objdir $(LLVM_OBJ_ROOT)/test" >>site.tmp From lattner at cs.uiuc.edu Wed Apr 12 13:09:47 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 12 Apr 2006 13:09:47 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp Message-ID: <200604121809.NAA03068@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: InstructionCombining.cpp updated: 1.464 -> 1.465 --- Log message: Turn casts into getelementptr's when possible. This enables SROA to be more aggressive in some cases where LLVMGCC 4 is inserting casts for no reason. This implements InstCombine/cast.ll:test27/28. --- Diffs of the changes: (+23 -0) InstructionCombining.cpp | 23 +++++++++++++++++++++++ 1 files changed, 23 insertions(+) Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.464 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.465 --- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.464 Mon Apr 10 18:06:36 2006 +++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Wed Apr 12 13:09:35 2006 @@ -4813,7 +4813,30 @@ if (isa(Src)) if (Instruction *NV = FoldOpIntoPhi(CI)) return NV; + + // If the source and destination are pointers, and this cast is equivalent to + // a getelementptr X, 0, 0, 0... turn it into the appropriate getelementptr. + // This can enhance SROA and other transforms that want type-safe pointers. + if (const PointerType *DstPTy = dyn_cast(CI.getType())) + if (const PointerType *SrcPTy = dyn_cast(Src->getType())) { + const Type *DstTy = DstPTy->getElementType(); + const Type *SrcTy = SrcPTy->getElementType(); + + Constant *ZeroUInt = Constant::getNullValue(Type::UIntTy); + unsigned NumZeros = 0; + while (SrcTy != DstTy && + isa(SrcTy) && !isa(SrcTy)) { + SrcTy = cast(SrcTy)->getTypeAtIndex(ZeroUInt); + ++NumZeros; + } + // If we found a path from the src to dest, create the getelementptr now. + if (SrcTy == DstTy) { + std::vector Idxs(NumZeros+1, ZeroUInt); + return new GetElementPtrInst(Src, Idxs); + } + } + // If the source value is an instruction with only this use, we can attempt to // propagate the cast into the instruction. Also, only handle integral types // for now. From reid at x10sys.com Wed Apr 12 13:21:47 2006 From: reid at x10sys.com (Reid Spencer) Date: Wed, 12 Apr 2006 13:21:47 -0500 Subject: [llvm-commits] CVS: llvm/Makefile.rules Message-ID: <200604121821.NAA03157@zion.cs.uiuc.edu> Changes in directory llvm: Makefile.rules updated: 1.361 -> 1.362 --- Log message: Make sure that the C Frontend's runtime library directory is included as a -L option to gccld whenever we're building a bytecode module or archive. This gets around the "Cannot find library 'crtend'" warning messages. --- Diffs of the changes: (+3 -2) Makefile.rules | 5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) Index: llvm/Makefile.rules diff -u llvm/Makefile.rules:1.361 llvm/Makefile.rules:1.362 --- llvm/Makefile.rules:1.361 Tue Apr 11 22:07:02 2006 +++ llvm/Makefile.rules Wed Apr 12 13:21:35 2006 @@ -690,7 +690,8 @@ else Module := $(LibDir)/$(MODULE_NAME).bc -LinkModule := $(GCCLD) +LinkModule := $(GCCLD) -L$(CFERuntimeLibDir) + ifdef EXPORTED_SYMBOL_FILE LinkModule += -internalize-public-api-file=$(EXPORTED_SYMBOL_FILE) @@ -800,7 +801,7 @@ all-local:: $(LibName.BCA) ifdef EXPORTED_SYMBOL_FILE -BCLinkLib = $(GCCLD) -internalize-public-api-file=$(EXPORTED_SYMBOL_FILE) +BCLinkLib = $(GCCLD) -L$(CFERuntimeLibDir) -internalize-public-api-file=$(EXPORTED_SYMBOL_FILE) $(LibName.BCA): $(ObjectsBC) $(LibDir)/.dir $(GCCLD) \ $(LLVMToolDir)/llvm-ar From lattner at cs.uiuc.edu Wed Apr 12 14:04:38 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 12 Apr 2006 14:04:38 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/vec_constants.ll Message-ID: <200604121904.OAA03438@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/PowerPC: vec_constants.ll added (r1.1) --- Log message: new testcase --- Diffs of the changes: (+20 -0) vec_constants.ll | 20 ++++++++++++++++++++ 1 files changed, 20 insertions(+) Index: llvm/test/Regression/CodeGen/PowerPC/vec_constants.ll diff -c /dev/null llvm/test/Regression/CodeGen/PowerPC/vec_constants.ll:1.1 *** /dev/null Wed Apr 12 14:04:37 2006 --- llvm/test/Regression/CodeGen/PowerPC/vec_constants.ll Wed Apr 12 14:04:27 2006 *************** *** 0 **** --- 1,20 ---- + ; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 && + ; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | not grep CPI + + + ; Tests spltw(0x80000000) and spltw(0x7FFFFFFF). + void %test1(<4 x int>* %P1, <4 x int>* %P2, <4 x float>* %P3) { + %tmp = load <4 x int>* %P1 + %tmp4 = and <4 x int> %tmp, < int -2147483648, int -2147483648, int -2147483648, int -2147483648 > + store <4 x int> %tmp4, <4 x int>* %P1 + %tmp7 = load <4 x int>* %P2 + %tmp9 = and <4 x int> %tmp7, < int 2147483647, int 2147483647, int 2147483647, int 2147483647 > + store <4 x int> %tmp9, <4 x int>* %P2 + %tmp = load <4 x float>* %P3 + %tmp11 = cast <4 x float> %tmp to <4 x int> + %tmp12 = and <4 x int> %tmp11, < int 2147483647, int 2147483647, int 2147483647, int 2147483647 > + %tmp13 = cast <4 x int> %tmp12 to <4 x float> + store <4 x float> %tmp13, <4 x float>* %P3 + ret void + } + From reid at x10sys.com Wed Apr 12 14:06:26 2006 From: reid at x10sys.com (Reid Spencer) Date: Wed, 12 Apr 2006 14:06:26 -0500 Subject: [llvm-commits] CVS: llvm/utils/Makefile Message-ID: <200604121906.OAA03505@zion.cs.uiuc.edu> Changes in directory llvm/utils: Makefile updated: 1.8 -> 1.9 --- Log message: Add the llvm-config directory to the EXTRA_DIST line so it gets distributed even though its not being built currently. This prevents dist-check from failing because configure can't find llvm-config.in.in --- Diffs of the changes: (+2 -1) Makefile | 3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index: llvm/utils/Makefile diff -u llvm/utils/Makefile:1.8 llvm/utils/Makefile:1.9 --- llvm/utils/Makefile:1.8 Thu Mar 23 17:21:29 2006 +++ llvm/utils/Makefile Wed Apr 12 14:06:14 2006 @@ -13,7 +13,8 @@ EXTRA_DIST = check-each-file codegen-diff countloc.sh cvsupdate emacs \ getsrcs.sh llvmdo llvmgrep llvm-native-gcc llvm-native-gxx \ makellvm NightlyTest.gnuplot NightlyTest.pl \ - NightlyTestTemplate.html profile.pl RegressionFinder.pl vim + NightlyTestTemplate.html profile.pl RegressionFinder.pl vim \ + llvm-config include $(LEVEL)/Makefile.common From lattner at cs.uiuc.edu Wed Apr 12 14:07:26 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 12 Apr 2006 14:07:26 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp README_ALTIVEC.txt Message-ID: <200604121907.OAA03517@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.146 -> 1.147 README_ALTIVEC.txt updated: 1.20 -> 1.21 --- Log message: Add a new way to match vector constants, which make it easier to bang bits of different types. Codegen spltw(0x7FFFFFFF) and spltw(0x80000000) without a constant pool load, implementing PowerPC/vec_constants.ll:test1. This compiles: typedef float vf __attribute__ ((vector_size (16))); typedef int vi __attribute__ ((vector_size (16))); void test(vi *P1, vi *P2, vf *P3) { *P1 &= (vi){0x80000000,0x80000000,0x80000000,0x80000000}; *P2 &= (vi){0x7FFFFFFF,0x7FFFFFFF,0x7FFFFFFF,0x7FFFFFFF}; *P3 = vec_abs((vector float)*P3); } to: _test: mfspr r2, 256 oris r6, r2, 49152 mtspr 256: http://llvm.cs.uiuc.edu/PR256 , r6 vspltisw v0, -1 vslw v0, v0, v0 lvx v1, 0, r3 vand v1, v1, v0 stvx v1, 0, r3 lvx v1, 0, r4 vandc v1, v1, v0 stvx v1, 0, r4 lvx v1, 0, r5 vandc v0, v1, v0 stvx v0, 0, r5 mtspr 256: http://llvm.cs.uiuc.edu/PR256 , r2 blr instead of (with two constant pool entries): _test: mfspr r2, 256 oris r6, r2, 49152 mtspr 256: http://llvm.cs.uiuc.edu/PR256 , r6 li r6, lo16(LCPI1_0) lis r7, ha16(LCPI1_0) li r8, lo16(LCPI1_1) lis r9, ha16(LCPI1_1) lvx v0, r7, r6 lvx v1, 0, r3 vand v0, v1, v0 stvx v0, 0, r3 lvx v0, r9, r8 lvx v1, 0, r4 vand v1, v1, v0 stvx v1, 0, r4 lvx v1, 0, r5 vand v0, v1, v0 stvx v0, 0, r5 mtspr 256: http://llvm.cs.uiuc.edu/PR256 , r2 blr GCC produces (with 2 cp entries): _test: mfspr r0,256 stw r0,-4(r1) oris r0,r0,0xc00c mtspr 256: http://llvm.cs.uiuc.edu/PR256 ,r0 lis r2,ha16(LC0) lis r9,ha16(LC1) la r2,lo16(LC0)(r2) lvx v0,0,r3 lvx v1,0,r5 la r9,lo16(LC1)(r9) lwz r12,-4(r1) lvx v12,0,r2 lvx v13,0,r9 vand v0,v0,v12 stvx v0,0,r3 vspltisw v0,-1 vslw v12,v0,v0 vandc v1,v1,v12 stvx v1,0,r5 lvx v0,0,r4 vand v0,v0,v13 stvx v0,0,r4 mtspr 256: http://llvm.cs.uiuc.edu/PR256 ,r12 blr --- Diffs of the changes: (+91 -7) PPCISelLowering.cpp | 89 +++++++++++++++++++++++++++++++++++++++++++++++++--- README_ALTIVEC.txt | 9 +++-- 2 files changed, 91 insertions(+), 7 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.146 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.147 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.146 Wed Apr 12 12:37:20 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Wed Apr 12 14:07:14 2006 @@ -544,6 +544,48 @@ return SDOperand(); } +// If this is a vector of constants or undefs, get the bits. A bit in +// UndefBits is set if the corresponding element of the vector is an +// ISD::UNDEF value. For undefs, the corresponding VectorBits values are +// zero. Return true if this is not an array of constants, false if it is. +// +// Note that VectorBits/UndefBits are returned in 'little endian' form, so +// elements 0,1 go in VectorBits[0] and 2,3 go in VectorBits[1] for a v4i32. +static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2], + uint64_t UndefBits[2]) { + // Start with zero'd results. + VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0; + + unsigned EltBitSize = MVT::getSizeInBits(BV->getOperand(0).getValueType()); + for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { + SDOperand OpVal = BV->getOperand(i); + + unsigned PartNo = i >= e/2; // In the upper 128 bits? + unsigned SlotNo = i & (e/2-1); // Which subpiece of the uint64_t it is. + + uint64_t EltBits = 0; + if (OpVal.getOpcode() == ISD::UNDEF) { + uint64_t EltUndefBits = ~0U >> (32-EltBitSize); + UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize); + continue; + } else if (ConstantSDNode *CN = dyn_cast(OpVal)) { + EltBits = CN->getValue() & (~0U >> (32-EltBitSize)); + } else if (ConstantFPSDNode *CN = dyn_cast(OpVal)) { + assert(CN->getValueType(0) == MVT::f32 && + "Only one legal FP vector type!"); + EltBits = FloatToBits(CN->getValue()); + } else { + // Nonconstant element. + return true; + } + + VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize); + } + + //printf("%llx %llx %llx %llx\n", + // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]); + return false; +} /// LowerOperation - Provide custom lowering hooks for some operations. /// @@ -922,12 +964,20 @@ } case ISD::BUILD_VECTOR: { // If this is a case we can't handle, return null and let the default - // expansion code take care of it. If we CAN select this case, return Op. - - // FIXME: We should handle splat(-0.0), and other cases here. + // expansion code take care of it. If we CAN select this case, return Op + // or something simpler. + + // If this is a vector of constants or undefs, get the bits. A bit in + // UndefBits is set if the corresponding element of the vector is an + // ISD::UNDEF value. For undefs, the corresponding VectorBits values are + // zero. + uint64_t VectorBits[2]; + uint64_t UndefBits[2]; + if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits)) + return SDOperand(); // Not a constant vector. // See if this is all zeros. - if (ISD::isBuildVectorAllZeros(Op.Val)) { + if ((VectorBits[0] | VectorBits[1]) == 0) { // Canonicalize all zero vectors to be v4i32. if (Op.getValueType() != MVT::v4i32) { SDOperand Z = DAG.getConstant(0, MVT::i32); @@ -962,6 +1012,37 @@ } return Op; } + + // If this is some other splat of 4-byte elements, see if we can handle it + // in another way. + // FIXME: Make this more undef happy and work with other widths (1,2 bytes). + if (VectorBits[0] == VectorBits[1] && + unsigned(VectorBits[0]) == unsigned(VectorBits[0] >> 32)) { + unsigned Bits = unsigned(VectorBits[0]); + + // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is + // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). These are important + // for fneg/fabs. + if (Bits == 0x80000000 || Bits == 0x7FFFFFFF) { + // Make -1 and vspltisw -1: + SDOperand OnesI = DAG.getConstant(~0U, MVT::i32); + SDOperand OnesV = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, + OnesI, OnesI, OnesI, OnesI); + + // Make the VSLW intrinsic, computing 0x8000_0000. + SDOperand Res + = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, MVT::v4i32, + DAG.getConstant(Intrinsic::ppc_altivec_vslw, MVT::i32), + OnesV, OnesV); + + // If this is 0x7FFF_FFFF, xor by OnesV to invert it. + if (Bits == 0x7FFFFFFF) + Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV); + + return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); + } + } + return SDOperand(); } Index: llvm/lib/Target/PowerPC/README_ALTIVEC.txt diff -u llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.20 llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.21 --- llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.20 Tue Apr 11 13:47:03 2006 +++ llvm/lib/Target/PowerPC/README_ALTIVEC.txt Wed Apr 12 14:07:14 2006 @@ -43,7 +43,8 @@ altivec instructions. Examples GCC does: "t=vsplti*, r = t+t" for constants it can't generate with one vsplti - -0.0 (sign bit): vspltisw v0,-1 / vslw v0,v0,v0 +This should be added to the ISD::BUILD_VECTOR case in +PPCTargetLowering::LowerOperation. //===----------------------------------------------------------------------===// @@ -110,8 +111,10 @@ This would fix two problems: 1. Writing patterns multiple times. -2. Identical operations in different types are not getting CSE'd (e.g. - { 0U, 0U, 0U, 0U } and {0.0, 0.0, 0.0, 0.0}. +2. Identical operations in different types are not getting CSE'd. + +We already do this for shuffle and build_vector. We need load,undef,and,or,xor, +etc. //===----------------------------------------------------------------------===// From reid at x10sys.com Wed Apr 12 14:28:27 2006 From: reid at x10sys.com (Reid Spencer) Date: Wed, 12 Apr 2006 14:28:27 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp Message-ID: <200604121928.OAA03629@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: LoopStrengthReduce.cpp updated: 1.82 -> 1.83 --- Log message: Get rid of a signed/unsigned compare warning. --- Diffs of the changes: (+1 -1) LoopStrengthReduce.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp diff -u llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.82 llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.83 --- llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:1.82 Fri Mar 24 01:14:34 2006 +++ llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp Wed Apr 12 14:28:15 2006 @@ -882,7 +882,7 @@ I = TLI->legal_am_scale_begin(), E = TLI->legal_am_scale_end(); I != E; ++I) { unsigned Scale = *I; - if (abs(SInt) < Scale || (SInt % Scale) != 0) + if (unsigned(abs(SInt)) < Scale || (SInt % Scale) != 0) continue; std::map::iterator SI = IVsByStride.find(SCEVUnknown::getIntegerSCEV(SInt/Scale, Type::UIntTy)); From reid at x10sys.com Wed Apr 12 15:53:26 2006 From: reid at x10sys.com (Reid Spencer) Date: Wed, 12 Apr 2006 15:53:26 -0500 Subject: [llvm-commits] CVS: llvm/Makefile Message-ID: <200604122053.PAA04155@zion.cs.uiuc.edu> Changes in directory llvm: Makefile updated: 1.57 -> 1.58 --- Log message: Include the win32 and Xcode directories in the distribution. --- Diffs of the changes: (+1 -1) Makefile | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/Makefile diff -u llvm/Makefile:1.57 llvm/Makefile:1.58 --- llvm/Makefile:1.57 Fri Apr 7 21:14:37 2006 +++ llvm/Makefile Wed Apr 12 15:53:14 2006 @@ -25,7 +25,7 @@ DIRS += docs endif endif -EXTRA_DIST := test llvm.spec include +EXTRA_DIST := test llvm.spec include win32 Xcode include $(LLVM_SRC_ROOT)/Makefile.rules From reid at x10sys.com Wed Apr 12 15:54:13 2006 From: reid at x10sys.com (Reid Spencer) Date: Wed, 12 Apr 2006 15:54:13 -0500 Subject: [llvm-commits] CVS: llvm/utils/Makefile Message-ID: <200604122054.PAA04173@zion.cs.uiuc.edu> Changes in directory llvm/utils: Makefile updated: 1.9 -> 1.10 --- Log message: Additional files to distribute. --- Diffs of the changes: (+7 -5) Makefile | 12 +++++++----- 1 files changed, 7 insertions(+), 5 deletions(-) Index: llvm/utils/Makefile diff -u llvm/utils/Makefile:1.9 llvm/utils/Makefile:1.10 --- llvm/utils/Makefile:1.9 Wed Apr 12 14:06:14 2006 +++ llvm/utils/Makefile Wed Apr 12 15:54:01 2006 @@ -10,11 +10,13 @@ LEVEL = .. DIRS = Burg TableGen fpcmp -EXTRA_DIST = check-each-file codegen-diff countloc.sh cvsupdate emacs \ - getsrcs.sh llvmdo llvmgrep llvm-native-gcc llvm-native-gxx \ - makellvm NightlyTest.gnuplot NightlyTest.pl \ - NightlyTestTemplate.html profile.pl RegressionFinder.pl vim \ - llvm-config +EXTRA_DIST := cgiplotNLT.pl check-each-file codegen-diff countloc.sh cvsupdate \ + DSAclean.py DSAextract.py emacs findsym.pl GenLibDeps.pl \ + getsrcs.sh importNLT.pl llvmdo llvmgrep llvm-native-gcc \ + llvm-native-gxx makellvm NightlyTest.gnuplot NightlyTest.pl \ + NightlyTestTemplate.html NLT.schema parseNTL.pl plotNLT.pl \ + profile.pl RegressionFinder.pl userloc.pl webNLT.pl \ + vim llvm-config include $(LEVEL)/Makefile.common From reid at x10sys.com Wed Apr 12 15:55:34 2006 From: reid at x10sys.com (Reid Spencer) Date: Wed, 12 Apr 2006 15:55:34 -0500 Subject: [llvm-commits] CVS: llvm/projects/Stacker/lib/compiler/Makefile Message-ID: <200604122055.PAA04201@zion.cs.uiuc.edu> Changes in directory llvm/projects/Stacker/lib/compiler: Makefile updated: 1.6 -> 1.7 --- Log message: Distribute the lex/yacc files from the cvs version. --- Diffs of the changes: (+2 -0) Makefile | 2 ++ 1 files changed, 2 insertions(+) Index: llvm/projects/Stacker/lib/compiler/Makefile diff -u llvm/projects/Stacker/lib/compiler/Makefile:1.6 llvm/projects/Stacker/lib/compiler/Makefile:1.7 --- llvm/projects/Stacker/lib/compiler/Makefile:1.6 Sat Aug 27 13:50:39 2005 +++ llvm/projects/Stacker/lib/compiler/Makefile Wed Apr 12 15:55:23 2006 @@ -2,6 +2,8 @@ LEVEL := ../.. LIBRARYNAME := stkr_compiler +EXTRA_DIST := Lexer.cpp.cvs Lexer.l.cvs \ + StackerParser.cpp.cvs StackerParser.h.cvs StackerParser.y.cvs include $(LEVEL)/Makefile.common From reid at x10sys.com Wed Apr 12 15:56:23 2006 From: reid at x10sys.com (Reid Spencer) Date: Wed, 12 Apr 2006 15:56:23 -0500 Subject: [llvm-commits] CVS: llvm/tools/llvmc/Makefile Message-ID: <200604122056.PAA04221@zion.cs.uiuc.edu> Changes in directory llvm/tools/llvmc: Makefile updated: 1.15 -> 1.16 --- Log message: Distribute CVS versions of lex files --- Diffs of the changes: (+1 -1) Makefile | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/tools/llvmc/Makefile diff -u llvm/tools/llvmc/Makefile:1.15 llvm/tools/llvmc/Makefile:1.16 --- llvm/tools/llvmc/Makefile:1.15 Wed May 18 19:52:29 2005 +++ llvm/tools/llvmc/Makefile Wed Apr 12 15:56:12 2006 @@ -10,7 +10,7 @@ TOOLNAME = llvmc USEDLIBS = LLVMBCReader LLVMCore LLVMSupport.a LLVMbzip2 LLVMSystem.a CONFIG_FILES = c cpp ll -EXTRA_DIST = c cpp ll +EXTRA_DIST = c cpp ll ConfigLexer.cpp.cvs ConfigLexer.l.cvs # The CompilerDriver needs to know the locations of several configured # directories and paths. We define these as preprocessor symbols so they can From reid at x10sys.com Wed Apr 12 15:57:17 2006 From: reid at x10sys.com (Reid Spencer) Date: Wed, 12 Apr 2006 15:57:17 -0500 Subject: [llvm-commits] CVS: llvm/lib/AsmParser/Makefile Message-ID: <200604122057.PAA04236@zion.cs.uiuc.edu> Changes in directory llvm/lib/AsmParser: Makefile updated: 1.8 -> 1.9 --- Log message: Make sure CVS versions of yacc and lex files get distributed. --- Diffs of the changes: (+2 -0) Makefile | 2 ++ 1 files changed, 2 insertions(+) Index: llvm/lib/AsmParser/Makefile diff -u llvm/lib/AsmParser/Makefile:1.8 llvm/lib/AsmParser/Makefile:1.9 --- llvm/lib/AsmParser/Makefile:1.8 Sat Aug 27 13:50:38 2005 +++ llvm/lib/AsmParser/Makefile Wed Apr 12 15:57:05 2006 @@ -9,6 +9,8 @@ LEVEL = ../.. LIBRARYNAME := LLVMAsmParser +EXTRA_DIST := Lexer.cpp.cvs Lexer.l.cvs \ + llvmAsmParser.cpp.cvs llvmAsmParser.h.cvs llvmAsmParser.y.cvs include $(LEVEL)/Makefile.common From reid at x10sys.com Wed Apr 12 16:03:17 2006 From: reid at x10sys.com (Reid Spencer) Date: Wed, 12 Apr 2006 16:03:17 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/Generic/vector.ll Message-ID: <200604122103.QAA04470@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/Generic: vector.ll updated: 1.8 -> 1.9 --- Log message: Don't dump the llc assembly output to stdout. --- Diffs of the changes: (+5 -5) vector.ll | 10 +++++----- 1 files changed, 5 insertions(+), 5 deletions(-) Index: llvm/test/Regression/CodeGen/Generic/vector.ll diff -u llvm/test/Regression/CodeGen/Generic/vector.ll:1.8 llvm/test/Regression/CodeGen/Generic/vector.ll:1.9 --- llvm/test/Regression/CodeGen/Generic/vector.ll:1.8 Fri Mar 31 11:59:16 2006 +++ llvm/test/Regression/CodeGen/Generic/vector.ll Wed Apr 12 16:03:04 2006 @@ -1,9 +1,9 @@ ; Test that vectors are scalarized/lowered correctly. -; RUN: llvm-as < %s | llc && -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 && -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g3 && -; RUN: llvm-as < %s | llc -march=x86 -mcpu=i386 && -; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah +; RUN: llvm-as < %s | llc > /dev/null && +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 > /dev/null && +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g3 > /dev/null && +; RUN: llvm-as < %s | llc -march=x86 -mcpu=i386 > /dev/null && +; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah -o /dev/null %f1 = type <1 x float> %f2 = type <2 x float> From evan.cheng at apple.com Wed Apr 12 16:20:36 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 12 Apr 2006 16:20:36 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <200604122120.QAA04694@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.363 -> 1.364 --- Log message: Promote vector AND, OR, and XOR --- Diffs of the changes: (+27 -0) LegalizeDAG.cpp | 27 +++++++++++++++++++++++++++ 1 files changed, 27 insertions(+) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.363 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.364 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.363 Wed Apr 12 11:33:18 2006 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Apr 12 16:20:24 2006 @@ -2076,6 +2076,25 @@ Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0), Ops); break; } + case TargetLowering::Promote: { + switch (Node->getOpcode()) { + default: assert(0 && "Do not know how to promote this BinOp!"); + case ISD::AND: + case ISD::OR: + case ISD::XOR: { + MVT::ValueType OVT = Node->getValueType(0); + MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); + assert(MVT::isVector(OVT) && "Cannot promote this BinOp!"); + // Bit convert each of the values to the new type. + Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); + Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); + Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); + // Bit convert the result back the original type. + Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); + break; + } + } + } } break; @@ -2953,6 +2972,14 @@ case ISD::AND: case ISD::OR: case ISD::XOR: + // The input may have strange things in the top bits of the registers, but + // these operations don't care. They may have weird bits going out, but + // that too is okay if they are integer operations. + Tmp1 = PromoteOp(Node->getOperand(0)); + Tmp2 = PromoteOp(Node->getOperand(1)); + assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); + Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); + break; case ISD::ADD: case ISD::SUB: case ISD::MUL: From evan.cheng at apple.com Wed Apr 12 16:22:09 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 12 Apr 2006 16:22:09 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/README.txt X86ISelLowering.cpp X86InstrSSE.td Message-ID: <200604122122.QAA04732@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: README.txt updated: 1.85 -> 1.86 X86ISelLowering.cpp updated: 1.163 -> 1.164 X86InstrSSE.td updated: 1.79 -> 1.80 --- Log message: All "integer" logical ops (pand, por, pxor) are now promoted to v2i64. Clean up and fix various logical ops issues. --- Diffs of the changes: (+71 -146) README.txt | 4 + X86ISelLowering.cpp | 45 ++++++++----- X86InstrSSE.td | 168 ++++++++++++---------------------------------------- 3 files changed, 71 insertions(+), 146 deletions(-) Index: llvm/lib/Target/X86/README.txt diff -u llvm/lib/Target/X86/README.txt:1.85 llvm/lib/Target/X86/README.txt:1.86 --- llvm/lib/Target/X86/README.txt:1.85 Mon Apr 10 16:51:03 2006 +++ llvm/lib/Target/X86/README.txt Wed Apr 12 16:21:57 2006 @@ -794,3 +794,7 @@ X86RegisterInfo::copyRegToReg() returns X86::MOVAPSrr for VR128. Is it possible to choose between movaps, movapd, and movdqa based on types of source and destination? + +How about andps, andpd, and pand? Do we really care about the type of the packed +elements? If not, why not always use the "ps" variants which are likely to be +shorter. Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.163 llvm/lib/Target/X86/X86ISelLowering.cpp:1.164 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.163 Wed Apr 12 12:12:36 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Wed Apr 12 16:21:57 2006 @@ -275,6 +275,9 @@ if (Subtarget->hasSSE1()) { addRegisterClass(MVT::v4f32, X86::VR128RegisterClass); + setOperationAction(ISD::AND, MVT::v4f32, Legal); + setOperationAction(ISD::OR, MVT::v4f32, Legal); + setOperationAction(ISD::XOR, MVT::v4f32, Legal); setOperationAction(ISD::ADD, MVT::v4f32, Legal); setOperationAction(ISD::SUB, MVT::v4f32, Legal); setOperationAction(ISD::MUL, MVT::v4f32, Legal); @@ -301,36 +304,43 @@ setOperationAction(ISD::SUB, MVT::v8i16, Legal); setOperationAction(ISD::SUB, MVT::v4i32, Legal); setOperationAction(ISD::MUL, MVT::v2f64, Legal); - setOperationAction(ISD::LOAD, MVT::v2f64, Legal); + setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); + setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); + + // Custom lower build_vector, vector_shuffle, and extract_vector_elt. + for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) { + setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Custom); + setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Custom); + setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Custom); + } setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); - setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom); - setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom); - setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom); setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); - setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); - setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i16, Custom); - setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i32, Custom); setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); - setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom); - setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); - setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); + setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); - // Promote v16i8, v8i16, v4i32 selects to v2i64. Custom lower v2i64, v2f64, - // and v4f32 selects. - for (unsigned VT = (unsigned)MVT::v16i8; - VT != (unsigned)MVT::v2i64; VT++) { - setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote); - AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v2i64); + // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. + for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) { + setOperationAction(ISD::AND, (MVT::ValueType)VT, Promote); + AddPromotedToType (ISD::AND, (MVT::ValueType)VT, MVT::v2i64); + setOperationAction(ISD::OR, (MVT::ValueType)VT, Promote); + AddPromotedToType (ISD::OR, (MVT::ValueType)VT, MVT::v2i64); + setOperationAction(ISD::XOR, (MVT::ValueType)VT, Promote); + AddPromotedToType (ISD::XOR, (MVT::ValueType)VT, MVT::v2i64); setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Promote); AddPromotedToType (ISD::LOAD, (MVT::ValueType)VT, MVT::v2i64); + setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote); + AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v2i64); } + + // Custom lower v2i64 and v2f64 selects. + setOperationAction(ISD::LOAD, MVT::v2f64, Legal); setOperationAction(ISD::LOAD, MVT::v2i64, Legal); - setOperationAction(ISD::SELECT, MVT::v2i64, Custom); setOperationAction(ISD::SELECT, MVT::v2f64, Custom); + setOperationAction(ISD::SELECT, MVT::v2i64, Custom); } // We want to custom lower some of our intrinsics. @@ -2827,6 +2837,7 @@ return SDOperand(); MVT::ValueType VT = Op.getValueType(); + // TODO: handle v16i8. if (MVT::getSizeInBits(VT) == 16) { // Transform it so it match pextrw which produces a 32-bit result. MVT::ValueType EVT = (MVT::ValueType)(VT+1); Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.79 llvm/lib/Target/X86/X86InstrSSE.td:1.80 --- llvm/lib/Target/X86/X86InstrSSE.td:1.79 Wed Apr 12 12:12:36 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Wed Apr 12 16:21:57 2006 @@ -1019,9 +1019,7 @@ let isCommutable = 1 in { def ANDPSrr : PSI<0x54, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), "andps {$src2, $dst|$dst, $src2}", - [(set VR128:$dst, - (and (bc_v4i32 (v4f32 VR128:$src1)), - (bc_v4i32 (v4f32 VR128:$src2))))]>; + [(set VR128:$dst, (v2i64 (and VR128:$src1, VR128:$src2)))]>; def ANDPDrr : PDI<0x54, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), "andpd {$src2, $dst|$dst, $src2}", [(set VR128:$dst, @@ -1029,9 +1027,7 @@ (bc_v2i64 (v2f64 VR128:$src2))))]>; def ORPSrr : PSI<0x56, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), "orps {$src2, $dst|$dst, $src2}", - [(set VR128:$dst, - (or (bc_v4i32 (v4f32 VR128:$src1)), - (bc_v4i32 (v4f32 VR128:$src2))))]>; + [(set VR128:$dst, (v2i64 (or VR128:$src1, VR128:$src2)))]>; def ORPDrr : PDI<0x56, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), "orpd {$src2, $dst|$dst, $src2}", [(set VR128:$dst, @@ -1039,9 +1035,7 @@ (bc_v2i64 (v2f64 VR128:$src2))))]>; def XORPSrr : PSI<0x57, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), "xorps {$src2, $dst|$dst, $src2}", - [(set VR128:$dst, - (xor (bc_v4i32 (v4f32 VR128:$src1)), - (bc_v4i32 (v4f32 VR128:$src2))))]>; + [(set VR128:$dst, (v2i64 (xor VR128:$src1, VR128:$src2)))]>; def XORPDrr : PDI<0x57, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), "xorpd {$src2, $dst|$dst, $src2}", [(set VR128:$dst, @@ -1050,9 +1044,8 @@ } def ANDPSrm : PSI<0x54, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), "andps {$src2, $dst|$dst, $src2}", - [(set VR128:$dst, - (and (bc_v4i32 (v4f32 VR128:$src1)), - (bc_v4i32 (loadv4f32 addr:$src2))))]>; + [(set VR128:$dst, (and VR128:$src1, + (bc_v2i64 (loadv4f32 addr:$src2))))]>; def ANDPDrm : PDI<0x54, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), "andpd {$src2, $dst|$dst, $src2}", [(set VR128:$dst, @@ -1060,9 +1053,8 @@ (bc_v2i64 (loadv2f64 addr:$src2))))]>; def ORPSrm : PSI<0x56, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), "orps {$src2, $dst|$dst, $src2}", - [(set VR128:$dst, - (or (bc_v4i32 (v4f32 VR128:$src1)), - (bc_v4i32 (loadv4f32 addr:$src2))))]>; + [(set VR128:$dst, (or VR128:$src1, + (bc_v2i64 (loadv4f32 addr:$src2))))]>; def ORPDrm : PDI<0x56, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), "orpd {$src2, $dst|$dst, $src2}", [(set VR128:$dst, @@ -1070,9 +1062,8 @@ (bc_v2i64 (loadv2f64 addr:$src2))))]>; def XORPSrm : PSI<0x57, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), "xorps {$src2, $dst|$dst, $src2}", - [(set VR128:$dst, - (xor (bc_v4i32 (v4f32 VR128:$src1)), - (bc_v4i32 (loadv4f32 addr:$src2))))]>; + [(set VR128:$dst, (xor VR128:$src1, + (bc_v2i64 (loadv4f32 addr:$src2))))]>; def XORPDrm : PDI<0x57, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), "xorpd {$src2, $dst|$dst, $src2}", [(set VR128:$dst, @@ -1080,14 +1071,14 @@ (bc_v2i64 (loadv2f64 addr:$src2))))]>; def ANDNPSrr : PSI<0x55, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), "andnps {$src2, $dst|$dst, $src2}", - [(set VR128:$dst, - (and (vnot (bc_v4i32 (v4f32 VR128:$src1))), - (bc_v4i32 (v4f32 VR128:$src2))))]>; + [(set VR128:$dst, (v2i64 (and (xor VR128:$src1, + (bc_v2i64 (v4i32 immAllOnesV))), + VR128:$src2)))]>; def ANDNPSrm : PSI<0x55, MRMSrcMem, (ops VR128:$dst, VR128:$src1,f128mem:$src2), "andnps {$src2, $dst|$dst, $src2}", - [(set VR128:$dst, - (and (vnot (bc_v4i32 (v4f32 VR128:$src1))), - (bc_v4i32 (loadv4f32 addr:$src2))))]>; + [(set VR128:$dst, (v2i64 (and (xor VR128:$src1, + (bc_v2i64 (v4i32 immAllOnesV))), + (bc_v2i64 (loadv4f32 addr:$src2)))))]>; def ANDNPDrr : PDI<0x55, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), "andnpd {$src2, $dst|$dst, $src2}", [(set VR128:$dst, @@ -1922,110 +1913,29 @@ // 128-bit logical shifts def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2), - (v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>; + (v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>, + Requires<[HasSSE2]>; def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2), - (v2i64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>; + (v2i64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>, + Requires<[HasSSE2]>; -// Logical ops -def : Pat<(and (bc_v4i32 (v4f32 VR128:$src1)), (loadv4i32 addr:$src2)), - (ANDPSrm VR128:$src1, addr:$src2)>; -def : Pat<(and (bc_v2i64 (v2f64 VR128:$src1)), (loadv2i64 addr:$src2)), - (ANDPDrm VR128:$src1, addr:$src2)>; -def : Pat<(or (bc_v4i32 (v4f32 VR128:$src1)), (loadv4i32 addr:$src2)), - (ORPSrm VR128:$src1, addr:$src2)>; -def : Pat<(or (bc_v2i64 (v2f64 VR128:$src1)), (loadv2i64 addr:$src2)), - (ORPDrm VR128:$src1, addr:$src2)>; -def : Pat<(xor (bc_v4i32 (v4f32 VR128:$src1)), (loadv4i32 addr:$src2)), - (XORPSrm VR128:$src1, addr:$src2)>; -def : Pat<(xor (bc_v2i64 (v2f64 VR128:$src1)), (loadv2i64 addr:$src2)), - (XORPDrm VR128:$src1, addr:$src2)>; -def : Pat<(and (vnot (bc_v4i32 (v4f32 VR128:$src1))), (loadv4i32 addr:$src2)), - (ANDNPSrm VR128:$src1, addr:$src2)>; -def : Pat<(and (vnot (bc_v2i64 (v2f64 VR128:$src1))), (loadv2i64 addr:$src2)), - (ANDNPDrm VR128:$src1, addr:$src2)>; - -def : Pat<(bc_v4f32 (v4i32 (and VR128:$src1, VR128:$src2))), - (ANDPSrr VR128:$src1, VR128:$src2)>; -def : Pat<(bc_v4f32 (v4i32 (or VR128:$src1, VR128:$src2))), - (ORPSrr VR128:$src1, VR128:$src2)>; -def : Pat<(bc_v4f32 (v4i32 (xor VR128:$src1, VR128:$src2))), - (XORPSrr VR128:$src1, VR128:$src2)>; -def : Pat<(bc_v4f32 (v4i32 (and (vnot VR128:$src1), VR128:$src2))), - (ANDNPSrr VR128:$src1, VR128:$src2)>; - -def : Pat<(bc_v4f32 (v4i32 (and VR128:$src1, (load addr:$src2)))), - (ANDPSrm (v4i32 VR128:$src1), addr:$src2)>; -def : Pat<(bc_v4f32 (v4i32 (or VR128:$src1, (load addr:$src2)))), - (ORPSrm VR128:$src1, addr:$src2)>; -def : Pat<(bc_v4f32 (v4i32 (xor VR128:$src1, (load addr:$src2)))), - (XORPSrm VR128:$src1, addr:$src2)>; -def : Pat<(bc_v4f32 (v4i32 (and (vnot VR128:$src1), (load addr:$src2)))), - (ANDNPSrm VR128:$src1, addr:$src2)>; - -def : Pat<(bc_v2f64 (v2i64 (and VR128:$src1, VR128:$src2))), - (ANDPDrr VR128:$src1, VR128:$src2)>; -def : Pat<(bc_v2f64 (v2i64 (or VR128:$src1, VR128:$src2))), - (ORPDrr VR128:$src1, VR128:$src2)>; -def : Pat<(bc_v2f64 (v2i64 (xor VR128:$src1, VR128:$src2))), - (XORPDrr VR128:$src1, VR128:$src2)>; -def : Pat<(bc_v2f64 (v2i64 (and (vnot VR128:$src1), VR128:$src2))), - (ANDNPDrr VR128:$src1, VR128:$src2)>; - -def : Pat<(bc_v2f64 (v2i64 (and VR128:$src1, (load addr:$src2)))), - (ANDPSrm (v2i64 VR128:$src1), addr:$src2)>; -def : Pat<(bc_v2f64 (v2i64 (or VR128:$src1, (load addr:$src2)))), - (ORPSrm VR128:$src1, addr:$src2)>; -def : Pat<(bc_v2f64 (v2i64 (xor VR128:$src1, (load addr:$src2)))), - (XORPSrm VR128:$src1, addr:$src2)>; -def : Pat<(bc_v2f64 (v2i64 (and (vnot VR128:$src1), (load addr:$src2)))), - (ANDNPSrm VR128:$src1, addr:$src2)>; - -def : Pat<(v4i32 (and VR128:$src1, VR128:$src2)), - (PANDrr VR128:$src1, VR128:$src2)>; -def : Pat<(v8i16 (and VR128:$src1, VR128:$src2)), - (PANDrr VR128:$src1, VR128:$src2)>; -def : Pat<(v16i8 (and VR128:$src1, VR128:$src2)), - (PANDrr VR128:$src1, VR128:$src2)>; -def : Pat<(v4i32 (or VR128:$src1, VR128:$src2)), - (PORrr VR128:$src1, VR128:$src2)>; -def : Pat<(v8i16 (or VR128:$src1, VR128:$src2)), - (PORrr VR128:$src1, VR128:$src2)>; -def : Pat<(v16i8 (or VR128:$src1, VR128:$src2)), - (PORrr VR128:$src1, VR128:$src2)>; -def : Pat<(v4i32 (xor VR128:$src1, VR128:$src2)), - (PXORrr VR128:$src1, VR128:$src2)>; -def : Pat<(v8i16 (xor VR128:$src1, VR128:$src2)), - (PXORrr VR128:$src1, VR128:$src2)>; -def : Pat<(v16i8 (xor VR128:$src1, VR128:$src2)), - (PXORrr VR128:$src1, VR128:$src2)>; -def : Pat<(v4i32 (and (vnot VR128:$src1), VR128:$src2)), - (PANDNrr VR128:$src1, VR128:$src2)>; -def : Pat<(v8i16 (and (vnot VR128:$src1), VR128:$src2)), - (PANDNrr VR128:$src1, VR128:$src2)>; -def : Pat<(v16i8 (and (vnot VR128:$src1), VR128:$src2)), - (PANDNrr VR128:$src1, VR128:$src2)>; - -def : Pat<(v4i32 (and VR128:$src1, (load addr:$src2))), - (PANDrm VR128:$src1, addr:$src2)>; -def : Pat<(v8i16 (and VR128:$src1, (load addr:$src2))), - (PANDrm VR128:$src1, addr:$src2)>; -def : Pat<(v16i8 (and VR128:$src1, (load addr:$src2))), - (PANDrm VR128:$src1, addr:$src2)>; -def : Pat<(v4i32 (or VR128:$src1, (load addr:$src2))), - (PORrm VR128:$src1, addr:$src2)>; -def : Pat<(v8i16 (or VR128:$src1, (load addr:$src2))), - (PORrm VR128:$src1, addr:$src2)>; -def : Pat<(v16i8 (or VR128:$src1, (load addr:$src2))), - (PORrm VR128:$src1, addr:$src2)>; -def : Pat<(v4i32 (xor VR128:$src1, (load addr:$src2))), - (PXORrm VR128:$src1, addr:$src2)>; -def : Pat<(v8i16 (xor VR128:$src1, (load addr:$src2))), - (PXORrm VR128:$src1, addr:$src2)>; -def : Pat<(v16i8 (xor VR128:$src1, (load addr:$src2))), - (PXORrm VR128:$src1, addr:$src2)>; -def : Pat<(v4i32 (and (vnot VR128:$src1), (load addr:$src2))), - (PANDNrm VR128:$src1, addr:$src2)>; -def : Pat<(v8i16 (and (vnot VR128:$src1), (load addr:$src2))), - (PANDNrm VR128:$src1, addr:$src2)>; -def : Pat<(v16i8 (and (vnot VR128:$src1), (load addr:$src2))), - (PANDNrm VR128:$src1, addr:$src2)>; +// Some special case pandn patterns. +def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))), + VR128:$src2)), + (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>; +def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))), + VR128:$src2)), + (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>; +def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))), + VR128:$src2)), + (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>; + +def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))), + (load addr:$src2))), + (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>; +def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))), + (load addr:$src2))), + (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>; +def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))), + (load addr:$src2))), + (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>; From evan.cheng at apple.com Wed Apr 12 16:28:26 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 12 Apr 2006 16:28:26 -0500 Subject: [llvm-commits] CVS: llvm/CREDITS.TXT Message-ID: <200604122128.QAA04800@zion.cs.uiuc.edu> Changes in directory llvm: CREDITS.TXT updated: 1.49 -> 1.50 --- Log message: Update my credits. Can I add "Build breaker" to my entry? --- Diffs of the changes: (+4 -1) CREDITS.TXT | 5 ++++- 1 files changed, 4 insertions(+), 1 deletion(-) Index: llvm/CREDITS.TXT diff -u llvm/CREDITS.TXT:1.49 llvm/CREDITS.TXT:1.50 --- llvm/CREDITS.TXT:1.49 Tue Apr 11 03:16:45 2006 +++ llvm/CREDITS.TXT Wed Apr 12 16:28:14 2006 @@ -41,7 +41,10 @@ N: Evan Cheng E: evan.cheng at apple.com -D: X86 backend improvements +D: X86 backend developer +D: Instruction scheduler improvements +D: Loop optimizer improvements +D: Target-independent code generator improvements N: Jeff Cohen E: jeffc at jolt-lang.org From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:50 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:50 -0500 Subject: [llvm-commits] CVS: llvm/test/Feature/dg.exp Message-ID: <200604122158.QAA05600@zion.cs.uiuc.edu> Changes in directory llvm/test/Feature: dg.exp updated: 1.3 -> 1.4 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Feature/dg.exp diff -u llvm/test/Feature/dg.exp:1.3 llvm/test/Feature/dg.exp:1.4 --- llvm/test/Feature/dg.exp:1.3 Fri Nov 19 16:42:44 2004 +++ llvm/test/Feature/dg.exp Wed Apr 12 16:57:23 2006 @@ -1,4 +1,4 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:46 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:46 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/TableGen/dg.exp Message-ID: <200604122158.QAA05559@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/TableGen: dg.exp updated: 1.3 -> 1.4 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/TableGen/dg.exp diff -u llvm/test/Regression/TableGen/dg.exp:1.3 llvm/test/Regression/TableGen/dg.exp:1.4 --- llvm/test/Regression/TableGen/dg.exp:1.3 Mon Apr 18 20:36:41 2005 +++ llvm/test/Regression/TableGen/dg.exp Wed Apr 12 16:57:35 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{td}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{td}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:50 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:50 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Other/dg.exp Message-ID: <200604122158.QAA05629@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Other: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Other/dg.exp diff -u llvm/test/Regression/Other/dg.exp:1.2 llvm/test/Regression/Other/dg.exp:1.3 --- llvm/test/Regression/Other/dg.exp:1.2 Fri Nov 19 16:43:52 2004 +++ llvm/test/Regression/Other/dg.exp Wed Apr 12 16:57:35 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:50 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:50 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Linker/dg.exp Message-ID: <200604122158.QAA05630@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Linker: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Linker/dg.exp diff -u llvm/test/Regression/Linker/dg.exp:1.2 llvm/test/Regression/Linker/dg.exp:1.3 --- llvm/test/Regression/Linker/dg.exp:1.2 Fri Nov 19 16:43:50 2004 +++ llvm/test/Regression/Linker/dg.exp Wed Apr 12 16:57:35 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:50 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:50 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/Alpha/dg.exp Message-ID: <200604122158.QAA05624@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/Alpha: dg.exp updated: 1.1 -> 1.2 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/CodeGen/Alpha/dg.exp diff -u llvm/test/Regression/CodeGen/Alpha/dg.exp:1.1 llvm/test/Regression/CodeGen/Alpha/dg.exp:1.2 --- llvm/test/Regression/CodeGen/Alpha/dg.exp:1.1 Fri May 13 10:44:55 2005 +++ llvm/test/Regression/CodeGen/Alpha/dg.exp Wed Apr 12 16:57:34 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:44 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:44 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/BugPoint/dg.exp Message-ID: <200604122158.QAA05535@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/BugPoint: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/BugPoint/dg.exp diff -u llvm/test/Regression/BugPoint/dg.exp:1.2 llvm/test/Regression/BugPoint/dg.exp:1.3 --- llvm/test/Regression/BugPoint/dg.exp:1.2 Fri Nov 19 16:43:17 2004 +++ llvm/test/Regression/BugPoint/dg.exp Wed Apr 12 16:57:33 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:45 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:45 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Archive/dg.exp Message-ID: <200604122158.QAA05543@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Archive: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Archive/dg.exp diff -u llvm/test/Regression/Archive/dg.exp:1.2 llvm/test/Regression/Archive/dg.exp:1.3 --- llvm/test/Regression/Archive/dg.exp:1.2 Sat Nov 20 01:25:10 2004 +++ llvm/test/Regression/Archive/dg.exp Wed Apr 12 16:57:33 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:50 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:50 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/IA64/dg.exp Message-ID: <200604122158.QAA05612@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/IA64: dg.exp updated: 1.1 -> 1.2 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/CodeGen/IA64/dg.exp diff -u llvm/test/Regression/CodeGen/IA64/dg.exp:1.1 llvm/test/Regression/CodeGen/IA64/dg.exp:1.2 --- llvm/test/Regression/CodeGen/IA64/dg.exp:1.1 Mon Aug 22 12:15:41 2005 +++ llvm/test/Regression/CodeGen/IA64/dg.exp Wed Apr 12 16:57:34 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:45 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:45 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CFrontend/dg.exp Message-ID: <200604122158.QAA05544@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CFrontend: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/CFrontend/dg.exp diff -u llvm/test/Regression/CFrontend/dg.exp:1.2 llvm/test/Regression/CFrontend/dg.exp:1.3 --- llvm/test/Regression/CFrontend/dg.exp:1.2 Fri Nov 19 16:43:25 2004 +++ llvm/test/Regression/CFrontend/dg.exp Wed Apr 12 16:57:34 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:46 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:46 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Debugger/dg.exp Message-ID: <200604122158.QAA05561@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Debugger: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Debugger/dg.exp diff -u llvm/test/Regression/Debugger/dg.exp:1.2 llvm/test/Regression/Debugger/dg.exp:1.3 --- llvm/test/Regression/Debugger/dg.exp:1.2 Fri Nov 19 16:43:45 2004 +++ llvm/test/Regression/Debugger/dg.exp Wed Apr 12 16:57:35 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:41 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:41 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Bytecode/dg.exp Message-ID: <200604122158.QAA05532@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Bytecode: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Bytecode/dg.exp diff -u llvm/test/Regression/Bytecode/dg.exp:1.2 llvm/test/Regression/Bytecode/dg.exp:1.3 --- llvm/test/Regression/Bytecode/dg.exp:1.2 Fri Nov 19 16:43:20 2004 +++ llvm/test/Regression/Bytecode/dg.exp Wed Apr 12 16:57:33 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:41 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:41 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/dg.exp Message-ID: <200604122158.QAA05531@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/PowerPC: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/CodeGen/PowerPC/dg.exp diff -u llvm/test/Regression/CodeGen/PowerPC/dg.exp:1.2 llvm/test/Regression/CodeGen/PowerPC/dg.exp:1.3 --- llvm/test/Regression/CodeGen/PowerPC/dg.exp:1.2 Fri Nov 19 16:43:37 2004 +++ llvm/test/Regression/CodeGen/PowerPC/dg.exp Wed Apr 12 16:57:34 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:36 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:36 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Assembler/dg.exp Message-ID: <200604122158.QAA05512@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Assembler: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Assembler/dg.exp diff -u llvm/test/Regression/Assembler/dg.exp:1.2 llvm/test/Regression/Assembler/dg.exp:1.3 --- llvm/test/Regression/Assembler/dg.exp:1.2 Fri Nov 19 16:43:14 2004 +++ llvm/test/Regression/Assembler/dg.exp Wed Apr 12 16:57:33 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:46 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:46 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/SCCP/dg.exp Message-ID: <200604122158.QAA05550@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/SCCP: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Transforms/SCCP/dg.exp diff -u llvm/test/Regression/Transforms/SCCP/dg.exp:1.2 llvm/test/Regression/Transforms/SCCP/dg.exp:1.3 --- llvm/test/Regression/Transforms/SCCP/dg.exp:1.2 Fri Nov 19 16:45:12 2004 +++ llvm/test/Regression/Transforms/SCCP/dg.exp Wed Apr 12 16:57:39 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:50 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:50 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/ADCE/dg.exp Message-ID: <200604122158.QAA05601@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/ADCE: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Transforms/ADCE/dg.exp diff -u llvm/test/Regression/Transforms/ADCE/dg.exp:1.2 llvm/test/Regression/Transforms/ADCE/dg.exp:1.3 --- llvm/test/Regression/Transforms/ADCE/dg.exp:1.2 Fri Nov 19 16:43:56 2004 +++ llvm/test/Regression/Transforms/ADCE/dg.exp Wed Apr 12 16:57:35 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:50 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:50 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/Inline/dg.exp Message-ID: <200604122158.QAA05631@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/Inline: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Transforms/Inline/dg.exp diff -u llvm/test/Regression/Transforms/Inline/dg.exp:1.2 llvm/test/Regression/Transforms/Inline/dg.exp:1.3 --- llvm/test/Regression/Transforms/Inline/dg.exp:1.2 Fri Nov 19 16:44:29 2004 +++ llvm/test/Regression/Transforms/Inline/dg.exp Wed Apr 12 16:57:38 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:50 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:50 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/TailDup/dg.exp Message-ID: <200604122158.QAA05643@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/TailDup: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Transforms/TailDup/dg.exp diff -u llvm/test/Regression/Transforms/TailDup/dg.exp:1.2 llvm/test/Regression/Transforms/TailDup/dg.exp:1.3 --- llvm/test/Regression/Transforms/TailDup/dg.exp:1.2 Fri Nov 19 16:45:22 2004 +++ llvm/test/Regression/Transforms/TailDup/dg.exp Wed Apr 12 16:57:40 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:49 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:49 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/LoopUnroll/dg.exp Message-ID: <200604122158.QAA05597@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/LoopUnroll: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Transforms/LoopUnroll/dg.exp diff -u llvm/test/Regression/Transforms/LoopUnroll/dg.exp:1.2 llvm/test/Regression/Transforms/LoopUnroll/dg.exp:1.3 --- llvm/test/Regression/Transforms/LoopUnroll/dg.exp:1.2 Fri Nov 19 16:44:39 2004 +++ llvm/test/Regression/Transforms/LoopUnroll/dg.exp Wed Apr 12 16:57:38 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:48 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:48 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/ExecutionEngine/dg.exp Message-ID: <200604122158.QAA05596@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/ExecutionEngine: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/ExecutionEngine/dg.exp diff -u llvm/test/Regression/ExecutionEngine/dg.exp:1.2 llvm/test/Regression/ExecutionEngine/dg.exp:1.3 --- llvm/test/Regression/ExecutionEngine/dg.exp:1.2 Fri Nov 19 16:43:48 2004 +++ llvm/test/Regression/ExecutionEngine/dg.exp Wed Apr 12 16:57:35 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:48 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:48 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/InstCombine/dg.exp Message-ID: <200604122158.QAA05595@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/InstCombine: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Transforms/InstCombine/dg.exp diff -u llvm/test/Regression/Transforms/InstCombine/dg.exp:1.2 llvm/test/Regression/Transforms/InstCombine/dg.exp:1.3 --- llvm/test/Regression/Transforms/InstCombine/dg.exp:1.2 Fri Nov 19 16:44:30 2004 +++ llvm/test/Regression/Transforms/InstCombine/dg.exp Wed Apr 12 16:57:38 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:45 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:45 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/SimplifyCFG/dg.exp Message-ID: <200604122158.QAA05547@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/SimplifyCFG: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Transforms/SimplifyCFG/dg.exp diff -u llvm/test/Regression/Transforms/SimplifyCFG/dg.exp:1.2 llvm/test/Regression/Transforms/SimplifyCFG/dg.exp:1.3 --- llvm/test/Regression/Transforms/SimplifyCFG/dg.exp:1.2 Fri Nov 19 16:45:16 2004 +++ llvm/test/Regression/Transforms/SimplifyCFG/dg.exp Wed Apr 12 16:57:39 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:33 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:33 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Analysis/Dominators/dg.exp Message-ID: <200604122158.QAA05504@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Analysis/Dominators: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Analysis/Dominators/dg.exp diff -u llvm/test/Regression/Analysis/Dominators/dg.exp:1.2 llvm/test/Regression/Analysis/Dominators/dg.exp:1.3 --- llvm/test/Regression/Analysis/Dominators/dg.exp:1.2 Fri Nov 19 16:42:59 2004 +++ llvm/test/Regression/Analysis/Dominators/dg.exp Wed Apr 12 16:57:33 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:46 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:46 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/LICM/dg.exp Message-ID: <200604122158.QAA05571@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/LICM: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Transforms/LICM/dg.exp diff -u llvm/test/Regression/Transforms/LICM/dg.exp:1.2 llvm/test/Regression/Transforms/LICM/dg.exp:1.3 --- llvm/test/Regression/Transforms/LICM/dg.exp:1.2 Fri Nov 19 16:44:34 2004 +++ llvm/test/Regression/Transforms/LICM/dg.exp Wed Apr 12 16:57:38 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:45 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:45 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/SparcV9/dg.exp Message-ID: <200604122158.QAA05538@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/SparcV9: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/CodeGen/SparcV9/dg.exp diff -u llvm/test/Regression/CodeGen/SparcV9/dg.exp:1.2 llvm/test/Regression/CodeGen/SparcV9/dg.exp:1.3 --- llvm/test/Regression/CodeGen/SparcV9/dg.exp:1.2 Fri Nov 19 16:43:40 2004 +++ llvm/test/Regression/CodeGen/SparcV9/dg.exp Wed Apr 12 16:57:35 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:46 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:46 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/GlobalDCE/dg.exp Message-ID: <200604122158.QAA05564@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/GlobalDCE: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Transforms/GlobalDCE/dg.exp diff -u llvm/test/Regression/Transforms/GlobalDCE/dg.exp:1.2 llvm/test/Regression/Transforms/GlobalDCE/dg.exp:1.3 --- llvm/test/Regression/Transforms/GlobalDCE/dg.exp:1.2 Fri Nov 19 16:44:21 2004 +++ llvm/test/Regression/Transforms/GlobalDCE/dg.exp Wed Apr 12 16:57:37 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:50 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:50 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/LowerSetJmp/dg.exp Message-ID: <200604122158.QAA05625@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/LowerSetJmp: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Transforms/LowerSetJmp/dg.exp diff -u llvm/test/Regression/Transforms/LowerSetJmp/dg.exp:1.2 llvm/test/Regression/Transforms/LowerSetJmp/dg.exp:1.3 --- llvm/test/Regression/Transforms/LowerSetJmp/dg.exp:1.2 Fri Nov 19 16:44:43 2004 +++ llvm/test/Regression/Transforms/LowerSetJmp/dg.exp Wed Apr 12 16:57:39 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:45 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:45 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/Generic/GC/dg.exp Message-ID: <200604122158.QAA05537@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/Generic/GC: dg.exp updated: 1.1 -> 1.2 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/CodeGen/Generic/GC/dg.exp diff -u llvm/test/Regression/CodeGen/Generic/GC/dg.exp:1.1 llvm/test/Regression/CodeGen/Generic/GC/dg.exp:1.2 --- llvm/test/Regression/CodeGen/Generic/GC/dg.exp:1.1 Sat Nov 20 17:51:38 2004 +++ llvm/test/Regression/CodeGen/Generic/GC/dg.exp Wed Apr 12 16:57:34 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:47 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:47 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/C++Frontend/dg.exp Message-ID: <200604122158.QAA05583@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/C++Frontend: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/C++Frontend/dg.exp diff -u llvm/test/Regression/C++Frontend/dg.exp:1.2 llvm/test/Regression/C++Frontend/dg.exp:1.3 --- llvm/test/Regression/C++Frontend/dg.exp:1.2 Fri Nov 19 16:43:22 2004 +++ llvm/test/Regression/C++Frontend/dg.exp Wed Apr 12 16:57:34 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:50 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:50 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/GCSE/dg.exp Message-ID: <200604122158.QAA05619@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/GCSE: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Transforms/GCSE/dg.exp diff -u llvm/test/Regression/Transforms/GCSE/dg.exp:1.2 llvm/test/Regression/Transforms/GCSE/dg.exp:1.3 --- llvm/test/Regression/Transforms/GCSE/dg.exp:1.2 Fri Nov 19 16:44:19 2004 +++ llvm/test/Regression/Transforms/GCSE/dg.exp Wed Apr 12 16:57:36 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:30 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:30 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Analysis/Andersens/dg.exp Message-ID: <200604122158.QAA05500@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Analysis/Andersens: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+2 -1) dg.exp | 3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index: llvm/test/Regression/Analysis/Andersens/dg.exp diff -u llvm/test/Regression/Analysis/Andersens/dg.exp:1.2 llvm/test/Regression/Analysis/Andersens/dg.exp:1.3 --- llvm/test/Regression/Analysis/Andersens/dg.exp:1.2 Fri Nov 19 16:42:49 2004 +++ llvm/test/Regression/Analysis/Andersens/dg.exp Wed Apr 12 16:57:32 2006 @@ -1,3 +1,4 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version + From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:50 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:50 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/SPARC/dg.exp Message-ID: <200604122158.QAA05632@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/SPARC: dg.exp updated: 1.1 -> 1.2 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/CodeGen/SPARC/dg.exp diff -u llvm/test/Regression/CodeGen/SPARC/dg.exp:1.1 llvm/test/Regression/CodeGen/SPARC/dg.exp:1.2 --- llvm/test/Regression/CodeGen/SPARC/dg.exp:1.1 Sat Feb 4 23:52:55 2006 +++ llvm/test/Regression/CodeGen/SPARC/dg.exp Wed Apr 12 16:57:34 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:46 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:46 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/ConstProp/dg.exp Message-ID: <200604122158.QAA05572@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/ConstProp: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Transforms/ConstProp/dg.exp diff -u llvm/test/Regression/Transforms/ConstProp/dg.exp:1.2 llvm/test/Regression/Transforms/ConstProp/dg.exp:1.3 --- llvm/test/Regression/Transforms/ConstProp/dg.exp:1.2 Fri Nov 19 16:44:05 2004 +++ llvm/test/Regression/Transforms/ConstProp/dg.exp Wed Apr 12 16:57:36 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:32 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:32 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Analysis/LoadVN/dg.exp Message-ID: <200604122158.QAA05502@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Analysis/LoadVN: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Analysis/LoadVN/dg.exp diff -u llvm/test/Regression/Analysis/LoadVN/dg.exp:1.2 llvm/test/Regression/Analysis/LoadVN/dg.exp:1.3 --- llvm/test/Regression/Analysis/LoadVN/dg.exp:1.2 Fri Nov 19 16:43:05 2004 +++ llvm/test/Regression/Analysis/LoadVN/dg.exp Wed Apr 12 16:57:33 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:50 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:50 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/LowerInvoke/dg.exp Message-ID: <200604122158.QAA05645@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/LowerInvoke: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Transforms/LowerInvoke/dg.exp diff -u llvm/test/Regression/Transforms/LowerInvoke/dg.exp:1.2 llvm/test/Regression/Transforms/LowerInvoke/dg.exp:1.3 --- llvm/test/Regression/Transforms/LowerInvoke/dg.exp:1.2 Fri Nov 19 16:44:42 2004 +++ llvm/test/Regression/Transforms/LowerInvoke/dg.exp Wed Apr 12 16:57:38 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:50 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:50 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/GlobalOpt/dg.exp Message-ID: <200604122158.QAA05628@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/GlobalOpt: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Transforms/GlobalOpt/dg.exp diff -u llvm/test/Regression/Transforms/GlobalOpt/dg.exp:1.2 llvm/test/Regression/Transforms/GlobalOpt/dg.exp:1.3 --- llvm/test/Regression/Transforms/GlobalOpt/dg.exp:1.2 Fri Nov 19 16:44:23 2004 +++ llvm/test/Regression/Transforms/GlobalOpt/dg.exp Wed Apr 12 16:57:37 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:48 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:48 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/PruneEH/dg.exp Message-ID: <200604122158.QAA05588@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/PruneEH: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Transforms/PruneEH/dg.exp diff -u llvm/test/Regression/Transforms/PruneEH/dg.exp:1.2 llvm/test/Regression/Transforms/PruneEH/dg.exp:1.3 --- llvm/test/Regression/Transforms/PruneEH/dg.exp:1.2 Fri Nov 19 16:45:01 2004 +++ llvm/test/Regression/Transforms/PruneEH/dg.exp Wed Apr 12 16:57:39 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:28 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:28 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Analysis/DSGraph/dg.exp Message-ID: <200604122158.QAA05498@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Analysis/DSGraph: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Analysis/DSGraph/dg.exp diff -u llvm/test/Regression/Analysis/DSGraph/dg.exp:1.2 llvm/test/Regression/Analysis/DSGraph/dg.exp:1.3 --- llvm/test/Regression/Analysis/DSGraph/dg.exp:1.2 Fri Nov 19 16:42:56 2004 +++ llvm/test/Regression/Analysis/DSGraph/dg.exp Wed Apr 12 16:57:32 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:50 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:50 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/LevelRaise/dg.exp Message-ID: <200604122158.QAA05647@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/LevelRaise: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Transforms/LevelRaise/dg.exp diff -u llvm/test/Regression/Transforms/LevelRaise/dg.exp:1.2 llvm/test/Regression/Transforms/LevelRaise/dg.exp:1.3 --- llvm/test/Regression/Transforms/LevelRaise/dg.exp:1.2 Fri Nov 19 16:44:36 2004 +++ llvm/test/Regression/Transforms/LevelRaise/dg.exp Wed Apr 12 16:57:38 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:50 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:50 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/Mem2Reg/dg.exp Message-ID: <200604122158.QAA05641@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/Mem2Reg: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Transforms/Mem2Reg/dg.exp diff -u llvm/test/Regression/Transforms/Mem2Reg/dg.exp:1.2 llvm/test/Regression/Transforms/Mem2Reg/dg.exp:1.3 --- llvm/test/Regression/Transforms/Mem2Reg/dg.exp:1.2 Fri Nov 19 16:44:56 2004 +++ llvm/test/Regression/Transforms/Mem2Reg/dg.exp Wed Apr 12 16:57:39 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:47 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:47 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/Generic/dg.exp Message-ID: <200604122158.QAA05563@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/Generic: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/CodeGen/Generic/dg.exp diff -u llvm/test/Regression/CodeGen/Generic/dg.exp:1.2 llvm/test/Regression/CodeGen/Generic/dg.exp:1.3 --- llvm/test/Regression/CodeGen/Generic/dg.exp:1.2 Fri Nov 19 16:43:33 2004 +++ llvm/test/Regression/CodeGen/Generic/dg.exp Wed Apr 12 16:57:34 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:41 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:41 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/ArgumentPromotion/dg.exp Message-ID: <200604122158.QAA05529@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/ArgumentPromotion: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Transforms/ArgumentPromotion/dg.exp diff -u llvm/test/Regression/Transforms/ArgumentPromotion/dg.exp:1.2 llvm/test/Regression/Transforms/ArgumentPromotion/dg.exp:1.3 --- llvm/test/Regression/Transforms/ArgumentPromotion/dg.exp:1.2 Fri Nov 19 16:43:58 2004 +++ llvm/test/Regression/Transforms/ArgumentPromotion/dg.exp Wed Apr 12 16:57:35 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:50 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:50 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/ScalarRepl/dg.exp Message-ID: <200604122158.QAA05635@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/ScalarRepl: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Transforms/ScalarRepl/dg.exp diff -u llvm/test/Regression/Transforms/ScalarRepl/dg.exp:1.2 llvm/test/Regression/Transforms/ScalarRepl/dg.exp:1.3 --- llvm/test/Regression/Transforms/ScalarRepl/dg.exp:1.2 Fri Nov 19 16:45:14 2004 +++ llvm/test/Regression/Transforms/ScalarRepl/dg.exp Wed Apr 12 16:57:39 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:41 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:41 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Analysis/GlobalsModRef/dg.exp Message-ID: <200604122158.QAA05526@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Analysis/GlobalsModRef: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Analysis/GlobalsModRef/dg.exp diff -u llvm/test/Regression/Analysis/GlobalsModRef/dg.exp:1.2 llvm/test/Regression/Analysis/GlobalsModRef/dg.exp:1.3 --- llvm/test/Regression/Analysis/GlobalsModRef/dg.exp:1.2 Fri Nov 19 16:43:02 2004 +++ llvm/test/Regression/Analysis/GlobalsModRef/dg.exp Wed Apr 12 16:57:33 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:46 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:46 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/DSAnalysis/dg.exp Message-ID: <200604122158.QAA05556@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/DSAnalysis: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Transforms/DSAnalysis/dg.exp diff -u llvm/test/Regression/Transforms/DSAnalysis/dg.exp:1.2 llvm/test/Regression/Transforms/DSAnalysis/dg.exp:1.3 --- llvm/test/Regression/Transforms/DSAnalysis/dg.exp:1.2 Fri Nov 19 16:44:10 2004 +++ llvm/test/Regression/Transforms/DSAnalysis/dg.exp Wed Apr 12 16:57:36 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:47 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:47 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/CondProp/dg.exp Message-ID: <200604122158.QAA05584@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/CondProp: dg.exp updated: 1.1 -> 1.2 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Transforms/CondProp/dg.exp diff -u llvm/test/Regression/Transforms/CondProp/dg.exp:1.1 llvm/test/Regression/Transforms/CondProp/dg.exp:1.2 --- llvm/test/Regression/Transforms/CondProp/dg.exp:1.1 Fri Apr 15 14:24:36 2005 +++ llvm/test/Regression/Transforms/CondProp/dg.exp Wed Apr 12 16:57:36 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:48 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:48 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/LowerSwitch/dg.exp Message-ID: <200604122158.QAA05591@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/LowerSwitch: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Transforms/LowerSwitch/dg.exp diff -u llvm/test/Regression/Transforms/LowerSwitch/dg.exp:1.2 llvm/test/Regression/Transforms/LowerSwitch/dg.exp:1.3 --- llvm/test/Regression/Transforms/LowerSwitch/dg.exp:1.2 Fri Nov 19 16:44:45 2004 +++ llvm/test/Regression/Transforms/LowerSwitch/dg.exp Wed Apr 12 16:57:39 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:50 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:50 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/BlockPlacement/dg.exp Message-ID: <200604122158.QAA05633@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/BlockPlacement: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Transforms/BlockPlacement/dg.exp diff -u llvm/test/Regression/Transforms/BlockPlacement/dg.exp:1.2 llvm/test/Regression/Transforms/BlockPlacement/dg.exp:1.3 --- llvm/test/Regression/Transforms/BlockPlacement/dg.exp:1.2 Fri Nov 19 16:44:00 2004 +++ llvm/test/Regression/Transforms/BlockPlacement/dg.exp Wed Apr 12 16:57:35 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:50 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:50 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/Reassociate/dg.exp Message-ID: <200604122158.QAA05613@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/Reassociate: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Transforms/Reassociate/dg.exp diff -u llvm/test/Regression/Transforms/Reassociate/dg.exp:1.2 llvm/test/Regression/Transforms/Reassociate/dg.exp:1.3 --- llvm/test/Regression/Transforms/Reassociate/dg.exp:1.2 Fri Nov 19 16:45:09 2004 +++ llvm/test/Regression/Transforms/Reassociate/dg.exp Wed Apr 12 16:57:39 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:46 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:46 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/X86/dg.exp Message-ID: <200604122158.QAA05570@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/X86: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/CodeGen/X86/dg.exp diff -u llvm/test/Regression/CodeGen/X86/dg.exp:1.2 llvm/test/Regression/CodeGen/X86/dg.exp:1.3 --- llvm/test/Regression/CodeGen/X86/dg.exp:1.2 Fri Nov 19 16:43:43 2004 +++ llvm/test/Regression/CodeGen/X86/dg.exp Wed Apr 12 16:57:35 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:45 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:45 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/TailCallElim/dg.exp Message-ID: <200604122158.QAA05545@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/TailCallElim: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Transforms/TailCallElim/dg.exp diff -u llvm/test/Regression/Transforms/TailCallElim/dg.exp:1.2 llvm/test/Regression/Transforms/TailCallElim/dg.exp:1.3 --- llvm/test/Regression/Transforms/TailCallElim/dg.exp:1.2 Fri Nov 19 16:45:18 2004 +++ llvm/test/Regression/Transforms/TailCallElim/dg.exp Wed Apr 12 16:57:40 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:50 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:50 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/DecomposeMultiDimRefs/dg.exp Message-ID: <200604122158.QAA05606@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/DecomposeMultiDimRefs: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Transforms/DecomposeMultiDimRefs/dg.exp diff -u llvm/test/Regression/Transforms/DecomposeMultiDimRefs/dg.exp:1.2 llvm/test/Regression/Transforms/DecomposeMultiDimRefs/dg.exp:1.3 --- llvm/test/Regression/Transforms/DecomposeMultiDimRefs/dg.exp:1.2 Fri Nov 19 16:44:15 2004 +++ llvm/test/Regression/Transforms/DecomposeMultiDimRefs/dg.exp Wed Apr 12 16:57:36 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:45 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:45 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/FunctionResolve/dg.exp Message-ID: <200604122158.QAA05554@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/FunctionResolve: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Transforms/FunctionResolve/dg.exp diff -u llvm/test/Regression/Transforms/FunctionResolve/dg.exp:1.2 llvm/test/Regression/Transforms/FunctionResolve/dg.exp:1.3 --- llvm/test/Regression/Transforms/FunctionResolve/dg.exp:1.2 Fri Nov 19 16:44:17 2004 +++ llvm/test/Regression/Transforms/FunctionResolve/dg.exp Wed Apr 12 16:57:36 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:47 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:47 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/CodeExtractor/dg.exp Message-ID: <200604122158.QAA05577@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/CodeExtractor: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Transforms/CodeExtractor/dg.exp diff -u llvm/test/Regression/Transforms/CodeExtractor/dg.exp:1.2 llvm/test/Regression/Transforms/CodeExtractor/dg.exp:1.3 --- llvm/test/Regression/Transforms/CodeExtractor/dg.exp:1.2 Fri Nov 19 16:44:03 2004 +++ llvm/test/Regression/Transforms/CodeExtractor/dg.exp Wed Apr 12 16:57:36 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:36 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:36 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Analysis/LoopInfo/dg.exp Message-ID: <200604122158.QAA05507@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Analysis/LoopInfo: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Analysis/LoopInfo/dg.exp diff -u llvm/test/Regression/Analysis/LoopInfo/dg.exp:1.2 llvm/test/Regression/Analysis/LoopInfo/dg.exp:1.3 --- llvm/test/Regression/Analysis/LoopInfo/dg.exp:1.2 Fri Nov 19 16:43:10 2004 +++ llvm/test/Regression/Analysis/LoopInfo/dg.exp Wed Apr 12 16:57:33 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:48 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:48 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/LoopSimplify/dg.exp Message-ID: <200604122158.QAA05582@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/LoopSimplify: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Transforms/LoopSimplify/dg.exp diff -u llvm/test/Regression/Transforms/LoopSimplify/dg.exp:1.2 llvm/test/Regression/Transforms/LoopSimplify/dg.exp:1.3 --- llvm/test/Regression/Transforms/LoopSimplify/dg.exp:1.2 Fri Nov 19 16:44:37 2004 +++ llvm/test/Regression/Transforms/LoopSimplify/dg.exp Wed Apr 12 16:57:38 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:50 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:50 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/CorrelatedExprs/dg.exp Message-ID: <200604122158.QAA05622@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/CorrelatedExprs: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Transforms/CorrelatedExprs/dg.exp diff -u llvm/test/Regression/Transforms/CorrelatedExprs/dg.exp:1.2 llvm/test/Regression/Transforms/CorrelatedExprs/dg.exp:1.3 --- llvm/test/Regression/Transforms/CorrelatedExprs/dg.exp:1.2 Fri Nov 19 16:44:09 2004 +++ llvm/test/Regression/Transforms/CorrelatedExprs/dg.exp Wed Apr 12 16:57:36 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:36 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:36 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Analysis/BasicAA/dg.exp Message-ID: <200604122158.QAA05509@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Analysis/BasicAA: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Analysis/BasicAA/dg.exp diff -u llvm/test/Regression/Analysis/BasicAA/dg.exp:1.2 llvm/test/Regression/Analysis/BasicAA/dg.exp:1.3 --- llvm/test/Regression/Analysis/BasicAA/dg.exp:1.2 Fri Nov 19 16:42:53 2004 +++ llvm/test/Regression/Analysis/BasicAA/dg.exp Wed Apr 12 16:57:32 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:50 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:50 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/RaiseAllocations/dg.exp Message-ID: <200604122158.QAA05620@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/RaiseAllocations: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Transforms/RaiseAllocations/dg.exp diff -u llvm/test/Regression/Transforms/RaiseAllocations/dg.exp:1.2 llvm/test/Regression/Transforms/RaiseAllocations/dg.exp:1.3 --- llvm/test/Regression/Transforms/RaiseAllocations/dg.exp:1.2 Fri Nov 19 16:45:05 2004 +++ llvm/test/Regression/Transforms/RaiseAllocations/dg.exp Wed Apr 12 16:57:39 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:46 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:46 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/DeadStoreElimination/dg.exp Message-ID: <200604122158.QAA05574@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/DeadStoreElimination: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Transforms/DeadStoreElimination/dg.exp diff -u llvm/test/Regression/Transforms/DeadStoreElimination/dg.exp:1.2 llvm/test/Regression/Transforms/DeadStoreElimination/dg.exp:1.3 --- llvm/test/Regression/Transforms/DeadStoreElimination/dg.exp:1.2 Fri Nov 19 16:44:13 2004 +++ llvm/test/Regression/Transforms/DeadStoreElimination/dg.exp Wed Apr 12 16:57:36 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:38 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:38 -0500 Subject: [llvm-commits] CVS: llvm/test/lib/llvm-dg.exp Message-ID: <200604122158.QAA05516@zion.cs.uiuc.edu> Changes in directory llvm/test/lib: llvm-dg.exp updated: 1.12 -> 1.13 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+6 -2) llvm-dg.exp | 8 ++++++-- 1 files changed, 6 insertions(+), 2 deletions(-) Index: llvm/test/lib/llvm-dg.exp diff -u llvm/test/lib/llvm-dg.exp:1.12 llvm/test/lib/llvm-dg.exp:1.13 --- llvm/test/lib/llvm-dg.exp:1.12 Wed Mar 8 16:32:20 2006 +++ llvm/test/lib/llvm-dg.exp Wed Apr 12 16:57:40 2006 @@ -1,4 +1,5 @@ -proc llvm-runtest { programs objdir srcdir subdir target_triplet llvmgcc llvmgxx prcontext} { +proc llvm-runtest { programs objdir srcdir subdir target_triplet llvmgcc llvmgxx prcontext llvmgcc_version} { + set timeout 60 @@ -65,7 +66,6 @@ puts $scriptFileId $new_runline } elseif {[regexp {XFAIL:[ *](.+)} $line match targets]} { set targets - #split up target if more then 1 specified foreach target [split $targets ,] { @@ -73,6 +73,10 @@ set outcome XFAIL } elseif { [regexp $target $target_triplet match] } { set outcome XFAIL + } elseif { [regexp {llvmgcc(([0-9]+)|([0-9]+[.][0-9]+))} $target match submatch submatch2] } { + if { [regexp ^($submatch)$|^(($submatch)(\.)) $llvmgcc_version match] } { + set outcome XFAIL + } } } From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:47 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:47 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/IndVarsSimplify/dg.exp Message-ID: <200604122158.QAA05573@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/IndVarsSimplify: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Transforms/IndVarsSimplify/dg.exp diff -u llvm/test/Regression/Transforms/IndVarsSimplify/dg.exp:1.2 llvm/test/Regression/Transforms/IndVarsSimplify/dg.exp:1.3 --- llvm/test/Regression/Transforms/IndVarsSimplify/dg.exp:1.2 Fri Nov 19 16:44:27 2004 +++ llvm/test/Regression/Transforms/IndVarsSimplify/dg.exp Wed Apr 12 16:57:38 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:46 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:46 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/LoopStrengthReduce/dg.exp Message-ID: <200604122158.QAA05552@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/LoopStrengthReduce: dg.exp updated: 1.1 -> 1.2 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Transforms/LoopStrengthReduce/dg.exp diff -u llvm/test/Regression/Transforms/LoopStrengthReduce/dg.exp:1.1 llvm/test/Regression/Transforms/LoopStrengthReduce/dg.exp:1.2 --- llvm/test/Regression/Transforms/LoopStrengthReduce/dg.exp:1.1 Sun Mar 6 15:42:59 2005 +++ llvm/test/Regression/Transforms/LoopStrengthReduce/dg.exp Wed Apr 12 16:57:38 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:50 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:50 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/SimplifyLibCalls/dg.exp Message-ID: <200604122158.QAA05638@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/SimplifyLibCalls: dg.exp updated: 1.1 -> 1.2 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Transforms/SimplifyLibCalls/dg.exp diff -u llvm/test/Regression/Transforms/SimplifyLibCalls/dg.exp:1.1 llvm/test/Regression/Transforms/SimplifyLibCalls/dg.exp:1.2 --- llvm/test/Regression/Transforms/SimplifyLibCalls/dg.exp:1.1 Sun Apr 24 21:50:08 2005 +++ llvm/test/Regression/Transforms/SimplifyLibCalls/dg.exp Wed Apr 12 16:57:39 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:48 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:48 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/LoopUnswitch/dg.exp Message-ID: <200604122158.QAA05587@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/LoopUnswitch: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Transforms/LoopUnswitch/dg.exp diff -u llvm/test/Regression/Transforms/LoopUnswitch/dg.exp:1.2 llvm/test/Regression/Transforms/LoopUnswitch/dg.exp:1.3 --- llvm/test/Regression/Transforms/LoopUnswitch/dg.exp:1.2 Fri Nov 19 16:44:40 2004 +++ llvm/test/Regression/Transforms/LoopUnswitch/dg.exp Wed Apr 12 16:57:38 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:50 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:50 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/DeadArgElim/dg.exp Message-ID: <200604122158.QAA05627@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/DeadArgElim: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Transforms/DeadArgElim/dg.exp diff -u llvm/test/Regression/Transforms/DeadArgElim/dg.exp:1.2 llvm/test/Regression/Transforms/DeadArgElim/dg.exp:1.3 --- llvm/test/Regression/Transforms/DeadArgElim/dg.exp:1.2 Fri Nov 19 16:44:12 2004 +++ llvm/test/Regression/Transforms/DeadArgElim/dg.exp Wed Apr 12 16:57:36 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:50 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:50 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/ConstantMerge/dg.exp Message-ID: <200604122158.QAA05623@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/ConstantMerge: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Transforms/ConstantMerge/dg.exp diff -u llvm/test/Regression/Transforms/ConstantMerge/dg.exp:1.2 llvm/test/Regression/Transforms/ConstantMerge/dg.exp:1.3 --- llvm/test/Regression/Transforms/ConstantMerge/dg.exp:1.2 Fri Nov 19 16:44:07 2004 +++ llvm/test/Regression/Transforms/ConstantMerge/dg.exp Wed Apr 12 16:57:36 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:41 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:41 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/CBackend/dg.exp Message-ID: <200604122158.QAA05530@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/CBackend: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/CodeGen/CBackend/dg.exp diff -u llvm/test/Regression/CodeGen/CBackend/dg.exp:1.2 llvm/test/Regression/CodeGen/CBackend/dg.exp:1.3 --- llvm/test/Regression/CodeGen/CBackend/dg.exp:1.2 Fri Nov 19 16:43:28 2004 +++ llvm/test/Regression/CodeGen/CBackend/dg.exp Wed Apr 12 16:57:34 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:41 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:41 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Verifier/2004-01-22-FloatNormalization.ll 2005-03-21-UndefinedTypeReference.ll dg.exp Message-ID: <200604122158.QAA05522@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Verifier: 2004-01-22-FloatNormalization.ll updated: 1.2 -> 1.3 2005-03-21-UndefinedTypeReference.ll updated: 1.1 -> 1.2 dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+2 -3) 2004-01-22-FloatNormalization.ll | 2 +- 2005-03-21-UndefinedTypeReference.ll | 1 - dg.exp | 2 +- 3 files changed, 2 insertions(+), 3 deletions(-) Index: llvm/test/Regression/Verifier/2004-01-22-FloatNormalization.ll diff -u llvm/test/Regression/Verifier/2004-01-22-FloatNormalization.ll:1.2 llvm/test/Regression/Verifier/2004-01-22-FloatNormalization.ll:1.3 --- llvm/test/Regression/Verifier/2004-01-22-FloatNormalization.ll:1.2 Fri Dec 23 10:13:52 2005 +++ llvm/test/Regression/Verifier/2004-01-22-FloatNormalization.ll Wed Apr 12 16:57:40 2006 @@ -1,5 +1,5 @@ ; RUN: not llvm-as < %s -o /dev/null -f -; XFAIL: * +; XFAIL: 3.4 ; make sure that invalid 'float' values are caught. Index: llvm/test/Regression/Verifier/2005-03-21-UndefinedTypeReference.ll diff -u llvm/test/Regression/Verifier/2005-03-21-UndefinedTypeReference.ll:1.1 llvm/test/Regression/Verifier/2005-03-21-UndefinedTypeReference.ll:1.2 --- llvm/test/Regression/Verifier/2005-03-21-UndefinedTypeReference.ll:1.1 Mon Mar 21 00:24:53 2005 +++ llvm/test/Regression/Verifier/2005-03-21-UndefinedTypeReference.ll Wed Apr 12 16:57:40 2006 @@ -1,5 +1,4 @@ ; RUN: not llvm-as -f %s -o /dev/null - void %test() { malloc %InvalidType ret void Index: llvm/test/Regression/Verifier/dg.exp diff -u llvm/test/Regression/Verifier/dg.exp:1.2 llvm/test/Regression/Verifier/dg.exp:1.3 --- llvm/test/Regression/Verifier/dg.exp:1.2 Fri Nov 19 16:45:25 2004 +++ llvm/test/Regression/Verifier/dg.exp Wed Apr 12 16:57:40 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From tbrethou at cs.uiuc.edu Wed Apr 12 16:58:50 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Wed, 12 Apr 2006 16:58:50 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/IPConstantProp/dg.exp Message-ID: <200604122158.QAA05640@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/IPConstantProp: dg.exp updated: 1.2 -> 1.3 --- Log message: Added the ability to xfail based on llvmgcc version --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Transforms/IPConstantProp/dg.exp diff -u llvm/test/Regression/Transforms/IPConstantProp/dg.exp:1.2 llvm/test/Regression/Transforms/IPConstantProp/dg.exp:1.3 --- llvm/test/Regression/Transforms/IPConstantProp/dg.exp:1.2 Fri Nov 19 16:44:25 2004 +++ llvm/test/Regression/Transforms/IPConstantProp/dg.exp Wed Apr 12 16:57:37 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From reid at x10sys.com Wed Apr 12 18:15:22 2006 From: reid at x10sys.com (Reid Spencer) Date: Wed, 12 Apr 2006 18:15:22 -0500 Subject: [llvm-commits] CVS: llvm/utils/Makefile Message-ID: <200604122315.SAA06289@zion.cs.uiuc.edu> Changes in directory llvm/utils: Makefile updated: 1.10 -> 1.11 --- Log message: Fix a typo in the name of a file. --- Diffs of the changes: (+1 -1) Makefile | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/utils/Makefile diff -u llvm/utils/Makefile:1.10 llvm/utils/Makefile:1.11 --- llvm/utils/Makefile:1.10 Wed Apr 12 15:54:01 2006 +++ llvm/utils/Makefile Wed Apr 12 18:15:10 2006 @@ -14,7 +14,7 @@ DSAclean.py DSAextract.py emacs findsym.pl GenLibDeps.pl \ getsrcs.sh importNLT.pl llvmdo llvmgrep llvm-native-gcc \ llvm-native-gxx makellvm NightlyTest.gnuplot NightlyTest.pl \ - NightlyTestTemplate.html NLT.schema parseNTL.pl plotNLT.pl \ + NightlyTestTemplate.html NLT.schema parseNLT.pl plotNLT.pl \ profile.pl RegressionFinder.pl userloc.pl webNLT.pl \ vim llvm-config From evan.cheng at apple.com Wed Apr 12 18:42:56 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 12 Apr 2006 18:42:56 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrMMX.td X86InstrSSE.td Message-ID: <200604122342.SAA06532@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrMMX.td updated: 1.10 -> 1.11 X86InstrSSE.td updated: 1.80 -> 1.81 --- Log message: SSE / SSE2 conversion intrinsics. --- Diffs of the changes: (+99 -33) X86InstrMMX.td | 24 ++++++++++++ X86InstrSSE.td | 108 ++++++++++++++++++++++++++++++++++++++++----------------- 2 files changed, 99 insertions(+), 33 deletions(-) Index: llvm/lib/Target/X86/X86InstrMMX.td diff -u llvm/lib/Target/X86/X86InstrMMX.td:1.10 llvm/lib/Target/X86/X86InstrMMX.td:1.11 --- llvm/lib/Target/X86/X86InstrMMX.td:1.10 Tue Apr 11 01:57:30 2006 +++ llvm/lib/Target/X86/X86InstrMMX.td Wed Apr 12 18:42:44 2006 @@ -14,7 +14,13 @@ //===----------------------------------------------------------------------===// // Instruction templates -// MMXi8 - MMX instructions with ImmT == Imm8 and TB prefix. +// MMXI - MMX instructions with TB prefix. +// MMX2I - MMX / SSE2 instructions with TB and OpSize prefixes. +// MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix. +class MMXI o, Format F, dag ops, string asm, list pattern> + : I, TB, Requires<[HasMMX]>; +class MMX2I o, Format F, dag ops, string asm, list pattern> + : I, TB, OpSize, Requires<[HasSSE2]>; class MMXIi8 o, Format F, dag ops, string asm, list pattern> : X86Inst, TB, Requires<[HasMMX]> { let Pattern = pattern; @@ -51,12 +57,28 @@ Requires<[HasMMX]>; // Conversion instructions +def CVTPI2PSrr : MMXI<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src), + "cvtpi2ps {$src, $dst|$dst, $src}", []>; +def CVTPI2PSrm : MMXI<0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src), + "cvtpi2ps {$src, $dst|$dst, $src}", []>; +def CVTPI2PDrr : MMX2I<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src), + "cvtpi2pd {$src, $dst|$dst, $src}", []>; +def CVTPI2PDrm : MMX2I<0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src), + "cvtpi2pd {$src, $dst|$dst, $src}", []>; def CVTTPS2PIrr: I<0x2C, MRMSrcReg, (ops VR64:$dst, VR128:$src), "cvttps2pi {$src, $dst|$dst, $src}", []>, TB, Requires<[HasSSE2]>; def CVTTPS2PIrm: I<0x2C, MRMSrcMem, (ops VR64:$dst, f64mem:$src), "cvttps2pi {$src, $dst|$dst, $src}", []>, TB, Requires<[HasMMX]>; +def CVTPS2PIrr : MMXI<0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src), + "cvtps2pi {$src, $dst|$dst, $src}", []>; +def CVTPS2PIrm : MMXI<0x2D, MRMSrcMem, (ops VR64:$dst, f64mem:$src), + "cvtps2pi {$src, $dst|$dst, $src}", []>; +def CVTPD2PIrr : MMX2I<0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src), + "cvtpd2pi {$src, $dst|$dst, $src}", []>; +def CVTPD2PIrm : MMX2I<0x2D, MRMSrcMem, (ops VR64:$dst, f128mem:$src), + "cvtpd2pi {$src, $dst|$dst, $src}", []>; // Shuffle and unpack instructions def PSHUFWri : MMXIi8<0x70, MRMSrcReg, Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.80 llvm/lib/Target/X86/X86InstrSSE.td:1.81 --- llvm/lib/Target/X86/X86InstrSSE.td:1.80 Wed Apr 12 16:21:57 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Wed Apr 12 18:42:44 2006 @@ -479,11 +479,6 @@ } // Conversion instructions -def CVTSS2SIrr: SSI<0x2D, MRMSrcReg, (ops R32:$dst, FR32:$src), - "cvtss2si {$src, $dst|$dst, $src}", []>; -def CVTSS2SIrm: SSI<0x2D, MRMSrcMem, (ops R32:$dst, f32mem:$src), - "cvtss2si {$src, $dst|$dst, $src}", []>; - def CVTTSS2SIrr: SSI<0x2C, MRMSrcReg, (ops R32:$dst, FR32:$src), "cvttss2si {$src, $dst|$dst, $src}", [(set R32:$dst, (fp_to_sint FR32:$src))]>; @@ -514,6 +509,7 @@ def CVTSI2SDrm: SDI<0x2A, MRMSrcMem, (ops FR64:$dst, i32mem:$src), "cvtsi2sd {$src, $dst|$dst, $src}", [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>; + // SSE2 instructions with XS prefix def CVTSS2SDrr: I<0x5A, MRMSrcReg, (ops FR64:$dst, FR32:$src), "cvtss2sd {$src, $dst|$dst, $src}", @@ -524,7 +520,23 @@ [(set FR64:$dst, (fextend (loadf32 addr:$src)))]>, XS, Requires<[HasSSE2]>; -// Aliases to match intrinsics which expect XMM operand(s). +// Match intrinsics which expect XMM operand(s). +def CVTSS2SIrr: SSI<0x2D, MRMSrcReg, (ops R32:$dst, VR128:$src), + "cvtss2si {$src, $dst|$dst, $src}", + [(set R32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>; +def CVTSS2SIrm: SSI<0x2D, MRMSrcMem, (ops R32:$dst, f32mem:$src), + "cvtss2si {$src, $dst|$dst, $src}", + [(set R32:$dst, (int_x86_sse_cvtss2si + (loadv4f32 addr:$src)))]>; + +// Aliases for intrinsics +def Int_CVTTSS2SIrr: SSI<0x2C, MRMSrcReg, (ops R32:$dst, VR128:$src), + "cvttss2si {$src, $dst|$dst, $src}", + [(set R32:$dst, (int_x86_sse_cvttss2si VR128:$src))]>; +def Int_CVTTSS2SIrm: SSI<0x2C, MRMSrcMem, (ops R32:$dst, f32mem:$src), + "cvttss2si {$src, $dst|$dst, $src}", + [(set R32:$dst, (int_x86_sse_cvttss2si + (loadv4f32 addr:$src)))]>; def Int_CVTTSD2SIrr: SDI<0x2C, MRMSrcReg, (ops R32:$dst, VR128:$src), "cvttsd2si {$src, $dst|$dst, $src}", [(set R32:$dst, (int_x86_sse2_cvttsd2si VR128:$src))]>; @@ -533,13 +545,18 @@ [(set R32:$dst, (int_x86_sse2_cvttsd2si (loadv2f64 addr:$src)))]>; -def CVTSD2SIrr: SDI<0x2D, MRMSrcReg, (ops R32:$dst, VR128:$src), - "cvtsd2si {$src, $dst|$dst, $src}", - [(set R32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>; -def CVTSD2SIrm: SDI<0x2D, MRMSrcMem, (ops R32:$dst, f128mem:$src), - "cvtsd2si {$src, $dst|$dst, $src}", - [(set R32:$dst, (int_x86_sse2_cvtsd2si - (loadv2f64 addr:$src)))]>; +let isTwoAddress = 1 in { +def Int_CVTSI2SSrr: SSI<0x2A, MRMSrcReg, + (ops VR128:$dst, VR128:$src1, R32:$src2), + "cvtsi2ss {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1, + R32:$src2))]>; +def Int_CVTSI2SSrm: SSI<0x2A, MRMSrcMem, + (ops VR128:$dst, VR128:$src1, i32mem:$src2), + "cvtsi2ss {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1, + (loadi32 addr:$src2)))]>; +} // Comparison instructions let isTwoAddress = 1 in { @@ -816,16 +833,6 @@ MOVHLPS_shuffle_mask)))]>; } -// Conversion instructions -def CVTPI2PSrr : PSI<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src), - "cvtpi2ps {$src, $dst|$dst, $src}", []>; -def CVTPI2PSrm : PSI<0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src), - "cvtpi2ps {$src, $dst|$dst, $src}", []>; -def CVTPI2PDrr : PDI<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src), - "cvtpi2pd {$src, $dst|$dst, $src}", []>; -def CVTPI2PDrm : PDI<0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src), - "cvtpi2pd {$src, $dst|$dst, $src}", []>; - // SSE2 instructions without OpSize prefix def CVTDQ2PSrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src), "cvtdq2ps {$src, $dst|$dst, $src}", @@ -848,15 +855,6 @@ (bc_v4i32 (loadv2i64 addr:$src))))]>, XS, Requires<[HasSSE2]>; -def CVTPS2PIrr : PSI<0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src), - "cvtps2pi {$src, $dst|$dst, $src}", []>; -def CVTPS2PIrm : PSI<0x2D, MRMSrcMem, (ops VR64:$dst, f64mem:$src), - "cvtps2pi {$src, $dst|$dst, $src}", []>; -def CVTPD2PIrr : PDI<0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src), - "cvtpd2pi {$src, $dst|$dst, $src}", []>; -def CVTPD2PIrm : PDI<0x2D, MRMSrcMem, (ops VR64:$dst, f128mem:$src), - "cvtpd2pi {$src, $dst|$dst, $src}", []>; - def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src), "cvtps2dq {$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>; @@ -912,6 +910,52 @@ [(set VR128:$dst, (int_x86_sse2_cvtpd2ps (loadv2f64 addr:$src)))]>; + +def CVTSD2SIrr: SDI<0x2D, MRMSrcReg, (ops R32:$dst, VR128:$src), + "cvtsd2si {$src, $dst|$dst, $src}", + [(set R32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>; +def CVTSD2SIrm: SDI<0x2D, MRMSrcMem, (ops R32:$dst, f128mem:$src), + "cvtsd2si {$src, $dst|$dst, $src}", + [(set R32:$dst, (int_x86_sse2_cvtsd2si + (loadv2f64 addr:$src)))]>; + +// Match intrinsics which expect XMM operand(s). +// Aliases for intrinsics +let isTwoAddress = 1 in { +def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg, + (ops VR128:$dst, VR128:$src1, R32:$src2), + "cvtsi2sd {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1, + R32:$src2))]>; +def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem, + (ops VR128:$dst, VR128:$src1, i32mem:$src2), + "cvtsi2sd {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1, + (loadi32 addr:$src2)))]>; +def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg, + (ops VR128:$dst, VR128:$src1, VR128:$src2), + "cvtsd2ss {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1, + VR128:$src2))]>; +def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem, + (ops VR128:$dst, VR128:$src1, f64mem:$src2), + "cvtsd2ss {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1, + (loadv2f64 addr:$src2)))]>; +def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg, + (ops VR128:$dst, VR128:$src1, VR128:$src2), + "cvtss2sd {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1, + VR128:$src2))]>, XS, + Requires<[HasSSE2]>; +def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem, + (ops VR128:$dst, VR128:$src1, f32mem:$src2), + "cvtss2sd {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1, + (loadv4f32 addr:$src2)))]>, XS, + Requires<[HasSSE2]>; +} + // Arithmetic let isTwoAddress = 1 in { let isCommutable = 1 in { From evan.cheng at apple.com Wed Apr 12 18:42:57 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 12 Apr 2006 18:42:57 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/IntrinsicsX86.td Message-ID: <200604122342.SAA06536@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm: IntrinsicsX86.td updated: 1.20 -> 1.21 --- Log message: SSE / SSE2 conversion intrinsics. --- Diffs of the changes: (+11 -7) IntrinsicsX86.td | 18 +++++++++++------- 1 files changed, 11 insertions(+), 7 deletions(-) Index: llvm/include/llvm/IntrinsicsX86.td diff -u llvm/include/llvm/IntrinsicsX86.td:1.20 llvm/include/llvm/IntrinsicsX86.td:1.21 --- llvm/include/llvm/IntrinsicsX86.td:1.20 Wed Apr 12 00:20:24 2006 +++ llvm/include/llvm/IntrinsicsX86.td Wed Apr 12 18:42:44 2006 @@ -112,16 +112,11 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse_cvtss2si : GCCBuiltin<"__builtin_ia32_cvtss2si">, Intrinsic<[llvm_int_ty, llvm_v4f32_ty], [IntrNoMem]>; - def int_x86_sse_cvtps2pi : GCCBuiltin<"__builtin_ia32_cvtps2pi">, - Intrinsic<[llvm_v2i32_ty, llvm_v4i32_ty], [IntrNoMem]>; def int_x86_sse_cvttss2si : GCCBuiltin<"__builtin_ia32_cvttss2si">, Intrinsic<[llvm_int_ty, llvm_v4f32_ty], [IntrNoMem]>; - def int_x86_sse_cvttps2pi : GCCBuiltin<"__builtin_ia32_cvttps2pi">, - Intrinsic<[llvm_v2i32_ty, llvm_v4i32_ty], [IntrNoMem]>; def int_x86_sse_cvtsi2ss : GCCBuiltin<"__builtin_ia32_cvtsi2ss">, - Intrinsic<[llvm_v4f32_ty, llvm_int_ty], [IntrNoMem]>; - def int_x86_sse_cvtpi2ps : GCCBuiltin<"__builtin_ia32_cvtpi2ps">, - Intrinsic<[llvm_v4f32_ty, llvm_v2i32_ty], [IntrNoMem]>; + Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, + llvm_int_ty], [IntrNoMem]>; } // SIMD load ops @@ -287,6 +282,15 @@ Intrinsic<[llvm_int_ty, llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_cvttsd2si : GCCBuiltin<"__builtin_ia32_cvttsd2si">, Intrinsic<[llvm_int_ty, llvm_v2f64_ty], [IntrNoMem]>; + def int_x86_sse2_cvtsi2sd : GCCBuiltin<"__builtin_ia32_cvtsi2sd">, + Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty, + llvm_int_ty], [IntrNoMem]>; + def int_x86_sse2_cvtsd2ss : GCCBuiltin<"__builtin_ia32_cvtsd2ss">, + Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, + llvm_v2f64_ty], [IntrNoMem]>; + def int_x86_sse2_cvtss2sd : GCCBuiltin<"__builtin_ia32_cvtss2sd">, + Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty, + llvm_v4f32_ty], [IntrNoMem]>; } // SIMD load ops From evan.cheng at apple.com Wed Apr 12 19:00:35 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 12 Apr 2006 19:00:35 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/IntrinsicsX86.td Message-ID: <200604130000.TAA06702@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm: IntrinsicsX86.td updated: 1.21 -> 1.22 --- Log message: Naming inconsistency. --- Diffs of the changes: (+1 -1) IntrinsicsX86.td | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/include/llvm/IntrinsicsX86.td diff -u llvm/include/llvm/IntrinsicsX86.td:1.21 llvm/include/llvm/IntrinsicsX86.td:1.22 --- llvm/include/llvm/IntrinsicsX86.td:1.21 Wed Apr 12 18:42:44 2006 +++ llvm/include/llvm/IntrinsicsX86.td Wed Apr 12 19:00:23 2006 @@ -341,7 +341,7 @@ // FIXME: Temporary workaround since 2-wide shuffle is broken. def int_x86_sse2_movl_dq : GCCBuiltin<"__builtin_ia32_movqv4si">, Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>; - def int_x86_sse2_movmskpd : GCCBuiltin<"__builtin_ia32_movmskpd">, + def int_x86_sse2_movmsk_pd : GCCBuiltin<"__builtin_ia32_movmskpd">, Intrinsic<[llvm_int_ty, llvm_v2f64_ty], [IntrNoMem]>; def int_x86_sse2_pmovmskb_128 : GCCBuiltin<"__builtin_ia32_pmovmskb128">, Intrinsic<[llvm_int_ty, llvm_v16i8_ty], [IntrNoMem]>; From evan.cheng at apple.com Wed Apr 12 19:00:36 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 12 Apr 2006 19:00:36 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td Message-ID: <200604130000.TAA06707@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrSSE.td updated: 1.81 -> 1.82 --- Log message: Naming inconsistency. --- Diffs of the changes: (+1 -1) X86InstrSSE.td | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.81 llvm/lib/Target/X86/X86InstrSSE.td:1.82 --- llvm/lib/Target/X86/X86InstrSSE.td:1.81 Wed Apr 12 18:42:44 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Wed Apr 12 19:00:23 2006 @@ -1613,7 +1613,7 @@ [(set R32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>; def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (ops R32:$dst, VR128:$src), "movmskpd {$src, $dst|$dst, $src}", - [(set R32:$dst, (int_x86_sse2_movmskpd VR128:$src))]>; + [(set R32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>; def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (ops R32:$dst, VR128:$src), "pmovmskb {$src, $dst|$dst, $src}", From evan.cheng at apple.com Wed Apr 12 19:43:47 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 12 Apr 2006 19:43:47 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td Message-ID: <200604130043.TAA06927@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrSSE.td updated: 1.82 -> 1.83 --- Log message: padds{b|w}, paddus{b|w}, psubs{b|w}, psubus{b|w} intrinsics. --- Diffs of the changes: (+78 -8) X86InstrSSE.td | 86 +++++++++++++++++++++++++++++++++++++++++++++++++++------ 1 files changed, 78 insertions(+), 8 deletions(-) Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.82 llvm/lib/Target/X86/X86InstrSSE.td:1.83 --- llvm/lib/Target/X86/X86InstrSSE.td:1.82 Wed Apr 12 19:00:23 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Wed Apr 12 19:43:35 2006 @@ -1283,23 +1283,59 @@ "paddq {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v2i64 (add VR128:$src1, VR128:$src2)))]>; } -def PADDBrm : PDI<0xFC, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), +def PADDBrm : PDI<0xFC, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), "paddb {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v16i8 (add VR128:$src1, (load addr:$src2))))]>; -def PADDWrm : PDI<0xFD, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), +def PADDWrm : PDI<0xFD, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), "paddw {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v8i16 (add VR128:$src1, (load addr:$src2))))]>; -def PADDDrm : PDI<0xFE, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), +def PADDDrm : PDI<0xFE, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), "paddd {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v4i32 (add VR128:$src1, (load addr:$src2))))]>; -def PADDQrm : PDI<0xD4, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), +def PADDQrm : PDI<0xD4, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), "paddd {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v2i64 (add VR128:$src1, (load addr:$src2))))]>; +let isCommutable = 1 in { +def PADDSBrr : PDI<0xEC, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), + "paddsb {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_padds_b VR128:$src1, + VR128:$src2))]>; +def PADDSWrr : PDI<0xED, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), + "paddsw {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_padds_w VR128:$src1, + VR128:$src2))]>; +def PADDUSBrr : PDI<0xDC, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), + "paddusb {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_paddus_b VR128:$src1, + VR128:$src2))]>; +def PADDUSWrr : PDI<0xDD, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), + "paddusw {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_paddus_w VR128:$src1, + VR128:$src2))]>; +} +def PADDSBrm : PDI<0xEC, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), + "paddsb {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_padds_b VR128:$src1, + (bc_v16i8 (loadv2i64 addr:$src2))))]>; +def PADDSWrm : PDI<0xED, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), + "paddsw {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_padds_w VR128:$src1, + (bc_v8i16 (loadv2i64 addr:$src2))))]>; +def PADDUSBrm : PDI<0xDC, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), + "paddusb {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_paddus_b VR128:$src1, + (bc_v16i8 (loadv2i64 addr:$src2))))]>; +def PADDUSWrm : PDI<0xDD, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), + "paddusw {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_paddus_w VR128:$src1, + (bc_v8i16 (loadv2i64 addr:$src2))))]>; + + def PSUBBrr : PDI<0xF8, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), "psubb {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v16i8 (sub VR128:$src1, VR128:$src2)))]>; @@ -1313,22 +1349,56 @@ "psubq {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v2i64 (sub VR128:$src1, VR128:$src2)))]>; -def PSUBBrm : PDI<0xF8, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), +def PSUBBrm : PDI<0xF8, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), "psubb {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v16i8 (sub VR128:$src1, (load addr:$src2))))]>; -def PSUBWrm : PDI<0xF9, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), +def PSUBWrm : PDI<0xF9, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), "psubw {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v8i16 (sub VR128:$src1, (load addr:$src2))))]>; -def PSUBDrm : PDI<0xFA, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), +def PSUBDrm : PDI<0xFA, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), "psubd {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v4i32 (sub VR128:$src1, (load addr:$src2))))]>; -def PSUBQrm : PDI<0xFB, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), +def PSUBQrm : PDI<0xFB, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), "psubd {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v2i64 (sub VR128:$src1, (load addr:$src2))))]>; + +def PSUBSBrr : PDI<0xE8, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), + "psubsb {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_psubs_b VR128:$src1, + VR128:$src2))]>; +def PSUBSWrr : PDI<0xE9, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), + "psubsw {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_psubs_w VR128:$src1, + VR128:$src2))]>; +def PSUBUSBrr : PDI<0xD8, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), + "psubusb {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_psubus_b VR128:$src1, + VR128:$src2))]>; +def PSUBUSWrr : PDI<0xD9, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), + "psubusw {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_psubus_w VR128:$src1, + VR128:$src2))]>; + +def PSUBSBrm : PDI<0xE8, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), + "psubsb {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_psubs_b VR128:$src1, + (bc_v16i8 (loadv2i64 addr:$src2))))]>; +def PSUBSWrm : PDI<0xE9, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), + "psubsw {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_psubs_w VR128:$src1, + (bc_v8i16 (loadv2i64 addr:$src2))))]>; +def PSUBUSBrm : PDI<0xD8, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), + "psubusb {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_psubus_b VR128:$src1, + (bc_v16i8 (loadv2i64 addr:$src2))))]>; +def PSUBUSWrm : PDI<0xD9, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), + "psubusw {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_psubus_w VR128:$src1, + (bc_v8i16 (loadv2i64 addr:$src2))))]>; } let isTwoAddress = 1 in { From evan.cheng at apple.com Wed Apr 12 19:43:48 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 12 Apr 2006 19:43:48 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/IntrinsicsX86.td Message-ID: <200604130043.TAA06931@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm: IntrinsicsX86.td updated: 1.22 -> 1.23 --- Log message: padds{b|w}, paddus{b|w}, psubs{b|w}, psubus{b|w} intrinsics. --- Diffs of the changes: (+28 -0) IntrinsicsX86.td | 28 ++++++++++++++++++++++++++++ 1 files changed, 28 insertions(+) Index: llvm/include/llvm/IntrinsicsX86.td diff -u llvm/include/llvm/IntrinsicsX86.td:1.22 llvm/include/llvm/IntrinsicsX86.td:1.23 --- llvm/include/llvm/IntrinsicsX86.td:1.22 Wed Apr 12 19:00:23 2006 +++ llvm/include/llvm/IntrinsicsX86.td Wed Apr 12 19:43:35 2006 @@ -250,6 +250,34 @@ llvm_v2f64_ty], [IntrNoMem]>; } +// Integer arithmetic ops. +let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". + def int_x86_sse2_padds_b : GCCBuiltin<"__builtin_ia32_paddsb128">, + Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, + llvm_v16i8_ty], [IntrNoMem]>; + def int_x86_sse2_padds_w : GCCBuiltin<"__builtin_ia32_paddsw128">, + Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, + llvm_v8i16_ty], [IntrNoMem]>; + def int_x86_sse2_paddus_b : GCCBuiltin<"__builtin_ia32_paddusb128">, + Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, + llvm_v16i8_ty], [IntrNoMem]>; + def int_x86_sse2_paddus_w : GCCBuiltin<"__builtin_ia32_paddusw128">, + Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, + llvm_v8i16_ty], [IntrNoMem]>; + def int_x86_sse2_psubs_b : GCCBuiltin<"__builtin_ia32_psubsb128">, + Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, + llvm_v16i8_ty], [IntrNoMem]>; + def int_x86_sse2_psubs_w : GCCBuiltin<"__builtin_ia32_psubsw128">, + Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, + llvm_v8i16_ty], [IntrNoMem]>; + def int_x86_sse2_psubus_b : GCCBuiltin<"__builtin_ia32_psubusb128">, + Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, + llvm_v16i8_ty], [IntrNoMem]>; + def int_x86_sse2_psubus_w : GCCBuiltin<"__builtin_ia32_psubusw128">, + Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, + llvm_v8i16_ty], [IntrNoMem]>; +} + // Integer shift ops. let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse2_psll_dq : GCCBuiltin<"__builtin_ia32_pslldqi128">, From alenhar2 at cs.uiuc.edu Wed Apr 12 21:05:42 2006 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Wed, 12 Apr 2006 21:05:42 -0500 Subject: [llvm-commits] CVS: llvm/CREDITS.TXT Message-ID: <200604130205.VAA07300@zion.cs.uiuc.edu> Changes in directory llvm: CREDITS.TXT updated: 1.50 -> 1.51 --- Log message: quick update --- Diffs of the changes: (+1 -0) CREDITS.TXT | 1 + 1 files changed, 1 insertion(+) Index: llvm/CREDITS.TXT diff -u llvm/CREDITS.TXT:1.50 llvm/CREDITS.TXT:1.51 --- llvm/CREDITS.TXT:1.50 Wed Apr 12 16:28:14 2006 +++ llvm/CREDITS.TXT Wed Apr 12 21:05:30 2006 @@ -109,6 +109,7 @@ E: alenhar2 at cs.uiuc.edu W: http://www.lenharth.org/~andrewl/ D: Alpha backend +D: Sampling based profiling N: Duraid Madina E: duraid at octopus.com.au From lattner at cs.uiuc.edu Wed Apr 12 23:22:04 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 12 Apr 2006 23:22:04 -0500 Subject: [llvm-commits] CVS: llvm/utils/llvm-config/llvm-config.in.in Message-ID: <200604130422.XAA07862@zion.cs.uiuc.edu> Changes in directory llvm/utils/llvm-config: llvm-config.in.in updated: 1.3 -> 1.4 --- Log message: one too many l's --- Diffs of the changes: (+1 -1) llvm-config.in.in | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/utils/llvm-config/llvm-config.in.in diff -u llvm/utils/llvm-config/llvm-config.in.in:1.3 llvm/utils/llvm-config/llvm-config.in.in:1.4 --- llvm/utils/llvm-config/llvm-config.in.in:1.3 Thu Mar 23 19:10:39 2006 +++ llvm/utils/llvm-config/llvm-config.in.in Wed Apr 12 23:21:31 2006 @@ -5,7 +5,7 @@ # Synopsis: Prints out compiler options needed to build against an installed # copy of LLVM. # -# Syntax: lllvm-config OPTIONS... [COMPONENTS...] +# Syntax: llvm-config OPTIONS... [COMPONENTS...] # # This file was written by Eric Kidd, and is placed into the public domain. # From evan.cheng at apple.com Thu Apr 13 00:09:19 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 13 Apr 2006 00:09:19 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/IntrinsicsX86.td Message-ID: <200604130509.AAA08089@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm: IntrinsicsX86.td updated: 1.23 -> 1.24 --- Log message: pmul*, pmadd*, and pavg* intrinsics. --- Diffs of the changes: (+18 -0) IntrinsicsX86.td | 18 ++++++++++++++++++ 1 files changed, 18 insertions(+) Index: llvm/include/llvm/IntrinsicsX86.td diff -u llvm/include/llvm/IntrinsicsX86.td:1.23 llvm/include/llvm/IntrinsicsX86.td:1.24 --- llvm/include/llvm/IntrinsicsX86.td:1.23 Wed Apr 12 19:43:35 2006 +++ llvm/include/llvm/IntrinsicsX86.td Thu Apr 13 00:09:06 2006 @@ -276,6 +276,24 @@ def int_x86_sse2_psubus_w : GCCBuiltin<"__builtin_ia32_psubusw128">, Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; + def int_x86_sse2_pmulhu_w : GCCBuiltin<"__builtin_ia32_pmulhuw128">, + Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, + llvm_v8i16_ty], [IntrNoMem]>; + def int_x86_sse2_pmulh_w : GCCBuiltin<"__builtin_ia32_pmulhw128">, + Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, + llvm_v8i16_ty], [IntrNoMem]>; + def int_x86_sse2_pmulu_dq : GCCBuiltin<"__builtin_ia32_pmuludq128">, + Intrinsic<[llvm_v2i64_ty, llvm_v4i32_ty, + llvm_v4i32_ty], [IntrNoMem]>; + def int_x86_sse2_pmadd_wd : GCCBuiltin<"__builtin_ia32_pmaddwd128">, + Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, + llvm_v8i16_ty], [IntrNoMem]>; + def int_x86_sse2_pavg_b : GCCBuiltin<"__builtin_ia32_pavgb128">, + Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, + llvm_v16i8_ty], [IntrNoMem]>; + def int_x86_sse2_pavg_w : GCCBuiltin<"__builtin_ia32_pavgw128">, + Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, + llvm_v8i16_ty], [IntrNoMem]>; } // Integer shift ops. From evan.cheng at apple.com Thu Apr 13 00:09:57 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 13 Apr 2006 00:09:57 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/README.txt Message-ID: <200604130509.AAA08111@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: README.txt updated: 1.86 -> 1.87 --- Log message: Update --- Diffs of the changes: (+12 -0) README.txt | 12 ++++++++++++ 1 files changed, 12 insertions(+) Index: llvm/lib/Target/X86/README.txt diff -u llvm/lib/Target/X86/README.txt:1.86 llvm/lib/Target/X86/README.txt:1.87 --- llvm/lib/Target/X86/README.txt:1.86 Wed Apr 12 16:21:57 2006 +++ llvm/lib/Target/X86/README.txt Thu Apr 13 00:09:45 2006 @@ -191,6 +191,18 @@ should be made smart enough to cannonicalize the load into the RHS of a compare when it can invert the result of the compare for free. +How about intrinsics? An example is: + *res = _mm_mulhi_epu16(*A, _mm_mul_epu32(*B, *C)); + +compiles to + pmuludq (%eax), %xmm0 + movl 8(%esp), %eax + movdqa (%eax), %xmm1 + pmulhuw %xmm0, %xmm1 + +The transformation probably requires a X86 specific pass or a DAG combiner +target specific hook. + //===---------------------------------------------------------------------===// LSR should be turned on for the X86 backend and tuned to take advantage of its From evan.cheng at apple.com Thu Apr 13 00:10:37 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 13 Apr 2006 00:10:37 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp Message-ID: <200604130510.AAA08130@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.164 -> 1.165 --- Log message: X86 SSE2 supports v8i16 multiplication --- Diffs of the changes: (+1 -0) X86ISelLowering.cpp | 1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.164 llvm/lib/Target/X86/X86ISelLowering.cpp:1.165 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.164 Wed Apr 12 16:21:57 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Thu Apr 13 00:10:25 2006 @@ -303,6 +303,7 @@ setOperationAction(ISD::SUB, MVT::v16i8, Legal); setOperationAction(ISD::SUB, MVT::v8i16, Legal); setOperationAction(ISD::SUB, MVT::v4i32, Legal); + setOperationAction(ISD::MUL, MVT::v8i16, Legal); setOperationAction(ISD::MUL, MVT::v2f64, Legal); setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); From evan.cheng at apple.com Thu Apr 13 00:25:46 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 13 Apr 2006 00:25:46 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td Message-ID: <200604130525.AAA08207@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrSSE.td updated: 1.83 -> 1.84 --- Log message: Various SSE2 packed integer intrinsics: pmulhuw, pavgw, etc. --- Diffs of the changes: (+71 -4) X86InstrSSE.td | 75 +++++++++++++++++++++++++++++++++++++++++++++++++++++---- 1 files changed, 71 insertions(+), 4 deletions(-) Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.83 llvm/lib/Target/X86/X86InstrSSE.td:1.84 --- llvm/lib/Target/X86/X86InstrSSE.td:1.83 Wed Apr 12 19:43:35 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Thu Apr 13 00:24:54 2006 @@ -1383,22 +1383,89 @@ [(set VR128:$dst, (int_x86_sse2_psubus_w VR128:$src1, VR128:$src2))]>; -def PSUBSBrm : PDI<0xE8, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), +def PSUBSBrm : PDI<0xE8, MRMSrcMem, + (ops VR128:$dst, VR128:$src1, i128mem:$src2), "psubsb {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse2_psubs_b VR128:$src1, (bc_v16i8 (loadv2i64 addr:$src2))))]>; -def PSUBSWrm : PDI<0xE9, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), +def PSUBSWrm : PDI<0xE9, MRMSrcMem, + (ops VR128:$dst, VR128:$src1, i128mem:$src2), "psubsw {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse2_psubs_w VR128:$src1, (bc_v8i16 (loadv2i64 addr:$src2))))]>; -def PSUBUSBrm : PDI<0xD8, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), +def PSUBUSBrm : PDI<0xD8, MRMSrcMem, + (ops VR128:$dst, VR128:$src1, i128mem:$src2), "psubusb {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse2_psubus_b VR128:$src1, (bc_v16i8 (loadv2i64 addr:$src2))))]>; -def PSUBUSWrm : PDI<0xD9, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), +def PSUBUSWrm : PDI<0xD9, MRMSrcMem, + (ops VR128:$dst, VR128:$src1, i128mem:$src2), "psubusw {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse2_psubus_w VR128:$src1, (bc_v8i16 (loadv2i64 addr:$src2))))]>; + +let isCommutable = 1 in { +def PMULHUWrr : PDI<0xE4, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), + "pmulhuw {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_pmulhu_w VR128:$src1, + VR128:$src2))]>; +def PMULHWrr : PDI<0xE5, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), + "pmulhw {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_pmulh_w VR128:$src1, + VR128:$src2))]>; +def PMULLWrr : PDI<0xD5, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), + "pmullw {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (v8i16 (mul VR128:$src1, VR128:$src2)))]>; +def PMULUDQrr : PDI<0xF4, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), + "pmuludq {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_pmulu_dq VR128:$src1, + VR128:$src2))]>; +} + +def PMULHUWrm : PDI<0xE4, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), + "pmulhuw {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_pmulhu_w VR128:$src1, + (bc_v8i16 (loadv2i64 addr:$src2))))]>; +def PMULHWrm : PDI<0xE5, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), + "pmulhw {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_pmulh_w VR128:$src1, + (bc_v8i16 (loadv2i64 addr:$src2))))]>; +def PMULLWrm : PDI<0xD5, MRMSrcMem, + (ops VR128:$dst, VR128:$src1, i128mem:$src2), + "pmullw {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (v8i16 (mul VR128:$src1, + (bc_v8i16 (loadv2i64 addr:$src2)))))]>; +def PMULUDQrm : PDI<0xF4, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), + "pmuludq {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_pmulu_dq VR128:$src1, + (bc_v4i32 (loadv2i64 addr:$src2))))]>; + +def PMADDWDrr : PDI<0xF5, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), + "pmaddwd {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_pmadd_wd VR128:$src1, + VR128:$src2))]>; +def PMADDWDrm : PDI<0xF5, MRMSrcMem, + (ops VR128:$dst, VR128:$src1, i128mem:$src2), + "pmaddwd {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_pmadd_wd VR128:$src1, + (bc_v8i16 (loadv2i64 addr:$src2))))]>; + +def PAVGBrr : PDI<0xE0, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), + "pavgb {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_pavg_b VR128:$src1, + VR128:$src2))]>; +def PAVGWrr : PDI<0xE3, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), + "pavgw {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_pavg_w VR128:$src1, + VR128:$src2))]>; +def PAVGBrm : PDI<0xE0, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), + "pavgb {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_pavg_b VR128:$src1, + (bc_v16i8 (loadv2i64 addr:$src2))))]>; +def PAVGWrm : PDI<0xE3, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), + "pavgw {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_pavg_w VR128:$src1, + (bc_v8i16 (loadv2i64 addr:$src2))))]>; } let isTwoAddress = 1 in { From evan.cheng at apple.com Thu Apr 13 01:10:28 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 13 Apr 2006 01:10:28 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/IntrinsicsX86.td Message-ID: <200604130610.BAA08338@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm: IntrinsicsX86.td updated: 1.24 -> 1.25 --- Log message: pmin, pmax, and psad intrinsics. --- Diffs of the changes: (+15 -0) IntrinsicsX86.td | 15 +++++++++++++++ 1 files changed, 15 insertions(+) Index: llvm/include/llvm/IntrinsicsX86.td diff -u llvm/include/llvm/IntrinsicsX86.td:1.24 llvm/include/llvm/IntrinsicsX86.td:1.25 --- llvm/include/llvm/IntrinsicsX86.td:1.24 Thu Apr 13 00:09:06 2006 +++ llvm/include/llvm/IntrinsicsX86.td Thu Apr 13 01:09:41 2006 @@ -294,6 +294,21 @@ def int_x86_sse2_pavg_w : GCCBuiltin<"__builtin_ia32_pavgw128">, Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; + def int_x86_sse2_pmaxu_b : GCCBuiltin<"__builtin_ia32_pmaxub128">, + Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, + llvm_v16i8_ty], [IntrNoMem]>; + def int_x86_sse2_pmaxs_w : GCCBuiltin<"__builtin_ia32_pmaxsw128">, + Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, + llvm_v8i16_ty], [IntrNoMem]>; + def int_x86_sse2_pminu_b : GCCBuiltin<"__builtin_ia32_pminub128">, + Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, + llvm_v16i8_ty], [IntrNoMem]>; + def int_x86_sse2_pmins_w : GCCBuiltin<"__builtin_ia32_pminsw128">, + Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, + llvm_v8i16_ty], [IntrNoMem]>; + def int_x86_sse2_psad_bw : GCCBuiltin<"__builtin_ia32_psadbw128">, + Intrinsic<[llvm_v2i64_ty, llvm_v16i8_ty, + llvm_v16i8_ty], [IntrNoMem]>; } // Integer shift ops. From evan.cheng at apple.com Thu Apr 13 01:12:37 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 13 Apr 2006 01:12:37 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td Message-ID: <200604130612.BAA08358@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrSSE.td updated: 1.84 -> 1.85 --- Log message: psad, pmax, pmin intrinsics. --- Diffs of the changes: (+54 -1) X86InstrSSE.td | 55 ++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 files changed, 54 insertions(+), 1 deletion(-) Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.84 llvm/lib/Target/X86/X86InstrSSE.td:1.85 --- llvm/lib/Target/X86/X86InstrSSE.td:1.84 Thu Apr 13 00:24:54 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Thu Apr 13 01:11:45 2006 @@ -1421,7 +1421,6 @@ [(set VR128:$dst, (int_x86_sse2_pmulu_dq VR128:$src1, VR128:$src2))]>; } - def PMULHUWrm : PDI<0xE4, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), "pmulhuw {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse2_pmulhu_w VR128:$src1, @@ -1440,16 +1439,19 @@ [(set VR128:$dst, (int_x86_sse2_pmulu_dq VR128:$src1, (bc_v4i32 (loadv2i64 addr:$src2))))]>; +let isCommutable = 1 in { def PMADDWDrr : PDI<0xF5, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), "pmaddwd {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse2_pmadd_wd VR128:$src1, VR128:$src2))]>; +} def PMADDWDrm : PDI<0xF5, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), "pmaddwd {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse2_pmadd_wd VR128:$src1, (bc_v8i16 (loadv2i64 addr:$src2))))]>; +let isCommutable = 1 in { def PAVGBrr : PDI<0xE0, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), "pavgb {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse2_pavg_b VR128:$src1, @@ -1458,6 +1460,7 @@ "pavgw {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse2_pavg_w VR128:$src1, VR128:$src2))]>; +} def PAVGBrm : PDI<0xE0, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), "pavgb {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse2_pavg_b VR128:$src1, @@ -1466,6 +1469,56 @@ "pavgw {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse2_pavg_w VR128:$src1, (bc_v8i16 (loadv2i64 addr:$src2))))]>; + +let isCommutable = 1 in { +def PMAXUBrr : PDI<0xDE, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), + "pmaxub {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_pmaxu_b VR128:$src1, + VR128:$src2))]>; +def PMAXSWrr : PDI<0xEE, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), + "pmaxsw {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_pmaxs_w VR128:$src1, + VR128:$src2))]>; +} +def PMAXUBrm : PDI<0xDE, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), + "pmaxub {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_pmaxu_b VR128:$src1, + (bc_v16i8 (loadv2i64 addr:$src2))))]>; +def PMAXSWrm : PDI<0xEE, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), + "pmaxsw {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_pmaxs_w VR128:$src1, + (bc_v8i16 (loadv2i64 addr:$src2))))]>; + +let isCommutable = 1 in { +def PMINUBrr : PDI<0xDA, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), + "pminub {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_pminu_b VR128:$src1, + VR128:$src2))]>; +def PMINSWrr : PDI<0xEA, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), + "pminsw {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_pmins_w VR128:$src1, + VR128:$src2))]>; +} +def PMINUBrm : PDI<0xDA, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), + "pminub {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_pminu_b VR128:$src1, + (bc_v16i8 (loadv2i64 addr:$src2))))]>; +def PMINSWrm : PDI<0xEA, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), + "pminsw {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_pmins_w VR128:$src1, + (bc_v8i16 (loadv2i64 addr:$src2))))]>; + + +let isCommutable = 1 in { +def PSADBWrr : PDI<0xE0, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), + "psadbw {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_psad_bw VR128:$src1, + VR128:$src2))]>; +} +def PSADBWrm : PDI<0xE0, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), + "psadbw {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_psad_bw VR128:$src1, + (bc_v16i8 (loadv2i64 addr:$src2))))]>; } let isTwoAddress = 1 in { From reid at x10sys.com Thu Apr 13 01:17:30 2006 From: reid at x10sys.com (Reid Spencer) Date: Thu, 13 Apr 2006 01:17:30 -0500 Subject: [llvm-commits] CVS: llvm/projects/Stacker/Makefile Message-ID: <200604130617.BAA08396@zion.cs.uiuc.edu> Changes in directory llvm/projects/Stacker: Makefile updated: 1.9 -> 1.10 --- Log message: Distribute the Stacker samples directory. --- Diffs of the changes: (+1 -1) Makefile | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/projects/Stacker/Makefile diff -u llvm/projects/Stacker/Makefile:1.9 llvm/projects/Stacker/Makefile:1.10 --- llvm/projects/Stacker/Makefile:1.9 Fri Oct 29 13:43:49 2004 +++ llvm/projects/Stacker/Makefile Thu Apr 13 01:16:37 2006 @@ -6,6 +6,6 @@ LEVEL = . DIRS = lib tools -EXTRA_DIST = test +EXTRA_DIST = test samples include $(LEVEL)/Makefile.common From reid at x10sys.com Thu Apr 13 01:28:13 2006 From: reid at x10sys.com (Reid Spencer) Date: Thu, 13 Apr 2006 01:28:13 -0500 Subject: [llvm-commits] CVS: llvm/utils/TableGen/Makefile Message-ID: <200604130628.BAA08450@zion.cs.uiuc.edu> Changes in directory llvm/utils/TableGen: Makefile updated: 1.16 -> 1.17 --- Log message: Add missing things to the distribution. --- Diffs of the changes: (+2 -0) Makefile | 2 ++ 1 files changed, 2 insertions(+) Index: llvm/utils/TableGen/Makefile diff -u llvm/utils/TableGen/Makefile:1.16 llvm/utils/TableGen/Makefile:1.17 --- llvm/utils/TableGen/Makefile:1.16 Sat Aug 27 13:50:39 2005 +++ llvm/utils/TableGen/Makefile Thu Apr 13 01:27:20 2006 @@ -9,6 +9,8 @@ LEVEL = ../.. TOOLNAME = tblgen USEDLIBS = LLVMSupport.a LLVMSystem.a +EXTRA_DIST = FileLexer.cpp.cvs FileLexer.l.cvs \ + FileParser.cpp.cvs FileParser.h.cvs FileParser.y.cvs include $(LEVEL)/Makefile.common From reid at x10sys.com Thu Apr 13 01:28:14 2006 From: reid at x10sys.com (Reid Spencer) Date: Thu, 13 Apr 2006 01:28:14 -0500 Subject: [llvm-commits] CVS: llvm/utils/Makefile Message-ID: <200604130628.BAA08454@zion.cs.uiuc.edu> Changes in directory llvm/utils: Makefile updated: 1.11 -> 1.12 --- Log message: Add missing things to the distribution. --- Diffs of the changes: (+3 -3) Makefile | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) Index: llvm/utils/Makefile diff -u llvm/utils/Makefile:1.11 llvm/utils/Makefile:1.12 --- llvm/utils/Makefile:1.11 Wed Apr 12 18:15:10 2006 +++ llvm/utils/Makefile Thu Apr 13 01:27:20 2006 @@ -14,9 +14,9 @@ DSAclean.py DSAextract.py emacs findsym.pl GenLibDeps.pl \ getsrcs.sh importNLT.pl llvmdo llvmgrep llvm-native-gcc \ llvm-native-gxx makellvm NightlyTest.gnuplot NightlyTest.pl \ - NightlyTestTemplate.html NLT.schema parseNLT.pl plotNLT.pl \ - profile.pl RegressionFinder.pl userloc.pl webNLT.pl \ - vim llvm-config + NightlyTestTemplate.html NLT.schema OldenDataRecover.pl \ + parseNLT.pl plotNLT.pl profile.pl RegressionFinder.pl userloc.pl \ + webNLT.pl vim llvm-config include $(LEVEL)/Makefile.common From reid at x10sys.com Thu Apr 13 01:28:14 2006 From: reid at x10sys.com (Reid Spencer) Date: Thu, 13 Apr 2006 01:28:14 -0500 Subject: [llvm-commits] CVS: llvm/utils/Burg/Makefile Message-ID: <200604130628.BAA08452@zion.cs.uiuc.edu> Changes in directory llvm/utils/Burg: Makefile updated: 1.30 -> 1.31 --- Log message: Add missing things to the distribution. --- Diffs of the changes: (+1 -1) Makefile | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/utils/Burg/Makefile diff -u llvm/utils/Burg/Makefile:1.30 llvm/utils/Burg/Makefile:1.31 --- llvm/utils/Burg/Makefile:1.30 Sat Oct 30 04:19:36 2004 +++ llvm/utils/Burg/Makefile Thu Apr 13 01:27:20 2006 @@ -10,7 +10,7 @@ TOOLNAME = burg BUILT_SOURCES = gram.tab.c gram.tab.h -EXTRA_DIST = gram.yc gram.tab.c gram.tab.h sample.gr +EXTRA_DIST = gram.yc gram.tab.c gram.tab.h sample.gr burg.shar.gz COPYRIGHT Doc include $(LEVEL)/Makefile.common From reid at x10sys.com Thu Apr 13 01:40:18 2006 From: reid at x10sys.com (Reid Spencer) Date: Thu, 13 Apr 2006 01:40:18 -0500 Subject: [llvm-commits] CVS: llvm/lib/System/Makefile Message-ID: <200604130640.BAA08538@zion.cs.uiuc.edu> Changes in directory llvm/lib/System: Makefile updated: 1.9 -> 1.10 --- Log message: Add the README files to the distribution. --- Diffs of the changes: (+1 -1) Makefile | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/System/Makefile diff -u llvm/lib/System/Makefile:1.9 llvm/lib/System/Makefile:1.10 --- llvm/lib/System/Makefile:1.9 Sun Oct 23 21:25:48 2005 +++ llvm/lib/System/Makefile Thu Apr 13 01:39:24 2006 @@ -11,6 +11,6 @@ LIBRARYNAME = LLVMSystem BUILD_ARCHIVE = 1 -EXTRA_DIST = Unix Win32 +EXTRA_DIST = Unix Win32 README.txt include $(LEVEL)/Makefile.common From reid at x10sys.com Thu Apr 13 01:40:19 2006 From: reid at x10sys.com (Reid Spencer) Date: Thu, 13 Apr 2006 01:40:19 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/Makefile Message-ID: <200604130640.BAA08542@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: Makefile updated: 1.25 -> 1.26 --- Log message: Add the README files to the distribution. --- Diffs of the changes: (+1 -0) Makefile | 1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Target/X86/Makefile diff -u llvm/lib/Target/X86/Makefile:1.25 llvm/lib/Target/X86/Makefile:1.26 --- llvm/lib/Target/X86/Makefile:1.25 Thu Jan 26 03:53:06 2006 +++ llvm/lib/Target/X86/Makefile Thu Apr 13 01:39:24 2006 @@ -9,6 +9,7 @@ LEVEL = ../../.. LIBRARYNAME = LLVMX86 TARGET = X86 +EXTRA_DIST = README.txt # Make sure that tblgen is run, first thing. BUILT_SOURCES = X86GenRegisterInfo.h.inc X86GenRegisterNames.inc \ X86GenRegisterInfo.inc X86GenInstrNames.inc \ From reid at x10sys.com Thu Apr 13 01:40:19 2006 From: reid at x10sys.com (Reid Spencer) Date: Thu, 13 Apr 2006 01:40:19 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Makefile Message-ID: <200604130640.BAA08541@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target: Makefile updated: 1.26 -> 1.27 --- Log message: Add the README files to the distribution. --- Diffs of the changes: (+1 -0) Makefile | 1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Target/Makefile diff -u llvm/lib/Target/Makefile:1.26 llvm/lib/Target/Makefile:1.27 --- llvm/lib/Target/Makefile:1.26 Sun Oct 23 21:25:48 2005 +++ llvm/lib/Target/Makefile Thu Apr 13 01:39:24 2006 @@ -10,6 +10,7 @@ LEVEL = ../.. LIBRARYNAME = LLVMTarget BUILD_ARCHIVE = 1 +EXTRA_DIST = README.txt # We include this early so we can access the value of TARGETS_TO_BUILD as the # value for PARALLEL_DIRS which must be set before Makefile.rules is included From reid at x10sys.com Thu Apr 13 01:40:20 2006 From: reid at x10sys.com (Reid Spencer) Date: Thu, 13 Apr 2006 01:40:20 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/Makefile Message-ID: <200604130640.BAA08548@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: Makefile updated: 1.21 -> 1.22 --- Log message: Add the README files to the distribution. --- Diffs of the changes: (+1 -0) Makefile | 1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Target/PowerPC/Makefile diff -u llvm/lib/Target/PowerPC/Makefile:1.21 llvm/lib/Target/PowerPC/Makefile:1.22 --- llvm/lib/Target/PowerPC/Makefile:1.21 Fri Oct 21 14:02:44 2005 +++ llvm/lib/Target/PowerPC/Makefile Thu Apr 13 01:39:24 2006 @@ -9,6 +9,7 @@ LEVEL = ../../.. LIBRARYNAME = LLVMPowerPC TARGET = PPC +EXTRA_DIST = README.txt README_ALTIVEC.txt # Make sure that tblgen is run, first thing. BUILT_SOURCES = PPCGenInstrNames.inc PPCGenRegisterNames.inc \ From reid at x10sys.com Thu Apr 13 01:40:20 2006 From: reid at x10sys.com (Reid Spencer) Date: Thu, 13 Apr 2006 01:40:20 -0500 Subject: [llvm-commits] CVS: llvm/lib/Debugger/Makefile Message-ID: <200604130640.BAA08544@zion.cs.uiuc.edu> Changes in directory llvm/lib/Debugger: Makefile updated: 1.2 -> 1.3 --- Log message: Add the README files to the distribution. --- Diffs of the changes: (+1 -0) Makefile | 1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Debugger/Makefile diff -u llvm/lib/Debugger/Makefile:1.2 llvm/lib/Debugger/Makefile:1.3 --- llvm/lib/Debugger/Makefile:1.2 Wed Oct 27 18:18:44 2004 +++ llvm/lib/Debugger/Makefile Thu Apr 13 01:39:24 2006 @@ -9,5 +9,6 @@ LEVEL = ../.. LIBRARYNAME = LLVMDebugger +EXTRA_DIST = README.txt include $(LEVEL)/Makefile.common From reid at x10sys.com Thu Apr 13 01:40:20 2006 From: reid at x10sys.com (Reid Spencer) Date: Thu, 13 Apr 2006 01:40:20 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/Makefile Message-ID: <200604130640.BAA08546@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Sparc: Makefile updated: 1.14 -> 1.15 --- Log message: Add the README files to the distribution. --- Diffs of the changes: (+1 -0) Makefile | 1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Target/Sparc/Makefile diff -u llvm/lib/Target/Sparc/Makefile:1.14 llvm/lib/Target/Sparc/Makefile:1.15 --- llvm/lib/Target/Sparc/Makefile:1.14 Sat Feb 4 23:50:24 2006 +++ llvm/lib/Target/Sparc/Makefile Thu Apr 13 01:39:24 2006 @@ -9,6 +9,7 @@ LEVEL = ../../.. LIBRARYNAME = LLVMSparc TARGET = Sparc +EXTRA_DIST = README.txt # Make sure that tblgen is run, first thing. BUILT_SOURCES = SparcGenRegisterInfo.h.inc SparcGenRegisterNames.inc \ From alenhar2 at cs.uiuc.edu Thu Apr 13 08:43:55 2006 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Thu, 13 Apr 2006 08:43:55 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/IPO/IndMemRemoval.cpp Message-ID: <200604131343.IAA22445@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/IPO: IndMemRemoval.cpp updated: 1.1 -> 1.2 --- Log message: linear -> constant time --- Diffs of the changes: (+3 -3) IndMemRemoval.cpp | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) Index: llvm/lib/Transforms/IPO/IndMemRemoval.cpp diff -u llvm/lib/Transforms/IPO/IndMemRemoval.cpp:1.1 llvm/lib/Transforms/IPO/IndMemRemoval.cpp:1.2 --- llvm/lib/Transforms/IPO/IndMemRemoval.cpp:1.1 Mon Apr 10 14:25:59 2006 +++ llvm/lib/Transforms/IPO/IndMemRemoval.cpp Thu Apr 13 08:43:31 2006 @@ -51,11 +51,11 @@ //to intrinsics. Therefor, this goes through and finds where the //address of free or malloc are taken and replaces those with bounce //functions, ensuring that all malloc and free that might happen - //happens through intrinsics. + //happen through intrinsics. bool changed = false; if (Function* F = M.getNamedFunction("free")) { assert(F->isExternal() && "free not external?"); - if (F->getNumUses()) { + if (!F->use_empty()) { Function* FN = new Function(F->getFunctionType(), GlobalValue::LinkOnceLinkage, "free_llvm_bounce", &M); @@ -70,7 +70,7 @@ } if (Function* F = M.getNamedFunction("malloc")) { assert(F->isExternal() && "malloc not external?"); - if (F->getNumUses()) { + if (!F->use_empty()) { Function* FN = new Function(F->getFunctionType(), GlobalValue::LinkOnceLinkage, "malloc_llvm_bounce", &M); From alenhar2 at cs.uiuc.edu Thu Apr 13 09:07:48 2006 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Thu, 13 Apr 2006 09:07:48 -0500 Subject: [llvm-commits] CVS: llvm-poolalloc/lib/PoolAllocate/TransformFunctionBody.cpp Message-ID: <200604131407.JAA22705@zion.cs.uiuc.edu> Changes in directory llvm-poolalloc/lib/PoolAllocate: TransformFunctionBody.cpp updated: 1.51 -> 1.52 --- Log message: Use the nifty new memset intrinsics --- Diffs of the changes: (+20 -17) TransformFunctionBody.cpp | 37 ++++++++++++++++++++----------------- 1 files changed, 20 insertions(+), 17 deletions(-) Index: llvm-poolalloc/lib/PoolAllocate/TransformFunctionBody.cpp diff -u llvm-poolalloc/lib/PoolAllocate/TransformFunctionBody.cpp:1.51 llvm-poolalloc/lib/PoolAllocate/TransformFunctionBody.cpp:1.52 --- llvm-poolalloc/lib/PoolAllocate/TransformFunctionBody.cpp:1.51 Fri Mar 31 16:27:40 2006 +++ llvm-poolalloc/lib/PoolAllocate/TransformFunctionBody.cpp Thu Apr 13 09:07:35 2006 @@ -291,19 +291,22 @@ void FuncTransform::visitCallocCall(CallSite CS) { + TargetData& TD = PAInfo.getAnalysis(); + bool useLong = TD.getTypeSize(PointerType::get(Type::SByteTy)) != 4; + Module *M = CS.getInstruction()->getParent()->getParent()->getParent(); assert(CS.arg_end()-CS.arg_begin() == 2 && "calloc takes two arguments!"); Value *V1 = CS.getArgument(0); Value *V2 = CS.getArgument(1); if (V1->getType() != V2->getType()) { - V1 = new CastInst(V1, Type::UIntTy, V1->getName(), CS.getInstruction()); - V2 = new CastInst(V2, Type::UIntTy, V2->getName(), CS.getInstruction()); + V1 = new CastInst(V1, useLong ? Type::ULongTy : Type::UIntTy, V1->getName(), CS.getInstruction()); + V2 = new CastInst(V2, useLong ? Type::ULongTy : Type::UIntTy, V2->getName(), CS.getInstruction()); } V2 = BinaryOperator::create(Instruction::Mul, V1, V2, "size", CS.getInstruction()); - if (V2->getType() != Type::UByteTy) - V2 = new CastInst(V2, Type::UIntTy, V2->getName(), CS.getInstruction()); + if (V2->getType() != (useLong ? Type::ULongTy : Type::UIntTy)) + V2 = new CastInst(V2, useLong ? Type::ULongTy : Type::UIntTy, V2->getName(), CS.getInstruction()); BasicBlock::iterator BBI = TransformAllocationInstr(CS.getInstruction(), V2); @@ -311,11 +314,11 @@ // We just turned the call of 'calloc' into the equivalent of malloc. To // finish calloc, we need to zero out the memory. - Function *MemSet = M->getOrInsertFunction("llvm.memset", - Type::VoidTy, - PointerType::get(Type::SByteTy), - Type::UByteTy, Type::UIntTy, - Type::UIntTy, NULL); + Function *MemSet = M->getOrInsertFunction((useLong ? "llvm.memset.i64" : "llvm.memset.i32"), + Type::VoidTy, + PointerType::get(Type::SByteTy), + Type::UByteTy, (useLong ? Type::ULongTy : Type::UIntTy), + Type::UIntTy, NULL); if (Ptr->getType() != PointerType::get(Type::SByteTy)) Ptr = new CastInst(Ptr, PointerType::get(Type::SByteTy), Ptr->getName(), @@ -579,14 +582,14 @@ // There is no reason to map globals here, since they are not passed as // arguments - // Map the nodes that are pointed to by globals. - // DSScalarMap &CalleeSM = CalleeGraph->getScalarMap(); - // for (DSScalarMap::global_iterator GI = G.getScalarMap().global_begin(), - // E = G.getScalarMap().global_end(); GI != E; ++GI) - // if (CalleeSM.count(*GI)) - // DSGraph::computeNodeMapping(CalleeGraph->getNodeForValue(*GI), - // getDSNodeHFor(*GI), - // NodeMapping, false); +// // Map the nodes that are pointed to by globals. +// DSScalarMap &CalleeSM = CalleeGraph->getScalarMap(); +// for (DSScalarMap::global_iterator GI = G.getScalarMap().global_begin(), +// E = G.getScalarMap().global_end(); GI != E; ++GI) +// if (CalleeSM.count(*GI)) +// DSGraph::computeNodeMapping(CalleeGraph->getNodeForValue(*GI), +// getDSNodeHFor(*GI), +// NodeMapping, false); // Okay, now that we have established our mapping, we can figure out which // pool descriptors to pass in... From lattner at cs.uiuc.edu Thu Apr 13 11:48:11 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 13 Apr 2006 11:48:11 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/README.txt README_ALTIVEC.txt Message-ID: <200604131648.LAA24360@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: README.txt updated: 1.84 -> 1.85 README_ALTIVEC.txt updated: 1.21 -> 1.22 --- Log message: add a note, move an altivec todo to the altivec list. --- Diffs of the changes: (+16 -7) README.txt | 13 ++++++------- README_ALTIVEC.txt | 10 ++++++++++ 2 files changed, 16 insertions(+), 7 deletions(-) Index: llvm/lib/Target/PowerPC/README.txt diff -u llvm/lib/Target/PowerPC/README.txt:1.84 llvm/lib/Target/PowerPC/README.txt:1.85 --- llvm/lib/Target/PowerPC/README.txt:1.84 Sun Apr 2 01:20:00 2006 +++ llvm/lib/Target/PowerPC/README.txt Thu Apr 13 11:48:00 2006 @@ -551,12 +551,11 @@ ===-------------------------------------------------------------------------=== -extract_vector_elt of an arbitrary constant vector can be done with the -following instructions: +Complete the signed i32 to FP conversion code using 64-bit registers +transformation, good for PI. See PPCISelLowering.cpp, this comment: -vTemp = vec_splat(v0,2); // 2 is the element the src is in. -vec_ste(&destloc,0,vTemp); + // FIXME: disable this lowered code. This generates 64-bit register values, + // and we don't model the fact that the top part is clobbered by calls. We + // need to flag these together so that the value isn't live across a call. + //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); -We can do an arbitrary non-constant value by using lvsr/perm/ste. - -===-------------------------------------------------------------------------=== Index: llvm/lib/Target/PowerPC/README_ALTIVEC.txt diff -u llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.21 llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.22 --- llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.21 Wed Apr 12 14:07:14 2006 +++ llvm/lib/Target/PowerPC/README_ALTIVEC.txt Thu Apr 13 11:48:00 2006 @@ -138,3 +138,13 @@ -> C = vsldoi A, B, 4 //===----------------------------------------------------------------------===// + +extract_vector_elt of an arbitrary constant vector can be done with the +following instructions: + +vTemp = vec_splat(v0,2); // 2 is the element the src is in. +vec_ste(&destloc,0,vTemp); + +We can do an arbitrary non-constant value by using lvsr/perm/ste. + +//===----------------------------------------------------------------------===// From lattner at cs.uiuc.edu Thu Apr 13 11:52:25 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 13 Apr 2006 11:52:25 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/vec_shuffle.ll Message-ID: <200604131652.LAA24439@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/PowerPC: vec_shuffle.ll updated: 1.6 -> 1.7 --- Log message: Update a count, this test now passes. --- Diffs of the changes: (+1 -1) vec_shuffle.ll | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/CodeGen/PowerPC/vec_shuffle.ll diff -u llvm/test/Regression/CodeGen/PowerPC/vec_shuffle.ll:1.6 llvm/test/Regression/CodeGen/PowerPC/vec_shuffle.ll:1.7 --- llvm/test/Regression/CodeGen/PowerPC/vec_shuffle.ll:1.6 Sat Apr 8 02:13:46 2006 +++ llvm/test/Regression/CodeGen/PowerPC/vec_shuffle.ll Thu Apr 13 11:52:13 2006 @@ -1,6 +1,6 @@ ; RUN: llvm-as < %s | opt -instcombine | llc -march=ppc32 -mcpu=g5 | not grep vperm && ; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vsldoi | wc -l | grep 2 && -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vmrgh | wc -l | grep 6 && +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vmrgh | wc -l | grep 7 && ; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vmrgl | wc -l | grep 6 && ; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vpkuhum | wc -l | grep 1 && ; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vpkuwum | wc -l | grep 1 From lattner at cs.uiuc.edu Thu Apr 13 12:10:15 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 13 Apr 2006 12:10:15 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/Generic/vector.ll Message-ID: <200604131710.MAA24709@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/Generic: vector.ll updated: 1.9 -> 1.10 --- Log message: Add a run with an unusual target triple, revert the patch that sent output to dev null as it broke the test and doesn't add anything. --- Diffs of the changes: (+6 -5) vector.ll | 11 ++++++----- 1 files changed, 6 insertions(+), 5 deletions(-) Index: llvm/test/Regression/CodeGen/Generic/vector.ll diff -u llvm/test/Regression/CodeGen/Generic/vector.ll:1.9 llvm/test/Regression/CodeGen/Generic/vector.ll:1.10 --- llvm/test/Regression/CodeGen/Generic/vector.ll:1.9 Wed Apr 12 16:03:04 2006 +++ llvm/test/Regression/CodeGen/Generic/vector.ll Thu Apr 13 12:10:03 2006 @@ -1,9 +1,10 @@ ; Test that vectors are scalarized/lowered correctly. -; RUN: llvm-as < %s | llc > /dev/null && -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 > /dev/null && -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g3 > /dev/null && -; RUN: llvm-as < %s | llc -march=x86 -mcpu=i386 > /dev/null && -; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah -o /dev/null +; RUN: llvm-as < %s | llc && +; RUN: llvm-as < %s | llc -mtriple a-b-c && +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 && +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g3 && +; RUN: llvm-as < %s | llc -march=x86 -mcpu=i386 && +; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah %f1 = type <1 x float> %f2 = type <2 x float> From lattner at cs.uiuc.edu Thu Apr 13 12:11:00 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 13 Apr 2006 12:11:00 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp Message-ID: <200604131711.MAA24719@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.147 -> 1.148 --- Log message: Force non-darwin targets to use a static relo model. This fixes PR734: http://llvm.cs.uiuc.edu/PR734 , tested by CodeGen/Generic/vector.ll --- Diffs of the changes: (+8 -7) PPCISelLowering.cpp | 15 ++++++++------- 1 files changed, 8 insertions(+), 7 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.147 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.148 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.147 Wed Apr 12 14:07:14 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Thu Apr 13 12:10:48 2006 @@ -805,7 +805,10 @@ SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i32, CP->getAlignment()); SDOperand Zero = DAG.getConstant(0, MVT::i32); - if (getTargetMachine().getRelocationModel() == Reloc::Static) { + // If this is a non-darwin platform, we don't support non-static relo models + // yet. + if (getTargetMachine().getRelocationModel() == Reloc::Static || + !getTargetMachine().getSubtarget().isDarwin()) { // Generate non-pic code that has direct accesses to the constant pool. // The address of the global is just (hi(&g)+lo(&g)). SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero); @@ -813,8 +816,6 @@ return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo); } - // Only lower ConstantPool on Darwin. - if (!getTargetMachine().getSubtarget().isDarwin()) break; SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero); if (getTargetMachine().getRelocationModel() == Reloc::PIC) { // With PIC, the first instruction is actually "GR+hi(&G)". @@ -832,7 +833,10 @@ SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32, GSDN->getOffset()); SDOperand Zero = DAG.getConstant(0, MVT::i32); - if (getTargetMachine().getRelocationModel() == Reloc::Static) { + // If this is a non-darwin platform, we don't support non-static relo models + // yet. + if (getTargetMachine().getRelocationModel() == Reloc::Static || + !getTargetMachine().getSubtarget().isDarwin()) { // Generate non-pic code that has direct accesses to globals. // The address of the global is just (hi(&g)+lo(&g)). SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, GA, Zero); @@ -840,9 +844,6 @@ return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo); } - // Only lower GlobalAddress on Darwin. - if (!getTargetMachine().getSubtarget().isDarwin()) break; - SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, GA, Zero); if (getTargetMachine().getRelocationModel() == Reloc::PIC) { // With PIC, the first instruction is actually "GR+hi(&G)". From lattner at cs.uiuc.edu Thu Apr 13 12:16:33 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 13 Apr 2006 12:16:33 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CFrontend/2003-01-30-UnionInit.c 2003-08-30-AggregateInitializer.c 2004-01-01-UnknownInitSize.c 2005-10-18-VariableSizedElementCrash.c 2006-01-13-StackSave.c 2006-01-23-FileScopeAsm.c 2006-03-16-VectorCtor.c Message-ID: <200604131716.MAA24847@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CFrontend: 2003-01-30-UnionInit.c updated: 1.5 -> 1.6 2003-08-30-AggregateInitializer.c updated: 1.5 -> 1.6 2004-01-01-UnknownInitSize.c updated: 1.5 -> 1.6 2005-10-18-VariableSizedElementCrash.c updated: 1.1 -> 1.2 2006-01-13-StackSave.c updated: 1.1 -> 1.2 2006-01-23-FileScopeAsm.c updated: 1.1 -> 1.2 2006-03-16-VectorCtor.c updated: 1.1 -> 1.2 --- Log message: These are only XFAILs with llvmgcc3, they pass with llvmgcc4 --- Diffs of the changes: (+10 -9) 2003-01-30-UnionInit.c | 3 +-- 2003-08-30-AggregateInitializer.c | 2 +- 2004-01-01-UnknownInitSize.c | 2 +- 2005-10-18-VariableSizedElementCrash.c | 3 ++- 2006-01-13-StackSave.c | 2 +- 2006-01-23-FileScopeAsm.c | 2 +- 2006-03-16-VectorCtor.c | 5 +++-- 7 files changed, 10 insertions(+), 9 deletions(-) Index: llvm/test/Regression/CFrontend/2003-01-30-UnionInit.c diff -u llvm/test/Regression/CFrontend/2003-01-30-UnionInit.c:1.5 llvm/test/Regression/CFrontend/2003-01-30-UnionInit.c:1.6 --- llvm/test/Regression/CFrontend/2003-01-30-UnionInit.c:1.5 Tue Dec 28 21:16:40 2004 +++ llvm/test/Regression/CFrontend/2003-01-30-UnionInit.c Thu Apr 13 12:16:21 2006 @@ -1,6 +1,5 @@ // RUN: %llvmgcc -S %s -o /dev/null - -// XFAIL: * +// XFAIL: llvmgcc3 union foo { struct { char A, B; } X; Index: llvm/test/Regression/CFrontend/2003-08-30-AggregateInitializer.c diff -u llvm/test/Regression/CFrontend/2003-08-30-AggregateInitializer.c:1.5 llvm/test/Regression/CFrontend/2003-08-30-AggregateInitializer.c:1.6 --- llvm/test/Regression/CFrontend/2003-08-30-AggregateInitializer.c:1.5 Tue Dec 28 21:17:30 2004 +++ llvm/test/Regression/CFrontend/2003-08-30-AggregateInitializer.c Thu Apr 13 12:16:21 2006 @@ -1,6 +1,6 @@ // RUN: %llvmgcc -S %s -o /dev/null -// XFAIL: * +// XFAIL: llvmgcc3 struct istruct { unsigned char C; Index: llvm/test/Regression/CFrontend/2004-01-01-UnknownInitSize.c diff -u llvm/test/Regression/CFrontend/2004-01-01-UnknownInitSize.c:1.5 llvm/test/Regression/CFrontend/2004-01-01-UnknownInitSize.c:1.6 --- llvm/test/Regression/CFrontend/2004-01-01-UnknownInitSize.c:1.5 Wed Dec 8 10:31:06 2004 +++ llvm/test/Regression/CFrontend/2004-01-01-UnknownInitSize.c Thu Apr 13 12:16:21 2006 @@ -1,9 +1,9 @@ // RUN: %llvmgcc -S %s -o /dev/null +// XFAIL: llvmgcc3 /* * This regression test ensures that the C front end can compile initializers * even when it cannot determine the size (as below). - * XFAIL: * */ struct one { Index: llvm/test/Regression/CFrontend/2005-10-18-VariableSizedElementCrash.c diff -u llvm/test/Regression/CFrontend/2005-10-18-VariableSizedElementCrash.c:1.1 llvm/test/Regression/CFrontend/2005-10-18-VariableSizedElementCrash.c:1.2 --- llvm/test/Regression/CFrontend/2005-10-18-VariableSizedElementCrash.c:1.1 Tue Oct 18 19:52:22 2005 +++ llvm/test/Regression/CFrontend/2005-10-18-VariableSizedElementCrash.c Thu Apr 13 12:16:21 2006 @@ -1,5 +1,6 @@ // RUN: %llvmgcc %s -S -o - -// XFAIL: * +// XFAIL: llvmgcc3 + int sub1(int i, char *pi) { typedef int foo[i]; struct bar {foo f1; int f2:3; int f3:4} *p = (struct bar *) pi; Index: llvm/test/Regression/CFrontend/2006-01-13-StackSave.c diff -u llvm/test/Regression/CFrontend/2006-01-13-StackSave.c:1.1 llvm/test/Regression/CFrontend/2006-01-13-StackSave.c:1.2 --- llvm/test/Regression/CFrontend/2006-01-13-StackSave.c:1.1 Fri Jan 13 16:05:36 2006 +++ llvm/test/Regression/CFrontend/2006-01-13-StackSave.c Thu Apr 13 12:16:21 2006 @@ -1,5 +1,5 @@ // RUN: %llvmgcc %s -S -o - | gccas | llvm-dis | grep llvm.stacksave -// XFAIL: * +// XFAIL: llvmgcc3 // PR691 Index: llvm/test/Regression/CFrontend/2006-01-23-FileScopeAsm.c diff -u llvm/test/Regression/CFrontend/2006-01-23-FileScopeAsm.c:1.1 llvm/test/Regression/CFrontend/2006-01-23-FileScopeAsm.c:1.2 --- llvm/test/Regression/CFrontend/2006-01-23-FileScopeAsm.c:1.1 Mon Jan 23 23:01:39 2006 +++ llvm/test/Regression/CFrontend/2006-01-23-FileScopeAsm.c Thu Apr 13 12:16:21 2006 @@ -1,5 +1,5 @@ // RUN: %llvmgcc %s -S -o - | gccas | llvm-dis | grep foo[12345] | wc -l | grep 5 -// XFAIL: * +// XFAIL: llvmgcc3 __asm__ ("foo1"); __asm__ ("foo2"); Index: llvm/test/Regression/CFrontend/2006-03-16-VectorCtor.c diff -u llvm/test/Regression/CFrontend/2006-03-16-VectorCtor.c:1.1 llvm/test/Regression/CFrontend/2006-03-16-VectorCtor.c:1.2 --- llvm/test/Regression/CFrontend/2006-03-16-VectorCtor.c:1.1 Thu Mar 16 12:47:51 2006 +++ llvm/test/Regression/CFrontend/2006-03-16-VectorCtor.c Thu Apr 13 12:16:21 2006 @@ -1,6 +1,7 @@ -// Passes with the new CFE. +// Test that basic generic vector support works + // RUN: %llvmgcc %s -S -o - -// XFAIL: * +// XFAIL: llvmgcc3 typedef int v4si __attribute__ ((__vector_size__ (16))); void test(v4si *P, v4si *Q, float X) { From lattner at cs.uiuc.edu Thu Apr 13 12:18:54 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 13 Apr 2006 12:18:54 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/stacksave-restore.ll Message-ID: <200604131718.MAA24969@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen: stacksave-restore.ll (r1.1) removed --- Log message: Oops, move misplaced test --- Diffs of the changes: (+0 -0) 0 files changed From lattner at cs.uiuc.edu Thu Apr 13 12:18:54 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 13 Apr 2006 12:18:54 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/Generic/stacksave-restore.ll Message-ID: <200604131718.MAA24973@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/Generic: stacksave-restore.ll added (r1.1) --- Log message: Oops, move misplaced test --- Diffs of the changes: (+12 -0) stacksave-restore.ll | 12 ++++++++++++ 1 files changed, 12 insertions(+) Index: llvm/test/Regression/CodeGen/Generic/stacksave-restore.ll diff -c /dev/null llvm/test/Regression/CodeGen/Generic/stacksave-restore.ll:1.1 *** /dev/null Thu Apr 13 12:18:52 2006 --- llvm/test/Regression/CodeGen/Generic/stacksave-restore.ll Thu Apr 13 12:18:42 2006 *************** *** 0 **** --- 1,12 ---- + ; RUN: llvm-as < %s | llc + + declare sbyte* %llvm.stacksave() + declare void %llvm.stackrestore(sbyte*) + + int *%test(uint %N) { + %tmp = call sbyte* %llvm.stacksave() + %P = alloca int, uint %N + call void %llvm.stackrestore(sbyte* %tmp) + %Q = alloca int, uint %N + ret int* %P + } From lattner at cs.uiuc.edu Thu Apr 13 12:19:46 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 13 Apr 2006 12:19:46 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/Alpha/bsr.ll Message-ID: <200604131719.MAA25010@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/Alpha: bsr.ll updated: 1.1 -> 1.2 --- Log message: This test fails and I don't know why, xfail it until andrew gets a chance to look at it. --- Diffs of the changes: (+1 -3) bsr.ll | 4 +--- 1 files changed, 1 insertion(+), 3 deletions(-) Index: llvm/test/Regression/CodeGen/Alpha/bsr.ll diff -u llvm/test/Regression/CodeGen/Alpha/bsr.ll:1.1 llvm/test/Regression/CodeGen/Alpha/bsr.ll:1.2 --- llvm/test/Regression/CodeGen/Alpha/bsr.ll:1.1 Wed Apr 13 11:16:01 2005 +++ llvm/test/Regression/CodeGen/Alpha/bsr.ll Thu Apr 13 12:19:34 2006 @@ -1,11 +1,9 @@ ; Make sure this testcase codegens the bsr instruction ; RUN: llvm-as < %s | llc -march=alpha | grep 'bsr' - -implementation ; Functions: +; XFAIL: * long %abc(int %x) { -entry: %tmp.2 = add int %x, -1 ; [#uses=1] %tmp.0 = call long %abc( int %tmp.2 ) ; [#uses=1] %tmp.5 = add int %x, -2 ; [#uses=1] From lattner at cs.uiuc.edu Thu Apr 13 12:22:01 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 13 Apr 2006 12:22:01 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Verifier/2004-01-22-FloatNormalization.ll Message-ID: <200604131722.MAA25097@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Verifier: 2004-01-22-FloatNormalization.ll updated: 1.3 -> 1.4 --- Log message: Fix an accidental commit. --- Diffs of the changes: (+1 -1) 2004-01-22-FloatNormalization.ll | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Verifier/2004-01-22-FloatNormalization.ll diff -u llvm/test/Regression/Verifier/2004-01-22-FloatNormalization.ll:1.3 llvm/test/Regression/Verifier/2004-01-22-FloatNormalization.ll:1.4 --- llvm/test/Regression/Verifier/2004-01-22-FloatNormalization.ll:1.3 Wed Apr 12 16:57:40 2006 +++ llvm/test/Regression/Verifier/2004-01-22-FloatNormalization.ll Thu Apr 13 12:21:49 2006 @@ -1,5 +1,5 @@ ; RUN: not llvm-as < %s -o /dev/null -f -; XFAIL: 3.4 +; XFAIL: * ; make sure that invalid 'float' values are caught. From lattner at cs.uiuc.edu Thu Apr 13 12:27:06 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 13 Apr 2006 12:27:06 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/C++Frontend/2003-11-09-ConstructorTypeSafety.cpp.tr 2003-11-18-MemberInitializationCasting.cpp.tr Message-ID: <200604131727.MAA25139@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/C++Frontend: 2003-11-09-ConstructorTypeSafety.cpp.tr updated: 1.1 -> 1.2 2003-11-18-MemberInitializationCasting.cpp.tr updated: 1.1 -> 1.2 --- Log message: Don't get confused by dead casts. --- Diffs of the changes: (+2 -2) 2003-11-09-ConstructorTypeSafety.cpp.tr | 2 +- 2003-11-18-MemberInitializationCasting.cpp.tr | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/test/Regression/C++Frontend/2003-11-09-ConstructorTypeSafety.cpp.tr diff -u llvm/test/Regression/C++Frontend/2003-11-09-ConstructorTypeSafety.cpp.tr:1.1 llvm/test/Regression/C++Frontend/2003-11-09-ConstructorTypeSafety.cpp.tr:1.2 --- llvm/test/Regression/C++Frontend/2003-11-09-ConstructorTypeSafety.cpp.tr:1.1 Sun Nov 9 01:05:02 2003 +++ llvm/test/Regression/C++Frontend/2003-11-09-ConstructorTypeSafety.cpp.tr Thu Apr 13 12:26:54 2006 @@ -1,5 +1,5 @@ // The code generated for this testcase should be completely typesafe! -// RUN: %llvmgcc -xc++ -S -o - %s | not grep ' cast ' +// RUN: %llvmgcc -xc++ -S -o - %s | llvm-as | opt -die | llvm-dis | not grep ' cast ' struct contained { unsigned X; Index: llvm/test/Regression/C++Frontend/2003-11-18-MemberInitializationCasting.cpp.tr diff -u llvm/test/Regression/C++Frontend/2003-11-18-MemberInitializationCasting.cpp.tr:1.1 llvm/test/Regression/C++Frontend/2003-11-18-MemberInitializationCasting.cpp.tr:1.2 --- llvm/test/Regression/C++Frontend/2003-11-18-MemberInitializationCasting.cpp.tr:1.1 Tue Nov 18 15:05:55 2003 +++ llvm/test/Regression/C++Frontend/2003-11-18-MemberInitializationCasting.cpp.tr Thu Apr 13 12:26:54 2006 @@ -1,4 +1,4 @@ -// RUN: %llvmgcc -xc++ -S -o - %s | not grep ' cast ' +// RUN: %llvmgcc -xc++ -S -o - %s | llvm-as | opt -die | llvm-dis | not grep ' cast ' struct A { A() : i(0) {} From lattner at cs.uiuc.edu Thu Apr 13 12:28:40 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 13 Apr 2006 12:28:40 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/C++Frontend/2005-07-21-VirtualBaseAccess.cpp Message-ID: <200604131728.MAA25174@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/C++Frontend: 2005-07-21-VirtualBaseAccess.cpp updated: 1.1 -> 1.2 --- Log message: Another case where a dead cast was causing the test to spuriously fail with the new front-end. --- Diffs of the changes: (+1 -1) 2005-07-21-VirtualBaseAccess.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/C++Frontend/2005-07-21-VirtualBaseAccess.cpp diff -u llvm/test/Regression/C++Frontend/2005-07-21-VirtualBaseAccess.cpp:1.1 llvm/test/Regression/C++Frontend/2005-07-21-VirtualBaseAccess.cpp:1.2 --- llvm/test/Regression/C++Frontend/2005-07-21-VirtualBaseAccess.cpp:1.1 Thu Jul 21 16:55:08 2005 +++ llvm/test/Regression/C++Frontend/2005-07-21-VirtualBaseAccess.cpp Thu Apr 13 12:28:28 2006 @@ -1,4 +1,4 @@ -// RUN: %llvmgxx -xc++ %s -c -o - | llvm-dis | not grep cast +// RUN: %llvmgxx -xc++ %s -c -o - | opt -die | llvm-dis | not grep cast void foo(int*); From lattner at cs.uiuc.edu Thu Apr 13 12:32:15 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 13 Apr 2006 12:32:15 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CFrontend/2004-02-20-StaticRedeclare.c.tr Message-ID: <200604131732.MAA25245@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CFrontend: 2004-02-20-StaticRedeclare.c.tr updated: 1.3 -> 1.4 --- Log message: This file is an invalid C file, test that it is properly rejected --- Diffs of the changes: (+5 -1) 2004-02-20-StaticRedeclare.c.tr | 6 +++++- 1 files changed, 5 insertions(+), 1 deletion(-) Index: llvm/test/Regression/CFrontend/2004-02-20-StaticRedeclare.c.tr diff -u llvm/test/Regression/CFrontend/2004-02-20-StaticRedeclare.c.tr:1.3 llvm/test/Regression/CFrontend/2004-02-20-StaticRedeclare.c.tr:1.4 --- llvm/test/Regression/CFrontend/2004-02-20-StaticRedeclare.c.tr:1.3 Tue Nov 30 10:48:26 2004 +++ llvm/test/Regression/CFrontend/2004-02-20-StaticRedeclare.c.tr Thu Apr 13 12:32:03 2006 @@ -1,4 +1,8 @@ -// RUN: %llvmgcc -xc %s -c -o - | llvm-dis | not grep declare +// RUN: not %llvmgcc -xc %s -S -o - + +// This is a malformed program that is not caught by llvmgcc3. +// XFAIL: llvmgcc3 + int one (int a) { two (a, 5); From lattner at cs.uiuc.edu Thu Apr 13 12:33:05 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 13 Apr 2006 12:33:05 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/BugPoint/dg.exp Message-ID: <200604131733.MAA25307@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/BugPoint: dg.exp updated: 1.3 -> 1.4 --- Log message: Only look at .ll files in this directory --- Diffs of the changes: (+1 -1) dg.exp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/BugPoint/dg.exp diff -u llvm/test/Regression/BugPoint/dg.exp:1.3 llvm/test/Regression/BugPoint/dg.exp:1.4 --- llvm/test/Regression/BugPoint/dg.exp:1.3 Wed Apr 12 16:57:33 2006 +++ llvm/test/Regression/BugPoint/dg.exp Thu Apr 13 12:32:53 2006 @@ -1,3 +1,3 @@ load_lib llvm-dg.exp -llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,llx,c,cpp,tr}]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version +llvm-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.ll]] $objdir $srcdir $subdir $target_triplet $llvmgcc $llvmgxx $prcontext $llvmgcc_version From lattner at cs.uiuc.edu Thu Apr 13 12:35:49 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 13 Apr 2006 12:35:49 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CFrontend/2005-12-04-DeclarationLineNumbers.c 2006-01-13-Includes.c Message-ID: <200604131735.MAA25419@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CFrontend: 2005-12-04-DeclarationLineNumbers.c updated: 1.1 -> 1.2 2006-01-13-Includes.c updated: 1.2 -> 1.3 --- Log message: These tests are now xfailed for llvmgcc4. This is PR735: http://llvm.cs.uiuc.edu/PR735 , unlikely to be resolved before 1.7 :( --- Diffs of the changes: (+4 -0) 2005-12-04-DeclarationLineNumbers.c | 3 +++ 2006-01-13-Includes.c | 1 + 2 files changed, 4 insertions(+) Index: llvm/test/Regression/CFrontend/2005-12-04-DeclarationLineNumbers.c diff -u llvm/test/Regression/CFrontend/2005-12-04-DeclarationLineNumbers.c:1.1 llvm/test/Regression/CFrontend/2005-12-04-DeclarationLineNumbers.c:1.2 --- llvm/test/Regression/CFrontend/2005-12-04-DeclarationLineNumbers.c:1.1 Sun Dec 4 21:22:46 2005 +++ llvm/test/Regression/CFrontend/2005-12-04-DeclarationLineNumbers.c Thu Apr 13 12:35:36 2006 @@ -1,5 +1,8 @@ // RUN: %llvmgcc %s -S -g -o - | grep 'llvm.dbg.stoppoint.*uint 14' // PR664: ensure that line #'s are emitted for declarations + +// XFAIL: llvmgcc4 + short test(short br_data_0, short br_data_1, short br_data_2, Index: llvm/test/Regression/CFrontend/2006-01-13-Includes.c diff -u llvm/test/Regression/CFrontend/2006-01-13-Includes.c:1.2 llvm/test/Regression/CFrontend/2006-01-13-Includes.c:1.3 --- llvm/test/Regression/CFrontend/2006-01-13-Includes.c:1.2 Thu Jan 19 00:49:46 2006 +++ llvm/test/Regression/CFrontend/2006-01-13-Includes.c Thu Apr 13 12:35:36 2006 @@ -1,4 +1,5 @@ // RUN: %llvmgcc %s -g -S -o - | gccas | llvm-dis | grep "test/Regression/CFrontend" +// XFAIL: llvmgcc4 // PR676 #include From alenhar2 at cs.uiuc.edu Thu Apr 13 12:52:44 2006 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Thu, 13 Apr 2006 12:52:44 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/Alpha/bsr.ll Message-ID: <200604131752.MAA25712@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/Alpha: bsr.ll updated: 1.2 -> 1.3 --- Log message: fix this for the more restrictive linkage --- Diffs of the changes: (+2 -2) bsr.ll | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/test/Regression/CodeGen/Alpha/bsr.ll diff -u llvm/test/Regression/CodeGen/Alpha/bsr.ll:1.2 llvm/test/Regression/CodeGen/Alpha/bsr.ll:1.3 --- llvm/test/Regression/CodeGen/Alpha/bsr.ll:1.2 Thu Apr 13 12:19:34 2006 +++ llvm/test/Regression/CodeGen/Alpha/bsr.ll Thu Apr 13 12:52:32 2006 @@ -1,9 +1,9 @@ ; Make sure this testcase codegens the bsr instruction ; RUN: llvm-as < %s | llc -march=alpha | grep 'bsr' -; XFAIL: * +implementation -long %abc(int %x) { +internal long %abc(int %x) { %tmp.2 = add int %x, -1 ; [#uses=1] %tmp.0 = call long %abc( int %tmp.2 ) ; [#uses=1] %tmp.5 = add int %x, -2 ; [#uses=1] From evan.cheng at apple.com Thu Apr 13 13:11:40 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 13 Apr 2006 13:11:40 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td Message-ID: <200604131811.NAA12703@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrSSE.td updated: 1.85 -> 1.86 --- Log message: Doh. PANDrm, etc. are not commutable. --- Diffs of the changes: (+7 -9) X86InstrSSE.td | 16 +++++++--------- 1 files changed, 7 insertions(+), 9 deletions(-) Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.85 llvm/lib/Target/X86/X86InstrSSE.td:1.86 --- llvm/lib/Target/X86/X86InstrSSE.td:1.85 Thu Apr 13 01:11:45 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Thu Apr 13 13:11:28 2006 @@ -1534,28 +1534,26 @@ def PANDrr : PDI<0xDB, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), "pand {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v2i64 (and VR128:$src1, VR128:$src2)))]>; +def PORrr : PDI<0xEB, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), + "por {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (v2i64 (or VR128:$src1, VR128:$src2)))]>; +def PXORrr : PDI<0xEF, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), + "pxor {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (v2i64 (xor VR128:$src1, VR128:$src2)))]>; +} def PANDrm : PDI<0xDB, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), "pand {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v2i64 (and VR128:$src1, (load addr:$src2))))]>; -def PORrr : PDI<0xEB, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), - "por {$src2, $dst|$dst, $src2}", - [(set VR128:$dst, (v2i64 (or VR128:$src1, VR128:$src2)))]>; - def PORrm : PDI<0xEB, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), "por {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v2i64 (or VR128:$src1, (load addr:$src2))))]>; -def PXORrr : PDI<0xEF, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), - "pxor {$src2, $dst|$dst, $src2}", - [(set VR128:$dst, (v2i64 (xor VR128:$src1, VR128:$src2)))]>; - def PXORrm : PDI<0xEF, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), "pxor {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v2i64 (xor VR128:$src1, (load addr:$src2))))]>; -} def PANDNrr : PDI<0xDF, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), "pandn {$src2, $dst|$dst, $src2}", From lattner at cs.uiuc.edu Thu Apr 13 13:15:36 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 13 Apr 2006 13:15:36 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/ExecutionEngine/2005-12-02-TailCallBug.ll Message-ID: <200604131815.NAA13045@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/ExecutionEngine: 2005-12-02-TailCallBug.ll updated: 1.2 -> 1.3 --- Log message: Try xfailing this --- Diffs of the changes: (+3 -1) 2005-12-02-TailCallBug.ll | 4 +++- 1 files changed, 3 insertions(+), 1 deletion(-) Index: llvm/test/Regression/ExecutionEngine/2005-12-02-TailCallBug.ll diff -u llvm/test/Regression/ExecutionEngine/2005-12-02-TailCallBug.ll:1.2 llvm/test/Regression/ExecutionEngine/2005-12-02-TailCallBug.ll:1.3 --- llvm/test/Regression/ExecutionEngine/2005-12-02-TailCallBug.ll:1.2 Sat Dec 3 11:20:57 2005 +++ llvm/test/Regression/ExecutionEngine/2005-12-02-TailCallBug.ll Thu Apr 13 13:15:24 2006 @@ -1,6 +1,8 @@ +; PR672 ; RUN: llvm-as < %s | lli -; PR672 +; This doesn't work on darwin/x86, xfail until PR736 is resolved. +; XFAIL: i686-apple-darwin int %main(){ %f = cast int (int, int*, int)* %check_tail to int* From lattner at cs.uiuc.edu Thu Apr 13 13:18:07 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 13 Apr 2006 13:18:07 -0500 Subject: [llvm-commits] CVS: llvm-gcc/gcc/llvm-expand.c Message-ID: <200604131818.NAA13263@zion.cs.uiuc.edu> Changes in directory llvm-gcc/gcc: llvm-expand.c updated: 1.126 -> 1.127 --- Log message: Use the appropriate type suffix for llvm.memcpy/llvm.memmove, resolving PR733: http://llvm.cs.uiuc.edu/PR733 --- Diffs of the changes: (+12 -5) llvm-expand.c | 17 ++++++++++++----- 1 files changed, 12 insertions(+), 5 deletions(-) Index: llvm-gcc/gcc/llvm-expand.c diff -u llvm-gcc/gcc/llvm-expand.c:1.126 llvm-gcc/gcc/llvm-expand.c:1.127 --- llvm-gcc/gcc/llvm-expand.c:1.126 Tue Jan 17 00:22:23 2006 +++ llvm-gcc/gcc/llvm-expand.c Thu Apr 13 13:17:55 2006 @@ -344,24 +344,31 @@ unsigned Alignment, int isMove) { static llvm_function *llvm_memcpy_fn = 0, *llvm_memmove_fn = 0; static llvm_type *size_tTy = 0; - + + if (size_tTy == 0) + size_tTy = llvm_type_get_from_tree(size_type_node); + llvm_instruction *I; if (!isMove && !llvm_memcpy_fn) { + const char *Name = size_tTy == UIntTy ? + "llvm.memcpy.i32" : "llvm.memcpy.i64"; llvm_type *FnTy = llvm_type_create_function(4, VoidTy); FnTy->Elements[1] = FnTy->Elements[2] = VoidPtrTy; - FnTy->Elements[3] = size_tTy = llvm_type_get_from_tree(size_type_node); + FnTy->Elements[3] = size_tTy; FnTy->Elements[4] = UIntTy; FnTy = llvm_type_get_cannonical_function(FnTy); - llvm_memcpy_fn = CreateIntrinsicFnWithType("llvm.memcpy", FnTy); + llvm_memcpy_fn = CreateIntrinsicFnWithType(Name, FnTy); } if (isMove && !llvm_memmove_fn) { + const char *Name = size_tTy == UIntTy ? + "llvm.memmove.i32" : "llvm.memmove.i64"; llvm_type *FnTy = llvm_type_create_function(4, VoidTy); FnTy->Elements[1] = FnTy->Elements[2] = VoidPtrTy; - FnTy->Elements[3] = size_tTy = llvm_type_get_from_tree(size_type_node); + FnTy->Elements[3] = size_tTy; FnTy->Elements[4] = UIntTy; FnTy = llvm_type_get_cannonical_function(FnTy); - llvm_memmove_fn = CreateIntrinsicFnWithType("llvm.memmove", FnTy); + llvm_memmove_fn = CreateIntrinsicFnWithType(Name, FnTy); } I = llvm_instruction_new(VoidTy, "", O_Call, 5); From lattner at cs.uiuc.edu Thu Apr 13 13:21:25 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 13 Apr 2006 13:21:25 -0500 Subject: [llvm-commits] CVS: llvm-gcc/gcc/llvm-expand.c Message-ID: <200604131821.NAA13560@zion.cs.uiuc.edu> Changes in directory llvm-gcc/gcc: llvm-expand.c updated: 1.127 -> 1.128 --- Log message: Add appropriate type suffix for llvm.memset also, for PR733: http://llvm.cs.uiuc.edu/PR733 --- Diffs of the changes: (+10 -4) llvm-expand.c | 14 ++++++++++---- 1 files changed, 10 insertions(+), 4 deletions(-) Index: llvm-gcc/gcc/llvm-expand.c diff -u llvm-gcc/gcc/llvm-expand.c:1.127 llvm-gcc/gcc/llvm-expand.c:1.128 --- llvm-gcc/gcc/llvm-expand.c:1.127 Thu Apr 13 13:17:55 2006 +++ llvm-gcc/gcc/llvm-expand.c Thu Apr 13 13:21:13 2006 @@ -344,11 +344,11 @@ unsigned Alignment, int isMove) { static llvm_function *llvm_memcpy_fn = 0, *llvm_memmove_fn = 0; static llvm_type *size_tTy = 0; + llvm_instruction *I; if (size_tTy == 0) size_tTy = llvm_type_get_from_tree(size_type_node); - llvm_instruction *I; if (!isMove && !llvm_memcpy_fn) { const char *Name = size_tTy == UIntTy ? "llvm.memcpy.i32" : "llvm.memcpy.i64"; @@ -387,16 +387,22 @@ llvm_value *Size, unsigned Alignment) { static llvm_function *llvm_memset_fn = 0; static llvm_type *size_tTy = 0; - llvm_instruction *I; + + if (size_tTy == 0) + size_tTy = llvm_type_get_from_tree(size_type_node); + if (!llvm_memset_fn) { + const char *Name = size_tTy == UIntTy ? + "llvm.memset.i32" : "llvm.memset.i64"; + llvm_type *FnTy = llvm_type_create_function(4, VoidTy); FnTy->Elements[1] = VoidPtrTy; FnTy->Elements[2] = UByteTy; - FnTy->Elements[3] = size_tTy = llvm_type_get_from_tree(size_type_node); + FnTy->Elements[3] = size_tTy; FnTy->Elements[4] = UIntTy; FnTy = llvm_type_get_cannonical_function(FnTy); - llvm_memset_fn = CreateIntrinsicFnWithType("llvm.memset", FnTy); + llvm_memset_fn = CreateIntrinsicFnWithType(Name, FnTy); } I = llvm_instruction_new(VoidTy, "", O_Call, 5); From lattner at cs.uiuc.edu Thu Apr 13 13:24:00 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 13 Apr 2006 13:24:00 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Intrinsics.td Message-ID: <200604131824.NAA13732@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm: Intrinsics.td updated: 1.33 -> 1.34 --- Log message: Fix an incorrect prototype for this intrinsic, fixing CFrontend/2003-08-18-SigSetJmp.c with llvm-gcc3. This is part of PR733: http://llvm.cs.uiuc.edu/PR733 . --- Diffs of the changes: (+1 -1) Intrinsics.td | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/include/llvm/Intrinsics.td diff -u llvm/include/llvm/Intrinsics.td:1.33 llvm/include/llvm/Intrinsics.td:1.34 --- llvm/include/llvm/Intrinsics.td:1.33 Mon Apr 10 17:02:38 2006 +++ llvm/include/llvm/Intrinsics.td Thu Apr 13 13:23:48 2006 @@ -176,7 +176,7 @@ // NOTE: these are internal interfaces. def int_setjmp : Intrinsic<[llvm_int_ty , llvm_ptr_ty]>; def int_longjmp : Intrinsic<[llvm_void_ty, llvm_ptr_ty, llvm_int_ty]>; -def int_sigsetjmp : Intrinsic<[llvm_int_ty , llvm_ptr_ty]>; +def int_sigsetjmp : Intrinsic<[llvm_int_ty , llvm_ptr_ty, llvm_int_ty]>; def int_siglongjmp : Intrinsic<[llvm_void_ty, llvm_ptr_ty, llvm_int_ty]>; //===-------------------- Bit Manipulation Intrinsics ---------------------===// From reid at x10sys.com Thu Apr 13 13:30:10 2006 From: reid at x10sys.com (Reid Spencer) Date: Thu, 13 Apr 2006 13:30:10 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/MachineDebugInfo.cpp Message-ID: <200604131830.NAA14254@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: MachineDebugInfo.cpp updated: 1.37 -> 1.38 --- Log message: Expand some code with temporary variables to rid ourselves of the warning about "dereferencing type-punned pointer will break strict-aliasing rules" --- Diffs of the changes: (+21 -7) MachineDebugInfo.cpp | 28 +++++++++++++++++++++------- 1 files changed, 21 insertions(+), 7 deletions(-) Index: llvm/lib/CodeGen/MachineDebugInfo.cpp diff -u llvm/lib/CodeGen/MachineDebugInfo.cpp:1.37 llvm/lib/CodeGen/MachineDebugInfo.cpp:1.38 --- llvm/lib/CodeGen/MachineDebugInfo.cpp:1.37 Fri Apr 7 11:34:45 2006 +++ llvm/lib/CodeGen/MachineDebugInfo.cpp Thu Apr 13 13:29:58 2006 @@ -580,7 +580,9 @@ void AnchoredDesc::ApplyToFields(DIVisitor *Visitor) { DebugInfoDesc::ApplyToFields(Visitor); - Visitor->Apply((DebugInfoDesc *&)Anchor); + DebugInfoDesc *Tmp = Anchor; + Visitor->Apply(Tmp); + Anchor = (AnchorDesc*)Tmp; } //===----------------------------------------------------------------------===// @@ -670,7 +672,9 @@ Visitor->Apply(Context); Visitor->Apply(Name); - Visitor->Apply((DebugInfoDesc *&)File); + DebugInfoDesc* Tmp = File; + Visitor->Apply(Tmp); + File = (CompileUnitDesc*)Tmp; Visitor->Apply(Line); Visitor->Apply(Size); Visitor->Apply(Align); @@ -775,7 +779,9 @@ void DerivedTypeDesc::ApplyToFields(DIVisitor *Visitor) { TypeDesc::ApplyToFields(Visitor); - Visitor->Apply((DebugInfoDesc *&)FromType); + DebugInfoDesc* Tmp = FromType; + Visitor->Apply(Tmp); + FromType = (TypeDesc*)Tmp; } /// getDescString - Return a string used to compose global names and labels. @@ -975,9 +981,13 @@ Visitor->Apply(Context); Visitor->Apply(Name); - Visitor->Apply((DebugInfoDesc *&)File); + DebugInfoDesc* Tmp1 = File; + Visitor->Apply(Tmp1); + File = (CompileUnitDesc*)Tmp1; Visitor->Apply(Line); - Visitor->Apply((DebugInfoDesc *&)TyDesc); + DebugInfoDesc* Tmp2 = TyDesc; + Visitor->Apply(Tmp2); + TyDesc = (TypeDesc*)Tmp2; } /// getDescString - Return a string used to compose global names and labels. @@ -1024,9 +1034,13 @@ Visitor->Apply(Context); Visitor->Apply(Name); - Visitor->Apply((DebugInfoDesc *&)File); + DebugInfoDesc* Tmp1 = File; + Visitor->Apply(Tmp1); + File = (CompileUnitDesc*)Tmp1; Visitor->Apply(Line); - Visitor->Apply((DebugInfoDesc *&)TyDesc); + DebugInfoDesc* Tmp2 = TyDesc; + Visitor->Apply(Tmp2); + TyDesc = (TypeDesc*)Tmp2; Visitor->Apply(IsStatic); Visitor->Apply(IsDefinition); } From alenhar2 at cs.uiuc.edu Thu Apr 13 14:32:12 2006 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Thu, 13 Apr 2006 14:32:12 -0500 Subject: [llvm-commits] CVS: llvm/lib/Analysis/DataStructure/Local.cpp Message-ID: <200604131932.OAA29987@apoc.cs.uiuc.edu> Changes in directory llvm/lib/Analysis/DataStructure: Local.cpp updated: 1.144 -> 1.145 --- Log message: Handle some kernel code than ends in [0 x sbyte]. I think this is safe --- Diffs of the changes: (+11 -2) Local.cpp | 13 +++++++++++-- 1 files changed, 11 insertions(+), 2 deletions(-) Index: llvm/lib/Analysis/DataStructure/Local.cpp diff -u llvm/lib/Analysis/DataStructure/Local.cpp:1.144 llvm/lib/Analysis/DataStructure/Local.cpp:1.145 --- llvm/lib/Analysis/DataStructure/Local.cpp:1.144 Tue Apr 4 21:42:36 2006 +++ llvm/lib/Analysis/DataStructure/Local.cpp Thu Apr 13 14:31:49 2006 @@ -1116,8 +1116,17 @@ const StructLayout *SL = TD.getStructLayout(CS->getType()); for (unsigned i = 0, e = CS->getNumOperands(); i != e; ++i) { DSNode *NHN = NH.getNode(); - DSNodeHandle NewNH(NHN, NH.getOffset()+(unsigned)SL->MemberOffsets[i]); - MergeConstantInitIntoNode(NewNH, cast(CS->getOperand(i))); + //Some programmers think ending a structure with a [0 x sbyte] is cute + //This should be ok as the allocation type should grow this type when + //it is merged in if it is bigger. + if (SL->MemberOffsets[i] < SL->StructSize) { + DSNodeHandle NewNH(NHN, NH.getOffset()+(unsigned)SL->MemberOffsets[i]); + MergeConstantInitIntoNode(NewNH, cast(CS->getOperand(i))); + } else if (SL->MemberOffsets[i] == SL->StructSize) { + DEBUG(std::cerr << "Zero size element at end of struct\n"); + } else { + assert(0 && "type was smaller than offsets of of struct layout indicate"); + } } } else if (isa(C) || isa(C)) { // Noop From lattner at cs.uiuc.edu Thu Apr 13 14:46:29 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 13 Apr 2006 14:46:29 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CFrontend/2005-02-27-MarkGlobalConstant.c Message-ID: <200604131946.OAA24361@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CFrontend: 2005-02-27-MarkGlobalConstant.c updated: 1.1 -> 1.2 --- Log message: Fix this regex to match what llvmgcc4 produces also --- Diffs of the changes: (+1 -1) 2005-02-27-MarkGlobalConstant.c | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/CFrontend/2005-02-27-MarkGlobalConstant.c diff -u llvm/test/Regression/CFrontend/2005-02-27-MarkGlobalConstant.c:1.1 llvm/test/Regression/CFrontend/2005-02-27-MarkGlobalConstant.c:1.2 --- llvm/test/Regression/CFrontend/2005-02-27-MarkGlobalConstant.c:1.1 Sun Feb 27 12:19:26 2005 +++ llvm/test/Regression/CFrontend/2005-02-27-MarkGlobalConstant.c Thu Apr 13 14:46:16 2006 @@ -1,4 +1,4 @@ -// RUN: %llvmgcc -xc %s -S -o - | grep 'ctor_.* constant ' +// RUN: %llvmgcc -xc %s -S -o - | grep 'internal constant ' // The synthetic global made by the CFE for big initializer should be marked // constant. From alenhar2 at cs.uiuc.edu Thu Apr 13 14:50:30 2006 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Thu, 13 Apr 2006 14:50:30 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Analysis/DSGraph/2006-04-13-ZeroArrayStruct.ll Message-ID: <200604131950.OAA30013@apoc.cs.uiuc.edu> Changes in directory llvm/test/Regression/Analysis/DSGraph: 2006-04-13-ZeroArrayStruct.ll added (r1.1) --- Log message: from the linux kernel --- Diffs of the changes: (+597 -0) 2006-04-13-ZeroArrayStruct.ll | 597 ++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 597 insertions(+) Index: llvm/test/Regression/Analysis/DSGraph/2006-04-13-ZeroArrayStruct.ll diff -c /dev/null llvm/test/Regression/Analysis/DSGraph/2006-04-13-ZeroArrayStruct.ll:1.1 *** /dev/null Thu Apr 13 14:50:17 2006 --- llvm/test/Regression/Analysis/DSGraph/2006-04-13-ZeroArrayStruct.ll Thu Apr 13 14:50:07 2006 *************** *** 0 **** --- 1,597 ---- + ; RUN: llvm-as < %s | analyze -datastructure + + ; ModuleID = 'bug3.bc' + target endian = little + target pointersize = 32 + target triple = "i686-pc-linux-gnu" + + %struct.Qdisc = type { + int (%struct.sk_buff*, %struct.Qdisc*)*, + %struct.sk_buff* (%struct.Qdisc*)*, + uint, + %struct.Qdisc_ops*, + %struct.Qdisc*, + uint, + %typedef.atomic_t, + %struct.sk_buff_head, + %struct.net_device*, + %struct.tc_stats, + int (%struct.sk_buff*, %struct.Qdisc*)*, + %struct.Qdisc*, + [0 x sbyte] } + + %struct.Qdisc_class_ops = type { int (%struct.Qdisc*, uint, %struct.Qdisc*, %struct.Qdisc**)*, %struct.Qdisc* (%struct.Qdisc*, uint)*, uint (%struct.Qdisc*, uint)*, void (%struct.Qdisc*, uint)*, int (%struct.Qdisc*, uint, uint, %struct.rtattr**, uint*)*, int (%struct.Qdisc*, uint)*, void (%struct.Qdisc*, %struct.qdisc_walker*)*, %struct.tcf_proto** (%struct.Qdisc*, uint)*, uint (%struct.Qdisc*, uint, uint)*, void (%struct.Qdisc*, uint)*, int (%struct.Qdisc*, uint, %struct.sk_buff*, %struct.tcmsg*)* } + %struct.Qdisc_ops = type { %struct.Qdisc_ops*, %struct.Qdisc_class_ops*, [16 x sbyte], int, int (%struct.sk_buff*, %struct.Qdisc*)*, %struct.sk_buff* (%struct.Qdisc*)*, int (%struct.sk_buff*, %struct.Qdisc*)*, uint (%struct.Qdisc*)*, int (%struct.Qdisc*, %struct.rtattr*)*, void (%struct.Qdisc*)*, void (%struct.Qdisc*)*, int (%struct.Qdisc*, %struct.rtattr*)*, int (%struct.Qdisc*, %struct.sk_buff*)* } + %struct.ViceFid = type { uint, uint, uint } + %struct.__wait_queue_head = type { %struct.icmp_filter, %struct.list_head } + %struct.address_space = type { %struct.list_head, %struct.list_head, %struct.list_head, uint, %struct.address_space_operations*, %struct.inode*, %struct.vm_area_struct*, %struct.vm_area_struct*, %struct.icmp_filter, int } + %struct.address_space_operations = type { int (%struct.page*)*, int (%struct.file*, %struct.page*)*, int (%struct.page*)*, int (%struct.file*, %struct.page*, uint, uint)*, int (%struct.file*, %struct.page*, uint, uint)*, int (%struct.address_space*, int)*, int (%struct.page*, uint)*, int (%struct.page*, int)*, int (int, %struct.inode*, %struct.kiobuf*, uint, int)*, int (int, %struct.file*, %struct.kiobuf*, uint, int)*, void (%struct.page*)* } + %struct.affs_bm_info = type { uint, uint } + %struct.block_device = type { %struct.list_head, %typedef.atomic_t, %struct.inode*, ushort, int, %struct.block_device_operations*, %struct.semaphore, %struct.list_head } + %struct.block_device_operations = type opaque + %struct.buffer_head = type { %struct.buffer_head*, uint, ushort, ushort, ushort, %typedef.atomic_t, ushort, uint, uint, %struct.buffer_head*, %struct.buffer_head*, %struct.buffer_head*, %struct.buffer_head*, %struct.buffer_head**, sbyte*, %struct.page*, void (%struct.buffer_head*, int)*, sbyte*, uint, %struct.__wait_queue_head, %struct.list_head } + %struct.char_device = type { %struct.list_head, %typedef.atomic_t, ushort, %typedef.atomic_t, %struct.semaphore } + %struct.completion = type { uint, %struct.__wait_queue_head } + %struct.ctl_table = type { int, sbyte*, sbyte*, int, ushort, %struct.ctl_table*, int (%struct.ctl_table*, int, %struct.file*, sbyte*, uint*)*, int (%struct.ctl_table*, int*, int, sbyte*, uint*, sbyte*, uint, sbyte**)*, %struct.proc_dir_entry*, sbyte*, sbyte* } + %struct.dentry = type { %typedef.atomic_t, uint, %struct.inode*, %struct.dentry*, %struct.list_head, %struct.list_head, %struct.list_head, %struct.list_head, %struct.list_head, int, %struct.qstr, uint, %struct.dentry_operations*, %struct.super_block*, uint, sbyte*, [16 x ubyte] } + %struct.dentry_operations = type { int (%struct.dentry*, int)*, int (%struct.dentry*, %struct.qstr*)*, int (%struct.dentry*, %struct.qstr*, %struct.qstr*)*, int (%struct.dentry*)*, void (%struct.dentry*)*, void (%struct.dentry*, %struct.inode*)* } + %struct.dev_mc_list = type { %struct.dev_mc_list*, [8 x ubyte], ubyte, int, int } + %struct.dnotify_struct = type opaque + %struct.dquot = type { %struct.list_head, %struct.list_head, %struct.list_head, %struct.__wait_queue_head, %struct.__wait_queue_head, int, int, %struct.super_block*, uint, ushort, long, short, short, uint, %struct.mem_dqblk } + %struct.dquot_operations = type { void (%struct.inode*, int)*, void (%struct.inode*)*, int (%struct.inode*, ulong, int)*, int (%struct.inode*, uint)*, void (%struct.inode*, ulong)*, void (%struct.inode*, uint)*, int (%struct.inode*, %struct.iattr*)*, int (%struct.dquot*)* } + %struct.dst_entry = type { %struct.dst_entry*, %typedef.atomic_t, int, %struct.net_device*, int, int, uint, uint, uint, uint, uint, uint, uint, uint, uint, uint, uint, uint, uint, int, %struct.neighbour*, %struct.hh_cache*, int (%struct.sk_buff*)*, int (%struct.sk_buff*)*, %struct.dst_ops*, [0 x sbyte] } + %struct.dst_ops = type { ushort, ushort, uint, int ()*, %struct.dst_entry* (%struct.dst_entry*, uint)*, %struct.dst_entry* (%struct.dst_entry*, %struct.sk_buff*)*, void (%struct.dst_entry*)*, %struct.dst_entry* (%struct.dst_entry*)*, void (%struct.sk_buff*)*, int, %typedef.atomic_t, %struct.kmem_cache_s* } + %struct.exec_domain = type opaque + %struct.ext2_inode_info = type { [15 x uint], uint, uint, ubyte, ubyte, uint, uint, uint, uint, uint, uint, uint, uint, uint, int } + %struct.ext3_inode_info = type { [15 x uint], uint, uint, uint, uint, uint, uint, uint, uint, uint, %struct.list_head, long, %struct.rw_semaphore } + %struct.fasync_struct = type { int, int, %struct.fasync_struct*, %struct.file* } + %struct.file = type { %struct.list_head, %struct.dentry*, %struct.vfsmount*, %struct.file_operations*, %typedef.atomic_t, uint, ushort, long, uint, uint, uint, uint, uint, %struct.fown_struct, uint, uint, int, uint, sbyte*, %struct.kiobuf*, int } + %struct.file_lock = type { %struct.file_lock*, %struct.list_head, %struct.list_head, %struct.files_struct*, uint, %struct.__wait_queue_head, %struct.file*, ubyte, ubyte, long, long, void (%struct.file_lock*)*, void (%struct.file_lock*)*, void (%struct.file_lock*)*, %struct.fasync_struct*, uint, { %struct.nfs_lock_info } } + %struct.file_operations = type { %struct.module*, long (%struct.file*, long, int)*, int (%struct.file*, sbyte*, uint, long*)*, int (%struct.file*, sbyte*, uint, long*)*, int (%struct.file*, sbyte*, int (sbyte*, sbyte*, int, long, uint, uint)*)*, uint (%struct.file*, %struct.poll_table_struct*)*, int (%struct.inode*, %struct.file*, uint, uint)*, int (%struct.file*, %struct.vm_area_struct*)*, int (%struct.inode*, %struct.file*)*, int (%struct.file*)*, int (%struct.inode*, %struct.file*)*, int (%struct.file*, %struct.dentry*, int)*, int (int, %struct.file*, int)*, int (%struct.file*, int, %struct.file_lock*)*, int (%struct.file*, %struct.iovec*, uint, long*)*, int (%struct.file*, %struct.iovec*, uint, long*)*, int (%struct.file*, %struct.page*, int, uint, long*, int)*, uint (%struct.file*, uint, uint, uint, uint)* } + %struct.file_system_type = type { sbyte*, int, %struct.super_block* (%struct.super_block*, sbyte*, int)*, %struct.module*, %struct.file_system_type*, %struct.list_head } + %struct.files_struct = type { %typedef.atomic_t, %typedef.rwlock_t, int, int, int, %struct.file**, %typedef.__kernel_fd_set*, %typedef.__kernel_fd_set*, %typedef.__kernel_fd_set, %typedef.__kernel_fd_set, [32 x %struct.file*] } + %struct.fown_struct = type { int, uint, uint, int } + %struct.fs_disk_quota = type { sbyte, sbyte, ushort, uint, ulong, ulong, ulong, ulong, ulong, ulong, int, int, ushort, ushort, int, ulong, ulong, ulong, int, ushort, short, [8 x sbyte] } + %struct.fs_qfilestat = type { ulong, ulong, uint } + %struct.fs_quota_stat = type { sbyte, ushort, sbyte, %struct.fs_qfilestat, %struct.fs_qfilestat, uint, int, int, int, ushort, ushort } + %struct.fs_struct = type { %typedef.atomic_t, %typedef.rwlock_t, int, %struct.dentry*, %struct.dentry*, %struct.dentry*, %struct.vfsmount*, %struct.vfsmount*, %struct.vfsmount* } + %struct.hh_cache = type { %struct.hh_cache*, %typedef.atomic_t, ushort, int, int (%struct.sk_buff*)*, %typedef.rwlock_t, [32 x uint] } + %struct.i387_fxsave_struct = type { ushort, ushort, ushort, ushort, int, int, int, int, int, int, [32 x int], [32 x int], [56 x int] } + %struct.iattr = type { uint, ushort, uint, uint, long, int, int, int, uint } + %struct.icmp_filter = type { uint } + %struct.if_dqblk = type { ulong, ulong, ulong, ulong, ulong, ulong, ulong, ulong, uint } + %struct.if_dqinfo = type { ulong, ulong, uint, uint } + %struct.ifmap = type { uint, uint, ushort, ubyte, ubyte, ubyte } + %struct.ifreq = type { { [16 x sbyte] }, { [2 x ulong] } } + %struct.inode = type { %struct.list_head, %struct.list_head, %struct.list_head, %struct.list_head, %struct.list_head, uint, %typedef.atomic_t, ushort, ushort, ushort, uint, uint, ushort, long, int, int, int, uint, uint, uint, uint, ushort, %struct.semaphore, %struct.rw_semaphore, %struct.semaphore, %struct.inode_operations*, %struct.file_operations*, %struct.super_block*, %struct.__wait_queue_head, %struct.file_lock*, %struct.address_space*, %struct.address_space, [2 x %struct.dquot*], %struct.list_head, %struct.pipe_inode_info*, %struct.block_device*, %struct.char_device*, uint, %struct.dnotify_struct*, uint, uint, ubyte, %typedef.atomic_t, uint, uint, { %struct.ext2_inode_info, %struct.ext3_inode_info, %struct.msdos_inode_info, %struct.iso_inode_info, %struct.nfs_inode_info, %struct.shmem_inode_info, %struct.proc_inode_info, %struct.socket, %struct.usbdev_inode_info, sbyte* } } + %struct.inode_operations = type { int (%struct.inode*, %struct.dentry*, int)*, %struct.dentry* (%struct.inode*, %struct.dentry*)*, int (%struct.dentry*, %struct.inode*, %struct.dentry*)*, int (%struct.inode*, %struct.dentry*)*, int (%struct.inode*, %struct.dentry*, sbyte*)*, int (%struct.inode*, %struct.dentry*, int)*, int (%struct.inode*, %struct.dentry*)*, int (%struct.inode*, %struct.dentry*, int, int)*, int (%struct.inode*, %struct.dentry*, %struct.inode*, %struct.dentry*)*, int (%struct.dentry*, sbyte*, int)*, int (%struct.dentry*, %struct.nameidata*)*, void (%struct.inode*)*, int (%struct.inode*, int)*, int (%struct.dentry*)*, int (%struct.dentry*, %struct.iattr*)*, int (%struct.dentry*, %struct.iattr*)*, int (%struct.dentry*, sbyte*, sbyte*, uint, int)*, int (%struct.dentry*, sbyte*, sbyte*, uint)*, int (%struct.dentry*, sbyte*, uint)*, int (%struct.dentry*, sbyte*)* } + %struct.iovec = type { sbyte*, uint } + %struct.ip_options = type { uint, ubyte, ubyte, ubyte, ubyte, ubyte, ubyte, ubyte, ubyte, [0 x ubyte] } + %struct.iso_inode_info = type { uint, ubyte, [3 x ubyte], uint, int } + %struct.iw_handler_def = type opaque + %struct.iw_statistics = type opaque + %struct.k_sigaction = type { %struct.sigaction } + %struct.kern_ipc_perm = type { int, uint, uint, uint, uint, ushort, uint } + %struct.kiobuf = type opaque + %struct.kmem_cache_s = type opaque + %struct.linger = type { int, int } + %struct.linux_binfmt = type { %struct.linux_binfmt*, %struct.module*, int (%struct.linux_binprm*, %struct.pt_regs*)*, int (%struct.file*)*, int (int, %struct.pt_regs*, %struct.file*)*, uint, int (%struct.linux_binprm*, sbyte*)* } + %struct.linux_binprm = type { [128 x sbyte], [32 x %struct.page*], uint, int, %struct.file*, int, int, uint, uint, uint, int, int, sbyte*, uint, uint } + %struct.list_head = type { %struct.list_head*, %struct.list_head* } + %struct.llva_sigcontext = type { %typedef.llva_icontext_t, %typedef.llva_fp_state_t, uint, uint, uint, uint, [1 x uint], sbyte* } + %struct.mem_dqblk = type { uint, uint, ulong, uint, uint, uint, int, int } + %struct.mem_dqinfo = type { %struct.quota_format_type*, int, uint, uint, { %struct.ViceFid } } + %struct.mm_struct = type { %struct.vm_area_struct*, %struct.rb_root_s, %struct.vm_area_struct*, %struct.icmp_filter*, %typedef.atomic_t, %typedef.atomic_t, int, %struct.rw_semaphore, %struct.icmp_filter, %struct.list_head, uint, uint, uint, uint, uint, uint, uint, uint, uint, uint, uint, uint, uint, uint, uint, uint, uint, uint, %struct.iovec } + %struct.module = type { uint, %struct.module*, sbyte*, uint, %typedef.atomic_t, uint, uint, uint, %struct.module_symbol*, %struct.module_ref*, %struct.module_ref*, int ()*, void ()*, %struct.affs_bm_info*, %struct.affs_bm_info*, %struct.module_persist*, %struct.module_persist*, int ()*, int, sbyte*, sbyte*, sbyte*, sbyte*, sbyte* } + %struct.module_persist = type opaque + %struct.module_ref = type { %struct.module*, %struct.module*, %struct.module_ref* } + %struct.module_symbol = type { uint, sbyte* } + %struct.msdos_inode_info = type { uint, int, int, int, int, int, %struct.inode*, %struct.list_head } + %struct.msghdr = type { sbyte*, int, %struct.iovec*, uint, sbyte*, uint, uint } + %struct.nameidata = type { %struct.dentry*, %struct.vfsmount*, %struct.qstr, uint, int } + %struct.namespace = type opaque + %struct.nda_cacheinfo = type { uint, uint, uint, uint } + %struct.neigh_ops = type { int, void (%struct.neighbour*)*, void (%struct.neighbour*, %struct.sk_buff*)*, void (%struct.neighbour*, %struct.sk_buff*)*, int (%struct.sk_buff*)*, int (%struct.sk_buff*)*, int (%struct.sk_buff*)*, int (%struct.sk_buff*)* } + %struct.neigh_parms = type { %struct.neigh_parms*, int (%struct.neighbour*)*, %struct.neigh_table*, int, sbyte*, sbyte*, int, int, int, int, int, int, int, int, int, int, int, int, int } + %struct.neigh_table = type { %struct.neigh_table*, int, int, int, uint (sbyte*, %struct.net_device*)*, int (%struct.neighbour*)*, int (%struct.pneigh_entry*)*, void (%struct.pneigh_entry*)*, void (%struct.sk_buff*)*, sbyte*, %struct.neigh_parms, int, int, int, int, uint, %struct.timer_list, %struct.timer_list, %struct.sk_buff_head, int, %typedef.rwlock_t, uint, %struct.neigh_parms*, %struct.kmem_cache_s*, %struct.tasklet_struct, %struct.nda_cacheinfo, [32 x %struct.neighbour*], [16 x %struct.pneigh_entry*] } + %struct.neighbour = type { %struct.neighbour*, %struct.neigh_table*, %struct.neigh_parms*, %struct.net_device*, uint, uint, uint, ubyte, ubyte, ubyte, ubyte, %typedef.atomic_t, %typedef.rwlock_t, [8 x ubyte], %struct.hh_cache*, %typedef.atomic_t, int (%struct.sk_buff*)*, %struct.sk_buff_head, %struct.timer_list, %struct.neigh_ops*, [0 x ubyte] } + %struct.net_bridge_port = type opaque + %struct.net_device = type { [16 x sbyte], uint, uint, uint, uint, uint, uint, ubyte, ubyte, uint, %struct.net_device*, int (%struct.net_device*)*, %struct.net_device*, int, int, %struct.net_device_stats* (%struct.net_device*)*, %struct.iw_statistics* (%struct.net_device*)*, %struct.iw_handler_def*, uint, uint, ushort, ushort, ushort, ushort, uint, ushort, ushort, sbyte*, %struct.net_device*, [8 x ubyte], [8 x ubyte], ubyte, %struct.dev_mc_list*, int, int, int, int, %struct.timer_list, sbyte*, sbyte*, sbyte*, sbyte*, sbyte*, %struct.list_head, int, int, %struct.Qdisc*, %struct.Qdisc*, %struct.Qdisc*, %struct.Qdisc*, uint, %struct.icmp_filter, int, %struct.icmp_filter, %typedef.atomic_t, int, int, void (%struct.net_device*)*, void (%struct.net_device*)*, int (%struct.net_device*)*, int (%struct.net_device*)*, int (%struct.sk_buff*, %struct.net_device*)*, int (%struct.net_device*, int*)*, int (%struct.sk_buff*, %struct.net_device*, ushort, sbyte*, sbyte*, uint)*, int (%struc! t.sk_buff*)*, void (%struct.net_device*)*, int (%struct.net_device*, sbyte*)*, int (%struct.net_device*, %struct.ifreq*, int)*, int (%struct.net_device*, %struct.ifmap*)*, int (%struct.neighbour*, %struct.hh_cache*)*, void (%struct.hh_cache*, %struct.net_device*, ubyte*)*, int (%struct.net_device*, int)*, void (%struct.net_device*)*, void (%struct.net_device*, %struct.vlan_group*)*, void (%struct.net_device*, ushort)*, void (%struct.net_device*, ushort)*, int (%struct.sk_buff*, ubyte*)*, int (%struct.net_device*, %struct.neigh_parms*)*, int (%struct.net_device*, %struct.dst_entry*)*, %struct.module*, %struct.net_bridge_port* } + %struct.net_device_stats = type { uint, uint, uint, uint, uint, uint, uint, uint, uint, uint, uint, uint, uint, uint, uint, uint, uint, uint, uint, uint, uint, uint, uint } + %struct.nf_conntrack = type { %typedef.atomic_t, void (%struct.nf_conntrack*)* } + %struct.nf_ct_info = type { %struct.nf_conntrack* } + %struct.nfs_fh = type { ushort, [64 x ubyte] } + %struct.nfs_inode_info = type { ulong, %struct.nfs_fh, ushort, uint, ulong, ulong, ulong, uint, uint, uint, [2 x uint], %struct.list_head, %struct.list_head, %struct.list_head, %struct.list_head, uint, uint, uint, uint, %struct.rpc_cred* } + %struct.nfs_lock_info = type { uint, uint, %struct.nlm_host* } + %struct.nlm_host = type opaque + %struct.notifier_block = type { int (%struct.notifier_block*, uint, sbyte*)*, %struct.notifier_block*, int } + %struct.open_request = type { %struct.open_request*, uint, uint, ushort, ushort, ubyte, ubyte, ushort, uint, uint, uint, uint, %struct.or_calltable*, %struct.sock*, { %struct.tcp_v4_open_req } } + %struct.or_calltable = type { int, int (%struct.sock*, %struct.open_request*, %struct.dst_entry*)*, void (%struct.sk_buff*, %struct.open_request*)*, void (%struct.open_request*)*, void (%struct.sk_buff*)* } + %struct.page = type { %struct.list_head, %struct.address_space*, uint, %struct.page*, %typedef.atomic_t, uint, %struct.list_head, %struct.page**, %struct.buffer_head* } + %struct.pipe_inode_info = type { %struct.__wait_queue_head, sbyte*, uint, uint, uint, uint, uint, uint, uint, uint } + %struct.pneigh_entry = type { %struct.pneigh_entry*, %struct.net_device*, [0 x ubyte] } + %struct.poll_table_page = type opaque + %struct.poll_table_struct = type { int, %struct.poll_table_page* } + %struct.proc_dir_entry = type { ushort, ushort, sbyte*, ushort, ushort, uint, uint, uint, %struct.inode_operations*, %struct.file_operations*, int (sbyte*, sbyte**, int, int)*, %struct.module*, %struct.proc_dir_entry*, %struct.proc_dir_entry*, %struct.proc_dir_entry*, sbyte*, int (sbyte*, sbyte**, int, int, int*, sbyte*)*, int (%struct.file*, sbyte*, uint, sbyte*)*, %typedef.atomic_t, int, ushort } + %struct.proc_inode_info = type { %struct.task_struct*, int, { int (%struct.task_struct*, sbyte*)* }, %struct.file* } + %struct.proto = type { void (%struct.sock*, int)*, int (%struct.sock*, %struct.sockaddr*, int)*, int (%struct.sock*, int)*, %struct.sock* (%struct.sock*, int, int*)*, int (%struct.sock*, int, uint)*, int (%struct.sock*)*, int (%struct.sock*)*, void (%struct.sock*, int)*, int (%struct.sock*, int, int, sbyte*, int)*, int (%struct.sock*, int, int, sbyte*, int*)*, int (%struct.sock*, %struct.msghdr*, int)*, int (%struct.sock*, %struct.msghdr*, int, int, int, int*)*, int (%struct.sock*, %struct.sockaddr*, int)*, int (%struct.sock*, %struct.sk_buff*)*, void (%struct.sock*)*, void (%struct.sock*)*, int (%struct.sock*, ushort)*, [32 x sbyte], [32 x { int, [28 x ubyte] }] } + %struct.proto_ops = type { int, int (%struct.socket*)*, int (%struct.socket*, %struct.sockaddr*, int)*, int (%struct.socket*, %struct.sockaddr*, int, int)*, int (%struct.socket*, %struct.socket*)*, int (%struct.socket*, %struct.socket*, int)*, int (%struct.socket*, %struct.sockaddr*, int*, int)*, uint (%struct.file*, %struct.socket*, %struct.poll_table_struct*)*, int (%struct.socket*, uint, uint)*, int (%struct.socket*, int)*, int (%struct.socket*, int)*, int (%struct.socket*, int, int, sbyte*, int)*, int (%struct.socket*, int, int, sbyte*, int*)*, int (%struct.socket*, %struct.msghdr*, int, %struct.scm_cookie*)*, int (%struct.socket*, %struct.msghdr*, int, int, %struct.scm_cookie*)*, int (%struct.file*, %struct.socket*, %struct.vm_area_struct*)*, int (%struct.socket*, %struct.page*, int, uint, int)* } + %struct.pt_regs = type { int, int, int, int, int, int, int, int, int, int, int, int, int, int, int } + %struct.qdisc_walker = type { int, int, int, int (%struct.Qdisc*, uint, %struct.qdisc_walker*)* } + %struct.qstr = type { ubyte*, uint, uint } + %struct.quota_format_ops = type { int (%struct.super_block*, int)*, int (%struct.super_block*, int)*, int (%struct.super_block*, int)*, int (%struct.super_block*, int)*, int (%struct.dquot*)*, int (%struct.dquot*)* } + %struct.quota_format_type = type opaque + %struct.quota_info = type { uint, %struct.semaphore, %struct.semaphore, [2 x %struct.file*], [2 x %struct.mem_dqinfo], [2 x %struct.quota_format_ops*] } + %struct.quotactl_ops = type { int (%struct.super_block*, int, int, sbyte*)*, int (%struct.super_block*, int)*, int (%struct.super_block*, int)*, int (%struct.super_block*, int, %struct.if_dqinfo*)*, int (%struct.super_block*, int, %struct.if_dqinfo*)*, int (%struct.super_block*, int, uint, %struct.if_dqblk*)*, int (%struct.super_block*, int, uint, %struct.if_dqblk*)*, int (%struct.super_block*, %struct.fs_quota_stat*)*, int (%struct.super_block*, uint, int)*, int (%struct.super_block*, int, uint, %struct.fs_disk_quota*)*, int (%struct.super_block*, int, uint, %struct.fs_disk_quota*)* } + %struct.rb_node_s = type { %struct.rb_node_s*, int, %struct.rb_node_s*, %struct.rb_node_s* } + %struct.rb_root_s = type { %struct.rb_node_s* } + %struct.revectored_struct = type { [8 x uint] } + %struct.rpc_cred = type opaque + %struct.rtattr = type { ushort, ushort } + %struct.rw_semaphore = type { int, %struct.icmp_filter, %struct.list_head } + %struct.scm_cookie = type { %struct.ViceFid, %struct.scm_fp_list*, uint } + %struct.scm_fp_list = type { int, [255 x %struct.file*] } + %struct.sem_array = type { %struct.kern_ipc_perm, int, int, %struct.linger*, %struct.sem_queue*, %struct.sem_queue**, %struct.sem_undo*, uint } + %struct.sem_queue = type { %struct.sem_queue*, %struct.sem_queue**, %struct.task_struct*, %struct.sem_undo*, int, int, %struct.sem_array*, int, %struct.sembuf*, int, int } + %struct.sem_undo = type { %struct.sem_undo*, %struct.sem_undo*, int, short* } + %struct.semaphore = type { %typedef.atomic_t, int, %struct.__wait_queue_head } + %struct.sembuf = type { ushort, short, short } + %struct.seq_file = type opaque + %struct.shmem_inode_info = type { %struct.icmp_filter, uint, [16 x %struct.icmp_filter], sbyte**, uint, uint, %struct.list_head, %struct.inode* } + %struct.sigaction = type { void (int)*, uint, void ()*, %typedef.sigset_t } + %struct.siginfo = type { int, int, int, { [29 x int] } } + %struct.signal_struct = type { %typedef.atomic_t, [64 x %struct.k_sigaction], %struct.icmp_filter } + %struct.sigpending = type { %struct.sigqueue*, %struct.sigqueue**, %typedef.sigset_t } + %struct.sigqueue = type { %struct.sigqueue*, %struct.siginfo } + %struct.sk_buff = type { %struct.sk_buff*, %struct.sk_buff*, %struct.sk_buff_head*, %struct.sock*, %struct.linger, %struct.net_device*, %struct.net_device*, { ubyte* }, { ubyte* }, { ubyte* }, %struct.dst_entry*, [48 x sbyte], uint, uint, uint, ubyte, ubyte, ubyte, ubyte, uint, %typedef.atomic_t, ushort, ushort, uint, ubyte*, ubyte*, ubyte*, ubyte*, void (%struct.sk_buff*)*, uint, uint, %struct.nf_ct_info*, uint } + %struct.sk_buff_head = type { %struct.sk_buff*, %struct.sk_buff*, uint, %struct.icmp_filter } + %struct.sock = type { uint, uint, ushort, ushort, int, %struct.sock*, %struct.sock**, %struct.sock*, %struct.sock**, ubyte, ubyte, ushort, ushort, ubyte, ubyte, %typedef.atomic_t, %typedef.socket_lock_t, int, %struct.__wait_queue_head*, %struct.dst_entry*, %typedef.rwlock_t, %typedef.atomic_t, %struct.sk_buff_head, %typedef.atomic_t, %struct.sk_buff_head, %typedef.atomic_t, int, int, uint, uint, int, %struct.sock*, sbyte, sbyte, sbyte, sbyte, sbyte, sbyte, sbyte, sbyte, sbyte, ubyte, ubyte, ubyte, ubyte, int, int, uint, int, %struct.sock*, { %struct.sk_buff*, %struct.sk_buff* }, %typedef.rwlock_t, %struct.sk_buff_head, %struct.proto*, { %struct.tcp_opt }, int, int, ushort, ushort, uint, ushort, ubyte, ubyte, %struct.ViceFid, int, int, int, { %struct.unix_opt }, %struct.timer_list, %struct.linger, %struct.socket*, sbyte*, void (%struct.sock*)*, void (%struct.sock*, int)*, void (%struct.sock*)*, void (%struct.sock*)*, int (%struct.sock*, %struct.sk_buff*)*, void (%struct.so! ck*)* } + %struct.sockaddr = type { ushort, [14 x sbyte] } + %struct.sockaddr_un = type { ushort, [108 x sbyte] } + %struct.socket = type { uint, uint, %struct.proto_ops*, %struct.inode*, %struct.fasync_struct*, %struct.file*, %struct.sock*, %struct.__wait_queue_head, short, ubyte } + %struct.statfs = type { int, int, int, int, int, int, int, %typedef.__kernel_fsid_t, int, [6 x int] } + %struct.super_block = type { %struct.list_head, ushort, uint, ubyte, ubyte, ulong, %struct.file_system_type*, %struct.super_operations*, %struct.dquot_operations*, %struct.quotactl_ops*, uint, uint, %struct.dentry*, %struct.rw_semaphore, %struct.semaphore, int, %typedef.atomic_t, %struct.list_head, %struct.list_head, %struct.list_head, %struct.block_device*, %struct.list_head, %struct.quota_info, { [115 x uint] }, %struct.semaphore, %struct.semaphore } + %struct.super_operations = type { %struct.inode* (%struct.super_block*)*, void (%struct.inode*)*, void (%struct.inode*)*, void (%struct.inode*, sbyte*)*, void (%struct.inode*)*, void (%struct.inode*, int)*, void (%struct.inode*)*, void (%struct.inode*)*, void (%struct.super_block*)*, void (%struct.super_block*)*, int (%struct.super_block*)*, void (%struct.super_block*)*, void (%struct.super_block*)*, int (%struct.super_block*, %struct.statfs*)*, int (%struct.super_block*, int*, sbyte*)*, void (%struct.inode*)*, void (%struct.super_block*)*, %struct.dentry* (%struct.super_block*, uint*, int, int, int)*, int (%struct.dentry*, uint*, int*, int)*, int (%struct.seq_file*, %struct.vfsmount*)* } + %struct.task_struct = type { int, uint, int, %struct.icmp_filter, %struct.exec_domain*, int, uint, int, int, int, uint, %struct.mm_struct*, int, uint, uint, %struct.list_head, uint, %struct.task_struct*, %struct.task_struct*, %struct.mm_struct*, %struct.list_head, uint, uint, %struct.linux_binfmt*, int, int, int, uint, int, int, int, int, int, int, int, %struct.task_struct*, %struct.task_struct*, %struct.task_struct*, %struct.task_struct*, %struct.task_struct*, %struct.list_head, %struct.task_struct*, %struct.task_struct**, %struct.__wait_queue_head, %struct.completion*, uint, uint, uint, uint, uint, uint, uint, %struct.timer_list, %struct.tms, uint, [32 x int], [32 x int], uint, uint, uint, uint, uint, uint, int, uint, uint, uint, uint, uint, uint, uint, uint, int, [32 x uint], uint, uint, uint, int, %struct.user_struct*, [11 x %struct.affs_bm_info], ushort, [16 x sbyte], int, int, %struct.tty_struct*, uint, %struct.sem_undo*, %struct.sem_queue*, %struct.thread_struct, %! struct.fs_struct*, %struct.files_struct*, %struct.namespace*, %struct.icmp_filter, %struct.signal_struct*, %typedef.sigset_t, %struct.sigpending, uint, uint, int (sbyte*)*, sbyte*, %typedef.sigset_t*, uint, uint, %struct.icmp_filter, sbyte*, %struct.llva_sigcontext*, uint, %struct.task_struct*, uint, %typedef.llva_icontext_t, %typedef.llva_fp_state_t, uint*, int, sbyte* } + %struct.tasklet_struct = type { %struct.tasklet_struct*, uint, %typedef.atomic_t, void (uint)*, uint } + %struct.tc_stats = type { ulong, uint, uint, uint, uint, uint, uint, uint, %struct.icmp_filter* } + %struct.tcf_proto = type { %struct.tcf_proto*, sbyte*, int (%struct.sk_buff*, %struct.tcf_proto*, %struct.affs_bm_info*)*, uint, uint, uint, %struct.Qdisc*, sbyte*, %struct.tcf_proto_ops* } + %struct.tcf_proto_ops = type { %struct.tcf_proto_ops*, [16 x sbyte], int (%struct.sk_buff*, %struct.tcf_proto*, %struct.affs_bm_info*)*, int (%struct.tcf_proto*)*, void (%struct.tcf_proto*)*, uint (%struct.tcf_proto*, uint)*, void (%struct.tcf_proto*, uint)*, int (%struct.tcf_proto*, uint, uint, %struct.rtattr**, uint*)*, int (%struct.tcf_proto*, uint)*, void (%struct.tcf_proto*, %struct.tcf_walker*)*, int (%struct.tcf_proto*, uint, %struct.sk_buff*, %struct.tcmsg*)* } + %struct.tcf_walker = type { int, int, int, int (%struct.tcf_proto*, uint, %struct.tcf_walker*)* } + %struct.tcmsg = type { ubyte, ubyte, ushort, int, uint, uint, uint } + %struct.tcp_bind_bucket = type { ushort, short, %struct.tcp_bind_bucket*, %struct.sock*, %struct.tcp_bind_bucket** } + %struct.tcp_bind_hashbucket = type { %struct.icmp_filter, %struct.tcp_bind_bucket* } + %struct.tcp_ehash_bucket = type { %typedef.rwlock_t, %struct.sock* } + %struct.tcp_func = type { int (%struct.sk_buff*)*, void (%struct.sock*, %struct.tcphdr*, int, %struct.sk_buff*)*, int (%struct.sock*)*, int (%struct.sock*, %struct.sk_buff*)*, %struct.sock* (%struct.sock*, %struct.sk_buff*, %struct.open_request*, %struct.dst_entry*)*, int (%struct.sock*)*, ushort, int (%struct.sock*, int, int, sbyte*, int)*, int (%struct.sock*, int, int, sbyte*, int*)*, void (%struct.sock*, %struct.sockaddr*)*, int } + %struct.tcp_hashinfo = type { %struct.tcp_ehash_bucket*, %struct.tcp_bind_hashbucket*, int, int, [32 x %struct.sock*], %typedef.rwlock_t, %typedef.atomic_t, %struct.__wait_queue_head, %struct.icmp_filter } + %struct.tcp_listen_opt = type { ubyte, int, int, int, uint, [512 x %struct.open_request*] } + %struct.tcp_opt = type { int, uint, uint, uint, uint, uint, uint, uint, { ubyte, ubyte, ubyte, ubyte, uint, uint, uint, ushort, ushort }, { %struct.sk_buff_head, %struct.task_struct*, %struct.iovec*, int, int }, uint, uint, uint, uint, ushort, ushort, ushort, ubyte, ubyte, ubyte, ubyte, ubyte, ubyte, uint, uint, uint, uint, uint, uint, uint, uint, uint, uint, uint, ushort, ushort, uint, uint, uint, %struct.timer_list, %struct.timer_list, %struct.sk_buff_head, %struct.tcp_func*, %struct.sk_buff*, %struct.page*, uint, uint, uint, uint, uint, uint, sbyte, sbyte, sbyte, sbyte, ubyte, ubyte, ubyte, ubyte, uint, uint, uint, int, ushort, ubyte, ubyte, [1 x %struct.affs_bm_info], [4 x %struct.affs_bm_info], uint, uint, ubyte, ubyte, ushort, ubyte, ubyte, ushort, uint, uint, uint, uint, uint, uint, int, uint, ushort, ubyte, ubyte, uint, %typedef.rwlock_t, %struct.tcp_listen_opt*, %struct.open_request*, %struct.open_request*, int, uint, uint, int, int, uint, uint } + %struct.tcp_v4_open_req = type { uint, uint, %struct.ip_options* } + %struct.tcphdr = type { ushort, ushort, uint, uint, ushort, ushort, ushort, ushort } + %struct.termios = type { uint, uint, uint, uint, ubyte, [19 x ubyte] } + %struct.thread_struct = type { uint, uint, uint, uint, uint, [8 x uint], uint, uint, uint, %union.i387_union, %struct.vm86_struct*, uint, uint, uint, uint, int, [33 x uint] } + %struct.timer_list = type { %struct.list_head, uint, uint, void (uint)* } + %struct.tms = type { int, int, int, int } + %struct.tq_struct = type { %struct.list_head, uint, void (sbyte*)*, sbyte* } + %struct.tty_driver = type { int, sbyte*, sbyte*, int, short, short, short, short, short, %struct.termios, int, int*, %struct.proc_dir_entry*, %struct.tty_driver*, %struct.tty_struct**, %struct.termios**, %struct.termios**, sbyte*, int (%struct.tty_struct*, %struct.file*)*, void (%struct.tty_struct*, %struct.file*)*, int (%struct.tty_struct*, int, ubyte*, int)*, void (%struct.tty_struct*, ubyte)*, void (%struct.tty_struct*)*, int (%struct.tty_struct*)*, int (%struct.tty_struct*)*, int (%struct.tty_struct*, %struct.file*, uint, uint)*, void (%struct.tty_struct*, %struct.termios*)*, void (%struct.tty_struct*)*, void (%struct.tty_struct*)*, void (%struct.tty_struct*)*, void (%struct.tty_struct*)*, void (%struct.tty_struct*)*, void (%struct.tty_struct*, int)*, void (%struct.tty_struct*)*, void (%struct.tty_struct*)*, void (%struct.tty_struct*, int)*, void (%struct.tty_struct*, sbyte)*, int (sbyte*, sbyte**, int, int, int*, sbyte*)*, int (%struct.file*, sbyte*, uint, sbyte*)*, ! %struct.tty_driver*, %struct.tty_driver* } + %struct.tty_flip_buffer = type { %struct.tq_struct, %struct.semaphore, sbyte*, ubyte*, int, int, [1024 x ubyte], [1024 x sbyte], [4 x ubyte] } + %struct.tty_ldisc = type { int, sbyte*, int, int, int (%struct.tty_struct*)*, void (%struct.tty_struct*)*, void (%struct.tty_struct*)*, int (%struct.tty_struct*)*, int (%struct.tty_struct*, %struct.file*, ubyte*, uint)*, int (%struct.tty_struct*, %struct.file*, ubyte*, uint)*, int (%struct.tty_struct*, %struct.file*, uint, uint)*, void (%struct.tty_struct*, %struct.termios*)*, uint (%struct.tty_struct*, %struct.file*, %struct.poll_table_struct*)*, void (%struct.tty_struct*, ubyte*, sbyte*, int)*, int (%struct.tty_struct*)*, void (%struct.tty_struct*)* } + %struct.tty_struct = type { int, %struct.tty_driver, %struct.tty_ldisc, %struct.termios*, %struct.termios*, int, int, ushort, uint, int, %struct.udphdr, ubyte, ubyte, %struct.tty_struct*, %struct.fasync_struct*, %struct.tty_flip_buffer, int, int, %struct.__wait_queue_head, %struct.__wait_queue_head, %struct.tq_struct, sbyte*, sbyte*, %struct.list_head, uint, ubyte, ushort, uint, int, [8 x uint], sbyte*, int, int, int, [128 x uint], int, uint, uint, %struct.semaphore, %struct.semaphore, %struct.icmp_filter, %struct.tq_struct } + %struct.udphdr = type { ushort, ushort, ushort, ushort } + %struct.unix_address = type { %typedef.atomic_t, int, uint, [0 x %struct.sockaddr_un] } + %struct.unix_opt = type { %struct.unix_address*, %struct.dentry*, %struct.vfsmount*, %struct.semaphore, %struct.sock*, %struct.sock**, %struct.sock*, %typedef.atomic_t, %typedef.rwlock_t, %struct.__wait_queue_head } + %struct.usb_bus = type opaque + %struct.usbdev_inode_info = type { %struct.list_head, %struct.list_head, { %struct.usb_bus* } } + %struct.user_struct = type { %typedef.atomic_t, %typedef.atomic_t, %typedef.atomic_t, %struct.user_struct*, %struct.user_struct**, uint } + %struct.vfsmount = type { %struct.list_head, %struct.vfsmount*, %struct.dentry*, %struct.dentry*, %struct.super_block*, %struct.list_head, %struct.list_head, %typedef.atomic_t, int, sbyte*, %struct.list_head } + %struct.vlan_group = type opaque + %struct.vm86_regs = type { int, int, int, int, int, int, int, int, int, int, int, int, int, ushort, ushort, int, int, ushort, ushort, ushort, ushort, ushort, ushort, ushort, ushort, ushort, ushort } + %struct.vm86_struct = type { %struct.vm86_regs, uint, uint, uint, %struct.revectored_struct, %struct.revectored_struct } + %struct.vm_area_struct = type { %struct.mm_struct*, uint, uint, %struct.vm_area_struct*, %struct.icmp_filter, uint, %struct.rb_node_s, %struct.vm_area_struct*, %struct.vm_area_struct**, %struct.vm_operations_struct*, uint, %struct.file*, uint, sbyte* } + %struct.vm_operations_struct = type { void (%struct.vm_area_struct*)*, void (%struct.vm_area_struct*)*, %struct.page* (%struct.vm_area_struct*, uint, int)* } + %typedef.__kernel_fd_set = type { [32 x int] } + %typedef.__kernel_fsid_t = type { [2 x int] } + %typedef.atomic_t = type { int } + %typedef.llva_fp_state_t = type { [7 x uint], [20 x uint] } + %typedef.llva_icontext_t = type { uint, uint, uint, uint, uint, uint, uint, uint, uint, uint, uint, uint, uint, uint, uint, uint, uint*, uint } + %typedef.rwlock_t = type { %struct.icmp_filter, %struct.icmp_filter, uint } + %typedef.sigset_t = type { [2 x uint] } + %typedef.socket_lock_t = type { %struct.icmp_filter, uint, %struct.__wait_queue_head } + %union.i387_union = type { %struct.i387_fxsave_struct } + %noqueue_qdisc_ops = global %struct.Qdisc_ops { + %struct.Qdisc_ops* null, + %struct.Qdisc_class_ops* null, + [16 x sbyte] c"noqueue\00\00\00\00\00\00\00\00\00", + int 0, + int (%struct.sk_buff*, %struct.Qdisc*)* %noop_enqueue, + %struct.sk_buff* (%struct.Qdisc*)* %noop_dequeue, + int (%struct.sk_buff*, %struct.Qdisc*)* %noop_requeue, + uint (%struct.Qdisc*)* null, + int (%struct.Qdisc*, %struct.rtattr*)* null, + void (%struct.Qdisc*)* null, + void (%struct.Qdisc*)* null, + int (%struct.Qdisc*, %struct.rtattr*)* null, + int (%struct.Qdisc*, %struct.sk_buff*)* null } ; <%struct.Qdisc_ops*> [#uses=1] + %noqueue_qdisc = global %struct.Qdisc { + int (%struct.sk_buff*, %struct.Qdisc*)* null, + %struct.sk_buff* (%struct.Qdisc*)* %noop_dequeue, + uint 1, + %struct.Qdisc_ops* %noqueue_qdisc_ops, + %struct.Qdisc* null, + uint 0, + %typedef.atomic_t zeroinitializer, + %struct.sk_buff_head zeroinitializer, + %struct.net_device* null, + %struct.tc_stats zeroinitializer, + int (%struct.sk_buff*, %struct.Qdisc*)* null, + %struct.Qdisc* null, + [0 x sbyte] zeroinitializer } ; <%struct.Qdisc*> [#uses=0] + %tcp_hashinfo = global %struct.tcp_hashinfo { + %struct.tcp_ehash_bucket* null, + %struct.tcp_bind_hashbucket* null, + int 0, + int 0, + [32 x %struct.sock*] zeroinitializer, + %typedef.rwlock_t { + %struct.icmp_filter { uint 1 }, + %struct.icmp_filter { uint 1 }, + uint 0 }, + %typedef.atomic_t zeroinitializer, + %struct.__wait_queue_head { %struct.icmp_filter { uint 1 }, %struct.list_head { %struct.list_head* getelementptr (%struct.tcp_hashinfo* %tcp_hashinfo, int 0, uint 7, uint 1), %struct.list_head* getelementptr (%struct.tcp_hashinfo* %tcp_hashinfo, int 0, uint 7, uint 1) } }, + %struct.icmp_filter { uint 1 } } ; <%struct.tcp_hashinfo*> [#uses=1] + %arp_tbl = global %struct.neigh_table { + %struct.neigh_table* null, + int 2, + int 112, + int 4, + uint (sbyte*, %struct.net_device*)* %arp_hash, + int (%struct.neighbour*)* %arp_constructor, + int (%struct.pneigh_entry*)* null, + void (%struct.pneigh_entry*)* null, + void (%struct.sk_buff*)* %parp_redo, + sbyte* getelementptr ([10 x sbyte]* %.str_1, int 0, int 0), + %struct.neigh_parms { + %struct.neigh_parms* null, + int (%struct.neighbour*)* null, + %struct.neigh_table* %arp_tbl, + int 0, + sbyte* null, + sbyte* null, + int 3000, + int 100, + int 6000, + int 3000, + int 500, + int 3, + int 3, + int 0, + int 3, + int 100, + int 80, + int 64, + int 100 }, + int 3000, + int 128, + int 512, + int 1024, + uint 0, + %struct.timer_list zeroinitializer, + %struct.timer_list zeroinitializer, + %struct.sk_buff_head zeroinitializer, + int 0, + %typedef.rwlock_t zeroinitializer, + uint 0, + %struct.neigh_parms* null, + %struct.kmem_cache_s* null, + %struct.tasklet_struct zeroinitializer, + %struct.nda_cacheinfo zeroinitializer, + [32 x %struct.neighbour*] zeroinitializer, + [16 x %struct.pneigh_entry*] zeroinitializer } ; <%struct.neigh_table*> [#uses=1] + %.str_1 = internal global [10 x sbyte] c"arp_cache\00" ; <[10 x sbyte]*> [#uses=1] + + implementation ; Functions: + + declare int %sock_no_connect(%struct.socket*, %struct.sockaddr*, int, int) + + declare int %sock_no_socketpair(%struct.socket*, %struct.socket*) + + declare int %sock_no_accept(%struct.socket*, %struct.socket*, int) + + declare int %sock_no_ioctl(%struct.socket*, uint, uint) + + declare int %sock_no_listen(%struct.socket*, int) + + declare int %sock_no_shutdown(%struct.socket*, int) + + declare int %sock_no_setsockopt(%struct.socket*, int, int, sbyte*, int) + + declare int %sock_no_getsockopt(%struct.socket*, int, int, sbyte*, int*) + + declare int %sock_no_mmap(%struct.file*, %struct.socket*, %struct.vm_area_struct*) + + declare int %sock_no_sendpage(%struct.socket*, %struct.page*, int, uint, int) + + declare uint %datagram_poll(%struct.file*, %struct.socket*, %struct.poll_table_struct*) + + declare int %proc_dointvec(%struct.ctl_table*, int, %struct.file*, sbyte*, uint*) + + declare int %proc_dointvec_jiffies(%struct.ctl_table*, int, %struct.file*, sbyte*, uint*) + + declare int %dev_queue_xmit(%struct.sk_buff*) + + declare int %dst_dev_event(%struct.notifier_block*, uint, sbyte*) + + declare int %neigh_compat_output(%struct.sk_buff*) + + declare int %rtnetlink_event(%struct.notifier_block*, uint, sbyte*) + + declare int %noop_enqueue(%struct.sk_buff*, %struct.Qdisc*) + + declare %struct.sk_buff* %noop_dequeue(%struct.Qdisc*) + + declare int %noop_requeue(%struct.sk_buff*, %struct.Qdisc*) + + declare int %netlink_create(%struct.socket*, int) + + declare int %netlink_release(%struct.socket*) + + declare int %netlink_bind(%struct.socket*, %struct.sockaddr*, int) + + declare int %netlink_connect(%struct.socket*, %struct.sockaddr*, int, int) + + declare int %netlink_getname(%struct.socket*, %struct.sockaddr*, int*, int) + + declare int %netlink_sendmsg(%struct.socket*, %struct.msghdr*, int, %struct.scm_cookie*) + + declare int %netlink_recvmsg(%struct.socket*, %struct.msghdr*, int, int, %struct.scm_cookie*) + + declare int %rt_garbage_collect() + + declare %struct.dst_entry* %ipv4_dst_check(%struct.dst_entry*, uint) + + declare %struct.dst_entry* %ipv4_dst_reroute(%struct.dst_entry*, %struct.sk_buff*) + + declare void %ipv4_dst_destroy(%struct.dst_entry*) + + declare %struct.dst_entry* %ipv4_negative_advice(%struct.dst_entry*) + + declare void %ipv4_link_failure(%struct.sk_buff*) + + declare void %rt_check_expire__thr(uint) + + declare void %rt_run_flush__thr(uint) + + declare int %ipv4_sysctl_rtcache_flush(%struct.ctl_table*, int, %struct.file*, sbyte*, uint*) + + declare int %ipv4_sysctl_rtcache_flush_strategy(%struct.ctl_table*, int*, int, sbyte*, uint*, sbyte*, uint, sbyte**) + + declare int %sysctl_jiffies(%struct.ctl_table*, int*, int, sbyte*, uint*, sbyte*, uint, sbyte**) + + declare int %tcp_v4_rcv(%struct.sk_buff*) + + declare void %tcp_v4_err(%struct.sk_buff*, uint) + + declare int %udp_rcv(%struct.sk_buff*) + + declare void %udp_err(%struct.sk_buff*, uint) + + declare int %icmp_rcv(%struct.sk_buff*) + + declare int %ip_queue_xmit(%struct.sk_buff*) + + declare int %ip_setsockopt(%struct.sock*, int, int, sbyte*, int) + + declare int %ip_getsockopt(%struct.sock*, int, int, sbyte*, int*) + + declare uint %tcp_poll(%struct.file*, %struct.socket*, %struct.poll_table_struct*) + + declare int %tcp_ioctl(%struct.sock*, int, uint) + + declare int %tcp_disconnect(%struct.sock*, int) + + declare int %tcp_sendpage(%struct.socket*, %struct.page*, int, uint, int) + + declare int %tcp_sendmsg(%struct.sock*, %struct.msghdr*, int) + + declare int %tcp_recvmsg(%struct.sock*, %struct.msghdr*, int, int, int, int*) + + declare void %tcp_shutdown(%struct.sock*, int) + + declare void %tcp_close(%struct.sock*, int) + + declare %struct.sock* %tcp_accept(%struct.sock*, int, int*) + + declare int %tcp_setsockopt(%struct.sock*, int, int, sbyte*, int) + + declare int %tcp_getsockopt(%struct.sock*, int, int, sbyte*, int*) + + declare int %tcp_v4_get_port(%struct.sock*, ushort) + + declare void %tcp_v4_hash(%struct.sock*) + + declare void %tcp_unhash(%struct.sock*) + + declare int %tcp_v4_connect(%struct.sock*, %struct.sockaddr*, int) + + declare void %tcp_v4_send_check(%struct.sock*, %struct.tcphdr*, int, %struct.sk_buff*) + + declare void %tcp_v4_send_reset(%struct.sk_buff*) + + declare void %tcp_v4_or_send_ack(%struct.sk_buff*, %struct.open_request*) + + declare int %tcp_v4_send_synack(%struct.sock*, %struct.open_request*, %struct.dst_entry*) + + declare void %tcp_v4_or_free(%struct.open_request*) + + declare int %tcp_v4_conn_request(%struct.sock*, %struct.sk_buff*) + + declare %struct.sock* %tcp_v4_syn_recv_sock(%struct.sock*, %struct.sk_buff*, %struct.open_request*, %struct.dst_entry*) + + declare int %tcp_v4_do_rcv(%struct.sock*, %struct.sk_buff*) + + declare int %tcp_v4_rebuild_header(%struct.sock*) + + declare void %v4_addr2sockaddr(%struct.sock*, %struct.sockaddr*) + + declare int %tcp_v4_remember_stamp(%struct.sock*) + + declare int %tcp_v4_init_sock(%struct.sock*) + + declare int %tcp_v4_destroy_sock(%struct.sock*) + + declare void %tcp_twkill__thr(uint) + + declare void %tcp_twcal_tick__thr(uint) + + declare void %raw_v4_hash(%struct.sock*) + + declare void %raw_v4_unhash(%struct.sock*) + + declare int %raw_rcv_skb(%struct.sock*, %struct.sk_buff*) + + declare int %raw_sendmsg(%struct.sock*, %struct.msghdr*, int) + + declare void %raw_close(%struct.sock*, int) + + declare int %raw_bind(%struct.sock*, %struct.sockaddr*, int) + + declare int %raw_recvmsg(%struct.sock*, %struct.msghdr*, int, int, int, int*) + + declare int %raw_init(%struct.sock*) + + declare int %raw_setsockopt(%struct.sock*, int, int, sbyte*, int) + + declare int %raw_getsockopt(%struct.sock*, int, int, sbyte*, int*) + + declare int %raw_ioctl(%struct.sock*, int, uint) + + declare int %udp_connect(%struct.sock*, %struct.sockaddr*, int) + + declare int %udp_disconnect(%struct.sock*, int) + + declare int %udp_v4_get_port(%struct.sock*, ushort) + + declare void %udp_v4_hash(%struct.sock*) + + declare void %udp_v4_unhash(%struct.sock*) + + declare int %udp_sendmsg(%struct.sock*, %struct.msghdr*, int) + + declare int %udp_ioctl(%struct.sock*, int, uint) + + declare int %udp_recvmsg(%struct.sock*, %struct.msghdr*, int, int, int, int*) + + declare void %udp_close(%struct.sock*, int) + + declare int %udp_queue_rcv_skb(%struct.sock*, %struct.sk_buff*) + + declare void %arp_solicit(%struct.neighbour*, %struct.sk_buff*) + + declare void %arp_error_report(%struct.neighbour*, %struct.sk_buff*) + + declare uint %arp_hash(sbyte*, %struct.net_device*) + + declare int %arp_constructor(%struct.neighbour*) + + declare void %parp_redo(%struct.sk_buff*) + + declare int %inetdev_event(%struct.notifier_block*, uint, sbyte*) + + declare int %inet_setsockopt(%struct.socket*, int, int, sbyte*, int) + + declare int %inet_getsockopt(%struct.socket*, int, int, sbyte*, int*) + + declare int %inet_listen(%struct.socket*, int) + + declare int %inet_create(%struct.socket*, int) + + declare int %inet_release(%struct.socket*) + + declare int %inet_bind(%struct.socket*, %struct.sockaddr*, int) + + declare int %inet_dgram_connect(%struct.socket*, %struct.sockaddr*, int, int) + + declare int %inet_stream_connect(%struct.socket*, %struct.sockaddr*, int, int) + + declare int %inet_accept(%struct.socket*, %struct.socket*, int) + + declare int %inet_getname(%struct.socket*, %struct.sockaddr*, int*, int) + + declare int %inet_recvmsg(%struct.socket*, %struct.msghdr*, int, int, %struct.scm_cookie*) + + declare int %inet_sendmsg(%struct.socket*, %struct.msghdr*, int, %struct.scm_cookie*) + + declare int %inet_shutdown(%struct.socket*, int) + + declare int %inet_ioctl(%struct.socket*, uint, uint) + + declare int %ipv4_sysctl_forward(%struct.ctl_table*, int, %struct.file*, sbyte*, uint*) + + declare int %ipv4_sysctl_forward_strategy(%struct.ctl_table*, int*, int, sbyte*, uint*, sbyte*, uint, sbyte**) + + declare int %proc_dointvec_minmax(%struct.ctl_table*, int, %struct.file*, sbyte*, uint*) + + declare int %sysctl_intvec(%struct.ctl_table*, int*, int, sbyte*, uint*, sbyte*, uint, sbyte**) + + void %get_current657() { + entry: + unreachable + } + + declare int %fib_inetaddr_event(%struct.notifier_block*, uint, sbyte*) + + declare int %fib_netdev_event(%struct.notifier_block*, uint, sbyte*) + + declare int %unix_listen(%struct.socket*, int) + + declare int %unix_create(%struct.socket*, int) + + declare int %unix_release(%struct.socket*) + + declare int %unix_bind(%struct.socket*, %struct.sockaddr*, int) + + declare int %unix_dgram_connect(%struct.socket*, %struct.sockaddr*, int, int) + + declare int %unix_stream_connect(%struct.socket*, %struct.sockaddr*, int, int) + + declare int %unix_socketpair(%struct.socket*, %struct.socket*) + + declare int %unix_accept(%struct.socket*, %struct.socket*, int) + + declare int %unix_getname(%struct.socket*, %struct.sockaddr*, int*, int) + + declare int %unix_dgram_sendmsg(%struct.socket*, %struct.msghdr*, int, %struct.scm_cookie*) + + declare int %unix_stream_sendmsg(%struct.socket*, %struct.msghdr*, int, %struct.scm_cookie*) + + declare int %unix_dgram_recvmsg(%struct.socket*, %struct.msghdr*, int, int, %struct.scm_cookie*) + + declare int %unix_stream_recvmsg(%struct.socket*, %struct.msghdr*, int, int, %struct.scm_cookie*) + + declare int %unix_shutdown(%struct.socket*, int) + + declare int %unix_ioctl(%struct.socket*, uint, uint) + + declare uint %unix_poll(%struct.file*, %struct.socket*, %struct.poll_table_struct*) + + declare int %packet_sendmsg_spkt(%struct.socket*, %struct.msghdr*, int, %struct.scm_cookie*) + + declare int %packet_sendmsg(%struct.socket*, %struct.msghdr*, int, %struct.scm_cookie*) + + declare int %packet_release(%struct.socket*) + + declare int %packet_bind_spkt(%struct.socket*, %struct.sockaddr*, int) + + declare int %packet_bind(%struct.socket*, %struct.sockaddr*, int) + + declare int %packet_recvmsg(%struct.socket*, %struct.msghdr*, int, int, %struct.scm_cookie*) + + declare int %packet_getname_spkt(%struct.socket*, %struct.sockaddr*, int*, int) + + declare int %packet_getname(%struct.socket*, %struct.sockaddr*, int*, int) + + declare int %packet_setsockopt(%struct.socket*, int, int, sbyte*, int) + + declare int %packet_getsockopt(%struct.socket*, int, int, sbyte*, int*) + + declare int %packet_ioctl(%struct.socket*, uint, uint) From reid at x10sys.com Thu Apr 13 15:34:12 2006 From: reid at x10sys.com (Reid Spencer) Date: Thu, 13 Apr 2006 15:34:12 -0500 Subject: [llvm-commits] CVS: llvm/test/Makefile Message-ID: <200604132034.PAA05463@zion.cs.uiuc.edu> Changes in directory llvm/test: Makefile updated: 1.86 -> 1.87 --- Log message: Use quotes properly so that the possibility of a null variable set is eliminated. This can happen, for example, if LLVM is configured without llvm-gcc in which case things like LLVMGCC_VERSION will be empty. In such cases, deja-gnu fails with: can't read "llvmgcc_version": no such variable because it sees: set llvmgcc_version instead of: set llvmgcc_version "" --- Diffs of the changes: (+4 -4) Makefile | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) Index: llvm/test/Makefile diff -u llvm/test/Makefile:1.86 llvm/test/Makefile:1.87 --- llvm/test/Makefile:1.86 Wed Apr 12 13:08:25 2006 +++ llvm/test/Makefile Thu Apr 13 15:33:59 2006 @@ -40,11 +40,11 @@ @echo '## these variables are automatically generated by make ##' >site.tmp @echo '# Do not edit here. If you wish to override these values' >>site.tmp @echo '# edit the last section' >>site.tmp - @echo "set target_triplet $(TARGET_TRIPLE)" >> site.tmp - @echo "set llvmgcc_version $(LLVMGCC_VERSION)" >> site.tmp + @echo 'set target_triplet "$(TARGET_TRIPLE)"' >> site.tmp + @echo 'set llvmgcc_version "$(LLVMGCC_VERSION)"' >> site.tmp @echo 'set prcontext "$(TCLSH) $(LLVM_SRC_ROOT)/test/Scripts/prcontext.tcl"' >> site.tmp - @echo 'set srcdir $(LLVM_SRC_ROOT)/test' >>site.tmp - @echo "set objdir $(LLVM_OBJ_ROOT)/test" >>site.tmp + @echo 'set srcdir "$(LLVM_SRC_ROOT)/test"' >>site.tmp + @echo 'set objdir "$(LLVM_OBJ_ROOT)/test"' >>site.tmp @echo 'set llvmgcc "PATH=\"$(LLVMToolDir):$(PATH)\" \"$(LLVMGCC)\""' >> site.tmp @echo 'set llvmgxx "PATH=\"$(LLVMToolDir):$(PATH)\" \"$(LLVMGCC)\""' >> site.tmp @echo 'set llvmgccmajvers "$(LLVMGCC_MAJVERS)"' >> site.tmp From reid at x10sys.com Thu Apr 13 16:18:03 2006 From: reid at x10sys.com (Reid Spencer) Date: Thu, 13 Apr 2006 16:18:03 -0500 Subject: [llvm-commits] [release_17] CVS: llvm/test/Makefile Message-ID: <200604132118.QAA02085@zion.cs.uiuc.edu> Changes in directory llvm/test: Makefile updated: 1.86 -> 1.86.2.1 --- Log message: Merge head changes needed for release (correction of dg variable quoting) --- Diffs of the changes: (+4 -4) Makefile | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) Index: llvm/test/Makefile diff -u llvm/test/Makefile:1.86 llvm/test/Makefile:1.86.2.1 --- llvm/test/Makefile:1.86 Wed Apr 12 13:08:25 2006 +++ llvm/test/Makefile Thu Apr 13 16:17:40 2006 @@ -40,11 +40,11 @@ @echo '## these variables are automatically generated by make ##' >site.tmp @echo '# Do not edit here. If you wish to override these values' >>site.tmp @echo '# edit the last section' >>site.tmp - @echo "set target_triplet $(TARGET_TRIPLE)" >> site.tmp - @echo "set llvmgcc_version $(LLVMGCC_VERSION)" >> site.tmp + @echo 'set target_triplet "$(TARGET_TRIPLE)"' >> site.tmp + @echo 'set llvmgcc_version "$(LLVMGCC_VERSION)"' >> site.tmp @echo 'set prcontext "$(TCLSH) $(LLVM_SRC_ROOT)/test/Scripts/prcontext.tcl"' >> site.tmp - @echo 'set srcdir $(LLVM_SRC_ROOT)/test' >>site.tmp - @echo "set objdir $(LLVM_OBJ_ROOT)/test" >>site.tmp + @echo 'set srcdir "$(LLVM_SRC_ROOT)/test"' >>site.tmp + @echo 'set objdir "$(LLVM_OBJ_ROOT)/test"' >>site.tmp @echo 'set llvmgcc "PATH=\"$(LLVMToolDir):$(PATH)\" \"$(LLVMGCC)\""' >> site.tmp @echo 'set llvmgxx "PATH=\"$(LLVMToolDir):$(PATH)\" \"$(LLVMGCC)\""' >> site.tmp @echo 'set llvmgccmajvers "$(LLVMGCC_MAJVERS)"' >> site.tmp From lattner at cs.uiuc.edu Thu Apr 13 16:19:25 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 13 Apr 2006 16:19:25 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CFrontend/2005-12-04-DeclarationLineNumbers.c Message-ID: <200604132119.QAA02128@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CFrontend: 2005-12-04-DeclarationLineNumbers.c updated: 1.2 -> 1.3 --- Log message: My addition of the xfail marker threw off the line #. move it. --- Diffs of the changes: (+3 -1) 2005-12-04-DeclarationLineNumbers.c | 4 +++- 1 files changed, 3 insertions(+), 1 deletion(-) Index: llvm/test/Regression/CFrontend/2005-12-04-DeclarationLineNumbers.c diff -u llvm/test/Regression/CFrontend/2005-12-04-DeclarationLineNumbers.c:1.2 llvm/test/Regression/CFrontend/2005-12-04-DeclarationLineNumbers.c:1.3 --- llvm/test/Regression/CFrontend/2005-12-04-DeclarationLineNumbers.c:1.2 Thu Apr 13 12:35:36 2006 +++ llvm/test/Regression/CFrontend/2005-12-04-DeclarationLineNumbers.c Thu Apr 13 16:19:13 2006 @@ -1,7 +1,6 @@ // RUN: %llvmgcc %s -S -g -o - | grep 'llvm.dbg.stoppoint.*uint 14' // PR664: ensure that line #'s are emitted for declarations -// XFAIL: llvmgcc4 short test(short br_data_0, short br_data_1, @@ -21,3 +20,6 @@ return s0734 + s1625; } + +// FIXME: PR735 +// XFAIL: llvmgcc4 From reid at x10sys.com Thu Apr 13 16:46:53 2006 From: reid at x10sys.com (Reid Spencer) Date: Thu, 13 Apr 2006 16:46:53 -0500 Subject: [llvm-commits] [release_17] CVS: llvm/examples/BFtoLLVM/Makefile Message-ID: <200604132146.QAA02252@zion.cs.uiuc.edu> Changes in directory llvm/examples/BFtoLLVM: Makefile updated: 1.2 -> 1.2.10.1 --- Log message: Make sure we distribute the "tests" directory too. --- Diffs of the changes: (+1 -0) Makefile | 1 + 1 files changed, 1 insertion(+) Index: llvm/examples/BFtoLLVM/Makefile diff -u llvm/examples/BFtoLLVM/Makefile:1.2 llvm/examples/BFtoLLVM/Makefile:1.2.10.1 --- llvm/examples/BFtoLLVM/Makefile:1.2 Thu Nov 18 04:03:47 2004 +++ llvm/examples/BFtoLLVM/Makefile Thu Apr 13 16:46:41 2006 @@ -10,4 +10,5 @@ LEVEL = ../.. TOOLNAME = BFtoLLVM EXAMPLE_TOOL = 1 +EXTRA_DIST = tests include $(LEVEL)/Makefile.common From llvm at cs.uiuc.edu Thu Apr 13 16:57:20 2006 From: llvm at cs.uiuc.edu (LLVM) Date: Thu, 13 Apr 2006 16:57:20 -0500 Subject: [llvm-commits] [release_17] CVS: llvm/lib/Target/Skeleton/.cvsignore Message-ID: <200604132157.QAA02302@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Skeleton: .cvsignore (r1.1) removed --- Log message: Remove the .cvsignore file so the SparcV8 directory gets pruned with the "cvs update -P" option. --- Diffs of the changes: (+0 -0) 0 files changed From llvm at cs.uiuc.edu Thu Apr 13 16:58:06 2006 From: llvm at cs.uiuc.edu (LLVM) Date: Thu, 13 Apr 2006 16:58:06 -0500 Subject: [llvm-commits] [release_17] CVS: llvm/lib/Target/SparcV8/.cvsignore Message-ID: <200604132158.QAA02320@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/SparcV8: .cvsignore (r1.1) removed --- Log message: Remove the .cvsignore file so this directory gets pruned. --- Diffs of the changes: (+0 -0) 0 files changed From llvm at cs.uiuc.edu Thu Apr 13 16:59:15 2006 From: llvm at cs.uiuc.edu (LLVM) Date: Thu, 13 Apr 2006 16:59:15 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Skeleton/.cvsignore Message-ID: <200604132159.QAA02336@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Skeleton: .cvsignore (r1.1) removed --- Log message: Remove .cvsignore so that this directory can be pruned. --- Diffs of the changes: (+0 -0) 0 files changed From llvm at cs.uiuc.edu Thu Apr 13 17:00:22 2006 From: llvm at cs.uiuc.edu (LLVM) Date: Thu, 13 Apr 2006 17:00:22 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/SparcV8/.cvsignore Message-ID: <200604132200.RAA02425@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/SparcV8: .cvsignore (r1.1) removed --- Log message: Remove the .cvsignore file so this directory can be pruned. --- Diffs of the changes: (+0 -0) 0 files changed From evan.cheng at apple.com Thu Apr 13 19:14:18 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 13 Apr 2006 19:14:18 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/IntrinsicsX86.td Message-ID: <200604140014.TAA10974@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm: IntrinsicsX86.td updated: 1.25 -> 1.26 --- Log message: psll*, psrl*, and psra* intrinsics. --- Diffs of the changes: (+24 -0) IntrinsicsX86.td | 24 ++++++++++++++++++++++++ 1 files changed, 24 insertions(+) Index: llvm/include/llvm/IntrinsicsX86.td diff -u llvm/include/llvm/IntrinsicsX86.td:1.25 llvm/include/llvm/IntrinsicsX86.td:1.26 --- llvm/include/llvm/IntrinsicsX86.td:1.25 Thu Apr 13 01:09:41 2006 +++ llvm/include/llvm/IntrinsicsX86.td Thu Apr 13 19:14:05 2006 @@ -313,12 +313,36 @@ // Integer shift ops. let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". + def int_x86_sse2_psll_w : + Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, + llvm_v4i32_ty], [IntrNoMem]>; + def int_x86_sse2_psll_d : + Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, + llvm_v4i32_ty], [IntrNoMem]>; + def int_x86_sse2_psll_q : + Intrinsic<[llvm_v2i64_ty, llvm_v2i64_ty, + llvm_v4i32_ty], [IntrNoMem]>; def int_x86_sse2_psll_dq : GCCBuiltin<"__builtin_ia32_pslldqi128">, Intrinsic<[llvm_v2i64_ty, llvm_v2i64_ty, llvm_int_ty], [IntrNoMem]>; + def int_x86_sse2_psrl_w : + Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, + llvm_v4i32_ty], [IntrNoMem]>; + def int_x86_sse2_psrl_d : + Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, + llvm_v4i32_ty], [IntrNoMem]>; + def int_x86_sse2_psrl_q : + Intrinsic<[llvm_v2i64_ty, llvm_v2i64_ty, + llvm_v4i32_ty], [IntrNoMem]>; def int_x86_sse2_psrl_dq : GCCBuiltin<"__builtin_ia32_psrldqi128">, Intrinsic<[llvm_v2i64_ty, llvm_v2i64_ty, llvm_int_ty], [IntrNoMem]>; + def int_x86_sse2_psra_w : + Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, + llvm_v4i32_ty], [IntrNoMem]>; + def int_x86_sse2_psra_d : + Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, + llvm_v4i32_ty], [IntrNoMem]>; } // Conversion ops From evan.cheng at apple.com Thu Apr 13 19:14:18 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 13 Apr 2006 19:14:18 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td Message-ID: <200604140014.TAA10978@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrSSE.td updated: 1.86 -> 1.87 --- Log message: psll*, psrl*, and psra* intrinsics. --- Diffs of the changes: (+99 -1) X86InstrSSE.td | 100 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 files changed, 99 insertions(+), 1 deletion(-) Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.86 llvm/lib/Target/X86/X86InstrSSE.td:1.87 --- llvm/lib/Target/X86/X86InstrSSE.td:1.86 Thu Apr 13 13:11:28 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Thu Apr 13 19:14:05 2006 @@ -1522,10 +1522,108 @@ } let isTwoAddress = 1 in { +def PSLLWrr : PDIi8<0xF1, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), + "psllw {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_psll_w VR128:$src1, + VR128:$src2))]>; +def PSLLWrm : PDIi8<0xF1, MRMSrcReg, (ops VR128:$dst, VR128:$src1, i128mem:$src2), + "psllw {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_psll_w VR128:$src1, + (bc_v4i32 (loadv2i64 addr:$src2))))]>; +def PSLLWri : PDIi8<0x71, MRM6r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2), + "psllw {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_psll_w VR128:$src1, + (scalar_to_vector (i32 imm:$src2))))]>; +def PSLLDrr : PDIi8<0xF2, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), + "pslld {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_psll_d VR128:$src1, + VR128:$src2))]>; +def PSLLDrm : PDIi8<0xF2, MRMSrcReg, (ops VR128:$dst, VR128:$src1, i128mem:$src2), + "pslld {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_psll_d VR128:$src1, + (bc_v4i32 (loadv2i64 addr:$src2))))]>; +def PSLLDri : PDIi8<0x72, MRM6r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2), + "pslld {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_psll_d VR128:$src1, + (scalar_to_vector (i32 imm:$src2))))]>; +def PSLLQrr : PDIi8<0xF3, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), + "psllq {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_psll_q VR128:$src1, + VR128:$src2))]>; +def PSLLQrm : PDIi8<0xF3, MRMSrcReg, (ops VR128:$dst, VR128:$src1, i128mem:$src2), + "psllq {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_psll_q VR128:$src1, + (bc_v4i32 (loadv2i64 addr:$src2))))]>; +def PSLLQri : PDIi8<0x73, MRM6r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2), + "psllq {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_psll_q VR128:$src1, + (scalar_to_vector (i32 imm:$src2))))]>; def PSLLDQri : PDIi8<0x73, MRM7r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2), "pslldq {$src2, $dst|$dst, $src2}", []>; -def PSRLDQri : PDIi8<0x73, MRM7r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2), + +def PSRLWrr : PDIi8<0xD1, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), + "psrlw {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_psrl_w VR128:$src1, + VR128:$src2))]>; +def PSRLWrm : PDIi8<0xD1, MRMSrcReg, (ops VR128:$dst, VR128:$src1, i128mem:$src2), + "psrlw {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_psrl_w VR128:$src1, + (bc_v4i32 (loadv2i64 addr:$src2))))]>; +def PSRLWri : PDIi8<0x71, MRM2r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2), + "psrlw {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_psrl_w VR128:$src1, + (scalar_to_vector (i32 imm:$src2))))]>; +def PSRLDrr : PDIi8<0xD2, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), + "psrld {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_psrl_d VR128:$src1, + VR128:$src2))]>; +def PSRLDrm : PDIi8<0xD2, MRMSrcReg, (ops VR128:$dst, VR128:$src1, i128mem:$src2), + "psrld {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_psrl_d VR128:$src1, + (bc_v4i32 (loadv2i64 addr:$src2))))]>; +def PSRLDri : PDIi8<0x72, MRM2r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2), + "psrld {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_psrl_d VR128:$src1, + (scalar_to_vector (i32 imm:$src2))))]>; +def PSRLQrr : PDIi8<0xD3, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), + "psrlq {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_psrl_q VR128:$src1, + VR128:$src2))]>; +def PSRLQrm : PDIi8<0xD3, MRMSrcReg, (ops VR128:$dst, VR128:$src1, i128mem:$src2), + "psrlq {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_psrl_q VR128:$src1, + (bc_v4i32 (loadv2i64 addr:$src2))))]>; +def PSRLQri : PDIi8<0x73, MRM2r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2), + "psrlq {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_psrl_q VR128:$src1, + (scalar_to_vector (i32 imm:$src2))))]>; +def PSRLDQri : PDIi8<0x73, MRM3r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2), "psrldq {$src2, $dst|$dst, $src2}", []>; + +def PSRAWrr : PDIi8<0xE1, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), + "psraw {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_psra_w VR128:$src1, + VR128:$src2))]>; +def PSRAWrm : PDIi8<0xE1, MRMSrcReg, (ops VR128:$dst, VR128:$src1, i128mem:$src2), + "psraw {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_psra_w VR128:$src1, + (bc_v4i32 (loadv2i64 addr:$src2))))]>; +def PSRAWri : PDIi8<0x71, MRM4r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2), + "psraw {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_psra_w VR128:$src1, + (scalar_to_vector (i32 imm:$src2))))]>; +def PSRADrr : PDIi8<0xE2, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), + "psrad {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_psra_d VR128:$src1, + VR128:$src2))]>; +def PSRADrm : PDIi8<0xE2, MRMSrcReg, (ops VR128:$dst, VR128:$src1, i128mem:$src2), + "psrad {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_psra_d VR128:$src1, + (bc_v4i32 (loadv2i64 addr:$src2))))]>; +def PSRADri : PDIi8<0x72, MRM4r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2), + "psrad {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_psra_d VR128:$src1, + (scalar_to_vector (i32 imm:$src2))))]>; } // Logical From evan.cheng at apple.com Thu Apr 13 20:40:07 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 13 Apr 2006 20:40:07 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/IntrinsicsX86.td Message-ID: <200604140140.UAA22877@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm: IntrinsicsX86.td updated: 1.26 -> 1.27 --- Log message: pcmpeq* and pcmpgt* intrinsics. --- Diffs of the changes: (+22 -0) IntrinsicsX86.td | 22 ++++++++++++++++++++++ 1 files changed, 22 insertions(+) Index: llvm/include/llvm/IntrinsicsX86.td diff -u llvm/include/llvm/IntrinsicsX86.td:1.26 llvm/include/llvm/IntrinsicsX86.td:1.27 --- llvm/include/llvm/IntrinsicsX86.td:1.26 Thu Apr 13 19:14:05 2006 +++ llvm/include/llvm/IntrinsicsX86.td Thu Apr 13 20:39:53 2006 @@ -345,6 +345,28 @@ llvm_v4i32_ty], [IntrNoMem]>; } +// Integer comparison ops +let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". + def int_x86_sse2_pcmpeq_b : GCCBuiltin<"__builtin_ia32_pcmpeqb128">, + Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, + llvm_v16i8_ty], [IntrNoMem]>; + def int_x86_sse2_pcmpeq_w : GCCBuiltin<"__builtin_ia32_pcmpeqw128">, + Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, + llvm_v8i16_ty], [IntrNoMem]>; + def int_x86_sse2_pcmpeq_d : GCCBuiltin<"__builtin_ia32_pcmpeqd128">, + Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, + llvm_v4i32_ty], [IntrNoMem]>; + def int_x86_sse2_pcmpgt_b : GCCBuiltin<"__builtin_ia32_pcmpgtb128">, + Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, + llvm_v16i8_ty], [IntrNoMem]>; + def int_x86_sse2_pcmpgt_w : GCCBuiltin<"__builtin_ia32_pcmpgtw128">, + Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, + llvm_v8i16_ty], [IntrNoMem]>; + def int_x86_sse2_pcmpgt_d : GCCBuiltin<"__builtin_ia32_pcmpgtd128">, + Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, + llvm_v4i32_ty], [IntrNoMem]>; +} + // Conversion ops let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse2_cvtdq2pd : GCCBuiltin<"__builtin_ia32_cvtdq2pd">, From evan.cheng at apple.com Thu Apr 13 20:40:07 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 13 Apr 2006 20:40:07 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td Message-ID: <200604140140.UAA22879@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrSSE.td updated: 1.87 -> 1.88 --- Log message: pcmpeq* and pcmpgt* intrinsics. --- Diffs of the changes: (+68 -2) X86InstrSSE.td | 70 +++++++++++++++++++++++++++++++++++++++++++++++++++++++-- 1 files changed, 68 insertions(+), 2 deletions(-) Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.87 llvm/lib/Target/X86/X86InstrSSE.td:1.88 --- llvm/lib/Target/X86/X86InstrSSE.td:1.87 Thu Apr 13 19:14:05 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Thu Apr 13 20:39:53 2006 @@ -1148,10 +1148,76 @@ (load addr:$src), imm:$cc))]>; def CMPPDrr : PDIi8<0xC2, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc), - "cmp${cc}pd {$src, $dst|$dst, $src}", []>; + "cmp${cc}pd {$src, $dst|$dst, $src}", + [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1, + VR128:$src, imm:$cc))]>; def CMPPDrm : PDIi8<0xC2, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc), - "cmp${cc}pd {$src, $dst|$dst, $src}", []>; + "cmp${cc}pd {$src, $dst|$dst, $src}", + [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1, + (load addr:$src), imm:$cc))]>; + +def PCMPEQBrr : PDI<0x74, MRMSrcReg, + (ops VR128:$dst, VR128:$src1, VR128:$src2), + "pcmpeqb {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_pcmpeq_b VR128:$src1, + VR128:$src2))]>; +def PCMPEQBrm : PDI<0x74, MRMSrcReg, + (ops VR128:$dst, VR128:$src1, i128mem:$src2), + "pcmpeqb {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_pcmpeq_b VR128:$src1, + (bc_v16i8 (loadv2i64 addr:$src2))))]>; +def PCMPEQWrr : PDI<0x75, MRMSrcReg, + (ops VR128:$dst, VR128:$src1, VR128:$src2), + "pcmpeqw {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_pcmpeq_w VR128:$src1, + VR128:$src2))]>; +def PCMPEQWrm : PDI<0x75, MRMSrcReg, + (ops VR128:$dst, VR128:$src1, i128mem:$src2), + "pcmpeqw {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_pcmpeq_w VR128:$src1, + (bc_v8i16 (loadv2i64 addr:$src2))))]>; +def PCMPEQDrr : PDI<0x76, MRMSrcReg, + (ops VR128:$dst, VR128:$src1, VR128:$src2), + "pcmpeqd {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_pcmpeq_d VR128:$src1, + VR128:$src2))]>; +def PCMPEQDrm : PDI<0x76, MRMSrcReg, + (ops VR128:$dst, VR128:$src1, i128mem:$src2), + "pcmpeqd {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_pcmpeq_d VR128:$src1, + (bc_v4i32 (loadv2i64 addr:$src2))))]>; + +def PCMPGTBrr : PDI<0x64, MRMSrcReg, + (ops VR128:$dst, VR128:$src1, VR128:$src2), + "pcmpgtb {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_pcmpgt_b VR128:$src1, + VR128:$src2))]>; +def PCMPGTBrm : PDI<0x64, MRMSrcReg, + (ops VR128:$dst, VR128:$src1, i128mem:$src2), + "pcmpgtb {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_pcmpgt_b VR128:$src1, + (bc_v16i8 (loadv2i64 addr:$src2))))]>; +def PCMPGTWrr : PDI<0x65, MRMSrcReg, + (ops VR128:$dst, VR128:$src1, VR128:$src2), + "pcmpgtw {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_pcmpgt_w VR128:$src1, + VR128:$src2))]>; +def PCMPGTWrm : PDI<0x65, MRMSrcReg, + (ops VR128:$dst, VR128:$src1, i128mem:$src2), + "pcmpgtw {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_pcmpgt_w VR128:$src1, + (bc_v8i16 (loadv2i64 addr:$src2))))]>; +def PCMPGTDrr : PDI<0x66, MRMSrcReg, + (ops VR128:$dst, VR128:$src1, VR128:$src2), + "pcmpgtd {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_pcmpgt_d VR128:$src1, + VR128:$src2))]>; +def PCMPGTDrm : PDI<0x66, MRMSrcReg, + (ops VR128:$dst, VR128:$src1, i128mem:$src2), + "pcmpgtd {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_pcmpgt_d VR128:$src1, + (bc_v4i32 (loadv2i64 addr:$src2))))]>; } // Shuffle and unpack instructions From reid at x10sys.com Thu Apr 13 21:55:55 2006 From: reid at x10sys.com (Reid Spencer) Date: Thu, 13 Apr 2006 21:55:55 -0500 Subject: [llvm-commits] CVS: llvm/configure Message-ID: <200604140255.VAA28255@zion.cs.uiuc.edu> Changes in directory llvm: configure updated: 1.219 -> 1.220 --- Log message: remove the "cvs" part of the version number for the release branch. --- Diffs of the changes: (+9 -9) configure | 18 +++++++++--------- 1 files changed, 9 insertions(+), 9 deletions(-) Index: llvm/configure diff -u llvm/configure:1.219 llvm/configure:1.220 --- llvm/configure:1.219 Sun Apr 9 15:42:14 2006 +++ llvm/configure Thu Apr 13 21:55:43 2006 @@ -1,6 +1,6 @@ #! /bin/sh # Guess values for system-dependent variables and create Makefiles. -# Generated by GNU Autoconf 2.59 for llvm 1.7cvs. +# Generated by GNU Autoconf 2.59 for llvm 1.7. # # Report bugs to . # @@ -425,8 +425,8 @@ # Identity of this package. PACKAGE_NAME='llvm' PACKAGE_TARNAME='-llvm-' -PACKAGE_VERSION='1.7cvs' -PACKAGE_STRING='llvm 1.7cvs' +PACKAGE_VERSION='1.7' +PACKAGE_STRING='llvm 1.7' PACKAGE_BUGREPORT='llvmbugs at cs.uiuc.edu' ac_unique_file="lib/VMCore/Module.cpp" @@ -965,7 +965,7 @@ # Omit some internal or obsolete options to make the list less imposing. # This message is too long to be a string in the A/UX 3.1 sh. cat <<_ACEOF -\`configure' configures llvm 1.7cvs to adapt to many kinds of systems. +\`configure' configures llvm 1.7 to adapt to many kinds of systems. Usage: $0 [OPTION]... [VAR=VALUE]... @@ -1027,7 +1027,7 @@ if test -n "$ac_init_help"; then case $ac_init_help in - short | recursive ) echo "Configuration of llvm 1.7cvs:";; + short | recursive ) echo "Configuration of llvm 1.7:";; esac cat <<\_ACEOF @@ -1176,7 +1176,7 @@ test -n "$ac_init_help" && exit 0 if $ac_init_version; then cat <<\_ACEOF -llvm configure 1.7cvs +llvm configure 1.7 generated by GNU Autoconf 2.59 Copyright (C) 2003 Free Software Foundation, Inc. @@ -1192,7 +1192,7 @@ This file contains any messages produced by compilers while running configure, to aid debugging if configure makes a mistake. -It was created by llvm $as_me 1.7cvs, which was +It was created by llvm $as_me 1.7, which was generated by GNU Autoconf 2.59. Invocation command line was $ $0 $@ @@ -31240,7 +31240,7 @@ } >&5 cat >&5 <<_CSEOF -This file was extended by llvm $as_me 1.7cvs, which was +This file was extended by llvm $as_me 1.7, which was generated by GNU Autoconf 2.59. Invocation command line was CONFIG_FILES = $CONFIG_FILES @@ -31303,7 +31303,7 @@ cat >>$CONFIG_STATUS <<_ACEOF ac_cs_version="\\ -llvm config.status 1.7cvs +llvm config.status 1.7 configured by $0, generated by GNU Autoconf 2.59, with options \\"`echo "$ac_configure_args" | sed 's/[\\""\`\$]/\\\\&/g'`\\" From reid at x10sys.com Thu Apr 13 21:55:56 2006 From: reid at x10sys.com (Reid Spencer) Date: Thu, 13 Apr 2006 21:55:56 -0500 Subject: [llvm-commits] CVS: llvm/autoconf/configure.ac Message-ID: <200604140255.VAA28259@zion.cs.uiuc.edu> Changes in directory llvm/autoconf: configure.ac updated: 1.217 -> 1.218 --- Log message: remove the "cvs" part of the version number for the release branch. --- Diffs of the changes: (+1 -1) configure.ac | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/autoconf/configure.ac diff -u llvm/autoconf/configure.ac:1.217 llvm/autoconf/configure.ac:1.218 --- llvm/autoconf/configure.ac:1.217 Sun Apr 9 15:42:14 2006 +++ llvm/autoconf/configure.ac Thu Apr 13 21:55:43 2006 @@ -31,7 +31,7 @@ dnl===-----------------------------------------------------------------------=== dnl Initialize autoconf and define the package name, version number and dnl email address for reporting bugs. -AC_INIT([[llvm]],[[1.7cvs]],[llvmbugs at cs.uiuc.edu]) +AC_INIT([[llvm]],[[1.7]],[llvmbugs at cs.uiuc.edu]) dnl Provide a copyright substitution and ensure the copyright notice is included dnl in the output of --version option of the generated configure script. From reid at x10sys.com Thu Apr 13 22:01:41 2006 From: reid at x10sys.com (Reid Spencer) Date: Thu, 13 Apr 2006 22:01:41 -0500 Subject: [llvm-commits] CVS: llvm/autoconf/configure.ac Message-ID: <200604140301.WAA28789@zion.cs.uiuc.edu> Changes in directory llvm/autoconf: configure.ac updated: 1.218 -> 1.219 --- Log message: Ahem. HEAD -> 1.8cvs not 1.7 (I'm an idiot). --- Diffs of the changes: (+1 -1) configure.ac | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/autoconf/configure.ac diff -u llvm/autoconf/configure.ac:1.218 llvm/autoconf/configure.ac:1.219 --- llvm/autoconf/configure.ac:1.218 Thu Apr 13 21:55:43 2006 +++ llvm/autoconf/configure.ac Thu Apr 13 22:01:27 2006 @@ -31,7 +31,7 @@ dnl===-----------------------------------------------------------------------=== dnl Initialize autoconf and define the package name, version number and dnl email address for reporting bugs. -AC_INIT([[llvm]],[[1.7]],[llvmbugs at cs.uiuc.edu]) +AC_INIT([[llvm]],[[1.8cvs]],[llvmbugs at cs.uiuc.edu]) dnl Provide a copyright substitution and ensure the copyright notice is included dnl in the output of --version option of the generated configure script. From reid at x10sys.com Thu Apr 13 22:01:41 2006 From: reid at x10sys.com (Reid Spencer) Date: Thu, 13 Apr 2006 22:01:41 -0500 Subject: [llvm-commits] CVS: llvm/configure Message-ID: <200604140301.WAA28793@zion.cs.uiuc.edu> Changes in directory llvm: configure updated: 1.220 -> 1.221 --- Log message: Ahem. HEAD -> 1.8cvs not 1.7 (I'm an idiot). --- Diffs of the changes: (+9 -9) configure | 18 +++++++++--------- 1 files changed, 9 insertions(+), 9 deletions(-) Index: llvm/configure diff -u llvm/configure:1.220 llvm/configure:1.221 --- llvm/configure:1.220 Thu Apr 13 21:55:43 2006 +++ llvm/configure Thu Apr 13 22:01:27 2006 @@ -1,6 +1,6 @@ #! /bin/sh # Guess values for system-dependent variables and create Makefiles. -# Generated by GNU Autoconf 2.59 for llvm 1.7. +# Generated by GNU Autoconf 2.59 for llvm 1.8cvs. # # Report bugs to . # @@ -425,8 +425,8 @@ # Identity of this package. PACKAGE_NAME='llvm' PACKAGE_TARNAME='-llvm-' -PACKAGE_VERSION='1.7' -PACKAGE_STRING='llvm 1.7' +PACKAGE_VERSION='1.8cvs' +PACKAGE_STRING='llvm 1.8cvs' PACKAGE_BUGREPORT='llvmbugs at cs.uiuc.edu' ac_unique_file="lib/VMCore/Module.cpp" @@ -965,7 +965,7 @@ # Omit some internal or obsolete options to make the list less imposing. # This message is too long to be a string in the A/UX 3.1 sh. cat <<_ACEOF -\`configure' configures llvm 1.7 to adapt to many kinds of systems. +\`configure' configures llvm 1.8cvs to adapt to many kinds of systems. Usage: $0 [OPTION]... [VAR=VALUE]... @@ -1027,7 +1027,7 @@ if test -n "$ac_init_help"; then case $ac_init_help in - short | recursive ) echo "Configuration of llvm 1.7:";; + short | recursive ) echo "Configuration of llvm 1.8cvs:";; esac cat <<\_ACEOF @@ -1176,7 +1176,7 @@ test -n "$ac_init_help" && exit 0 if $ac_init_version; then cat <<\_ACEOF -llvm configure 1.7 +llvm configure 1.8cvs generated by GNU Autoconf 2.59 Copyright (C) 2003 Free Software Foundation, Inc. @@ -1192,7 +1192,7 @@ This file contains any messages produced by compilers while running configure, to aid debugging if configure makes a mistake. -It was created by llvm $as_me 1.7, which was +It was created by llvm $as_me 1.8cvs, which was generated by GNU Autoconf 2.59. Invocation command line was $ $0 $@ @@ -31240,7 +31240,7 @@ } >&5 cat >&5 <<_CSEOF -This file was extended by llvm $as_me 1.7, which was +This file was extended by llvm $as_me 1.8cvs, which was generated by GNU Autoconf 2.59. Invocation command line was CONFIG_FILES = $CONFIG_FILES @@ -31303,7 +31303,7 @@ cat >>$CONFIG_STATUS <<_ACEOF ac_cs_version="\\ -llvm config.status 1.7 +llvm config.status 1.8cvs configured by $0, generated by GNU Autoconf 2.59, with options \\"`echo "$ac_configure_args" | sed 's/[\\""\`\$]/\\\\&/g'`\\" From reid at x10sys.com Thu Apr 13 22:03:33 2006 From: reid at x10sys.com (Reid Spencer) Date: Thu, 13 Apr 2006 22:03:33 -0500 Subject: [llvm-commits] [release_17] CVS: llvm/configure Message-ID: <200604140303.WAA28973@zion.cs.uiuc.edu> Changes in directory llvm: configure updated: 1.219 -> 1.219.2.1 --- Log message: Remove "cvs" suffix from 1.7 version number, on the release_17 branch. --- Diffs of the changes: (+9 -9) configure | 18 +++++++++--------- 1 files changed, 9 insertions(+), 9 deletions(-) Index: llvm/configure diff -u llvm/configure:1.219 llvm/configure:1.219.2.1 --- llvm/configure:1.219 Sun Apr 9 15:42:14 2006 +++ llvm/configure Thu Apr 13 22:03:21 2006 @@ -1,6 +1,6 @@ #! /bin/sh # Guess values for system-dependent variables and create Makefiles. -# Generated by GNU Autoconf 2.59 for llvm 1.7cvs. +# Generated by GNU Autoconf 2.59 for llvm 1.7. # # Report bugs to . # @@ -425,8 +425,8 @@ # Identity of this package. PACKAGE_NAME='llvm' PACKAGE_TARNAME='-llvm-' -PACKAGE_VERSION='1.7cvs' -PACKAGE_STRING='llvm 1.7cvs' +PACKAGE_VERSION='1.7' +PACKAGE_STRING='llvm 1.7' PACKAGE_BUGREPORT='llvmbugs at cs.uiuc.edu' ac_unique_file="lib/VMCore/Module.cpp" @@ -965,7 +965,7 @@ # Omit some internal or obsolete options to make the list less imposing. # This message is too long to be a string in the A/UX 3.1 sh. cat <<_ACEOF -\`configure' configures llvm 1.7cvs to adapt to many kinds of systems. +\`configure' configures llvm 1.7 to adapt to many kinds of systems. Usage: $0 [OPTION]... [VAR=VALUE]... @@ -1027,7 +1027,7 @@ if test -n "$ac_init_help"; then case $ac_init_help in - short | recursive ) echo "Configuration of llvm 1.7cvs:";; + short | recursive ) echo "Configuration of llvm 1.7:";; esac cat <<\_ACEOF @@ -1176,7 +1176,7 @@ test -n "$ac_init_help" && exit 0 if $ac_init_version; then cat <<\_ACEOF -llvm configure 1.7cvs +llvm configure 1.7 generated by GNU Autoconf 2.59 Copyright (C) 2003 Free Software Foundation, Inc. @@ -1192,7 +1192,7 @@ This file contains any messages produced by compilers while running configure, to aid debugging if configure makes a mistake. -It was created by llvm $as_me 1.7cvs, which was +It was created by llvm $as_me 1.7, which was generated by GNU Autoconf 2.59. Invocation command line was $ $0 $@ @@ -31240,7 +31240,7 @@ } >&5 cat >&5 <<_CSEOF -This file was extended by llvm $as_me 1.7cvs, which was +This file was extended by llvm $as_me 1.7, which was generated by GNU Autoconf 2.59. Invocation command line was CONFIG_FILES = $CONFIG_FILES @@ -31303,7 +31303,7 @@ cat >>$CONFIG_STATUS <<_ACEOF ac_cs_version="\\ -llvm config.status 1.7cvs +llvm config.status 1.7 configured by $0, generated by GNU Autoconf 2.59, with options \\"`echo "$ac_configure_args" | sed 's/[\\""\`\$]/\\\\&/g'`\\" From reid at x10sys.com Thu Apr 13 22:03:33 2006 From: reid at x10sys.com (Reid Spencer) Date: Thu, 13 Apr 2006 22:03:33 -0500 Subject: [llvm-commits] [release_17] CVS: llvm/autoconf/configure.ac Message-ID: <200604140303.WAA28977@zion.cs.uiuc.edu> Changes in directory llvm/autoconf: configure.ac updated: 1.217 -> 1.217.2.1 --- Log message: Remove "cvs" suffix from 1.7 version number, on the release_17 branch. --- Diffs of the changes: (+1 -1) configure.ac | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/autoconf/configure.ac diff -u llvm/autoconf/configure.ac:1.217 llvm/autoconf/configure.ac:1.217.2.1 --- llvm/autoconf/configure.ac:1.217 Sun Apr 9 15:42:14 2006 +++ llvm/autoconf/configure.ac Thu Apr 13 22:03:21 2006 @@ -31,7 +31,7 @@ dnl===-----------------------------------------------------------------------=== dnl Initialize autoconf and define the package name, version number and dnl email address for reporting bugs. -AC_INIT([[llvm]],[[1.7cvs]],[llvmbugs at cs.uiuc.edu]) +AC_INIT([[llvm]],[[1.7]],[llvmbugs at cs.uiuc.edu]) dnl Provide a copyright substitution and ensure the copyright notice is included dnl in the output of --version option of the generated configure script. From lattner at cs.uiuc.edu Thu Apr 13 23:47:38 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 13 Apr 2006 23:47:38 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CFrontend/2004-02-20-StaticRedeclare.c.tr Message-ID: <200604140447.XAA05523@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CFrontend: 2004-02-20-StaticRedeclare.c.tr (r1.4) removed --- Log message: Remove this test, there is no need to test GCC's bugs --- Diffs of the changes: (+0 -0) 0 files changed From lattner at cs.uiuc.edu Fri Apr 14 00:10:05 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 14 Apr 2006 00:10:05 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/GCSE/vectorops.ll Message-ID: <200604140510.AAA14160@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/GCSE: vectorops.ll added (r1.1) --- Log message: new testcase, vector operations should be CSE'd --- Diffs of the changes: (+26 -0) vectorops.ll | 26 ++++++++++++++++++++++++++ 1 files changed, 26 insertions(+) Index: llvm/test/Regression/Transforms/GCSE/vectorops.ll diff -c /dev/null llvm/test/Regression/Transforms/GCSE/vectorops.ll:1.1 *** /dev/null Fri Apr 14 00:10:03 2006 --- llvm/test/Regression/Transforms/GCSE/vectorops.ll Fri Apr 14 00:09:53 2006 *************** *** 0 **** --- 1,26 ---- + ; RUN: llvm-as < %s | opt -gcse -instcombine -disable-output && + ; RUN: llvm-as < %s | opt -gcse -instcombine | llvm-dis | not grep sub + + uint %test_extractelement(<4 x uint> %V) { + %R = extractelement <4 x uint> %V, uint 1 + %R2 = extractelement <4 x uint> %V, uint 1 + %V = sub uint %R, %R2 + ret uint %V + } + + <4 x uint> %test_insertelement(<4 x uint> %V) { + %R = insertelement <4 x uint> %V, uint 0, uint 0 + %R2 = insertelement <4 x uint> %V, uint 0, uint 0 + %x = sub <4 x uint> %R, %R2 + ret <4 x uint> %x + } + + <4 x uint> %test_shufflevector(<4 x uint> %V) { + %R = shufflevector <4 x uint> %V, <4 x uint> %V, + <4 x uint> < uint 1, uint undef, uint 7, uint 2> + %R2 = shufflevector <4 x uint> %V, <4 x uint> %V, + <4 x uint> < uint 1, uint undef, uint 7, uint 2> + %x = sub <4 x uint> %R, %R2 + ret <4 x uint> %x + } + From lattner at cs.uiuc.edu Fri Apr 14 00:10:32 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 14 Apr 2006 00:10:32 -0500 Subject: [llvm-commits] CVS: llvm/lib/Analysis/ValueNumbering.cpp Message-ID: <200604140510.AAA14196@zion.cs.uiuc.edu> Changes in directory llvm/lib/Analysis: ValueNumbering.cpp updated: 1.16 -> 1.17 --- Log message: Implement value #'ing for vector operations, implementing Regression/Transforms/GCSE/vectorops.ll --- Diffs of the changes: (+38 -32) ValueNumbering.cpp | 70 ++++++++++++++++++++++++++++------------------------- 1 files changed, 38 insertions(+), 32 deletions(-) Index: llvm/lib/Analysis/ValueNumbering.cpp diff -u llvm/lib/Analysis/ValueNumbering.cpp:1.16 llvm/lib/Analysis/ValueNumbering.cpp:1.17 --- llvm/lib/Analysis/ValueNumbering.cpp:1.16 Sat Feb 4 03:15:29 2006 +++ llvm/lib/Analysis/ValueNumbering.cpp Fri Apr 14 00:10:20 2006 @@ -73,14 +73,18 @@ std::vector &RetVals; BVNImpl(std::vector &RV) : RetVals(RV) {} - void handleBinaryInst(Instruction &I); - void visitBinaryOperator(BinaryOperator &I) { - handleBinaryInst((Instruction&)I); - } - void visitGetElementPtrInst(GetElementPtrInst &I); void visitCastInst(CastInst &I); - void visitShiftInst(ShiftInst &I) { handleBinaryInst((Instruction&)I); } - void visitSelectInst(SelectInst &I); + void visitGetElementPtrInst(GetElementPtrInst &I); + + void handleBinaryInst(Instruction &I); + void visitBinaryOperator(Instruction &I) { handleBinaryInst(I); } + void visitShiftInst(Instruction &I) { handleBinaryInst(I); } + void visitExtractElementInst(Instruction &I) { handleBinaryInst(I); } + + void handleTernaryInst(Instruction &I); + void visitSelectInst(Instruction &I) { handleTernaryInst(I); } + void visitInsertElementInst(Instruction &I) { handleTernaryInst(I); } + void visitShuffleVectorInst(Instruction &I) { handleTernaryInst(I); } void visitInstruction(Instruction &) { // Cannot value number calls or terminator instructions. } @@ -148,6 +152,24 @@ return false; } +// isIdenticalTernaryInst - Return true if the two ternary instructions are +// identical. +// +static inline bool isIdenticalTernaryInst(const Instruction &I1, + const Instruction *I2) { + // Is it embedded in the same function? (This could be false if LHS + // is a constant or global!) + if (I1.getParent()->getParent() != I2->getParent()->getParent()) + return false; + + // They are identical if all operands are the same! + return I1.getOperand(0) == I2->getOperand(0) && + I1.getOperand(1) == I2->getOperand(1) && + I1.getOperand(2) == I2->getOperand(2); +} + + + void BVNImpl::handleBinaryInst(Instruction &I) { Value *LHS = I.getOperand(0); @@ -199,37 +221,21 @@ } } -// isIdenticalSelectInst - Return true if the two select instructions are -// identical. -// -static inline bool isIdenticalSelectInst(const SelectInst &I1, - const SelectInst *I2) { - // Is it embedded in the same function? (This could be false if LHS - // is a constant or global!) - if (I1.getParent()->getParent() != I2->getParent()->getParent()) - return false; +void BVNImpl::handleTernaryInst(Instruction &I) { + Value *Op0 = I.getOperand(0); + Instruction *OtherInst; - // They are identical if both operands are the same! - return I1.getOperand(0) == I2->getOperand(0) && - I1.getOperand(1) == I2->getOperand(1) && - I1.getOperand(2) == I2->getOperand(2); - return true; - - return false; -} - -void BVNImpl::visitSelectInst(SelectInst &I) { - Value *Cond = I.getOperand(0); - - for (Value::use_iterator UI = Cond->use_begin(), UE = Cond->use_end(); + for (Value::use_iterator UI = Op0->use_begin(), UE = Op0->use_end(); UI != UE; ++UI) - if (SelectInst *Other = dyn_cast(*UI)) + if ((OtherInst = dyn_cast(*UI)) && + OtherInst->getOpcode() == I.getOpcode()) { // Check to see if this new select is not I, but has the same operands. - if (Other != &I && isIdenticalSelectInst(I, Other)) { + if (OtherInst != &I && isIdenticalTernaryInst(I, OtherInst)) { // These instructions are identical. Handle the situation. - RetVals.push_back(Other); + RetVals.push_back(OtherInst); } + } } From lattner at cs.uiuc.edu Fri Apr 14 00:19:30 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 14 Apr 2006 00:19:30 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp Message-ID: <200604140519.AAA16458@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.148 -> 1.149 --- Log message: Pull the VECTOR_SHUFFLE and BUILD_VECTOR lowering code out into separate functions, which makes the code much cleaner :) --- Diffs of the changes: (+155 -147) PPCISelLowering.cpp | 302 ++++++++++++++++++++++++++-------------------------- 1 files changed, 155 insertions(+), 147 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.148 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.149 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.148 Thu Apr 13 12:10:48 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Fri Apr 14 00:19:18 2006 @@ -587,11 +587,166 @@ return false; } +// If this is a case we can't handle, return null and let the default +// expansion code take care of it. If we CAN select this case, and if it +// selects to a single instruction, return Op. Otherwise, if we can codegen +// this case more efficiently than a constant pool load, lower it to the +// sequence of ops that should be used. +static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) { + // If this is a vector of constants or undefs, get the bits. A bit in + // UndefBits is set if the corresponding element of the vector is an + // ISD::UNDEF value. For undefs, the corresponding VectorBits values are + // zero. + uint64_t VectorBits[2]; + uint64_t UndefBits[2]; + if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits)) + return SDOperand(); // Not a constant vector. + + // See if this is all zeros. + if ((VectorBits[0] | VectorBits[1]) == 0) { + // Canonicalize all zero vectors to be v4i32. + if (Op.getValueType() != MVT::v4i32) { + SDOperand Z = DAG.getConstant(0, MVT::i32); + Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z); + Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z); + } + return Op; + } + + // Check to see if this is something we can use VSPLTI* to form. + MVT::ValueType CanonicalVT = MVT::Other; + SDNode *CST = 0; + + if ((CST = PPC::get_VSPLTI_elt(Op.Val, 4, DAG).Val)) // vspltisw + CanonicalVT = MVT::v4i32; + else if ((CST = PPC::get_VSPLTI_elt(Op.Val, 2, DAG).Val)) // vspltish + CanonicalVT = MVT::v8i16; + else if ((CST = PPC::get_VSPLTI_elt(Op.Val, 1, DAG).Val)) // vspltisb + CanonicalVT = MVT::v16i8; + + // If this matches one of the vsplti* patterns, force it to the canonical + // type for the pattern. + if (CST) { + if (Op.getValueType() != CanonicalVT) { + // Convert the splatted element to the right element type. + SDOperand Elt = DAG.getNode(ISD::TRUNCATE, + MVT::getVectorBaseType(CanonicalVT), + SDOperand(CST, 0)); + std::vector Ops(MVT::getVectorNumElements(CanonicalVT), Elt); + SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT, Ops); + Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); + } + return Op; + } + + // If this is some other splat of 4-byte elements, see if we can handle it + // in another way. + // FIXME: Make this more undef happy and work with other widths (1,2 bytes). + if (VectorBits[0] == VectorBits[1] && + unsigned(VectorBits[0]) == unsigned(VectorBits[0] >> 32)) { + unsigned Bits = unsigned(VectorBits[0]); + + // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is + // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). These are important + // for fneg/fabs. + if (Bits == 0x80000000 || Bits == 0x7FFFFFFF) { + // Make -1 and vspltisw -1: + SDOperand OnesI = DAG.getConstant(~0U, MVT::i32); + SDOperand OnesV = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, + OnesI, OnesI, OnesI, OnesI); + + // Make the VSLW intrinsic, computing 0x8000_0000. + SDOperand Res + = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, MVT::v4i32, + DAG.getConstant(Intrinsic::ppc_altivec_vslw, MVT::i32), + OnesV, OnesV); + + // If this is 0x7FFF_FFFF, xor by OnesV to invert it. + if (Bits == 0x7FFFFFFF) + Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV); + + return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); + } + } + + return SDOperand(); +} + +/// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this +/// is a shuffle we can handle in a single instruction, return it. Otherwise, +/// return the code it can be lowered into. Worst case, it can always be +/// lowered into a vperm. +static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) { + SDOperand V1 = Op.getOperand(0); + SDOperand V2 = Op.getOperand(1); + SDOperand PermMask = Op.getOperand(2); + + // Cases that are handled by instructions that take permute immediates + // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be + // selected by the instruction selector. + if (V2.getOpcode() == ISD::UNDEF) { + if (PPC::isSplatShuffleMask(PermMask.Val, 1) || + PPC::isSplatShuffleMask(PermMask.Val, 2) || + PPC::isSplatShuffleMask(PermMask.Val, 4) || + PPC::isVPKUWUMShuffleMask(PermMask.Val, true) || + PPC::isVPKUHUMShuffleMask(PermMask.Val, true) || + PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 || + PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) || + PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) || + PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) || + PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) || + PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) || + PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) { + return Op; + } + } + + // Altivec has a variety of "shuffle immediates" that take two vector inputs + // and produce a fixed permutation. If any of these match, do not lower to + // VPERM. + if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) || + PPC::isVPKUHUMShuffleMask(PermMask.Val, false) || + PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 || + PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) || + PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) || + PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) || + PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) || + PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) || + PPC::isVMRGHShuffleMask(PermMask.Val, 4, false)) + return Op; + + // TODO: Handle more cases, and also handle cases that are cheaper to do as + // multiple such instructions than as a constant pool load/vperm pair. + + // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant + // vector that will get spilled to the constant pool. + if (V2.getOpcode() == ISD::UNDEF) V2 = V1; + + // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except + // that it is in input element units, not in bytes. Convert now. + MVT::ValueType EltVT = MVT::getVectorBaseType(V1.getValueType()); + unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8; + + std::vector ResultMask; + for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) { + unsigned SrcElt =cast(PermMask.getOperand(i))->getValue(); + + for (unsigned j = 0; j != BytesPerElement; ++j) + ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j, + MVT::i8)); + } + + SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, ResultMask); + return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask); +} + /// LowerOperation - Provide custom lowering hooks for some operations. /// SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { switch (Op.getOpcode()) { default: assert(0 && "Wasn't expecting to be able to lower this!"); + case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); + case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); case ISD::FP_TO_SINT: { assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType())); SDOperand Src = Op.getOperand(0); @@ -963,153 +1118,6 @@ // Load it out. return DAG.getLoad(Op.getValueType(), Store, FIdx, DAG.getSrcValue(NULL)); } - case ISD::BUILD_VECTOR: { - // If this is a case we can't handle, return null and let the default - // expansion code take care of it. If we CAN select this case, return Op - // or something simpler. - - // If this is a vector of constants or undefs, get the bits. A bit in - // UndefBits is set if the corresponding element of the vector is an - // ISD::UNDEF value. For undefs, the corresponding VectorBits values are - // zero. - uint64_t VectorBits[2]; - uint64_t UndefBits[2]; - if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits)) - return SDOperand(); // Not a constant vector. - - // See if this is all zeros. - if ((VectorBits[0] | VectorBits[1]) == 0) { - // Canonicalize all zero vectors to be v4i32. - if (Op.getValueType() != MVT::v4i32) { - SDOperand Z = DAG.getConstant(0, MVT::i32); - Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z); - Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z); - } - return Op; - } - - // Check to see if this is something we can use VSPLTI* to form. - MVT::ValueType CanonicalVT = MVT::Other; - SDNode *CST = 0; - - if ((CST = PPC::get_VSPLTI_elt(Op.Val, 4, DAG).Val)) // vspltisw - CanonicalVT = MVT::v4i32; - else if ((CST = PPC::get_VSPLTI_elt(Op.Val, 2, DAG).Val)) // vspltish - CanonicalVT = MVT::v8i16; - else if ((CST = PPC::get_VSPLTI_elt(Op.Val, 1, DAG).Val)) // vspltisb - CanonicalVT = MVT::v16i8; - - // If this matches one of the vsplti* patterns, force it to the canonical - // type for the pattern. - if (CST) { - if (Op.getValueType() != CanonicalVT) { - // Convert the splatted element to the right element type. - SDOperand Elt = DAG.getNode(ISD::TRUNCATE, - MVT::getVectorBaseType(CanonicalVT), - SDOperand(CST, 0)); - std::vector Ops(MVT::getVectorNumElements(CanonicalVT), Elt); - SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT, Ops); - Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); - } - return Op; - } - - // If this is some other splat of 4-byte elements, see if we can handle it - // in another way. - // FIXME: Make this more undef happy and work with other widths (1,2 bytes). - if (VectorBits[0] == VectorBits[1] && - unsigned(VectorBits[0]) == unsigned(VectorBits[0] >> 32)) { - unsigned Bits = unsigned(VectorBits[0]); - - // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is - // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). These are important - // for fneg/fabs. - if (Bits == 0x80000000 || Bits == 0x7FFFFFFF) { - // Make -1 and vspltisw -1: - SDOperand OnesI = DAG.getConstant(~0U, MVT::i32); - SDOperand OnesV = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, - OnesI, OnesI, OnesI, OnesI); - - // Make the VSLW intrinsic, computing 0x8000_0000. - SDOperand Res - = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, MVT::v4i32, - DAG.getConstant(Intrinsic::ppc_altivec_vslw, MVT::i32), - OnesV, OnesV); - - // If this is 0x7FFF_FFFF, xor by OnesV to invert it. - if (Bits == 0x7FFFFFFF) - Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV); - - return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); - } - } - - - return SDOperand(); - } - case ISD::VECTOR_SHUFFLE: { - SDOperand V1 = Op.getOperand(0); - SDOperand V2 = Op.getOperand(1); - SDOperand PermMask = Op.getOperand(2); - - // Cases that are handled by instructions that take permute immediates - // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be - // selected by the instruction selector. - if (V2.getOpcode() == ISD::UNDEF) { - if (PPC::isSplatShuffleMask(PermMask.Val, 1) || - PPC::isSplatShuffleMask(PermMask.Val, 2) || - PPC::isSplatShuffleMask(PermMask.Val, 4) || - PPC::isVPKUWUMShuffleMask(PermMask.Val, true) || - PPC::isVPKUHUMShuffleMask(PermMask.Val, true) || - PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 || - PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) || - PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) || - PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) || - PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) || - PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) || - PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) { - return Op; - } - } - - // Altivec has a variety of "shuffle immediates" that take two vector inputs - // and produce a fixed permutation. If any of these match, do not lower to - // VPERM. - if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) || - PPC::isVPKUHUMShuffleMask(PermMask.Val, false) || - PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 || - PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) || - PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) || - PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) || - PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) || - PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) || - PPC::isVMRGHShuffleMask(PermMask.Val, 4, false)) - return Op; - - // TODO: Handle more cases, and also handle cases that are cheaper to do as - // multiple such instructions than as a constant pool load/vperm pair. - - // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant - // vector that will get spilled to the constant pool. - if (V2.getOpcode() == ISD::UNDEF) V2 = V1; - - // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except - // that it is in input element units, not in bytes. Convert now. - MVT::ValueType EltVT = MVT::getVectorBaseType(V1.getValueType()); - unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8; - - std::vector ResultMask; - for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) { - unsigned SrcElt =cast(PermMask.getOperand(i))->getValue(); - - for (unsigned j = 0; j != BytesPerElement; ++j) - ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j, - MVT::i8)); - } - - SDOperand VPermMask =DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, ResultMask); - return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask); - } case ISD::INTRINSIC_WO_CHAIN: { unsigned IntNo = cast(Op.getOperand(0))->getValue(); From lattner at cs.uiuc.edu Fri Apr 14 01:02:11 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 14 Apr 2006 01:02:11 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp Message-ID: <200604140602.BAA18995@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.149 -> 1.150 --- Log message: Move the rest of the PPCTargetLowering::LowerOperation cases out into separate functions, for simplicity and code clarity. --- Diffs of the changes: (+531 -470) PPCISelLowering.cpp | 1001 +++++++++++++++++++++++++++------------------------- 1 files changed, 531 insertions(+), 470 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.149 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.150 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.149 Fri Apr 14 00:19:18 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Fri Apr 14 01:01:58 2006 @@ -258,6 +258,10 @@ } } +//===----------------------------------------------------------------------===// +// Node matching predicates, for use by the tblgen matching code. +//===----------------------------------------------------------------------===// + /// isFloatingPointZero - Return true if this is 0.0 or -0.0. static bool isFloatingPointZero(SDOperand Op) { if (ConstantFPSDNode *CFP = dyn_cast(Op)) @@ -544,6 +548,388 @@ return SDOperand(); } +//===----------------------------------------------------------------------===// +// LowerOperation implementation +//===----------------------------------------------------------------------===// + +static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) { + ConstantPoolSDNode *CP = cast(Op); + Constant *C = CP->get(); + SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i32, CP->getAlignment()); + SDOperand Zero = DAG.getConstant(0, MVT::i32); + + const TargetMachine &TM = DAG.getTarget(); + + // If this is a non-darwin platform, we don't support non-static relo models + // yet. + if (TM.getRelocationModel() == Reloc::Static || + !TM.getSubtarget().isDarwin()) { + // Generate non-pic code that has direct accesses to the constant pool. + // The address of the global is just (hi(&g)+lo(&g)). + SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero); + SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, CPI, Zero); + return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo); + } + + SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero); + if (TM.getRelocationModel() == Reloc::PIC) { + // With PIC, the first instruction is actually "GR+hi(&G)". + Hi = DAG.getNode(ISD::ADD, MVT::i32, + DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi); + } + + SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, CPI, Zero); + Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo); + return Lo; +} + +static SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) { + GlobalAddressSDNode *GSDN = cast(Op); + GlobalValue *GV = GSDN->getGlobal(); + SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32, GSDN->getOffset()); + SDOperand Zero = DAG.getConstant(0, MVT::i32); + + const TargetMachine &TM = DAG.getTarget(); + + // If this is a non-darwin platform, we don't support non-static relo models + // yet. + if (TM.getRelocationModel() == Reloc::Static || + !TM.getSubtarget().isDarwin()) { + // Generate non-pic code that has direct accesses to globals. + // The address of the global is just (hi(&g)+lo(&g)). + SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, GA, Zero); + SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, GA, Zero); + return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo); + } + + SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, GA, Zero); + if (TM.getRelocationModel() == Reloc::PIC) { + // With PIC, the first instruction is actually "GR+hi(&G)". + Hi = DAG.getNode(ISD::ADD, MVT::i32, + DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi); + } + + SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, GA, Zero); + Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo); + + if (!GV->hasWeakLinkage() && !GV->hasLinkOnceLinkage() && + (!GV->isExternal() || GV->hasNotBeenReadFromBytecode())) + return Lo; + + // If the global is weak or external, we have to go through the lazy + // resolution stub. + return DAG.getLoad(MVT::i32, DAG.getEntryNode(), Lo, DAG.getSrcValue(0)); +} + +static SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG) { + ISD::CondCode CC = cast(Op.getOperand(2))->get(); + + // If we're comparing for equality to zero, expose the fact that this is + // implented as a ctlz/srl pair on ppc, so that the dag combiner can + // fold the new nodes. + if (ConstantSDNode *C = dyn_cast(Op.getOperand(1))) { + if (C->isNullValue() && CC == ISD::SETEQ) { + MVT::ValueType VT = Op.getOperand(0).getValueType(); + SDOperand Zext = Op.getOperand(0); + if (VT < MVT::i32) { + VT = MVT::i32; + Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0)); + } + unsigned Log2b = Log2_32(MVT::getSizeInBits(VT)); + SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext); + SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz, + DAG.getConstant(Log2b, MVT::i32)); + return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc); + } + // Leave comparisons against 0 and -1 alone for now, since they're usually + // optimized. FIXME: revisit this when we can custom lower all setcc + // optimizations. + if (C->isAllOnesValue() || C->isNullValue()) + return SDOperand(); + } + + // If we have an integer seteq/setne, turn it into a compare against zero + // by subtracting the rhs from the lhs, which is faster than setting a + // condition register, reading it back out, and masking the correct bit. + MVT::ValueType LHSVT = Op.getOperand(0).getValueType(); + if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) { + MVT::ValueType VT = Op.getValueType(); + SDOperand Sub = DAG.getNode(ISD::SUB, LHSVT, Op.getOperand(0), + Op.getOperand(1)); + return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC); + } + return SDOperand(); +} + +static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG, + unsigned VarArgsFrameIndex) { + // vastart just stores the address of the VarArgsFrameIndex slot into the + // memory location argument. + SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32); + return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), FR, + Op.getOperand(1), Op.getOperand(2)); +} + +static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) { + SDOperand Copy; + switch(Op.getNumOperands()) { + default: + assert(0 && "Do not know how to return this many arguments!"); + abort(); + case 1: + return SDOperand(); // ret void is legal + case 2: { + MVT::ValueType ArgVT = Op.getOperand(1).getValueType(); + unsigned ArgReg; + if (MVT::isVector(ArgVT)) + ArgReg = PPC::V2; + else if (MVT::isInteger(ArgVT)) + ArgReg = PPC::R3; + else { + assert(MVT::isFloatingPoint(ArgVT)); + ArgReg = PPC::F1; + } + + Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1), + SDOperand()); + + // If we haven't noted the R3/F1 are live out, do so now. + if (DAG.getMachineFunction().liveout_empty()) + DAG.getMachineFunction().addLiveOut(ArgReg); + break; + } + case 3: + Copy = DAG.getCopyToReg(Op.getOperand(0), PPC::R3, Op.getOperand(2), + SDOperand()); + Copy = DAG.getCopyToReg(Copy, PPC::R4, Op.getOperand(1),Copy.getValue(1)); + // If we haven't noted the R3+R4 are live out, do so now. + if (DAG.getMachineFunction().liveout_empty()) { + DAG.getMachineFunction().addLiveOut(PPC::R3); + DAG.getMachineFunction().addLiveOut(PPC::R4); + } + break; + } + return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); +} + +/// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when +/// possible. +static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) { + // Not FP? Not a fsel. + if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) || + !MVT::isFloatingPoint(Op.getOperand(2).getValueType())) + return SDOperand(); + + ISD::CondCode CC = cast(Op.getOperand(4))->get(); + + // Cannot handle SETEQ/SETNE. + if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDOperand(); + + MVT::ValueType ResVT = Op.getValueType(); + MVT::ValueType CmpVT = Op.getOperand(0).getValueType(); + SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); + SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3); + + // If the RHS of the comparison is a 0.0, we don't need to do the + // subtraction at all. + if (isFloatingPointZero(RHS)) + switch (CC) { + default: break; // SETUO etc aren't handled by fsel. + case ISD::SETULT: + case ISD::SETLT: + std::swap(TV, FV); // fsel is natively setge, swap operands for setlt + case ISD::SETUGE: + case ISD::SETGE: + if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits + LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); + return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV); + case ISD::SETUGT: + case ISD::SETGT: + std::swap(TV, FV); // fsel is natively setge, swap operands for setlt + case ISD::SETULE: + case ISD::SETLE: + if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits + LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); + return DAG.getNode(PPCISD::FSEL, ResVT, + DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV); + } + + SDOperand Cmp; + switch (CC) { + default: break; // SETUO etc aren't handled by fsel. + case ISD::SETULT: + case ISD::SETLT: + Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); + if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits + Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); + return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); + case ISD::SETUGE: + case ISD::SETGE: + Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); + if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits + Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); + return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); + case ISD::SETUGT: + case ISD::SETGT: + Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); + if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits + Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); + return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); + case ISD::SETULE: + case ISD::SETLE: + Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); + if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits + Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); + return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); + } + return SDOperand(); +} + +static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) { + assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType())); + SDOperand Src = Op.getOperand(0); + if (Src.getValueType() == MVT::f32) + Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src); + + SDOperand Tmp; + switch (Op.getValueType()) { + default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!"); + case MVT::i32: + Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src); + break; + case MVT::i64: + Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src); + break; + } + + // Convert the FP value to an int value through memory. + SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Tmp); + if (Op.getValueType() == MVT::i32) + Bits = DAG.getNode(ISD::TRUNCATE, MVT::i32, Bits); + return Bits; +} + +static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { + if (Op.getOperand(0).getValueType() == MVT::i64) { + SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0)); + SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits); + if (Op.getValueType() == MVT::f32) + FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP); + return FP; + } + + assert(Op.getOperand(0).getValueType() == MVT::i32 && + "Unhandled SINT_TO_FP type in custom expander!"); + // Since we only generate this in 64-bit mode, we can take advantage of + // 64-bit registers. In particular, sign extend the input value into the + // 64-bit register with extsw, store the WHOLE 64-bit value into the stack + // then lfd it and fcfid it. + MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); + int FrameIdx = FrameInfo->CreateStackObject(8, 8); + SDOperand FIdx = DAG.getFrameIndex(FrameIdx, MVT::i32); + + SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32, + Op.getOperand(0)); + + // STD the extended value into the stack slot. + SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other, + DAG.getEntryNode(), Ext64, FIdx, + DAG.getSrcValue(NULL)); + // Load the value as a double. + SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, DAG.getSrcValue(NULL)); + + // FCFID it and return it. + SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld); + if (Op.getValueType() == MVT::f32) + FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP); + return FP; +} + +static SDOperand LowerSHL(SDOperand Op, SelectionDAG &DAG) { + assert(Op.getValueType() == MVT::i64 && + Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!"); + // The generic code does a fine job expanding shift by a constant. + if (isa(Op.getOperand(1))) return SDOperand(); + + // Otherwise, expand into a bunch of logical ops. Note that these ops + // depend on the PPC behavior for oversized shift amounts. + SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), + DAG.getConstant(0, MVT::i32)); + SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), + DAG.getConstant(1, MVT::i32)); + SDOperand Amt = Op.getOperand(1); + + SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, + DAG.getConstant(32, MVT::i32), Amt); + SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt); + SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1); + SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); + SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, + DAG.getConstant(-32U, MVT::i32)); + SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5); + SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6); + SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt); + return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi); +} + +static SDOperand LowerSRL(SDOperand Op, SelectionDAG &DAG) { + assert(Op.getValueType() == MVT::i64 && + Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!"); + // The generic code does a fine job expanding shift by a constant. + if (isa(Op.getOperand(1))) return SDOperand(); + + // Otherwise, expand into a bunch of logical ops. Note that these ops + // depend on the PPC behavior for oversized shift amounts. + SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), + DAG.getConstant(0, MVT::i32)); + SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), + DAG.getConstant(1, MVT::i32)); + SDOperand Amt = Op.getOperand(1); + + SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, + DAG.getConstant(32, MVT::i32), Amt); + SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt); + SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1); + SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); + SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, + DAG.getConstant(-32U, MVT::i32)); + SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5); + SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6); + SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt); + return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi); +} + +static SDOperand LowerSRA(SDOperand Op, SelectionDAG &DAG) { + assert(Op.getValueType() == MVT::i64 && + Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!"); + // The generic code does a fine job expanding shift by a constant. + if (isa(Op.getOperand(1))) return SDOperand(); + + // Otherwise, expand into a bunch of logical ops, followed by a select_cc. + SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), + DAG.getConstant(0, MVT::i32)); + SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), + DAG.getConstant(1, MVT::i32)); + SDOperand Amt = Op.getOperand(1); + + SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, + DAG.getConstant(32, MVT::i32), Amt); + SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt); + SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1); + SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); + SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, + DAG.getConstant(-32U, MVT::i32)); + SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5); + SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt); + SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32), + Tmp4, Tmp6, ISD::SETLE); + return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi); +} + +//===----------------------------------------------------------------------===// +// Vector related lowering. +// + // If this is a vector of constants or undefs, get the bits. A bit in // UndefBits is set if the corresponding element of the vector is an // ISD::UNDEF value. For undefs, the corresponding VectorBits values are @@ -740,486 +1126,153 @@ return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask); } -/// LowerOperation - Provide custom lowering hooks for some operations. -/// -SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { - switch (Op.getOpcode()) { - default: assert(0 && "Wasn't expecting to be able to lower this!"); - case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); - case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); - case ISD::FP_TO_SINT: { - assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType())); - SDOperand Src = Op.getOperand(0); - if (Src.getValueType() == MVT::f32) - Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src); - - SDOperand Tmp; - switch (Op.getValueType()) { - default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!"); - case MVT::i32: - Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src); - break; - case MVT::i64: - Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src); - break; - } - - // Convert the FP value to an int value through memory. - SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Tmp); - if (Op.getValueType() == MVT::i32) - Bits = DAG.getNode(ISD::TRUNCATE, MVT::i32, Bits); - return Bits; +/// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom +/// lower, do it, otherwise return null. +static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) { + unsigned IntNo = cast(Op.getOperand(0))->getValue(); + + // If this is a lowered altivec predicate compare, CompareOpc is set to the + // opcode number of the comparison. + int CompareOpc = -1; + bool isDot = false; + switch (IntNo) { + default: return SDOperand(); // Don't custom lower most intrinsics. + // Comparison predicates. + case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break; + case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break; + case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break; + case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break; + case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break; + case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break; + case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break; + case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break; + case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break; + case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break; + case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break; + case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break; + case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break; + + // Normal Comparisons. + case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break; + case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break; + case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break; + case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break; + case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break; + case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break; + case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break; + case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break; + case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break; + case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break; + case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break; + case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break; + case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break; + } + + assert(CompareOpc>0 && "We only lower altivec predicate compares so far!"); + + // If this is a non-dot comparison, make the VCMP node. + if (!isDot) { + SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(), + Op.getOperand(1), Op.getOperand(2), + DAG.getConstant(CompareOpc, MVT::i32)); + return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp); } - case ISD::SINT_TO_FP: - if (Op.getOperand(0).getValueType() == MVT::i64) { - SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0)); - SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits); - if (Op.getValueType() == MVT::f32) - FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP); - return FP; - } else { - assert(Op.getOperand(0).getValueType() == MVT::i32 && - "Unhandled SINT_TO_FP type in custom expander!"); - // Since we only generate this in 64-bit mode, we can take advantage of - // 64-bit registers. In particular, sign extend the input value into the - // 64-bit register with extsw, store the WHOLE 64-bit value into the stack - // then lfd it and fcfid it. - MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); - int FrameIdx = FrameInfo->CreateStackObject(8, 8); - SDOperand FIdx = DAG.getFrameIndex(FrameIdx, MVT::i32); - - SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32, - Op.getOperand(0)); - - // STD the extended value into the stack slot. - SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other, - DAG.getEntryNode(), Ext64, FIdx, - DAG.getSrcValue(NULL)); - // Load the value as a double. - SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, DAG.getSrcValue(NULL)); - - // FCFID it and return it. - SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld); - if (Op.getValueType() == MVT::f32) - FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP); - return FP; - } + + // Create the PPCISD altivec 'dot' comparison node. + std::vector Ops; + std::vector VTs; + Ops.push_back(Op.getOperand(2)); // LHS + Ops.push_back(Op.getOperand(3)); // RHS + Ops.push_back(DAG.getConstant(CompareOpc, MVT::i32)); + VTs.push_back(Op.getOperand(2).getValueType()); + VTs.push_back(MVT::Flag); + SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops); + + // Now that we have the comparison, emit a copy from the CR to a GPR. + // This is flagged to the above dot comparison. + SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32, + DAG.getRegister(PPC::CR6, MVT::i32), + CompNode.getValue(1)); + + // Unpack the result based on how the target uses it. + unsigned BitNo; // Bit # of CR6. + bool InvertBit; // Invert result? + switch (cast(Op.getOperand(1))->getValue()) { + default: // Can't happen, don't crash on invalid number though. + case 0: // Return the value of the EQ bit of CR6. + BitNo = 0; InvertBit = false; break; - - case ISD::SELECT_CC: { - // Turn FP only select_cc's into fsel instructions. - if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) || - !MVT::isFloatingPoint(Op.getOperand(2).getValueType())) - break; - - ISD::CondCode CC = cast(Op.getOperand(4))->get(); - - // Cannot handle SETEQ/SETNE. - if (CC == ISD::SETEQ || CC == ISD::SETNE) break; - - MVT::ValueType ResVT = Op.getValueType(); - MVT::ValueType CmpVT = Op.getOperand(0).getValueType(); - SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); - SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3); - - // If the RHS of the comparison is a 0.0, we don't need to do the - // subtraction at all. - if (isFloatingPointZero(RHS)) - switch (CC) { - default: break; // SETUO etc aren't handled by fsel. - case ISD::SETULT: - case ISD::SETLT: - std::swap(TV, FV); // fsel is natively setge, swap operands for setlt - case ISD::SETUGE: - case ISD::SETGE: - if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits - LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); - return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV); - case ISD::SETUGT: - case ISD::SETGT: - std::swap(TV, FV); // fsel is natively setge, swap operands for setlt - case ISD::SETULE: - case ISD::SETLE: - if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits - LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); - return DAG.getNode(PPCISD::FSEL, ResVT, - DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV); - } - - SDOperand Cmp; - switch (CC) { - default: break; // SETUO etc aren't handled by fsel. - case ISD::SETULT: - case ISD::SETLT: - Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); - if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits - Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); - return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); - case ISD::SETUGE: - case ISD::SETGE: - Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); - if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits - Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); - return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); - case ISD::SETUGT: - case ISD::SETGT: - Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); - if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits - Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); - return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); - case ISD::SETULE: - case ISD::SETLE: - Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); - if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits - Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); - return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); - } + case 1: // Return the inverted value of the EQ bit of CR6. + BitNo = 0; InvertBit = true; break; - } - case ISD::SHL: { - assert(Op.getValueType() == MVT::i64 && - Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!"); - // The generic code does a fine job expanding shift by a constant. - if (isa(Op.getOperand(1))) break; - - // Otherwise, expand into a bunch of logical ops. Note that these ops - // depend on the PPC behavior for oversized shift amounts. - SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), - DAG.getConstant(0, MVT::i32)); - SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), - DAG.getConstant(1, MVT::i32)); - SDOperand Amt = Op.getOperand(1); - - SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, - DAG.getConstant(32, MVT::i32), Amt); - SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt); - SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1); - SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); - SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, - DAG.getConstant(-32U, MVT::i32)); - SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5); - SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6); - SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt); - return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi); - } - case ISD::SRL: { - assert(Op.getValueType() == MVT::i64 && - Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!"); - // The generic code does a fine job expanding shift by a constant. - if (isa(Op.getOperand(1))) break; - - // Otherwise, expand into a bunch of logical ops. Note that these ops - // depend on the PPC behavior for oversized shift amounts. - SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), - DAG.getConstant(0, MVT::i32)); - SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), - DAG.getConstant(1, MVT::i32)); - SDOperand Amt = Op.getOperand(1); - - SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, - DAG.getConstant(32, MVT::i32), Amt); - SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt); - SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1); - SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); - SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, - DAG.getConstant(-32U, MVT::i32)); - SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5); - SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6); - SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt); - return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi); - } - case ISD::SRA: { - assert(Op.getValueType() == MVT::i64 && - Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!"); - // The generic code does a fine job expanding shift by a constant. - if (isa(Op.getOperand(1))) break; - - // Otherwise, expand into a bunch of logical ops, followed by a select_cc. - SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), - DAG.getConstant(0, MVT::i32)); - SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), - DAG.getConstant(1, MVT::i32)); - SDOperand Amt = Op.getOperand(1); - - SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, - DAG.getConstant(32, MVT::i32), Amt); - SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt); - SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1); - SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); - SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, - DAG.getConstant(-32U, MVT::i32)); - SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5); - SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt); - SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32), - Tmp4, Tmp6, ISD::SETLE); - return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi); - } - case ISD::ConstantPool: { - ConstantPoolSDNode *CP = cast(Op); - Constant *C = CP->get(); - SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i32, CP->getAlignment()); - SDOperand Zero = DAG.getConstant(0, MVT::i32); - - // If this is a non-darwin platform, we don't support non-static relo models - // yet. - if (getTargetMachine().getRelocationModel() == Reloc::Static || - !getTargetMachine().getSubtarget().isDarwin()) { - // Generate non-pic code that has direct accesses to the constant pool. - // The address of the global is just (hi(&g)+lo(&g)). - SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero); - SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, CPI, Zero); - return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo); - } - - SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero); - if (getTargetMachine().getRelocationModel() == Reloc::PIC) { - // With PIC, the first instruction is actually "GR+hi(&G)". - Hi = DAG.getNode(ISD::ADD, MVT::i32, - DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi); - } - - SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, CPI, Zero); - Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo); - return Lo; - } - case ISD::GlobalAddress: { - GlobalAddressSDNode *GSDN = cast(Op); - GlobalValue *GV = GSDN->getGlobal(); - SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32, GSDN->getOffset()); - SDOperand Zero = DAG.getConstant(0, MVT::i32); - - // If this is a non-darwin platform, we don't support non-static relo models - // yet. - if (getTargetMachine().getRelocationModel() == Reloc::Static || - !getTargetMachine().getSubtarget().isDarwin()) { - // Generate non-pic code that has direct accesses to globals. - // The address of the global is just (hi(&g)+lo(&g)). - SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, GA, Zero); - SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, GA, Zero); - return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo); - } - - SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, GA, Zero); - if (getTargetMachine().getRelocationModel() == Reloc::PIC) { - // With PIC, the first instruction is actually "GR+hi(&G)". - Hi = DAG.getNode(ISD::ADD, MVT::i32, - DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi); - } - - SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, GA, Zero); - Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo); - - if (!GV->hasWeakLinkage() && !GV->hasLinkOnceLinkage() && - (!GV->isExternal() || GV->hasNotBeenReadFromBytecode())) - return Lo; - - // If the global is weak or external, we have to go through the lazy - // resolution stub. - return DAG.getLoad(MVT::i32, DAG.getEntryNode(), Lo, DAG.getSrcValue(0)); - } - case ISD::SETCC: { - ISD::CondCode CC = cast(Op.getOperand(2))->get(); - - // If we're comparing for equality to zero, expose the fact that this is - // implented as a ctlz/srl pair on ppc, so that the dag combiner can - // fold the new nodes. - if (ConstantSDNode *C = dyn_cast(Op.getOperand(1))) { - if (C->isNullValue() && CC == ISD::SETEQ) { - MVT::ValueType VT = Op.getOperand(0).getValueType(); - SDOperand Zext = Op.getOperand(0); - if (VT < MVT::i32) { - VT = MVT::i32; - Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0)); - } - unsigned Log2b = Log2_32(MVT::getSizeInBits(VT)); - SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext); - SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz, - DAG.getConstant(Log2b, getShiftAmountTy())); - return DAG.getNode(ISD::TRUNCATE, getSetCCResultTy(), Scc); - } - // Leave comparisons against 0 and -1 alone for now, since they're usually - // optimized. FIXME: revisit this when we can custom lower all setcc - // optimizations. - if (C->isAllOnesValue() || C->isNullValue()) - break; - } - - // If we have an integer seteq/setne, turn it into a compare against zero - // by subtracting the rhs from the lhs, which is faster than setting a - // condition register, reading it back out, and masking the correct bit. - MVT::ValueType LHSVT = Op.getOperand(0).getValueType(); - if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) { - MVT::ValueType VT = Op.getValueType(); - SDOperand Sub = DAG.getNode(ISD::SUB, LHSVT, Op.getOperand(0), - Op.getOperand(1)); - return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC); - } + case 2: // Return the value of the LT bit of CR6. + BitNo = 2; InvertBit = false; + break; + case 3: // Return the inverted value of the LT bit of CR6. + BitNo = 2; InvertBit = true; break; } - case ISD::VASTART: { - // vastart just stores the address of the VarArgsFrameIndex slot into the - // memory location argument. - // FIXME: Replace MVT::i32 with PointerTy - SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32); - return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), FR, - Op.getOperand(1), Op.getOperand(2)); - } - case ISD::RET: { - SDOperand Copy; - - switch(Op.getNumOperands()) { - default: - assert(0 && "Do not know how to return this many arguments!"); - abort(); - case 1: - return SDOperand(); // ret void is legal - case 2: { - MVT::ValueType ArgVT = Op.getOperand(1).getValueType(); - unsigned ArgReg; - if (MVT::isVector(ArgVT)) - ArgReg = PPC::V2; - else if (MVT::isInteger(ArgVT)) - ArgReg = PPC::R3; - else { - assert(MVT::isFloatingPoint(ArgVT)); - ArgReg = PPC::F1; - } - - Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1), - SDOperand()); - - // If we haven't noted the R3/F1 are live out, do so now. - if (DAG.getMachineFunction().liveout_empty()) - DAG.getMachineFunction().addLiveOut(ArgReg); - break; - } - case 3: - Copy = DAG.getCopyToReg(Op.getOperand(0), PPC::R3, Op.getOperand(2), - SDOperand()); - Copy = DAG.getCopyToReg(Copy, PPC::R4, Op.getOperand(1),Copy.getValue(1)); - // If we haven't noted the R3+R4 are live out, do so now. - if (DAG.getMachineFunction().liveout_empty()) { - DAG.getMachineFunction().addLiveOut(PPC::R3); - DAG.getMachineFunction().addLiveOut(PPC::R4); - } - break; - } - return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); - } - case ISD::SCALAR_TO_VECTOR: { - // Create a stack slot that is 16-byte aligned. - MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); - int FrameIdx = FrameInfo->CreateStackObject(16, 16); - SDOperand FIdx = DAG.getFrameIndex(FrameIdx, MVT::i32); - - // Store the input value into Value#0 of the stack slot. - SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), - Op.getOperand(0), FIdx,DAG.getSrcValue(NULL)); - // Load it out. - return DAG.getLoad(Op.getValueType(), Store, FIdx, DAG.getSrcValue(NULL)); - } - case ISD::INTRINSIC_WO_CHAIN: { - unsigned IntNo = cast(Op.getOperand(0))->getValue(); - - // If this is a lowered altivec predicate compare, CompareOpc is set to the - // opcode number of the comparison. - int CompareOpc = -1; - bool isDot = false; - switch (IntNo) { - default: return SDOperand(); // Don't custom lower most intrinsics. - // Comparison predicates. - case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break; - case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break; - case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break; - case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break; - case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break; - case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break; - case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break; - case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break; - case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break; - case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break; - case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break; - case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break; - case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break; - - // Normal Comparisons. - case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break; - case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break; - case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break; - case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break; - case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break; - case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break; - case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break; - case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break; - case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break; - case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break; - case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break; - case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break; - case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break; - } - - assert(CompareOpc>0 && "We only lower altivec predicate compares so far!"); - - // If this is a non-dot comparison, make the VCMP node. - if (!isDot) { - SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(), - Op.getOperand(1), Op.getOperand(2), - DAG.getConstant(CompareOpc, MVT::i32)); - return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp); - } - - // Create the PPCISD altivec 'dot' comparison node. - std::vector Ops; - std::vector VTs; - Ops.push_back(Op.getOperand(2)); // LHS - Ops.push_back(Op.getOperand(3)); // RHS - Ops.push_back(DAG.getConstant(CompareOpc, MVT::i32)); - VTs.push_back(Op.getOperand(2).getValueType()); - VTs.push_back(MVT::Flag); - SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops); - - // Now that we have the comparison, emit a copy from the CR to a GPR. - // This is flagged to the above dot comparison. - SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32, - DAG.getRegister(PPC::CR6, MVT::i32), - CompNode.getValue(1)); - - // Unpack the result based on how the target uses it. - unsigned BitNo; // Bit # of CR6. - bool InvertBit; // Invert result? - switch (cast(Op.getOperand(1))->getValue()) { - default: // Can't happen, don't crash on invalid number though. - case 0: // Return the value of the EQ bit of CR6. - BitNo = 0; InvertBit = false; - break; - case 1: // Return the inverted value of the EQ bit of CR6. - BitNo = 0; InvertBit = true; - break; - case 2: // Return the value of the LT bit of CR6. - BitNo = 2; InvertBit = false; - break; - case 3: // Return the inverted value of the LT bit of CR6. - BitNo = 2; InvertBit = true; - break; - } - - // Shift the bit into the low position. - Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags, - DAG.getConstant(8-(3-BitNo), MVT::i32)); - // Isolate the bit. - Flags = DAG.getNode(ISD::AND, MVT::i32, Flags, + + // Shift the bit into the low position. + Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags, + DAG.getConstant(8-(3-BitNo), MVT::i32)); + // Isolate the bit. + Flags = DAG.getNode(ISD::AND, MVT::i32, Flags, + DAG.getConstant(1, MVT::i32)); + + // If we are supposed to, toggle the bit. + if (InvertBit) + Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags, DAG.getConstant(1, MVT::i32)); - - // If we are supposed to, toggle the bit. - if (InvertBit) - Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags, - DAG.getConstant(1, MVT::i32)); - return Flags; - } + return Flags; +} + +static SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) { + // Create a stack slot that is 16-byte aligned. + MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); + int FrameIdx = FrameInfo->CreateStackObject(16, 16); + SDOperand FIdx = DAG.getFrameIndex(FrameIdx, MVT::i32); + + // Store the input value into Value#0 of the stack slot. + SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), + Op.getOperand(0), FIdx,DAG.getSrcValue(NULL)); + // Load it out. + return DAG.getLoad(Op.getValueType(), Store, FIdx, DAG.getSrcValue(NULL)); +} + +/// LowerOperation - Provide custom lowering hooks for some operations. +/// +SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { + switch (Op.getOpcode()) { + default: assert(0 && "Wasn't expecting to be able to lower this!"); + case ISD::ConstantPool: return LowerConstantPool(Op, DAG); + case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); + case ISD::SETCC: return LowerSETCC(Op, DAG); + case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex); + case ISD::RET: return LowerRET(Op, DAG); + + case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); + case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); + case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); + + // Lower 64-bit shifts. + case ISD::SHL: return LowerSHL(Op, DAG); + case ISD::SRL: return LowerSRL(Op, DAG); + case ISD::SRA: return LowerSRA(Op, DAG); + + // Vector-related lowering. + case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); + case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); + case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); + case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); } return SDOperand(); } +//===----------------------------------------------------------------------===// +// Other Lowering Code +//===----------------------------------------------------------------------===// + std::vector PPCTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { // @@ -1663,6 +1716,10 @@ return BB; } +//===----------------------------------------------------------------------===// +// Target Optimization Hooks +//===----------------------------------------------------------------------===// + SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { TargetMachine &TM = getTargetMachine(); @@ -1751,6 +1808,10 @@ return SDOperand(); } +//===----------------------------------------------------------------------===// +// Inline Assembly Support +//===----------------------------------------------------------------------===// + void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, uint64_t Mask, uint64_t &KnownZero, From lattner at cs.uiuc.edu Fri Apr 14 01:07:03 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 14 Apr 2006 01:07:03 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/Generic/2006-04-11-vecload.ll Message-ID: <200604140607.BAA19080@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/Generic: 2006-04-11-vecload.ll updated: 1.1 -> 1.2 --- Log message: Force a specific config, because this test fails in certain configs otherwise. --- Diffs of the changes: (+1 -1) 2006-04-11-vecload.ll | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/CodeGen/Generic/2006-04-11-vecload.ll diff -u llvm/test/Regression/CodeGen/Generic/2006-04-11-vecload.ll:1.1 llvm/test/Regression/CodeGen/Generic/2006-04-11-vecload.ll:1.2 --- llvm/test/Regression/CodeGen/Generic/2006-04-11-vecload.ll:1.1 Tue Apr 11 22:24:46 2006 +++ llvm/test/Regression/CodeGen/Generic/2006-04-11-vecload.ll Fri Apr 14 01:06:51 2006 @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc +; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah ; The vload was getting memoized to the previous scalar load! From lattner at cs.uiuc.edu Fri Apr 14 01:08:47 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 14 Apr 2006 01:08:47 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <200604140608.BAA19123@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.364 -> 1.365 --- Log message: Make this assertion better --- Diffs of the changes: (+1 -1) LegalizeDAG.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.364 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.365 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.364 Wed Apr 12 16:20:24 2006 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Apr 14 01:08:35 2006 @@ -4630,7 +4630,7 @@ } switch (Node->getOpcode()) { - default: Node->dump(); assert(0 && "Unknown vector operation!"); + default: Node->dump(); assert(0 && "Unhandled operation in SplitVectorOp!"); case ISD::VBUILD_VECTOR: { std::vector LoOps(Node->op_begin(), Node->op_begin()+NewNumElts); LoOps.push_back(NewNumEltsNode); From reid at x10sys.com Fri Apr 14 01:32:43 2006 From: reid at x10sys.com (Reid Spencer) Date: Fri, 14 Apr 2006 01:32:43 -0500 Subject: [llvm-commits] CVS: llvm/lib/VMCore/Makefile Message-ID: <200604140632.BAA19848@zion.cs.uiuc.edu> Changes in directory llvm/lib/VMCore: Makefile updated: 1.14 -> 1.15 --- Log message: Don't print out the install command for Intrinsics.gen unless VERBOSE mode. --- Diffs of the changes: (+2 -1) Makefile | 3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index: llvm/lib/VMCore/Makefile diff -u llvm/lib/VMCore/Makefile:1.14 llvm/lib/VMCore/Makefile:1.15 --- llvm/lib/VMCore/Makefile:1.14 Sun Mar 26 01:45:48 2006 +++ llvm/lib/VMCore/Makefile Fri Apr 14 01:32:31 2006 @@ -28,4 +28,5 @@ $(Verb) $(TableGen) $(INTRINSICTD) -o $@ -gen-intrinsic install-local:: $(GENFILE) - $(DataInstall) $(GENFILE) $(PROJ_includedir)/llvm/Intrinsics.gen + $(Echo) Installing $(PROJ_includedir)/llvm/Intrinsics.gen + $(Verb) $(DataInstall) $(GENFILE) $(PROJ_includedir)/llvm/Intrinsics.gen From evan.cheng at apple.com Fri Apr 14 02:24:21 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 14 Apr 2006 02:24:21 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/README.txt Message-ID: <200604140724.CAA16570@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: README.txt updated: 1.87 -> 1.88 --- Log message: New entry --- Diffs of the changes: (+5 -0) README.txt | 5 +++++ 1 files changed, 5 insertions(+) Index: llvm/lib/Target/X86/README.txt diff -u llvm/lib/Target/X86/README.txt:1.87 llvm/lib/Target/X86/README.txt:1.88 --- llvm/lib/Target/X86/README.txt:1.87 Thu Apr 13 00:09:45 2006 +++ llvm/lib/Target/X86/README.txt Fri Apr 14 02:24:04 2006 @@ -810,3 +810,8 @@ How about andps, andpd, and pand? Do we really care about the type of the packed elements? If not, why not always use the "ps" variants which are likely to be shorter. + +//===---------------------------------------------------------------------===// + +Make sure XMM registers are spilled to 128-bit locations (if not already) and +add vector SSE opcodes to X86RegisterInfo::foldMemoryOperand(). From evan.cheng at apple.com Fri Apr 14 02:26:55 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 14 Apr 2006 02:26:55 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp Message-ID: <200604140726.CAA17148@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86RegisterInfo.cpp updated: 1.136 -> 1.137 --- Log message: We were not adjusting the frame size to ensure proper alignment when alloca / vla are present in the function. This causes a crash when a leaf function allocates space on the stack used to store / load with 128-bit SSE instructions. --- Diffs of the changes: (+23 -30) X86RegisterInfo.cpp | 53 ++++++++++++++++++++++------------------------------ 1 files changed, 23 insertions(+), 30 deletions(-) Index: llvm/lib/Target/X86/X86RegisterInfo.cpp diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.136 llvm/lib/Target/X86/X86RegisterInfo.cpp:1.137 --- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.136 Mon Apr 10 02:21:31 2006 +++ llvm/lib/Target/X86/X86RegisterInfo.cpp Fri Apr 14 02:26:43 2006 @@ -573,17 +573,34 @@ // Get the number of bytes to allocate from the FrameInfo unsigned NumBytes = MFI->getStackSize(); + if (MFI->hasCalls() || MF.getFrameInfo()->hasVarSizedObjects()) { + // When we have no frame pointer, we reserve argument space for call sites + // in the function immediately on entry to the current function. This + // eliminates the need for add/sub ESP brackets around call sites. + // + if (!hasFP(MF)) + NumBytes += MFI->getMaxCallFrameSize(); + + // Round the size to a multiple of the alignment (don't forget the 4 byte + // offset though). + unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); + NumBytes = ((NumBytes+4)+Align-1)/Align*Align - 4; + } + + // Update frame info to pretend that this is part of the stack... + MFI->setStackSize(NumBytes); + + if (NumBytes) { // adjust stack pointer: ESP -= numbytes + unsigned Opc = NumBytes < 128 ? X86::SUB32ri8 : X86::SUB32ri; + MI = BuildMI(Opc, 1, X86::ESP,MachineOperand::UseAndDef).addImm(NumBytes); + MBB.insert(MBBI, MI); + } + if (hasFP(MF)) { // Get the offset of the stack slot for the EBP register... which is // guaranteed to be the last slot by processFunctionBeforeFrameFinalized. int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexBegin())+4; - if (NumBytes) { // adjust stack pointer: ESP -= numbytes - unsigned Opc = NumBytes < 128 ? X86::SUB32ri8 : X86::SUB32ri; - MI = BuildMI(Opc, 1, X86::ESP,MachineOperand::UseAndDef).addImm(NumBytes); - MBB.insert(MBBI, MI); - } - // Save EBP into the appropriate stack slot... MI = addRegOffset(BuildMI(X86::MOV32mr, 5), // mov [ESP-], EBP X86::ESP, EBPOffset+NumBytes).addReg(X86::EBP); @@ -596,30 +613,6 @@ MI = addRegOffset(BuildMI(X86::LEA32r, 5, X86::EBP), X86::ESP,NumBytes-4); MBB.insert(MBBI, MI); - - } else { - if (MFI->hasCalls()) { - // When we have no frame pointer, we reserve argument space for call sites - // in the function immediately on entry to the current function. This - // eliminates the need for add/sub ESP brackets around call sites. - // - NumBytes += MFI->getMaxCallFrameSize(); - - // Round the size to a multiple of the alignment (don't forget the 4 byte - // offset though). - unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); - NumBytes = ((NumBytes+4)+Align-1)/Align*Align - 4; - } - - // Update frame info to pretend that this is part of the stack... - MFI->setStackSize(NumBytes); - - if (NumBytes) { - // adjust stack pointer: ESP -= numbytes - unsigned Opc = NumBytes < 128 ? X86::SUB32ri8 : X86::SUB32ri; - MI= BuildMI(Opc, 1, X86::ESP, MachineOperand::UseAndDef).addImm(NumBytes); - MBB.insert(MBBI, MI); - } } } From evan.cheng at apple.com Fri Apr 14 02:43:25 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 14 Apr 2006 02:43:25 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/IntrinsicsX86.td Message-ID: <200604140743.CAA22302@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm: IntrinsicsX86.td updated: 1.27 -> 1.28 --- Log message: Misc. SSE2 intrinsics: clflush, lfench, mfence --- Diffs of the changes: (+6 -0) IntrinsicsX86.td | 6 ++++++ 1 files changed, 6 insertions(+) Index: llvm/include/llvm/IntrinsicsX86.td diff -u llvm/include/llvm/IntrinsicsX86.td:1.27 llvm/include/llvm/IntrinsicsX86.td:1.28 --- llvm/include/llvm/IntrinsicsX86.td:1.27 Thu Apr 13 20:39:53 2006 +++ llvm/include/llvm/IntrinsicsX86.td Fri Apr 14 02:43:12 2006 @@ -455,6 +455,12 @@ def int_x86_sse2_maskmov_dqu : GCCBuiltin<"__builtin_ia32_maskmovdqu">, Intrinsic<[llvm_void_ty, llvm_v16i8_ty, llvm_v16i8_ty, llvm_ptr_ty], [IntrWriteMem]>; + def int_x86_sse2_clflush : GCCBuiltin<"__builtin_ia32_clflush">, + Intrinsic<[llvm_void_ty, llvm_ptr_ty], [IntrWriteMem]>; + def int_x86_sse2_lfence : GCCBuiltin<"__builtin_ia32_lfence">, + Intrinsic<[llvm_void_ty], [IntrWriteMem]>; + def int_x86_sse2_mfence : GCCBuiltin<"__builtin_ia32_mfence">, + Intrinsic<[llvm_void_ty], [IntrWriteMem]>; } //===----------------------------------------------------------------------===// From evan.cheng at apple.com Fri Apr 14 02:43:25 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 14 Apr 2006 02:43:25 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td Message-ID: <200604140743.CAA22304@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrSSE.td updated: 1.88 -> 1.89 --- Log message: Misc. SSE2 intrinsics: clflush, lfench, mfence --- Diffs of the changes: (+11 -2) X86InstrSSE.td | 13 +++++++++++-- 1 files changed, 11 insertions(+), 2 deletions(-) Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.88 llvm/lib/Target/X86/X86InstrSSE.td:1.89 --- llvm/lib/Target/X86/X86InstrSSE.td:1.88 Thu Apr 13 20:39:53 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Fri Apr 14 02:43:12 2006 @@ -2002,12 +2002,21 @@ [(int_x86_sse2_movnt_i addr:$dst, R32:$src)]>, TB, Requires<[HasSSE2]>; -// Store fence +// Flush cache +def CLFLUSH : I<0xAE, MRM7m, (ops i8mem:$src), + "clflush $src", [(int_x86_sse2_clflush addr:$src)]>, + TB, Requires<[HasSSE2]>; + +// Load, store, and memory fence def SFENCE : I<0xAE, MRM7m, (ops), "sfence", [(int_x86_sse_sfence)]>, TB, Requires<[HasSSE1]>; +def LFENCE : I<0xAE, MRM5m, (ops), + "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>; +def MFENCE : I<0xAE, MRM6m, (ops), + "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>; // MXCSR register -def LDMXCSR : I<0xAE, MRM2m, (ops i32mem:$src), +def LDMXCSR : I<0xAE, MRM5m, (ops i32mem:$src), "ldmxcsr $src", [(int_x86_sse_ldmxcsr addr:$src)]>, TB, Requires<[HasSSE1]>; def STMXCSR : I<0xAE, MRM3m, (ops i32mem:$dst), From reid at x10sys.com Fri Apr 14 08:54:19 2006 From: reid at x10sys.com (Reid Spencer) Date: Fri, 14 Apr 2006 08:54:19 -0500 Subject: [llvm-commits] CVS: llvm/utils/NightlyTest.pl Message-ID: <200604141354.IAA26378@zion.cs.uiuc.edu> Changes in directory llvm/utils: NightlyTest.pl updated: 1.106 -> 1.107 --- Log message: Allow an option, -with-externals, to be specified that provides the location of the external tests. This turns into --with-externals option to configure. --- Diffs of the changes: (+4 -0) NightlyTest.pl | 4 ++++ 1 files changed, 4 insertions(+) Index: llvm/utils/NightlyTest.pl diff -u llvm/utils/NightlyTest.pl:1.106 llvm/utils/NightlyTest.pl:1.107 --- llvm/utils/NightlyTest.pl:1.106 Mon Mar 20 19:21:39 2006 +++ llvm/utils/NightlyTest.pl Fri Apr 14 08:53:56 2006 @@ -19,6 +19,7 @@ # LARGE_PROBLEM_SIZE enabled. # -noexternals Do not run the external tests (for cases where povray # or SPEC are not installed) +# -with-externals Specify a directory where the external tests are located. # -nodejagnu Do not run feature or regression tests # -parallel Run two parallel jobs with GNU Make. # -release Build an LLVM Release version @@ -310,6 +311,9 @@ if (/^-f2c$/) { $CONFIGUREARGS .= " --with-f2c=$ARGV[0]"; shift; next; } + if (/^-with-externals/) { + $CONFIGUREARGS .= "--with-externals=$ARGV[0]"; shift; next + } if (/^-gnuplotscript$/) { $PlotScriptFilename = $ARGV[0]; shift; next; } if (/^-templatefile$/) { $Template = $ARGV[0]; shift; next; } if (/^-gccpath/) { From reid at x10sys.com Fri Apr 14 09:12:00 2006 From: reid at x10sys.com (Reid Spencer) Date: Fri, 14 Apr 2006 09:12:00 -0500 Subject: [llvm-commits] CVS: llvm/docs/ProgrammersManual.html Message-ID: <200604141412.JAA26593@zion.cs.uiuc.edu> Changes in directory llvm/docs: ProgrammersManual.html updated: 1.90 -> 1.91 --- Log message: Correct the Superclasses list for GlobalVariable and Function to indicate that they are "Constant" as they derive from GlobalValue. Also, fix some of the wording where it mentions this. Patch inspired by Nai Xia. --- Diffs of the changes: (+21 -17) ProgrammersManual.html | 38 +++++++++++++++++++++----------------- 1 files changed, 21 insertions(+), 17 deletions(-) Index: llvm/docs/ProgrammersManual.html diff -u llvm/docs/ProgrammersManual.html:1.90 llvm/docs/ProgrammersManual.html:1.91 --- llvm/docs/ProgrammersManual.html:1.90 Mon Mar 13 23:39:39 2006 +++ llvm/docs/ProgrammersManual.html Fri Apr 14 09:11:48 2006 @@ -1710,8 +1710,8 @@ href="/doxygen/GlobalValue_8h-source.html">llvm/GlobalValue.h"
    doxygen info: GlobalValue Class
    -Superclasses: User, Value

    +Superclasses: Constant, +User, Value

    Global values (GlobalVariables or Functions) are the only LLVM values that are @@ -1778,15 +1778,17 @@

    #include "llvm/Function.h"
    doxygen info: Function Class
    -Superclasses: GlobalValue, User, Value

    +Superclasses: GlobalValue, +Constant, +User, +Value

    The Function class represents a single procedure in LLVM. It is actually one of the more complex classes in the LLVM heirarchy because it must keep track of a large amount of data. The Function class keeps track -of a list of BasicBlocks, a list of formal Arguments, and a SymbolTable.

    +of a list of BasicBlocks, a list of formal +Arguments, and a +SymbolTable.

    The list of BasicBlocks is the most commonly used part of Function objects. The list imposes an implicit @@ -1915,20 +1917,22 @@ href="/doxygen/GlobalVariable_8h-source.html">llvm/GlobalVariable.h"
    doxygen info: GlobalVariable -Class
    Superclasses: GlobalValue, User, Value

    + Class
    +Superclasses: GlobalValue, +Constant, +User, +Value

    Global variables are represented with the (suprise suprise) GlobalVariable class. Like functions, GlobalVariables are also subclasses of GlobalValue, and as such are always referenced by their address (global values must live in memory, so their -"name" refers to their address). See GlobalValue for more on this. Global variables -may have an initial value (which must be a Constant), and if they have an initializer, they -may be marked as "constant" themselves (indicating that their contents never -change at runtime).

    - +"name" refers to their constant address). See +GlobalValue for more on this. Global +variables may have an initial value (which must be a +Constant), and if they have an initializer, +they may be marked as "constant" themselves (indicating that their contents +never change at runtime).

    @@ -2277,7 +2281,7 @@ Dinakar Dhurjati and Chris Lattner
    The LLVM Compiler Infrastructure
    - Last modified: $Date: 2006/03/14 05:39:39 $ + Last modified: $Date: 2006/04/14 14:11:48 $ From reid at x10sys.com Fri Apr 14 09:20:07 2006 From: reid at x10sys.com (Reid Spencer) Date: Fri, 14 Apr 2006 09:20:07 -0500 Subject: [llvm-commits] [release_17] CVS: llvm/docs/ProgrammersManual.html Message-ID: <200604141420.JAA26673@zion.cs.uiuc.edu> Changes in directory llvm/docs: ProgrammersManual.html updated: 1.90 -> 1.90.2.1 --- Log message: Include corrected documentation on class hierarchy of GlobalValue (derived from constant). --- Diffs of the changes: (+21 -17) ProgrammersManual.html | 38 +++++++++++++++++++++----------------- 1 files changed, 21 insertions(+), 17 deletions(-) Index: llvm/docs/ProgrammersManual.html diff -u llvm/docs/ProgrammersManual.html:1.90 llvm/docs/ProgrammersManual.html:1.90.2.1 --- llvm/docs/ProgrammersManual.html:1.90 Mon Mar 13 23:39:39 2006 +++ llvm/docs/ProgrammersManual.html Fri Apr 14 09:19:55 2006 @@ -1710,8 +1710,8 @@ href="/doxygen/GlobalValue_8h-source.html">llvm/GlobalValue.h"
    doxygen info: GlobalValue Class
    -Superclasses: User, Value

    +Superclasses: Constant, +User, Value

    Global values (GlobalVariables or Functions) are the only LLVM values that are @@ -1778,15 +1778,17 @@

    #include "llvm/Function.h"
    doxygen info: Function Class
    -Superclasses: GlobalValue, User, Value

    +Superclasses: GlobalValue, +Constant, +User, +Value

    The Function class represents a single procedure in LLVM. It is actually one of the more complex classes in the LLVM heirarchy because it must keep track of a large amount of data. The Function class keeps track -of a list of BasicBlocks, a list of formal Arguments, and a SymbolTable.

    +of a list of BasicBlocks, a list of formal +Arguments, and a +SymbolTable.

    The list of BasicBlocks is the most commonly used part of Function objects. The list imposes an implicit @@ -1915,20 +1917,22 @@ href="/doxygen/GlobalVariable_8h-source.html">llvm/GlobalVariable.h"
    doxygen info: GlobalVariable -Class
    Superclasses: GlobalValue, User, Value

    + Class
    +Superclasses: GlobalValue, +Constant, +User, +Value

    Global variables are represented with the (suprise suprise) GlobalVariable class. Like functions, GlobalVariables are also subclasses of GlobalValue, and as such are always referenced by their address (global values must live in memory, so their -"name" refers to their address). See GlobalValue for more on this. Global variables -may have an initial value (which must be a Constant), and if they have an initializer, they -may be marked as "constant" themselves (indicating that their contents never -change at runtime).

    - +"name" refers to their constant address). See +GlobalValue for more on this. Global +variables may have an initial value (which must be a +Constant), and if they have an initializer, +they may be marked as "constant" themselves (indicating that their contents +never change at runtime).

    @@ -2277,7 +2281,7 @@ Dinakar Dhurjati and Chris Lattner
    The LLVM Compiler Infrastructure
    - Last modified: $Date: 2006/03/14 05:39:39 $ + Last modified: $Date: 2006/04/14 14:19:55 $ From tbrethou at cs.uiuc.edu Fri Apr 14 14:07:54 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Fri, 14 Apr 2006 14:07:54 -0500 Subject: [llvm-commits] CVS: llvm/docs/LangRef.html Message-ID: <200604141907.OAA03753@zion.cs.uiuc.edu> Changes in directory llvm/docs: LangRef.html updated: 1.147 -> 1.148 --- Log message: Removing unimplemented vector instructions from language referrence. --- Diffs of the changes: (+1 -192) LangRef.html | 193 ----------------------------------------------------------- 1 files changed, 1 insertion(+), 192 deletions(-) Index: llvm/docs/LangRef.html diff -u llvm/docs/LangRef.html:1.147 llvm/docs/LangRef.html:1.148 --- llvm/docs/LangRef.html:1.147 Sat Apr 8 18:07:04 2006 +++ llvm/docs/LangRef.html Fri Apr 14 14:07:42 2006 @@ -96,9 +96,6 @@
  • 'extractelement' Instruction
  • 'insertelement' Instruction
  • 'shufflevector' Instruction
    • -
  • 'vsetint' Instruction
    • -
  • 'vsetfp' Instruction
    • -
  • 'vselect' Instruction
  • Memory Access Operations @@ -2060,194 +2057,6 @@ - - -
    'vsetint' -Instruction
    -
    -
    Syntax:
    -
    <result> = vsetint <op>, <n x <ty>> <var1>, <var2>   ; yields <n x bool>
-
    - -
    Overview:
    - -

    The 'vsetint' instruction takes two integer vectors and -returns a vector of boolean values representing, at each position, the -result of the comparison between the values at that position in the -two operands.

    - -
    Arguments:
    - -

    The arguments to a 'vsetint' instruction are a comparison -operation and two value arguments. The value arguments must be of integral packed type, -and they must have identical types. The operation argument must be -one of eq, ne, slt, sgt, -sle, sge, ult, ugt, ule, -uge, true, and false. The result is a -packed bool value with the same length as each operand.

    - -
    Semantics:
    - -

    The following table shows the semantics of 'vsetint'. For -each position of the result, the comparison is done on the -corresponding positions of the two value arguments. Note that the -signedness of the comparison depends on the comparison opcode and -not on the signedness of the value operands. E.g., vsetint -slt <4 x unsigned> %x, %y does an elementwise signed -comparison of %x and %y.

    - - - - - - - - - - - - - - - - - -
    OperationResult is true iffComparison is
    eqvar1 == var2--
    nevar1 != var2--
    sltvar1 < var2signed
    sgtvar1 > var2signed
    slevar1 <= var2signed
    sgevar1 >= var2signed
    ultvar1 < var2unsigned
    ugtvar1 > var2unsigned
    ulevar1 <= var2unsigned
    ugevar1 >= var2unsigned
    truealways--
    falsenever--
    - -
    Example:
    -
      <result> = vsetint eq <2 x int> <int 0, int 1>, <int 1, int 0>      ; yields {<2 x bool>}:result = false, false
-  <result> = vsetint ne <2 x int> <int 0, int 1>, <int 1, int 0>      ; yields {<2 x bool>}:result = true, true
-  <result> = vsetint slt <2 x int> <int 0, int 1>, <int 1, int 0>      ; yields {<2 x bool>}:result = true, false
-  <result> = vsetint sgt <2 x int> <int 0, int 1>, <int 1, int 0>      ; yields {<2 x bool>}:result = false, true
-  <result> = vsetint sle <2 x int> <int 0, int 1>, <int 1, int 0>      ; yields {<2 x bool>}:result = true, false
-  <result> = vsetint sge <2 x int> <int 0, int 1>, <int 1, int 0>      ; yields {<2 x bool>}:result = false, true
-
    -
    - - -
    'vsetfp' -Instruction
    -
    -
    Syntax:
    -
    <result> = vsetfp <op>, <n x <ty>> <var1>, <var2>   ; yields <n x bool>
-
    - -
    Overview:
    - -

    The 'vsetfp' instruction takes two floating point vector -arguments and returns a vector of boolean values representing, at each -position, the result of the comparison between the values at that -position in the two operands.

    - -
    Arguments:
    - -

    The arguments to a 'vsetfp' instruction are a comparison -operation and two value arguments. The value arguments must be of floating point packed -type, and they must have identical types. The operation argument must -be one of eq, ne, lt, gt, -le, ge, oeq, one, olt, -ogt, ole, oge, ueq, une, -ult, ugt, ule, uge, o, -u, true, and false. The result is a packed -bool value with the same length as each operand.

    - -
    Semantics:
    - -

    The following table shows the semantics of 'vsetfp' for -floating point types. If either operand is a floating point Not a -Number (NaN) value, the operation is unordered, and the value in the -first column below is produced at that position. Otherwise, the -operation is ordered, and the value in the second column is -produced.

    - - - - - - - - - - - - - - - - - - - - - - - - - - - -
    OperationIf unorderedOtherwise true iff
    equndefinedvar1 == var2
    neundefinedvar1 != var2
    ltundefinedvar1 < var2
    gtundefinedvar1 > var2
    leundefinedvar1 <= var2
    geundefinedvar1 >= var2
    oeqfalsevar1 == var2
    onefalsevar1 != var2
    oltfalsevar1 < var2
    ogtfalsevar1 > var2
    olefalsevar1 <= var2
    ogefalsevar1 >= var2
    ueqtruevar1 == var2
    unetruevar1 != var2
    ulttruevar1 < var2
    ugttruevar1 > var2
    uletruevar1 <= var2
    ugetruevar1 >= var2
    ofalsealways
    utruenever
    truetruealways
    falsefalsenever
    - -
    Example:
    -
      <result> = vsetfp eq <2 x float> <float 0.0, float 1.0>, <float 1.0, float 0.0>      ; yields {<2 x bool>}:result = false, false
-  <result> = vsetfp ne <2 x float> <float 0.0, float 1.0>, <float 1.0, float 0.0>      ; yields {<2 x bool>}:result = true, true
-  <result> = vsetfp lt <2 x float> <float 0.0, float 1.0>, <float 1.0, float 0.0>      ; yields {<2 x bool>}:result = true, false
-  <result> = vsetfp gt <2 x float> <float 0.0, float 1.0>, <float 1.0, float 0.0>      ; yields {<2 x bool>}:result = false, true
-  <result> = vsetfp le <2 x float> <float 0.0, float 1.0>, <float 1.0, float 0.0>      ; yields {<2 x bool>}:result = true, false
-  <result> = vsetfp ge <2 x float> <float 0.0, float 1.0>, <float 1.0, float 0.0>      ; yields {<2 x bool>}:result = false, true
-
    -
    - - -
    - 'vselect' Instruction -
    - -
    - -
    Syntax:
    - -
    -  <result> = vselect <n x bool> <cond>, <n x <ty>> <val1>, <n x <ty>> <val2> ; yields <n x <ty>>
-
    - -
    Overview:
    - -

    -The 'vselect' instruction chooses one value at each position -of a vector based on a condition. -

    - - -
    Arguments:
    - -

    -The 'vselect' instruction requires a packed bool value indicating the -condition at each vector position, and two values of the same packed -type. All three operands must have the same length. The type of the -result is the same as the type of the two value operands.

    - -
    Semantics:
    - -

    -At each position where the bool vector is true, that position -of the result gets its value from the first value argument; otherwise, -it gets its value from the second value argument. -

    - -
    Example:
    - -
    -  %X = vselect bool <2 x bool> <bool true, bool false>, <2 x ubyte> <ubyte 17, ubyte 17>, 
-    <2 x ubyte> <ubyte 42, ubyte 42>      ; yields <2 x ubyte>:17, 42
-
    -
    - - -
    Memory Access Operations @@ -3817,7 +3626,7 @@ Chris Lattner
    The LLVM Compiler Infrastructure
    - Last modified: $Date: 2006/04/08 23:07:04 $ + Last modified: $Date: 2006/04/14 19:07:42 $ From tbrethou at cs.uiuc.edu Fri Apr 14 14:24:45 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Fri, 14 Apr 2006 14:24:45 -0500 Subject: [llvm-commits] CVS: llvm/docs/LangRef.html Message-ID: <200604141924.OAA03951@zion.cs.uiuc.edu> Changes in directory llvm/docs: LangRef.html updated: 1.148 -> 1.149 --- Log message: Adding back vector instructions to keep in mainline. --- Diffs of the changes: (+192 -1) LangRef.html | 193 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 files changed, 192 insertions(+), 1 deletion(-) Index: llvm/docs/LangRef.html diff -u llvm/docs/LangRef.html:1.148 llvm/docs/LangRef.html:1.149 --- llvm/docs/LangRef.html:1.148 Fri Apr 14 14:07:42 2006 +++ llvm/docs/LangRef.html Fri Apr 14 14:24:33 2006 @@ -96,6 +96,9 @@
  • 'extractelement' Instruction
  • 'insertelement' Instruction
  • 'shufflevector' Instruction
    • +
  • 'vsetint' Instruction
    • +
  • 'vsetfp' Instruction
    • +
  • 'vselect' Instruction
  • Memory Access Operations @@ -2057,6 +2060,194 @@ + + +
    'vsetint' +Instruction
    +
    +
    Syntax:
    +
    <result> = vsetint <op>, <n x <ty>> <var1>, <var2>   ; yields <n x bool>
+
    + +
    Overview:
    + +

    The 'vsetint' instruction takes two integer vectors and +returns a vector of boolean values representing, at each position, the +result of the comparison between the values at that position in the +two operands.

    + +
    Arguments:
    + +

    The arguments to a 'vsetint' instruction are a comparison +operation and two value arguments. The value arguments must be of integral packed type, +and they must have identical types. The operation argument must be +one of eq, ne, slt, sgt, +sle, sge, ult, ugt, ule, +uge, true, and false. The result is a +packed bool value with the same length as each operand.

    + +
    Semantics:
    + +

    The following table shows the semantics of 'vsetint'. For +each position of the result, the comparison is done on the +corresponding positions of the two value arguments. Note that the +signedness of the comparison depends on the comparison opcode and +not on the signedness of the value operands. E.g., vsetint +slt <4 x unsigned> %x, %y does an elementwise signed +comparison of %x and %y.

    + + + + + + + + + + + + + + + + + +
    OperationResult is true iffComparison is
    eqvar1 == var2--
    nevar1 != var2--
    sltvar1 < var2signed
    sgtvar1 > var2signed
    slevar1 <= var2signed
    sgevar1 >= var2signed
    ultvar1 < var2unsigned
    ugtvar1 > var2unsigned
    ulevar1 <= var2unsigned
    ugevar1 >= var2unsigned
    truealways--
    falsenever--
    + +
    Example:
    +
      <result> = vsetint eq <2 x int> <int 0, int 1>, <int 1, int 0>      ; yields {<2 x bool>}:result = false, false
+  <result> = vsetint ne <2 x int> <int 0, int 1>, <int 1, int 0>      ; yields {<2 x bool>}:result = true, true
+  <result> = vsetint slt <2 x int> <int 0, int 1>, <int 1, int 0>      ; yields {<2 x bool>}:result = true, false
+  <result> = vsetint sgt <2 x int> <int 0, int 1>, <int 1, int 0>      ; yields {<2 x bool>}:result = false, true
+  <result> = vsetint sle <2 x int> <int 0, int 1>, <int 1, int 0>      ; yields {<2 x bool>}:result = true, false
+  <result> = vsetint sge <2 x int> <int 0, int 1>, <int 1, int 0>      ; yields {<2 x bool>}:result = false, true
+
    +
    + + +
    'vsetfp' +Instruction
    +
    +
    Syntax:
    +
    <result> = vsetfp <op>, <n x <ty>> <var1>, <var2>   ; yields <n x bool>
+
    + +
    Overview:
    + +

    The 'vsetfp' instruction takes two floating point vector +arguments and returns a vector of boolean values representing, at each +position, the result of the comparison between the values at that +position in the two operands.

    + +
    Arguments:
    + +

    The arguments to a 'vsetfp' instruction are a comparison +operation and two value arguments. The value arguments must be of floating point packed +type, and they must have identical types. The operation argument must +be one of eq, ne, lt, gt, +le, ge, oeq, one, olt, +ogt, ole, oge, ueq, une, +ult, ugt, ule, uge, o, +u, true, and false. The result is a packed +bool value with the same length as each operand.

    + +
    Semantics:
    + +

    The following table shows the semantics of 'vsetfp' for +floating point types. If either operand is a floating point Not a +Number (NaN) value, the operation is unordered, and the value in the +first column below is produced at that position. Otherwise, the +operation is ordered, and the value in the second column is +produced.

    + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    OperationIf unorderedOtherwise true iff
    equndefinedvar1 == var2
    neundefinedvar1 != var2
    ltundefinedvar1 < var2
    gtundefinedvar1 > var2
    leundefinedvar1 <= var2
    geundefinedvar1 >= var2
    oeqfalsevar1 == var2
    onefalsevar1 != var2
    oltfalsevar1 < var2
    ogtfalsevar1 > var2
    olefalsevar1 <= var2
    ogefalsevar1 >= var2
    ueqtruevar1 == var2
    unetruevar1 != var2
    ulttruevar1 < var2
    ugttruevar1 > var2
    uletruevar1 <= var2
    ugetruevar1 >= var2
    ofalsealways
    utruenever
    truetruealways
    falsefalsenever
    + +
    Example:
    +
      <result> = vsetfp eq <2 x float> <float 0.0, float 1.0>, <float 1.0, float 0.0>      ; yields {<2 x bool>}:result = false, false
+  <result> = vsetfp ne <2 x float> <float 0.0, float 1.0>, <float 1.0, float 0.0>      ; yields {<2 x bool>}:result = true, true
+  <result> = vsetfp lt <2 x float> <float 0.0, float 1.0>, <float 1.0, float 0.0>      ; yields {<2 x bool>}:result = true, false
+  <result> = vsetfp gt <2 x float> <float 0.0, float 1.0>, <float 1.0, float 0.0>      ; yields {<2 x bool>}:result = false, true
+  <result> = vsetfp le <2 x float> <float 0.0, float 1.0>, <float 1.0, float 0.0>      ; yields {<2 x bool>}:result = true, false
+  <result> = vsetfp ge <2 x float> <float 0.0, float 1.0>, <float 1.0, float 0.0>      ; yields {<2 x bool>}:result = false, true
+
    +
    + + +
    + 'vselect' Instruction +
    + +
    + +
    Syntax:
    + +
    +  <result> = vselect <n x bool> <cond>, <n x <ty>> <val1>, <n x <ty>> <val2> ; yields <n x <ty>>
+
    + +
    Overview:
    + +

    +The 'vselect' instruction chooses one value at each position +of a vector based on a condition. +

    + + +
    Arguments:
    + +

    +The 'vselect' instruction requires a packed bool value indicating the +condition at each vector position, and two values of the same packed +type. All three operands must have the same length. The type of the +result is the same as the type of the two value operands.

    + +
    Semantics:
    + +

    +At each position where the bool vector is true, that position +of the result gets its value from the first value argument; otherwise, +it gets its value from the second value argument. +

    + +
    Example:
    + +
    +  %X = vselect bool <2 x bool> <bool true, bool false>, <2 x ubyte> <ubyte 17, ubyte 17>, 
+    <2 x ubyte> <ubyte 42, ubyte 42>      ; yields <2 x ubyte>:17, 42
+
    +
    + + +
    Memory Access Operations @@ -3626,7 +3817,7 @@ Chris Lattner
    The LLVM Compiler Infrastructure
    - Last modified: $Date: 2006/04/14 19:07:42 $ + Last modified: $Date: 2006/04/14 19:24:33 $ From tbrethou at cs.uiuc.edu Fri Apr 14 14:31:19 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Fri, 14 Apr 2006 14:31:19 -0500 Subject: [llvm-commits] [release_17] CVS: llvm/docs/LangRef.html Message-ID: <200604141931.OAA04045@zion.cs.uiuc.edu> Changes in directory llvm/docs: LangRef.html updated: 1.147 -> 1.147.2.1 --- Log message: Removing unimplemented vector operations for the release docs. --- Diffs of the changes: (+1 -192) LangRef.html | 193 ----------------------------------------------------------- 1 files changed, 1 insertion(+), 192 deletions(-) Index: llvm/docs/LangRef.html diff -u llvm/docs/LangRef.html:1.147 llvm/docs/LangRef.html:1.147.2.1 --- llvm/docs/LangRef.html:1.147 Sat Apr 8 18:07:04 2006 +++ llvm/docs/LangRef.html Fri Apr 14 14:31:07 2006 @@ -96,9 +96,6 @@
  • 'extractelement' Instruction
  • 'insertelement' Instruction
  • 'shufflevector' Instruction
    • -
  • 'vsetint' Instruction
    • -
  • 'vsetfp' Instruction
    • -
  • 'vselect' Instruction
  • Memory Access Operations @@ -2060,194 +2057,6 @@ - - -
    'vsetint' -Instruction
    -
    -
    Syntax:
    -
    <result> = vsetint <op>, <n x <ty>> <var1>, <var2>   ; yields <n x bool>
-
    - -
    Overview:
    - -

    The 'vsetint' instruction takes two integer vectors and -returns a vector of boolean values representing, at each position, the -result of the comparison between the values at that position in the -two operands.

    - -
    Arguments:
    - -

    The arguments to a 'vsetint' instruction are a comparison -operation and two value arguments. The value arguments must be of integral packed type, -and they must have identical types. The operation argument must be -one of eq, ne, slt, sgt, -sle, sge, ult, ugt, ule, -uge, true, and false. The result is a -packed bool value with the same length as each operand.

    - -
    Semantics:
    - -

    The following table shows the semantics of 'vsetint'. For -each position of the result, the comparison is done on the -corresponding positions of the two value arguments. Note that the -signedness of the comparison depends on the comparison opcode and -not on the signedness of the value operands. E.g., vsetint -slt <4 x unsigned> %x, %y does an elementwise signed -comparison of %x and %y.

    - - - - - - - - - - - - - - - - - -
    OperationResult is true iffComparison is
    eqvar1 == var2--
    nevar1 != var2--
    sltvar1 < var2signed
    sgtvar1 > var2signed
    slevar1 <= var2signed
    sgevar1 >= var2signed
    ultvar1 < var2unsigned
    ugtvar1 > var2unsigned
    ulevar1 <= var2unsigned
    ugevar1 >= var2unsigned
    truealways--
    falsenever--
    - -
    Example:
    -
      <result> = vsetint eq <2 x int> <int 0, int 1>, <int 1, int 0>      ; yields {<2 x bool>}:result = false, false
-  <result> = vsetint ne <2 x int> <int 0, int 1>, <int 1, int 0>      ; yields {<2 x bool>}:result = true, true
-  <result> = vsetint slt <2 x int> <int 0, int 1>, <int 1, int 0>      ; yields {<2 x bool>}:result = true, false
-  <result> = vsetint sgt <2 x int> <int 0, int 1>, <int 1, int 0>      ; yields {<2 x bool>}:result = false, true
-  <result> = vsetint sle <2 x int> <int 0, int 1>, <int 1, int 0>      ; yields {<2 x bool>}:result = true, false
-  <result> = vsetint sge <2 x int> <int 0, int 1>, <int 1, int 0>      ; yields {<2 x bool>}:result = false, true
-
    -
    - - -
    'vsetfp' -Instruction
    -
    -
    Syntax:
    -
    <result> = vsetfp <op>, <n x <ty>> <var1>, <var2>   ; yields <n x bool>
-
    - -
    Overview:
    - -

    The 'vsetfp' instruction takes two floating point vector -arguments and returns a vector of boolean values representing, at each -position, the result of the comparison between the values at that -position in the two operands.

    - -
    Arguments:
    - -

    The arguments to a 'vsetfp' instruction are a comparison -operation and two value arguments. The value arguments must be of floating point packed -type, and they must have identical types. The operation argument must -be one of eq, ne, lt, gt, -le, ge, oeq, one, olt, -ogt, ole, oge, ueq, une, -ult, ugt, ule, uge, o, -u, true, and false. The result is a packed -bool value with the same length as each operand.

    - -
    Semantics:
    - -

    The following table shows the semantics of 'vsetfp' for -floating point types. If either operand is a floating point Not a -Number (NaN) value, the operation is unordered, and the value in the -first column below is produced at that position. Otherwise, the -operation is ordered, and the value in the second column is -produced.

    - - - - - - - - - - - - - - - - - - - - - - - - - - - -
    OperationIf unorderedOtherwise true iff
    equndefinedvar1 == var2
    neundefinedvar1 != var2
    ltundefinedvar1 < var2
    gtundefinedvar1 > var2
    leundefinedvar1 <= var2
    geundefinedvar1 >= var2
    oeqfalsevar1 == var2
    onefalsevar1 != var2
    oltfalsevar1 < var2
    ogtfalsevar1 > var2
    olefalsevar1 <= var2
    ogefalsevar1 >= var2
    ueqtruevar1 == var2
    unetruevar1 != var2
    ulttruevar1 < var2
    ugttruevar1 > var2
    uletruevar1 <= var2
    ugetruevar1 >= var2
    ofalsealways
    utruenever
    truetruealways
    falsefalsenever
    - -
    Example:
    -
      <result> = vsetfp eq <2 x float> <float 0.0, float 1.0>, <float 1.0, float 0.0>      ; yields {<2 x bool>}:result = false, false
-  <result> = vsetfp ne <2 x float> <float 0.0, float 1.0>, <float 1.0, float 0.0>      ; yields {<2 x bool>}:result = true, true
-  <result> = vsetfp lt <2 x float> <float 0.0, float 1.0>, <float 1.0, float 0.0>      ; yields {<2 x bool>}:result = true, false
-  <result> = vsetfp gt <2 x float> <float 0.0, float 1.0>, <float 1.0, float 0.0>      ; yields {<2 x bool>}:result = false, true
-  <result> = vsetfp le <2 x float> <float 0.0, float 1.0>, <float 1.0, float 0.0>      ; yields {<2 x bool>}:result = true, false
-  <result> = vsetfp ge <2 x float> <float 0.0, float 1.0>, <float 1.0, float 0.0>      ; yields {<2 x bool>}:result = false, true
-
    -
    - - -
    - 'vselect' Instruction -
    - -
    - -
    Syntax:
    - -
    -  <result> = vselect <n x bool> <cond>, <n x <ty>> <val1>, <n x <ty>> <val2> ; yields <n x <ty>>
-
    - -
    Overview:
    - -

    -The 'vselect' instruction chooses one value at each position -of a vector based on a condition. -

    - - -
    Arguments:
    - -

    -The 'vselect' instruction requires a packed bool value indicating the -condition at each vector position, and two values of the same packed -type. All three operands must have the same length. The type of the -result is the same as the type of the two value operands.

    - -
    Semantics:
    - -

    -At each position where the bool vector is true, that position -of the result gets its value from the first value argument; otherwise, -it gets its value from the second value argument. -

    - -
    Example:
    - -
    -  %X = vselect bool <2 x bool> <bool true, bool false>, <2 x ubyte> <ubyte 17, ubyte 17>, 
-    <2 x ubyte> <ubyte 42, ubyte 42>      ; yields <2 x ubyte>:17, 42
-
    -
    - - -
    Memory Access Operations @@ -3817,7 +3626,7 @@ Chris Lattner
    The LLVM Compiler Infrastructure
    - Last modified: $Date: 2006/04/08 23:07:04 $ + Last modified: $Date: 2006/04/14 19:31:07 $ From tbrethou at cs.uiuc.edu Fri Apr 14 14:34:24 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Fri, 14 Apr 2006 14:34:24 -0500 Subject: [llvm-commits] [release_17] CVS: llvm/test/Regression/CFrontend/2005-12-04-DeclarationLineNumbers.c Message-ID: <200604141934.OAA04125@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CFrontend: 2005-12-04-DeclarationLineNumbers.c updated: 1.2 -> 1.2.2.1 --- Log message: Merging in fix from mainline --- Diffs of the changes: (+3 -1) 2005-12-04-DeclarationLineNumbers.c | 4 +++- 1 files changed, 3 insertions(+), 1 deletion(-) Index: llvm/test/Regression/CFrontend/2005-12-04-DeclarationLineNumbers.c diff -u llvm/test/Regression/CFrontend/2005-12-04-DeclarationLineNumbers.c:1.2 llvm/test/Regression/CFrontend/2005-12-04-DeclarationLineNumbers.c:1.2.2.1 --- llvm/test/Regression/CFrontend/2005-12-04-DeclarationLineNumbers.c:1.2 Thu Apr 13 12:35:36 2006 +++ llvm/test/Regression/CFrontend/2005-12-04-DeclarationLineNumbers.c Fri Apr 14 14:34:11 2006 @@ -1,7 +1,6 @@ // RUN: %llvmgcc %s -S -g -o - | grep 'llvm.dbg.stoppoint.*uint 14' // PR664: ensure that line #'s are emitted for declarations -// XFAIL: llvmgcc4 short test(short br_data_0, short br_data_1, @@ -21,3 +20,6 @@ return s0734 + s1625; } + +// FIXME: PR735 +// XFAIL: llvmgcc4 From tbrethou at cs.uiuc.edu Fri Apr 14 14:47:42 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Fri, 14 Apr 2006 14:47:42 -0500 Subject: [llvm-commits] [release_17] CVS: llvm/test/Regression/CFrontend/2004-02-20-StaticRedeclare.c.tr Message-ID: <200604141947.OAA04182@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CFrontend: 2004-02-20-StaticRedeclare.c.tr (r1.4) removed --- Log message: Removing from release. --- Diffs of the changes: (+0 -0) 0 files changed From tbrethou at cs.uiuc.edu Fri Apr 14 14:48:26 2006 From: tbrethou at cs.uiuc.edu (Tanya Brethour) Date: Fri, 14 Apr 2006 14:48:26 -0500 Subject: [llvm-commits] [release_17] CVS: llvm/test/Regression/CodeGen/Generic/2006-04-11-vecload.ll Message-ID: <200604141948.OAA04196@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/Generic: 2006-04-11-vecload.ll (r1.1) removed --- Log message: Removing from release --- Diffs of the changes: (+0 -0) 0 files changed From lattner at cs.uiuc.edu Fri Apr 14 16:42:06 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 14 Apr 2006 16:42:06 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/ScalarRepl/vector_promote.ll Message-ID: <200604142142.QAA19793@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/ScalarRepl: vector_promote.ll added (r1.1) --- Log message: New testcase, checking to see we can turn this code: void test(vector float *F, float f) { vector float G = *F + *F; *((float*)&G) = f; *F = G + G; } void test2(vector float *F, float f) { vector float G = *F + *F; ((float*)&G)[2] = f; *F = G + G; } void test3(vector float *F, float *f) { vector float G = *F + *F; *f = ((float*)&G)[2]; } void test4(vector float *F, float *f) { vector float G = *F + *F; *f = *((float*)&G); } into insert/extract element operations with no memory traffic. --- Diffs of the changes: (+56 -0) vector_promote.ll | 56 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 56 insertions(+) Index: llvm/test/Regression/Transforms/ScalarRepl/vector_promote.ll diff -c /dev/null llvm/test/Regression/Transforms/ScalarRepl/vector_promote.ll:1.1 *** /dev/null Fri Apr 14 16:42:04 2006 --- llvm/test/Regression/Transforms/ScalarRepl/vector_promote.ll Fri Apr 14 16:41:54 2006 *************** *** 0 **** --- 1,56 ---- + + ; RUN: llvm-as < %s | opt -scalarrepl -disable-output && + ; RUN: llvm-as < %s | opt -scalarrepl | llvm-dis | not grep alloca + + void %test(<4 x float>* %F, float %f) { + entry: + %G = alloca <4 x float>, align 16 ; <<4 x float>*> [#uses=3] + %tmp = load <4 x float>* %F ; <<4 x float>> [#uses=2] + %tmp3 = add <4 x float> %tmp, %tmp ; <<4 x float>> [#uses=1] + store <4 x float> %tmp3, <4 x float>* %G + %G = getelementptr <4 x float>* %G, int 0, int 0 ; [#uses=1] + store float %f, float* %G + %tmp4 = load <4 x float>* %G ; <<4 x float>> [#uses=2] + %tmp6 = add <4 x float> %tmp4, %tmp4 ; <<4 x float>> [#uses=1] + store <4 x float> %tmp6, <4 x float>* %F + ret void + } + + void %test2(<4 x float>* %F, float %f) { + entry: + %G = alloca <4 x float>, align 16 ; <<4 x float>*> [#uses=3] + %tmp = load <4 x float>* %F ; <<4 x float>> [#uses=2] + %tmp3 = add <4 x float> %tmp, %tmp ; <<4 x float>> [#uses=1] + store <4 x float> %tmp3, <4 x float>* %G + %tmp = getelementptr <4 x float>* %G, int 0, int 2 ; [#uses=1] + store float %f, float* %tmp + %tmp4 = load <4 x float>* %G ; <<4 x float>> [#uses=2] + %tmp6 = add <4 x float> %tmp4, %tmp4 ; <<4 x float>> [#uses=1] + store <4 x float> %tmp6, <4 x float>* %F + ret void + } + + void %test3(<4 x float>* %F, float* %f) { + entry: + %G = alloca <4 x float>, align 16 ; <<4 x float>*> [#uses=2] + %tmp = load <4 x float>* %F ; <<4 x float>> [#uses=2] + %tmp3 = add <4 x float> %tmp, %tmp ; <<4 x float>> [#uses=1] + store <4 x float> %tmp3, <4 x float>* %G + %tmp = getelementptr <4 x float>* %G, int 0, int 2 ; [#uses=1] + %tmp = load float* %tmp ; [#uses=1] + store float %tmp, float* %f + ret void + } + + void %test4(<4 x float>* %F, float* %f) { + entry: + %G = alloca <4 x float>, align 16 ; <<4 x float>*> [#uses=2] + %tmp = load <4 x float>* %F ; <<4 x float>> [#uses=2] + %tmp3 = add <4 x float> %tmp, %tmp ; <<4 x float>> [#uses=1] + store <4 x float> %tmp3, <4 x float>* %G + %G = getelementptr <4 x float>* %G, int 0, int 0 ; [#uses=1] + %tmp = load float* %G ; [#uses=1] + store float %tmp, float* %f + ret void + } + From lattner at cs.uiuc.edu Fri Apr 14 16:42:53 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 14 Apr 2006 16:42:53 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp Message-ID: <200604142142.QAA19828@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: ScalarReplAggregates.cpp updated: 1.37 -> 1.38 --- Log message: Teach scalarrepl to promote unions of vectors and floats, producing insert/extractelement operations. This implements Transforms/ScalarRepl/vector_promote.ll --- Diffs of the changes: (+101 -46) ScalarReplAggregates.cpp | 147 ++++++++++++++++++++++++++++++++--------------- 1 files changed, 101 insertions(+), 46 deletions(-) Index: llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp diff -u llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp:1.37 llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp:1.38 --- llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp:1.37 Tue Mar 7 19:05:29 2006 +++ llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp Fri Apr 14 16:42:41 2006 @@ -415,16 +415,30 @@ /// MergeInType - Add the 'In' type to the accumulated type so far. If the /// types are incompatible, return true, otherwise update Accum and return /// false. +/// +/// There are two cases we handle here: +/// 1) An effectively integer union, where the pieces are stored into as +/// smaller integers (common with byte swap and other idioms). +/// 2) A union of a vector and its elements. Here we turn element accesses +/// into insert/extract element operations. static bool MergeInType(const Type *In, const Type *&Accum) { - if (!In->isIntegral()) return true; - // If this is our first type, just use it. - if (Accum == Type::VoidTy) { + const PackedType *PTy; + if (Accum == Type::VoidTy || In == Accum) { Accum = In; - } else { + } else if (In->isIntegral() && Accum->isIntegral()) { // integer union. // Otherwise pick whichever type is larger. if (In->getTypeID() > Accum->getTypeID()) Accum = In; + } else if ((PTy = dyn_cast(Accum)) && + PTy->getElementType() == In) { + // Accum is a vector, and we are accessing an element: ok. + } else if ((PTy = dyn_cast(In)) && + PTy->getElementType() == Accum) { + // In is a vector, and accum is an element: ok, remember In. + Accum = In; + } else { + return true; } return false; } @@ -462,7 +476,7 @@ // Storing the pointer, not the into the value? if (SI->getOperand(0) == V) return 0; - // NOTE: We could handle storing of FP imms here! + // NOTE: We could handle storing of FP imms into integers here! if (MergeInType(SI->getOperand(0)->getType(), UsedType)) return 0; @@ -482,7 +496,7 @@ IsNotTrivial = true; const Type *SubElt = CanConvertToScalar(GEP, IsNotTrivial); if (SubElt == 0) return 0; - if (SubElt != Type::VoidTy) { + if (SubElt != Type::VoidTy && SubElt->isInteger()) { const Type *NewTy = getUIntAtLeastAsBitAs(SubElt->getPrimitiveSizeInBits()+BitOffset); if (NewTy == 0 || MergeInType(NewTy, UsedType)) return 0; @@ -499,8 +513,23 @@ if (const ArrayType *ATy = dyn_cast(AggTy)) { if (Idx >= ATy->getNumElements()) return 0; // Out of range. - } else if (const PackedType *PTy = dyn_cast(AggTy)) { - if (Idx >= PTy->getNumElements()) return 0; // Out of range. + } else if (const PackedType *PackedTy = dyn_cast(AggTy)) { + // Getting an element of the packed vector. + if (Idx >= PackedTy->getNumElements()) return 0; // Out of range. + + // Merge in the packed type. + if (MergeInType(PackedTy, UsedType)) return 0; + + const Type *SubTy = CanConvertToScalar(GEP, IsNotTrivial); + if (SubTy == 0) return 0; + + if (SubTy != Type::VoidTy && MergeInType(SubTy, UsedType)) + return 0; + + // We'll need to change this to an insert/extract element operation. + IsNotTrivial = true; + continue; // Everything looks ok + } else if (isa(AggTy)) { // Structs are always ok. } else { @@ -537,31 +566,47 @@ "Not in the entry block!"); EntryBlock->getInstList().remove(AI); // Take the alloca out of the program. + if (ActualTy->isInteger()) + ActualTy = ActualTy->getUnsignedVersion(); + // Create and insert the alloca. - AllocaInst *NewAI = new AllocaInst(ActualTy->getUnsignedVersion(), 0, - AI->getName(), EntryBlock->begin()); + AllocaInst *NewAI = new AllocaInst(ActualTy, 0, AI->getName(), + EntryBlock->begin()); ConvertUsesToScalar(AI, NewAI, 0); delete AI; } /// ConvertUsesToScalar - Convert all of the users of Ptr to use the new alloca -/// directly. Offset is an offset from the original alloca, in bits that need -/// to be shifted to the right. By the end of this, there should be no uses of -/// Ptr. +/// directly. This happens when we are converting an "integer union" to a +/// single integer scalar, or when we are converting a "vector union" to a +/// vector with insert/extractelement instructions. +/// +/// Offset is an offset from the original alloca, in bits that need to be +/// shifted to the right. By the end of this, there should be no uses of Ptr. void SROA::ConvertUsesToScalar(Value *Ptr, AllocaInst *NewAI, unsigned Offset) { + bool isVectorInsert = isa(NewAI->getType()->getElementType()); while (!Ptr->use_empty()) { Instruction *User = cast(Ptr->use_back()); if (LoadInst *LI = dyn_cast(User)) { // The load is a bit extract from NewAI shifted right by Offset bits. Value *NV = new LoadInst(NewAI, LI->getName(), LI); - if (Offset && Offset < NV->getType()->getPrimitiveSizeInBits()) - NV = new ShiftInst(Instruction::Shr, NV, - ConstantUInt::get(Type::UByteTy, Offset), - LI->getName(), LI); - if (NV->getType() != LI->getType()) - NV = new CastInst(NV, LI->getType(), LI->getName(), LI); + if (NV->getType() != LI->getType()) { + if (const PackedType *PTy = dyn_cast(NV->getType())) { + // Must be an element access. + unsigned Elt = Offset/PTy->getElementType()->getPrimitiveSizeInBits(); + NV = new ExtractElementInst(NV, ConstantUInt::get(Type::UIntTy, Elt), + "tmp", LI); + } else { + assert(NV->getType()->isInteger() && "Unknown promotion!"); + if (Offset && Offset < NV->getType()->getPrimitiveSizeInBits()) + NV = new ShiftInst(Instruction::Shr, NV, + ConstantUInt::get(Type::UByteTy, Offset), + LI->getName(), LI); + NV = new CastInst(NV, LI->getType(), LI->getName(), LI); + } + } LI->replaceAllUsesWith(NV); LI->eraseFromParent(); } else if (StoreInst *SI = dyn_cast(User)) { @@ -570,31 +615,41 @@ // Convert the stored type to the actual type, shift it left to insert // then 'or' into place. Value *SV = SI->getOperand(0); - if (SV->getType() != NewAI->getType()->getElementType() || Offset != 0) { + const Type *AllocaType = NewAI->getType()->getElementType(); + if (SV->getType() != AllocaType) { Value *Old = new LoadInst(NewAI, NewAI->getName()+".in", SI); - // If SV is signed, convert it to unsigned, so that the next cast zero - // extends the value. - if (SV->getType()->isSigned()) - SV = new CastInst(SV, SV->getType()->getUnsignedVersion(), - SV->getName(), SI); - SV = new CastInst(SV, Old->getType(), SV->getName(), SI); - if (Offset && Offset < SV->getType()->getPrimitiveSizeInBits()) - SV = new ShiftInst(Instruction::Shl, SV, - ConstantUInt::get(Type::UByteTy, Offset), - SV->getName()+".adj", SI); - // Mask out the bits we are about to insert from the old value. - unsigned TotalBits = SV->getType()->getPrimitiveSizeInBits(); - unsigned InsertBits = - SI->getOperand(0)->getType()->getPrimitiveSizeInBits(); - if (TotalBits != InsertBits) { - assert(TotalBits > InsertBits); - uint64_t Mask = ~(((1ULL << InsertBits)-1) << Offset); - if (TotalBits != 64) - Mask = Mask & ((1ULL << TotalBits)-1); - Old = BinaryOperator::createAnd(Old, + + if (const PackedType *PTy = dyn_cast(AllocaType)) { + // Must be an element insertion. + unsigned Elt = Offset/PTy->getElementType()->getPrimitiveSizeInBits(); + SV = new InsertElementInst(Old, SV, + ConstantUInt::get(Type::UIntTy, Elt), + "tmp", SI); + } else { + // If SV is signed, convert it to unsigned, so that the next cast zero + // extends the value. + if (SV->getType()->isSigned()) + SV = new CastInst(SV, SV->getType()->getUnsignedVersion(), + SV->getName(), SI); + SV = new CastInst(SV, Old->getType(), SV->getName(), SI); + if (Offset && Offset < SV->getType()->getPrimitiveSizeInBits()) + SV = new ShiftInst(Instruction::Shl, SV, + ConstantUInt::get(Type::UByteTy, Offset), + SV->getName()+".adj", SI); + // Mask out the bits we are about to insert from the old value. + unsigned TotalBits = SV->getType()->getPrimitiveSizeInBits(); + unsigned InsertBits = + SI->getOperand(0)->getType()->getPrimitiveSizeInBits(); + if (TotalBits != InsertBits) { + assert(TotalBits > InsertBits); + uint64_t Mask = ~(((1ULL << InsertBits)-1) << Offset); + if (TotalBits != 64) + Mask = Mask & ((1ULL << TotalBits)-1); + Old = BinaryOperator::createAnd(Old, ConstantUInt::get(Old->getType(), Mask), - Old->getName()+".mask", SI); - SV = BinaryOperator::createOr(Old, SV, SV->getName()+".ins", SI); + Old->getName()+".mask", SI); + SV = BinaryOperator::createOr(Old, SV, SV->getName()+".ins", SI); + } } } new StoreInst(SV, NewAI, SI); @@ -603,7 +658,7 @@ } else if (CastInst *CI = dyn_cast(User)) { unsigned NewOff = Offset; const TargetData &TD = getAnalysis(); - if (TD.isBigEndian()) { + if (TD.isBigEndian() && !isVectorInsert) { // Adjust the pointer. For example, storing 16-bits into a 32-bit // alloca with just a cast makes it modify the top 16-bits. const Type *SrcTy = cast(Ptr->getType())->getElementType(); @@ -625,7 +680,7 @@ unsigned Idx = cast(GEP->getOperand(1))->getRawValue(); unsigned BitOffset = Idx*AggSizeInBits; - if (TD.isLittleEndian()) + if (TD.isLittleEndian() || isVectorInsert) NewOffset += BitOffset; else NewOffset -= BitOffset; @@ -637,14 +692,14 @@ if (const SequentialType *SeqTy = dyn_cast(AggTy)) { unsigned ElSizeBits = TD.getTypeSize(SeqTy->getElementType())*8; - if (TD.isLittleEndian()) + if (TD.isLittleEndian() || isVectorInsert) NewOffset += ElSizeBits*Idx; else NewOffset += AggSizeInBits-ElSizeBits*(Idx+1); } else if (const StructType *STy = dyn_cast(AggTy)) { unsigned EltBitOffset = TD.getStructLayout(STy)->MemberOffsets[Idx]*8; - if (TD.isLittleEndian()) + if (TD.isLittleEndian() || isVectorInsert) NewOffset += EltBitOffset; else { const PointerType *ElPtrTy = cast(GEP->getType()); From evan.cheng at apple.com Fri Apr 14 16:59:15 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 14 Apr 2006 16:59:15 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.h X86ISelLowering.cpp X86InstrSSE.td Message-ID: <200604142159.QAA19975@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ISelLowering.h updated: 1.54 -> 1.55 X86ISelLowering.cpp updated: 1.165 -> 1.166 X86InstrSSE.td updated: 1.89 -> 1.90 --- Log message: Last few SSE3 intrinsics. --- Diffs of the changes: (+189 -32) X86ISelLowering.cpp | 59 +++++++++++++++++++ X86ISelLowering.h | 8 ++ X86InstrSSE.td | 154 +++++++++++++++++++++++++++++++++++++++++----------- 3 files changed, 189 insertions(+), 32 deletions(-) Index: llvm/lib/Target/X86/X86ISelLowering.h diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.54 llvm/lib/Target/X86/X86ISelLowering.h:1.55 --- llvm/lib/Target/X86/X86ISelLowering.h:1.54 Mon Apr 10 19:19:04 2006 +++ llvm/lib/Target/X86/X86ISelLowering.h Fri Apr 14 16:59:03 2006 @@ -237,6 +237,14 @@ /// specifies a shuffle of elements that is suitable for input to MOVS{S|D}. bool isMOVSMask(SDNode *N); + /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand + /// specifies a shuffle of elements that is suitable for input to MOVSHDUP. + bool isMOVSHDUPMask(SDNode *N); + + /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand + /// specifies a shuffle of elements that is suitable for input to MOVSLDUP. + bool isMOVSLDUPMask(SDNode *N); + /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand /// specifies a splat of a single element. bool isSplatMask(SDNode *N); Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.165 llvm/lib/Target/X86/X86ISelLowering.cpp:1.166 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.165 Thu Apr 13 00:10:25 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Fri Apr 14 16:59:03 2006 @@ -1715,6 +1715,58 @@ return true; } +/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand +/// specifies a shuffle of elements that is suitable for input to MOVSHDUP. +bool X86::isMOVSHDUPMask(SDNode *N) { + assert(N->getOpcode() == ISD::BUILD_VECTOR); + + if (N->getNumOperands() != 4) + return false; + + // Expect 1, 1, 3, 3 + for (unsigned i = 0; i < 2; ++i) { + SDOperand Arg = N->getOperand(i); + if (Arg.getOpcode() == ISD::UNDEF) continue; + assert(isa(Arg) && "Invalid VECTOR_SHUFFLE mask!"); + unsigned Val = cast(Arg)->getValue(); + if (Val != 1) return false; + } + for (unsigned i = 2; i < 4; ++i) { + SDOperand Arg = N->getOperand(i); + if (Arg.getOpcode() == ISD::UNDEF) continue; + assert(isa(Arg) && "Invalid VECTOR_SHUFFLE mask!"); + unsigned Val = cast(Arg)->getValue(); + if (Val != 3) return false; + } + return true; +} + +/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand +/// specifies a shuffle of elements that is suitable for input to MOVSLDUP. +bool X86::isMOVSLDUPMask(SDNode *N) { + assert(N->getOpcode() == ISD::BUILD_VECTOR); + + if (N->getNumOperands() != 4) + return false; + + // Expect 0, 0, 2, 2 + for (unsigned i = 0; i < 2; ++i) { + SDOperand Arg = N->getOperand(i); + if (Arg.getOpcode() == ISD::UNDEF) continue; + assert(isa(Arg) && "Invalid VECTOR_SHUFFLE mask!"); + unsigned Val = cast(Arg)->getValue(); + if (Val != 0) return false; + } + for (unsigned i = 2; i < 4; ++i) { + SDOperand Arg = N->getOperand(i); + if (Arg.getOpcode() == ISD::UNDEF) continue; + assert(isa(Arg) && "Invalid VECTOR_SHUFFLE mask!"); + unsigned Val = cast(Arg)->getValue(); + if (Val != 2) return false; + } + return true; +} + /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies /// a splat of a single element. bool X86::isSplatMask(SDNode *N) { @@ -2710,8 +2762,9 @@ if (NumElems == 2) return Op; - if (X86::isMOVSMask(PermMask.Val)) - // Leave the VECTOR_SHUFFLE alone. It matches MOVS{S|D}. + if (X86::isMOVSMask(PermMask.Val) || + X86::isMOVSHDUPMask(PermMask.Val) || + X86::isMOVSLDUPMask(PermMask.Val)) return Op; if (X86::isUNPCKLMask(PermMask.Val) || @@ -3143,6 +3196,8 @@ return (Mask.Val->getNumOperands() == 2 || X86::isSplatMask(Mask.Val) || X86::isMOVSMask(Mask.Val) || + X86::isMOVSHDUPMask(Mask.Val) || + X86::isMOVSLDUPMask(Mask.Val) || X86::isPSHUFDMask(Mask.Val) || isPSHUFHW_PSHUFLWMask(Mask.Val) || X86::isSHUFPMask(Mask.Val) || Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.89 llvm/lib/Target/X86/X86InstrSSE.td:1.90 --- llvm/lib/Target/X86/X86InstrSSE.td:1.89 Fri Apr 14 02:43:12 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Fri Apr 14 16:59:03 2006 @@ -88,6 +88,10 @@ return X86::isSplatMask(N); }], SHUFFLE_get_shuf_imm>; +def SSE_splat_v2_mask : PatLeaf<(build_vector), [{ + return X86::isSplatMask(N); +}]>; + def MOVLHPS_shuffle_mask : PatLeaf<(build_vector), [{ return X86::isMOVLHPSMask(N); }]>; @@ -108,6 +112,14 @@ return X86::isMOVSMask(N); }]>; +def MOVSHDUP_shuffle_mask : PatLeaf<(build_vector), [{ + return X86::isMOVSHDUPMask(N); +}]>; + +def MOVSLDUP_shuffle_mask : PatLeaf<(build_vector), [{ + return X86::isMOVSLDUPMask(N); +}]>; + def UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{ return X86::isUNPCKLMask(N); }]>; @@ -155,8 +167,9 @@ // PDI - SSE2 instructions with TB and OpSize prefixes. // PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix. // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes. +// S3I - SSE3 instructions with TB and OpSize prefixes. +// S3SI - SSE3 instructions with XS prefix. // S3SI - SSE3 instructions with XD prefix. -// S3DI - SSE3 instructions with TB and OpSize prefixes. class SSI o, Format F, dag ops, string asm, list pattern> : I, XS, Requires<[HasSSE1]>; class SDI o, Format F, dag ops, string asm, list pattern> @@ -174,8 +187,10 @@ let Pattern = pattern; } class S3SI o, Format F, dag ops, string asm, list pattern> - : I, XD, Requires<[HasSSE3]>; + : I, XS, Requires<[HasSSE3]>; class S3DI o, Format F, dag ops, string asm, list pattern> + : I, XD, Requires<[HasSSE3]>; +class S3I o, Format F, dag ops, string asm, list pattern> : I, TB, OpSize, Requires<[HasSSE3]>; //===----------------------------------------------------------------------===// @@ -232,18 +247,18 @@ : PDI; -class S3S_Intrr o, string asm, Intrinsic IntId> - : S3SI; -class S3S_Intrm o, string asm, Intrinsic IntId> - : S3SI; class S3D_Intrr o, string asm, Intrinsic IntId> : S3DI; + [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>; class S3D_Intrm o, string asm, Intrinsic IntId> : S3DI; +class S3_Intrr o, string asm, Intrinsic IntId> + : S3I; +class S3_Intrm o, string asm, Intrinsic IntId> + : S3I; @@ -528,6 +543,13 @@ "cvtss2si {$src, $dst|$dst, $src}", [(set R32:$dst, (int_x86_sse_cvtss2si (loadv4f32 addr:$src)))]>; +def CVTSD2SIrr: SDI<0x2D, MRMSrcReg, (ops R32:$dst, VR128:$src), + "cvtsd2si {$src, $dst|$dst, $src}", + [(set R32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>; +def CVTSD2SIrm: SDI<0x2D, MRMSrcMem, (ops R32:$dst, f128mem:$src), + "cvtsd2si {$src, $dst|$dst, $src}", + [(set R32:$dst, (int_x86_sse2_cvtsd2si + (loadv2f64 addr:$src)))]>; // Aliases for intrinsics def Int_CVTTSS2SIrr: SSI<0x2C, MRMSrcReg, (ops R32:$dst, VR128:$src), @@ -714,7 +736,7 @@ } //===----------------------------------------------------------------------===// -// SSE packed FP Instructions +// SSE packed Instructions //===----------------------------------------------------------------------===// // Some 'special' instructions @@ -766,6 +788,9 @@ "movdqu {$src, $dst|$dst, $src}", [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>, XS, Requires<[HasSSE2]>; +def LDDQUrm : S3DI<0xF0, MRMSrcMem, (ops VR128:$dst, i128mem:$src), + "lddqu {$src, $dst|$dst, $src}", + [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>; let isTwoAddress = 1 in { def MOVLPSrm : PSI<0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2), @@ -833,6 +858,39 @@ MOVHLPS_shuffle_mask)))]>; } +def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (ops VR128:$dst, VR128:$src), + "movshdup {$src, $dst|$dst, $src}", + [(set VR128:$dst, (v4f32 (vector_shuffle + VR128:$src, (undef), + MOVSHDUP_shuffle_mask)))]>; +def MOVSHDUPrm : S3SI<0x16, MRMSrcReg, (ops VR128:$dst, f128mem:$src), + "movshdup {$src, $dst|$dst, $src}", + [(set VR128:$dst, (v4f32 (vector_shuffle + (loadv4f32 addr:$src), (undef), + MOVSHDUP_shuffle_mask)))]>; + +def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src), + "movsldup {$src, $dst|$dst, $src}", + [(set VR128:$dst, (v4f32 (vector_shuffle + VR128:$src, (undef), + MOVSLDUP_shuffle_mask)))]>; +def MOVSLDUPrm : S3SI<0x12, MRMSrcReg, (ops VR128:$dst, f128mem:$src), + "movsldup {$src, $dst|$dst, $src}", + [(set VR128:$dst, (v4f32 (vector_shuffle + (loadv4f32 addr:$src), (undef), + MOVSLDUP_shuffle_mask)))]>; + +def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src), + "movddup {$src, $dst|$dst, $src}", + [(set VR128:$dst, (v2f64 (vector_shuffle + VR128:$src, (undef), + SSE_splat_v2_mask)))]>; +def MOVDDUPrm : S3DI<0x12, MRMSrcReg, (ops VR128:$dst, f64mem:$src), + "movddup {$src, $dst|$dst, $src}", + [(set VR128:$dst, (v2f64 (vector_shuffle + (loadv2f64 addr:$src), (undef), + SSE_splat_v2_mask)))]>; + // SSE2 instructions without OpSize prefix def CVTDQ2PSrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src), "cvtdq2ps {$src, $dst|$dst, $src}", @@ -910,15 +968,6 @@ [(set VR128:$dst, (int_x86_sse2_cvtpd2ps (loadv2f64 addr:$src)))]>; - -def CVTSD2SIrr: SDI<0x2D, MRMSrcReg, (ops R32:$dst, VR128:$src), - "cvtsd2si {$src, $dst|$dst, $src}", - [(set R32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>; -def CVTSD2SIrm: SDI<0x2D, MRMSrcMem, (ops R32:$dst, f128mem:$src), - "cvtsd2si {$src, $dst|$dst, $src}", - [(set R32:$dst, (int_x86_sse2_cvtsd2si - (loadv2f64 addr:$src)))]>; - // Match intrinsics which expect XMM operand(s). // Aliases for intrinsics let isTwoAddress = 1 in { @@ -1019,6 +1068,27 @@ "subpd {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v2f64 (fsub VR128:$src1, (load addr:$src2))))]>; + +def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg, + (ops VR128:$dst, VR128:$src1, VR128:$src2), + "addsubps {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1, + VR128:$src2))]>; +def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem, + (ops VR128:$dst, VR128:$src1, f128mem:$src2), + "addsubps {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1, + (loadv4f32 addr:$src2)))]>; +def ADDSUBPDrr : S3I<0xD0, MRMSrcReg, + (ops VR128:$dst, VR128:$src1, VR128:$src2), + "addsubpd {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1, + VR128:$src2))]>; +def ADDSUBPDrm : S3I<0xD0, MRMSrcMem, + (ops VR128:$dst, VR128:$src1, f128mem:$src2), + "addsubpd {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1, + (loadv2f64 addr:$src2)))]>; } def SQRTPSr : PS_Intr<0x51, "sqrtps {$src, $dst|$dst, $src}", @@ -1300,21 +1370,21 @@ // Horizontal ops let isTwoAddress = 1 in { -def HADDPSrr : S3S_Intrr<0x7C, "haddps {$src2, $dst|$dst, $src2}", +def HADDPSrr : S3D_Intrr<0x7C, "haddps {$src2, $dst|$dst, $src2}", int_x86_sse3_hadd_ps>; -def HADDPSrm : S3S_Intrm<0x7C, "haddps {$src2, $dst|$dst, $src2}", +def HADDPSrm : S3D_Intrm<0x7C, "haddps {$src2, $dst|$dst, $src2}", int_x86_sse3_hadd_ps>; -def HADDPDrr : S3D_Intrr<0x7C, "haddpd {$src2, $dst|$dst, $src2}", +def HADDPDrr : S3_Intrr<0x7C, "haddpd {$src2, $dst|$dst, $src2}", int_x86_sse3_hadd_pd>; -def HADDPDrm : S3D_Intrm<0x7C, "haddpd {$src2, $dst|$dst, $src2}", +def HADDPDrm : S3_Intrm<0x7C, "haddpd {$src2, $dst|$dst, $src2}", int_x86_sse3_hadd_pd>; -def HSUBPSrr : S3S_Intrr<0x7C, "hsubps {$src2, $dst|$dst, $src2}", +def HSUBPSrr : S3D_Intrr<0x7C, "hsubps {$src2, $dst|$dst, $src2}", int_x86_sse3_hsub_ps>; -def HSUBPSrm : S3S_Intrm<0x7C, "hsubps {$src2, $dst|$dst, $src2}", +def HSUBPSrm : S3D_Intrm<0x7C, "hsubps {$src2, $dst|$dst, $src2}", int_x86_sse3_hsub_ps>; -def HSUBPDrr : S3D_Intrr<0x7C, "hsubpd {$src2, $dst|$dst, $src2}", +def HSUBPDrr : S3_Intrr<0x7C, "hsubpd {$src2, $dst|$dst, $src2}", int_x86_sse3_hsub_pd>; -def HSUBPDrm : S3D_Intrm<0x7C, "hsubpd {$src2, $dst|$dst, $src2}", +def HSUBPDrm : S3_Intrm<0x7C, "hsubpd {$src2, $dst|$dst, $src2}", int_x86_sse3_hsub_pd>; } @@ -2023,6 +2093,14 @@ "stmxcsr $dst", [(int_x86_sse_stmxcsr addr:$dst)]>, TB, Requires<[HasSSE1]>; +// Thread synchronization +def MONITOR : I<0xC8, RawFrm, (ops), "monitor", + [(int_x86_sse3_monitor EAX, ECX, EDX)]>, + TB, Requires<[HasSSE3]>; +def MWAIT : I<0xC9, RawFrm, (ops), "mwait", + [(int_x86_sse3_mwait ECX, EAX)]>, + TB, Requires<[HasSSE3]>; + //===----------------------------------------------------------------------===// // Alias Instructions //===----------------------------------------------------------------------===// @@ -2271,9 +2349,9 @@ (MOVLDI2PDIrr (V_SET0_PI), (MOVZX32rr8 R8:$src))>, Requires<[HasSSE2]>; // Splat v2f64 / v2i64 -def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_mask:$sm), +def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_v2_mask:$sm), (v2f64 (UNPCKLPDrr VR128:$src, VR128:$src))>, Requires<[HasSSE2]>; -def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), SSE_splat_mask:$sm), +def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), SSE_splat_v2_mask:$sm), (v2i64 (PUNPCKLQDQrr VR128:$src, VR128:$src))>, Requires<[HasSSE2]>; // Splat v4f32 @@ -2316,6 +2394,22 @@ UNPCKL_v_undef_shuffle_mask)), (PUNPCKLDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>; +// vector_shuffle v1, <1, 1, 3, 3> +def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef), + MOVSHDUP_shuffle_mask)), + (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>; +def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (loadv2i64 addr:$src)), (undef), + MOVSHDUP_shuffle_mask)), + (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>; + +// vector_shuffle v1, <0, 0, 2, 2> +def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef), + MOVSLDUP_shuffle_mask)), + (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>; +def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (loadv2i64 addr:$src)), (undef), + MOVSLDUP_shuffle_mask)), + (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>; + // 128-bit logical shifts def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2), (v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>, From evan.cheng at apple.com Fri Apr 14 16:59:15 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 14 Apr 2006 16:59:15 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/IntrinsicsX86.td Message-ID: <200604142159.QAA19979@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm: IntrinsicsX86.td updated: 1.28 -> 1.29 --- Log message: Last few SSE3 intrinsics. --- Diffs of the changes: (+26 -0) IntrinsicsX86.td | 26 ++++++++++++++++++++++++++ 1 files changed, 26 insertions(+) Index: llvm/include/llvm/IntrinsicsX86.td diff -u llvm/include/llvm/IntrinsicsX86.td:1.28 llvm/include/llvm/IntrinsicsX86.td:1.29 --- llvm/include/llvm/IntrinsicsX86.td:1.28 Fri Apr 14 02:43:12 2006 +++ llvm/include/llvm/IntrinsicsX86.td Fri Apr 14 16:59:03 2006 @@ -466,6 +466,16 @@ //===----------------------------------------------------------------------===// // SSE3 +// Addition / subtraction ops. +let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". + def int_x86_sse3_addsub_ps : GCCBuiltin<"__builtin_ia32_addsubps">, + Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, + llvm_v4f32_ty], [IntrNoMem]>; + def int_x86_sse3_addsub_pd : GCCBuiltin<"__builtin_ia32_addsubpd">, + Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty, + llvm_v2f64_ty], [IntrNoMem]>; +} + // Horizontal ops. let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse3_hadd_ps : GCCBuiltin<"__builtin_ia32_haddps">, @@ -481,3 +491,19 @@ Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>; } + +// Specialized unaligned load. +let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". + def int_x86_sse3_ldu_dq : GCCBuiltin<"__builtin_ia32_lddqu">, + Intrinsic<[llvm_v16i8_ty, llvm_ptr_ty], [IntrReadMem]>; +} + +// Thread synchronization ops. +let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". + def int_x86_sse3_monitor : GCCBuiltin<"__builtin_ia32_monitor">, + Intrinsic<[llvm_void_ty, llvm_ptr_ty, + llvm_uint_ty, llvm_uint_ty], [IntrWriteMem]>; + def int_x86_sse3_mwait : GCCBuiltin<"__builtin_ia32_mwait">, + Intrinsic<[llvm_void_ty, llvm_uint_ty, + llvm_uint_ty], [IntrWriteMem]>; +} From lattner at cs.uiuc.edu Fri Apr 14 17:20:19 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 14 Apr 2006 17:20:19 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Instructions.h Message-ID: <200604142220.RAA21350@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm: Instructions.h updated: 1.33 -> 1.34 --- Log message: These instructions always return a packed vector. Improve the class definitions to expose this fact. --- Diffs of the changes: (+15 -14) Instructions.h | 29 +++++++++++++++-------------- 1 files changed, 15 insertions(+), 14 deletions(-) Index: llvm/include/llvm/Instructions.h diff -u llvm/include/llvm/Instructions.h:1.33 llvm/include/llvm/Instructions.h:1.34 --- llvm/include/llvm/Instructions.h:1.33 Fri Apr 7 23:04:54 2006 +++ llvm/include/llvm/Instructions.h Fri Apr 14 17:20:07 2006 @@ -24,6 +24,7 @@ class BasicBlock; class ConstantInt; class PointerType; +class PackedType; //===----------------------------------------------------------------------===// // AllocationInst Class @@ -776,13 +777,7 @@ /// class InsertElementInst : public Instruction { Use Ops[3]; - InsertElementInst(const InsertElementInst &IE) : - Instruction(IE.getType(), InsertElement, Ops, 3) { - Ops[0].init(IE.Ops[0], this); - Ops[1].init(IE.Ops[1], this); - Ops[2].init(IE.Ops[2], this); - } - + InsertElementInst(const InsertElementInst &IE); public: InsertElementInst(Value *Vec, Value *NewElt, Value *Idx, const std::string &Name = "",Instruction *InsertBefore = 0); @@ -798,6 +793,12 @@ virtual bool mayWriteToMemory() const { return false; } + /// getType - Overload to return most specific packed type. + /// + inline const PackedType *getType() const { + return reinterpret_cast(Instruction::getType()); + } + /// Transparently provide more efficient getOperand methods. Value *getOperand(unsigned i) const { assert(i < 3 && "getOperand() out of range!"); @@ -828,13 +829,7 @@ /// class ShuffleVectorInst : public Instruction { Use Ops[3]; - ShuffleVectorInst(const ShuffleVectorInst &IE) : - Instruction(IE.getType(), ShuffleVector, Ops, 3) { - Ops[0].init(IE.Ops[0], this); - Ops[1].init(IE.Ops[1], this); - Ops[2].init(IE.Ops[2], this); - } - + ShuffleVectorInst(const ShuffleVectorInst &IE); public: ShuffleVectorInst(Value *V1, Value *V2, Value *Mask, const std::string &Name = "", Instruction *InsertBefor = 0); @@ -850,6 +845,12 @@ virtual bool mayWriteToMemory() const { return false; } + /// getType - Overload to return most specific packed type. + /// + inline const PackedType *getType() const { + return reinterpret_cast(Instruction::getType()); + } + /// Transparently provide more efficient getOperand methods. Value *getOperand(unsigned i) const { assert(i < 3 && "getOperand() out of range!"); From lattner at cs.uiuc.edu Fri Apr 14 17:20:44 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 14 Apr 2006 17:20:44 -0500 Subject: [llvm-commits] CVS: llvm/lib/VMCore/Instructions.cpp Message-ID: <200604142220.RAA21388@zion.cs.uiuc.edu> Changes in directory llvm/lib/VMCore: Instructions.cpp updated: 1.34 -> 1.35 --- Log message: Move these ctors out of line --- Diffs of the changes: (+13 -0) Instructions.cpp | 13 +++++++++++++ 1 files changed, 13 insertions(+) Index: llvm/lib/VMCore/Instructions.cpp diff -u llvm/lib/VMCore/Instructions.cpp:1.34 llvm/lib/VMCore/Instructions.cpp:1.35 --- llvm/lib/VMCore/Instructions.cpp:1.34 Fri Apr 7 23:05:48 2006 +++ llvm/lib/VMCore/Instructions.cpp Fri Apr 14 17:20:32 2006 @@ -833,6 +833,12 @@ // InsertElementInst Implementation //===----------------------------------------------------------------------===// +InsertElementInst::InsertElementInst(const InsertElementInst &IE) + : Instruction(IE.getType(), InsertElement, Ops, 3) { + Ops[0].init(IE.Ops[0], this); + Ops[1].init(IE.Ops[1], this); + Ops[2].init(IE.Ops[2], this); +} InsertElementInst::InsertElementInst(Value *Vec, Value *Elt, Value *Index, const std::string &Name, Instruction *InsertBef) @@ -874,6 +880,13 @@ // ShuffleVectorInst Implementation //===----------------------------------------------------------------------===// +ShuffleVectorInst::ShuffleVectorInst(const ShuffleVectorInst &SV) + : Instruction(SV.getType(), ShuffleVector, Ops, 3) { + Ops[0].init(SV.Ops[0], this); + Ops[1].init(SV.Ops[1], this); + Ops[2].init(SV.Ops[2], this); +} + ShuffleVectorInst::ShuffleVectorInst(Value *V1, Value *V2, Value *Mask, const std::string &Name, Instruction *InsertBefore) From lattner at cs.uiuc.edu Fri Apr 14 18:19:20 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 14 Apr 2006 18:19:20 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp Message-ID: <200604142319.SAA22063@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.150 -> 1.151 --- Log message: Allow undef in a shuffle mask --- Diffs of the changes: (+1 -0) PPCISelLowering.cpp | 1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.150 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.151 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.150 Fri Apr 14 01:01:58 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Fri Apr 14 18:19:08 2006 @@ -416,6 +416,7 @@ assert(isa(Elt) && "Invalid VECTOR_SHUFFLE mask!"); for (unsigned i = EltSize, e = 16; i != e; i += EltSize) { + if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; assert(isa(N->getOperand(i)) && "Invalid VECTOR_SHUFFLE mask!"); for (unsigned j = 0; j != EltSize; ++j) From evan.cheng at apple.com Fri Apr 14 18:32:52 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 14 Apr 2006 18:32:52 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td Message-ID: <200604142332.SAA22205@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrSSE.td updated: 1.90 -> 1.91 --- Log message: Some clean up --- Diffs of the changes: (+81 -78) X86InstrSSE.td | 159 +++++++++++++++++++++++++++++---------------------------- 1 files changed, 81 insertions(+), 78 deletions(-) Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.90 llvm/lib/Target/X86/X86InstrSSE.td:1.91 --- llvm/lib/Target/X86/X86InstrSSE.td:1.90 Fri Apr 14 16:59:03 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Fri Apr 14 18:32:40 2006 @@ -736,7 +736,7 @@ } //===----------------------------------------------------------------------===// -// SSE packed Instructions +// SSE packed FP Instructions //===----------------------------------------------------------------------===// // Some 'special' instructions @@ -780,17 +780,6 @@ def MOVUPDmr : PDI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src), "movupd {$src, $dst|$dst, $src}", [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>; -def MOVDQUrm : I<0x6F, MRMSrcMem, (ops VR128:$dst, i128mem:$src), - "movdqu {$src, $dst|$dst, $src}", - [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>, - XS, Requires<[HasSSE2]>; -def MOVDQUmr : I<0x7F, MRMDestMem, (ops i128mem:$dst, VR128:$src), - "movdqu {$src, $dst|$dst, $src}", - [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>, - XS, Requires<[HasSSE2]>; -def LDDQUrm : S3DI<0xF0, MRMSrcMem, (ops VR128:$dst, i128mem:$src), - "lddqu {$src, $dst|$dst, $src}", - [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>; let isTwoAddress = 1 in { def MOVLPSrm : PSI<0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2), @@ -1226,68 +1215,6 @@ "cmp${cc}pd {$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1, (load addr:$src), imm:$cc))]>; - -def PCMPEQBrr : PDI<0x74, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, VR128:$src2), - "pcmpeqb {$src2, $dst|$dst, $src2}", - [(set VR128:$dst, (int_x86_sse2_pcmpeq_b VR128:$src1, - VR128:$src2))]>; -def PCMPEQBrm : PDI<0x74, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, i128mem:$src2), - "pcmpeqb {$src2, $dst|$dst, $src2}", - [(set VR128:$dst, (int_x86_sse2_pcmpeq_b VR128:$src1, - (bc_v16i8 (loadv2i64 addr:$src2))))]>; -def PCMPEQWrr : PDI<0x75, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, VR128:$src2), - "pcmpeqw {$src2, $dst|$dst, $src2}", - [(set VR128:$dst, (int_x86_sse2_pcmpeq_w VR128:$src1, - VR128:$src2))]>; -def PCMPEQWrm : PDI<0x75, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, i128mem:$src2), - "pcmpeqw {$src2, $dst|$dst, $src2}", - [(set VR128:$dst, (int_x86_sse2_pcmpeq_w VR128:$src1, - (bc_v8i16 (loadv2i64 addr:$src2))))]>; -def PCMPEQDrr : PDI<0x76, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, VR128:$src2), - "pcmpeqd {$src2, $dst|$dst, $src2}", - [(set VR128:$dst, (int_x86_sse2_pcmpeq_d VR128:$src1, - VR128:$src2))]>; -def PCMPEQDrm : PDI<0x76, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, i128mem:$src2), - "pcmpeqd {$src2, $dst|$dst, $src2}", - [(set VR128:$dst, (int_x86_sse2_pcmpeq_d VR128:$src1, - (bc_v4i32 (loadv2i64 addr:$src2))))]>; - -def PCMPGTBrr : PDI<0x64, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, VR128:$src2), - "pcmpgtb {$src2, $dst|$dst, $src2}", - [(set VR128:$dst, (int_x86_sse2_pcmpgt_b VR128:$src1, - VR128:$src2))]>; -def PCMPGTBrm : PDI<0x64, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, i128mem:$src2), - "pcmpgtb {$src2, $dst|$dst, $src2}", - [(set VR128:$dst, (int_x86_sse2_pcmpgt_b VR128:$src1, - (bc_v16i8 (loadv2i64 addr:$src2))))]>; -def PCMPGTWrr : PDI<0x65, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, VR128:$src2), - "pcmpgtw {$src2, $dst|$dst, $src2}", - [(set VR128:$dst, (int_x86_sse2_pcmpgt_w VR128:$src1, - VR128:$src2))]>; -def PCMPGTWrm : PDI<0x65, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, i128mem:$src2), - "pcmpgtw {$src2, $dst|$dst, $src2}", - [(set VR128:$dst, (int_x86_sse2_pcmpgt_w VR128:$src1, - (bc_v8i16 (loadv2i64 addr:$src2))))]>; -def PCMPGTDrr : PDI<0x66, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, VR128:$src2), - "pcmpgtd {$src2, $dst|$dst, $src2}", - [(set VR128:$dst, (int_x86_sse2_pcmpgt_d VR128:$src1, - VR128:$src2))]>; -def PCMPGTDrm : PDI<0x66, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, i128mem:$src2), - "pcmpgtd {$src2, $dst|$dst, $src2}", - [(set VR128:$dst, (int_x86_sse2_pcmpgt_d VR128:$src1, - (bc_v4i32 (loadv2i64 addr:$src2))))]>; } // Shuffle and unpack instructions @@ -1401,6 +1328,17 @@ def MOVDQAmr : PDI<0x7F, MRMDestMem, (ops i128mem:$dst, VR128:$src), "movdqa {$src, $dst|$dst, $src}", [(store (v2i64 VR128:$src), addr:$dst)]>; +def MOVDQUrm : I<0x6F, MRMSrcMem, (ops VR128:$dst, i128mem:$src), + "movdqu {$src, $dst|$dst, $src}", + [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>, + XS, Requires<[HasSSE2]>; +def MOVDQUmr : I<0x7F, MRMDestMem, (ops i128mem:$dst, VR128:$src), + "movdqu {$src, $dst|$dst, $src}", + [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>, + XS, Requires<[HasSSE2]>; +def LDDQUrm : S3DI<0xF0, MRMSrcMem, (ops VR128:$dst, i128mem:$src), + "lddqu {$src, $dst|$dst, $src}", + [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>; // 128-bit Integer Arithmetic let isTwoAddress = 1 in { @@ -1800,6 +1738,71 @@ (load addr:$src2))))]>; } +// SSE2 Integer comparison +let isTwoAddress = 1 in { +def PCMPEQBrr : PDI<0x74, MRMSrcReg, + (ops VR128:$dst, VR128:$src1, VR128:$src2), + "pcmpeqb {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_pcmpeq_b VR128:$src1, + VR128:$src2))]>; +def PCMPEQBrm : PDI<0x74, MRMSrcReg, + (ops VR128:$dst, VR128:$src1, i128mem:$src2), + "pcmpeqb {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_pcmpeq_b VR128:$src1, + (bc_v16i8 (loadv2i64 addr:$src2))))]>; +def PCMPEQWrr : PDI<0x75, MRMSrcReg, + (ops VR128:$dst, VR128:$src1, VR128:$src2), + "pcmpeqw {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_pcmpeq_w VR128:$src1, + VR128:$src2))]>; +def PCMPEQWrm : PDI<0x75, MRMSrcReg, + (ops VR128:$dst, VR128:$src1, i128mem:$src2), + "pcmpeqw {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_pcmpeq_w VR128:$src1, + (bc_v8i16 (loadv2i64 addr:$src2))))]>; +def PCMPEQDrr : PDI<0x76, MRMSrcReg, + (ops VR128:$dst, VR128:$src1, VR128:$src2), + "pcmpeqd {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_pcmpeq_d VR128:$src1, + VR128:$src2))]>; +def PCMPEQDrm : PDI<0x76, MRMSrcReg, + (ops VR128:$dst, VR128:$src1, i128mem:$src2), + "pcmpeqd {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_pcmpeq_d VR128:$src1, + (bc_v4i32 (loadv2i64 addr:$src2))))]>; + +def PCMPGTBrr : PDI<0x64, MRMSrcReg, + (ops VR128:$dst, VR128:$src1, VR128:$src2), + "pcmpgtb {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_pcmpgt_b VR128:$src1, + VR128:$src2))]>; +def PCMPGTBrm : PDI<0x64, MRMSrcReg, + (ops VR128:$dst, VR128:$src1, i128mem:$src2), + "pcmpgtb {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_pcmpgt_b VR128:$src1, + (bc_v16i8 (loadv2i64 addr:$src2))))]>; +def PCMPGTWrr : PDI<0x65, MRMSrcReg, + (ops VR128:$dst, VR128:$src1, VR128:$src2), + "pcmpgtw {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_pcmpgt_w VR128:$src1, + VR128:$src2))]>; +def PCMPGTWrm : PDI<0x65, MRMSrcReg, + (ops VR128:$dst, VR128:$src1, i128mem:$src2), + "pcmpgtw {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_pcmpgt_w VR128:$src1, + (bc_v8i16 (loadv2i64 addr:$src2))))]>; +def PCMPGTDrr : PDI<0x66, MRMSrcReg, + (ops VR128:$dst, VR128:$src1, VR128:$src2), + "pcmpgtd {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_pcmpgt_d VR128:$src1, + VR128:$src2))]>; +def PCMPGTDrm : PDI<0x66, MRMSrcReg, + (ops VR128:$dst, VR128:$src1, i128mem:$src2), + "pcmpgtd {$src2, $dst|$dst, $src2}", + [(set VR128:$dst, (int_x86_sse2_pcmpgt_d VR128:$src1, + (bc_v4i32 (loadv2i64 addr:$src2))))]>; +} + // Pack instructions let isTwoAddress = 1 in { def PACKSSWBrr : PDI<0x63, MRMSrcReg, (ops VR128:$dst, VR128:$src1, @@ -1998,12 +2001,12 @@ } // Extract / Insert -def PEXTRWr : PDIi8<0xC5, MRMSrcReg, +def PEXTRWri : PDIi8<0xC5, MRMSrcReg, (ops R32:$dst, VR128:$src1, i32i8imm:$src2), "pextrw {$src2, $src1, $dst|$dst, $src1, $src2}", [(set R32:$dst, (X86pextrw (v8i16 VR128:$src1), (i32 imm:$src2)))]>; -def PEXTRWm : PDIi8<0xC5, MRMSrcMem, +def PEXTRWmi : PDIi8<0xC5, MRMSrcMem, (ops R32:$dst, i128mem:$src1, i32i8imm:$src2), "pextrw {$src2, $src1, $dst|$dst, $src1, $src2}", [(set R32:$dst, (X86pextrw @@ -2011,12 +2014,12 @@ (i32 imm:$src2)))]>; let isTwoAddress = 1 in { -def PINSRWr : PDIi8<0xC4, MRMSrcReg, +def PINSRWrri : PDIi8<0xC4, MRMSrcReg, (ops VR128:$dst, VR128:$src1, R32:$src2, i32i8imm:$src3), "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}", [(set VR128:$dst, (v8i16 (X86pinsrw (v8i16 VR128:$src1), R32:$src2, (i32 imm:$src3))))]>; -def PINSRWm : PDIi8<0xC4, MRMSrcMem, +def PINSRWrmi : PDIi8<0xC4, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i16mem:$src2, i32i8imm:$src3), "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}", [(set VR128:$dst, From evan.cheng at apple.com Fri Apr 14 18:33:39 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 14 Apr 2006 18:33:39 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp Message-ID: <200604142333.SAA22220@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86RegisterInfo.cpp updated: 1.137 -> 1.138 --- Log message: Added SSE (and other) entries to foldMemoryOperand(). --- Diffs of the changes: (+155 -19) X86RegisterInfo.cpp | 174 ++++++++++++++++++++++++++++++++++++++++++++++------ 1 files changed, 155 insertions(+), 19 deletions(-) Index: llvm/lib/Target/X86/X86RegisterInfo.cpp diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.137 llvm/lib/Target/X86/X86RegisterInfo.cpp:1.138 --- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.137 Fri Apr 14 02:26:43 2006 +++ llvm/lib/Target/X86/X86RegisterInfo.cpp Fri Apr 14 18:33:27 2006 @@ -319,15 +319,9 @@ case X86::TEST8rr: return MakeMRInst(X86::TEST8mr ,FrameIndex, MI); case X86::TEST16rr: return MakeMRInst(X86::TEST16mr,FrameIndex, MI); case X86::TEST32rr: return MakeMRInst(X86::TEST32mr,FrameIndex, MI); - case X86::TEST8ri: return MakeMIInst(X86::TEST8mi ,FrameIndex, MI); - case X86::TEST16ri: return MakeMIInst(X86::TEST16mi,FrameIndex, MI); - case X86::TEST32ri: return MakeMIInst(X86::TEST32mi,FrameIndex, MI); case X86::CMP8rr: return MakeMRInst(X86::CMP8mr , FrameIndex, MI); case X86::CMP16rr: return MakeMRInst(X86::CMP16mr, FrameIndex, MI); case X86::CMP32rr: return MakeMRInst(X86::CMP32mr, FrameIndex, MI); - case X86::CMP8ri: return MakeMIInst(X86::CMP8mi , FrameIndex, MI); - case X86::CMP16ri: return MakeMIInst(X86::CMP16mi, FrameIndex, MI); - case X86::CMP32ri: return MakeMIInst(X86::CMP32mi, FrameIndex, MI); // Alias instructions case X86::MOV8r0: return MakeM0Inst(X86::MOV8mi, FrameIndex, MI); case X86::MOV16r0: return MakeM0Inst(X86::MOV16mi, FrameIndex, MI); @@ -338,13 +332,14 @@ // Scalar SSE instructions case X86::MOVSSrr: return MakeMRInst(X86::MOVSSmr, FrameIndex, MI); case X86::MOVSDrr: return MakeMRInst(X86::MOVSDmr, FrameIndex, MI); -#if 0 // Packed SSE instructions - // FIXME: Can't use these until we are spilling XMM registers to - // 128-bit locations. case X86::MOVAPSrr: return MakeMRInst(X86::MOVAPSmr, FrameIndex, MI); case X86::MOVAPDrr: return MakeMRInst(X86::MOVAPDmr, FrameIndex, MI); -#endif + case X86::MOVUPSrr: return MakeMRInst(X86::MOVUPSmr, FrameIndex, MI); + case X86::MOVUPDrr: return MakeMRInst(X86::MOVUPDmr, FrameIndex, MI); + // Alias packed SSE instructions + case X86::MOVPS2SSrr:return MakeMRInst(X86::MOVPS2SSmr, FrameIndex, MI); + case X86::MOVPDI2DIrr:return MakeMRInst(X86::MOVPDI2DImr, FrameIndex, MI); } } else if (i == 1) { switch(MI->getOpcode()) { @@ -402,6 +397,9 @@ case X86::TEST8rr: return MakeRMInst(X86::TEST8rm ,FrameIndex, MI); case X86::TEST16rr: return MakeRMInst(X86::TEST16rm,FrameIndex, MI); case X86::TEST32rr: return MakeRMInst(X86::TEST32rm,FrameIndex, MI); + case X86::TEST8ri: return MakeMIInst(X86::TEST8mi ,FrameIndex, MI); + case X86::TEST16ri: return MakeMIInst(X86::TEST16mi,FrameIndex, MI); + case X86::TEST32ri: return MakeMIInst(X86::TEST32mi,FrameIndex, MI); case X86::IMUL16rr: return MakeRMInst(X86::IMUL16rm,FrameIndex, MI); case X86::IMUL32rr: return MakeRMInst(X86::IMUL32rm,FrameIndex, MI); case X86::IMUL16rri: return MakeRMIInst(X86::IMUL16rmi, FrameIndex, MI); @@ -411,6 +409,11 @@ case X86::CMP8rr: return MakeRMInst(X86::CMP8rm , FrameIndex, MI); case X86::CMP16rr: return MakeRMInst(X86::CMP16rm, FrameIndex, MI); case X86::CMP32rr: return MakeRMInst(X86::CMP32rm, FrameIndex, MI); + case X86::CMP8ri: return MakeRMInst(X86::CMP8mi , FrameIndex, MI); + case X86::CMP16ri: return MakeMIInst(X86::CMP16mi, FrameIndex, MI); + case X86::CMP32ri: return MakeMIInst(X86::CMP32mi, FrameIndex, MI); + case X86::CMP16ri8: return MakeMIInst(X86::CMP16mi8, FrameIndex, MI); + case X86::CMP32ri8: return MakeRMInst(X86::CMP32mi8, FrameIndex, MI); case X86::MOVSX16rr8:return MakeRMInst(X86::MOVSX16rm8 , FrameIndex, MI); case X86::MOVSX32rr8:return MakeRMInst(X86::MOVSX32rm8, FrameIndex, MI); case X86::MOVSX32rr16:return MakeRMInst(X86::MOVSX32rm16, FrameIndex, MI); @@ -423,16 +426,22 @@ // Scalar SSE instructions case X86::MOVSSrr: return MakeRMInst(X86::MOVSSrm, FrameIndex, MI); case X86::MOVSDrr: return MakeRMInst(X86::MOVSDrm, FrameIndex, MI); + case X86::CVTSS2SIrr:return MakeRMInst(X86::CVTSS2SIrm, FrameIndex, MI); case X86::CVTTSS2SIrr:return MakeRMInst(X86::CVTTSS2SIrm, FrameIndex, MI); + case X86::CVTSD2SIrr:return MakeRMInst(X86::CVTSD2SIrm, FrameIndex, MI); case X86::CVTTSD2SIrr:return MakeRMInst(X86::CVTTSD2SIrm, FrameIndex, MI); case X86::CVTSS2SDrr:return MakeRMInst(X86::CVTSS2SDrm, FrameIndex, MI); case X86::CVTSD2SSrr:return MakeRMInst(X86::CVTSD2SSrm, FrameIndex, MI); case X86::CVTSI2SSrr:return MakeRMInst(X86::CVTSI2SSrm, FrameIndex, MI); case X86::CVTSI2SDrr:return MakeRMInst(X86::CVTSI2SDrm, FrameIndex, MI); + case X86::Int_CVTTSS2SIrr: + return MakeRMInst(X86::Int_CVTTSS2SIrm, FrameIndex, MI); + case X86::Int_CVTTSD2SIrr: + return MakeRMInst(X86::Int_CVTTSD2SIrm, FrameIndex, MI); + case X86::Int_CVTSI2SSrr: + return MakeRMInst(X86::Int_CVTSI2SSrm, FrameIndex, MI); case X86::SQRTSSr: return MakeRMInst(X86::SQRTSSm, FrameIndex, MI); case X86::SQRTSDr: return MakeRMInst(X86::SQRTSDm, FrameIndex, MI); - case X86::UCOMISSrr: return MakeRMInst(X86::UCOMISSrm, FrameIndex, MI); - case X86::UCOMISDrr: return MakeRMInst(X86::UCOMISDrm, FrameIndex, MI); case X86::ADDSSrr: return MakeRMInst(X86::ADDSSrm, FrameIndex, MI); case X86::ADDSDrr: return MakeRMInst(X86::ADDSDrm, FrameIndex, MI); case X86::MULSSrr: return MakeRMInst(X86::MULSSrm, FrameIndex, MI); @@ -443,10 +452,70 @@ case X86::SUBSDrr: return MakeRMInst(X86::SUBSDrm, FrameIndex, MI); case X86::CMPSSrr: return MakeRMInst(X86::CMPSSrm, FrameIndex, MI); case X86::CMPSDrr: return MakeRMInst(X86::CMPSDrm, FrameIndex, MI); -#if 0 + case X86::Int_CMPSSrr: return MakeRMInst(X86::Int_CMPSSrm, FrameIndex, MI); + case X86::Int_CMPSDrr: return MakeRMInst(X86::Int_CMPSDrm, FrameIndex, MI); + case X86::UCOMISSrr: return MakeRMInst(X86::UCOMISSrm, FrameIndex, MI); + case X86::UCOMISDrr: return MakeRMInst(X86::UCOMISDrm, FrameIndex, MI); + case X86::Int_UCOMISSrr: + return MakeRMInst(X86::Int_UCOMISSrm, FrameIndex, MI); + case X86::Int_UCOMISDrr: + return MakeRMInst(X86::Int_UCOMISDrm, FrameIndex, MI); + case X86::Int_COMISSrr: + return MakeRMInst(X86::Int_COMISSrm, FrameIndex, MI); + case X86::Int_COMISDrr: + return MakeRMInst(X86::Int_COMISDrm, FrameIndex, MI); + case X86::FsANDPSrr: return MakeRMInst(X86::FsANDPSrm, FrameIndex, MI); + case X86::FsANDPDrr: return MakeRMInst(X86::FsANDPDrm, FrameIndex, MI); + case X86::FsORPSrr: return MakeRMInst(X86::FsORPSrm, FrameIndex, MI); + case X86::FsORPDrr: return MakeRMInst(X86::FsORPDrm, FrameIndex, MI); + case X86::FsXORPSrr: return MakeRMInst(X86::FsXORPSrm, FrameIndex, MI); + case X86::FsXORPDrr: return MakeRMInst(X86::FsXORPDrm, FrameIndex, MI); + case X86::FsANDNPSrr: return MakeRMInst(X86::FsANDNPSrm, FrameIndex, MI); + case X86::FsANDNPDrr: return MakeRMInst(X86::FsANDNPDrm, FrameIndex, MI); // Packed SSE instructions - // FIXME: Can't use these until we are spilling XMM registers to - // 128-bit locations. + case X86::MOVAPSrr: return MakeRMInst(X86::MOVAPSrm, FrameIndex, MI); + case X86::MOVAPDrr: return MakeRMInst(X86::MOVAPDrm, FrameIndex, MI); + case X86::MOVUPSrr: return MakeRMInst(X86::MOVUPSrm, FrameIndex, MI); + case X86::MOVUPDrr: return MakeRMInst(X86::MOVUPDrm, FrameIndex, MI); + case X86::MOVSHDUPrr:return MakeRMInst(X86::MOVSHDUPrm, FrameIndex, MI); + case X86::MOVSLDUPrr:return MakeRMInst(X86::MOVSLDUPrm, FrameIndex, MI); + case X86::MOVDDUPrr: return MakeRMInst(X86::MOVDDUPrm, FrameIndex, MI); + case X86::CVTDQ2PSrr:return MakeRMInst(X86::CVTDQ2PSrm, FrameIndex, MI); + case X86::CVTDQ2PDrr:return MakeRMInst(X86::CVTDQ2PDrm, FrameIndex, MI); + case X86::CVTPS2DQrr:return MakeRMInst(X86::CVTPS2DQrm, FrameIndex, MI); + case X86::CVTTPS2DQrr:return MakeRMInst(X86::CVTTPS2DQrm, FrameIndex, MI); + case X86::CVTPD2DQrr:return MakeRMInst(X86::CVTPD2DQrm, FrameIndex, MI); + case X86::CVTTPD2DQrr:return MakeRMInst(X86::CVTTPD2DQrm, FrameIndex, MI); + case X86::CVTPS2PDrr:return MakeRMInst(X86::CVTPS2PDrm, FrameIndex, MI); + case X86::CVTPD2PSrr:return MakeRMInst(X86::CVTPD2PSrm, FrameIndex, MI); + case X86::Int_CVTSI2SDrr: + return MakeRMInst(X86::Int_CVTSI2SDrm, FrameIndex, MI); + case X86::Int_CVTSD2SSrr: + return MakeRMInst(X86::Int_CVTSD2SSrm, FrameIndex, MI); + case X86::Int_CVTSS2SDrr: + return MakeRMInst(X86::Int_CVTSS2SDrm, FrameIndex, MI); + case X86::ADDPSrr: return MakeRMInst(X86::ADDPSrm, FrameIndex, MI); + case X86::ADDPDrr: return MakeRMInst(X86::ADDPDrm, FrameIndex, MI); + case X86::SUBPSrr: return MakeRMInst(X86::SUBPSrm, FrameIndex, MI); + case X86::SUBPDrr: return MakeRMInst(X86::SUBPDrm, FrameIndex, MI); + case X86::MULPSrr: return MakeRMInst(X86::MULPSrm, FrameIndex, MI); + case X86::MULPDrr: return MakeRMInst(X86::MULPDrm, FrameIndex, MI); + case X86::DIVPSrr: return MakeRMInst(X86::DIVPSrm, FrameIndex, MI); + case X86::DIVPDrr: return MakeRMInst(X86::DIVPDrm, FrameIndex, MI); + case X86::ADDSUBPSrr:return MakeRMInst(X86::ADDSUBPSrm, FrameIndex, MI); + case X86::ADDSUBPDrr:return MakeRMInst(X86::ADDSUBPDrm, FrameIndex, MI); + case X86::HADDPSrr: return MakeRMInst(X86::HADDPSrm, FrameIndex, MI); + case X86::HADDPDrr: return MakeRMInst(X86::HADDPDrm, FrameIndex, MI); + case X86::HSUBPSrr: return MakeRMInst(X86::HSUBPSrm, FrameIndex, MI); + case X86::HSUBPDrr: return MakeRMInst(X86::HSUBPDrm, FrameIndex, MI); + case X86::SQRTPSr: return MakeRMInst(X86::SQRTPSm, FrameIndex, MI); + case X86::SQRTPDr: return MakeRMInst(X86::SQRTPDm, FrameIndex, MI); + case X86::RSQRTPSr: return MakeRMInst(X86::RSQRTPSm, FrameIndex, MI); + case X86::RCPPSr: return MakeRMInst(X86::RCPPSm, FrameIndex, MI); + case X86::MAXPSrr: return MakeRMInst(X86::MAXPSrm, FrameIndex, MI); + case X86::MAXPDrr: return MakeRMInst(X86::MAXPDrm, FrameIndex, MI); + case X86::MINPSrr: return MakeRMInst(X86::MINPSrm, FrameIndex, MI); + case X86::MINPDrr: return MakeRMInst(X86::MINPDrm, FrameIndex, MI); case X86::ANDPSrr: return MakeRMInst(X86::ANDPSrm, FrameIndex, MI); case X86::ANDPDrr: return MakeRMInst(X86::ANDPDrm, FrameIndex, MI); case X86::ORPSrr: return MakeRMInst(X86::ORPSrm, FrameIndex, MI); @@ -455,13 +524,80 @@ case X86::XORPDrr: return MakeRMInst(X86::XORPDrm, FrameIndex, MI); case X86::ANDNPSrr: return MakeRMInst(X86::ANDNPSrm, FrameIndex, MI); case X86::ANDNPDrr: return MakeRMInst(X86::ANDNPDrm, FrameIndex, MI); - case X86::MOVAPSrr: return MakeRMInst(X86::MOVAPSrm, FrameIndex, MI); - case X86::MOVAPDrr: return MakeRMInst(X86::MOVAPDrm, FrameIndex, MI); -#endif + case X86::CMPPSrr: return MakeRMInst(X86::CMPPSrm, FrameIndex, MI); + case X86::CMPPDrr: return MakeRMInst(X86::CMPPDrm, FrameIndex, MI); + case X86::SHUFPSrr: return MakeRMInst(X86::SHUFPSrm, FrameIndex, MI); + case X86::SHUFPDrr: return MakeRMInst(X86::SHUFPDrm, FrameIndex, MI); + case X86::UNPCKHPSrr:return MakeRMInst(X86::UNPCKHPSrm, FrameIndex, MI); + case X86::UNPCKHPDrr:return MakeRMInst(X86::UNPCKHPDrm, FrameIndex, MI); + case X86::UNPCKLPSrr:return MakeRMInst(X86::UNPCKLPSrm, FrameIndex, MI); + case X86::UNPCKLPDrr:return MakeRMInst(X86::UNPCKLPDrm, FrameIndex, MI); + case X86::PADDBrr: return MakeRMInst(X86::PADDBrm, FrameIndex, MI); + case X86::PADDWrr: return MakeRMInst(X86::PADDWrm, FrameIndex, MI); + case X86::PADDDrr: return MakeRMInst(X86::PADDDrm, FrameIndex, MI); + case X86::PADDSBrr: return MakeRMInst(X86::PADDSBrm, FrameIndex, MI); + case X86::PADDSWrr: return MakeRMInst(X86::PADDSWrm, FrameIndex, MI); + case X86::PSUBBrr: return MakeRMInst(X86::PSUBBrm, FrameIndex, MI); + case X86::PSUBWrr: return MakeRMInst(X86::PSUBWrm, FrameIndex, MI); + case X86::PSUBDrr: return MakeRMInst(X86::PSUBDrm, FrameIndex, MI); + case X86::PSUBSBrr: return MakeRMInst(X86::PSUBSBrm, FrameIndex, MI); + case X86::PSUBSWrr: return MakeRMInst(X86::PSUBSWrm, FrameIndex, MI); + case X86::PMULHUWrr: return MakeRMInst(X86::PMULHUWrm, FrameIndex, MI); + case X86::PMULHWrr: return MakeRMInst(X86::PMULHWrm, FrameIndex, MI); + case X86::PMULLWrr: return MakeRMInst(X86::PMULLWrm, FrameIndex, MI); + case X86::PMULUDQrr: return MakeRMInst(X86::PMULUDQrm, FrameIndex, MI); + case X86::PMADDWDrr: return MakeRMInst(X86::PMADDWDrm, FrameIndex, MI); + case X86::PAVGBrr: return MakeRMInst(X86::PAVGBrm, FrameIndex, MI); + case X86::PAVGWrr: return MakeRMInst(X86::PAVGWrm, FrameIndex, MI); + case X86::PMAXUBrr: return MakeRMInst(X86::PMAXUBrm, FrameIndex, MI); + case X86::PMAXSWrr: return MakeRMInst(X86::PMAXSWrm, FrameIndex, MI); + case X86::PMINUBrr: return MakeRMInst(X86::PMINUBrm, FrameIndex, MI); + case X86::PMINSWrr: return MakeRMInst(X86::PMINSWrm, FrameIndex, MI); + case X86::PSADBWrr: return MakeRMInst(X86::PSADBWrm, FrameIndex, MI); + case X86::PSLLWrr: return MakeRMInst(X86::PSLLWrm, FrameIndex, MI); + case X86::PSLLDrr: return MakeRMInst(X86::PSLLDrm, FrameIndex, MI); + case X86::PSLLQrr: return MakeRMInst(X86::PSLLQrm, FrameIndex, MI); + case X86::PSRLWrr: return MakeRMInst(X86::PSRLWrm, FrameIndex, MI); + case X86::PSRLDrr: return MakeRMInst(X86::PSRLDrm, FrameIndex, MI); + case X86::PSRLQrr: return MakeRMInst(X86::PSRLQrm, FrameIndex, MI); + case X86::PSRAWrr: return MakeRMInst(X86::PSRAWrm, FrameIndex, MI); + case X86::PSRADrr: return MakeRMInst(X86::PSRADrm, FrameIndex, MI); + case X86::PANDrr: return MakeRMInst(X86::PANDrm, FrameIndex, MI); + case X86::PORrr: return MakeRMInst(X86::PORrm, FrameIndex, MI); + case X86::PXORrr: return MakeRMInst(X86::PXORrm, FrameIndex, MI); + case X86::PANDNrr: return MakeRMInst(X86::PANDNrm, FrameIndex, MI); + case X86::PCMPEQBrr: return MakeRMInst(X86::PCMPEQBrm, FrameIndex, MI); + case X86::PCMPEQWrr: return MakeRMInst(X86::PCMPEQWrm, FrameIndex, MI); + case X86::PCMPEQDrr: return MakeRMInst(X86::PCMPEQDrm, FrameIndex, MI); + case X86::PCMPGTBrr: return MakeRMInst(X86::PCMPGTBrm, FrameIndex, MI); + case X86::PCMPGTWrr: return MakeRMInst(X86::PCMPGTWrm, FrameIndex, MI); + case X86::PCMPGTDrr: return MakeRMInst(X86::PCMPGTDrm, FrameIndex, MI); + case X86::PACKSSWBrr:return MakeRMInst(X86::PACKSSWBrm, FrameIndex, MI); + case X86::PACKSSDWrr:return MakeRMInst(X86::PACKSSDWrm, FrameIndex, MI); + case X86::PACKUSWBrr:return MakeRMInst(X86::PACKUSWBrm, FrameIndex, MI); + case X86::PSHUFDri: return MakeRMInst(X86::PSHUFDmi, FrameIndex, MI); + case X86::PSHUFHWri: return MakeRMInst(X86::PSHUFHWmi, FrameIndex, MI); + case X86::PSHUFLWri: return MakeRMInst(X86::PSHUFLWmi, FrameIndex, MI); + case X86::PUNPCKLBWrr:return MakeRMInst(X86::PUNPCKLBWrm, FrameIndex, MI); + case X86::PUNPCKLWDrr:return MakeRMInst(X86::PUNPCKLWDrm, FrameIndex, MI); + case X86::PUNPCKLDQrr:return MakeRMInst(X86::PUNPCKLDQrm, FrameIndex, MI); + case X86::PUNPCKLQDQrr:return MakeRMInst(X86::PUNPCKLQDQrm, FrameIndex, MI); + case X86::PUNPCKHBWrr:return MakeRMInst(X86::PUNPCKHBWrm, FrameIndex, MI); + case X86::PUNPCKHWDrr:return MakeRMInst(X86::PUNPCKHWDrm, FrameIndex, MI); + case X86::PUNPCKHDQrr:return MakeRMInst(X86::PUNPCKHDQrm, FrameIndex, MI); + case X86::PUNPCKHQDQrr:return MakeRMInst(X86::PUNPCKHQDQrm, FrameIndex, MI); + case X86::PEXTRWri: return MakeRMInst(X86::PEXTRWmi, FrameIndex, MI); + case X86::PINSRWrri: return MakeRMInst(X86::PINSRWrmi, FrameIndex, MI); + // Alias packed SSE instructions + case X86::MOVSS2PSrr:return MakeRMInst(X86::MOVSS2PSrm, FrameIndex, MI); + case X86::MOVSD2PDrr:return MakeRMInst(X86::MOVSD2PDrm, FrameIndex, MI); + case X86::MOVDI2PDIrr:return MakeRMInst(X86::MOVDI2PDIrm, FrameIndex, MI); + case X86::MOVQI2PQIrr:return MakeRMInst(X86::MOVQI2PQIrm, FrameIndex, MI); } } if (PrintFailedFusing) - std::cerr << "We failed to fuse: " << *MI; + std::cerr << "We failed to fuse (" + << ((i == 1) ? "r" : "s") << "): " << *MI; return NULL; } From lattner at cs.uiuc.edu Fri Apr 14 20:39:57 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 14 Apr 2006 20:39:57 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp Message-ID: <200604150139.UAA22960@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: InstructionCombining.cpp updated: 1.465 -> 1.466 --- Log message: significant cleanups to code that uses insert/extractelt heavily. This builds maximal shuffles out of them where possible. --- Diffs of the changes: (+126 -0) InstructionCombining.cpp | 126 +++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 126 insertions(+) Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.465 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.466 --- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.465 Wed Apr 12 13:09:35 2006 +++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Fri Apr 14 20:39:45 2006 @@ -137,6 +137,7 @@ Instruction *visitStoreInst(StoreInst &SI); Instruction *visitBranchInst(BranchInst &BI); Instruction *visitSwitchInst(SwitchInst &SI); + Instruction *visitInsertElementInst(InsertElementInst &IE); Instruction *visitExtractElementInst(ExtractElementInst &EI); Instruction *visitShuffleVectorInst(ShuffleVectorInst &SVI); @@ -6915,6 +6916,126 @@ return 0; } +/// CollectShuffleElements - We are building a shuffle between V and RHSVec, +/// which are both packed values with identical types. Return a shuffle mask +/// that computes V. +static Value *CollectShuffleElements(Value *V, std::vector &Mask, + Value *RHSVec) { + assert(isa(V->getType()) && V->getType() == RHSVec->getType() && + "Invalid shuffle!"); + unsigned NumElts = cast(V->getType())->getNumElements(); + + if (isa(V)) { + Mask.assign(NumElts, UndefValue::get(Type::UIntTy)); + return V; + } else if (isa(V)) { + Mask.assign(NumElts, ConstantUInt::get(Type::UIntTy, 0)); + return V; + } else if (InsertElementInst *IEI = dyn_cast(V)) { + // If this is an insert of an extract from some other vector, include it. + Value *VecOp = IEI->getOperand(0); + Value *ScalarOp = IEI->getOperand(1); + Value *IdxOp = IEI->getOperand(2); + + if (ExtractElementInst *EI = dyn_cast(ScalarOp)) { + if (isa(EI->getOperand(1)) && isa(IdxOp) && + EI->getOperand(0)->getType() == V->getType()) { + unsigned ExtractedIdx = + cast(EI->getOperand(1))->getRawValue(); + unsigned InsertedIdx = cast(IdxOp)->getRawValue(); + + // Either the extracted from or inserted into vector must be RHSVec, + // otherwise we'd end up with a shuffle of three inputs. + if (EI->getOperand(0) == RHSVec) { + Value *V = CollectShuffleElements(VecOp, Mask, RHSVec); + Mask[InsertedIdx & (NumElts-1)] = + ConstantUInt::get(Type::UIntTy, NumElts+ExtractedIdx); + return V; + } + + if (VecOp == RHSVec) { + Value *V = CollectShuffleElements(EI->getOperand(0), Mask, RHSVec); + // Everything but the extracted element is replaced with the RHS. + for (unsigned i = 0; i != NumElts; ++i) { + if (i != InsertedIdx) + Mask[i] = ConstantUInt::get(Type::UIntTy, NumElts+i); + } + return V; + } + } + } + } + + + // Otherwise, can't do anything fancy. Return an identity vector. + for (unsigned i = 0; i != NumElts; ++i) + Mask.push_back(ConstantUInt::get(Type::UIntTy, i)); + return V; +} + +Instruction *InstCombiner::visitInsertElementInst(InsertElementInst &IE) { + Value *VecOp = IE.getOperand(0); + Value *ScalarOp = IE.getOperand(1); + Value *IdxOp = IE.getOperand(2); + + // If the inserted element was extracted from some other vector, and if the + // indexes are constant, try to turn this into a shufflevector operation. + if (ExtractElementInst *EI = dyn_cast(ScalarOp)) { + if (isa(EI->getOperand(1)) && isa(IdxOp) && + EI->getOperand(0)->getType() == IE.getType()) { + unsigned NumVectorElts = IE.getType()->getNumElements(); + unsigned ExtractedIdx=cast(EI->getOperand(1))->getRawValue(); + unsigned InsertedIdx = cast(IdxOp)->getRawValue(); + + if (ExtractedIdx >= NumVectorElts) // Out of range extract. + return ReplaceInstUsesWith(IE, VecOp); + + if (InsertedIdx >= NumVectorElts) // Out of range insert. + return ReplaceInstUsesWith(IE, UndefValue::get(IE.getType())); + + // If we are extracting a value from a vector, then inserting it right + // back into the same place, just use the input vector. + if (EI->getOperand(0) == VecOp && ExtractedIdx == InsertedIdx) + return ReplaceInstUsesWith(IE, VecOp); + + // We could theoretically do this for ANY input. However, doing so could + // turn chains of insertelement instructions into a chain of shufflevector + // instructions, and right now we do not merge shufflevectors. As such, + // only do this in a situation where it is clear that there is benefit. + if (isa(VecOp) || isa(VecOp)) { + // Turn this into shuffle(EIOp0, VecOp, Mask). The result has all of + // the values of VecOp, except then one read from EIOp0. + // Build a new shuffle mask. + std::vector Mask; + if (isa(VecOp)) + Mask.assign(NumVectorElts, UndefValue::get(Type::UIntTy)); + else { + assert(isa(VecOp) && "Unknown thing"); + Mask.assign(NumVectorElts, ConstantUInt::get(Type::UIntTy, + NumVectorElts)); + } + Mask[InsertedIdx] = ConstantUInt::get(Type::UIntTy, ExtractedIdx); + return new ShuffleVectorInst(EI->getOperand(0), VecOp, + ConstantPacked::get(Mask)); + } + + // If this insertelement isn't used by some other insertelement, turn it + // (and any insertelements it points to), into one big shuffle. + if (!IE.hasOneUse() || !isa(IE.use_back())) { + std::vector Mask; + Value *InVecA = CollectShuffleElements(&IE, Mask, EI->getOperand(0)); + + // We now have a shuffle of InVecA, VecOp, Mask. + return new ShuffleVectorInst(InVecA, EI->getOperand(0), + ConstantPacked::get(Mask)); + } + } + } + + return 0; +} + + Instruction *InstCombiner::visitShuffleVectorInst(ShuffleVectorInst &SVI) { Value *LHS = SVI.getOperand(0); Value *RHS = SVI.getOperand(1); @@ -6925,6 +7046,11 @@ if (isa(Mask)) return ReplaceInstUsesWith(SVI, UndefValue::get(SVI.getType())); + // TODO: Canonicalize shuffle(undef,x) -> shuffle(x, undef). + + // TODO: If we have shuffle(x, undef, mask) and any elements of mask refer to + // the undef, change them to undefs. + // Canonicalize shuffle(x,x) -> shuffle(x,undef) if (LHS == RHS) { if (isa(LHS)) { From evan.cheng at apple.com Fri Apr 14 22:13:36 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 14 Apr 2006 22:13:36 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp Message-ID: <200604150313.WAA24000@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.166 -> 1.167 --- Log message: Do not use movs{h|l}dup for a shuffle with a single non-undef node. --- Diffs of the changes: (+14 -2) X86ISelLowering.cpp | 16 ++++++++++++++-- 1 files changed, 14 insertions(+), 2 deletions(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.166 llvm/lib/Target/X86/X86ISelLowering.cpp:1.167 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.166 Fri Apr 14 16:59:03 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Fri Apr 14 22:13:24 2006 @@ -1724,12 +1724,14 @@ return false; // Expect 1, 1, 3, 3 + unsigned NumNodes = 0; for (unsigned i = 0; i < 2; ++i) { SDOperand Arg = N->getOperand(i); if (Arg.getOpcode() == ISD::UNDEF) continue; assert(isa(Arg) && "Invalid VECTOR_SHUFFLE mask!"); unsigned Val = cast(Arg)->getValue(); if (Val != 1) return false; + NumNodes++; } for (unsigned i = 2; i < 4; ++i) { SDOperand Arg = N->getOperand(i); @@ -1737,8 +1739,12 @@ assert(isa(Arg) && "Invalid VECTOR_SHUFFLE mask!"); unsigned Val = cast(Arg)->getValue(); if (Val != 3) return false; + NumNodes++; } - return true; + + // Don't use movshdup if the resulting vector contains only one undef node. + // Use {p}shuf* instead. + return NumNodes > 1; } /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand @@ -1750,12 +1756,14 @@ return false; // Expect 0, 0, 2, 2 + unsigned NumNodes = 0; for (unsigned i = 0; i < 2; ++i) { SDOperand Arg = N->getOperand(i); if (Arg.getOpcode() == ISD::UNDEF) continue; assert(isa(Arg) && "Invalid VECTOR_SHUFFLE mask!"); unsigned Val = cast(Arg)->getValue(); if (Val != 0) return false; + NumNodes++; } for (unsigned i = 2; i < 4; ++i) { SDOperand Arg = N->getOperand(i); @@ -1763,8 +1771,12 @@ assert(isa(Arg) && "Invalid VECTOR_SHUFFLE mask!"); unsigned Val = cast(Arg)->getValue(); if (Val != 2) return false; + NumNodes++; } - return true; + + // Don't use movsldup if the resulting vector contains only one undef node. + // Use {p}shuf* instead. + return NumNodes > 1; } /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies From evan.cheng at apple.com Sat Apr 15 00:38:26 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Sat, 15 Apr 2006 00:38:26 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/README.txt X86ISelLowering.cpp X86InstrSSE.td Message-ID: <200604150538.AAA24939@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: README.txt updated: 1.88 -> 1.89 X86ISelLowering.cpp updated: 1.167 -> 1.168 X86InstrSSE.td updated: 1.91 -> 1.92 --- Log message: Silly bug --- Diffs of the changes: (+11 -18) README.txt | 5 ----- X86ISelLowering.cpp | 22 ++++++++++------------ X86InstrSSE.td | 2 +- 3 files changed, 11 insertions(+), 18 deletions(-) Index: llvm/lib/Target/X86/README.txt diff -u llvm/lib/Target/X86/README.txt:1.88 llvm/lib/Target/X86/README.txt:1.89 --- llvm/lib/Target/X86/README.txt:1.88 Fri Apr 14 02:24:04 2006 +++ llvm/lib/Target/X86/README.txt Sat Apr 15 00:37:34 2006 @@ -810,8 +810,3 @@ How about andps, andpd, and pand? Do we really care about the type of the packed elements? If not, why not always use the "ps" variants which are likely to be shorter. - -//===---------------------------------------------------------------------===// - -Make sure XMM registers are spilled to 128-bit locations (if not already) and -add vector SSE opcodes to X86RegisterInfo::foldMemoryOperand(). Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.167 llvm/lib/Target/X86/X86ISelLowering.cpp:1.168 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.167 Fri Apr 14 22:13:24 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Sat Apr 15 00:37:34 2006 @@ -1724,27 +1724,26 @@ return false; // Expect 1, 1, 3, 3 - unsigned NumNodes = 0; for (unsigned i = 0; i < 2; ++i) { SDOperand Arg = N->getOperand(i); if (Arg.getOpcode() == ISD::UNDEF) continue; assert(isa(Arg) && "Invalid VECTOR_SHUFFLE mask!"); unsigned Val = cast(Arg)->getValue(); if (Val != 1) return false; - NumNodes++; } + + bool HasHi = false; for (unsigned i = 2; i < 4; ++i) { SDOperand Arg = N->getOperand(i); if (Arg.getOpcode() == ISD::UNDEF) continue; assert(isa(Arg) && "Invalid VECTOR_SHUFFLE mask!"); unsigned Val = cast(Arg)->getValue(); if (Val != 3) return false; - NumNodes++; + HasHi = true; } - // Don't use movshdup if the resulting vector contains only one undef node. - // Use {p}shuf* instead. - return NumNodes > 1; + // Don't use movshdup if it can be done with a shufps. + return HasHi; } /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand @@ -1756,27 +1755,26 @@ return false; // Expect 0, 0, 2, 2 - unsigned NumNodes = 0; for (unsigned i = 0; i < 2; ++i) { SDOperand Arg = N->getOperand(i); if (Arg.getOpcode() == ISD::UNDEF) continue; assert(isa(Arg) && "Invalid VECTOR_SHUFFLE mask!"); unsigned Val = cast(Arg)->getValue(); if (Val != 0) return false; - NumNodes++; } + + bool HasHi = false; for (unsigned i = 2; i < 4; ++i) { SDOperand Arg = N->getOperand(i); if (Arg.getOpcode() == ISD::UNDEF) continue; assert(isa(Arg) && "Invalid VECTOR_SHUFFLE mask!"); unsigned Val = cast(Arg)->getValue(); if (Val != 2) return false; - NumNodes++; + HasHi = true; } - // Don't use movsldup if the resulting vector contains only one undef node. - // Use {p}shuf* instead. - return NumNodes > 1; + // Don't use movshdup if it can be done with a shufps. + return HasHi; } /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.91 llvm/lib/Target/X86/X86InstrSSE.td:1.92 --- llvm/lib/Target/X86/X86InstrSSE.td:1.91 Fri Apr 14 18:32:40 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Sat Apr 15 00:37:34 2006 @@ -169,7 +169,7 @@ // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes. // S3I - SSE3 instructions with TB and OpSize prefixes. // S3SI - SSE3 instructions with XS prefix. -// S3SI - SSE3 instructions with XD prefix. +// S3DI - SSE3 instructions with XD prefix. class SSI o, Format F, dag ops, string asm, list pattern> : I, XS, Requires<[HasSSE1]>; class SDI o, Format F, dag ops, string asm, list pattern> From evan.cheng at apple.com Sat Apr 15 00:53:32 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Sat, 15 Apr 2006 00:53:32 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td Message-ID: <200604150553.AAA25055@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrSSE.td updated: 1.92 -> 1.93 --- Log message: hsubp{s|d} encoding bug --- Diffs of the changes: (+4 -4) X86InstrSSE.td | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.92 llvm/lib/Target/X86/X86InstrSSE.td:1.93 --- llvm/lib/Target/X86/X86InstrSSE.td:1.92 Sat Apr 15 00:37:34 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Sat Apr 15 00:52:42 2006 @@ -1305,13 +1305,13 @@ int_x86_sse3_hadd_pd>; def HADDPDrm : S3_Intrm<0x7C, "haddpd {$src2, $dst|$dst, $src2}", int_x86_sse3_hadd_pd>; -def HSUBPSrr : S3D_Intrr<0x7C, "hsubps {$src2, $dst|$dst, $src2}", +def HSUBPSrr : S3D_Intrr<0x7D, "hsubps {$src2, $dst|$dst, $src2}", int_x86_sse3_hsub_ps>; -def HSUBPSrm : S3D_Intrm<0x7C, "hsubps {$src2, $dst|$dst, $src2}", +def HSUBPSrm : S3D_Intrm<0x7D, "hsubps {$src2, $dst|$dst, $src2}", int_x86_sse3_hsub_ps>; -def HSUBPDrr : S3_Intrr<0x7C, "hsubpd {$src2, $dst|$dst, $src2}", +def HSUBPDrr : S3_Intrr<0x7D, "hsubpd {$src2, $dst|$dst, $src2}", int_x86_sse3_hsub_pd>; -def HSUBPDrm : S3_Intrm<0x7C, "hsubpd {$src2, $dst|$dst, $src2}", +def HSUBPDrm : S3_Intrm<0x7D, "hsubpd {$src2, $dst|$dst, $src2}", int_x86_sse3_hsub_pd>; } From evan.cheng at apple.com Sat Apr 15 01:00:00 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Sat, 15 Apr 2006 01:00:00 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td Message-ID: <200604150600.BAA25085@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrSSE.td updated: 1.93 -> 1.94 --- Log message: pslldrm, psrawrm, etc. encoding bug --- Diffs of the changes: (+8 -8) X86InstrSSE.td | 16 ++++++++-------- 1 files changed, 8 insertions(+), 8 deletions(-) Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.93 llvm/lib/Target/X86/X86InstrSSE.td:1.94 --- llvm/lib/Target/X86/X86InstrSSE.td:1.93 Sat Apr 15 00:52:42 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Sat Apr 15 00:59:08 2006 @@ -1600,7 +1600,7 @@ "psllw {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse2_psll_w VR128:$src1, VR128:$src2))]>; -def PSLLWrm : PDIi8<0xF1, MRMSrcReg, (ops VR128:$dst, VR128:$src1, i128mem:$src2), +def PSLLWrm : PDIi8<0xF1, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), "psllw {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse2_psll_w VR128:$src1, (bc_v4i32 (loadv2i64 addr:$src2))))]>; @@ -1612,7 +1612,7 @@ "pslld {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse2_psll_d VR128:$src1, VR128:$src2))]>; -def PSLLDrm : PDIi8<0xF2, MRMSrcReg, (ops VR128:$dst, VR128:$src1, i128mem:$src2), +def PSLLDrm : PDIi8<0xF2, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), "pslld {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse2_psll_d VR128:$src1, (bc_v4i32 (loadv2i64 addr:$src2))))]>; @@ -1624,7 +1624,7 @@ "psllq {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse2_psll_q VR128:$src1, VR128:$src2))]>; -def PSLLQrm : PDIi8<0xF3, MRMSrcReg, (ops VR128:$dst, VR128:$src1, i128mem:$src2), +def PSLLQrm : PDIi8<0xF3, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), "psllq {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse2_psll_q VR128:$src1, (bc_v4i32 (loadv2i64 addr:$src2))))]>; @@ -1639,7 +1639,7 @@ "psrlw {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse2_psrl_w VR128:$src1, VR128:$src2))]>; -def PSRLWrm : PDIi8<0xD1, MRMSrcReg, (ops VR128:$dst, VR128:$src1, i128mem:$src2), +def PSRLWrm : PDIi8<0xD1, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), "psrlw {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse2_psrl_w VR128:$src1, (bc_v4i32 (loadv2i64 addr:$src2))))]>; @@ -1651,7 +1651,7 @@ "psrld {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse2_psrl_d VR128:$src1, VR128:$src2))]>; -def PSRLDrm : PDIi8<0xD2, MRMSrcReg, (ops VR128:$dst, VR128:$src1, i128mem:$src2), +def PSRLDrm : PDIi8<0xD2, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), "psrld {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse2_psrl_d VR128:$src1, (bc_v4i32 (loadv2i64 addr:$src2))))]>; @@ -1663,7 +1663,7 @@ "psrlq {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse2_psrl_q VR128:$src1, VR128:$src2))]>; -def PSRLQrm : PDIi8<0xD3, MRMSrcReg, (ops VR128:$dst, VR128:$src1, i128mem:$src2), +def PSRLQrm : PDIi8<0xD3, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), "psrlq {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse2_psrl_q VR128:$src1, (bc_v4i32 (loadv2i64 addr:$src2))))]>; @@ -1678,7 +1678,7 @@ "psraw {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse2_psra_w VR128:$src1, VR128:$src2))]>; -def PSRAWrm : PDIi8<0xE1, MRMSrcReg, (ops VR128:$dst, VR128:$src1, i128mem:$src2), +def PSRAWrm : PDIi8<0xE1, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), "psraw {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse2_psra_w VR128:$src1, (bc_v4i32 (loadv2i64 addr:$src2))))]>; @@ -1690,7 +1690,7 @@ "psrad {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse2_psra_d VR128:$src1, VR128:$src2))]>; -def PSRADrm : PDIi8<0xE2, MRMSrcReg, (ops VR128:$dst, VR128:$src1, i128mem:$src2), +def PSRADrm : PDIi8<0xE2, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), "psrad {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse2_psra_d VR128:$src1, (bc_v4i32 (loadv2i64 addr:$src2))))]>; From evan.cheng at apple.com Sat Apr 15 01:11:01 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Sat, 15 Apr 2006 01:11:01 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td Message-ID: <200604150611.BAA25178@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrSSE.td updated: 1.94 -> 1.95 --- Log message: More encoding bugs --- Diffs of the changes: (+8 -8) X86InstrSSE.td | 16 ++++++++-------- 1 files changed, 8 insertions(+), 8 deletions(-) Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.94 llvm/lib/Target/X86/X86InstrSSE.td:1.95 --- llvm/lib/Target/X86/X86InstrSSE.td:1.94 Sat Apr 15 00:59:08 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Sat Apr 15 01:10:09 2006 @@ -1745,7 +1745,7 @@ "pcmpeqb {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse2_pcmpeq_b VR128:$src1, VR128:$src2))]>; -def PCMPEQBrm : PDI<0x74, MRMSrcReg, +def PCMPEQBrm : PDI<0x74, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), "pcmpeqb {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse2_pcmpeq_b VR128:$src1, @@ -1755,7 +1755,7 @@ "pcmpeqw {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse2_pcmpeq_w VR128:$src1, VR128:$src2))]>; -def PCMPEQWrm : PDI<0x75, MRMSrcReg, +def PCMPEQWrm : PDI<0x75, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), "pcmpeqw {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse2_pcmpeq_w VR128:$src1, @@ -1765,7 +1765,7 @@ "pcmpeqd {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse2_pcmpeq_d VR128:$src1, VR128:$src2))]>; -def PCMPEQDrm : PDI<0x76, MRMSrcReg, +def PCMPEQDrm : PDI<0x76, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), "pcmpeqd {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse2_pcmpeq_d VR128:$src1, @@ -1776,7 +1776,7 @@ "pcmpgtb {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse2_pcmpgt_b VR128:$src1, VR128:$src2))]>; -def PCMPGTBrm : PDI<0x64, MRMSrcReg, +def PCMPGTBrm : PDI<0x64, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), "pcmpgtb {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse2_pcmpgt_b VR128:$src1, @@ -1786,7 +1786,7 @@ "pcmpgtw {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse2_pcmpgt_w VR128:$src1, VR128:$src2))]>; -def PCMPGTWrm : PDI<0x65, MRMSrcReg, +def PCMPGTWrm : PDI<0x65, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), "pcmpgtw {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse2_pcmpgt_w VR128:$src1, @@ -1796,7 +1796,7 @@ "pcmpgtd {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse2_pcmpgt_d VR128:$src1, VR128:$src2))]>; -def PCMPGTDrm : PDI<0x66, MRMSrcReg, +def PCMPGTDrm : PDI<0x66, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), "pcmpgtd {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse2_pcmpgt_d VR128:$src1, @@ -1823,7 +1823,7 @@ [(set VR128:$dst, (v4i32 (int_x86_sse2_packssdw_128 VR128:$src1, VR128:$src2)))]>; -def PACKSSDWrm : PDI<0x6B, MRMSrcReg, (ops VR128:$dst, VR128:$src1, +def PACKSSDWrm : PDI<0x6B, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), "packssdw {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v4i32 (int_x86_sse2_packssdw_128 @@ -1835,7 +1835,7 @@ [(set VR128:$dst, (v8i16 (int_x86_sse2_packuswb_128 VR128:$src1, VR128:$src2)))]>; -def PACKUSWBrm : PDI<0x67, MRMSrcReg, (ops VR128:$dst, VR128:$src1, +def PACKUSWBrm : PDI<0x67, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2), "packuswb {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (v8i16 (int_x86_sse2_packuswb_128 From lattner at cs.uiuc.edu Sat Apr 15 18:38:12 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 15 Apr 2006 18:38:12 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Message-ID: <200604152338.SAA10705@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAG.cpp updated: 1.299 -> 1.300 --- Log message: Make these predicates return true for bit_convert(buildvector)'s as well as buildvectors. --- Diffs of the changes: (+8 -0) SelectionDAG.cpp | 8 ++++++++ 1 files changed, 8 insertions(+) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.299 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.300 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.299 Wed Apr 12 11:20:43 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Sat Apr 15 18:38:00 2006 @@ -73,6 +73,10 @@ /// isBuildVectorAllOnes - Return true if the specified node is a /// BUILD_VECTOR where all of the elements are ~0 or undef. bool ISD::isBuildVectorAllOnes(const SDNode *N) { + // Look through a bit convert. + if (N->getOpcode() == ISD::BIT_CONVERT) + N = N->getOperand(0).Val; + if (N->getOpcode() != ISD::BUILD_VECTOR) return false; unsigned i = 0, e = N->getNumOperands(); @@ -117,6 +121,10 @@ /// isBuildVectorAllZeros - Return true if the specified node is a /// BUILD_VECTOR where all of the elements are 0 or undef. bool ISD::isBuildVectorAllZeros(const SDNode *N) { + // Look through a bit convert. + if (N->getOpcode() == ISD::BIT_CONVERT) + N = N->getOperand(0).Val; + if (N->getOpcode() != ISD::BUILD_VECTOR) return false; unsigned i = 0, e = N->getNumOperands(); From lattner at cs.uiuc.edu Sat Apr 15 18:39:26 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 15 Apr 2006 18:39:26 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td Message-ID: <200604152339.SAA10770@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target: TargetSelectionDAG.td updated: 1.63 -> 1.64 --- Log message: Add a new vnot_conv predicate for matching vnot's where the allones vector is bitconverted from some other type. --- Diffs of the changes: (+6 -0) TargetSelectionDAG.td | 6 ++++++ 1 files changed, 6 insertions(+) Index: llvm/lib/Target/TargetSelectionDAG.td diff -u llvm/lib/Target/TargetSelectionDAG.td:1.63 llvm/lib/Target/TargetSelectionDAG.td:1.64 --- llvm/lib/Target/TargetSelectionDAG.td:1.63 Fri Mar 31 13:21:16 2006 +++ llvm/lib/Target/TargetSelectionDAG.td Sat Apr 15 18:39:14 2006 @@ -394,9 +394,15 @@ return ISD::isBuildVectorAllZeros(N); }]>; +def immAllOnesV_bc: PatLeaf<(bitconvert), [{ + return ISD::isBuildVectorAllOnes(N); +}]>; + + // Other helper fragments. def not : PatFrag<(ops node:$in), (xor node:$in, immAllOnes)>; def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>; +def vnot_conv : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV_bc)>; def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>; // extending load & truncstore fragments. From lattner at cs.uiuc.edu Sat Apr 15 18:45:36 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 15 Apr 2006 18:45:36 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrAltivec.td Message-ID: <200604152345.SAA10954@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCInstrAltivec.td updated: 1.49 -> 1.50 --- Log message: Add patterns for matching vnots with bit converted inputs. Most of these will go away when I start using evan's binop type canonicalizer --- Diffs of the changes: (+17 -0) PPCInstrAltivec.td | 17 +++++++++++++++++ 1 files changed, 17 insertions(+) Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.49 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.50 --- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.49 Wed Apr 12 12:37:20 2006 +++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td Sat Apr 15 18:45:24 2006 @@ -607,10 +607,16 @@ def : Pat<(v8i16 (vnot VRRC:$vA)), (v8i16 (VNOR VRRC:$vA, VRRC:$vA))>; def : Pat<(v4i32 (vnot VRRC:$vA)), (v4i32 (VNOR VRRC:$vA, VRRC:$vA))>; +def : Pat<(v16i8 (vnot_conv VRRC:$vA)), (v16i8 (VNOR VRRC:$vA, VRRC:$vA))>; +def : Pat<(v8i16 (vnot_conv VRRC:$vA)), (v8i16 (VNOR VRRC:$vA, VRRC:$vA))>; +def : Pat<(v4i32 (vnot_conv VRRC:$vA)), (v4i32 (VNOR VRRC:$vA, VRRC:$vA))>; + + def : Pat<(v16i8 (and VRRC:$A, VRRC:$B)), (v16i8 (VAND VRRC:$A, VRRC:$B))>; def : Pat<(v8i16 (and VRRC:$A, VRRC:$B)), (v8i16 (VAND VRRC:$A, VRRC:$B))>; def : Pat<(v16i8 (or VRRC:$A, VRRC:$B)), (v16i8 (VOR VRRC:$A, VRRC:$B))>; def : Pat<(v8i16 (or VRRC:$A, VRRC:$B)), (v8i16 (VOR VRRC:$A, VRRC:$B))>; + def : Pat<(v16i8 (xor VRRC:$A, VRRC:$B)), (v16i8 (VXOR VRRC:$A, VRRC:$B))>; def : Pat<(v8i16 (xor VRRC:$A, VRRC:$B)), (v8i16 (VXOR VRRC:$A, VRRC:$B))>; def : Pat<(v16i8 (vnot (or VRRC:$A, VRRC:$B))),(v16i8 (VNOR VRRC:$A, VRRC:$B))>; @@ -620,6 +626,17 @@ def : Pat<(v8i16 (and VRRC:$A, (vnot VRRC:$B))), (v8i16 (VANDC VRRC:$A, VRRC:$B))>; + +def : Pat<(v16i8 (vnot_conv (or VRRC:$A, VRRC:$B))),(v16i8 (VNOR VRRC:$A, VRRC:$B))>; +def : Pat<(v8i16 (vnot_conv (or VRRC:$A, VRRC:$B))),(v8i16 (VNOR VRRC:$A, VRRC:$B))>; +def : Pat<(v4i32 (vnot_conv (or VRRC:$A, VRRC:$B))),(v4i32 (VNOR VRRC:$A, VRRC:$B))>; +def : Pat<(v16i8 (and VRRC:$A, (vnot_conv VRRC:$B))), + (v16i8 (VANDC VRRC:$A, VRRC:$B))>; +def : Pat<(v8i16 (and VRRC:$A, (vnot_conv VRRC:$B))), + (v8i16 (VANDC VRRC:$A, VRRC:$B))>; +def : Pat<(v4i32 (and VRRC:$A, (vnot_conv VRRC:$B))), + (v4i32 (VANDC VRRC:$A, VRRC:$B))>; + def : Pat<(fmul VRRC:$vA, VRRC:$vB), (VMADDFP VRRC:$vA, VRRC:$vB, (v4i32 (V_SET0)))>; From lattner at cs.uiuc.edu Sat Apr 15 18:48:17 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 15 Apr 2006 18:48:17 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp Message-ID: <200604152348.SAA11044@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.151 -> 1.152 --- Log message: Fix a crash when faced with a shuffle vector that has an undef in its mask. --- Diffs of the changes: (+5 -1) PPCISelLowering.cpp | 6 +++++- 1 files changed, 5 insertions(+), 1 deletion(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.151 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.152 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.151 Fri Apr 14 18:19:08 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Sat Apr 15 18:48:05 2006 @@ -1116,7 +1116,11 @@ std::vector ResultMask; for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) { - unsigned SrcElt =cast(PermMask.getOperand(i))->getValue(); + unsigned SrcElt; + if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF) + SrcElt = 0; + else + SrcElt = cast(PermMask.getOperand(i))->getValue(); for (unsigned j = 0; j != BytesPerElement; ++j) ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j, From lattner at cs.uiuc.edu Sat Apr 15 19:04:08 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 15 Apr 2006 19:04:08 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp Message-ID: <200604160004.TAA11322@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: InstructionCombining.cpp updated: 1.466 -> 1.467 --- Log message: Canonicalize shuffle(undef,x,mask) -> shuffle(x, undef,mask'). --- Diffs of the changes: (+22 -2) InstructionCombining.cpp | 24 ++++++++++++++++++++++-- 1 files changed, 22 insertions(+), 2 deletions(-) Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.466 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.467 --- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.466 Fri Apr 14 20:39:45 2006 +++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Sat Apr 15 19:03:56 2006 @@ -7046,8 +7046,6 @@ if (isa(Mask)) return ReplaceInstUsesWith(SVI, UndefValue::get(SVI.getType())); - // TODO: Canonicalize shuffle(undef,x) -> shuffle(x, undef). - // TODO: If we have shuffle(x, undef, mask) and any elements of mask refer to // the undef, change them to undefs. @@ -7077,6 +7075,28 @@ MadeChange = true; } + // Canonicalize shuffle(undef,x,mask) -> shuffle(x, undef,mask'). + if (isa(LHS)) { + // shuffle(undef,x,<0,0,0,0>) -> undef. + if (isa(Mask)) + return ReplaceInstUsesWith(SVI, UndefValue::get(SVI.getType())); + + ConstantPacked *CPM = cast(Mask); + std::vector Elts; + for (unsigned i = 0, e = CPM->getNumOperands(); i != e; ++i) { + if (isa(CPM->getOperand(i))) + Elts.push_back(CPM->getOperand(i)); + else { + unsigned EltNo = cast(CPM->getOperand(i))->getRawValue(); + if (EltNo >= e/2) + Elts.push_back(ConstantUInt::get(Type::UIntTy, EltNo-e/2)); + else // Referring to the undef. + Elts.push_back(UndefValue::get(Type::UIntTy)); + } + } + return new ShuffleVectorInst(RHS, LHS, ConstantPacked::get(Elts)); + } + if (ConstantPacked *CP = dyn_cast(Mask)) { bool isLHSID = true, isRHSID = true; From lattner at cs.uiuc.edu Sat Apr 15 19:51:59 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 15 Apr 2006 19:51:59 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp Message-ID: <200604160051.TAA16071@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: InstructionCombining.cpp updated: 1.467 -> 1.468 --- Log message: Fix a bug in the 'shuffle(undef,x,mask) -> shuffle(x, undef,mask')' xform Make the insert/extract elt -> shuffle code more aggressive. This fixes CodeGen/PowerPC/vec_shuffle.ll --- Diffs of the changes: (+84 -17) InstructionCombining.cpp | 101 +++++++++++++++++++++++++++++++++++++++-------- 1 files changed, 84 insertions(+), 17 deletions(-) Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.467 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.468 --- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.467 Sat Apr 15 19:03:56 2006 +++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Sat Apr 15 19:51:47 2006 @@ -6916,12 +6916,72 @@ return 0; } -/// CollectShuffleElements - We are building a shuffle between V and RHSVec, -/// which are both packed values with identical types. Return a shuffle mask -/// that computes V. +/// CollectSingleShuffleElements - If V is a shuffle of values that ONLY returns +/// elements from either LHS or RHS, return the shuffle mask and true. +/// Otherwise, return false. +static bool CollectSingleShuffleElements(Value *V, Value *LHS, Value *RHS, + std::vector &Mask) { + assert(V->getType() == LHS->getType() && V->getType() == RHS->getType() && + "Invalid CollectSingleShuffleElements"); + unsigned NumElts = cast(V->getType())->getNumElements(); + + if (isa(V)) { + Mask.assign(NumElts, UndefValue::get(Type::UIntTy)); + return true; + } else if (V == LHS) { + for (unsigned i = 0; i != NumElts; ++i) + Mask.push_back(ConstantUInt::get(Type::UIntTy, i)); + return true; + } else if (V == RHS) { + for (unsigned i = 0; i != NumElts; ++i) + Mask.push_back(ConstantUInt::get(Type::UIntTy, i+NumElts)); + return true; + } else if (InsertElementInst *IEI = dyn_cast(V)) { + // If this is an insert of an extract from some other vector, include it. + Value *VecOp = IEI->getOperand(0); + Value *ScalarOp = IEI->getOperand(1); + Value *IdxOp = IEI->getOperand(2); + + if (ExtractElementInst *EI = dyn_cast(ScalarOp)) { + if (isa(EI->getOperand(1)) && isa(IdxOp) && + EI->getOperand(0)->getType() == V->getType()) { + unsigned ExtractedIdx = + cast(EI->getOperand(1))->getRawValue(); + unsigned InsertedIdx = cast(IdxOp)->getRawValue(); + + // This must be extracting from either LHS or RHS. + if (EI->getOperand(0) == LHS || EI->getOperand(0) == RHS) { + // Okay, we can handle this if the vector we are insertinting into is + // transitively ok. + if (CollectSingleShuffleElements(VecOp, LHS, RHS, Mask)) { + // If so, update the mask to reflect the inserted value. + if (EI->getOperand(0) == LHS) { + Mask[InsertedIdx & (NumElts-1)] = + ConstantUInt::get(Type::UIntTy, ExtractedIdx); + } else { + assert(EI->getOperand(0) == RHS); + Mask[InsertedIdx & (NumElts-1)] = + ConstantUInt::get(Type::UIntTy, ExtractedIdx+NumElts); + + } + return true; + } + } + } + } + } + // TODO: Handle shufflevector here! + + return false; +} + +/// CollectShuffleElements - We are building a shuffle of V, using RHS as the +/// RHS of the shuffle instruction, if it is not null. Return a shuffle mask +/// that computes V and the LHS value of the shuffle. static Value *CollectShuffleElements(Value *V, std::vector &Mask, - Value *RHSVec) { - assert(isa(V->getType()) && V->getType() == RHSVec->getType() && + Value *&RHS) { + assert(isa(V->getType()) && + (RHS == 0 || V->getType() == RHS->getType()) && "Invalid shuffle!"); unsigned NumElts = cast(V->getType())->getNumElements(); @@ -6946,15 +7006,16 @@ // Either the extracted from or inserted into vector must be RHSVec, // otherwise we'd end up with a shuffle of three inputs. - if (EI->getOperand(0) == RHSVec) { - Value *V = CollectShuffleElements(VecOp, Mask, RHSVec); + if (EI->getOperand(0) == RHS || RHS == 0) { + RHS = EI->getOperand(0); + Value *V = CollectShuffleElements(VecOp, Mask, RHS); Mask[InsertedIdx & (NumElts-1)] = ConstantUInt::get(Type::UIntTy, NumElts+ExtractedIdx); return V; } - if (VecOp == RHSVec) { - Value *V = CollectShuffleElements(EI->getOperand(0), Mask, RHSVec); + if (VecOp == RHS) { + Value *V = CollectShuffleElements(EI->getOperand(0), Mask, RHS); // Everything but the extracted element is replaced with the RHS. for (unsigned i = 0; i != NumElts; ++i) { if (i != InsertedIdx) @@ -6962,10 +7023,16 @@ } return V; } + + // If this insertelement is a chain that comes from exactly these two + // vectors, return the vector and the effective shuffle. + if (CollectSingleShuffleElements(IEI, EI->getOperand(0), RHS, Mask)) + return EI->getOperand(0); + } } } - + // TODO: Handle shufflevector here! // Otherwise, can't do anything fancy. Return an identity vector. for (unsigned i = 0; i != NumElts; ++i) @@ -7023,11 +7090,11 @@ // (and any insertelements it points to), into one big shuffle. if (!IE.hasOneUse() || !isa(IE.use_back())) { std::vector Mask; - Value *InVecA = CollectShuffleElements(&IE, Mask, EI->getOperand(0)); - - // We now have a shuffle of InVecA, VecOp, Mask. - return new ShuffleVectorInst(InVecA, EI->getOperand(0), - ConstantPacked::get(Mask)); + Value *RHS = 0; + Value *LHS = CollectShuffleElements(&IE, Mask, RHS); + if (RHS == 0) RHS = UndefValue::get(LHS->getType()); + // We now have a shuffle of LHS, RHS, Mask. + return new ShuffleVectorInst(LHS, RHS, ConstantPacked::get(Mask)); } } } @@ -7088,8 +7155,8 @@ Elts.push_back(CPM->getOperand(i)); else { unsigned EltNo = cast(CPM->getOperand(i))->getRawValue(); - if (EltNo >= e/2) - Elts.push_back(ConstantUInt::get(Type::UIntTy, EltNo-e/2)); + if (EltNo >= e) + Elts.push_back(ConstantUInt::get(Type::UIntTy, EltNo-e)); else // Referring to the undef. Elts.push_back(UndefValue::get(Type::UIntTy)); } From lattner at cs.uiuc.edu Sat Apr 15 20:01:41 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 15 Apr 2006 20:01:41 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp README_ALTIVEC.txt Message-ID: <200604160101.UAA17513@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.152 -> 1.153 README_ALTIVEC.txt updated: 1.22 -> 1.23 --- Log message: Make the BUILD_VECTOR lowering code much more aggressive w.r.t constant vectors. Remove some done items from the todo list. --- Diffs of the changes: (+106 -67) PPCISelLowering.cpp | 143 ++++++++++++++++++++++++++++++++++------------------ README_ALTIVEC.txt | 30 +++------- 2 files changed, 106 insertions(+), 67 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.152 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.153 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.152 Sat Apr 15 18:48:05 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Sat Apr 15 20:01:29 2006 @@ -936,8 +936,6 @@ // ISD::UNDEF value. For undefs, the corresponding VectorBits values are // zero. Return true if this is not an array of constants, false if it is. // -// Note that VectorBits/UndefBits are returned in 'little endian' form, so -// elements 0,1 go in VectorBits[0] and 2,3 go in VectorBits[1] for a v4i32. static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2], uint64_t UndefBits[2]) { // Start with zero'd results. @@ -948,7 +946,7 @@ SDOperand OpVal = BV->getOperand(i); unsigned PartNo = i >= e/2; // In the upper 128 bits? - unsigned SlotNo = i & (e/2-1); // Which subpiece of the uint64_t it is. + unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t. uint64_t EltBits = 0; if (OpVal.getOpcode() == ISD::UNDEF) { @@ -974,6 +972,59 @@ return false; } +// If this is a splat (repetition) of a value across the whole vector, return +// the smallest size that splats it. For example, "0x01010101010101..." is a +// splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and +// SplatSize = 1 byte. +static bool isConstantSplat(const uint64_t Bits128[2], + const uint64_t Undef128[2], + unsigned &SplatBits, unsigned &SplatUndef, + unsigned &SplatSize) { + + // Don't let undefs prevent splats from matching. See if the top 64-bits are + // the same as the lower 64-bits, ignoring undefs. + if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0])) + return false; // Can't be a splat if two pieces don't match. + + uint64_t Bits64 = Bits128[0] | Bits128[1]; + uint64_t Undef64 = Undef128[0] & Undef128[1]; + + // Check that the top 32-bits are the same as the lower 32-bits, ignoring + // undefs. + if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64)) + return false; // Can't be a splat if two pieces don't match. + + uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32); + uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32); + + // If the top 16-bits are different than the lower 16-bits, ignoring + // undefs, we have an i32 splat. + if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) { + SplatBits = Bits32; + SplatUndef = Undef32; + SplatSize = 4; + return true; + } + + uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16); + uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16); + + // If the top 8-bits are different than the lower 8-bits, ignoring + // undefs, we have an i16 splat. + if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) { + SplatBits = Bits16; + SplatUndef = Undef16; + SplatSize = 2; + return true; + } + + // Otherwise, we have an 8-bit splat. + SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8); + SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8); + SplatSize = 1; + return true; +} + // If this is a case we can't handle, return null and let the default // expansion code take care of it. If we CAN select this case, and if it // selects to a single instruction, return Op. Otherwise, if we can codegen @@ -989,54 +1040,52 @@ if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits)) return SDOperand(); // Not a constant vector. - // See if this is all zeros. - if ((VectorBits[0] | VectorBits[1]) == 0) { - // Canonicalize all zero vectors to be v4i32. - if (Op.getValueType() != MVT::v4i32) { - SDOperand Z = DAG.getConstant(0, MVT::i32); - Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z); - Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z); + // If this is a splat (repetition) of a value across the whole vector, return + // the smallest size that splats it. For example, "0x01010101010101..." is a + // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and + // SplatSize = 1 byte. + unsigned SplatBits, SplatUndef, SplatSize; + if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){ + bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0; + + // First, handle single instruction cases. + + // All zeros? + if (SplatBits == 0) { + // Canonicalize all zero vectors to be v4i32. + if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) { + SDOperand Z = DAG.getConstant(0, MVT::i32); + Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z); + Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z); + } + return Op; } - return Op; - } - - // Check to see if this is something we can use VSPLTI* to form. - MVT::ValueType CanonicalVT = MVT::Other; - SDNode *CST = 0; - - if ((CST = PPC::get_VSPLTI_elt(Op.Val, 4, DAG).Val)) // vspltisw - CanonicalVT = MVT::v4i32; - else if ((CST = PPC::get_VSPLTI_elt(Op.Val, 2, DAG).Val)) // vspltish - CanonicalVT = MVT::v8i16; - else if ((CST = PPC::get_VSPLTI_elt(Op.Val, 1, DAG).Val)) // vspltisb - CanonicalVT = MVT::v16i8; - - // If this matches one of the vsplti* patterns, force it to the canonical - // type for the pattern. - if (CST) { - if (Op.getValueType() != CanonicalVT) { - // Convert the splatted element to the right element type. - SDOperand Elt = DAG.getNode(ISD::TRUNCATE, - MVT::getVectorBaseType(CanonicalVT), - SDOperand(CST, 0)); - std::vector Ops(MVT::getVectorNumElements(CanonicalVT), Elt); - SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT, Ops); - Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); + + // If the sign extended value is in the range [-16,15], use VSPLTI[bhw]. + int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize); + if (SextVal >= -16 && SextVal <= 15) { + const MVT::ValueType VTys[] = { // canonical VT to use for each size. + MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32 + }; + MVT::ValueType CanonicalVT = VTys[SplatSize-1]; + + // If this is a non-canonical splat for this value, + if (Op.getValueType() != CanonicalVT || HasAnyUndefs) { + SDOperand Elt = DAG.getConstant(SplatBits, + MVT::getVectorBaseType(CanonicalVT)); + std::vector Ops(MVT::getVectorNumElements(CanonicalVT), Elt); + SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT, Ops); + Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); + } + return Op; } - return Op; - } - - // If this is some other splat of 4-byte elements, see if we can handle it - // in another way. - // FIXME: Make this more undef happy and work with other widths (1,2 bytes). - if (VectorBits[0] == VectorBits[1] && - unsigned(VectorBits[0]) == unsigned(VectorBits[0] >> 32)) { - unsigned Bits = unsigned(VectorBits[0]); + // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). These are important // for fneg/fabs. - if (Bits == 0x80000000 || Bits == 0x7FFFFFFF) { + if (SplatSize == 4 && + SplatBits == 0x80000000 || SplatBits == (0x7FFFFFFF&~SplatUndef)) { // Make -1 and vspltisw -1: SDOperand OnesI = DAG.getConstant(~0U, MVT::i32); SDOperand OnesV = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, @@ -1049,13 +1098,13 @@ OnesV, OnesV); // If this is 0x7FFF_FFFF, xor by OnesV to invert it. - if (Bits == 0x7FFFFFFF) + if (SplatBits == 0x80000000) Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV); return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); } } - + return SDOperand(); } Index: llvm/lib/Target/PowerPC/README_ALTIVEC.txt diff -u llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.22 llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.23 --- llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.22 Thu Apr 13 11:48:00 2006 +++ llvm/lib/Target/PowerPC/README_ALTIVEC.txt Sat Apr 15 20:01:29 2006 @@ -40,8 +40,16 @@ //===----------------------------------------------------------------------===// There are a wide range of vector constants we can generate with combinations of -altivec instructions. Examples - GCC does: "t=vsplti*, r = t+t" for constants it can't generate with one vsplti +altivec instructions. + +Examples, these work with all widths: + Splat(+/- 16,18,20,22,24,28,30): t = vspliti I/2, r = t+t + Splat(+/- 17,19,21,23,25,29): t = vsplti +/-15, t2 = vsplti I-15, r=t + t2 + Splat(31): t = vsplti FB, r = srl t,t + Splat(256): t = vsplti 1, r = vsldoi t, t, 1 + +Lots more are listed here: +http://www.informatik.uni-bremen.de/~hobold/AltiVec.html This should be added to the ISD::BUILD_VECTOR case in PPCTargetLowering::LowerOperation. @@ -52,19 +60,6 @@ //===----------------------------------------------------------------------===// -Codegen the constant here with something better than a constant pool load. - -void %test_f(<4 x float>* %P, <4 x float>* %Q, float %X) { - %tmp = load <4 x float>* %Q - %tmp = cast <4 x float> %tmp to <4 x int> - %tmp1 = and <4 x int> %tmp, < int 2147483647, int 2147483647, int 2147483647, int 2147483647 > - %tmp2 = cast <4 x int> %tmp1 to <4 x float> - store <4 x float> %tmp2, <4 x float>* %P - ret void -} - -//===----------------------------------------------------------------------===// - For functions that use altivec AND have calls, we are VRSAVE'ing all call clobbered regs. @@ -92,11 +87,6 @@ //===----------------------------------------------------------------------===// -SROA should turn "vector unions" into the appropriate insert/extract element -instructions. - -//===----------------------------------------------------------------------===// - We need a way to teach tblgen that some operands of an intrinsic are required to be constants. The verifier should enforce this constraint. From lattner at cs.uiuc.edu Sat Apr 15 20:36:57 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 15 Apr 2006 20:36:57 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <200604160136.UAA19679@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.365 -> 1.366 --- Log message: Add support for promoting stores from one legal type to another, allowing us to write one pattern for vector stores instead of 4. --- Diffs of the changes: (+8 -0) LegalizeDAG.cpp | 8 ++++++++ 1 files changed, 8 insertions(+) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.365 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.366 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.365 Fri Apr 14 01:08:35 2006 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sat Apr 15 20:36:45 2006 @@ -1544,6 +1544,13 @@ Tmp1 = TLI.LowerOperation(Result, DAG); if (Tmp1.Val) Result = Tmp1; break; + case TargetLowering::Promote: + assert(MVT::isVector(VT) && "Unknown legal promote case!"); + Tmp3 = DAG.getNode(ISD::BIT_CONVERT, + TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); + Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, + Node->getOperand(3)); + break; } break; } @@ -1576,6 +1583,7 @@ Tmp3 = PackVectorOp(Node->getOperand(1), TVT); Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, Node->getOperand(3)); + Result = LegalizeOp(Result); break; } else if (NumElems == 1) { // Turn this into a normal store of the scalar type. From lattner at cs.uiuc.edu Sat Apr 15 20:38:09 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 15 Apr 2006 20:38:09 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCInstrAltivec.td README_ALTIVEC.txt Message-ID: <200604160138.UAA19716@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.153 -> 1.154 PPCInstrAltivec.td updated: 1.50 -> 1.51 README_ALTIVEC.txt updated: 1.23 -> 1.24 --- Log message: Implement a TODO: have the legalizer canonicalize a bunch of operations to one type (v4i32) so that we don't have to write patterns for each type, and so that more CSE opportunities are exposed. --- Diffs of the changes: (+32 -68) PPCISelLowering.cpp | 33 ++++++++++++++++++++++++--------- PPCInstrAltivec.td | 47 ++++++----------------------------------------- README_ALTIVEC.txt | 20 ++------------------ 3 files changed, 32 insertions(+), 68 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.153 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.154 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.153 Sat Apr 15 20:01:29 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Sat Apr 15 20:37:57 2006 @@ -87,10 +87,6 @@ setOperationAction(ISD::SELECT, MVT::i32, Expand); setOperationAction(ISD::SELECT, MVT::f32, Expand); setOperationAction(ISD::SELECT, MVT::f64, Expand); - setOperationAction(ISD::SELECT, MVT::v4f32, Expand); - setOperationAction(ISD::SELECT, MVT::v4i32, Expand); - setOperationAction(ISD::SELECT, MVT::v8i16, Expand); - setOperationAction(ISD::SELECT, MVT::v16i8, Expand); // PowerPC wants to turn select_cc of FP into fsel when possible. setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); @@ -178,17 +174,29 @@ // will selectively turn on ones that can be effectively codegen'd. for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { - // add/sub/and/or/xor are legal for all supported vector VT's. + // add/sub are legal for all supported vector VT's. setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal); setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal); - setOperationAction(ISD::AND , (MVT::ValueType)VT, Legal); - setOperationAction(ISD::OR , (MVT::ValueType)VT, Legal); - setOperationAction(ISD::XOR , (MVT::ValueType)VT, Legal); // We promote all shuffles to v16i8. setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote); - AddPromotedToType(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8); + AddPromotedToType (ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8); + + // We promote all non-typed operations to v4i32. + setOperationAction(ISD::AND , (MVT::ValueType)VT, Promote); + AddPromotedToType (ISD::AND , (MVT::ValueType)VT, MVT::v4i32); + setOperationAction(ISD::OR , (MVT::ValueType)VT, Promote); + AddPromotedToType (ISD::OR , (MVT::ValueType)VT, MVT::v4i32); + setOperationAction(ISD::XOR , (MVT::ValueType)VT, Promote); + AddPromotedToType (ISD::XOR , (MVT::ValueType)VT, MVT::v4i32); + setOperationAction(ISD::LOAD , (MVT::ValueType)VT, Promote); + AddPromotedToType (ISD::LOAD , (MVT::ValueType)VT, MVT::v4i32); + setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote); + AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v4i32); + setOperationAction(ISD::STORE, (MVT::ValueType)VT, Promote); + AddPromotedToType (ISD::STORE, (MVT::ValueType)VT, MVT::v4i32); + // No other operations are legal. setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand); setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand); setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand); @@ -205,6 +213,13 @@ // with merges, splats, etc. setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); + setOperationAction(ISD::AND , MVT::v4i32, Legal); + setOperationAction(ISD::OR , MVT::v4i32, Legal); + setOperationAction(ISD::XOR , MVT::v4i32, Legal); + setOperationAction(ISD::LOAD , MVT::v4i32, Legal); + setOperationAction(ISD::SELECT, MVT::v4i32, Expand); + setOperationAction(ISD::STORE , MVT::v4i32, Legal); + addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass); addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass); addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass); Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.50 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.51 --- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.50 Sat Apr 15 18:45:24 2006 +++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td Sat Apr 15 20:37:57 2006 @@ -158,7 +158,7 @@ // Instruction Definitions. def IMPLICIT_DEF_VRRC : Pseudo<(ops VRRC:$rD), "; $rD = IMPLICIT_DEF_VRRC", - [(set VRRC:$rD, (v4f32 (undef)))]>; + [(set VRRC:$rD, (v4i32 (undef)))]>; let noResults = 1 in { def DSS : DSS_Form<822, (ops u5imm:$A, u5imm:$STRM,u5imm:$ZERO1,u5imm:$ZERO2), @@ -541,25 +541,16 @@ (DSTST 1, imm:$STRM, GPRC:$rA, GPRC:$rB)>; // Undef. -def : Pat<(v16i8 (undef)), (v16i8 (IMPLICIT_DEF_VRRC))>; -def : Pat<(v8i16 (undef)), (v8i16 (IMPLICIT_DEF_VRRC))>; -def : Pat<(v4i32 (undef)), (v4i32 (IMPLICIT_DEF_VRRC))>; +def : Pat<(v16i8 (undef)), (IMPLICIT_DEF_VRRC)>; +def : Pat<(v8i16 (undef)), (IMPLICIT_DEF_VRRC)>; +def : Pat<(v4f32 (undef)), (IMPLICIT_DEF_VRRC)>; // Loads. -def : Pat<(v16i8 (load xoaddr:$src)), (v16i8 (LVX xoaddr:$src))>; -def : Pat<(v8i16 (load xoaddr:$src)), (v8i16 (LVX xoaddr:$src))>; def : Pat<(v4i32 (load xoaddr:$src)), (v4i32 (LVX xoaddr:$src))>; -def : Pat<(v4f32 (load xoaddr:$src)), (v4f32 (LVX xoaddr:$src))>; // Stores. -def : Pat<(store (v16i8 VRRC:$rS), xoaddr:$dst), - (STVX (v16i8 VRRC:$rS), xoaddr:$dst)>; -def : Pat<(store (v8i16 VRRC:$rS), xoaddr:$dst), - (STVX (v8i16 VRRC:$rS), xoaddr:$dst)>; def : Pat<(store (v4i32 VRRC:$rS), xoaddr:$dst), (STVX (v4i32 VRRC:$rS), xoaddr:$dst)>; -def : Pat<(store (v4f32 VRRC:$rS), xoaddr:$dst), - (STVX (v4f32 VRRC:$rS), xoaddr:$dst)>; // Bit conversions. def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>; @@ -603,37 +594,11 @@ (VMRGHW VRRC:$vA, VRRC:$vA)>; // Logical Operations -def : Pat<(v16i8 (vnot VRRC:$vA)), (v16i8 (VNOR VRRC:$vA, VRRC:$vA))>; -def : Pat<(v8i16 (vnot VRRC:$vA)), (v8i16 (VNOR VRRC:$vA, VRRC:$vA))>; def : Pat<(v4i32 (vnot VRRC:$vA)), (v4i32 (VNOR VRRC:$vA, VRRC:$vA))>; - -def : Pat<(v16i8 (vnot_conv VRRC:$vA)), (v16i8 (VNOR VRRC:$vA, VRRC:$vA))>; -def : Pat<(v8i16 (vnot_conv VRRC:$vA)), (v8i16 (VNOR VRRC:$vA, VRRC:$vA))>; def : Pat<(v4i32 (vnot_conv VRRC:$vA)), (v4i32 (VNOR VRRC:$vA, VRRC:$vA))>; - -def : Pat<(v16i8 (and VRRC:$A, VRRC:$B)), (v16i8 (VAND VRRC:$A, VRRC:$B))>; -def : Pat<(v8i16 (and VRRC:$A, VRRC:$B)), (v8i16 (VAND VRRC:$A, VRRC:$B))>; -def : Pat<(v16i8 (or VRRC:$A, VRRC:$B)), (v16i8 (VOR VRRC:$A, VRRC:$B))>; -def : Pat<(v8i16 (or VRRC:$A, VRRC:$B)), (v8i16 (VOR VRRC:$A, VRRC:$B))>; - -def : Pat<(v16i8 (xor VRRC:$A, VRRC:$B)), (v16i8 (VXOR VRRC:$A, VRRC:$B))>; -def : Pat<(v8i16 (xor VRRC:$A, VRRC:$B)), (v8i16 (VXOR VRRC:$A, VRRC:$B))>; -def : Pat<(v16i8 (vnot (or VRRC:$A, VRRC:$B))),(v16i8 (VNOR VRRC:$A, VRRC:$B))>; -def : Pat<(v8i16 (vnot (or VRRC:$A, VRRC:$B))),(v8i16 (VNOR VRRC:$A, VRRC:$B))>; -def : Pat<(v16i8 (and VRRC:$A, (vnot VRRC:$B))), - (v16i8 (VANDC VRRC:$A, VRRC:$B))>; -def : Pat<(v8i16 (and VRRC:$A, (vnot VRRC:$B))), - (v8i16 (VANDC VRRC:$A, VRRC:$B))>; - - -def : Pat<(v16i8 (vnot_conv (or VRRC:$A, VRRC:$B))),(v16i8 (VNOR VRRC:$A, VRRC:$B))>; -def : Pat<(v8i16 (vnot_conv (or VRRC:$A, VRRC:$B))),(v8i16 (VNOR VRRC:$A, VRRC:$B))>; -def : Pat<(v4i32 (vnot_conv (or VRRC:$A, VRRC:$B))),(v4i32 (VNOR VRRC:$A, VRRC:$B))>; -def : Pat<(v16i8 (and VRRC:$A, (vnot_conv VRRC:$B))), - (v16i8 (VANDC VRRC:$A, VRRC:$B))>; -def : Pat<(v8i16 (and VRRC:$A, (vnot_conv VRRC:$B))), - (v8i16 (VANDC VRRC:$A, VRRC:$B))>; +def : Pat<(v4i32 (vnot_conv (or VRRC:$A, VRRC:$B))), + (v4i32 (VNOR VRRC:$A, VRRC:$B))>; def : Pat<(v4i32 (and VRRC:$A, (vnot_conv VRRC:$B))), (v4i32 (VANDC VRRC:$A, VRRC:$B))>; Index: llvm/lib/Target/PowerPC/README_ALTIVEC.txt diff -u llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.23 llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.24 --- llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.23 Sat Apr 15 20:01:29 2006 +++ llvm/lib/Target/PowerPC/README_ALTIVEC.txt Sat Apr 15 20:37:57 2006 @@ -65,7 +65,7 @@ //===----------------------------------------------------------------------===// -Implement passing/returning vectors by value. +Implement passing vectors by value. //===----------------------------------------------------------------------===// @@ -75,7 +75,7 @@ //===----------------------------------------------------------------------===// We currently codegen SCALAR_TO_VECTOR as a store of the scalar to a 16-byte -aligned stack slot, followed by a lve*x/vperm. We should probably just store it +aligned stack slot, followed by a load/vperm. We should probably just store it to a scalar stack slot, then use lvsl/vperm to load it. If the value is already in memory, this is a huge win. @@ -92,22 +92,6 @@ //===----------------------------------------------------------------------===// -Instead of writting a pattern for type-agnostic operations (e.g. gen-zero, load, -store, and, ...) in every supported type, make legalize do the work. We should -have a canonical type that we want operations changed to (e.g. v4i32 for -build_vector) and legalize should change non-identical types to thse. This is -similar to what it does for operations that are only supported in some types, -e.g. x86 cmov (not supported on bytes). - -This would fix two problems: -1. Writing patterns multiple times. -2. Identical operations in different types are not getting CSE'd. - -We already do this for shuffle and build_vector. We need load,undef,and,or,xor, -etc. - -//===----------------------------------------------------------------------===// - Implement multiply for vector integer types, to avoid the horrible scalarized code produced by legalize. From evan.cheng at apple.com Sun Apr 16 01:58:31 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Sun, 16 Apr 2006 01:58:31 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp Message-ID: <200604160658.BAA26978@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86RegisterInfo.cpp updated: 1.138 -> 1.139 --- Log message: Can't fold loads into alias vector SSE ops used for scalar operation. The load address has to be 16-byte aligned but the values aren't spilled to 128-bit locations. --- Diffs of the changes: (+0 -8) X86RegisterInfo.cpp | 8 -------- 1 files changed, 8 deletions(-) Index: llvm/lib/Target/X86/X86RegisterInfo.cpp diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.138 llvm/lib/Target/X86/X86RegisterInfo.cpp:1.139 --- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.138 Fri Apr 14 18:33:27 2006 +++ llvm/lib/Target/X86/X86RegisterInfo.cpp Sun Apr 16 01:58:19 2006 @@ -464,14 +464,6 @@ return MakeRMInst(X86::Int_COMISSrm, FrameIndex, MI); case X86::Int_COMISDrr: return MakeRMInst(X86::Int_COMISDrm, FrameIndex, MI); - case X86::FsANDPSrr: return MakeRMInst(X86::FsANDPSrm, FrameIndex, MI); - case X86::FsANDPDrr: return MakeRMInst(X86::FsANDPDrm, FrameIndex, MI); - case X86::FsORPSrr: return MakeRMInst(X86::FsORPSrm, FrameIndex, MI); - case X86::FsORPDrr: return MakeRMInst(X86::FsORPDrm, FrameIndex, MI); - case X86::FsXORPSrr: return MakeRMInst(X86::FsXORPSrm, FrameIndex, MI); - case X86::FsXORPDrr: return MakeRMInst(X86::FsXORPDrm, FrameIndex, MI); - case X86::FsANDNPSrr: return MakeRMInst(X86::FsANDNPSrm, FrameIndex, MI); - case X86::FsANDNPDrr: return MakeRMInst(X86::FsANDNPDrm, FrameIndex, MI); // Packed SSE instructions case X86::MOVAPSrr: return MakeRMInst(X86::MOVAPSrm, FrameIndex, MI); case X86::MOVAPDrr: return MakeRMInst(X86::MOVAPDrm, FrameIndex, MI); From evan.cheng at apple.com Sun Apr 16 02:02:34 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Sun, 16 Apr 2006 02:02:34 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td Message-ID: <200604160702.CAA27044@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrSSE.td updated: 1.95 -> 1.96 --- Log message: Encoding bugs --- Diffs of the changes: (+2 -2) X86InstrSSE.td | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.95 llvm/lib/Target/X86/X86InstrSSE.td:1.96 --- llvm/lib/Target/X86/X86InstrSSE.td:1.95 Sat Apr 15 01:10:09 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Sun Apr 16 02:02:22 2006 @@ -766,10 +766,10 @@ def MOVUPSrr : PSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src), "movups {$src, $dst|$dst, $src}", []>; -def MOVUPSrm : PDI<0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src), +def MOVUPSrm : PSI<0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src), "movups {$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>; -def MOVUPSmr : PDI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src), +def MOVUPSmr : PSI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src), "movups {$src, $dst|$dst, $src}", [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>; def MOVUPDrr : PDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src), From evan.cheng at apple.com Sun Apr 16 13:11:54 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Sun, 16 Apr 2006 13:11:54 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td Message-ID: <200604161811.NAA16977@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrSSE.td updated: 1.96 -> 1.97 --- Log message: movduprm, movshduprm bugs --- Diffs of the changes: (+5 -4) X86InstrSSE.td | 9 +++++---- 1 files changed, 5 insertions(+), 4 deletions(-) Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.96 llvm/lib/Target/X86/X86InstrSSE.td:1.97 --- llvm/lib/Target/X86/X86InstrSSE.td:1.96 Sun Apr 16 02:02:22 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Sun Apr 16 13:11:28 2006 @@ -852,7 +852,7 @@ [(set VR128:$dst, (v4f32 (vector_shuffle VR128:$src, (undef), MOVSHDUP_shuffle_mask)))]>; -def MOVSHDUPrm : S3SI<0x16, MRMSrcReg, (ops VR128:$dst, f128mem:$src), +def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (ops VR128:$dst, f128mem:$src), "movshdup {$src, $dst|$dst, $src}", [(set VR128:$dst, (v4f32 (vector_shuffle (loadv4f32 addr:$src), (undef), @@ -863,7 +863,7 @@ [(set VR128:$dst, (v4f32 (vector_shuffle VR128:$src, (undef), MOVSLDUP_shuffle_mask)))]>; -def MOVSLDUPrm : S3SI<0x12, MRMSrcReg, (ops VR128:$dst, f128mem:$src), +def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (ops VR128:$dst, f128mem:$src), "movsldup {$src, $dst|$dst, $src}", [(set VR128:$dst, (v4f32 (vector_shuffle (loadv4f32 addr:$src), (undef), @@ -874,10 +874,11 @@ [(set VR128:$dst, (v2f64 (vector_shuffle VR128:$src, (undef), SSE_splat_v2_mask)))]>; -def MOVDDUPrm : S3DI<0x12, MRMSrcReg, (ops VR128:$dst, f64mem:$src), +def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (ops VR128:$dst, f64mem:$src), "movddup {$src, $dst|$dst, $src}", [(set VR128:$dst, (v2f64 (vector_shuffle - (loadv2f64 addr:$src), (undef), + (scalar_to_vector (loadf64 addr:$src)), + (undef), SSE_splat_v2_mask)))]>; // SSE2 instructions without OpSize prefix From evan.cheng at apple.com Sun Apr 16 13:16:55 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Sun, 16 Apr 2006 13:16:55 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/X86/vec_splat.ll Message-ID: <200604161816.NAA17057@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/X86: vec_splat.ll updated: 1.2 -> 1.3 --- Log message: Better way to splat v2f64 --- Diffs of the changes: (+1 -1) vec_splat.ll | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/CodeGen/X86/vec_splat.ll diff -u llvm/test/Regression/CodeGen/X86/vec_splat.ll:1.2 llvm/test/Regression/CodeGen/X86/vec_splat.ll:1.3 --- llvm/test/Regression/CodeGen/X86/vec_splat.ll:1.2 Wed Mar 29 12:59:48 2006 +++ llvm/test/Regression/CodeGen/X86/vec_splat.ll Sun Apr 16 13:16:43 2006 @@ -1,5 +1,5 @@ ; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep shufps -; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep unpcklpd +; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep mulpd void %test_v4sf(<4 x float>* %P, <4 x float>* %Q, float %X) { %tmp = insertelement <4 x float> zeroinitializer, float %X, uint 0 From lattner at cs.uiuc.edu Sun Apr 16 19:27:29 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 16 Apr 2006 19:27:29 -0500 Subject: [llvm-commits] CVS: llvm/utils/BuildShuffleTable/ Message-ID: <200604170027.TAA18883@zion.cs.uiuc.edu> Changes in directory llvm/utils/BuildShuffleTable: --- Log message: Directory /home/vadve/shared/PublicCVS/llvm/utils/BuildShuffleTable added to the repository --- Diffs of the changes: (+0 -0) 0 files changed From lattner at cs.uiuc.edu Sun Apr 16 19:30:53 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 16 Apr 2006 19:30:53 -0500 Subject: [llvm-commits] CVS: llvm/utils/BuildShuffleTable/BuildShuffleTable.cpp Makefile Message-ID: <200604170030.TAA18958@zion.cs.uiuc.edu> Changes in directory llvm/utils/BuildShuffleTable: BuildShuffleTable.cpp added (r1.1) Makefile added (r1.1) --- Log message: Initial checking of a perfect shuffle generation program for 4-element Altivec vectors. --- Diffs of the changes: (+487 -0) BuildShuffleTable.cpp | 474 ++++++++++++++++++++++++++++++++++++++++++++++++++ Makefile | 13 + 2 files changed, 487 insertions(+) Index: llvm/utils/BuildShuffleTable/BuildShuffleTable.cpp diff -c /dev/null llvm/utils/BuildShuffleTable/BuildShuffleTable.cpp:1.1 *** /dev/null Sun Apr 16 19:30:51 2006 --- llvm/utils/BuildShuffleTable/BuildShuffleTable.cpp Sun Apr 16 19:30:41 2006 *************** *** 0 **** --- 1,474 ---- + //===-- BuildShuffleTable.cpp - Perfect Shuffle Generator -----------------===// + // + // The LLVM Compiler Infrastructure + // + // This file was developed by Chris Lattner and is distributed under + // the University of Illinois Open Source License. See LICENSE.TXT for details. + // + //===----------------------------------------------------------------------===// + // + // This file computes an optimal sequence of instructions for doing all shuffles + // of two 4-element vectors. With a release build and when configured to emit + // an altivec instruction table, this takes about 30s to run on a 2.7Ghz + // PowerPC G5. + // + //===----------------------------------------------------------------------===// + + #include + #include + + struct Operator; + + // Masks are 4-nibble hex numbers. Values 0-7 in any nibble means that it takes + // an element from that value of the input vectors. A value of 8 means the + // entry is undefined. + + // Mask manipulation functions. + static inline unsigned short MakeMask(unsigned V0, unsigned V1, + unsigned V2, unsigned V3) { + return (V0 << (3*4)) | (V1 << (2*4)) | (V2 << (1*4)) | (V3 << (0*4)); + } + + /// getMaskElt - Return element N of the specified mask. + static unsigned getMaskElt(unsigned Mask, unsigned Elt) { + return (Mask >> ((3-Elt)*4)) & 0xF; + } + + static unsigned setMaskElt(unsigned Mask, unsigned Elt, unsigned NewVal) { + unsigned FieldShift = ((3-Elt)*4); + return (Mask & ~(0xF << FieldShift)) | (NewVal << FieldShift); + } + + // Reject elements where the values are 9-15. + static bool isValidMask(unsigned short Mask) { + unsigned short UndefBits = Mask & 0x8888; + return (Mask & ((UndefBits >> 1)|(UndefBits>>2)|(UndefBits>>3))) == 0; + } + + /// hasUndefElements - Return true if any of the elements in the mask are undefs + /// + static bool hasUndefElements(unsigned short Mask) { + return (Mask & 0x8888) != 0; + } + + /// isOnlyLHSMask - Return true if this mask only refers to its LHS, not + /// including undef values.. + static bool isOnlyLHSMask(unsigned short Mask) { + return (Mask & 0x4444) == 0; + } + + /// getLHSOnlyMask - Given a mask that refers to its LHS and RHS, modify it to + /// refer to the LHS only (for when one argument value is passed into the same + /// function twice). + static unsigned short getLHSOnlyMask(unsigned short Mask) { + return Mask & 0xBBBB; // Keep only LHS and Undefs. + } + + /// getCompressedMask - Turn a 16-bit uncompressed mask (where each elt uses 4 + /// bits) into a compressed 13-bit mask, where each elt is multiplied by 9. + static unsigned getCompressedMask(unsigned short Mask) { + return getMaskElt(Mask, 0)*9*9*9 + getMaskElt(Mask, 1)*9*9 + + getMaskElt(Mask, 2)*9 + getMaskElt(Mask, 3); + } + + static void PrintMask(unsigned i, std::ostream &OS) { + OS << "<" << (char)(getMaskElt(i, 0) == 8 ? 'u' : ('0'+getMaskElt(i, 0))) + << "," << (char)(getMaskElt(i, 1) == 8 ? 'u' : ('0'+getMaskElt(i, 1))) + << "," << (char)(getMaskElt(i, 2) == 8 ? 'u' : ('0'+getMaskElt(i, 2))) + << "," << (char)(getMaskElt(i, 3) == 8 ? 'u' : ('0'+getMaskElt(i, 3))) + << ">"; + } + + /// ShuffleVal - This represents a shufflevector operation. + struct ShuffleVal { + unsigned Cost; // Number of instrs used to generate this value. + Operator *Op; // The Operation used to generate this value. + unsigned short Arg0, Arg1; // Input operands for this value. + + ShuffleVal() : Cost(1000000) {} + }; + + + /// ShufTab - This is the actual shuffle table that we are trying to generate. + /// + static ShuffleVal ShufTab[65536]; + + /// TheOperators - All of the operators that this target supports. + static std::vector TheOperators; + + /// Operator - This is a vector operation that is available for use. + struct Operator { + unsigned short ShuffleMask; + unsigned short OpNum; + const char *Name; + + Operator(unsigned short shufflemask, const char *name) + : ShuffleMask(shufflemask), Name(name) { + OpNum = TheOperators.size(); + TheOperators.push_back(this); + } + ~Operator() { + assert(TheOperators.back() == this); + TheOperators.pop_back(); + } + + bool isOnlyLHSOperator() const { + return isOnlyLHSMask(ShuffleMask); + } + + const char *getName() const { return Name; } + + unsigned short getTransformedMask(unsigned short LHSMask, unsigned RHSMask) { + // Extract the elements from LHSMask and RHSMask, as appropriate. + unsigned Result = 0; + for (unsigned i = 0; i != 4; ++i) { + unsigned SrcElt = (ShuffleMask >> (4*i)) & 0xF; + unsigned ResElt; + if (SrcElt < 4) + ResElt = getMaskElt(LHSMask, SrcElt); + else if (SrcElt < 8) + ResElt = getMaskElt(RHSMask, SrcElt-4); + else { + assert(SrcElt == 8 && "Bad src elt!"); + ResElt = 8; + } + Result |= ResElt << (4*i); + } + return Result; + } + }; + + static const char *getZeroCostOpName(unsigned short Op) { + if (ShufTab[Op].Arg0 == 0x0123) + return "LHS"; + else if (ShufTab[Op].Arg0 == 0x4567) + return "RHS"; + else { + assert(0 && "bad zero cost operation"); + abort(); + } + } + + static void PrintOperation(unsigned ValNo, unsigned short Vals[]) { + unsigned short ThisOp = Vals[ValNo]; + std::cerr << "t" << ValNo; + PrintMask(ThisOp, std::cerr); + std::cerr << " = " << ShufTab[ThisOp].Op->getName() << "("; + + if (ShufTab[ShufTab[ThisOp].Arg0].Cost == 0) { + std::cerr << getZeroCostOpName(ShufTab[ThisOp].Arg0); + PrintMask(ShufTab[ThisOp].Arg0, std::cerr); + } else { + // Figure out what tmp # it is. + for (unsigned i = 0; ; ++i) + if (Vals[i] == ShufTab[ThisOp].Arg0) { + std::cerr << "t" << i; + break; + } + } + + if (!ShufTab[Vals[ValNo]].Op->isOnlyLHSOperator()) { + std::cerr << ", "; + if (ShufTab[ShufTab[ThisOp].Arg1].Cost == 0) { + std::cerr << getZeroCostOpName(ShufTab[ThisOp].Arg1); + PrintMask(ShufTab[ThisOp].Arg1, std::cerr); + } else { + // Figure out what tmp # it is. + for (unsigned i = 0; ; ++i) + if (Vals[i] == ShufTab[ThisOp].Arg1) { + std::cerr << "t" << i; + break; + } + } + } + std::cerr << ") "; + } + + static unsigned getNumEntered() { + unsigned Count = 0; + for (unsigned i = 0; i != 65536; ++i) + Count += ShufTab[i].Cost < 100; + return Count; + } + + static void EvaluateOps(unsigned short Elt, unsigned short Vals[], + unsigned &NumVals) { + if (ShufTab[Elt].Cost == 0) return; + + // If this value has already been evaluated, it is free. FIXME: match undefs. + for (unsigned i = 0, e = NumVals; i != e; ++i) + if (Vals[i] == Elt) return; + + // Otherwise, get the operands of the value, then add it. + unsigned Arg0 = ShufTab[Elt].Arg0, Arg1 = ShufTab[Elt].Arg1; + if (ShufTab[Arg0].Cost) + EvaluateOps(Arg0, Vals, NumVals); + if (Arg0 != Arg1 && ShufTab[Arg1].Cost) + EvaluateOps(Arg1, Vals, NumVals); + + Vals[NumVals++] = Elt; + } + + + int main() { + // Seed the table with accesses to the LHS and RHS. + ShufTab[0x0123].Cost = 0; + ShufTab[0x0123].Op = 0; + ShufTab[0x0123].Arg0 = 0x0123; + ShufTab[0x4567].Cost = 0; + ShufTab[0x4567].Op = 0; + ShufTab[0x4567].Arg0 = 0x4567; + + // Seed the first-level of shuffles, shuffles whose inputs are the input to + // the vectorshuffle operation. + bool MadeChange = true; + unsigned OpCount = 0; + while (MadeChange) { + MadeChange = false; + ++OpCount; + std::cerr << "Starting iteration #" << OpCount << " with " + << getNumEntered() << " entries established.\n"; + + // Scan the table for two reasons: First, compute the maximum cost of any + // operation left in the table. Second, make sure that values with undefs + // have the cheapest alternative that they match. + unsigned MaxCost = ShufTab[0].Cost; + for (unsigned i = 1; i != 0x8889; ++i) { + if (!isValidMask(i)) continue; + if (ShufTab[i].Cost > MaxCost) + MaxCost = ShufTab[i].Cost; + + // If this value has an undef, make it be computed the cheapest possible + // way of any of the things that it matches. + if (hasUndefElements(i)) { + // This code is a little bit tricky, so here's the idea: consider some + // permutation, like 7u4u. To compute the lowest cost for 7u4u, we + // need to take the minimum cost of all of 7[0-8]4[0-8], 81 entries. If + // there are 3 undefs, the number rises to 729 entries we have to scan, + // and for the 4 undef case, we have to scan the whole table. + // + // Instead of doing this huge amount of scanning, we process the table + // entries *in order*, and use the fact that 'u' is 8, larger than any + // valid index. Given an entry like 7u4u then, we only need to scan + // 7[0-7]4u - 8 entries. We can get away with this, because we already + // know that each of 704u, 714u, 724u, etc contain the minimum value of + // all of the 704[0-8], 714[0-8] and 724[0-8] entries respectively. + unsigned UndefIdx; + if (i & 0x8000) + UndefIdx = 0; + else if (i & 0x0800) + UndefIdx = 1; + else if (i & 0x0080) + UndefIdx = 2; + else if (i & 0x0008) + UndefIdx = 3; + else + abort(); + + unsigned MinVal = i; + unsigned MinCost = ShufTab[i].Cost; + + // Scan the 8 entries. + for (unsigned j = 0; j != 8; ++j) { + unsigned NewElt = setMaskElt(i, UndefIdx, j); + if (ShufTab[NewElt].Cost < MinCost) { + MinCost = ShufTab[NewElt].Cost; + MinVal = NewElt; + } + } + + // If we found something cheaper than what was here before, use it. + if (i != MinVal) { + MadeChange = true; + ShufTab[i] = ShufTab[MinVal]; + } + } + } + + for (unsigned LHS = 0; LHS != 0x8889; ++LHS) { + if (!isValidMask(LHS)) continue; + if (ShufTab[LHS].Cost > 1000) continue; + + // If nothing involving this operand could possibly be cheaper than what + // we already have, don't consider it. + if (ShufTab[LHS].Cost + 1 >= MaxCost) + continue; + + for (unsigned opnum = 0, e = TheOperators.size(); opnum != e; ++opnum) { + Operator *Op = TheOperators[opnum]; + unsigned short Mask = Op->ShuffleMask; + + // Evaluate op(LHS,LHS) + unsigned ResultMask = Op->getTransformedMask(LHS, LHS); + + unsigned Cost = ShufTab[LHS].Cost + 1; + if (Cost < ShufTab[ResultMask].Cost) { + ShufTab[ResultMask].Cost = Cost; + ShufTab[ResultMask].Op = Op; + ShufTab[ResultMask].Arg0 = LHS; + ShufTab[ResultMask].Arg1 = LHS; + MadeChange = true; + } + + // If this is a two input instruction, include the op(x,y) cases. If + // this is a one input instruction, skip this. + if (Op->isOnlyLHSOperator()) continue; + + for (unsigned RHS = 0; RHS != 0x8889; ++RHS) { + if (!isValidMask(RHS)) continue; + if (ShufTab[RHS].Cost > 1000) continue; + + // If nothing involving this operand could possibly be cheaper than + // what we already have, don't consider it. + if (ShufTab[RHS].Cost + 1 >= MaxCost) + continue; + + + // Evaluate op(LHS,RHS) + unsigned ResultMask = Op->getTransformedMask(LHS, RHS); + + if (ShufTab[ResultMask].Cost <= OpCount || + ShufTab[ResultMask].Cost <= ShufTab[LHS].Cost || + ShufTab[ResultMask].Cost <= ShufTab[RHS].Cost) + continue; + + // Figure out the cost to evaluate this, knowing that CSE's only need + // to be evaluated once. + unsigned short Vals[30]; + unsigned NumVals = 0; + EvaluateOps(LHS, Vals, NumVals); + EvaluateOps(RHS, Vals, NumVals); + + unsigned Cost = NumVals + 1; + if (Cost < ShufTab[ResultMask].Cost) { + ShufTab[ResultMask].Cost = Cost; + ShufTab[ResultMask].Op = Op; + ShufTab[ResultMask].Arg0 = LHS; + ShufTab[ResultMask].Arg1 = RHS; + MadeChange = true; + } + } + } + } + } + + std::cerr << "Finished Table has " << getNumEntered() + << " entries established.\n"; + + unsigned CostArray[10] = { 0 }; + + // Compute a cost histogram. + for (unsigned i = 0; i != 65536; ++i) { + if (!isValidMask(i)) continue; + if (ShufTab[i].Cost > 9) + ++CostArray[9]; + else + ++CostArray[ShufTab[i].Cost]; + } + + for (unsigned i = 0; i != 9; ++i) + if (CostArray[i]) + std::cout << "// " << CostArray[i] << " entries have cost " << i << "\n"; + if (CostArray[9]) + std::cout << "// " << CostArray[9] << " entries have higher cost!\n"; + + + // Build up the table to emit. + std::cout << "\n// This table is 6561*4 = 26244 bytes in size.\n"; + std::cout << "static const unsigned InstrTab[6561+1] = {\n"; + + for (unsigned i = 0; i != 0x8889; ++i) { + if (!isValidMask(i)) continue; + + // CostSat - The cost of this operation saturated to two bits. + unsigned CostSat = ShufTab[i].Cost; + if (CostSat > 3) CostSat = 3; + + unsigned OpNum = ShufTab[i].Op ? ShufTab[i].Op->OpNum : 0; + assert(OpNum < 16 && "Too few bits to encode operation!"); + + unsigned LHS = getCompressedMask(ShufTab[i].Arg0); + unsigned RHS = getCompressedMask(ShufTab[i].Arg1); + + // Encode this as 2 bits of saturated cost, 4 bits of opcodes, 13 bits of + // LHS, and 13 bits of RHS = 32 bits. + unsigned Val = (CostSat << 30) | (OpNum << 27) | (LHS << 13) | RHS; + + std::cout << " " << Val << "U,\t// "; + PrintMask(i, std::cout); + std::cout << ": Cost " << ShufTab[i].Cost; + std::cout << " " << (ShufTab[i].Op ? ShufTab[i].Op->getName() : "copy"); + std::cout << " "; + if (ShufTab[ShufTab[i].Arg0].Cost == 0) { + std::cout << getZeroCostOpName(ShufTab[i].Arg0); + } else { + PrintMask(ShufTab[i].Arg0, std::cout); + } + + if (ShufTab[i].Op && !ShufTab[i].Op->isOnlyLHSOperator()) { + std::cout << ", "; + if (ShufTab[ShufTab[i].Arg1].Cost == 0) { + std::cout << getZeroCostOpName(ShufTab[i].Arg1); + } else { + PrintMask(ShufTab[i].Arg1, std::cout); + } + } + std::cout << "\n"; + } + std::cout << " 0\n};\n"; + + if (0) { + // Print out the table. + for (unsigned i = 0; i != 0x8889; ++i) { + if (!isValidMask(i)) continue; + if (ShufTab[i].Cost < 1000) { + PrintMask(i, std::cerr); + std::cerr << " - Cost " << ShufTab[i].Cost << " - "; + + unsigned short Vals[30]; + unsigned NumVals = 0; + EvaluateOps(i, Vals, NumVals); + + for (unsigned j = 0, e = NumVals; j != e; ++j) + PrintOperation(j, Vals); + std::cerr << "\n"; + } + } + } + } + + + + ///===---------------------------------------------------------------------===// + /// The altivec instruction definitions. This is the altivec-specific part of + /// this file. + ///===---------------------------------------------------------------------===// + + struct vmrghw : public Operator { + vmrghw() : Operator(0x0415, "vmrghw") {} + } the_vmrghw; + + struct vmrglw : public Operator { + vmrglw() : Operator(0x2637, "vmrglw") {} + } the_vmrglw; + + template + struct vspltisw : public Operator { + vspltisw(const char *N) : Operator(MakeMask(Elt, Elt, Elt, Elt), N) {} + }; + + vspltisw<0> the_vspltisw0("vspltisw0"); + vspltisw<1> the_vspltisw1("vspltisw1"); + vspltisw<2> the_vspltisw2("vspltisw2"); + vspltisw<3> the_vspltisw3("vspltisw3"); + + template + struct vsldoi : public Operator { + vsldoi(const char *n) : Operator(MakeMask(N&7, (N+1)&7, (N+2)&7, (N+3)&7), n){ + } + }; + + vsldoi<1> the_vsldoi1("vsldoi4"); + vsldoi<2> the_vsldoi2("vsldoi8"); + vsldoi<3> the_vsldoi3("vsldoi12"); + Index: llvm/utils/BuildShuffleTable/Makefile diff -c /dev/null llvm/utils/BuildShuffleTable/Makefile:1.1 *** /dev/null Sun Apr 16 19:30:53 2006 --- llvm/utils/BuildShuffleTable/Makefile Sun Apr 16 19:30:41 2006 *************** *** 0 **** --- 1,13 ---- + ##===- utils/BuildShuffleTable/Makefile --------------------*- Makefile -*-===## + # + # The LLVM Compiler Infrastructure + # + # This file was developed by Chris Lattner and is distributed under + # the University of Illinois Open Source License. See LICENSE.TXT for details. + # + ##===----------------------------------------------------------------------===## + + LEVEL = ../.. + TOOLNAME = llvm-BuildShuffleTable + include $(LEVEL)/Makefile.common + From lattner at cs.uiuc.edu Sun Apr 16 19:33:47 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 16 Apr 2006 19:33:47 -0500 Subject: [llvm-commits] CVS: llvm/utils/BuildShuffleTable/BuildShuffleTable.cpp Message-ID: <200604170033.TAA19052@zion.cs.uiuc.edu> Changes in directory llvm/utils/BuildShuffleTable: BuildShuffleTable.cpp updated: 1.1 -> 1.2 --- Log message: rename the table --- Diffs of the changes: (+1 -1) BuildShuffleTable.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/utils/BuildShuffleTable/BuildShuffleTable.cpp diff -u llvm/utils/BuildShuffleTable/BuildShuffleTable.cpp:1.1 llvm/utils/BuildShuffleTable/BuildShuffleTable.cpp:1.2 --- llvm/utils/BuildShuffleTable/BuildShuffleTable.cpp:1.1 Sun Apr 16 19:30:41 2006 +++ llvm/utils/BuildShuffleTable/BuildShuffleTable.cpp Sun Apr 16 19:33:35 2006 @@ -375,7 +375,7 @@ // Build up the table to emit. std::cout << "\n// This table is 6561*4 = 26244 bytes in size.\n"; - std::cout << "static const unsigned InstrTab[6561+1] = {\n"; + std::cout << "static const unsigned PerfectShuffleTable[6561+1] = {\n"; for (unsigned i = 0; i != 0x8889; ++i) { if (!isValidMask(i)) continue; From lattner at cs.uiuc.edu Sun Apr 16 19:35:46 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 16 Apr 2006 19:35:46 -0500 Subject: [llvm-commits] CVS: llvm/utils/PerfectShuffle/Makefile PerfectShuffle.cpp Message-ID: <200604170035.TAA19150@zion.cs.uiuc.edu> Changes in directory llvm/utils/PerfectShuffle: Makefile updated: 1.1 -> 1.2 PerfectShuffle.cpp updated: 1.2 -> 1.3 --- Log message: Rename BuildShuffleTable -> PerfectShuffle --- Diffs of the changes: (+3 -3) Makefile | 4 ++-- PerfectShuffle.cpp | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) Index: llvm/utils/PerfectShuffle/Makefile diff -u llvm/utils/PerfectShuffle/Makefile:1.1 llvm/utils/PerfectShuffle/Makefile:1.2 --- llvm/utils/PerfectShuffle/Makefile:1.1 Sun Apr 16 19:30:41 2006 +++ llvm/utils/PerfectShuffle/Makefile Sun Apr 16 19:35:34 2006 @@ -1,4 +1,4 @@ -##===- utils/BuildShuffleTable/Makefile --------------------*- Makefile -*-===## +##===- utils/PerfectShuffle/Makefile -----------------------*- Makefile -*-===## # # The LLVM Compiler Infrastructure # @@ -8,6 +8,6 @@ ##===----------------------------------------------------------------------===## LEVEL = ../.. -TOOLNAME = llvm-BuildShuffleTable +TOOLNAME = llvm-PerfectShuffle include $(LEVEL)/Makefile.common Index: llvm/utils/PerfectShuffle/PerfectShuffle.cpp diff -u llvm/utils/PerfectShuffle/PerfectShuffle.cpp:1.2 llvm/utils/PerfectShuffle/PerfectShuffle.cpp:1.3 --- llvm/utils/PerfectShuffle/PerfectShuffle.cpp:1.2 Sun Apr 16 19:33:35 2006 +++ llvm/utils/PerfectShuffle/PerfectShuffle.cpp Sun Apr 16 19:35:34 2006 @@ -1,4 +1,4 @@ -//===-- BuildShuffleTable.cpp - Perfect Shuffle Generator -----------------===// +//===-- PerfectShuffle.cpp - Perfect Shuffle Generator --------------------===// // // The LLVM Compiler Infrastructure // From lattner at cs.uiuc.edu Sun Apr 16 19:35:47 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 16 Apr 2006 19:35:47 -0500 Subject: [llvm-commits] CVS: llvm/utils/Makefile Message-ID: <200604170035.TAA19154@zion.cs.uiuc.edu> Changes in directory llvm/utils: Makefile updated: 1.12 -> 1.13 --- Log message: Rename BuildShuffleTable -> PerfectShuffle --- Diffs of the changes: (+1 -1) Makefile | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/utils/Makefile diff -u llvm/utils/Makefile:1.12 llvm/utils/Makefile:1.13 --- llvm/utils/Makefile:1.12 Thu Apr 13 01:27:20 2006 +++ llvm/utils/Makefile Sun Apr 16 19:35:34 2006 @@ -8,7 +8,7 @@ ##===----------------------------------------------------------------------===## LEVEL = .. -DIRS = Burg TableGen fpcmp +DIRS = Burg TableGen fpcmp PerfectShuffle EXTRA_DIST := cgiplotNLT.pl check-each-file codegen-diff countloc.sh cvsupdate \ DSAclean.py DSAextract.py emacs findsym.pl GenLibDeps.pl \ From lattner at cs.uiuc.edu Sun Apr 16 19:37:14 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 16 Apr 2006 19:37:14 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCPerfectShuffle.h Message-ID: <200604170037.TAA19212@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCPerfectShuffle.h added (r1.1) --- Log message: Check in a table, generated by llvm-PerfectShuffle, of optimal shuffles of various 4-element vectors. --- Diffs of the changes: (+6586 -0) PPCPerfectShuffle.h | 6586 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 6586 insertions(+) Index: llvm/lib/Target/PowerPC/PPCPerfectShuffle.h diff -c /dev/null llvm/lib/Target/PowerPC/PPCPerfectShuffle.h:1.1 *** /dev/null Sun Apr 16 19:37:12 2006 --- llvm/lib/Target/PowerPC/PPCPerfectShuffle.h Sun Apr 16 19:37:02 2006 *************** *** 0 **** --- 1,6586 ---- + //===-- PPCPerfectShuffle.h - Altivec Perfect Shuffle Table ---------------===// + // + // The LLVM Compiler Infrastructure + // + // This file was developed by Chris Lattner and is distributed under + // the University of Illinois Open Source License. See LICENSE.TXT for details. + // + //===----------------------------------------------------------------------===// + // + // This file, which was autogenerated by llvm-PerfectShuffle, contains data + // for the optimal way to build a perfect shuffle without using vperm. + // + //===----------------------------------------------------------------------===// + + // 31 entries have cost 0 + // 292 entries have cost 1 + // 1384 entries have cost 2 + // 3061 entries have cost 3 + // 1733 entries have cost 4 + // 60 entries have cost 5 + + // This table is 6561*4 = 26244 bytes in size. + static const unsigned PerfectShuffleTable[6561+1] = { + 1343012966U, // <0,0,0,0>: Cost 1 vspltisw0 LHS + 2147483750U, // <0,0,0,1>: Cost 2 vmrghw <0,0,0,0>, LHS + 4026533325U, // <0,0,0,2>: Cost 3 vsldoi4 <0,0,0,0>, <2,0,3,0> + 4044449931U, // <0,0,0,3>: Cost 3 vsldoi4 <3,0,0,0>, <3,0,0,0> + 2952793398U, // <0,0,0,4>: Cost 2 vsldoi4 <0,0,0,0>, RHS + 3355443529U, // <0,0,0,5>: Cost 3 vmrglw <0,0,0,0>, <0,4,0,5> + 4026536277U, // <0,0,0,6>: Cost 3 vsldoi4 <0,0,0,0>, <6,0,7,0> + 4068340719U, // <0,0,0,7>: Cost 3 vsldoi4 <7,0,0,0>, <7,0,0,0> + 1343012966U, // <0,0,0,u>: Cost 1 vspltisw0 LHS + 2148319242U, // <0,0,1,0>: Cost 2 vmrghw LHS, <0,0,1,1> + 1074577510U, // <0,0,1,1>: Cost 1 vmrghw LHS, LHS + 3228745830U, // <0,0,1,2>: Cost 2 vsldoi12 <1,2,3,0>, LHS + 3222503676U, // <0,0,1,3>: Cost 3 vmrghw LHS, <0,3,1,0> + 2148360530U, // <0,0,1,4>: Cost 2 vmrghw LHS, <0,4,1,5> + 3222061522U, // <0,0,1,5>: Cost 3 vmrghw LHS, <0,5,6,7> + 3222061549U, // <0,0,1,6>: Cost 3 vmrghw LHS, <0,6,0,7> + 4068348912U, // <0,0,1,7>: Cost 3 vsldoi4 <7,0,0,1>, <7,0,0,1> + 1074578077U, // <0,0,1,u>: Cost 1 vmrghw LHS, LHS + 4160751053U, // <0,0,2,0>: Cost 3 vsldoi8 <0,0,0,0>, <2,0,3,0> + 3222642790U, // <0,0,2,1>: Cost 3 vmrghw <0,2,1,2>, LHS + 3222642861U, // <0,0,2,2>: Cost 3 vmrghw <0,2,1,2>, <0,2,1,2> + 4174685861U, // <0,0,2,3>: Cost 3 vsldoi8 <2,3,0,0>, <2,3,0,0> + 3222643026U, // <0,0,2,4>: Cost 4 vmrghw <0,2,1,2>, <0,4,1,5> + 4160751459U, // <0,0,2,5>: Cost 4 vsldoi8 <0,0,0,0>, <2,5,3,1> + 4160751546U, // <0,0,2,6>: Cost 3 vsldoi8 <0,0,0,0>, <2,6,3,7> + 4160751594U, // <0,0,2,7>: Cost 4 vsldoi8 <0,0,0,0>, <2,7,0,1> + 3222643357U, // <0,0,2,u>: Cost 3 vmrghw <0,2,1,2>, LHS + 4178667659U, // <0,0,3,0>: Cost 3 vsldoi8 <3,0,0,0>, <3,0,0,0> + 3223289958U, // <0,0,3,1>: Cost 3 vmrghw <0,3,1,0>, LHS + 3240689928U, // <0,0,3,2>: Cost 4 vsldoi12 <3,2,3,0>, <0,3,2,3> + 3223290108U, // <0,0,3,3>: Cost 3 vmrghw <0,3,1,0>, <0,3,1,0> + 4160752130U, // <0,0,3,4>: Cost 3 vsldoi8 <0,0,0,0>, <3,4,5,6> + 4068364386U, // <0,0,3,5>: Cost 4 vsldoi4 <7,0,0,3>, <5,6,7,0> + 4180658808U, // <0,0,3,6>: Cost 4 vsldoi8 <3,3,0,0>, <3,6,0,7> + 3374713464U, // <0,0,3,7>: Cost 4 vmrglw <3,2,0,3>, <3,6,0,7> + 3223290525U, // <0,0,3,u>: Cost 3 vmrghw <0,3,1,0>, LHS + 3223994368U, // <0,0,4,0>: Cost 3 vmrghw <0,4,1,5>, <0,0,0,0> + 2150252646U, // <0,0,4,1>: Cost 2 vmrghw <0,4,1,5>, LHS + 3223994541U, // <0,0,4,2>: Cost 4 vmrghw <0,4,1,5>, <0,2,1,2> + 3223290212U, // <0,0,4,3>: Cost 4 vsldoi12 <0,3,1,0>, <0,4,3,5> + 2150252882U, // <0,0,4,4>: Cost 2 vmrghw <0,4,1,5>, <0,4,1,5> + 3087011126U, // <0,0,4,5>: Cost 2 vsldoi8 <0,0,0,0>, RHS + 4160753017U, // <0,0,4,6>: Cost 4 vsldoi8 <0,0,0,0>, <4,6,5,2> + 3250127240U, // <0,0,4,7>: Cost 4 vsldoi12 <4,7,5,0>, <0,4,7,5> + 2150253213U, // <0,0,4,u>: Cost 2 vmrghw <0,4,1,5>, LHS + 3358138368U, // <0,0,5,0>: Cost 3 vmrglw <0,4,0,5>, <0,0,0,0> + 3224658022U, // <0,0,5,1>: Cost 3 vmrghw <0,5,1,5>, LHS + 4160753387U, // <0,0,5,2>: Cost 4 vsldoi8 <0,0,0,0>, <5,2,1,3> + 3395966100U, // <0,0,5,3>: Cost 4 vmrglw <6,7,0,5>, <7,2,0,3> + 4207202236U, // <0,0,5,4>: Cost 4 vsldoi8 <7,7,0,0>, <5,4,6,5> + 3376056788U, // <0,0,5,5>: Cost 3 vmrglw <3,4,0,5>, <3,4,0,5> + 3255583186U, // <0,0,5,6>: Cost 3 vsldoi12 <5,6,7,0>, <0,5,6,7> + 3395966428U, // <0,0,5,7>: Cost 4 vmrglw <6,7,0,5>, <7,6,0,7> + 3256910308U, // <0,0,5,u>: Cost 3 vsldoi12 <5,u,7,0>, <0,5,u,7> + 4160754005U, // <0,0,6,0>: Cost 3 vsldoi8 <0,0,0,0>, <6,0,7,0> + 3225264230U, // <0,0,6,1>: Cost 3 vmrghw <0,6,0,7>, LHS + 4160754170U, // <0,0,6,2>: Cost 3 vsldoi8 <0,0,0,0>, <6,2,7,3> + 4160754226U, // <0,0,6,3>: Cost 4 vsldoi8 <0,0,0,0>, <6,3,4,5> + 4068388150U, // <0,0,6,4>: Cost 4 vsldoi4 <7,0,0,6>, RHS + 4160754411U, // <0,0,6,5>: Cost 4 vsldoi8 <0,0,0,0>, <6,5,7,1> + 4160754488U, // <0,0,6,6>: Cost 3 vsldoi8 <0,0,0,0>, <6,6,6,6> + 4201231181U, // <0,0,6,7>: Cost 3 vsldoi8 <6,7,0,0>, <6,7,0,0> + 4201894814U, // <0,0,6,u>: Cost 3 vsldoi8 <6,u,0,0>, <6,u,0,0> + 4202558447U, // <0,0,7,0>: Cost 3 vsldoi8 <7,0,0,0>, <7,0,0,0> + 3225944166U, // <0,0,7,1>: Cost 3 vmrghw <0,7,1,0>, LHS + 3264578124U, // <0,0,7,2>: Cost 4 vsldoi12 <7,2,3,0>, <0,7,2,3> + 3377400112U, // <0,0,7,3>: Cost 4 vmrglw <3,6,0,7>, <3,2,0,3> + 4160755046U, // <0,0,7,4>: Cost 3 vsldoi8 <0,0,0,0>, <7,4,5,6> + 4068397154U, // <0,0,7,5>: Cost 4 vsldoi4 <7,0,0,7>, <5,6,7,0> + 3267527284U, // <0,0,7,6>: Cost 4 vsldoi12 <7,6,7,0>, <0,7,6,7> + 3377400440U, // <0,0,7,7>: Cost 3 vmrglw <3,6,0,7>, <3,6,0,7> + 4202558447U, // <0,0,7,u>: Cost 3 vsldoi8 <7,0,0,0>, <7,0,0,0> + 1343012966U, // <0,0,u,0>: Cost 1 vspltisw0 LHS + 1079222374U, // <0,0,u,1>: Cost 1 vmrghw LHS, LHS + 3228746397U, // <0,0,u,2>: Cost 2 vsldoi12 <1,2,3,0>, LHS + 3226706172U, // <0,0,u,3>: Cost 3 vmrghw LHS, <0,3,1,0> + 2152964434U, // <0,0,u,4>: Cost 2 vmrghw LHS, <0,4,1,5> + 3087014042U, // <0,0,u,5>: Cost 2 vsldoi8 <0,0,0,0>, RHS + 3255583186U, // <0,0,u,6>: Cost 3 vsldoi12 <5,6,7,0>, <0,5,6,7> + 4068406263U, // <0,0,u,7>: Cost 3 vsldoi4 <7,0,0,u>, <7,0,0,u> + 1079222941U, // <0,0,u,u>: Cost 1 vmrghw LHS, LHS + 4174692352U, // <0,1,0,0>: Cost 3 vsldoi8 <2,3,0,1>, <0,0,0,0> + 3100950630U, // <0,1,0,1>: Cost 2 vsldoi8 <2,3,0,1>, LHS + 3228746476U, // <0,1,0,2>: Cost 3 vsldoi12 <1,2,3,0>, <1,0,2,1> + 4044523668U, // <0,1,0,3>: Cost 3 vsldoi4 <3,0,1,0>, <3,0,1,0> + 4170047826U, // <0,1,0,4>: Cost 3 vsldoi8 <1,5,0,1>, <0,4,1,5> + 3355443538U, // <0,1,0,5>: Cost 3 vmrglw <0,0,0,0>, <0,4,1,5> + 4174692854U, // <0,1,0,6>: Cost 3 vsldoi8 <2,3,0,1>, <0,6,1,7> + 4068414456U, // <0,1,0,7>: Cost 3 vsldoi4 <7,0,1,0>, <7,0,1,0> + 3100951197U, // <0,1,0,u>: Cost 2 vsldoi8 <2,3,0,1>, LHS + 2952871946U, // <0,1,1,0>: Cost 2 vsldoi4 <0,0,1,1>, <0,0,1,1> + 2148361012U, // <0,1,1,1>: Cost 2 vmrghw LHS, <1,1,1,1> + 2148361110U, // <0,1,1,2>: Cost 2 vmrghw LHS, <1,2,3,0> + 3369386158U, // <0,1,1,3>: Cost 3 vmrglw <2,3,0,1>, <0,2,1,3> + 2952875318U, // <0,1,1,4>: Cost 2 vsldoi4 <0,0,1,1>, RHS + 3364741458U, // <0,1,1,5>: Cost 3 vmrglw <1,5,0,1>, <0,4,1,5> + 4026618279U, // <0,1,1,6>: Cost 3 vsldoi4 <0,0,1,1>, <6,1,7,1> + 4026618864U, // <0,1,1,7>: Cost 3 vsldoi4 <0,0,1,1>, <7,0,0,1> + 2148803964U, // <0,1,1,u>: Cost 2 vmrghw LHS, <1,u,3,0> + 2970796134U, // <0,1,2,0>: Cost 2 vsldoi4 <3,0,1,2>, LHS + 4032594660U, // <0,1,2,1>: Cost 3 vsldoi4 <1,0,1,2>, <1,0,1,2> + 4174693992U, // <0,1,2,2>: Cost 3 vsldoi8 <2,3,0,1>, <2,2,2,2> + 835584U, // <0,1,2,3>: Cost 0 copy LHS + 2970799414U, // <0,1,2,4>: Cost 2 vsldoi4 <3,0,1,2>, RHS + 4056485448U, // <0,1,2,5>: Cost 3 vsldoi4 <5,0,1,2>, <5,0,1,2> + 4174694330U, // <0,1,2,6>: Cost 3 vsldoi8 <2,3,0,1>, <2,6,3,7> + 2994689018U, // <0,1,2,7>: Cost 2 vsldoi4 <7,0,1,2>, <7,0,1,2> + 835584U, // <0,1,2,u>: Cost 0 copy LHS + 4174694548U, // <0,1,3,0>: Cost 3 vsldoi8 <2,3,0,1>, <3,0,1,0> + 3223290676U, // <0,1,3,1>: Cost 4 vmrghw <0,3,1,0>, <1,1,1,1> + 4174694728U, // <0,1,3,2>: Cost 3 vsldoi8 <2,3,0,1>, <3,2,3,0> + 4174694812U, // <0,1,3,3>: Cost 3 vsldoi8 <2,3,0,1>, <3,3,3,3> + 4174694914U, // <0,1,3,4>: Cost 3 vsldoi8 <2,3,0,1>, <3,4,5,6> + 3228746745U, // <0,1,3,5>: Cost 4 vsldoi12 <1,2,3,0>, <1,3,5,0> + 4201237168U, // <0,1,3,6>: Cost 3 vsldoi8 <6,7,0,1>, <3,6,7,0> + 4183321283U, // <0,1,3,7>: Cost 3 vsldoi8 <3,7,0,1>, <3,7,0,1> + 4174695198U, // <0,1,3,u>: Cost 3 vsldoi8 <2,3,0,1>, <3,u,1,2> + 4044554342U, // <0,1,4,0>: Cost 3 vsldoi4 <3,0,1,4>, LHS + 3223995188U, // <0,1,4,1>: Cost 3 vmrghw <0,4,1,5>, <1,1,1,1> + 3223995286U, // <0,1,4,2>: Cost 3 vmrghw <0,4,1,5>, <1,2,3,0> + 4044556440U, // <0,1,4,3>: Cost 3 vsldoi4 <3,0,1,4>, <3,0,1,4> + 4044557622U, // <0,1,4,4>: Cost 3 vsldoi4 <3,0,1,4>, RHS + 3100953910U, // <0,1,4,5>: Cost 2 vsldoi8 <2,3,0,1>, RHS + 4068447054U, // <0,1,4,6>: Cost 3 vsldoi4 <7,0,1,4>, <6,7,0,1> + 4068447228U, // <0,1,4,7>: Cost 3 vsldoi4 <7,0,1,4>, <7,0,1,4> + 3100954153U, // <0,1,4,u>: Cost 2 vsldoi8 <2,3,0,1>, RHS + 3228746863U, // <0,1,5,0>: Cost 4 vsldoi12 <1,2,3,0>, <1,5,0,1> + 4191284879U, // <0,1,5,1>: Cost 3 vsldoi8 <5,1,0,1>, <5,1,0,1> + 3376056470U, // <0,1,5,2>: Cost 3 vmrglw <3,4,0,5>, <3,0,1,2> + 3230737545U, // <0,1,5,3>: Cost 4 vsldoi12 <1,5,3,0>, <1,5,3,0> + 3228746903U, // <0,1,5,4>: Cost 4 vsldoi12 <1,2,3,0>, <1,5,4,5> + 4193939411U, // <0,1,5,5>: Cost 3 vsldoi8 <5,5,0,1>, <5,5,0,1> + 4194603044U, // <0,1,5,6>: Cost 3 vsldoi8 <5,6,0,1>, <5,6,0,1> + 4195266677U, // <0,1,5,7>: Cost 4 vsldoi8 <5,7,0,1>, <5,7,0,1> + 4195930310U, // <0,1,5,u>: Cost 3 vsldoi8 <5,u,0,1>, <5,u,0,1> + 4068458598U, // <0,1,6,0>: Cost 3 vsldoi4 <7,0,1,6>, LHS + 3228746959U, // <0,1,6,1>: Cost 4 vsldoi12 <1,2,3,0>, <1,6,1,7> + 4201239034U, // <0,1,6,2>: Cost 3 vsldoi8 <6,7,0,1>, <6,2,7,3> + 4178014792U, // <0,1,6,3>: Cost 4 vsldoi8 <2,u,0,1>, <6,3,7,0> + 4068461878U, // <0,1,6,4>: Cost 3 vsldoi4 <7,0,1,6>, RHS + 3228746995U, // <0,1,6,5>: Cost 4 vsldoi12 <1,2,3,0>, <1,6,5,7> + 4201239352U, // <0,1,6,6>: Cost 3 vsldoi8 <6,7,0,1>, <6,6,6,6> + 3127497550U, // <0,1,6,7>: Cost 2 vsldoi8 <6,7,0,1>, <6,7,0,1> + 3128161183U, // <0,1,6,u>: Cost 2 vsldoi8 <6,u,0,1>, <6,u,0,1> + 4201239544U, // <0,1,7,0>: Cost 3 vsldoi8 <6,7,0,1>, <7,0,1,0> + 3377397770U, // <0,1,7,1>: Cost 4 vmrglw <3,6,0,7>, <0,0,1,1> + 4174697644U, // <0,1,7,2>: Cost 3 vsldoi8 <2,3,0,1>, <7,2,3,0> + 4204557539U, // <0,1,7,3>: Cost 3 vsldoi8 <7,3,0,1>, <7,3,0,1> + 4201239910U, // <0,1,7,4>: Cost 3 vsldoi8 <6,7,0,1>, <7,4,5,6> + 3377398098U, // <0,1,7,5>: Cost 4 vmrglw <3,6,0,7>, <0,4,1,5> + 4201240084U, // <0,1,7,6>: Cost 3 vsldoi8 <6,7,0,1>, <7,6,7,0> + 4201240172U, // <0,1,7,7>: Cost 3 vsldoi8 <6,7,0,1>, <7,7,7,7> + 4201240194U, // <0,1,7,u>: Cost 3 vsldoi8 <6,7,0,1>, <7,u,1,2> + 2970845286U, // <0,1,u,0>: Cost 2 vsldoi4 <3,0,1,u>, LHS + 2152964916U, // <0,1,u,1>: Cost 2 vmrghw LHS, <1,1,1,1> + 2152965014U, // <0,1,u,2>: Cost 2 vmrghw LHS, <1,2,3,0> + 835584U, // <0,1,u,3>: Cost 0 copy LHS + 2970848566U, // <0,1,u,4>: Cost 2 vsldoi4 <3,0,1,u>, RHS + 3100956826U, // <0,1,u,5>: Cost 2 vsldoi8 <2,3,0,1>, RHS + 3226707151U, // <0,1,u,6>: Cost 3 vmrghw LHS, <1,6,1,7> + 2994738176U, // <0,1,u,7>: Cost 2 vsldoi4 <7,0,1,u>, <7,0,1,u> + 835584U, // <0,1,u,u>: Cost 0 copy LHS + 3221226957U, // <0,2,0,0>: Cost 3 vmrghw <0,0,0,0>, <2,0,3,0> + 3221308959U, // <0,2,0,1>: Cost 3 vmrghw <0,0,1,1>, <2,1,3,1> + 3221227112U, // <0,2,0,2>: Cost 3 vmrghw <0,0,0,0>, <2,2,2,2> + 2281701478U, // <0,2,0,3>: Cost 2 vmrglw <0,0,0,0>, LHS + 4044598582U, // <0,2,0,4>: Cost 4 vsldoi4 <3,0,2,0>, RHS + 3375350836U, // <0,2,0,5>: Cost 4 vmrglw <3,3,0,0>, <1,4,2,5> + 3221227450U, // <0,2,0,6>: Cost 3 vmrghw <0,0,0,0>, <2,6,3,7> + 3221227498U, // <0,2,0,7>: Cost 4 vmrghw <0,0,0,0>, <2,7,0,1> + 2281701483U, // <0,2,0,u>: Cost 2 vmrglw <0,0,0,0>, LHS + 3222504954U, // <0,2,1,0>: Cost 3 vmrghw LHS, <2,0,u,0> + 3222103583U, // <0,2,1,1>: Cost 3 vmrghw LHS, <2,1,3,1> + 2148361832U, // <0,2,1,2>: Cost 2 vmrghw LHS, <2,2,2,2> + 2148361894U, // <0,2,1,3>: Cost 2 vmrghw LHS, <2,3,0,1> + 3222505283U, // <0,2,1,4>: Cost 3 vmrghw LHS, <2,4,u,5> + 3222505365U, // <0,2,1,5>: Cost 3 vmrghw LHS, <2,5,u,6> + 2148362170U, // <0,2,1,6>: Cost 2 vmrghw LHS, <2,6,3,7> + 3222063082U, // <0,2,1,7>: Cost 3 vmrghw LHS, <2,7,0,1> + 2148362328U, // <0,2,1,u>: Cost 2 vmrghw LHS, <2,u,3,3> + 3222627834U, // <0,2,2,0>: Cost 4 vmrghw <0,2,1,0>, <2,0,u,0> + 3222636063U, // <0,2,2,1>: Cost 4 vmrghw <0,2,1,1>, <2,1,3,1> + 3222644328U, // <0,2,2,2>: Cost 3 vmrghw <0,2,1,2>, <2,2,2,2> + 3222652582U, // <0,2,2,3>: Cost 3 vmrghw <0,2,1,3>, <2,3,0,1> + 3222660931U, // <0,2,2,4>: Cost 4 vmrghw <0,2,1,4>, <2,4,u,5> + 3222669205U, // <0,2,2,5>: Cost 4 vmrghw <0,2,1,5>, <2,5,u,6> + 3222677434U, // <0,2,2,6>: Cost 3 vmrghw <0,2,1,6>, <2,6,3,7> + 4068504579U, // <0,2,2,7>: Cost 4 vsldoi4 <7,0,2,2>, <7,0,2,2> + 3222693976U, // <0,2,2,u>: Cost 3 vmrghw <0,2,1,u>, <2,u,3,3> + 3228747430U, // <0,2,3,0>: Cost 3 vsldoi12 <1,2,3,0>, <2,3,0,1> + 3228747440U, // <0,2,3,1>: Cost 3 vsldoi12 <1,2,3,0>, <2,3,1,2> + 3223291496U, // <0,2,3,2>: Cost 4 vmrghw <0,3,1,0>, <2,2,2,2> + 3228747456U, // <0,2,3,3>: Cost 3 vsldoi12 <1,2,3,0>, <2,3,3,0> + 3228747470U, // <0,2,3,4>: Cost 3 vsldoi12 <1,2,3,0>, <2,3,4,5> + 3255584472U, // <0,2,3,5>: Cost 3 vsldoi12 <5,6,7,0>, <2,3,5,6> + 3223291834U, // <0,2,3,6>: Cost 4 vmrghw <0,3,1,0>, <2,6,3,7> + 3235677924U, // <0,2,3,7>: Cost 3 vsldoi12 <2,3,7,0>, <2,3,7,0> + 3228747501U, // <0,2,3,u>: Cost 3 vsldoi12 <1,2,3,0>, <2,3,u,0> + 3223995898U, // <0,2,4,0>: Cost 4 vmrghw <0,4,1,5>, <2,0,u,0> + 3223995939U, // <0,2,4,1>: Cost 3 vmrghw <0,4,1,5>, <2,1,3,5> + 3223996008U, // <0,2,4,2>: Cost 3 vmrghw <0,4,1,5>, <2,2,2,2> + 3223996070U, // <0,2,4,3>: Cost 3 vmrghw <0,4,1,5>, <2,3,0,1> + 3223996223U, // <0,2,4,4>: Cost 4 vmrghw <0,4,1,5>, <2,4,u,1> + 3223996309U, // <0,2,4,5>: Cost 4 vmrghw <0,4,1,5>, <2,5,u,6> + 3223996346U, // <0,2,4,6>: Cost 3 vmrghw <0,4,1,5>, <2,6,3,7> + 4191292872U, // <0,2,4,7>: Cost 4 vsldoi8 <5,1,0,2>, <4,7,5,0> + 3223996475U, // <0,2,4,u>: Cost 3 vmrghw <0,4,1,5>, <2,u,0,1> + 3376054371U, // <0,2,5,0>: Cost 4 vmrglw <3,4,0,5>, <0,1,2,0> + 4191293072U, // <0,2,5,1>: Cost 4 vsldoi8 <5,1,0,2>, <5,1,0,2> + 3376055912U, // <0,2,5,2>: Cost 4 vmrglw <3,4,0,5>, <2,2,2,2> + 3376054374U, // <0,2,5,3>: Cost 3 vmrglw <3,4,0,5>, LHS + 3376054375U, // <0,2,5,4>: Cost 4 vmrglw <3,4,0,5>, <0,1,2,4> + 3374728244U, // <0,2,5,5>: Cost 4 vmrglw <3,2,0,5>, <1,4,2,5> + 4207882338U, // <0,2,5,6>: Cost 4 vsldoi8 <7,u,0,2>, <5,6,7,0> + 3376055512U, // <0,2,5,7>: Cost 4 vmrglw <3,4,0,5>, <1,6,2,7> + 3376054379U, // <0,2,5,u>: Cost 3 vmrglw <3,4,0,5>, LHS + 4044644454U, // <0,2,6,0>: Cost 4 vsldoi4 <3,0,2,6>, LHS + 4044645270U, // <0,2,6,1>: Cost 4 vsldoi4 <3,0,2,6>, <1,2,3,0> + 4044646330U, // <0,2,6,2>: Cost 4 vsldoi4 <3,0,2,6>, <2,6,3,7> + 3228747706U, // <0,2,6,3>: Cost 3 vsldoi12 <1,2,3,0>, <2,6,3,7> + 4044647734U, // <0,2,6,4>: Cost 4 vsldoi4 <3,0,2,6>, RHS + 4068536418U, // <0,2,6,5>: Cost 4 vsldoi4 <7,0,2,6>, <5,6,7,0> + 3225266106U, // <0,2,6,6>: Cost 4 vmrghw <0,6,0,7>, <2,6,3,7> + 4201247567U, // <0,2,6,7>: Cost 4 vsldoi8 <6,7,0,2>, <6,7,0,2> + 3228747751U, // <0,2,6,u>: Cost 3 vsldoi12 <1,2,3,0>, <2,6,u,7> + 4191294458U, // <0,2,7,0>: Cost 4 vsldoi8 <5,1,0,2>, <7,0,1,2> + 3377398508U, // <0,2,7,1>: Cost 4 vmrglw <3,6,0,7>, <1,0,2,1> + 3377398590U, // <0,2,7,2>: Cost 4 vmrglw <3,6,0,7>, <1,1,2,2> + 3377397862U, // <0,2,7,3>: Cost 3 vmrglw <3,6,0,7>, LHS + 4044655926U, // <0,2,7,4>: Cost 4 vsldoi4 <3,0,2,7>, RHS + 3377398836U, // <0,2,7,5>: Cost 4 vmrglw <3,6,0,7>, <1,4,2,5> + 4206556631U, // <0,2,7,6>: Cost 4 vsldoi8 <7,6,0,2>, <7,6,0,2> + 3225946090U, // <0,2,7,7>: Cost 4 vmrghw <0,7,1,0>, <2,7,0,1> + 3377397867U, // <0,2,7,u>: Cost 3 vmrglw <3,6,0,7>, LHS + 3226707450U, // <0,2,u,0>: Cost 3 vmrghw LHS, <2,0,u,0> + 3226707487U, // <0,2,u,1>: Cost 3 vmrghw LHS, <2,1,3,1> + 2152965736U, // <0,2,u,2>: Cost 2 vmrghw LHS, <2,2,2,2> + 2152965798U, // <0,2,u,3>: Cost 2 vmrghw LHS, <2,3,0,1> + 3226707779U, // <0,2,u,4>: Cost 3 vmrghw LHS, <2,4,u,5> + 3226707861U, // <0,2,u,5>: Cost 3 vmrghw LHS, <2,5,u,6> + 2152966074U, // <0,2,u,6>: Cost 2 vmrghw LHS, <2,6,3,7> + 3226707946U, // <0,2,u,7>: Cost 3 vmrghw LHS, <2,7,0,1> + 2152966203U, // <0,2,u,u>: Cost 2 vmrghw LHS, <2,u,0,1> + 4038696960U, // <0,3,0,0>: Cost 3 vsldoi4 <2,0,3,0>, <0,0,0,0> + 3223292054U, // <0,3,0,1>: Cost 3 vsldoi12 <0,3,1,0>, <3,0,1,2> + 4038698445U, // <0,3,0,2>: Cost 3 vsldoi4 <2,0,3,0>, <2,0,3,0> + 3221227932U, // <0,3,0,3>: Cost 3 vmrghw <0,0,0,0>, <3,3,3,3> + 3228747956U, // <0,3,0,4>: Cost 3 vsldoi12 <1,2,3,0>, <3,0,4,5> + 4068560994U, // <0,3,0,5>: Cost 4 vsldoi4 <7,0,3,0>, <5,6,7,0> + 4180017672U, // <0,3,0,6>: Cost 4 vsldoi8 <3,2,0,3>, <0,6,3,7> + 3355445178U, // <0,3,0,7>: Cost 3 vmrglw <0,0,0,0>, <2,6,3,7> + 3228747989U, // <0,3,0,u>: Cost 3 vsldoi12 <1,2,3,0>, <3,0,u,2> + 2148362390U, // <0,3,1,0>: Cost 2 vmrghw LHS, <3,0,1,2> + 3222104294U, // <0,3,1,1>: Cost 3 vmrghw LHS, <3,1,1,1> + 3222104385U, // <0,3,1,2>: Cost 3 vmrghw LHS, <3,2,2,2> + 2148362652U, // <0,3,1,3>: Cost 2 vmrghw LHS, <3,3,3,3> + 2148362754U, // <0,3,1,4>: Cost 2 vmrghw LHS, <3,4,5,6> + 3222063698U, // <0,3,1,5>: Cost 3 vmrghw LHS, <3,5,5,5> + 3222063736U, // <0,3,1,6>: Cost 3 vmrghw LHS, <3,6,0,7> + 3369387962U, // <0,3,1,7>: Cost 3 vmrglw <2,3,0,1>, <2,6,3,7> + 2148363038U, // <0,3,1,u>: Cost 2 vmrghw LHS, <3,u,1,2> + 3228748080U, // <0,3,2,0>: Cost 3 vsldoi12 <1,2,3,0>, <3,2,0,3> + 4044686230U, // <0,3,2,1>: Cost 4 vsldoi4 <3,0,3,2>, <1,2,3,0> + 3222645057U, // <0,3,2,2>: Cost 4 vmrghw <0,2,1,2>, <3,2,2,2> + 3240692040U, // <0,3,2,3>: Cost 3 vsldoi12 <3,2,3,0>, <3,2,3,0> + 3222645250U, // <0,3,2,4>: Cost 4 vmrghw <0,2,1,2>, <3,4,5,6> + 3362095460U, // <0,3,2,5>: Cost 5 vmrglw <1,1,0,2>, <0,4,3,5> + 3228748134U, // <0,3,2,6>: Cost 4 vsldoi12 <1,2,3,0>, <3,2,6,3> + 3365414842U, // <0,3,2,7>: Cost 4 vmrglw <1,6,0,2>, <2,6,3,7> + 3241060725U, // <0,3,2,u>: Cost 3 vsldoi12 <3,2,u,0>, <3,2,u,0> + 3223292054U, // <0,3,3,0>: Cost 3 vmrghw <0,3,1,0>, <3,0,1,2> + 3223300326U, // <0,3,3,1>: Cost 4 vmrghw <0,3,1,1>, <3,1,1,1> + 4180019504U, // <0,3,3,2>: Cost 3 vsldoi8 <3,2,0,3>, <3,2,0,3> + 3223316892U, // <0,3,3,3>: Cost 3 vmrghw <0,3,1,3>, <3,3,3,3> + 3223325186U, // <0,3,3,4>: Cost 3 vmrghw <0,3,1,4>, <3,4,5,6> + 4068585570U, // <0,3,3,5>: Cost 4 vsldoi4 <7,0,3,3>, <5,6,7,0> + 3228748212U, // <0,3,3,6>: Cost 4 vsldoi12 <1,2,3,0>, <3,3,6,0> + 3374712762U, // <0,3,3,7>: Cost 4 vmrglw <3,2,0,3>, <2,6,3,7> + 3223358238U, // <0,3,3,u>: Cost 3 vmrghw <0,3,1,u>, <3,u,1,2> + 3223996566U, // <0,3,4,0>: Cost 3 vmrghw <0,4,1,5>, <3,0,1,2> + 3223996646U, // <0,3,4,1>: Cost 4 vmrghw <0,4,1,5>, <3,1,1,1> + 3223996737U, // <0,3,4,2>: Cost 4 vmrghw <0,4,1,5>, <3,2,2,2> + 3223996828U, // <0,3,4,3>: Cost 3 vmrghw <0,4,1,5>, <3,3,3,3> + 3223996930U, // <0,3,4,4>: Cost 3 vmrghw <0,4,1,5>, <3,4,5,6> + 3228748290U, // <0,3,4,5>: Cost 3 vsldoi12 <1,2,3,0>, <3,4,5,6> + 4062622005U, // <0,3,4,6>: Cost 4 vsldoi4 <6,0,3,4>, <6,0,3,4> + 3364767674U, // <0,3,4,7>: Cost 4 vmrglw <1,5,0,4>, <2,6,3,7> + 3223997214U, // <0,3,4,u>: Cost 3 vmrghw <0,4,1,5>, <3,u,1,2> + 3228748326U, // <0,3,5,0>: Cost 4 vsldoi12 <1,2,3,0>, <3,5,0,6> + 3405916003U, // <0,3,5,1>: Cost 4 vmrglw , <2,5,3,1> + 3376055840U, // <0,3,5,2>: Cost 4 vmrglw <3,4,0,5>, <2,1,3,2> + 3376055679U, // <0,3,5,3>: Cost 4 vmrglw <3,4,0,5>, <1,u,3,3> + 3376055194U, // <0,3,5,4>: Cost 4 vmrglw <3,4,0,5>, <1,2,3,4> + 3255585362U, // <0,3,5,5>: Cost 4 vsldoi12 <5,6,7,0>, <3,5,5,5> + 4203909218U, // <0,3,5,6>: Cost 3 vsldoi8 <7,2,0,3>, <5,6,7,0> + 3376056250U, // <0,3,5,7>: Cost 4 vmrglw <3,4,0,5>, <2,6,3,7> + 4203909218U, // <0,3,5,u>: Cost 3 vsldoi8 <7,2,0,3>, <5,6,7,0> + 3228748408U, // <0,3,6,0>: Cost 3 vsldoi12 <1,2,3,0>, <3,6,0,7> + 4044718998U, // <0,3,6,1>: Cost 4 vsldoi4 <3,0,3,6>, <1,2,3,0> + 4197937595U, // <0,3,6,2>: Cost 4 vsldoi8 <6,2,0,3>, <6,2,0,3> + 4044720300U, // <0,3,6,3>: Cost 4 vsldoi4 <3,0,3,6>, <3,0,3,6> + 3229117084U, // <0,3,6,4>: Cost 4 vsldoi12 <1,2,u,0>, <3,6,4,7> + 3376728235U, // <0,3,6,5>: Cost 5 vmrglw <3,5,0,6>, <3,0,3,5> + 3255585453U, // <0,3,6,6>: Cost 4 vsldoi12 <5,6,7,0>, <3,6,6,6> + 3243641520U, // <0,3,6,7>: Cost 3 vsldoi12 <3,6,7,0>, <3,6,7,0> + 3228748408U, // <0,3,6,u>: Cost 3 vsldoi12 <1,2,3,0>, <3,6,0,7> + 3377398678U, // <0,3,7,0>: Cost 3 vmrglw <3,6,0,7>, <1,2,3,0> + 4209882202U, // <0,3,7,1>: Cost 4 vsldoi8 , <7,1,2,u> + 4203910292U, // <0,3,7,2>: Cost 3 vsldoi8 <7,2,0,3>, <7,2,0,3> + 3377399410U, // <0,3,7,3>: Cost 4 vmrglw <3,6,0,7>, <2,2,3,3> + 3377398682U, // <0,3,7,4>: Cost 4 vmrglw <3,6,0,7>, <1,2,3,4> + 4203910593U, // <0,3,7,5>: Cost 4 vsldoi8 <7,2,0,3>, <7,5,6,7> + 3377399980U, // <0,3,7,6>: Cost 4 vmrglw <3,6,0,7>, <3,0,3,6> + 3375409082U, // <0,3,7,7>: Cost 4 vmrglw <3,3,0,7>, <2,6,3,7> + 4207892090U, // <0,3,7,u>: Cost 3 vsldoi8 <7,u,0,3>, <7,u,0,3> + 2152966294U, // <0,3,u,0>: Cost 2 vmrghw LHS, <3,0,1,2> + 3226708198U, // <0,3,u,1>: Cost 3 vmrghw LHS, <3,1,1,1> + 3226708289U, // <0,3,u,2>: Cost 3 vmrghw LHS, <3,2,2,2> + 2152966556U, // <0,3,u,3>: Cost 2 vmrghw LHS, <3,3,3,3> + 2152966658U, // <0,3,u,4>: Cost 2 vmrghw LHS, <3,4,5,6> + 3228748614U, // <0,3,u,5>: Cost 3 vsldoi12 <1,2,3,0>, <3,u,5,6> + 3273501520U, // <0,3,u,6>: Cost 3 vsldoi12 , <3,u,6,7> + 3369445306U, // <0,3,u,7>: Cost 3 vmrglw <2,3,0,u>, <2,6,3,7> + 2152966942U, // <0,3,u,u>: Cost 2 vmrghw LHS, <3,u,1,2> + 3221228433U, // <0,4,0,0>: Cost 3 vmrghw <0,0,0,0>, <4,0,5,0> + 4170072166U, // <0,4,0,1>: Cost 3 vsldoi8 <1,5,0,4>, LHS + 3235457913U, // <0,4,0,2>: Cost 4 vsldoi12 <2,3,4,0>, <4,0,2,3> + 4044744879U, // <0,4,0,3>: Cost 4 vsldoi4 <3,0,4,0>, <3,0,4,0> + 4170072402U, // <0,4,0,4>: Cost 3 vsldoi8 <1,5,0,4>, <0,4,1,5> + 2147487030U, // <0,4,0,5>: Cost 2 vmrghw <0,0,0,0>, RHS + 4170072593U, // <0,4,0,6>: Cost 4 vsldoi8 <1,5,0,4>, <0,6,4,7> + 3250129828U, // <0,4,0,7>: Cost 4 vsldoi12 <4,7,5,0>, <4,0,7,1> + 2147487273U, // <0,4,0,u>: Cost 2 vmrghw <0,0,0,0>, RHS + 2148322194U, // <0,4,1,0>: Cost 2 vmrghw LHS, <4,0,5,1> + 3222064074U, // <0,4,1,1>: Cost 3 vmrghw LHS, <4,1,2,3> + 3222064181U, // <0,4,1,2>: Cost 3 vmrghw LHS, <4,2,5,2> + 4044753072U, // <0,4,1,3>: Cost 3 vsldoi4 <3,0,4,1>, <3,0,4,1> + 2148322512U, // <0,4,1,4>: Cost 2 vmrghw LHS, <4,4,4,4> + 1074580790U, // <0,4,1,5>: Cost 1 vmrghw LHS, RHS + 3222064505U, // <0,4,1,6>: Cost 3 vmrghw LHS, <4,6,5,2> + 4068643860U, // <0,4,1,7>: Cost 3 vsldoi4 <7,0,4,1>, <7,0,4,1> + 1074581033U, // <0,4,1,u>: Cost 1 vmrghw LHS, RHS + 4170073553U, // <0,4,2,0>: Cost 4 vsldoi8 <1,5,0,4>, <2,0,3,4> + 4170073635U, // <0,4,2,1>: Cost 4 vsldoi8 <1,5,0,4>, <2,1,3,5> + 4170073704U, // <0,4,2,2>: Cost 4 vsldoi8 <1,5,0,4>, <2,2,2,2> + 4174718633U, // <0,4,2,3>: Cost 3 vsldoi8 <2,3,0,4>, <2,3,0,4> + 4044762422U, // <0,4,2,4>: Cost 4 vsldoi4 <3,0,4,2>, RHS + 3222646070U, // <0,4,2,5>: Cost 3 vmrghw <0,2,1,2>, RHS + 4170074042U, // <0,4,2,6>: Cost 4 vsldoi8 <1,5,0,4>, <2,6,3,7> + 4177373165U, // <0,4,2,7>: Cost 4 vsldoi8 <2,7,0,4>, <2,7,0,4> + 3222646313U, // <0,4,2,u>: Cost 3 vmrghw <0,2,1,2>, RHS + 4170074262U, // <0,4,3,0>: Cost 4 vsldoi8 <1,5,0,4>, <3,0,1,2> + 4179364064U, // <0,4,3,1>: Cost 4 vsldoi8 <3,1,0,4>, <3,1,0,4> + 3229117549U, // <0,4,3,2>: Cost 5 vsldoi12 <1,2,u,0>, <4,3,2,4> + 4170074524U, // <0,4,3,3>: Cost 4 vsldoi8 <1,5,0,4>, <3,3,3,3> + 4170074626U, // <0,4,3,4>: Cost 4 vsldoi8 <1,5,0,4>, <3,4,5,6> + 3223293238U, // <0,4,3,5>: Cost 3 vmrghw <0,3,1,0>, RHS + 3229117585U, // <0,4,3,6>: Cost 5 vsldoi12 <1,2,u,0>, <4,3,6,4> + 4183345862U, // <0,4,3,7>: Cost 4 vsldoi8 <3,7,0,4>, <3,7,0,4> + 3223293481U, // <0,4,3,u>: Cost 3 vmrghw <0,3,1,0>, RHS + 4026859560U, // <0,4,4,0>: Cost 3 vsldoi4 <0,0,4,4>, <0,0,4,4> + 3223997410U, // <0,4,4,1>: Cost 3 vmrghw <0,4,1,5>, <4,1,5,0> + 4026861091U, // <0,4,4,2>: Cost 4 vsldoi4 <0,0,4,4>, <2,1,3,5> + 4044777651U, // <0,4,4,3>: Cost 4 vsldoi4 <3,0,4,4>, <3,0,4,4> + 3255586000U, // <0,4,4,4>: Cost 3 vsldoi12 <5,6,7,0>, <4,4,4,4> + 2150255926U, // <0,4,4,5>: Cost 2 vmrghw <0,4,1,5>, RHS + 4026864043U, // <0,4,4,6>: Cost 4 vsldoi4 <0,0,4,4>, <6,1,7,5> + 3250130156U, // <0,4,4,7>: Cost 4 vsldoi12 <4,7,5,0>, <4,4,7,5> + 2150256169U, // <0,4,4,u>: Cost 2 vmrghw <0,4,1,5>, RHS + 4044783718U, // <0,4,5,0>: Cost 3 vsldoi4 <3,0,4,5>, LHS + 4044784534U, // <0,4,5,1>: Cost 3 vsldoi4 <3,0,4,5>, <1,2,3,0> + 4044785256U, // <0,4,5,2>: Cost 4 vsldoi4 <3,0,4,5>, <2,2,2,2> + 4044785844U, // <0,4,5,3>: Cost 3 vsldoi4 <3,0,4,5>, <3,0,4,5> + 4044786998U, // <0,4,5,4>: Cost 3 vsldoi4 <3,0,4,5>, RHS + 3255586092U, // <0,4,5,5>: Cost 3 vsldoi12 <5,6,7,0>, <4,5,5,6> + 3228749110U, // <0,4,5,6>: Cost 2 vsldoi12 <1,2,3,0>, RHS + 4068676632U, // <0,4,5,7>: Cost 3 vsldoi4 <7,0,4,5>, <7,0,4,5> + 3228749128U, // <0,4,5,u>: Cost 2 vsldoi12 <1,2,3,0>, RHS + 3235458385U, // <0,4,6,0>: Cost 4 vsldoi12 <2,3,4,0>, <4,6,0,7> + 4201263531U, // <0,4,6,1>: Cost 4 vsldoi8 <6,7,0,4>, <6,1,7,5> + 4201263610U, // <0,4,6,2>: Cost 4 vsldoi8 <6,7,0,4>, <6,2,7,3> + 4198609421U, // <0,4,6,3>: Cost 4 vsldoi8 <6,3,0,4>, <6,3,0,4> + 4068683062U, // <0,4,6,4>: Cost 4 vsldoi4 <7,0,4,6>, RHS + 3225267510U, // <0,4,6,5>: Cost 3 vmrghw <0,6,0,7>, RHS + 4201263928U, // <0,4,6,6>: Cost 4 vsldoi8 <6,7,0,4>, <6,6,6,6> + 4201263953U, // <0,4,6,7>: Cost 3 vsldoi8 <6,7,0,4>, <6,7,0,4> + 4201927586U, // <0,4,6,u>: Cost 3 vsldoi8 <6,u,0,4>, <6,u,0,4> + 3383371465U, // <0,4,7,0>: Cost 4 vmrglw <4,6,0,7>, <2,3,4,0> + 4203254852U, // <0,4,7,1>: Cost 4 vsldoi8 <7,1,0,4>, <7,1,0,4> + 4178040010U, // <0,4,7,2>: Cost 5 vsldoi8 <2,u,0,4>, <7,2,6,3> + 4204582118U, // <0,4,7,3>: Cost 4 vsldoi8 <7,3,0,4>, <7,3,0,4> + 4056747318U, // <0,4,7,4>: Cost 4 vsldoi4 <5,0,4,7>, RHS + 3250130376U, // <0,4,7,5>: Cost 3 vsldoi12 <4,7,5,0>, <4,7,5,0> + 3383372686U, // <0,4,7,6>: Cost 5 vmrglw <4,6,0,7>, <4,0,4,6> + 3250130394U, // <0,4,7,7>: Cost 4 vsldoi12 <4,7,5,0>, <4,7,7,0> + 3250130376U, // <0,4,7,u>: Cost 3 vsldoi12 <4,7,5,0>, <4,7,5,0> + 2152967058U, // <0,4,u,0>: Cost 2 vmrghw LHS, <4,0,5,1> + 3226708962U, // <0,4,u,1>: Cost 3 vmrghw LHS, <4,1,5,0> + 3226709045U, // <0,4,u,2>: Cost 3 vmrghw LHS, <4,2,5,2> + 4044810423U, // <0,4,u,3>: Cost 3 vsldoi4 <3,0,4,u>, <3,0,4,u> + 2152967376U, // <0,4,u,4>: Cost 2 vmrghw LHS, <4,4,4,4> + 1079225654U, // <0,4,u,5>: Cost 1 vmrghw LHS, RHS + 3228749353U, // <0,4,u,6>: Cost 2 vsldoi12 <1,2,3,0>, RHS + 4068701211U, // <0,4,u,7>: Cost 3 vsldoi4 <7,0,4,u>, <7,0,4,u> + 1079225897U, // <0,4,u,u>: Cost 1 vmrghw LHS, RHS + 3355446161U, // <0,5,0,0>: Cost 3 vmrglw <0,0,0,0>, <4,0,5,0> + 4181360742U, // <0,5,0,1>: Cost 3 vsldoi8 <3,4,0,5>, LHS + 4181360850U, // <0,5,0,2>: Cost 4 vsldoi8 <3,4,0,5>, <0,2,5,3> + 4181360892U, // <0,5,0,3>: Cost 4 vsldoi8 <3,4,0,5>, <0,3,1,0> + 4163445065U, // <0,5,0,4>: Cost 3 vsldoi8 <0,4,0,5>, <0,4,0,5> + 3221229572U, // <0,5,0,5>: Cost 3 vmrghw <0,0,0,0>, <5,5,5,5> + 3255586420U, // <0,5,0,6>: Cost 3 vsldoi12 <5,6,7,0>, <5,0,6,1> + 3250130556U, // <0,5,0,7>: Cost 4 vsldoi12 <4,7,5,0>, <5,0,7,0> + 4181361309U, // <0,5,0,u>: Cost 3 vsldoi8 <3,4,0,5>, LHS + 2977054822U, // <0,5,1,0>: Cost 2 vsldoi4 <4,0,5,1>, LHS + 3385978394U, // <0,5,1,1>: Cost 3 vmrglw <5,1,0,1>, <4,u,5,1> + 3222064875U, // <0,5,1,2>: Cost 3 vmrghw LHS, <5,2,1,3> + 4050798742U, // <0,5,1,3>: Cost 3 vsldoi4 <4,0,5,1>, <3,0,1,2> + 2977057682U, // <0,5,1,4>: Cost 2 vsldoi4 <4,0,5,1>, <4,0,5,1> + 2148323332U, // <0,5,1,5>: Cost 2 vmrghw LHS, <5,5,5,5> + 2148323426U, // <0,5,1,6>: Cost 2 vmrghw LHS, <5,6,7,0> + 4050801658U, // <0,5,1,7>: Cost 3 vsldoi4 <4,0,5,1>, <7,0,1,2> + 2148323575U, // <0,5,1,u>: Cost 2 vmrghw LHS, <5,u,5,5> + 4175390157U, // <0,5,2,0>: Cost 4 vsldoi8 <2,4,0,5>, <2,0,3,0> + 4181362208U, // <0,5,2,1>: Cost 4 vsldoi8 <3,4,0,5>, <2,1,3,2> + 4181362280U, // <0,5,2,2>: Cost 4 vsldoi8 <3,4,0,5>, <2,2,2,2> + 4181362342U, // <0,5,2,3>: Cost 4 vsldoi8 <3,4,0,5>, <2,3,0,1> + 4175390459U, // <0,5,2,4>: Cost 4 vsldoi8 <2,4,0,5>, <2,4,0,5> + 3255586575U, // <0,5,2,5>: Cost 4 vsldoi12 <5,6,7,0>, <5,2,5,3> + 4181362618U, // <0,5,2,6>: Cost 4 vsldoi8 <3,4,0,5>, <2,6,3,7> + 4207904746U, // <0,5,2,7>: Cost 4 vsldoi8 <7,u,0,5>, <2,7,0,1> + 4178044991U, // <0,5,2,u>: Cost 4 vsldoi8 <2,u,0,5>, <2,u,0,5> + 4181362838U, // <0,5,3,0>: Cost 3 vsldoi8 <3,4,0,5>, <3,0,1,2> + 4179372257U, // <0,5,3,1>: Cost 4 vsldoi8 <3,1,0,5>, <3,1,0,5> + 4180035890U, // <0,5,3,2>: Cost 4 vsldoi8 <3,2,0,5>, <3,2,0,5> + 4181363071U, // <0,5,3,3>: Cost 4 vsldoi8 <3,4,0,5>, <3,3,0,1> + 4181363156U, // <0,5,3,4>: Cost 3 vsldoi8 <3,4,0,5>, <3,4,0,5> + 3253448541U, // <0,5,3,5>: Cost 4 vsldoi12 <5,3,5,0>, <5,3,5,0> + 3364096514U, // <0,5,3,6>: Cost 4 vmrglw <1,4,0,3>, <3,4,5,6> + 4183354055U, // <0,5,3,7>: Cost 4 vsldoi8 <3,7,0,5>, <3,7,0,5> + 4184017688U, // <0,5,3,u>: Cost 3 vsldoi8 <3,u,0,5>, <3,u,0,5> + 4205251474U, // <0,5,4,0>: Cost 3 vsldoi8 <7,4,0,5>, <4,0,5,1> + 4032905994U, // <0,5,4,1>: Cost 4 vsldoi4 <1,0,5,4>, <1,0,5,4> + 4032906921U, // <0,5,4,2>: Cost 4 vsldoi4 <1,0,5,4>, <2,3,0,4> + 3364766635U, // <0,5,4,3>: Cost 4 vmrglw <1,5,0,4>, <1,2,5,3> + 3223998388U, // <0,5,4,4>: Cost 3 vmrghw <0,4,1,5>, <5,4,5,6> + 4181364022U, // <0,5,4,5>: Cost 3 vsldoi8 <3,4,0,5>, RHS + 3255586748U, // <0,5,4,6>: Cost 3 vsldoi12 <5,6,7,0>, <5,4,6,5> + 3364766963U, // <0,5,4,7>: Cost 4 vmrglw <1,5,0,4>, <1,6,5,7> + 4181364265U, // <0,5,4,u>: Cost 3 vsldoi8 <3,4,0,5>, RHS + 3242168274U, // <0,5,5,0>: Cost 4 vsldoi12 <3,4,5,0>, <5,5,0,0> + 3399945106U, // <0,5,5,1>: Cost 3 vmrglw <7,4,0,5>, <4,0,5,1> + 3224637163U, // <0,5,5,2>: Cost 4 vmrghw <0,5,1,2>, <5,2,1,3> + 3376054482U, // <0,5,5,3>: Cost 4 vmrglw <3,4,0,5>, <0,2,5,3> + 4193308550U, // <0,5,5,4>: Cost 4 vsldoi8 <5,4,0,5>, <5,4,0,5> + 3255586820U, // <0,5,5,5>: Cost 3 vsldoi12 <5,6,7,0>, <5,5,5,5> + 4201271394U, // <0,5,5,6>: Cost 3 vsldoi8 <6,7,0,5>, <5,6,7,0> + 3254923281U, // <0,5,5,7>: Cost 4 vsldoi12 <5,5,7,0>, <5,5,7,0> + 4213215492U, // <0,5,5,u>: Cost 3 vsldoi8 , <5,u,7,0> + 4068753510U, // <0,5,6,0>: Cost 3 vsldoi4 <7,0,5,6>, LHS + 3255586867U, // <0,5,6,1>: Cost 4 vsldoi12 <5,6,7,0>, <5,6,1,7> + 4201271802U, // <0,5,6,2>: Cost 4 vsldoi8 <6,7,0,5>, <6,2,7,3> + 3248877634U, // <0,5,6,3>: Cost 4 vsldoi12 <4,5,6,0>, <5,6,3,4> + 4068756790U, // <0,5,6,4>: Cost 3 vsldoi4 <7,0,5,6>, RHS + 4068757602U, // <0,5,6,5>: Cost 3 vsldoi4 <7,0,5,6>, <5,6,7,0> + 3228749920U, // <0,5,6,6>: Cost 4 vsldoi12 <1,2,3,0>, <5,6,6,7> + 3255586914U, // <0,5,6,7>: Cost 2 vsldoi12 <5,6,7,0>, <5,6,7,0> + 3255660651U, // <0,5,6,u>: Cost 2 vsldoi12 <5,6,u,0>, <5,6,u,0> + 4207907834U, // <0,5,7,0>: Cost 3 vsldoi8 <7,u,0,5>, <7,0,1,2> + 3255586941U, // <0,5,7,1>: Cost 4 vsldoi12 <5,6,7,0>, <5,7,1,0> + 4201272468U, // <0,5,7,2>: Cost 4 vsldoi8 <6,7,0,5>, <7,2,0,3> + 4181365987U, // <0,5,7,3>: Cost 4 vsldoi8 <3,4,0,5>, <7,3,0,1> + 4205253944U, // <0,5,7,4>: Cost 3 vsldoi8 <7,4,0,5>, <7,4,0,5> + 3255586977U, // <0,5,7,5>: Cost 4 vsldoi12 <5,6,7,0>, <5,7,5,0> + 3377398135U, // <0,5,7,6>: Cost 4 vmrglw <3,6,0,7>, <0,4,5,6> + 4201272870U, // <0,5,7,7>: Cost 4 vsldoi8 <6,7,0,5>, <7,7,0,0> + 4207908476U, // <0,5,7,u>: Cost 3 vsldoi8 <7,u,0,5>, <7,u,0,5> + 2977112166U, // <0,5,u,0>: Cost 2 vsldoi4 <4,0,5,u>, LHS + 4181366574U, // <0,5,u,1>: Cost 3 vsldoi8 <3,4,0,5>, LHS + 3226709739U, // <0,5,u,2>: Cost 3 vmrghw LHS, <5,2,1,3> + 4050856086U, // <0,5,u,3>: Cost 3 vsldoi4 <4,0,5,u>, <3,0,1,2> + 2977115033U, // <0,5,u,4>: Cost 2 vsldoi4 <4,0,5,u>, <4,0,5,u> + 2152968196U, // <0,5,u,5>: Cost 2 vmrghw LHS, <5,5,5,5> + 2152968290U, // <0,5,u,6>: Cost 2 vmrghw LHS, <5,6,7,0> + 3256914180U, // <0,5,u,7>: Cost 2 vsldoi12 <5,u,7,0>, <5,u,7,0> + 3256987917U, // <0,5,u,u>: Cost 2 vsldoi12 <5,u,u,0>, <5,u,u,0> + 3221229909U, // <0,6,0,0>: Cost 3 vmrghw <0,0,0,0>, <6,0,7,0> + 3221311911U, // <0,6,0,1>: Cost 3 vmrghw <0,0,1,1>, <6,1,7,1> + 3221230074U, // <0,6,0,2>: Cost 3 vmrghw <0,0,0,0>, <6,2,7,3> + 3248877877U, // <0,6,0,3>: Cost 4 vsldoi12 <4,5,6,0>, <6,0,3,4> + 3228750143U, // <0,6,0,4>: Cost 4 vsldoi12 <1,2,3,0>, <6,0,4,5> + 4056837747U, // <0,6,0,5>: Cost 4 vsldoi4 <5,0,6,0>, <5,0,6,0> + 3221230392U, // <0,6,0,6>: Cost 3 vmrghw <0,0,0,0>, <6,6,6,6> + 2281704758U, // <0,6,0,7>: Cost 2 vmrglw <0,0,0,0>, RHS + 2281704759U, // <0,6,0,u>: Cost 2 vmrglw <0,0,0,0>, RHS + 3222065441U, // <0,6,1,0>: Cost 3 vmrghw LHS, <6,0,1,2> + 3222065575U, // <0,6,1,1>: Cost 3 vmrghw LHS, <6,1,7,1> + 2148323834U, // <0,6,1,2>: Cost 2 vmrghw LHS, <6,2,7,3> + 3222065714U, // <0,6,1,3>: Cost 3 vmrghw LHS, <6,3,4,5> + 3222065777U, // <0,6,1,4>: Cost 3 vmrghw LHS, <6,4,2,5> + 3222065899U, // <0,6,1,5>: Cost 3 vmrghw LHS, <6,5,7,1> + 2148324152U, // <0,6,1,6>: Cost 2 vmrghw LHS, <6,6,6,6> + 2295647542U, // <0,6,1,7>: Cost 2 vmrglw <2,3,0,1>, RHS + 2295647543U, // <0,6,1,u>: Cost 2 vmrglw <2,3,0,1>, RHS + 3248878011U, // <0,6,2,0>: Cost 4 vsldoi12 <4,5,6,0>, <6,2,0,3> + 3222655401U, // <0,6,2,1>: Cost 4 vmrghw <0,2,1,3>, <6,1,7,3> + 3222581754U, // <0,6,2,2>: Cost 4 vmrghw <0,2,0,3>, <6,2,7,3> + 3258610131U, // <0,6,2,3>: Cost 4 vsldoi12 <6,2,3,0>, <6,2,3,0> + 4068797750U, // <0,6,2,4>: Cost 4 vsldoi4 <7,0,6,2>, RHS + 4068798562U, // <0,6,2,5>: Cost 4 vsldoi4 <7,0,6,2>, <5,6,7,0> + 4180043706U, // <0,6,2,6>: Cost 4 vsldoi8 <3,2,0,6>, <2,6,3,7> + 3255587322U, // <0,6,2,7>: Cost 3 vsldoi12 <5,6,7,0>, <6,2,7,3> + 3255587331U, // <0,6,2,u>: Cost 3 vsldoi12 <5,6,7,0>, <6,2,u,3> + 4180043926U, // <0,6,3,0>: Cost 4 vsldoi8 <3,2,0,6>, <3,0,1,2> + 3259126290U, // <0,6,3,1>: Cost 4 vsldoi12 <6,3,1,0>, <6,3,1,0> + 4180044083U, // <0,6,3,2>: Cost 4 vsldoi8 <3,2,0,6>, <3,2,0,6> + 3223327282U, // <0,6,3,3>: Cost 4 vmrghw <0,3,1,4>, <6,3,4,5> + 4182034946U, // <0,6,3,4>: Cost 4 vsldoi8 <3,5,0,6>, <3,4,5,6> + 4182034982U, // <0,6,3,5>: Cost 4 vsldoi8 <3,5,0,6>, <3,5,0,6> + 4068807240U, // <0,6,3,6>: Cost 4 vsldoi4 <7,0,6,3>, <6,3,7,0> + 3374714166U, // <0,6,3,7>: Cost 3 vmrglw <3,2,0,3>, RHS + 3374714167U, // <0,6,3,u>: Cost 3 vmrglw <3,2,0,3>, RHS + 4205259666U, // <0,6,4,0>: Cost 4 vsldoi8 <7,4,0,6>, <4,0,5,1> + 3223998891U, // <0,6,4,1>: Cost 3 vmrghw <0,4,1,5>, <6,1,7,5> + 3223998970U, // <0,6,4,2>: Cost 3 vmrghw <0,4,1,5>, <6,2,7,3> + 3223999026U, // <0,6,4,3>: Cost 4 vmrghw <0,4,1,5>, <6,3,4,5> + 3223990941U, // <0,6,4,4>: Cost 4 vmrghw <0,4,1,4>, <6,4,7,4> + 4180045110U, // <0,6,4,5>: Cost 4 vsldoi8 <3,2,0,6>, RHS + 3223999288U, // <0,6,4,6>: Cost 3 vmrghw <0,4,1,5>, <6,6,6,6> + 3364769078U, // <0,6,4,7>: Cost 3 vmrglw <1,5,0,4>, RHS + 3364769079U, // <0,6,4,u>: Cost 3 vmrglw <1,5,0,4>, RHS + 3248878257U, // <0,6,5,0>: Cost 4 vsldoi12 <4,5,6,0>, <6,5,0,6> + 3395964532U, // <0,6,5,1>: Cost 4 vmrglw <6,7,0,5>, <5,0,6,1> + 3260527293U, // <0,6,5,2>: Cost 4 vsldoi12 <6,5,2,0>, <6,5,2,0> + 3376056678U, // <0,6,5,3>: Cost 5 vmrglw <3,4,0,5>, <3,2,6,3> + 4056878390U, // <0,6,5,4>: Cost 4 vsldoi4 <5,0,6,5>, RHS + 3395964860U, // <0,6,5,5>: Cost 4 vmrglw <6,7,0,5>, <5,4,6,5> + 3260822241U, // <0,6,5,6>: Cost 4 vsldoi12 <6,5,6,0>, <6,5,6,0> + 3376057654U, // <0,6,5,7>: Cost 3 vmrglw <3,4,0,5>, RHS + 3376057655U, // <0,6,5,u>: Cost 3 vmrglw <3,4,0,5>, RHS + 3248878332U, // <0,6,6,0>: Cost 4 vsldoi12 <4,5,6,0>, <6,6,0,0> + 3398624745U, // <0,6,6,1>: Cost 4 vmrglw <7,2,0,6>, <2,0,6,1> + 3225301498U, // <0,6,6,2>: Cost 3 vmrghw <0,6,1,2>, <6,2,7,3> + 3225309746U, // <0,6,6,3>: Cost 4 vmrghw <0,6,1,3>, <6,3,4,5> + 4068830518U, // <0,6,6,4>: Cost 4 vsldoi4 <7,0,6,6>, RHS + 4199953073U, // <0,6,6,5>: Cost 4 vsldoi8 <6,5,0,6>, <6,5,0,6> + 3255587640U, // <0,6,6,6>: Cost 3 vsldoi12 <5,6,7,0>, <6,6,6,6> + 3255587650U, // <0,6,6,7>: Cost 3 vsldoi12 <5,6,7,0>, <6,6,7,7> + 3255587659U, // <0,6,6,u>: Cost 3 vsldoi12 <5,6,7,0>, <6,6,u,7> + 3255587662U, // <0,6,7,0>: Cost 3 vsldoi12 <5,6,7,0>, <6,7,0,1> + 3228750680U, // <0,6,7,1>: Cost 3 vsldoi12 <1,2,3,0>, <6,7,1,2> + 3377400084U, // <0,6,7,2>: Cost 4 vmrglw <3,6,0,7>, <3,1,6,2> + 3261928296U, // <0,6,7,3>: Cost 3 vsldoi12 <6,7,3,0>, <6,7,3,0> + 3255587702U, // <0,6,7,4>: Cost 3 vsldoi12 <5,6,7,0>, <6,7,4,5> + 3255587712U, // <0,6,7,5>: Cost 3 vsldoi12 <5,6,7,0>, <6,7,5,6> + 3255587717U, // <0,6,7,6>: Cost 4 vsldoi12 <5,6,7,0>, <6,7,6,2> + 3377401142U, // <0,6,7,7>: Cost 3 vmrglw <3,6,0,7>, RHS + 3377401143U, // <0,6,7,u>: Cost 3 vmrglw <3,6,0,7>, RHS + 3255587743U, // <0,6,u,0>: Cost 3 vsldoi12 <5,6,7,0>, <6,u,0,1> + 3226710439U, // <0,6,u,1>: Cost 3 vmrghw LHS, <6,1,7,1> + 2152968698U, // <0,6,u,2>: Cost 2 vmrghw LHS, <6,2,7,3> + 3262591929U, // <0,6,u,3>: Cost 3 vsldoi12 <6,u,3,0>, <6,u,3,0> + 3255587783U, // <0,6,u,4>: Cost 3 vsldoi12 <5,6,7,0>, <6,u,4,5> + 3255587712U, // <0,6,u,5>: Cost 3 vsldoi12 <5,6,7,0>, <6,7,5,6> + 2152969016U, // <0,6,u,6>: Cost 2 vmrghw LHS, <6,6,6,6> + 2295704886U, // <0,6,u,7>: Cost 2 vmrglw <2,3,0,u>, RHS + 2295704887U, // <0,6,u,u>: Cost 2 vmrglw <2,3,0,u>, RHS + 4062879744U, // <0,7,0,0>: Cost 3 vsldoi4 <6,0,7,0>, <0,0,0,0> + 4182704230U, // <0,7,0,1>: Cost 3 vsldoi8 <3,6,0,7>, LHS + 4044965818U, // <0,7,0,2>: Cost 4 vsldoi4 <3,0,7,0>, <2,6,3,7> + 3355447802U, // <0,7,0,3>: Cost 3 vmrglw <0,0,0,0>, <6,2,7,3> + 3255587864U, // <0,7,0,4>: Cost 3 vsldoi12 <5,6,7,0>, <7,0,4,5> + 3255587874U, // <0,7,0,5>: Cost 3 vsldoi12 <5,6,7,0>, <7,0,5,6> + 4062884181U, // <0,7,0,6>: Cost 3 vsldoi4 <6,0,7,0>, <6,0,7,0> + 3221231212U, // <0,7,0,7>: Cost 3 vmrghw <0,0,0,0>, <7,7,7,7> + 4182704797U, // <0,7,0,u>: Cost 3 vsldoi8 <3,6,0,7>, LHS + 2148324346U, // <0,7,1,0>: Cost 2 vmrghw LHS, <7,0,1,2> + 3222066250U, // <0,7,1,1>: Cost 3 vmrghw LHS, <7,1,1,1> + 4182705046U, // <0,7,1,2>: Cost 3 vsldoi8 <3,6,0,7>, <1,2,3,0> + 3395932666U, // <0,7,1,3>: Cost 3 vmrglw <6,7,0,1>, <6,2,7,3> + 2148324710U, // <0,7,1,4>: Cost 2 vmrghw LHS, <7,4,5,6> + 3222066614U, // <0,7,1,5>: Cost 3 vmrghw LHS, <7,5,5,5> + 4062892374U, // <0,7,1,6>: Cost 3 vsldoi4 <6,0,7,1>, <6,0,7,1> + 2148324972U, // <0,7,1,7>: Cost 2 vmrghw LHS, <7,7,7,7> + 2148324994U, // <0,7,1,u>: Cost 2 vmrghw LHS, <7,u,1,2> + 3255587988U, // <0,7,2,0>: Cost 3 vsldoi12 <5,6,7,0>, <7,2,0,3> + 4170761760U, // <0,7,2,1>: Cost 5 vsldoi8 <1,6,0,7>, <2,1,3,2> + 4182705768U, // <0,7,2,2>: Cost 4 vsldoi8 <3,6,0,7>, <2,2,2,2> + 3264582828U, // <0,7,2,3>: Cost 3 vsldoi12 <7,2,3,0>, <7,2,3,0> + 3255661752U, // <0,7,2,4>: Cost 4 vsldoi12 <5,6,u,0>, <7,2,4,3> + 4068872290U, // <0,7,2,5>: Cost 4 vsldoi4 <7,0,7,2>, <5,6,7,0> + 4180715450U, // <0,7,2,6>: Cost 4 vsldoi8 <3,3,0,7>, <2,6,3,7> + 4068873264U, // <0,7,2,7>: Cost 4 vsldoi4 <7,0,7,2>, <7,0,7,2> + 3264951513U, // <0,7,2,u>: Cost 3 vsldoi12 <7,2,u,0>, <7,2,u,0> + 3398602850U, // <0,7,3,0>: Cost 3 vmrglw <7,2,0,3>, <5,6,7,0> + 4182706417U, // <0,7,3,1>: Cost 4 vsldoi8 <3,6,0,7>, <3,1,2,3> + 4182706480U, // <0,7,3,2>: Cost 4 vsldoi8 <3,6,0,7>, <3,2,0,3> + 4180715909U, // <0,7,3,3>: Cost 4 vsldoi8 <3,3,0,7>, <3,3,0,7> + 4182706690U, // <0,7,3,4>: Cost 4 vsldoi8 <3,6,0,7>, <3,4,5,6> + 4206594653U, // <0,7,3,5>: Cost 4 vsldoi8 <7,6,0,7>, <3,5,6,7> + 4182706808U, // <0,7,3,6>: Cost 3 vsldoi8 <3,6,0,7>, <3,6,0,7> + 3398603586U, // <0,7,3,7>: Cost 4 vmrglw <7,2,0,3>, <6,6,7,7> + 4184034074U, // <0,7,3,u>: Cost 3 vsldoi8 <3,u,0,7>, <3,u,0,7> + 3223999482U, // <0,7,4,0>: Cost 3 vmrghw <0,4,1,5>, <7,0,1,2> + 4062913430U, // <0,7,4,1>: Cost 4 vsldoi4 <6,0,7,4>, <1,2,3,0> + 3223999636U, // <0,7,4,2>: Cost 4 vmrghw <0,4,1,5>, <7,2,0,3> + 4062915192U, // <0,7,4,3>: Cost 4 vsldoi4 <6,0,7,4>, <3,6,0,7> + 3223999846U, // <0,7,4,4>: Cost 3 vmrghw <0,4,1,5>, <7,4,5,6> + 4182707510U, // <0,7,4,5>: Cost 3 vsldoi8 <3,6,0,7>, RHS + 4188679505U, // <0,7,4,6>: Cost 4 vsldoi8 <4,6,0,7>, <4,6,0,7> + 3224000108U, // <0,7,4,7>: Cost 3 vmrghw <0,4,1,5>, <7,7,7,7> + 4182707753U, // <0,7,4,u>: Cost 3 vsldoi8 <3,6,0,7>, RHS + 3395965026U, // <0,7,5,0>: Cost 3 vmrglw <6,7,0,5>, <5,6,7,0> + 3399946987U, // <0,7,5,1>: Cost 4 vmrglw <7,4,0,5>, <6,5,7,1> + 3224671380U, // <0,7,5,2>: Cost 4 vmrghw <0,5,1,6>, <7,2,0,3> + 4062922902U, // <0,7,5,3>: Cost 4 vsldoi4 <6,0,7,5>, <3,0,1,2> + 4062924086U, // <0,7,5,4>: Cost 4 vsldoi4 <6,0,7,5>, RHS + 3255588278U, // <0,7,5,5>: Cost 4 vsldoi12 <5,6,7,0>, <7,5,5,5> + 3255588289U, // <0,7,5,6>: Cost 3 vsldoi12 <5,6,7,0>, <7,5,6,7> + 3395965762U, // <0,7,5,7>: Cost 4 vmrglw <6,7,0,5>, <6,6,7,7> + 3256915411U, // <0,7,5,u>: Cost 3 vsldoi12 <5,u,7,0>, <7,5,u,7> + 3255588316U, // <0,7,6,0>: Cost 3 vsldoi12 <5,6,7,0>, <7,6,0,7> + 4182708604U, // <0,7,6,1>: Cost 5 vsldoi8 <3,6,0,7>, <6,1,2,3> + 3255588334U, // <0,7,6,2>: Cost 4 vsldoi12 <5,6,7,0>, <7,6,2,7> + 3270555127U, // <0,7,6,3>: Cost 4 vsldoi12 , <7,6,3,7> + 3255662080U, // <0,7,6,4>: Cost 4 vsldoi12 <5,6,u,0>, <7,6,4,7> + 4068905058U, // <0,7,6,5>: Cost 4 vsldoi4 <7,0,7,6>, <5,6,7,0> + 3255588369U, // <0,7,6,6>: Cost 4 vsldoi12 <5,6,7,0>, <7,6,6,6> + 3267532308U, // <0,7,6,7>: Cost 3 vsldoi12 <7,6,7,0>, <7,6,7,0> + 3267606045U, // <0,7,6,u>: Cost 3 vsldoi12 <7,6,u,0>, <7,6,u,0> + 3255588390U, // <0,7,7,0>: Cost 3 vsldoi12 <5,6,7,0>, <7,7,0,0> + 4062938006U, // <0,7,7,1>: Cost 4 vsldoi4 <6,0,7,7>, <1,2,3,0> + 3264583227U, // <0,7,7,2>: Cost 4 vsldoi12 <7,2,3,0>, <7,7,2,3> + 3377397988U, // <0,7,7,3>: Cost 4 vmrglw <3,6,0,7>, <0,2,7,3> + 3225982310U, // <0,7,7,4>: Cost 3 vmrghw <0,7,1,4>, <7,4,5,6> + 3255588441U, // <0,7,7,5>: Cost 4 vsldoi12 <5,6,7,0>, <7,7,5,6> + 4206597596U, // <0,7,7,6>: Cost 3 vsldoi8 <7,6,0,7>, <7,6,0,7> + 3255588460U, // <0,7,7,7>: Cost 3 vsldoi12 <5,6,7,0>, <7,7,7,7> + 4207924862U, // <0,7,7,u>: Cost 3 vsldoi8 <7,u,0,7>, <7,u,0,7> + 2152969210U, // <0,7,u,0>: Cost 2 vmrghw LHS, <7,0,1,2> + 4182710062U, // <0,7,u,1>: Cost 3 vsldoi8 <3,6,0,7>, LHS + 4062946989U, // <0,7,u,2>: Cost 3 vsldoi4 <6,0,7,u>, <2,3,0,u> + 3395990010U, // <0,7,u,3>: Cost 3 vmrglw <6,7,0,u>, <6,2,7,3> + 2152969574U, // <0,7,u,4>: Cost 2 vmrghw LHS, <7,4,5,6> + 4182710426U, // <0,7,u,5>: Cost 3 vsldoi8 <3,6,0,7>, RHS + 4062949725U, // <0,7,u,6>: Cost 3 vsldoi4 <6,0,7,u>, <6,0,7,u> + 2152969836U, // <0,7,u,7>: Cost 2 vmrghw LHS, <7,7,7,7> + 2152969858U, // <0,7,u,u>: Cost 2 vmrghw LHS, <7,u,1,2> + 1343012966U, // <0,u,0,0>: Cost 1 vspltisw0 LHS + 3101007974U, // <0,u,0,1>: Cost 2 vsldoi8 <2,3,0,u>, LHS + 4039067130U, // <0,u,0,2>: Cost 3 vsldoi4 <2,0,u,0>, <2,0,u,0> + 2281701532U, // <0,u,0,3>: Cost 2 vmrglw <0,0,0,0>, LHS + 2953383222U, // <0,u,0,4>: Cost 2 vsldoi4 <0,0,u,0>, RHS + 2147489946U, // <0,u,0,5>: Cost 2 vmrghw <0,0,0,0>, RHS + 4174750261U, // <0,u,0,6>: Cost 3 vsldoi8 <2,3,0,u>, <0,6,u,7> + 2281704776U, // <0,u,0,7>: Cost 2 vmrglw <0,0,0,0>, RHS + 1343012966U, // <0,u,0,u>: Cost 1 vspltisw0 LHS + 2148767443U, // <0,u,1,0>: Cost 2 vmrghw LHS, + 1074583342U, // <0,u,1,1>: Cost 1 vmrghw LHS, LHS + 2148808584U, // <0,u,1,2>: Cost 2 vmrghw LHS, + 2148808636U, // <0,u,1,3>: Cost 2 vmrghw LHS, + 2148767807U, // <0,u,1,4>: Cost 2 vmrghw LHS, + 1074583706U, // <0,u,1,5>: Cost 1 vmrghw LHS, RHS + 2148808912U, // <0,u,1,6>: Cost 2 vmrghw LHS, + 2295647560U, // <0,u,1,7>: Cost 2 vmrglw <2,3,0,1>, RHS + 1074583909U, // <0,u,1,u>: Cost 1 vmrghw LHS, LHS + 2971312230U, // <0,u,2,0>: Cost 2 vsldoi4 <3,0,u,2>, LHS + 3222648622U, // <0,u,2,1>: Cost 3 vmrghw <0,2,1,2>, LHS + 4174751336U, // <0,u,2,2>: Cost 3 vsldoi8 <2,3,0,u>, <2,2,2,2> + 835584U, // <0,u,2,3>: Cost 0 copy LHS + 2971315510U, // <0,u,2,4>: Cost 2 vsldoi4 <3,0,u,2>, RHS + 3222648986U, // <0,u,2,5>: Cost 3 vmrghw <0,2,1,2>, RHS + 4174751674U, // <0,u,2,6>: Cost 3 vsldoi8 <2,3,0,u>, <2,6,3,7> + 2995205177U, // <0,u,2,7>: Cost 2 vsldoi4 <7,0,u,2>, <7,0,u,2> + 835584U, // <0,u,2,u>: Cost 0 copy LHS + 3228751804U, // <0,u,3,0>: Cost 3 vsldoi12 <1,2,3,0>, + 3223295790U, // <0,u,3,1>: Cost 3 vmrghw <0,3,1,0>, LHS + 4180060469U, // <0,u,3,2>: Cost 3 vsldoi8 <3,2,0,u>, <3,2,0,u> + 3228751830U, // <0,u,3,3>: Cost 3 vsldoi12 <1,2,3,0>, + 3228751844U, // <0,u,3,4>: Cost 3 vsldoi12 <1,2,3,0>, + 3223296154U, // <0,u,3,5>: Cost 3 vmrghw <0,3,1,0>, RHS + 4182715001U, // <0,u,3,6>: Cost 3 vsldoi8 <3,6,0,u>, <3,6,0,u> + 3374714184U, // <0,u,3,7>: Cost 3 vmrglw <3,2,0,3>, RHS + 3223296357U, // <0,u,3,u>: Cost 3 vmrghw <0,3,1,0>, LHS + 3224000211U, // <0,u,4,0>: Cost 3 vmrghw <0,4,1,5>, + 2150258478U, // <0,u,4,1>: Cost 2 vmrghw <0,4,1,5>, LHS + 3224000392U, // <0,u,4,2>: Cost 3 vmrghw <0,4,1,5>, + 3224000444U, // <0,u,4,3>: Cost 3 vmrghw <0,4,1,5>, + 2150252882U, // <0,u,4,4>: Cost 2 vmrghw <0,4,1,5>, <0,4,1,5> + 2150258842U, // <0,u,4,5>: Cost 2 vmrghw <0,4,1,5>, RHS + 3224000720U, // <0,u,4,6>: Cost 3 vmrghw <0,4,1,5>, + 3364769096U, // <0,u,4,7>: Cost 3 vmrglw <1,5,0,4>, RHS + 2150259045U, // <0,u,4,u>: Cost 2 vmrghw <0,4,1,5>, LHS + 4045078630U, // <0,u,5,0>: Cost 3 vsldoi4 <3,0,u,5>, LHS + 4045079446U, // <0,u,5,1>: Cost 3 vsldoi4 <3,0,u,5>, <1,2,3,0> + 3376056470U, // <0,u,5,2>: Cost 3 vmrglw <3,4,0,5>, <3,0,1,2> + 4045080792U, // <0,u,5,3>: Cost 3 vsldoi4 <3,0,u,5>, <3,0,u,5> + 4045081910U, // <0,u,5,4>: Cost 3 vsldoi4 <3,0,u,5>, RHS + 4193996762U, // <0,u,5,5>: Cost 3 vsldoi8 <5,5,0,u>, <5,5,0,u> + 3228752026U, // <0,u,5,6>: Cost 2 vsldoi12 <1,2,3,0>, RHS + 3376057672U, // <0,u,5,7>: Cost 3 vmrglw <3,4,0,5>, RHS + 3228752044U, // <0,u,5,u>: Cost 2 vsldoi12 <1,2,3,0>, RHS + 3229120693U, // <0,u,6,0>: Cost 3 vsldoi12 <1,2,u,0>, + 3225270062U, // <0,u,6,1>: Cost 3 vmrghw <0,6,0,7>, LHS + 4201296378U, // <0,u,6,2>: Cost 3 vsldoi8 <6,7,0,u>, <6,2,7,3> + 3228752080U, // <0,u,6,3>: Cost 3 vsldoi12 <1,2,3,0>, + 4068977974U, // <0,u,6,4>: Cost 3 vsldoi4 <7,0,u,6>, RHS + 4068757602U, // <0,u,6,5>: Cost 3 vsldoi4 <7,0,5,6>, <5,6,7,0> + 4201296696U, // <0,u,6,6>: Cost 3 vsldoi8 <6,7,0,u>, <6,6,6,6> + 3127554901U, // <0,u,6,7>: Cost 2 vsldoi8 <6,7,0,u>, <6,7,0,u> + 3128218534U, // <0,u,6,u>: Cost 2 vsldoi8 <6,u,0,u>, <6,u,0,u> + 3255589120U, // <0,u,7,0>: Cost 3 vsldoi12 <5,6,7,0>, + 3273726216U, // <0,u,7,1>: Cost 3 vsldoi12 , + 4203951257U, // <0,u,7,2>: Cost 3 vsldoi8 <7,2,0,u>, <7,2,0,u> + 3377397916U, // <0,u,7,3>: Cost 3 vmrglw <3,6,0,7>, LHS + 3255589160U, // <0,u,7,4>: Cost 3 vsldoi12 <5,6,7,0>, + 3255589170U, // <0,u,7,5>: Cost 3 vsldoi12 <5,6,7,0>, + 4206605789U, // <0,u,7,6>: Cost 3 vsldoi8 <7,6,0,u>, <7,6,0,u> + 3377401160U, // <0,u,7,7>: Cost 3 vmrglw <3,6,0,7>, RHS + 3377397921U, // <0,u,7,u>: Cost 3 vmrglw <3,6,0,7>, LHS + 1343012966U, // <0,u,u,0>: Cost 1 vspltisw0 LHS + 1079228206U, // <0,u,u,1>: Cost 1 vmrghw LHS, LHS + 2152970120U, // <0,u,u,2>: Cost 2 vmrghw LHS, + 835584U, // <0,u,u,3>: Cost 0 copy LHS + 2152970303U, // <0,u,u,4>: Cost 2 vmrghw LHS, + 1079228570U, // <0,u,u,5>: Cost 1 vmrghw LHS, RHS + 2152970448U, // <0,u,u,6>: Cost 2 vmrghw LHS, + 2295704904U, // <0,u,u,7>: Cost 2 vmrglw <2,3,0,u>, RHS + 835584U, // <0,u,u,u>: Cost 0 copy LHS + 3226615808U, // <1,0,0,0>: Cost 3 vsldoi12 <0,u,1,1>, <0,0,0,0> + 3221307402U, // <1,0,0,1>: Cost 2 vsldoi12 <0,0,1,1>, <0,0,1,1> + 4162150571U, // <1,0,0,2>: Cost 4 vsldoi8 <0,2,1,0>, <0,2,1,0> + 4162814204U, // <1,0,0,3>: Cost 3 vsldoi8 <0,3,1,0>, <0,3,1,0> + 3221528613U, // <1,0,0,4>: Cost 3 vsldoi12 <0,0,4,1>, <0,0,4,1> + 4164141470U, // <1,0,0,5>: Cost 3 vsldoi8 <0,5,1,0>, <0,5,1,0> + 4178739702U, // <1,0,0,6>: Cost 4 vsldoi8 <3,0,1,0>, <0,6,1,7> + 4165468736U, // <1,0,0,7>: Cost 3 vsldoi8 <0,7,1,0>, <0,7,1,0> + 3221823561U, // <1,0,0,u>: Cost 2 vsldoi12 <0,0,u,1>, <0,0,u,1> + 3360833536U, // <1,0,1,0>: Cost 3 vmrglw <0,u,1,1>, <0,0,0,0> + 2154201190U, // <1,0,1,1>: Cost 2 vmrghw <1,1,1,1>, LHS + 3226615910U, // <1,0,1,2>: Cost 2 vsldoi12 <0,u,1,1>, LHS + 3227861244U, // <1,0,1,3>: Cost 4 vmrghw <1,1,0,0>, <0,3,1,0> + 4033178934U, // <1,0,1,4>: Cost 3 vsldoi4 <1,1,0,1>, RHS + 4057067151U, // <1,0,1,5>: Cost 3 vsldoi4 <5,1,0,1>, <5,1,0,1> + 3261710478U, // <1,0,1,6>: Cost 3 vsldoi12 <6,7,0,1>, <0,1,6,7> + 4057068538U, // <1,0,1,7>: Cost 4 vsldoi4 <5,1,0,1>, <7,0,1,2> + 3226615964U, // <1,0,1,u>: Cost 2 vsldoi12 <0,u,1,1>, LHS + 3228745728U, // <1,0,2,0>: Cost 3 vmrghw <1,2,3,0>, <0,0,0,0> + 2155004006U, // <1,0,2,1>: Cost 2 vmrghw <1,2,3,0>, LHS + 3356862524U, // <1,0,2,2>: Cost 4 vmrglw <0,2,1,2>, <2,u,0,2> + 4178740902U, // <1,0,2,3>: Cost 3 vsldoi8 <3,0,1,0>, <2,3,0,1> + 3228746066U, // <1,0,2,4>: Cost 3 vmrghw <1,2,3,0>, <0,4,1,5> + 3373451732U, // <1,0,2,5>: Cost 3 vmrglw <3,0,1,2>, <3,4,0,5> + 4162815930U, // <1,0,2,6>: Cost 4 vsldoi8 <0,3,1,0>, <2,6,3,7> + 3369470584U, // <1,0,2,7>: Cost 4 vmrglw <2,3,1,2>, <3,6,0,7> + 2155004573U, // <1,0,2,u>: Cost 2 vmrghw <1,2,3,0>, LHS + 4162816150U, // <1,0,3,0>: Cost 3 vsldoi8 <0,3,1,0>, <3,0,1,2> + 3356870310U, // <1,0,3,1>: Cost 3 vmrglw <0,2,1,3>, <2,3,0,1> + 3229196462U, // <1,0,3,2>: Cost 4 vmrghw <1,3,0,1>, <0,2,1,3> + 4162816383U, // <1,0,3,3>: Cost 4 vsldoi8 <0,3,1,0>, <3,3,0,1> + 4162816514U, // <1,0,3,4>: Cost 4 vsldoi8 <0,3,1,0>, <3,4,5,6> + 4182059561U, // <1,0,3,5>: Cost 4 vsldoi8 <3,5,1,0>, <3,5,1,0> + 3261710640U, // <1,0,3,6>: Cost 4 vsldoi12 <6,7,0,1>, <0,3,6,7> + 3366824568U, // <1,0,3,7>: Cost 5 vmrglw <1,u,1,3>, <3,6,0,7> + 4184050460U, // <1,0,3,u>: Cost 3 vsldoi8 <3,u,1,0>, <3,u,1,0> + 4211256210U, // <1,0,4,0>: Cost 3 vsldoi8 , <4,0,5,1> + 3226616146U, // <1,0,4,1>: Cost 3 vsldoi12 <0,u,1,1>, <0,4,1,5> + 3226616155U, // <1,0,4,2>: Cost 5 vsldoi12 <0,u,1,1>, <0,4,2,5> + 3229860096U, // <1,0,4,3>: Cost 4 vmrghw <1,4,0,1>, <0,3,1,4> + 3226616173U, // <1,0,4,4>: Cost 4 vsldoi12 <0,u,1,1>, <0,4,4,5> + 4162817334U, // <1,0,4,5>: Cost 3 vsldoi8 <0,3,1,0>, RHS + 3230269942U, // <1,0,4,6>: Cost 5 vmrghw <1,4,5,6>, <0,6,1,7> + 4213247432U, // <1,0,4,7>: Cost 4 vsldoi8 , <4,7,5,0> + 4162817577U, // <1,0,4,u>: Cost 3 vsldoi8 <0,3,1,0>, RHS + 3358212096U, // <1,0,5,0>: Cost 3 vmrglw <0,4,1,5>, <0,0,0,0> + 3358213798U, // <1,0,5,1>: Cost 3 vmrglw <0,4,1,5>, <2,3,0,1> + 4211920619U, // <1,0,5,2>: Cost 4 vsldoi8 , <5,2,1,3> + 3230859520U, // <1,0,5,3>: Cost 4 vmrghw <1,5,4,6>, <0,3,1,4> + 3358213801U, // <1,0,5,4>: Cost 3 vmrglw <0,4,1,5>, <2,3,0,4> + 4057099923U, // <1,0,5,5>: Cost 4 vsldoi4 <5,1,0,5>, <5,1,0,5> + 4195332194U, // <1,0,5,6>: Cost 4 vsldoi8 <5,7,1,0>, <5,6,7,0> + 4195332221U, // <1,0,5,7>: Cost 4 vsldoi8 <5,7,1,0>, <5,7,1,0> + 3358213805U, // <1,0,5,u>: Cost 3 vmrglw <0,4,1,5>, <2,3,0,u> + 3356893184U, // <1,0,6,0>: Cost 4 vmrglw <0,2,1,6>, <0,0,0,0> + 3231309926U, // <1,0,6,1>: Cost 3 vmrghw <1,6,1,7>, LHS + 3231187121U, // <1,0,6,2>: Cost 4 vmrghw <1,6,0,1>, <0,2,1,6> + 3231236348U, // <1,0,6,3>: Cost 4 vmrghw <1,6,0,7>, <0,3,1,0> + 3231605074U, // <1,0,6,4>: Cost 3 vmrghw <1,6,5,7>, <0,4,1,5> + 4211258091U, // <1,0,6,5>: Cost 4 vsldoi8 , <6,5,7,1> + 4202631992U, // <1,0,6,6>: Cost 4 vsldoi8 <7,0,1,0>, <6,6,6,6> + 4202632014U, // <1,0,6,7>: Cost 3 vsldoi8 <7,0,1,0>, <6,7,0,1> + 3231310482U, // <1,0,6,u>: Cost 3 vmrghw <1,6,1,7>, <0,u,1,1> + 4202632184U, // <1,0,7,0>: Cost 3 vsldoi8 <7,0,1,0>, <7,0,1,0> + 3359557286U, // <1,0,7,1>: Cost 3 vmrglw <0,6,1,7>, <2,3,0,1> + 4208604377U, // <1,0,7,2>: Cost 4 vsldoi8 , <7,2,u,0> + 4210595043U, // <1,0,7,3>: Cost 4 vsldoi8 , <7,3,0,1> + 4202632550U, // <1,0,7,4>: Cost 4 vsldoi8 <7,0,1,0>, <7,4,5,6> + 4205950349U, // <1,0,7,5>: Cost 4 vsldoi8 <7,5,1,0>, <7,5,1,0> + 4202632724U, // <1,0,7,6>: Cost 4 vsldoi8 <7,0,1,0>, <7,6,7,0> + 4202632812U, // <1,0,7,7>: Cost 4 vsldoi8 <7,0,1,0>, <7,7,7,7> + 4207941248U, // <1,0,7,u>: Cost 3 vsldoi8 <7,u,1,0>, <7,u,1,0> + 3358236672U, // <1,0,u,0>: Cost 3 vmrglw <0,4,1,u>, <0,0,0,0> + 3226616466U, // <1,0,u,1>: Cost 2 vsldoi12 <0,u,1,1>, <0,u,1,1> + 3226616477U, // <1,0,u,2>: Cost 2 vsldoi12 <0,u,1,1>, LHS + 4210595780U, // <1,0,u,3>: Cost 3 vsldoi8 , + 3226837677U, // <1,0,u,4>: Cost 3 vsldoi12 <0,u,4,1>, <0,u,4,1> + 4162820250U, // <1,0,u,5>: Cost 3 vsldoi8 <0,3,1,0>, RHS + 3261710478U, // <1,0,u,6>: Cost 3 vsldoi12 <6,7,0,1>, <0,1,6,7> + 4213250312U, // <1,0,u,7>: Cost 3 vsldoi8 , + 3226616531U, // <1,0,u,u>: Cost 2 vsldoi12 <0,u,1,1>, LHS + 3087089674U, // <1,1,0,0>: Cost 2 vsldoi8 <0,0,1,1>, <0,0,1,1> + 3092398182U, // <1,1,0,1>: Cost 2 vsldoi8 <0,u,1,1>, LHS + 3357509782U, // <1,1,0,2>: Cost 3 vmrglw <0,3,1,0>, <3,0,1,2> + 3357507596U, // <1,1,0,3>: Cost 4 vmrglw <0,3,1,0>, <0,0,1,3> + 4166140242U, // <1,1,0,4>: Cost 3 vsldoi8 <0,u,1,1>, <0,4,1,5> + 3357507922U, // <1,1,0,5>: Cost 4 vmrglw <0,3,1,0>, <0,4,1,5> + 3227288783U, // <1,1,0,6>: Cost 4 vmrghw <1,0,1,2>, <1,6,1,7> + 3373433334U, // <1,1,0,7>: Cost 4 vmrglw <3,0,1,0>, <0,6,1,7> + 3092398738U, // <1,1,0,u>: Cost 2 vsldoi8 <0,u,1,1>, <0,u,1,1> + 2959507558U, // <1,1,1,0>: Cost 2 vsldoi4 <1,1,1,1>, LHS + 1477230694U, // <1,1,1,1>: Cost 1 vspltisw1 LHS + 3360835734U, // <1,1,1,2>: Cost 3 vmrglw <0,u,1,1>, <3,0,1,2> + 3360834439U, // <1,1,1,3>: Cost 3 vmrglw <0,u,1,1>, <1,2,1,3> + 2959510838U, // <1,1,1,4>: Cost 2 vsldoi4 <1,1,1,1>, RHS + 3360833874U, // <1,1,1,5>: Cost 3 vmrglw <0,u,1,1>, <0,4,1,5> + 4166141135U, // <1,1,1,6>: Cost 3 vsldoi8 <0,u,1,1>, <1,6,1,7> + 4069086282U, // <1,1,1,7>: Cost 3 vsldoi4 <7,1,1,1>, <7,1,1,1> + 1477230694U, // <1,1,1,u>: Cost 1 vspltisw1 LHS + 3228746476U, // <1,1,2,0>: Cost 3 vmrghw <1,2,3,0>, <1,0,2,1> + 3226616711U, // <1,1,2,1>: Cost 3 vsldoi12 <0,u,1,1>, <1,2,1,3> + 2155004822U, // <1,1,2,2>: Cost 2 vmrghw <1,2,3,0>, <1,2,3,0> + 4166141606U, // <1,1,2,3>: Cost 3 vsldoi8 <0,u,1,1>, <2,3,0,1> + 4027288886U, // <1,1,2,4>: Cost 3 vsldoi4 <0,1,1,2>, RHS + 3373449554U, // <1,1,2,5>: Cost 3 vmrglw <3,0,1,2>, <0,4,1,5> + 4166141882U, // <1,1,2,6>: Cost 3 vsldoi8 <0,u,1,1>, <2,6,3,7> + 3361506511U, // <1,1,2,7>: Cost 4 vmrglw <1,0,1,2>, <1,6,1,7> + 2155004822U, // <1,1,2,u>: Cost 2 vmrghw <1,2,3,0>, <1,2,3,0> + 4166142102U, // <1,1,3,0>: Cost 3 vsldoi8 <0,u,1,1>, <3,0,1,2> + 4167469286U, // <1,1,3,1>: Cost 3 vsldoi8 <1,1,1,1>, <3,1,1,1> + 3356870806U, // <1,1,3,2>: Cost 4 vmrglw <0,2,1,3>, <3,0,1,2> + 3356868782U, // <1,1,3,3>: Cost 3 vmrglw <0,2,1,3>, <0,2,1,3> + 4166142466U, // <1,1,3,4>: Cost 3 vsldoi8 <0,u,1,1>, <3,4,5,6> + 3356868946U, // <1,1,3,5>: Cost 4 vmrglw <0,2,1,3>, <0,4,1,5> + 4213918328U, // <1,1,3,6>: Cost 4 vsldoi8 , <3,6,0,7> + 3362841807U, // <1,1,3,7>: Cost 4 vmrglw <1,2,1,3>, <1,6,1,7> + 4166142750U, // <1,1,3,u>: Cost 3 vsldoi8 <0,u,1,1>, <3,u,1,2> + 4033273958U, // <1,1,4,0>: Cost 3 vsldoi4 <1,1,1,4>, LHS + 3227943979U, // <1,1,4,1>: Cost 3 vsldoi12 <1,1,1,1>, <1,4,1,5> + 3230040982U, // <1,1,4,2>: Cost 3 vmrghw <1,4,2,5>, <1,2,3,0> + 4033276054U, // <1,1,4,3>: Cost 4 vsldoi4 <1,1,1,4>, <3,0,1,2> + 3357540608U, // <1,1,4,4>: Cost 3 vmrglw <0,3,1,4>, <0,3,1,4> + 3092401462U, // <1,1,4,5>: Cost 2 vsldoi8 <0,u,1,1>, RHS + 3230270671U, // <1,1,4,6>: Cost 4 vmrghw <1,4,5,6>, <1,6,1,7> + 3373466102U, // <1,1,4,7>: Cost 4 vmrglw <3,0,1,4>, <0,6,1,7> + 3092401705U, // <1,1,4,u>: Cost 2 vsldoi8 <0,u,1,1>, RHS + 3230524527U, // <1,1,5,0>: Cost 3 vsldoi12 <1,5,0,1>, <1,5,0,1> + 3358212106U, // <1,1,5,1>: Cost 3 vmrglw <0,4,1,5>, <0,0,1,1> + 3358214294U, // <1,1,5,2>: Cost 3 vmrglw <0,4,1,5>, <3,0,1,2> + 3358212270U, // <1,1,5,3>: Cost 4 vmrglw <0,4,1,5>, <0,2,1,3> + 3358212109U, // <1,1,5,4>: Cost 3 vmrglw <0,4,1,5>, <0,0,1,4> + 2284470610U, // <1,1,5,5>: Cost 2 vmrglw <0,4,1,5>, <0,4,1,5> + 4213919842U, // <1,1,5,6>: Cost 3 vsldoi8 , <5,6,7,0> + 3360867535U, // <1,1,5,7>: Cost 4 vmrglw <0,u,1,5>, <1,6,1,7> + 2284470610U, // <1,1,5,u>: Cost 2 vmrglw <0,4,1,5>, <0,4,1,5> + 4033290342U, // <1,1,6,0>: Cost 4 vsldoi4 <1,1,1,6>, LHS + 3226617039U, // <1,1,6,1>: Cost 3 vsldoi12 <0,u,1,1>, <1,6,1,7> + 4213920250U, // <1,1,6,2>: Cost 3 vsldoi8 , <6,2,7,3> + 3235169505U, // <1,1,6,3>: Cost 4 vsldoi12 <2,3,0,1>, <1,6,3,7> + 4033293622U, // <1,1,6,4>: Cost 4 vsldoi4 <1,1,1,6>, RHS + 3356893522U, // <1,1,6,5>: Cost 4 vmrglw <0,2,1,6>, <0,4,1,5> + 3356893361U, // <1,1,6,6>: Cost 3 vmrglw <0,2,1,6>, <0,2,1,6> + 3261711614U, // <1,1,6,7>: Cost 3 vsldoi12 <6,7,0,1>, <1,6,7,0> + 3262375175U, // <1,1,6,u>: Cost 3 vsldoi12 <6,u,0,1>, <1,6,u,0> + 4213920762U, // <1,1,7,0>: Cost 3 vsldoi8 , <7,0,1,2> + 3365528210U, // <1,1,7,1>: Cost 3 vmrglw <1,6,1,7>, <0,u,1,1> + 3365528292U, // <1,1,7,2>: Cost 4 vmrglw <1,6,1,7>, <1,0,1,2> + 3365528455U, // <1,1,7,3>: Cost 4 vmrglw <1,6,1,7>, <1,2,1,3> + 4213921126U, // <1,1,7,4>: Cost 3 vsldoi8 , <7,4,5,6> + 3365527890U, // <1,1,7,5>: Cost 4 vmrglw <1,6,1,7>, <0,4,1,5> + 3365528377U, // <1,1,7,6>: Cost 4 vmrglw <1,6,1,7>, <1,1,1,6> + 3365528783U, // <1,1,7,7>: Cost 3 vmrglw <1,6,1,7>, <1,6,1,7> + 4213921410U, // <1,1,7,u>: Cost 3 vsldoi8 , <7,u,1,2> + 2959507558U, // <1,1,u,0>: Cost 2 vsldoi4 <1,1,1,1>, LHS + 1477230694U, // <1,1,u,1>: Cost 1 vspltisw1 LHS + 2155004822U, // <1,1,u,2>: Cost 2 vmrghw <1,2,3,0>, <1,2,3,0> + 4166145980U, // <1,1,u,3>: Cost 3 vsldoi8 <0,u,1,1>, + 2959510838U, // <1,1,u,4>: Cost 2 vsldoi4 <1,1,1,1>, RHS + 3092404378U, // <1,1,u,5>: Cost 2 vsldoi8 <0,u,1,1>, RHS + 4166146256U, // <1,1,u,6>: Cost 3 vsldoi8 <0,u,1,1>, + 4213258505U, // <1,1,u,7>: Cost 3 vsldoi8 , + 1477230694U, // <1,1,u,u>: Cost 1 vspltisw1 LHS + 4178755584U, // <1,2,0,0>: Cost 3 vsldoi8 <3,0,1,2>, <0,0,0,0> + 3105013862U, // <1,2,0,1>: Cost 2 vsldoi8 <3,0,1,2>, LHS + 4162166957U, // <1,2,0,2>: Cost 3 vsldoi8 <0,2,1,2>, <0,2,1,2> + 3357507686U, // <1,2,0,3>: Cost 3 vmrglw <0,3,1,0>, LHS + 4178755922U, // <1,2,0,4>: Cost 3 vsldoi8 <3,0,1,2>, <0,4,1,5> + 4190699997U, // <1,2,0,5>: Cost 4 vsldoi8 <5,0,1,2>, <0,5,u,0> + 4164821489U, // <1,2,0,6>: Cost 3 vsldoi8 <0,6,1,2>, <0,6,1,2> + 4202644032U, // <1,2,0,7>: Cost 3 vsldoi8 <7,0,1,2>, <0,7,1,0> + 3105014429U, // <1,2,0,u>: Cost 2 vsldoi8 <3,0,1,2>, LHS + 4166812388U, // <1,2,1,0>: Cost 3 vsldoi8 <1,0,1,2>, <1,0,1,2> + 4178756404U, // <1,2,1,1>: Cost 3 vsldoi8 <3,0,1,2>, <1,1,1,1> + 3360835176U, // <1,2,1,2>: Cost 3 vmrglw <0,u,1,1>, <2,2,2,2> + 2287091814U, // <1,2,1,3>: Cost 2 vmrglw <0,u,1,1>, LHS + 4166812706U, // <1,2,1,4>: Cost 4 vsldoi8 <1,0,1,2>, <1,4,0,5> + 3227944808U, // <1,2,1,5>: Cost 4 vmrghw <1,1,1,1>, <2,5,3,6> + 3227944890U, // <1,2,1,6>: Cost 3 vmrghw <1,1,1,1>, <2,6,3,7> + 4202644777U, // <1,2,1,7>: Cost 4 vsldoi8 <7,0,1,2>, <1,7,2,7> + 2287091819U, // <1,2,1,u>: Cost 2 vmrglw <0,u,1,1>, LHS + 4033331302U, // <1,2,2,0>: Cost 3 vsldoi4 <1,1,2,2>, LHS + 4178757152U, // <1,2,2,1>: Cost 3 vsldoi8 <3,0,1,2>, <2,1,3,2> + 3356862056U, // <1,2,2,2>: Cost 3 vmrglw <0,2,1,2>, <2,2,2,2> + 2299707494U, // <1,2,2,3>: Cost 2 vmrglw <3,0,1,2>, LHS + 4033334582U, // <1,2,2,4>: Cost 3 vsldoi4 <1,1,2,2>, RHS + 3356860763U, // <1,2,2,5>: Cost 4 vmrglw <0,2,1,2>, <0,4,2,5> + 3228747706U, // <1,2,2,6>: Cost 3 vmrghw <1,2,3,0>, <2,6,3,7> + 3373450456U, // <1,2,2,7>: Cost 3 vmrglw <3,0,1,2>, <1,6,2,7> + 2299707499U, // <1,2,2,u>: Cost 2 vmrglw <3,0,1,2>, LHS + 1879883878U, // <1,2,3,0>: Cost 1 vsldoi4 LHS, LHS + 2953626420U, // <1,2,3,1>: Cost 2 vsldoi4 LHS, <1,1,1,1> + 2953627240U, // <1,2,3,2>: Cost 2 vsldoi4 LHS, <2,2,2,2> + 2953628060U, // <1,2,3,3>: Cost 2 vsldoi4 LHS, <3,3,3,3> + 1879887158U, // <1,2,3,4>: Cost 1 vsldoi4 LHS, RHS + 3001405444U, // <1,2,3,5>: Cost 2 vsldoi4 LHS, <5,5,5,5> + 3001405946U, // <1,2,3,6>: Cost 2 vsldoi4 LHS, <6,2,7,3> + 3001406458U, // <1,2,3,7>: Cost 2 vsldoi4 LHS, <7,0,1,2> + 1879889710U, // <1,2,3,u>: Cost 1 vsldoi4 LHS, LHS + 4184730479U, // <1,2,4,0>: Cost 3 vsldoi8 <4,0,1,2>, <4,0,1,2> + 3234064132U, // <1,2,4,1>: Cost 4 vsldoi12 <2,1,3,1>, <2,4,1,5> + 3357541992U, // <1,2,4,2>: Cost 4 vmrglw <0,3,1,4>, <2,2,2,2> + 3357540454U, // <1,2,4,3>: Cost 3 vmrglw <0,3,1,4>, LHS + 4202646736U, // <1,2,4,4>: Cost 3 vsldoi8 <7,0,1,2>, <4,4,4,4> + 3105017142U, // <1,2,4,5>: Cost 2 vsldoi8 <3,0,1,2>, RHS + 3229968314U, // <1,2,4,6>: Cost 4 vmrghw <1,4,1,5>, <2,6,3,7> + 4202646984U, // <1,2,4,7>: Cost 3 vsldoi8 <7,0,1,2>, <4,7,5,0> + 3105017385U, // <1,2,4,u>: Cost 2 vsldoi8 <3,0,1,2>, RHS + 4190703176U, // <1,2,5,0>: Cost 3 vsldoi8 <5,0,1,2>, <5,0,1,2> + 3230524963U, // <1,2,5,1>: Cost 4 vmrghw <1,5,0,1>, <2,1,3,5> + 3358213736U, // <1,2,5,2>: Cost 3 vmrglw <0,4,1,5>, <2,2,2,2> + 2284470374U, // <1,2,5,3>: Cost 2 vmrglw <0,4,1,5>, LHS + 4178759604U, // <1,2,5,4>: Cost 4 vsldoi8 <3,0,1,2>, <5,4,5,6> + 4202647556U, // <1,2,5,5>: Cost 3 vsldoi8 <7,0,1,2>, <5,5,5,5> + 4202647650U, // <1,2,5,6>: Cost 3 vsldoi8 <7,0,1,2>, <5,6,7,0> + 4202647722U, // <1,2,5,7>: Cost 4 vsldoi8 <7,0,1,2>, <5,7,6,0> + 2284470379U, // <1,2,5,u>: Cost 2 vmrglw <0,4,1,5>, LHS + 4196675873U, // <1,2,6,0>: Cost 3 vsldoi8 <6,0,1,2>, <6,0,1,2> + 4178760104U, // <1,2,6,1>: Cost 3 vsldoi8 <3,0,1,2>, <6,1,7,2> + 4202648058U, // <1,2,6,2>: Cost 3 vsldoi8 <7,0,1,2>, <6,2,7,3> + 3356893286U, // <1,2,6,3>: Cost 3 vmrglw <0,2,1,6>, LHS + 4033367350U, // <1,2,6,4>: Cost 4 vsldoi4 <1,1,2,6>, RHS + 3231606633U, // <1,2,6,5>: Cost 4 vmrghw <1,6,5,7>, <2,5,3,7> + 4202648376U, // <1,2,6,6>: Cost 3 vsldoi8 <7,0,1,2>, <6,6,6,6> + 4201321304U, // <1,2,6,7>: Cost 3 vsldoi8 <6,7,1,2>, <6,7,1,2> + 3356893291U, // <1,2,6,u>: Cost 3 vmrglw <0,2,1,6>, LHS + 3128906746U, // <1,2,7,0>: Cost 2 vsldoi8 <7,0,1,2>, <7,0,1,2> + 3371500916U, // <1,2,7,1>: Cost 4 vmrglw <2,6,1,7>, <1,u,2,1> + 3365529192U, // <1,2,7,2>: Cost 4 vmrglw <1,6,1,7>, <2,2,2,2> + 3365527654U, // <1,2,7,3>: Cost 3 vmrglw <1,6,1,7>, LHS + 4202648934U, // <1,2,7,4>: Cost 3 vsldoi8 <7,0,1,2>, <7,4,5,6> + 4190705029U, // <1,2,7,5>: Cost 4 vsldoi8 <5,0,1,2>, <7,5,0,1> + 4196677078U, // <1,2,7,6>: Cost 4 vsldoi8 <6,0,1,2>, <7,6,0,1> + 4202649127U, // <1,2,7,7>: Cost 3 vsldoi8 <7,0,1,2>, <7,7,0,1> + 3134215810U, // <1,2,7,u>: Cost 2 vsldoi8 <7,u,1,2>, <7,u,1,2> + 1879924843U, // <1,2,u,0>: Cost 1 vsldoi4 LHS, LHS + 2953667380U, // <1,2,u,1>: Cost 2 vsldoi4 LHS, <1,1,1,1> + 2953668200U, // <1,2,u,2>: Cost 2 vsldoi4 LHS, <2,2,2,2> + 2953668758U, // <1,2,u,3>: Cost 2 vsldoi4 LHS, <3,0,1,2> + 1879928118U, // <1,2,u,4>: Cost 1 vsldoi4 LHS, RHS + 3105020058U, // <1,2,u,5>: Cost 2 vsldoi8 <3,0,1,2>, RHS + 3001446906U, // <1,2,u,6>: Cost 2 vsldoi4 LHS, <6,2,7,3> + 3001447418U, // <1,2,u,7>: Cost 2 vsldoi4 LHS, <7,0,1,2> + 1879930670U, // <1,2,u,u>: Cost 1 vsldoi4 LHS, LHS + 3239151756U, // <1,3,0,0>: Cost 3 vsldoi12 <3,0,0,1>, <3,0,0,1> + 4162175078U, // <1,3,0,1>: Cost 3 vsldoi8 <0,2,1,3>, LHS + 4162175150U, // <1,3,0,2>: Cost 3 vsldoi8 <0,2,1,3>, <0,2,1,3> + 4162838783U, // <1,3,0,3>: Cost 3 vsldoi8 <0,3,1,3>, <0,3,1,3> + 3239446704U, // <1,3,0,4>: Cost 3 vsldoi12 <3,0,4,1>, <3,0,4,1> + 3357507940U, // <1,3,0,5>: Cost 4 vmrglw <0,3,1,0>, <0,4,3,5> + 4162175478U, // <1,3,0,6>: Cost 4 vsldoi8 <0,2,1,3>, <0,6,1,7> + 3357509562U, // <1,3,0,7>: Cost 4 vmrglw <0,3,1,0>, <2,6,3,7> + 4162175645U, // <1,3,0,u>: Cost 3 vsldoi8 <0,2,1,3>, LHS + 3360834454U, // <1,3,1,0>: Cost 3 vmrglw <0,u,1,1>, <1,2,3,0> + 3227945190U, // <1,3,1,1>: Cost 3 vmrghw <1,1,1,1>, <3,1,1,1> + 4168147847U, // <1,3,1,2>: Cost 3 vsldoi8 <1,2,1,3>, <1,2,1,3> + 3360835186U, // <1,3,1,3>: Cost 3 vmrglw <0,u,1,1>, <2,2,3,3> + 3360834458U, // <1,3,1,4>: Cost 3 vmrglw <0,u,1,1>, <1,2,3,4> + 3360835107U, // <1,3,1,5>: Cost 4 vmrglw <0,u,1,1>, <2,1,3,5> + 4162176225U, // <1,3,1,6>: Cost 4 vsldoi8 <0,2,1,3>, <1,6,3,7> + 3360835514U, // <1,3,1,7>: Cost 3 vmrglw <0,u,1,1>, <2,6,3,7> + 3360834462U, // <1,3,1,u>: Cost 3 vmrglw <0,u,1,1>, <1,2,3,u> + 3228747926U, // <1,3,2,0>: Cost 3 vmrghw <1,2,3,0>, <3,0,1,2> + 3228748017U, // <1,3,2,1>: Cost 3 vmrghw <1,2,3,0>, <3,1,2,3> + 4039378464U, // <1,3,2,2>: Cost 3 vsldoi4 <2,1,3,2>, <2,1,3,2> + 4162176678U, // <1,3,2,3>: Cost 3 vsldoi8 <0,2,1,3>, <2,3,0,1> + 3228748290U, // <1,3,2,4>: Cost 3 vmrghw <1,2,3,0>, <3,4,5,6> + 3373449572U, // <1,3,2,5>: Cost 4 vmrglw <3,0,1,2>, <0,4,3,5> + 3228748408U, // <1,3,2,6>: Cost 3 vmrghw <1,2,3,0>, <3,6,0,7> + 3373451194U, // <1,3,2,7>: Cost 3 vmrglw <3,0,1,2>, <2,6,3,7> + 3228748574U, // <1,3,2,u>: Cost 3 vmrghw <1,2,3,0>, <3,u,1,2> + 3241142655U, // <1,3,3,0>: Cost 3 vsldoi12 <3,3,0,1>, <3,3,0,1> + 3356874468U, // <1,3,3,1>: Cost 4 vmrglw <0,2,1,3>, + 4162177352U, // <1,3,3,2>: Cost 4 vsldoi8 <0,2,1,3>, <3,2,3,0> + 3357534620U, // <1,3,3,3>: Cost 3 vmrglw <0,3,1,3>, <3,3,3,3> + 3356869530U, // <1,3,3,4>: Cost 4 vmrglw <0,2,1,3>, <1,2,3,4> + 4057304748U, // <1,3,3,5>: Cost 4 vsldoi4 <5,1,3,3>, <5,1,3,3> + 3229387384U, // <1,3,3,6>: Cost 4 vmrghw <1,3,2,6>, <3,6,0,7> + 3356870586U, // <1,3,3,7>: Cost 4 vmrglw <0,2,1,3>, <2,6,3,7> + 3241732551U, // <1,3,3,u>: Cost 3 vsldoi12 <3,3,u,1>, <3,3,u,1> + 3241806288U, // <1,3,4,0>: Cost 3 vsldoi12 <3,4,0,1>, <3,4,0,1> + 3362186135U, // <1,3,4,1>: Cost 4 vmrglw <1,1,1,4>, <1,2,3,1> + 3230042416U, // <1,3,4,2>: Cost 4 vmrghw <1,4,2,5>, <3,2,0,3> + 3357542002U, // <1,3,4,3>: Cost 4 vmrglw <0,3,1,4>, <2,2,3,3> + 3357540626U, // <1,3,4,4>: Cost 4 vmrglw <0,3,1,4>, <0,3,3,4> + 4162178358U, // <1,3,4,5>: Cost 3 vsldoi8 <0,2,1,3>, RHS + 3357546622U, // <1,3,4,6>: Cost 4 vmrglw <0,3,1,4>, + 3357542330U, // <1,3,4,7>: Cost 4 vmrglw <0,3,1,4>, <2,6,3,7> + 4162178601U, // <1,3,4,u>: Cost 3 vsldoi8 <0,2,1,3>, RHS + 3358213014U, // <1,3,5,0>: Cost 3 vmrglw <0,4,1,5>, <1,2,3,0> + 3358213015U, // <1,3,5,1>: Cost 4 vmrglw <0,4,1,5>, <1,2,3,1> + 4039403043U, // <1,3,5,2>: Cost 3 vsldoi4 <2,1,3,5>, <2,1,3,5> + 3358213746U, // <1,3,5,3>: Cost 3 vmrglw <0,4,1,5>, <2,2,3,3> + 3358213018U, // <1,3,5,4>: Cost 3 vmrglw <0,4,1,5>, <1,2,3,4> + 3358213667U, // <1,3,5,5>: Cost 3 vmrglw <0,4,1,5>, <2,1,3,5> + 3358218366U, // <1,3,5,6>: Cost 4 vmrglw <0,4,1,5>, + 3358214074U, // <1,3,5,7>: Cost 3 vmrglw <0,4,1,5>, <2,6,3,7> + 3358213022U, // <1,3,5,u>: Cost 3 vmrglw <0,4,1,5>, <1,2,3,u> + 3231385750U, // <1,3,6,0>: Cost 3 vmrghw <1,6,2,7>, <3,0,1,2> + 3228756609U, // <1,3,6,1>: Cost 4 vsldoi12 <1,2,3,1>, <3,6,1,7> + 4039411236U, // <1,3,6,2>: Cost 4 vsldoi4 <2,1,3,6>, <2,1,3,6> + 3356894834U, // <1,3,6,3>: Cost 4 vmrglw <0,2,1,6>, <2,2,3,3> + 3356894106U, // <1,3,6,4>: Cost 4 vmrglw <0,2,1,6>, <1,2,3,4> + 3356894755U, // <1,3,6,5>: Cost 5 vmrglw <0,2,1,6>, <2,1,3,5> + 3356899130U, // <1,3,6,6>: Cost 4 vmrglw <0,2,1,6>, + 3356895162U, // <1,3,6,7>: Cost 3 vmrglw <0,2,1,6>, <2,6,3,7> + 3356895162U, // <1,3,6,u>: Cost 3 vmrglw <0,2,1,6>, <2,6,3,7> + 3243797187U, // <1,3,7,0>: Cost 3 vsldoi12 <3,7,0,1>, <3,7,0,1> + 4039419087U, // <1,3,7,1>: Cost 4 vsldoi4 <2,1,3,7>, <1,6,1,7> + 4039419429U, // <1,3,7,2>: Cost 4 vsldoi4 <2,1,3,7>, <2,1,3,7> + 3365529202U, // <1,3,7,3>: Cost 4 vmrglw <1,6,1,7>, <2,2,3,3> + 3365528474U, // <1,3,7,4>: Cost 4 vmrglw <1,6,1,7>, <1,2,3,4> + 4192040343U, // <1,3,7,5>: Cost 4 vsldoi8 <5,2,1,3>, <7,5,2,1> + 3261713151U, // <1,3,7,6>: Cost 4 vsldoi12 <6,7,0,1>, <3,7,6,7> + 3363538874U, // <1,3,7,7>: Cost 4 vmrglw <1,3,1,7>, <2,6,3,7> + 3244387083U, // <1,3,7,u>: Cost 3 vsldoi12 <3,7,u,1>, <3,7,u,1> + 3358237590U, // <1,3,u,0>: Cost 3 vmrglw <0,4,1,u>, <1,2,3,0> + 4162180910U, // <1,3,u,1>: Cost 3 vsldoi8 <0,2,1,3>, LHS + 4039427622U, // <1,3,u,2>: Cost 3 vsldoi4 <2,1,3,u>, <2,1,3,u> + 3356911704U, // <1,3,u,3>: Cost 3 vmrglw <0,2,1,u>, <2,u,3,3> + 3358237594U, // <1,3,u,4>: Cost 3 vmrglw <0,4,1,u>, <1,2,3,4> + 4162181274U, // <1,3,u,5>: Cost 3 vsldoi8 <0,2,1,3>, RHS + 3228748408U, // <1,3,u,6>: Cost 3 vmrghw <1,2,3,0>, <3,6,0,7> + 3358238650U, // <1,3,u,7>: Cost 3 vmrglw <0,4,1,u>, <2,6,3,7> + 4162181477U, // <1,3,u,u>: Cost 3 vsldoi8 <0,2,1,3>, LHS + 4160856077U, // <1,4,0,0>: Cost 3 vsldoi8 <0,0,1,4>, <0,0,1,4> + 4162846822U, // <1,4,0,1>: Cost 3 vsldoi8 <0,3,1,4>, LHS + 4162183343U, // <1,4,0,2>: Cost 4 vsldoi8 <0,2,1,4>, <0,2,1,4> + 4162846976U, // <1,4,0,3>: Cost 3 vsldoi8 <0,3,1,4>, <0,3,1,4> + 4160856402U, // <1,4,0,4>: Cost 3 vsldoi8 <0,0,1,4>, <0,4,1,5> + 3245493138U, // <1,4,0,5>: Cost 2 vsldoi12 <4,0,5,1>, <4,0,5,1> + 4178772470U, // <1,4,0,6>: Cost 4 vsldoi8 <3,0,1,4>, <0,6,1,7> + 4165501508U, // <1,4,0,7>: Cost 3 vsldoi8 <0,7,1,4>, <0,7,1,4> + 3245714349U, // <1,4,0,u>: Cost 2 vsldoi12 <4,0,u,1>, <4,0,u,1> + 3227945874U, // <1,4,1,0>: Cost 3 vmrghw <1,1,1,1>, <4,0,5,1> + 4167492407U, // <1,4,1,1>: Cost 3 vsldoi8 <1,1,1,4>, <1,1,1,4> + 4162847638U, // <1,4,1,2>: Cost 4 vsldoi8 <0,3,1,4>, <1,2,3,0> + 4168819673U, // <1,4,1,3>: Cost 4 vsldoi8 <1,3,1,4>, <1,3,1,4> + 3408612560U, // <1,4,1,4>: Cost 3 vmrglw , <4,4,4,4> + 2154204470U, // <1,4,1,5>: Cost 2 vmrghw <1,1,1,1>, RHS + 4162847978U, // <1,4,1,6>: Cost 4 vsldoi8 <0,3,1,4>, <1,6,4,7> + 3263335412U, // <1,4,1,7>: Cost 4 vsldoi12 <7,0,4,1>, <4,1,7,0> + 2154204713U, // <1,4,1,u>: Cost 2 vmrghw <1,1,1,1>, RHS + 3228748690U, // <1,4,2,0>: Cost 3 vmrghw <1,2,3,0>, <4,0,5,1> + 3228748772U, // <1,4,2,1>: Cost 3 vmrghw <1,2,3,0>, <4,1,5,2> + 4162848360U, // <1,4,2,2>: Cost 4 vsldoi8 <0,3,1,4>, <2,2,2,2> + 4178773670U, // <1,4,2,3>: Cost 3 vsldoi8 <3,0,1,4>, <2,3,0,1> + 3397340368U, // <1,4,2,4>: Cost 3 vmrglw <7,0,1,2>, <4,4,4,4> + 2155007286U, // <1,4,2,5>: Cost 2 vmrghw <1,2,3,0>, RHS + 4162848698U, // <1,4,2,6>: Cost 4 vsldoi8 <0,3,1,4>, <2,6,3,7> + 3373451932U, // <1,4,2,7>: Cost 4 vmrglw <3,0,1,2>, <3,6,4,7> + 2155007529U, // <1,4,2,u>: Cost 2 vmrghw <1,2,3,0>, RHS + 4178774168U, // <1,4,3,0>: Cost 3 vsldoi8 <3,0,1,4>, <3,0,1,4> + 4162849024U, // <1,4,3,1>: Cost 4 vsldoi8 <0,3,1,4>, <3,1,4,0> + 4178774344U, // <1,4,3,2>: Cost 4 vsldoi8 <3,0,1,4>, <3,2,3,0> + 4162849180U, // <1,4,3,3>: Cost 4 vsldoi8 <0,3,1,4>, <3,3,3,3> + 4162849282U, // <1,4,3,4>: Cost 3 vsldoi8 <0,3,1,4>, <3,4,5,6> + 3356870350U, // <1,4,3,5>: Cost 4 vmrglw <0,2,1,3>, <2,3,4,5> + 4202662576U, // <1,4,3,6>: Cost 4 vsldoi8 <7,0,1,4>, <3,6,7,0> + 3366824604U, // <1,4,3,7>: Cost 5 vmrglw <1,u,1,3>, <3,6,4,7> + 4184083232U, // <1,4,3,u>: Cost 3 vsldoi8 <3,u,1,4>, <3,u,1,4> + 3245493416U, // <1,4,4,0>: Cost 3 vsldoi12 <4,0,5,1>, <4,4,0,0> + 3226840242U, // <1,4,4,1>: Cost 4 vsldoi12 <0,u,4,1>, <4,4,1,1> + 4027524774U, // <1,4,4,2>: Cost 4 vsldoi4 <0,1,4,4>, <2,3,0,1> + 3357541282U, // <1,4,4,3>: Cost 4 vmrglw <0,3,1,4>, <1,2,4,3> + 3250801872U, // <1,4,4,4>: Cost 3 vsldoi12 <4,u,5,1>, <4,4,4,4> + 4162850102U, // <1,4,4,5>: Cost 3 vsldoi8 <0,3,1,4>, RHS + 3357541528U, // <1,4,4,6>: Cost 4 vmrglw <0,3,1,4>, <1,5,4,6> + 4213280204U, // <1,4,4,7>: Cost 4 vsldoi8 , <4,7,5,4> + 4162850345U, // <1,4,4,u>: Cost 3 vsldoi8 <0,3,1,4>, RHS + 4033503334U, // <1,4,5,0>: Cost 3 vsldoi4 <1,1,4,5>, LHS + 3358212133U, // <1,4,5,1>: Cost 3 vmrglw <0,4,1,5>, <0,0,4,1> + 4027532966U, // <1,4,5,2>: Cost 3 vsldoi4 <0,1,4,5>, <2,3,0,1> + 3358212297U, // <1,4,5,3>: Cost 4 vmrglw <0,4,1,5>, <0,2,4,3> + 3358212136U, // <1,4,5,4>: Cost 3 vmrglw <0,4,1,5>, <0,0,4,4> + 3358212461U, // <1,4,5,5>: Cost 3 vmrglw <0,4,1,5>, <0,4,4,5> + 3226619190U, // <1,4,5,6>: Cost 2 vsldoi12 <0,u,1,1>, RHS + 4057396218U, // <1,4,5,7>: Cost 4 vsldoi4 <5,1,4,5>, <7,0,1,2> + 3226619208U, // <1,4,5,u>: Cost 2 vsldoi12 <0,u,1,1>, RHS + 4196692259U, // <1,4,6,0>: Cost 4 vsldoi8 <6,0,1,4>, <6,0,1,4> + 3226840410U, // <1,4,6,1>: Cost 4 vsldoi12 <0,u,4,1>, <4,6,1,7> + 4202664442U, // <1,4,6,2>: Cost 4 vsldoi8 <7,0,1,4>, <6,2,7,3> + 4210627122U, // <1,4,6,3>: Cost 4 vsldoi8 , <6,3,4,5> + 3231608016U, // <1,4,6,4>: Cost 4 vmrghw <1,6,5,7>, <4,4,4,4> + 3231313206U, // <1,4,6,5>: Cost 3 vmrghw <1,6,1,7>, RHS + 4202664760U, // <1,4,6,6>: Cost 4 vsldoi8 <7,0,1,4>, <6,6,6,6> + 4202664782U, // <1,4,6,7>: Cost 3 vsldoi8 <7,0,1,4>, <6,7,0,1> + 3231313449U, // <1,4,6,u>: Cost 3 vmrghw <1,6,1,7>, RHS + 4202664956U, // <1,4,7,0>: Cost 3 vsldoi8 <7,0,1,4>, <7,0,1,4> + 3383444141U, // <1,4,7,1>: Cost 4 vmrglw <4,6,1,7>, <0,u,4,1> + 4208637145U, // <1,4,7,2>: Cost 4 vsldoi8 , <7,2,u,0> + 4210627851U, // <1,4,7,3>: Cost 4 vsldoi8 , <7,3,4,5> + 4213282150U, // <1,4,7,4>: Cost 3 vsldoi8 , <7,4,5,6> + 3365528403U, // <1,4,7,5>: Cost 4 vmrglw <1,6,1,7>, <1,1,4,5> + 4202665492U, // <1,4,7,6>: Cost 4 vsldoi8 <7,0,1,4>, <7,6,7,0> + 4202665580U, // <1,4,7,7>: Cost 4 vsldoi8 <7,0,1,4>, <7,7,7,7> + 4207974020U, // <1,4,7,u>: Cost 3 vsldoi8 <7,u,1,4>, <7,u,1,4> + 4033527910U, // <1,4,u,0>: Cost 3 vsldoi4 <1,1,4,u>, LHS + 4162852654U, // <1,4,u,1>: Cost 3 vsldoi8 <0,3,1,4>, LHS + 4027557542U, // <1,4,u,2>: Cost 3 vsldoi4 <0,1,4,u>, <2,3,0,1> + 4210628552U, // <1,4,u,3>: Cost 3 vsldoi8 , + 4166170687U, // <1,4,u,4>: Cost 3 vsldoi8 <0,u,1,4>, + 2158988598U, // <1,4,u,5>: Cost 2 vmrghw <1,u,3,0>, RHS + 3226619433U, // <1,4,u,6>: Cost 2 vsldoi12 <0,u,1,1>, RHS + 4213283084U, // <1,4,u,7>: Cost 3 vsldoi8 , + 3226619451U, // <1,4,u,u>: Cost 2 vsldoi12 <0,u,1,1>, RHS + 4163518464U, // <1,5,0,0>: Cost 3 vsldoi8 <0,4,1,5>, <0,0,0,0> + 3089776742U, // <1,5,0,1>: Cost 2 vsldoi8 <0,4,1,5>, LHS + 4162191536U, // <1,5,0,2>: Cost 4 vsldoi8 <0,2,1,5>, <0,2,1,5> + 4163518716U, // <1,5,0,3>: Cost 4 vsldoi8 <0,4,1,5>, <0,3,1,0> + 3089776978U, // <1,5,0,4>: Cost 2 vsldoi8 <0,4,1,5>, <0,4,1,5> + 4164182435U, // <1,5,0,5>: Cost 3 vsldoi8 <0,5,1,5>, <0,5,1,5> + 3251539572U, // <1,5,0,6>: Cost 3 vsldoi12 <5,0,6,1>, <5,0,6,1> + 4069373037U, // <1,5,0,7>: Cost 4 vsldoi4 <7,1,5,0>, <7,1,5,0> + 3089777309U, // <1,5,0,u>: Cost 2 vsldoi8 <0,4,1,5>, LHS + 3250802319U, // <1,5,1,0>: Cost 3 vsldoi12 <4,u,5,1>, <5,1,0,1> + 4163519284U, // <1,5,1,1>: Cost 3 vsldoi8 <0,4,1,5>, <1,1,1,1> + 4163519382U, // <1,5,1,2>: Cost 3 vsldoi8 <0,4,1,5>, <1,2,3,0> + 4163519481U, // <1,5,1,3>: Cost 4 vsldoi8 <0,4,1,5>, <1,3,5,0> + 4169491499U, // <1,5,1,4>: Cost 3 vsldoi8 <1,4,1,5>, <1,4,1,5> + 4163519599U, // <1,5,1,5>: Cost 3 vsldoi8 <0,4,1,5>, <1,5,0,1> + 4163519731U, // <1,5,1,6>: Cost 3 vsldoi8 <0,4,1,5>, <1,6,5,7> + 3360834803U, // <1,5,1,7>: Cost 4 vmrglw <0,u,1,1>, <1,6,5,7> + 4163519868U, // <1,5,1,u>: Cost 3 vsldoi8 <0,4,1,5>, <1,u,3,0> + 3397340616U, // <1,5,2,0>: Cost 3 vmrglw <7,0,1,2>, <4,7,5,0> + 4163520035U, // <1,5,2,1>: Cost 3 vsldoi8 <0,4,1,5>, <2,1,3,5> + 4163520104U, // <1,5,2,2>: Cost 3 vsldoi8 <0,4,1,5>, <2,2,2,2> + 4163520166U, // <1,5,2,3>: Cost 3 vsldoi8 <0,4,1,5>, <2,3,0,1> + 4051471332U, // <1,5,2,4>: Cost 3 vsldoi4 <4,1,5,2>, <4,1,5,2> + 3397340378U, // <1,5,2,5>: Cost 3 vmrglw <7,0,1,2>, <4,4,5,5> + 4163520442U, // <1,5,2,6>: Cost 3 vsldoi8 <0,4,1,5>, <2,6,3,7> + 3373450483U, // <1,5,2,7>: Cost 4 vmrglw <3,0,1,2>, <1,6,5,7> + 4163520571U, // <1,5,2,u>: Cost 3 vsldoi8 <0,4,1,5>, <2,u,0,1> + 4163520662U, // <1,5,3,0>: Cost 3 vsldoi8 <0,4,1,5>, <3,0,1,2> + 3386732058U, // <1,5,3,1>: Cost 3 vmrglw <5,2,1,3>, <4,u,5,1> + 4163520833U, // <1,5,3,2>: Cost 4 vsldoi8 <0,4,1,5>, <3,2,2,2> + 4163520924U, // <1,5,3,3>: Cost 3 vsldoi8 <0,4,1,5>, <3,3,3,3> + 4163521026U, // <1,5,3,4>: Cost 3 vsldoi8 <0,4,1,5>, <3,4,5,6> + 3386731738U, // <1,5,3,5>: Cost 4 vmrglw <5,2,1,3>, <4,4,5,5> + 3356871170U, // <1,5,3,6>: Cost 4 vmrglw <0,2,1,3>, <3,4,5,6> + 4211296963U, // <1,5,3,7>: Cost 4 vsldoi8 , <3,7,0,1> + 4163521310U, // <1,5,3,u>: Cost 3 vsldoi8 <0,4,1,5>, <3,u,1,2> + 4051484774U, // <1,5,4,0>: Cost 3 vsldoi4 <4,1,5,4>, LHS + 4163521506U, // <1,5,4,1>: Cost 3 vsldoi8 <0,4,1,5>, <4,1,5,0> + 4051486243U, // <1,5,4,2>: Cost 4 vsldoi4 <4,1,5,4>, <2,1,3,5> + 4045515021U, // <1,5,4,3>: Cost 4 vsldoi4 <3,1,5,4>, <3,1,5,4> + 4163521744U, // <1,5,4,4>: Cost 3 vsldoi8 <0,4,1,5>, <4,4,4,4> + 3089780022U, // <1,5,4,5>: Cost 2 vsldoi8 <0,4,1,5>, RHS + 3357542914U, // <1,5,4,6>: Cost 3 vmrglw <0,3,1,4>, <3,4,5,6> + 4069405809U, // <1,5,4,7>: Cost 4 vsldoi4 <7,1,5,4>, <7,1,5,4> + 3089780265U, // <1,5,4,u>: Cost 2 vsldoi8 <0,4,1,5>, RHS + 4033577062U, // <1,5,5,0>: Cost 3 vsldoi4 <1,1,5,5>, LHS + 4033577820U, // <1,5,5,1>: Cost 3 vsldoi4 <1,1,5,5>, <1,1,5,5> + 4033578531U, // <1,5,5,2>: Cost 4 vsldoi4 <1,1,5,5>, <2,1,3,5> + 3358213035U, // <1,5,5,3>: Cost 3 vmrglw <0,4,1,5>, <1,2,5,3> + 4033580342U, // <1,5,5,4>: Cost 3 vsldoi4 <1,1,5,5>, RHS + 3358212956U, // <1,5,5,5>: Cost 3 vmrglw <0,4,1,5>, <1,1,5,5> + 3358214658U, // <1,5,5,6>: Cost 3 vmrglw <0,4,1,5>, <3,4,5,6> + 3358213363U, // <1,5,5,7>: Cost 3 vmrglw <0,4,1,5>, <1,6,5,7> + 3358213040U, // <1,5,5,u>: Cost 3 vmrglw <0,4,1,5>, <1,2,5,u> + 3255078948U, // <1,5,6,0>: Cost 3 vsldoi12 <5,6,0,1>, <5,6,0,1> + 3250802739U, // <1,5,6,1>: Cost 3 vsldoi12 <4,u,5,1>, <5,6,1,7> + 4211298810U, // <1,5,6,2>: Cost 3 vsldoi8 , <6,2,7,3> + 3244757058U, // <1,5,6,3>: Cost 4 vsldoi12 <3,u,4,1>, <5,6,3,4> + 3231608756U, // <1,5,6,4>: Cost 4 vmrghw <1,6,5,7>, <5,4,5,6> + 3231608836U, // <1,5,6,5>: Cost 4 vmrghw <1,6,5,7>, <5,5,5,5> + 4211299128U, // <1,5,6,6>: Cost 3 vsldoi8 , <6,6,6,6> + 3250802786U, // <1,5,6,7>: Cost 3 vsldoi12 <4,u,5,1>, <5,6,7,0> + 3250802795U, // <1,5,6,u>: Cost 3 vsldoi12 <4,u,5,1>, <5,6,u,0> + 4211299322U, // <1,5,7,0>: Cost 3 vsldoi8 , <7,0,1,2> + 3389419034U, // <1,5,7,1>: Cost 3 vmrglw <5,6,1,7>, <4,u,5,1> + 4211299476U, // <1,5,7,2>: Cost 4 vsldoi8 , <7,2,0,3> + 4211299555U, // <1,5,7,3>: Cost 4 vsldoi8 , <7,3,0,1> + 4211299686U, // <1,5,7,4>: Cost 3 vsldoi8 , <7,4,5,6> + 3389418714U, // <1,5,7,5>: Cost 4 vmrglw <5,6,1,7>, <4,4,5,5> + 3365528656U, // <1,5,7,6>: Cost 4 vmrglw <1,6,1,7>, <1,4,5,6> + 4211299948U, // <1,5,7,7>: Cost 3 vsldoi8 , <7,7,7,7> + 4211299970U, // <1,5,7,u>: Cost 3 vsldoi8 , <7,u,1,2> + 4163524307U, // <1,5,u,0>: Cost 3 vsldoi8 <0,4,1,5>, + 3089782574U, // <1,5,u,1>: Cost 2 vsldoi8 <0,4,1,5>, LHS + 4163524488U, // <1,5,u,2>: Cost 3 vsldoi8 <0,4,1,5>, + 4163524540U, // <1,5,u,3>: Cost 3 vsldoi8 <0,4,1,5>, + 3137558554U, // <1,5,u,4>: Cost 2 vsldoi8 , + 3089782938U, // <1,5,u,5>: Cost 2 vsldoi8 <0,4,1,5>, RHS + 4163524816U, // <1,5,u,6>: Cost 3 vsldoi8 <0,4,1,5>, + 3250802948U, // <1,5,u,7>: Cost 3 vsldoi12 <4,u,5,1>, <5,u,7,0> + 3089783141U, // <1,5,u,u>: Cost 2 vsldoi8 <0,4,1,5>, LHS + 4162199552U, // <1,6,0,0>: Cost 4 vsldoi8 <0,2,1,6>, <0,0,0,0> + 4162199654U, // <1,6,0,1>: Cost 3 vsldoi8 <0,2,1,6>, LHS + 4162199729U, // <1,6,0,2>: Cost 3 vsldoi8 <0,2,1,6>, <0,2,1,6> + 3257291058U, // <1,6,0,3>: Cost 4 vsldoi12 <6,0,3,1>, <6,0,3,1> + 4162199890U, // <1,6,0,4>: Cost 4 vsldoi8 <0,2,1,6>, <0,4,1,5> + 4164190628U, // <1,6,0,5>: Cost 3 vsldoi8 <0,5,1,6>, <0,5,1,6> + 4164854261U, // <1,6,0,6>: Cost 3 vsldoi8 <0,6,1,6>, <0,6,1,6> + 3357510966U, // <1,6,0,7>: Cost 3 vmrglw <0,3,1,0>, RHS + 4162200221U, // <1,6,0,u>: Cost 3 vsldoi8 <0,2,1,6>, LHS + 4033618022U, // <1,6,1,0>: Cost 4 vsldoi4 <1,1,6,1>, LHS + 4162200372U, // <1,6,1,1>: Cost 4 vsldoi8 <0,2,1,6>, <1,1,1,1> + 3227947514U, // <1,6,1,2>: Cost 3 vmrghw <1,1,1,1>, <6,2,7,3> + 4162200585U, // <1,6,1,3>: Cost 4 vsldoi8 <0,2,1,6>, <1,3,6,7> + 4033621302U, // <1,6,1,4>: Cost 4 vsldoi4 <1,1,6,1>, RHS + 4170163325U, // <1,6,1,5>: Cost 4 vsldoi8 <1,5,1,6>, <1,5,1,6> + 3408614200U, // <1,6,1,6>: Cost 3 vmrglw , <6,6,6,6> + 2287095094U, // <1,6,1,7>: Cost 2 vmrglw <0,u,1,1>, RHS + 2287095095U, // <1,6,1,u>: Cost 2 vmrglw <0,u,1,1>, RHS + 4039598182U, // <1,6,2,0>: Cost 4 vsldoi4 <2,1,6,2>, LHS + 4162201145U, // <1,6,2,1>: Cost 4 vsldoi8 <0,2,1,6>, <2,1,6,0> + 3228750330U, // <1,6,2,2>: Cost 3 vmrghw <1,2,3,0>, <6,2,7,3> + 4162201254U, // <1,6,2,3>: Cost 4 vsldoi8 <0,2,1,6>, <2,3,0,1> + 4039601462U, // <1,6,2,4>: Cost 4 vsldoi4 <2,1,6,2>, RHS + 3373451057U, // <1,6,2,5>: Cost 4 vmrglw <3,0,1,2>, <2,4,6,5> + 4162201530U, // <1,6,2,6>: Cost 3 vsldoi8 <0,2,1,6>, <2,6,3,7> + 2299710774U, // <1,6,2,7>: Cost 2 vmrglw <3,0,1,2>, RHS + 2299710775U, // <1,6,2,u>: Cost 2 vmrglw <3,0,1,2>, RHS + 4162201750U, // <1,6,3,0>: Cost 4 vsldoi8 <0,2,1,6>, <3,0,1,2> + 3238933017U, // <1,6,3,1>: Cost 4 vsldoi12 <2,u,6,1>, <6,3,1,7> + 4162201958U, // <1,6,3,2>: Cost 4 vsldoi8 <0,2,1,6>, <3,2,6,3> + 4162202012U, // <1,6,3,3>: Cost 4 vsldoi8 <0,2,1,6>, <3,3,3,3> + 4162202114U, // <1,6,3,4>: Cost 4 vsldoi8 <0,2,1,6>, <3,4,5,6> + 4211968605U, // <1,6,3,5>: Cost 4 vsldoi8 , <3,5,6,7> + 3386733368U, // <1,6,3,6>: Cost 4 vmrglw <5,2,1,3>, <6,6,6,6> + 3356871990U, // <1,6,3,7>: Cost 3 vmrglw <0,2,1,3>, RHS + 3356871991U, // <1,6,3,u>: Cost 3 vmrglw <0,2,1,3>, RHS + 4039614566U, // <1,6,4,0>: Cost 4 vsldoi4 <2,1,6,4>, LHS + 3258249832U, // <1,6,4,1>: Cost 4 vsldoi12 <6,1,7,1>, <6,4,1,5> + 4039616061U, // <1,6,4,2>: Cost 4 vsldoi4 <2,1,6,4>, <2,1,6,4> + 4057532930U, // <1,6,4,3>: Cost 4 vsldoi4 <5,1,6,4>, <3,4,5,6> + 4039617846U, // <1,6,4,4>: Cost 4 vsldoi4 <2,1,6,4>, RHS + 4162202934U, // <1,6,4,5>: Cost 3 vsldoi8 <0,2,1,6>, RHS + 3261641365U, // <1,6,4,6>: Cost 4 vsldoi12 <6,6,u,1>, <6,4,6,5> + 3357543734U, // <1,6,4,7>: Cost 3 vmrglw <0,3,1,4>, RHS + 4162203177U, // <1,6,4,u>: Cost 3 vsldoi8 <0,2,1,6>, RHS + 4045594726U, // <1,6,5,0>: Cost 4 vsldoi4 <3,1,6,5>, LHS + 4045595891U, // <1,6,5,1>: Cost 4 vsldoi4 <3,1,6,5>, <1,6,5,7> + 3405989597U, // <1,6,5,2>: Cost 4 vmrglw , <2,3,6,2> + 3358214502U, // <1,6,5,3>: Cost 4 vmrglw <0,4,1,5>, <3,2,6,3> + 4045598006U, // <1,6,5,4>: Cost 4 vsldoi4 <3,1,6,5>, RHS + 4057542345U, // <1,6,5,5>: Cost 4 vsldoi4 <5,1,6,5>, <5,1,6,5> + 3405992760U, // <1,6,5,6>: Cost 3 vmrglw , <6,6,6,6> + 2284473654U, // <1,6,5,7>: Cost 2 vmrglw <0,4,1,5>, RHS + 2284473655U, // <1,6,5,u>: Cost 2 vmrglw <0,4,1,5>, RHS + 3261051645U, // <1,6,6,0>: Cost 3 vsldoi12 <6,6,0,1>, <6,6,0,1> + 4033659750U, // <1,6,6,1>: Cost 4 vsldoi4 <1,1,6,6>, <1,1,6,6> + 4033660858U, // <1,6,6,2>: Cost 4 vsldoi4 <1,1,6,6>, <2,6,3,7> + 3356894132U, // <1,6,6,3>: Cost 4 vmrglw <0,2,1,6>, <1,2,6,3> + 4033662262U, // <1,6,6,4>: Cost 4 vsldoi4 <1,1,6,6>, RHS + 4057550538U, // <1,6,6,5>: Cost 4 vsldoi4 <5,1,6,6>, <5,1,6,6> + 3250803512U, // <1,6,6,6>: Cost 3 vsldoi12 <4,u,5,1>, <6,6,6,6> + 3356896566U, // <1,6,6,7>: Cost 3 vmrglw <0,2,1,6>, RHS + 3356896567U, // <1,6,6,u>: Cost 3 vmrglw <0,2,1,6>, RHS + 3261715278U, // <1,6,7,0>: Cost 2 vsldoi12 <6,7,0,1>, <6,7,0,1> + 3261789015U, // <1,6,7,1>: Cost 3 vsldoi12 <6,7,1,1>, <6,7,1,1> + 3235173218U, // <1,6,7,2>: Cost 3 vsldoi12 <2,3,0,1>, <6,7,2,3> + 3250803560U, // <1,6,7,3>: Cost 4 vsldoi12 <4,u,5,1>, <6,7,3,0> + 3250803574U, // <1,6,7,4>: Cost 3 vsldoi12 <4,u,5,1>, <6,7,4,5> + 3365528664U, // <1,6,7,5>: Cost 4 vmrglw <1,6,1,7>, <1,4,6,5> + 3261715338U, // <1,6,7,6>: Cost 3 vsldoi12 <6,7,0,1>, <6,7,6,7> + 3365530934U, // <1,6,7,7>: Cost 3 vmrglw <1,6,1,7>, RHS + 3262305174U, // <1,6,7,u>: Cost 2 vsldoi12 <6,7,u,1>, <6,7,u,1> + 3262378911U, // <1,6,u,0>: Cost 2 vsldoi12 <6,u,0,1>, <6,u,0,1> + 4162205486U, // <1,6,u,1>: Cost 3 vsldoi8 <0,2,1,6>, LHS + 3262526385U, // <1,6,u,2>: Cost 3 vsldoi12 <6,u,2,1>, <6,u,2,1> + 4162205628U, // <1,6,u,3>: Cost 4 vsldoi8 <0,2,1,6>, + 3250803655U, // <1,6,u,4>: Cost 3 vsldoi12 <4,u,5,1>, <6,u,4,5> + 4162205850U, // <1,6,u,5>: Cost 3 vsldoi8 <0,2,1,6>, RHS + 4166187216U, // <1,6,u,6>: Cost 3 vsldoi8 <0,u,1,6>, + 2284498230U, // <1,6,u,7>: Cost 2 vmrglw <0,4,1,u>, RHS + 2284498231U, // <1,6,u,u>: Cost 2 vmrglw <0,4,1,u>, RHS + 3263042544U, // <1,7,0,0>: Cost 3 vsldoi12 <7,0,0,1>, <7,0,0,1> + 4170834022U, // <1,7,0,1>: Cost 3 vsldoi8 <1,6,1,7>, LHS + 3393343912U, // <1,7,0,2>: Cost 4 vmrglw <6,3,1,0>, <6,1,7,2> + 3397325306U, // <1,7,0,3>: Cost 4 vmrglw <7,0,1,0>, <6,2,7,3> + 3263337492U, // <1,7,0,4>: Cost 3 vsldoi12 <7,0,4,1>, <7,0,4,1> + 4057575117U, // <1,7,0,5>: Cost 4 vsldoi4 <5,1,7,0>, <5,1,7,0> + 4164862454U, // <1,7,0,6>: Cost 3 vsldoi8 <0,6,1,7>, <0,6,1,7> + 4165526087U, // <1,7,0,7>: Cost 3 vsldoi8 <0,7,1,7>, <0,7,1,7> + 4170834578U, // <1,7,0,u>: Cost 3 vsldoi8 <1,6,1,7>, <0,u,1,1> + 4063551498U, // <1,7,1,0>: Cost 3 vsldoi4 <6,1,7,1>, <0,0,1,1> + 3263779914U, // <1,7,1,1>: Cost 3 vsldoi12 <7,1,1,1>, <7,1,1,1> + 4170834823U, // <1,7,1,2>: Cost 4 vsldoi8 <1,6,1,7>, <1,2,1,3> + 3408613882U, // <1,7,1,3>: Cost 3 vmrglw , <6,2,7,3> + 4063554870U, // <1,7,1,4>: Cost 3 vsldoi4 <6,1,7,1>, RHS + 4194722981U, // <1,7,1,5>: Cost 4 vsldoi8 <5,6,1,7>, <1,5,6,1> + 4170835151U, // <1,7,1,6>: Cost 3 vsldoi8 <1,6,1,7>, <1,6,1,7> + 3408614210U, // <1,7,1,7>: Cost 3 vmrglw , <6,6,7,7> + 4172162417U, // <1,7,1,u>: Cost 3 vsldoi8 <1,u,1,7>, <1,u,1,7> + 4063559782U, // <1,7,2,0>: Cost 3 vsldoi4 <6,1,7,2>, LHS + 3228750933U, // <1,7,2,1>: Cost 3 vmrghw <1,2,3,0>, <7,1,2,3> + 3373453736U, // <1,7,2,2>: Cost 3 vmrglw <3,0,1,2>, <6,1,7,2> + 4063561878U, // <1,7,2,3>: Cost 3 vsldoi4 <6,1,7,2>, <3,0,1,2> + 4063563062U, // <1,7,2,4>: Cost 3 vsldoi4 <6,1,7,2>, RHS + 3385397675U, // <1,7,2,5>: Cost 4 vmrglw <5,0,1,2>, <6,1,7,5> + 4063564200U, // <1,7,2,6>: Cost 3 vsldoi4 <6,1,7,2>, <6,1,7,2> + 3397341451U, // <1,7,2,7>: Cost 3 vmrglw <7,0,1,2>, <5,u,7,7> + 4063565614U, // <1,7,2,u>: Cost 3 vsldoi4 <6,1,7,2>, LHS + 3265033443U, // <1,7,3,0>: Cost 3 vsldoi12 <7,3,0,1>, <7,3,0,1> + 4170836243U, // <1,7,3,1>: Cost 4 vsldoi8 <1,6,1,7>, <3,1,6,1> + 4063569574U, // <1,7,3,2>: Cost 4 vsldoi4 <6,1,7,3>, <2,3,0,1> + 4170836380U, // <1,7,3,3>: Cost 4 vsldoi8 <1,6,1,7>, <3,3,3,3> + 4170836482U, // <1,7,3,4>: Cost 4 vsldoi8 <1,6,1,7>, <3,4,5,6> + 4194724439U, // <1,7,3,5>: Cost 4 vsldoi8 <5,6,1,7>, <3,5,6,1> + 4182780545U, // <1,7,3,6>: Cost 4 vsldoi8 <3,6,1,7>, <3,6,1,7> + 3243799841U, // <1,7,3,7>: Cost 4 vsldoi12 <3,7,0,1>, <7,3,7,0> + 3265623339U, // <1,7,3,u>: Cost 3 vsldoi12 <7,3,u,1>, <7,3,u,1> + 3265697076U, // <1,7,4,0>: Cost 3 vsldoi12 <7,4,0,1>, <7,4,0,1> + 4063577295U, // <1,7,4,1>: Cost 4 vsldoi4 <6,1,7,4>, <1,6,1,7> + 3235173704U, // <1,7,4,2>: Cost 4 vsldoi12 <2,3,0,1>, <7,4,2,3> + 3397358074U, // <1,7,4,3>: Cost 4 vmrglw <7,0,1,4>, <6,2,7,3> + 3250804059U, // <1,7,4,4>: Cost 4 vsldoi12 <4,u,5,1>, <7,4,4,4> + 4170837302U, // <1,7,4,5>: Cost 3 vsldoi8 <1,6,1,7>, RHS + 4188753242U, // <1,7,4,6>: Cost 4 vsldoi8 <4,6,1,7>, <4,6,1,7> + 4057609574U, // <1,7,4,7>: Cost 4 vsldoi4 <5,1,7,4>, <7,4,5,6> + 4170837545U, // <1,7,4,u>: Cost 3 vsldoi8 <1,6,1,7>, RHS + 4063584358U, // <1,7,5,0>: Cost 3 vsldoi4 <6,1,7,5>, LHS + 3250804117U, // <1,7,5,1>: Cost 4 vsldoi12 <4,u,5,1>, <7,5,1,u> + 4045670330U, // <1,7,5,2>: Cost 4 vsldoi4 <3,1,7,5>, <2,6,3,7> + 3405992442U, // <1,7,5,3>: Cost 3 vmrglw , <6,2,7,3> + 4063587638U, // <1,7,5,4>: Cost 3 vsldoi4 <6,1,7,5>, RHS + 3358216619U, // <1,7,5,5>: Cost 3 vmrglw <0,4,1,5>, <6,1,7,5> + 4194725939U, // <1,7,5,6>: Cost 3 vsldoi8 <5,6,1,7>, <5,6,1,7> + 3405992770U, // <1,7,5,7>: Cost 3 vmrglw , <6,6,7,7> + 4196053205U, // <1,7,5,u>: Cost 3 vsldoi8 <5,u,1,7>, <5,u,1,7> + 3406663778U, // <1,7,6,0>: Cost 3 vmrglw , <5,6,7,0> + 4170838438U, // <1,7,6,1>: Cost 4 vsldoi8 <1,6,1,7>, <6,1,7,0> + 4045678522U, // <1,7,6,2>: Cost 4 vsldoi4 <3,1,7,6>, <2,6,3,7> + 4045678881U, // <1,7,6,3>: Cost 4 vsldoi4 <3,1,7,6>, <3,1,7,6> + 4045679926U, // <1,7,6,4>: Cost 4 vsldoi4 <3,1,7,6>, RHS + 3260904969U, // <1,7,6,5>: Cost 4 vsldoi12 <6,5,7,1>, <7,6,5,7> + 3250804241U, // <1,7,6,6>: Cost 4 vsldoi12 <4,u,5,1>, <7,6,6,6> + 3261715988U, // <1,7,6,7>: Cost 3 vsldoi12 <6,7,0,1>, <7,6,7,0> + 3262379549U, // <1,7,6,u>: Cost 3 vsldoi12 <6,u,0,1>, <7,6,u,0> + 3267687975U, // <1,7,7,0>: Cost 3 vsldoi12 <7,7,0,1>, <7,7,0,1> + 3365528426U, // <1,7,7,1>: Cost 4 vmrglw <1,6,1,7>, <1,1,7,1> + 4063602342U, // <1,7,7,2>: Cost 4 vsldoi4 <6,1,7,7>, <2,3,0,1> + 3365528509U, // <1,7,7,3>: Cost 4 vmrglw <1,6,1,7>, <1,2,7,3> + 3250804303U, // <1,7,7,4>: Cost 4 vsldoi12 <4,u,5,1>, <7,7,4,5> + 4057632468U, // <1,7,7,5>: Cost 4 vsldoi4 <5,1,7,7>, <5,1,7,7> + 4063605165U, // <1,7,7,6>: Cost 4 vsldoi4 <6,1,7,7>, <6,1,7,7> + 3250804332U, // <1,7,7,7>: Cost 3 vsldoi12 <4,u,5,1>, <7,7,7,7> + 3268277871U, // <1,7,7,u>: Cost 3 vsldoi12 <7,7,u,1>, <7,7,u,1> + 4063608849U, // <1,7,u,0>: Cost 3 vsldoi4 <6,1,7,u>, <0,0,1,u> + 4170839854U, // <1,7,u,1>: Cost 3 vsldoi8 <1,6,1,7>, LHS + 3373453736U, // <1,7,u,2>: Cost 3 vmrglw <3,0,1,2>, <6,1,7,2> + 3397390842U, // <1,7,u,3>: Cost 3 vmrglw <7,0,1,u>, <6,2,7,3> + 4063612214U, // <1,7,u,4>: Cost 3 vsldoi4 <6,1,7,u>, RHS + 4170840218U, // <1,7,u,5>: Cost 3 vsldoi8 <1,6,1,7>, RHS + 4063613358U, // <1,7,u,6>: Cost 3 vsldoi4 <6,1,7,u>, <6,1,7,u> + 3397391170U, // <1,7,u,7>: Cost 3 vmrglw <7,0,1,u>, <6,6,7,7> + 4170840421U, // <1,7,u,u>: Cost 3 vsldoi8 <1,6,1,7>, LHS + 3087147025U, // <1,u,0,0>: Cost 2 vsldoi8 <0,0,1,u>, <0,0,1,u> + 3089801318U, // <1,u,0,1>: Cost 2 vsldoi8 <0,4,1,u>, LHS + 4162216115U, // <1,u,0,2>: Cost 3 vsldoi8 <0,2,1,u>, <0,2,1,u> + 3357507740U, // <1,u,0,3>: Cost 3 vmrglw <0,3,1,0>, LHS + 3089801557U, // <1,u,0,4>: Cost 2 vsldoi8 <0,4,1,u>, <0,4,1,u> + 3269383926U, // <1,u,0,5>: Cost 2 vsldoi12 , + 4164870647U, // <1,u,0,6>: Cost 3 vsldoi8 <0,6,1,u>, <0,6,1,u> + 3357510984U, // <1,u,0,7>: Cost 3 vmrglw <0,3,1,0>, RHS + 3089801885U, // <1,u,0,u>: Cost 2 vsldoi8 <0,4,1,u>, LHS + 2959507558U, // <1,u,1,0>: Cost 2 vsldoi4 <1,1,1,1>, LHS + 1477230694U, // <1,u,1,1>: Cost 1 vspltisw1 LHS + 3226621742U, // <1,u,1,2>: Cost 2 vsldoi12 <0,u,1,1>, LHS + 2287091868U, // <1,u,1,3>: Cost 2 vmrglw <0,u,1,1>, LHS + 2959510838U, // <1,u,1,4>: Cost 2 vsldoi4 <1,1,1,1>, RHS + 2154207386U, // <1,u,1,5>: Cost 2 vmrghw <1,1,1,1>, RHS + 4163544334U, // <1,u,1,6>: Cost 3 vsldoi8 <0,4,1,u>, <1,6,u,7> + 2287095112U, // <1,u,1,7>: Cost 2 vmrglw <0,u,1,1>, RHS + 1477230694U, // <1,u,1,u>: Cost 1 vspltisw1 LHS + 3228751571U, // <1,u,2,0>: Cost 3 vmrghw <1,2,3,0>, + 2155009838U, // <1,u,2,1>: Cost 2 vmrghw <1,2,3,0>, LHS + 2155004822U, // <1,u,2,2>: Cost 2 vmrghw <1,2,3,0>, <1,2,3,0> + 2299707548U, // <1,u,2,3>: Cost 2 vmrglw <3,0,1,2>, LHS + 3228751935U, // <1,u,2,4>: Cost 3 vmrghw <1,2,3,0>, + 2155010202U, // <1,u,2,5>: Cost 2 vmrghw <1,2,3,0>, RHS + 4163545018U, // <1,u,2,6>: Cost 3 vsldoi8 <0,4,1,u>, <2,6,3,7> + 2299710792U, // <1,u,2,7>: Cost 2 vmrglw <3,0,1,2>, RHS + 2155010405U, // <1,u,2,u>: Cost 2 vmrghw <1,2,3,0>, LHS + 1880326300U, // <1,u,3,0>: Cost 1 vsldoi4 LHS, LHS + 2954068788U, // <1,u,3,1>: Cost 2 vsldoi4 LHS, <1,1,1,1> + 2954069608U, // <1,u,3,2>: Cost 2 vsldoi4 LHS, <2,2,2,2> + 2954070166U, // <1,u,3,3>: Cost 2 vsldoi4 LHS, <3,0,1,2> + 1880329526U, // <1,u,3,4>: Cost 1 vsldoi4 LHS, RHS + 3001847812U, // <1,u,3,5>: Cost 2 vsldoi4 LHS, <5,5,5,5> + 3001848314U, // <1,u,3,6>: Cost 2 vsldoi4 LHS, <6,2,7,3> + 3001848826U, // <1,u,3,7>: Cost 2 vsldoi4 LHS, <7,0,1,2> + 1880332078U, // <1,u,3,u>: Cost 1 vsldoi4 LHS, LHS + 4184779637U, // <1,u,4,0>: Cost 3 vsldoi8 <4,0,1,u>, <4,0,1,u> + 4163546109U, // <1,u,4,1>: Cost 3 vsldoi8 <0,4,1,u>, <4,1,u,0> + 3230040982U, // <1,u,4,2>: Cost 3 vmrghw <1,4,2,5>, <1,2,3,0> + 3357540508U, // <1,u,4,3>: Cost 3 vmrglw <0,3,1,4>, LHS + 4051708929U, // <1,u,4,4>: Cost 3 vsldoi4 <4,1,u,4>, <4,1,u,4> + 3089804598U, // <1,u,4,5>: Cost 2 vsldoi8 <0,4,1,u>, RHS + 3357542914U, // <1,u,4,6>: Cost 3 vmrglw <0,3,1,4>, <3,4,5,6> + 3357543752U, // <1,u,4,7>: Cost 3 vmrglw <0,3,1,4>, RHS + 3089804841U, // <1,u,4,u>: Cost 2 vsldoi8 <0,4,1,u>, RHS + 3358213059U, // <1,u,5,0>: Cost 3 vmrglw <0,4,1,5>, <1,2,u,0> + 3358213870U, // <1,u,5,1>: Cost 3 vmrglw <0,4,1,5>, <2,3,u,1> + 3358214357U, // <1,u,5,2>: Cost 3 vmrglw <0,4,1,5>, <3,0,u,2> + 2284470428U, // <1,u,5,3>: Cost 2 vmrglw <0,4,1,5>, LHS + 3358213063U, // <1,u,5,4>: Cost 3 vmrglw <0,4,1,5>, <1,2,u,4> + 2284470610U, // <1,u,5,5>: Cost 2 vmrglw <0,4,1,5>, <0,4,1,5> + 3226622106U, // <1,u,5,6>: Cost 2 vsldoi12 <0,u,1,1>, RHS + 2284473672U, // <1,u,5,7>: Cost 2 vmrglw <0,4,1,5>, RHS + 2284470433U, // <1,u,5,u>: Cost 2 vmrglw <0,4,1,5>, LHS + 4196725031U, // <1,u,6,0>: Cost 3 vsldoi8 <6,0,1,u>, <6,0,1,u> + 3227138238U, // <1,u,6,1>: Cost 3 vsldoi12 <0,u,u,1>, + 4202697210U, // <1,u,6,2>: Cost 3 vsldoi8 <7,0,1,u>, <6,2,7,3> + 3356893340U, // <1,u,6,3>: Cost 3 vmrglw <0,2,1,6>, LHS + 3231605074U, // <1,u,6,4>: Cost 3 vmrghw <1,6,5,7>, <0,4,1,5> + 3231316122U, // <1,u,6,5>: Cost 3 vmrghw <1,6,1,7>, RHS + 4202697528U, // <1,u,6,6>: Cost 3 vsldoi8 <7,0,1,u>, <6,6,6,6> + 3356896584U, // <1,u,6,7>: Cost 3 vmrglw <0,2,1,6>, RHS + 3356893345U, // <1,u,6,u>: Cost 3 vmrglw <0,2,1,6>, LHS + 3128955904U, // <1,u,7,0>: Cost 2 vsldoi8 <7,0,1,u>, <7,0,1,u> + 3407332049U, // <1,u,7,1>: Cost 3 vmrglw , <0,u,u,1> + 3235174676U, // <1,u,7,2>: Cost 3 vsldoi12 <2,3,0,1>, + 3365527708U, // <1,u,7,3>: Cost 3 vmrglw <1,6,1,7>, LHS + 3250805032U, // <1,u,7,4>: Cost 3 vsldoi12 <4,u,5,1>, + 3365527953U, // <1,u,7,5>: Cost 4 vmrglw <1,6,1,7>, <0,4,u,5> + 3261716796U, // <1,u,7,6>: Cost 3 vsldoi12 <6,7,0,1>, + 3365530952U, // <1,u,7,7>: Cost 3 vmrglw <1,6,1,7>, RHS + 3134264968U, // <1,u,7,u>: Cost 2 vsldoi8 <7,u,1,u>, <7,u,1,u> + 1880367265U, // <1,u,u,0>: Cost 1 vsldoi4 LHS, LHS + 1477230694U, // <1,u,u,1>: Cost 1 vspltisw1 LHS + 2954110568U, // <1,u,u,2>: Cost 2 vsldoi4 LHS, <2,2,2,2> + 2954111126U, // <1,u,u,3>: Cost 2 vsldoi4 LHS, <3,0,1,2> + 1880370486U, // <1,u,u,4>: Cost 1 vsldoi4 LHS, RHS + 3089807514U, // <1,u,u,5>: Cost 2 vsldoi8 <0,4,1,u>, RHS + 3226622349U, // <1,u,u,6>: Cost 2 vsldoi12 <0,u,1,1>, RHS + 2284498248U, // <1,u,u,7>: Cost 2 vmrglw <0,4,1,u>, RHS + 1880373038U, // <1,u,u,u>: Cost 1 vsldoi4 LHS, LHS + 3233390592U, // <2,0,0,0>: Cost 3 vmrghw <2,0,3,0>, <0,0,0,0> + 3233390694U, // <2,0,0,1>: Cost 3 vmrghw <2,0,3,0>, LHS + 3222642707U, // <2,0,0,2>: Cost 4 vsldoi12 <0,2,1,2>, <0,0,2,1> + 3239231516U, // <2,0,0,3>: Cost 4 vsldoi12 <3,0,1,2>, <0,0,3,1> + 3233390930U, // <2,0,0,4>: Cost 4 vmrghw <2,0,3,0>, <0,4,1,5> + 3356256724U, // <2,0,0,5>: Cost 4 vmrglw <0,1,2,0>, <3,4,0,5> + 3221684280U, // <2,0,0,6>: Cost 4 vsldoi12 <0,0,6,2>, <0,0,6,2> + 4165542473U, // <2,0,0,7>: Cost 4 vsldoi8 <0,7,2,0>, <0,7,2,0> + 3233391261U, // <2,0,0,u>: Cost 3 vmrghw <2,0,3,0>, LHS + 3234062346U, // <2,0,1,0>: Cost 3 vmrghw <2,1,3,1>, <0,0,1,1> + 3234062438U, // <2,0,1,1>: Cost 3 vmrghw <2,1,3,1>, LHS + 3234660454U, // <2,0,1,2>: Cost 2 vsldoi12 <2,2,2,2>, LHS + 4075645141U, // <2,0,1,3>: Cost 3 vsldoi4 , <3,0,u,2> + 3234095442U, // <2,0,1,4>: Cost 3 vmrghw <2,1,3,5>, <0,4,1,5> + 4057730784U, // <2,0,1,5>: Cost 4 vsldoi4 <5,2,0,1>, <5,2,0,1> + 3263119502U, // <2,0,1,6>: Cost 4 vsldoi12 <7,0,1,2>, <0,1,6,7> + 3366881912U, // <2,0,1,7>: Cost 4 vmrglw <1,u,2,1>, <3,6,0,7> + 3234660508U, // <2,0,1,u>: Cost 2 vsldoi12 <2,2,2,2>, LHS + 3234660352U, // <2,0,2,0>: Cost 3 vmrghw <2,2,2,2>, <0,0,0,0> + 2160918630U, // <2,0,2,1>: Cost 2 vmrghw <2,2,2,2>, LHS + 3234660525U, // <2,0,2,2>: Cost 3 vmrghw <2,2,2,2>, <0,2,1,2> + 3234660604U, // <2,0,2,3>: Cost 4 vmrghw <2,2,2,2>, <0,3,1,0> + 3234660690U, // <2,0,2,4>: Cost 3 vmrghw <2,2,2,2>, <0,4,1,5> + 3234660771U, // <2,0,2,5>: Cost 4 vmrghw <2,2,2,2>, <0,5,1,5> + 4183459770U, // <2,0,2,6>: Cost 4 vsldoi8 <3,7,2,0>, <2,6,3,7> + 3368880760U, // <2,0,2,7>: Cost 4 vmrglw <2,2,2,2>, <3,6,0,7> + 2160919197U, // <2,0,2,u>: Cost 2 vmrghw <2,2,2,2>, LHS + 2287181824U, // <2,0,3,0>: Cost 2 vmrglw LHS, <0,0,0,0> + 2287183526U, // <2,0,3,1>: Cost 2 vmrglw LHS, <2,3,0,1> + 3235168430U, // <2,0,3,2>: Cost 3 vmrghw <2,3,0,1>, <0,2,1,3> + 4045801776U, // <2,0,3,3>: Cost 3 vsldoi4 <3,2,0,3>, <3,2,0,3> + 3360924786U, // <2,0,3,4>: Cost 3 vmrglw LHS, <1,5,0,4> + 4069691490U, // <2,0,3,5>: Cost 3 vsldoi4 <7,2,0,3>, <5,6,7,0> + 3235168758U, // <2,0,3,6>: Cost 3 vmrghw <2,3,0,1>, <0,6,1,7> + 4069692564U, // <2,0,3,7>: Cost 3 vsldoi4 <7,2,0,3>, <7,2,0,3> + 2287183533U, // <2,0,3,u>: Cost 2 vmrglw LHS, <2,3,0,u> + 3368894464U, // <2,0,4,0>: Cost 4 vmrglw <2,2,2,4>, <0,0,0,0> + 3234660690U, // <2,0,4,1>: Cost 3 vsldoi12 <2,2,2,2>, <0,4,1,5> + 3222643035U, // <2,0,4,2>: Cost 4 vsldoi12 <0,2,1,2>, <0,4,2,5> + 3239231844U, // <2,0,4,3>: Cost 4 vsldoi12 <3,0,1,2>, <0,4,3,5> + 3234660717U, // <2,0,4,4>: Cost 4 vsldoi12 <2,2,2,2>, <0,4,4,5> + 4209339702U, // <2,0,4,5>: Cost 3 vsldoi8 , RHS + 4200050041U, // <2,0,4,6>: Cost 4 vsldoi8 <6,5,2,0>, <4,6,5,2> + 3263119752U, // <2,0,4,7>: Cost 4 vsldoi12 <7,0,1,2>, <0,4,7,5> + 3234660753U, // <2,0,4,u>: Cost 3 vsldoi12 <2,2,2,2>, <0,4,u,5> + 3364257792U, // <2,0,5,0>: Cost 4 vmrglw <1,4,2,5>, <0,0,0,0> + 3236757606U, // <2,0,5,1>: Cost 3 vmrghw <2,5,3,6>, LHS + 3237126320U, // <2,0,5,2>: Cost 4 vmrghw <2,5,u,6>, <0,2,1,5> + 3364260144U, // <2,0,5,3>: Cost 4 vmrglw <1,4,2,5>, <3,2,0,3> + 3236708690U, // <2,0,5,4>: Cost 4 vmrghw <2,5,3,0>, <0,4,1,5> + 3364260146U, // <2,0,5,5>: Cost 4 vmrglw <1,4,2,5>, <3,2,0,5> + 3263119826U, // <2,0,5,6>: Cost 4 vsldoi12 <7,0,1,2>, <0,5,6,7> + 3364260472U, // <2,0,5,7>: Cost 4 vmrglw <1,4,2,5>, <3,6,0,7> + 3236758173U, // <2,0,5,u>: Cost 3 vmrghw <2,5,3,6>, LHS + 3237429248U, // <2,0,6,0>: Cost 3 vmrghw <2,6,3,7>, <0,0,0,0> + 2163687526U, // <2,0,6,1>: Cost 2 vmrghw <2,6,3,7>, LHS + 3237429425U, // <2,0,6,2>: Cost 3 vmrghw <2,6,3,7>, <0,2,1,6> + 3237429500U, // <2,0,6,3>: Cost 4 vmrghw <2,6,3,7>, <0,3,1,0> + 3237429586U, // <2,0,6,4>: Cost 3 vmrghw <2,6,3,7>, <0,4,1,5> + 4200051389U, // <2,0,6,5>: Cost 4 vsldoi8 <6,5,2,0>, <6,5,2,0> + 3237429750U, // <2,0,6,6>: Cost 4 vmrghw <2,6,3,7>, <0,6,1,7> + 4201378655U, // <2,0,6,7>: Cost 4 vsldoi8 <6,7,2,0>, <6,7,2,0> + 2163688093U, // <2,0,6,u>: Cost 2 vmrghw <2,6,3,7>, LHS + 3371573248U, // <2,0,7,0>: Cost 4 vmrglw <2,6,2,7>, <0,0,0,0> + 3237822566U, // <2,0,7,1>: Cost 3 vmrghw <2,7,0,1>, LHS + 4204033187U, // <2,0,7,2>: Cost 4 vsldoi8 <7,2,2,0>, <7,2,2,0> + 4204696820U, // <2,0,7,3>: Cost 4 vsldoi8 <7,3,2,0>, <7,3,2,0> + 4209341798U, // <2,0,7,4>: Cost 4 vsldoi8 , <7,4,5,6> + 3356317308U, // <2,0,7,5>: Cost 4 vmrglw <0,1,2,7>, <7,u,0,5> + 4206687719U, // <2,0,7,6>: Cost 4 vsldoi8 <7,6,2,0>, <7,6,2,0> + 4209342060U, // <2,0,7,7>: Cost 4 vsldoi8 , <7,7,7,7> + 3237823133U, // <2,0,7,u>: Cost 3 vmrghw <2,7,0,1>, LHS + 2282577920U, // <2,0,u,0>: Cost 2 vmrglw LHS, <0,0,0,0> + 2282579622U, // <2,0,u,1>: Cost 2 vmrglw LHS, <2,3,0,1> + 3234661021U, // <2,0,u,2>: Cost 2 vsldoi12 <2,2,2,2>, LHS + 4045842741U, // <2,0,u,3>: Cost 3 vsldoi4 <3,2,0,u>, <3,2,0,u> + 3356321449U, // <2,0,u,4>: Cost 3 vmrglw LHS, <2,3,0,4> + 4069732450U, // <2,0,u,5>: Cost 3 vsldoi4 <7,2,0,u>, <5,6,7,0> + 3235168758U, // <2,0,u,6>: Cost 3 vmrghw <2,3,0,1>, <0,6,1,7> + 4069733529U, // <2,0,u,7>: Cost 3 vsldoi4 <7,2,0,u>, <7,2,0,u> + 2282579629U, // <2,0,u,u>: Cost 2 vmrglw LHS, <2,3,0,u> + 4027932843U, // <2,1,0,0>: Cost 4 vsldoi4 <0,2,1,0>, <0,2,1,0> + 3227288292U, // <2,1,0,1>: Cost 3 vsldoi12 <1,0,1,2>, <1,0,1,2> + 3404032798U, // <2,1,0,2>: Cost 3 vmrglw , <3,u,1,2> + 3239232244U, // <2,1,0,3>: Cost 4 vsldoi12 <3,0,1,2>, <1,0,3,0> + 4027936054U, // <2,1,0,4>: Cost 4 vsldoi4 <0,2,1,0>, RHS + 3233424498U, // <2,1,0,5>: Cost 4 vmrghw <2,0,3,4>, <1,5,0,4> + 4196737521U, // <2,1,0,6>: Cost 4 vsldoi8 <6,0,2,1>, <0,6,1,2> + 3374170614U, // <2,1,0,7>: Cost 5 vmrglw <3,1,2,0>, <0,6,1,7> + 3227804451U, // <2,1,0,u>: Cost 3 vsldoi12 <1,0,u,2>, <1,0,u,2> + 4166877932U, // <2,1,1,0>: Cost 3 vsldoi8 <1,0,2,1>, <1,0,2,1> + 3234661172U, // <2,1,1,1>: Cost 3 vsldoi12 <2,2,2,2>, <1,1,1,1> + 4172186518U, // <2,1,1,2>: Cost 3 vsldoi8 <1,u,2,1>, <1,2,3,0> + 3362235271U, // <2,1,1,3>: Cost 4 vmrglw <1,1,2,1>, <1,2,1,3> + 4027944246U, // <2,1,1,4>: Cost 4 vsldoi4 <0,2,1,1>, RHS + 3228246873U, // <2,1,1,5>: Cost 4 vsldoi12 <1,1,5,2>, <1,1,5,2> + 3234096371U, // <2,1,1,6>: Cost 4 vmrghw <2,1,3,5>, <1,6,5,7> + 4171523363U, // <2,1,1,7>: Cost 4 vsldoi8 <1,7,2,1>, <1,7,2,1> + 4172186996U, // <2,1,1,u>: Cost 3 vsldoi8 <1,u,2,1>, <1,u,2,1> + 4027949229U, // <2,1,2,0>: Cost 3 vsldoi4 <0,2,1,2>, <0,2,1,2> + 3234661172U, // <2,1,2,1>: Cost 3 vmrghw <2,2,2,2>, <1,1,1,1> + 4027950696U, // <2,1,2,2>: Cost 3 vsldoi4 <0,2,1,2>, <2,2,2,2> + 3228763032U, // <2,1,2,3>: Cost 3 vsldoi12 <1,2,3,2>, <1,2,3,2> + 4027952438U, // <2,1,2,4>: Cost 3 vsldoi4 <0,2,1,2>, RHS + 3368878418U, // <2,1,2,5>: Cost 3 vmrglw <2,2,2,2>, <0,4,1,5> + 4172187560U, // <2,1,2,6>: Cost 4 vsldoi8 <1,u,2,1>, <2,6,1,7> + 3263120314U, // <2,1,2,7>: Cost 3 vsldoi12 <7,0,1,2>, <1,2,7,0> + 4027954990U, // <2,1,2,u>: Cost 3 vsldoi4 <0,2,1,2>, LHS + 3356278793U, // <2,1,3,0>: Cost 3 vmrglw LHS, <0,0,1,0> + 2282536970U, // <2,1,3,1>: Cost 2 vmrglw LHS, <0,0,1,1> + 2287184022U, // <2,1,3,2>: Cost 2 vmrglw LHS, <3,0,1,2> + 3360923822U, // <2,1,3,3>: Cost 3 vmrglw LHS, <0,2,1,3> + 4027960630U, // <2,1,3,4>: Cost 3 vsldoi4 <0,2,1,3>, RHS + 2282537298U, // <2,1,3,5>: Cost 2 vmrglw LHS, <0,4,1,5> + 3360923825U, // <2,1,3,6>: Cost 3 vmrglw LHS, <0,2,1,6> + 3360924879U, // <2,1,3,7>: Cost 3 vmrglw LHS, <1,6,1,7> + 2282536977U, // <2,1,3,u>: Cost 2 vmrglw LHS, <0,0,1,u> + 4027965615U, // <2,1,4,0>: Cost 4 vsldoi4 <0,2,1,4>, <0,2,1,4> + 3234661419U, // <2,1,4,1>: Cost 4 vsldoi12 <2,2,2,2>, <1,4,1,5> + 3404065566U, // <2,1,4,2>: Cost 3 vmrglw , <3,u,1,2> + 4027967638U, // <2,1,4,3>: Cost 5 vsldoi4 <0,2,1,4>, <3,0,1,2> + 4027968822U, // <2,1,4,4>: Cost 4 vsldoi4 <0,2,1,4>, RHS + 4172188982U, // <2,1,4,5>: Cost 3 vsldoi8 <1,u,2,1>, RHS + 4202048889U, // <2,1,4,6>: Cost 4 vsldoi8 <6,u,2,1>, <4,6,5,2> + 3368895695U, // <2,1,4,7>: Cost 5 vmrglw <2,2,2,4>, <1,6,1,7> + 4172189225U, // <2,1,4,u>: Cost 3 vsldoi8 <1,u,2,1>, RHS + 4027973808U, // <2,1,5,0>: Cost 4 vsldoi4 <0,2,1,5>, <0,2,1,5> + 3364257802U, // <2,1,5,1>: Cost 4 vmrglw <1,4,2,5>, <0,0,1,1> + 4027975573U, // <2,1,5,2>: Cost 4 vsldoi4 <0,2,1,5>, <2,5,u,6> + 4027976194U, // <2,1,5,3>: Cost 4 vsldoi4 <0,2,1,5>, <3,4,5,6> + 4027977014U, // <2,1,5,4>: Cost 4 vsldoi4 <0,2,1,5>, RHS + 3364258130U, // <2,1,5,5>: Cost 4 vmrglw <1,4,2,5>, <0,4,1,5> + 3236766963U, // <2,1,5,6>: Cost 4 vmrghw <2,5,3,7>, <1,6,5,7> + 3263120557U, // <2,1,5,7>: Cost 4 vsldoi12 <7,0,1,2>, <1,5,7,0> + 4027979566U, // <2,1,5,u>: Cost 4 vsldoi4 <0,2,1,5>, LHS + 4027982001U, // <2,1,6,0>: Cost 3 vsldoi4 <0,2,1,6>, <0,2,1,6> + 3237430068U, // <2,1,6,1>: Cost 3 vmrghw <2,6,3,7>, <1,1,1,1> + 4027983802U, // <2,1,6,2>: Cost 3 vsldoi4 <0,2,1,6>, <2,6,3,7> + 4027984022U, // <2,1,6,3>: Cost 4 vsldoi4 <0,2,1,6>, <3,0,1,2> + 4027985206U, // <2,1,6,4>: Cost 3 vsldoi4 <0,2,1,6>, RHS + 3364929874U, // <2,1,6,5>: Cost 4 vmrglw <1,5,2,6>, <0,4,1,5> + 4027986744U, // <2,1,6,6>: Cost 4 vsldoi4 <0,2,1,6>, <6,6,6,6> + 4201386848U, // <2,1,6,7>: Cost 4 vsldoi8 <6,7,2,1>, <6,7,2,1> + 4027987758U, // <2,1,6,u>: Cost 3 vsldoi4 <0,2,1,6>, LHS + 4202050554U, // <2,1,7,0>: Cost 4 vsldoi8 <6,u,2,1>, <7,0,1,2> + 3371573258U, // <2,1,7,1>: Cost 4 vmrglw <2,6,2,7>, <0,0,1,1> + 3404093058U, // <2,1,7,2>: Cost 3 vmrglw , <7,u,1,2> + 4202050842U, // <2,1,7,3>: Cost 4 vsldoi8 <6,u,2,1>, <7,3,6,2> + 4202050918U, // <2,1,7,4>: Cost 4 vsldoi8 <6,u,2,1>, <7,4,5,6> + 3371573586U, // <2,1,7,5>: Cost 4 vmrglw <2,6,2,7>, <0,4,1,5> + 4202051054U, // <2,1,7,6>: Cost 4 vsldoi8 <6,u,2,1>, <7,6,2,7> + 4202051140U, // <2,1,7,7>: Cost 4 vsldoi8 <6,u,2,1>, <7,7,3,3> + 3404093058U, // <2,1,7,u>: Cost 3 vmrglw , <7,u,1,2> + 3356319753U, // <2,1,u,0>: Cost 3 vmrglw LHS, <0,0,1,0> + 2282577930U, // <2,1,u,1>: Cost 2 vmrglw LHS, <0,0,1,1> + 2282580118U, // <2,1,u,2>: Cost 2 vmrglw LHS, <3,0,1,2> + 3356319918U, // <2,1,u,3>: Cost 3 vmrglw LHS, <0,2,1,3> + 3356319757U, // <2,1,u,4>: Cost 3 vmrglw LHS, <0,0,1,4> + 2282578258U, // <2,1,u,5>: Cost 2 vmrglw LHS, <0,4,1,5> + 3356319921U, // <2,1,u,6>: Cost 3 vmrglw LHS, <0,2,1,6> + 3360965839U, // <2,1,u,7>: Cost 3 vmrglw LHS, <1,6,1,7> + 2282577937U, // <2,1,u,u>: Cost 2 vmrglw LHS, <0,0,1,u> + 3233392077U, // <2,2,0,0>: Cost 3 vmrghw <2,0,3,0>, <2,0,3,0> + 3100442726U, // <2,2,0,1>: Cost 2 vsldoi8 <2,2,2,2>, LHS + 4174184621U, // <2,2,0,2>: Cost 3 vsldoi8 <2,2,2,2>, <0,2,1,2> + 3233400486U, // <2,2,0,3>: Cost 3 vmrghw <2,0,3,1>, <2,3,0,1> + 4174184786U, // <2,2,0,4>: Cost 3 vsldoi8 <2,2,2,2>, <0,4,1,5> + 3233548136U, // <2,2,0,5>: Cost 4 vmrghw <2,0,5,1>, <2,5,3,6> + 3233621946U, // <2,2,0,6>: Cost 3 vmrghw <2,0,6,1>, <2,6,3,7> + 4069815459U, // <2,2,0,7>: Cost 4 vsldoi4 <7,2,2,0>, <7,2,2,0> + 3100443293U, // <2,2,0,u>: Cost 2 vsldoi8 <2,2,2,2>, LHS + 3227289092U, // <2,2,1,0>: Cost 4 vsldoi12 <1,0,1,2>, <2,1,0,1> + 3366880628U, // <2,2,1,1>: Cost 3 vmrglw <1,u,2,1>, <1,u,2,1> + 4174185366U, // <2,2,1,2>: Cost 3 vsldoi8 <2,2,2,2>, <1,2,3,0> + 3366879334U, // <2,2,1,3>: Cost 3 vmrglw <1,u,2,1>, LHS + 4174185515U, // <2,2,1,4>: Cost 4 vsldoi8 <2,2,2,2>, <1,4,1,5> + 4170204290U, // <2,2,1,5>: Cost 4 vsldoi8 <1,5,2,2>, <1,5,2,2> + 3234064314U, // <2,2,1,6>: Cost 4 vmrghw <2,1,3,1>, <2,6,3,7> + 3372853169U, // <2,2,1,7>: Cost 4 vmrglw <2,u,2,1>, <2,6,2,7> + 3366879339U, // <2,2,1,u>: Cost 3 vmrglw <1,u,2,1>, LHS + 2966224998U, // <2,2,2,0>: Cost 2 vsldoi4 <2,2,2,2>, LHS + 3368879557U, // <2,2,2,1>: Cost 3 vmrglw <2,2,2,2>, <2,0,2,1> + 1611448422U, // <2,2,2,2>: Cost 1 vspltisw2 LHS + 2295136358U, // <2,2,2,3>: Cost 2 vmrglw <2,2,2,2>, LHS + 2966228278U, // <2,2,2,4>: Cost 2 vsldoi4 <2,2,2,2>, RHS + 3368879885U, // <2,2,2,5>: Cost 3 vmrglw <2,2,2,2>, <2,4,2,5> + 3234662330U, // <2,2,2,6>: Cost 3 vmrghw <2,2,2,2>, <2,6,3,7> + 4069831845U, // <2,2,2,7>: Cost 3 vsldoi4 <7,2,2,2>, <7,2,2,2> + 1611448422U, // <2,2,2,u>: Cost 1 vspltisw2 LHS + 4174186646U, // <2,2,3,0>: Cost 3 vsldoi8 <2,2,2,2>, <3,0,1,2> + 3235251888U, // <2,2,3,1>: Cost 3 vsldoi12 <2,3,1,2>, <2,3,1,2> + 2287183464U, // <2,2,3,2>: Cost 2 vmrglw LHS, <2,2,2,2> + 1208795238U, // <2,2,3,3>: Cost 1 vmrglw LHS, LHS + 4174187010U, // <2,2,3,4>: Cost 3 vsldoi8 <2,2,2,2>, <3,4,5,6> + 3404055604U, // <2,2,3,5>: Cost 3 vmrglw LHS, <1,4,2,5> + 3360925373U, // <2,2,3,6>: Cost 3 vmrglw LHS, <2,3,2,6> + 4069840038U, // <2,2,3,7>: Cost 3 vsldoi4 <7,2,2,3>, <7,2,2,3> + 1208795243U, // <2,2,3,u>: Cost 1 vmrglw LHS, LHS + 4039983206U, // <2,2,4,0>: Cost 3 vsldoi4 <2,2,2,4>, LHS + 4174187466U, // <2,2,4,1>: Cost 4 vsldoi8 <2,2,2,2>, <4,1,2,3> + 3234662157U, // <2,2,4,2>: Cost 3 vsldoi12 <2,2,2,2>, <2,4,2,5> + 3368894566U, // <2,2,4,3>: Cost 3 vmrglw <2,2,2,4>, LHS + 3368896106U, // <2,2,4,4>: Cost 3 vmrglw <2,2,2,4>, <2,2,2,4> + 3100446006U, // <2,2,4,5>: Cost 2 vsldoi8 <2,2,2,2>, RHS + 3236308922U, // <2,2,4,6>: Cost 3 vmrghw <2,4,6,5>, <2,6,3,7> + 3368896433U, // <2,2,4,7>: Cost 4 vmrglw <2,2,2,4>, <2,6,2,7> + 3100446249U, // <2,2,4,u>: Cost 2 vsldoi8 <2,2,2,2>, RHS + 4174188104U, // <2,2,5,0>: Cost 4 vsldoi8 <2,2,2,2>, <5,0,1,2> + 3364258540U, // <2,2,5,1>: Cost 4 vmrglw <1,4,2,5>, <1,0,2,1> + 3370231400U, // <2,2,5,2>: Cost 3 vmrglw <2,4,2,5>, <2,2,2,2> + 3364257894U, // <2,2,5,3>: Cost 3 vmrglw <1,4,2,5>, LHS + 4174188468U, // <2,2,5,4>: Cost 4 vsldoi8 <2,2,2,2>, <5,4,5,6> + 3364258868U, // <2,2,5,5>: Cost 3 vmrglw <1,4,2,5>, <1,4,2,5> + 4174188642U, // <2,2,5,6>: Cost 3 vsldoi8 <2,2,2,2>, <5,6,7,0> + 3370231729U, // <2,2,5,7>: Cost 4 vmrglw <2,4,2,5>, <2,6,2,7> + 3364257899U, // <2,2,5,u>: Cost 3 vmrglw <1,4,2,5>, LHS + 3237430761U, // <2,2,6,0>: Cost 3 vmrghw <2,6,3,7>, <2,0,6,1> + 3237430815U, // <2,2,6,1>: Cost 4 vmrghw <2,6,3,7>, <2,1,3,1> + 3234662321U, // <2,2,6,2>: Cost 3 vsldoi12 <2,2,2,2>, <2,6,2,7> + 3234662330U, // <2,2,6,3>: Cost 3 vsldoi12 <2,2,2,2>, <2,6,3,7> + 3237431089U, // <2,2,6,4>: Cost 3 vmrghw <2,6,3,7>, <2,4,6,5> + 3237431144U, // <2,2,6,5>: Cost 4 vmrghw <2,6,3,7>, <2,5,3,6> + 2163689402U, // <2,2,6,6>: Cost 2 vmrghw <2,6,3,7>, <2,6,3,7> + 4201395041U, // <2,2,6,7>: Cost 3 vsldoi8 <6,7,2,2>, <6,7,2,2> + 2163689402U, // <2,2,6,u>: Cost 2 vmrghw <2,6,3,7>, <2,6,3,7> + 3263121386U, // <2,2,7,0>: Cost 3 vsldoi12 <7,0,1,2>, <2,7,0,1> + 3371574725U, // <2,2,7,1>: Cost 4 vmrglw <2,6,2,7>, <2,0,2,1> + 3371574888U, // <2,2,7,2>: Cost 3 vmrglw <2,6,2,7>, <2,2,2,2> + 3371573350U, // <2,2,7,3>: Cost 3 vmrglw <2,6,2,7>, LHS + 4174189926U, // <2,2,7,4>: Cost 3 vsldoi8 <2,2,2,2>, <7,4,5,6> + 3371575053U, // <2,2,7,5>: Cost 4 vmrglw <2,6,2,7>, <2,4,2,5> + 3237824433U, // <2,2,7,6>: Cost 4 vmrghw <2,7,0,1>, <2,6,2,7> + 3371575217U, // <2,2,7,7>: Cost 3 vmrglw <2,6,2,7>, <2,6,2,7> + 3371573355U, // <2,2,7,u>: Cost 3 vmrglw <2,6,2,7>, LHS + 2966224998U, // <2,2,u,0>: Cost 2 vsldoi4 <2,2,2,2>, LHS + 3100448558U, // <2,2,u,1>: Cost 2 vsldoi8 <2,2,2,2>, LHS + 1611448422U, // <2,2,u,2>: Cost 1 vspltisw2 LHS + 1208836198U, // <2,2,u,3>: Cost 1 vmrglw LHS, LHS + 2966228278U, // <2,2,u,4>: Cost 2 vsldoi4 <2,2,2,2>, RHS + 3100448922U, // <2,2,u,5>: Cost 2 vsldoi8 <2,2,2,2>, RHS + 2163689402U, // <2,2,u,6>: Cost 2 vmrghw <2,6,3,7>, <2,6,3,7> + 4069881003U, // <2,2,u,7>: Cost 3 vsldoi4 <7,2,2,u>, <7,2,2,u> + 1208836203U, // <2,2,u,u>: Cost 1 vmrglw LHS, LHS + 3087843328U, // <2,3,0,0>: Cost 2 vsldoi8 LHS, <0,0,0,0> + 2014101606U, // <2,3,0,1>: Cost 1 vsldoi8 LHS, LHS + 4166230189U, // <2,3,0,2>: Cost 3 vsldoi8 LHS, <0,2,1,2> + 4166230268U, // <2,3,0,3>: Cost 3 vsldoi8 LHS, <0,3,1,0> + 3087843666U, // <2,3,0,4>: Cost 2 vsldoi8 LHS, <0,4,1,5> + 4209361362U, // <2,3,0,5>: Cost 3 vsldoi8 LHS, <0,5,6,7> + 4209361398U, // <2,3,0,6>: Cost 3 vsldoi8 LHS, <0,6,1,7> + 4069889196U, // <2,3,0,7>: Cost 3 vsldoi4 <7,2,3,0>, <7,2,3,0> + 2014102173U, // <2,3,0,u>: Cost 1 vsldoi8 LHS, LHS + 4166230756U, // <2,3,1,0>: Cost 3 vsldoi8 LHS, <1,0,1,2> + 3087844148U, // <2,3,1,1>: Cost 2 vsldoi8 LHS, <1,1,1,1> + 3087844246U, // <2,3,1,2>: Cost 2 vsldoi8 LHS, <1,2,3,0> + 4166230989U, // <2,3,1,3>: Cost 4 vsldoi8 LHS, <1,3,0,1> + 4166231120U, // <2,3,1,4>: Cost 3 vsldoi8 LHS, <1,4,5,6> + 4166231151U, // <2,3,1,5>: Cost 3 vsldoi8 LHS, <1,5,0,1> + 4166231247U, // <2,3,1,6>: Cost 3 vsldoi8 LHS, <1,6,1,7> + 3366881210U, // <2,3,1,7>: Cost 4 vmrglw <1,u,2,1>, <2,6,3,7> + 3092489596U, // <2,3,1,u>: Cost 2 vsldoi8 LHS, <1,u,3,0> + 4166231501U, // <2,3,2,0>: Cost 3 vsldoi8 LHS, <2,0,3,0> + 4161586719U, // <2,3,2,1>: Cost 3 vsldoi8 LHS, <2,1,3,1> + 3087844968U, // <2,3,2,2>: Cost 2 vsldoi8 LHS, <2,2,2,2> + 3087845030U, // <2,3,2,3>: Cost 2 vsldoi8 LHS, <2,3,0,1> + 4166231830U, // <2,3,2,4>: Cost 3 vsldoi8 LHS, <2,4,3,5> + 4166231912U, // <2,3,2,5>: Cost 3 vsldoi8 LHS, <2,5,3,6> + 3087845306U, // <2,3,2,6>: Cost 2 vsldoi8 LHS, <2,6,3,7> + 3368880058U, // <2,3,2,7>: Cost 3 vmrglw <2,2,2,2>, <2,6,3,7> + 3087845464U, // <2,3,2,u>: Cost 2 vsldoi8 LHS, <2,u,3,3> + 2287182742U, // <2,3,3,0>: Cost 2 vmrglw LHS, <1,2,3,0> + 3356280351U, // <2,3,3,1>: Cost 3 vmrglw LHS, <2,1,3,1> + 2966308466U, // <2,3,3,2>: Cost 2 vsldoi4 <2,2,3,3>, <2,2,3,3> + 2282538610U, // <2,3,3,3>: Cost 2 vmrglw LHS, <2,2,3,3> + 2287182746U, // <2,3,3,4>: Cost 2 vmrglw LHS, <1,2,3,4> + 3356280355U, // <2,3,3,5>: Cost 3 vmrglw LHS, <2,1,3,5> + 3360929918U, // <2,3,3,6>: Cost 3 vmrglw LHS, + 2287183802U, // <2,3,3,7>: Cost 2 vmrglw LHS, <2,6,3,7> + 2282538615U, // <2,3,3,u>: Cost 2 vmrglw LHS, <2,2,3,u> + 2960343142U, // <2,3,4,0>: Cost 2 vsldoi4 <1,2,3,4>, LHS + 2960343962U, // <2,3,4,1>: Cost 2 vsldoi4 <1,2,3,4>, <1,2,3,4> + 4034086504U, // <2,3,4,2>: Cost 3 vsldoi4 <1,2,3,4>, <2,2,2,2> + 4034087062U, // <2,3,4,3>: Cost 3 vsldoi4 <1,2,3,4>, <3,0,1,2> + 2960346422U, // <2,3,4,4>: Cost 2 vsldoi4 <1,2,3,4>, RHS + 2014104886U, // <2,3,4,5>: Cost 1 vsldoi8 LHS, RHS + 4209364345U, // <2,3,4,6>: Cost 3 vsldoi8 LHS, <4,6,5,2> + 4069921968U, // <2,3,4,7>: Cost 3 vsldoi4 <7,2,3,4>, <7,2,3,4> + 2014105129U, // <2,3,4,u>: Cost 1 vsldoi8 LHS, RHS + 4166233672U, // <2,3,5,0>: Cost 3 vsldoi8 LHS, <5,0,1,2> + 4209364623U, // <2,3,5,1>: Cost 3 vsldoi8 LHS, <5,1,0,1> + 4209364715U, // <2,3,5,2>: Cost 3 vsldoi8 LHS, <5,2,1,3> + 4166233905U, // <2,3,5,3>: Cost 4 vsldoi8 LHS, <5,3,0,1> + 4166234036U, // <2,3,5,4>: Cost 3 vsldoi8 LHS, <5,4,5,6> + 3135623172U, // <2,3,5,5>: Cost 2 vsldoi8 LHS, <5,5,5,5> + 3135623266U, // <2,3,5,6>: Cost 2 vsldoi8 LHS, <5,6,7,0> + 3364259770U, // <2,3,5,7>: Cost 4 vmrglw <1,4,2,5>, <2,6,3,7> + 3135623428U, // <2,3,5,u>: Cost 2 vsldoi8 LHS, <5,u,7,0> + 3237431446U, // <2,3,6,0>: Cost 3 vmrghw <2,6,3,7>, <3,0,1,2> + 4209365415U, // <2,3,6,1>: Cost 3 vsldoi8 LHS, <6,1,7,1> + 3135623674U, // <2,3,6,2>: Cost 2 vsldoi8 LHS, <6,2,7,3> + 3237431708U, // <2,3,6,3>: Cost 3 vmrghw <2,6,3,7>, <3,3,3,3> + 3237431810U, // <2,3,6,4>: Cost 3 vmrghw <2,6,3,7>, <3,4,5,6> + 4209365739U, // <2,3,6,5>: Cost 3 vsldoi8 LHS, <6,5,7,1> + 3135623992U, // <2,3,6,6>: Cost 2 vsldoi8 LHS, <6,6,6,6> + 3135624014U, // <2,3,6,7>: Cost 2 vsldoi8 LHS, <6,7,0,1> + 3135624095U, // <2,3,6,u>: Cost 2 vsldoi8 LHS, <6,u,0,1> + 3135624186U, // <2,3,7,0>: Cost 2 vsldoi8 LHS, <7,0,1,2> + 4203394133U, // <2,3,7,1>: Cost 3 vsldoi8 <7,1,2,3>, <7,1,2,3> + 4204057766U, // <2,3,7,2>: Cost 3 vsldoi8 <7,2,2,3>, <7,2,2,3> + 4209366243U, // <2,3,7,3>: Cost 3 vsldoi8 LHS, <7,3,0,1> + 3135624550U, // <2,3,7,4>: Cost 2 vsldoi8 LHS, <7,4,5,6> + 4209366454U, // <2,3,7,5>: Cost 3 vsldoi8 LHS, <7,5,5,5> + 4209366492U, // <2,3,7,6>: Cost 3 vsldoi8 LHS, <7,6,0,7> + 3135624812U, // <2,3,7,7>: Cost 2 vsldoi8 LHS, <7,7,7,7> + 3135624834U, // <2,3,7,u>: Cost 2 vsldoi8 LHS, <7,u,1,2> + 2282578838U, // <2,3,u,0>: Cost 2 vmrglw LHS, <1,2,3,0> + 2014107438U, // <2,3,u,1>: Cost 1 vsldoi8 LHS, LHS + 3092494213U, // <2,3,u,2>: Cost 2 vsldoi8 LHS, + 2282579570U, // <2,3,u,3>: Cost 2 vmrglw LHS, <2,2,3,3> + 2282578842U, // <2,3,u,4>: Cost 2 vmrglw LHS, <1,2,3,4> + 2014107802U, // <2,3,u,5>: Cost 1 vsldoi8 LHS, RHS + 3092494544U, // <2,3,u,6>: Cost 2 vsldoi8 LHS, + 2282579898U, // <2,3,u,7>: Cost 2 vmrglw LHS, <2,6,3,7> + 2014108005U, // <2,3,u,u>: Cost 1 vsldoi8 LHS, LHS + 4174200832U, // <2,4,0,0>: Cost 4 vsldoi8 <2,2,2,4>, <0,0,0,0> + 4174200934U, // <2,4,0,1>: Cost 3 vsldoi8 <2,2,2,4>, LHS + 4173537453U, // <2,4,0,2>: Cost 4 vsldoi8 <2,1,2,4>, <0,2,1,2> + 4209369348U, // <2,4,0,3>: Cost 4 vsldoi8 , <0,3,1,u> + 4174201170U, // <2,4,0,4>: Cost 4 vsldoi8 <2,2,2,4>, <0,4,1,5> + 3233393974U, // <2,4,0,5>: Cost 3 vmrghw <2,0,3,0>, RHS + 3249482651U, // <2,4,0,6>: Cost 4 vsldoi12 <4,6,5,2>, <4,0,6,1> + 3263122340U, // <2,4,0,7>: Cost 4 vsldoi12 <7,0,1,2>, <4,0,7,1> + 3233394217U, // <2,4,0,u>: Cost 3 vmrghw <2,0,3,0>, RHS + 3245206455U, // <2,4,1,0>: Cost 4 vsldoi12 <4,0,1,2>, <4,1,0,2> + 3234098146U, // <2,4,1,1>: Cost 4 vmrghw <2,1,3,5>, <4,1,5,0> + 4168893334U, // <2,4,1,2>: Cost 4 vsldoi8 <1,3,2,4>, <1,2,3,0> + 4168893410U, // <2,4,1,3>: Cost 4 vsldoi8 <1,3,2,4>, <1,3,2,4> + 3234098384U, // <2,4,1,4>: Cost 4 vmrghw <2,1,3,5>, <4,4,4,4> + 3234065718U, // <2,4,1,5>: Cost 3 vmrghw <2,1,3,1>, RHS + 4161594584U, // <2,4,1,6>: Cost 4 vsldoi8 <0,1,2,4>, <1,6,2,7> + 4171547942U, // <2,4,1,7>: Cost 4 vsldoi8 <1,7,2,4>, <1,7,2,4> + 3234065961U, // <2,4,1,u>: Cost 3 vmrghw <2,1,3,1>, RHS + 3234663314U, // <2,4,2,0>: Cost 3 vmrghw <2,2,2,2>, <4,0,5,1> + 4173538841U, // <2,4,2,1>: Cost 4 vsldoi8 <2,1,2,4>, <2,1,2,4> + 4174202474U, // <2,4,2,2>: Cost 3 vsldoi8 <2,2,2,4>, <2,2,2,4> + 3368880468U, // <2,4,2,3>: Cost 4 vmrglw <2,2,2,2>, <3,2,4,3> + 3234663632U, // <2,4,2,4>: Cost 3 vmrghw <2,2,2,2>, <4,4,4,4> + 2160921910U, // <2,4,2,5>: Cost 2 vmrghw <2,2,2,2>, RHS + 4174202801U, // <2,4,2,6>: Cost 4 vsldoi8 <2,2,2,4>, <2,6,2,7> + 3368880796U, // <2,4,2,7>: Cost 4 vmrglw <2,2,2,2>, <3,6,4,7> + 2160922153U, // <2,4,2,u>: Cost 2 vmrghw <2,2,2,2>, RHS + 4046094438U, // <2,4,3,0>: Cost 3 vsldoi4 <3,2,4,3>, LHS + 3360923685U, // <2,4,3,1>: Cost 3 vmrglw LHS, <0,0,4,1> + 3235499062U, // <2,4,3,2>: Cost 3 vmrghw <2,3,4,5>, <4,2,5,3> + 4046096724U, // <2,4,3,3>: Cost 3 vsldoi4 <3,2,4,3>, <3,2,4,3> + 2330315984U, // <2,4,3,4>: Cost 2 vmrglw LHS, <4,4,4,4> + 2287183566U, // <2,4,3,5>: Cost 2 vmrglw LHS, <2,3,4,5> + 3235499390U, // <2,4,3,6>: Cost 3 vmrghw <2,3,4,5>, <4,6,5,7> + 4069987512U, // <2,4,3,7>: Cost 3 vsldoi4 <7,2,4,3>, <7,2,4,3> + 2287183569U, // <2,4,3,u>: Cost 2 vmrglw LHS, <2,3,4,u> + 4040130662U, // <2,4,4,0>: Cost 4 vsldoi4 <2,2,4,4>, LHS + 4185484235U, // <2,4,4,1>: Cost 4 vsldoi8 <4,1,2,4>, <4,1,2,4> + 4040132220U, // <2,4,4,2>: Cost 4 vsldoi4 <2,2,4,4>, <2,2,4,4> + 3368896123U, // <2,4,4,3>: Cost 4 vmrglw <2,2,2,4>, <2,2,4,3> + 3263122640U, // <2,4,4,4>: Cost 3 vsldoi12 <7,0,1,2>, <4,4,4,4> + 4174204214U, // <2,4,4,5>: Cost 3 vsldoi8 <2,2,2,4>, RHS + 3236089214U, // <2,4,4,6>: Cost 4 vmrghw <2,4,3,5>, <4,6,5,7> + 3263122668U, // <2,4,4,7>: Cost 4 vsldoi12 <7,0,1,2>, <4,4,7,5> + 4174204457U, // <2,4,4,u>: Cost 3 vsldoi8 <2,2,2,4>, RHS + 4040138854U, // <2,4,5,0>: Cost 3 vsldoi4 <2,2,4,5>, LHS + 4034167716U, // <2,4,5,1>: Cost 3 vsldoi4 <1,2,4,5>, <1,2,4,5> + 4040140413U, // <2,4,5,2>: Cost 3 vsldoi4 <2,2,4,5>, <2,2,4,5> + 4075972821U, // <2,4,5,3>: Cost 3 vsldoi4 , <3,0,u,2> + 4040142134U, // <2,4,5,4>: Cost 3 vsldoi4 <2,2,4,5>, RHS + 3236760886U, // <2,4,5,5>: Cost 3 vmrghw <2,5,3,6>, RHS + 3234663734U, // <2,4,5,6>: Cost 2 vsldoi12 <2,2,2,2>, RHS + 3263122744U, // <2,4,5,7>: Cost 4 vsldoi12 <7,0,1,2>, <4,5,7,0> + 3234663752U, // <2,4,5,u>: Cost 2 vsldoi12 <2,2,2,2>, RHS + 3237432210U, // <2,4,6,0>: Cost 3 vmrghw <2,6,3,7>, <4,0,5,1> + 3237432266U, // <2,4,6,1>: Cost 4 vmrghw <2,6,3,7>, <4,1,2,3> + 3237432377U, // <2,4,6,2>: Cost 3 vmrghw <2,6,3,7>, <4,2,5,6> + 3237432459U, // <2,4,6,3>: Cost 4 vmrghw <2,6,3,7>, <4,3,5,7> + 3237432528U, // <2,4,6,4>: Cost 3 vmrghw <2,6,3,7>, <4,4,4,4> + 2163690806U, // <2,4,6,5>: Cost 2 vmrghw <2,6,3,7>, RHS + 3237432702U, // <2,4,6,6>: Cost 4 vmrghw <2,6,3,7>, <4,6,5,7> + 4201411427U, // <2,4,6,7>: Cost 4 vsldoi8 <6,7,2,4>, <6,7,2,4> + 2163691049U, // <2,4,6,u>: Cost 2 vmrghw <2,6,3,7>, RHS + 4209374202U, // <2,4,7,0>: Cost 4 vsldoi8 , <7,0,1,2> + 3249851814U, // <2,4,7,1>: Cost 4 vsldoi12 <4,7,1,2>, <4,7,1,2> + 4204065959U, // <2,4,7,2>: Cost 4 vsldoi8 <7,2,2,4>, <7,2,2,4> + 4204729592U, // <2,4,7,3>: Cost 4 vsldoi8 <7,3,2,4>, <7,3,2,4> + 3401436368U, // <2,4,7,4>: Cost 4 vmrglw <7,6,2,7>, <4,4,4,4> + 3263122888U, // <2,4,7,5>: Cost 3 vsldoi12 <7,0,1,2>, <4,7,5,0> + 4206720491U, // <2,4,7,6>: Cost 4 vsldoi8 <7,6,2,4>, <7,6,2,4> + 3263122906U, // <2,4,7,7>: Cost 4 vsldoi12 <7,0,1,2>, <4,7,7,0> + 3263122915U, // <2,4,7,u>: Cost 3 vsldoi12 <7,0,1,2>, <4,7,u,0> + 4040163430U, // <2,4,u,0>: Cost 3 vsldoi4 <2,2,4,u>, LHS + 3356321968U, // <2,4,u,1>: Cost 3 vmrglw LHS, <3,0,4,1> + 4040164992U, // <2,4,u,2>: Cost 3 vsldoi4 <2,2,4,u>, <2,2,4,u> + 4046137689U, // <2,4,u,3>: Cost 3 vsldoi4 <3,2,4,u>, <3,2,4,u> + 2330356944U, // <2,4,u,4>: Cost 2 vmrglw LHS, <4,4,4,4> + 2282579662U, // <2,4,u,5>: Cost 2 vmrglw LHS, <2,3,4,5> + 3234663977U, // <2,4,u,6>: Cost 2 vsldoi12 <2,2,2,2>, RHS + 4070028477U, // <2,4,u,7>: Cost 3 vsldoi4 <7,2,4,u>, <7,2,4,u> + 2282579665U, // <2,4,u,u>: Cost 2 vmrglw LHS, <2,3,4,u> + 4169564160U, // <2,5,0,0>: Cost 4 vsldoi8 <1,4,2,5>, <0,0,0,0> + 4169564262U, // <2,5,0,1>: Cost 3 vsldoi8 <1,4,2,5>, LHS + 4163592365U, // <2,5,0,2>: Cost 4 vsldoi8 <0,4,2,5>, <0,2,1,2> + 3239235160U, // <2,5,0,3>: Cost 4 vsldoi12 <3,0,1,2>, <5,0,3,0> + 4163592539U, // <2,5,0,4>: Cost 4 vsldoi8 <0,4,2,5>, <0,4,2,5> + 3263123051U, // <2,5,0,5>: Cost 4 vsldoi12 <7,0,1,2>, <5,0,5,1> + 3263123060U, // <2,5,0,6>: Cost 4 vsldoi12 <7,0,1,2>, <5,0,6,1> + 3263123068U, // <2,5,0,7>: Cost 4 vsldoi12 <7,0,1,2>, <5,0,7,0> + 4169564829U, // <2,5,0,u>: Cost 3 vsldoi8 <1,4,2,5>, LHS + 4169564908U, // <2,5,1,0>: Cost 4 vsldoi8 <1,4,2,5>, <1,0,2,1> + 4169564980U, // <2,5,1,1>: Cost 4 vsldoi8 <1,4,2,5>, <1,1,1,1> + 4169565078U, // <2,5,1,2>: Cost 3 vsldoi8 <1,4,2,5>, <1,2,3,0> + 3384798262U, // <2,5,1,3>: Cost 4 vmrglw <4,u,2,1>, <4,2,5,3> + 4169565236U, // <2,5,1,4>: Cost 3 vsldoi8 <1,4,2,5>, <1,4,2,5> + 3234099204U, // <2,5,1,5>: Cost 4 vmrghw <2,1,3,5>, <5,5,5,5> + 3366879607U, // <2,5,1,6>: Cost 4 vmrglw <1,u,2,1>, <0,4,5,6> + 3263123149U, // <2,5,1,7>: Cost 4 vsldoi12 <7,0,1,2>, <5,1,7,0> + 4172219768U, // <2,5,1,u>: Cost 3 vsldoi8 <1,u,2,5>, <1,u,2,5> + 4052131942U, // <2,5,2,0>: Cost 3 vsldoi4 <4,2,5,2>, LHS + 3368881042U, // <2,5,2,1>: Cost 3 vmrglw <2,2,2,2>, <4,0,5,1> + 4175537768U, // <2,5,2,2>: Cost 3 vsldoi8 <2,4,2,5>, <2,2,2,2> + 4169565862U, // <2,5,2,3>: Cost 4 vsldoi8 <1,4,2,5>, <2,3,0,1> + 4175537933U, // <2,5,2,4>: Cost 3 vsldoi8 <2,4,2,5>, <2,4,2,5> + 3234664452U, // <2,5,2,5>: Cost 3 vmrghw <2,2,2,2>, <5,5,5,5> + 3368880642U, // <2,5,2,6>: Cost 3 vmrglw <2,2,2,2>, <3,4,5,6> + 3368879347U, // <2,5,2,7>: Cost 4 vmrglw <2,2,2,2>, <1,6,5,7> + 3368880644U, // <2,5,2,u>: Cost 3 vmrglw <2,2,2,2>, <3,4,5,u> + 3360926690U, // <2,5,3,0>: Cost 3 vmrglw LHS, <4,1,5,0> + 2330315666U, // <2,5,3,1>: Cost 2 vmrglw LHS, <4,0,5,1> + 4052141774U, // <2,5,3,2>: Cost 3 vsldoi4 <4,2,5,3>, <2,3,4,5> + 3360924587U, // <2,5,3,3>: Cost 3 vmrglw LHS, <1,2,5,3> + 3360926694U, // <2,5,3,4>: Cost 3 vmrglw LHS, <4,1,5,4> + 2330315994U, // <2,5,3,5>: Cost 2 vmrglw LHS, <4,4,5,5> + 2287184386U, // <2,5,3,6>: Cost 2 vmrglw LHS, <3,4,5,6> + 3360924915U, // <2,5,3,7>: Cost 3 vmrglw LHS, <1,6,5,7> + 2287184388U, // <2,5,3,u>: Cost 2 vmrglw LHS, <3,4,5,u> + 4052148326U, // <2,5,4,0>: Cost 4 vsldoi4 <4,2,5,4>, LHS + 4052149142U, // <2,5,4,1>: Cost 4 vsldoi4 <4,2,5,4>, <1,2,3,0> + 4169567283U, // <2,5,4,2>: Cost 4 vsldoi8 <1,4,2,5>, <4,2,5,0> + 3368895403U, // <2,5,4,3>: Cost 5 vmrglw <2,2,2,4>, <1,2,5,3> + 4052151351U, // <2,5,4,4>: Cost 4 vsldoi4 <4,2,5,4>, <4,2,5,4> + 4169567542U, // <2,5,4,5>: Cost 3 vsldoi8 <1,4,2,5>, RHS + 3363588610U, // <2,5,4,6>: Cost 4 vmrglw <1,3,2,4>, <3,4,5,6> + 3368895731U, // <2,5,4,7>: Cost 5 vmrglw <2,2,2,4>, <1,6,5,7> + 4169567785U, // <2,5,4,u>: Cost 3 vsldoi8 <1,4,2,5>, RHS + 4040212582U, // <2,5,5,0>: Cost 4 vsldoi4 <2,2,5,5>, LHS + 4040213398U, // <2,5,5,1>: Cost 4 vsldoi4 <2,2,5,5>, <1,2,3,0> + 4040214150U, // <2,5,5,2>: Cost 4 vsldoi4 <2,2,5,5>, <2,2,5,5> + 3364259460U, // <2,5,5,3>: Cost 4 vmrglw <1,4,2,5>, <2,2,5,3> + 4040215862U, // <2,5,5,4>: Cost 4 vsldoi4 <2,2,5,5>, RHS + 3263123460U, // <2,5,5,5>: Cost 3 vsldoi12 <7,0,1,2>, <5,5,5,5> + 3364258167U, // <2,5,5,6>: Cost 4 vmrglw <1,4,2,5>, <0,4,5,6> + 3263123473U, // <2,5,5,7>: Cost 4 vsldoi12 <7,0,1,2>, <5,5,7,0> + 3263123460U, // <2,5,5,u>: Cost 3 vsldoi12 <7,0,1,2>, <5,5,5,5> + 4052164710U, // <2,5,6,0>: Cost 3 vsldoi4 <4,2,5,6>, LHS + 3386166810U, // <2,5,6,1>: Cost 4 vmrglw <5,1,2,6>, <4,u,5,1> + 4199428602U, // <2,5,6,2>: Cost 3 vsldoi8 <6,4,2,5>, <6,2,7,3> + 3244544066U, // <2,5,6,3>: Cost 4 vsldoi12 <3,u,1,2>, <5,6,3,4> + 4199428721U, // <2,5,6,4>: Cost 3 vsldoi8 <6,4,2,5>, <6,4,2,5> + 3237433348U, // <2,5,6,5>: Cost 3 vmrghw <2,6,3,7>, <5,5,5,5> + 3237433442U, // <2,5,6,6>: Cost 3 vmrghw <2,6,3,7>, <5,6,7,0> + 3255603300U, // <2,5,6,7>: Cost 3 vsldoi12 <5,6,7,2>, <5,6,7,2> + 3255677037U, // <2,5,6,u>: Cost 3 vsldoi12 <5,6,u,2>, <5,6,u,2> + 4199429114U, // <2,5,7,0>: Cost 4 vsldoi8 <6,4,2,5>, <7,0,1,2> + 4203410519U, // <2,5,7,1>: Cost 4 vsldoi8 <7,1,2,5>, <7,1,2,5> + 3249483913U, // <2,5,7,2>: Cost 4 vsldoi12 <4,6,5,2>, <5,7,2,3> + 4199429402U, // <2,5,7,3>: Cost 4 vsldoi8 <6,4,2,5>, <7,3,6,2> + 4199429478U, // <2,5,7,4>: Cost 4 vsldoi8 <6,4,2,5>, <7,4,5,6> + 4206065051U, // <2,5,7,5>: Cost 4 vsldoi8 <7,5,2,5>, <7,5,2,5> + 3371575081U, // <2,5,7,6>: Cost 4 vmrglw <2,6,2,7>, <2,4,5,6> + 4199429700U, // <2,5,7,7>: Cost 4 vsldoi8 <6,4,2,5>, <7,7,3,3> + 3371575083U, // <2,5,7,u>: Cost 4 vmrglw <2,6,2,7>, <2,4,5,u> + 3360967650U, // <2,5,u,0>: Cost 3 vmrglw LHS, <4,1,5,0> + 2330356626U, // <2,5,u,1>: Cost 2 vmrglw LHS, <4,0,5,1> + 4052182734U, // <2,5,u,2>: Cost 3 vsldoi4 <4,2,5,u>, <2,3,4,5> + 3360965547U, // <2,5,u,3>: Cost 3 vmrglw LHS, <1,2,5,3> + 3360967654U, // <2,5,u,4>: Cost 3 vmrglw LHS, <4,1,5,4> + 2330356954U, // <2,5,u,5>: Cost 2 vmrglw LHS, <4,4,5,5> + 2282580482U, // <2,5,u,6>: Cost 2 vmrglw LHS, <3,4,5,6> + 3360965875U, // <2,5,u,7>: Cost 3 vmrglw LHS, <1,6,5,7> + 2282580484U, // <2,5,u,u>: Cost 2 vmrglw LHS, <3,4,5,u> + 4174880768U, // <2,6,0,0>: Cost 4 vsldoi8 <2,3,2,6>, <0,0,0,0> + 4174880870U, // <2,6,0,1>: Cost 3 vsldoi8 <2,3,2,6>, LHS + 4162273466U, // <2,6,0,2>: Cost 4 vsldoi8 <0,2,2,6>, <0,2,2,6> + 4046219619U, // <2,6,0,3>: Cost 4 vsldoi4 <3,2,6,0>, <3,2,6,0> + 4170236242U, // <2,6,0,4>: Cost 4 vsldoi8 <1,5,2,6>, <0,4,1,5> + 3378153265U, // <2,6,0,5>: Cost 5 vmrglw <3,7,2,0>, <2,4,6,5> + 3261206861U, // <2,6,0,6>: Cost 4 vsldoi12 <6,6,2,2>, <6,0,6,1> + 3404033334U, // <2,6,0,7>: Cost 3 vmrglw , RHS + 4174881437U, // <2,6,0,u>: Cost 3 vsldoi8 <2,3,2,6>, LHS + 4070113382U, // <2,6,1,0>: Cost 4 vsldoi4 <7,2,6,1>, LHS + 4167582530U, // <2,6,1,1>: Cost 4 vsldoi8 <1,1,2,6>, <1,1,2,6> + 4174881686U, // <2,6,1,2>: Cost 4 vsldoi8 <2,3,2,6>, <1,2,3,0> + 4070115478U, // <2,6,1,3>: Cost 4 vsldoi4 <7,2,6,1>, <3,0,1,2> + 4070116662U, // <2,6,1,4>: Cost 4 vsldoi4 <7,2,6,1>, RHS + 4170237062U, // <2,6,1,5>: Cost 4 vsldoi8 <1,5,2,6>, <1,5,2,6> + 4170900695U, // <2,6,1,6>: Cost 4 vsldoi8 <1,6,2,6>, <1,6,2,6> + 3366882614U, // <2,6,1,7>: Cost 3 vmrglw <1,u,2,1>, RHS + 3366882615U, // <2,6,1,u>: Cost 3 vmrglw <1,u,2,1>, RHS + 4040261734U, // <2,6,2,0>: Cost 4 vsldoi4 <2,2,6,2>, LHS + 3395424589U, // <2,6,2,1>: Cost 4 vmrglw <6,6,2,2>, <6,0,6,1> + 3234664953U, // <2,6,2,2>: Cost 3 vmrghw <2,2,2,2>, <6,2,7,2> + 4174882493U, // <2,6,2,3>: Cost 3 vsldoi8 <2,3,2,6>, <2,3,2,6> + 4040265014U, // <2,6,2,4>: Cost 4 vsldoi4 <2,2,6,2>, RHS + 4176209759U, // <2,6,2,5>: Cost 4 vsldoi8 <2,5,2,6>, <2,5,2,6> + 4174882746U, // <2,6,2,6>: Cost 3 vsldoi8 <2,3,2,6>, <2,6,3,7> + 2295139638U, // <2,6,2,7>: Cost 2 vmrglw <2,2,2,2>, RHS + 2295139639U, // <2,6,2,u>: Cost 2 vmrglw <2,2,2,2>, RHS + 4046241894U, // <2,6,3,0>: Cost 3 vsldoi4 <3,2,6,3>, LHS + 3404056041U, // <2,6,3,1>: Cost 3 vmrglw LHS, <2,0,6,1> + 4046243770U, // <2,6,3,2>: Cost 3 vsldoi4 <3,2,6,3>, <2,6,3,7> + 3360926054U, // <2,6,3,3>: Cost 3 vmrglw LHS, <3,2,6,3> + 4046245174U, // <2,6,3,4>: Cost 3 vsldoi4 <3,2,6,3>, RHS + 4058189592U, // <2,6,3,5>: Cost 3 vsldoi4 <5,2,6,3>, <5,2,6,3> + 2330317624U, // <2,6,3,6>: Cost 2 vmrglw LHS, <6,6,6,6> + 1208798518U, // <2,6,3,7>: Cost 1 vmrglw LHS, RHS + 1208798519U, // <2,6,3,u>: Cost 1 vmrglw LHS, RHS + 4046250086U, // <2,6,4,0>: Cost 4 vsldoi4 <3,2,6,4>, LHS + 4034306997U, // <2,6,4,1>: Cost 5 vsldoi4 <1,2,6,4>, <1,2,6,4> + 4046251709U, // <2,6,4,2>: Cost 4 vsldoi4 <3,2,6,4>, <2,3,2,6> + 4046252391U, // <2,6,4,3>: Cost 4 vsldoi4 <3,2,6,4>, <3,2,6,4> + 4046253366U, // <2,6,4,4>: Cost 4 vsldoi4 <3,2,6,4>, RHS + 4174884150U, // <2,6,4,5>: Cost 3 vsldoi8 <2,3,2,6>, RHS + 4199435641U, // <2,6,4,6>: Cost 4 vsldoi8 <6,4,2,6>, <4,6,5,2> + 3368897846U, // <2,6,4,7>: Cost 3 vmrglw <2,2,2,4>, RHS + 3368897847U, // <2,6,4,u>: Cost 3 vmrglw <2,2,2,4>, RHS + 3236761889U, // <2,6,5,0>: Cost 4 vmrghw <2,5,3,6>, <6,0,1,2> + 4191473318U, // <2,6,5,1>: Cost 4 vsldoi8 <5,1,2,6>, <5,1,2,6> + 4182183704U, // <2,6,5,2>: Cost 4 vsldoi8 <3,5,2,6>, <5,2,6,3> + 3236762162U, // <2,6,5,3>: Cost 4 vmrghw <2,5,3,6>, <6,3,4,5> + 3236762253U, // <2,6,5,4>: Cost 4 vmrghw <2,5,3,6>, <6,4,5,6> + 4194127850U, // <2,6,5,5>: Cost 4 vsldoi8 <5,5,2,6>, <5,5,2,6> + 4194791483U, // <2,6,5,6>: Cost 4 vsldoi8 <5,6,2,6>, <5,6,2,6> + 3364261174U, // <2,6,5,7>: Cost 3 vmrglw <1,4,2,5>, RHS + 3364261175U, // <2,6,5,u>: Cost 3 vmrglw <1,4,2,5>, RHS + 4040294502U, // <2,6,6,0>: Cost 3 vsldoi4 <2,2,6,6>, LHS + 3372893673U, // <2,6,6,1>: Cost 4 vmrglw <2,u,2,6>, <2,0,6,1> + 3261207312U, // <2,6,6,2>: Cost 3 vsldoi12 <6,6,2,2>, <6,6,2,2> + 3237433928U, // <2,6,6,3>: Cost 3 vmrghw <2,6,3,7>, <6,3,7,0> + 4040297782U, // <2,6,6,4>: Cost 3 vsldoi4 <2,2,6,6>, RHS + 3372894001U, // <2,6,6,5>: Cost 4 vmrglw <2,u,2,6>, <2,4,6,5> + 3263124280U, // <2,6,6,6>: Cost 3 vsldoi12 <7,0,1,2>, <6,6,6,6> + 3369577782U, // <2,6,6,7>: Cost 3 vmrglw <2,3,2,6>, RHS + 3369577783U, // <2,6,6,u>: Cost 3 vmrglw <2,3,2,6>, RHS + 3263124302U, // <2,6,7,0>: Cost 3 vsldoi12 <7,0,1,2>, <6,7,0,1> + 3261797208U, // <2,6,7,1>: Cost 3 vsldoi12 <6,7,1,2>, <6,7,1,2> + 3261870945U, // <2,6,7,2>: Cost 3 vsldoi12 <6,7,2,2>, <6,7,2,2> + 3239236456U, // <2,6,7,3>: Cost 3 vsldoi12 <3,0,1,2>, <6,7,3,0> + 3263124342U, // <2,6,7,4>: Cost 3 vsldoi12 <7,0,1,2>, <6,7,4,5> + 3371575089U, // <2,6,7,5>: Cost 4 vmrglw <2,6,2,7>, <2,4,6,5> + 3262165893U, // <2,6,7,6>: Cost 3 vsldoi12 <6,7,6,2>, <6,7,6,2> + 3371576630U, // <2,6,7,7>: Cost 3 vmrglw <2,6,2,7>, RHS + 3371576631U, // <2,6,7,u>: Cost 3 vmrglw <2,6,2,7>, RHS + 4046282854U, // <2,6,u,0>: Cost 3 vsldoi4 <3,2,6,u>, LHS + 4174886702U, // <2,6,u,1>: Cost 3 vsldoi8 <2,3,2,6>, LHS + 4046284775U, // <2,6,u,2>: Cost 3 vsldoi4 <3,2,6,u>, <2,6,u,7> + 3356322150U, // <2,6,u,3>: Cost 3 vmrglw LHS, <3,2,6,3> + 4046286134U, // <2,6,u,4>: Cost 3 vsldoi4 <3,2,6,u>, RHS + 4174887066U, // <2,6,u,5>: Cost 3 vsldoi8 <2,3,2,6>, RHS + 2330358584U, // <2,6,u,6>: Cost 2 vmrglw LHS, <6,6,6,6> + 1208839478U, // <2,6,u,7>: Cost 1 vmrglw LHS, RHS + 1208839479U, // <2,6,u,u>: Cost 1 vmrglw LHS, RHS + 4076150886U, // <2,7,0,0>: Cost 3 vsldoi4 , LHS + 3263124474U, // <2,7,0,1>: Cost 2 vsldoi12 <7,0,1,2>, <7,0,1,2> + 4170907821U, // <2,7,0,2>: Cost 4 vsldoi8 <1,6,2,7>, <0,2,1,2> + 3393417722U, // <2,7,0,3>: Cost 4 vmrglw <6,3,2,0>, <6,2,7,3> + 4076154166U, // <2,7,0,4>: Cost 3 vsldoi4 , RHS + 3263124514U, // <2,7,0,5>: Cost 4 vsldoi12 <7,0,1,2>, <7,0,5,6> + 4064211447U, // <2,7,0,6>: Cost 4 vsldoi4 <6,2,7,0>, <6,2,7,0> + 4076155961U, // <2,7,0,7>: Cost 3 vsldoi4 , <7,0,u,2> + 3263640633U, // <2,7,0,u>: Cost 2 vsldoi12 <7,0,u,2>, <7,0,u,2> + 4064215142U, // <2,7,1,0>: Cost 4 vsldoi4 <6,2,7,1>, LHS + 4176880436U, // <2,7,1,1>: Cost 4 vsldoi8 <2,6,2,7>, <1,1,1,1> + 4176880534U, // <2,7,1,2>: Cost 4 vsldoi8 <2,6,2,7>, <1,2,3,0> + 3396743674U, // <2,7,1,3>: Cost 3 vmrglw <6,u,2,1>, <6,2,7,3> + 4064218422U, // <2,7,1,4>: Cost 4 vsldoi4 <6,2,7,1>, RHS + 4176880751U, // <2,7,1,5>: Cost 5 vsldoi8 <2,6,2,7>, <1,5,0,1> + 4170908888U, // <2,7,1,6>: Cost 3 vsldoi8 <1,6,2,7>, <1,6,2,7> + 3396744002U, // <2,7,1,7>: Cost 4 vmrglw <6,u,2,1>, <6,6,7,7> + 3396743674U, // <2,7,1,u>: Cost 3 vmrglw <6,u,2,1>, <6,2,7,3> + 4064223334U, // <2,7,2,0>: Cost 3 vsldoi4 <6,2,7,2>, LHS + 4064224052U, // <2,7,2,1>: Cost 4 vsldoi4 <6,2,7,2>, <1,1,1,1> + 4176881256U, // <2,7,2,2>: Cost 3 vsldoi8 <2,6,2,7>, <2,2,2,2> + 3395424762U, // <2,7,2,3>: Cost 3 vmrglw <6,6,2,2>, <6,2,7,3> + 4064226614U, // <2,7,2,4>: Cost 3 vsldoi4 <6,2,7,2>, RHS + 3255604420U, // <2,7,2,5>: Cost 4 vsldoi12 <5,6,7,2>, <7,2,5,6> + 4176881585U, // <2,7,2,6>: Cost 3 vsldoi8 <2,6,2,7>, <2,6,2,7> + 3234666092U, // <2,7,2,7>: Cost 3 vmrghw <2,2,2,2>, <7,7,7,7> + 4178208851U, // <2,7,2,u>: Cost 3 vsldoi8 <2,u,2,7>, <2,u,2,7> + 2990489702U, // <2,7,3,0>: Cost 2 vsldoi4 <6,2,7,3>, LHS + 4064232244U, // <2,7,3,1>: Cost 3 vsldoi4 <6,2,7,3>, <1,1,1,1> + 4046317498U, // <2,7,3,2>: Cost 3 vsldoi4 <3,2,7,3>, <2,6,3,7> + 2330317306U, // <2,7,3,3>: Cost 2 vmrglw LHS, <6,2,7,3> + 2990492982U, // <2,7,3,4>: Cost 2 vsldoi4 <6,2,7,3>, RHS + 4064235524U, // <2,7,3,5>: Cost 3 vsldoi4 <6,2,7,3>, <5,5,5,5> + 2990494202U, // <2,7,3,6>: Cost 2 vsldoi4 <6,2,7,3>, <6,2,7,3> + 2330317634U, // <2,7,3,7>: Cost 2 vmrglw LHS, <6,6,7,7> + 2990495534U, // <2,7,3,u>: Cost 2 vsldoi4 <6,2,7,3>, LHS + 4064239718U, // <2,7,4,0>: Cost 4 vsldoi4 <6,2,7,4>, LHS + 3265779006U, // <2,7,4,1>: Cost 4 vsldoi12 <7,4,1,2>, <7,4,1,2> + 4064241256U, // <2,7,4,2>: Cost 4 vsldoi4 <6,2,7,4>, <2,2,2,2> + 3393450490U, // <2,7,4,3>: Cost 4 vmrglw <6,3,2,4>, <6,2,7,3> + 4064242998U, // <2,7,4,4>: Cost 4 vsldoi4 <6,2,7,4>, RHS + 4176882998U, // <2,7,4,5>: Cost 3 vsldoi8 <2,6,2,7>, RHS + 4064244219U, // <2,7,4,6>: Cost 4 vsldoi4 <6,2,7,4>, <6,2,7,4> + 3263124850U, // <2,7,4,7>: Cost 4 vsldoi12 <7,0,1,2>, <7,4,7,0> + 4176883241U, // <2,7,4,u>: Cost 3 vsldoi8 <2,6,2,7>, RHS + 3251180933U, // <2,7,5,0>: Cost 4 vsldoi12 <5,0,1,2>, <7,5,0,1> + 4064248726U, // <2,7,5,1>: Cost 4 vsldoi4 <6,2,7,5>, <1,2,3,0> + 3370233956U, // <2,7,5,2>: Cost 4 vmrglw <2,4,2,5>, <5,6,7,2> + 3394122234U, // <2,7,5,3>: Cost 3 vmrglw <6,4,2,5>, <6,2,7,3> + 4064251190U, // <2,7,5,4>: Cost 4 vsldoi4 <6,2,7,5>, RHS + 3263124918U, // <2,7,5,5>: Cost 4 vsldoi12 <7,0,1,2>, <7,5,5,5> + 4194799676U, // <2,7,5,6>: Cost 4 vsldoi8 <5,6,2,7>, <5,6,2,7> + 3394122562U, // <2,7,5,7>: Cost 4 vmrglw <6,4,2,5>, <6,6,7,7> + 3394122234U, // <2,7,5,u>: Cost 3 vmrglw <6,4,2,5>, <6,2,7,3> + 3237434362U, // <2,7,6,0>: Cost 3 vmrghw <2,6,3,7>, <7,0,1,2> + 4170912168U, // <2,7,6,1>: Cost 4 vsldoi8 <1,6,2,7>, <6,1,7,2> + 4206744058U, // <2,7,6,2>: Cost 3 vsldoi8 <7,6,2,7>, <6,2,7,3> + 3372894575U, // <2,7,6,3>: Cost 4 vmrglw <2,u,2,6>, <3,2,7,3> + 3237434726U, // <2,7,6,4>: Cost 3 vmrghw <2,6,3,7>, <7,4,5,6> + 3237434806U, // <2,7,6,5>: Cost 4 vmrghw <2,6,3,7>, <7,5,5,5> + 4064260605U, // <2,7,6,6>: Cost 4 vsldoi4 <6,2,7,6>, <6,2,7,6> + 3237434988U, // <2,7,6,7>: Cost 3 vmrghw <2,6,3,7>, <7,7,7,7> + 4206744058U, // <2,7,6,u>: Cost 3 vsldoi8 <7,6,2,7>, <6,2,7,3> + 3263125031U, // <2,7,7,0>: Cost 3 vsldoi12 <7,0,1,2>, <7,7,0,1> + 4064265432U, // <2,7,7,1>: Cost 4 vsldoi4 <6,2,7,7>, <1,6,2,7> + 3371574933U, // <2,7,7,2>: Cost 4 vmrglw <2,6,2,7>, <2,2,7,2> + 3401437690U, // <2,7,7,3>: Cost 3 vmrglw <7,6,2,7>, <6,2,7,3> + 4064267574U, // <2,7,7,4>: Cost 4 vsldoi4 <6,2,7,7>, RHS + 3371574855U, // <2,7,7,5>: Cost 5 vmrglw <2,6,2,7>, <2,1,7,5> + 4206745070U, // <2,7,7,6>: Cost 3 vsldoi8 <7,6,2,7>, <7,6,2,7> + 3263125100U, // <2,7,7,7>: Cost 3 vsldoi12 <7,0,1,2>, <7,7,7,7> + 3268433519U, // <2,7,7,u>: Cost 3 vsldoi12 <7,u,1,2>, <7,7,u,1> + 2990530662U, // <2,7,u,0>: Cost 2 vsldoi4 <6,2,7,u>, LHS + 3268433538U, // <2,7,u,1>: Cost 2 vsldoi12 <7,u,1,2>, <7,u,1,2> + 4046358458U, // <2,7,u,2>: Cost 3 vsldoi4 <3,2,7,u>, <2,6,3,7> + 2330358266U, // <2,7,u,3>: Cost 2 vmrglw LHS, <6,2,7,3> + 2990533942U, // <2,7,u,4>: Cost 2 vsldoi4 <6,2,7,u>, RHS + 4176885914U, // <2,7,u,5>: Cost 3 vsldoi8 <2,6,2,7>, RHS + 2990535167U, // <2,7,u,6>: Cost 2 vsldoi4 <6,2,7,u>, <6,2,7,u> + 2330358594U, // <2,7,u,7>: Cost 2 vmrglw LHS, <6,6,7,7> + 2990536494U, // <2,7,u,u>: Cost 2 vsldoi4 <6,2,7,u>, LHS + 3087884288U, // <2,u,0,0>: Cost 2 vsldoi8 LHS, <0,0,0,0> + 2014142571U, // <2,u,0,1>: Cost 1 vsldoi8 LHS, LHS + 4161626285U, // <2,u,0,2>: Cost 3 vsldoi8 LHS, <0,2,1,2> + 4161626364U, // <2,u,0,3>: Cost 3 vsldoi8 LHS, <0,3,1,0> + 3087884626U, // <2,u,0,4>: Cost 2 vsldoi8 LHS, <0,4,1,5> + 3233396890U, // <2,u,0,5>: Cost 3 vmrghw <2,0,3,0>, RHS + 4209402358U, // <2,u,0,6>: Cost 3 vsldoi8 LHS, <0,6,1,7> + 4070257881U, // <2,u,0,7>: Cost 3 vsldoi4 <7,2,u,0>, <7,2,u,0> + 2014143133U, // <2,u,0,u>: Cost 1 vsldoi8 LHS, LHS + 4166271716U, // <2,u,1,0>: Cost 3 vsldoi8 LHS, <1,0,1,2> + 3087885108U, // <2,u,1,1>: Cost 2 vsldoi8 LHS, <1,1,1,1> + 3087885206U, // <2,u,1,2>: Cost 2 vsldoi8 LHS, <1,2,3,0> + 3366879388U, // <2,u,1,3>: Cost 3 vmrglw <1,u,2,1>, LHS + 4166272080U, // <2,u,1,4>: Cost 3 vsldoi8 LHS, <1,4,5,6> + 4166272111U, // <2,u,1,5>: Cost 3 vsldoi8 LHS, <1,5,0,1> + 4166272207U, // <2,u,1,6>: Cost 3 vsldoi8 LHS, <1,6,1,7> + 3366882632U, // <2,u,1,7>: Cost 3 vmrglw <1,u,2,1>, RHS + 3092530556U, // <2,u,1,u>: Cost 2 vsldoi8 LHS, <1,u,3,0> + 2966224998U, // <2,u,2,0>: Cost 2 vsldoi4 <2,2,2,2>, LHS + 2160924462U, // <2,u,2,1>: Cost 2 vmrghw <2,2,2,2>, LHS + 1611448422U, // <2,u,2,2>: Cost 1 vspltisw2 LHS + 3087885990U, // <2,u,2,3>: Cost 2 vsldoi8 LHS, <2,3,0,1> + 2966228278U, // <2,u,2,4>: Cost 2 vsldoi4 <2,2,2,2>, RHS + 2160924826U, // <2,u,2,5>: Cost 2 vmrghw <2,2,2,2>, RHS + 3087886266U, // <2,u,2,6>: Cost 2 vsldoi8 LHS, <2,6,3,7> + 2295139656U, // <2,u,2,7>: Cost 2 vmrglw <2,2,2,2>, RHS + 1611448422U, // <2,u,2,u>: Cost 1 vspltisw2 LHS + 3087886486U, // <2,u,3,0>: Cost 2 vsldoi8 LHS, <3,0,1,2> + 2287181897U, // <2,u,3,1>: Cost 2 vmrglw LHS, <0,0,u,1> + 2287184085U, // <2,u,3,2>: Cost 2 vmrglw LHS, <3,0,u,2> + 1208795292U, // <2,u,3,3>: Cost 1 vmrglw LHS, LHS + 3087886850U, // <2,u,3,4>: Cost 2 vsldoi8 LHS, <3,4,5,6> + 2287182225U, // <2,u,3,5>: Cost 2 vmrglw LHS, <0,4,u,5> + 2287184413U, // <2,u,3,6>: Cost 2 vmrglw LHS, <3,4,u,6> + 1208798536U, // <2,u,3,7>: Cost 1 vmrglw LHS, RHS + 1208795297U, // <2,u,3,u>: Cost 1 vmrglw LHS, LHS + 2960711782U, // <2,u,4,0>: Cost 2 vsldoi4 <1,2,u,4>, LHS + 2960712647U, // <2,u,4,1>: Cost 2 vsldoi4 <1,2,u,4>, <1,2,u,4> + 4034455144U, // <2,u,4,2>: Cost 3 vsldoi4 <1,2,u,4>, <2,2,2,2> + 4034455702U, // <2,u,4,3>: Cost 3 vsldoi4 <1,2,u,4>, <3,0,1,2> + 2960715062U, // <2,u,4,4>: Cost 2 vsldoi4 <1,2,u,4>, RHS + 2014145846U, // <2,u,4,5>: Cost 1 vsldoi8 LHS, RHS + 4209405305U, // <2,u,4,6>: Cost 3 vsldoi8 LHS, <4,6,5,2> + 3368897864U, // <2,u,4,7>: Cost 3 vmrglw <2,2,2,4>, RHS + 2014146089U, // <2,u,4,u>: Cost 1 vsldoi8 LHS, RHS + 4166274632U, // <2,u,5,0>: Cost 3 vsldoi8 LHS, <5,0,1,2> + 3236763438U, // <2,u,5,1>: Cost 3 vmrghw <2,5,3,6>, LHS + 4040435361U, // <2,u,5,2>: Cost 3 vsldoi4 <2,2,u,5>, <2,2,u,5> + 3364257948U, // <2,u,5,3>: Cost 3 vmrglw <1,4,2,5>, LHS + 4166274996U, // <2,u,5,4>: Cost 3 vsldoi8 LHS, <5,4,5,6> + 3135664132U, // <2,u,5,5>: Cost 2 vsldoi8 LHS, <5,5,5,5> + 3234666650U, // <2,u,5,6>: Cost 2 vsldoi12 <2,2,2,2>, RHS + 3364261192U, // <2,u,5,7>: Cost 3 vmrglw <1,4,2,5>, RHS + 3234666668U, // <2,u,5,u>: Cost 2 vsldoi12 <2,2,2,2>, RHS + 3237435091U, // <2,u,6,0>: Cost 3 vmrghw <2,6,3,7>, + 2163693358U, // <2,u,6,1>: Cost 2 vmrghw <2,6,3,7>, LHS + 3135664634U, // <2,u,6,2>: Cost 2 vsldoi8 LHS, <6,2,7,3> + 3234666704U, // <2,u,6,3>: Cost 3 vsldoi12 <2,2,2,2>, + 3237435455U, // <2,u,6,4>: Cost 3 vmrghw <2,6,3,7>, + 2163693722U, // <2,u,6,5>: Cost 2 vmrghw <2,6,3,7>, RHS + 3135664952U, // <2,u,6,6>: Cost 2 vsldoi8 LHS, <6,6,6,6> + 3135664974U, // <2,u,6,7>: Cost 2 vsldoi8 LHS, <6,7,0,1> + 2163693925U, // <2,u,6,u>: Cost 2 vmrghw <2,6,3,7>, LHS + 3135665146U, // <2,u,7,0>: Cost 2 vsldoi8 LHS, <7,0,1,2> + 4203435098U, // <2,u,7,1>: Cost 3 vsldoi8 <7,1,2,u>, <7,1,2,u> + 4204098731U, // <2,u,7,2>: Cost 3 vsldoi8 <7,2,2,u>, <7,2,2,u> + 3371573404U, // <2,u,7,3>: Cost 3 vmrglw <2,6,2,7>, LHS + 3135665510U, // <2,u,7,4>: Cost 2 vsldoi8 LHS, <7,4,5,6> + 4209407414U, // <2,u,7,5>: Cost 3 vsldoi8 LHS, <7,5,5,5> + 4206753263U, // <2,u,7,6>: Cost 3 vsldoi8 <7,6,2,u>, <7,6,2,u> + 3135665772U, // <2,u,7,7>: Cost 2 vsldoi8 LHS, <7,7,7,7> + 3135665794U, // <2,u,7,u>: Cost 2 vsldoi8 LHS, <7,u,1,2> + 2287223747U, // <2,u,u,0>: Cost 2 vmrglw LHS, <1,2,u,0> + 2014148398U, // <2,u,u,1>: Cost 1 vsldoi8 LHS, LHS + 1611448422U, // <2,u,u,2>: Cost 1 vspltisw2 LHS + 1208836252U, // <2,u,u,3>: Cost 1 vmrglw LHS, LHS + 2287223751U, // <2,u,u,4>: Cost 2 vmrglw LHS, <1,2,u,4> + 2014148762U, // <2,u,u,5>: Cost 1 vsldoi8 LHS, RHS + 2282580509U, // <2,u,u,6>: Cost 2 vmrglw LHS, <3,4,u,6> + 1208839496U, // <2,u,u,7>: Cost 1 vmrglw LHS, RHS + 1208836257U, // <2,u,u,u>: Cost 1 vmrglw LHS, LHS + 3222061056U, // <3,0,0,0>: Cost 2 vsldoi12 LHS, <0,0,0,0> + 3222061066U, // <3,0,0,1>: Cost 2 vsldoi12 LHS, <0,0,1,1> + 4040468133U, // <3,0,0,2>: Cost 3 vsldoi4 <2,3,0,0>, <2,3,0,0> + 3362965808U, // <3,0,0,3>: Cost 3 vmrglw <1,2,3,0>, <3,2,0,3> + 3226705957U, // <3,0,0,4>: Cost 3 vsldoi12 LHS, <0,0,4,1> + 3362965729U, // <3,0,0,5>: Cost 4 vmrglw <1,2,3,0>, <3,1,0,5> + 3362966054U, // <3,0,0,6>: Cost 4 vmrglw <1,2,3,0>, <3,5,0,6> + 3362966136U, // <3,0,0,7>: Cost 3 vmrglw <1,2,3,0>, <3,6,0,7> + 3226705993U, // <3,0,0,u>: Cost 2 vsldoi12 LHS, <0,0,u,1> + 2966732902U, // <3,0,1,0>: Cost 2 vsldoi4 <2,3,0,1>, LHS + 3222503515U, // <3,0,1,1>: Cost 3 vsldoi12 LHS, <0,1,1,1> + 1074577510U, // <3,0,1,2>: Cost 1 vsldoi12 LHS, LHS + 4040476820U, // <3,0,1,3>: Cost 3 vsldoi4 <2,3,0,1>, <3,0,1,0> + 2966736182U, // <3,0,1,4>: Cost 2 vsldoi4 <2,3,0,1>, RHS + 4076310532U, // <3,0,1,5>: Cost 3 vsldoi4 , <5,5,5,5> + 3269836942U, // <3,0,1,6>: Cost 3 vsldoi12 LHS, <0,1,6,7> + 4070339811U, // <3,0,1,7>: Cost 3 vsldoi4 <7,3,0,1>, <7,3,0,1> + 1074577564U, // <3,0,1,u>: Cost 1 vsldoi12 LHS, LHS + 4172916173U, // <3,0,2,0>: Cost 3 vsldoi8 <2,0,3,0>, <2,0,3,0> + 3222503597U, // <3,0,2,1>: Cost 3 vsldoi12 LHS, <0,2,1,2> + 4168271464U, // <3,0,2,2>: Cost 3 vsldoi8 <1,2,3,0>, <2,2,2,2> + 4168271526U, // <3,0,2,3>: Cost 3 vsldoi8 <1,2,3,0>, <2,3,0,1> + 3226706119U, // <3,0,2,4>: Cost 4 vsldoi12 LHS, <0,2,4,1> + 4168271720U, // <3,0,2,5>: Cost 4 vsldoi8 <1,2,3,0>, <2,5,3,6> + 4168271802U, // <3,0,2,6>: Cost 3 vsldoi8 <1,2,3,0>, <2,6,3,7> + 4177561604U, // <3,0,2,7>: Cost 3 vsldoi8 <2,7,3,0>, <2,7,3,0> + 3226706156U, // <3,0,2,u>: Cost 3 vsldoi12 LHS, <0,2,u,2> + 4168272022U, // <3,0,3,0>: Cost 3 vsldoi8 <1,2,3,0>, <3,0,1,2> + 2167636070U, // <3,0,3,1>: Cost 2 vmrghw <3,3,3,3>, LHS + 4168272176U, // <3,0,3,2>: Cost 3 vsldoi8 <1,2,3,0>, <3,2,0,3> + 4168272254U, // <3,0,3,3>: Cost 3 vsldoi8 <1,2,3,0>, <3,3,0,0> + 4168272386U, // <3,0,3,4>: Cost 3 vsldoi8 <1,2,3,0>, <3,4,5,6> + 4168272422U, // <3,0,3,5>: Cost 4 vsldoi8 <1,2,3,0>, <3,5,0,6> + 4168272504U, // <3,0,3,6>: Cost 3 vsldoi8 <1,2,3,0>, <3,6,0,7> + 3368962680U, // <3,0,3,7>: Cost 4 vmrglw <2,2,3,3>, <3,6,0,7> + 2167636637U, // <3,0,3,u>: Cost 2 vmrghw <3,3,3,3>, LHS + 3362996224U, // <3,0,4,0>: Cost 3 vmrglw <1,2,3,4>, <0,0,0,0> + 3222061394U, // <3,0,4,1>: Cost 2 vsldoi12 LHS, <0,4,1,5> + 4040500905U, // <3,0,4,2>: Cost 3 vsldoi4 <2,3,0,4>, <2,3,0,4> + 3242213632U, // <3,0,4,3>: Cost 3 vmrghw <3,4,5,6>, <0,3,1,4> + 3226706285U, // <3,0,4,4>: Cost 3 vsldoi12 LHS, <0,4,4,5> + 3094531382U, // <3,0,4,5>: Cost 2 vsldoi8 <1,2,3,0>, RHS + 3242213878U, // <3,0,4,6>: Cost 4 vmrghw <3,4,5,6>, <0,6,1,7> + 3362998904U, // <3,0,4,7>: Cost 4 vmrglw <1,2,3,4>, <3,6,0,7> + 3226706321U, // <3,0,4,u>: Cost 2 vsldoi12 LHS, <0,4,u,5> + 4168273480U, // <3,0,5,0>: Cost 4 vsldoi8 <1,2,3,0>, <5,0,1,2> + 3222061475U, // <3,0,5,1>: Cost 3 vsldoi12 LHS, <0,5,1,5> + 4192161530U, // <3,0,5,2>: Cost 4 vsldoi8 <5,2,3,0>, <5,2,3,0> + 3403486842U, // <3,0,5,3>: Cost 4 vmrglw , <7,u,0,3> + 4168273844U, // <3,0,5,4>: Cost 4 vsldoi8 <1,2,3,0>, <5,4,5,6> + 4210077700U, // <3,0,5,5>: Cost 3 vsldoi8 , <5,5,5,5> + 3269837266U, // <3,0,5,6>: Cost 3 vsldoi12 LHS, <0,5,6,7> + 3269837268U, // <3,0,5,7>: Cost 4 vsldoi12 LHS, <0,5,7,0> + 3269837282U, // <3,0,5,u>: Cost 3 vsldoi12 LHS, <0,5,u,5> + 3222061549U, // <3,0,6,0>: Cost 3 vsldoi12 LHS, <0,6,0,7> + 3243180134U, // <3,0,6,1>: Cost 3 vmrghw <3,6,0,7>, LHS + 4210078202U, // <3,0,6,2>: Cost 3 vsldoi8 , <6,2,7,3> + 3240493576U, // <3,0,6,3>: Cost 4 vsldoi12 <3,2,0,3>, <0,6,3,7> + 3243180370U, // <3,0,6,4>: Cost 4 vmrghw <3,6,0,7>, <0,4,1,5> + 3269837338U, // <3,0,6,5>: Cost 4 vsldoi12 LHS, <0,6,5,7> + 4210078520U, // <3,0,6,6>: Cost 3 vsldoi8 , <6,6,6,6> + 4201452392U, // <3,0,6,7>: Cost 3 vsldoi8 <6,7,3,0>, <6,7,3,0> + 3243180701U, // <3,0,6,u>: Cost 3 vmrghw <3,6,0,7>, LHS + 3371646976U, // <3,0,7,0>: Cost 3 vmrglw <2,6,3,7>, <0,0,0,0> + 3371648678U, // <3,0,7,1>: Cost 3 vmrglw <2,6,3,7>, <2,3,0,1> + 4204106924U, // <3,0,7,2>: Cost 3 vsldoi8 <7,2,3,0>, <7,2,3,0> + 3371649328U, // <3,0,7,3>: Cost 4 vmrglw <2,6,3,7>, <3,2,0,3> + 4210079078U, // <3,0,7,4>: Cost 3 vsldoi8 , <7,4,5,6> + 4070387810U, // <3,0,7,5>: Cost 4 vsldoi4 <7,3,0,7>, <5,6,7,0> + 4201453079U, // <3,0,7,6>: Cost 4 vsldoi8 <6,7,3,0>, <7,6,7,3> + 4210079340U, // <3,0,7,7>: Cost 3 vsldoi8 , <7,7,7,7> + 3371648685U, // <3,0,7,u>: Cost 3 vmrglw <2,6,3,7>, <2,3,0,u> + 2966790246U, // <3,0,u,0>: Cost 2 vsldoi4 <2,3,0,u>, LHS + 3222061714U, // <3,0,u,1>: Cost 2 vsldoi12 LHS, <0,u,1,1> + 1074578077U, // <3,0,u,2>: Cost 1 vsldoi12 LHS, LHS + 4168275900U, // <3,0,u,3>: Cost 3 vsldoi8 <1,2,3,0>, + 2966793526U, // <3,0,u,4>: Cost 2 vsldoi4 <2,3,0,u>, RHS + 3094534298U, // <3,0,u,5>: Cost 2 vsldoi8 <1,2,3,0>, RHS + 4168276176U, // <3,0,u,6>: Cost 3 vsldoi8 <1,2,3,0>, + 4070397162U, // <3,0,u,7>: Cost 3 vsldoi4 <7,3,0,u>, <7,3,0,u> + 1074578131U, // <3,0,u,u>: Cost 1 vsldoi12 LHS, LHS + 4028596476U, // <3,1,0,0>: Cost 3 vsldoi4 <0,3,1,0>, <0,3,1,0> + 3226706660U, // <3,1,0,1>: Cost 3 vsldoi12 LHS, <1,0,1,2> + 3362963548U, // <3,1,0,2>: Cost 3 vmrglw <1,2,3,0>, <0,1,1,2> + 4028598422U, // <3,1,0,3>: Cost 3 vsldoi4 <0,3,1,0>, <3,0,1,2> + 4028599606U, // <3,1,0,4>: Cost 3 vsldoi4 <0,3,1,0>, RHS + 3362963794U, // <3,1,0,5>: Cost 3 vmrglw <1,2,3,0>, <0,4,1,5> + 3239232728U, // <3,1,0,6>: Cost 3 vmrghw <3,0,1,2>, <1,6,2,7> + 3362964687U, // <3,1,0,7>: Cost 4 vmrglw <1,2,3,0>, <1,6,1,7> + 4028602158U, // <3,1,0,u>: Cost 3 vsldoi4 <0,3,1,0>, LHS + 3226706731U, // <3,1,1,0>: Cost 3 vsldoi12 LHS, <1,1,0,1> + 3222061876U, // <3,1,1,1>: Cost 2 vsldoi12 LHS, <1,1,1,1> + 4168278935U, // <3,1,1,2>: Cost 3 vsldoi8 <1,2,3,1>, <1,2,3,1> + 3222651720U, // <3,1,1,3>: Cost 4 vsldoi12 <0,2,1,3>, <1,1,3,3> + 3226706771U, // <3,1,1,4>: Cost 3 vsldoi12 LHS, <1,1,4,5> + 3226706780U, // <3,1,1,5>: Cost 3 vsldoi12 LHS, <1,1,5,5> + 3226706785U, // <3,1,1,6>: Cost 4 vsldoi12 LHS, <1,1,6,1> + 4070413548U, // <3,1,1,7>: Cost 4 vsldoi4 <7,3,1,1>, <7,3,1,1> + 3222061876U, // <3,1,1,u>: Cost 2 vsldoi12 LHS, <1,1,1,1> + 4172924366U, // <3,1,2,0>: Cost 3 vsldoi8 <2,0,3,1>, <2,0,3,1> + 3226706823U, // <3,1,2,1>: Cost 3 vsldoi12 LHS, <1,2,1,3> + 3368290454U, // <3,1,2,2>: Cost 3 vmrglw <2,1,3,2>, <3,0,1,2> + 3222061974U, // <3,1,2,3>: Cost 2 vsldoi12 LHS, <1,2,3,0> + 4040559926U, // <3,1,2,4>: Cost 3 vsldoi4 <2,3,1,2>, RHS + 3226706859U, // <3,1,2,5>: Cost 3 vsldoi12 LHS, <1,2,5,3> + 3226706868U, // <3,1,2,6>: Cost 4 vsldoi12 LHS, <1,2,6,3> + 3269837754U, // <3,1,2,7>: Cost 3 vsldoi12 LHS, <1,2,7,0> + 3222504387U, // <3,1,2,u>: Cost 2 vsldoi12 LHS, <1,2,u,0> + 4028621055U, // <3,1,3,0>: Cost 3 vsldoi4 <0,3,1,3>, <0,3,1,3> + 3368960010U, // <3,1,3,1>: Cost 3 vmrglw <2,2,3,3>, <0,0,1,1> + 3366971542U, // <3,1,3,2>: Cost 3 vmrglw <1,u,3,3>, <3,0,1,2> + 4028623260U, // <3,1,3,3>: Cost 3 vsldoi4 <0,3,1,3>, <3,3,3,3> + 4028624182U, // <3,1,3,4>: Cost 3 vsldoi4 <0,3,1,3>, RHS + 3368960338U, // <3,1,3,5>: Cost 3 vmrglw <2,2,3,3>, <0,4,1,5> + 3226706953U, // <3,1,3,6>: Cost 4 vsldoi12 LHS, <1,3,6,7> + 3368961231U, // <3,1,3,7>: Cost 4 vmrglw <2,2,3,3>, <1,6,1,7> + 4028626734U, // <3,1,3,u>: Cost 3 vsldoi4 <0,3,1,3>, LHS + 4028629248U, // <3,1,4,0>: Cost 3 vsldoi4 <0,3,1,4>, <0,3,1,4> + 3362996234U, // <3,1,4,1>: Cost 3 vmrglw <1,2,3,4>, <0,0,1,1> + 3362998422U, // <3,1,4,2>: Cost 3 vmrglw <1,2,3,4>, <3,0,1,2> + 4028631554U, // <3,1,4,3>: Cost 3 vsldoi4 <0,3,1,4>, <3,4,5,6> + 4028632374U, // <3,1,4,4>: Cost 3 vsldoi4 <0,3,1,4>, RHS + 3226707024U, // <3,1,4,5>: Cost 3 vsldoi12 LHS, <1,4,5,6> + 3362996401U, // <3,1,4,6>: Cost 4 vmrglw <1,2,3,4>, <0,2,1,6> + 3362997455U, // <3,1,4,7>: Cost 4 vmrglw <1,2,3,4>, <1,6,1,7> + 4028634926U, // <3,1,4,u>: Cost 3 vsldoi4 <0,3,1,4>, LHS + 3226707055U, // <3,1,5,0>: Cost 3 vsldoi12 LHS, <1,5,0,1> + 3226707064U, // <3,1,5,1>: Cost 4 vsldoi12 LHS, <1,5,1,1> + 3358361750U, // <3,1,5,2>: Cost 4 vmrglw <0,4,3,5>, <3,0,1,2> + 3226707081U, // <3,1,5,3>: Cost 4 vsldoi12 LHS, <1,5,3,0> + 3226707095U, // <3,1,5,4>: Cost 3 vsldoi12 LHS, <1,5,4,5> + 3368313170U, // <3,1,5,5>: Cost 3 vmrglw <2,1,3,5>, <0,4,1,5> + 4208758882U, // <3,1,5,6>: Cost 4 vsldoi8 , <5,6,7,0> + 3269837998U, // <3,1,5,7>: Cost 4 vsldoi12 LHS, <1,5,7,1> + 3226707127U, // <3,1,5,u>: Cost 3 vsldoi12 LHS, <1,5,u,1> + 3226707136U, // <3,1,6,0>: Cost 4 vsldoi12 LHS, <1,6,0,1> + 3226707151U, // <3,1,6,1>: Cost 3 vsldoi12 LHS, <1,6,1,7> + 3243180950U, // <3,1,6,2>: Cost 3 vmrghw <3,6,0,7>, <1,2,3,0> + 3222652129U, // <3,1,6,3>: Cost 4 vsldoi12 <0,2,1,3>, <1,6,3,7> + 3226707176U, // <3,1,6,4>: Cost 4 vsldoi12 LHS, <1,6,4,5> + 3226707187U, // <3,1,6,5>: Cost 3 vsldoi12 LHS, <1,6,5,7> + 3226707196U, // <3,1,6,6>: Cost 4 vsldoi12 LHS, <1,6,6,7> + 3269838078U, // <3,1,6,7>: Cost 3 vsldoi12 LHS, <1,6,7,0> + 3226707214U, // <3,1,6,u>: Cost 3 vsldoi12 LHS, <1,6,u,7> + 4034625638U, // <3,1,7,0>: Cost 4 vsldoi4 <1,3,1,7>, LHS + 3371646986U, // <3,1,7,1>: Cost 3 vmrglw <2,6,3,7>, <0,0,1,1> + 3371649174U, // <3,1,7,2>: Cost 3 vmrglw <2,6,3,7>, <3,0,1,2> + 3365675182U, // <3,1,7,3>: Cost 4 vmrglw <1,6,3,7>, <0,2,1,3> + 4034628918U, // <3,1,7,4>: Cost 4 vsldoi4 <1,3,1,7>, RHS + 3371647314U, // <3,1,7,5>: Cost 3 vmrglw <2,6,3,7>, <0,4,1,5> + 3371647153U, // <3,1,7,6>: Cost 3 vmrglw <2,6,3,7>, <0,2,1,6> + 3368330447U, // <3,1,7,7>: Cost 4 vmrglw <2,1,3,7>, <1,6,1,7> + 3371646993U, // <3,1,7,u>: Cost 3 vmrglw <2,6,3,7>, <0,0,1,u> + 4028662020U, // <3,1,u,0>: Cost 3 vsldoi4 <0,3,1,u>, <0,3,1,u> + 3222061876U, // <3,1,u,1>: Cost 2 vsldoi12 LHS, <1,1,1,1> + 3363031190U, // <3,1,u,2>: Cost 3 vmrglw <1,2,3,u>, <3,0,1,2> + 3222504828U, // <3,1,u,3>: Cost 2 vsldoi12 LHS, <1,u,3,0> + 4028665142U, // <3,1,u,4>: Cost 3 vsldoi4 <0,3,1,u>, RHS + 3226707345U, // <3,1,u,5>: Cost 3 vsldoi12 LHS, <1,u,5,3> + 3371647153U, // <3,1,u,6>: Cost 3 vmrglw <2,6,3,7>, <0,2,1,6> + 3269838240U, // <3,1,u,7>: Cost 3 vsldoi12 LHS, <1,u,7,0> + 3226707369U, // <3,1,u,u>: Cost 2 vsldoi12 LHS, <1,u,u,0> + 3362964203U, // <3,2,0,0>: Cost 4 vmrglw <1,2,3,0>, <1,0,2,0> + 3362964204U, // <3,2,0,1>: Cost 3 vmrglw <1,2,3,0>, <1,0,2,1> + 3362964286U, // <3,2,0,2>: Cost 3 vmrglw <1,2,3,0>, <1,1,2,2> + 2289221734U, // <3,2,0,3>: Cost 2 vmrglw <1,2,3,0>, LHS + 3362964207U, // <3,2,0,4>: Cost 4 vmrglw <1,2,3,0>, <1,0,2,4> + 3362964532U, // <3,2,0,5>: Cost 3 vmrglw <1,2,3,0>, <1,4,2,5> + 3239233466U, // <3,2,0,6>: Cost 3 vmrghw <3,0,1,2>, <2,6,3,7> + 3396142296U, // <3,2,0,7>: Cost 4 vmrglw <6,7,3,0>, <1,6,2,7> + 2289221739U, // <3,2,0,u>: Cost 2 vmrglw <1,2,3,0>, LHS + 4034650214U, // <3,2,1,0>: Cost 4 vsldoi4 <1,3,2,1>, LHS + 4168287028U, // <3,2,1,1>: Cost 4 vsldoi8 <1,2,3,2>, <1,1,1,1> + 4168287128U, // <3,2,1,2>: Cost 3 vsldoi8 <1,2,3,2>, <1,2,3,2> + 3222062623U, // <3,2,1,3>: Cost 3 vsldoi12 LHS, <2,1,3,1> + 4034653494U, // <3,2,1,4>: Cost 4 vsldoi4 <1,3,2,1>, RHS + 3226707504U, // <3,2,1,5>: Cost 5 vsldoi12 LHS, <2,1,5,0> + 3226707513U, // <3,2,1,6>: Cost 4 vsldoi12 LHS, <2,1,6,0> + 3270280772U, // <3,2,1,7>: Cost 4 vsldoi12 LHS, <2,1,7,2> + 3222505036U, // <3,2,1,u>: Cost 3 vsldoi12 LHS, <2,1,u,1> + 4040630374U, // <3,2,2,0>: Cost 3 vsldoi4 <2,3,2,2>, LHS + 4173596192U, // <3,2,2,1>: Cost 3 vsldoi8 <2,1,3,2>, <2,1,3,2> + 3222062696U, // <3,2,2,2>: Cost 2 vsldoi12 LHS, <2,2,2,2> + 3222062706U, // <3,2,2,3>: Cost 2 vsldoi12 LHS, <2,2,3,3> + 4040633654U, // <3,2,2,4>: Cost 3 vsldoi4 <2,3,2,2>, RHS + 3368953613U, // <3,2,2,5>: Cost 4 vmrglw <2,2,3,2>, <2,4,2,5> + 3240937402U, // <3,2,2,6>: Cost 3 vmrghw <3,2,6,3>, <2,6,3,7> + 3368953777U, // <3,2,2,7>: Cost 4 vmrglw <2,2,3,2>, <2,6,2,7> + 3222505119U, // <3,2,2,u>: Cost 2 vsldoi12 LHS, <2,2,u,3> + 3222062758U, // <3,2,3,0>: Cost 2 vsldoi12 LHS, <2,3,0,1> + 3222062767U, // <3,2,3,1>: Cost 3 vsldoi12 LHS, <2,3,1,1> + 3222062777U, // <3,2,3,2>: Cost 3 vsldoi12 LHS, <2,3,2,2> + 2295218278U, // <3,2,3,3>: Cost 2 vmrglw <2,2,3,3>, LHS + 3222062798U, // <3,2,3,4>: Cost 2 vsldoi12 LHS, <2,3,4,5> + 3269838551U, // <3,2,3,5>: Cost 3 vsldoi12 LHS, <2,3,5,5> + 3241379770U, // <3,2,3,6>: Cost 3 vmrghw <3,3,3,3>, <2,6,3,7> + 3269838564U, // <3,2,3,7>: Cost 3 vsldoi12 LHS, <2,3,7,0> + 3222062830U, // <3,2,3,u>: Cost 2 vsldoi12 LHS, <2,3,u,1> + 4034674790U, // <3,2,4,0>: Cost 4 vsldoi4 <1,3,2,4>, LHS + 3362996972U, // <3,2,4,1>: Cost 4 vmrglw <1,2,3,4>, <1,0,2,1> + 3362997864U, // <3,2,4,2>: Cost 3 vmrglw <1,2,3,4>, <2,2,2,2> + 2289254502U, // <3,2,4,3>: Cost 2 vmrglw <1,2,3,4>, LHS + 3362998676U, // <3,2,4,4>: Cost 4 vmrglw <1,2,3,4>, <3,3,2,4> + 4168289590U, // <3,2,4,5>: Cost 3 vsldoi8 <1,2,3,2>, RHS + 3242215354U, // <3,2,4,6>: Cost 3 vmrghw <3,4,5,6>, <2,6,3,7> + 4070511864U, // <3,2,4,7>: Cost 4 vsldoi4 <7,3,2,4>, <7,3,2,4> + 2289254507U, // <3,2,4,u>: Cost 2 vmrglw <1,2,3,4>, LHS + 4040654950U, // <3,2,5,0>: Cost 4 vsldoi4 <2,3,2,5>, LHS + 3368313985U, // <3,2,5,1>: Cost 4 vmrglw <2,1,3,5>, <1,5,2,1> + 3368314472U, // <3,2,5,2>: Cost 4 vmrglw <2,1,3,5>, <2,2,2,2> + 3226707816U, // <3,2,5,3>: Cost 3 vsldoi12 LHS, <2,5,3,6> + 4040658230U, // <3,2,5,4>: Cost 4 vsldoi4 <2,3,2,5>, RHS + 3242952552U, // <3,2,5,5>: Cost 4 vmrghw <3,5,6,6>, <2,5,3,6> + 3243026362U, // <3,2,5,6>: Cost 4 vmrghw <3,5,7,6>, <2,6,3,7> + 3370305457U, // <3,2,5,7>: Cost 5 vmrglw <2,4,3,5>, <2,6,2,7> + 3222505365U, // <3,2,5,u>: Cost 3 vsldoi12 LHS, <2,5,u,6> + 4040663142U, // <3,2,6,0>: Cost 3 vsldoi4 <2,3,2,6>, LHS + 4040663860U, // <3,2,6,1>: Cost 4 vsldoi4 <2,3,2,6>, <1,1,1,1> + 4040664765U, // <3,2,6,2>: Cost 3 vsldoi4 <2,3,2,6>, <2,3,2,6> + 3222063034U, // <3,2,6,3>: Cost 2 vsldoi12 LHS, <2,6,3,7> + 4040666422U, // <3,2,6,4>: Cost 3 vsldoi4 <2,3,2,6>, RHS + 3370976956U, // <3,2,6,5>: Cost 4 vmrglw <2,5,3,6>, <2,3,2,5> + 3243698106U, // <3,2,6,6>: Cost 3 vmrghw <3,6,7,7>, <2,6,3,7> + 4201468778U, // <3,2,6,7>: Cost 4 vsldoi8 <6,7,3,2>, <6,7,3,2> + 3222505447U, // <3,2,6,u>: Cost 2 vsldoi12 LHS, <2,6,u,7> + 3269838826U, // <3,2,7,0>: Cost 3 vsldoi12 LHS, <2,7,0,1> + 3371647724U, // <3,2,7,1>: Cost 4 vmrglw <2,6,3,7>, <1,0,2,1> + 3371648616U, // <3,2,7,2>: Cost 3 vmrglw <2,6,3,7>, <2,2,2,2> + 2297905254U, // <3,2,7,3>: Cost 2 vmrglw <2,6,3,7>, LHS + 4040674614U, // <3,2,7,4>: Cost 4 vsldoi4 <2,3,2,7>, RHS + 3371648052U, // <3,2,7,5>: Cost 4 vmrglw <2,6,3,7>, <1,4,2,5> + 3371648701U, // <3,2,7,6>: Cost 3 vmrglw <2,6,3,7>, <2,3,2,6> + 3371648702U, // <3,2,7,7>: Cost 4 vmrglw <2,6,3,7>, <2,3,2,7> + 2297905259U, // <3,2,7,u>: Cost 2 vmrglw <2,6,3,7>, LHS + 3222505531U, // <3,2,u,0>: Cost 2 vsldoi12 LHS, <2,u,0,1> + 3222505540U, // <3,2,u,1>: Cost 3 vsldoi12 LHS, <2,u,1,1> + 3222062696U, // <3,2,u,2>: Cost 2 vsldoi12 LHS, <2,2,2,2> + 3222063192U, // <3,2,u,3>: Cost 2 vsldoi12 LHS, <2,u,3,3> + 3222505571U, // <3,2,u,4>: Cost 2 vsldoi12 LHS, <2,u,4,5> + 4168292506U, // <3,2,u,5>: Cost 3 vsldoi8 <1,2,3,2>, RHS + 3244541882U, // <3,2,u,6>: Cost 3 vmrghw <3,u,1,2>, <2,6,3,7> + 3270281337U, // <3,2,u,7>: Cost 3 vsldoi12 LHS, <2,u,7,0> + 3222505603U, // <3,2,u,u>: Cost 2 vsldoi12 LHS, <2,u,u,1> + 2289222550U, // <3,3,0,0>: Cost 2 vmrglw <1,2,3,0>, <1,2,3,0> + 3222063254U, // <3,3,0,1>: Cost 2 vsldoi12 LHS, <3,0,1,2> + 4040689344U, // <3,3,0,2>: Cost 3 vsldoi4 <2,3,3,0>, <2,3,3,0> + 3362965106U, // <3,3,0,3>: Cost 3 vmrglw <1,2,3,0>, <2,2,3,3> + 3222063280U, // <3,3,0,4>: Cost 3 vsldoi12 LHS, <3,0,4,1> + 3362965027U, // <3,3,0,5>: Cost 4 vmrglw <1,2,3,0>, <2,1,3,5> + 3362965352U, // <3,3,0,6>: Cost 4 vmrglw <1,2,3,0>, <2,5,3,6> + 3362965434U, // <3,3,0,7>: Cost 3 vmrglw <1,2,3,0>, <2,6,3,7> + 3222063317U, // <3,3,0,u>: Cost 2 vsldoi12 LHS, <3,0,u,2> + 3226708188U, // <3,3,1,0>: Cost 4 vsldoi12 LHS, <3,1,0,0> + 3222063334U, // <3,3,1,1>: Cost 3 vsldoi12 LHS, <3,1,1,1> + 3222063345U, // <3,3,1,2>: Cost 3 vsldoi12 LHS, <3,1,2,3> + 3378899356U, // <3,3,1,3>: Cost 3 vmrglw <3,u,3,1>, <3,3,3,3> + 3226708224U, // <3,3,1,4>: Cost 4 vsldoi12 LHS, <3,1,4,0> + 3226708233U, // <3,3,1,5>: Cost 4 vsldoi12 LHS, <3,1,5,0> + 3226708243U, // <3,3,1,6>: Cost 4 vsldoi12 LHS, <3,1,6,1> + 3362973626U, // <3,3,1,7>: Cost 4 vmrglw <1,2,3,1>, <2,6,3,7> + 3222505767U, // <3,3,1,u>: Cost 3 vsldoi12 LHS, <3,1,u,3> + 4040704102U, // <3,3,2,0>: Cost 3 vsldoi4 <2,3,3,2>, LHS + 3222063417U, // <3,3,2,1>: Cost 4 vsldoi12 LHS, <3,2,1,3> + 3100526194U, // <3,3,2,2>: Cost 2 vsldoi8 <2,2,3,3>, <2,2,3,3> + 3222063432U, // <3,3,2,3>: Cost 3 vsldoi12 LHS, <3,2,3,0> + 4040707382U, // <3,3,2,4>: Cost 3 vsldoi4 <2,3,3,2>, RHS + 3222505826U, // <3,3,2,5>: Cost 4 vsldoi12 LHS, <3,2,5,u> + 3222063462U, // <3,3,2,6>: Cost 3 vsldoi12 LHS, <3,2,6,3> + 3241011567U, // <3,3,2,7>: Cost 3 vsldoi12 <3,2,7,3>, <3,2,7,3> + 3104507992U, // <3,3,2,u>: Cost 2 vsldoi8 <2,u,3,3>, <2,u,3,3> + 2972942438U, // <3,3,3,0>: Cost 2 vsldoi4 <3,3,3,3>, LHS + 3375597735U, // <3,3,3,1>: Cost 3 vmrglw <3,3,3,3>, <3,0,3,1> + 4174268738U, // <3,3,3,2>: Cost 3 vsldoi8 <2,2,3,3>, <3,2,2,3> + 1745666150U, // <3,3,3,3>: Cost 1 vspltisw3 LHS + 2972945718U, // <3,3,3,4>: Cost 2 vsldoi4 <3,3,3,3>, RHS + 3375598063U, // <3,3,3,5>: Cost 3 vmrglw <3,3,3,3>, <3,4,3,5> + 4174269075U, // <3,3,3,6>: Cost 3 vsldoi8 <2,2,3,3>, <3,6,3,7> + 3368961978U, // <3,3,3,7>: Cost 3 vmrglw <2,2,3,3>, <2,6,3,7> + 1745666150U, // <3,3,3,u>: Cost 1 vspltisw3 LHS + 3362997142U, // <3,3,4,0>: Cost 3 vmrglw <1,2,3,4>, <1,2,3,0> + 4040721306U, // <3,3,4,1>: Cost 3 vsldoi4 <2,3,3,4>, <1,2,3,4> + 4040722116U, // <3,3,4,2>: Cost 3 vsldoi4 <2,3,3,4>, <2,3,3,4> + 3362997874U, // <3,3,4,3>: Cost 3 vmrglw <1,2,3,4>, <2,2,3,3> + 2289255322U, // <3,3,4,4>: Cost 2 vmrglw <1,2,3,4>, <1,2,3,4> + 3222505986U, // <3,3,4,5>: Cost 2 vsldoi12 LHS, <3,4,5,6> + 3362998120U, // <3,3,4,6>: Cost 4 vmrglw <1,2,3,4>, <2,5,3,6> + 3362998202U, // <3,3,4,7>: Cost 3 vmrglw <1,2,3,4>, <2,6,3,7> + 3222506013U, // <3,3,4,u>: Cost 2 vsldoi12 LHS, <3,4,u,6> + 3227150881U, // <3,3,5,0>: Cost 4 vsldoi12 LHS, <3,5,0,1> + 3376277671U, // <3,3,5,1>: Cost 4 vmrglw <3,4,3,5>, <3,0,3,1> + 4174270196U, // <3,3,5,2>: Cost 4 vsldoi8 <2,2,3,3>, <5,2,2,3> + 3376277916U, // <3,3,5,3>: Cost 3 vmrglw <3,4,3,5>, <3,3,3,3> + 3227150921U, // <3,3,5,4>: Cost 4 vsldoi12 LHS, <3,5,4,5> + 3368314403U, // <3,3,5,5>: Cost 3 vmrglw <2,1,3,5>, <2,1,3,5> + 3270281821U, // <3,3,5,6>: Cost 3 vsldoi12 LHS, <3,5,6,7> + 3368314810U, // <3,3,5,7>: Cost 4 vmrglw <2,1,3,5>, <2,6,3,7> + 3270281839U, // <3,3,5,u>: Cost 3 vsldoi12 LHS, <3,5,u,7> + 3269839480U, // <3,3,6,0>: Cost 3 vsldoi12 LHS, <3,6,0,7> + 3243182321U, // <3,3,6,1>: Cost 4 vmrghw <3,6,0,7>, <3,1,2,3> + 3258927754U, // <3,3,6,2>: Cost 3 vsldoi12 <6,2,7,3>, <3,6,2,7> + 3234744979U, // <3,3,6,3>: Cost 3 vsldoi12 <2,2,3,3>, <3,6,3,7> + 3269839516U, // <3,3,6,4>: Cost 3 vsldoi12 LHS, <3,6,4,7> + 3269839525U, // <3,3,6,5>: Cost 4 vsldoi12 LHS, <3,6,5,7> + 3370977128U, // <3,3,6,6>: Cost 3 vmrglw <2,5,3,6>, <2,5,3,6> + 4201476971U, // <3,3,6,7>: Cost 3 vsldoi8 <6,7,3,3>, <6,7,3,3> + 4202140604U, // <3,3,6,u>: Cost 3 vsldoi8 <6,u,3,3>, <6,u,3,3> + 4040745062U, // <3,3,7,0>: Cost 3 vsldoi4 <2,3,3,7>, LHS + 4040745780U, // <3,3,7,1>: Cost 4 vsldoi4 <2,3,3,7>, <1,1,1,1> + 4040746695U, // <3,3,7,2>: Cost 3 vsldoi4 <2,3,3,7>, <2,3,3,7> + 3371648626U, // <3,3,7,3>: Cost 3 vmrglw <2,6,3,7>, <2,2,3,3> + 4040748342U, // <3,3,7,4>: Cost 3 vsldoi4 <2,3,3,7>, RHS + 3371648547U, // <3,3,7,5>: Cost 4 vmrglw <2,6,3,7>, <2,1,3,5> + 3371648548U, // <3,3,7,6>: Cost 4 vmrglw <2,6,3,7>, <2,1,3,6> + 2297907130U, // <3,3,7,7>: Cost 2 vmrglw <2,6,3,7>, <2,6,3,7> + 2297907130U, // <3,3,7,u>: Cost 2 vmrglw <2,6,3,7>, <2,6,3,7> + 2289222550U, // <3,3,u,0>: Cost 2 vmrglw <1,2,3,0>, <1,2,3,0> + 3222506270U, // <3,3,u,1>: Cost 2 vsldoi12 LHS, <3,u,1,2> + 3136362376U, // <3,3,u,2>: Cost 2 vsldoi8 , + 1745666150U, // <3,3,u,3>: Cost 1 vspltisw3 LHS + 2972945718U, // <3,3,u,4>: Cost 2 vsldoi4 <3,3,3,3>, RHS + 3222506310U, // <3,3,u,5>: Cost 2 vsldoi12 LHS, <3,u,5,6> + 3226708812U, // <3,3,u,6>: Cost 3 vsldoi12 LHS, <3,u,6,3> + 2297907130U, // <3,3,u,7>: Cost 2 vmrglw <2,6,3,7>, <2,6,3,7> + 1745666150U, // <3,3,u,u>: Cost 1 vspltisw3 LHS + 4168302592U, // <3,4,0,0>: Cost 3 vsldoi8 <1,2,3,4>, <0,0,0,0> + 3094560870U, // <3,4,0,1>: Cost 2 vsldoi8 <1,2,3,4>, LHS + 4040763081U, // <3,4,0,2>: Cost 3 vsldoi4 <2,3,4,0>, <2,3,4,0> + 3239234692U, // <3,4,0,3>: Cost 3 vmrghw <3,0,1,2>, <4,3,5,0> + 4168302930U, // <3,4,0,4>: Cost 3 vsldoi8 <1,2,3,4>, <0,4,1,5> + 2165493046U, // <3,4,0,5>: Cost 2 vmrghw <3,0,1,2>, RHS + 3239234942U, // <3,4,0,6>: Cost 4 vmrghw <3,0,1,2>, <4,6,5,7> + 3366947484U, // <3,4,0,7>: Cost 4 vmrglw <1,u,3,0>, <3,6,4,7> + 3094561437U, // <3,4,0,u>: Cost 2 vsldoi8 <1,2,3,4>, LHS + 4040769638U, // <3,4,1,0>: Cost 3 vsldoi4 <2,3,4,1>, LHS + 4168303412U, // <3,4,1,1>: Cost 3 vsldoi8 <1,2,3,4>, <1,1,1,1> + 3094561690U, // <3,4,1,2>: Cost 2 vsldoi8 <1,2,3,4>, <1,2,3,4> + 4168303577U, // <3,4,1,3>: Cost 4 vsldoi8 <1,2,3,4>, <1,3,1,4> + 4040772918U, // <3,4,1,4>: Cost 3 vsldoi4 <2,3,4,1>, RHS + 3226708962U, // <3,4,1,5>: Cost 3 vsldoi12 LHS, <4,1,5,0> + 4168303823U, // <3,4,1,6>: Cost 4 vsldoi8 <1,2,3,4>, <1,6,1,7> + 4070634759U, // <3,4,1,7>: Cost 4 vsldoi4 <7,3,4,1>, <7,3,4,1> + 3098543488U, // <3,4,1,u>: Cost 2 vsldoi8 <1,u,3,4>, <1,u,3,4> + 4168304077U, // <3,4,2,0>: Cost 4 vsldoi8 <1,2,3,4>, <2,0,3,0> + 3227151378U, // <3,4,2,1>: Cost 4 vsldoi12 LHS, <4,2,1,3> + 4168304232U, // <3,4,2,2>: Cost 3 vsldoi8 <1,2,3,4>, <2,2,2,2> + 4168304294U, // <3,4,2,3>: Cost 3 vsldoi8 <1,2,3,4>, <2,3,0,1> + 4175603477U, // <3,4,2,4>: Cost 3 vsldoi8 <2,4,3,4>, <2,4,3,4> + 3240496438U, // <3,4,2,5>: Cost 3 vmrghw <3,2,0,3>, RHS + 4168304570U, // <3,4,2,6>: Cost 3 vsldoi8 <1,2,3,4>, <2,6,3,7> + 4177594376U, // <3,4,2,7>: Cost 3 vsldoi8 <2,7,3,4>, <2,7,3,4> + 4168304699U, // <3,4,2,u>: Cost 3 vsldoi8 <1,2,3,4>, <2,u,0,1> + 4168304790U, // <3,4,3,0>: Cost 3 vsldoi8 <1,2,3,4>, <3,0,1,2> + 4168304870U, // <3,4,3,1>: Cost 4 vsldoi8 <1,2,3,4>, <3,1,1,1> + 4168304980U, // <3,4,3,2>: Cost 3 vsldoi8 <1,2,3,4>, <3,2,4,3> + 4168305052U, // <3,4,3,3>: Cost 3 vsldoi8 <1,2,3,4>, <3,3,3,3> + 4168305104U, // <3,4,3,4>: Cost 3 vsldoi8 <1,2,3,4>, <3,4,0,1> + 2167639350U, // <3,4,3,5>: Cost 2 vmrghw <3,3,3,3>, RHS + 4168305308U, // <3,4,3,6>: Cost 3 vsldoi8 <1,2,3,4>, <3,6,4,7> + 3368962716U, // <3,4,3,7>: Cost 4 vmrglw <2,2,3,3>, <3,6,4,7> + 2167639593U, // <3,4,3,u>: Cost 2 vmrghw <3,3,3,3>, RHS + 4040794214U, // <3,4,4,0>: Cost 3 vsldoi4 <2,3,4,4>, LHS + 4040795034U, // <3,4,4,1>: Cost 3 vsldoi4 <2,3,4,4>, <1,2,3,4> + 4040795853U, // <3,4,4,2>: Cost 3 vsldoi4 <2,3,4,4>, <2,3,4,4> + 3362998612U, // <3,4,4,3>: Cost 3 vmrglw <1,2,3,4>, <3,2,4,3> + 3269840080U, // <3,4,4,4>: Cost 2 vsldoi12 LHS, <4,4,4,4> + 3094564150U, // <3,4,4,5>: Cost 2 vsldoi8 <1,2,3,4>, RHS + 3362998858U, // <3,4,4,6>: Cost 4 vmrglw <1,2,3,4>, <3,5,4,6> + 3362998940U, // <3,4,4,7>: Cost 3 vmrglw <1,2,3,4>, <3,6,4,7> + 3094564393U, // <3,4,4,u>: Cost 2 vsldoi8 <1,2,3,4>, RHS + 2967060582U, // <3,4,5,0>: Cost 2 vsldoi4 <2,3,4,5>, LHS + 4040803124U, // <3,4,5,1>: Cost 3 vsldoi4 <2,3,4,5>, <1,1,1,1> + 2967062222U, // <3,4,5,2>: Cost 2 vsldoi4 <2,3,4,5>, <2,3,4,5> + 4040804502U, // <3,4,5,3>: Cost 3 vsldoi4 <2,3,4,5>, <3,0,1,2> + 2967063862U, // <3,4,5,4>: Cost 2 vsldoi4 <2,3,4,5>, RHS + 3370305230U, // <3,4,5,5>: Cost 3 vmrglw <2,4,3,5>, <2,3,4,5> + 1074580790U, // <3,4,5,6>: Cost 1 vsldoi12 LHS, RHS + 4070667531U, // <3,4,5,7>: Cost 3 vsldoi4 <7,3,4,5>, <7,3,4,5> + 1074580808U, // <3,4,5,u>: Cost 1 vsldoi12 LHS, RHS + 4040810598U, // <3,4,6,0>: Cost 4 vsldoi4 <2,3,4,6>, LHS + 3227151706U, // <3,4,6,1>: Cost 4 vsldoi12 LHS, <4,6,1,7> + 4210110970U, // <3,4,6,2>: Cost 3 vsldoi8 , <6,2,7,3> + 3240791404U, // <3,4,6,3>: Cost 4 vsldoi12 <3,2,4,3>, <4,6,3,7> + 3269840245U, // <3,4,6,4>: Cost 3 vsldoi12 LHS, <4,6,4,7> + 3243183414U, // <3,4,6,5>: Cost 3 vmrghw <3,6,0,7>, RHS + 4210111288U, // <3,4,6,6>: Cost 3 vsldoi8 , <6,6,6,6> + 4201485164U, // <3,4,6,7>: Cost 3 vsldoi8 <6,7,3,4>, <6,7,3,4> + 3243183657U, // <3,4,6,u>: Cost 3 vmrghw <3,6,0,7>, RHS + 4210111482U, // <3,4,7,0>: Cost 3 vsldoi8 , <7,0,1,2> + 3371647013U, // <3,4,7,1>: Cost 4 vmrglw <2,6,3,7>, <0,0,4,1> + 4204139696U, // <3,4,7,2>: Cost 3 vsldoi8 <7,2,3,4>, <7,2,3,4> + 3371649364U, // <3,4,7,3>: Cost 4 vmrglw <2,6,3,7>, <3,2,4,3> + 4210111846U, // <3,4,7,4>: Cost 3 vsldoi8 , <7,4,5,6> + 3371648718U, // <3,4,7,5>: Cost 3 vmrglw <2,6,3,7>, <2,3,4,5> + 3371647180U, // <3,4,7,6>: Cost 4 vmrglw <2,6,3,7>, <0,2,4,6> + 4210112108U, // <3,4,7,7>: Cost 3 vsldoi8 , <7,7,7,7> + 3371648721U, // <3,4,7,u>: Cost 3 vmrglw <2,6,3,7>, <2,3,4,u> + 2967085158U, // <3,4,u,0>: Cost 2 vsldoi4 <2,3,4,u>, LHS + 3094566702U, // <3,4,u,1>: Cost 2 vsldoi8 <1,2,3,4>, LHS + 2967086801U, // <3,4,u,2>: Cost 2 vsldoi4 <2,3,4,u>, <2,3,4,u> + 4168308668U, // <3,4,u,3>: Cost 3 vsldoi8 <1,2,3,4>, + 2967088438U, // <3,4,u,4>: Cost 2 vsldoi4 <2,3,4,u>, RHS + 3094567066U, // <3,4,u,5>: Cost 2 vsldoi8 <1,2,3,4>, RHS + 1074581033U, // <3,4,u,6>: Cost 1 vsldoi12 LHS, RHS + 4070692110U, // <3,4,u,7>: Cost 3 vsldoi4 <7,3,4,u>, <7,3,4,u> + 1074581051U, // <3,4,u,u>: Cost 1 vsldoi12 LHS, RHS + 4052779110U, // <3,5,0,0>: Cost 3 vsldoi4 <4,3,5,0>, LHS + 3226709576U, // <3,5,0,1>: Cost 3 vsldoi12 LHS, <5,0,1,2> + 3404770843U, // <3,5,0,2>: Cost 3 vmrglw , <4,u,5,2> + 4052781206U, // <3,5,0,3>: Cost 3 vsldoi4 <4,3,5,0>, <3,0,1,2> + 3226709602U, // <3,5,0,4>: Cost 3 vsldoi12 LHS, <5,0,4,1> + 3269840491U, // <3,5,0,5>: Cost 3 vsldoi12 LHS, <5,0,5,1> + 3362966018U, // <3,5,0,6>: Cost 3 vmrglw <1,2,3,0>, <3,4,5,6> + 3362964723U, // <3,5,0,7>: Cost 4 vmrglw <1,2,3,0>, <1,6,5,7> + 3226709638U, // <3,5,0,u>: Cost 3 vsldoi12 LHS, <5,0,u,1> + 3269840527U, // <3,5,1,0>: Cost 3 vsldoi12 LHS, <5,1,0,1> + 3406769042U, // <3,5,1,1>: Cost 3 vmrglw , <4,0,5,1> + 4168311707U, // <3,5,1,2>: Cost 3 vsldoi8 <1,2,3,5>, <1,2,3,5> + 3228921518U, // <3,5,1,3>: Cost 4 vsldoi12 <1,2,5,3>, <5,1,3,5> + 3269840567U, // <3,5,1,4>: Cost 3 vsldoi12 LHS, <5,1,4,5> + 3226709691U, // <3,5,1,5>: Cost 4 vsldoi12 LHS, <5,1,5,0> + 3226709705U, // <3,5,1,6>: Cost 4 vsldoi12 LHS, <5,1,6,5> + 3269840589U, // <3,5,1,7>: Cost 4 vsldoi12 LHS, <5,1,7,0> + 3269840599U, // <3,5,1,u>: Cost 3 vsldoi12 LHS, <5,1,u,1> + 4173620671U, // <3,5,2,0>: Cost 4 vsldoi8 <2,1,3,5>, <2,0,1,4> + 4173620771U, // <3,5,2,1>: Cost 3 vsldoi8 <2,1,3,5>, <2,1,3,5> + 3226709747U, // <3,5,2,2>: Cost 4 vsldoi12 LHS, <5,2,2,2> + 4175611598U, // <3,5,2,3>: Cost 3 vsldoi8 <2,4,3,5>, <2,3,4,5> + 4175611670U, // <3,5,2,4>: Cost 3 vsldoi8 <2,4,3,5>, <2,4,3,5> + 3252809487U, // <3,5,2,5>: Cost 3 vsldoi12 <5,2,5,3>, <5,2,5,3> + 3252883224U, // <3,5,2,6>: Cost 3 vsldoi12 <5,2,6,3>, <5,2,6,3> + 3252956961U, // <3,5,2,7>: Cost 4 vsldoi12 <5,2,7,3>, <5,2,7,3> + 4178266202U, // <3,5,2,u>: Cost 3 vsldoi8 <2,u,3,5>, <2,u,3,5> + 4052803686U, // <3,5,3,0>: Cost 3 vsldoi4 <4,3,5,3>, LHS + 3404794770U, // <3,5,3,1>: Cost 3 vmrglw , <4,0,5,1> + 4034889330U, // <3,5,3,2>: Cost 4 vsldoi4 <1,3,5,3>, <2,2,3,3> + 4181584284U, // <3,5,3,3>: Cost 3 vsldoi8 <3,4,3,5>, <3,3,3,3> + 4181584367U, // <3,5,3,4>: Cost 3 vsldoi8 <3,4,3,5>, <3,4,3,5> + 3404795098U, // <3,5,3,5>: Cost 3 vmrglw , <4,4,5,5> + 3368962562U, // <3,5,3,6>: Cost 3 vmrglw <2,2,3,3>, <3,4,5,6> + 3368961267U, // <3,5,3,7>: Cost 4 vmrglw <2,2,3,3>, <1,6,5,7> + 3368962564U, // <3,5,3,u>: Cost 3 vmrglw <2,2,3,3>, <3,4,5,u> + 4052811878U, // <3,5,4,0>: Cost 3 vsldoi4 <4,3,5,4>, LHS + 3404802962U, // <3,5,4,1>: Cost 3 vmrglw , <4,0,5,1> + 3242217240U, // <3,5,4,2>: Cost 3 vmrghw <3,4,5,6>, <5,2,6,3> + 4052814338U, // <3,5,4,3>: Cost 3 vsldoi4 <4,3,5,4>, <3,4,5,6> + 4212108506U, // <3,5,4,4>: Cost 3 vsldoi8 , <4,4,5,5> + 3226709940U, // <3,5,4,5>: Cost 3 vsldoi12 LHS, <5,4,5,6> + 3362998786U, // <3,5,4,6>: Cost 3 vmrglw <1,2,3,4>, <3,4,5,6> + 3362997491U, // <3,5,4,7>: Cost 4 vmrglw <1,2,3,4>, <1,6,5,7> + 3226709967U, // <3,5,4,u>: Cost 3 vsldoi12 LHS, <5,4,u,6> + 3269840851U, // <3,5,5,0>: Cost 3 vsldoi12 LHS, <5,5,0,1> + 3269840860U, // <3,5,5,1>: Cost 3 vsldoi12 LHS, <5,5,1,1> + 4040877783U, // <3,5,5,2>: Cost 3 vsldoi4 <2,3,5,5>, <2,3,5,5> + 3228921840U, // <3,5,5,3>: Cost 4 vsldoi12 <1,2,5,3>, <5,5,3,3> + 3269840891U, // <3,5,5,4>: Cost 3 vsldoi12 LHS, <5,5,4,5> + 3269840900U, // <3,5,5,5>: Cost 2 vsldoi12 LHS, <5,5,5,5> + 3269840910U, // <3,5,5,6>: Cost 3 vsldoi12 LHS, <5,5,6,6> + 3368314099U, // <3,5,5,7>: Cost 4 vmrglw <2,1,3,5>, <1,6,5,7> + 3269840900U, // <3,5,5,u>: Cost 2 vsldoi12 LHS, <5,5,5,5> + 3269840932U, // <3,5,6,0>: Cost 3 vsldoi12 LHS, <5,6,0,1> + 3269840947U, // <3,5,6,1>: Cost 3 vsldoi12 LHS, <5,6,1,7> + 4040885976U, // <3,5,6,2>: Cost 3 vsldoi4 <2,3,5,6>, <2,3,5,6> + 3269840962U, // <3,5,6,3>: Cost 3 vsldoi12 LHS, <5,6,3,4> + 3269840972U, // <3,5,6,4>: Cost 3 vsldoi12 LHS, <5,6,4,5> + 3269840983U, // <3,5,6,5>: Cost 3 vsldoi12 LHS, <5,6,5,7> + 3370977794U, // <3,5,6,6>: Cost 3 vmrglw <2,5,3,6>, <3,4,5,6> + 3269840994U, // <3,5,6,7>: Cost 2 vsldoi12 LHS, <5,6,7,0> + 3269841003U, // <3,5,6,u>: Cost 2 vsldoi12 LHS, <5,6,u,0> + 4034920550U, // <3,5,7,0>: Cost 4 vsldoi4 <1,3,5,7>, LHS + 3407481746U, // <3,5,7,1>: Cost 3 vmrglw , <4,0,5,1> + 4034922426U, // <3,5,7,2>: Cost 4 vsldoi4 <1,3,5,7>, <2,6,3,7> + 3371647915U, // <3,5,7,3>: Cost 4 vmrglw <2,6,3,7>, <1,2,5,3> + 4034923830U, // <3,5,7,4>: Cost 4 vsldoi4 <1,3,5,7>, RHS + 3407482074U, // <3,5,7,5>: Cost 3 vmrglw , <4,4,5,5> + 3371649538U, // <3,5,7,6>: Cost 3 vmrglw <2,6,3,7>, <3,4,5,6> + 3370984691U, // <3,5,7,7>: Cost 4 vmrglw <2,5,3,7>, <1,6,5,7> + 3371649540U, // <3,5,7,u>: Cost 3 vmrglw <2,6,3,7>, <3,4,5,u> + 3269841094U, // <3,5,u,0>: Cost 3 vsldoi12 LHS, <5,u,0,1> + 3226710224U, // <3,5,u,1>: Cost 3 vsldoi12 LHS, <5,u,1,2> + 3404770843U, // <3,5,u,2>: Cost 3 vmrglw , <4,u,5,2> + 3269841124U, // <3,5,u,3>: Cost 3 vsldoi12 LHS, <5,u,3,4> + 3269841133U, // <3,5,u,4>: Cost 3 vsldoi12 LHS, <5,u,4,4> + 3269840900U, // <3,5,u,5>: Cost 2 vsldoi12 LHS, <5,5,5,5> + 3363031554U, // <3,5,u,6>: Cost 3 vmrglw <1,2,3,u>, <3,4,5,6> + 3269841156U, // <3,5,u,7>: Cost 2 vsldoi12 LHS, <5,u,7,0> + 3269841165U, // <3,5,u,u>: Cost 2 vsldoi12 LHS, <5,u,u,0> + 4176281600U, // <3,6,0,0>: Cost 4 vsldoi8 <2,5,3,6>, <0,0,0,0> + 4176281702U, // <3,6,0,1>: Cost 3 vsldoi8 <2,5,3,6>, LHS + 3258929449U, // <3,6,0,2>: Cost 3 vsldoi12 <6,2,7,3>, <6,0,2,1> + 3362965862U, // <3,6,0,3>: Cost 4 vmrglw <1,2,3,0>, <3,2,6,3> + 4176281938U, // <3,6,0,4>: Cost 4 vsldoi8 <2,5,3,6>, <0,4,1,5> + 4058828646U, // <3,6,0,5>: Cost 4 vsldoi4 <5,3,6,0>, <5,3,6,0> + 3269841229U, // <3,6,0,6>: Cost 3 vsldoi12 LHS, <6,0,6,1> + 2289225014U, // <3,6,0,7>: Cost 2 vmrglw <1,2,3,0>, RHS + 2289225015U, // <3,6,0,u>: Cost 2 vmrglw <1,2,3,0>, RHS + 3269841256U, // <3,6,1,0>: Cost 4 vsldoi12 LHS, <6,1,0,1> + 4176282420U, // <3,6,1,1>: Cost 4 vsldoi8 <2,5,3,6>, <1,1,1,1> + 4168319900U, // <3,6,1,2>: Cost 3 vsldoi8 <1,2,3,6>, <1,2,3,6> + 3226710408U, // <3,6,1,3>: Cost 5 vsldoi12 LHS, <6,1,3,6> + 3269841296U, // <3,6,1,4>: Cost 4 vsldoi12 LHS, <6,1,4,5> + 3269841306U, // <3,6,1,5>: Cost 4 vsldoi12 LHS, <6,1,5,6> + 3403453240U, // <3,6,1,6>: Cost 4 vmrglw , <6,6,6,6> + 3362975030U, // <3,6,1,7>: Cost 3 vmrglw <1,2,3,1>, RHS + 3362975031U, // <3,6,1,u>: Cost 3 vmrglw <1,2,3,1>, RHS + 4070785126U, // <3,6,2,0>: Cost 3 vsldoi4 <7,3,6,2>, LHS + 4173628964U, // <3,6,2,1>: Cost 4 vsldoi8 <2,1,3,6>, <2,1,3,6> + 4040926941U, // <3,6,2,2>: Cost 3 vsldoi4 <2,3,6,2>, <2,3,6,2> + 4174292669U, // <3,6,2,3>: Cost 4 vsldoi8 <2,2,3,6>, <2,3,2,6> + 4070788406U, // <3,6,2,4>: Cost 3 vsldoi4 <7,3,6,2>, RHS + 4176283496U, // <3,6,2,5>: Cost 3 vsldoi8 <2,5,3,6>, <2,5,3,6> + 4070789626U, // <3,6,2,6>: Cost 3 vsldoi4 <7,3,6,2>, <6,2,7,3> + 3258929658U, // <3,6,2,7>: Cost 2 vsldoi12 <6,2,7,3>, <6,2,7,3> + 3259003395U, // <3,6,2,u>: Cost 2 vsldoi12 <6,2,u,3>, <6,2,u,3> + 4176283798U, // <3,6,3,0>: Cost 4 vsldoi8 <2,5,3,6>, <3,0,1,2> + 3372942825U, // <3,6,3,1>: Cost 4 vmrglw <2,u,3,3>, <2,0,6,1> + 3241382394U, // <3,6,3,2>: Cost 3 vmrghw <3,3,3,3>, <6,2,7,3> + 3368962406U, // <3,6,3,3>: Cost 4 vmrglw <2,2,3,3>, <3,2,6,3> + 4176284162U, // <3,6,3,4>: Cost 3 vsldoi8 <2,5,3,6>, <3,4,5,6> + 4176284252U, // <3,6,3,5>: Cost 4 vsldoi8 <2,5,3,6>, <3,5,6,6> + 3404796728U, // <3,6,3,6>: Cost 3 vmrglw , <6,6,6,6> + 2295221558U, // <3,6,3,7>: Cost 2 vmrglw <2,2,3,3>, RHS + 2295221559U, // <3,6,3,u>: Cost 2 vmrglw <2,2,3,3>, RHS + 3242217761U, // <3,6,4,0>: Cost 3 vmrghw <3,4,5,6>, <6,0,1,2> + 4052886426U, // <3,6,4,1>: Cost 4 vsldoi4 <4,3,6,4>, <1,2,3,4> + 3258929777U, // <3,6,4,2>: Cost 3 vsldoi12 <6,2,7,3>, <6,4,2,5> + 3242218034U, // <3,6,4,3>: Cost 3 vmrghw <3,4,5,6>, <6,3,4,5> + 3242218125U, // <3,6,4,4>: Cost 3 vmrghw <3,4,5,6>, <6,4,5,6> + 4176284982U, // <3,6,4,5>: Cost 3 vsldoi8 <2,5,3,6>, RHS + 3269841557U, // <3,6,4,6>: Cost 3 vsldoi12 LHS, <6,4,6,5> + 2289257782U, // <3,6,4,7>: Cost 2 vmrglw <1,2,3,4>, RHS + 2289257783U, // <3,6,4,u>: Cost 2 vmrglw <1,2,3,4>, RHS + 3269841580U, // <3,6,5,0>: Cost 4 vsldoi12 LHS, <6,5,0,1> + 3372959209U, // <3,6,5,1>: Cost 5 vmrglw <2,u,3,5>, <2,0,6,1> + 3258929853U, // <3,6,5,2>: Cost 4 vsldoi12 <6,2,7,3>, <6,5,2,0> + 4176285542U, // <3,6,5,3>: Cost 4 vsldoi8 <2,5,3,6>, <5,3,6,0> + 3269841620U, // <3,6,5,4>: Cost 4 vsldoi12 LHS, <6,5,4,5> + 3269841629U, // <3,6,5,5>: Cost 4 vsldoi12 LHS, <6,5,5,5> + 3258929896U, // <3,6,5,6>: Cost 4 vsldoi12 <6,2,7,3>, <6,5,6,7> + 3368316214U, // <3,6,5,7>: Cost 3 vmrglw <2,1,3,5>, RHS + 3368316215U, // <3,6,5,u>: Cost 3 vmrglw <2,1,3,5>, RHS + 3269841661U, // <3,6,6,0>: Cost 3 vsldoi12 LHS, <6,6,0,1> + 3269841670U, // <3,6,6,1>: Cost 4 vsldoi12 LHS, <6,6,1,1> + 3258929936U, // <3,6,6,2>: Cost 3 vsldoi12 <6,2,7,3>, <6,6,2,2> + 3240940314U, // <3,6,6,3>: Cost 4 vsldoi12 <3,2,6,3>, <6,6,3,3> + 3269841701U, // <3,6,6,4>: Cost 3 vsldoi12 LHS, <6,6,4,5> + 4058877804U, // <3,6,6,5>: Cost 4 vsldoi4 <5,3,6,6>, <5,3,6,6> + 3269841720U, // <3,6,6,6>: Cost 2 vsldoi12 LHS, <6,6,6,6> + 3269841730U, // <3,6,6,7>: Cost 2 vsldoi12 LHS, <6,6,7,7> + 3269841739U, // <3,6,6,u>: Cost 2 vsldoi12 LHS, <6,6,u,7> + 3269841742U, // <3,6,7,0>: Cost 2 vsldoi12 LHS, <6,7,0,1> + 3371648489U, // <3,6,7,1>: Cost 3 vmrglw <2,6,3,7>, <2,0,6,1> + 3261879138U, // <3,6,7,2>: Cost 3 vsldoi12 <6,7,2,3>, <6,7,2,3> + 3371649382U, // <3,6,7,3>: Cost 3 vmrglw <2,6,3,7>, <3,2,6,3> + 3269841782U, // <3,6,7,4>: Cost 2 vsldoi12 LHS, <6,7,4,5> + 3371648817U, // <3,6,7,5>: Cost 3 vmrglw <2,6,3,7>, <2,4,6,5> + 3371648656U, // <3,6,7,6>: Cost 3 vmrglw <2,6,3,7>, <2,2,6,6> + 2297908534U, // <3,6,7,7>: Cost 2 vmrglw <2,6,3,7>, RHS + 2297908535U, // <3,6,7,u>: Cost 2 vmrglw <2,6,3,7>, RHS + 3269841823U, // <3,6,u,0>: Cost 2 vsldoi12 LHS, <6,u,0,1> + 4176287534U, // <3,6,u,1>: Cost 3 vsldoi8 <2,5,3,6>, LHS + 3258930097U, // <3,6,u,2>: Cost 3 vsldoi12 <6,2,7,3>, <6,u,2,1> + 3262616508U, // <3,6,u,3>: Cost 3 vsldoi12 <6,u,3,3>, <6,u,3,3> + 3269841863U, // <3,6,u,4>: Cost 2 vsldoi12 LHS, <6,u,4,5> + 4176287898U, // <3,6,u,5>: Cost 3 vsldoi8 <2,5,3,6>, RHS + 3269841720U, // <3,6,u,6>: Cost 2 vsldoi12 LHS, <6,6,6,6> + 2289290550U, // <3,6,u,7>: Cost 2 vmrglw <1,2,3,u>, RHS + 2289290551U, // <3,6,u,u>: Cost 2 vmrglw <1,2,3,u>, RHS + 4176953344U, // <3,7,0,0>: Cost 3 vsldoi8 <2,6,3,7>, <0,0,0,0> + 3103211622U, // <3,7,0,1>: Cost 2 vsldoi8 <2,6,3,7>, LHS + 4176953521U, // <3,7,0,2>: Cost 3 vsldoi8 <2,6,3,7>, <0,2,1,6> + 3404771834U, // <3,7,0,3>: Cost 3 vmrglw , <6,2,7,3> + 4176953682U, // <3,7,0,4>: Cost 3 vsldoi8 <2,6,3,7>, <0,4,1,5> + 3269841954U, // <3,7,0,5>: Cost 3 vsldoi12 LHS, <7,0,5,6> + 4064875080U, // <3,7,0,6>: Cost 3 vsldoi4 <6,3,7,0>, <6,3,7,0> + 3269841967U, // <3,7,0,7>: Cost 3 vsldoi12 LHS, <7,0,7,1> + 3103212189U, // <3,7,0,u>: Cost 2 vsldoi8 <2,6,3,7>, LHS + 4176954083U, // <3,7,1,0>: Cost 4 vsldoi8 <2,6,3,7>, <1,0,1,1> + 4176954164U, // <3,7,1,1>: Cost 3 vsldoi8 <2,6,3,7>, <1,1,1,1> + 4176954262U, // <3,7,1,2>: Cost 3 vsldoi8 <2,6,3,7>, <1,2,3,0> + 4176954332U, // <3,7,1,3>: Cost 4 vsldoi8 <2,6,3,7>, <1,3,1,7> + 4176954411U, // <3,7,1,4>: Cost 4 vsldoi8 <2,6,3,7>, <1,4,1,5> + 4176954479U, // <3,7,1,5>: Cost 4 vsldoi8 <2,6,3,7>, <1,5,0,1> + 4170982625U, // <3,7,1,6>: Cost 4 vsldoi8 <1,6,3,7>, <1,6,3,7> + 3403453250U, // <3,7,1,7>: Cost 4 vmrglw , <6,6,7,7> + 4176954748U, // <3,7,1,u>: Cost 3 vsldoi8 <2,6,3,7>, <1,u,3,0> + 4176954857U, // <3,7,2,0>: Cost 3 vsldoi8 <2,6,3,7>, <2,0,6,1> + 4173637157U, // <3,7,2,1>: Cost 4 vsldoi8 <2,1,3,7>, <2,1,3,7> + 4176954984U, // <3,7,2,2>: Cost 3 vsldoi8 <2,6,3,7>, <2,2,2,2> + 4174964423U, // <3,7,2,3>: Cost 3 vsldoi8 <2,3,3,7>, <2,3,3,7> + 4176955185U, // <3,7,2,4>: Cost 3 vsldoi8 <2,6,3,7>, <2,4,6,5> + 4176291689U, // <3,7,2,5>: Cost 4 vsldoi8 <2,5,3,7>, <2,5,3,7> + 3103213498U, // <3,7,2,6>: Cost 2 vsldoi8 <2,6,3,7>, <2,6,3,7> + 3264902355U, // <3,7,2,7>: Cost 3 vsldoi12 <7,2,7,3>, <7,2,7,3> + 3104540764U, // <3,7,2,u>: Cost 2 vsldoi8 <2,u,3,7>, <2,u,3,7> + 4176955542U, // <3,7,3,0>: Cost 3 vsldoi8 <2,6,3,7>, <3,0,1,2> + 4176955622U, // <3,7,3,1>: Cost 4 vsldoi8 <2,6,3,7>, <3,1,1,1> + 4176955750U, // <3,7,3,2>: Cost 3 vsldoi8 <2,6,3,7>, <3,2,6,3> + 4176955804U, // <3,7,3,3>: Cost 3 vsldoi8 <2,6,3,7>, <3,3,3,3> + 4176955906U, // <3,7,3,4>: Cost 3 vsldoi8 <2,6,3,7>, <3,4,5,6> + 4176956005U, // <3,7,3,5>: Cost 4 vsldoi8 <2,6,3,7>, <3,5,7,6> + 4176956087U, // <3,7,3,6>: Cost 3 vsldoi8 <2,6,3,7>, <3,6,7,7> + 4176956099U, // <3,7,3,7>: Cost 3 vsldoi8 <2,6,3,7>, <3,7,0,1> + 4176956190U, // <3,7,3,u>: Cost 3 vsldoi8 <2,6,3,7>, <3,u,1,2> + 4064903270U, // <3,7,4,0>: Cost 3 vsldoi4 <6,3,7,4>, LHS + 4176956362U, // <3,7,4,1>: Cost 4 vsldoi8 <2,6,3,7>, <4,1,2,3> + 4064905146U, // <3,7,4,2>: Cost 3 vsldoi4 <6,3,7,4>, <2,6,3,7> + 3404804602U, // <3,7,4,3>: Cost 3 vmrglw , <6,2,7,3> + 4064906550U, // <3,7,4,4>: Cost 3 vsldoi4 <6,3,7,4>, RHS + 3103214902U, // <3,7,4,5>: Cost 2 vsldoi8 <2,6,3,7>, RHS + 4064907852U, // <3,7,4,6>: Cost 3 vsldoi4 <6,3,7,4>, <6,3,7,4> + 3269842295U, // <3,7,4,7>: Cost 3 vsldoi12 LHS, <7,4,7,5> + 3103215145U, // <3,7,4,u>: Cost 2 vsldoi8 <2,6,3,7>, RHS + 4176957000U, // <3,7,5,0>: Cost 4 vsldoi8 <2,6,3,7>, <5,0,1,2> + 3269842317U, // <3,7,5,1>: Cost 4 vsldoi12 LHS, <7,5,1,0> + 4176957182U, // <3,7,5,2>: Cost 4 vsldoi8 <2,6,3,7>, <5,2,3,4> + 3258930592U, // <3,7,5,3>: Cost 4 vsldoi12 <6,2,7,3>, <7,5,3,1> + 4176957364U, // <3,7,5,4>: Cost 4 vsldoi8 <2,6,3,7>, <5,4,5,6> + 3269842358U, // <3,7,5,5>: Cost 3 vsldoi12 LHS, <7,5,5,5> + 3269842369U, // <3,7,5,6>: Cost 3 vsldoi12 LHS, <7,5,6,7> + 3269842371U, // <3,7,5,7>: Cost 4 vsldoi12 LHS, <7,5,7,0> + 3269842387U, // <3,7,5,u>: Cost 3 vsldoi12 LHS, <7,5,u,7> + 3269842396U, // <3,7,6,0>: Cost 3 vsldoi12 LHS, <7,6,0,7> + 3269842405U, // <3,7,6,1>: Cost 4 vsldoi12 LHS, <7,6,1,7> + 3258930670U, // <3,7,6,2>: Cost 3 vsldoi12 <6,2,7,3>, <7,6,2,7> + 4176958024U, // <3,7,6,3>: Cost 3 vsldoi8 <2,6,3,7>, <6,3,7,0> + 3269842432U, // <3,7,6,4>: Cost 3 vsldoi12 LHS, <7,6,4,7> + 3258930696U, // <3,7,6,5>: Cost 4 vsldoi12 <6,2,7,3>, <7,6,5,6> + 4176958264U, // <3,7,6,6>: Cost 3 vsldoi8 <2,6,3,7>, <6,6,6,6> + 3269842452U, // <3,7,6,7>: Cost 3 vsldoi12 LHS, <7,6,7,0> + 3262912036U, // <3,7,6,u>: Cost 3 vsldoi12 <6,u,7,3>, <7,6,u,7> + 4047011942U, // <3,7,7,0>: Cost 3 vsldoi4 <3,3,7,7>, LHS + 3371649227U, // <3,7,7,1>: Cost 4 vmrglw <2,6,3,7>, <3,0,7,1> + 4047013818U, // <3,7,7,2>: Cost 3 vsldoi4 <3,3,7,7>, <2,6,3,7> + 3371649391U, // <3,7,7,3>: Cost 3 vmrglw <2,6,3,7>, <3,2,7,3> + 4047015222U, // <3,7,7,4>: Cost 3 vsldoi4 <3,3,7,7>, RHS + 3371649312U, // <3,7,7,5>: Cost 4 vmrglw <2,6,3,7>, <3,1,7,5> + 4064932431U, // <3,7,7,6>: Cost 3 vsldoi4 <6,3,7,7>, <6,3,7,7> + 3269842540U, // <3,7,7,7>: Cost 2 vsldoi12 LHS, <7,7,7,7> + 3269842540U, // <3,7,7,u>: Cost 2 vsldoi12 LHS, <7,7,7,7> + 4176959187U, // <3,7,u,0>: Cost 3 vsldoi8 <2,6,3,7>, + 3103217454U, // <3,7,u,1>: Cost 2 vsldoi8 <2,6,3,7>, LHS + 4176959365U, // <3,7,u,2>: Cost 3 vsldoi8 <2,6,3,7>, + 4176959420U, // <3,7,u,3>: Cost 3 vsldoi8 <2,6,3,7>, + 4176959551U, // <3,7,u,4>: Cost 3 vsldoi8 <2,6,3,7>, + 3103217818U, // <3,7,u,5>: Cost 2 vsldoi8 <2,6,3,7>, RHS + 3139049680U, // <3,7,u,6>: Cost 2 vsldoi8 , + 3269842540U, // <3,7,u,7>: Cost 2 vsldoi12 LHS, <7,7,7,7> + 3103218021U, // <3,7,u,u>: Cost 2 vsldoi8 <2,6,3,7>, LHS + 3222061056U, // <3,u,0,0>: Cost 2 vsldoi12 LHS, <0,0,0,0> + 3222509267U, // <3,u,0,1>: Cost 2 vsldoi12 LHS, + 3362963611U, // <3,u,0,2>: Cost 3 vmrglw <1,2,3,0>, <0,1,u,2> + 2289221788U, // <3,u,0,3>: Cost 2 vmrglw <1,2,3,0>, LHS + 3222509293U, // <3,u,0,4>: Cost 3 vsldoi12 LHS, + 2165495962U, // <3,u,0,5>: Cost 2 vmrghw <3,0,1,2>, RHS + 3362966045U, // <3,u,0,6>: Cost 3 vmrglw <1,2,3,0>, <3,4,u,6> + 2289225032U, // <3,u,0,7>: Cost 2 vmrglw <1,2,3,0>, RHS + 3222509330U, // <3,u,0,u>: Cost 2 vsldoi12 LHS, + 2967322726U, // <3,u,1,0>: Cost 2 vsldoi4 <2,3,u,1>, LHS + 3222061876U, // <3,u,1,1>: Cost 2 vsldoi12 LHS, <1,1,1,1> + 1074583342U, // <3,u,1,2>: Cost 1 vsldoi12 LHS, LHS + 3222509365U, // <3,u,1,3>: Cost 3 vsldoi12 LHS, + 2967326006U, // <3,u,1,4>: Cost 2 vsldoi4 <2,3,u,1>, RHS + 3226711878U, // <3,u,1,5>: Cost 3 vsldoi12 LHS, + 3269842774U, // <3,u,1,6>: Cost 3 vsldoi12 LHS, + 3362975048U, // <3,u,1,7>: Cost 3 vmrglw <1,2,3,1>, RHS + 1074583396U, // <3,u,1,u>: Cost 1 vsldoi12 LHS, LHS + 4172981717U, // <3,u,2,0>: Cost 3 vsldoi8 <2,0,3,u>, <2,0,3,u> + 3227154294U, // <3,u,2,1>: Cost 3 vsldoi12 LHS, + 3100567159U, // <3,u,2,2>: Cost 2 vsldoi8 <2,2,3,u>, <2,2,3,u> + 3222509448U, // <3,u,2,3>: Cost 2 vsldoi12 LHS, + 4041076022U, // <3,u,2,4>: Cost 3 vsldoi4 <2,3,u,2>, RHS + 4176299882U, // <3,u,2,5>: Cost 3 vsldoi8 <2,5,3,u>, <2,5,3,u> + 3103221691U, // <3,u,2,6>: Cost 2 vsldoi8 <2,6,3,u>, <2,6,3,u> + 3269842860U, // <3,u,2,7>: Cost 2 vsldoi12 LHS, + 3226711989U, // <3,u,2,u>: Cost 2 vsldoi12 LHS, + 3222509500U, // <3,u,3,0>: Cost 2 vsldoi12 LHS, + 2167641902U, // <3,u,3,1>: Cost 2 vmrghw <3,3,3,3>, LHS + 3222509519U, // <3,u,3,2>: Cost 3 vsldoi12 LHS, + 1745666150U, // <3,u,3,3>: Cost 1 vspltisw3 LHS + 3222509540U, // <3,u,3,4>: Cost 2 vsldoi12 LHS, + 2167642266U, // <3,u,3,5>: Cost 2 vmrghw <3,3,3,3>, RHS + 4168338112U, // <3,u,3,6>: Cost 3 vsldoi8 <1,2,3,u>, <3,6,u,7> + 2295221576U, // <3,u,3,7>: Cost 2 vmrglw <2,2,3,3>, RHS + 1745666150U, // <3,u,3,u>: Cost 1 vspltisw3 LHS + 3362997187U, // <3,u,4,0>: Cost 3 vmrglw <1,2,3,4>, <1,2,u,0> + 2168477486U, // <3,u,4,1>: Cost 2 vmrghw <3,4,5,6>, LHS + 3362998485U, // <3,u,4,2>: Cost 3 vmrglw <1,2,3,4>, <3,0,u,2> + 2289254556U, // <3,u,4,3>: Cost 2 vmrglw <1,2,3,4>, LHS + 2289255322U, // <3,u,4,4>: Cost 2 vmrglw <1,2,3,4>, <1,2,3,4> + 3222509631U, // <3,u,4,5>: Cost 2 vsldoi12 LHS, + 3362998813U, // <3,u,4,6>: Cost 3 vmrglw <1,2,3,4>, <3,4,u,6> + 2289257800U, // <3,u,4,7>: Cost 2 vmrglw <1,2,3,4>, RHS + 3222509658U, // <3,u,4,u>: Cost 2 vsldoi12 LHS, + 2967355494U, // <3,u,5,0>: Cost 2 vsldoi4 <2,3,u,5>, LHS + 4041098036U, // <3,u,5,1>: Cost 3 vsldoi4 <2,3,u,5>, <1,1,1,1> + 2967357170U, // <3,u,5,2>: Cost 2 vsldoi4 <2,3,u,5>, <2,3,u,5> + 3222509694U, // <3,u,5,3>: Cost 3 vsldoi12 LHS, + 2967358774U, // <3,u,5,4>: Cost 2 vsldoi4 <2,3,u,5>, RHS + 3269840900U, // <3,u,5,5>: Cost 2 vsldoi12 LHS, <5,5,5,5> + 1074583706U, // <3,u,5,6>: Cost 1 vsldoi12 LHS, RHS + 3368316232U, // <3,u,5,7>: Cost 3 vmrglw <2,1,3,5>, RHS + 1074583724U, // <3,u,5,u>: Cost 1 vsldoi12 LHS, RHS + 4041105510U, // <3,u,6,0>: Cost 3 vsldoi4 <2,3,u,6>, LHS + 3227154622U, // <3,u,6,1>: Cost 3 vsldoi12 LHS, + 4041107187U, // <3,u,6,2>: Cost 3 vsldoi4 <2,3,u,6>, <2,3,u,6> + 3222509776U, // <3,u,6,3>: Cost 2 vsldoi12 LHS, + 4041108790U, // <3,u,6,4>: Cost 3 vsldoi4 <2,3,u,6>, RHS + 3243186330U, // <3,u,6,5>: Cost 3 vmrghw <3,6,0,7>, RHS + 3269841720U, // <3,u,6,6>: Cost 2 vsldoi12 LHS, <6,6,6,6> + 3269843181U, // <3,u,6,7>: Cost 2 vsldoi12 LHS, + 3226712317U, // <3,u,6,u>: Cost 2 vsldoi12 LHS, + 3269843200U, // <3,u,7,0>: Cost 2 vsldoi12 LHS, + 3371647049U, // <3,u,7,1>: Cost 3 vmrglw <2,6,3,7>, <0,0,u,1> + 4041115380U, // <3,u,7,2>: Cost 3 vsldoi4 <2,3,u,7>, <2,3,u,7> + 2297905308U, // <3,u,7,3>: Cost 2 vmrglw <2,6,3,7>, LHS + 3269843240U, // <3,u,7,4>: Cost 2 vsldoi12 LHS, + 3371647377U, // <3,u,7,5>: Cost 3 vmrglw <2,6,3,7>, <0,4,u,5> + 3371647216U, // <3,u,7,6>: Cost 3 vmrglw <2,6,3,7>, <0,2,u,6> + 2297908552U, // <3,u,7,7>: Cost 2 vmrglw <2,6,3,7>, RHS + 2297905313U, // <3,u,7,u>: Cost 2 vmrglw <2,6,3,7>, LHS + 3226712401U, // <3,u,u,0>: Cost 2 vsldoi12 LHS, + 3222509915U, // <3,u,u,1>: Cost 2 vsldoi12 LHS, + 1074583909U, // <3,u,u,2>: Cost 1 vsldoi12 LHS, LHS + 1745666150U, // <3,u,u,3>: Cost 1 vspltisw3 LHS + 3226712441U, // <3,u,u,4>: Cost 2 vsldoi12 LHS, + 3222509955U, // <3,u,u,5>: Cost 2 vsldoi12 LHS, + 1074583949U, // <3,u,u,6>: Cost 1 vsldoi12 LHS, RHS + 2289290568U, // <3,u,u,7>: Cost 2 vmrglw <1,2,3,u>, RHS + 1074583963U, // <3,u,u,u>: Cost 1 vsldoi12 LHS, LHS + 3228778496U, // <4,0,0,0>: Cost 3 vsldoi12 <1,2,3,4>, <0,0,0,0> + 2171748454U, // <4,0,0,1>: Cost 2 vmrghw <4,0,5,1>, LHS + 4053075657U, // <4,0,0,2>: Cost 4 vsldoi4 <4,4,0,0>, <2,3,4,0> + 3369675785U, // <4,0,0,3>: Cost 4 vmrglw <2,3,4,0>, <4,2,0,3> + 3221553192U, // <4,0,0,4>: Cost 3 vsldoi12 <0,0,4,4>, <0,0,4,4> + 3245490590U, // <4,0,0,5>: Cost 3 vmrghw <4,0,5,1>, <0,5,1,0> + 3245482477U, // <4,0,0,6>: Cost 4 vmrghw <4,0,5,0>, <0,6,0,7> + 3369676113U, // <4,0,0,7>: Cost 4 vmrglw <2,3,4,0>, <4,6,0,7> + 2171749021U, // <4,0,0,u>: Cost 2 vmrghw <4,0,5,1>, LHS + 4047110246U, // <4,0,1,0>: Cost 3 vsldoi4 <3,4,0,1>, LHS + 4047111066U, // <4,0,1,1>: Cost 3 vsldoi4 <3,4,0,1>, <1,2,3,4> + 3228778598U, // <4,0,1,2>: Cost 2 vsldoi12 <1,2,3,4>, LHS + 4047112656U, // <4,0,1,3>: Cost 3 vsldoi4 <3,4,0,1>, <3,4,0,1> + 4047113526U, // <4,0,1,4>: Cost 3 vsldoi4 <3,4,0,1>, RHS + 4071002214U, // <4,0,1,5>: Cost 3 vsldoi4 <7,4,0,1>, <5,6,7,4> + 4065030747U, // <4,0,1,6>: Cost 4 vsldoi4 <6,4,0,1>, <6,4,0,1> + 4071003444U, // <4,0,1,7>: Cost 3 vsldoi4 <7,4,0,1>, <7,4,0,1> + 3228778652U, // <4,0,1,u>: Cost 2 vsldoi12 <1,2,3,4>, LHS + 4047118438U, // <4,0,2,0>: Cost 4 vsldoi4 <3,4,0,2>, LHS + 3246833766U, // <4,0,2,1>: Cost 3 vmrghw <4,2,5,3>, LHS + 4174317176U, // <4,0,2,2>: Cost 4 vsldoi8 <2,2,4,0>, <2,2,4,0> + 4174980809U, // <4,0,2,3>: Cost 3 vsldoi8 <2,3,4,0>, <2,3,4,0> + 3373672105U, // <4,0,2,4>: Cost 4 vmrglw <3,0,4,2>, <2,3,0,4> + 4213466979U, // <4,0,2,5>: Cost 4 vsldoi8 , <2,5,3,1> + 4174981050U, // <4,0,2,6>: Cost 4 vsldoi8 <2,3,4,0>, <2,6,3,7> + 3386280568U, // <4,0,2,7>: Cost 5 vmrglw <5,1,4,2>, <3,6,0,7> + 4178298974U, // <4,0,2,u>: Cost 3 vsldoi8 <2,u,4,0>, <2,u,4,0> + 4035182694U, // <4,0,3,0>: Cost 4 vsldoi4 <1,4,0,3>, LHS + 3223322880U, // <4,0,3,1>: Cost 3 vsldoi12 <0,3,1,4>, <0,3,1,4> + 4174981460U, // <4,0,3,2>: Cost 4 vsldoi8 <2,3,4,0>, <3,2,4,3> + 3223322898U, // <4,0,3,3>: Cost 4 vsldoi12 <0,3,1,4>, <0,3,3,4> + 4035185974U, // <4,0,3,4>: Cost 4 vsldoi4 <1,4,0,3>, RHS + 4182280772U, // <4,0,3,5>: Cost 4 vsldoi8 <3,5,4,0>, <3,5,4,0> + 4174981788U, // <4,0,3,6>: Cost 4 vsldoi8 <2,3,4,0>, <3,6,4,7> + 4183608038U, // <4,0,3,7>: Cost 4 vsldoi8 <3,7,4,0>, <3,7,4,0> + 3223322880U, // <4,0,3,u>: Cost 3 vsldoi12 <0,3,1,4>, <0,3,1,4> + 4201524114U, // <4,0,4,0>: Cost 3 vsldoi8 <6,7,4,0>, <4,0,5,1> + 2174353510U, // <4,0,4,1>: Cost 2 vmrghw <4,4,4,4>, LHS + 3235193177U, // <4,0,4,2>: Cost 4 vsldoi12 <2,3,0,4>, <0,4,2,3> + 4174982235U, // <4,0,4,3>: Cost 4 vsldoi8 <2,3,4,0>, <4,3,0,4> + 3248095570U, // <4,0,4,4>: Cost 3 vmrghw <4,4,4,4>, <0,4,1,5> + 4174982454U, // <4,0,4,5>: Cost 3 vsldoi8 <2,3,4,0>, RHS + 4174982481U, // <4,0,4,6>: Cost 4 vsldoi8 <2,3,4,0>, <4,6,0,7> + 4071028023U, // <4,0,4,7>: Cost 4 vsldoi4 <7,4,0,4>, <7,4,0,4> + 2174354077U, // <4,0,4,u>: Cost 2 vmrghw <4,4,4,4>, LHS + 2175188992U, // <4,0,5,0>: Cost 2 vmrghw RHS, <0,0,0,0> + 1101447270U, // <4,0,5,1>: Cost 1 vmrghw RHS, LHS + 3248930989U, // <4,0,5,2>: Cost 3 vmrghw RHS, <0,2,1,2> + 4047145428U, // <4,0,5,3>: Cost 3 vsldoi4 <3,4,0,5>, <3,4,0,5> + 2175189330U, // <4,0,5,4>: Cost 2 vmrghw RHS, <0,4,1,5> + 3248939490U, // <4,0,5,5>: Cost 3 vmrghw RHS, <0,5,u,5> + 3248931318U, // <4,0,5,6>: Cost 3 vmrghw RHS, <0,6,1,7> + 4071036216U, // <4,0,5,7>: Cost 3 vsldoi4 <7,4,0,5>, <7,4,0,5> + 1101447837U, // <4,0,5,u>: Cost 1 vmrghw RHS, LHS + 3249471498U, // <4,0,6,0>: Cost 4 vmrghw <4,6,5,1>, <0,0,1,1> + 3249479782U, // <4,0,6,1>: Cost 3 vmrghw <4,6,5,2>, LHS + 4201525754U, // <4,0,6,2>: Cost 4 vsldoi8 <6,7,4,0>, <6,2,7,3> + 4198871597U, // <4,0,6,3>: Cost 4 vsldoi8 <6,3,4,0>, <6,3,4,0> + 3230548497U, // <4,0,6,4>: Cost 4 vsldoi12 <1,5,0,4>, <0,6,4,7> + 4201525995U, // <4,0,6,5>: Cost 4 vsldoi8 <6,7,4,0>, <6,5,7,1> + 3249513012U, // <4,0,6,6>: Cost 4 vmrghw <4,6,5,6>, <0,6,u,6> + 4201526129U, // <4,0,6,7>: Cost 3 vsldoi8 <6,7,4,0>, <6,7,4,0> + 3249480349U, // <4,0,6,u>: Cost 3 vmrghw <4,6,5,2>, LHS + 3377692672U, // <4,0,7,0>: Cost 4 vmrglw <3,6,4,7>, <0,0,0,0> + 3250126950U, // <4,0,7,1>: Cost 3 vmrghw <4,7,5,0>, LHS + 4178302154U, // <4,0,7,2>: Cost 5 vsldoi8 <2,u,4,0>, <7,2,6,3> + 4204844294U, // <4,0,7,3>: Cost 4 vsldoi8 <7,3,4,0>, <7,3,4,0> + 3250127186U, // <4,0,7,4>: Cost 4 vmrghw <4,7,5,0>, <0,4,1,5> + 4206171560U, // <4,0,7,5>: Cost 4 vsldoi8 <7,5,4,0>, <7,5,4,0> + 3250127350U, // <4,0,7,6>: Cost 5 vmrghw <4,7,5,0>, <0,6,1,7> + 4201526892U, // <4,0,7,7>: Cost 4 vsldoi8 <6,7,4,0>, <7,7,7,7> + 3250127517U, // <4,0,7,u>: Cost 3 vmrghw <4,7,5,0>, LHS + 2177179648U, // <4,0,u,0>: Cost 2 vmrghw RHS, <0,0,0,0> + 1103437926U, // <4,0,u,1>: Cost 1 vmrghw RHS, LHS + 3228779165U, // <4,0,u,2>: Cost 2 vsldoi12 <1,2,3,4>, LHS + 4047170007U, // <4,0,u,3>: Cost 3 vsldoi4 <3,4,0,u>, <3,4,0,u> + 2177179986U, // <4,0,u,4>: Cost 2 vmrghw RHS, <0,4,1,5> + 4174985370U, // <4,0,u,5>: Cost 3 vsldoi8 <2,3,4,0>, RHS + 3250921974U, // <4,0,u,6>: Cost 3 vmrghw RHS, <0,6,1,7> + 4071060795U, // <4,0,u,7>: Cost 3 vsldoi4 <7,4,0,u>, <7,4,0,u> + 1103438493U, // <4,0,u,u>: Cost 1 vmrghw RHS, LHS + 4077035622U, // <4,1,0,0>: Cost 3 vsldoi4 , LHS + 4166361190U, // <4,1,0,1>: Cost 3 vsldoi8 <0,u,4,1>, LHS + 3245204378U, // <4,1,0,2>: Cost 3 vmrghw <4,0,1,2>, <1,2,3,4> + 4047178200U, // <4,1,0,3>: Cost 4 vsldoi4 <3,4,1,0>, <3,4,1,0> + 4166361426U, // <4,1,0,4>: Cost 3 vsldoi8 <0,u,4,1>, <0,4,1,5> + 3361046866U, // <4,1,0,5>: Cost 4 vmrglw <0,u,4,0>, <0,4,1,5> + 4077040122U, // <4,1,0,6>: Cost 4 vsldoi4 , <6,2,7,3> + 4077040634U, // <4,1,0,7>: Cost 4 vsldoi4 , <7,0,1,2> + 4166361773U, // <4,1,0,u>: Cost 3 vsldoi8 <0,u,4,1>, <0,u,4,1> + 4167025406U, // <4,1,1,0>: Cost 4 vsldoi8 <1,0,4,1>, <1,0,4,1> + 3227968311U, // <4,1,1,1>: Cost 3 vsldoi12 <1,1,1,4>, <1,1,1,4> + 4174988186U, // <4,1,1,2>: Cost 3 vsldoi8 <2,3,4,1>, <1,2,3,4> + 3361057810U, // <4,1,1,3>: Cost 4 vmrglw <0,u,4,1>, <4,2,1,3> + 3223323474U, // <4,1,1,4>: Cost 4 vsldoi12 <0,3,1,4>, <1,1,4,4> + 3361055058U, // <4,1,1,5>: Cost 3 vmrglw <0,u,4,1>, <0,4,1,5> + 4166362355U, // <4,1,1,6>: Cost 4 vsldoi8 <0,u,4,1>, <1,6,5,7> + 3361058138U, // <4,1,1,7>: Cost 4 vmrglw <0,u,4,1>, <4,6,1,7> + 3246392704U, // <4,1,1,u>: Cost 3 vmrghw <4,1,u,3>, <1,u,3,4> + 4047192166U, // <4,1,2,0>: Cost 3 vsldoi4 <3,4,1,2>, LHS + 4047192986U, // <4,1,2,1>: Cost 3 vsldoi4 <3,4,1,2>, <1,2,3,4> + 4166362728U, // <4,1,2,2>: Cost 4 vsldoi8 <0,u,4,1>, <2,2,2,2> + 3228779418U, // <4,1,2,3>: Cost 2 vsldoi12 <1,2,3,4>, <1,2,3,4> + 4047195446U, // <4,1,2,4>: Cost 3 vsldoi4 <3,4,1,2>, RHS + 3361063250U, // <4,1,2,5>: Cost 4 vmrglw <0,u,4,2>, <0,4,1,5> + 4166363066U, // <4,1,2,6>: Cost 4 vsldoi8 <0,u,4,1>, <2,6,3,7> + 4071085374U, // <4,1,2,7>: Cost 4 vsldoi4 <7,4,1,2>, <7,4,1,2> + 3229148103U, // <4,1,2,u>: Cost 2 vsldoi12 <1,2,u,4>, <1,2,u,4> + 4178970800U, // <4,1,3,0>: Cost 3 vsldoi8 <3,0,4,1>, <3,0,4,1> + 3228779481U, // <4,1,3,1>: Cost 4 vsldoi12 <1,2,3,4>, <1,3,1,4> + 3229369314U, // <4,1,3,2>: Cost 4 vsldoi12 <1,3,2,4>, <1,3,2,4> + 4166363548U, // <4,1,3,3>: Cost 4 vsldoi8 <0,u,4,1>, <3,3,3,3> + 4184279554U, // <4,1,3,4>: Cost 3 vsldoi8 <3,u,4,1>, <3,4,5,6> + 3361071442U, // <4,1,3,5>: Cost 4 vmrglw <0,u,4,3>, <0,4,1,5> + 4174989980U, // <4,1,3,6>: Cost 4 vsldoi8 <2,3,4,1>, <3,6,4,7> + 4178307779U, // <4,1,3,7>: Cost 5 vsldoi8 <2,u,4,1>, <3,7,0,1> + 4184279864U, // <4,1,3,u>: Cost 3 vsldoi8 <3,u,4,1>, <3,u,4,1> + 4077068390U, // <4,1,4,0>: Cost 3 vsldoi4 , LHS + 3248096052U, // <4,1,4,1>: Cost 3 vmrghw <4,4,4,4>, <1,1,1,1> + 3248186266U, // <4,1,4,2>: Cost 3 vmrghw <4,4,5,6>, <1,2,3,4> + 3223323708U, // <4,1,4,3>: Cost 4 vsldoi12 <0,3,1,4>, <1,4,3,4> + 4077071568U, // <4,1,4,4>: Cost 3 vsldoi4 , <4,4,4,4> + 4166364470U, // <4,1,4,5>: Cost 3 vsldoi8 <0,u,4,1>, RHS + 4166364506U, // <4,1,4,6>: Cost 4 vsldoi8 <0,u,4,1>, <4,6,1,7> + 3263136860U, // <4,1,4,7>: Cost 4 vsldoi12 <7,0,1,4>, <1,4,7,0> + 4166364713U, // <4,1,4,u>: Cost 3 vsldoi8 <0,u,4,1>, RHS + 2955559250U, // <4,1,5,0>: Cost 2 vsldoi4 <0,4,1,5>, <0,4,1,5> + 2175189812U, // <4,1,5,1>: Cost 2 vmrghw RHS, <1,1,1,1> + 2175189910U, // <4,1,5,2>: Cost 2 vmrghw RHS, <1,2,3,0> + 4029302934U, // <4,1,5,3>: Cost 3 vsldoi4 <0,4,1,5>, <3,0,1,2> + 2955562294U, // <4,1,5,4>: Cost 2 vsldoi4 <0,4,1,5>, RHS + 4029304836U, // <4,1,5,5>: Cost 3 vsldoi4 <0,4,1,5>, <5,5,5,5> + 3248932047U, // <4,1,5,6>: Cost 3 vmrghw RHS, <1,6,1,7> + 4077081594U, // <4,1,5,7>: Cost 3 vsldoi4 , <7,0,1,2> + 2955564846U, // <4,1,5,u>: Cost 2 vsldoi4 <0,4,1,5>, LHS + 4184281377U, // <4,1,6,0>: Cost 4 vsldoi8 <3,u,4,1>, <6,0,1,2> + 3228779727U, // <4,1,6,1>: Cost 4 vsldoi12 <1,2,3,4>, <1,6,1,7> + 3249152922U, // <4,1,6,2>: Cost 4 vmrghw <4,6,0,7>, <1,2,3,4> + 4184281650U, // <4,1,6,3>: Cost 4 vsldoi8 <3,u,4,1>, <6,3,4,5> + 3223323882U, // <4,1,6,4>: Cost 4 vsldoi12 <0,3,1,4>, <1,6,4,7> + 3361096018U, // <4,1,6,5>: Cost 4 vmrglw <0,u,4,6>, <0,4,1,5> + 4190917432U, // <4,1,6,6>: Cost 4 vsldoi8 <5,0,4,1>, <6,6,6,6> + 4190917454U, // <4,1,6,7>: Cost 4 vsldoi8 <5,0,4,1>, <6,7,0,1> + 3228779790U, // <4,1,6,u>: Cost 4 vsldoi12 <1,2,3,4>, <1,6,u,7> + 4202861588U, // <4,1,7,0>: Cost 3 vsldoi8 <7,0,4,1>, <7,0,4,1> + 3377692682U, // <4,1,7,1>: Cost 4 vmrglw <3,6,4,7>, <0,0,1,1> + 3377694870U, // <4,1,7,2>: Cost 4 vmrglw <3,6,4,7>, <3,0,1,2> + 4204852487U, // <4,1,7,3>: Cost 4 vsldoi8 <7,3,4,1>, <7,3,4,1> + 4208170342U, // <4,1,7,4>: Cost 3 vsldoi8 <7,u,4,1>, <7,4,5,6> + 3377693010U, // <4,1,7,5>: Cost 4 vmrglw <3,6,4,7>, <0,4,1,5> + 3365749804U, // <4,1,7,6>: Cost 5 vmrglw <1,6,4,7>, <1,4,1,6> + 4190918252U, // <4,1,7,7>: Cost 4 vsldoi8 <5,0,4,1>, <7,7,7,7> + 4208170652U, // <4,1,7,u>: Cost 3 vsldoi8 <7,u,4,1>, <7,u,4,1> + 2955583829U, // <4,1,u,0>: Cost 2 vsldoi4 <0,4,1,u>, <0,4,1,u> + 2177180468U, // <4,1,u,1>: Cost 2 vmrghw RHS, <1,1,1,1> + 2177180566U, // <4,1,u,2>: Cost 2 vmrghw RHS, <1,2,3,0> + 3232761216U, // <4,1,u,3>: Cost 2 vsldoi12 <1,u,3,4>, <1,u,3,4> + 2955586870U, // <4,1,u,4>: Cost 2 vsldoi4 <0,4,1,u>, RHS + 3358458194U, // <4,1,u,5>: Cost 3 vmrglw <0,4,4,u>, <0,4,1,5> + 3250922703U, // <4,1,u,6>: Cost 3 vmrghw RHS, <1,6,1,7> + 4077106170U, // <4,1,u,7>: Cost 3 vsldoi4 , <7,0,1,2> + 2955589422U, // <4,1,u,u>: Cost 2 vsldoi4 <0,4,1,u>, LHS + 4065165414U, // <4,2,0,0>: Cost 4 vsldoi4 <6,4,2,0>, LHS + 4166369382U, // <4,2,0,1>: Cost 4 vsldoi8 <0,u,4,2>, LHS + 3245491816U, // <4,2,0,2>: Cost 3 vmrghw <4,0,5,1>, <2,2,2,2> + 3369672806U, // <4,2,0,3>: Cost 3 vmrglw <2,3,4,0>, LHS + 4166369618U, // <4,2,0,4>: Cost 4 vsldoi8 <0,u,4,2>, <0,4,1,5> + 3245492067U, // <4,2,0,5>: Cost 3 vmrghw <4,0,5,1>, <2,5,3,1> + 3245492154U, // <4,2,0,6>: Cost 3 vmrghw <4,0,5,1>, <2,6,3,7> + 3245492202U, // <4,2,0,7>: Cost 4 vmrghw <4,0,5,1>, <2,7,0,1> + 3369672811U, // <4,2,0,u>: Cost 3 vmrglw <2,3,4,0>, LHS + 4035313766U, // <4,2,1,0>: Cost 4 vsldoi4 <1,4,2,1>, LHS + 3246147107U, // <4,2,1,1>: Cost 4 vmrghw <4,1,5,0>, <2,1,3,5> + 3361056360U, // <4,2,1,2>: Cost 4 vmrglw <0,u,4,1>, <2,2,2,2> + 3361054822U, // <4,2,1,3>: Cost 3 vmrglw <0,u,4,1>, LHS + 4191585332U, // <4,2,1,4>: Cost 4 vsldoi8 <5,1,4,2>, <1,4,2,5> + 3246147426U, // <4,2,1,5>: Cost 4 vmrghw <4,1,5,0>, <2,5,3,0> + 3234309693U, // <4,2,1,6>: Cost 4 vsldoi12 <2,1,6,4>, <2,1,6,4> + 3369682865U, // <4,2,1,7>: Cost 5 vmrglw <2,3,4,1>, <2,6,2,7> + 3361054827U, // <4,2,1,u>: Cost 3 vmrglw <0,u,4,1>, LHS + 3234678357U, // <4,2,2,0>: Cost 4 vsldoi12 <2,2,2,4>, <2,2,0,1> + 4047266714U, // <4,2,2,1>: Cost 4 vsldoi4 <3,4,2,2>, <1,2,3,4> + 3228780136U, // <4,2,2,2>: Cost 3 vsldoi12 <1,2,3,4>, <2,2,2,2> + 3228780146U, // <4,2,2,3>: Cost 3 vsldoi12 <1,2,3,4>, <2,2,3,3> + 3234678392U, // <4,2,2,4>: Cost 4 vsldoi12 <2,2,2,4>, <2,2,4,0> + 3369027341U, // <4,2,2,5>: Cost 4 vmrglw <2,2,4,2>, <2,4,2,5> + 3246860218U, // <4,2,2,6>: Cost 3 vmrghw <4,2,5,6>, <2,6,3,7> + 4071159111U, // <4,2,2,7>: Cost 4 vsldoi4 <7,4,2,2>, <7,4,2,2> + 3228780191U, // <4,2,2,u>: Cost 3 vsldoi12 <1,2,3,4>, <2,2,u,3> + 3228780198U, // <4,2,3,0>: Cost 3 vsldoi12 <1,2,3,4>, <2,3,0,1> + 3227969199U, // <4,2,3,1>: Cost 4 vsldoi12 <1,1,1,4>, <2,3,1,1> + 3228780217U, // <4,2,3,2>: Cost 4 vsldoi12 <1,2,3,4>, <2,3,2,2> + 3228780228U, // <4,2,3,3>: Cost 3 vsldoi12 <1,2,3,4>, <2,3,3,4> + 3228780233U, // <4,2,3,4>: Cost 3 vsldoi12 <1,2,3,4>, <2,3,4,0> + 3235563222U, // <4,2,3,5>: Cost 4 vsldoi12 <2,3,5,4>, <2,3,5,4> + 3247531962U, // <4,2,3,6>: Cost 4 vmrghw <4,3,5,7>, <2,6,3,7> + 3235710696U, // <4,2,3,7>: Cost 3 vsldoi12 <2,3,7,4>, <2,3,7,4> + 3228780270U, // <4,2,3,u>: Cost 3 vsldoi12 <1,2,3,4>, <2,3,u,1> + 3234678519U, // <4,2,4,0>: Cost 4 vsldoi12 <2,2,2,4>, <2,4,0,1> + 3248096803U, // <4,2,4,1>: Cost 4 vmrghw <4,4,4,4>, <2,1,3,5> + 3248096872U, // <4,2,4,2>: Cost 3 vmrghw <4,4,4,4>, <2,2,2,2> + 2308571238U, // <4,2,4,3>: Cost 2 vmrglw <4,4,4,4>, LHS + 3248097045U, // <4,2,4,4>: Cost 3 vmrghw <4,4,4,4>, <2,4,3,4> + 3248179047U, // <4,2,4,5>: Cost 3 vmrghw <4,4,5,5>, <2,5,3,5> + 3248097210U, // <4,2,4,6>: Cost 3 vmrghw <4,4,4,4>, <2,6,3,7> + 4077147193U, // <4,2,4,7>: Cost 4 vsldoi4 , <7,0,u,2> + 2308571243U, // <4,2,4,u>: Cost 2 vmrglw <4,4,4,4>, LHS + 4035346534U, // <4,2,5,0>: Cost 3 vsldoi4 <1,4,2,5>, LHS + 4035347508U, // <4,2,5,1>: Cost 3 vsldoi4 <1,4,2,5>, <1,4,2,5> + 2175190632U, // <4,2,5,2>: Cost 2 vmrghw RHS, <2,2,2,2> + 2295971942U, // <4,2,5,3>: Cost 2 vmrglw <2,3,4,5>, LHS + 4035349814U, // <4,2,5,4>: Cost 3 vsldoi4 <1,4,2,5>, RHS + 3248932712U, // <4,2,5,5>: Cost 3 vmrghw RHS, <2,5,3,6> + 2175190970U, // <4,2,5,6>: Cost 2 vmrghw RHS, <2,6,3,7> + 3248932842U, // <4,2,5,7>: Cost 3 vmrghw RHS, <2,7,0,1> + 2295971947U, // <4,2,5,u>: Cost 2 vmrglw <2,3,4,5>, LHS + 4047298662U, // <4,2,6,0>: Cost 4 vsldoi4 <3,4,2,6>, LHS + 4047299482U, // <4,2,6,1>: Cost 4 vsldoi4 <3,4,2,6>, <1,2,3,4> + 3234678705U, // <4,2,6,2>: Cost 4 vsldoi12 <2,2,2,4>, <2,6,2,7> + 3228780474U, // <4,2,6,3>: Cost 3 vsldoi12 <1,2,3,4>, <2,6,3,7> + 3234678723U, // <4,2,6,4>: Cost 4 vsldoi12 <2,2,2,4>, <2,6,4,7> + 4071190630U, // <4,2,6,5>: Cost 4 vsldoi4 <7,4,2,6>, <5,6,7,4> + 3249481658U, // <4,2,6,6>: Cost 4 vmrghw <4,6,5,2>, <2,6,3,7> + 4201542515U, // <4,2,6,7>: Cost 4 vsldoi8 <6,7,4,2>, <6,7,4,2> + 3228780519U, // <4,2,6,u>: Cost 3 vsldoi12 <1,2,3,4>, <2,6,u,7> + 3270584298U, // <4,2,7,0>: Cost 4 vsldoi12 , <2,7,0,1> + 4203533414U, // <4,2,7,1>: Cost 4 vsldoi8 <7,1,4,2>, <7,1,4,2> + 3371722344U, // <4,2,7,2>: Cost 4 vmrglw <2,6,4,7>, <2,2,2,2> + 3377692774U, // <4,2,7,3>: Cost 3 vmrglw <3,6,4,7>, LHS + 3371722346U, // <4,2,7,4>: Cost 4 vmrglw <2,6,4,7>, <2,2,2,4> + 3371722509U, // <4,2,7,5>: Cost 5 vmrglw <2,6,4,7>, <2,4,2,5> + 3250128826U, // <4,2,7,6>: Cost 4 vmrghw <4,7,5,0>, <2,6,3,7> + 3250128874U, // <4,2,7,7>: Cost 4 vmrghw <4,7,5,0>, <2,7,0,1> + 3377692779U, // <4,2,7,u>: Cost 3 vmrglw <3,6,4,7>, LHS + 3228780603U, // <4,2,u,0>: Cost 3 vsldoi12 <1,2,3,4>, <2,u,0,1> + 4035372087U, // <4,2,u,1>: Cost 3 vsldoi4 <1,4,2,u>, <1,4,2,u> + 2177181288U, // <4,2,u,2>: Cost 2 vmrghw RHS, <2,2,2,2> + 2295996518U, // <4,2,u,3>: Cost 2 vmrglw <2,3,4,u>, LHS + 3228780643U, // <4,2,u,4>: Cost 3 vsldoi12 <1,2,3,4>, <2,u,4,5> + 3250923368U, // <4,2,u,5>: Cost 3 vmrghw RHS, <2,5,3,6> + 2177181626U, // <4,2,u,6>: Cost 2 vmrghw RHS, <2,6,3,7> + 3239028861U, // <4,2,u,7>: Cost 3 vsldoi12 <2,u,7,4>, <2,u,7,4> + 2295996523U, // <4,2,u,u>: Cost 2 vmrglw <2,3,4,u>, LHS + 3245492374U, // <4,3,0,0>: Cost 3 vmrghw <4,0,5,1>, <3,0,1,2> + 3228780694U, // <4,3,0,1>: Cost 3 vsldoi12 <1,2,3,4>, <3,0,1,2> + 3245205844U, // <4,3,0,2>: Cost 4 vmrghw <4,0,1,2>, <3,2,4,3> + 3245492636U, // <4,3,0,3>: Cost 3 vmrghw <4,0,5,1>, <3,3,3,3> + 3369673626U, // <4,3,0,4>: Cost 3 vmrglw <2,3,4,0>, <1,2,3,4> + 4071215206U, // <4,3,0,5>: Cost 4 vsldoi4 <7,4,3,0>, <5,6,7,4> + 3245206172U, // <4,3,0,6>: Cost 4 vmrghw <4,0,1,2>, <3,6,4,7> + 3369674682U, // <4,3,0,7>: Cost 4 vmrglw <2,3,4,0>, <2,6,3,7> + 3228780757U, // <4,3,0,u>: Cost 3 vsldoi12 <1,2,3,4>, <3,0,u,2> + 3361055638U, // <4,3,1,0>: Cost 4 vmrglw <0,u,4,1>, <1,2,3,0> + 3227969766U, // <4,3,1,1>: Cost 4 vsldoi12 <1,1,1,4>, <3,1,1,1> + 4180312986U, // <4,3,1,2>: Cost 3 vsldoi8 <3,2,4,3>, <1,2,3,4> + 3361056370U, // <4,3,1,3>: Cost 4 vmrglw <0,u,4,1>, <2,2,3,3> + 3369681818U, // <4,3,1,4>: Cost 3 vmrglw <2,3,4,1>, <1,2,3,4> + 3361056291U, // <4,3,1,5>: Cost 4 vmrglw <0,u,4,1>, <2,1,3,5> + 3378972520U, // <4,3,1,6>: Cost 4 vmrglw <3,u,4,1>, <2,5,3,6> + 3361056698U, // <4,3,1,7>: Cost 4 vmrglw <0,u,4,1>, <2,6,3,7> + 4180312986U, // <4,3,1,u>: Cost 3 vsldoi8 <3,2,4,3>, <1,2,3,4> + 3228780848U, // <4,3,2,0>: Cost 4 vsldoi12 <1,2,3,4>, <3,2,0,3> + 4047340442U, // <4,3,2,1>: Cost 4 vsldoi4 <3,4,3,2>, <1,2,3,4> + 3228780865U, // <4,3,2,2>: Cost 4 vsldoi12 <1,2,3,4>, <3,2,2,2> + 3240724812U, // <4,3,2,3>: Cost 3 vsldoi12 <3,2,3,4>, <3,2,3,4> + 3228780884U, // <4,3,2,4>: Cost 3 vsldoi12 <1,2,3,4>, <3,2,4,3> + 3223325026U, // <4,3,2,5>: Cost 5 vsldoi12 <0,3,1,4>, <3,2,5,u> + 3228780902U, // <4,3,2,6>: Cost 4 vsldoi12 <1,2,3,4>, <3,2,6,3> + 3255617903U, // <4,3,2,7>: Cost 4 vsldoi12 <5,6,7,4>, <3,2,7,3> + 3241093497U, // <4,3,2,u>: Cost 3 vsldoi12 <3,2,u,4>, <3,2,u,4> + 3247474838U, // <4,3,3,0>: Cost 3 vmrghw <4,3,5,0>, <3,0,1,2> + 4179650819U, // <4,3,3,1>: Cost 4 vsldoi8 <3,1,4,3>, <3,1,4,3> + 4180314452U, // <4,3,3,2>: Cost 3 vsldoi8 <3,2,4,3>, <3,2,4,3> + 3228780956U, // <4,3,3,3>: Cost 3 vsldoi12 <1,2,3,4>, <3,3,3,3> + 3228780966U, // <4,3,3,4>: Cost 3 vsldoi12 <1,2,3,4>, <3,3,4,4> + 3386951446U, // <4,3,3,5>: Cost 4 vmrglw <5,2,4,3>, <2,4,3,5> + 4180314780U, // <4,3,3,6>: Cost 4 vsldoi8 <3,2,4,3>, <3,6,4,7> + 3375007674U, // <4,3,3,7>: Cost 4 vmrglw <3,2,4,3>, <2,6,3,7> + 4184296250U, // <4,3,3,u>: Cost 3 vsldoi8 <3,u,4,3>, <3,u,4,3> + 3228781008U, // <4,3,4,0>: Cost 3 vsldoi12 <1,2,3,4>, <3,4,0,1> + 3228781018U, // <4,3,4,1>: Cost 3 vsldoi12 <1,2,3,4>, <3,4,1,2> + 4041385749U, // <4,3,4,2>: Cost 3 vsldoi4 <2,4,3,4>, <2,4,3,4> + 3248097692U, // <4,3,4,3>: Cost 3 vmrghw <4,4,4,4>, <3,3,3,3> + 3228781048U, // <4,3,4,4>: Cost 3 vsldoi12 <1,2,3,4>, <3,4,4,5> + 3223325186U, // <4,3,4,5>: Cost 3 vsldoi12 <0,3,1,4>, <3,4,5,6> + 4180315500U, // <4,3,4,6>: Cost 4 vsldoi8 <3,2,4,3>, <4,6,3,7> + 3382314938U, // <4,3,4,7>: Cost 3 vmrglw <4,4,4,4>, <2,6,3,7> + 3228781080U, // <4,3,4,u>: Cost 3 vsldoi12 <1,2,3,4>, <3,4,u,1> + 2175191190U, // <4,3,5,0>: Cost 2 vmrghw RHS, <3,0,1,2> + 3248933094U, // <4,3,5,1>: Cost 3 vmrghw RHS, <3,1,1,1> + 4041393942U, // <4,3,5,2>: Cost 3 vsldoi4 <2,4,3,5>, <2,4,3,5> + 2175191452U, // <4,3,5,3>: Cost 2 vmrghw RHS, <3,3,3,3> + 2175191554U, // <4,3,5,4>: Cost 2 vmrghw RHS, <3,4,5,6> + 3369715478U, // <4,3,5,5>: Cost 3 vmrglw <2,3,4,5>, <2,4,3,5> + 3248933496U, // <4,3,5,6>: Cost 3 vmrghw RHS, <3,6,0,7> + 3369715642U, // <4,3,5,7>: Cost 3 vmrglw <2,3,4,5>, <2,6,3,7> + 2175191838U, // <4,3,5,u>: Cost 2 vmrghw RHS, <3,u,1,2> + 3228781176U, // <4,3,6,0>: Cost 4 vsldoi12 <1,2,3,4>, <3,6,0,7> + 4047373210U, // <4,3,6,1>: Cost 4 vsldoi4 <3,4,3,6>, <1,2,3,4> + 3249375572U, // <4,3,6,2>: Cost 4 vmrghw <4,6,3,7>, <3,2,4,3> + 4047374832U, // <4,3,6,3>: Cost 4 vsldoi4 <3,4,3,6>, <3,4,3,6> + 3228781212U, // <4,3,6,4>: Cost 3 vsldoi12 <1,2,3,4>, <3,6,4,7> + 3361097251U, // <4,3,6,5>: Cost 5 vmrglw <0,u,4,6>, <2,1,3,5> + 3249515181U, // <4,3,6,6>: Cost 4 vmrghw <4,6,5,6>, <3,6,6,6> + 3243674292U, // <4,3,6,7>: Cost 3 vsldoi12 <3,6,7,4>, <3,6,7,4> + 3228781212U, // <4,3,6,u>: Cost 3 vsldoi12 <1,2,3,4>, <3,6,4,7> + 3377693590U, // <4,3,7,0>: Cost 4 vmrglw <3,6,4,7>, <1,2,3,0> + 3365751680U, // <4,3,7,1>: Cost 5 vmrglw <1,6,4,7>, <4,0,3,1> + 4204205240U, // <4,3,7,2>: Cost 3 vsldoi8 <7,2,4,3>, <7,2,4,3> + 3377694322U, // <4,3,7,3>: Cost 4 vmrglw <3,6,4,7>, <2,2,3,3> + 3377693594U, // <4,3,7,4>: Cost 3 vmrglw <3,6,4,7>, <1,2,3,4> + 4077244518U, // <4,3,7,5>: Cost 4 vsldoi4 , <5,6,7,4> + 3377695216U, // <4,3,7,6>: Cost 4 vmrglw <3,6,4,7>, <3,4,3,6> + 3375703994U, // <4,3,7,7>: Cost 4 vmrglw <3,3,4,7>, <2,6,3,7> + 4208187038U, // <4,3,7,u>: Cost 3 vsldoi8 <7,u,4,3>, <7,u,4,3> + 2177181846U, // <4,3,u,0>: Cost 2 vmrghw RHS, <3,0,1,2> + 3228781342U, // <4,3,u,1>: Cost 3 vsldoi12 <1,2,3,4>, <3,u,1,2> + 4041418521U, // <4,3,u,2>: Cost 3 vsldoi4 <2,4,3,u>, <2,4,3,u> + 2177182108U, // <4,3,u,3>: Cost 2 vmrghw RHS, <3,3,3,3> + 2177182210U, // <4,3,u,4>: Cost 2 vmrghw RHS, <3,4,5,6> + 3228781382U, // <4,3,u,5>: Cost 3 vsldoi12 <1,2,3,4>, <3,u,5,6> + 3250924152U, // <4,3,u,6>: Cost 3 vmrghw RHS, <3,6,0,7> + 3369740218U, // <4,3,u,7>: Cost 3 vmrglw <2,3,4,u>, <2,6,3,7> + 2177182494U, // <4,3,u,u>: Cost 2 vmrghw RHS, <3,u,1,2> + 2171751314U, // <4,4,0,0>: Cost 2 vmrghw <4,0,5,1>, <4,0,5,1> + 3113877606U, // <4,4,0,1>: Cost 2 vsldoi8 <4,4,4,4>, LHS + 4047398605U, // <4,4,0,2>: Cost 4 vsldoi4 <3,4,4,0>, <2,3,4,4> + 3223325568U, // <4,4,0,3>: Cost 4 vsldoi12 <0,3,1,4>, <4,0,3,1> + 4187619666U, // <4,4,0,4>: Cost 3 vsldoi8 <4,4,4,4>, <0,4,1,5> + 2171751734U, // <4,4,0,5>: Cost 2 vmrghw <4,0,5,1>, RHS + 3245493625U, // <4,4,0,6>: Cost 4 vmrghw <4,0,5,1>, <4,6,5,2> + 3369675420U, // <4,4,0,7>: Cost 4 vmrglw <2,3,4,0>, <3,6,4,7> + 2171751977U, // <4,4,0,u>: Cost 2 vmrghw <4,0,5,1>, RHS + 3369682633U, // <4,4,1,0>: Cost 4 vmrglw <2,3,4,1>, <2,3,4,0> + 3361055405U, // <4,4,1,1>: Cost 3 vmrglw <0,u,4,1>, <0,u,4,1> + 3228781514U, // <4,4,1,2>: Cost 3 vsldoi12 <1,2,3,4>, <4,1,2,3> + 3369683284U, // <4,4,1,3>: Cost 4 vmrglw <2,3,4,1>, <3,2,4,3> + 3384945872U, // <4,4,1,4>: Cost 3 vmrglw <4,u,4,1>, <4,4,4,4> + 3245952310U, // <4,4,1,5>: Cost 3 vmrghw <4,1,2,3>, RHS + 4187620595U, // <4,4,1,6>: Cost 4 vsldoi8 <4,4,4,4>, <1,6,5,7> + 3369683612U, // <4,4,1,7>: Cost 4 vmrglw <2,3,4,1>, <3,6,4,7> + 3232762880U, // <4,4,1,u>: Cost 3 vsldoi12 <1,u,3,4>, <4,1,u,3> + 4047413350U, // <4,4,2,0>: Cost 4 vsldoi4 <3,4,4,2>, LHS + 4047414170U, // <4,4,2,1>: Cost 4 vsldoi4 <3,4,4,2>, <1,2,3,4> + 3246836790U, // <4,4,2,2>: Cost 3 vmrghw <4,2,5,3>, <4,2,5,3> + 4175013581U, // <4,4,2,3>: Cost 3 vsldoi8 <2,3,4,4>, <2,3,4,4> + 4187621141U, // <4,4,2,4>: Cost 3 vsldoi8 <4,4,4,4>, <2,4,3,4> + 3246837046U, // <4,4,2,5>: Cost 3 vmrghw <4,2,5,3>, RHS + 4187621306U, // <4,4,2,6>: Cost 3 vsldoi8 <4,4,4,4>, <2,6,3,7> + 3228781640U, // <4,4,2,7>: Cost 4 vsldoi12 <1,2,3,4>, <4,2,7,3> + 4178331746U, // <4,4,2,u>: Cost 3 vsldoi8 <2,u,4,4>, <2,u,4,4> + 4187621526U, // <4,4,3,0>: Cost 3 vsldoi8 <4,4,4,4>, <3,0,1,2> + 4179659012U, // <4,4,3,1>: Cost 4 vsldoi8 <3,1,4,4>, <3,1,4,4> + 3228781677U, // <4,4,3,2>: Cost 4 vsldoi12 <1,2,3,4>, <4,3,2,4> + 3375008084U, // <4,4,3,3>: Cost 3 vmrglw <3,2,4,3>, <3,2,4,3> + 4181649911U, // <4,4,3,4>: Cost 3 vsldoi8 <3,4,4,4>, <3,4,4,4> + 3247476022U, // <4,4,3,5>: Cost 3 vmrghw <4,3,5,0>, RHS + 3228781713U, // <4,4,3,6>: Cost 4 vsldoi12 <1,2,3,4>, <4,3,6,4> + 3375008412U, // <4,4,3,7>: Cost 4 vmrglw <3,2,4,3>, <3,6,4,7> + 3375008084U, // <4,4,3,u>: Cost 3 vmrglw <3,2,4,3>, <3,2,4,3> + 2979659878U, // <4,4,4,0>: Cost 2 vsldoi4 <4,4,4,4>, LHS + 3382315913U, // <4,4,4,1>: Cost 3 vmrglw <4,4,4,4>, <4,0,4,1> + 4053403240U, // <4,4,4,2>: Cost 3 vsldoi4 <4,4,4,4>, <2,2,2,2> + 4047432183U, // <4,4,4,3>: Cost 3 vsldoi4 <3,4,4,4>, <3,4,4,4> + 1369886006U, // <4,4,4,4>: Cost 1 vspltisw0 RHS + 2174356790U, // <4,4,4,5>: Cost 2 vmrghw <4,4,4,4>, RHS + 4053406202U, // <4,4,4,6>: Cost 3 vsldoi4 <4,4,4,4>, <6,2,7,3> + 4071322971U, // <4,4,4,7>: Cost 3 vsldoi4 <7,4,4,4>, <7,4,4,4> + 1369886006U, // <4,4,4,u>: Cost 1 vspltisw0 RHS + 2175191954U, // <4,4,5,0>: Cost 2 vmrghw RHS, <4,0,5,1> + 4047438746U, // <4,4,5,1>: Cost 3 vsldoi4 <3,4,4,5>, <1,2,3,4> + 3248933941U, // <4,4,5,2>: Cost 3 vmrghw RHS, <4,2,5,2> + 4047440376U, // <4,4,5,3>: Cost 3 vsldoi4 <3,4,4,5>, <3,4,4,5> + 2175192282U, // <4,4,5,4>: Cost 2 vmrghw RHS, <4,4,5,5> + 1101450550U, // <4,4,5,5>: Cost 1 vmrghw RHS, RHS + 3228781878U, // <4,4,5,6>: Cost 2 vsldoi12 <1,2,3,4>, RHS + 3248942536U, // <4,4,5,7>: Cost 3 vmrghw RHS, <4,7,5,0> + 1101450793U, // <4,4,5,u>: Cost 1 vmrghw RHS, RHS + 3249482642U, // <4,4,6,0>: Cost 4 vmrghw <4,6,5,2>, <4,0,5,1> + 4161081771U, // <4,4,6,1>: Cost 4 vsldoi8 <0,0,4,4>, <6,1,7,5> + 4187623930U, // <4,4,6,2>: Cost 3 vsldoi8 <4,4,4,4>, <6,2,7,3> + 4198904369U, // <4,4,6,3>: Cost 4 vsldoi8 <6,3,4,4>, <6,3,4,4> + 4187624093U, // <4,4,6,4>: Cost 3 vsldoi8 <4,4,4,4>, <6,4,7,4> + 3249483062U, // <4,4,6,5>: Cost 3 vmrghw <4,6,5,2>, RHS + 3249483129U, // <4,4,6,6>: Cost 3 vmrghw <4,6,5,2>, <4,6,5,2> + 4201558901U, // <4,4,6,7>: Cost 3 vsldoi8 <6,7,4,4>, <6,7,4,4> + 3249483305U, // <4,4,6,u>: Cost 3 vmrghw <4,6,5,2>, RHS + 4187624442U, // <4,4,7,0>: Cost 3 vsldoi8 <4,4,4,4>, <7,0,1,2> + 3377694410U, // <4,4,7,1>: Cost 4 vmrglw <3,6,4,7>, <2,3,4,1> + 3264613808U, // <4,4,7,2>: Cost 4 vsldoi12 <7,2,3,4>, <4,7,2,3> + 3377695060U, // <4,4,7,3>: Cost 4 vmrglw <3,6,4,7>, <3,2,4,3> + 4205540699U, // <4,4,7,4>: Cost 3 vsldoi8 <7,4,4,4>, <7,4,4,4> + 3250130230U, // <4,4,7,5>: Cost 3 vmrghw <4,7,5,0>, RHS + 3267562968U, // <4,4,7,6>: Cost 4 vsldoi12 <7,6,7,4>, <4,7,6,7> + 3377695388U, // <4,4,7,7>: Cost 3 vmrglw <3,6,4,7>, <3,6,4,7> + 3250130473U, // <4,4,7,u>: Cost 3 vmrghw <4,7,5,0>, RHS + 2177182610U, // <4,4,u,0>: Cost 2 vmrghw RHS, <4,0,5,1> + 3113883438U, // <4,4,u,1>: Cost 2 vsldoi8 <4,4,4,4>, LHS + 3250924597U, // <4,4,u,2>: Cost 3 vmrghw RHS, <4,2,5,2> + 4047464955U, // <4,4,u,3>: Cost 3 vsldoi4 <3,4,4,u>, <3,4,4,u> + 1369886006U, // <4,4,u,4>: Cost 1 vspltisw0 RHS + 1103441206U, // <4,4,u,5>: Cost 1 vmrghw RHS, RHS + 3228782121U, // <4,4,u,6>: Cost 2 vsldoi12 <1,2,3,4>, RHS + 3250925000U, // <4,4,u,7>: Cost 3 vmrghw RHS, <4,7,5,0> + 1103441449U, // <4,4,u,u>: Cost 1 vmrghw RHS, RHS + 4175020032U, // <4,5,0,0>: Cost 3 vsldoi8 <2,3,4,5>, <0,0,0,0> + 3101278310U, // <4,5,0,1>: Cost 2 vsldoi8 <2,3,4,5>, LHS + 4047472334U, // <4,5,0,2>: Cost 3 vsldoi4 <3,4,5,0>, <2,3,4,5> + 4047473148U, // <4,5,0,3>: Cost 3 vsldoi4 <3,4,5,0>, <3,4,5,0> + 4163740013U, // <4,5,0,4>: Cost 3 vsldoi8 <0,4,4,5>, <0,4,4,5> + 3245494276U, // <4,5,0,5>: Cost 3 vmrghw <4,0,5,1>, <5,5,5,5> + 4071363446U, // <4,5,0,6>: Cost 3 vsldoi4 <7,4,5,0>, <6,7,4,5> + 4071363936U, // <4,5,0,7>: Cost 3 vsldoi4 <7,4,5,0>, <7,4,5,0> + 3101278877U, // <4,5,0,u>: Cost 2 vsldoi8 <2,3,4,5>, LHS + 3361057762U, // <4,5,1,0>: Cost 4 vmrglw <0,u,4,1>, <4,1,5,0> + 4167721811U, // <4,5,1,1>: Cost 3 vsldoi8 <1,1,4,5>, <1,1,4,5> + 4175020950U, // <4,5,1,2>: Cost 3 vsldoi8 <2,3,4,5>, <1,2,3,0> + 3361055659U, // <4,5,1,3>: Cost 4 vmrglw <0,u,4,1>, <1,2,5,3> + 4163740751U, // <4,5,1,4>: Cost 4 vsldoi8 <0,4,4,5>, <1,4,5,5> + 4170376343U, // <4,5,1,5>: Cost 3 vsldoi8 <1,5,4,5>, <1,5,4,5> + 3378973186U, // <4,5,1,6>: Cost 3 vmrglw <3,u,4,1>, <3,4,5,6> + 3361055987U, // <4,5,1,7>: Cost 4 vmrglw <0,u,4,1>, <1,6,5,7> + 4172367242U, // <4,5,1,u>: Cost 3 vsldoi8 <1,u,4,5>, <1,u,4,5> + 4047487078U, // <4,5,2,0>: Cost 3 vsldoi4 <3,4,5,2>, LHS + 4163741219U, // <4,5,2,1>: Cost 4 vsldoi8 <0,4,4,5>, <2,1,3,5> + 4174358141U, // <4,5,2,2>: Cost 3 vsldoi8 <2,2,4,5>, <2,2,4,5> + 3101279950U, // <4,5,2,3>: Cost 2 vsldoi8 <2,3,4,5>, <2,3,4,5> + 4175021846U, // <4,5,2,4>: Cost 3 vsldoi8 <2,3,4,5>, <2,4,3,5> + 4175021928U, // <4,5,2,5>: Cost 4 vsldoi8 <2,3,4,5>, <2,5,3,6> + 4175022010U, // <4,5,2,6>: Cost 3 vsldoi8 <2,3,4,5>, <2,6,3,7> + 4177676306U, // <4,5,2,7>: Cost 4 vsldoi8 <2,7,4,5>, <2,7,4,5> + 3104598115U, // <4,5,2,u>: Cost 2 vsldoi8 <2,u,4,5>, <2,u,4,5> + 4175022230U, // <4,5,3,0>: Cost 3 vsldoi8 <2,3,4,5>, <3,0,1,2> + 4167723241U, // <4,5,3,1>: Cost 4 vsldoi8 <1,1,4,5>, <3,1,1,4> + 4175022412U, // <4,5,3,2>: Cost 3 vsldoi8 <2,3,4,5>, <3,2,3,4> + 4175022492U, // <4,5,3,3>: Cost 3 vsldoi8 <2,3,4,5>, <3,3,3,3> + 4175022588U, // <4,5,3,4>: Cost 3 vsldoi8 <2,3,4,5>, <3,4,5,0> + 4182321737U, // <4,5,3,5>: Cost 4 vsldoi8 <3,5,4,5>, <3,5,4,5> + 4201564852U, // <4,5,3,6>: Cost 3 vsldoi8 <6,7,4,5>, <3,6,7,4> + 4183649003U, // <4,5,3,7>: Cost 3 vsldoi8 <3,7,4,5>, <3,7,4,5> + 4175022878U, // <4,5,3,u>: Cost 3 vsldoi8 <2,3,4,5>, <3,u,1,2> + 4047503462U, // <4,5,4,0>: Cost 3 vsldoi4 <3,4,5,4>, LHS + 3382315922U, // <4,5,4,1>: Cost 3 vmrglw <4,4,4,4>, <4,0,5,1> + 4175023158U, // <4,5,4,2>: Cost 3 vsldoi8 <2,3,4,5>, <4,2,5,3> + 4047505920U, // <4,5,4,3>: Cost 3 vsldoi4 <3,4,5,4>, <3,4,5,4> + 4175023322U, // <4,5,4,4>: Cost 3 vsldoi8 <2,3,4,5>, <4,4,5,5> + 3101281590U, // <4,5,4,5>: Cost 2 vsldoi8 <2,3,4,5>, RHS + 4175023486U, // <4,5,4,6>: Cost 3 vsldoi8 <2,3,4,5>, <4,6,5,7> + 4071396708U, // <4,5,4,7>: Cost 3 vsldoi4 <7,4,5,4>, <7,4,5,4> + 3101281833U, // <4,5,4,u>: Cost 2 vsldoi8 <2,3,4,5>, RHS + 2979741798U, // <4,5,5,0>: Cost 2 vsldoi4 <4,4,5,5>, LHS + 3386306074U, // <4,5,5,1>: Cost 3 vmrglw <5,1,4,5>, <4,u,5,1> + 4053485262U, // <4,5,5,2>: Cost 3 vsldoi4 <4,4,5,5>, <2,3,4,5> + 3369716790U, // <4,5,5,3>: Cost 3 vmrglw <2,3,4,5>, <4,2,5,3> + 2979744986U, // <4,5,5,4>: Cost 2 vsldoi4 <4,4,5,5>, <4,4,5,5> + 2175201284U, // <4,5,5,5>: Cost 2 vmrghw RHS, <5,5,5,5> + 2175201378U, // <4,5,5,6>: Cost 2 vmrghw RHS, <5,6,7,0> + 3369717118U, // <4,5,5,7>: Cost 3 vmrglw <2,3,4,5>, <4,6,5,7> + 2175348996U, // <4,5,5,u>: Cost 2 vmrghw RHS, <5,u,7,0> + 2973778022U, // <4,5,6,0>: Cost 2 vsldoi4 <3,4,5,6>, LHS + 4035576912U, // <4,5,6,1>: Cost 3 vsldoi4 <1,4,5,6>, <1,4,5,6> + 4041549609U, // <4,5,6,2>: Cost 3 vsldoi4 <2,4,5,6>, <2,4,5,6> + 2973780482U, // <4,5,6,3>: Cost 2 vsldoi4 <3,4,5,6>, <3,4,5,6> + 2973781302U, // <4,5,6,4>: Cost 2 vsldoi4 <3,4,5,6>, RHS + 4047523608U, // <4,5,6,5>: Cost 3 vsldoi4 <3,4,5,6>, <5,2,6,3> + 4065440397U, // <4,5,6,6>: Cost 3 vsldoi4 <6,4,5,6>, <6,4,5,6> + 27705344U, // <4,5,6,7>: Cost 0 copy RHS + 27705344U, // <4,5,6,u>: Cost 0 copy RHS + 4201567226U, // <4,5,7,0>: Cost 3 vsldoi8 <6,7,4,5>, <7,0,1,2> + 3255619713U, // <4,5,7,1>: Cost 4 vsldoi12 <5,6,7,4>, <5,7,1,4> + 4175025328U, // <4,5,7,2>: Cost 3 vsldoi8 <2,3,4,5>, <7,2,3,4> + 4204885259U, // <4,5,7,3>: Cost 3 vsldoi8 <7,3,4,5>, <7,3,4,5> + 4201567584U, // <4,5,7,4>: Cost 3 vsldoi8 <6,7,4,5>, <7,4,5,0> + 3250130948U, // <4,5,7,5>: Cost 4 vmrghw <4,7,5,0>, <5,5,5,5> + 4201567768U, // <4,5,7,6>: Cost 3 vsldoi8 <6,7,4,5>, <7,6,7,4> + 4201567852U, // <4,5,7,7>: Cost 3 vsldoi8 <6,7,4,5>, <7,7,7,7> + 4201567874U, // <4,5,7,u>: Cost 3 vsldoi8 <6,7,4,5>, <7,u,1,2> + 2973794406U, // <4,5,u,0>: Cost 2 vsldoi4 <3,4,5,u>, LHS + 3101284142U, // <4,5,u,1>: Cost 2 vsldoi8 <2,3,4,5>, LHS + 4175026053U, // <4,5,u,2>: Cost 3 vsldoi8 <2,3,4,5>, + 2973796868U, // <4,5,u,3>: Cost 2 vsldoi4 <3,4,5,u>, <3,4,5,u> + 2973797686U, // <4,5,u,4>: Cost 2 vsldoi4 <3,4,5,u>, RHS + 3101284506U, // <4,5,u,5>: Cost 2 vsldoi8 <2,3,4,5>, RHS + 2177183842U, // <4,5,u,6>: Cost 2 vmrghw RHS, <5,6,7,0> + 27705344U, // <4,5,u,7>: Cost 0 copy RHS + 27705344U, // <4,5,u,u>: Cost 0 copy RHS + 3245486421U, // <4,6,0,0>: Cost 4 vmrghw <4,0,5,0>, <6,0,7,0> + 4166402150U, // <4,6,0,1>: Cost 4 vsldoi8 <0,u,4,6>, LHS + 3245494778U, // <4,6,0,2>: Cost 3 vmrghw <4,0,5,1>, <6,2,7,3> + 4170383616U, // <4,6,0,3>: Cost 4 vsldoi8 <1,5,4,6>, <0,3,1,4> + 4166402386U, // <4,6,0,4>: Cost 4 vsldoi8 <0,u,4,6>, <0,4,1,5> + 3245495019U, // <4,6,0,5>: Cost 3 vmrghw <4,0,5,1>, <6,5,7,1> + 3245495096U, // <4,6,0,6>: Cost 3 vmrghw <4,0,5,1>, <6,6,6,6> + 3369676086U, // <4,6,0,7>: Cost 3 vmrglw <2,3,4,0>, RHS + 3369676087U, // <4,6,0,u>: Cost 3 vmrglw <2,3,4,0>, RHS + 3378973999U, // <4,6,1,0>: Cost 4 vmrglw <3,u,4,1>, <4,5,6,0> + 3378974648U, // <4,6,1,1>: Cost 4 vmrglw <3,u,4,1>, <5,4,6,1> + 4182328218U, // <4,6,1,2>: Cost 4 vsldoi8 <3,5,4,6>, <1,2,3,4> + 3378974002U, // <4,6,1,3>: Cost 4 vmrglw <3,u,4,1>, <4,5,6,3> + 3378974003U, // <4,6,1,4>: Cost 4 vmrglw <3,u,4,1>, <4,5,6,4> + 4170384536U, // <4,6,1,5>: Cost 4 vsldoi8 <1,5,4,6>, <1,5,4,6> + 3378974734U, // <4,6,1,6>: Cost 4 vmrglw <3,u,4,1>, <5,5,6,6> + 3361058102U, // <4,6,1,7>: Cost 3 vmrglw <0,u,4,1>, RHS + 3361058103U, // <4,6,1,u>: Cost 3 vmrglw <0,u,4,1>, RHS + 4071448678U, // <4,6,2,0>: Cost 4 vsldoi4 <7,4,6,2>, LHS + 4166403619U, // <4,6,2,1>: Cost 5 vsldoi8 <0,u,4,6>, <2,1,3,5> + 3246830073U, // <4,6,2,2>: Cost 4 vmrghw <4,2,5,2>, <6,2,7,2> + 4175029966U, // <4,6,2,3>: Cost 4 vsldoi8 <2,3,4,6>, <2,3,4,5> + 3248910815U, // <4,6,2,4>: Cost 4 vsldoi12 <4,5,6,4>, <6,2,4,3> + 4071452774U, // <4,6,2,5>: Cost 4 vsldoi4 <7,4,6,2>, <5,6,7,4> + 4204226490U, // <4,6,2,6>: Cost 4 vsldoi8 <7,2,4,6>, <2,6,3,7> + 3255620090U, // <4,6,2,7>: Cost 3 vsldoi12 <5,6,7,4>, <6,2,7,3> + 3255620099U, // <4,6,2,u>: Cost 3 vsldoi12 <5,6,7,4>, <6,2,u,3> + 3259085325U, // <4,6,3,0>: Cost 4 vsldoi12 <6,3,0,4>, <6,3,0,4> + 3247477160U, // <4,6,3,1>: Cost 4 vmrghw <4,3,5,0>, <6,1,7,2> + 3259232799U, // <4,6,3,2>: Cost 4 vsldoi12 <6,3,2,4>, <6,3,2,4> + 3259306536U, // <4,6,3,3>: Cost 4 vsldoi12 <6,3,3,4>, <6,3,3,4> + 4170385922U, // <4,6,3,4>: Cost 4 vsldoi8 <1,5,4,6>, <3,4,5,6> + 4182329930U, // <4,6,3,5>: Cost 4 vsldoi8 <3,5,4,6>, <3,5,4,6> + 3398898488U, // <4,6,3,6>: Cost 4 vmrglw <7,2,4,3>, <6,6,6,6> + 3375009078U, // <4,6,3,7>: Cost 3 vmrglw <3,2,4,3>, RHS + 3375009079U, // <4,6,3,u>: Cost 3 vmrglw <3,2,4,3>, RHS + 3248910939U, // <4,6,4,0>: Cost 4 vsldoi12 <4,5,6,4>, <6,4,0,1> + 3248099751U, // <4,6,4,1>: Cost 4 vmrghw <4,4,4,4>, <6,1,7,1> + 3248099834U, // <4,6,4,2>: Cost 3 vmrghw <4,4,4,4>, <6,2,7,3> + 3248910969U, // <4,6,4,3>: Cost 4 vsldoi12 <4,5,6,4>, <6,4,3,4> + 3248099997U, // <4,6,4,4>: Cost 3 vmrghw <4,4,4,4>, <6,4,7,4> + 3248181999U, // <4,6,4,5>: Cost 3 vmrghw <4,4,5,5>, <6,5,7,5> + 3248100152U, // <4,6,4,6>: Cost 3 vmrghw <4,4,4,4>, <6,6,6,6> + 2308574518U, // <4,6,4,7>: Cost 2 vmrglw <4,4,4,4>, RHS + 2308574519U, // <4,6,4,u>: Cost 2 vmrglw <4,4,4,4>, RHS + 3248935201U, // <4,6,5,0>: Cost 3 vmrghw RHS, <6,0,1,2> + 3248943527U, // <4,6,5,1>: Cost 3 vmrghw RHS, <6,1,7,1> + 2175201786U, // <4,6,5,2>: Cost 2 vmrghw RHS, <6,2,7,3> + 3248935474U, // <4,6,5,3>: Cost 3 vmrghw RHS, <6,3,4,5> + 3248935565U, // <4,6,5,4>: Cost 3 vmrghw RHS, <6,4,5,6> + 3248943851U, // <4,6,5,5>: Cost 3 vmrghw RHS, <6,5,7,1> + 2175202104U, // <4,6,5,6>: Cost 2 vmrghw RHS, <6,6,6,6> + 2295975222U, // <4,6,5,7>: Cost 2 vmrglw <2,3,4,5>, RHS + 2295975223U, // <4,6,5,u>: Cost 2 vmrglw <2,3,4,5>, RHS + 3249467681U, // <4,6,6,0>: Cost 4 vmrghw <4,6,5,0>, <6,0,1,2> + 3249476007U, // <4,6,6,1>: Cost 4 vmrghw <4,6,5,1>, <6,1,7,1> + 3249484282U, // <4,6,6,2>: Cost 3 vmrghw <4,6,5,2>, <6,2,7,3> + 3249492530U, // <4,6,6,3>: Cost 4 vmrghw <4,6,5,3>, <6,3,4,5> + 3248911140U, // <4,6,6,4>: Cost 4 vsldoi12 <4,5,6,4>, <6,6,4,4> + 3249509099U, // <4,6,6,5>: Cost 4 vmrghw <4,6,5,5>, <6,5,7,1> + 3249517368U, // <4,6,6,6>: Cost 3 vmrghw <4,6,5,6>, <6,6,6,6> + 3255620418U, // <4,6,6,7>: Cost 3 vsldoi12 <5,6,7,4>, <6,6,7,7> + 3255620427U, // <4,6,6,u>: Cost 3 vsldoi12 <5,6,7,4>, <6,6,u,7> + 3255620430U, // <4,6,7,0>: Cost 3 vsldoi12 <5,6,7,4>, <6,7,0,1> + 3255620439U, // <4,6,7,1>: Cost 4 vsldoi12 <5,6,7,4>, <6,7,1,1> + 3250131450U, // <4,6,7,2>: Cost 4 vmrghw <4,7,5,0>, <6,2,7,3> + 3261961068U, // <4,6,7,3>: Cost 3 vsldoi12 <6,7,3,4>, <6,7,3,4> + 3255620470U, // <4,6,7,4>: Cost 3 vsldoi12 <5,6,7,4>, <6,7,4,5> + 3252671356U, // <4,6,7,5>: Cost 4 vsldoi12 <5,2,3,4>, <6,7,5,2> + 3250131768U, // <4,6,7,6>: Cost 4 vmrghw <4,7,5,0>, <6,6,6,6> + 3377696054U, // <4,6,7,7>: Cost 3 vmrglw <3,6,4,7>, RHS + 3377696055U, // <4,6,7,u>: Cost 3 vmrglw <3,6,4,7>, RHS + 3250925857U, // <4,6,u,0>: Cost 3 vmrghw RHS, <6,0,1,2> + 3250925991U, // <4,6,u,1>: Cost 3 vmrghw RHS, <6,1,7,1> + 2177184250U, // <4,6,u,2>: Cost 2 vmrghw RHS, <6,2,7,3> + 3250926130U, // <4,6,u,3>: Cost 3 vmrghw RHS, <6,3,4,5> + 3250926221U, // <4,6,u,4>: Cost 3 vmrghw RHS, <6,4,5,6> + 3250926315U, // <4,6,u,5>: Cost 3 vmrghw RHS, <6,5,7,1> + 2177184568U, // <4,6,u,6>: Cost 2 vmrghw RHS, <6,6,6,6> + 2295999798U, // <4,6,u,7>: Cost 2 vmrglw <2,3,4,u>, RHS + 2295999799U, // <4,6,u,u>: Cost 2 vmrglw <2,3,4,u>, RHS + 3245495290U, // <4,7,0,0>: Cost 3 vmrghw <4,0,5,1>, <7,0,1,2> + 4182999142U, // <4,7,0,1>: Cost 3 vsldoi8 <3,6,4,7>, LHS + 3245495444U, // <4,7,0,2>: Cost 4 vmrghw <4,0,5,1>, <7,2,0,3> + 4171055360U, // <4,7,0,3>: Cost 4 vsldoi8 <1,6,4,7>, <0,3,1,4> + 3245495608U, // <4,7,0,4>: Cost 3 vmrghw <4,0,5,1>, <7,4,0,5> + 3255620642U, // <4,7,0,5>: Cost 4 vsldoi12 <5,6,7,4>, <7,0,5,6> + 4065538713U, // <4,7,0,6>: Cost 4 vsldoi4 <6,4,7,0>, <6,4,7,0> + 3245495916U, // <4,7,0,7>: Cost 3 vmrghw <4,0,5,1>, <7,7,7,7> + 4182999709U, // <4,7,0,u>: Cost 3 vsldoi8 <3,6,4,7>, LHS + 3385610338U, // <4,7,1,0>: Cost 4 vmrglw <5,0,4,1>, <5,6,7,0> + 4182999860U, // <4,7,1,1>: Cost 4 vsldoi8 <3,6,4,7>, <1,1,1,1> + 4182999962U, // <4,7,1,2>: Cost 3 vsldoi8 <3,6,4,7>, <1,2,3,4> + 3385610746U, // <4,7,1,3>: Cost 4 vmrglw <5,0,4,1>, <6,2,7,3> + 3385610342U, // <4,7,1,4>: Cost 4 vmrglw <5,0,4,1>, <5,6,7,4> + 3385610667U, // <4,7,1,5>: Cost 4 vmrglw <5,0,4,1>, <6,1,7,5> + 4171056362U, // <4,7,1,6>: Cost 4 vsldoi8 <1,6,4,7>, <1,6,4,7> + 3385611074U, // <4,7,1,7>: Cost 4 vmrglw <5,0,4,1>, <6,6,7,7> + 4182999962U, // <4,7,1,u>: Cost 3 vsldoi8 <3,6,4,7>, <1,2,3,4> + 3255620756U, // <4,7,2,0>: Cost 4 vsldoi12 <5,6,7,4>, <7,2,0,3> + 4047635354U, // <4,7,2,1>: Cost 5 vsldoi4 <3,4,7,2>, <1,2,3,4> + 4177028712U, // <4,7,2,2>: Cost 4 vsldoi8 <2,6,4,7>, <2,2,2,2> + 3264615600U, // <4,7,2,3>: Cost 3 vsldoi12 <7,2,3,4>, <7,2,3,4> + 3255620792U, // <4,7,2,4>: Cost 3 vsldoi12 <5,6,7,4>, <7,2,4,3> + 4071526502U, // <4,7,2,5>: Cost 4 vsldoi4 <7,4,7,2>, <5,6,7,4> + 4177029059U, // <4,7,2,6>: Cost 4 vsldoi8 <2,6,4,7>, <2,6,4,7> + 4071527796U, // <4,7,2,7>: Cost 4 vsldoi4 <7,4,7,2>, <7,4,7,2> + 3264984285U, // <4,7,2,u>: Cost 3 vsldoi12 <7,2,u,4>, <7,2,u,4> + 4183001238U, // <4,7,3,0>: Cost 4 vsldoi8 <3,6,4,7>, <3,0,1,2> + 4065559450U, // <4,7,3,1>: Cost 4 vsldoi4 <6,4,7,3>, <1,2,3,4> + 4183001428U, // <4,7,3,2>: Cost 4 vsldoi8 <3,6,4,7>, <3,2,4,3> + 4181010857U, // <4,7,3,3>: Cost 4 vsldoi8 <3,3,4,7>, <3,3,4,7> + 3398897766U, // <4,7,3,4>: Cost 3 vmrglw <7,2,4,3>, <5,6,7,4> + 4182338123U, // <4,7,3,5>: Cost 5 vsldoi8 <3,5,4,7>, <3,5,4,7> + 4183001756U, // <4,7,3,6>: Cost 3 vsldoi8 <3,6,4,7>, <3,6,4,7> + 3398898498U, // <4,7,3,7>: Cost 4 vmrglw <7,2,4,3>, <6,6,7,7> + 4184329022U, // <4,7,3,u>: Cost 3 vsldoi8 <3,u,4,7>, <3,u,4,7> + 3255620916U, // <4,7,4,0>: Cost 3 vsldoi12 <5,6,7,4>, <7,4,0,1> + 4183002058U, // <4,7,4,1>: Cost 4 vsldoi8 <3,6,4,7>, <4,1,2,3> + 4183002184U, // <4,7,4,2>: Cost 4 vsldoi8 <3,6,4,7>, <4,2,7,3> + 3382317562U, // <4,7,4,3>: Cost 3 vmrglw <4,4,4,4>, <6,2,7,3> + 4065570000U, // <4,7,4,4>: Cost 3 vsldoi4 <6,4,7,4>, <4,4,4,4> + 4183002422U, // <4,7,4,5>: Cost 3 vsldoi8 <3,6,4,7>, RHS + 4065571485U, // <4,7,4,6>: Cost 3 vsldoi4 <6,4,7,4>, <6,4,7,4> + 3248100972U, // <4,7,4,7>: Cost 3 vmrghw <4,4,4,4>, <7,7,7,7> + 4183002665U, // <4,7,4,u>: Cost 3 vsldoi8 <3,6,4,7>, RHS + 2175202298U, // <4,7,5,0>: Cost 2 vmrghw RHS, <7,0,1,2> + 3248944202U, // <4,7,5,1>: Cost 3 vmrghw RHS, <7,1,1,1> + 3248936138U, // <4,7,5,2>: Cost 3 vmrghw RHS, <7,2,6,3> + 3248944355U, // <4,7,5,3>: Cost 3 vmrghw RHS, <7,3,0,1> + 2175202662U, // <4,7,5,4>: Cost 2 vmrghw RHS, <7,4,5,6> + 3248944566U, // <4,7,5,5>: Cost 3 vmrghw RHS, <7,5,5,5> + 3248944622U, // <4,7,5,6>: Cost 3 vmrghw RHS, <7,6,2,7> + 2175202924U, // <4,7,5,7>: Cost 2 vmrghw RHS, <7,7,7,7> + 2175202946U, // <4,7,5,u>: Cost 2 vmrghw RHS, <7,u,1,2> + 3249484794U, // <4,7,6,0>: Cost 4 vmrghw <4,6,5,2>, <7,0,1,2> + 3249484874U, // <4,7,6,1>: Cost 5 vmrghw <4,6,5,2>, <7,1,1,1> + 3249525936U, // <4,7,6,2>: Cost 4 vmrghw <4,6,5,7>, <7,2,3,4> + 3386978810U, // <4,7,6,3>: Cost 4 vmrglw <5,2,4,6>, <6,2,7,3> + 3255621120U, // <4,7,6,4>: Cost 3 vsldoi12 <5,6,7,4>, <7,6,4,7> + 4071559270U, // <4,7,6,5>: Cost 4 vsldoi4 <7,4,7,6>, <5,6,7,4> + 3249485294U, // <4,7,6,6>: Cost 4 vmrghw <4,6,5,2>, <7,6,2,7> + 3267565080U, // <4,7,6,7>: Cost 3 vsldoi12 <7,6,7,4>, <7,6,7,4> + 3267638817U, // <4,7,6,u>: Cost 3 vsldoi12 <7,6,u,4>, <7,6,u,4> + 3250131962U, // <4,7,7,0>: Cost 3 vmrghw <4,7,5,0>, <7,0,1,2> + 4053648282U, // <4,7,7,1>: Cost 4 vsldoi4 <4,4,7,7>, <1,2,3,4> + 3250148554U, // <4,7,7,2>: Cost 4 vmrghw <4,7,5,2>, <7,2,6,3> + 3377695816U, // <4,7,7,3>: Cost 4 vmrglw <3,6,4,7>, <4,2,7,3> + 3250165094U, // <4,7,7,4>: Cost 3 vmrghw <4,7,5,4>, <7,4,5,6> + 3250173366U, // <4,7,7,5>: Cost 4 vmrghw <4,7,5,5>, <7,5,5,5> + 4206892544U, // <4,7,7,6>: Cost 3 vsldoi8 <7,6,4,7>, <7,6,4,7> + 3250189932U, // <4,7,7,7>: Cost 3 vmrghw <4,7,5,7>, <7,7,7,7> + 3250198146U, // <4,7,7,u>: Cost 3 vmrghw <4,7,5,u>, <7,u,1,2> + 2177184762U, // <4,7,u,0>: Cost 2 vmrghw RHS, <7,0,1,2> + 4183004974U, // <4,7,u,1>: Cost 3 vsldoi8 <3,6,4,7>, LHS + 3250926757U, // <4,7,u,2>: Cost 3 vmrghw RHS, <7,2,2,2> + 3250926819U, // <4,7,u,3>: Cost 3 vmrghw RHS, <7,3,0,1> + 2177185126U, // <4,7,u,4>: Cost 2 vmrghw RHS, <7,4,5,6> + 4183005338U, // <4,7,u,5>: Cost 3 vsldoi8 <3,6,4,7>, RHS + 3250927086U, // <4,7,u,6>: Cost 3 vmrghw RHS, <7,6,2,7> + 2177185388U, // <4,7,u,7>: Cost 2 vmrghw RHS, <7,7,7,7> + 2177185410U, // <4,7,u,u>: Cost 2 vmrghw RHS, <7,u,1,2> + 2171751314U, // <4,u,0,0>: Cost 2 vmrghw <4,0,5,1>, <4,0,5,1> + 3101302886U, // <4,u,0,1>: Cost 2 vsldoi8 <2,3,4,u>, LHS + 4047693521U, // <4,u,0,2>: Cost 3 vsldoi4 <3,4,u,0>, <2,3,4,u> + 3369672860U, // <4,u,0,3>: Cost 3 vmrglw <2,3,4,0>, LHS + 4163764592U, // <4,u,0,4>: Cost 3 vsldoi8 <0,4,4,u>, <0,4,4,u> + 2171754650U, // <4,u,0,5>: Cost 2 vmrghw <4,0,5,1>, RHS + 4071584633U, // <4,u,0,6>: Cost 3 vsldoi4 <7,4,u,0>, <6,7,4,u> + 3369676104U, // <4,u,0,7>: Cost 3 vmrglw <2,3,4,0>, RHS + 3101303453U, // <4,u,0,u>: Cost 2 vsldoi8 <2,3,4,u>, LHS + 4047700070U, // <4,u,1,0>: Cost 3 vsldoi4 <3,4,u,1>, LHS + 4167746390U, // <4,u,1,1>: Cost 3 vsldoi8 <1,1,4,u>, <1,1,4,u> + 3228784430U, // <4,u,1,2>: Cost 2 vsldoi12 <1,2,3,4>, LHS + 3361054876U, // <4,u,1,3>: Cost 3 vmrglw <0,u,4,1>, LHS + 3372999623U, // <4,u,1,4>: Cost 3 vmrglw <2,u,4,1>, <1,2,u,4> + 4170400922U, // <4,u,1,5>: Cost 3 vsldoi8 <1,5,4,u>, <1,5,4,u> + 3378973186U, // <4,u,1,6>: Cost 3 vmrglw <3,u,4,1>, <3,4,5,6> + 3361058120U, // <4,u,1,7>: Cost 3 vmrglw <0,u,4,1>, RHS + 3228784484U, // <4,u,1,u>: Cost 2 vsldoi12 <1,2,3,4>, LHS + 4047708262U, // <4,u,2,0>: Cost 3 vsldoi4 <3,4,u,2>, LHS + 3246839598U, // <4,u,2,1>: Cost 3 vmrghw <4,2,5,3>, LHS + 4174382720U, // <4,u,2,2>: Cost 3 vsldoi8 <2,2,4,u>, <2,2,4,u> + 3101304529U, // <4,u,2,3>: Cost 2 vsldoi8 <2,3,4,u>, <2,3,4,u> + 3229153169U, // <4,u,2,4>: Cost 3 vsldoi12 <1,2,u,4>, + 3246839962U, // <4,u,2,5>: Cost 3 vmrghw <4,2,5,3>, RHS + 4175046586U, // <4,u,2,6>: Cost 3 vsldoi8 <2,3,4,u>, <2,6,3,7> + 3255621548U, // <4,u,2,7>: Cost 3 vsldoi12 <5,6,7,4>, + 3104622694U, // <4,u,2,u>: Cost 2 vsldoi8 <2,u,4,u>, <2,u,4,u> + 3228784572U, // <4,u,3,0>: Cost 3 vsldoi12 <1,2,3,4>, + 3271104456U, // <4,u,3,1>: Cost 3 vsldoi12 , + 4180355417U, // <4,u,3,2>: Cost 3 vsldoi8 <3,2,4,u>, <3,2,4,u> + 3228784602U, // <4,u,3,3>: Cost 3 vsldoi12 <1,2,3,4>, + 3228784612U, // <4,u,3,4>: Cost 3 vsldoi12 <1,2,3,4>, + 3247478938U, // <4,u,3,5>: Cost 3 vmrghw <4,3,5,0>, RHS + 4183009949U, // <4,u,3,6>: Cost 3 vsldoi8 <3,6,4,u>, <3,6,4,u> + 3375009096U, // <4,u,3,7>: Cost 3 vmrglw <3,2,4,3>, RHS + 3228784644U, // <4,u,3,u>: Cost 3 vsldoi12 <1,2,3,4>, + 2979954790U, // <4,u,4,0>: Cost 2 vsldoi4 <4,4,u,4>, LHS + 2174359342U, // <4,u,4,1>: Cost 2 vmrghw <4,4,4,4>, LHS + 4175047761U, // <4,u,4,2>: Cost 3 vsldoi8 <2,3,4,u>, <4,2,u,3> + 2308571292U, // <4,u,4,3>: Cost 2 vmrglw <4,4,4,4>, LHS + 1369886006U, // <4,u,4,4>: Cost 1 vspltisw0 RHS + 3101306166U, // <4,u,4,5>: Cost 2 vsldoi8 <2,3,4,u>, RHS + 4175048089U, // <4,u,4,6>: Cost 3 vsldoi8 <2,3,4,u>, <4,6,u,7> + 2308574536U, // <4,u,4,7>: Cost 2 vmrglw <4,4,4,4>, RHS + 1369886006U, // <4,u,4,u>: Cost 1 vspltisw0 RHS + 2175194835U, // <4,u,5,0>: Cost 2 vmrghw RHS, + 1101453102U, // <4,u,5,1>: Cost 1 vmrghw RHS, LHS + 2175195013U, // <4,u,5,2>: Cost 2 vmrghw RHS, + 2295971996U, // <4,u,5,3>: Cost 2 vmrglw <2,3,4,5>, LHS + 2175195199U, // <4,u,5,4>: Cost 2 vmrghw RHS, + 1101453466U, // <4,u,5,5>: Cost 1 vmrghw RHS, RHS + 3228784794U, // <4,u,5,6>: Cost 2 vsldoi12 <1,2,3,4>, RHS + 2295975240U, // <4,u,5,7>: Cost 2 vmrglw <2,3,4,5>, RHS + 1101453669U, // <4,u,5,u>: Cost 1 vmrghw RHS, LHS + 2973999206U, // <4,u,6,0>: Cost 2 vsldoi4 <3,4,u,6>, LHS + 4035798123U, // <4,u,6,1>: Cost 3 vsldoi4 <1,4,u,6>, <1,4,u,6> + 4041770820U, // <4,u,6,2>: Cost 3 vsldoi4 <2,4,u,6>, <2,4,u,6> + 2974001693U, // <4,u,6,3>: Cost 2 vsldoi4 <3,4,u,6>, <3,4,u,6> + 2974002486U, // <4,u,6,4>: Cost 2 vsldoi4 <3,4,u,6>, RHS + 3249485978U, // <4,u,6,5>: Cost 3 vmrghw <4,6,5,2>, RHS + 4065661608U, // <4,u,6,6>: Cost 3 vsldoi4 <6,4,u,6>, <6,4,u,6> + 27705344U, // <4,u,6,7>: Cost 0 copy RHS + 27705344U, // <4,u,6,u>: Cost 0 copy RHS + 3255621888U, // <4,u,7,0>: Cost 3 vsldoi12 <5,6,7,4>, + 3250132782U, // <4,u,7,1>: Cost 3 vmrghw <4,7,5,0>, LHS + 4204246205U, // <4,u,7,2>: Cost 3 vsldoi8 <7,2,4,u>, <7,2,4,u> + 3377692828U, // <4,u,7,3>: Cost 3 vmrglw <3,6,4,7>, LHS + 3255621928U, // <4,u,7,4>: Cost 3 vsldoi12 <5,6,7,4>, + 3250133146U, // <4,u,7,5>: Cost 3 vmrghw <4,7,5,0>, RHS + 4206900737U, // <4,u,7,6>: Cost 3 vsldoi8 <7,6,4,u>, <7,6,4,u> + 3377696072U, // <4,u,7,7>: Cost 3 vmrglw <3,6,4,7>, RHS + 3377692833U, // <4,u,7,u>: Cost 3 vmrglw <3,6,4,7>, LHS + 2974015590U, // <4,u,u,0>: Cost 2 vsldoi4 <3,4,u,u>, LHS + 1103443758U, // <4,u,u,1>: Cost 1 vmrghw RHS, LHS + 3228784997U, // <4,u,u,2>: Cost 2 vsldoi12 <1,2,3,4>, LHS + 2295996572U, // <4,u,u,3>: Cost 2 vmrglw <2,3,4,u>, LHS + 1369886006U, // <4,u,u,4>: Cost 1 vspltisw0 RHS + 1103444122U, // <4,u,u,5>: Cost 1 vmrghw RHS, RHS + 3228785037U, // <4,u,u,6>: Cost 2 vsldoi12 <1,2,3,4>, RHS + 27705344U, // <4,u,u,7>: Cost 0 copy RHS + 27705344U, // <4,u,u,u>: Cost 0 copy RHS + 3223994368U, // <5,0,0,0>: Cost 3 vsldoi12 <0,4,1,5>, <0,0,0,0> + 3223994378U, // <5,0,0,1>: Cost 3 vsldoi12 <0,4,1,5>, <0,0,1,1> + 4053739214U, // <5,0,0,2>: Cost 4 vsldoi4 <4,5,0,0>, <2,3,4,5> + 3376385762U, // <5,0,0,3>: Cost 4 vmrglw <3,4,5,0>, <5,2,0,3> + 3223994405U, // <5,0,0,4>: Cost 3 vsldoi12 <0,4,1,5>, <0,0,4,1> + 3241836594U, // <5,0,0,5>: Cost 4 vsldoi12 <3,4,0,5>, <0,0,5,5> + 4185006573U, // <5,0,0,6>: Cost 4 vsldoi8 <4,0,5,0>, <0,6,0,7> + 3376386090U, // <5,0,0,7>: Cost 4 vmrglw <3,4,5,0>, <5,6,0,7> + 3227164745U, // <5,0,0,u>: Cost 3 vsldoi12 <0,u,u,5>, <0,0,u,1> + 4035829862U, // <5,0,1,0>: Cost 3 vsldoi4 <1,5,0,1>, LHS + 4035830895U, // <5,0,1,1>: Cost 3 vsldoi4 <1,5,0,1>, <1,5,0,1> + 3223994470U, // <5,0,1,2>: Cost 2 vsldoi12 <0,4,1,5>, LHS + 4169081849U, // <5,0,1,3>: Cost 4 vsldoi8 <1,3,5,0>, <1,3,5,0> + 4035833142U, // <5,0,1,4>: Cost 3 vsldoi4 <1,5,0,1>, RHS + 4059721683U, // <5,0,1,5>: Cost 3 vsldoi4 <5,5,0,1>, <5,5,0,1> + 4185670899U, // <5,0,1,6>: Cost 4 vsldoi8 <4,1,5,0>, <1,6,5,7> + 3385019000U, // <5,0,1,7>: Cost 4 vmrglw <4,u,5,1>, <3,6,0,7> + 3223994524U, // <5,0,1,u>: Cost 2 vsldoi12 <0,4,1,5>, LHS + 3376398336U, // <5,0,2,0>: Cost 4 vmrglw <3,4,5,2>, <0,0,0,0> + 3252510822U, // <5,0,2,1>: Cost 3 vmrghw <5,2,1,3>, LHS + 4175717992U, // <5,0,2,2>: Cost 4 vsldoi8 <2,4,5,0>, <2,2,2,2> + 4181690062U, // <5,0,2,3>: Cost 3 vsldoi8 <3,4,5,0>, <2,3,4,5> + 3223994567U, // <5,0,2,4>: Cost 4 vsldoi12 <0,4,1,5>, <0,2,4,1> + 3241836754U, // <5,0,2,5>: Cost 4 vsldoi12 <3,4,0,5>, <0,2,5,3> + 4181690298U, // <5,0,2,6>: Cost 4 vsldoi8 <3,4,5,0>, <2,6,3,7> + 4213540842U, // <5,0,2,7>: Cost 4 vsldoi8 , <2,7,0,1> + 3252511389U, // <5,0,2,u>: Cost 3 vmrghw <5,2,1,3>, LHS + 4186998934U, // <5,0,3,0>: Cost 3 vsldoi8 <4,3,5,0>, <3,0,1,2> + 3223994620U, // <5,0,3,1>: Cost 4 vsldoi12 <0,4,1,5>, <0,3,1,0> + 4181690700U, // <5,0,3,2>: Cost 4 vsldoi8 <3,4,5,0>, <3,2,3,4> + 4181690780U, // <5,0,3,3>: Cost 4 vsldoi8 <3,4,5,0>, <3,3,3,3> + 4181690876U, // <5,0,3,4>: Cost 3 vsldoi8 <3,4,5,0>, <3,4,5,0> + 3379726804U, // <5,0,3,5>: Cost 4 vmrglw <4,0,5,3>, <3,4,0,5> + 4205578932U, // <5,0,3,6>: Cost 4 vsldoi8 <7,4,5,0>, <3,6,7,4> + 3363138168U, // <5,0,3,7>: Cost 5 vmrglw <1,2,5,3>, <3,6,0,7> + 4184345408U, // <5,0,3,u>: Cost 3 vsldoi8 <3,u,5,0>, <3,u,5,0> + 4035854438U, // <5,0,4,0>: Cost 3 vsldoi4 <1,5,0,4>, LHS + 3223994706U, // <5,0,4,1>: Cost 2 vsldoi12 <0,4,1,5>, <0,4,1,5> + 3224068443U, // <5,0,4,2>: Cost 4 vsldoi12 <0,4,2,5>, <0,4,2,5> + 4186999940U, // <5,0,4,3>: Cost 3 vsldoi8 <4,3,5,0>, <4,3,5,0> + 3223994733U, // <5,0,4,4>: Cost 3 vsldoi12 <0,4,1,5>, <0,4,4,5> + 4181691702U, // <5,0,4,5>: Cost 3 vsldoi8 <3,4,5,0>, RHS + 4181691774U, // <5,0,4,6>: Cost 4 vsldoi8 <3,4,5,0>, <4,6,5,7> + 4189654472U, // <5,0,4,7>: Cost 3 vsldoi8 <4,7,5,0>, <4,7,5,0> + 3223994706U, // <5,0,4,u>: Cost 2 vsldoi12 <0,4,1,5>, <0,4,1,5> + 3385049088U, // <5,0,5,0>: Cost 3 vmrglw <4,u,5,5>, <0,0,0,0> + 2181070950U, // <5,0,5,1>: Cost 2 vmrghw <5,5,5,5>, LHS + 4181692130U, // <5,0,5,2>: Cost 4 vsldoi8 <3,4,5,0>, <5,2,0,3> + 3241836976U, // <5,0,5,3>: Cost 4 vsldoi12 <3,4,0,5>, <0,5,3,0> + 3254813010U, // <5,0,5,4>: Cost 3 vmrghw <5,5,5,5>, <0,4,1,5> + 3254813154U, // <5,0,5,5>: Cost 3 vmrghw <5,5,5,5>, <0,5,u,5> + 4181692458U, // <5,0,5,6>: Cost 4 vsldoi8 <3,4,5,0>, <5,6,0,7> + 3385051768U, // <5,0,5,7>: Cost 4 vmrglw <4,u,5,5>, <3,6,0,7> + 2181071517U, // <5,0,5,u>: Cost 2 vmrghw <5,5,5,5>, LHS + 3376431104U, // <5,0,6,0>: Cost 3 vmrglw <3,4,5,6>, <0,0,0,0> + 2181840998U, // <5,0,6,1>: Cost 2 vmrghw <5,6,7,0>, LHS + 4189655546U, // <5,0,6,2>: Cost 4 vsldoi8 <4,7,5,0>, <6,2,7,3> + 3376432160U, // <5,0,6,3>: Cost 4 vmrglw <3,4,5,6>, <1,4,0,3> + 3255583058U, // <5,0,6,4>: Cost 3 vmrghw <5,6,7,0>, <0,4,1,5> + 3255583140U, // <5,0,6,5>: Cost 3 vmrghw <5,6,7,0>, <0,5,1,6> + 3376433702U, // <5,0,6,6>: Cost 4 vmrglw <3,4,5,6>, <3,5,0,6> + 4205581174U, // <5,0,6,7>: Cost 3 vsldoi8 <7,4,5,0>, <6,7,4,5> + 2181841565U, // <5,0,6,u>: Cost 2 vmrghw <5,6,7,0>, LHS + 4189656058U, // <5,0,7,0>: Cost 3 vsldoi8 <4,7,5,0>, <7,0,1,2> + 3365823599U, // <5,0,7,1>: Cost 4 vmrglw <1,6,5,7>, <1,5,0,1> + 4211553501U, // <5,0,7,2>: Cost 4 vsldoi8 , <7,2,u,4> + 4187002083U, // <5,0,7,3>: Cost 4 vsldoi8 <4,3,5,0>, <7,3,0,1> + 4205581664U, // <5,0,7,4>: Cost 3 vsldoi8 <7,4,5,0>, <7,4,5,0> + 4189656452U, // <5,0,7,5>: Cost 4 vsldoi8 <4,7,5,0>, <7,5,0,0> + 4205581848U, // <5,0,7,6>: Cost 4 vsldoi8 <7,4,5,0>, <7,6,7,4> + 4189656615U, // <5,0,7,7>: Cost 4 vsldoi8 <4,7,5,0>, <7,7,0,1> + 4208236196U, // <5,0,7,u>: Cost 3 vsldoi8 <7,u,5,0>, <7,u,5,0> + 4035887206U, // <5,0,u,0>: Cost 3 vsldoi4 <1,5,0,u>, LHS + 3226649238U, // <5,0,u,1>: Cost 2 vsldoi12 <0,u,1,5>, <0,u,1,5> + 3223995037U, // <5,0,u,2>: Cost 2 vsldoi12 <0,4,1,5>, LHS + 4181690062U, // <5,0,u,3>: Cost 3 vsldoi8 <3,4,5,0>, <2,3,4,5> + 3223995053U, // <5,0,u,4>: Cost 3 vsldoi12 <0,4,1,5>, <0,u,4,1> + 4181694618U, // <5,0,u,5>: Cost 3 vsldoi8 <3,4,5,0>, RHS + 4181694672U, // <5,0,u,6>: Cost 4 vsldoi8 <3,4,5,0>, + 4213545260U, // <5,0,u,7>: Cost 3 vsldoi8 , + 3223995091U, // <5,0,u,u>: Cost 2 vsldoi12 <0,4,1,5>, LHS + 4190322688U, // <5,1,0,0>: Cost 3 vsldoi8 <4,u,5,1>, <0,0,0,0> + 3116580966U, // <5,1,0,1>: Cost 2 vsldoi8 <4,u,5,1>, LHS + 3384349690U, // <5,1,0,2>: Cost 3 vmrglw <4,7,5,0>, <7,0,1,2> + 4190322940U, // <5,1,0,3>: Cost 4 vsldoi8 <4,u,5,1>, <0,3,1,0> + 4190323026U, // <5,1,0,4>: Cost 3 vsldoi8 <4,u,5,1>, <0,4,1,5> + 3380363602U, // <5,1,0,5>: Cost 3 vmrglw <4,1,5,0>, <0,4,1,5> + 4190323190U, // <5,1,0,6>: Cost 4 vsldoi8 <4,u,5,1>, <0,6,1,7> + 4071732621U, // <5,1,0,7>: Cost 4 vsldoi4 <7,5,1,0>, <7,5,1,0> + 3116581533U, // <5,1,0,u>: Cost 2 vsldoi8 <4,u,5,1>, LHS + 4059791462U, // <5,1,1,0>: Cost 3 vsldoi4 <5,5,1,1>, LHS + 3223995188U, // <5,1,1,1>: Cost 3 vsldoi12 <0,4,1,5>, <1,1,1,1> + 3385018518U, // <5,1,1,2>: Cost 3 vmrglw <4,u,5,1>, <3,0,1,2> + 3385020139U, // <5,1,1,3>: Cost 3 vmrglw <4,u,5,1>, <5,2,1,3> + 3228197715U, // <5,1,1,4>: Cost 3 vsldoi12 <1,1,4,5>, <1,1,4,5> + 3223995228U, // <5,1,1,5>: Cost 3 vsldoi12 <0,4,1,5>, <1,1,5,5> + 3385016497U, // <5,1,1,6>: Cost 4 vmrglw <4,u,5,1>, <0,2,1,6> + 3385020467U, // <5,1,1,7>: Cost 3 vmrglw <4,u,5,1>, <5,6,1,7> + 3228492663U, // <5,1,1,u>: Cost 3 vsldoi12 <1,1,u,5>, <1,1,u,5> + 4035911782U, // <5,1,2,0>: Cost 4 vsldoi4 <1,5,1,2>, LHS + 3226649479U, // <5,1,2,1>: Cost 4 vsldoi12 <0,u,1,5>, <1,2,1,3> + 4190324328U, // <5,1,2,2>: Cost 3 vsldoi8 <4,u,5,1>, <2,2,2,2> + 3223995286U, // <5,1,2,3>: Cost 3 vsldoi12 <0,4,1,5>, <1,2,3,0> + 3228861348U, // <5,1,2,4>: Cost 3 vsldoi12 <1,2,4,5>, <1,2,4,5> + 3223995307U, // <5,1,2,5>: Cost 3 vsldoi12 <0,4,1,5>, <1,2,5,3> + 4190324666U, // <5,1,2,6>: Cost 3 vsldoi8 <4,u,5,1>, <2,6,3,7> + 3268379578U, // <5,1,2,7>: Cost 4 vsldoi12 <7,u,0,5>, <1,2,7,0> + 3223995331U, // <5,1,2,u>: Cost 3 vsldoi12 <0,4,1,5>, <1,2,u,0> + 4190324886U, // <5,1,3,0>: Cost 3 vsldoi8 <4,u,5,1>, <3,0,1,2> + 3363135498U, // <5,1,3,1>: Cost 4 vmrglw <1,2,5,3>, <0,0,1,1> + 3363137686U, // <5,1,3,2>: Cost 4 vmrglw <1,2,5,3>, <3,0,1,2> + 4190325148U, // <5,1,3,3>: Cost 3 vsldoi8 <4,u,5,1>, <3,3,3,3> + 4190325250U, // <5,1,3,4>: Cost 3 vsldoi8 <4,u,5,1>, <3,4,5,6> + 3363135826U, // <5,1,3,5>: Cost 3 vmrglw <1,2,5,3>, <0,4,1,5> + 4190325368U, // <5,1,3,6>: Cost 4 vsldoi8 <4,u,5,1>, <3,6,0,7> + 4190325443U, // <5,1,3,7>: Cost 4 vsldoi8 <4,u,5,1>, <3,7,0,1> + 4190325534U, // <5,1,3,u>: Cost 3 vsldoi8 <4,u,5,1>, <3,u,1,2> + 3111275410U, // <5,1,4,0>: Cost 2 vsldoi8 <4,0,5,1>, <4,0,5,1> + 3229967403U, // <5,1,4,1>: Cost 3 vsldoi12 <1,4,1,5>, <1,4,1,5> + 3230041140U, // <5,1,4,2>: Cost 3 vsldoi12 <1,4,2,5>, <1,4,2,5> + 4190325892U, // <5,1,4,3>: Cost 4 vsldoi8 <4,u,5,1>, <4,3,5,0> + 4190325968U, // <5,1,4,4>: Cost 3 vsldoi8 <4,u,5,1>, <4,4,4,4> + 3116584246U, // <5,1,4,5>: Cost 2 vsldoi8 <4,u,5,1>, RHS + 4188999032U, // <5,1,4,6>: Cost 4 vsldoi8 <4,6,5,1>, <4,6,5,1> + 4189662665U, // <5,1,4,7>: Cost 4 vsldoi8 <4,7,5,1>, <4,7,5,1> + 3116584474U, // <5,1,4,u>: Cost 2 vsldoi8 <4,u,5,1>, <4,u,5,1> + 3223995503U, // <5,1,5,0>: Cost 3 vsldoi12 <0,4,1,5>, <1,5,0,1> + 4190326415U, // <5,1,5,1>: Cost 3 vsldoi8 <4,u,5,1>, <5,1,0,1> + 4190326507U, // <5,1,5,2>: Cost 3 vsldoi8 <4,u,5,1>, <5,2,1,3> + 3223995529U, // <5,1,5,3>: Cost 4 vsldoi12 <0,4,1,5>, <1,5,3,0> + 3223995543U, // <5,1,5,4>: Cost 3 vsldoi12 <0,4,1,5>, <1,5,4,5> + 3362488658U, // <5,1,5,5>: Cost 3 vmrglw <1,1,5,5>, <0,4,1,5> + 4190326835U, // <5,1,5,6>: Cost 3 vsldoi8 <4,u,5,1>, <5,6,1,7> + 4190326909U, // <5,1,5,7>: Cost 4 vsldoi8 <4,u,5,1>, <5,7,1,0> + 3223995575U, // <5,1,5,u>: Cost 3 vsldoi12 <0,4,1,5>, <1,5,u,1> + 4077748326U, // <5,1,6,0>: Cost 3 vsldoi4 , LHS + 3364487826U, // <5,1,6,1>: Cost 3 vmrglw <1,4,5,6>, <0,u,1,1> + 3376433302U, // <5,1,6,2>: Cost 3 vmrglw <3,4,5,6>, <3,0,1,2> + 3364488071U, // <5,1,6,3>: Cost 4 vmrglw <1,4,5,6>, <1,2,1,3> + 3376431360U, // <5,1,6,4>: Cost 3 vmrglw <3,4,5,6>, <0,3,1,4> + 3223995635U, // <5,1,6,5>: Cost 3 vsldoi12 <0,4,1,5>, <1,6,5,7> + 4190327608U, // <5,1,6,6>: Cost 3 vsldoi8 <4,u,5,1>, <6,6,6,6> + 4190327630U, // <5,1,6,7>: Cost 3 vsldoi8 <4,u,5,1>, <6,7,0,1> + 3376431121U, // <5,1,6,u>: Cost 3 vmrglw <3,4,5,6>, <0,0,1,u> + 4190327802U, // <5,1,7,0>: Cost 3 vsldoi8 <4,u,5,1>, <7,0,1,2> + 3365822474U, // <5,1,7,1>: Cost 4 vmrglw <1,6,5,7>, <0,0,1,1> + 3365824662U, // <5,1,7,2>: Cost 4 vmrglw <1,6,5,7>, <3,0,1,2> + 4190328035U, // <5,1,7,3>: Cost 4 vsldoi8 <4,u,5,1>, <7,3,0,1> + 4190328166U, // <5,1,7,4>: Cost 3 vsldoi8 <4,u,5,1>, <7,4,5,6> + 3365822802U, // <5,1,7,5>: Cost 3 vmrglw <1,6,5,7>, <0,4,1,5> + 3365823613U, // <5,1,7,6>: Cost 4 vmrglw <1,6,5,7>, <1,5,1,6> + 4190328428U, // <5,1,7,7>: Cost 3 vsldoi8 <4,u,5,1>, <7,7,7,7> + 4190328450U, // <5,1,7,u>: Cost 3 vsldoi8 <4,u,5,1>, <7,u,1,2> + 3135166198U, // <5,1,u,0>: Cost 2 vsldoi8 , + 3116586798U, // <5,1,u,1>: Cost 2 vsldoi8 <4,u,5,1>, LHS + 3232695672U, // <5,1,u,2>: Cost 3 vsldoi12 <1,u,2,5>, <1,u,2,5> + 3223995772U, // <5,1,u,3>: Cost 3 vsldoi12 <0,4,1,5>, <1,u,3,0> + 3232843146U, // <5,1,u,4>: Cost 3 vsldoi12 <1,u,4,5>, <1,u,4,5> + 3116587162U, // <5,1,u,5>: Cost 2 vsldoi8 <4,u,5,1>, RHS + 4190329040U, // <5,1,u,6>: Cost 3 vsldoi8 <4,u,5,1>, + 4190329088U, // <5,1,u,7>: Cost 3 vsldoi8 <4,u,5,1>, + 3116587365U, // <5,1,u,u>: Cost 2 vsldoi8 <4,u,5,1>, LHS + 4181704704U, // <5,2,0,0>: Cost 4 vsldoi8 <3,4,5,2>, <0,0,0,0> + 4181704806U, // <5,2,0,1>: Cost 3 vsldoi8 <3,4,5,2>, LHS + 3234833861U, // <5,2,0,2>: Cost 4 vsldoi12 <2,2,4,5>, <2,0,2,1> + 3376382054U, // <5,2,0,3>: Cost 3 vmrglw <3,4,5,0>, LHS + 4167770450U, // <5,2,0,4>: Cost 4 vsldoi8 <1,1,5,2>, <0,4,1,5> + 3381027892U, // <5,2,0,5>: Cost 4 vmrglw <4,2,5,0>, <1,4,2,5> + 3238815209U, // <5,2,0,6>: Cost 4 vsldoi12 <2,u,4,5>, <2,0,6,1> + 3408232554U, // <5,2,0,7>: Cost 4 vmrglw , <0,1,2,7> + 3376382059U, // <5,2,0,u>: Cost 3 vmrglw <3,4,5,0>, LHS + 4035977318U, // <5,2,1,0>: Cost 4 vsldoi4 <1,5,2,1>, LHS + 4167770969U, // <5,2,1,1>: Cost 4 vsldoi8 <1,1,5,2>, <1,1,5,2> + 3385017960U, // <5,2,1,2>: Cost 3 vmrglw <4,u,5,1>, <2,2,2,2> + 2311274598U, // <5,2,1,3>: Cost 2 vmrglw <4,u,5,1>, LHS + 4035980598U, // <5,2,1,4>: Cost 4 vsldoi4 <1,5,2,1>, RHS + 3381036084U, // <5,2,1,5>: Cost 4 vmrglw <4,2,5,1>, <1,4,2,5> + 3385018045U, // <5,2,1,6>: Cost 4 vmrglw <4,u,5,1>, <2,3,2,6> + 3385017560U, // <5,2,1,7>: Cost 4 vmrglw <4,u,5,1>, <1,6,2,7> + 2311274603U, // <5,2,1,u>: Cost 2 vmrglw <4,u,5,1>, LHS + 4035985510U, // <5,2,2,0>: Cost 4 vsldoi4 <1,5,2,2>, LHS + 4035986562U, // <5,2,2,1>: Cost 4 vsldoi4 <1,5,2,2>, <1,5,2,2> + 3223996008U, // <5,2,2,2>: Cost 3 vsldoi12 <0,4,1,5>, <2,2,2,2> + 3223996018U, // <5,2,2,3>: Cost 3 vsldoi12 <0,4,1,5>, <2,2,3,3> + 3234834045U, // <5,2,2,4>: Cost 3 vsldoi12 <2,2,4,5>, <2,2,4,5> + 3230041732U, // <5,2,2,5>: Cost 4 vsldoi12 <1,4,2,5>, <2,2,5,3> + 3238815376U, // <5,2,2,6>: Cost 4 vsldoi12 <2,u,4,5>, <2,2,6,6> + 3376402492U, // <5,2,2,7>: Cost 4 vmrglw <3,4,5,2>, <5,6,2,7> + 3223996063U, // <5,2,2,u>: Cost 3 vsldoi12 <0,4,1,5>, <2,2,u,3> + 3223996070U, // <5,2,3,0>: Cost 3 vsldoi12 <0,4,1,5>, <2,3,0,1> + 3223996079U, // <5,2,3,1>: Cost 4 vsldoi12 <0,4,1,5>, <2,3,1,1> + 4053911246U, // <5,2,3,2>: Cost 3 vsldoi4 <4,5,2,3>, <2,3,4,5> + 3363135590U, // <5,2,3,3>: Cost 3 vmrglw <1,2,5,3>, LHS + 3235497678U, // <5,2,3,4>: Cost 2 vsldoi12 <2,3,4,5>, <2,3,4,5> + 3254814423U, // <5,2,3,5>: Cost 3 vsldoi12 <5,5,5,5>, <2,3,5,5> + 3250833121U, // <5,2,3,6>: Cost 4 vsldoi12 <4,u,5,5>, <2,3,6,6> + 4205595371U, // <5,2,3,7>: Cost 4 vsldoi8 <7,4,5,2>, <3,7,4,5> + 3235792626U, // <5,2,3,u>: Cost 2 vsldoi12 <2,3,u,5>, <2,3,u,5> + 3235866363U, // <5,2,4,0>: Cost 4 vsldoi12 <2,4,0,5>, <2,4,0,5> + 4185689060U, // <5,2,4,1>: Cost 3 vsldoi8 <4,1,5,2>, <4,1,5,2> + 3236013837U, // <5,2,4,2>: Cost 3 vsldoi12 <2,4,2,5>, <2,4,2,5> + 3235497750U, // <5,2,4,3>: Cost 3 vsldoi12 <2,3,4,5>, <2,4,3,5> + 3236161311U, // <5,2,4,4>: Cost 4 vsldoi12 <2,4,4,5>, <2,4,4,5> + 4181708086U, // <5,2,4,5>: Cost 3 vsldoi8 <3,4,5,2>, RHS + 4189007225U, // <5,2,4,6>: Cost 3 vsldoi8 <4,6,5,2>, <4,6,5,2> + 4189670858U, // <5,2,4,7>: Cost 4 vsldoi8 <4,7,5,2>, <4,7,5,2> + 3235497795U, // <5,2,4,u>: Cost 3 vsldoi12 <2,3,4,5>, <2,4,u,5> + 3230041928U, // <5,2,5,0>: Cost 4 vsldoi12 <1,4,2,5>, <2,5,0,1> + 3230041938U, // <5,2,5,1>: Cost 4 vsldoi12 <1,4,2,5>, <2,5,1,2> + 3385050728U, // <5,2,5,2>: Cost 3 vmrglw <4,u,5,5>, <2,2,2,2> + 2311307366U, // <5,2,5,3>: Cost 2 vmrglw <4,u,5,5>, LHS + 3230041968U, // <5,2,5,4>: Cost 4 vsldoi12 <1,4,2,5>, <2,5,4,5> + 3369124916U, // <5,2,5,5>: Cost 4 vmrglw <2,2,5,5>, <1,4,2,5> + 3254814650U, // <5,2,5,6>: Cost 3 vmrghw <5,5,5,5>, <2,6,3,7> + 4189008009U, // <5,2,5,7>: Cost 4 vsldoi8 <4,6,5,2>, <5,7,2,3> + 2311307371U, // <5,2,5,u>: Cost 2 vmrglw <4,u,5,5>, LHS + 4036018278U, // <5,2,6,0>: Cost 4 vsldoi4 <1,5,2,6>, LHS + 4036019334U, // <5,2,6,1>: Cost 4 vsldoi4 <1,5,2,6>, <1,5,2,6> + 3370460776U, // <5,2,6,2>: Cost 3 vmrglw <2,4,5,6>, <2,2,2,2> + 2302689382U, // <5,2,6,3>: Cost 2 vmrglw <3,4,5,6>, LHS + 4036021558U, // <5,2,6,4>: Cost 4 vsldoi4 <1,5,2,6>, RHS + 3230042060U, // <5,2,6,5>: Cost 4 vsldoi12 <1,4,2,5>, <2,6,5,7> + 3255584698U, // <5,2,6,6>: Cost 3 vmrghw <5,6,7,0>, <2,6,3,7> + 3370461105U, // <5,2,6,7>: Cost 4 vmrglw <2,4,5,6>, <2,6,2,7> + 2302689387U, // <5,2,6,u>: Cost 2 vmrglw <3,4,5,6>, LHS + 4189008890U, // <5,2,7,0>: Cost 4 vsldoi8 <4,6,5,2>, <7,0,1,2> + 4185691221U, // <5,2,7,1>: Cost 4 vsldoi8 <4,1,5,2>, <7,1,2,3> + 3365824104U, // <5,2,7,2>: Cost 4 vmrglw <1,6,5,7>, <2,2,2,2> + 3365822566U, // <5,2,7,3>: Cost 3 vmrglw <1,6,5,7>, LHS + 3238152210U, // <5,2,7,4>: Cost 4 vsldoi12 <2,7,4,5>, <2,7,4,5> + 3371795508U, // <5,2,7,5>: Cost 4 vmrglw <2,6,5,7>, <1,4,2,5> + 4189009390U, // <5,2,7,6>: Cost 4 vsldoi8 <4,6,5,2>, <7,6,2,7> + 4189009516U, // <5,2,7,7>: Cost 4 vsldoi8 <4,6,5,2>, <7,7,7,7> + 3365822571U, // <5,2,7,u>: Cost 3 vmrglw <1,6,5,7>, LHS + 3223996475U, // <5,2,u,0>: Cost 3 vsldoi12 <0,4,1,5>, <2,u,0,1> + 4181710638U, // <5,2,u,1>: Cost 3 vsldoi8 <3,4,5,2>, LHS + 3370477160U, // <5,2,u,2>: Cost 3 vmrglw <2,4,5,u>, <2,2,2,2> + 2302705766U, // <5,2,u,3>: Cost 2 vmrglw <3,4,5,u>, LHS + 3238815843U, // <5,2,u,4>: Cost 2 vsldoi12 <2,u,4,5>, <2,u,4,5> + 4181711002U, // <5,2,u,5>: Cost 3 vsldoi8 <3,4,5,2>, RHS + 3238963317U, // <5,2,u,6>: Cost 3 vsldoi12 <2,u,6,5>, <2,u,6,5> + 3370477489U, // <5,2,u,7>: Cost 4 vmrglw <2,4,5,u>, <2,6,2,7> + 3239110791U, // <5,2,u,u>: Cost 2 vsldoi12 <2,u,u,5>, <2,u,u,5> + 3223996555U, // <5,3,0,0>: Cost 4 vsldoi12 <0,4,1,5>, <3,0,0,0> + 3223996566U, // <5,3,0,1>: Cost 3 vsldoi12 <0,4,1,5>, <3,0,1,2> + 4042016610U, // <5,3,0,2>: Cost 4 vsldoi4 <2,5,3,0>, <2,5,3,0> + 4036044950U, // <5,3,0,3>: Cost 4 vsldoi4 <1,5,3,0>, <3,0,1,2> + 3223996592U, // <5,3,0,4>: Cost 3 vsldoi12 <0,4,1,5>, <3,0,4,1> + 3376383766U, // <5,3,0,5>: Cost 4 vmrglw <3,4,5,0>, <2,4,3,5> + 4172423697U, // <5,3,0,6>: Cost 5 vsldoi8 <1,u,5,3>, <0,6,4,7> + 3376383930U, // <5,3,0,7>: Cost 4 vmrglw <3,4,5,0>, <2,6,3,7> + 3223996629U, // <5,3,0,u>: Cost 3 vsldoi12 <0,4,1,5>, <3,0,u,2> + 3385017238U, // <5,3,1,0>: Cost 3 vmrglw <4,u,5,1>, <1,2,3,0> + 3379709795U, // <5,3,1,1>: Cost 3 vmrglw <4,0,5,1>, <2,5,3,1> + 4168442795U, // <5,3,1,2>: Cost 3 vsldoi8 <1,2,5,3>, <1,2,5,3> + 3385017970U, // <5,3,1,3>: Cost 3 vmrglw <4,u,5,1>, <2,2,3,3> + 3385017242U, // <5,3,1,4>: Cost 3 vmrglw <4,u,5,1>, <1,2,3,4> + 4168442991U, // <5,3,1,5>: Cost 4 vsldoi8 <1,2,5,3>, <1,5,0,1> + 4168443123U, // <5,3,1,6>: Cost 4 vsldoi8 <1,2,5,3>, <1,6,5,7> + 3385018298U, // <5,3,1,7>: Cost 3 vmrglw <4,u,5,1>, <2,6,3,7> + 4172424593U, // <5,3,1,u>: Cost 3 vsldoi8 <1,u,5,3>, <1,u,5,3> + 3385030533U, // <5,3,2,0>: Cost 3 vmrglw <4,u,5,2>, + 4168443427U, // <5,3,2,1>: Cost 4 vsldoi8 <1,2,5,3>, <2,1,3,5> + 3223996737U, // <5,3,2,2>: Cost 4 vsldoi12 <0,4,1,5>, <3,2,2,2> + 3235498316U, // <5,3,2,3>: Cost 3 vsldoi12 <2,3,4,5>, <3,2,3,4> + 3252881922U, // <5,3,2,4>: Cost 3 vmrghw <5,2,6,3>, <3,4,5,6> + 4168443747U, // <5,3,2,5>: Cost 4 vsldoi8 <1,2,5,3>, <2,5,3,1> + 3223996774U, // <5,3,2,6>: Cost 4 vsldoi12 <0,4,1,5>, <3,2,6,3> + 3238816111U, // <5,3,2,7>: Cost 4 vsldoi12 <2,u,4,5>, <3,2,7,3> + 3238816121U, // <5,3,2,u>: Cost 3 vsldoi12 <2,u,4,5>, <3,2,u,4> + 3223996799U, // <5,3,3,0>: Cost 4 vsldoi12 <0,4,1,5>, <3,3,0,1> + 4168444147U, // <5,3,3,1>: Cost 4 vsldoi8 <1,2,5,3>, <3,1,2,5> + 3235498386U, // <5,3,3,2>: Cost 4 vsldoi12 <2,3,4,5>, <3,3,2,2> + 3223996828U, // <5,3,3,3>: Cost 3 vsldoi12 <0,4,1,5>, <3,3,3,3> + 3241470375U, // <5,3,3,4>: Cost 3 vsldoi12 <3,3,4,5>, <3,3,4,5> + 3363137059U, // <5,3,3,5>: Cost 4 vmrglw <1,2,5,3>, <2,1,3,5> + 3375081320U, // <5,3,3,6>: Cost 4 vmrglw <3,2,5,3>, <2,5,3,6> + 3363137466U, // <5,3,3,7>: Cost 4 vmrglw <1,2,5,3>, <2,6,3,7> + 3241765323U, // <5,3,3,u>: Cost 3 vsldoi12 <3,3,u,5>, <3,3,u,5> + 3241839060U, // <5,3,4,0>: Cost 3 vsldoi12 <3,4,0,5>, <3,4,0,5> + 4168444898U, // <5,3,4,1>: Cost 4 vsldoi8 <1,2,5,3>, <4,1,5,0> + 4186360886U, // <5,3,4,2>: Cost 3 vsldoi8 <4,2,5,3>, <4,2,5,3> + 3242060271U, // <5,3,4,3>: Cost 3 vsldoi12 <3,4,3,5>, <3,4,3,5> + 3242134008U, // <5,3,4,4>: Cost 3 vsldoi12 <3,4,4,5>, <3,4,4,5> + 3223996930U, // <5,3,4,5>: Cost 3 vsldoi12 <0,4,1,5>, <3,4,5,6> + 3235498506U, // <5,3,4,6>: Cost 4 vsldoi12 <2,3,4,5>, <3,4,6,5> + 3376416698U, // <5,3,4,7>: Cost 4 vmrglw <3,4,5,4>, <2,6,3,7> + 3223996957U, // <5,3,4,u>: Cost 3 vsldoi12 <0,4,1,5>, <3,4,u,6> + 3385050006U, // <5,3,5,0>: Cost 3 vmrglw <4,u,5,5>, <1,2,3,0> + 4168445605U, // <5,3,5,1>: Cost 4 vsldoi8 <1,2,5,3>, <5,1,2,5> + 4192333583U, // <5,3,5,2>: Cost 3 vsldoi8 <5,2,5,3>, <5,2,5,3> + 3385050738U, // <5,3,5,3>: Cost 3 vmrglw <4,u,5,5>, <2,2,3,3> + 3385050010U, // <5,3,5,4>: Cost 3 vmrglw <4,u,5,5>, <1,2,3,4> + 3254815314U, // <5,3,5,5>: Cost 3 vmrghw <5,5,5,5>, <3,5,5,5> + 4168446021U, // <5,3,5,6>: Cost 4 vsldoi8 <1,2,5,3>, <5,6,3,7> + 3385051066U, // <5,3,5,7>: Cost 3 vmrglw <4,u,5,5>, <2,6,3,7> + 3385050014U, // <5,3,5,u>: Cost 3 vmrglw <4,u,5,5>, <1,2,3,u> + 4042063974U, // <5,3,6,0>: Cost 3 vsldoi4 <2,5,3,6>, LHS + 4042064692U, // <5,3,6,1>: Cost 4 vsldoi4 <2,5,3,6>, <1,1,1,1> + 4042065768U, // <5,3,6,2>: Cost 3 vsldoi4 <2,5,3,6>, <2,5,3,6> + 4042066434U, // <5,3,6,3>: Cost 3 vsldoi4 <2,5,3,6>, <3,4,5,6> + 4042067254U, // <5,3,6,4>: Cost 3 vsldoi4 <2,5,3,6>, RHS + 3255585373U, // <5,3,6,5>: Cost 3 vmrghw <5,6,7,0>, <3,5,6,7> + 3376433000U, // <5,3,6,6>: Cost 3 vmrglw <3,4,5,6>, <2,5,3,6> + 3376433082U, // <5,3,6,7>: Cost 3 vmrglw <3,4,5,6>, <2,6,3,7> + 4042069806U, // <5,3,6,u>: Cost 3 vsldoi4 <2,5,3,6>, LHS + 3365823382U, // <5,3,7,0>: Cost 4 vmrglw <1,6,5,7>, <1,2,3,0> + 4042073331U, // <5,3,7,1>: Cost 4 vsldoi4 <2,5,3,7>, <1,6,5,7> + 4042073961U, // <5,3,7,2>: Cost 4 vsldoi4 <2,5,3,7>, <2,5,3,7> + 3365824114U, // <5,3,7,3>: Cost 4 vmrglw <1,6,5,7>, <2,2,3,3> + 3244124907U, // <5,3,7,4>: Cost 3 vsldoi12 <3,7,4,5>, <3,7,4,5> + 3365824035U, // <5,3,7,5>: Cost 4 vmrglw <1,6,5,7>, <2,1,3,5> + 3383740183U, // <5,3,7,6>: Cost 4 vmrglw <4,6,5,7>, <2,4,3,6> + 3363833786U, // <5,3,7,7>: Cost 4 vmrglw <1,3,5,7>, <2,6,3,7> + 3244419855U, // <5,3,7,u>: Cost 3 vsldoi12 <3,7,u,5>, <3,7,u,5> + 4042080358U, // <5,3,u,0>: Cost 3 vsldoi4 <2,5,3,u>, LHS + 3223997214U, // <5,3,u,1>: Cost 3 vsldoi12 <0,4,1,5>, <3,u,1,2> + 4042082154U, // <5,3,u,2>: Cost 3 vsldoi4 <2,5,3,u>, <2,5,3,u> + 4042082820U, // <5,3,u,3>: Cost 3 vsldoi4 <2,5,3,u>, <3,4,5,u> + 4042083638U, // <5,3,u,4>: Cost 3 vsldoi4 <2,5,3,u>, RHS + 3223997254U, // <5,3,u,5>: Cost 3 vsldoi12 <0,4,1,5>, <3,u,5,6> + 3376433000U, // <5,3,u,6>: Cost 3 vmrglw <3,4,5,6>, <2,5,3,6> + 3376449466U, // <5,3,u,7>: Cost 3 vmrglw <3,4,5,u>, <2,6,3,7> + 3223997277U, // <5,3,u,u>: Cost 3 vsldoi12 <0,4,1,5>, <3,u,u,2> + 4167786509U, // <5,4,0,0>: Cost 4 vsldoi8 <1,1,5,4>, <0,0,1,4> + 4181721190U, // <5,4,0,1>: Cost 3 vsldoi8 <3,4,5,4>, LHS + 4054034126U, // <5,4,0,2>: Cost 4 vsldoi4 <4,5,4,0>, <2,3,4,5> + 4054034944U, // <5,4,0,3>: Cost 4 vsldoi4 <4,5,4,0>, <3,4,5,4> + 4185702738U, // <5,4,0,4>: Cost 3 vsldoi8 <4,1,5,4>, <0,4,1,5> + 3376383694U, // <5,4,0,5>: Cost 3 vmrglw <3,4,5,0>, <2,3,4,5> + 3376383695U, // <5,4,0,6>: Cost 5 vmrglw <3,4,5,0>, <2,3,4,6> + 3384351018U, // <5,4,0,7>: Cost 4 vmrglw <4,7,5,0>, + 4181721757U, // <5,4,0,u>: Cost 3 vsldoi8 <3,4,5,4>, LHS + 3379712881U, // <5,4,1,0>: Cost 3 vmrglw <4,0,5,1>, <6,7,4,0> + 4167787355U, // <5,4,1,1>: Cost 4 vsldoi8 <1,1,5,4>, <1,1,5,4> + 4169114522U, // <5,4,1,2>: Cost 4 vsldoi8 <1,3,5,4>, <1,2,3,4> + 4169114621U, // <5,4,1,3>: Cost 4 vsldoi8 <1,3,5,4>, <1,3,5,4> + 3385019600U, // <5,4,1,4>: Cost 3 vmrglw <4,u,5,1>, <4,4,4,4> + 3223997410U, // <5,4,1,5>: Cost 3 vsldoi12 <0,4,1,5>, <4,1,5,0> + 4185703667U, // <5,4,1,6>: Cost 4 vsldoi8 <4,1,5,4>, <1,6,5,7> + 3385019036U, // <5,4,1,7>: Cost 4 vmrglw <4,u,5,1>, <3,6,4,7> + 3385018065U, // <5,4,1,u>: Cost 3 vmrglw <4,u,5,1>, <2,3,4,u> + 4054048870U, // <5,4,2,0>: Cost 4 vsldoi4 <4,5,4,2>, LHS + 4185703971U, // <5,4,2,1>: Cost 4 vsldoi8 <4,1,5,4>, <2,1,3,5> + 4175750760U, // <5,4,2,2>: Cost 4 vsldoi8 <2,4,5,4>, <2,2,2,2> + 4181722830U, // <5,4,2,3>: Cost 3 vsldoi8 <3,4,5,4>, <2,3,4,5> + 4175750951U, // <5,4,2,4>: Cost 4 vsldoi8 <2,4,5,4>, <2,4,5,4> + 3235499062U, // <5,4,2,5>: Cost 3 vsldoi12 <2,3,4,5>, <4,2,5,3> + 4181723066U, // <5,4,2,6>: Cost 4 vsldoi8 <3,4,5,4>, <2,6,3,7> + 3376401052U, // <5,4,2,7>: Cost 5 vmrglw <3,4,5,2>, <3,6,4,7> + 3252514330U, // <5,4,2,u>: Cost 3 vmrghw <5,2,1,3>, <4,u,5,1> + 4181723286U, // <5,4,3,0>: Cost 4 vsldoi8 <3,4,5,4>, <3,0,1,2> + 3363135525U, // <5,4,3,1>: Cost 4 vmrglw <1,2,5,3>, <0,0,4,1> + 4181723468U, // <5,4,3,2>: Cost 4 vsldoi8 <3,4,5,4>, <3,2,3,4> + 4181723548U, // <5,4,3,3>: Cost 4 vsldoi8 <3,4,5,4>, <3,3,3,3> + 4181723648U, // <5,4,3,4>: Cost 3 vsldoi8 <3,4,5,4>, <3,4,5,4> + 3381053134U, // <5,4,3,5>: Cost 3 vmrglw <4,2,5,3>, <2,3,4,5> + 3262041236U, // <5,4,3,6>: Cost 4 vsldoi12 <6,7,4,5>, <4,3,6,7> + 3363138204U, // <5,4,3,7>: Cost 5 vmrglw <1,2,5,3>, <3,6,4,7> + 4184378180U, // <5,4,3,u>: Cost 3 vsldoi8 <3,u,5,4>, <3,u,5,4> + 4185041813U, // <5,4,4,0>: Cost 3 vsldoi8 <4,0,5,4>, <4,0,5,4> + 4185705446U, // <5,4,4,1>: Cost 3 vsldoi8 <4,1,5,4>, <4,1,5,4> + 4181724214U, // <5,4,4,2>: Cost 4 vsldoi8 <3,4,5,4>, <4,2,5,3> + 4187032712U, // <5,4,4,3>: Cost 3 vsldoi8 <4,3,5,4>, <4,3,5,4> + 3223997648U, // <5,4,4,4>: Cost 3 vsldoi12 <0,4,1,5>, <4,4,4,4> + 3248180442U, // <5,4,4,5>: Cost 2 vsldoi12 <4,4,5,5>, <4,4,5,5> + 4181724542U, // <5,4,4,6>: Cost 4 vsldoi8 <3,4,5,4>, <4,6,5,7> + 4189687244U, // <5,4,4,7>: Cost 3 vsldoi8 <4,7,5,4>, <4,7,5,4> + 3248401653U, // <5,4,4,u>: Cost 2 vsldoi12 <4,4,u,5>, <4,4,u,5> + 4036157542U, // <5,4,5,0>: Cost 3 vsldoi4 <1,5,4,5>, LHS + 4036158615U, // <5,4,5,1>: Cost 3 vsldoi4 <1,5,4,5>, <1,5,4,5> + 3235499278U, // <5,4,5,2>: Cost 3 vsldoi12 <2,3,4,5>, <4,5,2,3> + 4036159638U, // <5,4,5,3>: Cost 4 vsldoi4 <1,5,4,5>, <3,0,1,2> + 4036160822U, // <5,4,5,4>: Cost 3 vsldoi4 <1,5,4,5>, RHS + 2181074230U, // <5,4,5,5>: Cost 2 vmrghw <5,5,5,5>, RHS + 3223997750U, // <5,4,5,6>: Cost 2 vsldoi12 <0,4,1,5>, RHS + 3385051804U, // <5,4,5,7>: Cost 4 vmrglw <4,u,5,5>, <3,6,4,7> + 3223997768U, // <5,4,5,u>: Cost 2 vsldoi12 <0,4,1,5>, RHS + 3255585682U, // <5,4,6,0>: Cost 3 vmrghw <5,6,7,0>, <4,0,5,1> + 3376433976U, // <5,4,6,1>: Cost 3 vmrglw <3,4,5,6>, <3,u,4,1> + 3382406107U, // <5,4,6,2>: Cost 4 vmrglw <4,4,5,6>, <4,1,4,2> + 4036168194U, // <5,4,6,3>: Cost 4 vsldoi4 <1,5,4,6>, <3,4,5,6> + 3255586000U, // <5,4,6,4>: Cost 3 vmrghw <5,6,7,0>, <4,4,4,4> + 2181844278U, // <5,4,6,5>: Cost 2 vmrghw <5,6,7,0>, RHS + 3376432280U, // <5,4,6,6>: Cost 4 vmrglw <3,4,5,6>, <1,5,4,6> + 4205613942U, // <5,4,6,7>: Cost 3 vsldoi8 <7,4,5,4>, <6,7,4,5> + 2181844521U, // <5,4,6,u>: Cost 2 vmrghw <5,6,7,0>, RHS + 4189688826U, // <5,4,7,0>: Cost 4 vsldoi8 <4,7,5,4>, <7,0,1,2> + 3365822501U, // <5,4,7,1>: Cost 4 vmrglw <1,6,5,7>, <0,0,4,1> + 4211586269U, // <5,4,7,2>: Cost 4 vsldoi8 , <7,2,u,4> + 4187034891U, // <5,4,7,3>: Cost 4 vsldoi8 <4,3,5,4>, <7,3,4,5> + 4189689190U, // <5,4,7,4>: Cost 3 vsldoi8 <4,7,5,4>, <7,4,5,6> + 3383740110U, // <5,4,7,5>: Cost 3 vmrglw <4,6,5,7>, <2,3,4,5> + 3383740111U, // <5,4,7,6>: Cost 4 vmrglw <4,6,5,7>, <2,3,4,6> + 4189689423U, // <5,4,7,7>: Cost 4 vsldoi8 <4,7,5,4>, <7,7,4,5> + 4208268968U, // <5,4,7,u>: Cost 3 vsldoi8 <7,u,5,4>, <7,u,5,4> + 4036182118U, // <5,4,u,0>: Cost 3 vsldoi4 <1,5,4,u>, LHS + 4036183194U, // <5,4,u,1>: Cost 3 vsldoi4 <1,5,4,u>, <1,5,4,u> + 4054099662U, // <5,4,u,2>: Cost 3 vsldoi4 <4,5,4,u>, <2,3,4,5> + 4181722830U, // <5,4,u,3>: Cost 3 vsldoi8 <3,4,5,4>, <2,3,4,5> + 4036185398U, // <5,4,u,4>: Cost 3 vsldoi4 <1,5,4,u>, RHS + 3250834974U, // <5,4,u,5>: Cost 2 vsldoi12 <4,u,5,5>, <4,u,5,5> + 3223997993U, // <5,4,u,6>: Cost 2 vsldoi12 <0,4,1,5>, RHS + 4213578032U, // <5,4,u,7>: Cost 3 vsldoi8 , + 3223998011U, // <5,4,u,u>: Cost 2 vsldoi12 <0,4,1,5>, RHS + 3376384508U, // <5,5,0,0>: Cost 3 vmrglw <3,4,5,0>, <3,4,5,0> + 3116613734U, // <5,5,0,1>: Cost 2 vsldoi8 <4,u,5,5>, LHS + 3376384510U, // <5,5,0,2>: Cost 4 vmrglw <3,4,5,0>, <3,4,5,2> + 3376385078U, // <5,5,0,3>: Cost 4 vmrglw <3,4,5,0>, <4,2,5,3> + 3223998050U, // <5,5,0,4>: Cost 3 vsldoi12 <0,4,1,5>, <5,0,4,1> + 4194337250U, // <5,5,0,5>: Cost 3 vsldoi8 <5,5,5,5>, <0,5,u,5> + 3251540066U, // <5,5,0,6>: Cost 3 vmrghw <5,0,6,1>, <5,6,7,0> + 3376385406U, // <5,5,0,7>: Cost 4 vmrglw <3,4,5,0>, <4,6,5,7> + 3116614301U, // <5,5,0,u>: Cost 2 vsldoi8 <4,u,5,5>, LHS + 3379711189U, // <5,5,1,0>: Cost 3 vmrglw <4,0,5,1>, <4,4,5,0> + 2311278106U, // <5,5,1,1>: Cost 2 vmrglw <4,u,5,1>, <4,u,5,1> + 4190356374U, // <5,5,1,2>: Cost 3 vsldoi8 <4,u,5,5>, <1,2,3,0> + 4169122814U, // <5,5,1,3>: Cost 4 vsldoi8 <1,3,5,5>, <1,3,5,5> + 3252088503U, // <5,5,1,4>: Cost 3 vsldoi12 <5,1,4,5>, <5,1,4,5> + 3385019610U, // <5,5,1,5>: Cost 3 vmrglw <4,u,5,1>, <4,4,5,5> + 3385018882U, // <5,5,1,6>: Cost 3 vmrglw <4,u,5,1>, <3,4,5,6> + 3385017587U, // <5,5,1,7>: Cost 4 vmrglw <4,u,5,1>, <1,6,5,7> + 2311278106U, // <5,5,1,u>: Cost 2 vmrglw <4,u,5,1>, <4,u,5,1> + 3376400892U, // <5,5,2,0>: Cost 4 vmrglw <3,4,5,2>, <3,4,5,0> + 3223998187U, // <5,5,2,1>: Cost 4 vsldoi12 <0,4,1,5>, <5,2,1,3> + 3376400894U, // <5,5,2,2>: Cost 3 vmrglw <3,4,5,2>, <3,4,5,2> + 3235499774U, // <5,5,2,3>: Cost 3 vsldoi12 <2,3,4,5>, <5,2,3,4> + 3235499782U, // <5,5,2,4>: Cost 4 vsldoi12 <2,3,4,5>, <5,2,4,3> + 3250835215U, // <5,5,2,5>: Cost 3 vsldoi12 <4,u,5,5>, <5,2,5,3> + 4190357434U, // <5,5,2,6>: Cost 3 vsldoi8 <4,u,5,5>, <2,6,3,7> + 3376401790U, // <5,5,2,7>: Cost 4 vmrglw <3,4,5,2>, <4,6,5,7> + 3238817579U, // <5,5,2,u>: Cost 3 vsldoi12 <2,u,4,5>, <5,2,u,4> + 4190357654U, // <5,5,3,0>: Cost 3 vsldoi8 <4,u,5,5>, <3,0,1,2> + 4167796970U, // <5,5,3,1>: Cost 4 vsldoi8 <1,1,5,5>, <3,1,1,5> + 3235499845U, // <5,5,3,2>: Cost 4 vsldoi12 <2,3,4,5>, <5,3,2,3> + 3363136427U, // <5,5,3,3>: Cost 3 vmrglw <1,2,5,3>, <1,2,5,3> + 4190358018U, // <5,5,3,4>: Cost 3 vsldoi8 <4,u,5,5>, <3,4,5,6> + 3387026974U, // <5,5,3,5>: Cost 3 vmrglw <5,2,5,3>, <4,u,5,5> + 3363138050U, // <5,5,3,6>: Cost 4 vmrglw <1,2,5,3>, <3,4,5,6> + 3363136755U, // <5,5,3,7>: Cost 4 vmrglw <1,2,5,3>, <1,6,5,7> + 4190358302U, // <5,5,3,u>: Cost 3 vsldoi8 <4,u,5,5>, <3,u,1,2> + 4190358418U, // <5,5,4,0>: Cost 3 vsldoi8 <4,u,5,5>, <4,0,5,1> + 3223998351U, // <5,5,4,1>: Cost 4 vsldoi12 <0,4,1,5>, <5,4,1,5> + 3235499928U, // <5,5,4,2>: Cost 4 vsldoi12 <2,3,4,5>, <5,4,2,5> + 3376417846U, // <5,5,4,3>: Cost 4 vmrglw <3,4,5,4>, <4,2,5,3> + 3113962714U, // <5,5,4,4>: Cost 2 vsldoi8 <4,4,5,5>, <4,4,5,5> + 3116617014U, // <5,5,4,5>: Cost 2 vsldoi8 <4,u,5,5>, RHS + 3384382822U, // <5,5,4,6>: Cost 3 vmrglw <4,7,5,4>, <7,4,5,6> + 3376418174U, // <5,5,4,7>: Cost 4 vmrglw <3,4,5,4>, <4,6,5,7> + 3116617246U, // <5,5,4,u>: Cost 2 vsldoi8 <4,u,5,5>, <4,u,5,5> + 2986377318U, // <5,5,5,0>: Cost 2 vsldoi4 <5,5,5,5>, LHS + 3385052050U, // <5,5,5,1>: Cost 3 vmrglw <4,u,5,5>, <4,0,5,1> + 4190359311U, // <5,5,5,2>: Cost 3 vsldoi8 <4,u,5,5>, <5,2,5,3> + 3385052943U, // <5,5,5,3>: Cost 3 vmrglw <4,u,5,5>, <5,2,5,3> + 2986380598U, // <5,5,5,4>: Cost 2 vsldoi4 <5,5,5,5>, RHS + 1504103734U, // <5,5,5,5>: Cost 1 vspltisw1 RHS + 3385051650U, // <5,5,5,6>: Cost 3 vmrglw <4,u,5,5>, <3,4,5,6> + 3385053271U, // <5,5,5,7>: Cost 3 vmrglw <4,u,5,5>, <5,6,5,7> + 1504103734U, // <5,5,5,u>: Cost 1 vspltisw1 RHS + 3255586420U, // <5,5,6,0>: Cost 3 vmrghw <5,6,7,0>, <5,0,6,1> + 3400321938U, // <5,5,6,1>: Cost 3 vmrglw <7,4,5,6>, <4,0,5,1> + 4190360058U, // <5,5,6,2>: Cost 3 vsldoi8 <4,u,5,5>, <6,2,7,3> + 4036241922U, // <5,5,6,3>: Cost 4 vsldoi4 <1,5,5,6>, <3,4,5,6> + 3255406668U, // <5,5,6,4>: Cost 3 vsldoi12 <5,6,4,5>, <5,6,4,5> + 3250835543U, // <5,5,6,5>: Cost 3 vsldoi12 <4,u,5,5>, <5,6,5,7> + 2302691842U, // <5,5,6,6>: Cost 2 vmrglw <3,4,5,6>, <3,4,5,6> + 4190360398U, // <5,5,6,7>: Cost 3 vsldoi8 <4,u,5,5>, <6,7,0,1> + 2302691842U, // <5,5,6,u>: Cost 2 vmrglw <3,4,5,6>, <3,4,5,6> + 4190360570U, // <5,5,7,0>: Cost 3 vsldoi8 <4,u,5,5>, <7,0,1,2> + 3383741330U, // <5,5,7,1>: Cost 4 vmrglw <4,6,5,7>, <4,0,5,1> + 4054165198U, // <5,5,7,2>: Cost 4 vsldoi4 <4,5,5,7>, <2,3,4,5> + 3365823403U, // <5,5,7,3>: Cost 4 vmrglw <1,6,5,7>, <1,2,5,3> + 4190360934U, // <5,5,7,4>: Cost 3 vsldoi8 <4,u,5,5>, <7,4,5,6> + 4194342326U, // <5,5,7,5>: Cost 3 vsldoi8 <5,5,5,5>, <7,5,5,5> + 3365825026U, // <5,5,7,6>: Cost 4 vmrglw <1,6,5,7>, <3,4,5,6> + 3365823731U, // <5,5,7,7>: Cost 3 vmrglw <1,6,5,7>, <1,6,5,7> + 4190361218U, // <5,5,7,u>: Cost 3 vsldoi8 <4,u,5,5>, <7,u,1,2> + 2986377318U, // <5,5,u,0>: Cost 2 vsldoi4 <5,5,5,5>, LHS + 3116619566U, // <5,5,u,1>: Cost 2 vsldoi8 <4,u,5,5>, LHS + 4190361477U, // <5,5,u,2>: Cost 3 vsldoi8 <4,u,5,5>, + 4190361532U, // <5,5,u,3>: Cost 3 vsldoi8 <4,u,5,5>, + 2986380598U, // <5,5,u,4>: Cost 2 vsldoi4 <5,5,5,5>, RHS + 1504103734U, // <5,5,u,5>: Cost 1 vspltisw1 RHS + 2302691842U, // <5,5,u,6>: Cost 2 vmrglw <3,4,5,6>, <3,4,5,6> + 4190361856U, // <5,5,u,7>: Cost 3 vsldoi8 <4,u,5,5>, + 1504103734U, // <5,5,u,u>: Cost 1 vspltisw1 RHS + 4181737472U, // <5,6,0,0>: Cost 3 vsldoi8 <3,4,5,6>, <0,0,0,0> + 3107995750U, // <5,6,0,1>: Cost 2 vsldoi8 <3,4,5,6>, LHS + 4175765677U, // <5,6,0,2>: Cost 4 vsldoi8 <2,4,5,6>, <0,2,1,2> + 4181737728U, // <5,6,0,3>: Cost 3 vsldoi8 <3,4,5,6>, <0,3,1,4> + 4181737810U, // <5,6,0,4>: Cost 3 vsldoi8 <3,4,5,6>, <0,4,1,5> + 4181737892U, // <5,6,0,5>: Cost 4 vsldoi8 <3,4,5,6>, <0,5,1,6> + 4181737974U, // <5,6,0,6>: Cost 4 vsldoi8 <3,4,5,6>, <0,6,1,7> + 3376385334U, // <5,6,0,7>: Cost 3 vmrglw <3,4,5,0>, RHS + 3107996317U, // <5,6,0,u>: Cost 2 vsldoi8 <3,4,5,6>, LHS + 4169794276U, // <5,6,1,0>: Cost 4 vsldoi8 <1,4,5,6>, <1,0,1,2> + 4181738292U, // <5,6,1,1>: Cost 3 vsldoi8 <3,4,5,6>, <1,1,1,1> + 4181738390U, // <5,6,1,2>: Cost 3 vsldoi8 <3,4,5,6>, <1,2,3,0> + 4181738466U, // <5,6,1,3>: Cost 4 vsldoi8 <3,4,5,6>, <1,3,2,4> + 4169794640U, // <5,6,1,4>: Cost 3 vsldoi8 <1,4,5,6>, <1,4,5,6> + 4170458273U, // <5,6,1,5>: Cost 4 vsldoi8 <1,5,5,6>, <1,5,5,6> + 3385021240U, // <5,6,1,6>: Cost 3 vmrglw <4,u,5,1>, <6,6,6,6> + 2311277878U, // <5,6,1,7>: Cost 2 vmrglw <4,u,5,1>, RHS + 2311277879U, // <5,6,1,u>: Cost 2 vmrglw <4,u,5,1>, RHS + 4175766973U, // <5,6,2,0>: Cost 4 vsldoi8 <2,4,5,6>, <2,0,1,2> + 4181739039U, // <5,6,2,1>: Cost 4 vsldoi8 <3,4,5,6>, <2,1,3,1> + 4175767144U, // <5,6,2,2>: Cost 3 vsldoi8 <2,4,5,6>, <2,2,2,2> + 4181739174U, // <5,6,2,3>: Cost 3 vsldoi8 <3,4,5,6>, <2,3,0,1> + 4175767337U, // <5,6,2,4>: Cost 3 vsldoi8 <2,4,5,6>, <2,4,5,6> + 4181739368U, // <5,6,2,5>: Cost 3 vsldoi8 <3,4,5,6>, <2,5,3,6> + 4181739450U, // <5,6,2,6>: Cost 3 vsldoi8 <3,4,5,6>, <2,6,3,7> + 3376401718U, // <5,6,2,7>: Cost 3 vmrglw <3,4,5,2>, RHS + 4178421869U, // <5,6,2,u>: Cost 3 vsldoi8 <2,u,5,6>, <2,u,5,6> + 4181739670U, // <5,6,3,0>: Cost 3 vsldoi8 <3,4,5,6>, <3,0,1,2> + 4169795845U, // <5,6,3,1>: Cost 4 vsldoi8 <1,4,5,6>, <3,1,4,5> + 4175767873U, // <5,6,3,2>: Cost 4 vsldoi8 <2,4,5,6>, <3,2,2,2> + 4181739932U, // <5,6,3,3>: Cost 3 vsldoi8 <3,4,5,6>, <3,3,3,3> + 3107998210U, // <5,6,3,4>: Cost 2 vsldoi8 <3,4,5,6>, <3,4,5,6> + 3238965821U, // <5,6,3,5>: Cost 4 vsldoi12 <2,u,6,5>, <6,3,5,7> + 4181740146U, // <5,6,3,6>: Cost 4 vsldoi8 <3,4,5,6>, <3,6,0,1> + 3363138870U, // <5,6,3,7>: Cost 3 vmrglw <1,2,5,3>, RHS + 3110652742U, // <5,6,3,u>: Cost 2 vsldoi8 <3,u,5,6>, <3,u,5,6> + 4054212710U, // <5,6,4,0>: Cost 3 vsldoi4 <4,5,6,4>, LHS + 4181740490U, // <5,6,4,1>: Cost 4 vsldoi8 <3,4,5,6>, <4,1,2,3> + 3259904625U, // <5,6,4,2>: Cost 3 vsldoi12 <6,4,2,5>, <6,4,2,5> + 4054215170U, // <5,6,4,3>: Cost 3 vsldoi4 <4,5,6,4>, <3,4,5,6> + 4187712731U, // <5,6,4,4>: Cost 3 vsldoi8 <4,4,5,6>, <4,4,5,6> + 3107999030U, // <5,6,4,5>: Cost 2 vsldoi8 <3,4,5,6>, RHS + 4189039997U, // <5,6,4,6>: Cost 3 vsldoi8 <4,6,5,6>, <4,6,5,6> + 3376418102U, // <5,6,4,7>: Cost 3 vmrglw <3,4,5,4>, RHS + 3107999273U, // <5,6,4,u>: Cost 2 vsldoi8 <3,4,5,6>, RHS + 3238965932U, // <5,6,5,0>: Cost 4 vsldoi12 <2,u,6,5>, <6,5,0,1> + 4169797317U, // <5,6,5,1>: Cost 4 vsldoi8 <1,4,5,6>, <5,1,6,1> + 4181741336U, // <5,6,5,2>: Cost 3 vsldoi8 <3,4,5,6>, <5,2,6,3> + 4181741391U, // <5,6,5,3>: Cost 4 vsldoi8 <3,4,5,6>, <5,3,3,4> + 4193685428U, // <5,6,5,4>: Cost 3 vsldoi8 <5,4,5,6>, <5,4,5,6> + 4181741582U, // <5,6,5,5>: Cost 3 vsldoi8 <3,4,5,6>, <5,5,6,6> + 4181741604U, // <5,6,5,6>: Cost 3 vsldoi8 <3,4,5,6>, <5,6,0,1> + 2311310646U, // <5,6,5,7>: Cost 2 vmrglw <4,u,5,5>, RHS + 2311310647U, // <5,6,5,u>: Cost 2 vmrglw <4,u,5,5>, RHS + 4060201062U, // <5,6,6,0>: Cost 3 vsldoi4 <5,5,6,6>, LHS + 3364490949U, // <5,6,6,1>: Cost 4 vmrglw <1,4,5,6>, <5,1,6,1> + 3255587322U, // <5,6,6,2>: Cost 3 vmrghw <5,6,7,0>, <6,2,7,3> + 3376434968U, // <5,6,6,3>: Cost 3 vmrglw <3,4,5,6>, <5,2,6,3> + 4060204342U, // <5,6,6,4>: Cost 3 vsldoi4 <5,5,6,6>, RHS + 4060205070U, // <5,6,6,5>: Cost 3 vsldoi4 <5,5,6,6>, <5,5,6,6> + 3376435214U, // <5,6,6,6>: Cost 3 vmrglw <3,4,5,6>, <5,5,6,6> + 2302692662U, // <5,6,6,7>: Cost 2 vmrglw <3,4,5,6>, RHS + 2302692663U, // <5,6,6,u>: Cost 2 vmrglw <3,4,5,6>, RHS + 1906753638U, // <5,6,7,0>: Cost 1 vsldoi4 RHS, LHS + 2980496180U, // <5,6,7,1>: Cost 2 vsldoi4 RHS, <1,1,1,1> + 2980497000U, // <5,6,7,2>: Cost 2 vsldoi4 RHS, <2,2,2,2> + 2980497558U, // <5,6,7,3>: Cost 2 vsldoi4 RHS, <3,0,1,2> + 1906756918U, // <5,6,7,4>: Cost 1 vsldoi4 RHS, RHS + 2980499460U, // <5,6,7,5>: Cost 2 vsldoi4 RHS, <5,5,5,5> + 2980499962U, // <5,6,7,6>: Cost 2 vsldoi4 RHS, <6,2,7,3> + 2980501100U, // <5,6,7,7>: Cost 2 vsldoi4 RHS, <7,7,7,7> + 1906759470U, // <5,6,7,u>: Cost 1 vsldoi4 RHS, LHS + 1906761830U, // <5,6,u,0>: Cost 1 vsldoi4 RHS, LHS + 3108001582U, // <5,6,u,1>: Cost 2 vsldoi8 <3,4,5,6>, LHS + 2980505192U, // <5,6,u,2>: Cost 2 vsldoi4 RHS, <2,2,2,2> + 2980505750U, // <5,6,u,3>: Cost 2 vsldoi4 RHS, <3,0,1,2> + 1906765111U, // <5,6,u,4>: Cost 1 vsldoi4 RHS, RHS + 3108001946U, // <5,6,u,5>: Cost 2 vsldoi8 <3,4,5,6>, RHS + 2980508154U, // <5,6,u,6>: Cost 2 vsldoi4 RHS, <6,2,7,3> + 2302709046U, // <5,6,u,7>: Cost 2 vmrglw <3,4,5,u>, RHS + 1906767662U, // <5,6,u,u>: Cost 1 vsldoi4 RHS, LHS + 4171128832U, // <5,7,0,0>: Cost 4 vsldoi8 <1,6,5,7>, <0,0,0,0> + 4171128934U, // <5,7,0,1>: Cost 3 vsldoi8 <1,6,5,7>, LHS + 4054255715U, // <5,7,0,2>: Cost 4 vsldoi4 <4,5,7,0>, <2,u,4,5> + 3384349178U, // <5,7,0,3>: Cost 4 vmrglw <4,7,5,0>, <6,2,7,3> + 4171129170U, // <5,7,0,4>: Cost 3 vsldoi8 <1,6,5,7>, <0,4,1,5> + 3384347884U, // <5,7,0,5>: Cost 4 vmrglw <4,7,5,0>, <4,4,7,5> + 4066202346U, // <5,7,0,6>: Cost 4 vsldoi4 <6,5,7,0>, <6,5,7,0> + 4054258682U, // <5,7,0,7>: Cost 4 vsldoi4 <4,5,7,0>, <7,0,1,2> + 4171129501U, // <5,7,0,u>: Cost 3 vsldoi8 <1,6,5,7>, LHS + 3385020514U, // <5,7,1,0>: Cost 3 vmrglw <4,u,5,1>, <5,6,7,0> + 3379712747U, // <5,7,1,1>: Cost 3 vmrglw <4,0,5,1>, <6,5,7,1> + 4171129750U, // <5,7,1,2>: Cost 4 vsldoi8 <1,6,5,7>, <1,2,3,0> + 3385020922U, // <5,7,1,3>: Cost 3 vmrglw <4,u,5,1>, <6,2,7,3> + 3385020518U, // <5,7,1,4>: Cost 3 vmrglw <4,u,5,1>, <5,6,7,4> + 4171129967U, // <5,7,1,5>: Cost 4 vsldoi8 <1,6,5,7>, <1,5,0,1> + 4171130099U, // <5,7,1,6>: Cost 3 vsldoi8 <1,6,5,7>, <1,6,5,7> + 3385021250U, // <5,7,1,7>: Cost 3 vmrglw <4,u,5,1>, <6,6,7,7> + 4172457365U, // <5,7,1,u>: Cost 3 vsldoi8 <1,u,5,7>, <1,u,5,7> + 3383701602U, // <5,7,2,0>: Cost 4 vmrglw <4,6,5,2>, <5,6,7,0> + 4171130403U, // <5,7,2,1>: Cost 4 vsldoi8 <1,6,5,7>, <2,1,3,5> + 4171130472U, // <5,7,2,2>: Cost 4 vsldoi8 <1,6,5,7>, <2,2,2,2> + 3383702010U, // <5,7,2,3>: Cost 3 vmrglw <4,6,5,2>, <6,2,7,3> + 3383701606U, // <5,7,2,4>: Cost 4 vmrglw <4,6,5,2>, <5,6,7,4> + 4171130729U, // <5,7,2,5>: Cost 4 vsldoi8 <1,6,5,7>, <2,5,3,7> + 4169140154U, // <5,7,2,6>: Cost 4 vsldoi8 <1,3,5,7>, <2,6,3,7> + 3383702338U, // <5,7,2,7>: Cost 4 vmrglw <4,6,5,2>, <6,6,7,7> + 3383702010U, // <5,7,2,u>: Cost 3 vmrglw <4,6,5,2>, <6,2,7,3> + 4171131030U, // <5,7,3,0>: Cost 4 vsldoi8 <1,6,5,7>, <3,0,1,2> + 4171131159U, // <5,7,3,1>: Cost 4 vsldoi8 <1,6,5,7>, <3,1,6,5> + 4189047116U, // <5,7,3,2>: Cost 4 vsldoi8 <4,6,5,7>, <3,2,3,4> + 4171131292U, // <5,7,3,3>: Cost 4 vsldoi8 <1,6,5,7>, <3,3,3,3> + 3265361163U, // <5,7,3,4>: Cost 3 vsldoi12 <7,3,4,5>, <7,3,4,5> + 3385037470U, // <5,7,3,5>: Cost 4 vmrglw <4,u,5,3>, <6,4,7,5> + 4183075493U, // <5,7,3,6>: Cost 4 vsldoi8 <3,6,5,7>, <3,6,5,7> + 3244127525U, // <5,7,3,7>: Cost 4 vsldoi12 <3,7,4,5>, <7,3,7,4> + 3265656111U, // <5,7,3,u>: Cost 3 vsldoi12 <7,3,u,5>, <7,3,u,5> + 3265729848U, // <5,7,4,0>: Cost 3 vsldoi12 <7,4,0,5>, <7,4,0,5> + 4171131874U, // <5,7,4,1>: Cost 4 vsldoi8 <1,6,5,7>, <4,1,5,0> + 4054288483U, // <5,7,4,2>: Cost 4 vsldoi4 <4,5,7,4>, <2,u,4,5> + 4187057291U, // <5,7,4,3>: Cost 4 vsldoi8 <4,3,5,7>, <4,3,5,7> + 3266024796U, // <5,7,4,4>: Cost 3 vsldoi12 <7,4,4,5>, <7,4,4,5> + 4171132214U, // <5,7,4,5>: Cost 3 vsldoi8 <1,6,5,7>, RHS + 4189048190U, // <5,7,4,6>: Cost 3 vsldoi8 <4,6,5,7>, <4,6,5,7> + 4189711823U, // <5,7,4,7>: Cost 3 vsldoi8 <4,7,5,7>, <4,7,5,7> + 4171132457U, // <5,7,4,u>: Cost 3 vsldoi8 <1,6,5,7>, RHS + 3385053282U, // <5,7,5,0>: Cost 3 vmrglw <4,u,5,5>, <5,6,7,0> + 4171132617U, // <5,7,5,1>: Cost 4 vsldoi8 <1,6,5,7>, <5,1,6,5> + 4171132705U, // <5,7,5,2>: Cost 4 vsldoi8 <1,6,5,7>, <5,2,7,3> + 3385053690U, // <5,7,5,3>: Cost 3 vmrglw <4,u,5,5>, <6,2,7,3> + 3385053286U, // <5,7,5,4>: Cost 3 vmrglw <4,u,5,5>, <5,6,7,4> + 3254818230U, // <5,7,5,5>: Cost 3 vmrghw <5,5,5,5>, <7,5,5,5> + 4195020887U, // <5,7,5,6>: Cost 3 vsldoi8 <5,6,5,7>, <5,6,5,7> + 3385054018U, // <5,7,5,7>: Cost 3 vmrglw <4,u,5,5>, <6,6,7,7> + 3385053290U, // <5,7,5,u>: Cost 3 vmrglw <4,u,5,5>, <5,6,7,u> + 3255587834U, // <5,7,6,0>: Cost 3 vmrghw <5,6,7,0>, <7,0,1,2> + 3255587914U, // <5,7,6,1>: Cost 4 vmrghw <5,6,7,0>, <7,1,1,1> + 3255587988U, // <5,7,6,2>: Cost 3 vmrghw <5,6,7,0>, <7,2,0,3> + 4066249218U, // <5,7,6,3>: Cost 3 vsldoi4 <6,5,7,6>, <3,4,5,6> + 3255588198U, // <5,7,6,4>: Cost 3 vmrghw <5,6,7,0>, <7,4,5,6> + 3255588289U, // <5,7,6,5>: Cost 3 vmrghw <5,6,7,0>, <7,5,6,7> + 4066251504U, // <5,7,6,6>: Cost 3 vsldoi4 <6,5,7,6>, <6,5,7,6> + 3255588460U, // <5,7,6,7>: Cost 3 vmrghw <5,6,7,0>, <7,7,7,7> + 3255588482U, // <5,7,6,u>: Cost 3 vmrghw <5,6,7,0>, <7,u,1,2> + 4054311014U, // <5,7,7,0>: Cost 4 vsldoi4 <4,5,7,7>, LHS + 4060284147U, // <5,7,7,1>: Cost 4 vsldoi4 <5,5,7,7>, <1,6,5,7> + 4054313059U, // <5,7,7,2>: Cost 4 vsldoi4 <4,5,7,7>, <2,u,4,5> + 3365826337U, // <5,7,7,3>: Cost 4 vmrglw <1,6,5,7>, <5,2,7,3> + 3268015695U, // <5,7,7,4>: Cost 3 vsldoi12 <7,7,4,5>, <7,7,4,5> + 3365826258U, // <5,7,7,5>: Cost 4 vmrglw <1,6,5,7>, <5,1,7,5> + 4066259697U, // <5,7,7,6>: Cost 4 vsldoi4 <6,5,7,7>, <6,5,7,7> + 3384407660U, // <5,7,7,7>: Cost 3 vmrglw <4,7,5,7>, <7,7,7,7> + 3268310643U, // <5,7,7,u>: Cost 3 vsldoi12 <7,7,u,5>, <7,7,u,5> + 3385077858U, // <5,7,u,0>: Cost 3 vmrglw <4,u,5,u>, <5,6,7,0> + 4171134766U, // <5,7,u,1>: Cost 3 vsldoi8 <1,6,5,7>, LHS + 3255587988U, // <5,7,u,2>: Cost 3 vmrghw <5,6,7,0>, <7,2,0,3> + 3385078266U, // <5,7,u,3>: Cost 3 vmrglw <4,u,5,u>, <6,2,7,3> + 3385077862U, // <5,7,u,4>: Cost 3 vmrglw <4,u,5,u>, <5,6,7,4> + 4171135130U, // <5,7,u,5>: Cost 3 vsldoi8 <1,6,5,7>, RHS + 4066267890U, // <5,7,u,6>: Cost 3 vsldoi4 <6,5,7,u>, <6,5,7,u> + 3385078594U, // <5,7,u,7>: Cost 3 vmrglw <4,u,5,u>, <6,6,7,7> + 4171135333U, // <5,7,u,u>: Cost 3 vsldoi8 <1,6,5,7>, LHS + 4181753856U, // <5,u,0,0>: Cost 3 vsldoi8 <3,4,5,u>, <0,0,0,0> + 3108012134U, // <5,u,0,1>: Cost 2 vsldoi8 <3,4,5,u>, LHS + 3384349690U, // <5,u,0,2>: Cost 3 vmrglw <4,7,5,0>, <7,0,1,2> + 3376382108U, // <5,u,0,3>: Cost 3 vmrglw <3,4,5,0>, LHS + 3224000237U, // <5,u,0,4>: Cost 3 vsldoi12 <0,4,1,5>, + 3379037938U, // <5,u,0,5>: Cost 3 vmrglw <3,u,5,0>, <2,3,u,5> + 3251540066U, // <5,u,0,6>: Cost 3 vmrghw <5,0,6,1>, <5,6,7,0> + 3376385352U, // <5,u,0,7>: Cost 3 vmrglw <3,4,5,0>, RHS + 3108012701U, // <5,u,0,u>: Cost 2 vsldoi8 <3,4,5,u>, LHS + 4036419686U, // <5,u,1,0>: Cost 3 vsldoi4 <1,5,u,1>, LHS + 2311278106U, // <5,u,1,1>: Cost 2 vmrglw <4,u,5,1>, <4,u,5,1> + 3224000302U, // <5,u,1,2>: Cost 2 vsldoi12 <0,4,1,5>, LHS + 2311274652U, // <5,u,1,3>: Cost 2 vmrglw <4,u,5,1>, LHS + 4169811026U, // <5,u,1,4>: Cost 3 vsldoi8 <1,4,5,u>, <1,4,5,u> + 3226654534U, // <5,u,1,5>: Cost 3 vsldoi12 <0,u,1,5>, + 4171138292U, // <5,u,1,6>: Cost 3 vsldoi8 <1,6,5,u>, <1,6,5,u> + 2311277896U, // <5,u,1,7>: Cost 2 vmrglw <4,u,5,1>, RHS + 3224000356U, // <5,u,1,u>: Cost 2 vsldoi12 <0,4,1,5>, LHS + 3385030533U, // <5,u,2,0>: Cost 3 vmrglw <4,u,5,2>, + 3252516654U, // <5,u,2,1>: Cost 3 vmrghw <5,2,1,3>, LHS + 4175783528U, // <5,u,2,2>: Cost 3 vsldoi8 <2,4,5,u>, <2,2,2,2> + 3224000392U, // <5,u,2,3>: Cost 3 vsldoi12 <0,4,1,5>, + 4175783723U, // <5,u,2,4>: Cost 3 vsldoi8 <2,4,5,u>, <2,4,5,u> + 3227170714U, // <5,u,2,5>: Cost 3 vsldoi12 <0,u,u,5>, + 4181755834U, // <5,u,2,6>: Cost 3 vsldoi8 <3,4,5,u>, <2,6,3,7> + 3376401736U, // <5,u,2,7>: Cost 3 vmrglw <3,4,5,2>, RHS + 3224000437U, // <5,u,2,u>: Cost 3 vsldoi12 <0,4,1,5>, + 3224000444U, // <5,u,3,0>: Cost 3 vsldoi12 <0,4,1,5>, + 3224000453U, // <5,u,3,1>: Cost 4 vsldoi12 <0,4,1,5>, + 4053911246U, // <5,u,3,2>: Cost 3 vsldoi4 <4,5,2,3>, <2,3,4,5> + 3363135644U, // <5,u,3,3>: Cost 3 vmrglw <1,2,5,3>, LHS + 3108014596U, // <5,u,3,4>: Cost 2 vsldoi8 <3,4,5,u>, <3,4,5,u> + 3254818797U, // <5,u,3,5>: Cost 3 vsldoi12 <5,5,5,5>, + 3363138077U, // <5,u,3,6>: Cost 4 vmrglw <1,2,5,3>, <3,4,u,6> + 3363138888U, // <5,u,3,7>: Cost 3 vmrglw <1,2,5,3>, RHS + 3110669128U, // <5,u,3,u>: Cost 2 vsldoi8 <3,u,5,u>, <3,u,5,u> + 3111332761U, // <5,u,4,0>: Cost 2 vsldoi8 <4,0,5,u>, <4,0,5,u> + 3271776282U, // <5,u,4,1>: Cost 2 vsldoi12 , + 4186401851U, // <5,u,4,2>: Cost 3 vsldoi8 <4,2,5,u>, <4,2,5,u> + 3235502124U, // <5,u,4,3>: Cost 3 vsldoi12 <2,3,4,5>, + 3113987293U, // <5,u,4,4>: Cost 2 vsldoi8 <4,4,5,u>, <4,4,5,u> + 3108015414U, // <5,u,4,5>: Cost 2 vsldoi8 <3,4,5,u>, RHS + 4189056383U, // <5,u,4,6>: Cost 3 vsldoi8 <4,6,5,u>, <4,6,5,u> + 3376418120U, // <5,u,4,7>: Cost 3 vmrglw <3,4,5,4>, RHS + 3108015657U, // <5,u,4,u>: Cost 2 vsldoi8 <3,4,5,u>, RHS + 2986377318U, // <5,u,5,0>: Cost 2 vsldoi4 <5,5,5,5>, LHS + 2181076782U, // <5,u,5,1>: Cost 2 vmrghw <5,5,5,5>, LHS + 3235797106U, // <5,u,5,2>: Cost 3 vsldoi12 <2,3,u,5>, + 2311307420U, // <5,u,5,3>: Cost 2 vmrglw <4,u,5,5>, LHS + 2986380598U, // <5,u,5,4>: Cost 2 vsldoi4 <5,5,5,5>, RHS + 1504103734U, // <5,u,5,5>: Cost 1 vspltisw1 RHS + 3224000666U, // <5,u,5,6>: Cost 2 vsldoi12 <0,4,1,5>, RHS + 2311310664U, // <5,u,5,7>: Cost 2 vmrglw <4,u,5,5>, RHS + 1504103734U, // <5,u,5,u>: Cost 1 vspltisw1 RHS + 4042432614U, // <5,u,6,0>: Cost 3 vsldoi4 <2,5,u,6>, LHS + 2181846830U, // <5,u,6,1>: Cost 2 vmrghw <5,6,7,0>, LHS + 4042434453U, // <5,u,6,2>: Cost 3 vsldoi4 <2,5,u,6>, <2,5,u,6> + 2302689436U, // <5,u,6,3>: Cost 2 vmrglw <3,4,5,6>, LHS + 4042435894U, // <5,u,6,4>: Cost 3 vsldoi4 <2,5,u,6>, RHS + 2181847194U, // <5,u,6,5>: Cost 2 vmrghw <5,6,7,0>, RHS + 2302691842U, // <5,u,6,6>: Cost 2 vmrglw <3,4,5,6>, <3,4,5,6> + 2302692680U, // <5,u,6,7>: Cost 2 vmrglw <3,4,5,6>, RHS + 2302689441U, // <5,u,6,u>: Cost 2 vmrglw <3,4,5,6>, LHS + 1906901094U, // <5,u,7,0>: Cost 1 vsldoi4 RHS, LHS + 2980643636U, // <5,u,7,1>: Cost 2 vsldoi4 RHS, <1,1,1,1> + 2980644456U, // <5,u,7,2>: Cost 2 vsldoi4 RHS, <2,2,2,2> + 2980645014U, // <5,u,7,3>: Cost 2 vsldoi4 RHS, <3,0,1,2> + 1906904392U, // <5,u,7,4>: Cost 1 vsldoi4 RHS, RHS + 2980646916U, // <5,u,7,5>: Cost 2 vsldoi4 RHS, <5,5,5,5> + 2980647418U, // <5,u,7,6>: Cost 2 vsldoi4 RHS, <6,2,7,3> + 2980647930U, // <5,u,7,7>: Cost 2 vsldoi4 RHS, <7,0,1,2> + 1906906926U, // <5,u,7,u>: Cost 1 vsldoi4 RHS, LHS + 1906909286U, // <5,u,u,0>: Cost 1 vsldoi4 RHS, LHS + 3108017966U, // <5,u,u,1>: Cost 2 vsldoi8 <3,4,5,u>, LHS + 3224000869U, // <5,u,u,2>: Cost 2 vsldoi12 <0,4,1,5>, LHS + 2302705820U, // <5,u,u,3>: Cost 2 vmrglw <3,4,5,u>, LHS + 1906912585U, // <5,u,u,4>: Cost 1 vsldoi4 RHS, RHS + 1504103734U, // <5,u,u,5>: Cost 1 vspltisw1 RHS + 3224000909U, // <5,u,u,6>: Cost 2 vsldoi12 <0,4,1,5>, RHS + 2302709064U, // <5,u,u,7>: Cost 2 vmrglw <3,4,5,u>, RHS + 1906915118U, // <5,u,u,u>: Cost 1 vsldoi4 RHS, LHS + 3242213376U, // <6,0,0,0>: Cost 3 vsldoi12 <3,4,5,6>, <0,0,0,0> + 3242213386U, // <6,0,0,1>: Cost 3 vsldoi12 <3,4,5,6>, <0,0,1,1> + 4173799601U, // <6,0,0,2>: Cost 4 vsldoi8 <2,1,6,0>, <0,2,1,6> + 3383095739U, // <6,0,0,3>: Cost 4 vmrglw <4,5,6,0>, <6,2,0,3> + 3242213413U, // <6,0,0,4>: Cost 4 vsldoi12 <3,4,5,6>, <0,0,4,1> + 4060377123U, // <6,0,0,5>: Cost 4 vsldoi4 <5,6,0,0>, <5,6,0,0> + 3383095985U, // <6,0,0,6>: Cost 4 vmrglw <4,5,6,0>, <6,5,0,6> + 3383096067U, // <6,0,0,7>: Cost 4 vmrglw <4,5,6,0>, <6,6,0,7> + 3242213449U, // <6,0,0,u>: Cost 3 vsldoi12 <3,4,5,6>, <0,0,u,1> + 4060381286U, // <6,0,1,0>: Cost 3 vsldoi4 <5,6,0,1>, LHS + 3258245222U, // <6,0,1,1>: Cost 3 vmrghw <6,1,7,1>, LHS + 3242213478U, // <6,0,1,2>: Cost 2 vsldoi12 <3,4,5,6>, LHS + 4060383746U, // <6,0,1,3>: Cost 3 vsldoi4 <5,6,0,1>, <3,4,5,6> + 4060384566U, // <6,0,1,4>: Cost 3 vsldoi4 <5,6,0,1>, RHS + 4060385316U, // <6,0,1,5>: Cost 3 vsldoi4 <5,6,0,1>, <5,6,0,1> + 4066358013U, // <6,0,1,6>: Cost 3 vsldoi4 <6,6,0,1>, <6,6,0,1> + 4060386298U, // <6,0,1,7>: Cost 4 vsldoi4 <5,6,0,1>, <7,0,1,2> + 3242213532U, // <6,0,1,u>: Cost 2 vsldoi12 <3,4,5,6>, LHS + 3258925056U, // <6,0,2,0>: Cost 3 vmrghw <6,2,7,3>, <0,0,0,0> + 2185183334U, // <6,0,2,1>: Cost 2 vmrghw <6,2,7,3>, LHS + 3222675642U, // <6,0,2,2>: Cost 4 vsldoi12 <0,2,1,6>, <0,2,2,6> + 4180436669U, // <6,0,2,3>: Cost 4 vsldoi8 <3,2,6,0>, <2,3,2,6> + 3258925394U, // <6,0,2,4>: Cost 3 vmrghw <6,2,7,3>, <0,4,1,5> + 4188399464U, // <6,0,2,5>: Cost 4 vsldoi8 <4,5,6,0>, <2,5,3,6> + 3258925553U, // <6,0,2,6>: Cost 3 vmrghw <6,2,7,3>, <0,6,1,2> + 4072338903U, // <6,0,2,7>: Cost 4 vsldoi4 <7,6,0,2>, <7,6,0,2> + 2185183901U, // <6,0,2,u>: Cost 2 vmrghw <6,2,7,3>, LHS + 3375153152U, // <6,0,3,0>: Cost 4 vmrglw <3,2,6,3>, <0,0,0,0> + 3242213632U, // <6,0,3,1>: Cost 3 vsldoi12 <3,4,5,6>, <0,3,1,4> + 4180437347U, // <6,0,3,2>: Cost 4 vsldoi8 <3,2,6,0>, <3,2,6,0> + 3242213650U, // <6,0,3,3>: Cost 4 vsldoi12 <3,4,5,6>, <0,3,3,4> + 4188400130U, // <6,0,3,4>: Cost 3 vsldoi8 <4,5,6,0>, <3,4,5,6> + 4060401702U, // <6,0,3,5>: Cost 4 vsldoi4 <5,6,0,3>, <5,6,0,3> + 4204989048U, // <6,0,3,6>: Cost 4 vsldoi8 <7,3,6,0>, <3,6,0,7> + 4204325594U, // <6,0,3,7>: Cost 4 vsldoi8 <7,2,6,0>, <3,7,2,6> + 3242213695U, // <6,0,3,u>: Cost 3 vsldoi12 <3,4,5,6>, <0,3,u,4> + 3383123968U, // <6,0,4,0>: Cost 4 vmrglw <4,5,6,4>, <0,0,0,0> + 3242213714U, // <6,0,4,1>: Cost 3 vsldoi12 <3,4,5,6>, <0,4,1,5> + 4176456761U, // <6,0,4,2>: Cost 4 vsldoi8 <2,5,6,0>, <4,2,5,6> + 4060408322U, // <6,0,4,3>: Cost 4 vsldoi4 <5,6,0,4>, <3,4,5,6> + 3242213741U, // <6,0,4,4>: Cost 4 vsldoi12 <3,4,5,6>, <0,4,4,5> + 4188400943U, // <6,0,4,5>: Cost 3 vsldoi8 <4,5,6,0>, <4,5,6,0> + 3259900401U, // <6,0,4,6>: Cost 4 vmrghw <6,4,2,5>, <0,6,1,2> + 3383126648U, // <6,0,4,7>: Cost 5 vmrglw <4,5,6,4>, <3,6,0,7> + 3242213777U, // <6,0,4,u>: Cost 3 vsldoi12 <3,4,5,6>, <0,4,u,5> + 3373178880U, // <6,0,5,0>: Cost 4 vmrglw <2,u,6,5>, <0,0,0,0> + 3260899430U, // <6,0,5,1>: Cost 3 vmrghw <6,5,7,1>, LHS + 4188401432U, // <6,0,5,2>: Cost 4 vsldoi8 <4,5,6,0>, <5,2,6,3> + 4193046374U, // <6,0,5,3>: Cost 4 vsldoi8 <5,3,6,0>, <5,3,6,0> + 3260891474U, // <6,0,5,4>: Cost 4 vmrghw <6,5,7,0>, <0,4,1,5> + 4188401678U, // <6,0,5,5>: Cost 4 vsldoi8 <4,5,6,0>, <5,5,6,6> + 4188401700U, // <6,0,5,6>: Cost 4 vsldoi8 <4,5,6,0>, <5,6,0,1> + 3379153528U, // <6,0,5,7>: Cost 4 vmrglw <3,u,6,5>, <3,6,0,7> + 3260899997U, // <6,0,5,u>: Cost 3 vmrghw <6,5,7,1>, LHS + 3261530112U, // <6,0,6,0>: Cost 3 vmrghw <6,6,6,6>, <0,0,0,0> + 2187788390U, // <6,0,6,1>: Cost 2 vmrghw <6,6,6,6>, LHS + 4188402107U, // <6,0,6,2>: Cost 4 vsldoi8 <4,5,6,0>, <6,2,0,3> + 4188402226U, // <6,0,6,3>: Cost 4 vsldoi8 <4,5,6,0>, <6,3,4,5> + 3261530450U, // <6,0,6,4>: Cost 3 vmrghw <6,6,6,6>, <0,4,1,5> + 4188402353U, // <6,0,6,5>: Cost 4 vsldoi8 <4,5,6,0>, <6,5,0,6> + 4201009970U, // <6,0,6,6>: Cost 3 vsldoi8 <6,6,6,0>, <6,6,6,0> + 4190393166U, // <6,0,6,7>: Cost 4 vsldoi8 <4,u,6,0>, <6,7,0,1> + 2187788957U, // <6,0,6,u>: Cost 2 vmrghw <6,6,6,6>, LHS + 2309406720U, // <6,0,7,0>: Cost 2 vmrglw RHS, <0,0,0,0> + 2309408422U, // <6,0,7,1>: Cost 2 vmrglw RHS, <2,3,0,1> + 4048488040U, // <6,0,7,2>: Cost 4 vsldoi4 <3,6,0,7>, <2,2,2,2> + 4048489080U, // <6,0,7,3>: Cost 3 vsldoi4 <3,6,0,7>, <3,6,0,7> + 4048489782U, // <6,0,7,4>: Cost 3 vsldoi4 <3,6,0,7>, RHS + 3383151060U, // <6,0,7,5>: Cost 3 vmrglw RHS, <3,4,0,5> + 4048490837U, // <6,0,7,6>: Cost 4 vsldoi4 <3,6,0,7>, <6,0,7,0> + 3383151224U, // <6,0,7,7>: Cost 3 vmrglw RHS, <3,6,0,7> + 2309408429U, // <6,0,7,u>: Cost 2 vmrglw RHS, <2,3,0,u> + 2309414912U, // <6,0,u,0>: Cost 2 vmrglw RHS, <0,0,0,0> + 2309416614U, // <6,0,u,1>: Cost 2 vmrglw RHS, <2,3,0,1> + 3242214045U, // <6,0,u,2>: Cost 2 vsldoi12 <3,4,5,6>, LHS + 4048497273U, // <6,0,u,3>: Cost 3 vsldoi4 <3,6,0,u>, <3,6,0,u> + 4048497974U, // <6,0,u,4>: Cost 3 vsldoi4 <3,6,0,u>, RHS + 4188403866U, // <6,0,u,5>: Cost 3 vsldoi8 <4,5,6,0>, RHS + 4066415364U, // <6,0,u,6>: Cost 3 vsldoi4 <6,6,0,u>, <6,6,0,u> + 3383159416U, // <6,0,u,7>: Cost 3 vmrglw RHS, <3,6,0,7> + 3242214099U, // <6,0,u,u>: Cost 2 vsldoi12 <3,4,5,6>, LHS + 4178452480U, // <6,1,0,0>: Cost 4 vsldoi8 <2,u,6,1>, <0,0,0,0> + 4178452582U, // <6,1,0,1>: Cost 3 vsldoi8 <2,u,6,1>, LHS + 3373143763U, // <6,1,0,2>: Cost 4 vmrglw <2,u,6,0>, + 4030589442U, // <6,1,0,3>: Cost 4 vsldoi4 <0,6,1,0>, <3,4,5,6> + 4178452818U, // <6,1,0,4>: Cost 4 vsldoi8 <2,u,6,1>, <0,4,1,5> + 3383091538U, // <6,1,0,5>: Cost 4 vmrglw <4,5,6,0>, <0,4,1,5> + 3368493233U, // <6,1,0,6>: Cost 4 vmrglw <2,1,6,0>, <0,2,1,6> + 3362522319U, // <6,1,0,7>: Cost 5 vmrglw <1,1,6,0>, <1,6,1,7> + 4178453149U, // <6,1,0,u>: Cost 3 vsldoi8 <2,u,6,1>, LHS + 3230270251U, // <6,1,1,0>: Cost 4 vsldoi12 <1,4,5,6>, <1,1,0,1> + 3242214196U, // <6,1,1,1>: Cost 3 vsldoi12 <3,4,5,6>, <1,1,1,1> + 3228058434U, // <6,1,1,2>: Cost 4 vsldoi12 <1,1,2,6>, <1,1,2,6> + 3373150660U, // <6,1,1,3>: Cost 4 vmrglw <2,u,6,1>, <6,2,1,3> + 3230270291U, // <6,1,1,4>: Cost 4 vsldoi12 <1,4,5,6>, <1,1,4,5> + 3373146450U, // <6,1,1,5>: Cost 4 vmrglw <2,u,6,1>, <0,4,1,5> + 3222676326U, // <6,1,1,6>: Cost 4 vsldoi12 <0,2,1,6>, <1,1,6,6> + 3362530511U, // <6,1,1,7>: Cost 4 vmrglw <1,1,6,1>, <1,6,1,7> + 3242214196U, // <6,1,1,u>: Cost 3 vsldoi12 <3,4,5,6>, <1,1,1,1> + 4078379110U, // <6,1,2,0>: Cost 3 vsldoi4 , LHS + 3258925876U, // <6,1,2,1>: Cost 3 vmrghw <6,2,7,3>, <1,1,1,1> + 3258925974U, // <6,1,2,2>: Cost 3 vmrghw <6,2,7,3>, <1,2,3,0> + 3242214294U, // <6,1,2,3>: Cost 3 vsldoi12 <3,4,5,6>, <1,2,3,0> + 4078382390U, // <6,1,2,4>: Cost 3 vsldoi4 , RHS + 3242214315U, // <6,1,2,5>: Cost 4 vsldoi12 <3,4,5,6>, <1,2,5,3> + 4178454458U, // <6,1,2,6>: Cost 3 vsldoi8 <2,u,6,1>, <2,6,3,7> + 3266102202U, // <6,1,2,7>: Cost 4 vsldoi12 <7,4,5,6>, <1,2,7,0> + 4178454641U, // <6,1,2,u>: Cost 3 vsldoi8 <2,u,6,1>, <2,u,6,1> + 4178454678U, // <6,1,3,0>: Cost 4 vsldoi8 <2,u,6,1>, <3,0,1,2> + 4179781907U, // <6,1,3,1>: Cost 4 vsldoi8 <3,1,6,1>, <3,1,6,1> + 4178454886U, // <6,1,3,2>: Cost 4 vsldoi8 <2,u,6,1>, <3,2,6,3> + 4178454940U, // <6,1,3,3>: Cost 4 vsldoi8 <2,u,6,1>, <3,3,3,3> + 4178455042U, // <6,1,3,4>: Cost 4 vsldoi8 <2,u,6,1>, <3,4,5,6> + 3375153490U, // <6,1,3,5>: Cost 4 vmrglw <3,2,6,3>, <0,4,1,5> + 3222676489U, // <6,1,3,6>: Cost 4 vsldoi12 <0,2,1,6>, <1,3,6,7> + 4178455235U, // <6,1,3,7>: Cost 4 vsldoi8 <2,u,6,1>, <3,7,0,1> + 4178455326U, // <6,1,3,u>: Cost 4 vsldoi8 <2,u,6,1>, <3,u,1,2> + 3242214430U, // <6,1,4,0>: Cost 4 vsldoi12 <3,4,5,6>, <1,4,0,1> + 3242214443U, // <6,1,4,1>: Cost 4 vsldoi12 <3,4,5,6>, <1,4,1,5> + 3242214452U, // <6,1,4,2>: Cost 4 vsldoi12 <3,4,5,6>, <1,4,2,5> + 3242214460U, // <6,1,4,3>: Cost 4 vsldoi12 <3,4,5,6>, <1,4,3,4> + 3242214470U, // <6,1,4,4>: Cost 4 vsldoi12 <3,4,5,6>, <1,4,4,5> + 3230270544U, // <6,1,4,5>: Cost 3 vsldoi12 <1,4,5,6>, <1,4,5,6> + 3368526001U, // <6,1,4,6>: Cost 4 vmrglw <2,1,6,4>, <0,2,1,6> + 3266102368U, // <6,1,4,7>: Cost 4 vsldoi12 <7,4,5,6>, <1,4,7,4> + 3230491755U, // <6,1,4,u>: Cost 3 vsldoi12 <1,4,u,6>, <1,4,u,6> + 4191063668U, // <6,1,5,0>: Cost 3 vsldoi8 <5,0,6,1>, <5,0,6,1> + 3230639229U, // <6,1,5,1>: Cost 4 vsldoi12 <1,5,1,6>, <1,5,1,6> + 3230712966U, // <6,1,5,2>: Cost 4 vsldoi12 <1,5,2,6>, <1,5,2,6> + 3242214541U, // <6,1,5,3>: Cost 4 vsldoi12 <3,4,5,6>, <1,5,3,4> + 3230860440U, // <6,1,5,4>: Cost 4 vsldoi12 <1,5,4,6>, <1,5,4,6> + 3230934177U, // <6,1,5,5>: Cost 4 vsldoi12 <1,5,5,6>, <1,5,5,6> + 4196372578U, // <6,1,5,6>: Cost 3 vsldoi8 <5,u,6,1>, <5,6,7,0> + 3367208143U, // <6,1,5,7>: Cost 4 vmrglw <1,u,6,5>, <1,6,1,7> + 4196372732U, // <6,1,5,u>: Cost 3 vsldoi8 <5,u,6,1>, <5,u,6,1> + 4078411878U, // <6,1,6,0>: Cost 3 vsldoi4 , LHS + 3261530932U, // <6,1,6,1>: Cost 3 vmrghw <6,6,6,6>, <1,1,1,1> + 3261531030U, // <6,1,6,2>: Cost 3 vmrghw <6,6,6,6>, <1,2,3,0> + 4178457113U, // <6,1,6,3>: Cost 4 vsldoi8 <2,u,6,1>, <6,3,1,7> + 4078415158U, // <6,1,6,4>: Cost 3 vsldoi4 , RHS + 3395748178U, // <6,1,6,5>: Cost 3 vmrglw <6,6,6,6>, <0,4,1,5> + 4202345272U, // <6,1,6,6>: Cost 3 vsldoi8 <6,u,6,1>, <6,6,6,6> + 4196373326U, // <6,1,6,7>: Cost 4 vsldoi8 <5,u,6,1>, <6,7,0,1> + 3261531516U, // <6,1,6,u>: Cost 3 vmrghw <6,6,6,6>, <1,u,3,0> + 4036616294U, // <6,1,7,0>: Cost 3 vsldoi4 <1,6,1,7>, LHS + 2309406730U, // <6,1,7,1>: Cost 2 vmrglw RHS, <0,0,1,1> + 2309408918U, // <6,1,7,2>: Cost 2 vmrglw RHS, <3,0,1,2> + 3383148718U, // <6,1,7,3>: Cost 3 vmrglw RHS, <0,2,1,3> + 4036619574U, // <6,1,7,4>: Cost 3 vsldoi4 <1,6,1,7>, RHS + 2309407058U, // <6,1,7,5>: Cost 2 vmrglw RHS, <0,4,1,5> + 3383148721U, // <6,1,7,6>: Cost 3 vmrglw RHS, <0,2,1,6> + 3383149046U, // <6,1,7,7>: Cost 3 vmrglw RHS, <0,6,1,7> + 2309406737U, // <6,1,7,u>: Cost 2 vmrglw RHS, <0,0,1,u> + 4036624486U, // <6,1,u,0>: Cost 3 vsldoi4 <1,6,1,u>, LHS + 2309414922U, // <6,1,u,1>: Cost 2 vmrglw RHS, <0,0,1,1> + 2309417110U, // <6,1,u,2>: Cost 2 vmrglw RHS, <3,0,1,2> + 3242214780U, // <6,1,u,3>: Cost 3 vsldoi12 <3,4,5,6>, <1,u,3,0> + 4036627766U, // <6,1,u,4>: Cost 3 vsldoi4 <1,6,1,u>, RHS + 2309415250U, // <6,1,u,5>: Cost 2 vmrglw RHS, <0,4,1,5> + 3383156913U, // <6,1,u,6>: Cost 3 vmrglw RHS, <0,2,1,6> + 3383157238U, // <6,1,u,7>: Cost 3 vmrglw RHS, <0,6,1,7> + 2309414929U, // <6,1,u,u>: Cost 2 vmrglw RHS, <0,0,1,u> + 3257574861U, // <6,2,0,0>: Cost 4 vmrghw <6,0,7,0>, <2,0,3,0> + 4201685094U, // <6,2,0,1>: Cost 3 vsldoi8 <6,7,6,2>, LHS + 4173815985U, // <6,2,0,2>: Cost 4 vsldoi8 <2,1,6,2>, <0,2,1,6> + 3383091302U, // <6,2,0,3>: Cost 3 vmrglw <4,5,6,0>, LHS + 4066495798U, // <6,2,0,4>: Cost 4 vsldoi4 <6,6,2,0>, RHS + 3236759008U, // <6,2,0,5>: Cost 4 vsldoi12 <2,5,3,6>, <2,0,5,1> + 3238675945U, // <6,2,0,6>: Cost 4 vsldoi12 <2,u,2,6>, <2,0,6,1> + 4072469991U, // <6,2,0,7>: Cost 4 vsldoi4 <7,6,2,0>, <7,6,2,0> + 3383091307U, // <6,2,0,u>: Cost 3 vmrglw <4,5,6,0>, LHS + 3367840468U, // <6,2,1,0>: Cost 4 vmrglw <2,0,6,1>, <3,7,2,0> + 3258246687U, // <6,2,1,1>: Cost 4 vmrghw <6,1,7,1>, <2,1,3,1> + 3373147752U, // <6,2,1,2>: Cost 4 vmrglw <2,u,6,1>, <2,2,2,2> + 3373146214U, // <6,2,1,3>: Cost 3 vmrglw <2,u,6,1>, LHS + 4036644150U, // <6,2,1,4>: Cost 5 vsldoi4 <1,6,2,1>, RHS + 4170499238U, // <6,2,1,5>: Cost 4 vsldoi8 <1,5,6,2>, <1,5,6,2> + 3222677049U, // <6,2,1,6>: Cost 4 vsldoi12 <0,2,1,6>, <2,1,6,0> + 3373147838U, // <6,2,1,7>: Cost 5 vmrglw <2,u,6,1>, <2,3,2,7> + 3373146219U, // <6,2,1,u>: Cost 3 vmrglw <2,u,6,1>, LHS + 4066508902U, // <6,2,2,0>: Cost 3 vsldoi4 <6,6,2,2>, LHS + 4173817403U, // <6,2,2,1>: Cost 4 vsldoi8 <2,1,6,2>, <2,1,6,2> + 3236243048U, // <6,2,2,2>: Cost 3 vsldoi12 <2,4,5,6>, <2,2,2,2> + 3242215026U, // <6,2,2,3>: Cost 3 vsldoi12 <3,4,5,6>, <2,2,3,3> + 4066512182U, // <6,2,2,4>: Cost 3 vsldoi4 <6,6,2,2>, RHS + 4193060712U, // <6,2,2,5>: Cost 4 vsldoi8 <5,3,6,2>, <2,5,3,6> + 3258927034U, // <6,2,2,6>: Cost 3 vmrghw <6,2,7,3>, <2,6,3,7> + 3258927108U, // <6,2,2,7>: Cost 3 vmrghw <6,2,7,3>, <2,7,3,0> + 3242215071U, // <6,2,2,u>: Cost 3 vsldoi12 <3,4,5,6>, <2,2,u,3> + 3242215078U, // <6,2,3,0>: Cost 3 vsldoi12 <3,4,5,6>, <2,3,0,1> + 3230271154U, // <6,2,3,1>: Cost 4 vsldoi12 <1,4,5,6>, <2,3,1,4> + 3235358397U, // <6,2,3,2>: Cost 3 vsldoi12 <2,3,2,6>, <2,3,2,6> + 3375153254U, // <6,2,3,3>: Cost 3 vmrglw <3,2,6,3>, LHS + 3242215118U, // <6,2,3,4>: Cost 3 vsldoi12 <3,4,5,6>, <2,3,4,5> + 3235579608U, // <6,2,3,5>: Cost 3 vsldoi12 <2,3,5,6>, <2,3,5,6> + 3259566010U, // <6,2,3,6>: Cost 3 vmrghw <6,3,7,0>, <2,6,3,7> + 3266103016U, // <6,2,3,7>: Cost 3 vsldoi12 <7,4,5,6>, <2,3,7,4> + 3235800819U, // <6,2,3,u>: Cost 3 vsldoi12 <2,3,u,6>, <2,3,u,6> + 4060553318U, // <6,2,4,0>: Cost 4 vsldoi4 <5,6,2,4>, LHS + 3368530217U, // <6,2,4,1>: Cost 5 vmrglw <2,1,6,4>, <6,0,2,1> + 3236243213U, // <6,2,4,2>: Cost 4 vsldoi12 <2,4,5,6>, <2,4,2,5> + 3383124070U, // <6,2,4,3>: Cost 3 vmrglw <4,5,6,4>, LHS + 4060556598U, // <6,2,4,4>: Cost 4 vsldoi4 <5,6,2,4>, RHS + 3236243241U, // <6,2,4,5>: Cost 3 vsldoi12 <2,4,5,6>, <2,4,5,6> + 3238676273U, // <6,2,4,6>: Cost 4 vsldoi12 <2,u,2,6>, <2,4,6,5> + 3259901956U, // <6,2,4,7>: Cost 4 vmrghw <6,4,2,5>, <2,7,3,0> + 3236464452U, // <6,2,4,u>: Cost 3 vsldoi12 <2,4,u,6>, <2,4,u,6> + 4048617574U, // <6,2,5,0>: Cost 4 vsldoi4 <3,6,2,5>, LHS + 4191735494U, // <6,2,5,1>: Cost 4 vsldoi8 <5,1,6,2>, <5,1,6,2> + 3236685663U, // <6,2,5,2>: Cost 4 vsldoi12 <2,5,2,6>, <2,5,2,6> + 3236759400U, // <6,2,5,3>: Cost 3 vsldoi12 <2,5,3,6>, <2,5,3,6> + 4048620854U, // <6,2,5,4>: Cost 4 vsldoi4 <3,6,2,5>, RHS + 4194390026U, // <6,2,5,5>: Cost 4 vsldoi8 <5,5,6,2>, <5,5,6,2> + 3373180605U, // <6,2,5,6>: Cost 4 vmrglw <2,u,6,5>, <2,3,2,6> + 4195717292U, // <6,2,5,7>: Cost 4 vsldoi8 <5,7,6,2>, <5,7,6,2> + 3237128085U, // <6,2,5,u>: Cost 3 vsldoi12 <2,5,u,6>, <2,5,u,6> + 4036681830U, // <6,2,6,0>: Cost 4 vsldoi4 <1,6,2,6>, LHS + 4036682967U, // <6,2,6,1>: Cost 4 vsldoi4 <1,6,2,6>, <1,6,2,6> + 3261531752U, // <6,2,6,2>: Cost 3 vmrghw <6,6,6,6>, <2,2,2,2> + 2322006118U, // <6,2,6,3>: Cost 2 vmrglw <6,6,6,6>, LHS + 4036685110U, // <6,2,6,4>: Cost 4 vsldoi4 <1,6,2,6>, RHS + 4060573755U, // <6,2,6,5>: Cost 4 vsldoi4 <5,6,2,6>, <5,6,2,6> + 3261532090U, // <6,2,6,6>: Cost 3 vmrghw <6,6,6,6>, <2,6,3,7> + 4201689989U, // <6,2,6,7>: Cost 3 vsldoi8 <6,7,6,2>, <6,7,6,2> + 2322006123U, // <6,2,6,u>: Cost 2 vmrglw <6,6,6,6>, LHS + 4042661990U, // <6,2,7,0>: Cost 3 vsldoi4 <2,6,2,7>, LHS + 3383149292U, // <6,2,7,1>: Cost 3 vmrglw RHS, <1,0,2,1> + 2309408360U, // <6,2,7,2>: Cost 2 vmrglw RHS, <2,2,2,2> + 1235664998U, // <6,2,7,3>: Cost 1 vmrglw RHS, LHS + 4042665270U, // <6,2,7,4>: Cost 3 vsldoi4 <2,6,2,7>, RHS + 3383149620U, // <6,2,7,5>: Cost 3 vmrglw RHS, <1,4,2,5> + 3383150269U, // <6,2,7,6>: Cost 3 vmrglw RHS, <2,3,2,6> + 3383149784U, // <6,2,7,7>: Cost 3 vmrglw RHS, <1,6,2,7> + 1235665003U, // <6,2,7,u>: Cost 1 vmrglw RHS, LHS + 4042670182U, // <6,2,u,0>: Cost 3 vsldoi4 <2,6,2,u>, LHS + 3383157484U, // <6,2,u,1>: Cost 3 vmrglw RHS, <1,0,2,1> + 2309416552U, // <6,2,u,2>: Cost 2 vmrglw RHS, <2,2,2,2> + 1235673190U, // <6,2,u,3>: Cost 1 vmrglw RHS, LHS + 4042673462U, // <6,2,u,4>: Cost 3 vsldoi4 <2,6,2,u>, RHS + 3238897773U, // <6,2,u,5>: Cost 3 vsldoi12 <2,u,5,6>, <2,u,5,6> + 3383158461U, // <6,2,u,6>: Cost 3 vmrglw RHS, <2,3,2,6> + 3383157976U, // <6,2,u,7>: Cost 3 vmrglw RHS, <1,6,2,7> + 1235673195U, // <6,2,u,u>: Cost 1 vmrglw RHS, LHS + 4180459520U, // <6,3,0,0>: Cost 4 vsldoi8 <3,2,6,3>, <0,0,0,0> + 4180459622U, // <6,3,0,1>: Cost 3 vsldoi8 <3,2,6,3>, LHS + 4168515761U, // <6,3,0,2>: Cost 4 vsldoi8 <1,2,6,3>, <0,2,1,6> + 3239413932U, // <6,3,0,3>: Cost 4 vsldoi12 <3,0,3,6>, <3,0,3,6> + 3257149954U, // <6,3,0,4>: Cost 3 vmrghw <6,0,1,2>, <3,4,5,6> + 4060598334U, // <6,3,0,5>: Cost 4 vsldoi4 <5,6,3,0>, <5,6,3,0> + 3383093096U, // <6,3,0,6>: Cost 4 vmrglw <4,5,6,0>, <2,5,3,6> + 3368495034U, // <6,3,0,7>: Cost 4 vmrglw <2,1,6,0>, <2,6,3,7> + 4180460189U, // <6,3,0,u>: Cost 3 vsldoi8 <3,2,6,3>, LHS + 3258255510U, // <6,3,1,0>: Cost 3 vmrghw <6,1,7,2>, <3,0,1,2> + 4180460340U, // <6,3,1,1>: Cost 4 vsldoi8 <3,2,6,3>, <1,1,1,1> + 4168516532U, // <6,3,1,2>: Cost 4 vsldoi8 <1,2,6,3>, <1,2,6,3> + 3373147762U, // <6,3,1,3>: Cost 4 vmrglw <2,u,6,1>, <2,2,3,3> + 3230271749U, // <6,3,1,4>: Cost 4 vsldoi12 <1,4,5,6>, <3,1,4,5> + 3373147683U, // <6,3,1,5>: Cost 5 vmrglw <2,u,6,1>, <2,1,3,5> + 3391727545U, // <6,3,1,6>: Cost 4 vmrglw <6,0,6,1>, <2,6,3,6> + 3373148090U, // <6,3,1,7>: Cost 3 vmrglw <2,u,6,1>, <2,6,3,7> + 3258255510U, // <6,3,1,u>: Cost 3 vmrghw <6,1,7,2>, <3,0,1,2> + 3258927254U, // <6,3,2,0>: Cost 3 vmrghw <6,2,7,3>, <3,0,1,2> + 3258927334U, // <6,3,2,1>: Cost 4 vmrghw <6,2,7,3>, <3,1,1,1> + 4174489229U, // <6,3,2,2>: Cost 4 vsldoi8 <2,2,6,3>, <2,2,6,3> + 3258927516U, // <6,3,2,3>: Cost 3 vmrghw <6,2,7,3>, <3,3,3,3> + 3258927618U, // <6,3,2,4>: Cost 3 vmrghw <6,2,7,3>, <3,4,5,6> + 3236759901U, // <6,3,2,5>: Cost 4 vsldoi12 <2,5,3,6>, <3,2,5,3> + 4180461498U, // <6,3,2,6>: Cost 3 vsldoi8 <3,2,6,3>, <2,6,3,7> + 3368511418U, // <6,3,2,7>: Cost 4 vmrglw <2,1,6,2>, <2,6,3,7> + 3258927902U, // <6,3,2,u>: Cost 3 vmrghw <6,2,7,3>, <3,u,1,2> + 4042702950U, // <6,3,3,0>: Cost 4 vsldoi4 <2,6,3,3>, LHS + 4168517876U, // <6,3,3,1>: Cost 5 vsldoi8 <1,2,6,3>, <3,1,2,6> + 4180461926U, // <6,3,3,2>: Cost 3 vsldoi8 <3,2,6,3>, <3,2,6,3> + 3242215836U, // <6,3,3,3>: Cost 3 vsldoi12 <3,4,5,6>, <3,3,3,3> + 3242215847U, // <6,3,3,4>: Cost 3 vsldoi12 <3,4,5,6>, <3,3,4,5> + 4192406072U, // <6,3,3,5>: Cost 4 vsldoi8 <5,2,6,3>, <3,5,2,6> + 3236759994U, // <6,3,3,6>: Cost 4 vsldoi12 <2,5,3,6>, <3,3,6,6> + 3375155130U, // <6,3,3,7>: Cost 3 vmrglw <3,2,6,3>, <2,6,3,7> + 3244870091U, // <6,3,3,u>: Cost 3 vsldoi12 <3,u,5,6>, <3,3,u,5> + 4060627046U, // <6,3,4,0>: Cost 3 vsldoi4 <5,6,3,4>, LHS + 3242215898U, // <6,3,4,1>: Cost 4 vsldoi12 <3,4,5,6>, <3,4,1,2> + 3241994727U, // <6,3,4,2>: Cost 4 vsldoi12 <3,4,2,6>, <3,4,2,6> + 4060629506U, // <6,3,4,3>: Cost 3 vsldoi4 <5,6,3,4>, <3,4,5,6> + 4060630326U, // <6,3,4,4>: Cost 3 vsldoi4 <5,6,3,4>, RHS + 3242215938U, // <6,3,4,5>: Cost 2 vsldoi12 <3,4,5,6>, <3,4,5,6> + 3383125864U, // <6,3,4,6>: Cost 4 vmrglw <4,5,6,4>, <2,5,3,6> + 3368527802U, // <6,3,4,7>: Cost 4 vmrglw <2,1,6,4>, <2,6,3,7> + 3242437149U, // <6,3,4,u>: Cost 2 vsldoi12 <3,4,u,6>, <3,4,u,6> + 3373179798U, // <6,3,5,0>: Cost 4 vmrglw <2,u,6,5>, <1,2,3,0> + 4042720499U, // <6,3,5,1>: Cost 5 vsldoi4 <2,6,3,5>, <1,6,5,7> + 4192407320U, // <6,3,5,2>: Cost 3 vsldoi8 <5,2,6,3>, <5,2,6,3> + 3373180530U, // <6,3,5,3>: Cost 4 vmrglw <2,u,6,5>, <2,2,3,3> + 3260942850U, // <6,3,5,4>: Cost 3 vmrghw <6,5,7,6>, <3,4,5,6> + 4188426254U, // <6,3,5,5>: Cost 4 vsldoi8 <4,5,6,3>, <5,5,6,6> + 3236760156U, // <6,3,5,6>: Cost 4 vsldoi12 <2,5,3,6>, <3,5,6,6> + 3373180858U, // <6,3,5,7>: Cost 3 vmrglw <2,u,6,5>, <2,6,3,7> + 4196389118U, // <6,3,5,u>: Cost 3 vsldoi8 <5,u,6,3>, <5,u,6,3> + 3261532310U, // <6,3,6,0>: Cost 3 vmrghw <6,6,6,6>, <3,0,1,2> + 3261532390U, // <6,3,6,1>: Cost 4 vmrghw <6,6,6,6>, <3,1,1,1> + 4042729401U, // <6,3,6,2>: Cost 3 vsldoi4 <2,6,3,6>, <2,6,3,6> + 3261532572U, // <6,3,6,3>: Cost 3 vmrghw <6,6,6,6>, <3,3,3,3> + 3261532674U, // <6,3,6,4>: Cost 3 vmrghw <6,6,6,6>, <3,4,5,6> + 4188426956U, // <6,3,6,5>: Cost 4 vsldoi8 <4,5,6,3>, <6,5,3,6> + 4202361656U, // <6,3,6,6>: Cost 3 vsldoi8 <6,u,6,3>, <6,6,6,6> + 3395749818U, // <6,3,6,7>: Cost 3 vmrglw <6,6,6,6>, <2,6,3,7> + 3261532958U, // <6,3,6,u>: Cost 3 vmrghw <6,6,6,6>, <3,u,1,2> + 2968993894U, // <6,3,7,0>: Cost 2 vsldoi4 <2,6,3,7>, LHS + 4042736436U, // <6,3,7,1>: Cost 3 vsldoi4 <2,6,3,7>, <1,1,1,1> + 2968995770U, // <6,3,7,2>: Cost 2 vsldoi4 <2,6,3,7>, <2,6,3,7> + 2309408370U, // <6,3,7,3>: Cost 2 vmrglw RHS, <2,2,3,3> + 2968997174U, // <6,3,7,4>: Cost 2 vsldoi4 <2,6,3,7>, RHS + 3383150115U, // <6,3,7,5>: Cost 3 vmrglw RHS, <2,1,3,5> + 4042740296U, // <6,3,7,6>: Cost 3 vsldoi4 <2,6,3,7>, <6,3,7,0> + 2309408698U, // <6,3,7,7>: Cost 2 vmrglw RHS, <2,6,3,7> + 2968999726U, // <6,3,7,u>: Cost 2 vsldoi4 <2,6,3,7>, LHS + 2969002086U, // <6,3,u,0>: Cost 2 vsldoi4 <2,6,3,u>, LHS + 4042744628U, // <6,3,u,1>: Cost 3 vsldoi4 <2,6,3,u>, <1,1,1,1> + 2969003963U, // <6,3,u,2>: Cost 2 vsldoi4 <2,6,3,u>, <2,6,3,u> + 2309416562U, // <6,3,u,3>: Cost 2 vmrglw RHS, <2,2,3,3> + 2969005366U, // <6,3,u,4>: Cost 2 vsldoi4 <2,6,3,u>, RHS + 3244870470U, // <6,3,u,5>: Cost 2 vsldoi12 <3,u,5,6>, <3,u,5,6> + 4042748497U, // <6,3,u,6>: Cost 3 vsldoi4 <2,6,3,u>, <6,3,u,0> + 2309416890U, // <6,3,u,7>: Cost 2 vmrglw RHS, <2,6,3,7> + 2969007918U, // <6,3,u,u>: Cost 2 vsldoi4 <2,6,3,u>, LHS + 4188430336U, // <6,4,0,0>: Cost 4 vsldoi8 <4,5,6,4>, <0,0,0,0> + 4188430438U, // <6,4,0,1>: Cost 3 vsldoi8 <4,5,6,4>, LHS + 4173832369U, // <6,4,0,2>: Cost 4 vsldoi8 <2,1,6,4>, <0,2,1,6> + 3242216320U, // <6,4,0,3>: Cost 4 vsldoi12 <3,4,5,6>, <4,0,3,1> + 4188430674U, // <6,4,0,4>: Cost 4 vsldoi8 <4,5,6,4>, <0,4,1,5> + 3257150774U, // <6,4,0,5>: Cost 3 vmrghw <6,0,1,2>, RHS + 3257150839U, // <6,4,0,6>: Cost 4 vmrghw <6,0,1,2>, <4,6,5,0> + 3383092458U, // <6,4,0,7>: Cost 5 vmrglw <4,5,6,0>, <1,6,4,7> + 4188431005U, // <6,4,0,u>: Cost 3 vsldoi8 <4,5,6,4>, LHS + 3258248082U, // <6,4,1,0>: Cost 4 vmrghw <6,1,7,1>, <4,0,5,1> + 4188431156U, // <6,4,1,1>: Cost 4 vsldoi8 <4,5,6,4>, <1,1,1,1> + 3242216394U, // <6,4,1,2>: Cost 4 vsldoi12 <3,4,5,6>, <4,1,2,3> + 3258256516U, // <6,4,1,3>: Cost 4 vmrghw <6,1,7,2>, <4,3,5,0> + 3248188379U, // <6,4,1,4>: Cost 4 vsldoi12 <4,4,5,6>, <4,1,4,2> + 3258248502U, // <6,4,1,5>: Cost 3 vmrghw <6,1,7,1>, RHS + 3258248568U, // <6,4,1,6>: Cost 4 vmrghw <6,1,7,1>, <4,6,5,1> + 3266104312U, // <6,4,1,7>: Cost 4 vsldoi12 <7,4,5,6>, <4,1,7,4> + 3258248745U, // <6,4,1,u>: Cost 3 vmrghw <6,1,7,1>, RHS + 3258928018U, // <6,4,2,0>: Cost 3 vmrghw <6,2,7,3>, <4,0,5,1> + 4173833789U, // <6,4,2,1>: Cost 4 vsldoi8 <2,1,6,4>, <2,1,6,4> + 4188431976U, // <6,4,2,2>: Cost 4 vsldoi8 <4,5,6,4>, <2,2,2,2> + 4180469437U, // <6,4,2,3>: Cost 4 vsldoi8 <3,2,6,4>, <2,3,2,6> + 3258928336U, // <6,4,2,4>: Cost 3 vmrghw <6,2,7,3>, <4,4,4,4> + 2185186614U, // <6,4,2,5>: Cost 2 vmrghw <6,2,7,3>, RHS + 3258928505U, // <6,4,2,6>: Cost 3 vmrghw <6,2,7,3>, <4,6,5,2> + 3258928584U, // <6,4,2,7>: Cost 4 vmrghw <6,2,7,3>, <4,7,5,0> + 2185186857U, // <6,4,2,u>: Cost 2 vmrghw <6,2,7,3>, RHS + 4188432534U, // <6,4,3,0>: Cost 4 vsldoi8 <4,5,6,4>, <3,0,1,2> + 3383118648U, // <6,4,3,1>: Cost 4 vmrglw <4,5,6,3>, <3,u,4,1> + 4180470119U, // <6,4,3,2>: Cost 4 vsldoi8 <3,2,6,4>, <3,2,6,4> + 4188432796U, // <6,4,3,3>: Cost 4 vsldoi8 <4,5,6,4>, <3,3,3,3> + 4188432898U, // <6,4,3,4>: Cost 3 vsldoi8 <4,5,6,4>, <3,4,5,6> + 3259387190U, // <6,4,3,5>: Cost 3 vmrghw <6,3,4,5>, RHS + 4187105948U, // <6,4,3,6>: Cost 4 vsldoi8 <4,3,6,4>, <3,6,4,7> + 4204358362U, // <6,4,3,7>: Cost 4 vsldoi8 <7,2,6,4>, <3,7,2,6> + 3259387433U, // <6,4,3,u>: Cost 3 vmrghw <6,3,4,5>, RHS + 4190423954U, // <6,4,4,0>: Cost 4 vsldoi8 <4,u,6,4>, <4,0,5,1> + 3383126840U, // <6,4,4,1>: Cost 4 vmrglw <4,5,6,4>, <3,u,4,1> + 3260271670U, // <6,4,4,2>: Cost 4 vmrghw <6,4,7,5>, <4,2,5,3> + 4187106449U, // <6,4,4,3>: Cost 4 vsldoi8 <4,3,6,4>, <4,3,6,4> + 3260263632U, // <6,4,4,4>: Cost 3 vmrghw <6,4,7,4>, <4,4,4,4> + 3248188635U, // <6,4,4,5>: Cost 3 vsldoi12 <4,4,5,6>, <4,4,5,6> + 3383128789U, // <6,4,4,6>: Cost 4 vmrglw <4,5,6,4>, <6,5,4,6> + 3381799580U, // <6,4,4,7>: Cost 4 vmrglw <4,3,6,4>, <3,6,4,7> + 3248409846U, // <6,4,4,u>: Cost 3 vsldoi12 <4,4,u,6>, <4,4,u,6> + 4060708966U, // <6,4,5,0>: Cost 3 vsldoi4 <5,6,4,5>, LHS + 4036822248U, // <6,4,5,1>: Cost 4 vsldoi4 <1,6,4,5>, <1,6,4,5> + 4036822970U, // <6,4,5,2>: Cost 4 vsldoi4 <1,6,4,5>, <2,6,3,7> + 4060711426U, // <6,4,5,3>: Cost 3 vsldoi4 <5,6,4,5>, <3,4,5,6> + 4060712246U, // <6,4,5,4>: Cost 3 vsldoi4 <5,6,4,5>, RHS + 4060713036U, // <6,4,5,5>: Cost 3 vsldoi4 <5,6,4,5>, <5,6,4,5> + 3242216758U, // <6,4,5,6>: Cost 2 vsldoi12 <3,4,5,6>, RHS + 4060713978U, // <6,4,5,7>: Cost 4 vsldoi4 <5,6,4,5>, <7,0,1,2> + 3242216776U, // <6,4,5,u>: Cost 2 vsldoi12 <3,4,5,6>, RHS + 3261533074U, // <6,4,6,0>: Cost 3 vmrghw <6,6,6,6>, <4,0,5,1> + 3389115192U, // <6,4,6,1>: Cost 4 vmrglw <5,5,6,6>, <3,u,4,1> + 4188434911U, // <6,4,6,2>: Cost 4 vsldoi8 <4,5,6,4>, <6,2,4,3> + 4188434994U, // <6,4,6,3>: Cost 4 vsldoi8 <4,5,6,4>, <6,3,4,5> + 3261533392U, // <6,4,6,4>: Cost 3 vmrghw <6,6,6,6>, <4,4,4,4> + 2187791670U, // <6,4,6,5>: Cost 2 vmrghw <6,6,6,6>, RHS + 3261533565U, // <6,4,6,6>: Cost 3 vmrghw <6,6,6,6>, <4,6,5,6> + 4190425934U, // <6,4,6,7>: Cost 4 vsldoi8 <4,u,6,4>, <6,7,0,1> + 2187791913U, // <6,4,6,u>: Cost 2 vmrghw <6,6,6,6>, RHS + 4048781414U, // <6,4,7,0>: Cost 3 vsldoi4 <3,6,4,7>, LHS + 4048782234U, // <6,4,7,1>: Cost 3 vsldoi4 <3,6,4,7>, <1,2,3,4> + 4042811331U, // <6,4,7,2>: Cost 4 vsldoi4 <2,6,4,7>, <2,6,4,7> + 4048784028U, // <6,4,7,3>: Cost 3 vsldoi4 <3,6,4,7>, <3,6,4,7> + 2311400656U, // <6,4,7,4>: Cost 2 vmrglw RHS, <4,4,4,4> + 2309408462U, // <6,4,7,5>: Cost 2 vmrglw RHS, <2,3,4,5> + 4048786073U, // <6,4,7,6>: Cost 4 vsldoi4 <3,6,4,7>, <6,4,7,0> + 3383151260U, // <6,4,7,7>: Cost 3 vmrglw RHS, <3,6,4,7> + 2309408465U, // <6,4,7,u>: Cost 2 vmrglw RHS, <2,3,4,u> + 4048789606U, // <6,4,u,0>: Cost 3 vsldoi4 <3,6,4,u>, LHS + 4048790426U, // <6,4,u,1>: Cost 3 vsldoi4 <3,6,4,u>, <1,2,3,4> + 4036847546U, // <6,4,u,2>: Cost 4 vsldoi4 <1,6,4,u>, <2,6,3,7> + 4048792221U, // <6,4,u,3>: Cost 3 vsldoi4 <3,6,4,u>, <3,6,4,u> + 2309418192U, // <6,4,u,4>: Cost 2 vmrglw RHS, <4,4,4,4> + 2309416654U, // <6,4,u,5>: Cost 2 vmrglw RHS, <2,3,4,5> + 3242217001U, // <6,4,u,6>: Cost 2 vsldoi12 <3,4,5,6>, RHS + 3383159452U, // <6,4,u,7>: Cost 3 vmrglw RHS, <3,6,4,7> + 3242217019U, // <6,4,u,u>: Cost 2 vsldoi12 <3,4,5,6>, RHS + 4178485248U, // <6,5,0,0>: Cost 4 vsldoi8 <2,u,6,5>, <0,0,0,0> + 4178485350U, // <6,5,0,1>: Cost 3 vsldoi8 <2,u,6,5>, LHS + 4178485425U, // <6,5,0,2>: Cost 4 vsldoi8 <2,u,6,5>, <0,2,1,6> + 4054772226U, // <6,5,0,3>: Cost 4 vsldoi4 <4,6,5,0>, <3,4,5,6> + 4178485586U, // <6,5,0,4>: Cost 4 vsldoi8 <2,u,6,5>, <0,4,1,5> + 3385085146U, // <6,5,0,5>: Cost 4 vmrglw <4,u,6,0>, <4,4,5,5> + 3383093762U, // <6,5,0,6>: Cost 3 vmrglw <4,5,6,0>, <3,4,5,6> + 3376459134U, // <6,5,0,7>: Cost 5 vmrglw <3,4,6,0>, <4,6,5,7> + 4178485917U, // <6,5,0,u>: Cost 3 vsldoi8 <2,u,6,5>, LHS + 4054777866U, // <6,5,1,0>: Cost 4 vsldoi4 <4,6,5,1>, <0,0,1,1> + 4178486068U, // <6,5,1,1>: Cost 4 vsldoi8 <2,u,6,5>, <1,1,1,1> + 4178486166U, // <6,5,1,2>: Cost 4 vsldoi8 <2,u,6,5>, <1,2,3,0> + 3242217133U, // <6,5,1,3>: Cost 4 vsldoi12 <3,4,5,6>, <5,1,3,4> + 4054781304U, // <6,5,1,4>: Cost 4 vsldoi4 <4,6,5,1>, <4,6,5,1> + 3252170433U, // <6,5,1,5>: Cost 4 vsldoi12 <5,1,5,6>, <5,1,5,6> + 3230273221U, // <6,5,1,6>: Cost 4 vsldoi12 <1,4,5,6>, <5,1,6,1> + 3266105041U, // <6,5,1,7>: Cost 4 vsldoi12 <7,4,5,6>, <5,1,7,4> + 4172514716U, // <6,5,1,u>: Cost 4 vsldoi8 <1,u,6,5>, <1,u,6,5> + 4054786150U, // <6,5,2,0>: Cost 3 vsldoi4 <4,6,5,2>, LHS + 4054786868U, // <6,5,2,1>: Cost 4 vsldoi4 <4,6,5,2>, <1,1,1,1> + 4178486888U, // <6,5,2,2>: Cost 4 vsldoi8 <2,u,6,5>, <2,2,2,2> + 4178486950U, // <6,5,2,3>: Cost 4 vsldoi8 <2,u,6,5>, <2,3,0,1> + 4054789497U, // <6,5,2,4>: Cost 3 vsldoi4 <4,6,5,2>, <4,6,5,2> + 3258929156U, // <6,5,2,5>: Cost 3 vmrghw <6,2,7,3>, <5,5,5,5> + 4178487226U, // <6,5,2,6>: Cost 3 vsldoi8 <2,u,6,5>, <2,6,3,7> + 4054791162U, // <6,5,2,7>: Cost 4 vsldoi4 <4,6,5,2>, <7,0,1,2> + 4178487413U, // <6,5,2,u>: Cost 3 vsldoi8 <2,u,6,5>, <2,u,6,5> + 4178487446U, // <6,5,3,0>: Cost 4 vsldoi8 <2,u,6,5>, <3,0,1,2> + 4179814679U, // <6,5,3,1>: Cost 4 vsldoi8 <3,1,6,5>, <3,1,6,5> + 4178487654U, // <6,5,3,2>: Cost 4 vsldoi8 <2,u,6,5>, <3,2,6,3> + 4178487708U, // <6,5,3,3>: Cost 4 vsldoi8 <2,u,6,5>, <3,3,3,3> + 4178487810U, // <6,5,3,4>: Cost 4 vsldoi8 <2,u,6,5>, <3,4,5,6> + 3385109722U, // <6,5,3,5>: Cost 4 vmrglw <4,u,6,3>, <4,4,5,5> + 3383118338U, // <6,5,3,6>: Cost 3 vmrglw <4,5,6,3>, <3,4,5,6> + 4178488003U, // <6,5,3,7>: Cost 4 vsldoi8 <2,u,6,5>, <3,7,0,1> + 3383118338U, // <6,5,3,u>: Cost 3 vmrglw <4,5,6,3>, <3,4,5,6> + 4054802534U, // <6,5,4,0>: Cost 4 vsldoi4 <4,6,5,4>, LHS + 3385117586U, // <6,5,4,1>: Cost 4 vmrglw <4,u,6,4>, <4,0,5,1> + 3260133144U, // <6,5,4,2>: Cost 4 vmrghw <6,4,5,6>, <5,2,6,3> + 4054804994U, // <6,5,4,3>: Cost 4 vsldoi4 <4,6,5,4>, <3,4,5,6> + 4054805883U, // <6,5,4,4>: Cost 4 vsldoi4 <4,6,5,4>, <4,6,5,4> + 4178488630U, // <6,5,4,5>: Cost 3 vsldoi8 <2,u,6,5>, RHS + 3383126530U, // <6,5,4,6>: Cost 3 vmrglw <4,5,6,4>, <3,4,5,6> + 3266105284U, // <6,5,4,7>: Cost 4 vsldoi12 <7,4,5,6>, <5,4,7,4> + 4178488873U, // <6,5,4,u>: Cost 3 vsldoi8 <2,u,6,5>, RHS + 4054810726U, // <6,5,5,0>: Cost 4 vsldoi4 <4,6,5,5>, LHS + 4191760073U, // <6,5,5,1>: Cost 4 vsldoi8 <5,1,6,5>, <5,1,6,5> + 4188442392U, // <6,5,5,2>: Cost 4 vsldoi8 <4,5,6,5>, <5,2,6,3> + 3373183950U, // <6,5,5,3>: Cost 4 vmrglw <2,u,6,5>, <6,u,5,3> + 4193750972U, // <6,5,5,4>: Cost 3 vsldoi8 <5,4,6,5>, <5,4,6,5> + 3261534212U, // <6,5,5,5>: Cost 3 vsldoi12 <6,6,6,6>, <5,5,5,5> + 3242217486U, // <6,5,5,6>: Cost 3 vsldoi12 <3,4,5,6>, <5,5,6,6> + 3373183549U, // <6,5,5,7>: Cost 4 vmrglw <2,u,6,5>, <6,3,5,7> + 4196405504U, // <6,5,5,u>: Cost 3 vsldoi8 <5,u,6,5>, <5,u,6,5> + 3242217508U, // <6,5,6,0>: Cost 3 vsldoi12 <3,4,5,6>, <5,6,0,1> + 3395750802U, // <6,5,6,1>: Cost 3 vmrglw <6,6,6,6>, <4,0,5,1> + 3236245559U, // <6,5,6,2>: Cost 4 vsldoi12 <2,4,5,6>, <5,6,2,2> + 3242217538U, // <6,5,6,3>: Cost 3 vsldoi12 <3,4,5,6>, <5,6,3,4> + 3242217548U, // <6,5,6,4>: Cost 3 vsldoi12 <3,4,5,6>, <5,6,4,5> + 3261534212U, // <6,5,6,5>: Cost 3 vmrghw <6,6,6,6>, <5,5,5,5> + 3242217568U, // <6,5,6,6>: Cost 3 vsldoi12 <3,4,5,6>, <5,6,6,7> + 3255636072U, // <6,5,6,7>: Cost 3 vsldoi12 <5,6,7,6>, <5,6,7,6> + 3242217580U, // <6,5,6,u>: Cost 3 vsldoi12 <3,4,5,6>, <5,6,u,1> + 4036911206U, // <6,5,7,0>: Cost 3 vsldoi4 <1,6,5,7>, LHS + 2309409682U, // <6,5,7,1>: Cost 2 vmrglw RHS, <4,0,5,1> + 3383151102U, // <6,5,7,2>: Cost 3 vmrglw RHS, <3,4,5,2> + 3383149483U, // <6,5,7,3>: Cost 3 vmrglw RHS, <1,2,5,3> + 4036914486U, // <6,5,7,4>: Cost 3 vsldoi4 <1,6,5,7>, RHS + 2309410010U, // <6,5,7,5>: Cost 2 vmrglw RHS, <4,4,5,5> + 2309409282U, // <6,5,7,6>: Cost 2 vmrglw RHS, <3,4,5,6> + 3383149811U, // <6,5,7,7>: Cost 3 vmrglw RHS, <1,6,5,7> + 2309409284U, // <6,5,7,u>: Cost 2 vmrglw RHS, <3,4,5,u> + 4036919398U, // <6,5,u,0>: Cost 3 vsldoi4 <1,6,5,u>, LHS + 2309417874U, // <6,5,u,1>: Cost 2 vmrglw RHS, <4,0,5,1> + 3383159294U, // <6,5,u,2>: Cost 3 vmrglw RHS, <3,4,5,2> + 3383157675U, // <6,5,u,3>: Cost 3 vmrglw RHS, <1,2,5,3> + 4036922678U, // <6,5,u,4>: Cost 3 vsldoi4 <1,6,5,u>, RHS + 2309418202U, // <6,5,u,5>: Cost 2 vmrglw RHS, <4,4,5,5> + 2309417474U, // <6,5,u,6>: Cost 2 vmrglw RHS, <3,4,5,6> + 3383158003U, // <6,5,u,7>: Cost 3 vmrglw RHS, <1,6,5,7> + 2309417476U, // <6,5,u,u>: Cost 2 vmrglw RHS, <3,4,5,u> + 3383094575U, // <6,6,0,0>: Cost 3 vmrglw <4,5,6,0>, <4,5,6,0> + 3127312486U, // <6,6,0,1>: Cost 2 vsldoi8 <6,6,6,6>, LHS + 3257217530U, // <6,6,0,2>: Cost 3 vmrghw <6,0,2,1>, <6,2,7,3> + 3242217778U, // <6,6,0,3>: Cost 4 vsldoi12 <3,4,5,6>, <6,0,3,1> + 4201054546U, // <6,6,0,4>: Cost 3 vsldoi8 <6,6,6,6>, <0,4,1,5> + 4060819545U, // <6,6,0,5>: Cost 4 vsldoi4 <5,6,6,0>, <5,6,6,0> + 3261534541U, // <6,6,0,6>: Cost 3 vsldoi12 <6,6,6,6>, <6,0,6,1> + 3383094582U, // <6,6,0,7>: Cost 3 vmrglw <4,5,6,0>, RHS + 3127313053U, // <6,6,0,u>: Cost 2 vsldoi8 <6,6,6,6>, LHS + 3258249504U, // <6,6,1,0>: Cost 4 vmrghw <6,1,7,1>, <6,0,1,1> + 3373148273U, // <6,6,1,1>: Cost 3 vmrglw <2,u,6,1>, <2,u,6,1> + 4201055126U, // <6,6,1,2>: Cost 3 vsldoi8 <6,6,6,6>, <1,2,3,0> + 3373148518U, // <6,6,1,3>: Cost 4 vmrglw <2,u,6,1>, <3,2,6,3> + 3230273936U, // <6,6,1,4>: Cost 4 vsldoi12 <1,4,5,6>, <6,1,4,5> + 3373147953U, // <6,6,1,5>: Cost 4 vmrglw <2,u,6,1>, <2,4,6,5> + 3397038904U, // <6,6,1,6>: Cost 3 vmrglw <6,u,6,1>, <6,6,6,6> + 3373149494U, // <6,6,1,7>: Cost 3 vmrglw <2,u,6,1>, RHS + 3373149495U, // <6,6,1,u>: Cost 3 vmrglw <2,u,6,1>, RHS + 3258929449U, // <6,6,2,0>: Cost 3 vmrghw <6,2,7,3>, <6,0,2,1> + 3258929530U, // <6,6,2,1>: Cost 4 vmrghw <6,2,7,3>, <6,1,2,1> + 2185187834U, // <6,6,2,2>: Cost 2 vmrghw <6,2,7,3>, <6,2,7,3> + 4201055910U, // <6,6,2,3>: Cost 3 vsldoi8 <6,6,6,6>, <2,3,0,1> + 3258929777U, // <6,6,2,4>: Cost 3 vmrghw <6,2,7,3>, <6,4,2,5> + 3236762088U, // <6,6,2,5>: Cost 4 vsldoi12 <2,5,3,6>, <6,2,5,3> + 3258929936U, // <6,6,2,6>: Cost 3 vmrghw <6,2,7,3>, <6,6,2,2> + 3255636474U, // <6,6,2,7>: Cost 3 vsldoi12 <5,6,7,6>, <6,2,7,3> + 2185187834U, // <6,6,2,u>: Cost 2 vmrghw <6,2,7,3>, <6,2,7,3> + 4201056406U, // <6,6,3,0>: Cost 3 vsldoi8 <6,6,6,6>, <3,0,1,2> + 3375154665U, // <6,6,3,1>: Cost 4 vmrglw <3,2,6,3>, <2,0,6,1> + 3375154909U, // <6,6,3,2>: Cost 4 vmrglw <3,2,6,3>, <2,3,6,2> + 3375155558U, // <6,6,3,3>: Cost 3 vmrglw <3,2,6,3>, <3,2,6,3> + 3242218034U, // <6,6,3,4>: Cost 3 vsldoi12 <3,4,5,6>, <6,3,4,5> + 3375154993U, // <6,6,3,5>: Cost 4 vmrglw <3,2,6,3>, <2,4,6,5> + 3397055288U, // <6,6,3,6>: Cost 3 vmrglw <6,u,6,3>, <6,6,6,6> + 3375156534U, // <6,6,3,7>: Cost 3 vmrglw <3,2,6,3>, RHS + 3375156535U, // <6,6,3,u>: Cost 3 vmrglw <3,2,6,3>, RHS + 4201057170U, // <6,6,4,0>: Cost 3 vsldoi8 <6,6,6,6>, <4,0,5,1> + 3259830695U, // <6,6,4,1>: Cost 4 vmrghw <6,4,1,5>, <6,1,7,1> + 3259904506U, // <6,6,4,2>: Cost 3 vmrghw <6,4,2,5>, <6,2,7,3> + 3383127346U, // <6,6,4,3>: Cost 4 vmrglw <4,5,6,4>, <4,5,6,3> + 3383127347U, // <6,6,4,4>: Cost 3 vmrglw <4,5,6,4>, <4,5,6,4> + 3127315766U, // <6,6,4,5>: Cost 2 vsldoi8 <6,6,6,6>, RHS + 4201057661U, // <6,6,4,6>: Cost 3 vsldoi8 <6,6,6,6>, <4,6,5,6> + 3383127350U, // <6,6,4,7>: Cost 3 vmrglw <4,5,6,4>, RHS + 3127316009U, // <6,6,4,u>: Cost 2 vsldoi8 <6,6,6,6>, RHS + 4060856422U, // <6,6,5,0>: Cost 4 vsldoi4 <5,6,6,5>, LHS + 3373180393U, // <6,6,5,1>: Cost 4 vmrglw <2,u,6,5>, <2,0,6,1> + 4194422552U, // <6,6,5,2>: Cost 4 vsldoi8 <5,5,6,6>, <5,2,6,3> + 3373181286U, // <6,6,5,3>: Cost 4 vmrglw <2,u,6,5>, <3,2,6,3> + 4060859702U, // <6,6,5,4>: Cost 4 vsldoi4 <5,6,6,5>, RHS + 3373181045U, // <6,6,5,5>: Cost 3 vmrglw <2,u,6,5>, <2,u,6,5> + 4201058402U, // <6,6,5,6>: Cost 3 vsldoi8 <6,6,6,6>, <5,6,7,0> + 3373182262U, // <6,6,5,7>: Cost 3 vmrglw <2,u,6,5>, RHS + 3373182263U, // <6,6,5,u>: Cost 3 vmrglw <2,u,6,5>, RHS + 2993094758U, // <6,6,6,0>: Cost 2 vsldoi4 <6,6,6,6>, LHS + 3395752269U, // <6,6,6,1>: Cost 3 vmrglw <6,6,6,6>, <6,0,6,1> + 3261207034U, // <6,6,6,2>: Cost 3 vmrghw <6,6,2,2>, <6,2,7,3> + 3395752433U, // <6,6,6,3>: Cost 3 vmrglw <6,6,6,6>, <6,2,6,3> + 2993098038U, // <6,6,6,4>: Cost 2 vsldoi4 <6,6,6,6>, RHS + 3395752597U, // <6,6,6,5>: Cost 3 vmrglw <6,6,6,6>, <6,4,6,5> + 1638321462U, // <6,6,6,6>: Cost 1 vspltisw2 RHS + 2322009398U, // <6,6,6,7>: Cost 2 vmrglw <6,6,6,6>, RHS + 1638321462U, // <6,6,6,u>: Cost 1 vspltisw2 RHS + 3383151919U, // <6,6,7,0>: Cost 3 vmrglw RHS, <4,5,6,0> + 3383150057U, // <6,6,7,1>: Cost 3 vmrglw RHS, <2,0,6,1> + 3385144197U, // <6,6,7,2>: Cost 3 vmrglw RHS, <6,7,6,2> + 3383150950U, // <6,6,7,3>: Cost 3 vmrglw RHS, <3,2,6,3> + 3383151923U, // <6,6,7,4>: Cost 3 vmrglw RHS, <4,5,6,4> + 3383150385U, // <6,6,7,5>: Cost 3 vmrglw RHS, <2,4,6,5> + 2311402296U, // <6,6,7,6>: Cost 2 vmrglw RHS, <6,6,6,6> + 1235668278U, // <6,6,7,7>: Cost 1 vmrglw RHS, RHS + 1235668279U, // <6,6,7,u>: Cost 1 vmrglw RHS, RHS + 2993094758U, // <6,6,u,0>: Cost 2 vsldoi4 <6,6,6,6>, LHS + 3127318318U, // <6,6,u,1>: Cost 2 vsldoi8 <6,6,6,6>, LHS + 2185187834U, // <6,6,u,2>: Cost 2 vmrghw <6,2,7,3>, <6,2,7,3> + 3383159142U, // <6,6,u,3>: Cost 3 vmrglw RHS, <3,2,6,3> + 2993098038U, // <6,6,u,4>: Cost 2 vsldoi4 <6,6,6,6>, RHS + 3127318682U, // <6,6,u,5>: Cost 2 vsldoi8 <6,6,6,6>, RHS + 1638321462U, // <6,6,u,6>: Cost 1 vspltisw2 RHS + 1235676470U, // <6,6,u,7>: Cost 1 vmrglw RHS, RHS + 1235676471U, // <6,6,u,u>: Cost 1 vmrglw RHS, RHS + 3114713088U, // <6,7,0,0>: Cost 2 vsldoi8 RHS, <0,0,0,0> + 2040971366U, // <6,7,0,1>: Cost 1 vsldoi8 RHS, LHS + 4188455085U, // <6,7,0,2>: Cost 3 vsldoi8 RHS, <0,2,1,2> + 4188455164U, // <6,7,0,3>: Cost 3 vsldoi8 RHS, <0,3,1,0> + 3114713426U, // <6,7,0,4>: Cost 2 vsldoi8 RHS, <0,4,1,5> + 2987151458U, // <6,7,0,5>: Cost 2 vsldoi4 <5,6,7,0>, <5,6,7,0> + 4188455414U, // <6,7,0,6>: Cost 3 vsldoi8 RHS, <0,6,1,7> + 4060894202U, // <6,7,0,7>: Cost 3 vsldoi4 <5,6,7,0>, <7,0,1,2> + 2040971933U, // <6,7,0,u>: Cost 1 vsldoi8 RHS, LHS + 4188455651U, // <6,7,1,0>: Cost 3 vsldoi8 RHS, <1,0,1,1> + 3114713908U, // <6,7,1,1>: Cost 2 vsldoi8 RHS, <1,1,1,1> + 3114714006U, // <6,7,1,2>: Cost 2 vsldoi8 RHS, <1,2,3,0> + 4169212937U, // <6,7,1,3>: Cost 4 vsldoi8 <1,3,6,7>, <1,3,6,7> + 4188455979U, // <6,7,1,4>: Cost 3 vsldoi8 RHS, <1,4,1,5> + 4188456047U, // <6,7,1,5>: Cost 3 vsldoi8 RHS, <1,5,0,1> + 4188456143U, // <6,7,1,6>: Cost 3 vsldoi8 RHS, <1,6,1,7> + 3373148612U, // <6,7,1,7>: Cost 4 vmrglw <2,u,6,1>, <3,3,7,7> + 3114714492U, // <6,7,1,u>: Cost 2 vsldoi8 RHS, <1,u,3,0> + 4188456381U, // <6,7,2,0>: Cost 3 vsldoi8 RHS, <2,0,1,2> + 4188456479U, // <6,7,2,1>: Cost 3 vsldoi8 RHS, <2,1,3,1> + 3114714728U, // <6,7,2,2>: Cost 2 vsldoi8 RHS, <2,2,2,2> + 3114714790U, // <6,7,2,3>: Cost 2 vsldoi8 RHS, <2,3,0,1> + 4188456717U, // <6,7,2,4>: Cost 3 vsldoi8 RHS, <2,4,2,5> + 4188456808U, // <6,7,2,5>: Cost 3 vsldoi8 RHS, <2,5,3,6> + 3114715066U, // <6,7,2,6>: Cost 2 vsldoi8 RHS, <2,6,3,7> + 3258930796U, // <6,7,2,7>: Cost 3 vmrghw <6,2,7,3>, <7,7,7,7> + 3114715195U, // <6,7,2,u>: Cost 2 vsldoi8 RHS, <2,u,0,1> + 3114715286U, // <6,7,3,0>: Cost 2 vsldoi8 RHS, <3,0,1,2> + 4188457190U, // <6,7,3,1>: Cost 3 vsldoi8 RHS, <3,1,1,1> + 4188457264U, // <6,7,3,2>: Cost 3 vsldoi8 RHS, <3,2,0,3> + 3114715548U, // <6,7,3,3>: Cost 2 vsldoi8 RHS, <3,3,3,3> + 3114715650U, // <6,7,3,4>: Cost 2 vsldoi8 RHS, <3,4,5,6> + 4188457554U, // <6,7,3,5>: Cost 3 vsldoi8 RHS, <3,5,5,5> + 4188457592U, // <6,7,3,6>: Cost 3 vsldoi8 RHS, <3,6,0,7> + 4188457667U, // <6,7,3,7>: Cost 3 vsldoi8 RHS, <3,7,0,1> + 3114715934U, // <6,7,3,u>: Cost 2 vsldoi8 RHS, <3,u,1,2> + 3114716050U, // <6,7,4,0>: Cost 2 vsldoi8 RHS, <4,0,5,1> + 4188457930U, // <6,7,4,1>: Cost 3 vsldoi8 RHS, <4,1,2,3> + 4188458037U, // <6,7,4,2>: Cost 3 vsldoi8 RHS, <4,2,5,2> + 4188458116U, // <6,7,4,3>: Cost 3 vsldoi8 RHS, <4,3,5,0> + 3114716368U, // <6,7,4,4>: Cost 2 vsldoi8 RHS, <4,4,4,4> + 2040974646U, // <6,7,4,5>: Cost 1 vsldoi8 RHS, RHS + 4188458365U, // <6,7,4,6>: Cost 3 vsldoi8 RHS, <4,6,5,6> + 4188458447U, // <6,7,4,7>: Cost 3 vsldoi8 RHS, <4,7,5,7> + 2040974889U, // <6,7,4,u>: Cost 1 vsldoi8 RHS, RHS + 4188458568U, // <6,7,5,0>: Cost 3 vsldoi8 RHS, <5,0,1,2> + 4190449295U, // <6,7,5,1>: Cost 3 vsldoi8 RHS, <5,1,0,1> + 4188458750U, // <6,7,5,2>: Cost 3 vsldoi8 RHS, <5,2,3,4> + 3373181295U, // <6,7,5,3>: Cost 4 vmrglw <2,u,6,5>, <3,2,7,3> + 4188458932U, // <6,7,5,4>: Cost 3 vsldoi8 RHS, <5,4,5,6> + 3114717188U, // <6,7,5,5>: Cost 2 vsldoi8 RHS, <5,5,5,5> + 3114717282U, // <6,7,5,6>: Cost 2 vsldoi8 RHS, <5,6,7,0> + 3373181380U, // <6,7,5,7>: Cost 4 vmrglw <2,u,6,5>, <3,3,7,7> + 3116708100U, // <6,7,5,u>: Cost 2 vsldoi8 RHS, <5,u,7,0> + 4188459297U, // <6,7,6,0>: Cost 3 vsldoi8 RHS, <6,0,1,2> + 4188459431U, // <6,7,6,1>: Cost 3 vsldoi8 RHS, <6,1,7,1> + 3114717690U, // <6,7,6,2>: Cost 2 vsldoi8 RHS, <6,2,7,3> + 4188459570U, // <6,7,6,3>: Cost 3 vsldoi8 RHS, <6,3,4,5> + 4188459661U, // <6,7,6,4>: Cost 3 vsldoi8 RHS, <6,4,5,6> + 4188459755U, // <6,7,6,5>: Cost 3 vsldoi8 RHS, <6,5,7,1> + 3114718008U, // <6,7,6,6>: Cost 2 vsldoi8 RHS, <6,6,6,6> + 3114718030U, // <6,7,6,7>: Cost 2 vsldoi8 RHS, <6,7,0,1> + 3114718176U, // <6,7,6,u>: Cost 2 vsldoi8 RHS, <6,u,7,3> + 2311401570U, // <6,7,7,0>: Cost 2 vmrglw RHS, <5,6,7,0> + 3383152982U, // <6,7,7,1>: Cost 3 vmrglw RHS, <6,0,7,1> + 4049004474U, // <6,7,7,2>: Cost 3 vsldoi4 <3,6,7,7>, <2,6,3,7> + 2309411322U, // <6,7,7,3>: Cost 2 vmrglw RHS, <6,2,7,3> + 2311401574U, // <6,7,7,4>: Cost 2 vmrglw RHS, <5,6,7,4> + 3383153067U, // <6,7,7,5>: Cost 3 vmrglw RHS, <6,1,7,5> + 2993181506U, // <6,7,7,6>: Cost 2 vsldoi4 <6,6,7,7>, <6,6,7,7> + 2309411650U, // <6,7,7,7>: Cost 2 vmrglw RHS, <6,6,7,7> + 2309411327U, // <6,7,7,u>: Cost 2 vmrglw RHS, <6,2,7,u> + 3114718931U, // <6,7,u,0>: Cost 2 vsldoi8 RHS, + 2040977198U, // <6,7,u,1>: Cost 1 vsldoi8 RHS, LHS + 3114719109U, // <6,7,u,2>: Cost 2 vsldoi8 RHS, + 3114719164U, // <6,7,u,3>: Cost 2 vsldoi8 RHS, + 3114719295U, // <6,7,u,4>: Cost 2 vsldoi8 RHS, + 2040977562U, // <6,7,u,5>: Cost 1 vsldoi8 RHS, RHS + 3114719440U, // <6,7,u,6>: Cost 2 vsldoi8 RHS, + 2309419842U, // <6,7,u,7>: Cost 2 vmrglw RHS, <6,6,7,7> + 2040977765U, // <6,7,u,u>: Cost 1 vsldoi8 RHS, LHS + 3114721280U, // <6,u,0,0>: Cost 2 vsldoi8 RHS, <0,0,0,0> + 2040979558U, // <6,u,0,1>: Cost 1 vsldoi8 RHS, LHS + 4188463277U, // <6,u,0,2>: Cost 3 vsldoi8 RHS, <0,2,1,2> + 3383091356U, // <6,u,0,3>: Cost 3 vmrglw <4,5,6,0>, LHS + 3114721618U, // <6,u,0,4>: Cost 2 vsldoi8 RHS, <0,4,1,5> + 2987225195U, // <6,u,0,5>: Cost 2 vsldoi4 <5,6,u,0>, <5,6,u,0> + 4188463606U, // <6,u,0,6>: Cost 3 vsldoi8 RHS, <0,6,1,7> + 3383094600U, // <6,u,0,7>: Cost 3 vmrglw <4,5,6,0>, RHS + 2040980125U, // <6,u,0,u>: Cost 1 vsldoi8 RHS, LHS + 4188463843U, // <6,u,1,0>: Cost 3 vsldoi8 RHS, <1,0,1,1> + 3114722100U, // <6,u,1,1>: Cost 2 vsldoi8 RHS, <1,1,1,1> + 3242219310U, // <6,u,1,2>: Cost 2 vsldoi12 <3,4,5,6>, LHS + 3373146268U, // <6,u,1,3>: Cost 3 vmrglw <2,u,6,1>, LHS + 4188464171U, // <6,u,1,4>: Cost 3 vsldoi8 RHS, <1,4,1,5> + 4188464239U, // <6,u,1,5>: Cost 3 vsldoi8 RHS, <1,5,0,1> + 4188464335U, // <6,u,1,6>: Cost 3 vsldoi8 RHS, <1,6,1,7> + 3373149512U, // <6,u,1,7>: Cost 3 vmrglw <2,u,6,1>, RHS + 3242219364U, // <6,u,1,u>: Cost 2 vsldoi12 <3,4,5,6>, LHS + 4188464573U, // <6,u,2,0>: Cost 3 vsldoi8 RHS, <2,0,1,2> + 2185189166U, // <6,u,2,1>: Cost 2 vmrghw <6,2,7,3>, LHS + 3114722920U, // <6,u,2,2>: Cost 2 vsldoi8 RHS, <2,2,2,2> + 3114722982U, // <6,u,2,3>: Cost 2 vsldoi8 RHS, <2,3,0,1> + 4188464909U, // <6,u,2,4>: Cost 3 vsldoi8 RHS, <2,4,2,5> + 2185189530U, // <6,u,2,5>: Cost 2 vmrghw <6,2,7,3>, RHS + 3114723258U, // <6,u,2,6>: Cost 2 vsldoi8 RHS, <2,6,3,7> + 3258931456U, // <6,u,2,7>: Cost 3 vmrghw <6,2,7,3>, + 3114723387U, // <6,u,2,u>: Cost 2 vsldoi8 RHS, <2,u,0,1> + 3114723478U, // <6,u,3,0>: Cost 2 vsldoi8 RHS, <3,0,1,2> + 4188465382U, // <6,u,3,1>: Cost 3 vsldoi8 RHS, <3,1,1,1> + 4180502891U, // <6,u,3,2>: Cost 3 vsldoi8 <3,2,6,u>, <3,2,6,u> + 3114723740U, // <6,u,3,3>: Cost 2 vsldoi8 RHS, <3,3,3,3> + 3114723842U, // <6,u,3,4>: Cost 2 vsldoi8 RHS, <3,4,5,6> + 4188465746U, // <6,u,3,5>: Cost 3 vsldoi8 RHS, <3,5,5,5> + 4188465784U, // <6,u,3,6>: Cost 3 vsldoi8 RHS, <3,6,0,7> + 3375156552U, // <6,u,3,7>: Cost 3 vmrglw <3,2,6,3>, RHS + 3114724126U, // <6,u,3,u>: Cost 2 vsldoi8 RHS, <3,u,1,2> + 3114724242U, // <6,u,4,0>: Cost 2 vsldoi8 RHS, <4,0,5,1> + 4188466122U, // <6,u,4,1>: Cost 3 vsldoi8 RHS, <4,1,2,3> + 4188466229U, // <6,u,4,2>: Cost 3 vsldoi8 RHS, <4,2,5,2> + 3383124124U, // <6,u,4,3>: Cost 3 vmrglw <4,5,6,4>, LHS + 3114724560U, // <6,u,4,4>: Cost 2 vsldoi8 RHS, <4,4,4,4> + 2040982839U, // <6,u,4,5>: Cost 1 vsldoi8 RHS, RHS + 4188466553U, // <6,u,4,6>: Cost 3 vsldoi8 RHS, <4,6,5,2> + 3383127368U, // <6,u,4,7>: Cost 3 vmrglw <4,5,6,4>, RHS + 2040983081U, // <6,u,4,u>: Cost 1 vsldoi8 RHS, RHS + 4188466760U, // <6,u,5,0>: Cost 3 vsldoi8 RHS, <5,0,1,2> + 4190457487U, // <6,u,5,1>: Cost 3 vsldoi8 RHS, <5,1,0,1> + 4188466942U, // <6,u,5,2>: Cost 3 vsldoi8 RHS, <5,2,3,4> + 3373179036U, // <6,u,5,3>: Cost 3 vmrglw <2,u,6,5>, LHS + 4188467124U, // <6,u,5,4>: Cost 3 vsldoi8 RHS, <5,4,5,6> + 3114725380U, // <6,u,5,5>: Cost 2 vsldoi8 RHS, <5,5,5,5> + 3242219674U, // <6,u,5,6>: Cost 2 vsldoi12 <3,4,5,6>, RHS + 3373182280U, // <6,u,5,7>: Cost 3 vmrglw <2,u,6,5>, RHS + 3242219692U, // <6,u,5,u>: Cost 2 vsldoi12 <3,4,5,6>, RHS + 2993094758U, // <6,u,6,0>: Cost 2 vsldoi4 <6,6,6,6>, LHS + 2187794222U, // <6,u,6,1>: Cost 2 vmrghw <6,6,6,6>, LHS + 3114725882U, // <6,u,6,2>: Cost 2 vsldoi8 RHS, <6,2,7,3> + 2322006172U, // <6,u,6,3>: Cost 2 vmrglw <6,6,6,6>, LHS + 2993098038U, // <6,u,6,4>: Cost 2 vsldoi4 <6,6,6,6>, RHS + 2187794586U, // <6,u,6,5>: Cost 2 vmrghw <6,6,6,6>, RHS + 1638321462U, // <6,u,6,6>: Cost 1 vspltisw2 RHS + 3114726222U, // <6,u,6,7>: Cost 2 vsldoi8 RHS, <6,7,0,1> + 1638321462U, // <6,u,6,u>: Cost 1 vspltisw2 RHS + 2969362534U, // <6,u,7,0>: Cost 2 vsldoi4 <2,6,u,7>, LHS + 2309406793U, // <6,u,7,1>: Cost 2 vmrglw RHS, <0,0,u,1> + 2969364455U, // <6,u,7,2>: Cost 2 vsldoi4 <2,6,u,7>, <2,6,u,7> + 1235665052U, // <6,u,7,3>: Cost 1 vmrglw RHS, LHS + 2969365814U, // <6,u,7,4>: Cost 2 vsldoi4 <2,6,u,7>, RHS + 2309407121U, // <6,u,7,5>: Cost 2 vmrglw RHS, <0,4,u,5> + 2309409309U, // <6,u,7,6>: Cost 2 vmrglw RHS, <3,4,u,6> + 1235668296U, // <6,u,7,7>: Cost 1 vmrglw RHS, RHS + 1235665057U, // <6,u,7,u>: Cost 1 vmrglw RHS, LHS + 2969370726U, // <6,u,u,0>: Cost 2 vsldoi4 <2,6,u,u>, LHS + 2040985390U, // <6,u,u,1>: Cost 1 vsldoi8 RHS, LHS + 2969372648U, // <6,u,u,2>: Cost 2 vsldoi4 <2,6,u,u>, <2,6,u,u> + 1235673244U, // <6,u,u,3>: Cost 1 vmrglw RHS, LHS + 2969374006U, // <6,u,u,4>: Cost 2 vsldoi4 <2,6,u,u>, RHS + 2040985754U, // <6,u,u,5>: Cost 1 vsldoi8 RHS, RHS + 1638321462U, // <6,u,u,6>: Cost 1 vspltisw2 RHS + 1235676488U, // <6,u,u,7>: Cost 1 vmrglw RHS, RHS + 1235673249U, // <6,u,u,u>: Cost 1 vmrglw RHS, LHS + 3248930816U, // <7,0,0,0>: Cost 2 vsldoi12 RHS, <0,0,0,0> + 3248930826U, // <7,0,0,1>: Cost 2 vsldoi12 RHS, <0,0,1,1> + 4049094586U, // <7,0,0,2>: Cost 4 vsldoi4 <3,7,0,0>, <2,6,3,7> + 3389805716U, // <7,0,0,3>: Cost 3 vmrglw <5,6,7,0>, <7,2,0,3> + 3248930853U, // <7,0,0,4>: Cost 3 vsldoi12 RHS, <0,0,4,1> + 4072984674U, // <7,0,0,5>: Cost 3 vsldoi4 <7,7,0,0>, <5,6,7,0> + 4067013453U, // <7,0,0,6>: Cost 3 vsldoi4 <6,7,0,0>, <6,7,0,0> + 3389806044U, // <7,0,0,7>: Cost 3 vmrglw <5,6,7,0>, <7,6,0,7> + 3248930889U, // <7,0,0,u>: Cost 2 vsldoi12 RHS, <0,0,u,1> + 2993274982U, // <7,0,1,0>: Cost 2 vsldoi4 <6,7,0,1>, LHS + 3248930907U, // <7,0,1,1>: Cost 3 vsldoi12 RHS, <0,1,1,1> + 1101447270U, // <7,0,1,2>: Cost 1 vsldoi12 RHS, LHS + 4049103555U, // <7,0,1,3>: Cost 3 vsldoi4 <3,7,0,1>, <3,7,0,1> + 2993278262U, // <7,0,1,4>: Cost 2 vsldoi4 <6,7,0,1>, RHS + 4067020804U, // <7,0,1,5>: Cost 3 vsldoi4 <6,7,0,1>, <5,5,5,5> + 2993279822U, // <7,0,1,6>: Cost 2 vsldoi4 <6,7,0,1>, <6,7,0,1> + 4067021816U, // <7,0,1,7>: Cost 3 vsldoi4 <6,7,0,1>, <7,0,1,0> + 1101447324U, // <7,0,1,u>: Cost 1 vsldoi12 RHS, LHS + 3248930981U, // <7,0,2,0>: Cost 3 vsldoi12 RHS, <0,2,0,3> + 3237429425U, // <7,0,2,1>: Cost 3 vsldoi12 <2,6,3,7>, <0,2,1,6> + 4195108456U, // <7,0,2,2>: Cost 3 vsldoi8 <5,6,7,0>, <2,2,2,2> + 4195108518U, // <7,0,2,3>: Cost 3 vsldoi8 <5,6,7,0>, <2,3,0,1> + 3237429452U, // <7,0,2,4>: Cost 4 vsldoi12 <2,6,3,7>, <0,2,4,6> + 3248931026U, // <7,0,2,5>: Cost 4 vsldoi12 RHS, <0,2,5,3> + 4195108794U, // <7,0,2,6>: Cost 3 vsldoi8 <5,6,7,0>, <2,6,3,7> + 3243180260U, // <7,0,2,7>: Cost 4 vsldoi12 <3,6,0,7>, <0,2,7,3> + 3237429488U, // <7,0,2,u>: Cost 3 vsldoi12 <2,6,3,7>, <0,2,u,6> + 4195109014U, // <7,0,3,0>: Cost 3 vsldoi8 <5,6,7,0>, <3,0,1,2> + 3248931068U, // <7,0,3,1>: Cost 3 vsldoi12 RHS, <0,3,1,0> + 3248931077U, // <7,0,3,2>: Cost 4 vsldoi12 RHS, <0,3,2,0> + 4195109276U, // <7,0,3,3>: Cost 3 vsldoi8 <5,6,7,0>, <3,3,3,3> + 4195109378U, // <7,0,3,4>: Cost 3 vsldoi8 <5,6,7,0>, <3,4,5,6> + 4195109469U, // <7,0,3,5>: Cost 3 vsldoi8 <5,6,7,0>, <3,5,6,7> + 4183165616U, // <7,0,3,6>: Cost 3 vsldoi8 <3,6,7,0>, <3,6,7,0> + 3243180338U, // <7,0,3,7>: Cost 4 vsldoi12 <3,6,0,7>, <0,3,7,0> + 3248931131U, // <7,0,3,u>: Cost 3 vsldoi12 RHS, <0,3,u,0> + 4195109778U, // <7,0,4,0>: Cost 3 vsldoi8 <5,6,7,0>, <4,0,5,1> + 3248931154U, // <7,0,4,1>: Cost 2 vsldoi12 RHS, <0,4,1,5> + 4049127354U, // <7,0,4,2>: Cost 4 vsldoi4 <3,7,0,4>, <2,6,3,7> + 4049128134U, // <7,0,4,3>: Cost 4 vsldoi4 <3,7,0,4>, <3,7,0,4> + 3248931181U, // <7,0,4,4>: Cost 3 vsldoi12 RHS, <0,4,4,5> + 3121368374U, // <7,0,4,5>: Cost 2 vsldoi8 <5,6,7,0>, RHS + 4067046225U, // <7,0,4,6>: Cost 3 vsldoi4 <6,7,0,4>, <6,7,0,4> + 3266101828U, // <7,0,4,7>: Cost 3 vmrghw <7,4,5,6>, <0,7,1,4> + 3248931217U, // <7,0,4,u>: Cost 2 vsldoi12 RHS, <0,4,u,5> + 4195110516U, // <7,0,5,0>: Cost 3 vsldoi8 <5,6,7,0>, <5,0,6,1> + 3266756710U, // <7,0,5,1>: Cost 3 vmrghw <7,5,5,5>, LHS + 4195110635U, // <7,0,5,2>: Cost 4 vsldoi8 <5,6,7,0>, <5,2,1,3> + 3248931248U, // <7,0,5,3>: Cost 4 vsldoi12 RHS, <0,5,3,0> + 4195110844U, // <7,0,5,4>: Cost 3 vsldoi8 <5,6,7,0>, <5,4,6,5> + 4195110916U, // <7,0,5,5>: Cost 3 vsldoi8 <5,6,7,0>, <5,5,5,5> + 3121369186U, // <7,0,5,6>: Cost 2 vsldoi8 <5,6,7,0>, <5,6,7,0> + 4195111037U, // <7,0,5,7>: Cost 4 vsldoi8 <5,6,7,0>, <5,7,1,0> + 3122696452U, // <7,0,5,u>: Cost 2 vsldoi8 <5,u,7,0>, <5,u,7,0> + 4197101909U, // <7,0,6,0>: Cost 3 vsldoi8 <6,0,7,0>, <6,0,7,0> + 3248931318U, // <7,0,6,1>: Cost 3 vsldoi12 RHS, <0,6,1,7> + 4195111418U, // <7,0,6,2>: Cost 3 vsldoi8 <5,6,7,0>, <6,2,7,3> + 4199092808U, // <7,0,6,3>: Cost 3 vsldoi8 <6,3,7,0>, <6,3,7,0> + 3248931345U, // <7,0,6,4>: Cost 4 vsldoi12 RHS, <0,6,4,7> + 3248931354U, // <7,0,6,5>: Cost 4 vsldoi12 RHS, <0,6,5,7> + 4195111736U, // <7,0,6,6>: Cost 3 vsldoi8 <5,6,7,0>, <6,6,6,6> + 4195111758U, // <7,0,6,7>: Cost 3 vsldoi8 <5,6,7,0>, <6,7,0,1> + 3248931381U, // <7,0,6,u>: Cost 3 vsldoi12 RHS, <0,6,u,7> + 4195111930U, // <7,0,7,0>: Cost 3 vsldoi8 <5,6,7,0>, <7,0,1,2> + 2194505830U, // <7,0,7,1>: Cost 2 vmrghw <7,7,7,7>, LHS + 4195112084U, // <7,0,7,2>: Cost 3 vsldoi8 <5,6,7,0>, <7,2,0,3> + 3243180632U, // <7,0,7,3>: Cost 4 vsldoi12 <3,6,0,7>, <0,7,3,6> + 4195112294U, // <7,0,7,4>: Cost 3 vsldoi8 <5,6,7,0>, <7,4,5,6> + 4195112385U, // <7,0,7,5>: Cost 3 vsldoi8 <5,6,7,0>, <7,5,6,7> + 4195112412U, // <7,0,7,6>: Cost 3 vsldoi8 <5,6,7,0>, <7,6,0,7> + 4195112486U, // <7,0,7,7>: Cost 3 vsldoi8 <5,6,7,0>, <7,7,0,0> + 2194506397U, // <7,0,7,u>: Cost 2 vmrghw <7,7,7,7>, LHS + 2993332326U, // <7,0,u,0>: Cost 2 vsldoi4 <6,7,0,u>, LHS + 3248931474U, // <7,0,u,1>: Cost 2 vsldoi12 RHS, <0,u,1,1> + 1101447837U, // <7,0,u,2>: Cost 1 vsldoi12 RHS, LHS + 4049160906U, // <7,0,u,3>: Cost 3 vsldoi4 <3,7,0,u>, <3,7,0,u> + 2993335606U, // <7,0,u,4>: Cost 2 vsldoi4 <6,7,0,u>, RHS + 3121371290U, // <7,0,u,5>: Cost 2 vsldoi8 <5,6,7,0>, RHS + 2993337173U, // <7,0,u,6>: Cost 2 vsldoi4 <6,7,0,u>, <6,7,0,u> + 4195113216U, // <7,0,u,7>: Cost 3 vsldoi8 <5,6,7,0>, + 1101447891U, // <7,0,u,u>: Cost 1 vsldoi12 RHS, LHS + 4197769226U, // <7,1,0,0>: Cost 3 vsldoi8 <6,1,7,1>, <0,0,1,1> + 3248931555U, // <7,1,0,1>: Cost 3 vsldoi12 RHS, <1,0,1,1> + 3248931564U, // <7,1,0,2>: Cost 3 vsldoi12 RHS, <1,0,2,1> + 3248931572U, // <7,1,0,3>: Cost 4 vsldoi12 RHS, <1,0,3,0> + 4079029558U, // <7,1,0,4>: Cost 3 vsldoi4 , RHS + 3389800786U, // <7,1,0,5>: Cost 3 vmrglw <5,6,7,0>, <0,4,1,5> + 3389800868U, // <7,1,0,6>: Cost 3 vmrglw <5,6,7,0>, <0,5,1,6> + 4079031290U, // <7,1,0,7>: Cost 3 vsldoi4 , <7,0,1,2> + 3248931618U, // <7,1,0,u>: Cost 3 vsldoi12 RHS, <1,0,u,1> + 3248931627U, // <7,1,1,0>: Cost 3 vsldoi12 RHS, <1,1,0,1> + 3248931636U, // <7,1,1,1>: Cost 2 vsldoi12 RHS, <1,1,1,1> + 3248931646U, // <7,1,1,2>: Cost 3 vsldoi12 RHS, <1,1,2,2> + 4049177292U, // <7,1,1,3>: Cost 4 vsldoi4 <3,7,1,1>, <3,7,1,1> + 3248931667U, // <7,1,1,4>: Cost 3 vsldoi12 RHS, <1,1,4,5> + 3248931676U, // <7,1,1,5>: Cost 3 vsldoi12 RHS, <1,1,5,5> + 4067095383U, // <7,1,1,6>: Cost 3 vsldoi4 <6,7,1,1>, <6,7,1,1> + 3231310698U, // <7,1,1,7>: Cost 4 vsldoi12 <1,6,1,7>, <1,1,7,1> + 3248931636U, // <7,1,1,u>: Cost 2 vsldoi12 RHS, <1,1,1,1> + 3248931708U, // <7,1,2,0>: Cost 3 vsldoi12 RHS, <1,2,0,1> + 3248931719U, // <7,1,2,1>: Cost 3 vsldoi12 RHS, <1,2,1,3> + 3248931728U, // <7,1,2,2>: Cost 3 vsldoi12 RHS, <1,2,2,3> + 3248931734U, // <7,1,2,3>: Cost 2 vsldoi12 RHS, <1,2,3,0> + 3248931748U, // <7,1,2,4>: Cost 3 vsldoi12 RHS, <1,2,4,5> + 3248931755U, // <7,1,2,5>: Cost 3 vsldoi12 RHS, <1,2,5,3> + 4067103576U, // <7,1,2,6>: Cost 3 vsldoi4 <6,7,1,2>, <6,7,1,2> + 3272819642U, // <7,1,2,7>: Cost 3 vsldoi12 RHS, <1,2,7,0> + 3248931779U, // <7,1,2,u>: Cost 2 vsldoi12 RHS, <1,2,u,0> + 4179192011U, // <7,1,3,0>: Cost 4 vsldoi8 <3,0,7,1>, <3,0,7,1> + 3393142794U, // <7,1,3,1>: Cost 3 vmrglw <6,2,7,3>, <0,0,1,1> + 3389827222U, // <7,1,3,2>: Cost 3 vmrglw <5,6,7,3>, <3,0,1,2> + 3248931815U, // <7,1,3,3>: Cost 4 vsldoi12 RHS, <1,3,3,0> + 3248931824U, // <7,1,3,4>: Cost 4 vsldoi12 RHS, <1,3,4,0> + 3393143122U, // <7,1,3,5>: Cost 3 vmrglw <6,2,7,3>, <0,4,1,5> + 3229688841U, // <7,1,3,6>: Cost 4 vsldoi12 <1,3,6,7>, <1,3,6,7> + 3367265487U, // <7,1,3,7>: Cost 4 vmrglw <1,u,7,3>, <1,6,1,7> + 3393142801U, // <7,1,3,u>: Cost 3 vmrglw <6,2,7,3>, <0,0,1,u> + 4200426386U, // <7,1,4,0>: Cost 3 vsldoi8 <6,5,7,1>, <4,0,5,1> + 3248931883U, // <7,1,4,1>: Cost 3 vsldoi12 RHS, <1,4,1,5> + 3248931892U, // <7,1,4,2>: Cost 3 vsldoi12 RHS, <1,4,2,5> + 3248931896U, // <7,1,4,3>: Cost 4 vsldoi12 RHS, <1,4,3,0> + 4079062326U, // <7,1,4,4>: Cost 3 vsldoi4 , RHS + 3248931920U, // <7,1,4,5>: Cost 3 vsldoi12 RHS, <1,4,5,6> + 3231310936U, // <7,1,4,6>: Cost 4 vsldoi12 <1,6,1,7>, <1,4,6,5> + 4079064422U, // <7,1,4,7>: Cost 3 vsldoi4 , <7,4,5,6> + 3248931946U, // <7,1,4,u>: Cost 3 vsldoi12 RHS, <1,4,u,5> + 3248931951U, // <7,1,5,0>: Cost 3 vsldoi12 RHS, <1,5,0,1> + 3231605885U, // <7,1,5,1>: Cost 4 vsldoi12 <1,6,5,7>, <1,5,1,6> + 3237430406U, // <7,1,5,2>: Cost 4 vsldoi12 <2,6,3,7>, <1,5,2,6> + 3248931977U, // <7,1,5,3>: Cost 4 vsldoi12 RHS, <1,5,3,0> + 3248931991U, // <7,1,5,4>: Cost 3 vsldoi12 RHS, <1,5,4,5> + 3392495954U, // <7,1,5,5>: Cost 3 vmrglw <6,1,7,5>, <0,4,1,5> + 4195119203U, // <7,1,5,6>: Cost 3 vsldoi8 <5,6,7,1>, <5,6,7,1> + 3255198894U, // <7,1,5,7>: Cost 4 vsldoi12 <5,6,1,7>, <1,5,7,1> + 3248932023U, // <7,1,5,u>: Cost 3 vsldoi12 RHS, <1,5,u,1> + 4197110102U, // <7,1,6,0>: Cost 3 vsldoi8 <6,0,7,1>, <6,0,7,1> + 3231311055U, // <7,1,6,1>: Cost 3 vsldoi12 <1,6,1,7>, <1,6,1,7> + 3248932056U, // <7,1,6,2>: Cost 3 vsldoi12 RHS, <1,6,2,7> + 3231458529U, // <7,1,6,3>: Cost 4 vsldoi12 <1,6,3,7>, <1,6,3,7> + 3231532266U, // <7,1,6,4>: Cost 4 vsldoi12 <1,6,4,7>, <1,6,4,7> + 3231606003U, // <7,1,6,5>: Cost 3 vsldoi12 <1,6,5,7>, <1,6,5,7> + 3231679740U, // <7,1,6,6>: Cost 4 vsldoi12 <1,6,6,7>, <1,6,6,7> + 3272819966U, // <7,1,6,7>: Cost 3 vsldoi12 RHS, <1,6,7,0> + 3231827214U, // <7,1,6,u>: Cost 3 vsldoi12 <1,6,u,7>, <1,6,u,7> + 4079083622U, // <7,1,7,0>: Cost 3 vsldoi4 , LHS + 3395829770U, // <7,1,7,1>: Cost 3 vmrglw <6,6,7,7>, <0,0,1,1> + 3391190010U, // <7,1,7,2>: Cost 3 vmrglw <5,u,7,7>, <7,0,1,2> + 3395829934U, // <7,1,7,3>: Cost 4 vmrglw <6,6,7,7>, <0,2,1,3> + 4079086902U, // <7,1,7,4>: Cost 3 vsldoi4 , RHS + 3395830098U, // <7,1,7,5>: Cost 3 vmrglw <6,6,7,7>, <0,4,1,5> + 3375923377U, // <7,1,7,6>: Cost 4 vmrglw <3,3,7,7>, <0,2,1,6> + 4208391788U, // <7,1,7,7>: Cost 3 vsldoi8 <7,u,7,1>, <7,7,7,7> + 3395829777U, // <7,1,7,u>: Cost 3 vmrglw <6,6,7,7>, <0,0,1,u> + 3248932194U, // <7,1,u,0>: Cost 3 vsldoi12 RHS, <1,u,0,1> + 3248931636U, // <7,1,u,1>: Cost 2 vsldoi12 RHS, <1,1,1,1> + 3248932212U, // <7,1,u,2>: Cost 3 vsldoi12 RHS, <1,u,2,1> + 3248932220U, // <7,1,u,3>: Cost 2 vsldoi12 RHS, <1,u,3,0> + 3248932234U, // <7,1,u,4>: Cost 3 vsldoi12 RHS, <1,u,4,5> + 3232933269U, // <7,1,u,5>: Cost 3 vsldoi12 <1,u,5,7>, <1,u,5,7> + 4067152734U, // <7,1,u,6>: Cost 3 vsldoi4 <6,7,1,u>, <6,7,1,u> + 3272820128U, // <7,1,u,7>: Cost 3 vsldoi12 RHS, <1,u,7,0> + 3248932265U, // <7,1,u,u>: Cost 2 vsldoi12 RHS, <1,u,u,0> + 4049240166U, // <7,2,0,0>: Cost 4 vsldoi4 <3,7,2,0>, LHS + 3248932285U, // <7,2,0,1>: Cost 3 vsldoi12 RHS, <2,0,1,2> + 3248932293U, // <7,2,0,2>: Cost 3 vsldoi12 RHS, <2,0,2,1> + 2316058726U, // <7,2,0,3>: Cost 2 vmrglw <5,6,7,0>, LHS + 4049243446U, // <7,2,0,4>: Cost 4 vsldoi4 <3,7,2,0>, RHS + 3248932320U, // <7,2,0,5>: Cost 4 vsldoi12 RHS, <2,0,5,1> + 3237430761U, // <7,2,0,6>: Cost 3 vsldoi12 <2,6,3,7>, <2,0,6,1> + 3263121386U, // <7,2,0,7>: Cost 3 vmrghw <7,0,1,2>, <2,7,0,1> + 2316058731U, // <7,2,0,u>: Cost 2 vmrglw <5,6,7,0>, LHS + 3248932356U, // <7,2,1,0>: Cost 4 vsldoi12 RHS, <2,1,0,1> + 3248932365U, // <7,2,1,1>: Cost 4 vsldoi12 RHS, <2,1,1,1> + 3248932373U, // <7,2,1,2>: Cost 4 vsldoi12 RHS, <2,1,2,0> + 3248932383U, // <7,2,1,3>: Cost 3 vsldoi12 RHS, <2,1,3,1> + 3248932396U, // <7,2,1,4>: Cost 4 vsldoi12 RHS, <2,1,4,5> + 3236767286U, // <7,2,1,5>: Cost 5 vsldoi12 <2,5,3,7>, <2,1,5,6> + 3237430841U, // <7,2,1,6>: Cost 4 vsldoi12 <2,6,3,7>, <2,1,6,0> + 4197778722U, // <7,2,1,7>: Cost 4 vsldoi8 <6,1,7,2>, <1,7,2,0> + 3248932428U, // <7,2,1,u>: Cost 3 vsldoi12 RHS, <2,1,u,1> + 3248932437U, // <7,2,2,0>: Cost 3 vsldoi12 RHS, <2,2,0,1> + 3248932446U, // <7,2,2,1>: Cost 4 vsldoi12 RHS, <2,2,1,1> + 3248932456U, // <7,2,2,2>: Cost 2 vsldoi12 RHS, <2,2,2,2> + 3248932466U, // <7,2,2,3>: Cost 2 vsldoi12 RHS, <2,2,3,3> + 3248932477U, // <7,2,2,4>: Cost 3 vsldoi12 RHS, <2,2,4,5> + 3248932483U, // <7,2,2,5>: Cost 4 vsldoi12 RHS, <2,2,5,2> + 3237430928U, // <7,2,2,6>: Cost 3 vsldoi12 <2,6,3,7>, <2,2,6,6> + 3237357205U, // <7,2,2,7>: Cost 4 vsldoi12 <2,6,2,7>, <2,2,7,2> + 3248932511U, // <7,2,2,u>: Cost 2 vsldoi12 RHS, <2,2,u,3> + 3248932518U, // <7,2,3,0>: Cost 2 vsldoi12 RHS, <2,3,0,1> + 3248932527U, // <7,2,3,1>: Cost 3 vsldoi12 RHS, <2,3,1,1> + 3237430973U, // <7,2,3,2>: Cost 3 vsldoi12 <2,6,3,7>, <2,3,2,6> + 2319401062U, // <7,2,3,3>: Cost 2 vmrglw <6,2,7,3>, LHS + 3248932558U, // <7,2,3,4>: Cost 2 vsldoi12 RHS, <2,3,4,5> + 3248932567U, // <7,2,3,5>: Cost 3 vsldoi12 RHS, <2,3,5,5> + 4067185506U, // <7,2,3,6>: Cost 3 vsldoi4 <6,7,2,3>, <6,7,2,3> + 3393148398U, // <7,2,3,7>: Cost 3 vmrglw <6,2,7,3>, <7,6,2,7> + 3248932590U, // <7,2,3,u>: Cost 2 vsldoi12 RHS, <2,3,u,1> + 4049272934U, // <7,2,4,0>: Cost 4 vsldoi4 <3,7,2,4>, LHS + 3248932612U, // <7,2,4,1>: Cost 4 vsldoi12 RHS, <2,4,1,5> + 3248932621U, // <7,2,4,2>: Cost 3 vsldoi12 RHS, <2,4,2,5> + 2316091494U, // <7,2,4,3>: Cost 2 vmrglw <5,6,7,4>, LHS + 4049276214U, // <7,2,4,4>: Cost 4 vsldoi4 <3,7,2,4>, RHS + 3248932649U, // <7,2,4,5>: Cost 3 vsldoi12 RHS, <2,4,5,6> + 3237431089U, // <7,2,4,6>: Cost 3 vsldoi12 <2,6,3,7>, <2,4,6,5> + 3389834456U, // <7,2,4,7>: Cost 4 vmrglw <5,6,7,4>, <1,6,2,7> + 2316091499U, // <7,2,4,u>: Cost 2 vmrglw <5,6,7,4>, LHS + 3248932680U, // <7,2,5,0>: Cost 4 vsldoi12 RHS, <2,5,0,1> + 3248932690U, // <7,2,5,1>: Cost 4 vsldoi12 RHS, <2,5,1,2> + 3248932699U, // <7,2,5,2>: Cost 4 vsldoi12 RHS, <2,5,2,2> + 3248932712U, // <7,2,5,3>: Cost 3 vsldoi12 RHS, <2,5,3,6> + 3248932720U, // <7,2,5,4>: Cost 4 vsldoi12 RHS, <2,5,4,5> + 4195127300U, // <7,2,5,5>: Cost 4 vsldoi8 <5,6,7,2>, <5,5,5,5> + 4195127396U, // <7,2,5,6>: Cost 3 vsldoi8 <5,6,7,2>, <5,6,7,2> + 3237357452U, // <7,2,5,7>: Cost 5 vsldoi12 <2,6,2,7>, <2,5,7,6> + 3248932757U, // <7,2,5,u>: Cost 3 vsldoi12 RHS, <2,5,u,6> + 4049289318U, // <7,2,6,0>: Cost 3 vsldoi4 <3,7,2,6>, LHS + 4197781928U, // <7,2,6,1>: Cost 3 vsldoi8 <6,1,7,2>, <6,1,7,2> + 3237357489U, // <7,2,6,2>: Cost 3 vsldoi12 <2,6,2,7>, <2,6,2,7> + 3237431226U, // <7,2,6,3>: Cost 2 vsldoi12 <2,6,3,7>, <2,6,3,7> + 4049292598U, // <7,2,6,4>: Cost 3 vsldoi4 <3,7,2,6>, RHS + 3237578700U, // <7,2,6,5>: Cost 4 vsldoi12 <2,6,5,7>, <2,6,5,7> + 4067210085U, // <7,2,6,6>: Cost 3 vsldoi4 <6,7,2,6>, <6,7,2,6> + 3237357534U, // <7,2,6,7>: Cost 4 vsldoi12 <2,6,2,7>, <2,6,7,7> + 3237799911U, // <7,2,6,u>: Cost 2 vsldoi12 <2,6,u,7>, <2,6,u,7> + 3272820714U, // <7,2,7,0>: Cost 3 vsldoi12 RHS, <2,7,0,1> + 3248932856U, // <7,2,7,1>: Cost 4 vsldoi12 RHS, <2,7,1,6> + 3395831400U, // <7,2,7,2>: Cost 3 vmrglw <6,6,7,7>, <2,2,2,2> + 2322088038U, // <7,2,7,3>: Cost 2 vmrglw <6,6,7,7>, LHS + 3237357586U, // <7,2,7,4>: Cost 4 vsldoi12 <2,6,2,7>, <2,7,4,5> + 3395830836U, // <7,2,7,5>: Cost 4 vmrglw <6,6,7,7>, <1,4,2,5> + 3268249530U, // <7,2,7,6>: Cost 3 vmrghw <7,7,7,7>, <2,6,3,7> + 3371943857U, // <7,2,7,7>: Cost 4 vmrglw <2,6,7,7>, <2,6,2,7> + 2322088043U, // <7,2,7,u>: Cost 2 vmrglw <6,6,7,7>, LHS + 3248932923U, // <7,2,u,0>: Cost 2 vsldoi12 RHS, <2,u,0,1> + 3248932932U, // <7,2,u,1>: Cost 3 vsldoi12 RHS, <2,u,1,1> + 3248932456U, // <7,2,u,2>: Cost 2 vsldoi12 RHS, <2,2,2,2> + 3238758492U, // <7,2,u,3>: Cost 2 vsldoi12 <2,u,3,7>, <2,u,3,7> + 3248932963U, // <7,2,u,4>: Cost 2 vsldoi12 RHS, <2,u,4,5> + 3248932972U, // <7,2,u,5>: Cost 3 vsldoi12 RHS, <2,u,5,5> + 3237431409U, // <7,2,u,6>: Cost 3 vsldoi12 <2,6,3,7>, <2,u,6,1> + 3272820857U, // <7,2,u,7>: Cost 3 vsldoi12 RHS, <2,u,7,0> + 3239127177U, // <7,2,u,u>: Cost 2 vsldoi12 <2,u,u,7>, <2,u,u,7> + 3248933003U, // <7,3,0,0>: Cost 3 vsldoi12 RHS, <3,0,0,0> + 3248933014U, // <7,3,0,1>: Cost 2 vsldoi12 RHS, <3,0,1,2> + 4043343876U, // <7,3,0,2>: Cost 3 vsldoi4 <2,7,3,0>, <2,7,3,0> + 3248933031U, // <7,3,0,3>: Cost 3 vsldoi12 RHS, <3,0,3,1> + 3248933040U, // <7,3,0,4>: Cost 3 vsldoi12 RHS, <3,0,4,1> + 3248933053U, // <7,3,0,5>: Cost 4 vsldoi12 RHS, <3,0,5,5> + 4067234664U, // <7,3,0,6>: Cost 3 vsldoi4 <6,7,3,0>, <6,7,3,0> + 3389802426U, // <7,3,0,7>: Cost 3 vmrglw <5,6,7,0>, <2,6,3,7> + 3248933077U, // <7,3,0,u>: Cost 2 vsldoi12 RHS, <3,0,u,2> + 3248933084U, // <7,3,1,0>: Cost 4 vsldoi12 RHS, <3,1,0,0> + 3248933094U, // <7,3,1,1>: Cost 3 vsldoi12 RHS, <3,1,1,1> + 3248933105U, // <7,3,1,2>: Cost 3 vsldoi12 RHS, <3,1,2,3> + 3248933111U, // <7,3,1,3>: Cost 4 vsldoi12 RHS, <3,1,3,0> + 3248933120U, // <7,3,1,4>: Cost 4 vsldoi12 RHS, <3,1,4,0> + 3248933129U, // <7,3,1,5>: Cost 4 vsldoi12 RHS, <3,1,5,0> + 3231312147U, // <7,3,1,6>: Cost 4 vsldoi12 <1,6,1,7>, <3,1,6,1> + 3237431580U, // <7,3,1,7>: Cost 4 vsldoi12 <2,6,3,7>, <3,1,7,1> + 3248933159U, // <7,3,1,u>: Cost 3 vsldoi12 RHS, <3,1,u,3> + 3248933168U, // <7,3,2,0>: Cost 3 vsldoi12 RHS, <3,2,0,3> + 3248933176U, // <7,3,2,1>: Cost 4 vsldoi12 RHS, <3,2,1,2> + 3248933185U, // <7,3,2,2>: Cost 3 vsldoi12 RHS, <3,2,2,2> + 3248933192U, // <7,3,2,3>: Cost 3 vsldoi12 RHS, <3,2,3,0> + 3248933204U, // <7,3,2,4>: Cost 3 vsldoi12 RHS, <3,2,4,3> + 3248933213U, // <7,3,2,5>: Cost 4 vsldoi12 RHS, <3,2,5,3> + 3237431654U, // <7,3,2,6>: Cost 3 vsldoi12 <2,6,3,7>, <3,2,6,3> + 3237431663U, // <7,3,2,7>: Cost 3 vsldoi12 <2,6,3,7>, <3,2,7,3> + 3248933237U, // <7,3,2,u>: Cost 3 vsldoi12 RHS, <3,2,u,0> + 3248933246U, // <7,3,3,0>: Cost 3 vsldoi12 RHS, <3,3,0,0> + 3248933256U, // <7,3,3,1>: Cost 4 vsldoi12 RHS, <3,3,1,1> + 4180535663U, // <7,3,3,2>: Cost 3 vsldoi8 <3,2,7,3>, <3,2,7,3> + 3248933276U, // <7,3,3,3>: Cost 2 vsldoi12 RHS, <3,3,3,3> + 3248933286U, // <7,3,3,4>: Cost 3 vsldoi12 RHS, <3,3,4,4> + 3248933294U, // <7,3,3,5>: Cost 4 vsldoi12 RHS, <3,3,5,3> + 4067259243U, // <7,3,3,6>: Cost 3 vsldoi4 <6,7,3,3>, <6,7,3,3> + 3237431748U, // <7,3,3,7>: Cost 3 vsldoi12 <2,6,3,7>, <3,3,7,7> + 3248933276U, // <7,3,3,u>: Cost 2 vsldoi12 RHS, <3,3,3,3> + 3248933328U, // <7,3,4,0>: Cost 3 vsldoi12 RHS, <3,4,0,1> + 3248933338U, // <7,3,4,1>: Cost 3 vsldoi12 RHS, <3,4,1,2> + 4043376648U, // <7,3,4,2>: Cost 3 vsldoi4 <2,7,3,4>, <2,7,3,4> + 3248933359U, // <7,3,4,3>: Cost 3 vsldoi12 RHS, <3,4,3,5> + 3248933367U, // <7,3,4,4>: Cost 3 vsldoi12 RHS, <3,4,4,4> + 3248933378U, // <7,3,4,5>: Cost 2 vsldoi12 RHS, <3,4,5,6> + 4198452601U, // <7,3,4,6>: Cost 3 vsldoi8 <6,2,7,3>, <4,6,5,2> + 3389835194U, // <7,3,4,7>: Cost 3 vmrglw <5,6,7,4>, <2,6,3,7> + 3248933405U, // <7,3,4,u>: Cost 2 vsldoi12 RHS, <3,4,u,6> + 3248933409U, // <7,3,5,0>: Cost 4 vsldoi12 RHS, <3,5,0,1> + 4198452879U, // <7,3,5,1>: Cost 4 vsldoi8 <6,2,7,3>, <5,1,0,1> + 3248933427U, // <7,3,5,2>: Cost 4 vsldoi12 RHS, <3,5,2,1> + 3248933438U, // <7,3,5,3>: Cost 4 vsldoi12 RHS, <3,5,3,3> + 3248933449U, // <7,3,5,4>: Cost 4 vsldoi12 RHS, <3,5,4,5> + 3248933458U, // <7,3,5,5>: Cost 3 vsldoi12 RHS, <3,5,5,5> + 4195135589U, // <7,3,5,6>: Cost 3 vsldoi8 <5,6,7,3>, <5,6,7,3> + 3237431909U, // <7,3,5,7>: Cost 4 vsldoi12 <2,6,3,7>, <3,5,7,6> + 4196462855U, // <7,3,5,u>: Cost 3 vsldoi8 <5,u,7,3>, <5,u,7,3> + 3243182712U, // <7,3,6,0>: Cost 3 vsldoi12 <3,6,0,7>, <3,6,0,7> + 3243256449U, // <7,3,6,1>: Cost 4 vsldoi12 <3,6,1,7>, <3,6,1,7> + 3124711930U, // <7,3,6,2>: Cost 2 vsldoi8 <6,2,7,3>, <6,2,7,3> + 3243403923U, // <7,3,6,3>: Cost 3 vsldoi12 <3,6,3,7>, <3,6,3,7> + 3243477660U, // <7,3,6,4>: Cost 3 vsldoi12 <3,6,4,7>, <3,6,4,7> + 3243551397U, // <7,3,6,5>: Cost 4 vsldoi12 <3,6,5,7>, <3,6,5,7> + 4198454032U, // <7,3,6,6>: Cost 3 vsldoi8 <6,2,7,3>, <6,6,2,2> + 3237431991U, // <7,3,6,7>: Cost 3 vsldoi12 <2,6,3,7>, <3,6,7,7> + 3128693728U, // <7,3,6,u>: Cost 2 vsldoi8 <6,u,7,3>, <6,u,7,3> + 3237432003U, // <7,3,7,0>: Cost 3 vsldoi12 <2,6,3,7>, <3,7,0,1> + 3237432012U, // <7,3,7,1>: Cost 4 vsldoi12 <2,6,3,7>, <3,7,1,1> + 3237432026U, // <7,3,7,2>: Cost 3 vsldoi12 <2,6,3,7>, <3,7,2,6> + 4198454554U, // <7,3,7,3>: Cost 3 vsldoi8 <6,2,7,3>, <7,3,6,2> + 3237432043U, // <7,3,7,4>: Cost 3 vsldoi12 <2,6,3,7>, <3,7,4,5> + 3248933620U, // <7,3,7,5>: Cost 4 vsldoi12 RHS, <3,7,5,5> + 4198454766U, // <7,3,7,6>: Cost 3 vsldoi8 <6,2,7,3>, <7,6,2,7> + 3375925178U, // <7,3,7,7>: Cost 3 vmrglw <3,3,7,7>, <2,6,3,7> + 3237432075U, // <7,3,7,u>: Cost 3 vsldoi12 <2,6,3,7>, <3,7,u,1> + 3244509978U, // <7,3,u,0>: Cost 3 vsldoi12 <3,u,0,7>, <3,u,0,7> + 3248933662U, // <7,3,u,1>: Cost 2 vsldoi12 RHS, <3,u,1,2> + 3136657324U, // <7,3,u,2>: Cost 2 vsldoi8 , + 3248933276U, // <7,3,u,3>: Cost 2 vsldoi12 RHS, <3,3,3,3> + 3244804926U, // <7,3,u,4>: Cost 3 vsldoi12 <3,u,4,7>, <3,u,4,7> + 3248933702U, // <7,3,u,5>: Cost 2 vsldoi12 RHS, <3,u,5,6> + 3248933708U, // <7,3,u,6>: Cost 3 vsldoi12 RHS, <3,u,6,3> + 3237432149U, // <7,3,u,7>: Cost 3 vsldoi12 <2,6,3,7>, <3,u,7,3> + 3248933725U, // <7,3,u,u>: Cost 2 vsldoi12 RHS, <3,u,u,2> + 4195139584U, // <7,4,0,0>: Cost 3 vsldoi8 <5,6,7,4>, <0,0,0,0> + 3121397862U, // <7,4,0,1>: Cost 2 vsldoi8 <5,6,7,4>, LHS + 3248933751U, // <7,4,0,2>: Cost 4 vsldoi12 RHS, <4,0,2,1> + 3248933760U, // <7,4,0,3>: Cost 4 vsldoi12 RHS, <4,0,3,1> + 3389803728U, // <7,4,0,4>: Cost 3 vmrglw <5,6,7,0>, <4,4,4,4> + 3248933778U, // <7,4,0,5>: Cost 2 vsldoi12 RHS, <4,0,5,1> + 4067308401U, // <7,4,0,6>: Cost 3 vsldoi4 <6,7,4,0>, <6,7,4,0> + 3263122888U, // <7,4,0,7>: Cost 3 vmrghw <7,0,1,2>, <4,7,5,0> + 3250924461U, // <7,4,0,u>: Cost 2 vsldoi12 RHS, <4,0,u,1> + 3248933814U, // <7,4,1,0>: Cost 4 vsldoi12 RHS, <4,1,0,1> + 4195140404U, // <7,4,1,1>: Cost 3 vsldoi8 <5,6,7,4>, <1,1,1,1> + 3248933834U, // <7,4,1,2>: Cost 3 vsldoi12 RHS, <4,1,2,3> + 3248933840U, // <7,4,1,3>: Cost 4 vsldoi12 RHS, <4,1,3,0> + 3248933851U, // <7,4,1,4>: Cost 4 vsldoi12 RHS, <4,1,4,2> + 3248933858U, // <7,4,1,5>: Cost 3 vsldoi12 RHS, <4,1,5,0> + 4195140815U, // <7,4,1,6>: Cost 4 vsldoi8 <5,6,7,4>, <1,6,1,7> + 3394456220U, // <7,4,1,7>: Cost 4 vmrglw <6,4,7,1>, <3,6,4,7> + 3248933885U, // <7,4,1,u>: Cost 3 vsldoi12 RHS, <4,1,u,0> + 3248933897U, // <7,4,2,0>: Cost 4 vsldoi12 RHS, <4,2,0,3> + 3248933906U, // <7,4,2,1>: Cost 4 vsldoi12 RHS, <4,2,1,3> + 4195141224U, // <7,4,2,2>: Cost 3 vsldoi8 <5,6,7,4>, <2,2,2,2> + 4195141286U, // <7,4,2,3>: Cost 3 vsldoi8 <5,6,7,4>, <2,3,0,1> + 3248933933U, // <7,4,2,4>: Cost 3 vsldoi12 RHS, <4,2,4,3> + 3248933941U, // <7,4,2,5>: Cost 3 vsldoi12 RHS, <4,2,5,2> + 4195141562U, // <7,4,2,6>: Cost 3 vsldoi8 <5,6,7,4>, <2,6,3,7> + 3243478088U, // <7,4,2,7>: Cost 4 vsldoi12 <3,6,4,7>, <4,2,7,3> + 3248933969U, // <7,4,2,u>: Cost 3 vsldoi12 RHS, <4,2,u,3> + 4195141782U, // <7,4,3,0>: Cost 3 vsldoi8 <5,6,7,4>, <3,0,1,2> + 3248933986U, // <7,4,3,1>: Cost 4 vsldoi12 RHS, <4,3,1,2> + 3248933996U, // <7,4,3,2>: Cost 4 vsldoi12 RHS, <4,3,2,3> + 4195142044U, // <7,4,3,3>: Cost 3 vsldoi8 <5,6,7,4>, <3,3,3,3> + 4195142146U, // <7,4,3,4>: Cost 3 vsldoi8 <5,6,7,4>, <3,4,5,6> + 3248934020U, // <7,4,3,5>: Cost 3 vsldoi12 RHS, <4,3,5,0> + 4183198388U, // <7,4,3,6>: Cost 3 vsldoi8 <3,6,7,4>, <3,6,7,4> + 3243478170U, // <7,4,3,7>: Cost 4 vsldoi12 <3,6,4,7>, <4,3,7,4> + 3250924703U, // <7,4,3,u>: Cost 3 vsldoi12 RHS, <4,3,u,0> + 4195142546U, // <7,4,4,0>: Cost 3 vsldoi8 <5,6,7,4>, <4,0,5,1> + 3248934066U, // <7,4,4,1>: Cost 4 vsldoi12 RHS, <4,4,1,1> + 3248934076U, // <7,4,4,2>: Cost 4 vsldoi12 RHS, <4,4,2,2> + 3389838520U, // <7,4,4,3>: Cost 3 vmrglw <5,6,7,4>, <7,2,4,3> + 3248934096U, // <7,4,4,4>: Cost 2 vsldoi12 RHS, <4,4,4,4> + 3248934106U, // <7,4,4,5>: Cost 2 vsldoi12 RHS, <4,4,5,5> + 4067341173U, // <7,4,4,6>: Cost 3 vsldoi4 <6,7,4,4>, <6,7,4,4> + 3389838848U, // <7,4,4,7>: Cost 3 vmrglw <5,6,7,4>, <7,6,4,7> + 3250924789U, // <7,4,4,u>: Cost 2 vsldoi12 RHS, <4,4,u,5> + 2993602662U, // <7,4,5,0>: Cost 2 vsldoi4 <6,7,4,5>, LHS + 4067345204U, // <7,4,5,1>: Cost 3 vsldoi4 <6,7,4,5>, <1,1,1,1> + 4049430458U, // <7,4,5,2>: Cost 3 vsldoi4 <3,7,4,5>, <2,6,3,7> + 4049431275U, // <7,4,5,3>: Cost 3 vsldoi4 <3,7,4,5>, <3,7,4,5> + 2993605942U, // <7,4,5,4>: Cost 2 vsldoi4 <6,7,4,5>, RHS + 3248934182U, // <7,4,5,5>: Cost 3 vsldoi12 RHS, <4,5,5,0> + 1101450550U, // <7,4,5,6>: Cost 1 vsldoi12 RHS, RHS + 4067349498U, // <7,4,5,7>: Cost 3 vsldoi4 <6,7,4,5>, <7,0,1,2> + 1101450568U, // <7,4,5,u>: Cost 1 vsldoi12 RHS, RHS + 3248934225U, // <7,4,6,0>: Cost 4 vsldoi12 RHS, <4,6,0,7> + 3248934234U, // <7,4,6,1>: Cost 4 vsldoi12 RHS, <4,6,1,7> + 4195144186U, // <7,4,6,2>: Cost 3 vsldoi8 <5,6,7,4>, <6,2,7,3> + 4199125580U, // <7,4,6,3>: Cost 3 vsldoi8 <6,3,7,4>, <6,3,7,4> + 4199789213U, // <7,4,6,4>: Cost 3 vsldoi8 <6,4,7,4>, <6,4,7,4> + 3248934269U, // <7,4,6,5>: Cost 3 vsldoi12 RHS, <4,6,5,6> + 4195144504U, // <7,4,6,6>: Cost 3 vsldoi8 <5,6,7,4>, <6,6,6,6> + 4195144526U, // <7,4,6,7>: Cost 3 vsldoi8 <5,6,7,4>, <6,7,0,1> + 3248934297U, // <7,4,6,u>: Cost 3 vsldoi12 RHS, <4,6,u,7> + 4195144698U, // <7,4,7,0>: Cost 3 vsldoi8 <5,6,7,4>, <7,0,1,2> + 3243478438U, // <7,4,7,1>: Cost 4 vsldoi12 <3,6,4,7>, <4,7,1,2> + 4195144888U, // <7,4,7,2>: Cost 3 vsldoi8 <5,6,7,4>, <7,2,4,3> + 3243478460U, // <7,4,7,3>: Cost 4 vsldoi12 <3,6,4,7>, <4,7,3,6> + 4195145012U, // <7,4,7,4>: Cost 3 vsldoi8 <5,6,7,4>, <7,4,0,1> + 2194509110U, // <7,4,7,5>: Cost 2 vmrghw <7,7,7,7>, RHS + 4195145216U, // <7,4,7,6>: Cost 3 vsldoi8 <5,6,7,4>, <7,6,4,7> + 4195145294U, // <7,4,7,7>: Cost 3 vsldoi8 <5,6,7,4>, <7,7,4,4> + 2194509353U, // <7,4,7,u>: Cost 2 vmrghw <7,7,7,7>, RHS + 2993627238U, // <7,4,u,0>: Cost 2 vsldoi4 <6,7,4,u>, LHS + 3121403694U, // <7,4,u,1>: Cost 2 vsldoi8 <5,6,7,4>, LHS + 4049455034U, // <7,4,u,2>: Cost 3 vsldoi4 <3,7,4,u>, <2,6,3,7> + 4049455854U, // <7,4,u,3>: Cost 3 vsldoi4 <3,7,4,u>, <3,7,4,u> + 2993630518U, // <7,4,u,4>: Cost 2 vsldoi4 <6,7,4,u>, RHS + 3248934426U, // <7,4,u,5>: Cost 2 vsldoi12 RHS, <4,u,5,1> + 1101450793U, // <7,4,u,6>: Cost 1 vsldoi12 RHS, RHS + 4195145984U, // <7,4,u,7>: Cost 3 vsldoi8 <5,6,7,4>, + 1101450811U, // <7,4,u,u>: Cost 1 vsldoi12 RHS, RHS + 4055433318U, // <7,5,0,0>: Cost 3 vsldoi4 <4,7,5,0>, LHS + 3248934472U, // <7,5,0,1>: Cost 3 vsldoi12 RHS, <5,0,1,2> + 3248934482U, // <7,5,0,2>: Cost 4 vsldoi12 RHS, <5,0,2,3> + 3248934492U, // <7,5,0,3>: Cost 4 vsldoi12 RHS, <5,0,3,4> + 3248934498U, // <7,5,0,4>: Cost 3 vsldoi12 RHS, <5,0,4,1> + 3389803738U, // <7,5,0,5>: Cost 3 vmrglw <5,6,7,0>, <4,4,5,5> + 3389803010U, // <7,5,0,6>: Cost 3 vmrglw <5,6,7,0>, <3,4,5,6> + 4055438330U, // <7,5,0,7>: Cost 3 vsldoi4 <4,7,5,0>, <7,0,1,2> + 3248934534U, // <7,5,0,u>: Cost 3 vsldoi12 RHS, <5,0,u,1> + 3250925199U, // <7,5,1,0>: Cost 3 vsldoi12 RHS, <5,1,0,1> + 3395120018U, // <7,5,1,1>: Cost 3 vmrglw <6,5,7,1>, <4,0,5,1> + 3248934563U, // <7,5,1,2>: Cost 4 vsldoi12 RHS, <5,1,2,3> + 3248934574U, // <7,5,1,3>: Cost 4 vsldoi12 RHS, <5,1,3,5> + 3250925239U, // <7,5,1,4>: Cost 3 vsldoi12 RHS, <5,1,4,5> + 3248934587U, // <7,5,1,5>: Cost 4 vsldoi12 RHS, <5,1,5,0> + 3231608521U, // <7,5,1,6>: Cost 4 vsldoi12 <1,6,5,7>, <5,1,6,5> + 3231608530U, // <7,5,1,7>: Cost 4 vsldoi12 <1,6,5,7>, <5,1,7,5> + 3250925271U, // <7,5,1,u>: Cost 3 vsldoi12 RHS, <5,1,u,1> + 3248934624U, // <7,5,2,0>: Cost 4 vsldoi12 RHS, <5,2,0,1> + 3250925291U, // <7,5,2,1>: Cost 3 vsldoi12 RHS, <5,2,1,3> + 3248934643U, // <7,5,2,2>: Cost 4 vsldoi12 RHS, <5,2,2,2> + 3248934654U, // <7,5,2,3>: Cost 3 vsldoi12 RHS, <5,2,3,4> + 4183205681U, // <7,5,2,4>: Cost 4 vsldoi8 <3,6,7,5>, <2,4,6,5> + 3250925327U, // <7,5,2,5>: Cost 3 vsldoi12 RHS, <5,2,5,3> + 3248934680U, // <7,5,2,6>: Cost 3 vsldoi12 RHS, <5,2,6,3> + 3231608609U, // <7,5,2,7>: Cost 4 vsldoi12 <1,6,5,7>, <5,2,7,3> + 3248934698U, // <7,5,2,u>: Cost 3 vsldoi12 RHS, <5,2,u,3> + 3248934705U, // <7,5,3,0>: Cost 4 vsldoi12 RHS, <5,3,0,1> + 3393145746U, // <7,5,3,1>: Cost 3 vmrglw <6,2,7,3>, <4,0,5,1> + 3393146233U, // <7,5,3,2>: Cost 3 vmrglw <6,2,7,3>, <4,6,5,2> + 3248934734U, // <7,5,3,3>: Cost 4 vsldoi12 RHS, <5,3,3,3> + 4181879315U, // <7,5,3,4>: Cost 4 vsldoi8 <3,4,7,5>, <3,4,7,5> + 3393146074U, // <7,5,3,5>: Cost 3 vmrglw <6,2,7,3>, <4,4,5,5> + 3393145346U, // <7,5,3,6>: Cost 3 vmrglw <6,2,7,3>, <3,4,5,6> + 3248934771U, // <7,5,3,7>: Cost 4 vsldoi12 RHS, <5,3,7,4> + 3393145348U, // <7,5,3,u>: Cost 3 vmrglw <6,2,7,3>, <3,4,5,u> + 4055466086U, // <7,5,4,0>: Cost 3 vsldoi4 <4,7,5,4>, LHS + 3389836178U, // <7,5,4,1>: Cost 3 vmrglw <5,6,7,4>, <4,0,5,1> + 3248934806U, // <7,5,4,2>: Cost 4 vsldoi12 RHS, <5,4,2,3> + 3248934816U, // <7,5,4,3>: Cost 4 vsldoi12 RHS, <5,4,3,4> + 4055469516U, // <7,5,4,4>: Cost 3 vsldoi4 <4,7,5,4>, <4,7,5,4> + 3248934836U, // <7,5,4,5>: Cost 3 vsldoi12 RHS, <5,4,5,6> + 3389835778U, // <7,5,4,6>: Cost 3 vmrglw <5,6,7,4>, <3,4,5,6> + 4055471462U, // <7,5,4,7>: Cost 3 vsldoi4 <4,7,5,4>, <7,4,5,6> + 3248934863U, // <7,5,4,u>: Cost 3 vsldoi12 RHS, <5,4,u,6> + 3250925523U, // <7,5,5,0>: Cost 3 vsldoi12 RHS, <5,5,0,1> + 3250925532U, // <7,5,5,1>: Cost 3 vsldoi12 RHS, <5,5,1,1> + 3248934886U, // <7,5,5,2>: Cost 4 vsldoi12 RHS, <5,5,2,2> + 3248934896U, // <7,5,5,3>: Cost 4 vsldoi12 RHS, <5,5,3,3> + 3250925563U, // <7,5,5,4>: Cost 3 vsldoi12 RHS, <5,5,4,5> + 3248934916U, // <7,5,5,5>: Cost 2 vsldoi12 RHS, <5,5,5,5> + 3248934926U, // <7,5,5,6>: Cost 3 vsldoi12 RHS, <5,5,6,6> + 3231608856U, // <7,5,5,7>: Cost 4 vsldoi12 <1,6,5,7>, <5,5,7,7> + 3248934916U, // <7,5,5,u>: Cost 2 vsldoi12 RHS, <5,5,5,5> + 3248934948U, // <7,5,6,0>: Cost 3 vsldoi12 RHS, <5,6,0,1> + 3250925619U, // <7,5,6,1>: Cost 3 vsldoi12 RHS, <5,6,1,7> + 3248934967U, // <7,5,6,2>: Cost 4 vsldoi12 RHS, <5,6,2,2> + 3248934978U, // <7,5,6,3>: Cost 3 vsldoi12 RHS, <5,6,3,4> + 3248934988U, // <7,5,6,4>: Cost 3 vsldoi12 RHS, <5,6,4,5> + 3250925655U, // <7,5,6,5>: Cost 3 vsldoi12 RHS, <5,6,5,7> + 3248935008U, // <7,5,6,6>: Cost 3 vsldoi12 RHS, <5,6,6,7> + 3248935010U, // <7,5,6,7>: Cost 2 vsldoi12 RHS, <5,6,7,0> + 3249082475U, // <7,5,6,u>: Cost 2 vsldoi12 RHS, <5,6,u,0> + 4055490662U, // <7,5,7,0>: Cost 3 vsldoi4 <4,7,5,7>, LHS + 3395832722U, // <7,5,7,1>: Cost 3 vmrglw <6,6,7,7>, <4,0,5,1> + 4055492200U, // <7,5,7,2>: Cost 4 vsldoi4 <4,7,5,7>, <2,2,2,2> + 4055492758U, // <7,5,7,3>: Cost 4 vsldoi4 <4,7,5,7>, <3,0,1,2> + 4055494095U, // <7,5,7,4>: Cost 3 vsldoi4 <4,7,5,7>, <4,7,5,7> + 3395833050U, // <7,5,7,5>: Cost 3 vmrglw <6,6,7,7>, <4,4,5,5> + 3395832322U, // <7,5,7,6>: Cost 3 vmrglw <6,6,7,7>, <3,4,5,6> + 4055496300U, // <7,5,7,7>: Cost 3 vsldoi4 <4,7,5,7>, <7,7,7,7> + 4055496494U, // <7,5,7,u>: Cost 3 vsldoi4 <4,7,5,7>, LHS + 3248935110U, // <7,5,u,0>: Cost 3 vsldoi12 RHS, <5,u,0,1> + 3248935120U, // <7,5,u,1>: Cost 3 vsldoi12 RHS, <5,u,1,2> + 3393146233U, // <7,5,u,2>: Cost 3 vmrglw <6,2,7,3>, <4,6,5,2> + 3248935140U, // <7,5,u,3>: Cost 3 vsldoi12 RHS, <5,u,3,4> + 3248935149U, // <7,5,u,4>: Cost 3 vsldoi12 RHS, <5,u,4,4> + 3248934916U, // <7,5,u,5>: Cost 2 vsldoi12 RHS, <5,5,5,5> + 3248935166U, // <7,5,u,6>: Cost 3 vsldoi12 RHS, <5,u,6,3> + 3249082628U, // <7,5,u,7>: Cost 2 vsldoi12 RHS, <5,u,7,0> + 3250925837U, // <7,5,u,u>: Cost 2 vsldoi12 RHS, <5,u,u,0> + 3248935190U, // <7,6,0,0>: Cost 4 vsldoi12 RHS, <6,0,0,0> + 3248935201U, // <7,6,0,1>: Cost 3 vsldoi12 RHS, <6,0,1,2> + 3263123962U, // <7,6,0,2>: Cost 3 vmrghw <7,0,1,2>, <6,2,7,3> + 3248935218U, // <7,6,0,3>: Cost 4 vsldoi12 RHS, <6,0,3,1> + 3248935227U, // <7,6,0,4>: Cost 4 vsldoi12 RHS, <6,0,4,1> + 3389804476U, // <7,6,0,5>: Cost 3 vmrglw <5,6,7,0>, <5,4,6,5> + 3389805368U, // <7,6,0,6>: Cost 3 vmrglw <5,6,7,0>, <6,6,6,6> + 2316062006U, // <7,6,0,7>: Cost 2 vmrglw <5,6,7,0>, RHS + 2316062007U, // <7,6,0,u>: Cost 2 vmrglw <5,6,7,0>, RHS + 3248935272U, // <7,6,1,0>: Cost 4 vsldoi12 RHS, <6,1,0,1> + 3377866217U, // <7,6,1,1>: Cost 4 vmrglw <3,6,7,1>, <2,0,6,1> + 3248935292U, // <7,6,1,2>: Cost 4 vsldoi12 RHS, <6,1,2,3> + 3229692296U, // <7,6,1,3>: Cost 5 vsldoi12 <1,3,6,7>, <6,1,3,6> + 3248935312U, // <7,6,1,4>: Cost 4 vsldoi12 RHS, <6,1,4,5> + 3395122056U, // <7,6,1,5>: Cost 4 vmrglw <6,5,7,1>, <6,7,6,5> + 3389813560U, // <7,6,1,6>: Cost 4 vmrglw <5,6,7,1>, <6,6,6,6> + 3248935335U, // <7,6,1,7>: Cost 3 vsldoi12 RHS, <6,1,7,1> + 3249082800U, // <7,6,1,u>: Cost 3 vsldoi12 RHS, <6,1,u,1> + 4067467366U, // <7,6,2,0>: Cost 3 vsldoi4 <6,7,6,2>, LHS + 3248935364U, // <7,6,2,1>: Cost 4 vsldoi12 RHS, <6,2,1,3> + 3264606714U, // <7,6,2,2>: Cost 3 vmrghw <7,2,3,3>, <6,2,7,3> + 3237433813U, // <7,6,2,3>: Cost 4 vsldoi12 <2,6,3,7>, <6,2,3,2> + 4067470646U, // <7,6,2,4>: Cost 3 vsldoi4 <6,7,6,2>, RHS + 3248935400U, // <7,6,2,5>: Cost 4 vsldoi12 RHS, <6,2,5,3> + 4067472261U, // <7,6,2,6>: Cost 3 vsldoi4 <6,7,6,2>, <6,7,6,2> + 3248935418U, // <7,6,2,7>: Cost 2 vsldoi12 RHS, <6,2,7,3> + 3249082883U, // <7,6,2,u>: Cost 2 vsldoi12 RHS, <6,2,u,3> + 4049559654U, // <7,6,3,0>: Cost 4 vsldoi4 <3,7,6,3>, LHS + 4179896609U, // <7,6,3,1>: Cost 4 vsldoi8 <3,1,7,6>, <3,1,7,6> + 3393147781U, // <7,6,3,2>: Cost 3 vmrglw <6,2,7,3>, <6,7,6,2> + 3375229286U, // <7,6,3,3>: Cost 4 vmrglw <3,2,7,3>, <3,2,6,3> + 3248935474U, // <7,6,3,4>: Cost 3 vsldoi12 RHS, <6,3,4,5> + 3375228721U, // <7,6,3,5>: Cost 4 vmrglw <3,2,7,3>, <2,4,6,5> + 3393147704U, // <7,6,3,6>: Cost 3 vmrglw <6,2,7,3>, <6,6,6,6> + 2319404342U, // <7,6,3,7>: Cost 2 vmrglw <6,2,7,3>, RHS + 2319404343U, // <7,6,3,u>: Cost 2 vmrglw <6,2,7,3>, RHS + 3248935515U, // <7,6,4,0>: Cost 4 vsldoi12 RHS, <6,4,0,1> + 3389834729U, // <7,6,4,1>: Cost 4 vmrglw <5,6,7,4>, <2,0,6,1> + 3266105850U, // <7,6,4,2>: Cost 3 vmrghw <7,4,5,6>, <6,2,7,3> + 3248935545U, // <7,6,4,3>: Cost 4 vsldoi12 RHS, <6,4,3,4> + 3248935554U, // <7,6,4,4>: Cost 4 vsldoi12 RHS, <6,4,4,4> + 3248935565U, // <7,6,4,5>: Cost 3 vsldoi12 RHS, <6,4,5,6> + 3389838136U, // <7,6,4,6>: Cost 3 vmrglw <5,6,7,4>, <6,6,6,6> + 2316094774U, // <7,6,4,7>: Cost 2 vmrglw <5,6,7,4>, RHS + 2316094775U, // <7,6,4,u>: Cost 2 vmrglw <5,6,7,4>, RHS + 3248935596U, // <7,6,5,0>: Cost 4 vsldoi12 RHS, <6,5,0,1> + 3231314616U, // <7,6,5,1>: Cost 5 vsldoi12 <1,6,1,7>, <6,5,1,4> + 3248935619U, // <7,6,5,2>: Cost 4 vsldoi12 RHS, <6,5,2,6> + 3248935628U, // <7,6,5,3>: Cost 4 vsldoi12 RHS, <6,5,3,6> + 3248935636U, // <7,6,5,4>: Cost 4 vsldoi12 RHS, <6,5,4,5> + 3377899313U, // <7,6,5,5>: Cost 4 vmrglw <3,6,7,5>, <2,4,6,5> + 4195160168U, // <7,6,5,6>: Cost 3 vsldoi8 <5,6,7,6>, <5,6,7,6> + 3248935659U, // <7,6,5,7>: Cost 3 vsldoi12 RHS, <6,5,7,1> + 3249083124U, // <7,6,5,u>: Cost 3 vsldoi12 RHS, <6,5,u,1> + 4067500134U, // <7,6,6,0>: Cost 3 vsldoi4 <6,7,6,6>, LHS + 3248935686U, // <7,6,6,1>: Cost 4 vsldoi12 RHS, <6,6,1,1> + 4195160570U, // <7,6,6,2>: Cost 3 vsldoi8 <5,6,7,6>, <6,2,7,3> + 4049586942U, // <7,6,6,3>: Cost 4 vsldoi4 <3,7,6,6>, <3,7,6,6> + 4067503414U, // <7,6,6,4>: Cost 3 vsldoi4 <6,7,6,6>, RHS + 4200469232U, // <7,6,6,5>: Cost 3 vsldoi8 <6,5,7,6>, <6,5,7,6> + 3248935736U, // <7,6,6,6>: Cost 2 vsldoi12 RHS, <6,6,6,6> + 3248935746U, // <7,6,6,7>: Cost 2 vsldoi12 RHS, <6,6,7,7> + 3249083211U, // <7,6,6,u>: Cost 2 vsldoi12 RHS, <6,6,u,7> + 3248935758U, // <7,6,7,0>: Cost 2 vsldoi12 RHS, <6,7,0,1> + 3248935767U, // <7,6,7,1>: Cost 3 vsldoi12 RHS, <6,7,1,1> + 3248935777U, // <7,6,7,2>: Cost 3 vsldoi12 RHS, <6,7,2,2> + 3248935784U, // <7,6,7,3>: Cost 3 vsldoi12 RHS, <6,7,3,0> + 3248935798U, // <7,6,7,4>: Cost 2 vsldoi12 RHS, <6,7,4,5> + 3248935807U, // <7,6,7,5>: Cost 3 vsldoi12 RHS, <6,7,5,5> + 3248935813U, // <7,6,7,6>: Cost 3 vsldoi12 RHS, <6,7,6,2> + 2322091318U, // <7,6,7,7>: Cost 2 vmrglw <6,6,7,7>, RHS + 3248935830U, // <7,6,7,u>: Cost 2 vsldoi12 RHS, <6,7,u,1> + 3249083295U, // <7,6,u,0>: Cost 2 vsldoi12 RHS, <6,u,0,1> + 3248935849U, // <7,6,u,1>: Cost 3 vsldoi12 RHS, <6,u,1,2> + 3249083314U, // <7,6,u,2>: Cost 3 vsldoi12 RHS, <6,u,2,2> + 3249083321U, // <7,6,u,3>: Cost 3 vsldoi12 RHS, <6,u,3,0> + 3249083335U, // <7,6,u,4>: Cost 2 vsldoi12 RHS, <6,u,4,5> + 3248935889U, // <7,6,u,5>: Cost 3 vsldoi12 RHS, <6,u,5,6> + 3248935736U, // <7,6,u,6>: Cost 2 vsldoi12 RHS, <6,6,6,6> + 3248935904U, // <7,6,u,7>: Cost 2 vsldoi12 RHS, <6,u,7,3> + 3249083367U, // <7,6,u,u>: Cost 2 vsldoi12 RHS, <6,u,u,1> + 2316062818U, // <7,7,0,0>: Cost 2 vmrglw <5,6,7,0>, <5,6,7,0> + 3248935930U, // <7,7,0,1>: Cost 2 vsldoi12 RHS, <7,0,1,2> + 3237434370U, // <7,7,0,2>: Cost 4 vsldoi12 <2,6,3,7>, <7,0,2,1> + 3389805050U, // <7,7,0,3>: Cost 3 vmrglw <5,6,7,0>, <6,2,7,3> + 3248935956U, // <7,7,0,4>: Cost 3 vsldoi12 RHS, <7,0,4,1> + 4067528802U, // <7,7,0,5>: Cost 3 vsldoi4 <6,7,7,0>, <5,6,7,0> + 4067529612U, // <7,7,0,6>: Cost 3 vsldoi4 <6,7,7,0>, <6,7,7,0> + 3389805378U, // <7,7,0,7>: Cost 3 vmrglw <5,6,7,0>, <6,6,7,7> + 3248935993U, // <7,7,0,u>: Cost 2 vsldoi12 RHS, <7,0,u,2> + 3248936001U, // <7,7,1,0>: Cost 4 vsldoi12 RHS, <7,1,0,1> + 3248936010U, // <7,7,1,1>: Cost 3 vsldoi12 RHS, <7,1,1,1> + 3248936021U, // <7,7,1,2>: Cost 3 vsldoi12 RHS, <7,1,2,3> + 3389813242U, // <7,7,1,3>: Cost 4 vmrglw <5,6,7,1>, <6,2,7,3> + 3248936037U, // <7,7,1,4>: Cost 4 vsldoi12 RHS, <7,1,4,1> + 3248936045U, // <7,7,1,5>: Cost 4 vsldoi12 RHS, <7,1,5,0> + 3231315063U, // <7,7,1,6>: Cost 4 vsldoi12 <1,6,1,7>, <7,1,6,1> + 3403085420U, // <7,7,1,7>: Cost 3 vmrglw <7,u,7,1>, <7,7,7,7> + 3248936075U, // <7,7,1,u>: Cost 3 vsldoi12 RHS, <7,1,u,3> + 3272823956U, // <7,7,2,0>: Cost 3 vsldoi12 RHS, <7,2,0,3> + 3248936093U, // <7,7,2,1>: Cost 4 vsldoi12 RHS, <7,2,1,3> + 3248936101U, // <7,7,2,2>: Cost 3 vsldoi12 RHS, <7,2,2,2> + 3248936108U, // <7,7,2,3>: Cost 3 vsldoi12 RHS, <7,2,3,0> + 3272823992U, // <7,7,2,4>: Cost 3 vsldoi12 RHS, <7,2,4,3> + 3248936129U, // <7,7,2,5>: Cost 4 vsldoi12 RHS, <7,2,5,3> + 3237434570U, // <7,7,2,6>: Cost 3 vsldoi12 <2,6,3,7>, <7,2,6,3> + 3261617363U, // <7,7,2,7>: Cost 3 vsldoi12 <6,6,7,7>, <7,2,7,3> + 3238761692U, // <7,7,2,u>: Cost 3 vsldoi12 <2,u,3,7>, <7,2,u,3> + 3248936163U, // <7,7,3,0>: Cost 3 vsldoi12 RHS, <7,3,0,1> + 3248936172U, // <7,7,3,1>: Cost 4 vsldoi12 RHS, <7,3,1,1> + 3237434618U, // <7,7,3,2>: Cost 4 vsldoi12 <2,6,3,7>, <7,3,2,6> + 2319405562U, // <7,7,3,3>: Cost 2 vmrglw <6,2,7,3>, <6,2,7,3> + 3248936203U, // <7,7,3,4>: Cost 3 vsldoi12 RHS, <7,3,4,5> + 3248936212U, // <7,7,3,5>: Cost 4 vsldoi12 RHS, <7,3,5,5> + 4183222967U, // <7,7,3,6>: Cost 3 vsldoi8 <3,6,7,7>, <3,6,7,7> + 3393147714U, // <7,7,3,7>: Cost 3 vmrglw <6,2,7,3>, <6,6,7,7> + 2319405562U, // <7,7,3,u>: Cost 2 vmrglw <6,2,7,3>, <6,2,7,3> + 3248936248U, // <7,7,4,0>: Cost 3 vsldoi12 RHS, <7,4,0,5> + 3248936254U, // <7,7,4,1>: Cost 4 vsldoi12 RHS, <7,4,1,2> + 4049643450U, // <7,7,4,2>: Cost 4 vsldoi4 <3,7,7,4>, <2,6,3,7> + 3389837818U, // <7,7,4,3>: Cost 3 vmrglw <5,6,7,4>, <6,2,7,3> + 2316095590U, // <7,7,4,4>: Cost 2 vmrglw <5,6,7,4>, <5,6,7,4> + 3248936294U, // <7,7,4,5>: Cost 2 vsldoi12 RHS, <7,4,5,6> + 4067562384U, // <7,7,4,6>: Cost 3 vsldoi4 <6,7,7,4>, <6,7,7,4> + 3389838146U, // <7,7,4,7>: Cost 3 vmrglw <5,6,7,4>, <6,6,7,7> + 3248936321U, // <7,7,4,u>: Cost 2 vsldoi12 RHS, <7,4,u,6> + 3248936325U, // <7,7,5,0>: Cost 4 vsldoi12 RHS, <7,5,0,1> + 3250926989U, // <7,7,5,1>: Cost 4 vsldoi12 RHS, <7,5,1,0> + 3248936345U, // <7,7,5,2>: Cost 4 vsldoi12 RHS, <7,5,2,3> + 3389846010U, // <7,7,5,3>: Cost 4 vmrglw <5,6,7,5>, <6,2,7,3> + 3248936365U, // <7,7,5,4>: Cost 4 vsldoi12 RHS, <7,5,4,5> + 3248936374U, // <7,7,5,5>: Cost 3 vsldoi12 RHS, <7,5,5,5> + 3248936385U, // <7,7,5,6>: Cost 3 vsldoi12 RHS, <7,5,6,7> + 3403118188U, // <7,7,5,7>: Cost 3 vmrglw <7,u,7,5>, <7,7,7,7> + 3249083859U, // <7,7,5,u>: Cost 3 vsldoi12 RHS, <7,5,u,7> + 4067573862U, // <7,7,6,0>: Cost 3 vsldoi4 <6,7,7,6>, LHS + 3248936421U, // <7,7,6,1>: Cost 4 vsldoi12 RHS, <7,6,1,7> + 3248936430U, // <7,7,6,2>: Cost 3 vsldoi12 RHS, <7,6,2,7> + 3389854202U, // <7,7,6,3>: Cost 3 vmrglw <5,6,7,6>, <6,2,7,3> + 4067577142U, // <7,7,6,4>: Cost 3 vsldoi4 <6,7,7,6>, RHS + 3248936457U, // <7,7,6,5>: Cost 4 vsldoi12 RHS, <7,6,5,7> + 3127399234U, // <7,7,6,6>: Cost 2 vsldoi8 <6,6,7,7>, <6,6,7,7> + 3248936468U, // <7,7,6,7>: Cost 3 vsldoi12 RHS, <7,6,7,0> + 3128726500U, // <7,7,6,u>: Cost 2 vsldoi8 <6,u,7,7>, <6,u,7,7> + 2999812198U, // <7,7,7,0>: Cost 2 vsldoi4 <7,7,7,7>, LHS + 3402470447U, // <7,7,7,1>: Cost 3 vmrglw <7,7,7,7>, <7,0,7,1> + 4201141459U, // <7,7,7,2>: Cost 3 vsldoi8 <6,6,7,7>, <7,2,7,3> + 3395834362U, // <7,7,7,3>: Cost 3 vmrglw <6,6,7,7>, <6,2,7,3> + 2999815478U, // <7,7,7,4>: Cost 2 vsldoi4 <7,7,7,7>, RHS + 3402470775U, // <7,7,7,5>: Cost 3 vmrglw <7,7,7,7>, <7,4,7,5> + 4201141778U, // <7,7,7,6>: Cost 3 vsldoi8 <6,6,7,7>, <7,6,6,7> + 1772539190U, // <7,7,7,7>: Cost 1 vspltisw3 RHS + 1772539190U, // <7,7,7,u>: Cost 1 vspltisw3 RHS + 2316062818U, // <7,7,u,0>: Cost 2 vmrglw <5,6,7,0>, <5,6,7,0> + 3249084034U, // <7,7,u,1>: Cost 2 vsldoi12 RHS, <7,u,1,2> + 3249084044U, // <7,7,u,2>: Cost 3 vsldoi12 RHS, <7,u,2,3> + 2319405562U, // <7,7,u,3>: Cost 2 vmrglw <6,2,7,3>, <6,2,7,3> + 2316095590U, // <7,7,u,4>: Cost 2 vmrglw <5,6,7,4>, <5,6,7,4> + 3249084074U, // <7,7,u,5>: Cost 2 vsldoi12 RHS, <7,u,5,6> + 3139344628U, // <7,7,u,6>: Cost 2 vsldoi8 , + 1772539190U, // <7,7,u,7>: Cost 1 vspltisw3 RHS + 1772539190U, // <7,7,u,u>: Cost 1 vspltisw3 RHS + 3248930816U, // <7,u,0,0>: Cost 2 vsldoi12 RHS, <0,0,0,0> + 3248936659U, // <7,u,0,1>: Cost 2 vsldoi12 RHS, + 3389802709U, // <7,u,0,2>: Cost 3 vmrglw <5,6,7,0>, <3,0,u,2> + 2316058780U, // <7,u,0,3>: Cost 2 vmrglw <5,6,7,0>, LHS + 3248936685U, // <7,u,0,4>: Cost 3 vsldoi12 RHS, + 2189383834U, // <7,u,0,5>: Cost 2 vmrghw <7,0,1,2>, RHS + 3389803037U, // <7,u,0,6>: Cost 3 vmrglw <5,6,7,0>, <3,4,u,6> + 2316062024U, // <7,u,0,7>: Cost 2 vmrglw <5,6,7,0>, RHS + 3248936722U, // <7,u,0,u>: Cost 2 vsldoi12 RHS, + 2993864806U, // <7,u,1,0>: Cost 2 vsldoi4 <6,7,u,1>, LHS + 3248931636U, // <7,u,1,1>: Cost 2 vsldoi12 RHS, <1,1,1,1> + 1101453102U, // <7,u,1,2>: Cost 1 vsldoi12 RHS, LHS + 4049693451U, // <7,u,1,3>: Cost 3 vsldoi4 <3,7,u,1>, <3,7,u,1> + 2993868086U, // <7,u,1,4>: Cost 2 vsldoi4 <6,7,u,1>, RHS + 3248936774U, // <7,u,1,5>: Cost 3 vsldoi12 RHS, + 2993869718U, // <7,u,1,6>: Cost 2 vsldoi4 <6,7,u,1>, <6,7,u,1> + 3249084249U, // <7,u,1,7>: Cost 3 vsldoi12 RHS, + 1101453156U, // <7,u,1,u>: Cost 1 vsldoi12 RHS, LHS + 3248936811U, // <7,u,2,0>: Cost 3 vsldoi12 RHS, + 3248936822U, // <7,u,2,1>: Cost 3 vsldoi12 RHS, + 3248932456U, // <7,u,2,2>: Cost 2 vsldoi12 RHS, <2,2,2,2> + 3248936837U, // <7,u,2,3>: Cost 2 vsldoi12 RHS, + 3248936849U, // <7,u,2,4>: Cost 3 vsldoi12 RHS, + 3248936858U, // <7,u,2,5>: Cost 3 vsldoi12 RHS, + 3237435299U, // <7,u,2,6>: Cost 3 vsldoi12 <2,6,3,7>, + 3249084332U, // <7,u,2,7>: Cost 2 vsldoi12 RHS, + 3248936882U, // <7,u,2,u>: Cost 2 vsldoi12 RHS, + 3248936892U, // <7,u,3,0>: Cost 2 vsldoi12 RHS, + 3248936901U, // <7,u,3,1>: Cost 3 vsldoi12 RHS, + 3237435347U, // <7,u,3,2>: Cost 3 vsldoi12 <2,6,3,7>, + 2319401116U, // <7,u,3,3>: Cost 2 vmrglw <6,2,7,3>, LHS + 3248936932U, // <7,u,3,4>: Cost 2 vsldoi12 RHS, + 3248936941U, // <7,u,3,5>: Cost 3 vsldoi12 RHS, + 4183231160U, // <7,u,3,6>: Cost 3 vsldoi8 <3,6,7,u>, <3,6,7,u> + 2319404360U, // <7,u,3,7>: Cost 2 vmrglw <6,2,7,3>, RHS + 3248936964U, // <7,u,3,u>: Cost 2 vsldoi12 RHS, + 3248936973U, // <7,u,4,0>: Cost 3 vsldoi12 RHS, + 2192365358U, // <7,u,4,1>: Cost 2 vmrghw <7,4,5,6>, LHS + 3389835477U, // <7,u,4,2>: Cost 3 vmrglw <5,6,7,4>, <3,0,u,2> + 2316091548U, // <7,u,4,3>: Cost 2 vmrglw <5,6,7,4>, LHS + 3248934096U, // <7,u,4,4>: Cost 2 vsldoi12 RHS, <4,4,4,4> + 3248937023U, // <7,u,4,5>: Cost 2 vsldoi12 RHS, + 3389835805U, // <7,u,4,6>: Cost 3 vmrglw <5,6,7,4>, <3,4,u,6> + 2316094792U, // <7,u,4,7>: Cost 2 vmrglw <5,6,7,4>, RHS + 3248937050U, // <7,u,4,u>: Cost 2 vsldoi12 RHS, + 2993897574U, // <7,u,5,0>: Cost 2 vsldoi4 <6,7,u,5>, LHS + 3250927718U, // <7,u,5,1>: Cost 3 vsldoi12 RHS, + 4049725370U, // <7,u,5,2>: Cost 3 vsldoi4 <3,7,u,5>, <2,6,3,7> + 4049726223U, // <7,u,5,3>: Cost 3 vsldoi4 <3,7,u,5>, <3,7,u,5> + 2993900854U, // <7,u,5,4>: Cost 2 vsldoi4 <6,7,u,5>, RHS + 3248934916U, // <7,u,5,5>: Cost 2 vsldoi12 RHS, <5,5,5,5> + 1101453466U, // <7,u,5,6>: Cost 1 vsldoi12 RHS, RHS + 3249084573U, // <7,u,5,7>: Cost 3 vsldoi12 RHS, + 1101453484U, // <7,u,5,u>: Cost 1 vsldoi12 RHS, RHS + 3248937135U, // <7,u,6,0>: Cost 3 vsldoi12 RHS, + 3248937150U, // <7,u,6,1>: Cost 3 vsldoi12 RHS, + 3124752895U, // <7,u,6,2>: Cost 2 vsldoi8 <6,2,7,u>, <6,2,7,u> + 3248937168U, // <7,u,6,3>: Cost 2 vsldoi12 RHS, + 3248937175U, // <7,u,6,4>: Cost 3 vsldoi12 RHS, + 3248937186U, // <7,u,6,5>: Cost 3 vsldoi12 RHS, + 3127407427U, // <7,u,6,6>: Cost 2 vsldoi8 <6,6,7,u>, <6,6,7,u> + 3249084660U, // <7,u,6,7>: Cost 2 vsldoi12 RHS, + 3248937213U, // <7,u,6,u>: Cost 2 vsldoi12 RHS, + 3249084672U, // <7,u,7,0>: Cost 2 vsldoi12 RHS, + 2194511662U, // <7,u,7,1>: Cost 2 vmrghw <7,7,7,7>, LHS + 3237804311U, // <7,u,7,2>: Cost 3 vsldoi12 <2,6,u,7>, + 2322088092U, // <7,u,7,3>: Cost 2 vmrglw <6,6,7,7>, LHS + 3249084712U, // <7,u,7,4>: Cost 2 vsldoi12 RHS, + 2194512026U, // <7,u,7,5>: Cost 2 vmrghw <7,7,7,7>, RHS + 3249084727U, // <7,u,7,6>: Cost 3 vsldoi12 RHS, + 1772539190U, // <7,u,7,7>: Cost 1 vspltisw3 RHS + 1772539190U, // <7,u,7,u>: Cost 1 vspltisw3 RHS + 3248937297U, // <7,u,u,0>: Cost 2 vsldoi12 RHS, + 3248937307U, // <7,u,u,1>: Cost 2 vsldoi12 RHS, + 1101453669U, // <7,u,u,2>: Cost 1 vsldoi12 RHS, LHS + 3248937323U, // <7,u,u,3>: Cost 2 vsldoi12 RHS, + 3248937337U, // <7,u,u,4>: Cost 2 vsldoi12 RHS, + 3248937347U, // <7,u,u,5>: Cost 2 vsldoi12 RHS, + 1101453709U, // <7,u,u,6>: Cost 1 vsldoi12 RHS, RHS + 1772539190U, // <7,u,u,7>: Cost 1 vspltisw3 RHS + 1101453723U, // <7,u,u,u>: Cost 1 vsldoi12 RHS, LHS + 1343012966U, // : Cost 1 vspltisw0 LHS + 3222102026U, // : Cost 2 vsldoi12 LHS, <0,0,1,1> + 4043786298U, // : Cost 3 vsldoi4 <2,u,0,0>, <2,u,0,0> + 3363338093U, // : Cost 3 vmrglw <1,2,u,0>, + 2958101814U, // : Cost 2 vsldoi4 <0,u,0,0>, RHS + 4072984674U, // : Cost 3 vsldoi4 <7,7,0,0>, <5,6,7,0> + 4067677086U, // : Cost 3 vsldoi4 <6,u,0,0>, <6,u,0,0> + 3363338421U, // : Cost 3 vmrglw <1,2,u,0>, + 1343012966U, // : Cost 1 vspltisw0 LHS + 2970050662U, // : Cost 2 vsldoi4 <2,u,0,1>, LHS + 1122353254U, // : Cost 1 vmrghw LHS, LHS + 1074618475U, // : Cost 1 vsldoi12 LHS, LHS + 4043794582U, // : Cost 3 vsldoi4 <2,u,0,1>, <3,0,1,2> + 2970053942U, // : Cost 2 vsldoi4 <2,u,0,1>, RHS + 4061712582U, // : Cost 3 vsldoi4 <5,u,0,1>, <5,u,0,1> + 2993943455U, // : Cost 2 vsldoi4 <6,u,0,1>, <6,u,0,1> + 4067685370U, // : Cost 3 vsldoi4 <6,u,0,1>, <7,0,1,2> + 1074618524U, // : Cost 1 vsldoi12 LHS, LHS + 4173284858U, // : Cost 3 vsldoi8 <2,0,u,0>, <2,0,u,0> + 2196807782U, // : Cost 2 vmrghw , LHS + 4168640104U, // : Cost 3 vsldoi8 <1,2,u,0>, <2,2,2,2> + 4168640166U, // : Cost 3 vsldoi8 <1,2,u,0>, <2,3,0,1> + 3270549842U, // : Cost 3 vmrghw , <0,4,1,5> + 3373451732U, // : Cost 3 vmrglw <3,0,1,2>, <3,4,0,5> + 4168640442U, // : Cost 3 vsldoi8 <1,2,u,0>, <2,6,3,7> + 4177930289U, // : Cost 3 vsldoi8 <2,7,u,0>, <2,7,u,0> + 2196808349U, // : Cost 2 vmrghw , LHS + 2282979328U, // : Cost 2 vmrglw LHS, <0,0,0,0> + 2282981030U, // : Cost 2 vmrglw LHS, <2,3,0,1> + 4180584821U, // : Cost 3 vsldoi8 <3,2,u,0>, <3,2,u,0> + 4168640924U, // : Cost 3 vsldoi8 <1,2,u,0>, <3,3,3,3> + 3356722857U, // : Cost 3 vmrglw LHS, <2,3,0,4> + 4073672802U, // : Cost 3 vsldoi4 <7,u,0,3>, <5,6,7,0> + 4168272504U, // : Cost 3 vsldoi8 <1,2,3,0>, <3,6,0,7> + 4073674362U, // : Cost 3 vsldoi4 <7,u,0,3>, <7,u,0,3> + 2282981037U, // : Cost 2 vmrglw LHS, <2,3,0,u> + 3363364864U, // : Cost 3 vmrglw <1,2,u,4>, <0,0,0,0> + 3222102354U, // : Cost 2 vsldoi12 LHS, <0,4,1,5> + 4043819070U, // : Cost 3 vsldoi4 <2,u,0,4>, <2,u,0,4> + 3242213632U, // : Cost 3 vmrghw <3,4,5,6>, <0,3,1,4> + 2150252882U, // : Cost 2 vmrghw <0,4,1,5>, <0,4,1,5> + 3094900022U, // : Cost 2 vsldoi8 <1,2,u,0>, RHS + 4067709858U, // : Cost 3 vsldoi4 <6,u,0,4>, <6,u,0,4> + 4189654472U, // : Cost 3 vsldoi8 <4,7,5,0>, <4,7,5,0> + 3226747281U, // : Cost 2 vsldoi12 LHS, <0,4,u,5> + 2199076864U, // : Cost 2 vmrghw RHS, <0,0,0,0> + 1125335142U, // : Cost 1 vmrghw RHS, LHS + 3272818861U, // : Cost 3 vmrghw RHS, <0,2,1,2> + 4049799960U, // : Cost 3 vsldoi4 <3,u,0,5>, <3,u,0,5> + 2199077202U, // : Cost 2 vmrghw RHS, <0,4,1,5> + 4195184644U, // : Cost 3 vsldoi8 <5,6,u,0>, <5,5,5,5> + 3121442923U, // : Cost 2 vsldoi8 <5,6,u,0>, <5,6,u,0> + 4073690748U, // : Cost 3 vsldoi4 <7,u,0,5>, <7,u,0,5> + 1125335709U, // : Cost 1 vmrghw RHS, LHS + 3376652288U, // : Cost 3 vmrglw <3,4,u,6>, <0,0,0,0> + 2199519334U, // : Cost 2 vmrghw , LHS + 4195185146U, // : Cost 3 vsldoi8 <5,6,u,0>, <6,2,7,3> + 4199166545U, // : Cost 3 vsldoi8 <6,3,u,0>, <6,3,u,0> + 3273261394U, // : Cost 3 vmrghw , <0,4,1,5> + 3255583140U, // : Cost 3 vmrghw <5,6,7,0>, <0,5,1,6> + 4195185464U, // : Cost 3 vsldoi8 <5,6,u,0>, <6,6,6,6> + 4195185486U, // : Cost 3 vsldoi8 <5,6,u,0>, <6,7,0,1> + 2199519901U, // : Cost 2 vmrghw , LHS + 2309554176U, // : Cost 2 vmrglw RHS, <0,0,0,0> + 2309555878U, // : Cost 2 vmrglw RHS, <2,3,0,1> + 4204475609U, // : Cost 3 vsldoi8 <7,2,u,0>, <7,2,u,0> + 4049816346U, // : Cost 3 vsldoi4 <3,u,0,7>, <3,u,0,7> + 4049816886U, // : Cost 3 vsldoi4 <3,u,0,7>, RHS + 3383298516U, // : Cost 3 vmrglw RHS, <3,4,0,5> + 4207130141U, // : Cost 3 vsldoi8 <7,6,u,0>, <7,6,u,0> + 3383298680U, // : Cost 3 vmrglw RHS, <3,6,0,7> + 2309555885U, // : Cost 2 vmrglw RHS, <2,3,0,u> + 1343012966U, // : Cost 1 vspltisw0 LHS + 1126998118U, // : Cost 1 vmrghw LHS, LHS + 1074619037U, // : Cost 1 vsldoi12 LHS, LHS + 4168644540U, // : Cost 3 vsldoi8 <1,2,u,0>, + 2970111286U, // : Cost 2 vsldoi4 <2,u,0,u>, RHS + 3094902938U, // : Cost 2 vsldoi8 <1,2,u,0>, RHS + 2994000806U, // : Cost 2 vsldoi4 <6,u,0,u>, <6,u,0,u> + 3383306872U, // : Cost 3 vmrglw RHS, <3,6,0,7> + 1074619091U, // : Cost 1 vsldoi12 LHS, LHS + 3087605833U, // : Cost 2 vsldoi8 <0,0,u,1>, <0,0,u,1> + 3092914278U, // : Cost 2 vsldoi8 <0,u,u,1>, LHS + 3361347283U, // : Cost 3 vmrglw <0,u,u,0>, + 4049832732U, // : Cost 3 vsldoi4 <3,u,1,0>, <3,u,1,0> + 4031917366U, // : Cost 3 vsldoi4 <0,u,1,0>, RHS + 3363332434U, // : Cost 3 vmrglw <1,2,u,0>, <0,4,1,5> + 4073722774U, // : Cost 3 vsldoi4 <7,u,1,0>, <6,7,u,1> + 4073723520U, // : Cost 3 vsldoi4 <7,u,1,0>, <7,u,1,0> + 3092914897U, // : Cost 2 vsldoi8 <0,u,u,1>, <0,u,u,1> + 2958181010U, // : Cost 2 vsldoi4 <0,u,1,1>, <0,u,1,1> + 1477230694U, // : Cost 1 vspltisw1 LHS + 2196095894U, // : Cost 2 vmrghw LHS, <1,2,3,0> + 4031924374U, // : Cost 3 vsldoi4 <0,u,1,1>, <3,0,1,2> + 2958183734U, // : Cost 2 vsldoi4 <0,u,1,1>, RHS + 3226747740U, // : Cost 3 vsldoi12 LHS, <1,1,5,5> + 4067759016U, // : Cost 3 vsldoi4 <6,u,1,1>, <6,u,1,1> + 3361355966U, // : Cost 3 vmrglw <0,u,u,1>, + 1477230694U, // : Cost 1 vspltisw1 LHS + 2976104550U, // : Cost 2 vsldoi4 <3,u,1,2>, LHS + 3226747783U, // : Cost 3 vsldoi12 LHS, <1,2,1,3> + 2155004822U, // : Cost 2 vmrghw <1,2,3,0>, <1,2,3,0> + 835584U, // : Cost 0 copy LHS + 2976107830U, // : Cost 2 vsldoi4 <3,u,1,2>, RHS + 3226747819U, // : Cost 3 vsldoi12 LHS, <1,2,5,3> + 4166657978U, // : Cost 3 vsldoi8 <0,u,u,1>, <2,6,3,7> + 2999998082U, // : Cost 2 vsldoi4 <7,u,1,2>, <7,u,1,2> + 835584U, // : Cost 0 copy LHS + 3356721161U, // : Cost 3 vmrglw LHS, <0,0,1,0> + 2282979338U, // : Cost 2 vmrglw LHS, <0,0,1,1> + 2282981526U, // : Cost 2 vmrglw LHS, <3,0,1,2> + 3356721326U, // : Cost 3 vmrglw LHS, <0,2,1,3> + 3356721165U, // : Cost 3 vmrglw LHS, <0,0,1,4> + 2282979666U, // : Cost 2 vmrglw LHS, <0,4,1,5> + 3356721329U, // : Cost 3 vmrglw LHS, <0,2,1,6> + 3361367247U, // : Cost 3 vmrglw LHS, <1,6,1,7> + 2282979345U, // : Cost 2 vmrglw LHS, <0,0,1,u> + 3111496621U, // : Cost 2 vsldoi8 <4,0,u,1>, <4,0,u,1> + 3363364874U, // : Cost 3 vmrglw <1,2,u,4>, <0,0,1,1> + 3363367062U, // : Cost 3 vmrglw <1,2,u,4>, <3,0,1,2> + 4049865504U, // : Cost 3 vsldoi4 <3,u,1,4>, <3,u,1,4> + 4031950134U, // : Cost 3 vsldoi4 <0,u,1,4>, RHS + 3092917558U, // : Cost 2 vsldoi8 <0,u,u,1>, RHS + 4073755542U, // : Cost 3 vsldoi4 <7,u,1,4>, <6,7,u,1> + 4073756292U, // : Cost 3 vsldoi4 <7,u,1,4>, <7,u,1,4> + 3092917801U, // : Cost 2 vsldoi8 <0,u,u,1>, RHS + 2958213782U, // : Cost 2 vsldoi4 <0,u,1,5>, <0,u,1,5> + 2199077684U, // : Cost 2 vmrghw RHS, <1,1,1,1> + 2199077782U, // : Cost 2 vmrghw RHS, <1,2,3,0> + 4031957142U, // : Cost 3 vsldoi4 <0,u,1,5>, <3,0,1,2> + 2958216502U, // : Cost 2 vsldoi4 <0,u,1,5>, RHS + 2284470610U, // : Cost 2 vmrglw <0,4,1,5>, <0,4,1,5> + 4190548066U, // : Cost 3 vsldoi8 <4,u,u,1>, <5,6,7,0> + 4079735802U, // : Cost 3 vsldoi4 , <7,0,1,2> + 2958219054U, // : Cost 2 vsldoi4 <0,u,1,5>, LHS + 4031963799U, // : Cost 3 vsldoi4 <0,u,1,6>, <0,u,1,6> + 3226748111U, // : Cost 3 vsldoi12 LHS, <1,6,1,7> + 3376654486U, // : Cost 3 vmrglw <3,4,u,6>, <3,0,1,2> + 4031965334U, // : Cost 4 vsldoi4 <0,u,1,6>, <3,0,1,2> + 4031966518U, // : Cost 3 vsldoi4 <0,u,1,6>, RHS + 3226748147U, // : Cost 3 vsldoi12 LHS, <1,6,5,7> + 4190548792U, // : Cost 3 vsldoi8 <4,u,u,1>, <6,6,6,6> + 3128087446U, // : Cost 2 vsldoi8 <6,7,u,1>, <6,7,u,1> + 3128751079U, // : Cost 2 vsldoi8 <6,u,u,1>, <6,u,u,1> + 4037943398U, // : Cost 3 vsldoi4 <1,u,1,7>, LHS + 2309554186U, // : Cost 2 vmrglw RHS, <0,0,1,1> + 2309556374U, // : Cost 2 vmrglw RHS, <3,0,1,2> + 3383296174U, // : Cost 3 vmrglw RHS, <0,2,1,3> + 4037946678U, // : Cost 3 vsldoi4 <1,u,1,7>, RHS + 2309554514U, // : Cost 2 vmrglw RHS, <0,4,1,5> + 3383296177U, // : Cost 3 vmrglw RHS, <0,2,1,6> + 3383296502U, // : Cost 3 vmrglw RHS, <0,6,1,7> + 2309554193U, // : Cost 2 vmrglw RHS, <0,0,1,u> + 2958238361U, // : Cost 2 vsldoi4 <0,u,1,u>, <0,u,1,u> + 1477230694U, // : Cost 1 vspltisw1 LHS + 2283022486U, // : Cost 2 vmrglw LHS, <3,0,1,2> + 835584U, // : Cost 0 copy LHS + 2958241078U, // : Cost 2 vsldoi4 <0,u,1,u>, RHS + 2283020626U, // : Cost 2 vmrglw LHS, <0,4,1,5> + 3356762289U, // : Cost 3 vmrglw LHS, <0,2,1,6> + 3000047240U, // : Cost 2 vsldoi4 <7,u,1,u>, <7,u,1,u> + 835584U, // : Cost 0 copy LHS + 4179271680U, // : Cost 3 vsldoi8 <3,0,u,2>, <0,0,0,0> + 3105529958U, // : Cost 2 vsldoi8 <3,0,u,2>, LHS + 3363333736U, // : Cost 3 vmrglw <1,2,u,0>, <2,2,2,2> + 2289590374U, // : Cost 2 vmrglw <1,2,u,0>, LHS + 4179272018U, // : Cost 3 vsldoi8 <3,0,u,2>, <0,4,1,5> + 3362964532U, // : Cost 3 vmrglw <1,2,3,0>, <1,4,2,5> + 3248940521U, // : Cost 3 vsldoi12 RHS, <2,0,6,1> + 4202644032U, // : Cost 3 vsldoi8 <7,0,1,2>, <0,7,1,0> + 2289590379U, // : Cost 2 vmrglw <1,2,u,0>, LHS + 4167328547U, // : Cost 3 vsldoi8 <1,0,u,2>, <1,0,u,2> + 4037969268U, // : Cost 3 vsldoi4 <1,u,2,1>, <1,u,2,1> + 2196096616U, // : Cost 2 vmrghw LHS, <2,2,2,2> + 2287607910U, // : Cost 2 vmrglw <0,u,u,1>, LHS + 4037971254U, // : Cost 3 vsldoi4 <1,u,2,1>, RHS + 3269838696U, // : Cost 3 vmrghw LHS, <2,5,3,6> + 2196096954U, // : Cost 2 vmrghw LHS, <2,6,3,7> + 3269838826U, // : Cost 3 vmrghw LHS, <2,7,0,1> + 2287607915U, // : Cost 2 vmrglw <0,u,u,1>, LHS + 2966224998U, // : Cost 2 vsldoi4 <2,2,2,2>, LHS + 4173964877U, // : Cost 3 vsldoi8 <2,1,u,2>, <2,1,u,2> + 1611448422U, // : Cost 1 vspltisw2 LHS + 3222103666U, // : Cost 2 vsldoi12 LHS, <2,2,3,3> + 2966228278U, // : Cost 2 vsldoi4 <2,2,2,2>, RHS + 3368879885U, // : Cost 3 vmrglw <2,2,2,2>, <2,4,2,5> + 4179273658U, // : Cost 3 vsldoi8 <3,0,u,2>, <2,6,3,7> + 3373971655U, // : Cost 3 vmrglw <3,0,u,2>, + 1611448422U, // : Cost 1 vspltisw2 LHS + 1884529309U, // : Cost 1 vsldoi4 LHS, LHS + 2958271284U, // : Cost 2 vsldoi4 LHS, <1,1,1,1> + 2282980968U, // : Cost 2 vmrglw LHS, <2,2,2,2> + 1209237606U, // : Cost 1 vmrglw LHS, LHS + 1884532022U, // : Cost 1 vsldoi4 LHS, RHS + 3006050308U, // : Cost 2 vsldoi4 LHS, <5,5,5,5> + 3006050810U, // : Cost 2 vsldoi4 LHS, <6,2,7,3> + 3006051322U, // : Cost 2 vsldoi4 LHS, <7,0,1,2> + 1209237611U, // : Cost 1 vmrglw LHS, LHS + 4185246638U, // : Cost 3 vsldoi8 <4,0,u,2>, <4,0,u,2> + 3223995939U, // : Cost 3 vmrghw <0,4,1,5>, <2,1,3,5> + 3363366504U, // : Cost 3 vmrglw <1,2,u,4>, <2,2,2,2> + 2289623142U, // : Cost 2 vmrglw <1,2,u,4>, LHS + 4203162832U, // : Cost 3 vsldoi8 <7,0,u,2>, <4,4,4,4> + 3105533238U, // : Cost 2 vsldoi8 <3,0,u,2>, RHS + 3248940849U, // : Cost 3 vsldoi12 RHS, <2,4,6,5> + 4202646984U, // : Cost 3 vsldoi8 <7,0,1,2>, <4,7,5,0> + 2289623147U, // : Cost 2 vmrglw <1,2,u,4>, LHS + 4038000742U, // : Cost 3 vsldoi4 <1,u,2,5>, LHS + 4038002040U, // : Cost 3 vsldoi4 <1,u,2,5>, <1,u,2,5> + 2199078504U, // : Cost 2 vmrghw RHS, <2,2,2,2> + 2287640678U, // : Cost 2 vmrglw <0,u,u,5>, LHS + 4038004022U, // : Cost 3 vsldoi4 <1,u,2,5>, RHS + 4203163652U, // : Cost 3 vsldoi8 <7,0,u,2>, <5,5,5,5> + 2199078842U, // : Cost 2 vmrghw RHS, <2,6,3,7> + 3272820714U, // : Cost 3 vmrghw RHS, <2,7,0,1> + 2287640683U, // : Cost 2 vmrglw <0,u,u,5>, LHS + 4043980902U, // : Cost 3 vsldoi4 <2,u,2,6>, LHS + 4197855665U, // : Cost 3 vsldoi8 <6,1,u,2>, <6,1,u,2> + 3370681960U, // : Cost 3 vmrglw <2,4,u,6>, <2,2,2,2> + 3222103994U, // : Cost 2 vsldoi12 LHS, <2,6,3,7> + 4043984182U, // : Cost 3 vsldoi4 <2,u,2,6>, RHS + 3370682125U, // : Cost 4 vmrglw <2,4,u,6>, <2,4,2,5> + 2163689402U, // : Cost 2 vmrghw <2,6,3,7>, <2,6,3,7> + 4201837463U, // : Cost 3 vsldoi8 <6,7,u,2>, <6,7,u,2> + 3222104039U, // : Cost 2 vsldoi12 LHS, <2,6,u,7> + 3129422905U, // : Cost 2 vsldoi8 <7,0,u,2>, <7,0,u,2> + 3383296748U, // : Cost 3 vmrglw RHS, <1,0,2,1> + 2309555816U, // : Cost 2 vmrglw RHS, <2,2,2,2> + 1235812454U, // : Cost 1 vmrglw RHS, LHS + 4043992374U, // : Cost 3 vsldoi4 <2,u,2,7>, RHS + 3383297076U, // : Cost 3 vmrglw RHS, <1,4,2,5> + 3383297725U, // : Cost 3 vmrglw RHS, <2,3,2,6> + 3383297240U, // : Cost 3 vmrglw RHS, <1,6,2,7> + 1235812459U, // : Cost 1 vmrglw RHS, LHS + 1884570274U, // : Cost 1 vsldoi4 LHS, LHS + 2958312244U, // : Cost 2 vsldoi4 LHS, <1,1,1,1> + 1611448422U, // : Cost 1 vspltisw2 LHS + 1209278566U, // : Cost 1 vmrglw LHS, LHS + 1884572982U, // : Cost 1 vsldoi4 LHS, RHS + 3105536154U, // : Cost 2 vsldoi8 <3,0,u,2>, RHS + 2200741818U, // : Cost 2 vmrghw LHS, <2,6,3,7> + 3006092282U, // : Cost 2 vsldoi4 LHS, <7,0,1,2> + 1209278571U, // : Cost 1 vmrglw LHS, LHS + 3088285696U, // : Cost 2 vsldoi8 LHS, <0,0,0,0> + 2014544028U, // : Cost 1 vsldoi8 LHS, LHS + 4162027693U, // : Cost 3 vsldoi8 LHS, <0,2,1,2> + 4162027772U, // : Cost 3 vsldoi8 LHS, <0,3,1,0> + 3088286034U, // : Cost 2 vsldoi8 LHS, <0,4,1,5> + 4209803730U, // : Cost 3 vsldoi8 LHS, <0,5,6,7> + 4067898297U, // : Cost 3 vsldoi4 <6,u,3,0>, <6,u,3,0> + 3363334074U, // : Cost 3 vmrglw <1,2,u,0>, <2,6,3,7> + 2014544541U, // : Cost 1 vsldoi8 LHS, LHS + 2196097174U, // : Cost 2 vmrghw LHS, <3,0,1,2> + 3088286516U, // : Cost 2 vsldoi8 LHS, <1,1,1,1> + 3088286614U, // : Cost 2 vsldoi8 LHS, <1,2,3,0> + 2196097436U, // : Cost 2 vmrghw LHS, <3,3,3,3> + 2196097538U, // : Cost 2 vmrghw LHS, <3,4,5,6> + 4166673519U, // : Cost 3 vsldoi8 LHS, <1,5,0,1> + 4166673615U, // : Cost 3 vsldoi8 LHS, <1,6,1,7> + 3361351610U, // : Cost 3 vmrglw <0,u,u,1>, <2,6,3,7> + 3088287100U, // : Cost 2 vsldoi8 LHS, <1,u,3,0> + 4162029050U, // : Cost 3 vsldoi8 LHS, <2,0,u,0> + 4162029087U, // : Cost 3 vsldoi8 LHS, <2,1,3,1> + 3088287336U, // : Cost 2 vsldoi8 LHS, <2,2,2,2> + 3088287398U, // : Cost 2 vsldoi8 LHS, <2,3,0,1> + 4162029379U, // : Cost 3 vsldoi8 LHS, <2,4,u,5> + 4162029461U, // : Cost 3 vsldoi8 LHS, <2,5,u,6> + 3088287674U, // : Cost 2 vsldoi8 LHS, <2,6,3,7> + 3373967290U, // : Cost 3 vmrglw <3,0,u,2>, <2,6,3,7> + 3088287803U, // : Cost 2 vsldoi8 LHS, <2,u,0,1> + 2282980246U, // : Cost 2 vmrglw LHS, <1,2,3,0> + 3356722071U, // : Cost 3 vmrglw LHS, <1,2,3,1> + 2970290264U, // : Cost 2 vsldoi4 <2,u,3,3>, <2,u,3,3> + 1745666150U, // : Cost 1 vspltisw3 LHS + 2282980250U, // : Cost 2 vmrglw LHS, <1,2,3,4> + 3356722723U, // : Cost 3 vmrglw LHS, <2,1,3,5> + 3356727422U, // : Cost 3 vmrglw LHS, + 2282981306U, // : Cost 2 vmrglw LHS, <2,6,3,7> + 1745666150U, // : Cost 1 vspltisw3 LHS + 2964324454U, // : Cost 2 vsldoi4 <1,u,3,4>, LHS + 2964325760U, // : Cost 2 vsldoi4 <1,u,3,4>, <1,u,3,4> + 4038067816U, // : Cost 3 vsldoi4 <1,u,3,4>, <2,2,2,2> + 3363366514U, // : Cost 3 vmrglw <1,2,u,4>, <2,2,3,3> + 2964327734U, // : Cost 2 vsldoi4 <1,u,3,4>, RHS + 2014547254U, // : Cost 1 vsldoi8 LHS, RHS + 4067931069U, // : Cost 3 vsldoi4 <6,u,3,4>, <6,u,3,4> + 3363366842U, // : Cost 3 vmrglw <1,2,u,4>, <2,6,3,7> + 2014547497U, // : Cost 1 vsldoi8 LHS, RHS + 2199079062U, // : Cost 2 vmrghw RHS, <3,0,1,2> + 4209806991U, // : Cost 3 vsldoi8 LHS, <5,1,0,1> + 4044048474U, // : Cost 3 vsldoi4 <2,u,3,5>, <2,u,3,5> + 2199079324U, // : Cost 2 vmrghw RHS, <3,3,3,3> + 2199079426U, // : Cost 2 vmrghw RHS, <3,4,5,6> + 3136065540U, // : Cost 2 vsldoi8 LHS, <5,5,5,5> + 3136065634U, // : Cost 2 vsldoi8 LHS, <5,6,7,0> + 3361384378U, // : Cost 3 vmrglw <0,u,u,5>, <2,6,3,7> + 3136065796U, // : Cost 2 vsldoi8 LHS, <5,u,7,0> + 4044054630U, // : Cost 3 vsldoi4 <2,u,3,6>, LHS + 4209807783U, // : Cost 3 vsldoi8 LHS, <6,1,7,1> + 3124785667U, // : Cost 2 vsldoi8 <6,2,u,3>, <6,2,u,3> + 4044057117U, // : Cost 3 vsldoi4 <2,u,3,6>, <3,4,u,6> + 4044057910U, // : Cost 3 vsldoi4 <2,u,3,6>, RHS + 4209808107U, // : Cost 3 vsldoi8 LHS, <6,5,7,1> + 3136066360U, // : Cost 2 vsldoi8 LHS, <6,6,6,6> + 3136066382U, // : Cost 2 vsldoi8 LHS, <6,7,0,1> + 3128767465U, // : Cost 2 vsldoi8 <6,u,u,3>, <6,u,u,3> + 2970320998U, // : Cost 2 vsldoi4 <2,u,3,7>, LHS + 4044063540U, // : Cost 3 vsldoi4 <2,u,3,7>, <1,1,1,1> + 2970323036U, // : Cost 2 vsldoi4 <2,u,3,7>, <2,u,3,7> + 2309555826U, // : Cost 2 vmrglw RHS, <2,2,3,3> + 2970324278U, // : Cost 2 vsldoi4 <2,u,3,7>, RHS + 3383297571U, // : Cost 3 vmrglw RHS, <2,1,3,5> + 3383297896U, // : Cost 3 vmrglw RHS, <2,5,3,6> + 2309556154U, // : Cost 2 vmrglw RHS, <2,6,3,7> + 2970326830U, // : Cost 2 vsldoi4 <2,u,3,7>, LHS + 3088291539U, // : Cost 2 vsldoi8 LHS, + 2014549806U, // : Cost 1 vsldoi8 LHS, LHS + 3088291720U, // : Cost 2 vsldoi8 LHS, + 1745666150U, // : Cost 1 vspltisw3 LHS + 3088291903U, // : Cost 2 vsldoi8 LHS, + 2014550170U, // : Cost 1 vsldoi8 LHS, RHS + 3088292048U, // : Cost 2 vsldoi8 LHS, + 2283022266U, // : Cost 2 vmrglw LHS, <2,6,3,7> + 2014550373U, // : Cost 1 vsldoi8 LHS, LHS + 2171751314U, // : Cost 2 vmrghw <4,0,5,1>, <4,0,5,1> + 3094929510U, // : Cost 2 vsldoi8 <1,2,u,4>, LHS + 4044081246U, // : Cost 3 vsldoi4 <2,u,4,0>, <2,u,4,0> + 4162846976U, // : Cost 3 vsldoi8 <0,3,1,4>, <0,3,1,4> + 4168671570U, // : Cost 3 vsldoi8 <1,2,u,4>, <0,4,1,5> + 3248941970U, // : Cost 2 vsldoi12 RHS, <4,0,5,1> + 4067972034U, // : Cost 3 vsldoi4 <6,u,4,0>, <6,u,4,0> + 3263122888U, // : Cost 3 vmrghw <7,0,1,2>, <4,7,5,0> + 3094930077U, // : Cost 2 vsldoi8 <1,2,u,4>, LHS + 2196097938U, // : Cost 2 vmrghw LHS, <4,0,5,1> + 4168672052U, // : Cost 3 vsldoi8 <1,2,u,4>, <1,1,1,1> + 3094930375U, // : Cost 2 vsldoi8 <1,2,u,4>, <1,2,u,4> + 4050062136U, // : Cost 3 vsldoi4 <3,u,4,1>, <3,u,4,1> + 2196098256U, // : Cost 2 vmrghw LHS, <4,4,4,4> + 1122356534U, // : Cost 1 vmrghw LHS, RHS + 3269840249U, // : Cost 3 vmrghw LHS, <4,6,5,2> + 4073952924U, // : Cost 3 vsldoi4 <7,u,4,1>, <7,u,4,1> + 1122356777U, // : Cost 1 vmrghw LHS, RHS + 3270552466U, // : Cost 3 vmrghw , <4,0,5,1> + 3228748772U, // : Cost 3 vmrghw <1,2,3,0>, <4,1,5,2> + 4168672872U, // : Cost 3 vsldoi8 <1,2,u,4>, <2,2,2,2> + 4168672934U, // : Cost 3 vsldoi8 <1,2,u,4>, <2,3,0,1> + 3397856464U, // : Cost 3 vmrglw <7,0,u,2>, <4,4,4,4> + 2196811062U, // : Cost 2 vmrghw , RHS + 4168673210U, // : Cost 3 vsldoi8 <1,2,u,4>, <2,6,3,7> + 4177963061U, // : Cost 3 vsldoi8 <2,7,u,4>, <2,7,u,4> + 2196811305U, // : Cost 2 vmrghw , RHS + 4168673430U, // : Cost 3 vsldoi8 <1,2,u,4>, <3,0,1,2> + 3356723376U, // : Cost 3 vmrglw LHS, <3,0,4,1> + 4180617593U, // : Cost 3 vsldoi8 <3,2,u,4>, <3,2,u,4> + 4168673692U, // : Cost 3 vsldoi8 <1,2,u,4>, <3,3,3,3> + 2330758352U, // : Cost 2 vmrglw LHS, <4,4,4,4> + 2282981070U, // : Cost 2 vmrglw LHS, <2,3,4,5> + 4168305308U, // : Cost 3 vsldoi8 <1,2,3,4>, <3,6,4,7> + 4073969310U, // : Cost 3 vsldoi4 <7,u,4,3>, <7,u,4,3> + 2282981073U, // : Cost 2 vmrglw LHS, <2,3,4,u> + 2982314086U, // : Cost 2 vsldoi4 <4,u,4,4>, LHS + 4044112839U, // : Cost 3 vsldoi4 <2,u,4,4>, <1,2,u,4> + 4044114018U, // : Cost 3 vsldoi4 <2,u,4,4>, <2,u,4,4> + 3363370897U, // : Cost 3 vmrglw <1,2,u,4>, + 1369886006U, // : Cost 1 vspltisw0 RHS + 3094932790U, // : Cost 2 vsldoi8 <1,2,u,4>, RHS + 4068004806U, // : Cost 3 vsldoi4 <6,u,4,4>, <6,u,4,4> + 3363371225U, // : Cost 3 vmrglw <1,2,u,4>, + 1369886006U, // : Cost 1 vspltisw0 RHS + 2970378342U, // : Cost 2 vsldoi4 <2,u,4,5>, LHS + 4038149514U, // : Cost 3 vsldoi4 <1,u,4,5>, <1,u,4,5> + 2970380387U, // : Cost 2 vsldoi4 <2,u,4,5>, <2,u,4,5> + 4044122262U, // : Cost 3 vsldoi4 <2,u,4,5>, <3,0,1,2> + 2970381622U, // : Cost 2 vsldoi4 <2,u,4,5>, RHS + 1125338422U, // : Cost 1 vmrghw RHS, RHS + 1074621750U, // : Cost 1 vsldoi12 LHS, RHS + 4068013050U, // : Cost 3 vsldoi4 <6,u,4,5>, <7,0,1,2> + 1074621768U, // : Cost 1 vsldoi12 LHS, RHS + 3273264018U, // : Cost 3 vmrghw , <4,0,5,1> + 3376433976U, // : Cost 3 vmrglw <3,4,5,6>, <3,u,4,1> + 4195217914U, // : Cost 3 vsldoi8 <5,6,u,4>, <6,2,7,3> + 4199199317U, // : Cost 3 vsldoi8 <6,3,u,4>, <6,3,u,4> + 4199862950U, // : Cost 3 vsldoi8 <6,4,u,4>, <6,4,u,4> + 2199522614U, // : Cost 2 vmrghw , RHS + 4195218232U, // : Cost 3 vsldoi8 <5,6,u,4>, <6,6,6,6> + 4195218254U, // : Cost 3 vsldoi8 <5,6,u,4>, <6,7,0,1> + 2199522857U, // : Cost 2 vmrghw , RHS + 4050108518U, // : Cost 3 vsldoi4 <3,u,4,7>, LHS + 4050109338U, // : Cost 3 vsldoi4 <3,u,4,7>, <1,2,3,4> + 4204508381U, // : Cost 3 vsldoi8 <7,2,u,4>, <7,2,u,4> + 4050111294U, // : Cost 3 vsldoi4 <3,u,4,7>, <3,u,4,7> + 2309557456U, // : Cost 2 vmrglw RHS, <4,4,4,4> + 2309555918U, // : Cost 2 vmrglw RHS, <2,3,4,5> + 4207162913U, // : Cost 3 vsldoi8 <7,6,u,4>, <7,6,u,4> + 3383298716U, // : Cost 3 vmrglw RHS, <3,6,4,7> + 2309555921U, // : Cost 2 vmrglw RHS, <2,3,4,u> + 2970402918U, // : Cost 2 vsldoi4 <2,u,4,u>, LHS + 3094935342U, // : Cost 2 vsldoi8 <1,2,u,4>, LHS + 2970404966U, // : Cost 2 vsldoi4 <2,u,4,u>, <2,u,4,u> + 4168677308U, // : Cost 3 vsldoi8 <1,2,u,4>, + 1369886006U, // : Cost 1 vspltisw0 RHS + 1127001398U, // : Cost 1 vmrghw LHS, RHS + 1074621993U, // : Cost 1 vsldoi12 LHS, RHS + 3383306908U, // : Cost 3 vmrglw RHS, <3,6,4,7> + 1074622011U, // : Cost 1 vsldoi12 LHS, RHS + 4166688768U, // : Cost 3 vsldoi8 <0,u,u,5>, <0,0,0,0> + 3092947046U, // : Cost 2 vsldoi8 <0,u,u,5>, LHS + 4050126578U, // : Cost 3 vsldoi4 <3,u,5,0>, <2,3,u,5> + 4050127680U, // : Cost 3 vsldoi4 <3,u,5,0>, <3,u,5,0> + 3089776978U, // : Cost 2 vsldoi8 <0,4,1,5>, <0,4,1,5> + 3389877466U, // : Cost 3 vmrglw <5,6,u,0>, <4,4,5,5> + 3363334658U, // : Cost 3 vmrglw <1,2,u,0>, <3,4,5,6> + 4074018468U, // : Cost 3 vsldoi4 <7,u,5,0>, <7,u,5,0> + 3092947669U, // : Cost 2 vsldoi8 <0,u,u,5>, <0,u,u,5> + 2982363238U, // : Cost 2 vsldoi4 <4,u,5,1>, LHS + 2311278106U, // : Cost 2 vmrglw <4,u,5,1>, <4,u,5,1> + 4166689686U, // : Cost 3 vsldoi8 <0,u,u,5>, <1,2,3,0> + 4056107158U, // : Cost 3 vsldoi4 <4,u,5,1>, <3,0,1,2> + 2982366746U, // : Cost 2 vsldoi4 <4,u,5,1>, <4,u,5,1> + 2196099076U, // : Cost 2 vmrghw LHS, <5,5,5,5> + 2196099170U, // : Cost 2 vmrghw LHS, <5,6,7,0> + 4056110074U, // : Cost 3 vsldoi4 <4,u,5,1>, <7,0,1,2> + 2982369070U, // : Cost 2 vsldoi4 <4,u,5,1>, LHS + 4050141286U, // : Cost 3 vsldoi4 <3,u,5,2>, LHS + 4173989456U, // : Cost 3 vsldoi8 <2,1,u,5>, <2,1,u,5> + 4166690408U, // : Cost 3 vsldoi8 <0,u,u,5>, <2,2,2,2> + 3101574898U, // : Cost 2 vsldoi8 <2,3,u,5>, <2,3,u,5> + 4175980355U, // : Cost 3 vsldoi8 <2,4,u,5>, <2,4,u,5> + 3250933519U, // : Cost 3 vsldoi12 RHS, <5,2,5,3> + 4166690746U, // : Cost 3 vsldoi8 <0,u,u,5>, <2,6,3,7> + 4177971254U, // : Cost 4 vsldoi8 <2,7,u,5>, <2,7,u,5> + 3104893063U, // : Cost 2 vsldoi8 <2,u,u,5>, <2,u,u,5> + 3361369058U, // : Cost 3 vmrglw LHS, <4,1,5,0> + 2330758034U, // : Cost 2 vmrglw LHS, <4,0,5,1> + 4056123086U, // : Cost 3 vsldoi4 <4,u,5,3>, <2,3,4,5> + 3361366955U, // : Cost 3 vmrglw LHS, <1,2,5,3> + 3361369062U, // : Cost 3 vmrglw LHS, <4,1,5,4> + 2330758362U, // : Cost 2 vmrglw LHS, <4,4,5,5> + 2282981890U, // : Cost 2 vmrglw LHS, <3,4,5,6> + 3361367283U, // : Cost 3 vmrglw LHS, <1,6,5,7> + 2282981892U, // : Cost 2 vmrglw LHS, <3,4,5,u> + 4050157670U, // : Cost 3 vsldoi4 <3,u,5,4>, LHS + 3389909906U, // : Cost 3 vmrglw <5,6,u,4>, <4,0,5,1> + 4050159346U, // : Cost 3 vsldoi4 <3,u,5,4>, <2,3,u,5> + 4050160452U, // : Cost 3 vsldoi4 <3,u,5,4>, <3,u,5,4> + 3114183925U, // : Cost 2 vsldoi8 <4,4,u,5>, <4,4,u,5> + 3092950326U, // : Cost 2 vsldoi8 <0,u,u,5>, RHS + 3361380415U, // : Cost 3 vmrglw <0,u,u,4>, + 4074051240U, // : Cost 3 vsldoi4 <7,u,5,4>, <7,u,5,4> + 3092950569U, // : Cost 2 vsldoi8 <0,u,u,5>, RHS + 2982396006U, // : Cost 2 vsldoi4 <4,u,5,5>, LHS + 4056138548U, // : Cost 3 vsldoi4 <4,u,5,5>, <1,1,1,1> + 4056139368U, // : Cost 3 vsldoi4 <4,u,5,5>, <2,2,2,2> + 3361388442U, // : Cost 3 vmrglw <0,u,u,5>, + 2982399518U, // : Cost 2 vsldoi4 <4,u,5,5>, <4,u,5,5> + 1504103734U, // : Cost 1 vspltisw1 RHS + 2199081058U, // : Cost 2 vmrghw RHS, <5,6,7,0> + 3361388770U, // : Cost 3 vmrglw <0,u,u,5>, + 1504103734U, // : Cost 1 vspltisw1 RHS + 2976432230U, // : Cost 2 vsldoi4 <3,u,5,6>, LHS + 4038231444U, // : Cost 3 vsldoi4 <1,u,5,6>, <1,u,5,6> + 4044204141U, // : Cost 3 vsldoi4 <2,u,5,6>, <2,u,5,6> + 2976435014U, // : Cost 2 vsldoi4 <3,u,5,6>, <3,u,5,6> + 2976435510U, // : Cost 2 vsldoi4 <3,u,5,6>, RHS + 3250933847U, // : Cost 3 vsldoi12 RHS, <5,6,5,7> + 2302691842U, // : Cost 2 vmrglw <3,4,5,6>, <3,4,5,6> + 27705344U, // : Cost 0 copy RHS + 27705344U, // : Cost 0 copy RHS + 4038238310U, // : Cost 3 vsldoi4 <1,u,5,7>, LHS + 2309557138U, // : Cost 2 vmrglw RHS, <4,0,5,1> + 3383298558U, // : Cost 3 vmrglw RHS, <3,4,5,2> + 3383296939U, // : Cost 3 vmrglw RHS, <1,2,5,3> + 4038241590U, // : Cost 3 vsldoi4 <1,u,5,7>, RHS + 2309557466U, // : Cost 2 vmrglw RHS, <4,4,5,5> + 2309556738U, // : Cost 2 vmrglw RHS, <3,4,5,6> + 3383297267U, // : Cost 3 vmrglw RHS, <1,6,5,7> + 2309556740U, // : Cost 2 vmrglw RHS, <3,4,5,u> + 2976448614U, // : Cost 2 vsldoi4 <3,u,5,u>, LHS + 3092952878U, // : Cost 2 vsldoi8 <0,u,u,5>, LHS + 4166694789U, // : Cost 3 vsldoi8 <0,u,u,5>, + 2976451400U, // : Cost 2 vsldoi4 <3,u,5,u>, <3,u,5,u> + 2976451894U, // : Cost 2 vsldoi4 <3,u,5,u>, RHS + 1504103734U, // : Cost 1 vspltisw1 RHS + 2283022850U, // : Cost 2 vmrglw LHS, <3,4,5,6> + 27705344U, // : Cost 0 copy RHS + 27705344U, // : Cost 0 copy RHS + 4181958656U, // : Cost 3 vsldoi8 <3,4,u,6>, <0,0,0,0> + 3108216934U, // : Cost 2 vsldoi8 <3,4,u,6>, LHS + 3269095930U, // : Cost 3 vmrghw , <6,2,7,3> + 4056173085U, // : Cost 3 vsldoi4 <4,u,6,0>, <3,4,u,6> + 4181958994U, // : Cost 3 vsldoi8 <3,4,u,6>, <0,4,1,5> + 3389804476U, // : Cost 3 vmrglw <5,6,7,0>, <5,4,6,5> + 3389879096U, // : Cost 3 vmrglw <5,6,u,0>, <6,6,6,6> + 2289593654U, // : Cost 2 vmrglw <1,2,u,0>, RHS + 2289593655U, // : Cost 2 vmrglw <1,2,u,0>, RHS + 4044234854U, // : Cost 3 vsldoi4 <2,u,6,1>, LHS + 4181959476U, // : Cost 3 vsldoi8 <3,4,u,6>, <1,1,1,1> + 2196099578U, // : Cost 2 vmrghw LHS, <6,2,7,3> + 3269841458U, // : Cost 3 vmrghw LHS, <6,3,4,5> + 4170015851U, // : Cost 3 vsldoi8 <1,4,u,6>, <1,4,u,6> + 4062155004U, // : Cost 3 vsldoi4 <5,u,6,1>, <5,u,6,1> + 2196099896U, // : Cost 2 vmrghw LHS, <6,6,6,6> + 2287611190U, // : Cost 2 vmrglw <0,u,u,1>, RHS + 2287611191U, // : Cost 2 vmrglw <0,u,u,1>, RHS + 4068130918U, // : Cost 3 vsldoi4 <6,u,6,2>, LHS + 4173997649U, // : Cost 4 vsldoi8 <2,1,u,6>, <2,1,u,6> + 2185187834U, // : Cost 2 vmrghw <6,2,7,3>, <6,2,7,3> + 4175324915U, // : Cost 3 vsldoi8 <2,3,u,6>, <2,3,u,6> + 4175988548U, // : Cost 3 vsldoi8 <2,4,u,6>, <2,4,u,6> + 4176652181U, // : Cost 3 vsldoi8 <2,5,u,6>, <2,5,u,6> + 4181960634U, // : Cost 3 vsldoi8 <3,4,u,6>, <2,6,3,7> + 2300226870U, // : Cost 2 vmrglw <3,0,u,2>, RHS + 2300226871U, // : Cost 2 vmrglw <3,0,u,2>, RHS + 4181960854U, // : Cost 3 vsldoi8 <3,4,u,6>, <3,0,1,2> + 3404498409U, // : Cost 3 vmrglw LHS, <2,0,6,1> + 3404498653U, // : Cost 3 vmrglw LHS, <2,3,6,2> + 3356723558U, // : Cost 3 vmrglw LHS, <3,2,6,3> + 3108219421U, // : Cost 2 vsldoi8 <3,4,u,6>, <3,4,u,6> + 4062171390U, // : Cost 3 vsldoi4 <5,u,6,3>, <5,u,6,3> + 2330759992U, // : Cost 2 vmrglw LHS, <6,6,6,6> + 1209240886U, // : Cost 1 vmrglw LHS, RHS + 1209240887U, // : Cost 1 vmrglw LHS, RHS + 4056203366U, // : Cost 3 vsldoi4 <4,u,6,4>, LHS + 3223998891U, // : Cost 3 vmrghw <0,4,1,5>, <6,1,7,5> + 3259929204U, // : Cost 3 vsldoi12 <6,4,2,u>, <6,4,2,u> + 4056205853U, // : Cost 3 vsldoi4 <4,u,6,4>, <3,4,u,6> + 4187933942U, // : Cost 3 vsldoi8 <4,4,u,6>, <4,4,u,6> + 3108220214U, // : Cost 2 vsldoi8 <3,4,u,6>, RHS + 3389911864U, // : Cost 3 vmrglw <5,6,u,4>, <6,6,6,6> + 2289626422U, // : Cost 2 vmrglw <1,2,u,4>, RHS + 2289626423U, // : Cost 2 vmrglw <1,2,u,4>, RHS + 4044267622U, // : Cost 3 vsldoi4 <2,u,6,5>, LHS + 3272823207U, // : Cost 3 vmrghw RHS, <6,1,7,1> + 2199081466U, // : Cost 2 vmrghw RHS, <6,2,7,3> + 3272823346U, // : Cost 3 vmrghw RHS, <6,3,4,5> + 4044270902U, // : Cost 3 vsldoi4 <2,u,6,5>, RHS + 4062187776U, // : Cost 3 vsldoi4 <5,u,6,5>, <5,u,6,5> + 2199081784U, // : Cost 2 vmrghw RHS, <6,6,6,6> + 2287643958U, // : Cost 2 vmrglw <0,u,u,5>, RHS + 2287643959U, // : Cost 2 vmrglw <0,u,u,5>, RHS + 2993094758U, // : Cost 2 vsldoi4 <6,6,6,6>, LHS + 3395752269U, // : Cost 3 vmrglw <6,6,6,6>, <6,0,6,1> + 4195234298U, // : Cost 3 vsldoi8 <5,6,u,6>, <6,2,7,3> + 4080110109U, // : Cost 3 vsldoi4 , <3,4,u,6> + 2993098038U, // : Cost 2 vsldoi4 <6,6,6,6>, RHS + 4200542969U, // : Cost 3 vsldoi8 <6,5,u,6>, <6,5,u,6> + 1638321462U, // : Cost 1 vspltisw2 RHS + 2302913846U, // : Cost 2 vmrglw <3,4,u,6>, RHS + 1638321462U, // : Cost 1 vspltisw2 RHS + 1908744294U, // : Cost 1 vsldoi4 RHS, LHS + 2982486836U, // : Cost 2 vsldoi4 RHS, <1,1,1,1> + 2982487656U, // : Cost 2 vsldoi4 RHS, <2,2,2,2> + 2982488214U, // : Cost 2 vsldoi4 RHS, <3,0,1,2> + 1908747817U, // : Cost 1 vsldoi4 RHS, RHS + 2982490116U, // : Cost 2 vsldoi4 RHS, <5,5,5,5> + 2309559096U, // : Cost 2 vmrglw RHS, <6,6,6,6> + 1235815734U, // : Cost 1 vmrglw RHS, RHS + 1235815735U, // : Cost 1 vmrglw RHS, RHS + 1908752486U, // : Cost 1 vsldoi4 RHS, LHS + 3108222766U, // : Cost 2 vsldoi8 <3,4,u,6>, LHS + 2982495848U, // : Cost 2 vsldoi4 RHS, <2,2,2,2> + 2982496406U, // : Cost 2 vsldoi4 RHS, <3,0,1,2> + 1908756010U, // : Cost 1 vsldoi4 RHS, RHS + 3108223130U, // : Cost 2 vsldoi8 <3,4,u,6>, RHS + 1638321462U, // : Cost 1 vspltisw2 RHS + 1209281846U, // : Cost 1 vmrglw LHS, RHS + 1209281847U, // : Cost 1 vmrglw LHS, RHS + 3114860544U, // : Cost 2 vsldoi8 RHS, <0,0,0,0> + 2041118822U, // : Cost 1 vsldoi8 RHS, LHS + 4188602541U, // : Cost 3 vsldoi8 RHS, <0,2,1,2> + 4188602620U, // : Cost 3 vsldoi8 RHS, <0,3,1,0> + 3114860882U, // : Cost 2 vsldoi8 RHS, <0,4,1,5> + 2988478724U, // : Cost 2 vsldoi4 <5,u,7,0>, <5,u,7,0> + 4188602870U, // : Cost 3 vsldoi8 RHS, <0,6,1,7> + 3389879106U, // : Cost 3 vmrglw <5,6,u,0>, <6,6,7,7> + 2041119389U, // : Cost 1 vsldoi8 RHS, LHS + 2196100090U, // : Cost 2 vmrghw LHS, <7,0,1,2> + 3114861364U, // : Cost 2 vsldoi8 RHS, <1,1,1,1> + 3114861462U, // : Cost 2 vsldoi8 RHS, <1,2,3,0> + 3385242106U, // : Cost 3 vmrglw <4,u,u,1>, <6,2,7,3> + 2196100454U, // : Cost 2 vmrghw LHS, <7,4,5,6> + 4188603503U, // : Cost 3 vsldoi8 RHS, <1,5,0,1> + 4171351310U, // : Cost 3 vsldoi8 <1,6,u,7>, <1,6,u,7> + 2196100716U, // : Cost 2 vmrghw LHS, <7,7,7,7> + 3114861948U, // : Cost 2 vsldoi8 RHS, <1,u,3,0> + 4188603837U, // : Cost 3 vsldoi8 RHS, <2,0,1,2> + 4188603935U, // : Cost 3 vsldoi8 RHS, <2,1,3,1> + 3114862184U, // : Cost 2 vsldoi8 RHS, <2,2,2,2> + 3114862246U, // : Cost 2 vsldoi8 RHS, <2,3,0,1> + 4188604173U, // : Cost 3 vsldoi8 RHS, <2,4,2,5> + 4188604264U, // : Cost 3 vsldoi8 RHS, <2,5,3,6> + 3103582183U, // : Cost 2 vsldoi8 <2,6,u,7>, <2,6,u,7> + 3397858114U, // : Cost 3 vmrglw <7,0,u,2>, <6,6,7,7> + 3104909449U, // : Cost 2 vsldoi8 <2,u,u,7>, <2,u,u,7> + 3114862742U, // : Cost 2 vsldoi8 RHS, <3,0,1,2> + 4188604646U, // : Cost 3 vsldoi8 RHS, <3,1,1,1> + 4177324395U, // : Cost 3 vsldoi8 <2,6,u,7>, <3,2,6,u> + 3114863004U, // : Cost 2 vsldoi8 RHS, <3,3,3,3> + 3114863106U, // : Cost 2 vsldoi8 RHS, <3,4,5,6> + 4188605010U, // : Cost 3 vsldoi8 RHS, <3,5,5,5> + 2994476000U, // : Cost 2 vsldoi4 <6,u,7,3>, <6,u,7,3> + 2330760002U, // : Cost 2 vmrglw LHS, <6,6,7,7> + 3114863390U, // : Cost 2 vsldoi8 RHS, <3,u,1,2> + 3114863506U, // : Cost 2 vsldoi8 RHS, <4,0,5,1> + 4188605386U, // : Cost 3 vsldoi8 RHS, <4,1,2,3> + 4188605493U, // : Cost 3 vsldoi8 RHS, <4,2,5,2> + 4188605572U, // : Cost 3 vsldoi8 RHS, <4,3,5,0> + 3114863824U, // : Cost 2 vsldoi8 RHS, <4,4,4,4> + 2041122120U, // : Cost 1 vsldoi8 RHS, RHS + 4188605817U, // : Cost 3 vsldoi8 RHS, <4,6,5,2> + 4188605896U, // : Cost 3 vsldoi8 RHS, <4,7,5,0> + 2041122345U, // : Cost 1 vsldoi8 RHS, RHS + 2199081978U, // : Cost 2 vmrghw RHS, <7,0,1,2> + 4190596751U, // : Cost 3 vsldoi8 RHS, <5,1,0,1> + 4188606206U, // : Cost 3 vsldoi8 RHS, <5,2,3,4> + 3385274874U, // : Cost 3 vmrglw <4,u,u,5>, <6,2,7,3> + 2199082342U, // : Cost 2 vmrghw RHS, <7,4,5,6> + 3114864644U, // : Cost 2 vsldoi8 RHS, <5,5,5,5> + 3114864738U, // : Cost 2 vsldoi8 RHS, <5,6,7,0> + 2199082604U, // : Cost 2 vmrghw RHS, <7,7,7,7> + 3114864900U, // : Cost 2 vsldoi8 RHS, <5,u,7,0> + 4188606753U, // : Cost 3 vsldoi8 RHS, <6,0,1,2> + 4188606887U, // : Cost 3 vsldoi8 RHS, <6,1,7,1> + 3114865146U, // : Cost 2 vsldoi8 RHS, <6,2,7,3> + 4188607026U, // : Cost 3 vsldoi8 RHS, <6,3,4,5> + 4188607117U, // : Cost 3 vsldoi8 RHS, <6,4,5,6> + 4188607211U, // : Cost 3 vsldoi8 RHS, <6,5,7,1> + 3114865464U, // : Cost 2 vsldoi8 RHS, <6,6,6,6> + 3114865486U, // : Cost 2 vsldoi8 RHS, <6,7,0,1> + 3114865567U, // : Cost 2 vsldoi8 RHS, <6,u,0,1> + 2309558370U, // : Cost 2 vmrglw RHS, <5,6,7,0> + 3383300195U, // : Cost 3 vmrglw RHS, <5,6,7,1> + 4050331578U, // : Cost 3 vsldoi4 <3,u,7,7>, <2,6,3,7> + 2309558778U, // : Cost 2 vmrglw RHS, <6,2,7,3> + 2309558374U, // : Cost 2 vmrglw RHS, <5,6,7,4> + 3383300199U, // : Cost 3 vmrglw RHS, <5,6,7,5> + 2994508772U, // : Cost 2 vsldoi4 <6,u,7,7>, <6,u,7,7> + 1772539190U, // : Cost 1 vspltisw3 RHS + 1772539190U, // : Cost 1 vspltisw3 RHS + 3114866387U, // : Cost 2 vsldoi8 RHS, + 2041124654U, // : Cost 1 vsldoi8 RHS, LHS + 3114866565U, // : Cost 2 vsldoi8 RHS, + 3114866620U, // : Cost 2 vsldoi8 RHS, + 3114866751U, // : Cost 2 vsldoi8 RHS, + 2041125018U, // : Cost 1 vsldoi8 RHS, RHS + 3114866896U, // : Cost 2 vsldoi8 RHS, + 1772539190U, // : Cost 1 vspltisw3 RHS + 2041125221U, // : Cost 1 vsldoi8 RHS, LHS + 1343012966U, // : Cost 1 vspltisw0 LHS + 2014584993U, // : Cost 1 vsldoi8 LHS, LHS + 4162068653U, // : Cost 3 vsldoi8 LHS, <0,2,1,2> + 2289590428U, // : Cost 2 vmrglw <1,2,u,0>, LHS + 3088326994U, // : Cost 2 vsldoi8 LHS, <0,4,1,5> + 2988552461U, // : Cost 2 vsldoi4 <5,u,u,0>, <5,u,u,0> + 3363334685U, // : Cost 3 vmrglw <1,2,u,0>, <3,4,u,6> + 2289593672U, // : Cost 2 vmrglw <1,2,u,0>, RHS + 2014585501U, // : Cost 1 vsldoi8 LHS, LHS + 2958697169U, // : Cost 2 vsldoi4 <0,u,u,1>, <0,u,u,1> + 1122359086U, // : Cost 1 vmrghw LHS, LHS + 1074624302U, // : Cost 1 vsldoi12 LHS, LHS + 2287607964U, // : Cost 2 vmrglw <0,u,u,1>, LHS + 2958699830U, // : Cost 2 vsldoi4 <0,u,u,1>, RHS + 1122359450U, // : Cost 1 vmrghw LHS, RHS + 2994533351U, // : Cost 2 vsldoi4 <6,u,u,1>, <6,u,u,1> + 2287611208U, // : Cost 2 vmrglw <0,u,u,1>, RHS + 1074624356U, // : Cost 1 vsldoi12 LHS, LHS + 2976620646U, // : Cost 2 vsldoi4 <3,u,u,2>, LHS + 2196813614U, // : Cost 2 vmrghw , LHS + 1611448422U, // : Cost 1 vspltisw2 LHS + 835584U, // : Cost 0 copy LHS + 2976623926U, // : Cost 2 vsldoi4 <3,u,u,2>, RHS + 2196813978U, // : Cost 2 vmrghw , RHS + 3088328634U, // : Cost 2 vsldoi8 LHS, <2,6,3,7> + 2300226888U, // : Cost 2 vmrglw <3,0,u,2>, RHS + 835584U, // : Cost 0 copy LHS + 1884971731U, // : Cost 1 vsldoi4 LHS, LHS + 2282981102U, // : Cost 2 vmrglw LHS, <2,3,u,1> + 2282981589U, // : Cost 2 vmrglw LHS, <3,0,u,2> + 1209237660U, // : Cost 1 vmrglw LHS, LHS + 1884974390U, // : Cost 1 vsldoi4 LHS, RHS + 2282981106U, // : Cost 2 vmrglw LHS, <2,3,u,5> + 2282981917U, // : Cost 2 vmrglw LHS, <3,4,u,6> + 1209240904U, // : Cost 1 vmrglw LHS, RHS + 1209237665U, // : Cost 1 vmrglw LHS, LHS + 2964693094U, // : Cost 2 vsldoi4 <1,u,u,4>, LHS + 2964694445U, // : Cost 2 vsldoi4 <1,u,u,4>, <1,u,u,4> + 3363367125U, // : Cost 3 vmrglw <1,2,u,4>, <3,0,u,2> + 2289623196U, // : Cost 2 vmrglw <1,2,u,4>, LHS + 1369886006U, // : Cost 1 vspltisw0 RHS + 2014588214U, // : Cost 1 vsldoi8 LHS, RHS + 3363367453U, // : Cost 3 vmrglw <1,2,u,4>, <3,4,u,6> + 2289626440U, // : Cost 2 vmrglw <1,2,u,4>, RHS + 2014588457U, // : Cost 1 vsldoi8 LHS, RHS + 2958729941U, // : Cost 2 vsldoi4 <0,u,u,5>, <0,u,u,5> + 1125340974U, // : Cost 1 vmrghw RHS, LHS + 2970675335U, // : Cost 2 vsldoi4 <2,u,u,5>, <2,u,u,5> + 2287640732U, // : Cost 2 vmrglw <0,u,u,5>, LHS + 2958732598U, // : Cost 2 vsldoi4 <0,u,u,5>, RHS + 1125341338U, // : Cost 1 vmrghw RHS, RHS + 1074624666U, // : Cost 1 vsldoi12 LHS, RHS + 2287643976U, // : Cost 2 vmrglw <0,u,u,5>, RHS + 1074624684U, // : Cost 1 vsldoi12 LHS, RHS + 2976653414U, // : Cost 2 vsldoi4 <3,u,u,6>, LHS + 2199525166U, // : Cost 2 vmrghw , LHS + 3114873338U, // : Cost 2 vsldoi8 RHS, <6,2,7,3> + 3222550736U, // : Cost 2 vsldoi12 LHS, + 2976656694U, // : Cost 2 vsldoi4 <3,u,u,6>, RHS + 2199525530U, // : Cost 2 vmrghw , RHS + 1638321462U, // : Cost 1 vspltisw2 RHS + 27705344U, // : Cost 0 copy RHS + 27705344U, // : Cost 0 copy RHS + 1908891750U, // : Cost 1 vsldoi4 RHS, LHS + 2309554249U, // : Cost 2 vmrglw RHS, <0,0,u,1> + 2970691721U, // : Cost 2 vsldoi4 <2,u,u,7>, <2,u,u,7> + 1235812508U, // : Cost 1 vmrglw RHS, LHS + 1908895291U, // : Cost 1 vsldoi4 RHS, RHS + 2309554577U, // : Cost 2 vmrglw RHS, <0,4,u,5> + 2309556765U, // : Cost 2 vmrglw RHS, <3,4,u,6> + 1235815752U, // : Cost 1 vmrglw RHS, RHS + 1235812513U, // : Cost 1 vmrglw RHS, LHS + 1885012696U, // : Cost 1 vsldoi4 LHS, LHS + 2014590766U, // : Cost 1 vsldoi8 LHS, LHS + 1074624869U, // : Cost 1 vsldoi12 LHS, LHS + 835584U, // : Cost 0 copy LHS + 1885015350U, // : Cost 1 vsldoi4 LHS, RHS + 2014591130U, // : Cost 1 vsldoi8 LHS, RHS + 1074624909U, // : Cost 1 vsldoi12 LHS, RHS + 27705344U, // : Cost 0 copy RHS + 835584U, // : Cost 0 copy LHS + 0 + }; From lattner at cs.uiuc.edu Sun Apr 16 19:46:21 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 16 Apr 2006 19:46:21 -0500 Subject: [llvm-commits] CVS: llvm/utils/llvmdo Message-ID: <200604170046.TAA19275@zion.cs.uiuc.edu> Changes in directory llvm/utils: llvmdo updated: 1.11 -> 1.12 --- Log message: PPCPerfectShuffle.h is autogenerated, don't include it in the LOC counts. --- Diffs of the changes: (+1 -0) llvmdo | 1 + 1 files changed, 1 insertion(+) Index: llvm/utils/llvmdo diff -u llvm/utils/llvmdo:1.11 llvm/utils/llvmdo:1.12 --- llvm/utils/llvmdo:1.11 Tue Mar 14 00:08:05 2006 +++ llvm/utils/llvmdo Sun Apr 16 19:46:09 2006 @@ -105,6 +105,7 @@ \! -name 'StackerParser.h' \ \! -name 'StackerParser.cpp' \ \! -name 'ConfigLexer.cpp' \ + \! -name 'PPCPerfectShuffle.h' \ -exec $PROGRAM "$@" {} \; \ \) else From lattner at cs.uiuc.edu Sun Apr 16 19:47:30 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 16 Apr 2006 19:47:30 -0500 Subject: [llvm-commits] CVS: llvm/utils/PerfectShuffle/PerfectShuffle.cpp Message-ID: <200604170047.TAA19357@zion.cs.uiuc.edu> Changes in directory llvm/utils/PerfectShuffle: PerfectShuffle.cpp updated: 1.3 -> 1.4 --- Log message: assign stable opcodes to the various altivec ops. --- Diffs of the changes: (+33 -14) PerfectShuffle.cpp | 47 +++++++++++++++++++++++++++++++++-------------- 1 files changed, 33 insertions(+), 14 deletions(-) Index: llvm/utils/PerfectShuffle/PerfectShuffle.cpp diff -u llvm/utils/PerfectShuffle/PerfectShuffle.cpp:1.3 llvm/utils/PerfectShuffle/PerfectShuffle.cpp:1.4 --- llvm/utils/PerfectShuffle/PerfectShuffle.cpp:1.3 Sun Apr 16 19:35:34 2006 +++ llvm/utils/PerfectShuffle/PerfectShuffle.cpp Sun Apr 16 19:47:18 2006 @@ -102,9 +102,8 @@ unsigned short OpNum; const char *Name; - Operator(unsigned short shufflemask, const char *name) - : ShuffleMask(shufflemask), Name(name) { - OpNum = TheOperators.size(); + Operator(unsigned short shufflemask, const char *name, unsigned opnum) + : ShuffleMask(shufflemask), OpNum(opnum), Name(name) { TheOperators.push_back(this); } ~Operator() { @@ -438,37 +437,57 @@ } +#define GENERATE_ALTIVEC + +#ifdef GENERATE_ALTIVEC ///===---------------------------------------------------------------------===// /// The altivec instruction definitions. This is the altivec-specific part of /// this file. ///===---------------------------------------------------------------------===// +// Note that the opcode numbers here must match those in the PPC backend. +enum { + OP_COPY = 0, // Copy, used for things like to say it is <0,1,2,3> + OP_VMRGHW, + OP_VMRGLW, + OP_VSPLTISW0, + OP_VSPLTISW1, + OP_VSPLTISW2, + OP_VSPLTISW3, + OP_VSLDOI4, + OP_VSLDOI8, + OP_VSLDOI12, +}; + struct vmrghw : public Operator { - vmrghw() : Operator(0x0415, "vmrghw") {} + vmrghw() : Operator(0x0415, "vmrghw", OP_VMRGHW) {} } the_vmrghw; struct vmrglw : public Operator { - vmrglw() : Operator(0x2637, "vmrglw") {} + vmrglw() : Operator(0x2637, "vmrglw", OP_VMRGLW) {} } the_vmrglw; template struct vspltisw : public Operator { - vspltisw(const char *N) : Operator(MakeMask(Elt, Elt, Elt, Elt), N) {} + vspltisw(const char *N, unsigned Opc) + : Operator(MakeMask(Elt, Elt, Elt, Elt), N, Opc) {} }; -vspltisw<0> the_vspltisw0("vspltisw0"); -vspltisw<1> the_vspltisw1("vspltisw1"); -vspltisw<2> the_vspltisw2("vspltisw2"); -vspltisw<3> the_vspltisw3("vspltisw3"); +vspltisw<0> the_vspltisw0("vspltisw0", OP_VSPLTISW0); +vspltisw<1> the_vspltisw1("vspltisw1", OP_VSPLTISW1); +vspltisw<2> the_vspltisw2("vspltisw2", OP_VSPLTISW2); +vspltisw<3> the_vspltisw3("vspltisw3", OP_VSPLTISW3); template struct vsldoi : public Operator { - vsldoi(const char *n) : Operator(MakeMask(N&7, (N+1)&7, (N+2)&7, (N+3)&7), n){ + vsldoi(const char *Name, unsigned Opc) + : Operator(MakeMask(N&7, (N+1)&7, (N+2)&7, (N+3)&7), Name, Opc) { } }; -vsldoi<1> the_vsldoi1("vsldoi4"); -vsldoi<2> the_vsldoi2("vsldoi8"); -vsldoi<3> the_vsldoi3("vsldoi12"); +vsldoi<1> the_vsldoi1("vsldoi4" , OP_VSLDOI4); +vsldoi<2> the_vsldoi2("vsldoi8" , OP_VSLDOI8); +vsldoi<3> the_vsldoi3("vsldoi12", OP_VSLDOI12); +#endif From lattner at cs.uiuc.edu Sun Apr 16 19:48:00 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 16 Apr 2006 19:48:00 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCPerfectShuffle.h Message-ID: <200604170048.TAA19369@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCPerfectShuffle.h updated: 1.1 -> 1.2 --- Log message: Increase the opcodes by one each to disambiguate COPY from VMRGHW. --- Diffs of the changes: (+6530 -6530) PPCPerfectShuffle.h |13060 ++++++++++++++++++++++++++-------------------------- 1 files changed, 6530 insertions(+), 6530 deletions(-) Index: llvm/lib/Target/PowerPC/PPCPerfectShuffle.h diff -u llvm/lib/Target/PowerPC/PPCPerfectShuffle.h:1.1 llvm/lib/Target/PowerPC/PPCPerfectShuffle.h:1.2 --- llvm/lib/Target/PowerPC/PPCPerfectShuffle.h:1.1 Sun Apr 16 19:37:02 2006 +++ llvm/lib/Target/PowerPC/PPCPerfectShuffle.h Sun Apr 16 19:47:48 2006 @@ -21,6565 +21,6565 @@ // This table is 6561*4 = 26244 bytes in size. static const unsigned PerfectShuffleTable[6561+1] = { - 1343012966U, // <0,0,0,0>: Cost 1 vspltisw0 LHS - 2147483750U, // <0,0,0,1>: Cost 2 vmrghw <0,0,0,0>, LHS - 4026533325U, // <0,0,0,2>: Cost 3 vsldoi4 <0,0,0,0>, <2,0,3,0> - 4044449931U, // <0,0,0,3>: Cost 3 vsldoi4 <3,0,0,0>, <3,0,0,0> - 2952793398U, // <0,0,0,4>: Cost 2 vsldoi4 <0,0,0,0>, RHS - 3355443529U, // <0,0,0,5>: Cost 3 vmrglw <0,0,0,0>, <0,4,0,5> - 4026536277U, // <0,0,0,6>: Cost 3 vsldoi4 <0,0,0,0>, <6,0,7,0> - 4068340719U, // <0,0,0,7>: Cost 3 vsldoi4 <7,0,0,0>, <7,0,0,0> - 1343012966U, // <0,0,0,u>: Cost 1 vspltisw0 LHS - 2148319242U, // <0,0,1,0>: Cost 2 vmrghw LHS, <0,0,1,1> - 1074577510U, // <0,0,1,1>: Cost 1 vmrghw LHS, LHS - 3228745830U, // <0,0,1,2>: Cost 2 vsldoi12 <1,2,3,0>, LHS - 3222503676U, // <0,0,1,3>: Cost 3 vmrghw LHS, <0,3,1,0> - 2148360530U, // <0,0,1,4>: Cost 2 vmrghw LHS, <0,4,1,5> - 3222061522U, // <0,0,1,5>: Cost 3 vmrghw LHS, <0,5,6,7> - 3222061549U, // <0,0,1,6>: Cost 3 vmrghw LHS, <0,6,0,7> - 4068348912U, // <0,0,1,7>: Cost 3 vsldoi4 <7,0,0,1>, <7,0,0,1> - 1074578077U, // <0,0,1,u>: Cost 1 vmrghw LHS, LHS - 4160751053U, // <0,0,2,0>: Cost 3 vsldoi8 <0,0,0,0>, <2,0,3,0> - 3222642790U, // <0,0,2,1>: Cost 3 vmrghw <0,2,1,2>, LHS - 3222642861U, // <0,0,2,2>: Cost 3 vmrghw <0,2,1,2>, <0,2,1,2> - 4174685861U, // <0,0,2,3>: Cost 3 vsldoi8 <2,3,0,0>, <2,3,0,0> - 3222643026U, // <0,0,2,4>: Cost 4 vmrghw <0,2,1,2>, <0,4,1,5> - 4160751459U, // <0,0,2,5>: Cost 4 vsldoi8 <0,0,0,0>, <2,5,3,1> - 4160751546U, // <0,0,2,6>: Cost 3 vsldoi8 <0,0,0,0>, <2,6,3,7> - 4160751594U, // <0,0,2,7>: Cost 4 vsldoi8 <0,0,0,0>, <2,7,0,1> - 3222643357U, // <0,0,2,u>: Cost 3 vmrghw <0,2,1,2>, LHS - 4178667659U, // <0,0,3,0>: Cost 3 vsldoi8 <3,0,0,0>, <3,0,0,0> - 3223289958U, // <0,0,3,1>: Cost 3 vmrghw <0,3,1,0>, LHS - 3240689928U, // <0,0,3,2>: Cost 4 vsldoi12 <3,2,3,0>, <0,3,2,3> - 3223290108U, // <0,0,3,3>: Cost 3 vmrghw <0,3,1,0>, <0,3,1,0> - 4160752130U, // <0,0,3,4>: Cost 3 vsldoi8 <0,0,0,0>, <3,4,5,6> - 4068364386U, // <0,0,3,5>: Cost 4 vsldoi4 <7,0,0,3>, <5,6,7,0> - 4180658808U, // <0,0,3,6>: Cost 4 vsldoi8 <3,3,0,0>, <3,6,0,7> - 3374713464U, // <0,0,3,7>: Cost 4 vmrglw <3,2,0,3>, <3,6,0,7> - 3223290525U, // <0,0,3,u>: Cost 3 vmrghw <0,3,1,0>, LHS - 3223994368U, // <0,0,4,0>: Cost 3 vmrghw <0,4,1,5>, <0,0,0,0> - 2150252646U, // <0,0,4,1>: Cost 2 vmrghw <0,4,1,5>, LHS - 3223994541U, // <0,0,4,2>: Cost 4 vmrghw <0,4,1,5>, <0,2,1,2> - 3223290212U, // <0,0,4,3>: Cost 4 vsldoi12 <0,3,1,0>, <0,4,3,5> - 2150252882U, // <0,0,4,4>: Cost 2 vmrghw <0,4,1,5>, <0,4,1,5> - 3087011126U, // <0,0,4,5>: Cost 2 vsldoi8 <0,0,0,0>, RHS - 4160753017U, // <0,0,4,6>: Cost 4 vsldoi8 <0,0,0,0>, <4,6,5,2> - 3250127240U, // <0,0,4,7>: Cost 4 vsldoi12 <4,7,5,0>, <0,4,7,5> - 2150253213U, // <0,0,4,u>: Cost 2 vmrghw <0,4,1,5>, LHS - 3358138368U, // <0,0,5,0>: Cost 3 vmrglw <0,4,0,5>, <0,0,0,0> - 3224658022U, // <0,0,5,1>: Cost 3 vmrghw <0,5,1,5>, LHS - 4160753387U, // <0,0,5,2>: Cost 4 vsldoi8 <0,0,0,0>, <5,2,1,3> - 3395966100U, // <0,0,5,3>: Cost 4 vmrglw <6,7,0,5>, <7,2,0,3> - 4207202236U, // <0,0,5,4>: Cost 4 vsldoi8 <7,7,0,0>, <5,4,6,5> - 3376056788U, // <0,0,5,5>: Cost 3 vmrglw <3,4,0,5>, <3,4,0,5> - 3255583186U, // <0,0,5,6>: Cost 3 vsldoi12 <5,6,7,0>, <0,5,6,7> - 3395966428U, // <0,0,5,7>: Cost 4 vmrglw <6,7,0,5>, <7,6,0,7> - 3256910308U, // <0,0,5,u>: Cost 3 vsldoi12 <5,u,7,0>, <0,5,u,7> - 4160754005U, // <0,0,6,0>: Cost 3 vsldoi8 <0,0,0,0>, <6,0,7,0> - 3225264230U, // <0,0,6,1>: Cost 3 vmrghw <0,6,0,7>, LHS - 4160754170U, // <0,0,6,2>: Cost 3 vsldoi8 <0,0,0,0>, <6,2,7,3> - 4160754226U, // <0,0,6,3>: Cost 4 vsldoi8 <0,0,0,0>, <6,3,4,5> - 4068388150U, // <0,0,6,4>: Cost 4 vsldoi4 <7,0,0,6>, RHS - 4160754411U, // <0,0,6,5>: Cost 4 vsldoi8 <0,0,0,0>, <6,5,7,1> - 4160754488U, // <0,0,6,6>: Cost 3 vsldoi8 <0,0,0,0>, <6,6,6,6> - 4201231181U, // <0,0,6,7>: Cost 3 vsldoi8 <6,7,0,0>, <6,7,0,0> - 4201894814U, // <0,0,6,u>: Cost 3 vsldoi8 <6,u,0,0>, <6,u,0,0> - 4202558447U, // <0,0,7,0>: Cost 3 vsldoi8 <7,0,0,0>, <7,0,0,0> - 3225944166U, // <0,0,7,1>: Cost 3 vmrghw <0,7,1,0>, LHS - 3264578124U, // <0,0,7,2>: Cost 4 vsldoi12 <7,2,3,0>, <0,7,2,3> - 3377400112U, // <0,0,7,3>: Cost 4 vmrglw <3,6,0,7>, <3,2,0,3> - 4160755046U, // <0,0,7,4>: Cost 3 vsldoi8 <0,0,0,0>, <7,4,5,6> - 4068397154U, // <0,0,7,5>: Cost 4 vsldoi4 <7,0,0,7>, <5,6,7,0> - 3267527284U, // <0,0,7,6>: Cost 4 vsldoi12 <7,6,7,0>, <0,7,6,7> - 3377400440U, // <0,0,7,7>: Cost 3 vmrglw <3,6,0,7>, <3,6,0,7> - 4202558447U, // <0,0,7,u>: Cost 3 vsldoi8 <7,0,0,0>, <7,0,0,0> - 1343012966U, // <0,0,u,0>: Cost 1 vspltisw0 LHS - 1079222374U, // <0,0,u,1>: Cost 1 vmrghw LHS, LHS - 3228746397U, // <0,0,u,2>: Cost 2 vsldoi12 <1,2,3,0>, LHS - 3226706172U, // <0,0,u,3>: Cost 3 vmrghw LHS, <0,3,1,0> - 2152964434U, // <0,0,u,4>: Cost 2 vmrghw LHS, <0,4,1,5> - 3087014042U, // <0,0,u,5>: Cost 2 vsldoi8 <0,0,0,0>, RHS - 3255583186U, // <0,0,u,6>: Cost 3 vsldoi12 <5,6,7,0>, <0,5,6,7> - 4068406263U, // <0,0,u,7>: Cost 3 vsldoi4 <7,0,0,u>, <7,0,0,u> - 1079222941U, // <0,0,u,u>: Cost 1 vmrghw LHS, LHS - 4174692352U, // <0,1,0,0>: Cost 3 vsldoi8 <2,3,0,1>, <0,0,0,0> - 3100950630U, // <0,1,0,1>: Cost 2 vsldoi8 <2,3,0,1>, LHS - 3228746476U, // <0,1,0,2>: Cost 3 vsldoi12 <1,2,3,0>, <1,0,2,1> - 4044523668U, // <0,1,0,3>: Cost 3 vsldoi4 <3,0,1,0>, <3,0,1,0> - 4170047826U, // <0,1,0,4>: Cost 3 vsldoi8 <1,5,0,1>, <0,4,1,5> - 3355443538U, // <0,1,0,5>: Cost 3 vmrglw <0,0,0,0>, <0,4,1,5> - 4174692854U, // <0,1,0,6>: Cost 3 vsldoi8 <2,3,0,1>, <0,6,1,7> - 4068414456U, // <0,1,0,7>: Cost 3 vsldoi4 <7,0,1,0>, <7,0,1,0> - 3100951197U, // <0,1,0,u>: Cost 2 vsldoi8 <2,3,0,1>, LHS - 2952871946U, // <0,1,1,0>: Cost 2 vsldoi4 <0,0,1,1>, <0,0,1,1> - 2148361012U, // <0,1,1,1>: Cost 2 vmrghw LHS, <1,1,1,1> - 2148361110U, // <0,1,1,2>: Cost 2 vmrghw LHS, <1,2,3,0> - 3369386158U, // <0,1,1,3>: Cost 3 vmrglw <2,3,0,1>, <0,2,1,3> - 2952875318U, // <0,1,1,4>: Cost 2 vsldoi4 <0,0,1,1>, RHS - 3364741458U, // <0,1,1,5>: Cost 3 vmrglw <1,5,0,1>, <0,4,1,5> - 4026618279U, // <0,1,1,6>: Cost 3 vsldoi4 <0,0,1,1>, <6,1,7,1> - 4026618864U, // <0,1,1,7>: Cost 3 vsldoi4 <0,0,1,1>, <7,0,0,1> - 2148803964U, // <0,1,1,u>: Cost 2 vmrghw LHS, <1,u,3,0> - 2970796134U, // <0,1,2,0>: Cost 2 vsldoi4 <3,0,1,2>, LHS - 4032594660U, // <0,1,2,1>: Cost 3 vsldoi4 <1,0,1,2>, <1,0,1,2> - 4174693992U, // <0,1,2,2>: Cost 3 vsldoi8 <2,3,0,1>, <2,2,2,2> + 1477230694U, // <0,0,0,0>: Cost 1 vspltisw0 LHS + 2281701478U, // <0,0,0,1>: Cost 2 vmrghw <0,0,0,0>, LHS + 4160751053U, // <0,0,0,2>: Cost 3 vsldoi4 <0,0,0,0>, <2,0,3,0> + 4178667659U, // <0,0,0,3>: Cost 3 vsldoi4 <3,0,0,0>, <3,0,0,0> + 3087011126U, // <0,0,0,4>: Cost 2 vsldoi4 <0,0,0,0>, RHS + 3489661257U, // <0,0,0,5>: Cost 3 vmrglw <0,0,0,0>, <0,4,0,5> + 4160754005U, // <0,0,0,6>: Cost 3 vsldoi4 <0,0,0,0>, <6,0,7,0> + 4202558447U, // <0,0,0,7>: Cost 3 vsldoi4 <7,0,0,0>, <7,0,0,0> + 1477230694U, // <0,0,0,u>: Cost 1 vspltisw0 LHS + 2282536970U, // <0,0,1,0>: Cost 2 vmrghw LHS, <0,0,1,1> + 1208795238U, // <0,0,1,1>: Cost 1 vmrghw LHS, LHS + 3362963558U, // <0,0,1,2>: Cost 2 vsldoi12 <1,2,3,0>, LHS + 3356721404U, // <0,0,1,3>: Cost 3 vmrghw LHS, <0,3,1,0> + 2282578258U, // <0,0,1,4>: Cost 2 vmrghw LHS, <0,4,1,5> + 3356279250U, // <0,0,1,5>: Cost 3 vmrghw LHS, <0,5,6,7> + 3356279277U, // <0,0,1,6>: Cost 3 vmrghw LHS, <0,6,0,7> + 4202566640U, // <0,0,1,7>: Cost 3 vsldoi4 <7,0,0,1>, <7,0,0,1> + 1208795805U, // <0,0,1,u>: Cost 1 vmrghw LHS, LHS + 3221226957U, // <0,0,2,0>: Cost 3 vsldoi8 <0,0,0,0>, <2,0,3,0> + 3356860518U, // <0,0,2,1>: Cost 3 vmrghw <0,2,1,2>, LHS + 3356860589U, // <0,0,2,2>: Cost 3 vmrghw <0,2,1,2>, <0,2,1,2> + 3235161765U, // <0,0,2,3>: Cost 3 vsldoi8 <2,3,0,0>, <2,3,0,0> + 3356860754U, // <0,0,2,4>: Cost 4 vmrghw <0,2,1,2>, <0,4,1,5> + 3221227363U, // <0,0,2,5>: Cost 4 vsldoi8 <0,0,0,0>, <2,5,3,1> + 3221227450U, // <0,0,2,6>: Cost 3 vsldoi8 <0,0,0,0>, <2,6,3,7> + 3221227498U, // <0,0,2,7>: Cost 4 vsldoi8 <0,0,0,0>, <2,7,0,1> + 3356861085U, // <0,0,2,u>: Cost 3 vmrghw <0,2,1,2>, LHS + 3239143563U, // <0,0,3,0>: Cost 3 vsldoi8 <3,0,0,0>, <3,0,0,0> + 3357507686U, // <0,0,3,1>: Cost 3 vmrghw <0,3,1,0>, LHS + 3374907656U, // <0,0,3,2>: Cost 4 vsldoi12 <3,2,3,0>, <0,3,2,3> + 3357507836U, // <0,0,3,3>: Cost 3 vmrghw <0,3,1,0>, <0,3,1,0> + 3221228034U, // <0,0,3,4>: Cost 3 vsldoi8 <0,0,0,0>, <3,4,5,6> + 4202582114U, // <0,0,3,5>: Cost 4 vsldoi4 <7,0,0,3>, <5,6,7,0> + 3241134712U, // <0,0,3,6>: Cost 4 vsldoi8 <3,3,0,0>, <3,6,0,7> + 3508931192U, // <0,0,3,7>: Cost 4 vmrglw <3,2,0,3>, <3,6,0,7> + 3357508253U, // <0,0,3,u>: Cost 3 vmrghw <0,3,1,0>, LHS + 3358212096U, // <0,0,4,0>: Cost 3 vmrghw <0,4,1,5>, <0,0,0,0> + 2284470374U, // <0,0,4,1>: Cost 2 vmrghw <0,4,1,5>, LHS + 3358212269U, // <0,0,4,2>: Cost 4 vmrghw <0,4,1,5>, <0,2,1,2> + 3357507940U, // <0,0,4,3>: Cost 4 vsldoi12 <0,3,1,0>, <0,4,3,5> + 2284470610U, // <0,0,4,4>: Cost 2 vmrghw <0,4,1,5>, <0,4,1,5> + 3221228854U, // <0,0,4,5>: Cost 2 vsldoi8 <0,0,0,0>, RHS + 3221228921U, // <0,0,4,6>: Cost 4 vsldoi8 <0,0,0,0>, <4,6,5,2> + 3384344968U, // <0,0,4,7>: Cost 4 vsldoi12 <4,7,5,0>, <0,4,7,5> + 2284470941U, // <0,0,4,u>: Cost 2 vmrghw <0,4,1,5>, LHS + 3492356096U, // <0,0,5,0>: Cost 3 vmrglw <0,4,0,5>, <0,0,0,0> + 3358875750U, // <0,0,5,1>: Cost 3 vmrghw <0,5,1,5>, LHS + 3221229291U, // <0,0,5,2>: Cost 4 vsldoi8 <0,0,0,0>, <5,2,1,3> + 3530183828U, // <0,0,5,3>: Cost 4 vmrglw <6,7,0,5>, <7,2,0,3> + 3267678140U, // <0,0,5,4>: Cost 4 vsldoi8 <7,7,0,0>, <5,4,6,5> + 3510274516U, // <0,0,5,5>: Cost 3 vmrglw <3,4,0,5>, <3,4,0,5> + 3389800914U, // <0,0,5,6>: Cost 3 vsldoi12 <5,6,7,0>, <0,5,6,7> + 3530184156U, // <0,0,5,7>: Cost 4 vmrglw <6,7,0,5>, <7,6,0,7> + 3391128036U, // <0,0,5,u>: Cost 3 vsldoi12 <5,u,7,0>, <0,5,u,7> + 3221229909U, // <0,0,6,0>: Cost 3 vsldoi8 <0,0,0,0>, <6,0,7,0> + 3359481958U, // <0,0,6,1>: Cost 3 vmrghw <0,6,0,7>, LHS + 3221230074U, // <0,0,6,2>: Cost 3 vsldoi8 <0,0,0,0>, <6,2,7,3> + 3221230130U, // <0,0,6,3>: Cost 4 vsldoi8 <0,0,0,0>, <6,3,4,5> + 4202605878U, // <0,0,6,4>: Cost 4 vsldoi4 <7,0,0,6>, RHS + 3221230315U, // <0,0,6,5>: Cost 4 vsldoi8 <0,0,0,0>, <6,5,7,1> + 3221230392U, // <0,0,6,6>: Cost 3 vsldoi8 <0,0,0,0>, <6,6,6,6> + 3261707085U, // <0,0,6,7>: Cost 3 vsldoi8 <6,7,0,0>, <6,7,0,0> + 3262370718U, // <0,0,6,u>: Cost 3 vsldoi8 <6,u,0,0>, <6,u,0,0> + 3263034351U, // <0,0,7,0>: Cost 3 vsldoi8 <7,0,0,0>, <7,0,0,0> + 3360161894U, // <0,0,7,1>: Cost 3 vmrghw <0,7,1,0>, LHS + 3398795852U, // <0,0,7,2>: Cost 4 vsldoi12 <7,2,3,0>, <0,7,2,3> + 3511617840U, // <0,0,7,3>: Cost 4 vmrglw <3,6,0,7>, <3,2,0,3> + 3221230950U, // <0,0,7,4>: Cost 3 vsldoi8 <0,0,0,0>, <7,4,5,6> + 4202614882U, // <0,0,7,5>: Cost 4 vsldoi4 <7,0,0,7>, <5,6,7,0> + 3401745012U, // <0,0,7,6>: Cost 4 vsldoi12 <7,6,7,0>, <0,7,6,7> + 3511618168U, // <0,0,7,7>: Cost 3 vmrglw <3,6,0,7>, <3,6,0,7> + 3263034351U, // <0,0,7,u>: Cost 3 vsldoi8 <7,0,0,0>, <7,0,0,0> + 1477230694U, // <0,0,u,0>: Cost 1 vspltisw0 LHS + 1213440102U, // <0,0,u,1>: Cost 1 vmrghw LHS, LHS + 3362964125U, // <0,0,u,2>: Cost 2 vsldoi12 <1,2,3,0>, LHS + 3360923900U, // <0,0,u,3>: Cost 3 vmrghw LHS, <0,3,1,0> + 2287182162U, // <0,0,u,4>: Cost 2 vmrghw LHS, <0,4,1,5> + 3221231770U, // <0,0,u,5>: Cost 2 vsldoi8 <0,0,0,0>, RHS + 3389800914U, // <0,0,u,6>: Cost 3 vsldoi12 <5,6,7,0>, <0,5,6,7> + 4202623991U, // <0,0,u,7>: Cost 3 vsldoi4 <7,0,0,u>, <7,0,0,u> + 1213440669U, // <0,0,u,u>: Cost 1 vmrghw LHS, LHS + 3235168256U, // <0,1,0,0>: Cost 3 vsldoi8 <2,3,0,1>, <0,0,0,0> + 3235168358U, // <0,1,0,1>: Cost 2 vsldoi8 <2,3,0,1>, LHS + 3362964204U, // <0,1,0,2>: Cost 3 vsldoi12 <1,2,3,0>, <1,0,2,1> + 4178741396U, // <0,1,0,3>: Cost 3 vsldoi4 <3,0,1,0>, <3,0,1,0> + 3230523730U, // <0,1,0,4>: Cost 3 vsldoi8 <1,5,0,1>, <0,4,1,5> + 3489661266U, // <0,1,0,5>: Cost 3 vmrglw <0,0,0,0>, <0,4,1,5> + 3235168758U, // <0,1,0,6>: Cost 3 vsldoi8 <2,3,0,1>, <0,6,1,7> + 4202632184U, // <0,1,0,7>: Cost 3 vsldoi4 <7,0,1,0>, <7,0,1,0> + 3235168925U, // <0,1,0,u>: Cost 2 vsldoi8 <2,3,0,1>, LHS + 3087089674U, // <0,1,1,0>: Cost 2 vsldoi4 <0,0,1,1>, <0,0,1,1> + 2282578740U, // <0,1,1,1>: Cost 2 vmrghw LHS, <1,1,1,1> + 2282578838U, // <0,1,1,2>: Cost 2 vmrghw LHS, <1,2,3,0> + 3503603886U, // <0,1,1,3>: Cost 3 vmrglw <2,3,0,1>, <0,2,1,3> + 3087093046U, // <0,1,1,4>: Cost 2 vsldoi4 <0,0,1,1>, RHS + 3498959186U, // <0,1,1,5>: Cost 3 vmrglw <1,5,0,1>, <0,4,1,5> + 4160836007U, // <0,1,1,6>: Cost 3 vsldoi4 <0,0,1,1>, <6,1,7,1> + 4160836592U, // <0,1,1,7>: Cost 3 vsldoi4 <0,0,1,1>, <7,0,0,1> + 2283021692U, // <0,1,1,u>: Cost 2 vmrghw LHS, <1,u,3,0> + 3105013862U, // <0,1,2,0>: Cost 2 vsldoi4 <3,0,1,2>, LHS + 4166812388U, // <0,1,2,1>: Cost 3 vsldoi4 <1,0,1,2>, <1,0,1,2> + 3235169896U, // <0,1,2,2>: Cost 3 vsldoi8 <2,3,0,1>, <2,2,2,2> 835584U, // <0,1,2,3>: Cost 0 copy LHS - 2970799414U, // <0,1,2,4>: Cost 2 vsldoi4 <3,0,1,2>, RHS - 4056485448U, // <0,1,2,5>: Cost 3 vsldoi4 <5,0,1,2>, <5,0,1,2> - 4174694330U, // <0,1,2,6>: Cost 3 vsldoi8 <2,3,0,1>, <2,6,3,7> - 2994689018U, // <0,1,2,7>: Cost 2 vsldoi4 <7,0,1,2>, <7,0,1,2> + 3105017142U, // <0,1,2,4>: Cost 2 vsldoi4 <3,0,1,2>, RHS + 4190703176U, // <0,1,2,5>: Cost 3 vsldoi4 <5,0,1,2>, <5,0,1,2> + 3235170234U, // <0,1,2,6>: Cost 3 vsldoi8 <2,3,0,1>, <2,6,3,7> + 3128906746U, // <0,1,2,7>: Cost 2 vsldoi4 <7,0,1,2>, <7,0,1,2> 835584U, // <0,1,2,u>: Cost 0 copy LHS - 4174694548U, // <0,1,3,0>: Cost 3 vsldoi8 <2,3,0,1>, <3,0,1,0> - 3223290676U, // <0,1,3,1>: Cost 4 vmrghw <0,3,1,0>, <1,1,1,1> - 4174694728U, // <0,1,3,2>: Cost 3 vsldoi8 <2,3,0,1>, <3,2,3,0> - 4174694812U, // <0,1,3,3>: Cost 3 vsldoi8 <2,3,0,1>, <3,3,3,3> - 4174694914U, // <0,1,3,4>: Cost 3 vsldoi8 <2,3,0,1>, <3,4,5,6> - 3228746745U, // <0,1,3,5>: Cost 4 vsldoi12 <1,2,3,0>, <1,3,5,0> - 4201237168U, // <0,1,3,6>: Cost 3 vsldoi8 <6,7,0,1>, <3,6,7,0> - 4183321283U, // <0,1,3,7>: Cost 3 vsldoi8 <3,7,0,1>, <3,7,0,1> - 4174695198U, // <0,1,3,u>: Cost 3 vsldoi8 <2,3,0,1>, <3,u,1,2> - 4044554342U, // <0,1,4,0>: Cost 3 vsldoi4 <3,0,1,4>, LHS - 3223995188U, // <0,1,4,1>: Cost 3 vmrghw <0,4,1,5>, <1,1,1,1> - 3223995286U, // <0,1,4,2>: Cost 3 vmrghw <0,4,1,5>, <1,2,3,0> - 4044556440U, // <0,1,4,3>: Cost 3 vsldoi4 <3,0,1,4>, <3,0,1,4> - 4044557622U, // <0,1,4,4>: Cost 3 vsldoi4 <3,0,1,4>, RHS - 3100953910U, // <0,1,4,5>: Cost 2 vsldoi8 <2,3,0,1>, RHS - 4068447054U, // <0,1,4,6>: Cost 3 vsldoi4 <7,0,1,4>, <6,7,0,1> - 4068447228U, // <0,1,4,7>: Cost 3 vsldoi4 <7,0,1,4>, <7,0,1,4> - 3100954153U, // <0,1,4,u>: Cost 2 vsldoi8 <2,3,0,1>, RHS - 3228746863U, // <0,1,5,0>: Cost 4 vsldoi12 <1,2,3,0>, <1,5,0,1> - 4191284879U, // <0,1,5,1>: Cost 3 vsldoi8 <5,1,0,1>, <5,1,0,1> - 3376056470U, // <0,1,5,2>: Cost 3 vmrglw <3,4,0,5>, <3,0,1,2> - 3230737545U, // <0,1,5,3>: Cost 4 vsldoi12 <1,5,3,0>, <1,5,3,0> - 3228746903U, // <0,1,5,4>: Cost 4 vsldoi12 <1,2,3,0>, <1,5,4,5> - 4193939411U, // <0,1,5,5>: Cost 3 vsldoi8 <5,5,0,1>, <5,5,0,1> - 4194603044U, // <0,1,5,6>: Cost 3 vsldoi8 <5,6,0,1>, <5,6,0,1> - 4195266677U, // <0,1,5,7>: Cost 4 vsldoi8 <5,7,0,1>, <5,7,0,1> - 4195930310U, // <0,1,5,u>: Cost 3 vsldoi8 <5,u,0,1>, <5,u,0,1> - 4068458598U, // <0,1,6,0>: Cost 3 vsldoi4 <7,0,1,6>, LHS - 3228746959U, // <0,1,6,1>: Cost 4 vsldoi12 <1,2,3,0>, <1,6,1,7> - 4201239034U, // <0,1,6,2>: Cost 3 vsldoi8 <6,7,0,1>, <6,2,7,3> - 4178014792U, // <0,1,6,3>: Cost 4 vsldoi8 <2,u,0,1>, <6,3,7,0> - 4068461878U, // <0,1,6,4>: Cost 3 vsldoi4 <7,0,1,6>, RHS - 3228746995U, // <0,1,6,5>: Cost 4 vsldoi12 <1,2,3,0>, <1,6,5,7> - 4201239352U, // <0,1,6,6>: Cost 3 vsldoi8 <6,7,0,1>, <6,6,6,6> - 3127497550U, // <0,1,6,7>: Cost 2 vsldoi8 <6,7,0,1>, <6,7,0,1> - 3128161183U, // <0,1,6,u>: Cost 2 vsldoi8 <6,u,0,1>, <6,u,0,1> - 4201239544U, // <0,1,7,0>: Cost 3 vsldoi8 <6,7,0,1>, <7,0,1,0> - 3377397770U, // <0,1,7,1>: Cost 4 vmrglw <3,6,0,7>, <0,0,1,1> - 4174697644U, // <0,1,7,2>: Cost 3 vsldoi8 <2,3,0,1>, <7,2,3,0> - 4204557539U, // <0,1,7,3>: Cost 3 vsldoi8 <7,3,0,1>, <7,3,0,1> - 4201239910U, // <0,1,7,4>: Cost 3 vsldoi8 <6,7,0,1>, <7,4,5,6> - 3377398098U, // <0,1,7,5>: Cost 4 vmrglw <3,6,0,7>, <0,4,1,5> - 4201240084U, // <0,1,7,6>: Cost 3 vsldoi8 <6,7,0,1>, <7,6,7,0> - 4201240172U, // <0,1,7,7>: Cost 3 vsldoi8 <6,7,0,1>, <7,7,7,7> - 4201240194U, // <0,1,7,u>: Cost 3 vsldoi8 <6,7,0,1>, <7,u,1,2> - 2970845286U, // <0,1,u,0>: Cost 2 vsldoi4 <3,0,1,u>, LHS - 2152964916U, // <0,1,u,1>: Cost 2 vmrghw LHS, <1,1,1,1> - 2152965014U, // <0,1,u,2>: Cost 2 vmrghw LHS, <1,2,3,0> + 3235170452U, // <0,1,3,0>: Cost 3 vsldoi8 <2,3,0,1>, <3,0,1,0> + 3357508404U, // <0,1,3,1>: Cost 4 vmrghw <0,3,1,0>, <1,1,1,1> + 3235170632U, // <0,1,3,2>: Cost 3 vsldoi8 <2,3,0,1>, <3,2,3,0> + 3235170716U, // <0,1,3,3>: Cost 3 vsldoi8 <2,3,0,1>, <3,3,3,3> + 3235170818U, // <0,1,3,4>: Cost 3 vsldoi8 <2,3,0,1>, <3,4,5,6> + 3362964473U, // <0,1,3,5>: Cost 4 vsldoi12 <1,2,3,0>, <1,3,5,0> + 3261713072U, // <0,1,3,6>: Cost 3 vsldoi8 <6,7,0,1>, <3,6,7,0> + 3243797187U, // <0,1,3,7>: Cost 3 vsldoi8 <3,7,0,1>, <3,7,0,1> + 3235171102U, // <0,1,3,u>: Cost 3 vsldoi8 <2,3,0,1>, <3,u,1,2> + 4178772070U, // <0,1,4,0>: Cost 3 vsldoi4 <3,0,1,4>, LHS + 3358212916U, // <0,1,4,1>: Cost 3 vmrghw <0,4,1,5>, <1,1,1,1> + 3358213014U, // <0,1,4,2>: Cost 3 vmrghw <0,4,1,5>, <1,2,3,0> + 4178774168U, // <0,1,4,3>: Cost 3 vsldoi4 <3,0,1,4>, <3,0,1,4> + 4178775350U, // <0,1,4,4>: Cost 3 vsldoi4 <3,0,1,4>, RHS + 3235171638U, // <0,1,4,5>: Cost 2 vsldoi8 <2,3,0,1>, RHS + 4202664782U, // <0,1,4,6>: Cost 3 vsldoi4 <7,0,1,4>, <6,7,0,1> + 4202664956U, // <0,1,4,7>: Cost 3 vsldoi4 <7,0,1,4>, <7,0,1,4> + 3235171881U, // <0,1,4,u>: Cost 2 vsldoi8 <2,3,0,1>, RHS + 3362964591U, // <0,1,5,0>: Cost 4 vsldoi12 <1,2,3,0>, <1,5,0,1> + 3251760783U, // <0,1,5,1>: Cost 3 vsldoi8 <5,1,0,1>, <5,1,0,1> + 3510274198U, // <0,1,5,2>: Cost 3 vmrglw <3,4,0,5>, <3,0,1,2> + 3364955273U, // <0,1,5,3>: Cost 4 vsldoi12 <1,5,3,0>, <1,5,3,0> + 3362964631U, // <0,1,5,4>: Cost 4 vsldoi12 <1,2,3,0>, <1,5,4,5> + 3254415315U, // <0,1,5,5>: Cost 3 vsldoi8 <5,5,0,1>, <5,5,0,1> + 3255078948U, // <0,1,5,6>: Cost 3 vsldoi8 <5,6,0,1>, <5,6,0,1> + 3255742581U, // <0,1,5,7>: Cost 4 vsldoi8 <5,7,0,1>, <5,7,0,1> + 3256406214U, // <0,1,5,u>: Cost 3 vsldoi8 <5,u,0,1>, <5,u,0,1> + 4202676326U, // <0,1,6,0>: Cost 3 vsldoi4 <7,0,1,6>, LHS + 3362964687U, // <0,1,6,1>: Cost 4 vsldoi12 <1,2,3,0>, <1,6,1,7> + 3261714938U, // <0,1,6,2>: Cost 3 vsldoi8 <6,7,0,1>, <6,2,7,3> + 3238490696U, // <0,1,6,3>: Cost 4 vsldoi8 <2,u,0,1>, <6,3,7,0> + 4202679606U, // <0,1,6,4>: Cost 3 vsldoi4 <7,0,1,6>, RHS + 3362964723U, // <0,1,6,5>: Cost 4 vsldoi12 <1,2,3,0>, <1,6,5,7> + 3261715256U, // <0,1,6,6>: Cost 3 vsldoi8 <6,7,0,1>, <6,6,6,6> + 3261715278U, // <0,1,6,7>: Cost 2 vsldoi8 <6,7,0,1>, <6,7,0,1> + 3262378911U, // <0,1,6,u>: Cost 2 vsldoi8 <6,u,0,1>, <6,u,0,1> + 3261715448U, // <0,1,7,0>: Cost 3 vsldoi8 <6,7,0,1>, <7,0,1,0> + 3511615498U, // <0,1,7,1>: Cost 4 vmrglw <3,6,0,7>, <0,0,1,1> + 3235173548U, // <0,1,7,2>: Cost 3 vsldoi8 <2,3,0,1>, <7,2,3,0> + 3265033443U, // <0,1,7,3>: Cost 3 vsldoi8 <7,3,0,1>, <7,3,0,1> + 3261715814U, // <0,1,7,4>: Cost 3 vsldoi8 <6,7,0,1>, <7,4,5,6> + 3511615826U, // <0,1,7,5>: Cost 4 vmrglw <3,6,0,7>, <0,4,1,5> + 3261715988U, // <0,1,7,6>: Cost 3 vsldoi8 <6,7,0,1>, <7,6,7,0> + 3261716076U, // <0,1,7,7>: Cost 3 vsldoi8 <6,7,0,1>, <7,7,7,7> + 3261716098U, // <0,1,7,u>: Cost 3 vsldoi8 <6,7,0,1>, <7,u,1,2> + 3105063014U, // <0,1,u,0>: Cost 2 vsldoi4 <3,0,1,u>, LHS + 2287182644U, // <0,1,u,1>: Cost 2 vmrghw LHS, <1,1,1,1> + 2287182742U, // <0,1,u,2>: Cost 2 vmrghw LHS, <1,2,3,0> 835584U, // <0,1,u,3>: Cost 0 copy LHS - 2970848566U, // <0,1,u,4>: Cost 2 vsldoi4 <3,0,1,u>, RHS - 3100956826U, // <0,1,u,5>: Cost 2 vsldoi8 <2,3,0,1>, RHS - 3226707151U, // <0,1,u,6>: Cost 3 vmrghw LHS, <1,6,1,7> - 2994738176U, // <0,1,u,7>: Cost 2 vsldoi4 <7,0,1,u>, <7,0,1,u> + 3105066294U, // <0,1,u,4>: Cost 2 vsldoi4 <3,0,1,u>, RHS + 3235174554U, // <0,1,u,5>: Cost 2 vsldoi8 <2,3,0,1>, RHS + 3360924879U, // <0,1,u,6>: Cost 3 vmrghw LHS, <1,6,1,7> + 3128955904U, // <0,1,u,7>: Cost 2 vsldoi4 <7,0,1,u>, <7,0,1,u> 835584U, // <0,1,u,u>: Cost 0 copy LHS - 3221226957U, // <0,2,0,0>: Cost 3 vmrghw <0,0,0,0>, <2,0,3,0> - 3221308959U, // <0,2,0,1>: Cost 3 vmrghw <0,0,1,1>, <2,1,3,1> - 3221227112U, // <0,2,0,2>: Cost 3 vmrghw <0,0,0,0>, <2,2,2,2> - 2281701478U, // <0,2,0,3>: Cost 2 vmrglw <0,0,0,0>, LHS - 4044598582U, // <0,2,0,4>: Cost 4 vsldoi4 <3,0,2,0>, RHS - 3375350836U, // <0,2,0,5>: Cost 4 vmrglw <3,3,0,0>, <1,4,2,5> - 3221227450U, // <0,2,0,6>: Cost 3 vmrghw <0,0,0,0>, <2,6,3,7> - 3221227498U, // <0,2,0,7>: Cost 4 vmrghw <0,0,0,0>, <2,7,0,1> - 2281701483U, // <0,2,0,u>: Cost 2 vmrglw <0,0,0,0>, LHS - 3222504954U, // <0,2,1,0>: Cost 3 vmrghw LHS, <2,0,u,0> - 3222103583U, // <0,2,1,1>: Cost 3 vmrghw LHS, <2,1,3,1> - 2148361832U, // <0,2,1,2>: Cost 2 vmrghw LHS, <2,2,2,2> - 2148361894U, // <0,2,1,3>: Cost 2 vmrghw LHS, <2,3,0,1> - 3222505283U, // <0,2,1,4>: Cost 3 vmrghw LHS, <2,4,u,5> - 3222505365U, // <0,2,1,5>: Cost 3 vmrghw LHS, <2,5,u,6> - 2148362170U, // <0,2,1,6>: Cost 2 vmrghw LHS, <2,6,3,7> - 3222063082U, // <0,2,1,7>: Cost 3 vmrghw LHS, <2,7,0,1> - 2148362328U, // <0,2,1,u>: Cost 2 vmrghw LHS, <2,u,3,3> - 3222627834U, // <0,2,2,0>: Cost 4 vmrghw <0,2,1,0>, <2,0,u,0> - 3222636063U, // <0,2,2,1>: Cost 4 vmrghw <0,2,1,1>, <2,1,3,1> - 3222644328U, // <0,2,2,2>: Cost 3 vmrghw <0,2,1,2>, <2,2,2,2> - 3222652582U, // <0,2,2,3>: Cost 3 vmrghw <0,2,1,3>, <2,3,0,1> - 3222660931U, // <0,2,2,4>: Cost 4 vmrghw <0,2,1,4>, <2,4,u,5> - 3222669205U, // <0,2,2,5>: Cost 4 vmrghw <0,2,1,5>, <2,5,u,6> - 3222677434U, // <0,2,2,6>: Cost 3 vmrghw <0,2,1,6>, <2,6,3,7> - 4068504579U, // <0,2,2,7>: Cost 4 vsldoi4 <7,0,2,2>, <7,0,2,2> - 3222693976U, // <0,2,2,u>: Cost 3 vmrghw <0,2,1,u>, <2,u,3,3> - 3228747430U, // <0,2,3,0>: Cost 3 vsldoi12 <1,2,3,0>, <2,3,0,1> - 3228747440U, // <0,2,3,1>: Cost 3 vsldoi12 <1,2,3,0>, <2,3,1,2> - 3223291496U, // <0,2,3,2>: Cost 4 vmrghw <0,3,1,0>, <2,2,2,2> - 3228747456U, // <0,2,3,3>: Cost 3 vsldoi12 <1,2,3,0>, <2,3,3,0> - 3228747470U, // <0,2,3,4>: Cost 3 vsldoi12 <1,2,3,0>, <2,3,4,5> - 3255584472U, // <0,2,3,5>: Cost 3 vsldoi12 <5,6,7,0>, <2,3,5,6> - 3223291834U, // <0,2,3,6>: Cost 4 vmrghw <0,3,1,0>, <2,6,3,7> - 3235677924U, // <0,2,3,7>: Cost 3 vsldoi12 <2,3,7,0>, <2,3,7,0> - 3228747501U, // <0,2,3,u>: Cost 3 vsldoi12 <1,2,3,0>, <2,3,u,0> - 3223995898U, // <0,2,4,0>: Cost 4 vmrghw <0,4,1,5>, <2,0,u,0> - 3223995939U, // <0,2,4,1>: Cost 3 vmrghw <0,4,1,5>, <2,1,3,5> - 3223996008U, // <0,2,4,2>: Cost 3 vmrghw <0,4,1,5>, <2,2,2,2> - 3223996070U, // <0,2,4,3>: Cost 3 vmrghw <0,4,1,5>, <2,3,0,1> - 3223996223U, // <0,2,4,4>: Cost 4 vmrghw <0,4,1,5>, <2,4,u,1> - 3223996309U, // <0,2,4,5>: Cost 4 vmrghw <0,4,1,5>, <2,5,u,6> - 3223996346U, // <0,2,4,6>: Cost 3 vmrghw <0,4,1,5>, <2,6,3,7> - 4191292872U, // <0,2,4,7>: Cost 4 vsldoi8 <5,1,0,2>, <4,7,5,0> - 3223996475U, // <0,2,4,u>: Cost 3 vmrghw <0,4,1,5>, <2,u,0,1> - 3376054371U, // <0,2,5,0>: Cost 4 vmrglw <3,4,0,5>, <0,1,2,0> - 4191293072U, // <0,2,5,1>: Cost 4 vsldoi8 <5,1,0,2>, <5,1,0,2> - 3376055912U, // <0,2,5,2>: Cost 4 vmrglw <3,4,0,5>, <2,2,2,2> - 3376054374U, // <0,2,5,3>: Cost 3 vmrglw <3,4,0,5>, LHS - 3376054375U, // <0,2,5,4>: Cost 4 vmrglw <3,4,0,5>, <0,1,2,4> - 3374728244U, // <0,2,5,5>: Cost 4 vmrglw <3,2,0,5>, <1,4,2,5> - 4207882338U, // <0,2,5,6>: Cost 4 vsldoi8 <7,u,0,2>, <5,6,7,0> - 3376055512U, // <0,2,5,7>: Cost 4 vmrglw <3,4,0,5>, <1,6,2,7> - 3376054379U, // <0,2,5,u>: Cost 3 vmrglw <3,4,0,5>, LHS - 4044644454U, // <0,2,6,0>: Cost 4 vsldoi4 <3,0,2,6>, LHS - 4044645270U, // <0,2,6,1>: Cost 4 vsldoi4 <3,0,2,6>, <1,2,3,0> - 4044646330U, // <0,2,6,2>: Cost 4 vsldoi4 <3,0,2,6>, <2,6,3,7> - 3228747706U, // <0,2,6,3>: Cost 3 vsldoi12 <1,2,3,0>, <2,6,3,7> - 4044647734U, // <0,2,6,4>: Cost 4 vsldoi4 <3,0,2,6>, RHS - 4068536418U, // <0,2,6,5>: Cost 4 vsldoi4 <7,0,2,6>, <5,6,7,0> - 3225266106U, // <0,2,6,6>: Cost 4 vmrghw <0,6,0,7>, <2,6,3,7> - 4201247567U, // <0,2,6,7>: Cost 4 vsldoi8 <6,7,0,2>, <6,7,0,2> - 3228747751U, // <0,2,6,u>: Cost 3 vsldoi12 <1,2,3,0>, <2,6,u,7> - 4191294458U, // <0,2,7,0>: Cost 4 vsldoi8 <5,1,0,2>, <7,0,1,2> - 3377398508U, // <0,2,7,1>: Cost 4 vmrglw <3,6,0,7>, <1,0,2,1> - 3377398590U, // <0,2,7,2>: Cost 4 vmrglw <3,6,0,7>, <1,1,2,2> - 3377397862U, // <0,2,7,3>: Cost 3 vmrglw <3,6,0,7>, LHS - 4044655926U, // <0,2,7,4>: Cost 4 vsldoi4 <3,0,2,7>, RHS - 3377398836U, // <0,2,7,5>: Cost 4 vmrglw <3,6,0,7>, <1,4,2,5> - 4206556631U, // <0,2,7,6>: Cost 4 vsldoi8 <7,6,0,2>, <7,6,0,2> - 3225946090U, // <0,2,7,7>: Cost 4 vmrghw <0,7,1,0>, <2,7,0,1> - 3377397867U, // <0,2,7,u>: Cost 3 vmrglw <3,6,0,7>, LHS - 3226707450U, // <0,2,u,0>: Cost 3 vmrghw LHS, <2,0,u,0> - 3226707487U, // <0,2,u,1>: Cost 3 vmrghw LHS, <2,1,3,1> - 2152965736U, // <0,2,u,2>: Cost 2 vmrghw LHS, <2,2,2,2> - 2152965798U, // <0,2,u,3>: Cost 2 vmrghw LHS, <2,3,0,1> - 3226707779U, // <0,2,u,4>: Cost 3 vmrghw LHS, <2,4,u,5> - 3226707861U, // <0,2,u,5>: Cost 3 vmrghw LHS, <2,5,u,6> - 2152966074U, // <0,2,u,6>: Cost 2 vmrghw LHS, <2,6,3,7> - 3226707946U, // <0,2,u,7>: Cost 3 vmrghw LHS, <2,7,0,1> - 2152966203U, // <0,2,u,u>: Cost 2 vmrghw LHS, <2,u,0,1> - 4038696960U, // <0,3,0,0>: Cost 3 vsldoi4 <2,0,3,0>, <0,0,0,0> - 3223292054U, // <0,3,0,1>: Cost 3 vsldoi12 <0,3,1,0>, <3,0,1,2> - 4038698445U, // <0,3,0,2>: Cost 3 vsldoi4 <2,0,3,0>, <2,0,3,0> - 3221227932U, // <0,3,0,3>: Cost 3 vmrghw <0,0,0,0>, <3,3,3,3> - 3228747956U, // <0,3,0,4>: Cost 3 vsldoi12 <1,2,3,0>, <3,0,4,5> - 4068560994U, // <0,3,0,5>: Cost 4 vsldoi4 <7,0,3,0>, <5,6,7,0> - 4180017672U, // <0,3,0,6>: Cost 4 vsldoi8 <3,2,0,3>, <0,6,3,7> - 3355445178U, // <0,3,0,7>: Cost 3 vmrglw <0,0,0,0>, <2,6,3,7> - 3228747989U, // <0,3,0,u>: Cost 3 vsldoi12 <1,2,3,0>, <3,0,u,2> - 2148362390U, // <0,3,1,0>: Cost 2 vmrghw LHS, <3,0,1,2> - 3222104294U, // <0,3,1,1>: Cost 3 vmrghw LHS, <3,1,1,1> - 3222104385U, // <0,3,1,2>: Cost 3 vmrghw LHS, <3,2,2,2> - 2148362652U, // <0,3,1,3>: Cost 2 vmrghw LHS, <3,3,3,3> - 2148362754U, // <0,3,1,4>: Cost 2 vmrghw LHS, <3,4,5,6> - 3222063698U, // <0,3,1,5>: Cost 3 vmrghw LHS, <3,5,5,5> - 3222063736U, // <0,3,1,6>: Cost 3 vmrghw LHS, <3,6,0,7> - 3369387962U, // <0,3,1,7>: Cost 3 vmrglw <2,3,0,1>, <2,6,3,7> - 2148363038U, // <0,3,1,u>: Cost 2 vmrghw LHS, <3,u,1,2> - 3228748080U, // <0,3,2,0>: Cost 3 vsldoi12 <1,2,3,0>, <3,2,0,3> - 4044686230U, // <0,3,2,1>: Cost 4 vsldoi4 <3,0,3,2>, <1,2,3,0> - 3222645057U, // <0,3,2,2>: Cost 4 vmrghw <0,2,1,2>, <3,2,2,2> - 3240692040U, // <0,3,2,3>: Cost 3 vsldoi12 <3,2,3,0>, <3,2,3,0> - 3222645250U, // <0,3,2,4>: Cost 4 vmrghw <0,2,1,2>, <3,4,5,6> - 3362095460U, // <0,3,2,5>: Cost 5 vmrglw <1,1,0,2>, <0,4,3,5> - 3228748134U, // <0,3,2,6>: Cost 4 vsldoi12 <1,2,3,0>, <3,2,6,3> - 3365414842U, // <0,3,2,7>: Cost 4 vmrglw <1,6,0,2>, <2,6,3,7> - 3241060725U, // <0,3,2,u>: Cost 3 vsldoi12 <3,2,u,0>, <3,2,u,0> - 3223292054U, // <0,3,3,0>: Cost 3 vmrghw <0,3,1,0>, <3,0,1,2> - 3223300326U, // <0,3,3,1>: Cost 4 vmrghw <0,3,1,1>, <3,1,1,1> - 4180019504U, // <0,3,3,2>: Cost 3 vsldoi8 <3,2,0,3>, <3,2,0,3> - 3223316892U, // <0,3,3,3>: Cost 3 vmrghw <0,3,1,3>, <3,3,3,3> - 3223325186U, // <0,3,3,4>: Cost 3 vmrghw <0,3,1,4>, <3,4,5,6> - 4068585570U, // <0,3,3,5>: Cost 4 vsldoi4 <7,0,3,3>, <5,6,7,0> - 3228748212U, // <0,3,3,6>: Cost 4 vsldoi12 <1,2,3,0>, <3,3,6,0> - 3374712762U, // <0,3,3,7>: Cost 4 vmrglw <3,2,0,3>, <2,6,3,7> - 3223358238U, // <0,3,3,u>: Cost 3 vmrghw <0,3,1,u>, <3,u,1,2> - 3223996566U, // <0,3,4,0>: Cost 3 vmrghw <0,4,1,5>, <3,0,1,2> - 3223996646U, // <0,3,4,1>: Cost 4 vmrghw <0,4,1,5>, <3,1,1,1> - 3223996737U, // <0,3,4,2>: Cost 4 vmrghw <0,4,1,5>, <3,2,2,2> - 3223996828U, // <0,3,4,3>: Cost 3 vmrghw <0,4,1,5>, <3,3,3,3> - 3223996930U, // <0,3,4,4>: Cost 3 vmrghw <0,4,1,5>, <3,4,5,6> - 3228748290U, // <0,3,4,5>: Cost 3 vsldoi12 <1,2,3,0>, <3,4,5,6> - 4062622005U, // <0,3,4,6>: Cost 4 vsldoi4 <6,0,3,4>, <6,0,3,4> - 3364767674U, // <0,3,4,7>: Cost 4 vmrglw <1,5,0,4>, <2,6,3,7> - 3223997214U, // <0,3,4,u>: Cost 3 vmrghw <0,4,1,5>, <3,u,1,2> - 3228748326U, // <0,3,5,0>: Cost 4 vsldoi12 <1,2,3,0>, <3,5,0,6> - 3405916003U, // <0,3,5,1>: Cost 4 vmrglw , <2,5,3,1> - 3376055840U, // <0,3,5,2>: Cost 4 vmrglw <3,4,0,5>, <2,1,3,2> - 3376055679U, // <0,3,5,3>: Cost 4 vmrglw <3,4,0,5>, <1,u,3,3> - 3376055194U, // <0,3,5,4>: Cost 4 vmrglw <3,4,0,5>, <1,2,3,4> - 3255585362U, // <0,3,5,5>: Cost 4 vsldoi12 <5,6,7,0>, <3,5,5,5> - 4203909218U, // <0,3,5,6>: Cost 3 vsldoi8 <7,2,0,3>, <5,6,7,0> - 3376056250U, // <0,3,5,7>: Cost 4 vmrglw <3,4,0,5>, <2,6,3,7> - 4203909218U, // <0,3,5,u>: Cost 3 vsldoi8 <7,2,0,3>, <5,6,7,0> - 3228748408U, // <0,3,6,0>: Cost 3 vsldoi12 <1,2,3,0>, <3,6,0,7> - 4044718998U, // <0,3,6,1>: Cost 4 vsldoi4 <3,0,3,6>, <1,2,3,0> - 4197937595U, // <0,3,6,2>: Cost 4 vsldoi8 <6,2,0,3>, <6,2,0,3> - 4044720300U, // <0,3,6,3>: Cost 4 vsldoi4 <3,0,3,6>, <3,0,3,6> - 3229117084U, // <0,3,6,4>: Cost 4 vsldoi12 <1,2,u,0>, <3,6,4,7> - 3376728235U, // <0,3,6,5>: Cost 5 vmrglw <3,5,0,6>, <3,0,3,5> - 3255585453U, // <0,3,6,6>: Cost 4 vsldoi12 <5,6,7,0>, <3,6,6,6> - 3243641520U, // <0,3,6,7>: Cost 3 vsldoi12 <3,6,7,0>, <3,6,7,0> - 3228748408U, // <0,3,6,u>: Cost 3 vsldoi12 <1,2,3,0>, <3,6,0,7> - 3377398678U, // <0,3,7,0>: Cost 3 vmrglw <3,6,0,7>, <1,2,3,0> - 4209882202U, // <0,3,7,1>: Cost 4 vsldoi8 , <7,1,2,u> - 4203910292U, // <0,3,7,2>: Cost 3 vsldoi8 <7,2,0,3>, <7,2,0,3> - 3377399410U, // <0,3,7,3>: Cost 4 vmrglw <3,6,0,7>, <2,2,3,3> - 3377398682U, // <0,3,7,4>: Cost 4 vmrglw <3,6,0,7>, <1,2,3,4> - 4203910593U, // <0,3,7,5>: Cost 4 vsldoi8 <7,2,0,3>, <7,5,6,7> - 3377399980U, // <0,3,7,6>: Cost 4 vmrglw <3,6,0,7>, <3,0,3,6> - 3375409082U, // <0,3,7,7>: Cost 4 vmrglw <3,3,0,7>, <2,6,3,7> - 4207892090U, // <0,3,7,u>: Cost 3 vsldoi8 <7,u,0,3>, <7,u,0,3> - 2152966294U, // <0,3,u,0>: Cost 2 vmrghw LHS, <3,0,1,2> - 3226708198U, // <0,3,u,1>: Cost 3 vmrghw LHS, <3,1,1,1> - 3226708289U, // <0,3,u,2>: Cost 3 vmrghw LHS, <3,2,2,2> - 2152966556U, // <0,3,u,3>: Cost 2 vmrghw LHS, <3,3,3,3> - 2152966658U, // <0,3,u,4>: Cost 2 vmrghw LHS, <3,4,5,6> - 3228748614U, // <0,3,u,5>: Cost 3 vsldoi12 <1,2,3,0>, <3,u,5,6> - 3273501520U, // <0,3,u,6>: Cost 3 vsldoi12 , <3,u,6,7> - 3369445306U, // <0,3,u,7>: Cost 3 vmrglw <2,3,0,u>, <2,6,3,7> - 2152966942U, // <0,3,u,u>: Cost 2 vmrghw LHS, <3,u,1,2> - 3221228433U, // <0,4,0,0>: Cost 3 vmrghw <0,0,0,0>, <4,0,5,0> - 4170072166U, // <0,4,0,1>: Cost 3 vsldoi8 <1,5,0,4>, LHS - 3235457913U, // <0,4,0,2>: Cost 4 vsldoi12 <2,3,4,0>, <4,0,2,3> - 4044744879U, // <0,4,0,3>: Cost 4 vsldoi4 <3,0,4,0>, <3,0,4,0> - 4170072402U, // <0,4,0,4>: Cost 3 vsldoi8 <1,5,0,4>, <0,4,1,5> - 2147487030U, // <0,4,0,5>: Cost 2 vmrghw <0,0,0,0>, RHS - 4170072593U, // <0,4,0,6>: Cost 4 vsldoi8 <1,5,0,4>, <0,6,4,7> - 3250129828U, // <0,4,0,7>: Cost 4 vsldoi12 <4,7,5,0>, <4,0,7,1> - 2147487273U, // <0,4,0,u>: Cost 2 vmrghw <0,0,0,0>, RHS - 2148322194U, // <0,4,1,0>: Cost 2 vmrghw LHS, <4,0,5,1> - 3222064074U, // <0,4,1,1>: Cost 3 vmrghw LHS, <4,1,2,3> - 3222064181U, // <0,4,1,2>: Cost 3 vmrghw LHS, <4,2,5,2> - 4044753072U, // <0,4,1,3>: Cost 3 vsldoi4 <3,0,4,1>, <3,0,4,1> - 2148322512U, // <0,4,1,4>: Cost 2 vmrghw LHS, <4,4,4,4> - 1074580790U, // <0,4,1,5>: Cost 1 vmrghw LHS, RHS - 3222064505U, // <0,4,1,6>: Cost 3 vmrghw LHS, <4,6,5,2> - 4068643860U, // <0,4,1,7>: Cost 3 vsldoi4 <7,0,4,1>, <7,0,4,1> - 1074581033U, // <0,4,1,u>: Cost 1 vmrghw LHS, RHS - 4170073553U, // <0,4,2,0>: Cost 4 vsldoi8 <1,5,0,4>, <2,0,3,4> - 4170073635U, // <0,4,2,1>: Cost 4 vsldoi8 <1,5,0,4>, <2,1,3,5> - 4170073704U, // <0,4,2,2>: Cost 4 vsldoi8 <1,5,0,4>, <2,2,2,2> - 4174718633U, // <0,4,2,3>: Cost 3 vsldoi8 <2,3,0,4>, <2,3,0,4> - 4044762422U, // <0,4,2,4>: Cost 4 vsldoi4 <3,0,4,2>, RHS - 3222646070U, // <0,4,2,5>: Cost 3 vmrghw <0,2,1,2>, RHS - 4170074042U, // <0,4,2,6>: Cost 4 vsldoi8 <1,5,0,4>, <2,6,3,7> - 4177373165U, // <0,4,2,7>: Cost 4 vsldoi8 <2,7,0,4>, <2,7,0,4> - 3222646313U, // <0,4,2,u>: Cost 3 vmrghw <0,2,1,2>, RHS - 4170074262U, // <0,4,3,0>: Cost 4 vsldoi8 <1,5,0,4>, <3,0,1,2> - 4179364064U, // <0,4,3,1>: Cost 4 vsldoi8 <3,1,0,4>, <3,1,0,4> - 3229117549U, // <0,4,3,2>: Cost 5 vsldoi12 <1,2,u,0>, <4,3,2,4> - 4170074524U, // <0,4,3,3>: Cost 4 vsldoi8 <1,5,0,4>, <3,3,3,3> - 4170074626U, // <0,4,3,4>: Cost 4 vsldoi8 <1,5,0,4>, <3,4,5,6> - 3223293238U, // <0,4,3,5>: Cost 3 vmrghw <0,3,1,0>, RHS - 3229117585U, // <0,4,3,6>: Cost 5 vsldoi12 <1,2,u,0>, <4,3,6,4> - 4183345862U, // <0,4,3,7>: Cost 4 vsldoi8 <3,7,0,4>, <3,7,0,4> - 3223293481U, // <0,4,3,u>: Cost 3 vmrghw <0,3,1,0>, RHS - 4026859560U, // <0,4,4,0>: Cost 3 vsldoi4 <0,0,4,4>, <0,0,4,4> - 3223997410U, // <0,4,4,1>: Cost 3 vmrghw <0,4,1,5>, <4,1,5,0> - 4026861091U, // <0,4,4,2>: Cost 4 vsldoi4 <0,0,4,4>, <2,1,3,5> - 4044777651U, // <0,4,4,3>: Cost 4 vsldoi4 <3,0,4,4>, <3,0,4,4> - 3255586000U, // <0,4,4,4>: Cost 3 vsldoi12 <5,6,7,0>, <4,4,4,4> - 2150255926U, // <0,4,4,5>: Cost 2 vmrghw <0,4,1,5>, RHS - 4026864043U, // <0,4,4,6>: Cost 4 vsldoi4 <0,0,4,4>, <6,1,7,5> - 3250130156U, // <0,4,4,7>: Cost 4 vsldoi12 <4,7,5,0>, <4,4,7,5> - 2150256169U, // <0,4,4,u>: Cost 2 vmrghw <0,4,1,5>, RHS - 4044783718U, // <0,4,5,0>: Cost 3 vsldoi4 <3,0,4,5>, LHS - 4044784534U, // <0,4,5,1>: Cost 3 vsldoi4 <3,0,4,5>, <1,2,3,0> - 4044785256U, // <0,4,5,2>: Cost 4 vsldoi4 <3,0,4,5>, <2,2,2,2> - 4044785844U, // <0,4,5,3>: Cost 3 vsldoi4 <3,0,4,5>, <3,0,4,5> - 4044786998U, // <0,4,5,4>: Cost 3 vsldoi4 <3,0,4,5>, RHS - 3255586092U, // <0,4,5,5>: Cost 3 vsldoi12 <5,6,7,0>, <4,5,5,6> - 3228749110U, // <0,4,5,6>: Cost 2 vsldoi12 <1,2,3,0>, RHS - 4068676632U, // <0,4,5,7>: Cost 3 vsldoi4 <7,0,4,5>, <7,0,4,5> - 3228749128U, // <0,4,5,u>: Cost 2 vsldoi12 <1,2,3,0>, RHS - 3235458385U, // <0,4,6,0>: Cost 4 vsldoi12 <2,3,4,0>, <4,6,0,7> - 4201263531U, // <0,4,6,1>: Cost 4 vsldoi8 <6,7,0,4>, <6,1,7,5> - 4201263610U, // <0,4,6,2>: Cost 4 vsldoi8 <6,7,0,4>, <6,2,7,3> - 4198609421U, // <0,4,6,3>: Cost 4 vsldoi8 <6,3,0,4>, <6,3,0,4> - 4068683062U, // <0,4,6,4>: Cost 4 vsldoi4 <7,0,4,6>, RHS - 3225267510U, // <0,4,6,5>: Cost 3 vmrghw <0,6,0,7>, RHS - 4201263928U, // <0,4,6,6>: Cost 4 vsldoi8 <6,7,0,4>, <6,6,6,6> - 4201263953U, // <0,4,6,7>: Cost 3 vsldoi8 <6,7,0,4>, <6,7,0,4> - 4201927586U, // <0,4,6,u>: Cost 3 vsldoi8 <6,u,0,4>, <6,u,0,4> - 3383371465U, // <0,4,7,0>: Cost 4 vmrglw <4,6,0,7>, <2,3,4,0> - 4203254852U, // <0,4,7,1>: Cost 4 vsldoi8 <7,1,0,4>, <7,1,0,4> - 4178040010U, // <0,4,7,2>: Cost 5 vsldoi8 <2,u,0,4>, <7,2,6,3> - 4204582118U, // <0,4,7,3>: Cost 4 vsldoi8 <7,3,0,4>, <7,3,0,4> - 4056747318U, // <0,4,7,4>: Cost 4 vsldoi4 <5,0,4,7>, RHS - 3250130376U, // <0,4,7,5>: Cost 3 vsldoi12 <4,7,5,0>, <4,7,5,0> - 3383372686U, // <0,4,7,6>: Cost 5 vmrglw <4,6,0,7>, <4,0,4,6> - 3250130394U, // <0,4,7,7>: Cost 4 vsldoi12 <4,7,5,0>, <4,7,7,0> - 3250130376U, // <0,4,7,u>: Cost 3 vsldoi12 <4,7,5,0>, <4,7,5,0> - 2152967058U, // <0,4,u,0>: Cost 2 vmrghw LHS, <4,0,5,1> - 3226708962U, // <0,4,u,1>: Cost 3 vmrghw LHS, <4,1,5,0> - 3226709045U, // <0,4,u,2>: Cost 3 vmrghw LHS, <4,2,5,2> - 4044810423U, // <0,4,u,3>: Cost 3 vsldoi4 <3,0,4,u>, <3,0,4,u> - 2152967376U, // <0,4,u,4>: Cost 2 vmrghw LHS, <4,4,4,4> - 1079225654U, // <0,4,u,5>: Cost 1 vmrghw LHS, RHS - 3228749353U, // <0,4,u,6>: Cost 2 vsldoi12 <1,2,3,0>, RHS - 4068701211U, // <0,4,u,7>: Cost 3 vsldoi4 <7,0,4,u>, <7,0,4,u> - 1079225897U, // <0,4,u,u>: Cost 1 vmrghw LHS, RHS - 3355446161U, // <0,5,0,0>: Cost 3 vmrglw <0,0,0,0>, <4,0,5,0> - 4181360742U, // <0,5,0,1>: Cost 3 vsldoi8 <3,4,0,5>, LHS - 4181360850U, // <0,5,0,2>: Cost 4 vsldoi8 <3,4,0,5>, <0,2,5,3> - 4181360892U, // <0,5,0,3>: Cost 4 vsldoi8 <3,4,0,5>, <0,3,1,0> - 4163445065U, // <0,5,0,4>: Cost 3 vsldoi8 <0,4,0,5>, <0,4,0,5> - 3221229572U, // <0,5,0,5>: Cost 3 vmrghw <0,0,0,0>, <5,5,5,5> - 3255586420U, // <0,5,0,6>: Cost 3 vsldoi12 <5,6,7,0>, <5,0,6,1> - 3250130556U, // <0,5,0,7>: Cost 4 vsldoi12 <4,7,5,0>, <5,0,7,0> - 4181361309U, // <0,5,0,u>: Cost 3 vsldoi8 <3,4,0,5>, LHS - 2977054822U, // <0,5,1,0>: Cost 2 vsldoi4 <4,0,5,1>, LHS - 3385978394U, // <0,5,1,1>: Cost 3 vmrglw <5,1,0,1>, <4,u,5,1> - 3222064875U, // <0,5,1,2>: Cost 3 vmrghw LHS, <5,2,1,3> - 4050798742U, // <0,5,1,3>: Cost 3 vsldoi4 <4,0,5,1>, <3,0,1,2> - 2977057682U, // <0,5,1,4>: Cost 2 vsldoi4 <4,0,5,1>, <4,0,5,1> - 2148323332U, // <0,5,1,5>: Cost 2 vmrghw LHS, <5,5,5,5> - 2148323426U, // <0,5,1,6>: Cost 2 vmrghw LHS, <5,6,7,0> - 4050801658U, // <0,5,1,7>: Cost 3 vsldoi4 <4,0,5,1>, <7,0,1,2> - 2148323575U, // <0,5,1,u>: Cost 2 vmrghw LHS, <5,u,5,5> - 4175390157U, // <0,5,2,0>: Cost 4 vsldoi8 <2,4,0,5>, <2,0,3,0> - 4181362208U, // <0,5,2,1>: Cost 4 vsldoi8 <3,4,0,5>, <2,1,3,2> - 4181362280U, // <0,5,2,2>: Cost 4 vsldoi8 <3,4,0,5>, <2,2,2,2> - 4181362342U, // <0,5,2,3>: Cost 4 vsldoi8 <3,4,0,5>, <2,3,0,1> - 4175390459U, // <0,5,2,4>: Cost 4 vsldoi8 <2,4,0,5>, <2,4,0,5> - 3255586575U, // <0,5,2,5>: Cost 4 vsldoi12 <5,6,7,0>, <5,2,5,3> - 4181362618U, // <0,5,2,6>: Cost 4 vsldoi8 <3,4,0,5>, <2,6,3,7> - 4207904746U, // <0,5,2,7>: Cost 4 vsldoi8 <7,u,0,5>, <2,7,0,1> - 4178044991U, // <0,5,2,u>: Cost 4 vsldoi8 <2,u,0,5>, <2,u,0,5> - 4181362838U, // <0,5,3,0>: Cost 3 vsldoi8 <3,4,0,5>, <3,0,1,2> - 4179372257U, // <0,5,3,1>: Cost 4 vsldoi8 <3,1,0,5>, <3,1,0,5> - 4180035890U, // <0,5,3,2>: Cost 4 vsldoi8 <3,2,0,5>, <3,2,0,5> - 4181363071U, // <0,5,3,3>: Cost 4 vsldoi8 <3,4,0,5>, <3,3,0,1> - 4181363156U, // <0,5,3,4>: Cost 3 vsldoi8 <3,4,0,5>, <3,4,0,5> - 3253448541U, // <0,5,3,5>: Cost 4 vsldoi12 <5,3,5,0>, <5,3,5,0> - 3364096514U, // <0,5,3,6>: Cost 4 vmrglw <1,4,0,3>, <3,4,5,6> - 4183354055U, // <0,5,3,7>: Cost 4 vsldoi8 <3,7,0,5>, <3,7,0,5> - 4184017688U, // <0,5,3,u>: Cost 3 vsldoi8 <3,u,0,5>, <3,u,0,5> - 4205251474U, // <0,5,4,0>: Cost 3 vsldoi8 <7,4,0,5>, <4,0,5,1> - 4032905994U, // <0,5,4,1>: Cost 4 vsldoi4 <1,0,5,4>, <1,0,5,4> - 4032906921U, // <0,5,4,2>: Cost 4 vsldoi4 <1,0,5,4>, <2,3,0,4> - 3364766635U, // <0,5,4,3>: Cost 4 vmrglw <1,5,0,4>, <1,2,5,3> - 3223998388U, // <0,5,4,4>: Cost 3 vmrghw <0,4,1,5>, <5,4,5,6> - 4181364022U, // <0,5,4,5>: Cost 3 vsldoi8 <3,4,0,5>, RHS - 3255586748U, // <0,5,4,6>: Cost 3 vsldoi12 <5,6,7,0>, <5,4,6,5> - 3364766963U, // <0,5,4,7>: Cost 4 vmrglw <1,5,0,4>, <1,6,5,7> - 4181364265U, // <0,5,4,u>: Cost 3 vsldoi8 <3,4,0,5>, RHS - 3242168274U, // <0,5,5,0>: Cost 4 vsldoi12 <3,4,5,0>, <5,5,0,0> - 3399945106U, // <0,5,5,1>: Cost 3 vmrglw <7,4,0,5>, <4,0,5,1> - 3224637163U, // <0,5,5,2>: Cost 4 vmrghw <0,5,1,2>, <5,2,1,3> - 3376054482U, // <0,5,5,3>: Cost 4 vmrglw <3,4,0,5>, <0,2,5,3> - 4193308550U, // <0,5,5,4>: Cost 4 vsldoi8 <5,4,0,5>, <5,4,0,5> - 3255586820U, // <0,5,5,5>: Cost 3 vsldoi12 <5,6,7,0>, <5,5,5,5> - 4201271394U, // <0,5,5,6>: Cost 3 vsldoi8 <6,7,0,5>, <5,6,7,0> - 3254923281U, // <0,5,5,7>: Cost 4 vsldoi12 <5,5,7,0>, <5,5,7,0> - 4213215492U, // <0,5,5,u>: Cost 3 vsldoi8 , <5,u,7,0> - 4068753510U, // <0,5,6,0>: Cost 3 vsldoi4 <7,0,5,6>, LHS - 3255586867U, // <0,5,6,1>: Cost 4 vsldoi12 <5,6,7,0>, <5,6,1,7> - 4201271802U, // <0,5,6,2>: Cost 4 vsldoi8 <6,7,0,5>, <6,2,7,3> - 3248877634U, // <0,5,6,3>: Cost 4 vsldoi12 <4,5,6,0>, <5,6,3,4> - 4068756790U, // <0,5,6,4>: Cost 3 vsldoi4 <7,0,5,6>, RHS - 4068757602U, // <0,5,6,5>: Cost 3 vsldoi4 <7,0,5,6>, <5,6,7,0> - 3228749920U, // <0,5,6,6>: Cost 4 vsldoi12 <1,2,3,0>, <5,6,6,7> - 3255586914U, // <0,5,6,7>: Cost 2 vsldoi12 <5,6,7,0>, <5,6,7,0> - 3255660651U, // <0,5,6,u>: Cost 2 vsldoi12 <5,6,u,0>, <5,6,u,0> - 4207907834U, // <0,5,7,0>: Cost 3 vsldoi8 <7,u,0,5>, <7,0,1,2> - 3255586941U, // <0,5,7,1>: Cost 4 vsldoi12 <5,6,7,0>, <5,7,1,0> - 4201272468U, // <0,5,7,2>: Cost 4 vsldoi8 <6,7,0,5>, <7,2,0,3> - 4181365987U, // <0,5,7,3>: Cost 4 vsldoi8 <3,4,0,5>, <7,3,0,1> - 4205253944U, // <0,5,7,4>: Cost 3 vsldoi8 <7,4,0,5>, <7,4,0,5> - 3255586977U, // <0,5,7,5>: Cost 4 vsldoi12 <5,6,7,0>, <5,7,5,0> - 3377398135U, // <0,5,7,6>: Cost 4 vmrglw <3,6,0,7>, <0,4,5,6> - 4201272870U, // <0,5,7,7>: Cost 4 vsldoi8 <6,7,0,5>, <7,7,0,0> - 4207908476U, // <0,5,7,u>: Cost 3 vsldoi8 <7,u,0,5>, <7,u,0,5> - 2977112166U, // <0,5,u,0>: Cost 2 vsldoi4 <4,0,5,u>, LHS - 4181366574U, // <0,5,u,1>: Cost 3 vsldoi8 <3,4,0,5>, LHS - 3226709739U, // <0,5,u,2>: Cost 3 vmrghw LHS, <5,2,1,3> - 4050856086U, // <0,5,u,3>: Cost 3 vsldoi4 <4,0,5,u>, <3,0,1,2> - 2977115033U, // <0,5,u,4>: Cost 2 vsldoi4 <4,0,5,u>, <4,0,5,u> - 2152968196U, // <0,5,u,5>: Cost 2 vmrghw LHS, <5,5,5,5> - 2152968290U, // <0,5,u,6>: Cost 2 vmrghw LHS, <5,6,7,0> - 3256914180U, // <0,5,u,7>: Cost 2 vsldoi12 <5,u,7,0>, <5,u,7,0> - 3256987917U, // <0,5,u,u>: Cost 2 vsldoi12 <5,u,u,0>, <5,u,u,0> - 3221229909U, // <0,6,0,0>: Cost 3 vmrghw <0,0,0,0>, <6,0,7,0> - 3221311911U, // <0,6,0,1>: Cost 3 vmrghw <0,0,1,1>, <6,1,7,1> - 3221230074U, // <0,6,0,2>: Cost 3 vmrghw <0,0,0,0>, <6,2,7,3> - 3248877877U, // <0,6,0,3>: Cost 4 vsldoi12 <4,5,6,0>, <6,0,3,4> - 3228750143U, // <0,6,0,4>: Cost 4 vsldoi12 <1,2,3,0>, <6,0,4,5> - 4056837747U, // <0,6,0,5>: Cost 4 vsldoi4 <5,0,6,0>, <5,0,6,0> - 3221230392U, // <0,6,0,6>: Cost 3 vmrghw <0,0,0,0>, <6,6,6,6> - 2281704758U, // <0,6,0,7>: Cost 2 vmrglw <0,0,0,0>, RHS - 2281704759U, // <0,6,0,u>: Cost 2 vmrglw <0,0,0,0>, RHS - 3222065441U, // <0,6,1,0>: Cost 3 vmrghw LHS, <6,0,1,2> - 3222065575U, // <0,6,1,1>: Cost 3 vmrghw LHS, <6,1,7,1> - 2148323834U, // <0,6,1,2>: Cost 2 vmrghw LHS, <6,2,7,3> - 3222065714U, // <0,6,1,3>: Cost 3 vmrghw LHS, <6,3,4,5> - 3222065777U, // <0,6,1,4>: Cost 3 vmrghw LHS, <6,4,2,5> - 3222065899U, // <0,6,1,5>: Cost 3 vmrghw LHS, <6,5,7,1> - 2148324152U, // <0,6,1,6>: Cost 2 vmrghw LHS, <6,6,6,6> - 2295647542U, // <0,6,1,7>: Cost 2 vmrglw <2,3,0,1>, RHS - 2295647543U, // <0,6,1,u>: Cost 2 vmrglw <2,3,0,1>, RHS - 3248878011U, // <0,6,2,0>: Cost 4 vsldoi12 <4,5,6,0>, <6,2,0,3> - 3222655401U, // <0,6,2,1>: Cost 4 vmrghw <0,2,1,3>, <6,1,7,3> - 3222581754U, // <0,6,2,2>: Cost 4 vmrghw <0,2,0,3>, <6,2,7,3> - 3258610131U, // <0,6,2,3>: Cost 4 vsldoi12 <6,2,3,0>, <6,2,3,0> - 4068797750U, // <0,6,2,4>: Cost 4 vsldoi4 <7,0,6,2>, RHS - 4068798562U, // <0,6,2,5>: Cost 4 vsldoi4 <7,0,6,2>, <5,6,7,0> - 4180043706U, // <0,6,2,6>: Cost 4 vsldoi8 <3,2,0,6>, <2,6,3,7> - 3255587322U, // <0,6,2,7>: Cost 3 vsldoi12 <5,6,7,0>, <6,2,7,3> - 3255587331U, // <0,6,2,u>: Cost 3 vsldoi12 <5,6,7,0>, <6,2,u,3> - 4180043926U, // <0,6,3,0>: Cost 4 vsldoi8 <3,2,0,6>, <3,0,1,2> - 3259126290U, // <0,6,3,1>: Cost 4 vsldoi12 <6,3,1,0>, <6,3,1,0> - 4180044083U, // <0,6,3,2>: Cost 4 vsldoi8 <3,2,0,6>, <3,2,0,6> - 3223327282U, // <0,6,3,3>: Cost 4 vmrghw <0,3,1,4>, <6,3,4,5> - 4182034946U, // <0,6,3,4>: Cost 4 vsldoi8 <3,5,0,6>, <3,4,5,6> - 4182034982U, // <0,6,3,5>: Cost 4 vsldoi8 <3,5,0,6>, <3,5,0,6> - 4068807240U, // <0,6,3,6>: Cost 4 vsldoi4 <7,0,6,3>, <6,3,7,0> - 3374714166U, // <0,6,3,7>: Cost 3 vmrglw <3,2,0,3>, RHS - 3374714167U, // <0,6,3,u>: Cost 3 vmrglw <3,2,0,3>, RHS - 4205259666U, // <0,6,4,0>: Cost 4 vsldoi8 <7,4,0,6>, <4,0,5,1> - 3223998891U, // <0,6,4,1>: Cost 3 vmrghw <0,4,1,5>, <6,1,7,5> - 3223998970U, // <0,6,4,2>: Cost 3 vmrghw <0,4,1,5>, <6,2,7,3> - 3223999026U, // <0,6,4,3>: Cost 4 vmrghw <0,4,1,5>, <6,3,4,5> - 3223990941U, // <0,6,4,4>: Cost 4 vmrghw <0,4,1,4>, <6,4,7,4> - 4180045110U, // <0,6,4,5>: Cost 4 vsldoi8 <3,2,0,6>, RHS - 3223999288U, // <0,6,4,6>: Cost 3 vmrghw <0,4,1,5>, <6,6,6,6> - 3364769078U, // <0,6,4,7>: Cost 3 vmrglw <1,5,0,4>, RHS - 3364769079U, // <0,6,4,u>: Cost 3 vmrglw <1,5,0,4>, RHS - 3248878257U, // <0,6,5,0>: Cost 4 vsldoi12 <4,5,6,0>, <6,5,0,6> - 3395964532U, // <0,6,5,1>: Cost 4 vmrglw <6,7,0,5>, <5,0,6,1> - 3260527293U, // <0,6,5,2>: Cost 4 vsldoi12 <6,5,2,0>, <6,5,2,0> - 3376056678U, // <0,6,5,3>: Cost 5 vmrglw <3,4,0,5>, <3,2,6,3> - 4056878390U, // <0,6,5,4>: Cost 4 vsldoi4 <5,0,6,5>, RHS - 3395964860U, // <0,6,5,5>: Cost 4 vmrglw <6,7,0,5>, <5,4,6,5> - 3260822241U, // <0,6,5,6>: Cost 4 vsldoi12 <6,5,6,0>, <6,5,6,0> - 3376057654U, // <0,6,5,7>: Cost 3 vmrglw <3,4,0,5>, RHS - 3376057655U, // <0,6,5,u>: Cost 3 vmrglw <3,4,0,5>, RHS - 3248878332U, // <0,6,6,0>: Cost 4 vsldoi12 <4,5,6,0>, <6,6,0,0> - 3398624745U, // <0,6,6,1>: Cost 4 vmrglw <7,2,0,6>, <2,0,6,1> - 3225301498U, // <0,6,6,2>: Cost 3 vmrghw <0,6,1,2>, <6,2,7,3> - 3225309746U, // <0,6,6,3>: Cost 4 vmrghw <0,6,1,3>, <6,3,4,5> - 4068830518U, // <0,6,6,4>: Cost 4 vsldoi4 <7,0,6,6>, RHS - 4199953073U, // <0,6,6,5>: Cost 4 vsldoi8 <6,5,0,6>, <6,5,0,6> - 3255587640U, // <0,6,6,6>: Cost 3 vsldoi12 <5,6,7,0>, <6,6,6,6> - 3255587650U, // <0,6,6,7>: Cost 3 vsldoi12 <5,6,7,0>, <6,6,7,7> - 3255587659U, // <0,6,6,u>: Cost 3 vsldoi12 <5,6,7,0>, <6,6,u,7> - 3255587662U, // <0,6,7,0>: Cost 3 vsldoi12 <5,6,7,0>, <6,7,0,1> - 3228750680U, // <0,6,7,1>: Cost 3 vsldoi12 <1,2,3,0>, <6,7,1,2> - 3377400084U, // <0,6,7,2>: Cost 4 vmrglw <3,6,0,7>, <3,1,6,2> - 3261928296U, // <0,6,7,3>: Cost 3 vsldoi12 <6,7,3,0>, <6,7,3,0> - 3255587702U, // <0,6,7,4>: Cost 3 vsldoi12 <5,6,7,0>, <6,7,4,5> - 3255587712U, // <0,6,7,5>: Cost 3 vsldoi12 <5,6,7,0>, <6,7,5,6> - 3255587717U, // <0,6,7,6>: Cost 4 vsldoi12 <5,6,7,0>, <6,7,6,2> - 3377401142U, // <0,6,7,7>: Cost 3 vmrglw <3,6,0,7>, RHS - 3377401143U, // <0,6,7,u>: Cost 3 vmrglw <3,6,0,7>, RHS - 3255587743U, // <0,6,u,0>: Cost 3 vsldoi12 <5,6,7,0>, <6,u,0,1> - 3226710439U, // <0,6,u,1>: Cost 3 vmrghw LHS, <6,1,7,1> - 2152968698U, // <0,6,u,2>: Cost 2 vmrghw LHS, <6,2,7,3> - 3262591929U, // <0,6,u,3>: Cost 3 vsldoi12 <6,u,3,0>, <6,u,3,0> - 3255587783U, // <0,6,u,4>: Cost 3 vsldoi12 <5,6,7,0>, <6,u,4,5> - 3255587712U, // <0,6,u,5>: Cost 3 vsldoi12 <5,6,7,0>, <6,7,5,6> - 2152969016U, // <0,6,u,6>: Cost 2 vmrghw LHS, <6,6,6,6> - 2295704886U, // <0,6,u,7>: Cost 2 vmrglw <2,3,0,u>, RHS - 2295704887U, // <0,6,u,u>: Cost 2 vmrglw <2,3,0,u>, RHS - 4062879744U, // <0,7,0,0>: Cost 3 vsldoi4 <6,0,7,0>, <0,0,0,0> - 4182704230U, // <0,7,0,1>: Cost 3 vsldoi8 <3,6,0,7>, LHS - 4044965818U, // <0,7,0,2>: Cost 4 vsldoi4 <3,0,7,0>, <2,6,3,7> - 3355447802U, // <0,7,0,3>: Cost 3 vmrglw <0,0,0,0>, <6,2,7,3> - 3255587864U, // <0,7,0,4>: Cost 3 vsldoi12 <5,6,7,0>, <7,0,4,5> - 3255587874U, // <0,7,0,5>: Cost 3 vsldoi12 <5,6,7,0>, <7,0,5,6> - 4062884181U, // <0,7,0,6>: Cost 3 vsldoi4 <6,0,7,0>, <6,0,7,0> - 3221231212U, // <0,7,0,7>: Cost 3 vmrghw <0,0,0,0>, <7,7,7,7> - 4182704797U, // <0,7,0,u>: Cost 3 vsldoi8 <3,6,0,7>, LHS - 2148324346U, // <0,7,1,0>: Cost 2 vmrghw LHS, <7,0,1,2> - 3222066250U, // <0,7,1,1>: Cost 3 vmrghw LHS, <7,1,1,1> - 4182705046U, // <0,7,1,2>: Cost 3 vsldoi8 <3,6,0,7>, <1,2,3,0> - 3395932666U, // <0,7,1,3>: Cost 3 vmrglw <6,7,0,1>, <6,2,7,3> - 2148324710U, // <0,7,1,4>: Cost 2 vmrghw LHS, <7,4,5,6> - 3222066614U, // <0,7,1,5>: Cost 3 vmrghw LHS, <7,5,5,5> - 4062892374U, // <0,7,1,6>: Cost 3 vsldoi4 <6,0,7,1>, <6,0,7,1> - 2148324972U, // <0,7,1,7>: Cost 2 vmrghw LHS, <7,7,7,7> - 2148324994U, // <0,7,1,u>: Cost 2 vmrghw LHS, <7,u,1,2> - 3255587988U, // <0,7,2,0>: Cost 3 vsldoi12 <5,6,7,0>, <7,2,0,3> - 4170761760U, // <0,7,2,1>: Cost 5 vsldoi8 <1,6,0,7>, <2,1,3,2> - 4182705768U, // <0,7,2,2>: Cost 4 vsldoi8 <3,6,0,7>, <2,2,2,2> - 3264582828U, // <0,7,2,3>: Cost 3 vsldoi12 <7,2,3,0>, <7,2,3,0> - 3255661752U, // <0,7,2,4>: Cost 4 vsldoi12 <5,6,u,0>, <7,2,4,3> - 4068872290U, // <0,7,2,5>: Cost 4 vsldoi4 <7,0,7,2>, <5,6,7,0> - 4180715450U, // <0,7,2,6>: Cost 4 vsldoi8 <3,3,0,7>, <2,6,3,7> - 4068873264U, // <0,7,2,7>: Cost 4 vsldoi4 <7,0,7,2>, <7,0,7,2> - 3264951513U, // <0,7,2,u>: Cost 3 vsldoi12 <7,2,u,0>, <7,2,u,0> - 3398602850U, // <0,7,3,0>: Cost 3 vmrglw <7,2,0,3>, <5,6,7,0> - 4182706417U, // <0,7,3,1>: Cost 4 vsldoi8 <3,6,0,7>, <3,1,2,3> - 4182706480U, // <0,7,3,2>: Cost 4 vsldoi8 <3,6,0,7>, <3,2,0,3> - 4180715909U, // <0,7,3,3>: Cost 4 vsldoi8 <3,3,0,7>, <3,3,0,7> - 4182706690U, // <0,7,3,4>: Cost 4 vsldoi8 <3,6,0,7>, <3,4,5,6> - 4206594653U, // <0,7,3,5>: Cost 4 vsldoi8 <7,6,0,7>, <3,5,6,7> - 4182706808U, // <0,7,3,6>: Cost 3 vsldoi8 <3,6,0,7>, <3,6,0,7> - 3398603586U, // <0,7,3,7>: Cost 4 vmrglw <7,2,0,3>, <6,6,7,7> - 4184034074U, // <0,7,3,u>: Cost 3 vsldoi8 <3,u,0,7>, <3,u,0,7> - 3223999482U, // <0,7,4,0>: Cost 3 vmrghw <0,4,1,5>, <7,0,1,2> - 4062913430U, // <0,7,4,1>: Cost 4 vsldoi4 <6,0,7,4>, <1,2,3,0> - 3223999636U, // <0,7,4,2>: Cost 4 vmrghw <0,4,1,5>, <7,2,0,3> - 4062915192U, // <0,7,4,3>: Cost 4 vsldoi4 <6,0,7,4>, <3,6,0,7> - 3223999846U, // <0,7,4,4>: Cost 3 vmrghw <0,4,1,5>, <7,4,5,6> - 4182707510U, // <0,7,4,5>: Cost 3 vsldoi8 <3,6,0,7>, RHS - 4188679505U, // <0,7,4,6>: Cost 4 vsldoi8 <4,6,0,7>, <4,6,0,7> - 3224000108U, // <0,7,4,7>: Cost 3 vmrghw <0,4,1,5>, <7,7,7,7> - 4182707753U, // <0,7,4,u>: Cost 3 vsldoi8 <3,6,0,7>, RHS - 3395965026U, // <0,7,5,0>: Cost 3 vmrglw <6,7,0,5>, <5,6,7,0> - 3399946987U, // <0,7,5,1>: Cost 4 vmrglw <7,4,0,5>, <6,5,7,1> - 3224671380U, // <0,7,5,2>: Cost 4 vmrghw <0,5,1,6>, <7,2,0,3> - 4062922902U, // <0,7,5,3>: Cost 4 vsldoi4 <6,0,7,5>, <3,0,1,2> - 4062924086U, // <0,7,5,4>: Cost 4 vsldoi4 <6,0,7,5>, RHS - 3255588278U, // <0,7,5,5>: Cost 4 vsldoi12 <5,6,7,0>, <7,5,5,5> - 3255588289U, // <0,7,5,6>: Cost 3 vsldoi12 <5,6,7,0>, <7,5,6,7> - 3395965762U, // <0,7,5,7>: Cost 4 vmrglw <6,7,0,5>, <6,6,7,7> - 3256915411U, // <0,7,5,u>: Cost 3 vsldoi12 <5,u,7,0>, <7,5,u,7> - 3255588316U, // <0,7,6,0>: Cost 3 vsldoi12 <5,6,7,0>, <7,6,0,7> - 4182708604U, // <0,7,6,1>: Cost 5 vsldoi8 <3,6,0,7>, <6,1,2,3> - 3255588334U, // <0,7,6,2>: Cost 4 vsldoi12 <5,6,7,0>, <7,6,2,7> - 3270555127U, // <0,7,6,3>: Cost 4 vsldoi12 , <7,6,3,7> - 3255662080U, // <0,7,6,4>: Cost 4 vsldoi12 <5,6,u,0>, <7,6,4,7> - 4068905058U, // <0,7,6,5>: Cost 4 vsldoi4 <7,0,7,6>, <5,6,7,0> - 3255588369U, // <0,7,6,6>: Cost 4 vsldoi12 <5,6,7,0>, <7,6,6,6> - 3267532308U, // <0,7,6,7>: Cost 3 vsldoi12 <7,6,7,0>, <7,6,7,0> - 3267606045U, // <0,7,6,u>: Cost 3 vsldoi12 <7,6,u,0>, <7,6,u,0> - 3255588390U, // <0,7,7,0>: Cost 3 vsldoi12 <5,6,7,0>, <7,7,0,0> - 4062938006U, // <0,7,7,1>: Cost 4 vsldoi4 <6,0,7,7>, <1,2,3,0> - 3264583227U, // <0,7,7,2>: Cost 4 vsldoi12 <7,2,3,0>, <7,7,2,3> - 3377397988U, // <0,7,7,3>: Cost 4 vmrglw <3,6,0,7>, <0,2,7,3> - 3225982310U, // <0,7,7,4>: Cost 3 vmrghw <0,7,1,4>, <7,4,5,6> - 3255588441U, // <0,7,7,5>: Cost 4 vsldoi12 <5,6,7,0>, <7,7,5,6> - 4206597596U, // <0,7,7,6>: Cost 3 vsldoi8 <7,6,0,7>, <7,6,0,7> - 3255588460U, // <0,7,7,7>: Cost 3 vsldoi12 <5,6,7,0>, <7,7,7,7> - 4207924862U, // <0,7,7,u>: Cost 3 vsldoi8 <7,u,0,7>, <7,u,0,7> - 2152969210U, // <0,7,u,0>: Cost 2 vmrghw LHS, <7,0,1,2> - 4182710062U, // <0,7,u,1>: Cost 3 vsldoi8 <3,6,0,7>, LHS - 4062946989U, // <0,7,u,2>: Cost 3 vsldoi4 <6,0,7,u>, <2,3,0,u> - 3395990010U, // <0,7,u,3>: Cost 3 vmrglw <6,7,0,u>, <6,2,7,3> - 2152969574U, // <0,7,u,4>: Cost 2 vmrghw LHS, <7,4,5,6> - 4182710426U, // <0,7,u,5>: Cost 3 vsldoi8 <3,6,0,7>, RHS - 4062949725U, // <0,7,u,6>: Cost 3 vsldoi4 <6,0,7,u>, <6,0,7,u> - 2152969836U, // <0,7,u,7>: Cost 2 vmrghw LHS, <7,7,7,7> - 2152969858U, // <0,7,u,u>: Cost 2 vmrghw LHS, <7,u,1,2> - 1343012966U, // <0,u,0,0>: Cost 1 vspltisw0 LHS - 3101007974U, // <0,u,0,1>: Cost 2 vsldoi8 <2,3,0,u>, LHS - 4039067130U, // <0,u,0,2>: Cost 3 vsldoi4 <2,0,u,0>, <2,0,u,0> - 2281701532U, // <0,u,0,3>: Cost 2 vmrglw <0,0,0,0>, LHS - 2953383222U, // <0,u,0,4>: Cost 2 vsldoi4 <0,0,u,0>, RHS - 2147489946U, // <0,u,0,5>: Cost 2 vmrghw <0,0,0,0>, RHS - 4174750261U, // <0,u,0,6>: Cost 3 vsldoi8 <2,3,0,u>, <0,6,u,7> - 2281704776U, // <0,u,0,7>: Cost 2 vmrglw <0,0,0,0>, RHS - 1343012966U, // <0,u,0,u>: Cost 1 vspltisw0 LHS - 2148767443U, // <0,u,1,0>: Cost 2 vmrghw LHS, - 1074583342U, // <0,u,1,1>: Cost 1 vmrghw LHS, LHS - 2148808584U, // <0,u,1,2>: Cost 2 vmrghw LHS, - 2148808636U, // <0,u,1,3>: Cost 2 vmrghw LHS, - 2148767807U, // <0,u,1,4>: Cost 2 vmrghw LHS, - 1074583706U, // <0,u,1,5>: Cost 1 vmrghw LHS, RHS - 2148808912U, // <0,u,1,6>: Cost 2 vmrghw LHS, - 2295647560U, // <0,u,1,7>: Cost 2 vmrglw <2,3,0,1>, RHS - 1074583909U, // <0,u,1,u>: Cost 1 vmrghw LHS, LHS - 2971312230U, // <0,u,2,0>: Cost 2 vsldoi4 <3,0,u,2>, LHS - 3222648622U, // <0,u,2,1>: Cost 3 vmrghw <0,2,1,2>, LHS - 4174751336U, // <0,u,2,2>: Cost 3 vsldoi8 <2,3,0,u>, <2,2,2,2> + 3355444685U, // <0,2,0,0>: Cost 3 vmrghw <0,0,0,0>, <2,0,3,0> + 3355526687U, // <0,2,0,1>: Cost 3 vmrghw <0,0,1,1>, <2,1,3,1> + 3355444840U, // <0,2,0,2>: Cost 3 vmrghw <0,0,0,0>, <2,2,2,2> + 2415919206U, // <0,2,0,3>: Cost 2 vmrglw <0,0,0,0>, LHS + 4178816310U, // <0,2,0,4>: Cost 4 vsldoi4 <3,0,2,0>, RHS + 3509568564U, // <0,2,0,5>: Cost 4 vmrglw <3,3,0,0>, <1,4,2,5> + 3355445178U, // <0,2,0,6>: Cost 3 vmrghw <0,0,0,0>, <2,6,3,7> + 3355445226U, // <0,2,0,7>: Cost 4 vmrghw <0,0,0,0>, <2,7,0,1> + 2415919211U, // <0,2,0,u>: Cost 2 vmrglw <0,0,0,0>, LHS + 3356722682U, // <0,2,1,0>: Cost 3 vmrghw LHS, <2,0,u,0> + 3356321311U, // <0,2,1,1>: Cost 3 vmrghw LHS, <2,1,3,1> + 2282579560U, // <0,2,1,2>: Cost 2 vmrghw LHS, <2,2,2,2> + 2282579622U, // <0,2,1,3>: Cost 2 vmrghw LHS, <2,3,0,1> + 3356723011U, // <0,2,1,4>: Cost 3 vmrghw LHS, <2,4,u,5> + 3356723093U, // <0,2,1,5>: Cost 3 vmrghw LHS, <2,5,u,6> + 2282579898U, // <0,2,1,6>: Cost 2 vmrghw LHS, <2,6,3,7> + 3356280810U, // <0,2,1,7>: Cost 3 vmrghw LHS, <2,7,0,1> + 2282580056U, // <0,2,1,u>: Cost 2 vmrghw LHS, <2,u,3,3> + 3356845562U, // <0,2,2,0>: Cost 4 vmrghw <0,2,1,0>, <2,0,u,0> + 3356853791U, // <0,2,2,1>: Cost 4 vmrghw <0,2,1,1>, <2,1,3,1> + 3356862056U, // <0,2,2,2>: Cost 3 vmrghw <0,2,1,2>, <2,2,2,2> + 3356870310U, // <0,2,2,3>: Cost 3 vmrghw <0,2,1,3>, <2,3,0,1> + 3356878659U, // <0,2,2,4>: Cost 4 vmrghw <0,2,1,4>, <2,4,u,5> + 3356886933U, // <0,2,2,5>: Cost 4 vmrghw <0,2,1,5>, <2,5,u,6> + 3356895162U, // <0,2,2,6>: Cost 3 vmrghw <0,2,1,6>, <2,6,3,7> + 4202722307U, // <0,2,2,7>: Cost 4 vsldoi4 <7,0,2,2>, <7,0,2,2> + 3356911704U, // <0,2,2,u>: Cost 3 vmrghw <0,2,1,u>, <2,u,3,3> + 3362965158U, // <0,2,3,0>: Cost 3 vsldoi12 <1,2,3,0>, <2,3,0,1> + 3362965168U, // <0,2,3,1>: Cost 3 vsldoi12 <1,2,3,0>, <2,3,1,2> + 3357509224U, // <0,2,3,2>: Cost 4 vmrghw <0,3,1,0>, <2,2,2,2> + 3362965184U, // <0,2,3,3>: Cost 3 vsldoi12 <1,2,3,0>, <2,3,3,0> + 3362965198U, // <0,2,3,4>: Cost 3 vsldoi12 <1,2,3,0>, <2,3,4,5> + 3389802200U, // <0,2,3,5>: Cost 3 vsldoi12 <5,6,7,0>, <2,3,5,6> + 3357509562U, // <0,2,3,6>: Cost 4 vmrghw <0,3,1,0>, <2,6,3,7> + 3369895652U, // <0,2,3,7>: Cost 3 vsldoi12 <2,3,7,0>, <2,3,7,0> + 3362965229U, // <0,2,3,u>: Cost 3 vsldoi12 <1,2,3,0>, <2,3,u,0> + 3358213626U, // <0,2,4,0>: Cost 4 vmrghw <0,4,1,5>, <2,0,u,0> + 3358213667U, // <0,2,4,1>: Cost 3 vmrghw <0,4,1,5>, <2,1,3,5> + 3358213736U, // <0,2,4,2>: Cost 3 vmrghw <0,4,1,5>, <2,2,2,2> + 3358213798U, // <0,2,4,3>: Cost 3 vmrghw <0,4,1,5>, <2,3,0,1> + 3358213951U, // <0,2,4,4>: Cost 4 vmrghw <0,4,1,5>, <2,4,u,1> + 3358214037U, // <0,2,4,5>: Cost 4 vmrghw <0,4,1,5>, <2,5,u,6> + 3358214074U, // <0,2,4,6>: Cost 3 vmrghw <0,4,1,5>, <2,6,3,7> + 3251768776U, // <0,2,4,7>: Cost 4 vsldoi8 <5,1,0,2>, <4,7,5,0> + 3358214203U, // <0,2,4,u>: Cost 3 vmrghw <0,4,1,5>, <2,u,0,1> + 3510272099U, // <0,2,5,0>: Cost 4 vmrglw <3,4,0,5>, <0,1,2,0> + 3251768976U, // <0,2,5,1>: Cost 4 vsldoi8 <5,1,0,2>, <5,1,0,2> + 3510273640U, // <0,2,5,2>: Cost 4 vmrglw <3,4,0,5>, <2,2,2,2> + 3510272102U, // <0,2,5,3>: Cost 3 vmrglw <3,4,0,5>, LHS + 3510272103U, // <0,2,5,4>: Cost 4 vmrglw <3,4,0,5>, <0,1,2,4> + 3508945972U, // <0,2,5,5>: Cost 4 vmrglw <3,2,0,5>, <1,4,2,5> + 3268358242U, // <0,2,5,6>: Cost 4 vsldoi8 <7,u,0,2>, <5,6,7,0> + 3510273240U, // <0,2,5,7>: Cost 4 vmrglw <3,4,0,5>, <1,6,2,7> + 3510272107U, // <0,2,5,u>: Cost 3 vmrglw <3,4,0,5>, LHS + 4178862182U, // <0,2,6,0>: Cost 4 vsldoi4 <3,0,2,6>, LHS + 4178862998U, // <0,2,6,1>: Cost 4 vsldoi4 <3,0,2,6>, <1,2,3,0> + 4178864058U, // <0,2,6,2>: Cost 4 vsldoi4 <3,0,2,6>, <2,6,3,7> + 3362965434U, // <0,2,6,3>: Cost 3 vsldoi12 <1,2,3,0>, <2,6,3,7> + 4178865462U, // <0,2,6,4>: Cost 4 vsldoi4 <3,0,2,6>, RHS + 4202754146U, // <0,2,6,5>: Cost 4 vsldoi4 <7,0,2,6>, <5,6,7,0> + 3359483834U, // <0,2,6,6>: Cost 4 vmrghw <0,6,0,7>, <2,6,3,7> + 3261723471U, // <0,2,6,7>: Cost 4 vsldoi8 <6,7,0,2>, <6,7,0,2> + 3362965479U, // <0,2,6,u>: Cost 3 vsldoi12 <1,2,3,0>, <2,6,u,7> + 3251770362U, // <0,2,7,0>: Cost 4 vsldoi8 <5,1,0,2>, <7,0,1,2> + 3511616236U, // <0,2,7,1>: Cost 4 vmrglw <3,6,0,7>, <1,0,2,1> + 3511616318U, // <0,2,7,2>: Cost 4 vmrglw <3,6,0,7>, <1,1,2,2> + 3511615590U, // <0,2,7,3>: Cost 3 vmrglw <3,6,0,7>, LHS + 4178873654U, // <0,2,7,4>: Cost 4 vsldoi4 <3,0,2,7>, RHS + 3511616564U, // <0,2,7,5>: Cost 4 vmrglw <3,6,0,7>, <1,4,2,5> + 3267032535U, // <0,2,7,6>: Cost 4 vsldoi8 <7,6,0,2>, <7,6,0,2> + 3360163818U, // <0,2,7,7>: Cost 4 vmrghw <0,7,1,0>, <2,7,0,1> + 3511615595U, // <0,2,7,u>: Cost 3 vmrglw <3,6,0,7>, LHS + 3360925178U, // <0,2,u,0>: Cost 3 vmrghw LHS, <2,0,u,0> + 3360925215U, // <0,2,u,1>: Cost 3 vmrghw LHS, <2,1,3,1> + 2287183464U, // <0,2,u,2>: Cost 2 vmrghw LHS, <2,2,2,2> + 2287183526U, // <0,2,u,3>: Cost 2 vmrghw LHS, <2,3,0,1> + 3360925507U, // <0,2,u,4>: Cost 3 vmrghw LHS, <2,4,u,5> + 3360925589U, // <0,2,u,5>: Cost 3 vmrghw LHS, <2,5,u,6> + 2287183802U, // <0,2,u,6>: Cost 2 vmrghw LHS, <2,6,3,7> + 3360925674U, // <0,2,u,7>: Cost 3 vmrghw LHS, <2,7,0,1> + 2287183931U, // <0,2,u,u>: Cost 2 vmrghw LHS, <2,u,0,1> + 4172914688U, // <0,3,0,0>: Cost 3 vsldoi4 <2,0,3,0>, <0,0,0,0> + 3357509782U, // <0,3,0,1>: Cost 3 vsldoi12 <0,3,1,0>, <3,0,1,2> + 4172916173U, // <0,3,0,2>: Cost 3 vsldoi4 <2,0,3,0>, <2,0,3,0> + 3355445660U, // <0,3,0,3>: Cost 3 vmrghw <0,0,0,0>, <3,3,3,3> + 3362965684U, // <0,3,0,4>: Cost 3 vsldoi12 <1,2,3,0>, <3,0,4,5> + 4202778722U, // <0,3,0,5>: Cost 4 vsldoi4 <7,0,3,0>, <5,6,7,0> + 3240493576U, // <0,3,0,6>: Cost 4 vsldoi8 <3,2,0,3>, <0,6,3,7> + 3489662906U, // <0,3,0,7>: Cost 3 vmrglw <0,0,0,0>, <2,6,3,7> + 3362965717U, // <0,3,0,u>: Cost 3 vsldoi12 <1,2,3,0>, <3,0,u,2> + 2282580118U, // <0,3,1,0>: Cost 2 vmrghw LHS, <3,0,1,2> + 3356322022U, // <0,3,1,1>: Cost 3 vmrghw LHS, <3,1,1,1> + 3356322113U, // <0,3,1,2>: Cost 3 vmrghw LHS, <3,2,2,2> + 2282580380U, // <0,3,1,3>: Cost 2 vmrghw LHS, <3,3,3,3> + 2282580482U, // <0,3,1,4>: Cost 2 vmrghw LHS, <3,4,5,6> + 3356281426U, // <0,3,1,5>: Cost 3 vmrghw LHS, <3,5,5,5> + 3356281464U, // <0,3,1,6>: Cost 3 vmrghw LHS, <3,6,0,7> + 3503605690U, // <0,3,1,7>: Cost 3 vmrglw <2,3,0,1>, <2,6,3,7> + 2282580766U, // <0,3,1,u>: Cost 2 vmrghw LHS, <3,u,1,2> + 3362965808U, // <0,3,2,0>: Cost 3 vsldoi12 <1,2,3,0>, <3,2,0,3> + 4178903958U, // <0,3,2,1>: Cost 4 vsldoi4 <3,0,3,2>, <1,2,3,0> + 3356862785U, // <0,3,2,2>: Cost 4 vmrghw <0,2,1,2>, <3,2,2,2> + 3374909768U, // <0,3,2,3>: Cost 3 vsldoi12 <3,2,3,0>, <3,2,3,0> + 3356862978U, // <0,3,2,4>: Cost 4 vmrghw <0,2,1,2>, <3,4,5,6> + 3496313188U, // <0,3,2,5>: Cost 5 vmrglw <1,1,0,2>, <0,4,3,5> + 3362965862U, // <0,3,2,6>: Cost 4 vsldoi12 <1,2,3,0>, <3,2,6,3> + 3499632570U, // <0,3,2,7>: Cost 4 vmrglw <1,6,0,2>, <2,6,3,7> + 3375278453U, // <0,3,2,u>: Cost 3 vsldoi12 <3,2,u,0>, <3,2,u,0> + 3357509782U, // <0,3,3,0>: Cost 3 vmrghw <0,3,1,0>, <3,0,1,2> + 3357518054U, // <0,3,3,1>: Cost 4 vmrghw <0,3,1,1>, <3,1,1,1> + 3240495408U, // <0,3,3,2>: Cost 3 vsldoi8 <3,2,0,3>, <3,2,0,3> + 3357534620U, // <0,3,3,3>: Cost 3 vmrghw <0,3,1,3>, <3,3,3,3> + 3357542914U, // <0,3,3,4>: Cost 3 vmrghw <0,3,1,4>, <3,4,5,6> + 4202803298U, // <0,3,3,5>: Cost 4 vsldoi4 <7,0,3,3>, <5,6,7,0> + 3362965940U, // <0,3,3,6>: Cost 4 vsldoi12 <1,2,3,0>, <3,3,6,0> + 3508930490U, // <0,3,3,7>: Cost 4 vmrglw <3,2,0,3>, <2,6,3,7> + 3357575966U, // <0,3,3,u>: Cost 3 vmrghw <0,3,1,u>, <3,u,1,2> + 3358214294U, // <0,3,4,0>: Cost 3 vmrghw <0,4,1,5>, <3,0,1,2> + 3358214374U, // <0,3,4,1>: Cost 4 vmrghw <0,4,1,5>, <3,1,1,1> + 3358214465U, // <0,3,4,2>: Cost 4 vmrghw <0,4,1,5>, <3,2,2,2> + 3358214556U, // <0,3,4,3>: Cost 3 vmrghw <0,4,1,5>, <3,3,3,3> + 3358214658U, // <0,3,4,4>: Cost 3 vmrghw <0,4,1,5>, <3,4,5,6> + 3362966018U, // <0,3,4,5>: Cost 3 vsldoi12 <1,2,3,0>, <3,4,5,6> + 4196839733U, // <0,3,4,6>: Cost 4 vsldoi4 <6,0,3,4>, <6,0,3,4> + 3498985402U, // <0,3,4,7>: Cost 4 vmrglw <1,5,0,4>, <2,6,3,7> + 3358214942U, // <0,3,4,u>: Cost 3 vmrghw <0,4,1,5>, <3,u,1,2> + 3362966054U, // <0,3,5,0>: Cost 4 vsldoi12 <1,2,3,0>, <3,5,0,6> + 3540133731U, // <0,3,5,1>: Cost 4 vmrglw , <2,5,3,1> + 3510273568U, // <0,3,5,2>: Cost 4 vmrglw <3,4,0,5>, <2,1,3,2> + 3510273407U, // <0,3,5,3>: Cost 4 vmrglw <3,4,0,5>, <1,u,3,3> + 3510272922U, // <0,3,5,4>: Cost 4 vmrglw <3,4,0,5>, <1,2,3,4> + 3389803090U, // <0,3,5,5>: Cost 4 vsldoi12 <5,6,7,0>, <3,5,5,5> + 3264385122U, // <0,3,5,6>: Cost 3 vsldoi8 <7,2,0,3>, <5,6,7,0> + 3510273978U, // <0,3,5,7>: Cost 4 vmrglw <3,4,0,5>, <2,6,3,7> + 3264385122U, // <0,3,5,u>: Cost 3 vsldoi8 <7,2,0,3>, <5,6,7,0> + 3362966136U, // <0,3,6,0>: Cost 3 vsldoi12 <1,2,3,0>, <3,6,0,7> + 4178936726U, // <0,3,6,1>: Cost 4 vsldoi4 <3,0,3,6>, <1,2,3,0> + 3258413499U, // <0,3,6,2>: Cost 4 vsldoi8 <6,2,0,3>, <6,2,0,3> + 4178938028U, // <0,3,6,3>: Cost 4 vsldoi4 <3,0,3,6>, <3,0,3,6> + 3363334812U, // <0,3,6,4>: Cost 4 vsldoi12 <1,2,u,0>, <3,6,4,7> + 3510945963U, // <0,3,6,5>: Cost 5 vmrglw <3,5,0,6>, <3,0,3,5> + 3389803181U, // <0,3,6,6>: Cost 4 vsldoi12 <5,6,7,0>, <3,6,6,6> + 3377859248U, // <0,3,6,7>: Cost 3 vsldoi12 <3,6,7,0>, <3,6,7,0> + 3362966136U, // <0,3,6,u>: Cost 3 vsldoi12 <1,2,3,0>, <3,6,0,7> + 3511616406U, // <0,3,7,0>: Cost 3 vmrglw <3,6,0,7>, <1,2,3,0> + 3270358106U, // <0,3,7,1>: Cost 4 vsldoi8 , <7,1,2,u> + 3264386196U, // <0,3,7,2>: Cost 3 vsldoi8 <7,2,0,3>, <7,2,0,3> + 3511617138U, // <0,3,7,3>: Cost 4 vmrglw <3,6,0,7>, <2,2,3,3> + 3511616410U, // <0,3,7,4>: Cost 4 vmrglw <3,6,0,7>, <1,2,3,4> + 3264386497U, // <0,3,7,5>: Cost 4 vsldoi8 <7,2,0,3>, <7,5,6,7> + 3511617708U, // <0,3,7,6>: Cost 4 vmrglw <3,6,0,7>, <3,0,3,6> + 3509626810U, // <0,3,7,7>: Cost 4 vmrglw <3,3,0,7>, <2,6,3,7> + 3268367994U, // <0,3,7,u>: Cost 3 vsldoi8 <7,u,0,3>, <7,u,0,3> + 2287184022U, // <0,3,u,0>: Cost 2 vmrghw LHS, <3,0,1,2> + 3360925926U, // <0,3,u,1>: Cost 3 vmrghw LHS, <3,1,1,1> + 3360926017U, // <0,3,u,2>: Cost 3 vmrghw LHS, <3,2,2,2> + 2287184284U, // <0,3,u,3>: Cost 2 vmrghw LHS, <3,3,3,3> + 2287184386U, // <0,3,u,4>: Cost 2 vmrghw LHS, <3,4,5,6> + 3362966342U, // <0,3,u,5>: Cost 3 vsldoi12 <1,2,3,0>, <3,u,5,6> + 3407719248U, // <0,3,u,6>: Cost 3 vsldoi12 , <3,u,6,7> + 3503663034U, // <0,3,u,7>: Cost 3 vmrglw <2,3,0,u>, <2,6,3,7> + 2287184670U, // <0,3,u,u>: Cost 2 vmrghw LHS, <3,u,1,2> + 3355446161U, // <0,4,0,0>: Cost 3 vmrghw <0,0,0,0>, <4,0,5,0> + 3230548070U, // <0,4,0,1>: Cost 3 vsldoi8 <1,5,0,4>, LHS + 3369675641U, // <0,4,0,2>: Cost 4 vsldoi12 <2,3,4,0>, <4,0,2,3> + 4178962607U, // <0,4,0,3>: Cost 4 vsldoi4 <3,0,4,0>, <3,0,4,0> + 3230548306U, // <0,4,0,4>: Cost 3 vsldoi8 <1,5,0,4>, <0,4,1,5> + 2281704758U, // <0,4,0,5>: Cost 2 vmrghw <0,0,0,0>, RHS + 3230548497U, // <0,4,0,6>: Cost 4 vsldoi8 <1,5,0,4>, <0,6,4,7> + 3384347556U, // <0,4,0,7>: Cost 4 vsldoi12 <4,7,5,0>, <4,0,7,1> + 2281705001U, // <0,4,0,u>: Cost 2 vmrghw <0,0,0,0>, RHS + 2282539922U, // <0,4,1,0>: Cost 2 vmrghw LHS, <4,0,5,1> + 3356281802U, // <0,4,1,1>: Cost 3 vmrghw LHS, <4,1,2,3> + 3356281909U, // <0,4,1,2>: Cost 3 vmrghw LHS, <4,2,5,2> + 4178970800U, // <0,4,1,3>: Cost 3 vsldoi4 <3,0,4,1>, <3,0,4,1> + 2282540240U, // <0,4,1,4>: Cost 2 vmrghw LHS, <4,4,4,4> + 1208798518U, // <0,4,1,5>: Cost 1 vmrghw LHS, RHS + 3356282233U, // <0,4,1,6>: Cost 3 vmrghw LHS, <4,6,5,2> + 4202861588U, // <0,4,1,7>: Cost 3 vsldoi4 <7,0,4,1>, <7,0,4,1> + 1208798761U, // <0,4,1,u>: Cost 1 vmrghw LHS, RHS + 3230549457U, // <0,4,2,0>: Cost 4 vsldoi8 <1,5,0,4>, <2,0,3,4> + 3230549539U, // <0,4,2,1>: Cost 4 vsldoi8 <1,5,0,4>, <2,1,3,5> + 3230549608U, // <0,4,2,2>: Cost 4 vsldoi8 <1,5,0,4>, <2,2,2,2> + 3235194537U, // <0,4,2,3>: Cost 3 vsldoi8 <2,3,0,4>, <2,3,0,4> + 4178980150U, // <0,4,2,4>: Cost 4 vsldoi4 <3,0,4,2>, RHS + 3356863798U, // <0,4,2,5>: Cost 3 vmrghw <0,2,1,2>, RHS + 3230549946U, // <0,4,2,6>: Cost 4 vsldoi8 <1,5,0,4>, <2,6,3,7> + 3237849069U, // <0,4,2,7>: Cost 4 vsldoi8 <2,7,0,4>, <2,7,0,4> + 3356864041U, // <0,4,2,u>: Cost 3 vmrghw <0,2,1,2>, RHS + 3230550166U, // <0,4,3,0>: Cost 4 vsldoi8 <1,5,0,4>, <3,0,1,2> + 3239839968U, // <0,4,3,1>: Cost 4 vsldoi8 <3,1,0,4>, <3,1,0,4> + 3363335277U, // <0,4,3,2>: Cost 5 vsldoi12 <1,2,u,0>, <4,3,2,4> + 3230550428U, // <0,4,3,3>: Cost 4 vsldoi8 <1,5,0,4>, <3,3,3,3> + 3230550530U, // <0,4,3,4>: Cost 4 vsldoi8 <1,5,0,4>, <3,4,5,6> + 3357510966U, // <0,4,3,5>: Cost 3 vmrghw <0,3,1,0>, RHS + 3363335313U, // <0,4,3,6>: Cost 5 vsldoi12 <1,2,u,0>, <4,3,6,4> + 3243821766U, // <0,4,3,7>: Cost 4 vsldoi8 <3,7,0,4>, <3,7,0,4> + 3357511209U, // <0,4,3,u>: Cost 3 vmrghw <0,3,1,0>, RHS + 4161077288U, // <0,4,4,0>: Cost 3 vsldoi4 <0,0,4,4>, <0,0,4,4> + 3358215138U, // <0,4,4,1>: Cost 3 vmrghw <0,4,1,5>, <4,1,5,0> + 4161078819U, // <0,4,4,2>: Cost 4 vsldoi4 <0,0,4,4>, <2,1,3,5> + 4178995379U, // <0,4,4,3>: Cost 4 vsldoi4 <3,0,4,4>, <3,0,4,4> + 3389803728U, // <0,4,4,4>: Cost 3 vsldoi12 <5,6,7,0>, <4,4,4,4> + 2284473654U, // <0,4,4,5>: Cost 2 vmrghw <0,4,1,5>, RHS + 4161081771U, // <0,4,4,6>: Cost 4 vsldoi4 <0,0,4,4>, <6,1,7,5> + 3384347884U, // <0,4,4,7>: Cost 4 vsldoi12 <4,7,5,0>, <4,4,7,5> + 2284473897U, // <0,4,4,u>: Cost 2 vmrghw <0,4,1,5>, RHS + 4179001446U, // <0,4,5,0>: Cost 3 vsldoi4 <3,0,4,5>, LHS + 4179002262U, // <0,4,5,1>: Cost 3 vsldoi4 <3,0,4,5>, <1,2,3,0> + 4179002984U, // <0,4,5,2>: Cost 4 vsldoi4 <3,0,4,5>, <2,2,2,2> + 4179003572U, // <0,4,5,3>: Cost 3 vsldoi4 <3,0,4,5>, <3,0,4,5> + 4179004726U, // <0,4,5,4>: Cost 3 vsldoi4 <3,0,4,5>, RHS + 3389803820U, // <0,4,5,5>: Cost 3 vsldoi12 <5,6,7,0>, <4,5,5,6> + 3362966838U, // <0,4,5,6>: Cost 2 vsldoi12 <1,2,3,0>, RHS + 4202894360U, // <0,4,5,7>: Cost 3 vsldoi4 <7,0,4,5>, <7,0,4,5> + 3362966856U, // <0,4,5,u>: Cost 2 vsldoi12 <1,2,3,0>, RHS + 3369676113U, // <0,4,6,0>: Cost 4 vsldoi12 <2,3,4,0>, <4,6,0,7> + 3261739435U, // <0,4,6,1>: Cost 4 vsldoi8 <6,7,0,4>, <6,1,7,5> + 3261739514U, // <0,4,6,2>: Cost 4 vsldoi8 <6,7,0,4>, <6,2,7,3> + 3259085325U, // <0,4,6,3>: Cost 4 vsldoi8 <6,3,0,4>, <6,3,0,4> + 4202900790U, // <0,4,6,4>: Cost 4 vsldoi4 <7,0,4,6>, RHS + 3359485238U, // <0,4,6,5>: Cost 3 vmrghw <0,6,0,7>, RHS + 3261739832U, // <0,4,6,6>: Cost 4 vsldoi8 <6,7,0,4>, <6,6,6,6> + 3261739857U, // <0,4,6,7>: Cost 3 vsldoi8 <6,7,0,4>, <6,7,0,4> + 3262403490U, // <0,4,6,u>: Cost 3 vsldoi8 <6,u,0,4>, <6,u,0,4> + 3517589193U, // <0,4,7,0>: Cost 4 vmrglw <4,6,0,7>, <2,3,4,0> + 3263730756U, // <0,4,7,1>: Cost 4 vsldoi8 <7,1,0,4>, <7,1,0,4> + 3238515914U, // <0,4,7,2>: Cost 5 vsldoi8 <2,u,0,4>, <7,2,6,3> + 3265058022U, // <0,4,7,3>: Cost 4 vsldoi8 <7,3,0,4>, <7,3,0,4> + 4190965046U, // <0,4,7,4>: Cost 4 vsldoi4 <5,0,4,7>, RHS + 3384348104U, // <0,4,7,5>: Cost 3 vsldoi12 <4,7,5,0>, <4,7,5,0> + 3517590414U, // <0,4,7,6>: Cost 5 vmrglw <4,6,0,7>, <4,0,4,6> + 3384348122U, // <0,4,7,7>: Cost 4 vsldoi12 <4,7,5,0>, <4,7,7,0> + 3384348104U, // <0,4,7,u>: Cost 3 vsldoi12 <4,7,5,0>, <4,7,5,0> + 2287184786U, // <0,4,u,0>: Cost 2 vmrghw LHS, <4,0,5,1> + 3360926690U, // <0,4,u,1>: Cost 3 vmrghw LHS, <4,1,5,0> + 3360926773U, // <0,4,u,2>: Cost 3 vmrghw LHS, <4,2,5,2> + 4179028151U, // <0,4,u,3>: Cost 3 vsldoi4 <3,0,4,u>, <3,0,4,u> + 2287185104U, // <0,4,u,4>: Cost 2 vmrghw LHS, <4,4,4,4> + 1213443382U, // <0,4,u,5>: Cost 1 vmrghw LHS, RHS + 3362967081U, // <0,4,u,6>: Cost 2 vsldoi12 <1,2,3,0>, RHS + 4202918939U, // <0,4,u,7>: Cost 3 vsldoi4 <7,0,4,u>, <7,0,4,u> + 1213443625U, // <0,4,u,u>: Cost 1 vmrghw LHS, RHS + 3489663889U, // <0,5,0,0>: Cost 3 vmrglw <0,0,0,0>, <4,0,5,0> + 3241836646U, // <0,5,0,1>: Cost 3 vsldoi8 <3,4,0,5>, LHS + 3241836754U, // <0,5,0,2>: Cost 4 vsldoi8 <3,4,0,5>, <0,2,5,3> + 3241836796U, // <0,5,0,3>: Cost 4 vsldoi8 <3,4,0,5>, <0,3,1,0> + 3223920969U, // <0,5,0,4>: Cost 3 vsldoi8 <0,4,0,5>, <0,4,0,5> + 3355447300U, // <0,5,0,5>: Cost 3 vmrghw <0,0,0,0>, <5,5,5,5> + 3389804148U, // <0,5,0,6>: Cost 3 vsldoi12 <5,6,7,0>, <5,0,6,1> + 3384348284U, // <0,5,0,7>: Cost 4 vsldoi12 <4,7,5,0>, <5,0,7,0> + 3241837213U, // <0,5,0,u>: Cost 3 vsldoi8 <3,4,0,5>, LHS + 3111272550U, // <0,5,1,0>: Cost 2 vsldoi4 <4,0,5,1>, LHS + 3520196122U, // <0,5,1,1>: Cost 3 vmrglw <5,1,0,1>, <4,u,5,1> + 3356282603U, // <0,5,1,2>: Cost 3 vmrghw LHS, <5,2,1,3> + 4185016470U, // <0,5,1,3>: Cost 3 vsldoi4 <4,0,5,1>, <3,0,1,2> + 3111275410U, // <0,5,1,4>: Cost 2 vsldoi4 <4,0,5,1>, <4,0,5,1> + 2282541060U, // <0,5,1,5>: Cost 2 vmrghw LHS, <5,5,5,5> + 2282541154U, // <0,5,1,6>: Cost 2 vmrghw LHS, <5,6,7,0> + 4185019386U, // <0,5,1,7>: Cost 3 vsldoi4 <4,0,5,1>, <7,0,1,2> + 2282541303U, // <0,5,1,u>: Cost 2 vmrghw LHS, <5,u,5,5> + 3235866061U, // <0,5,2,0>: Cost 4 vsldoi8 <2,4,0,5>, <2,0,3,0> + 3241838112U, // <0,5,2,1>: Cost 4 vsldoi8 <3,4,0,5>, <2,1,3,2> + 3241838184U, // <0,5,2,2>: Cost 4 vsldoi8 <3,4,0,5>, <2,2,2,2> + 3241838246U, // <0,5,2,3>: Cost 4 vsldoi8 <3,4,0,5>, <2,3,0,1> + 3235866363U, // <0,5,2,4>: Cost 4 vsldoi8 <2,4,0,5>, <2,4,0,5> + 3389804303U, // <0,5,2,5>: Cost 4 vsldoi12 <5,6,7,0>, <5,2,5,3> + 3241838522U, // <0,5,2,6>: Cost 4 vsldoi8 <3,4,0,5>, <2,6,3,7> + 3268380650U, // <0,5,2,7>: Cost 4 vsldoi8 <7,u,0,5>, <2,7,0,1> + 3238520895U, // <0,5,2,u>: Cost 4 vsldoi8 <2,u,0,5>, <2,u,0,5> + 3241838742U, // <0,5,3,0>: Cost 3 vsldoi8 <3,4,0,5>, <3,0,1,2> + 3239848161U, // <0,5,3,1>: Cost 4 vsldoi8 <3,1,0,5>, <3,1,0,5> + 3240511794U, // <0,5,3,2>: Cost 4 vsldoi8 <3,2,0,5>, <3,2,0,5> + 3241838975U, // <0,5,3,3>: Cost 4 vsldoi8 <3,4,0,5>, <3,3,0,1> + 3241839060U, // <0,5,3,4>: Cost 3 vsldoi8 <3,4,0,5>, <3,4,0,5> + 3387666269U, // <0,5,3,5>: Cost 4 vsldoi12 <5,3,5,0>, <5,3,5,0> + 3498314242U, // <0,5,3,6>: Cost 4 vmrglw <1,4,0,3>, <3,4,5,6> + 3243829959U, // <0,5,3,7>: Cost 4 vsldoi8 <3,7,0,5>, <3,7,0,5> + 3244493592U, // <0,5,3,u>: Cost 3 vsldoi8 <3,u,0,5>, <3,u,0,5> + 3265727378U, // <0,5,4,0>: Cost 3 vsldoi8 <7,4,0,5>, <4,0,5,1> + 4167123722U, // <0,5,4,1>: Cost 4 vsldoi4 <1,0,5,4>, <1,0,5,4> + 4167124649U, // <0,5,4,2>: Cost 4 vsldoi4 <1,0,5,4>, <2,3,0,4> + 3498984363U, // <0,5,4,3>: Cost 4 vmrglw <1,5,0,4>, <1,2,5,3> + 3358216116U, // <0,5,4,4>: Cost 3 vmrghw <0,4,1,5>, <5,4,5,6> + 3241839926U, // <0,5,4,5>: Cost 3 vsldoi8 <3,4,0,5>, RHS + 3389804476U, // <0,5,4,6>: Cost 3 vsldoi12 <5,6,7,0>, <5,4,6,5> + 3498984691U, // <0,5,4,7>: Cost 4 vmrglw <1,5,0,4>, <1,6,5,7> + 3241840169U, // <0,5,4,u>: Cost 3 vsldoi8 <3,4,0,5>, RHS + 3376386002U, // <0,5,5,0>: Cost 4 vsldoi12 <3,4,5,0>, <5,5,0,0> + 3534162834U, // <0,5,5,1>: Cost 3 vmrglw <7,4,0,5>, <4,0,5,1> + 3358854891U, // <0,5,5,2>: Cost 4 vmrghw <0,5,1,2>, <5,2,1,3> + 3510272210U, // <0,5,5,3>: Cost 4 vmrglw <3,4,0,5>, <0,2,5,3> + 3253784454U, // <0,5,5,4>: Cost 4 vsldoi8 <5,4,0,5>, <5,4,0,5> + 3389804548U, // <0,5,5,5>: Cost 3 vsldoi12 <5,6,7,0>, <5,5,5,5> + 3261747298U, // <0,5,5,6>: Cost 3 vsldoi8 <6,7,0,5>, <5,6,7,0> + 3389141009U, // <0,5,5,7>: Cost 4 vsldoi12 <5,5,7,0>, <5,5,7,0> + 3273691396U, // <0,5,5,u>: Cost 3 vsldoi8 , <5,u,7,0> + 4202971238U, // <0,5,6,0>: Cost 3 vsldoi4 <7,0,5,6>, LHS + 3389804595U, // <0,5,6,1>: Cost 4 vsldoi12 <5,6,7,0>, <5,6,1,7> + 3261747706U, // <0,5,6,2>: Cost 4 vsldoi8 <6,7,0,5>, <6,2,7,3> + 3383095362U, // <0,5,6,3>: Cost 4 vsldoi12 <4,5,6,0>, <5,6,3,4> + 4202974518U, // <0,5,6,4>: Cost 3 vsldoi4 <7,0,5,6>, RHS + 4202975330U, // <0,5,6,5>: Cost 3 vsldoi4 <7,0,5,6>, <5,6,7,0> + 3362967648U, // <0,5,6,6>: Cost 4 vsldoi12 <1,2,3,0>, <5,6,6,7> + 3389804642U, // <0,5,6,7>: Cost 2 vsldoi12 <5,6,7,0>, <5,6,7,0> + 3389878379U, // <0,5,6,u>: Cost 2 vsldoi12 <5,6,u,0>, <5,6,u,0> + 3268383738U, // <0,5,7,0>: Cost 3 vsldoi8 <7,u,0,5>, <7,0,1,2> + 3389804669U, // <0,5,7,1>: Cost 4 vsldoi12 <5,6,7,0>, <5,7,1,0> + 3261748372U, // <0,5,7,2>: Cost 4 vsldoi8 <6,7,0,5>, <7,2,0,3> + 3241841891U, // <0,5,7,3>: Cost 4 vsldoi8 <3,4,0,5>, <7,3,0,1> + 3265729848U, // <0,5,7,4>: Cost 3 vsldoi8 <7,4,0,5>, <7,4,0,5> + 3389804705U, // <0,5,7,5>: Cost 4 vsldoi12 <5,6,7,0>, <5,7,5,0> + 3511615863U, // <0,5,7,6>: Cost 4 vmrglw <3,6,0,7>, <0,4,5,6> + 3261748774U, // <0,5,7,7>: Cost 4 vsldoi8 <6,7,0,5>, <7,7,0,0> + 3268384380U, // <0,5,7,u>: Cost 3 vsldoi8 <7,u,0,5>, <7,u,0,5> + 3111329894U, // <0,5,u,0>: Cost 2 vsldoi4 <4,0,5,u>, LHS + 3241842478U, // <0,5,u,1>: Cost 3 vsldoi8 <3,4,0,5>, LHS + 3360927467U, // <0,5,u,2>: Cost 3 vmrghw LHS, <5,2,1,3> + 4185073814U, // <0,5,u,3>: Cost 3 vsldoi4 <4,0,5,u>, <3,0,1,2> + 3111332761U, // <0,5,u,4>: Cost 2 vsldoi4 <4,0,5,u>, <4,0,5,u> + 2287185924U, // <0,5,u,5>: Cost 2 vmrghw LHS, <5,5,5,5> + 2287186018U, // <0,5,u,6>: Cost 2 vmrghw LHS, <5,6,7,0> + 3391131908U, // <0,5,u,7>: Cost 2 vsldoi12 <5,u,7,0>, <5,u,7,0> + 3391205645U, // <0,5,u,u>: Cost 2 vsldoi12 <5,u,u,0>, <5,u,u,0> + 3355447637U, // <0,6,0,0>: Cost 3 vmrghw <0,0,0,0>, <6,0,7,0> + 3355529639U, // <0,6,0,1>: Cost 3 vmrghw <0,0,1,1>, <6,1,7,1> + 3355447802U, // <0,6,0,2>: Cost 3 vmrghw <0,0,0,0>, <6,2,7,3> + 3383095605U, // <0,6,0,3>: Cost 4 vsldoi12 <4,5,6,0>, <6,0,3,4> + 3362967871U, // <0,6,0,4>: Cost 4 vsldoi12 <1,2,3,0>, <6,0,4,5> + 4191055475U, // <0,6,0,5>: Cost 4 vsldoi4 <5,0,6,0>, <5,0,6,0> + 3355448120U, // <0,6,0,6>: Cost 3 vmrghw <0,0,0,0>, <6,6,6,6> + 2415922486U, // <0,6,0,7>: Cost 2 vmrglw <0,0,0,0>, RHS + 2415922487U, // <0,6,0,u>: Cost 2 vmrglw <0,0,0,0>, RHS + 3356283169U, // <0,6,1,0>: Cost 3 vmrghw LHS, <6,0,1,2> + 3356283303U, // <0,6,1,1>: Cost 3 vmrghw LHS, <6,1,7,1> + 2282541562U, // <0,6,1,2>: Cost 2 vmrghw LHS, <6,2,7,3> + 3356283442U, // <0,6,1,3>: Cost 3 vmrghw LHS, <6,3,4,5> + 3356283505U, // <0,6,1,4>: Cost 3 vmrghw LHS, <6,4,2,5> + 3356283627U, // <0,6,1,5>: Cost 3 vmrghw LHS, <6,5,7,1> + 2282541880U, // <0,6,1,6>: Cost 2 vmrghw LHS, <6,6,6,6> + 2429865270U, // <0,6,1,7>: Cost 2 vmrglw <2,3,0,1>, RHS + 2429865271U, // <0,6,1,u>: Cost 2 vmrglw <2,3,0,1>, RHS + 3383095739U, // <0,6,2,0>: Cost 4 vsldoi12 <4,5,6,0>, <6,2,0,3> + 3356873129U, // <0,6,2,1>: Cost 4 vmrghw <0,2,1,3>, <6,1,7,3> + 3356799482U, // <0,6,2,2>: Cost 4 vmrghw <0,2,0,3>, <6,2,7,3> + 3392827859U, // <0,6,2,3>: Cost 4 vsldoi12 <6,2,3,0>, <6,2,3,0> + 4203015478U, // <0,6,2,4>: Cost 4 vsldoi4 <7,0,6,2>, RHS + 4203016290U, // <0,6,2,5>: Cost 4 vsldoi4 <7,0,6,2>, <5,6,7,0> + 3240519610U, // <0,6,2,6>: Cost 4 vsldoi8 <3,2,0,6>, <2,6,3,7> + 3389805050U, // <0,6,2,7>: Cost 3 vsldoi12 <5,6,7,0>, <6,2,7,3> + 3389805059U, // <0,6,2,u>: Cost 3 vsldoi12 <5,6,7,0>, <6,2,u,3> + 3240519830U, // <0,6,3,0>: Cost 4 vsldoi8 <3,2,0,6>, <3,0,1,2> + 3393344018U, // <0,6,3,1>: Cost 4 vsldoi12 <6,3,1,0>, <6,3,1,0> + 3240519987U, // <0,6,3,2>: Cost 4 vsldoi8 <3,2,0,6>, <3,2,0,6> + 3357545010U, // <0,6,3,3>: Cost 4 vmrghw <0,3,1,4>, <6,3,4,5> + 3242510850U, // <0,6,3,4>: Cost 4 vsldoi8 <3,5,0,6>, <3,4,5,6> + 3242510886U, // <0,6,3,5>: Cost 4 vsldoi8 <3,5,0,6>, <3,5,0,6> + 4203024968U, // <0,6,3,6>: Cost 4 vsldoi4 <7,0,6,3>, <6,3,7,0> + 3508931894U, // <0,6,3,7>: Cost 3 vmrglw <3,2,0,3>, RHS + 3508931895U, // <0,6,3,u>: Cost 3 vmrglw <3,2,0,3>, RHS + 3265735570U, // <0,6,4,0>: Cost 4 vsldoi8 <7,4,0,6>, <4,0,5,1> + 3358216619U, // <0,6,4,1>: Cost 3 vmrghw <0,4,1,5>, <6,1,7,5> + 3358216698U, // <0,6,4,2>: Cost 3 vmrghw <0,4,1,5>, <6,2,7,3> + 3358216754U, // <0,6,4,3>: Cost 4 vmrghw <0,4,1,5>, <6,3,4,5> + 3358208669U, // <0,6,4,4>: Cost 4 vmrghw <0,4,1,4>, <6,4,7,4> + 3240521014U, // <0,6,4,5>: Cost 4 vsldoi8 <3,2,0,6>, RHS + 3358217016U, // <0,6,4,6>: Cost 3 vmrghw <0,4,1,5>, <6,6,6,6> + 3498986806U, // <0,6,4,7>: Cost 3 vmrglw <1,5,0,4>, RHS + 3498986807U, // <0,6,4,u>: Cost 3 vmrglw <1,5,0,4>, RHS + 3383095985U, // <0,6,5,0>: Cost 4 vsldoi12 <4,5,6,0>, <6,5,0,6> + 3530182260U, // <0,6,5,1>: Cost 4 vmrglw <6,7,0,5>, <5,0,6,1> + 3394745021U, // <0,6,5,2>: Cost 4 vsldoi12 <6,5,2,0>, <6,5,2,0> + 3510274406U, // <0,6,5,3>: Cost 5 vmrglw <3,4,0,5>, <3,2,6,3> + 4191096118U, // <0,6,5,4>: Cost 4 vsldoi4 <5,0,6,5>, RHS + 3530182588U, // <0,6,5,5>: Cost 4 vmrglw <6,7,0,5>, <5,4,6,5> + 3395039969U, // <0,6,5,6>: Cost 4 vsldoi12 <6,5,6,0>, <6,5,6,0> + 3510275382U, // <0,6,5,7>: Cost 3 vmrglw <3,4,0,5>, RHS + 3510275383U, // <0,6,5,u>: Cost 3 vmrglw <3,4,0,5>, RHS + 3383096060U, // <0,6,6,0>: Cost 4 vsldoi12 <4,5,6,0>, <6,6,0,0> + 3532842473U, // <0,6,6,1>: Cost 4 vmrglw <7,2,0,6>, <2,0,6,1> + 3359519226U, // <0,6,6,2>: Cost 3 vmrghw <0,6,1,2>, <6,2,7,3> + 3359527474U, // <0,6,6,3>: Cost 4 vmrghw <0,6,1,3>, <6,3,4,5> + 4203048246U, // <0,6,6,4>: Cost 4 vsldoi4 <7,0,6,6>, RHS + 3260428977U, // <0,6,6,5>: Cost 4 vsldoi8 <6,5,0,6>, <6,5,0,6> + 3389805368U, // <0,6,6,6>: Cost 3 vsldoi12 <5,6,7,0>, <6,6,6,6> + 3389805378U, // <0,6,6,7>: Cost 3 vsldoi12 <5,6,7,0>, <6,6,7,7> + 3389805387U, // <0,6,6,u>: Cost 3 vsldoi12 <5,6,7,0>, <6,6,u,7> + 3389805390U, // <0,6,7,0>: Cost 3 vsldoi12 <5,6,7,0>, <6,7,0,1> + 3362968408U, // <0,6,7,1>: Cost 3 vsldoi12 <1,2,3,0>, <6,7,1,2> + 3511617812U, // <0,6,7,2>: Cost 4 vmrglw <3,6,0,7>, <3,1,6,2> + 3396146024U, // <0,6,7,3>: Cost 3 vsldoi12 <6,7,3,0>, <6,7,3,0> + 3389805430U, // <0,6,7,4>: Cost 3 vsldoi12 <5,6,7,0>, <6,7,4,5> + 3389805440U, // <0,6,7,5>: Cost 3 vsldoi12 <5,6,7,0>, <6,7,5,6> + 3389805445U, // <0,6,7,6>: Cost 4 vsldoi12 <5,6,7,0>, <6,7,6,2> + 3511618870U, // <0,6,7,7>: Cost 3 vmrglw <3,6,0,7>, RHS + 3511618871U, // <0,6,7,u>: Cost 3 vmrglw <3,6,0,7>, RHS + 3389805471U, // <0,6,u,0>: Cost 3 vsldoi12 <5,6,7,0>, <6,u,0,1> + 3360928167U, // <0,6,u,1>: Cost 3 vmrghw LHS, <6,1,7,1> + 2287186426U, // <0,6,u,2>: Cost 2 vmrghw LHS, <6,2,7,3> + 3396809657U, // <0,6,u,3>: Cost 3 vsldoi12 <6,u,3,0>, <6,u,3,0> + 3389805511U, // <0,6,u,4>: Cost 3 vsldoi12 <5,6,7,0>, <6,u,4,5> + 3389805440U, // <0,6,u,5>: Cost 3 vsldoi12 <5,6,7,0>, <6,7,5,6> + 2287186744U, // <0,6,u,6>: Cost 2 vmrghw LHS, <6,6,6,6> + 2429922614U, // <0,6,u,7>: Cost 2 vmrglw <2,3,0,u>, RHS + 2429922615U, // <0,6,u,u>: Cost 2 vmrglw <2,3,0,u>, RHS + 4197097472U, // <0,7,0,0>: Cost 3 vsldoi4 <6,0,7,0>, <0,0,0,0> + 3243180134U, // <0,7,0,1>: Cost 3 vsldoi8 <3,6,0,7>, LHS + 4179183546U, // <0,7,0,2>: Cost 4 vsldoi4 <3,0,7,0>, <2,6,3,7> + 3489665530U, // <0,7,0,3>: Cost 3 vmrglw <0,0,0,0>, <6,2,7,3> + 3389805592U, // <0,7,0,4>: Cost 3 vsldoi12 <5,6,7,0>, <7,0,4,5> + 3389805602U, // <0,7,0,5>: Cost 3 vsldoi12 <5,6,7,0>, <7,0,5,6> + 4197101909U, // <0,7,0,6>: Cost 3 vsldoi4 <6,0,7,0>, <6,0,7,0> + 3355448940U, // <0,7,0,7>: Cost 3 vmrghw <0,0,0,0>, <7,7,7,7> + 3243180701U, // <0,7,0,u>: Cost 3 vsldoi8 <3,6,0,7>, LHS + 2282542074U, // <0,7,1,0>: Cost 2 vmrghw LHS, <7,0,1,2> + 3356283978U, // <0,7,1,1>: Cost 3 vmrghw LHS, <7,1,1,1> + 3243180950U, // <0,7,1,2>: Cost 3 vsldoi8 <3,6,0,7>, <1,2,3,0> + 3530150394U, // <0,7,1,3>: Cost 3 vmrglw <6,7,0,1>, <6,2,7,3> + 2282542438U, // <0,7,1,4>: Cost 2 vmrghw LHS, <7,4,5,6> + 3356284342U, // <0,7,1,5>: Cost 3 vmrghw LHS, <7,5,5,5> + 4197110102U, // <0,7,1,6>: Cost 3 vsldoi4 <6,0,7,1>, <6,0,7,1> + 2282542700U, // <0,7,1,7>: Cost 2 vmrghw LHS, <7,7,7,7> + 2282542722U, // <0,7,1,u>: Cost 2 vmrghw LHS, <7,u,1,2> + 3389805716U, // <0,7,2,0>: Cost 3 vsldoi12 <5,6,7,0>, <7,2,0,3> + 3231237664U, // <0,7,2,1>: Cost 5 vsldoi8 <1,6,0,7>, <2,1,3,2> + 3243181672U, // <0,7,2,2>: Cost 4 vsldoi8 <3,6,0,7>, <2,2,2,2> + 3398800556U, // <0,7,2,3>: Cost 3 vsldoi12 <7,2,3,0>, <7,2,3,0> + 3389879480U, // <0,7,2,4>: Cost 4 vsldoi12 <5,6,u,0>, <7,2,4,3> + 4203090018U, // <0,7,2,5>: Cost 4 vsldoi4 <7,0,7,2>, <5,6,7,0> + 3241191354U, // <0,7,2,6>: Cost 4 vsldoi8 <3,3,0,7>, <2,6,3,7> + 4203090992U, // <0,7,2,7>: Cost 4 vsldoi4 <7,0,7,2>, <7,0,7,2> + 3399169241U, // <0,7,2,u>: Cost 3 vsldoi12 <7,2,u,0>, <7,2,u,0> + 3532820578U, // <0,7,3,0>: Cost 3 vmrglw <7,2,0,3>, <5,6,7,0> + 3243182321U, // <0,7,3,1>: Cost 4 vsldoi8 <3,6,0,7>, <3,1,2,3> + 3243182384U, // <0,7,3,2>: Cost 4 vsldoi8 <3,6,0,7>, <3,2,0,3> + 3241191813U, // <0,7,3,3>: Cost 4 vsldoi8 <3,3,0,7>, <3,3,0,7> + 3243182594U, // <0,7,3,4>: Cost 4 vsldoi8 <3,6,0,7>, <3,4,5,6> + 3267070557U, // <0,7,3,5>: Cost 4 vsldoi8 <7,6,0,7>, <3,5,6,7> + 3243182712U, // <0,7,3,6>: Cost 3 vsldoi8 <3,6,0,7>, <3,6,0,7> + 3532821314U, // <0,7,3,7>: Cost 4 vmrglw <7,2,0,3>, <6,6,7,7> + 3244509978U, // <0,7,3,u>: Cost 3 vsldoi8 <3,u,0,7>, <3,u,0,7> + 3358217210U, // <0,7,4,0>: Cost 3 vmrghw <0,4,1,5>, <7,0,1,2> + 4197131158U, // <0,7,4,1>: Cost 4 vsldoi4 <6,0,7,4>, <1,2,3,0> + 3358217364U, // <0,7,4,2>: Cost 4 vmrghw <0,4,1,5>, <7,2,0,3> + 4197132920U, // <0,7,4,3>: Cost 4 vsldoi4 <6,0,7,4>, <3,6,0,7> + 3358217574U, // <0,7,4,4>: Cost 3 vmrghw <0,4,1,5>, <7,4,5,6> + 3243183414U, // <0,7,4,5>: Cost 3 vsldoi8 <3,6,0,7>, RHS + 3249155409U, // <0,7,4,6>: Cost 4 vsldoi8 <4,6,0,7>, <4,6,0,7> + 3358217836U, // <0,7,4,7>: Cost 3 vmrghw <0,4,1,5>, <7,7,7,7> + 3243183657U, // <0,7,4,u>: Cost 3 vsldoi8 <3,6,0,7>, RHS + 3530182754U, // <0,7,5,0>: Cost 3 vmrglw <6,7,0,5>, <5,6,7,0> + 3534164715U, // <0,7,5,1>: Cost 4 vmrglw <7,4,0,5>, <6,5,7,1> + 3358889108U, // <0,7,5,2>: Cost 4 vmrghw <0,5,1,6>, <7,2,0,3> + 4197140630U, // <0,7,5,3>: Cost 4 vsldoi4 <6,0,7,5>, <3,0,1,2> + 4197141814U, // <0,7,5,4>: Cost 4 vsldoi4 <6,0,7,5>, RHS + 3389806006U, // <0,7,5,5>: Cost 4 vsldoi12 <5,6,7,0>, <7,5,5,5> + 3389806017U, // <0,7,5,6>: Cost 3 vsldoi12 <5,6,7,0>, <7,5,6,7> + 3530183490U, // <0,7,5,7>: Cost 4 vmrglw <6,7,0,5>, <6,6,7,7> + 3391133139U, // <0,7,5,u>: Cost 3 vsldoi12 <5,u,7,0>, <7,5,u,7> + 3389806044U, // <0,7,6,0>: Cost 3 vsldoi12 <5,6,7,0>, <7,6,0,7> + 3243184508U, // <0,7,6,1>: Cost 5 vsldoi8 <3,6,0,7>, <6,1,2,3> + 3389806062U, // <0,7,6,2>: Cost 4 vsldoi12 <5,6,7,0>, <7,6,2,7> + 3404772855U, // <0,7,6,3>: Cost 4 vsldoi12 , <7,6,3,7> + 3389879808U, // <0,7,6,4>: Cost 4 vsldoi12 <5,6,u,0>, <7,6,4,7> + 4203122786U, // <0,7,6,5>: Cost 4 vsldoi4 <7,0,7,6>, <5,6,7,0> + 3389806097U, // <0,7,6,6>: Cost 4 vsldoi12 <5,6,7,0>, <7,6,6,6> + 3401750036U, // <0,7,6,7>: Cost 3 vsldoi12 <7,6,7,0>, <7,6,7,0> + 3401823773U, // <0,7,6,u>: Cost 3 vsldoi12 <7,6,u,0>, <7,6,u,0> + 3389806118U, // <0,7,7,0>: Cost 3 vsldoi12 <5,6,7,0>, <7,7,0,0> + 4197155734U, // <0,7,7,1>: Cost 4 vsldoi4 <6,0,7,7>, <1,2,3,0> + 3398800955U, // <0,7,7,2>: Cost 4 vsldoi12 <7,2,3,0>, <7,7,2,3> + 3511615716U, // <0,7,7,3>: Cost 4 vmrglw <3,6,0,7>, <0,2,7,3> + 3360200038U, // <0,7,7,4>: Cost 3 vmrghw <0,7,1,4>, <7,4,5,6> + 3389806169U, // <0,7,7,5>: Cost 4 vsldoi12 <5,6,7,0>, <7,7,5,6> + 3267073500U, // <0,7,7,6>: Cost 3 vsldoi8 <7,6,0,7>, <7,6,0,7> + 3389806188U, // <0,7,7,7>: Cost 3 vsldoi12 <5,6,7,0>, <7,7,7,7> + 3268400766U, // <0,7,7,u>: Cost 3 vsldoi8 <7,u,0,7>, <7,u,0,7> + 2287186938U, // <0,7,u,0>: Cost 2 vmrghw LHS, <7,0,1,2> + 3243185966U, // <0,7,u,1>: Cost 3 vsldoi8 <3,6,0,7>, LHS + 4197164717U, // <0,7,u,2>: Cost 3 vsldoi4 <6,0,7,u>, <2,3,0,u> + 3530207738U, // <0,7,u,3>: Cost 3 vmrglw <6,7,0,u>, <6,2,7,3> + 2287187302U, // <0,7,u,4>: Cost 2 vmrghw LHS, <7,4,5,6> + 3243186330U, // <0,7,u,5>: Cost 3 vsldoi8 <3,6,0,7>, RHS + 4197167453U, // <0,7,u,6>: Cost 3 vsldoi4 <6,0,7,u>, <6,0,7,u> + 2287187564U, // <0,7,u,7>: Cost 2 vmrghw LHS, <7,7,7,7> + 2287187586U, // <0,7,u,u>: Cost 2 vmrghw LHS, <7,u,1,2> + 1477230694U, // <0,u,0,0>: Cost 1 vspltisw0 LHS + 3235225702U, // <0,u,0,1>: Cost 2 vsldoi8 <2,3,0,u>, LHS + 4173284858U, // <0,u,0,2>: Cost 3 vsldoi4 <2,0,u,0>, <2,0,u,0> + 2415919260U, // <0,u,0,3>: Cost 2 vmrglw <0,0,0,0>, LHS + 3087600950U, // <0,u,0,4>: Cost 2 vsldoi4 <0,0,u,0>, RHS + 2281707674U, // <0,u,0,5>: Cost 2 vmrghw <0,0,0,0>, RHS + 3235226165U, // <0,u,0,6>: Cost 3 vsldoi8 <2,3,0,u>, <0,6,u,7> + 2415922504U, // <0,u,0,7>: Cost 2 vmrglw <0,0,0,0>, RHS + 1477230694U, // <0,u,0,u>: Cost 1 vspltisw0 LHS + 2282985171U, // <0,u,1,0>: Cost 2 vmrghw LHS, + 1208801070U, // <0,u,1,1>: Cost 1 vmrghw LHS, LHS + 2283026312U, // <0,u,1,2>: Cost 2 vmrghw LHS, + 2283026364U, // <0,u,1,3>: Cost 2 vmrghw LHS, + 2282985535U, // <0,u,1,4>: Cost 2 vmrghw LHS, + 1208801434U, // <0,u,1,5>: Cost 1 vmrghw LHS, RHS + 2283026640U, // <0,u,1,6>: Cost 2 vmrghw LHS, + 2429865288U, // <0,u,1,7>: Cost 2 vmrglw <2,3,0,1>, RHS + 1208801637U, // <0,u,1,u>: Cost 1 vmrghw LHS, LHS + 3105529958U, // <0,u,2,0>: Cost 2 vsldoi4 <3,0,u,2>, LHS + 3356866350U, // <0,u,2,1>: Cost 3 vmrghw <0,2,1,2>, LHS + 3235227240U, // <0,u,2,2>: Cost 3 vsldoi8 <2,3,0,u>, <2,2,2,2> 835584U, // <0,u,2,3>: Cost 0 copy LHS - 2971315510U, // <0,u,2,4>: Cost 2 vsldoi4 <3,0,u,2>, RHS - 3222648986U, // <0,u,2,5>: Cost 3 vmrghw <0,2,1,2>, RHS - 4174751674U, // <0,u,2,6>: Cost 3 vsldoi8 <2,3,0,u>, <2,6,3,7> - 2995205177U, // <0,u,2,7>: Cost 2 vsldoi4 <7,0,u,2>, <7,0,u,2> + 3105533238U, // <0,u,2,4>: Cost 2 vsldoi4 <3,0,u,2>, RHS + 3356866714U, // <0,u,2,5>: Cost 3 vmrghw <0,2,1,2>, RHS + 3235227578U, // <0,u,2,6>: Cost 3 vsldoi8 <2,3,0,u>, <2,6,3,7> + 3129422905U, // <0,u,2,7>: Cost 2 vsldoi4 <7,0,u,2>, <7,0,u,2> 835584U, // <0,u,2,u>: Cost 0 copy LHS - 3228751804U, // <0,u,3,0>: Cost 3 vsldoi12 <1,2,3,0>, - 3223295790U, // <0,u,3,1>: Cost 3 vmrghw <0,3,1,0>, LHS - 4180060469U, // <0,u,3,2>: Cost 3 vsldoi8 <3,2,0,u>, <3,2,0,u> - 3228751830U, // <0,u,3,3>: Cost 3 vsldoi12 <1,2,3,0>, - 3228751844U, // <0,u,3,4>: Cost 3 vsldoi12 <1,2,3,0>, - 3223296154U, // <0,u,3,5>: Cost 3 vmrghw <0,3,1,0>, RHS - 4182715001U, // <0,u,3,6>: Cost 3 vsldoi8 <3,6,0,u>, <3,6,0,u> - 3374714184U, // <0,u,3,7>: Cost 3 vmrglw <3,2,0,3>, RHS - 3223296357U, // <0,u,3,u>: Cost 3 vmrghw <0,3,1,0>, LHS - 3224000211U, // <0,u,4,0>: Cost 3 vmrghw <0,4,1,5>, - 2150258478U, // <0,u,4,1>: Cost 2 vmrghw <0,4,1,5>, LHS - 3224000392U, // <0,u,4,2>: Cost 3 vmrghw <0,4,1,5>, - 3224000444U, // <0,u,4,3>: Cost 3 vmrghw <0,4,1,5>, - 2150252882U, // <0,u,4,4>: Cost 2 vmrghw <0,4,1,5>, <0,4,1,5> - 2150258842U, // <0,u,4,5>: Cost 2 vmrghw <0,4,1,5>, RHS - 3224000720U, // <0,u,4,6>: Cost 3 vmrghw <0,4,1,5>, - 3364769096U, // <0,u,4,7>: Cost 3 vmrglw <1,5,0,4>, RHS - 2150259045U, // <0,u,4,u>: Cost 2 vmrghw <0,4,1,5>, LHS - 4045078630U, // <0,u,5,0>: Cost 3 vsldoi4 <3,0,u,5>, LHS - 4045079446U, // <0,u,5,1>: Cost 3 vsldoi4 <3,0,u,5>, <1,2,3,0> - 3376056470U, // <0,u,5,2>: Cost 3 vmrglw <3,4,0,5>, <3,0,1,2> - 4045080792U, // <0,u,5,3>: Cost 3 vsldoi4 <3,0,u,5>, <3,0,u,5> - 4045081910U, // <0,u,5,4>: Cost 3 vsldoi4 <3,0,u,5>, RHS - 4193996762U, // <0,u,5,5>: Cost 3 vsldoi8 <5,5,0,u>, <5,5,0,u> - 3228752026U, // <0,u,5,6>: Cost 2 vsldoi12 <1,2,3,0>, RHS - 3376057672U, // <0,u,5,7>: Cost 3 vmrglw <3,4,0,5>, RHS - 3228752044U, // <0,u,5,u>: Cost 2 vsldoi12 <1,2,3,0>, RHS - 3229120693U, // <0,u,6,0>: Cost 3 vsldoi12 <1,2,u,0>, - 3225270062U, // <0,u,6,1>: Cost 3 vmrghw <0,6,0,7>, LHS - 4201296378U, // <0,u,6,2>: Cost 3 vsldoi8 <6,7,0,u>, <6,2,7,3> - 3228752080U, // <0,u,6,3>: Cost 3 vsldoi12 <1,2,3,0>, - 4068977974U, // <0,u,6,4>: Cost 3 vsldoi4 <7,0,u,6>, RHS - 4068757602U, // <0,u,6,5>: Cost 3 vsldoi4 <7,0,5,6>, <5,6,7,0> - 4201296696U, // <0,u,6,6>: Cost 3 vsldoi8 <6,7,0,u>, <6,6,6,6> - 3127554901U, // <0,u,6,7>: Cost 2 vsldoi8 <6,7,0,u>, <6,7,0,u> - 3128218534U, // <0,u,6,u>: Cost 2 vsldoi8 <6,u,0,u>, <6,u,0,u> - 3255589120U, // <0,u,7,0>: Cost 3 vsldoi12 <5,6,7,0>, - 3273726216U, // <0,u,7,1>: Cost 3 vsldoi12 , - 4203951257U, // <0,u,7,2>: Cost 3 vsldoi8 <7,2,0,u>, <7,2,0,u> - 3377397916U, // <0,u,7,3>: Cost 3 vmrglw <3,6,0,7>, LHS - 3255589160U, // <0,u,7,4>: Cost 3 vsldoi12 <5,6,7,0>, - 3255589170U, // <0,u,7,5>: Cost 3 vsldoi12 <5,6,7,0>, - 4206605789U, // <0,u,7,6>: Cost 3 vsldoi8 <7,6,0,u>, <7,6,0,u> - 3377401160U, // <0,u,7,7>: Cost 3 vmrglw <3,6,0,7>, RHS - 3377397921U, // <0,u,7,u>: Cost 3 vmrglw <3,6,0,7>, LHS - 1343012966U, // <0,u,u,0>: Cost 1 vspltisw0 LHS - 1079228206U, // <0,u,u,1>: Cost 1 vmrghw LHS, LHS - 2152970120U, // <0,u,u,2>: Cost 2 vmrghw LHS, + 3362969532U, // <0,u,3,0>: Cost 3 vsldoi12 <1,2,3,0>, + 3357513518U, // <0,u,3,1>: Cost 3 vmrghw <0,3,1,0>, LHS + 3240536373U, // <0,u,3,2>: Cost 3 vsldoi8 <3,2,0,u>, <3,2,0,u> + 3362969558U, // <0,u,3,3>: Cost 3 vsldoi12 <1,2,3,0>, + 3362969572U, // <0,u,3,4>: Cost 3 vsldoi12 <1,2,3,0>, + 3357513882U, // <0,u,3,5>: Cost 3 vmrghw <0,3,1,0>, RHS + 3243190905U, // <0,u,3,6>: Cost 3 vsldoi8 <3,6,0,u>, <3,6,0,u> + 3508931912U, // <0,u,3,7>: Cost 3 vmrglw <3,2,0,3>, RHS + 3357514085U, // <0,u,3,u>: Cost 3 vmrghw <0,3,1,0>, LHS + 3358217939U, // <0,u,4,0>: Cost 3 vmrghw <0,4,1,5>, + 2284476206U, // <0,u,4,1>: Cost 2 vmrghw <0,4,1,5>, LHS + 3358218120U, // <0,u,4,2>: Cost 3 vmrghw <0,4,1,5>, + 3358218172U, // <0,u,4,3>: Cost 3 vmrghw <0,4,1,5>, + 2284470610U, // <0,u,4,4>: Cost 2 vmrghw <0,4,1,5>, <0,4,1,5> + 2284476570U, // <0,u,4,5>: Cost 2 vmrghw <0,4,1,5>, RHS + 3358218448U, // <0,u,4,6>: Cost 3 vmrghw <0,4,1,5>, + 3498986824U, // <0,u,4,7>: Cost 3 vmrglw <1,5,0,4>, RHS + 2284476773U, // <0,u,4,u>: Cost 2 vmrghw <0,4,1,5>, LHS + 4179296358U, // <0,u,5,0>: Cost 3 vsldoi4 <3,0,u,5>, LHS + 4179297174U, // <0,u,5,1>: Cost 3 vsldoi4 <3,0,u,5>, <1,2,3,0> + 3510274198U, // <0,u,5,2>: Cost 3 vmrglw <3,4,0,5>, <3,0,1,2> + 4179298520U, // <0,u,5,3>: Cost 3 vsldoi4 <3,0,u,5>, <3,0,u,5> + 4179299638U, // <0,u,5,4>: Cost 3 vsldoi4 <3,0,u,5>, RHS + 3254472666U, // <0,u,5,5>: Cost 3 vsldoi8 <5,5,0,u>, <5,5,0,u> + 3362969754U, // <0,u,5,6>: Cost 2 vsldoi12 <1,2,3,0>, RHS + 3510275400U, // <0,u,5,7>: Cost 3 vmrglw <3,4,0,5>, RHS + 3362969772U, // <0,u,5,u>: Cost 2 vsldoi12 <1,2,3,0>, RHS + 3363338421U, // <0,u,6,0>: Cost 3 vsldoi12 <1,2,u,0>, + 3359487790U, // <0,u,6,1>: Cost 3 vmrghw <0,6,0,7>, LHS + 3261772282U, // <0,u,6,2>: Cost 3 vsldoi8 <6,7,0,u>, <6,2,7,3> + 3362969808U, // <0,u,6,3>: Cost 3 vsldoi12 <1,2,3,0>, + 4203195702U, // <0,u,6,4>: Cost 3 vsldoi4 <7,0,u,6>, RHS + 4202975330U, // <0,u,6,5>: Cost 3 vsldoi4 <7,0,5,6>, <5,6,7,0> + 3261772600U, // <0,u,6,6>: Cost 3 vsldoi8 <6,7,0,u>, <6,6,6,6> + 3261772629U, // <0,u,6,7>: Cost 2 vsldoi8 <6,7,0,u>, <6,7,0,u> + 3262436262U, // <0,u,6,u>: Cost 2 vsldoi8 <6,u,0,u>, <6,u,0,u> + 3389806848U, // <0,u,7,0>: Cost 3 vsldoi12 <5,6,7,0>, + 3407943944U, // <0,u,7,1>: Cost 3 vsldoi12 , + 3264427161U, // <0,u,7,2>: Cost 3 vsldoi8 <7,2,0,u>, <7,2,0,u> + 3511615644U, // <0,u,7,3>: Cost 3 vmrglw <3,6,0,7>, LHS + 3389806888U, // <0,u,7,4>: Cost 3 vsldoi12 <5,6,7,0>, + 3389806898U, // <0,u,7,5>: Cost 3 vsldoi12 <5,6,7,0>, + 3267081693U, // <0,u,7,6>: Cost 3 vsldoi8 <7,6,0,u>, <7,6,0,u> + 3511618888U, // <0,u,7,7>: Cost 3 vmrglw <3,6,0,7>, RHS + 3511615649U, // <0,u,7,u>: Cost 3 vmrglw <3,6,0,7>, LHS + 1477230694U, // <0,u,u,0>: Cost 1 vspltisw0 LHS + 1213445934U, // <0,u,u,1>: Cost 1 vmrghw LHS, LHS + 2287187848U, // <0,u,u,2>: Cost 2 vmrghw LHS, 835584U, // <0,u,u,3>: Cost 0 copy LHS - 2152970303U, // <0,u,u,4>: Cost 2 vmrghw LHS, - 1079228570U, // <0,u,u,5>: Cost 1 vmrghw LHS, RHS - 2152970448U, // <0,u,u,6>: Cost 2 vmrghw LHS, - 2295704904U, // <0,u,u,7>: Cost 2 vmrglw <2,3,0,u>, RHS + 2287188031U, // <0,u,u,4>: Cost 2 vmrghw LHS, + 1213446298U, // <0,u,u,5>: Cost 1 vmrghw LHS, RHS + 2287188176U, // <0,u,u,6>: Cost 2 vmrghw LHS, + 2429922632U, // <0,u,u,7>: Cost 2 vmrglw <2,3,0,u>, RHS 835584U, // <0,u,u,u>: Cost 0 copy LHS - 3226615808U, // <1,0,0,0>: Cost 3 vsldoi12 <0,u,1,1>, <0,0,0,0> - 3221307402U, // <1,0,0,1>: Cost 2 vsldoi12 <0,0,1,1>, <0,0,1,1> - 4162150571U, // <1,0,0,2>: Cost 4 vsldoi8 <0,2,1,0>, <0,2,1,0> - 4162814204U, // <1,0,0,3>: Cost 3 vsldoi8 <0,3,1,0>, <0,3,1,0> - 3221528613U, // <1,0,0,4>: Cost 3 vsldoi12 <0,0,4,1>, <0,0,4,1> - 4164141470U, // <1,0,0,5>: Cost 3 vsldoi8 <0,5,1,0>, <0,5,1,0> - 4178739702U, // <1,0,0,6>: Cost 4 vsldoi8 <3,0,1,0>, <0,6,1,7> - 4165468736U, // <1,0,0,7>: Cost 3 vsldoi8 <0,7,1,0>, <0,7,1,0> - 3221823561U, // <1,0,0,u>: Cost 2 vsldoi12 <0,0,u,1>, <0,0,u,1> - 3360833536U, // <1,0,1,0>: Cost 3 vmrglw <0,u,1,1>, <0,0,0,0> - 2154201190U, // <1,0,1,1>: Cost 2 vmrghw <1,1,1,1>, LHS - 3226615910U, // <1,0,1,2>: Cost 2 vsldoi12 <0,u,1,1>, LHS - 3227861244U, // <1,0,1,3>: Cost 4 vmrghw <1,1,0,0>, <0,3,1,0> - 4033178934U, // <1,0,1,4>: Cost 3 vsldoi4 <1,1,0,1>, RHS - 4057067151U, // <1,0,1,5>: Cost 3 vsldoi4 <5,1,0,1>, <5,1,0,1> - 3261710478U, // <1,0,1,6>: Cost 3 vsldoi12 <6,7,0,1>, <0,1,6,7> - 4057068538U, // <1,0,1,7>: Cost 4 vsldoi4 <5,1,0,1>, <7,0,1,2> - 3226615964U, // <1,0,1,u>: Cost 2 vsldoi12 <0,u,1,1>, LHS - 3228745728U, // <1,0,2,0>: Cost 3 vmrghw <1,2,3,0>, <0,0,0,0> - 2155004006U, // <1,0,2,1>: Cost 2 vmrghw <1,2,3,0>, LHS - 3356862524U, // <1,0,2,2>: Cost 4 vmrglw <0,2,1,2>, <2,u,0,2> - 4178740902U, // <1,0,2,3>: Cost 3 vsldoi8 <3,0,1,0>, <2,3,0,1> - 3228746066U, // <1,0,2,4>: Cost 3 vmrghw <1,2,3,0>, <0,4,1,5> - 3373451732U, // <1,0,2,5>: Cost 3 vmrglw <3,0,1,2>, <3,4,0,5> - 4162815930U, // <1,0,2,6>: Cost 4 vsldoi8 <0,3,1,0>, <2,6,3,7> - 3369470584U, // <1,0,2,7>: Cost 4 vmrglw <2,3,1,2>, <3,6,0,7> - 2155004573U, // <1,0,2,u>: Cost 2 vmrghw <1,2,3,0>, LHS - 4162816150U, // <1,0,3,0>: Cost 3 vsldoi8 <0,3,1,0>, <3,0,1,2> - 3356870310U, // <1,0,3,1>: Cost 3 vmrglw <0,2,1,3>, <2,3,0,1> - 3229196462U, // <1,0,3,2>: Cost 4 vmrghw <1,3,0,1>, <0,2,1,3> - 4162816383U, // <1,0,3,3>: Cost 4 vsldoi8 <0,3,1,0>, <3,3,0,1> - 4162816514U, // <1,0,3,4>: Cost 4 vsldoi8 <0,3,1,0>, <3,4,5,6> - 4182059561U, // <1,0,3,5>: Cost 4 vsldoi8 <3,5,1,0>, <3,5,1,0> - 3261710640U, // <1,0,3,6>: Cost 4 vsldoi12 <6,7,0,1>, <0,3,6,7> - 3366824568U, // <1,0,3,7>: Cost 5 vmrglw <1,u,1,3>, <3,6,0,7> - 4184050460U, // <1,0,3,u>: Cost 3 vsldoi8 <3,u,1,0>, <3,u,1,0> - 4211256210U, // <1,0,4,0>: Cost 3 vsldoi8 , <4,0,5,1> - 3226616146U, // <1,0,4,1>: Cost 3 vsldoi12 <0,u,1,1>, <0,4,1,5> - 3226616155U, // <1,0,4,2>: Cost 5 vsldoi12 <0,u,1,1>, <0,4,2,5> - 3229860096U, // <1,0,4,3>: Cost 4 vmrghw <1,4,0,1>, <0,3,1,4> - 3226616173U, // <1,0,4,4>: Cost 4 vsldoi12 <0,u,1,1>, <0,4,4,5> - 4162817334U, // <1,0,4,5>: Cost 3 vsldoi8 <0,3,1,0>, RHS - 3230269942U, // <1,0,4,6>: Cost 5 vmrghw <1,4,5,6>, <0,6,1,7> - 4213247432U, // <1,0,4,7>: Cost 4 vsldoi8 , <4,7,5,0> - 4162817577U, // <1,0,4,u>: Cost 3 vsldoi8 <0,3,1,0>, RHS - 3358212096U, // <1,0,5,0>: Cost 3 vmrglw <0,4,1,5>, <0,0,0,0> - 3358213798U, // <1,0,5,1>: Cost 3 vmrglw <0,4,1,5>, <2,3,0,1> - 4211920619U, // <1,0,5,2>: Cost 4 vsldoi8 , <5,2,1,3> - 3230859520U, // <1,0,5,3>: Cost 4 vmrghw <1,5,4,6>, <0,3,1,4> - 3358213801U, // <1,0,5,4>: Cost 3 vmrglw <0,4,1,5>, <2,3,0,4> - 4057099923U, // <1,0,5,5>: Cost 4 vsldoi4 <5,1,0,5>, <5,1,0,5> - 4195332194U, // <1,0,5,6>: Cost 4 vsldoi8 <5,7,1,0>, <5,6,7,0> - 4195332221U, // <1,0,5,7>: Cost 4 vsldoi8 <5,7,1,0>, <5,7,1,0> - 3358213805U, // <1,0,5,u>: Cost 3 vmrglw <0,4,1,5>, <2,3,0,u> - 3356893184U, // <1,0,6,0>: Cost 4 vmrglw <0,2,1,6>, <0,0,0,0> - 3231309926U, // <1,0,6,1>: Cost 3 vmrghw <1,6,1,7>, LHS - 3231187121U, // <1,0,6,2>: Cost 4 vmrghw <1,6,0,1>, <0,2,1,6> - 3231236348U, // <1,0,6,3>: Cost 4 vmrghw <1,6,0,7>, <0,3,1,0> - 3231605074U, // <1,0,6,4>: Cost 3 vmrghw <1,6,5,7>, <0,4,1,5> - 4211258091U, // <1,0,6,5>: Cost 4 vsldoi8 , <6,5,7,1> - 4202631992U, // <1,0,6,6>: Cost 4 vsldoi8 <7,0,1,0>, <6,6,6,6> - 4202632014U, // <1,0,6,7>: Cost 3 vsldoi8 <7,0,1,0>, <6,7,0,1> - 3231310482U, // <1,0,6,u>: Cost 3 vmrghw <1,6,1,7>, <0,u,1,1> - 4202632184U, // <1,0,7,0>: Cost 3 vsldoi8 <7,0,1,0>, <7,0,1,0> - 3359557286U, // <1,0,7,1>: Cost 3 vmrglw <0,6,1,7>, <2,3,0,1> - 4208604377U, // <1,0,7,2>: Cost 4 vsldoi8 , <7,2,u,0> - 4210595043U, // <1,0,7,3>: Cost 4 vsldoi8 , <7,3,0,1> - 4202632550U, // <1,0,7,4>: Cost 4 vsldoi8 <7,0,1,0>, <7,4,5,6> - 4205950349U, // <1,0,7,5>: Cost 4 vsldoi8 <7,5,1,0>, <7,5,1,0> - 4202632724U, // <1,0,7,6>: Cost 4 vsldoi8 <7,0,1,0>, <7,6,7,0> - 4202632812U, // <1,0,7,7>: Cost 4 vsldoi8 <7,0,1,0>, <7,7,7,7> - 4207941248U, // <1,0,7,u>: Cost 3 vsldoi8 <7,u,1,0>, <7,u,1,0> - 3358236672U, // <1,0,u,0>: Cost 3 vmrglw <0,4,1,u>, <0,0,0,0> - 3226616466U, // <1,0,u,1>: Cost 2 vsldoi12 <0,u,1,1>, <0,u,1,1> - 3226616477U, // <1,0,u,2>: Cost 2 vsldoi12 <0,u,1,1>, LHS - 4210595780U, // <1,0,u,3>: Cost 3 vsldoi8 , - 3226837677U, // <1,0,u,4>: Cost 3 vsldoi12 <0,u,4,1>, <0,u,4,1> - 4162820250U, // <1,0,u,5>: Cost 3 vsldoi8 <0,3,1,0>, RHS - 3261710478U, // <1,0,u,6>: Cost 3 vsldoi12 <6,7,0,1>, <0,1,6,7> - 4213250312U, // <1,0,u,7>: Cost 3 vsldoi8 , - 3226616531U, // <1,0,u,u>: Cost 2 vsldoi12 <0,u,1,1>, LHS - 3087089674U, // <1,1,0,0>: Cost 2 vsldoi8 <0,0,1,1>, <0,0,1,1> - 3092398182U, // <1,1,0,1>: Cost 2 vsldoi8 <0,u,1,1>, LHS - 3357509782U, // <1,1,0,2>: Cost 3 vmrglw <0,3,1,0>, <3,0,1,2> - 3357507596U, // <1,1,0,3>: Cost 4 vmrglw <0,3,1,0>, <0,0,1,3> - 4166140242U, // <1,1,0,4>: Cost 3 vsldoi8 <0,u,1,1>, <0,4,1,5> - 3357507922U, // <1,1,0,5>: Cost 4 vmrglw <0,3,1,0>, <0,4,1,5> - 3227288783U, // <1,1,0,6>: Cost 4 vmrghw <1,0,1,2>, <1,6,1,7> - 3373433334U, // <1,1,0,7>: Cost 4 vmrglw <3,0,1,0>, <0,6,1,7> - 3092398738U, // <1,1,0,u>: Cost 2 vsldoi8 <0,u,1,1>, <0,u,1,1> - 2959507558U, // <1,1,1,0>: Cost 2 vsldoi4 <1,1,1,1>, LHS - 1477230694U, // <1,1,1,1>: Cost 1 vspltisw1 LHS - 3360835734U, // <1,1,1,2>: Cost 3 vmrglw <0,u,1,1>, <3,0,1,2> - 3360834439U, // <1,1,1,3>: Cost 3 vmrglw <0,u,1,1>, <1,2,1,3> - 2959510838U, // <1,1,1,4>: Cost 2 vsldoi4 <1,1,1,1>, RHS - 3360833874U, // <1,1,1,5>: Cost 3 vmrglw <0,u,1,1>, <0,4,1,5> - 4166141135U, // <1,1,1,6>: Cost 3 vsldoi8 <0,u,1,1>, <1,6,1,7> - 4069086282U, // <1,1,1,7>: Cost 3 vsldoi4 <7,1,1,1>, <7,1,1,1> - 1477230694U, // <1,1,1,u>: Cost 1 vspltisw1 LHS - 3228746476U, // <1,1,2,0>: Cost 3 vmrghw <1,2,3,0>, <1,0,2,1> - 3226616711U, // <1,1,2,1>: Cost 3 vsldoi12 <0,u,1,1>, <1,2,1,3> - 2155004822U, // <1,1,2,2>: Cost 2 vmrghw <1,2,3,0>, <1,2,3,0> - 4166141606U, // <1,1,2,3>: Cost 3 vsldoi8 <0,u,1,1>, <2,3,0,1> - 4027288886U, // <1,1,2,4>: Cost 3 vsldoi4 <0,1,1,2>, RHS - 3373449554U, // <1,1,2,5>: Cost 3 vmrglw <3,0,1,2>, <0,4,1,5> - 4166141882U, // <1,1,2,6>: Cost 3 vsldoi8 <0,u,1,1>, <2,6,3,7> - 3361506511U, // <1,1,2,7>: Cost 4 vmrglw <1,0,1,2>, <1,6,1,7> - 2155004822U, // <1,1,2,u>: Cost 2 vmrghw <1,2,3,0>, <1,2,3,0> - 4166142102U, // <1,1,3,0>: Cost 3 vsldoi8 <0,u,1,1>, <3,0,1,2> - 4167469286U, // <1,1,3,1>: Cost 3 vsldoi8 <1,1,1,1>, <3,1,1,1> - 3356870806U, // <1,1,3,2>: Cost 4 vmrglw <0,2,1,3>, <3,0,1,2> - 3356868782U, // <1,1,3,3>: Cost 3 vmrglw <0,2,1,3>, <0,2,1,3> - 4166142466U, // <1,1,3,4>: Cost 3 vsldoi8 <0,u,1,1>, <3,4,5,6> - 3356868946U, // <1,1,3,5>: Cost 4 vmrglw <0,2,1,3>, <0,4,1,5> - 4213918328U, // <1,1,3,6>: Cost 4 vsldoi8 , <3,6,0,7> - 3362841807U, // <1,1,3,7>: Cost 4 vmrglw <1,2,1,3>, <1,6,1,7> - 4166142750U, // <1,1,3,u>: Cost 3 vsldoi8 <0,u,1,1>, <3,u,1,2> - 4033273958U, // <1,1,4,0>: Cost 3 vsldoi4 <1,1,1,4>, LHS - 3227943979U, // <1,1,4,1>: Cost 3 vsldoi12 <1,1,1,1>, <1,4,1,5> - 3230040982U, // <1,1,4,2>: Cost 3 vmrghw <1,4,2,5>, <1,2,3,0> - 4033276054U, // <1,1,4,3>: Cost 4 vsldoi4 <1,1,1,4>, <3,0,1,2> - 3357540608U, // <1,1,4,4>: Cost 3 vmrglw <0,3,1,4>, <0,3,1,4> - 3092401462U, // <1,1,4,5>: Cost 2 vsldoi8 <0,u,1,1>, RHS - 3230270671U, // <1,1,4,6>: Cost 4 vmrghw <1,4,5,6>, <1,6,1,7> - 3373466102U, // <1,1,4,7>: Cost 4 vmrglw <3,0,1,4>, <0,6,1,7> - 3092401705U, // <1,1,4,u>: Cost 2 vsldoi8 <0,u,1,1>, RHS - 3230524527U, // <1,1,5,0>: Cost 3 vsldoi12 <1,5,0,1>, <1,5,0,1> - 3358212106U, // <1,1,5,1>: Cost 3 vmrglw <0,4,1,5>, <0,0,1,1> - 3358214294U, // <1,1,5,2>: Cost 3 vmrglw <0,4,1,5>, <3,0,1,2> - 3358212270U, // <1,1,5,3>: Cost 4 vmrglw <0,4,1,5>, <0,2,1,3> - 3358212109U, // <1,1,5,4>: Cost 3 vmrglw <0,4,1,5>, <0,0,1,4> - 2284470610U, // <1,1,5,5>: Cost 2 vmrglw <0,4,1,5>, <0,4,1,5> - 4213919842U, // <1,1,5,6>: Cost 3 vsldoi8 , <5,6,7,0> - 3360867535U, // <1,1,5,7>: Cost 4 vmrglw <0,u,1,5>, <1,6,1,7> - 2284470610U, // <1,1,5,u>: Cost 2 vmrglw <0,4,1,5>, <0,4,1,5> - 4033290342U, // <1,1,6,0>: Cost 4 vsldoi4 <1,1,1,6>, LHS - 3226617039U, // <1,1,6,1>: Cost 3 vsldoi12 <0,u,1,1>, <1,6,1,7> - 4213920250U, // <1,1,6,2>: Cost 3 vsldoi8 , <6,2,7,3> - 3235169505U, // <1,1,6,3>: Cost 4 vsldoi12 <2,3,0,1>, <1,6,3,7> - 4033293622U, // <1,1,6,4>: Cost 4 vsldoi4 <1,1,1,6>, RHS - 3356893522U, // <1,1,6,5>: Cost 4 vmrglw <0,2,1,6>, <0,4,1,5> - 3356893361U, // <1,1,6,6>: Cost 3 vmrglw <0,2,1,6>, <0,2,1,6> - 3261711614U, // <1,1,6,7>: Cost 3 vsldoi12 <6,7,0,1>, <1,6,7,0> - 3262375175U, // <1,1,6,u>: Cost 3 vsldoi12 <6,u,0,1>, <1,6,u,0> - 4213920762U, // <1,1,7,0>: Cost 3 vsldoi8 , <7,0,1,2> - 3365528210U, // <1,1,7,1>: Cost 3 vmrglw <1,6,1,7>, <0,u,1,1> - 3365528292U, // <1,1,7,2>: Cost 4 vmrglw <1,6,1,7>, <1,0,1,2> - 3365528455U, // <1,1,7,3>: Cost 4 vmrglw <1,6,1,7>, <1,2,1,3> - 4213921126U, // <1,1,7,4>: Cost 3 vsldoi8 , <7,4,5,6> - 3365527890U, // <1,1,7,5>: Cost 4 vmrglw <1,6,1,7>, <0,4,1,5> - 3365528377U, // <1,1,7,6>: Cost 4 vmrglw <1,6,1,7>, <1,1,1,6> - 3365528783U, // <1,1,7,7>: Cost 3 vmrglw <1,6,1,7>, <1,6,1,7> - 4213921410U, // <1,1,7,u>: Cost 3 vsldoi8 , <7,u,1,2> - 2959507558U, // <1,1,u,0>: Cost 2 vsldoi4 <1,1,1,1>, LHS - 1477230694U, // <1,1,u,1>: Cost 1 vspltisw1 LHS - 2155004822U, // <1,1,u,2>: Cost 2 vmrghw <1,2,3,0>, <1,2,3,0> - 4166145980U, // <1,1,u,3>: Cost 3 vsldoi8 <0,u,1,1>, - 2959510838U, // <1,1,u,4>: Cost 2 vsldoi4 <1,1,1,1>, RHS - 3092404378U, // <1,1,u,5>: Cost 2 vsldoi8 <0,u,1,1>, RHS - 4166146256U, // <1,1,u,6>: Cost 3 vsldoi8 <0,u,1,1>, - 4213258505U, // <1,1,u,7>: Cost 3 vsldoi8 , - 1477230694U, // <1,1,u,u>: Cost 1 vspltisw1 LHS - 4178755584U, // <1,2,0,0>: Cost 3 vsldoi8 <3,0,1,2>, <0,0,0,0> - 3105013862U, // <1,2,0,1>: Cost 2 vsldoi8 <3,0,1,2>, LHS - 4162166957U, // <1,2,0,2>: Cost 3 vsldoi8 <0,2,1,2>, <0,2,1,2> - 3357507686U, // <1,2,0,3>: Cost 3 vmrglw <0,3,1,0>, LHS - 4178755922U, // <1,2,0,4>: Cost 3 vsldoi8 <3,0,1,2>, <0,4,1,5> - 4190699997U, // <1,2,0,5>: Cost 4 vsldoi8 <5,0,1,2>, <0,5,u,0> - 4164821489U, // <1,2,0,6>: Cost 3 vsldoi8 <0,6,1,2>, <0,6,1,2> - 4202644032U, // <1,2,0,7>: Cost 3 vsldoi8 <7,0,1,2>, <0,7,1,0> - 3105014429U, // <1,2,0,u>: Cost 2 vsldoi8 <3,0,1,2>, LHS - 4166812388U, // <1,2,1,0>: Cost 3 vsldoi8 <1,0,1,2>, <1,0,1,2> - 4178756404U, // <1,2,1,1>: Cost 3 vsldoi8 <3,0,1,2>, <1,1,1,1> - 3360835176U, // <1,2,1,2>: Cost 3 vmrglw <0,u,1,1>, <2,2,2,2> - 2287091814U, // <1,2,1,3>: Cost 2 vmrglw <0,u,1,1>, LHS - 4166812706U, // <1,2,1,4>: Cost 4 vsldoi8 <1,0,1,2>, <1,4,0,5> - 3227944808U, // <1,2,1,5>: Cost 4 vmrghw <1,1,1,1>, <2,5,3,6> - 3227944890U, // <1,2,1,6>: Cost 3 vmrghw <1,1,1,1>, <2,6,3,7> - 4202644777U, // <1,2,1,7>: Cost 4 vsldoi8 <7,0,1,2>, <1,7,2,7> - 2287091819U, // <1,2,1,u>: Cost 2 vmrglw <0,u,1,1>, LHS - 4033331302U, // <1,2,2,0>: Cost 3 vsldoi4 <1,1,2,2>, LHS - 4178757152U, // <1,2,2,1>: Cost 3 vsldoi8 <3,0,1,2>, <2,1,3,2> - 3356862056U, // <1,2,2,2>: Cost 3 vmrglw <0,2,1,2>, <2,2,2,2> - 2299707494U, // <1,2,2,3>: Cost 2 vmrglw <3,0,1,2>, LHS - 4033334582U, // <1,2,2,4>: Cost 3 vsldoi4 <1,1,2,2>, RHS - 3356860763U, // <1,2,2,5>: Cost 4 vmrglw <0,2,1,2>, <0,4,2,5> - 3228747706U, // <1,2,2,6>: Cost 3 vmrghw <1,2,3,0>, <2,6,3,7> - 3373450456U, // <1,2,2,7>: Cost 3 vmrglw <3,0,1,2>, <1,6,2,7> - 2299707499U, // <1,2,2,u>: Cost 2 vmrglw <3,0,1,2>, LHS - 1879883878U, // <1,2,3,0>: Cost 1 vsldoi4 LHS, LHS - 2953626420U, // <1,2,3,1>: Cost 2 vsldoi4 LHS, <1,1,1,1> - 2953627240U, // <1,2,3,2>: Cost 2 vsldoi4 LHS, <2,2,2,2> - 2953628060U, // <1,2,3,3>: Cost 2 vsldoi4 LHS, <3,3,3,3> - 1879887158U, // <1,2,3,4>: Cost 1 vsldoi4 LHS, RHS - 3001405444U, // <1,2,3,5>: Cost 2 vsldoi4 LHS, <5,5,5,5> - 3001405946U, // <1,2,3,6>: Cost 2 vsldoi4 LHS, <6,2,7,3> - 3001406458U, // <1,2,3,7>: Cost 2 vsldoi4 LHS, <7,0,1,2> - 1879889710U, // <1,2,3,u>: Cost 1 vsldoi4 LHS, LHS - 4184730479U, // <1,2,4,0>: Cost 3 vsldoi8 <4,0,1,2>, <4,0,1,2> - 3234064132U, // <1,2,4,1>: Cost 4 vsldoi12 <2,1,3,1>, <2,4,1,5> - 3357541992U, // <1,2,4,2>: Cost 4 vmrglw <0,3,1,4>, <2,2,2,2> - 3357540454U, // <1,2,4,3>: Cost 3 vmrglw <0,3,1,4>, LHS - 4202646736U, // <1,2,4,4>: Cost 3 vsldoi8 <7,0,1,2>, <4,4,4,4> - 3105017142U, // <1,2,4,5>: Cost 2 vsldoi8 <3,0,1,2>, RHS - 3229968314U, // <1,2,4,6>: Cost 4 vmrghw <1,4,1,5>, <2,6,3,7> - 4202646984U, // <1,2,4,7>: Cost 3 vsldoi8 <7,0,1,2>, <4,7,5,0> - 3105017385U, // <1,2,4,u>: Cost 2 vsldoi8 <3,0,1,2>, RHS - 4190703176U, // <1,2,5,0>: Cost 3 vsldoi8 <5,0,1,2>, <5,0,1,2> - 3230524963U, // <1,2,5,1>: Cost 4 vmrghw <1,5,0,1>, <2,1,3,5> - 3358213736U, // <1,2,5,2>: Cost 3 vmrglw <0,4,1,5>, <2,2,2,2> - 2284470374U, // <1,2,5,3>: Cost 2 vmrglw <0,4,1,5>, LHS - 4178759604U, // <1,2,5,4>: Cost 4 vsldoi8 <3,0,1,2>, <5,4,5,6> - 4202647556U, // <1,2,5,5>: Cost 3 vsldoi8 <7,0,1,2>, <5,5,5,5> - 4202647650U, // <1,2,5,6>: Cost 3 vsldoi8 <7,0,1,2>, <5,6,7,0> - 4202647722U, // <1,2,5,7>: Cost 4 vsldoi8 <7,0,1,2>, <5,7,6,0> - 2284470379U, // <1,2,5,u>: Cost 2 vmrglw <0,4,1,5>, LHS - 4196675873U, // <1,2,6,0>: Cost 3 vsldoi8 <6,0,1,2>, <6,0,1,2> - 4178760104U, // <1,2,6,1>: Cost 3 vsldoi8 <3,0,1,2>, <6,1,7,2> - 4202648058U, // <1,2,6,2>: Cost 3 vsldoi8 <7,0,1,2>, <6,2,7,3> - 3356893286U, // <1,2,6,3>: Cost 3 vmrglw <0,2,1,6>, LHS - 4033367350U, // <1,2,6,4>: Cost 4 vsldoi4 <1,1,2,6>, RHS - 3231606633U, // <1,2,6,5>: Cost 4 vmrghw <1,6,5,7>, <2,5,3,7> - 4202648376U, // <1,2,6,6>: Cost 3 vsldoi8 <7,0,1,2>, <6,6,6,6> - 4201321304U, // <1,2,6,7>: Cost 3 vsldoi8 <6,7,1,2>, <6,7,1,2> - 3356893291U, // <1,2,6,u>: Cost 3 vmrglw <0,2,1,6>, LHS - 3128906746U, // <1,2,7,0>: Cost 2 vsldoi8 <7,0,1,2>, <7,0,1,2> - 3371500916U, // <1,2,7,1>: Cost 4 vmrglw <2,6,1,7>, <1,u,2,1> - 3365529192U, // <1,2,7,2>: Cost 4 vmrglw <1,6,1,7>, <2,2,2,2> - 3365527654U, // <1,2,7,3>: Cost 3 vmrglw <1,6,1,7>, LHS - 4202648934U, // <1,2,7,4>: Cost 3 vsldoi8 <7,0,1,2>, <7,4,5,6> - 4190705029U, // <1,2,7,5>: Cost 4 vsldoi8 <5,0,1,2>, <7,5,0,1> - 4196677078U, // <1,2,7,6>: Cost 4 vsldoi8 <6,0,1,2>, <7,6,0,1> - 4202649127U, // <1,2,7,7>: Cost 3 vsldoi8 <7,0,1,2>, <7,7,0,1> - 3134215810U, // <1,2,7,u>: Cost 2 vsldoi8 <7,u,1,2>, <7,u,1,2> - 1879924843U, // <1,2,u,0>: Cost 1 vsldoi4 LHS, LHS - 2953667380U, // <1,2,u,1>: Cost 2 vsldoi4 LHS, <1,1,1,1> - 2953668200U, // <1,2,u,2>: Cost 2 vsldoi4 LHS, <2,2,2,2> - 2953668758U, // <1,2,u,3>: Cost 2 vsldoi4 LHS, <3,0,1,2> - 1879928118U, // <1,2,u,4>: Cost 1 vsldoi4 LHS, RHS - 3105020058U, // <1,2,u,5>: Cost 2 vsldoi8 <3,0,1,2>, RHS - 3001446906U, // <1,2,u,6>: Cost 2 vsldoi4 LHS, <6,2,7,3> - 3001447418U, // <1,2,u,7>: Cost 2 vsldoi4 LHS, <7,0,1,2> - 1879930670U, // <1,2,u,u>: Cost 1 vsldoi4 LHS, LHS - 3239151756U, // <1,3,0,0>: Cost 3 vsldoi12 <3,0,0,1>, <3,0,0,1> - 4162175078U, // <1,3,0,1>: Cost 3 vsldoi8 <0,2,1,3>, LHS - 4162175150U, // <1,3,0,2>: Cost 3 vsldoi8 <0,2,1,3>, <0,2,1,3> - 4162838783U, // <1,3,0,3>: Cost 3 vsldoi8 <0,3,1,3>, <0,3,1,3> - 3239446704U, // <1,3,0,4>: Cost 3 vsldoi12 <3,0,4,1>, <3,0,4,1> - 3357507940U, // <1,3,0,5>: Cost 4 vmrglw <0,3,1,0>, <0,4,3,5> - 4162175478U, // <1,3,0,6>: Cost 4 vsldoi8 <0,2,1,3>, <0,6,1,7> - 3357509562U, // <1,3,0,7>: Cost 4 vmrglw <0,3,1,0>, <2,6,3,7> - 4162175645U, // <1,3,0,u>: Cost 3 vsldoi8 <0,2,1,3>, LHS - 3360834454U, // <1,3,1,0>: Cost 3 vmrglw <0,u,1,1>, <1,2,3,0> - 3227945190U, // <1,3,1,1>: Cost 3 vmrghw <1,1,1,1>, <3,1,1,1> - 4168147847U, // <1,3,1,2>: Cost 3 vsldoi8 <1,2,1,3>, <1,2,1,3> - 3360835186U, // <1,3,1,3>: Cost 3 vmrglw <0,u,1,1>, <2,2,3,3> - 3360834458U, // <1,3,1,4>: Cost 3 vmrglw <0,u,1,1>, <1,2,3,4> - 3360835107U, // <1,3,1,5>: Cost 4 vmrglw <0,u,1,1>, <2,1,3,5> - 4162176225U, // <1,3,1,6>: Cost 4 vsldoi8 <0,2,1,3>, <1,6,3,7> - 3360835514U, // <1,3,1,7>: Cost 3 vmrglw <0,u,1,1>, <2,6,3,7> - 3360834462U, // <1,3,1,u>: Cost 3 vmrglw <0,u,1,1>, <1,2,3,u> - 3228747926U, // <1,3,2,0>: Cost 3 vmrghw <1,2,3,0>, <3,0,1,2> - 3228748017U, // <1,3,2,1>: Cost 3 vmrghw <1,2,3,0>, <3,1,2,3> - 4039378464U, // <1,3,2,2>: Cost 3 vsldoi4 <2,1,3,2>, <2,1,3,2> - 4162176678U, // <1,3,2,3>: Cost 3 vsldoi8 <0,2,1,3>, <2,3,0,1> - 3228748290U, // <1,3,2,4>: Cost 3 vmrghw <1,2,3,0>, <3,4,5,6> - 3373449572U, // <1,3,2,5>: Cost 4 vmrglw <3,0,1,2>, <0,4,3,5> - 3228748408U, // <1,3,2,6>: Cost 3 vmrghw <1,2,3,0>, <3,6,0,7> - 3373451194U, // <1,3,2,7>: Cost 3 vmrglw <3,0,1,2>, <2,6,3,7> - 3228748574U, // <1,3,2,u>: Cost 3 vmrghw <1,2,3,0>, <3,u,1,2> - 3241142655U, // <1,3,3,0>: Cost 3 vsldoi12 <3,3,0,1>, <3,3,0,1> - 3356874468U, // <1,3,3,1>: Cost 4 vmrglw <0,2,1,3>, - 4162177352U, // <1,3,3,2>: Cost 4 vsldoi8 <0,2,1,3>, <3,2,3,0> - 3357534620U, // <1,3,3,3>: Cost 3 vmrglw <0,3,1,3>, <3,3,3,3> - 3356869530U, // <1,3,3,4>: Cost 4 vmrglw <0,2,1,3>, <1,2,3,4> - 4057304748U, // <1,3,3,5>: Cost 4 vsldoi4 <5,1,3,3>, <5,1,3,3> - 3229387384U, // <1,3,3,6>: Cost 4 vmrghw <1,3,2,6>, <3,6,0,7> - 3356870586U, // <1,3,3,7>: Cost 4 vmrglw <0,2,1,3>, <2,6,3,7> - 3241732551U, // <1,3,3,u>: Cost 3 vsldoi12 <3,3,u,1>, <3,3,u,1> - 3241806288U, // <1,3,4,0>: Cost 3 vsldoi12 <3,4,0,1>, <3,4,0,1> - 3362186135U, // <1,3,4,1>: Cost 4 vmrglw <1,1,1,4>, <1,2,3,1> - 3230042416U, // <1,3,4,2>: Cost 4 vmrghw <1,4,2,5>, <3,2,0,3> - 3357542002U, // <1,3,4,3>: Cost 4 vmrglw <0,3,1,4>, <2,2,3,3> - 3357540626U, // <1,3,4,4>: Cost 4 vmrglw <0,3,1,4>, <0,3,3,4> - 4162178358U, // <1,3,4,5>: Cost 3 vsldoi8 <0,2,1,3>, RHS - 3357546622U, // <1,3,4,6>: Cost 4 vmrglw <0,3,1,4>, - 3357542330U, // <1,3,4,7>: Cost 4 vmrglw <0,3,1,4>, <2,6,3,7> - 4162178601U, // <1,3,4,u>: Cost 3 vsldoi8 <0,2,1,3>, RHS - 3358213014U, // <1,3,5,0>: Cost 3 vmrglw <0,4,1,5>, <1,2,3,0> - 3358213015U, // <1,3,5,1>: Cost 4 vmrglw <0,4,1,5>, <1,2,3,1> - 4039403043U, // <1,3,5,2>: Cost 3 vsldoi4 <2,1,3,5>, <2,1,3,5> - 3358213746U, // <1,3,5,3>: Cost 3 vmrglw <0,4,1,5>, <2,2,3,3> - 3358213018U, // <1,3,5,4>: Cost 3 vmrglw <0,4,1,5>, <1,2,3,4> - 3358213667U, // <1,3,5,5>: Cost 3 vmrglw <0,4,1,5>, <2,1,3,5> - 3358218366U, // <1,3,5,6>: Cost 4 vmrglw <0,4,1,5>, - 3358214074U, // <1,3,5,7>: Cost 3 vmrglw <0,4,1,5>, <2,6,3,7> - 3358213022U, // <1,3,5,u>: Cost 3 vmrglw <0,4,1,5>, <1,2,3,u> - 3231385750U, // <1,3,6,0>: Cost 3 vmrghw <1,6,2,7>, <3,0,1,2> - 3228756609U, // <1,3,6,1>: Cost 4 vsldoi12 <1,2,3,1>, <3,6,1,7> - 4039411236U, // <1,3,6,2>: Cost 4 vsldoi4 <2,1,3,6>, <2,1,3,6> - 3356894834U, // <1,3,6,3>: Cost 4 vmrglw <0,2,1,6>, <2,2,3,3> - 3356894106U, // <1,3,6,4>: Cost 4 vmrglw <0,2,1,6>, <1,2,3,4> - 3356894755U, // <1,3,6,5>: Cost 5 vmrglw <0,2,1,6>, <2,1,3,5> - 3356899130U, // <1,3,6,6>: Cost 4 vmrglw <0,2,1,6>, - 3356895162U, // <1,3,6,7>: Cost 3 vmrglw <0,2,1,6>, <2,6,3,7> - 3356895162U, // <1,3,6,u>: Cost 3 vmrglw <0,2,1,6>, <2,6,3,7> - 3243797187U, // <1,3,7,0>: Cost 3 vsldoi12 <3,7,0,1>, <3,7,0,1> - 4039419087U, // <1,3,7,1>: Cost 4 vsldoi4 <2,1,3,7>, <1,6,1,7> - 4039419429U, // <1,3,7,2>: Cost 4 vsldoi4 <2,1,3,7>, <2,1,3,7> - 3365529202U, // <1,3,7,3>: Cost 4 vmrglw <1,6,1,7>, <2,2,3,3> - 3365528474U, // <1,3,7,4>: Cost 4 vmrglw <1,6,1,7>, <1,2,3,4> - 4192040343U, // <1,3,7,5>: Cost 4 vsldoi8 <5,2,1,3>, <7,5,2,1> - 3261713151U, // <1,3,7,6>: Cost 4 vsldoi12 <6,7,0,1>, <3,7,6,7> - 3363538874U, // <1,3,7,7>: Cost 4 vmrglw <1,3,1,7>, <2,6,3,7> - 3244387083U, // <1,3,7,u>: Cost 3 vsldoi12 <3,7,u,1>, <3,7,u,1> - 3358237590U, // <1,3,u,0>: Cost 3 vmrglw <0,4,1,u>, <1,2,3,0> - 4162180910U, // <1,3,u,1>: Cost 3 vsldoi8 <0,2,1,3>, LHS - 4039427622U, // <1,3,u,2>: Cost 3 vsldoi4 <2,1,3,u>, <2,1,3,u> - 3356911704U, // <1,3,u,3>: Cost 3 vmrglw <0,2,1,u>, <2,u,3,3> - 3358237594U, // <1,3,u,4>: Cost 3 vmrglw <0,4,1,u>, <1,2,3,4> - 4162181274U, // <1,3,u,5>: Cost 3 vsldoi8 <0,2,1,3>, RHS - 3228748408U, // <1,3,u,6>: Cost 3 vmrghw <1,2,3,0>, <3,6,0,7> - 3358238650U, // <1,3,u,7>: Cost 3 vmrglw <0,4,1,u>, <2,6,3,7> - 4162181477U, // <1,3,u,u>: Cost 3 vsldoi8 <0,2,1,3>, LHS - 4160856077U, // <1,4,0,0>: Cost 3 vsldoi8 <0,0,1,4>, <0,0,1,4> - 4162846822U, // <1,4,0,1>: Cost 3 vsldoi8 <0,3,1,4>, LHS - 4162183343U, // <1,4,0,2>: Cost 4 vsldoi8 <0,2,1,4>, <0,2,1,4> - 4162846976U, // <1,4,0,3>: Cost 3 vsldoi8 <0,3,1,4>, <0,3,1,4> - 4160856402U, // <1,4,0,4>: Cost 3 vsldoi8 <0,0,1,4>, <0,4,1,5> - 3245493138U, // <1,4,0,5>: Cost 2 vsldoi12 <4,0,5,1>, <4,0,5,1> - 4178772470U, // <1,4,0,6>: Cost 4 vsldoi8 <3,0,1,4>, <0,6,1,7> - 4165501508U, // <1,4,0,7>: Cost 3 vsldoi8 <0,7,1,4>, <0,7,1,4> - 3245714349U, // <1,4,0,u>: Cost 2 vsldoi12 <4,0,u,1>, <4,0,u,1> - 3227945874U, // <1,4,1,0>: Cost 3 vmrghw <1,1,1,1>, <4,0,5,1> - 4167492407U, // <1,4,1,1>: Cost 3 vsldoi8 <1,1,1,4>, <1,1,1,4> - 4162847638U, // <1,4,1,2>: Cost 4 vsldoi8 <0,3,1,4>, <1,2,3,0> - 4168819673U, // <1,4,1,3>: Cost 4 vsldoi8 <1,3,1,4>, <1,3,1,4> - 3408612560U, // <1,4,1,4>: Cost 3 vmrglw , <4,4,4,4> - 2154204470U, // <1,4,1,5>: Cost 2 vmrghw <1,1,1,1>, RHS - 4162847978U, // <1,4,1,6>: Cost 4 vsldoi8 <0,3,1,4>, <1,6,4,7> - 3263335412U, // <1,4,1,7>: Cost 4 vsldoi12 <7,0,4,1>, <4,1,7,0> - 2154204713U, // <1,4,1,u>: Cost 2 vmrghw <1,1,1,1>, RHS - 3228748690U, // <1,4,2,0>: Cost 3 vmrghw <1,2,3,0>, <4,0,5,1> - 3228748772U, // <1,4,2,1>: Cost 3 vmrghw <1,2,3,0>, <4,1,5,2> - 4162848360U, // <1,4,2,2>: Cost 4 vsldoi8 <0,3,1,4>, <2,2,2,2> - 4178773670U, // <1,4,2,3>: Cost 3 vsldoi8 <3,0,1,4>, <2,3,0,1> - 3397340368U, // <1,4,2,4>: Cost 3 vmrglw <7,0,1,2>, <4,4,4,4> - 2155007286U, // <1,4,2,5>: Cost 2 vmrghw <1,2,3,0>, RHS - 4162848698U, // <1,4,2,6>: Cost 4 vsldoi8 <0,3,1,4>, <2,6,3,7> - 3373451932U, // <1,4,2,7>: Cost 4 vmrglw <3,0,1,2>, <3,6,4,7> - 2155007529U, // <1,4,2,u>: Cost 2 vmrghw <1,2,3,0>, RHS - 4178774168U, // <1,4,3,0>: Cost 3 vsldoi8 <3,0,1,4>, <3,0,1,4> - 4162849024U, // <1,4,3,1>: Cost 4 vsldoi8 <0,3,1,4>, <3,1,4,0> - 4178774344U, // <1,4,3,2>: Cost 4 vsldoi8 <3,0,1,4>, <3,2,3,0> - 4162849180U, // <1,4,3,3>: Cost 4 vsldoi8 <0,3,1,4>, <3,3,3,3> - 4162849282U, // <1,4,3,4>: Cost 3 vsldoi8 <0,3,1,4>, <3,4,5,6> - 3356870350U, // <1,4,3,5>: Cost 4 vmrglw <0,2,1,3>, <2,3,4,5> - 4202662576U, // <1,4,3,6>: Cost 4 vsldoi8 <7,0,1,4>, <3,6,7,0> - 3366824604U, // <1,4,3,7>: Cost 5 vmrglw <1,u,1,3>, <3,6,4,7> - 4184083232U, // <1,4,3,u>: Cost 3 vsldoi8 <3,u,1,4>, <3,u,1,4> - 3245493416U, // <1,4,4,0>: Cost 3 vsldoi12 <4,0,5,1>, <4,4,0,0> - 3226840242U, // <1,4,4,1>: Cost 4 vsldoi12 <0,u,4,1>, <4,4,1,1> - 4027524774U, // <1,4,4,2>: Cost 4 vsldoi4 <0,1,4,4>, <2,3,0,1> - 3357541282U, // <1,4,4,3>: Cost 4 vmrglw <0,3,1,4>, <1,2,4,3> - 3250801872U, // <1,4,4,4>: Cost 3 vsldoi12 <4,u,5,1>, <4,4,4,4> - 4162850102U, // <1,4,4,5>: Cost 3 vsldoi8 <0,3,1,4>, RHS - 3357541528U, // <1,4,4,6>: Cost 4 vmrglw <0,3,1,4>, <1,5,4,6> - 4213280204U, // <1,4,4,7>: Cost 4 vsldoi8 , <4,7,5,4> - 4162850345U, // <1,4,4,u>: Cost 3 vsldoi8 <0,3,1,4>, RHS - 4033503334U, // <1,4,5,0>: Cost 3 vsldoi4 <1,1,4,5>, LHS - 3358212133U, // <1,4,5,1>: Cost 3 vmrglw <0,4,1,5>, <0,0,4,1> - 4027532966U, // <1,4,5,2>: Cost 3 vsldoi4 <0,1,4,5>, <2,3,0,1> - 3358212297U, // <1,4,5,3>: Cost 4 vmrglw <0,4,1,5>, <0,2,4,3> - 3358212136U, // <1,4,5,4>: Cost 3 vmrglw <0,4,1,5>, <0,0,4,4> - 3358212461U, // <1,4,5,5>: Cost 3 vmrglw <0,4,1,5>, <0,4,4,5> - 3226619190U, // <1,4,5,6>: Cost 2 vsldoi12 <0,u,1,1>, RHS - 4057396218U, // <1,4,5,7>: Cost 4 vsldoi4 <5,1,4,5>, <7,0,1,2> - 3226619208U, // <1,4,5,u>: Cost 2 vsldoi12 <0,u,1,1>, RHS - 4196692259U, // <1,4,6,0>: Cost 4 vsldoi8 <6,0,1,4>, <6,0,1,4> - 3226840410U, // <1,4,6,1>: Cost 4 vsldoi12 <0,u,4,1>, <4,6,1,7> - 4202664442U, // <1,4,6,2>: Cost 4 vsldoi8 <7,0,1,4>, <6,2,7,3> - 4210627122U, // <1,4,6,3>: Cost 4 vsldoi8 , <6,3,4,5> - 3231608016U, // <1,4,6,4>: Cost 4 vmrghw <1,6,5,7>, <4,4,4,4> - 3231313206U, // <1,4,6,5>: Cost 3 vmrghw <1,6,1,7>, RHS - 4202664760U, // <1,4,6,6>: Cost 4 vsldoi8 <7,0,1,4>, <6,6,6,6> - 4202664782U, // <1,4,6,7>: Cost 3 vsldoi8 <7,0,1,4>, <6,7,0,1> - 3231313449U, // <1,4,6,u>: Cost 3 vmrghw <1,6,1,7>, RHS - 4202664956U, // <1,4,7,0>: Cost 3 vsldoi8 <7,0,1,4>, <7,0,1,4> - 3383444141U, // <1,4,7,1>: Cost 4 vmrglw <4,6,1,7>, <0,u,4,1> - 4208637145U, // <1,4,7,2>: Cost 4 vsldoi8 , <7,2,u,0> - 4210627851U, // <1,4,7,3>: Cost 4 vsldoi8 , <7,3,4,5> - 4213282150U, // <1,4,7,4>: Cost 3 vsldoi8 , <7,4,5,6> - 3365528403U, // <1,4,7,5>: Cost 4 vmrglw <1,6,1,7>, <1,1,4,5> - 4202665492U, // <1,4,7,6>: Cost 4 vsldoi8 <7,0,1,4>, <7,6,7,0> - 4202665580U, // <1,4,7,7>: Cost 4 vsldoi8 <7,0,1,4>, <7,7,7,7> - 4207974020U, // <1,4,7,u>: Cost 3 vsldoi8 <7,u,1,4>, <7,u,1,4> - 4033527910U, // <1,4,u,0>: Cost 3 vsldoi4 <1,1,4,u>, LHS - 4162852654U, // <1,4,u,1>: Cost 3 vsldoi8 <0,3,1,4>, LHS - 4027557542U, // <1,4,u,2>: Cost 3 vsldoi4 <0,1,4,u>, <2,3,0,1> - 4210628552U, // <1,4,u,3>: Cost 3 vsldoi8 , - 4166170687U, // <1,4,u,4>: Cost 3 vsldoi8 <0,u,1,4>, - 2158988598U, // <1,4,u,5>: Cost 2 vmrghw <1,u,3,0>, RHS - 3226619433U, // <1,4,u,6>: Cost 2 vsldoi12 <0,u,1,1>, RHS - 4213283084U, // <1,4,u,7>: Cost 3 vsldoi8 , - 3226619451U, // <1,4,u,u>: Cost 2 vsldoi12 <0,u,1,1>, RHS - 4163518464U, // <1,5,0,0>: Cost 3 vsldoi8 <0,4,1,5>, <0,0,0,0> - 3089776742U, // <1,5,0,1>: Cost 2 vsldoi8 <0,4,1,5>, LHS - 4162191536U, // <1,5,0,2>: Cost 4 vsldoi8 <0,2,1,5>, <0,2,1,5> - 4163518716U, // <1,5,0,3>: Cost 4 vsldoi8 <0,4,1,5>, <0,3,1,0> - 3089776978U, // <1,5,0,4>: Cost 2 vsldoi8 <0,4,1,5>, <0,4,1,5> - 4164182435U, // <1,5,0,5>: Cost 3 vsldoi8 <0,5,1,5>, <0,5,1,5> - 3251539572U, // <1,5,0,6>: Cost 3 vsldoi12 <5,0,6,1>, <5,0,6,1> - 4069373037U, // <1,5,0,7>: Cost 4 vsldoi4 <7,1,5,0>, <7,1,5,0> - 3089777309U, // <1,5,0,u>: Cost 2 vsldoi8 <0,4,1,5>, LHS - 3250802319U, // <1,5,1,0>: Cost 3 vsldoi12 <4,u,5,1>, <5,1,0,1> - 4163519284U, // <1,5,1,1>: Cost 3 vsldoi8 <0,4,1,5>, <1,1,1,1> - 4163519382U, // <1,5,1,2>: Cost 3 vsldoi8 <0,4,1,5>, <1,2,3,0> - 4163519481U, // <1,5,1,3>: Cost 4 vsldoi8 <0,4,1,5>, <1,3,5,0> - 4169491499U, // <1,5,1,4>: Cost 3 vsldoi8 <1,4,1,5>, <1,4,1,5> - 4163519599U, // <1,5,1,5>: Cost 3 vsldoi8 <0,4,1,5>, <1,5,0,1> - 4163519731U, // <1,5,1,6>: Cost 3 vsldoi8 <0,4,1,5>, <1,6,5,7> - 3360834803U, // <1,5,1,7>: Cost 4 vmrglw <0,u,1,1>, <1,6,5,7> - 4163519868U, // <1,5,1,u>: Cost 3 vsldoi8 <0,4,1,5>, <1,u,3,0> - 3397340616U, // <1,5,2,0>: Cost 3 vmrglw <7,0,1,2>, <4,7,5,0> - 4163520035U, // <1,5,2,1>: Cost 3 vsldoi8 <0,4,1,5>, <2,1,3,5> - 4163520104U, // <1,5,2,2>: Cost 3 vsldoi8 <0,4,1,5>, <2,2,2,2> - 4163520166U, // <1,5,2,3>: Cost 3 vsldoi8 <0,4,1,5>, <2,3,0,1> - 4051471332U, // <1,5,2,4>: Cost 3 vsldoi4 <4,1,5,2>, <4,1,5,2> - 3397340378U, // <1,5,2,5>: Cost 3 vmrglw <7,0,1,2>, <4,4,5,5> - 4163520442U, // <1,5,2,6>: Cost 3 vsldoi8 <0,4,1,5>, <2,6,3,7> - 3373450483U, // <1,5,2,7>: Cost 4 vmrglw <3,0,1,2>, <1,6,5,7> - 4163520571U, // <1,5,2,u>: Cost 3 vsldoi8 <0,4,1,5>, <2,u,0,1> - 4163520662U, // <1,5,3,0>: Cost 3 vsldoi8 <0,4,1,5>, <3,0,1,2> - 3386732058U, // <1,5,3,1>: Cost 3 vmrglw <5,2,1,3>, <4,u,5,1> - 4163520833U, // <1,5,3,2>: Cost 4 vsldoi8 <0,4,1,5>, <3,2,2,2> - 4163520924U, // <1,5,3,3>: Cost 3 vsldoi8 <0,4,1,5>, <3,3,3,3> - 4163521026U, // <1,5,3,4>: Cost 3 vsldoi8 <0,4,1,5>, <3,4,5,6> - 3386731738U, // <1,5,3,5>: Cost 4 vmrglw <5,2,1,3>, <4,4,5,5> - 3356871170U, // <1,5,3,6>: Cost 4 vmrglw <0,2,1,3>, <3,4,5,6> - 4211296963U, // <1,5,3,7>: Cost 4 vsldoi8 , <3,7,0,1> - 4163521310U, // <1,5,3,u>: Cost 3 vsldoi8 <0,4,1,5>, <3,u,1,2> - 4051484774U, // <1,5,4,0>: Cost 3 vsldoi4 <4,1,5,4>, LHS - 4163521506U, // <1,5,4,1>: Cost 3 vsldoi8 <0,4,1,5>, <4,1,5,0> - 4051486243U, // <1,5,4,2>: Cost 4 vsldoi4 <4,1,5,4>, <2,1,3,5> - 4045515021U, // <1,5,4,3>: Cost 4 vsldoi4 <3,1,5,4>, <3,1,5,4> - 4163521744U, // <1,5,4,4>: Cost 3 vsldoi8 <0,4,1,5>, <4,4,4,4> - 3089780022U, // <1,5,4,5>: Cost 2 vsldoi8 <0,4,1,5>, RHS - 3357542914U, // <1,5,4,6>: Cost 3 vmrglw <0,3,1,4>, <3,4,5,6> - 4069405809U, // <1,5,4,7>: Cost 4 vsldoi4 <7,1,5,4>, <7,1,5,4> - 3089780265U, // <1,5,4,u>: Cost 2 vsldoi8 <0,4,1,5>, RHS - 4033577062U, // <1,5,5,0>: Cost 3 vsldoi4 <1,1,5,5>, LHS - 4033577820U, // <1,5,5,1>: Cost 3 vsldoi4 <1,1,5,5>, <1,1,5,5> - 4033578531U, // <1,5,5,2>: Cost 4 vsldoi4 <1,1,5,5>, <2,1,3,5> - 3358213035U, // <1,5,5,3>: Cost 3 vmrglw <0,4,1,5>, <1,2,5,3> - 4033580342U, // <1,5,5,4>: Cost 3 vsldoi4 <1,1,5,5>, RHS - 3358212956U, // <1,5,5,5>: Cost 3 vmrglw <0,4,1,5>, <1,1,5,5> - 3358214658U, // <1,5,5,6>: Cost 3 vmrglw <0,4,1,5>, <3,4,5,6> - 3358213363U, // <1,5,5,7>: Cost 3 vmrglw <0,4,1,5>, <1,6,5,7> - 3358213040U, // <1,5,5,u>: Cost 3 vmrglw <0,4,1,5>, <1,2,5,u> - 3255078948U, // <1,5,6,0>: Cost 3 vsldoi12 <5,6,0,1>, <5,6,0,1> - 3250802739U, // <1,5,6,1>: Cost 3 vsldoi12 <4,u,5,1>, <5,6,1,7> - 4211298810U, // <1,5,6,2>: Cost 3 vsldoi8 , <6,2,7,3> - 3244757058U, // <1,5,6,3>: Cost 4 vsldoi12 <3,u,4,1>, <5,6,3,4> - 3231608756U, // <1,5,6,4>: Cost 4 vmrghw <1,6,5,7>, <5,4,5,6> - 3231608836U, // <1,5,6,5>: Cost 4 vmrghw <1,6,5,7>, <5,5,5,5> - 4211299128U, // <1,5,6,6>: Cost 3 vsldoi8 , <6,6,6,6> - 3250802786U, // <1,5,6,7>: Cost 3 vsldoi12 <4,u,5,1>, <5,6,7,0> - 3250802795U, // <1,5,6,u>: Cost 3 vsldoi12 <4,u,5,1>, <5,6,u,0> - 4211299322U, // <1,5,7,0>: Cost 3 vsldoi8 , <7,0,1,2> - 3389419034U, // <1,5,7,1>: Cost 3 vmrglw <5,6,1,7>, <4,u,5,1> - 4211299476U, // <1,5,7,2>: Cost 4 vsldoi8 , <7,2,0,3> - 4211299555U, // <1,5,7,3>: Cost 4 vsldoi8 , <7,3,0,1> - 4211299686U, // <1,5,7,4>: Cost 3 vsldoi8 , <7,4,5,6> - 3389418714U, // <1,5,7,5>: Cost 4 vmrglw <5,6,1,7>, <4,4,5,5> - 3365528656U, // <1,5,7,6>: Cost 4 vmrglw <1,6,1,7>, <1,4,5,6> - 4211299948U, // <1,5,7,7>: Cost 3 vsldoi8 , <7,7,7,7> - 4211299970U, // <1,5,7,u>: Cost 3 vsldoi8 , <7,u,1,2> - 4163524307U, // <1,5,u,0>: Cost 3 vsldoi8 <0,4,1,5>, - 3089782574U, // <1,5,u,1>: Cost 2 vsldoi8 <0,4,1,5>, LHS - 4163524488U, // <1,5,u,2>: Cost 3 vsldoi8 <0,4,1,5>, - 4163524540U, // <1,5,u,3>: Cost 3 vsldoi8 <0,4,1,5>, - 3137558554U, // <1,5,u,4>: Cost 2 vsldoi8 , - 3089782938U, // <1,5,u,5>: Cost 2 vsldoi8 <0,4,1,5>, RHS - 4163524816U, // <1,5,u,6>: Cost 3 vsldoi8 <0,4,1,5>, - 3250802948U, // <1,5,u,7>: Cost 3 vsldoi12 <4,u,5,1>, <5,u,7,0> - 3089783141U, // <1,5,u,u>: Cost 2 vsldoi8 <0,4,1,5>, LHS - 4162199552U, // <1,6,0,0>: Cost 4 vsldoi8 <0,2,1,6>, <0,0,0,0> - 4162199654U, // <1,6,0,1>: Cost 3 vsldoi8 <0,2,1,6>, LHS - 4162199729U, // <1,6,0,2>: Cost 3 vsldoi8 <0,2,1,6>, <0,2,1,6> - 3257291058U, // <1,6,0,3>: Cost 4 vsldoi12 <6,0,3,1>, <6,0,3,1> - 4162199890U, // <1,6,0,4>: Cost 4 vsldoi8 <0,2,1,6>, <0,4,1,5> - 4164190628U, // <1,6,0,5>: Cost 3 vsldoi8 <0,5,1,6>, <0,5,1,6> - 4164854261U, // <1,6,0,6>: Cost 3 vsldoi8 <0,6,1,6>, <0,6,1,6> - 3357510966U, // <1,6,0,7>: Cost 3 vmrglw <0,3,1,0>, RHS - 4162200221U, // <1,6,0,u>: Cost 3 vsldoi8 <0,2,1,6>, LHS - 4033618022U, // <1,6,1,0>: Cost 4 vsldoi4 <1,1,6,1>, LHS - 4162200372U, // <1,6,1,1>: Cost 4 vsldoi8 <0,2,1,6>, <1,1,1,1> - 3227947514U, // <1,6,1,2>: Cost 3 vmrghw <1,1,1,1>, <6,2,7,3> - 4162200585U, // <1,6,1,3>: Cost 4 vsldoi8 <0,2,1,6>, <1,3,6,7> - 4033621302U, // <1,6,1,4>: Cost 4 vsldoi4 <1,1,6,1>, RHS - 4170163325U, // <1,6,1,5>: Cost 4 vsldoi8 <1,5,1,6>, <1,5,1,6> - 3408614200U, // <1,6,1,6>: Cost 3 vmrglw , <6,6,6,6> - 2287095094U, // <1,6,1,7>: Cost 2 vmrglw <0,u,1,1>, RHS - 2287095095U, // <1,6,1,u>: Cost 2 vmrglw <0,u,1,1>, RHS - 4039598182U, // <1,6,2,0>: Cost 4 vsldoi4 <2,1,6,2>, LHS - 4162201145U, // <1,6,2,1>: Cost 4 vsldoi8 <0,2,1,6>, <2,1,6,0> - 3228750330U, // <1,6,2,2>: Cost 3 vmrghw <1,2,3,0>, <6,2,7,3> - 4162201254U, // <1,6,2,3>: Cost 4 vsldoi8 <0,2,1,6>, <2,3,0,1> - 4039601462U, // <1,6,2,4>: Cost 4 vsldoi4 <2,1,6,2>, RHS - 3373451057U, // <1,6,2,5>: Cost 4 vmrglw <3,0,1,2>, <2,4,6,5> - 4162201530U, // <1,6,2,6>: Cost 3 vsldoi8 <0,2,1,6>, <2,6,3,7> - 2299710774U, // <1,6,2,7>: Cost 2 vmrglw <3,0,1,2>, RHS - 2299710775U, // <1,6,2,u>: Cost 2 vmrglw <3,0,1,2>, RHS - 4162201750U, // <1,6,3,0>: Cost 4 vsldoi8 <0,2,1,6>, <3,0,1,2> - 3238933017U, // <1,6,3,1>: Cost 4 vsldoi12 <2,u,6,1>, <6,3,1,7> - 4162201958U, // <1,6,3,2>: Cost 4 vsldoi8 <0,2,1,6>, <3,2,6,3> - 4162202012U, // <1,6,3,3>: Cost 4 vsldoi8 <0,2,1,6>, <3,3,3,3> - 4162202114U, // <1,6,3,4>: Cost 4 vsldoi8 <0,2,1,6>, <3,4,5,6> - 4211968605U, // <1,6,3,5>: Cost 4 vsldoi8 , <3,5,6,7> - 3386733368U, // <1,6,3,6>: Cost 4 vmrglw <5,2,1,3>, <6,6,6,6> - 3356871990U, // <1,6,3,7>: Cost 3 vmrglw <0,2,1,3>, RHS - 3356871991U, // <1,6,3,u>: Cost 3 vmrglw <0,2,1,3>, RHS - 4039614566U, // <1,6,4,0>: Cost 4 vsldoi4 <2,1,6,4>, LHS - 3258249832U, // <1,6,4,1>: Cost 4 vsldoi12 <6,1,7,1>, <6,4,1,5> - 4039616061U, // <1,6,4,2>: Cost 4 vsldoi4 <2,1,6,4>, <2,1,6,4> - 4057532930U, // <1,6,4,3>: Cost 4 vsldoi4 <5,1,6,4>, <3,4,5,6> - 4039617846U, // <1,6,4,4>: Cost 4 vsldoi4 <2,1,6,4>, RHS - 4162202934U, // <1,6,4,5>: Cost 3 vsldoi8 <0,2,1,6>, RHS - 3261641365U, // <1,6,4,6>: Cost 4 vsldoi12 <6,6,u,1>, <6,4,6,5> - 3357543734U, // <1,6,4,7>: Cost 3 vmrglw <0,3,1,4>, RHS - 4162203177U, // <1,6,4,u>: Cost 3 vsldoi8 <0,2,1,6>, RHS - 4045594726U, // <1,6,5,0>: Cost 4 vsldoi4 <3,1,6,5>, LHS - 4045595891U, // <1,6,5,1>: Cost 4 vsldoi4 <3,1,6,5>, <1,6,5,7> - 3405989597U, // <1,6,5,2>: Cost 4 vmrglw , <2,3,6,2> - 3358214502U, // <1,6,5,3>: Cost 4 vmrglw <0,4,1,5>, <3,2,6,3> - 4045598006U, // <1,6,5,4>: Cost 4 vsldoi4 <3,1,6,5>, RHS - 4057542345U, // <1,6,5,5>: Cost 4 vsldoi4 <5,1,6,5>, <5,1,6,5> - 3405992760U, // <1,6,5,6>: Cost 3 vmrglw , <6,6,6,6> - 2284473654U, // <1,6,5,7>: Cost 2 vmrglw <0,4,1,5>, RHS - 2284473655U, // <1,6,5,u>: Cost 2 vmrglw <0,4,1,5>, RHS - 3261051645U, // <1,6,6,0>: Cost 3 vsldoi12 <6,6,0,1>, <6,6,0,1> - 4033659750U, // <1,6,6,1>: Cost 4 vsldoi4 <1,1,6,6>, <1,1,6,6> - 4033660858U, // <1,6,6,2>: Cost 4 vsldoi4 <1,1,6,6>, <2,6,3,7> - 3356894132U, // <1,6,6,3>: Cost 4 vmrglw <0,2,1,6>, <1,2,6,3> - 4033662262U, // <1,6,6,4>: Cost 4 vsldoi4 <1,1,6,6>, RHS - 4057550538U, // <1,6,6,5>: Cost 4 vsldoi4 <5,1,6,6>, <5,1,6,6> - 3250803512U, // <1,6,6,6>: Cost 3 vsldoi12 <4,u,5,1>, <6,6,6,6> - 3356896566U, // <1,6,6,7>: Cost 3 vmrglw <0,2,1,6>, RHS - 3356896567U, // <1,6,6,u>: Cost 3 vmrglw <0,2,1,6>, RHS - 3261715278U, // <1,6,7,0>: Cost 2 vsldoi12 <6,7,0,1>, <6,7,0,1> - 3261789015U, // <1,6,7,1>: Cost 3 vsldoi12 <6,7,1,1>, <6,7,1,1> - 3235173218U, // <1,6,7,2>: Cost 3 vsldoi12 <2,3,0,1>, <6,7,2,3> - 3250803560U, // <1,6,7,3>: Cost 4 vsldoi12 <4,u,5,1>, <6,7,3,0> - 3250803574U, // <1,6,7,4>: Cost 3 vsldoi12 <4,u,5,1>, <6,7,4,5> - 3365528664U, // <1,6,7,5>: Cost 4 vmrglw <1,6,1,7>, <1,4,6,5> - 3261715338U, // <1,6,7,6>: Cost 3 vsldoi12 <6,7,0,1>, <6,7,6,7> - 3365530934U, // <1,6,7,7>: Cost 3 vmrglw <1,6,1,7>, RHS - 3262305174U, // <1,6,7,u>: Cost 2 vsldoi12 <6,7,u,1>, <6,7,u,1> - 3262378911U, // <1,6,u,0>: Cost 2 vsldoi12 <6,u,0,1>, <6,u,0,1> - 4162205486U, // <1,6,u,1>: Cost 3 vsldoi8 <0,2,1,6>, LHS - 3262526385U, // <1,6,u,2>: Cost 3 vsldoi12 <6,u,2,1>, <6,u,2,1> - 4162205628U, // <1,6,u,3>: Cost 4 vsldoi8 <0,2,1,6>, - 3250803655U, // <1,6,u,4>: Cost 3 vsldoi12 <4,u,5,1>, <6,u,4,5> - 4162205850U, // <1,6,u,5>: Cost 3 vsldoi8 <0,2,1,6>, RHS - 4166187216U, // <1,6,u,6>: Cost 3 vsldoi8 <0,u,1,6>, - 2284498230U, // <1,6,u,7>: Cost 2 vmrglw <0,4,1,u>, RHS - 2284498231U, // <1,6,u,u>: Cost 2 vmrglw <0,4,1,u>, RHS - 3263042544U, // <1,7,0,0>: Cost 3 vsldoi12 <7,0,0,1>, <7,0,0,1> - 4170834022U, // <1,7,0,1>: Cost 3 vsldoi8 <1,6,1,7>, LHS - 3393343912U, // <1,7,0,2>: Cost 4 vmrglw <6,3,1,0>, <6,1,7,2> - 3397325306U, // <1,7,0,3>: Cost 4 vmrglw <7,0,1,0>, <6,2,7,3> - 3263337492U, // <1,7,0,4>: Cost 3 vsldoi12 <7,0,4,1>, <7,0,4,1> - 4057575117U, // <1,7,0,5>: Cost 4 vsldoi4 <5,1,7,0>, <5,1,7,0> - 4164862454U, // <1,7,0,6>: Cost 3 vsldoi8 <0,6,1,7>, <0,6,1,7> - 4165526087U, // <1,7,0,7>: Cost 3 vsldoi8 <0,7,1,7>, <0,7,1,7> - 4170834578U, // <1,7,0,u>: Cost 3 vsldoi8 <1,6,1,7>, <0,u,1,1> - 4063551498U, // <1,7,1,0>: Cost 3 vsldoi4 <6,1,7,1>, <0,0,1,1> - 3263779914U, // <1,7,1,1>: Cost 3 vsldoi12 <7,1,1,1>, <7,1,1,1> - 4170834823U, // <1,7,1,2>: Cost 4 vsldoi8 <1,6,1,7>, <1,2,1,3> - 3408613882U, // <1,7,1,3>: Cost 3 vmrglw , <6,2,7,3> - 4063554870U, // <1,7,1,4>: Cost 3 vsldoi4 <6,1,7,1>, RHS - 4194722981U, // <1,7,1,5>: Cost 4 vsldoi8 <5,6,1,7>, <1,5,6,1> - 4170835151U, // <1,7,1,6>: Cost 3 vsldoi8 <1,6,1,7>, <1,6,1,7> - 3408614210U, // <1,7,1,7>: Cost 3 vmrglw , <6,6,7,7> - 4172162417U, // <1,7,1,u>: Cost 3 vsldoi8 <1,u,1,7>, <1,u,1,7> - 4063559782U, // <1,7,2,0>: Cost 3 vsldoi4 <6,1,7,2>, LHS - 3228750933U, // <1,7,2,1>: Cost 3 vmrghw <1,2,3,0>, <7,1,2,3> - 3373453736U, // <1,7,2,2>: Cost 3 vmrglw <3,0,1,2>, <6,1,7,2> - 4063561878U, // <1,7,2,3>: Cost 3 vsldoi4 <6,1,7,2>, <3,0,1,2> - 4063563062U, // <1,7,2,4>: Cost 3 vsldoi4 <6,1,7,2>, RHS - 3385397675U, // <1,7,2,5>: Cost 4 vmrglw <5,0,1,2>, <6,1,7,5> - 4063564200U, // <1,7,2,6>: Cost 3 vsldoi4 <6,1,7,2>, <6,1,7,2> - 3397341451U, // <1,7,2,7>: Cost 3 vmrglw <7,0,1,2>, <5,u,7,7> - 4063565614U, // <1,7,2,u>: Cost 3 vsldoi4 <6,1,7,2>, LHS - 3265033443U, // <1,7,3,0>: Cost 3 vsldoi12 <7,3,0,1>, <7,3,0,1> - 4170836243U, // <1,7,3,1>: Cost 4 vsldoi8 <1,6,1,7>, <3,1,6,1> - 4063569574U, // <1,7,3,2>: Cost 4 vsldoi4 <6,1,7,3>, <2,3,0,1> - 4170836380U, // <1,7,3,3>: Cost 4 vsldoi8 <1,6,1,7>, <3,3,3,3> - 4170836482U, // <1,7,3,4>: Cost 4 vsldoi8 <1,6,1,7>, <3,4,5,6> - 4194724439U, // <1,7,3,5>: Cost 4 vsldoi8 <5,6,1,7>, <3,5,6,1> - 4182780545U, // <1,7,3,6>: Cost 4 vsldoi8 <3,6,1,7>, <3,6,1,7> - 3243799841U, // <1,7,3,7>: Cost 4 vsldoi12 <3,7,0,1>, <7,3,7,0> - 3265623339U, // <1,7,3,u>: Cost 3 vsldoi12 <7,3,u,1>, <7,3,u,1> - 3265697076U, // <1,7,4,0>: Cost 3 vsldoi12 <7,4,0,1>, <7,4,0,1> - 4063577295U, // <1,7,4,1>: Cost 4 vsldoi4 <6,1,7,4>, <1,6,1,7> - 3235173704U, // <1,7,4,2>: Cost 4 vsldoi12 <2,3,0,1>, <7,4,2,3> - 3397358074U, // <1,7,4,3>: Cost 4 vmrglw <7,0,1,4>, <6,2,7,3> - 3250804059U, // <1,7,4,4>: Cost 4 vsldoi12 <4,u,5,1>, <7,4,4,4> - 4170837302U, // <1,7,4,5>: Cost 3 vsldoi8 <1,6,1,7>, RHS - 4188753242U, // <1,7,4,6>: Cost 4 vsldoi8 <4,6,1,7>, <4,6,1,7> - 4057609574U, // <1,7,4,7>: Cost 4 vsldoi4 <5,1,7,4>, <7,4,5,6> - 4170837545U, // <1,7,4,u>: Cost 3 vsldoi8 <1,6,1,7>, RHS - 4063584358U, // <1,7,5,0>: Cost 3 vsldoi4 <6,1,7,5>, LHS - 3250804117U, // <1,7,5,1>: Cost 4 vsldoi12 <4,u,5,1>, <7,5,1,u> - 4045670330U, // <1,7,5,2>: Cost 4 vsldoi4 <3,1,7,5>, <2,6,3,7> - 3405992442U, // <1,7,5,3>: Cost 3 vmrglw , <6,2,7,3> - 4063587638U, // <1,7,5,4>: Cost 3 vsldoi4 <6,1,7,5>, RHS - 3358216619U, // <1,7,5,5>: Cost 3 vmrglw <0,4,1,5>, <6,1,7,5> - 4194725939U, // <1,7,5,6>: Cost 3 vsldoi8 <5,6,1,7>, <5,6,1,7> - 3405992770U, // <1,7,5,7>: Cost 3 vmrglw , <6,6,7,7> - 4196053205U, // <1,7,5,u>: Cost 3 vsldoi8 <5,u,1,7>, <5,u,1,7> - 3406663778U, // <1,7,6,0>: Cost 3 vmrglw , <5,6,7,0> - 4170838438U, // <1,7,6,1>: Cost 4 vsldoi8 <1,6,1,7>, <6,1,7,0> - 4045678522U, // <1,7,6,2>: Cost 4 vsldoi4 <3,1,7,6>, <2,6,3,7> - 4045678881U, // <1,7,6,3>: Cost 4 vsldoi4 <3,1,7,6>, <3,1,7,6> - 4045679926U, // <1,7,6,4>: Cost 4 vsldoi4 <3,1,7,6>, RHS - 3260904969U, // <1,7,6,5>: Cost 4 vsldoi12 <6,5,7,1>, <7,6,5,7> - 3250804241U, // <1,7,6,6>: Cost 4 vsldoi12 <4,u,5,1>, <7,6,6,6> - 3261715988U, // <1,7,6,7>: Cost 3 vsldoi12 <6,7,0,1>, <7,6,7,0> - 3262379549U, // <1,7,6,u>: Cost 3 vsldoi12 <6,u,0,1>, <7,6,u,0> - 3267687975U, // <1,7,7,0>: Cost 3 vsldoi12 <7,7,0,1>, <7,7,0,1> - 3365528426U, // <1,7,7,1>: Cost 4 vmrglw <1,6,1,7>, <1,1,7,1> - 4063602342U, // <1,7,7,2>: Cost 4 vsldoi4 <6,1,7,7>, <2,3,0,1> - 3365528509U, // <1,7,7,3>: Cost 4 vmrglw <1,6,1,7>, <1,2,7,3> - 3250804303U, // <1,7,7,4>: Cost 4 vsldoi12 <4,u,5,1>, <7,7,4,5> - 4057632468U, // <1,7,7,5>: Cost 4 vsldoi4 <5,1,7,7>, <5,1,7,7> - 4063605165U, // <1,7,7,6>: Cost 4 vsldoi4 <6,1,7,7>, <6,1,7,7> - 3250804332U, // <1,7,7,7>: Cost 3 vsldoi12 <4,u,5,1>, <7,7,7,7> - 3268277871U, // <1,7,7,u>: Cost 3 vsldoi12 <7,7,u,1>, <7,7,u,1> - 4063608849U, // <1,7,u,0>: Cost 3 vsldoi4 <6,1,7,u>, <0,0,1,u> - 4170839854U, // <1,7,u,1>: Cost 3 vsldoi8 <1,6,1,7>, LHS - 3373453736U, // <1,7,u,2>: Cost 3 vmrglw <3,0,1,2>, <6,1,7,2> - 3397390842U, // <1,7,u,3>: Cost 3 vmrglw <7,0,1,u>, <6,2,7,3> - 4063612214U, // <1,7,u,4>: Cost 3 vsldoi4 <6,1,7,u>, RHS - 4170840218U, // <1,7,u,5>: Cost 3 vsldoi8 <1,6,1,7>, RHS - 4063613358U, // <1,7,u,6>: Cost 3 vsldoi4 <6,1,7,u>, <6,1,7,u> - 3397391170U, // <1,7,u,7>: Cost 3 vmrglw <7,0,1,u>, <6,6,7,7> - 4170840421U, // <1,7,u,u>: Cost 3 vsldoi8 <1,6,1,7>, LHS - 3087147025U, // <1,u,0,0>: Cost 2 vsldoi8 <0,0,1,u>, <0,0,1,u> - 3089801318U, // <1,u,0,1>: Cost 2 vsldoi8 <0,4,1,u>, LHS - 4162216115U, // <1,u,0,2>: Cost 3 vsldoi8 <0,2,1,u>, <0,2,1,u> - 3357507740U, // <1,u,0,3>: Cost 3 vmrglw <0,3,1,0>, LHS - 3089801557U, // <1,u,0,4>: Cost 2 vsldoi8 <0,4,1,u>, <0,4,1,u> - 3269383926U, // <1,u,0,5>: Cost 2 vsldoi12 , - 4164870647U, // <1,u,0,6>: Cost 3 vsldoi8 <0,6,1,u>, <0,6,1,u> - 3357510984U, // <1,u,0,7>: Cost 3 vmrglw <0,3,1,0>, RHS - 3089801885U, // <1,u,0,u>: Cost 2 vsldoi8 <0,4,1,u>, LHS - 2959507558U, // <1,u,1,0>: Cost 2 vsldoi4 <1,1,1,1>, LHS - 1477230694U, // <1,u,1,1>: Cost 1 vspltisw1 LHS - 3226621742U, // <1,u,1,2>: Cost 2 vsldoi12 <0,u,1,1>, LHS - 2287091868U, // <1,u,1,3>: Cost 2 vmrglw <0,u,1,1>, LHS - 2959510838U, // <1,u,1,4>: Cost 2 vsldoi4 <1,1,1,1>, RHS - 2154207386U, // <1,u,1,5>: Cost 2 vmrghw <1,1,1,1>, RHS - 4163544334U, // <1,u,1,6>: Cost 3 vsldoi8 <0,4,1,u>, <1,6,u,7> - 2287095112U, // <1,u,1,7>: Cost 2 vmrglw <0,u,1,1>, RHS - 1477230694U, // <1,u,1,u>: Cost 1 vspltisw1 LHS - 3228751571U, // <1,u,2,0>: Cost 3 vmrghw <1,2,3,0>, - 2155009838U, // <1,u,2,1>: Cost 2 vmrghw <1,2,3,0>, LHS - 2155004822U, // <1,u,2,2>: Cost 2 vmrghw <1,2,3,0>, <1,2,3,0> - 2299707548U, // <1,u,2,3>: Cost 2 vmrglw <3,0,1,2>, LHS - 3228751935U, // <1,u,2,4>: Cost 3 vmrghw <1,2,3,0>, - 2155010202U, // <1,u,2,5>: Cost 2 vmrghw <1,2,3,0>, RHS - 4163545018U, // <1,u,2,6>: Cost 3 vsldoi8 <0,4,1,u>, <2,6,3,7> - 2299710792U, // <1,u,2,7>: Cost 2 vmrglw <3,0,1,2>, RHS - 2155010405U, // <1,u,2,u>: Cost 2 vmrghw <1,2,3,0>, LHS - 1880326300U, // <1,u,3,0>: Cost 1 vsldoi4 LHS, LHS - 2954068788U, // <1,u,3,1>: Cost 2 vsldoi4 LHS, <1,1,1,1> - 2954069608U, // <1,u,3,2>: Cost 2 vsldoi4 LHS, <2,2,2,2> - 2954070166U, // <1,u,3,3>: Cost 2 vsldoi4 LHS, <3,0,1,2> - 1880329526U, // <1,u,3,4>: Cost 1 vsldoi4 LHS, RHS - 3001847812U, // <1,u,3,5>: Cost 2 vsldoi4 LHS, <5,5,5,5> - 3001848314U, // <1,u,3,6>: Cost 2 vsldoi4 LHS, <6,2,7,3> - 3001848826U, // <1,u,3,7>: Cost 2 vsldoi4 LHS, <7,0,1,2> - 1880332078U, // <1,u,3,u>: Cost 1 vsldoi4 LHS, LHS - 4184779637U, // <1,u,4,0>: Cost 3 vsldoi8 <4,0,1,u>, <4,0,1,u> - 4163546109U, // <1,u,4,1>: Cost 3 vsldoi8 <0,4,1,u>, <4,1,u,0> - 3230040982U, // <1,u,4,2>: Cost 3 vmrghw <1,4,2,5>, <1,2,3,0> - 3357540508U, // <1,u,4,3>: Cost 3 vmrglw <0,3,1,4>, LHS - 4051708929U, // <1,u,4,4>: Cost 3 vsldoi4 <4,1,u,4>, <4,1,u,4> - 3089804598U, // <1,u,4,5>: Cost 2 vsldoi8 <0,4,1,u>, RHS - 3357542914U, // <1,u,4,6>: Cost 3 vmrglw <0,3,1,4>, <3,4,5,6> - 3357543752U, // <1,u,4,7>: Cost 3 vmrglw <0,3,1,4>, RHS - 3089804841U, // <1,u,4,u>: Cost 2 vsldoi8 <0,4,1,u>, RHS - 3358213059U, // <1,u,5,0>: Cost 3 vmrglw <0,4,1,5>, <1,2,u,0> - 3358213870U, // <1,u,5,1>: Cost 3 vmrglw <0,4,1,5>, <2,3,u,1> - 3358214357U, // <1,u,5,2>: Cost 3 vmrglw <0,4,1,5>, <3,0,u,2> - 2284470428U, // <1,u,5,3>: Cost 2 vmrglw <0,4,1,5>, LHS - 3358213063U, // <1,u,5,4>: Cost 3 vmrglw <0,4,1,5>, <1,2,u,4> - 2284470610U, // <1,u,5,5>: Cost 2 vmrglw <0,4,1,5>, <0,4,1,5> - 3226622106U, // <1,u,5,6>: Cost 2 vsldoi12 <0,u,1,1>, RHS - 2284473672U, // <1,u,5,7>: Cost 2 vmrglw <0,4,1,5>, RHS - 2284470433U, // <1,u,5,u>: Cost 2 vmrglw <0,4,1,5>, LHS - 4196725031U, // <1,u,6,0>: Cost 3 vsldoi8 <6,0,1,u>, <6,0,1,u> - 3227138238U, // <1,u,6,1>: Cost 3 vsldoi12 <0,u,u,1>, - 4202697210U, // <1,u,6,2>: Cost 3 vsldoi8 <7,0,1,u>, <6,2,7,3> - 3356893340U, // <1,u,6,3>: Cost 3 vmrglw <0,2,1,6>, LHS - 3231605074U, // <1,u,6,4>: Cost 3 vmrghw <1,6,5,7>, <0,4,1,5> - 3231316122U, // <1,u,6,5>: Cost 3 vmrghw <1,6,1,7>, RHS - 4202697528U, // <1,u,6,6>: Cost 3 vsldoi8 <7,0,1,u>, <6,6,6,6> - 3356896584U, // <1,u,6,7>: Cost 3 vmrglw <0,2,1,6>, RHS - 3356893345U, // <1,u,6,u>: Cost 3 vmrglw <0,2,1,6>, LHS - 3128955904U, // <1,u,7,0>: Cost 2 vsldoi8 <7,0,1,u>, <7,0,1,u> - 3407332049U, // <1,u,7,1>: Cost 3 vmrglw , <0,u,u,1> - 3235174676U, // <1,u,7,2>: Cost 3 vsldoi12 <2,3,0,1>, - 3365527708U, // <1,u,7,3>: Cost 3 vmrglw <1,6,1,7>, LHS - 3250805032U, // <1,u,7,4>: Cost 3 vsldoi12 <4,u,5,1>, - 3365527953U, // <1,u,7,5>: Cost 4 vmrglw <1,6,1,7>, <0,4,u,5> - 3261716796U, // <1,u,7,6>: Cost 3 vsldoi12 <6,7,0,1>, - 3365530952U, // <1,u,7,7>: Cost 3 vmrglw <1,6,1,7>, RHS - 3134264968U, // <1,u,7,u>: Cost 2 vsldoi8 <7,u,1,u>, <7,u,1,u> - 1880367265U, // <1,u,u,0>: Cost 1 vsldoi4 LHS, LHS - 1477230694U, // <1,u,u,1>: Cost 1 vspltisw1 LHS - 2954110568U, // <1,u,u,2>: Cost 2 vsldoi4 LHS, <2,2,2,2> - 2954111126U, // <1,u,u,3>: Cost 2 vsldoi4 LHS, <3,0,1,2> - 1880370486U, // <1,u,u,4>: Cost 1 vsldoi4 LHS, RHS - 3089807514U, // <1,u,u,5>: Cost 2 vsldoi8 <0,4,1,u>, RHS - 3226622349U, // <1,u,u,6>: Cost 2 vsldoi12 <0,u,1,1>, RHS - 2284498248U, // <1,u,u,7>: Cost 2 vmrglw <0,4,1,u>, RHS - 1880373038U, // <1,u,u,u>: Cost 1 vsldoi4 LHS, LHS - 3233390592U, // <2,0,0,0>: Cost 3 vmrghw <2,0,3,0>, <0,0,0,0> - 3233390694U, // <2,0,0,1>: Cost 3 vmrghw <2,0,3,0>, LHS - 3222642707U, // <2,0,0,2>: Cost 4 vsldoi12 <0,2,1,2>, <0,0,2,1> - 3239231516U, // <2,0,0,3>: Cost 4 vsldoi12 <3,0,1,2>, <0,0,3,1> - 3233390930U, // <2,0,0,4>: Cost 4 vmrghw <2,0,3,0>, <0,4,1,5> - 3356256724U, // <2,0,0,5>: Cost 4 vmrglw <0,1,2,0>, <3,4,0,5> - 3221684280U, // <2,0,0,6>: Cost 4 vsldoi12 <0,0,6,2>, <0,0,6,2> - 4165542473U, // <2,0,0,7>: Cost 4 vsldoi8 <0,7,2,0>, <0,7,2,0> - 3233391261U, // <2,0,0,u>: Cost 3 vmrghw <2,0,3,0>, LHS - 3234062346U, // <2,0,1,0>: Cost 3 vmrghw <2,1,3,1>, <0,0,1,1> - 3234062438U, // <2,0,1,1>: Cost 3 vmrghw <2,1,3,1>, LHS - 3234660454U, // <2,0,1,2>: Cost 2 vsldoi12 <2,2,2,2>, LHS - 4075645141U, // <2,0,1,3>: Cost 3 vsldoi4 , <3,0,u,2> - 3234095442U, // <2,0,1,4>: Cost 3 vmrghw <2,1,3,5>, <0,4,1,5> - 4057730784U, // <2,0,1,5>: Cost 4 vsldoi4 <5,2,0,1>, <5,2,0,1> - 3263119502U, // <2,0,1,6>: Cost 4 vsldoi12 <7,0,1,2>, <0,1,6,7> - 3366881912U, // <2,0,1,7>: Cost 4 vmrglw <1,u,2,1>, <3,6,0,7> - 3234660508U, // <2,0,1,u>: Cost 2 vsldoi12 <2,2,2,2>, LHS - 3234660352U, // <2,0,2,0>: Cost 3 vmrghw <2,2,2,2>, <0,0,0,0> - 2160918630U, // <2,0,2,1>: Cost 2 vmrghw <2,2,2,2>, LHS - 3234660525U, // <2,0,2,2>: Cost 3 vmrghw <2,2,2,2>, <0,2,1,2> - 3234660604U, // <2,0,2,3>: Cost 4 vmrghw <2,2,2,2>, <0,3,1,0> - 3234660690U, // <2,0,2,4>: Cost 3 vmrghw <2,2,2,2>, <0,4,1,5> - 3234660771U, // <2,0,2,5>: Cost 4 vmrghw <2,2,2,2>, <0,5,1,5> - 4183459770U, // <2,0,2,6>: Cost 4 vsldoi8 <3,7,2,0>, <2,6,3,7> - 3368880760U, // <2,0,2,7>: Cost 4 vmrglw <2,2,2,2>, <3,6,0,7> - 2160919197U, // <2,0,2,u>: Cost 2 vmrghw <2,2,2,2>, LHS - 2287181824U, // <2,0,3,0>: Cost 2 vmrglw LHS, <0,0,0,0> - 2287183526U, // <2,0,3,1>: Cost 2 vmrglw LHS, <2,3,0,1> - 3235168430U, // <2,0,3,2>: Cost 3 vmrghw <2,3,0,1>, <0,2,1,3> - 4045801776U, // <2,0,3,3>: Cost 3 vsldoi4 <3,2,0,3>, <3,2,0,3> - 3360924786U, // <2,0,3,4>: Cost 3 vmrglw LHS, <1,5,0,4> - 4069691490U, // <2,0,3,5>: Cost 3 vsldoi4 <7,2,0,3>, <5,6,7,0> - 3235168758U, // <2,0,3,6>: Cost 3 vmrghw <2,3,0,1>, <0,6,1,7> - 4069692564U, // <2,0,3,7>: Cost 3 vsldoi4 <7,2,0,3>, <7,2,0,3> - 2287183533U, // <2,0,3,u>: Cost 2 vmrglw LHS, <2,3,0,u> - 3368894464U, // <2,0,4,0>: Cost 4 vmrglw <2,2,2,4>, <0,0,0,0> - 3234660690U, // <2,0,4,1>: Cost 3 vsldoi12 <2,2,2,2>, <0,4,1,5> - 3222643035U, // <2,0,4,2>: Cost 4 vsldoi12 <0,2,1,2>, <0,4,2,5> - 3239231844U, // <2,0,4,3>: Cost 4 vsldoi12 <3,0,1,2>, <0,4,3,5> - 3234660717U, // <2,0,4,4>: Cost 4 vsldoi12 <2,2,2,2>, <0,4,4,5> - 4209339702U, // <2,0,4,5>: Cost 3 vsldoi8 , RHS - 4200050041U, // <2,0,4,6>: Cost 4 vsldoi8 <6,5,2,0>, <4,6,5,2> - 3263119752U, // <2,0,4,7>: Cost 4 vsldoi12 <7,0,1,2>, <0,4,7,5> - 3234660753U, // <2,0,4,u>: Cost 3 vsldoi12 <2,2,2,2>, <0,4,u,5> - 3364257792U, // <2,0,5,0>: Cost 4 vmrglw <1,4,2,5>, <0,0,0,0> - 3236757606U, // <2,0,5,1>: Cost 3 vmrghw <2,5,3,6>, LHS - 3237126320U, // <2,0,5,2>: Cost 4 vmrghw <2,5,u,6>, <0,2,1,5> - 3364260144U, // <2,0,5,3>: Cost 4 vmrglw <1,4,2,5>, <3,2,0,3> - 3236708690U, // <2,0,5,4>: Cost 4 vmrghw <2,5,3,0>, <0,4,1,5> - 3364260146U, // <2,0,5,5>: Cost 4 vmrglw <1,4,2,5>, <3,2,0,5> - 3263119826U, // <2,0,5,6>: Cost 4 vsldoi12 <7,0,1,2>, <0,5,6,7> - 3364260472U, // <2,0,5,7>: Cost 4 vmrglw <1,4,2,5>, <3,6,0,7> - 3236758173U, // <2,0,5,u>: Cost 3 vmrghw <2,5,3,6>, LHS - 3237429248U, // <2,0,6,0>: Cost 3 vmrghw <2,6,3,7>, <0,0,0,0> - 2163687526U, // <2,0,6,1>: Cost 2 vmrghw <2,6,3,7>, LHS - 3237429425U, // <2,0,6,2>: Cost 3 vmrghw <2,6,3,7>, <0,2,1,6> - 3237429500U, // <2,0,6,3>: Cost 4 vmrghw <2,6,3,7>, <0,3,1,0> - 3237429586U, // <2,0,6,4>: Cost 3 vmrghw <2,6,3,7>, <0,4,1,5> - 4200051389U, // <2,0,6,5>: Cost 4 vsldoi8 <6,5,2,0>, <6,5,2,0> - 3237429750U, // <2,0,6,6>: Cost 4 vmrghw <2,6,3,7>, <0,6,1,7> - 4201378655U, // <2,0,6,7>: Cost 4 vsldoi8 <6,7,2,0>, <6,7,2,0> - 2163688093U, // <2,0,6,u>: Cost 2 vmrghw <2,6,3,7>, LHS - 3371573248U, // <2,0,7,0>: Cost 4 vmrglw <2,6,2,7>, <0,0,0,0> - 3237822566U, // <2,0,7,1>: Cost 3 vmrghw <2,7,0,1>, LHS - 4204033187U, // <2,0,7,2>: Cost 4 vsldoi8 <7,2,2,0>, <7,2,2,0> - 4204696820U, // <2,0,7,3>: Cost 4 vsldoi8 <7,3,2,0>, <7,3,2,0> - 4209341798U, // <2,0,7,4>: Cost 4 vsldoi8 , <7,4,5,6> - 3356317308U, // <2,0,7,5>: Cost 4 vmrglw <0,1,2,7>, <7,u,0,5> - 4206687719U, // <2,0,7,6>: Cost 4 vsldoi8 <7,6,2,0>, <7,6,2,0> - 4209342060U, // <2,0,7,7>: Cost 4 vsldoi8 , <7,7,7,7> - 3237823133U, // <2,0,7,u>: Cost 3 vmrghw <2,7,0,1>, LHS - 2282577920U, // <2,0,u,0>: Cost 2 vmrglw LHS, <0,0,0,0> - 2282579622U, // <2,0,u,1>: Cost 2 vmrglw LHS, <2,3,0,1> - 3234661021U, // <2,0,u,2>: Cost 2 vsldoi12 <2,2,2,2>, LHS - 4045842741U, // <2,0,u,3>: Cost 3 vsldoi4 <3,2,0,u>, <3,2,0,u> - 3356321449U, // <2,0,u,4>: Cost 3 vmrglw LHS, <2,3,0,4> - 4069732450U, // <2,0,u,5>: Cost 3 vsldoi4 <7,2,0,u>, <5,6,7,0> - 3235168758U, // <2,0,u,6>: Cost 3 vmrghw <2,3,0,1>, <0,6,1,7> - 4069733529U, // <2,0,u,7>: Cost 3 vsldoi4 <7,2,0,u>, <7,2,0,u> - 2282579629U, // <2,0,u,u>: Cost 2 vmrglw LHS, <2,3,0,u> - 4027932843U, // <2,1,0,0>: Cost 4 vsldoi4 <0,2,1,0>, <0,2,1,0> - 3227288292U, // <2,1,0,1>: Cost 3 vsldoi12 <1,0,1,2>, <1,0,1,2> - 3404032798U, // <2,1,0,2>: Cost 3 vmrglw , <3,u,1,2> - 3239232244U, // <2,1,0,3>: Cost 4 vsldoi12 <3,0,1,2>, <1,0,3,0> - 4027936054U, // <2,1,0,4>: Cost 4 vsldoi4 <0,2,1,0>, RHS - 3233424498U, // <2,1,0,5>: Cost 4 vmrghw <2,0,3,4>, <1,5,0,4> - 4196737521U, // <2,1,0,6>: Cost 4 vsldoi8 <6,0,2,1>, <0,6,1,2> - 3374170614U, // <2,1,0,7>: Cost 5 vmrglw <3,1,2,0>, <0,6,1,7> - 3227804451U, // <2,1,0,u>: Cost 3 vsldoi12 <1,0,u,2>, <1,0,u,2> - 4166877932U, // <2,1,1,0>: Cost 3 vsldoi8 <1,0,2,1>, <1,0,2,1> - 3234661172U, // <2,1,1,1>: Cost 3 vsldoi12 <2,2,2,2>, <1,1,1,1> - 4172186518U, // <2,1,1,2>: Cost 3 vsldoi8 <1,u,2,1>, <1,2,3,0> - 3362235271U, // <2,1,1,3>: Cost 4 vmrglw <1,1,2,1>, <1,2,1,3> - 4027944246U, // <2,1,1,4>: Cost 4 vsldoi4 <0,2,1,1>, RHS - 3228246873U, // <2,1,1,5>: Cost 4 vsldoi12 <1,1,5,2>, <1,1,5,2> - 3234096371U, // <2,1,1,6>: Cost 4 vmrghw <2,1,3,5>, <1,6,5,7> - 4171523363U, // <2,1,1,7>: Cost 4 vsldoi8 <1,7,2,1>, <1,7,2,1> - 4172186996U, // <2,1,1,u>: Cost 3 vsldoi8 <1,u,2,1>, <1,u,2,1> - 4027949229U, // <2,1,2,0>: Cost 3 vsldoi4 <0,2,1,2>, <0,2,1,2> - 3234661172U, // <2,1,2,1>: Cost 3 vmrghw <2,2,2,2>, <1,1,1,1> - 4027950696U, // <2,1,2,2>: Cost 3 vsldoi4 <0,2,1,2>, <2,2,2,2> - 3228763032U, // <2,1,2,3>: Cost 3 vsldoi12 <1,2,3,2>, <1,2,3,2> - 4027952438U, // <2,1,2,4>: Cost 3 vsldoi4 <0,2,1,2>, RHS - 3368878418U, // <2,1,2,5>: Cost 3 vmrglw <2,2,2,2>, <0,4,1,5> - 4172187560U, // <2,1,2,6>: Cost 4 vsldoi8 <1,u,2,1>, <2,6,1,7> - 3263120314U, // <2,1,2,7>: Cost 3 vsldoi12 <7,0,1,2>, <1,2,7,0> - 4027954990U, // <2,1,2,u>: Cost 3 vsldoi4 <0,2,1,2>, LHS - 3356278793U, // <2,1,3,0>: Cost 3 vmrglw LHS, <0,0,1,0> - 2282536970U, // <2,1,3,1>: Cost 2 vmrglw LHS, <0,0,1,1> - 2287184022U, // <2,1,3,2>: Cost 2 vmrglw LHS, <3,0,1,2> - 3360923822U, // <2,1,3,3>: Cost 3 vmrglw LHS, <0,2,1,3> - 4027960630U, // <2,1,3,4>: Cost 3 vsldoi4 <0,2,1,3>, RHS - 2282537298U, // <2,1,3,5>: Cost 2 vmrglw LHS, <0,4,1,5> - 3360923825U, // <2,1,3,6>: Cost 3 vmrglw LHS, <0,2,1,6> - 3360924879U, // <2,1,3,7>: Cost 3 vmrglw LHS, <1,6,1,7> - 2282536977U, // <2,1,3,u>: Cost 2 vmrglw LHS, <0,0,1,u> - 4027965615U, // <2,1,4,0>: Cost 4 vsldoi4 <0,2,1,4>, <0,2,1,4> - 3234661419U, // <2,1,4,1>: Cost 4 vsldoi12 <2,2,2,2>, <1,4,1,5> - 3404065566U, // <2,1,4,2>: Cost 3 vmrglw , <3,u,1,2> - 4027967638U, // <2,1,4,3>: Cost 5 vsldoi4 <0,2,1,4>, <3,0,1,2> - 4027968822U, // <2,1,4,4>: Cost 4 vsldoi4 <0,2,1,4>, RHS - 4172188982U, // <2,1,4,5>: Cost 3 vsldoi8 <1,u,2,1>, RHS - 4202048889U, // <2,1,4,6>: Cost 4 vsldoi8 <6,u,2,1>, <4,6,5,2> - 3368895695U, // <2,1,4,7>: Cost 5 vmrglw <2,2,2,4>, <1,6,1,7> - 4172189225U, // <2,1,4,u>: Cost 3 vsldoi8 <1,u,2,1>, RHS - 4027973808U, // <2,1,5,0>: Cost 4 vsldoi4 <0,2,1,5>, <0,2,1,5> - 3364257802U, // <2,1,5,1>: Cost 4 vmrglw <1,4,2,5>, <0,0,1,1> - 4027975573U, // <2,1,5,2>: Cost 4 vsldoi4 <0,2,1,5>, <2,5,u,6> - 4027976194U, // <2,1,5,3>: Cost 4 vsldoi4 <0,2,1,5>, <3,4,5,6> - 4027977014U, // <2,1,5,4>: Cost 4 vsldoi4 <0,2,1,5>, RHS - 3364258130U, // <2,1,5,5>: Cost 4 vmrglw <1,4,2,5>, <0,4,1,5> - 3236766963U, // <2,1,5,6>: Cost 4 vmrghw <2,5,3,7>, <1,6,5,7> - 3263120557U, // <2,1,5,7>: Cost 4 vsldoi12 <7,0,1,2>, <1,5,7,0> - 4027979566U, // <2,1,5,u>: Cost 4 vsldoi4 <0,2,1,5>, LHS - 4027982001U, // <2,1,6,0>: Cost 3 vsldoi4 <0,2,1,6>, <0,2,1,6> - 3237430068U, // <2,1,6,1>: Cost 3 vmrghw <2,6,3,7>, <1,1,1,1> - 4027983802U, // <2,1,6,2>: Cost 3 vsldoi4 <0,2,1,6>, <2,6,3,7> - 4027984022U, // <2,1,6,3>: Cost 4 vsldoi4 <0,2,1,6>, <3,0,1,2> - 4027985206U, // <2,1,6,4>: Cost 3 vsldoi4 <0,2,1,6>, RHS - 3364929874U, // <2,1,6,5>: Cost 4 vmrglw <1,5,2,6>, <0,4,1,5> - 4027986744U, // <2,1,6,6>: Cost 4 vsldoi4 <0,2,1,6>, <6,6,6,6> - 4201386848U, // <2,1,6,7>: Cost 4 vsldoi8 <6,7,2,1>, <6,7,2,1> - 4027987758U, // <2,1,6,u>: Cost 3 vsldoi4 <0,2,1,6>, LHS - 4202050554U, // <2,1,7,0>: Cost 4 vsldoi8 <6,u,2,1>, <7,0,1,2> - 3371573258U, // <2,1,7,1>: Cost 4 vmrglw <2,6,2,7>, <0,0,1,1> - 3404093058U, // <2,1,7,2>: Cost 3 vmrglw , <7,u,1,2> - 4202050842U, // <2,1,7,3>: Cost 4 vsldoi8 <6,u,2,1>, <7,3,6,2> - 4202050918U, // <2,1,7,4>: Cost 4 vsldoi8 <6,u,2,1>, <7,4,5,6> - 3371573586U, // <2,1,7,5>: Cost 4 vmrglw <2,6,2,7>, <0,4,1,5> - 4202051054U, // <2,1,7,6>: Cost 4 vsldoi8 <6,u,2,1>, <7,6,2,7> - 4202051140U, // <2,1,7,7>: Cost 4 vsldoi8 <6,u,2,1>, <7,7,3,3> - 3404093058U, // <2,1,7,u>: Cost 3 vmrglw , <7,u,1,2> - 3356319753U, // <2,1,u,0>: Cost 3 vmrglw LHS, <0,0,1,0> - 2282577930U, // <2,1,u,1>: Cost 2 vmrglw LHS, <0,0,1,1> - 2282580118U, // <2,1,u,2>: Cost 2 vmrglw LHS, <3,0,1,2> - 3356319918U, // <2,1,u,3>: Cost 3 vmrglw LHS, <0,2,1,3> - 3356319757U, // <2,1,u,4>: Cost 3 vmrglw LHS, <0,0,1,4> - 2282578258U, // <2,1,u,5>: Cost 2 vmrglw LHS, <0,4,1,5> - 3356319921U, // <2,1,u,6>: Cost 3 vmrglw LHS, <0,2,1,6> - 3360965839U, // <2,1,u,7>: Cost 3 vmrglw LHS, <1,6,1,7> - 2282577937U, // <2,1,u,u>: Cost 2 vmrglw LHS, <0,0,1,u> - 3233392077U, // <2,2,0,0>: Cost 3 vmrghw <2,0,3,0>, <2,0,3,0> - 3100442726U, // <2,2,0,1>: Cost 2 vsldoi8 <2,2,2,2>, LHS - 4174184621U, // <2,2,0,2>: Cost 3 vsldoi8 <2,2,2,2>, <0,2,1,2> - 3233400486U, // <2,2,0,3>: Cost 3 vmrghw <2,0,3,1>, <2,3,0,1> - 4174184786U, // <2,2,0,4>: Cost 3 vsldoi8 <2,2,2,2>, <0,4,1,5> - 3233548136U, // <2,2,0,5>: Cost 4 vmrghw <2,0,5,1>, <2,5,3,6> - 3233621946U, // <2,2,0,6>: Cost 3 vmrghw <2,0,6,1>, <2,6,3,7> - 4069815459U, // <2,2,0,7>: Cost 4 vsldoi4 <7,2,2,0>, <7,2,2,0> - 3100443293U, // <2,2,0,u>: Cost 2 vsldoi8 <2,2,2,2>, LHS - 3227289092U, // <2,2,1,0>: Cost 4 vsldoi12 <1,0,1,2>, <2,1,0,1> - 3366880628U, // <2,2,1,1>: Cost 3 vmrglw <1,u,2,1>, <1,u,2,1> - 4174185366U, // <2,2,1,2>: Cost 3 vsldoi8 <2,2,2,2>, <1,2,3,0> - 3366879334U, // <2,2,1,3>: Cost 3 vmrglw <1,u,2,1>, LHS - 4174185515U, // <2,2,1,4>: Cost 4 vsldoi8 <2,2,2,2>, <1,4,1,5> - 4170204290U, // <2,2,1,5>: Cost 4 vsldoi8 <1,5,2,2>, <1,5,2,2> - 3234064314U, // <2,2,1,6>: Cost 4 vmrghw <2,1,3,1>, <2,6,3,7> - 3372853169U, // <2,2,1,7>: Cost 4 vmrglw <2,u,2,1>, <2,6,2,7> - 3366879339U, // <2,2,1,u>: Cost 3 vmrglw <1,u,2,1>, LHS - 2966224998U, // <2,2,2,0>: Cost 2 vsldoi4 <2,2,2,2>, LHS - 3368879557U, // <2,2,2,1>: Cost 3 vmrglw <2,2,2,2>, <2,0,2,1> - 1611448422U, // <2,2,2,2>: Cost 1 vspltisw2 LHS - 2295136358U, // <2,2,2,3>: Cost 2 vmrglw <2,2,2,2>, LHS - 2966228278U, // <2,2,2,4>: Cost 2 vsldoi4 <2,2,2,2>, RHS - 3368879885U, // <2,2,2,5>: Cost 3 vmrglw <2,2,2,2>, <2,4,2,5> - 3234662330U, // <2,2,2,6>: Cost 3 vmrghw <2,2,2,2>, <2,6,3,7> - 4069831845U, // <2,2,2,7>: Cost 3 vsldoi4 <7,2,2,2>, <7,2,2,2> - 1611448422U, // <2,2,2,u>: Cost 1 vspltisw2 LHS - 4174186646U, // <2,2,3,0>: Cost 3 vsldoi8 <2,2,2,2>, <3,0,1,2> - 3235251888U, // <2,2,3,1>: Cost 3 vsldoi12 <2,3,1,2>, <2,3,1,2> - 2287183464U, // <2,2,3,2>: Cost 2 vmrglw LHS, <2,2,2,2> - 1208795238U, // <2,2,3,3>: Cost 1 vmrglw LHS, LHS - 4174187010U, // <2,2,3,4>: Cost 3 vsldoi8 <2,2,2,2>, <3,4,5,6> - 3404055604U, // <2,2,3,5>: Cost 3 vmrglw LHS, <1,4,2,5> - 3360925373U, // <2,2,3,6>: Cost 3 vmrglw LHS, <2,3,2,6> - 4069840038U, // <2,2,3,7>: Cost 3 vsldoi4 <7,2,2,3>, <7,2,2,3> - 1208795243U, // <2,2,3,u>: Cost 1 vmrglw LHS, LHS - 4039983206U, // <2,2,4,0>: Cost 3 vsldoi4 <2,2,2,4>, LHS - 4174187466U, // <2,2,4,1>: Cost 4 vsldoi8 <2,2,2,2>, <4,1,2,3> - 3234662157U, // <2,2,4,2>: Cost 3 vsldoi12 <2,2,2,2>, <2,4,2,5> - 3368894566U, // <2,2,4,3>: Cost 3 vmrglw <2,2,2,4>, LHS - 3368896106U, // <2,2,4,4>: Cost 3 vmrglw <2,2,2,4>, <2,2,2,4> - 3100446006U, // <2,2,4,5>: Cost 2 vsldoi8 <2,2,2,2>, RHS - 3236308922U, // <2,2,4,6>: Cost 3 vmrghw <2,4,6,5>, <2,6,3,7> - 3368896433U, // <2,2,4,7>: Cost 4 vmrglw <2,2,2,4>, <2,6,2,7> - 3100446249U, // <2,2,4,u>: Cost 2 vsldoi8 <2,2,2,2>, RHS - 4174188104U, // <2,2,5,0>: Cost 4 vsldoi8 <2,2,2,2>, <5,0,1,2> - 3364258540U, // <2,2,5,1>: Cost 4 vmrglw <1,4,2,5>, <1,0,2,1> - 3370231400U, // <2,2,5,2>: Cost 3 vmrglw <2,4,2,5>, <2,2,2,2> - 3364257894U, // <2,2,5,3>: Cost 3 vmrglw <1,4,2,5>, LHS - 4174188468U, // <2,2,5,4>: Cost 4 vsldoi8 <2,2,2,2>, <5,4,5,6> - 3364258868U, // <2,2,5,5>: Cost 3 vmrglw <1,4,2,5>, <1,4,2,5> - 4174188642U, // <2,2,5,6>: Cost 3 vsldoi8 <2,2,2,2>, <5,6,7,0> - 3370231729U, // <2,2,5,7>: Cost 4 vmrglw <2,4,2,5>, <2,6,2,7> - 3364257899U, // <2,2,5,u>: Cost 3 vmrglw <1,4,2,5>, LHS - 3237430761U, // <2,2,6,0>: Cost 3 vmrghw <2,6,3,7>, <2,0,6,1> - 3237430815U, // <2,2,6,1>: Cost 4 vmrghw <2,6,3,7>, <2,1,3,1> - 3234662321U, // <2,2,6,2>: Cost 3 vsldoi12 <2,2,2,2>, <2,6,2,7> - 3234662330U, // <2,2,6,3>: Cost 3 vsldoi12 <2,2,2,2>, <2,6,3,7> - 3237431089U, // <2,2,6,4>: Cost 3 vmrghw <2,6,3,7>, <2,4,6,5> - 3237431144U, // <2,2,6,5>: Cost 4 vmrghw <2,6,3,7>, <2,5,3,6> - 2163689402U, // <2,2,6,6>: Cost 2 vmrghw <2,6,3,7>, <2,6,3,7> - 4201395041U, // <2,2,6,7>: Cost 3 vsldoi8 <6,7,2,2>, <6,7,2,2> - 2163689402U, // <2,2,6,u>: Cost 2 vmrghw <2,6,3,7>, <2,6,3,7> - 3263121386U, // <2,2,7,0>: Cost 3 vsldoi12 <7,0,1,2>, <2,7,0,1> - 3371574725U, // <2,2,7,1>: Cost 4 vmrglw <2,6,2,7>, <2,0,2,1> - 3371574888U, // <2,2,7,2>: Cost 3 vmrglw <2,6,2,7>, <2,2,2,2> - 3371573350U, // <2,2,7,3>: Cost 3 vmrglw <2,6,2,7>, LHS - 4174189926U, // <2,2,7,4>: Cost 3 vsldoi8 <2,2,2,2>, <7,4,5,6> - 3371575053U, // <2,2,7,5>: Cost 4 vmrglw <2,6,2,7>, <2,4,2,5> - 3237824433U, // <2,2,7,6>: Cost 4 vmrghw <2,7,0,1>, <2,6,2,7> - 3371575217U, // <2,2,7,7>: Cost 3 vmrglw <2,6,2,7>, <2,6,2,7> - 3371573355U, // <2,2,7,u>: Cost 3 vmrglw <2,6,2,7>, LHS - 2966224998U, // <2,2,u,0>: Cost 2 vsldoi4 <2,2,2,2>, LHS - 3100448558U, // <2,2,u,1>: Cost 2 vsldoi8 <2,2,2,2>, LHS - 1611448422U, // <2,2,u,2>: Cost 1 vspltisw2 LHS - 1208836198U, // <2,2,u,3>: Cost 1 vmrglw LHS, LHS - 2966228278U, // <2,2,u,4>: Cost 2 vsldoi4 <2,2,2,2>, RHS - 3100448922U, // <2,2,u,5>: Cost 2 vsldoi8 <2,2,2,2>, RHS - 2163689402U, // <2,2,u,6>: Cost 2 vmrghw <2,6,3,7>, <2,6,3,7> - 4069881003U, // <2,2,u,7>: Cost 3 vsldoi4 <7,2,2,u>, <7,2,2,u> - 1208836203U, // <2,2,u,u>: Cost 1 vmrglw LHS, LHS - 3087843328U, // <2,3,0,0>: Cost 2 vsldoi8 LHS, <0,0,0,0> - 2014101606U, // <2,3,0,1>: Cost 1 vsldoi8 LHS, LHS - 4166230189U, // <2,3,0,2>: Cost 3 vsldoi8 LHS, <0,2,1,2> - 4166230268U, // <2,3,0,3>: Cost 3 vsldoi8 LHS, <0,3,1,0> - 3087843666U, // <2,3,0,4>: Cost 2 vsldoi8 LHS, <0,4,1,5> - 4209361362U, // <2,3,0,5>: Cost 3 vsldoi8 LHS, <0,5,6,7> - 4209361398U, // <2,3,0,6>: Cost 3 vsldoi8 LHS, <0,6,1,7> - 4069889196U, // <2,3,0,7>: Cost 3 vsldoi4 <7,2,3,0>, <7,2,3,0> - 2014102173U, // <2,3,0,u>: Cost 1 vsldoi8 LHS, LHS - 4166230756U, // <2,3,1,0>: Cost 3 vsldoi8 LHS, <1,0,1,2> - 3087844148U, // <2,3,1,1>: Cost 2 vsldoi8 LHS, <1,1,1,1> - 3087844246U, // <2,3,1,2>: Cost 2 vsldoi8 LHS, <1,2,3,0> - 4166230989U, // <2,3,1,3>: Cost 4 vsldoi8 LHS, <1,3,0,1> - 4166231120U, // <2,3,1,4>: Cost 3 vsldoi8 LHS, <1,4,5,6> - 4166231151U, // <2,3,1,5>: Cost 3 vsldoi8 LHS, <1,5,0,1> - 4166231247U, // <2,3,1,6>: Cost 3 vsldoi8 LHS, <1,6,1,7> - 3366881210U, // <2,3,1,7>: Cost 4 vmrglw <1,u,2,1>, <2,6,3,7> - 3092489596U, // <2,3,1,u>: Cost 2 vsldoi8 LHS, <1,u,3,0> - 4166231501U, // <2,3,2,0>: Cost 3 vsldoi8 LHS, <2,0,3,0> - 4161586719U, // <2,3,2,1>: Cost 3 vsldoi8 LHS, <2,1,3,1> - 3087844968U, // <2,3,2,2>: Cost 2 vsldoi8 LHS, <2,2,2,2> - 3087845030U, // <2,3,2,3>: Cost 2 vsldoi8 LHS, <2,3,0,1> - 4166231830U, // <2,3,2,4>: Cost 3 vsldoi8 LHS, <2,4,3,5> - 4166231912U, // <2,3,2,5>: Cost 3 vsldoi8 LHS, <2,5,3,6> - 3087845306U, // <2,3,2,6>: Cost 2 vsldoi8 LHS, <2,6,3,7> - 3368880058U, // <2,3,2,7>: Cost 3 vmrglw <2,2,2,2>, <2,6,3,7> - 3087845464U, // <2,3,2,u>: Cost 2 vsldoi8 LHS, <2,u,3,3> - 2287182742U, // <2,3,3,0>: Cost 2 vmrglw LHS, <1,2,3,0> - 3356280351U, // <2,3,3,1>: Cost 3 vmrglw LHS, <2,1,3,1> - 2966308466U, // <2,3,3,2>: Cost 2 vsldoi4 <2,2,3,3>, <2,2,3,3> - 2282538610U, // <2,3,3,3>: Cost 2 vmrglw LHS, <2,2,3,3> - 2287182746U, // <2,3,3,4>: Cost 2 vmrglw LHS, <1,2,3,4> - 3356280355U, // <2,3,3,5>: Cost 3 vmrglw LHS, <2,1,3,5> - 3360929918U, // <2,3,3,6>: Cost 3 vmrglw LHS, - 2287183802U, // <2,3,3,7>: Cost 2 vmrglw LHS, <2,6,3,7> - 2282538615U, // <2,3,3,u>: Cost 2 vmrglw LHS, <2,2,3,u> - 2960343142U, // <2,3,4,0>: Cost 2 vsldoi4 <1,2,3,4>, LHS - 2960343962U, // <2,3,4,1>: Cost 2 vsldoi4 <1,2,3,4>, <1,2,3,4> - 4034086504U, // <2,3,4,2>: Cost 3 vsldoi4 <1,2,3,4>, <2,2,2,2> - 4034087062U, // <2,3,4,3>: Cost 3 vsldoi4 <1,2,3,4>, <3,0,1,2> - 2960346422U, // <2,3,4,4>: Cost 2 vsldoi4 <1,2,3,4>, RHS - 2014104886U, // <2,3,4,5>: Cost 1 vsldoi8 LHS, RHS - 4209364345U, // <2,3,4,6>: Cost 3 vsldoi8 LHS, <4,6,5,2> - 4069921968U, // <2,3,4,7>: Cost 3 vsldoi4 <7,2,3,4>, <7,2,3,4> - 2014105129U, // <2,3,4,u>: Cost 1 vsldoi8 LHS, RHS - 4166233672U, // <2,3,5,0>: Cost 3 vsldoi8 LHS, <5,0,1,2> - 4209364623U, // <2,3,5,1>: Cost 3 vsldoi8 LHS, <5,1,0,1> - 4209364715U, // <2,3,5,2>: Cost 3 vsldoi8 LHS, <5,2,1,3> - 4166233905U, // <2,3,5,3>: Cost 4 vsldoi8 LHS, <5,3,0,1> - 4166234036U, // <2,3,5,4>: Cost 3 vsldoi8 LHS, <5,4,5,6> - 3135623172U, // <2,3,5,5>: Cost 2 vsldoi8 LHS, <5,5,5,5> - 3135623266U, // <2,3,5,6>: Cost 2 vsldoi8 LHS, <5,6,7,0> - 3364259770U, // <2,3,5,7>: Cost 4 vmrglw <1,4,2,5>, <2,6,3,7> - 3135623428U, // <2,3,5,u>: Cost 2 vsldoi8 LHS, <5,u,7,0> - 3237431446U, // <2,3,6,0>: Cost 3 vmrghw <2,6,3,7>, <3,0,1,2> - 4209365415U, // <2,3,6,1>: Cost 3 vsldoi8 LHS, <6,1,7,1> - 3135623674U, // <2,3,6,2>: Cost 2 vsldoi8 LHS, <6,2,7,3> - 3237431708U, // <2,3,6,3>: Cost 3 vmrghw <2,6,3,7>, <3,3,3,3> - 3237431810U, // <2,3,6,4>: Cost 3 vmrghw <2,6,3,7>, <3,4,5,6> - 4209365739U, // <2,3,6,5>: Cost 3 vsldoi8 LHS, <6,5,7,1> - 3135623992U, // <2,3,6,6>: Cost 2 vsldoi8 LHS, <6,6,6,6> - 3135624014U, // <2,3,6,7>: Cost 2 vsldoi8 LHS, <6,7,0,1> - 3135624095U, // <2,3,6,u>: Cost 2 vsldoi8 LHS, <6,u,0,1> - 3135624186U, // <2,3,7,0>: Cost 2 vsldoi8 LHS, <7,0,1,2> - 4203394133U, // <2,3,7,1>: Cost 3 vsldoi8 <7,1,2,3>, <7,1,2,3> - 4204057766U, // <2,3,7,2>: Cost 3 vsldoi8 <7,2,2,3>, <7,2,2,3> - 4209366243U, // <2,3,7,3>: Cost 3 vsldoi8 LHS, <7,3,0,1> - 3135624550U, // <2,3,7,4>: Cost 2 vsldoi8 LHS, <7,4,5,6> - 4209366454U, // <2,3,7,5>: Cost 3 vsldoi8 LHS, <7,5,5,5> - 4209366492U, // <2,3,7,6>: Cost 3 vsldoi8 LHS, <7,6,0,7> - 3135624812U, // <2,3,7,7>: Cost 2 vsldoi8 LHS, <7,7,7,7> - 3135624834U, // <2,3,7,u>: Cost 2 vsldoi8 LHS, <7,u,1,2> - 2282578838U, // <2,3,u,0>: Cost 2 vmrglw LHS, <1,2,3,0> - 2014107438U, // <2,3,u,1>: Cost 1 vsldoi8 LHS, LHS - 3092494213U, // <2,3,u,2>: Cost 2 vsldoi8 LHS, - 2282579570U, // <2,3,u,3>: Cost 2 vmrglw LHS, <2,2,3,3> - 2282578842U, // <2,3,u,4>: Cost 2 vmrglw LHS, <1,2,3,4> - 2014107802U, // <2,3,u,5>: Cost 1 vsldoi8 LHS, RHS - 3092494544U, // <2,3,u,6>: Cost 2 vsldoi8 LHS, - 2282579898U, // <2,3,u,7>: Cost 2 vmrglw LHS, <2,6,3,7> - 2014108005U, // <2,3,u,u>: Cost 1 vsldoi8 LHS, LHS - 4174200832U, // <2,4,0,0>: Cost 4 vsldoi8 <2,2,2,4>, <0,0,0,0> - 4174200934U, // <2,4,0,1>: Cost 3 vsldoi8 <2,2,2,4>, LHS - 4173537453U, // <2,4,0,2>: Cost 4 vsldoi8 <2,1,2,4>, <0,2,1,2> - 4209369348U, // <2,4,0,3>: Cost 4 vsldoi8 , <0,3,1,u> - 4174201170U, // <2,4,0,4>: Cost 4 vsldoi8 <2,2,2,4>, <0,4,1,5> - 3233393974U, // <2,4,0,5>: Cost 3 vmrghw <2,0,3,0>, RHS - 3249482651U, // <2,4,0,6>: Cost 4 vsldoi12 <4,6,5,2>, <4,0,6,1> - 3263122340U, // <2,4,0,7>: Cost 4 vsldoi12 <7,0,1,2>, <4,0,7,1> - 3233394217U, // <2,4,0,u>: Cost 3 vmrghw <2,0,3,0>, RHS - 3245206455U, // <2,4,1,0>: Cost 4 vsldoi12 <4,0,1,2>, <4,1,0,2> - 3234098146U, // <2,4,1,1>: Cost 4 vmrghw <2,1,3,5>, <4,1,5,0> - 4168893334U, // <2,4,1,2>: Cost 4 vsldoi8 <1,3,2,4>, <1,2,3,0> - 4168893410U, // <2,4,1,3>: Cost 4 vsldoi8 <1,3,2,4>, <1,3,2,4> - 3234098384U, // <2,4,1,4>: Cost 4 vmrghw <2,1,3,5>, <4,4,4,4> - 3234065718U, // <2,4,1,5>: Cost 3 vmrghw <2,1,3,1>, RHS - 4161594584U, // <2,4,1,6>: Cost 4 vsldoi8 <0,1,2,4>, <1,6,2,7> - 4171547942U, // <2,4,1,7>: Cost 4 vsldoi8 <1,7,2,4>, <1,7,2,4> - 3234065961U, // <2,4,1,u>: Cost 3 vmrghw <2,1,3,1>, RHS - 3234663314U, // <2,4,2,0>: Cost 3 vmrghw <2,2,2,2>, <4,0,5,1> - 4173538841U, // <2,4,2,1>: Cost 4 vsldoi8 <2,1,2,4>, <2,1,2,4> - 4174202474U, // <2,4,2,2>: Cost 3 vsldoi8 <2,2,2,4>, <2,2,2,4> - 3368880468U, // <2,4,2,3>: Cost 4 vmrglw <2,2,2,2>, <3,2,4,3> - 3234663632U, // <2,4,2,4>: Cost 3 vmrghw <2,2,2,2>, <4,4,4,4> - 2160921910U, // <2,4,2,5>: Cost 2 vmrghw <2,2,2,2>, RHS - 4174202801U, // <2,4,2,6>: Cost 4 vsldoi8 <2,2,2,4>, <2,6,2,7> - 3368880796U, // <2,4,2,7>: Cost 4 vmrglw <2,2,2,2>, <3,6,4,7> - 2160922153U, // <2,4,2,u>: Cost 2 vmrghw <2,2,2,2>, RHS - 4046094438U, // <2,4,3,0>: Cost 3 vsldoi4 <3,2,4,3>, LHS - 3360923685U, // <2,4,3,1>: Cost 3 vmrglw LHS, <0,0,4,1> - 3235499062U, // <2,4,3,2>: Cost 3 vmrghw <2,3,4,5>, <4,2,5,3> - 4046096724U, // <2,4,3,3>: Cost 3 vsldoi4 <3,2,4,3>, <3,2,4,3> - 2330315984U, // <2,4,3,4>: Cost 2 vmrglw LHS, <4,4,4,4> - 2287183566U, // <2,4,3,5>: Cost 2 vmrglw LHS, <2,3,4,5> - 3235499390U, // <2,4,3,6>: Cost 3 vmrghw <2,3,4,5>, <4,6,5,7> - 4069987512U, // <2,4,3,7>: Cost 3 vsldoi4 <7,2,4,3>, <7,2,4,3> - 2287183569U, // <2,4,3,u>: Cost 2 vmrglw LHS, <2,3,4,u> - 4040130662U, // <2,4,4,0>: Cost 4 vsldoi4 <2,2,4,4>, LHS - 4185484235U, // <2,4,4,1>: Cost 4 vsldoi8 <4,1,2,4>, <4,1,2,4> - 4040132220U, // <2,4,4,2>: Cost 4 vsldoi4 <2,2,4,4>, <2,2,4,4> - 3368896123U, // <2,4,4,3>: Cost 4 vmrglw <2,2,2,4>, <2,2,4,3> - 3263122640U, // <2,4,4,4>: Cost 3 vsldoi12 <7,0,1,2>, <4,4,4,4> - 4174204214U, // <2,4,4,5>: Cost 3 vsldoi8 <2,2,2,4>, RHS - 3236089214U, // <2,4,4,6>: Cost 4 vmrghw <2,4,3,5>, <4,6,5,7> - 3263122668U, // <2,4,4,7>: Cost 4 vsldoi12 <7,0,1,2>, <4,4,7,5> - 4174204457U, // <2,4,4,u>: Cost 3 vsldoi8 <2,2,2,4>, RHS - 4040138854U, // <2,4,5,0>: Cost 3 vsldoi4 <2,2,4,5>, LHS - 4034167716U, // <2,4,5,1>: Cost 3 vsldoi4 <1,2,4,5>, <1,2,4,5> - 4040140413U, // <2,4,5,2>: Cost 3 vsldoi4 <2,2,4,5>, <2,2,4,5> - 4075972821U, // <2,4,5,3>: Cost 3 vsldoi4 , <3,0,u,2> - 4040142134U, // <2,4,5,4>: Cost 3 vsldoi4 <2,2,4,5>, RHS - 3236760886U, // <2,4,5,5>: Cost 3 vmrghw <2,5,3,6>, RHS - 3234663734U, // <2,4,5,6>: Cost 2 vsldoi12 <2,2,2,2>, RHS - 3263122744U, // <2,4,5,7>: Cost 4 vsldoi12 <7,0,1,2>, <4,5,7,0> - 3234663752U, // <2,4,5,u>: Cost 2 vsldoi12 <2,2,2,2>, RHS - 3237432210U, // <2,4,6,0>: Cost 3 vmrghw <2,6,3,7>, <4,0,5,1> - 3237432266U, // <2,4,6,1>: Cost 4 vmrghw <2,6,3,7>, <4,1,2,3> - 3237432377U, // <2,4,6,2>: Cost 3 vmrghw <2,6,3,7>, <4,2,5,6> - 3237432459U, // <2,4,6,3>: Cost 4 vmrghw <2,6,3,7>, <4,3,5,7> - 3237432528U, // <2,4,6,4>: Cost 3 vmrghw <2,6,3,7>, <4,4,4,4> - 2163690806U, // <2,4,6,5>: Cost 2 vmrghw <2,6,3,7>, RHS - 3237432702U, // <2,4,6,6>: Cost 4 vmrghw <2,6,3,7>, <4,6,5,7> - 4201411427U, // <2,4,6,7>: Cost 4 vsldoi8 <6,7,2,4>, <6,7,2,4> - 2163691049U, // <2,4,6,u>: Cost 2 vmrghw <2,6,3,7>, RHS - 4209374202U, // <2,4,7,0>: Cost 4 vsldoi8 , <7,0,1,2> - 3249851814U, // <2,4,7,1>: Cost 4 vsldoi12 <4,7,1,2>, <4,7,1,2> - 4204065959U, // <2,4,7,2>: Cost 4 vsldoi8 <7,2,2,4>, <7,2,2,4> - 4204729592U, // <2,4,7,3>: Cost 4 vsldoi8 <7,3,2,4>, <7,3,2,4> - 3401436368U, // <2,4,7,4>: Cost 4 vmrglw <7,6,2,7>, <4,4,4,4> - 3263122888U, // <2,4,7,5>: Cost 3 vsldoi12 <7,0,1,2>, <4,7,5,0> - 4206720491U, // <2,4,7,6>: Cost 4 vsldoi8 <7,6,2,4>, <7,6,2,4> - 3263122906U, // <2,4,7,7>: Cost 4 vsldoi12 <7,0,1,2>, <4,7,7,0> - 3263122915U, // <2,4,7,u>: Cost 3 vsldoi12 <7,0,1,2>, <4,7,u,0> - 4040163430U, // <2,4,u,0>: Cost 3 vsldoi4 <2,2,4,u>, LHS - 3356321968U, // <2,4,u,1>: Cost 3 vmrglw LHS, <3,0,4,1> - 4040164992U, // <2,4,u,2>: Cost 3 vsldoi4 <2,2,4,u>, <2,2,4,u> - 4046137689U, // <2,4,u,3>: Cost 3 vsldoi4 <3,2,4,u>, <3,2,4,u> - 2330356944U, // <2,4,u,4>: Cost 2 vmrglw LHS, <4,4,4,4> - 2282579662U, // <2,4,u,5>: Cost 2 vmrglw LHS, <2,3,4,5> - 3234663977U, // <2,4,u,6>: Cost 2 vsldoi12 <2,2,2,2>, RHS - 4070028477U, // <2,4,u,7>: Cost 3 vsldoi4 <7,2,4,u>, <7,2,4,u> - 2282579665U, // <2,4,u,u>: Cost 2 vmrglw LHS, <2,3,4,u> - 4169564160U, // <2,5,0,0>: Cost 4 vsldoi8 <1,4,2,5>, <0,0,0,0> - 4169564262U, // <2,5,0,1>: Cost 3 vsldoi8 <1,4,2,5>, LHS - 4163592365U, // <2,5,0,2>: Cost 4 vsldoi8 <0,4,2,5>, <0,2,1,2> - 3239235160U, // <2,5,0,3>: Cost 4 vsldoi12 <3,0,1,2>, <5,0,3,0> - 4163592539U, // <2,5,0,4>: Cost 4 vsldoi8 <0,4,2,5>, <0,4,2,5> - 3263123051U, // <2,5,0,5>: Cost 4 vsldoi12 <7,0,1,2>, <5,0,5,1> - 3263123060U, // <2,5,0,6>: Cost 4 vsldoi12 <7,0,1,2>, <5,0,6,1> - 3263123068U, // <2,5,0,7>: Cost 4 vsldoi12 <7,0,1,2>, <5,0,7,0> - 4169564829U, // <2,5,0,u>: Cost 3 vsldoi8 <1,4,2,5>, LHS - 4169564908U, // <2,5,1,0>: Cost 4 vsldoi8 <1,4,2,5>, <1,0,2,1> - 4169564980U, // <2,5,1,1>: Cost 4 vsldoi8 <1,4,2,5>, <1,1,1,1> - 4169565078U, // <2,5,1,2>: Cost 3 vsldoi8 <1,4,2,5>, <1,2,3,0> - 3384798262U, // <2,5,1,3>: Cost 4 vmrglw <4,u,2,1>, <4,2,5,3> - 4169565236U, // <2,5,1,4>: Cost 3 vsldoi8 <1,4,2,5>, <1,4,2,5> - 3234099204U, // <2,5,1,5>: Cost 4 vmrghw <2,1,3,5>, <5,5,5,5> - 3366879607U, // <2,5,1,6>: Cost 4 vmrglw <1,u,2,1>, <0,4,5,6> - 3263123149U, // <2,5,1,7>: Cost 4 vsldoi12 <7,0,1,2>, <5,1,7,0> - 4172219768U, // <2,5,1,u>: Cost 3 vsldoi8 <1,u,2,5>, <1,u,2,5> - 4052131942U, // <2,5,2,0>: Cost 3 vsldoi4 <4,2,5,2>, LHS - 3368881042U, // <2,5,2,1>: Cost 3 vmrglw <2,2,2,2>, <4,0,5,1> - 4175537768U, // <2,5,2,2>: Cost 3 vsldoi8 <2,4,2,5>, <2,2,2,2> - 4169565862U, // <2,5,2,3>: Cost 4 vsldoi8 <1,4,2,5>, <2,3,0,1> - 4175537933U, // <2,5,2,4>: Cost 3 vsldoi8 <2,4,2,5>, <2,4,2,5> - 3234664452U, // <2,5,2,5>: Cost 3 vmrghw <2,2,2,2>, <5,5,5,5> - 3368880642U, // <2,5,2,6>: Cost 3 vmrglw <2,2,2,2>, <3,4,5,6> - 3368879347U, // <2,5,2,7>: Cost 4 vmrglw <2,2,2,2>, <1,6,5,7> - 3368880644U, // <2,5,2,u>: Cost 3 vmrglw <2,2,2,2>, <3,4,5,u> - 3360926690U, // <2,5,3,0>: Cost 3 vmrglw LHS, <4,1,5,0> - 2330315666U, // <2,5,3,1>: Cost 2 vmrglw LHS, <4,0,5,1> - 4052141774U, // <2,5,3,2>: Cost 3 vsldoi4 <4,2,5,3>, <2,3,4,5> - 3360924587U, // <2,5,3,3>: Cost 3 vmrglw LHS, <1,2,5,3> - 3360926694U, // <2,5,3,4>: Cost 3 vmrglw LHS, <4,1,5,4> - 2330315994U, // <2,5,3,5>: Cost 2 vmrglw LHS, <4,4,5,5> - 2287184386U, // <2,5,3,6>: Cost 2 vmrglw LHS, <3,4,5,6> - 3360924915U, // <2,5,3,7>: Cost 3 vmrglw LHS, <1,6,5,7> - 2287184388U, // <2,5,3,u>: Cost 2 vmrglw LHS, <3,4,5,u> - 4052148326U, // <2,5,4,0>: Cost 4 vsldoi4 <4,2,5,4>, LHS - 4052149142U, // <2,5,4,1>: Cost 4 vsldoi4 <4,2,5,4>, <1,2,3,0> - 4169567283U, // <2,5,4,2>: Cost 4 vsldoi8 <1,4,2,5>, <4,2,5,0> - 3368895403U, // <2,5,4,3>: Cost 5 vmrglw <2,2,2,4>, <1,2,5,3> - 4052151351U, // <2,5,4,4>: Cost 4 vsldoi4 <4,2,5,4>, <4,2,5,4> - 4169567542U, // <2,5,4,5>: Cost 3 vsldoi8 <1,4,2,5>, RHS - 3363588610U, // <2,5,4,6>: Cost 4 vmrglw <1,3,2,4>, <3,4,5,6> - 3368895731U, // <2,5,4,7>: Cost 5 vmrglw <2,2,2,4>, <1,6,5,7> - 4169567785U, // <2,5,4,u>: Cost 3 vsldoi8 <1,4,2,5>, RHS - 4040212582U, // <2,5,5,0>: Cost 4 vsldoi4 <2,2,5,5>, LHS - 4040213398U, // <2,5,5,1>: Cost 4 vsldoi4 <2,2,5,5>, <1,2,3,0> - 4040214150U, // <2,5,5,2>: Cost 4 vsldoi4 <2,2,5,5>, <2,2,5,5> - 3364259460U, // <2,5,5,3>: Cost 4 vmrglw <1,4,2,5>, <2,2,5,3> - 4040215862U, // <2,5,5,4>: Cost 4 vsldoi4 <2,2,5,5>, RHS - 3263123460U, // <2,5,5,5>: Cost 3 vsldoi12 <7,0,1,2>, <5,5,5,5> - 3364258167U, // <2,5,5,6>: Cost 4 vmrglw <1,4,2,5>, <0,4,5,6> - 3263123473U, // <2,5,5,7>: Cost 4 vsldoi12 <7,0,1,2>, <5,5,7,0> - 3263123460U, // <2,5,5,u>: Cost 3 vsldoi12 <7,0,1,2>, <5,5,5,5> - 4052164710U, // <2,5,6,0>: Cost 3 vsldoi4 <4,2,5,6>, LHS - 3386166810U, // <2,5,6,1>: Cost 4 vmrglw <5,1,2,6>, <4,u,5,1> - 4199428602U, // <2,5,6,2>: Cost 3 vsldoi8 <6,4,2,5>, <6,2,7,3> - 3244544066U, // <2,5,6,3>: Cost 4 vsldoi12 <3,u,1,2>, <5,6,3,4> - 4199428721U, // <2,5,6,4>: Cost 3 vsldoi8 <6,4,2,5>, <6,4,2,5> - 3237433348U, // <2,5,6,5>: Cost 3 vmrghw <2,6,3,7>, <5,5,5,5> - 3237433442U, // <2,5,6,6>: Cost 3 vmrghw <2,6,3,7>, <5,6,7,0> - 3255603300U, // <2,5,6,7>: Cost 3 vsldoi12 <5,6,7,2>, <5,6,7,2> - 3255677037U, // <2,5,6,u>: Cost 3 vsldoi12 <5,6,u,2>, <5,6,u,2> - 4199429114U, // <2,5,7,0>: Cost 4 vsldoi8 <6,4,2,5>, <7,0,1,2> - 4203410519U, // <2,5,7,1>: Cost 4 vsldoi8 <7,1,2,5>, <7,1,2,5> - 3249483913U, // <2,5,7,2>: Cost 4 vsldoi12 <4,6,5,2>, <5,7,2,3> - 4199429402U, // <2,5,7,3>: Cost 4 vsldoi8 <6,4,2,5>, <7,3,6,2> - 4199429478U, // <2,5,7,4>: Cost 4 vsldoi8 <6,4,2,5>, <7,4,5,6> - 4206065051U, // <2,5,7,5>: Cost 4 vsldoi8 <7,5,2,5>, <7,5,2,5> - 3371575081U, // <2,5,7,6>: Cost 4 vmrglw <2,6,2,7>, <2,4,5,6> - 4199429700U, // <2,5,7,7>: Cost 4 vsldoi8 <6,4,2,5>, <7,7,3,3> - 3371575083U, // <2,5,7,u>: Cost 4 vmrglw <2,6,2,7>, <2,4,5,u> - 3360967650U, // <2,5,u,0>: Cost 3 vmrglw LHS, <4,1,5,0> - 2330356626U, // <2,5,u,1>: Cost 2 vmrglw LHS, <4,0,5,1> - 4052182734U, // <2,5,u,2>: Cost 3 vsldoi4 <4,2,5,u>, <2,3,4,5> - 3360965547U, // <2,5,u,3>: Cost 3 vmrglw LHS, <1,2,5,3> - 3360967654U, // <2,5,u,4>: Cost 3 vmrglw LHS, <4,1,5,4> - 2330356954U, // <2,5,u,5>: Cost 2 vmrglw LHS, <4,4,5,5> - 2282580482U, // <2,5,u,6>: Cost 2 vmrglw LHS, <3,4,5,6> - 3360965875U, // <2,5,u,7>: Cost 3 vmrglw LHS, <1,6,5,7> - 2282580484U, // <2,5,u,u>: Cost 2 vmrglw LHS, <3,4,5,u> - 4174880768U, // <2,6,0,0>: Cost 4 vsldoi8 <2,3,2,6>, <0,0,0,0> - 4174880870U, // <2,6,0,1>: Cost 3 vsldoi8 <2,3,2,6>, LHS - 4162273466U, // <2,6,0,2>: Cost 4 vsldoi8 <0,2,2,6>, <0,2,2,6> - 4046219619U, // <2,6,0,3>: Cost 4 vsldoi4 <3,2,6,0>, <3,2,6,0> - 4170236242U, // <2,6,0,4>: Cost 4 vsldoi8 <1,5,2,6>, <0,4,1,5> - 3378153265U, // <2,6,0,5>: Cost 5 vmrglw <3,7,2,0>, <2,4,6,5> - 3261206861U, // <2,6,0,6>: Cost 4 vsldoi12 <6,6,2,2>, <6,0,6,1> - 3404033334U, // <2,6,0,7>: Cost 3 vmrglw , RHS - 4174881437U, // <2,6,0,u>: Cost 3 vsldoi8 <2,3,2,6>, LHS - 4070113382U, // <2,6,1,0>: Cost 4 vsldoi4 <7,2,6,1>, LHS - 4167582530U, // <2,6,1,1>: Cost 4 vsldoi8 <1,1,2,6>, <1,1,2,6> - 4174881686U, // <2,6,1,2>: Cost 4 vsldoi8 <2,3,2,6>, <1,2,3,0> - 4070115478U, // <2,6,1,3>: Cost 4 vsldoi4 <7,2,6,1>, <3,0,1,2> - 4070116662U, // <2,6,1,4>: Cost 4 vsldoi4 <7,2,6,1>, RHS - 4170237062U, // <2,6,1,5>: Cost 4 vsldoi8 <1,5,2,6>, <1,5,2,6> - 4170900695U, // <2,6,1,6>: Cost 4 vsldoi8 <1,6,2,6>, <1,6,2,6> - 3366882614U, // <2,6,1,7>: Cost 3 vmrglw <1,u,2,1>, RHS - 3366882615U, // <2,6,1,u>: Cost 3 vmrglw <1,u,2,1>, RHS - 4040261734U, // <2,6,2,0>: Cost 4 vsldoi4 <2,2,6,2>, LHS - 3395424589U, // <2,6,2,1>: Cost 4 vmrglw <6,6,2,2>, <6,0,6,1> - 3234664953U, // <2,6,2,2>: Cost 3 vmrghw <2,2,2,2>, <6,2,7,2> - 4174882493U, // <2,6,2,3>: Cost 3 vsldoi8 <2,3,2,6>, <2,3,2,6> - 4040265014U, // <2,6,2,4>: Cost 4 vsldoi4 <2,2,6,2>, RHS - 4176209759U, // <2,6,2,5>: Cost 4 vsldoi8 <2,5,2,6>, <2,5,2,6> - 4174882746U, // <2,6,2,6>: Cost 3 vsldoi8 <2,3,2,6>, <2,6,3,7> - 2295139638U, // <2,6,2,7>: Cost 2 vmrglw <2,2,2,2>, RHS - 2295139639U, // <2,6,2,u>: Cost 2 vmrglw <2,2,2,2>, RHS - 4046241894U, // <2,6,3,0>: Cost 3 vsldoi4 <3,2,6,3>, LHS - 3404056041U, // <2,6,3,1>: Cost 3 vmrglw LHS, <2,0,6,1> - 4046243770U, // <2,6,3,2>: Cost 3 vsldoi4 <3,2,6,3>, <2,6,3,7> - 3360926054U, // <2,6,3,3>: Cost 3 vmrglw LHS, <3,2,6,3> - 4046245174U, // <2,6,3,4>: Cost 3 vsldoi4 <3,2,6,3>, RHS - 4058189592U, // <2,6,3,5>: Cost 3 vsldoi4 <5,2,6,3>, <5,2,6,3> - 2330317624U, // <2,6,3,6>: Cost 2 vmrglw LHS, <6,6,6,6> - 1208798518U, // <2,6,3,7>: Cost 1 vmrglw LHS, RHS - 1208798519U, // <2,6,3,u>: Cost 1 vmrglw LHS, RHS - 4046250086U, // <2,6,4,0>: Cost 4 vsldoi4 <3,2,6,4>, LHS - 4034306997U, // <2,6,4,1>: Cost 5 vsldoi4 <1,2,6,4>, <1,2,6,4> - 4046251709U, // <2,6,4,2>: Cost 4 vsldoi4 <3,2,6,4>, <2,3,2,6> - 4046252391U, // <2,6,4,3>: Cost 4 vsldoi4 <3,2,6,4>, <3,2,6,4> - 4046253366U, // <2,6,4,4>: Cost 4 vsldoi4 <3,2,6,4>, RHS - 4174884150U, // <2,6,4,5>: Cost 3 vsldoi8 <2,3,2,6>, RHS - 4199435641U, // <2,6,4,6>: Cost 4 vsldoi8 <6,4,2,6>, <4,6,5,2> - 3368897846U, // <2,6,4,7>: Cost 3 vmrglw <2,2,2,4>, RHS - 3368897847U, // <2,6,4,u>: Cost 3 vmrglw <2,2,2,4>, RHS - 3236761889U, // <2,6,5,0>: Cost 4 vmrghw <2,5,3,6>, <6,0,1,2> - 4191473318U, // <2,6,5,1>: Cost 4 vsldoi8 <5,1,2,6>, <5,1,2,6> - 4182183704U, // <2,6,5,2>: Cost 4 vsldoi8 <3,5,2,6>, <5,2,6,3> - 3236762162U, // <2,6,5,3>: Cost 4 vmrghw <2,5,3,6>, <6,3,4,5> - 3236762253U, // <2,6,5,4>: Cost 4 vmrghw <2,5,3,6>, <6,4,5,6> - 4194127850U, // <2,6,5,5>: Cost 4 vsldoi8 <5,5,2,6>, <5,5,2,6> - 4194791483U, // <2,6,5,6>: Cost 4 vsldoi8 <5,6,2,6>, <5,6,2,6> - 3364261174U, // <2,6,5,7>: Cost 3 vmrglw <1,4,2,5>, RHS - 3364261175U, // <2,6,5,u>: Cost 3 vmrglw <1,4,2,5>, RHS - 4040294502U, // <2,6,6,0>: Cost 3 vsldoi4 <2,2,6,6>, LHS - 3372893673U, // <2,6,6,1>: Cost 4 vmrglw <2,u,2,6>, <2,0,6,1> - 3261207312U, // <2,6,6,2>: Cost 3 vsldoi12 <6,6,2,2>, <6,6,2,2> - 3237433928U, // <2,6,6,3>: Cost 3 vmrghw <2,6,3,7>, <6,3,7,0> - 4040297782U, // <2,6,6,4>: Cost 3 vsldoi4 <2,2,6,6>, RHS - 3372894001U, // <2,6,6,5>: Cost 4 vmrglw <2,u,2,6>, <2,4,6,5> - 3263124280U, // <2,6,6,6>: Cost 3 vsldoi12 <7,0,1,2>, <6,6,6,6> - 3369577782U, // <2,6,6,7>: Cost 3 vmrglw <2,3,2,6>, RHS - 3369577783U, // <2,6,6,u>: Cost 3 vmrglw <2,3,2,6>, RHS - 3263124302U, // <2,6,7,0>: Cost 3 vsldoi12 <7,0,1,2>, <6,7,0,1> - 3261797208U, // <2,6,7,1>: Cost 3 vsldoi12 <6,7,1,2>, <6,7,1,2> - 3261870945U, // <2,6,7,2>: Cost 3 vsldoi12 <6,7,2,2>, <6,7,2,2> - 3239236456U, // <2,6,7,3>: Cost 3 vsldoi12 <3,0,1,2>, <6,7,3,0> - 3263124342U, // <2,6,7,4>: Cost 3 vsldoi12 <7,0,1,2>, <6,7,4,5> - 3371575089U, // <2,6,7,5>: Cost 4 vmrglw <2,6,2,7>, <2,4,6,5> - 3262165893U, // <2,6,7,6>: Cost 3 vsldoi12 <6,7,6,2>, <6,7,6,2> - 3371576630U, // <2,6,7,7>: Cost 3 vmrglw <2,6,2,7>, RHS - 3371576631U, // <2,6,7,u>: Cost 3 vmrglw <2,6,2,7>, RHS - 4046282854U, // <2,6,u,0>: Cost 3 vsldoi4 <3,2,6,u>, LHS - 4174886702U, // <2,6,u,1>: Cost 3 vsldoi8 <2,3,2,6>, LHS - 4046284775U, // <2,6,u,2>: Cost 3 vsldoi4 <3,2,6,u>, <2,6,u,7> - 3356322150U, // <2,6,u,3>: Cost 3 vmrglw LHS, <3,2,6,3> - 4046286134U, // <2,6,u,4>: Cost 3 vsldoi4 <3,2,6,u>, RHS - 4174887066U, // <2,6,u,5>: Cost 3 vsldoi8 <2,3,2,6>, RHS - 2330358584U, // <2,6,u,6>: Cost 2 vmrglw LHS, <6,6,6,6> - 1208839478U, // <2,6,u,7>: Cost 1 vmrglw LHS, RHS - 1208839479U, // <2,6,u,u>: Cost 1 vmrglw LHS, RHS - 4076150886U, // <2,7,0,0>: Cost 3 vsldoi4 , LHS - 3263124474U, // <2,7,0,1>: Cost 2 vsldoi12 <7,0,1,2>, <7,0,1,2> - 4170907821U, // <2,7,0,2>: Cost 4 vsldoi8 <1,6,2,7>, <0,2,1,2> - 3393417722U, // <2,7,0,3>: Cost 4 vmrglw <6,3,2,0>, <6,2,7,3> - 4076154166U, // <2,7,0,4>: Cost 3 vsldoi4 , RHS - 3263124514U, // <2,7,0,5>: Cost 4 vsldoi12 <7,0,1,2>, <7,0,5,6> - 4064211447U, // <2,7,0,6>: Cost 4 vsldoi4 <6,2,7,0>, <6,2,7,0> - 4076155961U, // <2,7,0,7>: Cost 3 vsldoi4 , <7,0,u,2> - 3263640633U, // <2,7,0,u>: Cost 2 vsldoi12 <7,0,u,2>, <7,0,u,2> - 4064215142U, // <2,7,1,0>: Cost 4 vsldoi4 <6,2,7,1>, LHS - 4176880436U, // <2,7,1,1>: Cost 4 vsldoi8 <2,6,2,7>, <1,1,1,1> - 4176880534U, // <2,7,1,2>: Cost 4 vsldoi8 <2,6,2,7>, <1,2,3,0> - 3396743674U, // <2,7,1,3>: Cost 3 vmrglw <6,u,2,1>, <6,2,7,3> - 4064218422U, // <2,7,1,4>: Cost 4 vsldoi4 <6,2,7,1>, RHS - 4176880751U, // <2,7,1,5>: Cost 5 vsldoi8 <2,6,2,7>, <1,5,0,1> - 4170908888U, // <2,7,1,6>: Cost 3 vsldoi8 <1,6,2,7>, <1,6,2,7> - 3396744002U, // <2,7,1,7>: Cost 4 vmrglw <6,u,2,1>, <6,6,7,7> - 3396743674U, // <2,7,1,u>: Cost 3 vmrglw <6,u,2,1>, <6,2,7,3> - 4064223334U, // <2,7,2,0>: Cost 3 vsldoi4 <6,2,7,2>, LHS - 4064224052U, // <2,7,2,1>: Cost 4 vsldoi4 <6,2,7,2>, <1,1,1,1> - 4176881256U, // <2,7,2,2>: Cost 3 vsldoi8 <2,6,2,7>, <2,2,2,2> - 3395424762U, // <2,7,2,3>: Cost 3 vmrglw <6,6,2,2>, <6,2,7,3> - 4064226614U, // <2,7,2,4>: Cost 3 vsldoi4 <6,2,7,2>, RHS - 3255604420U, // <2,7,2,5>: Cost 4 vsldoi12 <5,6,7,2>, <7,2,5,6> - 4176881585U, // <2,7,2,6>: Cost 3 vsldoi8 <2,6,2,7>, <2,6,2,7> - 3234666092U, // <2,7,2,7>: Cost 3 vmrghw <2,2,2,2>, <7,7,7,7> - 4178208851U, // <2,7,2,u>: Cost 3 vsldoi8 <2,u,2,7>, <2,u,2,7> - 2990489702U, // <2,7,3,0>: Cost 2 vsldoi4 <6,2,7,3>, LHS - 4064232244U, // <2,7,3,1>: Cost 3 vsldoi4 <6,2,7,3>, <1,1,1,1> - 4046317498U, // <2,7,3,2>: Cost 3 vsldoi4 <3,2,7,3>, <2,6,3,7> - 2330317306U, // <2,7,3,3>: Cost 2 vmrglw LHS, <6,2,7,3> - 2990492982U, // <2,7,3,4>: Cost 2 vsldoi4 <6,2,7,3>, RHS - 4064235524U, // <2,7,3,5>: Cost 3 vsldoi4 <6,2,7,3>, <5,5,5,5> - 2990494202U, // <2,7,3,6>: Cost 2 vsldoi4 <6,2,7,3>, <6,2,7,3> - 2330317634U, // <2,7,3,7>: Cost 2 vmrglw LHS, <6,6,7,7> - 2990495534U, // <2,7,3,u>: Cost 2 vsldoi4 <6,2,7,3>, LHS - 4064239718U, // <2,7,4,0>: Cost 4 vsldoi4 <6,2,7,4>, LHS - 3265779006U, // <2,7,4,1>: Cost 4 vsldoi12 <7,4,1,2>, <7,4,1,2> - 4064241256U, // <2,7,4,2>: Cost 4 vsldoi4 <6,2,7,4>, <2,2,2,2> - 3393450490U, // <2,7,4,3>: Cost 4 vmrglw <6,3,2,4>, <6,2,7,3> - 4064242998U, // <2,7,4,4>: Cost 4 vsldoi4 <6,2,7,4>, RHS - 4176882998U, // <2,7,4,5>: Cost 3 vsldoi8 <2,6,2,7>, RHS - 4064244219U, // <2,7,4,6>: Cost 4 vsldoi4 <6,2,7,4>, <6,2,7,4> - 3263124850U, // <2,7,4,7>: Cost 4 vsldoi12 <7,0,1,2>, <7,4,7,0> - 4176883241U, // <2,7,4,u>: Cost 3 vsldoi8 <2,6,2,7>, RHS - 3251180933U, // <2,7,5,0>: Cost 4 vsldoi12 <5,0,1,2>, <7,5,0,1> - 4064248726U, // <2,7,5,1>: Cost 4 vsldoi4 <6,2,7,5>, <1,2,3,0> - 3370233956U, // <2,7,5,2>: Cost 4 vmrglw <2,4,2,5>, <5,6,7,2> - 3394122234U, // <2,7,5,3>: Cost 3 vmrglw <6,4,2,5>, <6,2,7,3> - 4064251190U, // <2,7,5,4>: Cost 4 vsldoi4 <6,2,7,5>, RHS - 3263124918U, // <2,7,5,5>: Cost 4 vsldoi12 <7,0,1,2>, <7,5,5,5> - 4194799676U, // <2,7,5,6>: Cost 4 vsldoi8 <5,6,2,7>, <5,6,2,7> - 3394122562U, // <2,7,5,7>: Cost 4 vmrglw <6,4,2,5>, <6,6,7,7> - 3394122234U, // <2,7,5,u>: Cost 3 vmrglw <6,4,2,5>, <6,2,7,3> - 3237434362U, // <2,7,6,0>: Cost 3 vmrghw <2,6,3,7>, <7,0,1,2> - 4170912168U, // <2,7,6,1>: Cost 4 vsldoi8 <1,6,2,7>, <6,1,7,2> - 4206744058U, // <2,7,6,2>: Cost 3 vsldoi8 <7,6,2,7>, <6,2,7,3> - 3372894575U, // <2,7,6,3>: Cost 4 vmrglw <2,u,2,6>, <3,2,7,3> - 3237434726U, // <2,7,6,4>: Cost 3 vmrghw <2,6,3,7>, <7,4,5,6> - 3237434806U, // <2,7,6,5>: Cost 4 vmrghw <2,6,3,7>, <7,5,5,5> - 4064260605U, // <2,7,6,6>: Cost 4 vsldoi4 <6,2,7,6>, <6,2,7,6> - 3237434988U, // <2,7,6,7>: Cost 3 vmrghw <2,6,3,7>, <7,7,7,7> - 4206744058U, // <2,7,6,u>: Cost 3 vsldoi8 <7,6,2,7>, <6,2,7,3> - 3263125031U, // <2,7,7,0>: Cost 3 vsldoi12 <7,0,1,2>, <7,7,0,1> - 4064265432U, // <2,7,7,1>: Cost 4 vsldoi4 <6,2,7,7>, <1,6,2,7> - 3371574933U, // <2,7,7,2>: Cost 4 vmrglw <2,6,2,7>, <2,2,7,2> - 3401437690U, // <2,7,7,3>: Cost 3 vmrglw <7,6,2,7>, <6,2,7,3> - 4064267574U, // <2,7,7,4>: Cost 4 vsldoi4 <6,2,7,7>, RHS - 3371574855U, // <2,7,7,5>: Cost 5 vmrglw <2,6,2,7>, <2,1,7,5> - 4206745070U, // <2,7,7,6>: Cost 3 vsldoi8 <7,6,2,7>, <7,6,2,7> - 3263125100U, // <2,7,7,7>: Cost 3 vsldoi12 <7,0,1,2>, <7,7,7,7> - 3268433519U, // <2,7,7,u>: Cost 3 vsldoi12 <7,u,1,2>, <7,7,u,1> - 2990530662U, // <2,7,u,0>: Cost 2 vsldoi4 <6,2,7,u>, LHS - 3268433538U, // <2,7,u,1>: Cost 2 vsldoi12 <7,u,1,2>, <7,u,1,2> - 4046358458U, // <2,7,u,2>: Cost 3 vsldoi4 <3,2,7,u>, <2,6,3,7> - 2330358266U, // <2,7,u,3>: Cost 2 vmrglw LHS, <6,2,7,3> - 2990533942U, // <2,7,u,4>: Cost 2 vsldoi4 <6,2,7,u>, RHS - 4176885914U, // <2,7,u,5>: Cost 3 vsldoi8 <2,6,2,7>, RHS - 2990535167U, // <2,7,u,6>: Cost 2 vsldoi4 <6,2,7,u>, <6,2,7,u> - 2330358594U, // <2,7,u,7>: Cost 2 vmrglw LHS, <6,6,7,7> - 2990536494U, // <2,7,u,u>: Cost 2 vsldoi4 <6,2,7,u>, LHS - 3087884288U, // <2,u,0,0>: Cost 2 vsldoi8 LHS, <0,0,0,0> - 2014142571U, // <2,u,0,1>: Cost 1 vsldoi8 LHS, LHS - 4161626285U, // <2,u,0,2>: Cost 3 vsldoi8 LHS, <0,2,1,2> - 4161626364U, // <2,u,0,3>: Cost 3 vsldoi8 LHS, <0,3,1,0> - 3087884626U, // <2,u,0,4>: Cost 2 vsldoi8 LHS, <0,4,1,5> - 3233396890U, // <2,u,0,5>: Cost 3 vmrghw <2,0,3,0>, RHS - 4209402358U, // <2,u,0,6>: Cost 3 vsldoi8 LHS, <0,6,1,7> - 4070257881U, // <2,u,0,7>: Cost 3 vsldoi4 <7,2,u,0>, <7,2,u,0> - 2014143133U, // <2,u,0,u>: Cost 1 vsldoi8 LHS, LHS - 4166271716U, // <2,u,1,0>: Cost 3 vsldoi8 LHS, <1,0,1,2> - 3087885108U, // <2,u,1,1>: Cost 2 vsldoi8 LHS, <1,1,1,1> - 3087885206U, // <2,u,1,2>: Cost 2 vsldoi8 LHS, <1,2,3,0> - 3366879388U, // <2,u,1,3>: Cost 3 vmrglw <1,u,2,1>, LHS - 4166272080U, // <2,u,1,4>: Cost 3 vsldoi8 LHS, <1,4,5,6> - 4166272111U, // <2,u,1,5>: Cost 3 vsldoi8 LHS, <1,5,0,1> - 4166272207U, // <2,u,1,6>: Cost 3 vsldoi8 LHS, <1,6,1,7> - 3366882632U, // <2,u,1,7>: Cost 3 vmrglw <1,u,2,1>, RHS - 3092530556U, // <2,u,1,u>: Cost 2 vsldoi8 LHS, <1,u,3,0> - 2966224998U, // <2,u,2,0>: Cost 2 vsldoi4 <2,2,2,2>, LHS - 2160924462U, // <2,u,2,1>: Cost 2 vmrghw <2,2,2,2>, LHS - 1611448422U, // <2,u,2,2>: Cost 1 vspltisw2 LHS - 3087885990U, // <2,u,2,3>: Cost 2 vsldoi8 LHS, <2,3,0,1> - 2966228278U, // <2,u,2,4>: Cost 2 vsldoi4 <2,2,2,2>, RHS - 2160924826U, // <2,u,2,5>: Cost 2 vmrghw <2,2,2,2>, RHS - 3087886266U, // <2,u,2,6>: Cost 2 vsldoi8 LHS, <2,6,3,7> - 2295139656U, // <2,u,2,7>: Cost 2 vmrglw <2,2,2,2>, RHS - 1611448422U, // <2,u,2,u>: Cost 1 vspltisw2 LHS - 3087886486U, // <2,u,3,0>: Cost 2 vsldoi8 LHS, <3,0,1,2> - 2287181897U, // <2,u,3,1>: Cost 2 vmrglw LHS, <0,0,u,1> - 2287184085U, // <2,u,3,2>: Cost 2 vmrglw LHS, <3,0,u,2> - 1208795292U, // <2,u,3,3>: Cost 1 vmrglw LHS, LHS - 3087886850U, // <2,u,3,4>: Cost 2 vsldoi8 LHS, <3,4,5,6> - 2287182225U, // <2,u,3,5>: Cost 2 vmrglw LHS, <0,4,u,5> - 2287184413U, // <2,u,3,6>: Cost 2 vmrglw LHS, <3,4,u,6> - 1208798536U, // <2,u,3,7>: Cost 1 vmrglw LHS, RHS - 1208795297U, // <2,u,3,u>: Cost 1 vmrglw LHS, LHS - 2960711782U, // <2,u,4,0>: Cost 2 vsldoi4 <1,2,u,4>, LHS - 2960712647U, // <2,u,4,1>: Cost 2 vsldoi4 <1,2,u,4>, <1,2,u,4> - 4034455144U, // <2,u,4,2>: Cost 3 vsldoi4 <1,2,u,4>, <2,2,2,2> - 4034455702U, // <2,u,4,3>: Cost 3 vsldoi4 <1,2,u,4>, <3,0,1,2> - 2960715062U, // <2,u,4,4>: Cost 2 vsldoi4 <1,2,u,4>, RHS - 2014145846U, // <2,u,4,5>: Cost 1 vsldoi8 LHS, RHS - 4209405305U, // <2,u,4,6>: Cost 3 vsldoi8 LHS, <4,6,5,2> - 3368897864U, // <2,u,4,7>: Cost 3 vmrglw <2,2,2,4>, RHS - 2014146089U, // <2,u,4,u>: Cost 1 vsldoi8 LHS, RHS - 4166274632U, // <2,u,5,0>: Cost 3 vsldoi8 LHS, <5,0,1,2> - 3236763438U, // <2,u,5,1>: Cost 3 vmrghw <2,5,3,6>, LHS - 4040435361U, // <2,u,5,2>: Cost 3 vsldoi4 <2,2,u,5>, <2,2,u,5> - 3364257948U, // <2,u,5,3>: Cost 3 vmrglw <1,4,2,5>, LHS - 4166274996U, // <2,u,5,4>: Cost 3 vsldoi8 LHS, <5,4,5,6> - 3135664132U, // <2,u,5,5>: Cost 2 vsldoi8 LHS, <5,5,5,5> - 3234666650U, // <2,u,5,6>: Cost 2 vsldoi12 <2,2,2,2>, RHS - 3364261192U, // <2,u,5,7>: Cost 3 vmrglw <1,4,2,5>, RHS - 3234666668U, // <2,u,5,u>: Cost 2 vsldoi12 <2,2,2,2>, RHS - 3237435091U, // <2,u,6,0>: Cost 3 vmrghw <2,6,3,7>, - 2163693358U, // <2,u,6,1>: Cost 2 vmrghw <2,6,3,7>, LHS - 3135664634U, // <2,u,6,2>: Cost 2 vsldoi8 LHS, <6,2,7,3> - 3234666704U, // <2,u,6,3>: Cost 3 vsldoi12 <2,2,2,2>, - 3237435455U, // <2,u,6,4>: Cost 3 vmrghw <2,6,3,7>, - 2163693722U, // <2,u,6,5>: Cost 2 vmrghw <2,6,3,7>, RHS - 3135664952U, // <2,u,6,6>: Cost 2 vsldoi8 LHS, <6,6,6,6> - 3135664974U, // <2,u,6,7>: Cost 2 vsldoi8 LHS, <6,7,0,1> - 2163693925U, // <2,u,6,u>: Cost 2 vmrghw <2,6,3,7>, LHS - 3135665146U, // <2,u,7,0>: Cost 2 vsldoi8 LHS, <7,0,1,2> - 4203435098U, // <2,u,7,1>: Cost 3 vsldoi8 <7,1,2,u>, <7,1,2,u> - 4204098731U, // <2,u,7,2>: Cost 3 vsldoi8 <7,2,2,u>, <7,2,2,u> - 3371573404U, // <2,u,7,3>: Cost 3 vmrglw <2,6,2,7>, LHS - 3135665510U, // <2,u,7,4>: Cost 2 vsldoi8 LHS, <7,4,5,6> - 4209407414U, // <2,u,7,5>: Cost 3 vsldoi8 LHS, <7,5,5,5> - 4206753263U, // <2,u,7,6>: Cost 3 vsldoi8 <7,6,2,u>, <7,6,2,u> - 3135665772U, // <2,u,7,7>: Cost 2 vsldoi8 LHS, <7,7,7,7> - 3135665794U, // <2,u,7,u>: Cost 2 vsldoi8 LHS, <7,u,1,2> - 2287223747U, // <2,u,u,0>: Cost 2 vmrglw LHS, <1,2,u,0> - 2014148398U, // <2,u,u,1>: Cost 1 vsldoi8 LHS, LHS - 1611448422U, // <2,u,u,2>: Cost 1 vspltisw2 LHS - 1208836252U, // <2,u,u,3>: Cost 1 vmrglw LHS, LHS - 2287223751U, // <2,u,u,4>: Cost 2 vmrglw LHS, <1,2,u,4> - 2014148762U, // <2,u,u,5>: Cost 1 vsldoi8 LHS, RHS - 2282580509U, // <2,u,u,6>: Cost 2 vmrglw LHS, <3,4,u,6> - 1208839496U, // <2,u,u,7>: Cost 1 vmrglw LHS, RHS - 1208836257U, // <2,u,u,u>: Cost 1 vmrglw LHS, LHS - 3222061056U, // <3,0,0,0>: Cost 2 vsldoi12 LHS, <0,0,0,0> - 3222061066U, // <3,0,0,1>: Cost 2 vsldoi12 LHS, <0,0,1,1> - 4040468133U, // <3,0,0,2>: Cost 3 vsldoi4 <2,3,0,0>, <2,3,0,0> - 3362965808U, // <3,0,0,3>: Cost 3 vmrglw <1,2,3,0>, <3,2,0,3> - 3226705957U, // <3,0,0,4>: Cost 3 vsldoi12 LHS, <0,0,4,1> - 3362965729U, // <3,0,0,5>: Cost 4 vmrglw <1,2,3,0>, <3,1,0,5> - 3362966054U, // <3,0,0,6>: Cost 4 vmrglw <1,2,3,0>, <3,5,0,6> - 3362966136U, // <3,0,0,7>: Cost 3 vmrglw <1,2,3,0>, <3,6,0,7> - 3226705993U, // <3,0,0,u>: Cost 2 vsldoi12 LHS, <0,0,u,1> - 2966732902U, // <3,0,1,0>: Cost 2 vsldoi4 <2,3,0,1>, LHS - 3222503515U, // <3,0,1,1>: Cost 3 vsldoi12 LHS, <0,1,1,1> - 1074577510U, // <3,0,1,2>: Cost 1 vsldoi12 LHS, LHS - 4040476820U, // <3,0,1,3>: Cost 3 vsldoi4 <2,3,0,1>, <3,0,1,0> - 2966736182U, // <3,0,1,4>: Cost 2 vsldoi4 <2,3,0,1>, RHS - 4076310532U, // <3,0,1,5>: Cost 3 vsldoi4 , <5,5,5,5> - 3269836942U, // <3,0,1,6>: Cost 3 vsldoi12 LHS, <0,1,6,7> - 4070339811U, // <3,0,1,7>: Cost 3 vsldoi4 <7,3,0,1>, <7,3,0,1> - 1074577564U, // <3,0,1,u>: Cost 1 vsldoi12 LHS, LHS - 4172916173U, // <3,0,2,0>: Cost 3 vsldoi8 <2,0,3,0>, <2,0,3,0> - 3222503597U, // <3,0,2,1>: Cost 3 vsldoi12 LHS, <0,2,1,2> - 4168271464U, // <3,0,2,2>: Cost 3 vsldoi8 <1,2,3,0>, <2,2,2,2> - 4168271526U, // <3,0,2,3>: Cost 3 vsldoi8 <1,2,3,0>, <2,3,0,1> - 3226706119U, // <3,0,2,4>: Cost 4 vsldoi12 LHS, <0,2,4,1> - 4168271720U, // <3,0,2,5>: Cost 4 vsldoi8 <1,2,3,0>, <2,5,3,6> - 4168271802U, // <3,0,2,6>: Cost 3 vsldoi8 <1,2,3,0>, <2,6,3,7> - 4177561604U, // <3,0,2,7>: Cost 3 vsldoi8 <2,7,3,0>, <2,7,3,0> - 3226706156U, // <3,0,2,u>: Cost 3 vsldoi12 LHS, <0,2,u,2> - 4168272022U, // <3,0,3,0>: Cost 3 vsldoi8 <1,2,3,0>, <3,0,1,2> - 2167636070U, // <3,0,3,1>: Cost 2 vmrghw <3,3,3,3>, LHS - 4168272176U, // <3,0,3,2>: Cost 3 vsldoi8 <1,2,3,0>, <3,2,0,3> - 4168272254U, // <3,0,3,3>: Cost 3 vsldoi8 <1,2,3,0>, <3,3,0,0> - 4168272386U, // <3,0,3,4>: Cost 3 vsldoi8 <1,2,3,0>, <3,4,5,6> - 4168272422U, // <3,0,3,5>: Cost 4 vsldoi8 <1,2,3,0>, <3,5,0,6> - 4168272504U, // <3,0,3,6>: Cost 3 vsldoi8 <1,2,3,0>, <3,6,0,7> - 3368962680U, // <3,0,3,7>: Cost 4 vmrglw <2,2,3,3>, <3,6,0,7> - 2167636637U, // <3,0,3,u>: Cost 2 vmrghw <3,3,3,3>, LHS - 3362996224U, // <3,0,4,0>: Cost 3 vmrglw <1,2,3,4>, <0,0,0,0> - 3222061394U, // <3,0,4,1>: Cost 2 vsldoi12 LHS, <0,4,1,5> - 4040500905U, // <3,0,4,2>: Cost 3 vsldoi4 <2,3,0,4>, <2,3,0,4> - 3242213632U, // <3,0,4,3>: Cost 3 vmrghw <3,4,5,6>, <0,3,1,4> - 3226706285U, // <3,0,4,4>: Cost 3 vsldoi12 LHS, <0,4,4,5> - 3094531382U, // <3,0,4,5>: Cost 2 vsldoi8 <1,2,3,0>, RHS - 3242213878U, // <3,0,4,6>: Cost 4 vmrghw <3,4,5,6>, <0,6,1,7> - 3362998904U, // <3,0,4,7>: Cost 4 vmrglw <1,2,3,4>, <3,6,0,7> - 3226706321U, // <3,0,4,u>: Cost 2 vsldoi12 LHS, <0,4,u,5> - 4168273480U, // <3,0,5,0>: Cost 4 vsldoi8 <1,2,3,0>, <5,0,1,2> - 3222061475U, // <3,0,5,1>: Cost 3 vsldoi12 LHS, <0,5,1,5> - 4192161530U, // <3,0,5,2>: Cost 4 vsldoi8 <5,2,3,0>, <5,2,3,0> - 3403486842U, // <3,0,5,3>: Cost 4 vmrglw , <7,u,0,3> - 4168273844U, // <3,0,5,4>: Cost 4 vsldoi8 <1,2,3,0>, <5,4,5,6> - 4210077700U, // <3,0,5,5>: Cost 3 vsldoi8 , <5,5,5,5> - 3269837266U, // <3,0,5,6>: Cost 3 vsldoi12 LHS, <0,5,6,7> - 3269837268U, // <3,0,5,7>: Cost 4 vsldoi12 LHS, <0,5,7,0> - 3269837282U, // <3,0,5,u>: Cost 3 vsldoi12 LHS, <0,5,u,5> - 3222061549U, // <3,0,6,0>: Cost 3 vsldoi12 LHS, <0,6,0,7> - 3243180134U, // <3,0,6,1>: Cost 3 vmrghw <3,6,0,7>, LHS - 4210078202U, // <3,0,6,2>: Cost 3 vsldoi8 , <6,2,7,3> - 3240493576U, // <3,0,6,3>: Cost 4 vsldoi12 <3,2,0,3>, <0,6,3,7> - 3243180370U, // <3,0,6,4>: Cost 4 vmrghw <3,6,0,7>, <0,4,1,5> - 3269837338U, // <3,0,6,5>: Cost 4 vsldoi12 LHS, <0,6,5,7> - 4210078520U, // <3,0,6,6>: Cost 3 vsldoi8 , <6,6,6,6> - 4201452392U, // <3,0,6,7>: Cost 3 vsldoi8 <6,7,3,0>, <6,7,3,0> - 3243180701U, // <3,0,6,u>: Cost 3 vmrghw <3,6,0,7>, LHS - 3371646976U, // <3,0,7,0>: Cost 3 vmrglw <2,6,3,7>, <0,0,0,0> - 3371648678U, // <3,0,7,1>: Cost 3 vmrglw <2,6,3,7>, <2,3,0,1> - 4204106924U, // <3,0,7,2>: Cost 3 vsldoi8 <7,2,3,0>, <7,2,3,0> - 3371649328U, // <3,0,7,3>: Cost 4 vmrglw <2,6,3,7>, <3,2,0,3> - 4210079078U, // <3,0,7,4>: Cost 3 vsldoi8 , <7,4,5,6> - 4070387810U, // <3,0,7,5>: Cost 4 vsldoi4 <7,3,0,7>, <5,6,7,0> - 4201453079U, // <3,0,7,6>: Cost 4 vsldoi8 <6,7,3,0>, <7,6,7,3> - 4210079340U, // <3,0,7,7>: Cost 3 vsldoi8 , <7,7,7,7> - 3371648685U, // <3,0,7,u>: Cost 3 vmrglw <2,6,3,7>, <2,3,0,u> - 2966790246U, // <3,0,u,0>: Cost 2 vsldoi4 <2,3,0,u>, LHS - 3222061714U, // <3,0,u,1>: Cost 2 vsldoi12 LHS, <0,u,1,1> - 1074578077U, // <3,0,u,2>: Cost 1 vsldoi12 LHS, LHS - 4168275900U, // <3,0,u,3>: Cost 3 vsldoi8 <1,2,3,0>, - 2966793526U, // <3,0,u,4>: Cost 2 vsldoi4 <2,3,0,u>, RHS - 3094534298U, // <3,0,u,5>: Cost 2 vsldoi8 <1,2,3,0>, RHS - 4168276176U, // <3,0,u,6>: Cost 3 vsldoi8 <1,2,3,0>, - 4070397162U, // <3,0,u,7>: Cost 3 vsldoi4 <7,3,0,u>, <7,3,0,u> - 1074578131U, // <3,0,u,u>: Cost 1 vsldoi12 LHS, LHS - 4028596476U, // <3,1,0,0>: Cost 3 vsldoi4 <0,3,1,0>, <0,3,1,0> - 3226706660U, // <3,1,0,1>: Cost 3 vsldoi12 LHS, <1,0,1,2> - 3362963548U, // <3,1,0,2>: Cost 3 vmrglw <1,2,3,0>, <0,1,1,2> - 4028598422U, // <3,1,0,3>: Cost 3 vsldoi4 <0,3,1,0>, <3,0,1,2> - 4028599606U, // <3,1,0,4>: Cost 3 vsldoi4 <0,3,1,0>, RHS - 3362963794U, // <3,1,0,5>: Cost 3 vmrglw <1,2,3,0>, <0,4,1,5> - 3239232728U, // <3,1,0,6>: Cost 3 vmrghw <3,0,1,2>, <1,6,2,7> - 3362964687U, // <3,1,0,7>: Cost 4 vmrglw <1,2,3,0>, <1,6,1,7> - 4028602158U, // <3,1,0,u>: Cost 3 vsldoi4 <0,3,1,0>, LHS - 3226706731U, // <3,1,1,0>: Cost 3 vsldoi12 LHS, <1,1,0,1> - 3222061876U, // <3,1,1,1>: Cost 2 vsldoi12 LHS, <1,1,1,1> - 4168278935U, // <3,1,1,2>: Cost 3 vsldoi8 <1,2,3,1>, <1,2,3,1> - 3222651720U, // <3,1,1,3>: Cost 4 vsldoi12 <0,2,1,3>, <1,1,3,3> - 3226706771U, // <3,1,1,4>: Cost 3 vsldoi12 LHS, <1,1,4,5> - 3226706780U, // <3,1,1,5>: Cost 3 vsldoi12 LHS, <1,1,5,5> - 3226706785U, // <3,1,1,6>: Cost 4 vsldoi12 LHS, <1,1,6,1> - 4070413548U, // <3,1,1,7>: Cost 4 vsldoi4 <7,3,1,1>, <7,3,1,1> - 3222061876U, // <3,1,1,u>: Cost 2 vsldoi12 LHS, <1,1,1,1> - 4172924366U, // <3,1,2,0>: Cost 3 vsldoi8 <2,0,3,1>, <2,0,3,1> - 3226706823U, // <3,1,2,1>: Cost 3 vsldoi12 LHS, <1,2,1,3> - 3368290454U, // <3,1,2,2>: Cost 3 vmrglw <2,1,3,2>, <3,0,1,2> - 3222061974U, // <3,1,2,3>: Cost 2 vsldoi12 LHS, <1,2,3,0> - 4040559926U, // <3,1,2,4>: Cost 3 vsldoi4 <2,3,1,2>, RHS - 3226706859U, // <3,1,2,5>: Cost 3 vsldoi12 LHS, <1,2,5,3> - 3226706868U, // <3,1,2,6>: Cost 4 vsldoi12 LHS, <1,2,6,3> - 3269837754U, // <3,1,2,7>: Cost 3 vsldoi12 LHS, <1,2,7,0> - 3222504387U, // <3,1,2,u>: Cost 2 vsldoi12 LHS, <1,2,u,0> - 4028621055U, // <3,1,3,0>: Cost 3 vsldoi4 <0,3,1,3>, <0,3,1,3> - 3368960010U, // <3,1,3,1>: Cost 3 vmrglw <2,2,3,3>, <0,0,1,1> - 3366971542U, // <3,1,3,2>: Cost 3 vmrglw <1,u,3,3>, <3,0,1,2> - 4028623260U, // <3,1,3,3>: Cost 3 vsldoi4 <0,3,1,3>, <3,3,3,3> - 4028624182U, // <3,1,3,4>: Cost 3 vsldoi4 <0,3,1,3>, RHS - 3368960338U, // <3,1,3,5>: Cost 3 vmrglw <2,2,3,3>, <0,4,1,5> - 3226706953U, // <3,1,3,6>: Cost 4 vsldoi12 LHS, <1,3,6,7> - 3368961231U, // <3,1,3,7>: Cost 4 vmrglw <2,2,3,3>, <1,6,1,7> - 4028626734U, // <3,1,3,u>: Cost 3 vsldoi4 <0,3,1,3>, LHS - 4028629248U, // <3,1,4,0>: Cost 3 vsldoi4 <0,3,1,4>, <0,3,1,4> - 3362996234U, // <3,1,4,1>: Cost 3 vmrglw <1,2,3,4>, <0,0,1,1> - 3362998422U, // <3,1,4,2>: Cost 3 vmrglw <1,2,3,4>, <3,0,1,2> - 4028631554U, // <3,1,4,3>: Cost 3 vsldoi4 <0,3,1,4>, <3,4,5,6> - 4028632374U, // <3,1,4,4>: Cost 3 vsldoi4 <0,3,1,4>, RHS - 3226707024U, // <3,1,4,5>: Cost 3 vsldoi12 LHS, <1,4,5,6> - 3362996401U, // <3,1,4,6>: Cost 4 vmrglw <1,2,3,4>, <0,2,1,6> - 3362997455U, // <3,1,4,7>: Cost 4 vmrglw <1,2,3,4>, <1,6,1,7> - 4028634926U, // <3,1,4,u>: Cost 3 vsldoi4 <0,3,1,4>, LHS - 3226707055U, // <3,1,5,0>: Cost 3 vsldoi12 LHS, <1,5,0,1> - 3226707064U, // <3,1,5,1>: Cost 4 vsldoi12 LHS, <1,5,1,1> - 3358361750U, // <3,1,5,2>: Cost 4 vmrglw <0,4,3,5>, <3,0,1,2> - 3226707081U, // <3,1,5,3>: Cost 4 vsldoi12 LHS, <1,5,3,0> - 3226707095U, // <3,1,5,4>: Cost 3 vsldoi12 LHS, <1,5,4,5> - 3368313170U, // <3,1,5,5>: Cost 3 vmrglw <2,1,3,5>, <0,4,1,5> - 4208758882U, // <3,1,5,6>: Cost 4 vsldoi8 , <5,6,7,0> - 3269837998U, // <3,1,5,7>: Cost 4 vsldoi12 LHS, <1,5,7,1> - 3226707127U, // <3,1,5,u>: Cost 3 vsldoi12 LHS, <1,5,u,1> - 3226707136U, // <3,1,6,0>: Cost 4 vsldoi12 LHS, <1,6,0,1> - 3226707151U, // <3,1,6,1>: Cost 3 vsldoi12 LHS, <1,6,1,7> - 3243180950U, // <3,1,6,2>: Cost 3 vmrghw <3,6,0,7>, <1,2,3,0> - 3222652129U, // <3,1,6,3>: Cost 4 vsldoi12 <0,2,1,3>, <1,6,3,7> - 3226707176U, // <3,1,6,4>: Cost 4 vsldoi12 LHS, <1,6,4,5> - 3226707187U, // <3,1,6,5>: Cost 3 vsldoi12 LHS, <1,6,5,7> - 3226707196U, // <3,1,6,6>: Cost 4 vsldoi12 LHS, <1,6,6,7> - 3269838078U, // <3,1,6,7>: Cost 3 vsldoi12 LHS, <1,6,7,0> - 3226707214U, // <3,1,6,u>: Cost 3 vsldoi12 LHS, <1,6,u,7> - 4034625638U, // <3,1,7,0>: Cost 4 vsldoi4 <1,3,1,7>, LHS - 3371646986U, // <3,1,7,1>: Cost 3 vmrglw <2,6,3,7>, <0,0,1,1> - 3371649174U, // <3,1,7,2>: Cost 3 vmrglw <2,6,3,7>, <3,0,1,2> - 3365675182U, // <3,1,7,3>: Cost 4 vmrglw <1,6,3,7>, <0,2,1,3> - 4034628918U, // <3,1,7,4>: Cost 4 vsldoi4 <1,3,1,7>, RHS - 3371647314U, // <3,1,7,5>: Cost 3 vmrglw <2,6,3,7>, <0,4,1,5> - 3371647153U, // <3,1,7,6>: Cost 3 vmrglw <2,6,3,7>, <0,2,1,6> - 3368330447U, // <3,1,7,7>: Cost 4 vmrglw <2,1,3,7>, <1,6,1,7> - 3371646993U, // <3,1,7,u>: Cost 3 vmrglw <2,6,3,7>, <0,0,1,u> - 4028662020U, // <3,1,u,0>: Cost 3 vsldoi4 <0,3,1,u>, <0,3,1,u> - 3222061876U, // <3,1,u,1>: Cost 2 vsldoi12 LHS, <1,1,1,1> - 3363031190U, // <3,1,u,2>: Cost 3 vmrglw <1,2,3,u>, <3,0,1,2> - 3222504828U, // <3,1,u,3>: Cost 2 vsldoi12 LHS, <1,u,3,0> - 4028665142U, // <3,1,u,4>: Cost 3 vsldoi4 <0,3,1,u>, RHS - 3226707345U, // <3,1,u,5>: Cost 3 vsldoi12 LHS, <1,u,5,3> - 3371647153U, // <3,1,u,6>: Cost 3 vmrglw <2,6,3,7>, <0,2,1,6> - 3269838240U, // <3,1,u,7>: Cost 3 vsldoi12 LHS, <1,u,7,0> - 3226707369U, // <3,1,u,u>: Cost 2 vsldoi12 LHS, <1,u,u,0> - 3362964203U, // <3,2,0,0>: Cost 4 vmrglw <1,2,3,0>, <1,0,2,0> - 3362964204U, // <3,2,0,1>: Cost 3 vmrglw <1,2,3,0>, <1,0,2,1> - 3362964286U, // <3,2,0,2>: Cost 3 vmrglw <1,2,3,0>, <1,1,2,2> - 2289221734U, // <3,2,0,3>: Cost 2 vmrglw <1,2,3,0>, LHS - 3362964207U, // <3,2,0,4>: Cost 4 vmrglw <1,2,3,0>, <1,0,2,4> - 3362964532U, // <3,2,0,5>: Cost 3 vmrglw <1,2,3,0>, <1,4,2,5> - 3239233466U, // <3,2,0,6>: Cost 3 vmrghw <3,0,1,2>, <2,6,3,7> - 3396142296U, // <3,2,0,7>: Cost 4 vmrglw <6,7,3,0>, <1,6,2,7> - 2289221739U, // <3,2,0,u>: Cost 2 vmrglw <1,2,3,0>, LHS - 4034650214U, // <3,2,1,0>: Cost 4 vsldoi4 <1,3,2,1>, LHS - 4168287028U, // <3,2,1,1>: Cost 4 vsldoi8 <1,2,3,2>, <1,1,1,1> - 4168287128U, // <3,2,1,2>: Cost 3 vsldoi8 <1,2,3,2>, <1,2,3,2> - 3222062623U, // <3,2,1,3>: Cost 3 vsldoi12 LHS, <2,1,3,1> - 4034653494U, // <3,2,1,4>: Cost 4 vsldoi4 <1,3,2,1>, RHS - 3226707504U, // <3,2,1,5>: Cost 5 vsldoi12 LHS, <2,1,5,0> - 3226707513U, // <3,2,1,6>: Cost 4 vsldoi12 LHS, <2,1,6,0> - 3270280772U, // <3,2,1,7>: Cost 4 vsldoi12 LHS, <2,1,7,2> - 3222505036U, // <3,2,1,u>: Cost 3 vsldoi12 LHS, <2,1,u,1> - 4040630374U, // <3,2,2,0>: Cost 3 vsldoi4 <2,3,2,2>, LHS - 4173596192U, // <3,2,2,1>: Cost 3 vsldoi8 <2,1,3,2>, <2,1,3,2> - 3222062696U, // <3,2,2,2>: Cost 2 vsldoi12 LHS, <2,2,2,2> - 3222062706U, // <3,2,2,3>: Cost 2 vsldoi12 LHS, <2,2,3,3> - 4040633654U, // <3,2,2,4>: Cost 3 vsldoi4 <2,3,2,2>, RHS - 3368953613U, // <3,2,2,5>: Cost 4 vmrglw <2,2,3,2>, <2,4,2,5> - 3240937402U, // <3,2,2,6>: Cost 3 vmrghw <3,2,6,3>, <2,6,3,7> - 3368953777U, // <3,2,2,7>: Cost 4 vmrglw <2,2,3,2>, <2,6,2,7> - 3222505119U, // <3,2,2,u>: Cost 2 vsldoi12 LHS, <2,2,u,3> - 3222062758U, // <3,2,3,0>: Cost 2 vsldoi12 LHS, <2,3,0,1> - 3222062767U, // <3,2,3,1>: Cost 3 vsldoi12 LHS, <2,3,1,1> - 3222062777U, // <3,2,3,2>: Cost 3 vsldoi12 LHS, <2,3,2,2> - 2295218278U, // <3,2,3,3>: Cost 2 vmrglw <2,2,3,3>, LHS - 3222062798U, // <3,2,3,4>: Cost 2 vsldoi12 LHS, <2,3,4,5> - 3269838551U, // <3,2,3,5>: Cost 3 vsldoi12 LHS, <2,3,5,5> - 3241379770U, // <3,2,3,6>: Cost 3 vmrghw <3,3,3,3>, <2,6,3,7> - 3269838564U, // <3,2,3,7>: Cost 3 vsldoi12 LHS, <2,3,7,0> - 3222062830U, // <3,2,3,u>: Cost 2 vsldoi12 LHS, <2,3,u,1> - 4034674790U, // <3,2,4,0>: Cost 4 vsldoi4 <1,3,2,4>, LHS - 3362996972U, // <3,2,4,1>: Cost 4 vmrglw <1,2,3,4>, <1,0,2,1> - 3362997864U, // <3,2,4,2>: Cost 3 vmrglw <1,2,3,4>, <2,2,2,2> - 2289254502U, // <3,2,4,3>: Cost 2 vmrglw <1,2,3,4>, LHS - 3362998676U, // <3,2,4,4>: Cost 4 vmrglw <1,2,3,4>, <3,3,2,4> - 4168289590U, // <3,2,4,5>: Cost 3 vsldoi8 <1,2,3,2>, RHS - 3242215354U, // <3,2,4,6>: Cost 3 vmrghw <3,4,5,6>, <2,6,3,7> - 4070511864U, // <3,2,4,7>: Cost 4 vsldoi4 <7,3,2,4>, <7,3,2,4> - 2289254507U, // <3,2,4,u>: Cost 2 vmrglw <1,2,3,4>, LHS - 4040654950U, // <3,2,5,0>: Cost 4 vsldoi4 <2,3,2,5>, LHS - 3368313985U, // <3,2,5,1>: Cost 4 vmrglw <2,1,3,5>, <1,5,2,1> - 3368314472U, // <3,2,5,2>: Cost 4 vmrglw <2,1,3,5>, <2,2,2,2> - 3226707816U, // <3,2,5,3>: Cost 3 vsldoi12 LHS, <2,5,3,6> - 4040658230U, // <3,2,5,4>: Cost 4 vsldoi4 <2,3,2,5>, RHS - 3242952552U, // <3,2,5,5>: Cost 4 vmrghw <3,5,6,6>, <2,5,3,6> - 3243026362U, // <3,2,5,6>: Cost 4 vmrghw <3,5,7,6>, <2,6,3,7> - 3370305457U, // <3,2,5,7>: Cost 5 vmrglw <2,4,3,5>, <2,6,2,7> - 3222505365U, // <3,2,5,u>: Cost 3 vsldoi12 LHS, <2,5,u,6> - 4040663142U, // <3,2,6,0>: Cost 3 vsldoi4 <2,3,2,6>, LHS - 4040663860U, // <3,2,6,1>: Cost 4 vsldoi4 <2,3,2,6>, <1,1,1,1> - 4040664765U, // <3,2,6,2>: Cost 3 vsldoi4 <2,3,2,6>, <2,3,2,6> - 3222063034U, // <3,2,6,3>: Cost 2 vsldoi12 LHS, <2,6,3,7> - 4040666422U, // <3,2,6,4>: Cost 3 vsldoi4 <2,3,2,6>, RHS - 3370976956U, // <3,2,6,5>: Cost 4 vmrglw <2,5,3,6>, <2,3,2,5> - 3243698106U, // <3,2,6,6>: Cost 3 vmrghw <3,6,7,7>, <2,6,3,7> - 4201468778U, // <3,2,6,7>: Cost 4 vsldoi8 <6,7,3,2>, <6,7,3,2> - 3222505447U, // <3,2,6,u>: Cost 2 vsldoi12 LHS, <2,6,u,7> - 3269838826U, // <3,2,7,0>: Cost 3 vsldoi12 LHS, <2,7,0,1> - 3371647724U, // <3,2,7,1>: Cost 4 vmrglw <2,6,3,7>, <1,0,2,1> - 3371648616U, // <3,2,7,2>: Cost 3 vmrglw <2,6,3,7>, <2,2,2,2> - 2297905254U, // <3,2,7,3>: Cost 2 vmrglw <2,6,3,7>, LHS - 4040674614U, // <3,2,7,4>: Cost 4 vsldoi4 <2,3,2,7>, RHS - 3371648052U, // <3,2,7,5>: Cost 4 vmrglw <2,6,3,7>, <1,4,2,5> - 3371648701U, // <3,2,7,6>: Cost 3 vmrglw <2,6,3,7>, <2,3,2,6> - 3371648702U, // <3,2,7,7>: Cost 4 vmrglw <2,6,3,7>, <2,3,2,7> - 2297905259U, // <3,2,7,u>: Cost 2 vmrglw <2,6,3,7>, LHS - 3222505531U, // <3,2,u,0>: Cost 2 vsldoi12 LHS, <2,u,0,1> - 3222505540U, // <3,2,u,1>: Cost 3 vsldoi12 LHS, <2,u,1,1> - 3222062696U, // <3,2,u,2>: Cost 2 vsldoi12 LHS, <2,2,2,2> - 3222063192U, // <3,2,u,3>: Cost 2 vsldoi12 LHS, <2,u,3,3> - 3222505571U, // <3,2,u,4>: Cost 2 vsldoi12 LHS, <2,u,4,5> - 4168292506U, // <3,2,u,5>: Cost 3 vsldoi8 <1,2,3,2>, RHS - 3244541882U, // <3,2,u,6>: Cost 3 vmrghw <3,u,1,2>, <2,6,3,7> - 3270281337U, // <3,2,u,7>: Cost 3 vsldoi12 LHS, <2,u,7,0> - 3222505603U, // <3,2,u,u>: Cost 2 vsldoi12 LHS, <2,u,u,1> - 2289222550U, // <3,3,0,0>: Cost 2 vmrglw <1,2,3,0>, <1,2,3,0> - 3222063254U, // <3,3,0,1>: Cost 2 vsldoi12 LHS, <3,0,1,2> - 4040689344U, // <3,3,0,2>: Cost 3 vsldoi4 <2,3,3,0>, <2,3,3,0> - 3362965106U, // <3,3,0,3>: Cost 3 vmrglw <1,2,3,0>, <2,2,3,3> - 3222063280U, // <3,3,0,4>: Cost 3 vsldoi12 LHS, <3,0,4,1> - 3362965027U, // <3,3,0,5>: Cost 4 vmrglw <1,2,3,0>, <2,1,3,5> - 3362965352U, // <3,3,0,6>: Cost 4 vmrglw <1,2,3,0>, <2,5,3,6> - 3362965434U, // <3,3,0,7>: Cost 3 vmrglw <1,2,3,0>, <2,6,3,7> - 3222063317U, // <3,3,0,u>: Cost 2 vsldoi12 LHS, <3,0,u,2> - 3226708188U, // <3,3,1,0>: Cost 4 vsldoi12 LHS, <3,1,0,0> - 3222063334U, // <3,3,1,1>: Cost 3 vsldoi12 LHS, <3,1,1,1> - 3222063345U, // <3,3,1,2>: Cost 3 vsldoi12 LHS, <3,1,2,3> - 3378899356U, // <3,3,1,3>: Cost 3 vmrglw <3,u,3,1>, <3,3,3,3> - 3226708224U, // <3,3,1,4>: Cost 4 vsldoi12 LHS, <3,1,4,0> - 3226708233U, // <3,3,1,5>: Cost 4 vsldoi12 LHS, <3,1,5,0> - 3226708243U, // <3,3,1,6>: Cost 4 vsldoi12 LHS, <3,1,6,1> - 3362973626U, // <3,3,1,7>: Cost 4 vmrglw <1,2,3,1>, <2,6,3,7> - 3222505767U, // <3,3,1,u>: Cost 3 vsldoi12 LHS, <3,1,u,3> - 4040704102U, // <3,3,2,0>: Cost 3 vsldoi4 <2,3,3,2>, LHS - 3222063417U, // <3,3,2,1>: Cost 4 vsldoi12 LHS, <3,2,1,3> - 3100526194U, // <3,3,2,2>: Cost 2 vsldoi8 <2,2,3,3>, <2,2,3,3> - 3222063432U, // <3,3,2,3>: Cost 3 vsldoi12 LHS, <3,2,3,0> - 4040707382U, // <3,3,2,4>: Cost 3 vsldoi4 <2,3,3,2>, RHS - 3222505826U, // <3,3,2,5>: Cost 4 vsldoi12 LHS, <3,2,5,u> - 3222063462U, // <3,3,2,6>: Cost 3 vsldoi12 LHS, <3,2,6,3> - 3241011567U, // <3,3,2,7>: Cost 3 vsldoi12 <3,2,7,3>, <3,2,7,3> - 3104507992U, // <3,3,2,u>: Cost 2 vsldoi8 <2,u,3,3>, <2,u,3,3> - 2972942438U, // <3,3,3,0>: Cost 2 vsldoi4 <3,3,3,3>, LHS - 3375597735U, // <3,3,3,1>: Cost 3 vmrglw <3,3,3,3>, <3,0,3,1> - 4174268738U, // <3,3,3,2>: Cost 3 vsldoi8 <2,2,3,3>, <3,2,2,3> - 1745666150U, // <3,3,3,3>: Cost 1 vspltisw3 LHS - 2972945718U, // <3,3,3,4>: Cost 2 vsldoi4 <3,3,3,3>, RHS - 3375598063U, // <3,3,3,5>: Cost 3 vmrglw <3,3,3,3>, <3,4,3,5> - 4174269075U, // <3,3,3,6>: Cost 3 vsldoi8 <2,2,3,3>, <3,6,3,7> - 3368961978U, // <3,3,3,7>: Cost 3 vmrglw <2,2,3,3>, <2,6,3,7> - 1745666150U, // <3,3,3,u>: Cost 1 vspltisw3 LHS - 3362997142U, // <3,3,4,0>: Cost 3 vmrglw <1,2,3,4>, <1,2,3,0> - 4040721306U, // <3,3,4,1>: Cost 3 vsldoi4 <2,3,3,4>, <1,2,3,4> - 4040722116U, // <3,3,4,2>: Cost 3 vsldoi4 <2,3,3,4>, <2,3,3,4> - 3362997874U, // <3,3,4,3>: Cost 3 vmrglw <1,2,3,4>, <2,2,3,3> - 2289255322U, // <3,3,4,4>: Cost 2 vmrglw <1,2,3,4>, <1,2,3,4> - 3222505986U, // <3,3,4,5>: Cost 2 vsldoi12 LHS, <3,4,5,6> - 3362998120U, // <3,3,4,6>: Cost 4 vmrglw <1,2,3,4>, <2,5,3,6> - 3362998202U, // <3,3,4,7>: Cost 3 vmrglw <1,2,3,4>, <2,6,3,7> - 3222506013U, // <3,3,4,u>: Cost 2 vsldoi12 LHS, <3,4,u,6> - 3227150881U, // <3,3,5,0>: Cost 4 vsldoi12 LHS, <3,5,0,1> - 3376277671U, // <3,3,5,1>: Cost 4 vmrglw <3,4,3,5>, <3,0,3,1> - 4174270196U, // <3,3,5,2>: Cost 4 vsldoi8 <2,2,3,3>, <5,2,2,3> - 3376277916U, // <3,3,5,3>: Cost 3 vmrglw <3,4,3,5>, <3,3,3,3> - 3227150921U, // <3,3,5,4>: Cost 4 vsldoi12 LHS, <3,5,4,5> - 3368314403U, // <3,3,5,5>: Cost 3 vmrglw <2,1,3,5>, <2,1,3,5> - 3270281821U, // <3,3,5,6>: Cost 3 vsldoi12 LHS, <3,5,6,7> - 3368314810U, // <3,3,5,7>: Cost 4 vmrglw <2,1,3,5>, <2,6,3,7> - 3270281839U, // <3,3,5,u>: Cost 3 vsldoi12 LHS, <3,5,u,7> - 3269839480U, // <3,3,6,0>: Cost 3 vsldoi12 LHS, <3,6,0,7> - 3243182321U, // <3,3,6,1>: Cost 4 vmrghw <3,6,0,7>, <3,1,2,3> - 3258927754U, // <3,3,6,2>: Cost 3 vsldoi12 <6,2,7,3>, <3,6,2,7> - 3234744979U, // <3,3,6,3>: Cost 3 vsldoi12 <2,2,3,3>, <3,6,3,7> - 3269839516U, // <3,3,6,4>: Cost 3 vsldoi12 LHS, <3,6,4,7> - 3269839525U, // <3,3,6,5>: Cost 4 vsldoi12 LHS, <3,6,5,7> - 3370977128U, // <3,3,6,6>: Cost 3 vmrglw <2,5,3,6>, <2,5,3,6> - 4201476971U, // <3,3,6,7>: Cost 3 vsldoi8 <6,7,3,3>, <6,7,3,3> - 4202140604U, // <3,3,6,u>: Cost 3 vsldoi8 <6,u,3,3>, <6,u,3,3> - 4040745062U, // <3,3,7,0>: Cost 3 vsldoi4 <2,3,3,7>, LHS - 4040745780U, // <3,3,7,1>: Cost 4 vsldoi4 <2,3,3,7>, <1,1,1,1> - 4040746695U, // <3,3,7,2>: Cost 3 vsldoi4 <2,3,3,7>, <2,3,3,7> - 3371648626U, // <3,3,7,3>: Cost 3 vmrglw <2,6,3,7>, <2,2,3,3> - 4040748342U, // <3,3,7,4>: Cost 3 vsldoi4 <2,3,3,7>, RHS - 3371648547U, // <3,3,7,5>: Cost 4 vmrglw <2,6,3,7>, <2,1,3,5> - 3371648548U, // <3,3,7,6>: Cost 4 vmrglw <2,6,3,7>, <2,1,3,6> - 2297907130U, // <3,3,7,7>: Cost 2 vmrglw <2,6,3,7>, <2,6,3,7> - 2297907130U, // <3,3,7,u>: Cost 2 vmrglw <2,6,3,7>, <2,6,3,7> - 2289222550U, // <3,3,u,0>: Cost 2 vmrglw <1,2,3,0>, <1,2,3,0> - 3222506270U, // <3,3,u,1>: Cost 2 vsldoi12 LHS, <3,u,1,2> - 3136362376U, // <3,3,u,2>: Cost 2 vsldoi8 , - 1745666150U, // <3,3,u,3>: Cost 1 vspltisw3 LHS - 2972945718U, // <3,3,u,4>: Cost 2 vsldoi4 <3,3,3,3>, RHS - 3222506310U, // <3,3,u,5>: Cost 2 vsldoi12 LHS, <3,u,5,6> - 3226708812U, // <3,3,u,6>: Cost 3 vsldoi12 LHS, <3,u,6,3> - 2297907130U, // <3,3,u,7>: Cost 2 vmrglw <2,6,3,7>, <2,6,3,7> - 1745666150U, // <3,3,u,u>: Cost 1 vspltisw3 LHS - 4168302592U, // <3,4,0,0>: Cost 3 vsldoi8 <1,2,3,4>, <0,0,0,0> - 3094560870U, // <3,4,0,1>: Cost 2 vsldoi8 <1,2,3,4>, LHS - 4040763081U, // <3,4,0,2>: Cost 3 vsldoi4 <2,3,4,0>, <2,3,4,0> - 3239234692U, // <3,4,0,3>: Cost 3 vmrghw <3,0,1,2>, <4,3,5,0> - 4168302930U, // <3,4,0,4>: Cost 3 vsldoi8 <1,2,3,4>, <0,4,1,5> - 2165493046U, // <3,4,0,5>: Cost 2 vmrghw <3,0,1,2>, RHS - 3239234942U, // <3,4,0,6>: Cost 4 vmrghw <3,0,1,2>, <4,6,5,7> - 3366947484U, // <3,4,0,7>: Cost 4 vmrglw <1,u,3,0>, <3,6,4,7> - 3094561437U, // <3,4,0,u>: Cost 2 vsldoi8 <1,2,3,4>, LHS - 4040769638U, // <3,4,1,0>: Cost 3 vsldoi4 <2,3,4,1>, LHS - 4168303412U, // <3,4,1,1>: Cost 3 vsldoi8 <1,2,3,4>, <1,1,1,1> - 3094561690U, // <3,4,1,2>: Cost 2 vsldoi8 <1,2,3,4>, <1,2,3,4> - 4168303577U, // <3,4,1,3>: Cost 4 vsldoi8 <1,2,3,4>, <1,3,1,4> - 4040772918U, // <3,4,1,4>: Cost 3 vsldoi4 <2,3,4,1>, RHS - 3226708962U, // <3,4,1,5>: Cost 3 vsldoi12 LHS, <4,1,5,0> - 4168303823U, // <3,4,1,6>: Cost 4 vsldoi8 <1,2,3,4>, <1,6,1,7> - 4070634759U, // <3,4,1,7>: Cost 4 vsldoi4 <7,3,4,1>, <7,3,4,1> - 3098543488U, // <3,4,1,u>: Cost 2 vsldoi8 <1,u,3,4>, <1,u,3,4> - 4168304077U, // <3,4,2,0>: Cost 4 vsldoi8 <1,2,3,4>, <2,0,3,0> - 3227151378U, // <3,4,2,1>: Cost 4 vsldoi12 LHS, <4,2,1,3> - 4168304232U, // <3,4,2,2>: Cost 3 vsldoi8 <1,2,3,4>, <2,2,2,2> - 4168304294U, // <3,4,2,3>: Cost 3 vsldoi8 <1,2,3,4>, <2,3,0,1> - 4175603477U, // <3,4,2,4>: Cost 3 vsldoi8 <2,4,3,4>, <2,4,3,4> - 3240496438U, // <3,4,2,5>: Cost 3 vmrghw <3,2,0,3>, RHS - 4168304570U, // <3,4,2,6>: Cost 3 vsldoi8 <1,2,3,4>, <2,6,3,7> - 4177594376U, // <3,4,2,7>: Cost 3 vsldoi8 <2,7,3,4>, <2,7,3,4> - 4168304699U, // <3,4,2,u>: Cost 3 vsldoi8 <1,2,3,4>, <2,u,0,1> - 4168304790U, // <3,4,3,0>: Cost 3 vsldoi8 <1,2,3,4>, <3,0,1,2> - 4168304870U, // <3,4,3,1>: Cost 4 vsldoi8 <1,2,3,4>, <3,1,1,1> - 4168304980U, // <3,4,3,2>: Cost 3 vsldoi8 <1,2,3,4>, <3,2,4,3> - 4168305052U, // <3,4,3,3>: Cost 3 vsldoi8 <1,2,3,4>, <3,3,3,3> - 4168305104U, // <3,4,3,4>: Cost 3 vsldoi8 <1,2,3,4>, <3,4,0,1> - 2167639350U, // <3,4,3,5>: Cost 2 vmrghw <3,3,3,3>, RHS - 4168305308U, // <3,4,3,6>: Cost 3 vsldoi8 <1,2,3,4>, <3,6,4,7> - 3368962716U, // <3,4,3,7>: Cost 4 vmrglw <2,2,3,3>, <3,6,4,7> - 2167639593U, // <3,4,3,u>: Cost 2 vmrghw <3,3,3,3>, RHS - 4040794214U, // <3,4,4,0>: Cost 3 vsldoi4 <2,3,4,4>, LHS - 4040795034U, // <3,4,4,1>: Cost 3 vsldoi4 <2,3,4,4>, <1,2,3,4> - 4040795853U, // <3,4,4,2>: Cost 3 vsldoi4 <2,3,4,4>, <2,3,4,4> - 3362998612U, // <3,4,4,3>: Cost 3 vmrglw <1,2,3,4>, <3,2,4,3> - 3269840080U, // <3,4,4,4>: Cost 2 vsldoi12 LHS, <4,4,4,4> - 3094564150U, // <3,4,4,5>: Cost 2 vsldoi8 <1,2,3,4>, RHS - 3362998858U, // <3,4,4,6>: Cost 4 vmrglw <1,2,3,4>, <3,5,4,6> - 3362998940U, // <3,4,4,7>: Cost 3 vmrglw <1,2,3,4>, <3,6,4,7> - 3094564393U, // <3,4,4,u>: Cost 2 vsldoi8 <1,2,3,4>, RHS - 2967060582U, // <3,4,5,0>: Cost 2 vsldoi4 <2,3,4,5>, LHS - 4040803124U, // <3,4,5,1>: Cost 3 vsldoi4 <2,3,4,5>, <1,1,1,1> - 2967062222U, // <3,4,5,2>: Cost 2 vsldoi4 <2,3,4,5>, <2,3,4,5> - 4040804502U, // <3,4,5,3>: Cost 3 vsldoi4 <2,3,4,5>, <3,0,1,2> - 2967063862U, // <3,4,5,4>: Cost 2 vsldoi4 <2,3,4,5>, RHS - 3370305230U, // <3,4,5,5>: Cost 3 vmrglw <2,4,3,5>, <2,3,4,5> - 1074580790U, // <3,4,5,6>: Cost 1 vsldoi12 LHS, RHS - 4070667531U, // <3,4,5,7>: Cost 3 vsldoi4 <7,3,4,5>, <7,3,4,5> - 1074580808U, // <3,4,5,u>: Cost 1 vsldoi12 LHS, RHS - 4040810598U, // <3,4,6,0>: Cost 4 vsldoi4 <2,3,4,6>, LHS - 3227151706U, // <3,4,6,1>: Cost 4 vsldoi12 LHS, <4,6,1,7> - 4210110970U, // <3,4,6,2>: Cost 3 vsldoi8 , <6,2,7,3> - 3240791404U, // <3,4,6,3>: Cost 4 vsldoi12 <3,2,4,3>, <4,6,3,7> - 3269840245U, // <3,4,6,4>: Cost 3 vsldoi12 LHS, <4,6,4,7> - 3243183414U, // <3,4,6,5>: Cost 3 vmrghw <3,6,0,7>, RHS - 4210111288U, // <3,4,6,6>: Cost 3 vsldoi8 , <6,6,6,6> - 4201485164U, // <3,4,6,7>: Cost 3 vsldoi8 <6,7,3,4>, <6,7,3,4> - 3243183657U, // <3,4,6,u>: Cost 3 vmrghw <3,6,0,7>, RHS - 4210111482U, // <3,4,7,0>: Cost 3 vsldoi8 , <7,0,1,2> - 3371647013U, // <3,4,7,1>: Cost 4 vmrglw <2,6,3,7>, <0,0,4,1> - 4204139696U, // <3,4,7,2>: Cost 3 vsldoi8 <7,2,3,4>, <7,2,3,4> - 3371649364U, // <3,4,7,3>: Cost 4 vmrglw <2,6,3,7>, <3,2,4,3> - 4210111846U, // <3,4,7,4>: Cost 3 vsldoi8 , <7,4,5,6> - 3371648718U, // <3,4,7,5>: Cost 3 vmrglw <2,6,3,7>, <2,3,4,5> - 3371647180U, // <3,4,7,6>: Cost 4 vmrglw <2,6,3,7>, <0,2,4,6> - 4210112108U, // <3,4,7,7>: Cost 3 vsldoi8 , <7,7,7,7> - 3371648721U, // <3,4,7,u>: Cost 3 vmrglw <2,6,3,7>, <2,3,4,u> - 2967085158U, // <3,4,u,0>: Cost 2 vsldoi4 <2,3,4,u>, LHS - 3094566702U, // <3,4,u,1>: Cost 2 vsldoi8 <1,2,3,4>, LHS - 2967086801U, // <3,4,u,2>: Cost 2 vsldoi4 <2,3,4,u>, <2,3,4,u> - 4168308668U, // <3,4,u,3>: Cost 3 vsldoi8 <1,2,3,4>, - 2967088438U, // <3,4,u,4>: Cost 2 vsldoi4 <2,3,4,u>, RHS - 3094567066U, // <3,4,u,5>: Cost 2 vsldoi8 <1,2,3,4>, RHS - 1074581033U, // <3,4,u,6>: Cost 1 vsldoi12 LHS, RHS - 4070692110U, // <3,4,u,7>: Cost 3 vsldoi4 <7,3,4,u>, <7,3,4,u> - 1074581051U, // <3,4,u,u>: Cost 1 vsldoi12 LHS, RHS - 4052779110U, // <3,5,0,0>: Cost 3 vsldoi4 <4,3,5,0>, LHS - 3226709576U, // <3,5,0,1>: Cost 3 vsldoi12 LHS, <5,0,1,2> - 3404770843U, // <3,5,0,2>: Cost 3 vmrglw , <4,u,5,2> - 4052781206U, // <3,5,0,3>: Cost 3 vsldoi4 <4,3,5,0>, <3,0,1,2> - 3226709602U, // <3,5,0,4>: Cost 3 vsldoi12 LHS, <5,0,4,1> - 3269840491U, // <3,5,0,5>: Cost 3 vsldoi12 LHS, <5,0,5,1> - 3362966018U, // <3,5,0,6>: Cost 3 vmrglw <1,2,3,0>, <3,4,5,6> - 3362964723U, // <3,5,0,7>: Cost 4 vmrglw <1,2,3,0>, <1,6,5,7> - 3226709638U, // <3,5,0,u>: Cost 3 vsldoi12 LHS, <5,0,u,1> - 3269840527U, // <3,5,1,0>: Cost 3 vsldoi12 LHS, <5,1,0,1> - 3406769042U, // <3,5,1,1>: Cost 3 vmrglw , <4,0,5,1> - 4168311707U, // <3,5,1,2>: Cost 3 vsldoi8 <1,2,3,5>, <1,2,3,5> - 3228921518U, // <3,5,1,3>: Cost 4 vsldoi12 <1,2,5,3>, <5,1,3,5> - 3269840567U, // <3,5,1,4>: Cost 3 vsldoi12 LHS, <5,1,4,5> - 3226709691U, // <3,5,1,5>: Cost 4 vsldoi12 LHS, <5,1,5,0> - 3226709705U, // <3,5,1,6>: Cost 4 vsldoi12 LHS, <5,1,6,5> - 3269840589U, // <3,5,1,7>: Cost 4 vsldoi12 LHS, <5,1,7,0> - 3269840599U, // <3,5,1,u>: Cost 3 vsldoi12 LHS, <5,1,u,1> - 4173620671U, // <3,5,2,0>: Cost 4 vsldoi8 <2,1,3,5>, <2,0,1,4> - 4173620771U, // <3,5,2,1>: Cost 3 vsldoi8 <2,1,3,5>, <2,1,3,5> - 3226709747U, // <3,5,2,2>: Cost 4 vsldoi12 LHS, <5,2,2,2> - 4175611598U, // <3,5,2,3>: Cost 3 vsldoi8 <2,4,3,5>, <2,3,4,5> - 4175611670U, // <3,5,2,4>: Cost 3 vsldoi8 <2,4,3,5>, <2,4,3,5> - 3252809487U, // <3,5,2,5>: Cost 3 vsldoi12 <5,2,5,3>, <5,2,5,3> - 3252883224U, // <3,5,2,6>: Cost 3 vsldoi12 <5,2,6,3>, <5,2,6,3> - 3252956961U, // <3,5,2,7>: Cost 4 vsldoi12 <5,2,7,3>, <5,2,7,3> - 4178266202U, // <3,5,2,u>: Cost 3 vsldoi8 <2,u,3,5>, <2,u,3,5> - 4052803686U, // <3,5,3,0>: Cost 3 vsldoi4 <4,3,5,3>, LHS - 3404794770U, // <3,5,3,1>: Cost 3 vmrglw , <4,0,5,1> - 4034889330U, // <3,5,3,2>: Cost 4 vsldoi4 <1,3,5,3>, <2,2,3,3> - 4181584284U, // <3,5,3,3>: Cost 3 vsldoi8 <3,4,3,5>, <3,3,3,3> - 4181584367U, // <3,5,3,4>: Cost 3 vsldoi8 <3,4,3,5>, <3,4,3,5> - 3404795098U, // <3,5,3,5>: Cost 3 vmrglw , <4,4,5,5> - 3368962562U, // <3,5,3,6>: Cost 3 vmrglw <2,2,3,3>, <3,4,5,6> - 3368961267U, // <3,5,3,7>: Cost 4 vmrglw <2,2,3,3>, <1,6,5,7> - 3368962564U, // <3,5,3,u>: Cost 3 vmrglw <2,2,3,3>, <3,4,5,u> - 4052811878U, // <3,5,4,0>: Cost 3 vsldoi4 <4,3,5,4>, LHS - 3404802962U, // <3,5,4,1>: Cost 3 vmrglw , <4,0,5,1> - 3242217240U, // <3,5,4,2>: Cost 3 vmrghw <3,4,5,6>, <5,2,6,3> - 4052814338U, // <3,5,4,3>: Cost 3 vsldoi4 <4,3,5,4>, <3,4,5,6> - 4212108506U, // <3,5,4,4>: Cost 3 vsldoi8 , <4,4,5,5> - 3226709940U, // <3,5,4,5>: Cost 3 vsldoi12 LHS, <5,4,5,6> - 3362998786U, // <3,5,4,6>: Cost 3 vmrglw <1,2,3,4>, <3,4,5,6> - 3362997491U, // <3,5,4,7>: Cost 4 vmrglw <1,2,3,4>, <1,6,5,7> - 3226709967U, // <3,5,4,u>: Cost 3 vsldoi12 LHS, <5,4,u,6> - 3269840851U, // <3,5,5,0>: Cost 3 vsldoi12 LHS, <5,5,0,1> - 3269840860U, // <3,5,5,1>: Cost 3 vsldoi12 LHS, <5,5,1,1> - 4040877783U, // <3,5,5,2>: Cost 3 vsldoi4 <2,3,5,5>, <2,3,5,5> - 3228921840U, // <3,5,5,3>: Cost 4 vsldoi12 <1,2,5,3>, <5,5,3,3> - 3269840891U, // <3,5,5,4>: Cost 3 vsldoi12 LHS, <5,5,4,5> - 3269840900U, // <3,5,5,5>: Cost 2 vsldoi12 LHS, <5,5,5,5> - 3269840910U, // <3,5,5,6>: Cost 3 vsldoi12 LHS, <5,5,6,6> - 3368314099U, // <3,5,5,7>: Cost 4 vmrglw <2,1,3,5>, <1,6,5,7> - 3269840900U, // <3,5,5,u>: Cost 2 vsldoi12 LHS, <5,5,5,5> - 3269840932U, // <3,5,6,0>: Cost 3 vsldoi12 LHS, <5,6,0,1> - 3269840947U, // <3,5,6,1>: Cost 3 vsldoi12 LHS, <5,6,1,7> - 4040885976U, // <3,5,6,2>: Cost 3 vsldoi4 <2,3,5,6>, <2,3,5,6> - 3269840962U, // <3,5,6,3>: Cost 3 vsldoi12 LHS, <5,6,3,4> - 3269840972U, // <3,5,6,4>: Cost 3 vsldoi12 LHS, <5,6,4,5> - 3269840983U, // <3,5,6,5>: Cost 3 vsldoi12 LHS, <5,6,5,7> - 3370977794U, // <3,5,6,6>: Cost 3 vmrglw <2,5,3,6>, <3,4,5,6> - 3269840994U, // <3,5,6,7>: Cost 2 vsldoi12 LHS, <5,6,7,0> - 3269841003U, // <3,5,6,u>: Cost 2 vsldoi12 LHS, <5,6,u,0> - 4034920550U, // <3,5,7,0>: Cost 4 vsldoi4 <1,3,5,7>, LHS - 3407481746U, // <3,5,7,1>: Cost 3 vmrglw , <4,0,5,1> - 4034922426U, // <3,5,7,2>: Cost 4 vsldoi4 <1,3,5,7>, <2,6,3,7> - 3371647915U, // <3,5,7,3>: Cost 4 vmrglw <2,6,3,7>, <1,2,5,3> - 4034923830U, // <3,5,7,4>: Cost 4 vsldoi4 <1,3,5,7>, RHS - 3407482074U, // <3,5,7,5>: Cost 3 vmrglw , <4,4,5,5> - 3371649538U, // <3,5,7,6>: Cost 3 vmrglw <2,6,3,7>, <3,4,5,6> - 3370984691U, // <3,5,7,7>: Cost 4 vmrglw <2,5,3,7>, <1,6,5,7> - 3371649540U, // <3,5,7,u>: Cost 3 vmrglw <2,6,3,7>, <3,4,5,u> - 3269841094U, // <3,5,u,0>: Cost 3 vsldoi12 LHS, <5,u,0,1> - 3226710224U, // <3,5,u,1>: Cost 3 vsldoi12 LHS, <5,u,1,2> - 3404770843U, // <3,5,u,2>: Cost 3 vmrglw , <4,u,5,2> - 3269841124U, // <3,5,u,3>: Cost 3 vsldoi12 LHS, <5,u,3,4> - 3269841133U, // <3,5,u,4>: Cost 3 vsldoi12 LHS, <5,u,4,4> - 3269840900U, // <3,5,u,5>: Cost 2 vsldoi12 LHS, <5,5,5,5> - 3363031554U, // <3,5,u,6>: Cost 3 vmrglw <1,2,3,u>, <3,4,5,6> - 3269841156U, // <3,5,u,7>: Cost 2 vsldoi12 LHS, <5,u,7,0> - 3269841165U, // <3,5,u,u>: Cost 2 vsldoi12 LHS, <5,u,u,0> - 4176281600U, // <3,6,0,0>: Cost 4 vsldoi8 <2,5,3,6>, <0,0,0,0> - 4176281702U, // <3,6,0,1>: Cost 3 vsldoi8 <2,5,3,6>, LHS - 3258929449U, // <3,6,0,2>: Cost 3 vsldoi12 <6,2,7,3>, <6,0,2,1> - 3362965862U, // <3,6,0,3>: Cost 4 vmrglw <1,2,3,0>, <3,2,6,3> - 4176281938U, // <3,6,0,4>: Cost 4 vsldoi8 <2,5,3,6>, <0,4,1,5> - 4058828646U, // <3,6,0,5>: Cost 4 vsldoi4 <5,3,6,0>, <5,3,6,0> - 3269841229U, // <3,6,0,6>: Cost 3 vsldoi12 LHS, <6,0,6,1> - 2289225014U, // <3,6,0,7>: Cost 2 vmrglw <1,2,3,0>, RHS - 2289225015U, // <3,6,0,u>: Cost 2 vmrglw <1,2,3,0>, RHS - 3269841256U, // <3,6,1,0>: Cost 4 vsldoi12 LHS, <6,1,0,1> - 4176282420U, // <3,6,1,1>: Cost 4 vsldoi8 <2,5,3,6>, <1,1,1,1> - 4168319900U, // <3,6,1,2>: Cost 3 vsldoi8 <1,2,3,6>, <1,2,3,6> - 3226710408U, // <3,6,1,3>: Cost 5 vsldoi12 LHS, <6,1,3,6> - 3269841296U, // <3,6,1,4>: Cost 4 vsldoi12 LHS, <6,1,4,5> - 3269841306U, // <3,6,1,5>: Cost 4 vsldoi12 LHS, <6,1,5,6> - 3403453240U, // <3,6,1,6>: Cost 4 vmrglw , <6,6,6,6> - 3362975030U, // <3,6,1,7>: Cost 3 vmrglw <1,2,3,1>, RHS - 3362975031U, // <3,6,1,u>: Cost 3 vmrglw <1,2,3,1>, RHS - 4070785126U, // <3,6,2,0>: Cost 3 vsldoi4 <7,3,6,2>, LHS - 4173628964U, // <3,6,2,1>: Cost 4 vsldoi8 <2,1,3,6>, <2,1,3,6> - 4040926941U, // <3,6,2,2>: Cost 3 vsldoi4 <2,3,6,2>, <2,3,6,2> - 4174292669U, // <3,6,2,3>: Cost 4 vsldoi8 <2,2,3,6>, <2,3,2,6> - 4070788406U, // <3,6,2,4>: Cost 3 vsldoi4 <7,3,6,2>, RHS - 4176283496U, // <3,6,2,5>: Cost 3 vsldoi8 <2,5,3,6>, <2,5,3,6> - 4070789626U, // <3,6,2,6>: Cost 3 vsldoi4 <7,3,6,2>, <6,2,7,3> - 3258929658U, // <3,6,2,7>: Cost 2 vsldoi12 <6,2,7,3>, <6,2,7,3> - 3259003395U, // <3,6,2,u>: Cost 2 vsldoi12 <6,2,u,3>, <6,2,u,3> - 4176283798U, // <3,6,3,0>: Cost 4 vsldoi8 <2,5,3,6>, <3,0,1,2> - 3372942825U, // <3,6,3,1>: Cost 4 vmrglw <2,u,3,3>, <2,0,6,1> - 3241382394U, // <3,6,3,2>: Cost 3 vmrghw <3,3,3,3>, <6,2,7,3> - 3368962406U, // <3,6,3,3>: Cost 4 vmrglw <2,2,3,3>, <3,2,6,3> - 4176284162U, // <3,6,3,4>: Cost 3 vsldoi8 <2,5,3,6>, <3,4,5,6> - 4176284252U, // <3,6,3,5>: Cost 4 vsldoi8 <2,5,3,6>, <3,5,6,6> - 3404796728U, // <3,6,3,6>: Cost 3 vmrglw , <6,6,6,6> - 2295221558U, // <3,6,3,7>: Cost 2 vmrglw <2,2,3,3>, RHS - 2295221559U, // <3,6,3,u>: Cost 2 vmrglw <2,2,3,3>, RHS - 3242217761U, // <3,6,4,0>: Cost 3 vmrghw <3,4,5,6>, <6,0,1,2> - 4052886426U, // <3,6,4,1>: Cost 4 vsldoi4 <4,3,6,4>, <1,2,3,4> - 3258929777U, // <3,6,4,2>: Cost 3 vsldoi12 <6,2,7,3>, <6,4,2,5> - 3242218034U, // <3,6,4,3>: Cost 3 vmrghw <3,4,5,6>, <6,3,4,5> - 3242218125U, // <3,6,4,4>: Cost 3 vmrghw <3,4,5,6>, <6,4,5,6> - 4176284982U, // <3,6,4,5>: Cost 3 vsldoi8 <2,5,3,6>, RHS - 3269841557U, // <3,6,4,6>: Cost 3 vsldoi12 LHS, <6,4,6,5> - 2289257782U, // <3,6,4,7>: Cost 2 vmrglw <1,2,3,4>, RHS - 2289257783U, // <3,6,4,u>: Cost 2 vmrglw <1,2,3,4>, RHS - 3269841580U, // <3,6,5,0>: Cost 4 vsldoi12 LHS, <6,5,0,1> - 3372959209U, // <3,6,5,1>: Cost 5 vmrglw <2,u,3,5>, <2,0,6,1> - 3258929853U, // <3,6,5,2>: Cost 4 vsldoi12 <6,2,7,3>, <6,5,2,0> - 4176285542U, // <3,6,5,3>: Cost 4 vsldoi8 <2,5,3,6>, <5,3,6,0> - 3269841620U, // <3,6,5,4>: Cost 4 vsldoi12 LHS, <6,5,4,5> - 3269841629U, // <3,6,5,5>: Cost 4 vsldoi12 LHS, <6,5,5,5> - 3258929896U, // <3,6,5,6>: Cost 4 vsldoi12 <6,2,7,3>, <6,5,6,7> - 3368316214U, // <3,6,5,7>: Cost 3 vmrglw <2,1,3,5>, RHS - 3368316215U, // <3,6,5,u>: Cost 3 vmrglw <2,1,3,5>, RHS - 3269841661U, // <3,6,6,0>: Cost 3 vsldoi12 LHS, <6,6,0,1> - 3269841670U, // <3,6,6,1>: Cost 4 vsldoi12 LHS, <6,6,1,1> - 3258929936U, // <3,6,6,2>: Cost 3 vsldoi12 <6,2,7,3>, <6,6,2,2> - 3240940314U, // <3,6,6,3>: Cost 4 vsldoi12 <3,2,6,3>, <6,6,3,3> - 3269841701U, // <3,6,6,4>: Cost 3 vsldoi12 LHS, <6,6,4,5> - 4058877804U, // <3,6,6,5>: Cost 4 vsldoi4 <5,3,6,6>, <5,3,6,6> - 3269841720U, // <3,6,6,6>: Cost 2 vsldoi12 LHS, <6,6,6,6> - 3269841730U, // <3,6,6,7>: Cost 2 vsldoi12 LHS, <6,6,7,7> - 3269841739U, // <3,6,6,u>: Cost 2 vsldoi12 LHS, <6,6,u,7> - 3269841742U, // <3,6,7,0>: Cost 2 vsldoi12 LHS, <6,7,0,1> - 3371648489U, // <3,6,7,1>: Cost 3 vmrglw <2,6,3,7>, <2,0,6,1> - 3261879138U, // <3,6,7,2>: Cost 3 vsldoi12 <6,7,2,3>, <6,7,2,3> - 3371649382U, // <3,6,7,3>: Cost 3 vmrglw <2,6,3,7>, <3,2,6,3> - 3269841782U, // <3,6,7,4>: Cost 2 vsldoi12 LHS, <6,7,4,5> - 3371648817U, // <3,6,7,5>: Cost 3 vmrglw <2,6,3,7>, <2,4,6,5> - 3371648656U, // <3,6,7,6>: Cost 3 vmrglw <2,6,3,7>, <2,2,6,6> - 2297908534U, // <3,6,7,7>: Cost 2 vmrglw <2,6,3,7>, RHS - 2297908535U, // <3,6,7,u>: Cost 2 vmrglw <2,6,3,7>, RHS - 3269841823U, // <3,6,u,0>: Cost 2 vsldoi12 LHS, <6,u,0,1> - 4176287534U, // <3,6,u,1>: Cost 3 vsldoi8 <2,5,3,6>, LHS - 3258930097U, // <3,6,u,2>: Cost 3 vsldoi12 <6,2,7,3>, <6,u,2,1> - 3262616508U, // <3,6,u,3>: Cost 3 vsldoi12 <6,u,3,3>, <6,u,3,3> - 3269841863U, // <3,6,u,4>: Cost 2 vsldoi12 LHS, <6,u,4,5> - 4176287898U, // <3,6,u,5>: Cost 3 vsldoi8 <2,5,3,6>, RHS - 3269841720U, // <3,6,u,6>: Cost 2 vsldoi12 LHS, <6,6,6,6> - 2289290550U, // <3,6,u,7>: Cost 2 vmrglw <1,2,3,u>, RHS - 2289290551U, // <3,6,u,u>: Cost 2 vmrglw <1,2,3,u>, RHS - 4176953344U, // <3,7,0,0>: Cost 3 vsldoi8 <2,6,3,7>, <0,0,0,0> - 3103211622U, // <3,7,0,1>: Cost 2 vsldoi8 <2,6,3,7>, LHS - 4176953521U, // <3,7,0,2>: Cost 3 vsldoi8 <2,6,3,7>, <0,2,1,6> - 3404771834U, // <3,7,0,3>: Cost 3 vmrglw , <6,2,7,3> - 4176953682U, // <3,7,0,4>: Cost 3 vsldoi8 <2,6,3,7>, <0,4,1,5> - 3269841954U, // <3,7,0,5>: Cost 3 vsldoi12 LHS, <7,0,5,6> - 4064875080U, // <3,7,0,6>: Cost 3 vsldoi4 <6,3,7,0>, <6,3,7,0> - 3269841967U, // <3,7,0,7>: Cost 3 vsldoi12 LHS, <7,0,7,1> - 3103212189U, // <3,7,0,u>: Cost 2 vsldoi8 <2,6,3,7>, LHS - 4176954083U, // <3,7,1,0>: Cost 4 vsldoi8 <2,6,3,7>, <1,0,1,1> - 4176954164U, // <3,7,1,1>: Cost 3 vsldoi8 <2,6,3,7>, <1,1,1,1> - 4176954262U, // <3,7,1,2>: Cost 3 vsldoi8 <2,6,3,7>, <1,2,3,0> - 4176954332U, // <3,7,1,3>: Cost 4 vsldoi8 <2,6,3,7>, <1,3,1,7> - 4176954411U, // <3,7,1,4>: Cost 4 vsldoi8 <2,6,3,7>, <1,4,1,5> - 4176954479U, // <3,7,1,5>: Cost 4 vsldoi8 <2,6,3,7>, <1,5,0,1> - 4170982625U, // <3,7,1,6>: Cost 4 vsldoi8 <1,6,3,7>, <1,6,3,7> - 3403453250U, // <3,7,1,7>: Cost 4 vmrglw , <6,6,7,7> - 4176954748U, // <3,7,1,u>: Cost 3 vsldoi8 <2,6,3,7>, <1,u,3,0> - 4176954857U, // <3,7,2,0>: Cost 3 vsldoi8 <2,6,3,7>, <2,0,6,1> - 4173637157U, // <3,7,2,1>: Cost 4 vsldoi8 <2,1,3,7>, <2,1,3,7> - 4176954984U, // <3,7,2,2>: Cost 3 vsldoi8 <2,6,3,7>, <2,2,2,2> - 4174964423U, // <3,7,2,3>: Cost 3 vsldoi8 <2,3,3,7>, <2,3,3,7> - 4176955185U, // <3,7,2,4>: Cost 3 vsldoi8 <2,6,3,7>, <2,4,6,5> - 4176291689U, // <3,7,2,5>: Cost 4 vsldoi8 <2,5,3,7>, <2,5,3,7> - 3103213498U, // <3,7,2,6>: Cost 2 vsldoi8 <2,6,3,7>, <2,6,3,7> - 3264902355U, // <3,7,2,7>: Cost 3 vsldoi12 <7,2,7,3>, <7,2,7,3> - 3104540764U, // <3,7,2,u>: Cost 2 vsldoi8 <2,u,3,7>, <2,u,3,7> - 4176955542U, // <3,7,3,0>: Cost 3 vsldoi8 <2,6,3,7>, <3,0,1,2> - 4176955622U, // <3,7,3,1>: Cost 4 vsldoi8 <2,6,3,7>, <3,1,1,1> - 4176955750U, // <3,7,3,2>: Cost 3 vsldoi8 <2,6,3,7>, <3,2,6,3> - 4176955804U, // <3,7,3,3>: Cost 3 vsldoi8 <2,6,3,7>, <3,3,3,3> - 4176955906U, // <3,7,3,4>: Cost 3 vsldoi8 <2,6,3,7>, <3,4,5,6> - 4176956005U, // <3,7,3,5>: Cost 4 vsldoi8 <2,6,3,7>, <3,5,7,6> - 4176956087U, // <3,7,3,6>: Cost 3 vsldoi8 <2,6,3,7>, <3,6,7,7> - 4176956099U, // <3,7,3,7>: Cost 3 vsldoi8 <2,6,3,7>, <3,7,0,1> - 4176956190U, // <3,7,3,u>: Cost 3 vsldoi8 <2,6,3,7>, <3,u,1,2> - 4064903270U, // <3,7,4,0>: Cost 3 vsldoi4 <6,3,7,4>, LHS - 4176956362U, // <3,7,4,1>: Cost 4 vsldoi8 <2,6,3,7>, <4,1,2,3> - 4064905146U, // <3,7,4,2>: Cost 3 vsldoi4 <6,3,7,4>, <2,6,3,7> - 3404804602U, // <3,7,4,3>: Cost 3 vmrglw , <6,2,7,3> - 4064906550U, // <3,7,4,4>: Cost 3 vsldoi4 <6,3,7,4>, RHS - 3103214902U, // <3,7,4,5>: Cost 2 vsldoi8 <2,6,3,7>, RHS - 4064907852U, // <3,7,4,6>: Cost 3 vsldoi4 <6,3,7,4>, <6,3,7,4> - 3269842295U, // <3,7,4,7>: Cost 3 vsldoi12 LHS, <7,4,7,5> - 3103215145U, // <3,7,4,u>: Cost 2 vsldoi8 <2,6,3,7>, RHS - 4176957000U, // <3,7,5,0>: Cost 4 vsldoi8 <2,6,3,7>, <5,0,1,2> - 3269842317U, // <3,7,5,1>: Cost 4 vsldoi12 LHS, <7,5,1,0> - 4176957182U, // <3,7,5,2>: Cost 4 vsldoi8 <2,6,3,7>, <5,2,3,4> - 3258930592U, // <3,7,5,3>: Cost 4 vsldoi12 <6,2,7,3>, <7,5,3,1> - 4176957364U, // <3,7,5,4>: Cost 4 vsldoi8 <2,6,3,7>, <5,4,5,6> - 3269842358U, // <3,7,5,5>: Cost 3 vsldoi12 LHS, <7,5,5,5> - 3269842369U, // <3,7,5,6>: Cost 3 vsldoi12 LHS, <7,5,6,7> - 3269842371U, // <3,7,5,7>: Cost 4 vsldoi12 LHS, <7,5,7,0> - 3269842387U, // <3,7,5,u>: Cost 3 vsldoi12 LHS, <7,5,u,7> - 3269842396U, // <3,7,6,0>: Cost 3 vsldoi12 LHS, <7,6,0,7> - 3269842405U, // <3,7,6,1>: Cost 4 vsldoi12 LHS, <7,6,1,7> - 3258930670U, // <3,7,6,2>: Cost 3 vsldoi12 <6,2,7,3>, <7,6,2,7> - 4176958024U, // <3,7,6,3>: Cost 3 vsldoi8 <2,6,3,7>, <6,3,7,0> - 3269842432U, // <3,7,6,4>: Cost 3 vsldoi12 LHS, <7,6,4,7> - 3258930696U, // <3,7,6,5>: Cost 4 vsldoi12 <6,2,7,3>, <7,6,5,6> - 4176958264U, // <3,7,6,6>: Cost 3 vsldoi8 <2,6,3,7>, <6,6,6,6> - 3269842452U, // <3,7,6,7>: Cost 3 vsldoi12 LHS, <7,6,7,0> - 3262912036U, // <3,7,6,u>: Cost 3 vsldoi12 <6,u,7,3>, <7,6,u,7> - 4047011942U, // <3,7,7,0>: Cost 3 vsldoi4 <3,3,7,7>, LHS - 3371649227U, // <3,7,7,1>: Cost 4 vmrglw <2,6,3,7>, <3,0,7,1> - 4047013818U, // <3,7,7,2>: Cost 3 vsldoi4 <3,3,7,7>, <2,6,3,7> - 3371649391U, // <3,7,7,3>: Cost 3 vmrglw <2,6,3,7>, <3,2,7,3> - 4047015222U, // <3,7,7,4>: Cost 3 vsldoi4 <3,3,7,7>, RHS - 3371649312U, // <3,7,7,5>: Cost 4 vmrglw <2,6,3,7>, <3,1,7,5> - 4064932431U, // <3,7,7,6>: Cost 3 vsldoi4 <6,3,7,7>, <6,3,7,7> - 3269842540U, // <3,7,7,7>: Cost 2 vsldoi12 LHS, <7,7,7,7> - 3269842540U, // <3,7,7,u>: Cost 2 vsldoi12 LHS, <7,7,7,7> - 4176959187U, // <3,7,u,0>: Cost 3 vsldoi8 <2,6,3,7>, - 3103217454U, // <3,7,u,1>: Cost 2 vsldoi8 <2,6,3,7>, LHS - 4176959365U, // <3,7,u,2>: Cost 3 vsldoi8 <2,6,3,7>, - 4176959420U, // <3,7,u,3>: Cost 3 vsldoi8 <2,6,3,7>, - 4176959551U, // <3,7,u,4>: Cost 3 vsldoi8 <2,6,3,7>, - 3103217818U, // <3,7,u,5>: Cost 2 vsldoi8 <2,6,3,7>, RHS - 3139049680U, // <3,7,u,6>: Cost 2 vsldoi8 , - 3269842540U, // <3,7,u,7>: Cost 2 vsldoi12 LHS, <7,7,7,7> - 3103218021U, // <3,7,u,u>: Cost 2 vsldoi8 <2,6,3,7>, LHS - 3222061056U, // <3,u,0,0>: Cost 2 vsldoi12 LHS, <0,0,0,0> - 3222509267U, // <3,u,0,1>: Cost 2 vsldoi12 LHS, - 3362963611U, // <3,u,0,2>: Cost 3 vmrglw <1,2,3,0>, <0,1,u,2> - 2289221788U, // <3,u,0,3>: Cost 2 vmrglw <1,2,3,0>, LHS - 3222509293U, // <3,u,0,4>: Cost 3 vsldoi12 LHS, - 2165495962U, // <3,u,0,5>: Cost 2 vmrghw <3,0,1,2>, RHS - 3362966045U, // <3,u,0,6>: Cost 3 vmrglw <1,2,3,0>, <3,4,u,6> - 2289225032U, // <3,u,0,7>: Cost 2 vmrglw <1,2,3,0>, RHS - 3222509330U, // <3,u,0,u>: Cost 2 vsldoi12 LHS, - 2967322726U, // <3,u,1,0>: Cost 2 vsldoi4 <2,3,u,1>, LHS - 3222061876U, // <3,u,1,1>: Cost 2 vsldoi12 LHS, <1,1,1,1> - 1074583342U, // <3,u,1,2>: Cost 1 vsldoi12 LHS, LHS - 3222509365U, // <3,u,1,3>: Cost 3 vsldoi12 LHS, - 2967326006U, // <3,u,1,4>: Cost 2 vsldoi4 <2,3,u,1>, RHS - 3226711878U, // <3,u,1,5>: Cost 3 vsldoi12 LHS, - 3269842774U, // <3,u,1,6>: Cost 3 vsldoi12 LHS, - 3362975048U, // <3,u,1,7>: Cost 3 vmrglw <1,2,3,1>, RHS - 1074583396U, // <3,u,1,u>: Cost 1 vsldoi12 LHS, LHS - 4172981717U, // <3,u,2,0>: Cost 3 vsldoi8 <2,0,3,u>, <2,0,3,u> - 3227154294U, // <3,u,2,1>: Cost 3 vsldoi12 LHS, - 3100567159U, // <3,u,2,2>: Cost 2 vsldoi8 <2,2,3,u>, <2,2,3,u> - 3222509448U, // <3,u,2,3>: Cost 2 vsldoi12 LHS, - 4041076022U, // <3,u,2,4>: Cost 3 vsldoi4 <2,3,u,2>, RHS - 4176299882U, // <3,u,2,5>: Cost 3 vsldoi8 <2,5,3,u>, <2,5,3,u> - 3103221691U, // <3,u,2,6>: Cost 2 vsldoi8 <2,6,3,u>, <2,6,3,u> - 3269842860U, // <3,u,2,7>: Cost 2 vsldoi12 LHS, - 3226711989U, // <3,u,2,u>: Cost 2 vsldoi12 LHS, - 3222509500U, // <3,u,3,0>: Cost 2 vsldoi12 LHS, - 2167641902U, // <3,u,3,1>: Cost 2 vmrghw <3,3,3,3>, LHS - 3222509519U, // <3,u,3,2>: Cost 3 vsldoi12 LHS, - 1745666150U, // <3,u,3,3>: Cost 1 vspltisw3 LHS - 3222509540U, // <3,u,3,4>: Cost 2 vsldoi12 LHS, - 2167642266U, // <3,u,3,5>: Cost 2 vmrghw <3,3,3,3>, RHS - 4168338112U, // <3,u,3,6>: Cost 3 vsldoi8 <1,2,3,u>, <3,6,u,7> - 2295221576U, // <3,u,3,7>: Cost 2 vmrglw <2,2,3,3>, RHS - 1745666150U, // <3,u,3,u>: Cost 1 vspltisw3 LHS - 3362997187U, // <3,u,4,0>: Cost 3 vmrglw <1,2,3,4>, <1,2,u,0> - 2168477486U, // <3,u,4,1>: Cost 2 vmrghw <3,4,5,6>, LHS - 3362998485U, // <3,u,4,2>: Cost 3 vmrglw <1,2,3,4>, <3,0,u,2> - 2289254556U, // <3,u,4,3>: Cost 2 vmrglw <1,2,3,4>, LHS - 2289255322U, // <3,u,4,4>: Cost 2 vmrglw <1,2,3,4>, <1,2,3,4> - 3222509631U, // <3,u,4,5>: Cost 2 vsldoi12 LHS, - 3362998813U, // <3,u,4,6>: Cost 3 vmrglw <1,2,3,4>, <3,4,u,6> - 2289257800U, // <3,u,4,7>: Cost 2 vmrglw <1,2,3,4>, RHS - 3222509658U, // <3,u,4,u>: Cost 2 vsldoi12 LHS, - 2967355494U, // <3,u,5,0>: Cost 2 vsldoi4 <2,3,u,5>, LHS - 4041098036U, // <3,u,5,1>: Cost 3 vsldoi4 <2,3,u,5>, <1,1,1,1> - 2967357170U, // <3,u,5,2>: Cost 2 vsldoi4 <2,3,u,5>, <2,3,u,5> - 3222509694U, // <3,u,5,3>: Cost 3 vsldoi12 LHS, - 2967358774U, // <3,u,5,4>: Cost 2 vsldoi4 <2,3,u,5>, RHS - 3269840900U, // <3,u,5,5>: Cost 2 vsldoi12 LHS, <5,5,5,5> - 1074583706U, // <3,u,5,6>: Cost 1 vsldoi12 LHS, RHS - 3368316232U, // <3,u,5,7>: Cost 3 vmrglw <2,1,3,5>, RHS - 1074583724U, // <3,u,5,u>: Cost 1 vsldoi12 LHS, RHS - 4041105510U, // <3,u,6,0>: Cost 3 vsldoi4 <2,3,u,6>, LHS - 3227154622U, // <3,u,6,1>: Cost 3 vsldoi12 LHS, - 4041107187U, // <3,u,6,2>: Cost 3 vsldoi4 <2,3,u,6>, <2,3,u,6> - 3222509776U, // <3,u,6,3>: Cost 2 vsldoi12 LHS, - 4041108790U, // <3,u,6,4>: Cost 3 vsldoi4 <2,3,u,6>, RHS - 3243186330U, // <3,u,6,5>: Cost 3 vmrghw <3,6,0,7>, RHS - 3269841720U, // <3,u,6,6>: Cost 2 vsldoi12 LHS, <6,6,6,6> - 3269843181U, // <3,u,6,7>: Cost 2 vsldoi12 LHS, - 3226712317U, // <3,u,6,u>: Cost 2 vsldoi12 LHS, - 3269843200U, // <3,u,7,0>: Cost 2 vsldoi12 LHS, - 3371647049U, // <3,u,7,1>: Cost 3 vmrglw <2,6,3,7>, <0,0,u,1> - 4041115380U, // <3,u,7,2>: Cost 3 vsldoi4 <2,3,u,7>, <2,3,u,7> - 2297905308U, // <3,u,7,3>: Cost 2 vmrglw <2,6,3,7>, LHS - 3269843240U, // <3,u,7,4>: Cost 2 vsldoi12 LHS, - 3371647377U, // <3,u,7,5>: Cost 3 vmrglw <2,6,3,7>, <0,4,u,5> - 3371647216U, // <3,u,7,6>: Cost 3 vmrglw <2,6,3,7>, <0,2,u,6> - 2297908552U, // <3,u,7,7>: Cost 2 vmrglw <2,6,3,7>, RHS - 2297905313U, // <3,u,7,u>: Cost 2 vmrglw <2,6,3,7>, LHS - 3226712401U, // <3,u,u,0>: Cost 2 vsldoi12 LHS, - 3222509915U, // <3,u,u,1>: Cost 2 vsldoi12 LHS, - 1074583909U, // <3,u,u,2>: Cost 1 vsldoi12 LHS, LHS - 1745666150U, // <3,u,u,3>: Cost 1 vspltisw3 LHS - 3226712441U, // <3,u,u,4>: Cost 2 vsldoi12 LHS, - 3222509955U, // <3,u,u,5>: Cost 2 vsldoi12 LHS, - 1074583949U, // <3,u,u,6>: Cost 1 vsldoi12 LHS, RHS - 2289290568U, // <3,u,u,7>: Cost 2 vmrglw <1,2,3,u>, RHS - 1074583963U, // <3,u,u,u>: Cost 1 vsldoi12 LHS, LHS - 3228778496U, // <4,0,0,0>: Cost 3 vsldoi12 <1,2,3,4>, <0,0,0,0> - 2171748454U, // <4,0,0,1>: Cost 2 vmrghw <4,0,5,1>, LHS - 4053075657U, // <4,0,0,2>: Cost 4 vsldoi4 <4,4,0,0>, <2,3,4,0> - 3369675785U, // <4,0,0,3>: Cost 4 vmrglw <2,3,4,0>, <4,2,0,3> - 3221553192U, // <4,0,0,4>: Cost 3 vsldoi12 <0,0,4,4>, <0,0,4,4> - 3245490590U, // <4,0,0,5>: Cost 3 vmrghw <4,0,5,1>, <0,5,1,0> - 3245482477U, // <4,0,0,6>: Cost 4 vmrghw <4,0,5,0>, <0,6,0,7> - 3369676113U, // <4,0,0,7>: Cost 4 vmrglw <2,3,4,0>, <4,6,0,7> - 2171749021U, // <4,0,0,u>: Cost 2 vmrghw <4,0,5,1>, LHS - 4047110246U, // <4,0,1,0>: Cost 3 vsldoi4 <3,4,0,1>, LHS - 4047111066U, // <4,0,1,1>: Cost 3 vsldoi4 <3,4,0,1>, <1,2,3,4> - 3228778598U, // <4,0,1,2>: Cost 2 vsldoi12 <1,2,3,4>, LHS - 4047112656U, // <4,0,1,3>: Cost 3 vsldoi4 <3,4,0,1>, <3,4,0,1> - 4047113526U, // <4,0,1,4>: Cost 3 vsldoi4 <3,4,0,1>, RHS - 4071002214U, // <4,0,1,5>: Cost 3 vsldoi4 <7,4,0,1>, <5,6,7,4> - 4065030747U, // <4,0,1,6>: Cost 4 vsldoi4 <6,4,0,1>, <6,4,0,1> - 4071003444U, // <4,0,1,7>: Cost 3 vsldoi4 <7,4,0,1>, <7,4,0,1> - 3228778652U, // <4,0,1,u>: Cost 2 vsldoi12 <1,2,3,4>, LHS - 4047118438U, // <4,0,2,0>: Cost 4 vsldoi4 <3,4,0,2>, LHS - 3246833766U, // <4,0,2,1>: Cost 3 vmrghw <4,2,5,3>, LHS - 4174317176U, // <4,0,2,2>: Cost 4 vsldoi8 <2,2,4,0>, <2,2,4,0> - 4174980809U, // <4,0,2,3>: Cost 3 vsldoi8 <2,3,4,0>, <2,3,4,0> - 3373672105U, // <4,0,2,4>: Cost 4 vmrglw <3,0,4,2>, <2,3,0,4> - 4213466979U, // <4,0,2,5>: Cost 4 vsldoi8 , <2,5,3,1> - 4174981050U, // <4,0,2,6>: Cost 4 vsldoi8 <2,3,4,0>, <2,6,3,7> - 3386280568U, // <4,0,2,7>: Cost 5 vmrglw <5,1,4,2>, <3,6,0,7> - 4178298974U, // <4,0,2,u>: Cost 3 vsldoi8 <2,u,4,0>, <2,u,4,0> - 4035182694U, // <4,0,3,0>: Cost 4 vsldoi4 <1,4,0,3>, LHS - 3223322880U, // <4,0,3,1>: Cost 3 vsldoi12 <0,3,1,4>, <0,3,1,4> - 4174981460U, // <4,0,3,2>: Cost 4 vsldoi8 <2,3,4,0>, <3,2,4,3> - 3223322898U, // <4,0,3,3>: Cost 4 vsldoi12 <0,3,1,4>, <0,3,3,4> - 4035185974U, // <4,0,3,4>: Cost 4 vsldoi4 <1,4,0,3>, RHS - 4182280772U, // <4,0,3,5>: Cost 4 vsldoi8 <3,5,4,0>, <3,5,4,0> - 4174981788U, // <4,0,3,6>: Cost 4 vsldoi8 <2,3,4,0>, <3,6,4,7> - 4183608038U, // <4,0,3,7>: Cost 4 vsldoi8 <3,7,4,0>, <3,7,4,0> - 3223322880U, // <4,0,3,u>: Cost 3 vsldoi12 <0,3,1,4>, <0,3,1,4> - 4201524114U, // <4,0,4,0>: Cost 3 vsldoi8 <6,7,4,0>, <4,0,5,1> - 2174353510U, // <4,0,4,1>: Cost 2 vmrghw <4,4,4,4>, LHS - 3235193177U, // <4,0,4,2>: Cost 4 vsldoi12 <2,3,0,4>, <0,4,2,3> - 4174982235U, // <4,0,4,3>: Cost 4 vsldoi8 <2,3,4,0>, <4,3,0,4> - 3248095570U, // <4,0,4,4>: Cost 3 vmrghw <4,4,4,4>, <0,4,1,5> - 4174982454U, // <4,0,4,5>: Cost 3 vsldoi8 <2,3,4,0>, RHS - 4174982481U, // <4,0,4,6>: Cost 4 vsldoi8 <2,3,4,0>, <4,6,0,7> - 4071028023U, // <4,0,4,7>: Cost 4 vsldoi4 <7,4,0,4>, <7,4,0,4> - 2174354077U, // <4,0,4,u>: Cost 2 vmrghw <4,4,4,4>, LHS - 2175188992U, // <4,0,5,0>: Cost 2 vmrghw RHS, <0,0,0,0> - 1101447270U, // <4,0,5,1>: Cost 1 vmrghw RHS, LHS - 3248930989U, // <4,0,5,2>: Cost 3 vmrghw RHS, <0,2,1,2> - 4047145428U, // <4,0,5,3>: Cost 3 vsldoi4 <3,4,0,5>, <3,4,0,5> - 2175189330U, // <4,0,5,4>: Cost 2 vmrghw RHS, <0,4,1,5> - 3248939490U, // <4,0,5,5>: Cost 3 vmrghw RHS, <0,5,u,5> - 3248931318U, // <4,0,5,6>: Cost 3 vmrghw RHS, <0,6,1,7> - 4071036216U, // <4,0,5,7>: Cost 3 vsldoi4 <7,4,0,5>, <7,4,0,5> - 1101447837U, // <4,0,5,u>: Cost 1 vmrghw RHS, LHS - 3249471498U, // <4,0,6,0>: Cost 4 vmrghw <4,6,5,1>, <0,0,1,1> - 3249479782U, // <4,0,6,1>: Cost 3 vmrghw <4,6,5,2>, LHS - 4201525754U, // <4,0,6,2>: Cost 4 vsldoi8 <6,7,4,0>, <6,2,7,3> - 4198871597U, // <4,0,6,3>: Cost 4 vsldoi8 <6,3,4,0>, <6,3,4,0> - 3230548497U, // <4,0,6,4>: Cost 4 vsldoi12 <1,5,0,4>, <0,6,4,7> - 4201525995U, // <4,0,6,5>: Cost 4 vsldoi8 <6,7,4,0>, <6,5,7,1> - 3249513012U, // <4,0,6,6>: Cost 4 vmrghw <4,6,5,6>, <0,6,u,6> - 4201526129U, // <4,0,6,7>: Cost 3 vsldoi8 <6,7,4,0>, <6,7,4,0> - 3249480349U, // <4,0,6,u>: Cost 3 vmrghw <4,6,5,2>, LHS - 3377692672U, // <4,0,7,0>: Cost 4 vmrglw <3,6,4,7>, <0,0,0,0> - 3250126950U, // <4,0,7,1>: Cost 3 vmrghw <4,7,5,0>, LHS - 4178302154U, // <4,0,7,2>: Cost 5 vsldoi8 <2,u,4,0>, <7,2,6,3> - 4204844294U, // <4,0,7,3>: Cost 4 vsldoi8 <7,3,4,0>, <7,3,4,0> - 3250127186U, // <4,0,7,4>: Cost 4 vmrghw <4,7,5,0>, <0,4,1,5> - 4206171560U, // <4,0,7,5>: Cost 4 vsldoi8 <7,5,4,0>, <7,5,4,0> - 3250127350U, // <4,0,7,6>: Cost 5 vmrghw <4,7,5,0>, <0,6,1,7> - 4201526892U, // <4,0,7,7>: Cost 4 vsldoi8 <6,7,4,0>, <7,7,7,7> - 3250127517U, // <4,0,7,u>: Cost 3 vmrghw <4,7,5,0>, LHS - 2177179648U, // <4,0,u,0>: Cost 2 vmrghw RHS, <0,0,0,0> - 1103437926U, // <4,0,u,1>: Cost 1 vmrghw RHS, LHS - 3228779165U, // <4,0,u,2>: Cost 2 vsldoi12 <1,2,3,4>, LHS - 4047170007U, // <4,0,u,3>: Cost 3 vsldoi4 <3,4,0,u>, <3,4,0,u> - 2177179986U, // <4,0,u,4>: Cost 2 vmrghw RHS, <0,4,1,5> - 4174985370U, // <4,0,u,5>: Cost 3 vsldoi8 <2,3,4,0>, RHS - 3250921974U, // <4,0,u,6>: Cost 3 vmrghw RHS, <0,6,1,7> - 4071060795U, // <4,0,u,7>: Cost 3 vsldoi4 <7,4,0,u>, <7,4,0,u> - 1103438493U, // <4,0,u,u>: Cost 1 vmrghw RHS, LHS - 4077035622U, // <4,1,0,0>: Cost 3 vsldoi4 , LHS - 4166361190U, // <4,1,0,1>: Cost 3 vsldoi8 <0,u,4,1>, LHS - 3245204378U, // <4,1,0,2>: Cost 3 vmrghw <4,0,1,2>, <1,2,3,4> - 4047178200U, // <4,1,0,3>: Cost 4 vsldoi4 <3,4,1,0>, <3,4,1,0> - 4166361426U, // <4,1,0,4>: Cost 3 vsldoi8 <0,u,4,1>, <0,4,1,5> - 3361046866U, // <4,1,0,5>: Cost 4 vmrglw <0,u,4,0>, <0,4,1,5> - 4077040122U, // <4,1,0,6>: Cost 4 vsldoi4 , <6,2,7,3> - 4077040634U, // <4,1,0,7>: Cost 4 vsldoi4 , <7,0,1,2> - 4166361773U, // <4,1,0,u>: Cost 3 vsldoi8 <0,u,4,1>, <0,u,4,1> - 4167025406U, // <4,1,1,0>: Cost 4 vsldoi8 <1,0,4,1>, <1,0,4,1> - 3227968311U, // <4,1,1,1>: Cost 3 vsldoi12 <1,1,1,4>, <1,1,1,4> - 4174988186U, // <4,1,1,2>: Cost 3 vsldoi8 <2,3,4,1>, <1,2,3,4> - 3361057810U, // <4,1,1,3>: Cost 4 vmrglw <0,u,4,1>, <4,2,1,3> - 3223323474U, // <4,1,1,4>: Cost 4 vsldoi12 <0,3,1,4>, <1,1,4,4> - 3361055058U, // <4,1,1,5>: Cost 3 vmrglw <0,u,4,1>, <0,4,1,5> - 4166362355U, // <4,1,1,6>: Cost 4 vsldoi8 <0,u,4,1>, <1,6,5,7> - 3361058138U, // <4,1,1,7>: Cost 4 vmrglw <0,u,4,1>, <4,6,1,7> - 3246392704U, // <4,1,1,u>: Cost 3 vmrghw <4,1,u,3>, <1,u,3,4> - 4047192166U, // <4,1,2,0>: Cost 3 vsldoi4 <3,4,1,2>, LHS - 4047192986U, // <4,1,2,1>: Cost 3 vsldoi4 <3,4,1,2>, <1,2,3,4> - 4166362728U, // <4,1,2,2>: Cost 4 vsldoi8 <0,u,4,1>, <2,2,2,2> - 3228779418U, // <4,1,2,3>: Cost 2 vsldoi12 <1,2,3,4>, <1,2,3,4> - 4047195446U, // <4,1,2,4>: Cost 3 vsldoi4 <3,4,1,2>, RHS - 3361063250U, // <4,1,2,5>: Cost 4 vmrglw <0,u,4,2>, <0,4,1,5> - 4166363066U, // <4,1,2,6>: Cost 4 vsldoi8 <0,u,4,1>, <2,6,3,7> - 4071085374U, // <4,1,2,7>: Cost 4 vsldoi4 <7,4,1,2>, <7,4,1,2> - 3229148103U, // <4,1,2,u>: Cost 2 vsldoi12 <1,2,u,4>, <1,2,u,4> - 4178970800U, // <4,1,3,0>: Cost 3 vsldoi8 <3,0,4,1>, <3,0,4,1> - 3228779481U, // <4,1,3,1>: Cost 4 vsldoi12 <1,2,3,4>, <1,3,1,4> - 3229369314U, // <4,1,3,2>: Cost 4 vsldoi12 <1,3,2,4>, <1,3,2,4> - 4166363548U, // <4,1,3,3>: Cost 4 vsldoi8 <0,u,4,1>, <3,3,3,3> - 4184279554U, // <4,1,3,4>: Cost 3 vsldoi8 <3,u,4,1>, <3,4,5,6> - 3361071442U, // <4,1,3,5>: Cost 4 vmrglw <0,u,4,3>, <0,4,1,5> - 4174989980U, // <4,1,3,6>: Cost 4 vsldoi8 <2,3,4,1>, <3,6,4,7> - 4178307779U, // <4,1,3,7>: Cost 5 vsldoi8 <2,u,4,1>, <3,7,0,1> - 4184279864U, // <4,1,3,u>: Cost 3 vsldoi8 <3,u,4,1>, <3,u,4,1> - 4077068390U, // <4,1,4,0>: Cost 3 vsldoi4 , LHS - 3248096052U, // <4,1,4,1>: Cost 3 vmrghw <4,4,4,4>, <1,1,1,1> - 3248186266U, // <4,1,4,2>: Cost 3 vmrghw <4,4,5,6>, <1,2,3,4> - 3223323708U, // <4,1,4,3>: Cost 4 vsldoi12 <0,3,1,4>, <1,4,3,4> - 4077071568U, // <4,1,4,4>: Cost 3 vsldoi4 , <4,4,4,4> - 4166364470U, // <4,1,4,5>: Cost 3 vsldoi8 <0,u,4,1>, RHS - 4166364506U, // <4,1,4,6>: Cost 4 vsldoi8 <0,u,4,1>, <4,6,1,7> - 3263136860U, // <4,1,4,7>: Cost 4 vsldoi12 <7,0,1,4>, <1,4,7,0> - 4166364713U, // <4,1,4,u>: Cost 3 vsldoi8 <0,u,4,1>, RHS - 2955559250U, // <4,1,5,0>: Cost 2 vsldoi4 <0,4,1,5>, <0,4,1,5> - 2175189812U, // <4,1,5,1>: Cost 2 vmrghw RHS, <1,1,1,1> - 2175189910U, // <4,1,5,2>: Cost 2 vmrghw RHS, <1,2,3,0> - 4029302934U, // <4,1,5,3>: Cost 3 vsldoi4 <0,4,1,5>, <3,0,1,2> - 2955562294U, // <4,1,5,4>: Cost 2 vsldoi4 <0,4,1,5>, RHS - 4029304836U, // <4,1,5,5>: Cost 3 vsldoi4 <0,4,1,5>, <5,5,5,5> - 3248932047U, // <4,1,5,6>: Cost 3 vmrghw RHS, <1,6,1,7> - 4077081594U, // <4,1,5,7>: Cost 3 vsldoi4 , <7,0,1,2> - 2955564846U, // <4,1,5,u>: Cost 2 vsldoi4 <0,4,1,5>, LHS - 4184281377U, // <4,1,6,0>: Cost 4 vsldoi8 <3,u,4,1>, <6,0,1,2> - 3228779727U, // <4,1,6,1>: Cost 4 vsldoi12 <1,2,3,4>, <1,6,1,7> - 3249152922U, // <4,1,6,2>: Cost 4 vmrghw <4,6,0,7>, <1,2,3,4> - 4184281650U, // <4,1,6,3>: Cost 4 vsldoi8 <3,u,4,1>, <6,3,4,5> - 3223323882U, // <4,1,6,4>: Cost 4 vsldoi12 <0,3,1,4>, <1,6,4,7> - 3361096018U, // <4,1,6,5>: Cost 4 vmrglw <0,u,4,6>, <0,4,1,5> - 4190917432U, // <4,1,6,6>: Cost 4 vsldoi8 <5,0,4,1>, <6,6,6,6> - 4190917454U, // <4,1,6,7>: Cost 4 vsldoi8 <5,0,4,1>, <6,7,0,1> - 3228779790U, // <4,1,6,u>: Cost 4 vsldoi12 <1,2,3,4>, <1,6,u,7> - 4202861588U, // <4,1,7,0>: Cost 3 vsldoi8 <7,0,4,1>, <7,0,4,1> - 3377692682U, // <4,1,7,1>: Cost 4 vmrglw <3,6,4,7>, <0,0,1,1> - 3377694870U, // <4,1,7,2>: Cost 4 vmrglw <3,6,4,7>, <3,0,1,2> - 4204852487U, // <4,1,7,3>: Cost 4 vsldoi8 <7,3,4,1>, <7,3,4,1> - 4208170342U, // <4,1,7,4>: Cost 3 vsldoi8 <7,u,4,1>, <7,4,5,6> - 3377693010U, // <4,1,7,5>: Cost 4 vmrglw <3,6,4,7>, <0,4,1,5> - 3365749804U, // <4,1,7,6>: Cost 5 vmrglw <1,6,4,7>, <1,4,1,6> - 4190918252U, // <4,1,7,7>: Cost 4 vsldoi8 <5,0,4,1>, <7,7,7,7> - 4208170652U, // <4,1,7,u>: Cost 3 vsldoi8 <7,u,4,1>, <7,u,4,1> - 2955583829U, // <4,1,u,0>: Cost 2 vsldoi4 <0,4,1,u>, <0,4,1,u> - 2177180468U, // <4,1,u,1>: Cost 2 vmrghw RHS, <1,1,1,1> - 2177180566U, // <4,1,u,2>: Cost 2 vmrghw RHS, <1,2,3,0> - 3232761216U, // <4,1,u,3>: Cost 2 vsldoi12 <1,u,3,4>, <1,u,3,4> - 2955586870U, // <4,1,u,4>: Cost 2 vsldoi4 <0,4,1,u>, RHS - 3358458194U, // <4,1,u,5>: Cost 3 vmrglw <0,4,4,u>, <0,4,1,5> - 3250922703U, // <4,1,u,6>: Cost 3 vmrghw RHS, <1,6,1,7> - 4077106170U, // <4,1,u,7>: Cost 3 vsldoi4 , <7,0,1,2> - 2955589422U, // <4,1,u,u>: Cost 2 vsldoi4 <0,4,1,u>, LHS - 4065165414U, // <4,2,0,0>: Cost 4 vsldoi4 <6,4,2,0>, LHS - 4166369382U, // <4,2,0,1>: Cost 4 vsldoi8 <0,u,4,2>, LHS - 3245491816U, // <4,2,0,2>: Cost 3 vmrghw <4,0,5,1>, <2,2,2,2> - 3369672806U, // <4,2,0,3>: Cost 3 vmrglw <2,3,4,0>, LHS - 4166369618U, // <4,2,0,4>: Cost 4 vsldoi8 <0,u,4,2>, <0,4,1,5> - 3245492067U, // <4,2,0,5>: Cost 3 vmrghw <4,0,5,1>, <2,5,3,1> - 3245492154U, // <4,2,0,6>: Cost 3 vmrghw <4,0,5,1>, <2,6,3,7> - 3245492202U, // <4,2,0,7>: Cost 4 vmrghw <4,0,5,1>, <2,7,0,1> - 3369672811U, // <4,2,0,u>: Cost 3 vmrglw <2,3,4,0>, LHS - 4035313766U, // <4,2,1,0>: Cost 4 vsldoi4 <1,4,2,1>, LHS - 3246147107U, // <4,2,1,1>: Cost 4 vmrghw <4,1,5,0>, <2,1,3,5> - 3361056360U, // <4,2,1,2>: Cost 4 vmrglw <0,u,4,1>, <2,2,2,2> - 3361054822U, // <4,2,1,3>: Cost 3 vmrglw <0,u,4,1>, LHS - 4191585332U, // <4,2,1,4>: Cost 4 vsldoi8 <5,1,4,2>, <1,4,2,5> - 3246147426U, // <4,2,1,5>: Cost 4 vmrghw <4,1,5,0>, <2,5,3,0> - 3234309693U, // <4,2,1,6>: Cost 4 vsldoi12 <2,1,6,4>, <2,1,6,4> - 3369682865U, // <4,2,1,7>: Cost 5 vmrglw <2,3,4,1>, <2,6,2,7> - 3361054827U, // <4,2,1,u>: Cost 3 vmrglw <0,u,4,1>, LHS - 3234678357U, // <4,2,2,0>: Cost 4 vsldoi12 <2,2,2,4>, <2,2,0,1> - 4047266714U, // <4,2,2,1>: Cost 4 vsldoi4 <3,4,2,2>, <1,2,3,4> - 3228780136U, // <4,2,2,2>: Cost 3 vsldoi12 <1,2,3,4>, <2,2,2,2> - 3228780146U, // <4,2,2,3>: Cost 3 vsldoi12 <1,2,3,4>, <2,2,3,3> - 3234678392U, // <4,2,2,4>: Cost 4 vsldoi12 <2,2,2,4>, <2,2,4,0> - 3369027341U, // <4,2,2,5>: Cost 4 vmrglw <2,2,4,2>, <2,4,2,5> - 3246860218U, // <4,2,2,6>: Cost 3 vmrghw <4,2,5,6>, <2,6,3,7> - 4071159111U, // <4,2,2,7>: Cost 4 vsldoi4 <7,4,2,2>, <7,4,2,2> - 3228780191U, // <4,2,2,u>: Cost 3 vsldoi12 <1,2,3,4>, <2,2,u,3> - 3228780198U, // <4,2,3,0>: Cost 3 vsldoi12 <1,2,3,4>, <2,3,0,1> - 3227969199U, // <4,2,3,1>: Cost 4 vsldoi12 <1,1,1,4>, <2,3,1,1> - 3228780217U, // <4,2,3,2>: Cost 4 vsldoi12 <1,2,3,4>, <2,3,2,2> - 3228780228U, // <4,2,3,3>: Cost 3 vsldoi12 <1,2,3,4>, <2,3,3,4> - 3228780233U, // <4,2,3,4>: Cost 3 vsldoi12 <1,2,3,4>, <2,3,4,0> - 3235563222U, // <4,2,3,5>: Cost 4 vsldoi12 <2,3,5,4>, <2,3,5,4> - 3247531962U, // <4,2,3,6>: Cost 4 vmrghw <4,3,5,7>, <2,6,3,7> - 3235710696U, // <4,2,3,7>: Cost 3 vsldoi12 <2,3,7,4>, <2,3,7,4> - 3228780270U, // <4,2,3,u>: Cost 3 vsldoi12 <1,2,3,4>, <2,3,u,1> - 3234678519U, // <4,2,4,0>: Cost 4 vsldoi12 <2,2,2,4>, <2,4,0,1> - 3248096803U, // <4,2,4,1>: Cost 4 vmrghw <4,4,4,4>, <2,1,3,5> - 3248096872U, // <4,2,4,2>: Cost 3 vmrghw <4,4,4,4>, <2,2,2,2> - 2308571238U, // <4,2,4,3>: Cost 2 vmrglw <4,4,4,4>, LHS - 3248097045U, // <4,2,4,4>: Cost 3 vmrghw <4,4,4,4>, <2,4,3,4> - 3248179047U, // <4,2,4,5>: Cost 3 vmrghw <4,4,5,5>, <2,5,3,5> - 3248097210U, // <4,2,4,6>: Cost 3 vmrghw <4,4,4,4>, <2,6,3,7> - 4077147193U, // <4,2,4,7>: Cost 4 vsldoi4 , <7,0,u,2> - 2308571243U, // <4,2,4,u>: Cost 2 vmrglw <4,4,4,4>, LHS - 4035346534U, // <4,2,5,0>: Cost 3 vsldoi4 <1,4,2,5>, LHS - 4035347508U, // <4,2,5,1>: Cost 3 vsldoi4 <1,4,2,5>, <1,4,2,5> - 2175190632U, // <4,2,5,2>: Cost 2 vmrghw RHS, <2,2,2,2> - 2295971942U, // <4,2,5,3>: Cost 2 vmrglw <2,3,4,5>, LHS - 4035349814U, // <4,2,5,4>: Cost 3 vsldoi4 <1,4,2,5>, RHS - 3248932712U, // <4,2,5,5>: Cost 3 vmrghw RHS, <2,5,3,6> - 2175190970U, // <4,2,5,6>: Cost 2 vmrghw RHS, <2,6,3,7> - 3248932842U, // <4,2,5,7>: Cost 3 vmrghw RHS, <2,7,0,1> - 2295971947U, // <4,2,5,u>: Cost 2 vmrglw <2,3,4,5>, LHS - 4047298662U, // <4,2,6,0>: Cost 4 vsldoi4 <3,4,2,6>, LHS - 4047299482U, // <4,2,6,1>: Cost 4 vsldoi4 <3,4,2,6>, <1,2,3,4> - 3234678705U, // <4,2,6,2>: Cost 4 vsldoi12 <2,2,2,4>, <2,6,2,7> - 3228780474U, // <4,2,6,3>: Cost 3 vsldoi12 <1,2,3,4>, <2,6,3,7> - 3234678723U, // <4,2,6,4>: Cost 4 vsldoi12 <2,2,2,4>, <2,6,4,7> - 4071190630U, // <4,2,6,5>: Cost 4 vsldoi4 <7,4,2,6>, <5,6,7,4> - 3249481658U, // <4,2,6,6>: Cost 4 vmrghw <4,6,5,2>, <2,6,3,7> - 4201542515U, // <4,2,6,7>: Cost 4 vsldoi8 <6,7,4,2>, <6,7,4,2> - 3228780519U, // <4,2,6,u>: Cost 3 vsldoi12 <1,2,3,4>, <2,6,u,7> - 3270584298U, // <4,2,7,0>: Cost 4 vsldoi12 , <2,7,0,1> - 4203533414U, // <4,2,7,1>: Cost 4 vsldoi8 <7,1,4,2>, <7,1,4,2> - 3371722344U, // <4,2,7,2>: Cost 4 vmrglw <2,6,4,7>, <2,2,2,2> - 3377692774U, // <4,2,7,3>: Cost 3 vmrglw <3,6,4,7>, LHS - 3371722346U, // <4,2,7,4>: Cost 4 vmrglw <2,6,4,7>, <2,2,2,4> - 3371722509U, // <4,2,7,5>: Cost 5 vmrglw <2,6,4,7>, <2,4,2,5> - 3250128826U, // <4,2,7,6>: Cost 4 vmrghw <4,7,5,0>, <2,6,3,7> - 3250128874U, // <4,2,7,7>: Cost 4 vmrghw <4,7,5,0>, <2,7,0,1> - 3377692779U, // <4,2,7,u>: Cost 3 vmrglw <3,6,4,7>, LHS - 3228780603U, // <4,2,u,0>: Cost 3 vsldoi12 <1,2,3,4>, <2,u,0,1> - 4035372087U, // <4,2,u,1>: Cost 3 vsldoi4 <1,4,2,u>, <1,4,2,u> - 2177181288U, // <4,2,u,2>: Cost 2 vmrghw RHS, <2,2,2,2> - 2295996518U, // <4,2,u,3>: Cost 2 vmrglw <2,3,4,u>, LHS - 3228780643U, // <4,2,u,4>: Cost 3 vsldoi12 <1,2,3,4>, <2,u,4,5> - 3250923368U, // <4,2,u,5>: Cost 3 vmrghw RHS, <2,5,3,6> - 2177181626U, // <4,2,u,6>: Cost 2 vmrghw RHS, <2,6,3,7> - 3239028861U, // <4,2,u,7>: Cost 3 vsldoi12 <2,u,7,4>, <2,u,7,4> - 2295996523U, // <4,2,u,u>: Cost 2 vmrglw <2,3,4,u>, LHS - 3245492374U, // <4,3,0,0>: Cost 3 vmrghw <4,0,5,1>, <3,0,1,2> - 3228780694U, // <4,3,0,1>: Cost 3 vsldoi12 <1,2,3,4>, <3,0,1,2> - 3245205844U, // <4,3,0,2>: Cost 4 vmrghw <4,0,1,2>, <3,2,4,3> - 3245492636U, // <4,3,0,3>: Cost 3 vmrghw <4,0,5,1>, <3,3,3,3> - 3369673626U, // <4,3,0,4>: Cost 3 vmrglw <2,3,4,0>, <1,2,3,4> - 4071215206U, // <4,3,0,5>: Cost 4 vsldoi4 <7,4,3,0>, <5,6,7,4> - 3245206172U, // <4,3,0,6>: Cost 4 vmrghw <4,0,1,2>, <3,6,4,7> - 3369674682U, // <4,3,0,7>: Cost 4 vmrglw <2,3,4,0>, <2,6,3,7> - 3228780757U, // <4,3,0,u>: Cost 3 vsldoi12 <1,2,3,4>, <3,0,u,2> - 3361055638U, // <4,3,1,0>: Cost 4 vmrglw <0,u,4,1>, <1,2,3,0> - 3227969766U, // <4,3,1,1>: Cost 4 vsldoi12 <1,1,1,4>, <3,1,1,1> - 4180312986U, // <4,3,1,2>: Cost 3 vsldoi8 <3,2,4,3>, <1,2,3,4> - 3361056370U, // <4,3,1,3>: Cost 4 vmrglw <0,u,4,1>, <2,2,3,3> - 3369681818U, // <4,3,1,4>: Cost 3 vmrglw <2,3,4,1>, <1,2,3,4> - 3361056291U, // <4,3,1,5>: Cost 4 vmrglw <0,u,4,1>, <2,1,3,5> - 3378972520U, // <4,3,1,6>: Cost 4 vmrglw <3,u,4,1>, <2,5,3,6> - 3361056698U, // <4,3,1,7>: Cost 4 vmrglw <0,u,4,1>, <2,6,3,7> - 4180312986U, // <4,3,1,u>: Cost 3 vsldoi8 <3,2,4,3>, <1,2,3,4> - 3228780848U, // <4,3,2,0>: Cost 4 vsldoi12 <1,2,3,4>, <3,2,0,3> - 4047340442U, // <4,3,2,1>: Cost 4 vsldoi4 <3,4,3,2>, <1,2,3,4> - 3228780865U, // <4,3,2,2>: Cost 4 vsldoi12 <1,2,3,4>, <3,2,2,2> - 3240724812U, // <4,3,2,3>: Cost 3 vsldoi12 <3,2,3,4>, <3,2,3,4> - 3228780884U, // <4,3,2,4>: Cost 3 vsldoi12 <1,2,3,4>, <3,2,4,3> - 3223325026U, // <4,3,2,5>: Cost 5 vsldoi12 <0,3,1,4>, <3,2,5,u> - 3228780902U, // <4,3,2,6>: Cost 4 vsldoi12 <1,2,3,4>, <3,2,6,3> - 3255617903U, // <4,3,2,7>: Cost 4 vsldoi12 <5,6,7,4>, <3,2,7,3> - 3241093497U, // <4,3,2,u>: Cost 3 vsldoi12 <3,2,u,4>, <3,2,u,4> - 3247474838U, // <4,3,3,0>: Cost 3 vmrghw <4,3,5,0>, <3,0,1,2> - 4179650819U, // <4,3,3,1>: Cost 4 vsldoi8 <3,1,4,3>, <3,1,4,3> - 4180314452U, // <4,3,3,2>: Cost 3 vsldoi8 <3,2,4,3>, <3,2,4,3> - 3228780956U, // <4,3,3,3>: Cost 3 vsldoi12 <1,2,3,4>, <3,3,3,3> - 3228780966U, // <4,3,3,4>: Cost 3 vsldoi12 <1,2,3,4>, <3,3,4,4> - 3386951446U, // <4,3,3,5>: Cost 4 vmrglw <5,2,4,3>, <2,4,3,5> - 4180314780U, // <4,3,3,6>: Cost 4 vsldoi8 <3,2,4,3>, <3,6,4,7> - 3375007674U, // <4,3,3,7>: Cost 4 vmrglw <3,2,4,3>, <2,6,3,7> - 4184296250U, // <4,3,3,u>: Cost 3 vsldoi8 <3,u,4,3>, <3,u,4,3> - 3228781008U, // <4,3,4,0>: Cost 3 vsldoi12 <1,2,3,4>, <3,4,0,1> - 3228781018U, // <4,3,4,1>: Cost 3 vsldoi12 <1,2,3,4>, <3,4,1,2> - 4041385749U, // <4,3,4,2>: Cost 3 vsldoi4 <2,4,3,4>, <2,4,3,4> - 3248097692U, // <4,3,4,3>: Cost 3 vmrghw <4,4,4,4>, <3,3,3,3> - 3228781048U, // <4,3,4,4>: Cost 3 vsldoi12 <1,2,3,4>, <3,4,4,5> - 3223325186U, // <4,3,4,5>: Cost 3 vsldoi12 <0,3,1,4>, <3,4,5,6> - 4180315500U, // <4,3,4,6>: Cost 4 vsldoi8 <3,2,4,3>, <4,6,3,7> - 3382314938U, // <4,3,4,7>: Cost 3 vmrglw <4,4,4,4>, <2,6,3,7> - 3228781080U, // <4,3,4,u>: Cost 3 vsldoi12 <1,2,3,4>, <3,4,u,1> - 2175191190U, // <4,3,5,0>: Cost 2 vmrghw RHS, <3,0,1,2> - 3248933094U, // <4,3,5,1>: Cost 3 vmrghw RHS, <3,1,1,1> - 4041393942U, // <4,3,5,2>: Cost 3 vsldoi4 <2,4,3,5>, <2,4,3,5> - 2175191452U, // <4,3,5,3>: Cost 2 vmrghw RHS, <3,3,3,3> - 2175191554U, // <4,3,5,4>: Cost 2 vmrghw RHS, <3,4,5,6> - 3369715478U, // <4,3,5,5>: Cost 3 vmrglw <2,3,4,5>, <2,4,3,5> - 3248933496U, // <4,3,5,6>: Cost 3 vmrghw RHS, <3,6,0,7> - 3369715642U, // <4,3,5,7>: Cost 3 vmrglw <2,3,4,5>, <2,6,3,7> - 2175191838U, // <4,3,5,u>: Cost 2 vmrghw RHS, <3,u,1,2> - 3228781176U, // <4,3,6,0>: Cost 4 vsldoi12 <1,2,3,4>, <3,6,0,7> - 4047373210U, // <4,3,6,1>: Cost 4 vsldoi4 <3,4,3,6>, <1,2,3,4> - 3249375572U, // <4,3,6,2>: Cost 4 vmrghw <4,6,3,7>, <3,2,4,3> - 4047374832U, // <4,3,6,3>: Cost 4 vsldoi4 <3,4,3,6>, <3,4,3,6> - 3228781212U, // <4,3,6,4>: Cost 3 vsldoi12 <1,2,3,4>, <3,6,4,7> - 3361097251U, // <4,3,6,5>: Cost 5 vmrglw <0,u,4,6>, <2,1,3,5> - 3249515181U, // <4,3,6,6>: Cost 4 vmrghw <4,6,5,6>, <3,6,6,6> - 3243674292U, // <4,3,6,7>: Cost 3 vsldoi12 <3,6,7,4>, <3,6,7,4> - 3228781212U, // <4,3,6,u>: Cost 3 vsldoi12 <1,2,3,4>, <3,6,4,7> - 3377693590U, // <4,3,7,0>: Cost 4 vmrglw <3,6,4,7>, <1,2,3,0> - 3365751680U, // <4,3,7,1>: Cost 5 vmrglw <1,6,4,7>, <4,0,3,1> - 4204205240U, // <4,3,7,2>: Cost 3 vsldoi8 <7,2,4,3>, <7,2,4,3> - 3377694322U, // <4,3,7,3>: Cost 4 vmrglw <3,6,4,7>, <2,2,3,3> - 3377693594U, // <4,3,7,4>: Cost 3 vmrglw <3,6,4,7>, <1,2,3,4> - 4077244518U, // <4,3,7,5>: Cost 4 vsldoi4 , <5,6,7,4> - 3377695216U, // <4,3,7,6>: Cost 4 vmrglw <3,6,4,7>, <3,4,3,6> - 3375703994U, // <4,3,7,7>: Cost 4 vmrglw <3,3,4,7>, <2,6,3,7> - 4208187038U, // <4,3,7,u>: Cost 3 vsldoi8 <7,u,4,3>, <7,u,4,3> - 2177181846U, // <4,3,u,0>: Cost 2 vmrghw RHS, <3,0,1,2> - 3228781342U, // <4,3,u,1>: Cost 3 vsldoi12 <1,2,3,4>, <3,u,1,2> - 4041418521U, // <4,3,u,2>: Cost 3 vsldoi4 <2,4,3,u>, <2,4,3,u> - 2177182108U, // <4,3,u,3>: Cost 2 vmrghw RHS, <3,3,3,3> - 2177182210U, // <4,3,u,4>: Cost 2 vmrghw RHS, <3,4,5,6> - 3228781382U, // <4,3,u,5>: Cost 3 vsldoi12 <1,2,3,4>, <3,u,5,6> - 3250924152U, // <4,3,u,6>: Cost 3 vmrghw RHS, <3,6,0,7> - 3369740218U, // <4,3,u,7>: Cost 3 vmrglw <2,3,4,u>, <2,6,3,7> - 2177182494U, // <4,3,u,u>: Cost 2 vmrghw RHS, <3,u,1,2> - 2171751314U, // <4,4,0,0>: Cost 2 vmrghw <4,0,5,1>, <4,0,5,1> - 3113877606U, // <4,4,0,1>: Cost 2 vsldoi8 <4,4,4,4>, LHS - 4047398605U, // <4,4,0,2>: Cost 4 vsldoi4 <3,4,4,0>, <2,3,4,4> - 3223325568U, // <4,4,0,3>: Cost 4 vsldoi12 <0,3,1,4>, <4,0,3,1> - 4187619666U, // <4,4,0,4>: Cost 3 vsldoi8 <4,4,4,4>, <0,4,1,5> - 2171751734U, // <4,4,0,5>: Cost 2 vmrghw <4,0,5,1>, RHS - 3245493625U, // <4,4,0,6>: Cost 4 vmrghw <4,0,5,1>, <4,6,5,2> - 3369675420U, // <4,4,0,7>: Cost 4 vmrglw <2,3,4,0>, <3,6,4,7> - 2171751977U, // <4,4,0,u>: Cost 2 vmrghw <4,0,5,1>, RHS - 3369682633U, // <4,4,1,0>: Cost 4 vmrglw <2,3,4,1>, <2,3,4,0> - 3361055405U, // <4,4,1,1>: Cost 3 vmrglw <0,u,4,1>, <0,u,4,1> - 3228781514U, // <4,4,1,2>: Cost 3 vsldoi12 <1,2,3,4>, <4,1,2,3> - 3369683284U, // <4,4,1,3>: Cost 4 vmrglw <2,3,4,1>, <3,2,4,3> - 3384945872U, // <4,4,1,4>: Cost 3 vmrglw <4,u,4,1>, <4,4,4,4> - 3245952310U, // <4,4,1,5>: Cost 3 vmrghw <4,1,2,3>, RHS - 4187620595U, // <4,4,1,6>: Cost 4 vsldoi8 <4,4,4,4>, <1,6,5,7> - 3369683612U, // <4,4,1,7>: Cost 4 vmrglw <2,3,4,1>, <3,6,4,7> - 3232762880U, // <4,4,1,u>: Cost 3 vsldoi12 <1,u,3,4>, <4,1,u,3> - 4047413350U, // <4,4,2,0>: Cost 4 vsldoi4 <3,4,4,2>, LHS - 4047414170U, // <4,4,2,1>: Cost 4 vsldoi4 <3,4,4,2>, <1,2,3,4> - 3246836790U, // <4,4,2,2>: Cost 3 vmrghw <4,2,5,3>, <4,2,5,3> - 4175013581U, // <4,4,2,3>: Cost 3 vsldoi8 <2,3,4,4>, <2,3,4,4> - 4187621141U, // <4,4,2,4>: Cost 3 vsldoi8 <4,4,4,4>, <2,4,3,4> - 3246837046U, // <4,4,2,5>: Cost 3 vmrghw <4,2,5,3>, RHS - 4187621306U, // <4,4,2,6>: Cost 3 vsldoi8 <4,4,4,4>, <2,6,3,7> - 3228781640U, // <4,4,2,7>: Cost 4 vsldoi12 <1,2,3,4>, <4,2,7,3> - 4178331746U, // <4,4,2,u>: Cost 3 vsldoi8 <2,u,4,4>, <2,u,4,4> - 4187621526U, // <4,4,3,0>: Cost 3 vsldoi8 <4,4,4,4>, <3,0,1,2> - 4179659012U, // <4,4,3,1>: Cost 4 vsldoi8 <3,1,4,4>, <3,1,4,4> - 3228781677U, // <4,4,3,2>: Cost 4 vsldoi12 <1,2,3,4>, <4,3,2,4> - 3375008084U, // <4,4,3,3>: Cost 3 vmrglw <3,2,4,3>, <3,2,4,3> - 4181649911U, // <4,4,3,4>: Cost 3 vsldoi8 <3,4,4,4>, <3,4,4,4> - 3247476022U, // <4,4,3,5>: Cost 3 vmrghw <4,3,5,0>, RHS - 3228781713U, // <4,4,3,6>: Cost 4 vsldoi12 <1,2,3,4>, <4,3,6,4> - 3375008412U, // <4,4,3,7>: Cost 4 vmrglw <3,2,4,3>, <3,6,4,7> - 3375008084U, // <4,4,3,u>: Cost 3 vmrglw <3,2,4,3>, <3,2,4,3> - 2979659878U, // <4,4,4,0>: Cost 2 vsldoi4 <4,4,4,4>, LHS - 3382315913U, // <4,4,4,1>: Cost 3 vmrglw <4,4,4,4>, <4,0,4,1> - 4053403240U, // <4,4,4,2>: Cost 3 vsldoi4 <4,4,4,4>, <2,2,2,2> - 4047432183U, // <4,4,4,3>: Cost 3 vsldoi4 <3,4,4,4>, <3,4,4,4> - 1369886006U, // <4,4,4,4>: Cost 1 vspltisw0 RHS - 2174356790U, // <4,4,4,5>: Cost 2 vmrghw <4,4,4,4>, RHS - 4053406202U, // <4,4,4,6>: Cost 3 vsldoi4 <4,4,4,4>, <6,2,7,3> - 4071322971U, // <4,4,4,7>: Cost 3 vsldoi4 <7,4,4,4>, <7,4,4,4> - 1369886006U, // <4,4,4,u>: Cost 1 vspltisw0 RHS - 2175191954U, // <4,4,5,0>: Cost 2 vmrghw RHS, <4,0,5,1> - 4047438746U, // <4,4,5,1>: Cost 3 vsldoi4 <3,4,4,5>, <1,2,3,4> - 3248933941U, // <4,4,5,2>: Cost 3 vmrghw RHS, <4,2,5,2> - 4047440376U, // <4,4,5,3>: Cost 3 vsldoi4 <3,4,4,5>, <3,4,4,5> - 2175192282U, // <4,4,5,4>: Cost 2 vmrghw RHS, <4,4,5,5> - 1101450550U, // <4,4,5,5>: Cost 1 vmrghw RHS, RHS - 3228781878U, // <4,4,5,6>: Cost 2 vsldoi12 <1,2,3,4>, RHS - 3248942536U, // <4,4,5,7>: Cost 3 vmrghw RHS, <4,7,5,0> - 1101450793U, // <4,4,5,u>: Cost 1 vmrghw RHS, RHS - 3249482642U, // <4,4,6,0>: Cost 4 vmrghw <4,6,5,2>, <4,0,5,1> - 4161081771U, // <4,4,6,1>: Cost 4 vsldoi8 <0,0,4,4>, <6,1,7,5> - 4187623930U, // <4,4,6,2>: Cost 3 vsldoi8 <4,4,4,4>, <6,2,7,3> - 4198904369U, // <4,4,6,3>: Cost 4 vsldoi8 <6,3,4,4>, <6,3,4,4> - 4187624093U, // <4,4,6,4>: Cost 3 vsldoi8 <4,4,4,4>, <6,4,7,4> - 3249483062U, // <4,4,6,5>: Cost 3 vmrghw <4,6,5,2>, RHS - 3249483129U, // <4,4,6,6>: Cost 3 vmrghw <4,6,5,2>, <4,6,5,2> - 4201558901U, // <4,4,6,7>: Cost 3 vsldoi8 <6,7,4,4>, <6,7,4,4> - 3249483305U, // <4,4,6,u>: Cost 3 vmrghw <4,6,5,2>, RHS - 4187624442U, // <4,4,7,0>: Cost 3 vsldoi8 <4,4,4,4>, <7,0,1,2> - 3377694410U, // <4,4,7,1>: Cost 4 vmrglw <3,6,4,7>, <2,3,4,1> - 3264613808U, // <4,4,7,2>: Cost 4 vsldoi12 <7,2,3,4>, <4,7,2,3> - 3377695060U, // <4,4,7,3>: Cost 4 vmrglw <3,6,4,7>, <3,2,4,3> - 4205540699U, // <4,4,7,4>: Cost 3 vsldoi8 <7,4,4,4>, <7,4,4,4> - 3250130230U, // <4,4,7,5>: Cost 3 vmrghw <4,7,5,0>, RHS - 3267562968U, // <4,4,7,6>: Cost 4 vsldoi12 <7,6,7,4>, <4,7,6,7> - 3377695388U, // <4,4,7,7>: Cost 3 vmrglw <3,6,4,7>, <3,6,4,7> - 3250130473U, // <4,4,7,u>: Cost 3 vmrghw <4,7,5,0>, RHS - 2177182610U, // <4,4,u,0>: Cost 2 vmrghw RHS, <4,0,5,1> - 3113883438U, // <4,4,u,1>: Cost 2 vsldoi8 <4,4,4,4>, LHS - 3250924597U, // <4,4,u,2>: Cost 3 vmrghw RHS, <4,2,5,2> - 4047464955U, // <4,4,u,3>: Cost 3 vsldoi4 <3,4,4,u>, <3,4,4,u> - 1369886006U, // <4,4,u,4>: Cost 1 vspltisw0 RHS - 1103441206U, // <4,4,u,5>: Cost 1 vmrghw RHS, RHS - 3228782121U, // <4,4,u,6>: Cost 2 vsldoi12 <1,2,3,4>, RHS - 3250925000U, // <4,4,u,7>: Cost 3 vmrghw RHS, <4,7,5,0> - 1103441449U, // <4,4,u,u>: Cost 1 vmrghw RHS, RHS - 4175020032U, // <4,5,0,0>: Cost 3 vsldoi8 <2,3,4,5>, <0,0,0,0> - 3101278310U, // <4,5,0,1>: Cost 2 vsldoi8 <2,3,4,5>, LHS - 4047472334U, // <4,5,0,2>: Cost 3 vsldoi4 <3,4,5,0>, <2,3,4,5> - 4047473148U, // <4,5,0,3>: Cost 3 vsldoi4 <3,4,5,0>, <3,4,5,0> - 4163740013U, // <4,5,0,4>: Cost 3 vsldoi8 <0,4,4,5>, <0,4,4,5> - 3245494276U, // <4,5,0,5>: Cost 3 vmrghw <4,0,5,1>, <5,5,5,5> - 4071363446U, // <4,5,0,6>: Cost 3 vsldoi4 <7,4,5,0>, <6,7,4,5> - 4071363936U, // <4,5,0,7>: Cost 3 vsldoi4 <7,4,5,0>, <7,4,5,0> - 3101278877U, // <4,5,0,u>: Cost 2 vsldoi8 <2,3,4,5>, LHS - 3361057762U, // <4,5,1,0>: Cost 4 vmrglw <0,u,4,1>, <4,1,5,0> - 4167721811U, // <4,5,1,1>: Cost 3 vsldoi8 <1,1,4,5>, <1,1,4,5> - 4175020950U, // <4,5,1,2>: Cost 3 vsldoi8 <2,3,4,5>, <1,2,3,0> - 3361055659U, // <4,5,1,3>: Cost 4 vmrglw <0,u,4,1>, <1,2,5,3> - 4163740751U, // <4,5,1,4>: Cost 4 vsldoi8 <0,4,4,5>, <1,4,5,5> - 4170376343U, // <4,5,1,5>: Cost 3 vsldoi8 <1,5,4,5>, <1,5,4,5> - 3378973186U, // <4,5,1,6>: Cost 3 vmrglw <3,u,4,1>, <3,4,5,6> - 3361055987U, // <4,5,1,7>: Cost 4 vmrglw <0,u,4,1>, <1,6,5,7> - 4172367242U, // <4,5,1,u>: Cost 3 vsldoi8 <1,u,4,5>, <1,u,4,5> - 4047487078U, // <4,5,2,0>: Cost 3 vsldoi4 <3,4,5,2>, LHS - 4163741219U, // <4,5,2,1>: Cost 4 vsldoi8 <0,4,4,5>, <2,1,3,5> - 4174358141U, // <4,5,2,2>: Cost 3 vsldoi8 <2,2,4,5>, <2,2,4,5> - 3101279950U, // <4,5,2,3>: Cost 2 vsldoi8 <2,3,4,5>, <2,3,4,5> - 4175021846U, // <4,5,2,4>: Cost 3 vsldoi8 <2,3,4,5>, <2,4,3,5> - 4175021928U, // <4,5,2,5>: Cost 4 vsldoi8 <2,3,4,5>, <2,5,3,6> - 4175022010U, // <4,5,2,6>: Cost 3 vsldoi8 <2,3,4,5>, <2,6,3,7> - 4177676306U, // <4,5,2,7>: Cost 4 vsldoi8 <2,7,4,5>, <2,7,4,5> - 3104598115U, // <4,5,2,u>: Cost 2 vsldoi8 <2,u,4,5>, <2,u,4,5> - 4175022230U, // <4,5,3,0>: Cost 3 vsldoi8 <2,3,4,5>, <3,0,1,2> - 4167723241U, // <4,5,3,1>: Cost 4 vsldoi8 <1,1,4,5>, <3,1,1,4> - 4175022412U, // <4,5,3,2>: Cost 3 vsldoi8 <2,3,4,5>, <3,2,3,4> - 4175022492U, // <4,5,3,3>: Cost 3 vsldoi8 <2,3,4,5>, <3,3,3,3> - 4175022588U, // <4,5,3,4>: Cost 3 vsldoi8 <2,3,4,5>, <3,4,5,0> - 4182321737U, // <4,5,3,5>: Cost 4 vsldoi8 <3,5,4,5>, <3,5,4,5> - 4201564852U, // <4,5,3,6>: Cost 3 vsldoi8 <6,7,4,5>, <3,6,7,4> - 4183649003U, // <4,5,3,7>: Cost 3 vsldoi8 <3,7,4,5>, <3,7,4,5> - 4175022878U, // <4,5,3,u>: Cost 3 vsldoi8 <2,3,4,5>, <3,u,1,2> - 4047503462U, // <4,5,4,0>: Cost 3 vsldoi4 <3,4,5,4>, LHS - 3382315922U, // <4,5,4,1>: Cost 3 vmrglw <4,4,4,4>, <4,0,5,1> - 4175023158U, // <4,5,4,2>: Cost 3 vsldoi8 <2,3,4,5>, <4,2,5,3> - 4047505920U, // <4,5,4,3>: Cost 3 vsldoi4 <3,4,5,4>, <3,4,5,4> - 4175023322U, // <4,5,4,4>: Cost 3 vsldoi8 <2,3,4,5>, <4,4,5,5> - 3101281590U, // <4,5,4,5>: Cost 2 vsldoi8 <2,3,4,5>, RHS - 4175023486U, // <4,5,4,6>: Cost 3 vsldoi8 <2,3,4,5>, <4,6,5,7> - 4071396708U, // <4,5,4,7>: Cost 3 vsldoi4 <7,4,5,4>, <7,4,5,4> - 3101281833U, // <4,5,4,u>: Cost 2 vsldoi8 <2,3,4,5>, RHS - 2979741798U, // <4,5,5,0>: Cost 2 vsldoi4 <4,4,5,5>, LHS - 3386306074U, // <4,5,5,1>: Cost 3 vmrglw <5,1,4,5>, <4,u,5,1> - 4053485262U, // <4,5,5,2>: Cost 3 vsldoi4 <4,4,5,5>, <2,3,4,5> - 3369716790U, // <4,5,5,3>: Cost 3 vmrglw <2,3,4,5>, <4,2,5,3> - 2979744986U, // <4,5,5,4>: Cost 2 vsldoi4 <4,4,5,5>, <4,4,5,5> - 2175201284U, // <4,5,5,5>: Cost 2 vmrghw RHS, <5,5,5,5> - 2175201378U, // <4,5,5,6>: Cost 2 vmrghw RHS, <5,6,7,0> - 3369717118U, // <4,5,5,7>: Cost 3 vmrglw <2,3,4,5>, <4,6,5,7> - 2175348996U, // <4,5,5,u>: Cost 2 vmrghw RHS, <5,u,7,0> - 2973778022U, // <4,5,6,0>: Cost 2 vsldoi4 <3,4,5,6>, LHS - 4035576912U, // <4,5,6,1>: Cost 3 vsldoi4 <1,4,5,6>, <1,4,5,6> - 4041549609U, // <4,5,6,2>: Cost 3 vsldoi4 <2,4,5,6>, <2,4,5,6> - 2973780482U, // <4,5,6,3>: Cost 2 vsldoi4 <3,4,5,6>, <3,4,5,6> - 2973781302U, // <4,5,6,4>: Cost 2 vsldoi4 <3,4,5,6>, RHS - 4047523608U, // <4,5,6,5>: Cost 3 vsldoi4 <3,4,5,6>, <5,2,6,3> - 4065440397U, // <4,5,6,6>: Cost 3 vsldoi4 <6,4,5,6>, <6,4,5,6> + 3360833536U, // <1,0,0,0>: Cost 3 vsldoi12 <0,u,1,1>, <0,0,0,0> + 3355525130U, // <1,0,0,1>: Cost 2 vsldoi12 <0,0,1,1>, <0,0,1,1> + 3222626475U, // <1,0,0,2>: Cost 4 vsldoi8 <0,2,1,0>, <0,2,1,0> + 3223290108U, // <1,0,0,3>: Cost 3 vsldoi8 <0,3,1,0>, <0,3,1,0> + 3355746341U, // <1,0,0,4>: Cost 3 vsldoi12 <0,0,4,1>, <0,0,4,1> + 3224617374U, // <1,0,0,5>: Cost 3 vsldoi8 <0,5,1,0>, <0,5,1,0> + 3239215606U, // <1,0,0,6>: Cost 4 vsldoi8 <3,0,1,0>, <0,6,1,7> + 3225944640U, // <1,0,0,7>: Cost 3 vsldoi8 <0,7,1,0>, <0,7,1,0> + 3356041289U, // <1,0,0,u>: Cost 2 vsldoi12 <0,0,u,1>, <0,0,u,1> + 3495051264U, // <1,0,1,0>: Cost 3 vmrglw <0,u,1,1>, <0,0,0,0> + 2288418918U, // <1,0,1,1>: Cost 2 vmrghw <1,1,1,1>, LHS + 3360833638U, // <1,0,1,2>: Cost 2 vsldoi12 <0,u,1,1>, LHS + 3362078972U, // <1,0,1,3>: Cost 4 vmrghw <1,1,0,0>, <0,3,1,0> + 4167396662U, // <1,0,1,4>: Cost 3 vsldoi4 <1,1,0,1>, RHS + 4191284879U, // <1,0,1,5>: Cost 3 vsldoi4 <5,1,0,1>, <5,1,0,1> + 3395928206U, // <1,0,1,6>: Cost 3 vsldoi12 <6,7,0,1>, <0,1,6,7> + 4191286266U, // <1,0,1,7>: Cost 4 vsldoi4 <5,1,0,1>, <7,0,1,2> + 3360833692U, // <1,0,1,u>: Cost 2 vsldoi12 <0,u,1,1>, LHS + 3362963456U, // <1,0,2,0>: Cost 3 vmrghw <1,2,3,0>, <0,0,0,0> + 2289221734U, // <1,0,2,1>: Cost 2 vmrghw <1,2,3,0>, LHS + 3491080252U, // <1,0,2,2>: Cost 4 vmrglw <0,2,1,2>, <2,u,0,2> + 3239216806U, // <1,0,2,3>: Cost 3 vsldoi8 <3,0,1,0>, <2,3,0,1> + 3362963794U, // <1,0,2,4>: Cost 3 vmrghw <1,2,3,0>, <0,4,1,5> + 3507669460U, // <1,0,2,5>: Cost 3 vmrglw <3,0,1,2>, <3,4,0,5> + 3223291834U, // <1,0,2,6>: Cost 4 vsldoi8 <0,3,1,0>, <2,6,3,7> + 3503688312U, // <1,0,2,7>: Cost 4 vmrglw <2,3,1,2>, <3,6,0,7> + 2289222301U, // <1,0,2,u>: Cost 2 vmrghw <1,2,3,0>, LHS + 3223292054U, // <1,0,3,0>: Cost 3 vsldoi8 <0,3,1,0>, <3,0,1,2> + 3491088038U, // <1,0,3,1>: Cost 3 vmrglw <0,2,1,3>, <2,3,0,1> + 3363414190U, // <1,0,3,2>: Cost 4 vmrghw <1,3,0,1>, <0,2,1,3> + 3223292287U, // <1,0,3,3>: Cost 4 vsldoi8 <0,3,1,0>, <3,3,0,1> + 3223292418U, // <1,0,3,4>: Cost 4 vsldoi8 <0,3,1,0>, <3,4,5,6> + 3242535465U, // <1,0,3,5>: Cost 4 vsldoi8 <3,5,1,0>, <3,5,1,0> + 3395928368U, // <1,0,3,6>: Cost 4 vsldoi12 <6,7,0,1>, <0,3,6,7> + 3501042296U, // <1,0,3,7>: Cost 5 vmrglw <1,u,1,3>, <3,6,0,7> + 3244526364U, // <1,0,3,u>: Cost 3 vsldoi8 <3,u,1,0>, <3,u,1,0> + 3271732114U, // <1,0,4,0>: Cost 3 vsldoi8 , <4,0,5,1> + 3360833874U, // <1,0,4,1>: Cost 3 vsldoi12 <0,u,1,1>, <0,4,1,5> + 3360833883U, // <1,0,4,2>: Cost 5 vsldoi12 <0,u,1,1>, <0,4,2,5> + 3364077824U, // <1,0,4,3>: Cost 4 vmrghw <1,4,0,1>, <0,3,1,4> + 3360833901U, // <1,0,4,4>: Cost 4 vsldoi12 <0,u,1,1>, <0,4,4,5> + 3223293238U, // <1,0,4,5>: Cost 3 vsldoi8 <0,3,1,0>, RHS + 3364487670U, // <1,0,4,6>: Cost 5 vmrghw <1,4,5,6>, <0,6,1,7> + 3273723336U, // <1,0,4,7>: Cost 4 vsldoi8 , <4,7,5,0> + 3223293481U, // <1,0,4,u>: Cost 3 vsldoi8 <0,3,1,0>, RHS + 3492429824U, // <1,0,5,0>: Cost 3 vmrglw <0,4,1,5>, <0,0,0,0> + 3492431526U, // <1,0,5,1>: Cost 3 vmrglw <0,4,1,5>, <2,3,0,1> + 3272396523U, // <1,0,5,2>: Cost 4 vsldoi8 , <5,2,1,3> + 3365077248U, // <1,0,5,3>: Cost 4 vmrghw <1,5,4,6>, <0,3,1,4> + 3492431529U, // <1,0,5,4>: Cost 3 vmrglw <0,4,1,5>, <2,3,0,4> + 4191317651U, // <1,0,5,5>: Cost 4 vsldoi4 <5,1,0,5>, <5,1,0,5> + 3255808098U, // <1,0,5,6>: Cost 4 vsldoi8 <5,7,1,0>, <5,6,7,0> + 3255808125U, // <1,0,5,7>: Cost 4 vsldoi8 <5,7,1,0>, <5,7,1,0> + 3492431533U, // <1,0,5,u>: Cost 3 vmrglw <0,4,1,5>, <2,3,0,u> + 3491110912U, // <1,0,6,0>: Cost 4 vmrglw <0,2,1,6>, <0,0,0,0> + 3365527654U, // <1,0,6,1>: Cost 3 vmrghw <1,6,1,7>, LHS + 3365404849U, // <1,0,6,2>: Cost 4 vmrghw <1,6,0,1>, <0,2,1,6> + 3365454076U, // <1,0,6,3>: Cost 4 vmrghw <1,6,0,7>, <0,3,1,0> + 3365822802U, // <1,0,6,4>: Cost 3 vmrghw <1,6,5,7>, <0,4,1,5> + 3271733995U, // <1,0,6,5>: Cost 4 vsldoi8 , <6,5,7,1> + 3263107896U, // <1,0,6,6>: Cost 4 vsldoi8 <7,0,1,0>, <6,6,6,6> + 3263107918U, // <1,0,6,7>: Cost 3 vsldoi8 <7,0,1,0>, <6,7,0,1> + 3365528210U, // <1,0,6,u>: Cost 3 vmrghw <1,6,1,7>, <0,u,1,1> + 3263108088U, // <1,0,7,0>: Cost 3 vsldoi8 <7,0,1,0>, <7,0,1,0> + 3493775014U, // <1,0,7,1>: Cost 3 vmrglw <0,6,1,7>, <2,3,0,1> + 3269080281U, // <1,0,7,2>: Cost 4 vsldoi8 , <7,2,u,0> + 3271070947U, // <1,0,7,3>: Cost 4 vsldoi8 , <7,3,0,1> + 3263108454U, // <1,0,7,4>: Cost 4 vsldoi8 <7,0,1,0>, <7,4,5,6> + 3266426253U, // <1,0,7,5>: Cost 4 vsldoi8 <7,5,1,0>, <7,5,1,0> + 3263108628U, // <1,0,7,6>: Cost 4 vsldoi8 <7,0,1,0>, <7,6,7,0> + 3263108716U, // <1,0,7,7>: Cost 4 vsldoi8 <7,0,1,0>, <7,7,7,7> + 3268417152U, // <1,0,7,u>: Cost 3 vsldoi8 <7,u,1,0>, <7,u,1,0> + 3492454400U, // <1,0,u,0>: Cost 3 vmrglw <0,4,1,u>, <0,0,0,0> + 3360834194U, // <1,0,u,1>: Cost 2 vsldoi12 <0,u,1,1>, <0,u,1,1> + 3360834205U, // <1,0,u,2>: Cost 2 vsldoi12 <0,u,1,1>, LHS + 3271071684U, // <1,0,u,3>: Cost 3 vsldoi8 , + 3361055405U, // <1,0,u,4>: Cost 3 vsldoi12 <0,u,4,1>, <0,u,4,1> + 3223296154U, // <1,0,u,5>: Cost 3 vsldoi8 <0,3,1,0>, RHS + 3395928206U, // <1,0,u,6>: Cost 3 vsldoi12 <6,7,0,1>, <0,1,6,7> + 3273726216U, // <1,0,u,7>: Cost 3 vsldoi8 , + 3360834259U, // <1,0,u,u>: Cost 2 vsldoi12 <0,u,1,1>, LHS + 3221307402U, // <1,1,0,0>: Cost 2 vsldoi8 <0,0,1,1>, <0,0,1,1> + 3226615910U, // <1,1,0,1>: Cost 2 vsldoi8 <0,u,1,1>, LHS + 3491727510U, // <1,1,0,2>: Cost 3 vmrglw <0,3,1,0>, <3,0,1,2> + 3491725324U, // <1,1,0,3>: Cost 4 vmrglw <0,3,1,0>, <0,0,1,3> + 3226616146U, // <1,1,0,4>: Cost 3 vsldoi8 <0,u,1,1>, <0,4,1,5> + 3491725650U, // <1,1,0,5>: Cost 4 vmrglw <0,3,1,0>, <0,4,1,5> + 3361506511U, // <1,1,0,6>: Cost 4 vmrghw <1,0,1,2>, <1,6,1,7> + 3507651062U, // <1,1,0,7>: Cost 4 vmrglw <3,0,1,0>, <0,6,1,7> + 3226616466U, // <1,1,0,u>: Cost 2 vsldoi8 <0,u,1,1>, <0,u,1,1> + 3093725286U, // <1,1,1,0>: Cost 2 vsldoi4 <1,1,1,1>, LHS + 1611448422U, // <1,1,1,1>: Cost 1 vspltisw1 LHS + 3495053462U, // <1,1,1,2>: Cost 3 vmrglw <0,u,1,1>, <3,0,1,2> + 3495052167U, // <1,1,1,3>: Cost 3 vmrglw <0,u,1,1>, <1,2,1,3> + 3093728566U, // <1,1,1,4>: Cost 2 vsldoi4 <1,1,1,1>, RHS + 3495051602U, // <1,1,1,5>: Cost 3 vmrglw <0,u,1,1>, <0,4,1,5> + 3226617039U, // <1,1,1,6>: Cost 3 vsldoi8 <0,u,1,1>, <1,6,1,7> + 4203304010U, // <1,1,1,7>: Cost 3 vsldoi4 <7,1,1,1>, <7,1,1,1> + 1611448422U, // <1,1,1,u>: Cost 1 vspltisw1 LHS + 3362964204U, // <1,1,2,0>: Cost 3 vmrghw <1,2,3,0>, <1,0,2,1> + 3360834439U, // <1,1,2,1>: Cost 3 vsldoi12 <0,u,1,1>, <1,2,1,3> + 2289222550U, // <1,1,2,2>: Cost 2 vmrghw <1,2,3,0>, <1,2,3,0> + 3226617510U, // <1,1,2,3>: Cost 3 vsldoi8 <0,u,1,1>, <2,3,0,1> + 4161506614U, // <1,1,2,4>: Cost 3 vsldoi4 <0,1,1,2>, RHS + 3507667282U, // <1,1,2,5>: Cost 3 vmrglw <3,0,1,2>, <0,4,1,5> + 3226617786U, // <1,1,2,6>: Cost 3 vsldoi8 <0,u,1,1>, <2,6,3,7> + 3495724239U, // <1,1,2,7>: Cost 4 vmrglw <1,0,1,2>, <1,6,1,7> + 2289222550U, // <1,1,2,u>: Cost 2 vmrghw <1,2,3,0>, <1,2,3,0> + 3226618006U, // <1,1,3,0>: Cost 3 vsldoi8 <0,u,1,1>, <3,0,1,2> + 3227945190U, // <1,1,3,1>: Cost 3 vsldoi8 <1,1,1,1>, <3,1,1,1> + 3491088534U, // <1,1,3,2>: Cost 4 vmrglw <0,2,1,3>, <3,0,1,2> + 3491086510U, // <1,1,3,3>: Cost 3 vmrglw <0,2,1,3>, <0,2,1,3> + 3226618370U, // <1,1,3,4>: Cost 3 vsldoi8 <0,u,1,1>, <3,4,5,6> + 3491086674U, // <1,1,3,5>: Cost 4 vmrglw <0,2,1,3>, <0,4,1,5> + 3274394232U, // <1,1,3,6>: Cost 4 vsldoi8 , <3,6,0,7> + 3497059535U, // <1,1,3,7>: Cost 4 vmrglw <1,2,1,3>, <1,6,1,7> + 3226618654U, // <1,1,3,u>: Cost 3 vsldoi8 <0,u,1,1>, <3,u,1,2> + 4167491686U, // <1,1,4,0>: Cost 3 vsldoi4 <1,1,1,4>, LHS + 3362161707U, // <1,1,4,1>: Cost 3 vsldoi12 <1,1,1,1>, <1,4,1,5> + 3364258710U, // <1,1,4,2>: Cost 3 vmrghw <1,4,2,5>, <1,2,3,0> + 4167493782U, // <1,1,4,3>: Cost 4 vsldoi4 <1,1,1,4>, <3,0,1,2> + 3491758336U, // <1,1,4,4>: Cost 3 vmrglw <0,3,1,4>, <0,3,1,4> + 3226619190U, // <1,1,4,5>: Cost 2 vsldoi8 <0,u,1,1>, RHS + 3364488399U, // <1,1,4,6>: Cost 4 vmrghw <1,4,5,6>, <1,6,1,7> + 3507683830U, // <1,1,4,7>: Cost 4 vmrglw <3,0,1,4>, <0,6,1,7> + 3226619433U, // <1,1,4,u>: Cost 2 vsldoi8 <0,u,1,1>, RHS + 3364742255U, // <1,1,5,0>: Cost 3 vsldoi12 <1,5,0,1>, <1,5,0,1> + 3492429834U, // <1,1,5,1>: Cost 3 vmrglw <0,4,1,5>, <0,0,1,1> + 3492432022U, // <1,1,5,2>: Cost 3 vmrglw <0,4,1,5>, <3,0,1,2> + 3492429998U, // <1,1,5,3>: Cost 4 vmrglw <0,4,1,5>, <0,2,1,3> + 3492429837U, // <1,1,5,4>: Cost 3 vmrglw <0,4,1,5>, <0,0,1,4> + 2418688338U, // <1,1,5,5>: Cost 2 vmrglw <0,4,1,5>, <0,4,1,5> + 3274395746U, // <1,1,5,6>: Cost 3 vsldoi8 , <5,6,7,0> + 3495085263U, // <1,1,5,7>: Cost 4 vmrglw <0,u,1,5>, <1,6,1,7> + 2418688338U, // <1,1,5,u>: Cost 2 vmrglw <0,4,1,5>, <0,4,1,5> + 4167508070U, // <1,1,6,0>: Cost 4 vsldoi4 <1,1,1,6>, LHS + 3360834767U, // <1,1,6,1>: Cost 3 vsldoi12 <0,u,1,1>, <1,6,1,7> + 3274396154U, // <1,1,6,2>: Cost 3 vsldoi8 , <6,2,7,3> + 3369387233U, // <1,1,6,3>: Cost 4 vsldoi12 <2,3,0,1>, <1,6,3,7> + 4167511350U, // <1,1,6,4>: Cost 4 vsldoi4 <1,1,1,6>, RHS + 3491111250U, // <1,1,6,5>: Cost 4 vmrglw <0,2,1,6>, <0,4,1,5> + 3491111089U, // <1,1,6,6>: Cost 3 vmrglw <0,2,1,6>, <0,2,1,6> + 3395929342U, // <1,1,6,7>: Cost 3 vsldoi12 <6,7,0,1>, <1,6,7,0> + 3396592903U, // <1,1,6,u>: Cost 3 vsldoi12 <6,u,0,1>, <1,6,u,0> + 3274396666U, // <1,1,7,0>: Cost 3 vsldoi8 , <7,0,1,2> + 3499745938U, // <1,1,7,1>: Cost 3 vmrglw <1,6,1,7>, <0,u,1,1> + 3499746020U, // <1,1,7,2>: Cost 4 vmrglw <1,6,1,7>, <1,0,1,2> + 3499746183U, // <1,1,7,3>: Cost 4 vmrglw <1,6,1,7>, <1,2,1,3> + 3274397030U, // <1,1,7,4>: Cost 3 vsldoi8 , <7,4,5,6> + 3499745618U, // <1,1,7,5>: Cost 4 vmrglw <1,6,1,7>, <0,4,1,5> + 3499746105U, // <1,1,7,6>: Cost 4 vmrglw <1,6,1,7>, <1,1,1,6> + 3499746511U, // <1,1,7,7>: Cost 3 vmrglw <1,6,1,7>, <1,6,1,7> + 3274397314U, // <1,1,7,u>: Cost 3 vsldoi8 , <7,u,1,2> + 3093725286U, // <1,1,u,0>: Cost 2 vsldoi4 <1,1,1,1>, LHS + 1611448422U, // <1,1,u,1>: Cost 1 vspltisw1 LHS + 2289222550U, // <1,1,u,2>: Cost 2 vmrghw <1,2,3,0>, <1,2,3,0> + 3226621884U, // <1,1,u,3>: Cost 3 vsldoi8 <0,u,1,1>, + 3093728566U, // <1,1,u,4>: Cost 2 vsldoi4 <1,1,1,1>, RHS + 3226622106U, // <1,1,u,5>: Cost 2 vsldoi8 <0,u,1,1>, RHS + 3226622160U, // <1,1,u,6>: Cost 3 vsldoi8 <0,u,1,1>, + 3273734409U, // <1,1,u,7>: Cost 3 vsldoi8 , + 1611448422U, // <1,1,u,u>: Cost 1 vspltisw1 LHS + 3239231488U, // <1,2,0,0>: Cost 3 vsldoi8 <3,0,1,2>, <0,0,0,0> + 3239231590U, // <1,2,0,1>: Cost 2 vsldoi8 <3,0,1,2>, LHS + 3222642861U, // <1,2,0,2>: Cost 3 vsldoi8 <0,2,1,2>, <0,2,1,2> + 3491725414U, // <1,2,0,3>: Cost 3 vmrglw <0,3,1,0>, LHS + 3239231826U, // <1,2,0,4>: Cost 3 vsldoi8 <3,0,1,2>, <0,4,1,5> + 3251175901U, // <1,2,0,5>: Cost 4 vsldoi8 <5,0,1,2>, <0,5,u,0> + 3225297393U, // <1,2,0,6>: Cost 3 vsldoi8 <0,6,1,2>, <0,6,1,2> + 3263119936U, // <1,2,0,7>: Cost 3 vsldoi8 <7,0,1,2>, <0,7,1,0> + 3239232157U, // <1,2,0,u>: Cost 2 vsldoi8 <3,0,1,2>, LHS + 3227288292U, // <1,2,1,0>: Cost 3 vsldoi8 <1,0,1,2>, <1,0,1,2> + 3239232308U, // <1,2,1,1>: Cost 3 vsldoi8 <3,0,1,2>, <1,1,1,1> + 3495052904U, // <1,2,1,2>: Cost 3 vmrglw <0,u,1,1>, <2,2,2,2> + 2421309542U, // <1,2,1,3>: Cost 2 vmrglw <0,u,1,1>, LHS + 3227288610U, // <1,2,1,4>: Cost 4 vsldoi8 <1,0,1,2>, <1,4,0,5> + 3362162536U, // <1,2,1,5>: Cost 4 vmrghw <1,1,1,1>, <2,5,3,6> + 3362162618U, // <1,2,1,6>: Cost 3 vmrghw <1,1,1,1>, <2,6,3,7> + 3263120681U, // <1,2,1,7>: Cost 4 vsldoi8 <7,0,1,2>, <1,7,2,7> + 2421309547U, // <1,2,1,u>: Cost 2 vmrglw <0,u,1,1>, LHS + 4167549030U, // <1,2,2,0>: Cost 3 vsldoi4 <1,1,2,2>, LHS + 3239233056U, // <1,2,2,1>: Cost 3 vsldoi8 <3,0,1,2>, <2,1,3,2> + 3491079784U, // <1,2,2,2>: Cost 3 vmrglw <0,2,1,2>, <2,2,2,2> + 2433925222U, // <1,2,2,3>: Cost 2 vmrglw <3,0,1,2>, LHS + 4167552310U, // <1,2,2,4>: Cost 3 vsldoi4 <1,1,2,2>, RHS + 3491078491U, // <1,2,2,5>: Cost 4 vmrglw <0,2,1,2>, <0,4,2,5> + 3362965434U, // <1,2,2,6>: Cost 3 vmrghw <1,2,3,0>, <2,6,3,7> + 3507668184U, // <1,2,2,7>: Cost 3 vmrglw <3,0,1,2>, <1,6,2,7> + 2433925227U, // <1,2,2,u>: Cost 2 vmrglw <3,0,1,2>, LHS + 2014101606U, // <1,2,3,0>: Cost 1 vsldoi4 LHS, LHS + 3087844148U, // <1,2,3,1>: Cost 2 vsldoi4 LHS, <1,1,1,1> + 3087844968U, // <1,2,3,2>: Cost 2 vsldoi4 LHS, <2,2,2,2> + 3087845788U, // <1,2,3,3>: Cost 2 vsldoi4 LHS, <3,3,3,3> + 2014104886U, // <1,2,3,4>: Cost 1 vsldoi4 LHS, RHS + 3135623172U, // <1,2,3,5>: Cost 2 vsldoi4 LHS, <5,5,5,5> + 3135623674U, // <1,2,3,6>: Cost 2 vsldoi4 LHS, <6,2,7,3> + 3135624186U, // <1,2,3,7>: Cost 2 vsldoi4 LHS, <7,0,1,2> + 2014107438U, // <1,2,3,u>: Cost 1 vsldoi4 LHS, LHS + 3245206383U, // <1,2,4,0>: Cost 3 vsldoi8 <4,0,1,2>, <4,0,1,2> + 3368281860U, // <1,2,4,1>: Cost 4 vsldoi12 <2,1,3,1>, <2,4,1,5> + 3491759720U, // <1,2,4,2>: Cost 4 vmrglw <0,3,1,4>, <2,2,2,2> + 3491758182U, // <1,2,4,3>: Cost 3 vmrglw <0,3,1,4>, LHS + 3263122640U, // <1,2,4,4>: Cost 3 vsldoi8 <7,0,1,2>, <4,4,4,4> + 3239234870U, // <1,2,4,5>: Cost 2 vsldoi8 <3,0,1,2>, RHS + 3364186042U, // <1,2,4,6>: Cost 4 vmrghw <1,4,1,5>, <2,6,3,7> + 3263122888U, // <1,2,4,7>: Cost 3 vsldoi8 <7,0,1,2>, <4,7,5,0> + 3239235113U, // <1,2,4,u>: Cost 2 vsldoi8 <3,0,1,2>, RHS + 3251179080U, // <1,2,5,0>: Cost 3 vsldoi8 <5,0,1,2>, <5,0,1,2> + 3364742691U, // <1,2,5,1>: Cost 4 vmrghw <1,5,0,1>, <2,1,3,5> + 3492431464U, // <1,2,5,2>: Cost 3 vmrglw <0,4,1,5>, <2,2,2,2> + 2418688102U, // <1,2,5,3>: Cost 2 vmrglw <0,4,1,5>, LHS + 3239235508U, // <1,2,5,4>: Cost 4 vsldoi8 <3,0,1,2>, <5,4,5,6> + 3263123460U, // <1,2,5,5>: Cost 3 vsldoi8 <7,0,1,2>, <5,5,5,5> + 3263123554U, // <1,2,5,6>: Cost 3 vsldoi8 <7,0,1,2>, <5,6,7,0> + 3263123626U, // <1,2,5,7>: Cost 4 vsldoi8 <7,0,1,2>, <5,7,6,0> + 2418688107U, // <1,2,5,u>: Cost 2 vmrglw <0,4,1,5>, LHS + 3257151777U, // <1,2,6,0>: Cost 3 vsldoi8 <6,0,1,2>, <6,0,1,2> + 3239236008U, // <1,2,6,1>: Cost 3 vsldoi8 <3,0,1,2>, <6,1,7,2> + 3263123962U, // <1,2,6,2>: Cost 3 vsldoi8 <7,0,1,2>, <6,2,7,3> + 3491111014U, // <1,2,6,3>: Cost 3 vmrglw <0,2,1,6>, LHS + 4167585078U, // <1,2,6,4>: Cost 4 vsldoi4 <1,1,2,6>, RHS + 3365824361U, // <1,2,6,5>: Cost 4 vmrghw <1,6,5,7>, <2,5,3,7> + 3263124280U, // <1,2,6,6>: Cost 3 vsldoi8 <7,0,1,2>, <6,6,6,6> + 3261797208U, // <1,2,6,7>: Cost 3 vsldoi8 <6,7,1,2>, <6,7,1,2> + 3491111019U, // <1,2,6,u>: Cost 3 vmrglw <0,2,1,6>, LHS + 3263124474U, // <1,2,7,0>: Cost 2 vsldoi8 <7,0,1,2>, <7,0,1,2> + 3505718644U, // <1,2,7,1>: Cost 4 vmrglw <2,6,1,7>, <1,u,2,1> + 3499746920U, // <1,2,7,2>: Cost 4 vmrglw <1,6,1,7>, <2,2,2,2> + 3499745382U, // <1,2,7,3>: Cost 3 vmrglw <1,6,1,7>, LHS + 3263124838U, // <1,2,7,4>: Cost 3 vsldoi8 <7,0,1,2>, <7,4,5,6> + 3251180933U, // <1,2,7,5>: Cost 4 vsldoi8 <5,0,1,2>, <7,5,0,1> + 3257152982U, // <1,2,7,6>: Cost 4 vsldoi8 <6,0,1,2>, <7,6,0,1> + 3263125031U, // <1,2,7,7>: Cost 3 vsldoi8 <7,0,1,2>, <7,7,0,1> + 3268433538U, // <1,2,7,u>: Cost 2 vsldoi8 <7,u,1,2>, <7,u,1,2> + 2014142571U, // <1,2,u,0>: Cost 1 vsldoi4 LHS, LHS + 3087885108U, // <1,2,u,1>: Cost 2 vsldoi4 LHS, <1,1,1,1> + 3087885928U, // <1,2,u,2>: Cost 2 vsldoi4 LHS, <2,2,2,2> + 3087886486U, // <1,2,u,3>: Cost 2 vsldoi4 LHS, <3,0,1,2> + 2014145846U, // <1,2,u,4>: Cost 1 vsldoi4 LHS, RHS + 3239237786U, // <1,2,u,5>: Cost 2 vsldoi8 <3,0,1,2>, RHS + 3135664634U, // <1,2,u,6>: Cost 2 vsldoi4 LHS, <6,2,7,3> + 3135665146U, // <1,2,u,7>: Cost 2 vsldoi4 LHS, <7,0,1,2> + 2014148398U, // <1,2,u,u>: Cost 1 vsldoi4 LHS, LHS + 3373369484U, // <1,3,0,0>: Cost 3 vsldoi12 <3,0,0,1>, <3,0,0,1> + 3222650982U, // <1,3,0,1>: Cost 3 vsldoi8 <0,2,1,3>, LHS + 3222651054U, // <1,3,0,2>: Cost 3 vsldoi8 <0,2,1,3>, <0,2,1,3> + 3223314687U, // <1,3,0,3>: Cost 3 vsldoi8 <0,3,1,3>, <0,3,1,3> + 3373664432U, // <1,3,0,4>: Cost 3 vsldoi12 <3,0,4,1>, <3,0,4,1> + 3491725668U, // <1,3,0,5>: Cost 4 vmrglw <0,3,1,0>, <0,4,3,5> + 3222651382U, // <1,3,0,6>: Cost 4 vsldoi8 <0,2,1,3>, <0,6,1,7> + 3491727290U, // <1,3,0,7>: Cost 4 vmrglw <0,3,1,0>, <2,6,3,7> + 3222651549U, // <1,3,0,u>: Cost 3 vsldoi8 <0,2,1,3>, LHS + 3495052182U, // <1,3,1,0>: Cost 3 vmrglw <0,u,1,1>, <1,2,3,0> + 3362162918U, // <1,3,1,1>: Cost 3 vmrghw <1,1,1,1>, <3,1,1,1> + 3228623751U, // <1,3,1,2>: Cost 3 vsldoi8 <1,2,1,3>, <1,2,1,3> + 3495052914U, // <1,3,1,3>: Cost 3 vmrglw <0,u,1,1>, <2,2,3,3> + 3495052186U, // <1,3,1,4>: Cost 3 vmrglw <0,u,1,1>, <1,2,3,4> + 3495052835U, // <1,3,1,5>: Cost 4 vmrglw <0,u,1,1>, <2,1,3,5> + 3222652129U, // <1,3,1,6>: Cost 4 vsldoi8 <0,2,1,3>, <1,6,3,7> + 3495053242U, // <1,3,1,7>: Cost 3 vmrglw <0,u,1,1>, <2,6,3,7> + 3495052190U, // <1,3,1,u>: Cost 3 vmrglw <0,u,1,1>, <1,2,3,u> + 3362965654U, // <1,3,2,0>: Cost 3 vmrghw <1,2,3,0>, <3,0,1,2> + 3362965745U, // <1,3,2,1>: Cost 3 vmrghw <1,2,3,0>, <3,1,2,3> + 4173596192U, // <1,3,2,2>: Cost 3 vsldoi4 <2,1,3,2>, <2,1,3,2> + 3222652582U, // <1,3,2,3>: Cost 3 vsldoi8 <0,2,1,3>, <2,3,0,1> + 3362966018U, // <1,3,2,4>: Cost 3 vmrghw <1,2,3,0>, <3,4,5,6> + 3507667300U, // <1,3,2,5>: Cost 4 vmrglw <3,0,1,2>, <0,4,3,5> + 3362966136U, // <1,3,2,6>: Cost 3 vmrghw <1,2,3,0>, <3,6,0,7> + 3507668922U, // <1,3,2,7>: Cost 3 vmrglw <3,0,1,2>, <2,6,3,7> + 3362966302U, // <1,3,2,u>: Cost 3 vmrghw <1,2,3,0>, <3,u,1,2> + 3375360383U, // <1,3,3,0>: Cost 3 vsldoi12 <3,3,0,1>, <3,3,0,1> + 3491092196U, // <1,3,3,1>: Cost 4 vmrglw <0,2,1,3>, + 3222653256U, // <1,3,3,2>: Cost 4 vsldoi8 <0,2,1,3>, <3,2,3,0> + 3491752348U, // <1,3,3,3>: Cost 3 vmrglw <0,3,1,3>, <3,3,3,3> + 3491087258U, // <1,3,3,4>: Cost 4 vmrglw <0,2,1,3>, <1,2,3,4> + 4191522476U, // <1,3,3,5>: Cost 4 vsldoi4 <5,1,3,3>, <5,1,3,3> + 3363605112U, // <1,3,3,6>: Cost 4 vmrghw <1,3,2,6>, <3,6,0,7> + 3491088314U, // <1,3,3,7>: Cost 4 vmrglw <0,2,1,3>, <2,6,3,7> + 3375950279U, // <1,3,3,u>: Cost 3 vsldoi12 <3,3,u,1>, <3,3,u,1> + 3376024016U, // <1,3,4,0>: Cost 3 vsldoi12 <3,4,0,1>, <3,4,0,1> + 3496403863U, // <1,3,4,1>: Cost 4 vmrglw <1,1,1,4>, <1,2,3,1> + 3364260144U, // <1,3,4,2>: Cost 4 vmrghw <1,4,2,5>, <3,2,0,3> + 3491759730U, // <1,3,4,3>: Cost 4 vmrglw <0,3,1,4>, <2,2,3,3> + 3491758354U, // <1,3,4,4>: Cost 4 vmrglw <0,3,1,4>, <0,3,3,4> + 3222654262U, // <1,3,4,5>: Cost 3 vsldoi8 <0,2,1,3>, RHS + 3491764350U, // <1,3,4,6>: Cost 4 vmrglw <0,3,1,4>, + 3491760058U, // <1,3,4,7>: Cost 4 vmrglw <0,3,1,4>, <2,6,3,7> + 3222654505U, // <1,3,4,u>: Cost 3 vsldoi8 <0,2,1,3>, RHS + 3492430742U, // <1,3,5,0>: Cost 3 vmrglw <0,4,1,5>, <1,2,3,0> + 3492430743U, // <1,3,5,1>: Cost 4 vmrglw <0,4,1,5>, <1,2,3,1> + 4173620771U, // <1,3,5,2>: Cost 3 vsldoi4 <2,1,3,5>, <2,1,3,5> + 3492431474U, // <1,3,5,3>: Cost 3 vmrglw <0,4,1,5>, <2,2,3,3> + 3492430746U, // <1,3,5,4>: Cost 3 vmrglw <0,4,1,5>, <1,2,3,4> + 3492431395U, // <1,3,5,5>: Cost 3 vmrglw <0,4,1,5>, <2,1,3,5> + 3492436094U, // <1,3,5,6>: Cost 4 vmrglw <0,4,1,5>, + 3492431802U, // <1,3,5,7>: Cost 3 vmrglw <0,4,1,5>, <2,6,3,7> + 3492430750U, // <1,3,5,u>: Cost 3 vmrglw <0,4,1,5>, <1,2,3,u> + 3365603478U, // <1,3,6,0>: Cost 3 vmrghw <1,6,2,7>, <3,0,1,2> + 3362974337U, // <1,3,6,1>: Cost 4 vsldoi12 <1,2,3,1>, <3,6,1,7> + 4173628964U, // <1,3,6,2>: Cost 4 vsldoi4 <2,1,3,6>, <2,1,3,6> + 3491112562U, // <1,3,6,3>: Cost 4 vmrglw <0,2,1,6>, <2,2,3,3> + 3491111834U, // <1,3,6,4>: Cost 4 vmrglw <0,2,1,6>, <1,2,3,4> + 3491112483U, // <1,3,6,5>: Cost 5 vmrglw <0,2,1,6>, <2,1,3,5> + 3491116858U, // <1,3,6,6>: Cost 4 vmrglw <0,2,1,6>, + 3491112890U, // <1,3,6,7>: Cost 3 vmrglw <0,2,1,6>, <2,6,3,7> + 3491112890U, // <1,3,6,u>: Cost 3 vmrglw <0,2,1,6>, <2,6,3,7> + 3378014915U, // <1,3,7,0>: Cost 3 vsldoi12 <3,7,0,1>, <3,7,0,1> + 4173636815U, // <1,3,7,1>: Cost 4 vsldoi4 <2,1,3,7>, <1,6,1,7> + 4173637157U, // <1,3,7,2>: Cost 4 vsldoi4 <2,1,3,7>, <2,1,3,7> + 3499746930U, // <1,3,7,3>: Cost 4 vmrglw <1,6,1,7>, <2,2,3,3> + 3499746202U, // <1,3,7,4>: Cost 4 vmrglw <1,6,1,7>, <1,2,3,4> + 3252516247U, // <1,3,7,5>: Cost 4 vsldoi8 <5,2,1,3>, <7,5,2,1> + 3395930879U, // <1,3,7,6>: Cost 4 vsldoi12 <6,7,0,1>, <3,7,6,7> + 3497756602U, // <1,3,7,7>: Cost 4 vmrglw <1,3,1,7>, <2,6,3,7> + 3378604811U, // <1,3,7,u>: Cost 3 vsldoi12 <3,7,u,1>, <3,7,u,1> + 3492455318U, // <1,3,u,0>: Cost 3 vmrglw <0,4,1,u>, <1,2,3,0> + 3222656814U, // <1,3,u,1>: Cost 3 vsldoi8 <0,2,1,3>, LHS + 4173645350U, // <1,3,u,2>: Cost 3 vsldoi4 <2,1,3,u>, <2,1,3,u> + 3491129432U, // <1,3,u,3>: Cost 3 vmrglw <0,2,1,u>, <2,u,3,3> + 3492455322U, // <1,3,u,4>: Cost 3 vmrglw <0,4,1,u>, <1,2,3,4> + 3222657178U, // <1,3,u,5>: Cost 3 vsldoi8 <0,2,1,3>, RHS + 3362966136U, // <1,3,u,6>: Cost 3 vmrghw <1,2,3,0>, <3,6,0,7> + 3492456378U, // <1,3,u,7>: Cost 3 vmrglw <0,4,1,u>, <2,6,3,7> + 3222657381U, // <1,3,u,u>: Cost 3 vsldoi8 <0,2,1,3>, LHS + 3221331981U, // <1,4,0,0>: Cost 3 vsldoi8 <0,0,1,4>, <0,0,1,4> + 3223322726U, // <1,4,0,1>: Cost 3 vsldoi8 <0,3,1,4>, LHS + 3222659247U, // <1,4,0,2>: Cost 4 vsldoi8 <0,2,1,4>, <0,2,1,4> + 3223322880U, // <1,4,0,3>: Cost 3 vsldoi8 <0,3,1,4>, <0,3,1,4> + 3221332306U, // <1,4,0,4>: Cost 3 vsldoi8 <0,0,1,4>, <0,4,1,5> + 3379710866U, // <1,4,0,5>: Cost 2 vsldoi12 <4,0,5,1>, <4,0,5,1> + 3239248374U, // <1,4,0,6>: Cost 4 vsldoi8 <3,0,1,4>, <0,6,1,7> + 3225977412U, // <1,4,0,7>: Cost 3 vsldoi8 <0,7,1,4>, <0,7,1,4> + 3379932077U, // <1,4,0,u>: Cost 2 vsldoi12 <4,0,u,1>, <4,0,u,1> + 3362163602U, // <1,4,1,0>: Cost 3 vmrghw <1,1,1,1>, <4,0,5,1> + 3227968311U, // <1,4,1,1>: Cost 3 vsldoi8 <1,1,1,4>, <1,1,1,4> + 3223323542U, // <1,4,1,2>: Cost 4 vsldoi8 <0,3,1,4>, <1,2,3,0> + 3229295577U, // <1,4,1,3>: Cost 4 vsldoi8 <1,3,1,4>, <1,3,1,4> + 3542830288U, // <1,4,1,4>: Cost 3 vmrglw , <4,4,4,4> + 2288422198U, // <1,4,1,5>: Cost 2 vmrghw <1,1,1,1>, RHS + 3223323882U, // <1,4,1,6>: Cost 4 vsldoi8 <0,3,1,4>, <1,6,4,7> + 3397553140U, // <1,4,1,7>: Cost 4 vsldoi12 <7,0,4,1>, <4,1,7,0> + 2288422441U, // <1,4,1,u>: Cost 2 vmrghw <1,1,1,1>, RHS + 3362966418U, // <1,4,2,0>: Cost 3 vmrghw <1,2,3,0>, <4,0,5,1> + 3362966500U, // <1,4,2,1>: Cost 3 vmrghw <1,2,3,0>, <4,1,5,2> + 3223324264U, // <1,4,2,2>: Cost 4 vsldoi8 <0,3,1,4>, <2,2,2,2> + 3239249574U, // <1,4,2,3>: Cost 3 vsldoi8 <3,0,1,4>, <2,3,0,1> + 3531558096U, // <1,4,2,4>: Cost 3 vmrglw <7,0,1,2>, <4,4,4,4> + 2289225014U, // <1,4,2,5>: Cost 2 vmrghw <1,2,3,0>, RHS + 3223324602U, // <1,4,2,6>: Cost 4 vsldoi8 <0,3,1,4>, <2,6,3,7> + 3507669660U, // <1,4,2,7>: Cost 4 vmrglw <3,0,1,2>, <3,6,4,7> + 2289225257U, // <1,4,2,u>: Cost 2 vmrghw <1,2,3,0>, RHS + 3239250072U, // <1,4,3,0>: Cost 3 vsldoi8 <3,0,1,4>, <3,0,1,4> + 3223324928U, // <1,4,3,1>: Cost 4 vsldoi8 <0,3,1,4>, <3,1,4,0> + 3239250248U, // <1,4,3,2>: Cost 4 vsldoi8 <3,0,1,4>, <3,2,3,0> + 3223325084U, // <1,4,3,3>: Cost 4 vsldoi8 <0,3,1,4>, <3,3,3,3> + 3223325186U, // <1,4,3,4>: Cost 3 vsldoi8 <0,3,1,4>, <3,4,5,6> + 3491088078U, // <1,4,3,5>: Cost 4 vmrglw <0,2,1,3>, <2,3,4,5> + 3263138480U, // <1,4,3,6>: Cost 4 vsldoi8 <7,0,1,4>, <3,6,7,0> + 3501042332U, // <1,4,3,7>: Cost 5 vmrglw <1,u,1,3>, <3,6,4,7> + 3244559136U, // <1,4,3,u>: Cost 3 vsldoi8 <3,u,1,4>, <3,u,1,4> + 3379711144U, // <1,4,4,0>: Cost 3 vsldoi12 <4,0,5,1>, <4,4,0,0> + 3361057970U, // <1,4,4,1>: Cost 4 vsldoi12 <0,u,4,1>, <4,4,1,1> + 4161742502U, // <1,4,4,2>: Cost 4 vsldoi4 <0,1,4,4>, <2,3,0,1> + 3491759010U, // <1,4,4,3>: Cost 4 vmrglw <0,3,1,4>, <1,2,4,3> + 3385019600U, // <1,4,4,4>: Cost 3 vsldoi12 <4,u,5,1>, <4,4,4,4> + 3223326006U, // <1,4,4,5>: Cost 3 vsldoi8 <0,3,1,4>, RHS + 3491759256U, // <1,4,4,6>: Cost 4 vmrglw <0,3,1,4>, <1,5,4,6> + 3273756108U, // <1,4,4,7>: Cost 4 vsldoi8 , <4,7,5,4> + 3223326249U, // <1,4,4,u>: Cost 3 vsldoi8 <0,3,1,4>, RHS + 4167721062U, // <1,4,5,0>: Cost 3 vsldoi4 <1,1,4,5>, LHS + 3492429861U, // <1,4,5,1>: Cost 3 vmrglw <0,4,1,5>, <0,0,4,1> + 4161750694U, // <1,4,5,2>: Cost 3 vsldoi4 <0,1,4,5>, <2,3,0,1> + 3492430025U, // <1,4,5,3>: Cost 4 vmrglw <0,4,1,5>, <0,2,4,3> + 3492429864U, // <1,4,5,4>: Cost 3 vmrglw <0,4,1,5>, <0,0,4,4> + 3492430189U, // <1,4,5,5>: Cost 3 vmrglw <0,4,1,5>, <0,4,4,5> + 3360836918U, // <1,4,5,6>: Cost 2 vsldoi12 <0,u,1,1>, RHS + 4191613946U, // <1,4,5,7>: Cost 4 vsldoi4 <5,1,4,5>, <7,0,1,2> + 3360836936U, // <1,4,5,u>: Cost 2 vsldoi12 <0,u,1,1>, RHS + 3257168163U, // <1,4,6,0>: Cost 4 vsldoi8 <6,0,1,4>, <6,0,1,4> + 3361058138U, // <1,4,6,1>: Cost 4 vsldoi12 <0,u,4,1>, <4,6,1,7> + 3263140346U, // <1,4,6,2>: Cost 4 vsldoi8 <7,0,1,4>, <6,2,7,3> + 3271103026U, // <1,4,6,3>: Cost 4 vsldoi8 , <6,3,4,5> + 3365825744U, // <1,4,6,4>: Cost 4 vmrghw <1,6,5,7>, <4,4,4,4> + 3365530934U, // <1,4,6,5>: Cost 3 vmrghw <1,6,1,7>, RHS + 3263140664U, // <1,4,6,6>: Cost 4 vsldoi8 <7,0,1,4>, <6,6,6,6> + 3263140686U, // <1,4,6,7>: Cost 3 vsldoi8 <7,0,1,4>, <6,7,0,1> + 3365531177U, // <1,4,6,u>: Cost 3 vmrghw <1,6,1,7>, RHS + 3263140860U, // <1,4,7,0>: Cost 3 vsldoi8 <7,0,1,4>, <7,0,1,4> + 3517661869U, // <1,4,7,1>: Cost 4 vmrglw <4,6,1,7>, <0,u,4,1> + 3269113049U, // <1,4,7,2>: Cost 4 vsldoi8 , <7,2,u,0> + 3271103755U, // <1,4,7,3>: Cost 4 vsldoi8 , <7,3,4,5> + 3273758054U, // <1,4,7,4>: Cost 3 vsldoi8 , <7,4,5,6> + 3499746131U, // <1,4,7,5>: Cost 4 vmrglw <1,6,1,7>, <1,1,4,5> + 3263141396U, // <1,4,7,6>: Cost 4 vsldoi8 <7,0,1,4>, <7,6,7,0> + 3263141484U, // <1,4,7,7>: Cost 4 vsldoi8 <7,0,1,4>, <7,7,7,7> + 3268449924U, // <1,4,7,u>: Cost 3 vsldoi8 <7,u,1,4>, <7,u,1,4> + 4167745638U, // <1,4,u,0>: Cost 3 vsldoi4 <1,1,4,u>, LHS + 3223328558U, // <1,4,u,1>: Cost 3 vsldoi8 <0,3,1,4>, LHS + 4161775270U, // <1,4,u,2>: Cost 3 vsldoi4 <0,1,4,u>, <2,3,0,1> + 3271104456U, // <1,4,u,3>: Cost 3 vsldoi8 , + 3226646591U, // <1,4,u,4>: Cost 3 vsldoi8 <0,u,1,4>, + 2293206326U, // <1,4,u,5>: Cost 2 vmrghw <1,u,3,0>, RHS + 3360837161U, // <1,4,u,6>: Cost 2 vsldoi12 <0,u,1,1>, RHS + 3273758988U, // <1,4,u,7>: Cost 3 vsldoi8 , + 3360837179U, // <1,4,u,u>: Cost 2 vsldoi12 <0,u,1,1>, RHS + 3223994368U, // <1,5,0,0>: Cost 3 vsldoi8 <0,4,1,5>, <0,0,0,0> + 3223994470U, // <1,5,0,1>: Cost 2 vsldoi8 <0,4,1,5>, LHS + 3222667440U, // <1,5,0,2>: Cost 4 vsldoi8 <0,2,1,5>, <0,2,1,5> + 3223994620U, // <1,5,0,3>: Cost 4 vsldoi8 <0,4,1,5>, <0,3,1,0> + 3223994706U, // <1,5,0,4>: Cost 2 vsldoi8 <0,4,1,5>, <0,4,1,5> + 3224658339U, // <1,5,0,5>: Cost 3 vsldoi8 <0,5,1,5>, <0,5,1,5> + 3385757300U, // <1,5,0,6>: Cost 3 vsldoi12 <5,0,6,1>, <5,0,6,1> + 4203590765U, // <1,5,0,7>: Cost 4 vsldoi4 <7,1,5,0>, <7,1,5,0> + 3223995037U, // <1,5,0,u>: Cost 2 vsldoi8 <0,4,1,5>, LHS + 3385020047U, // <1,5,1,0>: Cost 3 vsldoi12 <4,u,5,1>, <5,1,0,1> + 3223995188U, // <1,5,1,1>: Cost 3 vsldoi8 <0,4,1,5>, <1,1,1,1> + 3223995286U, // <1,5,1,2>: Cost 3 vsldoi8 <0,4,1,5>, <1,2,3,0> + 3223995385U, // <1,5,1,3>: Cost 4 vsldoi8 <0,4,1,5>, <1,3,5,0> + 3229967403U, // <1,5,1,4>: Cost 3 vsldoi8 <1,4,1,5>, <1,4,1,5> + 3223995503U, // <1,5,1,5>: Cost 3 vsldoi8 <0,4,1,5>, <1,5,0,1> + 3223995635U, // <1,5,1,6>: Cost 3 vsldoi8 <0,4,1,5>, <1,6,5,7> + 3495052531U, // <1,5,1,7>: Cost 4 vmrglw <0,u,1,1>, <1,6,5,7> + 3223995772U, // <1,5,1,u>: Cost 3 vsldoi8 <0,4,1,5>, <1,u,3,0> + 3531558344U, // <1,5,2,0>: Cost 3 vmrglw <7,0,1,2>, <4,7,5,0> + 3223995939U, // <1,5,2,1>: Cost 3 vsldoi8 <0,4,1,5>, <2,1,3,5> + 3223996008U, // <1,5,2,2>: Cost 3 vsldoi8 <0,4,1,5>, <2,2,2,2> + 3223996070U, // <1,5,2,3>: Cost 3 vsldoi8 <0,4,1,5>, <2,3,0,1> + 4185689060U, // <1,5,2,4>: Cost 3 vsldoi4 <4,1,5,2>, <4,1,5,2> + 3531558106U, // <1,5,2,5>: Cost 3 vmrglw <7,0,1,2>, <4,4,5,5> + 3223996346U, // <1,5,2,6>: Cost 3 vsldoi8 <0,4,1,5>, <2,6,3,7> + 3507668211U, // <1,5,2,7>: Cost 4 vmrglw <3,0,1,2>, <1,6,5,7> + 3223996475U, // <1,5,2,u>: Cost 3 vsldoi8 <0,4,1,5>, <2,u,0,1> + 3223996566U, // <1,5,3,0>: Cost 3 vsldoi8 <0,4,1,5>, <3,0,1,2> + 3520949786U, // <1,5,3,1>: Cost 3 vmrglw <5,2,1,3>, <4,u,5,1> + 3223996737U, // <1,5,3,2>: Cost 4 vsldoi8 <0,4,1,5>, <3,2,2,2> + 3223996828U, // <1,5,3,3>: Cost 3 vsldoi8 <0,4,1,5>, <3,3,3,3> + 3223996930U, // <1,5,3,4>: Cost 3 vsldoi8 <0,4,1,5>, <3,4,5,6> + 3520949466U, // <1,5,3,5>: Cost 4 vmrglw <5,2,1,3>, <4,4,5,5> + 3491088898U, // <1,5,3,6>: Cost 4 vmrglw <0,2,1,3>, <3,4,5,6> + 3271772867U, // <1,5,3,7>: Cost 4 vsldoi8 , <3,7,0,1> + 3223997214U, // <1,5,3,u>: Cost 3 vsldoi8 <0,4,1,5>, <3,u,1,2> + 4185702502U, // <1,5,4,0>: Cost 3 vsldoi4 <4,1,5,4>, LHS + 3223997410U, // <1,5,4,1>: Cost 3 vsldoi8 <0,4,1,5>, <4,1,5,0> + 4185703971U, // <1,5,4,2>: Cost 4 vsldoi4 <4,1,5,4>, <2,1,3,5> + 4179732749U, // <1,5,4,3>: Cost 4 vsldoi4 <3,1,5,4>, <3,1,5,4> + 3223997648U, // <1,5,4,4>: Cost 3 vsldoi8 <0,4,1,5>, <4,4,4,4> + 3223997750U, // <1,5,4,5>: Cost 2 vsldoi8 <0,4,1,5>, RHS + 3491760642U, // <1,5,4,6>: Cost 3 vmrglw <0,3,1,4>, <3,4,5,6> + 4203623537U, // <1,5,4,7>: Cost 4 vsldoi4 <7,1,5,4>, <7,1,5,4> + 3223997993U, // <1,5,4,u>: Cost 2 vsldoi8 <0,4,1,5>, RHS + 4167794790U, // <1,5,5,0>: Cost 3 vsldoi4 <1,1,5,5>, LHS + 4167795548U, // <1,5,5,1>: Cost 3 vsldoi4 <1,1,5,5>, <1,1,5,5> + 4167796259U, // <1,5,5,2>: Cost 4 vsldoi4 <1,1,5,5>, <2,1,3,5> + 3492430763U, // <1,5,5,3>: Cost 3 vmrglw <0,4,1,5>, <1,2,5,3> + 4167798070U, // <1,5,5,4>: Cost 3 vsldoi4 <1,1,5,5>, RHS + 3492430684U, // <1,5,5,5>: Cost 3 vmrglw <0,4,1,5>, <1,1,5,5> + 3492432386U, // <1,5,5,6>: Cost 3 vmrglw <0,4,1,5>, <3,4,5,6> + 3492431091U, // <1,5,5,7>: Cost 3 vmrglw <0,4,1,5>, <1,6,5,7> + 3492430768U, // <1,5,5,u>: Cost 3 vmrglw <0,4,1,5>, <1,2,5,u> + 3389296676U, // <1,5,6,0>: Cost 3 vsldoi12 <5,6,0,1>, <5,6,0,1> + 3385020467U, // <1,5,6,1>: Cost 3 vsldoi12 <4,u,5,1>, <5,6,1,7> + 3271774714U, // <1,5,6,2>: Cost 3 vsldoi8 , <6,2,7,3> + 3378974786U, // <1,5,6,3>: Cost 4 vsldoi12 <3,u,4,1>, <5,6,3,4> + 3365826484U, // <1,5,6,4>: Cost 4 vmrghw <1,6,5,7>, <5,4,5,6> + 3365826564U, // <1,5,6,5>: Cost 4 vmrghw <1,6,5,7>, <5,5,5,5> + 3271775032U, // <1,5,6,6>: Cost 3 vsldoi8 , <6,6,6,6> + 3385020514U, // <1,5,6,7>: Cost 3 vsldoi12 <4,u,5,1>, <5,6,7,0> + 3385020523U, // <1,5,6,u>: Cost 3 vsldoi12 <4,u,5,1>, <5,6,u,0> + 3271775226U, // <1,5,7,0>: Cost 3 vsldoi8 , <7,0,1,2> + 3523636762U, // <1,5,7,1>: Cost 3 vmrglw <5,6,1,7>, <4,u,5,1> + 3271775380U, // <1,5,7,2>: Cost 4 vsldoi8 , <7,2,0,3> + 3271775459U, // <1,5,7,3>: Cost 4 vsldoi8 , <7,3,0,1> + 3271775590U, // <1,5,7,4>: Cost 3 vsldoi8 , <7,4,5,6> + 3523636442U, // <1,5,7,5>: Cost 4 vmrglw <5,6,1,7>, <4,4,5,5> + 3499746384U, // <1,5,7,6>: Cost 4 vmrglw <1,6,1,7>, <1,4,5,6> + 3271775852U, // <1,5,7,7>: Cost 3 vsldoi8 , <7,7,7,7> + 3271775874U, // <1,5,7,u>: Cost 3 vsldoi8 , <7,u,1,2> + 3224000211U, // <1,5,u,0>: Cost 3 vsldoi8 <0,4,1,5>, + 3224000302U, // <1,5,u,1>: Cost 2 vsldoi8 <0,4,1,5>, LHS + 3224000392U, // <1,5,u,2>: Cost 3 vsldoi8 <0,4,1,5>, + 3224000444U, // <1,5,u,3>: Cost 3 vsldoi8 <0,4,1,5>, + 3271776282U, // <1,5,u,4>: Cost 2 vsldoi8 , + 3224000666U, // <1,5,u,5>: Cost 2 vsldoi8 <0,4,1,5>, RHS + 3224000720U, // <1,5,u,6>: Cost 3 vsldoi8 <0,4,1,5>, + 3385020676U, // <1,5,u,7>: Cost 3 vsldoi12 <4,u,5,1>, <5,u,7,0> + 3224000869U, // <1,5,u,u>: Cost 2 vsldoi8 <0,4,1,5>, LHS + 3222675456U, // <1,6,0,0>: Cost 4 vsldoi8 <0,2,1,6>, <0,0,0,0> + 3222675558U, // <1,6,0,1>: Cost 3 vsldoi8 <0,2,1,6>, LHS + 3222675633U, // <1,6,0,2>: Cost 3 vsldoi8 <0,2,1,6>, <0,2,1,6> + 3391508786U, // <1,6,0,3>: Cost 4 vsldoi12 <6,0,3,1>, <6,0,3,1> + 3222675794U, // <1,6,0,4>: Cost 4 vsldoi8 <0,2,1,6>, <0,4,1,5> + 3224666532U, // <1,6,0,5>: Cost 3 vsldoi8 <0,5,1,6>, <0,5,1,6> + 3225330165U, // <1,6,0,6>: Cost 3 vsldoi8 <0,6,1,6>, <0,6,1,6> + 3491728694U, // <1,6,0,7>: Cost 3 vmrglw <0,3,1,0>, RHS + 3222676125U, // <1,6,0,u>: Cost 3 vsldoi8 <0,2,1,6>, LHS + 4167835750U, // <1,6,1,0>: Cost 4 vsldoi4 <1,1,6,1>, LHS + 3222676276U, // <1,6,1,1>: Cost 4 vsldoi8 <0,2,1,6>, <1,1,1,1> + 3362165242U, // <1,6,1,2>: Cost 3 vmrghw <1,1,1,1>, <6,2,7,3> + 3222676489U, // <1,6,1,3>: Cost 4 vsldoi8 <0,2,1,6>, <1,3,6,7> + 4167839030U, // <1,6,1,4>: Cost 4 vsldoi4 <1,1,6,1>, RHS + 3230639229U, // <1,6,1,5>: Cost 4 vsldoi8 <1,5,1,6>, <1,5,1,6> + 3542831928U, // <1,6,1,6>: Cost 3 vmrglw , <6,6,6,6> + 2421312822U, // <1,6,1,7>: Cost 2 vmrglw <0,u,1,1>, RHS + 2421312823U, // <1,6,1,u>: Cost 2 vmrglw <0,u,1,1>, RHS + 4173815910U, // <1,6,2,0>: Cost 4 vsldoi4 <2,1,6,2>, LHS + 3222677049U, // <1,6,2,1>: Cost 4 vsldoi8 <0,2,1,6>, <2,1,6,0> + 3362968058U, // <1,6,2,2>: Cost 3 vmrghw <1,2,3,0>, <6,2,7,3> + 3222677158U, // <1,6,2,3>: Cost 4 vsldoi8 <0,2,1,6>, <2,3,0,1> + 4173819190U, // <1,6,2,4>: Cost 4 vsldoi4 <2,1,6,2>, RHS + 3507668785U, // <1,6,2,5>: Cost 4 vmrglw <3,0,1,2>, <2,4,6,5> + 3222677434U, // <1,6,2,6>: Cost 3 vsldoi8 <0,2,1,6>, <2,6,3,7> + 2433928502U, // <1,6,2,7>: Cost 2 vmrglw <3,0,1,2>, RHS + 2433928503U, // <1,6,2,u>: Cost 2 vmrglw <3,0,1,2>, RHS + 3222677654U, // <1,6,3,0>: Cost 4 vsldoi8 <0,2,1,6>, <3,0,1,2> + 3373150745U, // <1,6,3,1>: Cost 4 vsldoi12 <2,u,6,1>, <6,3,1,7> + 3222677862U, // <1,6,3,2>: Cost 4 vsldoi8 <0,2,1,6>, <3,2,6,3> + 3222677916U, // <1,6,3,3>: Cost 4 vsldoi8 <0,2,1,6>, <3,3,3,3> + 3222678018U, // <1,6,3,4>: Cost 4 vsldoi8 <0,2,1,6>, <3,4,5,6> + 3272444509U, // <1,6,3,5>: Cost 4 vsldoi8 , <3,5,6,7> + 3520951096U, // <1,6,3,6>: Cost 4 vmrglw <5,2,1,3>, <6,6,6,6> + 3491089718U, // <1,6,3,7>: Cost 3 vmrglw <0,2,1,3>, RHS + 3491089719U, // <1,6,3,u>: Cost 3 vmrglw <0,2,1,3>, RHS + 4173832294U, // <1,6,4,0>: Cost 4 vsldoi4 <2,1,6,4>, LHS + 3392467560U, // <1,6,4,1>: Cost 4 vsldoi12 <6,1,7,1>, <6,4,1,5> + 4173833789U, // <1,6,4,2>: Cost 4 vsldoi4 <2,1,6,4>, <2,1,6,4> + 4191750658U, // <1,6,4,3>: Cost 4 vsldoi4 <5,1,6,4>, <3,4,5,6> + 4173835574U, // <1,6,4,4>: Cost 4 vsldoi4 <2,1,6,4>, RHS + 3222678838U, // <1,6,4,5>: Cost 3 vsldoi8 <0,2,1,6>, RHS + 3395859093U, // <1,6,4,6>: Cost 4 vsldoi12 <6,6,u,1>, <6,4,6,5> + 3491761462U, // <1,6,4,7>: Cost 3 vmrglw <0,3,1,4>, RHS + 3222679081U, // <1,6,4,u>: Cost 3 vsldoi8 <0,2,1,6>, RHS + 4179812454U, // <1,6,5,0>: Cost 4 vsldoi4 <3,1,6,5>, LHS + 4179813619U, // <1,6,5,1>: Cost 4 vsldoi4 <3,1,6,5>, <1,6,5,7> + 3540207325U, // <1,6,5,2>: Cost 4 vmrglw , <2,3,6,2> + 3492432230U, // <1,6,5,3>: Cost 4 vmrglw <0,4,1,5>, <3,2,6,3> + 4179815734U, // <1,6,5,4>: Cost 4 vsldoi4 <3,1,6,5>, RHS + 4191760073U, // <1,6,5,5>: Cost 4 vsldoi4 <5,1,6,5>, <5,1,6,5> + 3540210488U, // <1,6,5,6>: Cost 3 vmrglw , <6,6,6,6> + 2418691382U, // <1,6,5,7>: Cost 2 vmrglw <0,4,1,5>, RHS + 2418691383U, // <1,6,5,u>: Cost 2 vmrglw <0,4,1,5>, RHS + 3395269373U, // <1,6,6,0>: Cost 3 vsldoi12 <6,6,0,1>, <6,6,0,1> + 4167877478U, // <1,6,6,1>: Cost 4 vsldoi4 <1,1,6,6>, <1,1,6,6> + 4167878586U, // <1,6,6,2>: Cost 4 vsldoi4 <1,1,6,6>, <2,6,3,7> + 3491111860U, // <1,6,6,3>: Cost 4 vmrglw <0,2,1,6>, <1,2,6,3> + 4167879990U, // <1,6,6,4>: Cost 4 vsldoi4 <1,1,6,6>, RHS + 4191768266U, // <1,6,6,5>: Cost 4 vsldoi4 <5,1,6,6>, <5,1,6,6> + 3385021240U, // <1,6,6,6>: Cost 3 vsldoi12 <4,u,5,1>, <6,6,6,6> + 3491114294U, // <1,6,6,7>: Cost 3 vmrglw <0,2,1,6>, RHS + 3491114295U, // <1,6,6,u>: Cost 3 vmrglw <0,2,1,6>, RHS + 3395933006U, // <1,6,7,0>: Cost 2 vsldoi12 <6,7,0,1>, <6,7,0,1> + 3396006743U, // <1,6,7,1>: Cost 3 vsldoi12 <6,7,1,1>, <6,7,1,1> + 3369390946U, // <1,6,7,2>: Cost 3 vsldoi12 <2,3,0,1>, <6,7,2,3> + 3385021288U, // <1,6,7,3>: Cost 4 vsldoi12 <4,u,5,1>, <6,7,3,0> + 3385021302U, // <1,6,7,4>: Cost 3 vsldoi12 <4,u,5,1>, <6,7,4,5> + 3499746392U, // <1,6,7,5>: Cost 4 vmrglw <1,6,1,7>, <1,4,6,5> + 3395933066U, // <1,6,7,6>: Cost 3 vsldoi12 <6,7,0,1>, <6,7,6,7> + 3499748662U, // <1,6,7,7>: Cost 3 vmrglw <1,6,1,7>, RHS + 3396522902U, // <1,6,7,u>: Cost 2 vsldoi12 <6,7,u,1>, <6,7,u,1> + 3396596639U, // <1,6,u,0>: Cost 2 vsldoi12 <6,u,0,1>, <6,u,0,1> + 3222681390U, // <1,6,u,1>: Cost 3 vsldoi8 <0,2,1,6>, LHS + 3396744113U, // <1,6,u,2>: Cost 3 vsldoi12 <6,u,2,1>, <6,u,2,1> + 3222681532U, // <1,6,u,3>: Cost 4 vsldoi8 <0,2,1,6>, + 3385021383U, // <1,6,u,4>: Cost 3 vsldoi12 <4,u,5,1>, <6,u,4,5> + 3222681754U, // <1,6,u,5>: Cost 3 vsldoi8 <0,2,1,6>, RHS + 3226663120U, // <1,6,u,6>: Cost 3 vsldoi8 <0,u,1,6>, + 2418715958U, // <1,6,u,7>: Cost 2 vmrglw <0,4,1,u>, RHS + 2418715959U, // <1,6,u,u>: Cost 2 vmrglw <0,4,1,u>, RHS + 3397260272U, // <1,7,0,0>: Cost 3 vsldoi12 <7,0,0,1>, <7,0,0,1> + 3231309926U, // <1,7,0,1>: Cost 3 vsldoi8 <1,6,1,7>, LHS + 3527561640U, // <1,7,0,2>: Cost 4 vmrglw <6,3,1,0>, <6,1,7,2> + 3531543034U, // <1,7,0,3>: Cost 4 vmrglw <7,0,1,0>, <6,2,7,3> + 3397555220U, // <1,7,0,4>: Cost 3 vsldoi12 <7,0,4,1>, <7,0,4,1> + 4191792845U, // <1,7,0,5>: Cost 4 vsldoi4 <5,1,7,0>, <5,1,7,0> + 3225338358U, // <1,7,0,6>: Cost 3 vsldoi8 <0,6,1,7>, <0,6,1,7> + 3226001991U, // <1,7,0,7>: Cost 3 vsldoi8 <0,7,1,7>, <0,7,1,7> + 3231310482U, // <1,7,0,u>: Cost 3 vsldoi8 <1,6,1,7>, <0,u,1,1> + 4197769226U, // <1,7,1,0>: Cost 3 vsldoi4 <6,1,7,1>, <0,0,1,1> + 3397997642U, // <1,7,1,1>: Cost 3 vsldoi12 <7,1,1,1>, <7,1,1,1> + 3231310727U, // <1,7,1,2>: Cost 4 vsldoi8 <1,6,1,7>, <1,2,1,3> + 3542831610U, // <1,7,1,3>: Cost 3 vmrglw , <6,2,7,3> + 4197772598U, // <1,7,1,4>: Cost 3 vsldoi4 <6,1,7,1>, RHS + 3255198885U, // <1,7,1,5>: Cost 4 vsldoi8 <5,6,1,7>, <1,5,6,1> + 3231311055U, // <1,7,1,6>: Cost 3 vsldoi8 <1,6,1,7>, <1,6,1,7> + 3542831938U, // <1,7,1,7>: Cost 3 vmrglw , <6,6,7,7> + 3232638321U, // <1,7,1,u>: Cost 3 vsldoi8 <1,u,1,7>, <1,u,1,7> + 4197777510U, // <1,7,2,0>: Cost 3 vsldoi4 <6,1,7,2>, LHS + 3362968661U, // <1,7,2,1>: Cost 3 vmrghw <1,2,3,0>, <7,1,2,3> + 3507671464U, // <1,7,2,2>: Cost 3 vmrglw <3,0,1,2>, <6,1,7,2> + 4197779606U, // <1,7,2,3>: Cost 3 vsldoi4 <6,1,7,2>, <3,0,1,2> + 4197780790U, // <1,7,2,4>: Cost 3 vsldoi4 <6,1,7,2>, RHS + 3519615403U, // <1,7,2,5>: Cost 4 vmrglw <5,0,1,2>, <6,1,7,5> + 4197781928U, // <1,7,2,6>: Cost 3 vsldoi4 <6,1,7,2>, <6,1,7,2> + 3531559179U, // <1,7,2,7>: Cost 3 vmrglw <7,0,1,2>, <5,u,7,7> + 4197783342U, // <1,7,2,u>: Cost 3 vsldoi4 <6,1,7,2>, LHS + 3399251171U, // <1,7,3,0>: Cost 3 vsldoi12 <7,3,0,1>, <7,3,0,1> + 3231312147U, // <1,7,3,1>: Cost 4 vsldoi8 <1,6,1,7>, <3,1,6,1> + 4197787302U, // <1,7,3,2>: Cost 4 vsldoi4 <6,1,7,3>, <2,3,0,1> + 3231312284U, // <1,7,3,3>: Cost 4 vsldoi8 <1,6,1,7>, <3,3,3,3> + 3231312386U, // <1,7,3,4>: Cost 4 vsldoi8 <1,6,1,7>, <3,4,5,6> + 3255200343U, // <1,7,3,5>: Cost 4 vsldoi8 <5,6,1,7>, <3,5,6,1> + 3243256449U, // <1,7,3,6>: Cost 4 vsldoi8 <3,6,1,7>, <3,6,1,7> + 3378017569U, // <1,7,3,7>: Cost 4 vsldoi12 <3,7,0,1>, <7,3,7,0> + 3399841067U, // <1,7,3,u>: Cost 3 vsldoi12 <7,3,u,1>, <7,3,u,1> + 3399914804U, // <1,7,4,0>: Cost 3 vsldoi12 <7,4,0,1>, <7,4,0,1> + 4197795023U, // <1,7,4,1>: Cost 4 vsldoi4 <6,1,7,4>, <1,6,1,7> + 3369391432U, // <1,7,4,2>: Cost 4 vsldoi12 <2,3,0,1>, <7,4,2,3> + 3531575802U, // <1,7,4,3>: Cost 4 vmrglw <7,0,1,4>, <6,2,7,3> + 3385021787U, // <1,7,4,4>: Cost 4 vsldoi12 <4,u,5,1>, <7,4,4,4> + 3231313206U, // <1,7,4,5>: Cost 3 vsldoi8 <1,6,1,7>, RHS + 3249229146U, // <1,7,4,6>: Cost 4 vsldoi8 <4,6,1,7>, <4,6,1,7> + 4191827302U, // <1,7,4,7>: Cost 4 vsldoi4 <5,1,7,4>, <7,4,5,6> + 3231313449U, // <1,7,4,u>: Cost 3 vsldoi8 <1,6,1,7>, RHS + 4197802086U, // <1,7,5,0>: Cost 3 vsldoi4 <6,1,7,5>, LHS + 3385021845U, // <1,7,5,1>: Cost 4 vsldoi12 <4,u,5,1>, <7,5,1,u> + 4179888058U, // <1,7,5,2>: Cost 4 vsldoi4 <3,1,7,5>, <2,6,3,7> + 3540210170U, // <1,7,5,3>: Cost 3 vmrglw , <6,2,7,3> + 4197805366U, // <1,7,5,4>: Cost 3 vsldoi4 <6,1,7,5>, RHS + 3492434347U, // <1,7,5,5>: Cost 3 vmrglw <0,4,1,5>, <6,1,7,5> + 3255201843U, // <1,7,5,6>: Cost 3 vsldoi8 <5,6,1,7>, <5,6,1,7> + 3540210498U, // <1,7,5,7>: Cost 3 vmrglw , <6,6,7,7> + 3256529109U, // <1,7,5,u>: Cost 3 vsldoi8 <5,u,1,7>, <5,u,1,7> + 3540881506U, // <1,7,6,0>: Cost 3 vmrglw , <5,6,7,0> + 3231314342U, // <1,7,6,1>: Cost 4 vsldoi8 <1,6,1,7>, <6,1,7,0> + 4179896250U, // <1,7,6,2>: Cost 4 vsldoi4 <3,1,7,6>, <2,6,3,7> + 4179896609U, // <1,7,6,3>: Cost 4 vsldoi4 <3,1,7,6>, <3,1,7,6> + 4179897654U, // <1,7,6,4>: Cost 4 vsldoi4 <3,1,7,6>, RHS + 3395122697U, // <1,7,6,5>: Cost 4 vsldoi12 <6,5,7,1>, <7,6,5,7> + 3385021969U, // <1,7,6,6>: Cost 4 vsldoi12 <4,u,5,1>, <7,6,6,6> + 3395933716U, // <1,7,6,7>: Cost 3 vsldoi12 <6,7,0,1>, <7,6,7,0> + 3396597277U, // <1,7,6,u>: Cost 3 vsldoi12 <6,u,0,1>, <7,6,u,0> + 3401905703U, // <1,7,7,0>: Cost 3 vsldoi12 <7,7,0,1>, <7,7,0,1> + 3499746154U, // <1,7,7,1>: Cost 4 vmrglw <1,6,1,7>, <1,1,7,1> + 4197820070U, // <1,7,7,2>: Cost 4 vsldoi4 <6,1,7,7>, <2,3,0,1> + 3499746237U, // <1,7,7,3>: Cost 4 vmrglw <1,6,1,7>, <1,2,7,3> + 3385022031U, // <1,7,7,4>: Cost 4 vsldoi12 <4,u,5,1>, <7,7,4,5> + 4191850196U, // <1,7,7,5>: Cost 4 vsldoi4 <5,1,7,7>, <5,1,7,7> + 4197822893U, // <1,7,7,6>: Cost 4 vsldoi4 <6,1,7,7>, <6,1,7,7> + 3385022060U, // <1,7,7,7>: Cost 3 vsldoi12 <4,u,5,1>, <7,7,7,7> + 3402495599U, // <1,7,7,u>: Cost 3 vsldoi12 <7,7,u,1>, <7,7,u,1> + 4197826577U, // <1,7,u,0>: Cost 3 vsldoi4 <6,1,7,u>, <0,0,1,u> + 3231315758U, // <1,7,u,1>: Cost 3 vsldoi8 <1,6,1,7>, LHS + 3507671464U, // <1,7,u,2>: Cost 3 vmrglw <3,0,1,2>, <6,1,7,2> + 3531608570U, // <1,7,u,3>: Cost 3 vmrglw <7,0,1,u>, <6,2,7,3> + 4197829942U, // <1,7,u,4>: Cost 3 vsldoi4 <6,1,7,u>, RHS + 3231316122U, // <1,7,u,5>: Cost 3 vsldoi8 <1,6,1,7>, RHS + 4197831086U, // <1,7,u,6>: Cost 3 vsldoi4 <6,1,7,u>, <6,1,7,u> + 3531608898U, // <1,7,u,7>: Cost 3 vmrglw <7,0,1,u>, <6,6,7,7> + 3231316325U, // <1,7,u,u>: Cost 3 vsldoi8 <1,6,1,7>, LHS + 3221364753U, // <1,u,0,0>: Cost 2 vsldoi8 <0,0,1,u>, <0,0,1,u> + 3224019046U, // <1,u,0,1>: Cost 2 vsldoi8 <0,4,1,u>, LHS + 3222692019U, // <1,u,0,2>: Cost 3 vsldoi8 <0,2,1,u>, <0,2,1,u> + 3491725468U, // <1,u,0,3>: Cost 3 vmrglw <0,3,1,0>, LHS + 3224019285U, // <1,u,0,4>: Cost 2 vsldoi8 <0,4,1,u>, <0,4,1,u> + 3403601654U, // <1,u,0,5>: Cost 2 vsldoi12 , + 3225346551U, // <1,u,0,6>: Cost 3 vsldoi8 <0,6,1,u>, <0,6,1,u> + 3491728712U, // <1,u,0,7>: Cost 3 vmrglw <0,3,1,0>, RHS + 3224019613U, // <1,u,0,u>: Cost 2 vsldoi8 <0,4,1,u>, LHS + 3093725286U, // <1,u,1,0>: Cost 2 vsldoi4 <1,1,1,1>, LHS + 1611448422U, // <1,u,1,1>: Cost 1 vspltisw1 LHS + 3360839470U, // <1,u,1,2>: Cost 2 vsldoi12 <0,u,1,1>, LHS + 2421309596U, // <1,u,1,3>: Cost 2 vmrglw <0,u,1,1>, LHS + 3093728566U, // <1,u,1,4>: Cost 2 vsldoi4 <1,1,1,1>, RHS + 2288425114U, // <1,u,1,5>: Cost 2 vmrghw <1,1,1,1>, RHS + 3224020238U, // <1,u,1,6>: Cost 3 vsldoi8 <0,4,1,u>, <1,6,u,7> + 2421312840U, // <1,u,1,7>: Cost 2 vmrglw <0,u,1,1>, RHS + 1611448422U, // <1,u,1,u>: Cost 1 vspltisw1 LHS + 3362969299U, // <1,u,2,0>: Cost 3 vmrghw <1,2,3,0>, + 2289227566U, // <1,u,2,1>: Cost 2 vmrghw <1,2,3,0>, LHS + 2289222550U, // <1,u,2,2>: Cost 2 vmrghw <1,2,3,0>, <1,2,3,0> + 2433925276U, // <1,u,2,3>: Cost 2 vmrglw <3,0,1,2>, LHS + 3362969663U, // <1,u,2,4>: Cost 3 vmrghw <1,2,3,0>, + 2289227930U, // <1,u,2,5>: Cost 2 vmrghw <1,2,3,0>, RHS + 3224020922U, // <1,u,2,6>: Cost 3 vsldoi8 <0,4,1,u>, <2,6,3,7> + 2433928520U, // <1,u,2,7>: Cost 2 vmrglw <3,0,1,2>, RHS + 2289228133U, // <1,u,2,u>: Cost 2 vmrghw <1,2,3,0>, LHS + 2014544028U, // <1,u,3,0>: Cost 1 vsldoi4 LHS, LHS + 3088286516U, // <1,u,3,1>: Cost 2 vsldoi4 LHS, <1,1,1,1> + 3088287336U, // <1,u,3,2>: Cost 2 vsldoi4 LHS, <2,2,2,2> + 3088287894U, // <1,u,3,3>: Cost 2 vsldoi4 LHS, <3,0,1,2> + 2014547254U, // <1,u,3,4>: Cost 1 vsldoi4 LHS, RHS + 3136065540U, // <1,u,3,5>: Cost 2 vsldoi4 LHS, <5,5,5,5> + 3136066042U, // <1,u,3,6>: Cost 2 vsldoi4 LHS, <6,2,7,3> + 3136066554U, // <1,u,3,7>: Cost 2 vsldoi4 LHS, <7,0,1,2> + 2014549806U, // <1,u,3,u>: Cost 1 vsldoi4 LHS, LHS + 3245255541U, // <1,u,4,0>: Cost 3 vsldoi8 <4,0,1,u>, <4,0,1,u> + 3224022013U, // <1,u,4,1>: Cost 3 vsldoi8 <0,4,1,u>, <4,1,u,0> + 3364258710U, // <1,u,4,2>: Cost 3 vmrghw <1,4,2,5>, <1,2,3,0> + 3491758236U, // <1,u,4,3>: Cost 3 vmrglw <0,3,1,4>, LHS + 4185926657U, // <1,u,4,4>: Cost 3 vsldoi4 <4,1,u,4>, <4,1,u,4> + 3224022326U, // <1,u,4,5>: Cost 2 vsldoi8 <0,4,1,u>, RHS + 3491760642U, // <1,u,4,6>: Cost 3 vmrglw <0,3,1,4>, <3,4,5,6> + 3491761480U, // <1,u,4,7>: Cost 3 vmrglw <0,3,1,4>, RHS + 3224022569U, // <1,u,4,u>: Cost 2 vsldoi8 <0,4,1,u>, RHS + 3492430787U, // <1,u,5,0>: Cost 3 vmrglw <0,4,1,5>, <1,2,u,0> + 3492431598U, // <1,u,5,1>: Cost 3 vmrglw <0,4,1,5>, <2,3,u,1> + 3492432085U, // <1,u,5,2>: Cost 3 vmrglw <0,4,1,5>, <3,0,u,2> + 2418688156U, // <1,u,5,3>: Cost 2 vmrglw <0,4,1,5>, LHS + 3492430791U, // <1,u,5,4>: Cost 3 vmrglw <0,4,1,5>, <1,2,u,4> + 2418688338U, // <1,u,5,5>: Cost 2 vmrglw <0,4,1,5>, <0,4,1,5> + 3360839834U, // <1,u,5,6>: Cost 2 vsldoi12 <0,u,1,1>, RHS + 2418691400U, // <1,u,5,7>: Cost 2 vmrglw <0,4,1,5>, RHS + 2418688161U, // <1,u,5,u>: Cost 2 vmrglw <0,4,1,5>, LHS + 3257200935U, // <1,u,6,0>: Cost 3 vsldoi8 <6,0,1,u>, <6,0,1,u> + 3361355966U, // <1,u,6,1>: Cost 3 vsldoi12 <0,u,u,1>, + 3263173114U, // <1,u,6,2>: Cost 3 vsldoi8 <7,0,1,u>, <6,2,7,3> + 3491111068U, // <1,u,6,3>: Cost 3 vmrglw <0,2,1,6>, LHS + 3365822802U, // <1,u,6,4>: Cost 3 vmrghw <1,6,5,7>, <0,4,1,5> + 3365533850U, // <1,u,6,5>: Cost 3 vmrghw <1,6,1,7>, RHS + 3263173432U, // <1,u,6,6>: Cost 3 vsldoi8 <7,0,1,u>, <6,6,6,6> + 3491114312U, // <1,u,6,7>: Cost 3 vmrglw <0,2,1,6>, RHS + 3491111073U, // <1,u,6,u>: Cost 3 vmrglw <0,2,1,6>, LHS + 3263173632U, // <1,u,7,0>: Cost 2 vsldoi8 <7,0,1,u>, <7,0,1,u> + 3541549777U, // <1,u,7,1>: Cost 3 vmrglw , <0,u,u,1> + 3369392404U, // <1,u,7,2>: Cost 3 vsldoi12 <2,3,0,1>, + 3499745436U, // <1,u,7,3>: Cost 3 vmrglw <1,6,1,7>, LHS + 3385022760U, // <1,u,7,4>: Cost 3 vsldoi12 <4,u,5,1>, + 3499745681U, // <1,u,7,5>: Cost 4 vmrglw <1,6,1,7>, <0,4,u,5> + 3395934524U, // <1,u,7,6>: Cost 3 vsldoi12 <6,7,0,1>, + 3499748680U, // <1,u,7,7>: Cost 3 vmrglw <1,6,1,7>, RHS + 3268482696U, // <1,u,7,u>: Cost 2 vsldoi8 <7,u,1,u>, <7,u,1,u> + 2014584993U, // <1,u,u,0>: Cost 1 vsldoi4 LHS, LHS + 1611448422U, // <1,u,u,1>: Cost 1 vspltisw1 LHS + 3088328296U, // <1,u,u,2>: Cost 2 vsldoi4 LHS, <2,2,2,2> + 3088328854U, // <1,u,u,3>: Cost 2 vsldoi4 LHS, <3,0,1,2> + 2014588214U, // <1,u,u,4>: Cost 1 vsldoi4 LHS, RHS + 3224025242U, // <1,u,u,5>: Cost 2 vsldoi8 <0,4,1,u>, RHS + 3360840077U, // <1,u,u,6>: Cost 2 vsldoi12 <0,u,1,1>, RHS + 2418715976U, // <1,u,u,7>: Cost 2 vmrglw <0,4,1,u>, RHS + 2014590766U, // <1,u,u,u>: Cost 1 vsldoi4 LHS, LHS + 3367608320U, // <2,0,0,0>: Cost 3 vmrghw <2,0,3,0>, <0,0,0,0> + 3367608422U, // <2,0,0,1>: Cost 3 vmrghw <2,0,3,0>, LHS + 3356860435U, // <2,0,0,2>: Cost 4 vsldoi12 <0,2,1,2>, <0,0,2,1> + 3373449244U, // <2,0,0,3>: Cost 4 vsldoi12 <3,0,1,2>, <0,0,3,1> + 3367608658U, // <2,0,0,4>: Cost 4 vmrghw <2,0,3,0>, <0,4,1,5> + 3490474452U, // <2,0,0,5>: Cost 4 vmrglw <0,1,2,0>, <3,4,0,5> + 3355902008U, // <2,0,0,6>: Cost 4 vsldoi12 <0,0,6,2>, <0,0,6,2> + 3226018377U, // <2,0,0,7>: Cost 4 vsldoi8 <0,7,2,0>, <0,7,2,0> + 3367608989U, // <2,0,0,u>: Cost 3 vmrghw <2,0,3,0>, LHS + 3368280074U, // <2,0,1,0>: Cost 3 vmrghw <2,1,3,1>, <0,0,1,1> + 3368280166U, // <2,0,1,1>: Cost 3 vmrghw <2,1,3,1>, LHS + 3368878182U, // <2,0,1,2>: Cost 2 vsldoi12 <2,2,2,2>, LHS + 4209862869U, // <2,0,1,3>: Cost 3 vsldoi4 , <3,0,u,2> + 3368313170U, // <2,0,1,4>: Cost 3 vmrghw <2,1,3,5>, <0,4,1,5> + 4191948512U, // <2,0,1,5>: Cost 4 vsldoi4 <5,2,0,1>, <5,2,0,1> + 3397337230U, // <2,0,1,6>: Cost 4 vsldoi12 <7,0,1,2>, <0,1,6,7> + 3501099640U, // <2,0,1,7>: Cost 4 vmrglw <1,u,2,1>, <3,6,0,7> + 3368878236U, // <2,0,1,u>: Cost 2 vsldoi12 <2,2,2,2>, LHS + 3368878080U, // <2,0,2,0>: Cost 3 vmrghw <2,2,2,2>, <0,0,0,0> + 2295136358U, // <2,0,2,1>: Cost 2 vmrghw <2,2,2,2>, LHS + 3368878253U, // <2,0,2,2>: Cost 3 vmrghw <2,2,2,2>, <0,2,1,2> + 3368878332U, // <2,0,2,3>: Cost 4 vmrghw <2,2,2,2>, <0,3,1,0> + 3368878418U, // <2,0,2,4>: Cost 3 vmrghw <2,2,2,2>, <0,4,1,5> + 3368878499U, // <2,0,2,5>: Cost 4 vmrghw <2,2,2,2>, <0,5,1,5> + 3243935674U, // <2,0,2,6>: Cost 4 vsldoi8 <3,7,2,0>, <2,6,3,7> + 3503098488U, // <2,0,2,7>: Cost 4 vmrglw <2,2,2,2>, <3,6,0,7> + 2295136925U, // <2,0,2,u>: Cost 2 vmrghw <2,2,2,2>, LHS + 2421399552U, // <2,0,3,0>: Cost 2 vmrglw LHS, <0,0,0,0> + 2421401254U, // <2,0,3,1>: Cost 2 vmrglw LHS, <2,3,0,1> + 3369386158U, // <2,0,3,2>: Cost 3 vmrghw <2,3,0,1>, <0,2,1,3> + 4180019504U, // <2,0,3,3>: Cost 3 vsldoi4 <3,2,0,3>, <3,2,0,3> + 3495142514U, // <2,0,3,4>: Cost 3 vmrglw LHS, <1,5,0,4> + 4203909218U, // <2,0,3,5>: Cost 3 vsldoi4 <7,2,0,3>, <5,6,7,0> + 3369386486U, // <2,0,3,6>: Cost 3 vmrghw <2,3,0,1>, <0,6,1,7> + 4203910292U, // <2,0,3,7>: Cost 3 vsldoi4 <7,2,0,3>, <7,2,0,3> + 2421401261U, // <2,0,3,u>: Cost 2 vmrglw LHS, <2,3,0,u> + 3503112192U, // <2,0,4,0>: Cost 4 vmrglw <2,2,2,4>, <0,0,0,0> + 3368878418U, // <2,0,4,1>: Cost 3 vsldoi12 <2,2,2,2>, <0,4,1,5> + 3356860763U, // <2,0,4,2>: Cost 4 vsldoi12 <0,2,1,2>, <0,4,2,5> + 3373449572U, // <2,0,4,3>: Cost 4 vsldoi12 <3,0,1,2>, <0,4,3,5> + 3368878445U, // <2,0,4,4>: Cost 4 vsldoi12 <2,2,2,2>, <0,4,4,5> + 3269815606U, // <2,0,4,5>: Cost 3 vsldoi8 , RHS + 3260525945U, // <2,0,4,6>: Cost 4 vsldoi8 <6,5,2,0>, <4,6,5,2> + 3397337480U, // <2,0,4,7>: Cost 4 vsldoi12 <7,0,1,2>, <0,4,7,5> + 3368878481U, // <2,0,4,u>: Cost 3 vsldoi12 <2,2,2,2>, <0,4,u,5> + 3498475520U, // <2,0,5,0>: Cost 4 vmrglw <1,4,2,5>, <0,0,0,0> + 3370975334U, // <2,0,5,1>: Cost 3 vmrghw <2,5,3,6>, LHS + 3371344048U, // <2,0,5,2>: Cost 4 vmrghw <2,5,u,6>, <0,2,1,5> + 3498477872U, // <2,0,5,3>: Cost 4 vmrglw <1,4,2,5>, <3,2,0,3> + 3370926418U, // <2,0,5,4>: Cost 4 vmrghw <2,5,3,0>, <0,4,1,5> + 3498477874U, // <2,0,5,5>: Cost 4 vmrglw <1,4,2,5>, <3,2,0,5> + 3397337554U, // <2,0,5,6>: Cost 4 vsldoi12 <7,0,1,2>, <0,5,6,7> + 3498478200U, // <2,0,5,7>: Cost 4 vmrglw <1,4,2,5>, <3,6,0,7> + 3370975901U, // <2,0,5,u>: Cost 3 vmrghw <2,5,3,6>, LHS + 3371646976U, // <2,0,6,0>: Cost 3 vmrghw <2,6,3,7>, <0,0,0,0> + 2297905254U, // <2,0,6,1>: Cost 2 vmrghw <2,6,3,7>, LHS + 3371647153U, // <2,0,6,2>: Cost 3 vmrghw <2,6,3,7>, <0,2,1,6> + 3371647228U, // <2,0,6,3>: Cost 4 vmrghw <2,6,3,7>, <0,3,1,0> + 3371647314U, // <2,0,6,4>: Cost 3 vmrghw <2,6,3,7>, <0,4,1,5> + 3260527293U, // <2,0,6,5>: Cost 4 vsldoi8 <6,5,2,0>, <6,5,2,0> + 3371647478U, // <2,0,6,6>: Cost 4 vmrghw <2,6,3,7>, <0,6,1,7> + 3261854559U, // <2,0,6,7>: Cost 4 vsldoi8 <6,7,2,0>, <6,7,2,0> + 2297905821U, // <2,0,6,u>: Cost 2 vmrghw <2,6,3,7>, LHS + 3505790976U, // <2,0,7,0>: Cost 4 vmrglw <2,6,2,7>, <0,0,0,0> + 3372040294U, // <2,0,7,1>: Cost 3 vmrghw <2,7,0,1>, LHS + 3264509091U, // <2,0,7,2>: Cost 4 vsldoi8 <7,2,2,0>, <7,2,2,0> + 3265172724U, // <2,0,7,3>: Cost 4 vsldoi8 <7,3,2,0>, <7,3,2,0> + 3269817702U, // <2,0,7,4>: Cost 4 vsldoi8 , <7,4,5,6> + 3490535036U, // <2,0,7,5>: Cost 4 vmrglw <0,1,2,7>, <7,u,0,5> + 3267163623U, // <2,0,7,6>: Cost 4 vsldoi8 <7,6,2,0>, <7,6,2,0> + 3269817964U, // <2,0,7,7>: Cost 4 vsldoi8 , <7,7,7,7> + 3372040861U, // <2,0,7,u>: Cost 3 vmrghw <2,7,0,1>, LHS + 2416795648U, // <2,0,u,0>: Cost 2 vmrglw LHS, <0,0,0,0> + 2416797350U, // <2,0,u,1>: Cost 2 vmrglw LHS, <2,3,0,1> + 3368878749U, // <2,0,u,2>: Cost 2 vsldoi12 <2,2,2,2>, LHS + 4180060469U, // <2,0,u,3>: Cost 3 vsldoi4 <3,2,0,u>, <3,2,0,u> + 3490539177U, // <2,0,u,4>: Cost 3 vmrglw LHS, <2,3,0,4> + 4203950178U, // <2,0,u,5>: Cost 3 vsldoi4 <7,2,0,u>, <5,6,7,0> + 3369386486U, // <2,0,u,6>: Cost 3 vmrghw <2,3,0,1>, <0,6,1,7> + 4203951257U, // <2,0,u,7>: Cost 3 vsldoi4 <7,2,0,u>, <7,2,0,u> + 2416797357U, // <2,0,u,u>: Cost 2 vmrglw LHS, <2,3,0,u> + 4162150571U, // <2,1,0,0>: Cost 4 vsldoi4 <0,2,1,0>, <0,2,1,0> + 3361506020U, // <2,1,0,1>: Cost 3 vsldoi12 <1,0,1,2>, <1,0,1,2> + 3538250526U, // <2,1,0,2>: Cost 3 vmrglw , <3,u,1,2> + 3373449972U, // <2,1,0,3>: Cost 4 vsldoi12 <3,0,1,2>, <1,0,3,0> + 4162153782U, // <2,1,0,4>: Cost 4 vsldoi4 <0,2,1,0>, RHS + 3367642226U, // <2,1,0,5>: Cost 4 vmrghw <2,0,3,4>, <1,5,0,4> + 3257213425U, // <2,1,0,6>: Cost 4 vsldoi8 <6,0,2,1>, <0,6,1,2> + 3508388342U, // <2,1,0,7>: Cost 5 vmrglw <3,1,2,0>, <0,6,1,7> + 3362022179U, // <2,1,0,u>: Cost 3 vsldoi12 <1,0,u,2>, <1,0,u,2> + 3227353836U, // <2,1,1,0>: Cost 3 vsldoi8 <1,0,2,1>, <1,0,2,1> + 3368878900U, // <2,1,1,1>: Cost 3 vsldoi12 <2,2,2,2>, <1,1,1,1> + 3232662422U, // <2,1,1,2>: Cost 3 vsldoi8 <1,u,2,1>, <1,2,3,0> + 3496452999U, // <2,1,1,3>: Cost 4 vmrglw <1,1,2,1>, <1,2,1,3> + 4162161974U, // <2,1,1,4>: Cost 4 vsldoi4 <0,2,1,1>, RHS + 3362464601U, // <2,1,1,5>: Cost 4 vsldoi12 <1,1,5,2>, <1,1,5,2> + 3368314099U, // <2,1,1,6>: Cost 4 vmrghw <2,1,3,5>, <1,6,5,7> + 3231999267U, // <2,1,1,7>: Cost 4 vsldoi8 <1,7,2,1>, <1,7,2,1> + 3232662900U, // <2,1,1,u>: Cost 3 vsldoi8 <1,u,2,1>, <1,u,2,1> + 4162166957U, // <2,1,2,0>: Cost 3 vsldoi4 <0,2,1,2>, <0,2,1,2> + 3368878900U, // <2,1,2,1>: Cost 3 vmrghw <2,2,2,2>, <1,1,1,1> + 4162168424U, // <2,1,2,2>: Cost 3 vsldoi4 <0,2,1,2>, <2,2,2,2> + 3362980760U, // <2,1,2,3>: Cost 3 vsldoi12 <1,2,3,2>, <1,2,3,2> + 4162170166U, // <2,1,2,4>: Cost 3 vsldoi4 <0,2,1,2>, RHS + 3503096146U, // <2,1,2,5>: Cost 3 vmrglw <2,2,2,2>, <0,4,1,5> + 3232663464U, // <2,1,2,6>: Cost 4 vsldoi8 <1,u,2,1>, <2,6,1,7> + 3397338042U, // <2,1,2,7>: Cost 3 vsldoi12 <7,0,1,2>, <1,2,7,0> + 4162172718U, // <2,1,2,u>: Cost 3 vsldoi4 <0,2,1,2>, LHS + 3490496521U, // <2,1,3,0>: Cost 3 vmrglw LHS, <0,0,1,0> + 2416754698U, // <2,1,3,1>: Cost 2 vmrglw LHS, <0,0,1,1> + 2421401750U, // <2,1,3,2>: Cost 2 vmrglw LHS, <3,0,1,2> + 3495141550U, // <2,1,3,3>: Cost 3 vmrglw LHS, <0,2,1,3> + 4162178358U, // <2,1,3,4>: Cost 3 vsldoi4 <0,2,1,3>, RHS + 2416755026U, // <2,1,3,5>: Cost 2 vmrglw LHS, <0,4,1,5> + 3495141553U, // <2,1,3,6>: Cost 3 vmrglw LHS, <0,2,1,6> + 3495142607U, // <2,1,3,7>: Cost 3 vmrglw LHS, <1,6,1,7> + 2416754705U, // <2,1,3,u>: Cost 2 vmrglw LHS, <0,0,1,u> + 4162183343U, // <2,1,4,0>: Cost 4 vsldoi4 <0,2,1,4>, <0,2,1,4> + 3368879147U, // <2,1,4,1>: Cost 4 vsldoi12 <2,2,2,2>, <1,4,1,5> + 3538283294U, // <2,1,4,2>: Cost 3 vmrglw , <3,u,1,2> + 4162185366U, // <2,1,4,3>: Cost 5 vsldoi4 <0,2,1,4>, <3,0,1,2> + 4162186550U, // <2,1,4,4>: Cost 4 vsldoi4 <0,2,1,4>, RHS + 3232664886U, // <2,1,4,5>: Cost 3 vsldoi8 <1,u,2,1>, RHS + 3262524793U, // <2,1,4,6>: Cost 4 vsldoi8 <6,u,2,1>, <4,6,5,2> + 3503113423U, // <2,1,4,7>: Cost 5 vmrglw <2,2,2,4>, <1,6,1,7> + 3232665129U, // <2,1,4,u>: Cost 3 vsldoi8 <1,u,2,1>, RHS + 4162191536U, // <2,1,5,0>: Cost 4 vsldoi4 <0,2,1,5>, <0,2,1,5> + 3498475530U, // <2,1,5,1>: Cost 4 vmrglw <1,4,2,5>, <0,0,1,1> + 4162193301U, // <2,1,5,2>: Cost 4 vsldoi4 <0,2,1,5>, <2,5,u,6> + 4162193922U, // <2,1,5,3>: Cost 4 vsldoi4 <0,2,1,5>, <3,4,5,6> + 4162194742U, // <2,1,5,4>: Cost 4 vsldoi4 <0,2,1,5>, RHS + 3498475858U, // <2,1,5,5>: Cost 4 vmrglw <1,4,2,5>, <0,4,1,5> + 3370984691U, // <2,1,5,6>: Cost 4 vmrghw <2,5,3,7>, <1,6,5,7> + 3397338285U, // <2,1,5,7>: Cost 4 vsldoi12 <7,0,1,2>, <1,5,7,0> + 4162197294U, // <2,1,5,u>: Cost 4 vsldoi4 <0,2,1,5>, LHS + 4162199729U, // <2,1,6,0>: Cost 3 vsldoi4 <0,2,1,6>, <0,2,1,6> + 3371647796U, // <2,1,6,1>: Cost 3 vmrghw <2,6,3,7>, <1,1,1,1> + 4162201530U, // <2,1,6,2>: Cost 3 vsldoi4 <0,2,1,6>, <2,6,3,7> + 4162201750U, // <2,1,6,3>: Cost 4 vsldoi4 <0,2,1,6>, <3,0,1,2> + 4162202934U, // <2,1,6,4>: Cost 3 vsldoi4 <0,2,1,6>, RHS + 3499147602U, // <2,1,6,5>: Cost 4 vmrglw <1,5,2,6>, <0,4,1,5> + 4162204472U, // <2,1,6,6>: Cost 4 vsldoi4 <0,2,1,6>, <6,6,6,6> + 3261862752U, // <2,1,6,7>: Cost 4 vsldoi8 <6,7,2,1>, <6,7,2,1> + 4162205486U, // <2,1,6,u>: Cost 3 vsldoi4 <0,2,1,6>, LHS + 3262526458U, // <2,1,7,0>: Cost 4 vsldoi8 <6,u,2,1>, <7,0,1,2> + 3505790986U, // <2,1,7,1>: Cost 4 vmrglw <2,6,2,7>, <0,0,1,1> + 3538310786U, // <2,1,7,2>: Cost 3 vmrglw , <7,u,1,2> + 3262526746U, // <2,1,7,3>: Cost 4 vsldoi8 <6,u,2,1>, <7,3,6,2> + 3262526822U, // <2,1,7,4>: Cost 4 vsldoi8 <6,u,2,1>, <7,4,5,6> + 3505791314U, // <2,1,7,5>: Cost 4 vmrglw <2,6,2,7>, <0,4,1,5> + 3262526958U, // <2,1,7,6>: Cost 4 vsldoi8 <6,u,2,1>, <7,6,2,7> + 3262527044U, // <2,1,7,7>: Cost 4 vsldoi8 <6,u,2,1>, <7,7,3,3> + 3538310786U, // <2,1,7,u>: Cost 3 vmrglw , <7,u,1,2> + 3490537481U, // <2,1,u,0>: Cost 3 vmrglw LHS, <0,0,1,0> + 2416795658U, // <2,1,u,1>: Cost 2 vmrglw LHS, <0,0,1,1> + 2416797846U, // <2,1,u,2>: Cost 2 vmrglw LHS, <3,0,1,2> + 3490537646U, // <2,1,u,3>: Cost 3 vmrglw LHS, <0,2,1,3> + 3490537485U, // <2,1,u,4>: Cost 3 vmrglw LHS, <0,0,1,4> + 2416795986U, // <2,1,u,5>: Cost 2 vmrglw LHS, <0,4,1,5> + 3490537649U, // <2,1,u,6>: Cost 3 vmrglw LHS, <0,2,1,6> + 3495183567U, // <2,1,u,7>: Cost 3 vmrglw LHS, <1,6,1,7> + 2416795665U, // <2,1,u,u>: Cost 2 vmrglw LHS, <0,0,1,u> + 3367609805U, // <2,2,0,0>: Cost 3 vmrghw <2,0,3,0>, <2,0,3,0> + 3234660454U, // <2,2,0,1>: Cost 2 vsldoi8 <2,2,2,2>, LHS + 3234660525U, // <2,2,0,2>: Cost 3 vsldoi8 <2,2,2,2>, <0,2,1,2> + 3367618214U, // <2,2,0,3>: Cost 3 vmrghw <2,0,3,1>, <2,3,0,1> + 3234660690U, // <2,2,0,4>: Cost 3 vsldoi8 <2,2,2,2>, <0,4,1,5> + 3367765864U, // <2,2,0,5>: Cost 4 vmrghw <2,0,5,1>, <2,5,3,6> + 3367839674U, // <2,2,0,6>: Cost 3 vmrghw <2,0,6,1>, <2,6,3,7> + 4204033187U, // <2,2,0,7>: Cost 4 vsldoi4 <7,2,2,0>, <7,2,2,0> + 3234661021U, // <2,2,0,u>: Cost 2 vsldoi8 <2,2,2,2>, LHS + 3361506820U, // <2,2,1,0>: Cost 4 vsldoi12 <1,0,1,2>, <2,1,0,1> + 3501098356U, // <2,2,1,1>: Cost 3 vmrglw <1,u,2,1>, <1,u,2,1> + 3234661270U, // <2,2,1,2>: Cost 3 vsldoi8 <2,2,2,2>, <1,2,3,0> + 3501097062U, // <2,2,1,3>: Cost 3 vmrglw <1,u,2,1>, LHS + 3234661419U, // <2,2,1,4>: Cost 4 vsldoi8 <2,2,2,2>, <1,4,1,5> + 3230680194U, // <2,2,1,5>: Cost 4 vsldoi8 <1,5,2,2>, <1,5,2,2> + 3368282042U, // <2,2,1,6>: Cost 4 vmrghw <2,1,3,1>, <2,6,3,7> + 3507070897U, // <2,2,1,7>: Cost 4 vmrglw <2,u,2,1>, <2,6,2,7> + 3501097067U, // <2,2,1,u>: Cost 3 vmrglw <1,u,2,1>, LHS + 3100442726U, // <2,2,2,0>: Cost 2 vsldoi4 <2,2,2,2>, LHS + 3503097285U, // <2,2,2,1>: Cost 3 vmrglw <2,2,2,2>, <2,0,2,1> + 1745666150U, // <2,2,2,2>: Cost 1 vspltisw2 LHS + 2429354086U, // <2,2,2,3>: Cost 2 vmrglw <2,2,2,2>, LHS + 3100446006U, // <2,2,2,4>: Cost 2 vsldoi4 <2,2,2,2>, RHS + 3503097613U, // <2,2,2,5>: Cost 3 vmrglw <2,2,2,2>, <2,4,2,5> + 3368880058U, // <2,2,2,6>: Cost 3 vmrghw <2,2,2,2>, <2,6,3,7> + 4204049573U, // <2,2,2,7>: Cost 3 vsldoi4 <7,2,2,2>, <7,2,2,2> + 1745666150U, // <2,2,2,u>: Cost 1 vspltisw2 LHS + 3234662550U, // <2,2,3,0>: Cost 3 vsldoi8 <2,2,2,2>, <3,0,1,2> + 3369469616U, // <2,2,3,1>: Cost 3 vsldoi12 <2,3,1,2>, <2,3,1,2> + 2421401192U, // <2,2,3,2>: Cost 2 vmrglw LHS, <2,2,2,2> + 1343012966U, // <2,2,3,3>: Cost 1 vmrglw LHS, LHS + 3234662914U, // <2,2,3,4>: Cost 3 vsldoi8 <2,2,2,2>, <3,4,5,6> + 3538273332U, // <2,2,3,5>: Cost 3 vmrglw LHS, <1,4,2,5> + 3495143101U, // <2,2,3,6>: Cost 3 vmrglw LHS, <2,3,2,6> + 4204057766U, // <2,2,3,7>: Cost 3 vsldoi4 <7,2,2,3>, <7,2,2,3> + 1343012971U, // <2,2,3,u>: Cost 1 vmrglw LHS, LHS + 4174200934U, // <2,2,4,0>: Cost 3 vsldoi4 <2,2,2,4>, LHS + 3234663370U, // <2,2,4,1>: Cost 4 vsldoi8 <2,2,2,2>, <4,1,2,3> + 3368879885U, // <2,2,4,2>: Cost 3 vsldoi12 <2,2,2,2>, <2,4,2,5> + 3503112294U, // <2,2,4,3>: Cost 3 vmrglw <2,2,2,4>, LHS + 3503113834U, // <2,2,4,4>: Cost 3 vmrglw <2,2,2,4>, <2,2,2,4> + 3234663734U, // <2,2,4,5>: Cost 2 vsldoi8 <2,2,2,2>, RHS + 3370526650U, // <2,2,4,6>: Cost 3 vmrghw <2,4,6,5>, <2,6,3,7> + 3503114161U, // <2,2,4,7>: Cost 4 vmrglw <2,2,2,4>, <2,6,2,7> + 3234663977U, // <2,2,4,u>: Cost 2 vsldoi8 <2,2,2,2>, RHS + 3234664008U, // <2,2,5,0>: Cost 4 vsldoi8 <2,2,2,2>, <5,0,1,2> + 3498476268U, // <2,2,5,1>: Cost 4 vmrglw <1,4,2,5>, <1,0,2,1> + 3504449128U, // <2,2,5,2>: Cost 3 vmrglw <2,4,2,5>, <2,2,2,2> + 3498475622U, // <2,2,5,3>: Cost 3 vmrglw <1,4,2,5>, LHS + 3234664372U, // <2,2,5,4>: Cost 4 vsldoi8 <2,2,2,2>, <5,4,5,6> + 3498476596U, // <2,2,5,5>: Cost 3 vmrglw <1,4,2,5>, <1,4,2,5> + 3234664546U, // <2,2,5,6>: Cost 3 vsldoi8 <2,2,2,2>, <5,6,7,0> + 3504449457U, // <2,2,5,7>: Cost 4 vmrglw <2,4,2,5>, <2,6,2,7> + 3498475627U, // <2,2,5,u>: Cost 3 vmrglw <1,4,2,5>, LHS + 3371648489U, // <2,2,6,0>: Cost 3 vmrghw <2,6,3,7>, <2,0,6,1> + 3371648543U, // <2,2,6,1>: Cost 4 vmrghw <2,6,3,7>, <2,1,3,1> + 3368880049U, // <2,2,6,2>: Cost 3 vsldoi12 <2,2,2,2>, <2,6,2,7> + 3368880058U, // <2,2,6,3>: Cost 3 vsldoi12 <2,2,2,2>, <2,6,3,7> + 3371648817U, // <2,2,6,4>: Cost 3 vmrghw <2,6,3,7>, <2,4,6,5> + 3371648872U, // <2,2,6,5>: Cost 4 vmrghw <2,6,3,7>, <2,5,3,6> + 2297907130U, // <2,2,6,6>: Cost 2 vmrghw <2,6,3,7>, <2,6,3,7> + 3261870945U, // <2,2,6,7>: Cost 3 vsldoi8 <6,7,2,2>, <6,7,2,2> + 2297907130U, // <2,2,6,u>: Cost 2 vmrghw <2,6,3,7>, <2,6,3,7> + 3397339114U, // <2,2,7,0>: Cost 3 vsldoi12 <7,0,1,2>, <2,7,0,1> + 3505792453U, // <2,2,7,1>: Cost 4 vmrglw <2,6,2,7>, <2,0,2,1> + 3505792616U, // <2,2,7,2>: Cost 3 vmrglw <2,6,2,7>, <2,2,2,2> + 3505791078U, // <2,2,7,3>: Cost 3 vmrglw <2,6,2,7>, LHS + 3234665830U, // <2,2,7,4>: Cost 3 vsldoi8 <2,2,2,2>, <7,4,5,6> + 3505792781U, // <2,2,7,5>: Cost 4 vmrglw <2,6,2,7>, <2,4,2,5> + 3372042161U, // <2,2,7,6>: Cost 4 vmrghw <2,7,0,1>, <2,6,2,7> + 3505792945U, // <2,2,7,7>: Cost 3 vmrglw <2,6,2,7>, <2,6,2,7> + 3505791083U, // <2,2,7,u>: Cost 3 vmrglw <2,6,2,7>, LHS + 3100442726U, // <2,2,u,0>: Cost 2 vsldoi4 <2,2,2,2>, LHS + 3234666286U, // <2,2,u,1>: Cost 2 vsldoi8 <2,2,2,2>, LHS + 1745666150U, // <2,2,u,2>: Cost 1 vspltisw2 LHS + 1343053926U, // <2,2,u,3>: Cost 1 vmrglw LHS, LHS + 3100446006U, // <2,2,u,4>: Cost 2 vsldoi4 <2,2,2,2>, RHS + 3234666650U, // <2,2,u,5>: Cost 2 vsldoi8 <2,2,2,2>, RHS + 2297907130U, // <2,2,u,6>: Cost 2 vmrghw <2,6,3,7>, <2,6,3,7> + 4204098731U, // <2,2,u,7>: Cost 3 vsldoi4 <7,2,2,u>, <7,2,2,u> + 1343053931U, // <2,2,u,u>: Cost 1 vmrglw LHS, LHS + 3222061056U, // <2,3,0,0>: Cost 2 vsldoi8 LHS, <0,0,0,0> + 1074577510U, // <2,3,0,1>: Cost 1 vsldoi8 LHS, LHS + 3226706093U, // <2,3,0,2>: Cost 3 vsldoi8 LHS, <0,2,1,2> + 3226706172U, // <2,3,0,3>: Cost 3 vsldoi8 LHS, <0,3,1,0> + 3222061394U, // <2,3,0,4>: Cost 2 vsldoi8 LHS, <0,4,1,5> + 3269837266U, // <2,3,0,5>: Cost 3 vsldoi8 LHS, <0,5,6,7> + 3269837302U, // <2,3,0,6>: Cost 3 vsldoi8 LHS, <0,6,1,7> + 4204106924U, // <2,3,0,7>: Cost 3 vsldoi4 <7,2,3,0>, <7,2,3,0> + 1074578077U, // <2,3,0,u>: Cost 1 vsldoi8 LHS, LHS + 3226706660U, // <2,3,1,0>: Cost 3 vsldoi8 LHS, <1,0,1,2> + 3222061876U, // <2,3,1,1>: Cost 2 vsldoi8 LHS, <1,1,1,1> + 3222061974U, // <2,3,1,2>: Cost 2 vsldoi8 LHS, <1,2,3,0> + 3226706893U, // <2,3,1,3>: Cost 4 vsldoi8 LHS, <1,3,0,1> + 3226707024U, // <2,3,1,4>: Cost 3 vsldoi8 LHS, <1,4,5,6> + 3226707055U, // <2,3,1,5>: Cost 3 vsldoi8 LHS, <1,5,0,1> + 3226707151U, // <2,3,1,6>: Cost 3 vsldoi8 LHS, <1,6,1,7> + 3501098938U, // <2,3,1,7>: Cost 4 vmrglw <1,u,2,1>, <2,6,3,7> + 3226707324U, // <2,3,1,u>: Cost 2 vsldoi8 LHS, <1,u,3,0> + 3226707405U, // <2,3,2,0>: Cost 3 vsldoi8 LHS, <2,0,3,0> + 3222062623U, // <2,3,2,1>: Cost 3 vsldoi8 LHS, <2,1,3,1> + 3222062696U, // <2,3,2,2>: Cost 2 vsldoi8 LHS, <2,2,2,2> + 3222062758U, // <2,3,2,3>: Cost 2 vsldoi8 LHS, <2,3,0,1> + 3226707734U, // <2,3,2,4>: Cost 3 vsldoi8 LHS, <2,4,3,5> + 3226707816U, // <2,3,2,5>: Cost 3 vsldoi8 LHS, <2,5,3,6> + 3222063034U, // <2,3,2,6>: Cost 2 vsldoi8 LHS, <2,6,3,7> + 3503097786U, // <2,3,2,7>: Cost 3 vmrglw <2,2,2,2>, <2,6,3,7> + 3222063192U, // <2,3,2,u>: Cost 2 vsldoi8 LHS, <2,u,3,3> + 2421400470U, // <2,3,3,0>: Cost 2 vmrglw LHS, <1,2,3,0> + 3490498079U, // <2,3,3,1>: Cost 3 vmrglw LHS, <2,1,3,1> + 3100526194U, // <2,3,3,2>: Cost 2 vsldoi4 <2,2,3,3>, <2,2,3,3> + 2416756338U, // <2,3,3,3>: Cost 2 vmrglw LHS, <2,2,3,3> + 2421400474U, // <2,3,3,4>: Cost 2 vmrglw LHS, <1,2,3,4> + 3490498083U, // <2,3,3,5>: Cost 3 vmrglw LHS, <2,1,3,5> + 3495147646U, // <2,3,3,6>: Cost 3 vmrglw LHS, + 2421401530U, // <2,3,3,7>: Cost 2 vmrglw LHS, <2,6,3,7> + 2416756343U, // <2,3,3,u>: Cost 2 vmrglw LHS, <2,2,3,u> + 3094560870U, // <2,3,4,0>: Cost 2 vsldoi4 <1,2,3,4>, LHS + 3094561690U, // <2,3,4,1>: Cost 2 vsldoi4 <1,2,3,4>, <1,2,3,4> + 4168304232U, // <2,3,4,2>: Cost 3 vsldoi4 <1,2,3,4>, <2,2,2,2> + 4168304790U, // <2,3,4,3>: Cost 3 vsldoi4 <1,2,3,4>, <3,0,1,2> + 3094564150U, // <2,3,4,4>: Cost 2 vsldoi4 <1,2,3,4>, RHS + 1074580790U, // <2,3,4,5>: Cost 1 vsldoi8 LHS, RHS + 3269840249U, // <2,3,4,6>: Cost 3 vsldoi8 LHS, <4,6,5,2> + 4204139696U, // <2,3,4,7>: Cost 3 vsldoi4 <7,2,3,4>, <7,2,3,4> + 1074581033U, // <2,3,4,u>: Cost 1 vsldoi8 LHS, RHS + 3226709576U, // <2,3,5,0>: Cost 3 vsldoi8 LHS, <5,0,1,2> + 3269840527U, // <2,3,5,1>: Cost 3 vsldoi8 LHS, <5,1,0,1> + 3269840619U, // <2,3,5,2>: Cost 3 vsldoi8 LHS, <5,2,1,3> + 3226709809U, // <2,3,5,3>: Cost 4 vsldoi8 LHS, <5,3,0,1> + 3226709940U, // <2,3,5,4>: Cost 3 vsldoi8 LHS, <5,4,5,6> + 3269840900U, // <2,3,5,5>: Cost 2 vsldoi8 LHS, <5,5,5,5> + 3269840994U, // <2,3,5,6>: Cost 2 vsldoi8 LHS, <5,6,7,0> + 3498477498U, // <2,3,5,7>: Cost 4 vmrglw <1,4,2,5>, <2,6,3,7> + 3269841156U, // <2,3,5,u>: Cost 2 vsldoi8 LHS, <5,u,7,0> + 3371649174U, // <2,3,6,0>: Cost 3 vmrghw <2,6,3,7>, <3,0,1,2> + 3269841319U, // <2,3,6,1>: Cost 3 vsldoi8 LHS, <6,1,7,1> + 3269841402U, // <2,3,6,2>: Cost 2 vsldoi8 LHS, <6,2,7,3> + 3371649436U, // <2,3,6,3>: Cost 3 vmrghw <2,6,3,7>, <3,3,3,3> + 3371649538U, // <2,3,6,4>: Cost 3 vmrghw <2,6,3,7>, <3,4,5,6> + 3269841643U, // <2,3,6,5>: Cost 3 vsldoi8 LHS, <6,5,7,1> + 3269841720U, // <2,3,6,6>: Cost 2 vsldoi8 LHS, <6,6,6,6> + 3269841742U, // <2,3,6,7>: Cost 2 vsldoi8 LHS, <6,7,0,1> + 3269841823U, // <2,3,6,u>: Cost 2 vsldoi8 LHS, <6,u,0,1> + 3269841914U, // <2,3,7,0>: Cost 2 vsldoi8 LHS, <7,0,1,2> + 3263870037U, // <2,3,7,1>: Cost 3 vsldoi8 <7,1,2,3>, <7,1,2,3> + 3264533670U, // <2,3,7,2>: Cost 3 vsldoi8 <7,2,2,3>, <7,2,2,3> + 3269842147U, // <2,3,7,3>: Cost 3 vsldoi8 LHS, <7,3,0,1> + 3269842278U, // <2,3,7,4>: Cost 2 vsldoi8 LHS, <7,4,5,6> + 3269842358U, // <2,3,7,5>: Cost 3 vsldoi8 LHS, <7,5,5,5> + 3269842396U, // <2,3,7,6>: Cost 3 vsldoi8 LHS, <7,6,0,7> + 3269842540U, // <2,3,7,7>: Cost 2 vsldoi8 LHS, <7,7,7,7> + 3269842562U, // <2,3,7,u>: Cost 2 vsldoi8 LHS, <7,u,1,2> + 2416796566U, // <2,3,u,0>: Cost 2 vmrglw LHS, <1,2,3,0> + 1074583342U, // <2,3,u,1>: Cost 1 vsldoi8 LHS, LHS + 3226711941U, // <2,3,u,2>: Cost 2 vsldoi8 LHS, + 2416797298U, // <2,3,u,3>: Cost 2 vmrglw LHS, <2,2,3,3> + 2416796570U, // <2,3,u,4>: Cost 2 vmrglw LHS, <1,2,3,4> + 1074583706U, // <2,3,u,5>: Cost 1 vsldoi8 LHS, RHS + 3226712272U, // <2,3,u,6>: Cost 2 vsldoi8 LHS, + 2416797626U, // <2,3,u,7>: Cost 2 vmrglw LHS, <2,6,3,7> + 1074583909U, // <2,3,u,u>: Cost 1 vsldoi8 LHS, LHS + 3234676736U, // <2,4,0,0>: Cost 4 vsldoi8 <2,2,2,4>, <0,0,0,0> + 3234676838U, // <2,4,0,1>: Cost 3 vsldoi8 <2,2,2,4>, LHS + 3234013357U, // <2,4,0,2>: Cost 4 vsldoi8 <2,1,2,4>, <0,2,1,2> + 3269845252U, // <2,4,0,3>: Cost 4 vsldoi8 , <0,3,1,u> + 3234677074U, // <2,4,0,4>: Cost 4 vsldoi8 <2,2,2,4>, <0,4,1,5> + 3367611702U, // <2,4,0,5>: Cost 3 vmrghw <2,0,3,0>, RHS + 3383700379U, // <2,4,0,6>: Cost 4 vsldoi12 <4,6,5,2>, <4,0,6,1> + 3397340068U, // <2,4,0,7>: Cost 4 vsldoi12 <7,0,1,2>, <4,0,7,1> + 3367611945U, // <2,4,0,u>: Cost 3 vmrghw <2,0,3,0>, RHS + 3379424183U, // <2,4,1,0>: Cost 4 vsldoi12 <4,0,1,2>, <4,1,0,2> + 3368315874U, // <2,4,1,1>: Cost 4 vmrghw <2,1,3,5>, <4,1,5,0> + 3229369238U, // <2,4,1,2>: Cost 4 vsldoi8 <1,3,2,4>, <1,2,3,0> + 3229369314U, // <2,4,1,3>: Cost 4 vsldoi8 <1,3,2,4>, <1,3,2,4> + 3368316112U, // <2,4,1,4>: Cost 4 vmrghw <2,1,3,5>, <4,4,4,4> + 3368283446U, // <2,4,1,5>: Cost 3 vmrghw <2,1,3,1>, RHS + 3222070488U, // <2,4,1,6>: Cost 4 vsldoi8 <0,1,2,4>, <1,6,2,7> + 3232023846U, // <2,4,1,7>: Cost 4 vsldoi8 <1,7,2,4>, <1,7,2,4> + 3368283689U, // <2,4,1,u>: Cost 3 vmrghw <2,1,3,1>, RHS + 3368881042U, // <2,4,2,0>: Cost 3 vmrghw <2,2,2,2>, <4,0,5,1> + 3234014745U, // <2,4,2,1>: Cost 4 vsldoi8 <2,1,2,4>, <2,1,2,4> + 3234678378U, // <2,4,2,2>: Cost 3 vsldoi8 <2,2,2,4>, <2,2,2,4> + 3503098196U, // <2,4,2,3>: Cost 4 vmrglw <2,2,2,2>, <3,2,4,3> + 3368881360U, // <2,4,2,4>: Cost 3 vmrghw <2,2,2,2>, <4,4,4,4> + 2295139638U, // <2,4,2,5>: Cost 2 vmrghw <2,2,2,2>, RHS + 3234678705U, // <2,4,2,6>: Cost 4 vsldoi8 <2,2,2,4>, <2,6,2,7> + 3503098524U, // <2,4,2,7>: Cost 4 vmrglw <2,2,2,2>, <3,6,4,7> + 2295139881U, // <2,4,2,u>: Cost 2 vmrghw <2,2,2,2>, RHS + 4180312166U, // <2,4,3,0>: Cost 3 vsldoi4 <3,2,4,3>, LHS + 3495141413U, // <2,4,3,1>: Cost 3 vmrglw LHS, <0,0,4,1> + 3369716790U, // <2,4,3,2>: Cost 3 vmrghw <2,3,4,5>, <4,2,5,3> + 4180314452U, // <2,4,3,3>: Cost 3 vsldoi4 <3,2,4,3>, <3,2,4,3> + 2464533712U, // <2,4,3,4>: Cost 2 vmrglw LHS, <4,4,4,4> + 2421401294U, // <2,4,3,5>: Cost 2 vmrglw LHS, <2,3,4,5> + 3369717118U, // <2,4,3,6>: Cost 3 vmrghw <2,3,4,5>, <4,6,5,7> + 4204205240U, // <2,4,3,7>: Cost 3 vsldoi4 <7,2,4,3>, <7,2,4,3> + 2421401297U, // <2,4,3,u>: Cost 2 vmrglw LHS, <2,3,4,u> + 4174348390U, // <2,4,4,0>: Cost 4 vsldoi4 <2,2,4,4>, LHS + 3245960139U, // <2,4,4,1>: Cost 4 vsldoi8 <4,1,2,4>, <4,1,2,4> + 4174349948U, // <2,4,4,2>: Cost 4 vsldoi4 <2,2,4,4>, <2,2,4,4> + 3503113851U, // <2,4,4,3>: Cost 4 vmrglw <2,2,2,4>, <2,2,4,3> + 3397340368U, // <2,4,4,4>: Cost 3 vsldoi12 <7,0,1,2>, <4,4,4,4> + 3234680118U, // <2,4,4,5>: Cost 3 vsldoi8 <2,2,2,4>, RHS + 3370306942U, // <2,4,4,6>: Cost 4 vmrghw <2,4,3,5>, <4,6,5,7> + 3397340396U, // <2,4,4,7>: Cost 4 vsldoi12 <7,0,1,2>, <4,4,7,5> + 3234680361U, // <2,4,4,u>: Cost 3 vsldoi8 <2,2,2,4>, RHS + 4174356582U, // <2,4,5,0>: Cost 3 vsldoi4 <2,2,4,5>, LHS + 4168385444U, // <2,4,5,1>: Cost 3 vsldoi4 <1,2,4,5>, <1,2,4,5> + 4174358141U, // <2,4,5,2>: Cost 3 vsldoi4 <2,2,4,5>, <2,2,4,5> + 4210190549U, // <2,4,5,3>: Cost 3 vsldoi4 , <3,0,u,2> + 4174359862U, // <2,4,5,4>: Cost 3 vsldoi4 <2,2,4,5>, RHS + 3370978614U, // <2,4,5,5>: Cost 3 vmrghw <2,5,3,6>, RHS + 3368881462U, // <2,4,5,6>: Cost 2 vsldoi12 <2,2,2,2>, RHS + 3397340472U, // <2,4,5,7>: Cost 4 vsldoi12 <7,0,1,2>, <4,5,7,0> + 3368881480U, // <2,4,5,u>: Cost 2 vsldoi12 <2,2,2,2>, RHS + 3371649938U, // <2,4,6,0>: Cost 3 vmrghw <2,6,3,7>, <4,0,5,1> + 3371649994U, // <2,4,6,1>: Cost 4 vmrghw <2,6,3,7>, <4,1,2,3> + 3371650105U, // <2,4,6,2>: Cost 3 vmrghw <2,6,3,7>, <4,2,5,6> + 3371650187U, // <2,4,6,3>: Cost 4 vmrghw <2,6,3,7>, <4,3,5,7> + 3371650256U, // <2,4,6,4>: Cost 3 vmrghw <2,6,3,7>, <4,4,4,4> + 2297908534U, // <2,4,6,5>: Cost 2 vmrghw <2,6,3,7>, RHS + 3371650430U, // <2,4,6,6>: Cost 4 vmrghw <2,6,3,7>, <4,6,5,7> + 3261887331U, // <2,4,6,7>: Cost 4 vsldoi8 <6,7,2,4>, <6,7,2,4> + 2297908777U, // <2,4,6,u>: Cost 2 vmrghw <2,6,3,7>, RHS + 3269850106U, // <2,4,7,0>: Cost 4 vsldoi8 , <7,0,1,2> + 3384069542U, // <2,4,7,1>: Cost 4 vsldoi12 <4,7,1,2>, <4,7,1,2> + 3264541863U, // <2,4,7,2>: Cost 4 vsldoi8 <7,2,2,4>, <7,2,2,4> + 3265205496U, // <2,4,7,3>: Cost 4 vsldoi8 <7,3,2,4>, <7,3,2,4> + 3535654096U, // <2,4,7,4>: Cost 4 vmrglw <7,6,2,7>, <4,4,4,4> + 3397340616U, // <2,4,7,5>: Cost 3 vsldoi12 <7,0,1,2>, <4,7,5,0> + 3267196395U, // <2,4,7,6>: Cost 4 vsldoi8 <7,6,2,4>, <7,6,2,4> + 3397340634U, // <2,4,7,7>: Cost 4 vsldoi12 <7,0,1,2>, <4,7,7,0> + 3397340643U, // <2,4,7,u>: Cost 3 vsldoi12 <7,0,1,2>, <4,7,u,0> + 4174381158U, // <2,4,u,0>: Cost 3 vsldoi4 <2,2,4,u>, LHS + 3490539696U, // <2,4,u,1>: Cost 3 vmrglw LHS, <3,0,4,1> + 4174382720U, // <2,4,u,2>: Cost 3 vsldoi4 <2,2,4,u>, <2,2,4,u> + 4180355417U, // <2,4,u,3>: Cost 3 vsldoi4 <3,2,4,u>, <3,2,4,u> + 2464574672U, // <2,4,u,4>: Cost 2 vmrglw LHS, <4,4,4,4> + 2416797390U, // <2,4,u,5>: Cost 2 vmrglw LHS, <2,3,4,5> + 3368881705U, // <2,4,u,6>: Cost 2 vsldoi12 <2,2,2,2>, RHS + 4204246205U, // <2,4,u,7>: Cost 3 vsldoi4 <7,2,4,u>, <7,2,4,u> + 2416797393U, // <2,4,u,u>: Cost 2 vmrglw LHS, <2,3,4,u> + 3230040064U, // <2,5,0,0>: Cost 4 vsldoi8 <1,4,2,5>, <0,0,0,0> + 3230040166U, // <2,5,0,1>: Cost 3 vsldoi8 <1,4,2,5>, LHS + 3224068269U, // <2,5,0,2>: Cost 4 vsldoi8 <0,4,2,5>, <0,2,1,2> + 3373452888U, // <2,5,0,3>: Cost 4 vsldoi12 <3,0,1,2>, <5,0,3,0> + 3224068443U, // <2,5,0,4>: Cost 4 vsldoi8 <0,4,2,5>, <0,4,2,5> + 3397340779U, // <2,5,0,5>: Cost 4 vsldoi12 <7,0,1,2>, <5,0,5,1> + 3397340788U, // <2,5,0,6>: Cost 4 vsldoi12 <7,0,1,2>, <5,0,6,1> + 3397340796U, // <2,5,0,7>: Cost 4 vsldoi12 <7,0,1,2>, <5,0,7,0> + 3230040733U, // <2,5,0,u>: Cost 3 vsldoi8 <1,4,2,5>, LHS + 3230040812U, // <2,5,1,0>: Cost 4 vsldoi8 <1,4,2,5>, <1,0,2,1> + 3230040884U, // <2,5,1,1>: Cost 4 vsldoi8 <1,4,2,5>, <1,1,1,1> + 3230040982U, // <2,5,1,2>: Cost 3 vsldoi8 <1,4,2,5>, <1,2,3,0> + 3519015990U, // <2,5,1,3>: Cost 4 vmrglw <4,u,2,1>, <4,2,5,3> + 3230041140U, // <2,5,1,4>: Cost 3 vsldoi8 <1,4,2,5>, <1,4,2,5> + 3368316932U, // <2,5,1,5>: Cost 4 vmrghw <2,1,3,5>, <5,5,5,5> + 3501097335U, // <2,5,1,6>: Cost 4 vmrglw <1,u,2,1>, <0,4,5,6> + 3397340877U, // <2,5,1,7>: Cost 4 vsldoi12 <7,0,1,2>, <5,1,7,0> + 3232695672U, // <2,5,1,u>: Cost 3 vsldoi8 <1,u,2,5>, <1,u,2,5> + 4186349670U, // <2,5,2,0>: Cost 3 vsldoi4 <4,2,5,2>, LHS + 3503098770U, // <2,5,2,1>: Cost 3 vmrglw <2,2,2,2>, <4,0,5,1> + 3236013672U, // <2,5,2,2>: Cost 3 vsldoi8 <2,4,2,5>, <2,2,2,2> + 3230041766U, // <2,5,2,3>: Cost 4 vsldoi8 <1,4,2,5>, <2,3,0,1> + 3236013837U, // <2,5,2,4>: Cost 3 vsldoi8 <2,4,2,5>, <2,4,2,5> + 3368882180U, // <2,5,2,5>: Cost 3 vmrghw <2,2,2,2>, <5,5,5,5> + 3503098370U, // <2,5,2,6>: Cost 3 vmrglw <2,2,2,2>, <3,4,5,6> + 3503097075U, // <2,5,2,7>: Cost 4 vmrglw <2,2,2,2>, <1,6,5,7> + 3503098372U, // <2,5,2,u>: Cost 3 vmrglw <2,2,2,2>, <3,4,5,u> + 3495144418U, // <2,5,3,0>: Cost 3 vmrglw LHS, <4,1,5,0> + 2464533394U, // <2,5,3,1>: Cost 2 vmrglw LHS, <4,0,5,1> + 4186359502U, // <2,5,3,2>: Cost 3 vsldoi4 <4,2,5,3>, <2,3,4,5> + 3495142315U, // <2,5,3,3>: Cost 3 vmrglw LHS, <1,2,5,3> + 3495144422U, // <2,5,3,4>: Cost 3 vmrglw LHS, <4,1,5,4> + 2464533722U, // <2,5,3,5>: Cost 2 vmrglw LHS, <4,4,5,5> + 2421402114U, // <2,5,3,6>: Cost 2 vmrglw LHS, <3,4,5,6> + 3495142643U, // <2,5,3,7>: Cost 3 vmrglw LHS, <1,6,5,7> + 2421402116U, // <2,5,3,u>: Cost 2 vmrglw LHS, <3,4,5,u> + 4186366054U, // <2,5,4,0>: Cost 4 vsldoi4 <4,2,5,4>, LHS + 4186366870U, // <2,5,4,1>: Cost 4 vsldoi4 <4,2,5,4>, <1,2,3,0> + 3230043187U, // <2,5,4,2>: Cost 4 vsldoi8 <1,4,2,5>, <4,2,5,0> + 3503113131U, // <2,5,4,3>: Cost 5 vmrglw <2,2,2,4>, <1,2,5,3> + 4186369079U, // <2,5,4,4>: Cost 4 vsldoi4 <4,2,5,4>, <4,2,5,4> + 3230043446U, // <2,5,4,5>: Cost 3 vsldoi8 <1,4,2,5>, RHS + 3497806338U, // <2,5,4,6>: Cost 4 vmrglw <1,3,2,4>, <3,4,5,6> + 3503113459U, // <2,5,4,7>: Cost 5 vmrglw <2,2,2,4>, <1,6,5,7> + 3230043689U, // <2,5,4,u>: Cost 3 vsldoi8 <1,4,2,5>, RHS + 4174430310U, // <2,5,5,0>: Cost 4 vsldoi4 <2,2,5,5>, LHS + 4174431126U, // <2,5,5,1>: Cost 4 vsldoi4 <2,2,5,5>, <1,2,3,0> + 4174431878U, // <2,5,5,2>: Cost 4 vsldoi4 <2,2,5,5>, <2,2,5,5> + 3498477188U, // <2,5,5,3>: Cost 4 vmrglw <1,4,2,5>, <2,2,5,3> + 4174433590U, // <2,5,5,4>: Cost 4 vsldoi4 <2,2,5,5>, RHS + 3397341188U, // <2,5,5,5>: Cost 3 vsldoi12 <7,0,1,2>, <5,5,5,5> + 3498475895U, // <2,5,5,6>: Cost 4 vmrglw <1,4,2,5>, <0,4,5,6> + 3397341201U, // <2,5,5,7>: Cost 4 vsldoi12 <7,0,1,2>, <5,5,7,0> + 3397341188U, // <2,5,5,u>: Cost 3 vsldoi12 <7,0,1,2>, <5,5,5,5> + 4186382438U, // <2,5,6,0>: Cost 3 vsldoi4 <4,2,5,6>, LHS + 3520384538U, // <2,5,6,1>: Cost 4 vmrglw <5,1,2,6>, <4,u,5,1> + 3259904506U, // <2,5,6,2>: Cost 3 vsldoi8 <6,4,2,5>, <6,2,7,3> + 3378761794U, // <2,5,6,3>: Cost 4 vsldoi12 <3,u,1,2>, <5,6,3,4> + 3259904625U, // <2,5,6,4>: Cost 3 vsldoi8 <6,4,2,5>, <6,4,2,5> + 3371651076U, // <2,5,6,5>: Cost 3 vmrghw <2,6,3,7>, <5,5,5,5> + 3371651170U, // <2,5,6,6>: Cost 3 vmrghw <2,6,3,7>, <5,6,7,0> + 3389821028U, // <2,5,6,7>: Cost 3 vsldoi12 <5,6,7,2>, <5,6,7,2> + 3389894765U, // <2,5,6,u>: Cost 3 vsldoi12 <5,6,u,2>, <5,6,u,2> + 3259905018U, // <2,5,7,0>: Cost 4 vsldoi8 <6,4,2,5>, <7,0,1,2> + 3263886423U, // <2,5,7,1>: Cost 4 vsldoi8 <7,1,2,5>, <7,1,2,5> + 3383701641U, // <2,5,7,2>: Cost 4 vsldoi12 <4,6,5,2>, <5,7,2,3> + 3259905306U, // <2,5,7,3>: Cost 4 vsldoi8 <6,4,2,5>, <7,3,6,2> + 3259905382U, // <2,5,7,4>: Cost 4 vsldoi8 <6,4,2,5>, <7,4,5,6> + 3266540955U, // <2,5,7,5>: Cost 4 vsldoi8 <7,5,2,5>, <7,5,2,5> + 3505792809U, // <2,5,7,6>: Cost 4 vmrglw <2,6,2,7>, <2,4,5,6> + 3259905604U, // <2,5,7,7>: Cost 4 vsldoi8 <6,4,2,5>, <7,7,3,3> + 3505792811U, // <2,5,7,u>: Cost 4 vmrglw <2,6,2,7>, <2,4,5,u> + 3495185378U, // <2,5,u,0>: Cost 3 vmrglw LHS, <4,1,5,0> + 2464574354U, // <2,5,u,1>: Cost 2 vmrglw LHS, <4,0,5,1> + 4186400462U, // <2,5,u,2>: Cost 3 vsldoi4 <4,2,5,u>, <2,3,4,5> + 3495183275U, // <2,5,u,3>: Cost 3 vmrglw LHS, <1,2,5,3> + 3495185382U, // <2,5,u,4>: Cost 3 vmrglw LHS, <4,1,5,4> + 2464574682U, // <2,5,u,5>: Cost 2 vmrglw LHS, <4,4,5,5> + 2416798210U, // <2,5,u,6>: Cost 2 vmrglw LHS, <3,4,5,6> + 3495183603U, // <2,5,u,7>: Cost 3 vmrglw LHS, <1,6,5,7> + 2416798212U, // <2,5,u,u>: Cost 2 vmrglw LHS, <3,4,5,u> + 3235356672U, // <2,6,0,0>: Cost 4 vsldoi8 <2,3,2,6>, <0,0,0,0> + 3235356774U, // <2,6,0,1>: Cost 3 vsldoi8 <2,3,2,6>, LHS + 3222749370U, // <2,6,0,2>: Cost 4 vsldoi8 <0,2,2,6>, <0,2,2,6> + 4180437347U, // <2,6,0,3>: Cost 4 vsldoi4 <3,2,6,0>, <3,2,6,0> + 3230712146U, // <2,6,0,4>: Cost 4 vsldoi8 <1,5,2,6>, <0,4,1,5> + 3512370993U, // <2,6,0,5>: Cost 5 vmrglw <3,7,2,0>, <2,4,6,5> + 3395424589U, // <2,6,0,6>: Cost 4 vsldoi12 <6,6,2,2>, <6,0,6,1> + 3538251062U, // <2,6,0,7>: Cost 3 vmrglw , RHS + 3235357341U, // <2,6,0,u>: Cost 3 vsldoi8 <2,3,2,6>, LHS + 4204331110U, // <2,6,1,0>: Cost 4 vsldoi4 <7,2,6,1>, LHS + 3228058434U, // <2,6,1,1>: Cost 4 vsldoi8 <1,1,2,6>, <1,1,2,6> + 3235357590U, // <2,6,1,2>: Cost 4 vsldoi8 <2,3,2,6>, <1,2,3,0> + 4204333206U, // <2,6,1,3>: Cost 4 vsldoi4 <7,2,6,1>, <3,0,1,2> + 4204334390U, // <2,6,1,4>: Cost 4 vsldoi4 <7,2,6,1>, RHS + 3230712966U, // <2,6,1,5>: Cost 4 vsldoi8 <1,5,2,6>, <1,5,2,6> + 3231376599U, // <2,6,1,6>: Cost 4 vsldoi8 <1,6,2,6>, <1,6,2,6> + 3501100342U, // <2,6,1,7>: Cost 3 vmrglw <1,u,2,1>, RHS + 3501100343U, // <2,6,1,u>: Cost 3 vmrglw <1,u,2,1>, RHS + 4174479462U, // <2,6,2,0>: Cost 4 vsldoi4 <2,2,6,2>, LHS + 3529642317U, // <2,6,2,1>: Cost 4 vmrglw <6,6,2,2>, <6,0,6,1> + 3368882681U, // <2,6,2,2>: Cost 3 vmrghw <2,2,2,2>, <6,2,7,2> + 3235358397U, // <2,6,2,3>: Cost 3 vsldoi8 <2,3,2,6>, <2,3,2,6> + 4174482742U, // <2,6,2,4>: Cost 4 vsldoi4 <2,2,6,2>, RHS + 3236685663U, // <2,6,2,5>: Cost 4 vsldoi8 <2,5,2,6>, <2,5,2,6> + 3235358650U, // <2,6,2,6>: Cost 3 vsldoi8 <2,3,2,6>, <2,6,3,7> + 2429357366U, // <2,6,2,7>: Cost 2 vmrglw <2,2,2,2>, RHS + 2429357367U, // <2,6,2,u>: Cost 2 vmrglw <2,2,2,2>, RHS + 4180459622U, // <2,6,3,0>: Cost 3 vsldoi4 <3,2,6,3>, LHS + 3538273769U, // <2,6,3,1>: Cost 3 vmrglw LHS, <2,0,6,1> + 4180461498U, // <2,6,3,2>: Cost 3 vsldoi4 <3,2,6,3>, <2,6,3,7> + 3495143782U, // <2,6,3,3>: Cost 3 vmrglw LHS, <3,2,6,3> + 4180462902U, // <2,6,3,4>: Cost 3 vsldoi4 <3,2,6,3>, RHS + 4192407320U, // <2,6,3,5>: Cost 3 vsldoi4 <5,2,6,3>, <5,2,6,3> + 2464535352U, // <2,6,3,6>: Cost 2 vmrglw LHS, <6,6,6,6> + 1343016246U, // <2,6,3,7>: Cost 1 vmrglw LHS, RHS + 1343016247U, // <2,6,3,u>: Cost 1 vmrglw LHS, RHS + 4180467814U, // <2,6,4,0>: Cost 4 vsldoi4 <3,2,6,4>, LHS + 4168524725U, // <2,6,4,1>: Cost 5 vsldoi4 <1,2,6,4>, <1,2,6,4> + 4180469437U, // <2,6,4,2>: Cost 4 vsldoi4 <3,2,6,4>, <2,3,2,6> + 4180470119U, // <2,6,4,3>: Cost 4 vsldoi4 <3,2,6,4>, <3,2,6,4> + 4180471094U, // <2,6,4,4>: Cost 4 vsldoi4 <3,2,6,4>, RHS + 3235360054U, // <2,6,4,5>: Cost 3 vsldoi8 <2,3,2,6>, RHS + 3259911545U, // <2,6,4,6>: Cost 4 vsldoi8 <6,4,2,6>, <4,6,5,2> + 3503115574U, // <2,6,4,7>: Cost 3 vmrglw <2,2,2,4>, RHS + 3503115575U, // <2,6,4,u>: Cost 3 vmrglw <2,2,2,4>, RHS + 3370979617U, // <2,6,5,0>: Cost 4 vmrghw <2,5,3,6>, <6,0,1,2> + 3251949222U, // <2,6,5,1>: Cost 4 vsldoi8 <5,1,2,6>, <5,1,2,6> + 3242659608U, // <2,6,5,2>: Cost 4 vsldoi8 <3,5,2,6>, <5,2,6,3> + 3370979890U, // <2,6,5,3>: Cost 4 vmrghw <2,5,3,6>, <6,3,4,5> + 3370979981U, // <2,6,5,4>: Cost 4 vmrghw <2,5,3,6>, <6,4,5,6> + 3254603754U, // <2,6,5,5>: Cost 4 vsldoi8 <5,5,2,6>, <5,5,2,6> + 3255267387U, // <2,6,5,6>: Cost 4 vsldoi8 <5,6,2,6>, <5,6,2,6> + 3498478902U, // <2,6,5,7>: Cost 3 vmrglw <1,4,2,5>, RHS + 3498478903U, // <2,6,5,u>: Cost 3 vmrglw <1,4,2,5>, RHS + 4174512230U, // <2,6,6,0>: Cost 3 vsldoi4 <2,2,6,6>, LHS + 3507111401U, // <2,6,6,1>: Cost 4 vmrglw <2,u,2,6>, <2,0,6,1> + 3395425040U, // <2,6,6,2>: Cost 3 vsldoi12 <6,6,2,2>, <6,6,2,2> + 3371651656U, // <2,6,6,3>: Cost 3 vmrghw <2,6,3,7>, <6,3,7,0> + 4174515510U, // <2,6,6,4>: Cost 3 vsldoi4 <2,2,6,6>, RHS + 3507111729U, // <2,6,6,5>: Cost 4 vmrglw <2,u,2,6>, <2,4,6,5> + 3397342008U, // <2,6,6,6>: Cost 3 vsldoi12 <7,0,1,2>, <6,6,6,6> + 3503795510U, // <2,6,6,7>: Cost 3 vmrglw <2,3,2,6>, RHS + 3503795511U, // <2,6,6,u>: Cost 3 vmrglw <2,3,2,6>, RHS + 3397342030U, // <2,6,7,0>: Cost 3 vsldoi12 <7,0,1,2>, <6,7,0,1> + 3396014936U, // <2,6,7,1>: Cost 3 vsldoi12 <6,7,1,2>, <6,7,1,2> + 3396088673U, // <2,6,7,2>: Cost 3 vsldoi12 <6,7,2,2>, <6,7,2,2> + 3373454184U, // <2,6,7,3>: Cost 3 vsldoi12 <3,0,1,2>, <6,7,3,0> + 3397342070U, // <2,6,7,4>: Cost 3 vsldoi12 <7,0,1,2>, <6,7,4,5> + 3505792817U, // <2,6,7,5>: Cost 4 vmrglw <2,6,2,7>, <2,4,6,5> + 3396383621U, // <2,6,7,6>: Cost 3 vsldoi12 <6,7,6,2>, <6,7,6,2> + 3505794358U, // <2,6,7,7>: Cost 3 vmrglw <2,6,2,7>, RHS + 3505794359U, // <2,6,7,u>: Cost 3 vmrglw <2,6,2,7>, RHS + 4180500582U, // <2,6,u,0>: Cost 3 vsldoi4 <3,2,6,u>, LHS + 3235362606U, // <2,6,u,1>: Cost 3 vsldoi8 <2,3,2,6>, LHS + 4180502503U, // <2,6,u,2>: Cost 3 vsldoi4 <3,2,6,u>, <2,6,u,7> + 3490539878U, // <2,6,u,3>: Cost 3 vmrglw LHS, <3,2,6,3> + 4180503862U, // <2,6,u,4>: Cost 3 vsldoi4 <3,2,6,u>, RHS + 3235362970U, // <2,6,u,5>: Cost 3 vsldoi8 <2,3,2,6>, RHS + 2464576312U, // <2,6,u,6>: Cost 2 vmrglw LHS, <6,6,6,6> + 1343057206U, // <2,6,u,7>: Cost 1 vmrglw LHS, RHS + 1343057207U, // <2,6,u,u>: Cost 1 vmrglw LHS, RHS + 4210368614U, // <2,7,0,0>: Cost 3 vsldoi4 , LHS + 3397342202U, // <2,7,0,1>: Cost 2 vsldoi12 <7,0,1,2>, <7,0,1,2> + 3231383725U, // <2,7,0,2>: Cost 4 vsldoi8 <1,6,2,7>, <0,2,1,2> + 3527635450U, // <2,7,0,3>: Cost 4 vmrglw <6,3,2,0>, <6,2,7,3> + 4210371894U, // <2,7,0,4>: Cost 3 vsldoi4 , RHS + 3397342242U, // <2,7,0,5>: Cost 4 vsldoi12 <7,0,1,2>, <7,0,5,6> + 4198429175U, // <2,7,0,6>: Cost 4 vsldoi4 <6,2,7,0>, <6,2,7,0> + 4210373689U, // <2,7,0,7>: Cost 3 vsldoi4 , <7,0,u,2> + 3397858361U, // <2,7,0,u>: Cost 2 vsldoi12 <7,0,u,2>, <7,0,u,2> + 4198432870U, // <2,7,1,0>: Cost 4 vsldoi4 <6,2,7,1>, LHS + 3237356340U, // <2,7,1,1>: Cost 4 vsldoi8 <2,6,2,7>, <1,1,1,1> + 3237356438U, // <2,7,1,2>: Cost 4 vsldoi8 <2,6,2,7>, <1,2,3,0> + 3530961402U, // <2,7,1,3>: Cost 3 vmrglw <6,u,2,1>, <6,2,7,3> + 4198436150U, // <2,7,1,4>: Cost 4 vsldoi4 <6,2,7,1>, RHS + 3237356655U, // <2,7,1,5>: Cost 5 vsldoi8 <2,6,2,7>, <1,5,0,1> + 3231384792U, // <2,7,1,6>: Cost 3 vsldoi8 <1,6,2,7>, <1,6,2,7> + 3530961730U, // <2,7,1,7>: Cost 4 vmrglw <6,u,2,1>, <6,6,7,7> + 3530961402U, // <2,7,1,u>: Cost 3 vmrglw <6,u,2,1>, <6,2,7,3> + 4198441062U, // <2,7,2,0>: Cost 3 vsldoi4 <6,2,7,2>, LHS + 4198441780U, // <2,7,2,1>: Cost 4 vsldoi4 <6,2,7,2>, <1,1,1,1> + 3237357160U, // <2,7,2,2>: Cost 3 vsldoi8 <2,6,2,7>, <2,2,2,2> + 3529642490U, // <2,7,2,3>: Cost 3 vmrglw <6,6,2,2>, <6,2,7,3> + 4198444342U, // <2,7,2,4>: Cost 3 vsldoi4 <6,2,7,2>, RHS + 3389822148U, // <2,7,2,5>: Cost 4 vsldoi12 <5,6,7,2>, <7,2,5,6> + 3237357489U, // <2,7,2,6>: Cost 3 vsldoi8 <2,6,2,7>, <2,6,2,7> + 3368883820U, // <2,7,2,7>: Cost 3 vmrghw <2,2,2,2>, <7,7,7,7> + 3238684755U, // <2,7,2,u>: Cost 3 vsldoi8 <2,u,2,7>, <2,u,2,7> + 3124707430U, // <2,7,3,0>: Cost 2 vsldoi4 <6,2,7,3>, LHS + 4198449972U, // <2,7,3,1>: Cost 3 vsldoi4 <6,2,7,3>, <1,1,1,1> + 4180535226U, // <2,7,3,2>: Cost 3 vsldoi4 <3,2,7,3>, <2,6,3,7> + 2464535034U, // <2,7,3,3>: Cost 2 vmrglw LHS, <6,2,7,3> + 3124710710U, // <2,7,3,4>: Cost 2 vsldoi4 <6,2,7,3>, RHS + 4198453252U, // <2,7,3,5>: Cost 3 vsldoi4 <6,2,7,3>, <5,5,5,5> + 3124711930U, // <2,7,3,6>: Cost 2 vsldoi4 <6,2,7,3>, <6,2,7,3> + 2464535362U, // <2,7,3,7>: Cost 2 vmrglw LHS, <6,6,7,7> + 3124713262U, // <2,7,3,u>: Cost 2 vsldoi4 <6,2,7,3>, LHS + 4198457446U, // <2,7,4,0>: Cost 4 vsldoi4 <6,2,7,4>, LHS + 3399996734U, // <2,7,4,1>: Cost 4 vsldoi12 <7,4,1,2>, <7,4,1,2> + 4198458984U, // <2,7,4,2>: Cost 4 vsldoi4 <6,2,7,4>, <2,2,2,2> + 3527668218U, // <2,7,4,3>: Cost 4 vmrglw <6,3,2,4>, <6,2,7,3> + 4198460726U, // <2,7,4,4>: Cost 4 vsldoi4 <6,2,7,4>, RHS + 3237358902U, // <2,7,4,5>: Cost 3 vsldoi8 <2,6,2,7>, RHS + 4198461947U, // <2,7,4,6>: Cost 4 vsldoi4 <6,2,7,4>, <6,2,7,4> + 3397342578U, // <2,7,4,7>: Cost 4 vsldoi12 <7,0,1,2>, <7,4,7,0> + 3237359145U, // <2,7,4,u>: Cost 3 vsldoi8 <2,6,2,7>, RHS + 3385398661U, // <2,7,5,0>: Cost 4 vsldoi12 <5,0,1,2>, <7,5,0,1> + 4198466454U, // <2,7,5,1>: Cost 4 vsldoi4 <6,2,7,5>, <1,2,3,0> + 3504451684U, // <2,7,5,2>: Cost 4 vmrglw <2,4,2,5>, <5,6,7,2> + 3528339962U, // <2,7,5,3>: Cost 3 vmrglw <6,4,2,5>, <6,2,7,3> + 4198468918U, // <2,7,5,4>: Cost 4 vsldoi4 <6,2,7,5>, RHS + 3397342646U, // <2,7,5,5>: Cost 4 vsldoi12 <7,0,1,2>, <7,5,5,5> + 3255275580U, // <2,7,5,6>: Cost 4 vsldoi8 <5,6,2,7>, <5,6,2,7> + 3528340290U, // <2,7,5,7>: Cost 4 vmrglw <6,4,2,5>, <6,6,7,7> + 3528339962U, // <2,7,5,u>: Cost 3 vmrglw <6,4,2,5>, <6,2,7,3> + 3371652090U, // <2,7,6,0>: Cost 3 vmrghw <2,6,3,7>, <7,0,1,2> + 3231388072U, // <2,7,6,1>: Cost 4 vsldoi8 <1,6,2,7>, <6,1,7,2> + 3267219962U, // <2,7,6,2>: Cost 3 vsldoi8 <7,6,2,7>, <6,2,7,3> + 3507112303U, // <2,7,6,3>: Cost 4 vmrglw <2,u,2,6>, <3,2,7,3> + 3371652454U, // <2,7,6,4>: Cost 3 vmrghw <2,6,3,7>, <7,4,5,6> + 3371652534U, // <2,7,6,5>: Cost 4 vmrghw <2,6,3,7>, <7,5,5,5> + 4198478333U, // <2,7,6,6>: Cost 4 vsldoi4 <6,2,7,6>, <6,2,7,6> + 3371652716U, // <2,7,6,7>: Cost 3 vmrghw <2,6,3,7>, <7,7,7,7> + 3267219962U, // <2,7,6,u>: Cost 3 vsldoi8 <7,6,2,7>, <6,2,7,3> + 3397342759U, // <2,7,7,0>: Cost 3 vsldoi12 <7,0,1,2>, <7,7,0,1> + 4198483160U, // <2,7,7,1>: Cost 4 vsldoi4 <6,2,7,7>, <1,6,2,7> + 3505792661U, // <2,7,7,2>: Cost 4 vmrglw <2,6,2,7>, <2,2,7,2> + 3535655418U, // <2,7,7,3>: Cost 3 vmrglw <7,6,2,7>, <6,2,7,3> + 4198485302U, // <2,7,7,4>: Cost 4 vsldoi4 <6,2,7,7>, RHS + 3505792583U, // <2,7,7,5>: Cost 5 vmrglw <2,6,2,7>, <2,1,7,5> + 3267220974U, // <2,7,7,6>: Cost 3 vsldoi8 <7,6,2,7>, <7,6,2,7> + 3397342828U, // <2,7,7,7>: Cost 3 vsldoi12 <7,0,1,2>, <7,7,7,7> + 3402651247U, // <2,7,7,u>: Cost 3 vsldoi12 <7,u,1,2>, <7,7,u,1> + 3124748390U, // <2,7,u,0>: Cost 2 vsldoi4 <6,2,7,u>, LHS + 3402651266U, // <2,7,u,1>: Cost 2 vsldoi12 <7,u,1,2>, <7,u,1,2> + 4180576186U, // <2,7,u,2>: Cost 3 vsldoi4 <3,2,7,u>, <2,6,3,7> + 2464575994U, // <2,7,u,3>: Cost 2 vmrglw LHS, <6,2,7,3> + 3124751670U, // <2,7,u,4>: Cost 2 vsldoi4 <6,2,7,u>, RHS + 3237361818U, // <2,7,u,5>: Cost 3 vsldoi8 <2,6,2,7>, RHS + 3124752895U, // <2,7,u,6>: Cost 2 vsldoi4 <6,2,7,u>, <6,2,7,u> + 2464576322U, // <2,7,u,7>: Cost 2 vmrglw LHS, <6,6,7,7> + 3124754222U, // <2,7,u,u>: Cost 2 vsldoi4 <6,2,7,u>, LHS + 3222102016U, // <2,u,0,0>: Cost 2 vsldoi8 LHS, <0,0,0,0> + 1074618475U, // <2,u,0,1>: Cost 1 vsldoi8 LHS, LHS + 3222102189U, // <2,u,0,2>: Cost 3 vsldoi8 LHS, <0,2,1,2> + 3222102268U, // <2,u,0,3>: Cost 3 vsldoi8 LHS, <0,3,1,0> + 3222102354U, // <2,u,0,4>: Cost 2 vsldoi8 LHS, <0,4,1,5> + 3367614618U, // <2,u,0,5>: Cost 3 vmrghw <2,0,3,0>, RHS + 3269878262U, // <2,u,0,6>: Cost 3 vsldoi8 LHS, <0,6,1,7> + 4204475609U, // <2,u,0,7>: Cost 3 vsldoi4 <7,2,u,0>, <7,2,u,0> + 1074619037U, // <2,u,0,u>: Cost 1 vsldoi8 LHS, LHS + 3226747620U, // <2,u,1,0>: Cost 3 vsldoi8 LHS, <1,0,1,2> + 3222102836U, // <2,u,1,1>: Cost 2 vsldoi8 LHS, <1,1,1,1> + 3222102934U, // <2,u,1,2>: Cost 2 vsldoi8 LHS, <1,2,3,0> + 3501097116U, // <2,u,1,3>: Cost 3 vmrglw <1,u,2,1>, LHS + 3226747984U, // <2,u,1,4>: Cost 3 vsldoi8 LHS, <1,4,5,6> + 3226748015U, // <2,u,1,5>: Cost 3 vsldoi8 LHS, <1,5,0,1> + 3226748111U, // <2,u,1,6>: Cost 3 vsldoi8 LHS, <1,6,1,7> + 3501100360U, // <2,u,1,7>: Cost 3 vmrglw <1,u,2,1>, RHS + 3226748284U, // <2,u,1,u>: Cost 2 vsldoi8 LHS, <1,u,3,0> + 3100442726U, // <2,u,2,0>: Cost 2 vsldoi4 <2,2,2,2>, LHS + 2295142190U, // <2,u,2,1>: Cost 2 vmrghw <2,2,2,2>, LHS + 1745666150U, // <2,u,2,2>: Cost 1 vspltisw2 LHS + 3222103718U, // <2,u,2,3>: Cost 2 vsldoi8 LHS, <2,3,0,1> + 3100446006U, // <2,u,2,4>: Cost 2 vsldoi4 <2,2,2,2>, RHS + 2295142554U, // <2,u,2,5>: Cost 2 vmrghw <2,2,2,2>, RHS + 3222103994U, // <2,u,2,6>: Cost 2 vsldoi8 LHS, <2,6,3,7> + 2429357384U, // <2,u,2,7>: Cost 2 vmrglw <2,2,2,2>, RHS + 1745666150U, // <2,u,2,u>: Cost 1 vspltisw2 LHS + 3222104214U, // <2,u,3,0>: Cost 2 vsldoi8 LHS, <3,0,1,2> + 2421399625U, // <2,u,3,1>: Cost 2 vmrglw LHS, <0,0,u,1> + 2421401813U, // <2,u,3,2>: Cost 2 vmrglw LHS, <3,0,u,2> + 1343013020U, // <2,u,3,3>: Cost 1 vmrglw LHS, LHS + 3222104578U, // <2,u,3,4>: Cost 2 vsldoi8 LHS, <3,4,5,6> + 2421399953U, // <2,u,3,5>: Cost 2 vmrglw LHS, <0,4,u,5> + 2421402141U, // <2,u,3,6>: Cost 2 vmrglw LHS, <3,4,u,6> + 1343016264U, // <2,u,3,7>: Cost 1 vmrglw LHS, RHS + 1343013025U, // <2,u,3,u>: Cost 1 vmrglw LHS, LHS + 3094929510U, // <2,u,4,0>: Cost 2 vsldoi4 <1,2,u,4>, LHS + 3094930375U, // <2,u,4,1>: Cost 2 vsldoi4 <1,2,u,4>, <1,2,u,4> + 4168672872U, // <2,u,4,2>: Cost 3 vsldoi4 <1,2,u,4>, <2,2,2,2> + 4168673430U, // <2,u,4,3>: Cost 3 vsldoi4 <1,2,u,4>, <3,0,1,2> + 3094932790U, // <2,u,4,4>: Cost 2 vsldoi4 <1,2,u,4>, RHS + 1074621750U, // <2,u,4,5>: Cost 1 vsldoi8 LHS, RHS + 3269881209U, // <2,u,4,6>: Cost 3 vsldoi8 LHS, <4,6,5,2> + 3503115592U, // <2,u,4,7>: Cost 3 vmrglw <2,2,2,4>, RHS + 1074621993U, // <2,u,4,u>: Cost 1 vsldoi8 LHS, RHS + 3226750536U, // <2,u,5,0>: Cost 3 vsldoi8 LHS, <5,0,1,2> + 3370981166U, // <2,u,5,1>: Cost 3 vmrghw <2,5,3,6>, LHS + 4174653089U, // <2,u,5,2>: Cost 3 vsldoi4 <2,2,u,5>, <2,2,u,5> + 3498475676U, // <2,u,5,3>: Cost 3 vmrglw <1,4,2,5>, LHS + 3226750900U, // <2,u,5,4>: Cost 3 vsldoi8 LHS, <5,4,5,6> + 3269881860U, // <2,u,5,5>: Cost 2 vsldoi8 LHS, <5,5,5,5> + 3368884378U, // <2,u,5,6>: Cost 2 vsldoi12 <2,2,2,2>, RHS + 3498478920U, // <2,u,5,7>: Cost 3 vmrglw <1,4,2,5>, RHS + 3368884396U, // <2,u,5,u>: Cost 2 vsldoi12 <2,2,2,2>, RHS + 3371652819U, // <2,u,6,0>: Cost 3 vmrghw <2,6,3,7>, + 2297911086U, // <2,u,6,1>: Cost 2 vmrghw <2,6,3,7>, LHS + 3269882362U, // <2,u,6,2>: Cost 2 vsldoi8 LHS, <6,2,7,3> + 3368884432U, // <2,u,6,3>: Cost 3 vsldoi12 <2,2,2,2>, + 3371653183U, // <2,u,6,4>: Cost 3 vmrghw <2,6,3,7>, + 2297911450U, // <2,u,6,5>: Cost 2 vmrghw <2,6,3,7>, RHS + 3269882680U, // <2,u,6,6>: Cost 2 vsldoi8 LHS, <6,6,6,6> + 3269882702U, // <2,u,6,7>: Cost 2 vsldoi8 LHS, <6,7,0,1> + 2297911653U, // <2,u,6,u>: Cost 2 vmrghw <2,6,3,7>, LHS + 3269882874U, // <2,u,7,0>: Cost 2 vsldoi8 LHS, <7,0,1,2> + 3263911002U, // <2,u,7,1>: Cost 3 vsldoi8 <7,1,2,u>, <7,1,2,u> + 3264574635U, // <2,u,7,2>: Cost 3 vsldoi8 <7,2,2,u>, <7,2,2,u> + 3505791132U, // <2,u,7,3>: Cost 3 vmrglw <2,6,2,7>, LHS + 3269883238U, // <2,u,7,4>: Cost 2 vsldoi8 LHS, <7,4,5,6> + 3269883318U, // <2,u,7,5>: Cost 3 vsldoi8 LHS, <7,5,5,5> + 3267229167U, // <2,u,7,6>: Cost 3 vsldoi8 <7,6,2,u>, <7,6,2,u> + 3269883500U, // <2,u,7,7>: Cost 2 vsldoi8 LHS, <7,7,7,7> + 3269883522U, // <2,u,7,u>: Cost 2 vsldoi8 LHS, <7,u,1,2> + 2421441475U, // <2,u,u,0>: Cost 2 vmrglw LHS, <1,2,u,0> + 1074624302U, // <2,u,u,1>: Cost 1 vsldoi8 LHS, LHS + 1745666150U, // <2,u,u,2>: Cost 1 vspltisw2 LHS + 1343053980U, // <2,u,u,3>: Cost 1 vmrglw LHS, LHS + 2421441479U, // <2,u,u,4>: Cost 2 vmrglw LHS, <1,2,u,4> + 1074624666U, // <2,u,u,5>: Cost 1 vsldoi8 LHS, RHS + 2416798237U, // <2,u,u,6>: Cost 2 vmrglw LHS, <3,4,u,6> + 1343057224U, // <2,u,u,7>: Cost 1 vmrglw LHS, RHS + 1343053985U, // <2,u,u,u>: Cost 1 vmrglw LHS, LHS + 3356278784U, // <3,0,0,0>: Cost 2 vsldoi12 LHS, <0,0,0,0> + 3356278794U, // <3,0,0,1>: Cost 2 vsldoi12 LHS, <0,0,1,1> + 4174685861U, // <3,0,0,2>: Cost 3 vsldoi4 <2,3,0,0>, <2,3,0,0> + 3497183536U, // <3,0,0,3>: Cost 3 vmrglw <1,2,3,0>, <3,2,0,3> + 3360923685U, // <3,0,0,4>: Cost 3 vsldoi12 LHS, <0,0,4,1> + 3497183457U, // <3,0,0,5>: Cost 4 vmrglw <1,2,3,0>, <3,1,0,5> + 3497183782U, // <3,0,0,6>: Cost 4 vmrglw <1,2,3,0>, <3,5,0,6> + 3497183864U, // <3,0,0,7>: Cost 3 vmrglw <1,2,3,0>, <3,6,0,7> + 3360923721U, // <3,0,0,u>: Cost 2 vsldoi12 LHS, <0,0,u,1> + 3100950630U, // <3,0,1,0>: Cost 2 vsldoi4 <2,3,0,1>, LHS + 3356721243U, // <3,0,1,1>: Cost 3 vsldoi12 LHS, <0,1,1,1> + 1208795238U, // <3,0,1,2>: Cost 1 vsldoi12 LHS, LHS + 4174694548U, // <3,0,1,3>: Cost 3 vsldoi4 <2,3,0,1>, <3,0,1,0> + 3100953910U, // <3,0,1,4>: Cost 2 vsldoi4 <2,3,0,1>, RHS + 4210528260U, // <3,0,1,5>: Cost 3 vsldoi4 , <5,5,5,5> + 3404054670U, // <3,0,1,6>: Cost 3 vsldoi12 LHS, <0,1,6,7> + 4204557539U, // <3,0,1,7>: Cost 3 vsldoi4 <7,3,0,1>, <7,3,0,1> + 1208795292U, // <3,0,1,u>: Cost 1 vsldoi12 LHS, LHS + 3233392077U, // <3,0,2,0>: Cost 3 vsldoi8 <2,0,3,0>, <2,0,3,0> + 3356721325U, // <3,0,2,1>: Cost 3 vsldoi12 LHS, <0,2,1,2> + 3228747368U, // <3,0,2,2>: Cost 3 vsldoi8 <1,2,3,0>, <2,2,2,2> + 3228747430U, // <3,0,2,3>: Cost 3 vsldoi8 <1,2,3,0>, <2,3,0,1> + 3360923847U, // <3,0,2,4>: Cost 4 vsldoi12 LHS, <0,2,4,1> + 3228747624U, // <3,0,2,5>: Cost 4 vsldoi8 <1,2,3,0>, <2,5,3,6> + 3228747706U, // <3,0,2,6>: Cost 3 vsldoi8 <1,2,3,0>, <2,6,3,7> + 3238037508U, // <3,0,2,7>: Cost 3 vsldoi8 <2,7,3,0>, <2,7,3,0> + 3360923884U, // <3,0,2,u>: Cost 3 vsldoi12 LHS, <0,2,u,2> + 3228747926U, // <3,0,3,0>: Cost 3 vsldoi8 <1,2,3,0>, <3,0,1,2> + 2301853798U, // <3,0,3,1>: Cost 2 vmrghw <3,3,3,3>, LHS + 3228748080U, // <3,0,3,2>: Cost 3 vsldoi8 <1,2,3,0>, <3,2,0,3> + 3228748158U, // <3,0,3,3>: Cost 3 vsldoi8 <1,2,3,0>, <3,3,0,0> + 3228748290U, // <3,0,3,4>: Cost 3 vsldoi8 <1,2,3,0>, <3,4,5,6> + 3228748326U, // <3,0,3,5>: Cost 4 vsldoi8 <1,2,3,0>, <3,5,0,6> + 3228748408U, // <3,0,3,6>: Cost 3 vsldoi8 <1,2,3,0>, <3,6,0,7> + 3503180408U, // <3,0,3,7>: Cost 4 vmrglw <2,2,3,3>, <3,6,0,7> + 2301854365U, // <3,0,3,u>: Cost 2 vmrghw <3,3,3,3>, LHS + 3497213952U, // <3,0,4,0>: Cost 3 vmrglw <1,2,3,4>, <0,0,0,0> + 3356279122U, // <3,0,4,1>: Cost 2 vsldoi12 LHS, <0,4,1,5> + 4174718633U, // <3,0,4,2>: Cost 3 vsldoi4 <2,3,0,4>, <2,3,0,4> + 3376431360U, // <3,0,4,3>: Cost 3 vmrghw <3,4,5,6>, <0,3,1,4> + 3360924013U, // <3,0,4,4>: Cost 3 vsldoi12 LHS, <0,4,4,5> + 3228749110U, // <3,0,4,5>: Cost 2 vsldoi8 <1,2,3,0>, RHS + 3376431606U, // <3,0,4,6>: Cost 4 vmrghw <3,4,5,6>, <0,6,1,7> + 3497216632U, // <3,0,4,7>: Cost 4 vmrglw <1,2,3,4>, <3,6,0,7> + 3360924049U, // <3,0,4,u>: Cost 2 vsldoi12 LHS, <0,4,u,5> + 3228749384U, // <3,0,5,0>: Cost 4 vsldoi8 <1,2,3,0>, <5,0,1,2> + 3356279203U, // <3,0,5,1>: Cost 3 vsldoi12 LHS, <0,5,1,5> + 3252637434U, // <3,0,5,2>: Cost 4 vsldoi8 <5,2,3,0>, <5,2,3,0> + 3537704570U, // <3,0,5,3>: Cost 4 vmrglw , <7,u,0,3> + 3228749748U, // <3,0,5,4>: Cost 4 vsldoi8 <1,2,3,0>, <5,4,5,6> + 3270553604U, // <3,0,5,5>: Cost 3 vsldoi8 , <5,5,5,5> + 3404054994U, // <3,0,5,6>: Cost 3 vsldoi12 LHS, <0,5,6,7> + 3404054996U, // <3,0,5,7>: Cost 4 vsldoi12 LHS, <0,5,7,0> + 3404055010U, // <3,0,5,u>: Cost 3 vsldoi12 LHS, <0,5,u,5> + 3356279277U, // <3,0,6,0>: Cost 3 vsldoi12 LHS, <0,6,0,7> + 3377397862U, // <3,0,6,1>: Cost 3 vmrghw <3,6,0,7>, LHS + 3270554106U, // <3,0,6,2>: Cost 3 vsldoi8 , <6,2,7,3> + 3374711304U, // <3,0,6,3>: Cost 4 vsldoi12 <3,2,0,3>, <0,6,3,7> + 3377398098U, // <3,0,6,4>: Cost 4 vmrghw <3,6,0,7>, <0,4,1,5> + 3404055066U, // <3,0,6,5>: Cost 4 vsldoi12 LHS, <0,6,5,7> + 3270554424U, // <3,0,6,6>: Cost 3 vsldoi8 , <6,6,6,6> + 3261928296U, // <3,0,6,7>: Cost 3 vsldoi8 <6,7,3,0>, <6,7,3,0> + 3377398429U, // <3,0,6,u>: Cost 3 vmrghw <3,6,0,7>, LHS + 3505864704U, // <3,0,7,0>: Cost 3 vmrglw <2,6,3,7>, <0,0,0,0> + 3505866406U, // <3,0,7,1>: Cost 3 vmrglw <2,6,3,7>, <2,3,0,1> + 3264582828U, // <3,0,7,2>: Cost 3 vsldoi8 <7,2,3,0>, <7,2,3,0> + 3505867056U, // <3,0,7,3>: Cost 4 vmrglw <2,6,3,7>, <3,2,0,3> + 3270554982U, // <3,0,7,4>: Cost 3 vsldoi8 , <7,4,5,6> + 4204605538U, // <3,0,7,5>: Cost 4 vsldoi4 <7,3,0,7>, <5,6,7,0> + 3261928983U, // <3,0,7,6>: Cost 4 vsldoi8 <6,7,3,0>, <7,6,7,3> + 3270555244U, // <3,0,7,7>: Cost 3 vsldoi8 , <7,7,7,7> + 3505866413U, // <3,0,7,u>: Cost 3 vmrglw <2,6,3,7>, <2,3,0,u> + 3101007974U, // <3,0,u,0>: Cost 2 vsldoi4 <2,3,0,u>, LHS + 3356279442U, // <3,0,u,1>: Cost 2 vsldoi12 LHS, <0,u,1,1> + 1208795805U, // <3,0,u,2>: Cost 1 vsldoi12 LHS, LHS + 3228751804U, // <3,0,u,3>: Cost 3 vsldoi8 <1,2,3,0>, + 3101011254U, // <3,0,u,4>: Cost 2 vsldoi4 <2,3,0,u>, RHS + 3228752026U, // <3,0,u,5>: Cost 2 vsldoi8 <1,2,3,0>, RHS + 3228752080U, // <3,0,u,6>: Cost 3 vsldoi8 <1,2,3,0>, + 4204614890U, // <3,0,u,7>: Cost 3 vsldoi4 <7,3,0,u>, <7,3,0,u> + 1208795859U, // <3,0,u,u>: Cost 1 vsldoi12 LHS, LHS + 4162814204U, // <3,1,0,0>: Cost 3 vsldoi4 <0,3,1,0>, <0,3,1,0> + 3360924388U, // <3,1,0,1>: Cost 3 vsldoi12 LHS, <1,0,1,2> + 3497181276U, // <3,1,0,2>: Cost 3 vmrglw <1,2,3,0>, <0,1,1,2> + 4162816150U, // <3,1,0,3>: Cost 3 vsldoi4 <0,3,1,0>, <3,0,1,2> + 4162817334U, // <3,1,0,4>: Cost 3 vsldoi4 <0,3,1,0>, RHS + 3497181522U, // <3,1,0,5>: Cost 3 vmrglw <1,2,3,0>, <0,4,1,5> + 3373450456U, // <3,1,0,6>: Cost 3 vmrghw <3,0,1,2>, <1,6,2,7> + 3497182415U, // <3,1,0,7>: Cost 4 vmrglw <1,2,3,0>, <1,6,1,7> + 4162819886U, // <3,1,0,u>: Cost 3 vsldoi4 <0,3,1,0>, LHS + 3360924459U, // <3,1,1,0>: Cost 3 vsldoi12 LHS, <1,1,0,1> + 3356279604U, // <3,1,1,1>: Cost 2 vsldoi12 LHS, <1,1,1,1> + 3228754839U, // <3,1,1,2>: Cost 3 vsldoi8 <1,2,3,1>, <1,2,3,1> + 3356869448U, // <3,1,1,3>: Cost 4 vsldoi12 <0,2,1,3>, <1,1,3,3> + 3360924499U, // <3,1,1,4>: Cost 3 vsldoi12 LHS, <1,1,4,5> + 3360924508U, // <3,1,1,5>: Cost 3 vsldoi12 LHS, <1,1,5,5> + 3360924513U, // <3,1,1,6>: Cost 4 vsldoi12 LHS, <1,1,6,1> + 4204631276U, // <3,1,1,7>: Cost 4 vsldoi4 <7,3,1,1>, <7,3,1,1> + 3356279604U, // <3,1,1,u>: Cost 2 vsldoi12 LHS, <1,1,1,1> + 3233400270U, // <3,1,2,0>: Cost 3 vsldoi8 <2,0,3,1>, <2,0,3,1> + 3360924551U, // <3,1,2,1>: Cost 3 vsldoi12 LHS, <1,2,1,3> + 3502508182U, // <3,1,2,2>: Cost 3 vmrglw <2,1,3,2>, <3,0,1,2> + 3356279702U, // <3,1,2,3>: Cost 2 vsldoi12 LHS, <1,2,3,0> + 4174777654U, // <3,1,2,4>: Cost 3 vsldoi4 <2,3,1,2>, RHS + 3360924587U, // <3,1,2,5>: Cost 3 vsldoi12 LHS, <1,2,5,3> + 3360924596U, // <3,1,2,6>: Cost 4 vsldoi12 LHS, <1,2,6,3> + 3404055482U, // <3,1,2,7>: Cost 3 vsldoi12 LHS, <1,2,7,0> + 3356722115U, // <3,1,2,u>: Cost 2 vsldoi12 LHS, <1,2,u,0> + 4162838783U, // <3,1,3,0>: Cost 3 vsldoi4 <0,3,1,3>, <0,3,1,3> + 3503177738U, // <3,1,3,1>: Cost 3 vmrglw <2,2,3,3>, <0,0,1,1> + 3501189270U, // <3,1,3,2>: Cost 3 vmrglw <1,u,3,3>, <3,0,1,2> + 4162840988U, // <3,1,3,3>: Cost 3 vsldoi4 <0,3,1,3>, <3,3,3,3> + 4162841910U, // <3,1,3,4>: Cost 3 vsldoi4 <0,3,1,3>, RHS + 3503178066U, // <3,1,3,5>: Cost 3 vmrglw <2,2,3,3>, <0,4,1,5> + 3360924681U, // <3,1,3,6>: Cost 4 vsldoi12 LHS, <1,3,6,7> + 3503178959U, // <3,1,3,7>: Cost 4 vmrglw <2,2,3,3>, <1,6,1,7> + 4162844462U, // <3,1,3,u>: Cost 3 vsldoi4 <0,3,1,3>, LHS + 4162846976U, // <3,1,4,0>: Cost 3 vsldoi4 <0,3,1,4>, <0,3,1,4> + 3497213962U, // <3,1,4,1>: Cost 3 vmrglw <1,2,3,4>, <0,0,1,1> + 3497216150U, // <3,1,4,2>: Cost 3 vmrglw <1,2,3,4>, <3,0,1,2> + 4162849282U, // <3,1,4,3>: Cost 3 vsldoi4 <0,3,1,4>, <3,4,5,6> + 4162850102U, // <3,1,4,4>: Cost 3 vsldoi4 <0,3,1,4>, RHS + 3360924752U, // <3,1,4,5>: Cost 3 vsldoi12 LHS, <1,4,5,6> + 3497214129U, // <3,1,4,6>: Cost 4 vmrglw <1,2,3,4>, <0,2,1,6> + 3497215183U, // <3,1,4,7>: Cost 4 vmrglw <1,2,3,4>, <1,6,1,7> + 4162852654U, // <3,1,4,u>: Cost 3 vsldoi4 <0,3,1,4>, LHS + 3360924783U, // <3,1,5,0>: Cost 3 vsldoi12 LHS, <1,5,0,1> + 3360924792U, // <3,1,5,1>: Cost 4 vsldoi12 LHS, <1,5,1,1> + 3492579478U, // <3,1,5,2>: Cost 4 vmrglw <0,4,3,5>, <3,0,1,2> + 3360924809U, // <3,1,5,3>: Cost 4 vsldoi12 LHS, <1,5,3,0> + 3360924823U, // <3,1,5,4>: Cost 3 vsldoi12 LHS, <1,5,4,5> + 3502530898U, // <3,1,5,5>: Cost 3 vmrglw <2,1,3,5>, <0,4,1,5> + 3269234786U, // <3,1,5,6>: Cost 4 vsldoi8 , <5,6,7,0> + 3404055726U, // <3,1,5,7>: Cost 4 vsldoi12 LHS, <1,5,7,1> + 3360924855U, // <3,1,5,u>: Cost 3 vsldoi12 LHS, <1,5,u,1> + 3360924864U, // <3,1,6,0>: Cost 4 vsldoi12 LHS, <1,6,0,1> + 3360924879U, // <3,1,6,1>: Cost 3 vsldoi12 LHS, <1,6,1,7> + 3377398678U, // <3,1,6,2>: Cost 3 vmrghw <3,6,0,7>, <1,2,3,0> + 3356869857U, // <3,1,6,3>: Cost 4 vsldoi12 <0,2,1,3>, <1,6,3,7> + 3360924904U, // <3,1,6,4>: Cost 4 vsldoi12 LHS, <1,6,4,5> + 3360924915U, // <3,1,6,5>: Cost 3 vsldoi12 LHS, <1,6,5,7> + 3360924924U, // <3,1,6,6>: Cost 4 vsldoi12 LHS, <1,6,6,7> + 3404055806U, // <3,1,6,7>: Cost 3 vsldoi12 LHS, <1,6,7,0> + 3360924942U, // <3,1,6,u>: Cost 3 vsldoi12 LHS, <1,6,u,7> + 4168843366U, // <3,1,7,0>: Cost 4 vsldoi4 <1,3,1,7>, LHS + 3505864714U, // <3,1,7,1>: Cost 3 vmrglw <2,6,3,7>, <0,0,1,1> + 3505866902U, // <3,1,7,2>: Cost 3 vmrglw <2,6,3,7>, <3,0,1,2> + 3499892910U, // <3,1,7,3>: Cost 4 vmrglw <1,6,3,7>, <0,2,1,3> + 4168846646U, // <3,1,7,4>: Cost 4 vsldoi4 <1,3,1,7>, RHS + 3505865042U, // <3,1,7,5>: Cost 3 vmrglw <2,6,3,7>, <0,4,1,5> + 3505864881U, // <3,1,7,6>: Cost 3 vmrglw <2,6,3,7>, <0,2,1,6> + 3502548175U, // <3,1,7,7>: Cost 4 vmrglw <2,1,3,7>, <1,6,1,7> + 3505864721U, // <3,1,7,u>: Cost 3 vmrglw <2,6,3,7>, <0,0,1,u> + 4162879748U, // <3,1,u,0>: Cost 3 vsldoi4 <0,3,1,u>, <0,3,1,u> + 3356279604U, // <3,1,u,1>: Cost 2 vsldoi12 LHS, <1,1,1,1> + 3497248918U, // <3,1,u,2>: Cost 3 vmrglw <1,2,3,u>, <3,0,1,2> + 3356722556U, // <3,1,u,3>: Cost 2 vsldoi12 LHS, <1,u,3,0> + 4162882870U, // <3,1,u,4>: Cost 3 vsldoi4 <0,3,1,u>, RHS + 3360925073U, // <3,1,u,5>: Cost 3 vsldoi12 LHS, <1,u,5,3> + 3505864881U, // <3,1,u,6>: Cost 3 vmrglw <2,6,3,7>, <0,2,1,6> + 3404055968U, // <3,1,u,7>: Cost 3 vsldoi12 LHS, <1,u,7,0> + 3360925097U, // <3,1,u,u>: Cost 2 vsldoi12 LHS, <1,u,u,0> + 3497181931U, // <3,2,0,0>: Cost 4 vmrglw <1,2,3,0>, <1,0,2,0> + 3497181932U, // <3,2,0,1>: Cost 3 vmrglw <1,2,3,0>, <1,0,2,1> + 3497182014U, // <3,2,0,2>: Cost 3 vmrglw <1,2,3,0>, <1,1,2,2> + 2423439462U, // <3,2,0,3>: Cost 2 vmrglw <1,2,3,0>, LHS + 3497181935U, // <3,2,0,4>: Cost 4 vmrglw <1,2,3,0>, <1,0,2,4> + 3497182260U, // <3,2,0,5>: Cost 3 vmrglw <1,2,3,0>, <1,4,2,5> + 3373451194U, // <3,2,0,6>: Cost 3 vmrghw <3,0,1,2>, <2,6,3,7> + 3530360024U, // <3,2,0,7>: Cost 4 vmrglw <6,7,3,0>, <1,6,2,7> + 2423439467U, // <3,2,0,u>: Cost 2 vmrglw <1,2,3,0>, LHS + 4168867942U, // <3,2,1,0>: Cost 4 vsldoi4 <1,3,2,1>, LHS + 3228762932U, // <3,2,1,1>: Cost 4 vsldoi8 <1,2,3,2>, <1,1,1,1> + 3228763032U, // <3,2,1,2>: Cost 3 vsldoi8 <1,2,3,2>, <1,2,3,2> + 3356280351U, // <3,2,1,3>: Cost 3 vsldoi12 LHS, <2,1,3,1> + 4168871222U, // <3,2,1,4>: Cost 4 vsldoi4 <1,3,2,1>, RHS + 3360925232U, // <3,2,1,5>: Cost 5 vsldoi12 LHS, <2,1,5,0> + 3360925241U, // <3,2,1,6>: Cost 4 vsldoi12 LHS, <2,1,6,0> + 3404498500U, // <3,2,1,7>: Cost 4 vsldoi12 LHS, <2,1,7,2> + 3356722764U, // <3,2,1,u>: Cost 3 vsldoi12 LHS, <2,1,u,1> + 4174848102U, // <3,2,2,0>: Cost 3 vsldoi4 <2,3,2,2>, LHS + 3234072096U, // <3,2,2,1>: Cost 3 vsldoi8 <2,1,3,2>, <2,1,3,2> + 3356280424U, // <3,2,2,2>: Cost 2 vsldoi12 LHS, <2,2,2,2> + 3356280434U, // <3,2,2,3>: Cost 2 vsldoi12 LHS, <2,2,3,3> + 4174851382U, // <3,2,2,4>: Cost 3 vsldoi4 <2,3,2,2>, RHS + 3503171341U, // <3,2,2,5>: Cost 4 vmrglw <2,2,3,2>, <2,4,2,5> + 3375155130U, // <3,2,2,6>: Cost 3 vmrghw <3,2,6,3>, <2,6,3,7> + 3503171505U, // <3,2,2,7>: Cost 4 vmrglw <2,2,3,2>, <2,6,2,7> + 3356722847U, // <3,2,2,u>: Cost 2 vsldoi12 LHS, <2,2,u,3> + 3356280486U, // <3,2,3,0>: Cost 2 vsldoi12 LHS, <2,3,0,1> + 3356280495U, // <3,2,3,1>: Cost 3 vsldoi12 LHS, <2,3,1,1> + 3356280505U, // <3,2,3,2>: Cost 3 vsldoi12 LHS, <2,3,2,2> + 2429436006U, // <3,2,3,3>: Cost 2 vmrglw <2,2,3,3>, LHS + 3356280526U, // <3,2,3,4>: Cost 2 vsldoi12 LHS, <2,3,4,5> + 3404056279U, // <3,2,3,5>: Cost 3 vsldoi12 LHS, <2,3,5,5> + 3375597498U, // <3,2,3,6>: Cost 3 vmrghw <3,3,3,3>, <2,6,3,7> + 3404056292U, // <3,2,3,7>: Cost 3 vsldoi12 LHS, <2,3,7,0> + 3356280558U, // <3,2,3,u>: Cost 2 vsldoi12 LHS, <2,3,u,1> + 4168892518U, // <3,2,4,0>: Cost 4 vsldoi4 <1,3,2,4>, LHS + 3497214700U, // <3,2,4,1>: Cost 4 vmrglw <1,2,3,4>, <1,0,2,1> + 3497215592U, // <3,2,4,2>: Cost 3 vmrglw <1,2,3,4>, <2,2,2,2> + 2423472230U, // <3,2,4,3>: Cost 2 vmrglw <1,2,3,4>, LHS + 3497216404U, // <3,2,4,4>: Cost 4 vmrglw <1,2,3,4>, <3,3,2,4> + 3228765494U, // <3,2,4,5>: Cost 3 vsldoi8 <1,2,3,2>, RHS + 3376433082U, // <3,2,4,6>: Cost 3 vmrghw <3,4,5,6>, <2,6,3,7> + 4204729592U, // <3,2,4,7>: Cost 4 vsldoi4 <7,3,2,4>, <7,3,2,4> + 2423472235U, // <3,2,4,u>: Cost 2 vmrglw <1,2,3,4>, LHS + 4174872678U, // <3,2,5,0>: Cost 4 vsldoi4 <2,3,2,5>, LHS + 3502531713U, // <3,2,5,1>: Cost 4 vmrglw <2,1,3,5>, <1,5,2,1> + 3502532200U, // <3,2,5,2>: Cost 4 vmrglw <2,1,3,5>, <2,2,2,2> + 3360925544U, // <3,2,5,3>: Cost 3 vsldoi12 LHS, <2,5,3,6> + 4174875958U, // <3,2,5,4>: Cost 4 vsldoi4 <2,3,2,5>, RHS + 3377170280U, // <3,2,5,5>: Cost 4 vmrghw <3,5,6,6>, <2,5,3,6> + 3377244090U, // <3,2,5,6>: Cost 4 vmrghw <3,5,7,6>, <2,6,3,7> + 3504523185U, // <3,2,5,7>: Cost 5 vmrglw <2,4,3,5>, <2,6,2,7> + 3356723093U, // <3,2,5,u>: Cost 3 vsldoi12 LHS, <2,5,u,6> + 4174880870U, // <3,2,6,0>: Cost 3 vsldoi4 <2,3,2,6>, LHS + 4174881588U, // <3,2,6,1>: Cost 4 vsldoi4 <2,3,2,6>, <1,1,1,1> + 4174882493U, // <3,2,6,2>: Cost 3 vsldoi4 <2,3,2,6>, <2,3,2,6> + 3356280762U, // <3,2,6,3>: Cost 2 vsldoi12 LHS, <2,6,3,7> + 4174884150U, // <3,2,6,4>: Cost 3 vsldoi4 <2,3,2,6>, RHS + 3505194684U, // <3,2,6,5>: Cost 4 vmrglw <2,5,3,6>, <2,3,2,5> + 3377915834U, // <3,2,6,6>: Cost 3 vmrghw <3,6,7,7>, <2,6,3,7> + 3261944682U, // <3,2,6,7>: Cost 4 vsldoi8 <6,7,3,2>, <6,7,3,2> + 3356723175U, // <3,2,6,u>: Cost 2 vsldoi12 LHS, <2,6,u,7> + 3404056554U, // <3,2,7,0>: Cost 3 vsldoi12 LHS, <2,7,0,1> + 3505865452U, // <3,2,7,1>: Cost 4 vmrglw <2,6,3,7>, <1,0,2,1> + 3505866344U, // <3,2,7,2>: Cost 3 vmrglw <2,6,3,7>, <2,2,2,2> + 2432122982U, // <3,2,7,3>: Cost 2 vmrglw <2,6,3,7>, LHS + 4174892342U, // <3,2,7,4>: Cost 4 vsldoi4 <2,3,2,7>, RHS + 3505865780U, // <3,2,7,5>: Cost 4 vmrglw <2,6,3,7>, <1,4,2,5> + 3505866429U, // <3,2,7,6>: Cost 3 vmrglw <2,6,3,7>, <2,3,2,6> + 3505866430U, // <3,2,7,7>: Cost 4 vmrglw <2,6,3,7>, <2,3,2,7> + 2432122987U, // <3,2,7,u>: Cost 2 vmrglw <2,6,3,7>, LHS + 3356723259U, // <3,2,u,0>: Cost 2 vsldoi12 LHS, <2,u,0,1> + 3356723268U, // <3,2,u,1>: Cost 3 vsldoi12 LHS, <2,u,1,1> + 3356280424U, // <3,2,u,2>: Cost 2 vsldoi12 LHS, <2,2,2,2> + 3356280920U, // <3,2,u,3>: Cost 2 vsldoi12 LHS, <2,u,3,3> + 3356723299U, // <3,2,u,4>: Cost 2 vsldoi12 LHS, <2,u,4,5> + 3228768410U, // <3,2,u,5>: Cost 3 vsldoi8 <1,2,3,2>, RHS + 3378759610U, // <3,2,u,6>: Cost 3 vmrghw <3,u,1,2>, <2,6,3,7> + 3404499065U, // <3,2,u,7>: Cost 3 vsldoi12 LHS, <2,u,7,0> + 3356723331U, // <3,2,u,u>: Cost 2 vsldoi12 LHS, <2,u,u,1> + 2423440278U, // <3,3,0,0>: Cost 2 vmrglw <1,2,3,0>, <1,2,3,0> + 3356280982U, // <3,3,0,1>: Cost 2 vsldoi12 LHS, <3,0,1,2> + 4174907072U, // <3,3,0,2>: Cost 3 vsldoi4 <2,3,3,0>, <2,3,3,0> + 3497182834U, // <3,3,0,3>: Cost 3 vmrglw <1,2,3,0>, <2,2,3,3> + 3356281008U, // <3,3,0,4>: Cost 3 vsldoi12 LHS, <3,0,4,1> + 3497182755U, // <3,3,0,5>: Cost 4 vmrglw <1,2,3,0>, <2,1,3,5> + 3497183080U, // <3,3,0,6>: Cost 4 vmrglw <1,2,3,0>, <2,5,3,6> + 3497183162U, // <3,3,0,7>: Cost 3 vmrglw <1,2,3,0>, <2,6,3,7> + 3356281045U, // <3,3,0,u>: Cost 2 vsldoi12 LHS, <3,0,u,2> + 3360925916U, // <3,3,1,0>: Cost 4 vsldoi12 LHS, <3,1,0,0> + 3356281062U, // <3,3,1,1>: Cost 3 vsldoi12 LHS, <3,1,1,1> + 3356281073U, // <3,3,1,2>: Cost 3 vsldoi12 LHS, <3,1,2,3> + 3513117084U, // <3,3,1,3>: Cost 3 vmrglw <3,u,3,1>, <3,3,3,3> + 3360925952U, // <3,3,1,4>: Cost 4 vsldoi12 LHS, <3,1,4,0> + 3360925961U, // <3,3,1,5>: Cost 4 vsldoi12 LHS, <3,1,5,0> + 3360925971U, // <3,3,1,6>: Cost 4 vsldoi12 LHS, <3,1,6,1> + 3497191354U, // <3,3,1,7>: Cost 4 vmrglw <1,2,3,1>, <2,6,3,7> + 3356723495U, // <3,3,1,u>: Cost 3 vsldoi12 LHS, <3,1,u,3> + 4174921830U, // <3,3,2,0>: Cost 3 vsldoi4 <2,3,3,2>, LHS + 3356281145U, // <3,3,2,1>: Cost 4 vsldoi12 LHS, <3,2,1,3> + 3234743922U, // <3,3,2,2>: Cost 2 vsldoi8 <2,2,3,3>, <2,2,3,3> + 3356281160U, // <3,3,2,3>: Cost 3 vsldoi12 LHS, <3,2,3,0> + 4174925110U, // <3,3,2,4>: Cost 3 vsldoi4 <2,3,3,2>, RHS + 3356723554U, // <3,3,2,5>: Cost 4 vsldoi12 LHS, <3,2,5,u> + 3356281190U, // <3,3,2,6>: Cost 3 vsldoi12 LHS, <3,2,6,3> + 3375229295U, // <3,3,2,7>: Cost 3 vsldoi12 <3,2,7,3>, <3,2,7,3> + 3238725720U, // <3,3,2,u>: Cost 2 vsldoi8 <2,u,3,3>, <2,u,3,3> + 3107160166U, // <3,3,3,0>: Cost 2 vsldoi4 <3,3,3,3>, LHS + 3509815463U, // <3,3,3,1>: Cost 3 vmrglw <3,3,3,3>, <3,0,3,1> + 3234744642U, // <3,3,3,2>: Cost 3 vsldoi8 <2,2,3,3>, <3,2,2,3> + 1879883878U, // <3,3,3,3>: Cost 1 vspltisw3 LHS + 3107163446U, // <3,3,3,4>: Cost 2 vsldoi4 <3,3,3,3>, RHS + 3509815791U, // <3,3,3,5>: Cost 3 vmrglw <3,3,3,3>, <3,4,3,5> + 3234744979U, // <3,3,3,6>: Cost 3 vsldoi8 <2,2,3,3>, <3,6,3,7> + 3503179706U, // <3,3,3,7>: Cost 3 vmrglw <2,2,3,3>, <2,6,3,7> + 1879883878U, // <3,3,3,u>: Cost 1 vspltisw3 LHS + 3497214870U, // <3,3,4,0>: Cost 3 vmrglw <1,2,3,4>, <1,2,3,0> + 4174939034U, // <3,3,4,1>: Cost 3 vsldoi4 <2,3,3,4>, <1,2,3,4> + 4174939844U, // <3,3,4,2>: Cost 3 vsldoi4 <2,3,3,4>, <2,3,3,4> + 3497215602U, // <3,3,4,3>: Cost 3 vmrglw <1,2,3,4>, <2,2,3,3> + 2423473050U, // <3,3,4,4>: Cost 2 vmrglw <1,2,3,4>, <1,2,3,4> + 3356723714U, // <3,3,4,5>: Cost 2 vsldoi12 LHS, <3,4,5,6> + 3497215848U, // <3,3,4,6>: Cost 4 vmrglw <1,2,3,4>, <2,5,3,6> + 3497215930U, // <3,3,4,7>: Cost 3 vmrglw <1,2,3,4>, <2,6,3,7> + 3356723741U, // <3,3,4,u>: Cost 2 vsldoi12 LHS, <3,4,u,6> + 3361368609U, // <3,3,5,0>: Cost 4 vsldoi12 LHS, <3,5,0,1> + 3510495399U, // <3,3,5,1>: Cost 4 vmrglw <3,4,3,5>, <3,0,3,1> + 3234746100U, // <3,3,5,2>: Cost 4 vsldoi8 <2,2,3,3>, <5,2,2,3> + 3510495644U, // <3,3,5,3>: Cost 3 vmrglw <3,4,3,5>, <3,3,3,3> + 3361368649U, // <3,3,5,4>: Cost 4 vsldoi12 LHS, <3,5,4,5> + 3502532131U, // <3,3,5,5>: Cost 3 vmrglw <2,1,3,5>, <2,1,3,5> + 3404499549U, // <3,3,5,6>: Cost 3 vsldoi12 LHS, <3,5,6,7> + 3502532538U, // <3,3,5,7>: Cost 4 vmrglw <2,1,3,5>, <2,6,3,7> + 3404499567U, // <3,3,5,u>: Cost 3 vsldoi12 LHS, <3,5,u,7> + 3404057208U, // <3,3,6,0>: Cost 3 vsldoi12 LHS, <3,6,0,7> + 3377400049U, // <3,3,6,1>: Cost 4 vmrghw <3,6,0,7>, <3,1,2,3> + 3393145482U, // <3,3,6,2>: Cost 3 vsldoi12 <6,2,7,3>, <3,6,2,7> + 3368962707U, // <3,3,6,3>: Cost 3 vsldoi12 <2,2,3,3>, <3,6,3,7> + 3404057244U, // <3,3,6,4>: Cost 3 vsldoi12 LHS, <3,6,4,7> + 3404057253U, // <3,3,6,5>: Cost 4 vsldoi12 LHS, <3,6,5,7> + 3505194856U, // <3,3,6,6>: Cost 3 vmrglw <2,5,3,6>, <2,5,3,6> + 3261952875U, // <3,3,6,7>: Cost 3 vsldoi8 <6,7,3,3>, <6,7,3,3> + 3262616508U, // <3,3,6,u>: Cost 3 vsldoi8 <6,u,3,3>, <6,u,3,3> + 4174962790U, // <3,3,7,0>: Cost 3 vsldoi4 <2,3,3,7>, LHS + 4174963508U, // <3,3,7,1>: Cost 4 vsldoi4 <2,3,3,7>, <1,1,1,1> + 4174964423U, // <3,3,7,2>: Cost 3 vsldoi4 <2,3,3,7>, <2,3,3,7> + 3505866354U, // <3,3,7,3>: Cost 3 vmrglw <2,6,3,7>, <2,2,3,3> + 4174966070U, // <3,3,7,4>: Cost 3 vsldoi4 <2,3,3,7>, RHS + 3505866275U, // <3,3,7,5>: Cost 4 vmrglw <2,6,3,7>, <2,1,3,5> + 3505866276U, // <3,3,7,6>: Cost 4 vmrglw <2,6,3,7>, <2,1,3,6> + 2432124858U, // <3,3,7,7>: Cost 2 vmrglw <2,6,3,7>, <2,6,3,7> + 2432124858U, // <3,3,7,u>: Cost 2 vmrglw <2,6,3,7>, <2,6,3,7> + 2423440278U, // <3,3,u,0>: Cost 2 vmrglw <1,2,3,0>, <1,2,3,0> + 3356723998U, // <3,3,u,1>: Cost 2 vsldoi12 LHS, <3,u,1,2> + 3270580104U, // <3,3,u,2>: Cost 2 vsldoi8 , + 1879883878U, // <3,3,u,3>: Cost 1 vspltisw3 LHS + 3107163446U, // <3,3,u,4>: Cost 2 vsldoi4 <3,3,3,3>, RHS + 3356724038U, // <3,3,u,5>: Cost 2 vsldoi12 LHS, <3,u,5,6> + 3360926540U, // <3,3,u,6>: Cost 3 vsldoi12 LHS, <3,u,6,3> + 2432124858U, // <3,3,u,7>: Cost 2 vmrglw <2,6,3,7>, <2,6,3,7> + 1879883878U, // <3,3,u,u>: Cost 1 vspltisw3 LHS + 3228778496U, // <3,4,0,0>: Cost 3 vsldoi8 <1,2,3,4>, <0,0,0,0> + 3228778598U, // <3,4,0,1>: Cost 2 vsldoi8 <1,2,3,4>, LHS + 4174980809U, // <3,4,0,2>: Cost 3 vsldoi4 <2,3,4,0>, <2,3,4,0> + 3373452420U, // <3,4,0,3>: Cost 3 vmrghw <3,0,1,2>, <4,3,5,0> + 3228778834U, // <3,4,0,4>: Cost 3 vsldoi8 <1,2,3,4>, <0,4,1,5> + 2299710774U, // <3,4,0,5>: Cost 2 vmrghw <3,0,1,2>, RHS + 3373452670U, // <3,4,0,6>: Cost 4 vmrghw <3,0,1,2>, <4,6,5,7> + 3501165212U, // <3,4,0,7>: Cost 4 vmrglw <1,u,3,0>, <3,6,4,7> + 3228779165U, // <3,4,0,u>: Cost 2 vsldoi8 <1,2,3,4>, LHS + 4174987366U, // <3,4,1,0>: Cost 3 vsldoi4 <2,3,4,1>, LHS + 3228779316U, // <3,4,1,1>: Cost 3 vsldoi8 <1,2,3,4>, <1,1,1,1> + 3228779418U, // <3,4,1,2>: Cost 2 vsldoi8 <1,2,3,4>, <1,2,3,4> + 3228779481U, // <3,4,1,3>: Cost 4 vsldoi8 <1,2,3,4>, <1,3,1,4> + 4174990646U, // <3,4,1,4>: Cost 3 vsldoi4 <2,3,4,1>, RHS + 3360926690U, // <3,4,1,5>: Cost 3 vsldoi12 LHS, <4,1,5,0> + 3228779727U, // <3,4,1,6>: Cost 4 vsldoi8 <1,2,3,4>, <1,6,1,7> + 4204852487U, // <3,4,1,7>: Cost 4 vsldoi4 <7,3,4,1>, <7,3,4,1> + 3232761216U, // <3,4,1,u>: Cost 2 vsldoi8 <1,u,3,4>, <1,u,3,4> + 3228779981U, // <3,4,2,0>: Cost 4 vsldoi8 <1,2,3,4>, <2,0,3,0> + 3361369106U, // <3,4,2,1>: Cost 4 vsldoi12 LHS, <4,2,1,3> + 3228780136U, // <3,4,2,2>: Cost 3 vsldoi8 <1,2,3,4>, <2,2,2,2> + 3228780198U, // <3,4,2,3>: Cost 3 vsldoi8 <1,2,3,4>, <2,3,0,1> + 3236079381U, // <3,4,2,4>: Cost 3 vsldoi8 <2,4,3,4>, <2,4,3,4> + 3374714166U, // <3,4,2,5>: Cost 3 vmrghw <3,2,0,3>, RHS + 3228780474U, // <3,4,2,6>: Cost 3 vsldoi8 <1,2,3,4>, <2,6,3,7> + 3238070280U, // <3,4,2,7>: Cost 3 vsldoi8 <2,7,3,4>, <2,7,3,4> + 3228780603U, // <3,4,2,u>: Cost 3 vsldoi8 <1,2,3,4>, <2,u,0,1> + 3228780694U, // <3,4,3,0>: Cost 3 vsldoi8 <1,2,3,4>, <3,0,1,2> + 3228780774U, // <3,4,3,1>: Cost 4 vsldoi8 <1,2,3,4>, <3,1,1,1> + 3228780884U, // <3,4,3,2>: Cost 3 vsldoi8 <1,2,3,4>, <3,2,4,3> + 3228780956U, // <3,4,3,3>: Cost 3 vsldoi8 <1,2,3,4>, <3,3,3,3> + 3228781008U, // <3,4,3,4>: Cost 3 vsldoi8 <1,2,3,4>, <3,4,0,1> + 2301857078U, // <3,4,3,5>: Cost 2 vmrghw <3,3,3,3>, RHS + 3228781212U, // <3,4,3,6>: Cost 3 vsldoi8 <1,2,3,4>, <3,6,4,7> + 3503180444U, // <3,4,3,7>: Cost 4 vmrglw <2,2,3,3>, <3,6,4,7> + 2301857321U, // <3,4,3,u>: Cost 2 vmrghw <3,3,3,3>, RHS + 4175011942U, // <3,4,4,0>: Cost 3 vsldoi4 <2,3,4,4>, LHS + 4175012762U, // <3,4,4,1>: Cost 3 vsldoi4 <2,3,4,4>, <1,2,3,4> + 4175013581U, // <3,4,4,2>: Cost 3 vsldoi4 <2,3,4,4>, <2,3,4,4> + 3497216340U, // <3,4,4,3>: Cost 3 vmrglw <1,2,3,4>, <3,2,4,3> + 3404057808U, // <3,4,4,4>: Cost 2 vsldoi12 LHS, <4,4,4,4> + 3228781878U, // <3,4,4,5>: Cost 2 vsldoi8 <1,2,3,4>, RHS + 3497216586U, // <3,4,4,6>: Cost 4 vmrglw <1,2,3,4>, <3,5,4,6> + 3497216668U, // <3,4,4,7>: Cost 3 vmrglw <1,2,3,4>, <3,6,4,7> + 3228782121U, // <3,4,4,u>: Cost 2 vsldoi8 <1,2,3,4>, RHS + 3101278310U, // <3,4,5,0>: Cost 2 vsldoi4 <2,3,4,5>, LHS + 4175020852U, // <3,4,5,1>: Cost 3 vsldoi4 <2,3,4,5>, <1,1,1,1> + 3101279950U, // <3,4,5,2>: Cost 2 vsldoi4 <2,3,4,5>, <2,3,4,5> + 4175022230U, // <3,4,5,3>: Cost 3 vsldoi4 <2,3,4,5>, <3,0,1,2> + 3101281590U, // <3,4,5,4>: Cost 2 vsldoi4 <2,3,4,5>, RHS + 3504522958U, // <3,4,5,5>: Cost 3 vmrglw <2,4,3,5>, <2,3,4,5> + 1208798518U, // <3,4,5,6>: Cost 1 vsldoi12 LHS, RHS + 4204885259U, // <3,4,5,7>: Cost 3 vsldoi4 <7,3,4,5>, <7,3,4,5> + 1208798536U, // <3,4,5,u>: Cost 1 vsldoi12 LHS, RHS + 4175028326U, // <3,4,6,0>: Cost 4 vsldoi4 <2,3,4,6>, LHS + 3361369434U, // <3,4,6,1>: Cost 4 vsldoi12 LHS, <4,6,1,7> + 3270586874U, // <3,4,6,2>: Cost 3 vsldoi8 , <6,2,7,3> + 3375009132U, // <3,4,6,3>: Cost 4 vsldoi12 <3,2,4,3>, <4,6,3,7> + 3404057973U, // <3,4,6,4>: Cost 3 vsldoi12 LHS, <4,6,4,7> + 3377401142U, // <3,4,6,5>: Cost 3 vmrghw <3,6,0,7>, RHS + 3270587192U, // <3,4,6,6>: Cost 3 vsldoi8 , <6,6,6,6> + 3261961068U, // <3,4,6,7>: Cost 3 vsldoi8 <6,7,3,4>, <6,7,3,4> + 3377401385U, // <3,4,6,u>: Cost 3 vmrghw <3,6,0,7>, RHS + 3270587386U, // <3,4,7,0>: Cost 3 vsldoi8 , <7,0,1,2> + 3505864741U, // <3,4,7,1>: Cost 4 vmrglw <2,6,3,7>, <0,0,4,1> + 3264615600U, // <3,4,7,2>: Cost 3 vsldoi8 <7,2,3,4>, <7,2,3,4> + 3505867092U, // <3,4,7,3>: Cost 4 vmrglw <2,6,3,7>, <3,2,4,3> + 3270587750U, // <3,4,7,4>: Cost 3 vsldoi8 , <7,4,5,6> + 3505866446U, // <3,4,7,5>: Cost 3 vmrglw <2,6,3,7>, <2,3,4,5> + 3505864908U, // <3,4,7,6>: Cost 4 vmrglw <2,6,3,7>, <0,2,4,6> + 3270588012U, // <3,4,7,7>: Cost 3 vsldoi8 , <7,7,7,7> + 3505866449U, // <3,4,7,u>: Cost 3 vmrglw <2,6,3,7>, <2,3,4,u> + 3101302886U, // <3,4,u,0>: Cost 2 vsldoi4 <2,3,4,u>, LHS + 3228784430U, // <3,4,u,1>: Cost 2 vsldoi8 <1,2,3,4>, LHS + 3101304529U, // <3,4,u,2>: Cost 2 vsldoi4 <2,3,4,u>, <2,3,4,u> + 3228784572U, // <3,4,u,3>: Cost 3 vsldoi8 <1,2,3,4>, + 3101306166U, // <3,4,u,4>: Cost 2 vsldoi4 <2,3,4,u>, RHS + 3228784794U, // <3,4,u,5>: Cost 2 vsldoi8 <1,2,3,4>, RHS + 1208798761U, // <3,4,u,6>: Cost 1 vsldoi12 LHS, RHS + 4204909838U, // <3,4,u,7>: Cost 3 vsldoi4 <7,3,4,u>, <7,3,4,u> + 1208798779U, // <3,4,u,u>: Cost 1 vsldoi12 LHS, RHS + 4186996838U, // <3,5,0,0>: Cost 3 vsldoi4 <4,3,5,0>, LHS + 3360927304U, // <3,5,0,1>: Cost 3 vsldoi12 LHS, <5,0,1,2> + 3538988571U, // <3,5,0,2>: Cost 3 vmrglw , <4,u,5,2> + 4186998934U, // <3,5,0,3>: Cost 3 vsldoi4 <4,3,5,0>, <3,0,1,2> + 3360927330U, // <3,5,0,4>: Cost 3 vsldoi12 LHS, <5,0,4,1> + 3404058219U, // <3,5,0,5>: Cost 3 vsldoi12 LHS, <5,0,5,1> + 3497183746U, // <3,5,0,6>: Cost 3 vmrglw <1,2,3,0>, <3,4,5,6> + 3497182451U, // <3,5,0,7>: Cost 4 vmrglw <1,2,3,0>, <1,6,5,7> + 3360927366U, // <3,5,0,u>: Cost 3 vsldoi12 LHS, <5,0,u,1> + 3404058255U, // <3,5,1,0>: Cost 3 vsldoi12 LHS, <5,1,0,1> + 3540986770U, // <3,5,1,1>: Cost 3 vmrglw , <4,0,5,1> + 3228787611U, // <3,5,1,2>: Cost 3 vsldoi8 <1,2,3,5>, <1,2,3,5> + 3363139246U, // <3,5,1,3>: Cost 4 vsldoi12 <1,2,5,3>, <5,1,3,5> + 3404058295U, // <3,5,1,4>: Cost 3 vsldoi12 LHS, <5,1,4,5> + 3360927419U, // <3,5,1,5>: Cost 4 vsldoi12 LHS, <5,1,5,0> + 3360927433U, // <3,5,1,6>: Cost 4 vsldoi12 LHS, <5,1,6,5> + 3404058317U, // <3,5,1,7>: Cost 4 vsldoi12 LHS, <5,1,7,0> + 3404058327U, // <3,5,1,u>: Cost 3 vsldoi12 LHS, <5,1,u,1> + 3234096575U, // <3,5,2,0>: Cost 4 vsldoi8 <2,1,3,5>, <2,0,1,4> + 3234096675U, // <3,5,2,1>: Cost 3 vsldoi8 <2,1,3,5>, <2,1,3,5> + 3360927475U, // <3,5,2,2>: Cost 4 vsldoi12 LHS, <5,2,2,2> + 3236087502U, // <3,5,2,3>: Cost 3 vsldoi8 <2,4,3,5>, <2,3,4,5> + 3236087574U, // <3,5,2,4>: Cost 3 vsldoi8 <2,4,3,5>, <2,4,3,5> + 3387027215U, // <3,5,2,5>: Cost 3 vsldoi12 <5,2,5,3>, <5,2,5,3> + 3387100952U, // <3,5,2,6>: Cost 3 vsldoi12 <5,2,6,3>, <5,2,6,3> + 3387174689U, // <3,5,2,7>: Cost 4 vsldoi12 <5,2,7,3>, <5,2,7,3> + 3238742106U, // <3,5,2,u>: Cost 3 vsldoi8 <2,u,3,5>, <2,u,3,5> + 4187021414U, // <3,5,3,0>: Cost 3 vsldoi4 <4,3,5,3>, LHS + 3539012498U, // <3,5,3,1>: Cost 3 vmrglw , <4,0,5,1> + 4169107058U, // <3,5,3,2>: Cost 4 vsldoi4 <1,3,5,3>, <2,2,3,3> + 3242060188U, // <3,5,3,3>: Cost 3 vsldoi8 <3,4,3,5>, <3,3,3,3> + 3242060271U, // <3,5,3,4>: Cost 3 vsldoi8 <3,4,3,5>, <3,4,3,5> + 3539012826U, // <3,5,3,5>: Cost 3 vmrglw , <4,4,5,5> + 3503180290U, // <3,5,3,6>: Cost 3 vmrglw <2,2,3,3>, <3,4,5,6> + 3503178995U, // <3,5,3,7>: Cost 4 vmrglw <2,2,3,3>, <1,6,5,7> + 3503180292U, // <3,5,3,u>: Cost 3 vmrglw <2,2,3,3>, <3,4,5,u> + 4187029606U, // <3,5,4,0>: Cost 3 vsldoi4 <4,3,5,4>, LHS + 3539020690U, // <3,5,4,1>: Cost 3 vmrglw , <4,0,5,1> + 3376434968U, // <3,5,4,2>: Cost 3 vmrghw <3,4,5,6>, <5,2,6,3> + 4187032066U, // <3,5,4,3>: Cost 3 vsldoi4 <4,3,5,4>, <3,4,5,6> + 3272584410U, // <3,5,4,4>: Cost 3 vsldoi8 , <4,4,5,5> + 3360927668U, // <3,5,4,5>: Cost 3 vsldoi12 LHS, <5,4,5,6> + 3497216514U, // <3,5,4,6>: Cost 3 vmrglw <1,2,3,4>, <3,4,5,6> + 3497215219U, // <3,5,4,7>: Cost 4 vmrglw <1,2,3,4>, <1,6,5,7> + 3360927695U, // <3,5,4,u>: Cost 3 vsldoi12 LHS, <5,4,u,6> + 3404058579U, // <3,5,5,0>: Cost 3 vsldoi12 LHS, <5,5,0,1> + 3404058588U, // <3,5,5,1>: Cost 3 vsldoi12 LHS, <5,5,1,1> + 4175095511U, // <3,5,5,2>: Cost 3 vsldoi4 <2,3,5,5>, <2,3,5,5> + 3363139568U, // <3,5,5,3>: Cost 4 vsldoi12 <1,2,5,3>, <5,5,3,3> + 3404058619U, // <3,5,5,4>: Cost 3 vsldoi12 LHS, <5,5,4,5> + 3404058628U, // <3,5,5,5>: Cost 2 vsldoi12 LHS, <5,5,5,5> + 3404058638U, // <3,5,5,6>: Cost 3 vsldoi12 LHS, <5,5,6,6> + 3502531827U, // <3,5,5,7>: Cost 4 vmrglw <2,1,3,5>, <1,6,5,7> + 3404058628U, // <3,5,5,u>: Cost 2 vsldoi12 LHS, <5,5,5,5> + 3404058660U, // <3,5,6,0>: Cost 3 vsldoi12 LHS, <5,6,0,1> + 3404058675U, // <3,5,6,1>: Cost 3 vsldoi12 LHS, <5,6,1,7> + 4175103704U, // <3,5,6,2>: Cost 3 vsldoi4 <2,3,5,6>, <2,3,5,6> + 3404058690U, // <3,5,6,3>: Cost 3 vsldoi12 LHS, <5,6,3,4> + 3404058700U, // <3,5,6,4>: Cost 3 vsldoi12 LHS, <5,6,4,5> + 3404058711U, // <3,5,6,5>: Cost 3 vsldoi12 LHS, <5,6,5,7> + 3505195522U, // <3,5,6,6>: Cost 3 vmrglw <2,5,3,6>, <3,4,5,6> + 3404058722U, // <3,5,6,7>: Cost 2 vsldoi12 LHS, <5,6,7,0> + 3404058731U, // <3,5,6,u>: Cost 2 vsldoi12 LHS, <5,6,u,0> + 4169138278U, // <3,5,7,0>: Cost 4 vsldoi4 <1,3,5,7>, LHS + 3541699474U, // <3,5,7,1>: Cost 3 vmrglw , <4,0,5,1> + 4169140154U, // <3,5,7,2>: Cost 4 vsldoi4 <1,3,5,7>, <2,6,3,7> + 3505865643U, // <3,5,7,3>: Cost 4 vmrglw <2,6,3,7>, <1,2,5,3> + 4169141558U, // <3,5,7,4>: Cost 4 vsldoi4 <1,3,5,7>, RHS + 3541699802U, // <3,5,7,5>: Cost 3 vmrglw , <4,4,5,5> + 3505867266U, // <3,5,7,6>: Cost 3 vmrglw <2,6,3,7>, <3,4,5,6> + 3505202419U, // <3,5,7,7>: Cost 4 vmrglw <2,5,3,7>, <1,6,5,7> + 3505867268U, // <3,5,7,u>: Cost 3 vmrglw <2,6,3,7>, <3,4,5,u> + 3404058822U, // <3,5,u,0>: Cost 3 vsldoi12 LHS, <5,u,0,1> + 3360927952U, // <3,5,u,1>: Cost 3 vsldoi12 LHS, <5,u,1,2> + 3538988571U, // <3,5,u,2>: Cost 3 vmrglw , <4,u,5,2> + 3404058852U, // <3,5,u,3>: Cost 3 vsldoi12 LHS, <5,u,3,4> + 3404058861U, // <3,5,u,4>: Cost 3 vsldoi12 LHS, <5,u,4,4> + 3404058628U, // <3,5,u,5>: Cost 2 vsldoi12 LHS, <5,5,5,5> + 3497249282U, // <3,5,u,6>: Cost 3 vmrglw <1,2,3,u>, <3,4,5,6> + 3404058884U, // <3,5,u,7>: Cost 2 vsldoi12 LHS, <5,u,7,0> + 3404058893U, // <3,5,u,u>: Cost 2 vsldoi12 LHS, <5,u,u,0> + 3236757504U, // <3,6,0,0>: Cost 4 vsldoi8 <2,5,3,6>, <0,0,0,0> + 3236757606U, // <3,6,0,1>: Cost 3 vsldoi8 <2,5,3,6>, LHS + 3393147177U, // <3,6,0,2>: Cost 3 vsldoi12 <6,2,7,3>, <6,0,2,1> + 3497183590U, // <3,6,0,3>: Cost 4 vmrglw <1,2,3,0>, <3,2,6,3> + 3236757842U, // <3,6,0,4>: Cost 4 vsldoi8 <2,5,3,6>, <0,4,1,5> + 4193046374U, // <3,6,0,5>: Cost 4 vsldoi4 <5,3,6,0>, <5,3,6,0> + 3404058957U, // <3,6,0,6>: Cost 3 vsldoi12 LHS, <6,0,6,1> + 2423442742U, // <3,6,0,7>: Cost 2 vmrglw <1,2,3,0>, RHS + 2423442743U, // <3,6,0,u>: Cost 2 vmrglw <1,2,3,0>, RHS + 3404058984U, // <3,6,1,0>: Cost 4 vsldoi12 LHS, <6,1,0,1> + 3236758324U, // <3,6,1,1>: Cost 4 vsldoi8 <2,5,3,6>, <1,1,1,1> + 3228795804U, // <3,6,1,2>: Cost 3 vsldoi8 <1,2,3,6>, <1,2,3,6> + 3360928136U, // <3,6,1,3>: Cost 5 vsldoi12 LHS, <6,1,3,6> + 3404059024U, // <3,6,1,4>: Cost 4 vsldoi12 LHS, <6,1,4,5> + 3404059034U, // <3,6,1,5>: Cost 4 vsldoi12 LHS, <6,1,5,6> + 3537670968U, // <3,6,1,6>: Cost 4 vmrglw , <6,6,6,6> + 3497192758U, // <3,6,1,7>: Cost 3 vmrglw <1,2,3,1>, RHS + 3497192759U, // <3,6,1,u>: Cost 3 vmrglw <1,2,3,1>, RHS + 4205002854U, // <3,6,2,0>: Cost 3 vsldoi4 <7,3,6,2>, LHS + 3234104868U, // <3,6,2,1>: Cost 4 vsldoi8 <2,1,3,6>, <2,1,3,6> + 4175144669U, // <3,6,2,2>: Cost 3 vsldoi4 <2,3,6,2>, <2,3,6,2> + 3234768573U, // <3,6,2,3>: Cost 4 vsldoi8 <2,2,3,6>, <2,3,2,6> + 4205006134U, // <3,6,2,4>: Cost 3 vsldoi4 <7,3,6,2>, RHS + 3236759400U, // <3,6,2,5>: Cost 3 vsldoi8 <2,5,3,6>, <2,5,3,6> + 4205007354U, // <3,6,2,6>: Cost 3 vsldoi4 <7,3,6,2>, <6,2,7,3> + 3393147386U, // <3,6,2,7>: Cost 2 vsldoi12 <6,2,7,3>, <6,2,7,3> + 3393221123U, // <3,6,2,u>: Cost 2 vsldoi12 <6,2,u,3>, <6,2,u,3> + 3236759702U, // <3,6,3,0>: Cost 4 vsldoi8 <2,5,3,6>, <3,0,1,2> + 3507160553U, // <3,6,3,1>: Cost 4 vmrglw <2,u,3,3>, <2,0,6,1> + 3375600122U, // <3,6,3,2>: Cost 3 vmrghw <3,3,3,3>, <6,2,7,3> + 3503180134U, // <3,6,3,3>: Cost 4 vmrglw <2,2,3,3>, <3,2,6,3> + 3236760066U, // <3,6,3,4>: Cost 3 vsldoi8 <2,5,3,6>, <3,4,5,6> + 3236760156U, // <3,6,3,5>: Cost 4 vsldoi8 <2,5,3,6>, <3,5,6,6> + 3539014456U, // <3,6,3,6>: Cost 3 vmrglw , <6,6,6,6> + 2429439286U, // <3,6,3,7>: Cost 2 vmrglw <2,2,3,3>, RHS + 2429439287U, // <3,6,3,u>: Cost 2 vmrglw <2,2,3,3>, RHS + 3376435489U, // <3,6,4,0>: Cost 3 vmrghw <3,4,5,6>, <6,0,1,2> + 4187104154U, // <3,6,4,1>: Cost 4 vsldoi4 <4,3,6,4>, <1,2,3,4> + 3393147505U, // <3,6,4,2>: Cost 3 vsldoi12 <6,2,7,3>, <6,4,2,5> + 3376435762U, // <3,6,4,3>: Cost 3 vmrghw <3,4,5,6>, <6,3,4,5> + 3376435853U, // <3,6,4,4>: Cost 3 vmrghw <3,4,5,6>, <6,4,5,6> + 3236760886U, // <3,6,4,5>: Cost 3 vsldoi8 <2,5,3,6>, RHS + 3404059285U, // <3,6,4,6>: Cost 3 vsldoi12 LHS, <6,4,6,5> + 2423475510U, // <3,6,4,7>: Cost 2 vmrglw <1,2,3,4>, RHS + 2423475511U, // <3,6,4,u>: Cost 2 vmrglw <1,2,3,4>, RHS + 3404059308U, // <3,6,5,0>: Cost 4 vsldoi12 LHS, <6,5,0,1> + 3507176937U, // <3,6,5,1>: Cost 5 vmrglw <2,u,3,5>, <2,0,6,1> + 3393147581U, // <3,6,5,2>: Cost 4 vsldoi12 <6,2,7,3>, <6,5,2,0> + 3236761446U, // <3,6,5,3>: Cost 4 vsldoi8 <2,5,3,6>, <5,3,6,0> + 3404059348U, // <3,6,5,4>: Cost 4 vsldoi12 LHS, <6,5,4,5> + 3404059357U, // <3,6,5,5>: Cost 4 vsldoi12 LHS, <6,5,5,5> + 3393147624U, // <3,6,5,6>: Cost 4 vsldoi12 <6,2,7,3>, <6,5,6,7> + 3502533942U, // <3,6,5,7>: Cost 3 vmrglw <2,1,3,5>, RHS + 3502533943U, // <3,6,5,u>: Cost 3 vmrglw <2,1,3,5>, RHS + 3404059389U, // <3,6,6,0>: Cost 3 vsldoi12 LHS, <6,6,0,1> + 3404059398U, // <3,6,6,1>: Cost 4 vsldoi12 LHS, <6,6,1,1> + 3393147664U, // <3,6,6,2>: Cost 3 vsldoi12 <6,2,7,3>, <6,6,2,2> + 3375158042U, // <3,6,6,3>: Cost 4 vsldoi12 <3,2,6,3>, <6,6,3,3> + 3404059429U, // <3,6,6,4>: Cost 3 vsldoi12 LHS, <6,6,4,5> + 4193095532U, // <3,6,6,5>: Cost 4 vsldoi4 <5,3,6,6>, <5,3,6,6> + 3404059448U, // <3,6,6,6>: Cost 2 vsldoi12 LHS, <6,6,6,6> + 3404059458U, // <3,6,6,7>: Cost 2 vsldoi12 LHS, <6,6,7,7> + 3404059467U, // <3,6,6,u>: Cost 2 vsldoi12 LHS, <6,6,u,7> + 3404059470U, // <3,6,7,0>: Cost 2 vsldoi12 LHS, <6,7,0,1> + 3505866217U, // <3,6,7,1>: Cost 3 vmrglw <2,6,3,7>, <2,0,6,1> + 3396096866U, // <3,6,7,2>: Cost 3 vsldoi12 <6,7,2,3>, <6,7,2,3> + 3505867110U, // <3,6,7,3>: Cost 3 vmrglw <2,6,3,7>, <3,2,6,3> + 3404059510U, // <3,6,7,4>: Cost 2 vsldoi12 LHS, <6,7,4,5> + 3505866545U, // <3,6,7,5>: Cost 3 vmrglw <2,6,3,7>, <2,4,6,5> + 3505866384U, // <3,6,7,6>: Cost 3 vmrglw <2,6,3,7>, <2,2,6,6> + 2432126262U, // <3,6,7,7>: Cost 2 vmrglw <2,6,3,7>, RHS + 2432126263U, // <3,6,7,u>: Cost 2 vmrglw <2,6,3,7>, RHS + 3404059551U, // <3,6,u,0>: Cost 2 vsldoi12 LHS, <6,u,0,1> + 3236763438U, // <3,6,u,1>: Cost 3 vsldoi8 <2,5,3,6>, LHS + 3393147825U, // <3,6,u,2>: Cost 3 vsldoi12 <6,2,7,3>, <6,u,2,1> + 3396834236U, // <3,6,u,3>: Cost 3 vsldoi12 <6,u,3,3>, <6,u,3,3> + 3404059591U, // <3,6,u,4>: Cost 2 vsldoi12 LHS, <6,u,4,5> + 3236763802U, // <3,6,u,5>: Cost 3 vsldoi8 <2,5,3,6>, RHS + 3404059448U, // <3,6,u,6>: Cost 2 vsldoi12 LHS, <6,6,6,6> + 2423508278U, // <3,6,u,7>: Cost 2 vmrglw <1,2,3,u>, RHS + 2423508279U, // <3,6,u,u>: Cost 2 vmrglw <1,2,3,u>, RHS + 3237429248U, // <3,7,0,0>: Cost 3 vsldoi8 <2,6,3,7>, <0,0,0,0> + 3237429350U, // <3,7,0,1>: Cost 2 vsldoi8 <2,6,3,7>, LHS + 3237429425U, // <3,7,0,2>: Cost 3 vsldoi8 <2,6,3,7>, <0,2,1,6> + 3538989562U, // <3,7,0,3>: Cost 3 vmrglw , <6,2,7,3> + 3237429586U, // <3,7,0,4>: Cost 3 vsldoi8 <2,6,3,7>, <0,4,1,5> + 3404059682U, // <3,7,0,5>: Cost 3 vsldoi12 LHS, <7,0,5,6> + 4199092808U, // <3,7,0,6>: Cost 3 vsldoi4 <6,3,7,0>, <6,3,7,0> + 3404059695U, // <3,7,0,7>: Cost 3 vsldoi12 LHS, <7,0,7,1> + 3237429917U, // <3,7,0,u>: Cost 2 vsldoi8 <2,6,3,7>, LHS + 3237429987U, // <3,7,1,0>: Cost 4 vsldoi8 <2,6,3,7>, <1,0,1,1> + 3237430068U, // <3,7,1,1>: Cost 3 vsldoi8 <2,6,3,7>, <1,1,1,1> + 3237430166U, // <3,7,1,2>: Cost 3 vsldoi8 <2,6,3,7>, <1,2,3,0> + 3237430236U, // <3,7,1,3>: Cost 4 vsldoi8 <2,6,3,7>, <1,3,1,7> + 3237430315U, // <3,7,1,4>: Cost 4 vsldoi8 <2,6,3,7>, <1,4,1,5> + 3237430383U, // <3,7,1,5>: Cost 4 vsldoi8 <2,6,3,7>, <1,5,0,1> + 3231458529U, // <3,7,1,6>: Cost 4 vsldoi8 <1,6,3,7>, <1,6,3,7> + 3537670978U, // <3,7,1,7>: Cost 4 vmrglw , <6,6,7,7> + 3237430652U, // <3,7,1,u>: Cost 3 vsldoi8 <2,6,3,7>, <1,u,3,0> + 3237430761U, // <3,7,2,0>: Cost 3 vsldoi8 <2,6,3,7>, <2,0,6,1> + 3234113061U, // <3,7,2,1>: Cost 4 vsldoi8 <2,1,3,7>, <2,1,3,7> + 3237430888U, // <3,7,2,2>: Cost 3 vsldoi8 <2,6,3,7>, <2,2,2,2> + 3235440327U, // <3,7,2,3>: Cost 3 vsldoi8 <2,3,3,7>, <2,3,3,7> + 3237431089U, // <3,7,2,4>: Cost 3 vsldoi8 <2,6,3,7>, <2,4,6,5> + 3236767593U, // <3,7,2,5>: Cost 4 vsldoi8 <2,5,3,7>, <2,5,3,7> + 3237431226U, // <3,7,2,6>: Cost 2 vsldoi8 <2,6,3,7>, <2,6,3,7> + 3399120083U, // <3,7,2,7>: Cost 3 vsldoi12 <7,2,7,3>, <7,2,7,3> + 3238758492U, // <3,7,2,u>: Cost 2 vsldoi8 <2,u,3,7>, <2,u,3,7> + 3237431446U, // <3,7,3,0>: Cost 3 vsldoi8 <2,6,3,7>, <3,0,1,2> + 3237431526U, // <3,7,3,1>: Cost 4 vsldoi8 <2,6,3,7>, <3,1,1,1> + 3237431654U, // <3,7,3,2>: Cost 3 vsldoi8 <2,6,3,7>, <3,2,6,3> + 3237431708U, // <3,7,3,3>: Cost 3 vsldoi8 <2,6,3,7>, <3,3,3,3> + 3237431810U, // <3,7,3,4>: Cost 3 vsldoi8 <2,6,3,7>, <3,4,5,6> + 3237431909U, // <3,7,3,5>: Cost 4 vsldoi8 <2,6,3,7>, <3,5,7,6> + 3237431991U, // <3,7,3,6>: Cost 3 vsldoi8 <2,6,3,7>, <3,6,7,7> + 3237432003U, // <3,7,3,7>: Cost 3 vsldoi8 <2,6,3,7>, <3,7,0,1> + 3237432094U, // <3,7,3,u>: Cost 3 vsldoi8 <2,6,3,7>, <3,u,1,2> + 4199120998U, // <3,7,4,0>: Cost 3 vsldoi4 <6,3,7,4>, LHS + 3237432266U, // <3,7,4,1>: Cost 4 vsldoi8 <2,6,3,7>, <4,1,2,3> + 4199122874U, // <3,7,4,2>: Cost 3 vsldoi4 <6,3,7,4>, <2,6,3,7> + 3539022330U, // <3,7,4,3>: Cost 3 vmrglw , <6,2,7,3> + 4199124278U, // <3,7,4,4>: Cost 3 vsldoi4 <6,3,7,4>, RHS + 3237432630U, // <3,7,4,5>: Cost 2 vsldoi8 <2,6,3,7>, RHS + 4199125580U, // <3,7,4,6>: Cost 3 vsldoi4 <6,3,7,4>, <6,3,7,4> + 3404060023U, // <3,7,4,7>: Cost 3 vsldoi12 LHS, <7,4,7,5> + 3237432873U, // <3,7,4,u>: Cost 2 vsldoi8 <2,6,3,7>, RHS + 3237432904U, // <3,7,5,0>: Cost 4 vsldoi8 <2,6,3,7>, <5,0,1,2> + 3404060045U, // <3,7,5,1>: Cost 4 vsldoi12 LHS, <7,5,1,0> + 3237433086U, // <3,7,5,2>: Cost 4 vsldoi8 <2,6,3,7>, <5,2,3,4> + 3393148320U, // <3,7,5,3>: Cost 4 vsldoi12 <6,2,7,3>, <7,5,3,1> + 3237433268U, // <3,7,5,4>: Cost 4 vsldoi8 <2,6,3,7>, <5,4,5,6> + 3404060086U, // <3,7,5,5>: Cost 3 vsldoi12 LHS, <7,5,5,5> + 3404060097U, // <3,7,5,6>: Cost 3 vsldoi12 LHS, <7,5,6,7> + 3404060099U, // <3,7,5,7>: Cost 4 vsldoi12 LHS, <7,5,7,0> + 3404060115U, // <3,7,5,u>: Cost 3 vsldoi12 LHS, <7,5,u,7> + 3404060124U, // <3,7,6,0>: Cost 3 vsldoi12 LHS, <7,6,0,7> + 3404060133U, // <3,7,6,1>: Cost 4 vsldoi12 LHS, <7,6,1,7> + 3393148398U, // <3,7,6,2>: Cost 3 vsldoi12 <6,2,7,3>, <7,6,2,7> + 3237433928U, // <3,7,6,3>: Cost 3 vsldoi8 <2,6,3,7>, <6,3,7,0> + 3404060160U, // <3,7,6,4>: Cost 3 vsldoi12 LHS, <7,6,4,7> + 3393148424U, // <3,7,6,5>: Cost 4 vsldoi12 <6,2,7,3>, <7,6,5,6> + 3237434168U, // <3,7,6,6>: Cost 3 vsldoi8 <2,6,3,7>, <6,6,6,6> + 3404060180U, // <3,7,6,7>: Cost 3 vsldoi12 LHS, <7,6,7,0> + 3397129764U, // <3,7,6,u>: Cost 3 vsldoi12 <6,u,7,3>, <7,6,u,7> + 4181229670U, // <3,7,7,0>: Cost 3 vsldoi4 <3,3,7,7>, LHS + 3505866955U, // <3,7,7,1>: Cost 4 vmrglw <2,6,3,7>, <3,0,7,1> + 4181231546U, // <3,7,7,2>: Cost 3 vsldoi4 <3,3,7,7>, <2,6,3,7> + 3505867119U, // <3,7,7,3>: Cost 3 vmrglw <2,6,3,7>, <3,2,7,3> + 4181232950U, // <3,7,7,4>: Cost 3 vsldoi4 <3,3,7,7>, RHS + 3505867040U, // <3,7,7,5>: Cost 4 vmrglw <2,6,3,7>, <3,1,7,5> + 4199150159U, // <3,7,7,6>: Cost 3 vsldoi4 <6,3,7,7>, <6,3,7,7> + 3404060268U, // <3,7,7,7>: Cost 2 vsldoi12 LHS, <7,7,7,7> + 3404060268U, // <3,7,7,u>: Cost 2 vsldoi12 LHS, <7,7,7,7> + 3237435091U, // <3,7,u,0>: Cost 3 vsldoi8 <2,6,3,7>, + 3237435182U, // <3,7,u,1>: Cost 2 vsldoi8 <2,6,3,7>, LHS + 3237435269U, // <3,7,u,2>: Cost 3 vsldoi8 <2,6,3,7>, + 3237435324U, // <3,7,u,3>: Cost 3 vsldoi8 <2,6,3,7>, + 3237435455U, // <3,7,u,4>: Cost 3 vsldoi8 <2,6,3,7>, + 3237435546U, // <3,7,u,5>: Cost 2 vsldoi8 <2,6,3,7>, RHS + 3273267408U, // <3,7,u,6>: Cost 2 vsldoi8 , + 3404060268U, // <3,7,u,7>: Cost 2 vsldoi12 LHS, <7,7,7,7> + 3237435749U, // <3,7,u,u>: Cost 2 vsldoi8 <2,6,3,7>, LHS + 3356278784U, // <3,u,0,0>: Cost 2 vsldoi12 LHS, <0,0,0,0> + 3356726995U, // <3,u,0,1>: Cost 2 vsldoi12 LHS, + 3497181339U, // <3,u,0,2>: Cost 3 vmrglw <1,2,3,0>, <0,1,u,2> + 2423439516U, // <3,u,0,3>: Cost 2 vmrglw <1,2,3,0>, LHS + 3356727021U, // <3,u,0,4>: Cost 3 vsldoi12 LHS, + 2299713690U, // <3,u,0,5>: Cost 2 vmrghw <3,0,1,2>, RHS + 3497183773U, // <3,u,0,6>: Cost 3 vmrglw <1,2,3,0>, <3,4,u,6> + 2423442760U, // <3,u,0,7>: Cost 2 vmrglw <1,2,3,0>, RHS + 3356727058U, // <3,u,0,u>: Cost 2 vsldoi12 LHS, + 3101540454U, // <3,u,1,0>: Cost 2 vsldoi4 <2,3,u,1>, LHS + 3356279604U, // <3,u,1,1>: Cost 2 vsldoi12 LHS, <1,1,1,1> + 1208801070U, // <3,u,1,2>: Cost 1 vsldoi12 LHS, LHS + 3356727093U, // <3,u,1,3>: Cost 3 vsldoi12 LHS, + 3101543734U, // <3,u,1,4>: Cost 2 vsldoi4 <2,3,u,1>, RHS + 3360929606U, // <3,u,1,5>: Cost 3 vsldoi12 LHS, + 3404060502U, // <3,u,1,6>: Cost 3 vsldoi12 LHS, + 3497192776U, // <3,u,1,7>: Cost 3 vmrglw <1,2,3,1>, RHS + 1208801124U, // <3,u,1,u>: Cost 1 vsldoi12 LHS, LHS + 3233457621U, // <3,u,2,0>: Cost 3 vsldoi8 <2,0,3,u>, <2,0,3,u> + 3361372022U, // <3,u,2,1>: Cost 3 vsldoi12 LHS, + 3234784887U, // <3,u,2,2>: Cost 2 vsldoi8 <2,2,3,u>, <2,2,3,u> + 3356727176U, // <3,u,2,3>: Cost 2 vsldoi12 LHS, + 4175293750U, // <3,u,2,4>: Cost 3 vsldoi4 <2,3,u,2>, RHS + 3236775786U, // <3,u,2,5>: Cost 3 vsldoi8 <2,5,3,u>, <2,5,3,u> + 3237439419U, // <3,u,2,6>: Cost 2 vsldoi8 <2,6,3,u>, <2,6,3,u> + 3404060588U, // <3,u,2,7>: Cost 2 vsldoi12 LHS, + 3360929717U, // <3,u,2,u>: Cost 2 vsldoi12 LHS, + 3356727228U, // <3,u,3,0>: Cost 2 vsldoi12 LHS, + 2301859630U, // <3,u,3,1>: Cost 2 vmrghw <3,3,3,3>, LHS + 3356727247U, // <3,u,3,2>: Cost 3 vsldoi12 LHS, + 1879883878U, // <3,u,3,3>: Cost 1 vspltisw3 LHS + 3356727268U, // <3,u,3,4>: Cost 2 vsldoi12 LHS, + 2301859994U, // <3,u,3,5>: Cost 2 vmrghw <3,3,3,3>, RHS + 3228814016U, // <3,u,3,6>: Cost 3 vsldoi8 <1,2,3,u>, <3,6,u,7> + 2429439304U, // <3,u,3,7>: Cost 2 vmrglw <2,2,3,3>, RHS + 1879883878U, // <3,u,3,u>: Cost 1 vspltisw3 LHS + 3497214915U, // <3,u,4,0>: Cost 3 vmrglw <1,2,3,4>, <1,2,u,0> + 2302695214U, // <3,u,4,1>: Cost 2 vmrghw <3,4,5,6>, LHS + 3497216213U, // <3,u,4,2>: Cost 3 vmrglw <1,2,3,4>, <3,0,u,2> + 2423472284U, // <3,u,4,3>: Cost 2 vmrglw <1,2,3,4>, LHS + 2423473050U, // <3,u,4,4>: Cost 2 vmrglw <1,2,3,4>, <1,2,3,4> + 3356727359U, // <3,u,4,5>: Cost 2 vsldoi12 LHS, + 3497216541U, // <3,u,4,6>: Cost 3 vmrglw <1,2,3,4>, <3,4,u,6> + 2423475528U, // <3,u,4,7>: Cost 2 vmrglw <1,2,3,4>, RHS + 3356727386U, // <3,u,4,u>: Cost 2 vsldoi12 LHS, + 3101573222U, // <3,u,5,0>: Cost 2 vsldoi4 <2,3,u,5>, LHS + 4175315764U, // <3,u,5,1>: Cost 3 vsldoi4 <2,3,u,5>, <1,1,1,1> + 3101574898U, // <3,u,5,2>: Cost 2 vsldoi4 <2,3,u,5>, <2,3,u,5> + 3356727422U, // <3,u,5,3>: Cost 3 vsldoi12 LHS, + 3101576502U, // <3,u,5,4>: Cost 2 vsldoi4 <2,3,u,5>, RHS + 3404058628U, // <3,u,5,5>: Cost 2 vsldoi12 LHS, <5,5,5,5> + 1208801434U, // <3,u,5,6>: Cost 1 vsldoi12 LHS, RHS + 3502533960U, // <3,u,5,7>: Cost 3 vmrglw <2,1,3,5>, RHS + 1208801452U, // <3,u,5,u>: Cost 1 vsldoi12 LHS, RHS + 4175323238U, // <3,u,6,0>: Cost 3 vsldoi4 <2,3,u,6>, LHS + 3361372350U, // <3,u,6,1>: Cost 3 vsldoi12 LHS, + 4175324915U, // <3,u,6,2>: Cost 3 vsldoi4 <2,3,u,6>, <2,3,u,6> + 3356727504U, // <3,u,6,3>: Cost 2 vsldoi12 LHS, + 4175326518U, // <3,u,6,4>: Cost 3 vsldoi4 <2,3,u,6>, RHS + 3377404058U, // <3,u,6,5>: Cost 3 vmrghw <3,6,0,7>, RHS + 3404059448U, // <3,u,6,6>: Cost 2 vsldoi12 LHS, <6,6,6,6> + 3404060909U, // <3,u,6,7>: Cost 2 vsldoi12 LHS, + 3360930045U, // <3,u,6,u>: Cost 2 vsldoi12 LHS, + 3404060928U, // <3,u,7,0>: Cost 2 vsldoi12 LHS, + 3505864777U, // <3,u,7,1>: Cost 3 vmrglw <2,6,3,7>, <0,0,u,1> + 4175333108U, // <3,u,7,2>: Cost 3 vsldoi4 <2,3,u,7>, <2,3,u,7> + 2432123036U, // <3,u,7,3>: Cost 2 vmrglw <2,6,3,7>, LHS + 3404060968U, // <3,u,7,4>: Cost 2 vsldoi12 LHS, + 3505865105U, // <3,u,7,5>: Cost 3 vmrglw <2,6,3,7>, <0,4,u,5> + 3505864944U, // <3,u,7,6>: Cost 3 vmrglw <2,6,3,7>, <0,2,u,6> + 2432126280U, // <3,u,7,7>: Cost 2 vmrglw <2,6,3,7>, RHS + 2432123041U, // <3,u,7,u>: Cost 2 vmrglw <2,6,3,7>, LHS + 3360930129U, // <3,u,u,0>: Cost 2 vsldoi12 LHS, + 3356727643U, // <3,u,u,1>: Cost 2 vsldoi12 LHS, + 1208801637U, // <3,u,u,2>: Cost 1 vsldoi12 LHS, LHS + 1879883878U, // <3,u,u,3>: Cost 1 vspltisw3 LHS + 3360930169U, // <3,u,u,4>: Cost 2 vsldoi12 LHS, + 3356727683U, // <3,u,u,5>: Cost 2 vsldoi12 LHS, + 1208801677U, // <3,u,u,6>: Cost 1 vsldoi12 LHS, RHS + 2423508296U, // <3,u,u,7>: Cost 2 vmrglw <1,2,3,u>, RHS + 1208801691U, // <3,u,u,u>: Cost 1 vsldoi12 LHS, LHS + 3362996224U, // <4,0,0,0>: Cost 3 vsldoi12 <1,2,3,4>, <0,0,0,0> + 2305966182U, // <4,0,0,1>: Cost 2 vmrghw <4,0,5,1>, LHS + 4187293385U, // <4,0,0,2>: Cost 4 vsldoi4 <4,4,0,0>, <2,3,4,0> + 3503893513U, // <4,0,0,3>: Cost 4 vmrglw <2,3,4,0>, <4,2,0,3> + 3355770920U, // <4,0,0,4>: Cost 3 vsldoi12 <0,0,4,4>, <0,0,4,4> + 3379708318U, // <4,0,0,5>: Cost 3 vmrghw <4,0,5,1>, <0,5,1,0> + 3379700205U, // <4,0,0,6>: Cost 4 vmrghw <4,0,5,0>, <0,6,0,7> + 3503893841U, // <4,0,0,7>: Cost 4 vmrglw <2,3,4,0>, <4,6,0,7> + 2305966749U, // <4,0,0,u>: Cost 2 vmrghw <4,0,5,1>, LHS + 4181327974U, // <4,0,1,0>: Cost 3 vsldoi4 <3,4,0,1>, LHS + 4181328794U, // <4,0,1,1>: Cost 3 vsldoi4 <3,4,0,1>, <1,2,3,4> + 3362996326U, // <4,0,1,2>: Cost 2 vsldoi12 <1,2,3,4>, LHS + 4181330384U, // <4,0,1,3>: Cost 3 vsldoi4 <3,4,0,1>, <3,4,0,1> + 4181331254U, // <4,0,1,4>: Cost 3 vsldoi4 <3,4,0,1>, RHS + 4205219942U, // <4,0,1,5>: Cost 3 vsldoi4 <7,4,0,1>, <5,6,7,4> + 4199248475U, // <4,0,1,6>: Cost 4 vsldoi4 <6,4,0,1>, <6,4,0,1> + 4205221172U, // <4,0,1,7>: Cost 3 vsldoi4 <7,4,0,1>, <7,4,0,1> + 3362996380U, // <4,0,1,u>: Cost 2 vsldoi12 <1,2,3,4>, LHS + 4181336166U, // <4,0,2,0>: Cost 4 vsldoi4 <3,4,0,2>, LHS + 3381051494U, // <4,0,2,1>: Cost 3 vmrghw <4,2,5,3>, LHS + 3234793080U, // <4,0,2,2>: Cost 4 vsldoi8 <2,2,4,0>, <2,2,4,0> + 3235456713U, // <4,0,2,3>: Cost 3 vsldoi8 <2,3,4,0>, <2,3,4,0> + 3507889833U, // <4,0,2,4>: Cost 4 vmrglw <3,0,4,2>, <2,3,0,4> + 3273942883U, // <4,0,2,5>: Cost 4 vsldoi8 , <2,5,3,1> + 3235456954U, // <4,0,2,6>: Cost 4 vsldoi8 <2,3,4,0>, <2,6,3,7> + 3520498296U, // <4,0,2,7>: Cost 5 vmrglw <5,1,4,2>, <3,6,0,7> + 3238774878U, // <4,0,2,u>: Cost 3 vsldoi8 <2,u,4,0>, <2,u,4,0> + 4169400422U, // <4,0,3,0>: Cost 4 vsldoi4 <1,4,0,3>, LHS + 3357540608U, // <4,0,3,1>: Cost 3 vsldoi12 <0,3,1,4>, <0,3,1,4> + 3235457364U, // <4,0,3,2>: Cost 4 vsldoi8 <2,3,4,0>, <3,2,4,3> + 3357540626U, // <4,0,3,3>: Cost 4 vsldoi12 <0,3,1,4>, <0,3,3,4> + 4169403702U, // <4,0,3,4>: Cost 4 vsldoi4 <1,4,0,3>, RHS + 3242756676U, // <4,0,3,5>: Cost 4 vsldoi8 <3,5,4,0>, <3,5,4,0> + 3235457692U, // <4,0,3,6>: Cost 4 vsldoi8 <2,3,4,0>, <3,6,4,7> + 3244083942U, // <4,0,3,7>: Cost 4 vsldoi8 <3,7,4,0>, <3,7,4,0> + 3357540608U, // <4,0,3,u>: Cost 3 vsldoi12 <0,3,1,4>, <0,3,1,4> + 3262000018U, // <4,0,4,0>: Cost 3 vsldoi8 <6,7,4,0>, <4,0,5,1> + 2308571238U, // <4,0,4,1>: Cost 2 vmrghw <4,4,4,4>, LHS + 3369410905U, // <4,0,4,2>: Cost 4 vsldoi12 <2,3,0,4>, <0,4,2,3> + 3235458139U, // <4,0,4,3>: Cost 4 vsldoi8 <2,3,4,0>, <4,3,0,4> + 3382313298U, // <4,0,4,4>: Cost 3 vmrghw <4,4,4,4>, <0,4,1,5> + 3235458358U, // <4,0,4,5>: Cost 3 vsldoi8 <2,3,4,0>, RHS + 3235458385U, // <4,0,4,6>: Cost 4 vsldoi8 <2,3,4,0>, <4,6,0,7> + 4205245751U, // <4,0,4,7>: Cost 4 vsldoi4 <7,4,0,4>, <7,4,0,4> + 2308571805U, // <4,0,4,u>: Cost 2 vmrghw <4,4,4,4>, LHS + 2309406720U, // <4,0,5,0>: Cost 2 vmrghw RHS, <0,0,0,0> + 1235664998U, // <4,0,5,1>: Cost 1 vmrghw RHS, LHS + 3383148717U, // <4,0,5,2>: Cost 3 vmrghw RHS, <0,2,1,2> + 4181363156U, // <4,0,5,3>: Cost 3 vsldoi4 <3,4,0,5>, <3,4,0,5> + 2309407058U, // <4,0,5,4>: Cost 2 vmrghw RHS, <0,4,1,5> + 3383157218U, // <4,0,5,5>: Cost 3 vmrghw RHS, <0,5,u,5> + 3383149046U, // <4,0,5,6>: Cost 3 vmrghw RHS, <0,6,1,7> + 4205253944U, // <4,0,5,7>: Cost 3 vsldoi4 <7,4,0,5>, <7,4,0,5> + 1235665565U, // <4,0,5,u>: Cost 1 vmrghw RHS, LHS + 3383689226U, // <4,0,6,0>: Cost 4 vmrghw <4,6,5,1>, <0,0,1,1> + 3383697510U, // <4,0,6,1>: Cost 3 vmrghw <4,6,5,2>, LHS + 3262001658U, // <4,0,6,2>: Cost 4 vsldoi8 <6,7,4,0>, <6,2,7,3> + 3259347501U, // <4,0,6,3>: Cost 4 vsldoi8 <6,3,4,0>, <6,3,4,0> + 3364766225U, // <4,0,6,4>: Cost 4 vsldoi12 <1,5,0,4>, <0,6,4,7> + 3262001899U, // <4,0,6,5>: Cost 4 vsldoi8 <6,7,4,0>, <6,5,7,1> + 3383730740U, // <4,0,6,6>: Cost 4 vmrghw <4,6,5,6>, <0,6,u,6> + 3262002033U, // <4,0,6,7>: Cost 3 vsldoi8 <6,7,4,0>, <6,7,4,0> + 3383698077U, // <4,0,6,u>: Cost 3 vmrghw <4,6,5,2>, LHS + 3511910400U, // <4,0,7,0>: Cost 4 vmrglw <3,6,4,7>, <0,0,0,0> + 3384344678U, // <4,0,7,1>: Cost 3 vmrghw <4,7,5,0>, LHS + 3238778058U, // <4,0,7,2>: Cost 5 vsldoi8 <2,u,4,0>, <7,2,6,3> + 3265320198U, // <4,0,7,3>: Cost 4 vsldoi8 <7,3,4,0>, <7,3,4,0> + 3384344914U, // <4,0,7,4>: Cost 4 vmrghw <4,7,5,0>, <0,4,1,5> + 3266647464U, // <4,0,7,5>: Cost 4 vsldoi8 <7,5,4,0>, <7,5,4,0> + 3384345078U, // <4,0,7,6>: Cost 5 vmrghw <4,7,5,0>, <0,6,1,7> + 3262002796U, // <4,0,7,7>: Cost 4 vsldoi8 <6,7,4,0>, <7,7,7,7> + 3384345245U, // <4,0,7,u>: Cost 3 vmrghw <4,7,5,0>, LHS + 2311397376U, // <4,0,u,0>: Cost 2 vmrghw RHS, <0,0,0,0> + 1237655654U, // <4,0,u,1>: Cost 1 vmrghw RHS, LHS + 3362996893U, // <4,0,u,2>: Cost 2 vsldoi12 <1,2,3,4>, LHS + 4181387735U, // <4,0,u,3>: Cost 3 vsldoi4 <3,4,0,u>, <3,4,0,u> + 2311397714U, // <4,0,u,4>: Cost 2 vmrghw RHS, <0,4,1,5> + 3235461274U, // <4,0,u,5>: Cost 3 vsldoi8 <2,3,4,0>, RHS + 3385139702U, // <4,0,u,6>: Cost 3 vmrghw RHS, <0,6,1,7> + 4205278523U, // <4,0,u,7>: Cost 3 vsldoi4 <7,4,0,u>, <7,4,0,u> + 1237656221U, // <4,0,u,u>: Cost 1 vmrghw RHS, LHS + 4211253350U, // <4,1,0,0>: Cost 3 vsldoi4 , LHS + 3226837094U, // <4,1,0,1>: Cost 3 vsldoi8 <0,u,4,1>, LHS + 3379422106U, // <4,1,0,2>: Cost 3 vmrghw <4,0,1,2>, <1,2,3,4> + 4181395928U, // <4,1,0,3>: Cost 4 vsldoi4 <3,4,1,0>, <3,4,1,0> + 3226837330U, // <4,1,0,4>: Cost 3 vsldoi8 <0,u,4,1>, <0,4,1,5> + 3495264594U, // <4,1,0,5>: Cost 4 vmrglw <0,u,4,0>, <0,4,1,5> + 4211257850U, // <4,1,0,6>: Cost 4 vsldoi4 , <6,2,7,3> + 4211258362U, // <4,1,0,7>: Cost 4 vsldoi4 , <7,0,1,2> + 3226837677U, // <4,1,0,u>: Cost 3 vsldoi8 <0,u,4,1>, <0,u,4,1> + 3227501310U, // <4,1,1,0>: Cost 4 vsldoi8 <1,0,4,1>, <1,0,4,1> + 3362186039U, // <4,1,1,1>: Cost 3 vsldoi12 <1,1,1,4>, <1,1,1,4> + 3235464090U, // <4,1,1,2>: Cost 3 vsldoi8 <2,3,4,1>, <1,2,3,4> + 3495275538U, // <4,1,1,3>: Cost 4 vmrglw <0,u,4,1>, <4,2,1,3> + 3357541202U, // <4,1,1,4>: Cost 4 vsldoi12 <0,3,1,4>, <1,1,4,4> + 3495272786U, // <4,1,1,5>: Cost 3 vmrglw <0,u,4,1>, <0,4,1,5> + 3226838259U, // <4,1,1,6>: Cost 4 vsldoi8 <0,u,4,1>, <1,6,5,7> + 3495275866U, // <4,1,1,7>: Cost 4 vmrglw <0,u,4,1>, <4,6,1,7> + 3380610432U, // <4,1,1,u>: Cost 3 vmrghw <4,1,u,3>, <1,u,3,4> + 4181409894U, // <4,1,2,0>: Cost 3 vsldoi4 <3,4,1,2>, LHS + 4181410714U, // <4,1,2,1>: Cost 3 vsldoi4 <3,4,1,2>, <1,2,3,4> + 3226838632U, // <4,1,2,2>: Cost 4 vsldoi8 <0,u,4,1>, <2,2,2,2> + 3362997146U, // <4,1,2,3>: Cost 2 vsldoi12 <1,2,3,4>, <1,2,3,4> + 4181413174U, // <4,1,2,4>: Cost 3 vsldoi4 <3,4,1,2>, RHS + 3495280978U, // <4,1,2,5>: Cost 4 vmrglw <0,u,4,2>, <0,4,1,5> + 3226838970U, // <4,1,2,6>: Cost 4 vsldoi8 <0,u,4,1>, <2,6,3,7> + 4205303102U, // <4,1,2,7>: Cost 4 vsldoi4 <7,4,1,2>, <7,4,1,2> + 3363365831U, // <4,1,2,u>: Cost 2 vsldoi12 <1,2,u,4>, <1,2,u,4> + 3239446704U, // <4,1,3,0>: Cost 3 vsldoi8 <3,0,4,1>, <3,0,4,1> + 3362997209U, // <4,1,3,1>: Cost 4 vsldoi12 <1,2,3,4>, <1,3,1,4> + 3363587042U, // <4,1,3,2>: Cost 4 vsldoi12 <1,3,2,4>, <1,3,2,4> + 3226839452U, // <4,1,3,3>: Cost 4 vsldoi8 <0,u,4,1>, <3,3,3,3> + 3244755458U, // <4,1,3,4>: Cost 3 vsldoi8 <3,u,4,1>, <3,4,5,6> + 3495289170U, // <4,1,3,5>: Cost 4 vmrglw <0,u,4,3>, <0,4,1,5> + 3235465884U, // <4,1,3,6>: Cost 4 vsldoi8 <2,3,4,1>, <3,6,4,7> + 3238783683U, // <4,1,3,7>: Cost 5 vsldoi8 <2,u,4,1>, <3,7,0,1> + 3244755768U, // <4,1,3,u>: Cost 3 vsldoi8 <3,u,4,1>, <3,u,4,1> + 4211286118U, // <4,1,4,0>: Cost 3 vsldoi4 , LHS + 3382313780U, // <4,1,4,1>: Cost 3 vmrghw <4,4,4,4>, <1,1,1,1> + 3382403994U, // <4,1,4,2>: Cost 3 vmrghw <4,4,5,6>, <1,2,3,4> + 3357541436U, // <4,1,4,3>: Cost 4 vsldoi12 <0,3,1,4>, <1,4,3,4> + 4211289296U, // <4,1,4,4>: Cost 3 vsldoi4 , <4,4,4,4> + 3226840374U, // <4,1,4,5>: Cost 3 vsldoi8 <0,u,4,1>, RHS + 3226840410U, // <4,1,4,6>: Cost 4 vsldoi8 <0,u,4,1>, <4,6,1,7> + 3397354588U, // <4,1,4,7>: Cost 4 vsldoi12 <7,0,1,4>, <1,4,7,0> + 3226840617U, // <4,1,4,u>: Cost 3 vsldoi8 <0,u,4,1>, RHS + 3089776978U, // <4,1,5,0>: Cost 2 vsldoi4 <0,4,1,5>, <0,4,1,5> + 2309407540U, // <4,1,5,1>: Cost 2 vmrghw RHS, <1,1,1,1> + 2309407638U, // <4,1,5,2>: Cost 2 vmrghw RHS, <1,2,3,0> + 4163520662U, // <4,1,5,3>: Cost 3 vsldoi4 <0,4,1,5>, <3,0,1,2> + 3089780022U, // <4,1,5,4>: Cost 2 vsldoi4 <0,4,1,5>, RHS + 4163522564U, // <4,1,5,5>: Cost 3 vsldoi4 <0,4,1,5>, <5,5,5,5> + 3383149775U, // <4,1,5,6>: Cost 3 vmrghw RHS, <1,6,1,7> + 4211299322U, // <4,1,5,7>: Cost 3 vsldoi4 , <7,0,1,2> + 3089782574U, // <4,1,5,u>: Cost 2 vsldoi4 <0,4,1,5>, LHS + 3244757281U, // <4,1,6,0>: Cost 4 vsldoi8 <3,u,4,1>, <6,0,1,2> + 3362997455U, // <4,1,6,1>: Cost 4 vsldoi12 <1,2,3,4>, <1,6,1,7> + 3383370650U, // <4,1,6,2>: Cost 4 vmrghw <4,6,0,7>, <1,2,3,4> + 3244757554U, // <4,1,6,3>: Cost 4 vsldoi8 <3,u,4,1>, <6,3,4,5> + 3357541610U, // <4,1,6,4>: Cost 4 vsldoi12 <0,3,1,4>, <1,6,4,7> + 3495313746U, // <4,1,6,5>: Cost 4 vmrglw <0,u,4,6>, <0,4,1,5> + 3251393336U, // <4,1,6,6>: Cost 4 vsldoi8 <5,0,4,1>, <6,6,6,6> + 3251393358U, // <4,1,6,7>: Cost 4 vsldoi8 <5,0,4,1>, <6,7,0,1> + 3362997518U, // <4,1,6,u>: Cost 4 vsldoi12 <1,2,3,4>, <1,6,u,7> + 3263337492U, // <4,1,7,0>: Cost 3 vsldoi8 <7,0,4,1>, <7,0,4,1> + 3511910410U, // <4,1,7,1>: Cost 4 vmrglw <3,6,4,7>, <0,0,1,1> + 3511912598U, // <4,1,7,2>: Cost 4 vmrglw <3,6,4,7>, <3,0,1,2> + 3265328391U, // <4,1,7,3>: Cost 4 vsldoi8 <7,3,4,1>, <7,3,4,1> + 3268646246U, // <4,1,7,4>: Cost 3 vsldoi8 <7,u,4,1>, <7,4,5,6> + 3511910738U, // <4,1,7,5>: Cost 4 vmrglw <3,6,4,7>, <0,4,1,5> + 3499967532U, // <4,1,7,6>: Cost 5 vmrglw <1,6,4,7>, <1,4,1,6> + 3251394156U, // <4,1,7,7>: Cost 4 vsldoi8 <5,0,4,1>, <7,7,7,7> + 3268646556U, // <4,1,7,u>: Cost 3 vsldoi8 <7,u,4,1>, <7,u,4,1> + 3089801557U, // <4,1,u,0>: Cost 2 vsldoi4 <0,4,1,u>, <0,4,1,u> + 2311398196U, // <4,1,u,1>: Cost 2 vmrghw RHS, <1,1,1,1> + 2311398294U, // <4,1,u,2>: Cost 2 vmrghw RHS, <1,2,3,0> + 3366978944U, // <4,1,u,3>: Cost 2 vsldoi12 <1,u,3,4>, <1,u,3,4> + 3089804598U, // <4,1,u,4>: Cost 2 vsldoi4 <0,4,1,u>, RHS + 3492675922U, // <4,1,u,5>: Cost 3 vmrglw <0,4,4,u>, <0,4,1,5> + 3385140431U, // <4,1,u,6>: Cost 3 vmrghw RHS, <1,6,1,7> + 4211323898U, // <4,1,u,7>: Cost 3 vsldoi4 , <7,0,1,2> + 3089807150U, // <4,1,u,u>: Cost 2 vsldoi4 <0,4,1,u>, LHS + 4199383142U, // <4,2,0,0>: Cost 4 vsldoi4 <6,4,2,0>, LHS + 3226845286U, // <4,2,0,1>: Cost 4 vsldoi8 <0,u,4,2>, LHS + 3379709544U, // <4,2,0,2>: Cost 3 vmrghw <4,0,5,1>, <2,2,2,2> + 3503890534U, // <4,2,0,3>: Cost 3 vmrglw <2,3,4,0>, LHS + 3226845522U, // <4,2,0,4>: Cost 4 vsldoi8 <0,u,4,2>, <0,4,1,5> + 3379709795U, // <4,2,0,5>: Cost 3 vmrghw <4,0,5,1>, <2,5,3,1> + 3379709882U, // <4,2,0,6>: Cost 3 vmrghw <4,0,5,1>, <2,6,3,7> + 3379709930U, // <4,2,0,7>: Cost 4 vmrghw <4,0,5,1>, <2,7,0,1> + 3503890539U, // <4,2,0,u>: Cost 3 vmrglw <2,3,4,0>, LHS + 4169531494U, // <4,2,1,0>: Cost 4 vsldoi4 <1,4,2,1>, LHS + 3380364835U, // <4,2,1,1>: Cost 4 vmrghw <4,1,5,0>, <2,1,3,5> + 3495274088U, // <4,2,1,2>: Cost 4 vmrglw <0,u,4,1>, <2,2,2,2> + 3495272550U, // <4,2,1,3>: Cost 3 vmrglw <0,u,4,1>, LHS + 3252061236U, // <4,2,1,4>: Cost 4 vsldoi8 <5,1,4,2>, <1,4,2,5> + 3380365154U, // <4,2,1,5>: Cost 4 vmrghw <4,1,5,0>, <2,5,3,0> + 3368527421U, // <4,2,1,6>: Cost 4 vsldoi12 <2,1,6,4>, <2,1,6,4> + 3503900593U, // <4,2,1,7>: Cost 5 vmrglw <2,3,4,1>, <2,6,2,7> + 3495272555U, // <4,2,1,u>: Cost 3 vmrglw <0,u,4,1>, LHS + 3368896085U, // <4,2,2,0>: Cost 4 vsldoi12 <2,2,2,4>, <2,2,0,1> + 4181484442U, // <4,2,2,1>: Cost 4 vsldoi4 <3,4,2,2>, <1,2,3,4> + 3362997864U, // <4,2,2,2>: Cost 3 vsldoi12 <1,2,3,4>, <2,2,2,2> + 3362997874U, // <4,2,2,3>: Cost 3 vsldoi12 <1,2,3,4>, <2,2,3,3> + 3368896120U, // <4,2,2,4>: Cost 4 vsldoi12 <2,2,2,4>, <2,2,4,0> + 3503245069U, // <4,2,2,5>: Cost 4 vmrglw <2,2,4,2>, <2,4,2,5> + 3381077946U, // <4,2,2,6>: Cost 3 vmrghw <4,2,5,6>, <2,6,3,7> + 4205376839U, // <4,2,2,7>: Cost 4 vsldoi4 <7,4,2,2>, <7,4,2,2> + 3362997919U, // <4,2,2,u>: Cost 3 vsldoi12 <1,2,3,4>, <2,2,u,3> + 3362997926U, // <4,2,3,0>: Cost 3 vsldoi12 <1,2,3,4>, <2,3,0,1> + 3362186927U, // <4,2,3,1>: Cost 4 vsldoi12 <1,1,1,4>, <2,3,1,1> + 3362997945U, // <4,2,3,2>: Cost 4 vsldoi12 <1,2,3,4>, <2,3,2,2> + 3362997956U, // <4,2,3,3>: Cost 3 vsldoi12 <1,2,3,4>, <2,3,3,4> + 3362997961U, // <4,2,3,4>: Cost 3 vsldoi12 <1,2,3,4>, <2,3,4,0> + 3369780950U, // <4,2,3,5>: Cost 4 vsldoi12 <2,3,5,4>, <2,3,5,4> + 3381749690U, // <4,2,3,6>: Cost 4 vmrghw <4,3,5,7>, <2,6,3,7> + 3369928424U, // <4,2,3,7>: Cost 3 vsldoi12 <2,3,7,4>, <2,3,7,4> + 3362997998U, // <4,2,3,u>: Cost 3 vsldoi12 <1,2,3,4>, <2,3,u,1> + 3368896247U, // <4,2,4,0>: Cost 4 vsldoi12 <2,2,2,4>, <2,4,0,1> + 3382314531U, // <4,2,4,1>: Cost 4 vmrghw <4,4,4,4>, <2,1,3,5> + 3382314600U, // <4,2,4,2>: Cost 3 vmrghw <4,4,4,4>, <2,2,2,2> + 2442788966U, // <4,2,4,3>: Cost 2 vmrglw <4,4,4,4>, LHS + 3382314773U, // <4,2,4,4>: Cost 3 vmrghw <4,4,4,4>, <2,4,3,4> + 3382396775U, // <4,2,4,5>: Cost 3 vmrghw <4,4,5,5>, <2,5,3,5> + 3382314938U, // <4,2,4,6>: Cost 3 vmrghw <4,4,4,4>, <2,6,3,7> + 4211364921U, // <4,2,4,7>: Cost 4 vsldoi4 , <7,0,u,2> + 2442788971U, // <4,2,4,u>: Cost 2 vmrglw <4,4,4,4>, LHS + 4169564262U, // <4,2,5,0>: Cost 3 vsldoi4 <1,4,2,5>, LHS + 4169565236U, // <4,2,5,1>: Cost 3 vsldoi4 <1,4,2,5>, <1,4,2,5> + 2309408360U, // <4,2,5,2>: Cost 2 vmrghw RHS, <2,2,2,2> + 2430189670U, // <4,2,5,3>: Cost 2 vmrglw <2,3,4,5>, LHS + 4169567542U, // <4,2,5,4>: Cost 3 vsldoi4 <1,4,2,5>, RHS + 3383150440U, // <4,2,5,5>: Cost 3 vmrghw RHS, <2,5,3,6> + 2309408698U, // <4,2,5,6>: Cost 2 vmrghw RHS, <2,6,3,7> + 3383150570U, // <4,2,5,7>: Cost 3 vmrghw RHS, <2,7,0,1> + 2430189675U, // <4,2,5,u>: Cost 2 vmrglw <2,3,4,5>, LHS + 4181516390U, // <4,2,6,0>: Cost 4 vsldoi4 <3,4,2,6>, LHS + 4181517210U, // <4,2,6,1>: Cost 4 vsldoi4 <3,4,2,6>, <1,2,3,4> + 3368896433U, // <4,2,6,2>: Cost 4 vsldoi12 <2,2,2,4>, <2,6,2,7> + 3362998202U, // <4,2,6,3>: Cost 3 vsldoi12 <1,2,3,4>, <2,6,3,7> + 3368896451U, // <4,2,6,4>: Cost 4 vsldoi12 <2,2,2,4>, <2,6,4,7> + 4205408358U, // <4,2,6,5>: Cost 4 vsldoi4 <7,4,2,6>, <5,6,7,4> + 3383699386U, // <4,2,6,6>: Cost 4 vmrghw <4,6,5,2>, <2,6,3,7> + 3262018419U, // <4,2,6,7>: Cost 4 vsldoi8 <6,7,4,2>, <6,7,4,2> + 3362998247U, // <4,2,6,u>: Cost 3 vsldoi12 <1,2,3,4>, <2,6,u,7> + 3404802026U, // <4,2,7,0>: Cost 4 vsldoi12 , <2,7,0,1> + 3264009318U, // <4,2,7,1>: Cost 4 vsldoi8 <7,1,4,2>, <7,1,4,2> + 3505940072U, // <4,2,7,2>: Cost 4 vmrglw <2,6,4,7>, <2,2,2,2> + 3511910502U, // <4,2,7,3>: Cost 3 vmrglw <3,6,4,7>, LHS + 3505940074U, // <4,2,7,4>: Cost 4 vmrglw <2,6,4,7>, <2,2,2,4> + 3505940237U, // <4,2,7,5>: Cost 5 vmrglw <2,6,4,7>, <2,4,2,5> + 3384346554U, // <4,2,7,6>: Cost 4 vmrghw <4,7,5,0>, <2,6,3,7> + 3384346602U, // <4,2,7,7>: Cost 4 vmrghw <4,7,5,0>, <2,7,0,1> + 3511910507U, // <4,2,7,u>: Cost 3 vmrglw <3,6,4,7>, LHS + 3362998331U, // <4,2,u,0>: Cost 3 vsldoi12 <1,2,3,4>, <2,u,0,1> + 4169589815U, // <4,2,u,1>: Cost 3 vsldoi4 <1,4,2,u>, <1,4,2,u> + 2311399016U, // <4,2,u,2>: Cost 2 vmrghw RHS, <2,2,2,2> + 2430214246U, // <4,2,u,3>: Cost 2 vmrglw <2,3,4,u>, LHS + 3362998371U, // <4,2,u,4>: Cost 3 vsldoi12 <1,2,3,4>, <2,u,4,5> + 3385141096U, // <4,2,u,5>: Cost 3 vmrghw RHS, <2,5,3,6> + 2311399354U, // <4,2,u,6>: Cost 2 vmrghw RHS, <2,6,3,7> + 3373246589U, // <4,2,u,7>: Cost 3 vsldoi12 <2,u,7,4>, <2,u,7,4> + 2430214251U, // <4,2,u,u>: Cost 2 vmrglw <2,3,4,u>, LHS + 3379710102U, // <4,3,0,0>: Cost 3 vmrghw <4,0,5,1>, <3,0,1,2> + 3362998422U, // <4,3,0,1>: Cost 3 vsldoi12 <1,2,3,4>, <3,0,1,2> + 3379423572U, // <4,3,0,2>: Cost 4 vmrghw <4,0,1,2>, <3,2,4,3> + 3379710364U, // <4,3,0,3>: Cost 3 vmrghw <4,0,5,1>, <3,3,3,3> + 3503891354U, // <4,3,0,4>: Cost 3 vmrglw <2,3,4,0>, <1,2,3,4> + 4205432934U, // <4,3,0,5>: Cost 4 vsldoi4 <7,4,3,0>, <5,6,7,4> + 3379423900U, // <4,3,0,6>: Cost 4 vmrghw <4,0,1,2>, <3,6,4,7> + 3503892410U, // <4,3,0,7>: Cost 4 vmrglw <2,3,4,0>, <2,6,3,7> + 3362998485U, // <4,3,0,u>: Cost 3 vsldoi12 <1,2,3,4>, <3,0,u,2> + 3495273366U, // <4,3,1,0>: Cost 4 vmrglw <0,u,4,1>, <1,2,3,0> + 3362187494U, // <4,3,1,1>: Cost 4 vsldoi12 <1,1,1,4>, <3,1,1,1> + 3240788890U, // <4,3,1,2>: Cost 3 vsldoi8 <3,2,4,3>, <1,2,3,4> + 3495274098U, // <4,3,1,3>: Cost 4 vmrglw <0,u,4,1>, <2,2,3,3> + 3503899546U, // <4,3,1,4>: Cost 3 vmrglw <2,3,4,1>, <1,2,3,4> + 3495274019U, // <4,3,1,5>: Cost 4 vmrglw <0,u,4,1>, <2,1,3,5> + 3513190248U, // <4,3,1,6>: Cost 4 vmrglw <3,u,4,1>, <2,5,3,6> + 3495274426U, // <4,3,1,7>: Cost 4 vmrglw <0,u,4,1>, <2,6,3,7> + 3240788890U, // <4,3,1,u>: Cost 3 vsldoi8 <3,2,4,3>, <1,2,3,4> + 3362998576U, // <4,3,2,0>: Cost 4 vsldoi12 <1,2,3,4>, <3,2,0,3> + 4181558170U, // <4,3,2,1>: Cost 4 vsldoi4 <3,4,3,2>, <1,2,3,4> + 3362998593U, // <4,3,2,2>: Cost 4 vsldoi12 <1,2,3,4>, <3,2,2,2> + 3374942540U, // <4,3,2,3>: Cost 3 vsldoi12 <3,2,3,4>, <3,2,3,4> + 3362998612U, // <4,3,2,4>: Cost 3 vsldoi12 <1,2,3,4>, <3,2,4,3> + 3357542754U, // <4,3,2,5>: Cost 5 vsldoi12 <0,3,1,4>, <3,2,5,u> + 3362998630U, // <4,3,2,6>: Cost 4 vsldoi12 <1,2,3,4>, <3,2,6,3> + 3389835631U, // <4,3,2,7>: Cost 4 vsldoi12 <5,6,7,4>, <3,2,7,3> + 3375311225U, // <4,3,2,u>: Cost 3 vsldoi12 <3,2,u,4>, <3,2,u,4> + 3381692566U, // <4,3,3,0>: Cost 3 vmrghw <4,3,5,0>, <3,0,1,2> + 3240126723U, // <4,3,3,1>: Cost 4 vsldoi8 <3,1,4,3>, <3,1,4,3> + 3240790356U, // <4,3,3,2>: Cost 3 vsldoi8 <3,2,4,3>, <3,2,4,3> + 3362998684U, // <4,3,3,3>: Cost 3 vsldoi12 <1,2,3,4>, <3,3,3,3> + 3362998694U, // <4,3,3,4>: Cost 3 vsldoi12 <1,2,3,4>, <3,3,4,4> + 3521169174U, // <4,3,3,5>: Cost 4 vmrglw <5,2,4,3>, <2,4,3,5> + 3240790684U, // <4,3,3,6>: Cost 4 vsldoi8 <3,2,4,3>, <3,6,4,7> + 3509225402U, // <4,3,3,7>: Cost 4 vmrglw <3,2,4,3>, <2,6,3,7> + 3244772154U, // <4,3,3,u>: Cost 3 vsldoi8 <3,u,4,3>, <3,u,4,3> + 3362998736U, // <4,3,4,0>: Cost 3 vsldoi12 <1,2,3,4>, <3,4,0,1> + 3362998746U, // <4,3,4,1>: Cost 3 vsldoi12 <1,2,3,4>, <3,4,1,2> + 4175603477U, // <4,3,4,2>: Cost 3 vsldoi4 <2,4,3,4>, <2,4,3,4> + 3382315420U, // <4,3,4,3>: Cost 3 vmrghw <4,4,4,4>, <3,3,3,3> + 3362998776U, // <4,3,4,4>: Cost 3 vsldoi12 <1,2,3,4>, <3,4,4,5> + 3357542914U, // <4,3,4,5>: Cost 3 vsldoi12 <0,3,1,4>, <3,4,5,6> + 3240791404U, // <4,3,4,6>: Cost 4 vsldoi8 <3,2,4,3>, <4,6,3,7> + 3516532666U, // <4,3,4,7>: Cost 3 vmrglw <4,4,4,4>, <2,6,3,7> + 3362998808U, // <4,3,4,u>: Cost 3 vsldoi12 <1,2,3,4>, <3,4,u,1> + 2309408918U, // <4,3,5,0>: Cost 2 vmrghw RHS, <3,0,1,2> + 3383150822U, // <4,3,5,1>: Cost 3 vmrghw RHS, <3,1,1,1> + 4175611670U, // <4,3,5,2>: Cost 3 vsldoi4 <2,4,3,5>, <2,4,3,5> + 2309409180U, // <4,3,5,3>: Cost 2 vmrghw RHS, <3,3,3,3> + 2309409282U, // <4,3,5,4>: Cost 2 vmrghw RHS, <3,4,5,6> + 3503933206U, // <4,3,5,5>: Cost 3 vmrglw <2,3,4,5>, <2,4,3,5> + 3383151224U, // <4,3,5,6>: Cost 3 vmrghw RHS, <3,6,0,7> + 3503933370U, // <4,3,5,7>: Cost 3 vmrglw <2,3,4,5>, <2,6,3,7> + 2309409566U, // <4,3,5,u>: Cost 2 vmrghw RHS, <3,u,1,2> + 3362998904U, // <4,3,6,0>: Cost 4 vsldoi12 <1,2,3,4>, <3,6,0,7> + 4181590938U, // <4,3,6,1>: Cost 4 vsldoi4 <3,4,3,6>, <1,2,3,4> + 3383593300U, // <4,3,6,2>: Cost 4 vmrghw <4,6,3,7>, <3,2,4,3> + 4181592560U, // <4,3,6,3>: Cost 4 vsldoi4 <3,4,3,6>, <3,4,3,6> + 3362998940U, // <4,3,6,4>: Cost 3 vsldoi12 <1,2,3,4>, <3,6,4,7> + 3495314979U, // <4,3,6,5>: Cost 5 vmrglw <0,u,4,6>, <2,1,3,5> + 3383732909U, // <4,3,6,6>: Cost 4 vmrghw <4,6,5,6>, <3,6,6,6> + 3377892020U, // <4,3,6,7>: Cost 3 vsldoi12 <3,6,7,4>, <3,6,7,4> + 3362998940U, // <4,3,6,u>: Cost 3 vsldoi12 <1,2,3,4>, <3,6,4,7> + 3511911318U, // <4,3,7,0>: Cost 4 vmrglw <3,6,4,7>, <1,2,3,0> + 3499969408U, // <4,3,7,1>: Cost 5 vmrglw <1,6,4,7>, <4,0,3,1> + 3264681144U, // <4,3,7,2>: Cost 3 vsldoi8 <7,2,4,3>, <7,2,4,3> + 3511912050U, // <4,3,7,3>: Cost 4 vmrglw <3,6,4,7>, <2,2,3,3> + 3511911322U, // <4,3,7,4>: Cost 3 vmrglw <3,6,4,7>, <1,2,3,4> + 4211462246U, // <4,3,7,5>: Cost 4 vsldoi4 , <5,6,7,4> + 3511912944U, // <4,3,7,6>: Cost 4 vmrglw <3,6,4,7>, <3,4,3,6> + 3509921722U, // <4,3,7,7>: Cost 4 vmrglw <3,3,4,7>, <2,6,3,7> + 3268662942U, // <4,3,7,u>: Cost 3 vsldoi8 <7,u,4,3>, <7,u,4,3> + 2311399574U, // <4,3,u,0>: Cost 2 vmrghw RHS, <3,0,1,2> + 3362999070U, // <4,3,u,1>: Cost 3 vsldoi12 <1,2,3,4>, <3,u,1,2> + 4175636249U, // <4,3,u,2>: Cost 3 vsldoi4 <2,4,3,u>, <2,4,3,u> + 2311399836U, // <4,3,u,3>: Cost 2 vmrghw RHS, <3,3,3,3> + 2311399938U, // <4,3,u,4>: Cost 2 vmrghw RHS, <3,4,5,6> + 3362999110U, // <4,3,u,5>: Cost 3 vsldoi12 <1,2,3,4>, <3,u,5,6> + 3385141880U, // <4,3,u,6>: Cost 3 vmrghw RHS, <3,6,0,7> + 3503957946U, // <4,3,u,7>: Cost 3 vmrglw <2,3,4,u>, <2,6,3,7> + 2311400222U, // <4,3,u,u>: Cost 2 vmrghw RHS, <3,u,1,2> + 2305969042U, // <4,4,0,0>: Cost 2 vmrghw <4,0,5,1>, <4,0,5,1> + 3248095334U, // <4,4,0,1>: Cost 2 vsldoi8 <4,4,4,4>, LHS + 4181616333U, // <4,4,0,2>: Cost 4 vsldoi4 <3,4,4,0>, <2,3,4,4> + 3357543296U, // <4,4,0,3>: Cost 4 vsldoi12 <0,3,1,4>, <4,0,3,1> + 3248095570U, // <4,4,0,4>: Cost 3 vsldoi8 <4,4,4,4>, <0,4,1,5> + 2305969462U, // <4,4,0,5>: Cost 2 vmrghw <4,0,5,1>, RHS + 3379711353U, // <4,4,0,6>: Cost 4 vmrghw <4,0,5,1>, <4,6,5,2> + 3503893148U, // <4,4,0,7>: Cost 4 vmrglw <2,3,4,0>, <3,6,4,7> + 2305969705U, // <4,4,0,u>: Cost 2 vmrghw <4,0,5,1>, RHS + 3503900361U, // <4,4,1,0>: Cost 4 vmrglw <2,3,4,1>, <2,3,4,0> + 3495273133U, // <4,4,1,1>: Cost 3 vmrglw <0,u,4,1>, <0,u,4,1> + 3362999242U, // <4,4,1,2>: Cost 3 vsldoi12 <1,2,3,4>, <4,1,2,3> + 3503901012U, // <4,4,1,3>: Cost 4 vmrglw <2,3,4,1>, <3,2,4,3> + 3519163600U, // <4,4,1,4>: Cost 3 vmrglw <4,u,4,1>, <4,4,4,4> + 3380170038U, // <4,4,1,5>: Cost 3 vmrghw <4,1,2,3>, RHS + 3248096499U, // <4,4,1,6>: Cost 4 vsldoi8 <4,4,4,4>, <1,6,5,7> + 3503901340U, // <4,4,1,7>: Cost 4 vmrglw <2,3,4,1>, <3,6,4,7> + 3366980608U, // <4,4,1,u>: Cost 3 vsldoi12 <1,u,3,4>, <4,1,u,3> + 4181631078U, // <4,4,2,0>: Cost 4 vsldoi4 <3,4,4,2>, LHS + 4181631898U, // <4,4,2,1>: Cost 4 vsldoi4 <3,4,4,2>, <1,2,3,4> + 3381054518U, // <4,4,2,2>: Cost 3 vmrghw <4,2,5,3>, <4,2,5,3> + 3235489485U, // <4,4,2,3>: Cost 3 vsldoi8 <2,3,4,4>, <2,3,4,4> + 3248097045U, // <4,4,2,4>: Cost 3 vsldoi8 <4,4,4,4>, <2,4,3,4> + 3381054774U, // <4,4,2,5>: Cost 3 vmrghw <4,2,5,3>, RHS + 3248097210U, // <4,4,2,6>: Cost 3 vsldoi8 <4,4,4,4>, <2,6,3,7> + 3362999368U, // <4,4,2,7>: Cost 4 vsldoi12 <1,2,3,4>, <4,2,7,3> + 3238807650U, // <4,4,2,u>: Cost 3 vsldoi8 <2,u,4,4>, <2,u,4,4> + 3248097430U, // <4,4,3,0>: Cost 3 vsldoi8 <4,4,4,4>, <3,0,1,2> + 3240134916U, // <4,4,3,1>: Cost 4 vsldoi8 <3,1,4,4>, <3,1,4,4> + 3362999405U, // <4,4,3,2>: Cost 4 vsldoi12 <1,2,3,4>, <4,3,2,4> + 3509225812U, // <4,4,3,3>: Cost 3 vmrglw <3,2,4,3>, <3,2,4,3> + 3242125815U, // <4,4,3,4>: Cost 3 vsldoi8 <3,4,4,4>, <3,4,4,4> + 3381693750U, // <4,4,3,5>: Cost 3 vmrghw <4,3,5,0>, RHS + 3362999441U, // <4,4,3,6>: Cost 4 vsldoi12 <1,2,3,4>, <4,3,6,4> + 3509226140U, // <4,4,3,7>: Cost 4 vmrglw <3,2,4,3>, <3,6,4,7> + 3509225812U, // <4,4,3,u>: Cost 3 vmrglw <3,2,4,3>, <3,2,4,3> + 3113877606U, // <4,4,4,0>: Cost 2 vsldoi4 <4,4,4,4>, LHS + 3516533641U, // <4,4,4,1>: Cost 3 vmrglw <4,4,4,4>, <4,0,4,1> + 4187620968U, // <4,4,4,2>: Cost 3 vsldoi4 <4,4,4,4>, <2,2,2,2> + 4181649911U, // <4,4,4,3>: Cost 3 vsldoi4 <3,4,4,4>, <3,4,4,4> + 1504103734U, // <4,4,4,4>: Cost 1 vspltisw0 RHS + 2308574518U, // <4,4,4,5>: Cost 2 vmrghw <4,4,4,4>, RHS + 4187623930U, // <4,4,4,6>: Cost 3 vsldoi4 <4,4,4,4>, <6,2,7,3> + 4205540699U, // <4,4,4,7>: Cost 3 vsldoi4 <7,4,4,4>, <7,4,4,4> + 1504103734U, // <4,4,4,u>: Cost 1 vspltisw0 RHS + 2309409682U, // <4,4,5,0>: Cost 2 vmrghw RHS, <4,0,5,1> + 4181656474U, // <4,4,5,1>: Cost 3 vsldoi4 <3,4,4,5>, <1,2,3,4> + 3383151669U, // <4,4,5,2>: Cost 3 vmrghw RHS, <4,2,5,2> + 4181658104U, // <4,4,5,3>: Cost 3 vsldoi4 <3,4,4,5>, <3,4,4,5> + 2309410010U, // <4,4,5,4>: Cost 2 vmrghw RHS, <4,4,5,5> + 1235668278U, // <4,4,5,5>: Cost 1 vmrghw RHS, RHS + 3362999606U, // <4,4,5,6>: Cost 2 vsldoi12 <1,2,3,4>, RHS + 3383160264U, // <4,4,5,7>: Cost 3 vmrghw RHS, <4,7,5,0> + 1235668521U, // <4,4,5,u>: Cost 1 vmrghw RHS, RHS + 3383700370U, // <4,4,6,0>: Cost 4 vmrghw <4,6,5,2>, <4,0,5,1> + 3221557675U, // <4,4,6,1>: Cost 4 vsldoi8 <0,0,4,4>, <6,1,7,5> + 3248099834U, // <4,4,6,2>: Cost 3 vsldoi8 <4,4,4,4>, <6,2,7,3> + 3259380273U, // <4,4,6,3>: Cost 4 vsldoi8 <6,3,4,4>, <6,3,4,4> + 3248099997U, // <4,4,6,4>: Cost 3 vsldoi8 <4,4,4,4>, <6,4,7,4> + 3383700790U, // <4,4,6,5>: Cost 3 vmrghw <4,6,5,2>, RHS + 3383700857U, // <4,4,6,6>: Cost 3 vmrghw <4,6,5,2>, <4,6,5,2> + 3262034805U, // <4,4,6,7>: Cost 3 vsldoi8 <6,7,4,4>, <6,7,4,4> + 3383701033U, // <4,4,6,u>: Cost 3 vmrghw <4,6,5,2>, RHS + 3248100346U, // <4,4,7,0>: Cost 3 vsldoi8 <4,4,4,4>, <7,0,1,2> + 3511912138U, // <4,4,7,1>: Cost 4 vmrglw <3,6,4,7>, <2,3,4,1> + 3398831536U, // <4,4,7,2>: Cost 4 vsldoi12 <7,2,3,4>, <4,7,2,3> + 3511912788U, // <4,4,7,3>: Cost 4 vmrglw <3,6,4,7>, <3,2,4,3> + 3266016603U, // <4,4,7,4>: Cost 3 vsldoi8 <7,4,4,4>, <7,4,4,4> + 3384347958U, // <4,4,7,5>: Cost 3 vmrghw <4,7,5,0>, RHS + 3401780696U, // <4,4,7,6>: Cost 4 vsldoi12 <7,6,7,4>, <4,7,6,7> + 3511913116U, // <4,4,7,7>: Cost 3 vmrglw <3,6,4,7>, <3,6,4,7> + 3384348201U, // <4,4,7,u>: Cost 3 vmrghw <4,7,5,0>, RHS + 2311400338U, // <4,4,u,0>: Cost 2 vmrghw RHS, <4,0,5,1> + 3248101166U, // <4,4,u,1>: Cost 2 vsldoi8 <4,4,4,4>, LHS + 3385142325U, // <4,4,u,2>: Cost 3 vmrghw RHS, <4,2,5,2> + 4181682683U, // <4,4,u,3>: Cost 3 vsldoi4 <3,4,4,u>, <3,4,4,u> + 1504103734U, // <4,4,u,4>: Cost 1 vspltisw0 RHS + 1237658934U, // <4,4,u,5>: Cost 1 vmrghw RHS, RHS + 3362999849U, // <4,4,u,6>: Cost 2 vsldoi12 <1,2,3,4>, RHS + 3385142728U, // <4,4,u,7>: Cost 3 vmrghw RHS, <4,7,5,0> + 1237659177U, // <4,4,u,u>: Cost 1 vmrghw RHS, RHS + 3235495936U, // <4,5,0,0>: Cost 3 vsldoi8 <2,3,4,5>, <0,0,0,0> + 3235496038U, // <4,5,0,1>: Cost 2 vsldoi8 <2,3,4,5>, LHS + 4181690062U, // <4,5,0,2>: Cost 3 vsldoi4 <3,4,5,0>, <2,3,4,5> + 4181690876U, // <4,5,0,3>: Cost 3 vsldoi4 <3,4,5,0>, <3,4,5,0> + 3224215917U, // <4,5,0,4>: Cost 3 vsldoi8 <0,4,4,5>, <0,4,4,5> + 3379712004U, // <4,5,0,5>: Cost 3 vmrghw <4,0,5,1>, <5,5,5,5> + 4205581174U, // <4,5,0,6>: Cost 3 vsldoi4 <7,4,5,0>, <6,7,4,5> + 4205581664U, // <4,5,0,7>: Cost 3 vsldoi4 <7,4,5,0>, <7,4,5,0> + 3235496605U, // <4,5,0,u>: Cost 2 vsldoi8 <2,3,4,5>, LHS + 3495275490U, // <4,5,1,0>: Cost 4 vmrglw <0,u,4,1>, <4,1,5,0> + 3228197715U, // <4,5,1,1>: Cost 3 vsldoi8 <1,1,4,5>, <1,1,4,5> + 3235496854U, // <4,5,1,2>: Cost 3 vsldoi8 <2,3,4,5>, <1,2,3,0> + 3495273387U, // <4,5,1,3>: Cost 4 vmrglw <0,u,4,1>, <1,2,5,3> + 3224216655U, // <4,5,1,4>: Cost 4 vsldoi8 <0,4,4,5>, <1,4,5,5> + 3230852247U, // <4,5,1,5>: Cost 3 vsldoi8 <1,5,4,5>, <1,5,4,5> + 3513190914U, // <4,5,1,6>: Cost 3 vmrglw <3,u,4,1>, <3,4,5,6> + 3495273715U, // <4,5,1,7>: Cost 4 vmrglw <0,u,4,1>, <1,6,5,7> + 3232843146U, // <4,5,1,u>: Cost 3 vsldoi8 <1,u,4,5>, <1,u,4,5> + 4181704806U, // <4,5,2,0>: Cost 3 vsldoi4 <3,4,5,2>, LHS + 3224217123U, // <4,5,2,1>: Cost 4 vsldoi8 <0,4,4,5>, <2,1,3,5> + 3234834045U, // <4,5,2,2>: Cost 3 vsldoi8 <2,2,4,5>, <2,2,4,5> + 3235497678U, // <4,5,2,3>: Cost 2 vsldoi8 <2,3,4,5>, <2,3,4,5> + 3235497750U, // <4,5,2,4>: Cost 3 vsldoi8 <2,3,4,5>, <2,4,3,5> + 3235497832U, // <4,5,2,5>: Cost 4 vsldoi8 <2,3,4,5>, <2,5,3,6> + 3235497914U, // <4,5,2,6>: Cost 3 vsldoi8 <2,3,4,5>, <2,6,3,7> + 3238152210U, // <4,5,2,7>: Cost 4 vsldoi8 <2,7,4,5>, <2,7,4,5> + 3238815843U, // <4,5,2,u>: Cost 2 vsldoi8 <2,u,4,5>, <2,u,4,5> + 3235498134U, // <4,5,3,0>: Cost 3 vsldoi8 <2,3,4,5>, <3,0,1,2> + 3228199145U, // <4,5,3,1>: Cost 4 vsldoi8 <1,1,4,5>, <3,1,1,4> + 3235498316U, // <4,5,3,2>: Cost 3 vsldoi8 <2,3,4,5>, <3,2,3,4> + 3235498396U, // <4,5,3,3>: Cost 3 vsldoi8 <2,3,4,5>, <3,3,3,3> + 3235498492U, // <4,5,3,4>: Cost 3 vsldoi8 <2,3,4,5>, <3,4,5,0> + 3242797641U, // <4,5,3,5>: Cost 4 vsldoi8 <3,5,4,5>, <3,5,4,5> + 3262040756U, // <4,5,3,6>: Cost 3 vsldoi8 <6,7,4,5>, <3,6,7,4> + 3244124907U, // <4,5,3,7>: Cost 3 vsldoi8 <3,7,4,5>, <3,7,4,5> + 3235498782U, // <4,5,3,u>: Cost 3 vsldoi8 <2,3,4,5>, <3,u,1,2> + 4181721190U, // <4,5,4,0>: Cost 3 vsldoi4 <3,4,5,4>, LHS + 3516533650U, // <4,5,4,1>: Cost 3 vmrglw <4,4,4,4>, <4,0,5,1> + 3235499062U, // <4,5,4,2>: Cost 3 vsldoi8 <2,3,4,5>, <4,2,5,3> + 4181723648U, // <4,5,4,3>: Cost 3 vsldoi4 <3,4,5,4>, <3,4,5,4> + 3235499226U, // <4,5,4,4>: Cost 3 vsldoi8 <2,3,4,5>, <4,4,5,5> + 3235499318U, // <4,5,4,5>: Cost 2 vsldoi8 <2,3,4,5>, RHS + 3235499390U, // <4,5,4,6>: Cost 3 vsldoi8 <2,3,4,5>, <4,6,5,7> + 4205614436U, // <4,5,4,7>: Cost 3 vsldoi4 <7,4,5,4>, <7,4,5,4> + 3235499561U, // <4,5,4,u>: Cost 2 vsldoi8 <2,3,4,5>, RHS + 3113959526U, // <4,5,5,0>: Cost 2 vsldoi4 <4,4,5,5>, LHS + 3520523802U, // <4,5,5,1>: Cost 3 vmrglw <5,1,4,5>, <4,u,5,1> + 4187702990U, // <4,5,5,2>: Cost 3 vsldoi4 <4,4,5,5>, <2,3,4,5> + 3503934518U, // <4,5,5,3>: Cost 3 vmrglw <2,3,4,5>, <4,2,5,3> + 3113962714U, // <4,5,5,4>: Cost 2 vsldoi4 <4,4,5,5>, <4,4,5,5> + 2309419012U, // <4,5,5,5>: Cost 2 vmrghw RHS, <5,5,5,5> + 2309419106U, // <4,5,5,6>: Cost 2 vmrghw RHS, <5,6,7,0> + 3503934846U, // <4,5,5,7>: Cost 3 vmrglw <2,3,4,5>, <4,6,5,7> + 2309566724U, // <4,5,5,u>: Cost 2 vmrghw RHS, <5,u,7,0> + 3107995750U, // <4,5,6,0>: Cost 2 vsldoi4 <3,4,5,6>, LHS + 4169794640U, // <4,5,6,1>: Cost 3 vsldoi4 <1,4,5,6>, <1,4,5,6> + 4175767337U, // <4,5,6,2>: Cost 3 vsldoi4 <2,4,5,6>, <2,4,5,6> + 3107998210U, // <4,5,6,3>: Cost 2 vsldoi4 <3,4,5,6>, <3,4,5,6> + 3107999030U, // <4,5,6,4>: Cost 2 vsldoi4 <3,4,5,6>, RHS + 4181741336U, // <4,5,6,5>: Cost 3 vsldoi4 <3,4,5,6>, <5,2,6,3> + 4199658125U, // <4,5,6,6>: Cost 3 vsldoi4 <6,4,5,6>, <6,4,5,6> 27705344U, // <4,5,6,7>: Cost 0 copy RHS 27705344U, // <4,5,6,u>: Cost 0 copy RHS - 4201567226U, // <4,5,7,0>: Cost 3 vsldoi8 <6,7,4,5>, <7,0,1,2> - 3255619713U, // <4,5,7,1>: Cost 4 vsldoi12 <5,6,7,4>, <5,7,1,4> - 4175025328U, // <4,5,7,2>: Cost 3 vsldoi8 <2,3,4,5>, <7,2,3,4> - 4204885259U, // <4,5,7,3>: Cost 3 vsldoi8 <7,3,4,5>, <7,3,4,5> - 4201567584U, // <4,5,7,4>: Cost 3 vsldoi8 <6,7,4,5>, <7,4,5,0> - 3250130948U, // <4,5,7,5>: Cost 4 vmrghw <4,7,5,0>, <5,5,5,5> - 4201567768U, // <4,5,7,6>: Cost 3 vsldoi8 <6,7,4,5>, <7,6,7,4> - 4201567852U, // <4,5,7,7>: Cost 3 vsldoi8 <6,7,4,5>, <7,7,7,7> - 4201567874U, // <4,5,7,u>: Cost 3 vsldoi8 <6,7,4,5>, <7,u,1,2> - 2973794406U, // <4,5,u,0>: Cost 2 vsldoi4 <3,4,5,u>, LHS - 3101284142U, // <4,5,u,1>: Cost 2 vsldoi8 <2,3,4,5>, LHS - 4175026053U, // <4,5,u,2>: Cost 3 vsldoi8 <2,3,4,5>, - 2973796868U, // <4,5,u,3>: Cost 2 vsldoi4 <3,4,5,u>, <3,4,5,u> - 2973797686U, // <4,5,u,4>: Cost 2 vsldoi4 <3,4,5,u>, RHS - 3101284506U, // <4,5,u,5>: Cost 2 vsldoi8 <2,3,4,5>, RHS - 2177183842U, // <4,5,u,6>: Cost 2 vmrghw RHS, <5,6,7,0> + 3262043130U, // <4,5,7,0>: Cost 3 vsldoi8 <6,7,4,5>, <7,0,1,2> + 3389837441U, // <4,5,7,1>: Cost 4 vsldoi12 <5,6,7,4>, <5,7,1,4> + 3235501232U, // <4,5,7,2>: Cost 3 vsldoi8 <2,3,4,5>, <7,2,3,4> + 3265361163U, // <4,5,7,3>: Cost 3 vsldoi8 <7,3,4,5>, <7,3,4,5> + 3262043488U, // <4,5,7,4>: Cost 3 vsldoi8 <6,7,4,5>, <7,4,5,0> + 3384348676U, // <4,5,7,5>: Cost 4 vmrghw <4,7,5,0>, <5,5,5,5> + 3262043672U, // <4,5,7,6>: Cost 3 vsldoi8 <6,7,4,5>, <7,6,7,4> + 3262043756U, // <4,5,7,7>: Cost 3 vsldoi8 <6,7,4,5>, <7,7,7,7> + 3262043778U, // <4,5,7,u>: Cost 3 vsldoi8 <6,7,4,5>, <7,u,1,2> + 3108012134U, // <4,5,u,0>: Cost 2 vsldoi4 <3,4,5,u>, LHS + 3235501870U, // <4,5,u,1>: Cost 2 vsldoi8 <2,3,4,5>, LHS + 3235501957U, // <4,5,u,2>: Cost 3 vsldoi8 <2,3,4,5>, + 3108014596U, // <4,5,u,3>: Cost 2 vsldoi4 <3,4,5,u>, <3,4,5,u> + 3108015414U, // <4,5,u,4>: Cost 2 vsldoi4 <3,4,5,u>, RHS + 3235502234U, // <4,5,u,5>: Cost 2 vsldoi8 <2,3,4,5>, RHS + 2311401570U, // <4,5,u,6>: Cost 2 vmrghw RHS, <5,6,7,0> 27705344U, // <4,5,u,7>: Cost 0 copy RHS 27705344U, // <4,5,u,u>: Cost 0 copy RHS - 3245486421U, // <4,6,0,0>: Cost 4 vmrghw <4,0,5,0>, <6,0,7,0> - 4166402150U, // <4,6,0,1>: Cost 4 vsldoi8 <0,u,4,6>, LHS - 3245494778U, // <4,6,0,2>: Cost 3 vmrghw <4,0,5,1>, <6,2,7,3> - 4170383616U, // <4,6,0,3>: Cost 4 vsldoi8 <1,5,4,6>, <0,3,1,4> - 4166402386U, // <4,6,0,4>: Cost 4 vsldoi8 <0,u,4,6>, <0,4,1,5> - 3245495019U, // <4,6,0,5>: Cost 3 vmrghw <4,0,5,1>, <6,5,7,1> - 3245495096U, // <4,6,0,6>: Cost 3 vmrghw <4,0,5,1>, <6,6,6,6> - 3369676086U, // <4,6,0,7>: Cost 3 vmrglw <2,3,4,0>, RHS - 3369676087U, // <4,6,0,u>: Cost 3 vmrglw <2,3,4,0>, RHS - 3378973999U, // <4,6,1,0>: Cost 4 vmrglw <3,u,4,1>, <4,5,6,0> - 3378974648U, // <4,6,1,1>: Cost 4 vmrglw <3,u,4,1>, <5,4,6,1> - 4182328218U, // <4,6,1,2>: Cost 4 vsldoi8 <3,5,4,6>, <1,2,3,4> - 3378974002U, // <4,6,1,3>: Cost 4 vmrglw <3,u,4,1>, <4,5,6,3> - 3378974003U, // <4,6,1,4>: Cost 4 vmrglw <3,u,4,1>, <4,5,6,4> - 4170384536U, // <4,6,1,5>: Cost 4 vsldoi8 <1,5,4,6>, <1,5,4,6> - 3378974734U, // <4,6,1,6>: Cost 4 vmrglw <3,u,4,1>, <5,5,6,6> - 3361058102U, // <4,6,1,7>: Cost 3 vmrglw <0,u,4,1>, RHS - 3361058103U, // <4,6,1,u>: Cost 3 vmrglw <0,u,4,1>, RHS - 4071448678U, // <4,6,2,0>: Cost 4 vsldoi4 <7,4,6,2>, LHS - 4166403619U, // <4,6,2,1>: Cost 5 vsldoi8 <0,u,4,6>, <2,1,3,5> - 3246830073U, // <4,6,2,2>: Cost 4 vmrghw <4,2,5,2>, <6,2,7,2> - 4175029966U, // <4,6,2,3>: Cost 4 vsldoi8 <2,3,4,6>, <2,3,4,5> - 3248910815U, // <4,6,2,4>: Cost 4 vsldoi12 <4,5,6,4>, <6,2,4,3> - 4071452774U, // <4,6,2,5>: Cost 4 vsldoi4 <7,4,6,2>, <5,6,7,4> - 4204226490U, // <4,6,2,6>: Cost 4 vsldoi8 <7,2,4,6>, <2,6,3,7> - 3255620090U, // <4,6,2,7>: Cost 3 vsldoi12 <5,6,7,4>, <6,2,7,3> - 3255620099U, // <4,6,2,u>: Cost 3 vsldoi12 <5,6,7,4>, <6,2,u,3> - 3259085325U, // <4,6,3,0>: Cost 4 vsldoi12 <6,3,0,4>, <6,3,0,4> - 3247477160U, // <4,6,3,1>: Cost 4 vmrghw <4,3,5,0>, <6,1,7,2> - 3259232799U, // <4,6,3,2>: Cost 4 vsldoi12 <6,3,2,4>, <6,3,2,4> - 3259306536U, // <4,6,3,3>: Cost 4 vsldoi12 <6,3,3,4>, <6,3,3,4> - 4170385922U, // <4,6,3,4>: Cost 4 vsldoi8 <1,5,4,6>, <3,4,5,6> - 4182329930U, // <4,6,3,5>: Cost 4 vsldoi8 <3,5,4,6>, <3,5,4,6> - 3398898488U, // <4,6,3,6>: Cost 4 vmrglw <7,2,4,3>, <6,6,6,6> - 3375009078U, // <4,6,3,7>: Cost 3 vmrglw <3,2,4,3>, RHS - 3375009079U, // <4,6,3,u>: Cost 3 vmrglw <3,2,4,3>, RHS - 3248910939U, // <4,6,4,0>: Cost 4 vsldoi12 <4,5,6,4>, <6,4,0,1> - 3248099751U, // <4,6,4,1>: Cost 4 vmrghw <4,4,4,4>, <6,1,7,1> - 3248099834U, // <4,6,4,2>: Cost 3 vmrghw <4,4,4,4>, <6,2,7,3> - 3248910969U, // <4,6,4,3>: Cost 4 vsldoi12 <4,5,6,4>, <6,4,3,4> - 3248099997U, // <4,6,4,4>: Cost 3 vmrghw <4,4,4,4>, <6,4,7,4> - 3248181999U, // <4,6,4,5>: Cost 3 vmrghw <4,4,5,5>, <6,5,7,5> - 3248100152U, // <4,6,4,6>: Cost 3 vmrghw <4,4,4,4>, <6,6,6,6> - 2308574518U, // <4,6,4,7>: Cost 2 vmrglw <4,4,4,4>, RHS - 2308574519U, // <4,6,4,u>: Cost 2 vmrglw <4,4,4,4>, RHS - 3248935201U, // <4,6,5,0>: Cost 3 vmrghw RHS, <6,0,1,2> - 3248943527U, // <4,6,5,1>: Cost 3 vmrghw RHS, <6,1,7,1> - 2175201786U, // <4,6,5,2>: Cost 2 vmrghw RHS, <6,2,7,3> - 3248935474U, // <4,6,5,3>: Cost 3 vmrghw RHS, <6,3,4,5> - 3248935565U, // <4,6,5,4>: Cost 3 vmrghw RHS, <6,4,5,6> - 3248943851U, // <4,6,5,5>: Cost 3 vmrghw RHS, <6,5,7,1> - 2175202104U, // <4,6,5,6>: Cost 2 vmrghw RHS, <6,6,6,6> - 2295975222U, // <4,6,5,7>: Cost 2 vmrglw <2,3,4,5>, RHS - 2295975223U, // <4,6,5,u>: Cost 2 vmrglw <2,3,4,5>, RHS - 3249467681U, // <4,6,6,0>: Cost 4 vmrghw <4,6,5,0>, <6,0,1,2> - 3249476007U, // <4,6,6,1>: Cost 4 vmrghw <4,6,5,1>, <6,1,7,1> - 3249484282U, // <4,6,6,2>: Cost 3 vmrghw <4,6,5,2>, <6,2,7,3> - 3249492530U, // <4,6,6,3>: Cost 4 vmrghw <4,6,5,3>, <6,3,4,5> - 3248911140U, // <4,6,6,4>: Cost 4 vsldoi12 <4,5,6,4>, <6,6,4,4> - 3249509099U, // <4,6,6,5>: Cost 4 vmrghw <4,6,5,5>, <6,5,7,1> - 3249517368U, // <4,6,6,6>: Cost 3 vmrghw <4,6,5,6>, <6,6,6,6> - 3255620418U, // <4,6,6,7>: Cost 3 vsldoi12 <5,6,7,4>, <6,6,7,7> - 3255620427U, // <4,6,6,u>: Cost 3 vsldoi12 <5,6,7,4>, <6,6,u,7> - 3255620430U, // <4,6,7,0>: Cost 3 vsldoi12 <5,6,7,4>, <6,7,0,1> - 3255620439U, // <4,6,7,1>: Cost 4 vsldoi12 <5,6,7,4>, <6,7,1,1> - 3250131450U, // <4,6,7,2>: Cost 4 vmrghw <4,7,5,0>, <6,2,7,3> - 3261961068U, // <4,6,7,3>: Cost 3 vsldoi12 <6,7,3,4>, <6,7,3,4> - 3255620470U, // <4,6,7,4>: Cost 3 vsldoi12 <5,6,7,4>, <6,7,4,5> - 3252671356U, // <4,6,7,5>: Cost 4 vsldoi12 <5,2,3,4>, <6,7,5,2> - 3250131768U, // <4,6,7,6>: Cost 4 vmrghw <4,7,5,0>, <6,6,6,6> - 3377696054U, // <4,6,7,7>: Cost 3 vmrglw <3,6,4,7>, RHS - 3377696055U, // <4,6,7,u>: Cost 3 vmrglw <3,6,4,7>, RHS - 3250925857U, // <4,6,u,0>: Cost 3 vmrghw RHS, <6,0,1,2> - 3250925991U, // <4,6,u,1>: Cost 3 vmrghw RHS, <6,1,7,1> - 2177184250U, // <4,6,u,2>: Cost 2 vmrghw RHS, <6,2,7,3> - 3250926130U, // <4,6,u,3>: Cost 3 vmrghw RHS, <6,3,4,5> - 3250926221U, // <4,6,u,4>: Cost 3 vmrghw RHS, <6,4,5,6> - 3250926315U, // <4,6,u,5>: Cost 3 vmrghw RHS, <6,5,7,1> - 2177184568U, // <4,6,u,6>: Cost 2 vmrghw RHS, <6,6,6,6> - 2295999798U, // <4,6,u,7>: Cost 2 vmrglw <2,3,4,u>, RHS - 2295999799U, // <4,6,u,u>: Cost 2 vmrglw <2,3,4,u>, RHS - 3245495290U, // <4,7,0,0>: Cost 3 vmrghw <4,0,5,1>, <7,0,1,2> - 4182999142U, // <4,7,0,1>: Cost 3 vsldoi8 <3,6,4,7>, LHS - 3245495444U, // <4,7,0,2>: Cost 4 vmrghw <4,0,5,1>, <7,2,0,3> - 4171055360U, // <4,7,0,3>: Cost 4 vsldoi8 <1,6,4,7>, <0,3,1,4> - 3245495608U, // <4,7,0,4>: Cost 3 vmrghw <4,0,5,1>, <7,4,0,5> - 3255620642U, // <4,7,0,5>: Cost 4 vsldoi12 <5,6,7,4>, <7,0,5,6> - 4065538713U, // <4,7,0,6>: Cost 4 vsldoi4 <6,4,7,0>, <6,4,7,0> - 3245495916U, // <4,7,0,7>: Cost 3 vmrghw <4,0,5,1>, <7,7,7,7> - 4182999709U, // <4,7,0,u>: Cost 3 vsldoi8 <3,6,4,7>, LHS - 3385610338U, // <4,7,1,0>: Cost 4 vmrglw <5,0,4,1>, <5,6,7,0> - 4182999860U, // <4,7,1,1>: Cost 4 vsldoi8 <3,6,4,7>, <1,1,1,1> - 4182999962U, // <4,7,1,2>: Cost 3 vsldoi8 <3,6,4,7>, <1,2,3,4> - 3385610746U, // <4,7,1,3>: Cost 4 vmrglw <5,0,4,1>, <6,2,7,3> - 3385610342U, // <4,7,1,4>: Cost 4 vmrglw <5,0,4,1>, <5,6,7,4> - 3385610667U, // <4,7,1,5>: Cost 4 vmrglw <5,0,4,1>, <6,1,7,5> - 4171056362U, // <4,7,1,6>: Cost 4 vsldoi8 <1,6,4,7>, <1,6,4,7> - 3385611074U, // <4,7,1,7>: Cost 4 vmrglw <5,0,4,1>, <6,6,7,7> - 4182999962U, // <4,7,1,u>: Cost 3 vsldoi8 <3,6,4,7>, <1,2,3,4> - 3255620756U, // <4,7,2,0>: Cost 4 vsldoi12 <5,6,7,4>, <7,2,0,3> - 4047635354U, // <4,7,2,1>: Cost 5 vsldoi4 <3,4,7,2>, <1,2,3,4> - 4177028712U, // <4,7,2,2>: Cost 4 vsldoi8 <2,6,4,7>, <2,2,2,2> - 3264615600U, // <4,7,2,3>: Cost 3 vsldoi12 <7,2,3,4>, <7,2,3,4> - 3255620792U, // <4,7,2,4>: Cost 3 vsldoi12 <5,6,7,4>, <7,2,4,3> - 4071526502U, // <4,7,2,5>: Cost 4 vsldoi4 <7,4,7,2>, <5,6,7,4> - 4177029059U, // <4,7,2,6>: Cost 4 vsldoi8 <2,6,4,7>, <2,6,4,7> - 4071527796U, // <4,7,2,7>: Cost 4 vsldoi4 <7,4,7,2>, <7,4,7,2> - 3264984285U, // <4,7,2,u>: Cost 3 vsldoi12 <7,2,u,4>, <7,2,u,4> - 4183001238U, // <4,7,3,0>: Cost 4 vsldoi8 <3,6,4,7>, <3,0,1,2> - 4065559450U, // <4,7,3,1>: Cost 4 vsldoi4 <6,4,7,3>, <1,2,3,4> - 4183001428U, // <4,7,3,2>: Cost 4 vsldoi8 <3,6,4,7>, <3,2,4,3> - 4181010857U, // <4,7,3,3>: Cost 4 vsldoi8 <3,3,4,7>, <3,3,4,7> - 3398897766U, // <4,7,3,4>: Cost 3 vmrglw <7,2,4,3>, <5,6,7,4> - 4182338123U, // <4,7,3,5>: Cost 5 vsldoi8 <3,5,4,7>, <3,5,4,7> - 4183001756U, // <4,7,3,6>: Cost 3 vsldoi8 <3,6,4,7>, <3,6,4,7> - 3398898498U, // <4,7,3,7>: Cost 4 vmrglw <7,2,4,3>, <6,6,7,7> - 4184329022U, // <4,7,3,u>: Cost 3 vsldoi8 <3,u,4,7>, <3,u,4,7> - 3255620916U, // <4,7,4,0>: Cost 3 vsldoi12 <5,6,7,4>, <7,4,0,1> - 4183002058U, // <4,7,4,1>: Cost 4 vsldoi8 <3,6,4,7>, <4,1,2,3> - 4183002184U, // <4,7,4,2>: Cost 4 vsldoi8 <3,6,4,7>, <4,2,7,3> - 3382317562U, // <4,7,4,3>: Cost 3 vmrglw <4,4,4,4>, <6,2,7,3> - 4065570000U, // <4,7,4,4>: Cost 3 vsldoi4 <6,4,7,4>, <4,4,4,4> - 4183002422U, // <4,7,4,5>: Cost 3 vsldoi8 <3,6,4,7>, RHS - 4065571485U, // <4,7,4,6>: Cost 3 vsldoi4 <6,4,7,4>, <6,4,7,4> - 3248100972U, // <4,7,4,7>: Cost 3 vmrghw <4,4,4,4>, <7,7,7,7> - 4183002665U, // <4,7,4,u>: Cost 3 vsldoi8 <3,6,4,7>, RHS - 2175202298U, // <4,7,5,0>: Cost 2 vmrghw RHS, <7,0,1,2> - 3248944202U, // <4,7,5,1>: Cost 3 vmrghw RHS, <7,1,1,1> - 3248936138U, // <4,7,5,2>: Cost 3 vmrghw RHS, <7,2,6,3> - 3248944355U, // <4,7,5,3>: Cost 3 vmrghw RHS, <7,3,0,1> - 2175202662U, // <4,7,5,4>: Cost 2 vmrghw RHS, <7,4,5,6> - 3248944566U, // <4,7,5,5>: Cost 3 vmrghw RHS, <7,5,5,5> - 3248944622U, // <4,7,5,6>: Cost 3 vmrghw RHS, <7,6,2,7> - 2175202924U, // <4,7,5,7>: Cost 2 vmrghw RHS, <7,7,7,7> - 2175202946U, // <4,7,5,u>: Cost 2 vmrghw RHS, <7,u,1,2> - 3249484794U, // <4,7,6,0>: Cost 4 vmrghw <4,6,5,2>, <7,0,1,2> - 3249484874U, // <4,7,6,1>: Cost 5 vmrghw <4,6,5,2>, <7,1,1,1> - 3249525936U, // <4,7,6,2>: Cost 4 vmrghw <4,6,5,7>, <7,2,3,4> - 3386978810U, // <4,7,6,3>: Cost 4 vmrglw <5,2,4,6>, <6,2,7,3> - 3255621120U, // <4,7,6,4>: Cost 3 vsldoi12 <5,6,7,4>, <7,6,4,7> - 4071559270U, // <4,7,6,5>: Cost 4 vsldoi4 <7,4,7,6>, <5,6,7,4> - 3249485294U, // <4,7,6,6>: Cost 4 vmrghw <4,6,5,2>, <7,6,2,7> - 3267565080U, // <4,7,6,7>: Cost 3 vsldoi12 <7,6,7,4>, <7,6,7,4> - 3267638817U, // <4,7,6,u>: Cost 3 vsldoi12 <7,6,u,4>, <7,6,u,4> - 3250131962U, // <4,7,7,0>: Cost 3 vmrghw <4,7,5,0>, <7,0,1,2> - 4053648282U, // <4,7,7,1>: Cost 4 vsldoi4 <4,4,7,7>, <1,2,3,4> - 3250148554U, // <4,7,7,2>: Cost 4 vmrghw <4,7,5,2>, <7,2,6,3> - 3377695816U, // <4,7,7,3>: Cost 4 vmrglw <3,6,4,7>, <4,2,7,3> - 3250165094U, // <4,7,7,4>: Cost 3 vmrghw <4,7,5,4>, <7,4,5,6> - 3250173366U, // <4,7,7,5>: Cost 4 vmrghw <4,7,5,5>, <7,5,5,5> - 4206892544U, // <4,7,7,6>: Cost 3 vsldoi8 <7,6,4,7>, <7,6,4,7> - 3250189932U, // <4,7,7,7>: Cost 3 vmrghw <4,7,5,7>, <7,7,7,7> - 3250198146U, // <4,7,7,u>: Cost 3 vmrghw <4,7,5,u>, <7,u,1,2> - 2177184762U, // <4,7,u,0>: Cost 2 vmrghw RHS, <7,0,1,2> - 4183004974U, // <4,7,u,1>: Cost 3 vsldoi8 <3,6,4,7>, LHS - 3250926757U, // <4,7,u,2>: Cost 3 vmrghw RHS, <7,2,2,2> - 3250926819U, // <4,7,u,3>: Cost 3 vmrghw RHS, <7,3,0,1> - 2177185126U, // <4,7,u,4>: Cost 2 vmrghw RHS, <7,4,5,6> - 4183005338U, // <4,7,u,5>: Cost 3 vsldoi8 <3,6,4,7>, RHS - 3250927086U, // <4,7,u,6>: Cost 3 vmrghw RHS, <7,6,2,7> - 2177185388U, // <4,7,u,7>: Cost 2 vmrghw RHS, <7,7,7,7> - 2177185410U, // <4,7,u,u>: Cost 2 vmrghw RHS, <7,u,1,2> - 2171751314U, // <4,u,0,0>: Cost 2 vmrghw <4,0,5,1>, <4,0,5,1> - 3101302886U, // <4,u,0,1>: Cost 2 vsldoi8 <2,3,4,u>, LHS - 4047693521U, // <4,u,0,2>: Cost 3 vsldoi4 <3,4,u,0>, <2,3,4,u> - 3369672860U, // <4,u,0,3>: Cost 3 vmrglw <2,3,4,0>, LHS - 4163764592U, // <4,u,0,4>: Cost 3 vsldoi8 <0,4,4,u>, <0,4,4,u> - 2171754650U, // <4,u,0,5>: Cost 2 vmrghw <4,0,5,1>, RHS - 4071584633U, // <4,u,0,6>: Cost 3 vsldoi4 <7,4,u,0>, <6,7,4,u> - 3369676104U, // <4,u,0,7>: Cost 3 vmrglw <2,3,4,0>, RHS - 3101303453U, // <4,u,0,u>: Cost 2 vsldoi8 <2,3,4,u>, LHS - 4047700070U, // <4,u,1,0>: Cost 3 vsldoi4 <3,4,u,1>, LHS - 4167746390U, // <4,u,1,1>: Cost 3 vsldoi8 <1,1,4,u>, <1,1,4,u> - 3228784430U, // <4,u,1,2>: Cost 2 vsldoi12 <1,2,3,4>, LHS - 3361054876U, // <4,u,1,3>: Cost 3 vmrglw <0,u,4,1>, LHS - 3372999623U, // <4,u,1,4>: Cost 3 vmrglw <2,u,4,1>, <1,2,u,4> - 4170400922U, // <4,u,1,5>: Cost 3 vsldoi8 <1,5,4,u>, <1,5,4,u> - 3378973186U, // <4,u,1,6>: Cost 3 vmrglw <3,u,4,1>, <3,4,5,6> - 3361058120U, // <4,u,1,7>: Cost 3 vmrglw <0,u,4,1>, RHS - 3228784484U, // <4,u,1,u>: Cost 2 vsldoi12 <1,2,3,4>, LHS - 4047708262U, // <4,u,2,0>: Cost 3 vsldoi4 <3,4,u,2>, LHS - 3246839598U, // <4,u,2,1>: Cost 3 vmrghw <4,2,5,3>, LHS - 4174382720U, // <4,u,2,2>: Cost 3 vsldoi8 <2,2,4,u>, <2,2,4,u> - 3101304529U, // <4,u,2,3>: Cost 2 vsldoi8 <2,3,4,u>, <2,3,4,u> - 3229153169U, // <4,u,2,4>: Cost 3 vsldoi12 <1,2,u,4>, - 3246839962U, // <4,u,2,5>: Cost 3 vmrghw <4,2,5,3>, RHS - 4175046586U, // <4,u,2,6>: Cost 3 vsldoi8 <2,3,4,u>, <2,6,3,7> - 3255621548U, // <4,u,2,7>: Cost 3 vsldoi12 <5,6,7,4>, - 3104622694U, // <4,u,2,u>: Cost 2 vsldoi8 <2,u,4,u>, <2,u,4,u> - 3228784572U, // <4,u,3,0>: Cost 3 vsldoi12 <1,2,3,4>, - 3271104456U, // <4,u,3,1>: Cost 3 vsldoi12 , - 4180355417U, // <4,u,3,2>: Cost 3 vsldoi8 <3,2,4,u>, <3,2,4,u> - 3228784602U, // <4,u,3,3>: Cost 3 vsldoi12 <1,2,3,4>, - 3228784612U, // <4,u,3,4>: Cost 3 vsldoi12 <1,2,3,4>, - 3247478938U, // <4,u,3,5>: Cost 3 vmrghw <4,3,5,0>, RHS - 4183009949U, // <4,u,3,6>: Cost 3 vsldoi8 <3,6,4,u>, <3,6,4,u> - 3375009096U, // <4,u,3,7>: Cost 3 vmrglw <3,2,4,3>, RHS - 3228784644U, // <4,u,3,u>: Cost 3 vsldoi12 <1,2,3,4>, - 2979954790U, // <4,u,4,0>: Cost 2 vsldoi4 <4,4,u,4>, LHS - 2174359342U, // <4,u,4,1>: Cost 2 vmrghw <4,4,4,4>, LHS - 4175047761U, // <4,u,4,2>: Cost 3 vsldoi8 <2,3,4,u>, <4,2,u,3> - 2308571292U, // <4,u,4,3>: Cost 2 vmrglw <4,4,4,4>, LHS - 1369886006U, // <4,u,4,4>: Cost 1 vspltisw0 RHS - 3101306166U, // <4,u,4,5>: Cost 2 vsldoi8 <2,3,4,u>, RHS - 4175048089U, // <4,u,4,6>: Cost 3 vsldoi8 <2,3,4,u>, <4,6,u,7> - 2308574536U, // <4,u,4,7>: Cost 2 vmrglw <4,4,4,4>, RHS - 1369886006U, // <4,u,4,u>: Cost 1 vspltisw0 RHS - 2175194835U, // <4,u,5,0>: Cost 2 vmrghw RHS, - 1101453102U, // <4,u,5,1>: Cost 1 vmrghw RHS, LHS - 2175195013U, // <4,u,5,2>: Cost 2 vmrghw RHS, - 2295971996U, // <4,u,5,3>: Cost 2 vmrglw <2,3,4,5>, LHS - 2175195199U, // <4,u,5,4>: Cost 2 vmrghw RHS, - 1101453466U, // <4,u,5,5>: Cost 1 vmrghw RHS, RHS - 3228784794U, // <4,u,5,6>: Cost 2 vsldoi12 <1,2,3,4>, RHS - 2295975240U, // <4,u,5,7>: Cost 2 vmrglw <2,3,4,5>, RHS - 1101453669U, // <4,u,5,u>: Cost 1 vmrghw RHS, LHS - 2973999206U, // <4,u,6,0>: Cost 2 vsldoi4 <3,4,u,6>, LHS - 4035798123U, // <4,u,6,1>: Cost 3 vsldoi4 <1,4,u,6>, <1,4,u,6> - 4041770820U, // <4,u,6,2>: Cost 3 vsldoi4 <2,4,u,6>, <2,4,u,6> - 2974001693U, // <4,u,6,3>: Cost 2 vsldoi4 <3,4,u,6>, <3,4,u,6> - 2974002486U, // <4,u,6,4>: Cost 2 vsldoi4 <3,4,u,6>, RHS - 3249485978U, // <4,u,6,5>: Cost 3 vmrghw <4,6,5,2>, RHS - 4065661608U, // <4,u,6,6>: Cost 3 vsldoi4 <6,4,u,6>, <6,4,u,6> + 3379704149U, // <4,6,0,0>: Cost 4 vmrghw <4,0,5,0>, <6,0,7,0> + 3226878054U, // <4,6,0,1>: Cost 4 vsldoi8 <0,u,4,6>, LHS + 3379712506U, // <4,6,0,2>: Cost 3 vmrghw <4,0,5,1>, <6,2,7,3> + 3230859520U, // <4,6,0,3>: Cost 4 vsldoi8 <1,5,4,6>, <0,3,1,4> + 3226878290U, // <4,6,0,4>: Cost 4 vsldoi8 <0,u,4,6>, <0,4,1,5> + 3379712747U, // <4,6,0,5>: Cost 3 vmrghw <4,0,5,1>, <6,5,7,1> + 3379712824U, // <4,6,0,6>: Cost 3 vmrghw <4,0,5,1>, <6,6,6,6> + 3503893814U, // <4,6,0,7>: Cost 3 vmrglw <2,3,4,0>, RHS + 3503893815U, // <4,6,0,u>: Cost 3 vmrglw <2,3,4,0>, RHS + 3513191727U, // <4,6,1,0>: Cost 4 vmrglw <3,u,4,1>, <4,5,6,0> + 3513192376U, // <4,6,1,1>: Cost 4 vmrglw <3,u,4,1>, <5,4,6,1> + 3242804122U, // <4,6,1,2>: Cost 4 vsldoi8 <3,5,4,6>, <1,2,3,4> + 3513191730U, // <4,6,1,3>: Cost 4 vmrglw <3,u,4,1>, <4,5,6,3> + 3513191731U, // <4,6,1,4>: Cost 4 vmrglw <3,u,4,1>, <4,5,6,4> + 3230860440U, // <4,6,1,5>: Cost 4 vsldoi8 <1,5,4,6>, <1,5,4,6> + 3513192462U, // <4,6,1,6>: Cost 4 vmrglw <3,u,4,1>, <5,5,6,6> + 3495275830U, // <4,6,1,7>: Cost 3 vmrglw <0,u,4,1>, RHS + 3495275831U, // <4,6,1,u>: Cost 3 vmrglw <0,u,4,1>, RHS + 4205666406U, // <4,6,2,0>: Cost 4 vsldoi4 <7,4,6,2>, LHS + 3226879523U, // <4,6,2,1>: Cost 5 vsldoi8 <0,u,4,6>, <2,1,3,5> + 3381047801U, // <4,6,2,2>: Cost 4 vmrghw <4,2,5,2>, <6,2,7,2> + 3235505870U, // <4,6,2,3>: Cost 4 vsldoi8 <2,3,4,6>, <2,3,4,5> + 3383128543U, // <4,6,2,4>: Cost 4 vsldoi12 <4,5,6,4>, <6,2,4,3> + 4205670502U, // <4,6,2,5>: Cost 4 vsldoi4 <7,4,6,2>, <5,6,7,4> + 3264702394U, // <4,6,2,6>: Cost 4 vsldoi8 <7,2,4,6>, <2,6,3,7> + 3389837818U, // <4,6,2,7>: Cost 3 vsldoi12 <5,6,7,4>, <6,2,7,3> + 3389837827U, // <4,6,2,u>: Cost 3 vsldoi12 <5,6,7,4>, <6,2,u,3> + 3393303053U, // <4,6,3,0>: Cost 4 vsldoi12 <6,3,0,4>, <6,3,0,4> + 3381694888U, // <4,6,3,1>: Cost 4 vmrghw <4,3,5,0>, <6,1,7,2> + 3393450527U, // <4,6,3,2>: Cost 4 vsldoi12 <6,3,2,4>, <6,3,2,4> + 3393524264U, // <4,6,3,3>: Cost 4 vsldoi12 <6,3,3,4>, <6,3,3,4> + 3230861826U, // <4,6,3,4>: Cost 4 vsldoi8 <1,5,4,6>, <3,4,5,6> + 3242805834U, // <4,6,3,5>: Cost 4 vsldoi8 <3,5,4,6>, <3,5,4,6> + 3533116216U, // <4,6,3,6>: Cost 4 vmrglw <7,2,4,3>, <6,6,6,6> + 3509226806U, // <4,6,3,7>: Cost 3 vmrglw <3,2,4,3>, RHS + 3509226807U, // <4,6,3,u>: Cost 3 vmrglw <3,2,4,3>, RHS + 3383128667U, // <4,6,4,0>: Cost 4 vsldoi12 <4,5,6,4>, <6,4,0,1> + 3382317479U, // <4,6,4,1>: Cost 4 vmrghw <4,4,4,4>, <6,1,7,1> + 3382317562U, // <4,6,4,2>: Cost 3 vmrghw <4,4,4,4>, <6,2,7,3> + 3383128697U, // <4,6,4,3>: Cost 4 vsldoi12 <4,5,6,4>, <6,4,3,4> + 3382317725U, // <4,6,4,4>: Cost 3 vmrghw <4,4,4,4>, <6,4,7,4> + 3382399727U, // <4,6,4,5>: Cost 3 vmrghw <4,4,5,5>, <6,5,7,5> + 3382317880U, // <4,6,4,6>: Cost 3 vmrghw <4,4,4,4>, <6,6,6,6> + 2442792246U, // <4,6,4,7>: Cost 2 vmrglw <4,4,4,4>, RHS + 2442792247U, // <4,6,4,u>: Cost 2 vmrglw <4,4,4,4>, RHS + 3383152929U, // <4,6,5,0>: Cost 3 vmrghw RHS, <6,0,1,2> + 3383161255U, // <4,6,5,1>: Cost 3 vmrghw RHS, <6,1,7,1> + 2309419514U, // <4,6,5,2>: Cost 2 vmrghw RHS, <6,2,7,3> + 3383153202U, // <4,6,5,3>: Cost 3 vmrghw RHS, <6,3,4,5> + 3383153293U, // <4,6,5,4>: Cost 3 vmrghw RHS, <6,4,5,6> + 3383161579U, // <4,6,5,5>: Cost 3 vmrghw RHS, <6,5,7,1> + 2309419832U, // <4,6,5,6>: Cost 2 vmrghw RHS, <6,6,6,6> + 2430192950U, // <4,6,5,7>: Cost 2 vmrglw <2,3,4,5>, RHS + 2430192951U, // <4,6,5,u>: Cost 2 vmrglw <2,3,4,5>, RHS + 3383685409U, // <4,6,6,0>: Cost 4 vmrghw <4,6,5,0>, <6,0,1,2> + 3383693735U, // <4,6,6,1>: Cost 4 vmrghw <4,6,5,1>, <6,1,7,1> + 3383702010U, // <4,6,6,2>: Cost 3 vmrghw <4,6,5,2>, <6,2,7,3> + 3383710258U, // <4,6,6,3>: Cost 4 vmrghw <4,6,5,3>, <6,3,4,5> + 3383128868U, // <4,6,6,4>: Cost 4 vsldoi12 <4,5,6,4>, <6,6,4,4> + 3383726827U, // <4,6,6,5>: Cost 4 vmrghw <4,6,5,5>, <6,5,7,1> + 3383735096U, // <4,6,6,6>: Cost 3 vmrghw <4,6,5,6>, <6,6,6,6> + 3389838146U, // <4,6,6,7>: Cost 3 vsldoi12 <5,6,7,4>, <6,6,7,7> + 3389838155U, // <4,6,6,u>: Cost 3 vsldoi12 <5,6,7,4>, <6,6,u,7> + 3389838158U, // <4,6,7,0>: Cost 3 vsldoi12 <5,6,7,4>, <6,7,0,1> + 3389838167U, // <4,6,7,1>: Cost 4 vsldoi12 <5,6,7,4>, <6,7,1,1> + 3384349178U, // <4,6,7,2>: Cost 4 vmrghw <4,7,5,0>, <6,2,7,3> + 3396178796U, // <4,6,7,3>: Cost 3 vsldoi12 <6,7,3,4>, <6,7,3,4> + 3389838198U, // <4,6,7,4>: Cost 3 vsldoi12 <5,6,7,4>, <6,7,4,5> + 3386889084U, // <4,6,7,5>: Cost 4 vsldoi12 <5,2,3,4>, <6,7,5,2> + 3384349496U, // <4,6,7,6>: Cost 4 vmrghw <4,7,5,0>, <6,6,6,6> + 3511913782U, // <4,6,7,7>: Cost 3 vmrglw <3,6,4,7>, RHS + 3511913783U, // <4,6,7,u>: Cost 3 vmrglw <3,6,4,7>, RHS + 3385143585U, // <4,6,u,0>: Cost 3 vmrghw RHS, <6,0,1,2> + 3385143719U, // <4,6,u,1>: Cost 3 vmrghw RHS, <6,1,7,1> + 2311401978U, // <4,6,u,2>: Cost 2 vmrghw RHS, <6,2,7,3> + 3385143858U, // <4,6,u,3>: Cost 3 vmrghw RHS, <6,3,4,5> + 3385143949U, // <4,6,u,4>: Cost 3 vmrghw RHS, <6,4,5,6> + 3385144043U, // <4,6,u,5>: Cost 3 vmrghw RHS, <6,5,7,1> + 2311402296U, // <4,6,u,6>: Cost 2 vmrghw RHS, <6,6,6,6> + 2430217526U, // <4,6,u,7>: Cost 2 vmrglw <2,3,4,u>, RHS + 2430217527U, // <4,6,u,u>: Cost 2 vmrglw <2,3,4,u>, RHS + 3379713018U, // <4,7,0,0>: Cost 3 vmrghw <4,0,5,1>, <7,0,1,2> + 3243475046U, // <4,7,0,1>: Cost 3 vsldoi8 <3,6,4,7>, LHS + 3379713172U, // <4,7,0,2>: Cost 4 vmrghw <4,0,5,1>, <7,2,0,3> + 3231531264U, // <4,7,0,3>: Cost 4 vsldoi8 <1,6,4,7>, <0,3,1,4> + 3379713336U, // <4,7,0,4>: Cost 3 vmrghw <4,0,5,1>, <7,4,0,5> + 3389838370U, // <4,7,0,5>: Cost 4 vsldoi12 <5,6,7,4>, <7,0,5,6> + 4199756441U, // <4,7,0,6>: Cost 4 vsldoi4 <6,4,7,0>, <6,4,7,0> + 3379713644U, // <4,7,0,7>: Cost 3 vmrghw <4,0,5,1>, <7,7,7,7> + 3243475613U, // <4,7,0,u>: Cost 3 vsldoi8 <3,6,4,7>, LHS + 3519828066U, // <4,7,1,0>: Cost 4 vmrglw <5,0,4,1>, <5,6,7,0> + 3243475764U, // <4,7,1,1>: Cost 4 vsldoi8 <3,6,4,7>, <1,1,1,1> + 3243475866U, // <4,7,1,2>: Cost 3 vsldoi8 <3,6,4,7>, <1,2,3,4> + 3519828474U, // <4,7,1,3>: Cost 4 vmrglw <5,0,4,1>, <6,2,7,3> + 3519828070U, // <4,7,1,4>: Cost 4 vmrglw <5,0,4,1>, <5,6,7,4> + 3519828395U, // <4,7,1,5>: Cost 4 vmrglw <5,0,4,1>, <6,1,7,5> + 3231532266U, // <4,7,1,6>: Cost 4 vsldoi8 <1,6,4,7>, <1,6,4,7> + 3519828802U, // <4,7,1,7>: Cost 4 vmrglw <5,0,4,1>, <6,6,7,7> + 3243475866U, // <4,7,1,u>: Cost 3 vsldoi8 <3,6,4,7>, <1,2,3,4> + 3389838484U, // <4,7,2,0>: Cost 4 vsldoi12 <5,6,7,4>, <7,2,0,3> + 4181853082U, // <4,7,2,1>: Cost 5 vsldoi4 <3,4,7,2>, <1,2,3,4> + 3237504616U, // <4,7,2,2>: Cost 4 vsldoi8 <2,6,4,7>, <2,2,2,2> + 3398833328U, // <4,7,2,3>: Cost 3 vsldoi12 <7,2,3,4>, <7,2,3,4> + 3389838520U, // <4,7,2,4>: Cost 3 vsldoi12 <5,6,7,4>, <7,2,4,3> + 4205744230U, // <4,7,2,5>: Cost 4 vsldoi4 <7,4,7,2>, <5,6,7,4> + 3237504963U, // <4,7,2,6>: Cost 4 vsldoi8 <2,6,4,7>, <2,6,4,7> + 4205745524U, // <4,7,2,7>: Cost 4 vsldoi4 <7,4,7,2>, <7,4,7,2> + 3399202013U, // <4,7,2,u>: Cost 3 vsldoi12 <7,2,u,4>, <7,2,u,4> + 3243477142U, // <4,7,3,0>: Cost 4 vsldoi8 <3,6,4,7>, <3,0,1,2> + 4199777178U, // <4,7,3,1>: Cost 4 vsldoi4 <6,4,7,3>, <1,2,3,4> + 3243477332U, // <4,7,3,2>: Cost 4 vsldoi8 <3,6,4,7>, <3,2,4,3> + 3241486761U, // <4,7,3,3>: Cost 4 vsldoi8 <3,3,4,7>, <3,3,4,7> + 3533115494U, // <4,7,3,4>: Cost 3 vmrglw <7,2,4,3>, <5,6,7,4> + 3242814027U, // <4,7,3,5>: Cost 5 vsldoi8 <3,5,4,7>, <3,5,4,7> + 3243477660U, // <4,7,3,6>: Cost 3 vsldoi8 <3,6,4,7>, <3,6,4,7> + 3533116226U, // <4,7,3,7>: Cost 4 vmrglw <7,2,4,3>, <6,6,7,7> + 3244804926U, // <4,7,3,u>: Cost 3 vsldoi8 <3,u,4,7>, <3,u,4,7> + 3389838644U, // <4,7,4,0>: Cost 3 vsldoi12 <5,6,7,4>, <7,4,0,1> + 3243477962U, // <4,7,4,1>: Cost 4 vsldoi8 <3,6,4,7>, <4,1,2,3> + 3243478088U, // <4,7,4,2>: Cost 4 vsldoi8 <3,6,4,7>, <4,2,7,3> + 3516535290U, // <4,7,4,3>: Cost 3 vmrglw <4,4,4,4>, <6,2,7,3> + 4199787728U, // <4,7,4,4>: Cost 3 vsldoi4 <6,4,7,4>, <4,4,4,4> + 3243478326U, // <4,7,4,5>: Cost 3 vsldoi8 <3,6,4,7>, RHS + 4199789213U, // <4,7,4,6>: Cost 3 vsldoi4 <6,4,7,4>, <6,4,7,4> + 3382318700U, // <4,7,4,7>: Cost 3 vmrghw <4,4,4,4>, <7,7,7,7> + 3243478569U, // <4,7,4,u>: Cost 3 vsldoi8 <3,6,4,7>, RHS + 2309420026U, // <4,7,5,0>: Cost 2 vmrghw RHS, <7,0,1,2> + 3383161930U, // <4,7,5,1>: Cost 3 vmrghw RHS, <7,1,1,1> + 3383153866U, // <4,7,5,2>: Cost 3 vmrghw RHS, <7,2,6,3> + 3383162083U, // <4,7,5,3>: Cost 3 vmrghw RHS, <7,3,0,1> + 2309420390U, // <4,7,5,4>: Cost 2 vmrghw RHS, <7,4,5,6> + 3383162294U, // <4,7,5,5>: Cost 3 vmrghw RHS, <7,5,5,5> + 3383162350U, // <4,7,5,6>: Cost 3 vmrghw RHS, <7,6,2,7> + 2309420652U, // <4,7,5,7>: Cost 2 vmrghw RHS, <7,7,7,7> + 2309420674U, // <4,7,5,u>: Cost 2 vmrghw RHS, <7,u,1,2> + 3383702522U, // <4,7,6,0>: Cost 4 vmrghw <4,6,5,2>, <7,0,1,2> + 3383702602U, // <4,7,6,1>: Cost 5 vmrghw <4,6,5,2>, <7,1,1,1> + 3383743664U, // <4,7,6,2>: Cost 4 vmrghw <4,6,5,7>, <7,2,3,4> + 3521196538U, // <4,7,6,3>: Cost 4 vmrglw <5,2,4,6>, <6,2,7,3> + 3389838848U, // <4,7,6,4>: Cost 3 vsldoi12 <5,6,7,4>, <7,6,4,7> + 4205776998U, // <4,7,6,5>: Cost 4 vsldoi4 <7,4,7,6>, <5,6,7,4> + 3383703022U, // <4,7,6,6>: Cost 4 vmrghw <4,6,5,2>, <7,6,2,7> + 3401782808U, // <4,7,6,7>: Cost 3 vsldoi12 <7,6,7,4>, <7,6,7,4> + 3401856545U, // <4,7,6,u>: Cost 3 vsldoi12 <7,6,u,4>, <7,6,u,4> + 3384349690U, // <4,7,7,0>: Cost 3 vmrghw <4,7,5,0>, <7,0,1,2> + 4187866010U, // <4,7,7,1>: Cost 4 vsldoi4 <4,4,7,7>, <1,2,3,4> + 3384366282U, // <4,7,7,2>: Cost 4 vmrghw <4,7,5,2>, <7,2,6,3> + 3511913544U, // <4,7,7,3>: Cost 4 vmrglw <3,6,4,7>, <4,2,7,3> + 3384382822U, // <4,7,7,4>: Cost 3 vmrghw <4,7,5,4>, <7,4,5,6> + 3384391094U, // <4,7,7,5>: Cost 4 vmrghw <4,7,5,5>, <7,5,5,5> + 3267368448U, // <4,7,7,6>: Cost 3 vsldoi8 <7,6,4,7>, <7,6,4,7> + 3384407660U, // <4,7,7,7>: Cost 3 vmrghw <4,7,5,7>, <7,7,7,7> + 3384415874U, // <4,7,7,u>: Cost 3 vmrghw <4,7,5,u>, <7,u,1,2> + 2311402490U, // <4,7,u,0>: Cost 2 vmrghw RHS, <7,0,1,2> + 3243480878U, // <4,7,u,1>: Cost 3 vsldoi8 <3,6,4,7>, LHS + 3385144485U, // <4,7,u,2>: Cost 3 vmrghw RHS, <7,2,2,2> + 3385144547U, // <4,7,u,3>: Cost 3 vmrghw RHS, <7,3,0,1> + 2311402854U, // <4,7,u,4>: Cost 2 vmrghw RHS, <7,4,5,6> + 3243481242U, // <4,7,u,5>: Cost 3 vsldoi8 <3,6,4,7>, RHS + 3385144814U, // <4,7,u,6>: Cost 3 vmrghw RHS, <7,6,2,7> + 2311403116U, // <4,7,u,7>: Cost 2 vmrghw RHS, <7,7,7,7> + 2311403138U, // <4,7,u,u>: Cost 2 vmrghw RHS, <7,u,1,2> + 2305969042U, // <4,u,0,0>: Cost 2 vmrghw <4,0,5,1>, <4,0,5,1> + 3235520614U, // <4,u,0,1>: Cost 2 vsldoi8 <2,3,4,u>, LHS + 4181911249U, // <4,u,0,2>: Cost 3 vsldoi4 <3,4,u,0>, <2,3,4,u> + 3503890588U, // <4,u,0,3>: Cost 3 vmrglw <2,3,4,0>, LHS + 3224240496U, // <4,u,0,4>: Cost 3 vsldoi8 <0,4,4,u>, <0,4,4,u> + 2305972378U, // <4,u,0,5>: Cost 2 vmrghw <4,0,5,1>, RHS + 4205802361U, // <4,u,0,6>: Cost 3 vsldoi4 <7,4,u,0>, <6,7,4,u> + 3503893832U, // <4,u,0,7>: Cost 3 vmrglw <2,3,4,0>, RHS + 3235521181U, // <4,u,0,u>: Cost 2 vsldoi8 <2,3,4,u>, LHS + 4181917798U, // <4,u,1,0>: Cost 3 vsldoi4 <3,4,u,1>, LHS + 3228222294U, // <4,u,1,1>: Cost 3 vsldoi8 <1,1,4,u>, <1,1,4,u> + 3363002158U, // <4,u,1,2>: Cost 2 vsldoi12 <1,2,3,4>, LHS + 3495272604U, // <4,u,1,3>: Cost 3 vmrglw <0,u,4,1>, LHS + 3507217351U, // <4,u,1,4>: Cost 3 vmrglw <2,u,4,1>, <1,2,u,4> + 3230876826U, // <4,u,1,5>: Cost 3 vsldoi8 <1,5,4,u>, <1,5,4,u> + 3513190914U, // <4,u,1,6>: Cost 3 vmrglw <3,u,4,1>, <3,4,5,6> + 3495275848U, // <4,u,1,7>: Cost 3 vmrglw <0,u,4,1>, RHS + 3363002212U, // <4,u,1,u>: Cost 2 vsldoi12 <1,2,3,4>, LHS + 4181925990U, // <4,u,2,0>: Cost 3 vsldoi4 <3,4,u,2>, LHS + 3381057326U, // <4,u,2,1>: Cost 3 vmrghw <4,2,5,3>, LHS + 3234858624U, // <4,u,2,2>: Cost 3 vsldoi8 <2,2,4,u>, <2,2,4,u> + 3235522257U, // <4,u,2,3>: Cost 2 vsldoi8 <2,3,4,u>, <2,3,4,u> + 3363370897U, // <4,u,2,4>: Cost 3 vsldoi12 <1,2,u,4>, + 3381057690U, // <4,u,2,5>: Cost 3 vmrghw <4,2,5,3>, RHS + 3235522490U, // <4,u,2,6>: Cost 3 vsldoi8 <2,3,4,u>, <2,6,3,7> + 3389839276U, // <4,u,2,7>: Cost 3 vsldoi12 <5,6,7,4>, + 3238840422U, // <4,u,2,u>: Cost 2 vsldoi8 <2,u,4,u>, <2,u,4,u> + 3363002300U, // <4,u,3,0>: Cost 3 vsldoi12 <1,2,3,4>, + 3405322184U, // <4,u,3,1>: Cost 3 vsldoi12 , + 3240831321U, // <4,u,3,2>: Cost 3 vsldoi8 <3,2,4,u>, <3,2,4,u> + 3363002330U, // <4,u,3,3>: Cost 3 vsldoi12 <1,2,3,4>, + 3363002340U, // <4,u,3,4>: Cost 3 vsldoi12 <1,2,3,4>, + 3381696666U, // <4,u,3,5>: Cost 3 vmrghw <4,3,5,0>, RHS + 3243485853U, // <4,u,3,6>: Cost 3 vsldoi8 <3,6,4,u>, <3,6,4,u> + 3509226824U, // <4,u,3,7>: Cost 3 vmrglw <3,2,4,3>, RHS + 3363002372U, // <4,u,3,u>: Cost 3 vsldoi12 <1,2,3,4>, + 3114172518U, // <4,u,4,0>: Cost 2 vsldoi4 <4,4,u,4>, LHS + 2308577070U, // <4,u,4,1>: Cost 2 vmrghw <4,4,4,4>, LHS + 3235523665U, // <4,u,4,2>: Cost 3 vsldoi8 <2,3,4,u>, <4,2,u,3> + 2442789020U, // <4,u,4,3>: Cost 2 vmrglw <4,4,4,4>, LHS + 1504103734U, // <4,u,4,4>: Cost 1 vspltisw0 RHS + 3235523894U, // <4,u,4,5>: Cost 2 vsldoi8 <2,3,4,u>, RHS + 3235523993U, // <4,u,4,6>: Cost 3 vsldoi8 <2,3,4,u>, <4,6,u,7> + 2442792264U, // <4,u,4,7>: Cost 2 vmrglw <4,4,4,4>, RHS + 1504103734U, // <4,u,4,u>: Cost 1 vspltisw0 RHS + 2309412563U, // <4,u,5,0>: Cost 2 vmrghw RHS, + 1235670830U, // <4,u,5,1>: Cost 1 vmrghw RHS, LHS + 2309412741U, // <4,u,5,2>: Cost 2 vmrghw RHS, + 2430189724U, // <4,u,5,3>: Cost 2 vmrglw <2,3,4,5>, LHS + 2309412927U, // <4,u,5,4>: Cost 2 vmrghw RHS, + 1235671194U, // <4,u,5,5>: Cost 1 vmrghw RHS, RHS + 3363002522U, // <4,u,5,6>: Cost 2 vsldoi12 <1,2,3,4>, RHS + 2430192968U, // <4,u,5,7>: Cost 2 vmrglw <2,3,4,5>, RHS + 1235671397U, // <4,u,5,u>: Cost 1 vmrghw RHS, LHS + 3108216934U, // <4,u,6,0>: Cost 2 vsldoi4 <3,4,u,6>, LHS + 4170015851U, // <4,u,6,1>: Cost 3 vsldoi4 <1,4,u,6>, <1,4,u,6> + 4175988548U, // <4,u,6,2>: Cost 3 vsldoi4 <2,4,u,6>, <2,4,u,6> + 3108219421U, // <4,u,6,3>: Cost 2 vsldoi4 <3,4,u,6>, <3,4,u,6> + 3108220214U, // <4,u,6,4>: Cost 2 vsldoi4 <3,4,u,6>, RHS + 3383703706U, // <4,u,6,5>: Cost 3 vmrghw <4,6,5,2>, RHS + 4199879336U, // <4,u,6,6>: Cost 3 vsldoi4 <6,4,u,6>, <6,4,u,6> 27705344U, // <4,u,6,7>: Cost 0 copy RHS 27705344U, // <4,u,6,u>: Cost 0 copy RHS - 3255621888U, // <4,u,7,0>: Cost 3 vsldoi12 <5,6,7,4>, - 3250132782U, // <4,u,7,1>: Cost 3 vmrghw <4,7,5,0>, LHS - 4204246205U, // <4,u,7,2>: Cost 3 vsldoi8 <7,2,4,u>, <7,2,4,u> - 3377692828U, // <4,u,7,3>: Cost 3 vmrglw <3,6,4,7>, LHS - 3255621928U, // <4,u,7,4>: Cost 3 vsldoi12 <5,6,7,4>, - 3250133146U, // <4,u,7,5>: Cost 3 vmrghw <4,7,5,0>, RHS - 4206900737U, // <4,u,7,6>: Cost 3 vsldoi8 <7,6,4,u>, <7,6,4,u> - 3377696072U, // <4,u,7,7>: Cost 3 vmrglw <3,6,4,7>, RHS - 3377692833U, // <4,u,7,u>: Cost 3 vmrglw <3,6,4,7>, LHS - 2974015590U, // <4,u,u,0>: Cost 2 vsldoi4 <3,4,u,u>, LHS - 1103443758U, // <4,u,u,1>: Cost 1 vmrghw RHS, LHS - 3228784997U, // <4,u,u,2>: Cost 2 vsldoi12 <1,2,3,4>, LHS - 2295996572U, // <4,u,u,3>: Cost 2 vmrglw <2,3,4,u>, LHS - 1369886006U, // <4,u,u,4>: Cost 1 vspltisw0 RHS - 1103444122U, // <4,u,u,5>: Cost 1 vmrghw RHS, RHS - 3228785037U, // <4,u,u,6>: Cost 2 vsldoi12 <1,2,3,4>, RHS + 3389839616U, // <4,u,7,0>: Cost 3 vsldoi12 <5,6,7,4>, + 3384350510U, // <4,u,7,1>: Cost 3 vmrghw <4,7,5,0>, LHS + 3264722109U, // <4,u,7,2>: Cost 3 vsldoi8 <7,2,4,u>, <7,2,4,u> + 3511910556U, // <4,u,7,3>: Cost 3 vmrglw <3,6,4,7>, LHS + 3389839656U, // <4,u,7,4>: Cost 3 vsldoi12 <5,6,7,4>, + 3384350874U, // <4,u,7,5>: Cost 3 vmrghw <4,7,5,0>, RHS + 3267376641U, // <4,u,7,6>: Cost 3 vsldoi8 <7,6,4,u>, <7,6,4,u> + 3511913800U, // <4,u,7,7>: Cost 3 vmrglw <3,6,4,7>, RHS + 3511910561U, // <4,u,7,u>: Cost 3 vmrglw <3,6,4,7>, LHS + 3108233318U, // <4,u,u,0>: Cost 2 vsldoi4 <3,4,u,u>, LHS + 1237661486U, // <4,u,u,1>: Cost 1 vmrghw RHS, LHS + 3363002725U, // <4,u,u,2>: Cost 2 vsldoi12 <1,2,3,4>, LHS + 2430214300U, // <4,u,u,3>: Cost 2 vmrglw <2,3,4,u>, LHS + 1504103734U, // <4,u,u,4>: Cost 1 vspltisw0 RHS + 1237661850U, // <4,u,u,5>: Cost 1 vmrghw RHS, RHS + 3363002765U, // <4,u,u,6>: Cost 2 vsldoi12 <1,2,3,4>, RHS 27705344U, // <4,u,u,7>: Cost 0 copy RHS 27705344U, // <4,u,u,u>: Cost 0 copy RHS - 3223994368U, // <5,0,0,0>: Cost 3 vsldoi12 <0,4,1,5>, <0,0,0,0> - 3223994378U, // <5,0,0,1>: Cost 3 vsldoi12 <0,4,1,5>, <0,0,1,1> - 4053739214U, // <5,0,0,2>: Cost 4 vsldoi4 <4,5,0,0>, <2,3,4,5> - 3376385762U, // <5,0,0,3>: Cost 4 vmrglw <3,4,5,0>, <5,2,0,3> - 3223994405U, // <5,0,0,4>: Cost 3 vsldoi12 <0,4,1,5>, <0,0,4,1> - 3241836594U, // <5,0,0,5>: Cost 4 vsldoi12 <3,4,0,5>, <0,0,5,5> - 4185006573U, // <5,0,0,6>: Cost 4 vsldoi8 <4,0,5,0>, <0,6,0,7> - 3376386090U, // <5,0,0,7>: Cost 4 vmrglw <3,4,5,0>, <5,6,0,7> - 3227164745U, // <5,0,0,u>: Cost 3 vsldoi12 <0,u,u,5>, <0,0,u,1> - 4035829862U, // <5,0,1,0>: Cost 3 vsldoi4 <1,5,0,1>, LHS - 4035830895U, // <5,0,1,1>: Cost 3 vsldoi4 <1,5,0,1>, <1,5,0,1> - 3223994470U, // <5,0,1,2>: Cost 2 vsldoi12 <0,4,1,5>, LHS - 4169081849U, // <5,0,1,3>: Cost 4 vsldoi8 <1,3,5,0>, <1,3,5,0> - 4035833142U, // <5,0,1,4>: Cost 3 vsldoi4 <1,5,0,1>, RHS - 4059721683U, // <5,0,1,5>: Cost 3 vsldoi4 <5,5,0,1>, <5,5,0,1> - 4185670899U, // <5,0,1,6>: Cost 4 vsldoi8 <4,1,5,0>, <1,6,5,7> - 3385019000U, // <5,0,1,7>: Cost 4 vmrglw <4,u,5,1>, <3,6,0,7> - 3223994524U, // <5,0,1,u>: Cost 2 vsldoi12 <0,4,1,5>, LHS - 3376398336U, // <5,0,2,0>: Cost 4 vmrglw <3,4,5,2>, <0,0,0,0> - 3252510822U, // <5,0,2,1>: Cost 3 vmrghw <5,2,1,3>, LHS - 4175717992U, // <5,0,2,2>: Cost 4 vsldoi8 <2,4,5,0>, <2,2,2,2> - 4181690062U, // <5,0,2,3>: Cost 3 vsldoi8 <3,4,5,0>, <2,3,4,5> - 3223994567U, // <5,0,2,4>: Cost 4 vsldoi12 <0,4,1,5>, <0,2,4,1> - 3241836754U, // <5,0,2,5>: Cost 4 vsldoi12 <3,4,0,5>, <0,2,5,3> - 4181690298U, // <5,0,2,6>: Cost 4 vsldoi8 <3,4,5,0>, <2,6,3,7> - 4213540842U, // <5,0,2,7>: Cost 4 vsldoi8 , <2,7,0,1> - 3252511389U, // <5,0,2,u>: Cost 3 vmrghw <5,2,1,3>, LHS - 4186998934U, // <5,0,3,0>: Cost 3 vsldoi8 <4,3,5,0>, <3,0,1,2> - 3223994620U, // <5,0,3,1>: Cost 4 vsldoi12 <0,4,1,5>, <0,3,1,0> - 4181690700U, // <5,0,3,2>: Cost 4 vsldoi8 <3,4,5,0>, <3,2,3,4> - 4181690780U, // <5,0,3,3>: Cost 4 vsldoi8 <3,4,5,0>, <3,3,3,3> - 4181690876U, // <5,0,3,4>: Cost 3 vsldoi8 <3,4,5,0>, <3,4,5,0> - 3379726804U, // <5,0,3,5>: Cost 4 vmrglw <4,0,5,3>, <3,4,0,5> - 4205578932U, // <5,0,3,6>: Cost 4 vsldoi8 <7,4,5,0>, <3,6,7,4> - 3363138168U, // <5,0,3,7>: Cost 5 vmrglw <1,2,5,3>, <3,6,0,7> - 4184345408U, // <5,0,3,u>: Cost 3 vsldoi8 <3,u,5,0>, <3,u,5,0> - 4035854438U, // <5,0,4,0>: Cost 3 vsldoi4 <1,5,0,4>, LHS - 3223994706U, // <5,0,4,1>: Cost 2 vsldoi12 <0,4,1,5>, <0,4,1,5> - 3224068443U, // <5,0,4,2>: Cost 4 vsldoi12 <0,4,2,5>, <0,4,2,5> - 4186999940U, // <5,0,4,3>: Cost 3 vsldoi8 <4,3,5,0>, <4,3,5,0> - 3223994733U, // <5,0,4,4>: Cost 3 vsldoi12 <0,4,1,5>, <0,4,4,5> - 4181691702U, // <5,0,4,5>: Cost 3 vsldoi8 <3,4,5,0>, RHS - 4181691774U, // <5,0,4,6>: Cost 4 vsldoi8 <3,4,5,0>, <4,6,5,7> - 4189654472U, // <5,0,4,7>: Cost 3 vsldoi8 <4,7,5,0>, <4,7,5,0> - 3223994706U, // <5,0,4,u>: Cost 2 vsldoi12 <0,4,1,5>, <0,4,1,5> - 3385049088U, // <5,0,5,0>: Cost 3 vmrglw <4,u,5,5>, <0,0,0,0> - 2181070950U, // <5,0,5,1>: Cost 2 vmrghw <5,5,5,5>, LHS - 4181692130U, // <5,0,5,2>: Cost 4 vsldoi8 <3,4,5,0>, <5,2,0,3> - 3241836976U, // <5,0,5,3>: Cost 4 vsldoi12 <3,4,0,5>, <0,5,3,0> - 3254813010U, // <5,0,5,4>: Cost 3 vmrghw <5,5,5,5>, <0,4,1,5> - 3254813154U, // <5,0,5,5>: Cost 3 vmrghw <5,5,5,5>, <0,5,u,5> - 4181692458U, // <5,0,5,6>: Cost 4 vsldoi8 <3,4,5,0>, <5,6,0,7> - 3385051768U, // <5,0,5,7>: Cost 4 vmrglw <4,u,5,5>, <3,6,0,7> - 2181071517U, // <5,0,5,u>: Cost 2 vmrghw <5,5,5,5>, LHS - 3376431104U, // <5,0,6,0>: Cost 3 vmrglw <3,4,5,6>, <0,0,0,0> - 2181840998U, // <5,0,6,1>: Cost 2 vmrghw <5,6,7,0>, LHS - 4189655546U, // <5,0,6,2>: Cost 4 vsldoi8 <4,7,5,0>, <6,2,7,3> - 3376432160U, // <5,0,6,3>: Cost 4 vmrglw <3,4,5,6>, <1,4,0,3> - 3255583058U, // <5,0,6,4>: Cost 3 vmrghw <5,6,7,0>, <0,4,1,5> - 3255583140U, // <5,0,6,5>: Cost 3 vmrghw <5,6,7,0>, <0,5,1,6> - 3376433702U, // <5,0,6,6>: Cost 4 vmrglw <3,4,5,6>, <3,5,0,6> - 4205581174U, // <5,0,6,7>: Cost 3 vsldoi8 <7,4,5,0>, <6,7,4,5> - 2181841565U, // <5,0,6,u>: Cost 2 vmrghw <5,6,7,0>, LHS - 4189656058U, // <5,0,7,0>: Cost 3 vsldoi8 <4,7,5,0>, <7,0,1,2> - 3365823599U, // <5,0,7,1>: Cost 4 vmrglw <1,6,5,7>, <1,5,0,1> - 4211553501U, // <5,0,7,2>: Cost 4 vsldoi8 , <7,2,u,4> - 4187002083U, // <5,0,7,3>: Cost 4 vsldoi8 <4,3,5,0>, <7,3,0,1> - 4205581664U, // <5,0,7,4>: Cost 3 vsldoi8 <7,4,5,0>, <7,4,5,0> - 4189656452U, // <5,0,7,5>: Cost 4 vsldoi8 <4,7,5,0>, <7,5,0,0> - 4205581848U, // <5,0,7,6>: Cost 4 vsldoi8 <7,4,5,0>, <7,6,7,4> - 4189656615U, // <5,0,7,7>: Cost 4 vsldoi8 <4,7,5,0>, <7,7,0,1> - 4208236196U, // <5,0,7,u>: Cost 3 vsldoi8 <7,u,5,0>, <7,u,5,0> - 4035887206U, // <5,0,u,0>: Cost 3 vsldoi4 <1,5,0,u>, LHS - 3226649238U, // <5,0,u,1>: Cost 2 vsldoi12 <0,u,1,5>, <0,u,1,5> - 3223995037U, // <5,0,u,2>: Cost 2 vsldoi12 <0,4,1,5>, LHS - 4181690062U, // <5,0,u,3>: Cost 3 vsldoi8 <3,4,5,0>, <2,3,4,5> - 3223995053U, // <5,0,u,4>: Cost 3 vsldoi12 <0,4,1,5>, <0,u,4,1> - 4181694618U, // <5,0,u,5>: Cost 3 vsldoi8 <3,4,5,0>, RHS - 4181694672U, // <5,0,u,6>: Cost 4 vsldoi8 <3,4,5,0>, - 4213545260U, // <5,0,u,7>: Cost 3 vsldoi8 , - 3223995091U, // <5,0,u,u>: Cost 2 vsldoi12 <0,4,1,5>, LHS - 4190322688U, // <5,1,0,0>: Cost 3 vsldoi8 <4,u,5,1>, <0,0,0,0> - 3116580966U, // <5,1,0,1>: Cost 2 vsldoi8 <4,u,5,1>, LHS - 3384349690U, // <5,1,0,2>: Cost 3 vmrglw <4,7,5,0>, <7,0,1,2> - 4190322940U, // <5,1,0,3>: Cost 4 vsldoi8 <4,u,5,1>, <0,3,1,0> - 4190323026U, // <5,1,0,4>: Cost 3 vsldoi8 <4,u,5,1>, <0,4,1,5> - 3380363602U, // <5,1,0,5>: Cost 3 vmrglw <4,1,5,0>, <0,4,1,5> - 4190323190U, // <5,1,0,6>: Cost 4 vsldoi8 <4,u,5,1>, <0,6,1,7> - 4071732621U, // <5,1,0,7>: Cost 4 vsldoi4 <7,5,1,0>, <7,5,1,0> - 3116581533U, // <5,1,0,u>: Cost 2 vsldoi8 <4,u,5,1>, LHS - 4059791462U, // <5,1,1,0>: Cost 3 vsldoi4 <5,5,1,1>, LHS - 3223995188U, // <5,1,1,1>: Cost 3 vsldoi12 <0,4,1,5>, <1,1,1,1> - 3385018518U, // <5,1,1,2>: Cost 3 vmrglw <4,u,5,1>, <3,0,1,2> - 3385020139U, // <5,1,1,3>: Cost 3 vmrglw <4,u,5,1>, <5,2,1,3> - 3228197715U, // <5,1,1,4>: Cost 3 vsldoi12 <1,1,4,5>, <1,1,4,5> - 3223995228U, // <5,1,1,5>: Cost 3 vsldoi12 <0,4,1,5>, <1,1,5,5> - 3385016497U, // <5,1,1,6>: Cost 4 vmrglw <4,u,5,1>, <0,2,1,6> - 3385020467U, // <5,1,1,7>: Cost 3 vmrglw <4,u,5,1>, <5,6,1,7> - 3228492663U, // <5,1,1,u>: Cost 3 vsldoi12 <1,1,u,5>, <1,1,u,5> - 4035911782U, // <5,1,2,0>: Cost 4 vsldoi4 <1,5,1,2>, LHS - 3226649479U, // <5,1,2,1>: Cost 4 vsldoi12 <0,u,1,5>, <1,2,1,3> - 4190324328U, // <5,1,2,2>: Cost 3 vsldoi8 <4,u,5,1>, <2,2,2,2> - 3223995286U, // <5,1,2,3>: Cost 3 vsldoi12 <0,4,1,5>, <1,2,3,0> - 3228861348U, // <5,1,2,4>: Cost 3 vsldoi12 <1,2,4,5>, <1,2,4,5> - 3223995307U, // <5,1,2,5>: Cost 3 vsldoi12 <0,4,1,5>, <1,2,5,3> - 4190324666U, // <5,1,2,6>: Cost 3 vsldoi8 <4,u,5,1>, <2,6,3,7> - 3268379578U, // <5,1,2,7>: Cost 4 vsldoi12 <7,u,0,5>, <1,2,7,0> - 3223995331U, // <5,1,2,u>: Cost 3 vsldoi12 <0,4,1,5>, <1,2,u,0> - 4190324886U, // <5,1,3,0>: Cost 3 vsldoi8 <4,u,5,1>, <3,0,1,2> - 3363135498U, // <5,1,3,1>: Cost 4 vmrglw <1,2,5,3>, <0,0,1,1> - 3363137686U, // <5,1,3,2>: Cost 4 vmrglw <1,2,5,3>, <3,0,1,2> - 4190325148U, // <5,1,3,3>: Cost 3 vsldoi8 <4,u,5,1>, <3,3,3,3> - 4190325250U, // <5,1,3,4>: Cost 3 vsldoi8 <4,u,5,1>, <3,4,5,6> - 3363135826U, // <5,1,3,5>: Cost 3 vmrglw <1,2,5,3>, <0,4,1,5> - 4190325368U, // <5,1,3,6>: Cost 4 vsldoi8 <4,u,5,1>, <3,6,0,7> - 4190325443U, // <5,1,3,7>: Cost 4 vsldoi8 <4,u,5,1>, <3,7,0,1> - 4190325534U, // <5,1,3,u>: Cost 3 vsldoi8 <4,u,5,1>, <3,u,1,2> - 3111275410U, // <5,1,4,0>: Cost 2 vsldoi8 <4,0,5,1>, <4,0,5,1> - 3229967403U, // <5,1,4,1>: Cost 3 vsldoi12 <1,4,1,5>, <1,4,1,5> - 3230041140U, // <5,1,4,2>: Cost 3 vsldoi12 <1,4,2,5>, <1,4,2,5> - 4190325892U, // <5,1,4,3>: Cost 4 vsldoi8 <4,u,5,1>, <4,3,5,0> - 4190325968U, // <5,1,4,4>: Cost 3 vsldoi8 <4,u,5,1>, <4,4,4,4> - 3116584246U, // <5,1,4,5>: Cost 2 vsldoi8 <4,u,5,1>, RHS - 4188999032U, // <5,1,4,6>: Cost 4 vsldoi8 <4,6,5,1>, <4,6,5,1> - 4189662665U, // <5,1,4,7>: Cost 4 vsldoi8 <4,7,5,1>, <4,7,5,1> - 3116584474U, // <5,1,4,u>: Cost 2 vsldoi8 <4,u,5,1>, <4,u,5,1> - 3223995503U, // <5,1,5,0>: Cost 3 vsldoi12 <0,4,1,5>, <1,5,0,1> - 4190326415U, // <5,1,5,1>: Cost 3 vsldoi8 <4,u,5,1>, <5,1,0,1> - 4190326507U, // <5,1,5,2>: Cost 3 vsldoi8 <4,u,5,1>, <5,2,1,3> - 3223995529U, // <5,1,5,3>: Cost 4 vsldoi12 <0,4,1,5>, <1,5,3,0> - 3223995543U, // <5,1,5,4>: Cost 3 vsldoi12 <0,4,1,5>, <1,5,4,5> - 3362488658U, // <5,1,5,5>: Cost 3 vmrglw <1,1,5,5>, <0,4,1,5> - 4190326835U, // <5,1,5,6>: Cost 3 vsldoi8 <4,u,5,1>, <5,6,1,7> - 4190326909U, // <5,1,5,7>: Cost 4 vsldoi8 <4,u,5,1>, <5,7,1,0> - 3223995575U, // <5,1,5,u>: Cost 3 vsldoi12 <0,4,1,5>, <1,5,u,1> - 4077748326U, // <5,1,6,0>: Cost 3 vsldoi4 , LHS - 3364487826U, // <5,1,6,1>: Cost 3 vmrglw <1,4,5,6>, <0,u,1,1> - 3376433302U, // <5,1,6,2>: Cost 3 vmrglw <3,4,5,6>, <3,0,1,2> - 3364488071U, // <5,1,6,3>: Cost 4 vmrglw <1,4,5,6>, <1,2,1,3> - 3376431360U, // <5,1,6,4>: Cost 3 vmrglw <3,4,5,6>, <0,3,1,4> - 3223995635U, // <5,1,6,5>: Cost 3 vsldoi12 <0,4,1,5>, <1,6,5,7> - 4190327608U, // <5,1,6,6>: Cost 3 vsldoi8 <4,u,5,1>, <6,6,6,6> - 4190327630U, // <5,1,6,7>: Cost 3 vsldoi8 <4,u,5,1>, <6,7,0,1> - 3376431121U, // <5,1,6,u>: Cost 3 vmrglw <3,4,5,6>, <0,0,1,u> - 4190327802U, // <5,1,7,0>: Cost 3 vsldoi8 <4,u,5,1>, <7,0,1,2> - 3365822474U, // <5,1,7,1>: Cost 4 vmrglw <1,6,5,7>, <0,0,1,1> - 3365824662U, // <5,1,7,2>: Cost 4 vmrglw <1,6,5,7>, <3,0,1,2> - 4190328035U, // <5,1,7,3>: Cost 4 vsldoi8 <4,u,5,1>, <7,3,0,1> - 4190328166U, // <5,1,7,4>: Cost 3 vsldoi8 <4,u,5,1>, <7,4,5,6> - 3365822802U, // <5,1,7,5>: Cost 3 vmrglw <1,6,5,7>, <0,4,1,5> - 3365823613U, // <5,1,7,6>: Cost 4 vmrglw <1,6,5,7>, <1,5,1,6> - 4190328428U, // <5,1,7,7>: Cost 3 vsldoi8 <4,u,5,1>, <7,7,7,7> - 4190328450U, // <5,1,7,u>: Cost 3 vsldoi8 <4,u,5,1>, <7,u,1,2> - 3135166198U, // <5,1,u,0>: Cost 2 vsldoi8 , - 3116586798U, // <5,1,u,1>: Cost 2 vsldoi8 <4,u,5,1>, LHS - 3232695672U, // <5,1,u,2>: Cost 3 vsldoi12 <1,u,2,5>, <1,u,2,5> - 3223995772U, // <5,1,u,3>: Cost 3 vsldoi12 <0,4,1,5>, <1,u,3,0> - 3232843146U, // <5,1,u,4>: Cost 3 vsldoi12 <1,u,4,5>, <1,u,4,5> - 3116587162U, // <5,1,u,5>: Cost 2 vsldoi8 <4,u,5,1>, RHS - 4190329040U, // <5,1,u,6>: Cost 3 vsldoi8 <4,u,5,1>, - 4190329088U, // <5,1,u,7>: Cost 3 vsldoi8 <4,u,5,1>, - 3116587365U, // <5,1,u,u>: Cost 2 vsldoi8 <4,u,5,1>, LHS - 4181704704U, // <5,2,0,0>: Cost 4 vsldoi8 <3,4,5,2>, <0,0,0,0> - 4181704806U, // <5,2,0,1>: Cost 3 vsldoi8 <3,4,5,2>, LHS - 3234833861U, // <5,2,0,2>: Cost 4 vsldoi12 <2,2,4,5>, <2,0,2,1> - 3376382054U, // <5,2,0,3>: Cost 3 vmrglw <3,4,5,0>, LHS - 4167770450U, // <5,2,0,4>: Cost 4 vsldoi8 <1,1,5,2>, <0,4,1,5> - 3381027892U, // <5,2,0,5>: Cost 4 vmrglw <4,2,5,0>, <1,4,2,5> - 3238815209U, // <5,2,0,6>: Cost 4 vsldoi12 <2,u,4,5>, <2,0,6,1> - 3408232554U, // <5,2,0,7>: Cost 4 vmrglw , <0,1,2,7> - 3376382059U, // <5,2,0,u>: Cost 3 vmrglw <3,4,5,0>, LHS - 4035977318U, // <5,2,1,0>: Cost 4 vsldoi4 <1,5,2,1>, LHS - 4167770969U, // <5,2,1,1>: Cost 4 vsldoi8 <1,1,5,2>, <1,1,5,2> - 3385017960U, // <5,2,1,2>: Cost 3 vmrglw <4,u,5,1>, <2,2,2,2> - 2311274598U, // <5,2,1,3>: Cost 2 vmrglw <4,u,5,1>, LHS - 4035980598U, // <5,2,1,4>: Cost 4 vsldoi4 <1,5,2,1>, RHS - 3381036084U, // <5,2,1,5>: Cost 4 vmrglw <4,2,5,1>, <1,4,2,5> - 3385018045U, // <5,2,1,6>: Cost 4 vmrglw <4,u,5,1>, <2,3,2,6> - 3385017560U, // <5,2,1,7>: Cost 4 vmrglw <4,u,5,1>, <1,6,2,7> - 2311274603U, // <5,2,1,u>: Cost 2 vmrglw <4,u,5,1>, LHS - 4035985510U, // <5,2,2,0>: Cost 4 vsldoi4 <1,5,2,2>, LHS - 4035986562U, // <5,2,2,1>: Cost 4 vsldoi4 <1,5,2,2>, <1,5,2,2> - 3223996008U, // <5,2,2,2>: Cost 3 vsldoi12 <0,4,1,5>, <2,2,2,2> - 3223996018U, // <5,2,2,3>: Cost 3 vsldoi12 <0,4,1,5>, <2,2,3,3> - 3234834045U, // <5,2,2,4>: Cost 3 vsldoi12 <2,2,4,5>, <2,2,4,5> - 3230041732U, // <5,2,2,5>: Cost 4 vsldoi12 <1,4,2,5>, <2,2,5,3> - 3238815376U, // <5,2,2,6>: Cost 4 vsldoi12 <2,u,4,5>, <2,2,6,6> - 3376402492U, // <5,2,2,7>: Cost 4 vmrglw <3,4,5,2>, <5,6,2,7> - 3223996063U, // <5,2,2,u>: Cost 3 vsldoi12 <0,4,1,5>, <2,2,u,3> - 3223996070U, // <5,2,3,0>: Cost 3 vsldoi12 <0,4,1,5>, <2,3,0,1> - 3223996079U, // <5,2,3,1>: Cost 4 vsldoi12 <0,4,1,5>, <2,3,1,1> - 4053911246U, // <5,2,3,2>: Cost 3 vsldoi4 <4,5,2,3>, <2,3,4,5> - 3363135590U, // <5,2,3,3>: Cost 3 vmrglw <1,2,5,3>, LHS - 3235497678U, // <5,2,3,4>: Cost 2 vsldoi12 <2,3,4,5>, <2,3,4,5> - 3254814423U, // <5,2,3,5>: Cost 3 vsldoi12 <5,5,5,5>, <2,3,5,5> - 3250833121U, // <5,2,3,6>: Cost 4 vsldoi12 <4,u,5,5>, <2,3,6,6> - 4205595371U, // <5,2,3,7>: Cost 4 vsldoi8 <7,4,5,2>, <3,7,4,5> - 3235792626U, // <5,2,3,u>: Cost 2 vsldoi12 <2,3,u,5>, <2,3,u,5> - 3235866363U, // <5,2,4,0>: Cost 4 vsldoi12 <2,4,0,5>, <2,4,0,5> - 4185689060U, // <5,2,4,1>: Cost 3 vsldoi8 <4,1,5,2>, <4,1,5,2> - 3236013837U, // <5,2,4,2>: Cost 3 vsldoi12 <2,4,2,5>, <2,4,2,5> - 3235497750U, // <5,2,4,3>: Cost 3 vsldoi12 <2,3,4,5>, <2,4,3,5> - 3236161311U, // <5,2,4,4>: Cost 4 vsldoi12 <2,4,4,5>, <2,4,4,5> - 4181708086U, // <5,2,4,5>: Cost 3 vsldoi8 <3,4,5,2>, RHS - 4189007225U, // <5,2,4,6>: Cost 3 vsldoi8 <4,6,5,2>, <4,6,5,2> - 4189670858U, // <5,2,4,7>: Cost 4 vsldoi8 <4,7,5,2>, <4,7,5,2> - 3235497795U, // <5,2,4,u>: Cost 3 vsldoi12 <2,3,4,5>, <2,4,u,5> - 3230041928U, // <5,2,5,0>: Cost 4 vsldoi12 <1,4,2,5>, <2,5,0,1> - 3230041938U, // <5,2,5,1>: Cost 4 vsldoi12 <1,4,2,5>, <2,5,1,2> - 3385050728U, // <5,2,5,2>: Cost 3 vmrglw <4,u,5,5>, <2,2,2,2> - 2311307366U, // <5,2,5,3>: Cost 2 vmrglw <4,u,5,5>, LHS - 3230041968U, // <5,2,5,4>: Cost 4 vsldoi12 <1,4,2,5>, <2,5,4,5> - 3369124916U, // <5,2,5,5>: Cost 4 vmrglw <2,2,5,5>, <1,4,2,5> - 3254814650U, // <5,2,5,6>: Cost 3 vmrghw <5,5,5,5>, <2,6,3,7> - 4189008009U, // <5,2,5,7>: Cost 4 vsldoi8 <4,6,5,2>, <5,7,2,3> - 2311307371U, // <5,2,5,u>: Cost 2 vmrglw <4,u,5,5>, LHS - 4036018278U, // <5,2,6,0>: Cost 4 vsldoi4 <1,5,2,6>, LHS - 4036019334U, // <5,2,6,1>: Cost 4 vsldoi4 <1,5,2,6>, <1,5,2,6> - 3370460776U, // <5,2,6,2>: Cost 3 vmrglw <2,4,5,6>, <2,2,2,2> - 2302689382U, // <5,2,6,3>: Cost 2 vmrglw <3,4,5,6>, LHS - 4036021558U, // <5,2,6,4>: Cost 4 vsldoi4 <1,5,2,6>, RHS - 3230042060U, // <5,2,6,5>: Cost 4 vsldoi12 <1,4,2,5>, <2,6,5,7> - 3255584698U, // <5,2,6,6>: Cost 3 vmrghw <5,6,7,0>, <2,6,3,7> - 3370461105U, // <5,2,6,7>: Cost 4 vmrglw <2,4,5,6>, <2,6,2,7> - 2302689387U, // <5,2,6,u>: Cost 2 vmrglw <3,4,5,6>, LHS - 4189008890U, // <5,2,7,0>: Cost 4 vsldoi8 <4,6,5,2>, <7,0,1,2> - 4185691221U, // <5,2,7,1>: Cost 4 vsldoi8 <4,1,5,2>, <7,1,2,3> - 3365824104U, // <5,2,7,2>: Cost 4 vmrglw <1,6,5,7>, <2,2,2,2> - 3365822566U, // <5,2,7,3>: Cost 3 vmrglw <1,6,5,7>, LHS - 3238152210U, // <5,2,7,4>: Cost 4 vsldoi12 <2,7,4,5>, <2,7,4,5> - 3371795508U, // <5,2,7,5>: Cost 4 vmrglw <2,6,5,7>, <1,4,2,5> - 4189009390U, // <5,2,7,6>: Cost 4 vsldoi8 <4,6,5,2>, <7,6,2,7> - 4189009516U, // <5,2,7,7>: Cost 4 vsldoi8 <4,6,5,2>, <7,7,7,7> - 3365822571U, // <5,2,7,u>: Cost 3 vmrglw <1,6,5,7>, LHS - 3223996475U, // <5,2,u,0>: Cost 3 vsldoi12 <0,4,1,5>, <2,u,0,1> - 4181710638U, // <5,2,u,1>: Cost 3 vsldoi8 <3,4,5,2>, LHS - 3370477160U, // <5,2,u,2>: Cost 3 vmrglw <2,4,5,u>, <2,2,2,2> - 2302705766U, // <5,2,u,3>: Cost 2 vmrglw <3,4,5,u>, LHS - 3238815843U, // <5,2,u,4>: Cost 2 vsldoi12 <2,u,4,5>, <2,u,4,5> - 4181711002U, // <5,2,u,5>: Cost 3 vsldoi8 <3,4,5,2>, RHS - 3238963317U, // <5,2,u,6>: Cost 3 vsldoi12 <2,u,6,5>, <2,u,6,5> - 3370477489U, // <5,2,u,7>: Cost 4 vmrglw <2,4,5,u>, <2,6,2,7> - 3239110791U, // <5,2,u,u>: Cost 2 vsldoi12 <2,u,u,5>, <2,u,u,5> - 3223996555U, // <5,3,0,0>: Cost 4 vsldoi12 <0,4,1,5>, <3,0,0,0> - 3223996566U, // <5,3,0,1>: Cost 3 vsldoi12 <0,4,1,5>, <3,0,1,2> - 4042016610U, // <5,3,0,2>: Cost 4 vsldoi4 <2,5,3,0>, <2,5,3,0> - 4036044950U, // <5,3,0,3>: Cost 4 vsldoi4 <1,5,3,0>, <3,0,1,2> - 3223996592U, // <5,3,0,4>: Cost 3 vsldoi12 <0,4,1,5>, <3,0,4,1> - 3376383766U, // <5,3,0,5>: Cost 4 vmrglw <3,4,5,0>, <2,4,3,5> - 4172423697U, // <5,3,0,6>: Cost 5 vsldoi8 <1,u,5,3>, <0,6,4,7> - 3376383930U, // <5,3,0,7>: Cost 4 vmrglw <3,4,5,0>, <2,6,3,7> - 3223996629U, // <5,3,0,u>: Cost 3 vsldoi12 <0,4,1,5>, <3,0,u,2> - 3385017238U, // <5,3,1,0>: Cost 3 vmrglw <4,u,5,1>, <1,2,3,0> - 3379709795U, // <5,3,1,1>: Cost 3 vmrglw <4,0,5,1>, <2,5,3,1> - 4168442795U, // <5,3,1,2>: Cost 3 vsldoi8 <1,2,5,3>, <1,2,5,3> - 3385017970U, // <5,3,1,3>: Cost 3 vmrglw <4,u,5,1>, <2,2,3,3> - 3385017242U, // <5,3,1,4>: Cost 3 vmrglw <4,u,5,1>, <1,2,3,4> - 4168442991U, // <5,3,1,5>: Cost 4 vsldoi8 <1,2,5,3>, <1,5,0,1> - 4168443123U, // <5,3,1,6>: Cost 4 vsldoi8 <1,2,5,3>, <1,6,5,7> - 3385018298U, // <5,3,1,7>: Cost 3 vmrglw <4,u,5,1>, <2,6,3,7> - 4172424593U, // <5,3,1,u>: Cost 3 vsldoi8 <1,u,5,3>, <1,u,5,3> - 3385030533U, // <5,3,2,0>: Cost 3 vmrglw <4,u,5,2>, - 4168443427U, // <5,3,2,1>: Cost 4 vsldoi8 <1,2,5,3>, <2,1,3,5> - 3223996737U, // <5,3,2,2>: Cost 4 vsldoi12 <0,4,1,5>, <3,2,2,2> - 3235498316U, // <5,3,2,3>: Cost 3 vsldoi12 <2,3,4,5>, <3,2,3,4> - 3252881922U, // <5,3,2,4>: Cost 3 vmrghw <5,2,6,3>, <3,4,5,6> - 4168443747U, // <5,3,2,5>: Cost 4 vsldoi8 <1,2,5,3>, <2,5,3,1> - 3223996774U, // <5,3,2,6>: Cost 4 vsldoi12 <0,4,1,5>, <3,2,6,3> - 3238816111U, // <5,3,2,7>: Cost 4 vsldoi12 <2,u,4,5>, <3,2,7,3> - 3238816121U, // <5,3,2,u>: Cost 3 vsldoi12 <2,u,4,5>, <3,2,u,4> - 3223996799U, // <5,3,3,0>: Cost 4 vsldoi12 <0,4,1,5>, <3,3,0,1> - 4168444147U, // <5,3,3,1>: Cost 4 vsldoi8 <1,2,5,3>, <3,1,2,5> - 3235498386U, // <5,3,3,2>: Cost 4 vsldoi12 <2,3,4,5>, <3,3,2,2> - 3223996828U, // <5,3,3,3>: Cost 3 vsldoi12 <0,4,1,5>, <3,3,3,3> - 3241470375U, // <5,3,3,4>: Cost 3 vsldoi12 <3,3,4,5>, <3,3,4,5> - 3363137059U, // <5,3,3,5>: Cost 4 vmrglw <1,2,5,3>, <2,1,3,5> - 3375081320U, // <5,3,3,6>: Cost 4 vmrglw <3,2,5,3>, <2,5,3,6> - 3363137466U, // <5,3,3,7>: Cost 4 vmrglw <1,2,5,3>, <2,6,3,7> - 3241765323U, // <5,3,3,u>: Cost 3 vsldoi12 <3,3,u,5>, <3,3,u,5> - 3241839060U, // <5,3,4,0>: Cost 3 vsldoi12 <3,4,0,5>, <3,4,0,5> - 4168444898U, // <5,3,4,1>: Cost 4 vsldoi8 <1,2,5,3>, <4,1,5,0> - 4186360886U, // <5,3,4,2>: Cost 3 vsldoi8 <4,2,5,3>, <4,2,5,3> - 3242060271U, // <5,3,4,3>: Cost 3 vsldoi12 <3,4,3,5>, <3,4,3,5> - 3242134008U, // <5,3,4,4>: Cost 3 vsldoi12 <3,4,4,5>, <3,4,4,5> - 3223996930U, // <5,3,4,5>: Cost 3 vsldoi12 <0,4,1,5>, <3,4,5,6> - 3235498506U, // <5,3,4,6>: Cost 4 vsldoi12 <2,3,4,5>, <3,4,6,5> - 3376416698U, // <5,3,4,7>: Cost 4 vmrglw <3,4,5,4>, <2,6,3,7> - 3223996957U, // <5,3,4,u>: Cost 3 vsldoi12 <0,4,1,5>, <3,4,u,6> - 3385050006U, // <5,3,5,0>: Cost 3 vmrglw <4,u,5,5>, <1,2,3,0> - 4168445605U, // <5,3,5,1>: Cost 4 vsldoi8 <1,2,5,3>, <5,1,2,5> - 4192333583U, // <5,3,5,2>: Cost 3 vsldoi8 <5,2,5,3>, <5,2,5,3> - 3385050738U, // <5,3,5,3>: Cost 3 vmrglw <4,u,5,5>, <2,2,3,3> - 3385050010U, // <5,3,5,4>: Cost 3 vmrglw <4,u,5,5>, <1,2,3,4> - 3254815314U, // <5,3,5,5>: Cost 3 vmrghw <5,5,5,5>, <3,5,5,5> - 4168446021U, // <5,3,5,6>: Cost 4 vsldoi8 <1,2,5,3>, <5,6,3,7> - 3385051066U, // <5,3,5,7>: Cost 3 vmrglw <4,u,5,5>, <2,6,3,7> - 3385050014U, // <5,3,5,u>: Cost 3 vmrglw <4,u,5,5>, <1,2,3,u> - 4042063974U, // <5,3,6,0>: Cost 3 vsldoi4 <2,5,3,6>, LHS - 4042064692U, // <5,3,6,1>: Cost 4 vsldoi4 <2,5,3,6>, <1,1,1,1> - 4042065768U, // <5,3,6,2>: Cost 3 vsldoi4 <2,5,3,6>, <2,5,3,6> - 4042066434U, // <5,3,6,3>: Cost 3 vsldoi4 <2,5,3,6>, <3,4,5,6> - 4042067254U, // <5,3,6,4>: Cost 3 vsldoi4 <2,5,3,6>, RHS - 3255585373U, // <5,3,6,5>: Cost 3 vmrghw <5,6,7,0>, <3,5,6,7> - 3376433000U, // <5,3,6,6>: Cost 3 vmrglw <3,4,5,6>, <2,5,3,6> - 3376433082U, // <5,3,6,7>: Cost 3 vmrglw <3,4,5,6>, <2,6,3,7> - 4042069806U, // <5,3,6,u>: Cost 3 vsldoi4 <2,5,3,6>, LHS - 3365823382U, // <5,3,7,0>: Cost 4 vmrglw <1,6,5,7>, <1,2,3,0> - 4042073331U, // <5,3,7,1>: Cost 4 vsldoi4 <2,5,3,7>, <1,6,5,7> - 4042073961U, // <5,3,7,2>: Cost 4 vsldoi4 <2,5,3,7>, <2,5,3,7> - 3365824114U, // <5,3,7,3>: Cost 4 vmrglw <1,6,5,7>, <2,2,3,3> - 3244124907U, // <5,3,7,4>: Cost 3 vsldoi12 <3,7,4,5>, <3,7,4,5> - 3365824035U, // <5,3,7,5>: Cost 4 vmrglw <1,6,5,7>, <2,1,3,5> - 3383740183U, // <5,3,7,6>: Cost 4 vmrglw <4,6,5,7>, <2,4,3,6> - 3363833786U, // <5,3,7,7>: Cost 4 vmrglw <1,3,5,7>, <2,6,3,7> - 3244419855U, // <5,3,7,u>: Cost 3 vsldoi12 <3,7,u,5>, <3,7,u,5> - 4042080358U, // <5,3,u,0>: Cost 3 vsldoi4 <2,5,3,u>, LHS - 3223997214U, // <5,3,u,1>: Cost 3 vsldoi12 <0,4,1,5>, <3,u,1,2> - 4042082154U, // <5,3,u,2>: Cost 3 vsldoi4 <2,5,3,u>, <2,5,3,u> - 4042082820U, // <5,3,u,3>: Cost 3 vsldoi4 <2,5,3,u>, <3,4,5,u> - 4042083638U, // <5,3,u,4>: Cost 3 vsldoi4 <2,5,3,u>, RHS - 3223997254U, // <5,3,u,5>: Cost 3 vsldoi12 <0,4,1,5>, <3,u,5,6> - 3376433000U, // <5,3,u,6>: Cost 3 vmrglw <3,4,5,6>, <2,5,3,6> - 3376449466U, // <5,3,u,7>: Cost 3 vmrglw <3,4,5,u>, <2,6,3,7> - 3223997277U, // <5,3,u,u>: Cost 3 vsldoi12 <0,4,1,5>, <3,u,u,2> - 4167786509U, // <5,4,0,0>: Cost 4 vsldoi8 <1,1,5,4>, <0,0,1,4> - 4181721190U, // <5,4,0,1>: Cost 3 vsldoi8 <3,4,5,4>, LHS - 4054034126U, // <5,4,0,2>: Cost 4 vsldoi4 <4,5,4,0>, <2,3,4,5> - 4054034944U, // <5,4,0,3>: Cost 4 vsldoi4 <4,5,4,0>, <3,4,5,4> - 4185702738U, // <5,4,0,4>: Cost 3 vsldoi8 <4,1,5,4>, <0,4,1,5> - 3376383694U, // <5,4,0,5>: Cost 3 vmrglw <3,4,5,0>, <2,3,4,5> - 3376383695U, // <5,4,0,6>: Cost 5 vmrglw <3,4,5,0>, <2,3,4,6> - 3384351018U, // <5,4,0,7>: Cost 4 vmrglw <4,7,5,0>, - 4181721757U, // <5,4,0,u>: Cost 3 vsldoi8 <3,4,5,4>, LHS - 3379712881U, // <5,4,1,0>: Cost 3 vmrglw <4,0,5,1>, <6,7,4,0> - 4167787355U, // <5,4,1,1>: Cost 4 vsldoi8 <1,1,5,4>, <1,1,5,4> - 4169114522U, // <5,4,1,2>: Cost 4 vsldoi8 <1,3,5,4>, <1,2,3,4> - 4169114621U, // <5,4,1,3>: Cost 4 vsldoi8 <1,3,5,4>, <1,3,5,4> - 3385019600U, // <5,4,1,4>: Cost 3 vmrglw <4,u,5,1>, <4,4,4,4> - 3223997410U, // <5,4,1,5>: Cost 3 vsldoi12 <0,4,1,5>, <4,1,5,0> - 4185703667U, // <5,4,1,6>: Cost 4 vsldoi8 <4,1,5,4>, <1,6,5,7> - 3385019036U, // <5,4,1,7>: Cost 4 vmrglw <4,u,5,1>, <3,6,4,7> - 3385018065U, // <5,4,1,u>: Cost 3 vmrglw <4,u,5,1>, <2,3,4,u> - 4054048870U, // <5,4,2,0>: Cost 4 vsldoi4 <4,5,4,2>, LHS - 4185703971U, // <5,4,2,1>: Cost 4 vsldoi8 <4,1,5,4>, <2,1,3,5> - 4175750760U, // <5,4,2,2>: Cost 4 vsldoi8 <2,4,5,4>, <2,2,2,2> - 4181722830U, // <5,4,2,3>: Cost 3 vsldoi8 <3,4,5,4>, <2,3,4,5> - 4175750951U, // <5,4,2,4>: Cost 4 vsldoi8 <2,4,5,4>, <2,4,5,4> - 3235499062U, // <5,4,2,5>: Cost 3 vsldoi12 <2,3,4,5>, <4,2,5,3> - 4181723066U, // <5,4,2,6>: Cost 4 vsldoi8 <3,4,5,4>, <2,6,3,7> - 3376401052U, // <5,4,2,7>: Cost 5 vmrglw <3,4,5,2>, <3,6,4,7> - 3252514330U, // <5,4,2,u>: Cost 3 vmrghw <5,2,1,3>, <4,u,5,1> - 4181723286U, // <5,4,3,0>: Cost 4 vsldoi8 <3,4,5,4>, <3,0,1,2> - 3363135525U, // <5,4,3,1>: Cost 4 vmrglw <1,2,5,3>, <0,0,4,1> - 4181723468U, // <5,4,3,2>: Cost 4 vsldoi8 <3,4,5,4>, <3,2,3,4> - 4181723548U, // <5,4,3,3>: Cost 4 vsldoi8 <3,4,5,4>, <3,3,3,3> - 4181723648U, // <5,4,3,4>: Cost 3 vsldoi8 <3,4,5,4>, <3,4,5,4> - 3381053134U, // <5,4,3,5>: Cost 3 vmrglw <4,2,5,3>, <2,3,4,5> - 3262041236U, // <5,4,3,6>: Cost 4 vsldoi12 <6,7,4,5>, <4,3,6,7> - 3363138204U, // <5,4,3,7>: Cost 5 vmrglw <1,2,5,3>, <3,6,4,7> - 4184378180U, // <5,4,3,u>: Cost 3 vsldoi8 <3,u,5,4>, <3,u,5,4> - 4185041813U, // <5,4,4,0>: Cost 3 vsldoi8 <4,0,5,4>, <4,0,5,4> - 4185705446U, // <5,4,4,1>: Cost 3 vsldoi8 <4,1,5,4>, <4,1,5,4> - 4181724214U, // <5,4,4,2>: Cost 4 vsldoi8 <3,4,5,4>, <4,2,5,3> - 4187032712U, // <5,4,4,3>: Cost 3 vsldoi8 <4,3,5,4>, <4,3,5,4> - 3223997648U, // <5,4,4,4>: Cost 3 vsldoi12 <0,4,1,5>, <4,4,4,4> - 3248180442U, // <5,4,4,5>: Cost 2 vsldoi12 <4,4,5,5>, <4,4,5,5> - 4181724542U, // <5,4,4,6>: Cost 4 vsldoi8 <3,4,5,4>, <4,6,5,7> - 4189687244U, // <5,4,4,7>: Cost 3 vsldoi8 <4,7,5,4>, <4,7,5,4> - 3248401653U, // <5,4,4,u>: Cost 2 vsldoi12 <4,4,u,5>, <4,4,u,5> - 4036157542U, // <5,4,5,0>: Cost 3 vsldoi4 <1,5,4,5>, LHS - 4036158615U, // <5,4,5,1>: Cost 3 vsldoi4 <1,5,4,5>, <1,5,4,5> - 3235499278U, // <5,4,5,2>: Cost 3 vsldoi12 <2,3,4,5>, <4,5,2,3> - 4036159638U, // <5,4,5,3>: Cost 4 vsldoi4 <1,5,4,5>, <3,0,1,2> - 4036160822U, // <5,4,5,4>: Cost 3 vsldoi4 <1,5,4,5>, RHS - 2181074230U, // <5,4,5,5>: Cost 2 vmrghw <5,5,5,5>, RHS - 3223997750U, // <5,4,5,6>: Cost 2 vsldoi12 <0,4,1,5>, RHS - 3385051804U, // <5,4,5,7>: Cost 4 vmrglw <4,u,5,5>, <3,6,4,7> - 3223997768U, // <5,4,5,u>: Cost 2 vsldoi12 <0,4,1,5>, RHS - 3255585682U, // <5,4,6,0>: Cost 3 vmrghw <5,6,7,0>, <4,0,5,1> - 3376433976U, // <5,4,6,1>: Cost 3 vmrglw <3,4,5,6>, <3,u,4,1> - 3382406107U, // <5,4,6,2>: Cost 4 vmrglw <4,4,5,6>, <4,1,4,2> - 4036168194U, // <5,4,6,3>: Cost 4 vsldoi4 <1,5,4,6>, <3,4,5,6> - 3255586000U, // <5,4,6,4>: Cost 3 vmrghw <5,6,7,0>, <4,4,4,4> - 2181844278U, // <5,4,6,5>: Cost 2 vmrghw <5,6,7,0>, RHS - 3376432280U, // <5,4,6,6>: Cost 4 vmrglw <3,4,5,6>, <1,5,4,6> - 4205613942U, // <5,4,6,7>: Cost 3 vsldoi8 <7,4,5,4>, <6,7,4,5> - 2181844521U, // <5,4,6,u>: Cost 2 vmrghw <5,6,7,0>, RHS - 4189688826U, // <5,4,7,0>: Cost 4 vsldoi8 <4,7,5,4>, <7,0,1,2> - 3365822501U, // <5,4,7,1>: Cost 4 vmrglw <1,6,5,7>, <0,0,4,1> - 4211586269U, // <5,4,7,2>: Cost 4 vsldoi8 , <7,2,u,4> - 4187034891U, // <5,4,7,3>: Cost 4 vsldoi8 <4,3,5,4>, <7,3,4,5> - 4189689190U, // <5,4,7,4>: Cost 3 vsldoi8 <4,7,5,4>, <7,4,5,6> - 3383740110U, // <5,4,7,5>: Cost 3 vmrglw <4,6,5,7>, <2,3,4,5> - 3383740111U, // <5,4,7,6>: Cost 4 vmrglw <4,6,5,7>, <2,3,4,6> - 4189689423U, // <5,4,7,7>: Cost 4 vsldoi8 <4,7,5,4>, <7,7,4,5> - 4208268968U, // <5,4,7,u>: Cost 3 vsldoi8 <7,u,5,4>, <7,u,5,4> - 4036182118U, // <5,4,u,0>: Cost 3 vsldoi4 <1,5,4,u>, LHS - 4036183194U, // <5,4,u,1>: Cost 3 vsldoi4 <1,5,4,u>, <1,5,4,u> - 4054099662U, // <5,4,u,2>: Cost 3 vsldoi4 <4,5,4,u>, <2,3,4,5> - 4181722830U, // <5,4,u,3>: Cost 3 vsldoi8 <3,4,5,4>, <2,3,4,5> - 4036185398U, // <5,4,u,4>: Cost 3 vsldoi4 <1,5,4,u>, RHS - 3250834974U, // <5,4,u,5>: Cost 2 vsldoi12 <4,u,5,5>, <4,u,5,5> - 3223997993U, // <5,4,u,6>: Cost 2 vsldoi12 <0,4,1,5>, RHS - 4213578032U, // <5,4,u,7>: Cost 3 vsldoi8 , - 3223998011U, // <5,4,u,u>: Cost 2 vsldoi12 <0,4,1,5>, RHS - 3376384508U, // <5,5,0,0>: Cost 3 vmrglw <3,4,5,0>, <3,4,5,0> - 3116613734U, // <5,5,0,1>: Cost 2 vsldoi8 <4,u,5,5>, LHS - 3376384510U, // <5,5,0,2>: Cost 4 vmrglw <3,4,5,0>, <3,4,5,2> - 3376385078U, // <5,5,0,3>: Cost 4 vmrglw <3,4,5,0>, <4,2,5,3> - 3223998050U, // <5,5,0,4>: Cost 3 vsldoi12 <0,4,1,5>, <5,0,4,1> - 4194337250U, // <5,5,0,5>: Cost 3 vsldoi8 <5,5,5,5>, <0,5,u,5> - 3251540066U, // <5,5,0,6>: Cost 3 vmrghw <5,0,6,1>, <5,6,7,0> - 3376385406U, // <5,5,0,7>: Cost 4 vmrglw <3,4,5,0>, <4,6,5,7> - 3116614301U, // <5,5,0,u>: Cost 2 vsldoi8 <4,u,5,5>, LHS - 3379711189U, // <5,5,1,0>: Cost 3 vmrglw <4,0,5,1>, <4,4,5,0> - 2311278106U, // <5,5,1,1>: Cost 2 vmrglw <4,u,5,1>, <4,u,5,1> - 4190356374U, // <5,5,1,2>: Cost 3 vsldoi8 <4,u,5,5>, <1,2,3,0> - 4169122814U, // <5,5,1,3>: Cost 4 vsldoi8 <1,3,5,5>, <1,3,5,5> - 3252088503U, // <5,5,1,4>: Cost 3 vsldoi12 <5,1,4,5>, <5,1,4,5> - 3385019610U, // <5,5,1,5>: Cost 3 vmrglw <4,u,5,1>, <4,4,5,5> - 3385018882U, // <5,5,1,6>: Cost 3 vmrglw <4,u,5,1>, <3,4,5,6> - 3385017587U, // <5,5,1,7>: Cost 4 vmrglw <4,u,5,1>, <1,6,5,7> - 2311278106U, // <5,5,1,u>: Cost 2 vmrglw <4,u,5,1>, <4,u,5,1> - 3376400892U, // <5,5,2,0>: Cost 4 vmrglw <3,4,5,2>, <3,4,5,0> - 3223998187U, // <5,5,2,1>: Cost 4 vsldoi12 <0,4,1,5>, <5,2,1,3> - 3376400894U, // <5,5,2,2>: Cost 3 vmrglw <3,4,5,2>, <3,4,5,2> - 3235499774U, // <5,5,2,3>: Cost 3 vsldoi12 <2,3,4,5>, <5,2,3,4> - 3235499782U, // <5,5,2,4>: Cost 4 vsldoi12 <2,3,4,5>, <5,2,4,3> - 3250835215U, // <5,5,2,5>: Cost 3 vsldoi12 <4,u,5,5>, <5,2,5,3> - 4190357434U, // <5,5,2,6>: Cost 3 vsldoi8 <4,u,5,5>, <2,6,3,7> - 3376401790U, // <5,5,2,7>: Cost 4 vmrglw <3,4,5,2>, <4,6,5,7> - 3238817579U, // <5,5,2,u>: Cost 3 vsldoi12 <2,u,4,5>, <5,2,u,4> - 4190357654U, // <5,5,3,0>: Cost 3 vsldoi8 <4,u,5,5>, <3,0,1,2> - 4167796970U, // <5,5,3,1>: Cost 4 vsldoi8 <1,1,5,5>, <3,1,1,5> - 3235499845U, // <5,5,3,2>: Cost 4 vsldoi12 <2,3,4,5>, <5,3,2,3> - 3363136427U, // <5,5,3,3>: Cost 3 vmrglw <1,2,5,3>, <1,2,5,3> - 4190358018U, // <5,5,3,4>: Cost 3 vsldoi8 <4,u,5,5>, <3,4,5,6> - 3387026974U, // <5,5,3,5>: Cost 3 vmrglw <5,2,5,3>, <4,u,5,5> - 3363138050U, // <5,5,3,6>: Cost 4 vmrglw <1,2,5,3>, <3,4,5,6> - 3363136755U, // <5,5,3,7>: Cost 4 vmrglw <1,2,5,3>, <1,6,5,7> - 4190358302U, // <5,5,3,u>: Cost 3 vsldoi8 <4,u,5,5>, <3,u,1,2> - 4190358418U, // <5,5,4,0>: Cost 3 vsldoi8 <4,u,5,5>, <4,0,5,1> - 3223998351U, // <5,5,4,1>: Cost 4 vsldoi12 <0,4,1,5>, <5,4,1,5> - 3235499928U, // <5,5,4,2>: Cost 4 vsldoi12 <2,3,4,5>, <5,4,2,5> - 3376417846U, // <5,5,4,3>: Cost 4 vmrglw <3,4,5,4>, <4,2,5,3> - 3113962714U, // <5,5,4,4>: Cost 2 vsldoi8 <4,4,5,5>, <4,4,5,5> - 3116617014U, // <5,5,4,5>: Cost 2 vsldoi8 <4,u,5,5>, RHS - 3384382822U, // <5,5,4,6>: Cost 3 vmrglw <4,7,5,4>, <7,4,5,6> - 3376418174U, // <5,5,4,7>: Cost 4 vmrglw <3,4,5,4>, <4,6,5,7> - 3116617246U, // <5,5,4,u>: Cost 2 vsldoi8 <4,u,5,5>, <4,u,5,5> - 2986377318U, // <5,5,5,0>: Cost 2 vsldoi4 <5,5,5,5>, LHS - 3385052050U, // <5,5,5,1>: Cost 3 vmrglw <4,u,5,5>, <4,0,5,1> - 4190359311U, // <5,5,5,2>: Cost 3 vsldoi8 <4,u,5,5>, <5,2,5,3> - 3385052943U, // <5,5,5,3>: Cost 3 vmrglw <4,u,5,5>, <5,2,5,3> - 2986380598U, // <5,5,5,4>: Cost 2 vsldoi4 <5,5,5,5>, RHS - 1504103734U, // <5,5,5,5>: Cost 1 vspltisw1 RHS - 3385051650U, // <5,5,5,6>: Cost 3 vmrglw <4,u,5,5>, <3,4,5,6> - 3385053271U, // <5,5,5,7>: Cost 3 vmrglw <4,u,5,5>, <5,6,5,7> - 1504103734U, // <5,5,5,u>: Cost 1 vspltisw1 RHS - 3255586420U, // <5,5,6,0>: Cost 3 vmrghw <5,6,7,0>, <5,0,6,1> - 3400321938U, // <5,5,6,1>: Cost 3 vmrglw <7,4,5,6>, <4,0,5,1> - 4190360058U, // <5,5,6,2>: Cost 3 vsldoi8 <4,u,5,5>, <6,2,7,3> - 4036241922U, // <5,5,6,3>: Cost 4 vsldoi4 <1,5,5,6>, <3,4,5,6> - 3255406668U, // <5,5,6,4>: Cost 3 vsldoi12 <5,6,4,5>, <5,6,4,5> - 3250835543U, // <5,5,6,5>: Cost 3 vsldoi12 <4,u,5,5>, <5,6,5,7> - 2302691842U, // <5,5,6,6>: Cost 2 vmrglw <3,4,5,6>, <3,4,5,6> - 4190360398U, // <5,5,6,7>: Cost 3 vsldoi8 <4,u,5,5>, <6,7,0,1> - 2302691842U, // <5,5,6,u>: Cost 2 vmrglw <3,4,5,6>, <3,4,5,6> - 4190360570U, // <5,5,7,0>: Cost 3 vsldoi8 <4,u,5,5>, <7,0,1,2> - 3383741330U, // <5,5,7,1>: Cost 4 vmrglw <4,6,5,7>, <4,0,5,1> - 4054165198U, // <5,5,7,2>: Cost 4 vsldoi4 <4,5,5,7>, <2,3,4,5> - 3365823403U, // <5,5,7,3>: Cost 4 vmrglw <1,6,5,7>, <1,2,5,3> - 4190360934U, // <5,5,7,4>: Cost 3 vsldoi8 <4,u,5,5>, <7,4,5,6> - 4194342326U, // <5,5,7,5>: Cost 3 vsldoi8 <5,5,5,5>, <7,5,5,5> - 3365825026U, // <5,5,7,6>: Cost 4 vmrglw <1,6,5,7>, <3,4,5,6> - 3365823731U, // <5,5,7,7>: Cost 3 vmrglw <1,6,5,7>, <1,6,5,7> - 4190361218U, // <5,5,7,u>: Cost 3 vsldoi8 <4,u,5,5>, <7,u,1,2> - 2986377318U, // <5,5,u,0>: Cost 2 vsldoi4 <5,5,5,5>, LHS - 3116619566U, // <5,5,u,1>: Cost 2 vsldoi8 <4,u,5,5>, LHS - 4190361477U, // <5,5,u,2>: Cost 3 vsldoi8 <4,u,5,5>, - 4190361532U, // <5,5,u,3>: Cost 3 vsldoi8 <4,u,5,5>, - 2986380598U, // <5,5,u,4>: Cost 2 vsldoi4 <5,5,5,5>, RHS - 1504103734U, // <5,5,u,5>: Cost 1 vspltisw1 RHS - 2302691842U, // <5,5,u,6>: Cost 2 vmrglw <3,4,5,6>, <3,4,5,6> - 4190361856U, // <5,5,u,7>: Cost 3 vsldoi8 <4,u,5,5>, - 1504103734U, // <5,5,u,u>: Cost 1 vspltisw1 RHS - 4181737472U, // <5,6,0,0>: Cost 3 vsldoi8 <3,4,5,6>, <0,0,0,0> - 3107995750U, // <5,6,0,1>: Cost 2 vsldoi8 <3,4,5,6>, LHS - 4175765677U, // <5,6,0,2>: Cost 4 vsldoi8 <2,4,5,6>, <0,2,1,2> - 4181737728U, // <5,6,0,3>: Cost 3 vsldoi8 <3,4,5,6>, <0,3,1,4> - 4181737810U, // <5,6,0,4>: Cost 3 vsldoi8 <3,4,5,6>, <0,4,1,5> - 4181737892U, // <5,6,0,5>: Cost 4 vsldoi8 <3,4,5,6>, <0,5,1,6> - 4181737974U, // <5,6,0,6>: Cost 4 vsldoi8 <3,4,5,6>, <0,6,1,7> - 3376385334U, // <5,6,0,7>: Cost 3 vmrglw <3,4,5,0>, RHS - 3107996317U, // <5,6,0,u>: Cost 2 vsldoi8 <3,4,5,6>, LHS - 4169794276U, // <5,6,1,0>: Cost 4 vsldoi8 <1,4,5,6>, <1,0,1,2> - 4181738292U, // <5,6,1,1>: Cost 3 vsldoi8 <3,4,5,6>, <1,1,1,1> - 4181738390U, // <5,6,1,2>: Cost 3 vsldoi8 <3,4,5,6>, <1,2,3,0> - 4181738466U, // <5,6,1,3>: Cost 4 vsldoi8 <3,4,5,6>, <1,3,2,4> - 4169794640U, // <5,6,1,4>: Cost 3 vsldoi8 <1,4,5,6>, <1,4,5,6> - 4170458273U, // <5,6,1,5>: Cost 4 vsldoi8 <1,5,5,6>, <1,5,5,6> - 3385021240U, // <5,6,1,6>: Cost 3 vmrglw <4,u,5,1>, <6,6,6,6> - 2311277878U, // <5,6,1,7>: Cost 2 vmrglw <4,u,5,1>, RHS - 2311277879U, // <5,6,1,u>: Cost 2 vmrglw <4,u,5,1>, RHS - 4175766973U, // <5,6,2,0>: Cost 4 vsldoi8 <2,4,5,6>, <2,0,1,2> - 4181739039U, // <5,6,2,1>: Cost 4 vsldoi8 <3,4,5,6>, <2,1,3,1> - 4175767144U, // <5,6,2,2>: Cost 3 vsldoi8 <2,4,5,6>, <2,2,2,2> - 4181739174U, // <5,6,2,3>: Cost 3 vsldoi8 <3,4,5,6>, <2,3,0,1> - 4175767337U, // <5,6,2,4>: Cost 3 vsldoi8 <2,4,5,6>, <2,4,5,6> - 4181739368U, // <5,6,2,5>: Cost 3 vsldoi8 <3,4,5,6>, <2,5,3,6> - 4181739450U, // <5,6,2,6>: Cost 3 vsldoi8 <3,4,5,6>, <2,6,3,7> - 3376401718U, // <5,6,2,7>: Cost 3 vmrglw <3,4,5,2>, RHS - 4178421869U, // <5,6,2,u>: Cost 3 vsldoi8 <2,u,5,6>, <2,u,5,6> - 4181739670U, // <5,6,3,0>: Cost 3 vsldoi8 <3,4,5,6>, <3,0,1,2> - 4169795845U, // <5,6,3,1>: Cost 4 vsldoi8 <1,4,5,6>, <3,1,4,5> - 4175767873U, // <5,6,3,2>: Cost 4 vsldoi8 <2,4,5,6>, <3,2,2,2> - 4181739932U, // <5,6,3,3>: Cost 3 vsldoi8 <3,4,5,6>, <3,3,3,3> - 3107998210U, // <5,6,3,4>: Cost 2 vsldoi8 <3,4,5,6>, <3,4,5,6> - 3238965821U, // <5,6,3,5>: Cost 4 vsldoi12 <2,u,6,5>, <6,3,5,7> - 4181740146U, // <5,6,3,6>: Cost 4 vsldoi8 <3,4,5,6>, <3,6,0,1> - 3363138870U, // <5,6,3,7>: Cost 3 vmrglw <1,2,5,3>, RHS - 3110652742U, // <5,6,3,u>: Cost 2 vsldoi8 <3,u,5,6>, <3,u,5,6> - 4054212710U, // <5,6,4,0>: Cost 3 vsldoi4 <4,5,6,4>, LHS - 4181740490U, // <5,6,4,1>: Cost 4 vsldoi8 <3,4,5,6>, <4,1,2,3> - 3259904625U, // <5,6,4,2>: Cost 3 vsldoi12 <6,4,2,5>, <6,4,2,5> - 4054215170U, // <5,6,4,3>: Cost 3 vsldoi4 <4,5,6,4>, <3,4,5,6> - 4187712731U, // <5,6,4,4>: Cost 3 vsldoi8 <4,4,5,6>, <4,4,5,6> - 3107999030U, // <5,6,4,5>: Cost 2 vsldoi8 <3,4,5,6>, RHS - 4189039997U, // <5,6,4,6>: Cost 3 vsldoi8 <4,6,5,6>, <4,6,5,6> - 3376418102U, // <5,6,4,7>: Cost 3 vmrglw <3,4,5,4>, RHS - 3107999273U, // <5,6,4,u>: Cost 2 vsldoi8 <3,4,5,6>, RHS - 3238965932U, // <5,6,5,0>: Cost 4 vsldoi12 <2,u,6,5>, <6,5,0,1> - 4169797317U, // <5,6,5,1>: Cost 4 vsldoi8 <1,4,5,6>, <5,1,6,1> - 4181741336U, // <5,6,5,2>: Cost 3 vsldoi8 <3,4,5,6>, <5,2,6,3> - 4181741391U, // <5,6,5,3>: Cost 4 vsldoi8 <3,4,5,6>, <5,3,3,4> - 4193685428U, // <5,6,5,4>: Cost 3 vsldoi8 <5,4,5,6>, <5,4,5,6> - 4181741582U, // <5,6,5,5>: Cost 3 vsldoi8 <3,4,5,6>, <5,5,6,6> - 4181741604U, // <5,6,5,6>: Cost 3 vsldoi8 <3,4,5,6>, <5,6,0,1> - 2311310646U, // <5,6,5,7>: Cost 2 vmrglw <4,u,5,5>, RHS - 2311310647U, // <5,6,5,u>: Cost 2 vmrglw <4,u,5,5>, RHS - 4060201062U, // <5,6,6,0>: Cost 3 vsldoi4 <5,5,6,6>, LHS - 3364490949U, // <5,6,6,1>: Cost 4 vmrglw <1,4,5,6>, <5,1,6,1> - 3255587322U, // <5,6,6,2>: Cost 3 vmrghw <5,6,7,0>, <6,2,7,3> - 3376434968U, // <5,6,6,3>: Cost 3 vmrglw <3,4,5,6>, <5,2,6,3> - 4060204342U, // <5,6,6,4>: Cost 3 vsldoi4 <5,5,6,6>, RHS - 4060205070U, // <5,6,6,5>: Cost 3 vsldoi4 <5,5,6,6>, <5,5,6,6> - 3376435214U, // <5,6,6,6>: Cost 3 vmrglw <3,4,5,6>, <5,5,6,6> - 2302692662U, // <5,6,6,7>: Cost 2 vmrglw <3,4,5,6>, RHS - 2302692663U, // <5,6,6,u>: Cost 2 vmrglw <3,4,5,6>, RHS - 1906753638U, // <5,6,7,0>: Cost 1 vsldoi4 RHS, LHS - 2980496180U, // <5,6,7,1>: Cost 2 vsldoi4 RHS, <1,1,1,1> - 2980497000U, // <5,6,7,2>: Cost 2 vsldoi4 RHS, <2,2,2,2> - 2980497558U, // <5,6,7,3>: Cost 2 vsldoi4 RHS, <3,0,1,2> - 1906756918U, // <5,6,7,4>: Cost 1 vsldoi4 RHS, RHS - 2980499460U, // <5,6,7,5>: Cost 2 vsldoi4 RHS, <5,5,5,5> - 2980499962U, // <5,6,7,6>: Cost 2 vsldoi4 RHS, <6,2,7,3> - 2980501100U, // <5,6,7,7>: Cost 2 vsldoi4 RHS, <7,7,7,7> - 1906759470U, // <5,6,7,u>: Cost 1 vsldoi4 RHS, LHS - 1906761830U, // <5,6,u,0>: Cost 1 vsldoi4 RHS, LHS - 3108001582U, // <5,6,u,1>: Cost 2 vsldoi8 <3,4,5,6>, LHS - 2980505192U, // <5,6,u,2>: Cost 2 vsldoi4 RHS, <2,2,2,2> - 2980505750U, // <5,6,u,3>: Cost 2 vsldoi4 RHS, <3,0,1,2> - 1906765111U, // <5,6,u,4>: Cost 1 vsldoi4 RHS, RHS - 3108001946U, // <5,6,u,5>: Cost 2 vsldoi8 <3,4,5,6>, RHS - 2980508154U, // <5,6,u,6>: Cost 2 vsldoi4 RHS, <6,2,7,3> - 2302709046U, // <5,6,u,7>: Cost 2 vmrglw <3,4,5,u>, RHS - 1906767662U, // <5,6,u,u>: Cost 1 vsldoi4 RHS, LHS - 4171128832U, // <5,7,0,0>: Cost 4 vsldoi8 <1,6,5,7>, <0,0,0,0> - 4171128934U, // <5,7,0,1>: Cost 3 vsldoi8 <1,6,5,7>, LHS - 4054255715U, // <5,7,0,2>: Cost 4 vsldoi4 <4,5,7,0>, <2,u,4,5> - 3384349178U, // <5,7,0,3>: Cost 4 vmrglw <4,7,5,0>, <6,2,7,3> - 4171129170U, // <5,7,0,4>: Cost 3 vsldoi8 <1,6,5,7>, <0,4,1,5> - 3384347884U, // <5,7,0,5>: Cost 4 vmrglw <4,7,5,0>, <4,4,7,5> - 4066202346U, // <5,7,0,6>: Cost 4 vsldoi4 <6,5,7,0>, <6,5,7,0> - 4054258682U, // <5,7,0,7>: Cost 4 vsldoi4 <4,5,7,0>, <7,0,1,2> - 4171129501U, // <5,7,0,u>: Cost 3 vsldoi8 <1,6,5,7>, LHS - 3385020514U, // <5,7,1,0>: Cost 3 vmrglw <4,u,5,1>, <5,6,7,0> - 3379712747U, // <5,7,1,1>: Cost 3 vmrglw <4,0,5,1>, <6,5,7,1> - 4171129750U, // <5,7,1,2>: Cost 4 vsldoi8 <1,6,5,7>, <1,2,3,0> - 3385020922U, // <5,7,1,3>: Cost 3 vmrglw <4,u,5,1>, <6,2,7,3> - 3385020518U, // <5,7,1,4>: Cost 3 vmrglw <4,u,5,1>, <5,6,7,4> - 4171129967U, // <5,7,1,5>: Cost 4 vsldoi8 <1,6,5,7>, <1,5,0,1> - 4171130099U, // <5,7,1,6>: Cost 3 vsldoi8 <1,6,5,7>, <1,6,5,7> - 3385021250U, // <5,7,1,7>: Cost 3 vmrglw <4,u,5,1>, <6,6,7,7> - 4172457365U, // <5,7,1,u>: Cost 3 vsldoi8 <1,u,5,7>, <1,u,5,7> - 3383701602U, // <5,7,2,0>: Cost 4 vmrglw <4,6,5,2>, <5,6,7,0> - 4171130403U, // <5,7,2,1>: Cost 4 vsldoi8 <1,6,5,7>, <2,1,3,5> - 4171130472U, // <5,7,2,2>: Cost 4 vsldoi8 <1,6,5,7>, <2,2,2,2> - 3383702010U, // <5,7,2,3>: Cost 3 vmrglw <4,6,5,2>, <6,2,7,3> - 3383701606U, // <5,7,2,4>: Cost 4 vmrglw <4,6,5,2>, <5,6,7,4> - 4171130729U, // <5,7,2,5>: Cost 4 vsldoi8 <1,6,5,7>, <2,5,3,7> - 4169140154U, // <5,7,2,6>: Cost 4 vsldoi8 <1,3,5,7>, <2,6,3,7> - 3383702338U, // <5,7,2,7>: Cost 4 vmrglw <4,6,5,2>, <6,6,7,7> - 3383702010U, // <5,7,2,u>: Cost 3 vmrglw <4,6,5,2>, <6,2,7,3> - 4171131030U, // <5,7,3,0>: Cost 4 vsldoi8 <1,6,5,7>, <3,0,1,2> - 4171131159U, // <5,7,3,1>: Cost 4 vsldoi8 <1,6,5,7>, <3,1,6,5> - 4189047116U, // <5,7,3,2>: Cost 4 vsldoi8 <4,6,5,7>, <3,2,3,4> - 4171131292U, // <5,7,3,3>: Cost 4 vsldoi8 <1,6,5,7>, <3,3,3,3> - 3265361163U, // <5,7,3,4>: Cost 3 vsldoi12 <7,3,4,5>, <7,3,4,5> - 3385037470U, // <5,7,3,5>: Cost 4 vmrglw <4,u,5,3>, <6,4,7,5> - 4183075493U, // <5,7,3,6>: Cost 4 vsldoi8 <3,6,5,7>, <3,6,5,7> - 3244127525U, // <5,7,3,7>: Cost 4 vsldoi12 <3,7,4,5>, <7,3,7,4> - 3265656111U, // <5,7,3,u>: Cost 3 vsldoi12 <7,3,u,5>, <7,3,u,5> - 3265729848U, // <5,7,4,0>: Cost 3 vsldoi12 <7,4,0,5>, <7,4,0,5> - 4171131874U, // <5,7,4,1>: Cost 4 vsldoi8 <1,6,5,7>, <4,1,5,0> - 4054288483U, // <5,7,4,2>: Cost 4 vsldoi4 <4,5,7,4>, <2,u,4,5> - 4187057291U, // <5,7,4,3>: Cost 4 vsldoi8 <4,3,5,7>, <4,3,5,7> - 3266024796U, // <5,7,4,4>: Cost 3 vsldoi12 <7,4,4,5>, <7,4,4,5> - 4171132214U, // <5,7,4,5>: Cost 3 vsldoi8 <1,6,5,7>, RHS - 4189048190U, // <5,7,4,6>: Cost 3 vsldoi8 <4,6,5,7>, <4,6,5,7> - 4189711823U, // <5,7,4,7>: Cost 3 vsldoi8 <4,7,5,7>, <4,7,5,7> - 4171132457U, // <5,7,4,u>: Cost 3 vsldoi8 <1,6,5,7>, RHS - 3385053282U, // <5,7,5,0>: Cost 3 vmrglw <4,u,5,5>, <5,6,7,0> - 4171132617U, // <5,7,5,1>: Cost 4 vsldoi8 <1,6,5,7>, <5,1,6,5> - 4171132705U, // <5,7,5,2>: Cost 4 vsldoi8 <1,6,5,7>, <5,2,7,3> - 3385053690U, // <5,7,5,3>: Cost 3 vmrglw <4,u,5,5>, <6,2,7,3> - 3385053286U, // <5,7,5,4>: Cost 3 vmrglw <4,u,5,5>, <5,6,7,4> - 3254818230U, // <5,7,5,5>: Cost 3 vmrghw <5,5,5,5>, <7,5,5,5> - 4195020887U, // <5,7,5,6>: Cost 3 vsldoi8 <5,6,5,7>, <5,6,5,7> - 3385054018U, // <5,7,5,7>: Cost 3 vmrglw <4,u,5,5>, <6,6,7,7> - 3385053290U, // <5,7,5,u>: Cost 3 vmrglw <4,u,5,5>, <5,6,7,u> - 3255587834U, // <5,7,6,0>: Cost 3 vmrghw <5,6,7,0>, <7,0,1,2> - 3255587914U, // <5,7,6,1>: Cost 4 vmrghw <5,6,7,0>, <7,1,1,1> - 3255587988U, // <5,7,6,2>: Cost 3 vmrghw <5,6,7,0>, <7,2,0,3> - 4066249218U, // <5,7,6,3>: Cost 3 vsldoi4 <6,5,7,6>, <3,4,5,6> - 3255588198U, // <5,7,6,4>: Cost 3 vmrghw <5,6,7,0>, <7,4,5,6> - 3255588289U, // <5,7,6,5>: Cost 3 vmrghw <5,6,7,0>, <7,5,6,7> - 4066251504U, // <5,7,6,6>: Cost 3 vsldoi4 <6,5,7,6>, <6,5,7,6> - 3255588460U, // <5,7,6,7>: Cost 3 vmrghw <5,6,7,0>, <7,7,7,7> - 3255588482U, // <5,7,6,u>: Cost 3 vmrghw <5,6,7,0>, <7,u,1,2> - 4054311014U, // <5,7,7,0>: Cost 4 vsldoi4 <4,5,7,7>, LHS - 4060284147U, // <5,7,7,1>: Cost 4 vsldoi4 <5,5,7,7>, <1,6,5,7> - 4054313059U, // <5,7,7,2>: Cost 4 vsldoi4 <4,5,7,7>, <2,u,4,5> - 3365826337U, // <5,7,7,3>: Cost 4 vmrglw <1,6,5,7>, <5,2,7,3> - 3268015695U, // <5,7,7,4>: Cost 3 vsldoi12 <7,7,4,5>, <7,7,4,5> - 3365826258U, // <5,7,7,5>: Cost 4 vmrglw <1,6,5,7>, <5,1,7,5> - 4066259697U, // <5,7,7,6>: Cost 4 vsldoi4 <6,5,7,7>, <6,5,7,7> - 3384407660U, // <5,7,7,7>: Cost 3 vmrglw <4,7,5,7>, <7,7,7,7> - 3268310643U, // <5,7,7,u>: Cost 3 vsldoi12 <7,7,u,5>, <7,7,u,5> - 3385077858U, // <5,7,u,0>: Cost 3 vmrglw <4,u,5,u>, <5,6,7,0> - 4171134766U, // <5,7,u,1>: Cost 3 vsldoi8 <1,6,5,7>, LHS - 3255587988U, // <5,7,u,2>: Cost 3 vmrghw <5,6,7,0>, <7,2,0,3> - 3385078266U, // <5,7,u,3>: Cost 3 vmrglw <4,u,5,u>, <6,2,7,3> - 3385077862U, // <5,7,u,4>: Cost 3 vmrglw <4,u,5,u>, <5,6,7,4> - 4171135130U, // <5,7,u,5>: Cost 3 vsldoi8 <1,6,5,7>, RHS - 4066267890U, // <5,7,u,6>: Cost 3 vsldoi4 <6,5,7,u>, <6,5,7,u> - 3385078594U, // <5,7,u,7>: Cost 3 vmrglw <4,u,5,u>, <6,6,7,7> - 4171135333U, // <5,7,u,u>: Cost 3 vsldoi8 <1,6,5,7>, LHS - 4181753856U, // <5,u,0,0>: Cost 3 vsldoi8 <3,4,5,u>, <0,0,0,0> - 3108012134U, // <5,u,0,1>: Cost 2 vsldoi8 <3,4,5,u>, LHS - 3384349690U, // <5,u,0,2>: Cost 3 vmrglw <4,7,5,0>, <7,0,1,2> - 3376382108U, // <5,u,0,3>: Cost 3 vmrglw <3,4,5,0>, LHS - 3224000237U, // <5,u,0,4>: Cost 3 vsldoi12 <0,4,1,5>, - 3379037938U, // <5,u,0,5>: Cost 3 vmrglw <3,u,5,0>, <2,3,u,5> - 3251540066U, // <5,u,0,6>: Cost 3 vmrghw <5,0,6,1>, <5,6,7,0> - 3376385352U, // <5,u,0,7>: Cost 3 vmrglw <3,4,5,0>, RHS - 3108012701U, // <5,u,0,u>: Cost 2 vsldoi8 <3,4,5,u>, LHS - 4036419686U, // <5,u,1,0>: Cost 3 vsldoi4 <1,5,u,1>, LHS - 2311278106U, // <5,u,1,1>: Cost 2 vmrglw <4,u,5,1>, <4,u,5,1> - 3224000302U, // <5,u,1,2>: Cost 2 vsldoi12 <0,4,1,5>, LHS - 2311274652U, // <5,u,1,3>: Cost 2 vmrglw <4,u,5,1>, LHS - 4169811026U, // <5,u,1,4>: Cost 3 vsldoi8 <1,4,5,u>, <1,4,5,u> - 3226654534U, // <5,u,1,5>: Cost 3 vsldoi12 <0,u,1,5>, - 4171138292U, // <5,u,1,6>: Cost 3 vsldoi8 <1,6,5,u>, <1,6,5,u> - 2311277896U, // <5,u,1,7>: Cost 2 vmrglw <4,u,5,1>, RHS - 3224000356U, // <5,u,1,u>: Cost 2 vsldoi12 <0,4,1,5>, LHS - 3385030533U, // <5,u,2,0>: Cost 3 vmrglw <4,u,5,2>, - 3252516654U, // <5,u,2,1>: Cost 3 vmrghw <5,2,1,3>, LHS - 4175783528U, // <5,u,2,2>: Cost 3 vsldoi8 <2,4,5,u>, <2,2,2,2> - 3224000392U, // <5,u,2,3>: Cost 3 vsldoi12 <0,4,1,5>, - 4175783723U, // <5,u,2,4>: Cost 3 vsldoi8 <2,4,5,u>, <2,4,5,u> - 3227170714U, // <5,u,2,5>: Cost 3 vsldoi12 <0,u,u,5>, - 4181755834U, // <5,u,2,6>: Cost 3 vsldoi8 <3,4,5,u>, <2,6,3,7> - 3376401736U, // <5,u,2,7>: Cost 3 vmrglw <3,4,5,2>, RHS - 3224000437U, // <5,u,2,u>: Cost 3 vsldoi12 <0,4,1,5>, - 3224000444U, // <5,u,3,0>: Cost 3 vsldoi12 <0,4,1,5>, - 3224000453U, // <5,u,3,1>: Cost 4 vsldoi12 <0,4,1,5>, - 4053911246U, // <5,u,3,2>: Cost 3 vsldoi4 <4,5,2,3>, <2,3,4,5> - 3363135644U, // <5,u,3,3>: Cost 3 vmrglw <1,2,5,3>, LHS - 3108014596U, // <5,u,3,4>: Cost 2 vsldoi8 <3,4,5,u>, <3,4,5,u> - 3254818797U, // <5,u,3,5>: Cost 3 vsldoi12 <5,5,5,5>, - 3363138077U, // <5,u,3,6>: Cost 4 vmrglw <1,2,5,3>, <3,4,u,6> - 3363138888U, // <5,u,3,7>: Cost 3 vmrglw <1,2,5,3>, RHS - 3110669128U, // <5,u,3,u>: Cost 2 vsldoi8 <3,u,5,u>, <3,u,5,u> - 3111332761U, // <5,u,4,0>: Cost 2 vsldoi8 <4,0,5,u>, <4,0,5,u> - 3271776282U, // <5,u,4,1>: Cost 2 vsldoi12 , - 4186401851U, // <5,u,4,2>: Cost 3 vsldoi8 <4,2,5,u>, <4,2,5,u> - 3235502124U, // <5,u,4,3>: Cost 3 vsldoi12 <2,3,4,5>, - 3113987293U, // <5,u,4,4>: Cost 2 vsldoi8 <4,4,5,u>, <4,4,5,u> - 3108015414U, // <5,u,4,5>: Cost 2 vsldoi8 <3,4,5,u>, RHS - 4189056383U, // <5,u,4,6>: Cost 3 vsldoi8 <4,6,5,u>, <4,6,5,u> - 3376418120U, // <5,u,4,7>: Cost 3 vmrglw <3,4,5,4>, RHS - 3108015657U, // <5,u,4,u>: Cost 2 vsldoi8 <3,4,5,u>, RHS - 2986377318U, // <5,u,5,0>: Cost 2 vsldoi4 <5,5,5,5>, LHS - 2181076782U, // <5,u,5,1>: Cost 2 vmrghw <5,5,5,5>, LHS - 3235797106U, // <5,u,5,2>: Cost 3 vsldoi12 <2,3,u,5>, - 2311307420U, // <5,u,5,3>: Cost 2 vmrglw <4,u,5,5>, LHS - 2986380598U, // <5,u,5,4>: Cost 2 vsldoi4 <5,5,5,5>, RHS - 1504103734U, // <5,u,5,5>: Cost 1 vspltisw1 RHS - 3224000666U, // <5,u,5,6>: Cost 2 vsldoi12 <0,4,1,5>, RHS - 2311310664U, // <5,u,5,7>: Cost 2 vmrglw <4,u,5,5>, RHS - 1504103734U, // <5,u,5,u>: Cost 1 vspltisw1 RHS - 4042432614U, // <5,u,6,0>: Cost 3 vsldoi4 <2,5,u,6>, LHS - 2181846830U, // <5,u,6,1>: Cost 2 vmrghw <5,6,7,0>, LHS - 4042434453U, // <5,u,6,2>: Cost 3 vsldoi4 <2,5,u,6>, <2,5,u,6> - 2302689436U, // <5,u,6,3>: Cost 2 vmrglw <3,4,5,6>, LHS - 4042435894U, // <5,u,6,4>: Cost 3 vsldoi4 <2,5,u,6>, RHS - 2181847194U, // <5,u,6,5>: Cost 2 vmrghw <5,6,7,0>, RHS - 2302691842U, // <5,u,6,6>: Cost 2 vmrglw <3,4,5,6>, <3,4,5,6> - 2302692680U, // <5,u,6,7>: Cost 2 vmrglw <3,4,5,6>, RHS - 2302689441U, // <5,u,6,u>: Cost 2 vmrglw <3,4,5,6>, LHS - 1906901094U, // <5,u,7,0>: Cost 1 vsldoi4 RHS, LHS - 2980643636U, // <5,u,7,1>: Cost 2 vsldoi4 RHS, <1,1,1,1> - 2980644456U, // <5,u,7,2>: Cost 2 vsldoi4 RHS, <2,2,2,2> - 2980645014U, // <5,u,7,3>: Cost 2 vsldoi4 RHS, <3,0,1,2> - 1906904392U, // <5,u,7,4>: Cost 1 vsldoi4 RHS, RHS - 2980646916U, // <5,u,7,5>: Cost 2 vsldoi4 RHS, <5,5,5,5> - 2980647418U, // <5,u,7,6>: Cost 2 vsldoi4 RHS, <6,2,7,3> - 2980647930U, // <5,u,7,7>: Cost 2 vsldoi4 RHS, <7,0,1,2> - 1906906926U, // <5,u,7,u>: Cost 1 vsldoi4 RHS, LHS - 1906909286U, // <5,u,u,0>: Cost 1 vsldoi4 RHS, LHS - 3108017966U, // <5,u,u,1>: Cost 2 vsldoi8 <3,4,5,u>, LHS - 3224000869U, // <5,u,u,2>: Cost 2 vsldoi12 <0,4,1,5>, LHS - 2302705820U, // <5,u,u,3>: Cost 2 vmrglw <3,4,5,u>, LHS - 1906912585U, // <5,u,u,4>: Cost 1 vsldoi4 RHS, RHS - 1504103734U, // <5,u,u,5>: Cost 1 vspltisw1 RHS - 3224000909U, // <5,u,u,6>: Cost 2 vsldoi12 <0,4,1,5>, RHS - 2302709064U, // <5,u,u,7>: Cost 2 vmrglw <3,4,5,u>, RHS - 1906915118U, // <5,u,u,u>: Cost 1 vsldoi4 RHS, LHS - 3242213376U, // <6,0,0,0>: Cost 3 vsldoi12 <3,4,5,6>, <0,0,0,0> - 3242213386U, // <6,0,0,1>: Cost 3 vsldoi12 <3,4,5,6>, <0,0,1,1> - 4173799601U, // <6,0,0,2>: Cost 4 vsldoi8 <2,1,6,0>, <0,2,1,6> - 3383095739U, // <6,0,0,3>: Cost 4 vmrglw <4,5,6,0>, <6,2,0,3> - 3242213413U, // <6,0,0,4>: Cost 4 vsldoi12 <3,4,5,6>, <0,0,4,1> - 4060377123U, // <6,0,0,5>: Cost 4 vsldoi4 <5,6,0,0>, <5,6,0,0> - 3383095985U, // <6,0,0,6>: Cost 4 vmrglw <4,5,6,0>, <6,5,0,6> - 3383096067U, // <6,0,0,7>: Cost 4 vmrglw <4,5,6,0>, <6,6,0,7> - 3242213449U, // <6,0,0,u>: Cost 3 vsldoi12 <3,4,5,6>, <0,0,u,1> - 4060381286U, // <6,0,1,0>: Cost 3 vsldoi4 <5,6,0,1>, LHS - 3258245222U, // <6,0,1,1>: Cost 3 vmrghw <6,1,7,1>, LHS - 3242213478U, // <6,0,1,2>: Cost 2 vsldoi12 <3,4,5,6>, LHS - 4060383746U, // <6,0,1,3>: Cost 3 vsldoi4 <5,6,0,1>, <3,4,5,6> - 4060384566U, // <6,0,1,4>: Cost 3 vsldoi4 <5,6,0,1>, RHS - 4060385316U, // <6,0,1,5>: Cost 3 vsldoi4 <5,6,0,1>, <5,6,0,1> - 4066358013U, // <6,0,1,6>: Cost 3 vsldoi4 <6,6,0,1>, <6,6,0,1> - 4060386298U, // <6,0,1,7>: Cost 4 vsldoi4 <5,6,0,1>, <7,0,1,2> - 3242213532U, // <6,0,1,u>: Cost 2 vsldoi12 <3,4,5,6>, LHS - 3258925056U, // <6,0,2,0>: Cost 3 vmrghw <6,2,7,3>, <0,0,0,0> - 2185183334U, // <6,0,2,1>: Cost 2 vmrghw <6,2,7,3>, LHS - 3222675642U, // <6,0,2,2>: Cost 4 vsldoi12 <0,2,1,6>, <0,2,2,6> - 4180436669U, // <6,0,2,3>: Cost 4 vsldoi8 <3,2,6,0>, <2,3,2,6> - 3258925394U, // <6,0,2,4>: Cost 3 vmrghw <6,2,7,3>, <0,4,1,5> - 4188399464U, // <6,0,2,5>: Cost 4 vsldoi8 <4,5,6,0>, <2,5,3,6> - 3258925553U, // <6,0,2,6>: Cost 3 vmrghw <6,2,7,3>, <0,6,1,2> - 4072338903U, // <6,0,2,7>: Cost 4 vsldoi4 <7,6,0,2>, <7,6,0,2> - 2185183901U, // <6,0,2,u>: Cost 2 vmrghw <6,2,7,3>, LHS - 3375153152U, // <6,0,3,0>: Cost 4 vmrglw <3,2,6,3>, <0,0,0,0> - 3242213632U, // <6,0,3,1>: Cost 3 vsldoi12 <3,4,5,6>, <0,3,1,4> - 4180437347U, // <6,0,3,2>: Cost 4 vsldoi8 <3,2,6,0>, <3,2,6,0> - 3242213650U, // <6,0,3,3>: Cost 4 vsldoi12 <3,4,5,6>, <0,3,3,4> - 4188400130U, // <6,0,3,4>: Cost 3 vsldoi8 <4,5,6,0>, <3,4,5,6> - 4060401702U, // <6,0,3,5>: Cost 4 vsldoi4 <5,6,0,3>, <5,6,0,3> - 4204989048U, // <6,0,3,6>: Cost 4 vsldoi8 <7,3,6,0>, <3,6,0,7> - 4204325594U, // <6,0,3,7>: Cost 4 vsldoi8 <7,2,6,0>, <3,7,2,6> - 3242213695U, // <6,0,3,u>: Cost 3 vsldoi12 <3,4,5,6>, <0,3,u,4> - 3383123968U, // <6,0,4,0>: Cost 4 vmrglw <4,5,6,4>, <0,0,0,0> - 3242213714U, // <6,0,4,1>: Cost 3 vsldoi12 <3,4,5,6>, <0,4,1,5> - 4176456761U, // <6,0,4,2>: Cost 4 vsldoi8 <2,5,6,0>, <4,2,5,6> - 4060408322U, // <6,0,4,3>: Cost 4 vsldoi4 <5,6,0,4>, <3,4,5,6> - 3242213741U, // <6,0,4,4>: Cost 4 vsldoi12 <3,4,5,6>, <0,4,4,5> - 4188400943U, // <6,0,4,5>: Cost 3 vsldoi8 <4,5,6,0>, <4,5,6,0> - 3259900401U, // <6,0,4,6>: Cost 4 vmrghw <6,4,2,5>, <0,6,1,2> - 3383126648U, // <6,0,4,7>: Cost 5 vmrglw <4,5,6,4>, <3,6,0,7> - 3242213777U, // <6,0,4,u>: Cost 3 vsldoi12 <3,4,5,6>, <0,4,u,5> - 3373178880U, // <6,0,5,0>: Cost 4 vmrglw <2,u,6,5>, <0,0,0,0> - 3260899430U, // <6,0,5,1>: Cost 3 vmrghw <6,5,7,1>, LHS - 4188401432U, // <6,0,5,2>: Cost 4 vsldoi8 <4,5,6,0>, <5,2,6,3> - 4193046374U, // <6,0,5,3>: Cost 4 vsldoi8 <5,3,6,0>, <5,3,6,0> - 3260891474U, // <6,0,5,4>: Cost 4 vmrghw <6,5,7,0>, <0,4,1,5> - 4188401678U, // <6,0,5,5>: Cost 4 vsldoi8 <4,5,6,0>, <5,5,6,6> - 4188401700U, // <6,0,5,6>: Cost 4 vsldoi8 <4,5,6,0>, <5,6,0,1> - 3379153528U, // <6,0,5,7>: Cost 4 vmrglw <3,u,6,5>, <3,6,0,7> - 3260899997U, // <6,0,5,u>: Cost 3 vmrghw <6,5,7,1>, LHS - 3261530112U, // <6,0,6,0>: Cost 3 vmrghw <6,6,6,6>, <0,0,0,0> - 2187788390U, // <6,0,6,1>: Cost 2 vmrghw <6,6,6,6>, LHS - 4188402107U, // <6,0,6,2>: Cost 4 vsldoi8 <4,5,6,0>, <6,2,0,3> - 4188402226U, // <6,0,6,3>: Cost 4 vsldoi8 <4,5,6,0>, <6,3,4,5> - 3261530450U, // <6,0,6,4>: Cost 3 vmrghw <6,6,6,6>, <0,4,1,5> - 4188402353U, // <6,0,6,5>: Cost 4 vsldoi8 <4,5,6,0>, <6,5,0,6> - 4201009970U, // <6,0,6,6>: Cost 3 vsldoi8 <6,6,6,0>, <6,6,6,0> - 4190393166U, // <6,0,6,7>: Cost 4 vsldoi8 <4,u,6,0>, <6,7,0,1> - 2187788957U, // <6,0,6,u>: Cost 2 vmrghw <6,6,6,6>, LHS - 2309406720U, // <6,0,7,0>: Cost 2 vmrglw RHS, <0,0,0,0> - 2309408422U, // <6,0,7,1>: Cost 2 vmrglw RHS, <2,3,0,1> - 4048488040U, // <6,0,7,2>: Cost 4 vsldoi4 <3,6,0,7>, <2,2,2,2> - 4048489080U, // <6,0,7,3>: Cost 3 vsldoi4 <3,6,0,7>, <3,6,0,7> - 4048489782U, // <6,0,7,4>: Cost 3 vsldoi4 <3,6,0,7>, RHS - 3383151060U, // <6,0,7,5>: Cost 3 vmrglw RHS, <3,4,0,5> - 4048490837U, // <6,0,7,6>: Cost 4 vsldoi4 <3,6,0,7>, <6,0,7,0> - 3383151224U, // <6,0,7,7>: Cost 3 vmrglw RHS, <3,6,0,7> - 2309408429U, // <6,0,7,u>: Cost 2 vmrglw RHS, <2,3,0,u> - 2309414912U, // <6,0,u,0>: Cost 2 vmrglw RHS, <0,0,0,0> - 2309416614U, // <6,0,u,1>: Cost 2 vmrglw RHS, <2,3,0,1> - 3242214045U, // <6,0,u,2>: Cost 2 vsldoi12 <3,4,5,6>, LHS - 4048497273U, // <6,0,u,3>: Cost 3 vsldoi4 <3,6,0,u>, <3,6,0,u> - 4048497974U, // <6,0,u,4>: Cost 3 vsldoi4 <3,6,0,u>, RHS - 4188403866U, // <6,0,u,5>: Cost 3 vsldoi8 <4,5,6,0>, RHS - 4066415364U, // <6,0,u,6>: Cost 3 vsldoi4 <6,6,0,u>, <6,6,0,u> - 3383159416U, // <6,0,u,7>: Cost 3 vmrglw RHS, <3,6,0,7> - 3242214099U, // <6,0,u,u>: Cost 2 vsldoi12 <3,4,5,6>, LHS - 4178452480U, // <6,1,0,0>: Cost 4 vsldoi8 <2,u,6,1>, <0,0,0,0> - 4178452582U, // <6,1,0,1>: Cost 3 vsldoi8 <2,u,6,1>, LHS - 3373143763U, // <6,1,0,2>: Cost 4 vmrglw <2,u,6,0>, - 4030589442U, // <6,1,0,3>: Cost 4 vsldoi4 <0,6,1,0>, <3,4,5,6> - 4178452818U, // <6,1,0,4>: Cost 4 vsldoi8 <2,u,6,1>, <0,4,1,5> - 3383091538U, // <6,1,0,5>: Cost 4 vmrglw <4,5,6,0>, <0,4,1,5> - 3368493233U, // <6,1,0,6>: Cost 4 vmrglw <2,1,6,0>, <0,2,1,6> - 3362522319U, // <6,1,0,7>: Cost 5 vmrglw <1,1,6,0>, <1,6,1,7> - 4178453149U, // <6,1,0,u>: Cost 3 vsldoi8 <2,u,6,1>, LHS - 3230270251U, // <6,1,1,0>: Cost 4 vsldoi12 <1,4,5,6>, <1,1,0,1> - 3242214196U, // <6,1,1,1>: Cost 3 vsldoi12 <3,4,5,6>, <1,1,1,1> - 3228058434U, // <6,1,1,2>: Cost 4 vsldoi12 <1,1,2,6>, <1,1,2,6> - 3373150660U, // <6,1,1,3>: Cost 4 vmrglw <2,u,6,1>, <6,2,1,3> - 3230270291U, // <6,1,1,4>: Cost 4 vsldoi12 <1,4,5,6>, <1,1,4,5> - 3373146450U, // <6,1,1,5>: Cost 4 vmrglw <2,u,6,1>, <0,4,1,5> - 3222676326U, // <6,1,1,6>: Cost 4 vsldoi12 <0,2,1,6>, <1,1,6,6> - 3362530511U, // <6,1,1,7>: Cost 4 vmrglw <1,1,6,1>, <1,6,1,7> - 3242214196U, // <6,1,1,u>: Cost 3 vsldoi12 <3,4,5,6>, <1,1,1,1> - 4078379110U, // <6,1,2,0>: Cost 3 vsldoi4 , LHS - 3258925876U, // <6,1,2,1>: Cost 3 vmrghw <6,2,7,3>, <1,1,1,1> - 3258925974U, // <6,1,2,2>: Cost 3 vmrghw <6,2,7,3>, <1,2,3,0> - 3242214294U, // <6,1,2,3>: Cost 3 vsldoi12 <3,4,5,6>, <1,2,3,0> - 4078382390U, // <6,1,2,4>: Cost 3 vsldoi4 , RHS - 3242214315U, // <6,1,2,5>: Cost 4 vsldoi12 <3,4,5,6>, <1,2,5,3> - 4178454458U, // <6,1,2,6>: Cost 3 vsldoi8 <2,u,6,1>, <2,6,3,7> - 3266102202U, // <6,1,2,7>: Cost 4 vsldoi12 <7,4,5,6>, <1,2,7,0> - 4178454641U, // <6,1,2,u>: Cost 3 vsldoi8 <2,u,6,1>, <2,u,6,1> - 4178454678U, // <6,1,3,0>: Cost 4 vsldoi8 <2,u,6,1>, <3,0,1,2> - 4179781907U, // <6,1,3,1>: Cost 4 vsldoi8 <3,1,6,1>, <3,1,6,1> - 4178454886U, // <6,1,3,2>: Cost 4 vsldoi8 <2,u,6,1>, <3,2,6,3> - 4178454940U, // <6,1,3,3>: Cost 4 vsldoi8 <2,u,6,1>, <3,3,3,3> - 4178455042U, // <6,1,3,4>: Cost 4 vsldoi8 <2,u,6,1>, <3,4,5,6> - 3375153490U, // <6,1,3,5>: Cost 4 vmrglw <3,2,6,3>, <0,4,1,5> - 3222676489U, // <6,1,3,6>: Cost 4 vsldoi12 <0,2,1,6>, <1,3,6,7> - 4178455235U, // <6,1,3,7>: Cost 4 vsldoi8 <2,u,6,1>, <3,7,0,1> - 4178455326U, // <6,1,3,u>: Cost 4 vsldoi8 <2,u,6,1>, <3,u,1,2> - 3242214430U, // <6,1,4,0>: Cost 4 vsldoi12 <3,4,5,6>, <1,4,0,1> - 3242214443U, // <6,1,4,1>: Cost 4 vsldoi12 <3,4,5,6>, <1,4,1,5> - 3242214452U, // <6,1,4,2>: Cost 4 vsldoi12 <3,4,5,6>, <1,4,2,5> - 3242214460U, // <6,1,4,3>: Cost 4 vsldoi12 <3,4,5,6>, <1,4,3,4> - 3242214470U, // <6,1,4,4>: Cost 4 vsldoi12 <3,4,5,6>, <1,4,4,5> - 3230270544U, // <6,1,4,5>: Cost 3 vsldoi12 <1,4,5,6>, <1,4,5,6> - 3368526001U, // <6,1,4,6>: Cost 4 vmrglw <2,1,6,4>, <0,2,1,6> - 3266102368U, // <6,1,4,7>: Cost 4 vsldoi12 <7,4,5,6>, <1,4,7,4> - 3230491755U, // <6,1,4,u>: Cost 3 vsldoi12 <1,4,u,6>, <1,4,u,6> - 4191063668U, // <6,1,5,0>: Cost 3 vsldoi8 <5,0,6,1>, <5,0,6,1> - 3230639229U, // <6,1,5,1>: Cost 4 vsldoi12 <1,5,1,6>, <1,5,1,6> - 3230712966U, // <6,1,5,2>: Cost 4 vsldoi12 <1,5,2,6>, <1,5,2,6> - 3242214541U, // <6,1,5,3>: Cost 4 vsldoi12 <3,4,5,6>, <1,5,3,4> - 3230860440U, // <6,1,5,4>: Cost 4 vsldoi12 <1,5,4,6>, <1,5,4,6> - 3230934177U, // <6,1,5,5>: Cost 4 vsldoi12 <1,5,5,6>, <1,5,5,6> - 4196372578U, // <6,1,5,6>: Cost 3 vsldoi8 <5,u,6,1>, <5,6,7,0> - 3367208143U, // <6,1,5,7>: Cost 4 vmrglw <1,u,6,5>, <1,6,1,7> - 4196372732U, // <6,1,5,u>: Cost 3 vsldoi8 <5,u,6,1>, <5,u,6,1> - 4078411878U, // <6,1,6,0>: Cost 3 vsldoi4 , LHS - 3261530932U, // <6,1,6,1>: Cost 3 vmrghw <6,6,6,6>, <1,1,1,1> - 3261531030U, // <6,1,6,2>: Cost 3 vmrghw <6,6,6,6>, <1,2,3,0> - 4178457113U, // <6,1,6,3>: Cost 4 vsldoi8 <2,u,6,1>, <6,3,1,7> - 4078415158U, // <6,1,6,4>: Cost 3 vsldoi4 , RHS - 3395748178U, // <6,1,6,5>: Cost 3 vmrglw <6,6,6,6>, <0,4,1,5> - 4202345272U, // <6,1,6,6>: Cost 3 vsldoi8 <6,u,6,1>, <6,6,6,6> - 4196373326U, // <6,1,6,7>: Cost 4 vsldoi8 <5,u,6,1>, <6,7,0,1> - 3261531516U, // <6,1,6,u>: Cost 3 vmrghw <6,6,6,6>, <1,u,3,0> - 4036616294U, // <6,1,7,0>: Cost 3 vsldoi4 <1,6,1,7>, LHS - 2309406730U, // <6,1,7,1>: Cost 2 vmrglw RHS, <0,0,1,1> - 2309408918U, // <6,1,7,2>: Cost 2 vmrglw RHS, <3,0,1,2> - 3383148718U, // <6,1,7,3>: Cost 3 vmrglw RHS, <0,2,1,3> - 4036619574U, // <6,1,7,4>: Cost 3 vsldoi4 <1,6,1,7>, RHS - 2309407058U, // <6,1,7,5>: Cost 2 vmrglw RHS, <0,4,1,5> - 3383148721U, // <6,1,7,6>: Cost 3 vmrglw RHS, <0,2,1,6> - 3383149046U, // <6,1,7,7>: Cost 3 vmrglw RHS, <0,6,1,7> - 2309406737U, // <6,1,7,u>: Cost 2 vmrglw RHS, <0,0,1,u> - 4036624486U, // <6,1,u,0>: Cost 3 vsldoi4 <1,6,1,u>, LHS - 2309414922U, // <6,1,u,1>: Cost 2 vmrglw RHS, <0,0,1,1> - 2309417110U, // <6,1,u,2>: Cost 2 vmrglw RHS, <3,0,1,2> - 3242214780U, // <6,1,u,3>: Cost 3 vsldoi12 <3,4,5,6>, <1,u,3,0> - 4036627766U, // <6,1,u,4>: Cost 3 vsldoi4 <1,6,1,u>, RHS - 2309415250U, // <6,1,u,5>: Cost 2 vmrglw RHS, <0,4,1,5> - 3383156913U, // <6,1,u,6>: Cost 3 vmrglw RHS, <0,2,1,6> - 3383157238U, // <6,1,u,7>: Cost 3 vmrglw RHS, <0,6,1,7> - 2309414929U, // <6,1,u,u>: Cost 2 vmrglw RHS, <0,0,1,u> - 3257574861U, // <6,2,0,0>: Cost 4 vmrghw <6,0,7,0>, <2,0,3,0> - 4201685094U, // <6,2,0,1>: Cost 3 vsldoi8 <6,7,6,2>, LHS - 4173815985U, // <6,2,0,2>: Cost 4 vsldoi8 <2,1,6,2>, <0,2,1,6> - 3383091302U, // <6,2,0,3>: Cost 3 vmrglw <4,5,6,0>, LHS - 4066495798U, // <6,2,0,4>: Cost 4 vsldoi4 <6,6,2,0>, RHS - 3236759008U, // <6,2,0,5>: Cost 4 vsldoi12 <2,5,3,6>, <2,0,5,1> - 3238675945U, // <6,2,0,6>: Cost 4 vsldoi12 <2,u,2,6>, <2,0,6,1> - 4072469991U, // <6,2,0,7>: Cost 4 vsldoi4 <7,6,2,0>, <7,6,2,0> - 3383091307U, // <6,2,0,u>: Cost 3 vmrglw <4,5,6,0>, LHS - 3367840468U, // <6,2,1,0>: Cost 4 vmrglw <2,0,6,1>, <3,7,2,0> - 3258246687U, // <6,2,1,1>: Cost 4 vmrghw <6,1,7,1>, <2,1,3,1> - 3373147752U, // <6,2,1,2>: Cost 4 vmrglw <2,u,6,1>, <2,2,2,2> - 3373146214U, // <6,2,1,3>: Cost 3 vmrglw <2,u,6,1>, LHS - 4036644150U, // <6,2,1,4>: Cost 5 vsldoi4 <1,6,2,1>, RHS - 4170499238U, // <6,2,1,5>: Cost 4 vsldoi8 <1,5,6,2>, <1,5,6,2> - 3222677049U, // <6,2,1,6>: Cost 4 vsldoi12 <0,2,1,6>, <2,1,6,0> - 3373147838U, // <6,2,1,7>: Cost 5 vmrglw <2,u,6,1>, <2,3,2,7> - 3373146219U, // <6,2,1,u>: Cost 3 vmrglw <2,u,6,1>, LHS - 4066508902U, // <6,2,2,0>: Cost 3 vsldoi4 <6,6,2,2>, LHS - 4173817403U, // <6,2,2,1>: Cost 4 vsldoi8 <2,1,6,2>, <2,1,6,2> - 3236243048U, // <6,2,2,2>: Cost 3 vsldoi12 <2,4,5,6>, <2,2,2,2> - 3242215026U, // <6,2,2,3>: Cost 3 vsldoi12 <3,4,5,6>, <2,2,3,3> - 4066512182U, // <6,2,2,4>: Cost 3 vsldoi4 <6,6,2,2>, RHS - 4193060712U, // <6,2,2,5>: Cost 4 vsldoi8 <5,3,6,2>, <2,5,3,6> - 3258927034U, // <6,2,2,6>: Cost 3 vmrghw <6,2,7,3>, <2,6,3,7> - 3258927108U, // <6,2,2,7>: Cost 3 vmrghw <6,2,7,3>, <2,7,3,0> - 3242215071U, // <6,2,2,u>: Cost 3 vsldoi12 <3,4,5,6>, <2,2,u,3> - 3242215078U, // <6,2,3,0>: Cost 3 vsldoi12 <3,4,5,6>, <2,3,0,1> - 3230271154U, // <6,2,3,1>: Cost 4 vsldoi12 <1,4,5,6>, <2,3,1,4> - 3235358397U, // <6,2,3,2>: Cost 3 vsldoi12 <2,3,2,6>, <2,3,2,6> - 3375153254U, // <6,2,3,3>: Cost 3 vmrglw <3,2,6,3>, LHS - 3242215118U, // <6,2,3,4>: Cost 3 vsldoi12 <3,4,5,6>, <2,3,4,5> - 3235579608U, // <6,2,3,5>: Cost 3 vsldoi12 <2,3,5,6>, <2,3,5,6> - 3259566010U, // <6,2,3,6>: Cost 3 vmrghw <6,3,7,0>, <2,6,3,7> - 3266103016U, // <6,2,3,7>: Cost 3 vsldoi12 <7,4,5,6>, <2,3,7,4> - 3235800819U, // <6,2,3,u>: Cost 3 vsldoi12 <2,3,u,6>, <2,3,u,6> - 4060553318U, // <6,2,4,0>: Cost 4 vsldoi4 <5,6,2,4>, LHS - 3368530217U, // <6,2,4,1>: Cost 5 vmrglw <2,1,6,4>, <6,0,2,1> - 3236243213U, // <6,2,4,2>: Cost 4 vsldoi12 <2,4,5,6>, <2,4,2,5> - 3383124070U, // <6,2,4,3>: Cost 3 vmrglw <4,5,6,4>, LHS - 4060556598U, // <6,2,4,4>: Cost 4 vsldoi4 <5,6,2,4>, RHS - 3236243241U, // <6,2,4,5>: Cost 3 vsldoi12 <2,4,5,6>, <2,4,5,6> - 3238676273U, // <6,2,4,6>: Cost 4 vsldoi12 <2,u,2,6>, <2,4,6,5> - 3259901956U, // <6,2,4,7>: Cost 4 vmrghw <6,4,2,5>, <2,7,3,0> - 3236464452U, // <6,2,4,u>: Cost 3 vsldoi12 <2,4,u,6>, <2,4,u,6> - 4048617574U, // <6,2,5,0>: Cost 4 vsldoi4 <3,6,2,5>, LHS - 4191735494U, // <6,2,5,1>: Cost 4 vsldoi8 <5,1,6,2>, <5,1,6,2> - 3236685663U, // <6,2,5,2>: Cost 4 vsldoi12 <2,5,2,6>, <2,5,2,6> - 3236759400U, // <6,2,5,3>: Cost 3 vsldoi12 <2,5,3,6>, <2,5,3,6> - 4048620854U, // <6,2,5,4>: Cost 4 vsldoi4 <3,6,2,5>, RHS - 4194390026U, // <6,2,5,5>: Cost 4 vsldoi8 <5,5,6,2>, <5,5,6,2> - 3373180605U, // <6,2,5,6>: Cost 4 vmrglw <2,u,6,5>, <2,3,2,6> - 4195717292U, // <6,2,5,7>: Cost 4 vsldoi8 <5,7,6,2>, <5,7,6,2> - 3237128085U, // <6,2,5,u>: Cost 3 vsldoi12 <2,5,u,6>, <2,5,u,6> - 4036681830U, // <6,2,6,0>: Cost 4 vsldoi4 <1,6,2,6>, LHS - 4036682967U, // <6,2,6,1>: Cost 4 vsldoi4 <1,6,2,6>, <1,6,2,6> - 3261531752U, // <6,2,6,2>: Cost 3 vmrghw <6,6,6,6>, <2,2,2,2> - 2322006118U, // <6,2,6,3>: Cost 2 vmrglw <6,6,6,6>, LHS - 4036685110U, // <6,2,6,4>: Cost 4 vsldoi4 <1,6,2,6>, RHS - 4060573755U, // <6,2,6,5>: Cost 4 vsldoi4 <5,6,2,6>, <5,6,2,6> - 3261532090U, // <6,2,6,6>: Cost 3 vmrghw <6,6,6,6>, <2,6,3,7> - 4201689989U, // <6,2,6,7>: Cost 3 vsldoi8 <6,7,6,2>, <6,7,6,2> - 2322006123U, // <6,2,6,u>: Cost 2 vmrglw <6,6,6,6>, LHS - 4042661990U, // <6,2,7,0>: Cost 3 vsldoi4 <2,6,2,7>, LHS - 3383149292U, // <6,2,7,1>: Cost 3 vmrglw RHS, <1,0,2,1> - 2309408360U, // <6,2,7,2>: Cost 2 vmrglw RHS, <2,2,2,2> - 1235664998U, // <6,2,7,3>: Cost 1 vmrglw RHS, LHS - 4042665270U, // <6,2,7,4>: Cost 3 vsldoi4 <2,6,2,7>, RHS - 3383149620U, // <6,2,7,5>: Cost 3 vmrglw RHS, <1,4,2,5> - 3383150269U, // <6,2,7,6>: Cost 3 vmrglw RHS, <2,3,2,6> - 3383149784U, // <6,2,7,7>: Cost 3 vmrglw RHS, <1,6,2,7> - 1235665003U, // <6,2,7,u>: Cost 1 vmrglw RHS, LHS - 4042670182U, // <6,2,u,0>: Cost 3 vsldoi4 <2,6,2,u>, LHS - 3383157484U, // <6,2,u,1>: Cost 3 vmrglw RHS, <1,0,2,1> - 2309416552U, // <6,2,u,2>: Cost 2 vmrglw RHS, <2,2,2,2> - 1235673190U, // <6,2,u,3>: Cost 1 vmrglw RHS, LHS - 4042673462U, // <6,2,u,4>: Cost 3 vsldoi4 <2,6,2,u>, RHS - 3238897773U, // <6,2,u,5>: Cost 3 vsldoi12 <2,u,5,6>, <2,u,5,6> - 3383158461U, // <6,2,u,6>: Cost 3 vmrglw RHS, <2,3,2,6> - 3383157976U, // <6,2,u,7>: Cost 3 vmrglw RHS, <1,6,2,7> - 1235673195U, // <6,2,u,u>: Cost 1 vmrglw RHS, LHS - 4180459520U, // <6,3,0,0>: Cost 4 vsldoi8 <3,2,6,3>, <0,0,0,0> - 4180459622U, // <6,3,0,1>: Cost 3 vsldoi8 <3,2,6,3>, LHS - 4168515761U, // <6,3,0,2>: Cost 4 vsldoi8 <1,2,6,3>, <0,2,1,6> - 3239413932U, // <6,3,0,3>: Cost 4 vsldoi12 <3,0,3,6>, <3,0,3,6> - 3257149954U, // <6,3,0,4>: Cost 3 vmrghw <6,0,1,2>, <3,4,5,6> - 4060598334U, // <6,3,0,5>: Cost 4 vsldoi4 <5,6,3,0>, <5,6,3,0> - 3383093096U, // <6,3,0,6>: Cost 4 vmrglw <4,5,6,0>, <2,5,3,6> - 3368495034U, // <6,3,0,7>: Cost 4 vmrglw <2,1,6,0>, <2,6,3,7> - 4180460189U, // <6,3,0,u>: Cost 3 vsldoi8 <3,2,6,3>, LHS - 3258255510U, // <6,3,1,0>: Cost 3 vmrghw <6,1,7,2>, <3,0,1,2> - 4180460340U, // <6,3,1,1>: Cost 4 vsldoi8 <3,2,6,3>, <1,1,1,1> - 4168516532U, // <6,3,1,2>: Cost 4 vsldoi8 <1,2,6,3>, <1,2,6,3> - 3373147762U, // <6,3,1,3>: Cost 4 vmrglw <2,u,6,1>, <2,2,3,3> - 3230271749U, // <6,3,1,4>: Cost 4 vsldoi12 <1,4,5,6>, <3,1,4,5> - 3373147683U, // <6,3,1,5>: Cost 5 vmrglw <2,u,6,1>, <2,1,3,5> - 3391727545U, // <6,3,1,6>: Cost 4 vmrglw <6,0,6,1>, <2,6,3,6> - 3373148090U, // <6,3,1,7>: Cost 3 vmrglw <2,u,6,1>, <2,6,3,7> - 3258255510U, // <6,3,1,u>: Cost 3 vmrghw <6,1,7,2>, <3,0,1,2> - 3258927254U, // <6,3,2,0>: Cost 3 vmrghw <6,2,7,3>, <3,0,1,2> - 3258927334U, // <6,3,2,1>: Cost 4 vmrghw <6,2,7,3>, <3,1,1,1> - 4174489229U, // <6,3,2,2>: Cost 4 vsldoi8 <2,2,6,3>, <2,2,6,3> - 3258927516U, // <6,3,2,3>: Cost 3 vmrghw <6,2,7,3>, <3,3,3,3> - 3258927618U, // <6,3,2,4>: Cost 3 vmrghw <6,2,7,3>, <3,4,5,6> - 3236759901U, // <6,3,2,5>: Cost 4 vsldoi12 <2,5,3,6>, <3,2,5,3> - 4180461498U, // <6,3,2,6>: Cost 3 vsldoi8 <3,2,6,3>, <2,6,3,7> - 3368511418U, // <6,3,2,7>: Cost 4 vmrglw <2,1,6,2>, <2,6,3,7> - 3258927902U, // <6,3,2,u>: Cost 3 vmrghw <6,2,7,3>, <3,u,1,2> - 4042702950U, // <6,3,3,0>: Cost 4 vsldoi4 <2,6,3,3>, LHS - 4168517876U, // <6,3,3,1>: Cost 5 vsldoi8 <1,2,6,3>, <3,1,2,6> - 4180461926U, // <6,3,3,2>: Cost 3 vsldoi8 <3,2,6,3>, <3,2,6,3> - 3242215836U, // <6,3,3,3>: Cost 3 vsldoi12 <3,4,5,6>, <3,3,3,3> - 3242215847U, // <6,3,3,4>: Cost 3 vsldoi12 <3,4,5,6>, <3,3,4,5> - 4192406072U, // <6,3,3,5>: Cost 4 vsldoi8 <5,2,6,3>, <3,5,2,6> - 3236759994U, // <6,3,3,6>: Cost 4 vsldoi12 <2,5,3,6>, <3,3,6,6> - 3375155130U, // <6,3,3,7>: Cost 3 vmrglw <3,2,6,3>, <2,6,3,7> - 3244870091U, // <6,3,3,u>: Cost 3 vsldoi12 <3,u,5,6>, <3,3,u,5> - 4060627046U, // <6,3,4,0>: Cost 3 vsldoi4 <5,6,3,4>, LHS - 3242215898U, // <6,3,4,1>: Cost 4 vsldoi12 <3,4,5,6>, <3,4,1,2> - 3241994727U, // <6,3,4,2>: Cost 4 vsldoi12 <3,4,2,6>, <3,4,2,6> - 4060629506U, // <6,3,4,3>: Cost 3 vsldoi4 <5,6,3,4>, <3,4,5,6> - 4060630326U, // <6,3,4,4>: Cost 3 vsldoi4 <5,6,3,4>, RHS - 3242215938U, // <6,3,4,5>: Cost 2 vsldoi12 <3,4,5,6>, <3,4,5,6> - 3383125864U, // <6,3,4,6>: Cost 4 vmrglw <4,5,6,4>, <2,5,3,6> - 3368527802U, // <6,3,4,7>: Cost 4 vmrglw <2,1,6,4>, <2,6,3,7> - 3242437149U, // <6,3,4,u>: Cost 2 vsldoi12 <3,4,u,6>, <3,4,u,6> - 3373179798U, // <6,3,5,0>: Cost 4 vmrglw <2,u,6,5>, <1,2,3,0> - 4042720499U, // <6,3,5,1>: Cost 5 vsldoi4 <2,6,3,5>, <1,6,5,7> - 4192407320U, // <6,3,5,2>: Cost 3 vsldoi8 <5,2,6,3>, <5,2,6,3> - 3373180530U, // <6,3,5,3>: Cost 4 vmrglw <2,u,6,5>, <2,2,3,3> - 3260942850U, // <6,3,5,4>: Cost 3 vmrghw <6,5,7,6>, <3,4,5,6> - 4188426254U, // <6,3,5,5>: Cost 4 vsldoi8 <4,5,6,3>, <5,5,6,6> - 3236760156U, // <6,3,5,6>: Cost 4 vsldoi12 <2,5,3,6>, <3,5,6,6> - 3373180858U, // <6,3,5,7>: Cost 3 vmrglw <2,u,6,5>, <2,6,3,7> - 4196389118U, // <6,3,5,u>: Cost 3 vsldoi8 <5,u,6,3>, <5,u,6,3> - 3261532310U, // <6,3,6,0>: Cost 3 vmrghw <6,6,6,6>, <3,0,1,2> - 3261532390U, // <6,3,6,1>: Cost 4 vmrghw <6,6,6,6>, <3,1,1,1> - 4042729401U, // <6,3,6,2>: Cost 3 vsldoi4 <2,6,3,6>, <2,6,3,6> - 3261532572U, // <6,3,6,3>: Cost 3 vmrghw <6,6,6,6>, <3,3,3,3> - 3261532674U, // <6,3,6,4>: Cost 3 vmrghw <6,6,6,6>, <3,4,5,6> - 4188426956U, // <6,3,6,5>: Cost 4 vsldoi8 <4,5,6,3>, <6,5,3,6> - 4202361656U, // <6,3,6,6>: Cost 3 vsldoi8 <6,u,6,3>, <6,6,6,6> - 3395749818U, // <6,3,6,7>: Cost 3 vmrglw <6,6,6,6>, <2,6,3,7> - 3261532958U, // <6,3,6,u>: Cost 3 vmrghw <6,6,6,6>, <3,u,1,2> - 2968993894U, // <6,3,7,0>: Cost 2 vsldoi4 <2,6,3,7>, LHS - 4042736436U, // <6,3,7,1>: Cost 3 vsldoi4 <2,6,3,7>, <1,1,1,1> - 2968995770U, // <6,3,7,2>: Cost 2 vsldoi4 <2,6,3,7>, <2,6,3,7> - 2309408370U, // <6,3,7,3>: Cost 2 vmrglw RHS, <2,2,3,3> - 2968997174U, // <6,3,7,4>: Cost 2 vsldoi4 <2,6,3,7>, RHS - 3383150115U, // <6,3,7,5>: Cost 3 vmrglw RHS, <2,1,3,5> - 4042740296U, // <6,3,7,6>: Cost 3 vsldoi4 <2,6,3,7>, <6,3,7,0> - 2309408698U, // <6,3,7,7>: Cost 2 vmrglw RHS, <2,6,3,7> - 2968999726U, // <6,3,7,u>: Cost 2 vsldoi4 <2,6,3,7>, LHS - 2969002086U, // <6,3,u,0>: Cost 2 vsldoi4 <2,6,3,u>, LHS - 4042744628U, // <6,3,u,1>: Cost 3 vsldoi4 <2,6,3,u>, <1,1,1,1> - 2969003963U, // <6,3,u,2>: Cost 2 vsldoi4 <2,6,3,u>, <2,6,3,u> - 2309416562U, // <6,3,u,3>: Cost 2 vmrglw RHS, <2,2,3,3> - 2969005366U, // <6,3,u,4>: Cost 2 vsldoi4 <2,6,3,u>, RHS - 3244870470U, // <6,3,u,5>: Cost 2 vsldoi12 <3,u,5,6>, <3,u,5,6> - 4042748497U, // <6,3,u,6>: Cost 3 vsldoi4 <2,6,3,u>, <6,3,u,0> - 2309416890U, // <6,3,u,7>: Cost 2 vmrglw RHS, <2,6,3,7> - 2969007918U, // <6,3,u,u>: Cost 2 vsldoi4 <2,6,3,u>, LHS - 4188430336U, // <6,4,0,0>: Cost 4 vsldoi8 <4,5,6,4>, <0,0,0,0> - 4188430438U, // <6,4,0,1>: Cost 3 vsldoi8 <4,5,6,4>, LHS - 4173832369U, // <6,4,0,2>: Cost 4 vsldoi8 <2,1,6,4>, <0,2,1,6> - 3242216320U, // <6,4,0,3>: Cost 4 vsldoi12 <3,4,5,6>, <4,0,3,1> - 4188430674U, // <6,4,0,4>: Cost 4 vsldoi8 <4,5,6,4>, <0,4,1,5> - 3257150774U, // <6,4,0,5>: Cost 3 vmrghw <6,0,1,2>, RHS - 3257150839U, // <6,4,0,6>: Cost 4 vmrghw <6,0,1,2>, <4,6,5,0> - 3383092458U, // <6,4,0,7>: Cost 5 vmrglw <4,5,6,0>, <1,6,4,7> - 4188431005U, // <6,4,0,u>: Cost 3 vsldoi8 <4,5,6,4>, LHS - 3258248082U, // <6,4,1,0>: Cost 4 vmrghw <6,1,7,1>, <4,0,5,1> - 4188431156U, // <6,4,1,1>: Cost 4 vsldoi8 <4,5,6,4>, <1,1,1,1> - 3242216394U, // <6,4,1,2>: Cost 4 vsldoi12 <3,4,5,6>, <4,1,2,3> - 3258256516U, // <6,4,1,3>: Cost 4 vmrghw <6,1,7,2>, <4,3,5,0> - 3248188379U, // <6,4,1,4>: Cost 4 vsldoi12 <4,4,5,6>, <4,1,4,2> - 3258248502U, // <6,4,1,5>: Cost 3 vmrghw <6,1,7,1>, RHS - 3258248568U, // <6,4,1,6>: Cost 4 vmrghw <6,1,7,1>, <4,6,5,1> - 3266104312U, // <6,4,1,7>: Cost 4 vsldoi12 <7,4,5,6>, <4,1,7,4> - 3258248745U, // <6,4,1,u>: Cost 3 vmrghw <6,1,7,1>, RHS - 3258928018U, // <6,4,2,0>: Cost 3 vmrghw <6,2,7,3>, <4,0,5,1> - 4173833789U, // <6,4,2,1>: Cost 4 vsldoi8 <2,1,6,4>, <2,1,6,4> - 4188431976U, // <6,4,2,2>: Cost 4 vsldoi8 <4,5,6,4>, <2,2,2,2> - 4180469437U, // <6,4,2,3>: Cost 4 vsldoi8 <3,2,6,4>, <2,3,2,6> - 3258928336U, // <6,4,2,4>: Cost 3 vmrghw <6,2,7,3>, <4,4,4,4> - 2185186614U, // <6,4,2,5>: Cost 2 vmrghw <6,2,7,3>, RHS - 3258928505U, // <6,4,2,6>: Cost 3 vmrghw <6,2,7,3>, <4,6,5,2> - 3258928584U, // <6,4,2,7>: Cost 4 vmrghw <6,2,7,3>, <4,7,5,0> - 2185186857U, // <6,4,2,u>: Cost 2 vmrghw <6,2,7,3>, RHS - 4188432534U, // <6,4,3,0>: Cost 4 vsldoi8 <4,5,6,4>, <3,0,1,2> - 3383118648U, // <6,4,3,1>: Cost 4 vmrglw <4,5,6,3>, <3,u,4,1> - 4180470119U, // <6,4,3,2>: Cost 4 vsldoi8 <3,2,6,4>, <3,2,6,4> - 4188432796U, // <6,4,3,3>: Cost 4 vsldoi8 <4,5,6,4>, <3,3,3,3> - 4188432898U, // <6,4,3,4>: Cost 3 vsldoi8 <4,5,6,4>, <3,4,5,6> - 3259387190U, // <6,4,3,5>: Cost 3 vmrghw <6,3,4,5>, RHS - 4187105948U, // <6,4,3,6>: Cost 4 vsldoi8 <4,3,6,4>, <3,6,4,7> - 4204358362U, // <6,4,3,7>: Cost 4 vsldoi8 <7,2,6,4>, <3,7,2,6> - 3259387433U, // <6,4,3,u>: Cost 3 vmrghw <6,3,4,5>, RHS - 4190423954U, // <6,4,4,0>: Cost 4 vsldoi8 <4,u,6,4>, <4,0,5,1> - 3383126840U, // <6,4,4,1>: Cost 4 vmrglw <4,5,6,4>, <3,u,4,1> - 3260271670U, // <6,4,4,2>: Cost 4 vmrghw <6,4,7,5>, <4,2,5,3> - 4187106449U, // <6,4,4,3>: Cost 4 vsldoi8 <4,3,6,4>, <4,3,6,4> - 3260263632U, // <6,4,4,4>: Cost 3 vmrghw <6,4,7,4>, <4,4,4,4> - 3248188635U, // <6,4,4,5>: Cost 3 vsldoi12 <4,4,5,6>, <4,4,5,6> - 3383128789U, // <6,4,4,6>: Cost 4 vmrglw <4,5,6,4>, <6,5,4,6> - 3381799580U, // <6,4,4,7>: Cost 4 vmrglw <4,3,6,4>, <3,6,4,7> - 3248409846U, // <6,4,4,u>: Cost 3 vsldoi12 <4,4,u,6>, <4,4,u,6> - 4060708966U, // <6,4,5,0>: Cost 3 vsldoi4 <5,6,4,5>, LHS - 4036822248U, // <6,4,5,1>: Cost 4 vsldoi4 <1,6,4,5>, <1,6,4,5> - 4036822970U, // <6,4,5,2>: Cost 4 vsldoi4 <1,6,4,5>, <2,6,3,7> - 4060711426U, // <6,4,5,3>: Cost 3 vsldoi4 <5,6,4,5>, <3,4,5,6> - 4060712246U, // <6,4,5,4>: Cost 3 vsldoi4 <5,6,4,5>, RHS - 4060713036U, // <6,4,5,5>: Cost 3 vsldoi4 <5,6,4,5>, <5,6,4,5> - 3242216758U, // <6,4,5,6>: Cost 2 vsldoi12 <3,4,5,6>, RHS - 4060713978U, // <6,4,5,7>: Cost 4 vsldoi4 <5,6,4,5>, <7,0,1,2> - 3242216776U, // <6,4,5,u>: Cost 2 vsldoi12 <3,4,5,6>, RHS - 3261533074U, // <6,4,6,0>: Cost 3 vmrghw <6,6,6,6>, <4,0,5,1> - 3389115192U, // <6,4,6,1>: Cost 4 vmrglw <5,5,6,6>, <3,u,4,1> - 4188434911U, // <6,4,6,2>: Cost 4 vsldoi8 <4,5,6,4>, <6,2,4,3> - 4188434994U, // <6,4,6,3>: Cost 4 vsldoi8 <4,5,6,4>, <6,3,4,5> - 3261533392U, // <6,4,6,4>: Cost 3 vmrghw <6,6,6,6>, <4,4,4,4> - 2187791670U, // <6,4,6,5>: Cost 2 vmrghw <6,6,6,6>, RHS - 3261533565U, // <6,4,6,6>: Cost 3 vmrghw <6,6,6,6>, <4,6,5,6> - 4190425934U, // <6,4,6,7>: Cost 4 vsldoi8 <4,u,6,4>, <6,7,0,1> - 2187791913U, // <6,4,6,u>: Cost 2 vmrghw <6,6,6,6>, RHS - 4048781414U, // <6,4,7,0>: Cost 3 vsldoi4 <3,6,4,7>, LHS - 4048782234U, // <6,4,7,1>: Cost 3 vsldoi4 <3,6,4,7>, <1,2,3,4> - 4042811331U, // <6,4,7,2>: Cost 4 vsldoi4 <2,6,4,7>, <2,6,4,7> - 4048784028U, // <6,4,7,3>: Cost 3 vsldoi4 <3,6,4,7>, <3,6,4,7> - 2311400656U, // <6,4,7,4>: Cost 2 vmrglw RHS, <4,4,4,4> - 2309408462U, // <6,4,7,5>: Cost 2 vmrglw RHS, <2,3,4,5> - 4048786073U, // <6,4,7,6>: Cost 4 vsldoi4 <3,6,4,7>, <6,4,7,0> - 3383151260U, // <6,4,7,7>: Cost 3 vmrglw RHS, <3,6,4,7> - 2309408465U, // <6,4,7,u>: Cost 2 vmrglw RHS, <2,3,4,u> - 4048789606U, // <6,4,u,0>: Cost 3 vsldoi4 <3,6,4,u>, LHS - 4048790426U, // <6,4,u,1>: Cost 3 vsldoi4 <3,6,4,u>, <1,2,3,4> - 4036847546U, // <6,4,u,2>: Cost 4 vsldoi4 <1,6,4,u>, <2,6,3,7> - 4048792221U, // <6,4,u,3>: Cost 3 vsldoi4 <3,6,4,u>, <3,6,4,u> - 2309418192U, // <6,4,u,4>: Cost 2 vmrglw RHS, <4,4,4,4> - 2309416654U, // <6,4,u,5>: Cost 2 vmrglw RHS, <2,3,4,5> - 3242217001U, // <6,4,u,6>: Cost 2 vsldoi12 <3,4,5,6>, RHS - 3383159452U, // <6,4,u,7>: Cost 3 vmrglw RHS, <3,6,4,7> - 3242217019U, // <6,4,u,u>: Cost 2 vsldoi12 <3,4,5,6>, RHS - 4178485248U, // <6,5,0,0>: Cost 4 vsldoi8 <2,u,6,5>, <0,0,0,0> - 4178485350U, // <6,5,0,1>: Cost 3 vsldoi8 <2,u,6,5>, LHS - 4178485425U, // <6,5,0,2>: Cost 4 vsldoi8 <2,u,6,5>, <0,2,1,6> - 4054772226U, // <6,5,0,3>: Cost 4 vsldoi4 <4,6,5,0>, <3,4,5,6> - 4178485586U, // <6,5,0,4>: Cost 4 vsldoi8 <2,u,6,5>, <0,4,1,5> - 3385085146U, // <6,5,0,5>: Cost 4 vmrglw <4,u,6,0>, <4,4,5,5> - 3383093762U, // <6,5,0,6>: Cost 3 vmrglw <4,5,6,0>, <3,4,5,6> - 3376459134U, // <6,5,0,7>: Cost 5 vmrglw <3,4,6,0>, <4,6,5,7> - 4178485917U, // <6,5,0,u>: Cost 3 vsldoi8 <2,u,6,5>, LHS - 4054777866U, // <6,5,1,0>: Cost 4 vsldoi4 <4,6,5,1>, <0,0,1,1> - 4178486068U, // <6,5,1,1>: Cost 4 vsldoi8 <2,u,6,5>, <1,1,1,1> - 4178486166U, // <6,5,1,2>: Cost 4 vsldoi8 <2,u,6,5>, <1,2,3,0> - 3242217133U, // <6,5,1,3>: Cost 4 vsldoi12 <3,4,5,6>, <5,1,3,4> - 4054781304U, // <6,5,1,4>: Cost 4 vsldoi4 <4,6,5,1>, <4,6,5,1> - 3252170433U, // <6,5,1,5>: Cost 4 vsldoi12 <5,1,5,6>, <5,1,5,6> - 3230273221U, // <6,5,1,6>: Cost 4 vsldoi12 <1,4,5,6>, <5,1,6,1> - 3266105041U, // <6,5,1,7>: Cost 4 vsldoi12 <7,4,5,6>, <5,1,7,4> - 4172514716U, // <6,5,1,u>: Cost 4 vsldoi8 <1,u,6,5>, <1,u,6,5> - 4054786150U, // <6,5,2,0>: Cost 3 vsldoi4 <4,6,5,2>, LHS - 4054786868U, // <6,5,2,1>: Cost 4 vsldoi4 <4,6,5,2>, <1,1,1,1> - 4178486888U, // <6,5,2,2>: Cost 4 vsldoi8 <2,u,6,5>, <2,2,2,2> - 4178486950U, // <6,5,2,3>: Cost 4 vsldoi8 <2,u,6,5>, <2,3,0,1> - 4054789497U, // <6,5,2,4>: Cost 3 vsldoi4 <4,6,5,2>, <4,6,5,2> - 3258929156U, // <6,5,2,5>: Cost 3 vmrghw <6,2,7,3>, <5,5,5,5> - 4178487226U, // <6,5,2,6>: Cost 3 vsldoi8 <2,u,6,5>, <2,6,3,7> - 4054791162U, // <6,5,2,7>: Cost 4 vsldoi4 <4,6,5,2>, <7,0,1,2> - 4178487413U, // <6,5,2,u>: Cost 3 vsldoi8 <2,u,6,5>, <2,u,6,5> - 4178487446U, // <6,5,3,0>: Cost 4 vsldoi8 <2,u,6,5>, <3,0,1,2> - 4179814679U, // <6,5,3,1>: Cost 4 vsldoi8 <3,1,6,5>, <3,1,6,5> - 4178487654U, // <6,5,3,2>: Cost 4 vsldoi8 <2,u,6,5>, <3,2,6,3> - 4178487708U, // <6,5,3,3>: Cost 4 vsldoi8 <2,u,6,5>, <3,3,3,3> - 4178487810U, // <6,5,3,4>: Cost 4 vsldoi8 <2,u,6,5>, <3,4,5,6> - 3385109722U, // <6,5,3,5>: Cost 4 vmrglw <4,u,6,3>, <4,4,5,5> - 3383118338U, // <6,5,3,6>: Cost 3 vmrglw <4,5,6,3>, <3,4,5,6> - 4178488003U, // <6,5,3,7>: Cost 4 vsldoi8 <2,u,6,5>, <3,7,0,1> - 3383118338U, // <6,5,3,u>: Cost 3 vmrglw <4,5,6,3>, <3,4,5,6> - 4054802534U, // <6,5,4,0>: Cost 4 vsldoi4 <4,6,5,4>, LHS - 3385117586U, // <6,5,4,1>: Cost 4 vmrglw <4,u,6,4>, <4,0,5,1> - 3260133144U, // <6,5,4,2>: Cost 4 vmrghw <6,4,5,6>, <5,2,6,3> - 4054804994U, // <6,5,4,3>: Cost 4 vsldoi4 <4,6,5,4>, <3,4,5,6> - 4054805883U, // <6,5,4,4>: Cost 4 vsldoi4 <4,6,5,4>, <4,6,5,4> - 4178488630U, // <6,5,4,5>: Cost 3 vsldoi8 <2,u,6,5>, RHS - 3383126530U, // <6,5,4,6>: Cost 3 vmrglw <4,5,6,4>, <3,4,5,6> - 3266105284U, // <6,5,4,7>: Cost 4 vsldoi12 <7,4,5,6>, <5,4,7,4> - 4178488873U, // <6,5,4,u>: Cost 3 vsldoi8 <2,u,6,5>, RHS - 4054810726U, // <6,5,5,0>: Cost 4 vsldoi4 <4,6,5,5>, LHS - 4191760073U, // <6,5,5,1>: Cost 4 vsldoi8 <5,1,6,5>, <5,1,6,5> - 4188442392U, // <6,5,5,2>: Cost 4 vsldoi8 <4,5,6,5>, <5,2,6,3> - 3373183950U, // <6,5,5,3>: Cost 4 vmrglw <2,u,6,5>, <6,u,5,3> - 4193750972U, // <6,5,5,4>: Cost 3 vsldoi8 <5,4,6,5>, <5,4,6,5> - 3261534212U, // <6,5,5,5>: Cost 3 vsldoi12 <6,6,6,6>, <5,5,5,5> - 3242217486U, // <6,5,5,6>: Cost 3 vsldoi12 <3,4,5,6>, <5,5,6,6> - 3373183549U, // <6,5,5,7>: Cost 4 vmrglw <2,u,6,5>, <6,3,5,7> - 4196405504U, // <6,5,5,u>: Cost 3 vsldoi8 <5,u,6,5>, <5,u,6,5> - 3242217508U, // <6,5,6,0>: Cost 3 vsldoi12 <3,4,5,6>, <5,6,0,1> - 3395750802U, // <6,5,6,1>: Cost 3 vmrglw <6,6,6,6>, <4,0,5,1> - 3236245559U, // <6,5,6,2>: Cost 4 vsldoi12 <2,4,5,6>, <5,6,2,2> - 3242217538U, // <6,5,6,3>: Cost 3 vsldoi12 <3,4,5,6>, <5,6,3,4> - 3242217548U, // <6,5,6,4>: Cost 3 vsldoi12 <3,4,5,6>, <5,6,4,5> - 3261534212U, // <6,5,6,5>: Cost 3 vmrghw <6,6,6,6>, <5,5,5,5> - 3242217568U, // <6,5,6,6>: Cost 3 vsldoi12 <3,4,5,6>, <5,6,6,7> - 3255636072U, // <6,5,6,7>: Cost 3 vsldoi12 <5,6,7,6>, <5,6,7,6> - 3242217580U, // <6,5,6,u>: Cost 3 vsldoi12 <3,4,5,6>, <5,6,u,1> - 4036911206U, // <6,5,7,0>: Cost 3 vsldoi4 <1,6,5,7>, LHS - 2309409682U, // <6,5,7,1>: Cost 2 vmrglw RHS, <4,0,5,1> - 3383151102U, // <6,5,7,2>: Cost 3 vmrglw RHS, <3,4,5,2> - 3383149483U, // <6,5,7,3>: Cost 3 vmrglw RHS, <1,2,5,3> - 4036914486U, // <6,5,7,4>: Cost 3 vsldoi4 <1,6,5,7>, RHS - 2309410010U, // <6,5,7,5>: Cost 2 vmrglw RHS, <4,4,5,5> - 2309409282U, // <6,5,7,6>: Cost 2 vmrglw RHS, <3,4,5,6> - 3383149811U, // <6,5,7,7>: Cost 3 vmrglw RHS, <1,6,5,7> - 2309409284U, // <6,5,7,u>: Cost 2 vmrglw RHS, <3,4,5,u> - 4036919398U, // <6,5,u,0>: Cost 3 vsldoi4 <1,6,5,u>, LHS - 2309417874U, // <6,5,u,1>: Cost 2 vmrglw RHS, <4,0,5,1> - 3383159294U, // <6,5,u,2>: Cost 3 vmrglw RHS, <3,4,5,2> - 3383157675U, // <6,5,u,3>: Cost 3 vmrglw RHS, <1,2,5,3> - 4036922678U, // <6,5,u,4>: Cost 3 vsldoi4 <1,6,5,u>, RHS - 2309418202U, // <6,5,u,5>: Cost 2 vmrglw RHS, <4,4,5,5> - 2309417474U, // <6,5,u,6>: Cost 2 vmrglw RHS, <3,4,5,6> - 3383158003U, // <6,5,u,7>: Cost 3 vmrglw RHS, <1,6,5,7> - 2309417476U, // <6,5,u,u>: Cost 2 vmrglw RHS, <3,4,5,u> - 3383094575U, // <6,6,0,0>: Cost 3 vmrglw <4,5,6,0>, <4,5,6,0> - 3127312486U, // <6,6,0,1>: Cost 2 vsldoi8 <6,6,6,6>, LHS - 3257217530U, // <6,6,0,2>: Cost 3 vmrghw <6,0,2,1>, <6,2,7,3> - 3242217778U, // <6,6,0,3>: Cost 4 vsldoi12 <3,4,5,6>, <6,0,3,1> - 4201054546U, // <6,6,0,4>: Cost 3 vsldoi8 <6,6,6,6>, <0,4,1,5> - 4060819545U, // <6,6,0,5>: Cost 4 vsldoi4 <5,6,6,0>, <5,6,6,0> - 3261534541U, // <6,6,0,6>: Cost 3 vsldoi12 <6,6,6,6>, <6,0,6,1> - 3383094582U, // <6,6,0,7>: Cost 3 vmrglw <4,5,6,0>, RHS - 3127313053U, // <6,6,0,u>: Cost 2 vsldoi8 <6,6,6,6>, LHS - 3258249504U, // <6,6,1,0>: Cost 4 vmrghw <6,1,7,1>, <6,0,1,1> - 3373148273U, // <6,6,1,1>: Cost 3 vmrglw <2,u,6,1>, <2,u,6,1> - 4201055126U, // <6,6,1,2>: Cost 3 vsldoi8 <6,6,6,6>, <1,2,3,0> - 3373148518U, // <6,6,1,3>: Cost 4 vmrglw <2,u,6,1>, <3,2,6,3> - 3230273936U, // <6,6,1,4>: Cost 4 vsldoi12 <1,4,5,6>, <6,1,4,5> - 3373147953U, // <6,6,1,5>: Cost 4 vmrglw <2,u,6,1>, <2,4,6,5> - 3397038904U, // <6,6,1,6>: Cost 3 vmrglw <6,u,6,1>, <6,6,6,6> - 3373149494U, // <6,6,1,7>: Cost 3 vmrglw <2,u,6,1>, RHS - 3373149495U, // <6,6,1,u>: Cost 3 vmrglw <2,u,6,1>, RHS - 3258929449U, // <6,6,2,0>: Cost 3 vmrghw <6,2,7,3>, <6,0,2,1> - 3258929530U, // <6,6,2,1>: Cost 4 vmrghw <6,2,7,3>, <6,1,2,1> - 2185187834U, // <6,6,2,2>: Cost 2 vmrghw <6,2,7,3>, <6,2,7,3> - 4201055910U, // <6,6,2,3>: Cost 3 vsldoi8 <6,6,6,6>, <2,3,0,1> - 3258929777U, // <6,6,2,4>: Cost 3 vmrghw <6,2,7,3>, <6,4,2,5> - 3236762088U, // <6,6,2,5>: Cost 4 vsldoi12 <2,5,3,6>, <6,2,5,3> - 3258929936U, // <6,6,2,6>: Cost 3 vmrghw <6,2,7,3>, <6,6,2,2> - 3255636474U, // <6,6,2,7>: Cost 3 vsldoi12 <5,6,7,6>, <6,2,7,3> - 2185187834U, // <6,6,2,u>: Cost 2 vmrghw <6,2,7,3>, <6,2,7,3> - 4201056406U, // <6,6,3,0>: Cost 3 vsldoi8 <6,6,6,6>, <3,0,1,2> - 3375154665U, // <6,6,3,1>: Cost 4 vmrglw <3,2,6,3>, <2,0,6,1> - 3375154909U, // <6,6,3,2>: Cost 4 vmrglw <3,2,6,3>, <2,3,6,2> - 3375155558U, // <6,6,3,3>: Cost 3 vmrglw <3,2,6,3>, <3,2,6,3> - 3242218034U, // <6,6,3,4>: Cost 3 vsldoi12 <3,4,5,6>, <6,3,4,5> - 3375154993U, // <6,6,3,5>: Cost 4 vmrglw <3,2,6,3>, <2,4,6,5> - 3397055288U, // <6,6,3,6>: Cost 3 vmrglw <6,u,6,3>, <6,6,6,6> - 3375156534U, // <6,6,3,7>: Cost 3 vmrglw <3,2,6,3>, RHS - 3375156535U, // <6,6,3,u>: Cost 3 vmrglw <3,2,6,3>, RHS - 4201057170U, // <6,6,4,0>: Cost 3 vsldoi8 <6,6,6,6>, <4,0,5,1> - 3259830695U, // <6,6,4,1>: Cost 4 vmrghw <6,4,1,5>, <6,1,7,1> - 3259904506U, // <6,6,4,2>: Cost 3 vmrghw <6,4,2,5>, <6,2,7,3> - 3383127346U, // <6,6,4,3>: Cost 4 vmrglw <4,5,6,4>, <4,5,6,3> - 3383127347U, // <6,6,4,4>: Cost 3 vmrglw <4,5,6,4>, <4,5,6,4> - 3127315766U, // <6,6,4,5>: Cost 2 vsldoi8 <6,6,6,6>, RHS - 4201057661U, // <6,6,4,6>: Cost 3 vsldoi8 <6,6,6,6>, <4,6,5,6> - 3383127350U, // <6,6,4,7>: Cost 3 vmrglw <4,5,6,4>, RHS - 3127316009U, // <6,6,4,u>: Cost 2 vsldoi8 <6,6,6,6>, RHS - 4060856422U, // <6,6,5,0>: Cost 4 vsldoi4 <5,6,6,5>, LHS - 3373180393U, // <6,6,5,1>: Cost 4 vmrglw <2,u,6,5>, <2,0,6,1> - 4194422552U, // <6,6,5,2>: Cost 4 vsldoi8 <5,5,6,6>, <5,2,6,3> - 3373181286U, // <6,6,5,3>: Cost 4 vmrglw <2,u,6,5>, <3,2,6,3> - 4060859702U, // <6,6,5,4>: Cost 4 vsldoi4 <5,6,6,5>, RHS - 3373181045U, // <6,6,5,5>: Cost 3 vmrglw <2,u,6,5>, <2,u,6,5> - 4201058402U, // <6,6,5,6>: Cost 3 vsldoi8 <6,6,6,6>, <5,6,7,0> - 3373182262U, // <6,6,5,7>: Cost 3 vmrglw <2,u,6,5>, RHS - 3373182263U, // <6,6,5,u>: Cost 3 vmrglw <2,u,6,5>, RHS - 2993094758U, // <6,6,6,0>: Cost 2 vsldoi4 <6,6,6,6>, LHS - 3395752269U, // <6,6,6,1>: Cost 3 vmrglw <6,6,6,6>, <6,0,6,1> - 3261207034U, // <6,6,6,2>: Cost 3 vmrghw <6,6,2,2>, <6,2,7,3> - 3395752433U, // <6,6,6,3>: Cost 3 vmrglw <6,6,6,6>, <6,2,6,3> - 2993098038U, // <6,6,6,4>: Cost 2 vsldoi4 <6,6,6,6>, RHS - 3395752597U, // <6,6,6,5>: Cost 3 vmrglw <6,6,6,6>, <6,4,6,5> - 1638321462U, // <6,6,6,6>: Cost 1 vspltisw2 RHS - 2322009398U, // <6,6,6,7>: Cost 2 vmrglw <6,6,6,6>, RHS - 1638321462U, // <6,6,6,u>: Cost 1 vspltisw2 RHS - 3383151919U, // <6,6,7,0>: Cost 3 vmrglw RHS, <4,5,6,0> - 3383150057U, // <6,6,7,1>: Cost 3 vmrglw RHS, <2,0,6,1> - 3385144197U, // <6,6,7,2>: Cost 3 vmrglw RHS, <6,7,6,2> - 3383150950U, // <6,6,7,3>: Cost 3 vmrglw RHS, <3,2,6,3> - 3383151923U, // <6,6,7,4>: Cost 3 vmrglw RHS, <4,5,6,4> - 3383150385U, // <6,6,7,5>: Cost 3 vmrglw RHS, <2,4,6,5> - 2311402296U, // <6,6,7,6>: Cost 2 vmrglw RHS, <6,6,6,6> - 1235668278U, // <6,6,7,7>: Cost 1 vmrglw RHS, RHS - 1235668279U, // <6,6,7,u>: Cost 1 vmrglw RHS, RHS - 2993094758U, // <6,6,u,0>: Cost 2 vsldoi4 <6,6,6,6>, LHS - 3127318318U, // <6,6,u,1>: Cost 2 vsldoi8 <6,6,6,6>, LHS - 2185187834U, // <6,6,u,2>: Cost 2 vmrghw <6,2,7,3>, <6,2,7,3> - 3383159142U, // <6,6,u,3>: Cost 3 vmrglw RHS, <3,2,6,3> - 2993098038U, // <6,6,u,4>: Cost 2 vsldoi4 <6,6,6,6>, RHS - 3127318682U, // <6,6,u,5>: Cost 2 vsldoi8 <6,6,6,6>, RHS - 1638321462U, // <6,6,u,6>: Cost 1 vspltisw2 RHS - 1235676470U, // <6,6,u,7>: Cost 1 vmrglw RHS, RHS - 1235676471U, // <6,6,u,u>: Cost 1 vmrglw RHS, RHS - 3114713088U, // <6,7,0,0>: Cost 2 vsldoi8 RHS, <0,0,0,0> - 2040971366U, // <6,7,0,1>: Cost 1 vsldoi8 RHS, LHS - 4188455085U, // <6,7,0,2>: Cost 3 vsldoi8 RHS, <0,2,1,2> - 4188455164U, // <6,7,0,3>: Cost 3 vsldoi8 RHS, <0,3,1,0> - 3114713426U, // <6,7,0,4>: Cost 2 vsldoi8 RHS, <0,4,1,5> - 2987151458U, // <6,7,0,5>: Cost 2 vsldoi4 <5,6,7,0>, <5,6,7,0> - 4188455414U, // <6,7,0,6>: Cost 3 vsldoi8 RHS, <0,6,1,7> - 4060894202U, // <6,7,0,7>: Cost 3 vsldoi4 <5,6,7,0>, <7,0,1,2> - 2040971933U, // <6,7,0,u>: Cost 1 vsldoi8 RHS, LHS - 4188455651U, // <6,7,1,0>: Cost 3 vsldoi8 RHS, <1,0,1,1> - 3114713908U, // <6,7,1,1>: Cost 2 vsldoi8 RHS, <1,1,1,1> - 3114714006U, // <6,7,1,2>: Cost 2 vsldoi8 RHS, <1,2,3,0> - 4169212937U, // <6,7,1,3>: Cost 4 vsldoi8 <1,3,6,7>, <1,3,6,7> - 4188455979U, // <6,7,1,4>: Cost 3 vsldoi8 RHS, <1,4,1,5> - 4188456047U, // <6,7,1,5>: Cost 3 vsldoi8 RHS, <1,5,0,1> - 4188456143U, // <6,7,1,6>: Cost 3 vsldoi8 RHS, <1,6,1,7> - 3373148612U, // <6,7,1,7>: Cost 4 vmrglw <2,u,6,1>, <3,3,7,7> - 3114714492U, // <6,7,1,u>: Cost 2 vsldoi8 RHS, <1,u,3,0> - 4188456381U, // <6,7,2,0>: Cost 3 vsldoi8 RHS, <2,0,1,2> - 4188456479U, // <6,7,2,1>: Cost 3 vsldoi8 RHS, <2,1,3,1> - 3114714728U, // <6,7,2,2>: Cost 2 vsldoi8 RHS, <2,2,2,2> - 3114714790U, // <6,7,2,3>: Cost 2 vsldoi8 RHS, <2,3,0,1> - 4188456717U, // <6,7,2,4>: Cost 3 vsldoi8 RHS, <2,4,2,5> - 4188456808U, // <6,7,2,5>: Cost 3 vsldoi8 RHS, <2,5,3,6> - 3114715066U, // <6,7,2,6>: Cost 2 vsldoi8 RHS, <2,6,3,7> - 3258930796U, // <6,7,2,7>: Cost 3 vmrghw <6,2,7,3>, <7,7,7,7> - 3114715195U, // <6,7,2,u>: Cost 2 vsldoi8 RHS, <2,u,0,1> - 3114715286U, // <6,7,3,0>: Cost 2 vsldoi8 RHS, <3,0,1,2> - 4188457190U, // <6,7,3,1>: Cost 3 vsldoi8 RHS, <3,1,1,1> - 4188457264U, // <6,7,3,2>: Cost 3 vsldoi8 RHS, <3,2,0,3> - 3114715548U, // <6,7,3,3>: Cost 2 vsldoi8 RHS, <3,3,3,3> - 3114715650U, // <6,7,3,4>: Cost 2 vsldoi8 RHS, <3,4,5,6> - 4188457554U, // <6,7,3,5>: Cost 3 vsldoi8 RHS, <3,5,5,5> - 4188457592U, // <6,7,3,6>: Cost 3 vsldoi8 RHS, <3,6,0,7> - 4188457667U, // <6,7,3,7>: Cost 3 vsldoi8 RHS, <3,7,0,1> - 3114715934U, // <6,7,3,u>: Cost 2 vsldoi8 RHS, <3,u,1,2> - 3114716050U, // <6,7,4,0>: Cost 2 vsldoi8 RHS, <4,0,5,1> - 4188457930U, // <6,7,4,1>: Cost 3 vsldoi8 RHS, <4,1,2,3> - 4188458037U, // <6,7,4,2>: Cost 3 vsldoi8 RHS, <4,2,5,2> - 4188458116U, // <6,7,4,3>: Cost 3 vsldoi8 RHS, <4,3,5,0> - 3114716368U, // <6,7,4,4>: Cost 2 vsldoi8 RHS, <4,4,4,4> - 2040974646U, // <6,7,4,5>: Cost 1 vsldoi8 RHS, RHS - 4188458365U, // <6,7,4,6>: Cost 3 vsldoi8 RHS, <4,6,5,6> - 4188458447U, // <6,7,4,7>: Cost 3 vsldoi8 RHS, <4,7,5,7> - 2040974889U, // <6,7,4,u>: Cost 1 vsldoi8 RHS, RHS - 4188458568U, // <6,7,5,0>: Cost 3 vsldoi8 RHS, <5,0,1,2> - 4190449295U, // <6,7,5,1>: Cost 3 vsldoi8 RHS, <5,1,0,1> - 4188458750U, // <6,7,5,2>: Cost 3 vsldoi8 RHS, <5,2,3,4> - 3373181295U, // <6,7,5,3>: Cost 4 vmrglw <2,u,6,5>, <3,2,7,3> - 4188458932U, // <6,7,5,4>: Cost 3 vsldoi8 RHS, <5,4,5,6> - 3114717188U, // <6,7,5,5>: Cost 2 vsldoi8 RHS, <5,5,5,5> - 3114717282U, // <6,7,5,6>: Cost 2 vsldoi8 RHS, <5,6,7,0> - 3373181380U, // <6,7,5,7>: Cost 4 vmrglw <2,u,6,5>, <3,3,7,7> - 3116708100U, // <6,7,5,u>: Cost 2 vsldoi8 RHS, <5,u,7,0> - 4188459297U, // <6,7,6,0>: Cost 3 vsldoi8 RHS, <6,0,1,2> - 4188459431U, // <6,7,6,1>: Cost 3 vsldoi8 RHS, <6,1,7,1> - 3114717690U, // <6,7,6,2>: Cost 2 vsldoi8 RHS, <6,2,7,3> - 4188459570U, // <6,7,6,3>: Cost 3 vsldoi8 RHS, <6,3,4,5> - 4188459661U, // <6,7,6,4>: Cost 3 vsldoi8 RHS, <6,4,5,6> - 4188459755U, // <6,7,6,5>: Cost 3 vsldoi8 RHS, <6,5,7,1> - 3114718008U, // <6,7,6,6>: Cost 2 vsldoi8 RHS, <6,6,6,6> - 3114718030U, // <6,7,6,7>: Cost 2 vsldoi8 RHS, <6,7,0,1> - 3114718176U, // <6,7,6,u>: Cost 2 vsldoi8 RHS, <6,u,7,3> - 2311401570U, // <6,7,7,0>: Cost 2 vmrglw RHS, <5,6,7,0> - 3383152982U, // <6,7,7,1>: Cost 3 vmrglw RHS, <6,0,7,1> - 4049004474U, // <6,7,7,2>: Cost 3 vsldoi4 <3,6,7,7>, <2,6,3,7> - 2309411322U, // <6,7,7,3>: Cost 2 vmrglw RHS, <6,2,7,3> - 2311401574U, // <6,7,7,4>: Cost 2 vmrglw RHS, <5,6,7,4> - 3383153067U, // <6,7,7,5>: Cost 3 vmrglw RHS, <6,1,7,5> - 2993181506U, // <6,7,7,6>: Cost 2 vsldoi4 <6,6,7,7>, <6,6,7,7> - 2309411650U, // <6,7,7,7>: Cost 2 vmrglw RHS, <6,6,7,7> - 2309411327U, // <6,7,7,u>: Cost 2 vmrglw RHS, <6,2,7,u> - 3114718931U, // <6,7,u,0>: Cost 2 vsldoi8 RHS, - 2040977198U, // <6,7,u,1>: Cost 1 vsldoi8 RHS, LHS - 3114719109U, // <6,7,u,2>: Cost 2 vsldoi8 RHS, - 3114719164U, // <6,7,u,3>: Cost 2 vsldoi8 RHS, - 3114719295U, // <6,7,u,4>: Cost 2 vsldoi8 RHS, - 2040977562U, // <6,7,u,5>: Cost 1 vsldoi8 RHS, RHS - 3114719440U, // <6,7,u,6>: Cost 2 vsldoi8 RHS, - 2309419842U, // <6,7,u,7>: Cost 2 vmrglw RHS, <6,6,7,7> - 2040977765U, // <6,7,u,u>: Cost 1 vsldoi8 RHS, LHS - 3114721280U, // <6,u,0,0>: Cost 2 vsldoi8 RHS, <0,0,0,0> - 2040979558U, // <6,u,0,1>: Cost 1 vsldoi8 RHS, LHS - 4188463277U, // <6,u,0,2>: Cost 3 vsldoi8 RHS, <0,2,1,2> - 3383091356U, // <6,u,0,3>: Cost 3 vmrglw <4,5,6,0>, LHS - 3114721618U, // <6,u,0,4>: Cost 2 vsldoi8 RHS, <0,4,1,5> - 2987225195U, // <6,u,0,5>: Cost 2 vsldoi4 <5,6,u,0>, <5,6,u,0> - 4188463606U, // <6,u,0,6>: Cost 3 vsldoi8 RHS, <0,6,1,7> - 3383094600U, // <6,u,0,7>: Cost 3 vmrglw <4,5,6,0>, RHS - 2040980125U, // <6,u,0,u>: Cost 1 vsldoi8 RHS, LHS - 4188463843U, // <6,u,1,0>: Cost 3 vsldoi8 RHS, <1,0,1,1> - 3114722100U, // <6,u,1,1>: Cost 2 vsldoi8 RHS, <1,1,1,1> - 3242219310U, // <6,u,1,2>: Cost 2 vsldoi12 <3,4,5,6>, LHS - 3373146268U, // <6,u,1,3>: Cost 3 vmrglw <2,u,6,1>, LHS - 4188464171U, // <6,u,1,4>: Cost 3 vsldoi8 RHS, <1,4,1,5> - 4188464239U, // <6,u,1,5>: Cost 3 vsldoi8 RHS, <1,5,0,1> - 4188464335U, // <6,u,1,6>: Cost 3 vsldoi8 RHS, <1,6,1,7> - 3373149512U, // <6,u,1,7>: Cost 3 vmrglw <2,u,6,1>, RHS - 3242219364U, // <6,u,1,u>: Cost 2 vsldoi12 <3,4,5,6>, LHS - 4188464573U, // <6,u,2,0>: Cost 3 vsldoi8 RHS, <2,0,1,2> - 2185189166U, // <6,u,2,1>: Cost 2 vmrghw <6,2,7,3>, LHS - 3114722920U, // <6,u,2,2>: Cost 2 vsldoi8 RHS, <2,2,2,2> - 3114722982U, // <6,u,2,3>: Cost 2 vsldoi8 RHS, <2,3,0,1> - 4188464909U, // <6,u,2,4>: Cost 3 vsldoi8 RHS, <2,4,2,5> - 2185189530U, // <6,u,2,5>: Cost 2 vmrghw <6,2,7,3>, RHS - 3114723258U, // <6,u,2,6>: Cost 2 vsldoi8 RHS, <2,6,3,7> - 3258931456U, // <6,u,2,7>: Cost 3 vmrghw <6,2,7,3>, - 3114723387U, // <6,u,2,u>: Cost 2 vsldoi8 RHS, <2,u,0,1> - 3114723478U, // <6,u,3,0>: Cost 2 vsldoi8 RHS, <3,0,1,2> - 4188465382U, // <6,u,3,1>: Cost 3 vsldoi8 RHS, <3,1,1,1> - 4180502891U, // <6,u,3,2>: Cost 3 vsldoi8 <3,2,6,u>, <3,2,6,u> - 3114723740U, // <6,u,3,3>: Cost 2 vsldoi8 RHS, <3,3,3,3> - 3114723842U, // <6,u,3,4>: Cost 2 vsldoi8 RHS, <3,4,5,6> - 4188465746U, // <6,u,3,5>: Cost 3 vsldoi8 RHS, <3,5,5,5> - 4188465784U, // <6,u,3,6>: Cost 3 vsldoi8 RHS, <3,6,0,7> - 3375156552U, // <6,u,3,7>: Cost 3 vmrglw <3,2,6,3>, RHS - 3114724126U, // <6,u,3,u>: Cost 2 vsldoi8 RHS, <3,u,1,2> - 3114724242U, // <6,u,4,0>: Cost 2 vsldoi8 RHS, <4,0,5,1> - 4188466122U, // <6,u,4,1>: Cost 3 vsldoi8 RHS, <4,1,2,3> - 4188466229U, // <6,u,4,2>: Cost 3 vsldoi8 RHS, <4,2,5,2> - 3383124124U, // <6,u,4,3>: Cost 3 vmrglw <4,5,6,4>, LHS - 3114724560U, // <6,u,4,4>: Cost 2 vsldoi8 RHS, <4,4,4,4> - 2040982839U, // <6,u,4,5>: Cost 1 vsldoi8 RHS, RHS - 4188466553U, // <6,u,4,6>: Cost 3 vsldoi8 RHS, <4,6,5,2> - 3383127368U, // <6,u,4,7>: Cost 3 vmrglw <4,5,6,4>, RHS - 2040983081U, // <6,u,4,u>: Cost 1 vsldoi8 RHS, RHS - 4188466760U, // <6,u,5,0>: Cost 3 vsldoi8 RHS, <5,0,1,2> - 4190457487U, // <6,u,5,1>: Cost 3 vsldoi8 RHS, <5,1,0,1> - 4188466942U, // <6,u,5,2>: Cost 3 vsldoi8 RHS, <5,2,3,4> - 3373179036U, // <6,u,5,3>: Cost 3 vmrglw <2,u,6,5>, LHS - 4188467124U, // <6,u,5,4>: Cost 3 vsldoi8 RHS, <5,4,5,6> - 3114725380U, // <6,u,5,5>: Cost 2 vsldoi8 RHS, <5,5,5,5> - 3242219674U, // <6,u,5,6>: Cost 2 vsldoi12 <3,4,5,6>, RHS - 3373182280U, // <6,u,5,7>: Cost 3 vmrglw <2,u,6,5>, RHS - 3242219692U, // <6,u,5,u>: Cost 2 vsldoi12 <3,4,5,6>, RHS - 2993094758U, // <6,u,6,0>: Cost 2 vsldoi4 <6,6,6,6>, LHS - 2187794222U, // <6,u,6,1>: Cost 2 vmrghw <6,6,6,6>, LHS - 3114725882U, // <6,u,6,2>: Cost 2 vsldoi8 RHS, <6,2,7,3> - 2322006172U, // <6,u,6,3>: Cost 2 vmrglw <6,6,6,6>, LHS - 2993098038U, // <6,u,6,4>: Cost 2 vsldoi4 <6,6,6,6>, RHS - 2187794586U, // <6,u,6,5>: Cost 2 vmrghw <6,6,6,6>, RHS - 1638321462U, // <6,u,6,6>: Cost 1 vspltisw2 RHS - 3114726222U, // <6,u,6,7>: Cost 2 vsldoi8 RHS, <6,7,0,1> - 1638321462U, // <6,u,6,u>: Cost 1 vspltisw2 RHS - 2969362534U, // <6,u,7,0>: Cost 2 vsldoi4 <2,6,u,7>, LHS - 2309406793U, // <6,u,7,1>: Cost 2 vmrglw RHS, <0,0,u,1> - 2969364455U, // <6,u,7,2>: Cost 2 vsldoi4 <2,6,u,7>, <2,6,u,7> - 1235665052U, // <6,u,7,3>: Cost 1 vmrglw RHS, LHS - 2969365814U, // <6,u,7,4>: Cost 2 vsldoi4 <2,6,u,7>, RHS - 2309407121U, // <6,u,7,5>: Cost 2 vmrglw RHS, <0,4,u,5> - 2309409309U, // <6,u,7,6>: Cost 2 vmrglw RHS, <3,4,u,6> - 1235668296U, // <6,u,7,7>: Cost 1 vmrglw RHS, RHS - 1235665057U, // <6,u,7,u>: Cost 1 vmrglw RHS, LHS - 2969370726U, // <6,u,u,0>: Cost 2 vsldoi4 <2,6,u,u>, LHS - 2040985390U, // <6,u,u,1>: Cost 1 vsldoi8 RHS, LHS - 2969372648U, // <6,u,u,2>: Cost 2 vsldoi4 <2,6,u,u>, <2,6,u,u> - 1235673244U, // <6,u,u,3>: Cost 1 vmrglw RHS, LHS - 2969374006U, // <6,u,u,4>: Cost 2 vsldoi4 <2,6,u,u>, RHS - 2040985754U, // <6,u,u,5>: Cost 1 vsldoi8 RHS, RHS - 1638321462U, // <6,u,u,6>: Cost 1 vspltisw2 RHS - 1235676488U, // <6,u,u,7>: Cost 1 vmrglw RHS, RHS - 1235673249U, // <6,u,u,u>: Cost 1 vmrglw RHS, LHS - 3248930816U, // <7,0,0,0>: Cost 2 vsldoi12 RHS, <0,0,0,0> - 3248930826U, // <7,0,0,1>: Cost 2 vsldoi12 RHS, <0,0,1,1> - 4049094586U, // <7,0,0,2>: Cost 4 vsldoi4 <3,7,0,0>, <2,6,3,7> - 3389805716U, // <7,0,0,3>: Cost 3 vmrglw <5,6,7,0>, <7,2,0,3> - 3248930853U, // <7,0,0,4>: Cost 3 vsldoi12 RHS, <0,0,4,1> - 4072984674U, // <7,0,0,5>: Cost 3 vsldoi4 <7,7,0,0>, <5,6,7,0> - 4067013453U, // <7,0,0,6>: Cost 3 vsldoi4 <6,7,0,0>, <6,7,0,0> - 3389806044U, // <7,0,0,7>: Cost 3 vmrglw <5,6,7,0>, <7,6,0,7> - 3248930889U, // <7,0,0,u>: Cost 2 vsldoi12 RHS, <0,0,u,1> - 2993274982U, // <7,0,1,0>: Cost 2 vsldoi4 <6,7,0,1>, LHS - 3248930907U, // <7,0,1,1>: Cost 3 vsldoi12 RHS, <0,1,1,1> - 1101447270U, // <7,0,1,2>: Cost 1 vsldoi12 RHS, LHS - 4049103555U, // <7,0,1,3>: Cost 3 vsldoi4 <3,7,0,1>, <3,7,0,1> - 2993278262U, // <7,0,1,4>: Cost 2 vsldoi4 <6,7,0,1>, RHS - 4067020804U, // <7,0,1,5>: Cost 3 vsldoi4 <6,7,0,1>, <5,5,5,5> - 2993279822U, // <7,0,1,6>: Cost 2 vsldoi4 <6,7,0,1>, <6,7,0,1> - 4067021816U, // <7,0,1,7>: Cost 3 vsldoi4 <6,7,0,1>, <7,0,1,0> - 1101447324U, // <7,0,1,u>: Cost 1 vsldoi12 RHS, LHS - 3248930981U, // <7,0,2,0>: Cost 3 vsldoi12 RHS, <0,2,0,3> - 3237429425U, // <7,0,2,1>: Cost 3 vsldoi12 <2,6,3,7>, <0,2,1,6> - 4195108456U, // <7,0,2,2>: Cost 3 vsldoi8 <5,6,7,0>, <2,2,2,2> - 4195108518U, // <7,0,2,3>: Cost 3 vsldoi8 <5,6,7,0>, <2,3,0,1> - 3237429452U, // <7,0,2,4>: Cost 4 vsldoi12 <2,6,3,7>, <0,2,4,6> - 3248931026U, // <7,0,2,5>: Cost 4 vsldoi12 RHS, <0,2,5,3> - 4195108794U, // <7,0,2,6>: Cost 3 vsldoi8 <5,6,7,0>, <2,6,3,7> - 3243180260U, // <7,0,2,7>: Cost 4 vsldoi12 <3,6,0,7>, <0,2,7,3> - 3237429488U, // <7,0,2,u>: Cost 3 vsldoi12 <2,6,3,7>, <0,2,u,6> - 4195109014U, // <7,0,3,0>: Cost 3 vsldoi8 <5,6,7,0>, <3,0,1,2> - 3248931068U, // <7,0,3,1>: Cost 3 vsldoi12 RHS, <0,3,1,0> - 3248931077U, // <7,0,3,2>: Cost 4 vsldoi12 RHS, <0,3,2,0> - 4195109276U, // <7,0,3,3>: Cost 3 vsldoi8 <5,6,7,0>, <3,3,3,3> - 4195109378U, // <7,0,3,4>: Cost 3 vsldoi8 <5,6,7,0>, <3,4,5,6> - 4195109469U, // <7,0,3,5>: Cost 3 vsldoi8 <5,6,7,0>, <3,5,6,7> - 4183165616U, // <7,0,3,6>: Cost 3 vsldoi8 <3,6,7,0>, <3,6,7,0> - 3243180338U, // <7,0,3,7>: Cost 4 vsldoi12 <3,6,0,7>, <0,3,7,0> - 3248931131U, // <7,0,3,u>: Cost 3 vsldoi12 RHS, <0,3,u,0> - 4195109778U, // <7,0,4,0>: Cost 3 vsldoi8 <5,6,7,0>, <4,0,5,1> - 3248931154U, // <7,0,4,1>: Cost 2 vsldoi12 RHS, <0,4,1,5> - 4049127354U, // <7,0,4,2>: Cost 4 vsldoi4 <3,7,0,4>, <2,6,3,7> - 4049128134U, // <7,0,4,3>: Cost 4 vsldoi4 <3,7,0,4>, <3,7,0,4> - 3248931181U, // <7,0,4,4>: Cost 3 vsldoi12 RHS, <0,4,4,5> - 3121368374U, // <7,0,4,5>: Cost 2 vsldoi8 <5,6,7,0>, RHS - 4067046225U, // <7,0,4,6>: Cost 3 vsldoi4 <6,7,0,4>, <6,7,0,4> - 3266101828U, // <7,0,4,7>: Cost 3 vmrghw <7,4,5,6>, <0,7,1,4> - 3248931217U, // <7,0,4,u>: Cost 2 vsldoi12 RHS, <0,4,u,5> - 4195110516U, // <7,0,5,0>: Cost 3 vsldoi8 <5,6,7,0>, <5,0,6,1> - 3266756710U, // <7,0,5,1>: Cost 3 vmrghw <7,5,5,5>, LHS - 4195110635U, // <7,0,5,2>: Cost 4 vsldoi8 <5,6,7,0>, <5,2,1,3> - 3248931248U, // <7,0,5,3>: Cost 4 vsldoi12 RHS, <0,5,3,0> - 4195110844U, // <7,0,5,4>: Cost 3 vsldoi8 <5,6,7,0>, <5,4,6,5> - 4195110916U, // <7,0,5,5>: Cost 3 vsldoi8 <5,6,7,0>, <5,5,5,5> - 3121369186U, // <7,0,5,6>: Cost 2 vsldoi8 <5,6,7,0>, <5,6,7,0> - 4195111037U, // <7,0,5,7>: Cost 4 vsldoi8 <5,6,7,0>, <5,7,1,0> - 3122696452U, // <7,0,5,u>: Cost 2 vsldoi8 <5,u,7,0>, <5,u,7,0> - 4197101909U, // <7,0,6,0>: Cost 3 vsldoi8 <6,0,7,0>, <6,0,7,0> - 3248931318U, // <7,0,6,1>: Cost 3 vsldoi12 RHS, <0,6,1,7> - 4195111418U, // <7,0,6,2>: Cost 3 vsldoi8 <5,6,7,0>, <6,2,7,3> - 4199092808U, // <7,0,6,3>: Cost 3 vsldoi8 <6,3,7,0>, <6,3,7,0> - 3248931345U, // <7,0,6,4>: Cost 4 vsldoi12 RHS, <0,6,4,7> - 3248931354U, // <7,0,6,5>: Cost 4 vsldoi12 RHS, <0,6,5,7> - 4195111736U, // <7,0,6,6>: Cost 3 vsldoi8 <5,6,7,0>, <6,6,6,6> - 4195111758U, // <7,0,6,7>: Cost 3 vsldoi8 <5,6,7,0>, <6,7,0,1> - 3248931381U, // <7,0,6,u>: Cost 3 vsldoi12 RHS, <0,6,u,7> - 4195111930U, // <7,0,7,0>: Cost 3 vsldoi8 <5,6,7,0>, <7,0,1,2> - 2194505830U, // <7,0,7,1>: Cost 2 vmrghw <7,7,7,7>, LHS - 4195112084U, // <7,0,7,2>: Cost 3 vsldoi8 <5,6,7,0>, <7,2,0,3> - 3243180632U, // <7,0,7,3>: Cost 4 vsldoi12 <3,6,0,7>, <0,7,3,6> - 4195112294U, // <7,0,7,4>: Cost 3 vsldoi8 <5,6,7,0>, <7,4,5,6> - 4195112385U, // <7,0,7,5>: Cost 3 vsldoi8 <5,6,7,0>, <7,5,6,7> - 4195112412U, // <7,0,7,6>: Cost 3 vsldoi8 <5,6,7,0>, <7,6,0,7> - 4195112486U, // <7,0,7,7>: Cost 3 vsldoi8 <5,6,7,0>, <7,7,0,0> - 2194506397U, // <7,0,7,u>: Cost 2 vmrghw <7,7,7,7>, LHS - 2993332326U, // <7,0,u,0>: Cost 2 vsldoi4 <6,7,0,u>, LHS - 3248931474U, // <7,0,u,1>: Cost 2 vsldoi12 RHS, <0,u,1,1> - 1101447837U, // <7,0,u,2>: Cost 1 vsldoi12 RHS, LHS - 4049160906U, // <7,0,u,3>: Cost 3 vsldoi4 <3,7,0,u>, <3,7,0,u> - 2993335606U, // <7,0,u,4>: Cost 2 vsldoi4 <6,7,0,u>, RHS - 3121371290U, // <7,0,u,5>: Cost 2 vsldoi8 <5,6,7,0>, RHS - 2993337173U, // <7,0,u,6>: Cost 2 vsldoi4 <6,7,0,u>, <6,7,0,u> - 4195113216U, // <7,0,u,7>: Cost 3 vsldoi8 <5,6,7,0>, - 1101447891U, // <7,0,u,u>: Cost 1 vsldoi12 RHS, LHS - 4197769226U, // <7,1,0,0>: Cost 3 vsldoi8 <6,1,7,1>, <0,0,1,1> - 3248931555U, // <7,1,0,1>: Cost 3 vsldoi12 RHS, <1,0,1,1> - 3248931564U, // <7,1,0,2>: Cost 3 vsldoi12 RHS, <1,0,2,1> - 3248931572U, // <7,1,0,3>: Cost 4 vsldoi12 RHS, <1,0,3,0> - 4079029558U, // <7,1,0,4>: Cost 3 vsldoi4 , RHS - 3389800786U, // <7,1,0,5>: Cost 3 vmrglw <5,6,7,0>, <0,4,1,5> - 3389800868U, // <7,1,0,6>: Cost 3 vmrglw <5,6,7,0>, <0,5,1,6> - 4079031290U, // <7,1,0,7>: Cost 3 vsldoi4 , <7,0,1,2> - 3248931618U, // <7,1,0,u>: Cost 3 vsldoi12 RHS, <1,0,u,1> - 3248931627U, // <7,1,1,0>: Cost 3 vsldoi12 RHS, <1,1,0,1> - 3248931636U, // <7,1,1,1>: Cost 2 vsldoi12 RHS, <1,1,1,1> - 3248931646U, // <7,1,1,2>: Cost 3 vsldoi12 RHS, <1,1,2,2> - 4049177292U, // <7,1,1,3>: Cost 4 vsldoi4 <3,7,1,1>, <3,7,1,1> - 3248931667U, // <7,1,1,4>: Cost 3 vsldoi12 RHS, <1,1,4,5> - 3248931676U, // <7,1,1,5>: Cost 3 vsldoi12 RHS, <1,1,5,5> - 4067095383U, // <7,1,1,6>: Cost 3 vsldoi4 <6,7,1,1>, <6,7,1,1> - 3231310698U, // <7,1,1,7>: Cost 4 vsldoi12 <1,6,1,7>, <1,1,7,1> - 3248931636U, // <7,1,1,u>: Cost 2 vsldoi12 RHS, <1,1,1,1> - 3248931708U, // <7,1,2,0>: Cost 3 vsldoi12 RHS, <1,2,0,1> - 3248931719U, // <7,1,2,1>: Cost 3 vsldoi12 RHS, <1,2,1,3> - 3248931728U, // <7,1,2,2>: Cost 3 vsldoi12 RHS, <1,2,2,3> - 3248931734U, // <7,1,2,3>: Cost 2 vsldoi12 RHS, <1,2,3,0> - 3248931748U, // <7,1,2,4>: Cost 3 vsldoi12 RHS, <1,2,4,5> - 3248931755U, // <7,1,2,5>: Cost 3 vsldoi12 RHS, <1,2,5,3> - 4067103576U, // <7,1,2,6>: Cost 3 vsldoi4 <6,7,1,2>, <6,7,1,2> - 3272819642U, // <7,1,2,7>: Cost 3 vsldoi12 RHS, <1,2,7,0> - 3248931779U, // <7,1,2,u>: Cost 2 vsldoi12 RHS, <1,2,u,0> - 4179192011U, // <7,1,3,0>: Cost 4 vsldoi8 <3,0,7,1>, <3,0,7,1> - 3393142794U, // <7,1,3,1>: Cost 3 vmrglw <6,2,7,3>, <0,0,1,1> - 3389827222U, // <7,1,3,2>: Cost 3 vmrglw <5,6,7,3>, <3,0,1,2> - 3248931815U, // <7,1,3,3>: Cost 4 vsldoi12 RHS, <1,3,3,0> - 3248931824U, // <7,1,3,4>: Cost 4 vsldoi12 RHS, <1,3,4,0> - 3393143122U, // <7,1,3,5>: Cost 3 vmrglw <6,2,7,3>, <0,4,1,5> - 3229688841U, // <7,1,3,6>: Cost 4 vsldoi12 <1,3,6,7>, <1,3,6,7> - 3367265487U, // <7,1,3,7>: Cost 4 vmrglw <1,u,7,3>, <1,6,1,7> - 3393142801U, // <7,1,3,u>: Cost 3 vmrglw <6,2,7,3>, <0,0,1,u> - 4200426386U, // <7,1,4,0>: Cost 3 vsldoi8 <6,5,7,1>, <4,0,5,1> - 3248931883U, // <7,1,4,1>: Cost 3 vsldoi12 RHS, <1,4,1,5> - 3248931892U, // <7,1,4,2>: Cost 3 vsldoi12 RHS, <1,4,2,5> - 3248931896U, // <7,1,4,3>: Cost 4 vsldoi12 RHS, <1,4,3,0> - 4079062326U, // <7,1,4,4>: Cost 3 vsldoi4 , RHS - 3248931920U, // <7,1,4,5>: Cost 3 vsldoi12 RHS, <1,4,5,6> - 3231310936U, // <7,1,4,6>: Cost 4 vsldoi12 <1,6,1,7>, <1,4,6,5> - 4079064422U, // <7,1,4,7>: Cost 3 vsldoi4 , <7,4,5,6> - 3248931946U, // <7,1,4,u>: Cost 3 vsldoi12 RHS, <1,4,u,5> - 3248931951U, // <7,1,5,0>: Cost 3 vsldoi12 RHS, <1,5,0,1> - 3231605885U, // <7,1,5,1>: Cost 4 vsldoi12 <1,6,5,7>, <1,5,1,6> - 3237430406U, // <7,1,5,2>: Cost 4 vsldoi12 <2,6,3,7>, <1,5,2,6> - 3248931977U, // <7,1,5,3>: Cost 4 vsldoi12 RHS, <1,5,3,0> - 3248931991U, // <7,1,5,4>: Cost 3 vsldoi12 RHS, <1,5,4,5> - 3392495954U, // <7,1,5,5>: Cost 3 vmrglw <6,1,7,5>, <0,4,1,5> - 4195119203U, // <7,1,5,6>: Cost 3 vsldoi8 <5,6,7,1>, <5,6,7,1> - 3255198894U, // <7,1,5,7>: Cost 4 vsldoi12 <5,6,1,7>, <1,5,7,1> - 3248932023U, // <7,1,5,u>: Cost 3 vsldoi12 RHS, <1,5,u,1> - 4197110102U, // <7,1,6,0>: Cost 3 vsldoi8 <6,0,7,1>, <6,0,7,1> - 3231311055U, // <7,1,6,1>: Cost 3 vsldoi12 <1,6,1,7>, <1,6,1,7> - 3248932056U, // <7,1,6,2>: Cost 3 vsldoi12 RHS, <1,6,2,7> - 3231458529U, // <7,1,6,3>: Cost 4 vsldoi12 <1,6,3,7>, <1,6,3,7> - 3231532266U, // <7,1,6,4>: Cost 4 vsldoi12 <1,6,4,7>, <1,6,4,7> - 3231606003U, // <7,1,6,5>: Cost 3 vsldoi12 <1,6,5,7>, <1,6,5,7> - 3231679740U, // <7,1,6,6>: Cost 4 vsldoi12 <1,6,6,7>, <1,6,6,7> - 3272819966U, // <7,1,6,7>: Cost 3 vsldoi12 RHS, <1,6,7,0> - 3231827214U, // <7,1,6,u>: Cost 3 vsldoi12 <1,6,u,7>, <1,6,u,7> - 4079083622U, // <7,1,7,0>: Cost 3 vsldoi4 , LHS - 3395829770U, // <7,1,7,1>: Cost 3 vmrglw <6,6,7,7>, <0,0,1,1> - 3391190010U, // <7,1,7,2>: Cost 3 vmrglw <5,u,7,7>, <7,0,1,2> - 3395829934U, // <7,1,7,3>: Cost 4 vmrglw <6,6,7,7>, <0,2,1,3> - 4079086902U, // <7,1,7,4>: Cost 3 vsldoi4 , RHS - 3395830098U, // <7,1,7,5>: Cost 3 vmrglw <6,6,7,7>, <0,4,1,5> - 3375923377U, // <7,1,7,6>: Cost 4 vmrglw <3,3,7,7>, <0,2,1,6> - 4208391788U, // <7,1,7,7>: Cost 3 vsldoi8 <7,u,7,1>, <7,7,7,7> - 3395829777U, // <7,1,7,u>: Cost 3 vmrglw <6,6,7,7>, <0,0,1,u> - 3248932194U, // <7,1,u,0>: Cost 3 vsldoi12 RHS, <1,u,0,1> - 3248931636U, // <7,1,u,1>: Cost 2 vsldoi12 RHS, <1,1,1,1> - 3248932212U, // <7,1,u,2>: Cost 3 vsldoi12 RHS, <1,u,2,1> - 3248932220U, // <7,1,u,3>: Cost 2 vsldoi12 RHS, <1,u,3,0> - 3248932234U, // <7,1,u,4>: Cost 3 vsldoi12 RHS, <1,u,4,5> - 3232933269U, // <7,1,u,5>: Cost 3 vsldoi12 <1,u,5,7>, <1,u,5,7> - 4067152734U, // <7,1,u,6>: Cost 3 vsldoi4 <6,7,1,u>, <6,7,1,u> - 3272820128U, // <7,1,u,7>: Cost 3 vsldoi12 RHS, <1,u,7,0> - 3248932265U, // <7,1,u,u>: Cost 2 vsldoi12 RHS, <1,u,u,0> - 4049240166U, // <7,2,0,0>: Cost 4 vsldoi4 <3,7,2,0>, LHS - 3248932285U, // <7,2,0,1>: Cost 3 vsldoi12 RHS, <2,0,1,2> - 3248932293U, // <7,2,0,2>: Cost 3 vsldoi12 RHS, <2,0,2,1> - 2316058726U, // <7,2,0,3>: Cost 2 vmrglw <5,6,7,0>, LHS - 4049243446U, // <7,2,0,4>: Cost 4 vsldoi4 <3,7,2,0>, RHS - 3248932320U, // <7,2,0,5>: Cost 4 vsldoi12 RHS, <2,0,5,1> - 3237430761U, // <7,2,0,6>: Cost 3 vsldoi12 <2,6,3,7>, <2,0,6,1> - 3263121386U, // <7,2,0,7>: Cost 3 vmrghw <7,0,1,2>, <2,7,0,1> - 2316058731U, // <7,2,0,u>: Cost 2 vmrglw <5,6,7,0>, LHS - 3248932356U, // <7,2,1,0>: Cost 4 vsldoi12 RHS, <2,1,0,1> - 3248932365U, // <7,2,1,1>: Cost 4 vsldoi12 RHS, <2,1,1,1> - 3248932373U, // <7,2,1,2>: Cost 4 vsldoi12 RHS, <2,1,2,0> - 3248932383U, // <7,2,1,3>: Cost 3 vsldoi12 RHS, <2,1,3,1> - 3248932396U, // <7,2,1,4>: Cost 4 vsldoi12 RHS, <2,1,4,5> - 3236767286U, // <7,2,1,5>: Cost 5 vsldoi12 <2,5,3,7>, <2,1,5,6> - 3237430841U, // <7,2,1,6>: Cost 4 vsldoi12 <2,6,3,7>, <2,1,6,0> - 4197778722U, // <7,2,1,7>: Cost 4 vsldoi8 <6,1,7,2>, <1,7,2,0> - 3248932428U, // <7,2,1,u>: Cost 3 vsldoi12 RHS, <2,1,u,1> - 3248932437U, // <7,2,2,0>: Cost 3 vsldoi12 RHS, <2,2,0,1> - 3248932446U, // <7,2,2,1>: Cost 4 vsldoi12 RHS, <2,2,1,1> - 3248932456U, // <7,2,2,2>: Cost 2 vsldoi12 RHS, <2,2,2,2> - 3248932466U, // <7,2,2,3>: Cost 2 vsldoi12 RHS, <2,2,3,3> - 3248932477U, // <7,2,2,4>: Cost 3 vsldoi12 RHS, <2,2,4,5> - 3248932483U, // <7,2,2,5>: Cost 4 vsldoi12 RHS, <2,2,5,2> - 3237430928U, // <7,2,2,6>: Cost 3 vsldoi12 <2,6,3,7>, <2,2,6,6> - 3237357205U, // <7,2,2,7>: Cost 4 vsldoi12 <2,6,2,7>, <2,2,7,2> - 3248932511U, // <7,2,2,u>: Cost 2 vsldoi12 RHS, <2,2,u,3> - 3248932518U, // <7,2,3,0>: Cost 2 vsldoi12 RHS, <2,3,0,1> - 3248932527U, // <7,2,3,1>: Cost 3 vsldoi12 RHS, <2,3,1,1> - 3237430973U, // <7,2,3,2>: Cost 3 vsldoi12 <2,6,3,7>, <2,3,2,6> - 2319401062U, // <7,2,3,3>: Cost 2 vmrglw <6,2,7,3>, LHS - 3248932558U, // <7,2,3,4>: Cost 2 vsldoi12 RHS, <2,3,4,5> - 3248932567U, // <7,2,3,5>: Cost 3 vsldoi12 RHS, <2,3,5,5> - 4067185506U, // <7,2,3,6>: Cost 3 vsldoi4 <6,7,2,3>, <6,7,2,3> - 3393148398U, // <7,2,3,7>: Cost 3 vmrglw <6,2,7,3>, <7,6,2,7> - 3248932590U, // <7,2,3,u>: Cost 2 vsldoi12 RHS, <2,3,u,1> - 4049272934U, // <7,2,4,0>: Cost 4 vsldoi4 <3,7,2,4>, LHS - 3248932612U, // <7,2,4,1>: Cost 4 vsldoi12 RHS, <2,4,1,5> - 3248932621U, // <7,2,4,2>: Cost 3 vsldoi12 RHS, <2,4,2,5> - 2316091494U, // <7,2,4,3>: Cost 2 vmrglw <5,6,7,4>, LHS - 4049276214U, // <7,2,4,4>: Cost 4 vsldoi4 <3,7,2,4>, RHS - 3248932649U, // <7,2,4,5>: Cost 3 vsldoi12 RHS, <2,4,5,6> - 3237431089U, // <7,2,4,6>: Cost 3 vsldoi12 <2,6,3,7>, <2,4,6,5> - 3389834456U, // <7,2,4,7>: Cost 4 vmrglw <5,6,7,4>, <1,6,2,7> - 2316091499U, // <7,2,4,u>: Cost 2 vmrglw <5,6,7,4>, LHS - 3248932680U, // <7,2,5,0>: Cost 4 vsldoi12 RHS, <2,5,0,1> - 3248932690U, // <7,2,5,1>: Cost 4 vsldoi12 RHS, <2,5,1,2> - 3248932699U, // <7,2,5,2>: Cost 4 vsldoi12 RHS, <2,5,2,2> - 3248932712U, // <7,2,5,3>: Cost 3 vsldoi12 RHS, <2,5,3,6> - 3248932720U, // <7,2,5,4>: Cost 4 vsldoi12 RHS, <2,5,4,5> - 4195127300U, // <7,2,5,5>: Cost 4 vsldoi8 <5,6,7,2>, <5,5,5,5> - 4195127396U, // <7,2,5,6>: Cost 3 vsldoi8 <5,6,7,2>, <5,6,7,2> - 3237357452U, // <7,2,5,7>: Cost 5 vsldoi12 <2,6,2,7>, <2,5,7,6> - 3248932757U, // <7,2,5,u>: Cost 3 vsldoi12 RHS, <2,5,u,6> - 4049289318U, // <7,2,6,0>: Cost 3 vsldoi4 <3,7,2,6>, LHS - 4197781928U, // <7,2,6,1>: Cost 3 vsldoi8 <6,1,7,2>, <6,1,7,2> - 3237357489U, // <7,2,6,2>: Cost 3 vsldoi12 <2,6,2,7>, <2,6,2,7> - 3237431226U, // <7,2,6,3>: Cost 2 vsldoi12 <2,6,3,7>, <2,6,3,7> - 4049292598U, // <7,2,6,4>: Cost 3 vsldoi4 <3,7,2,6>, RHS - 3237578700U, // <7,2,6,5>: Cost 4 vsldoi12 <2,6,5,7>, <2,6,5,7> - 4067210085U, // <7,2,6,6>: Cost 3 vsldoi4 <6,7,2,6>, <6,7,2,6> - 3237357534U, // <7,2,6,7>: Cost 4 vsldoi12 <2,6,2,7>, <2,6,7,7> - 3237799911U, // <7,2,6,u>: Cost 2 vsldoi12 <2,6,u,7>, <2,6,u,7> - 3272820714U, // <7,2,7,0>: Cost 3 vsldoi12 RHS, <2,7,0,1> - 3248932856U, // <7,2,7,1>: Cost 4 vsldoi12 RHS, <2,7,1,6> - 3395831400U, // <7,2,7,2>: Cost 3 vmrglw <6,6,7,7>, <2,2,2,2> - 2322088038U, // <7,2,7,3>: Cost 2 vmrglw <6,6,7,7>, LHS - 3237357586U, // <7,2,7,4>: Cost 4 vsldoi12 <2,6,2,7>, <2,7,4,5> - 3395830836U, // <7,2,7,5>: Cost 4 vmrglw <6,6,7,7>, <1,4,2,5> - 3268249530U, // <7,2,7,6>: Cost 3 vmrghw <7,7,7,7>, <2,6,3,7> - 3371943857U, // <7,2,7,7>: Cost 4 vmrglw <2,6,7,7>, <2,6,2,7> - 2322088043U, // <7,2,7,u>: Cost 2 vmrglw <6,6,7,7>, LHS - 3248932923U, // <7,2,u,0>: Cost 2 vsldoi12 RHS, <2,u,0,1> - 3248932932U, // <7,2,u,1>: Cost 3 vsldoi12 RHS, <2,u,1,1> - 3248932456U, // <7,2,u,2>: Cost 2 vsldoi12 RHS, <2,2,2,2> - 3238758492U, // <7,2,u,3>: Cost 2 vsldoi12 <2,u,3,7>, <2,u,3,7> - 3248932963U, // <7,2,u,4>: Cost 2 vsldoi12 RHS, <2,u,4,5> - 3248932972U, // <7,2,u,5>: Cost 3 vsldoi12 RHS, <2,u,5,5> - 3237431409U, // <7,2,u,6>: Cost 3 vsldoi12 <2,6,3,7>, <2,u,6,1> - 3272820857U, // <7,2,u,7>: Cost 3 vsldoi12 RHS, <2,u,7,0> - 3239127177U, // <7,2,u,u>: Cost 2 vsldoi12 <2,u,u,7>, <2,u,u,7> - 3248933003U, // <7,3,0,0>: Cost 3 vsldoi12 RHS, <3,0,0,0> - 3248933014U, // <7,3,0,1>: Cost 2 vsldoi12 RHS, <3,0,1,2> - 4043343876U, // <7,3,0,2>: Cost 3 vsldoi4 <2,7,3,0>, <2,7,3,0> - 3248933031U, // <7,3,0,3>: Cost 3 vsldoi12 RHS, <3,0,3,1> - 3248933040U, // <7,3,0,4>: Cost 3 vsldoi12 RHS, <3,0,4,1> - 3248933053U, // <7,3,0,5>: Cost 4 vsldoi12 RHS, <3,0,5,5> - 4067234664U, // <7,3,0,6>: Cost 3 vsldoi4 <6,7,3,0>, <6,7,3,0> - 3389802426U, // <7,3,0,7>: Cost 3 vmrglw <5,6,7,0>, <2,6,3,7> - 3248933077U, // <7,3,0,u>: Cost 2 vsldoi12 RHS, <3,0,u,2> - 3248933084U, // <7,3,1,0>: Cost 4 vsldoi12 RHS, <3,1,0,0> - 3248933094U, // <7,3,1,1>: Cost 3 vsldoi12 RHS, <3,1,1,1> - 3248933105U, // <7,3,1,2>: Cost 3 vsldoi12 RHS, <3,1,2,3> - 3248933111U, // <7,3,1,3>: Cost 4 vsldoi12 RHS, <3,1,3,0> - 3248933120U, // <7,3,1,4>: Cost 4 vsldoi12 RHS, <3,1,4,0> - 3248933129U, // <7,3,1,5>: Cost 4 vsldoi12 RHS, <3,1,5,0> - 3231312147U, // <7,3,1,6>: Cost 4 vsldoi12 <1,6,1,7>, <3,1,6,1> - 3237431580U, // <7,3,1,7>: Cost 4 vsldoi12 <2,6,3,7>, <3,1,7,1> - 3248933159U, // <7,3,1,u>: Cost 3 vsldoi12 RHS, <3,1,u,3> - 3248933168U, // <7,3,2,0>: Cost 3 vsldoi12 RHS, <3,2,0,3> - 3248933176U, // <7,3,2,1>: Cost 4 vsldoi12 RHS, <3,2,1,2> - 3248933185U, // <7,3,2,2>: Cost 3 vsldoi12 RHS, <3,2,2,2> - 3248933192U, // <7,3,2,3>: Cost 3 vsldoi12 RHS, <3,2,3,0> - 3248933204U, // <7,3,2,4>: Cost 3 vsldoi12 RHS, <3,2,4,3> - 3248933213U, // <7,3,2,5>: Cost 4 vsldoi12 RHS, <3,2,5,3> - 3237431654U, // <7,3,2,6>: Cost 3 vsldoi12 <2,6,3,7>, <3,2,6,3> - 3237431663U, // <7,3,2,7>: Cost 3 vsldoi12 <2,6,3,7>, <3,2,7,3> - 3248933237U, // <7,3,2,u>: Cost 3 vsldoi12 RHS, <3,2,u,0> - 3248933246U, // <7,3,3,0>: Cost 3 vsldoi12 RHS, <3,3,0,0> - 3248933256U, // <7,3,3,1>: Cost 4 vsldoi12 RHS, <3,3,1,1> - 4180535663U, // <7,3,3,2>: Cost 3 vsldoi8 <3,2,7,3>, <3,2,7,3> - 3248933276U, // <7,3,3,3>: Cost 2 vsldoi12 RHS, <3,3,3,3> - 3248933286U, // <7,3,3,4>: Cost 3 vsldoi12 RHS, <3,3,4,4> - 3248933294U, // <7,3,3,5>: Cost 4 vsldoi12 RHS, <3,3,5,3> - 4067259243U, // <7,3,3,6>: Cost 3 vsldoi4 <6,7,3,3>, <6,7,3,3> - 3237431748U, // <7,3,3,7>: Cost 3 vsldoi12 <2,6,3,7>, <3,3,7,7> - 3248933276U, // <7,3,3,u>: Cost 2 vsldoi12 RHS, <3,3,3,3> - 3248933328U, // <7,3,4,0>: Cost 3 vsldoi12 RHS, <3,4,0,1> - 3248933338U, // <7,3,4,1>: Cost 3 vsldoi12 RHS, <3,4,1,2> - 4043376648U, // <7,3,4,2>: Cost 3 vsldoi4 <2,7,3,4>, <2,7,3,4> - 3248933359U, // <7,3,4,3>: Cost 3 vsldoi12 RHS, <3,4,3,5> - 3248933367U, // <7,3,4,4>: Cost 3 vsldoi12 RHS, <3,4,4,4> - 3248933378U, // <7,3,4,5>: Cost 2 vsldoi12 RHS, <3,4,5,6> - 4198452601U, // <7,3,4,6>: Cost 3 vsldoi8 <6,2,7,3>, <4,6,5,2> - 3389835194U, // <7,3,4,7>: Cost 3 vmrglw <5,6,7,4>, <2,6,3,7> - 3248933405U, // <7,3,4,u>: Cost 2 vsldoi12 RHS, <3,4,u,6> - 3248933409U, // <7,3,5,0>: Cost 4 vsldoi12 RHS, <3,5,0,1> - 4198452879U, // <7,3,5,1>: Cost 4 vsldoi8 <6,2,7,3>, <5,1,0,1> - 3248933427U, // <7,3,5,2>: Cost 4 vsldoi12 RHS, <3,5,2,1> - 3248933438U, // <7,3,5,3>: Cost 4 vsldoi12 RHS, <3,5,3,3> - 3248933449U, // <7,3,5,4>: Cost 4 vsldoi12 RHS, <3,5,4,5> - 3248933458U, // <7,3,5,5>: Cost 3 vsldoi12 RHS, <3,5,5,5> - 4195135589U, // <7,3,5,6>: Cost 3 vsldoi8 <5,6,7,3>, <5,6,7,3> - 3237431909U, // <7,3,5,7>: Cost 4 vsldoi12 <2,6,3,7>, <3,5,7,6> - 4196462855U, // <7,3,5,u>: Cost 3 vsldoi8 <5,u,7,3>, <5,u,7,3> - 3243182712U, // <7,3,6,0>: Cost 3 vsldoi12 <3,6,0,7>, <3,6,0,7> - 3243256449U, // <7,3,6,1>: Cost 4 vsldoi12 <3,6,1,7>, <3,6,1,7> - 3124711930U, // <7,3,6,2>: Cost 2 vsldoi8 <6,2,7,3>, <6,2,7,3> - 3243403923U, // <7,3,6,3>: Cost 3 vsldoi12 <3,6,3,7>, <3,6,3,7> - 3243477660U, // <7,3,6,4>: Cost 3 vsldoi12 <3,6,4,7>, <3,6,4,7> - 3243551397U, // <7,3,6,5>: Cost 4 vsldoi12 <3,6,5,7>, <3,6,5,7> - 4198454032U, // <7,3,6,6>: Cost 3 vsldoi8 <6,2,7,3>, <6,6,2,2> - 3237431991U, // <7,3,6,7>: Cost 3 vsldoi12 <2,6,3,7>, <3,6,7,7> - 3128693728U, // <7,3,6,u>: Cost 2 vsldoi8 <6,u,7,3>, <6,u,7,3> - 3237432003U, // <7,3,7,0>: Cost 3 vsldoi12 <2,6,3,7>, <3,7,0,1> - 3237432012U, // <7,3,7,1>: Cost 4 vsldoi12 <2,6,3,7>, <3,7,1,1> - 3237432026U, // <7,3,7,2>: Cost 3 vsldoi12 <2,6,3,7>, <3,7,2,6> - 4198454554U, // <7,3,7,3>: Cost 3 vsldoi8 <6,2,7,3>, <7,3,6,2> - 3237432043U, // <7,3,7,4>: Cost 3 vsldoi12 <2,6,3,7>, <3,7,4,5> - 3248933620U, // <7,3,7,5>: Cost 4 vsldoi12 RHS, <3,7,5,5> - 4198454766U, // <7,3,7,6>: Cost 3 vsldoi8 <6,2,7,3>, <7,6,2,7> - 3375925178U, // <7,3,7,7>: Cost 3 vmrglw <3,3,7,7>, <2,6,3,7> - 3237432075U, // <7,3,7,u>: Cost 3 vsldoi12 <2,6,3,7>, <3,7,u,1> - 3244509978U, // <7,3,u,0>: Cost 3 vsldoi12 <3,u,0,7>, <3,u,0,7> - 3248933662U, // <7,3,u,1>: Cost 2 vsldoi12 RHS, <3,u,1,2> - 3136657324U, // <7,3,u,2>: Cost 2 vsldoi8 , - 3248933276U, // <7,3,u,3>: Cost 2 vsldoi12 RHS, <3,3,3,3> - 3244804926U, // <7,3,u,4>: Cost 3 vsldoi12 <3,u,4,7>, <3,u,4,7> - 3248933702U, // <7,3,u,5>: Cost 2 vsldoi12 RHS, <3,u,5,6> - 3248933708U, // <7,3,u,6>: Cost 3 vsldoi12 RHS, <3,u,6,3> - 3237432149U, // <7,3,u,7>: Cost 3 vsldoi12 <2,6,3,7>, <3,u,7,3> - 3248933725U, // <7,3,u,u>: Cost 2 vsldoi12 RHS, <3,u,u,2> - 4195139584U, // <7,4,0,0>: Cost 3 vsldoi8 <5,6,7,4>, <0,0,0,0> - 3121397862U, // <7,4,0,1>: Cost 2 vsldoi8 <5,6,7,4>, LHS - 3248933751U, // <7,4,0,2>: Cost 4 vsldoi12 RHS, <4,0,2,1> - 3248933760U, // <7,4,0,3>: Cost 4 vsldoi12 RHS, <4,0,3,1> - 3389803728U, // <7,4,0,4>: Cost 3 vmrglw <5,6,7,0>, <4,4,4,4> - 3248933778U, // <7,4,0,5>: Cost 2 vsldoi12 RHS, <4,0,5,1> - 4067308401U, // <7,4,0,6>: Cost 3 vsldoi4 <6,7,4,0>, <6,7,4,0> - 3263122888U, // <7,4,0,7>: Cost 3 vmrghw <7,0,1,2>, <4,7,5,0> - 3250924461U, // <7,4,0,u>: Cost 2 vsldoi12 RHS, <4,0,u,1> - 3248933814U, // <7,4,1,0>: Cost 4 vsldoi12 RHS, <4,1,0,1> - 4195140404U, // <7,4,1,1>: Cost 3 vsldoi8 <5,6,7,4>, <1,1,1,1> - 3248933834U, // <7,4,1,2>: Cost 3 vsldoi12 RHS, <4,1,2,3> - 3248933840U, // <7,4,1,3>: Cost 4 vsldoi12 RHS, <4,1,3,0> - 3248933851U, // <7,4,1,4>: Cost 4 vsldoi12 RHS, <4,1,4,2> - 3248933858U, // <7,4,1,5>: Cost 3 vsldoi12 RHS, <4,1,5,0> - 4195140815U, // <7,4,1,6>: Cost 4 vsldoi8 <5,6,7,4>, <1,6,1,7> - 3394456220U, // <7,4,1,7>: Cost 4 vmrglw <6,4,7,1>, <3,6,4,7> - 3248933885U, // <7,4,1,u>: Cost 3 vsldoi12 RHS, <4,1,u,0> - 3248933897U, // <7,4,2,0>: Cost 4 vsldoi12 RHS, <4,2,0,3> - 3248933906U, // <7,4,2,1>: Cost 4 vsldoi12 RHS, <4,2,1,3> - 4195141224U, // <7,4,2,2>: Cost 3 vsldoi8 <5,6,7,4>, <2,2,2,2> - 4195141286U, // <7,4,2,3>: Cost 3 vsldoi8 <5,6,7,4>, <2,3,0,1> - 3248933933U, // <7,4,2,4>: Cost 3 vsldoi12 RHS, <4,2,4,3> - 3248933941U, // <7,4,2,5>: Cost 3 vsldoi12 RHS, <4,2,5,2> - 4195141562U, // <7,4,2,6>: Cost 3 vsldoi8 <5,6,7,4>, <2,6,3,7> - 3243478088U, // <7,4,2,7>: Cost 4 vsldoi12 <3,6,4,7>, <4,2,7,3> - 3248933969U, // <7,4,2,u>: Cost 3 vsldoi12 RHS, <4,2,u,3> - 4195141782U, // <7,4,3,0>: Cost 3 vsldoi8 <5,6,7,4>, <3,0,1,2> - 3248933986U, // <7,4,3,1>: Cost 4 vsldoi12 RHS, <4,3,1,2> - 3248933996U, // <7,4,3,2>: Cost 4 vsldoi12 RHS, <4,3,2,3> - 4195142044U, // <7,4,3,3>: Cost 3 vsldoi8 <5,6,7,4>, <3,3,3,3> - 4195142146U, // <7,4,3,4>: Cost 3 vsldoi8 <5,6,7,4>, <3,4,5,6> - 3248934020U, // <7,4,3,5>: Cost 3 vsldoi12 RHS, <4,3,5,0> - 4183198388U, // <7,4,3,6>: Cost 3 vsldoi8 <3,6,7,4>, <3,6,7,4> - 3243478170U, // <7,4,3,7>: Cost 4 vsldoi12 <3,6,4,7>, <4,3,7,4> - 3250924703U, // <7,4,3,u>: Cost 3 vsldoi12 RHS, <4,3,u,0> - 4195142546U, // <7,4,4,0>: Cost 3 vsldoi8 <5,6,7,4>, <4,0,5,1> - 3248934066U, // <7,4,4,1>: Cost 4 vsldoi12 RHS, <4,4,1,1> - 3248934076U, // <7,4,4,2>: Cost 4 vsldoi12 RHS, <4,4,2,2> - 3389838520U, // <7,4,4,3>: Cost 3 vmrglw <5,6,7,4>, <7,2,4,3> - 3248934096U, // <7,4,4,4>: Cost 2 vsldoi12 RHS, <4,4,4,4> - 3248934106U, // <7,4,4,5>: Cost 2 vsldoi12 RHS, <4,4,5,5> - 4067341173U, // <7,4,4,6>: Cost 3 vsldoi4 <6,7,4,4>, <6,7,4,4> - 3389838848U, // <7,4,4,7>: Cost 3 vmrglw <5,6,7,4>, <7,6,4,7> - 3250924789U, // <7,4,4,u>: Cost 2 vsldoi12 RHS, <4,4,u,5> - 2993602662U, // <7,4,5,0>: Cost 2 vsldoi4 <6,7,4,5>, LHS - 4067345204U, // <7,4,5,1>: Cost 3 vsldoi4 <6,7,4,5>, <1,1,1,1> - 4049430458U, // <7,4,5,2>: Cost 3 vsldoi4 <3,7,4,5>, <2,6,3,7> - 4049431275U, // <7,4,5,3>: Cost 3 vsldoi4 <3,7,4,5>, <3,7,4,5> - 2993605942U, // <7,4,5,4>: Cost 2 vsldoi4 <6,7,4,5>, RHS - 3248934182U, // <7,4,5,5>: Cost 3 vsldoi12 RHS, <4,5,5,0> - 1101450550U, // <7,4,5,6>: Cost 1 vsldoi12 RHS, RHS - 4067349498U, // <7,4,5,7>: Cost 3 vsldoi4 <6,7,4,5>, <7,0,1,2> - 1101450568U, // <7,4,5,u>: Cost 1 vsldoi12 RHS, RHS - 3248934225U, // <7,4,6,0>: Cost 4 vsldoi12 RHS, <4,6,0,7> - 3248934234U, // <7,4,6,1>: Cost 4 vsldoi12 RHS, <4,6,1,7> - 4195144186U, // <7,4,6,2>: Cost 3 vsldoi8 <5,6,7,4>, <6,2,7,3> - 4199125580U, // <7,4,6,3>: Cost 3 vsldoi8 <6,3,7,4>, <6,3,7,4> - 4199789213U, // <7,4,6,4>: Cost 3 vsldoi8 <6,4,7,4>, <6,4,7,4> - 3248934269U, // <7,4,6,5>: Cost 3 vsldoi12 RHS, <4,6,5,6> - 4195144504U, // <7,4,6,6>: Cost 3 vsldoi8 <5,6,7,4>, <6,6,6,6> - 4195144526U, // <7,4,6,7>: Cost 3 vsldoi8 <5,6,7,4>, <6,7,0,1> - 3248934297U, // <7,4,6,u>: Cost 3 vsldoi12 RHS, <4,6,u,7> - 4195144698U, // <7,4,7,0>: Cost 3 vsldoi8 <5,6,7,4>, <7,0,1,2> - 3243478438U, // <7,4,7,1>: Cost 4 vsldoi12 <3,6,4,7>, <4,7,1,2> - 4195144888U, // <7,4,7,2>: Cost 3 vsldoi8 <5,6,7,4>, <7,2,4,3> - 3243478460U, // <7,4,7,3>: Cost 4 vsldoi12 <3,6,4,7>, <4,7,3,6> - 4195145012U, // <7,4,7,4>: Cost 3 vsldoi8 <5,6,7,4>, <7,4,0,1> - 2194509110U, // <7,4,7,5>: Cost 2 vmrghw <7,7,7,7>, RHS - 4195145216U, // <7,4,7,6>: Cost 3 vsldoi8 <5,6,7,4>, <7,6,4,7> - 4195145294U, // <7,4,7,7>: Cost 3 vsldoi8 <5,6,7,4>, <7,7,4,4> - 2194509353U, // <7,4,7,u>: Cost 2 vmrghw <7,7,7,7>, RHS - 2993627238U, // <7,4,u,0>: Cost 2 vsldoi4 <6,7,4,u>, LHS - 3121403694U, // <7,4,u,1>: Cost 2 vsldoi8 <5,6,7,4>, LHS - 4049455034U, // <7,4,u,2>: Cost 3 vsldoi4 <3,7,4,u>, <2,6,3,7> - 4049455854U, // <7,4,u,3>: Cost 3 vsldoi4 <3,7,4,u>, <3,7,4,u> - 2993630518U, // <7,4,u,4>: Cost 2 vsldoi4 <6,7,4,u>, RHS - 3248934426U, // <7,4,u,5>: Cost 2 vsldoi12 RHS, <4,u,5,1> - 1101450793U, // <7,4,u,6>: Cost 1 vsldoi12 RHS, RHS - 4195145984U, // <7,4,u,7>: Cost 3 vsldoi8 <5,6,7,4>, - 1101450811U, // <7,4,u,u>: Cost 1 vsldoi12 RHS, RHS - 4055433318U, // <7,5,0,0>: Cost 3 vsldoi4 <4,7,5,0>, LHS - 3248934472U, // <7,5,0,1>: Cost 3 vsldoi12 RHS, <5,0,1,2> - 3248934482U, // <7,5,0,2>: Cost 4 vsldoi12 RHS, <5,0,2,3> - 3248934492U, // <7,5,0,3>: Cost 4 vsldoi12 RHS, <5,0,3,4> - 3248934498U, // <7,5,0,4>: Cost 3 vsldoi12 RHS, <5,0,4,1> - 3389803738U, // <7,5,0,5>: Cost 3 vmrglw <5,6,7,0>, <4,4,5,5> - 3389803010U, // <7,5,0,6>: Cost 3 vmrglw <5,6,7,0>, <3,4,5,6> - 4055438330U, // <7,5,0,7>: Cost 3 vsldoi4 <4,7,5,0>, <7,0,1,2> - 3248934534U, // <7,5,0,u>: Cost 3 vsldoi12 RHS, <5,0,u,1> - 3250925199U, // <7,5,1,0>: Cost 3 vsldoi12 RHS, <5,1,0,1> - 3395120018U, // <7,5,1,1>: Cost 3 vmrglw <6,5,7,1>, <4,0,5,1> - 3248934563U, // <7,5,1,2>: Cost 4 vsldoi12 RHS, <5,1,2,3> - 3248934574U, // <7,5,1,3>: Cost 4 vsldoi12 RHS, <5,1,3,5> - 3250925239U, // <7,5,1,4>: Cost 3 vsldoi12 RHS, <5,1,4,5> - 3248934587U, // <7,5,1,5>: Cost 4 vsldoi12 RHS, <5,1,5,0> - 3231608521U, // <7,5,1,6>: Cost 4 vsldoi12 <1,6,5,7>, <5,1,6,5> - 3231608530U, // <7,5,1,7>: Cost 4 vsldoi12 <1,6,5,7>, <5,1,7,5> - 3250925271U, // <7,5,1,u>: Cost 3 vsldoi12 RHS, <5,1,u,1> - 3248934624U, // <7,5,2,0>: Cost 4 vsldoi12 RHS, <5,2,0,1> - 3250925291U, // <7,5,2,1>: Cost 3 vsldoi12 RHS, <5,2,1,3> - 3248934643U, // <7,5,2,2>: Cost 4 vsldoi12 RHS, <5,2,2,2> - 3248934654U, // <7,5,2,3>: Cost 3 vsldoi12 RHS, <5,2,3,4> - 4183205681U, // <7,5,2,4>: Cost 4 vsldoi8 <3,6,7,5>, <2,4,6,5> - 3250925327U, // <7,5,2,5>: Cost 3 vsldoi12 RHS, <5,2,5,3> - 3248934680U, // <7,5,2,6>: Cost 3 vsldoi12 RHS, <5,2,6,3> - 3231608609U, // <7,5,2,7>: Cost 4 vsldoi12 <1,6,5,7>, <5,2,7,3> - 3248934698U, // <7,5,2,u>: Cost 3 vsldoi12 RHS, <5,2,u,3> - 3248934705U, // <7,5,3,0>: Cost 4 vsldoi12 RHS, <5,3,0,1> - 3393145746U, // <7,5,3,1>: Cost 3 vmrglw <6,2,7,3>, <4,0,5,1> - 3393146233U, // <7,5,3,2>: Cost 3 vmrglw <6,2,7,3>, <4,6,5,2> - 3248934734U, // <7,5,3,3>: Cost 4 vsldoi12 RHS, <5,3,3,3> - 4181879315U, // <7,5,3,4>: Cost 4 vsldoi8 <3,4,7,5>, <3,4,7,5> - 3393146074U, // <7,5,3,5>: Cost 3 vmrglw <6,2,7,3>, <4,4,5,5> - 3393145346U, // <7,5,3,6>: Cost 3 vmrglw <6,2,7,3>, <3,4,5,6> - 3248934771U, // <7,5,3,7>: Cost 4 vsldoi12 RHS, <5,3,7,4> - 3393145348U, // <7,5,3,u>: Cost 3 vmrglw <6,2,7,3>, <3,4,5,u> - 4055466086U, // <7,5,4,0>: Cost 3 vsldoi4 <4,7,5,4>, LHS - 3389836178U, // <7,5,4,1>: Cost 3 vmrglw <5,6,7,4>, <4,0,5,1> - 3248934806U, // <7,5,4,2>: Cost 4 vsldoi12 RHS, <5,4,2,3> - 3248934816U, // <7,5,4,3>: Cost 4 vsldoi12 RHS, <5,4,3,4> - 4055469516U, // <7,5,4,4>: Cost 3 vsldoi4 <4,7,5,4>, <4,7,5,4> - 3248934836U, // <7,5,4,5>: Cost 3 vsldoi12 RHS, <5,4,5,6> - 3389835778U, // <7,5,4,6>: Cost 3 vmrglw <5,6,7,4>, <3,4,5,6> - 4055471462U, // <7,5,4,7>: Cost 3 vsldoi4 <4,7,5,4>, <7,4,5,6> - 3248934863U, // <7,5,4,u>: Cost 3 vsldoi12 RHS, <5,4,u,6> - 3250925523U, // <7,5,5,0>: Cost 3 vsldoi12 RHS, <5,5,0,1> - 3250925532U, // <7,5,5,1>: Cost 3 vsldoi12 RHS, <5,5,1,1> - 3248934886U, // <7,5,5,2>: Cost 4 vsldoi12 RHS, <5,5,2,2> - 3248934896U, // <7,5,5,3>: Cost 4 vsldoi12 RHS, <5,5,3,3> - 3250925563U, // <7,5,5,4>: Cost 3 vsldoi12 RHS, <5,5,4,5> - 3248934916U, // <7,5,5,5>: Cost 2 vsldoi12 RHS, <5,5,5,5> - 3248934926U, // <7,5,5,6>: Cost 3 vsldoi12 RHS, <5,5,6,6> - 3231608856U, // <7,5,5,7>: Cost 4 vsldoi12 <1,6,5,7>, <5,5,7,7> - 3248934916U, // <7,5,5,u>: Cost 2 vsldoi12 RHS, <5,5,5,5> - 3248934948U, // <7,5,6,0>: Cost 3 vsldoi12 RHS, <5,6,0,1> - 3250925619U, // <7,5,6,1>: Cost 3 vsldoi12 RHS, <5,6,1,7> - 3248934967U, // <7,5,6,2>: Cost 4 vsldoi12 RHS, <5,6,2,2> - 3248934978U, // <7,5,6,3>: Cost 3 vsldoi12 RHS, <5,6,3,4> - 3248934988U, // <7,5,6,4>: Cost 3 vsldoi12 RHS, <5,6,4,5> - 3250925655U, // <7,5,6,5>: Cost 3 vsldoi12 RHS, <5,6,5,7> - 3248935008U, // <7,5,6,6>: Cost 3 vsldoi12 RHS, <5,6,6,7> - 3248935010U, // <7,5,6,7>: Cost 2 vsldoi12 RHS, <5,6,7,0> - 3249082475U, // <7,5,6,u>: Cost 2 vsldoi12 RHS, <5,6,u,0> - 4055490662U, // <7,5,7,0>: Cost 3 vsldoi4 <4,7,5,7>, LHS - 3395832722U, // <7,5,7,1>: Cost 3 vmrglw <6,6,7,7>, <4,0,5,1> - 4055492200U, // <7,5,7,2>: Cost 4 vsldoi4 <4,7,5,7>, <2,2,2,2> - 4055492758U, // <7,5,7,3>: Cost 4 vsldoi4 <4,7,5,7>, <3,0,1,2> - 4055494095U, // <7,5,7,4>: Cost 3 vsldoi4 <4,7,5,7>, <4,7,5,7> - 3395833050U, // <7,5,7,5>: Cost 3 vmrglw <6,6,7,7>, <4,4,5,5> - 3395832322U, // <7,5,7,6>: Cost 3 vmrglw <6,6,7,7>, <3,4,5,6> - 4055496300U, // <7,5,7,7>: Cost 3 vsldoi4 <4,7,5,7>, <7,7,7,7> - 4055496494U, // <7,5,7,u>: Cost 3 vsldoi4 <4,7,5,7>, LHS - 3248935110U, // <7,5,u,0>: Cost 3 vsldoi12 RHS, <5,u,0,1> - 3248935120U, // <7,5,u,1>: Cost 3 vsldoi12 RHS, <5,u,1,2> - 3393146233U, // <7,5,u,2>: Cost 3 vmrglw <6,2,7,3>, <4,6,5,2> - 3248935140U, // <7,5,u,3>: Cost 3 vsldoi12 RHS, <5,u,3,4> - 3248935149U, // <7,5,u,4>: Cost 3 vsldoi12 RHS, <5,u,4,4> - 3248934916U, // <7,5,u,5>: Cost 2 vsldoi12 RHS, <5,5,5,5> - 3248935166U, // <7,5,u,6>: Cost 3 vsldoi12 RHS, <5,u,6,3> - 3249082628U, // <7,5,u,7>: Cost 2 vsldoi12 RHS, <5,u,7,0> - 3250925837U, // <7,5,u,u>: Cost 2 vsldoi12 RHS, <5,u,u,0> - 3248935190U, // <7,6,0,0>: Cost 4 vsldoi12 RHS, <6,0,0,0> - 3248935201U, // <7,6,0,1>: Cost 3 vsldoi12 RHS, <6,0,1,2> - 3263123962U, // <7,6,0,2>: Cost 3 vmrghw <7,0,1,2>, <6,2,7,3> - 3248935218U, // <7,6,0,3>: Cost 4 vsldoi12 RHS, <6,0,3,1> - 3248935227U, // <7,6,0,4>: Cost 4 vsldoi12 RHS, <6,0,4,1> - 3389804476U, // <7,6,0,5>: Cost 3 vmrglw <5,6,7,0>, <5,4,6,5> - 3389805368U, // <7,6,0,6>: Cost 3 vmrglw <5,6,7,0>, <6,6,6,6> - 2316062006U, // <7,6,0,7>: Cost 2 vmrglw <5,6,7,0>, RHS - 2316062007U, // <7,6,0,u>: Cost 2 vmrglw <5,6,7,0>, RHS - 3248935272U, // <7,6,1,0>: Cost 4 vsldoi12 RHS, <6,1,0,1> - 3377866217U, // <7,6,1,1>: Cost 4 vmrglw <3,6,7,1>, <2,0,6,1> - 3248935292U, // <7,6,1,2>: Cost 4 vsldoi12 RHS, <6,1,2,3> - 3229692296U, // <7,6,1,3>: Cost 5 vsldoi12 <1,3,6,7>, <6,1,3,6> - 3248935312U, // <7,6,1,4>: Cost 4 vsldoi12 RHS, <6,1,4,5> - 3395122056U, // <7,6,1,5>: Cost 4 vmrglw <6,5,7,1>, <6,7,6,5> - 3389813560U, // <7,6,1,6>: Cost 4 vmrglw <5,6,7,1>, <6,6,6,6> - 3248935335U, // <7,6,1,7>: Cost 3 vsldoi12 RHS, <6,1,7,1> - 3249082800U, // <7,6,1,u>: Cost 3 vsldoi12 RHS, <6,1,u,1> - 4067467366U, // <7,6,2,0>: Cost 3 vsldoi4 <6,7,6,2>, LHS - 3248935364U, // <7,6,2,1>: Cost 4 vsldoi12 RHS, <6,2,1,3> - 3264606714U, // <7,6,2,2>: Cost 3 vmrghw <7,2,3,3>, <6,2,7,3> - 3237433813U, // <7,6,2,3>: Cost 4 vsldoi12 <2,6,3,7>, <6,2,3,2> - 4067470646U, // <7,6,2,4>: Cost 3 vsldoi4 <6,7,6,2>, RHS - 3248935400U, // <7,6,2,5>: Cost 4 vsldoi12 RHS, <6,2,5,3> - 4067472261U, // <7,6,2,6>: Cost 3 vsldoi4 <6,7,6,2>, <6,7,6,2> - 3248935418U, // <7,6,2,7>: Cost 2 vsldoi12 RHS, <6,2,7,3> - 3249082883U, // <7,6,2,u>: Cost 2 vsldoi12 RHS, <6,2,u,3> - 4049559654U, // <7,6,3,0>: Cost 4 vsldoi4 <3,7,6,3>, LHS - 4179896609U, // <7,6,3,1>: Cost 4 vsldoi8 <3,1,7,6>, <3,1,7,6> - 3393147781U, // <7,6,3,2>: Cost 3 vmrglw <6,2,7,3>, <6,7,6,2> - 3375229286U, // <7,6,3,3>: Cost 4 vmrglw <3,2,7,3>, <3,2,6,3> - 3248935474U, // <7,6,3,4>: Cost 3 vsldoi12 RHS, <6,3,4,5> - 3375228721U, // <7,6,3,5>: Cost 4 vmrglw <3,2,7,3>, <2,4,6,5> - 3393147704U, // <7,6,3,6>: Cost 3 vmrglw <6,2,7,3>, <6,6,6,6> - 2319404342U, // <7,6,3,7>: Cost 2 vmrglw <6,2,7,3>, RHS - 2319404343U, // <7,6,3,u>: Cost 2 vmrglw <6,2,7,3>, RHS - 3248935515U, // <7,6,4,0>: Cost 4 vsldoi12 RHS, <6,4,0,1> - 3389834729U, // <7,6,4,1>: Cost 4 vmrglw <5,6,7,4>, <2,0,6,1> - 3266105850U, // <7,6,4,2>: Cost 3 vmrghw <7,4,5,6>, <6,2,7,3> - 3248935545U, // <7,6,4,3>: Cost 4 vsldoi12 RHS, <6,4,3,4> - 3248935554U, // <7,6,4,4>: Cost 4 vsldoi12 RHS, <6,4,4,4> - 3248935565U, // <7,6,4,5>: Cost 3 vsldoi12 RHS, <6,4,5,6> - 3389838136U, // <7,6,4,6>: Cost 3 vmrglw <5,6,7,4>, <6,6,6,6> - 2316094774U, // <7,6,4,7>: Cost 2 vmrglw <5,6,7,4>, RHS - 2316094775U, // <7,6,4,u>: Cost 2 vmrglw <5,6,7,4>, RHS - 3248935596U, // <7,6,5,0>: Cost 4 vsldoi12 RHS, <6,5,0,1> - 3231314616U, // <7,6,5,1>: Cost 5 vsldoi12 <1,6,1,7>, <6,5,1,4> - 3248935619U, // <7,6,5,2>: Cost 4 vsldoi12 RHS, <6,5,2,6> - 3248935628U, // <7,6,5,3>: Cost 4 vsldoi12 RHS, <6,5,3,6> - 3248935636U, // <7,6,5,4>: Cost 4 vsldoi12 RHS, <6,5,4,5> - 3377899313U, // <7,6,5,5>: Cost 4 vmrglw <3,6,7,5>, <2,4,6,5> - 4195160168U, // <7,6,5,6>: Cost 3 vsldoi8 <5,6,7,6>, <5,6,7,6> - 3248935659U, // <7,6,5,7>: Cost 3 vsldoi12 RHS, <6,5,7,1> - 3249083124U, // <7,6,5,u>: Cost 3 vsldoi12 RHS, <6,5,u,1> - 4067500134U, // <7,6,6,0>: Cost 3 vsldoi4 <6,7,6,6>, LHS - 3248935686U, // <7,6,6,1>: Cost 4 vsldoi12 RHS, <6,6,1,1> - 4195160570U, // <7,6,6,2>: Cost 3 vsldoi8 <5,6,7,6>, <6,2,7,3> - 4049586942U, // <7,6,6,3>: Cost 4 vsldoi4 <3,7,6,6>, <3,7,6,6> - 4067503414U, // <7,6,6,4>: Cost 3 vsldoi4 <6,7,6,6>, RHS - 4200469232U, // <7,6,6,5>: Cost 3 vsldoi8 <6,5,7,6>, <6,5,7,6> - 3248935736U, // <7,6,6,6>: Cost 2 vsldoi12 RHS, <6,6,6,6> - 3248935746U, // <7,6,6,7>: Cost 2 vsldoi12 RHS, <6,6,7,7> - 3249083211U, // <7,6,6,u>: Cost 2 vsldoi12 RHS, <6,6,u,7> - 3248935758U, // <7,6,7,0>: Cost 2 vsldoi12 RHS, <6,7,0,1> - 3248935767U, // <7,6,7,1>: Cost 3 vsldoi12 RHS, <6,7,1,1> - 3248935777U, // <7,6,7,2>: Cost 3 vsldoi12 RHS, <6,7,2,2> - 3248935784U, // <7,6,7,3>: Cost 3 vsldoi12 RHS, <6,7,3,0> - 3248935798U, // <7,6,7,4>: Cost 2 vsldoi12 RHS, <6,7,4,5> - 3248935807U, // <7,6,7,5>: Cost 3 vsldoi12 RHS, <6,7,5,5> - 3248935813U, // <7,6,7,6>: Cost 3 vsldoi12 RHS, <6,7,6,2> - 2322091318U, // <7,6,7,7>: Cost 2 vmrglw <6,6,7,7>, RHS - 3248935830U, // <7,6,7,u>: Cost 2 vsldoi12 RHS, <6,7,u,1> - 3249083295U, // <7,6,u,0>: Cost 2 vsldoi12 RHS, <6,u,0,1> - 3248935849U, // <7,6,u,1>: Cost 3 vsldoi12 RHS, <6,u,1,2> - 3249083314U, // <7,6,u,2>: Cost 3 vsldoi12 RHS, <6,u,2,2> - 3249083321U, // <7,6,u,3>: Cost 3 vsldoi12 RHS, <6,u,3,0> - 3249083335U, // <7,6,u,4>: Cost 2 vsldoi12 RHS, <6,u,4,5> - 3248935889U, // <7,6,u,5>: Cost 3 vsldoi12 RHS, <6,u,5,6> - 3248935736U, // <7,6,u,6>: Cost 2 vsldoi12 RHS, <6,6,6,6> - 3248935904U, // <7,6,u,7>: Cost 2 vsldoi12 RHS, <6,u,7,3> - 3249083367U, // <7,6,u,u>: Cost 2 vsldoi12 RHS, <6,u,u,1> - 2316062818U, // <7,7,0,0>: Cost 2 vmrglw <5,6,7,0>, <5,6,7,0> - 3248935930U, // <7,7,0,1>: Cost 2 vsldoi12 RHS, <7,0,1,2> - 3237434370U, // <7,7,0,2>: Cost 4 vsldoi12 <2,6,3,7>, <7,0,2,1> - 3389805050U, // <7,7,0,3>: Cost 3 vmrglw <5,6,7,0>, <6,2,7,3> - 3248935956U, // <7,7,0,4>: Cost 3 vsldoi12 RHS, <7,0,4,1> - 4067528802U, // <7,7,0,5>: Cost 3 vsldoi4 <6,7,7,0>, <5,6,7,0> - 4067529612U, // <7,7,0,6>: Cost 3 vsldoi4 <6,7,7,0>, <6,7,7,0> - 3389805378U, // <7,7,0,7>: Cost 3 vmrglw <5,6,7,0>, <6,6,7,7> - 3248935993U, // <7,7,0,u>: Cost 2 vsldoi12 RHS, <7,0,u,2> - 3248936001U, // <7,7,1,0>: Cost 4 vsldoi12 RHS, <7,1,0,1> - 3248936010U, // <7,7,1,1>: Cost 3 vsldoi12 RHS, <7,1,1,1> - 3248936021U, // <7,7,1,2>: Cost 3 vsldoi12 RHS, <7,1,2,3> - 3389813242U, // <7,7,1,3>: Cost 4 vmrglw <5,6,7,1>, <6,2,7,3> - 3248936037U, // <7,7,1,4>: Cost 4 vsldoi12 RHS, <7,1,4,1> - 3248936045U, // <7,7,1,5>: Cost 4 vsldoi12 RHS, <7,1,5,0> - 3231315063U, // <7,7,1,6>: Cost 4 vsldoi12 <1,6,1,7>, <7,1,6,1> - 3403085420U, // <7,7,1,7>: Cost 3 vmrglw <7,u,7,1>, <7,7,7,7> - 3248936075U, // <7,7,1,u>: Cost 3 vsldoi12 RHS, <7,1,u,3> - 3272823956U, // <7,7,2,0>: Cost 3 vsldoi12 RHS, <7,2,0,3> - 3248936093U, // <7,7,2,1>: Cost 4 vsldoi12 RHS, <7,2,1,3> - 3248936101U, // <7,7,2,2>: Cost 3 vsldoi12 RHS, <7,2,2,2> - 3248936108U, // <7,7,2,3>: Cost 3 vsldoi12 RHS, <7,2,3,0> - 3272823992U, // <7,7,2,4>: Cost 3 vsldoi12 RHS, <7,2,4,3> - 3248936129U, // <7,7,2,5>: Cost 4 vsldoi12 RHS, <7,2,5,3> - 3237434570U, // <7,7,2,6>: Cost 3 vsldoi12 <2,6,3,7>, <7,2,6,3> - 3261617363U, // <7,7,2,7>: Cost 3 vsldoi12 <6,6,7,7>, <7,2,7,3> - 3238761692U, // <7,7,2,u>: Cost 3 vsldoi12 <2,u,3,7>, <7,2,u,3> - 3248936163U, // <7,7,3,0>: Cost 3 vsldoi12 RHS, <7,3,0,1> - 3248936172U, // <7,7,3,1>: Cost 4 vsldoi12 RHS, <7,3,1,1> - 3237434618U, // <7,7,3,2>: Cost 4 vsldoi12 <2,6,3,7>, <7,3,2,6> - 2319405562U, // <7,7,3,3>: Cost 2 vmrglw <6,2,7,3>, <6,2,7,3> - 3248936203U, // <7,7,3,4>: Cost 3 vsldoi12 RHS, <7,3,4,5> - 3248936212U, // <7,7,3,5>: Cost 4 vsldoi12 RHS, <7,3,5,5> - 4183222967U, // <7,7,3,6>: Cost 3 vsldoi8 <3,6,7,7>, <3,6,7,7> - 3393147714U, // <7,7,3,7>: Cost 3 vmrglw <6,2,7,3>, <6,6,7,7> - 2319405562U, // <7,7,3,u>: Cost 2 vmrglw <6,2,7,3>, <6,2,7,3> - 3248936248U, // <7,7,4,0>: Cost 3 vsldoi12 RHS, <7,4,0,5> - 3248936254U, // <7,7,4,1>: Cost 4 vsldoi12 RHS, <7,4,1,2> - 4049643450U, // <7,7,4,2>: Cost 4 vsldoi4 <3,7,7,4>, <2,6,3,7> - 3389837818U, // <7,7,4,3>: Cost 3 vmrglw <5,6,7,4>, <6,2,7,3> - 2316095590U, // <7,7,4,4>: Cost 2 vmrglw <5,6,7,4>, <5,6,7,4> - 3248936294U, // <7,7,4,5>: Cost 2 vsldoi12 RHS, <7,4,5,6> - 4067562384U, // <7,7,4,6>: Cost 3 vsldoi4 <6,7,7,4>, <6,7,7,4> - 3389838146U, // <7,7,4,7>: Cost 3 vmrglw <5,6,7,4>, <6,6,7,7> - 3248936321U, // <7,7,4,u>: Cost 2 vsldoi12 RHS, <7,4,u,6> - 3248936325U, // <7,7,5,0>: Cost 4 vsldoi12 RHS, <7,5,0,1> - 3250926989U, // <7,7,5,1>: Cost 4 vsldoi12 RHS, <7,5,1,0> - 3248936345U, // <7,7,5,2>: Cost 4 vsldoi12 RHS, <7,5,2,3> - 3389846010U, // <7,7,5,3>: Cost 4 vmrglw <5,6,7,5>, <6,2,7,3> - 3248936365U, // <7,7,5,4>: Cost 4 vsldoi12 RHS, <7,5,4,5> - 3248936374U, // <7,7,5,5>: Cost 3 vsldoi12 RHS, <7,5,5,5> - 3248936385U, // <7,7,5,6>: Cost 3 vsldoi12 RHS, <7,5,6,7> - 3403118188U, // <7,7,5,7>: Cost 3 vmrglw <7,u,7,5>, <7,7,7,7> - 3249083859U, // <7,7,5,u>: Cost 3 vsldoi12 RHS, <7,5,u,7> - 4067573862U, // <7,7,6,0>: Cost 3 vsldoi4 <6,7,7,6>, LHS - 3248936421U, // <7,7,6,1>: Cost 4 vsldoi12 RHS, <7,6,1,7> - 3248936430U, // <7,7,6,2>: Cost 3 vsldoi12 RHS, <7,6,2,7> - 3389854202U, // <7,7,6,3>: Cost 3 vmrglw <5,6,7,6>, <6,2,7,3> - 4067577142U, // <7,7,6,4>: Cost 3 vsldoi4 <6,7,7,6>, RHS - 3248936457U, // <7,7,6,5>: Cost 4 vsldoi12 RHS, <7,6,5,7> - 3127399234U, // <7,7,6,6>: Cost 2 vsldoi8 <6,6,7,7>, <6,6,7,7> - 3248936468U, // <7,7,6,7>: Cost 3 vsldoi12 RHS, <7,6,7,0> - 3128726500U, // <7,7,6,u>: Cost 2 vsldoi8 <6,u,7,7>, <6,u,7,7> - 2999812198U, // <7,7,7,0>: Cost 2 vsldoi4 <7,7,7,7>, LHS - 3402470447U, // <7,7,7,1>: Cost 3 vmrglw <7,7,7,7>, <7,0,7,1> - 4201141459U, // <7,7,7,2>: Cost 3 vsldoi8 <6,6,7,7>, <7,2,7,3> - 3395834362U, // <7,7,7,3>: Cost 3 vmrglw <6,6,7,7>, <6,2,7,3> - 2999815478U, // <7,7,7,4>: Cost 2 vsldoi4 <7,7,7,7>, RHS - 3402470775U, // <7,7,7,5>: Cost 3 vmrglw <7,7,7,7>, <7,4,7,5> - 4201141778U, // <7,7,7,6>: Cost 3 vsldoi8 <6,6,7,7>, <7,6,6,7> - 1772539190U, // <7,7,7,7>: Cost 1 vspltisw3 RHS - 1772539190U, // <7,7,7,u>: Cost 1 vspltisw3 RHS - 2316062818U, // <7,7,u,0>: Cost 2 vmrglw <5,6,7,0>, <5,6,7,0> - 3249084034U, // <7,7,u,1>: Cost 2 vsldoi12 RHS, <7,u,1,2> - 3249084044U, // <7,7,u,2>: Cost 3 vsldoi12 RHS, <7,u,2,3> - 2319405562U, // <7,7,u,3>: Cost 2 vmrglw <6,2,7,3>, <6,2,7,3> - 2316095590U, // <7,7,u,4>: Cost 2 vmrglw <5,6,7,4>, <5,6,7,4> - 3249084074U, // <7,7,u,5>: Cost 2 vsldoi12 RHS, <7,u,5,6> - 3139344628U, // <7,7,u,6>: Cost 2 vsldoi8 , - 1772539190U, // <7,7,u,7>: Cost 1 vspltisw3 RHS - 1772539190U, // <7,7,u,u>: Cost 1 vspltisw3 RHS - 3248930816U, // <7,u,0,0>: Cost 2 vsldoi12 RHS, <0,0,0,0> - 3248936659U, // <7,u,0,1>: Cost 2 vsldoi12 RHS, - 3389802709U, // <7,u,0,2>: Cost 3 vmrglw <5,6,7,0>, <3,0,u,2> - 2316058780U, // <7,u,0,3>: Cost 2 vmrglw <5,6,7,0>, LHS - 3248936685U, // <7,u,0,4>: Cost 3 vsldoi12 RHS, - 2189383834U, // <7,u,0,5>: Cost 2 vmrghw <7,0,1,2>, RHS - 3389803037U, // <7,u,0,6>: Cost 3 vmrglw <5,6,7,0>, <3,4,u,6> - 2316062024U, // <7,u,0,7>: Cost 2 vmrglw <5,6,7,0>, RHS - 3248936722U, // <7,u,0,u>: Cost 2 vsldoi12 RHS, - 2993864806U, // <7,u,1,0>: Cost 2 vsldoi4 <6,7,u,1>, LHS - 3248931636U, // <7,u,1,1>: Cost 2 vsldoi12 RHS, <1,1,1,1> - 1101453102U, // <7,u,1,2>: Cost 1 vsldoi12 RHS, LHS - 4049693451U, // <7,u,1,3>: Cost 3 vsldoi4 <3,7,u,1>, <3,7,u,1> - 2993868086U, // <7,u,1,4>: Cost 2 vsldoi4 <6,7,u,1>, RHS - 3248936774U, // <7,u,1,5>: Cost 3 vsldoi12 RHS, - 2993869718U, // <7,u,1,6>: Cost 2 vsldoi4 <6,7,u,1>, <6,7,u,1> - 3249084249U, // <7,u,1,7>: Cost 3 vsldoi12 RHS, - 1101453156U, // <7,u,1,u>: Cost 1 vsldoi12 RHS, LHS - 3248936811U, // <7,u,2,0>: Cost 3 vsldoi12 RHS, - 3248936822U, // <7,u,2,1>: Cost 3 vsldoi12 RHS, - 3248932456U, // <7,u,2,2>: Cost 2 vsldoi12 RHS, <2,2,2,2> - 3248936837U, // <7,u,2,3>: Cost 2 vsldoi12 RHS, - 3248936849U, // <7,u,2,4>: Cost 3 vsldoi12 RHS, - 3248936858U, // <7,u,2,5>: Cost 3 vsldoi12 RHS, - 3237435299U, // <7,u,2,6>: Cost 3 vsldoi12 <2,6,3,7>, - 3249084332U, // <7,u,2,7>: Cost 2 vsldoi12 RHS, - 3248936882U, // <7,u,2,u>: Cost 2 vsldoi12 RHS, - 3248936892U, // <7,u,3,0>: Cost 2 vsldoi12 RHS, - 3248936901U, // <7,u,3,1>: Cost 3 vsldoi12 RHS, - 3237435347U, // <7,u,3,2>: Cost 3 vsldoi12 <2,6,3,7>, - 2319401116U, // <7,u,3,3>: Cost 2 vmrglw <6,2,7,3>, LHS - 3248936932U, // <7,u,3,4>: Cost 2 vsldoi12 RHS, - 3248936941U, // <7,u,3,5>: Cost 3 vsldoi12 RHS, - 4183231160U, // <7,u,3,6>: Cost 3 vsldoi8 <3,6,7,u>, <3,6,7,u> - 2319404360U, // <7,u,3,7>: Cost 2 vmrglw <6,2,7,3>, RHS - 3248936964U, // <7,u,3,u>: Cost 2 vsldoi12 RHS, - 3248936973U, // <7,u,4,0>: Cost 3 vsldoi12 RHS, - 2192365358U, // <7,u,4,1>: Cost 2 vmrghw <7,4,5,6>, LHS - 3389835477U, // <7,u,4,2>: Cost 3 vmrglw <5,6,7,4>, <3,0,u,2> - 2316091548U, // <7,u,4,3>: Cost 2 vmrglw <5,6,7,4>, LHS - 3248934096U, // <7,u,4,4>: Cost 2 vsldoi12 RHS, <4,4,4,4> - 3248937023U, // <7,u,4,5>: Cost 2 vsldoi12 RHS, - 3389835805U, // <7,u,4,6>: Cost 3 vmrglw <5,6,7,4>, <3,4,u,6> - 2316094792U, // <7,u,4,7>: Cost 2 vmrglw <5,6,7,4>, RHS - 3248937050U, // <7,u,4,u>: Cost 2 vsldoi12 RHS, - 2993897574U, // <7,u,5,0>: Cost 2 vsldoi4 <6,7,u,5>, LHS - 3250927718U, // <7,u,5,1>: Cost 3 vsldoi12 RHS, - 4049725370U, // <7,u,5,2>: Cost 3 vsldoi4 <3,7,u,5>, <2,6,3,7> - 4049726223U, // <7,u,5,3>: Cost 3 vsldoi4 <3,7,u,5>, <3,7,u,5> - 2993900854U, // <7,u,5,4>: Cost 2 vsldoi4 <6,7,u,5>, RHS - 3248934916U, // <7,u,5,5>: Cost 2 vsldoi12 RHS, <5,5,5,5> - 1101453466U, // <7,u,5,6>: Cost 1 vsldoi12 RHS, RHS - 3249084573U, // <7,u,5,7>: Cost 3 vsldoi12 RHS, - 1101453484U, // <7,u,5,u>: Cost 1 vsldoi12 RHS, RHS - 3248937135U, // <7,u,6,0>: Cost 3 vsldoi12 RHS, - 3248937150U, // <7,u,6,1>: Cost 3 vsldoi12 RHS, - 3124752895U, // <7,u,6,2>: Cost 2 vsldoi8 <6,2,7,u>, <6,2,7,u> - 3248937168U, // <7,u,6,3>: Cost 2 vsldoi12 RHS, - 3248937175U, // <7,u,6,4>: Cost 3 vsldoi12 RHS, - 3248937186U, // <7,u,6,5>: Cost 3 vsldoi12 RHS, - 3127407427U, // <7,u,6,6>: Cost 2 vsldoi8 <6,6,7,u>, <6,6,7,u> - 3249084660U, // <7,u,6,7>: Cost 2 vsldoi12 RHS, - 3248937213U, // <7,u,6,u>: Cost 2 vsldoi12 RHS, - 3249084672U, // <7,u,7,0>: Cost 2 vsldoi12 RHS, - 2194511662U, // <7,u,7,1>: Cost 2 vmrghw <7,7,7,7>, LHS - 3237804311U, // <7,u,7,2>: Cost 3 vsldoi12 <2,6,u,7>, - 2322088092U, // <7,u,7,3>: Cost 2 vmrglw <6,6,7,7>, LHS - 3249084712U, // <7,u,7,4>: Cost 2 vsldoi12 RHS, - 2194512026U, // <7,u,7,5>: Cost 2 vmrghw <7,7,7,7>, RHS - 3249084727U, // <7,u,7,6>: Cost 3 vsldoi12 RHS, - 1772539190U, // <7,u,7,7>: Cost 1 vspltisw3 RHS - 1772539190U, // <7,u,7,u>: Cost 1 vspltisw3 RHS - 3248937297U, // <7,u,u,0>: Cost 2 vsldoi12 RHS, - 3248937307U, // <7,u,u,1>: Cost 2 vsldoi12 RHS, - 1101453669U, // <7,u,u,2>: Cost 1 vsldoi12 RHS, LHS - 3248937323U, // <7,u,u,3>: Cost 2 vsldoi12 RHS, - 3248937337U, // <7,u,u,4>: Cost 2 vsldoi12 RHS, - 3248937347U, // <7,u,u,5>: Cost 2 vsldoi12 RHS, - 1101453709U, // <7,u,u,6>: Cost 1 vsldoi12 RHS, RHS - 1772539190U, // <7,u,u,7>: Cost 1 vspltisw3 RHS - 1101453723U, // <7,u,u,u>: Cost 1 vsldoi12 RHS, LHS - 1343012966U, // : Cost 1 vspltisw0 LHS - 3222102026U, // : Cost 2 vsldoi12 LHS, <0,0,1,1> - 4043786298U, // : Cost 3 vsldoi4 <2,u,0,0>, <2,u,0,0> - 3363338093U, // : Cost 3 vmrglw <1,2,u,0>, - 2958101814U, // : Cost 2 vsldoi4 <0,u,0,0>, RHS - 4072984674U, // : Cost 3 vsldoi4 <7,7,0,0>, <5,6,7,0> - 4067677086U, // : Cost 3 vsldoi4 <6,u,0,0>, <6,u,0,0> - 3363338421U, // : Cost 3 vmrglw <1,2,u,0>, - 1343012966U, // : Cost 1 vspltisw0 LHS - 2970050662U, // : Cost 2 vsldoi4 <2,u,0,1>, LHS - 1122353254U, // : Cost 1 vmrghw LHS, LHS - 1074618475U, // : Cost 1 vsldoi12 LHS, LHS - 4043794582U, // : Cost 3 vsldoi4 <2,u,0,1>, <3,0,1,2> - 2970053942U, // : Cost 2 vsldoi4 <2,u,0,1>, RHS - 4061712582U, // : Cost 3 vsldoi4 <5,u,0,1>, <5,u,0,1> - 2993943455U, // : Cost 2 vsldoi4 <6,u,0,1>, <6,u,0,1> - 4067685370U, // : Cost 3 vsldoi4 <6,u,0,1>, <7,0,1,2> - 1074618524U, // : Cost 1 vsldoi12 LHS, LHS - 4173284858U, // : Cost 3 vsldoi8 <2,0,u,0>, <2,0,u,0> - 2196807782U, // : Cost 2 vmrghw , LHS - 4168640104U, // : Cost 3 vsldoi8 <1,2,u,0>, <2,2,2,2> - 4168640166U, // : Cost 3 vsldoi8 <1,2,u,0>, <2,3,0,1> - 3270549842U, // : Cost 3 vmrghw , <0,4,1,5> - 3373451732U, // : Cost 3 vmrglw <3,0,1,2>, <3,4,0,5> - 4168640442U, // : Cost 3 vsldoi8 <1,2,u,0>, <2,6,3,7> - 4177930289U, // : Cost 3 vsldoi8 <2,7,u,0>, <2,7,u,0> - 2196808349U, // : Cost 2 vmrghw , LHS - 2282979328U, // : Cost 2 vmrglw LHS, <0,0,0,0> - 2282981030U, // : Cost 2 vmrglw LHS, <2,3,0,1> - 4180584821U, // : Cost 3 vsldoi8 <3,2,u,0>, <3,2,u,0> - 4168640924U, // : Cost 3 vsldoi8 <1,2,u,0>, <3,3,3,3> - 3356722857U, // : Cost 3 vmrglw LHS, <2,3,0,4> - 4073672802U, // : Cost 3 vsldoi4 <7,u,0,3>, <5,6,7,0> - 4168272504U, // : Cost 3 vsldoi8 <1,2,3,0>, <3,6,0,7> - 4073674362U, // : Cost 3 vsldoi4 <7,u,0,3>, <7,u,0,3> - 2282981037U, // : Cost 2 vmrglw LHS, <2,3,0,u> - 3363364864U, // : Cost 3 vmrglw <1,2,u,4>, <0,0,0,0> - 3222102354U, // : Cost 2 vsldoi12 LHS, <0,4,1,5> - 4043819070U, // : Cost 3 vsldoi4 <2,u,0,4>, <2,u,0,4> - 3242213632U, // : Cost 3 vmrghw <3,4,5,6>, <0,3,1,4> - 2150252882U, // : Cost 2 vmrghw <0,4,1,5>, <0,4,1,5> - 3094900022U, // : Cost 2 vsldoi8 <1,2,u,0>, RHS - 4067709858U, // : Cost 3 vsldoi4 <6,u,0,4>, <6,u,0,4> - 4189654472U, // : Cost 3 vsldoi8 <4,7,5,0>, <4,7,5,0> - 3226747281U, // : Cost 2 vsldoi12 LHS, <0,4,u,5> - 2199076864U, // : Cost 2 vmrghw RHS, <0,0,0,0> - 1125335142U, // : Cost 1 vmrghw RHS, LHS - 3272818861U, // : Cost 3 vmrghw RHS, <0,2,1,2> - 4049799960U, // : Cost 3 vsldoi4 <3,u,0,5>, <3,u,0,5> - 2199077202U, // : Cost 2 vmrghw RHS, <0,4,1,5> - 4195184644U, // : Cost 3 vsldoi8 <5,6,u,0>, <5,5,5,5> - 3121442923U, // : Cost 2 vsldoi8 <5,6,u,0>, <5,6,u,0> - 4073690748U, // : Cost 3 vsldoi4 <7,u,0,5>, <7,u,0,5> - 1125335709U, // : Cost 1 vmrghw RHS, LHS - 3376652288U, // : Cost 3 vmrglw <3,4,u,6>, <0,0,0,0> - 2199519334U, // : Cost 2 vmrghw , LHS - 4195185146U, // : Cost 3 vsldoi8 <5,6,u,0>, <6,2,7,3> - 4199166545U, // : Cost 3 vsldoi8 <6,3,u,0>, <6,3,u,0> - 3273261394U, // : Cost 3 vmrghw , <0,4,1,5> - 3255583140U, // : Cost 3 vmrghw <5,6,7,0>, <0,5,1,6> - 4195185464U, // : Cost 3 vsldoi8 <5,6,u,0>, <6,6,6,6> - 4195185486U, // : Cost 3 vsldoi8 <5,6,u,0>, <6,7,0,1> - 2199519901U, // : Cost 2 vmrghw , LHS - 2309554176U, // : Cost 2 vmrglw RHS, <0,0,0,0> - 2309555878U, // : Cost 2 vmrglw RHS, <2,3,0,1> - 4204475609U, // : Cost 3 vsldoi8 <7,2,u,0>, <7,2,u,0> - 4049816346U, // : Cost 3 vsldoi4 <3,u,0,7>, <3,u,0,7> - 4049816886U, // : Cost 3 vsldoi4 <3,u,0,7>, RHS - 3383298516U, // : Cost 3 vmrglw RHS, <3,4,0,5> - 4207130141U, // : Cost 3 vsldoi8 <7,6,u,0>, <7,6,u,0> - 3383298680U, // : Cost 3 vmrglw RHS, <3,6,0,7> - 2309555885U, // : Cost 2 vmrglw RHS, <2,3,0,u> - 1343012966U, // : Cost 1 vspltisw0 LHS - 1126998118U, // : Cost 1 vmrghw LHS, LHS - 1074619037U, // : Cost 1 vsldoi12 LHS, LHS - 4168644540U, // : Cost 3 vsldoi8 <1,2,u,0>, - 2970111286U, // : Cost 2 vsldoi4 <2,u,0,u>, RHS - 3094902938U, // : Cost 2 vsldoi8 <1,2,u,0>, RHS - 2994000806U, // : Cost 2 vsldoi4 <6,u,0,u>, <6,u,0,u> - 3383306872U, // : Cost 3 vmrglw RHS, <3,6,0,7> - 1074619091U, // : Cost 1 vsldoi12 LHS, LHS - 3087605833U, // : Cost 2 vsldoi8 <0,0,u,1>, <0,0,u,1> - 3092914278U, // : Cost 2 vsldoi8 <0,u,u,1>, LHS - 3361347283U, // : Cost 3 vmrglw <0,u,u,0>, - 4049832732U, // : Cost 3 vsldoi4 <3,u,1,0>, <3,u,1,0> - 4031917366U, // : Cost 3 vsldoi4 <0,u,1,0>, RHS - 3363332434U, // : Cost 3 vmrglw <1,2,u,0>, <0,4,1,5> - 4073722774U, // : Cost 3 vsldoi4 <7,u,1,0>, <6,7,u,1> - 4073723520U, // : Cost 3 vsldoi4 <7,u,1,0>, <7,u,1,0> - 3092914897U, // : Cost 2 vsldoi8 <0,u,u,1>, <0,u,u,1> - 2958181010U, // : Cost 2 vsldoi4 <0,u,1,1>, <0,u,1,1> - 1477230694U, // : Cost 1 vspltisw1 LHS - 2196095894U, // : Cost 2 vmrghw LHS, <1,2,3,0> - 4031924374U, // : Cost 3 vsldoi4 <0,u,1,1>, <3,0,1,2> - 2958183734U, // : Cost 2 vsldoi4 <0,u,1,1>, RHS - 3226747740U, // : Cost 3 vsldoi12 LHS, <1,1,5,5> - 4067759016U, // : Cost 3 vsldoi4 <6,u,1,1>, <6,u,1,1> - 3361355966U, // : Cost 3 vmrglw <0,u,u,1>, - 1477230694U, // : Cost 1 vspltisw1 LHS - 2976104550U, // : Cost 2 vsldoi4 <3,u,1,2>, LHS - 3226747783U, // : Cost 3 vsldoi12 LHS, <1,2,1,3> - 2155004822U, // : Cost 2 vmrghw <1,2,3,0>, <1,2,3,0> + 3358212096U, // <5,0,0,0>: Cost 3 vsldoi12 <0,4,1,5>, <0,0,0,0> + 3358212106U, // <5,0,0,1>: Cost 3 vsldoi12 <0,4,1,5>, <0,0,1,1> + 4187956942U, // <5,0,0,2>: Cost 4 vsldoi4 <4,5,0,0>, <2,3,4,5> + 3510603490U, // <5,0,0,3>: Cost 4 vmrglw <3,4,5,0>, <5,2,0,3> + 3358212133U, // <5,0,0,4>: Cost 3 vsldoi12 <0,4,1,5>, <0,0,4,1> + 3376054322U, // <5,0,0,5>: Cost 4 vsldoi12 <3,4,0,5>, <0,0,5,5> + 3245482477U, // <5,0,0,6>: Cost 4 vsldoi8 <4,0,5,0>, <0,6,0,7> + 3510603818U, // <5,0,0,7>: Cost 4 vmrglw <3,4,5,0>, <5,6,0,7> + 3361382473U, // <5,0,0,u>: Cost 3 vsldoi12 <0,u,u,5>, <0,0,u,1> + 4170047590U, // <5,0,1,0>: Cost 3 vsldoi4 <1,5,0,1>, LHS + 4170048623U, // <5,0,1,1>: Cost 3 vsldoi4 <1,5,0,1>, <1,5,0,1> + 3358212198U, // <5,0,1,2>: Cost 2 vsldoi12 <0,4,1,5>, LHS + 3229557753U, // <5,0,1,3>: Cost 4 vsldoi8 <1,3,5,0>, <1,3,5,0> + 4170050870U, // <5,0,1,4>: Cost 3 vsldoi4 <1,5,0,1>, RHS + 4193939411U, // <5,0,1,5>: Cost 3 vsldoi4 <5,5,0,1>, <5,5,0,1> + 3246146803U, // <5,0,1,6>: Cost 4 vsldoi8 <4,1,5,0>, <1,6,5,7> + 3519236728U, // <5,0,1,7>: Cost 4 vmrglw <4,u,5,1>, <3,6,0,7> + 3358212252U, // <5,0,1,u>: Cost 2 vsldoi12 <0,4,1,5>, LHS + 3510616064U, // <5,0,2,0>: Cost 4 vmrglw <3,4,5,2>, <0,0,0,0> + 3386728550U, // <5,0,2,1>: Cost 3 vmrghw <5,2,1,3>, LHS + 3236193896U, // <5,0,2,2>: Cost 4 vsldoi8 <2,4,5,0>, <2,2,2,2> + 3242165966U, // <5,0,2,3>: Cost 3 vsldoi8 <3,4,5,0>, <2,3,4,5> + 3358212295U, // <5,0,2,4>: Cost 4 vsldoi12 <0,4,1,5>, <0,2,4,1> + 3376054482U, // <5,0,2,5>: Cost 4 vsldoi12 <3,4,0,5>, <0,2,5,3> + 3242166202U, // <5,0,2,6>: Cost 4 vsldoi8 <3,4,5,0>, <2,6,3,7> + 3274016746U, // <5,0,2,7>: Cost 4 vsldoi8 , <2,7,0,1> + 3386729117U, // <5,0,2,u>: Cost 3 vmrghw <5,2,1,3>, LHS + 3247474838U, // <5,0,3,0>: Cost 3 vsldoi8 <4,3,5,0>, <3,0,1,2> + 3358212348U, // <5,0,3,1>: Cost 4 vsldoi12 <0,4,1,5>, <0,3,1,0> + 3242166604U, // <5,0,3,2>: Cost 4 vsldoi8 <3,4,5,0>, <3,2,3,4> + 3242166684U, // <5,0,3,3>: Cost 4 vsldoi8 <3,4,5,0>, <3,3,3,3> + 3242166780U, // <5,0,3,4>: Cost 3 vsldoi8 <3,4,5,0>, <3,4,5,0> + 3513944532U, // <5,0,3,5>: Cost 4 vmrglw <4,0,5,3>, <3,4,0,5> + 3266054836U, // <5,0,3,6>: Cost 4 vsldoi8 <7,4,5,0>, <3,6,7,4> + 3497355896U, // <5,0,3,7>: Cost 5 vmrglw <1,2,5,3>, <3,6,0,7> + 3244821312U, // <5,0,3,u>: Cost 3 vsldoi8 <3,u,5,0>, <3,u,5,0> + 4170072166U, // <5,0,4,0>: Cost 3 vsldoi4 <1,5,0,4>, LHS + 3358212434U, // <5,0,4,1>: Cost 2 vsldoi12 <0,4,1,5>, <0,4,1,5> + 3358286171U, // <5,0,4,2>: Cost 4 vsldoi12 <0,4,2,5>, <0,4,2,5> + 3247475844U, // <5,0,4,3>: Cost 3 vsldoi8 <4,3,5,0>, <4,3,5,0> + 3358212461U, // <5,0,4,4>: Cost 3 vsldoi12 <0,4,1,5>, <0,4,4,5> + 3242167606U, // <5,0,4,5>: Cost 3 vsldoi8 <3,4,5,0>, RHS + 3242167678U, // <5,0,4,6>: Cost 4 vsldoi8 <3,4,5,0>, <4,6,5,7> + 3250130376U, // <5,0,4,7>: Cost 3 vsldoi8 <4,7,5,0>, <4,7,5,0> + 3358212434U, // <5,0,4,u>: Cost 2 vsldoi12 <0,4,1,5>, <0,4,1,5> + 3519266816U, // <5,0,5,0>: Cost 3 vmrglw <4,u,5,5>, <0,0,0,0> + 2315288678U, // <5,0,5,1>: Cost 2 vmrghw <5,5,5,5>, LHS + 3242168034U, // <5,0,5,2>: Cost 4 vsldoi8 <3,4,5,0>, <5,2,0,3> + 3376054704U, // <5,0,5,3>: Cost 4 vsldoi12 <3,4,0,5>, <0,5,3,0> + 3389030738U, // <5,0,5,4>: Cost 3 vmrghw <5,5,5,5>, <0,4,1,5> + 3389030882U, // <5,0,5,5>: Cost 3 vmrghw <5,5,5,5>, <0,5,u,5> + 3242168362U, // <5,0,5,6>: Cost 4 vsldoi8 <3,4,5,0>, <5,6,0,7> + 3519269496U, // <5,0,5,7>: Cost 4 vmrglw <4,u,5,5>, <3,6,0,7> + 2315289245U, // <5,0,5,u>: Cost 2 vmrghw <5,5,5,5>, LHS + 3510648832U, // <5,0,6,0>: Cost 3 vmrglw <3,4,5,6>, <0,0,0,0> + 2316058726U, // <5,0,6,1>: Cost 2 vmrghw <5,6,7,0>, LHS + 3250131450U, // <5,0,6,2>: Cost 4 vsldoi8 <4,7,5,0>, <6,2,7,3> + 3510649888U, // <5,0,6,3>: Cost 4 vmrglw <3,4,5,6>, <1,4,0,3> + 3389800786U, // <5,0,6,4>: Cost 3 vmrghw <5,6,7,0>, <0,4,1,5> + 3389800868U, // <5,0,6,5>: Cost 3 vmrghw <5,6,7,0>, <0,5,1,6> + 3510651430U, // <5,0,6,6>: Cost 4 vmrglw <3,4,5,6>, <3,5,0,6> + 3266057078U, // <5,0,6,7>: Cost 3 vsldoi8 <7,4,5,0>, <6,7,4,5> + 2316059293U, // <5,0,6,u>: Cost 2 vmrghw <5,6,7,0>, LHS + 3250131962U, // <5,0,7,0>: Cost 3 vsldoi8 <4,7,5,0>, <7,0,1,2> + 3500041327U, // <5,0,7,1>: Cost 4 vmrglw <1,6,5,7>, <1,5,0,1> + 3272029405U, // <5,0,7,2>: Cost 4 vsldoi8 , <7,2,u,4> + 3247477987U, // <5,0,7,3>: Cost 4 vsldoi8 <4,3,5,0>, <7,3,0,1> + 3266057568U, // <5,0,7,4>: Cost 3 vsldoi8 <7,4,5,0>, <7,4,5,0> + 3250132356U, // <5,0,7,5>: Cost 4 vsldoi8 <4,7,5,0>, <7,5,0,0> + 3266057752U, // <5,0,7,6>: Cost 4 vsldoi8 <7,4,5,0>, <7,6,7,4> + 3250132519U, // <5,0,7,7>: Cost 4 vsldoi8 <4,7,5,0>, <7,7,0,1> + 3268712100U, // <5,0,7,u>: Cost 3 vsldoi8 <7,u,5,0>, <7,u,5,0> + 4170104934U, // <5,0,u,0>: Cost 3 vsldoi4 <1,5,0,u>, LHS + 3360866966U, // <5,0,u,1>: Cost 2 vsldoi12 <0,u,1,5>, <0,u,1,5> + 3358212765U, // <5,0,u,2>: Cost 2 vsldoi12 <0,4,1,5>, LHS + 3242165966U, // <5,0,u,3>: Cost 3 vsldoi8 <3,4,5,0>, <2,3,4,5> + 3358212781U, // <5,0,u,4>: Cost 3 vsldoi12 <0,4,1,5>, <0,u,4,1> + 3242170522U, // <5,0,u,5>: Cost 3 vsldoi8 <3,4,5,0>, RHS + 3242170576U, // <5,0,u,6>: Cost 4 vsldoi8 <3,4,5,0>, + 3274021164U, // <5,0,u,7>: Cost 3 vsldoi8 , + 3358212819U, // <5,0,u,u>: Cost 2 vsldoi12 <0,4,1,5>, LHS + 3250798592U, // <5,1,0,0>: Cost 3 vsldoi8 <4,u,5,1>, <0,0,0,0> + 3250798694U, // <5,1,0,1>: Cost 2 vsldoi8 <4,u,5,1>, LHS + 3518567418U, // <5,1,0,2>: Cost 3 vmrglw <4,7,5,0>, <7,0,1,2> + 3250798844U, // <5,1,0,3>: Cost 4 vsldoi8 <4,u,5,1>, <0,3,1,0> + 3250798930U, // <5,1,0,4>: Cost 3 vsldoi8 <4,u,5,1>, <0,4,1,5> + 3514581330U, // <5,1,0,5>: Cost 3 vmrglw <4,1,5,0>, <0,4,1,5> + 3250799094U, // <5,1,0,6>: Cost 4 vsldoi8 <4,u,5,1>, <0,6,1,7> + 4205950349U, // <5,1,0,7>: Cost 4 vsldoi4 <7,5,1,0>, <7,5,1,0> + 3250799261U, // <5,1,0,u>: Cost 2 vsldoi8 <4,u,5,1>, LHS + 4194009190U, // <5,1,1,0>: Cost 3 vsldoi4 <5,5,1,1>, LHS + 3358212916U, // <5,1,1,1>: Cost 3 vsldoi12 <0,4,1,5>, <1,1,1,1> + 3519236246U, // <5,1,1,2>: Cost 3 vmrglw <4,u,5,1>, <3,0,1,2> + 3519237867U, // <5,1,1,3>: Cost 3 vmrglw <4,u,5,1>, <5,2,1,3> + 3362415443U, // <5,1,1,4>: Cost 3 vsldoi12 <1,1,4,5>, <1,1,4,5> + 3358212956U, // <5,1,1,5>: Cost 3 vsldoi12 <0,4,1,5>, <1,1,5,5> + 3519234225U, // <5,1,1,6>: Cost 4 vmrglw <4,u,5,1>, <0,2,1,6> + 3519238195U, // <5,1,1,7>: Cost 3 vmrglw <4,u,5,1>, <5,6,1,7> + 3362710391U, // <5,1,1,u>: Cost 3 vsldoi12 <1,1,u,5>, <1,1,u,5> + 4170129510U, // <5,1,2,0>: Cost 4 vsldoi4 <1,5,1,2>, LHS + 3360867207U, // <5,1,2,1>: Cost 4 vsldoi12 <0,u,1,5>, <1,2,1,3> + 3250800232U, // <5,1,2,2>: Cost 3 vsldoi8 <4,u,5,1>, <2,2,2,2> + 3358213014U, // <5,1,2,3>: Cost 3 vsldoi12 <0,4,1,5>, <1,2,3,0> + 3363079076U, // <5,1,2,4>: Cost 3 vsldoi12 <1,2,4,5>, <1,2,4,5> + 3358213035U, // <5,1,2,5>: Cost 3 vsldoi12 <0,4,1,5>, <1,2,5,3> + 3250800570U, // <5,1,2,6>: Cost 3 vsldoi8 <4,u,5,1>, <2,6,3,7> + 3402597306U, // <5,1,2,7>: Cost 4 vsldoi12 <7,u,0,5>, <1,2,7,0> + 3358213059U, // <5,1,2,u>: Cost 3 vsldoi12 <0,4,1,5>, <1,2,u,0> + 3250800790U, // <5,1,3,0>: Cost 3 vsldoi8 <4,u,5,1>, <3,0,1,2> + 3497353226U, // <5,1,3,1>: Cost 4 vmrglw <1,2,5,3>, <0,0,1,1> + 3497355414U, // <5,1,3,2>: Cost 4 vmrglw <1,2,5,3>, <3,0,1,2> + 3250801052U, // <5,1,3,3>: Cost 3 vsldoi8 <4,u,5,1>, <3,3,3,3> + 3250801154U, // <5,1,3,4>: Cost 3 vsldoi8 <4,u,5,1>, <3,4,5,6> + 3497353554U, // <5,1,3,5>: Cost 3 vmrglw <1,2,5,3>, <0,4,1,5> + 3250801272U, // <5,1,3,6>: Cost 4 vsldoi8 <4,u,5,1>, <3,6,0,7> + 3250801347U, // <5,1,3,7>: Cost 4 vsldoi8 <4,u,5,1>, <3,7,0,1> + 3250801438U, // <5,1,3,u>: Cost 3 vsldoi8 <4,u,5,1>, <3,u,1,2> + 3245493138U, // <5,1,4,0>: Cost 2 vsldoi8 <4,0,5,1>, <4,0,5,1> + 3364185131U, // <5,1,4,1>: Cost 3 vsldoi12 <1,4,1,5>, <1,4,1,5> + 3364258868U, // <5,1,4,2>: Cost 3 vsldoi12 <1,4,2,5>, <1,4,2,5> + 3250801796U, // <5,1,4,3>: Cost 4 vsldoi8 <4,u,5,1>, <4,3,5,0> + 3250801872U, // <5,1,4,4>: Cost 3 vsldoi8 <4,u,5,1>, <4,4,4,4> + 3250801974U, // <5,1,4,5>: Cost 2 vsldoi8 <4,u,5,1>, RHS + 3249474936U, // <5,1,4,6>: Cost 4 vsldoi8 <4,6,5,1>, <4,6,5,1> + 3250138569U, // <5,1,4,7>: Cost 4 vsldoi8 <4,7,5,1>, <4,7,5,1> + 3250802202U, // <5,1,4,u>: Cost 2 vsldoi8 <4,u,5,1>, <4,u,5,1> + 3358213231U, // <5,1,5,0>: Cost 3 vsldoi12 <0,4,1,5>, <1,5,0,1> + 3250802319U, // <5,1,5,1>: Cost 3 vsldoi8 <4,u,5,1>, <5,1,0,1> + 3250802411U, // <5,1,5,2>: Cost 3 vsldoi8 <4,u,5,1>, <5,2,1,3> + 3358213257U, // <5,1,5,3>: Cost 4 vsldoi12 <0,4,1,5>, <1,5,3,0> + 3358213271U, // <5,1,5,4>: Cost 3 vsldoi12 <0,4,1,5>, <1,5,4,5> + 3496706386U, // <5,1,5,5>: Cost 3 vmrglw <1,1,5,5>, <0,4,1,5> + 3250802739U, // <5,1,5,6>: Cost 3 vsldoi8 <4,u,5,1>, <5,6,1,7> + 3250802813U, // <5,1,5,7>: Cost 4 vsldoi8 <4,u,5,1>, <5,7,1,0> + 3358213303U, // <5,1,5,u>: Cost 3 vsldoi12 <0,4,1,5>, <1,5,u,1> + 4211966054U, // <5,1,6,0>: Cost 3 vsldoi4 , LHS + 3498705554U, // <5,1,6,1>: Cost 3 vmrglw <1,4,5,6>, <0,u,1,1> + 3510651030U, // <5,1,6,2>: Cost 3 vmrglw <3,4,5,6>, <3,0,1,2> + 3498705799U, // <5,1,6,3>: Cost 4 vmrglw <1,4,5,6>, <1,2,1,3> + 3510649088U, // <5,1,6,4>: Cost 3 vmrglw <3,4,5,6>, <0,3,1,4> + 3358213363U, // <5,1,6,5>: Cost 3 vsldoi12 <0,4,1,5>, <1,6,5,7> + 3250803512U, // <5,1,6,6>: Cost 3 vsldoi8 <4,u,5,1>, <6,6,6,6> + 3250803534U, // <5,1,6,7>: Cost 3 vsldoi8 <4,u,5,1>, <6,7,0,1> + 3510648849U, // <5,1,6,u>: Cost 3 vmrglw <3,4,5,6>, <0,0,1,u> + 3250803706U, // <5,1,7,0>: Cost 3 vsldoi8 <4,u,5,1>, <7,0,1,2> + 3500040202U, // <5,1,7,1>: Cost 4 vmrglw <1,6,5,7>, <0,0,1,1> + 3500042390U, // <5,1,7,2>: Cost 4 vmrglw <1,6,5,7>, <3,0,1,2> + 3250803939U, // <5,1,7,3>: Cost 4 vsldoi8 <4,u,5,1>, <7,3,0,1> + 3250804070U, // <5,1,7,4>: Cost 3 vsldoi8 <4,u,5,1>, <7,4,5,6> + 3500040530U, // <5,1,7,5>: Cost 3 vmrglw <1,6,5,7>, <0,4,1,5> + 3500041341U, // <5,1,7,6>: Cost 4 vmrglw <1,6,5,7>, <1,5,1,6> + 3250804332U, // <5,1,7,7>: Cost 3 vsldoi8 <4,u,5,1>, <7,7,7,7> + 3250804354U, // <5,1,7,u>: Cost 3 vsldoi8 <4,u,5,1>, <7,u,1,2> + 3269383926U, // <5,1,u,0>: Cost 2 vsldoi8 , + 3250804526U, // <5,1,u,1>: Cost 2 vsldoi8 <4,u,5,1>, LHS + 3366913400U, // <5,1,u,2>: Cost 3 vsldoi12 <1,u,2,5>, <1,u,2,5> + 3358213500U, // <5,1,u,3>: Cost 3 vsldoi12 <0,4,1,5>, <1,u,3,0> + 3367060874U, // <5,1,u,4>: Cost 3 vsldoi12 <1,u,4,5>, <1,u,4,5> + 3250804890U, // <5,1,u,5>: Cost 2 vsldoi8 <4,u,5,1>, RHS + 3250804944U, // <5,1,u,6>: Cost 3 vsldoi8 <4,u,5,1>, + 3250804992U, // <5,1,u,7>: Cost 3 vsldoi8 <4,u,5,1>, + 3250805093U, // <5,1,u,u>: Cost 2 vsldoi8 <4,u,5,1>, LHS + 3242180608U, // <5,2,0,0>: Cost 4 vsldoi8 <3,4,5,2>, <0,0,0,0> + 3242180710U, // <5,2,0,1>: Cost 3 vsldoi8 <3,4,5,2>, LHS + 3369051589U, // <5,2,0,2>: Cost 4 vsldoi12 <2,2,4,5>, <2,0,2,1> + 3510599782U, // <5,2,0,3>: Cost 3 vmrglw <3,4,5,0>, LHS + 3228246354U, // <5,2,0,4>: Cost 4 vsldoi8 <1,1,5,2>, <0,4,1,5> + 3515245620U, // <5,2,0,5>: Cost 4 vmrglw <4,2,5,0>, <1,4,2,5> + 3373032937U, // <5,2,0,6>: Cost 4 vsldoi12 <2,u,4,5>, <2,0,6,1> + 3542450282U, // <5,2,0,7>: Cost 4 vmrglw , <0,1,2,7> + 3510599787U, // <5,2,0,u>: Cost 3 vmrglw <3,4,5,0>, LHS + 4170195046U, // <5,2,1,0>: Cost 4 vsldoi4 <1,5,2,1>, LHS + 3228246873U, // <5,2,1,1>: Cost 4 vsldoi8 <1,1,5,2>, <1,1,5,2> + 3519235688U, // <5,2,1,2>: Cost 3 vmrglw <4,u,5,1>, <2,2,2,2> + 2445492326U, // <5,2,1,3>: Cost 2 vmrglw <4,u,5,1>, LHS + 4170198326U, // <5,2,1,4>: Cost 4 vsldoi4 <1,5,2,1>, RHS + 3515253812U, // <5,2,1,5>: Cost 4 vmrglw <4,2,5,1>, <1,4,2,5> + 3519235773U, // <5,2,1,6>: Cost 4 vmrglw <4,u,5,1>, <2,3,2,6> + 3519235288U, // <5,2,1,7>: Cost 4 vmrglw <4,u,5,1>, <1,6,2,7> + 2445492331U, // <5,2,1,u>: Cost 2 vmrglw <4,u,5,1>, LHS + 4170203238U, // <5,2,2,0>: Cost 4 vsldoi4 <1,5,2,2>, LHS + 4170204290U, // <5,2,2,1>: Cost 4 vsldoi4 <1,5,2,2>, <1,5,2,2> + 3358213736U, // <5,2,2,2>: Cost 3 vsldoi12 <0,4,1,5>, <2,2,2,2> + 3358213746U, // <5,2,2,3>: Cost 3 vsldoi12 <0,4,1,5>, <2,2,3,3> + 3369051773U, // <5,2,2,4>: Cost 3 vsldoi12 <2,2,4,5>, <2,2,4,5> + 3364259460U, // <5,2,2,5>: Cost 4 vsldoi12 <1,4,2,5>, <2,2,5,3> + 3373033104U, // <5,2,2,6>: Cost 4 vsldoi12 <2,u,4,5>, <2,2,6,6> + 3510620220U, // <5,2,2,7>: Cost 4 vmrglw <3,4,5,2>, <5,6,2,7> + 3358213791U, // <5,2,2,u>: Cost 3 vsldoi12 <0,4,1,5>, <2,2,u,3> + 3358213798U, // <5,2,3,0>: Cost 3 vsldoi12 <0,4,1,5>, <2,3,0,1> + 3358213807U, // <5,2,3,1>: Cost 4 vsldoi12 <0,4,1,5>, <2,3,1,1> + 4188128974U, // <5,2,3,2>: Cost 3 vsldoi4 <4,5,2,3>, <2,3,4,5> + 3497353318U, // <5,2,3,3>: Cost 3 vmrglw <1,2,5,3>, LHS + 3369715406U, // <5,2,3,4>: Cost 2 vsldoi12 <2,3,4,5>, <2,3,4,5> + 3389032151U, // <5,2,3,5>: Cost 3 vsldoi12 <5,5,5,5>, <2,3,5,5> + 3385050849U, // <5,2,3,6>: Cost 4 vsldoi12 <4,u,5,5>, <2,3,6,6> + 3266071275U, // <5,2,3,7>: Cost 4 vsldoi8 <7,4,5,2>, <3,7,4,5> + 3370010354U, // <5,2,3,u>: Cost 2 vsldoi12 <2,3,u,5>, <2,3,u,5> + 3370084091U, // <5,2,4,0>: Cost 4 vsldoi12 <2,4,0,5>, <2,4,0,5> + 3246164964U, // <5,2,4,1>: Cost 3 vsldoi8 <4,1,5,2>, <4,1,5,2> + 3370231565U, // <5,2,4,2>: Cost 3 vsldoi12 <2,4,2,5>, <2,4,2,5> + 3369715478U, // <5,2,4,3>: Cost 3 vsldoi12 <2,3,4,5>, <2,4,3,5> + 3370379039U, // <5,2,4,4>: Cost 4 vsldoi12 <2,4,4,5>, <2,4,4,5> + 3242183990U, // <5,2,4,5>: Cost 3 vsldoi8 <3,4,5,2>, RHS + 3249483129U, // <5,2,4,6>: Cost 3 vsldoi8 <4,6,5,2>, <4,6,5,2> + 3250146762U, // <5,2,4,7>: Cost 4 vsldoi8 <4,7,5,2>, <4,7,5,2> + 3369715523U, // <5,2,4,u>: Cost 3 vsldoi12 <2,3,4,5>, <2,4,u,5> + 3364259656U, // <5,2,5,0>: Cost 4 vsldoi12 <1,4,2,5>, <2,5,0,1> + 3364259666U, // <5,2,5,1>: Cost 4 vsldoi12 <1,4,2,5>, <2,5,1,2> + 3519268456U, // <5,2,5,2>: Cost 3 vmrglw <4,u,5,5>, <2,2,2,2> + 2445525094U, // <5,2,5,3>: Cost 2 vmrglw <4,u,5,5>, LHS + 3364259696U, // <5,2,5,4>: Cost 4 vsldoi12 <1,4,2,5>, <2,5,4,5> + 3503342644U, // <5,2,5,5>: Cost 4 vmrglw <2,2,5,5>, <1,4,2,5> + 3389032378U, // <5,2,5,6>: Cost 3 vmrghw <5,5,5,5>, <2,6,3,7> + 3249483913U, // <5,2,5,7>: Cost 4 vsldoi8 <4,6,5,2>, <5,7,2,3> + 2445525099U, // <5,2,5,u>: Cost 2 vmrglw <4,u,5,5>, LHS + 4170236006U, // <5,2,6,0>: Cost 4 vsldoi4 <1,5,2,6>, LHS + 4170237062U, // <5,2,6,1>: Cost 4 vsldoi4 <1,5,2,6>, <1,5,2,6> + 3504678504U, // <5,2,6,2>: Cost 3 vmrglw <2,4,5,6>, <2,2,2,2> + 2436907110U, // <5,2,6,3>: Cost 2 vmrglw <3,4,5,6>, LHS + 4170239286U, // <5,2,6,4>: Cost 4 vsldoi4 <1,5,2,6>, RHS + 3364259788U, // <5,2,6,5>: Cost 4 vsldoi12 <1,4,2,5>, <2,6,5,7> + 3389802426U, // <5,2,6,6>: Cost 3 vmrghw <5,6,7,0>, <2,6,3,7> + 3504678833U, // <5,2,6,7>: Cost 4 vmrglw <2,4,5,6>, <2,6,2,7> + 2436907115U, // <5,2,6,u>: Cost 2 vmrglw <3,4,5,6>, LHS + 3249484794U, // <5,2,7,0>: Cost 4 vsldoi8 <4,6,5,2>, <7,0,1,2> + 3246167125U, // <5,2,7,1>: Cost 4 vsldoi8 <4,1,5,2>, <7,1,2,3> + 3500041832U, // <5,2,7,2>: Cost 4 vmrglw <1,6,5,7>, <2,2,2,2> + 3500040294U, // <5,2,7,3>: Cost 3 vmrglw <1,6,5,7>, LHS + 3372369938U, // <5,2,7,4>: Cost 4 vsldoi12 <2,7,4,5>, <2,7,4,5> + 3506013236U, // <5,2,7,5>: Cost 4 vmrglw <2,6,5,7>, <1,4,2,5> + 3249485294U, // <5,2,7,6>: Cost 4 vsldoi8 <4,6,5,2>, <7,6,2,7> + 3249485420U, // <5,2,7,7>: Cost 4 vsldoi8 <4,6,5,2>, <7,7,7,7> + 3500040299U, // <5,2,7,u>: Cost 3 vmrglw <1,6,5,7>, LHS + 3358214203U, // <5,2,u,0>: Cost 3 vsldoi12 <0,4,1,5>, <2,u,0,1> + 3242186542U, // <5,2,u,1>: Cost 3 vsldoi8 <3,4,5,2>, LHS + 3504694888U, // <5,2,u,2>: Cost 3 vmrglw <2,4,5,u>, <2,2,2,2> + 2436923494U, // <5,2,u,3>: Cost 2 vmrglw <3,4,5,u>, LHS + 3373033571U, // <5,2,u,4>: Cost 2 vsldoi12 <2,u,4,5>, <2,u,4,5> + 3242186906U, // <5,2,u,5>: Cost 3 vsldoi8 <3,4,5,2>, RHS + 3373181045U, // <5,2,u,6>: Cost 3 vsldoi12 <2,u,6,5>, <2,u,6,5> + 3504695217U, // <5,2,u,7>: Cost 4 vmrglw <2,4,5,u>, <2,6,2,7> + 3373328519U, // <5,2,u,u>: Cost 2 vsldoi12 <2,u,u,5>, <2,u,u,5> + 3358214283U, // <5,3,0,0>: Cost 4 vsldoi12 <0,4,1,5>, <3,0,0,0> + 3358214294U, // <5,3,0,1>: Cost 3 vsldoi12 <0,4,1,5>, <3,0,1,2> + 4176234338U, // <5,3,0,2>: Cost 4 vsldoi4 <2,5,3,0>, <2,5,3,0> + 4170262678U, // <5,3,0,3>: Cost 4 vsldoi4 <1,5,3,0>, <3,0,1,2> + 3358214320U, // <5,3,0,4>: Cost 3 vsldoi12 <0,4,1,5>, <3,0,4,1> + 3510601494U, // <5,3,0,5>: Cost 4 vmrglw <3,4,5,0>, <2,4,3,5> + 3232899601U, // <5,3,0,6>: Cost 5 vsldoi8 <1,u,5,3>, <0,6,4,7> + 3510601658U, // <5,3,0,7>: Cost 4 vmrglw <3,4,5,0>, <2,6,3,7> + 3358214357U, // <5,3,0,u>: Cost 3 vsldoi12 <0,4,1,5>, <3,0,u,2> + 3519234966U, // <5,3,1,0>: Cost 3 vmrglw <4,u,5,1>, <1,2,3,0> + 3513927523U, // <5,3,1,1>: Cost 3 vmrglw <4,0,5,1>, <2,5,3,1> + 3228918699U, // <5,3,1,2>: Cost 3 vsldoi8 <1,2,5,3>, <1,2,5,3> + 3519235698U, // <5,3,1,3>: Cost 3 vmrglw <4,u,5,1>, <2,2,3,3> + 3519234970U, // <5,3,1,4>: Cost 3 vmrglw <4,u,5,1>, <1,2,3,4> + 3228918895U, // <5,3,1,5>: Cost 4 vsldoi8 <1,2,5,3>, <1,5,0,1> + 3228919027U, // <5,3,1,6>: Cost 4 vsldoi8 <1,2,5,3>, <1,6,5,7> + 3519236026U, // <5,3,1,7>: Cost 3 vmrglw <4,u,5,1>, <2,6,3,7> + 3232900497U, // <5,3,1,u>: Cost 3 vsldoi8 <1,u,5,3>, <1,u,5,3> + 3519248261U, // <5,3,2,0>: Cost 3 vmrglw <4,u,5,2>, + 3228919331U, // <5,3,2,1>: Cost 4 vsldoi8 <1,2,5,3>, <2,1,3,5> + 3358214465U, // <5,3,2,2>: Cost 4 vsldoi12 <0,4,1,5>, <3,2,2,2> + 3369716044U, // <5,3,2,3>: Cost 3 vsldoi12 <2,3,4,5>, <3,2,3,4> + 3387099650U, // <5,3,2,4>: Cost 3 vmrghw <5,2,6,3>, <3,4,5,6> + 3228919651U, // <5,3,2,5>: Cost 4 vsldoi8 <1,2,5,3>, <2,5,3,1> + 3358214502U, // <5,3,2,6>: Cost 4 vsldoi12 <0,4,1,5>, <3,2,6,3> + 3373033839U, // <5,3,2,7>: Cost 4 vsldoi12 <2,u,4,5>, <3,2,7,3> + 3373033849U, // <5,3,2,u>: Cost 3 vsldoi12 <2,u,4,5>, <3,2,u,4> + 3358214527U, // <5,3,3,0>: Cost 4 vsldoi12 <0,4,1,5>, <3,3,0,1> + 3228920051U, // <5,3,3,1>: Cost 4 vsldoi8 <1,2,5,3>, <3,1,2,5> + 3369716114U, // <5,3,3,2>: Cost 4 vsldoi12 <2,3,4,5>, <3,3,2,2> + 3358214556U, // <5,3,3,3>: Cost 3 vsldoi12 <0,4,1,5>, <3,3,3,3> + 3375688103U, // <5,3,3,4>: Cost 3 vsldoi12 <3,3,4,5>, <3,3,4,5> + 3497354787U, // <5,3,3,5>: Cost 4 vmrglw <1,2,5,3>, <2,1,3,5> + 3509299048U, // <5,3,3,6>: Cost 4 vmrglw <3,2,5,3>, <2,5,3,6> + 3497355194U, // <5,3,3,7>: Cost 4 vmrglw <1,2,5,3>, <2,6,3,7> + 3375983051U, // <5,3,3,u>: Cost 3 vsldoi12 <3,3,u,5>, <3,3,u,5> + 3376056788U, // <5,3,4,0>: Cost 3 vsldoi12 <3,4,0,5>, <3,4,0,5> + 3228920802U, // <5,3,4,1>: Cost 4 vsldoi8 <1,2,5,3>, <4,1,5,0> + 3246836790U, // <5,3,4,2>: Cost 3 vsldoi8 <4,2,5,3>, <4,2,5,3> + 3376277999U, // <5,3,4,3>: Cost 3 vsldoi12 <3,4,3,5>, <3,4,3,5> + 3376351736U, // <5,3,4,4>: Cost 3 vsldoi12 <3,4,4,5>, <3,4,4,5> + 3358214658U, // <5,3,4,5>: Cost 3 vsldoi12 <0,4,1,5>, <3,4,5,6> + 3369716234U, // <5,3,4,6>: Cost 4 vsldoi12 <2,3,4,5>, <3,4,6,5> + 3510634426U, // <5,3,4,7>: Cost 4 vmrglw <3,4,5,4>, <2,6,3,7> + 3358214685U, // <5,3,4,u>: Cost 3 vsldoi12 <0,4,1,5>, <3,4,u,6> + 3519267734U, // <5,3,5,0>: Cost 3 vmrglw <4,u,5,5>, <1,2,3,0> + 3228921509U, // <5,3,5,1>: Cost 4 vsldoi8 <1,2,5,3>, <5,1,2,5> + 3252809487U, // <5,3,5,2>: Cost 3 vsldoi8 <5,2,5,3>, <5,2,5,3> + 3519268466U, // <5,3,5,3>: Cost 3 vmrglw <4,u,5,5>, <2,2,3,3> + 3519267738U, // <5,3,5,4>: Cost 3 vmrglw <4,u,5,5>, <1,2,3,4> + 3389033042U, // <5,3,5,5>: Cost 3 vmrghw <5,5,5,5>, <3,5,5,5> + 3228921925U, // <5,3,5,6>: Cost 4 vsldoi8 <1,2,5,3>, <5,6,3,7> + 3519268794U, // <5,3,5,7>: Cost 3 vmrglw <4,u,5,5>, <2,6,3,7> + 3519267742U, // <5,3,5,u>: Cost 3 vmrglw <4,u,5,5>, <1,2,3,u> + 4176281702U, // <5,3,6,0>: Cost 3 vsldoi4 <2,5,3,6>, LHS + 4176282420U, // <5,3,6,1>: Cost 4 vsldoi4 <2,5,3,6>, <1,1,1,1> + 4176283496U, // <5,3,6,2>: Cost 3 vsldoi4 <2,5,3,6>, <2,5,3,6> + 4176284162U, // <5,3,6,3>: Cost 3 vsldoi4 <2,5,3,6>, <3,4,5,6> + 4176284982U, // <5,3,6,4>: Cost 3 vsldoi4 <2,5,3,6>, RHS + 3389803101U, // <5,3,6,5>: Cost 3 vmrghw <5,6,7,0>, <3,5,6,7> + 3510650728U, // <5,3,6,6>: Cost 3 vmrglw <3,4,5,6>, <2,5,3,6> + 3510650810U, // <5,3,6,7>: Cost 3 vmrglw <3,4,5,6>, <2,6,3,7> + 4176287534U, // <5,3,6,u>: Cost 3 vsldoi4 <2,5,3,6>, LHS + 3500041110U, // <5,3,7,0>: Cost 4 vmrglw <1,6,5,7>, <1,2,3,0> + 4176291059U, // <5,3,7,1>: Cost 4 vsldoi4 <2,5,3,7>, <1,6,5,7> + 4176291689U, // <5,3,7,2>: Cost 4 vsldoi4 <2,5,3,7>, <2,5,3,7> + 3500041842U, // <5,3,7,3>: Cost 4 vmrglw <1,6,5,7>, <2,2,3,3> + 3378342635U, // <5,3,7,4>: Cost 3 vsldoi12 <3,7,4,5>, <3,7,4,5> + 3500041763U, // <5,3,7,5>: Cost 4 vmrglw <1,6,5,7>, <2,1,3,5> + 3517957911U, // <5,3,7,6>: Cost 4 vmrglw <4,6,5,7>, <2,4,3,6> + 3498051514U, // <5,3,7,7>: Cost 4 vmrglw <1,3,5,7>, <2,6,3,7> + 3378637583U, // <5,3,7,u>: Cost 3 vsldoi12 <3,7,u,5>, <3,7,u,5> + 4176298086U, // <5,3,u,0>: Cost 3 vsldoi4 <2,5,3,u>, LHS + 3358214942U, // <5,3,u,1>: Cost 3 vsldoi12 <0,4,1,5>, <3,u,1,2> + 4176299882U, // <5,3,u,2>: Cost 3 vsldoi4 <2,5,3,u>, <2,5,3,u> + 4176300548U, // <5,3,u,3>: Cost 3 vsldoi4 <2,5,3,u>, <3,4,5,u> + 4176301366U, // <5,3,u,4>: Cost 3 vsldoi4 <2,5,3,u>, RHS + 3358214982U, // <5,3,u,5>: Cost 3 vsldoi12 <0,4,1,5>, <3,u,5,6> + 3510650728U, // <5,3,u,6>: Cost 3 vmrglw <3,4,5,6>, <2,5,3,6> + 3510667194U, // <5,3,u,7>: Cost 3 vmrglw <3,4,5,u>, <2,6,3,7> + 3358215005U, // <5,3,u,u>: Cost 3 vsldoi12 <0,4,1,5>, <3,u,u,2> + 3228262413U, // <5,4,0,0>: Cost 4 vsldoi8 <1,1,5,4>, <0,0,1,4> + 3242197094U, // <5,4,0,1>: Cost 3 vsldoi8 <3,4,5,4>, LHS + 4188251854U, // <5,4,0,2>: Cost 4 vsldoi4 <4,5,4,0>, <2,3,4,5> + 4188252672U, // <5,4,0,3>: Cost 4 vsldoi4 <4,5,4,0>, <3,4,5,4> + 3246178642U, // <5,4,0,4>: Cost 3 vsldoi8 <4,1,5,4>, <0,4,1,5> + 3510601422U, // <5,4,0,5>: Cost 3 vmrglw <3,4,5,0>, <2,3,4,5> + 3510601423U, // <5,4,0,6>: Cost 5 vmrglw <3,4,5,0>, <2,3,4,6> + 3518568746U, // <5,4,0,7>: Cost 4 vmrglw <4,7,5,0>, + 3242197661U, // <5,4,0,u>: Cost 3 vsldoi8 <3,4,5,4>, LHS + 3513930609U, // <5,4,1,0>: Cost 3 vmrglw <4,0,5,1>, <6,7,4,0> + 3228263259U, // <5,4,1,1>: Cost 4 vsldoi8 <1,1,5,4>, <1,1,5,4> + 3229590426U, // <5,4,1,2>: Cost 4 vsldoi8 <1,3,5,4>, <1,2,3,4> + 3229590525U, // <5,4,1,3>: Cost 4 vsldoi8 <1,3,5,4>, <1,3,5,4> + 3519237328U, // <5,4,1,4>: Cost 3 vmrglw <4,u,5,1>, <4,4,4,4> + 3358215138U, // <5,4,1,5>: Cost 3 vsldoi12 <0,4,1,5>, <4,1,5,0> + 3246179571U, // <5,4,1,6>: Cost 4 vsldoi8 <4,1,5,4>, <1,6,5,7> + 3519236764U, // <5,4,1,7>: Cost 4 vmrglw <4,u,5,1>, <3,6,4,7> + 3519235793U, // <5,4,1,u>: Cost 3 vmrglw <4,u,5,1>, <2,3,4,u> + 4188266598U, // <5,4,2,0>: Cost 4 vsldoi4 <4,5,4,2>, LHS + 3246179875U, // <5,4,2,1>: Cost 4 vsldoi8 <4,1,5,4>, <2,1,3,5> + 3236226664U, // <5,4,2,2>: Cost 4 vsldoi8 <2,4,5,4>, <2,2,2,2> + 3242198734U, // <5,4,2,3>: Cost 3 vsldoi8 <3,4,5,4>, <2,3,4,5> + 3236226855U, // <5,4,2,4>: Cost 4 vsldoi8 <2,4,5,4>, <2,4,5,4> + 3369716790U, // <5,4,2,5>: Cost 3 vsldoi12 <2,3,4,5>, <4,2,5,3> + 3242198970U, // <5,4,2,6>: Cost 4 vsldoi8 <3,4,5,4>, <2,6,3,7> + 3510618780U, // <5,4,2,7>: Cost 5 vmrglw <3,4,5,2>, <3,6,4,7> + 3386732058U, // <5,4,2,u>: Cost 3 vmrghw <5,2,1,3>, <4,u,5,1> + 3242199190U, // <5,4,3,0>: Cost 4 vsldoi8 <3,4,5,4>, <3,0,1,2> + 3497353253U, // <5,4,3,1>: Cost 4 vmrglw <1,2,5,3>, <0,0,4,1> + 3242199372U, // <5,4,3,2>: Cost 4 vsldoi8 <3,4,5,4>, <3,2,3,4> + 3242199452U, // <5,4,3,3>: Cost 4 vsldoi8 <3,4,5,4>, <3,3,3,3> + 3242199552U, // <5,4,3,4>: Cost 3 vsldoi8 <3,4,5,4>, <3,4,5,4> + 3515270862U, // <5,4,3,5>: Cost 3 vmrglw <4,2,5,3>, <2,3,4,5> + 3396258964U, // <5,4,3,6>: Cost 4 vsldoi12 <6,7,4,5>, <4,3,6,7> + 3497355932U, // <5,4,3,7>: Cost 5 vmrglw <1,2,5,3>, <3,6,4,7> + 3244854084U, // <5,4,3,u>: Cost 3 vsldoi8 <3,u,5,4>, <3,u,5,4> + 3245517717U, // <5,4,4,0>: Cost 3 vsldoi8 <4,0,5,4>, <4,0,5,4> + 3246181350U, // <5,4,4,1>: Cost 3 vsldoi8 <4,1,5,4>, <4,1,5,4> + 3242200118U, // <5,4,4,2>: Cost 4 vsldoi8 <3,4,5,4>, <4,2,5,3> + 3247508616U, // <5,4,4,3>: Cost 3 vsldoi8 <4,3,5,4>, <4,3,5,4> + 3358215376U, // <5,4,4,4>: Cost 3 vsldoi12 <0,4,1,5>, <4,4,4,4> + 3382398170U, // <5,4,4,5>: Cost 2 vsldoi12 <4,4,5,5>, <4,4,5,5> + 3242200446U, // <5,4,4,6>: Cost 4 vsldoi8 <3,4,5,4>, <4,6,5,7> + 3250163148U, // <5,4,4,7>: Cost 3 vsldoi8 <4,7,5,4>, <4,7,5,4> + 3382619381U, // <5,4,4,u>: Cost 2 vsldoi12 <4,4,u,5>, <4,4,u,5> + 4170375270U, // <5,4,5,0>: Cost 3 vsldoi4 <1,5,4,5>, LHS + 4170376343U, // <5,4,5,1>: Cost 3 vsldoi4 <1,5,4,5>, <1,5,4,5> + 3369717006U, // <5,4,5,2>: Cost 3 vsldoi12 <2,3,4,5>, <4,5,2,3> + 4170377366U, // <5,4,5,3>: Cost 4 vsldoi4 <1,5,4,5>, <3,0,1,2> + 4170378550U, // <5,4,5,4>: Cost 3 vsldoi4 <1,5,4,5>, RHS + 2315291958U, // <5,4,5,5>: Cost 2 vmrghw <5,5,5,5>, RHS + 3358215478U, // <5,4,5,6>: Cost 2 vsldoi12 <0,4,1,5>, RHS + 3519269532U, // <5,4,5,7>: Cost 4 vmrglw <4,u,5,5>, <3,6,4,7> + 3358215496U, // <5,4,5,u>: Cost 2 vsldoi12 <0,4,1,5>, RHS + 3389803410U, // <5,4,6,0>: Cost 3 vmrghw <5,6,7,0>, <4,0,5,1> + 3510651704U, // <5,4,6,1>: Cost 3 vmrglw <3,4,5,6>, <3,u,4,1> + 3516623835U, // <5,4,6,2>: Cost 4 vmrglw <4,4,5,6>, <4,1,4,2> + 4170385922U, // <5,4,6,3>: Cost 4 vsldoi4 <1,5,4,6>, <3,4,5,6> + 3389803728U, // <5,4,6,4>: Cost 3 vmrghw <5,6,7,0>, <4,4,4,4> + 2316062006U, // <5,4,6,5>: Cost 2 vmrghw <5,6,7,0>, RHS + 3510650008U, // <5,4,6,6>: Cost 4 vmrglw <3,4,5,6>, <1,5,4,6> + 3266089846U, // <5,4,6,7>: Cost 3 vsldoi8 <7,4,5,4>, <6,7,4,5> + 2316062249U, // <5,4,6,u>: Cost 2 vmrghw <5,6,7,0>, RHS + 3250164730U, // <5,4,7,0>: Cost 4 vsldoi8 <4,7,5,4>, <7,0,1,2> + 3500040229U, // <5,4,7,1>: Cost 4 vmrglw <1,6,5,7>, <0,0,4,1> + 3272062173U, // <5,4,7,2>: Cost 4 vsldoi8 , <7,2,u,4> + 3247510795U, // <5,4,7,3>: Cost 4 vsldoi8 <4,3,5,4>, <7,3,4,5> + 3250165094U, // <5,4,7,4>: Cost 3 vsldoi8 <4,7,5,4>, <7,4,5,6> + 3517957838U, // <5,4,7,5>: Cost 3 vmrglw <4,6,5,7>, <2,3,4,5> + 3517957839U, // <5,4,7,6>: Cost 4 vmrglw <4,6,5,7>, <2,3,4,6> + 3250165327U, // <5,4,7,7>: Cost 4 vsldoi8 <4,7,5,4>, <7,7,4,5> + 3268744872U, // <5,4,7,u>: Cost 3 vsldoi8 <7,u,5,4>, <7,u,5,4> + 4170399846U, // <5,4,u,0>: Cost 3 vsldoi4 <1,5,4,u>, LHS + 4170400922U, // <5,4,u,1>: Cost 3 vsldoi4 <1,5,4,u>, <1,5,4,u> + 4188317390U, // <5,4,u,2>: Cost 3 vsldoi4 <4,5,4,u>, <2,3,4,5> + 3242198734U, // <5,4,u,3>: Cost 3 vsldoi8 <3,4,5,4>, <2,3,4,5> + 4170403126U, // <5,4,u,4>: Cost 3 vsldoi4 <1,5,4,u>, RHS + 3385052702U, // <5,4,u,5>: Cost 2 vsldoi12 <4,u,5,5>, <4,u,5,5> + 3358215721U, // <5,4,u,6>: Cost 2 vsldoi12 <0,4,1,5>, RHS + 3274053936U, // <5,4,u,7>: Cost 3 vsldoi8 , + 3358215739U, // <5,4,u,u>: Cost 2 vsldoi12 <0,4,1,5>, RHS + 3510602236U, // <5,5,0,0>: Cost 3 vmrglw <3,4,5,0>, <3,4,5,0> + 3250831462U, // <5,5,0,1>: Cost 2 vsldoi8 <4,u,5,5>, LHS + 3510602238U, // <5,5,0,2>: Cost 4 vmrglw <3,4,5,0>, <3,4,5,2> + 3510602806U, // <5,5,0,3>: Cost 4 vmrglw <3,4,5,0>, <4,2,5,3> + 3358215778U, // <5,5,0,4>: Cost 3 vsldoi12 <0,4,1,5>, <5,0,4,1> + 3254813154U, // <5,5,0,5>: Cost 3 vsldoi8 <5,5,5,5>, <0,5,u,5> + 3385757794U, // <5,5,0,6>: Cost 3 vmrghw <5,0,6,1>, <5,6,7,0> + 3510603134U, // <5,5,0,7>: Cost 4 vmrglw <3,4,5,0>, <4,6,5,7> + 3250832029U, // <5,5,0,u>: Cost 2 vsldoi8 <4,u,5,5>, LHS + 3513928917U, // <5,5,1,0>: Cost 3 vmrglw <4,0,5,1>, <4,4,5,0> + 2445495834U, // <5,5,1,1>: Cost 2 vmrglw <4,u,5,1>, <4,u,5,1> + 3250832278U, // <5,5,1,2>: Cost 3 vsldoi8 <4,u,5,5>, <1,2,3,0> + 3229598718U, // <5,5,1,3>: Cost 4 vsldoi8 <1,3,5,5>, <1,3,5,5> + 3386306231U, // <5,5,1,4>: Cost 3 vsldoi12 <5,1,4,5>, <5,1,4,5> + 3519237338U, // <5,5,1,5>: Cost 3 vmrglw <4,u,5,1>, <4,4,5,5> + 3519236610U, // <5,5,1,6>: Cost 3 vmrglw <4,u,5,1>, <3,4,5,6> + 3519235315U, // <5,5,1,7>: Cost 4 vmrglw <4,u,5,1>, <1,6,5,7> + 2445495834U, // <5,5,1,u>: Cost 2 vmrglw <4,u,5,1>, <4,u,5,1> + 3510618620U, // <5,5,2,0>: Cost 4 vmrglw <3,4,5,2>, <3,4,5,0> + 3358215915U, // <5,5,2,1>: Cost 4 vsldoi12 <0,4,1,5>, <5,2,1,3> + 3510618622U, // <5,5,2,2>: Cost 3 vmrglw <3,4,5,2>, <3,4,5,2> + 3369717502U, // <5,5,2,3>: Cost 3 vsldoi12 <2,3,4,5>, <5,2,3,4> + 3369717510U, // <5,5,2,4>: Cost 4 vsldoi12 <2,3,4,5>, <5,2,4,3> + 3385052943U, // <5,5,2,5>: Cost 3 vsldoi12 <4,u,5,5>, <5,2,5,3> + 3250833338U, // <5,5,2,6>: Cost 3 vsldoi8 <4,u,5,5>, <2,6,3,7> + 3510619518U, // <5,5,2,7>: Cost 4 vmrglw <3,4,5,2>, <4,6,5,7> + 3373035307U, // <5,5,2,u>: Cost 3 vsldoi12 <2,u,4,5>, <5,2,u,4> + 3250833558U, // <5,5,3,0>: Cost 3 vsldoi8 <4,u,5,5>, <3,0,1,2> + 3228272874U, // <5,5,3,1>: Cost 4 vsldoi8 <1,1,5,5>, <3,1,1,5> + 3369717573U, // <5,5,3,2>: Cost 4 vsldoi12 <2,3,4,5>, <5,3,2,3> + 3497354155U, // <5,5,3,3>: Cost 3 vmrglw <1,2,5,3>, <1,2,5,3> + 3250833922U, // <5,5,3,4>: Cost 3 vsldoi8 <4,u,5,5>, <3,4,5,6> + 3521244702U, // <5,5,3,5>: Cost 3 vmrglw <5,2,5,3>, <4,u,5,5> + 3497355778U, // <5,5,3,6>: Cost 4 vmrglw <1,2,5,3>, <3,4,5,6> + 3497354483U, // <5,5,3,7>: Cost 4 vmrglw <1,2,5,3>, <1,6,5,7> + 3250834206U, // <5,5,3,u>: Cost 3 vsldoi8 <4,u,5,5>, <3,u,1,2> + 3250834322U, // <5,5,4,0>: Cost 3 vsldoi8 <4,u,5,5>, <4,0,5,1> + 3358216079U, // <5,5,4,1>: Cost 4 vsldoi12 <0,4,1,5>, <5,4,1,5> + 3369717656U, // <5,5,4,2>: Cost 4 vsldoi12 <2,3,4,5>, <5,4,2,5> + 3510635574U, // <5,5,4,3>: Cost 4 vmrglw <3,4,5,4>, <4,2,5,3> + 3248180442U, // <5,5,4,4>: Cost 2 vsldoi8 <4,4,5,5>, <4,4,5,5> + 3250834742U, // <5,5,4,5>: Cost 2 vsldoi8 <4,u,5,5>, RHS + 3518600550U, // <5,5,4,6>: Cost 3 vmrglw <4,7,5,4>, <7,4,5,6> + 3510635902U, // <5,5,4,7>: Cost 4 vmrglw <3,4,5,4>, <4,6,5,7> + 3250834974U, // <5,5,4,u>: Cost 2 vsldoi8 <4,u,5,5>, <4,u,5,5> + 3120595046U, // <5,5,5,0>: Cost 2 vsldoi4 <5,5,5,5>, LHS + 3519269778U, // <5,5,5,1>: Cost 3 vmrglw <4,u,5,5>, <4,0,5,1> + 3250835215U, // <5,5,5,2>: Cost 3 vsldoi8 <4,u,5,5>, <5,2,5,3> + 3519270671U, // <5,5,5,3>: Cost 3 vmrglw <4,u,5,5>, <5,2,5,3> + 3120598326U, // <5,5,5,4>: Cost 2 vsldoi4 <5,5,5,5>, RHS + 1638321462U, // <5,5,5,5>: Cost 1 vspltisw1 RHS + 3519269378U, // <5,5,5,6>: Cost 3 vmrglw <4,u,5,5>, <3,4,5,6> + 3519270999U, // <5,5,5,7>: Cost 3 vmrglw <4,u,5,5>, <5,6,5,7> + 1638321462U, // <5,5,5,u>: Cost 1 vspltisw1 RHS + 3389804148U, // <5,5,6,0>: Cost 3 vmrghw <5,6,7,0>, <5,0,6,1> + 3534539666U, // <5,5,6,1>: Cost 3 vmrglw <7,4,5,6>, <4,0,5,1> + 3250835962U, // <5,5,6,2>: Cost 3 vsldoi8 <4,u,5,5>, <6,2,7,3> + 4170459650U, // <5,5,6,3>: Cost 4 vsldoi4 <1,5,5,6>, <3,4,5,6> + 3389624396U, // <5,5,6,4>: Cost 3 vsldoi12 <5,6,4,5>, <5,6,4,5> + 3385053271U, // <5,5,6,5>: Cost 3 vsldoi12 <4,u,5,5>, <5,6,5,7> + 2436909570U, // <5,5,6,6>: Cost 2 vmrglw <3,4,5,6>, <3,4,5,6> + 3250836302U, // <5,5,6,7>: Cost 3 vsldoi8 <4,u,5,5>, <6,7,0,1> + 2436909570U, // <5,5,6,u>: Cost 2 vmrglw <3,4,5,6>, <3,4,5,6> + 3250836474U, // <5,5,7,0>: Cost 3 vsldoi8 <4,u,5,5>, <7,0,1,2> + 3517959058U, // <5,5,7,1>: Cost 4 vmrglw <4,6,5,7>, <4,0,5,1> + 4188382926U, // <5,5,7,2>: Cost 4 vsldoi4 <4,5,5,7>, <2,3,4,5> + 3500041131U, // <5,5,7,3>: Cost 4 vmrglw <1,6,5,7>, <1,2,5,3> + 3250836838U, // <5,5,7,4>: Cost 3 vsldoi8 <4,u,5,5>, <7,4,5,6> + 3254818230U, // <5,5,7,5>: Cost 3 vsldoi8 <5,5,5,5>, <7,5,5,5> + 3500042754U, // <5,5,7,6>: Cost 4 vmrglw <1,6,5,7>, <3,4,5,6> + 3500041459U, // <5,5,7,7>: Cost 3 vmrglw <1,6,5,7>, <1,6,5,7> + 3250837122U, // <5,5,7,u>: Cost 3 vsldoi8 <4,u,5,5>, <7,u,1,2> + 3120595046U, // <5,5,u,0>: Cost 2 vsldoi4 <5,5,5,5>, LHS + 3250837294U, // <5,5,u,1>: Cost 2 vsldoi8 <4,u,5,5>, LHS + 3250837381U, // <5,5,u,2>: Cost 3 vsldoi8 <4,u,5,5>, + 3250837436U, // <5,5,u,3>: Cost 3 vsldoi8 <4,u,5,5>, + 3120598326U, // <5,5,u,4>: Cost 2 vsldoi4 <5,5,5,5>, RHS + 1638321462U, // <5,5,u,5>: Cost 1 vspltisw1 RHS + 2436909570U, // <5,5,u,6>: Cost 2 vmrglw <3,4,5,6>, <3,4,5,6> + 3250837760U, // <5,5,u,7>: Cost 3 vsldoi8 <4,u,5,5>, + 1638321462U, // <5,5,u,u>: Cost 1 vspltisw1 RHS + 3242213376U, // <5,6,0,0>: Cost 3 vsldoi8 <3,4,5,6>, <0,0,0,0> + 3242213478U, // <5,6,0,1>: Cost 2 vsldoi8 <3,4,5,6>, LHS + 3236241581U, // <5,6,0,2>: Cost 4 vsldoi8 <2,4,5,6>, <0,2,1,2> + 3242213632U, // <5,6,0,3>: Cost 3 vsldoi8 <3,4,5,6>, <0,3,1,4> + 3242213714U, // <5,6,0,4>: Cost 3 vsldoi8 <3,4,5,6>, <0,4,1,5> + 3242213796U, // <5,6,0,5>: Cost 4 vsldoi8 <3,4,5,6>, <0,5,1,6> + 3242213878U, // <5,6,0,6>: Cost 4 vsldoi8 <3,4,5,6>, <0,6,1,7> + 3510603062U, // <5,6,0,7>: Cost 3 vmrglw <3,4,5,0>, RHS + 3242214045U, // <5,6,0,u>: Cost 2 vsldoi8 <3,4,5,6>, LHS + 3230270180U, // <5,6,1,0>: Cost 4 vsldoi8 <1,4,5,6>, <1,0,1,2> + 3242214196U, // <5,6,1,1>: Cost 3 vsldoi8 <3,4,5,6>, <1,1,1,1> + 3242214294U, // <5,6,1,2>: Cost 3 vsldoi8 <3,4,5,6>, <1,2,3,0> + 3242214370U, // <5,6,1,3>: Cost 4 vsldoi8 <3,4,5,6>, <1,3,2,4> + 3230270544U, // <5,6,1,4>: Cost 3 vsldoi8 <1,4,5,6>, <1,4,5,6> + 3230934177U, // <5,6,1,5>: Cost 4 vsldoi8 <1,5,5,6>, <1,5,5,6> + 3519238968U, // <5,6,1,6>: Cost 3 vmrglw <4,u,5,1>, <6,6,6,6> + 2445495606U, // <5,6,1,7>: Cost 2 vmrglw <4,u,5,1>, RHS + 2445495607U, // <5,6,1,u>: Cost 2 vmrglw <4,u,5,1>, RHS + 3236242877U, // <5,6,2,0>: Cost 4 vsldoi8 <2,4,5,6>, <2,0,1,2> + 3242214943U, // <5,6,2,1>: Cost 4 vsldoi8 <3,4,5,6>, <2,1,3,1> + 3236243048U, // <5,6,2,2>: Cost 3 vsldoi8 <2,4,5,6>, <2,2,2,2> + 3242215078U, // <5,6,2,3>: Cost 3 vsldoi8 <3,4,5,6>, <2,3,0,1> + 3236243241U, // <5,6,2,4>: Cost 3 vsldoi8 <2,4,5,6>, <2,4,5,6> + 3242215272U, // <5,6,2,5>: Cost 3 vsldoi8 <3,4,5,6>, <2,5,3,6> + 3242215354U, // <5,6,2,6>: Cost 3 vsldoi8 <3,4,5,6>, <2,6,3,7> + 3510619446U, // <5,6,2,7>: Cost 3 vmrglw <3,4,5,2>, RHS + 3238897773U, // <5,6,2,u>: Cost 3 vsldoi8 <2,u,5,6>, <2,u,5,6> + 3242215574U, // <5,6,3,0>: Cost 3 vsldoi8 <3,4,5,6>, <3,0,1,2> + 3230271749U, // <5,6,3,1>: Cost 4 vsldoi8 <1,4,5,6>, <3,1,4,5> + 3236243777U, // <5,6,3,2>: Cost 4 vsldoi8 <2,4,5,6>, <3,2,2,2> + 3242215836U, // <5,6,3,3>: Cost 3 vsldoi8 <3,4,5,6>, <3,3,3,3> + 3242215938U, // <5,6,3,4>: Cost 2 vsldoi8 <3,4,5,6>, <3,4,5,6> + 3373183549U, // <5,6,3,5>: Cost 4 vsldoi12 <2,u,6,5>, <6,3,5,7> + 3242216050U, // <5,6,3,6>: Cost 4 vsldoi8 <3,4,5,6>, <3,6,0,1> + 3497356598U, // <5,6,3,7>: Cost 3 vmrglw <1,2,5,3>, RHS + 3244870470U, // <5,6,3,u>: Cost 2 vsldoi8 <3,u,5,6>, <3,u,5,6> + 4188430438U, // <5,6,4,0>: Cost 3 vsldoi4 <4,5,6,4>, LHS + 3242216394U, // <5,6,4,1>: Cost 4 vsldoi8 <3,4,5,6>, <4,1,2,3> + 3394122353U, // <5,6,4,2>: Cost 3 vsldoi12 <6,4,2,5>, <6,4,2,5> + 4188432898U, // <5,6,4,3>: Cost 3 vsldoi4 <4,5,6,4>, <3,4,5,6> + 3248188635U, // <5,6,4,4>: Cost 3 vsldoi8 <4,4,5,6>, <4,4,5,6> + 3242216758U, // <5,6,4,5>: Cost 2 vsldoi8 <3,4,5,6>, RHS + 3249515901U, // <5,6,4,6>: Cost 3 vsldoi8 <4,6,5,6>, <4,6,5,6> + 3510635830U, // <5,6,4,7>: Cost 3 vmrglw <3,4,5,4>, RHS + 3242217001U, // <5,6,4,u>: Cost 2 vsldoi8 <3,4,5,6>, RHS + 3373183660U, // <5,6,5,0>: Cost 4 vsldoi12 <2,u,6,5>, <6,5,0,1> + 3230273221U, // <5,6,5,1>: Cost 4 vsldoi8 <1,4,5,6>, <5,1,6,1> + 3242217240U, // <5,6,5,2>: Cost 3 vsldoi8 <3,4,5,6>, <5,2,6,3> + 3242217295U, // <5,6,5,3>: Cost 4 vsldoi8 <3,4,5,6>, <5,3,3,4> + 3254161332U, // <5,6,5,4>: Cost 3 vsldoi8 <5,4,5,6>, <5,4,5,6> + 3242217486U, // <5,6,5,5>: Cost 3 vsldoi8 <3,4,5,6>, <5,5,6,6> + 3242217508U, // <5,6,5,6>: Cost 3 vsldoi8 <3,4,5,6>, <5,6,0,1> + 2445528374U, // <5,6,5,7>: Cost 2 vmrglw <4,u,5,5>, RHS + 2445528375U, // <5,6,5,u>: Cost 2 vmrglw <4,u,5,5>, RHS + 4194418790U, // <5,6,6,0>: Cost 3 vsldoi4 <5,5,6,6>, LHS + 3498708677U, // <5,6,6,1>: Cost 4 vmrglw <1,4,5,6>, <5,1,6,1> + 3389805050U, // <5,6,6,2>: Cost 3 vmrghw <5,6,7,0>, <6,2,7,3> + 3510652696U, // <5,6,6,3>: Cost 3 vmrglw <3,4,5,6>, <5,2,6,3> + 4194422070U, // <5,6,6,4>: Cost 3 vsldoi4 <5,5,6,6>, RHS + 4194422798U, // <5,6,6,5>: Cost 3 vsldoi4 <5,5,6,6>, <5,5,6,6> + 3510652942U, // <5,6,6,6>: Cost 3 vmrglw <3,4,5,6>, <5,5,6,6> + 2436910390U, // <5,6,6,7>: Cost 2 vmrglw <3,4,5,6>, RHS + 2436910391U, // <5,6,6,u>: Cost 2 vmrglw <3,4,5,6>, RHS + 2040971366U, // <5,6,7,0>: Cost 1 vsldoi4 RHS, LHS + 3114713908U, // <5,6,7,1>: Cost 2 vsldoi4 RHS, <1,1,1,1> + 3114714728U, // <5,6,7,2>: Cost 2 vsldoi4 RHS, <2,2,2,2> + 3114715286U, // <5,6,7,3>: Cost 2 vsldoi4 RHS, <3,0,1,2> + 2040974646U, // <5,6,7,4>: Cost 1 vsldoi4 RHS, RHS + 3114717188U, // <5,6,7,5>: Cost 2 vsldoi4 RHS, <5,5,5,5> + 3114717690U, // <5,6,7,6>: Cost 2 vsldoi4 RHS, <6,2,7,3> + 3114718828U, // <5,6,7,7>: Cost 2 vsldoi4 RHS, <7,7,7,7> + 2040977198U, // <5,6,7,u>: Cost 1 vsldoi4 RHS, LHS + 2040979558U, // <5,6,u,0>: Cost 1 vsldoi4 RHS, LHS + 3242219310U, // <5,6,u,1>: Cost 2 vsldoi8 <3,4,5,6>, LHS + 3114722920U, // <5,6,u,2>: Cost 2 vsldoi4 RHS, <2,2,2,2> + 3114723478U, // <5,6,u,3>: Cost 2 vsldoi4 RHS, <3,0,1,2> + 2040982839U, // <5,6,u,4>: Cost 1 vsldoi4 RHS, RHS + 3242219674U, // <5,6,u,5>: Cost 2 vsldoi8 <3,4,5,6>, RHS + 3114725882U, // <5,6,u,6>: Cost 2 vsldoi4 RHS, <6,2,7,3> + 2436926774U, // <5,6,u,7>: Cost 2 vmrglw <3,4,5,u>, RHS + 2040985390U, // <5,6,u,u>: Cost 1 vsldoi4 RHS, LHS + 3231604736U, // <5,7,0,0>: Cost 4 vsldoi8 <1,6,5,7>, <0,0,0,0> + 3231604838U, // <5,7,0,1>: Cost 3 vsldoi8 <1,6,5,7>, LHS + 4188473443U, // <5,7,0,2>: Cost 4 vsldoi4 <4,5,7,0>, <2,u,4,5> + 3518566906U, // <5,7,0,3>: Cost 4 vmrglw <4,7,5,0>, <6,2,7,3> + 3231605074U, // <5,7,0,4>: Cost 3 vsldoi8 <1,6,5,7>, <0,4,1,5> + 3518565612U, // <5,7,0,5>: Cost 4 vmrglw <4,7,5,0>, <4,4,7,5> + 4200420074U, // <5,7,0,6>: Cost 4 vsldoi4 <6,5,7,0>, <6,5,7,0> + 4188476410U, // <5,7,0,7>: Cost 4 vsldoi4 <4,5,7,0>, <7,0,1,2> + 3231605405U, // <5,7,0,u>: Cost 3 vsldoi8 <1,6,5,7>, LHS + 3519238242U, // <5,7,1,0>: Cost 3 vmrglw <4,u,5,1>, <5,6,7,0> + 3513930475U, // <5,7,1,1>: Cost 3 vmrglw <4,0,5,1>, <6,5,7,1> + 3231605654U, // <5,7,1,2>: Cost 4 vsldoi8 <1,6,5,7>, <1,2,3,0> + 3519238650U, // <5,7,1,3>: Cost 3 vmrglw <4,u,5,1>, <6,2,7,3> + 3519238246U, // <5,7,1,4>: Cost 3 vmrglw <4,u,5,1>, <5,6,7,4> + 3231605871U, // <5,7,1,5>: Cost 4 vsldoi8 <1,6,5,7>, <1,5,0,1> + 3231606003U, // <5,7,1,6>: Cost 3 vsldoi8 <1,6,5,7>, <1,6,5,7> + 3519238978U, // <5,7,1,7>: Cost 3 vmrglw <4,u,5,1>, <6,6,7,7> + 3232933269U, // <5,7,1,u>: Cost 3 vsldoi8 <1,u,5,7>, <1,u,5,7> + 3517919330U, // <5,7,2,0>: Cost 4 vmrglw <4,6,5,2>, <5,6,7,0> + 3231606307U, // <5,7,2,1>: Cost 4 vsldoi8 <1,6,5,7>, <2,1,3,5> + 3231606376U, // <5,7,2,2>: Cost 4 vsldoi8 <1,6,5,7>, <2,2,2,2> + 3517919738U, // <5,7,2,3>: Cost 3 vmrglw <4,6,5,2>, <6,2,7,3> + 3517919334U, // <5,7,2,4>: Cost 4 vmrglw <4,6,5,2>, <5,6,7,4> + 3231606633U, // <5,7,2,5>: Cost 4 vsldoi8 <1,6,5,7>, <2,5,3,7> + 3229616058U, // <5,7,2,6>: Cost 4 vsldoi8 <1,3,5,7>, <2,6,3,7> + 3517920066U, // <5,7,2,7>: Cost 4 vmrglw <4,6,5,2>, <6,6,7,7> + 3517919738U, // <5,7,2,u>: Cost 3 vmrglw <4,6,5,2>, <6,2,7,3> + 3231606934U, // <5,7,3,0>: Cost 4 vsldoi8 <1,6,5,7>, <3,0,1,2> + 3231607063U, // <5,7,3,1>: Cost 4 vsldoi8 <1,6,5,7>, <3,1,6,5> + 3249523020U, // <5,7,3,2>: Cost 4 vsldoi8 <4,6,5,7>, <3,2,3,4> + 3231607196U, // <5,7,3,3>: Cost 4 vsldoi8 <1,6,5,7>, <3,3,3,3> + 3399578891U, // <5,7,3,4>: Cost 3 vsldoi12 <7,3,4,5>, <7,3,4,5> + 3519255198U, // <5,7,3,5>: Cost 4 vmrglw <4,u,5,3>, <6,4,7,5> + 3243551397U, // <5,7,3,6>: Cost 4 vsldoi8 <3,6,5,7>, <3,6,5,7> + 3378345253U, // <5,7,3,7>: Cost 4 vsldoi12 <3,7,4,5>, <7,3,7,4> + 3399873839U, // <5,7,3,u>: Cost 3 vsldoi12 <7,3,u,5>, <7,3,u,5> + 3399947576U, // <5,7,4,0>: Cost 3 vsldoi12 <7,4,0,5>, <7,4,0,5> + 3231607778U, // <5,7,4,1>: Cost 4 vsldoi8 <1,6,5,7>, <4,1,5,0> + 4188506211U, // <5,7,4,2>: Cost 4 vsldoi4 <4,5,7,4>, <2,u,4,5> + 3247533195U, // <5,7,4,3>: Cost 4 vsldoi8 <4,3,5,7>, <4,3,5,7> + 3400242524U, // <5,7,4,4>: Cost 3 vsldoi12 <7,4,4,5>, <7,4,4,5> + 3231608118U, // <5,7,4,5>: Cost 3 vsldoi8 <1,6,5,7>, RHS + 3249524094U, // <5,7,4,6>: Cost 3 vsldoi8 <4,6,5,7>, <4,6,5,7> + 3250187727U, // <5,7,4,7>: Cost 3 vsldoi8 <4,7,5,7>, <4,7,5,7> + 3231608361U, // <5,7,4,u>: Cost 3 vsldoi8 <1,6,5,7>, RHS + 3519271010U, // <5,7,5,0>: Cost 3 vmrglw <4,u,5,5>, <5,6,7,0> + 3231608521U, // <5,7,5,1>: Cost 4 vsldoi8 <1,6,5,7>, <5,1,6,5> + 3231608609U, // <5,7,5,2>: Cost 4 vsldoi8 <1,6,5,7>, <5,2,7,3> + 3519271418U, // <5,7,5,3>: Cost 3 vmrglw <4,u,5,5>, <6,2,7,3> + 3519271014U, // <5,7,5,4>: Cost 3 vmrglw <4,u,5,5>, <5,6,7,4> + 3389035958U, // <5,7,5,5>: Cost 3 vmrghw <5,5,5,5>, <7,5,5,5> + 3255496791U, // <5,7,5,6>: Cost 3 vsldoi8 <5,6,5,7>, <5,6,5,7> + 3519271746U, // <5,7,5,7>: Cost 3 vmrglw <4,u,5,5>, <6,6,7,7> + 3519271018U, // <5,7,5,u>: Cost 3 vmrglw <4,u,5,5>, <5,6,7,u> + 3389805562U, // <5,7,6,0>: Cost 3 vmrghw <5,6,7,0>, <7,0,1,2> + 3389805642U, // <5,7,6,1>: Cost 4 vmrghw <5,6,7,0>, <7,1,1,1> + 3389805716U, // <5,7,6,2>: Cost 3 vmrghw <5,6,7,0>, <7,2,0,3> + 4200466946U, // <5,7,6,3>: Cost 3 vsldoi4 <6,5,7,6>, <3,4,5,6> + 3389805926U, // <5,7,6,4>: Cost 3 vmrghw <5,6,7,0>, <7,4,5,6> + 3389806017U, // <5,7,6,5>: Cost 3 vmrghw <5,6,7,0>, <7,5,6,7> + 4200469232U, // <5,7,6,6>: Cost 3 vsldoi4 <6,5,7,6>, <6,5,7,6> + 3389806188U, // <5,7,6,7>: Cost 3 vmrghw <5,6,7,0>, <7,7,7,7> + 3389806210U, // <5,7,6,u>: Cost 3 vmrghw <5,6,7,0>, <7,u,1,2> + 4188528742U, // <5,7,7,0>: Cost 4 vsldoi4 <4,5,7,7>, LHS + 4194501875U, // <5,7,7,1>: Cost 4 vsldoi4 <5,5,7,7>, <1,6,5,7> + 4188530787U, // <5,7,7,2>: Cost 4 vsldoi4 <4,5,7,7>, <2,u,4,5> + 3500044065U, // <5,7,7,3>: Cost 4 vmrglw <1,6,5,7>, <5,2,7,3> + 3402233423U, // <5,7,7,4>: Cost 3 vsldoi12 <7,7,4,5>, <7,7,4,5> + 3500043986U, // <5,7,7,5>: Cost 4 vmrglw <1,6,5,7>, <5,1,7,5> + 4200477425U, // <5,7,7,6>: Cost 4 vsldoi4 <6,5,7,7>, <6,5,7,7> + 3518625388U, // <5,7,7,7>: Cost 3 vmrglw <4,7,5,7>, <7,7,7,7> + 3402528371U, // <5,7,7,u>: Cost 3 vsldoi12 <7,7,u,5>, <7,7,u,5> + 3519295586U, // <5,7,u,0>: Cost 3 vmrglw <4,u,5,u>, <5,6,7,0> + 3231610670U, // <5,7,u,1>: Cost 3 vsldoi8 <1,6,5,7>, LHS + 3389805716U, // <5,7,u,2>: Cost 3 vmrghw <5,6,7,0>, <7,2,0,3> + 3519295994U, // <5,7,u,3>: Cost 3 vmrglw <4,u,5,u>, <6,2,7,3> + 3519295590U, // <5,7,u,4>: Cost 3 vmrglw <4,u,5,u>, <5,6,7,4> + 3231611034U, // <5,7,u,5>: Cost 3 vsldoi8 <1,6,5,7>, RHS + 4200485618U, // <5,7,u,6>: Cost 3 vsldoi4 <6,5,7,u>, <6,5,7,u> + 3519296322U, // <5,7,u,7>: Cost 3 vmrglw <4,u,5,u>, <6,6,7,7> + 3231611237U, // <5,7,u,u>: Cost 3 vsldoi8 <1,6,5,7>, LHS + 3242229760U, // <5,u,0,0>: Cost 3 vsldoi8 <3,4,5,u>, <0,0,0,0> + 3242229862U, // <5,u,0,1>: Cost 2 vsldoi8 <3,4,5,u>, LHS + 3518567418U, // <5,u,0,2>: Cost 3 vmrglw <4,7,5,0>, <7,0,1,2> + 3510599836U, // <5,u,0,3>: Cost 3 vmrglw <3,4,5,0>, LHS + 3358217965U, // <5,u,0,4>: Cost 3 vsldoi12 <0,4,1,5>, + 3513255666U, // <5,u,0,5>: Cost 3 vmrglw <3,u,5,0>, <2,3,u,5> + 3385757794U, // <5,u,0,6>: Cost 3 vmrghw <5,0,6,1>, <5,6,7,0> + 3510603080U, // <5,u,0,7>: Cost 3 vmrglw <3,4,5,0>, RHS + 3242230429U, // <5,u,0,u>: Cost 2 vsldoi8 <3,4,5,u>, LHS + 4170637414U, // <5,u,1,0>: Cost 3 vsldoi4 <1,5,u,1>, LHS + 2445495834U, // <5,u,1,1>: Cost 2 vmrglw <4,u,5,1>, <4,u,5,1> + 3358218030U, // <5,u,1,2>: Cost 2 vsldoi12 <0,4,1,5>, LHS + 2445492380U, // <5,u,1,3>: Cost 2 vmrglw <4,u,5,1>, LHS + 3230286930U, // <5,u,1,4>: Cost 3 vsldoi8 <1,4,5,u>, <1,4,5,u> + 3360872262U, // <5,u,1,5>: Cost 3 vsldoi12 <0,u,1,5>, + 3231614196U, // <5,u,1,6>: Cost 3 vsldoi8 <1,6,5,u>, <1,6,5,u> + 2445495624U, // <5,u,1,7>: Cost 2 vmrglw <4,u,5,1>, RHS + 3358218084U, // <5,u,1,u>: Cost 2 vsldoi12 <0,4,1,5>, LHS + 3519248261U, // <5,u,2,0>: Cost 3 vmrglw <4,u,5,2>, + 3386734382U, // <5,u,2,1>: Cost 3 vmrghw <5,2,1,3>, LHS + 3236259432U, // <5,u,2,2>: Cost 3 vsldoi8 <2,4,5,u>, <2,2,2,2> + 3358218120U, // <5,u,2,3>: Cost 3 vsldoi12 <0,4,1,5>, + 3236259627U, // <5,u,2,4>: Cost 3 vsldoi8 <2,4,5,u>, <2,4,5,u> + 3361388442U, // <5,u,2,5>: Cost 3 vsldoi12 <0,u,u,5>, + 3242231738U, // <5,u,2,6>: Cost 3 vsldoi8 <3,4,5,u>, <2,6,3,7> + 3510619464U, // <5,u,2,7>: Cost 3 vmrglw <3,4,5,2>, RHS + 3358218165U, // <5,u,2,u>: Cost 3 vsldoi12 <0,4,1,5>, + 3358218172U, // <5,u,3,0>: Cost 3 vsldoi12 <0,4,1,5>, + 3358218181U, // <5,u,3,1>: Cost 4 vsldoi12 <0,4,1,5>, + 4188128974U, // <5,u,3,2>: Cost 3 vsldoi4 <4,5,2,3>, <2,3,4,5> + 3497353372U, // <5,u,3,3>: Cost 3 vmrglw <1,2,5,3>, LHS + 3242232324U, // <5,u,3,4>: Cost 2 vsldoi8 <3,4,5,u>, <3,4,5,u> + 3389036525U, // <5,u,3,5>: Cost 3 vsldoi12 <5,5,5,5>, + 3497355805U, // <5,u,3,6>: Cost 4 vmrglw <1,2,5,3>, <3,4,u,6> + 3497356616U, // <5,u,3,7>: Cost 3 vmrglw <1,2,5,3>, RHS + 3244886856U, // <5,u,3,u>: Cost 2 vsldoi8 <3,u,5,u>, <3,u,5,u> + 3245550489U, // <5,u,4,0>: Cost 2 vsldoi8 <4,0,5,u>, <4,0,5,u> + 3405994010U, // <5,u,4,1>: Cost 2 vsldoi12 , + 3246877755U, // <5,u,4,2>: Cost 3 vsldoi8 <4,2,5,u>, <4,2,5,u> + 3369719852U, // <5,u,4,3>: Cost 3 vsldoi12 <2,3,4,5>, + 3248205021U, // <5,u,4,4>: Cost 2 vsldoi8 <4,4,5,u>, <4,4,5,u> + 3242233142U, // <5,u,4,5>: Cost 2 vsldoi8 <3,4,5,u>, RHS + 3249532287U, // <5,u,4,6>: Cost 3 vsldoi8 <4,6,5,u>, <4,6,5,u> + 3510635848U, // <5,u,4,7>: Cost 3 vmrglw <3,4,5,4>, RHS + 3242233385U, // <5,u,4,u>: Cost 2 vsldoi8 <3,4,5,u>, RHS + 3120595046U, // <5,u,5,0>: Cost 2 vsldoi4 <5,5,5,5>, LHS + 2315294510U, // <5,u,5,1>: Cost 2 vmrghw <5,5,5,5>, LHS + 3370014834U, // <5,u,5,2>: Cost 3 vsldoi12 <2,3,u,5>, + 2445525148U, // <5,u,5,3>: Cost 2 vmrglw <4,u,5,5>, LHS + 3120598326U, // <5,u,5,4>: Cost 2 vsldoi4 <5,5,5,5>, RHS + 1638321462U, // <5,u,5,5>: Cost 1 vspltisw1 RHS + 3358218394U, // <5,u,5,6>: Cost 2 vsldoi12 <0,4,1,5>, RHS + 2445528392U, // <5,u,5,7>: Cost 2 vmrglw <4,u,5,5>, RHS + 1638321462U, // <5,u,5,u>: Cost 1 vspltisw1 RHS + 4176650342U, // <5,u,6,0>: Cost 3 vsldoi4 <2,5,u,6>, LHS + 2316064558U, // <5,u,6,1>: Cost 2 vmrghw <5,6,7,0>, LHS + 4176652181U, // <5,u,6,2>: Cost 3 vsldoi4 <2,5,u,6>, <2,5,u,6> + 2436907164U, // <5,u,6,3>: Cost 2 vmrglw <3,4,5,6>, LHS + 4176653622U, // <5,u,6,4>: Cost 3 vsldoi4 <2,5,u,6>, RHS + 2316064922U, // <5,u,6,5>: Cost 2 vmrghw <5,6,7,0>, RHS + 2436909570U, // <5,u,6,6>: Cost 2 vmrglw <3,4,5,6>, <3,4,5,6> + 2436910408U, // <5,u,6,7>: Cost 2 vmrglw <3,4,5,6>, RHS + 2436907169U, // <5,u,6,u>: Cost 2 vmrglw <3,4,5,6>, LHS + 2041118822U, // <5,u,7,0>: Cost 1 vsldoi4 RHS, LHS + 3114861364U, // <5,u,7,1>: Cost 2 vsldoi4 RHS, <1,1,1,1> + 3114862184U, // <5,u,7,2>: Cost 2 vsldoi4 RHS, <2,2,2,2> + 3114862742U, // <5,u,7,3>: Cost 2 vsldoi4 RHS, <3,0,1,2> + 2041122120U, // <5,u,7,4>: Cost 1 vsldoi4 RHS, RHS + 3114864644U, // <5,u,7,5>: Cost 2 vsldoi4 RHS, <5,5,5,5> + 3114865146U, // <5,u,7,6>: Cost 2 vsldoi4 RHS, <6,2,7,3> + 3114865658U, // <5,u,7,7>: Cost 2 vsldoi4 RHS, <7,0,1,2> + 2041124654U, // <5,u,7,u>: Cost 1 vsldoi4 RHS, LHS + 2041127014U, // <5,u,u,0>: Cost 1 vsldoi4 RHS, LHS + 3242235694U, // <5,u,u,1>: Cost 2 vsldoi8 <3,4,5,u>, LHS + 3358218597U, // <5,u,u,2>: Cost 2 vsldoi12 <0,4,1,5>, LHS + 2436923548U, // <5,u,u,3>: Cost 2 vmrglw <3,4,5,u>, LHS + 2041130313U, // <5,u,u,4>: Cost 1 vsldoi4 RHS, RHS + 1638321462U, // <5,u,u,5>: Cost 1 vspltisw1 RHS + 3358218637U, // <5,u,u,6>: Cost 2 vsldoi12 <0,4,1,5>, RHS + 2436926792U, // <5,u,u,7>: Cost 2 vmrglw <3,4,5,u>, RHS + 2041132846U, // <5,u,u,u>: Cost 1 vsldoi4 RHS, LHS + 3376431104U, // <6,0,0,0>: Cost 3 vsldoi12 <3,4,5,6>, <0,0,0,0> + 3376431114U, // <6,0,0,1>: Cost 3 vsldoi12 <3,4,5,6>, <0,0,1,1> + 3234275505U, // <6,0,0,2>: Cost 4 vsldoi8 <2,1,6,0>, <0,2,1,6> + 3517313467U, // <6,0,0,3>: Cost 4 vmrglw <4,5,6,0>, <6,2,0,3> + 3376431141U, // <6,0,0,4>: Cost 4 vsldoi12 <3,4,5,6>, <0,0,4,1> + 4194594851U, // <6,0,0,5>: Cost 4 vsldoi4 <5,6,0,0>, <5,6,0,0> + 3517313713U, // <6,0,0,6>: Cost 4 vmrglw <4,5,6,0>, <6,5,0,6> + 3517313795U, // <6,0,0,7>: Cost 4 vmrglw <4,5,6,0>, <6,6,0,7> + 3376431177U, // <6,0,0,u>: Cost 3 vsldoi12 <3,4,5,6>, <0,0,u,1> + 4194599014U, // <6,0,1,0>: Cost 3 vsldoi4 <5,6,0,1>, LHS + 3392462950U, // <6,0,1,1>: Cost 3 vmrghw <6,1,7,1>, LHS + 3376431206U, // <6,0,1,2>: Cost 2 vsldoi12 <3,4,5,6>, LHS + 4194601474U, // <6,0,1,3>: Cost 3 vsldoi4 <5,6,0,1>, <3,4,5,6> + 4194602294U, // <6,0,1,4>: Cost 3 vsldoi4 <5,6,0,1>, RHS + 4194603044U, // <6,0,1,5>: Cost 3 vsldoi4 <5,6,0,1>, <5,6,0,1> + 4200575741U, // <6,0,1,6>: Cost 3 vsldoi4 <6,6,0,1>, <6,6,0,1> + 4194604026U, // <6,0,1,7>: Cost 4 vsldoi4 <5,6,0,1>, <7,0,1,2> + 3376431260U, // <6,0,1,u>: Cost 2 vsldoi12 <3,4,5,6>, LHS + 3393142784U, // <6,0,2,0>: Cost 3 vmrghw <6,2,7,3>, <0,0,0,0> + 2319401062U, // <6,0,2,1>: Cost 2 vmrghw <6,2,7,3>, LHS + 3356893370U, // <6,0,2,2>: Cost 4 vsldoi12 <0,2,1,6>, <0,2,2,6> + 3240912573U, // <6,0,2,3>: Cost 4 vsldoi8 <3,2,6,0>, <2,3,2,6> + 3393143122U, // <6,0,2,4>: Cost 3 vmrghw <6,2,7,3>, <0,4,1,5> + 3248875368U, // <6,0,2,5>: Cost 4 vsldoi8 <4,5,6,0>, <2,5,3,6> + 3393143281U, // <6,0,2,6>: Cost 3 vmrghw <6,2,7,3>, <0,6,1,2> + 4206556631U, // <6,0,2,7>: Cost 4 vsldoi4 <7,6,0,2>, <7,6,0,2> + 2319401629U, // <6,0,2,u>: Cost 2 vmrghw <6,2,7,3>, LHS + 3509370880U, // <6,0,3,0>: Cost 4 vmrglw <3,2,6,3>, <0,0,0,0> + 3376431360U, // <6,0,3,1>: Cost 3 vsldoi12 <3,4,5,6>, <0,3,1,4> + 3240913251U, // <6,0,3,2>: Cost 4 vsldoi8 <3,2,6,0>, <3,2,6,0> + 3376431378U, // <6,0,3,3>: Cost 4 vsldoi12 <3,4,5,6>, <0,3,3,4> + 3248876034U, // <6,0,3,4>: Cost 3 vsldoi8 <4,5,6,0>, <3,4,5,6> + 4194619430U, // <6,0,3,5>: Cost 4 vsldoi4 <5,6,0,3>, <5,6,0,3> + 3265464952U, // <6,0,3,6>: Cost 4 vsldoi8 <7,3,6,0>, <3,6,0,7> + 3264801498U, // <6,0,3,7>: Cost 4 vsldoi8 <7,2,6,0>, <3,7,2,6> + 3376431423U, // <6,0,3,u>: Cost 3 vsldoi12 <3,4,5,6>, <0,3,u,4> + 3517341696U, // <6,0,4,0>: Cost 4 vmrglw <4,5,6,4>, <0,0,0,0> + 3376431442U, // <6,0,4,1>: Cost 3 vsldoi12 <3,4,5,6>, <0,4,1,5> + 3236932665U, // <6,0,4,2>: Cost 4 vsldoi8 <2,5,6,0>, <4,2,5,6> + 4194626050U, // <6,0,4,3>: Cost 4 vsldoi4 <5,6,0,4>, <3,4,5,6> + 3376431469U, // <6,0,4,4>: Cost 4 vsldoi12 <3,4,5,6>, <0,4,4,5> + 3248876847U, // <6,0,4,5>: Cost 3 vsldoi8 <4,5,6,0>, <4,5,6,0> + 3394118129U, // <6,0,4,6>: Cost 4 vmrghw <6,4,2,5>, <0,6,1,2> + 3517344376U, // <6,0,4,7>: Cost 5 vmrglw <4,5,6,4>, <3,6,0,7> + 3376431505U, // <6,0,4,u>: Cost 3 vsldoi12 <3,4,5,6>, <0,4,u,5> + 3507396608U, // <6,0,5,0>: Cost 4 vmrglw <2,u,6,5>, <0,0,0,0> + 3395117158U, // <6,0,5,1>: Cost 3 vmrghw <6,5,7,1>, LHS + 3248877336U, // <6,0,5,2>: Cost 4 vsldoi8 <4,5,6,0>, <5,2,6,3> + 3253522278U, // <6,0,5,3>: Cost 4 vsldoi8 <5,3,6,0>, <5,3,6,0> + 3395109202U, // <6,0,5,4>: Cost 4 vmrghw <6,5,7,0>, <0,4,1,5> + 3248877582U, // <6,0,5,5>: Cost 4 vsldoi8 <4,5,6,0>, <5,5,6,6> + 3248877604U, // <6,0,5,6>: Cost 4 vsldoi8 <4,5,6,0>, <5,6,0,1> + 3513371256U, // <6,0,5,7>: Cost 4 vmrglw <3,u,6,5>, <3,6,0,7> + 3395117725U, // <6,0,5,u>: Cost 3 vmrghw <6,5,7,1>, LHS + 3395747840U, // <6,0,6,0>: Cost 3 vmrghw <6,6,6,6>, <0,0,0,0> + 2322006118U, // <6,0,6,1>: Cost 2 vmrghw <6,6,6,6>, LHS + 3248878011U, // <6,0,6,2>: Cost 4 vsldoi8 <4,5,6,0>, <6,2,0,3> + 3248878130U, // <6,0,6,3>: Cost 4 vsldoi8 <4,5,6,0>, <6,3,4,5> + 3395748178U, // <6,0,6,4>: Cost 3 vmrghw <6,6,6,6>, <0,4,1,5> + 3248878257U, // <6,0,6,5>: Cost 4 vsldoi8 <4,5,6,0>, <6,5,0,6> + 3261485874U, // <6,0,6,6>: Cost 3 vsldoi8 <6,6,6,0>, <6,6,6,0> + 3250869070U, // <6,0,6,7>: Cost 4 vsldoi8 <4,u,6,0>, <6,7,0,1> + 2322006685U, // <6,0,6,u>: Cost 2 vmrghw <6,6,6,6>, LHS + 2443624448U, // <6,0,7,0>: Cost 2 vmrglw RHS, <0,0,0,0> + 2443626150U, // <6,0,7,1>: Cost 2 vmrglw RHS, <2,3,0,1> + 4182705768U, // <6,0,7,2>: Cost 4 vsldoi4 <3,6,0,7>, <2,2,2,2> + 4182706808U, // <6,0,7,3>: Cost 3 vsldoi4 <3,6,0,7>, <3,6,0,7> + 4182707510U, // <6,0,7,4>: Cost 3 vsldoi4 <3,6,0,7>, RHS + 3517368788U, // <6,0,7,5>: Cost 3 vmrglw RHS, <3,4,0,5> + 4182708565U, // <6,0,7,6>: Cost 4 vsldoi4 <3,6,0,7>, <6,0,7,0> + 3517368952U, // <6,0,7,7>: Cost 3 vmrglw RHS, <3,6,0,7> + 2443626157U, // <6,0,7,u>: Cost 2 vmrglw RHS, <2,3,0,u> + 2443632640U, // <6,0,u,0>: Cost 2 vmrglw RHS, <0,0,0,0> + 2443634342U, // <6,0,u,1>: Cost 2 vmrglw RHS, <2,3,0,1> + 3376431773U, // <6,0,u,2>: Cost 2 vsldoi12 <3,4,5,6>, LHS + 4182715001U, // <6,0,u,3>: Cost 3 vsldoi4 <3,6,0,u>, <3,6,0,u> + 4182715702U, // <6,0,u,4>: Cost 3 vsldoi4 <3,6,0,u>, RHS + 3248879770U, // <6,0,u,5>: Cost 3 vsldoi8 <4,5,6,0>, RHS + 4200633092U, // <6,0,u,6>: Cost 3 vsldoi4 <6,6,0,u>, <6,6,0,u> + 3517377144U, // <6,0,u,7>: Cost 3 vmrglw RHS, <3,6,0,7> + 3376431827U, // <6,0,u,u>: Cost 2 vsldoi12 <3,4,5,6>, LHS + 3238928384U, // <6,1,0,0>: Cost 4 vsldoi8 <2,u,6,1>, <0,0,0,0> + 3238928486U, // <6,1,0,1>: Cost 3 vsldoi8 <2,u,6,1>, LHS + 3507361491U, // <6,1,0,2>: Cost 4 vmrglw <2,u,6,0>, + 4164807170U, // <6,1,0,3>: Cost 4 vsldoi4 <0,6,1,0>, <3,4,5,6> + 3238928722U, // <6,1,0,4>: Cost 4 vsldoi8 <2,u,6,1>, <0,4,1,5> + 3517309266U, // <6,1,0,5>: Cost 4 vmrglw <4,5,6,0>, <0,4,1,5> + 3502710961U, // <6,1,0,6>: Cost 4 vmrglw <2,1,6,0>, <0,2,1,6> + 3496740047U, // <6,1,0,7>: Cost 5 vmrglw <1,1,6,0>, <1,6,1,7> + 3238929053U, // <6,1,0,u>: Cost 3 vsldoi8 <2,u,6,1>, LHS + 3364487979U, // <6,1,1,0>: Cost 4 vsldoi12 <1,4,5,6>, <1,1,0,1> + 3376431924U, // <6,1,1,1>: Cost 3 vsldoi12 <3,4,5,6>, <1,1,1,1> + 3362276162U, // <6,1,1,2>: Cost 4 vsldoi12 <1,1,2,6>, <1,1,2,6> + 3507368388U, // <6,1,1,3>: Cost 4 vmrglw <2,u,6,1>, <6,2,1,3> + 3364488019U, // <6,1,1,4>: Cost 4 vsldoi12 <1,4,5,6>, <1,1,4,5> + 3507364178U, // <6,1,1,5>: Cost 4 vmrglw <2,u,6,1>, <0,4,1,5> + 3356894054U, // <6,1,1,6>: Cost 4 vsldoi12 <0,2,1,6>, <1,1,6,6> + 3496748239U, // <6,1,1,7>: Cost 4 vmrglw <1,1,6,1>, <1,6,1,7> + 3376431924U, // <6,1,1,u>: Cost 3 vsldoi12 <3,4,5,6>, <1,1,1,1> + 4212596838U, // <6,1,2,0>: Cost 3 vsldoi4 , LHS + 3393143604U, // <6,1,2,1>: Cost 3 vmrghw <6,2,7,3>, <1,1,1,1> + 3393143702U, // <6,1,2,2>: Cost 3 vmrghw <6,2,7,3>, <1,2,3,0> + 3376432022U, // <6,1,2,3>: Cost 3 vsldoi12 <3,4,5,6>, <1,2,3,0> + 4212600118U, // <6,1,2,4>: Cost 3 vsldoi4 , RHS + 3376432043U, // <6,1,2,5>: Cost 4 vsldoi12 <3,4,5,6>, <1,2,5,3> + 3238930362U, // <6,1,2,6>: Cost 3 vsldoi8 <2,u,6,1>, <2,6,3,7> + 3400319930U, // <6,1,2,7>: Cost 4 vsldoi12 <7,4,5,6>, <1,2,7,0> + 3238930545U, // <6,1,2,u>: Cost 3 vsldoi8 <2,u,6,1>, <2,u,6,1> + 3238930582U, // <6,1,3,0>: Cost 4 vsldoi8 <2,u,6,1>, <3,0,1,2> + 3240257811U, // <6,1,3,1>: Cost 4 vsldoi8 <3,1,6,1>, <3,1,6,1> + 3238930790U, // <6,1,3,2>: Cost 4 vsldoi8 <2,u,6,1>, <3,2,6,3> + 3238930844U, // <6,1,3,3>: Cost 4 vsldoi8 <2,u,6,1>, <3,3,3,3> + 3238930946U, // <6,1,3,4>: Cost 4 vsldoi8 <2,u,6,1>, <3,4,5,6> + 3509371218U, // <6,1,3,5>: Cost 4 vmrglw <3,2,6,3>, <0,4,1,5> + 3356894217U, // <6,1,3,6>: Cost 4 vsldoi12 <0,2,1,6>, <1,3,6,7> + 3238931139U, // <6,1,3,7>: Cost 4 vsldoi8 <2,u,6,1>, <3,7,0,1> + 3238931230U, // <6,1,3,u>: Cost 4 vsldoi8 <2,u,6,1>, <3,u,1,2> + 3376432158U, // <6,1,4,0>: Cost 4 vsldoi12 <3,4,5,6>, <1,4,0,1> + 3376432171U, // <6,1,4,1>: Cost 4 vsldoi12 <3,4,5,6>, <1,4,1,5> + 3376432180U, // <6,1,4,2>: Cost 4 vsldoi12 <3,4,5,6>, <1,4,2,5> + 3376432188U, // <6,1,4,3>: Cost 4 vsldoi12 <3,4,5,6>, <1,4,3,4> + 3376432198U, // <6,1,4,4>: Cost 4 vsldoi12 <3,4,5,6>, <1,4,4,5> + 3364488272U, // <6,1,4,5>: Cost 3 vsldoi12 <1,4,5,6>, <1,4,5,6> + 3502743729U, // <6,1,4,6>: Cost 4 vmrglw <2,1,6,4>, <0,2,1,6> + 3400320096U, // <6,1,4,7>: Cost 4 vsldoi12 <7,4,5,6>, <1,4,7,4> + 3364709483U, // <6,1,4,u>: Cost 3 vsldoi12 <1,4,u,6>, <1,4,u,6> + 3251539572U, // <6,1,5,0>: Cost 3 vsldoi8 <5,0,6,1>, <5,0,6,1> + 3364856957U, // <6,1,5,1>: Cost 4 vsldoi12 <1,5,1,6>, <1,5,1,6> + 3364930694U, // <6,1,5,2>: Cost 4 vsldoi12 <1,5,2,6>, <1,5,2,6> + 3376432269U, // <6,1,5,3>: Cost 4 vsldoi12 <3,4,5,6>, <1,5,3,4> + 3365078168U, // <6,1,5,4>: Cost 4 vsldoi12 <1,5,4,6>, <1,5,4,6> + 3365151905U, // <6,1,5,5>: Cost 4 vsldoi12 <1,5,5,6>, <1,5,5,6> + 3256848482U, // <6,1,5,6>: Cost 3 vsldoi8 <5,u,6,1>, <5,6,7,0> + 3501425871U, // <6,1,5,7>: Cost 4 vmrglw <1,u,6,5>, <1,6,1,7> + 3256848636U, // <6,1,5,u>: Cost 3 vsldoi8 <5,u,6,1>, <5,u,6,1> + 4212629606U, // <6,1,6,0>: Cost 3 vsldoi4 , LHS + 3395748660U, // <6,1,6,1>: Cost 3 vmrghw <6,6,6,6>, <1,1,1,1> + 3395748758U, // <6,1,6,2>: Cost 3 vmrghw <6,6,6,6>, <1,2,3,0> + 3238933017U, // <6,1,6,3>: Cost 4 vsldoi8 <2,u,6,1>, <6,3,1,7> + 4212632886U, // <6,1,6,4>: Cost 3 vsldoi4 , RHS + 3529965906U, // <6,1,6,5>: Cost 3 vmrglw <6,6,6,6>, <0,4,1,5> + 3262821176U, // <6,1,6,6>: Cost 3 vsldoi8 <6,u,6,1>, <6,6,6,6> + 3256849230U, // <6,1,6,7>: Cost 4 vsldoi8 <5,u,6,1>, <6,7,0,1> + 3395749244U, // <6,1,6,u>: Cost 3 vmrghw <6,6,6,6>, <1,u,3,0> + 4170834022U, // <6,1,7,0>: Cost 3 vsldoi4 <1,6,1,7>, LHS + 2443624458U, // <6,1,7,1>: Cost 2 vmrglw RHS, <0,0,1,1> + 2443626646U, // <6,1,7,2>: Cost 2 vmrglw RHS, <3,0,1,2> + 3517366446U, // <6,1,7,3>: Cost 3 vmrglw RHS, <0,2,1,3> + 4170837302U, // <6,1,7,4>: Cost 3 vsldoi4 <1,6,1,7>, RHS + 2443624786U, // <6,1,7,5>: Cost 2 vmrglw RHS, <0,4,1,5> + 3517366449U, // <6,1,7,6>: Cost 3 vmrglw RHS, <0,2,1,6> + 3517366774U, // <6,1,7,7>: Cost 3 vmrglw RHS, <0,6,1,7> + 2443624465U, // <6,1,7,u>: Cost 2 vmrglw RHS, <0,0,1,u> + 4170842214U, // <6,1,u,0>: Cost 3 vsldoi4 <1,6,1,u>, LHS + 2443632650U, // <6,1,u,1>: Cost 2 vmrglw RHS, <0,0,1,1> + 2443634838U, // <6,1,u,2>: Cost 2 vmrglw RHS, <3,0,1,2> + 3376432508U, // <6,1,u,3>: Cost 3 vsldoi12 <3,4,5,6>, <1,u,3,0> + 4170845494U, // <6,1,u,4>: Cost 3 vsldoi4 <1,6,1,u>, RHS + 2443632978U, // <6,1,u,5>: Cost 2 vmrglw RHS, <0,4,1,5> + 3517374641U, // <6,1,u,6>: Cost 3 vmrglw RHS, <0,2,1,6> + 3517374966U, // <6,1,u,7>: Cost 3 vmrglw RHS, <0,6,1,7> + 2443632657U, // <6,1,u,u>: Cost 2 vmrglw RHS, <0,0,1,u> + 3391792589U, // <6,2,0,0>: Cost 4 vmrghw <6,0,7,0>, <2,0,3,0> + 3262160998U, // <6,2,0,1>: Cost 3 vsldoi8 <6,7,6,2>, LHS + 3234291889U, // <6,2,0,2>: Cost 4 vsldoi8 <2,1,6,2>, <0,2,1,6> + 3517309030U, // <6,2,0,3>: Cost 3 vmrglw <4,5,6,0>, LHS + 4200713526U, // <6,2,0,4>: Cost 4 vsldoi4 <6,6,2,0>, RHS + 3370976736U, // <6,2,0,5>: Cost 4 vsldoi12 <2,5,3,6>, <2,0,5,1> + 3372893673U, // <6,2,0,6>: Cost 4 vsldoi12 <2,u,2,6>, <2,0,6,1> + 4206687719U, // <6,2,0,7>: Cost 4 vsldoi4 <7,6,2,0>, <7,6,2,0> + 3517309035U, // <6,2,0,u>: Cost 3 vmrglw <4,5,6,0>, LHS + 3502058196U, // <6,2,1,0>: Cost 4 vmrglw <2,0,6,1>, <3,7,2,0> + 3392464415U, // <6,2,1,1>: Cost 4 vmrghw <6,1,7,1>, <2,1,3,1> + 3507365480U, // <6,2,1,2>: Cost 4 vmrglw <2,u,6,1>, <2,2,2,2> + 3507363942U, // <6,2,1,3>: Cost 3 vmrglw <2,u,6,1>, LHS + 4170861878U, // <6,2,1,4>: Cost 5 vsldoi4 <1,6,2,1>, RHS + 3230975142U, // <6,2,1,5>: Cost 4 vsldoi8 <1,5,6,2>, <1,5,6,2> + 3356894777U, // <6,2,1,6>: Cost 4 vsldoi12 <0,2,1,6>, <2,1,6,0> + 3507365566U, // <6,2,1,7>: Cost 5 vmrglw <2,u,6,1>, <2,3,2,7> + 3507363947U, // <6,2,1,u>: Cost 3 vmrglw <2,u,6,1>, LHS + 4200726630U, // <6,2,2,0>: Cost 3 vsldoi4 <6,6,2,2>, LHS + 3234293307U, // <6,2,2,1>: Cost 4 vsldoi8 <2,1,6,2>, <2,1,6,2> + 3370460776U, // <6,2,2,2>: Cost 3 vsldoi12 <2,4,5,6>, <2,2,2,2> + 3376432754U, // <6,2,2,3>: Cost 3 vsldoi12 <3,4,5,6>, <2,2,3,3> + 4200729910U, // <6,2,2,4>: Cost 3 vsldoi4 <6,6,2,2>, RHS + 3253536616U, // <6,2,2,5>: Cost 4 vsldoi8 <5,3,6,2>, <2,5,3,6> + 3393144762U, // <6,2,2,6>: Cost 3 vmrghw <6,2,7,3>, <2,6,3,7> + 3393144836U, // <6,2,2,7>: Cost 3 vmrghw <6,2,7,3>, <2,7,3,0> + 3376432799U, // <6,2,2,u>: Cost 3 vsldoi12 <3,4,5,6>, <2,2,u,3> + 3376432806U, // <6,2,3,0>: Cost 3 vsldoi12 <3,4,5,6>, <2,3,0,1> + 3364488882U, // <6,2,3,1>: Cost 4 vsldoi12 <1,4,5,6>, <2,3,1,4> + 3369576125U, // <6,2,3,2>: Cost 3 vsldoi12 <2,3,2,6>, <2,3,2,6> + 3509370982U, // <6,2,3,3>: Cost 3 vmrglw <3,2,6,3>, LHS + 3376432846U, // <6,2,3,4>: Cost 3 vsldoi12 <3,4,5,6>, <2,3,4,5> + 3369797336U, // <6,2,3,5>: Cost 3 vsldoi12 <2,3,5,6>, <2,3,5,6> + 3393783738U, // <6,2,3,6>: Cost 3 vmrghw <6,3,7,0>, <2,6,3,7> + 3400320744U, // <6,2,3,7>: Cost 3 vsldoi12 <7,4,5,6>, <2,3,7,4> + 3370018547U, // <6,2,3,u>: Cost 3 vsldoi12 <2,3,u,6>, <2,3,u,6> + 4194771046U, // <6,2,4,0>: Cost 4 vsldoi4 <5,6,2,4>, LHS + 3502747945U, // <6,2,4,1>: Cost 5 vmrglw <2,1,6,4>, <6,0,2,1> + 3370460941U, // <6,2,4,2>: Cost 4 vsldoi12 <2,4,5,6>, <2,4,2,5> + 3517341798U, // <6,2,4,3>: Cost 3 vmrglw <4,5,6,4>, LHS + 4194774326U, // <6,2,4,4>: Cost 4 vsldoi4 <5,6,2,4>, RHS + 3370460969U, // <6,2,4,5>: Cost 3 vsldoi12 <2,4,5,6>, <2,4,5,6> + 3372894001U, // <6,2,4,6>: Cost 4 vsldoi12 <2,u,2,6>, <2,4,6,5> + 3394119684U, // <6,2,4,7>: Cost 4 vmrghw <6,4,2,5>, <2,7,3,0> + 3370682180U, // <6,2,4,u>: Cost 3 vsldoi12 <2,4,u,6>, <2,4,u,6> + 4182835302U, // <6,2,5,0>: Cost 4 vsldoi4 <3,6,2,5>, LHS + 3252211398U, // <6,2,5,1>: Cost 4 vsldoi8 <5,1,6,2>, <5,1,6,2> + 3370903391U, // <6,2,5,2>: Cost 4 vsldoi12 <2,5,2,6>, <2,5,2,6> + 3370977128U, // <6,2,5,3>: Cost 3 vsldoi12 <2,5,3,6>, <2,5,3,6> + 4182838582U, // <6,2,5,4>: Cost 4 vsldoi4 <3,6,2,5>, RHS + 3254865930U, // <6,2,5,5>: Cost 4 vsldoi8 <5,5,6,2>, <5,5,6,2> + 3507398333U, // <6,2,5,6>: Cost 4 vmrglw <2,u,6,5>, <2,3,2,6> + 3256193196U, // <6,2,5,7>: Cost 4 vsldoi8 <5,7,6,2>, <5,7,6,2> + 3371345813U, // <6,2,5,u>: Cost 3 vsldoi12 <2,5,u,6>, <2,5,u,6> + 4170899558U, // <6,2,6,0>: Cost 4 vsldoi4 <1,6,2,6>, LHS + 4170900695U, // <6,2,6,1>: Cost 4 vsldoi4 <1,6,2,6>, <1,6,2,6> + 3395749480U, // <6,2,6,2>: Cost 3 vmrghw <6,6,6,6>, <2,2,2,2> + 2456223846U, // <6,2,6,3>: Cost 2 vmrglw <6,6,6,6>, LHS + 4170902838U, // <6,2,6,4>: Cost 4 vsldoi4 <1,6,2,6>, RHS + 4194791483U, // <6,2,6,5>: Cost 4 vsldoi4 <5,6,2,6>, <5,6,2,6> + 3395749818U, // <6,2,6,6>: Cost 3 vmrghw <6,6,6,6>, <2,6,3,7> + 3262165893U, // <6,2,6,7>: Cost 3 vsldoi8 <6,7,6,2>, <6,7,6,2> + 2456223851U, // <6,2,6,u>: Cost 2 vmrglw <6,6,6,6>, LHS + 4176879718U, // <6,2,7,0>: Cost 3 vsldoi4 <2,6,2,7>, LHS + 3517367020U, // <6,2,7,1>: Cost 3 vmrglw RHS, <1,0,2,1> + 2443626088U, // <6,2,7,2>: Cost 2 vmrglw RHS, <2,2,2,2> + 1369882726U, // <6,2,7,3>: Cost 1 vmrglw RHS, LHS + 4176882998U, // <6,2,7,4>: Cost 3 vsldoi4 <2,6,2,7>, RHS + 3517367348U, // <6,2,7,5>: Cost 3 vmrglw RHS, <1,4,2,5> + 3517367997U, // <6,2,7,6>: Cost 3 vmrglw RHS, <2,3,2,6> + 3517367512U, // <6,2,7,7>: Cost 3 vmrglw RHS, <1,6,2,7> + 1369882731U, // <6,2,7,u>: Cost 1 vmrglw RHS, LHS + 4176887910U, // <6,2,u,0>: Cost 3 vsldoi4 <2,6,2,u>, LHS + 3517375212U, // <6,2,u,1>: Cost 3 vmrglw RHS, <1,0,2,1> + 2443634280U, // <6,2,u,2>: Cost 2 vmrglw RHS, <2,2,2,2> + 1369890918U, // <6,2,u,3>: Cost 1 vmrglw RHS, LHS + 4176891190U, // <6,2,u,4>: Cost 3 vsldoi4 <2,6,2,u>, RHS + 3373115501U, // <6,2,u,5>: Cost 3 vsldoi12 <2,u,5,6>, <2,u,5,6> + 3517376189U, // <6,2,u,6>: Cost 3 vmrglw RHS, <2,3,2,6> + 3517375704U, // <6,2,u,7>: Cost 3 vmrglw RHS, <1,6,2,7> + 1369890923U, // <6,2,u,u>: Cost 1 vmrglw RHS, LHS + 3240935424U, // <6,3,0,0>: Cost 4 vsldoi8 <3,2,6,3>, <0,0,0,0> + 3240935526U, // <6,3,0,1>: Cost 3 vsldoi8 <3,2,6,3>, LHS + 3228991665U, // <6,3,0,2>: Cost 4 vsldoi8 <1,2,6,3>, <0,2,1,6> + 3373631660U, // <6,3,0,3>: Cost 4 vsldoi12 <3,0,3,6>, <3,0,3,6> + 3391367682U, // <6,3,0,4>: Cost 3 vmrghw <6,0,1,2>, <3,4,5,6> + 4194816062U, // <6,3,0,5>: Cost 4 vsldoi4 <5,6,3,0>, <5,6,3,0> + 3517310824U, // <6,3,0,6>: Cost 4 vmrglw <4,5,6,0>, <2,5,3,6> + 3502712762U, // <6,3,0,7>: Cost 4 vmrglw <2,1,6,0>, <2,6,3,7> + 3240936093U, // <6,3,0,u>: Cost 3 vsldoi8 <3,2,6,3>, LHS + 3392473238U, // <6,3,1,0>: Cost 3 vmrghw <6,1,7,2>, <3,0,1,2> + 3240936244U, // <6,3,1,1>: Cost 4 vsldoi8 <3,2,6,3>, <1,1,1,1> + 3228992436U, // <6,3,1,2>: Cost 4 vsldoi8 <1,2,6,3>, <1,2,6,3> + 3507365490U, // <6,3,1,3>: Cost 4 vmrglw <2,u,6,1>, <2,2,3,3> + 3364489477U, // <6,3,1,4>: Cost 4 vsldoi12 <1,4,5,6>, <3,1,4,5> + 3507365411U, // <6,3,1,5>: Cost 5 vmrglw <2,u,6,1>, <2,1,3,5> + 3525945273U, // <6,3,1,6>: Cost 4 vmrglw <6,0,6,1>, <2,6,3,6> + 3507365818U, // <6,3,1,7>: Cost 3 vmrglw <2,u,6,1>, <2,6,3,7> + 3392473238U, // <6,3,1,u>: Cost 3 vmrghw <6,1,7,2>, <3,0,1,2> + 3393144982U, // <6,3,2,0>: Cost 3 vmrghw <6,2,7,3>, <3,0,1,2> + 3393145062U, // <6,3,2,1>: Cost 4 vmrghw <6,2,7,3>, <3,1,1,1> + 3234965133U, // <6,3,2,2>: Cost 4 vsldoi8 <2,2,6,3>, <2,2,6,3> + 3393145244U, // <6,3,2,3>: Cost 3 vmrghw <6,2,7,3>, <3,3,3,3> + 3393145346U, // <6,3,2,4>: Cost 3 vmrghw <6,2,7,3>, <3,4,5,6> + 3370977629U, // <6,3,2,5>: Cost 4 vsldoi12 <2,5,3,6>, <3,2,5,3> + 3240937402U, // <6,3,2,6>: Cost 3 vsldoi8 <3,2,6,3>, <2,6,3,7> + 3502729146U, // <6,3,2,7>: Cost 4 vmrglw <2,1,6,2>, <2,6,3,7> + 3393145630U, // <6,3,2,u>: Cost 3 vmrghw <6,2,7,3>, <3,u,1,2> + 4176920678U, // <6,3,3,0>: Cost 4 vsldoi4 <2,6,3,3>, LHS + 3228993780U, // <6,3,3,1>: Cost 5 vsldoi8 <1,2,6,3>, <3,1,2,6> + 3240937830U, // <6,3,3,2>: Cost 3 vsldoi8 <3,2,6,3>, <3,2,6,3> + 3376433564U, // <6,3,3,3>: Cost 3 vsldoi12 <3,4,5,6>, <3,3,3,3> + 3376433575U, // <6,3,3,4>: Cost 3 vsldoi12 <3,4,5,6>, <3,3,4,5> + 3252881976U, // <6,3,3,5>: Cost 4 vsldoi8 <5,2,6,3>, <3,5,2,6> + 3370977722U, // <6,3,3,6>: Cost 4 vsldoi12 <2,5,3,6>, <3,3,6,6> + 3509372858U, // <6,3,3,7>: Cost 3 vmrglw <3,2,6,3>, <2,6,3,7> + 3379087819U, // <6,3,3,u>: Cost 3 vsldoi12 <3,u,5,6>, <3,3,u,5> + 4194844774U, // <6,3,4,0>: Cost 3 vsldoi4 <5,6,3,4>, LHS + 3376433626U, // <6,3,4,1>: Cost 4 vsldoi12 <3,4,5,6>, <3,4,1,2> + 3376212455U, // <6,3,4,2>: Cost 4 vsldoi12 <3,4,2,6>, <3,4,2,6> + 4194847234U, // <6,3,4,3>: Cost 3 vsldoi4 <5,6,3,4>, <3,4,5,6> + 4194848054U, // <6,3,4,4>: Cost 3 vsldoi4 <5,6,3,4>, RHS + 3376433666U, // <6,3,4,5>: Cost 2 vsldoi12 <3,4,5,6>, <3,4,5,6> + 3517343592U, // <6,3,4,6>: Cost 4 vmrglw <4,5,6,4>, <2,5,3,6> + 3502745530U, // <6,3,4,7>: Cost 4 vmrglw <2,1,6,4>, <2,6,3,7> + 3376654877U, // <6,3,4,u>: Cost 2 vsldoi12 <3,4,u,6>, <3,4,u,6> + 3507397526U, // <6,3,5,0>: Cost 4 vmrglw <2,u,6,5>, <1,2,3,0> + 4176938227U, // <6,3,5,1>: Cost 5 vsldoi4 <2,6,3,5>, <1,6,5,7> + 3252883224U, // <6,3,5,2>: Cost 3 vsldoi8 <5,2,6,3>, <5,2,6,3> + 3507398258U, // <6,3,5,3>: Cost 4 vmrglw <2,u,6,5>, <2,2,3,3> + 3395160578U, // <6,3,5,4>: Cost 3 vmrghw <6,5,7,6>, <3,4,5,6> + 3248902158U, // <6,3,5,5>: Cost 4 vsldoi8 <4,5,6,3>, <5,5,6,6> + 3370977884U, // <6,3,5,6>: Cost 4 vsldoi12 <2,5,3,6>, <3,5,6,6> + 3507398586U, // <6,3,5,7>: Cost 3 vmrglw <2,u,6,5>, <2,6,3,7> + 3256865022U, // <6,3,5,u>: Cost 3 vsldoi8 <5,u,6,3>, <5,u,6,3> + 3395750038U, // <6,3,6,0>: Cost 3 vmrghw <6,6,6,6>, <3,0,1,2> + 3395750118U, // <6,3,6,1>: Cost 4 vmrghw <6,6,6,6>, <3,1,1,1> + 4176947129U, // <6,3,6,2>: Cost 3 vsldoi4 <2,6,3,6>, <2,6,3,6> + 3395750300U, // <6,3,6,3>: Cost 3 vmrghw <6,6,6,6>, <3,3,3,3> + 3395750402U, // <6,3,6,4>: Cost 3 vmrghw <6,6,6,6>, <3,4,5,6> + 3248902860U, // <6,3,6,5>: Cost 4 vsldoi8 <4,5,6,3>, <6,5,3,6> + 3262837560U, // <6,3,6,6>: Cost 3 vsldoi8 <6,u,6,3>, <6,6,6,6> + 3529967546U, // <6,3,6,7>: Cost 3 vmrglw <6,6,6,6>, <2,6,3,7> + 3395750686U, // <6,3,6,u>: Cost 3 vmrghw <6,6,6,6>, <3,u,1,2> + 3103211622U, // <6,3,7,0>: Cost 2 vsldoi4 <2,6,3,7>, LHS + 4176954164U, // <6,3,7,1>: Cost 3 vsldoi4 <2,6,3,7>, <1,1,1,1> + 3103213498U, // <6,3,7,2>: Cost 2 vsldoi4 <2,6,3,7>, <2,6,3,7> + 2443626098U, // <6,3,7,3>: Cost 2 vmrglw RHS, <2,2,3,3> + 3103214902U, // <6,3,7,4>: Cost 2 vsldoi4 <2,6,3,7>, RHS + 3517367843U, // <6,3,7,5>: Cost 3 vmrglw RHS, <2,1,3,5> + 4176958024U, // <6,3,7,6>: Cost 3 vsldoi4 <2,6,3,7>, <6,3,7,0> + 2443626426U, // <6,3,7,7>: Cost 2 vmrglw RHS, <2,6,3,7> + 3103217454U, // <6,3,7,u>: Cost 2 vsldoi4 <2,6,3,7>, LHS + 3103219814U, // <6,3,u,0>: Cost 2 vsldoi4 <2,6,3,u>, LHS + 4176962356U, // <6,3,u,1>: Cost 3 vsldoi4 <2,6,3,u>, <1,1,1,1> + 3103221691U, // <6,3,u,2>: Cost 2 vsldoi4 <2,6,3,u>, <2,6,3,u> + 2443634290U, // <6,3,u,3>: Cost 2 vmrglw RHS, <2,2,3,3> + 3103223094U, // <6,3,u,4>: Cost 2 vsldoi4 <2,6,3,u>, RHS + 3379088198U, // <6,3,u,5>: Cost 2 vsldoi12 <3,u,5,6>, <3,u,5,6> + 4176966225U, // <6,3,u,6>: Cost 3 vsldoi4 <2,6,3,u>, <6,3,u,0> + 2443634618U, // <6,3,u,7>: Cost 2 vmrglw RHS, <2,6,3,7> + 3103225646U, // <6,3,u,u>: Cost 2 vsldoi4 <2,6,3,u>, LHS + 3248906240U, // <6,4,0,0>: Cost 4 vsldoi8 <4,5,6,4>, <0,0,0,0> + 3248906342U, // <6,4,0,1>: Cost 3 vsldoi8 <4,5,6,4>, LHS + 3234308273U, // <6,4,0,2>: Cost 4 vsldoi8 <2,1,6,4>, <0,2,1,6> + 3376434048U, // <6,4,0,3>: Cost 4 vsldoi12 <3,4,5,6>, <4,0,3,1> + 3248906578U, // <6,4,0,4>: Cost 4 vsldoi8 <4,5,6,4>, <0,4,1,5> + 3391368502U, // <6,4,0,5>: Cost 3 vmrghw <6,0,1,2>, RHS + 3391368567U, // <6,4,0,6>: Cost 4 vmrghw <6,0,1,2>, <4,6,5,0> + 3517310186U, // <6,4,0,7>: Cost 5 vmrglw <4,5,6,0>, <1,6,4,7> + 3248906909U, // <6,4,0,u>: Cost 3 vsldoi8 <4,5,6,4>, LHS + 3392465810U, // <6,4,1,0>: Cost 4 vmrghw <6,1,7,1>, <4,0,5,1> + 3248907060U, // <6,4,1,1>: Cost 4 vsldoi8 <4,5,6,4>, <1,1,1,1> + 3376434122U, // <6,4,1,2>: Cost 4 vsldoi12 <3,4,5,6>, <4,1,2,3> + 3392474244U, // <6,4,1,3>: Cost 4 vmrghw <6,1,7,2>, <4,3,5,0> + 3382406107U, // <6,4,1,4>: Cost 4 vsldoi12 <4,4,5,6>, <4,1,4,2> + 3392466230U, // <6,4,1,5>: Cost 3 vmrghw <6,1,7,1>, RHS + 3392466296U, // <6,4,1,6>: Cost 4 vmrghw <6,1,7,1>, <4,6,5,1> + 3400322040U, // <6,4,1,7>: Cost 4 vsldoi12 <7,4,5,6>, <4,1,7,4> + 3392466473U, // <6,4,1,u>: Cost 3 vmrghw <6,1,7,1>, RHS + 3393145746U, // <6,4,2,0>: Cost 3 vmrghw <6,2,7,3>, <4,0,5,1> + 3234309693U, // <6,4,2,1>: Cost 4 vsldoi8 <2,1,6,4>, <2,1,6,4> + 3248907880U, // <6,4,2,2>: Cost 4 vsldoi8 <4,5,6,4>, <2,2,2,2> + 3240945341U, // <6,4,2,3>: Cost 4 vsldoi8 <3,2,6,4>, <2,3,2,6> + 3393146064U, // <6,4,2,4>: Cost 3 vmrghw <6,2,7,3>, <4,4,4,4> + 2319404342U, // <6,4,2,5>: Cost 2 vmrghw <6,2,7,3>, RHS + 3393146233U, // <6,4,2,6>: Cost 3 vmrghw <6,2,7,3>, <4,6,5,2> + 3393146312U, // <6,4,2,7>: Cost 4 vmrghw <6,2,7,3>, <4,7,5,0> + 2319404585U, // <6,4,2,u>: Cost 2 vmrghw <6,2,7,3>, RHS + 3248908438U, // <6,4,3,0>: Cost 4 vsldoi8 <4,5,6,4>, <3,0,1,2> + 3517336376U, // <6,4,3,1>: Cost 4 vmrglw <4,5,6,3>, <3,u,4,1> + 3240946023U, // <6,4,3,2>: Cost 4 vsldoi8 <3,2,6,4>, <3,2,6,4> + 3248908700U, // <6,4,3,3>: Cost 4 vsldoi8 <4,5,6,4>, <3,3,3,3> + 3248908802U, // <6,4,3,4>: Cost 3 vsldoi8 <4,5,6,4>, <3,4,5,6> + 3393604918U, // <6,4,3,5>: Cost 3 vmrghw <6,3,4,5>, RHS + 3247581852U, // <6,4,3,6>: Cost 4 vsldoi8 <4,3,6,4>, <3,6,4,7> + 3264834266U, // <6,4,3,7>: Cost 4 vsldoi8 <7,2,6,4>, <3,7,2,6> + 3393605161U, // <6,4,3,u>: Cost 3 vmrghw <6,3,4,5>, RHS + 3250899858U, // <6,4,4,0>: Cost 4 vsldoi8 <4,u,6,4>, <4,0,5,1> + 3517344568U, // <6,4,4,1>: Cost 4 vmrglw <4,5,6,4>, <3,u,4,1> + 3394489398U, // <6,4,4,2>: Cost 4 vmrghw <6,4,7,5>, <4,2,5,3> + 3247582353U, // <6,4,4,3>: Cost 4 vsldoi8 <4,3,6,4>, <4,3,6,4> + 3394481360U, // <6,4,4,4>: Cost 3 vmrghw <6,4,7,4>, <4,4,4,4> + 3382406363U, // <6,4,4,5>: Cost 3 vsldoi12 <4,4,5,6>, <4,4,5,6> + 3517346517U, // <6,4,4,6>: Cost 4 vmrglw <4,5,6,4>, <6,5,4,6> + 3516017308U, // <6,4,4,7>: Cost 4 vmrglw <4,3,6,4>, <3,6,4,7> + 3382627574U, // <6,4,4,u>: Cost 3 vsldoi12 <4,4,u,6>, <4,4,u,6> + 4194926694U, // <6,4,5,0>: Cost 3 vsldoi4 <5,6,4,5>, LHS + 4171039976U, // <6,4,5,1>: Cost 4 vsldoi4 <1,6,4,5>, <1,6,4,5> + 4171040698U, // <6,4,5,2>: Cost 4 vsldoi4 <1,6,4,5>, <2,6,3,7> + 4194929154U, // <6,4,5,3>: Cost 3 vsldoi4 <5,6,4,5>, <3,4,5,6> + 4194929974U, // <6,4,5,4>: Cost 3 vsldoi4 <5,6,4,5>, RHS + 4194930764U, // <6,4,5,5>: Cost 3 vsldoi4 <5,6,4,5>, <5,6,4,5> + 3376434486U, // <6,4,5,6>: Cost 2 vsldoi12 <3,4,5,6>, RHS + 4194931706U, // <6,4,5,7>: Cost 4 vsldoi4 <5,6,4,5>, <7,0,1,2> + 3376434504U, // <6,4,5,u>: Cost 2 vsldoi12 <3,4,5,6>, RHS + 3395750802U, // <6,4,6,0>: Cost 3 vmrghw <6,6,6,6>, <4,0,5,1> + 3523332920U, // <6,4,6,1>: Cost 4 vmrglw <5,5,6,6>, <3,u,4,1> + 3248910815U, // <6,4,6,2>: Cost 4 vsldoi8 <4,5,6,4>, <6,2,4,3> + 3248910898U, // <6,4,6,3>: Cost 4 vsldoi8 <4,5,6,4>, <6,3,4,5> + 3395751120U, // <6,4,6,4>: Cost 3 vmrghw <6,6,6,6>, <4,4,4,4> + 2322009398U, // <6,4,6,5>: Cost 2 vmrghw <6,6,6,6>, RHS + 3395751293U, // <6,4,6,6>: Cost 3 vmrghw <6,6,6,6>, <4,6,5,6> + 3250901838U, // <6,4,6,7>: Cost 4 vsldoi8 <4,u,6,4>, <6,7,0,1> + 2322009641U, // <6,4,6,u>: Cost 2 vmrghw <6,6,6,6>, RHS + 4182999142U, // <6,4,7,0>: Cost 3 vsldoi4 <3,6,4,7>, LHS + 4182999962U, // <6,4,7,1>: Cost 3 vsldoi4 <3,6,4,7>, <1,2,3,4> + 4177029059U, // <6,4,7,2>: Cost 4 vsldoi4 <2,6,4,7>, <2,6,4,7> + 4183001756U, // <6,4,7,3>: Cost 3 vsldoi4 <3,6,4,7>, <3,6,4,7> + 2445618384U, // <6,4,7,4>: Cost 2 vmrglw RHS, <4,4,4,4> + 2443626190U, // <6,4,7,5>: Cost 2 vmrglw RHS, <2,3,4,5> + 4183003801U, // <6,4,7,6>: Cost 4 vsldoi4 <3,6,4,7>, <6,4,7,0> + 3517368988U, // <6,4,7,7>: Cost 3 vmrglw RHS, <3,6,4,7> + 2443626193U, // <6,4,7,u>: Cost 2 vmrglw RHS, <2,3,4,u> + 4183007334U, // <6,4,u,0>: Cost 3 vsldoi4 <3,6,4,u>, LHS + 4183008154U, // <6,4,u,1>: Cost 3 vsldoi4 <3,6,4,u>, <1,2,3,4> + 4171065274U, // <6,4,u,2>: Cost 4 vsldoi4 <1,6,4,u>, <2,6,3,7> + 4183009949U, // <6,4,u,3>: Cost 3 vsldoi4 <3,6,4,u>, <3,6,4,u> + 2443635920U, // <6,4,u,4>: Cost 2 vmrglw RHS, <4,4,4,4> + 2443634382U, // <6,4,u,5>: Cost 2 vmrglw RHS, <2,3,4,5> + 3376434729U, // <6,4,u,6>: Cost 2 vsldoi12 <3,4,5,6>, RHS + 3517377180U, // <6,4,u,7>: Cost 3 vmrglw RHS, <3,6,4,7> + 3376434747U, // <6,4,u,u>: Cost 2 vsldoi12 <3,4,5,6>, RHS + 3238961152U, // <6,5,0,0>: Cost 4 vsldoi8 <2,u,6,5>, <0,0,0,0> + 3238961254U, // <6,5,0,1>: Cost 3 vsldoi8 <2,u,6,5>, LHS + 3238961329U, // <6,5,0,2>: Cost 4 vsldoi8 <2,u,6,5>, <0,2,1,6> + 4188989954U, // <6,5,0,3>: Cost 4 vsldoi4 <4,6,5,0>, <3,4,5,6> + 3238961490U, // <6,5,0,4>: Cost 4 vsldoi8 <2,u,6,5>, <0,4,1,5> + 3519302874U, // <6,5,0,5>: Cost 4 vmrglw <4,u,6,0>, <4,4,5,5> + 3517311490U, // <6,5,0,6>: Cost 3 vmrglw <4,5,6,0>, <3,4,5,6> + 3510676862U, // <6,5,0,7>: Cost 5 vmrglw <3,4,6,0>, <4,6,5,7> + 3238961821U, // <6,5,0,u>: Cost 3 vsldoi8 <2,u,6,5>, LHS + 4188995594U, // <6,5,1,0>: Cost 4 vsldoi4 <4,6,5,1>, <0,0,1,1> + 3238961972U, // <6,5,1,1>: Cost 4 vsldoi8 <2,u,6,5>, <1,1,1,1> + 3238962070U, // <6,5,1,2>: Cost 4 vsldoi8 <2,u,6,5>, <1,2,3,0> + 3376434861U, // <6,5,1,3>: Cost 4 vsldoi12 <3,4,5,6>, <5,1,3,4> + 4188999032U, // <6,5,1,4>: Cost 4 vsldoi4 <4,6,5,1>, <4,6,5,1> + 3386388161U, // <6,5,1,5>: Cost 4 vsldoi12 <5,1,5,6>, <5,1,5,6> + 3364490949U, // <6,5,1,6>: Cost 4 vsldoi12 <1,4,5,6>, <5,1,6,1> + 3400322769U, // <6,5,1,7>: Cost 4 vsldoi12 <7,4,5,6>, <5,1,7,4> + 3232990620U, // <6,5,1,u>: Cost 4 vsldoi8 <1,u,6,5>, <1,u,6,5> + 4189003878U, // <6,5,2,0>: Cost 3 vsldoi4 <4,6,5,2>, LHS + 4189004596U, // <6,5,2,1>: Cost 4 vsldoi4 <4,6,5,2>, <1,1,1,1> + 3238962792U, // <6,5,2,2>: Cost 4 vsldoi8 <2,u,6,5>, <2,2,2,2> + 3238962854U, // <6,5,2,3>: Cost 4 vsldoi8 <2,u,6,5>, <2,3,0,1> + 4189007225U, // <6,5,2,4>: Cost 3 vsldoi4 <4,6,5,2>, <4,6,5,2> + 3393146884U, // <6,5,2,5>: Cost 3 vmrghw <6,2,7,3>, <5,5,5,5> + 3238963130U, // <6,5,2,6>: Cost 3 vsldoi8 <2,u,6,5>, <2,6,3,7> + 4189008890U, // <6,5,2,7>: Cost 4 vsldoi4 <4,6,5,2>, <7,0,1,2> + 3238963317U, // <6,5,2,u>: Cost 3 vsldoi8 <2,u,6,5>, <2,u,6,5> + 3238963350U, // <6,5,3,0>: Cost 4 vsldoi8 <2,u,6,5>, <3,0,1,2> + 3240290583U, // <6,5,3,1>: Cost 4 vsldoi8 <3,1,6,5>, <3,1,6,5> + 3238963558U, // <6,5,3,2>: Cost 4 vsldoi8 <2,u,6,5>, <3,2,6,3> + 3238963612U, // <6,5,3,3>: Cost 4 vsldoi8 <2,u,6,5>, <3,3,3,3> + 3238963714U, // <6,5,3,4>: Cost 4 vsldoi8 <2,u,6,5>, <3,4,5,6> + 3519327450U, // <6,5,3,5>: Cost 4 vmrglw <4,u,6,3>, <4,4,5,5> + 3517336066U, // <6,5,3,6>: Cost 3 vmrglw <4,5,6,3>, <3,4,5,6> + 3238963907U, // <6,5,3,7>: Cost 4 vsldoi8 <2,u,6,5>, <3,7,0,1> + 3517336066U, // <6,5,3,u>: Cost 3 vmrglw <4,5,6,3>, <3,4,5,6> + 4189020262U, // <6,5,4,0>: Cost 4 vsldoi4 <4,6,5,4>, LHS + 3519335314U, // <6,5,4,1>: Cost 4 vmrglw <4,u,6,4>, <4,0,5,1> + 3394350872U, // <6,5,4,2>: Cost 4 vmrghw <6,4,5,6>, <5,2,6,3> + 4189022722U, // <6,5,4,3>: Cost 4 vsldoi4 <4,6,5,4>, <3,4,5,6> + 4189023611U, // <6,5,4,4>: Cost 4 vsldoi4 <4,6,5,4>, <4,6,5,4> + 3238964534U, // <6,5,4,5>: Cost 3 vsldoi8 <2,u,6,5>, RHS + 3517344258U, // <6,5,4,6>: Cost 3 vmrglw <4,5,6,4>, <3,4,5,6> + 3400323012U, // <6,5,4,7>: Cost 4 vsldoi12 <7,4,5,6>, <5,4,7,4> + 3238964777U, // <6,5,4,u>: Cost 3 vsldoi8 <2,u,6,5>, RHS + 4189028454U, // <6,5,5,0>: Cost 4 vsldoi4 <4,6,5,5>, LHS + 3252235977U, // <6,5,5,1>: Cost 4 vsldoi8 <5,1,6,5>, <5,1,6,5> + 3248918296U, // <6,5,5,2>: Cost 4 vsldoi8 <4,5,6,5>, <5,2,6,3> + 3507401678U, // <6,5,5,3>: Cost 4 vmrglw <2,u,6,5>, <6,u,5,3> + 3254226876U, // <6,5,5,4>: Cost 3 vsldoi8 <5,4,6,5>, <5,4,6,5> + 3395751940U, // <6,5,5,5>: Cost 3 vsldoi12 <6,6,6,6>, <5,5,5,5> + 3376435214U, // <6,5,5,6>: Cost 3 vsldoi12 <3,4,5,6>, <5,5,6,6> + 3507401277U, // <6,5,5,7>: Cost 4 vmrglw <2,u,6,5>, <6,3,5,7> + 3256881408U, // <6,5,5,u>: Cost 3 vsldoi8 <5,u,6,5>, <5,u,6,5> + 3376435236U, // <6,5,6,0>: Cost 3 vsldoi12 <3,4,5,6>, <5,6,0,1> + 3529968530U, // <6,5,6,1>: Cost 3 vmrglw <6,6,6,6>, <4,0,5,1> + 3370463287U, // <6,5,6,2>: Cost 4 vsldoi12 <2,4,5,6>, <5,6,2,2> + 3376435266U, // <6,5,6,3>: Cost 3 vsldoi12 <3,4,5,6>, <5,6,3,4> + 3376435276U, // <6,5,6,4>: Cost 3 vsldoi12 <3,4,5,6>, <5,6,4,5> + 3395751940U, // <6,5,6,5>: Cost 3 vmrghw <6,6,6,6>, <5,5,5,5> + 3376435296U, // <6,5,6,6>: Cost 3 vsldoi12 <3,4,5,6>, <5,6,6,7> + 3389853800U, // <6,5,6,7>: Cost 3 vsldoi12 <5,6,7,6>, <5,6,7,6> + 3376435308U, // <6,5,6,u>: Cost 3 vsldoi12 <3,4,5,6>, <5,6,u,1> + 4171128934U, // <6,5,7,0>: Cost 3 vsldoi4 <1,6,5,7>, LHS + 2443627410U, // <6,5,7,1>: Cost 2 vmrglw RHS, <4,0,5,1> + 3517368830U, // <6,5,7,2>: Cost 3 vmrglw RHS, <3,4,5,2> + 3517367211U, // <6,5,7,3>: Cost 3 vmrglw RHS, <1,2,5,3> + 4171132214U, // <6,5,7,4>: Cost 3 vsldoi4 <1,6,5,7>, RHS + 2443627738U, // <6,5,7,5>: Cost 2 vmrglw RHS, <4,4,5,5> + 2443627010U, // <6,5,7,6>: Cost 2 vmrglw RHS, <3,4,5,6> + 3517367539U, // <6,5,7,7>: Cost 3 vmrglw RHS, <1,6,5,7> + 2443627012U, // <6,5,7,u>: Cost 2 vmrglw RHS, <3,4,5,u> + 4171137126U, // <6,5,u,0>: Cost 3 vsldoi4 <1,6,5,u>, LHS + 2443635602U, // <6,5,u,1>: Cost 2 vmrglw RHS, <4,0,5,1> + 3517377022U, // <6,5,u,2>: Cost 3 vmrglw RHS, <3,4,5,2> + 3517375403U, // <6,5,u,3>: Cost 3 vmrglw RHS, <1,2,5,3> + 4171140406U, // <6,5,u,4>: Cost 3 vsldoi4 <1,6,5,u>, RHS + 2443635930U, // <6,5,u,5>: Cost 2 vmrglw RHS, <4,4,5,5> + 2443635202U, // <6,5,u,6>: Cost 2 vmrglw RHS, <3,4,5,6> + 3517375731U, // <6,5,u,7>: Cost 3 vmrglw RHS, <1,6,5,7> + 2443635204U, // <6,5,u,u>: Cost 2 vmrglw RHS, <3,4,5,u> + 3517312303U, // <6,6,0,0>: Cost 3 vmrglw <4,5,6,0>, <4,5,6,0> + 3261530214U, // <6,6,0,1>: Cost 2 vsldoi8 <6,6,6,6>, LHS + 3391435258U, // <6,6,0,2>: Cost 3 vmrghw <6,0,2,1>, <6,2,7,3> + 3376435506U, // <6,6,0,3>: Cost 4 vsldoi12 <3,4,5,6>, <6,0,3,1> + 3261530450U, // <6,6,0,4>: Cost 3 vsldoi8 <6,6,6,6>, <0,4,1,5> + 4195037273U, // <6,6,0,5>: Cost 4 vsldoi4 <5,6,6,0>, <5,6,6,0> + 3395752269U, // <6,6,0,6>: Cost 3 vsldoi12 <6,6,6,6>, <6,0,6,1> + 3517312310U, // <6,6,0,7>: Cost 3 vmrglw <4,5,6,0>, RHS + 3261530781U, // <6,6,0,u>: Cost 2 vsldoi8 <6,6,6,6>, LHS + 3392467232U, // <6,6,1,0>: Cost 4 vmrghw <6,1,7,1>, <6,0,1,1> + 3507366001U, // <6,6,1,1>: Cost 3 vmrglw <2,u,6,1>, <2,u,6,1> + 3261531030U, // <6,6,1,2>: Cost 3 vsldoi8 <6,6,6,6>, <1,2,3,0> + 3507366246U, // <6,6,1,3>: Cost 4 vmrglw <2,u,6,1>, <3,2,6,3> + 3364491664U, // <6,6,1,4>: Cost 4 vsldoi12 <1,4,5,6>, <6,1,4,5> + 3507365681U, // <6,6,1,5>: Cost 4 vmrglw <2,u,6,1>, <2,4,6,5> + 3531256632U, // <6,6,1,6>: Cost 3 vmrglw <6,u,6,1>, <6,6,6,6> + 3507367222U, // <6,6,1,7>: Cost 3 vmrglw <2,u,6,1>, RHS + 3507367223U, // <6,6,1,u>: Cost 3 vmrglw <2,u,6,1>, RHS + 3393147177U, // <6,6,2,0>: Cost 3 vmrghw <6,2,7,3>, <6,0,2,1> + 3393147258U, // <6,6,2,1>: Cost 4 vmrghw <6,2,7,3>, <6,1,2,1> + 2319405562U, // <6,6,2,2>: Cost 2 vmrghw <6,2,7,3>, <6,2,7,3> + 3261531814U, // <6,6,2,3>: Cost 3 vsldoi8 <6,6,6,6>, <2,3,0,1> + 3393147505U, // <6,6,2,4>: Cost 3 vmrghw <6,2,7,3>, <6,4,2,5> + 3370979816U, // <6,6,2,5>: Cost 4 vsldoi12 <2,5,3,6>, <6,2,5,3> + 3393147664U, // <6,6,2,6>: Cost 3 vmrghw <6,2,7,3>, <6,6,2,2> + 3389854202U, // <6,6,2,7>: Cost 3 vsldoi12 <5,6,7,6>, <6,2,7,3> + 2319405562U, // <6,6,2,u>: Cost 2 vmrghw <6,2,7,3>, <6,2,7,3> + 3261532310U, // <6,6,3,0>: Cost 3 vsldoi8 <6,6,6,6>, <3,0,1,2> + 3509372393U, // <6,6,3,1>: Cost 4 vmrglw <3,2,6,3>, <2,0,6,1> + 3509372637U, // <6,6,3,2>: Cost 4 vmrglw <3,2,6,3>, <2,3,6,2> + 3509373286U, // <6,6,3,3>: Cost 3 vmrglw <3,2,6,3>, <3,2,6,3> + 3376435762U, // <6,6,3,4>: Cost 3 vsldoi12 <3,4,5,6>, <6,3,4,5> + 3509372721U, // <6,6,3,5>: Cost 4 vmrglw <3,2,6,3>, <2,4,6,5> + 3531273016U, // <6,6,3,6>: Cost 3 vmrglw <6,u,6,3>, <6,6,6,6> + 3509374262U, // <6,6,3,7>: Cost 3 vmrglw <3,2,6,3>, RHS + 3509374263U, // <6,6,3,u>: Cost 3 vmrglw <3,2,6,3>, RHS + 3261533074U, // <6,6,4,0>: Cost 3 vsldoi8 <6,6,6,6>, <4,0,5,1> + 3394048423U, // <6,6,4,1>: Cost 4 vmrghw <6,4,1,5>, <6,1,7,1> + 3394122234U, // <6,6,4,2>: Cost 3 vmrghw <6,4,2,5>, <6,2,7,3> + 3517345074U, // <6,6,4,3>: Cost 4 vmrglw <4,5,6,4>, <4,5,6,3> + 3517345075U, // <6,6,4,4>: Cost 3 vmrglw <4,5,6,4>, <4,5,6,4> + 3261533494U, // <6,6,4,5>: Cost 2 vsldoi8 <6,6,6,6>, RHS + 3261533565U, // <6,6,4,6>: Cost 3 vsldoi8 <6,6,6,6>, <4,6,5,6> + 3517345078U, // <6,6,4,7>: Cost 3 vmrglw <4,5,6,4>, RHS + 3261533737U, // <6,6,4,u>: Cost 2 vsldoi8 <6,6,6,6>, RHS + 4195074150U, // <6,6,5,0>: Cost 4 vsldoi4 <5,6,6,5>, LHS + 3507398121U, // <6,6,5,1>: Cost 4 vmrglw <2,u,6,5>, <2,0,6,1> + 3254898456U, // <6,6,5,2>: Cost 4 vsldoi8 <5,5,6,6>, <5,2,6,3> + 3507399014U, // <6,6,5,3>: Cost 4 vmrglw <2,u,6,5>, <3,2,6,3> + 4195077430U, // <6,6,5,4>: Cost 4 vsldoi4 <5,6,6,5>, RHS + 3507398773U, // <6,6,5,5>: Cost 3 vmrglw <2,u,6,5>, <2,u,6,5> + 3261534306U, // <6,6,5,6>: Cost 3 vsldoi8 <6,6,6,6>, <5,6,7,0> + 3507399990U, // <6,6,5,7>: Cost 3 vmrglw <2,u,6,5>, RHS + 3507399991U, // <6,6,5,u>: Cost 3 vmrglw <2,u,6,5>, RHS + 3127312486U, // <6,6,6,0>: Cost 2 vsldoi4 <6,6,6,6>, LHS + 3529969997U, // <6,6,6,1>: Cost 3 vmrglw <6,6,6,6>, <6,0,6,1> + 3395424762U, // <6,6,6,2>: Cost 3 vmrghw <6,6,2,2>, <6,2,7,3> + 3529970161U, // <6,6,6,3>: Cost 3 vmrglw <6,6,6,6>, <6,2,6,3> + 3127315766U, // <6,6,6,4>: Cost 2 vsldoi4 <6,6,6,6>, RHS + 3529970325U, // <6,6,6,5>: Cost 3 vmrglw <6,6,6,6>, <6,4,6,5> + 1772539190U, // <6,6,6,6>: Cost 1 vspltisw2 RHS + 2456227126U, // <6,6,6,7>: Cost 2 vmrglw <6,6,6,6>, RHS + 1772539190U, // <6,6,6,u>: Cost 1 vspltisw2 RHS + 3517369647U, // <6,6,7,0>: Cost 3 vmrglw RHS, <4,5,6,0> + 3517367785U, // <6,6,7,1>: Cost 3 vmrglw RHS, <2,0,6,1> + 3519361925U, // <6,6,7,2>: Cost 3 vmrglw RHS, <6,7,6,2> + 3517368678U, // <6,6,7,3>: Cost 3 vmrglw RHS, <3,2,6,3> + 3517369651U, // <6,6,7,4>: Cost 3 vmrglw RHS, <4,5,6,4> + 3517368113U, // <6,6,7,5>: Cost 3 vmrglw RHS, <2,4,6,5> + 2445620024U, // <6,6,7,6>: Cost 2 vmrglw RHS, <6,6,6,6> + 1369886006U, // <6,6,7,7>: Cost 1 vmrglw RHS, RHS + 1369886007U, // <6,6,7,u>: Cost 1 vmrglw RHS, RHS + 3127312486U, // <6,6,u,0>: Cost 2 vsldoi4 <6,6,6,6>, LHS + 3261536046U, // <6,6,u,1>: Cost 2 vsldoi8 <6,6,6,6>, LHS + 2319405562U, // <6,6,u,2>: Cost 2 vmrghw <6,2,7,3>, <6,2,7,3> + 3517376870U, // <6,6,u,3>: Cost 3 vmrglw RHS, <3,2,6,3> + 3127315766U, // <6,6,u,4>: Cost 2 vsldoi4 <6,6,6,6>, RHS + 3261536410U, // <6,6,u,5>: Cost 2 vsldoi8 <6,6,6,6>, RHS + 1772539190U, // <6,6,u,6>: Cost 1 vspltisw2 RHS + 1369894198U, // <6,6,u,7>: Cost 1 vmrglw RHS, RHS + 1369894199U, // <6,6,u,u>: Cost 1 vmrglw RHS, RHS + 3248930816U, // <6,7,0,0>: Cost 2 vsldoi8 RHS, <0,0,0,0> + 1101447270U, // <6,7,0,1>: Cost 1 vsldoi8 RHS, LHS + 3248930989U, // <6,7,0,2>: Cost 3 vsldoi8 RHS, <0,2,1,2> + 3248931068U, // <6,7,0,3>: Cost 3 vsldoi8 RHS, <0,3,1,0> + 3248931154U, // <6,7,0,4>: Cost 2 vsldoi8 RHS, <0,4,1,5> + 3121369186U, // <6,7,0,5>: Cost 2 vsldoi4 <5,6,7,0>, <5,6,7,0> + 3248931318U, // <6,7,0,6>: Cost 3 vsldoi8 RHS, <0,6,1,7> + 4195111930U, // <6,7,0,7>: Cost 3 vsldoi4 <5,6,7,0>, <7,0,1,2> + 1101447837U, // <6,7,0,u>: Cost 1 vsldoi8 RHS, LHS + 3248931555U, // <6,7,1,0>: Cost 3 vsldoi8 RHS, <1,0,1,1> + 3248931636U, // <6,7,1,1>: Cost 2 vsldoi8 RHS, <1,1,1,1> + 3248931734U, // <6,7,1,2>: Cost 2 vsldoi8 RHS, <1,2,3,0> + 3229688841U, // <6,7,1,3>: Cost 4 vsldoi8 <1,3,6,7>, <1,3,6,7> + 3248931883U, // <6,7,1,4>: Cost 3 vsldoi8 RHS, <1,4,1,5> + 3248931951U, // <6,7,1,5>: Cost 3 vsldoi8 RHS, <1,5,0,1> + 3248932047U, // <6,7,1,6>: Cost 3 vsldoi8 RHS, <1,6,1,7> + 3507366340U, // <6,7,1,7>: Cost 4 vmrglw <2,u,6,1>, <3,3,7,7> + 3248932220U, // <6,7,1,u>: Cost 2 vsldoi8 RHS, <1,u,3,0> + 3248932285U, // <6,7,2,0>: Cost 3 vsldoi8 RHS, <2,0,1,2> + 3248932383U, // <6,7,2,1>: Cost 3 vsldoi8 RHS, <2,1,3,1> + 3248932456U, // <6,7,2,2>: Cost 2 vsldoi8 RHS, <2,2,2,2> + 3248932518U, // <6,7,2,3>: Cost 2 vsldoi8 RHS, <2,3,0,1> + 3248932621U, // <6,7,2,4>: Cost 3 vsldoi8 RHS, <2,4,2,5> + 3248932712U, // <6,7,2,5>: Cost 3 vsldoi8 RHS, <2,5,3,6> + 3248932794U, // <6,7,2,6>: Cost 2 vsldoi8 RHS, <2,6,3,7> + 3393148524U, // <6,7,2,7>: Cost 3 vmrghw <6,2,7,3>, <7,7,7,7> + 3248932923U, // <6,7,2,u>: Cost 2 vsldoi8 RHS, <2,u,0,1> + 3248933014U, // <6,7,3,0>: Cost 2 vsldoi8 RHS, <3,0,1,2> + 3248933094U, // <6,7,3,1>: Cost 3 vsldoi8 RHS, <3,1,1,1> + 3248933168U, // <6,7,3,2>: Cost 3 vsldoi8 RHS, <3,2,0,3> + 3248933276U, // <6,7,3,3>: Cost 2 vsldoi8 RHS, <3,3,3,3> + 3248933378U, // <6,7,3,4>: Cost 2 vsldoi8 RHS, <3,4,5,6> + 3248933458U, // <6,7,3,5>: Cost 3 vsldoi8 RHS, <3,5,5,5> + 3248933496U, // <6,7,3,6>: Cost 3 vsldoi8 RHS, <3,6,0,7> + 3248933571U, // <6,7,3,7>: Cost 3 vsldoi8 RHS, <3,7,0,1> + 3248933662U, // <6,7,3,u>: Cost 2 vsldoi8 RHS, <3,u,1,2> + 3248933778U, // <6,7,4,0>: Cost 2 vsldoi8 RHS, <4,0,5,1> + 3248933834U, // <6,7,4,1>: Cost 3 vsldoi8 RHS, <4,1,2,3> + 3248933941U, // <6,7,4,2>: Cost 3 vsldoi8 RHS, <4,2,5,2> + 3248934020U, // <6,7,4,3>: Cost 3 vsldoi8 RHS, <4,3,5,0> + 3248934096U, // <6,7,4,4>: Cost 2 vsldoi8 RHS, <4,4,4,4> + 1101450550U, // <6,7,4,5>: Cost 1 vsldoi8 RHS, RHS + 3248934269U, // <6,7,4,6>: Cost 3 vsldoi8 RHS, <4,6,5,6> + 3248934351U, // <6,7,4,7>: Cost 3 vsldoi8 RHS, <4,7,5,7> + 1101450793U, // <6,7,4,u>: Cost 1 vsldoi8 RHS, RHS + 3248934472U, // <6,7,5,0>: Cost 3 vsldoi8 RHS, <5,0,1,2> + 3250925199U, // <6,7,5,1>: Cost 3 vsldoi8 RHS, <5,1,0,1> + 3248934654U, // <6,7,5,2>: Cost 3 vsldoi8 RHS, <5,2,3,4> + 3507399023U, // <6,7,5,3>: Cost 4 vmrglw <2,u,6,5>, <3,2,7,3> + 3248934836U, // <6,7,5,4>: Cost 3 vsldoi8 RHS, <5,4,5,6> + 3248934916U, // <6,7,5,5>: Cost 2 vsldoi8 RHS, <5,5,5,5> + 3248935010U, // <6,7,5,6>: Cost 2 vsldoi8 RHS, <5,6,7,0> + 3507399108U, // <6,7,5,7>: Cost 4 vmrglw <2,u,6,5>, <3,3,7,7> + 3250925828U, // <6,7,5,u>: Cost 2 vsldoi8 RHS, <5,u,7,0> + 3248935201U, // <6,7,6,0>: Cost 3 vsldoi8 RHS, <6,0,1,2> + 3248935335U, // <6,7,6,1>: Cost 3 vsldoi8 RHS, <6,1,7,1> + 3248935418U, // <6,7,6,2>: Cost 2 vsldoi8 RHS, <6,2,7,3> + 3248935474U, // <6,7,6,3>: Cost 3 vsldoi8 RHS, <6,3,4,5> + 3248935565U, // <6,7,6,4>: Cost 3 vsldoi8 RHS, <6,4,5,6> + 3248935659U, // <6,7,6,5>: Cost 3 vsldoi8 RHS, <6,5,7,1> + 3248935736U, // <6,7,6,6>: Cost 2 vsldoi8 RHS, <6,6,6,6> + 3248935758U, // <6,7,6,7>: Cost 2 vsldoi8 RHS, <6,7,0,1> + 3248935904U, // <6,7,6,u>: Cost 2 vsldoi8 RHS, <6,u,7,3> + 2445619298U, // <6,7,7,0>: Cost 2 vmrglw RHS, <5,6,7,0> + 3517370710U, // <6,7,7,1>: Cost 3 vmrglw RHS, <6,0,7,1> + 4183222202U, // <6,7,7,2>: Cost 3 vsldoi4 <3,6,7,7>, <2,6,3,7> + 2443629050U, // <6,7,7,3>: Cost 2 vmrglw RHS, <6,2,7,3> + 2445619302U, // <6,7,7,4>: Cost 2 vmrglw RHS, <5,6,7,4> + 3517370795U, // <6,7,7,5>: Cost 3 vmrglw RHS, <6,1,7,5> + 3127399234U, // <6,7,7,6>: Cost 2 vsldoi4 <6,6,7,7>, <6,6,7,7> + 2443629378U, // <6,7,7,7>: Cost 2 vmrglw RHS, <6,6,7,7> + 2443629055U, // <6,7,7,u>: Cost 2 vmrglw RHS, <6,2,7,u> + 3248936659U, // <6,7,u,0>: Cost 2 vsldoi8 RHS, + 1101453102U, // <6,7,u,1>: Cost 1 vsldoi8 RHS, LHS + 3248936837U, // <6,7,u,2>: Cost 2 vsldoi8 RHS, + 3248936892U, // <6,7,u,3>: Cost 2 vsldoi8 RHS, + 3248937023U, // <6,7,u,4>: Cost 2 vsldoi8 RHS, + 1101453466U, // <6,7,u,5>: Cost 1 vsldoi8 RHS, RHS + 3248937168U, // <6,7,u,6>: Cost 2 vsldoi8 RHS, + 2443637570U, // <6,7,u,7>: Cost 2 vmrglw RHS, <6,6,7,7> + 1101453669U, // <6,7,u,u>: Cost 1 vsldoi8 RHS, LHS + 3248939008U, // <6,u,0,0>: Cost 2 vsldoi8 RHS, <0,0,0,0> + 1101455462U, // <6,u,0,1>: Cost 1 vsldoi8 RHS, LHS + 3248939181U, // <6,u,0,2>: Cost 3 vsldoi8 RHS, <0,2,1,2> + 3517309084U, // <6,u,0,3>: Cost 3 vmrglw <4,5,6,0>, LHS + 3248939346U, // <6,u,0,4>: Cost 2 vsldoi8 RHS, <0,4,1,5> + 3121442923U, // <6,u,0,5>: Cost 2 vsldoi4 <5,6,u,0>, <5,6,u,0> + 3248939510U, // <6,u,0,6>: Cost 3 vsldoi8 RHS, <0,6,1,7> + 3517312328U, // <6,u,0,7>: Cost 3 vmrglw <4,5,6,0>, RHS + 1101456029U, // <6,u,0,u>: Cost 1 vsldoi8 RHS, LHS + 3248939747U, // <6,u,1,0>: Cost 3 vsldoi8 RHS, <1,0,1,1> + 3248939828U, // <6,u,1,1>: Cost 2 vsldoi8 RHS, <1,1,1,1> + 3376437038U, // <6,u,1,2>: Cost 2 vsldoi12 <3,4,5,6>, LHS + 3507363996U, // <6,u,1,3>: Cost 3 vmrglw <2,u,6,1>, LHS + 3248940075U, // <6,u,1,4>: Cost 3 vsldoi8 RHS, <1,4,1,5> + 3248940143U, // <6,u,1,5>: Cost 3 vsldoi8 RHS, <1,5,0,1> + 3248940239U, // <6,u,1,6>: Cost 3 vsldoi8 RHS, <1,6,1,7> + 3507367240U, // <6,u,1,7>: Cost 3 vmrglw <2,u,6,1>, RHS + 3376437092U, // <6,u,1,u>: Cost 2 vsldoi12 <3,4,5,6>, LHS + 3248940477U, // <6,u,2,0>: Cost 3 vsldoi8 RHS, <2,0,1,2> + 2319406894U, // <6,u,2,1>: Cost 2 vmrghw <6,2,7,3>, LHS + 3248940648U, // <6,u,2,2>: Cost 2 vsldoi8 RHS, <2,2,2,2> + 3248940710U, // <6,u,2,3>: Cost 2 vsldoi8 RHS, <2,3,0,1> + 3248940813U, // <6,u,2,4>: Cost 3 vsldoi8 RHS, <2,4,2,5> + 2319407258U, // <6,u,2,5>: Cost 2 vmrghw <6,2,7,3>, RHS + 3248940986U, // <6,u,2,6>: Cost 2 vsldoi8 RHS, <2,6,3,7> + 3393149184U, // <6,u,2,7>: Cost 3 vmrghw <6,2,7,3>, + 3248941115U, // <6,u,2,u>: Cost 2 vsldoi8 RHS, <2,u,0,1> + 3248941206U, // <6,u,3,0>: Cost 2 vsldoi8 RHS, <3,0,1,2> + 3248941286U, // <6,u,3,1>: Cost 3 vsldoi8 RHS, <3,1,1,1> + 3240978795U, // <6,u,3,2>: Cost 3 vsldoi8 <3,2,6,u>, <3,2,6,u> + 3248941468U, // <6,u,3,3>: Cost 2 vsldoi8 RHS, <3,3,3,3> + 3248941570U, // <6,u,3,4>: Cost 2 vsldoi8 RHS, <3,4,5,6> + 3248941650U, // <6,u,3,5>: Cost 3 vsldoi8 RHS, <3,5,5,5> + 3248941688U, // <6,u,3,6>: Cost 3 vsldoi8 RHS, <3,6,0,7> + 3509374280U, // <6,u,3,7>: Cost 3 vmrglw <3,2,6,3>, RHS + 3248941854U, // <6,u,3,u>: Cost 2 vsldoi8 RHS, <3,u,1,2> + 3248941970U, // <6,u,4,0>: Cost 2 vsldoi8 RHS, <4,0,5,1> + 3248942026U, // <6,u,4,1>: Cost 3 vsldoi8 RHS, <4,1,2,3> + 3248942133U, // <6,u,4,2>: Cost 3 vsldoi8 RHS, <4,2,5,2> + 3517341852U, // <6,u,4,3>: Cost 3 vmrglw <4,5,6,4>, LHS + 3248942288U, // <6,u,4,4>: Cost 2 vsldoi8 RHS, <4,4,4,4> + 1101458743U, // <6,u,4,5>: Cost 1 vsldoi8 RHS, RHS + 3248942457U, // <6,u,4,6>: Cost 3 vsldoi8 RHS, <4,6,5,2> + 3517345096U, // <6,u,4,7>: Cost 3 vmrglw <4,5,6,4>, RHS + 1101458985U, // <6,u,4,u>: Cost 1 vsldoi8 RHS, RHS + 3248942664U, // <6,u,5,0>: Cost 3 vsldoi8 RHS, <5,0,1,2> + 3250933391U, // <6,u,5,1>: Cost 3 vsldoi8 RHS, <5,1,0,1> + 3248942846U, // <6,u,5,2>: Cost 3 vsldoi8 RHS, <5,2,3,4> + 3507396764U, // <6,u,5,3>: Cost 3 vmrglw <2,u,6,5>, LHS + 3248943028U, // <6,u,5,4>: Cost 3 vsldoi8 RHS, <5,4,5,6> + 3248943108U, // <6,u,5,5>: Cost 2 vsldoi8 RHS, <5,5,5,5> + 3376437402U, // <6,u,5,6>: Cost 2 vsldoi12 <3,4,5,6>, RHS + 3507400008U, // <6,u,5,7>: Cost 3 vmrglw <2,u,6,5>, RHS + 3376437420U, // <6,u,5,u>: Cost 2 vsldoi12 <3,4,5,6>, RHS + 3127312486U, // <6,u,6,0>: Cost 2 vsldoi4 <6,6,6,6>, LHS + 2322011950U, // <6,u,6,1>: Cost 2 vmrghw <6,6,6,6>, LHS + 3248943610U, // <6,u,6,2>: Cost 2 vsldoi8 RHS, <6,2,7,3> + 2456223900U, // <6,u,6,3>: Cost 2 vmrglw <6,6,6,6>, LHS + 3127315766U, // <6,u,6,4>: Cost 2 vsldoi4 <6,6,6,6>, RHS + 2322012314U, // <6,u,6,5>: Cost 2 vmrghw <6,6,6,6>, RHS + 1772539190U, // <6,u,6,6>: Cost 1 vspltisw2 RHS + 3248943950U, // <6,u,6,7>: Cost 2 vsldoi8 RHS, <6,7,0,1> + 1772539190U, // <6,u,6,u>: Cost 1 vspltisw2 RHS + 3103580262U, // <6,u,7,0>: Cost 2 vsldoi4 <2,6,u,7>, LHS + 2443624521U, // <6,u,7,1>: Cost 2 vmrglw RHS, <0,0,u,1> + 3103582183U, // <6,u,7,2>: Cost 2 vsldoi4 <2,6,u,7>, <2,6,u,7> + 1369882780U, // <6,u,7,3>: Cost 1 vmrglw RHS, LHS + 3103583542U, // <6,u,7,4>: Cost 2 vsldoi4 <2,6,u,7>, RHS + 2443624849U, // <6,u,7,5>: Cost 2 vmrglw RHS, <0,4,u,5> + 2443627037U, // <6,u,7,6>: Cost 2 vmrglw RHS, <3,4,u,6> + 1369886024U, // <6,u,7,7>: Cost 1 vmrglw RHS, RHS + 1369882785U, // <6,u,7,u>: Cost 1 vmrglw RHS, LHS + 3103588454U, // <6,u,u,0>: Cost 2 vsldoi4 <2,6,u,u>, LHS + 1101461294U, // <6,u,u,1>: Cost 1 vsldoi8 RHS, LHS + 3103590376U, // <6,u,u,2>: Cost 2 vsldoi4 <2,6,u,u>, <2,6,u,u> + 1369890972U, // <6,u,u,3>: Cost 1 vmrglw RHS, LHS + 3103591734U, // <6,u,u,4>: Cost 2 vsldoi4 <2,6,u,u>, RHS + 1101461658U, // <6,u,u,5>: Cost 1 vsldoi8 RHS, RHS + 1772539190U, // <6,u,u,6>: Cost 1 vspltisw2 RHS + 1369894216U, // <6,u,u,7>: Cost 1 vmrglw RHS, RHS + 1369890977U, // <6,u,u,u>: Cost 1 vmrglw RHS, LHS + 3383148544U, // <7,0,0,0>: Cost 2 vsldoi12 RHS, <0,0,0,0> + 3383148554U, // <7,0,0,1>: Cost 2 vsldoi12 RHS, <0,0,1,1> + 4183312314U, // <7,0,0,2>: Cost 4 vsldoi4 <3,7,0,0>, <2,6,3,7> + 3524023444U, // <7,0,0,3>: Cost 3 vmrglw <5,6,7,0>, <7,2,0,3> + 3383148581U, // <7,0,0,4>: Cost 3 vsldoi12 RHS, <0,0,4,1> + 4207202402U, // <7,0,0,5>: Cost 3 vsldoi4 <7,7,0,0>, <5,6,7,0> + 4201231181U, // <7,0,0,6>: Cost 3 vsldoi4 <6,7,0,0>, <6,7,0,0> + 3524023772U, // <7,0,0,7>: Cost 3 vmrglw <5,6,7,0>, <7,6,0,7> + 3383148617U, // <7,0,0,u>: Cost 2 vsldoi12 RHS, <0,0,u,1> + 3127492710U, // <7,0,1,0>: Cost 2 vsldoi4 <6,7,0,1>, LHS + 3383148635U, // <7,0,1,1>: Cost 3 vsldoi12 RHS, <0,1,1,1> + 1235664998U, // <7,0,1,2>: Cost 1 vsldoi12 RHS, LHS + 4183321283U, // <7,0,1,3>: Cost 3 vsldoi4 <3,7,0,1>, <3,7,0,1> + 3127495990U, // <7,0,1,4>: Cost 2 vsldoi4 <6,7,0,1>, RHS + 4201238532U, // <7,0,1,5>: Cost 3 vsldoi4 <6,7,0,1>, <5,5,5,5> + 3127497550U, // <7,0,1,6>: Cost 2 vsldoi4 <6,7,0,1>, <6,7,0,1> + 4201239544U, // <7,0,1,7>: Cost 3 vsldoi4 <6,7,0,1>, <7,0,1,0> + 1235665052U, // <7,0,1,u>: Cost 1 vsldoi12 RHS, LHS + 3383148709U, // <7,0,2,0>: Cost 3 vsldoi12 RHS, <0,2,0,3> + 3371647153U, // <7,0,2,1>: Cost 3 vsldoi12 <2,6,3,7>, <0,2,1,6> + 3255584360U, // <7,0,2,2>: Cost 3 vsldoi8 <5,6,7,0>, <2,2,2,2> + 3255584422U, // <7,0,2,3>: Cost 3 vsldoi8 <5,6,7,0>, <2,3,0,1> + 3371647180U, // <7,0,2,4>: Cost 4 vsldoi12 <2,6,3,7>, <0,2,4,6> + 3383148754U, // <7,0,2,5>: Cost 4 vsldoi12 RHS, <0,2,5,3> + 3255584698U, // <7,0,2,6>: Cost 3 vsldoi8 <5,6,7,0>, <2,6,3,7> + 3377397988U, // <7,0,2,7>: Cost 4 vsldoi12 <3,6,0,7>, <0,2,7,3> + 3371647216U, // <7,0,2,u>: Cost 3 vsldoi12 <2,6,3,7>, <0,2,u,6> + 3255584918U, // <7,0,3,0>: Cost 3 vsldoi8 <5,6,7,0>, <3,0,1,2> + 3383148796U, // <7,0,3,1>: Cost 3 vsldoi12 RHS, <0,3,1,0> + 3383148805U, // <7,0,3,2>: Cost 4 vsldoi12 RHS, <0,3,2,0> + 3255585180U, // <7,0,3,3>: Cost 3 vsldoi8 <5,6,7,0>, <3,3,3,3> + 3255585282U, // <7,0,3,4>: Cost 3 vsldoi8 <5,6,7,0>, <3,4,5,6> + 3255585373U, // <7,0,3,5>: Cost 3 vsldoi8 <5,6,7,0>, <3,5,6,7> + 3243641520U, // <7,0,3,6>: Cost 3 vsldoi8 <3,6,7,0>, <3,6,7,0> + 3377398066U, // <7,0,3,7>: Cost 4 vsldoi12 <3,6,0,7>, <0,3,7,0> + 3383148859U, // <7,0,3,u>: Cost 3 vsldoi12 RHS, <0,3,u,0> + 3255585682U, // <7,0,4,0>: Cost 3 vsldoi8 <5,6,7,0>, <4,0,5,1> + 3383148882U, // <7,0,4,1>: Cost 2 vsldoi12 RHS, <0,4,1,5> + 4183345082U, // <7,0,4,2>: Cost 4 vsldoi4 <3,7,0,4>, <2,6,3,7> + 4183345862U, // <7,0,4,3>: Cost 4 vsldoi4 <3,7,0,4>, <3,7,0,4> + 3383148909U, // <7,0,4,4>: Cost 3 vsldoi12 RHS, <0,4,4,5> + 3255586102U, // <7,0,4,5>: Cost 2 vsldoi8 <5,6,7,0>, RHS + 4201263953U, // <7,0,4,6>: Cost 3 vsldoi4 <6,7,0,4>, <6,7,0,4> + 3400319556U, // <7,0,4,7>: Cost 3 vmrghw <7,4,5,6>, <0,7,1,4> + 3383148945U, // <7,0,4,u>: Cost 2 vsldoi12 RHS, <0,4,u,5> + 3255586420U, // <7,0,5,0>: Cost 3 vsldoi8 <5,6,7,0>, <5,0,6,1> + 3400974438U, // <7,0,5,1>: Cost 3 vmrghw <7,5,5,5>, LHS + 3255586539U, // <7,0,5,2>: Cost 4 vsldoi8 <5,6,7,0>, <5,2,1,3> + 3383148976U, // <7,0,5,3>: Cost 4 vsldoi12 RHS, <0,5,3,0> + 3255586748U, // <7,0,5,4>: Cost 3 vsldoi8 <5,6,7,0>, <5,4,6,5> + 3255586820U, // <7,0,5,5>: Cost 3 vsldoi8 <5,6,7,0>, <5,5,5,5> + 3255586914U, // <7,0,5,6>: Cost 2 vsldoi8 <5,6,7,0>, <5,6,7,0> + 3255586941U, // <7,0,5,7>: Cost 4 vsldoi8 <5,6,7,0>, <5,7,1,0> + 3256914180U, // <7,0,5,u>: Cost 2 vsldoi8 <5,u,7,0>, <5,u,7,0> + 3257577813U, // <7,0,6,0>: Cost 3 vsldoi8 <6,0,7,0>, <6,0,7,0> + 3383149046U, // <7,0,6,1>: Cost 3 vsldoi12 RHS, <0,6,1,7> + 3255587322U, // <7,0,6,2>: Cost 3 vsldoi8 <5,6,7,0>, <6,2,7,3> + 3259568712U, // <7,0,6,3>: Cost 3 vsldoi8 <6,3,7,0>, <6,3,7,0> + 3383149073U, // <7,0,6,4>: Cost 4 vsldoi12 RHS, <0,6,4,7> + 3383149082U, // <7,0,6,5>: Cost 4 vsldoi12 RHS, <0,6,5,7> + 3255587640U, // <7,0,6,6>: Cost 3 vsldoi8 <5,6,7,0>, <6,6,6,6> + 3255587662U, // <7,0,6,7>: Cost 3 vsldoi8 <5,6,7,0>, <6,7,0,1> + 3383149109U, // <7,0,6,u>: Cost 3 vsldoi12 RHS, <0,6,u,7> + 3255587834U, // <7,0,7,0>: Cost 3 vsldoi8 <5,6,7,0>, <7,0,1,2> + 2328723558U, // <7,0,7,1>: Cost 2 vmrghw <7,7,7,7>, LHS + 3255587988U, // <7,0,7,2>: Cost 3 vsldoi8 <5,6,7,0>, <7,2,0,3> + 3377398360U, // <7,0,7,3>: Cost 4 vsldoi12 <3,6,0,7>, <0,7,3,6> + 3255588198U, // <7,0,7,4>: Cost 3 vsldoi8 <5,6,7,0>, <7,4,5,6> + 3255588289U, // <7,0,7,5>: Cost 3 vsldoi8 <5,6,7,0>, <7,5,6,7> + 3255588316U, // <7,0,7,6>: Cost 3 vsldoi8 <5,6,7,0>, <7,6,0,7> + 3255588390U, // <7,0,7,7>: Cost 3 vsldoi8 <5,6,7,0>, <7,7,0,0> + 2328724125U, // <7,0,7,u>: Cost 2 vmrghw <7,7,7,7>, LHS + 3127550054U, // <7,0,u,0>: Cost 2 vsldoi4 <6,7,0,u>, LHS + 3383149202U, // <7,0,u,1>: Cost 2 vsldoi12 RHS, <0,u,1,1> + 1235665565U, // <7,0,u,2>: Cost 1 vsldoi12 RHS, LHS + 4183378634U, // <7,0,u,3>: Cost 3 vsldoi4 <3,7,0,u>, <3,7,0,u> + 3127553334U, // <7,0,u,4>: Cost 2 vsldoi4 <6,7,0,u>, RHS + 3255589018U, // <7,0,u,5>: Cost 2 vsldoi8 <5,6,7,0>, RHS + 3127554901U, // <7,0,u,6>: Cost 2 vsldoi4 <6,7,0,u>, <6,7,0,u> + 3255589120U, // <7,0,u,7>: Cost 3 vsldoi8 <5,6,7,0>, + 1235665619U, // <7,0,u,u>: Cost 1 vsldoi12 RHS, LHS + 3258245130U, // <7,1,0,0>: Cost 3 vsldoi8 <6,1,7,1>, <0,0,1,1> + 3383149283U, // <7,1,0,1>: Cost 3 vsldoi12 RHS, <1,0,1,1> + 3383149292U, // <7,1,0,2>: Cost 3 vsldoi12 RHS, <1,0,2,1> + 3383149300U, // <7,1,0,3>: Cost 4 vsldoi12 RHS, <1,0,3,0> + 4213247286U, // <7,1,0,4>: Cost 3 vsldoi4 , RHS + 3524018514U, // <7,1,0,5>: Cost 3 vmrglw <5,6,7,0>, <0,4,1,5> + 3524018596U, // <7,1,0,6>: Cost 3 vmrglw <5,6,7,0>, <0,5,1,6> + 4213249018U, // <7,1,0,7>: Cost 3 vsldoi4 , <7,0,1,2> + 3383149346U, // <7,1,0,u>: Cost 3 vsldoi12 RHS, <1,0,u,1> + 3383149355U, // <7,1,1,0>: Cost 3 vsldoi12 RHS, <1,1,0,1> + 3383149364U, // <7,1,1,1>: Cost 2 vsldoi12 RHS, <1,1,1,1> + 3383149374U, // <7,1,1,2>: Cost 3 vsldoi12 RHS, <1,1,2,2> + 4183395020U, // <7,1,1,3>: Cost 4 vsldoi4 <3,7,1,1>, <3,7,1,1> + 3383149395U, // <7,1,1,4>: Cost 3 vsldoi12 RHS, <1,1,4,5> + 3383149404U, // <7,1,1,5>: Cost 3 vsldoi12 RHS, <1,1,5,5> + 4201313111U, // <7,1,1,6>: Cost 3 vsldoi4 <6,7,1,1>, <6,7,1,1> + 3365528426U, // <7,1,1,7>: Cost 4 vsldoi12 <1,6,1,7>, <1,1,7,1> + 3383149364U, // <7,1,1,u>: Cost 2 vsldoi12 RHS, <1,1,1,1> + 3383149436U, // <7,1,2,0>: Cost 3 vsldoi12 RHS, <1,2,0,1> + 3383149447U, // <7,1,2,1>: Cost 3 vsldoi12 RHS, <1,2,1,3> + 3383149456U, // <7,1,2,2>: Cost 3 vsldoi12 RHS, <1,2,2,3> + 3383149462U, // <7,1,2,3>: Cost 2 vsldoi12 RHS, <1,2,3,0> + 3383149476U, // <7,1,2,4>: Cost 3 vsldoi12 RHS, <1,2,4,5> + 3383149483U, // <7,1,2,5>: Cost 3 vsldoi12 RHS, <1,2,5,3> + 4201321304U, // <7,1,2,6>: Cost 3 vsldoi4 <6,7,1,2>, <6,7,1,2> + 3407037370U, // <7,1,2,7>: Cost 3 vsldoi12 RHS, <1,2,7,0> + 3383149507U, // <7,1,2,u>: Cost 2 vsldoi12 RHS, <1,2,u,0> + 3239667915U, // <7,1,3,0>: Cost 4 vsldoi8 <3,0,7,1>, <3,0,7,1> + 3527360522U, // <7,1,3,1>: Cost 3 vmrglw <6,2,7,3>, <0,0,1,1> + 3524044950U, // <7,1,3,2>: Cost 3 vmrglw <5,6,7,3>, <3,0,1,2> + 3383149543U, // <7,1,3,3>: Cost 4 vsldoi12 RHS, <1,3,3,0> + 3383149552U, // <7,1,3,4>: Cost 4 vsldoi12 RHS, <1,3,4,0> + 3527360850U, // <7,1,3,5>: Cost 3 vmrglw <6,2,7,3>, <0,4,1,5> + 3363906569U, // <7,1,3,6>: Cost 4 vsldoi12 <1,3,6,7>, <1,3,6,7> + 3501483215U, // <7,1,3,7>: Cost 4 vmrglw <1,u,7,3>, <1,6,1,7> + 3527360529U, // <7,1,3,u>: Cost 3 vmrglw <6,2,7,3>, <0,0,1,u> + 3260902290U, // <7,1,4,0>: Cost 3 vsldoi8 <6,5,7,1>, <4,0,5,1> + 3383149611U, // <7,1,4,1>: Cost 3 vsldoi12 RHS, <1,4,1,5> + 3383149620U, // <7,1,4,2>: Cost 3 vsldoi12 RHS, <1,4,2,5> + 3383149624U, // <7,1,4,3>: Cost 4 vsldoi12 RHS, <1,4,3,0> + 4213280054U, // <7,1,4,4>: Cost 3 vsldoi4 , RHS + 3383149648U, // <7,1,4,5>: Cost 3 vsldoi12 RHS, <1,4,5,6> + 3365528664U, // <7,1,4,6>: Cost 4 vsldoi12 <1,6,1,7>, <1,4,6,5> + 4213282150U, // <7,1,4,7>: Cost 3 vsldoi4 , <7,4,5,6> + 3383149674U, // <7,1,4,u>: Cost 3 vsldoi12 RHS, <1,4,u,5> + 3383149679U, // <7,1,5,0>: Cost 3 vsldoi12 RHS, <1,5,0,1> + 3365823613U, // <7,1,5,1>: Cost 4 vsldoi12 <1,6,5,7>, <1,5,1,6> + 3371648134U, // <7,1,5,2>: Cost 4 vsldoi12 <2,6,3,7>, <1,5,2,6> + 3383149705U, // <7,1,5,3>: Cost 4 vsldoi12 RHS, <1,5,3,0> + 3383149719U, // <7,1,5,4>: Cost 3 vsldoi12 RHS, <1,5,4,5> + 3526713682U, // <7,1,5,5>: Cost 3 vmrglw <6,1,7,5>, <0,4,1,5> + 3255595107U, // <7,1,5,6>: Cost 3 vsldoi8 <5,6,7,1>, <5,6,7,1> + 3389416622U, // <7,1,5,7>: Cost 4 vsldoi12 <5,6,1,7>, <1,5,7,1> + 3383149751U, // <7,1,5,u>: Cost 3 vsldoi12 RHS, <1,5,u,1> + 3257586006U, // <7,1,6,0>: Cost 3 vsldoi8 <6,0,7,1>, <6,0,7,1> + 3365528783U, // <7,1,6,1>: Cost 3 vsldoi12 <1,6,1,7>, <1,6,1,7> + 3383149784U, // <7,1,6,2>: Cost 3 vsldoi12 RHS, <1,6,2,7> + 3365676257U, // <7,1,6,3>: Cost 4 vsldoi12 <1,6,3,7>, <1,6,3,7> + 3365749994U, // <7,1,6,4>: Cost 4 vsldoi12 <1,6,4,7>, <1,6,4,7> + 3365823731U, // <7,1,6,5>: Cost 3 vsldoi12 <1,6,5,7>, <1,6,5,7> + 3365897468U, // <7,1,6,6>: Cost 4 vsldoi12 <1,6,6,7>, <1,6,6,7> + 3407037694U, // <7,1,6,7>: Cost 3 vsldoi12 RHS, <1,6,7,0> + 3366044942U, // <7,1,6,u>: Cost 3 vsldoi12 <1,6,u,7>, <1,6,u,7> + 4213301350U, // <7,1,7,0>: Cost 3 vsldoi4 , LHS + 3530047498U, // <7,1,7,1>: Cost 3 vmrglw <6,6,7,7>, <0,0,1,1> + 3525407738U, // <7,1,7,2>: Cost 3 vmrglw <5,u,7,7>, <7,0,1,2> + 3530047662U, // <7,1,7,3>: Cost 4 vmrglw <6,6,7,7>, <0,2,1,3> + 4213304630U, // <7,1,7,4>: Cost 3 vsldoi4 , RHS + 3530047826U, // <7,1,7,5>: Cost 3 vmrglw <6,6,7,7>, <0,4,1,5> + 3510141105U, // <7,1,7,6>: Cost 4 vmrglw <3,3,7,7>, <0,2,1,6> + 3268867692U, // <7,1,7,7>: Cost 3 vsldoi8 <7,u,7,1>, <7,7,7,7> + 3530047505U, // <7,1,7,u>: Cost 3 vmrglw <6,6,7,7>, <0,0,1,u> + 3383149922U, // <7,1,u,0>: Cost 3 vsldoi12 RHS, <1,u,0,1> + 3383149364U, // <7,1,u,1>: Cost 2 vsldoi12 RHS, <1,1,1,1> + 3383149940U, // <7,1,u,2>: Cost 3 vsldoi12 RHS, <1,u,2,1> + 3383149948U, // <7,1,u,3>: Cost 2 vsldoi12 RHS, <1,u,3,0> + 3383149962U, // <7,1,u,4>: Cost 3 vsldoi12 RHS, <1,u,4,5> + 3367150997U, // <7,1,u,5>: Cost 3 vsldoi12 <1,u,5,7>, <1,u,5,7> + 4201370462U, // <7,1,u,6>: Cost 3 vsldoi4 <6,7,1,u>, <6,7,1,u> + 3407037856U, // <7,1,u,7>: Cost 3 vsldoi12 RHS, <1,u,7,0> + 3383149993U, // <7,1,u,u>: Cost 2 vsldoi12 RHS, <1,u,u,0> + 4183457894U, // <7,2,0,0>: Cost 4 vsldoi4 <3,7,2,0>, LHS + 3383150013U, // <7,2,0,1>: Cost 3 vsldoi12 RHS, <2,0,1,2> + 3383150021U, // <7,2,0,2>: Cost 3 vsldoi12 RHS, <2,0,2,1> + 2450276454U, // <7,2,0,3>: Cost 2 vmrglw <5,6,7,0>, LHS + 4183461174U, // <7,2,0,4>: Cost 4 vsldoi4 <3,7,2,0>, RHS + 3383150048U, // <7,2,0,5>: Cost 4 vsldoi12 RHS, <2,0,5,1> + 3371648489U, // <7,2,0,6>: Cost 3 vsldoi12 <2,6,3,7>, <2,0,6,1> + 3397339114U, // <7,2,0,7>: Cost 3 vmrghw <7,0,1,2>, <2,7,0,1> + 2450276459U, // <7,2,0,u>: Cost 2 vmrglw <5,6,7,0>, LHS + 3383150084U, // <7,2,1,0>: Cost 4 vsldoi12 RHS, <2,1,0,1> + 3383150093U, // <7,2,1,1>: Cost 4 vsldoi12 RHS, <2,1,1,1> + 3383150101U, // <7,2,1,2>: Cost 4 vsldoi12 RHS, <2,1,2,0> + 3383150111U, // <7,2,1,3>: Cost 3 vsldoi12 RHS, <2,1,3,1> + 3383150124U, // <7,2,1,4>: Cost 4 vsldoi12 RHS, <2,1,4,5> + 3370985014U, // <7,2,1,5>: Cost 5 vsldoi12 <2,5,3,7>, <2,1,5,6> + 3371648569U, // <7,2,1,6>: Cost 4 vsldoi12 <2,6,3,7>, <2,1,6,0> + 3258254626U, // <7,2,1,7>: Cost 4 vsldoi8 <6,1,7,2>, <1,7,2,0> + 3383150156U, // <7,2,1,u>: Cost 3 vsldoi12 RHS, <2,1,u,1> + 3383150165U, // <7,2,2,0>: Cost 3 vsldoi12 RHS, <2,2,0,1> + 3383150174U, // <7,2,2,1>: Cost 4 vsldoi12 RHS, <2,2,1,1> + 3383150184U, // <7,2,2,2>: Cost 2 vsldoi12 RHS, <2,2,2,2> + 3383150194U, // <7,2,2,3>: Cost 2 vsldoi12 RHS, <2,2,3,3> + 3383150205U, // <7,2,2,4>: Cost 3 vsldoi12 RHS, <2,2,4,5> + 3383150211U, // <7,2,2,5>: Cost 4 vsldoi12 RHS, <2,2,5,2> + 3371648656U, // <7,2,2,6>: Cost 3 vsldoi12 <2,6,3,7>, <2,2,6,6> + 3371574933U, // <7,2,2,7>: Cost 4 vsldoi12 <2,6,2,7>, <2,2,7,2> + 3383150239U, // <7,2,2,u>: Cost 2 vsldoi12 RHS, <2,2,u,3> + 3383150246U, // <7,2,3,0>: Cost 2 vsldoi12 RHS, <2,3,0,1> + 3383150255U, // <7,2,3,1>: Cost 3 vsldoi12 RHS, <2,3,1,1> + 3371648701U, // <7,2,3,2>: Cost 3 vsldoi12 <2,6,3,7>, <2,3,2,6> + 2453618790U, // <7,2,3,3>: Cost 2 vmrglw <6,2,7,3>, LHS + 3383150286U, // <7,2,3,4>: Cost 2 vsldoi12 RHS, <2,3,4,5> + 3383150295U, // <7,2,3,5>: Cost 3 vsldoi12 RHS, <2,3,5,5> + 4201403234U, // <7,2,3,6>: Cost 3 vsldoi4 <6,7,2,3>, <6,7,2,3> + 3527366126U, // <7,2,3,7>: Cost 3 vmrglw <6,2,7,3>, <7,6,2,7> + 3383150318U, // <7,2,3,u>: Cost 2 vsldoi12 RHS, <2,3,u,1> + 4183490662U, // <7,2,4,0>: Cost 4 vsldoi4 <3,7,2,4>, LHS + 3383150340U, // <7,2,4,1>: Cost 4 vsldoi12 RHS, <2,4,1,5> + 3383150349U, // <7,2,4,2>: Cost 3 vsldoi12 RHS, <2,4,2,5> + 2450309222U, // <7,2,4,3>: Cost 2 vmrglw <5,6,7,4>, LHS + 4183493942U, // <7,2,4,4>: Cost 4 vsldoi4 <3,7,2,4>, RHS + 3383150377U, // <7,2,4,5>: Cost 3 vsldoi12 RHS, <2,4,5,6> + 3371648817U, // <7,2,4,6>: Cost 3 vsldoi12 <2,6,3,7>, <2,4,6,5> + 3524052184U, // <7,2,4,7>: Cost 4 vmrglw <5,6,7,4>, <1,6,2,7> + 2450309227U, // <7,2,4,u>: Cost 2 vmrglw <5,6,7,4>, LHS + 3383150408U, // <7,2,5,0>: Cost 4 vsldoi12 RHS, <2,5,0,1> + 3383150418U, // <7,2,5,1>: Cost 4 vsldoi12 RHS, <2,5,1,2> + 3383150427U, // <7,2,5,2>: Cost 4 vsldoi12 RHS, <2,5,2,2> + 3383150440U, // <7,2,5,3>: Cost 3 vsldoi12 RHS, <2,5,3,6> + 3383150448U, // <7,2,5,4>: Cost 4 vsldoi12 RHS, <2,5,4,5> + 3255603204U, // <7,2,5,5>: Cost 4 vsldoi8 <5,6,7,2>, <5,5,5,5> + 3255603300U, // <7,2,5,6>: Cost 3 vsldoi8 <5,6,7,2>, <5,6,7,2> + 3371575180U, // <7,2,5,7>: Cost 5 vsldoi12 <2,6,2,7>, <2,5,7,6> + 3383150485U, // <7,2,5,u>: Cost 3 vsldoi12 RHS, <2,5,u,6> + 4183507046U, // <7,2,6,0>: Cost 3 vsldoi4 <3,7,2,6>, LHS + 3258257832U, // <7,2,6,1>: Cost 3 vsldoi8 <6,1,7,2>, <6,1,7,2> + 3371575217U, // <7,2,6,2>: Cost 3 vsldoi12 <2,6,2,7>, <2,6,2,7> + 3371648954U, // <7,2,6,3>: Cost 2 vsldoi12 <2,6,3,7>, <2,6,3,7> + 4183510326U, // <7,2,6,4>: Cost 3 vsldoi4 <3,7,2,6>, RHS + 3371796428U, // <7,2,6,5>: Cost 4 vsldoi12 <2,6,5,7>, <2,6,5,7> + 4201427813U, // <7,2,6,6>: Cost 3 vsldoi4 <6,7,2,6>, <6,7,2,6> + 3371575262U, // <7,2,6,7>: Cost 4 vsldoi12 <2,6,2,7>, <2,6,7,7> + 3372017639U, // <7,2,6,u>: Cost 2 vsldoi12 <2,6,u,7>, <2,6,u,7> + 3407038442U, // <7,2,7,0>: Cost 3 vsldoi12 RHS, <2,7,0,1> + 3383150584U, // <7,2,7,1>: Cost 4 vsldoi12 RHS, <2,7,1,6> + 3530049128U, // <7,2,7,2>: Cost 3 vmrglw <6,6,7,7>, <2,2,2,2> + 2456305766U, // <7,2,7,3>: Cost 2 vmrglw <6,6,7,7>, LHS + 3371575314U, // <7,2,7,4>: Cost 4 vsldoi12 <2,6,2,7>, <2,7,4,5> + 3530048564U, // <7,2,7,5>: Cost 4 vmrglw <6,6,7,7>, <1,4,2,5> + 3402467258U, // <7,2,7,6>: Cost 3 vmrghw <7,7,7,7>, <2,6,3,7> + 3506161585U, // <7,2,7,7>: Cost 4 vmrglw <2,6,7,7>, <2,6,2,7> + 2456305771U, // <7,2,7,u>: Cost 2 vmrglw <6,6,7,7>, LHS + 3383150651U, // <7,2,u,0>: Cost 2 vsldoi12 RHS, <2,u,0,1> + 3383150660U, // <7,2,u,1>: Cost 3 vsldoi12 RHS, <2,u,1,1> + 3383150184U, // <7,2,u,2>: Cost 2 vsldoi12 RHS, <2,2,2,2> + 3372976220U, // <7,2,u,3>: Cost 2 vsldoi12 <2,u,3,7>, <2,u,3,7> + 3383150691U, // <7,2,u,4>: Cost 2 vsldoi12 RHS, <2,u,4,5> + 3383150700U, // <7,2,u,5>: Cost 3 vsldoi12 RHS, <2,u,5,5> + 3371649137U, // <7,2,u,6>: Cost 3 vsldoi12 <2,6,3,7>, <2,u,6,1> + 3407038585U, // <7,2,u,7>: Cost 3 vsldoi12 RHS, <2,u,7,0> + 3373344905U, // <7,2,u,u>: Cost 2 vsldoi12 <2,u,u,7>, <2,u,u,7> + 3383150731U, // <7,3,0,0>: Cost 3 vsldoi12 RHS, <3,0,0,0> + 3383150742U, // <7,3,0,1>: Cost 2 vsldoi12 RHS, <3,0,1,2> + 4177561604U, // <7,3,0,2>: Cost 3 vsldoi4 <2,7,3,0>, <2,7,3,0> + 3383150759U, // <7,3,0,3>: Cost 3 vsldoi12 RHS, <3,0,3,1> + 3383150768U, // <7,3,0,4>: Cost 3 vsldoi12 RHS, <3,0,4,1> + 3383150781U, // <7,3,0,5>: Cost 4 vsldoi12 RHS, <3,0,5,5> + 4201452392U, // <7,3,0,6>: Cost 3 vsldoi4 <6,7,3,0>, <6,7,3,0> + 3524020154U, // <7,3,0,7>: Cost 3 vmrglw <5,6,7,0>, <2,6,3,7> + 3383150805U, // <7,3,0,u>: Cost 2 vsldoi12 RHS, <3,0,u,2> + 3383150812U, // <7,3,1,0>: Cost 4 vsldoi12 RHS, <3,1,0,0> + 3383150822U, // <7,3,1,1>: Cost 3 vsldoi12 RHS, <3,1,1,1> + 3383150833U, // <7,3,1,2>: Cost 3 vsldoi12 RHS, <3,1,2,3> + 3383150839U, // <7,3,1,3>: Cost 4 vsldoi12 RHS, <3,1,3,0> + 3383150848U, // <7,3,1,4>: Cost 4 vsldoi12 RHS, <3,1,4,0> + 3383150857U, // <7,3,1,5>: Cost 4 vsldoi12 RHS, <3,1,5,0> + 3365529875U, // <7,3,1,6>: Cost 4 vsldoi12 <1,6,1,7>, <3,1,6,1> + 3371649308U, // <7,3,1,7>: Cost 4 vsldoi12 <2,6,3,7>, <3,1,7,1> + 3383150887U, // <7,3,1,u>: Cost 3 vsldoi12 RHS, <3,1,u,3> + 3383150896U, // <7,3,2,0>: Cost 3 vsldoi12 RHS, <3,2,0,3> + 3383150904U, // <7,3,2,1>: Cost 4 vsldoi12 RHS, <3,2,1,2> + 3383150913U, // <7,3,2,2>: Cost 3 vsldoi12 RHS, <3,2,2,2> + 3383150920U, // <7,3,2,3>: Cost 3 vsldoi12 RHS, <3,2,3,0> + 3383150932U, // <7,3,2,4>: Cost 3 vsldoi12 RHS, <3,2,4,3> + 3383150941U, // <7,3,2,5>: Cost 4 vsldoi12 RHS, <3,2,5,3> + 3371649382U, // <7,3,2,6>: Cost 3 vsldoi12 <2,6,3,7>, <3,2,6,3> + 3371649391U, // <7,3,2,7>: Cost 3 vsldoi12 <2,6,3,7>, <3,2,7,3> + 3383150965U, // <7,3,2,u>: Cost 3 vsldoi12 RHS, <3,2,u,0> + 3383150974U, // <7,3,3,0>: Cost 3 vsldoi12 RHS, <3,3,0,0> + 3383150984U, // <7,3,3,1>: Cost 4 vsldoi12 RHS, <3,3,1,1> + 3241011567U, // <7,3,3,2>: Cost 3 vsldoi8 <3,2,7,3>, <3,2,7,3> + 3383151004U, // <7,3,3,3>: Cost 2 vsldoi12 RHS, <3,3,3,3> + 3383151014U, // <7,3,3,4>: Cost 3 vsldoi12 RHS, <3,3,4,4> + 3383151022U, // <7,3,3,5>: Cost 4 vsldoi12 RHS, <3,3,5,3> + 4201476971U, // <7,3,3,6>: Cost 3 vsldoi4 <6,7,3,3>, <6,7,3,3> + 3371649476U, // <7,3,3,7>: Cost 3 vsldoi12 <2,6,3,7>, <3,3,7,7> + 3383151004U, // <7,3,3,u>: Cost 2 vsldoi12 RHS, <3,3,3,3> + 3383151056U, // <7,3,4,0>: Cost 3 vsldoi12 RHS, <3,4,0,1> + 3383151066U, // <7,3,4,1>: Cost 3 vsldoi12 RHS, <3,4,1,2> + 4177594376U, // <7,3,4,2>: Cost 3 vsldoi4 <2,7,3,4>, <2,7,3,4> + 3383151087U, // <7,3,4,3>: Cost 3 vsldoi12 RHS, <3,4,3,5> + 3383151095U, // <7,3,4,4>: Cost 3 vsldoi12 RHS, <3,4,4,4> + 3383151106U, // <7,3,4,5>: Cost 2 vsldoi12 RHS, <3,4,5,6> + 3258928505U, // <7,3,4,6>: Cost 3 vsldoi8 <6,2,7,3>, <4,6,5,2> + 3524052922U, // <7,3,4,7>: Cost 3 vmrglw <5,6,7,4>, <2,6,3,7> + 3383151133U, // <7,3,4,u>: Cost 2 vsldoi12 RHS, <3,4,u,6> + 3383151137U, // <7,3,5,0>: Cost 4 vsldoi12 RHS, <3,5,0,1> + 3258928783U, // <7,3,5,1>: Cost 4 vsldoi8 <6,2,7,3>, <5,1,0,1> + 3383151155U, // <7,3,5,2>: Cost 4 vsldoi12 RHS, <3,5,2,1> + 3383151166U, // <7,3,5,3>: Cost 4 vsldoi12 RHS, <3,5,3,3> + 3383151177U, // <7,3,5,4>: Cost 4 vsldoi12 RHS, <3,5,4,5> + 3383151186U, // <7,3,5,5>: Cost 3 vsldoi12 RHS, <3,5,5,5> + 3255611493U, // <7,3,5,6>: Cost 3 vsldoi8 <5,6,7,3>, <5,6,7,3> + 3371649637U, // <7,3,5,7>: Cost 4 vsldoi12 <2,6,3,7>, <3,5,7,6> + 3256938759U, // <7,3,5,u>: Cost 3 vsldoi8 <5,u,7,3>, <5,u,7,3> + 3377400440U, // <7,3,6,0>: Cost 3 vsldoi12 <3,6,0,7>, <3,6,0,7> + 3377474177U, // <7,3,6,1>: Cost 4 vsldoi12 <3,6,1,7>, <3,6,1,7> + 3258929658U, // <7,3,6,2>: Cost 2 vsldoi8 <6,2,7,3>, <6,2,7,3> + 3377621651U, // <7,3,6,3>: Cost 3 vsldoi12 <3,6,3,7>, <3,6,3,7> + 3377695388U, // <7,3,6,4>: Cost 3 vsldoi12 <3,6,4,7>, <3,6,4,7> + 3377769125U, // <7,3,6,5>: Cost 4 vsldoi12 <3,6,5,7>, <3,6,5,7> + 3258929936U, // <7,3,6,6>: Cost 3 vsldoi8 <6,2,7,3>, <6,6,2,2> + 3371649719U, // <7,3,6,7>: Cost 3 vsldoi12 <2,6,3,7>, <3,6,7,7> + 3262911456U, // <7,3,6,u>: Cost 2 vsldoi8 <6,u,7,3>, <6,u,7,3> + 3371649731U, // <7,3,7,0>: Cost 3 vsldoi12 <2,6,3,7>, <3,7,0,1> + 3371649740U, // <7,3,7,1>: Cost 4 vsldoi12 <2,6,3,7>, <3,7,1,1> + 3371649754U, // <7,3,7,2>: Cost 3 vsldoi12 <2,6,3,7>, <3,7,2,6> + 3258930458U, // <7,3,7,3>: Cost 3 vsldoi8 <6,2,7,3>, <7,3,6,2> + 3371649771U, // <7,3,7,4>: Cost 3 vsldoi12 <2,6,3,7>, <3,7,4,5> + 3383151348U, // <7,3,7,5>: Cost 4 vsldoi12 RHS, <3,7,5,5> + 3258930670U, // <7,3,7,6>: Cost 3 vsldoi8 <6,2,7,3>, <7,6,2,7> + 3510142906U, // <7,3,7,7>: Cost 3 vmrglw <3,3,7,7>, <2,6,3,7> + 3371649803U, // <7,3,7,u>: Cost 3 vsldoi12 <2,6,3,7>, <3,7,u,1> + 3378727706U, // <7,3,u,0>: Cost 3 vsldoi12 <3,u,0,7>, <3,u,0,7> + 3383151390U, // <7,3,u,1>: Cost 2 vsldoi12 RHS, <3,u,1,2> + 3270875052U, // <7,3,u,2>: Cost 2 vsldoi8 , + 3383151004U, // <7,3,u,3>: Cost 2 vsldoi12 RHS, <3,3,3,3> + 3379022654U, // <7,3,u,4>: Cost 3 vsldoi12 <3,u,4,7>, <3,u,4,7> + 3383151430U, // <7,3,u,5>: Cost 2 vsldoi12 RHS, <3,u,5,6> + 3383151436U, // <7,3,u,6>: Cost 3 vsldoi12 RHS, <3,u,6,3> + 3371649877U, // <7,3,u,7>: Cost 3 vsldoi12 <2,6,3,7>, <3,u,7,3> + 3383151453U, // <7,3,u,u>: Cost 2 vsldoi12 RHS, <3,u,u,2> + 3255615488U, // <7,4,0,0>: Cost 3 vsldoi8 <5,6,7,4>, <0,0,0,0> + 3255615590U, // <7,4,0,1>: Cost 2 vsldoi8 <5,6,7,4>, LHS + 3383151479U, // <7,4,0,2>: Cost 4 vsldoi12 RHS, <4,0,2,1> + 3383151488U, // <7,4,0,3>: Cost 4 vsldoi12 RHS, <4,0,3,1> + 3524021456U, // <7,4,0,4>: Cost 3 vmrglw <5,6,7,0>, <4,4,4,4> + 3383151506U, // <7,4,0,5>: Cost 2 vsldoi12 RHS, <4,0,5,1> + 4201526129U, // <7,4,0,6>: Cost 3 vsldoi4 <6,7,4,0>, <6,7,4,0> + 3397340616U, // <7,4,0,7>: Cost 3 vmrghw <7,0,1,2>, <4,7,5,0> + 3385142189U, // <7,4,0,u>: Cost 2 vsldoi12 RHS, <4,0,u,1> + 3383151542U, // <7,4,1,0>: Cost 4 vsldoi12 RHS, <4,1,0,1> + 3255616308U, // <7,4,1,1>: Cost 3 vsldoi8 <5,6,7,4>, <1,1,1,1> + 3383151562U, // <7,4,1,2>: Cost 3 vsldoi12 RHS, <4,1,2,3> + 3383151568U, // <7,4,1,3>: Cost 4 vsldoi12 RHS, <4,1,3,0> + 3383151579U, // <7,4,1,4>: Cost 4 vsldoi12 RHS, <4,1,4,2> + 3383151586U, // <7,4,1,5>: Cost 3 vsldoi12 RHS, <4,1,5,0> + 3255616719U, // <7,4,1,6>: Cost 4 vsldoi8 <5,6,7,4>, <1,6,1,7> + 3528673948U, // <7,4,1,7>: Cost 4 vmrglw <6,4,7,1>, <3,6,4,7> + 3383151613U, // <7,4,1,u>: Cost 3 vsldoi12 RHS, <4,1,u,0> + 3383151625U, // <7,4,2,0>: Cost 4 vsldoi12 RHS, <4,2,0,3> + 3383151634U, // <7,4,2,1>: Cost 4 vsldoi12 RHS, <4,2,1,3> + 3255617128U, // <7,4,2,2>: Cost 3 vsldoi8 <5,6,7,4>, <2,2,2,2> + 3255617190U, // <7,4,2,3>: Cost 3 vsldoi8 <5,6,7,4>, <2,3,0,1> + 3383151661U, // <7,4,2,4>: Cost 3 vsldoi12 RHS, <4,2,4,3> + 3383151669U, // <7,4,2,5>: Cost 3 vsldoi12 RHS, <4,2,5,2> + 3255617466U, // <7,4,2,6>: Cost 3 vsldoi8 <5,6,7,4>, <2,6,3,7> + 3377695816U, // <7,4,2,7>: Cost 4 vsldoi12 <3,6,4,7>, <4,2,7,3> + 3383151697U, // <7,4,2,u>: Cost 3 vsldoi12 RHS, <4,2,u,3> + 3255617686U, // <7,4,3,0>: Cost 3 vsldoi8 <5,6,7,4>, <3,0,1,2> + 3383151714U, // <7,4,3,1>: Cost 4 vsldoi12 RHS, <4,3,1,2> + 3383151724U, // <7,4,3,2>: Cost 4 vsldoi12 RHS, <4,3,2,3> + 3255617948U, // <7,4,3,3>: Cost 3 vsldoi8 <5,6,7,4>, <3,3,3,3> + 3255618050U, // <7,4,3,4>: Cost 3 vsldoi8 <5,6,7,4>, <3,4,5,6> + 3383151748U, // <7,4,3,5>: Cost 3 vsldoi12 RHS, <4,3,5,0> + 3243674292U, // <7,4,3,6>: Cost 3 vsldoi8 <3,6,7,4>, <3,6,7,4> + 3377695898U, // <7,4,3,7>: Cost 4 vsldoi12 <3,6,4,7>, <4,3,7,4> + 3385142431U, // <7,4,3,u>: Cost 3 vsldoi12 RHS, <4,3,u,0> + 3255618450U, // <7,4,4,0>: Cost 3 vsldoi8 <5,6,7,4>, <4,0,5,1> + 3383151794U, // <7,4,4,1>: Cost 4 vsldoi12 RHS, <4,4,1,1> + 3383151804U, // <7,4,4,2>: Cost 4 vsldoi12 RHS, <4,4,2,2> + 3524056248U, // <7,4,4,3>: Cost 3 vmrglw <5,6,7,4>, <7,2,4,3> + 3383151824U, // <7,4,4,4>: Cost 2 vsldoi12 RHS, <4,4,4,4> + 3383151834U, // <7,4,4,5>: Cost 2 vsldoi12 RHS, <4,4,5,5> + 4201558901U, // <7,4,4,6>: Cost 3 vsldoi4 <6,7,4,4>, <6,7,4,4> + 3524056576U, // <7,4,4,7>: Cost 3 vmrglw <5,6,7,4>, <7,6,4,7> + 3385142517U, // <7,4,4,u>: Cost 2 vsldoi12 RHS, <4,4,u,5> + 3127820390U, // <7,4,5,0>: Cost 2 vsldoi4 <6,7,4,5>, LHS + 4201562932U, // <7,4,5,1>: Cost 3 vsldoi4 <6,7,4,5>, <1,1,1,1> + 4183648186U, // <7,4,5,2>: Cost 3 vsldoi4 <3,7,4,5>, <2,6,3,7> + 4183649003U, // <7,4,5,3>: Cost 3 vsldoi4 <3,7,4,5>, <3,7,4,5> + 3127823670U, // <7,4,5,4>: Cost 2 vsldoi4 <6,7,4,5>, RHS + 3383151910U, // <7,4,5,5>: Cost 3 vsldoi12 RHS, <4,5,5,0> + 1235668278U, // <7,4,5,6>: Cost 1 vsldoi12 RHS, RHS + 4201567226U, // <7,4,5,7>: Cost 3 vsldoi4 <6,7,4,5>, <7,0,1,2> + 1235668296U, // <7,4,5,u>: Cost 1 vsldoi12 RHS, RHS + 3383151953U, // <7,4,6,0>: Cost 4 vsldoi12 RHS, <4,6,0,7> + 3383151962U, // <7,4,6,1>: Cost 4 vsldoi12 RHS, <4,6,1,7> + 3255620090U, // <7,4,6,2>: Cost 3 vsldoi8 <5,6,7,4>, <6,2,7,3> + 3259601484U, // <7,4,6,3>: Cost 3 vsldoi8 <6,3,7,4>, <6,3,7,4> + 3260265117U, // <7,4,6,4>: Cost 3 vsldoi8 <6,4,7,4>, <6,4,7,4> + 3383151997U, // <7,4,6,5>: Cost 3 vsldoi12 RHS, <4,6,5,6> + 3255620408U, // <7,4,6,6>: Cost 3 vsldoi8 <5,6,7,4>, <6,6,6,6> + 3255620430U, // <7,4,6,7>: Cost 3 vsldoi8 <5,6,7,4>, <6,7,0,1> + 3383152025U, // <7,4,6,u>: Cost 3 vsldoi12 RHS, <4,6,u,7> + 3255620602U, // <7,4,7,0>: Cost 3 vsldoi8 <5,6,7,4>, <7,0,1,2> + 3377696166U, // <7,4,7,1>: Cost 4 vsldoi12 <3,6,4,7>, <4,7,1,2> + 3255620792U, // <7,4,7,2>: Cost 3 vsldoi8 <5,6,7,4>, <7,2,4,3> + 3377696188U, // <7,4,7,3>: Cost 4 vsldoi12 <3,6,4,7>, <4,7,3,6> + 3255620916U, // <7,4,7,4>: Cost 3 vsldoi8 <5,6,7,4>, <7,4,0,1> + 2328726838U, // <7,4,7,5>: Cost 2 vmrghw <7,7,7,7>, RHS + 3255621120U, // <7,4,7,6>: Cost 3 vsldoi8 <5,6,7,4>, <7,6,4,7> + 3255621198U, // <7,4,7,7>: Cost 3 vsldoi8 <5,6,7,4>, <7,7,4,4> + 2328727081U, // <7,4,7,u>: Cost 2 vmrghw <7,7,7,7>, RHS + 3127844966U, // <7,4,u,0>: Cost 2 vsldoi4 <6,7,4,u>, LHS + 3255621422U, // <7,4,u,1>: Cost 2 vsldoi8 <5,6,7,4>, LHS + 4183672762U, // <7,4,u,2>: Cost 3 vsldoi4 <3,7,4,u>, <2,6,3,7> + 4183673582U, // <7,4,u,3>: Cost 3 vsldoi4 <3,7,4,u>, <3,7,4,u> + 3127848246U, // <7,4,u,4>: Cost 2 vsldoi4 <6,7,4,u>, RHS + 3383152154U, // <7,4,u,5>: Cost 2 vsldoi12 RHS, <4,u,5,1> + 1235668521U, // <7,4,u,6>: Cost 1 vsldoi12 RHS, RHS + 3255621888U, // <7,4,u,7>: Cost 3 vsldoi8 <5,6,7,4>, + 1235668539U, // <7,4,u,u>: Cost 1 vsldoi12 RHS, RHS + 4189651046U, // <7,5,0,0>: Cost 3 vsldoi4 <4,7,5,0>, LHS + 3383152200U, // <7,5,0,1>: Cost 3 vsldoi12 RHS, <5,0,1,2> + 3383152210U, // <7,5,0,2>: Cost 4 vsldoi12 RHS, <5,0,2,3> + 3383152220U, // <7,5,0,3>: Cost 4 vsldoi12 RHS, <5,0,3,4> + 3383152226U, // <7,5,0,4>: Cost 3 vsldoi12 RHS, <5,0,4,1> + 3524021466U, // <7,5,0,5>: Cost 3 vmrglw <5,6,7,0>, <4,4,5,5> + 3524020738U, // <7,5,0,6>: Cost 3 vmrglw <5,6,7,0>, <3,4,5,6> + 4189656058U, // <7,5,0,7>: Cost 3 vsldoi4 <4,7,5,0>, <7,0,1,2> + 3383152262U, // <7,5,0,u>: Cost 3 vsldoi12 RHS, <5,0,u,1> + 3385142927U, // <7,5,1,0>: Cost 3 vsldoi12 RHS, <5,1,0,1> + 3529337746U, // <7,5,1,1>: Cost 3 vmrglw <6,5,7,1>, <4,0,5,1> + 3383152291U, // <7,5,1,2>: Cost 4 vsldoi12 RHS, <5,1,2,3> + 3383152302U, // <7,5,1,3>: Cost 4 vsldoi12 RHS, <5,1,3,5> + 3385142967U, // <7,5,1,4>: Cost 3 vsldoi12 RHS, <5,1,4,5> + 3383152315U, // <7,5,1,5>: Cost 4 vsldoi12 RHS, <5,1,5,0> + 3365826249U, // <7,5,1,6>: Cost 4 vsldoi12 <1,6,5,7>, <5,1,6,5> + 3365826258U, // <7,5,1,7>: Cost 4 vsldoi12 <1,6,5,7>, <5,1,7,5> + 3385142999U, // <7,5,1,u>: Cost 3 vsldoi12 RHS, <5,1,u,1> + 3383152352U, // <7,5,2,0>: Cost 4 vsldoi12 RHS, <5,2,0,1> + 3385143019U, // <7,5,2,1>: Cost 3 vsldoi12 RHS, <5,2,1,3> + 3383152371U, // <7,5,2,2>: Cost 4 vsldoi12 RHS, <5,2,2,2> + 3383152382U, // <7,5,2,3>: Cost 3 vsldoi12 RHS, <5,2,3,4> + 3243681585U, // <7,5,2,4>: Cost 4 vsldoi8 <3,6,7,5>, <2,4,6,5> + 3385143055U, // <7,5,2,5>: Cost 3 vsldoi12 RHS, <5,2,5,3> + 3383152408U, // <7,5,2,6>: Cost 3 vsldoi12 RHS, <5,2,6,3> + 3365826337U, // <7,5,2,7>: Cost 4 vsldoi12 <1,6,5,7>, <5,2,7,3> + 3383152426U, // <7,5,2,u>: Cost 3 vsldoi12 RHS, <5,2,u,3> + 3383152433U, // <7,5,3,0>: Cost 4 vsldoi12 RHS, <5,3,0,1> + 3527363474U, // <7,5,3,1>: Cost 3 vmrglw <6,2,7,3>, <4,0,5,1> + 3527363961U, // <7,5,3,2>: Cost 3 vmrglw <6,2,7,3>, <4,6,5,2> + 3383152462U, // <7,5,3,3>: Cost 4 vsldoi12 RHS, <5,3,3,3> + 3242355219U, // <7,5,3,4>: Cost 4 vsldoi8 <3,4,7,5>, <3,4,7,5> + 3527363802U, // <7,5,3,5>: Cost 3 vmrglw <6,2,7,3>, <4,4,5,5> + 3527363074U, // <7,5,3,6>: Cost 3 vmrglw <6,2,7,3>, <3,4,5,6> + 3383152499U, // <7,5,3,7>: Cost 4 vsldoi12 RHS, <5,3,7,4> + 3527363076U, // <7,5,3,u>: Cost 3 vmrglw <6,2,7,3>, <3,4,5,u> + 4189683814U, // <7,5,4,0>: Cost 3 vsldoi4 <4,7,5,4>, LHS + 3524053906U, // <7,5,4,1>: Cost 3 vmrglw <5,6,7,4>, <4,0,5,1> + 3383152534U, // <7,5,4,2>: Cost 4 vsldoi12 RHS, <5,4,2,3> + 3383152544U, // <7,5,4,3>: Cost 4 vsldoi12 RHS, <5,4,3,4> + 4189687244U, // <7,5,4,4>: Cost 3 vsldoi4 <4,7,5,4>, <4,7,5,4> + 3383152564U, // <7,5,4,5>: Cost 3 vsldoi12 RHS, <5,4,5,6> + 3524053506U, // <7,5,4,6>: Cost 3 vmrglw <5,6,7,4>, <3,4,5,6> + 4189689190U, // <7,5,4,7>: Cost 3 vsldoi4 <4,7,5,4>, <7,4,5,6> + 3383152591U, // <7,5,4,u>: Cost 3 vsldoi12 RHS, <5,4,u,6> + 3385143251U, // <7,5,5,0>: Cost 3 vsldoi12 RHS, <5,5,0,1> + 3385143260U, // <7,5,5,1>: Cost 3 vsldoi12 RHS, <5,5,1,1> + 3383152614U, // <7,5,5,2>: Cost 4 vsldoi12 RHS, <5,5,2,2> + 3383152624U, // <7,5,5,3>: Cost 4 vsldoi12 RHS, <5,5,3,3> + 3385143291U, // <7,5,5,4>: Cost 3 vsldoi12 RHS, <5,5,4,5> + 3383152644U, // <7,5,5,5>: Cost 2 vsldoi12 RHS, <5,5,5,5> + 3383152654U, // <7,5,5,6>: Cost 3 vsldoi12 RHS, <5,5,6,6> + 3365826584U, // <7,5,5,7>: Cost 4 vsldoi12 <1,6,5,7>, <5,5,7,7> + 3383152644U, // <7,5,5,u>: Cost 2 vsldoi12 RHS, <5,5,5,5> + 3383152676U, // <7,5,6,0>: Cost 3 vsldoi12 RHS, <5,6,0,1> + 3385143347U, // <7,5,6,1>: Cost 3 vsldoi12 RHS, <5,6,1,7> + 3383152695U, // <7,5,6,2>: Cost 4 vsldoi12 RHS, <5,6,2,2> + 3383152706U, // <7,5,6,3>: Cost 3 vsldoi12 RHS, <5,6,3,4> + 3383152716U, // <7,5,6,4>: Cost 3 vsldoi12 RHS, <5,6,4,5> + 3385143383U, // <7,5,6,5>: Cost 3 vsldoi12 RHS, <5,6,5,7> + 3383152736U, // <7,5,6,6>: Cost 3 vsldoi12 RHS, <5,6,6,7> + 3383152738U, // <7,5,6,7>: Cost 2 vsldoi12 RHS, <5,6,7,0> + 3383300203U, // <7,5,6,u>: Cost 2 vsldoi12 RHS, <5,6,u,0> + 4189708390U, // <7,5,7,0>: Cost 3 vsldoi4 <4,7,5,7>, LHS + 3530050450U, // <7,5,7,1>: Cost 3 vmrglw <6,6,7,7>, <4,0,5,1> + 4189709928U, // <7,5,7,2>: Cost 4 vsldoi4 <4,7,5,7>, <2,2,2,2> + 4189710486U, // <7,5,7,3>: Cost 4 vsldoi4 <4,7,5,7>, <3,0,1,2> + 4189711823U, // <7,5,7,4>: Cost 3 vsldoi4 <4,7,5,7>, <4,7,5,7> + 3530050778U, // <7,5,7,5>: Cost 3 vmrglw <6,6,7,7>, <4,4,5,5> + 3530050050U, // <7,5,7,6>: Cost 3 vmrglw <6,6,7,7>, <3,4,5,6> + 4189714028U, // <7,5,7,7>: Cost 3 vsldoi4 <4,7,5,7>, <7,7,7,7> + 4189714222U, // <7,5,7,u>: Cost 3 vsldoi4 <4,7,5,7>, LHS + 3383152838U, // <7,5,u,0>: Cost 3 vsldoi12 RHS, <5,u,0,1> + 3383152848U, // <7,5,u,1>: Cost 3 vsldoi12 RHS, <5,u,1,2> + 3527363961U, // <7,5,u,2>: Cost 3 vmrglw <6,2,7,3>, <4,6,5,2> + 3383152868U, // <7,5,u,3>: Cost 3 vsldoi12 RHS, <5,u,3,4> + 3383152877U, // <7,5,u,4>: Cost 3 vsldoi12 RHS, <5,u,4,4> + 3383152644U, // <7,5,u,5>: Cost 2 vsldoi12 RHS, <5,5,5,5> + 3383152894U, // <7,5,u,6>: Cost 3 vsldoi12 RHS, <5,u,6,3> + 3383300356U, // <7,5,u,7>: Cost 2 vsldoi12 RHS, <5,u,7,0> + 3385143565U, // <7,5,u,u>: Cost 2 vsldoi12 RHS, <5,u,u,0> + 3383152918U, // <7,6,0,0>: Cost 4 vsldoi12 RHS, <6,0,0,0> + 3383152929U, // <7,6,0,1>: Cost 3 vsldoi12 RHS, <6,0,1,2> + 3397341690U, // <7,6,0,2>: Cost 3 vmrghw <7,0,1,2>, <6,2,7,3> + 3383152946U, // <7,6,0,3>: Cost 4 vsldoi12 RHS, <6,0,3,1> + 3383152955U, // <7,6,0,4>: Cost 4 vsldoi12 RHS, <6,0,4,1> + 3524022204U, // <7,6,0,5>: Cost 3 vmrglw <5,6,7,0>, <5,4,6,5> + 3524023096U, // <7,6,0,6>: Cost 3 vmrglw <5,6,7,0>, <6,6,6,6> + 2450279734U, // <7,6,0,7>: Cost 2 vmrglw <5,6,7,0>, RHS + 2450279735U, // <7,6,0,u>: Cost 2 vmrglw <5,6,7,0>, RHS + 3383153000U, // <7,6,1,0>: Cost 4 vsldoi12 RHS, <6,1,0,1> + 3512083945U, // <7,6,1,1>: Cost 4 vmrglw <3,6,7,1>, <2,0,6,1> + 3383153020U, // <7,6,1,2>: Cost 4 vsldoi12 RHS, <6,1,2,3> + 3363910024U, // <7,6,1,3>: Cost 5 vsldoi12 <1,3,6,7>, <6,1,3,6> + 3383153040U, // <7,6,1,4>: Cost 4 vsldoi12 RHS, <6,1,4,5> + 3529339784U, // <7,6,1,5>: Cost 4 vmrglw <6,5,7,1>, <6,7,6,5> + 3524031288U, // <7,6,1,6>: Cost 4 vmrglw <5,6,7,1>, <6,6,6,6> + 3383153063U, // <7,6,1,7>: Cost 3 vsldoi12 RHS, <6,1,7,1> + 3383300528U, // <7,6,1,u>: Cost 3 vsldoi12 RHS, <6,1,u,1> + 4201685094U, // <7,6,2,0>: Cost 3 vsldoi4 <6,7,6,2>, LHS + 3383153092U, // <7,6,2,1>: Cost 4 vsldoi12 RHS, <6,2,1,3> + 3398824442U, // <7,6,2,2>: Cost 3 vmrghw <7,2,3,3>, <6,2,7,3> + 3371651541U, // <7,6,2,3>: Cost 4 vsldoi12 <2,6,3,7>, <6,2,3,2> + 4201688374U, // <7,6,2,4>: Cost 3 vsldoi4 <6,7,6,2>, RHS + 3383153128U, // <7,6,2,5>: Cost 4 vsldoi12 RHS, <6,2,5,3> + 4201689989U, // <7,6,2,6>: Cost 3 vsldoi4 <6,7,6,2>, <6,7,6,2> + 3383153146U, // <7,6,2,7>: Cost 2 vsldoi12 RHS, <6,2,7,3> + 3383300611U, // <7,6,2,u>: Cost 2 vsldoi12 RHS, <6,2,u,3> + 4183777382U, // <7,6,3,0>: Cost 4 vsldoi4 <3,7,6,3>, LHS + 3240372513U, // <7,6,3,1>: Cost 4 vsldoi8 <3,1,7,6>, <3,1,7,6> + 3527365509U, // <7,6,3,2>: Cost 3 vmrglw <6,2,7,3>, <6,7,6,2> + 3509447014U, // <7,6,3,3>: Cost 4 vmrglw <3,2,7,3>, <3,2,6,3> + 3383153202U, // <7,6,3,4>: Cost 3 vsldoi12 RHS, <6,3,4,5> + 3509446449U, // <7,6,3,5>: Cost 4 vmrglw <3,2,7,3>, <2,4,6,5> + 3527365432U, // <7,6,3,6>: Cost 3 vmrglw <6,2,7,3>, <6,6,6,6> + 2453622070U, // <7,6,3,7>: Cost 2 vmrglw <6,2,7,3>, RHS + 2453622071U, // <7,6,3,u>: Cost 2 vmrglw <6,2,7,3>, RHS + 3383153243U, // <7,6,4,0>: Cost 4 vsldoi12 RHS, <6,4,0,1> + 3524052457U, // <7,6,4,1>: Cost 4 vmrglw <5,6,7,4>, <2,0,6,1> + 3400323578U, // <7,6,4,2>: Cost 3 vmrghw <7,4,5,6>, <6,2,7,3> + 3383153273U, // <7,6,4,3>: Cost 4 vsldoi12 RHS, <6,4,3,4> + 3383153282U, // <7,6,4,4>: Cost 4 vsldoi12 RHS, <6,4,4,4> + 3383153293U, // <7,6,4,5>: Cost 3 vsldoi12 RHS, <6,4,5,6> + 3524055864U, // <7,6,4,6>: Cost 3 vmrglw <5,6,7,4>, <6,6,6,6> + 2450312502U, // <7,6,4,7>: Cost 2 vmrglw <5,6,7,4>, RHS + 2450312503U, // <7,6,4,u>: Cost 2 vmrglw <5,6,7,4>, RHS + 3383153324U, // <7,6,5,0>: Cost 4 vsldoi12 RHS, <6,5,0,1> + 3365532344U, // <7,6,5,1>: Cost 5 vsldoi12 <1,6,1,7>, <6,5,1,4> + 3383153347U, // <7,6,5,2>: Cost 4 vsldoi12 RHS, <6,5,2,6> + 3383153356U, // <7,6,5,3>: Cost 4 vsldoi12 RHS, <6,5,3,6> + 3383153364U, // <7,6,5,4>: Cost 4 vsldoi12 RHS, <6,5,4,5> + 3512117041U, // <7,6,5,5>: Cost 4 vmrglw <3,6,7,5>, <2,4,6,5> + 3255636072U, // <7,6,5,6>: Cost 3 vsldoi8 <5,6,7,6>, <5,6,7,6> + 3383153387U, // <7,6,5,7>: Cost 3 vsldoi12 RHS, <6,5,7,1> + 3383300852U, // <7,6,5,u>: Cost 3 vsldoi12 RHS, <6,5,u,1> + 4201717862U, // <7,6,6,0>: Cost 3 vsldoi4 <6,7,6,6>, LHS + 3383153414U, // <7,6,6,1>: Cost 4 vsldoi12 RHS, <6,6,1,1> + 3255636474U, // <7,6,6,2>: Cost 3 vsldoi8 <5,6,7,6>, <6,2,7,3> + 4183804670U, // <7,6,6,3>: Cost 4 vsldoi4 <3,7,6,6>, <3,7,6,6> + 4201721142U, // <7,6,6,4>: Cost 3 vsldoi4 <6,7,6,6>, RHS + 3260945136U, // <7,6,6,5>: Cost 3 vsldoi8 <6,5,7,6>, <6,5,7,6> + 3383153464U, // <7,6,6,6>: Cost 2 vsldoi12 RHS, <6,6,6,6> + 3383153474U, // <7,6,6,7>: Cost 2 vsldoi12 RHS, <6,6,7,7> + 3383300939U, // <7,6,6,u>: Cost 2 vsldoi12 RHS, <6,6,u,7> + 3383153486U, // <7,6,7,0>: Cost 2 vsldoi12 RHS, <6,7,0,1> + 3383153495U, // <7,6,7,1>: Cost 3 vsldoi12 RHS, <6,7,1,1> + 3383153505U, // <7,6,7,2>: Cost 3 vsldoi12 RHS, <6,7,2,2> + 3383153512U, // <7,6,7,3>: Cost 3 vsldoi12 RHS, <6,7,3,0> + 3383153526U, // <7,6,7,4>: Cost 2 vsldoi12 RHS, <6,7,4,5> + 3383153535U, // <7,6,7,5>: Cost 3 vsldoi12 RHS, <6,7,5,5> + 3383153541U, // <7,6,7,6>: Cost 3 vsldoi12 RHS, <6,7,6,2> + 2456309046U, // <7,6,7,7>: Cost 2 vmrglw <6,6,7,7>, RHS + 3383153558U, // <7,6,7,u>: Cost 2 vsldoi12 RHS, <6,7,u,1> + 3383301023U, // <7,6,u,0>: Cost 2 vsldoi12 RHS, <6,u,0,1> + 3383153577U, // <7,6,u,1>: Cost 3 vsldoi12 RHS, <6,u,1,2> + 3383301042U, // <7,6,u,2>: Cost 3 vsldoi12 RHS, <6,u,2,2> + 3383301049U, // <7,6,u,3>: Cost 3 vsldoi12 RHS, <6,u,3,0> + 3383301063U, // <7,6,u,4>: Cost 2 vsldoi12 RHS, <6,u,4,5> + 3383153617U, // <7,6,u,5>: Cost 3 vsldoi12 RHS, <6,u,5,6> + 3383153464U, // <7,6,u,6>: Cost 2 vsldoi12 RHS, <6,6,6,6> + 3383153632U, // <7,6,u,7>: Cost 2 vsldoi12 RHS, <6,u,7,3> + 3383301095U, // <7,6,u,u>: Cost 2 vsldoi12 RHS, <6,u,u,1> + 2450280546U, // <7,7,0,0>: Cost 2 vmrglw <5,6,7,0>, <5,6,7,0> + 3383153658U, // <7,7,0,1>: Cost 2 vsldoi12 RHS, <7,0,1,2> + 3371652098U, // <7,7,0,2>: Cost 4 vsldoi12 <2,6,3,7>, <7,0,2,1> + 3524022778U, // <7,7,0,3>: Cost 3 vmrglw <5,6,7,0>, <6,2,7,3> + 3383153684U, // <7,7,0,4>: Cost 3 vsldoi12 RHS, <7,0,4,1> + 4201746530U, // <7,7,0,5>: Cost 3 vsldoi4 <6,7,7,0>, <5,6,7,0> + 4201747340U, // <7,7,0,6>: Cost 3 vsldoi4 <6,7,7,0>, <6,7,7,0> + 3524023106U, // <7,7,0,7>: Cost 3 vmrglw <5,6,7,0>, <6,6,7,7> + 3383153721U, // <7,7,0,u>: Cost 2 vsldoi12 RHS, <7,0,u,2> + 3383153729U, // <7,7,1,0>: Cost 4 vsldoi12 RHS, <7,1,0,1> + 3383153738U, // <7,7,1,1>: Cost 3 vsldoi12 RHS, <7,1,1,1> + 3383153749U, // <7,7,1,2>: Cost 3 vsldoi12 RHS, <7,1,2,3> + 3524030970U, // <7,7,1,3>: Cost 4 vmrglw <5,6,7,1>, <6,2,7,3> + 3383153765U, // <7,7,1,4>: Cost 4 vsldoi12 RHS, <7,1,4,1> + 3383153773U, // <7,7,1,5>: Cost 4 vsldoi12 RHS, <7,1,5,0> + 3365532791U, // <7,7,1,6>: Cost 4 vsldoi12 <1,6,1,7>, <7,1,6,1> + 3537303148U, // <7,7,1,7>: Cost 3 vmrglw <7,u,7,1>, <7,7,7,7> + 3383153803U, // <7,7,1,u>: Cost 3 vsldoi12 RHS, <7,1,u,3> + 3407041684U, // <7,7,2,0>: Cost 3 vsldoi12 RHS, <7,2,0,3> + 3383153821U, // <7,7,2,1>: Cost 4 vsldoi12 RHS, <7,2,1,3> + 3383153829U, // <7,7,2,2>: Cost 3 vsldoi12 RHS, <7,2,2,2> + 3383153836U, // <7,7,2,3>: Cost 3 vsldoi12 RHS, <7,2,3,0> + 3407041720U, // <7,7,2,4>: Cost 3 vsldoi12 RHS, <7,2,4,3> + 3383153857U, // <7,7,2,5>: Cost 4 vsldoi12 RHS, <7,2,5,3> + 3371652298U, // <7,7,2,6>: Cost 3 vsldoi12 <2,6,3,7>, <7,2,6,3> + 3395835091U, // <7,7,2,7>: Cost 3 vsldoi12 <6,6,7,7>, <7,2,7,3> + 3372979420U, // <7,7,2,u>: Cost 3 vsldoi12 <2,u,3,7>, <7,2,u,3> + 3383153891U, // <7,7,3,0>: Cost 3 vsldoi12 RHS, <7,3,0,1> + 3383153900U, // <7,7,3,1>: Cost 4 vsldoi12 RHS, <7,3,1,1> + 3371652346U, // <7,7,3,2>: Cost 4 vsldoi12 <2,6,3,7>, <7,3,2,6> + 2453623290U, // <7,7,3,3>: Cost 2 vmrglw <6,2,7,3>, <6,2,7,3> + 3383153931U, // <7,7,3,4>: Cost 3 vsldoi12 RHS, <7,3,4,5> + 3383153940U, // <7,7,3,5>: Cost 4 vsldoi12 RHS, <7,3,5,5> + 3243698871U, // <7,7,3,6>: Cost 3 vsldoi8 <3,6,7,7>, <3,6,7,7> + 3527365442U, // <7,7,3,7>: Cost 3 vmrglw <6,2,7,3>, <6,6,7,7> + 2453623290U, // <7,7,3,u>: Cost 2 vmrglw <6,2,7,3>, <6,2,7,3> + 3383153976U, // <7,7,4,0>: Cost 3 vsldoi12 RHS, <7,4,0,5> + 3383153982U, // <7,7,4,1>: Cost 4 vsldoi12 RHS, <7,4,1,2> + 4183861178U, // <7,7,4,2>: Cost 4 vsldoi4 <3,7,7,4>, <2,6,3,7> + 3524055546U, // <7,7,4,3>: Cost 3 vmrglw <5,6,7,4>, <6,2,7,3> + 2450313318U, // <7,7,4,4>: Cost 2 vmrglw <5,6,7,4>, <5,6,7,4> + 3383154022U, // <7,7,4,5>: Cost 2 vsldoi12 RHS, <7,4,5,6> + 4201780112U, // <7,7,4,6>: Cost 3 vsldoi4 <6,7,7,4>, <6,7,7,4> + 3524055874U, // <7,7,4,7>: Cost 3 vmrglw <5,6,7,4>, <6,6,7,7> + 3383154049U, // <7,7,4,u>: Cost 2 vsldoi12 RHS, <7,4,u,6> + 3383154053U, // <7,7,5,0>: Cost 4 vsldoi12 RHS, <7,5,0,1> + 3385144717U, // <7,7,5,1>: Cost 4 vsldoi12 RHS, <7,5,1,0> + 3383154073U, // <7,7,5,2>: Cost 4 vsldoi12 RHS, <7,5,2,3> + 3524063738U, // <7,7,5,3>: Cost 4 vmrglw <5,6,7,5>, <6,2,7,3> + 3383154093U, // <7,7,5,4>: Cost 4 vsldoi12 RHS, <7,5,4,5> + 3383154102U, // <7,7,5,5>: Cost 3 vsldoi12 RHS, <7,5,5,5> + 3383154113U, // <7,7,5,6>: Cost 3 vsldoi12 RHS, <7,5,6,7> + 3537335916U, // <7,7,5,7>: Cost 3 vmrglw <7,u,7,5>, <7,7,7,7> + 3383301587U, // <7,7,5,u>: Cost 3 vsldoi12 RHS, <7,5,u,7> + 4201791590U, // <7,7,6,0>: Cost 3 vsldoi4 <6,7,7,6>, LHS + 3383154149U, // <7,7,6,1>: Cost 4 vsldoi12 RHS, <7,6,1,7> + 3383154158U, // <7,7,6,2>: Cost 3 vsldoi12 RHS, <7,6,2,7> + 3524071930U, // <7,7,6,3>: Cost 3 vmrglw <5,6,7,6>, <6,2,7,3> + 4201794870U, // <7,7,6,4>: Cost 3 vsldoi4 <6,7,7,6>, RHS + 3383154185U, // <7,7,6,5>: Cost 4 vsldoi12 RHS, <7,6,5,7> + 3261616962U, // <7,7,6,6>: Cost 2 vsldoi8 <6,6,7,7>, <6,6,7,7> + 3383154196U, // <7,7,6,7>: Cost 3 vsldoi12 RHS, <7,6,7,0> + 3262944228U, // <7,7,6,u>: Cost 2 vsldoi8 <6,u,7,7>, <6,u,7,7> + 3134029926U, // <7,7,7,0>: Cost 2 vsldoi4 <7,7,7,7>, LHS + 3536688175U, // <7,7,7,1>: Cost 3 vmrglw <7,7,7,7>, <7,0,7,1> + 3261617363U, // <7,7,7,2>: Cost 3 vsldoi8 <6,6,7,7>, <7,2,7,3> + 3530052090U, // <7,7,7,3>: Cost 3 vmrglw <6,6,7,7>, <6,2,7,3> + 3134033206U, // <7,7,7,4>: Cost 2 vsldoi4 <7,7,7,7>, RHS + 3536688503U, // <7,7,7,5>: Cost 3 vmrglw <7,7,7,7>, <7,4,7,5> + 3261617682U, // <7,7,7,6>: Cost 3 vsldoi8 <6,6,7,7>, <7,6,6,7> + 1906756918U, // <7,7,7,7>: Cost 1 vspltisw3 RHS + 1906756918U, // <7,7,7,u>: Cost 1 vspltisw3 RHS + 2450280546U, // <7,7,u,0>: Cost 2 vmrglw <5,6,7,0>, <5,6,7,0> + 3383301762U, // <7,7,u,1>: Cost 2 vsldoi12 RHS, <7,u,1,2> + 3383301772U, // <7,7,u,2>: Cost 3 vsldoi12 RHS, <7,u,2,3> + 2453623290U, // <7,7,u,3>: Cost 2 vmrglw <6,2,7,3>, <6,2,7,3> + 2450313318U, // <7,7,u,4>: Cost 2 vmrglw <5,6,7,4>, <5,6,7,4> + 3383301802U, // <7,7,u,5>: Cost 2 vsldoi12 RHS, <7,u,5,6> + 3273562356U, // <7,7,u,6>: Cost 2 vsldoi8 , + 1906756918U, // <7,7,u,7>: Cost 1 vspltisw3 RHS + 1906756918U, // <7,7,u,u>: Cost 1 vspltisw3 RHS + 3383148544U, // <7,u,0,0>: Cost 2 vsldoi12 RHS, <0,0,0,0> + 3383154387U, // <7,u,0,1>: Cost 2 vsldoi12 RHS, + 3524020437U, // <7,u,0,2>: Cost 3 vmrglw <5,6,7,0>, <3,0,u,2> + 2450276508U, // <7,u,0,3>: Cost 2 vmrglw <5,6,7,0>, LHS + 3383154413U, // <7,u,0,4>: Cost 3 vsldoi12 RHS, + 2323601562U, // <7,u,0,5>: Cost 2 vmrghw <7,0,1,2>, RHS + 3524020765U, // <7,u,0,6>: Cost 3 vmrglw <5,6,7,0>, <3,4,u,6> + 2450279752U, // <7,u,0,7>: Cost 2 vmrglw <5,6,7,0>, RHS + 3383154450U, // <7,u,0,u>: Cost 2 vsldoi12 RHS, + 3128082534U, // <7,u,1,0>: Cost 2 vsldoi4 <6,7,u,1>, LHS + 3383149364U, // <7,u,1,1>: Cost 2 vsldoi12 RHS, <1,1,1,1> + 1235670830U, // <7,u,1,2>: Cost 1 vsldoi12 RHS, LHS + 4183911179U, // <7,u,1,3>: Cost 3 vsldoi4 <3,7,u,1>, <3,7,u,1> + 3128085814U, // <7,u,1,4>: Cost 2 vsldoi4 <6,7,u,1>, RHS + 3383154502U, // <7,u,1,5>: Cost 3 vsldoi12 RHS, + 3128087446U, // <7,u,1,6>: Cost 2 vsldoi4 <6,7,u,1>, <6,7,u,1> + 3383301977U, // <7,u,1,7>: Cost 3 vsldoi12 RHS, + 1235670884U, // <7,u,1,u>: Cost 1 vsldoi12 RHS, LHS + 3383154539U, // <7,u,2,0>: Cost 3 vsldoi12 RHS, + 3383154550U, // <7,u,2,1>: Cost 3 vsldoi12 RHS, + 3383150184U, // <7,u,2,2>: Cost 2 vsldoi12 RHS, <2,2,2,2> + 3383154565U, // <7,u,2,3>: Cost 2 vsldoi12 RHS, + 3383154577U, // <7,u,2,4>: Cost 3 vsldoi12 RHS, + 3383154586U, // <7,u,2,5>: Cost 3 vsldoi12 RHS, + 3371653027U, // <7,u,2,6>: Cost 3 vsldoi12 <2,6,3,7>, + 3383302060U, // <7,u,2,7>: Cost 2 vsldoi12 RHS, + 3383154610U, // <7,u,2,u>: Cost 2 vsldoi12 RHS, + 3383154620U, // <7,u,3,0>: Cost 2 vsldoi12 RHS, + 3383154629U, // <7,u,3,1>: Cost 3 vsldoi12 RHS, + 3371653075U, // <7,u,3,2>: Cost 3 vsldoi12 <2,6,3,7>, + 2453618844U, // <7,u,3,3>: Cost 2 vmrglw <6,2,7,3>, LHS + 3383154660U, // <7,u,3,4>: Cost 2 vsldoi12 RHS, + 3383154669U, // <7,u,3,5>: Cost 3 vsldoi12 RHS, + 3243707064U, // <7,u,3,6>: Cost 3 vsldoi8 <3,6,7,u>, <3,6,7,u> + 2453622088U, // <7,u,3,7>: Cost 2 vmrglw <6,2,7,3>, RHS + 3383154692U, // <7,u,3,u>: Cost 2 vsldoi12 RHS, + 3383154701U, // <7,u,4,0>: Cost 3 vsldoi12 RHS, + 2326583086U, // <7,u,4,1>: Cost 2 vmrghw <7,4,5,6>, LHS + 3524053205U, // <7,u,4,2>: Cost 3 vmrglw <5,6,7,4>, <3,0,u,2> + 2450309276U, // <7,u,4,3>: Cost 2 vmrglw <5,6,7,4>, LHS + 3383151824U, // <7,u,4,4>: Cost 2 vsldoi12 RHS, <4,4,4,4> + 3383154751U, // <7,u,4,5>: Cost 2 vsldoi12 RHS, + 3524053533U, // <7,u,4,6>: Cost 3 vmrglw <5,6,7,4>, <3,4,u,6> + 2450312520U, // <7,u,4,7>: Cost 2 vmrglw <5,6,7,4>, RHS + 3383154778U, // <7,u,4,u>: Cost 2 vsldoi12 RHS, + 3128115302U, // <7,u,5,0>: Cost 2 vsldoi4 <6,7,u,5>, LHS + 3385145446U, // <7,u,5,1>: Cost 3 vsldoi12 RHS, + 4183943098U, // <7,u,5,2>: Cost 3 vsldoi4 <3,7,u,5>, <2,6,3,7> + 4183943951U, // <7,u,5,3>: Cost 3 vsldoi4 <3,7,u,5>, <3,7,u,5> + 3128118582U, // <7,u,5,4>: Cost 2 vsldoi4 <6,7,u,5>, RHS + 3383152644U, // <7,u,5,5>: Cost 2 vsldoi12 RHS, <5,5,5,5> + 1235671194U, // <7,u,5,6>: Cost 1 vsldoi12 RHS, RHS + 3383302301U, // <7,u,5,7>: Cost 3 vsldoi12 RHS, + 1235671212U, // <7,u,5,u>: Cost 1 vsldoi12 RHS, RHS + 3383154863U, // <7,u,6,0>: Cost 3 vsldoi12 RHS, + 3383154878U, // <7,u,6,1>: Cost 3 vsldoi12 RHS, + 3258970623U, // <7,u,6,2>: Cost 2 vsldoi8 <6,2,7,u>, <6,2,7,u> + 3383154896U, // <7,u,6,3>: Cost 2 vsldoi12 RHS, + 3383154903U, // <7,u,6,4>: Cost 3 vsldoi12 RHS, + 3383154914U, // <7,u,6,5>: Cost 3 vsldoi12 RHS, + 3261625155U, // <7,u,6,6>: Cost 2 vsldoi8 <6,6,7,u>, <6,6,7,u> + 3383302388U, // <7,u,6,7>: Cost 2 vsldoi12 RHS, + 3383154941U, // <7,u,6,u>: Cost 2 vsldoi12 RHS, + 3383302400U, // <7,u,7,0>: Cost 2 vsldoi12 RHS, + 2328729390U, // <7,u,7,1>: Cost 2 vmrghw <7,7,7,7>, LHS + 3372022039U, // <7,u,7,2>: Cost 3 vsldoi12 <2,6,u,7>, + 2456305820U, // <7,u,7,3>: Cost 2 vmrglw <6,6,7,7>, LHS + 3383302440U, // <7,u,7,4>: Cost 2 vsldoi12 RHS, + 2328729754U, // <7,u,7,5>: Cost 2 vmrghw <7,7,7,7>, RHS + 3383302455U, // <7,u,7,6>: Cost 3 vsldoi12 RHS, + 1906756918U, // <7,u,7,7>: Cost 1 vspltisw3 RHS + 1906756918U, // <7,u,7,u>: Cost 1 vspltisw3 RHS + 3383155025U, // <7,u,u,0>: Cost 2 vsldoi12 RHS, + 3383155035U, // <7,u,u,1>: Cost 2 vsldoi12 RHS, + 1235671397U, // <7,u,u,2>: Cost 1 vsldoi12 RHS, LHS + 3383155051U, // <7,u,u,3>: Cost 2 vsldoi12 RHS, + 3383155065U, // <7,u,u,4>: Cost 2 vsldoi12 RHS, + 3383155075U, // <7,u,u,5>: Cost 2 vsldoi12 RHS, + 1235671437U, // <7,u,u,6>: Cost 1 vsldoi12 RHS, RHS + 1906756918U, // <7,u,u,7>: Cost 1 vspltisw3 RHS + 1235671451U, // <7,u,u,u>: Cost 1 vsldoi12 RHS, LHS + 1477230694U, // : Cost 1 vspltisw0 LHS + 3356319754U, // : Cost 2 vsldoi12 LHS, <0,0,1,1> + 4178004026U, // : Cost 3 vsldoi4 <2,u,0,0>, <2,u,0,0> + 3497555821U, // : Cost 3 vmrglw <1,2,u,0>, + 3092319542U, // : Cost 2 vsldoi4 <0,u,0,0>, RHS + 4207202402U, // : Cost 3 vsldoi4 <7,7,0,0>, <5,6,7,0> + 4201894814U, // : Cost 3 vsldoi4 <6,u,0,0>, <6,u,0,0> + 3497556149U, // : Cost 3 vmrglw <1,2,u,0>, + 1477230694U, // : Cost 1 vspltisw0 LHS + 3104268390U, // : Cost 2 vsldoi4 <2,u,0,1>, LHS + 1256570982U, // : Cost 1 vmrghw LHS, LHS + 1208836203U, // : Cost 1 vsldoi12 LHS, LHS + 4178012310U, // : Cost 3 vsldoi4 <2,u,0,1>, <3,0,1,2> + 3104271670U, // : Cost 2 vsldoi4 <2,u,0,1>, RHS + 4195930310U, // : Cost 3 vsldoi4 <5,u,0,1>, <5,u,0,1> + 3128161183U, // : Cost 2 vsldoi4 <6,u,0,1>, <6,u,0,1> + 4201903098U, // : Cost 3 vsldoi4 <6,u,0,1>, <7,0,1,2> + 1208836252U, // : Cost 1 vsldoi12 LHS, LHS + 3233760762U, // : Cost 3 vsldoi8 <2,0,u,0>, <2,0,u,0> + 2331025510U, // : Cost 2 vmrghw , LHS + 3229116008U, // : Cost 3 vsldoi8 <1,2,u,0>, <2,2,2,2> + 3229116070U, // : Cost 3 vsldoi8 <1,2,u,0>, <2,3,0,1> + 3404767570U, // : Cost 3 vmrghw , <0,4,1,5> + 3507669460U, // : Cost 3 vmrglw <3,0,1,2>, <3,4,0,5> + 3229116346U, // : Cost 3 vsldoi8 <1,2,u,0>, <2,6,3,7> + 3238406193U, // : Cost 3 vsldoi8 <2,7,u,0>, <2,7,u,0> + 2331026077U, // : Cost 2 vmrghw , LHS + 2417197056U, // : Cost 2 vmrglw LHS, <0,0,0,0> + 2417198758U, // : Cost 2 vmrglw LHS, <2,3,0,1> + 3241060725U, // : Cost 3 vsldoi8 <3,2,u,0>, <3,2,u,0> + 3229116828U, // : Cost 3 vsldoi8 <1,2,u,0>, <3,3,3,3> + 3490940585U, // : Cost 3 vmrglw LHS, <2,3,0,4> + 4207890530U, // : Cost 3 vsldoi4 <7,u,0,3>, <5,6,7,0> + 3228748408U, // : Cost 3 vsldoi8 <1,2,3,0>, <3,6,0,7> + 4207892090U, // : Cost 3 vsldoi4 <7,u,0,3>, <7,u,0,3> + 2417198765U, // : Cost 2 vmrglw LHS, <2,3,0,u> + 3497582592U, // : Cost 3 vmrglw <1,2,u,4>, <0,0,0,0> + 3356320082U, // : Cost 2 vsldoi12 LHS, <0,4,1,5> + 4178036798U, // : Cost 3 vsldoi4 <2,u,0,4>, <2,u,0,4> + 3376431360U, // : Cost 3 vmrghw <3,4,5,6>, <0,3,1,4> + 2284470610U, // : Cost 2 vmrghw <0,4,1,5>, <0,4,1,5> + 3229117750U, // : Cost 2 vsldoi8 <1,2,u,0>, RHS + 4201927586U, // : Cost 3 vsldoi4 <6,u,0,4>, <6,u,0,4> + 3250130376U, // : Cost 3 vsldoi8 <4,7,5,0>, <4,7,5,0> + 3360965009U, // : Cost 2 vsldoi12 LHS, <0,4,u,5> + 2333294592U, // : Cost 2 vmrghw RHS, <0,0,0,0> + 1259552870U, // : Cost 1 vmrghw RHS, LHS + 3407036589U, // : Cost 3 vmrghw RHS, <0,2,1,2> + 4184017688U, // : Cost 3 vsldoi4 <3,u,0,5>, <3,u,0,5> + 2333294930U, // : Cost 2 vmrghw RHS, <0,4,1,5> + 3255660548U, // : Cost 3 vsldoi8 <5,6,u,0>, <5,5,5,5> + 3255660651U, // : Cost 2 vsldoi8 <5,6,u,0>, <5,6,u,0> + 4207908476U, // : Cost 3 vsldoi4 <7,u,0,5>, <7,u,0,5> + 1259553437U, // : Cost 1 vmrghw RHS, LHS + 3510870016U, // : Cost 3 vmrglw <3,4,u,6>, <0,0,0,0> + 2333737062U, // : Cost 2 vmrghw , LHS + 3255661050U, // : Cost 3 vsldoi8 <5,6,u,0>, <6,2,7,3> + 3259642449U, // : Cost 3 vsldoi8 <6,3,u,0>, <6,3,u,0> + 3407479122U, // : Cost 3 vmrghw , <0,4,1,5> + 3389800868U, // : Cost 3 vmrghw <5,6,7,0>, <0,5,1,6> + 3255661368U, // : Cost 3 vsldoi8 <5,6,u,0>, <6,6,6,6> + 3255661390U, // : Cost 3 vsldoi8 <5,6,u,0>, <6,7,0,1> + 2333737629U, // : Cost 2 vmrghw , LHS + 2443771904U, // : Cost 2 vmrglw RHS, <0,0,0,0> + 2443773606U, // : Cost 2 vmrglw RHS, <2,3,0,1> + 3264951513U, // : Cost 3 vsldoi8 <7,2,u,0>, <7,2,u,0> + 4184034074U, // : Cost 3 vsldoi4 <3,u,0,7>, <3,u,0,7> + 4184034614U, // : Cost 3 vsldoi4 <3,u,0,7>, RHS + 3517516244U, // : Cost 3 vmrglw RHS, <3,4,0,5> + 3267606045U, // : Cost 3 vsldoi8 <7,6,u,0>, <7,6,u,0> + 3517516408U, // : Cost 3 vmrglw RHS, <3,6,0,7> + 2443773613U, // : Cost 2 vmrglw RHS, <2,3,0,u> + 1477230694U, // : Cost 1 vspltisw0 LHS + 1261215846U, // : Cost 1 vmrghw LHS, LHS + 1208836765U, // : Cost 1 vsldoi12 LHS, LHS + 3229120444U, // : Cost 3 vsldoi8 <1,2,u,0>, + 3104329014U, // : Cost 2 vsldoi4 <2,u,0,u>, RHS + 3229120666U, // : Cost 2 vsldoi8 <1,2,u,0>, RHS + 3128218534U, // : Cost 2 vsldoi4 <6,u,0,u>, <6,u,0,u> + 3517524600U, // : Cost 3 vmrglw RHS, <3,6,0,7> + 1208836819U, // : Cost 1 vsldoi12 LHS, LHS + 3221823561U, // : Cost 2 vsldoi8 <0,0,u,1>, <0,0,u,1> + 3227132006U, // : Cost 2 vsldoi8 <0,u,u,1>, LHS + 3495565011U, // : Cost 3 vmrglw <0,u,u,0>, + 4184050460U, // : Cost 3 vsldoi4 <3,u,1,0>, <3,u,1,0> + 4166135094U, // : Cost 3 vsldoi4 <0,u,1,0>, RHS + 3497550162U, // : Cost 3 vmrglw <1,2,u,0>, <0,4,1,5> + 4207940502U, // : Cost 3 vsldoi4 <7,u,1,0>, <6,7,u,1> + 4207941248U, // : Cost 3 vsldoi4 <7,u,1,0>, <7,u,1,0> + 3227132625U, // : Cost 2 vsldoi8 <0,u,u,1>, <0,u,u,1> + 3092398738U, // : Cost 2 vsldoi4 <0,u,1,1>, <0,u,1,1> + 1611448422U, // : Cost 1 vspltisw1 LHS + 2330313622U, // : Cost 2 vmrghw LHS, <1,2,3,0> + 4166142102U, // : Cost 3 vsldoi4 <0,u,1,1>, <3,0,1,2> + 3092401462U, // : Cost 2 vsldoi4 <0,u,1,1>, RHS + 3360965468U, // : Cost 3 vsldoi12 LHS, <1,1,5,5> + 4201976744U, // : Cost 3 vsldoi4 <6,u,1,1>, <6,u,1,1> + 3495573694U, // : Cost 3 vmrglw <0,u,u,1>, + 1611448422U, // : Cost 1 vspltisw1 LHS + 3110322278U, // : Cost 2 vsldoi4 <3,u,1,2>, LHS + 3360965511U, // : Cost 3 vsldoi12 LHS, <1,2,1,3> + 2289222550U, // : Cost 2 vmrghw <1,2,3,0>, <1,2,3,0> 835584U, // : Cost 0 copy LHS - 2976107830U, // : Cost 2 vsldoi4 <3,u,1,2>, RHS - 3226747819U, // : Cost 3 vsldoi12 LHS, <1,2,5,3> - 4166657978U, // : Cost 3 vsldoi8 <0,u,u,1>, <2,6,3,7> - 2999998082U, // : Cost 2 vsldoi4 <7,u,1,2>, <7,u,1,2> + 3110325558U, // : Cost 2 vsldoi4 <3,u,1,2>, RHS + 3360965547U, // : Cost 3 vsldoi12 LHS, <1,2,5,3> + 3227133882U, // : Cost 3 vsldoi8 <0,u,u,1>, <2,6,3,7> + 3134215810U, // : Cost 2 vsldoi4 <7,u,1,2>, <7,u,1,2> 835584U, // : Cost 0 copy LHS - 3356721161U, // : Cost 3 vmrglw LHS, <0,0,1,0> - 2282979338U, // : Cost 2 vmrglw LHS, <0,0,1,1> - 2282981526U, // : Cost 2 vmrglw LHS, <3,0,1,2> - 3356721326U, // : Cost 3 vmrglw LHS, <0,2,1,3> - 3356721165U, // : Cost 3 vmrglw LHS, <0,0,1,4> - 2282979666U, // : Cost 2 vmrglw LHS, <0,4,1,5> - 3356721329U, // : Cost 3 vmrglw LHS, <0,2,1,6> - 3361367247U, // : Cost 3 vmrglw LHS, <1,6,1,7> - 2282979345U, // : Cost 2 vmrglw LHS, <0,0,1,u> - 3111496621U, // : Cost 2 vsldoi8 <4,0,u,1>, <4,0,u,1> - 3363364874U, // : Cost 3 vmrglw <1,2,u,4>, <0,0,1,1> - 3363367062U, // : Cost 3 vmrglw <1,2,u,4>, <3,0,1,2> - 4049865504U, // : Cost 3 vsldoi4 <3,u,1,4>, <3,u,1,4> - 4031950134U, // : Cost 3 vsldoi4 <0,u,1,4>, RHS - 3092917558U, // : Cost 2 vsldoi8 <0,u,u,1>, RHS - 4073755542U, // : Cost 3 vsldoi4 <7,u,1,4>, <6,7,u,1> - 4073756292U, // : Cost 3 vsldoi4 <7,u,1,4>, <7,u,1,4> - 3092917801U, // : Cost 2 vsldoi8 <0,u,u,1>, RHS - 2958213782U, // : Cost 2 vsldoi4 <0,u,1,5>, <0,u,1,5> - 2199077684U, // : Cost 2 vmrghw RHS, <1,1,1,1> - 2199077782U, // : Cost 2 vmrghw RHS, <1,2,3,0> - 4031957142U, // : Cost 3 vsldoi4 <0,u,1,5>, <3,0,1,2> - 2958216502U, // : Cost 2 vsldoi4 <0,u,1,5>, RHS - 2284470610U, // : Cost 2 vmrglw <0,4,1,5>, <0,4,1,5> - 4190548066U, // : Cost 3 vsldoi8 <4,u,u,1>, <5,6,7,0> - 4079735802U, // : Cost 3 vsldoi4 , <7,0,1,2> - 2958219054U, // : Cost 2 vsldoi4 <0,u,1,5>, LHS - 4031963799U, // : Cost 3 vsldoi4 <0,u,1,6>, <0,u,1,6> - 3226748111U, // : Cost 3 vsldoi12 LHS, <1,6,1,7> - 3376654486U, // : Cost 3 vmrglw <3,4,u,6>, <3,0,1,2> - 4031965334U, // : Cost 4 vsldoi4 <0,u,1,6>, <3,0,1,2> - 4031966518U, // : Cost 3 vsldoi4 <0,u,1,6>, RHS - 3226748147U, // : Cost 3 vsldoi12 LHS, <1,6,5,7> - 4190548792U, // : Cost 3 vsldoi8 <4,u,u,1>, <6,6,6,6> - 3128087446U, // : Cost 2 vsldoi8 <6,7,u,1>, <6,7,u,1> - 3128751079U, // : Cost 2 vsldoi8 <6,u,u,1>, <6,u,u,1> - 4037943398U, // : Cost 3 vsldoi4 <1,u,1,7>, LHS - 2309554186U, // : Cost 2 vmrglw RHS, <0,0,1,1> - 2309556374U, // : Cost 2 vmrglw RHS, <3,0,1,2> - 3383296174U, // : Cost 3 vmrglw RHS, <0,2,1,3> - 4037946678U, // : Cost 3 vsldoi4 <1,u,1,7>, RHS - 2309554514U, // : Cost 2 vmrglw RHS, <0,4,1,5> - 3383296177U, // : Cost 3 vmrglw RHS, <0,2,1,6> - 3383296502U, // : Cost 3 vmrglw RHS, <0,6,1,7> - 2309554193U, // : Cost 2 vmrglw RHS, <0,0,1,u> - 2958238361U, // : Cost 2 vsldoi4 <0,u,1,u>, <0,u,1,u> - 1477230694U, // : Cost 1 vspltisw1 LHS - 2283022486U, // : Cost 2 vmrglw LHS, <3,0,1,2> + 3490938889U, // : Cost 3 vmrglw LHS, <0,0,1,0> + 2417197066U, // : Cost 2 vmrglw LHS, <0,0,1,1> + 2417199254U, // : Cost 2 vmrglw LHS, <3,0,1,2> + 3490939054U, // : Cost 3 vmrglw LHS, <0,2,1,3> + 3490938893U, // : Cost 3 vmrglw LHS, <0,0,1,4> + 2417197394U, // : Cost 2 vmrglw LHS, <0,4,1,5> + 3490939057U, // : Cost 3 vmrglw LHS, <0,2,1,6> + 3495584975U, // : Cost 3 vmrglw LHS, <1,6,1,7> + 2417197073U, // : Cost 2 vmrglw LHS, <0,0,1,u> + 3245714349U, // : Cost 2 vsldoi8 <4,0,u,1>, <4,0,u,1> + 3497582602U, // : Cost 3 vmrglw <1,2,u,4>, <0,0,1,1> + 3497584790U, // : Cost 3 vmrglw <1,2,u,4>, <3,0,1,2> + 4184083232U, // : Cost 3 vsldoi4 <3,u,1,4>, <3,u,1,4> + 4166167862U, // : Cost 3 vsldoi4 <0,u,1,4>, RHS + 3227135286U, // : Cost 2 vsldoi8 <0,u,u,1>, RHS + 4207973270U, // : Cost 3 vsldoi4 <7,u,1,4>, <6,7,u,1> + 4207974020U, // : Cost 3 vsldoi4 <7,u,1,4>, <7,u,1,4> + 3227135529U, // : Cost 2 vsldoi8 <0,u,u,1>, RHS + 3092431510U, // : Cost 2 vsldoi4 <0,u,1,5>, <0,u,1,5> + 2333295412U, // : Cost 2 vmrghw RHS, <1,1,1,1> + 2333295510U, // : Cost 2 vmrghw RHS, <1,2,3,0> + 4166174870U, // : Cost 3 vsldoi4 <0,u,1,5>, <3,0,1,2> + 3092434230U, // : Cost 2 vsldoi4 <0,u,1,5>, RHS + 2418688338U, // : Cost 2 vmrglw <0,4,1,5>, <0,4,1,5> + 3251023970U, // : Cost 3 vsldoi8 <4,u,u,1>, <5,6,7,0> + 4213953530U, // : Cost 3 vsldoi4 , <7,0,1,2> + 3092436782U, // : Cost 2 vsldoi4 <0,u,1,5>, LHS + 4166181527U, // : Cost 3 vsldoi4 <0,u,1,6>, <0,u,1,6> + 3360965839U, // : Cost 3 vsldoi12 LHS, <1,6,1,7> + 3510872214U, // : Cost 3 vmrglw <3,4,u,6>, <3,0,1,2> + 4166183062U, // : Cost 4 vsldoi4 <0,u,1,6>, <3,0,1,2> + 4166184246U, // : Cost 3 vsldoi4 <0,u,1,6>, RHS + 3360965875U, // : Cost 3 vsldoi12 LHS, <1,6,5,7> + 3251024696U, // : Cost 3 vsldoi8 <4,u,u,1>, <6,6,6,6> + 3262305174U, // : Cost 2 vsldoi8 <6,7,u,1>, <6,7,u,1> + 3262968807U, // : Cost 2 vsldoi8 <6,u,u,1>, <6,u,u,1> + 4172161126U, // : Cost 3 vsldoi4 <1,u,1,7>, LHS + 2443771914U, // : Cost 2 vmrglw RHS, <0,0,1,1> + 2443774102U, // : Cost 2 vmrglw RHS, <3,0,1,2> + 3517513902U, // : Cost 3 vmrglw RHS, <0,2,1,3> + 4172164406U, // : Cost 3 vsldoi4 <1,u,1,7>, RHS + 2443772242U, // : Cost 2 vmrglw RHS, <0,4,1,5> + 3517513905U, // : Cost 3 vmrglw RHS, <0,2,1,6> + 3517514230U, // : Cost 3 vmrglw RHS, <0,6,1,7> + 2443771921U, // : Cost 2 vmrglw RHS, <0,0,1,u> + 3092456089U, // : Cost 2 vsldoi4 <0,u,1,u>, <0,u,1,u> + 1611448422U, // : Cost 1 vspltisw1 LHS + 2417240214U, // : Cost 2 vmrglw LHS, <3,0,1,2> 835584U, // : Cost 0 copy LHS - 2958241078U, // : Cost 2 vsldoi4 <0,u,1,u>, RHS - 2283020626U, // : Cost 2 vmrglw LHS, <0,4,1,5> - 3356762289U, // : Cost 3 vmrglw LHS, <0,2,1,6> - 3000047240U, // : Cost 2 vsldoi4 <7,u,1,u>, <7,u,1,u> + 3092458806U, // : Cost 2 vsldoi4 <0,u,1,u>, RHS + 2417238354U, // : Cost 2 vmrglw LHS, <0,4,1,5> + 3490980017U, // : Cost 3 vmrglw LHS, <0,2,1,6> + 3134264968U, // : Cost 2 vsldoi4 <7,u,1,u>, <7,u,1,u> 835584U, // : Cost 0 copy LHS - 4179271680U, // : Cost 3 vsldoi8 <3,0,u,2>, <0,0,0,0> - 3105529958U, // : Cost 2 vsldoi8 <3,0,u,2>, LHS - 3363333736U, // : Cost 3 vmrglw <1,2,u,0>, <2,2,2,2> - 2289590374U, // : Cost 2 vmrglw <1,2,u,0>, LHS - 4179272018U, // : Cost 3 vsldoi8 <3,0,u,2>, <0,4,1,5> - 3362964532U, // : Cost 3 vmrglw <1,2,3,0>, <1,4,2,5> - 3248940521U, // : Cost 3 vsldoi12 RHS, <2,0,6,1> - 4202644032U, // : Cost 3 vsldoi8 <7,0,1,2>, <0,7,1,0> - 2289590379U, // : Cost 2 vmrglw <1,2,u,0>, LHS - 4167328547U, // : Cost 3 vsldoi8 <1,0,u,2>, <1,0,u,2> - 4037969268U, // : Cost 3 vsldoi4 <1,u,2,1>, <1,u,2,1> - 2196096616U, // : Cost 2 vmrghw LHS, <2,2,2,2> - 2287607910U, // : Cost 2 vmrglw <0,u,u,1>, LHS - 4037971254U, // : Cost 3 vsldoi4 <1,u,2,1>, RHS - 3269838696U, // : Cost 3 vmrghw LHS, <2,5,3,6> - 2196096954U, // : Cost 2 vmrghw LHS, <2,6,3,7> - 3269838826U, // : Cost 3 vmrghw LHS, <2,7,0,1> - 2287607915U, // : Cost 2 vmrglw <0,u,u,1>, LHS - 2966224998U, // : Cost 2 vsldoi4 <2,2,2,2>, LHS - 4173964877U, // : Cost 3 vsldoi8 <2,1,u,2>, <2,1,u,2> - 1611448422U, // : Cost 1 vspltisw2 LHS - 3222103666U, // : Cost 2 vsldoi12 LHS, <2,2,3,3> - 2966228278U, // : Cost 2 vsldoi4 <2,2,2,2>, RHS - 3368879885U, // : Cost 3 vmrglw <2,2,2,2>, <2,4,2,5> - 4179273658U, // : Cost 3 vsldoi8 <3,0,u,2>, <2,6,3,7> - 3373971655U, // : Cost 3 vmrglw <3,0,u,2>, - 1611448422U, // : Cost 1 vspltisw2 LHS - 1884529309U, // : Cost 1 vsldoi4 LHS, LHS - 2958271284U, // : Cost 2 vsldoi4 LHS, <1,1,1,1> - 2282980968U, // : Cost 2 vmrglw LHS, <2,2,2,2> - 1209237606U, // : Cost 1 vmrglw LHS, LHS - 1884532022U, // : Cost 1 vsldoi4 LHS, RHS - 3006050308U, // : Cost 2 vsldoi4 LHS, <5,5,5,5> - 3006050810U, // : Cost 2 vsldoi4 LHS, <6,2,7,3> - 3006051322U, // : Cost 2 vsldoi4 LHS, <7,0,1,2> - 1209237611U, // : Cost 1 vmrglw LHS, LHS - 4185246638U, // : Cost 3 vsldoi8 <4,0,u,2>, <4,0,u,2> - 3223995939U, // : Cost 3 vmrghw <0,4,1,5>, <2,1,3,5> - 3363366504U, // : Cost 3 vmrglw <1,2,u,4>, <2,2,2,2> - 2289623142U, // : Cost 2 vmrglw <1,2,u,4>, LHS - 4203162832U, // : Cost 3 vsldoi8 <7,0,u,2>, <4,4,4,4> - 3105533238U, // : Cost 2 vsldoi8 <3,0,u,2>, RHS - 3248940849U, // : Cost 3 vsldoi12 RHS, <2,4,6,5> - 4202646984U, // : Cost 3 vsldoi8 <7,0,1,2>, <4,7,5,0> - 2289623147U, // : Cost 2 vmrglw <1,2,u,4>, LHS - 4038000742U, // : Cost 3 vsldoi4 <1,u,2,5>, LHS - 4038002040U, // : Cost 3 vsldoi4 <1,u,2,5>, <1,u,2,5> - 2199078504U, // : Cost 2 vmrghw RHS, <2,2,2,2> - 2287640678U, // : Cost 2 vmrglw <0,u,u,5>, LHS - 4038004022U, // : Cost 3 vsldoi4 <1,u,2,5>, RHS - 4203163652U, // : Cost 3 vsldoi8 <7,0,u,2>, <5,5,5,5> - 2199078842U, // : Cost 2 vmrghw RHS, <2,6,3,7> - 3272820714U, // : Cost 3 vmrghw RHS, <2,7,0,1> - 2287640683U, // : Cost 2 vmrglw <0,u,u,5>, LHS - 4043980902U, // : Cost 3 vsldoi4 <2,u,2,6>, LHS - 4197855665U, // : Cost 3 vsldoi8 <6,1,u,2>, <6,1,u,2> - 3370681960U, // : Cost 3 vmrglw <2,4,u,6>, <2,2,2,2> - 3222103994U, // : Cost 2 vsldoi12 LHS, <2,6,3,7> - 4043984182U, // : Cost 3 vsldoi4 <2,u,2,6>, RHS - 3370682125U, // : Cost 4 vmrglw <2,4,u,6>, <2,4,2,5> - 2163689402U, // : Cost 2 vmrghw <2,6,3,7>, <2,6,3,7> - 4201837463U, // : Cost 3 vsldoi8 <6,7,u,2>, <6,7,u,2> - 3222104039U, // : Cost 2 vsldoi12 LHS, <2,6,u,7> - 3129422905U, // : Cost 2 vsldoi8 <7,0,u,2>, <7,0,u,2> - 3383296748U, // : Cost 3 vmrglw RHS, <1,0,2,1> - 2309555816U, // : Cost 2 vmrglw RHS, <2,2,2,2> - 1235812454U, // : Cost 1 vmrglw RHS, LHS - 4043992374U, // : Cost 3 vsldoi4 <2,u,2,7>, RHS - 3383297076U, // : Cost 3 vmrglw RHS, <1,4,2,5> - 3383297725U, // : Cost 3 vmrglw RHS, <2,3,2,6> - 3383297240U, // : Cost 3 vmrglw RHS, <1,6,2,7> - 1235812459U, // : Cost 1 vmrglw RHS, LHS - 1884570274U, // : Cost 1 vsldoi4 LHS, LHS - 2958312244U, // : Cost 2 vsldoi4 LHS, <1,1,1,1> - 1611448422U, // : Cost 1 vspltisw2 LHS - 1209278566U, // : Cost 1 vmrglw LHS, LHS - 1884572982U, // : Cost 1 vsldoi4 LHS, RHS - 3105536154U, // : Cost 2 vsldoi8 <3,0,u,2>, RHS - 2200741818U, // : Cost 2 vmrghw LHS, <2,6,3,7> - 3006092282U, // : Cost 2 vsldoi4 LHS, <7,0,1,2> - 1209278571U, // : Cost 1 vmrglw LHS, LHS - 3088285696U, // : Cost 2 vsldoi8 LHS, <0,0,0,0> - 2014544028U, // : Cost 1 vsldoi8 LHS, LHS - 4162027693U, // : Cost 3 vsldoi8 LHS, <0,2,1,2> - 4162027772U, // : Cost 3 vsldoi8 LHS, <0,3,1,0> - 3088286034U, // : Cost 2 vsldoi8 LHS, <0,4,1,5> - 4209803730U, // : Cost 3 vsldoi8 LHS, <0,5,6,7> - 4067898297U, // : Cost 3 vsldoi4 <6,u,3,0>, <6,u,3,0> - 3363334074U, // : Cost 3 vmrglw <1,2,u,0>, <2,6,3,7> - 2014544541U, // : Cost 1 vsldoi8 LHS, LHS - 2196097174U, // : Cost 2 vmrghw LHS, <3,0,1,2> - 3088286516U, // : Cost 2 vsldoi8 LHS, <1,1,1,1> - 3088286614U, // : Cost 2 vsldoi8 LHS, <1,2,3,0> - 2196097436U, // : Cost 2 vmrghw LHS, <3,3,3,3> - 2196097538U, // : Cost 2 vmrghw LHS, <3,4,5,6> - 4166673519U, // : Cost 3 vsldoi8 LHS, <1,5,0,1> - 4166673615U, // : Cost 3 vsldoi8 LHS, <1,6,1,7> - 3361351610U, // : Cost 3 vmrglw <0,u,u,1>, <2,6,3,7> - 3088287100U, // : Cost 2 vsldoi8 LHS, <1,u,3,0> - 4162029050U, // : Cost 3 vsldoi8 LHS, <2,0,u,0> - 4162029087U, // : Cost 3 vsldoi8 LHS, <2,1,3,1> - 3088287336U, // : Cost 2 vsldoi8 LHS, <2,2,2,2> - 3088287398U, // : Cost 2 vsldoi8 LHS, <2,3,0,1> - 4162029379U, // : Cost 3 vsldoi8 LHS, <2,4,u,5> - 4162029461U, // : Cost 3 vsldoi8 LHS, <2,5,u,6> - 3088287674U, // : Cost 2 vsldoi8 LHS, <2,6,3,7> - 3373967290U, // : Cost 3 vmrglw <3,0,u,2>, <2,6,3,7> - 3088287803U, // : Cost 2 vsldoi8 LHS, <2,u,0,1> - 2282980246U, // : Cost 2 vmrglw LHS, <1,2,3,0> - 3356722071U, // : Cost 3 vmrglw LHS, <1,2,3,1> - 2970290264U, // : Cost 2 vsldoi4 <2,u,3,3>, <2,u,3,3> - 1745666150U, // : Cost 1 vspltisw3 LHS - 2282980250U, // : Cost 2 vmrglw LHS, <1,2,3,4> - 3356722723U, // : Cost 3 vmrglw LHS, <2,1,3,5> - 3356727422U, // : Cost 3 vmrglw LHS, - 2282981306U, // : Cost 2 vmrglw LHS, <2,6,3,7> - 1745666150U, // : Cost 1 vspltisw3 LHS - 2964324454U, // : Cost 2 vsldoi4 <1,u,3,4>, LHS - 2964325760U, // : Cost 2 vsldoi4 <1,u,3,4>, <1,u,3,4> - 4038067816U, // : Cost 3 vsldoi4 <1,u,3,4>, <2,2,2,2> - 3363366514U, // : Cost 3 vmrglw <1,2,u,4>, <2,2,3,3> - 2964327734U, // : Cost 2 vsldoi4 <1,u,3,4>, RHS - 2014547254U, // : Cost 1 vsldoi8 LHS, RHS - 4067931069U, // : Cost 3 vsldoi4 <6,u,3,4>, <6,u,3,4> - 3363366842U, // : Cost 3 vmrglw <1,2,u,4>, <2,6,3,7> - 2014547497U, // : Cost 1 vsldoi8 LHS, RHS - 2199079062U, // : Cost 2 vmrghw RHS, <3,0,1,2> - 4209806991U, // : Cost 3 vsldoi8 LHS, <5,1,0,1> - 4044048474U, // : Cost 3 vsldoi4 <2,u,3,5>, <2,u,3,5> - 2199079324U, // : Cost 2 vmrghw RHS, <3,3,3,3> - 2199079426U, // : Cost 2 vmrghw RHS, <3,4,5,6> - 3136065540U, // : Cost 2 vsldoi8 LHS, <5,5,5,5> - 3136065634U, // : Cost 2 vsldoi8 LHS, <5,6,7,0> - 3361384378U, // : Cost 3 vmrglw <0,u,u,5>, <2,6,3,7> - 3136065796U, // : Cost 2 vsldoi8 LHS, <5,u,7,0> - 4044054630U, // : Cost 3 vsldoi4 <2,u,3,6>, LHS - 4209807783U, // : Cost 3 vsldoi8 LHS, <6,1,7,1> - 3124785667U, // : Cost 2 vsldoi8 <6,2,u,3>, <6,2,u,3> - 4044057117U, // : Cost 3 vsldoi4 <2,u,3,6>, <3,4,u,6> - 4044057910U, // : Cost 3 vsldoi4 <2,u,3,6>, RHS - 4209808107U, // : Cost 3 vsldoi8 LHS, <6,5,7,1> - 3136066360U, // : Cost 2 vsldoi8 LHS, <6,6,6,6> - 3136066382U, // : Cost 2 vsldoi8 LHS, <6,7,0,1> - 3128767465U, // : Cost 2 vsldoi8 <6,u,u,3>, <6,u,u,3> - 2970320998U, // : Cost 2 vsldoi4 <2,u,3,7>, LHS - 4044063540U, // : Cost 3 vsldoi4 <2,u,3,7>, <1,1,1,1> - 2970323036U, // : Cost 2 vsldoi4 <2,u,3,7>, <2,u,3,7> - 2309555826U, // : Cost 2 vmrglw RHS, <2,2,3,3> - 2970324278U, // : Cost 2 vsldoi4 <2,u,3,7>, RHS - 3383297571U, // : Cost 3 vmrglw RHS, <2,1,3,5> - 3383297896U, // : Cost 3 vmrglw RHS, <2,5,3,6> - 2309556154U, // : Cost 2 vmrglw RHS, <2,6,3,7> - 2970326830U, // : Cost 2 vsldoi4 <2,u,3,7>, LHS - 3088291539U, // : Cost 2 vsldoi8 LHS, - 2014549806U, // : Cost 1 vsldoi8 LHS, LHS - 3088291720U, // : Cost 2 vsldoi8 LHS, - 1745666150U, // : Cost 1 vspltisw3 LHS - 3088291903U, // : Cost 2 vsldoi8 LHS, - 2014550170U, // : Cost 1 vsldoi8 LHS, RHS - 3088292048U, // : Cost 2 vsldoi8 LHS, - 2283022266U, // : Cost 2 vmrglw LHS, <2,6,3,7> - 2014550373U, // : Cost 1 vsldoi8 LHS, LHS - 2171751314U, // : Cost 2 vmrghw <4,0,5,1>, <4,0,5,1> - 3094929510U, // : Cost 2 vsldoi8 <1,2,u,4>, LHS - 4044081246U, // : Cost 3 vsldoi4 <2,u,4,0>, <2,u,4,0> - 4162846976U, // : Cost 3 vsldoi8 <0,3,1,4>, <0,3,1,4> - 4168671570U, // : Cost 3 vsldoi8 <1,2,u,4>, <0,4,1,5> - 3248941970U, // : Cost 2 vsldoi12 RHS, <4,0,5,1> - 4067972034U, // : Cost 3 vsldoi4 <6,u,4,0>, <6,u,4,0> - 3263122888U, // : Cost 3 vmrghw <7,0,1,2>, <4,7,5,0> - 3094930077U, // : Cost 2 vsldoi8 <1,2,u,4>, LHS - 2196097938U, // : Cost 2 vmrghw LHS, <4,0,5,1> - 4168672052U, // : Cost 3 vsldoi8 <1,2,u,4>, <1,1,1,1> - 3094930375U, // : Cost 2 vsldoi8 <1,2,u,4>, <1,2,u,4> - 4050062136U, // : Cost 3 vsldoi4 <3,u,4,1>, <3,u,4,1> - 2196098256U, // : Cost 2 vmrghw LHS, <4,4,4,4> - 1122356534U, // : Cost 1 vmrghw LHS, RHS - 3269840249U, // : Cost 3 vmrghw LHS, <4,6,5,2> - 4073952924U, // : Cost 3 vsldoi4 <7,u,4,1>, <7,u,4,1> - 1122356777U, // : Cost 1 vmrghw LHS, RHS - 3270552466U, // : Cost 3 vmrghw , <4,0,5,1> - 3228748772U, // : Cost 3 vmrghw <1,2,3,0>, <4,1,5,2> - 4168672872U, // : Cost 3 vsldoi8 <1,2,u,4>, <2,2,2,2> - 4168672934U, // : Cost 3 vsldoi8 <1,2,u,4>, <2,3,0,1> - 3397856464U, // : Cost 3 vmrglw <7,0,u,2>, <4,4,4,4> - 2196811062U, // : Cost 2 vmrghw , RHS - 4168673210U, // : Cost 3 vsldoi8 <1,2,u,4>, <2,6,3,7> - 4177963061U, // : Cost 3 vsldoi8 <2,7,u,4>, <2,7,u,4> - 2196811305U, // : Cost 2 vmrghw , RHS - 4168673430U, // : Cost 3 vsldoi8 <1,2,u,4>, <3,0,1,2> - 3356723376U, // : Cost 3 vmrglw LHS, <3,0,4,1> - 4180617593U, // : Cost 3 vsldoi8 <3,2,u,4>, <3,2,u,4> - 4168673692U, // : Cost 3 vsldoi8 <1,2,u,4>, <3,3,3,3> - 2330758352U, // : Cost 2