From lattner at cs.uiuc.edu Mon May 1 00:54:14 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 1 May 2006 00:54:14 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86IntelAsmPrinter.cpp X86IntelAsmPrinter.h Message-ID: <200605010554.AAA06883@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86IntelAsmPrinter.cpp updated: 1.30 -> 1.31 X86IntelAsmPrinter.h updated: 1.14 -> 1.15 --- Log message: Remove %'s from register names when in intel mode. --- Diffs of the changes: (+4 -6) X86IntelAsmPrinter.cpp | 7 +++---- X86IntelAsmPrinter.h | 3 +-- 2 files changed, 4 insertions(+), 6 deletions(-) Index: llvm/lib/Target/X86/X86IntelAsmPrinter.cpp diff -u llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.30 llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.31 --- llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.30 Fri Apr 28 18:19:39 2006 +++ llvm/lib/Target/X86/X86IntelAsmPrinter.cpp Mon May 1 00:53:50 2006 @@ -102,10 +102,9 @@ // FALLTHROUGH case MachineOperand::MO_MachineRegister: if (MRegisterInfo::isPhysicalRegister(MO.getReg())) - // Bug Workaround: See note in Printer::doInitialization about %. - O << "%" << RI.get(MO.getReg()).Name; + O << RI.get(MO.getReg()).Name; else - O << "%reg" << MO.getReg(); + O << "reg" << MO.getReg(); return; case MachineOperand::MO_SignExtendedImmed: @@ -355,7 +354,7 @@ break; } - O << '%' << Name; + O << Name; return false; } Index: llvm/lib/Target/X86/X86IntelAsmPrinter.h diff -u llvm/lib/Target/X86/X86IntelAsmPrinter.h:1.14 llvm/lib/Target/X86/X86IntelAsmPrinter.h:1.15 --- llvm/lib/Target/X86/X86IntelAsmPrinter.h:1.14 Fri Apr 28 18:19:39 2006 +++ llvm/lib/Target/X86/X86IntelAsmPrinter.h Mon May 1 00:53:50 2006 @@ -40,8 +40,7 @@ const MachineOperand &MO = MI->getOperand(OpNo); if (MO.getType() == MachineOperand::MO_MachineRegister) { assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physref??"); - // Bug Workaround: See note in Printer::doInitialization about %. - O << "%" << TM.getRegisterInfo()->get(MO.getReg()).Name; + O << TM.getRegisterInfo()->get(MO.getReg()).Name; } else { printOp(MO, Modifier); } From lattner at cs.uiuc.edu Mon May 1 00:57:03 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 1 May 2006 00:57:03 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/X86/2005-08-30-RegAllocAliasProblem.ll 2005-12-03-IndirectTailCall.ll fast-cc-merge-stack-adj.ll fast-cc-pass-in-regs.ll overlap-add.ll overlap-shift.ll Message-ID: <200605010557.AAA08383@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/X86: 2005-08-30-RegAllocAliasProblem.ll updated: 1.1 -> 1.2 2005-12-03-IndirectTailCall.ll updated: 1.2 -> 1.3 fast-cc-merge-stack-adj.ll updated: 1.3 -> 1.4 fast-cc-pass-in-regs.ll updated: 1.4 -> 1.5 overlap-add.ll updated: 1.3 -> 1.4 overlap-shift.ll updated: 1.4 -> 1.5 --- Log message: Intel mode no longer uses %'s on registers --- Diffs of the changes: (+7 -7) 2005-08-30-RegAllocAliasProblem.ll | 4 ++-- 2005-12-03-IndirectTailCall.ll | 2 +- fast-cc-merge-stack-adj.ll | 2 +- fast-cc-pass-in-regs.ll | 2 +- overlap-add.ll | 2 +- overlap-shift.ll | 2 +- 6 files changed, 7 insertions(+), 7 deletions(-) Index: llvm/test/Regression/CodeGen/X86/2005-08-30-RegAllocAliasProblem.ll diff -u llvm/test/Regression/CodeGen/X86/2005-08-30-RegAllocAliasProblem.ll:1.1 llvm/test/Regression/CodeGen/X86/2005-08-30-RegAllocAliasProblem.ll:1.2 --- llvm/test/Regression/CodeGen/X86/2005-08-30-RegAllocAliasProblem.ll:1.1 Tue Aug 30 16:02:51 2005 +++ llvm/test/Regression/CodeGen/X86/2005-08-30-RegAllocAliasProblem.ll Mon May 1 00:56:51 2006 @@ -1,5 +1,5 @@ -; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | not grep 'test.*%AL' || \ -; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | not grep 'cmove.*%EAX' +; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | not grep 'test.*AL' || \ +; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | not grep 'cmove.*EAX' ; This testcase was compiling to: ; Index: llvm/test/Regression/CodeGen/X86/2005-12-03-IndirectTailCall.ll diff -u llvm/test/Regression/CodeGen/X86/2005-12-03-IndirectTailCall.ll:1.2 llvm/test/Regression/CodeGen/X86/2005-12-03-IndirectTailCall.ll:1.3 --- llvm/test/Regression/CodeGen/X86/2005-12-03-IndirectTailCall.ll:1.2 Fri Jan 27 15:13:27 2006 +++ llvm/test/Regression/CodeGen/X86/2005-12-03-IndirectTailCall.ll Mon May 1 00:56:51 2006 @@ -1,5 +1,5 @@ ; XFAIL: * -; RUN: llvm-as < %s | llc -march=x86 -enable-x86-fastcc | grep 'jmp \*%ecx' +; RUN: llvm-as < %s | llc -march=x86 -enable-x86-fastcc | grep 'jmp \*ecx' declare int %putchar(int) int %main(){ Index: llvm/test/Regression/CodeGen/X86/fast-cc-merge-stack-adj.ll diff -u llvm/test/Regression/CodeGen/X86/fast-cc-merge-stack-adj.ll:1.3 llvm/test/Regression/CodeGen/X86/fast-cc-merge-stack-adj.ll:1.4 --- llvm/test/Regression/CodeGen/X86/fast-cc-merge-stack-adj.ll:1.3 Wed Jul 20 14:12:00 2005 +++ llvm/test/Regression/CodeGen/X86/fast-cc-merge-stack-adj.ll Mon May 1 00:56:51 2006 @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel -enable-x86-fastcc | grep 'add %ESP, 8' +; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel -enable-x86-fastcc | grep 'add ESP, 8' target triple = "i686-pc-linux-gnu" Index: llvm/test/Regression/CodeGen/X86/fast-cc-pass-in-regs.ll diff -u llvm/test/Regression/CodeGen/X86/fast-cc-pass-in-regs.ll:1.4 llvm/test/Regression/CodeGen/X86/fast-cc-pass-in-regs.ll:1.5 --- llvm/test/Regression/CodeGen/X86/fast-cc-pass-in-regs.ll:1.4 Sat Mar 18 17:48:54 2006 +++ llvm/test/Regression/CodeGen/X86/fast-cc-pass-in-regs.ll Mon May 1 00:56:51 2006 @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel -enable-x86-fastcc | grep 'mov %EDX, 1' +; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel -enable-x86-fastcc | grep 'mov EDX, 1' ; check that fastcc is passing stuff in regs. ; Argument reg passing is disabled due to regalloc issues. FIXME! Index: llvm/test/Regression/CodeGen/X86/overlap-add.ll diff -u llvm/test/Regression/CodeGen/X86/overlap-add.ll:1.3 llvm/test/Regression/CodeGen/X86/overlap-add.ll:1.4 --- llvm/test/Regression/CodeGen/X86/overlap-add.ll:1.3 Fri Mar 24 01:13:29 2006 +++ llvm/test/Regression/CodeGen/X86/overlap-add.ll Mon May 1 00:56:51 2006 @@ -6,7 +6,7 @@ ; Check that the shift gets turned into an LEA. -; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | not grep 'mov %E.X, %E.X' +; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | not grep 'mov E.X, E.X' ; FIXME: We need live variable information about flags to do this xform safely. :( ; XFAIL: * Index: llvm/test/Regression/CodeGen/X86/overlap-shift.ll diff -u llvm/test/Regression/CodeGen/X86/overlap-shift.ll:1.4 llvm/test/Regression/CodeGen/X86/overlap-shift.ll:1.5 --- llvm/test/Regression/CodeGen/X86/overlap-shift.ll:1.4 Fri Mar 24 01:13:29 2006 +++ llvm/test/Regression/CodeGen/X86/overlap-shift.ll Mon May 1 00:56:51 2006 @@ -6,7 +6,7 @@ ; Check that the shift gets turned into an LEA. -; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | not grep 'mov %E.X, %E.X' +; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | not grep 'mov E.X, E.X' %G = external global int From evan.cheng at apple.com Mon May 1 03:55:10 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 1 May 2006 03:55:10 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/VirtRegMap.cpp Message-ID: <200605010855.DAA20312@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: VirtRegMap.cpp updated: 1.61 -> 1.62 --- Log message: Remove temp. option -spiller-check-liveout, it didn't cause any failure nor performance regressions. --- Diffs of the changes: (+1 -5) VirtRegMap.cpp | 6 +----- 1 files changed, 1 insertion(+), 5 deletions(-) Index: llvm/lib/CodeGen/VirtRegMap.cpp diff -u llvm/lib/CodeGen/VirtRegMap.cpp:1.61 llvm/lib/CodeGen/VirtRegMap.cpp:1.62 --- llvm/lib/CodeGen/VirtRegMap.cpp:1.61 Sun Apr 30 03:41:47 2006 +++ llvm/lib/CodeGen/VirtRegMap.cpp Mon May 1 03:54:57 2006 @@ -50,10 +50,6 @@ clEnumVal(local, " local spiller"), clEnumValEnd), cl::init(local)); - - // TEMPORARY option to test a fix. - cl::opt - SpillerCheckLiveOut("spiller-check-liveout", cl::Hidden); } //===----------------------------------------------------------------------===// @@ -735,7 +731,7 @@ // If we get here, the store is dead, nuke it now. assert(!(MR & VirtRegMap::isRef) && "Can't be modref!"); // Don't nuke it if the value is needed in another block. - if (!SpillerCheckLiveOut || !(MR & VirtRegMap::isLiveOut)) { + if (!(MR & VirtRegMap::isLiveOut)) { DEBUG(std::cerr << " Killed store:\t" << *MDSI->second); MBB.erase(MDSI->second); MaybeDeadStores.erase(MDSI); From evan.cheng at apple.com Mon May 1 03:55:10 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 1 May 2006 03:55:10 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Message-ID: <200605010855.DAA20316@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: ScheduleDAGList.cpp updated: 1.48 -> 1.49 --- Log message: Remove temp. option -spiller-check-liveout, it didn't cause any failure nor performance regressions. --- Diffs of the changes: (+33 -17) ScheduleDAGList.cpp | 50 +++++++++++++++++++++++++++++++++----------------- 1 files changed, 33 insertions(+), 17 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.48 llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.49 --- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.48 Sun Mar 12 03:01:41 2006 +++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Mon May 1 03:54:57 2006 @@ -51,6 +51,7 @@ short NumSuccsLeft; // # of succs not scheduled. short NumChainPredsLeft; // # of chain preds not scheduled. short NumChainSuccsLeft; // # of chain succs not scheduled. + bool isStore : 1; // Is a store. bool isTwoAddress : 1; // Is a two-address instruction. bool isDefNUseOperand : 1; // Is a def&use operand. bool isPending : 1; // True once pending. @@ -63,7 +64,7 @@ SUnit(SDNode *node, unsigned nodenum) : Node(node), NumPredsLeft(0), NumSuccsLeft(0), - NumChainPredsLeft(0), NumChainSuccsLeft(0), + NumChainPredsLeft(0), NumChainSuccsLeft(0), isStore(false), isTwoAddress(false), isDefNUseOperand(false), isPending(false), isAvailable(false), isScheduled(false), Latency(0), CycleBound(0), Cycle(0), NodeNum(nodenum) {} @@ -315,9 +316,13 @@ SUnit *SU = &SUnits[su]; SDNode *MainNode = SU->Node; - if (MainNode->isTargetOpcode() && - TII->isTwoAddrInstr(MainNode->getTargetOpcode())) - SU->isTwoAddress = true; + if (MainNode->isTargetOpcode()) { + unsigned Opc = MainNode->getTargetOpcode(); + if (TII->isTwoAddrInstr(Opc)) + SU->isTwoAddress = true; + if (TII->isStore(Opc)) + SU->isStore = true; + } // Find all predecessors and successors of the group. // Temporarily add N to make code simpler. @@ -358,9 +363,9 @@ SU->FlaggedNodes.pop_back(); } - return; DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su) SUnits[su].dumpAll(&DAG)); + return; } /// EmitSchedule - Emit the machine code in scheduled order. @@ -735,7 +740,7 @@ const std::vector *SUnits; // SethiUllmanNumbers - The SethiUllman number for each node. - std::vector SethiUllmanNumbers; + std::vector SethiUllmanNumbers; std::priority_queue, ls_rr_sort> Queue; public: @@ -774,7 +779,7 @@ } private: void CalculatePriorities(); - int CalcNodePriority(const SUnit *SU); + unsigned CalcNodePriority(const SUnit *SU); }; } @@ -784,7 +789,7 @@ int LBonus = (int)left ->isDefNUseOperand; int RBonus = (int)right->isDefNUseOperand; - + // Special tie breaker: if two nodes share a operand, the one that // use it as a def&use operand is preferred. if (left->isTwoAddress && !right->isTwoAddress) { @@ -798,6 +803,20 @@ RBonus++; } + // Push stores up as much as possible. This really help code like this: + // load + // compute + // store + // load + // compute + // store + // This would make sure the scheduled code completed all computations and + // the stores before the next series of computation starts. + if (!left->isStore && right->isStore) + LBonus += 2; + if (left->isStore && !right->isStore) + RBonus += 2; + // Priority1 is just the number of live range genned. int LPriority1 = left ->NumPredsLeft - LBonus; int RPriority1 = right->NumPredsLeft - RBonus; @@ -819,9 +838,9 @@ /// CalcNodePriority - Priority is the Sethi Ullman number. /// Smaller number is the higher priority. -int RegReductionPriorityQueue::CalcNodePriority(const SUnit *SU) { - int &SethiUllmanNumber = SethiUllmanNumbers[SU->NodeNum]; - if (SethiUllmanNumber != INT_MIN) +unsigned RegReductionPriorityQueue::CalcNodePriority(const SUnit *SU) { + unsigned &SethiUllmanNumber = SethiUllmanNumbers[SU->NodeNum]; + if (SethiUllmanNumber != 0) return SethiUllmanNumber; if (SU->Preds.size() == 0) { @@ -832,7 +851,7 @@ I = SU->Preds.begin(), E = SU->Preds.end(); I != E; ++I) { if (I->second) continue; // ignore chain preds. SUnit *PredSU = I->first; - int PredSethiUllman = CalcNodePriority(PredSU); + unsigned PredSethiUllman = CalcNodePriority(PredSU); if (PredSethiUllman > SethiUllmanNumber) { SethiUllmanNumber = PredSethiUllman; Extra = 0; @@ -840,10 +859,7 @@ Extra++; } - if (SU->Node->getOpcode() != ISD::TokenFactor) - SethiUllmanNumber += Extra; - else - SethiUllmanNumber = (Extra == 1) ? 0 : Extra-1; + SethiUllmanNumber += Extra; } return SethiUllmanNumber; @@ -851,7 +867,7 @@ /// CalculatePriorities - Calculate priorities of all scheduling units. void RegReductionPriorityQueue::CalculatePriorities() { - SethiUllmanNumbers.assign(SUnits->size(), INT_MIN); + SethiUllmanNumbers.assign(SUnits->size(), 0); for (unsigned i = 0, e = SUnits->size(); i != e; ++i) CalcNodePriority(&(*SUnits)[i]); From evan.cheng at apple.com Mon May 1 03:56:47 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 1 May 2006 03:56:47 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Message-ID: <200605010856.DAA20585@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: ScheduleDAGList.cpp updated: 1.49 -> 1.50 --- Log message: Didn't mean ScheduleDAGList.cpp to make the last checkin. --- Diffs of the changes: (+17 -33) ScheduleDAGList.cpp | 50 +++++++++++++++++--------------------------------- 1 files changed, 17 insertions(+), 33 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.49 llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.50 --- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.49 Mon May 1 03:54:57 2006 +++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Mon May 1 03:56:34 2006 @@ -51,7 +51,6 @@ short NumSuccsLeft; // # of succs not scheduled. short NumChainPredsLeft; // # of chain preds not scheduled. short NumChainSuccsLeft; // # of chain succs not scheduled. - bool isStore : 1; // Is a store. bool isTwoAddress : 1; // Is a two-address instruction. bool isDefNUseOperand : 1; // Is a def&use operand. bool isPending : 1; // True once pending. @@ -64,7 +63,7 @@ SUnit(SDNode *node, unsigned nodenum) : Node(node), NumPredsLeft(0), NumSuccsLeft(0), - NumChainPredsLeft(0), NumChainSuccsLeft(0), isStore(false), + NumChainPredsLeft(0), NumChainSuccsLeft(0), isTwoAddress(false), isDefNUseOperand(false), isPending(false), isAvailable(false), isScheduled(false), Latency(0), CycleBound(0), Cycle(0), NodeNum(nodenum) {} @@ -316,13 +315,9 @@ SUnit *SU = &SUnits[su]; SDNode *MainNode = SU->Node; - if (MainNode->isTargetOpcode()) { - unsigned Opc = MainNode->getTargetOpcode(); - if (TII->isTwoAddrInstr(Opc)) - SU->isTwoAddress = true; - if (TII->isStore(Opc)) - SU->isStore = true; - } + if (MainNode->isTargetOpcode() && + TII->isTwoAddrInstr(MainNode->getTargetOpcode())) + SU->isTwoAddress = true; // Find all predecessors and successors of the group. // Temporarily add N to make code simpler. @@ -363,9 +358,9 @@ SU->FlaggedNodes.pop_back(); } + return; DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su) SUnits[su].dumpAll(&DAG)); - return; } /// EmitSchedule - Emit the machine code in scheduled order. @@ -740,7 +735,7 @@ const std::vector *SUnits; // SethiUllmanNumbers - The SethiUllman number for each node. - std::vector SethiUllmanNumbers; + std::vector SethiUllmanNumbers; std::priority_queue, ls_rr_sort> Queue; public: @@ -779,7 +774,7 @@ } private: void CalculatePriorities(); - unsigned CalcNodePriority(const SUnit *SU); + int CalcNodePriority(const SUnit *SU); }; } @@ -789,7 +784,7 @@ int LBonus = (int)left ->isDefNUseOperand; int RBonus = (int)right->isDefNUseOperand; - + // Special tie breaker: if two nodes share a operand, the one that // use it as a def&use operand is preferred. if (left->isTwoAddress && !right->isTwoAddress) { @@ -803,20 +798,6 @@ RBonus++; } - // Push stores up as much as possible. This really help code like this: - // load - // compute - // store - // load - // compute - // store - // This would make sure the scheduled code completed all computations and - // the stores before the next series of computation starts. - if (!left->isStore && right->isStore) - LBonus += 2; - if (left->isStore && !right->isStore) - RBonus += 2; - // Priority1 is just the number of live range genned. int LPriority1 = left ->NumPredsLeft - LBonus; int RPriority1 = right->NumPredsLeft - RBonus; @@ -838,9 +819,9 @@ /// CalcNodePriority - Priority is the Sethi Ullman number. /// Smaller number is the higher priority. -unsigned RegReductionPriorityQueue::CalcNodePriority(const SUnit *SU) { - unsigned &SethiUllmanNumber = SethiUllmanNumbers[SU->NodeNum]; - if (SethiUllmanNumber != 0) +int RegReductionPriorityQueue::CalcNodePriority(const SUnit *SU) { + int &SethiUllmanNumber = SethiUllmanNumbers[SU->NodeNum]; + if (SethiUllmanNumber != INT_MIN) return SethiUllmanNumber; if (SU->Preds.size() == 0) { @@ -851,7 +832,7 @@ I = SU->Preds.begin(), E = SU->Preds.end(); I != E; ++I) { if (I->second) continue; // ignore chain preds. SUnit *PredSU = I->first; - unsigned PredSethiUllman = CalcNodePriority(PredSU); + int PredSethiUllman = CalcNodePriority(PredSU); if (PredSethiUllman > SethiUllmanNumber) { SethiUllmanNumber = PredSethiUllman; Extra = 0; @@ -859,7 +840,10 @@ Extra++; } - SethiUllmanNumber += Extra; + if (SU->Node->getOpcode() != ISD::TokenFactor) + SethiUllmanNumber += Extra; + else + SethiUllmanNumber = (Extra == 1) ? 0 : Extra-1; } return SethiUllmanNumber; @@ -867,7 +851,7 @@ /// CalculatePriorities - Calculate priorities of all scheduling units. void RegReductionPriorityQueue::CalculatePriorities() { - SethiUllmanNumbers.assign(SUnits->size(), 0); + SethiUllmanNumbers.assign(SUnits->size(), INT_MIN); for (unsigned i = 0, e = SUnits->size(); i != e; ++i) CalcNodePriority(&(*SUnits)[i]); From evan.cheng at apple.com Mon May 1 03:57:30 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 1 May 2006 03:57:30 -0500 Subject: [llvm-commits] CVS: llvm-test/Makefile.programs Message-ID: <200605010857.DAA20690@zion.cs.uiuc.edu> Changes in directory llvm-test: Makefile.programs updated: 1.206 -> 1.207 --- Log message: Revert x86 llcbeta to -enable-x86-fastcc --- Diffs of the changes: (+1 -1) Makefile.programs | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm-test/Makefile.programs diff -u llvm-test/Makefile.programs:1.206 llvm-test/Makefile.programs:1.207 --- llvm-test/Makefile.programs:1.206 Sun Apr 30 03:42:35 2006 +++ llvm-test/Makefile.programs Mon May 1 03:57:18 2006 @@ -197,7 +197,7 @@ LLCBETAOPTION := -sched=simple endif ifeq ($(ARCH),x86) -LLCBETAOPTION := -spiller-check-liveout +LLCBETAOPTION := -enable-x86-fastcc endif ifeq ($(ARCH),Sparc) LLCBETAOPTION := -enable-sparc-v9-insts From evan.cheng at apple.com Mon May 1 04:04:33 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 1 May 2006 04:04:33 -0500 Subject: [llvm-commits] CVS: llvm/utils/TableGen/InstrInfoEmitter.cpp Message-ID: <200605010904.EAA22089@zion.cs.uiuc.edu> Changes in directory llvm/utils/TableGen: InstrInfoEmitter.cpp updated: 1.36 -> 1.37 --- Log message: Mark instructions whose pattern is (store ...) isStore. --- Diffs of the changes: (+17 -1) InstrInfoEmitter.cpp | 18 +++++++++++++++++- 1 files changed, 17 insertions(+), 1 deletion(-) Index: llvm/utils/TableGen/InstrInfoEmitter.cpp diff -u llvm/utils/TableGen/InstrInfoEmitter.cpp:1.36 llvm/utils/TableGen/InstrInfoEmitter.cpp:1.37 --- llvm/utils/TableGen/InstrInfoEmitter.cpp:1.36 Thu Apr 20 13:32:22 2006 +++ llvm/utils/TableGen/InstrInfoEmitter.cpp Mon May 1 04:04:20 2006 @@ -184,6 +184,22 @@ OS << "\",\t" << NumOperands << ", " << ItinClass << ", 0"; + // Try to determine (from the pattern), if the instruction is a store. + bool isStore = false; + if (dynamic_cast(Inst.TheDef->getValueInit("Pattern"))) { + ListInit *LI = Inst.TheDef->getValueAsListInit("Pattern"); + if (LI && LI->getSize() > 0) { + DagInit *Dag = (DagInit *)LI->getElement(0); + DefInit *OpDef = dynamic_cast(Dag->getOperator()); + if (OpDef) { + Record *Operator = OpDef->getDef(); + if (Operator->isSubClassOf("SDNode") && + Operator->getValueAsString("Opcode") == "ISD::STORE") + isStore = true; + } + } + } + // Emit all of the target indepedent flags... if (Inst.isReturn) OS << "|M_RET_FLAG"; if (Inst.isBranch) OS << "|M_BRANCH_FLAG"; @@ -191,7 +207,7 @@ if (Inst.hasDelaySlot) OS << "|M_DELAY_SLOT_FLAG"; if (Inst.isCall) OS << "|M_CALL_FLAG"; if (Inst.isLoad) OS << "|M_LOAD_FLAG"; - if (Inst.isStore) OS << "|M_STORE_FLAG"; + if (Inst.isStore || isStore) OS << "|M_STORE_FLAG"; if (Inst.isTwoAddress) OS << "|M_2_ADDR_FLAG"; if (Inst.isConvertibleToThreeAddress) OS << "|M_CONVERTIBLE_TO_3_ADDR"; if (Inst.isCommutable) OS << "|M_COMMUTABLE"; From evan.cheng at apple.com Mon May 1 04:15:18 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 1 May 2006 04:15:18 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Message-ID: <200605010915.EAA25936@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: ScheduleDAGList.cpp updated: 1.50 -> 1.51 --- Log message: Bottom up register-pressure reduction scheduler now pushes store operations up the schedule. This helps code that looks like this: loads ... computations (first set) ... stores (first set) ... loads computations (seccond set) ... stores (seccond set) ... Without this change, the stores and computations are more likely to interleave: loads ... loads ... computations (first set) ... computations (second set) ... computations (first set) ... stores (first set) ... computations (second set) ... stores (stores set) ... This can increase the number of spills if we are unlucky. --- Diffs of the changes: (+41 -17) ScheduleDAGList.cpp | 58 ++++++++++++++++++++++++++++++++++++---------------- 1 files changed, 41 insertions(+), 17 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.50 llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.51 --- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.50 Mon May 1 03:56:34 2006 +++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Mon May 1 04:14:40 2006 @@ -33,6 +33,13 @@ using namespace llvm; namespace { + // TEMPORARY option to test a fix. + cl::opt + SchedIgnorStore("sched-ignore-store", cl::Hidden); + +} + +namespace { Statistic<> NumNoops ("scheduler", "Number of noops inserted"); Statistic<> NumStalls("scheduler", "Number of pipeline stalls"); @@ -51,6 +58,7 @@ short NumSuccsLeft; // # of succs not scheduled. short NumChainPredsLeft; // # of chain preds not scheduled. short NumChainSuccsLeft; // # of chain succs not scheduled. + bool isStore : 1; // Is a store. bool isTwoAddress : 1; // Is a two-address instruction. bool isDefNUseOperand : 1; // Is a def&use operand. bool isPending : 1; // True once pending. @@ -63,7 +71,7 @@ SUnit(SDNode *node, unsigned nodenum) : Node(node), NumPredsLeft(0), NumSuccsLeft(0), - NumChainPredsLeft(0), NumChainSuccsLeft(0), + NumChainPredsLeft(0), NumChainSuccsLeft(0), isStore(false), isTwoAddress(false), isDefNUseOperand(false), isPending(false), isAvailable(false), isScheduled(false), Latency(0), CycleBound(0), Cycle(0), NodeNum(nodenum) {} @@ -315,9 +323,14 @@ SUnit *SU = &SUnits[su]; SDNode *MainNode = SU->Node; - if (MainNode->isTargetOpcode() && - TII->isTwoAddrInstr(MainNode->getTargetOpcode())) - SU->isTwoAddress = true; + if (MainNode->isTargetOpcode()) { + unsigned Opc = MainNode->getTargetOpcode(); + if (TII->isTwoAddrInstr(Opc)) + SU->isTwoAddress = true; + if (TII->isStore(Opc)) + if (!SchedIgnorStore) + SU->isStore = true; + } // Find all predecessors and successors of the group. // Temporarily add N to make code simpler. @@ -358,9 +371,9 @@ SU->FlaggedNodes.pop_back(); } - return; DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su) SUnits[su].dumpAll(&DAG)); + return; } /// EmitSchedule - Emit the machine code in scheduled order. @@ -735,7 +748,7 @@ const std::vector *SUnits; // SethiUllmanNumbers - The SethiUllman number for each node. - std::vector SethiUllmanNumbers; + std::vector SethiUllmanNumbers; std::priority_queue, ls_rr_sort> Queue; public: @@ -774,7 +787,7 @@ } private: void CalculatePriorities(); - int CalcNodePriority(const SUnit *SU); + unsigned CalcNodePriority(const SUnit *SU); }; } @@ -784,7 +797,7 @@ int LBonus = (int)left ->isDefNUseOperand; int RBonus = (int)right->isDefNUseOperand; - + // Special tie breaker: if two nodes share a operand, the one that // use it as a def&use operand is preferred. if (left->isTwoAddress && !right->isTwoAddress) { @@ -798,6 +811,20 @@ RBonus++; } + // Push stores up as much as possible. This really help code like this: + // load + // compute + // store + // load + // compute + // store + // This would make sure the scheduled code completed all computations and + // the stores before the next series of computation starts. + if (!left->isStore && right->isStore) + LBonus += 2; + if (left->isStore && !right->isStore) + RBonus += 2; + // Priority1 is just the number of live range genned. int LPriority1 = left ->NumPredsLeft - LBonus; int RPriority1 = right->NumPredsLeft - RBonus; @@ -819,9 +846,9 @@ /// CalcNodePriority - Priority is the Sethi Ullman number. /// Smaller number is the higher priority. -int RegReductionPriorityQueue::CalcNodePriority(const SUnit *SU) { - int &SethiUllmanNumber = SethiUllmanNumbers[SU->NodeNum]; - if (SethiUllmanNumber != INT_MIN) +unsigned RegReductionPriorityQueue::CalcNodePriority(const SUnit *SU) { + unsigned &SethiUllmanNumber = SethiUllmanNumbers[SU->NodeNum]; + if (SethiUllmanNumber != 0) return SethiUllmanNumber; if (SU->Preds.size() == 0) { @@ -832,7 +859,7 @@ I = SU->Preds.begin(), E = SU->Preds.end(); I != E; ++I) { if (I->second) continue; // ignore chain preds. SUnit *PredSU = I->first; - int PredSethiUllman = CalcNodePriority(PredSU); + unsigned PredSethiUllman = CalcNodePriority(PredSU); if (PredSethiUllman > SethiUllmanNumber) { SethiUllmanNumber = PredSethiUllman; Extra = 0; @@ -840,10 +867,7 @@ Extra++; } - if (SU->Node->getOpcode() != ISD::TokenFactor) - SethiUllmanNumber += Extra; - else - SethiUllmanNumber = (Extra == 1) ? 0 : Extra-1; + SethiUllmanNumber += Extra; } return SethiUllmanNumber; @@ -851,7 +875,7 @@ /// CalculatePriorities - Calculate priorities of all scheduling units. void RegReductionPriorityQueue::CalculatePriorities() { - SethiUllmanNumbers.assign(SUnits->size(), INT_MIN); + SethiUllmanNumbers.assign(SUnits->size(), 0); for (unsigned i = 0, e = SUnits->size(); i != e; ++i) CalcNodePriority(&(*SUnits)[i]); From evan.cheng at apple.com Mon May 1 04:16:44 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 1 May 2006 04:16:44 -0500 Subject: [llvm-commits] CVS: llvm-test/Makefile.programs Message-ID: <200605010916.EAA25988@zion.cs.uiuc.edu> Changes in directory llvm-test: Makefile.programs updated: 1.207 -> 1.208 --- Log message: Set llcbeta to -sched-ignore-store to test a scheduler tweak. (This option turns off the tweak.) --- Diffs of the changes: (+1 -1) Makefile.programs | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm-test/Makefile.programs diff -u llvm-test/Makefile.programs:1.207 llvm-test/Makefile.programs:1.208 --- llvm-test/Makefile.programs:1.207 Mon May 1 03:57:18 2006 +++ llvm-test/Makefile.programs Mon May 1 04:16:32 2006 @@ -197,7 +197,7 @@ LLCBETAOPTION := -sched=simple endif ifeq ($(ARCH),x86) -LLCBETAOPTION := -enable-x86-fastcc +LLCBETAOPTION := -sched-ignore-store endif ifeq ($(ARCH),Sparc) LLCBETAOPTION := -enable-sparc-v9-insts From evan.cheng at apple.com Mon May 1 04:21:24 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 1 May 2006 04:21:24 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Message-ID: <200605010921.EAA26150@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: ScheduleDAGList.cpp updated: 1.51 -> 1.52 --- Log message: Dis-favor stores more --- Diffs of the changes: (+2 -2) ScheduleDAGList.cpp | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.51 llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.52 --- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.51 Mon May 1 04:14:40 2006 +++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Mon May 1 04:20:44 2006 @@ -821,9 +821,9 @@ // This would make sure the scheduled code completed all computations and // the stores before the next series of computation starts. if (!left->isStore && right->isStore) - LBonus += 2; + LBonus += 4; if (left->isStore && !right->isStore) - RBonus += 2; + RBonus += 4; // Priority1 is just the number of live range genned. int LPriority1 = left ->NumPredsLeft - LBonus; From evan.cheng at apple.com Mon May 1 04:30:51 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 1 May 2006 04:30:51 -0500 Subject: [llvm-commits] CVS: llvm/utils/TableGen/InstrInfoEmitter.cpp Message-ID: <200605010930.EAA27526@zion.cs.uiuc.edu> Changes in directory llvm/utils/TableGen: InstrInfoEmitter.cpp updated: 1.37 -> 1.38 --- Log message: Formating --- Diffs of the changes: (+1 -1) InstrInfoEmitter.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/utils/TableGen/InstrInfoEmitter.cpp diff -u llvm/utils/TableGen/InstrInfoEmitter.cpp:1.37 llvm/utils/TableGen/InstrInfoEmitter.cpp:1.38 --- llvm/utils/TableGen/InstrInfoEmitter.cpp:1.37 Mon May 1 04:04:20 2006 +++ llvm/utils/TableGen/InstrInfoEmitter.cpp Mon May 1 04:30:17 2006 @@ -195,7 +195,7 @@ Record *Operator = OpDef->getDef(); if (Operator->isSubClassOf("SDNode") && Operator->getValueAsString("Opcode") == "ISD::STORE") - isStore = true; + isStore = true; } } } From lattner at cs.uiuc.edu Mon May 1 12:01:13 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 1 May 2006 12:01:13 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Target.td Message-ID: <200605011701.MAA03006@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target: Target.td updated: 1.77 -> 1.78 --- Log message: Put PHI/INLINEASM into the correct namespace. --- Diffs of the changes: (+2 -0) Target.td | 2 ++ 1 files changed, 2 insertions(+) Index: llvm/lib/Target/Target.td diff -u llvm/lib/Target/Target.td:1.77 llvm/lib/Target/Target.td:1.78 --- llvm/lib/Target/Target.td:1.77 Wed Apr 19 15:38:28 2006 +++ llvm/lib/Target/Target.td Mon May 1 12:00:49 2006 @@ -224,10 +224,12 @@ def PHI : Instruction { let OperandList = (ops variable_ops); let AsmString = "PHINODE"; + let Namespace = "TargetInstrInfo"; } def INLINEASM : Instruction { let OperandList = (ops variable_ops); let AsmString = ""; + let Namespace = "TargetInstrInfo"; } //===----------------------------------------------------------------------===// From lattner at cs.uiuc.edu Mon May 1 12:01:29 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 1 May 2006 12:01:29 -0500 Subject: [llvm-commits] CVS: llvm/utils/TableGen/AsmWriterEmitter.cpp Message-ID: <200605011701.MAA03018@zion.cs.uiuc.edu> Changes in directory llvm/utils/TableGen: AsmWriterEmitter.cpp updated: 1.27 -> 1.28 --- Log message: instructions can be in different namespaces. Make sure to use the right one for each instruction. --- Diffs of the changes: (+4 -8) AsmWriterEmitter.cpp | 12 ++++-------- 1 files changed, 4 insertions(+), 8 deletions(-) Index: llvm/utils/TableGen/AsmWriterEmitter.cpp diff -u llvm/utils/TableGen/AsmWriterEmitter.cpp:1.27 llvm/utils/TableGen/AsmWriterEmitter.cpp:1.28 --- llvm/utils/TableGen/AsmWriterEmitter.cpp:1.27 Mon Feb 6 17:40:48 2006 +++ llvm/utils/TableGen/AsmWriterEmitter.cpp Mon May 1 12:01:17 2006 @@ -287,12 +287,10 @@ } } - std::string Namespace = FirstInst.CGI->Namespace; - - O << " case " << Namespace << "::" + O << " case " << FirstInst.CGI->Namespace << "::" << FirstInst.CGI->TheDef->getName() << ":\n"; for (unsigned i = 0, e = SimilarInsts.size(); i != e; ++i) - O << " case " << Namespace << "::" + O << " case " << SimilarInsts[i].CGI->Namespace << "::" << SimilarInsts[i].CGI->TheDef->getName() << ":\n"; for (unsigned i = 0, e = FirstInst.Operands.size(); i != e; ++i) { if (i != DifferingOperand) { @@ -304,13 +302,13 @@ // emit a switch for just this operand now. O << " switch (MI->getOpcode()) {\n"; std::vector > OpsToPrint; - OpsToPrint.push_back(std::make_pair(Namespace+"::"+ + OpsToPrint.push_back(std::make_pair(FirstInst.CGI->Namespace + "::" + FirstInst.CGI->TheDef->getName(), FirstInst.Operands[i])); for (unsigned si = 0, e = SimilarInsts.size(); si != e; ++si) { AsmWriterInst &AWI = SimilarInsts[si]; - OpsToPrint.push_back(std::make_pair(Namespace+"::"+ + OpsToPrint.push_back(std::make_pair(AWI.CGI->Namespace+"::"+ AWI.CGI->TheDef->getName(), AWI.Operands[i])); } @@ -341,8 +339,6 @@ "bool " << Target.getName() << ClassName << "::printInstruction(const MachineInstr *MI) {\n"; - std::string Namespace = Target.inst_begin()->second.Namespace; - std::vector Instructions; for (CodeGenTarget::inst_iterator I = Target.inst_begin(), From lattner at cs.uiuc.edu Mon May 1 16:16:15 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 1 May 2006 16:16:15 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/LiveIntervalAnalysis.cpp VirtRegMap.cpp VirtRegMap.h Message-ID: <200605012116.QAA11929@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: LiveIntervalAnalysis.cpp updated: 1.155 -> 1.156 VirtRegMap.cpp updated: 1.62 -> 1.63 VirtRegMap.h updated: 1.19 -> 1.20 --- Log message: Remove previous patch, which wasn't quite right. --- Diffs of the changes: (+23 -24) LiveIntervalAnalysis.cpp | 4 +--- VirtRegMap.cpp | 30 ++++++++++++------------------ VirtRegMap.h | 13 ++++++++++--- 3 files changed, 23 insertions(+), 24 deletions(-) Index: llvm/lib/CodeGen/LiveIntervalAnalysis.cpp diff -u llvm/lib/CodeGen/LiveIntervalAnalysis.cpp:1.155 llvm/lib/CodeGen/LiveIntervalAnalysis.cpp:1.156 --- llvm/lib/CodeGen/LiveIntervalAnalysis.cpp:1.155 Sun Apr 30 03:41:47 2006 +++ llvm/lib/CodeGen/LiveIntervalAnalysis.cpp Mon May 1 16:16:03 2006 @@ -272,9 +272,7 @@ if (lv_) lv_->instructionChanged(MI, fmi); MachineBasicBlock &MBB = *MI->getParent(); - bool LiveOut = li.liveAt(getInstructionIndex(&MBB.back()) + - InstrSlots::NUM); - vrm.virtFolded(li.reg, MI, i, fmi, LiveOut); + vrm.virtFolded(li.reg, MI, i, fmi); mi2iMap_.erase(MI); i2miMap_[index/InstrSlots::NUM] = fmi; mi2iMap_[fmi] = index; Index: llvm/lib/CodeGen/VirtRegMap.cpp diff -u llvm/lib/CodeGen/VirtRegMap.cpp:1.62 llvm/lib/CodeGen/VirtRegMap.cpp:1.63 --- llvm/lib/CodeGen/VirtRegMap.cpp:1.62 Mon May 1 03:54:57 2006 +++ llvm/lib/CodeGen/VirtRegMap.cpp Mon May 1 16:16:03 2006 @@ -81,8 +81,7 @@ } void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI, - unsigned OpNo, MachineInstr *NewMI, - bool LiveOut) { + unsigned OpNo, MachineInstr *NewMI) { // Move previous memory references folded to new instruction. MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI); for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI), @@ -97,7 +96,6 @@ MRInfo = isRef; } else { MRInfo = OldMI->getOperand(OpNo).isUse() ? isModRef : isMod; - if (LiveOut) MRInfo = (ModRef)(MRInfo | isLiveOut); } // add new memory reference @@ -133,12 +131,11 @@ namespace { struct SimpleSpiller : public Spiller { - bool runOnMachineFunction(MachineFunction& mf, const VirtRegMap &VRM); + bool runOnMachineFunction(MachineFunction& mf, VirtRegMap &VRM); }; } -bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, - const VirtRegMap &VRM) { +bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) { DEBUG(std::cerr << "********** REWRITE MACHINE CODE **********\n"); DEBUG(std::cerr << "********** Function: " << MF.getFunction()->getName() << '\n'); @@ -211,7 +208,7 @@ const MRegisterInfo *MRI; const TargetInstrInfo *TII; public: - bool runOnMachineFunction(MachineFunction &MF, const VirtRegMap &VRM) { + bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) { MRI = MF.getTarget().getRegisterInfo(); TII = MF.getTarget().getInstrInfo(); DEBUG(std::cerr << "\n**** Local spiller rewriting function '" @@ -223,7 +220,7 @@ return true; } private: - void RewriteMBB(MachineBasicBlock &MBB, const VirtRegMap &VRM); + void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM); void ClobberPhysReg(unsigned PR, std::map &SpillSlots, std::multimap &PhysRegs); void ClobberPhysRegOnly(unsigned PR, std::map &SpillSlots, @@ -484,7 +481,7 @@ /// rewriteMBB - Keep track of which spills are available even after the /// register allocator is done with them. If possible, avoid reloading vregs. -void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, const VirtRegMap &VRM) { +void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { DEBUG(std::cerr << MBB.getBasicBlock()->getName() << ":\n"); @@ -729,14 +726,11 @@ MaybeDeadStores.erase(MDSI); else { // If we get here, the store is dead, nuke it now. - assert(!(MR & VirtRegMap::isRef) && "Can't be modref!"); - // Don't nuke it if the value is needed in another block. - if (!(MR & VirtRegMap::isLiveOut)) { - DEBUG(std::cerr << " Killed store:\t" << *MDSI->second); - MBB.erase(MDSI->second); - MaybeDeadStores.erase(MDSI); - ++NumDSE; - } + assert(VirtRegMap::isMod && "Can't be modref!"); + DEBUG(std::cerr << "Removed dead store:\t" << *MDSI->second); + MBB.erase(MDSI->second); + MaybeDeadStores.erase(MDSI); + ++NumDSE; } } @@ -837,7 +831,7 @@ // If there is a dead store to this stack slot, nuke it now. MachineInstr *&LastStore = MaybeDeadStores[StackSlot]; if (LastStore) { - DEBUG(std::cerr << " Killed store:\t" << *LastStore); + DEBUG(std::cerr << "Removed dead store:\t" << *LastStore); ++NumDSE; MBB.erase(LastStore); } Index: llvm/lib/CodeGen/VirtRegMap.h diff -u llvm/lib/CodeGen/VirtRegMap.h:1.19 llvm/lib/CodeGen/VirtRegMap.h:1.20 --- llvm/lib/CodeGen/VirtRegMap.h:1.19 Sun Apr 30 03:41:47 2006 +++ llvm/lib/CodeGen/VirtRegMap.h Mon May 1 16:16:03 2006 @@ -26,7 +26,7 @@ class VirtRegMap { public: - enum ModRef { isRef = 1, isMod = 2, isModRef = 3, isLiveOut = 4 }; + enum ModRef { isRef = 1, isMod = 2, isModRef = 3 }; typedef std::multimap > MI2VirtMapTy; @@ -128,7 +128,7 @@ /// folded into newMI machine instruction. The OpNum argument indicates the /// operand number of OldMI that is folded. void virtFolded(unsigned VirtReg, MachineInstr *OldMI, unsigned OpNum, - MachineInstr *NewMI, bool LiveOut); + MachineInstr *NewMI); /// @brief returns the virtual registers' values folded in memory /// operands of this instruction @@ -136,6 +136,13 @@ getFoldedVirts(MachineInstr* MI) const { return MI2VirtMap.equal_range(MI); } + + /// RemoveFromFoldedVirtMap - Given a machine instruction in the folded + /// instruction map, remove the entry in the folded instruction map. + void RemoveFromFoldedVirtMap(MachineInstr *MI) { + bool ErasedAny = MI2VirtMap.erase(MI); + assert(ErasedAny && "Machine instr not in folded vreg map!"); + } void print(std::ostream &OS) const; void dump() const; @@ -151,7 +158,7 @@ struct Spiller { virtual ~Spiller(); virtual bool runOnMachineFunction(MachineFunction &MF, - const VirtRegMap &VRM) = 0; + VirtRegMap &VRM) = 0; }; /// createSpiller - Create an return a spiller object, as specified on the From lattner at cs.uiuc.edu Mon May 1 16:17:22 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 1 May 2006 16:17:22 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/VirtRegMap.cpp Message-ID: <200605012117.QAA11993@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: VirtRegMap.cpp updated: 1.63 -> 1.64 --- Log message: When promoting a load to a reg-reg copy, where the load was a previous instruction folded with spill code, make sure the remove the load from the virt reg folded map. --- Diffs of the changes: (+1 -0) VirtRegMap.cpp | 1 + 1 files changed, 1 insertion(+) Index: llvm/lib/CodeGen/VirtRegMap.cpp diff -u llvm/lib/CodeGen/VirtRegMap.cpp:1.63 llvm/lib/CodeGen/VirtRegMap.cpp:1.64 --- llvm/lib/CodeGen/VirtRegMap.cpp:1.63 Mon May 1 16:16:03 2006 +++ llvm/lib/CodeGen/VirtRegMap.cpp Mon May 1 16:17:10 2006 @@ -712,6 +712,7 @@ NextMII = &MI; --NextMII; // backtrack to the copy. } + VRM.RemoveFromFoldedVirtMap(&MI); MBB.erase(&MI); goto ProcessNextInst; } From lattner at cs.uiuc.edu Mon May 1 17:03:36 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 1 May 2006 17:03:36 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/VirtRegMap.cpp VirtRegMap.h Message-ID: <200605012203.RAA16584@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: VirtRegMap.cpp updated: 1.64 -> 1.65 VirtRegMap.h updated: 1.20 -> 1.21 --- Log message: Fix a latent bug that my spiller patch last week exposed: we were leaving instructions in the virtregfolded map that were deleted. Because they were deleted, newly allocated instructions could end up at the same address, magically finding themselves in the map. The solution is to remove entries from the map when we delete the instructions. --- Diffs of the changes: (+7 -4) VirtRegMap.cpp | 4 ++++ VirtRegMap.h | 7 +++---- 2 files changed, 7 insertions(+), 4 deletions(-) Index: llvm/lib/CodeGen/VirtRegMap.cpp diff -u llvm/lib/CodeGen/VirtRegMap.cpp:1.64 llvm/lib/CodeGen/VirtRegMap.cpp:1.65 --- llvm/lib/CodeGen/VirtRegMap.cpp:1.64 Mon May 1 16:17:10 2006 +++ llvm/lib/CodeGen/VirtRegMap.cpp Mon May 1 17:03:24 2006 @@ -730,6 +730,7 @@ assert(VirtRegMap::isMod && "Can't be modref!"); DEBUG(std::cerr << "Removed dead store:\t" << *MDSI->second); MBB.erase(MDSI->second); + VRM.RemoveFromFoldedVirtMap(MDSI->second); MaybeDeadStores.erase(MDSI); ++NumDSE; } @@ -791,6 +792,7 @@ ++NumDCE; DEBUG(std::cerr << "Removing now-noop copy: " << MI); MBB.erase(&MI); + VRM.RemoveFromFoldedVirtMap(&MI); goto ProcessNextInst; } Spills.ClobberPhysReg(VirtReg); @@ -825,6 +827,7 @@ ++NumDCE; DEBUG(std::cerr << "Removing now-noop copy: " << MI); MBB.erase(&MI); + VRM.RemoveFromFoldedVirtMap(&MI); goto ProcessNextInst; } } @@ -835,6 +838,7 @@ DEBUG(std::cerr << "Removed dead store:\t" << *LastStore); ++NumDSE; MBB.erase(LastStore); + VRM.RemoveFromFoldedVirtMap(LastStore); } LastStore = next(MII); Index: llvm/lib/CodeGen/VirtRegMap.h diff -u llvm/lib/CodeGen/VirtRegMap.h:1.20 llvm/lib/CodeGen/VirtRegMap.h:1.21 --- llvm/lib/CodeGen/VirtRegMap.h:1.20 Mon May 1 16:16:03 2006 +++ llvm/lib/CodeGen/VirtRegMap.h Mon May 1 17:03:24 2006 @@ -137,11 +137,10 @@ return MI2VirtMap.equal_range(MI); } - /// RemoveFromFoldedVirtMap - Given a machine instruction in the folded - /// instruction map, remove the entry in the folded instruction map. + /// RemoveFromFoldedVirtMap - If the specified machine instruction is in + /// the folded instruction map, remove its entry from the map. void RemoveFromFoldedVirtMap(MachineInstr *MI) { - bool ErasedAny = MI2VirtMap.erase(MI); - assert(ErasedAny && "Machine instr not in folded vreg map!"); + MI2VirtMap.erase(MI); } void print(std::ostream &OS) const; From lattner at cs.uiuc.edu Mon May 1 18:19:07 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 1 May 2006 18:19:07 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CFrontend/2006-05-01-AppleAlignmentPragma.c Message-ID: <200605012319.SAA23485@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CFrontend: 2006-05-01-AppleAlignmentPragma.c added (r1.1) --- Log message: New testcase that crashes the new CFE. --- Diffs of the changes: (+12 -0) 2006-05-01-AppleAlignmentPragma.c | 12 ++++++++++++ 1 files changed, 12 insertions(+) Index: llvm/test/Regression/CFrontend/2006-05-01-AppleAlignmentPragma.c diff -c /dev/null llvm/test/Regression/CFrontend/2006-05-01-AppleAlignmentPragma.c:1.1 *** /dev/null Mon May 1 18:19:05 2006 --- llvm/test/Regression/CFrontend/2006-05-01-AppleAlignmentPragma.c Mon May 1 18:18:55 2006 *************** *** 0 **** --- 1,12 ---- + // RUN: %llvmgcc %s -S -o - + + #ifdef __APPLE__ + /* test that X is layed out correctly when this pragma is used. */ + #pragma options align=mac68k + #endif + + struct S { + unsigned A; + unsigned short B; + } X; + From lattner at cs.uiuc.edu Mon May 1 18:46:29 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 1 May 2006 18:46:29 -0500 Subject: [llvm-commits] CVS: llvm/utils/TableGen/InstrInfoEmitter.cpp Message-ID: <200605012346.SAA24506@zion.cs.uiuc.edu> Changes in directory llvm/utils/TableGen: InstrInfoEmitter.cpp updated: 1.38 -> 1.39 --- Log message: Put instruction names into the first non TargetInstrInfo namespace found. --- Diffs of the changes: (+18 -10) InstrInfoEmitter.cpp | 28 ++++++++++++++++++---------- 1 files changed, 18 insertions(+), 10 deletions(-) Index: llvm/utils/TableGen/InstrInfoEmitter.cpp diff -u llvm/utils/TableGen/InstrInfoEmitter.cpp:1.38 llvm/utils/TableGen/InstrInfoEmitter.cpp:1.39 --- llvm/utils/TableGen/InstrInfoEmitter.cpp:1.38 Mon May 1 04:30:17 2006 +++ llvm/utils/TableGen/InstrInfoEmitter.cpp Mon May 1 18:46:16 2006 @@ -28,23 +28,31 @@ // We must emit the PHI opcode first... Record *InstrInfo = Target.getInstructionSet(); - std::string Namespace = Target.inst_begin()->second.Namespace; - - if (!Namespace.empty()) - OS << "namespace " << Namespace << " {\n"; - OS << " enum {\n"; + std::string Namespace; + for (CodeGenTarget::inst_iterator II = Target.inst_begin(), + E = Target.inst_end(); II != E; ++II) { + if (II->second.Namespace != "TargetInstrInfo") { + Namespace = II->second.Namespace; + break; + } + } + + if (Namespace.empty()) { + std::cerr << "No instructions defined!\n"; + exit(1); + } std::vector NumberedInstructions; Target.getInstructionsByEnumValue(NumberedInstructions); + OS << "namespace " << Namespace << " {\n"; + OS << " enum {\n"; for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { OS << " " << NumberedInstructions[i]->TheDef->getName() - << ", \t// " << i << "\n"; + << "\t= " << i << ",\n"; } - OS << " INSTRUCTION_LIST_END\n"; - OS << " };\n"; - if (!Namespace.empty()) - OS << "}\n"; + OS << " INSTRUCTION_LIST_END = " << NumberedInstructions.size() << "\n"; + OS << " };\n}\n"; OS << "} // End llvm namespace \n"; } From jeffc at jolt-lang.org Mon May 1 20:16:41 2006 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Mon, 1 May 2006 20:16:41 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/AsmPrinter.cpp Message-ID: <200605020116.UAA01196@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: AsmPrinter.cpp updated: 1.60 -> 1.61 --- Log message: Make Intel syntax mode friendlier to Microsoft ML assembler (still needs more work). --- Diffs of the changes: (+16 -10) AsmPrinter.cpp | 26 ++++++++++++++++---------- 1 files changed, 16 insertions(+), 10 deletions(-) Index: llvm/lib/CodeGen/AsmPrinter.cpp diff -u llvm/lib/CodeGen/AsmPrinter.cpp:1.60 llvm/lib/CodeGen/AsmPrinter.cpp:1.61 --- llvm/lib/CodeGen/AsmPrinter.cpp:1.60 Sun Apr 30 23:11:03 2006 +++ llvm/lib/CodeGen/AsmPrinter.cpp Mon May 1 20:16:28 2006 @@ -372,6 +372,21 @@ O << "\""; } +/// EmitString - Emit a zero-byte-terminated string constant. +/// +void AsmPrinter::EmitString(const ConstantArray *CVA) const { + unsigned NumElts = CVA->getNumOperands(); + if (AscizDirective && NumElts && + cast(CVA->getOperand(NumElts-1))->getRawValue() == 0) { + O << AscizDirective; + printAsCString(O, CVA, NumElts-1); + } else { + O << AsciiDirective; + printAsCString(O, CVA, NumElts); + } + O << "\n"; +} + /// EmitGlobalConstant - Print a general LLVM constant to the .s file. /// void AsmPrinter::EmitGlobalConstant(const Constant *CV) { @@ -382,16 +397,7 @@ return; } else if (const ConstantArray *CVA = dyn_cast(CV)) { if (CVA->isString()) { - unsigned NumElts = CVA->getNumOperands(); - if (AscizDirective && NumElts && - cast(CVA->getOperand(NumElts-1))->getRawValue() == 0) { - O << AscizDirective; - printAsCString(O, CVA, NumElts-1); - } else { - O << AsciiDirective; - printAsCString(O, CVA, NumElts); - } - O << "\n"; + EmitString(CVA); } else { // Not a string. Print the values in successive locations for (unsigned i = 0, e = CVA->getNumOperands(); i != e; ++i) EmitGlobalConstant(CVA->getOperand(i)); From jeffc at jolt-lang.org Mon May 1 20:16:42 2006 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Mon, 1 May 2006 20:16:42 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/AsmPrinter.h Message-ID: <200605020116.UAA01200@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: AsmPrinter.h updated: 1.32 -> 1.33 --- Log message: Make Intel syntax mode friendlier to Microsoft ML assembler (still needs more work). --- Diffs of the changes: (+6 -1) AsmPrinter.h | 7 ++++++- 1 files changed, 6 insertions(+), 1 deletion(-) Index: llvm/include/llvm/CodeGen/AsmPrinter.h diff -u llvm/include/llvm/CodeGen/AsmPrinter.h:1.32 llvm/include/llvm/CodeGen/AsmPrinter.h:1.33 --- llvm/include/llvm/CodeGen/AsmPrinter.h:1.32 Sat Apr 22 13:53:45 2006 +++ llvm/include/llvm/CodeGen/AsmPrinter.h Mon May 1 20:16:28 2006 @@ -21,6 +21,7 @@ namespace llvm { class Constant; + class ConstantArray; class Mangler; class GlobalVariable; @@ -253,7 +254,11 @@ /// EmitZeros - Emit a block of zeros. /// - void EmitZeros(uint64_t NumZeros) const; + virtual void EmitZeros(uint64_t NumZeros) const; + + /// EmitString - Emit a zero-byte-terminated string constant. + /// + virtual void EmitString(const ConstantArray *CVA) const; /// EmitConstantValueOnly - Print out the specified constant, without a /// storage class. Only constants of first-class type are allowed here. From jeffc at jolt-lang.org Mon May 1 20:16:43 2006 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Mon, 1 May 2006 20:16:43 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86IntelAsmPrinter.cpp X86IntelAsmPrinter.h Message-ID: <200605020116.UAA01206@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86IntelAsmPrinter.cpp updated: 1.31 -> 1.32 X86IntelAsmPrinter.h updated: 1.15 -> 1.16 --- Log message: Make Intel syntax mode friendlier to Microsoft ML assembler (still needs more work). --- Diffs of the changes: (+97 -17) X86IntelAsmPrinter.cpp | 106 ++++++++++++++++++++++++++++++++++++++++++------- X86IntelAsmPrinter.h | 8 ++- 2 files changed, 97 insertions(+), 17 deletions(-) Index: llvm/lib/Target/X86/X86IntelAsmPrinter.cpp diff -u llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.31 llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.32 --- llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.31 Mon May 1 00:53:50 2006 +++ llvm/lib/Target/X86/X86IntelAsmPrinter.cpp Mon May 1 20:16:28 2006 @@ -15,12 +15,31 @@ #include "X86IntelAsmPrinter.h" #include "X86.h" +#include "llvm/Constants.h" #include "llvm/Module.h" #include "llvm/Assembly/Writer.h" #include "llvm/Support/Mangler.h" #include "llvm/Target/TargetOptions.h" using namespace llvm; +X86IntelAsmPrinter::X86IntelAsmPrinter(std::ostream &O, X86TargetMachine &TM) + : X86SharedAsmPrinter(O, TM) { + CommentString = ";"; + GlobalPrefix = "_"; + PrivateGlobalPrefix = "$"; + AlignDirective = "\talign\t"; + ZeroDirective = 0; + AsciiDirective = "\tdb\t"; + AscizDirective = 0; + Data8bitsDirective = "\t.db\t"; + Data16bitsDirective = "\t.dw\t"; + Data32bitsDirective = "\t.dd\t"; + Data64bitsDirective = "\t.dq\t"; + HasDotTypeDotSizeDirective = false; + + O << "\t.686\n\t.model flat\n\toption dotname\n"; +} + /// runOnMachineFunction - This uses the printMachineInstruction() /// method to print assembly for each instruction. /// @@ -38,12 +57,11 @@ EmitConstantPool(MF.getConstantPool()); // Print out labels for the function. - SwitchSection("\t.text\n", MF.getFunction()); + SwitchSection(".code\n", MF.getFunction()); EmitAlignment(4); - O << "\t.globl\t" << CurrentFnName << "\n"; - if (HasDotTypeDotSizeDirective) - O << "\t.type\t" << CurrentFnName << ", @function\n"; - O << CurrentFnName << ":\n"; + if (MF.getFunction()->getLinkage() == GlobalValue::ExternalLinkage) + O << "\tpublic " << CurrentFnName << "\n"; + O << CurrentFnName << "\tproc near\n"; if (forDarwin) { // Emit pre-function debug information. @@ -71,6 +89,8 @@ DW.EndFunction(); } + O << CurrentFnName << "\tendp\n"; + // We didn't modify anything. return false; } @@ -403,17 +423,75 @@ bool X86IntelAsmPrinter::doInitialization(Module &M) { X86SharedAsmPrinter::doInitialization(M); - // Tell gas we are outputting Intel syntax (not AT&T syntax) assembly. - // - // Bug: gas in `intel_syntax noprefix' mode interprets the symbol `Sp' in an - // instruction as a reference to the register named sp, and if you try to - // reference a symbol `Sp' (e.g. `mov ECX, OFFSET Sp') then it gets lowercased - // before being looked up in the symbol table. This creates spurious - // `undefined symbol' errors when linking. Workaround: Do not use `noprefix' - // mode, and decorate all register names with percent signs. - O << "\t.intel_syntax\n"; + Mang->markCharUnacceptable('.'); return false; } +void X86IntelAsmPrinter::EmitZeros(uint64_t NumZeros) const { + if (NumZeros) { + O << "\tdb " << NumZeros << " dup(0)\n"; + } +} + +void X86IntelAsmPrinter::EmitString(const ConstantArray *CVA) const { + unsigned NumElts = CVA->getNumOperands(); + if (NumElts) { + // ML does not have escape sequences except '' for '. It also has a maximum + // string length of 255. + unsigned len = 0; + bool inString = false; + for (unsigned i = 0; i < NumElts; i++) { + int n = cast(CVA->getOperand(i))->getRawValue() & 255; + if (len == 0) + O << "\tdb "; + + if (n >= 32 && n <= 127) { + if (!inString) { + if (len > 0) { + O << ",'"; + len += 2; + } else { + O << "'"; + len++; + } + inString = true; + } + if (n == '\'') { + O << "'"; + len++; + } + O << char(n); + } else { + if (inString) { + O << "'"; + len++; + inString = false; + } + if (len > 0) { + O << ","; + len++; + } + O << n; + len += 1 + (n > 9) + (n > 99); + } + + if (len > 60) { + if (inString) { + O << "'"; + inString = false; + } + O << "\n"; + len = 0; + } + } + + if (len > 0) { + if (inString) + O << "'"; + O << "\n"; + } + } +} + // Include the auto-generated portion of the assembly writer. #include "X86GenAsmWriter1.inc" Index: llvm/lib/Target/X86/X86IntelAsmPrinter.h diff -u llvm/lib/Target/X86/X86IntelAsmPrinter.h:1.15 llvm/lib/Target/X86/X86IntelAsmPrinter.h:1.16 --- llvm/lib/Target/X86/X86IntelAsmPrinter.h:1.15 Mon May 1 00:53:50 2006 +++ llvm/lib/Target/X86/X86IntelAsmPrinter.h Mon May 1 20:16:28 2006 @@ -21,8 +21,7 @@ namespace llvm { struct X86IntelAsmPrinter : public X86SharedAsmPrinter { - X86IntelAsmPrinter(std::ostream &O, X86TargetMachine &TM) - : X86SharedAsmPrinter(O, TM) { } + X86IntelAsmPrinter(std::ostream &O, X86TargetMachine &TM); virtual const char *getPassName() const { return "X86 Intel-Style Assembly Printer"; @@ -84,13 +83,16 @@ unsigned AsmVariant, const char *ExtraCode); bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode); - void printMachineInstruction(const MachineInstr *MI); + void printMachineInstruction(const MachineInstr *MI); void printOp(const MachineOperand &MO, const char *Modifier = 0); void printSSECC(const MachineInstr *MI, unsigned Op); void printMemReference(const MachineInstr *MI, unsigned Op); void printPICLabel(const MachineInstr *MI, unsigned Op); bool runOnMachineFunction(MachineFunction &F); bool doInitialization(Module &M); + + virtual void EmitZeros(uint64_t NumZeros) const; + virtual void EmitString(const ConstantArray *CVA) const; }; } // end namespace llvm From jeffc at jolt-lang.org Mon May 1 22:12:02 2006 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Mon, 1 May 2006 22:12:02 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/AsmPrinter.h Message-ID: <200605020312.WAA07010@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: AsmPrinter.h updated: 1.33 -> 1.34 --- Log message: Finish support for Microsoft ML/MASM. May still be a few rough edges. --- Diffs of the changes: (+3 -1) AsmPrinter.h | 4 +++- 1 files changed, 3 insertions(+), 1 deletion(-) Index: llvm/include/llvm/CodeGen/AsmPrinter.h diff -u llvm/include/llvm/CodeGen/AsmPrinter.h:1.33 llvm/include/llvm/CodeGen/AsmPrinter.h:1.34 --- llvm/include/llvm/CodeGen/AsmPrinter.h:1.33 Mon May 1 20:16:28 2006 +++ llvm/include/llvm/CodeGen/AsmPrinter.h Mon May 1 22:11:50 2006 @@ -26,10 +26,12 @@ class GlobalVariable; class AsmPrinter : public MachineFunctionPass { + protected: /// CurrentSection - The current section we are emitting to. This is /// controlled and used by the SwitchSection method. std::string CurrentSection; + private: /// FunctionNumber - This provides a unique ID for each function emitted in /// this translation unit. It is autoincremented by SetupMachineFunction, /// and can be accessed with getFunctionNumber() and @@ -185,7 +187,7 @@ /// If the new section is an empty string, this method forgets what the /// current section is, but does not emit a .section directive. /// - void SwitchSection(const char *NewSection, const GlobalValue *GV); + virtual void SwitchSection(const char *NewSection, const GlobalValue *GV); /// getPreferredAlignmentLog - Return the preferred alignment of the /// specified global, returned in log form. This includes an explicitly From jeffc at jolt-lang.org Mon May 1 22:12:02 2006 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Mon, 1 May 2006 22:12:02 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86IntelAsmPrinter.cpp X86IntelAsmPrinter.h Message-ID: <200605020312.WAA07016@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86IntelAsmPrinter.cpp updated: 1.32 -> 1.33 X86IntelAsmPrinter.h updated: 1.16 -> 1.17 --- Log message: Finish support for Microsoft ML/MASM. May still be a few rough edges. --- Diffs of the changes: (+50 -3) X86IntelAsmPrinter.cpp | 51 ++++++++++++++++++++++++++++++++++++++++++++++--- X86IntelAsmPrinter.h | 2 + 2 files changed, 50 insertions(+), 3 deletions(-) Index: llvm/lib/Target/X86/X86IntelAsmPrinter.cpp diff -u llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.32 llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.33 --- llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.32 Mon May 1 20:16:28 2006 +++ llvm/lib/Target/X86/X86IntelAsmPrinter.cpp Mon May 1 22:11:50 2006 @@ -36,8 +36,6 @@ Data32bitsDirective = "\t.dd\t"; Data64bitsDirective = "\t.dq\t"; HasDotTypeDotSizeDirective = false; - - O << "\t.686\n\t.model flat\n\toption dotname\n"; } /// runOnMachineFunction - This uses the printMachineInstruction() @@ -57,7 +55,7 @@ EmitConstantPool(MF.getConstantPool()); // Print out labels for the function. - SwitchSection(".code\n", MF.getFunction()); + SwitchSection(".code", MF.getFunction()); EmitAlignment(4); if (MF.getFunction()->getLinkage() == GlobalValue::ExternalLinkage) O << "\tpublic " << CurrentFnName << "\n"; @@ -424,9 +422,56 @@ bool X86IntelAsmPrinter::doInitialization(Module &M) { X86SharedAsmPrinter::doInitialization(M); Mang->markCharUnacceptable('.'); + PrivateGlobalPrefix = "$"; // need this here too :( + O << "\t.686\n\t.model flat\n\n"; + + // Emit declarations for external functions. + for (Module::iterator I = M.begin(), E = M.end(); I != E; ++I) + if (I->isExternal()) + O << "\textern " << Mang->getValueName(I) << ":near\n"; + + // Emit declarations for external globals. + for (Module::const_global_iterator I = M.global_begin(), E = M.global_end(); + I != E; ++I) { + if (I->isExternal()) + O << "\textern " << Mang->getValueName(I) << ":byte\n"; + } + return false; } +bool X86IntelAsmPrinter::doFinalization(Module &M) { + X86SharedAsmPrinter::doFinalization(M); + if (CurrentSection != "") + O << CurrentSection << "\tends\n"; + O << "\tend\n"; + return false; +} + +void X86IntelAsmPrinter::SwitchSection(const char *NewSection, + const GlobalValue *GV) { + if (*NewSection == 0) + return; + + std::string NS; + bool isData = strcmp(NewSection , ".data") == 0; + + if (GV && GV->hasSection()) + NS = GV->getSection(); + else if (isData) + NS = "_data"; + else + NS = "_text"; + + if (CurrentSection != NS) { + if (CurrentSection != "") + O << CurrentSection << "\tends\n"; + CurrentSection = NS; + O << CurrentSection << (isData ? "\tsegment 'DATA'\n" + : "\tsegment 'CODE'\n"); + } +} + void X86IntelAsmPrinter::EmitZeros(uint64_t NumZeros) const { if (NumZeros) { O << "\tdb " << NumZeros << " dup(0)\n"; Index: llvm/lib/Target/X86/X86IntelAsmPrinter.h diff -u llvm/lib/Target/X86/X86IntelAsmPrinter.h:1.16 llvm/lib/Target/X86/X86IntelAsmPrinter.h:1.17 --- llvm/lib/Target/X86/X86IntelAsmPrinter.h:1.16 Mon May 1 20:16:28 2006 +++ llvm/lib/Target/X86/X86IntelAsmPrinter.h Mon May 1 22:11:50 2006 @@ -90,7 +90,9 @@ void printPICLabel(const MachineInstr *MI, unsigned Op); bool runOnMachineFunction(MachineFunction &F); bool doInitialization(Module &M); + bool doFinalization(Module &M); + virtual void SwitchSection(const char *NewSection, const GlobalValue *GV); virtual void EmitZeros(uint64_t NumZeros) const; virtual void EmitString(const ConstantArray *CVA) const; }; From jeffc at jolt-lang.org Mon May 1 22:46:26 2006 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Mon, 1 May 2006 22:46:26 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/AsmPrinter.cpp Message-ID: <200605020346.WAA08884@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: AsmPrinter.cpp updated: 1.61 -> 1.62 --- Log message: De-virtualize EmitZeroes. --- Diffs of the changes: (+7 -3) AsmPrinter.cpp | 10 +++++++--- 1 files changed, 7 insertions(+), 3 deletions(-) Index: llvm/lib/CodeGen/AsmPrinter.cpp diff -u llvm/lib/CodeGen/AsmPrinter.cpp:1.61 llvm/lib/CodeGen/AsmPrinter.cpp:1.62 --- llvm/lib/CodeGen/AsmPrinter.cpp:1.61 Mon May 1 20:16:28 2006 +++ llvm/lib/CodeGen/AsmPrinter.cpp Mon May 1 22:46:13 2006 @@ -37,6 +37,7 @@ InlineAsmStart("#APP\n\t"), InlineAsmEnd("\t#NO_APP\n"), ZeroDirective("\t.zero\t"), + ZeroDirectiveSuffix(0), AsciiDirective("\t.ascii\t"), AscizDirective("\t.asciz\t"), Data8bitsDirective("\t.byte\t"), @@ -240,9 +241,12 @@ /// void AsmPrinter::EmitZeros(uint64_t NumZeros) const { if (NumZeros) { - if (ZeroDirective) - O << ZeroDirective << NumZeros << "\n"; - else { + if (ZeroDirective) { + O << ZeroDirective << NumZeros; + if (ZeroDirectiveSuffix) + O << ZeroDirectiveSuffix; + O << "\n"; + } else { for (; NumZeros; --NumZeros) O << Data8bitsDirective << "0\n"; } From jeffc at jolt-lang.org Mon May 1 22:46:27 2006 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Mon, 1 May 2006 22:46:27 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86IntelAsmPrinter.cpp X86IntelAsmPrinter.h Message-ID: <200605020346.WAA08894@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86IntelAsmPrinter.cpp updated: 1.33 -> 1.34 X86IntelAsmPrinter.h updated: 1.17 -> 1.18 --- Log message: De-virtualize EmitZeroes. --- Diffs of the changes: (+2 -8) X86IntelAsmPrinter.cpp | 9 ++------- X86IntelAsmPrinter.h | 1 - 2 files changed, 2 insertions(+), 8 deletions(-) Index: llvm/lib/Target/X86/X86IntelAsmPrinter.cpp diff -u llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.33 llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.34 --- llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.33 Mon May 1 22:11:50 2006 +++ llvm/lib/Target/X86/X86IntelAsmPrinter.cpp Mon May 1 22:46:13 2006 @@ -28,7 +28,8 @@ GlobalPrefix = "_"; PrivateGlobalPrefix = "$"; AlignDirective = "\talign\t"; - ZeroDirective = 0; + ZeroDirective = "\tdb\t"; + ZeroDirectiveSuffix = " dup(0)"; AsciiDirective = "\tdb\t"; AscizDirective = 0; Data8bitsDirective = "\t.db\t"; @@ -472,12 +473,6 @@ } } -void X86IntelAsmPrinter::EmitZeros(uint64_t NumZeros) const { - if (NumZeros) { - O << "\tdb " << NumZeros << " dup(0)\n"; - } -} - void X86IntelAsmPrinter::EmitString(const ConstantArray *CVA) const { unsigned NumElts = CVA->getNumOperands(); if (NumElts) { Index: llvm/lib/Target/X86/X86IntelAsmPrinter.h diff -u llvm/lib/Target/X86/X86IntelAsmPrinter.h:1.17 llvm/lib/Target/X86/X86IntelAsmPrinter.h:1.18 --- llvm/lib/Target/X86/X86IntelAsmPrinter.h:1.17 Mon May 1 22:11:50 2006 +++ llvm/lib/Target/X86/X86IntelAsmPrinter.h Mon May 1 22:46:13 2006 @@ -93,7 +93,6 @@ bool doFinalization(Module &M); virtual void SwitchSection(const char *NewSection, const GlobalValue *GV); - virtual void EmitZeros(uint64_t NumZeros) const; virtual void EmitString(const ConstantArray *CVA) const; }; From jeffc at jolt-lang.org Mon May 1 22:46:27 2006 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Mon, 1 May 2006 22:46:27 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/AsmPrinter.h Message-ID: <200605020346.WAA08888@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: AsmPrinter.h updated: 1.34 -> 1.35 --- Log message: De-virtualize EmitZeroes. --- Diffs of the changes: (+2 -1) AsmPrinter.h | 3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index: llvm/include/llvm/CodeGen/AsmPrinter.h diff -u llvm/include/llvm/CodeGen/AsmPrinter.h:1.34 llvm/include/llvm/CodeGen/AsmPrinter.h:1.35 --- llvm/include/llvm/CodeGen/AsmPrinter.h:1.34 Mon May 1 22:11:50 2006 +++ llvm/include/llvm/CodeGen/AsmPrinter.h Mon May 1 22:46:13 2006 @@ -101,6 +101,7 @@ /// "\t.zero\t" and "\t.space\t". If this is set to null, the /// Data*bitsDirective's will be used to emit zero bytes. const char *ZeroDirective; // Defaults to "\t.zero\t" + const char *ZeroDirectiveSuffix; // Defaults to "" /// AsciiDirective - This directive allows emission of an ascii string with /// the standard C escape characters embedded into it. @@ -256,7 +257,7 @@ /// EmitZeros - Emit a block of zeros. /// - virtual void EmitZeros(uint64_t NumZeros) const; + void EmitZeros(uint64_t NumZeros) const; /// EmitString - Emit a zero-byte-terminated string constant. /// From jeffc at jolt-lang.org Mon May 1 22:58:58 2006 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Mon, 1 May 2006 22:58:58 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/AsmPrinter.h Message-ID: <200605020358.WAA12350@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: AsmPrinter.h updated: 1.35 -> 1.36 --- Log message: De-virtualize SwitchSection. --- Diffs of the changes: (+2 -3) AsmPrinter.h | 5 ++--- 1 files changed, 2 insertions(+), 3 deletions(-) Index: llvm/include/llvm/CodeGen/AsmPrinter.h diff -u llvm/include/llvm/CodeGen/AsmPrinter.h:1.35 llvm/include/llvm/CodeGen/AsmPrinter.h:1.36 --- llvm/include/llvm/CodeGen/AsmPrinter.h:1.35 Mon May 1 22:46:13 2006 +++ llvm/include/llvm/CodeGen/AsmPrinter.h Mon May 1 22:58:45 2006 @@ -26,12 +26,10 @@ class GlobalVariable; class AsmPrinter : public MachineFunctionPass { - protected: /// CurrentSection - The current section we are emitting to. This is /// controlled and used by the SwitchSection method. std::string CurrentSection; - private: /// FunctionNumber - This provides a unique ID for each function emitted in /// this translation unit. It is autoincremented by SetupMachineFunction, /// and can be accessed with getFunctionNumber() and @@ -139,6 +137,7 @@ /// emit a global to an arbitrary section. The section name is emited after /// this. const char *SwitchToSectionDirective; // Defaults to "\t.section\t" + bool MLSections; // True if Microsoft ML assembler is targetted /// ConstantPoolSection - This is the section that we SwitchToSection right /// before emitting the constant pool for a function. @@ -188,7 +187,7 @@ /// If the new section is an empty string, this method forgets what the /// current section is, but does not emit a .section directive. /// - virtual void SwitchSection(const char *NewSection, const GlobalValue *GV); + void SwitchSection(const char *NewSection, const GlobalValue *GV); /// getPreferredAlignmentLog - Return the preferred alignment of the /// specified global, returned in log form. This includes an explicitly From jeffc at jolt-lang.org Mon May 1 22:58:59 2006 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Mon, 1 May 2006 22:58:59 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/AsmPrinter.cpp Message-ID: <200605020358.WAA12354@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: AsmPrinter.cpp updated: 1.62 -> 1.63 --- Log message: De-virtualize SwitchSection. --- Diffs of the changes: (+42 -10) AsmPrinter.cpp | 52 ++++++++++++++++++++++++++++++++++++++++++---------- 1 files changed, 42 insertions(+), 10 deletions(-) Index: llvm/lib/CodeGen/AsmPrinter.cpp diff -u llvm/lib/CodeGen/AsmPrinter.cpp:1.62 llvm/lib/CodeGen/AsmPrinter.cpp:1.63 --- llvm/lib/CodeGen/AsmPrinter.cpp:1.62 Mon May 1 22:46:13 2006 +++ llvm/lib/CodeGen/AsmPrinter.cpp Mon May 1 22:58:45 2006 @@ -47,6 +47,7 @@ AlignDirective("\t.align\t"), AlignmentIsInBytes(true), SwitchToSectionDirective("\t.section\t"), + MLSections(false), ConstantPoolSection("\t.section .rodata\n"), JumpTableSection("\t.section .rodata\n"), StaticCtorsSection("\t.section .ctors,\"aw\", at progbits"), @@ -63,16 +64,47 @@ /// void AsmPrinter::SwitchSection(const char *NewSection, const GlobalValue *GV) { std::string NS; - - if (GV && GV->hasSection()) - NS = SwitchToSectionDirective + GV->getSection(); - else - NS = std::string("\t")+NewSection; - - if (CurrentSection != NS) { - CurrentSection = NS; - if (!CurrentSection.empty()) - O << CurrentSection << '\n'; + + // Microsoft ML/MASM has a fundamentally different approach to handling + // sections. + + if (MLSections) { + if (*NewSection == 0) { + // Simply end the current section, if any. + if (CurrentSection != "") { + O << CurrentSection << "\tends\n"; + CurrentSection = ""; + } + return; + } + + bool isData = strcmp(NewSection , ".data") == 0; + + if (GV && GV->hasSection()) + NS = GV->getSection(); + else if (isData) + NS = "_data"; + else + NS = "_text"; + + if (CurrentSection != NS) { + if (CurrentSection != "") + O << CurrentSection << "\tends\n"; + CurrentSection = NS; + O << CurrentSection << (isData ? "\tsegment 'DATA'\n" + : "\tsegment 'CODE'\n"); + } + } else { + if (GV && GV->hasSection()) + NS = SwitchToSectionDirective + GV->getSection(); + else + NS = std::string("\t")+NewSection; + + if (CurrentSection != NS) { + CurrentSection = NS; + if (!CurrentSection.empty()) + O << CurrentSection << '\n'; + } } } From jeffc at jolt-lang.org Mon May 1 22:58:59 2006 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Mon, 1 May 2006 22:58:59 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86IntelAsmPrinter.cpp X86IntelAsmPrinter.h Message-ID: <200605020358.WAA12360@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86IntelAsmPrinter.cpp updated: 1.34 -> 1.35 X86IntelAsmPrinter.h updated: 1.18 -> 1.19 --- Log message: De-virtualize SwitchSection. --- Diffs of the changes: (+2 -27) X86IntelAsmPrinter.cpp | 28 ++-------------------------- X86IntelAsmPrinter.h | 1 - 2 files changed, 2 insertions(+), 27 deletions(-) Index: llvm/lib/Target/X86/X86IntelAsmPrinter.cpp diff -u llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.34 llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.35 --- llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.34 Mon May 1 22:46:13 2006 +++ llvm/lib/Target/X86/X86IntelAsmPrinter.cpp Mon May 1 22:58:45 2006 @@ -28,6 +28,7 @@ GlobalPrefix = "_"; PrivateGlobalPrefix = "$"; AlignDirective = "\talign\t"; + MLSections = true; ZeroDirective = "\tdb\t"; ZeroDirectiveSuffix = " dup(0)"; AsciiDirective = "\tdb\t"; @@ -443,36 +444,11 @@ bool X86IntelAsmPrinter::doFinalization(Module &M) { X86SharedAsmPrinter::doFinalization(M); - if (CurrentSection != "") - O << CurrentSection << "\tends\n"; + SwitchSection("", 0); O << "\tend\n"; return false; } -void X86IntelAsmPrinter::SwitchSection(const char *NewSection, - const GlobalValue *GV) { - if (*NewSection == 0) - return; - - std::string NS; - bool isData = strcmp(NewSection , ".data") == 0; - - if (GV && GV->hasSection()) - NS = GV->getSection(); - else if (isData) - NS = "_data"; - else - NS = "_text"; - - if (CurrentSection != NS) { - if (CurrentSection != "") - O << CurrentSection << "\tends\n"; - CurrentSection = NS; - O << CurrentSection << (isData ? "\tsegment 'DATA'\n" - : "\tsegment 'CODE'\n"); - } -} - void X86IntelAsmPrinter::EmitString(const ConstantArray *CVA) const { unsigned NumElts = CVA->getNumOperands(); if (NumElts) { Index: llvm/lib/Target/X86/X86IntelAsmPrinter.h diff -u llvm/lib/Target/X86/X86IntelAsmPrinter.h:1.18 llvm/lib/Target/X86/X86IntelAsmPrinter.h:1.19 --- llvm/lib/Target/X86/X86IntelAsmPrinter.h:1.18 Mon May 1 22:46:13 2006 +++ llvm/lib/Target/X86/X86IntelAsmPrinter.h Mon May 1 22:58:45 2006 @@ -92,7 +92,6 @@ bool doInitialization(Module &M); bool doFinalization(Module &M); - virtual void SwitchSection(const char *NewSection, const GlobalValue *GV); virtual void EmitString(const ConstantArray *CVA) const; }; From lattner at cs.uiuc.edu Mon May 1 23:24:33 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 1 May 2006 23:24:33 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Transforms/Scalar.h Message-ID: <200605020424.XAA16066@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/Transforms: Scalar.h updated: 1.63 -> 1.64 --- Log message: Add pass ID's for various passes, so they can be AddRequiredID. Patch by Domagoj Babic! --- Diffs of the changes: (+20 -14) Scalar.h | 34 ++++++++++++++++++++-------------- 1 files changed, 20 insertions(+), 14 deletions(-) Index: llvm/include/llvm/Transforms/Scalar.h diff -u llvm/include/llvm/Transforms/Scalar.h:1.63 llvm/include/llvm/Transforms/Scalar.h:1.64 --- llvm/include/llvm/Transforms/Scalar.h:1.63 Thu Apr 20 10:45:54 2006 +++ llvm/include/llvm/Transforms/Scalar.h Mon May 1 23:24:20 2006 @@ -163,6 +163,7 @@ // ret int %Y // FunctionPass *createPromoteMemoryToRegisterPass(); +extern const PassInfo *PromoteMemoryToRegisterID; //===----------------------------------------------------------------------===// // @@ -240,31 +241,36 @@ extern const PassInfo *LoopSimplifyID; //===----------------------------------------------------------------------===// +// This pass converts SelectInst instructions into conditional branch and PHI +// instructions. If the OnlyFP flag is set to true, then only floating point +// select instructions are lowered. // -// This pass eliminates call instructions to the current function which occur -// immediately before return instructions. -// -FunctionPass *createTailCallEliminationPass(); - +FunctionPass *createLowerSelectPass(bool OnlyFP = false); +extern const PassInfo *LowerSelectID; //===----------------------------------------------------------------------===// -// This pass convert malloc and free instructions to %malloc & %free function -// calls. +// +// LowerAllocations Pass - Turn malloc and free instructions into %malloc and +// %free calls. +// +// AU.addRequiredID(LowerAllocationsID); // FunctionPass *createLowerAllocationsPass(bool LowerMallocArgToInteger = false); +extern const PassInfo *LowerAllocationsID; //===----------------------------------------------------------------------===// -// This pass converts SwitchInst instructions into a sequence of chained binary -// branch instructions. // -FunctionPass *createLowerSwitchPass(); +// This pass eliminates call instructions to the current function which occur +// immediately before return instructions. +// +FunctionPass *createTailCallEliminationPass(); //===----------------------------------------------------------------------===// -// This pass converts SelectInst instructions into conditional branch and PHI -// instructions. If the OnlyFP flag is set to true, then only floating point -// select instructions are lowered. +// This pass converts SwitchInst instructions into a sequence of chained binary +// branch instructions. // -FunctionPass *createLowerSelectPass(bool OnlyFP = false); +FunctionPass *createLowerSwitchPass(); +extern const PassInfo *LowerSwitchID; //===----------------------------------------------------------------------===// // This pass converts PackedType operations into low-level scalar operations. From lattner at cs.uiuc.edu Mon May 1 23:24:49 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 1 May 2006 23:24:49 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/LowerAllocations.cpp LowerSelect.cpp LowerSwitch.cpp Mem2Reg.cpp Message-ID: <200605020424.XAA16095@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: LowerAllocations.cpp updated: 1.55 -> 1.56 LowerSelect.cpp updated: 1.3 -> 1.4 LowerSwitch.cpp updated: 1.18 -> 1.19 Mem2Reg.cpp updated: 1.14 -> 1.15 --- Log message: Add pass ID's for various passes, so they can be AddRequiredID. Patch by Domagoj Babic! --- Diffs of the changes: (+8 -0) LowerAllocations.cpp | 2 ++ LowerSelect.cpp | 2 ++ LowerSwitch.cpp | 2 ++ Mem2Reg.cpp | 2 ++ 4 files changed, 8 insertions(+) Index: llvm/lib/Transforms/Scalar/LowerAllocations.cpp diff -u llvm/lib/Transforms/Scalar/LowerAllocations.cpp:1.55 llvm/lib/Transforms/Scalar/LowerAllocations.cpp:1.56 --- llvm/lib/Transforms/Scalar/LowerAllocations.cpp:1.55 Sat Oct 22 23:37:20 2005 +++ llvm/lib/Transforms/Scalar/LowerAllocations.cpp Mon May 1 23:24:36 2006 @@ -60,6 +60,8 @@ X("lowerallocs", "Lower allocations from instructions to calls"); } +// Publically exposed interface to pass... +const PassInfo *llvm::LowerAllocationsID = X.getPassInfo(); // createLowerAllocationsPass - Interface to this file... FunctionPass *llvm::createLowerAllocationsPass(bool LowerMallocArgToInteger) { return new LowerAllocations(LowerMallocArgToInteger); Index: llvm/lib/Transforms/Scalar/LowerSelect.cpp diff -u llvm/lib/Transforms/Scalar/LowerSelect.cpp:1.3 llvm/lib/Transforms/Scalar/LowerSelect.cpp:1.4 --- llvm/lib/Transforms/Scalar/LowerSelect.cpp:1.3 Thu Apr 21 18:45:12 2005 +++ llvm/lib/Transforms/Scalar/LowerSelect.cpp Mon May 1 23:24:36 2006 @@ -47,6 +47,8 @@ X("lowerselect", "Lower select instructions to branches"); } +// Publically exposed interface to pass... +const PassInfo *llvm::LowerSelectID = X.getPassInfo(); //===----------------------------------------------------------------------===// // This pass converts SelectInst instructions into conditional branch and PHI // instructions. If the OnlyFP flag is set to true, then only floating point Index: llvm/lib/Transforms/Scalar/LowerSwitch.cpp diff -u llvm/lib/Transforms/Scalar/LowerSwitch.cpp:1.18 llvm/lib/Transforms/Scalar/LowerSwitch.cpp:1.19 --- llvm/lib/Transforms/Scalar/LowerSwitch.cpp:1.18 Sun Jan 22 17:32:06 2006 +++ llvm/lib/Transforms/Scalar/LowerSwitch.cpp Mon May 1 23:24:36 2006 @@ -60,6 +60,8 @@ X("lowerswitch", "Lower SwitchInst's to branches"); } +// Publically exposed interface to pass... +const PassInfo *llvm::LowerSwitchID = X.getPassInfo(); // createLowerSwitchPass - Interface to this file... FunctionPass *llvm::createLowerSwitchPass() { return new LowerSwitch(); Index: llvm/lib/Transforms/Scalar/Mem2Reg.cpp diff -u llvm/lib/Transforms/Scalar/Mem2Reg.cpp:1.14 llvm/lib/Transforms/Scalar/Mem2Reg.cpp:1.15 --- llvm/lib/Transforms/Scalar/Mem2Reg.cpp:1.14 Thu Apr 21 18:45:12 2005 +++ llvm/lib/Transforms/Scalar/Mem2Reg.cpp Mon May 1 23:24:36 2006 @@ -74,6 +74,8 @@ return Changed; } +// Publically exposed interface to pass... +const PassInfo *llvm::PromoteMemoryToRegisterID = X.getPassInfo(); // createPromoteMemoryToRegister - Provide an entry point to create this pass. // FunctionPass *llvm::createPromoteMemoryToRegisterPass() { From natebegeman at mac.com Mon May 1 23:50:19 2006 From: natebegeman at mac.com (Nate Begeman) Date: Mon, 1 May 2006 23:50:19 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCJITInfo.cpp Message-ID: <200605020450.XAA17649@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCJITInfo.cpp updated: 1.19 -> 1.20 --- Log message: Update the PPC compilation callback code to not need weird abi-violating prologs and epilogs, keep all the asm in one place, and remove use of compiler builtin functions. --- Diffs of the changes: (+46 -49) PPCJITInfo.cpp | 95 +++++++++++++++++++++++++++------------------------------ 1 files changed, 46 insertions(+), 49 deletions(-) Index: llvm/lib/Target/PowerPC/PPCJITInfo.cpp diff -u llvm/lib/Target/PowerPC/PPCJITInfo.cpp:1.19 llvm/lib/Target/PowerPC/PPCJITInfo.cpp:1.20 --- llvm/lib/Target/PowerPC/PPCJITInfo.cpp:1.19 Mon Apr 24 23:45:59 2006 +++ llvm/lib/Target/PowerPC/PPCJITInfo.cpp Mon May 1 23:50:05 2006 @@ -60,23 +60,51 @@ ".align 2\n" ".globl _PPC32CompilationCallback\n" "_PPC32CompilationCallback:\n" - // Make space for 29 ints r[3-31] and 14 doubles f[0-13] - "stwu r1, -272(r1)\n" - "mflr r11\n" - "stw r11, 280(r1)\n" // Set up a proper stack frame - "stmw r3, 156(r1)\n" // Save all of the integer registers + // Make space for 8 ints r[3-10] and 13 doubles f[1-13] and the + // FIXME: need to save v[0-19] for altivec? + // Set up a proper stack frame + "stwu r1, -208(r1)\n" + "mflr r0\n" + "stw r0, 216(r1)\n" + // Save all int arg registers + "stw r10, 204(r1)\n" "stw r9, 200(r1)\n" + "stw r8, 196(r1)\n" "stw r7, 192(r1)\n" + "stw r6, 188(r1)\n" "stw r5, 184(r1)\n" + "stw r4, 180(r1)\n" "stw r3, 176(r1)\n" // Save all call-clobbered FP regs. - "stfd f1, 44(r1)\n" "stfd f2, 52(r1)\n" "stfd f3, 60(r1)\n" - "stfd f4, 68(r1)\n" "stfd f5, 76(r1)\n" "stfd f6, 84(r1)\n" - "stfd f7, 92(r1)\n" "stfd f8, 100(r1)\n" "stfd f9, 108(r1)\n" - "stfd f10, 116(r1)\n" "stfd f11, 124(r1)\n" "stfd f12, 132(r1)\n" - "stfd f13, 140(r1)\n" - - // Now that everything is saved, go to the C compilation callback function, - // passing the address of the intregs and fpregs. - "addi r3, r1, 156\n" // &IntRegs[0] - "addi r4, r1, 44\n" // &FPRegs[0] + "stfd f13, 168(r1)\n" "stfd f12, 160(r1)\n" + "stfd f11, 152(r1)\n" "stfd f10, 144(r1)\n" + "stfd f9, 136(r1)\n" "stfd f8, 128(r1)\n" + "stfd f7, 120(r1)\n" "stfd f6, 112(r1)\n" + "stfd f5, 104(r1)\n" "stfd f4, 96(r1)\n" + "stfd f3, 88(r1)\n" "stfd f2, 80(r1)\n" + "stfd f1, 72(r1)\n" + // Arguments to Compilation Callback: + // r3 - our lr (address of the call instruction in stub plus 4) + // r4 - stub's lr (address of instruction that called the stub plus 4) + "mr r3, r0\n" + "lwz r2, 208(r1)\n" // stub's frame + "lwz r4, 8(r2)\n" // stub's lr "bl _PPC32CompilationCallbackC\n" + "mtctr r3\n" + // Restore all int arg registers + "lwz r10, 204(r1)\n" "lwz r9, 200(r1)\n" + "lwz r8, 196(r1)\n" "lwz r7, 192(r1)\n" + "lwz r6, 188(r1)\n" "lwz r5, 184(r1)\n" + "lwz r4, 180(r1)\n" "lwz r3, 176(r1)\n" + // Restore all FP arg registers + "lfd f13, 168(r1)\n" "lfd f12, 160(r1)\n" + "lfd f11, 152(r1)\n" "lfd f10, 144(r1)\n" + "lfd f9, 136(r1)\n" "lfd f8, 128(r1)\n" + "lfd f7, 120(r1)\n" "lfd f6, 112(r1)\n" + "lfd f5, 104(r1)\n" "lfd f4, 96(r1)\n" + "lfd f3, 88(r1)\n" "lfd f2, 80(r1)\n" + "lfd f1, 72(r1)\n" + // Pop 3 frames off the stack and branch to target + "lwz r1, 208(r1)\n" + "lwz r2, 8(r1)\n" + "mtlr r2\n" + "bctr\n" ); #else void PPC32CompilationCallback() { @@ -85,12 +113,8 @@ } #endif -extern "C" void PPC32CompilationCallbackC(unsigned *IntRegs, double *FPRegs) { - unsigned *StubCallAddrPlus4 = (unsigned*)__builtin_return_address(0+1); - unsigned *OrigCallAddrPlus4 = (unsigned*)__builtin_return_address(1+1); - unsigned *CurStackPtr = (unsigned*)__builtin_frame_address(0); - unsigned *OrigStackPtr = (unsigned*)__builtin_frame_address(2+1); - +extern "C" unsigned *PPC32CompilationCallbackC(unsigned *StubCallAddrPlus4, + unsigned *OrigCallAddrPlus4) { // Adjust the pointer to the address of the call instruction in the stub // emitted by emitFunctionStub, rather than the instruction after it. unsigned *StubCallAddr = StubCallAddrPlus4 - 1; @@ -124,37 +148,10 @@ // who took the address of the stub. EmitBranchToAt(StubCallAddr, Target, false); - // Change the stored stack pointer so that we pop three stack frames: - // 1. PPC32CompilationCallbackC's frame - // 2. _PPC32CompilationCallback's frame - // 3. the stub's frame - *CurStackPtr = (intptr_t)OrigStackPtr; - // Put the address of the target function to call and the address to return to // after calling the target function in a place that is easy to get on the // stack after we restore all regs. - CurStackPtr[2] = (intptr_t)Target; - CurStackPtr[1] = (intptr_t)OrigCallAddrPlus4; - - // Note, this is not a standard epilog! -#if defined(__POWERPC__) || defined (__ppc__) || defined(_POWER) - register unsigned *IRR asm ("r2") = IntRegs; - register double *FRR asm ("r3") = FPRegs; - __asm__ __volatile__ ( - "lfd f1, 0(%0)\n" "lfd f2, 8(%0)\n" "lfd f3, 16(%0)\n" - "lfd f4, 24(%0)\n" "lfd f5, 32(%0)\n" "lfd f6, 40(%0)\n" - "lfd f7, 48(%0)\n" "lfd f8, 56(%0)\n" "lfd f9, 64(%0)\n" - "lfd f10, 72(%0)\n" "lfd f11, 80(%0)\n" "lfd f12, 88(%0)\n" - "lfd f13, 96(%0)\n" - "lmw r3, 0(%1)\n" // Load all integer regs - "lwz r0,4(r1)\n" // Get OrigCallAddrPlus4 (LR value when stub was called) - "mtlr r0\n" // Put it in the LR register - "lwz r0,8(r1)\n" // Get target function pointer - "mtctr r0\n" // Put it into the CTR register - "lwz r1,0(r1)\n" // Pop three frames off - "bctr\n" :: // Call target function - "b" (FRR), "b" (IRR)); -#endif + return (unsigned *)Target; } From natebegeman at mac.com Tue May 2 00:37:48 2006 From: natebegeman at mac.com (Nate Begeman) Date: Tue, 2 May 2006 00:37:48 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/AsmPrinter.h Message-ID: <200605020537.AAA22416@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: AsmPrinter.h updated: 1.36 -> 1.37 --- Log message: Extend printBasicBlockLabel a bit so that it can be used to print all basic block labels, consolidating the code to do so in one place for each target. --- Diffs of the changes: (+3 -1) AsmPrinter.h | 4 +++- 1 files changed, 3 insertions(+), 1 deletion(-) Index: llvm/include/llvm/CodeGen/AsmPrinter.h diff -u llvm/include/llvm/CodeGen/AsmPrinter.h:1.36 llvm/include/llvm/CodeGen/AsmPrinter.h:1.37 --- llvm/include/llvm/CodeGen/AsmPrinter.h:1.36 Mon May 1 22:58:45 2006 +++ llvm/include/llvm/CodeGen/AsmPrinter.h Tue May 2 00:37:32 2006 @@ -276,7 +276,9 @@ /// printBasicBlockLabel - This method prints the label for the specified /// MachineBasicBlock - virtual void printBasicBlockLabel(const MachineBasicBlock *MBB) const; + virtual void printBasicBlockLabel(const MachineBasicBlock *MBB, + bool printColon = false, + bool printComment = true) const; private: void EmitXXStructorList(Constant *List); From natebegeman at mac.com Tue May 2 00:37:49 2006 From: natebegeman at mac.com (Nate Begeman) Date: Tue, 2 May 2006 00:37:49 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp Message-ID: <200605020537.AAA22420@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCAsmPrinter.cpp updated: 1.164 -> 1.165 --- Log message: Extend printBasicBlockLabel a bit so that it can be used to print all basic block labels, consolidating the code to do so in one place for each target. --- Diffs of the changes: (+13 -9) PPCAsmPrinter.cpp | 22 +++++++++++++--------- 1 files changed, 13 insertions(+), 9 deletions(-) Index: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp diff -u llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.164 llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.165 --- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.164 Sat Apr 22 13:53:45 2006 +++ llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp Tue May 2 00:37:32 2006 @@ -233,7 +233,9 @@ printOperand(MI, OpNo+1); } - virtual void printBasicBlockLabel(const MachineBasicBlock *MBB) const; + virtual void printBasicBlockLabel(const MachineBasicBlock *MBB, + bool printColon = false, + bool printComment = true) const; virtual bool runOnMachineFunction(MachineFunction &F) = 0; virtual bool doFinalization(Module &M) = 0; @@ -505,10 +507,15 @@ return; } -void PPCAsmPrinter::printBasicBlockLabel(const MachineBasicBlock *MBB) const { +void PPCAsmPrinter::printBasicBlockLabel(const MachineBasicBlock *MBB, + bool printColon, + bool printComment) const { O << PrivateGlobalPrefix << "BB" << getFunctionNumber() << "_" - << MBB->getNumber() << '\t' << CommentString - << MBB->getBasicBlock()->getName(); + << MBB->getNumber(); + if (printColon) + O << ':'; + if (printComment) + O << '\t' << CommentString << MBB->getBasicBlock()->getName(); } /// runOnMachineFunction - This uses the printMachineInstruction() @@ -557,11 +564,8 @@ I != E; ++I) { // Print a label for the basic block. if (I != MF.begin()) { - O << PrivateGlobalPrefix << "BB" << getFunctionNumber() << '_' - << I->getNumber() << ":\t"; - if (!I->getBasicBlock()->getName().empty()) - O << CommentString << " " << I->getBasicBlock()->getName(); - O << "\n"; + printBasicBlockLabel(I, true); + O << '\n'; } for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end(); II != E; ++II) { From natebegeman at mac.com Tue May 2 00:37:49 2006 From: natebegeman at mac.com (Nate Begeman) Date: Tue, 2 May 2006 00:37:49 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/IA64/IA64AsmPrinter.cpp Message-ID: <200605020537.AAA22430@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/IA64: IA64AsmPrinter.cpp updated: 1.26 -> 1.27 --- Log message: Extend printBasicBlockLabel a bit so that it can be used to print all basic block labels, consolidating the code to do so in one place for each target. --- Diffs of the changes: (+4 -4) IA64AsmPrinter.cpp | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) Index: llvm/lib/Target/IA64/IA64AsmPrinter.cpp diff -u llvm/lib/Target/IA64/IA64AsmPrinter.cpp:1.26 llvm/lib/Target/IA64/IA64AsmPrinter.cpp:1.27 --- llvm/lib/Target/IA64/IA64AsmPrinter.cpp:1.26 Sat Apr 22 13:53:45 2006 +++ llvm/lib/Target/IA64/IA64AsmPrinter.cpp Tue May 2 00:37:32 2006 @@ -153,10 +153,10 @@ for (MachineFunction::const_iterator I = MF.begin(), E = MF.end(); I != E; ++I) { // Print a label for the basic block if there are any predecessors. - if (I->pred_begin() != I->pred_end()) - O << PrivateGlobalPrefix << "LBB" << CurrentFnName << "_" - << I->getNumber() << ":\t" - << CommentString << " " << I->getBasicBlock()->getName() << "\n"; + if (I->pred_begin() != I->pred_end()) { + printBasicBlockLabel(I, true); + O << '\n'; + } for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end(); II != E; ++II) { // Print the assembly for the instruction. From natebegeman at mac.com Tue May 2 00:37:49 2006 From: natebegeman at mac.com (Nate Begeman) Date: Tue, 2 May 2006 00:37:49 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp Message-ID: <200605020537.AAA22428@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Alpha: AlphaAsmPrinter.cpp updated: 1.34 -> 1.35 --- Log message: Extend printBasicBlockLabel a bit so that it can be used to print all basic block labels, consolidating the code to do so in one place for each target. --- Diffs of the changes: (+2 -3) AlphaAsmPrinter.cpp | 5 ++--- 1 files changed, 2 insertions(+), 3 deletions(-) Index: llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp diff -u llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.34 llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.35 --- llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.34 Sat Apr 22 13:53:45 2006 +++ llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp Tue May 2 00:37:32 2006 @@ -191,9 +191,8 @@ // Print out code for the function. for (MachineFunction::const_iterator I = MF.begin(), E = MF.end(); I != E; ++I) { - // Print a label for the basic block. - O << PrivateGlobalPrefix << "LBB" << CurrentFnName << "_" << I->getNumber() - << ":\t" << CommentString << " " << I->getBasicBlock()->getName() << "\n"; + printBasicBlockLabel(I, true); + O << '\n'; for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end(); II != E; ++II) { // Print the assembly for the instruction. From natebegeman at mac.com Tue May 2 00:37:49 2006 From: natebegeman at mac.com (Nate Begeman) Date: Tue, 2 May 2006 00:37:49 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp X86AsmPrinter.cpp X86AsmPrinter.h X86IntelAsmPrinter.cpp Message-ID: <200605020537.AAA22442@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ATTAsmPrinter.cpp updated: 1.37 -> 1.38 X86AsmPrinter.cpp updated: 1.173 -> 1.174 X86AsmPrinter.h updated: 1.15 -> 1.16 X86IntelAsmPrinter.cpp updated: 1.35 -> 1.36 --- Log message: Extend printBasicBlockLabel a bit so that it can be used to print all basic block labels, consolidating the code to do so in one place for each target. --- Diffs of the changes: (+20 -14) X86ATTAsmPrinter.cpp | 8 ++++---- X86AsmPrinter.cpp | 14 +++++++++----- X86AsmPrinter.h | 4 +++- X86IntelAsmPrinter.cpp | 8 ++++---- 4 files changed, 20 insertions(+), 14 deletions(-) Index: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp diff -u llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.37 llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.38 --- llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.37 Fri Apr 28 18:19:39 2006 +++ llvm/lib/Target/X86/X86ATTAsmPrinter.cpp Tue May 2 00:37:32 2006 @@ -80,10 +80,10 @@ for (MachineFunction::const_iterator I = MF.begin(), E = MF.end(); I != E; ++I) { // Print a label for the basic block. - if (I->pred_begin() != I->pred_end()) - O << PrivateGlobalPrefix << "BB" << CurrentFnName << "_" << I->getNumber() - << ":\t" << CommentString << " " << I->getBasicBlock()->getName() - << "\n"; + if (I->pred_begin() != I->pred_end()) { + printBasicBlockLabel(I, true); + O << '\n'; + } for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end(); II != E; ++II) { // Print the assembly for the instruction. Index: llvm/lib/Target/X86/X86AsmPrinter.cpp diff -u llvm/lib/Target/X86/X86AsmPrinter.cpp:1.173 llvm/lib/Target/X86/X86AsmPrinter.cpp:1.174 --- llvm/lib/Target/X86/X86AsmPrinter.cpp:1.173 Sat Apr 22 13:53:45 2006 +++ llvm/lib/Target/X86/X86AsmPrinter.cpp Tue May 2 00:37:32 2006 @@ -206,12 +206,16 @@ return false; // success } -void X86SharedAsmPrinter::printBasicBlockLabel(const MachineBasicBlock *MBB) - const { +void X86SharedAsmPrinter::printBasicBlockLabel(const MachineBasicBlock *MBB, + bool printColon, + bool printComment) const { O << PrivateGlobalPrefix << "BB" - << Mang->getValueName(MBB->getParent()->getFunction()) - << "_" << MBB->getNumber() << '\t' << CommentString - << MBB->getBasicBlock()->getName(); + << Mang->getValueName(MBB->getParent()->getFunction()) << "_" + << MBB->getNumber(); + if (printColon) + O << ':'; + if (printComment) + O << '\t' << CommentString << MBB->getBasicBlock()->getName(); } /// createX86CodePrinterPass - Returns a pass that prints the X86 assembly code Index: llvm/lib/Target/X86/X86AsmPrinter.h diff -u llvm/lib/Target/X86/X86AsmPrinter.h:1.15 llvm/lib/Target/X86/X86AsmPrinter.h:1.16 --- llvm/lib/Target/X86/X86AsmPrinter.h:1.15 Sat Apr 22 13:53:45 2006 +++ llvm/lib/Target/X86/X86AsmPrinter.h Tue May 2 00:37:32 2006 @@ -89,7 +89,9 @@ MI->getOperand(Op+3).isConstantPoolIndex()); } - virtual void printBasicBlockLabel(const MachineBasicBlock *MBB) const; + virtual void printBasicBlockLabel(const MachineBasicBlock *MBB, + bool printColon = false, + bool printComment = true) const; }; } // end namespace llvm Index: llvm/lib/Target/X86/X86IntelAsmPrinter.cpp diff -u llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.35 llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.36 --- llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.35 Mon May 1 22:58:45 2006 +++ llvm/lib/Target/X86/X86IntelAsmPrinter.cpp Tue May 2 00:37:32 2006 @@ -72,10 +72,10 @@ for (MachineFunction::const_iterator I = MF.begin(), E = MF.end(); I != E; ++I) { // Print a label for the basic block if there are any predecessors. - if (I->pred_begin() != I->pred_end()) - O << PrivateGlobalPrefix << "BB" << CurrentFnName << "_" << I->getNumber() - << ":\t" - << CommentString << " " << I->getBasicBlock()->getName() << "\n"; + if (I->pred_begin() != I->pred_end()) { + printBasicBlockLabel(I, true); + O << '\n'; + } for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end(); II != E; ++II) { // Print the assembly for the instruction. From natebegeman at mac.com Tue May 2 00:37:49 2006 From: natebegeman at mac.com (Nate Begeman) Date: Tue, 2 May 2006 00:37:49 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/AsmPrinter.cpp Message-ID: <200605020537.AAA22422@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: AsmPrinter.cpp updated: 1.63 -> 1.64 --- Log message: Extend printBasicBlockLabel a bit so that it can be used to print all basic block labels, consolidating the code to do so in one place for each target. --- Diffs of the changes: (+8 -3) AsmPrinter.cpp | 11 ++++++++--- 1 files changed, 8 insertions(+), 3 deletions(-) Index: llvm/lib/CodeGen/AsmPrinter.cpp diff -u llvm/lib/CodeGen/AsmPrinter.cpp:1.63 llvm/lib/CodeGen/AsmPrinter.cpp:1.64 --- llvm/lib/CodeGen/AsmPrinter.cpp:1.63 Mon May 1 22:58:45 2006 +++ llvm/lib/CodeGen/AsmPrinter.cpp Tue May 2 00:37:32 2006 @@ -728,9 +728,14 @@ /// printBasicBlockLabel - This method prints the label for the specified /// MachineBasicBlock -void AsmPrinter::printBasicBlockLabel(const MachineBasicBlock *MBB) const { +void AsmPrinter::printBasicBlockLabel(const MachineBasicBlock *MBB, + bool printColon, + bool printComment) const { O << PrivateGlobalPrefix << "LBB" << Mang->getValueName(MBB->getParent()->getFunction()) - << "_" << MBB->getNumber() << '\t' << CommentString - << MBB->getBasicBlock()->getName(); + << "_" << MBB->getNumber(); + if (printColon) + O << ':'; + if (printComment) + O << '\t' << CommentString << MBB->getBasicBlock()->getName(); } From natebegeman at mac.com Tue May 2 00:37:49 2006 From: natebegeman at mac.com (Nate Begeman) Date: Tue, 2 May 2006 00:37:49 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcAsmPrinter.cpp Message-ID: <200605020537.AAA22446@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Sparc: SparcAsmPrinter.cpp updated: 1.58 -> 1.59 --- Log message: Extend printBasicBlockLabel a bit so that it can be used to print all basic block labels, consolidating the code to do so in one place for each target. --- Diffs of the changes: (+4 -4) SparcAsmPrinter.cpp | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) Index: llvm/lib/Target/Sparc/SparcAsmPrinter.cpp diff -u llvm/lib/Target/Sparc/SparcAsmPrinter.cpp:1.58 llvm/lib/Target/Sparc/SparcAsmPrinter.cpp:1.59 --- llvm/lib/Target/Sparc/SparcAsmPrinter.cpp:1.58 Sat Apr 22 13:53:45 2006 +++ llvm/lib/Target/Sparc/SparcAsmPrinter.cpp Tue May 2 00:37:32 2006 @@ -116,10 +116,10 @@ for (MachineFunction::const_iterator I = MF.begin(), E = MF.end(); I != E; ++I) { // Print a label for the basic block. - if (I != MF.begin()) - O << ".LBB" << Mang->getValueName(MF.getFunction ()) - << "_" << I->getNumber () << ":\t! " - << I->getBasicBlock ()->getName () << "\n"; + if (I != MF.begin()) { + printBasicBlockLabel(I, true); + O << '\n'; + } for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end(); II != E; ++II) { // Print the assembly for the instruction. From lattner at cs.uiuc.edu Tue May 2 11:59:43 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 2 May 2006 11:59:43 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/MachineCodeEmitter.cpp Message-ID: <200605021659.LAA10623@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: MachineCodeEmitter.cpp updated: 1.26 -> 1.27 --- Log message: Remove the debug machine code emitter. The "FilePrinterEmitter" is more useful for debugging. --- Diffs of the changes: (+0 -52) MachineCodeEmitter.cpp | 52 ------------------------------------------------- 1 files changed, 52 deletions(-) Index: llvm/lib/CodeGen/MachineCodeEmitter.cpp diff -u llvm/lib/CodeGen/MachineCodeEmitter.cpp:1.26 llvm/lib/CodeGen/MachineCodeEmitter.cpp:1.27 --- llvm/lib/CodeGen/MachineCodeEmitter.cpp:1.26 Sat Apr 22 13:53:45 2006 +++ llvm/lib/CodeGen/MachineCodeEmitter.cpp Tue May 2 11:59:24 2006 @@ -12,55 +12,12 @@ //===----------------------------------------------------------------------===// #include "llvm/CodeGen/MachineCodeEmitter.h" -#include "llvm/CodeGen/MachineFunction.h" -#include "llvm/Function.h" #include #include -#include using namespace llvm; namespace { - struct DebugMachineCodeEmitter : public MachineCodeEmitter { - void startFunction(MachineFunction &F) { - std::cout << "\n**** Writing machine code for function: " - << F.getFunction()->getName() << "\n"; - } - void finishFunction(MachineFunction &F) { - std::cout << "\n"; - } - void startFunctionStub(unsigned StubSize) { - std::cout << "\n--- Function stub:\n"; - } - void *finishFunctionStub(const Function *F) { - std::cout << "\n--- End of stub for Function\n"; - return 0; - } - - void emitByte(unsigned char B) { - std::cout << "0x" << std::hex << (unsigned int)B << std::dec << " "; - } - void emitWord(unsigned W) { - std::cout << "0x" << std::hex << W << std::dec << " "; - } - void emitWordAt(unsigned W, unsigned *Ptr) { - std::cout << "0x" << std::hex << W << std::dec << " (at " - << (void*) Ptr << ") "; - } - - void addRelocation(const MachineRelocation &MR) { - std::cout << " "; - } - - virtual unsigned char* allocateGlobal(unsigned size, unsigned alignment) - { return 0; } - - uint64_t getConstantPoolEntryAddress(unsigned Num) { return 0; } - uint64_t getJumpTableEntryAddress(unsigned Num) { return 0; } - uint64_t getCurrentPCValue() { return 0; } - uint64_t getCurrentPCOffset() { return 0; } - }; - class FilePrinterEmitter : public MachineCodeEmitter { std::ofstream actual; std::ostream &o; @@ -172,15 +129,6 @@ }; } -/// createDebugMachineCodeEmitter - Return a dynamically allocated machine -/// code emitter, which just prints the opcodes and fields out the cout. This -/// can be used for debugging users of the MachineCodeEmitter interface. -/// -MachineCodeEmitter * -MachineCodeEmitter::createDebugEmitter() { - return new DebugMachineCodeEmitter(); -} - MachineCodeEmitter * MachineCodeEmitter::createFilePrinterEmitter(MachineCodeEmitter &MCE) { return new FilePrinterEmitter(MCE, std::cerr); From lattner at cs.uiuc.edu Tue May 2 12:00:01 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 2 May 2006 12:00:01 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineCodeEmitter.h Message-ID: <200605021700.MAA10703@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineCodeEmitter.h updated: 1.30 -> 1.31 --- Log message: Remove the debug machine code emitter. The "FilePrinterEmitter" is moreuseful for debugging. --- Diffs of the changes: (+0 -6) MachineCodeEmitter.h | 6 ------ 1 files changed, 6 deletions(-) Index: llvm/include/llvm/CodeGen/MachineCodeEmitter.h diff -u llvm/include/llvm/CodeGen/MachineCodeEmitter.h:1.30 llvm/include/llvm/CodeGen/MachineCodeEmitter.h:1.31 --- llvm/include/llvm/CodeGen/MachineCodeEmitter.h:1.30 Sat Apr 22 18:52:35 2006 +++ llvm/include/llvm/CodeGen/MachineCodeEmitter.h Tue May 2 11:59:49 2006 @@ -115,12 +115,6 @@ // allocateGlobal - Allocate some space for a global variable. virtual unsigned char* allocateGlobal(unsigned size, unsigned alignment) = 0; - /// createDebugEmitter - Return a dynamically allocated machine - /// code emitter, which just prints the opcodes and fields out the cout. This - /// can be used for debugging users of the MachineCodeEmitter interface. - /// - static MachineCodeEmitter *createDebugEmitter(); - /// createFilePrinterEmitter - Return a dynamically allocated /// machine code emitter, which prints binary code to a file. This /// can be used for debugging users of the MachineCodeEmitter interface. From lattner at cs.uiuc.edu Tue May 2 12:16:32 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 2 May 2006 12:16:32 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86CodeEmitter.cpp Message-ID: <200605021716.MAA10901@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86CodeEmitter.cpp updated: 1.94 -> 1.95 --- Log message: There is no reason to use a virtual method to store this word. --- Diffs of the changes: (+2 -2) X86CodeEmitter.cpp | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/Target/X86/X86CodeEmitter.cpp diff -u llvm/lib/Target/X86/X86CodeEmitter.cpp:1.94 llvm/lib/Target/X86/X86CodeEmitter.cpp:1.95 --- llvm/lib/Target/X86/X86CodeEmitter.cpp:1.94 Sat Apr 22 13:53:45 2006 +++ llvm/lib/Target/X86/X86CodeEmitter.cpp Tue May 2 12:16:20 2006 @@ -89,11 +89,11 @@ MCE.emitJumpTableInfo(MF.getJumpTableInfo(), BasicBlockAddrs); MCE.finishFunction(MF); - // Resolve all forward branches now... + // Resolve all forward branches now. for (unsigned i = 0, e = BBRefs.size(); i != e; ++i) { unsigned Location = BasicBlockAddrs[BBRefs[i].first]; unsigned Ref = BBRefs[i].second; - MCE.emitWordAt(Location-Ref-4, (unsigned*)(intptr_t)Ref); + *((unsigned*)(intptr_t)Ref) = Location-Ref-4; } BBRefs.clear(); BasicBlockAddrs.clear(); From lattner at cs.uiuc.edu Tue May 2 12:17:25 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 2 May 2006 12:17:25 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineCodeEmitter.h Message-ID: <200605021717.MAA10974@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineCodeEmitter.h updated: 1.31 -> 1.32 --- Log message: Remove a now-dead method --- Diffs of the changes: (+0 -6) MachineCodeEmitter.h | 6 ------ 1 files changed, 6 deletions(-) Index: llvm/include/llvm/CodeGen/MachineCodeEmitter.h diff -u llvm/include/llvm/CodeGen/MachineCodeEmitter.h:1.31 llvm/include/llvm/CodeGen/MachineCodeEmitter.h:1.32 --- llvm/include/llvm/CodeGen/MachineCodeEmitter.h:1.31 Tue May 2 11:59:49 2006 +++ llvm/include/llvm/CodeGen/MachineCodeEmitter.h Tue May 2 12:17:13 2006 @@ -77,12 +77,6 @@ /// virtual void emitByte(unsigned char B) {} - /// emitWordAt - This callback is invoked when a word needs to be written to - /// the output stream at a different position than the current PC (for - /// instance, when performing relocations). - /// - virtual void emitWordAt(unsigned W, unsigned *Ptr) {} - /// emitWord - This callback is invoked when a word needs to be written to the /// output stream. /// From lattner at cs.uiuc.edu Tue May 2 12:17:59 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 2 May 2006 12:17:59 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/ELFWriter.cpp MachineCodeEmitter.cpp Message-ID: <200605021717.MAA11047@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: ELFWriter.cpp updated: 1.18 -> 1.19 MachineCodeEmitter.cpp updated: 1.27 -> 1.28 --- Log message: Remove dead method --- Diffs of the changes: (+0 -7) ELFWriter.cpp | 3 --- MachineCodeEmitter.cpp | 4 ---- 2 files changed, 7 deletions(-) Index: llvm/lib/CodeGen/ELFWriter.cpp diff -u llvm/lib/CodeGen/ELFWriter.cpp:1.18 llvm/lib/CodeGen/ELFWriter.cpp:1.19 --- llvm/lib/CodeGen/ELFWriter.cpp:1.18 Sat Apr 22 13:53:45 2006 +++ llvm/lib/CodeGen/ELFWriter.cpp Tue May 2 12:17:47 2006 @@ -65,9 +65,6 @@ virtual void emitByte(unsigned char B) { OutBuffer->push_back(B); } - virtual void emitWordAt(unsigned W, unsigned *Ptr) { - assert(0 && "ni"); - } virtual void emitWord(unsigned W) { assert(0 && "ni"); } Index: llvm/lib/CodeGen/MachineCodeEmitter.cpp diff -u llvm/lib/CodeGen/MachineCodeEmitter.cpp:1.27 llvm/lib/CodeGen/MachineCodeEmitter.cpp:1.28 --- llvm/lib/CodeGen/MachineCodeEmitter.cpp:1.27 Tue May 2 11:59:24 2006 +++ llvm/lib/CodeGen/MachineCodeEmitter.cpp Tue May 2 12:17:47 2006 @@ -14,7 +14,6 @@ #include "llvm/CodeGen/MachineCodeEmitter.h" #include #include - using namespace llvm; namespace { @@ -105,9 +104,6 @@ void emitWord(unsigned W) { MCE.emitWord(W); } - void emitWordAt(unsigned W, unsigned *Ptr) { - MCE.emitWordAt(W, Ptr); - } uint64_t getConstantPoolEntryAddress(unsigned Num) { return MCE.getConstantPoolEntryAddress(Num); } From lattner at cs.uiuc.edu Tue May 2 12:20:40 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 2 May 2006 12:20:40 -0500 Subject: [llvm-commits] CVS: llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp Message-ID: <200605021720.MAA11201@zion.cs.uiuc.edu> Changes in directory llvm/lib/ExecutionEngine/JIT: JITEmitter.cpp updated: 1.84 -> 1.85 --- Log message: Remove dead method --- Diffs of the changes: (+0 -5) JITEmitter.cpp | 5 ----- 1 files changed, 5 deletions(-) Index: llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp diff -u llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.84 llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.85 --- llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.84 Tue Apr 25 12:46:32 2006 +++ llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp Tue May 2 12:20:28 2006 @@ -458,7 +458,6 @@ virtual void* finishFunctionStub(const Function *F); virtual void emitByte(unsigned char B); virtual void emitWord(unsigned W); - virtual void emitWordAt(unsigned W, unsigned *Ptr); virtual void addRelocation(const MachineRelocation &MR) { Relocations.push_back(MR); @@ -671,10 +670,6 @@ CurByte += sizeof(unsigned); } -void JITEmitter::emitWordAt(unsigned W, unsigned *Ptr) { - *Ptr = W; -} - // getConstantPoolEntryAddress - Return the address of the 'ConstantNum' entry // in the constant pool that was last emitted with the 'emitConstantPool' // method. From natebegeman at mac.com Tue May 2 12:35:03 2006 From: natebegeman at mac.com (Nate Begeman) Date: Tue, 2 May 2006 12:35:03 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86AsmPrinter.cpp X86AsmPrinter.h Message-ID: <200605021735.MAA11664@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86AsmPrinter.cpp updated: 1.174 -> 1.175 X86AsmPrinter.h updated: 1.16 -> 1.17 --- Log message: Hooray, everyone now uses the same printBasicBlockLabel implementation --- Diffs of the changes: (+0 -16) X86AsmPrinter.cpp | 12 ------------ X86AsmPrinter.h | 4 ---- 2 files changed, 16 deletions(-) Index: llvm/lib/Target/X86/X86AsmPrinter.cpp diff -u llvm/lib/Target/X86/X86AsmPrinter.cpp:1.174 llvm/lib/Target/X86/X86AsmPrinter.cpp:1.175 --- llvm/lib/Target/X86/X86AsmPrinter.cpp:1.174 Tue May 2 00:37:32 2006 +++ llvm/lib/Target/X86/X86AsmPrinter.cpp Tue May 2 12:34:51 2006 @@ -206,18 +206,6 @@ return false; // success } -void X86SharedAsmPrinter::printBasicBlockLabel(const MachineBasicBlock *MBB, - bool printColon, - bool printComment) const { - O << PrivateGlobalPrefix << "BB" - << Mang->getValueName(MBB->getParent()->getFunction()) << "_" - << MBB->getNumber(); - if (printColon) - O << ':'; - if (printComment) - O << '\t' << CommentString << MBB->getBasicBlock()->getName(); -} - /// createX86CodePrinterPass - Returns a pass that prints the X86 assembly code /// for a MachineFunction to the given output stream, using the given target /// machine description. Index: llvm/lib/Target/X86/X86AsmPrinter.h diff -u llvm/lib/Target/X86/X86AsmPrinter.h:1.16 llvm/lib/Target/X86/X86AsmPrinter.h:1.17 --- llvm/lib/Target/X86/X86AsmPrinter.h:1.16 Tue May 2 00:37:32 2006 +++ llvm/lib/Target/X86/X86AsmPrinter.h Tue May 2 12:34:51 2006 @@ -88,10 +88,6 @@ MI->getOperand(Op+3).isGlobalAddress() || MI->getOperand(Op+3).isConstantPoolIndex()); } - - virtual void printBasicBlockLabel(const MachineBasicBlock *MBB, - bool printColon = false, - bool printComment = true) const; }; } // end namespace llvm From natebegeman at mac.com Tue May 2 12:35:04 2006 From: natebegeman at mac.com (Nate Begeman) Date: Tue, 2 May 2006 12:35:04 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp Message-ID: <200605021735.MAA11668@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCAsmPrinter.cpp updated: 1.165 -> 1.166 --- Log message: Hooray, everyone now uses the same printBasicBlockLabel implementation --- Diffs of the changes: (+3 -20) PPCAsmPrinter.cpp | 23 +++-------------------- 1 files changed, 3 insertions(+), 20 deletions(-) Index: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp diff -u llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.165 llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.166 --- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.165 Tue May 2 00:37:32 2006 +++ llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp Tue May 2 12:34:51 2006 @@ -233,10 +233,6 @@ printOperand(MI, OpNo+1); } - virtual void printBasicBlockLabel(const MachineBasicBlock *MBB, - bool printColon = false, - bool printComment = true) const; - virtual bool runOnMachineFunction(MachineFunction &F) = 0; virtual bool doFinalization(Module &M) = 0; @@ -507,17 +503,6 @@ return; } -void PPCAsmPrinter::printBasicBlockLabel(const MachineBasicBlock *MBB, - bool printColon, - bool printComment) const { - O << PrivateGlobalPrefix << "BB" << getFunctionNumber() << "_" - << MBB->getNumber(); - if (printColon) - O << ':'; - if (printComment) - O << '\t' << CommentString << MBB->getBasicBlock()->getName(); -} - /// runOnMachineFunction - This uses the printMachineInstruction() /// method to print assembly for each instruction. /// @@ -729,7 +714,7 @@ return false; // success } -/// runOnMachineFunction - This uses the e() +/// runOnMachineFunction - This uses the printMachineInstruction() /// method to print assembly for each instruction. /// bool AIXAsmPrinter::runOnMachineFunction(MachineFunction &MF) { @@ -752,10 +737,8 @@ // Print out code for the function. for (MachineFunction::const_iterator I = MF.begin(), E = MF.end(); I != E; ++I) { - // Print a label for the basic block. - O << PrivateGlobalPrefix << "BB" << getFunctionNumber() << '_' - << I->getNumber() - << ":\t" << CommentString << I->getBasicBlock()->getName() << '\n'; + printBasicBlockLabel(I); + O << '\n'; for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end(); II != E; ++II) { // Print the assembly for the instruction. From natebegeman at mac.com Tue May 2 12:36:58 2006 From: natebegeman at mac.com (Nate Begeman) Date: Tue, 2 May 2006 12:36:58 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/AsmPrinter.cpp Message-ID: <200605021736.MAA11690@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: AsmPrinter.cpp updated: 1.64 -> 1.65 --- Log message: Print function number instead of name --- Diffs of the changes: (+2 -3) AsmPrinter.cpp | 5 ++--- 1 files changed, 2 insertions(+), 3 deletions(-) Index: llvm/lib/CodeGen/AsmPrinter.cpp diff -u llvm/lib/CodeGen/AsmPrinter.cpp:1.64 llvm/lib/CodeGen/AsmPrinter.cpp:1.65 --- llvm/lib/CodeGen/AsmPrinter.cpp:1.64 Tue May 2 00:37:32 2006 +++ llvm/lib/CodeGen/AsmPrinter.cpp Tue May 2 12:36:46 2006 @@ -731,9 +731,8 @@ void AsmPrinter::printBasicBlockLabel(const MachineBasicBlock *MBB, bool printColon, bool printComment) const { - O << PrivateGlobalPrefix << "LBB" - << Mang->getValueName(MBB->getParent()->getFunction()) - << "_" << MBB->getNumber(); + O << PrivateGlobalPrefix << "BB" << FunctionNumber << "_" + << MBB->getNumber(); if (printColon) O << ':'; if (printComment) From natebegeman at mac.com Tue May 2 12:37:43 2006 From: natebegeman at mac.com (Nate Begeman) Date: Tue, 2 May 2006 12:37:43 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp PPCRegisterInfo.td Message-ID: <200605021737.MAA11705@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCRegisterInfo.cpp updated: 1.61 -> 1.62 PPCRegisterInfo.td updated: 1.34 -> 1.35 --- Log message: Since we don't handle callee-save CRs right yet, don't allocate them. Also don't step on R11 in the middle of a function when saving and restoring CRs --- Diffs of the changes: (+26 -9) PPCRegisterInfo.cpp | 14 ++++++++------ PPCRegisterInfo.td | 21 ++++++++++++++++++--- 2 files changed, 26 insertions(+), 9 deletions(-) Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.61 llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.62 --- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.61 Mon Apr 17 16:48:13 2006 +++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Tue May 2 12:37:31 2006 @@ -102,8 +102,9 @@ BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11); addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx); } else if (RC == PPC::CRRCRegisterClass) { - BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R11); - addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx); + // FIXME: We use R0 here, because it isn't available for RA. + BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R0); + addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R0), FrameIdx); } else if (RC == PPC::GPRCRegisterClass) { addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(SrcReg),FrameIdx); } else if (RC == PPC::G8RCRegisterClass) { @@ -118,7 +119,7 @@ // Dest = LVX R0, R11 // // FIXME: We use R0 here, because it isn't available for RA. - addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0); + addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 2, PPC::R0), FrameIdx, 0, 0); BuildMI(MBB, MI, PPC::STVX, 3) .addReg(SrcReg).addReg(PPC::R0).addReg(PPC::R0); } else { @@ -136,8 +137,9 @@ addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx); BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11); } else if (RC == PPC::CRRCRegisterClass) { - addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx); - BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R11); + // FIXME: We use R0 here, because it isn't available for RA. + addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R0), FrameIdx); + BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R0); } else if (RC == PPC::GPRCRegisterClass) { addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, DestReg), FrameIdx); } else if (RC == PPC::G8RCRegisterClass) { @@ -152,7 +154,7 @@ // Dest = LVX R0, R11 // // FIXME: We use R0 here, because it isn't available for RA. - addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0); + addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 2, PPC::R0), FrameIdx, 0, 0); BuildMI(MBB, MI, PPC::LVX, 2, DestReg).addReg(PPC::R0).addReg(PPC::R0); } else { assert(0 && "Unknown regclass!"); Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.td diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.td:1.34 llvm/lib/Target/PowerPC/PPCRegisterInfo.td:1.35 --- llvm/lib/Target/PowerPC/PPCRegisterInfo.td:1.34 Mon Apr 17 16:19:12 2006 +++ llvm/lib/Target/PowerPC/PPCRegisterInfo.td Tue May 2 12:37:31 2006 @@ -264,6 +264,21 @@ V6, V7, V8, V9, V10, V11, V12, V13, V14, V15, V16, V17, V18, V19, V20, V21, V22, V23, V24, V25, V26, V27, V28, V29, V30, V31]>; -def CRRC : RegisterClass<"PPC", [i32], 32, [CR0, CR1, CR5, CR6, CR7, CR2, - CR3, CR4]>; - +def CRRC : RegisterClass<"PPC", [i32], 32, [CR0, CR1, CR5, CR6, CR7, CR2, CR3, CR4]> +{ + let MethodProtos = [{ + iterator allocation_order_begin(MachineFunction &MF) const; + iterator allocation_order_end(MachineFunction &MF) const; + }]; + let MethodBodies = [{ + CRRCClass::iterator + CRRCClass::allocation_order_begin(MachineFunction &MF) const { + return begin(); + } + CRRCClass::iterator + CRRCClass::allocation_order_end(MachineFunction &MF) const { + return end()-3; + } + }]; +} + From lattner at cs.uiuc.edu Tue May 2 13:27:41 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 2 May 2006 13:27:41 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp Message-ID: <200605021827.NAA12175@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Alpha: AlphaCodeEmitter.cpp updated: 1.9 -> 1.10 --- Log message: Refactor the machine code emitter interface to pull the pointers for the current code emission location into the base class, instead of being in the derived classes. This change means that low-level methods like emitByte/emitWord now are no longer virtual (yaay for speed), and we now have a framework to support growable code segments. This implements feature request #1 of PR469: http://llvm.cs.uiuc.edu/PR469 . --- Diffs of the changes: (+9 -5) AlphaCodeEmitter.cpp | 14 +++++++++----- 1 files changed, 9 insertions(+), 5 deletions(-) Index: llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp diff -u llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp:1.9 llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp:1.10 --- llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp:1.9 Sun Jan 22 17:37:17 2006 +++ llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp Tue May 2 13:27:26 2006 @@ -80,11 +80,15 @@ bool AlphaCodeEmitter::runOnMachineFunction(MachineFunction &MF) { II = ((AlphaTargetMachine&)MF.getTarget()).getInstrInfo(); - MCE.startFunction(MF); - MCE.emitConstantPool(MF.getConstantPool()); - for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) - emitBasicBlock(*I); - MCE.finishFunction(MF); + do { + BBRefs.clear(); + BasicBlockAddrs.clear(); + + MCE.startFunction(MF); + MCE.emitConstantPool(MF.getConstantPool()); + for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) + emitBasicBlock(*I); + } while (MCE.finishFunction(MF)); // Resolve all forward branches now... for (unsigned i = 0, e = BBRefs.size(); i != e; ++i) { From lattner at cs.uiuc.edu Tue May 2 13:27:42 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 2 May 2006 13:27:42 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86CodeEmitter.cpp Message-ID: <200605021827.NAA12189@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86CodeEmitter.cpp updated: 1.95 -> 1.96 --- Log message: Refactor the machine code emitter interface to pull the pointers for the current code emission location into the base class, instead of being in the derived classes. This change means that low-level methods like emitByte/emitWord now are no longer virtual (yaay for speed), and we now have a framework to support growable code segments. This implements feature request #1 of PR469: http://llvm.cs.uiuc.edu/PR469 . --- Diffs of the changes: (+11 -7) X86CodeEmitter.cpp | 18 +++++++++++------- 1 files changed, 11 insertions(+), 7 deletions(-) Index: llvm/lib/Target/X86/X86CodeEmitter.cpp diff -u llvm/lib/Target/X86/X86CodeEmitter.cpp:1.95 llvm/lib/Target/X86/X86CodeEmitter.cpp:1.96 --- llvm/lib/Target/X86/X86CodeEmitter.cpp:1.95 Tue May 2 12:16:20 2006 +++ llvm/lib/Target/X86/X86CodeEmitter.cpp Tue May 2 13:27:26 2006 @@ -81,13 +81,17 @@ "JIT relocation model must be set to static or default!"); II = ((X86TargetMachine&)MF.getTarget()).getInstrInfo(); - MCE.startFunction(MF); - MCE.emitConstantPool(MF.getConstantPool()); - MCE.initJumpTableInfo(MF.getJumpTableInfo()); - for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) - emitBasicBlock(*I); - MCE.emitJumpTableInfo(MF.getJumpTableInfo(), BasicBlockAddrs); - MCE.finishFunction(MF); + do { + BBRefs.clear(); + BasicBlockAddrs.clear(); + + MCE.startFunction(MF); + MCE.emitConstantPool(MF.getConstantPool()); + MCE.initJumpTableInfo(MF.getJumpTableInfo()); + for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) + emitBasicBlock(*I); + MCE.emitJumpTableInfo(MF.getJumpTableInfo(), BasicBlockAddrs); + } while (MCE.finishFunction(MF)); // Resolve all forward branches now. for (unsigned i = 0, e = BBRefs.size(); i != e; ++i) { From lattner at cs.uiuc.edu Tue May 2 13:27:42 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 2 May 2006 13:27:42 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/ELFWriter.cpp MachineCodeEmitter.cpp Message-ID: <200605021827.NAA12187@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: ELFWriter.cpp updated: 1.19 -> 1.20 MachineCodeEmitter.cpp (r1.28) removed --- Log message: Refactor the machine code emitter interface to pull the pointers for the current code emission location into the base class, instead of being in the derived classes. This change means that low-level methods like emitByte/emitWord now are no longer virtual (yaay for speed), and we now have a framework to support growable code segments. This implements feature request #1 of PR469: http://llvm.cs.uiuc.edu/PR469 . --- Diffs of the changes: (+7 -14) ELFWriter.cpp | 21 +++++++-------------- 1 files changed, 7 insertions(+), 14 deletions(-) Index: llvm/lib/CodeGen/ELFWriter.cpp diff -u llvm/lib/CodeGen/ELFWriter.cpp:1.19 llvm/lib/CodeGen/ELFWriter.cpp:1.20 --- llvm/lib/CodeGen/ELFWriter.cpp:1.19 Tue May 2 12:17:47 2006 +++ llvm/lib/CodeGen/ELFWriter.cpp Tue May 2 13:27:26 2006 @@ -56,24 +56,12 @@ ELFCodeEmitter(ELFWriter &ew) : EW(ew), OutBuffer(0) {} void startFunction(MachineFunction &F); - void finishFunction(MachineFunction &F); + bool finishFunction(MachineFunction &F); void emitConstantPool(MachineConstantPool *MCP) { if (MCP->isEmpty()) return; assert(0 && "unimp"); } - virtual void emitByte(unsigned char B) { - OutBuffer->push_back(B); - } - virtual void emitWord(unsigned W) { - assert(0 && "ni"); - } - virtual uint64_t getCurrentPCValue() { - return OutBuffer->size(); - } - virtual uint64_t getCurrentPCOffset() { - return OutBuffer->size()-FnStart; - } void addRelocation(const MachineRelocation &MR) { assert(0 && "relo not handled yet!"); } @@ -113,6 +101,10 @@ ELFWriter::ELFSection::SHF_EXECINSTR | ELFWriter::ELFSection::SHF_ALLOC); OutBuffer = &ES->SectionData; + std::cerr << "FIXME: This code needs to be updated for changes in the" + << " CodeEmitter interfaces. In particular, this should set " + << "BufferBegin/BufferEnd/CurBufferPtr, not deal with OutBuffer!"; + abort(); // Upgrade the section alignment if required. if (ES->Align < Align) ES->Align = Align; @@ -127,7 +119,7 @@ /// finishFunction - This callback is invoked after the function is completely /// finished. -void ELFCodeEmitter::finishFunction(MachineFunction &F) { +bool ELFCodeEmitter::finishFunction(MachineFunction &F) { // We now know the size of the function, add a symbol to represent it. ELFWriter::ELFSym FnSym(F.getFunction()); @@ -157,6 +149,7 @@ // Finally, add it to the symtab. EW.SymbolTable.push_back(FnSym); + return false; } //===----------------------------------------------------------------------===// From lattner at cs.uiuc.edu Tue May 2 13:27:41 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 2 May 2006 13:27:41 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineCodeEmitter.h Message-ID: <200605021827.NAA12179@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineCodeEmitter.h updated: 1.32 -> 1.33 --- Log message: Refactor the machine code emitter interface to pull the pointers for the current code emission location into the base class, instead of being in the derived classes. This change means that low-level methods like emitByte/emitWord now are no longer virtual (yaay for speed), and we now have a framework to support growable code segments. This implements feature request #1 of PR469: http://llvm.cs.uiuc.edu/PR469 . --- Diffs of the changes: (+56 -16) MachineCodeEmitter.h | 72 +++++++++++++++++++++++++++++++++++++++------------ 1 files changed, 56 insertions(+), 16 deletions(-) Index: llvm/include/llvm/CodeGen/MachineCodeEmitter.h diff -u llvm/include/llvm/CodeGen/MachineCodeEmitter.h:1.32 llvm/include/llvm/CodeGen/MachineCodeEmitter.h:1.33 --- llvm/include/llvm/CodeGen/MachineCodeEmitter.h:1.32 Tue May 2 12:17:13 2006 +++ llvm/include/llvm/CodeGen/MachineCodeEmitter.h Tue May 2 13:27:26 2006 @@ -31,19 +31,50 @@ class GlobalValue; class Function; +/// MachineCodeEmitter - This class defines two sorts of methods: those for +/// emitting the actual bytes of machine code, and those for emitting auxillary +/// structures, such as jump tables, relocations, etc. +/// +/// Emission of machine code is complicated by the fact that we don't (in +/// general) know the size of the machine code that we're about to emit before +/// we emit it. As such, we preallocate a certain amount of memory, and set the +/// BufferBegin/BufferEnd pointers to the start and end of the buffer. As we +/// emit machine instructions, we advance the CurBufferPtr to indicate the +/// location of the next byte to emit. In the case of a buffer overflow (we +/// need to emit more machine code than we have allocated space for), the +/// CurBufferPtr will saturate to BufferEnd and ignore stores. Once the entire +/// function has been emitted, the overflow condition is checked, and if it has +/// occurred, more memory is allocated, and we reemit the code into it. +/// class MachineCodeEmitter { +protected: + /// BufferBegin/BufferEnd - Pointers to the start and end of the memory + /// allocated for this code buffer. + unsigned char *BufferBegin, *BufferEnd; + + /// CurBufferPtr - Pointer to the next byte of memory to fill when emitting + /// code. This is guranteed to be in the range [BufferBegin,BufferEnd]. If + /// this pointer is at BufferEnd, it will never move due to code emission, and + /// all code emission requests will be ignored (this is the buffer overflow + /// condition). + unsigned char *CurBufferPtr; public: virtual ~MachineCodeEmitter() {} /// startFunction - This callback is invoked when the specified function is - /// about to be code generated. + /// about to be code generated. This initializes the BufferBegin/End/Ptr + /// fields. /// virtual void startFunction(MachineFunction &F) {} /// finishFunction - This callback is invoked when the specified function has - /// finished code generation. - /// - virtual void finishFunction(MachineFunction &F) {} + /// finished code generation. If a buffer overflow has occurred, this method + /// returns true (the callee is required to try again), otherwise it returns + /// false. + /// + virtual bool finishFunction(MachineFunction &F) { + return CurBufferPtr == BufferEnd; + } /// emitConstantPool - This callback is invoked to output the constant pool /// for the function. @@ -63,7 +94,8 @@ /// startFunctionStub - This callback is invoked when the JIT needs the /// address of a function that has not been code generated yet. The StubSize /// specifies the total size required by the stub. Stubs are not allowed to - /// have constant pools, the can only use the other emit* methods. + /// have constant pools, the can only use the other emitByte*/emitWord* + /// methods. /// virtual void startFunctionStub(unsigned StubSize) {} @@ -75,22 +107,36 @@ /// emitByte - This callback is invoked when a byte needs to be written to the /// output stream. /// - virtual void emitByte(unsigned char B) {} + void emitByte(unsigned char B) { + if (CurBufferPtr != BufferEnd) + *CurBufferPtr++ = B; + } /// emitWord - This callback is invoked when a word needs to be written to the /// output stream. /// - virtual void emitWord(unsigned W) = 0; + void emitWord(unsigned W) { + // FIXME: handle endian mismatches for .o file emission. + if (CurBufferPtr+4 <= BufferEnd) { + *(unsigned*)CurBufferPtr = W; + CurBufferPtr += 4; + } else { + CurBufferPtr = BufferEnd; + } + } /// getCurrentPCValue - This returns the address that the next emitted byte /// will be output to. /// - virtual uint64_t getCurrentPCValue() = 0; - + virtual intptr_t getCurrentPCValue() const { + return (intptr_t)CurBufferPtr; + } /// getCurrentPCOffset - Return the offset from the start of the emitted /// buffer that we are currently writing to. - virtual uint64_t getCurrentPCOffset() = 0; + intptr_t getCurrentPCOffset() const { + return CurBufferPtr-BufferBegin; + } /// addRelocation - Whenever a relocatable address is needed, it should be /// noted with this interface. @@ -108,12 +154,6 @@ // allocateGlobal - Allocate some space for a global variable. virtual unsigned char* allocateGlobal(unsigned size, unsigned alignment) = 0; - - /// createFilePrinterEmitter - Return a dynamically allocated - /// machine code emitter, which prints binary code to a file. This - /// can be used for debugging users of the MachineCodeEmitter interface. - /// - static MachineCodeEmitter *createFilePrinterEmitter(MachineCodeEmitter&); }; } // End llvm namespace From lattner at cs.uiuc.edu Tue May 2 13:27:42 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 2 May 2006 13:27:42 -0500 Subject: [llvm-commits] CVS: llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp Message-ID: <200605021827.NAA12183@zion.cs.uiuc.edu> Changes in directory llvm/lib/ExecutionEngine/JIT: JITEmitter.cpp updated: 1.85 -> 1.86 --- Log message: Refactor the machine code emitter interface to pull the pointers for the current code emission location into the base class, instead of being in the derived classes. This change means that low-level methods like emitByte/emitWord now are no longer virtual (yaay for speed), and we now have a framework to support growable code segments. This implements feature request #1 of PR469: http://llvm.cs.uiuc.edu/PR469 . --- Diffs of the changes: (+31 -52) JITEmitter.cpp | 83 +++++++++++++++++++++------------------------------------ 1 files changed, 31 insertions(+), 52 deletions(-) Index: llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp diff -u llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.85 llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.86 --- llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.85 Tue May 2 12:20:28 2006 +++ llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp Tue May 2 13:27:26 2006 @@ -413,13 +413,9 @@ class JITEmitter : public MachineCodeEmitter { JITMemoryManager MemMgr; - // CurBlock - The start of the current block of memory. CurByte - The - // current byte being emitted to. - unsigned char *CurBlock, *CurByte; - // When outputting a function stub in the context of some other function, we - // save CurBlock and CurByte here. - unsigned char *SavedCurBlock, *SavedCurByte; + // save BufferBegin/BufferEnd/CurBufferPtr here. + unsigned char *SavedBufferBegin, *SavedBufferEnd, *SavedCurBufferPtr; /// Relocations - These are the relocations that the function needs, as /// emitted. @@ -449,22 +445,18 @@ } virtual void startFunction(MachineFunction &F); - virtual void finishFunction(MachineFunction &F); + virtual bool finishFunction(MachineFunction &F); virtual void emitConstantPool(MachineConstantPool *MCP); virtual void initJumpTableInfo(MachineJumpTableInfo *MJTI); virtual void emitJumpTableInfo(MachineJumpTableInfo *MJTI, std::map &MBBM); virtual void startFunctionStub(unsigned StubSize); virtual void* finishFunctionStub(const Function *F); - virtual void emitByte(unsigned char B); - virtual void emitWord(unsigned W); virtual void addRelocation(const MachineRelocation &MR) { Relocations.push_back(MR); } - virtual uint64_t getCurrentPCValue(); - virtual uint64_t getCurrentPCOffset(); virtual uint64_t getConstantPoolEntryAddress(unsigned Entry); virtual uint64_t getJumpTableEntryAddress(unsigned Entry); virtual unsigned char* allocateGlobal(unsigned size, unsigned alignment); @@ -511,13 +503,16 @@ } void JITEmitter::startFunction(MachineFunction &F) { - CurByte = CurBlock = MemMgr.startFunctionBody(); - TheJIT->addGlobalMapping(F.getFunction(), CurBlock); + BufferBegin = CurBufferPtr = MemMgr.startFunctionBody(); + TheJIT->updateGlobalMapping(F.getFunction(), BufferBegin); + + /// FIXME: implement out of space handling correctly! + BufferEnd = (unsigned char*)(intptr_t)~0ULL; } -void JITEmitter::finishFunction(MachineFunction &F) { - MemMgr.endFunctionBody(CurByte); - NumBytes += CurByte-CurBlock; +bool JITEmitter::finishFunction(MachineFunction &F) { + MemMgr.endFunctionBody(CurBufferPtr); + NumBytes += getCurrentPCOffset(); if (!Relocations.empty()) { NumRelos += Relocations.size(); @@ -534,7 +529,7 @@ ResultPtr = getJITResolver(this).getExternalFunctionStub(ResultPtr); } else if (MR.isGlobalValue()) ResultPtr = getPointerToGlobal(MR.getGlobalValue(), - CurBlock+MR.getMachineCodeOffset(), + BufferBegin+MR.getMachineCodeOffset(), MR.doesntNeedFunctionStub()); else //ConstantPoolIndex ResultPtr = @@ -557,25 +552,26 @@ } } - TheJIT->getJITInfo().relocate(CurBlock, &Relocations[0], + TheJIT->getJITInfo().relocate(BufferBegin, &Relocations[0], Relocations.size(), MemMgr.getGOTBase()); } //Update the GOT entry for F to point to the new code. if(MemMgr.isManagingGOT()) { - unsigned idx = getJITResolver(this).getGOTIndexForAddr((void*)CurBlock); - if (((void**)MemMgr.getGOTBase())[idx] != (void*)CurBlock) { - DEBUG(std::cerr << "GOT was out of date for " << (void*)CurBlock + unsigned idx = getJITResolver(this).getGOTIndexForAddr((void*)BufferBegin); + if (((void**)MemMgr.getGOTBase())[idx] != (void*)BufferBegin) { + DEBUG(std::cerr << "GOT was out of date for " << (void*)BufferBegin << " pointing at " << ((void**)MemMgr.getGOTBase())[idx] << "\n"); - ((void**)MemMgr.getGOTBase())[idx] = (void*)CurBlock; + ((void**)MemMgr.getGOTBase())[idx] = (void*)BufferBegin; } } - DEBUG(std::cerr << "JIT: Finished CodeGen of [" << (void*)CurBlock + DEBUG(std::cerr << "JIT: Finished CodeGen of [" << (void*)BufferBegin << "] Function: " << F.getFunction()->getName() - << ": " << CurByte-CurBlock << " bytes of text, " + << ": " << getCurrentPCOffset() << " bytes of text, " << Relocations.size() << " relocations\n"); Relocations.clear(); + return false; } void JITEmitter::emitConstantPool(MachineConstantPool *MCP) { @@ -648,26 +644,20 @@ } void JITEmitter::startFunctionStub(unsigned StubSize) { - SavedCurBlock = CurBlock; SavedCurByte = CurByte; - CurByte = CurBlock = MemMgr.allocateStub(StubSize); + SavedBufferBegin = BufferBegin; + SavedBufferEnd = BufferEnd; + SavedCurBufferPtr = CurBufferPtr; + + BufferBegin = CurBufferPtr = MemMgr.allocateStub(StubSize); + BufferEnd = BufferBegin+StubSize+1; } void *JITEmitter::finishFunctionStub(const Function *F) { - NumBytes += CurByte-CurBlock; - std::swap(CurBlock, SavedCurBlock); - CurByte = SavedCurByte; - return SavedCurBlock; -} - -void JITEmitter::emitByte(unsigned char B) { - *CurByte++ = B; // Write the byte to memory -} - -void JITEmitter::emitWord(unsigned W) { - // This won't work if the endianness of the host and target don't agree! (For - // a JIT this can't happen though. :) - *(unsigned*)CurByte = W; - CurByte += sizeof(unsigned); + NumBytes += getCurrentPCOffset(); + std::swap(SavedBufferBegin, BufferBegin); + BufferEnd = SavedBufferEnd; + CurBufferPtr = SavedCurBufferPtr; + return SavedBufferBegin; } // getConstantPoolEntryAddress - Return the address of the 'ConstantNum' entry @@ -702,17 +692,6 @@ return MemMgr.allocateGlobal(size, alignment); } -// getCurrentPCValue - This returns the address that the next emitted byte -// will be output to. -// -uint64_t JITEmitter::getCurrentPCValue() { - return (intptr_t)CurByte; -} - -uint64_t JITEmitter::getCurrentPCOffset() { - return (intptr_t)CurByte-(intptr_t)CurBlock; -} - // getPointerToNamedFunction - This function is used as a global wrapper to // JIT::getPointerToNamedFunction for the purpose of resolving symbols when // bugpoint is debugging the JIT. In that scenario, we are loading an .so and From lattner at cs.uiuc.edu Tue May 2 13:27:42 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 2 May 2006 13:27:42 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp Message-ID: <200605021827.NAA12195@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCCodeEmitter.cpp updated: 1.53 -> 1.54 --- Log message: Refactor the machine code emitter interface to pull the pointers for the current code emission location into the base class, instead of being in the derived classes. This change means that low-level methods like emitByte/emitWord now are no longer virtual (yaay for speed), and we now have a framework to support growable code segments. This implements feature request #1 of PR469: http://llvm.cs.uiuc.edu/PR469 . --- Diffs of the changes: (+11 -7) PPCCodeEmitter.cpp | 18 +++++++++++------- 1 files changed, 11 insertions(+), 7 deletions(-) Index: llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp diff -u llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp:1.53 llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp:1.54 --- llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp:1.53 Sat Apr 22 13:53:45 2006 +++ llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp Tue May 2 13:27:26 2006 @@ -89,13 +89,17 @@ assert((MF.getTarget().getRelocationModel() != Reloc::Default || MF.getTarget().getRelocationModel() != Reloc::Static) && "JIT relocation model must be set to static or default!"); - MCE.startFunction(MF); - MCE.emitConstantPool(MF.getConstantPool()); - MCE.initJumpTableInfo(MF.getJumpTableInfo()); - for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB) - emitBasicBlock(*BB); - MCE.emitJumpTableInfo(MF.getJumpTableInfo(), BBLocations); - MCE.finishFunction(MF); + do { + BBRefs.clear(); + BBLocations.clear(); + + MCE.startFunction(MF); + MCE.emitConstantPool(MF.getConstantPool()); + MCE.initJumpTableInfo(MF.getJumpTableInfo()); + for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB) + emitBasicBlock(*BB); + MCE.emitJumpTableInfo(MF.getJumpTableInfo(), BBLocations); + } while (MCE.finishFunction(MF)); // Resolve branches to BasicBlocks for the entire function for (unsigned i = 0, e = BBRefs.size(); i != e; ++i) { From lattner at cs.uiuc.edu Tue May 2 14:15:02 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 2 May 2006 14:15:02 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86CodeEmitter.cpp X86JITInfo.cpp Message-ID: <200605021915.OAA12615@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86CodeEmitter.cpp updated: 1.96 -> 1.97 X86JITInfo.cpp updated: 1.17 -> 1.18 --- Log message: Fix a purely hypothetical problem (for now): emitWord emits in the host byte format. This doesn't work when using the code emitter in a cross target environment. Since the code emitter is only really used by the JIT, this isn't a current problem, but if we ever start emitting .o files, it would be. --- Diffs of the changes: (+7 -7) X86CodeEmitter.cpp | 10 +++++----- X86JITInfo.cpp | 4 ++-- 2 files changed, 7 insertions(+), 7 deletions(-) Index: llvm/lib/Target/X86/X86CodeEmitter.cpp diff -u llvm/lib/Target/X86/X86CodeEmitter.cpp:1.96 llvm/lib/Target/X86/X86CodeEmitter.cpp:1.97 --- llvm/lib/Target/X86/X86CodeEmitter.cpp:1.96 Tue May 2 13:27:26 2006 +++ llvm/lib/Target/X86/X86CodeEmitter.cpp Tue May 2 14:14:47 2006 @@ -116,7 +116,7 @@ /// emitPCRelativeValue - Emit a 32-bit PC relative address. /// void Emitter::emitPCRelativeValue(unsigned Address) { - MCE.emitWord(Address-MCE.getCurrentPCValue()-4); + MCE.emitWordLE(Address-MCE.getCurrentPCValue()-4); } /// emitPCRelativeBlockAddress - This method emits the PC relative address of @@ -134,7 +134,7 @@ // Otherwise, remember where this reference was and where it is to so we can // deal with it later. BBRefs.push_back(std::make_pair(MBB, MCE.getCurrentPCValue())); - MCE.emitWord(0); + MCE.emitWordLE(0); } } @@ -145,7 +145,7 @@ MCE.addRelocation(MachineRelocation(MCE.getCurrentPCOffset(), X86::reloc_pcrel_word, GV, 0, !isTailCall /*Doesn'tNeedStub*/)); - MCE.emitWord(0); + MCE.emitWordLE(0); } /// emitGlobalAddress - Emit the specified address to the code stream assuming @@ -155,7 +155,7 @@ void Emitter::emitGlobalAddressForPtr(GlobalValue *GV, int Disp /* = 0 */) { MCE.addRelocation(MachineRelocation(MCE.getCurrentPCOffset(), X86::reloc_absolute_word, GV)); - MCE.emitWord(Disp); // The relocated value will be added to the displacement + MCE.emitWordLE(Disp); // The relocated value will be added to the displacement } /// emitExternalSymbolAddress - Arrange for the address of an external symbol to @@ -165,7 +165,7 @@ bool isTailCall) { MCE.addRelocation(MachineRelocation(MCE.getCurrentPCOffset(), isPCRelative ? X86::reloc_pcrel_word : X86::reloc_absolute_word, ES)); - MCE.emitWord(0); + MCE.emitWordLE(0); } /// N86 namespace - Native X86 Register numbers... used by X86 backend. Index: llvm/lib/Target/X86/X86JITInfo.cpp diff -u llvm/lib/Target/X86/X86JITInfo.cpp:1.17 llvm/lib/Target/X86/X86JITInfo.cpp:1.18 --- llvm/lib/Target/X86/X86JITInfo.cpp:1.17 Sat Apr 29 13:41:44 2006 +++ llvm/lib/Target/X86/X86JITInfo.cpp Tue May 2 14:14:47 2006 @@ -170,14 +170,14 @@ if (Fn != X86CompilationCallback) { MCE.startFunctionStub(5); MCE.emitByte(0xE9); - MCE.emitWord((intptr_t)Fn-MCE.getCurrentPCValue()-4); + MCE.emitWordLE((intptr_t)Fn-MCE.getCurrentPCValue()-4); return MCE.finishFunctionStub(0); } MCE.startFunctionStub(6); MCE.emitByte(0xE8); // Call with 32 bit pc-rel destination... - MCE.emitWord((intptr_t)Fn-MCE.getCurrentPCValue()-4); + MCE.emitWordLE((intptr_t)Fn-MCE.getCurrentPCValue()-4); MCE.emitByte(0xCD); // Interrupt - Just a marker identifying the stub! return MCE.finishFunctionStub(0); From lattner at cs.uiuc.edu Tue May 2 14:15:02 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 2 May 2006 14:15:02 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp AlphaJITInfo.cpp Message-ID: <200605021915.OAA12625@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Alpha: AlphaCodeEmitter.cpp updated: 1.10 -> 1.11 AlphaJITInfo.cpp updated: 1.8 -> 1.9 --- Log message: Fix a purely hypothetical problem (for now): emitWord emits in the host byte format. This doesn't work when using the code emitter in a cross target environment. Since the code emitter is only really used by the JIT, this isn't a current problem, but if we ever start emitting .o files, it would be. --- Diffs of the changes: (+2 -6) AlphaCodeEmitter.cpp | 6 +----- AlphaJITInfo.cpp | 2 +- 2 files changed, 2 insertions(+), 6 deletions(-) Index: llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp diff -u llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp:1.10 llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp:1.11 --- llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp:1.10 Tue May 2 13:27:26 2006 +++ llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp Tue May 2 14:14:47 2006 @@ -55,10 +55,6 @@ void emitInstruction(const MachineInstr &MI); - /// emitWord - write a 32-bit word to memory at the current PC - /// - void emitWord(unsigned w) { MCE.emitWord(w); } - /// getBinaryCodeForInstr - This function, generated by the /// CodeEmitterGenerator using TableGen, produces the binary encoding for /// machine instructions. @@ -117,7 +113,7 @@ unsigned Opcode = MI.getOpcode(); switch(MI.getOpcode()) { default: - emitWord(getBinaryCodeForInstr(*I)); + MCE.emitWordLE(getBinaryCodeForInstr(*I)); break; case Alpha::ALTENT: case Alpha::PCLABEL: Index: llvm/lib/Target/Alpha/AlphaJITInfo.cpp diff -u llvm/lib/Target/Alpha/AlphaJITInfo.cpp:1.8 llvm/lib/Target/Alpha/AlphaJITInfo.cpp:1.9 --- llvm/lib/Target/Alpha/AlphaJITInfo.cpp:1.8 Sun Jan 1 16:20:31 2006 +++ llvm/lib/Target/Alpha/AlphaJITInfo.cpp Tue May 2 14:14:47 2006 @@ -197,7 +197,7 @@ MCE.startFunctionStub(19*4); void* Addr = (void*)(intptr_t)MCE.getCurrentPCValue(); for (int x = 0; x < 19; ++ x) - MCE.emitWord(0); + MCE.emitWordLE(0); EmitBranchToAt(Addr, Fn); DEBUG(std::cerr << "Emitting Stub to " << Fn << " at [" << Addr << "]\n"); return MCE.finishFunctionStub(0); From lattner at cs.uiuc.edu Tue May 2 14:15:02 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 2 May 2006 14:15:02 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp PPCJITInfo.cpp Message-ID: <200605021915.OAA12631@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCCodeEmitter.cpp updated: 1.54 -> 1.55 PPCJITInfo.cpp updated: 1.20 -> 1.21 --- Log message: Fix a purely hypothetical problem (for now): emitWord emits in the host byte format. This doesn't work when using the code emitter in a cross target environment. Since the code emitter is only really used by the JIT, this isn't a current problem, but if we ever start emitting .o files, it would be. --- Diffs of the changes: (+12 -16) PPCCodeEmitter.cpp | 6 +----- PPCJITInfo.cpp | 22 +++++++++++----------- 2 files changed, 12 insertions(+), 16 deletions(-) Index: llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp diff -u llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp:1.54 llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp:1.55 --- llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp:1.54 Tue May 2 13:27:26 2006 +++ llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp Tue May 2 14:14:47 2006 @@ -54,10 +54,6 @@ /// void emitBasicBlock(MachineBasicBlock &MBB); - /// emitWord - write a 32-bit word to memory at the current PC - /// - void emitWord(unsigned w) { MCE.emitWord(w); } - /// getValueBit - return the particular bit of Val /// unsigned getValueBit(int64_t Val, unsigned bit) { return (Val >> bit) & 1; } @@ -133,7 +129,7 @@ unsigned Opcode = MI.getOpcode(); switch (MI.getOpcode()) { default: - emitWord(getBinaryCodeForInstr(*I)); + MCE.emitWordBE(getBinaryCodeForInstr(*I)); break; case PPC::IMPLICIT_DEF_GPR: case PPC::IMPLICIT_DEF_F8: Index: llvm/lib/Target/PowerPC/PPCJITInfo.cpp diff -u llvm/lib/Target/PowerPC/PPCJITInfo.cpp:1.20 llvm/lib/Target/PowerPC/PPCJITInfo.cpp:1.21 --- llvm/lib/Target/PowerPC/PPCJITInfo.cpp:1.20 Mon May 1 23:50:05 2006 +++ llvm/lib/Target/PowerPC/PPCJITInfo.cpp Tue May 2 14:14:47 2006 @@ -168,23 +168,23 @@ if (Fn != PPC32CompilationCallback) { MCE.startFunctionStub(4*4); void *Addr = (void*)(intptr_t)MCE.getCurrentPCValue(); - MCE.emitWord(0); - MCE.emitWord(0); - MCE.emitWord(0); - MCE.emitWord(0); + MCE.emitWordBE(0); + MCE.emitWordBE(0); + MCE.emitWordBE(0); + MCE.emitWordBE(0); EmitBranchToAt(Addr, Fn, false); return MCE.finishFunctionStub(0); } MCE.startFunctionStub(4*7); - MCE.emitWord(0x9421ffe0); // stwu r1,-32(r1) - MCE.emitWord(0x7d6802a6); // mflr r11 - MCE.emitWord(0x91610028); // stw r11, 40(r1) + MCE.emitWordBE(0x9421ffe0); // stwu r1,-32(r1) + MCE.emitWordBE(0x7d6802a6); // mflr r11 + MCE.emitWordBE(0x91610028); // stw r11, 40(r1) void *Addr = (void*)(intptr_t)MCE.getCurrentPCValue(); - MCE.emitWord(0); - MCE.emitWord(0); - MCE.emitWord(0); - MCE.emitWord(0); + MCE.emitWordBE(0); + MCE.emitWordBE(0); + MCE.emitWordBE(0); + MCE.emitWordBE(0); EmitBranchToAt(Addr, Fn, true/*is call*/); return MCE.finishFunctionStub(0); } From lattner at cs.uiuc.edu Tue May 2 14:15:02 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 2 May 2006 14:15:02 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineCodeEmitter.h Message-ID: <200605021915.OAA12617@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineCodeEmitter.h updated: 1.33 -> 1.34 --- Log message: Fix a purely hypothetical problem (for now): emitWord emits in the host byte format. This doesn't work when using the code emitter in a cross target environment. Since the code emitter is only really used by the JIT, this isn't a current problem, but if we ever start emitting .o files, it would be. --- Diffs of the changes: (+21 -6) MachineCodeEmitter.h | 27 +++++++++++++++++++++------ 1 files changed, 21 insertions(+), 6 deletions(-) Index: llvm/include/llvm/CodeGen/MachineCodeEmitter.h diff -u llvm/include/llvm/CodeGen/MachineCodeEmitter.h:1.33 llvm/include/llvm/CodeGen/MachineCodeEmitter.h:1.34 --- llvm/include/llvm/CodeGen/MachineCodeEmitter.h:1.33 Tue May 2 13:27:26 2006 +++ llvm/include/llvm/CodeGen/MachineCodeEmitter.h Tue May 2 14:14:47 2006 @@ -112,14 +112,29 @@ *CurBufferPtr++ = B; } - /// emitWord - This callback is invoked when a word needs to be written to the - /// output stream. + /// emitWordLE - This callback is invoked when a 32-bit word needs to be + /// written to the output stream in little-endian format. /// - void emitWord(unsigned W) { - // FIXME: handle endian mismatches for .o file emission. + void emitWordLE(unsigned W) { if (CurBufferPtr+4 <= BufferEnd) { - *(unsigned*)CurBufferPtr = W; - CurBufferPtr += 4; + *CurBufferPtr++ = (unsigned char)(W >> 0); + *CurBufferPtr++ = (unsigned char)(W >> 8); + *CurBufferPtr++ = (unsigned char)(W >> 16); + *CurBufferPtr++ = (unsigned char)(W >> 24); + } else { + CurBufferPtr = BufferEnd; + } + } + + /// emitWordBE - This callback is invoked when a 32-bit word needs to be + /// written to the output stream in big-endian format. + /// + void emitWordBE(unsigned W) { + if (CurBufferPtr+4 <= BufferEnd) { + *CurBufferPtr++ = (unsigned char)(W >> 24); + *CurBufferPtr++ = (unsigned char)(W >> 16); + *CurBufferPtr++ = (unsigned char)(W >> 8); + *CurBufferPtr++ = (unsigned char)(W >> 0); } else { CurBufferPtr = BufferEnd; } From lattner at cs.uiuc.edu Tue May 2 16:44:28 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 2 May 2006 16:44:28 -0500 Subject: [llvm-commits] CVS: llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp Message-ID: <200605022144.QAA14265@zion.cs.uiuc.edu> Changes in directory llvm/lib/ExecutionEngine/JIT: JITEmitter.cpp updated: 1.86 -> 1.87 --- Log message: Minor cleanups, no functionality change. --- Diffs of the changes: (+11 -17) JITEmitter.cpp | 28 +++++++++++----------------- 1 files changed, 11 insertions(+), 17 deletions(-) Index: llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp diff -u llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.86 llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.87 --- llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.86 Tue May 2 13:27:26 2006 +++ llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp Tue May 2 16:44:14 2006 @@ -54,10 +54,10 @@ class JITMemoryManager { std::list Blocks; // List of blocks allocated by the JIT unsigned char *FunctionBase; // Start of the function body area - unsigned char *GlobalBase; // Start of the Global area + unsigned char *GlobalBase; // Start of the Global area unsigned char *ConstantBase; // Memory allocated for constant pools unsigned char *CurStubPtr, *CurFunctionPtr, *CurConstantPtr, *CurGlobalPtr; - unsigned char *GOTBase; //Target Specific reserved memory + unsigned char *GOTBase; // Target Specific reserved memory // centralize memory block allocation sys::MemoryBlock getNewMemoryBlock(unsigned size); @@ -72,9 +72,13 @@ unsigned Alignment); inline unsigned char *startFunctionBody(); inline void endFunctionBody(unsigned char *FunctionEnd); - inline unsigned char* getGOTBase() const; - - inline bool isManagingGOT() const; + + unsigned char *getGOTBase() const { + return GOTBase; + } + bool isManagingGOT() const { + return GOTBase != NULL; + } }; } @@ -117,7 +121,7 @@ unsigned char *JITMemoryManager::allocateStub(unsigned StubSize) { CurStubPtr -= StubSize; if (CurStubPtr < FunctionBase) { - //FIXME: allocate a new block + // FIXME: allocate a new block std::cerr << "JIT ran out of memory for function stubs!\n"; abort(); } @@ -169,14 +173,6 @@ CurFunctionPtr = FunctionEnd; } -unsigned char* JITMemoryManager::getGOTBase() const { - return GOTBase; -} - -bool JITMemoryManager::isManagingGOT() const { - return GOTBase != NULL; -} - sys::MemoryBlock JITMemoryManager::getNewMemoryBlock(unsigned size) { const sys::MemoryBlock* BOld = 0; if (Blocks.size()) @@ -439,9 +435,7 @@ public: JITEmitter(JIT &jit) : MemMgr(jit.getJITInfo().needsGOT()) { TheJIT = &jit; - DEBUG(std::cerr << - (MemMgr.isManagingGOT() ? "JIT is managing GOT\n" - : "JIT is not managing GOT\n")); + DEBUG(if (MemMgr.isManagingGOT()) std::cerr << "JIT is managing a GOT\n"); } virtual void startFunction(MachineFunction &F); From lattner at cs.uiuc.edu Tue May 2 16:58:04 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 2 May 2006 16:58:04 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineCodeEmitter.h Message-ID: <200605022158.QAA14506@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineCodeEmitter.h updated: 1.34 -> 1.35 --- Log message: Do not make the JIT memory manager manage the memory for globals. Instead just have the JIT malloc them. --- Diffs of the changes: (+0 -3) MachineCodeEmitter.h | 3 --- 1 files changed, 3 deletions(-) Index: llvm/include/llvm/CodeGen/MachineCodeEmitter.h diff -u llvm/include/llvm/CodeGen/MachineCodeEmitter.h:1.34 llvm/include/llvm/CodeGen/MachineCodeEmitter.h:1.35 --- llvm/include/llvm/CodeGen/MachineCodeEmitter.h:1.34 Tue May 2 14:14:47 2006 +++ llvm/include/llvm/CodeGen/MachineCodeEmitter.h Tue May 2 16:57:51 2006 @@ -166,9 +166,6 @@ /// 'Index' in the function that last called initJumpTableInfo. /// virtual uint64_t getJumpTableEntryAddress(unsigned Index) = 0; - - // allocateGlobal - Allocate some space for a global variable. - virtual unsigned char* allocateGlobal(unsigned size, unsigned alignment) = 0; }; } // End llvm namespace From lattner at cs.uiuc.edu Tue May 2 16:58:05 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 2 May 2006 16:58:05 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/ELFWriter.cpp Message-ID: <200605022158.QAA14510@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: ELFWriter.cpp updated: 1.20 -> 1.21 --- Log message: Do not make the JIT memory manager manage the memory for globals. Instead just have the JIT malloc them. --- Diffs of the changes: (+0 -4) ELFWriter.cpp | 4 ---- 1 files changed, 4 deletions(-) Index: llvm/lib/CodeGen/ELFWriter.cpp diff -u llvm/lib/CodeGen/ELFWriter.cpp:1.20 llvm/lib/CodeGen/ELFWriter.cpp:1.21 --- llvm/lib/CodeGen/ELFWriter.cpp:1.20 Tue May 2 13:27:26 2006 +++ llvm/lib/CodeGen/ELFWriter.cpp Tue May 2 16:57:51 2006 @@ -73,10 +73,6 @@ assert(0 && "JT not implementated yet!"); return 0; } - virtual unsigned char* allocateGlobal(unsigned size, unsigned alignment) { - assert(0 && "Globals not implemented yet!"); - return 0; - } /// JIT SPECIFIC FUNCTIONS - DO NOT IMPLEMENT THESE HERE! void startFunctionStub(unsigned StubSize) { From lattner at cs.uiuc.edu Tue May 2 16:58:05 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 2 May 2006 16:58:05 -0500 Subject: [llvm-commits] CVS: llvm/lib/ExecutionEngine/JIT/JIT.cpp JITEmitter.cpp Message-ID: <200605022158.QAA14516@zion.cs.uiuc.edu> Changes in directory llvm/lib/ExecutionEngine/JIT: JIT.cpp updated: 1.61 -> 1.62 JITEmitter.cpp updated: 1.87 -> 1.88 --- Log message: Do not make the JIT memory manager manage the memory for globals. Instead just have the JIT malloc them. --- Diffs of the changes: (+19 -39) JIT.cpp | 20 ++++++++++++++++---- JITEmitter.cpp | 38 +++----------------------------------- 2 files changed, 19 insertions(+), 39 deletions(-) Index: llvm/lib/ExecutionEngine/JIT/JIT.cpp diff -u llvm/lib/ExecutionEngine/JIT/JIT.cpp:1.61 llvm/lib/ExecutionEngine/JIT/JIT.cpp:1.62 --- llvm/lib/ExecutionEngine/JIT/JIT.cpp:1.61 Thu Mar 23 20:53:49 2006 +++ llvm/lib/ExecutionEngine/JIT/JIT.cpp Tue May 2 16:57:51 2006 @@ -301,10 +301,22 @@ // If the global hasn't been emitted to memory yet, allocate space. We will // actually initialize the global after current function has finished // compilation. - uint64_t S = getTargetData().getTypeSize(GV->getType()->getElementType()); - unsigned char A = - getTargetData().getTypeAlignment(GV->getType()->getElementType()); - Ptr = MCE->allocateGlobal(S, A); + const Type *GlobalType = GV->getType()->getElementType(); + size_t S = getTargetData().getTypeSize(GlobalType); + size_t A = getTargetData().getTypeAlignment(GlobalType); + if (A <= 8) { + Ptr = malloc(S); + } else { + // Allocate S+A bytes of memory, then use an aligned pointer within that + // space. + Ptr = malloc(S+A); + unsigned MisAligned = ((intptr_t)Ptr & (A-1)); + unsigned Offset = MisAligned ? (A-MisAligned) : 0; + + // Trim the tail off the memory block. + realloc(Ptr, S+Offset); + Ptr = (char*)Ptr + Offset; + } state.getPendingGlobals(locked).push_back(GV); } addGlobalMapping(GV, Ptr); Index: llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp diff -u llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.87 llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.88 --- llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.87 Tue May 2 16:44:14 2006 +++ llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp Tue May 2 16:57:51 2006 @@ -54,9 +54,8 @@ class JITMemoryManager { std::list Blocks; // List of blocks allocated by the JIT unsigned char *FunctionBase; // Start of the function body area - unsigned char *GlobalBase; // Start of the Global area unsigned char *ConstantBase; // Memory allocated for constant pools - unsigned char *CurStubPtr, *CurFunctionPtr, *CurConstantPtr, *CurGlobalPtr; + unsigned char *CurStubPtr, *CurFunctionPtr, *CurConstantPtr; unsigned char *GOTBase; // Target Specific reserved memory // centralize memory block allocation @@ -68,8 +67,6 @@ inline unsigned char *allocateStub(unsigned StubSize); inline unsigned char *allocateConstant(unsigned ConstantSize, unsigned Alignment); - inline unsigned char* allocateGlobal(unsigned Size, - unsigned Alignment); inline unsigned char *startFunctionBody(); inline void endFunctionBody(unsigned char *FunctionEnd); @@ -87,28 +84,22 @@ sys::MemoryBlock FunBlock = getNewMemoryBlock(16 << 20); // Allocate a 1M block of memory for Constants sys::MemoryBlock ConstBlock = getNewMemoryBlock(1 << 20); - // Allocate a 1M Block of memory for Globals - sys::MemoryBlock GVBlock = getNewMemoryBlock(1 << 20); Blocks.push_front(FunBlock); Blocks.push_front(ConstBlock); - Blocks.push_front(GVBlock); FunctionBase = reinterpret_cast(FunBlock.base()); ConstantBase = reinterpret_cast(ConstBlock.base()); - GlobalBase = reinterpret_cast(GVBlock.base()); // Allocate stubs backwards from the base, allocate functions forward // from the base. CurStubPtr = CurFunctionPtr = FunctionBase + 512*1024;// Use 512k for stubs CurConstantPtr = ConstantBase + ConstBlock.size(); - CurGlobalPtr = GlobalBase + GVBlock.size(); - //Allocate the GOT just like a global array + // Allocate the GOT. GOTBase = NULL; - if (useGOT) - GOTBase = allocateGlobal(sizeof(void*) * 8192, 8); + if (useGOT) GOTBase = (unsigned char*)malloc(sizeof(void*) * 8192); } JITMemoryManager::~JITMemoryManager() { @@ -145,23 +136,6 @@ return CurConstantPtr; } -unsigned char *JITMemoryManager::allocateGlobal(unsigned Size, - unsigned Alignment) { - // Reserve space and align pointer. - CurGlobalPtr -= Size; - CurGlobalPtr = - (unsigned char *)((intptr_t)CurGlobalPtr & ~((intptr_t)Alignment - 1)); - - if (CurGlobalPtr < GlobalBase) { - //Either allocate another MB or 2xSize - sys::MemoryBlock GVBlock = getNewMemoryBlock(2 * Size); - GlobalBase = reinterpret_cast(GVBlock.base()); - CurGlobalPtr = GlobalBase + GVBlock.size(); - return allocateGlobal(Size, Alignment); - } - return CurGlobalPtr; -} - unsigned char *JITMemoryManager::startFunctionBody() { // Round up to an even multiple of 8 bytes, this should eventually be target // specific. @@ -453,7 +427,6 @@ virtual uint64_t getConstantPoolEntryAddress(unsigned Entry); virtual uint64_t getJumpTableEntryAddress(unsigned Entry); - virtual unsigned char* allocateGlobal(unsigned size, unsigned alignment); private: void *getPointerToGlobal(GlobalValue *GV, void *Reference, bool NoNeedStub); @@ -681,11 +654,6 @@ return (intptr_t)((char *)JumpTableBase + Offset); } -unsigned char* JITEmitter::allocateGlobal(unsigned size, unsigned alignment) -{ - return MemMgr.allocateGlobal(size, alignment); -} - // getPointerToNamedFunction - This function is used as a global wrapper to // JIT::getPointerToNamedFunction for the purpose of resolving symbols when // bugpoint is debugging the JIT. In that scenario, we are loading an .so and From natebegeman at mac.com Tue May 2 17:43:43 2006 From: natebegeman at mac.com (Nate Begeman) Date: Tue, 2 May 2006 17:43:43 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/README.txt Message-ID: <200605022243.RAA21886@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: README.txt updated: 1.100 -> 1.101 --- Log message: Remove some stuff from the README --- Diffs of the changes: (+0 -21) README.txt | 21 --------------------- 1 files changed, 21 deletions(-) Index: llvm/lib/Target/X86/README.txt diff -u llvm/lib/Target/X86/README.txt:1.100 llvm/lib/Target/X86/README.txt:1.101 --- llvm/lib/Target/X86/README.txt:1.100 Thu Apr 27 16:40:57 2006 +++ llvm/lib/Target/X86/README.txt Tue May 2 17:43:31 2006 @@ -1126,27 +1126,6 @@ //===---------------------------------------------------------------------===// -typedef short v8i16 __attribute__ ((__vector_size__ (16))); -v8i16 test(v8i16 x, v8i16 y) { - return x + y; -} - -compiles to - -_test: - paddw %xmm0, %xmm1 - movaps %xmm1, %xmm0 - ret - -It should be - - paddw %xmm1, %xmm0 - ret - -since paddw is commutative. - -//===---------------------------------------------------------------------===// - This testcase: %G1 = weak global <4 x float> zeroinitializer ; <<4 x float>*> [#uses=1] From lattner at cs.uiuc.edu Tue May 2 17:51:15 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 2 May 2006 17:51:15 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineCodeEmitter.h Message-ID: <200605022251.RAA28628@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineCodeEmitter.h updated: 1.35 -> 1.36 --- Log message: Add a method for allocating space from the code buffer. --- Diffs of the changes: (+22 -0) MachineCodeEmitter.h | 22 ++++++++++++++++++++++ 1 files changed, 22 insertions(+) Index: llvm/include/llvm/CodeGen/MachineCodeEmitter.h diff -u llvm/include/llvm/CodeGen/MachineCodeEmitter.h:1.35 llvm/include/llvm/CodeGen/MachineCodeEmitter.h:1.36 --- llvm/include/llvm/CodeGen/MachineCodeEmitter.h:1.35 Tue May 2 16:57:51 2006 +++ llvm/include/llvm/CodeGen/MachineCodeEmitter.h Tue May 2 17:51:03 2006 @@ -140,6 +140,28 @@ } } + /// allocateSpace - Allocate a block of space in the current output buffer, + /// returning null (and setting conditions to indicate buffer overflow) on + /// failure. Alignment is the alignment in bytes of the buffer desired. + void *allocateSpace(intptr_t Size, unsigned Alignment) { + if (Alignment == 0) Alignment = 1; + // Move the current buffer ptr up to the specified alignment. + CurBufferPtr = + (unsigned char*)(((intptr_t)CurBufferPtr+Alignment-1) & ~(Alignment-1)); + void *Result = CurBufferPtr; + + // Allocate the space. + CurBufferPtr += Size; + + // Check for buffer overflow. + if (CurBufferPtr >= BufferEnd) { + CurBufferPtr = BufferEnd; + Result = 0; + } + return Result; + } + + /// getCurrentPCValue - This returns the address that the next emitted byte /// will be output to. /// From lattner at cs.uiuc.edu Tue May 2 18:22:39 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 2 May 2006 18:22:39 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86CodeEmitter.cpp Message-ID: <200605022322.SAA29006@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86CodeEmitter.cpp updated: 1.97 -> 1.98 --- Log message: Several related changes: 1. Change several methods in the MachineCodeEmitter class to be pure virtual. 2. Suck emitConstantPool/initJumpTableInfo into startFunction, removing them from the MachineCodeEmitter interface, and reducing the amount of target- specific code. 3. Change the JITEmitter so that it allocates constantpools and jump tables *right* next to the functions that they belong to, instead of in a separate pool of memory. This makes all memory for a function be contiguous, and means the JITEmitter only tracks one block of memory now. --- Diffs of the changes: (+0 -2) X86CodeEmitter.cpp | 2 -- 1 files changed, 2 deletions(-) Index: llvm/lib/Target/X86/X86CodeEmitter.cpp diff -u llvm/lib/Target/X86/X86CodeEmitter.cpp:1.97 llvm/lib/Target/X86/X86CodeEmitter.cpp:1.98 --- llvm/lib/Target/X86/X86CodeEmitter.cpp:1.97 Tue May 2 14:14:47 2006 +++ llvm/lib/Target/X86/X86CodeEmitter.cpp Tue May 2 18:22:24 2006 @@ -86,8 +86,6 @@ BasicBlockAddrs.clear(); MCE.startFunction(MF); - MCE.emitConstantPool(MF.getConstantPool()); - MCE.initJumpTableInfo(MF.getJumpTableInfo()); for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) emitBasicBlock(*I); MCE.emitJumpTableInfo(MF.getJumpTableInfo(), BasicBlockAddrs); From lattner at cs.uiuc.edu Tue May 2 18:22:40 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 2 May 2006 18:22:40 -0500 Subject: [llvm-commits] CVS: llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp Message-ID: <200605022322.SAA29010@zion.cs.uiuc.edu> Changes in directory llvm/lib/ExecutionEngine/JIT: JITEmitter.cpp updated: 1.88 -> 1.89 --- Log message: Several related changes: 1. Change several methods in the MachineCodeEmitter class to be pure virtual. 2. Suck emitConstantPool/initJumpTableInfo into startFunction, removing them from the MachineCodeEmitter interface, and reducing the amount of target- specific code. 3. Change the JITEmitter so that it allocates constantpools and jump tables *right* next to the functions that they belong to, instead of in a separate pool of memory. This makes all memory for a function be contiguous, and means the JITEmitter only tracks one block of memory now. --- Diffs of the changes: (+23 -39) JITEmitter.cpp | 62 +++++++++++++++++++++------------------------------------ 1 files changed, 23 insertions(+), 39 deletions(-) Index: llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp diff -u llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.88 llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.89 --- llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.88 Tue May 2 16:57:51 2006 +++ llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp Tue May 2 18:22:24 2006 @@ -54,8 +54,7 @@ class JITMemoryManager { std::list Blocks; // List of blocks allocated by the JIT unsigned char *FunctionBase; // Start of the function body area - unsigned char *ConstantBase; // Memory allocated for constant pools - unsigned char *CurStubPtr, *CurFunctionPtr, *CurConstantPtr; + unsigned char *CurStubPtr, *CurFunctionPtr; unsigned char *GOTBase; // Target Specific reserved memory // centralize memory block allocation @@ -65,8 +64,6 @@ ~JITMemoryManager(); inline unsigned char *allocateStub(unsigned StubSize); - inline unsigned char *allocateConstant(unsigned ConstantSize, - unsigned Alignment); inline unsigned char *startFunctionBody(); inline void endFunctionBody(unsigned char *FunctionEnd); @@ -82,21 +79,15 @@ JITMemoryManager::JITMemoryManager(bool useGOT) { // Allocate a 16M block of memory for functions sys::MemoryBlock FunBlock = getNewMemoryBlock(16 << 20); - // Allocate a 1M block of memory for Constants - sys::MemoryBlock ConstBlock = getNewMemoryBlock(1 << 20); Blocks.push_front(FunBlock); - Blocks.push_front(ConstBlock); FunctionBase = reinterpret_cast(FunBlock.base()); - ConstantBase = reinterpret_cast(ConstBlock.base()); // Allocate stubs backwards from the base, allocate functions forward // from the base. CurStubPtr = CurFunctionPtr = FunctionBase + 512*1024;// Use 512k for stubs - CurConstantPtr = ConstantBase + ConstBlock.size(); - // Allocate the GOT. GOTBase = NULL; if (useGOT) GOTBase = (unsigned char*)malloc(sizeof(void*) * 8192); @@ -119,23 +110,6 @@ return CurStubPtr; } -unsigned char *JITMemoryManager::allocateConstant(unsigned ConstantSize, - unsigned Alignment) { - // Reserve space and align pointer. - CurConstantPtr -= ConstantSize; - CurConstantPtr = - (unsigned char *)((intptr_t)CurConstantPtr & ~((intptr_t)Alignment - 1)); - - if (CurConstantPtr < ConstantBase) { - //Either allocate another MB or 2xConstantSize - sys::MemoryBlock ConstBlock = getNewMemoryBlock(2 * ConstantSize); - ConstantBase = reinterpret_cast(ConstBlock.base()); - CurConstantPtr = ConstantBase + ConstBlock.size(); - return allocateConstant(ConstantSize, Alignment); - } - return CurConstantPtr; -} - unsigned char *JITMemoryManager::startFunctionBody() { // Round up to an even multiple of 8 bytes, this should eventually be target // specific. @@ -414,10 +388,12 @@ virtual void startFunction(MachineFunction &F); virtual bool finishFunction(MachineFunction &F); - virtual void emitConstantPool(MachineConstantPool *MCP); - virtual void initJumpTableInfo(MachineJumpTableInfo *MJTI); + + void emitConstantPool(MachineConstantPool *MCP); + void initJumpTableInfo(MachineJumpTableInfo *MJTI); virtual void emitJumpTableInfo(MachineJumpTableInfo *MJTI, std::map &MBBM); + virtual void startFunctionStub(unsigned StubSize); virtual void* finishFunctionStub(const Function *F); @@ -471,10 +447,16 @@ void JITEmitter::startFunction(MachineFunction &F) { BufferBegin = CurBufferPtr = MemMgr.startFunctionBody(); - TheJIT->updateGlobalMapping(F.getFunction(), BufferBegin); /// FIXME: implement out of space handling correctly! BufferEnd = (unsigned char*)(intptr_t)~0ULL; + + emitConstantPool(F.getConstantPool()); + initJumpTableInfo(F.getJumpTableInfo()); + + // About to start emitting the machine code for the function. + // FIXME: align it? + TheJIT->updateGlobalMapping(F.getFunction(), CurBufferPtr); } bool JITEmitter::finishFunction(MachineFunction &F) { @@ -548,10 +530,11 @@ unsigned Size = Constants.back().Offset; Size += TheJIT->getTargetData().getTypeSize(Constants.back().Val->getType()); - ConstantPoolBase = MemMgr.allocateConstant(Size, - 1 << MCP->getConstantPoolAlignment()); + ConstantPoolBase = allocateSpace(Size, 1 << MCP->getConstantPoolAlignment()); ConstantPool = MCP; - + + if (ConstantPoolBase == 0) return; // Buffer overflow. + // Initialize the memory for all of the constant pool entries. for (unsigned i = 0, e = Constants.size(); i != e; ++i) { void *CAddr = (char*)ConstantPoolBase+Constants[i].Offset; @@ -563,22 +546,23 @@ const std::vector &JT = MJTI->getJumpTables(); if (JT.empty()) return; - unsigned Size = 0; - unsigned EntrySize = MJTI->getEntrySize(); + unsigned NumEntries = 0; for (unsigned i = 0, e = JT.size(); i != e; ++i) - Size += JT[i].MBBs.size() * EntrySize; - + NumEntries += JT[i].MBBs.size(); + + unsigned EntrySize = MJTI->getEntrySize(); + // Just allocate space for all the jump tables now. We will fix up the actual // MBB entries in the tables after we emit the code for each block, since then // we will know the final locations of the MBBs in memory. JumpTable = MJTI; - JumpTableBase = MemMgr.allocateConstant(Size, MJTI->getAlignment()); + JumpTableBase = allocateSpace(NumEntries * EntrySize, MJTI->getAlignment()); } void JITEmitter::emitJumpTableInfo(MachineJumpTableInfo *MJTI, std::map &MBBM){ const std::vector &JT = MJTI->getJumpTables(); - if (JT.empty()) return; + if (JT.empty() || JumpTableBase == 0) return; unsigned Offset = 0; unsigned EntrySize = MJTI->getEntrySize(); From lattner at cs.uiuc.edu Tue May 2 18:22:40 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 2 May 2006 18:22:40 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineCodeEmitter.h Message-ID: <200605022322.SAA29012@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineCodeEmitter.h updated: 1.36 -> 1.37 --- Log message: Several related changes: 1. Change several methods in the MachineCodeEmitter class to be pure virtual. 2. Suck emitConstantPool/initJumpTableInfo into startFunction, removing them from the MachineCodeEmitter interface, and reducing the amount of target- specific code. 3. Change the JITEmitter so that it allocates constantpools and jump tables *right* next to the functions that they belong to, instead of in a separate pool of memory. This makes all memory for a function be contiguous, and means the JITEmitter only tracks one block of memory now. --- Diffs of the changes: (+5 -15) MachineCodeEmitter.h | 20 +++++--------------- 1 files changed, 5 insertions(+), 15 deletions(-) Index: llvm/include/llvm/CodeGen/MachineCodeEmitter.h diff -u llvm/include/llvm/CodeGen/MachineCodeEmitter.h:1.36 llvm/include/llvm/CodeGen/MachineCodeEmitter.h:1.37 --- llvm/include/llvm/CodeGen/MachineCodeEmitter.h:1.36 Tue May 2 17:51:03 2006 +++ llvm/include/llvm/CodeGen/MachineCodeEmitter.h Tue May 2 18:22:24 2006 @@ -65,31 +65,21 @@ /// about to be code generated. This initializes the BufferBegin/End/Ptr /// fields. /// - virtual void startFunction(MachineFunction &F) {} + virtual void startFunction(MachineFunction &F) = 0; /// finishFunction - This callback is invoked when the specified function has /// finished code generation. If a buffer overflow has occurred, this method /// returns true (the callee is required to try again), otherwise it returns /// false. /// - virtual bool finishFunction(MachineFunction &F) { - return CurBufferPtr == BufferEnd; - } - - /// emitConstantPool - This callback is invoked to output the constant pool - /// for the function. - virtual void emitConstantPool(MachineConstantPool *MCP) {} - - /// initJumpTableInfo - This callback is invoked by the JIT to allocate the - /// necessary memory to hold the jump tables. - virtual void initJumpTableInfo(MachineJumpTableInfo *MJTI) {} + virtual bool finishFunction(MachineFunction &F) = 0; /// emitJumpTableInfo - This callback is invoked to output the jump tables /// for the function. In addition to a pointer to the MachineJumpTableInfo, /// this function also takes a map of MBBs to addresses, so that the final /// addresses of the MBBs can be written to the jump tables. virtual void emitJumpTableInfo(MachineJumpTableInfo *MJTI, - std::map &MBBM) {} + std::map &MBBM) = 0; /// startFunctionStub - This callback is invoked when the JIT needs the /// address of a function that has not been code generated yet. The StubSize @@ -97,12 +87,12 @@ /// have constant pools, the can only use the other emitByte*/emitWord* /// methods. /// - virtual void startFunctionStub(unsigned StubSize) {} + virtual void startFunctionStub(unsigned StubSize) = 0; /// finishFunctionStub - This callback is invoked to terminate a function /// stub. /// - virtual void *finishFunctionStub(const Function *F) { return 0; } + virtual void *finishFunctionStub(const Function *F) = 0; /// emitByte - This callback is invoked when a byte needs to be written to the /// output stream. From lattner at cs.uiuc.edu Tue May 2 18:22:41 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 2 May 2006 18:22:41 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp Message-ID: <200605022322.SAA29022@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Alpha: AlphaCodeEmitter.cpp updated: 1.11 -> 1.12 --- Log message: Several related changes: 1. Change several methods in the MachineCodeEmitter class to be pure virtual. 2. Suck emitConstantPool/initJumpTableInfo into startFunction, removing them from the MachineCodeEmitter interface, and reducing the amount of target- specific code. 3. Change the JITEmitter so that it allocates constantpools and jump tables *right* next to the functions that they belong to, instead of in a separate pool of memory. This makes all memory for a function be contiguous, and means the JITEmitter only tracks one block of memory now. --- Diffs of the changes: (+0 -1) AlphaCodeEmitter.cpp | 1 - 1 files changed, 1 deletion(-) Index: llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp diff -u llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp:1.11 llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp:1.12 --- llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp:1.11 Tue May 2 14:14:47 2006 +++ llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp Tue May 2 18:22:24 2006 @@ -81,7 +81,6 @@ BasicBlockAddrs.clear(); MCE.startFunction(MF); - MCE.emitConstantPool(MF.getConstantPool()); for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) emitBasicBlock(*I); } while (MCE.finishFunction(MF)); From lattner at cs.uiuc.edu Tue May 2 18:22:41 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 2 May 2006 18:22:41 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/ELFWriter.cpp Message-ID: <200605022322.SAA29024@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: ELFWriter.cpp updated: 1.21 -> 1.22 --- Log message: Several related changes: 1. Change several methods in the MachineCodeEmitter class to be pure virtual. 2. Suck emitConstantPool/initJumpTableInfo into startFunction, removing them from the MachineCodeEmitter interface, and reducing the amount of target- specific code. 3. Change the JITEmitter so that it allocates constantpools and jump tables *right* next to the functions that they belong to, instead of in a separate pool of memory. This makes all memory for a function be contiguous, and means the JITEmitter only tracks one block of memory now. --- Diffs of the changes: (+6 -4) ELFWriter.cpp | 10 ++++++---- 1 files changed, 6 insertions(+), 4 deletions(-) Index: llvm/lib/CodeGen/ELFWriter.cpp diff -u llvm/lib/CodeGen/ELFWriter.cpp:1.21 llvm/lib/CodeGen/ELFWriter.cpp:1.22 --- llvm/lib/CodeGen/ELFWriter.cpp:1.21 Tue May 2 16:57:51 2006 +++ llvm/lib/CodeGen/ELFWriter.cpp Tue May 2 18:22:24 2006 @@ -58,10 +58,6 @@ void startFunction(MachineFunction &F); bool finishFunction(MachineFunction &F); - void emitConstantPool(MachineConstantPool *MCP) { - if (MCP->isEmpty()) return; - assert(0 && "unimp"); - } void addRelocation(const MachineRelocation &MR) { assert(0 && "relo not handled yet!"); } @@ -73,6 +69,12 @@ assert(0 && "JT not implementated yet!"); return 0; } + + virtual void emitJumpTableInfo(MachineJumpTableInfo *MJTI, + std::map &MBBM){ + assert(0 && "JT not implementated yet!"); + } + /// JIT SPECIFIC FUNCTIONS - DO NOT IMPLEMENT THESE HERE! void startFunctionStub(unsigned StubSize) { From lattner at cs.uiuc.edu Tue May 2 18:22:40 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 2 May 2006 18:22:40 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp Message-ID: <200605022322.SAA29014@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCCodeEmitter.cpp updated: 1.55 -> 1.56 --- Log message: Several related changes: 1. Change several methods in the MachineCodeEmitter class to be pure virtual. 2. Suck emitConstantPool/initJumpTableInfo into startFunction, removing them from the MachineCodeEmitter interface, and reducing the amount of target- specific code. 3. Change the JITEmitter so that it allocates constantpools and jump tables *right* next to the functions that they belong to, instead of in a separate pool of memory. This makes all memory for a function be contiguous, and means the JITEmitter only tracks one block of memory now. --- Diffs of the changes: (+0 -2) PPCCodeEmitter.cpp | 2 -- 1 files changed, 2 deletions(-) Index: llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp diff -u llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp:1.55 llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp:1.56 --- llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp:1.55 Tue May 2 14:14:47 2006 +++ llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp Tue May 2 18:22:24 2006 @@ -90,8 +90,6 @@ BBLocations.clear(); MCE.startFunction(MF); - MCE.emitConstantPool(MF.getConstantPool()); - MCE.initJumpTableInfo(MF.getJumpTableInfo()); for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB) emitBasicBlock(*BB); MCE.emitJumpTableInfo(MF.getJumpTableInfo(), BBLocations); From lattner at cs.uiuc.edu Tue May 2 19:13:18 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 2 May 2006 19:13:18 -0500 Subject: [llvm-commits] CVS: llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp Message-ID: <200605030013.TAA29431@zion.cs.uiuc.edu> Changes in directory llvm/lib/ExecutionEngine/JIT: JITEmitter.cpp updated: 1.89 -> 1.90 --- Log message: Simplify some code --- Diffs of the changes: (+7 -21) JITEmitter.cpp | 28 +++++++--------------------- 1 files changed, 7 insertions(+), 21 deletions(-) Index: llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp diff -u llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.89 llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.90 --- llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.89 Tue May 2 18:22:24 2006 +++ llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp Tue May 2 19:13:06 2006 @@ -565,32 +565,18 @@ if (JT.empty() || JumpTableBase == 0) return; unsigned Offset = 0; - unsigned EntrySize = MJTI->getEntrySize(); + assert(MJTI->getEntrySize() == sizeof(void*) && "Cross JIT'ing?"); // For each jump table, map each target in the jump table to the address of // an emitted MachineBasicBlock. + intptr_t *SlotPtr = (intptr_t*)JumpTableBase; + for (unsigned i = 0, e = JT.size(); i != e; ++i) { const std::vector &MBBs = JT[i].MBBs; - for (unsigned mi = 0, me = MBBs.size(); mi != me; ++mi) { - uint64_t addr = MBBM[MBBs[mi]]; - GenericValue addrgv; - const Type *Ty; - if (EntrySize == 4) { - addrgv.UIntVal = addr; - Ty = Type::UIntTy; - } else if (EntrySize == 8) { - addrgv.ULongVal = addr; - Ty = Type::ULongTy; - } else { - assert(0 && "Unhandled jump table entry size!"); - abort(); - } - // Store the address of the basic block for this jump table slot in the - // memory we allocated for the jump table in 'initJumpTableInfo' - void *ptr = (void *)((char *)JumpTableBase + Offset); - TheJIT->StoreValueToMemory(addrgv, (GenericValue *)ptr, Ty); - Offset += EntrySize; - } + // Store the address of the basic block for this jump table slot in the + // memory we allocated for the jump table in 'initJumpTableInfo' + for (unsigned mi = 0, me = MBBs.size(); mi != me; ++mi) + *SlotPtr++ = (intptr_t)MBBM[MBBs[mi]]; } } From lattner at cs.uiuc.edu Tue May 2 19:28:29 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 2 May 2006 19:28:29 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp Message-ID: <200605030028.TAA29565@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCCodeEmitter.cpp updated: 1.56 -> 1.57 --- Log message: Change the BasicBlockAddrs map to be a vector, indexed by MBB number. --- Diffs of the changes: (+9 -7) PPCCodeEmitter.cpp | 16 +++++++++------- 1 files changed, 9 insertions(+), 7 deletions(-) Index: llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp diff -u llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp:1.56 llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp:1.57 --- llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp:1.56 Tue May 2 18:22:24 2006 +++ llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp Tue May 2 19:28:15 2006 @@ -33,8 +33,8 @@ // Tracks which instruction references which BasicBlock std::vector > BBRefs; - // Tracks where each BasicBlock starts - std::map BBLocations; + // Tracks where each BasicBlock starts, indexes by BB number. + std::vector BasicBlockAddrs; /// getMachineOpValue - evaluates the MachineOperand of a given MachineInstr /// @@ -87,17 +87,17 @@ "JIT relocation model must be set to static or default!"); do { BBRefs.clear(); - BBLocations.clear(); + BasicBlockAddrs.clear(); MCE.startFunction(MF); for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB) emitBasicBlock(*BB); - MCE.emitJumpTableInfo(MF.getJumpTableInfo(), BBLocations); + MCE.emitJumpTableInfo(MF.getJumpTableInfo(), BasicBlockAddrs); } while (MCE.finishFunction(MF)); // Resolve branches to BasicBlocks for the entire function for (unsigned i = 0, e = BBRefs.size(); i != e; ++i) { - intptr_t Location = BBLocations[BBRefs[i].first]; + intptr_t Location = BasicBlockAddrs[BBRefs[i].first->getNumber()]; unsigned *Ref = BBRefs[i].second; DEBUG(std::cerr << "Fixup @ " << (void*)Ref << " to " << (void*)Location << "\n"); @@ -115,13 +115,15 @@ } } BBRefs.clear(); - BBLocations.clear(); + BasicBlockAddrs.clear(); return false; } void PPCCodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) { - BBLocations[&MBB] = MCE.getCurrentPCValue(); + if (BasicBlockAddrs.size() <= (unsigned)MBB.getNumber()) + BasicBlockAddrs.resize((MBB.getNumber()+1)*2); + BasicBlockAddrs[MBB.getNumber()] = MCE.getCurrentPCValue(); for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){ MachineInstr &MI = *I; unsigned Opcode = MI.getOpcode(); From lattner at cs.uiuc.edu Tue May 2 19:28:30 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 2 May 2006 19:28:30 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/ELFWriter.cpp Message-ID: <200605030028.TAA29569@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: ELFWriter.cpp updated: 1.22 -> 1.23 --- Log message: Change the BasicBlockAddrs map to be a vector, indexed by MBB number. --- Diffs of the changes: (+1 -1) ELFWriter.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/CodeGen/ELFWriter.cpp diff -u llvm/lib/CodeGen/ELFWriter.cpp:1.22 llvm/lib/CodeGen/ELFWriter.cpp:1.23 --- llvm/lib/CodeGen/ELFWriter.cpp:1.22 Tue May 2 18:22:24 2006 +++ llvm/lib/CodeGen/ELFWriter.cpp Tue May 2 19:28:15 2006 @@ -71,7 +71,7 @@ } virtual void emitJumpTableInfo(MachineJumpTableInfo *MJTI, - std::map &MBBM){ + std::vector &MBBM) { assert(0 && "JT not implementated yet!"); } From lattner at cs.uiuc.edu Tue May 2 19:28:30 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 2 May 2006 19:28:30 -0500 Subject: [llvm-commits] CVS: llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp Message-ID: <200605030028.TAA29573@zion.cs.uiuc.edu> Changes in directory llvm/lib/ExecutionEngine/JIT: JITEmitter.cpp updated: 1.90 -> 1.91 --- Log message: Change the BasicBlockAddrs map to be a vector, indexed by MBB number. --- Diffs of the changes: (+3 -3) JITEmitter.cpp | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) Index: llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp diff -u llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.90 llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.91 --- llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.90 Tue May 2 19:13:06 2006 +++ llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp Tue May 2 19:28:15 2006 @@ -392,7 +392,7 @@ void emitConstantPool(MachineConstantPool *MCP); void initJumpTableInfo(MachineJumpTableInfo *MJTI); virtual void emitJumpTableInfo(MachineJumpTableInfo *MJTI, - std::map &MBBM); + std::vector &MBBM); virtual void startFunctionStub(unsigned StubSize); virtual void* finishFunctionStub(const Function *F); @@ -560,7 +560,7 @@ } void JITEmitter::emitJumpTableInfo(MachineJumpTableInfo *MJTI, - std::map &MBBM){ + std::vector &MBBM) { const std::vector &JT = MJTI->getJumpTables(); if (JT.empty() || JumpTableBase == 0) return; @@ -576,7 +576,7 @@ // Store the address of the basic block for this jump table slot in the // memory we allocated for the jump table in 'initJumpTableInfo' for (unsigned mi = 0, me = MBBs.size(); mi != me; ++mi) - *SlotPtr++ = (intptr_t)MBBM[MBBs[mi]]; + *SlotPtr++ = (intptr_t)MBBM[MBBs[mi]->getNumber()]; } } From lattner at cs.uiuc.edu Tue May 2 19:28:30 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 2 May 2006 19:28:30 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86CodeEmitter.cpp Message-ID: <200605030028.TAA29577@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86CodeEmitter.cpp updated: 1.98 -> 1.99 --- Log message: Change the BasicBlockAddrs map to be a vector, indexed by MBB number. --- Diffs of the changes: (+8 -7) X86CodeEmitter.cpp | 15 ++++++++------- 1 files changed, 8 insertions(+), 7 deletions(-) Index: llvm/lib/Target/X86/X86CodeEmitter.cpp diff -u llvm/lib/Target/X86/X86CodeEmitter.cpp:1.98 llvm/lib/Target/X86/X86CodeEmitter.cpp:1.99 --- llvm/lib/Target/X86/X86CodeEmitter.cpp:1.98 Tue May 2 18:22:24 2006 +++ llvm/lib/Target/X86/X86CodeEmitter.cpp Tue May 2 19:28:15 2006 @@ -35,7 +35,7 @@ class Emitter : public MachineFunctionPass { const X86InstrInfo *II; MachineCodeEmitter &MCE; - std::map BasicBlockAddrs; + std::vector BasicBlockAddrs; std::vector > BBRefs; public: explicit Emitter(MachineCodeEmitter &mce) : II(0), MCE(mce) {} @@ -93,7 +93,7 @@ // Resolve all forward branches now. for (unsigned i = 0, e = BBRefs.size(); i != e; ++i) { - unsigned Location = BasicBlockAddrs[BBRefs[i].first]; + unsigned Location = BasicBlockAddrs[BBRefs[i].first->getNumber()]; unsigned Ref = BBRefs[i].second; *((unsigned*)(intptr_t)Ref) = Location-Ref-4; } @@ -103,8 +103,9 @@ } void Emitter::emitBasicBlock(MachineBasicBlock &MBB) { - if (uint64_t Addr = MCE.getCurrentPCValue()) - BasicBlockAddrs[&MBB] = Addr; + if (BasicBlockAddrs.size() <= (unsigned)MBB.getNumber()) + BasicBlockAddrs.resize((MBB.getNumber()+1)*2); + BasicBlockAddrs[MBB.getNumber()] = MCE.getCurrentPCValue(); for (MachineBasicBlock::const_iterator I = MBB.begin(), E = MBB.end(); I != E; ++I) @@ -125,9 +126,9 @@ void Emitter::emitPCRelativeBlockAddress(MachineBasicBlock *MBB) { // If this is a backwards branch, we already know the address of the target, // so just emit the value. - std::map::iterator I = BasicBlockAddrs.find(MBB); - if (I != BasicBlockAddrs.end()) { - emitPCRelativeValue(I->second); + unsigned MBBNo = MBB->getNumber(); + if (MBBNo < BasicBlockAddrs.size() && BasicBlockAddrs[MBBNo]) { + emitPCRelativeValue(BasicBlockAddrs[MBBNo]); } else { // Otherwise, remember where this reference was and where it is to so we can // deal with it later. From jeffc at jolt-lang.org Tue May 2 19:29:02 2006 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Tue, 2 May 2006 19:29:02 -0500 Subject: [llvm-commits] CVS: llvm/win32/CodeGen/CodeGen.vcproj Message-ID: <200605030029.TAA29594@zion.cs.uiuc.edu> Changes in directory llvm/win32/CodeGen: CodeGen.vcproj updated: 1.23 -> 1.24 --- Log message: Keep Visual Studio happy. --- Diffs of the changes: (+0 -3) CodeGen.vcproj | 3 --- 1 files changed, 3 deletions(-) Index: llvm/win32/CodeGen/CodeGen.vcproj diff -u llvm/win32/CodeGen/CodeGen.vcproj:1.23 llvm/win32/CodeGen/CodeGen.vcproj:1.24 --- llvm/win32/CodeGen/CodeGen.vcproj:1.23 Sat Apr 22 23:37:08 2006 +++ llvm/win32/CodeGen/CodeGen.vcproj Tue May 2 19:28:50 2006 @@ -136,9 +136,6 @@ RelativePath="..\..\lib\CodeGen\MachineBasicBlock.cpp"> - - Changes in directory llvm/lib/Target/Alpha: AlphaCodeEmitter.cpp updated: 1.12 -> 1.13 --- Log message: Keep the alpha JIT similar to the PPC/X86 jits --- Diffs of the changes: (+6 -4) AlphaCodeEmitter.cpp | 10 ++++++---- 1 files changed, 6 insertions(+), 4 deletions(-) Index: llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp diff -u llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp:1.12 llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp:1.13 --- llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp:1.12 Tue May 2 18:22:24 2006 +++ llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp Tue May 2 19:31:21 2006 @@ -35,7 +35,7 @@ class AlphaCodeEmitter : public MachineFunctionPass { const AlphaInstrInfo *II; MachineCodeEmitter &MCE; - std::map BasicBlockAddrs; + std::vector BasicBlockAddrs; std::vector > BBRefs; /// getMachineOpValue - evaluates the MachineOperand of a given MachineInstr @@ -87,7 +87,7 @@ // Resolve all forward branches now... for (unsigned i = 0, e = BBRefs.size(); i != e; ++i) { - unsigned* Location = (unsigned*)BasicBlockAddrs[BBRefs[i].first]; + unsigned* Location = BasicBlockAddrs[BBRefs[i].first->getNumber()]; unsigned* Ref = (unsigned*)BBRefs[i].second; intptr_t BranchTargetDisp = (((unsigned char*)Location - (unsigned char*)Ref) >> 2) - 1; @@ -103,8 +103,10 @@ } void AlphaCodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) { - uintptr_t Addr = MCE.getCurrentPCValue(); - BasicBlockAddrs[&MBB] = (unsigned*)Addr; + if (BasicBlockAddrs.size() <= (unsigned)MBB.getNumber()) + BasicBlockAddrs.resize((MBB.getNumber()+1)*2); + + BasicBlockAddrs[MBB.getNumber()] = (unsigned*)MCE.getCurrentPCValue(); for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I) { From lattner at cs.uiuc.edu Tue May 2 19:33:07 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 2 May 2006 19:33:07 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineCodeEmitter.h Message-ID: <200605030033.TAA29707@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineCodeEmitter.h updated: 1.37 -> 1.38 --- Log message: Change the BasicBlockAddrs map to be a vector, indexed by MBB number. --- Diffs of the changes: (+3 -3) MachineCodeEmitter.h | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) Index: llvm/include/llvm/CodeGen/MachineCodeEmitter.h diff -u llvm/include/llvm/CodeGen/MachineCodeEmitter.h:1.37 llvm/include/llvm/CodeGen/MachineCodeEmitter.h:1.38 --- llvm/include/llvm/CodeGen/MachineCodeEmitter.h:1.37 Tue May 2 18:22:24 2006 +++ llvm/include/llvm/CodeGen/MachineCodeEmitter.h Tue May 2 19:32:55 2006 @@ -18,7 +18,7 @@ #define LLVM_CODEGEN_MACHINECODEEMITTER_H #include "llvm/Support/DataTypes.h" -#include +#include namespace llvm { @@ -76,10 +76,10 @@ /// emitJumpTableInfo - This callback is invoked to output the jump tables /// for the function. In addition to a pointer to the MachineJumpTableInfo, - /// this function also takes a map of MBBs to addresses, so that the final + /// this function also takes a map of MBB IDs to addresses, so that the final /// addresses of the MBBs can be written to the jump tables. virtual void emitJumpTableInfo(MachineJumpTableInfo *MJTI, - std::map &MBBM) = 0; + std::vector &MBBM) = 0; /// startFunctionStub - This callback is invoked when the JIT needs the /// address of a function that has not been code generated yet. The StubSize From lattner at cs.uiuc.edu Tue May 2 19:48:34 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 2 May 2006 19:48:34 -0500 Subject: [llvm-commits] CVS: llvm/lib/VMCore/Instructions.cpp Message-ID: <200605030048.TAA29830@zion.cs.uiuc.edu> Changes in directory llvm/lib/VMCore: Instructions.cpp updated: 1.35 -> 1.36 --- Log message: Add assertions that verify that the actual arguments to a call or invoke match the prototype of the called function. --- Diffs of the changes: (+22 -4) Instructions.cpp | 26 ++++++++++++++++++++++---- 1 files changed, 22 insertions(+), 4 deletions(-) Index: llvm/lib/VMCore/Instructions.cpp diff -u llvm/lib/VMCore/Instructions.cpp:1.35 llvm/lib/VMCore/Instructions.cpp:1.36 --- llvm/lib/VMCore/Instructions.cpp:1.35 Fri Apr 14 17:20:32 2006 +++ llvm/lib/VMCore/Instructions.cpp Tue May 2 19:48:22 2006 @@ -197,9 +197,13 @@ assert((Params.size() == FTy->getNumParams() || (FTy->isVarArg() && Params.size() > FTy->getNumParams())) && - "Calling a function with bad signature"); - for (unsigned i = 0, e = Params.size(); i != e; ++i) + "Calling a function with bad signature!"); + for (unsigned i = 0, e = Params.size(); i != e; ++i) { + assert((i >= FTy->getNumParams() || + FTy->getParamType(i) == Params[i]->getType()) && + "Calling a function with a bad signature!"); OL[i+1].init(Params[i], this); + } } void CallInst::init(Value *Func, Value *Actual1, Value *Actual2) { @@ -213,8 +217,14 @@ cast(cast(Func->getType())->getElementType()); assert((FTy->getNumParams() == 2 || - (FTy->isVarArg() && FTy->getNumParams() == 0)) && + (FTy->isVarArg() && FTy->getNumParams() < 2)) && "Calling a function with bad signature"); + assert((0 >= FTy->getNumParams() || + FTy->getParamType(0) == Actual1->getType()) && + "Calling a function with a bad signature!"); + assert((1 >= FTy->getNumParams() || + FTy->getParamType(1) == Actual2->getType()) && + "Calling a function with a bad signature!"); } void CallInst::init(Value *Func, Value *Actual) { @@ -229,6 +239,9 @@ assert((FTy->getNumParams() == 1 || (FTy->isVarArg() && FTy->getNumParams() == 0)) && "Calling a function with bad signature"); + assert((0 == FTy->getNumParams() || + FTy->getParamType(0) == Actual->getType()) && + "Calling a function with a bad signature!"); } void CallInst::init(Value *Func) { @@ -339,8 +352,13 @@ (FTy->isVarArg() && Params.size() > FTy->getNumParams()) && "Calling a function with bad signature"); - for (unsigned i = 0, e = Params.size(); i != e; i++) + for (unsigned i = 0, e = Params.size(); i != e; i++) { + assert((i >= FTy->getNumParams() || + FTy->getParamType(i) == Params[i]->getType()) && + "Invoking a function with a bad signature!"); + OL[i+3].init(Params[i], this); + } } InvokeInst::InvokeInst(Value *Fn, BasicBlock *IfNormal, From lattner at cs.uiuc.edu Tue May 2 19:55:01 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 2 May 2006 19:55:01 -0500 Subject: [llvm-commits] CVS: llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp Message-ID: <200605030055.TAA29917@zion.cs.uiuc.edu> Changes in directory llvm/lib/ExecutionEngine/JIT: JITEmitter.cpp updated: 1.91 -> 1.92 --- Log message: Simplify some code. Don't add memory blocks to the Blocks list twice. --- Diffs of the changes: (+8 -16) JITEmitter.cpp | 24 ++++++++---------------- 1 files changed, 8 insertions(+), 16 deletions(-) Index: llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp diff -u llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.91 llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.92 --- llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.91 Tue May 2 19:28:15 2006 +++ llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp Tue May 2 19:54:49 2006 @@ -30,7 +30,6 @@ #include "llvm/System/Memory.h" #include #include -#include using namespace llvm; namespace { @@ -52,7 +51,7 @@ /// are emitting is. This never bothers to release the memory, because when /// we are ready to destroy the JIT, the program exits. class JITMemoryManager { - std::list Blocks; // List of blocks allocated by the JIT + std::vector Blocks; // Memory blocks allocated by the JIT unsigned char *FunctionBase; // Start of the function body area unsigned char *CurStubPtr, *CurFunctionPtr; unsigned char *GOTBase; // Target Specific reserved memory @@ -80,8 +79,6 @@ // Allocate a 16M block of memory for functions sys::MemoryBlock FunBlock = getNewMemoryBlock(16 << 20); - Blocks.push_front(FunBlock); - FunctionBase = reinterpret_cast(FunBlock.base()); // Allocate stubs backwards from the base, allocate functions forward @@ -94,9 +91,8 @@ } JITMemoryManager::~JITMemoryManager() { - for (std::list::iterator ib = Blocks.begin(), - ie = Blocks.end(); ib != ie; ++ib) - sys::Memory::ReleaseRWX(*ib); + for (unsigned i = 0, e = Blocks.size(); i != e; ++i) + sys::Memory::ReleaseRWX(Blocks[i]); Blocks.clear(); } @@ -122,20 +118,16 @@ } sys::MemoryBlock JITMemoryManager::getNewMemoryBlock(unsigned size) { - const sys::MemoryBlock* BOld = 0; - if (Blocks.size()) - BOld = &Blocks.front(); - //never allocate less than 1 MB - sys::MemoryBlock B; try { - B = sys::Memory::AllocateRWX(std::max(((unsigned)1 << 20), size), BOld); - } catch (std::string& err) { + const sys::MemoryBlock *BOld = Blocks.empty() ? 0 : &Blocks.front(); + sys::MemoryBlock B = sys::Memory::AllocateRWX(size, BOld); + Blocks.push_back(B); + return B; + } catch (std::string &err) { std::cerr << "Allocation failed when allocating new memory in the JIT\n"; std::cerr << err << "\n"; abort(); } - Blocks.push_front(B); - return B; } //===----------------------------------------------------------------------===// From lattner at cs.uiuc.edu Tue May 2 20:02:03 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 2 May 2006 20:02:03 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineCodeEmitter.h Message-ID: <200605030102.UAA30040@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineCodeEmitter.h updated: 1.38 -> 1.39 --- Log message: Add a new emitAlignment method --- Diffs of the changes: (+12 -4) MachineCodeEmitter.h | 16 ++++++++++++---- 1 files changed, 12 insertions(+), 4 deletions(-) Index: llvm/include/llvm/CodeGen/MachineCodeEmitter.h diff -u llvm/include/llvm/CodeGen/MachineCodeEmitter.h:1.38 llvm/include/llvm/CodeGen/MachineCodeEmitter.h:1.39 --- llvm/include/llvm/CodeGen/MachineCodeEmitter.h:1.38 Tue May 2 19:32:55 2006 +++ llvm/include/llvm/CodeGen/MachineCodeEmitter.h Tue May 2 20:01:51 2006 @@ -130,14 +130,22 @@ } } - /// allocateSpace - Allocate a block of space in the current output buffer, - /// returning null (and setting conditions to indicate buffer overflow) on - /// failure. Alignment is the alignment in bytes of the buffer desired. - void *allocateSpace(intptr_t Size, unsigned Alignment) { + /// emitAlignment - Move the CurBufferPtr pointer up the the specified + /// alignment (saturated to BufferEnd of course). + void emitAlignment(unsigned Alignment) { if (Alignment == 0) Alignment = 1; // Move the current buffer ptr up to the specified alignment. CurBufferPtr = (unsigned char*)(((intptr_t)CurBufferPtr+Alignment-1) & ~(Alignment-1)); + if (CurBufferPtr > BufferEnd) + CurBufferPtr = BufferEnd; + } + + /// allocateSpace - Allocate a block of space in the current output buffer, + /// returning null (and setting conditions to indicate buffer overflow) on + /// failure. Alignment is the alignment in bytes of the buffer desired. + void *allocateSpace(intptr_t Size, unsigned Alignment) { + emitAlignment(Alignment); void *Result = CurBufferPtr; // Allocate the space. From lattner at cs.uiuc.edu Tue May 2 20:03:32 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 2 May 2006 20:03:32 -0500 Subject: [llvm-commits] CVS: llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp Message-ID: <200605030103.UAA30102@zion.cs.uiuc.edu> Changes in directory llvm/lib/ExecutionEngine/JIT: JITEmitter.cpp updated: 1.92 -> 1.93 --- Log message: Align function bodies correctly. --- Diffs of the changes: (+2 -4) JITEmitter.cpp | 6 ++---- 1 files changed, 2 insertions(+), 4 deletions(-) Index: llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp diff -u llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.92 llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.93 --- llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.92 Tue May 2 19:54:49 2006 +++ llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp Tue May 2 20:03:20 2006 @@ -107,9 +107,7 @@ } unsigned char *JITMemoryManager::startFunctionBody() { - // Round up to an even multiple of 8 bytes, this should eventually be target - // specific. - return (unsigned char*)(((intptr_t)CurFunctionPtr + 7) & ~7); + return CurFunctionPtr; } void JITMemoryManager::endFunctionBody(unsigned char *FunctionEnd) { @@ -447,7 +445,7 @@ initJumpTableInfo(F.getJumpTableInfo()); // About to start emitting the machine code for the function. - // FIXME: align it? + emitAlignment(std::max(F.getFunction()->getAlignment(), 8U)); TheJIT->updateGlobalMapping(F.getFunction(), CurBufferPtr); } From evan.cheng at apple.com Tue May 2 21:08:45 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 2 May 2006 21:08:45 -0500 Subject: [llvm-commits] CVS: llvm/utils/TableGen/InstrInfoEmitter.cpp Message-ID: <200605030208.VAA30705@zion.cs.uiuc.edu> Changes in directory llvm/utils/TableGen: InstrInfoEmitter.cpp updated: 1.39 -> 1.40 --- Log message: Set isStore of instructions with ISD::TRUNCSTORE root node. --- Diffs of the changes: (+5 -3) InstrInfoEmitter.cpp | 8 +++++--- 1 files changed, 5 insertions(+), 3 deletions(-) Index: llvm/utils/TableGen/InstrInfoEmitter.cpp diff -u llvm/utils/TableGen/InstrInfoEmitter.cpp:1.39 llvm/utils/TableGen/InstrInfoEmitter.cpp:1.40 --- llvm/utils/TableGen/InstrInfoEmitter.cpp:1.39 Mon May 1 18:46:16 2006 +++ llvm/utils/TableGen/InstrInfoEmitter.cpp Tue May 2 21:08:34 2006 @@ -201,9 +201,11 @@ DefInit *OpDef = dynamic_cast(Dag->getOperator()); if (OpDef) { Record *Operator = OpDef->getDef(); - if (Operator->isSubClassOf("SDNode") && - Operator->getValueAsString("Opcode") == "ISD::STORE") - isStore = true; + if (Operator->isSubClassOf("SDNode")) { + const std::string Opcode = Operator->getValueAsString("Opcode"); + if (Opcode == "ISD::STORE" || Opcode == "ISD::TRUNCSTORE") + isStore = true; + } } } } From evan.cheng at apple.com Tue May 2 21:10:57 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 2 May 2006 21:10:57 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Message-ID: <200605030210.VAA30731@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: ScheduleDAGList.cpp updated: 1.52 -> 1.53 --- Log message: Bottom up register pressure reduction work: clean up some hacks and enhanced the heuristic to further reduce spills for several test cases. (Note, it may not necessarily translate to runtime win!) --- Diffs of the changes: (+72 -75) ScheduleDAGList.cpp | 147 +++++++++++++++++++++++++--------------------------- 1 files changed, 72 insertions(+), 75 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.52 llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.53 --- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.52 Mon May 1 04:20:44 2006 +++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Tue May 2 21:10:45 2006 @@ -33,13 +33,6 @@ using namespace llvm; namespace { - // TEMPORARY option to test a fix. - cl::opt - SchedIgnorStore("sched-ignore-store", cl::Hidden); - -} - -namespace { Statistic<> NumNoops ("scheduler", "Number of noops inserted"); Statistic<> NumStalls("scheduler", "Number of pipeline stalls"); @@ -58,7 +51,6 @@ short NumSuccsLeft; // # of succs not scheduled. short NumChainPredsLeft; // # of chain preds not scheduled. short NumChainSuccsLeft; // # of chain succs not scheduled. - bool isStore : 1; // Is a store. bool isTwoAddress : 1; // Is a two-address instruction. bool isDefNUseOperand : 1; // Is a def&use operand. bool isPending : 1; // True once pending. @@ -71,9 +63,9 @@ SUnit(SDNode *node, unsigned nodenum) : Node(node), NumPredsLeft(0), NumSuccsLeft(0), - NumChainPredsLeft(0), NumChainSuccsLeft(0), isStore(false), - isTwoAddress(false), isDefNUseOperand(false), - isPending(false), isAvailable(false), isScheduled(false), + NumChainPredsLeft(0), NumChainSuccsLeft(0), + isTwoAddress(false), isDefNUseOperand(false), isPending(false), + isAvailable(false), isScheduled(false), Latency(0), CycleBound(0), Cycle(0), NodeNum(nodenum) {} void dump(const SelectionDAG *G) const; @@ -82,7 +74,7 @@ } void SUnit::dump(const SelectionDAG *G) const { - std::cerr << "SU: "; + std::cerr << "SU(" << NodeNum << "): "; Node->dump(G); std::cerr << "\n"; if (FlaggedNodes.size() != 0) { @@ -325,11 +317,13 @@ if (MainNode->isTargetOpcode()) { unsigned Opc = MainNode->getTargetOpcode(); - if (TII->isTwoAddrInstr(Opc)) + if (TII->isTwoAddrInstr(Opc)) { SU->isTwoAddress = true; - if (TII->isStore(Opc)) - if (!SchedIgnorStore) - SU->isStore = true; + SDNode *OpN = MainNode->getOperand(0).Val; + SUnit *OpSU = SUnitMap[OpN]; + if (OpSU) + OpSU->isDefNUseOperand = true; + } } // Find all predecessors and successors of the group. @@ -345,7 +339,7 @@ SUnit *OpSU = SUnitMap[OpN]; assert(OpSU && "Node has no SUnit!"); if (OpSU == SU) continue; // In the same group. - + MVT::ValueType OpVT = N->getOperand(i).getValueType(); assert(OpVT != MVT::Flag && "Flagged nodes should be in same sunit!"); bool isChain = OpVT == MVT::Other; @@ -470,6 +464,7 @@ DEBUG(SU->dump(&DAG)); SU->Cycle = CurCycle; + AvailableQueue->ScheduledNode(SU); Sequence.push_back(SU); // Bottom up: release predecessors @@ -480,6 +475,8 @@ // calculate directly. if (!I->second) SU->NumPredsLeft--; + else + SU->NumChainPredsLeft--; } } @@ -499,9 +496,9 @@ // While Available queue is not empty, grab the node with the highest // priority. If it is not ready put it back. Schedule the node. std::vector NotReady; + SUnit *CurrNode = NULL; while (!AvailableQueue->empty()) { SUnit *CurrNode = AvailableQueue->pop(); - while (!isReady(CurrNode, CurrCycle)) { NotReady.push_back(CurrNode); CurrNode = AvailableQueue->pop(); @@ -514,7 +511,6 @@ ScheduleNodeBottomUp(CurrNode, CurrCycle); CurrCycle++; CurrNode->isScheduled = true; - AvailableQueue->ScheduledNode(CurrNode); } // Add entry node last @@ -748,12 +744,12 @@ const std::vector *SUnits; // SethiUllmanNumbers - The SethiUllman number for each node. - std::vector SethiUllmanNumbers; + std::vector SethiUllmanNumbers; std::priority_queue, ls_rr_sort> Queue; public: - RegReductionPriorityQueue() : Queue(ls_rr_sort(this)) { - } + RegReductionPriorityQueue() : + Queue(ls_rr_sort(this)) {} void initNodes(const std::vector &sunits) { SUnits = &sunits; @@ -765,7 +761,7 @@ SethiUllmanNumbers.clear(); } - unsigned getSethiUllmanNumber(unsigned NodeNum) const { + int getSethiUllmanNumber(unsigned NodeNum) const { assert(NodeNum < SethiUllmanNumbers.size()); return SethiUllmanNumbers[NodeNum]; } @@ -785,88 +781,89 @@ Queue.pop(); return V; } + private: void CalculatePriorities(); - unsigned CalcNodePriority(const SUnit *SU); + int CalcNodePriority(const SUnit *SU); }; } bool ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const { unsigned LeftNum = left->NodeNum; unsigned RightNum = right->NodeNum; - - int LBonus = (int)left ->isDefNUseOperand; - int RBonus = (int)right->isDefNUseOperand; - - // Special tie breaker: if two nodes share a operand, the one that - // use it as a def&use operand is preferred. - if (left->isTwoAddress && !right->isTwoAddress) { - SDNode *DUNode = left->Node->getOperand(0).Val; - if (DUNode->isOperand(right->Node)) - LBonus++; - } - if (!left->isTwoAddress && right->isTwoAddress) { - SDNode *DUNode = right->Node->getOperand(0).Val; - if (DUNode->isOperand(left->Node)) - RBonus++; + bool LIsTarget = left->Node->isTargetOpcode(); + bool RIsTarget = right->Node->isTargetOpcode(); + int LPriority = SPQ->getSethiUllmanNumber(LeftNum); + int RPriority = SPQ->getSethiUllmanNumber(RightNum); + bool LIsFloater = LIsTarget && (LPriority == 1 || LPriority == 0); + bool RIsFloater = RIsTarget && (RPriority == 1 || RPriority == 0); + + // Schedule floaters (e.g. load from some constant address) and immediate use + // of floaters (with no other operands) just before the use. + if (LIsFloater && !RIsFloater) + LPriority += 2; + else if (!LIsFloater && RIsFloater) + RPriority += 2; + + // Special tie breaker: if two nodes share a operand, the one that use it + // as a def&use operand is preferred. + if (LIsTarget && RIsTarget) { + if (left->isTwoAddress && !right->isTwoAddress) { + SDNode *DUNode = left->Node->getOperand(0).Val; + if (DUNode->isOperand(right->Node)) + LPriority += 2; + } + if (!left->isTwoAddress && right->isTwoAddress) { + SDNode *DUNode = right->Node->getOperand(0).Val; + if (DUNode->isOperand(left->Node)) + RPriority += 2; + } } - - // Push stores up as much as possible. This really help code like this: - // load - // compute - // store - // load - // compute - // store - // This would make sure the scheduled code completed all computations and - // the stores before the next series of computation starts. - if (!left->isStore && right->isStore) - LBonus += 4; - if (left->isStore && !right->isStore) - RBonus += 4; - - // Priority1 is just the number of live range genned. - int LPriority1 = left ->NumPredsLeft - LBonus; - int RPriority1 = right->NumPredsLeft - RBonus; - int LPriority2 = SPQ->getSethiUllmanNumber(LeftNum) + LBonus; - int RPriority2 = SPQ->getSethiUllmanNumber(RightNum) + RBonus; - - if (LPriority1 > RPriority1) + + if (LPriority < RPriority) return true; - else if (LPriority1 == RPriority1) - if (LPriority2 < RPriority2) + else if (LPriority == RPriority) + if (left->NumPredsLeft > right->NumPredsLeft) return true; - else if (LPriority2 == RPriority2) + else if (left->NumPredsLeft == right->NumPredsLeft) if (left->CycleBound > right->CycleBound) return true; - return false; } /// CalcNodePriority - Priority is the Sethi Ullman number. /// Smaller number is the higher priority. -unsigned RegReductionPriorityQueue::CalcNodePriority(const SUnit *SU) { - unsigned &SethiUllmanNumber = SethiUllmanNumbers[SU->NodeNum]; +int RegReductionPriorityQueue::CalcNodePriority(const SUnit *SU) { + int &SethiUllmanNumber = SethiUllmanNumbers[SU->NodeNum]; if (SethiUllmanNumber != 0) return SethiUllmanNumber; - - if (SU->Preds.size() == 0) { + + unsigned Opc = SU->Node->getOpcode(); + if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg) + SethiUllmanNumber = INT_MAX - 10; + else if (SU->NumSuccsLeft == 0) + // If SU does not have a use, i.e. it doesn't produce a value that would + // be consumed (e.g. store), then it terminates a chain of computation. + // Give it a small SethiUllman number so it will be scheduled right before its + // predecessors that it doesn't lengthen their live ranges. + SethiUllmanNumber = INT_MIN + 10; + else if (SU->NumPredsLeft == 0 && Opc != ISD::CopyFromReg) SethiUllmanNumber = 1; - } else { + else { int Extra = 0; for (std::set >::const_iterator I = SU->Preds.begin(), E = SU->Preds.end(); I != E; ++I) { - if (I->second) continue; // ignore chain preds. + if (I->second) continue; // ignore chain preds SUnit *PredSU = I->first; - unsigned PredSethiUllman = CalcNodePriority(PredSU); + int PredSethiUllman = CalcNodePriority(PredSU); if (PredSethiUllman > SethiUllmanNumber) { SethiUllmanNumber = PredSethiUllman; Extra = 0; - } else if (PredSethiUllman == SethiUllmanNumber) + } else if (PredSethiUllman == SethiUllmanNumber && !I->second) Extra++; } - + SethiUllmanNumber += Extra; } @@ -964,7 +961,7 @@ // single predecessor has a higher priority, since scheduling it will make // the node available. void ScheduledNode(SUnit *Node); - + private: void CalculatePriorities(); int CalcLatency(const SUnit &SU); From evan.cheng at apple.com Tue May 2 21:11:48 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 2 May 2006 21:11:48 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/X86/2006-05-01-SchedCausingSpills.ll 2006-05-02-InstrSched1.ll 2006-05-02-InstrSched2.ll Message-ID: <200605030211.VAA30751@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/X86: 2006-05-01-SchedCausingSpills.ll added (r1.1) 2006-05-02-InstrSched1.ll added (r1.1) 2006-05-02-InstrSched2.ll added (r1.1) --- Log message: A few instruction scheduling test cases. --- Diffs of the changes: (+117 -0) 2006-05-01-SchedCausingSpills.ll | 73 +++++++++++++++++++++++++++++++++++++++ 2006-05-02-InstrSched1.ll | 20 ++++++++++ 2006-05-02-InstrSched2.ll | 24 ++++++++++++ 3 files changed, 117 insertions(+) Index: llvm/test/Regression/CodeGen/X86/2006-05-01-SchedCausingSpills.ll diff -c /dev/null llvm/test/Regression/CodeGen/X86/2006-05-01-SchedCausingSpills.ll:1.1 *** /dev/null Tue May 2 21:11:46 2006 --- llvm/test/Regression/CodeGen/X86/2006-05-01-SchedCausingSpills.ll Tue May 2 21:11:36 2006 *************** *** 0 **** --- 1,73 ---- + ; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah -stats 2>&1 | not grep 'Number of register spills' + + int %foo(<4 x float>* %a, <4 x float>* %b, <4 x float>* %c, <4 x float>* %d) { + %tmp44 = load <4 x float>* %a ; <<4 x float>> [#uses=9] + %tmp46 = load <4 x float>* %b ; <<4 x float>> [#uses=1] + %tmp48 = load <4 x float>* %c ; <<4 x float>> [#uses=1] + %tmp50 = load <4 x float>* %d ; <<4 x float>> [#uses=1] + %tmp51 = cast <4 x float> %tmp44 to <4 x int> ; <<4 x int>> [#uses=1] + %tmp = shufflevector <4 x int> %tmp51, <4 x int> undef, <4 x uint> < uint 3, uint 3, uint 3, uint 3 > ; <<4 x int>> [#uses=2] + %tmp52 = cast <4 x int> %tmp to <4 x float> ; <<4 x float>> [#uses=1] + %tmp60 = xor <4 x int> %tmp, < int -2147483648, int -2147483648, int -2147483648, int -2147483648 > ; <<4 x int>> [#uses=1] + %tmp61 = cast <4 x int> %tmp60 to <4 x float> ; <<4 x float>> [#uses=1] + %tmp74 = tail call <4 x float> %llvm.x86.sse.cmp.ps( <4 x float> %tmp52, <4 x float> %tmp44, sbyte 1 ) ; <<4 x float>> [#uses=1] + %tmp75 = cast <4 x float> %tmp74 to <4 x int> ; <<4 x int>> [#uses=1] + %tmp88 = tail call <4 x float> %llvm.x86.sse.cmp.ps( <4 x float> %tmp44, <4 x float> %tmp61, sbyte 1 ) ; <<4 x float>> [#uses=1] + %tmp89 = cast <4 x float> %tmp88 to <4 x int> ; <<4 x int>> [#uses=1] + %tmp98 = tail call <4 x int> %llvm.x86.sse2.packssdw.128( <4 x int> %tmp75, <4 x int> %tmp89 ) ; <<4 x int>> [#uses=1] + %tmp102 = cast <4 x int> %tmp98 to <8 x short> ; <<8 x short>> [#uses=1] + %tmp = shufflevector <8 x short> %tmp102, <8 x short> undef, <8 x uint> < uint 0, uint 1, uint 2, uint 3, uint 6, uint 5, uint 4, uint 7 > ; <<8 x short>> [#uses=1] + %tmp105 = shufflevector <8 x short> %tmp, <8 x short> undef, <8 x uint> < uint 2, uint 1, uint 0, uint 3, uint 4, uint 5, uint 6, uint 7 > ; <<8 x short>> [#uses=1] + %tmp105 = cast <8 x short> %tmp105 to <4 x float> ; <<4 x float>> [#uses=1] + store <4 x float> %tmp105, <4 x float>* %a + %tmp108 = cast <4 x float> %tmp46 to <4 x int> ; <<4 x int>> [#uses=1] + %tmp109 = shufflevector <4 x int> %tmp108, <4 x int> undef, <4 x uint> < uint 3, uint 3, uint 3, uint 3 > ; <<4 x int>> [#uses=2] + %tmp109 = cast <4 x int> %tmp109 to <4 x float> ; <<4 x float>> [#uses=1] + %tmp119 = xor <4 x int> %tmp109, < int -2147483648, int -2147483648, int -2147483648, int -2147483648 > ; <<4 x int>> [#uses=1] + %tmp120 = cast <4 x int> %tmp119 to <4 x float> ; <<4 x float>> [#uses=1] + %tmp133 = tail call <4 x float> %llvm.x86.sse.cmp.ps( <4 x float> %tmp109, <4 x float> %tmp44, sbyte 1 ) ; <<4 x float>> [#uses=1] + %tmp134 = cast <4 x float> %tmp133 to <4 x int> ; <<4 x int>> [#uses=1] + %tmp147 = tail call <4 x float> %llvm.x86.sse.cmp.ps( <4 x float> %tmp44, <4 x float> %tmp120, sbyte 1 ) ; <<4 x float>> [#uses=1] + %tmp148 = cast <4 x float> %tmp147 to <4 x int> ; <<4 x int>> [#uses=1] + %tmp159 = tail call <4 x int> %llvm.x86.sse2.packssdw.128( <4 x int> %tmp134, <4 x int> %tmp148 ) ; <<4 x int>> [#uses=1] + %tmp163 = cast <4 x int> %tmp159 to <8 x short> ; <<8 x short>> [#uses=1] + %tmp164 = shufflevector <8 x short> %tmp163, <8 x short> undef, <8 x uint> < uint 0, uint 1, uint 2, uint 3, uint 6, uint 5, uint 4, uint 7 > ; <<8 x short>> [#uses=1] + %tmp166 = shufflevector <8 x short> %tmp164, <8 x short> undef, <8 x uint> < uint 2, uint 1, uint 0, uint 3, uint 4, uint 5, uint 6, uint 7 > ; <<8 x short>> [#uses=1] + %tmp166 = cast <8 x short> %tmp166 to <4 x float> ; <<4 x float>> [#uses=1] + store <4 x float> %tmp166, <4 x float>* %b + %tmp169 = cast <4 x float> %tmp48 to <4 x int> ; <<4 x int>> [#uses=1] + %tmp170 = shufflevector <4 x int> %tmp169, <4 x int> undef, <4 x uint> < uint 3, uint 3, uint 3, uint 3 > ; <<4 x int>> [#uses=2] + %tmp170 = cast <4 x int> %tmp170 to <4 x float> ; <<4 x float>> [#uses=1] + %tmp180 = xor <4 x int> %tmp170, < int -2147483648, int -2147483648, int -2147483648, int -2147483648 > ; <<4 x int>> [#uses=1] + %tmp181 = cast <4 x int> %tmp180 to <4 x float> ; <<4 x float>> [#uses=1] + %tmp194 = tail call <4 x float> %llvm.x86.sse.cmp.ps( <4 x float> %tmp170, <4 x float> %tmp44, sbyte 1 ) ; <<4 x float>> [#uses=1] + %tmp195 = cast <4 x float> %tmp194 to <4 x int> ; <<4 x int>> [#uses=1] + %tmp208 = tail call <4 x float> %llvm.x86.sse.cmp.ps( <4 x float> %tmp44, <4 x float> %tmp181, sbyte 1 ) ; <<4 x float>> [#uses=1] + %tmp209 = cast <4 x float> %tmp208 to <4 x int> ; <<4 x int>> [#uses=1] + %tmp220 = tail call <4 x int> %llvm.x86.sse2.packssdw.128( <4 x int> %tmp195, <4 x int> %tmp209 ) ; <<4 x int>> [#uses=1] + %tmp224 = cast <4 x int> %tmp220 to <8 x short> ; <<8 x short>> [#uses=1] + %tmp225 = shufflevector <8 x short> %tmp224, <8 x short> undef, <8 x uint> < uint 0, uint 1, uint 2, uint 3, uint 6, uint 5, uint 4, uint 7 > ; <<8 x short>> [#uses=1] + %tmp227 = shufflevector <8 x short> %tmp225, <8 x short> undef, <8 x uint> < uint 2, uint 1, uint 0, uint 3, uint 4, uint 5, uint 6, uint 7 > ; <<8 x short>> [#uses=1] + %tmp227 = cast <8 x short> %tmp227 to <4 x float> ; <<4 x float>> [#uses=1] + store <4 x float> %tmp227, <4 x float>* %c + %tmp230 = cast <4 x float> %tmp50 to <4 x int> ; <<4 x int>> [#uses=1] + %tmp231 = shufflevector <4 x int> %tmp230, <4 x int> undef, <4 x uint> < uint 3, uint 3, uint 3, uint 3 > ; <<4 x int>> [#uses=2] + %tmp231 = cast <4 x int> %tmp231 to <4 x float> ; <<4 x float>> [#uses=1] + %tmp241 = xor <4 x int> %tmp231, < int -2147483648, int -2147483648, int -2147483648, int -2147483648 > ; <<4 x int>> [#uses=1] + %tmp242 = cast <4 x int> %tmp241 to <4 x float> ; <<4 x float>> [#uses=1] + %tmp255 = tail call <4 x float> %llvm.x86.sse.cmp.ps( <4 x float> %tmp231, <4 x float> %tmp44, sbyte 1 ) ; <<4 x float>> [#uses=1] + %tmp256 = cast <4 x float> %tmp255 to <4 x int> ; <<4 x int>> [#uses=1] + %tmp269 = tail call <4 x float> %llvm.x86.sse.cmp.ps( <4 x float> %tmp44, <4 x float> %tmp242, sbyte 1 ) ; <<4 x float>> [#uses=1] + %tmp270 = cast <4 x float> %tmp269 to <4 x int> ; <<4 x int>> [#uses=1] + %tmp281 = tail call <4 x int> %llvm.x86.sse2.packssdw.128( <4 x int> %tmp256, <4 x int> %tmp270 ) ; <<4 x int>> [#uses=1] + %tmp285 = cast <4 x int> %tmp281 to <8 x short> ; <<8 x short>> [#uses=1] + %tmp286 = shufflevector <8 x short> %tmp285, <8 x short> undef, <8 x uint> < uint 0, uint 1, uint 2, uint 3, uint 6, uint 5, uint 4, uint 7 > ; <<8 x short>> [#uses=1] + %tmp288 = shufflevector <8 x short> %tmp286, <8 x short> undef, <8 x uint> < uint 2, uint 1, uint 0, uint 3, uint 4, uint 5, uint 6, uint 7 > ; <<8 x short>> [#uses=1] + %tmp288 = cast <8 x short> %tmp288 to <4 x float> ; <<4 x float>> [#uses=1] + store <4 x float> %tmp288, <4 x float>* %d + ret int 0 + } + + declare <4 x float> %llvm.x86.sse.cmp.ps(<4 x float>, <4 x float>, sbyte) + + declare <4 x int> %llvm.x86.sse2.packssdw.128(<4 x int>, <4 x int>) Index: llvm/test/Regression/CodeGen/X86/2006-05-02-InstrSched1.ll diff -c /dev/null llvm/test/Regression/CodeGen/X86/2006-05-02-InstrSched1.ll:1.1 *** /dev/null Tue May 2 21:11:48 2006 --- llvm/test/Regression/CodeGen/X86/2006-05-02-InstrSched1.ll Tue May 2 21:11:36 2006 *************** *** 0 **** --- 1,20 ---- + ; RUN: llvm-as < %s | llc -march=x86 -relocation-model=static -stats 2>&1 | grep "asm-printer" | grep 14 + %size20 = external global uint ; [#uses=1] + %in5 = external global ubyte* ; [#uses=1] + + int %compare(sbyte* %a, sbyte* %b) { + %tmp = cast sbyte* %a to uint* ; [#uses=1] + %tmp1 = cast sbyte* %b to uint* ; [#uses=1] + %tmp = load uint* %size20 ; [#uses=1] + %tmp = load ubyte** %in5 ; [#uses=2] + %tmp3 = load uint* %tmp1 ; [#uses=1] + %tmp4 = getelementptr ubyte* %tmp, uint %tmp3 ; [#uses=1] + %tmp7 = load uint* %tmp ; [#uses=1] + %tmp8 = getelementptr ubyte* %tmp, uint %tmp7 ; [#uses=1] + %tmp8 = cast ubyte* %tmp8 to sbyte* ; [#uses=1] + %tmp4 = cast ubyte* %tmp4 to sbyte* ; [#uses=1] + %tmp = tail call int %memcmp( sbyte* %tmp8, sbyte* %tmp4, uint %tmp ) ; [#uses=1] + ret int %tmp + } + + declare int %memcmp(sbyte*, sbyte*, uint) Index: llvm/test/Regression/CodeGen/X86/2006-05-02-InstrSched2.ll diff -c /dev/null llvm/test/Regression/CodeGen/X86/2006-05-02-InstrSched2.ll:1.1 *** /dev/null Tue May 2 21:11:48 2006 --- llvm/test/Regression/CodeGen/X86/2006-05-02-InstrSched2.ll Tue May 2 21:11:36 2006 *************** *** 0 **** --- 1,24 ---- + ; RUN: llvm-as < %s | llc -march=x86 -stats 2>&1 | grep "asm-printer" | grep 19 + + void %_ZN9__gnu_cxx9hashtableISt4pairIKPKciES3_NS_4hashIS3_EESt10_Select1stIS5_E5eqstrSaIiEE14find_or_insertERKS5__cond_true456.i(sbyte* %tmp435.i, uint* %tmp449.i.out) { + newFuncRoot: + br label %cond_true456.i + + bb459.i.exitStub: ; preds = %cond_true456.i + store uint %tmp449.i, uint* %tmp449.i.out + ret void + + cond_true456.i: ; preds = %cond_true456.i, %newFuncRoot + %__s441.2.4.i = phi sbyte* [ %tmp451.i, %cond_true456.i ], [ %tmp435.i, %newFuncRoot ] ; [#uses=2] + %__h.2.4.i = phi uint [ %tmp449.i, %cond_true456.i ], [ 0, %newFuncRoot ] ; [#uses=1] + %tmp446.i = mul uint %__h.2.4.i, 5 ; [#uses=1] + %tmp.i = load sbyte* %__s441.2.4.i ; [#uses=1] + %tmp448.i = cast sbyte %tmp.i to uint ; [#uses=1] + %tmp449.i = add uint %tmp448.i, %tmp446.i ; [#uses=2] + %tmp450.i = cast sbyte* %__s441.2.4.i to uint ; [#uses=1] + %tmp451.i = add uint %tmp450.i, 1 ; [#uses=1] + %tmp451.i = cast uint %tmp451.i to sbyte* ; [#uses=2] + %tmp45435.i = load sbyte* %tmp451.i ; [#uses=1] + %tmp45536.i = seteq sbyte %tmp45435.i, 0 ; [#uses=1] + br bool %tmp45536.i, label %bb459.i.exitStub, label %cond_true456.i + } From evan.cheng at apple.com Tue May 2 21:17:25 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 2 May 2006 21:17:25 -0500 Subject: [llvm-commits] CVS: llvm-test/Makefile.programs Message-ID: <200605030217.VAA30786@zion.cs.uiuc.edu> Changes in directory llvm-test: Makefile.programs updated: 1.208 -> 1.209 --- Log message: x86 LLCBETA back to -enable-x86-fastcc --- Diffs of the changes: (+1 -1) Makefile.programs | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm-test/Makefile.programs diff -u llvm-test/Makefile.programs:1.208 llvm-test/Makefile.programs:1.209 --- llvm-test/Makefile.programs:1.208 Mon May 1 04:16:32 2006 +++ llvm-test/Makefile.programs Tue May 2 21:17:13 2006 @@ -197,7 +197,7 @@ LLCBETAOPTION := -sched=simple endif ifeq ($(ARCH),x86) -LLCBETAOPTION := -sched-ignore-store +LLCBETAOPTION := -enable-x86-fastcc endif ifeq ($(ARCH),Sparc) LLCBETAOPTION := -enable-sparc-v9-insts From natebegeman at mac.com Tue May 2 22:48:14 2006 From: natebegeman at mac.com (Nate Begeman) Date: Tue, 2 May 2006 22:48:14 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Message-ID: <200605030348.WAA31192@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAGISel.cpp updated: 1.232 -> 1.233 --- Log message: Finish up the initial jump table implementation by allowing jump tables to not be 100% dense. Increase the minimum threshold for the number of cases in a switch statement from 4 to 6 in order to create a jump table. --- Diffs of the changes: (+34 -26) SelectionDAGISel.cpp | 60 ++++++++++++++++++++++++++++----------------------- 1 files changed, 34 insertions(+), 26 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.232 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.233 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.232 Tue May 2 20:29:56 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue May 2 22:48:02 2006 @@ -836,11 +836,6 @@ SDOperand ADD = DAG.getNode(ISD::ADD, PTy, IDX, DAG.getJumpTable(JT.JTI,PTy)); SDOperand LD = DAG.getLoad(PTy, Copy.getValue(1), ADD, DAG.getSrcValue(0)); DAG.setRoot(DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), LD)); - - // Update successor info - for (std::set::iterator ii = JT.SuccMBBs.begin(), - ee = JT.SuccMBBs.end(); ii != ee; ++ii) - JT.MBB->addSuccessor(*ii); } void SelectionDAGLowering::visitSwitch(SwitchInst &I) { @@ -885,22 +880,18 @@ const BasicBlock *LLVMBB = CurMBB->getBasicBlock(); Reloc::Model Relocs = TLI.getTargetMachine().getRelocationModel(); - // If the switch has more than 3 blocks, and is 100% dense, then emit a jump - // table rather than lowering the switch to a binary tree of conditional + // If the switch has more than 5 blocks, and at least 75% dense, then emit a + // jump table rather than lowering the switch to a binary tree of conditional // branches. - // FIXME: Make this work with 64 bit targets someday, possibly by always - // doing differences there so that entries stay 32 bits. // FIXME: Make this work with PIC code if (TLI.isOperationLegal(ISD::BRIND, TLI.getPointerTy()) && - TLI.getPointerTy() == MVT::i32 && (Relocs == Reloc::Static || Relocs == Reloc::DynamicNoPIC) && - Cases.size() > 3) { + Cases.size() > 5) { uint64_t First = cast(Cases.front().first)->getRawValue(); uint64_t Last = cast(Cases.back().first)->getRawValue(); - - // Determine density - // FIXME: support sub-100% density - if (((Last - First) + 1ULL) == (uint64_t)Cases.size()) { + double Density = (double)Cases.size() / (double)((Last - First) + 1ULL); + + if (Density >= 0.75) { // Create a new basic block to hold the code for loading the address // of the jump table, and jumping to it. Update successor information; // we will either branch to the default case for the switch, or the jump @@ -938,16 +929,31 @@ DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP, DAG.getBasicBlock(Default))); - // Build a sorted vector of destination BBs, corresponding to each target - // of the switch. - // FIXME: need to insert DefaultMBB for each "hole" in the jump table, - // when we support jump tables with < 100% density. + // Build a vector of destination BBs, corresponding to each target + // of the jump table. If the value of the jump table slot corresponds to + // a case statement, push the case's BB onto the vector, otherwise, push + // the default BB. std::set UniqueBBs; std::vector DestBBs; - for (CaseItr ii = Cases.begin(), ee = Cases.end(); ii != ee; ++ii) { - DestBBs.push_back(ii->second); - UniqueBBs.insert(ii->second); + uint64_t TEI = First; + for (CaseItr ii = Cases.begin(), ee = Cases.end(); ii != ee; ++TEI) { + if (cast(ii->first)->getRawValue() == TEI) { + DestBBs.push_back(ii->second); + UniqueBBs.insert(ii->second); + ++ii; + } else { + DestBBs.push_back(Default); + UniqueBBs.insert(Default); + } } + + // Update successor info + for (std::set::iterator ii = UniqueBBs.begin(), + ee = UniqueBBs.end(); ii != ee; ++ii) + JumpTableBB->addSuccessor(*ii); + + // Create a jump table index for this jump table, or return an existing + // one. unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs); // Set the jump table information so that we can codegen it as a second @@ -956,7 +962,6 @@ JT.JTI = JTI; JT.MBB = JumpTableBB; JT.Default = Default; - JT.SuccMBBs = UniqueBBs; return; } } @@ -3227,10 +3232,13 @@ MachineBasicBlock *PHIBB = PHI->getParent(); assert(PHI->getOpcode() == TargetInstrInfo::PHI && "This is not a machine PHI node that we are updating!"); - if (PHIBB == JT.Default || JT.SuccMBBs.find(PHIBB) != JT.SuccMBBs.end()) { - PHIBB = (PHIBB == JT.Default) ? RangeBB : BB; + if (PHIBB == JT.Default) { PHI->addRegOperand(PHINodesToUpdate[pi].second); - PHI->addMachineBasicBlockOperand(PHIBB); + PHI->addMachineBasicBlockOperand(RangeBB); + } + if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) { + PHI->addRegOperand(PHINodesToUpdate[pi].second); + PHI->addMachineBasicBlockOperand(BB); } } return; From resistor at mac.com Tue May 2 20:30:17 2006 From: resistor at mac.com (Owen Anderson) Date: Tue, 2 May 2006 20:30:17 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/CBackend/CTargetMachine.h Message-ID: <200605030130.UAA30319@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/CBackend: CTargetMachine.h updated: 1.10 -> 1.11 --- Log message: Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference. This fixes PR 759: http://llvm.cs.uiuc.edu/PR759 . --- Diffs of the changes: (+6 -1) CTargetMachine.h | 7 ++++++- 1 files changed, 6 insertions(+), 1 deletion(-) Index: llvm/lib/Target/CBackend/CTargetMachine.h diff -u llvm/lib/Target/CBackend/CTargetMachine.h:1.10 llvm/lib/Target/CBackend/CTargetMachine.h:1.11 --- llvm/lib/Target/CBackend/CTargetMachine.h:1.10 Wed Mar 22 23:43:15 2006 +++ llvm/lib/Target/CBackend/CTargetMachine.h Tue May 2 20:29:57 2006 @@ -19,8 +19,11 @@ namespace llvm { struct CTargetMachine : public TargetMachine { + const TargetData DataLayout; // Calculates type size & alignment + CTargetMachine(const Module &M, const std::string &FS) - : TargetMachine("CBackend", M) {} + : TargetMachine("CBackend", M), + DataLayout("CBackend") {} // This is the only thing that actually does anything here. virtual bool addPassesToEmitFile(PassManager &PM, std::ostream &Out, @@ -28,6 +31,8 @@ // This class always works, but shouldn't be the default in most cases. static unsigned getModuleMatchQuality(const Module &M) { return 1; } + + virtual const TargetData *getTargetData() const { return &DataLayout; } }; } // End llvm namespace From resistor at mac.com Tue May 2 20:30:20 2006 From: resistor at mac.com (Owen Anderson) Date: Tue, 2 May 2006 20:30:20 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/DwarfWriter.h MachineConstantPool.h MachineJumpTableInfo.h Message-ID: <200605030130.UAA30327@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: DwarfWriter.h updated: 1.34 -> 1.35 MachineConstantPool.h updated: 1.15 -> 1.16 MachineJumpTableInfo.h updated: 1.2 -> 1.3 --- Log message: Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference. This fixes PR 759: http://llvm.cs.uiuc.edu/PR759 . --- Diffs of the changes: (+5 -5) DwarfWriter.h | 2 +- MachineConstantPool.h | 4 ++-- MachineJumpTableInfo.h | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) Index: llvm/include/llvm/CodeGen/DwarfWriter.h diff -u llvm/include/llvm/CodeGen/DwarfWriter.h:1.34 llvm/include/llvm/CodeGen/DwarfWriter.h:1.35 --- llvm/include/llvm/CodeGen/DwarfWriter.h:1.34 Fri Apr 7 15:44:42 2006 +++ llvm/include/llvm/CodeGen/DwarfWriter.h Tue May 2 20:29:56 2006 @@ -85,7 +85,7 @@ AsmPrinter *Asm; /// TD - Target data. - const TargetData &TD; + const TargetData *TD; /// RI - Register Information. const MRegisterInfo *RI; Index: llvm/include/llvm/CodeGen/MachineConstantPool.h diff -u llvm/include/llvm/CodeGen/MachineConstantPool.h:1.15 llvm/include/llvm/CodeGen/MachineConstantPool.h:1.16 --- llvm/include/llvm/CodeGen/MachineConstantPool.h:1.15 Tue Apr 18 11:03:18 2006 +++ llvm/include/llvm/CodeGen/MachineConstantPool.h Tue May 2 20:29:56 2006 @@ -42,11 +42,11 @@ }; class MachineConstantPool { - const TargetData &TD; + const TargetData *TD; unsigned PoolAlignment; std::vector Constants; public: - MachineConstantPool(const TargetData &td) : TD(td), PoolAlignment(1) {} + MachineConstantPool(const TargetData *td) : TD(td), PoolAlignment(1) {} /// getConstantPoolAlignment - Return the log2 of the alignment required by /// the whole constant pool, of which the first element must be aligned. Index: llvm/include/llvm/CodeGen/MachineJumpTableInfo.h diff -u llvm/include/llvm/CodeGen/MachineJumpTableInfo.h:1.2 llvm/include/llvm/CodeGen/MachineJumpTableInfo.h:1.3 --- llvm/include/llvm/CodeGen/MachineJumpTableInfo.h:1.2 Sat Apr 22 18:52:35 2006 +++ llvm/include/llvm/CodeGen/MachineJumpTableInfo.h Tue May 2 20:29:56 2006 @@ -37,10 +37,10 @@ }; class MachineJumpTableInfo { - const TargetData &TD; + const TargetData *TD; std::vector JumpTables; public: - MachineJumpTableInfo(const TargetData &td) : TD(td) {} + MachineJumpTableInfo(const TargetData *td) : TD(td) {} /// getJumpTableIndex - Create a new jump table or return an existing one. /// From resistor at mac.com Tue May 2 20:30:21 2006 From: resistor at mac.com (Owen Anderson) Date: Tue, 2 May 2006 20:30:21 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86AsmPrinter.cpp X86ISelLowering.cpp X86TargetMachine.cpp X86TargetMachine.h Message-ID: <200605030130.UAA30373@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86AsmPrinter.cpp updated: 1.175 -> 1.176 X86ISelLowering.cpp updated: 1.197 -> 1.198 X86TargetMachine.cpp updated: 1.112 -> 1.113 X86TargetMachine.h updated: 1.33 -> 1.34 --- Log message: Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference. This fixes PR 759: http://llvm.cs.uiuc.edu/PR759 . --- Diffs of the changes: (+8 -5) X86AsmPrinter.cpp | 4 ++-- X86ISelLowering.cpp | 4 ++-- X86TargetMachine.cpp | 3 ++- X86TargetMachine.h | 2 ++ 4 files changed, 8 insertions(+), 5 deletions(-) Index: llvm/lib/Target/X86/X86AsmPrinter.cpp diff -u llvm/lib/Target/X86/X86AsmPrinter.cpp:1.175 llvm/lib/Target/X86/X86AsmPrinter.cpp:1.176 --- llvm/lib/Target/X86/X86AsmPrinter.cpp:1.175 Tue May 2 12:34:51 2006 +++ llvm/lib/Target/X86/X86AsmPrinter.cpp Tue May 2 20:29:57 2006 @@ -84,7 +84,7 @@ } bool X86SharedAsmPrinter::doFinalization(Module &M) { - const TargetData &TD = TM.getTargetData(); + const TargetData *TD = TM.getTargetData(); // Print out module-level global variables here. for (Module::const_global_iterator I = M.global_begin(), E = M.global_end(); @@ -97,7 +97,7 @@ std::string name = Mang->getValueName(I); Constant *C = I->getInitializer(); - unsigned Size = TD.getTypeSize(C->getType()); + unsigned Size = TD->getTypeSize(C->getType()); unsigned Align = getPreferredAlignmentLog(I); if (C->isNullValue() && /* FIXME: Verify correct */ Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.197 llvm/lib/Target/X86/X86ISelLowering.cpp:1.198 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.197 Fri Apr 28 16:29:37 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Tue May 2 20:29:57 2006 @@ -3522,7 +3522,7 @@ if ((Align & 3) != 0 || (I && I->getValue() < Subtarget->getMinRepStrSizeThreshold())) { MVT::ValueType IntPtr = getPointerTy(); - const Type *IntPtrTy = getTargetData().getIntPtrType(); + const Type *IntPtrTy = getTargetData()->getIntPtrType(); std::vector > Args; Args.push_back(std::make_pair(Op.getOperand(1), IntPtrTy)); // Extend the ubyte argument to be an int value for the call. @@ -3655,7 +3655,7 @@ if ((Align & 3) != 0 || (I && I->getValue() < Subtarget->getMinRepStrSizeThreshold())) { MVT::ValueType IntPtr = getPointerTy(); - const Type *IntPtrTy = getTargetData().getIntPtrType(); + const Type *IntPtrTy = getTargetData()->getIntPtrType(); std::vector > Args; Args.push_back(std::make_pair(Op.getOperand(1), IntPtrTy)); Args.push_back(std::make_pair(Op.getOperand(2), IntPtrTy)); Index: llvm/lib/Target/X86/X86TargetMachine.cpp diff -u llvm/lib/Target/X86/X86TargetMachine.cpp:1.112 llvm/lib/Target/X86/X86TargetMachine.cpp:1.113 --- llvm/lib/Target/X86/X86TargetMachine.cpp:1.112 Sat Apr 8 14:46:55 2006 +++ llvm/lib/Target/X86/X86TargetMachine.cpp Tue May 2 20:29:57 2006 @@ -68,7 +68,8 @@ /// X86TargetMachine ctor - Create an ILP32 architecture model /// X86TargetMachine::X86TargetMachine(const Module &M, const std::string &FS) - : TargetMachine("X86", true, 4, 4, 4, 4, 4), + : TargetMachine("X86"), + DataLayout("X86", true, 4, 4, 4, 4, 4), Subtarget(M, FS), FrameInfo(TargetFrameInfo::StackGrowsDown, Subtarget.getStackAlignment(), -4), Index: llvm/lib/Target/X86/X86TargetMachine.h diff -u llvm/lib/Target/X86/X86TargetMachine.h:1.33 llvm/lib/Target/X86/X86TargetMachine.h:1.34 --- llvm/lib/Target/X86/X86TargetMachine.h:1.33 Wed Mar 22 23:43:16 2006 +++ llvm/lib/Target/X86/X86TargetMachine.h Tue May 2 20:29:57 2006 @@ -26,6 +26,7 @@ namespace llvm { class X86TargetMachine : public TargetMachine { + const TargetData DataLayout; // Calculates type size & alignment X86InstrInfo InstrInfo; X86Subtarget Subtarget; TargetFrameInfo FrameInfo; @@ -42,6 +43,7 @@ virtual const MRegisterInfo *getRegisterInfo() const { return &InstrInfo.getRegisterInfo(); } + virtual const TargetData *getTargetData() const { return &DataLayout; } virtual bool addPassesToEmitMachineCode(FunctionPassManager &PM, MachineCodeEmitter &MCE); From resistor at mac.com Tue May 2 20:30:21 2006 From: resistor at mac.com (Owen Anderson) Date: Tue, 2 May 2006 20:30:21 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/AsmPrinter.cpp DwarfWriter.cpp ELFWriter.cpp MachineFunction.cpp Message-ID: <200605030130.UAA30375@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: AsmPrinter.cpp updated: 1.65 -> 1.66 DwarfWriter.cpp updated: 1.57 -> 1.58 ELFWriter.cpp updated: 1.23 -> 1.24 MachineFunction.cpp updated: 1.89 -> 1.90 --- Log message: Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference. This fixes PR 759: http://llvm.cs.uiuc.edu/PR759 . --- Diffs of the changes: (+25 -25) AsmPrinter.cpp | 32 ++++++++++++++++---------------- DwarfWriter.cpp | 4 ++-- ELFWriter.cpp | 8 ++++---- MachineFunction.cpp | 6 +++--- 4 files changed, 25 insertions(+), 25 deletions(-) Index: llvm/lib/CodeGen/AsmPrinter.cpp diff -u llvm/lib/CodeGen/AsmPrinter.cpp:1.65 llvm/lib/CodeGen/AsmPrinter.cpp:1.66 --- llvm/lib/CodeGen/AsmPrinter.cpp:1.65 Tue May 2 12:36:46 2006 +++ llvm/lib/CodeGen/AsmPrinter.cpp Tue May 2 20:29:56 2006 @@ -144,7 +144,7 @@ void AsmPrinter::EmitConstantPool(MachineConstantPool *MCP) { const std::vector &CP = MCP->getConstants(); if (CP.empty()) return; - const TargetData &TD = TM.getTargetData(); + const TargetData *TD = TM.getTargetData(); SwitchSection(ConstantPoolSection, 0); EmitAlignment(MCP->getConstantPoolAlignment()); @@ -154,7 +154,7 @@ WriteTypeSymbolic(O, CP[i].Val->getType(), 0) << '\n'; EmitGlobalConstant(CP[i].Val); if (i != e-1) { - unsigned EntSize = TM.getTargetData().getTypeSize(CP[i].Val->getType()); + unsigned EntSize = TM.getTargetData()->getTypeSize(CP[i].Val->getType()); unsigned ValEnd = CP[i].Offset + EntSize; // Emit inter-object padding for alignment. EmitZeros(CP[i+1].Offset-ValEnd); @@ -168,7 +168,7 @@ void AsmPrinter::EmitJumpTableInfo(MachineJumpTableInfo *MJTI) { const std::vector &JT = MJTI->getJumpTables(); if (JT.empty()) return; - const TargetData &TD = TM.getTargetData(); + const TargetData *TD = TM.getTargetData(); // FIXME: someday we need to handle PIC jump tables assert((TM.getRelocationModel() == Reloc::Static || @@ -176,7 +176,7 @@ "Unhandled relocation model emitting jump table information!"); SwitchSection(JumpTableSection, 0); - EmitAlignment(Log2_32(TD.getPointerAlignment())); + EmitAlignment(Log2_32(TD->getPointerAlignment())); for (unsigned i = 0, e = JT.size(); i != e; ++i) { O << PrivateGlobalPrefix << "JTI" << getFunctionNumber() << '_' << i << ":\n"; @@ -242,7 +242,7 @@ /// specified global, returned in log form. This includes an explicitly /// requested alignment (if the global has one). unsigned AsmPrinter::getPreferredAlignmentLog(const GlobalVariable *GV) const { - unsigned Alignment = TM.getTargetData().getTypeAlignmentShift(GV->getType()); + unsigned Alignment = TM.getTargetData()->getTypeAlignmentShift(GV->getType()); if (GV->getAlignment() > (1U << Alignment)) Alignment = Log2_32(GV->getAlignment()); @@ -253,7 +253,7 @@ if (Alignment < 4) { // If the global is not external, see if it is large. If so, give it a // larger alignment. - if (TM.getTargetData().getTypeSize(GV->getType()->getElementType()) > 128) + if (TM.getTargetData()->getTypeSize(GV->getType()->getElementType()) > 128) Alignment = 4; // 16-byte alignment. } } @@ -310,13 +310,13 @@ else O << GlobalVarAddrPrefix << Mang->getValueName(GV) << GlobalVarAddrSuffix; } else if (const ConstantExpr *CE = dyn_cast(CV)) { - const TargetData &TD = TM.getTargetData(); + const TargetData *TD = TM.getTargetData(); switch(CE->getOpcode()) { case Instruction::GetElementPtr: { // generate a symbolic expression for the byte address const Constant *ptrVal = CE->getOperand(0); std::vector idxVec(CE->op_begin()+1, CE->op_end()); - if (int64_t Offset = TD.getIndexedOffset(ptrVal->getType(), idxVec)) { + if (int64_t Offset = TD->getIndexedOffset(ptrVal->getType(), idxVec)) { if (Offset) O << "("; EmitConstantValueOnly(ptrVal); @@ -344,7 +344,7 @@ || (isa(Ty) && (OpTy == Type::LongTy || OpTy == Type::ULongTy || OpTy == Type::IntTy || OpTy == Type::UIntTy)) - || (((TD.getTypeSize(Ty) >= TD.getTypeSize(OpTy)) + || (((TD->getTypeSize(Ty) >= TD->getTypeSize(OpTy)) && OpTy->isLosslesslyConvertibleTo(Ty)))) && "FIXME: Don't yet support this kind of constant cast expr"); EmitConstantValueOnly(Op); @@ -426,10 +426,10 @@ /// EmitGlobalConstant - Print a general LLVM constant to the .s file. /// void AsmPrinter::EmitGlobalConstant(const Constant *CV) { - const TargetData &TD = TM.getTargetData(); + const TargetData *TD = TM.getTargetData(); if (CV->isNullValue() || isa(CV)) { - EmitZeros(TD.getTypeSize(CV->getType())); + EmitZeros(TD->getTypeSize(CV->getType())); return; } else if (const ConstantArray *CVA = dyn_cast(CV)) { if (CVA->isString()) { @@ -441,13 +441,13 @@ return; } else if (const ConstantStruct *CVS = dyn_cast(CV)) { // Print the fields in successive locations. Pad to align if needed! - const StructLayout *cvsLayout = TD.getStructLayout(CVS->getType()); + const StructLayout *cvsLayout = TD->getStructLayout(CVS->getType()); uint64_t sizeSoFar = 0; for (unsigned i = 0, e = CVS->getNumOperands(); i != e; ++i) { const Constant* field = CVS->getOperand(i); // Check if padding is needed and insert one or more 0s. - uint64_t fieldSize = TD.getTypeSize(field->getType()); + uint64_t fieldSize = TD->getTypeSize(field->getType()); uint64_t padSize = ((i == e-1? cvsLayout->StructSize : cvsLayout->MemberOffsets[i+1]) - cvsLayout->MemberOffsets[i]) - fieldSize; @@ -470,7 +470,7 @@ if (Data64bitsDirective) O << Data64bitsDirective << DoubleToBits(Val) << "\t" << CommentString << " double value: " << Val << "\n"; - else if (TD.isBigEndian()) { + else if (TD->isBigEndian()) { O << Data32bitsDirective << unsigned(DoubleToBits(Val) >> 32) << "\t" << CommentString << " double most significant word " << Val << "\n"; @@ -497,7 +497,7 @@ if (Data64bitsDirective) O << Data64bitsDirective << Val << "\n"; - else if (TD.isBigEndian()) { + else if (TD->isBigEndian()) { O << Data32bitsDirective << unsigned(Val >> 32) << "\t" << CommentString << " Double-word most significant word " << Val << "\n"; @@ -533,7 +533,7 @@ O << Data16bitsDirective; break; case Type::PointerTyID: - if (TD.getPointerSize() == 8) { + if (TD->getPointerSize() == 8) { O << Data64bitsDirective; break; } Index: llvm/lib/CodeGen/DwarfWriter.cpp diff -u llvm/lib/CodeGen/DwarfWriter.cpp:1.57 llvm/lib/CodeGen/DwarfWriter.cpp:1.58 --- llvm/lib/CodeGen/DwarfWriter.cpp:1.57 Mon Apr 10 18:09:19 2006 +++ llvm/lib/CodeGen/DwarfWriter.cpp Tue May 2 20:29:56 2006 @@ -1075,7 +1075,7 @@ if (Asm->Data64bitsDirective) { O << Asm->Data64bitsDirective << "0x" << std::hex << Value << std::dec; } else { - if (TD.isBigEndian()) { + if (TD->isBigEndian()) { EmitInt32(unsigned(Value >> 32)); O << "\n"; EmitInt32(unsigned(Value)); } else { @@ -1361,7 +1361,7 @@ Offset -= FieldOffset; // Maybe we need to work from the other end. - if (TD.isLittleEndian()) Offset = FieldSize - (Offset + Size); + if (TD->isLittleEndian()) Offset = FieldSize - (Offset + Size); Member->AddUInt(DW_AT_byte_size, 0, FieldSize >> 3); Member->AddUInt(DW_AT_bit_size, 0, Size); Index: llvm/lib/CodeGen/ELFWriter.cpp diff -u llvm/lib/CodeGen/ELFWriter.cpp:1.23 llvm/lib/CodeGen/ELFWriter.cpp:1.24 --- llvm/lib/CodeGen/ELFWriter.cpp:1.23 Tue May 2 19:28:15 2006 +++ llvm/lib/CodeGen/ELFWriter.cpp Tue May 2 20:29:56 2006 @@ -158,8 +158,8 @@ e_machine = 0; // e_machine defaults to 'No Machine' e_flags = 0; // e_flags defaults to 0, no flags. - is64Bit = TM.getTargetData().getPointerSizeInBits() == 64; - isLittleEndian = TM.getTargetData().isLittleEndian(); + is64Bit = TM.getTargetData()->getPointerSizeInBits() == 64; + isLittleEndian = TM.getTargetData()->isLittleEndian(); // Create the machine code emitter object for this target. MCE = new ELFCodeEmitter(*this); @@ -233,8 +233,8 @@ } const Type *GVType = (const Type*)GV->getType(); - unsigned Align = TM.getTargetData().getTypeAlignment(GVType); - unsigned Size = TM.getTargetData().getTypeSize(GVType); + unsigned Align = TM.getTargetData()->getTypeAlignment(GVType); + unsigned Size = TM.getTargetData()->getTypeSize(GVType); // If this global has a zero initializer, it is part of the .bss or common // section. Index: llvm/lib/CodeGen/MachineFunction.cpp diff -u llvm/lib/CodeGen/MachineFunction.cpp:1.89 llvm/lib/CodeGen/MachineFunction.cpp:1.90 --- llvm/lib/CodeGen/MachineFunction.cpp:1.89 Sat Apr 22 18:52:35 2006 +++ llvm/lib/CodeGen/MachineFunction.cpp Tue May 2 20:29:56 2006 @@ -367,11 +367,11 @@ } unsigned MachineJumpTableInfo::getEntrySize() const { - return TD.getPointerSize(); + return TD->getPointerSize(); } unsigned MachineJumpTableInfo::getAlignment() const { - return TD.getPointerAlignment(); + return TD->getPointerAlignment(); } void MachineJumpTableInfo::dump() const { print(std::cerr); } @@ -400,7 +400,7 @@ unsigned Offset = 0; if (!Constants.empty()) { Offset = Constants.back().Offset; - Offset += TD.getTypeSize(Constants.back().Val->getType()); + Offset += TD->getTypeSize(Constants.back().Val->getType()); Offset = (Offset+AlignMask)&~AlignMask; } From resistor at mac.com Tue May 2 20:30:21 2006 From: resistor at mac.com (Owen Anderson) Date: Tue, 2 May 2006 20:30:21 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp AlphaTargetMachine.cpp AlphaTargetMachine.h Message-ID: <200605030130.UAA30367@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Alpha: AlphaAsmPrinter.cpp updated: 1.35 -> 1.36 AlphaTargetMachine.cpp updated: 1.23 -> 1.24 AlphaTargetMachine.h updated: 1.12 -> 1.13 --- Log message: Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference. This fixes PR 759: http://llvm.cs.uiuc.edu/PR759 . --- Diffs of the changes: (+9 -6) AlphaAsmPrinter.cpp | 8 ++++---- AlphaTargetMachine.cpp | 3 ++- AlphaTargetMachine.h | 4 +++- 3 files changed, 9 insertions(+), 6 deletions(-) Index: llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp diff -u llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.35 llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.36 --- llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.35 Tue May 2 00:37:32 2006 +++ llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp Tue May 2 20:29:57 2006 @@ -221,7 +221,7 @@ } bool AlphaAsmPrinter::doFinalization(Module &M) { - const TargetData &TD = TM.getTargetData(); + const TargetData *TD = TM.getTargetData(); for (Module::const_global_iterator I = M.global_begin(), E = M.global_end(); I != E; ++I) if (I->hasInitializer()) { // External global require no code @@ -232,8 +232,8 @@ O << "\n\n"; std::string name = Mang->getValueName(I); Constant *C = I->getInitializer(); - unsigned Size = TD.getTypeSize(C->getType()); - // unsigned Align = TD.getTypeAlignmentShift(C->getType()); + unsigned Size = TD->getTypeSize(C->getType()); + // unsigned Align = TD->getTypeAlignmentShift(C->getType()); unsigned Align = getPreferredAlignmentLog(I); if (C->isNullValue() && @@ -243,7 +243,7 @@ if (I->hasInternalLinkage()) O << "\t.local " << name << "\n"; - O << "\t.comm " << name << "," << TD.getTypeSize(C->getType()) + O << "\t.comm " << name << "," << TD->getTypeSize(C->getType()) << "," << (1 << Align) << "\n"; } else { Index: llvm/lib/Target/Alpha/AlphaTargetMachine.cpp diff -u llvm/lib/Target/Alpha/AlphaTargetMachine.cpp:1.23 llvm/lib/Target/Alpha/AlphaTargetMachine.cpp:1.24 --- llvm/lib/Target/Alpha/AlphaTargetMachine.cpp:1.23 Sat Apr 8 14:46:55 2006 +++ llvm/lib/Target/Alpha/AlphaTargetMachine.cpp Tue May 2 20:29:57 2006 @@ -54,7 +54,8 @@ } AlphaTargetMachine::AlphaTargetMachine(const Module &M, const std::string &FS) - : TargetMachine("alpha", true), + : TargetMachine("alpha"), + DataLayout("alpha", true), FrameInfo(TargetFrameInfo::StackGrowsDown, 16, 0), JITInfo(*this), Subtarget(M, FS) Index: llvm/lib/Target/Alpha/AlphaTargetMachine.h diff -u llvm/lib/Target/Alpha/AlphaTargetMachine.h:1.12 llvm/lib/Target/Alpha/AlphaTargetMachine.h:1.13 --- llvm/lib/Target/Alpha/AlphaTargetMachine.h:1.12 Wed Mar 22 23:43:15 2006 +++ llvm/lib/Target/Alpha/AlphaTargetMachine.h Tue May 2 20:29:57 2006 @@ -26,11 +26,12 @@ class GlobalValue; class AlphaTargetMachine : public TargetMachine { + const TargetData DataLayout; // Calculates type size & alignment AlphaInstrInfo InstrInfo; TargetFrameInfo FrameInfo; AlphaJITInfo JITInfo; AlphaSubtarget Subtarget; - + public: AlphaTargetMachine(const Module &M, const std::string &FS); @@ -40,6 +41,7 @@ virtual const MRegisterInfo *getRegisterInfo() const { return &InstrInfo.getRegisterInfo(); } + virtual const TargetData *getTargetData() const { return &DataLayout; } virtual TargetJITInfo* getJITInfo() { return &JITInfo; } From resistor at mac.com Tue May 2 20:30:21 2006 From: resistor at mac.com (Owen Anderson) Date: Tue, 2 May 2006 20:30:21 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/ExecutionEngine/ExecutionEngine.h Message-ID: <200605030130.UAA30357@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/ExecutionEngine: ExecutionEngine.h updated: 1.36 -> 1.37 --- Log message: Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference. This fixes PR 759: http://llvm.cs.uiuc.edu/PR759 . --- Diffs of the changes: (+3 -3) ExecutionEngine.h | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) Index: llvm/include/llvm/ExecutionEngine/ExecutionEngine.h diff -u llvm/include/llvm/ExecutionEngine/ExecutionEngine.h:1.36 llvm/include/llvm/ExecutionEngine/ExecutionEngine.h:1.37 --- llvm/include/llvm/ExecutionEngine/ExecutionEngine.h:1.36 Wed Mar 22 23:22:24 2006 +++ llvm/include/llvm/ExecutionEngine/ExecutionEngine.h Tue May 2 20:29:56 2006 @@ -67,8 +67,8 @@ protected: ModuleProvider *MP; - void setTargetData(const TargetData &td) { - TD = &td; + void setTargetData(const TargetData *td) { + TD = td; } // To avoid having libexecutionengine depend on the JIT and interpreter @@ -88,7 +88,7 @@ virtual ~ExecutionEngine(); Module &getModule() const { return CurMod; } - const TargetData &getTargetData() const { return *TD; } + const TargetData *getTargetData() const { return TD; } /// create - This is the factory method for creating an execution engine which /// is appropriate for the current machine. From resistor at mac.com Tue May 2 20:30:20 2006 From: resistor at mac.com (Owen Anderson) Date: Tue, 2 May 2006 20:30:20 -0500 Subject: [llvm-commits] CVS: llvm/lib/ExecutionEngine/ExecutionEngine.cpp Message-ID: <200605030130.UAA30331@zion.cs.uiuc.edu> Changes in directory llvm/lib/ExecutionEngine: ExecutionEngine.cpp updated: 1.80 -> 1.81 --- Log message: Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference. This fixes PR 759: http://llvm.cs.uiuc.edu/PR759 . --- Diffs of the changes: (+15 -15) ExecutionEngine.cpp | 30 +++++++++++++++--------------- 1 files changed, 15 insertions(+), 15 deletions(-) Index: llvm/lib/ExecutionEngine/ExecutionEngine.cpp diff -u llvm/lib/ExecutionEngine/ExecutionEngine.cpp:1.80 llvm/lib/ExecutionEngine/ExecutionEngine.cpp:1.81 --- llvm/lib/ExecutionEngine/ExecutionEngine.cpp:1.80 Sat Apr 22 13:53:45 2006 +++ llvm/lib/ExecutionEngine/ExecutionEngine.cpp Tue May 2 20:29:56 2006 @@ -70,7 +70,7 @@ // static void *CreateArgv(ExecutionEngine *EE, const std::vector &InputArgv) { - unsigned PtrSize = EE->getTargetData().getPointerSize(); + unsigned PtrSize = EE->getTargetData()->getPointerSize(); char *Result = new char[(InputArgv.size()+1)*PtrSize]; DEBUG(std::cerr << "ARGV = " << (void*)Result << "\n"); @@ -218,7 +218,7 @@ uint64_t Offset = TD->getIndexedOffset(CE->getOperand(0)->getType(), Indexes); - if (getTargetData().getPointerSize() == 4) + if (getTargetData()->getPointerSize() == 4) Result.IntVal += Offset; else Result.LongVal += Offset; @@ -335,7 +335,7 @@ /// void ExecutionEngine::StoreValueToMemory(GenericValue Val, GenericValue *Ptr, const Type *Ty) { - if (getTargetData().isLittleEndian()) { + if (getTargetData()->isLittleEndian()) { switch (Ty->getTypeID()) { case Type::BoolTyID: case Type::UByteTyID: @@ -352,7 +352,7 @@ Ptr->Untyped[2] = (Val.UIntVal >> 16) & 255; Ptr->Untyped[3] = (Val.UIntVal >> 24) & 255; break; - case Type::PointerTyID: if (getTargetData().getPointerSize() == 4) + case Type::PointerTyID: if (getTargetData()->getPointerSize() == 4) goto Store4BytesLittleEndian; case Type::DoubleTyID: case Type::ULongTyID: @@ -386,7 +386,7 @@ Ptr->Untyped[1] = (Val.UIntVal >> 16) & 255; Ptr->Untyped[0] = (Val.UIntVal >> 24) & 255; break; - case Type::PointerTyID: if (getTargetData().getPointerSize() == 4) + case Type::PointerTyID: if (getTargetData()->getPointerSize() == 4) goto Store4BytesBigEndian; case Type::DoubleTyID: case Type::ULongTyID: @@ -411,7 +411,7 @@ GenericValue ExecutionEngine::LoadValueFromMemory(GenericValue *Ptr, const Type *Ty) { GenericValue Result; - if (getTargetData().isLittleEndian()) { + if (getTargetData()->isLittleEndian()) { switch (Ty->getTypeID()) { case Type::BoolTyID: case Type::UByteTyID: @@ -428,7 +428,7 @@ ((unsigned)Ptr->Untyped[2] << 16) | ((unsigned)Ptr->Untyped[3] << 24); break; - case Type::PointerTyID: if (getTargetData().getPointerSize() == 4) + case Type::PointerTyID: if (getTargetData()->getPointerSize() == 4) goto Load4BytesLittleEndian; case Type::DoubleTyID: case Type::ULongTyID: @@ -462,7 +462,7 @@ ((unsigned)Ptr->Untyped[1] << 16) | ((unsigned)Ptr->Untyped[0] << 24); break; - case Type::PointerTyID: if (getTargetData().getPointerSize() == 4) + case Type::PointerTyID: if (getTargetData()->getPointerSize() == 4) goto Load4BytesBigEndian; case Type::DoubleTyID: case Type::ULongTyID: @@ -491,7 +491,7 @@ return; } else if (const ConstantPacked *CP = dyn_cast(Init)) { unsigned ElementSize = - getTargetData().getTypeSize(CP->getType()->getElementType()); + getTargetData()->getTypeSize(CP->getType()->getElementType()); for (unsigned i = 0, e = CP->getNumOperands(); i != e; ++i) InitializeMemory(CP->getOperand(i), (char*)Addr+i*ElementSize); return; @@ -500,7 +500,7 @@ StoreValueToMemory(Val, (GenericValue*)Addr, Init->getType()); return; } else if (isa(Init)) { - memset(Addr, 0, (size_t)getTargetData().getTypeSize(Init->getType())); + memset(Addr, 0, (size_t)getTargetData()->getTypeSize(Init->getType())); return; } @@ -508,7 +508,7 @@ case Type::ArrayTyID: { const ConstantArray *CPA = cast(Init); unsigned ElementSize = - getTargetData().getTypeSize(CPA->getType()->getElementType()); + getTargetData()->getTypeSize(CPA->getType()->getElementType()); for (unsigned i = 0, e = CPA->getNumOperands(); i != e; ++i) InitializeMemory(CPA->getOperand(i), (char*)Addr+i*ElementSize); return; @@ -517,7 +517,7 @@ case Type::StructTyID: { const ConstantStruct *CPS = cast(Init); const StructLayout *SL = - getTargetData().getStructLayout(cast(CPS->getType())); + getTargetData()->getStructLayout(cast(CPS->getType())); for (unsigned i = 0, e = CPS->getNumOperands(); i != e; ++i) InitializeMemory(CPS->getOperand(i), (char*)Addr+SL->MemberOffsets[i]); return; @@ -534,7 +534,7 @@ /// their initializers into the memory. /// void ExecutionEngine::emitGlobals() { - const TargetData &TD = getTargetData(); + const TargetData *TD = getTargetData(); // Loop over all of the global variables in the program, allocating the memory // to hold them. @@ -546,7 +546,7 @@ const Type *Ty = I->getType()->getElementType(); // Allocate some memory for it! - unsigned Size = TD.getTypeSize(Ty); + unsigned Size = TD->getTypeSize(Ty); addGlobalMapping(I, new char[Size]); } else { // External variable reference. Try to use the dynamic loader to @@ -577,7 +577,7 @@ DEBUG(std::cerr << "Global '" << GV->getName() << "' -> " << GA << "\n"); const Type *ElTy = GV->getType()->getElementType(); - size_t GVSize = (size_t)getTargetData().getTypeSize(ElTy); + size_t GVSize = (size_t)getTargetData()->getTypeSize(ElTy); if (GA == 0) { // If it's not already specified, allocate memory for the global. GA = new char[GVSize]; From resistor at mac.com Tue May 2 20:30:22 2006 From: resistor at mac.com (Owen Anderson) Date: Tue, 2 May 2006 20:30:22 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetData.h TargetLowering.h TargetMachine.h Message-ID: <200605030130.UAA30401@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/Target: TargetData.h updated: 1.33 -> 1.34 TargetLowering.h updated: 1.69 -> 1.70 TargetMachine.h updated: 1.63 -> 1.64 --- Log message: Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference. This fixes PR 759: http://llvm.cs.uiuc.edu/PR759 . --- Diffs of the changes: (+15 -23) TargetData.h | 22 +++++++++++----------- TargetLowering.h | 4 ++-- TargetMachine.h | 12 ++---------- 3 files changed, 15 insertions(+), 23 deletions(-) Index: llvm/include/llvm/Target/TargetData.h diff -u llvm/include/llvm/Target/TargetData.h:1.33 llvm/include/llvm/Target/TargetData.h:1.34 --- llvm/include/llvm/Target/TargetData.h:1.33 Fri Jan 13 18:06:42 2006 +++ llvm/include/llvm/Target/TargetData.h Tue May 2 20:29:56 2006 @@ -54,18 +54,18 @@ unsigned char ByteAl = 1, unsigned char BoolAl = 1); // Copy constructor - TargetData (const TargetData &TD) : + TargetData (const TargetData *TD) : ImmutablePass(), - LittleEndian(TD.isLittleEndian()), - BoolAlignment(TD.getBoolAlignment()), - ByteAlignment(TD.getByteAlignment()), - ShortAlignment(TD.getShortAlignment()), - IntAlignment(TD.getIntAlignment()), - LongAlignment(TD.getLongAlignment()), - FloatAlignment(TD.getFloatAlignment()), - DoubleAlignment(TD.getDoubleAlignment()), - PointerSize(TD.getPointerSize()), - PointerAlignment(TD.getPointerAlignment()) { + LittleEndian(TD->isLittleEndian()), + BoolAlignment(TD->getBoolAlignment()), + ByteAlignment(TD->getByteAlignment()), + ShortAlignment(TD->getShortAlignment()), + IntAlignment(TD->getIntAlignment()), + LongAlignment(TD->getLongAlignment()), + FloatAlignment(TD->getFloatAlignment()), + DoubleAlignment(TD->getDoubleAlignment()), + PointerSize(TD->getPointerSize()), + PointerAlignment(TD->getPointerAlignment()) { } TargetData(const std::string &ToolName, const Module *M); Index: llvm/include/llvm/Target/TargetLowering.h diff -u llvm/include/llvm/Target/TargetLowering.h:1.69 llvm/include/llvm/Target/TargetLowering.h:1.70 --- llvm/include/llvm/Target/TargetLowering.h:1.69 Thu Apr 20 03:54:13 2006 +++ llvm/include/llvm/Target/TargetLowering.h Tue May 2 20:29:56 2006 @@ -78,7 +78,7 @@ virtual ~TargetLowering(); TargetMachine &getTargetMachine() const { return TM; } - const TargetData &getTargetData() const { return TD; } + const TargetData *getTargetData() const { return TD; } bool isLittleEndian() const { return IsLittleEndian; } MVT::ValueType getPointerTy() const { return PointerTy; } @@ -648,7 +648,7 @@ std::vector LegalAddressScales; TargetMachine &TM; - const TargetData &TD; + const TargetData *TD; /// IsLittleEndian - True if this is a little endian target. /// Index: llvm/include/llvm/Target/TargetMachine.h diff -u llvm/include/llvm/Target/TargetMachine.h:1.63 llvm/include/llvm/Target/TargetMachine.h:1.64 --- llvm/include/llvm/Target/TargetMachine.h:1.63 Thu Apr 20 13:17:21 2006 +++ llvm/include/llvm/Target/TargetMachine.h Tue May 2 20:29:56 2006 @@ -50,19 +50,11 @@ /// class TargetMachine { const std::string Name; - const TargetData DataLayout; // Calculates type size & alignment TargetMachine(const TargetMachine&); // DO NOT IMPLEMENT void operator=(const TargetMachine&); // DO NOT IMPLEMENT protected: // Can only create subclasses... - TargetMachine(const std::string &name, bool LittleEndian = false, - unsigned char PtrSize = 8, unsigned char PtrAl = 8, - unsigned char DoubleAl = 8, unsigned char FloatAl = 4, - unsigned char LongAl = 8, unsigned char IntAl = 4, - unsigned char ShortAl = 2, unsigned char ByteAl = 1, - unsigned char BoolAl = 1); - - TargetMachine(const std::string &name, const TargetData &TD); + TargetMachine(const std::string &name) : Name(name) { }; /// This constructor is used for targets that support arbitrary TargetData /// layouts, like the C backend. It initializes the TargetData to match that @@ -101,7 +93,7 @@ virtual const TargetInstrInfo *getInstrInfo() const { return 0; } virtual const TargetFrameInfo *getFrameInfo() const { return 0; } virtual TargetLowering *getTargetLowering() const { return 0; } - const TargetData &getTargetData() const { return DataLayout; } + virtual const TargetData *getTargetData() const { return 0; } /// getSubtarget - This method returns a pointer to the specified type of /// TargetSubtarget. In debug builds, it verifies that the object being From resistor at mac.com Tue May 2 20:30:22 2006 From: resistor at mac.com (Owen Anderson) Date: Tue, 2 May 2006 20:30:22 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp ScheduleDAG.cpp SelectionDAGISel.cpp Message-ID: <200605030130.UAA30395@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.370 -> 1.371 ScheduleDAG.cpp updated: 1.82 -> 1.83 SelectionDAGISel.cpp updated: 1.231 -> 1.232 --- Log message: Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference. This fixes PR 759: http://llvm.cs.uiuc.edu/PR759 . --- Diffs of the changes: (+24 -24) LegalizeDAG.cpp | 6 +++--- ScheduleDAG.cpp | 4 ++-- SelectionDAGISel.cpp | 38 +++++++++++++++++++------------------- 3 files changed, 24 insertions(+), 24 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.370 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.371 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.370 Sat Apr 22 13:53:45 2006 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue May 2 20:29:56 2006 @@ -1986,7 +1986,7 @@ // Otherwise, the target does not support this operation. Lower the // operation to an explicit libcall as appropriate. MVT::ValueType IntPtr = TLI.getPointerTy(); - const Type *IntPtrTy = TLI.getTargetData().getIntPtrType(); + const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType(); std::vector > Args; const char *FnName = 0; @@ -2781,8 +2781,8 @@ // slots and always reusing the same one. We currently always create // new ones, as reuse may inhibit scheduling. const Type *Ty = MVT::getTypeForValueType(ExtraVT); - unsigned TySize = (unsigned)TLI.getTargetData().getTypeSize(Ty); - unsigned Align = TLI.getTargetData().getTypeAlignment(Ty); + unsigned TySize = (unsigned)TLI.getTargetData()->getTypeSize(Ty); + unsigned Align = TLI.getTargetData()->getTypeAlignment(Ty); MachineFunction &MF = DAG.getMachineFunction(); int SSFI = MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align); Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.82 llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.83 --- llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.82 Sat Apr 22 13:53:45 2006 +++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Tue May 2 20:29:56 2006 @@ -130,10 +130,10 @@ Align = 3; // always 8-byte align doubles. else { Align = TM.getTargetData() - .getTypeAlignmentShift(CP->get()->getType()); + ->getTypeAlignmentShift(CP->get()->getType()); if (Align == 0) { // Alignment of packed types. FIXME! - Align = TM.getTargetData().getTypeSize(CP->get()->getType()); + Align = TM.getTargetData()->getTypeSize(CP->get()->getType()); Align = Log2_64(Align); } } Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.231 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.232 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.231 Fri Apr 28 13:54:11 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue May 2 20:29:56 2006 @@ -225,9 +225,9 @@ if (AllocaInst *AI = dyn_cast(I)) if (ConstantUInt *CUI = dyn_cast(AI->getArraySize())) { const Type *Ty = AI->getAllocatedType(); - uint64_t TySize = TLI.getTargetData().getTypeSize(Ty); + uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty); unsigned Align = - std::max((unsigned)TLI.getTargetData().getTypeAlignment(Ty), + std::max((unsigned)TLI.getTargetData()->getTypeAlignment(Ty), AI->getAlignment()); // If the alignment of the value is smaller than the size of the value, @@ -394,7 +394,7 @@ // implemented with a libcall, etc. TargetLowering &TLI; SelectionDAG &DAG; - const TargetData &TD; + const TargetData *TD; /// SwitchCases - Vector of CaseBlock structures used to communicate /// SwitchInst code generation information. @@ -1202,7 +1202,7 @@ void SelectionDAGLowering::visitGetElementPtr(User &I) { SDOperand N = getValue(I.getOperand(0)); const Type *Ty = I.getOperand(0)->getType(); - const Type *UIntPtrTy = TD.getIntPtrType(); + const Type *UIntPtrTy = TD->getIntPtrType(); for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end(); OI != E; ++OI) { @@ -1211,7 +1211,7 @@ unsigned Field = cast(Idx)->getValue(); if (Field) { // N = N + Offset - uint64_t Offset = TD.getStructLayout(StTy)->MemberOffsets[Field]; + uint64_t Offset = TD->getStructLayout(StTy)->MemberOffsets[Field]; N = DAG.getNode(ISD::ADD, N.getValueType(), N, getIntPtrConstant(Offset)); } @@ -1225,15 +1225,15 @@ uint64_t Offs; if (ConstantSInt *CSI = dyn_cast(CI)) - Offs = (int64_t)TD.getTypeSize(Ty)*CSI->getValue(); + Offs = (int64_t)TD->getTypeSize(Ty)*CSI->getValue(); else - Offs = TD.getTypeSize(Ty)*cast(CI)->getValue(); + Offs = TD->getTypeSize(Ty)*cast(CI)->getValue(); N = DAG.getNode(ISD::ADD, N.getValueType(), N, getIntPtrConstant(Offs)); continue; } // N = N + Idx * ElementSize; - uint64_t ElementSize = TD.getTypeSize(Ty); + uint64_t ElementSize = TD->getTypeSize(Ty); SDOperand IdxN = getValue(Idx); // If the index is smaller or larger than intptr_t, truncate or extend @@ -1271,8 +1271,8 @@ return; // getValue will auto-populate this. const Type *Ty = I.getAllocatedType(); - uint64_t TySize = TLI.getTargetData().getTypeSize(Ty); - unsigned Align = std::max((unsigned)TLI.getTargetData().getTypeAlignment(Ty), + uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty); + unsigned Align = std::max((unsigned)TLI.getTargetData()->getTypeAlignment(Ty), I.getAlignment()); SDOperand AllocSize = getValue(I.getArraySize()); @@ -2267,12 +2267,12 @@ Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src); // Scale the source by the type size. - uint64_t ElementSize = TD.getTypeSize(I.getType()->getElementType()); + uint64_t ElementSize = TD->getTypeSize(I.getType()->getElementType()); Src = DAG.getNode(ISD::MUL, Src.getValueType(), Src, getIntPtrConstant(ElementSize)); std::vector > Args; - Args.push_back(std::make_pair(Src, TLI.getTargetData().getIntPtrType())); + Args.push_back(std::make_pair(Src, TLI.getTargetData()->getIntPtrType())); std::pair Result = TLI.LowerCallTo(getRoot(), I.getType(), false, CallingConv::C, true, @@ -2285,7 +2285,7 @@ void SelectionDAGLowering::visitFree(FreeInst &I) { std::vector > Args; Args.push_back(std::make_pair(getValue(I.getOperand(0)), - TLI.getTargetData().getIntPtrType())); + TLI.getTargetData()->getIntPtrType())); MVT::ValueType IntPtr = TLI.getPointerTy(); std::pair Result = TLI.LowerCallTo(getRoot(), Type::VoidTy, false, CallingConv::C, true, @@ -2766,7 +2766,7 @@ /// stores that use it. In this case, decompose the GEP and move constant /// indices into blocks that use it. static void OptimizeGEPExpression(GetElementPtrInst *GEPI, - const TargetData &TD) { + const TargetData *TD) { // If this GEP is only used inside the block it is defined in, there is no // need to rewrite it. bool isUsedOutsideDefBB = false; @@ -2797,7 +2797,7 @@ // Otherwise, decompose the GEP instruction into multiplies and adds. Sum the // constant offset (which we now know is non-zero) and deal with it later. uint64_t ConstantOffset = 0; - const Type *UIntPtrTy = TD.getIntPtrType(); + const Type *UIntPtrTy = TD->getIntPtrType(); Value *Ptr = new CastInst(GEPI->getOperand(0), UIntPtrTy, "", GEPI); const Type *Ty = GEPI->getOperand(0)->getType(); @@ -2807,7 +2807,7 @@ if (const StructType *StTy = dyn_cast(Ty)) { unsigned Field = cast(Idx)->getValue(); if (Field) - ConstantOffset += TD.getStructLayout(StTy)->MemberOffsets[Field]; + ConstantOffset += TD->getStructLayout(StTy)->MemberOffsets[Field]; Ty = StTy->getElementType(Field); } else { Ty = cast(Ty)->getElementType(); @@ -2817,9 +2817,9 @@ if (CI->getRawValue() == 0) continue; if (ConstantSInt *CSI = dyn_cast(CI)) - ConstantOffset += (int64_t)TD.getTypeSize(Ty)*CSI->getValue(); + ConstantOffset += (int64_t)TD->getTypeSize(Ty)*CSI->getValue(); else - ConstantOffset+=TD.getTypeSize(Ty)*cast(CI)->getValue(); + ConstantOffset+=TD->getTypeSize(Ty)*cast(CI)->getValue(); continue; } @@ -2828,7 +2828,7 @@ // Cast Idx to UIntPtrTy if needed. Idx = new CastInst(Idx, UIntPtrTy, "", GEPI); - uint64_t ElementSize = TD.getTypeSize(Ty); + uint64_t ElementSize = TD->getTypeSize(Ty); // Mask off bits that should not be set. ElementSize &= ~0ULL >> (64-UIntPtrTy->getPrimitiveSizeInBits()); Constant *SizeCst = ConstantUInt::get(UIntPtrTy, ElementSize); From resistor at mac.com Tue May 2 20:30:21 2006 From: resistor at mac.com (Owen Anderson) Date: Tue, 2 May 2006 20:30:21 -0500 Subject: [llvm-commits] CVS: llvm/lib/ExecutionEngine/JIT/JIT.cpp JITEmitter.cpp Message-ID: <200605030130.UAA30385@zion.cs.uiuc.edu> Changes in directory llvm/lib/ExecutionEngine/JIT: JIT.cpp updated: 1.62 -> 1.63 JITEmitter.cpp updated: 1.93 -> 1.94 --- Log message: Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference. This fixes PR 759: http://llvm.cs.uiuc.edu/PR759 . --- Diffs of the changes: (+3 -3) JIT.cpp | 4 ++-- JITEmitter.cpp | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) Index: llvm/lib/ExecutionEngine/JIT/JIT.cpp diff -u llvm/lib/ExecutionEngine/JIT/JIT.cpp:1.62 llvm/lib/ExecutionEngine/JIT/JIT.cpp:1.63 --- llvm/lib/ExecutionEngine/JIT/JIT.cpp:1.62 Tue May 2 16:57:51 2006 +++ llvm/lib/ExecutionEngine/JIT/JIT.cpp Tue May 2 20:29:56 2006 @@ -302,8 +302,8 @@ // actually initialize the global after current function has finished // compilation. const Type *GlobalType = GV->getType()->getElementType(); - size_t S = getTargetData().getTypeSize(GlobalType); - size_t A = getTargetData().getTypeAlignment(GlobalType); + size_t S = getTargetData()->getTypeSize(GlobalType); + size_t A = getTargetData()->getTypeAlignment(GlobalType); if (A <= 8) { Ptr = malloc(S); } else { Index: llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp diff -u llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.93 llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.94 --- llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.93 Tue May 2 20:03:20 2006 +++ llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp Tue May 2 20:29:56 2006 @@ -518,7 +518,7 @@ if (Constants.empty()) return; unsigned Size = Constants.back().Offset; - Size += TheJIT->getTargetData().getTypeSize(Constants.back().Val->getType()); + Size += TheJIT->getTargetData()->getTypeSize(Constants.back().Val->getType()); ConstantPoolBase = allocateSpace(Size, 1 << MCP->getConstantPoolAlignment()); ConstantPool = MCP; From resistor at mac.com Tue May 2 20:30:21 2006 From: resistor at mac.com (Owen Anderson) Date: Tue, 2 May 2006 20:30:21 -0500 Subject: [llvm-commits] CVS: llvm/lib/ExecutionEngine/Interpreter/Interpreter.cpp Message-ID: <200605030130.UAA30346@zion.cs.uiuc.edu> Changes in directory llvm/lib/ExecutionEngine/Interpreter: Interpreter.cpp updated: 1.29 -> 1.30 --- Log message: Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference. This fixes PR 759: http://llvm.cs.uiuc.edu/PR759 . --- Diffs of the changes: (+1 -1) Interpreter.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/ExecutionEngine/Interpreter/Interpreter.cpp diff -u llvm/lib/ExecutionEngine/Interpreter/Interpreter.cpp:1.29 llvm/lib/ExecutionEngine/Interpreter/Interpreter.cpp:1.30 --- llvm/lib/ExecutionEngine/Interpreter/Interpreter.cpp:1.29 Thu Mar 23 20:53:49 2006 +++ llvm/lib/ExecutionEngine/Interpreter/Interpreter.cpp Tue May 2 20:29:56 2006 @@ -71,7 +71,7 @@ isLongPointer ? 8 : 4) { memset(&ExitValue, 0, sizeof(ExitValue)); - setTargetData(TD); + setTargetData(&TD); // Initialize the "backend" initializeExecutionEngine(); initializeExternalFunctions(); From resistor at mac.com Tue May 2 20:30:21 2006 From: resistor at mac.com (Owen Anderson) Date: Tue, 2 May 2006 20:30:21 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp PPCTargetMachine.cpp PPCTargetMachine.h Message-ID: <200605030130.UAA30337@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCAsmPrinter.cpp updated: 1.166 -> 1.167 PPCTargetMachine.cpp updated: 1.88 -> 1.89 PPCTargetMachine.h updated: 1.18 -> 1.19 --- Log message: Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference. This fixes PR 759: http://llvm.cs.uiuc.edu/PR759 . --- Diffs of the changes: (+10 -7) PPCAsmPrinter.cpp | 12 ++++++------ PPCTargetMachine.cpp | 3 ++- PPCTargetMachine.h | 2 ++ 3 files changed, 10 insertions(+), 7 deletions(-) Index: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp diff -u llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.166 llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.167 --- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.166 Tue May 2 12:34:51 2006 +++ llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp Tue May 2 20:29:57 2006 @@ -582,7 +582,7 @@ } bool DarwinAsmPrinter::doFinalization(Module &M) { - const TargetData &TD = TM.getTargetData(); + const TargetData *TD = TM.getTargetData(); // Print out module-level global variables here. for (Module::const_global_iterator I = M.global_begin(), E = M.global_end(); @@ -595,7 +595,7 @@ std::string name = Mang->getValueName(I); Constant *C = I->getInitializer(); - unsigned Size = TD.getTypeSize(C->getType()); + unsigned Size = TD->getTypeSize(C->getType()); unsigned Align = getPreferredAlignmentLog(I); if (C->isNullValue() && /* FIXME: Verify correct */ @@ -761,7 +761,7 @@ bool AIXAsmPrinter::doInitialization(Module &M) { SwitchSection("", 0); - const TargetData &TD = TM.getTargetData(); + const TargetData *TD = TM.getTargetData(); O << "\t.machine \"ppc64\"\n" << "\t.toc\n" @@ -810,7 +810,7 @@ } bool AIXAsmPrinter::doFinalization(Module &M) { - const TargetData &TD = TM.getTargetData(); + const TargetData *TD = TM.getTargetData(); // Print out module-level global variables for (Module::const_global_iterator I = M.global_begin(), E = M.global_end(); I != E; ++I) { @@ -821,8 +821,8 @@ if (I->hasInternalLinkage()) { O << "\t.lcomm " << Name << ",16,_global.bss_c"; } else { - O << "\t.comm " << Name << "," << TD.getTypeSize(I->getType()) - << "," << Log2_32((unsigned)TD.getTypeAlignment(I->getType())); + O << "\t.comm " << Name << "," << TD->getTypeSize(I->getType()) + << "," << Log2_32((unsigned)TD->getTypeAlignment(I->getType())); } O << "\t\t" << CommentString << " "; WriteAsOperand(O, I, false, true, &M); Index: llvm/lib/Target/PowerPC/PPCTargetMachine.cpp diff -u llvm/lib/Target/PowerPC/PPCTargetMachine.cpp:1.88 llvm/lib/Target/PowerPC/PPCTargetMachine.cpp:1.89 --- llvm/lib/Target/PowerPC/PPCTargetMachine.cpp:1.88 Fri Apr 21 17:11:27 2006 +++ llvm/lib/Target/PowerPC/PPCTargetMachine.cpp Tue May 2 20:29:57 2006 @@ -58,7 +58,8 @@ } PPCTargetMachine::PPCTargetMachine(const Module &M, const std::string &FS) -: TargetMachine("PowerPC", false, 4, 4, 4, 4, 4, 4, 2, 1, 1), +: TargetMachine("PowerPC"), + DataLayout("PowerPC", false, 4, 4, 4, 4, 4), Subtarget(M, FS), FrameInfo(*this, false), JITInfo(*this), TLInfo(*this), InstrItins(Subtarget.getInstrItineraryData()) { if (TargetDefault == PPCTarget) { Index: llvm/lib/Target/PowerPC/PPCTargetMachine.h diff -u llvm/lib/Target/PowerPC/PPCTargetMachine.h:1.18 llvm/lib/Target/PowerPC/PPCTargetMachine.h:1.19 --- llvm/lib/Target/PowerPC/PPCTargetMachine.h:1.18 Wed Mar 22 23:43:15 2006 +++ llvm/lib/Target/PowerPC/PPCTargetMachine.h Tue May 2 20:29:57 2006 @@ -26,6 +26,7 @@ class GlobalValue; class PPCTargetMachine : public TargetMachine { + const TargetData DataLayout; // Calculates type size & alignment PPCInstrInfo InstrInfo; PPCSubtarget Subtarget; PPCFrameInfo FrameInfo; @@ -43,6 +44,7 @@ virtual const MRegisterInfo *getRegisterInfo() const { return &InstrInfo.getRegisterInfo(); } + virtual const TargetData *getTargetData() const { return &DataLayout; } virtual const InstrItineraryData getInstrItineraryData() const { return InstrItins; } From resistor at mac.com Tue May 2 20:30:21 2006 From: resistor at mac.com (Owen Anderson) Date: Tue, 2 May 2006 20:30:21 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp TargetMachine.cpp Message-ID: <200605030130.UAA30353@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target: TargetLowering.cpp updated: 1.53 -> 1.54 TargetMachine.cpp updated: 1.43 -> 1.44 --- Log message: Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference. This fixes PR 759: http://llvm.cs.uiuc.edu/PR759 . --- Diffs of the changes: (+3 -17) TargetLowering.cpp | 4 ++-- TargetMachine.cpp | 16 +--------------- 2 files changed, 3 insertions(+), 17 deletions(-) Index: llvm/lib/Target/TargetLowering.cpp diff -u llvm/lib/Target/TargetLowering.cpp:1.53 llvm/lib/Target/TargetLowering.cpp:1.54 --- llvm/lib/Target/TargetLowering.cpp:1.53 Sun Apr 2 00:19:46 2006 +++ llvm/lib/Target/TargetLowering.cpp Tue May 2 20:29:56 2006 @@ -27,8 +27,8 @@ // All operations default to being supported. memset(OpActions, 0, sizeof(OpActions)); - IsLittleEndian = TD.isLittleEndian(); - ShiftAmountTy = SetCCResultTy = PointerTy = getValueType(TD.getIntPtrType()); + IsLittleEndian = TD->isLittleEndian(); + ShiftAmountTy = SetCCResultTy = PointerTy = getValueType(TD->getIntPtrType()); ShiftAmtHandling = Undefined; memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); memset(TargetDAGCombineArray, 0, Index: llvm/lib/Target/TargetMachine.cpp diff -u llvm/lib/Target/TargetMachine.cpp:1.43 llvm/lib/Target/TargetMachine.cpp:1.44 --- llvm/lib/Target/TargetMachine.cpp:1.43 Wed Mar 22 23:43:15 2006 +++ llvm/lib/Target/TargetMachine.cpp Tue May 2 20:29:56 2006 @@ -69,23 +69,9 @@ //--------------------------------------------------------------------------- // TargetMachine Class // -TargetMachine::TargetMachine(const std::string &name, bool LittleEndian, - unsigned char PtrSize, unsigned char PtrAl, - unsigned char DoubleAl, unsigned char FloatAl, - unsigned char LongAl, unsigned char IntAl, - unsigned char ShortAl, unsigned char ByteAl, - unsigned char BoolAl) - : Name(name), DataLayout(name, LittleEndian, - PtrSize, PtrAl, DoubleAl, FloatAl, LongAl, - IntAl, ShortAl, ByteAl, BoolAl) { -} - -TargetMachine::TargetMachine(const std::string &name, const TargetData &TD) - : Name(name), DataLayout(TD) { -} TargetMachine::TargetMachine(const std::string &name, const Module &M) - : Name(name), DataLayout(name, &M) { + : Name(name) { } TargetMachine::~TargetMachine() { From resistor at mac.com Tue May 2 20:30:22 2006 From: resistor at mac.com (Owen Anderson) Date: Tue, 2 May 2006 20:30:22 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcAsmPrinter.cpp SparcTargetMachine.cpp SparcTargetMachine.h Message-ID: <200605030130.UAA30419@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Sparc: SparcAsmPrinter.cpp updated: 1.59 -> 1.60 SparcTargetMachine.cpp updated: 1.44 -> 1.45 SparcTargetMachine.h updated: 1.12 -> 1.13 --- Log message: Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference. This fixes PR 759: http://llvm.cs.uiuc.edu/PR759 . --- Diffs of the changes: (+9 -7) SparcAsmPrinter.cpp | 10 +++++----- SparcTargetMachine.cpp | 3 ++- SparcTargetMachine.h | 3 ++- 3 files changed, 9 insertions(+), 7 deletions(-) Index: llvm/lib/Target/Sparc/SparcAsmPrinter.cpp diff -u llvm/lib/Target/Sparc/SparcAsmPrinter.cpp:1.59 llvm/lib/Target/Sparc/SparcAsmPrinter.cpp:1.60 --- llvm/lib/Target/Sparc/SparcAsmPrinter.cpp:1.59 Tue May 2 00:37:32 2006 +++ llvm/lib/Target/Sparc/SparcAsmPrinter.cpp Tue May 2 20:29:57 2006 @@ -232,7 +232,7 @@ } bool SparcAsmPrinter::doFinalization(Module &M) { - const TargetData &TD = TM.getTargetData(); + const TargetData *TD = TM.getTargetData(); // Print out module-level global variables here. for (Module::const_global_iterator I = M.global_begin(), E = M.global_end(); @@ -245,8 +245,8 @@ O << "\n\n"; std::string name = Mang->getValueName(I); Constant *C = I->getInitializer(); - unsigned Size = TD.getTypeSize(C->getType()); - unsigned Align = TD.getTypeAlignment(C->getType()); + unsigned Size = TD->getTypeSize(C->getType()); + unsigned Align = TD->getTypeAlignment(C->getType()); if (C->isNullValue() && (I->hasLinkOnceLinkage() || I->hasInternalLinkage() || @@ -255,8 +255,8 @@ if (I->hasInternalLinkage()) O << "\t.local " << name << "\n"; - O << "\t.comm " << name << "," << TD.getTypeSize(C->getType()) - << "," << (unsigned)TD.getTypeAlignment(C->getType()); + O << "\t.comm " << name << "," << TD->getTypeSize(C->getType()) + << "," << (unsigned)TD->getTypeAlignment(C->getType()); O << "\t\t! "; WriteAsOperand(O, I, true, true, &M); O << "\n"; Index: llvm/lib/Target/Sparc/SparcTargetMachine.cpp diff -u llvm/lib/Target/Sparc/SparcTargetMachine.cpp:1.44 llvm/lib/Target/Sparc/SparcTargetMachine.cpp:1.45 --- llvm/lib/Target/Sparc/SparcTargetMachine.cpp:1.44 Sat Apr 8 14:46:55 2006 +++ llvm/lib/Target/Sparc/SparcTargetMachine.cpp Tue May 2 20:29:57 2006 @@ -31,7 +31,8 @@ /// SparcTargetMachine ctor - Create an ILP32 architecture model /// SparcTargetMachine::SparcTargetMachine(const Module &M, const std::string &FS) - : TargetMachine("Sparc", false, 4, 4), + : TargetMachine("Sparc"), + DataLayout("Sparc", false, 4, 4), Subtarget(M, FS), InstrInfo(Subtarget), FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0) { } Index: llvm/lib/Target/Sparc/SparcTargetMachine.h diff -u llvm/lib/Target/Sparc/SparcTargetMachine.h:1.12 llvm/lib/Target/Sparc/SparcTargetMachine.h:1.13 --- llvm/lib/Target/Sparc/SparcTargetMachine.h:1.12 Wed Mar 22 23:43:15 2006 +++ llvm/lib/Target/Sparc/SparcTargetMachine.h Tue May 2 20:29:57 2006 @@ -25,6 +25,7 @@ class Module; class SparcTargetMachine : public TargetMachine { + const TargetData DataLayout; // Calculates type size & alignment SparcSubtarget Subtarget; SparcInstrInfo InstrInfo; TargetFrameInfo FrameInfo; @@ -37,7 +38,7 @@ virtual const MRegisterInfo *getRegisterInfo() const { return &InstrInfo.getRegisterInfo(); } - + virtual const TargetData *getTargetData() const { return &DataLayout; } static unsigned getModuleMatchQuality(const Module &M); virtual bool addPassesToEmitFile(PassManager &PM, std::ostream &Out, From resistor at mac.com Tue May 2 20:30:22 2006 From: resistor at mac.com (Owen Anderson) Date: Tue, 2 May 2006 20:30:22 -0500 Subject: [llvm-commits] CVS: llvm/tools/llc/llc.cpp Message-ID: <200605030130.UAA30403@zion.cs.uiuc.edu> Changes in directory llvm/tools/llc: llc.cpp updated: 1.130 -> 1.131 --- Log message: Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference. This fixes PR 759: http://llvm.cs.uiuc.edu/PR759 . --- Diffs of the changes: (+1 -1) llc.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/tools/llc/llc.cpp diff -u llvm/tools/llc/llc.cpp:1.130 llvm/tools/llc/llc.cpp:1.131 --- llvm/tools/llc/llc.cpp:1.130 Tue Apr 18 00:31:20 2006 +++ llvm/tools/llc/llc.cpp Tue May 2 20:29:57 2006 @@ -143,7 +143,7 @@ std::auto_ptr target(MArch->CtorFn(mod, FeaturesStr)); assert(target.get() && "Could not allocate target machine!"); TargetMachine &Target = *target.get(); - const TargetData &TD = Target.getTargetData(); + const TargetData *TD = Target.getTargetData(); // Build up all of the passes that we want to do to the module... PassManager Passes; From resistor at mac.com Tue May 2 20:30:22 2006 From: resistor at mac.com (Owen Anderson) Date: Tue, 2 May 2006 20:30:22 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/IA64/IA64AsmPrinter.cpp IA64TargetMachine.cpp IA64TargetMachine.h Message-ID: <200605030130.UAA30421@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/IA64: IA64AsmPrinter.cpp updated: 1.27 -> 1.28 IA64TargetMachine.cpp updated: 1.14 -> 1.15 IA64TargetMachine.h updated: 1.7 -> 1.8 --- Log message: Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference. This fixes PR 759: http://llvm.cs.uiuc.edu/PR759 . --- Diffs of the changes: (+8 -6) IA64AsmPrinter.cpp | 10 +++++----- IA64TargetMachine.cpp | 2 +- IA64TargetMachine.h | 2 ++ 3 files changed, 8 insertions(+), 6 deletions(-) Index: llvm/lib/Target/IA64/IA64AsmPrinter.cpp diff -u llvm/lib/Target/IA64/IA64AsmPrinter.cpp:1.27 llvm/lib/Target/IA64/IA64AsmPrinter.cpp:1.28 --- llvm/lib/Target/IA64/IA64AsmPrinter.cpp:1.27 Tue May 2 00:37:32 2006 +++ llvm/lib/Target/IA64/IA64AsmPrinter.cpp Tue May 2 20:29:57 2006 @@ -277,7 +277,7 @@ } bool IA64AsmPrinter::doFinalization(Module &M) { - const TargetData &TD = TM.getTargetData(); + const TargetData *TD = TM.getTargetData(); // Print out module-level global variables here. for (Module::const_global_iterator I = M.global_begin(), E = M.global_end(); @@ -290,19 +290,19 @@ O << "\n\n"; std::string name = Mang->getValueName(I); Constant *C = I->getInitializer(); - unsigned Size = TD.getTypeSize(C->getType()); - unsigned Align = TD.getTypeAlignmentShift(C->getType()); + unsigned Size = TD->getTypeSize(C->getType()); + unsigned Align = TD->getTypeAlignmentShift(C->getType()); if (C->isNullValue() && (I->hasLinkOnceLinkage() || I->hasInternalLinkage() || I->hasWeakLinkage() /* FIXME: Verify correct */)) { SwitchSection(".data", I); if (I->hasInternalLinkage()) { - O << "\t.lcomm " << name << "#," << TD.getTypeSize(C->getType()) + O << "\t.lcomm " << name << "#," << TD->getTypeSize(C->getType()) << "," << (1 << Align); O << "\t\t// "; } else { - O << "\t.common " << name << "#," << TD.getTypeSize(C->getType()) + O << "\t.common " << name << "#," << TD->getTypeSize(C->getType()) << "," << (1 << Align); O << "\t\t// "; } Index: llvm/lib/Target/IA64/IA64TargetMachine.cpp diff -u llvm/lib/Target/IA64/IA64TargetMachine.cpp:1.14 llvm/lib/Target/IA64/IA64TargetMachine.cpp:1.15 --- llvm/lib/Target/IA64/IA64TargetMachine.cpp:1.14 Sat Apr 8 14:46:55 2006 +++ llvm/lib/Target/IA64/IA64TargetMachine.cpp Tue May 2 20:29:57 2006 @@ -76,7 +76,7 @@ /// IA64TargetMachine ctor - Create an LP64 architecture model /// IA64TargetMachine::IA64TargetMachine(const Module &M, const std::string &FS) - : TargetMachine("IA64", true), + : TargetMachine("IA64"), DataLayout("IA64", true), FrameInfo(TargetFrameInfo::StackGrowsDown, 16, 0), TLInfo(*this) { // FIXME? check this stuff } Index: llvm/lib/Target/IA64/IA64TargetMachine.h diff -u llvm/lib/Target/IA64/IA64TargetMachine.h:1.7 llvm/lib/Target/IA64/IA64TargetMachine.h:1.8 --- llvm/lib/Target/IA64/IA64TargetMachine.h:1.7 Wed Mar 22 23:43:15 2006 +++ llvm/lib/Target/IA64/IA64TargetMachine.h Tue May 2 20:29:57 2006 @@ -23,6 +23,7 @@ namespace llvm { class IA64TargetMachine : public TargetMachine { + const TargetData DataLayout; // Calculates type size & alignment IA64InstrInfo InstrInfo; TargetFrameInfo FrameInfo; //IA64JITInfo JITInfo; @@ -36,6 +37,7 @@ virtual const MRegisterInfo *getRegisterInfo() const { return &InstrInfo.getRegisterInfo(); } + virtual const TargetData *getTargetData() const { return &DataLayout; } virtual bool addPassesToEmitFile(PassManager &PM, std::ostream &Out, CodeGenFileType FileType, bool Fast); From natebegeman at mac.com Tue May 2 23:52:59 2006 From: natebegeman at mac.com (Nate Begeman) Date: Tue, 2 May 2006 23:52:59 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86CodeEmitter.cpp Message-ID: <200605030452.XAA00897@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86CodeEmitter.cpp updated: 1.99 -> 1.100 --- Log message: Teach the x86 jit how to handle jump tables not directly used by a jump instruction. --- Diffs of the changes: (+3 -0) X86CodeEmitter.cpp | 3 +++ 1 files changed, 3 insertions(+) Index: llvm/lib/Target/X86/X86CodeEmitter.cpp diff -u llvm/lib/Target/X86/X86CodeEmitter.cpp:1.99 llvm/lib/Target/X86/X86CodeEmitter.cpp:1.100 --- llvm/lib/Target/X86/X86CodeEmitter.cpp:1.99 Tue May 2 19:28:15 2006 +++ llvm/lib/Target/X86/X86CodeEmitter.cpp Tue May 2 23:52:47 2006 @@ -517,6 +517,9 @@ else if (MI.getOperand(4).isGlobalAddress()) emitGlobalAddressForPtr(MI.getOperand(4).getGlobal(), MI.getOperand(4).getOffset()); + else if (MI.getOperand(4).isJumpTableIndex()) + emitConstant(MCE.getJumpTableEntryAddress(MI.getOperand(4) + .getJumpTableIndex()), 4); else assert(0 && "Unknown operand!"); } From lattner at cs.uiuc.edu Wed May 3 00:48:53 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 3 May 2006 00:48:53 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/CBackend/CTargetMachine.h Message-ID: <200605030548.AAA01350@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/CBackend: CTargetMachine.h updated: 1.11 -> 1.12 --- Log message: Fix a bug in Owen's checkin that broke the CBE on all non sparc v9 platforms. --- Diffs of the changes: (+1 -1) CTargetMachine.h | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/CBackend/CTargetMachine.h diff -u llvm/lib/Target/CBackend/CTargetMachine.h:1.11 llvm/lib/Target/CBackend/CTargetMachine.h:1.12 --- llvm/lib/Target/CBackend/CTargetMachine.h:1.11 Tue May 2 20:29:57 2006 +++ llvm/lib/Target/CBackend/CTargetMachine.h Wed May 3 00:48:41 2006 @@ -23,7 +23,7 @@ CTargetMachine(const Module &M, const std::string &FS) : TargetMachine("CBackend", M), - DataLayout("CBackend") {} + DataLayout("CBackend", &M) {} // This is the only thing that actually does anything here. virtual bool addPassesToEmitFile(PassManager &PM, std::ostream &Out, From lattner at cs.uiuc.edu Wed May 3 12:11:06 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 3 May 2006 12:11:06 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp Message-ID: <200605031711.MAA22301@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Alpha: AlphaCodeEmitter.cpp updated: 1.13 -> 1.14 --- Log message: Suck block address tracking out of targets into the JIT Emitter. This simplifies the MachineCodeEmitter interface just a little bit and makes BasicBlocks work like constant pools and jump tables. --- Diffs of the changes: (+4 -11) AlphaCodeEmitter.cpp | 15 ++++----------- 1 files changed, 4 insertions(+), 11 deletions(-) Index: llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp diff -u llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp:1.13 llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp:1.14 --- llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp:1.13 Tue May 2 19:31:21 2006 +++ llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp Wed May 3 12:10:41 2006 @@ -35,8 +35,7 @@ class AlphaCodeEmitter : public MachineFunctionPass { const AlphaInstrInfo *II; MachineCodeEmitter &MCE; - std::vector BasicBlockAddrs; - std::vector > BBRefs; + std::vector > BBRefs; /// getMachineOpValue - evaluates the MachineOperand of a given MachineInstr /// @@ -78,7 +77,6 @@ do { BBRefs.clear(); - BasicBlockAddrs.clear(); MCE.startFunction(MF); for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) @@ -87,7 +85,8 @@ // Resolve all forward branches now... for (unsigned i = 0, e = BBRefs.size(); i != e; ++i) { - unsigned* Location = BasicBlockAddrs[BBRefs[i].first->getNumber()]; + unsigned* Location = + (unsigned*)MCE.getMachineBasicBlockAddress(BBRefs[i].first); unsigned* Ref = (unsigned*)BBRefs[i].second; intptr_t BranchTargetDisp = (((unsigned char*)Location - (unsigned char*)Ref) >> 2) - 1; @@ -97,17 +96,11 @@ *Ref |= (BranchTargetDisp & ((1 << 21)-1)); } BBRefs.clear(); - BasicBlockAddrs.clear(); - return false; } void AlphaCodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) { - if (BasicBlockAddrs.size() <= (unsigned)MBB.getNumber()) - BasicBlockAddrs.resize((MBB.getNumber()+1)*2); - - BasicBlockAddrs[MBB.getNumber()] = (unsigned*)MCE.getCurrentPCValue(); - + MCE.StartMachineBasicBlock(&MBB); for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I) { MachineInstr &MI = *I; From lattner at cs.uiuc.edu Wed May 3 12:11:06 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 3 May 2006 12:11:06 -0500 Subject: [llvm-commits] CVS: llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp Message-ID: <200605031711.MAA22302@zion.cs.uiuc.edu> Changes in directory llvm/lib/ExecutionEngine/JIT: JITEmitter.cpp updated: 1.94 -> 1.95 --- Log message: Suck block address tracking out of targets into the JIT Emitter. This simplifies the MachineCodeEmitter interface just a little bit and makes BasicBlocks work like constant pools and jump tables. --- Diffs of the changes: (+29 -9) JITEmitter.cpp | 38 +++++++++++++++++++++++++++++--------- 1 files changed, 29 insertions(+), 9 deletions(-) Index: llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp diff -u llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.94 llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.95 --- llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.94 Tue May 2 20:29:56 2006 +++ llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp Wed May 3 12:10:41 2006 @@ -354,6 +354,11 @@ /// Relocations - These are the relocations that the function needs, as /// emitted. std::vector Relocations; + + /// MBBLocations - This vector is a mapping from MBB ID's to their address. + /// It is filled in by the StartMachineBasicBlock callback and queried by + /// the getMachineBasicBlockAddress callback. + std::vector MBBLocations; /// ConstantPool - The constant pool for the current function. /// @@ -381,8 +386,7 @@ void emitConstantPool(MachineConstantPool *MCP); void initJumpTableInfo(MachineJumpTableInfo *MJTI); - virtual void emitJumpTableInfo(MachineJumpTableInfo *MJTI, - std::vector &MBBM); + void emitJumpTableInfo(MachineJumpTableInfo *MJTI); virtual void startFunctionStub(unsigned StubSize); virtual void* finishFunctionStub(const Function *F); @@ -390,9 +394,22 @@ virtual void addRelocation(const MachineRelocation &MR) { Relocations.push_back(MR); } + + virtual void StartMachineBasicBlock(MachineBasicBlock *MBB) { + if (MBBLocations.size() <= (unsigned)MBB->getNumber()) + MBBLocations.resize((MBB->getNumber()+1)*2); + MBBLocations[MBB->getNumber()] = getCurrentPCValue(); + } + + virtual intptr_t getConstantPoolEntryAddress(unsigned Entry) const; + virtual intptr_t getJumpTableEntryAddress(unsigned Entry) const; + + virtual intptr_t getMachineBasicBlockAddress(MachineBasicBlock *MBB) const { + assert(MBBLocations.size() > (unsigned)MBB->getNumber() && + MBBLocations[MBB->getNumber()] && "MBB not emitted!"); + return MBBLocations[MBB->getNumber()]; + } - virtual uint64_t getConstantPoolEntryAddress(unsigned Entry); - virtual uint64_t getJumpTableEntryAddress(unsigned Entry); private: void *getPointerToGlobal(GlobalValue *GV, void *Reference, bool NoNeedStub); @@ -447,9 +464,13 @@ // About to start emitting the machine code for the function. emitAlignment(std::max(F.getFunction()->getAlignment(), 8U)); TheJIT->updateGlobalMapping(F.getFunction(), CurBufferPtr); + + MBBLocations.clear(); } bool JITEmitter::finishFunction(MachineFunction &F) { + emitJumpTableInfo(F.getJumpTableInfo()); + MemMgr.endFunctionBody(CurBufferPtr); NumBytes += getCurrentPCOffset(); @@ -549,8 +570,7 @@ JumpTableBase = allocateSpace(NumEntries * EntrySize, MJTI->getAlignment()); } -void JITEmitter::emitJumpTableInfo(MachineJumpTableInfo *MJTI, - std::vector &MBBM) { +void JITEmitter::emitJumpTableInfo(MachineJumpTableInfo *MJTI) { const std::vector &JT = MJTI->getJumpTables(); if (JT.empty() || JumpTableBase == 0) return; @@ -566,7 +586,7 @@ // Store the address of the basic block for this jump table slot in the // memory we allocated for the jump table in 'initJumpTableInfo' for (unsigned mi = 0, me = MBBs.size(); mi != me; ++mi) - *SlotPtr++ = (intptr_t)MBBM[MBBs[mi]->getNumber()]; + *SlotPtr++ = getMachineBasicBlockAddress(MBBs[mi]); } } @@ -591,7 +611,7 @@ // in the constant pool that was last emitted with the 'emitConstantPool' // method. // -uint64_t JITEmitter::getConstantPoolEntryAddress(unsigned ConstantNum) { +intptr_t JITEmitter::getConstantPoolEntryAddress(unsigned ConstantNum) const { assert(ConstantNum < ConstantPool->getConstants().size() && "Invalid ConstantPoolIndex!"); return (intptr_t)ConstantPoolBase + @@ -601,7 +621,7 @@ // getJumpTableEntryAddress - Return the address of the JumpTable with index // 'Index' in the jumpp table that was last initialized with 'initJumpTableInfo' // -uint64_t JITEmitter::getJumpTableEntryAddress(unsigned Index) { +intptr_t JITEmitter::getJumpTableEntryAddress(unsigned Index) const { const std::vector &JT = JumpTable->getJumpTables(); assert(Index < JT.size() && "Invalid jump table index!"); From lattner at cs.uiuc.edu Wed May 3 12:11:06 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 3 May 2006 12:11:06 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineCodeEmitter.h Message-ID: <200605031711.MAA22300@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineCodeEmitter.h updated: 1.39 -> 1.40 --- Log message: Suck block address tracking out of targets into the JIT Emitter. This simplifies the MachineCodeEmitter interface just a little bit and makes BasicBlocks work like constant pools and jump tables. --- Diffs of the changes: (+16 -10) MachineCodeEmitter.h | 26 ++++++++++++++++---------- 1 files changed, 16 insertions(+), 10 deletions(-) Index: llvm/include/llvm/CodeGen/MachineCodeEmitter.h diff -u llvm/include/llvm/CodeGen/MachineCodeEmitter.h:1.39 llvm/include/llvm/CodeGen/MachineCodeEmitter.h:1.40 --- llvm/include/llvm/CodeGen/MachineCodeEmitter.h:1.39 Tue May 2 20:01:51 2006 +++ llvm/include/llvm/CodeGen/MachineCodeEmitter.h Wed May 3 12:10:41 2006 @@ -74,13 +74,6 @@ /// virtual bool finishFunction(MachineFunction &F) = 0; - /// emitJumpTableInfo - This callback is invoked to output the jump tables - /// for the function. In addition to a pointer to the MachineJumpTableInfo, - /// this function also takes a map of MBB IDs to addresses, so that the final - /// addresses of the MBBs can be written to the jump tables. - virtual void emitJumpTableInfo(MachineJumpTableInfo *MJTI, - std::vector &MBBM) = 0; - /// startFunctionStub - This callback is invoked when the JIT needs the /// address of a function that has not been code generated yet. The StubSize /// specifies the total size required by the stub. Stubs are not allowed to @@ -158,7 +151,11 @@ } return Result; } - + + /// StartMachineBasicBlock - This should be called by the target when a new + /// basic block is about to be emitted. This way the MCE knows where the + /// start of the block is, and can implement getMachineBasicBlockAddress. + virtual void StartMachineBasicBlock(MachineBasicBlock *MBB) = 0; /// getCurrentPCValue - This returns the address that the next emitted byte /// will be output to. @@ -177,15 +174,24 @@ /// noted with this interface. virtual void addRelocation(const MachineRelocation &MR) = 0; + + /// FIXME: These should all be handled with relocations! + /// getConstantPoolEntryAddress - Return the address of the 'Index' entry in /// the constant pool that was last emitted with the emitConstantPool method. /// - virtual uint64_t getConstantPoolEntryAddress(unsigned Index) = 0; + virtual intptr_t getConstantPoolEntryAddress(unsigned Index) const = 0; /// getJumpTableEntryAddress - Return the address of the jump table with index /// 'Index' in the function that last called initJumpTableInfo. /// - virtual uint64_t getJumpTableEntryAddress(unsigned Index) = 0; + virtual intptr_t getJumpTableEntryAddress(unsigned Index) const = 0; + + /// getMachineBasicBlockAddress - Return the address of the specified + /// MachineBasicBlock, only usable after the label for the MBB has been + /// emitted. + /// + virtual intptr_t getMachineBasicBlockAddress(MachineBasicBlock *MBB) const= 0; }; } // End llvm namespace From lattner at cs.uiuc.edu Wed May 3 12:11:06 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 3 May 2006 12:11:06 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp Message-ID: <200605031711.MAA22303@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCCodeEmitter.cpp updated: 1.57 -> 1.58 --- Log message: Suck block address tracking out of targets into the JIT Emitter. This simplifies the MachineCodeEmitter interface just a little bit and makes BasicBlocks work like constant pools and jump tables. --- Diffs of the changes: (+6 -12) PPCCodeEmitter.cpp | 18 ++++++------------ 1 files changed, 6 insertions(+), 12 deletions(-) Index: llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp diff -u llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp:1.57 llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp:1.58 --- llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp:1.57 Tue May 2 19:28:15 2006 +++ llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp Wed May 3 12:10:41 2006 @@ -33,9 +33,7 @@ // Tracks which instruction references which BasicBlock std::vector > BBRefs; - // Tracks where each BasicBlock starts, indexes by BB number. - std::vector BasicBlockAddrs; - + /// getMachineOpValue - evaluates the MachineOperand of a given MachineInstr /// int getMachineOpValue(MachineInstr &MI, MachineOperand &MO); @@ -87,17 +85,15 @@ "JIT relocation model must be set to static or default!"); do { BBRefs.clear(); - BasicBlockAddrs.clear(); MCE.startFunction(MF); for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB) emitBasicBlock(*BB); - MCE.emitJumpTableInfo(MF.getJumpTableInfo(), BasicBlockAddrs); } while (MCE.finishFunction(MF)); // Resolve branches to BasicBlocks for the entire function for (unsigned i = 0, e = BBRefs.size(); i != e; ++i) { - intptr_t Location = BasicBlockAddrs[BBRefs[i].first->getNumber()]; + intptr_t Location = MCE.getMachineBasicBlockAddress(BBRefs[i].first); unsigned *Ref = BBRefs[i].second; DEBUG(std::cerr << "Fixup @ " << (void*)Ref << " to " << (void*)Location << "\n"); @@ -115,15 +111,13 @@ } } BBRefs.clear(); - BasicBlockAddrs.clear(); return false; } void PPCCodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) { - if (BasicBlockAddrs.size() <= (unsigned)MBB.getNumber()) - BasicBlockAddrs.resize((MBB.getNumber()+1)*2); - BasicBlockAddrs[MBB.getNumber()] = MCE.getCurrentPCValue(); + MCE.StartMachineBasicBlock(&MBB); + for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){ MachineInstr &MI = *I; unsigned Opcode = MI.getOpcode(); @@ -145,8 +139,8 @@ int PPCCodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) { - int rv = 0; // Return value; defaults to 0 for unhandled cases - // or things that get fixed up later by the JIT. + intptr_t rv = 0; // Return value; defaults to 0 for unhandled cases + // or things that get fixed up later by the JIT. if (MO.isRegister()) { rv = PPCRegisterInfo::getRegisterNumbering(MO.getReg()); From lattner at cs.uiuc.edu Wed May 3 12:11:06 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 3 May 2006 12:11:06 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/ELFWriter.cpp Message-ID: <200605031711.MAA22304@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: ELFWriter.cpp updated: 1.24 -> 1.25 --- Log message: Suck block address tracking out of targets into the JIT Emitter. This simplifies the MachineCodeEmitter interface just a little bit and makes BasicBlocks work like constant pools and jump tables. --- Diffs of the changes: (+9 -6) ELFWriter.cpp | 15 +++++++++------ 1 files changed, 9 insertions(+), 6 deletions(-) Index: llvm/lib/CodeGen/ELFWriter.cpp diff -u llvm/lib/CodeGen/ELFWriter.cpp:1.24 llvm/lib/CodeGen/ELFWriter.cpp:1.25 --- llvm/lib/CodeGen/ELFWriter.cpp:1.24 Tue May 2 20:29:56 2006 +++ llvm/lib/CodeGen/ELFWriter.cpp Wed May 3 12:10:41 2006 @@ -61,21 +61,24 @@ void addRelocation(const MachineRelocation &MR) { assert(0 && "relo not handled yet!"); } - virtual uint64_t getConstantPoolEntryAddress(unsigned Index) { + + virtual void StartMachineBasicBlock(MachineBasicBlock *MBB) { + } + + virtual intptr_t getConstantPoolEntryAddress(unsigned Index) const { assert(0 && "CP not implementated yet!"); return 0; } - virtual uint64_t getJumpTableEntryAddress(unsigned Index) { + virtual intptr_t getJumpTableEntryAddress(unsigned Index) const { assert(0 && "JT not implementated yet!"); return 0; } - - virtual void emitJumpTableInfo(MachineJumpTableInfo *MJTI, - std::vector &MBBM) { + + virtual intptr_t getMachineBasicBlockAddress(MachineBasicBlock *MBB) const { assert(0 && "JT not implementated yet!"); + return 0; } - /// JIT SPECIFIC FUNCTIONS - DO NOT IMPLEMENT THESE HERE! void startFunctionStub(unsigned StubSize) { assert(0 && "JIT specific function called!"); From lattner at cs.uiuc.edu Wed May 3 12:11:06 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 3 May 2006 12:11:06 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86CodeEmitter.cpp Message-ID: <200605031711.MAA22299@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86CodeEmitter.cpp updated: 1.100 -> 1.101 --- Log message: Suck block address tracking out of targets into the JIT Emitter. This simplifies the MachineCodeEmitter interface just a little bit and makes BasicBlocks work like constant pools and jump tables. --- Diffs of the changes: (+9 -24) X86CodeEmitter.cpp | 33 +++++++++------------------------ 1 files changed, 9 insertions(+), 24 deletions(-) Index: llvm/lib/Target/X86/X86CodeEmitter.cpp diff -u llvm/lib/Target/X86/X86CodeEmitter.cpp:1.100 llvm/lib/Target/X86/X86CodeEmitter.cpp:1.101 --- llvm/lib/Target/X86/X86CodeEmitter.cpp:1.100 Tue May 2 23:52:47 2006 +++ llvm/lib/Target/X86/X86CodeEmitter.cpp Wed May 3 12:10:41 2006 @@ -35,7 +35,6 @@ class Emitter : public MachineFunctionPass { const X86InstrInfo *II; MachineCodeEmitter &MCE; - std::vector BasicBlockAddrs; std::vector > BBRefs; public: explicit Emitter(MachineCodeEmitter &mce) : II(0), MCE(mce) {} @@ -83,30 +82,24 @@ do { BBRefs.clear(); - BasicBlockAddrs.clear(); MCE.startFunction(MF); for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) emitBasicBlock(*I); - MCE.emitJumpTableInfo(MF.getJumpTableInfo(), BasicBlockAddrs); } while (MCE.finishFunction(MF)); // Resolve all forward branches now. for (unsigned i = 0, e = BBRefs.size(); i != e; ++i) { - unsigned Location = BasicBlockAddrs[BBRefs[i].first->getNumber()]; + unsigned Location = MCE.getMachineBasicBlockAddress(BBRefs[i].first); unsigned Ref = BBRefs[i].second; *((unsigned*)(intptr_t)Ref) = Location-Ref-4; } BBRefs.clear(); - BasicBlockAddrs.clear(); return false; } void Emitter::emitBasicBlock(MachineBasicBlock &MBB) { - if (BasicBlockAddrs.size() <= (unsigned)MBB.getNumber()) - BasicBlockAddrs.resize((MBB.getNumber()+1)*2); - BasicBlockAddrs[MBB.getNumber()] = MCE.getCurrentPCValue(); - + MCE.StartMachineBasicBlock(&MBB); for (MachineBasicBlock::const_iterator I = MBB.begin(), E = MBB.end(); I != E; ++I) emitInstruction(*I); @@ -118,23 +111,15 @@ MCE.emitWordLE(Address-MCE.getCurrentPCValue()-4); } -/// emitPCRelativeBlockAddress - This method emits the PC relative address of -/// the specified basic block, or if the basic block hasn't been emitted yet -/// (because this is a forward branch), it keeps track of the information -/// necessary to resolve this address later (and emits a dummy value). +/// emitPCRelativeBlockAddress - This method keeps track of the information +/// necessary to resolve the address of this block later and emits a dummy +/// value. /// void Emitter::emitPCRelativeBlockAddress(MachineBasicBlock *MBB) { - // If this is a backwards branch, we already know the address of the target, - // so just emit the value. - unsigned MBBNo = MBB->getNumber(); - if (MBBNo < BasicBlockAddrs.size() && BasicBlockAddrs[MBBNo]) { - emitPCRelativeValue(BasicBlockAddrs[MBBNo]); - } else { - // Otherwise, remember where this reference was and where it is to so we can - // deal with it later. - BBRefs.push_back(std::make_pair(MBB, MCE.getCurrentPCValue())); - MCE.emitWordLE(0); - } + // Remember where this reference was and where it is to so we can + // deal with it later. + BBRefs.push_back(std::make_pair(MBB, MCE.getCurrentPCValue())); + MCE.emitWordLE(0); } /// emitGlobalAddressForCall - Emit the specified address to the code stream From lattner at cs.uiuc.edu Wed May 3 12:21:44 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 3 May 2006 12:21:44 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86CodeEmitter.cpp Message-ID: <200605031721.MAA22420@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86CodeEmitter.cpp updated: 1.101 -> 1.102 --- Log message: inline a simple method --- Diffs of the changes: (+7 -10) X86CodeEmitter.cpp | 17 +++++++---------- 1 files changed, 7 insertions(+), 10 deletions(-) Index: llvm/lib/Target/X86/X86CodeEmitter.cpp diff -u llvm/lib/Target/X86/X86CodeEmitter.cpp:1.101 llvm/lib/Target/X86/X86CodeEmitter.cpp:1.102 --- llvm/lib/Target/X86/X86CodeEmitter.cpp:1.101 Wed May 3 12:10:41 2006 +++ llvm/lib/Target/X86/X86CodeEmitter.cpp Wed May 3 12:21:32 2006 @@ -50,7 +50,6 @@ void emitInstruction(const MachineInstr &MI); private: - void emitBasicBlock(MachineBasicBlock &MBB); void emitPCRelativeBlockAddress(MachineBasicBlock *MBB); void emitPCRelativeValue(unsigned Address); void emitGlobalAddressForCall(GlobalValue *GV, bool isTailCall); @@ -84,8 +83,13 @@ BBRefs.clear(); MCE.startFunction(MF); - for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) - emitBasicBlock(*I); + for (MachineFunction::iterator MBB = MF.begin(), E = MF.end(); + MBB != E; ++MBB) { + MCE.StartMachineBasicBlock(MBB); + for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end(); + I != E; ++I) + emitInstruction(*I); + } } while (MCE.finishFunction(MF)); // Resolve all forward branches now. @@ -98,13 +102,6 @@ return false; } -void Emitter::emitBasicBlock(MachineBasicBlock &MBB) { - MCE.StartMachineBasicBlock(&MBB); - for (MachineBasicBlock::const_iterator I = MBB.begin(), E = MBB.end(); - I != E; ++I) - emitInstruction(*I); -} - /// emitPCRelativeValue - Emit a 32-bit PC relative address. /// void Emitter::emitPCRelativeValue(unsigned Address) { From reid at x10sys.com Wed May 3 12:50:02 2006 From: reid at x10sys.com (Reid Spencer) Date: Wed, 3 May 2006 12:50:02 -0500 Subject: [llvm-commits] CVS: llvm/tools/llvm-config/Makefile FinalLibDeps.txt LibDeps.txt Message-ID: <200605031750.MAA22575@zion.cs.uiuc.edu> Changes in directory llvm/tools/llvm-config: Makefile updated: 1.5 -> 1.6 FinalLibDeps.txt (r1.1) removed LibDeps.txt (r1.3) removed --- Log message: For PR764: http://llvm.cs.uiuc.edu/PR764 : Don't check in the LibDeps.txt and FinalLibDeps.txt files to CVS because the content differs from platform to platform. Instead, adjust the makefile so that a dummy llvm-config is built if Perl is not available. --- Diffs of the changes: (+21 -10) Makefile | 31 +++++++++++++++++++++---------- 1 files changed, 21 insertions(+), 10 deletions(-) Index: llvm/tools/llvm-config/Makefile diff -u llvm/tools/llvm-config/Makefile:1.5 llvm/tools/llvm-config/Makefile:1.6 --- llvm/tools/llvm-config/Makefile:1.5 Thu Apr 20 16:13:58 2006 +++ llvm/tools/llvm-config/Makefile Wed May 3 12:49:50 2006 @@ -9,10 +9,15 @@ LEVEL = ../.. -EXTRA_DIST = LibDeps.txt llvm-config.in.in find-cycles.pl +EXTRA_DIST = LibDeps.txt FinalLibDeps.txt llvm-config.in.in find-cycles.pl include $(LEVEL)/Makefile.common +# If we don't have Perl, we can't generate the library dependencies upon which +# llvm-config depends. Therefore, only if we detect perl will we do anything +# useful. +ifeq ($(HAVE_PERL),1) + # Combine preprocessor flags (except for -I) and CXX flags. SUB_CXXFLAGS = ${CPP.BaseFlags} ${CXX.Flags} @@ -21,10 +26,8 @@ # user to use libtool when linking against LLVM. SUB_LDFLAGS = -FinalLibDeps = $(PROJ_SRC_DIR)/FinalLibDeps.txt -ifdef HAVE_PERL -ifeq ($(HAVE_PERL),1) -LibDeps = $(PROJ_SRC_DIR)/LibDeps.txt +FinalLibDeps = $(PROJ_OBJ_DIR)/FinalLibDeps.txt +LibDeps = $(PROJ_OBJ_DIR)/LibDeps.txt GenLibDeps = $(PROJ_SRC_ROOT)/utils/GenLibDeps.pl # MANUAL USE ONLY! GenLibDeps.pl is very non-portable, so LibDeps.txt # should only be re-built manually. No other rule in this file should @@ -37,9 +40,7 @@ # don't have to process them at runtime. $(FinalLibDeps): find-cycles.pl $(LibDeps) $(Echo) "Finding cyclic dependencies between LLVM libraries." - $(Verb) $(PERL) $< < $(PROJ_SRC_DIR)/LibDeps.txt > $@ -endif -endif + $(Verb) $(PERL) $< < $(LibDeps) > $@ # Rerun our configure substitutions as needed. ConfigInIn = $(PROJ_SRC_DIR)/llvm-config.in.in @@ -56,13 +57,23 @@ $(Verb) $(SED) -f temp.sed < $< > $@ $(Verb) $(RM) temp.sed $(Verb) cat $(FinalLibDeps) >> $@ - $(Verb) chmod +x llvm-config + $(Verb) chmod +x $@ + +else +# We don't have perl, just generate a dummy llvm-config +llvm-config: + $(Echo) "Building place holder llvm-config script." + $(Verb) $(ECHO) 'echo llvm-config: Perl not found so llvm-config could not be generated' >> $@ + $(Verb) chmod +x $@ +endif # Hook into the standard Makefile rules. all-local:: llvm-config clean-local:: - $(Verb) $(RM) -f llvm-config llvm-config.in + $(Verb) $(RM) -f llvm-config llvm-config.in $(FinalLibDeps) $(LibDeps) \ + GenLibDeps.out install-local:: all-local $(Echo) Installing llvm-config $(Verb) $(MKDIR) $(PROJ_bindir) $(Verb) $(ScriptInstall) llvm-config $(PROJ_bindir) + From reid at x10sys.com Wed May 3 13:16:13 2006 From: reid at x10sys.com (Reid Spencer) Date: Wed, 3 May 2006 13:16:13 -0500 Subject: [llvm-commits] CVS: llvm/utils/GenLibDeps.pl Message-ID: <200605031816.NAA22835@zion.cs.uiuc.edu> Changes in directory llvm/utils: GenLibDeps.pl updated: 1.6 -> 1.7 --- Log message: Attempt to get this script working on Darwin. --- Diffs of the changes: (+2 -2) GenLibDeps.pl | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/utils/GenLibDeps.pl diff -u llvm/utils/GenLibDeps.pl:1.6 llvm/utils/GenLibDeps.pl:1.7 --- llvm/utils/GenLibDeps.pl:1.6 Fri Apr 21 00:29:25 2006 +++ llvm/utils/GenLibDeps.pl Wed May 3 13:16:01 2006 @@ -6,7 +6,7 @@ # libraries. The output of this script should periodically replace # the similar content in the UsingLibraries.html document. # -# Syntax: GenLibDeps.pl +# Syntax: GenLibDeps.pl [-flat] # # Parse arguments... @@ -76,7 +76,7 @@ print "
$lib
    \n"; } open UNDEFS, - "nm -g -u $Directory/$lib | grep ' U ' | sed -e 's/ U //' | sort | uniq |"; + "nm -g -u $Directory/$lib | sed -e 's/^ *U //' | sort | uniq |"; open DEPENDS, "| sort | uniq > GenLibDeps.out"; while () { From lattner at cs.uiuc.edu Wed May 3 13:52:43 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 3 May 2006 13:52:43 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineRelocation.h Message-ID: <200605031852.NAA23108@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineRelocation.h updated: 1.7 -> 1.8 --- Log message: Cleanup the internal implementation of MachineRelocation. No interface or functionality changes. --- Diffs of the changes: (+44 -36) MachineRelocation.h | 80 ++++++++++++++++++++++++++++------------------------ 1 files changed, 44 insertions(+), 36 deletions(-) Index: llvm/include/llvm/CodeGen/MachineRelocation.h diff -u llvm/include/llvm/CodeGen/MachineRelocation.h:1.7 llvm/include/llvm/CodeGen/MachineRelocation.h:1.8 --- llvm/include/llvm/CodeGen/MachineRelocation.h:1.7 Wed Jul 27 00:53:43 2005 +++ llvm/include/llvm/CodeGen/MachineRelocation.h Wed May 3 13:52:31 2006 @@ -35,65 +35,71 @@ /// 6. An index into the GOT, if the target uses a GOT /// class MachineRelocation { - /// OffsetTypeExternal - The low 24-bits of this value is the offset from the - /// start of the code buffer of the relocation to perform. Bit 24 of this is - /// set if Target should use ExtSym instead of GV, Bit 25 is the CanRewrite - /// bit, and the high 6 bits hold the relocation type. - // FIXME: with the additional types of relocatable things, rearrange the - // storage of things to be a bit more effiecient - unsigned OffsetTypeExternal; + enum AddressType { + isResult, // Relocation has be transformed into its result pointer. + isGV, // The Target.GV field is valid. + isExtSym, // The Target.ExtSym field is valid. + isConstPool, // The Target.ConstPool field is valid. + isGOTIndex // The Target.GOTIndex field is valid. + }; + + /// Offset - This is the offset from the start of the code buffer of the + /// relocation to perform. + unsigned Offset; + + /// ConstantVal - A field that may be used by the target relocation type. + intptr_t ConstantVal; + union { + void *Result; // If this has been resolved to a resolved pointer GlobalValue *GV; // If this is a pointer to an LLVM global const char *ExtSym; // If this is a pointer to a named symbol - void *Result; // If this has been resolved to a resolved pointer + unsigned ConstPool; // In this is a pointer to a constant pool entry unsigned GOTIndex; // Index in the GOT of this symbol/global - unsigned CPool; // Index in the Constant Pool } Target; - intptr_t ConstantVal; - bool GOTRelative; //out of bits in OffsetTypeExternal - bool isConstPool; + + unsigned TargetReloType : 6; // The target relocation ID. + AddressType AddrType : 3; // The field of Target to use. + bool DoesntNeedFnStub : 1; // True if we don't need a fn stub. + bool GOTRelative : 1; // Should this relocation be relative to the GOT? public: - MachineRelocation(unsigned Offset, unsigned RelocationType, GlobalValue *GV, + MachineRelocation(unsigned offset, unsigned RelocationType, GlobalValue *GV, intptr_t cst = 0, bool DoesntNeedFunctionStub = 0, bool GOTrelative = 0) - : OffsetTypeExternal(Offset + (RelocationType << 26)), ConstantVal(cst), - GOTRelative(GOTrelative), isConstPool(0) { - assert((Offset & ~((1 << 24)-1)) == 0 && "Code offset too large!"); + : Offset(offset), ConstantVal(cst), TargetReloType(RelocationType), + AddrType(isGV), DoesntNeedFnStub(DoesntNeedFunctionStub), + GOTRelative(GOTrelative){ assert((RelocationType & ~63) == 0 && "Relocation type too large!"); Target.GV = GV; - if (DoesntNeedFunctionStub) - OffsetTypeExternal |= 1 << 25; } - MachineRelocation(unsigned Offset, unsigned RelocationType, const char *ES, + MachineRelocation(unsigned offset, unsigned RelocationType, const char *ES, intptr_t cst = 0, bool GOTrelative = 0) - : OffsetTypeExternal(Offset + (1 << 24) + (RelocationType << 26)), - ConstantVal(cst), GOTRelative(GOTrelative), isConstPool(0) { - assert((Offset & ~((1 << 24)-1)) == 0 && "Code offset too large!"); + : Offset(offset), ConstantVal(cst), TargetReloType(RelocationType), + AddrType(isExtSym), DoesntNeedFnStub(false), GOTRelative(GOTrelative) { assert((RelocationType & ~63) == 0 && "Relocation type too large!"); Target.ExtSym = ES; } - MachineRelocation(unsigned Offset, unsigned RelocationType, unsigned CPI, + MachineRelocation(unsigned offset, unsigned RelocationType, unsigned CPI, intptr_t cst = 0) - : OffsetTypeExternal(Offset + (RelocationType << 26)), - ConstantVal(cst), GOTRelative(0), isConstPool(1) { - assert((Offset & ~((1 << 24)-1)) == 0 && "Code offset too large!"); + : Offset(offset), ConstantVal(cst), TargetReloType(RelocationType), + AddrType(isConstPool), DoesntNeedFnStub(false), GOTRelative(0) { assert((RelocationType & ~63) == 0 && "Relocation type too large!"); - Target.CPool = CPI; + Target.ConstPool = CPI; } /// getMachineCodeOffset - Return the offset into the code buffer that the /// relocation should be performed. unsigned getMachineCodeOffset() const { - return OffsetTypeExternal & ((1 << 24)-1); + return Offset; } /// getRelocationType - Return the target-specific relocation ID for this /// relocation. unsigned getRelocationType() const { - return OffsetTypeExternal >> 26; + return TargetReloType; } /// getConstantVal - Get the constant value associated with this relocation. @@ -106,19 +112,19 @@ /// isGlobalValue - Return true if this relocation is a GlobalValue, as /// opposed to a constant string. bool isGlobalValue() const { - return (OffsetTypeExternal & (1 << 24)) == 0 && !isConstantPoolIndex(); + return AddrType == isGV; } /// isString - Return true if this is a constant string. /// bool isString() const { - return !isGlobalValue() && !isConstantPoolIndex(); + return AddrType == isExtSym; } /// isConstantPoolIndex - Return true if this is a constant pool reference. /// bool isConstantPoolIndex() const { - return isConstPool; + return AddrType == isConstPool; } /// isGOTRelative - Return true the target wants the index into the GOT of @@ -133,7 +139,7 @@ /// to be false, but targets can improve their compilation callback functions /// to handle more general cases if they want improved performance. bool doesntNeedFunctionStub() const { - return (OffsetTypeExternal & (1 << 25)) != 0; + return DoesntNeedFnStub; } /// getGlobalValue - If this is a global value reference, return the @@ -154,12 +160,13 @@ /// the index into the constant pool. unsigned getConstantPoolIndex() const { assert(isConstantPoolIndex() && "This is not a constant pool reference!"); - return Target.CPool; + return Target.ConstPool; } /// getResultPointer - Once this has been resolved to point to an actual /// address, this returns the pointer. void *getResultPointer() const { + assert(AddrType == isResult && "Result pointer isn't set yet!"); return Target.Result; } @@ -167,10 +174,12 @@ /// void setResultPointer(void *Ptr) { Target.Result = Ptr; + AddrType = isResult; } /// setGOTIndex - Set the GOT index to a specific value. void setGOTIndex(unsigned idx) { + AddrType = isGOTIndex; Target.GOTIndex = idx; } @@ -178,11 +187,10 @@ /// this returns that index. The index is from the lowest address entry /// in the GOT. unsigned getGOTIndex() const { + assert(AddrType == isGOTIndex); return Target.GOTIndex; } - }; - } #endif From lattner at cs.uiuc.edu Wed May 3 13:56:08 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 3 May 2006 13:56:08 -0500 Subject: [llvm-commits] CVS: llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp Message-ID: <200605031856.NAA23184@zion.cs.uiuc.edu> Changes in directory llvm/lib/ExecutionEngine/JIT: JITEmitter.cpp updated: 1.95 -> 1.96 --- Log message: minor cleanups, no functionality change --- Diffs of the changes: (+7 -7) JITEmitter.cpp | 14 +++++++------- 1 files changed, 7 insertions(+), 7 deletions(-) Index: llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp diff -u llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.95 llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.96 --- llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.95 Wed May 3 12:10:41 2006 +++ llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp Wed May 3 13:55:56 2006 @@ -487,20 +487,20 @@ // If the target REALLY wants a stub for this function, emit it now. if (!MR.doesntNeedFunctionStub()) ResultPtr = getJITResolver(this).getExternalFunctionStub(ResultPtr); - } else if (MR.isGlobalValue()) + } else if (MR.isGlobalValue()) { ResultPtr = getPointerToGlobal(MR.getGlobalValue(), BufferBegin+MR.getMachineCodeOffset(), MR.doesntNeedFunctionStub()); - else //ConstantPoolIndex - ResultPtr = - (void*)(intptr_t)getConstantPoolEntryAddress(MR.getConstantPoolIndex()); + } else { + assert(MR.isConstantPoolIndex()); + ResultPtr=(void*)getConstantPoolEntryAddress(MR.getConstantPoolIndex()); + } MR.setResultPointer(ResultPtr); // if we are managing the GOT and the relocation wants an index, // give it one - if (MemMgr.isManagingGOT() && !MR.isConstantPoolIndex() && - MR.isGOTRelative()) { + if (MemMgr.isManagingGOT() && MR.isGOTRelative()) { unsigned idx = getJITResolver(this).getGOTIndexForAddr(ResultPtr); MR.setGOTIndex(idx); if (((void**)MemMgr.getGOTBase())[idx] != ResultPtr) { @@ -516,7 +516,7 @@ Relocations.size(), MemMgr.getGOTBase()); } - //Update the GOT entry for F to point to the new code. + // Update the GOT entry for F to point to the new code. if(MemMgr.isManagingGOT()) { unsigned idx = getJITResolver(this).getGOTIndexForAddr((void*)BufferBegin); if (((void**)MemMgr.getGOTBase())[idx] != (void*)BufferBegin) { From evan.cheng at apple.com Wed May 3 15:29:46 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 3 May 2006 15:29:46 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/X86/vec_shuffle-5.ll Message-ID: <200605032029.PAA23645@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/X86: vec_shuffle-5.ll added (r1.1) --- Log message: Use movsd to shuffle in the lowest two elements of a v4f32 / v4i32 vector when movlps cannot be used (e.g. when load from m64 has multiple uses). --- Diffs of the changes: (+11 -0) vec_shuffle-5.ll | 11 +++++++++++ 1 files changed, 11 insertions(+) Index: llvm/test/Regression/CodeGen/X86/vec_shuffle-5.ll diff -c /dev/null llvm/test/Regression/CodeGen/X86/vec_shuffle-5.ll:1.1 *** /dev/null Wed May 3 15:29:44 2006 --- llvm/test/Regression/CodeGen/X86/vec_shuffle-5.ll Wed May 3 15:29:34 2006 *************** *** 0 **** --- 1,11 ---- + ; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movsd | wc -l | grep 1 + + void %test() { + %tmp1 = load <4 x float>* null + %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> < float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00 >, <4 x uint> < uint 0, uint 1, uint 6, uint 7 > + %tmp3 = shufflevector <4 x float> %tmp1, <4 x float> zeroinitializer, <4 x uint> < uint 2, uint 3, uint 6, uint 7 > + %tmp4 = add <4 x float> %tmp2, %tmp3 + store <4 x float> %tmp4, <4 x float>* null + ret void + } + From lattner at cs.uiuc.edu Wed May 3 15:30:34 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 3 May 2006 15:30:34 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineRelocation.h Message-ID: <200605032030.PAA23731@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineRelocation.h updated: 1.8 -> 1.9 --- Log message: Change from using MachineRelocation ctors to using static methods in MachineRelocation to create Relocations. --- Diffs of the changes: (+46 -19) MachineRelocation.h | 65 ++++++++++++++++++++++++++++++++++++---------------- 1 files changed, 46 insertions(+), 19 deletions(-) Index: llvm/include/llvm/CodeGen/MachineRelocation.h diff -u llvm/include/llvm/CodeGen/MachineRelocation.h:1.8 llvm/include/llvm/CodeGen/MachineRelocation.h:1.9 --- llvm/include/llvm/CodeGen/MachineRelocation.h:1.8 Wed May 3 13:52:31 2006 +++ llvm/include/llvm/CodeGen/MachineRelocation.h Wed May 3 15:30:20 2006 @@ -45,7 +45,7 @@ /// Offset - This is the offset from the start of the code buffer of the /// relocation to perform. - unsigned Offset; + intptr_t Offset; /// ConstantVal - A field that may be used by the target relocation type. intptr_t ConstantVal; @@ -64,35 +64,62 @@ bool GOTRelative : 1; // Should this relocation be relative to the GOT? public: - MachineRelocation(unsigned offset, unsigned RelocationType, GlobalValue *GV, - intptr_t cst = 0, bool DoesntNeedFunctionStub = 0, - bool GOTrelative = 0) - : Offset(offset), ConstantVal(cst), TargetReloType(RelocationType), - AddrType(isGV), DoesntNeedFnStub(DoesntNeedFunctionStub), - GOTRelative(GOTrelative){ + /// MachineRelocation::getGV - Return a relocation entry for a GlobalValue. + /// + static MachineRelocation getGV(intptr_t offset, unsigned RelocationType, + GlobalValue *GV, intptr_t cst = 0, + bool DoesntNeedFunctionStub = 0, + bool GOTrelative = 0) { assert((RelocationType & ~63) == 0 && "Relocation type too large!"); - Target.GV = GV; + MachineRelocation Result; + Result.Offset = offset; + Result.ConstantVal = cst; + Result.TargetReloType = RelocationType; + Result.AddrType = isGV; + Result.DoesntNeedFnStub = DoesntNeedFunctionStub; + Result.GOTRelative = GOTrelative; + Result.Target.GV = GV; + return Result; } - MachineRelocation(unsigned offset, unsigned RelocationType, const char *ES, - intptr_t cst = 0, bool GOTrelative = 0) - : Offset(offset), ConstantVal(cst), TargetReloType(RelocationType), - AddrType(isExtSym), DoesntNeedFnStub(false), GOTRelative(GOTrelative) { + /// MachineRelocation::getExtSym - Return a relocation entry for an external + /// symbol, like "free". + /// + static MachineRelocation getExtSym(intptr_t offset, unsigned RelocationType, + const char *ES, intptr_t cst = 0, + bool GOTrelative = 0) { assert((RelocationType & ~63) == 0 && "Relocation type too large!"); - Target.ExtSym = ES; + MachineRelocation Result; + Result.Offset = offset; + Result.ConstantVal = cst; + Result.TargetReloType = RelocationType; + Result.AddrType = isExtSym; + Result.DoesntNeedFnStub = false; + Result.GOTRelative = GOTrelative; + Result.Target.ExtSym = ES; + return Result; } - MachineRelocation(unsigned offset, unsigned RelocationType, unsigned CPI, - intptr_t cst = 0) - : Offset(offset), ConstantVal(cst), TargetReloType(RelocationType), - AddrType(isConstPool), DoesntNeedFnStub(false), GOTRelative(0) { + /// MachineRelocation::getConstPool - Return a relocation entry for a constant + /// pool entry. + /// + static MachineRelocation getConstPool(intptr_t offset,unsigned RelocationType, + unsigned CPI, intptr_t cst = 0) { assert((RelocationType & ~63) == 0 && "Relocation type too large!"); - Target.ConstPool = CPI; + MachineRelocation Result; + Result.Offset = offset; + Result.ConstantVal = cst; + Result.TargetReloType = RelocationType; + Result.AddrType = isConstPool; + Result.DoesntNeedFnStub = false; + Result.GOTRelative = false; + Result.Target.ConstPool = CPI; + return Result; } /// getMachineCodeOffset - Return the offset into the code buffer that the /// relocation should be performed. - unsigned getMachineCodeOffset() const { + intptr_t getMachineCodeOffset() const { return Offset; } From lattner at cs.uiuc.edu Wed May 3 15:30:35 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 3 May 2006 15:30:35 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp Message-ID: <200605032030.PAA23743@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCCodeEmitter.cpp updated: 1.58 -> 1.59 --- Log message: Change from using MachineRelocation ctors to using static methods in MachineRelocation to create Relocations. --- Diffs of the changes: (+2 -2) PPCCodeEmitter.cpp | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp diff -u llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp:1.58 llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp:1.59 --- llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp:1.58 Wed May 3 12:10:41 2006 +++ llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp Wed May 3 15:30:20 2006 @@ -180,10 +180,10 @@ } } if (MO.isGlobalAddress()) - MCE.addRelocation(MachineRelocation(MCE.getCurrentPCOffset(), + MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc, MO.getGlobal(), 0)); else - MCE.addRelocation(MachineRelocation(MCE.getCurrentPCOffset(), + MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(), Reloc, MO.getSymbolName(), 0)); } else if (MO.isMachineBasicBlock()) { unsigned* CurrPC = (unsigned*)(intptr_t)MCE.getCurrentPCValue(); From lattner at cs.uiuc.edu Wed May 3 15:30:34 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 3 May 2006 15:30:34 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86CodeEmitter.cpp Message-ID: <200605032030.PAA23739@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86CodeEmitter.cpp updated: 1.102 -> 1.103 --- Log message: Change from using MachineRelocation ctors to using static methods in MachineRelocation to create Relocations. --- Diffs of the changes: (+3 -3) X86CodeEmitter.cpp | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) Index: llvm/lib/Target/X86/X86CodeEmitter.cpp diff -u llvm/lib/Target/X86/X86CodeEmitter.cpp:1.102 llvm/lib/Target/X86/X86CodeEmitter.cpp:1.103 --- llvm/lib/Target/X86/X86CodeEmitter.cpp:1.102 Wed May 3 12:21:32 2006 +++ llvm/lib/Target/X86/X86CodeEmitter.cpp Wed May 3 15:30:20 2006 @@ -123,7 +123,7 @@ /// assuming this is part of a function call, which is PC relative. /// void Emitter::emitGlobalAddressForCall(GlobalValue *GV, bool isTailCall) { - MCE.addRelocation(MachineRelocation(MCE.getCurrentPCOffset(), + MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), X86::reloc_pcrel_word, GV, 0, !isTailCall /*Doesn'tNeedStub*/)); MCE.emitWordLE(0); @@ -134,7 +134,7 @@ /// PC relative. /// void Emitter::emitGlobalAddressForPtr(GlobalValue *GV, int Disp /* = 0 */) { - MCE.addRelocation(MachineRelocation(MCE.getCurrentPCOffset(), + MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), X86::reloc_absolute_word, GV)); MCE.emitWordLE(Disp); // The relocated value will be added to the displacement } @@ -144,7 +144,7 @@ /// relative. void Emitter::emitExternalSymbolAddress(const char *ES, bool isPCRelative, bool isTailCall) { - MCE.addRelocation(MachineRelocation(MCE.getCurrentPCOffset(), + MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(), isPCRelative ? X86::reloc_pcrel_word : X86::reloc_absolute_word, ES)); MCE.emitWordLE(0); } From lattner at cs.uiuc.edu Wed May 3 15:30:34 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 3 May 2006 15:30:34 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp Message-ID: <200605032030.PAA23735@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Alpha: AlphaCodeEmitter.cpp updated: 1.14 -> 1.15 --- Log message: Change from using MachineRelocation ctors to using static methods in MachineRelocation to create Relocations. --- Diffs of the changes: (+3 -3) AlphaCodeEmitter.cpp | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) Index: llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp diff -u llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp:1.14 llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp:1.15 --- llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp:1.14 Wed May 3 12:10:41 2006 +++ llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp Wed May 3 15:30:20 2006 @@ -215,15 +215,15 @@ abort(); } if (MO.isGlobalAddress()) - MCE.addRelocation(MachineRelocation((unsigned)MCE.getCurrentPCOffset(), + MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc, MO.getGlobal(), Offset, false, useGOT)); else if (MO.isExternalSymbol()) - MCE.addRelocation(MachineRelocation((unsigned)MCE.getCurrentPCOffset(), + MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(), Reloc, MO.getSymbolName(), Offset, true)); else - MCE.addRelocation(MachineRelocation((unsigned)MCE.getCurrentPCOffset(), + MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(), Reloc, MO.getConstantPoolIndex(), Offset)); } else if (MO.isMachineBasicBlock()) { From evan.cheng at apple.com Wed May 3 15:32:15 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 3 May 2006 15:32:15 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td Message-ID: <200605032032.PAA23760@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrSSE.td updated: 1.114 -> 1.115 --- Log message: Use movsd to shuffle in the lowest two elements of a v4f32 / v4i32 vector when movlps cannot be used (e.g. when load from m64 has multiple uses). --- Diffs of the changes: (+8 -0) X86InstrSSE.td | 8 ++++++++ 1 files changed, 8 insertions(+) Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.114 llvm/lib/Target/X86/X86InstrSSE.td:1.115 --- llvm/lib/Target/X86/X86InstrSSE.td:1.114 Tue Apr 25 12:48:41 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Wed May 3 15:32:03 2006 @@ -2481,6 +2481,14 @@ MOVL_shuffle_mask)), (v2i64 (MOVLPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>; +// vector_shuffle v1, v2 <4, 5, 2, 3> using MOVLPDrr (movsd) +def : Pat<(v4f32 (vector_shuffle VR128:$src1, VR128:$src2, + MOVLP_shuffle_mask)), + (v4f32 (MOVLPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>; +def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2, + MOVLP_shuffle_mask)), + (v4i32 (MOVLPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>; + // Set lowest element and zero upper elements. def : Pat<(bc_v2i64 (vector_shuffle immAllZerosV, (v2f64 (scalar_to_vector (loadf64 addr:$src))), From lattner at cs.uiuc.edu Wed May 3 19:42:20 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 3 May 2006 19:42:20 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86CodeEmitter.cpp Message-ID: <200605040042.TAA29921@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86CodeEmitter.cpp updated: 1.103 -> 1.104 --- Log message: Simplify handling of relocations --- Diffs of the changes: (+38 -24) X86CodeEmitter.cpp | 62 ++++++++++++++++++++++++++++++++--------------------- 1 files changed, 38 insertions(+), 24 deletions(-) Index: llvm/lib/Target/X86/X86CodeEmitter.cpp diff -u llvm/lib/Target/X86/X86CodeEmitter.cpp:1.103 llvm/lib/Target/X86/X86CodeEmitter.cpp:1.104 --- llvm/lib/Target/X86/X86CodeEmitter.cpp:1.103 Wed May 3 15:30:20 2006 +++ llvm/lib/Target/X86/X86CodeEmitter.cpp Wed May 3 19:42:08 2006 @@ -57,6 +57,8 @@ void emitExternalSymbolAddress(const char *ES, bool isPCRelative, bool isTailCall); + void emitDisplacementField(const MachineOperand *RelocOp, int DispVal); + void emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeField); void emitSIBByte(unsigned SS, unsigned Index, unsigned Base); void emitConstant(unsigned Val, unsigned Size); @@ -211,19 +213,39 @@ } } +/// isDisp8 - Return true if this signed displacement fits in a 8-bit +/// sign-extended field. static bool isDisp8(int Value) { return Value == (signed char)Value; } +void Emitter::emitDisplacementField(const MachineOperand *RelocOp, + int DispVal) { + // If this is a simple integer displacement that doesn't require a relocation, + // emit it now. + if (!RelocOp) { + emitConstant(DispVal, 4); + return; + } + + // Otherwise, this is something that requires a relocation. Emit it as such + // now. + if (RelocOp->isGlobalAddress()) { + emitGlobalAddressForPtr(RelocOp->getGlobal(), RelocOp->getOffset()); + } else { + assert(0 && "Unknown value to relocate!"); + } +} + void Emitter::emitMemModRMByte(const MachineInstr &MI, unsigned Op, unsigned RegOpcodeField) { const MachineOperand &Op3 = MI.getOperand(Op+3); - GlobalValue *GV = 0; int DispVal = 0; - + const MachineOperand *DispForReloc = 0; + + // Figure out what sort of displacement we have to handle here. if (Op3.isGlobalAddress()) { - GV = Op3.getGlobal(); - DispVal = Op3.getOffset(); + DispForReloc = &Op3; } else if (Op3.isConstantPoolIndex()) { DispVal += MCE.getConstantPoolEntryAddress(Op3.getConstantPoolIndex()); DispVal += Op3.getOffset(); @@ -244,27 +266,21 @@ if (BaseReg == 0) { // Just a displacement? // Emit special case [disp32] encoding MCE.emitByte(ModRMByte(0, RegOpcodeField, 5)); - if (GV) - emitGlobalAddressForPtr(GV, DispVal); - else - emitConstant(DispVal, 4); + + emitDisplacementField(DispForReloc, DispVal); } else { unsigned BaseRegNo = getX86RegNum(BaseReg); - if (GV) { - // Emit the most general non-SIB encoding: [REG+disp32] - MCE.emitByte(ModRMByte(2, RegOpcodeField, BaseRegNo)); - emitGlobalAddressForPtr(GV, DispVal); - } else if (DispVal == 0 && BaseRegNo != N86::EBP) { + if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) { // Emit simple indirect register encoding... [EAX] f.e. MCE.emitByte(ModRMByte(0, RegOpcodeField, BaseRegNo)); - } else if (isDisp8(DispVal)) { + } else if (!DispForReloc && isDisp8(DispVal)) { // Emit the disp8 encoding... [REG+disp8] MCE.emitByte(ModRMByte(1, RegOpcodeField, BaseRegNo)); emitConstant(DispVal, 1); } else { // Emit the most general non-SIB encoding: [REG+disp32] MCE.emitByte(ModRMByte(2, RegOpcodeField, BaseRegNo)); - emitConstant(DispVal, 4); + emitDisplacementField(DispForReloc, DispVal); } } @@ -278,8 +294,8 @@ // MOD=0, BASE=5, to JUST get the index, scale, and displacement. MCE.emitByte(ModRMByte(0, RegOpcodeField, 4)); ForceDisp32 = true; - } else if (GV) { - // Emit the normal disp32 encoding... + } else if (DispForReloc) { + // Emit the normal disp32 encoding. MCE.emitByte(ModRMByte(2, RegOpcodeField, 4)); ForceDisp32 = true; } else if (DispVal == 0 && BaseReg != X86::EBP) { @@ -314,13 +330,10 @@ } // Do we need to output a displacement? - if (DispVal != 0 || ForceDisp32 || ForceDisp8) { - if (!ForceDisp32 && isDisp8(DispVal)) - emitConstant(DispVal, 1); - else if (GV) - emitGlobalAddressForPtr(GV, DispVal); - else - emitConstant(DispVal, 4); + if (ForceDisp8) { + emitConstant(DispVal, 1); + } else if (DispVal != 0 || ForceDisp32) { + emitDisplacementField(DispForReloc, DispVal); } } } @@ -420,6 +433,7 @@ if (MI.getNumOperands() == 2) { const MachineOperand &MO1 = MI.getOperand(1); if (Value *V = MO1.getVRegValueOrNull()) { + assert(0 && "??"); assert(sizeOfImm(Desc) == 4 && "Don't know how to emit non-pointer values!"); emitGlobalAddressForPtr(cast(V)); From lattner at cs.uiuc.edu Wed May 3 19:44:42 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 3 May 2006 19:44:42 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/MachineInstr.cpp Message-ID: <200605040044.TAA30130@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: MachineInstr.cpp updated: 1.111 -> 1.112 --- Log message: Remove some more unused stuff from MachineInstr that was leftover from V9. --- Diffs of the changes: (+0 -38) MachineInstr.cpp | 38 -------------------------------------- 1 files changed, 38 deletions(-) Index: llvm/lib/CodeGen/MachineInstr.cpp diff -u llvm/lib/CodeGen/MachineInstr.cpp:1.111 llvm/lib/CodeGen/MachineInstr.cpp:1.112 --- llvm/lib/CodeGen/MachineInstr.cpp:1.111 Sat Apr 22 13:53:45 2006 +++ llvm/lib/CodeGen/MachineInstr.cpp Wed May 3 19:44:25 2006 @@ -199,14 +199,6 @@ if (MO.hasAllocatedReg()) OutputReg(OS, MO.getReg(), MRI); break; - case MachineOperand::MO_CCRegister: - OS << "%ccreg"; - OutputValue(OS, MO.getVRegValue()); - if (MO.hasAllocatedReg()) { - OS << "=="; - OutputReg(OS, MO.getReg(), MRI); - } - break; case MachineOperand::MO_MachineRegister: OutputReg(OS, MO.getMachineRegNum(), MRI); break; @@ -216,17 +208,6 @@ case MachineOperand::MO_UnextendedImmed: OS << (long)MO.getImmedValue(); break; - case MachineOperand::MO_PCRelativeDisp: { - const Value* opVal = MO.getVRegValue(); - bool isLabel = isa(opVal) || isa(opVal); - OS << "%disp(" << (isLabel? "label " : "addr-of-val "); - if (opVal->hasName()) - OS << opVal->getName(); - else - OS << (const void*) opVal; - OS << ")"; - break; - } case MachineOperand::MO_MachineBasicBlock: OS << "mbb<" << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName() @@ -341,14 +322,6 @@ OutputValue(OS, MO.getVRegValue()); } break; - case MachineOperand::MO_CCRegister: - OS << "%ccreg"; - OutputValue(OS, MO.getVRegValue()); - if (MO.hasAllocatedReg()) { - OS << "=="; - OutputReg(OS, MO.getReg()); - } - break; case MachineOperand::MO_MachineRegister: OutputReg(OS, MO.getMachineRegNum()); break; @@ -358,17 +331,6 @@ case MachineOperand::MO_UnextendedImmed: OS << (long)MO.getImmedValue(); break; - case MachineOperand::MO_PCRelativeDisp: { - const Value* opVal = MO.getVRegValue(); - bool isLabel = isa(opVal) || isa(opVal); - OS << "%disp(" << (isLabel? "label " : "addr-of-val "); - if (opVal->hasName()) - OS << opVal->getName(); - else - OS << (const void*) opVal; - OS << ")"; - break; - } case MachineOperand::MO_MachineBasicBlock: OS << "getBasicBlock())->getName() From lattner at cs.uiuc.edu Wed May 3 19:44:43 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 3 May 2006 19:44:43 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp Message-ID: <200605040044.TAA30142@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Alpha: AlphaAsmPrinter.cpp updated: 1.36 -> 1.37 --- Log message: Remove some more unused stuff from MachineInstr that was leftover from V9. --- Diffs of the changes: (+0 -6) AlphaAsmPrinter.cpp | 6 ------ 1 files changed, 6 deletions(-) Index: llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp diff -u llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.36 llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.37 --- llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.36 Tue May 2 20:29:57 2006 +++ llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp Wed May 3 19:44:25 2006 @@ -100,7 +100,6 @@ } // FALLTHROUGH case MachineOperand::MO_MachineRegister: - case MachineOperand::MO_CCRegister: O << RI.get(MO.getReg()).Name; return; @@ -110,11 +109,6 @@ abort(); return; - case MachineOperand::MO_PCRelativeDisp: - std::cerr << "Shouldn't use addPCDisp() when building Alpha MachineInstrs"; - abort(); - return; - case MachineOperand::MO_MachineBasicBlock: printBasicBlockLabel(MO.getMachineBasicBlock()); return; From lattner at cs.uiuc.edu Wed May 3 19:44:43 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 3 May 2006 19:44:43 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcAsmPrinter.cpp Message-ID: <200605040044.TAA30141@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Sparc: SparcAsmPrinter.cpp updated: 1.60 -> 1.61 --- Log message: Remove some more unused stuff from MachineInstr that was leftover from V9. --- Diffs of the changes: (+0 -4) SparcAsmPrinter.cpp | 4 ---- 1 files changed, 4 deletions(-) Index: llvm/lib/Target/Sparc/SparcAsmPrinter.cpp diff -u llvm/lib/Target/Sparc/SparcAsmPrinter.cpp:1.60 llvm/lib/Target/Sparc/SparcAsmPrinter.cpp:1.61 --- llvm/lib/Target/Sparc/SparcAsmPrinter.cpp:1.60 Tue May 2 20:29:57 2006 +++ llvm/lib/Target/Sparc/SparcAsmPrinter.cpp Wed May 3 19:44:25 2006 @@ -166,10 +166,6 @@ case MachineOperand::MO_MachineBasicBlock: printBasicBlockLabel(MO.getMachineBasicBlock()); return; - case MachineOperand::MO_PCRelativeDisp: - std::cerr << "Shouldn't use addPCDisp() when building Sparc MachineInstrs"; - abort (); - return; case MachineOperand::MO_GlobalAddress: O << Mang->getValueName(MO.getGlobal()); break; From lattner at cs.uiuc.edu Wed May 3 19:44:43 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 3 May 2006 19:44:43 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp Message-ID: <200605040044.TAA30138@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCAsmPrinter.cpp updated: 1.167 -> 1.168 --- Log message: Remove some more unused stuff from MachineInstr that was leftover from V9. --- Diffs of the changes: (+0 -6) PPCAsmPrinter.cpp | 6 ------ 1 files changed, 6 deletions(-) Index: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp diff -u llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.167 llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.168 --- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.167 Tue May 2 20:29:57 2006 +++ llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp Wed May 3 19:44:25 2006 @@ -360,7 +360,6 @@ } // FALLTHROUGH case MachineOperand::MO_MachineRegister: - case MachineOperand::MO_CCRegister: O << RI.get(MO.getReg()).Name; return; @@ -370,11 +369,6 @@ abort(); return; - case MachineOperand::MO_PCRelativeDisp: - std::cerr << "Shouldn't use addPCDisp() when building PPC MachineInstrs"; - abort(); - return; - case MachineOperand::MO_MachineBasicBlock: printBasicBlockLabel(MO.getMachineBasicBlock()); return; From lattner at cs.uiuc.edu Wed May 3 19:44:43 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 3 May 2006 19:44:43 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineInstr.h MachineInstrBuilder.h Message-ID: <200605040044.TAA30152@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineInstr.h updated: 1.168 -> 1.169 MachineInstrBuilder.h updated: 1.30 -> 1.31 --- Log message: Remove some more unused stuff from MachineInstr that was leftover from V9. --- Diffs of the changes: (+3 -71) MachineInstr.h | 49 +++---------------------------------------------- MachineInstrBuilder.h | 25 ------------------------- 2 files changed, 3 insertions(+), 71 deletions(-) Index: llvm/include/llvm/CodeGen/MachineInstr.h diff -u llvm/include/llvm/CodeGen/MachineInstr.h:1.168 llvm/include/llvm/CodeGen/MachineInstr.h:1.169 --- llvm/include/llvm/CodeGen/MachineInstr.h:1.168 Sat Apr 22 13:53:45 2006 +++ llvm/include/llvm/CodeGen/MachineInstr.h Wed May 3 19:44:25 2006 @@ -98,10 +98,8 @@ enum MachineOperandType { MO_VirtualRegister, // virtual register for *value MO_MachineRegister, // pre-assigned machine register `regNum' - MO_CCRegister, MO_SignExtendedImmed, MO_UnextendedImmed, - MO_PCRelativeDisp, MO_MachineBasicBlock, // MachineBasicBlock reference MO_FrameIndex, // Abstract Stack Frame Index MO_ConstantPoolIndex, // Address of indexed Constant in Constant Pool @@ -237,7 +235,6 @@ /// Accessors that tell you what kind of MachineOperand you're looking at. /// bool isMachineBasicBlock() const { return opType == MO_MachineBasicBlock; } - bool isPCRelativeDisp() const { return opType == MO_PCRelativeDisp; } bool isImmediate() const { return opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed; } @@ -251,16 +248,14 @@ /// has one. This is deprecated and only used by the SPARC v9 backend. /// Value* getVRegValueOrNull() const { - return (opType == MO_VirtualRegister || opType == MO_CCRegister || - isPCRelativeDisp()) ? contents.value : NULL; + return opType == MO_VirtualRegister ? contents.value : NULL; } /// MachineOperand accessors that only work on certain types of /// MachineOperand... /// Value* getVRegValue() const { - assert ((opType == MO_VirtualRegister || opType == MO_CCRegister - || isPCRelativeDisp()) && "Wrong MachineOperand accessor"); + assert(opType == MO_VirtualRegister && "Wrong MachineOperand accessor"); return contents.value; } int getMachineRegNum() const { @@ -322,8 +317,7 @@ /// bool hasAllocatedReg() const { return (extra.regNum >= 0 && - (opType == MO_VirtualRegister || opType == MO_CCRegister || - opType == MO_MachineRegister)); + (opType == MO_VirtualRegister || opType == MO_MachineRegister)); } /// getReg - Returns the register number. It is a runtime error to call this @@ -362,25 +356,6 @@ friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop); - /// markHi32, markLo32, etc. - These methods are deprecated and only used by - /// the SPARC v9 back-end. - /// - void markHi32() { flags |= HIFLAG32; } - void markLo32() { flags |= LOFLAG32; } - void markHi64() { flags |= HIFLAG64; } - void markLo64() { flags |= LOFLAG64; } - -private: - /// setRegForValue - Replaces the Value with its corresponding physical - /// register after register allocation is complete. This is deprecated - /// and only used by the SPARC v9 back-end. - /// - void setRegForValue(int reg) { - assert(opType == MO_VirtualRegister || opType == MO_CCRegister || - opType == MO_MachineRegister); - extra.regNum = reg; - } - friend class MachineInstr; }; @@ -507,15 +482,6 @@ UTy, isPCRelative)); } - void addCCRegOperand(Value *V, - MachineOperand::UseType UTy = MachineOperand::Use) { - assert(!OperandsComplete() && - "Trying to add an operand to a machine instr that is already done!"); - operands.push_back(MachineOperand(V, MachineOperand::MO_CCRegister, UTy, - false)); - } - - /// addRegOperand - Add a symbolic virtual register reference... /// void addRegOperand(int reg, bool isDef) { @@ -536,15 +502,6 @@ MachineOperand(reg, MachineOperand::MO_VirtualRegister, UTy)); } - /// addPCDispOperand - Add a PC relative displacement operand to the MI - /// - void addPCDispOperand(Value *V) { - assert(!OperandsComplete() && - "Trying to add an operand to a machine instr that is already done!"); - operands.push_back( - MachineOperand(V, MachineOperand::MO_PCRelativeDisp,MachineOperand::Use)); - } - /// addMachineRegOperand - Add a virtual register operand to this MachineInstr /// void addMachineRegOperand(int reg, bool isDef) { Index: llvm/include/llvm/CodeGen/MachineInstrBuilder.h diff -u llvm/include/llvm/CodeGen/MachineInstrBuilder.h:1.30 llvm/include/llvm/CodeGen/MachineInstrBuilder.h:1.31 --- llvm/include/llvm/CodeGen/MachineInstrBuilder.h:1.30 Mon Apr 24 01:42:15 2006 +++ llvm/include/llvm/CodeGen/MachineInstrBuilder.h Wed May 3 19:44:25 2006 @@ -55,15 +55,6 @@ return *this; } - /// addReg - Add an LLVM value that is to be used as a register... - /// - const MachineInstrBuilder &addCCReg( - Value *V, - MachineOperand::UseType Ty = MachineOperand::Use) const { - MI->addCCRegOperand(V, Ty); - return *this; - } - /// addRegDef - Add an LLVM value that is to be defined as a register... this /// is the same as addReg(V, MachineOperand::Def). /// @@ -71,22 +62,6 @@ return addReg(V, MachineOperand::Def); } - /// addPCDisp - Add an LLVM value to be treated as a PC relative - /// displacement... - /// - const MachineInstrBuilder &addPCDisp(Value *V) const { - MI->addPCDispOperand(V); - return *this; - } - - /// addMReg - Add a machine register operand... - /// - const MachineInstrBuilder &addMReg(int Reg, MachineOperand::UseType Ty - = MachineOperand::Use) const { - MI->addMachineRegOperand(Reg, Ty); - return *this; - } - /// addImm - Add a new immediate operand. /// const MachineInstrBuilder &addImm(int Val) const { From lattner at cs.uiuc.edu Wed May 3 19:44:43 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 3 May 2006 19:44:43 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/IA64/IA64AsmPrinter.cpp Message-ID: <200605040044.TAA30134@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/IA64: IA64AsmPrinter.cpp updated: 1.28 -> 1.29 --- Log message: Remove some more unused stuff from MachineInstr that was leftover from V9. --- Diffs of the changes: (+0 -7) IA64AsmPrinter.cpp | 7 ------- 1 files changed, 7 deletions(-) Index: llvm/lib/Target/IA64/IA64AsmPrinter.cpp diff -u llvm/lib/Target/IA64/IA64AsmPrinter.cpp:1.28 llvm/lib/Target/IA64/IA64AsmPrinter.cpp:1.29 --- llvm/lib/Target/IA64/IA64AsmPrinter.cpp:1.28 Tue May 2 20:29:57 2006 +++ llvm/lib/Target/IA64/IA64AsmPrinter.cpp Wed May 3 19:44:25 2006 @@ -180,10 +180,8 @@ } // FALLTHROUGH case MachineOperand::MO_MachineRegister: - case MachineOperand::MO_CCRegister: { O << RI.get(MO.getReg()).Name; return; - } case MachineOperand::MO_SignExtendedImmed: case MachineOperand::MO_UnextendedImmed: @@ -192,11 +190,6 @@ case MachineOperand::MO_MachineBasicBlock: printBasicBlockLabel(MO.getMachineBasicBlock()); return; - case MachineOperand::MO_PCRelativeDisp: - std::cerr << "Shouldn't use addPCDisp() when building IA64 MachineInstrs"; - abort (); - return; - case MachineOperand::MO_ConstantPoolIndex: { O << "@gprel(" << PrivateGlobalPrefix << "CPI" << getFunctionNumber() << "_" << MO.getConstantPoolIndex() << ")"; From lattner at cs.uiuc.edu Wed May 3 19:44:43 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 3 May 2006 19:44:43 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp X86IntelAsmPrinter.cpp Message-ID: <200605040044.TAA30158@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ATTAsmPrinter.cpp updated: 1.38 -> 1.39 X86IntelAsmPrinter.cpp updated: 1.36 -> 1.37 --- Log message: Remove some more unused stuff from MachineInstr that was leftover from V9. --- Diffs of the changes: (+0 -8) X86ATTAsmPrinter.cpp | 4 ---- X86IntelAsmPrinter.cpp | 4 ---- 2 files changed, 8 deletions(-) Index: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp diff -u llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.38 llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.39 --- llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.38 Tue May 2 00:37:32 2006 +++ llvm/lib/Target/X86/X86ATTAsmPrinter.cpp Wed May 3 19:44:25 2006 @@ -126,10 +126,6 @@ case MachineOperand::MO_MachineBasicBlock: printBasicBlockLabel(MO.getMachineBasicBlock()); return; - case MachineOperand::MO_PCRelativeDisp: - std::cerr << "Shouldn't use addPCDisp() when building X86 MachineInstrs"; - abort (); - return; case MachineOperand::MO_JumpTableIndex: { bool isMemOp = Modifier && !strcmp(Modifier, "mem"); if (!isMemOp) O << '$'; Index: llvm/lib/Target/X86/X86IntelAsmPrinter.cpp diff -u llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.36 llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.37 --- llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.36 Tue May 2 00:37:32 2006 +++ llvm/lib/Target/X86/X86IntelAsmPrinter.cpp Wed May 3 19:44:25 2006 @@ -134,10 +134,6 @@ case MachineOperand::MO_MachineBasicBlock: printBasicBlockLabel(MO.getMachineBasicBlock()); return; - case MachineOperand::MO_PCRelativeDisp: - assert(0 && "Shouldn't use addPCDisp() when building X86 MachineInstrs"); - abort (); - return; case MachineOperand::MO_ConstantPoolIndex: { bool isMemOp = Modifier && !strcmp(Modifier, "mem"); if (!isMemOp) O << "OFFSET "; From lattner at cs.uiuc.edu Wed May 3 19:50:13 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 3 May 2006 19:50:13 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp Message-ID: <200605040050.TAA30666@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Alpha: AlphaAsmPrinter.cpp updated: 1.37 -> 1.38 --- Log message: Remove some more V9-specific stuff. --- Diffs of the changes: (+1 -6) AlphaAsmPrinter.cpp | 7 +------ 1 files changed, 1 insertion(+), 6 deletions(-) Index: llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp diff -u llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.37 llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.38 --- llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.37 Wed May 3 19:44:25 2006 +++ llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp Wed May 3 19:49:59 2006 @@ -123,12 +123,7 @@ return; case MachineOperand::MO_GlobalAddress: - //Abuse PCrel to specify pcrel calls - //calls are the only thing that use this flag -// if (MO.isPCRelative()) -// O << PrivateGlobalPrefix << Mang->getValueName(MO.getGlobal()) << "..ng"; -// else - O << Mang->getValueName(MO.getGlobal()); + O << Mang->getValueName(MO.getGlobal()); return; default: From lattner at cs.uiuc.edu Wed May 3 19:50:13 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 3 May 2006 19:50:13 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/MachineInstr.cpp Message-ID: <200605040050.TAA30670@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: MachineInstr.cpp updated: 1.112 -> 1.113 --- Log message: Remove some more V9-specific stuff. --- Diffs of the changes: (+2 -32) MachineInstr.cpp | 34 ++-------------------------------- 1 files changed, 2 insertions(+), 32 deletions(-) Index: llvm/lib/CodeGen/MachineInstr.cpp diff -u llvm/lib/CodeGen/MachineInstr.cpp:1.112 llvm/lib/CodeGen/MachineInstr.cpp:1.113 --- llvm/lib/CodeGen/MachineInstr.cpp:1.112 Wed May 3 19:44:25 2006 +++ llvm/lib/CodeGen/MachineInstr.cpp Wed May 3 19:49:59 2006 @@ -176,18 +176,6 @@ if (TM) MRI = TM->getRegisterInfo(); - bool CloseParen = true; - if (MO.isHiBits32()) - OS << "%lm("; - else if (MO.isLoBits32()) - OS << "%lo("; - else if (MO.isHiBits64()) - OS << "%hh("; - else if (MO.isLoBits64()) - OS << "%hm("; - else - CloseParen = false; - switch (MO.getType()) { case MachineOperand::MO_VirtualRegister: if (MO.getVRegValue()) { @@ -235,9 +223,6 @@ default: assert(0 && "Unrecognized operand type"); } - - if (CloseParen) - OS << ")"; } void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const { @@ -272,8 +257,7 @@ OS << "\n"; } -namespace llvm { -std::ostream &operator<<(std::ostream &os, const MachineInstr &MI) { +std::ostream &llvm::operator<<(std::ostream &os, const MachineInstr &MI) { // If the instruction is embedded into a basic block, we can find the target // info for the instruction. if (const MachineBasicBlock *MBB = MI.getParent()) { @@ -301,16 +285,7 @@ return os << "\n"; } -std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO) { - if (MO.isHiBits32()) - OS << "%lm("; - else if (MO.isLoBits32()) - OS << "%lo("; - else if (MO.isHiBits64()) - OS << "%hh("; - else if (MO.isLoBits64()) - OS << "%hm("; - +std::ostream &llvm::operator<<(std::ostream &OS, const MachineOperand &MO) { switch (MO.getType()) { case MachineOperand::MO_VirtualRegister: if (MO.hasAllocatedReg()) @@ -356,10 +331,5 @@ break; } - if (MO.isHiBits32() || MO.isLoBits32() || MO.isHiBits64() || MO.isLoBits64()) - OS << ")"; - return OS; } - -} From lattner at cs.uiuc.edu Wed May 3 19:50:13 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 3 May 2006 19:50:13 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86CodeEmitter.cpp Message-ID: <200605040050.TAA30674@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86CodeEmitter.cpp updated: 1.104 -> 1.105 --- Log message: Remove some more V9-specific stuff. --- Diffs of the changes: (+0 -1) X86CodeEmitter.cpp | 1 - 1 files changed, 1 deletion(-) Index: llvm/lib/Target/X86/X86CodeEmitter.cpp diff -u llvm/lib/Target/X86/X86CodeEmitter.cpp:1.104 llvm/lib/Target/X86/X86CodeEmitter.cpp:1.105 --- llvm/lib/Target/X86/X86CodeEmitter.cpp:1.104 Wed May 3 19:42:08 2006 +++ llvm/lib/Target/X86/X86CodeEmitter.cpp Wed May 3 19:49:59 2006 @@ -440,7 +440,6 @@ } else if (MO1.isGlobalAddress()) { assert(sizeOfImm(Desc) == 4 && "Don't know how to emit non-pointer values!"); - assert(!MO1.isPCRelative() && "Function pointer ref is PC relative?"); emitGlobalAddressForPtr(MO1.getGlobal(), MO1.getOffset()); } else if (MO1.isExternalSymbol()) { assert(sizeOfImm(Desc) == 4 && From lattner at cs.uiuc.edu Wed May 3 19:50:14 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 3 May 2006 19:50:14 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineInstr.h Message-ID: <200605040050.TAA30678@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineInstr.h updated: 1.169 -> 1.170 --- Log message: Remove some more V9-specific stuff. --- Diffs of the changes: (+0 -15) MachineInstr.h | 15 --------------- 1 files changed, 15 deletions(-) Index: llvm/include/llvm/CodeGen/MachineInstr.h diff -u llvm/include/llvm/CodeGen/MachineInstr.h:1.169 llvm/include/llvm/CodeGen/MachineInstr.h:1.170 --- llvm/include/llvm/CodeGen/MachineInstr.h:1.169 Wed May 3 19:44:25 2006 +++ llvm/include/llvm/CodeGen/MachineInstr.h Wed May 3 19:49:59 2006 @@ -75,10 +75,6 @@ enum { DEFFLAG = 0x01, // this is a def of the operand USEFLAG = 0x02, // this is a use of the operand - HIFLAG32 = 0x04, // operand is %hi32(value_or_immedVal) - LOFLAG32 = 0x08, // operand is %lo32(value_or_immedVal) - HIFLAG64 = 0x10, // operand is %hi64(value_or_immedVal) - LOFLAG64 = 0x20, // operand is %lo64(value_or_immedVal) PCRELATIVE = 0x40 // Operand is relative to PC, not a global address }; @@ -215,13 +211,6 @@ /// UseType getUseType() const { return UseType(flags & (USEFLAG|DEFFLAG)); } - /// isPCRelative - This returns the value of the PCRELATIVE flag, which - /// indicates whether this operand should be emitted as a PC relative value - /// instead of a global address. This is used for operands of the forms: - /// MachineBasicBlock, GlobalAddress, ExternalSymbol - /// - bool isPCRelative() const { return (flags & PCRELATIVE) != 0; } - /// isRegister - Return true if this operand is a register operand. The X86 /// backend currently can't decide whether to use MO_MR or MO_VR to represent /// them, so we accept both. @@ -307,10 +296,6 @@ MachineOperand& setUse () { flags |= USEFLAG; return *this; } bool isDef () const { return flags & DEFFLAG; } MachineOperand& setDef () { flags |= DEFFLAG; return *this; } - bool isHiBits32 () const { return flags & HIFLAG32; } - bool isLoBits32 () const { return flags & LOFLAG32; } - bool isHiBits64 () const { return flags & HIFLAG64; } - bool isLoBits64 () const { return flags & LOFLAG64; } /// hasAllocatedReg - Returns true iff a machine register has been /// allocated to this operand. From lattner at cs.uiuc.edu Wed May 3 20:15:19 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 3 May 2006 20:15:19 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp Message-ID: <200605040115.UAA31816@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCAsmPrinter.cpp updated: 1.168 -> 1.169 --- Log message: Remove a bunch more SparcV9 specific stuff --- Diffs of the changes: (+1 -8) PPCAsmPrinter.cpp | 9 +-------- 1 files changed, 1 insertion(+), 8 deletions(-) Index: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp diff -u llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.168 llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.169 --- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.168 Wed May 3 19:44:25 2006 +++ llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp Wed May 3 20:15:02 2006 @@ -86,7 +86,7 @@ void printOperand(const MachineInstr *MI, unsigned OpNo) { const MachineOperand &MO = MI->getOperand(OpNo); - if (MO.getType() == MachineOperand::MO_MachineRegister) { + if (MO.getType() == MachineOperand::MO_VirtualRegister) { assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??"); O << TM.getRegisterInfo()->get(MO.getReg()).Name; } else if (MO.isImmediate()) { @@ -353,13 +353,6 @@ int new_symbol; switch (MO.getType()) { - case MachineOperand::MO_VirtualRegister: - if (Value *V = MO.getVRegValueOrNull()) { - O << "<" << V->getName() << ">"; - return; - } - // FALLTHROUGH - case MachineOperand::MO_MachineRegister: O << RI.get(MO.getReg()).Name; return; From lattner at cs.uiuc.edu Wed May 3 20:15:19 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 3 May 2006 20:15:19 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/IA64/IA64AsmPrinter.cpp Message-ID: <200605040115.UAA31818@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/IA64: IA64AsmPrinter.cpp updated: 1.29 -> 1.30 --- Log message: Remove a bunch more SparcV9 specific stuff --- Diffs of the changes: (+1 -7) IA64AsmPrinter.cpp | 8 +------- 1 files changed, 1 insertion(+), 7 deletions(-) Index: llvm/lib/Target/IA64/IA64AsmPrinter.cpp diff -u llvm/lib/Target/IA64/IA64AsmPrinter.cpp:1.29 llvm/lib/Target/IA64/IA64AsmPrinter.cpp:1.30 --- llvm/lib/Target/IA64/IA64AsmPrinter.cpp:1.29 Wed May 3 19:44:25 2006 +++ llvm/lib/Target/IA64/IA64AsmPrinter.cpp Wed May 3 20:15:02 2006 @@ -66,7 +66,7 @@ // This method is used by the tablegen'erated instruction printer. void printOperand(const MachineInstr *MI, unsigned OpNo){ const MachineOperand &MO = MI->getOperand(OpNo); - if (MO.getType() == MachineOperand::MO_MachineRegister) { + if (MO.getType() == MachineOperand::MO_VirtualRegister) { assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physref??"); //XXX Bug Workaround: See note in Printer::doInitialization about %. O << TM.getRegisterInfo()->get(MO.getReg()).Name; @@ -174,12 +174,6 @@ const MRegisterInfo &RI = *TM.getRegisterInfo(); switch (MO.getType()) { case MachineOperand::MO_VirtualRegister: - if (Value *V = MO.getVRegValueOrNull()) { - O << "<" << V->getName() << ">"; - return; - } - // FALLTHROUGH - case MachineOperand::MO_MachineRegister: O << RI.get(MO.getReg()).Name; return; From lattner at cs.uiuc.edu Wed May 3 20:15:19 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 3 May 2006 20:15:19 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/MachineInstr.cpp Message-ID: <200605040115.UAA31836@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: MachineInstr.cpp updated: 1.113 -> 1.114 --- Log message: Remove a bunch more SparcV9 specific stuff --- Diffs of the changes: (+1 -7) MachineInstr.cpp | 8 +------- 1 files changed, 1 insertion(+), 7 deletions(-) Index: llvm/lib/CodeGen/MachineInstr.cpp diff -u llvm/lib/CodeGen/MachineInstr.cpp:1.113 llvm/lib/CodeGen/MachineInstr.cpp:1.114 --- llvm/lib/CodeGen/MachineInstr.cpp:1.113 Wed May 3 19:49:59 2006 +++ llvm/lib/CodeGen/MachineInstr.cpp Wed May 3 20:15:02 2006 @@ -141,7 +141,7 @@ void MachineInstr::SetMachineOperandReg(unsigned i, int regNum) { assert(i < getNumOperands()); // must be explicit op - operands[i].opType = MachineOperand::MO_MachineRegister; + operands[i].opType = MachineOperand::MO_VirtualRegister; operands[i].contents.value = NULL; operands[i].extra.regNum = regNum; } @@ -187,9 +187,6 @@ if (MO.hasAllocatedReg()) OutputReg(OS, MO.getReg(), MRI); break; - case MachineOperand::MO_MachineRegister: - OutputReg(OS, MO.getMachineRegNum(), MRI); - break; case MachineOperand::MO_SignExtendedImmed: OS << (long)MO.getImmedValue(); break; @@ -297,9 +294,6 @@ OutputValue(OS, MO.getVRegValue()); } break; - case MachineOperand::MO_MachineRegister: - OutputReg(OS, MO.getMachineRegNum()); - break; case MachineOperand::MO_SignExtendedImmed: OS << (long)MO.getImmedValue(); break; From lattner at cs.uiuc.edu Wed May 3 20:15:19 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 3 May 2006 20:15:19 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp X86InstrBuilder.h X86IntelAsmPrinter.cpp X86IntelAsmPrinter.h X86RegisterInfo.cpp Message-ID: <200605040115.UAA31828@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ATTAsmPrinter.cpp updated: 1.39 -> 1.40 X86InstrBuilder.h updated: 1.17 -> 1.18 X86IntelAsmPrinter.cpp updated: 1.37 -> 1.38 X86IntelAsmPrinter.h updated: 1.19 -> 1.20 X86RegisterInfo.cpp updated: 1.145 -> 1.146 --- Log message: Remove a bunch more SparcV9 specific stuff --- Diffs of the changes: (+4 -11) X86ATTAsmPrinter.cpp | 1 - X86InstrBuilder.h | 2 +- X86IntelAsmPrinter.cpp | 6 ------ X86IntelAsmPrinter.h | 4 ++-- X86RegisterInfo.cpp | 2 +- 5 files changed, 4 insertions(+), 11 deletions(-) Index: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp diff -u llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.39 llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.40 --- llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.39 Wed May 3 19:44:25 2006 +++ llvm/lib/Target/X86/X86ATTAsmPrinter.cpp Wed May 3 20:15:02 2006 @@ -109,7 +109,6 @@ const MRegisterInfo &RI = *TM.getRegisterInfo(); switch (MO.getType()) { case MachineOperand::MO_VirtualRegister: - case MachineOperand::MO_MachineRegister: assert(MRegisterInfo::isPhysicalRegister(MO.getReg()) && "Virtual registers should not make it this far!"); O << '%'; Index: llvm/lib/Target/X86/X86InstrBuilder.h diff -u llvm/lib/Target/X86/X86InstrBuilder.h:1.17 llvm/lib/Target/X86/X86InstrBuilder.h:1.18 --- llvm/lib/Target/X86/X86InstrBuilder.h:1.17 Thu Apr 21 18:38:14 2005 +++ llvm/lib/Target/X86/X86InstrBuilder.h Wed May 3 20:15:02 2006 @@ -93,7 +93,7 @@ assert (0); MIB.addZImm(AM.Scale).addReg(AM.IndexReg); if (AM.GV) - return MIB.addGlobalAddress(AM.GV, false, AM.Disp); + return MIB.addGlobalAddress(AM.GV, AM.Disp); else return MIB.addSImm(AM.Disp); } Index: llvm/lib/Target/X86/X86IntelAsmPrinter.cpp diff -u llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.37 llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.38 --- llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.37 Wed May 3 19:44:25 2006 +++ llvm/lib/Target/X86/X86IntelAsmPrinter.cpp Wed May 3 20:15:02 2006 @@ -115,12 +115,6 @@ const MRegisterInfo &RI = *TM.getRegisterInfo(); switch (MO.getType()) { case MachineOperand::MO_VirtualRegister: - if (Value *V = MO.getVRegValueOrNull()) { - O << "<" << V->getName() << ">"; - return; - } - // FALLTHROUGH - case MachineOperand::MO_MachineRegister: if (MRegisterInfo::isPhysicalRegister(MO.getReg())) O << RI.get(MO.getReg()).Name; else Index: llvm/lib/Target/X86/X86IntelAsmPrinter.h diff -u llvm/lib/Target/X86/X86IntelAsmPrinter.h:1.19 llvm/lib/Target/X86/X86IntelAsmPrinter.h:1.20 --- llvm/lib/Target/X86/X86IntelAsmPrinter.h:1.19 Mon May 1 22:58:45 2006 +++ llvm/lib/Target/X86/X86IntelAsmPrinter.h Wed May 3 20:15:02 2006 @@ -37,8 +37,8 @@ void printOperand(const MachineInstr *MI, unsigned OpNo, const char *Modifier = 0) { const MachineOperand &MO = MI->getOperand(OpNo); - if (MO.getType() == MachineOperand::MO_MachineRegister) { - assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physref??"); + if (MO.getType() == MachineOperand::MO_VirtualRegister) { + assert(MRegisterInfo::isPhysicalRegister(MO.getReg()) && "Not physreg??"); O << TM.getRegisterInfo()->get(MO.getReg()).Name; } else { printOp(MO, Modifier); Index: llvm/lib/Target/X86/X86RegisterInfo.cpp diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.145 llvm/lib/Target/X86/X86RegisterInfo.cpp:1.146 --- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.145 Thu Apr 27 21:23:35 2006 +++ llvm/lib/Target/X86/X86RegisterInfo.cpp Wed May 3 20:15:02 2006 @@ -150,7 +150,7 @@ else if (MI->getOperand(1).isGlobalAddress()) return addFrameReference(BuildMI(Opcode, 5), FrameIndex) .addGlobalAddress(MI->getOperand(1).getGlobal(), - false, MI->getOperand(1).getOffset()); + MI->getOperand(1).getOffset()); else if (MI->getOperand(1).isJumpTableIndex()) return addFrameReference(BuildMI(Opcode, 5), FrameIndex) .addJumpTableIndex(MI->getOperand(1).getJumpTableIndex()); From lattner at cs.uiuc.edu Wed May 3 20:15:20 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 3 May 2006 20:15:20 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Message-ID: <200605040115.UAA31852@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: ScheduleDAG.cpp updated: 1.83 -> 1.84 --- Log message: Remove a bunch more SparcV9 specific stuff --- Diffs of the changes: (+5 -5) ScheduleDAG.cpp | 10 +++++----- 1 files changed, 5 insertions(+), 5 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.83 llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.84 --- llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.83 Tue May 2 20:29:56 2006 +++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Wed May 3 20:15:02 2006 @@ -110,7 +110,7 @@ MI->addRegOperand(R->getReg(), MachineOperand::Use); } else if (GlobalAddressSDNode *TGA = dyn_cast(Op)) { - MI->addGlobalAddressOperand(TGA->getGlobal(), false, TGA->getOffset()); + MI->addGlobalAddressOperand(TGA->getGlobal(), TGA->getOffset()); } else if (BasicBlockSDNode *BB = dyn_cast(Op)) { MI->addMachineBasicBlockOperand(BB->getBasicBlock()); @@ -143,7 +143,7 @@ MI->addConstantPoolIndexOperand(Idx, Offset); } else if (ExternalSymbolSDNode *ES = dyn_cast(Op)) { - MI->addExternalSymbolOperand(ES->getSymbol(), false); + MI->addExternalSymbolOperand(ES->getSymbol()); } else { assert(Op.getValueType() != MVT::Other && Op.getValueType() != MVT::Flag && @@ -296,7 +296,7 @@ // Add the asm string as an external symbol operand. const char *AsmStr = cast(Node->getOperand(1))->getSymbol(); - MI->addExternalSymbolOperand(AsmStr, false); + MI->addExternalSymbolOperand(AsmStr); // Add all of the operand registers to the instruction. for (unsigned i = 2; i != NumOps;) { @@ -311,13 +311,13 @@ case 1: // Use of register. for (; NumVals; --NumVals, ++i) { unsigned Reg = cast(Node->getOperand(i))->getReg(); - MI->addMachineRegOperand(Reg, MachineOperand::Use); + MI->addRegOperand(Reg, MachineOperand::Use); } break; case 2: // Def of register. for (; NumVals; --NumVals, ++i) { unsigned Reg = cast(Node->getOperand(i))->getReg(); - MI->addMachineRegOperand(Reg, MachineOperand::Def); + MI->addRegOperand(Reg, MachineOperand::Def); } break; case 3: { // Immediate. From lattner at cs.uiuc.edu Wed May 3 20:15:21 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 3 May 2006 20:15:21 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp AlphaRegisterInfo.cpp Message-ID: <200605040115.UAA31858@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Alpha: AlphaAsmPrinter.cpp updated: 1.38 -> 1.39 AlphaRegisterInfo.cpp updated: 1.40 -> 1.41 --- Log message: Remove a bunch more SparcV9 specific stuff --- Diffs of the changes: (+3 -8) AlphaAsmPrinter.cpp | 8 +------- AlphaRegisterInfo.cpp | 3 ++- 2 files changed, 3 insertions(+), 8 deletions(-) Index: llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp diff -u llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.38 llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.39 --- llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.38 Wed May 3 19:49:59 2006 +++ llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp Wed May 3 20:15:02 2006 @@ -77,7 +77,7 @@ void AlphaAsmPrinter::printOperand(const MachineInstr *MI, int opNum) { const MachineOperand &MO = MI->getOperand(opNum); - if (MO.getType() == MachineOperand::MO_MachineRegister) { + if (MO.getType() == MachineOperand::MO_VirtualRegister) { assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??"); O << TM.getRegisterInfo()->get(MO.getReg()).Name; } else if (MO.isImmediate()) { @@ -94,12 +94,6 @@ switch (MO.getType()) { case MachineOperand::MO_VirtualRegister: - if (Value *V = MO.getVRegValueOrNull()) { - O << "<" << V->getName() << ">"; - return; - } - // FALLTHROUGH - case MachineOperand::MO_MachineRegister: O << RI.get(MO.getReg()).Name; return; Index: llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp diff -u llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.40 llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.41 --- llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.40 Fri Apr 7 11:34:45 2006 +++ llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp Wed May 3 20:15:02 2006 @@ -263,7 +263,8 @@ .addReg(Alpha::R29).addImm(curgpdist); //evil const_cast until MO stuff setup to handle const - BuildMI(MBB, MBBI, Alpha::ALTENT, 1).addGlobalAddress(const_cast(MF.getFunction()), true); + BuildMI(MBB, MBBI, Alpha::ALTENT, 1) + .addGlobalAddress(const_cast(MF.getFunction())); // Get the number of bytes to allocate from the FrameInfo long NumBytes = MFI->getStackSize(); From lattner at cs.uiuc.edu Wed May 3 20:15:20 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 3 May 2006 20:15:20 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineInstr.h MachineInstrBuilder.h Message-ID: <200605040115.UAA31842@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineInstr.h updated: 1.170 -> 1.171 MachineInstrBuilder.h updated: 1.31 -> 1.32 --- Log message: Remove a bunch more SparcV9 specific stuff --- Diffs of the changes: (+13 -93) MachineInstr.h | 82 ++++++-------------------------------------------- MachineInstrBuilder.h | 24 +------------- 2 files changed, 13 insertions(+), 93 deletions(-) Index: llvm/include/llvm/CodeGen/MachineInstr.h diff -u llvm/include/llvm/CodeGen/MachineInstr.h:1.170 llvm/include/llvm/CodeGen/MachineInstr.h:1.171 --- llvm/include/llvm/CodeGen/MachineInstr.h:1.170 Wed May 3 19:49:59 2006 +++ llvm/include/llvm/CodeGen/MachineInstr.h Wed May 3 20:15:02 2006 @@ -58,9 +58,6 @@ // - Reg will be of virtual register type MO_MInstrVirtualReg. The field // MachineInstr* minstr will point to the instruction that computes reg. // -// - %sp will be of virtual register type MO_MachineReg. -// The field regNum identifies the machine register. -// // - NumElements will be of virtual register type MO_VirtualReg. // The field Value* value identifies the value. // @@ -75,7 +72,6 @@ enum { DEFFLAG = 0x01, // this is a def of the operand USEFLAG = 0x02, // this is a use of the operand - PCRELATIVE = 0x40 // Operand is relative to PC, not a global address }; public: @@ -93,7 +89,6 @@ enum MachineOperandType { MO_VirtualRegister, // virtual register for *value - MO_MachineRegister, // pre-assigned machine register `regNum' MO_SignExtendedImmed, MO_UnextendedImmed, MO_MachineBasicBlock, // MachineBasicBlock reference @@ -152,18 +147,9 @@ extra.regNum = Reg; } - MachineOperand(Value *V, MachineOperandType OpTy, UseType UseTy, - bool isPCRelative = false) - : flags(UseTy | (isPCRelative?PCRELATIVE:0)), opType(OpTy) { - assert(OpTy != MachineOperand::MO_GlobalAddress); - zeroContents(); - contents.value = V; - extra.regNum = -1; - } - MachineOperand(GlobalValue *V, MachineOperandType OpTy, UseType UseTy, - bool isPCRelative = false, int Offset = 0) - : flags(UseTy | (isPCRelative?PCRELATIVE:0)), opType(OpTy) { + int Offset = 0) + : flags(UseTy), opType(OpTy) { assert(OpTy == MachineOperand::MO_GlobalAddress); zeroContents (); contents.value = (Value*)V; @@ -177,8 +163,8 @@ extra.regNum = -1; } - MachineOperand(const char *SymName, bool isPCRelative, int Offset) - : flags(isPCRelative?PCRELATIVE:0), opType(MO_ExternalSymbol) { + MachineOperand(const char *SymName, int Offset) + : flags(0), opType(MO_ExternalSymbol) { zeroContents (); contents.SymbolName = SymName; extra.offset = Offset; @@ -192,7 +178,6 @@ extra = M.extra; } - ~MachineOperand() {} const MachineOperand &operator=(const MachineOperand &MO) { @@ -218,7 +203,7 @@ /// Note: The sparc backend should not use this method. /// bool isRegister() const { - return opType == MO_MachineRegister || opType == MO_VirtualRegister; + return opType == MO_VirtualRegister; } /// Accessors that tell you what kind of MachineOperand you're looking at. @@ -247,10 +232,6 @@ assert(opType == MO_VirtualRegister && "Wrong MachineOperand accessor"); return contents.value; } - int getMachineRegNum() const { - assert(opType == MO_MachineRegister && "Wrong MachineOperand accessor"); - return extra.regNum; - } int64_t getImmedValue() const { assert(isImmediate() && "Wrong MachineOperand accessor"); return contents.immedVal; @@ -301,8 +282,7 @@ /// allocated to this operand. /// bool hasAllocatedReg() const { - return (extra.regNum >= 0 && - (opType == MO_VirtualRegister || opType == MO_MachineRegister)); + return extra.regNum >= 0 && opType == MO_VirtualRegister; } /// getReg - Returns the register number. It is a runtime error to call this @@ -445,28 +425,6 @@ // Accessors to add operands when building up machine instructions // - /// addRegOperand - Add a MO_VirtualRegister operand to the end of the - /// operands list... - /// - void addRegOperand(Value *V, bool isDef, bool isDefAndUse=false) { - assert(!OperandsComplete() && - "Trying to add an operand to a machine instr that is already done!"); - operands.push_back( - MachineOperand(V, MachineOperand::MO_VirtualRegister, - !isDef ? MachineOperand::Use : - (isDefAndUse ? MachineOperand::UseAndDef : - MachineOperand::Def))); - } - - void addRegOperand(Value *V, - MachineOperand::UseType UTy = MachineOperand::Use, - bool isPCRelative = false) { - assert(!OperandsComplete() && - "Trying to add an operand to a machine instr that is already done!"); - operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister, - UTy, isPCRelative)); - } - /// addRegOperand - Add a symbolic virtual register reference... /// void addRegOperand(int reg, bool isDef) { @@ -487,26 +445,6 @@ MachineOperand(reg, MachineOperand::MO_VirtualRegister, UTy)); } - /// addMachineRegOperand - Add a virtual register operand to this MachineInstr - /// - void addMachineRegOperand(int reg, bool isDef) { - assert(!OperandsComplete() && - "Trying to add an operand to a machine instr that is already done!"); - operands.push_back( - MachineOperand(reg, MachineOperand::MO_MachineRegister, - isDef ? MachineOperand::Def : MachineOperand::Use)); - } - - /// addMachineRegOperand - Add a virtual register operand to this MachineInstr - /// - void addMachineRegOperand(int reg, - MachineOperand::UseType UTy = MachineOperand::Use) { - assert(!OperandsComplete() && - "Trying to add an operand to a machine instr that is already done!"); - operands.push_back( - MachineOperand(reg, MachineOperand::MO_MachineRegister, UTy)); - } - /// addZeroExtImmOperand - Add a zero extended constant argument to the /// machine instruction. /// @@ -569,18 +507,18 @@ operands.push_back(MachineOperand(I, MachineOperand::MO_JumpTableIndex)); } - void addGlobalAddressOperand(GlobalValue *GV, bool isPCRelative, int Offset) { + void addGlobalAddressOperand(GlobalValue *GV, int Offset) { assert(!OperandsComplete() && "Trying to add an operand to a machine instr that is already done!"); operands.push_back( MachineOperand(GV, MachineOperand::MO_GlobalAddress, - MachineOperand::Use, isPCRelative, Offset)); + MachineOperand::Use, Offset)); } /// addExternalSymbolOperand - Add an external symbol operand to this instr /// - void addExternalSymbolOperand(const char *SymName, bool isPCRelative) { - operands.push_back(MachineOperand(SymName, isPCRelative, 0)); + void addExternalSymbolOperand(const char *SymName) { + operands.push_back(MachineOperand(SymName, 0)); } //===--------------------------------------------------------------------===// Index: llvm/include/llvm/CodeGen/MachineInstrBuilder.h diff -u llvm/include/llvm/CodeGen/MachineInstrBuilder.h:1.31 llvm/include/llvm/CodeGen/MachineInstrBuilder.h:1.32 --- llvm/include/llvm/CodeGen/MachineInstrBuilder.h:1.31 Wed May 3 19:44:25 2006 +++ llvm/include/llvm/CodeGen/MachineInstrBuilder.h Wed May 3 20:15:02 2006 @@ -46,22 +46,6 @@ return *this; } - /// addReg - Add an LLVM value that is to be used as a register... - /// - const MachineInstrBuilder &addReg( - Value *V, - MachineOperand::UseType Ty = MachineOperand::Use) const { - MI->addRegOperand(V, Ty); - return *this; - } - - /// addRegDef - Add an LLVM value that is to be defined as a register... this - /// is the same as addReg(V, MachineOperand::Def). - /// - const MachineInstrBuilder &addRegDef(Value *V) const { - return addReg(V, MachineOperand::Def); - } - /// addImm - Add a new immediate operand. /// const MachineInstrBuilder &addImm(int Val) const { @@ -112,15 +96,13 @@ } const MachineInstrBuilder &addGlobalAddress(GlobalValue *GV, - bool isPCRelative = false, int Offset = 0) const { - MI->addGlobalAddressOperand(GV, isPCRelative, Offset); + MI->addGlobalAddressOperand(GV, Offset); return *this; } - const MachineInstrBuilder &addExternalSymbol(const char *FnName, - bool isPCRelative = false) const{ - MI->addExternalSymbolOperand(FnName, isPCRelative); + const MachineInstrBuilder &addExternalSymbol(const char *FnName) const{ + MI->addExternalSymbolOperand(FnName); return *this; } }; From lattner at cs.uiuc.edu Wed May 3 20:15:20 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 3 May 2006 20:15:20 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcAsmPrinter.cpp Message-ID: <200605040115.UAA31846@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Sparc: SparcAsmPrinter.cpp updated: 1.61 -> 1.62 --- Log message: Remove a bunch more SparcV9 specific stuff --- Diffs of the changes: (+1 -8) SparcAsmPrinter.cpp | 9 +-------- 1 files changed, 1 insertion(+), 8 deletions(-) Index: llvm/lib/Target/Sparc/SparcAsmPrinter.cpp diff -u llvm/lib/Target/Sparc/SparcAsmPrinter.cpp:1.61 llvm/lib/Target/Sparc/SparcAsmPrinter.cpp:1.62 --- llvm/lib/Target/Sparc/SparcAsmPrinter.cpp:1.61 Wed May 3 19:44:25 2006 +++ llvm/lib/Target/Sparc/SparcAsmPrinter.cpp Wed May 3 20:15:02 2006 @@ -147,12 +147,6 @@ } switch (MO.getType()) { case MachineOperand::MO_VirtualRegister: - if (Value *V = MO.getVRegValueOrNull()) { - O << "<" << V->getName() << ">"; - break; - } - // FALLTHROUGH - case MachineOperand::MO_MachineRegister: if (MRegisterInfo::isPhysicalRegister(MO.getReg())) O << "%" << LowercaseString (RI.get(MO.getReg()).Name); else @@ -195,8 +189,7 @@ MachineOperand::MachineOperandType OpTy = MI->getOperand(opNum+1).getType(); - if ((OpTy == MachineOperand::MO_VirtualRegister || - OpTy == MachineOperand::MO_MachineRegister) && + if (OpTy == MachineOperand::MO_VirtualRegister && MI->getOperand(opNum+1).getReg() == SP::G0) return; // don't print "+%g0" if ((OpTy == MachineOperand::MO_SignExtendedImmed || From lattner at cs.uiuc.edu Wed May 3 20:26:52 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 3 May 2006 20:26:52 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineInstr.h Message-ID: <200605040126.UAA31959@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineInstr.h updated: 1.171 -> 1.172 --- Log message: Remove a bunch more dead V9 specific stuff --- Diffs of the changes: (+7 -70) MachineInstr.h | 77 +++++---------------------------------------------------- 1 files changed, 7 insertions(+), 70 deletions(-) Index: llvm/include/llvm/CodeGen/MachineInstr.h diff -u llvm/include/llvm/CodeGen/MachineInstr.h:1.171 llvm/include/llvm/CodeGen/MachineInstr.h:1.172 --- llvm/include/llvm/CodeGen/MachineInstr.h:1.171 Wed May 3 20:15:02 2006 +++ llvm/include/llvm/CodeGen/MachineInstr.h Wed May 3 20:26:39 2006 @@ -37,35 +37,8 @@ //===----------------------------------------------------------------------===// // class MachineOperand // -// Purpose: // Representation of each machine instruction operand. -// This class is designed so that you can allocate a vector of operands -// first and initialize each one later. -// -// E.g, for this VM instruction: -// ptr = alloca type, numElements -// we generate 2 machine instructions on the SPARC: -// -// mul Constant, Numelements -> Reg -// add %sp, Reg -> Ptr -// -// Each instruction has 3 operands, listed above. Of those: -// - Reg, NumElements, and Ptr are of operand type MO_Register. -// - Constant is of operand type MO_SignExtendedImmed on the SPARC. -// -// For the register operands, the virtual register type is as follows: -// -// - Reg will be of virtual register type MO_MInstrVirtualReg. The field -// MachineInstr* minstr will point to the instruction that computes reg. // -// - NumElements will be of virtual register type MO_VirtualReg. -// The field Value* value identifies the value. -// -// - Ptr will also be of virtual register type MO_VirtualReg. -// Again, the field Value* value identifies the value. -// -//===----------------------------------------------------------------------===// - struct MachineOperand { private: // Bit fields of the flags variable used for different operand properties @@ -130,15 +103,11 @@ memset (&extra, 0, sizeof (extra)); } - MachineOperand(int64_t ImmVal = 0, - MachineOperandType OpTy = MO_VirtualRegister, int Offset = 0) + MachineOperand(int64_t ImmVal, MachineOperandType OpTy, int Offset = 0) : flags(0), opType(OpTy) { zeroContents (); contents.immedVal = ImmVal; - if (OpTy == MachineOperand::MO_ConstantPoolIndex) - extra.offset = Offset; - else - extra.regNum = -1; + extra.offset = Offset; } MachineOperand(int Reg, MachineOperandType OpTy, UseType UseTy) @@ -147,10 +116,8 @@ extra.regNum = Reg; } - MachineOperand(GlobalValue *V, MachineOperandType OpTy, UseType UseTy, - int Offset = 0) - : flags(UseTy), opType(OpTy) { - assert(OpTy == MachineOperand::MO_GlobalAddress); + MachineOperand(GlobalValue *V, int Offset = 0) + : flags(MachineOperand::Use), opType(MachineOperand::MO_GlobalAddress) { zeroContents (); contents.value = (Value*)V; extra.offset = Offset; @@ -160,7 +127,6 @@ : flags(0), opType(MO_MachineBasicBlock) { zeroContents (); contents.MBB = mbb; - extra.regNum = -1; } MachineOperand(const char *SymName, int Offset) @@ -196,11 +162,7 @@ /// UseType getUseType() const { return UseType(flags & (USEFLAG|DEFFLAG)); } - /// isRegister - Return true if this operand is a register operand. The X86 - /// backend currently can't decide whether to use MO_MR or MO_VR to represent - /// them, so we accept both. - /// - /// Note: The sparc backend should not use this method. + /// isRegister - Return true if this operand is a register operand. /// bool isRegister() const { return opType == MO_VirtualRegister; @@ -218,20 +180,6 @@ bool isGlobalAddress() const { return opType == MO_GlobalAddress; } bool isExternalSymbol() const { return opType == MO_ExternalSymbol; } - /// getVRegValueOrNull - Get the Value* out of a MachineOperand if it - /// has one. This is deprecated and only used by the SPARC v9 backend. - /// - Value* getVRegValueOrNull() const { - return opType == MO_VirtualRegister ? contents.value : NULL; - } - - /// MachineOperand accessors that only work on certain types of - /// MachineOperand... - /// - Value* getVRegValue() const { - assert(opType == MO_VirtualRegister && "Wrong MachineOperand accessor"); - return contents.value; - } int64_t getImmedValue() const { assert(isImmediate() && "Wrong MachineOperand accessor"); return contents.immedVal; @@ -293,20 +241,13 @@ return extra.regNum; } - /// MachineOperand mutators... + /// MachineOperand mutators. /// void setReg(unsigned Reg) { - // This method's comment used to say: 'TODO: get rid of this duplicate - // code.' It's not clear where the duplication is. assert(hasAllocatedReg() && "This operand cannot have a register number!"); extra.regNum = Reg; } - void setValueReg(Value *val) { - assert(getVRegValueOrNull() != 0 && "Original operand must of type Value*"); - contents.value = val; - } - void setImmedValue(int immVal) { assert(isImmediate() && "Wrong MachineOperand mutator"); contents.immedVal = immVal; @@ -362,8 +303,6 @@ friend struct ilist_traits; public: - MachineInstr(short Opcode, unsigned numOperands); - /// MachineInstr ctor - This constructor only does a _reserve_ of the /// operands, not a resize for them. It is expected that if you use this that /// you call add* methods below to fill up the operands, instead of the Set @@ -510,9 +449,7 @@ void addGlobalAddressOperand(GlobalValue *GV, int Offset) { assert(!OperandsComplete() && "Trying to add an operand to a machine instr that is already done!"); - operands.push_back( - MachineOperand(GV, MachineOperand::MO_GlobalAddress, - MachineOperand::Use, Offset)); + operands.push_back(MachineOperand(GV, Offset)); } /// addExternalSymbolOperand - Add an external symbol operand to this instr From lattner at cs.uiuc.edu Wed May 3 20:26:53 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 3 May 2006 20:26:53 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/LiveVariables.cpp MachineBasicBlock.cpp MachineInstr.cpp Message-ID: <200605040126.UAA31969@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: LiveVariables.cpp updated: 1.54 -> 1.55 MachineBasicBlock.cpp updated: 1.25 -> 1.26 MachineInstr.cpp updated: 1.114 -> 1.115 --- Log message: Remove a bunch more dead V9 specific stuff --- Diffs of the changes: (+9 -34) LiveVariables.cpp | 14 ++++++-------- MachineBasicBlock.cpp | 2 +- MachineInstr.cpp | 27 ++------------------------- 3 files changed, 9 insertions(+), 34 deletions(-) Index: llvm/lib/CodeGen/LiveVariables.cpp diff -u llvm/lib/CodeGen/LiveVariables.cpp:1.54 llvm/lib/CodeGen/LiveVariables.cpp:1.55 --- llvm/lib/CodeGen/LiveVariables.cpp:1.54 Tue Jan 3 23:40:30 2006 +++ llvm/lib/CodeGen/LiveVariables.cpp Wed May 3 20:26:39 2006 @@ -296,14 +296,12 @@ "Didn't find an entry for our predecessor??"); if (MI->getOperand(i+1).getMachineBasicBlock() == MBB) { MachineOperand &MO = MI->getOperand(i); - if (!MO.getVRegValueOrNull()) { - VarInfo &VRInfo = getVarInfo(MO.getReg()); - assert(VRInfo.DefInst && "Register use before def (or no def)!"); - - // Only mark it alive only in the block we are representing. - MarkVirtRegAliveInBlock(VRInfo, MBB); - break; // Found the PHI entry for this block. - } + VarInfo &VRInfo = getVarInfo(MO.getReg()); + assert(VRInfo.DefInst && "Register use before def (or no def)!"); + + // Only mark it alive only in the block we are representing. + MarkVirtRegAliveInBlock(VRInfo, MBB); + break; // Found the PHI entry for this block. } } } Index: llvm/lib/CodeGen/MachineBasicBlock.cpp diff -u llvm/lib/CodeGen/MachineBasicBlock.cpp:1.25 llvm/lib/CodeGen/MachineBasicBlock.cpp:1.26 --- llvm/lib/CodeGen/MachineBasicBlock.cpp:1.25 Thu Apr 21 17:33:33 2005 +++ llvm/lib/CodeGen/MachineBasicBlock.cpp Wed May 3 20:26:39 2006 @@ -47,7 +47,7 @@ MachineInstr* ilist_traits::createSentinel() { - MachineInstr* dummy = new MachineInstr(0, 0); + MachineInstr* dummy = new MachineInstr(0, 0, true, true); LeakDetector::removeGarbageObject(dummy); return dummy; } Index: llvm/lib/CodeGen/MachineInstr.cpp diff -u llvm/lib/CodeGen/MachineInstr.cpp:1.114 llvm/lib/CodeGen/MachineInstr.cpp:1.115 --- llvm/lib/CodeGen/MachineInstr.cpp:1.114 Wed May 3 20:15:02 2006 +++ llvm/lib/CodeGen/MachineInstr.cpp Wed May 3 20:26:39 2006 @@ -36,15 +36,6 @@ extern const TargetInstrDescriptor *TargetInstrDescriptors; } -// Constructor for instructions with variable #operands -MachineInstr::MachineInstr(short opcode, unsigned numOperands) - : Opcode(opcode), - operands(numOperands, MachineOperand()), - parent(0) { - // Make sure that we get added to a machine basicblock - LeakDetector::addGarbageObject(this); -} - /// MachineInstr ctor - This constructor only does a _reserve_ of the operands, /// not a resize for them. It is expected that if you use this that you call /// add* methods below to fill up the operands, instead of the Set methods. @@ -178,14 +169,7 @@ switch (MO.getType()) { case MachineOperand::MO_VirtualRegister: - if (MO.getVRegValue()) { - OS << "%reg"; - OutputValue(OS, MO.getVRegValue()); - if (MO.hasAllocatedReg()) - OS << "=="; - } - if (MO.hasAllocatedReg()) - OutputReg(OS, MO.getReg(), MRI); + OutputReg(OS, MO.getReg(), MRI); break; case MachineOperand::MO_SignExtendedImmed: OS << (long)MO.getImmedValue(); @@ -285,14 +269,7 @@ std::ostream &llvm::operator<<(std::ostream &OS, const MachineOperand &MO) { switch (MO.getType()) { case MachineOperand::MO_VirtualRegister: - if (MO.hasAllocatedReg()) - OutputReg(OS, MO.getReg()); - - if (MO.getVRegValue()) { - if (MO.hasAllocatedReg()) OS << "=="; - OS << "%vreg"; - OutputValue(OS, MO.getVRegValue()); - } + OutputReg(OS, MO.getReg()); break; case MachineOperand::MO_SignExtendedImmed: OS << (long)MO.getImmedValue(); From lattner at cs.uiuc.edu Wed May 3 20:26:53 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 3 May 2006 20:26:53 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86CodeEmitter.cpp Message-ID: <200605040126.UAA31967@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86CodeEmitter.cpp updated: 1.105 -> 1.106 --- Log message: Remove a bunch more dead V9 specific stuff --- Diffs of the changes: (+1 -6) X86CodeEmitter.cpp | 7 +------ 1 files changed, 1 insertion(+), 6 deletions(-) Index: llvm/lib/Target/X86/X86CodeEmitter.cpp diff -u llvm/lib/Target/X86/X86CodeEmitter.cpp:1.105 llvm/lib/Target/X86/X86CodeEmitter.cpp:1.106 --- llvm/lib/Target/X86/X86CodeEmitter.cpp:1.105 Wed May 3 19:49:59 2006 +++ llvm/lib/Target/X86/X86CodeEmitter.cpp Wed May 3 20:26:39 2006 @@ -432,12 +432,7 @@ MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(0).getReg())); if (MI.getNumOperands() == 2) { const MachineOperand &MO1 = MI.getOperand(1); - if (Value *V = MO1.getVRegValueOrNull()) { - assert(0 && "??"); - assert(sizeOfImm(Desc) == 4 && - "Don't know how to emit non-pointer values!"); - emitGlobalAddressForPtr(cast(V)); - } else if (MO1.isGlobalAddress()) { + if (MO1.isGlobalAddress()) { assert(sizeOfImm(Desc) == 4 && "Don't know how to emit non-pointer values!"); emitGlobalAddressForPtr(MO1.getGlobal(), MO1.getOffset()); From jeffc at jolt-lang.org Thu May 4 11:19:52 2006 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Thu, 4 May 2006 11:19:52 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86AsmPrinter.cpp Message-ID: <200605041619.LAA11200@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86AsmPrinter.cpp updated: 1.176 -> 1.177 --- Log message: Make Intel syntax the default when LLVM is built with VC++. --- Diffs of the changes: (+6 -1) X86AsmPrinter.cpp | 7 ++++++- 1 files changed, 6 insertions(+), 1 deletion(-) Index: llvm/lib/Target/X86/X86AsmPrinter.cpp diff -u llvm/lib/Target/X86/X86AsmPrinter.cpp:1.176 llvm/lib/Target/X86/X86AsmPrinter.cpp:1.177 --- llvm/lib/Target/X86/X86AsmPrinter.cpp:1.176 Tue May 2 20:29:57 2006 +++ llvm/lib/Target/X86/X86AsmPrinter.cpp Thu May 4 11:19:27 2006 @@ -37,7 +37,12 @@ clEnumVal(att, " Emit AT&T-style assembly"), clEnumVal(intel, " Emit Intel-style assembly"), clEnumValEnd), - cl::init(att)); +#ifdef _MSC_VER + cl::init(intel) +#else + cl::init(att) +#endif + ); /// doInitialization bool X86SharedAsmPrinter::doInitialization(Module &M) { From jeffc at jolt-lang.org Thu May 4 11:20:35 2006 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Thu, 4 May 2006 11:20:35 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86IntelAsmPrinter.cpp Message-ID: <200605041620.LAA11217@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86IntelAsmPrinter.cpp updated: 1.38 -> 1.39 --- Log message: Make external globals public; other minor cleanup. --- Diffs of the changes: (+17 -15) X86IntelAsmPrinter.cpp | 32 +++++++++++++++++--------------- 1 files changed, 17 insertions(+), 15 deletions(-) Index: llvm/lib/Target/X86/X86IntelAsmPrinter.cpp diff -u llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.38 llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.39 --- llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.38 Wed May 3 20:15:02 2006 +++ llvm/lib/Target/X86/X86IntelAsmPrinter.cpp Thu May 4 11:20:22 2006 @@ -24,20 +24,6 @@ X86IntelAsmPrinter::X86IntelAsmPrinter(std::ostream &O, X86TargetMachine &TM) : X86SharedAsmPrinter(O, TM) { - CommentString = ";"; - GlobalPrefix = "_"; - PrivateGlobalPrefix = "$"; - AlignDirective = "\talign\t"; - MLSections = true; - ZeroDirective = "\tdb\t"; - ZeroDirectiveSuffix = " dup(0)"; - AsciiDirective = "\tdb\t"; - AscizDirective = 0; - Data8bitsDirective = "\t.db\t"; - Data16bitsDirective = "\t.dw\t"; - Data32bitsDirective = "\t.dd\t"; - Data64bitsDirective = "\t.dq\t"; - HasDotTypeDotSizeDirective = false; } /// runOnMachineFunction - This uses the printMachineInstruction() @@ -413,8 +399,22 @@ bool X86IntelAsmPrinter::doInitialization(Module &M) { X86SharedAsmPrinter::doInitialization(M); + CommentString = ";"; + GlobalPrefix = "_"; + PrivateGlobalPrefix = "$"; + AlignDirective = "\talign\t"; + MLSections = true; + ZeroDirective = "\tdb\t"; + ZeroDirectiveSuffix = " dup(0)"; + AsciiDirective = "\tdb\t"; + AscizDirective = 0; + Data8bitsDirective = "\t.db\t"; + Data16bitsDirective = "\t.dw\t"; + Data32bitsDirective = "\t.dd\t"; + Data64bitsDirective = "\t.dq\t"; + HasDotTypeDotSizeDirective = false; Mang->markCharUnacceptable('.'); - PrivateGlobalPrefix = "$"; // need this here too :( + O << "\t.686\n\t.model flat\n\n"; // Emit declarations for external functions. @@ -427,6 +427,8 @@ I != E; ++I) { if (I->isExternal()) O << "\textern " << Mang->getValueName(I) << ":byte\n"; + else if (I->getLinkage() == GlobalValue::ExternalLinkage) + O << "\tpublic " << Mang->getValueName(I) << "\n"; } return false; From lattner at cs.uiuc.edu Thu May 4 11:56:58 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 4 May 2006 11:56:58 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp PPCRegisterInfo.td Message-ID: <200605041656.LAA11906@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCRegisterInfo.cpp updated: 1.62 -> 1.63 PPCRegisterInfo.td updated: 1.35 -> 1.36 --- Log message: Revert Nate's CR patch from last night, which caused many regressions (e.g. fhourstones). Loading and storing off R0 isn't what we wanted. Also, taking some CR's out of CRRC seems to cause failures as well. Further investigation is required. --- Diffs of the changes: (+9 -26) PPCRegisterInfo.cpp | 14 ++++++-------- PPCRegisterInfo.td | 21 +++------------------ 2 files changed, 9 insertions(+), 26 deletions(-) Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.62 llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.63 --- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.62 Tue May 2 12:37:31 2006 +++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Thu May 4 11:56:45 2006 @@ -102,9 +102,8 @@ BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11); addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx); } else if (RC == PPC::CRRCRegisterClass) { - // FIXME: We use R0 here, because it isn't available for RA. - BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R0); - addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R0), FrameIdx); + BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R11); + addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx); } else if (RC == PPC::GPRCRegisterClass) { addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(SrcReg),FrameIdx); } else if (RC == PPC::G8RCRegisterClass) { @@ -119,7 +118,7 @@ // Dest = LVX R0, R11 // // FIXME: We use R0 here, because it isn't available for RA. - addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 2, PPC::R0), FrameIdx, 0, 0); + addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0); BuildMI(MBB, MI, PPC::STVX, 3) .addReg(SrcReg).addReg(PPC::R0).addReg(PPC::R0); } else { @@ -137,9 +136,8 @@ addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx); BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11); } else if (RC == PPC::CRRCRegisterClass) { - // FIXME: We use R0 here, because it isn't available for RA. - addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R0), FrameIdx); - BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R0); + addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx); + BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R11); } else if (RC == PPC::GPRCRegisterClass) { addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, DestReg), FrameIdx); } else if (RC == PPC::G8RCRegisterClass) { @@ -154,7 +152,7 @@ // Dest = LVX R0, R11 // // FIXME: We use R0 here, because it isn't available for RA. - addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 2, PPC::R0), FrameIdx, 0, 0); + addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0); BuildMI(MBB, MI, PPC::LVX, 2, DestReg).addReg(PPC::R0).addReg(PPC::R0); } else { assert(0 && "Unknown regclass!"); Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.td diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.td:1.35 llvm/lib/Target/PowerPC/PPCRegisterInfo.td:1.36 --- llvm/lib/Target/PowerPC/PPCRegisterInfo.td:1.35 Tue May 2 12:37:31 2006 +++ llvm/lib/Target/PowerPC/PPCRegisterInfo.td Thu May 4 11:56:45 2006 @@ -264,21 +264,6 @@ V6, V7, V8, V9, V10, V11, V12, V13, V14, V15, V16, V17, V18, V19, V20, V21, V22, V23, V24, V25, V26, V27, V28, V29, V30, V31]>; -def CRRC : RegisterClass<"PPC", [i32], 32, [CR0, CR1, CR5, CR6, CR7, CR2, CR3, CR4]> -{ - let MethodProtos = [{ - iterator allocation_order_begin(MachineFunction &MF) const; - iterator allocation_order_end(MachineFunction &MF) const; - }]; - let MethodBodies = [{ - CRRCClass::iterator - CRRCClass::allocation_order_begin(MachineFunction &MF) const { - return begin(); - } - CRRCClass::iterator - CRRCClass::allocation_order_end(MachineFunction &MF) const { - return end()-3; - } - }]; -} - +def CRRC : RegisterClass<"PPC", [i32], 32, [CR0, CR1, CR5, CR6, CR7, CR2, + CR3, CR4]>; + From lattner at cs.uiuc.edu Thu May 4 12:03:04 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 4 May 2006 12:03:04 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineInstr.h MachineInstrBuilder.h Message-ID: <200605041703.MAA13691@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineInstr.h updated: 1.172 -> 1.173 MachineInstrBuilder.h updated: 1.32 -> 1.33 --- Log message: Change "value" in MachineOperand to be a GlobalValue, as that is the only thing that can be in it. Remove a dead method. --- Diffs of the changes: (+12 -33) MachineInstr.h | 37 +++++++++++-------------------------- MachineInstrBuilder.h | 8 +------- 2 files changed, 12 insertions(+), 33 deletions(-) Index: llvm/include/llvm/CodeGen/MachineInstr.h diff -u llvm/include/llvm/CodeGen/MachineInstr.h:1.172 llvm/include/llvm/CodeGen/MachineInstr.h:1.173 --- llvm/include/llvm/CodeGen/MachineInstr.h:1.172 Wed May 3 20:26:39 2006 +++ llvm/include/llvm/CodeGen/MachineInstr.h Thu May 4 12:02:50 2006 @@ -74,15 +74,8 @@ private: union { - Value* value; // BasicBlockVal for a label operand. - // ConstantVal for a non-address immediate. - // Virtual register for an SSA operand, - // including hidden operands required for - // the generated machine code. - // LLVM global for MO_GlobalAddress. - + GlobalValue *GV; // LLVM global for MO_GlobalAddress. int64_t immedVal; // Constant value for an explicit constant - MachineBasicBlock *MBB; // For MO_MachineBasicBlock type const char *SymbolName; // For MO_ExternalSymbol type } contents; @@ -90,36 +83,32 @@ char flags; // see bit field definitions above MachineOperandType opType:8; // Pack into 8 bits efficiently after flags. union { - int regNum; // register number for an explicit register - // will be set for a value after reg allocation - - int offset; // Offset to address of global or external, only - // valid for MO_GlobalAddress, MO_ExternalSym - // and MO_ConstantPoolIndex + int regNum; // register number for an explicit register + int offset; // Offset to address of global or external, only + // valid for MO_GlobalAddress, MO_ExternalSym + // and MO_ConstantPoolIndex } extra; - void zeroContents () { - memset (&contents, 0, sizeof (contents)); - memset (&extra, 0, sizeof (extra)); + void zeroContents() { + contents.immedVal = 0; + extra.offset = 0; } MachineOperand(int64_t ImmVal, MachineOperandType OpTy, int Offset = 0) : flags(0), opType(OpTy) { - zeroContents (); contents.immedVal = ImmVal; extra.offset = Offset; } MachineOperand(int Reg, MachineOperandType OpTy, UseType UseTy) : flags(UseTy), opType(OpTy) { - zeroContents (); + zeroContents(); extra.regNum = Reg; } MachineOperand(GlobalValue *V, int Offset = 0) : flags(MachineOperand::Use), opType(MachineOperand::MO_GlobalAddress) { - zeroContents (); - contents.value = (Value*)V; + contents.GV = V; extra.offset = Offset; } @@ -206,7 +195,7 @@ } GlobalValue *getGlobal() const { assert(isGlobalAddress() && "Wrong MachineOperand accessor"); - return (GlobalValue*)contents.value; + return contents.GV; } int getOffset() const { assert((isGlobalAddress() || isExternalSymbol() || isConstantPoolIndex()) && @@ -476,10 +465,6 @@ // Access to set the operands when building the machine instruction // - void SetMachineOperandVal(unsigned i, - MachineOperand::MachineOperandType operandType, - Value* V); - void SetMachineOperandConst(unsigned i, MachineOperand::MachineOperandType operandType, int intValue); Index: llvm/include/llvm/CodeGen/MachineInstrBuilder.h diff -u llvm/include/llvm/CodeGen/MachineInstrBuilder.h:1.32 llvm/include/llvm/CodeGen/MachineInstrBuilder.h:1.33 --- llvm/include/llvm/CodeGen/MachineInstrBuilder.h:1.32 Wed May 3 20:15:02 2006 +++ llvm/include/llvm/CodeGen/MachineInstrBuilder.h Thu May 4 12:02:51 2006 @@ -8,13 +8,7 @@ //===----------------------------------------------------------------------===// // // This file exposes a function named BuildMI, which is useful for dramatically -// simplifying how MachineInstr's are created. Instead of using code like this: -// -// M = new MachineInstr(X86::ADDrr8); -// M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, argVal1); -// M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, argVal2); -// -// we can now use code like this: +// simplifying how MachineInstr's are created. It allows use of code like this: // // M = BuildMI(X86::ADDrr8, 2).addReg(argVal1).addReg(argVal2); // From lattner at cs.uiuc.edu Thu May 4 12:03:04 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 4 May 2006 12:03:04 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/MachineInstr.cpp Message-ID: <200605041703.MAA13695@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: MachineInstr.cpp updated: 1.115 -> 1.116 --- Log message: Change "value" in MachineOperand to be a GlobalValue, as that is the only thing that can be in it. Remove a dead method. --- Diffs of the changes: (+3 -14) MachineInstr.cpp | 17 +++-------------- 1 files changed, 3 insertions(+), 14 deletions(-) Index: llvm/lib/CodeGen/MachineInstr.cpp diff -u llvm/lib/CodeGen/MachineInstr.cpp:1.115 llvm/lib/CodeGen/MachineInstr.cpp:1.116 --- llvm/lib/CodeGen/MachineInstr.cpp:1.115 Wed May 3 20:26:39 2006 +++ llvm/lib/CodeGen/MachineInstr.cpp Thu May 4 12:02:51 2006 @@ -107,33 +107,22 @@ return false; } -void MachineInstr::SetMachineOperandVal(unsigned i, - MachineOperand::MachineOperandType opTy, - Value* V) { - assert(i < operands.size()); // may be explicit or implicit op - operands[i].opType = opTy; - operands[i].contents.value = V; - operands[i].extra.regNum = -1; -} - void MachineInstr::SetMachineOperandConst(unsigned i, MachineOperand::MachineOperandType opTy, int intValue) { - assert(i < getNumOperands()); // must be explicit op - + assert(i < getNumOperands()); operands[i].opType = opTy; - operands[i].contents.value = NULL; operands[i].contents.immedVal = intValue; operands[i].extra.regNum = -1; operands[i].flags = 0; } void MachineInstr::SetMachineOperandReg(unsigned i, int regNum) { - assert(i < getNumOperands()); // must be explicit op + assert(i < getNumOperands()); operands[i].opType = MachineOperand::MO_VirtualRegister; - operands[i].contents.value = NULL; + operands[i].contents.GV = NULL; operands[i].extra.regNum = regNum; } From lattner at cs.uiuc.edu Thu May 4 12:21:36 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 4 May 2006 12:21:36 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp PPCBranchSelector.cpp PPCInstrBuilder.h PPCRegisterInfo.cpp Message-ID: <200605041721.MAA15648@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCAsmPrinter.cpp updated: 1.169 -> 1.170 PPCBranchSelector.cpp updated: 1.22 -> 1.23 PPCInstrBuilder.h updated: 1.4 -> 1.5 PPCRegisterInfo.cpp updated: 1.63 -> 1.64 --- Log message: There shalt be only one "immediate" operand type! --- Diffs of the changes: (+17 -19) PPCAsmPrinter.cpp | 3 +-- PPCBranchSelector.cpp | 2 +- PPCInstrBuilder.h | 6 +++--- PPCRegisterInfo.cpp | 25 ++++++++++++------------- 4 files changed, 17 insertions(+), 19 deletions(-) Index: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp diff -u llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.169 llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.170 --- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.169 Wed May 3 20:15:02 2006 +++ llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp Thu May 4 12:21:19 2006 @@ -356,8 +356,7 @@ O << RI.get(MO.getReg()).Name; return; - case MachineOperand::MO_SignExtendedImmed: - case MachineOperand::MO_UnextendedImmed: + case MachineOperand::MO_Immediate: std::cerr << "printOp() does not handle immediate values\n"; abort(); return; Index: llvm/lib/Target/PowerPC/PPCBranchSelector.cpp diff -u llvm/lib/Target/PowerPC/PPCBranchSelector.cpp:1.22 llvm/lib/Target/PowerPC/PPCBranchSelector.cpp:1.23 --- llvm/lib/Target/PowerPC/PPCBranchSelector.cpp:1.22 Thu Mar 16 19:40:33 2006 +++ llvm/lib/Target/PowerPC/PPCBranchSelector.cpp Thu May 4 12:21:19 2006 @@ -131,7 +131,7 @@ if (Displacement >= -32768 && Displacement <= 32767) { BuildMI(*MBB, MBBJ, Opcode, 2).addReg(CRReg).addMBB(trueMBB); } else { - BuildMI(*MBB, MBBJ, Inverted, 2).addReg(CRReg).addSImm(8); + BuildMI(*MBB, MBBJ, Inverted, 2).addReg(CRReg).addImm(8); BuildMI(*MBB, MBBJ, PPC::B, 1).addMBB(trueMBB); } Index: llvm/lib/Target/PowerPC/PPCInstrBuilder.h diff -u llvm/lib/Target/PowerPC/PPCInstrBuilder.h:1.4 llvm/lib/Target/PowerPC/PPCInstrBuilder.h:1.5 --- llvm/lib/Target/PowerPC/PPCInstrBuilder.h:1.4 Sun Oct 16 00:39:50 2005 +++ llvm/lib/Target/PowerPC/PPCInstrBuilder.h Thu May 4 12:21:19 2006 @@ -33,9 +33,9 @@ addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0, bool mem = true) { if (mem) - return MIB.addSImm(Offset).addFrameIndex(FI); + return MIB.addImm(Offset).addFrameIndex(FI); else - return MIB.addFrameIndex(FI).addSImm(Offset); + return MIB.addFrameIndex(FI).addImm(Offset); } /// addConstantPoolReference - This function is used to add a reference to the @@ -47,7 +47,7 @@ inline const MachineInstrBuilder& addConstantPoolReference(const MachineInstrBuilder &MIB, unsigned CPI, int Offset = 0) { - return MIB.addSImm(Offset).addConstantPoolIndex(CPI); + return MIB.addImm(Offset).addConstantPoolIndex(CPI); } } // End llvm namespace Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.63 llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.64 --- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.63 Thu May 4 11:56:45 2006 +++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Thu May 4 12:21:19 2006 @@ -269,10 +269,10 @@ // Replace the pseudo instruction with a new instruction... if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) { - BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addSImm(-Amount); + BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addImm(-Amount); } else { assert(Old->getOpcode() == PPC::ADJCALLSTACKUP); - BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addSImm(Amount); + BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addImm(Amount); } } } @@ -311,7 +311,7 @@ if (Offset > 32767 || Offset < -32768) { // Insert a set of r0 with the full offset value before the ld, st, or add MachineBasicBlock *MBB = MI.getParent(); - BuildMI(*MBB, II, PPC::LIS, 1, PPC::R0).addSImm(Offset >> 16); + BuildMI(*MBB, II, PPC::LIS, 1, PPC::R0).addImm(Offset >> 16); BuildMI(*MBB, II, PPC::ORI, 2, PPC::R0).addReg(PPC::R0).addImm(Offset); // convert into indexed form of the instruction @@ -333,8 +333,7 @@ Offset >>= 2; // The actual encoded value has the low two bits zero. break; } - MI.SetMachineOperandConst(OffIdx, MachineOperand::MO_SignExtendedImmed, - Offset); + MI.SetMachineOperandConst(OffIdx, MachineOperand::MO_Immediate, Offset); } } @@ -511,14 +510,14 @@ BuildMI(MBB, MBBI, PPC::RLWINM, 4, PPC::R0) .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31); BuildMI(MBB, MBBI, PPC::SUBFIC,2,PPC::R0).addReg(PPC::R0) - .addSImm(MaxAlign-NumBytes); + .addImm(MaxAlign-NumBytes); BuildMI(MBB, MBBI, PPC::STWUX, 3) .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0); } else if (NumBytes <= 32768) { - BuildMI(MBB, MBBI, PPC::STWU, 3).addReg(PPC::R1).addSImm(NegNumbytes) + BuildMI(MBB, MBBI, PPC::STWU, 3).addReg(PPC::R1).addImm(NegNumbytes) .addReg(PPC::R1); } else { - BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addSImm(NegNumbytes >> 16); + BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addImm(NegNumbytes >> 16); BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0).addReg(PPC::R0) .addImm(NegNumbytes & 0xFFFF); BuildMI(MBB, MBBI, PPC::STWUX, 3).addReg(PPC::R1).addReg(PPC::R1) @@ -534,13 +533,13 @@ MachineLocation Src(MachineLocation::VirtualFP, NegNumbytes); Moves.push_back(new MachineMove(LabelID, Dst, Src)); - BuildMI(MBB, MBBI, PPC::DWARF_LABEL, 1).addSImm(LabelID); + BuildMI(MBB, MBBI, PPC::DWARF_LABEL, 1).addImm(LabelID); } // If there is a frame pointer, copy R1 (SP) into R31 (FP) if (HasFP) { BuildMI(MBB, MBBI, PPC::STW, 3) - .addReg(PPC::R31).addSImm(GPRSize).addReg(PPC::R1); + .addReg(PPC::R31).addImm(GPRSize).addReg(PPC::R1); BuildMI(MBB, MBBI, PPC::OR4, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1); } } @@ -564,16 +563,16 @@ // its stack slot. if (hasFP(MF)) { BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R31) - .addSImm(GPRSize).addReg(PPC::R31); + .addImm(GPRSize).addReg(PPC::R31); } // The loaded (or persistent) stack pointer value is offseted by the 'stwu' // on entry to the function. Add this offset back now. if (NumBytes < 32768 && TargetAlign >= MFI->getMaxAlignment()) { BuildMI(MBB, MBBI, PPC::ADDI, 2, PPC::R1) - .addReg(PPC::R1).addSImm(NumBytes); + .addReg(PPC::R1).addImm(NumBytes); } else { - BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R1).addSImm(0).addReg(PPC::R1); + BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R1).addImm(0).addReg(PPC::R1); } } } From lattner at cs.uiuc.edu Thu May 4 12:21:37 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 4 May 2006 12:21:37 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/IA64/IA64AsmPrinter.cpp IA64InstrBuilder.h IA64RegisterInfo.cpp Message-ID: <200605041721.MAA15662@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/IA64: IA64AsmPrinter.cpp updated: 1.30 -> 1.31 IA64InstrBuilder.h updated: 1.2 -> 1.3 IA64RegisterInfo.cpp updated: 1.17 -> 1.18 --- Log message: There shalt be only one "immediate" operand type! --- Diffs of the changes: (+11 -12) IA64AsmPrinter.cpp | 7 +++---- IA64InstrBuilder.h | 6 +++--- IA64RegisterInfo.cpp | 10 +++++----- 3 files changed, 11 insertions(+), 12 deletions(-) Index: llvm/lib/Target/IA64/IA64AsmPrinter.cpp diff -u llvm/lib/Target/IA64/IA64AsmPrinter.cpp:1.30 llvm/lib/Target/IA64/IA64AsmPrinter.cpp:1.31 --- llvm/lib/Target/IA64/IA64AsmPrinter.cpp:1.30 Wed May 3 20:15:02 2006 +++ llvm/lib/Target/IA64/IA64AsmPrinter.cpp Thu May 4 12:21:19 2006 @@ -170,16 +170,15 @@ } void IA64AsmPrinter::printOp(const MachineOperand &MO, - bool isBRCALLinsn /* = false */) { + bool isBRCALLinsn /* = false */) { const MRegisterInfo &RI = *TM.getRegisterInfo(); switch (MO.getType()) { case MachineOperand::MO_VirtualRegister: O << RI.get(MO.getReg()).Name; return; - case MachineOperand::MO_SignExtendedImmed: - case MachineOperand::MO_UnextendedImmed: - O << /*(unsigned int)*/MO.getImmedValue(); + case MachineOperand::MO_Immediate: + O << MO.getImmedValue(); return; case MachineOperand::MO_MachineBasicBlock: printBasicBlockLabel(MO.getMachineBasicBlock()); Index: llvm/lib/Target/IA64/IA64InstrBuilder.h diff -u llvm/lib/Target/IA64/IA64InstrBuilder.h:1.2 llvm/lib/Target/IA64/IA64InstrBuilder.h:1.3 --- llvm/lib/Target/IA64/IA64InstrBuilder.h:1.2 Thu Apr 21 18:13:11 2005 +++ llvm/lib/Target/IA64/IA64InstrBuilder.h Thu May 4 12:21:19 2006 @@ -29,9 +29,9 @@ addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0, bool mem = true) { if (mem) - return MIB.addSImm(Offset).addFrameIndex(FI); + return MIB.addImm(Offset).addFrameIndex(FI); else - return MIB.addFrameIndex(FI).addSImm(Offset); + return MIB.addFrameIndex(FI).addImm(Offset); } /// addConstantPoolReference - This function is used to add a reference to the @@ -43,7 +43,7 @@ inline const MachineInstrBuilder& addConstantPoolReference(const MachineInstrBuilder &MIB, unsigned CPI, int Offset = 0) { - return MIB.addSImm(Offset).addConstantPoolIndex(CPI); + return MIB.addImm(Offset).addConstantPoolIndex(CPI); } } // End llvm namespace Index: llvm/lib/Target/IA64/IA64RegisterInfo.cpp diff -u llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.17 llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.18 --- llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.17 Fri Apr 7 11:34:45 2006 +++ llvm/lib/Target/IA64/IA64RegisterInfo.cpp Thu May 4 12:21:19 2006 @@ -122,11 +122,11 @@ MachineInstr *New; if (Old->getOpcode() == IA64::ADJUSTCALLSTACKDOWN) { New=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12) - .addSImm(-Amount); + .addImm(-Amount); } else { assert(Old->getOpcode() == IA64::ADJUSTCALLSTACKUP); New=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12) - .addSImm(Amount); + .addImm(Amount); } // Replace the pseudo instruction with a new instruction... @@ -173,7 +173,7 @@ // (the bundler wants to know this) //insert the new MachineInstr* nMI=BuildMI(IA64::ADDIMM22, 2, IA64::r22) - .addReg(BaseRegister).addSImm(Offset); + .addReg(BaseRegister).addImm(Offset); MBB.insert(II, nMI); } else { // it's big //fix up the old: @@ -181,7 +181,7 @@ MI.getOperand(i).setUse(); // mark r22 as being used // (the bundler wants to know this) MachineInstr* nMI; - nMI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addSImm(Offset); + nMI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addImm(Offset); MBB.insert(II, nMI); nMI=BuildMI(IA64::ADD, 2, IA64::r22).addReg(BaseRegister) .addReg(IA64::r22); @@ -272,7 +272,7 @@ MI=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12).addImm(-NumBytes); MBB.insert(MBBI, MI); } else { // we use r22 as a scratch register here - MI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addSImm(-NumBytes); + MI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addImm(-NumBytes); // FIXME: MOVLSI32 expects a _u_32imm MBB.insert(MBBI, MI); // first load the decrement into r22 MI=BuildMI(IA64::ADD, 2, IA64::r12).addReg(IA64::r12).addReg(IA64::r22); From lattner at cs.uiuc.edu Thu May 4 12:21:37 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 4 May 2006 12:21:37 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/MachineInstr.cpp Message-ID: <200605041721.MAA15664@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: MachineInstr.cpp updated: 1.116 -> 1.117 --- Log message: There shalt be only one "immediate" operand type! --- Diffs of the changes: (+2 -8) MachineInstr.cpp | 10 ++-------- 1 files changed, 2 insertions(+), 8 deletions(-) Index: llvm/lib/CodeGen/MachineInstr.cpp diff -u llvm/lib/CodeGen/MachineInstr.cpp:1.116 llvm/lib/CodeGen/MachineInstr.cpp:1.117 --- llvm/lib/CodeGen/MachineInstr.cpp:1.116 Thu May 4 12:02:51 2006 +++ llvm/lib/CodeGen/MachineInstr.cpp Thu May 4 12:21:19 2006 @@ -160,10 +160,7 @@ case MachineOperand::MO_VirtualRegister: OutputReg(OS, MO.getReg(), MRI); break; - case MachineOperand::MO_SignExtendedImmed: - OS << (long)MO.getImmedValue(); - break; - case MachineOperand::MO_UnextendedImmed: + case MachineOperand::MO_Immediate: OS << (long)MO.getImmedValue(); break; case MachineOperand::MO_MachineBasicBlock: @@ -260,10 +257,7 @@ case MachineOperand::MO_VirtualRegister: OutputReg(OS, MO.getReg()); break; - case MachineOperand::MO_SignExtendedImmed: - OS << (long)MO.getImmedValue(); - break; - case MachineOperand::MO_UnextendedImmed: + case MachineOperand::MO_Immediate: OS << (long)MO.getImmedValue(); break; case MachineOperand::MO_MachineBasicBlock: From lattner at cs.uiuc.edu Thu May 4 12:21:37 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 4 May 2006 12:21:37 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcAsmPrinter.cpp SparcRegisterInfo.cpp Message-ID: <200605041721.MAA15672@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Sparc: SparcAsmPrinter.cpp updated: 1.62 -> 1.63 SparcRegisterInfo.cpp updated: 1.41 -> 1.42 --- Log message: There shalt be only one "immediate" operand type! --- Diffs of the changes: (+5 -7) SparcAsmPrinter.cpp | 6 ++---- SparcRegisterInfo.cpp | 6 +++--- 2 files changed, 5 insertions(+), 7 deletions(-) Index: llvm/lib/Target/Sparc/SparcAsmPrinter.cpp diff -u llvm/lib/Target/Sparc/SparcAsmPrinter.cpp:1.62 llvm/lib/Target/Sparc/SparcAsmPrinter.cpp:1.63 --- llvm/lib/Target/Sparc/SparcAsmPrinter.cpp:1.62 Wed May 3 20:15:02 2006 +++ llvm/lib/Target/Sparc/SparcAsmPrinter.cpp Thu May 4 12:21:19 2006 @@ -153,8 +153,7 @@ O << "%reg" << MO.getReg(); break; - case MachineOperand::MO_SignExtendedImmed: - case MachineOperand::MO_UnextendedImmed: + case MachineOperand::MO_Immediate: O << (int)MO.getImmedValue(); break; case MachineOperand::MO_MachineBasicBlock: @@ -192,8 +191,7 @@ if (OpTy == MachineOperand::MO_VirtualRegister && MI->getOperand(opNum+1).getReg() == SP::G0) return; // don't print "+%g0" - if ((OpTy == MachineOperand::MO_SignExtendedImmed || - OpTy == MachineOperand::MO_UnextendedImmed) && + if (OpTy == MachineOperand::MO_Immediate && MI->getOperand(opNum+1).getImmedValue() == 0) return; // don't print "+0" Index: llvm/lib/Target/Sparc/SparcRegisterInfo.cpp diff -u llvm/lib/Target/Sparc/SparcRegisterInfo.cpp:1.41 llvm/lib/Target/Sparc/SparcRegisterInfo.cpp:1.42 --- llvm/lib/Target/Sparc/SparcRegisterInfo.cpp:1.41 Fri Apr 7 11:34:45 2006 +++ llvm/lib/Target/Sparc/SparcRegisterInfo.cpp Thu May 4 12:21:19 2006 @@ -111,7 +111,7 @@ if (MI.getOpcode() == SP::ADJCALLSTACKDOWN) Size = -Size; if (Size) - BuildMI(MBB, I, SP::ADDri, 2, SP::O6).addReg(SP::O6).addSImm(Size); + BuildMI(MBB, I, SP::ADDri, 2, SP::O6).addReg(SP::O6).addImm(Size); MBB.erase(I); } @@ -136,7 +136,7 @@ // If the offset is small enough to fit in the immediate field, directly // encode it. MI.SetMachineOperandReg(i, SP::I6); - MI.SetMachineOperandConst(i+1, MachineOperand::MO_SignExtendedImmed,Offset); + MI.SetMachineOperandConst(i+1, MachineOperand::MO_Immediate, Offset); } else { // Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to // scavenge a register here instead of reserving G1 all of the time. @@ -147,7 +147,7 @@ SP::G1).addReg(SP::G1).addReg(SP::I6); // Insert: G1+%lo(offset) into the user. MI.SetMachineOperandReg(i, SP::G1); - MI.SetMachineOperandConst(i+1, MachineOperand::MO_SignExtendedImmed, + MI.SetMachineOperandConst(i+1, MachineOperand::MO_Immediate, Offset & ((1 << 10)-1)); } } From lattner at cs.uiuc.edu Thu May 4 12:21:37 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 4 May 2006 12:21:37 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineInstr.h MachineInstrBuilder.h Message-ID: <200605041721.MAA15654@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineInstr.h updated: 1.173 -> 1.174 MachineInstrBuilder.h updated: 1.33 -> 1.34 --- Log message: There shalt be only one "immediate" operand type! --- Diffs of the changes: (+4 -25) MachineInstr.h | 22 ++++------------------ MachineInstrBuilder.h | 7 ------- 2 files changed, 4 insertions(+), 25 deletions(-) Index: llvm/include/llvm/CodeGen/MachineInstr.h diff -u llvm/include/llvm/CodeGen/MachineInstr.h:1.173 llvm/include/llvm/CodeGen/MachineInstr.h:1.174 --- llvm/include/llvm/CodeGen/MachineInstr.h:1.173 Thu May 4 12:02:50 2006 +++ llvm/include/llvm/CodeGen/MachineInstr.h Thu May 4 12:21:19 2006 @@ -62,8 +62,7 @@ enum MachineOperandType { MO_VirtualRegister, // virtual register for *value - MO_SignExtendedImmed, - MO_UnextendedImmed, + MO_Immediate, // Immediate Operand MO_MachineBasicBlock, // MachineBasicBlock reference MO_FrameIndex, // Abstract Stack Frame Index MO_ConstantPoolIndex, // Address of indexed Constant in Constant Pool @@ -160,9 +159,7 @@ /// Accessors that tell you what kind of MachineOperand you're looking at. /// bool isMachineBasicBlock() const { return opType == MO_MachineBasicBlock; } - bool isImmediate() const { - return opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed; - } + bool isImmediate() const { return opType == MO_Immediate; } bool isFrameIndex() const { return opType == MO_FrameIndex; } bool isConstantPoolIndex() const { return opType == MO_ConstantPoolIndex; } bool isJumpTableIndex() const { return opType == MO_JumpTableIndex; } @@ -380,7 +377,7 @@ assert(!OperandsComplete() && "Trying to add an operand to a machine instr that is already done!"); operands.push_back( - MachineOperand(intValue, MachineOperand::MO_UnextendedImmed)); + MachineOperand(intValue, MachineOperand::MO_Immediate)); } /// addZeroExtImm64Operand - Add a zero extended 64-bit constant argument @@ -389,18 +386,7 @@ void addZeroExtImm64Operand(uint64_t intValue) { assert(!OperandsComplete() && "Trying to add an operand to a machine instr that is already done!"); - operands.push_back( - MachineOperand(intValue, MachineOperand::MO_UnextendedImmed)); - } - - /// addSignExtImmOperand - Add a zero extended constant argument to the - /// machine instruction. - /// - void addSignExtImmOperand(int intValue) { - assert(!OperandsComplete() && - "Trying to add an operand to a machine instr that is already done!"); - operands.push_back( - MachineOperand(intValue, MachineOperand::MO_SignExtendedImmed)); + operands.push_back(MachineOperand(intValue, MachineOperand::MO_Immediate)); } void addMachineBasicBlockOperand(MachineBasicBlock *MBB) { Index: llvm/include/llvm/CodeGen/MachineInstrBuilder.h diff -u llvm/include/llvm/CodeGen/MachineInstrBuilder.h:1.33 llvm/include/llvm/CodeGen/MachineInstrBuilder.h:1.34 --- llvm/include/llvm/CodeGen/MachineInstrBuilder.h:1.33 Thu May 4 12:02:51 2006 +++ llvm/include/llvm/CodeGen/MachineInstrBuilder.h Thu May 4 12:21:19 2006 @@ -47,13 +47,6 @@ return *this; } - /// addSImm - Add a new sign extended immediate operand... - /// - const MachineInstrBuilder &addSImm(int val) const { - MI->addSignExtImmOperand(val); - return *this; - } - /// addZImm - Add a new zero extended immediate operand... /// const MachineInstrBuilder &addZImm(unsigned Val) const { From lattner at cs.uiuc.edu Thu May 4 12:21:37 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 4 May 2006 12:21:37 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp X86InstrBuilder.h X86IntelAsmPrinter.cpp X86RegisterInfo.cpp Message-ID: <200605041721.MAA15682@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ATTAsmPrinter.cpp updated: 1.40 -> 1.41 X86InstrBuilder.h updated: 1.18 -> 1.19 X86IntelAsmPrinter.cpp updated: 1.39 -> 1.40 X86RegisterInfo.cpp updated: 1.146 -> 1.147 --- Log message: There shalt be only one "immediate" operand type! --- Diffs of the changes: (+9 -11) X86ATTAsmPrinter.cpp | 3 +-- X86InstrBuilder.h | 12 ++++++------ X86IntelAsmPrinter.cpp | 3 +-- X86RegisterInfo.cpp | 2 +- 4 files changed, 9 insertions(+), 11 deletions(-) Index: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp diff -u llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.40 llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.41 --- llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.40 Wed May 3 20:15:02 2006 +++ llvm/lib/Target/X86/X86ATTAsmPrinter.cpp Thu May 4 12:21:20 2006 @@ -116,8 +116,7 @@ O << (char)tolower(*Name); return; - case MachineOperand::MO_SignExtendedImmed: - case MachineOperand::MO_UnextendedImmed: + case MachineOperand::MO_Immediate: if (!Modifier || strcmp(Modifier, "debug") != 0) O << '$'; O << (int)MO.getImmedValue(); Index: llvm/lib/Target/X86/X86InstrBuilder.h diff -u llvm/lib/Target/X86/X86InstrBuilder.h:1.18 llvm/lib/Target/X86/X86InstrBuilder.h:1.19 --- llvm/lib/Target/X86/X86InstrBuilder.h:1.18 Wed May 3 20:15:02 2006 +++ llvm/lib/Target/X86/X86InstrBuilder.h Thu May 4 12:21:20 2006 @@ -61,7 +61,7 @@ unsigned Reg) { // Because memory references are always represented with four // values, this adds: Reg, [1, NoReg, 0] to the instruction. - return MIB.addReg(Reg).addZImm(1).addReg(0).addSImm(0); + return MIB.addReg(Reg).addZImm(1).addReg(0).addImm(0); } @@ -71,14 +71,14 @@ /// inline const MachineInstrBuilder &addRegOffset(const MachineInstrBuilder &MIB, unsigned Reg, int Offset) { - return MIB.addReg(Reg).addZImm(1).addReg(0).addSImm(Offset); + return MIB.addReg(Reg).addZImm(1).addReg(0).addImm(Offset); } /// addRegReg - This function is used to add a memory reference of the form: /// [Reg + Reg]. inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB, unsigned Reg1, unsigned Reg2) { - return MIB.addReg(Reg1).addZImm(1).addReg(Reg2).addSImm(0); + return MIB.addReg(Reg1).addZImm(1).addReg(Reg2).addImm(0); } inline const MachineInstrBuilder &addFullAddress(const MachineInstrBuilder &MIB, @@ -95,7 +95,7 @@ if (AM.GV) return MIB.addGlobalAddress(AM.GV, AM.Disp); else - return MIB.addSImm(AM.Disp); + return MIB.addImm(AM.Disp); } /// addFrameReference - This function is used to add a reference to the base of @@ -105,7 +105,7 @@ /// inline const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0) { - return MIB.addFrameIndex(FI).addZImm(1).addReg(0).addSImm(Offset); + return MIB.addFrameIndex(FI).addZImm(1).addReg(0).addImm(Offset); } /// addConstantPoolReference - This function is used to add a reference to the @@ -117,7 +117,7 @@ inline const MachineInstrBuilder & addConstantPoolReference(const MachineInstrBuilder &MIB, unsigned CPI, int Offset = 0) { - return MIB.addConstantPoolIndex(CPI).addZImm(1).addReg(0).addSImm(Offset); + return MIB.addConstantPoolIndex(CPI).addZImm(1).addReg(0).addImm(Offset); } } // End llvm namespace Index: llvm/lib/Target/X86/X86IntelAsmPrinter.cpp diff -u llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.39 llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.40 --- llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.39 Thu May 4 11:20:22 2006 +++ llvm/lib/Target/X86/X86IntelAsmPrinter.cpp Thu May 4 12:21:20 2006 @@ -107,8 +107,7 @@ O << "reg" << MO.getReg(); return; - case MachineOperand::MO_SignExtendedImmed: - case MachineOperand::MO_UnextendedImmed: + case MachineOperand::MO_Immediate: O << (int)MO.getImmedValue(); return; case MachineOperand::MO_MachineBasicBlock: Index: llvm/lib/Target/X86/X86RegisterInfo.cpp diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.146 llvm/lib/Target/X86/X86RegisterInfo.cpp:1.147 --- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.146 Wed May 3 20:15:02 2006 +++ llvm/lib/Target/X86/X86RegisterInfo.cpp Thu May 4 12:21:20 2006 @@ -676,7 +676,7 @@ else Offset += 4; // Skip the saved EBP - MI.SetMachineOperandConst(i+3, MachineOperand::MO_SignExtendedImmed, Offset); + MI.SetMachineOperandConst(i+3, MachineOperand::MO_Immediate, Offset); } void From lattner at cs.uiuc.edu Thu May 4 12:21:38 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 4 May 2006 12:21:38 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp AlphaRegisterInfo.cpp Message-ID: <200605041721.MAA15688@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Alpha: AlphaAsmPrinter.cpp updated: 1.39 -> 1.40 AlphaRegisterInfo.cpp updated: 1.41 -> 1.42 --- Log message: There shalt be only one "immediate" operand type! --- Diffs of the changes: (+3 -4) AlphaAsmPrinter.cpp | 3 +-- AlphaRegisterInfo.cpp | 4 ++-- 2 files changed, 3 insertions(+), 4 deletions(-) Index: llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp diff -u llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.39 llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.40 --- llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.39 Wed May 3 20:15:02 2006 +++ llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp Thu May 4 12:21:19 2006 @@ -97,8 +97,7 @@ O << RI.get(MO.getReg()).Name; return; - case MachineOperand::MO_SignExtendedImmed: - case MachineOperand::MO_UnextendedImmed: + case MachineOperand::MO_Immediate: std::cerr << "printOp() does not handle immediate values\n"; abort(); return; Index: llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp diff -u llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.41 llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.42 --- llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.41 Wed May 3 20:15:02 2006 +++ llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp Thu May 4 12:21:19 2006 @@ -234,14 +234,14 @@ //inst off the SP/FP //fix up the old: MI.SetMachineOperandReg(i + 1, Alpha::R28); - MI.SetMachineOperandConst(i, MachineOperand::MO_SignExtendedImmed, + MI.SetMachineOperandConst(i, MachineOperand::MO_Immediate, getLower16(Offset)); //insert the new MachineInstr* nMI=BuildMI(Alpha::LDAH, 2, Alpha::R28) .addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30); MBB.insert(II, nMI); } else { - MI.SetMachineOperandConst(i, MachineOperand::MO_SignExtendedImmed, Offset); + MI.SetMachineOperandConst(i, MachineOperand::MO_Immediate, Offset); } } From lattner at cs.uiuc.edu Thu May 4 12:33:37 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 4 May 2006 12:33:37 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/InstCombine/2006-05-04-DemandedBitCrash.ll Message-ID: <200605041733.MAA17751@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/InstCombine: 2006-05-04-DemandedBitCrash.ll added (r1.1) --- Log message: new testcase that crashes the instcombine pass --- Diffs of the changes: (+50 -0) 2006-05-04-DemandedBitCrash.ll | 50 +++++++++++++++++++++++++++++++++++++++++ 1 files changed, 50 insertions(+) Index: llvm/test/Regression/Transforms/InstCombine/2006-05-04-DemandedBitCrash.ll diff -c /dev/null llvm/test/Regression/Transforms/InstCombine/2006-05-04-DemandedBitCrash.ll:1.1 *** /dev/null Thu May 4 12:33:34 2006 --- llvm/test/Regression/Transforms/InstCombine/2006-05-04-DemandedBitCrash.ll Thu May 4 12:33:24 2006 *************** *** 0 **** --- 1,50 ---- + ; RUN: llvm-as < %s | opt -instcombine -disable-output + + void %test() { + bb38.i: + %varspec.0.i1014 = cast long 123814269237067777 to ulong ; [#uses=1] + %locspec.0.i1015 = cast int 1 to uint ; [#uses=2] + %tmp51391.i1018 = shr ulong %varspec.0.i1014, ubyte 16 ; [#uses=1] + %tmp51392.i1019 = cast ulong %tmp51391.i1018 to uint ; [#uses=2] + %tmp51392.mask.i1020 = shr uint %tmp51392.i1019, ubyte 29 ; [#uses=1] + %tmp7.i1021 = and uint %tmp51392.mask.i1020, 1 ; [#uses=2] + %tmp18.i1026 = shr uint %tmp51392.i1019, ubyte 31 ; [#uses=2] + %tmp18.i1027 = cast uint %tmp18.i1026 to ubyte ; [#uses=1] + br bool false, label %cond_false1148.i1653, label %bb377.i1259 + + bb377.i1259: ; preds = %bb38.i + br bool false, label %cond_true541.i1317, label %cond_false1148.i1653 + + cond_true541.i1317: ; preds = %bb377.i1259 + %tmp545.i1318 = shr uint %locspec.0.i1015, ubyte 10 ; [#uses=1] + %tmp550.i1319 = shr uint %locspec.0.i1015, ubyte 4 ; [#uses=1] + %tmp550551.i1320 = and uint %tmp550.i1319, 63 ; [#uses=1] + %tmp553.i1321 = setlt uint %tmp550551.i1320, 4 ; [#uses=1] + %tmp558.i1322 = seteq uint %tmp7.i1021, 0 ; [#uses=1] + %bothcond.i1326 = or bool %tmp553.i1321, false ; [#uses=1] + %bothcond1.i1327 = or bool %bothcond.i1326, false ; [#uses=1] + %bothcond2.not.i1328 = or bool %bothcond1.i1327, false ; [#uses=1] + %bothcond3.i1329 = or bool %bothcond2.not.i1328, %tmp558.i1322 ; [#uses=0] + br bool false, label %cond_true583.i1333, label %cond_next592.i1337 + + cond_true583.i1333: ; preds = %cond_true541.i1317 + br bool false, label %cond_true586.i1335, label %cond_next592.i1337 + + cond_true586.i1335: ; preds = %cond_true583.i1333 + br label %cond_true.i + + cond_next592.i1337: ; preds = %cond_true583.i1333, %cond_true541.i1317 + %mask_z.0.i1339 = phi uint [ %tmp18.i1026, %cond_true541.i1317 ], [ 0, %cond_true583.i1333 ] ; [#uses=0] + %tmp594.i1340 = and uint %tmp545.i1318, 15 ; [#uses=0] + br label %cond_true.i + + cond_false1148.i1653: ; preds = %bb377.i1259, %bb38.i + %tmp1150.i1654 = seteq uint %tmp7.i1021, 0 ; [#uses=1] + %tmp1160.i1656 = seteq ubyte %tmp18.i1027, 0 ; [#uses=1] + %bothcond8.i1658 = or bool %tmp1150.i1654, %tmp1160.i1656 ; [#uses=1] + %bothcond9.i1659 = or bool %bothcond8.i1658, false ; [#uses=0] + br label %cond_true.i + + cond_true.i: ; preds = %cond_false1148.i1653, %cond_next592.i1337, %cond_true586.i1335 + ret void + } From lattner at cs.uiuc.edu Thu May 4 12:33:48 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 4 May 2006 12:33:48 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp Message-ID: <200605041733.MAA17759@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: InstructionCombining.cpp updated: 1.473 -> 1.474 --- Log message: Fix Transforms/InstCombine/2006-05-04-DemandedBitCrash.ll --- Diffs of the changes: (+4 -0) InstructionCombining.cpp | 4 ++++ 1 files changed, 4 insertions(+) Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.473 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.474 --- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.473 Fri Apr 28 17:21:41 2006 +++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Thu May 4 12:33:35 2006 @@ -456,6 +456,8 @@ Instruction *I = dyn_cast(V); if (!I) return; + Mask &= V->getType()->getIntegralTypeMask(); + switch (I->getOpcode()) { case Instruction::And: // If either the LHS or the RHS are Zero, the result is zero. @@ -713,6 +715,8 @@ Instruction *I = dyn_cast(V); if (!I) return false; // Only analyze instructions. + DemandedMask &= V->getType()->getIntegralTypeMask(); + uint64_t KnownZero2, KnownOne2; switch (I->getOpcode()) { default: break; From lattner at cs.uiuc.edu Thu May 4 12:52:39 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 4 May 2006 12:52:39 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp PPCRegisterInfo.cpp Message-ID: <200605041752.MAA18927@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCInstrInfo.cpp updated: 1.19 -> 1.20 PPCRegisterInfo.cpp updated: 1.64 -> 1.65 --- Log message: Move some methods out of MachineInstr into MachineOperand --- Diffs of the changes: (+6 -6) PPCInstrInfo.cpp | 4 ++-- PPCRegisterInfo.cpp | 8 ++++---- 2 files changed, 6 insertions(+), 6 deletions(-) Index: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.19 llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.20 --- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.19 Thu Mar 16 16:24:02 2006 +++ llvm/lib/Target/PowerPC/PPCInstrInfo.cpp Thu May 4 12:52:23 2006 @@ -136,8 +136,8 @@ // Swap op1/op2 unsigned Reg1 = MI->getOperand(1).getReg(); unsigned Reg2 = MI->getOperand(2).getReg(); - MI->SetMachineOperandReg(2, Reg1); - MI->SetMachineOperandReg(1, Reg2); + MI->getOperand(2).setReg(Reg1); + MI->getOperand(1).setReg(Reg2); // Swap the mask around. unsigned MB = MI->getOperand(4).getImmedValue(); Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.64 llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.65 --- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.64 Thu May 4 12:21:19 2006 +++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Thu May 4 12:52:23 2006 @@ -294,7 +294,7 @@ int FrameIndex = MI.getOperand(i).getFrameIndex(); // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). - MI.SetMachineOperandReg(i, hasFP(MF) ? PPC::R31 : PPC::R1); + MI.getOperand(i).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1); // Take into account whether it's an add or mem instruction unsigned OffIdx = (i == 2) ? 1 : 2; @@ -321,8 +321,8 @@ "No indexed form of load or store available!"); unsigned NewOpcode = ImmToIdxMap.find(MI.getOpcode())->second; MI.setOpcode(NewOpcode); - MI.SetMachineOperandReg(1, MI.getOperand(i).getReg()); - MI.SetMachineOperandReg(2, PPC::R0); + MI.getOperand(1).ChangeToRegister(MI.getOperand(i).getReg()); + MI.getOperand(2).ChangeToRegister(PPC::R0); } else { switch (MI.getOpcode()) { case PPC::LWA: @@ -333,7 +333,7 @@ Offset >>= 2; // The actual encoded value has the low two bits zero. break; } - MI.SetMachineOperandConst(OffIdx, MachineOperand::MO_Immediate, Offset); + MI.getOperand(OffIdx).ChangeToImmediate(Offset); } } From lattner at cs.uiuc.edu Thu May 4 12:52:41 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 4 May 2006 12:52:41 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineInstr.h Message-ID: <200605041752.MAA18931@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineInstr.h updated: 1.174 -> 1.175 --- Log message: Move some methods out of MachineInstr into MachineOperand --- Diffs of the changes: (+17 -10) MachineInstr.h | 27 +++++++++++++++++---------- 1 files changed, 17 insertions(+), 10 deletions(-) Index: llvm/include/llvm/CodeGen/MachineInstr.h diff -u llvm/include/llvm/CodeGen/MachineInstr.h:1.174 llvm/include/llvm/CodeGen/MachineInstr.h:1.175 --- llvm/include/llvm/CodeGen/MachineInstr.h:1.174 Thu May 4 12:21:19 2006 +++ llvm/include/llvm/CodeGen/MachineInstr.h Thu May 4 12:52:22 2006 @@ -234,7 +234,7 @@ extra.regNum = Reg; } - void setImmedValue(int immVal) { + void setImmedValue(int64_t immVal) { assert(isImmediate() && "Wrong MachineOperand mutator"); contents.immedVal = immVal; } @@ -245,6 +245,22 @@ "Wrong MachineOperand accessor"); extra.offset = Offset; } + + /// ChangeToImmediate - Replace this operand with a new immediate operand of + /// the specified value. If an operand is known to be an immediate already, + /// the setImmedValue method should be used. + void ChangeToImmediate(int64_t ImmVal) { + opType = MO_Immediate; + contents.immedVal = ImmVal; + } + + /// ChangeToRegister - Replace this operand with a new register operand of + /// the specified value. If an operand is known to be an register already, + /// the setReg method should be used. + void ChangeToRegister(unsigned Reg) { + opType = MO_VirtualRegister; + extra.regNum = Reg; + } friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop); @@ -436,7 +452,6 @@ //===--------------------------------------------------------------------===// // Accessors used to modify instructions in place. // - // FIXME: Move this stuff to MachineOperand itself! /// setOpcode - Replace the opcode of the current instruction with a new one. /// @@ -448,14 +463,6 @@ void RemoveOperand(unsigned i) { operands.erase(operands.begin()+i); } - - // Access to set the operands when building the machine instruction - // - void SetMachineOperandConst(unsigned i, - MachineOperand::MachineOperandType operandType, - int intValue); - - void SetMachineOperandReg(unsigned i, int regNum); }; //===----------------------------------------------------------------------===// From lattner at cs.uiuc.edu Thu May 4 12:52:42 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 4 May 2006 12:52:42 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/FPMover.cpp SparcRegisterInfo.cpp Message-ID: <200605041752.MAA18937@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Sparc: FPMover.cpp updated: 1.12 -> 1.13 SparcRegisterInfo.cpp updated: 1.42 -> 1.43 --- Log message: Move some methods out of MachineInstr into MachineOperand --- Diffs of the changes: (+6 -7) FPMover.cpp | 4 ++-- SparcRegisterInfo.cpp | 9 ++++----- 2 files changed, 6 insertions(+), 7 deletions(-) Index: llvm/lib/Target/Sparc/FPMover.cpp diff -u llvm/lib/Target/Sparc/FPMover.cpp:1.12 llvm/lib/Target/Sparc/FPMover.cpp:1.13 --- llvm/lib/Target/Sparc/FPMover.cpp:1.12 Sat Feb 4 23:50:24 2006 +++ llvm/lib/Target/Sparc/FPMover.cpp Thu May 4 12:52:23 2006 @@ -104,8 +104,8 @@ else assert(0 && "Unknown opcode!"); - MI->SetMachineOperandReg(0, EvenDestReg); - MI->SetMachineOperandReg(1, EvenSrcReg); + MI->getOperand(0).setReg(EvenDestReg); + MI->getOperand(1).setReg(EvenSrcReg); DEBUG(std::cerr << "FPMover: the modified instr is: " << *MI); // Insert copy for the other half of the double. if (DestDReg != SrcDReg) { Index: llvm/lib/Target/Sparc/SparcRegisterInfo.cpp diff -u llvm/lib/Target/Sparc/SparcRegisterInfo.cpp:1.42 llvm/lib/Target/Sparc/SparcRegisterInfo.cpp:1.43 --- llvm/lib/Target/Sparc/SparcRegisterInfo.cpp:1.42 Thu May 4 12:21:19 2006 +++ llvm/lib/Target/Sparc/SparcRegisterInfo.cpp Thu May 4 12:52:23 2006 @@ -135,8 +135,8 @@ if (Offset >= -4096 && Offset <= 4095) { // If the offset is small enough to fit in the immediate field, directly // encode it. - MI.SetMachineOperandReg(i, SP::I6); - MI.SetMachineOperandConst(i+1, MachineOperand::MO_Immediate, Offset); + MI.getOperand(i).ChangeToRegister(SP::I6); + MI.getOperand(i+1).ChangeToImmediate(Offset); } else { // Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to // scavenge a register here instead of reserving G1 all of the time. @@ -146,9 +146,8 @@ BuildMI(*MI.getParent(), II, SP::ADDrr, 2, SP::G1).addReg(SP::G1).addReg(SP::I6); // Insert: G1+%lo(offset) into the user. - MI.SetMachineOperandReg(i, SP::G1); - MI.SetMachineOperandConst(i+1, MachineOperand::MO_Immediate, - Offset & ((1 << 10)-1)); + MI.getOperand(i).ChangeToRegister(SP::G1); + MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1)); } } From lattner at cs.uiuc.edu Thu May 4 12:52:42 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 4 May 2006 12:52:42 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp Message-ID: <200605041752.MAA18959@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86RegisterInfo.cpp updated: 1.147 -> 1.148 --- Log message: Move some methods out of MachineInstr into MachineOperand --- Diffs of the changes: (+2 -2) X86RegisterInfo.cpp | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/Target/X86/X86RegisterInfo.cpp diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.147 llvm/lib/Target/X86/X86RegisterInfo.cpp:1.148 --- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.147 Thu May 4 12:21:20 2006 +++ llvm/lib/Target/X86/X86RegisterInfo.cpp Thu May 4 12:52:23 2006 @@ -665,7 +665,7 @@ // This must be part of a four operand memory reference. Replace the // FrameIndex with base register with EBP. Add add an offset to the offset. - MI.SetMachineOperandReg(i, hasFP(MF) ? X86::EBP : X86::ESP); + MI.getOperand(i).ChangeToRegister(hasFP(MF) ? X86::EBP : X86::ESP); // Now add the frame object offset to the offset from EBP. int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + @@ -676,7 +676,7 @@ else Offset += 4; // Skip the saved EBP - MI.SetMachineOperandConst(i+3, MachineOperand::MO_Immediate, Offset); + MI.getOperand(i+3).ChangeToImmediate(Offset); } void From lattner at cs.uiuc.edu Thu May 4 12:52:42 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 4 May 2006 12:52:42 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp Message-ID: <200605041752.MAA18941@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Alpha: AlphaRegisterInfo.cpp updated: 1.42 -> 1.43 --- Log message: Move some methods out of MachineInstr into MachineOperand --- Diffs of the changes: (+4 -5) AlphaRegisterInfo.cpp | 9 ++++----- 1 files changed, 4 insertions(+), 5 deletions(-) Index: llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp diff -u llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.42 llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.43 --- llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.42 Thu May 4 12:21:19 2006 +++ llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp Thu May 4 12:52:23 2006 @@ -216,7 +216,7 @@ int FrameIndex = MI.getOperand(i).getFrameIndex(); // Add the base register of R30 (SP) or R15 (FP). - MI.SetMachineOperandReg(i + 1, FP ? Alpha::R15 : Alpha::R30); + MI.getOperand(i + 1).ChangeToRegister(FP ? Alpha::R15 : Alpha::R30); // Now add the frame object offset to the offset from the virtual frame index. int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex); @@ -233,15 +233,14 @@ //so in this case, we need to use a temporary register, and move the original //inst off the SP/FP //fix up the old: - MI.SetMachineOperandReg(i + 1, Alpha::R28); - MI.SetMachineOperandConst(i, MachineOperand::MO_Immediate, - getLower16(Offset)); + MI.getOperand(i + 1).ChangeToRegister(Alpha::R28); + MI.getOperand(i).ChangeToImmediate(getLower16(Offset)); //insert the new MachineInstr* nMI=BuildMI(Alpha::LDAH, 2, Alpha::R28) .addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30); MBB.insert(II, nMI); } else { - MI.SetMachineOperandConst(i, MachineOperand::MO_Immediate, Offset); + MI.getOperand(i).ChangeToImmediate(Offset); } } From lattner at cs.uiuc.edu Thu May 4 12:52:42 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 4 May 2006 12:52:42 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/IA64/IA64RegisterInfo.cpp Message-ID: <200605041752.MAA18951@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/IA64: IA64RegisterInfo.cpp updated: 1.18 -> 1.19 --- Log message: Move some methods out of MachineInstr into MachineOperand --- Diffs of the changes: (+3 -3) IA64RegisterInfo.cpp | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) Index: llvm/lib/Target/IA64/IA64RegisterInfo.cpp diff -u llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.18 llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.19 --- llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.18 Thu May 4 12:21:19 2006 +++ llvm/lib/Target/IA64/IA64RegisterInfo.cpp Thu May 4 12:52:23 2006 @@ -155,7 +155,7 @@ // choose a base register: ( hasFP? framepointer : stack pointer ) unsigned BaseRegister = FP ? IA64::r5 : IA64::r12; // Add the base register - MI.SetMachineOperandReg(i, BaseRegister); + MI.getOperand(i).ChangeToRegister(BaseRegister); // Now add the frame object offset to the offset from r1. int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex); @@ -168,7 +168,7 @@ // XXX: we use 'r22' as another hack+slash temporary register here :( if ( Offset <= 8191 && Offset >= -8192) { // smallish offset //fix up the old: - MI.SetMachineOperandReg(i, IA64::r22); + MI.getOperand(i).ChangeToRegister(IA64::r22); MI.getOperand(i).setUse(); // mark r22 as being used // (the bundler wants to know this) //insert the new @@ -177,7 +177,7 @@ MBB.insert(II, nMI); } else { // it's big //fix up the old: - MI.SetMachineOperandReg(i, IA64::r22); + MI.getOperand(i).ChangeToRegister(IA64::r22); MI.getOperand(i).setUse(); // mark r22 as being used // (the bundler wants to know this) MachineInstr* nMI; From lattner at cs.uiuc.edu Thu May 4 12:52:42 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 4 May 2006 12:52:42 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/LiveIntervalAnalysis.cpp MachineInstr.cpp RegAllocLocal.cpp RegAllocSimple.cpp TwoAddressInstructionPass.cpp VirtRegMap.cpp Message-ID: <200605041752.MAA18957@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: LiveIntervalAnalysis.cpp updated: 1.156 -> 1.157 MachineInstr.cpp updated: 1.117 -> 1.118 RegAllocLocal.cpp updated: 1.77 -> 1.78 RegAllocSimple.cpp updated: 1.66 -> 1.67 TwoAddressInstructionPass.cpp updated: 1.32 -> 1.33 VirtRegMap.cpp updated: 1.65 -> 1.66 --- Log message: Move some methods out of MachineInstr into MachineOperand --- Diffs of the changes: (+16 -35) LiveIntervalAnalysis.cpp | 6 +++--- MachineInstr.cpp | 19 ------------------- RegAllocLocal.cpp | 6 +++--- RegAllocSimple.cpp | 2 +- TwoAddressInstructionPass.cpp | 2 +- VirtRegMap.cpp | 16 ++++++++-------- 6 files changed, 16 insertions(+), 35 deletions(-) Index: llvm/lib/CodeGen/LiveIntervalAnalysis.cpp diff -u llvm/lib/CodeGen/LiveIntervalAnalysis.cpp:1.156 llvm/lib/CodeGen/LiveIntervalAnalysis.cpp:1.157 --- llvm/lib/CodeGen/LiveIntervalAnalysis.cpp:1.156 Mon May 1 16:16:03 2006 +++ llvm/lib/CodeGen/LiveIntervalAnalysis.cpp Thu May 4 12:52:23 2006 @@ -187,7 +187,7 @@ MRegisterInfo::isVirtualRegister(mop.getReg())) { // replace register with representative register unsigned reg = rep(mop.getReg()); - mii->SetMachineOperandReg(i, reg); + mii->getOperand(i).setReg(reg); LiveInterval &RegInt = getInterval(reg); RegInt.weight += @@ -263,7 +263,7 @@ if (NewRegLiveIn && mop.isUse()) { // We already emitted a reload of this value, reuse it for // subsequent operands. - MI->SetMachineOperandReg(i, NewRegLiveIn); + MI->getOperand(i).setReg(NewRegLiveIn); DEBUG(std::cerr << "\t\t\t\treused reload into reg" << NewRegLiveIn << " for operand #" << i << '\n'); } else if (MachineInstr* fmi = mri_->foldMemoryOperand(MI, i, slot)) { @@ -300,7 +300,7 @@ // create a new register for this spill NewRegLiveIn = mf_->getSSARegMap()->createVirtualRegister(rc); - MI->SetMachineOperandReg(i, NewRegLiveIn); + MI->getOperand(i).setReg(NewRegLiveIn); vrm.grow(); vrm.assignVirt2StackSlot(NewRegLiveIn, slot); LiveInterval& nI = getOrCreateInterval(NewRegLiveIn); Index: llvm/lib/CodeGen/MachineInstr.cpp diff -u llvm/lib/CodeGen/MachineInstr.cpp:1.117 llvm/lib/CodeGen/MachineInstr.cpp:1.118 --- llvm/lib/CodeGen/MachineInstr.cpp:1.117 Thu May 4 12:21:19 2006 +++ llvm/lib/CodeGen/MachineInstr.cpp Thu May 4 12:52:23 2006 @@ -107,25 +107,6 @@ return false; } -void -MachineInstr::SetMachineOperandConst(unsigned i, - MachineOperand::MachineOperandType opTy, - int intValue) { - assert(i < getNumOperands()); - operands[i].opType = opTy; - operands[i].contents.immedVal = intValue; - operands[i].extra.regNum = -1; - operands[i].flags = 0; -} - -void MachineInstr::SetMachineOperandReg(unsigned i, int regNum) { - assert(i < getNumOperands()); - - operands[i].opType = MachineOperand::MO_VirtualRegister; - operands[i].contents.GV = NULL; - operands[i].extra.regNum = regNum; -} - void MachineInstr::dump() const { std::cerr << " " << *this; } Index: llvm/lib/CodeGen/RegAllocLocal.cpp diff -u llvm/lib/CodeGen/RegAllocLocal.cpp:1.77 llvm/lib/CodeGen/RegAllocLocal.cpp:1.78 --- llvm/lib/CodeGen/RegAllocLocal.cpp:1.77 Sun Jan 22 17:39:54 2006 +++ llvm/lib/CodeGen/RegAllocLocal.cpp Thu May 4 12:52:23 2006 @@ -443,7 +443,7 @@ // and return. if (unsigned PR = getVirt2PhysRegMapSlot(VirtReg)) { MarkPhysRegRecentlyUsed(PR); // Already have this value available! - MI->SetMachineOperandReg(OpNum, PR); // Assign the input register + MI->getOperand(OpNum).setReg(PR); // Assign the input register return MI; } @@ -481,7 +481,7 @@ ++NumLoads; // Update statistics PhysRegsEverUsed[PhysReg] = true; - MI->SetMachineOperandReg(OpNum, PhysReg); // Assign the input register + MI->getOperand(OpNum).setReg(PhysReg); // Assign the input register return MI; } @@ -599,7 +599,7 @@ DestPhysReg = getReg(MBB, MI, DestVirtReg); PhysRegsEverUsed[DestPhysReg] = true; markVirtRegModified(DestVirtReg); - MI->SetMachineOperandReg(i, DestPhysReg); // Assign the output register + MI->getOperand(i).setReg(DestPhysReg); // Assign the output register } } Index: llvm/lib/CodeGen/RegAllocSimple.cpp diff -u llvm/lib/CodeGen/RegAllocSimple.cpp:1.66 llvm/lib/CodeGen/RegAllocSimple.cpp:1.67 --- llvm/lib/CodeGen/RegAllocSimple.cpp:1.66 Sun Jan 22 17:39:54 2006 +++ llvm/lib/CodeGen/RegAllocSimple.cpp Thu May 4 12:52:23 2006 @@ -211,7 +211,7 @@ Virt2PhysRegMap[virtualReg] = physReg; } } - MI->SetMachineOperandReg(i, physReg); + MI->getOperand(i).setReg(physReg); DEBUG(std::cerr << "virt: " << virtualReg << ", phys: " << op.getReg() << "\n"); } Index: llvm/lib/CodeGen/TwoAddressInstructionPass.cpp diff -u llvm/lib/CodeGen/TwoAddressInstructionPass.cpp:1.32 llvm/lib/CodeGen/TwoAddressInstructionPass.cpp:1.33 --- llvm/lib/CodeGen/TwoAddressInstructionPass.cpp:1.32 Sun Jan 22 17:41:00 2006 +++ llvm/lib/CodeGen/TwoAddressInstructionPass.cpp Thu May 4 12:52:23 2006 @@ -200,7 +200,7 @@ for (unsigned i = 1, e = mi->getNumOperands(); i != e; ++i) { if (mi->getOperand(i).isRegister() && mi->getOperand(i).getReg() == regB) - mi->SetMachineOperandReg(i, regA); + mi->getOperand(i).setReg(regA); } } Index: llvm/lib/CodeGen/VirtRegMap.cpp diff -u llvm/lib/CodeGen/VirtRegMap.cpp:1.65 llvm/lib/CodeGen/VirtRegMap.cpp:1.66 --- llvm/lib/CodeGen/VirtRegMap.cpp:1.65 Mon May 1 17:03:24 2006 +++ llvm/lib/CodeGen/VirtRegMap.cpp Thu May 4 12:52:23 2006 @@ -182,7 +182,7 @@ } } PhysRegsUsed[PhysReg] = true; - MI.SetMachineOperandReg(i, PhysReg); + MI.getOperand(i).setReg(PhysReg); } else { PhysRegsUsed[MO.getReg()] = true; } @@ -458,7 +458,7 @@ // Any stores to this stack slot are not dead anymore. MaybeDeadStores.erase(NewOp.StackSlot); - MI->SetMachineOperandReg(NewOp.Operand, NewPhysReg); + MI->getOperand(NewOp.Operand).setReg(NewPhysReg); Spills.addAvailable(NewOp.StackSlot, NewPhysReg); ++NumLoads; @@ -536,7 +536,7 @@ // This virtual register was assigned a physreg! unsigned Phys = VRM.getPhys(VirtReg); PhysRegsUsed[Phys] = true; - MI.SetMachineOperandReg(i, Phys); + MI.getOperand(i).setReg(Phys); continue; } @@ -567,7 +567,7 @@ << MRI->getName(PhysReg) << " for vreg" << VirtReg <<" instead of reloading into physreg " << MRI->getName(VRM.getPhys(VirtReg)) << "\n"); - MI.SetMachineOperandReg(i, PhysReg); + MI.getOperand(i).setReg(PhysReg); // The only technical detail we have is that we don't know that // PhysReg won't be clobbered by a reloaded stack slot that occurs @@ -618,7 +618,7 @@ << MRI->getName(PhysReg) << " for vreg" << VirtReg << " instead of reloading into same physreg.\n"); - MI.SetMachineOperandReg(i, PhysReg); + MI.getOperand(i).setReg(PhysReg); ++NumReused; continue; } @@ -633,7 +633,7 @@ Spills.ClobberPhysReg(DesignatedReg); Spills.addAvailable(StackSlot, DesignatedReg); - MI.SetMachineOperandReg(i, DesignatedReg); + MI.getOperand(i).setReg(DesignatedReg); DEBUG(std::cerr << '\t' << *prior(MII)); ++NumReused; continue; @@ -662,7 +662,7 @@ MaybeDeadStores.erase(StackSlot); Spills.addAvailable(StackSlot, PhysReg); ++NumLoads; - MI.SetMachineOperandReg(i, PhysReg); + MI.getOperand(i).setReg(PhysReg); DEBUG(std::cerr << '\t' << *prior(MII)); } @@ -817,7 +817,7 @@ PhysRegsUsed[PhysReg] = true; MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC); DEBUG(std::cerr << "Store:\t" << *next(MII)); - MI.SetMachineOperandReg(i, PhysReg); + MI.getOperand(i).setReg(PhysReg); // Check to see if this is a noop copy. If so, eliminate the // instruction before considering the dest reg to be changed. From lattner at cs.uiuc.edu Thu May 4 12:52:43 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 4 May 2006 12:52:43 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/TargetInstrInfo.cpp Message-ID: <200605041752.MAA18967@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target: TargetInstrInfo.cpp updated: 1.17 -> 1.18 --- Log message: Move some methods out of MachineInstr into MachineOperand --- Diffs of the changes: (+2 -2) TargetInstrInfo.cpp | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/Target/TargetInstrInfo.cpp diff -u llvm/lib/Target/TargetInstrInfo.cpp:1.17 llvm/lib/Target/TargetInstrInfo.cpp:1.18 --- llvm/lib/Target/TargetInstrInfo.cpp:1.17 Thu Apr 20 13:33:11 2006 +++ llvm/lib/Target/TargetInstrInfo.cpp Thu May 4 12:52:23 2006 @@ -46,7 +46,7 @@ "This only knows how to commute register operands so far"); unsigned Reg1 = MI->getOperand(1).getReg(); unsigned Reg2 = MI->getOperand(1).getReg(); - MI->SetMachineOperandReg(2, Reg1); - MI->SetMachineOperandReg(1, Reg2); + MI->getOperand(2).setReg(Reg1); + MI->getOperand(1).setReg(Reg2); return MI; } From lattner at cs.uiuc.edu Thu May 4 12:56:35 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 4 May 2006 12:56:35 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineInstr.h Message-ID: <200605041756.MAA19590@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineInstr.h updated: 1.175 -> 1.176 --- Log message: remove hasAllocatedReg --- Diffs of the changes: (+5 -18) MachineInstr.h | 23 +++++------------------ 1 files changed, 5 insertions(+), 18 deletions(-) Index: llvm/include/llvm/CodeGen/MachineInstr.h diff -u llvm/include/llvm/CodeGen/MachineInstr.h:1.175 llvm/include/llvm/CodeGen/MachineInstr.h:1.176 --- llvm/include/llvm/CodeGen/MachineInstr.h:1.175 Thu May 4 12:52:22 2006 +++ llvm/include/llvm/CodeGen/MachineInstr.h Thu May 4 12:56:20 2006 @@ -150,16 +150,11 @@ /// UseType getUseType() const { return UseType(flags & (USEFLAG|DEFFLAG)); } - /// isRegister - Return true if this operand is a register operand. - /// - bool isRegister() const { - return opType == MO_VirtualRegister; - } - /// Accessors that tell you what kind of MachineOperand you're looking at. /// - bool isMachineBasicBlock() const { return opType == MO_MachineBasicBlock; } + bool isRegister() const { return opType == MO_VirtualRegister; } bool isImmediate() const { return opType == MO_Immediate; } + bool isMachineBasicBlock() const { return opType == MO_MachineBasicBlock; } bool isFrameIndex() const { return opType == MO_FrameIndex; } bool isConstantPoolIndex() const { return opType == MO_ConstantPoolIndex; } bool isJumpTableIndex() const { return opType == MO_JumpTableIndex; } @@ -212,25 +207,17 @@ bool isDef () const { return flags & DEFFLAG; } MachineOperand& setDef () { flags |= DEFFLAG; return *this; } - /// hasAllocatedReg - Returns true iff a machine register has been - /// allocated to this operand. - /// - bool hasAllocatedReg() const { - return extra.regNum >= 0 && opType == MO_VirtualRegister; - } - - /// getReg - Returns the register number. It is a runtime error to call this - /// if a register is not allocated. + /// getReg - Returns the register number. /// unsigned getReg() const { - assert(hasAllocatedReg()); + assert(isRegister() && "This is not a register operand!"); return extra.regNum; } /// MachineOperand mutators. /// void setReg(unsigned Reg) { - assert(hasAllocatedReg() && "This operand cannot have a register number!"); + assert(isRegister() && "This is not a register operand!"); extra.regNum = Reg; } From lattner at cs.uiuc.edu Thu May 4 13:06:03 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 4 May 2006 13:06:03 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/MachineInstr.cpp Message-ID: <200605041806.NAA20126@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: MachineInstr.cpp updated: 1.118 -> 1.119 --- Log message: Rename MO_VirtualRegister -> MO_Register. Clean up immediate handling. --- Diffs of the changes: (+2 -2) MachineInstr.cpp | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/CodeGen/MachineInstr.cpp diff -u llvm/lib/CodeGen/MachineInstr.cpp:1.118 llvm/lib/CodeGen/MachineInstr.cpp:1.119 --- llvm/lib/CodeGen/MachineInstr.cpp:1.118 Thu May 4 12:52:23 2006 +++ llvm/lib/CodeGen/MachineInstr.cpp Thu May 4 13:05:43 2006 @@ -138,7 +138,7 @@ if (TM) MRI = TM->getRegisterInfo(); switch (MO.getType()) { - case MachineOperand::MO_VirtualRegister: + case MachineOperand::MO_Register: OutputReg(OS, MO.getReg(), MRI); break; case MachineOperand::MO_Immediate: @@ -235,7 +235,7 @@ std::ostream &llvm::operator<<(std::ostream &OS, const MachineOperand &MO) { switch (MO.getType()) { - case MachineOperand::MO_VirtualRegister: + case MachineOperand::MO_Register: OutputReg(OS, MO.getReg()); break; case MachineOperand::MO_Immediate: From lattner at cs.uiuc.edu Thu May 4 13:06:03 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 4 May 2006 13:06:03 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp Message-ID: <200605041806.NAA20132@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCAsmPrinter.cpp updated: 1.170 -> 1.171 --- Log message: Rename MO_VirtualRegister -> MO_Register. Clean up immediate handling. --- Diffs of the changes: (+1 -1) PPCAsmPrinter.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp diff -u llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.170 llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.171 --- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.170 Thu May 4 12:21:19 2006 +++ llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp Thu May 4 13:05:43 2006 @@ -86,7 +86,7 @@ void printOperand(const MachineInstr *MI, unsigned OpNo) { const MachineOperand &MO = MI->getOperand(OpNo); - if (MO.getType() == MachineOperand::MO_VirtualRegister) { + if (MO.isRegister()) { assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??"); O << TM.getRegisterInfo()->get(MO.getReg()).Name; } else if (MO.isImmediate()) { From lattner at cs.uiuc.edu Thu May 4 13:06:05 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 4 May 2006 13:06:05 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp Message-ID: <200605041806.NAA20163@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Alpha: AlphaAsmPrinter.cpp updated: 1.40 -> 1.41 --- Log message: Rename MO_VirtualRegister -> MO_Register. Clean up immediate handling. --- Diffs of the changes: (+2 -2) AlphaAsmPrinter.cpp | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp diff -u llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.40 llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.41 --- llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.40 Thu May 4 12:21:19 2006 +++ llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp Thu May 4 13:05:43 2006 @@ -77,7 +77,7 @@ void AlphaAsmPrinter::printOperand(const MachineInstr *MI, int opNum) { const MachineOperand &MO = MI->getOperand(opNum); - if (MO.getType() == MachineOperand::MO_VirtualRegister) { + if (MO.getType() == MachineOperand::MO_Register) { assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??"); O << TM.getRegisterInfo()->get(MO.getReg()).Name; } else if (MO.isImmediate()) { @@ -93,7 +93,7 @@ int new_symbol; switch (MO.getType()) { - case MachineOperand::MO_VirtualRegister: + case MachineOperand::MO_Register: O << RI.get(MO.getReg()).Name; return; From lattner at cs.uiuc.edu Thu May 4 13:06:03 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 4 May 2006 13:06:03 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Message-ID: <200605041806.NAA20134@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: ScheduleDAG.cpp updated: 1.84 -> 1.85 --- Log message: Rename MO_VirtualRegister -> MO_Register. Clean up immediate handling. --- Diffs of the changes: (+3 -3) ScheduleDAG.cpp | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.84 llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.85 --- llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.84 Wed May 3 20:15:02 2006 +++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Thu May 4 13:05:43 2006 @@ -104,7 +104,7 @@ } } else if (ConstantSDNode *C = dyn_cast(Op)) { - MI->addZeroExtImm64Operand(C->getValue()); + MI->addImmOperand(C->getValue()); } else if (RegisterSDNode*R = dyn_cast(Op)) { MI->addRegOperand(R->getReg(), MachineOperand::Use); @@ -303,7 +303,7 @@ unsigned Flags = cast(Node->getOperand(i))->getValue(); unsigned NumVals = Flags >> 3; - MI->addZeroExtImm64Operand(Flags); + MI->addImmOperand(Flags); ++i; // Skip the ID value. switch (Flags & 7) { @@ -323,7 +323,7 @@ case 3: { // Immediate. assert(NumVals == 1 && "Unknown immediate value!"); uint64_t Val = cast(Node->getOperand(i))->getValue(); - MI->addZeroExtImm64Operand(Val); + MI->addImmOperand(Val); ++i; break; } From lattner at cs.uiuc.edu Thu May 4 13:06:04 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 4 May 2006 13:06:04 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcAsmPrinter.cpp Message-ID: <200605041806.NAA20139@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Sparc: SparcAsmPrinter.cpp updated: 1.63 -> 1.64 --- Log message: Rename MO_VirtualRegister -> MO_Register. Clean up immediate handling. --- Diffs of the changes: (+5 -5) SparcAsmPrinter.cpp | 10 +++++----- 1 files changed, 5 insertions(+), 5 deletions(-) Index: llvm/lib/Target/Sparc/SparcAsmPrinter.cpp diff -u llvm/lib/Target/Sparc/SparcAsmPrinter.cpp:1.63 llvm/lib/Target/Sparc/SparcAsmPrinter.cpp:1.64 --- llvm/lib/Target/Sparc/SparcAsmPrinter.cpp:1.63 Thu May 4 12:21:19 2006 +++ llvm/lib/Target/Sparc/SparcAsmPrinter.cpp Thu May 4 13:05:43 2006 @@ -146,7 +146,7 @@ CloseParen = true; } switch (MO.getType()) { - case MachineOperand::MO_VirtualRegister: + case MachineOperand::MO_Register: if (MRegisterInfo::isPhysicalRegister(MO.getReg())) O << "%" << LowercaseString (RI.get(MO.getReg()).Name); else @@ -188,16 +188,16 @@ MachineOperand::MachineOperandType OpTy = MI->getOperand(opNum+1).getType(); - if (OpTy == MachineOperand::MO_VirtualRegister && + if (MI->getOperand(opNum+1).isRegister() && MI->getOperand(opNum+1).getReg() == SP::G0) return; // don't print "+%g0" - if (OpTy == MachineOperand::MO_Immediate && + if (MI->getOperand(opNum+1).isImmediate() && MI->getOperand(opNum+1).getImmedValue() == 0) return; // don't print "+0" O << "+"; - if (OpTy == MachineOperand::MO_GlobalAddress || - OpTy == MachineOperand::MO_ConstantPoolIndex) { + if (MI->getOperand(opNum+1).isGlobalAddress() || + MI->getOperand(opNum+1).isConstantPoolIndex()) { O << "%lo("; printOperand(MI, opNum+1); O << ")"; From lattner at cs.uiuc.edu Thu May 4 13:06:05 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 4 May 2006 13:06:05 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineInstr.h MachineInstrBuilder.h Message-ID: <200605041806.NAA20151@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineInstr.h updated: 1.176 -> 1.177 MachineInstrBuilder.h updated: 1.34 -> 1.35 --- Log message: Rename MO_VirtualRegister -> MO_Register. Clean up immediate handling. --- Diffs of the changes: (+19 -34) MachineInstr.h | 45 +++++++++++++++------------------------------ MachineInstrBuilder.h | 8 ++++---- 2 files changed, 19 insertions(+), 34 deletions(-) Index: llvm/include/llvm/CodeGen/MachineInstr.h diff -u llvm/include/llvm/CodeGen/MachineInstr.h:1.176 llvm/include/llvm/CodeGen/MachineInstr.h:1.177 --- llvm/include/llvm/CodeGen/MachineInstr.h:1.176 Thu May 4 12:56:20 2006 +++ llvm/include/llvm/CodeGen/MachineInstr.h Thu May 4 13:05:42 2006 @@ -61,7 +61,7 @@ }; enum MachineOperandType { - MO_VirtualRegister, // virtual register for *value + MO_Register, // Register operand. MO_Immediate, // Immediate Operand MO_MachineBasicBlock, // MachineBasicBlock reference MO_FrameIndex, // Abstract Stack Frame Index @@ -93,12 +93,17 @@ extra.offset = 0; } - MachineOperand(int64_t ImmVal, MachineOperandType OpTy, int Offset = 0) - : flags(0), opType(OpTy) { + MachineOperand(int64_t ImmVal) : flags(0), opType(MO_Immediate) { contents.immedVal = ImmVal; - extra.offset = Offset; + extra.offset = 0; } + MachineOperand(unsigned Idx, MachineOperandType OpTy) + : flags(0), opType(OpTy) { + contents.immedVal = Idx; + extra.offset = 0; + } + MachineOperand(int Reg, MachineOperandType OpTy, UseType UseTy) : flags(UseTy), opType(OpTy) { zeroContents(); @@ -152,7 +157,7 @@ /// Accessors that tell you what kind of MachineOperand you're looking at. /// - bool isRegister() const { return opType == MO_VirtualRegister; } + bool isRegister() const { return opType == MO_Register; } bool isImmediate() const { return opType == MO_Immediate; } bool isMachineBasicBlock() const { return opType == MO_MachineBasicBlock; } bool isFrameIndex() const { return opType == MO_FrameIndex; } @@ -245,7 +250,7 @@ /// the specified value. If an operand is known to be an register already, /// the setReg method should be used. void ChangeToRegister(unsigned Reg) { - opType = MO_VirtualRegister; + opType = MO_Register; extra.regNum = Reg; } @@ -355,41 +360,21 @@ /// addRegOperand - Add a symbolic virtual register reference... /// - void addRegOperand(int reg, bool isDef) { - assert(!OperandsComplete() && - "Trying to add an operand to a machine instr that is already done!"); - operands.push_back( - MachineOperand(reg, MachineOperand::MO_VirtualRegister, - isDef ? MachineOperand::Def : MachineOperand::Use)); - } - - /// addRegOperand - Add a symbolic virtual register reference... - /// void addRegOperand(int reg, MachineOperand::UseType UTy = MachineOperand::Use) { assert(!OperandsComplete() && "Trying to add an operand to a machine instr that is already done!"); operands.push_back( - MachineOperand(reg, MachineOperand::MO_VirtualRegister, UTy)); + MachineOperand(reg, MachineOperand::MO_Register, UTy)); } - /// addZeroExtImmOperand - Add a zero extended constant argument to the + /// addImmOperand - Add a zero extended constant argument to the /// machine instruction. /// - void addZeroExtImmOperand(int intValue) { - assert(!OperandsComplete() && - "Trying to add an operand to a machine instr that is already done!"); - operands.push_back( - MachineOperand(intValue, MachineOperand::MO_Immediate)); - } - - /// addZeroExtImm64Operand - Add a zero extended 64-bit constant argument - /// to the machine instruction. - /// - void addZeroExtImm64Operand(uint64_t intValue) { + void addImmOperand(int64_t Val) { assert(!OperandsComplete() && "Trying to add an operand to a machine instr that is already done!"); - operands.push_back(MachineOperand(intValue, MachineOperand::MO_Immediate)); + operands.push_back(MachineOperand(Val)); } void addMachineBasicBlockOperand(MachineBasicBlock *MBB) { Index: llvm/include/llvm/CodeGen/MachineInstrBuilder.h diff -u llvm/include/llvm/CodeGen/MachineInstrBuilder.h:1.34 llvm/include/llvm/CodeGen/MachineInstrBuilder.h:1.35 --- llvm/include/llvm/CodeGen/MachineInstrBuilder.h:1.34 Thu May 4 12:21:19 2006 +++ llvm/include/llvm/CodeGen/MachineInstrBuilder.h Thu May 4 13:05:43 2006 @@ -42,22 +42,22 @@ /// addImm - Add a new immediate operand. /// - const MachineInstrBuilder &addImm(int Val) const { - MI->addZeroExtImmOperand(Val); + const MachineInstrBuilder &addImm(int64_t Val) const { + MI->addImmOperand(Val); return *this; } /// addZImm - Add a new zero extended immediate operand... /// const MachineInstrBuilder &addZImm(unsigned Val) const { - MI->addZeroExtImmOperand(Val); + MI->addImmOperand(Val); return *this; } /// addImm64 - Add a new 64-bit immediate operand... /// const MachineInstrBuilder &addImm64(uint64_t Val) const { - MI->addZeroExtImm64Operand(Val); + MI->addImmOperand(Val); return *this; } From lattner at cs.uiuc.edu Thu May 4 13:06:04 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 4 May 2006 13:06:04 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/IA64/IA64AsmPrinter.cpp Message-ID: <200605041806.NAA20137@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/IA64: IA64AsmPrinter.cpp updated: 1.31 -> 1.32 --- Log message: Rename MO_VirtualRegister -> MO_Register. Clean up immediate handling. --- Diffs of the changes: (+2 -2) IA64AsmPrinter.cpp | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/Target/IA64/IA64AsmPrinter.cpp diff -u llvm/lib/Target/IA64/IA64AsmPrinter.cpp:1.31 llvm/lib/Target/IA64/IA64AsmPrinter.cpp:1.32 --- llvm/lib/Target/IA64/IA64AsmPrinter.cpp:1.31 Thu May 4 12:21:19 2006 +++ llvm/lib/Target/IA64/IA64AsmPrinter.cpp Thu May 4 13:05:43 2006 @@ -66,7 +66,7 @@ // This method is used by the tablegen'erated instruction printer. void printOperand(const MachineInstr *MI, unsigned OpNo){ const MachineOperand &MO = MI->getOperand(OpNo); - if (MO.getType() == MachineOperand::MO_VirtualRegister) { + if (MO.getType() == MachineOperand::MO_Register) { assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physref??"); //XXX Bug Workaround: See note in Printer::doInitialization about %. O << TM.getRegisterInfo()->get(MO.getReg()).Name; @@ -173,7 +173,7 @@ bool isBRCALLinsn /* = false */) { const MRegisterInfo &RI = *TM.getRegisterInfo(); switch (MO.getType()) { - case MachineOperand::MO_VirtualRegister: + case MachineOperand::MO_Register: O << RI.get(MO.getReg()).Name; return; From lattner at cs.uiuc.edu Thu May 4 13:06:05 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 4 May 2006 13:06:05 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp X86IntelAsmPrinter.cpp X86IntelAsmPrinter.h Message-ID: <200605041806.NAA20159@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ATTAsmPrinter.cpp updated: 1.41 -> 1.42 X86IntelAsmPrinter.cpp updated: 1.40 -> 1.41 X86IntelAsmPrinter.h updated: 1.20 -> 1.21 --- Log message: Rename MO_VirtualRegister -> MO_Register. Clean up immediate handling. --- Diffs of the changes: (+3 -3) X86ATTAsmPrinter.cpp | 2 +- X86IntelAsmPrinter.cpp | 2 +- X86IntelAsmPrinter.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) Index: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp diff -u llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.41 llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.42 --- llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.41 Thu May 4 12:21:20 2006 +++ llvm/lib/Target/X86/X86ATTAsmPrinter.cpp Thu May 4 13:05:43 2006 @@ -108,7 +108,7 @@ const MachineOperand &MO = MI->getOperand(OpNo); const MRegisterInfo &RI = *TM.getRegisterInfo(); switch (MO.getType()) { - case MachineOperand::MO_VirtualRegister: + case MachineOperand::MO_Register: assert(MRegisterInfo::isPhysicalRegister(MO.getReg()) && "Virtual registers should not make it this far!"); O << '%'; Index: llvm/lib/Target/X86/X86IntelAsmPrinter.cpp diff -u llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.40 llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.41 --- llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.40 Thu May 4 12:21:20 2006 +++ llvm/lib/Target/X86/X86IntelAsmPrinter.cpp Thu May 4 13:05:43 2006 @@ -100,7 +100,7 @@ const char *Modifier) { const MRegisterInfo &RI = *TM.getRegisterInfo(); switch (MO.getType()) { - case MachineOperand::MO_VirtualRegister: + case MachineOperand::MO_Register: if (MRegisterInfo::isPhysicalRegister(MO.getReg())) O << RI.get(MO.getReg()).Name; else Index: llvm/lib/Target/X86/X86IntelAsmPrinter.h diff -u llvm/lib/Target/X86/X86IntelAsmPrinter.h:1.20 llvm/lib/Target/X86/X86IntelAsmPrinter.h:1.21 --- llvm/lib/Target/X86/X86IntelAsmPrinter.h:1.20 Wed May 3 20:15:02 2006 +++ llvm/lib/Target/X86/X86IntelAsmPrinter.h Thu May 4 13:05:43 2006 @@ -37,7 +37,7 @@ void printOperand(const MachineInstr *MI, unsigned OpNo, const char *Modifier = 0) { const MachineOperand &MO = MI->getOperand(OpNo); - if (MO.getType() == MachineOperand::MO_VirtualRegister) { + if (MO.isRegister()) { assert(MRegisterInfo::isPhysicalRegister(MO.getReg()) && "Not physreg??"); O << TM.getRegisterInfo()->get(MO.getReg()).Name; } else { From lattner at cs.uiuc.edu Thu May 4 13:16:16 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 4 May 2006 13:16:16 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/MachineBasicBlock.cpp MachineInstr.cpp Message-ID: <200605041816.NAA21889@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: MachineBasicBlock.cpp updated: 1.26 -> 1.27 MachineInstr.cpp updated: 1.119 -> 1.120 --- Log message: Remove and simplify some more machineinstr/machineoperand stuff. --- Diffs of the changes: (+2 -2) MachineBasicBlock.cpp | 2 +- MachineInstr.cpp | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/CodeGen/MachineBasicBlock.cpp diff -u llvm/lib/CodeGen/MachineBasicBlock.cpp:1.26 llvm/lib/CodeGen/MachineBasicBlock.cpp:1.27 --- llvm/lib/CodeGen/MachineBasicBlock.cpp:1.26 Wed May 3 20:26:39 2006 +++ llvm/lib/CodeGen/MachineBasicBlock.cpp Thu May 4 13:16:01 2006 @@ -47,7 +47,7 @@ MachineInstr* ilist_traits::createSentinel() { - MachineInstr* dummy = new MachineInstr(0, 0, true, true); + MachineInstr* dummy = new MachineInstr(0, 0); LeakDetector::removeGarbageObject(dummy); return dummy; } Index: llvm/lib/CodeGen/MachineInstr.cpp diff -u llvm/lib/CodeGen/MachineInstr.cpp:1.119 llvm/lib/CodeGen/MachineInstr.cpp:1.120 --- llvm/lib/CodeGen/MachineInstr.cpp:1.119 Thu May 4 13:05:43 2006 +++ llvm/lib/CodeGen/MachineInstr.cpp Thu May 4 13:16:01 2006 @@ -41,7 +41,7 @@ /// add* methods below to fill up the operands, instead of the Set methods. /// Eventually, the "resizing" ctors will be phased out. /// -MachineInstr::MachineInstr(short opcode, unsigned numOperands, bool XX, bool YY) +MachineInstr::MachineInstr(short opcode, unsigned numOperands) : Opcode(opcode), parent(0) { operands.reserve(numOperands); // Make sure that we get added to a machine basicblock From lattner at cs.uiuc.edu Thu May 4 13:16:17 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 4 May 2006 13:16:17 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Message-ID: <200605041816.NAA21897@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: ScheduleDAG.cpp updated: 1.85 -> 1.86 --- Log message: Remove and simplify some more machineinstr/machineoperand stuff. --- Diffs of the changes: (+1 -1) ScheduleDAG.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.85 llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.86 --- llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.85 Thu May 4 13:05:43 2006 +++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Thu May 4 13:16:01 2006 @@ -184,7 +184,7 @@ #endif // Create the new machine instruction. - MachineInstr *MI = new MachineInstr(Opc, NumMIOperands, true, true); + MachineInstr *MI = new MachineInstr(Opc, NumMIOperands); // Add result register values for things that are defined by this // instruction. From lattner at cs.uiuc.edu Thu May 4 13:16:17 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 4 May 2006 13:16:17 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineInstr.h MachineInstrBuilder.h Message-ID: <200605041816.NAA21895@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineInstr.h updated: 1.177 -> 1.178 MachineInstrBuilder.h updated: 1.35 -> 1.36 --- Log message: Remove and simplify some more machineinstr/machineoperand stuff. --- Diffs of the changes: (+10 -44) MachineInstr.h | 30 +++++------------------------- MachineInstrBuilder.h | 24 +++++------------------- 2 files changed, 10 insertions(+), 44 deletions(-) Index: llvm/include/llvm/CodeGen/MachineInstr.h diff -u llvm/include/llvm/CodeGen/MachineInstr.h:1.177 llvm/include/llvm/CodeGen/MachineInstr.h:1.178 --- llvm/include/llvm/CodeGen/MachineInstr.h:1.177 Thu May 4 13:05:42 2006 +++ llvm/include/llvm/CodeGen/MachineInstr.h Thu May 4 13:16:01 2006 @@ -261,23 +261,8 @@ //===----------------------------------------------------------------------===// -// class MachineInstr -// -// Purpose: -// Representation of each machine instruction. -// -// MachineOpCode must be an enum, defined separately for each target. -// E.g., It is defined in SparcInstructionSelection.h for the SPARC. -// -// There are 2 kinds of operands: -// -// (1) Explicit operands of the machine instruction in vector operands[] -// -// (2) "Implicit operands" are values implicitly used or defined by the -// machine instruction, such as arguments to a CALL, return value of -// a CALL (if any), and return value of a RETURN. -//===----------------------------------------------------------------------===// - +/// MachineInstr - Representation of each machine instruction. +/// class MachineInstr { short Opcode; // the opcode std::vector operands; // the operands @@ -287,9 +272,7 @@ // OperandComplete - Return true if it's illegal to add a new operand bool OperandsComplete() const; - //Constructor used by clone() method MachineInstr(const MachineInstr&); - void operator=(const MachineInstr&); // DO NOT IMPLEMENT // Intrusive list support @@ -297,12 +280,9 @@ friend struct ilist_traits; public: - /// MachineInstr ctor - This constructor only does a _reserve_ of the - /// operands, not a resize for them. It is expected that if you use this that - /// you call add* methods below to fill up the operands, instead of the Set - /// methods. Eventually, the "resizing" ctors will be phased out. - /// - MachineInstr(short Opcode, unsigned numOperands, bool XX, bool YY); + /// MachineInstr ctor - This constructor reserve's space for numOperand + /// operands. + MachineInstr(short Opcode, unsigned numOperands); /// MachineInstr ctor - Work exactly the same as the ctor above, except that /// the MachineInstr is created and added to the end of the specified basic Index: llvm/include/llvm/CodeGen/MachineInstrBuilder.h diff -u llvm/include/llvm/CodeGen/MachineInstrBuilder.h:1.35 llvm/include/llvm/CodeGen/MachineInstrBuilder.h:1.36 --- llvm/include/llvm/CodeGen/MachineInstrBuilder.h:1.35 Thu May 4 13:05:43 2006 +++ llvm/include/llvm/CodeGen/MachineInstrBuilder.h Thu May 4 13:16:01 2006 @@ -47,20 +47,6 @@ return *this; } - /// addZImm - Add a new zero extended immediate operand... - /// - const MachineInstrBuilder &addZImm(unsigned Val) const { - MI->addImmOperand(Val); - return *this; - } - - /// addImm64 - Add a new 64-bit immediate operand... - /// - const MachineInstrBuilder &addImm64(uint64_t Val) const { - MI->addImmOperand(Val); - return *this; - } - const MachineInstrBuilder &addMBB(MachineBasicBlock *MBB) const { MI->addMachineBasicBlockOperand(MBB); return *this; @@ -99,7 +85,7 @@ /// allow for memory efficient representation of machine instructions. /// inline MachineInstrBuilder BuildMI(int Opcode, unsigned NumOperands) { - return MachineInstrBuilder(new MachineInstr(Opcode, NumOperands, true, true)); + return MachineInstrBuilder(new MachineInstr(Opcode, NumOperands)); } /// BuildMI - This version of the builder sets up the first operand as a @@ -110,8 +96,8 @@ int Opcode, unsigned NumOperands, unsigned DestReg, MachineOperand::UseType useType = MachineOperand::Def) { - return MachineInstrBuilder(new MachineInstr(Opcode, NumOperands+1, - true, true)).addReg(DestReg, useType); + return MachineInstrBuilder(new MachineInstr(Opcode, NumOperands+1)) + .addReg(DestReg, useType); } /// BuildMI - This version of the builder inserts the newly-built @@ -124,7 +110,7 @@ MachineBasicBlock::iterator I, int Opcode, unsigned NumOperands, unsigned DestReg) { - MachineInstr *MI = new MachineInstr(Opcode, NumOperands+1, true, true); + MachineInstr *MI = new MachineInstr(Opcode, NumOperands+1); BB.insert(I, MI); return MachineInstrBuilder(MI).addReg(DestReg, MachineOperand::Def); } @@ -136,7 +122,7 @@ inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineBasicBlock::iterator I, int Opcode, unsigned NumOperands) { - MachineInstr *MI = new MachineInstr(Opcode, NumOperands, true, true); + MachineInstr *MI = new MachineInstr(Opcode, NumOperands); BB.insert(I, MI); return MachineInstrBuilder(MI); } From lattner at cs.uiuc.edu Thu May 4 13:16:17 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 4 May 2006 13:16:17 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrBuilder.h X86RegisterInfo.cpp Message-ID: <200605041816.NAA21905@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrBuilder.h updated: 1.19 -> 1.20 X86RegisterInfo.cpp updated: 1.148 -> 1.149 --- Log message: Remove and simplify some more machineinstr/machineoperand stuff. --- Diffs of the changes: (+15 -15) X86InstrBuilder.h | 12 ++++++------ X86RegisterInfo.cpp | 18 +++++++++--------- 2 files changed, 15 insertions(+), 15 deletions(-) Index: llvm/lib/Target/X86/X86InstrBuilder.h diff -u llvm/lib/Target/X86/X86InstrBuilder.h:1.19 llvm/lib/Target/X86/X86InstrBuilder.h:1.20 --- llvm/lib/Target/X86/X86InstrBuilder.h:1.19 Thu May 4 12:21:20 2006 +++ llvm/lib/Target/X86/X86InstrBuilder.h Thu May 4 13:16:01 2006 @@ -61,7 +61,7 @@ unsigned Reg) { // Because memory references are always represented with four // values, this adds: Reg, [1, NoReg, 0] to the instruction. - return MIB.addReg(Reg).addZImm(1).addReg(0).addImm(0); + return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0); } @@ -71,14 +71,14 @@ /// inline const MachineInstrBuilder &addRegOffset(const MachineInstrBuilder &MIB, unsigned Reg, int Offset) { - return MIB.addReg(Reg).addZImm(1).addReg(0).addImm(Offset); + return MIB.addReg(Reg).addImm(1).addReg(0).addImm(Offset); } /// addRegReg - This function is used to add a memory reference of the form: /// [Reg + Reg]. inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB, unsigned Reg1, unsigned Reg2) { - return MIB.addReg(Reg1).addZImm(1).addReg(Reg2).addImm(0); + return MIB.addReg(Reg1).addImm(1).addReg(Reg2).addImm(0); } inline const MachineInstrBuilder &addFullAddress(const MachineInstrBuilder &MIB, @@ -91,7 +91,7 @@ MIB.addFrameIndex(AM.Base.FrameIndex); else assert (0); - MIB.addZImm(AM.Scale).addReg(AM.IndexReg); + MIB.addImm(AM.Scale).addReg(AM.IndexReg); if (AM.GV) return MIB.addGlobalAddress(AM.GV, AM.Disp); else @@ -105,7 +105,7 @@ /// inline const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0) { - return MIB.addFrameIndex(FI).addZImm(1).addReg(0).addImm(Offset); + return MIB.addFrameIndex(FI).addImm(1).addReg(0).addImm(Offset); } /// addConstantPoolReference - This function is used to add a reference to the @@ -117,7 +117,7 @@ inline const MachineInstrBuilder & addConstantPoolReference(const MachineInstrBuilder &MIB, unsigned CPI, int Offset = 0) { - return MIB.addConstantPoolIndex(CPI).addZImm(1).addReg(0).addImm(Offset); + return MIB.addConstantPoolIndex(CPI).addImm(1).addReg(0).addImm(Offset); } } // End llvm namespace Index: llvm/lib/Target/X86/X86RegisterInfo.cpp diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.148 llvm/lib/Target/X86/X86RegisterInfo.cpp:1.149 --- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.148 Thu May 4 12:52:23 2006 +++ llvm/lib/Target/X86/X86RegisterInfo.cpp Thu May 4 13:16:01 2006 @@ -139,14 +139,14 @@ MachineInstr *MI) { return addFrameReference(BuildMI(Opcode, 6), FrameIndex) .addReg(MI->getOperand(1).getReg()) - .addZImm(MI->getOperand(2).getImmedValue()); + .addImm(MI->getOperand(2).getImmedValue()); } static MachineInstr *MakeMIInst(unsigned Opcode, unsigned FrameIndex, MachineInstr *MI) { if (MI->getOperand(1).isImmediate()) return addFrameReference(BuildMI(Opcode, 5), FrameIndex) - .addZImm(MI->getOperand(1).getImmedValue()); + .addImm(MI->getOperand(1).getImmedValue()); else if (MI->getOperand(1).isGlobalAddress()) return addFrameReference(BuildMI(Opcode, 5), FrameIndex) .addGlobalAddress(MI->getOperand(1).getGlobal(), @@ -160,7 +160,7 @@ static MachineInstr *MakeM0Inst(unsigned Opcode, unsigned FrameIndex, MachineInstr *MI) { - return addFrameReference(BuildMI(Opcode, 5), FrameIndex).addZImm(0); + return addFrameReference(BuildMI(Opcode, 5), FrameIndex).addImm(0); } static MachineInstr *MakeRMInst(unsigned Opcode, unsigned FrameIndex, @@ -174,7 +174,7 @@ MachineInstr *MI) { const MachineOperand& op = MI->getOperand(0); return addFrameReference(BuildMI(Opcode, 6, op.getReg(), op.getUseType()), - FrameIndex).addZImm(MI->getOperand(2).getImmedValue()); + FrameIndex).addImm(MI->getOperand(2).getImmedValue()); } @@ -620,7 +620,7 @@ MachineInstr *New = 0; if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) { New=BuildMI(X86::SUB32ri, 1, X86::ESP, MachineOperand::UseAndDef) - .addZImm(Amount); + .addImm(Amount); } else { assert(Old->getOpcode() == X86::ADJCALLSTACKUP); // factor out the amount the callee already popped. @@ -629,7 +629,7 @@ if (Amount) { unsigned Opc = Amount < 128 ? X86::ADD32ri8 : X86::ADD32ri; New = BuildMI(Opc, 1, X86::ESP, - MachineOperand::UseAndDef).addZImm(Amount); + MachineOperand::UseAndDef).addImm(Amount); } } @@ -644,7 +644,7 @@ unsigned Opc = CalleeAmt < 128 ? X86::SUB32ri8 : X86::SUB32ri; MachineInstr *New = BuildMI(Opc, 1, X86::ESP, - MachineOperand::UseAndDef).addZImm(CalleeAmt); + MachineOperand::UseAndDef).addImm(CalleeAmt); MBB.insert(I, New); } } @@ -793,11 +793,11 @@ if (NumBytes > 0) { unsigned Opc = NumBytes < 128 ? X86::ADD32ri8 : X86::ADD32ri; BuildMI(MBB, MBBI, Opc, 2) - .addReg(X86::ESP, MachineOperand::UseAndDef).addZImm(NumBytes); + .addReg(X86::ESP, MachineOperand::UseAndDef).addImm(NumBytes); } else if ((int)NumBytes < 0) { unsigned Opc = -NumBytes < 128 ? X86::SUB32ri8 : X86::SUB32ri; BuildMI(MBB, MBBI, Opc, 2) - .addReg(X86::ESP, MachineOperand::UseAndDef).addZImm(-NumBytes); + .addReg(X86::ESP, MachineOperand::UseAndDef).addImm(-NumBytes); } } } From lattner at cs.uiuc.edu Thu May 4 13:25:32 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 4 May 2006 13:25:32 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineInstr.h Message-ID: <200605041825.NAA22069@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineInstr.h updated: 1.178 -> 1.179 --- Log message: Move register numbers out of "extra" into "contents". Other minor cleanup. --- Diffs of the changes: (+21 -34) MachineInstr.h | 55 +++++++++++++++++++++---------------------------------- 1 files changed, 21 insertions(+), 34 deletions(-) Index: llvm/include/llvm/CodeGen/MachineInstr.h diff -u llvm/include/llvm/CodeGen/MachineInstr.h:1.178 llvm/include/llvm/CodeGen/MachineInstr.h:1.179 --- llvm/include/llvm/CodeGen/MachineInstr.h:1.178 Thu May 4 13:16:01 2006 +++ llvm/include/llvm/CodeGen/MachineInstr.h Thu May 4 13:25:20 2006 @@ -32,8 +32,6 @@ template struct ilist_traits; template struct ilist; -typedef short MachineOpCode; - //===----------------------------------------------------------------------===// // class MachineOperand // @@ -77,64 +75,53 @@ int64_t immedVal; // Constant value for an explicit constant MachineBasicBlock *MBB; // For MO_MachineBasicBlock type const char *SymbolName; // For MO_ExternalSymbol type + unsigned RegNo; // For MO_Register number for an explicit register } contents; char flags; // see bit field definitions above MachineOperandType opType:8; // Pack into 8 bits efficiently after flags. - union { - int regNum; // register number for an explicit register - int offset; // Offset to address of global or external, only - // valid for MO_GlobalAddress, MO_ExternalSym - // and MO_ConstantPoolIndex - } extra; - - void zeroContents() { - contents.immedVal = 0; - extra.offset = 0; - } + + /// offset - Offset to address of global or external, only valid for + /// MO_GlobalAddress, MO_ExternalSym and MO_ConstantPoolIndex + int offset; MachineOperand(int64_t ImmVal) : flags(0), opType(MO_Immediate) { contents.immedVal = ImmVal; - extra.offset = 0; + offset = 0; } - MachineOperand(unsigned Idx, MachineOperandType OpTy) - : flags(0), opType(OpTy) { + MachineOperand(unsigned Idx, MachineOperandType OpTy): flags(0), opType(OpTy){ contents.immedVal = Idx; - extra.offset = 0; + offset = 0; } MachineOperand(int Reg, MachineOperandType OpTy, UseType UseTy) : flags(UseTy), opType(OpTy) { - zeroContents(); - extra.regNum = Reg; + contents.RegNo = Reg; + offset = 0; } MachineOperand(GlobalValue *V, int Offset = 0) : flags(MachineOperand::Use), opType(MachineOperand::MO_GlobalAddress) { contents.GV = V; - extra.offset = Offset; + offset = Offset; } MachineOperand(MachineBasicBlock *mbb) : flags(0), opType(MO_MachineBasicBlock) { - zeroContents (); contents.MBB = mbb; + offset = 0; } MachineOperand(const char *SymName, int Offset) : flags(0), opType(MO_ExternalSymbol) { - zeroContents (); contents.SymbolName = SymName; - extra.offset = Offset; + offset = Offset; } public: - MachineOperand(const MachineOperand &M) - : flags(M.flags), opType(M.opType) { - zeroContents (); - contents = M.contents; - extra = M.extra; + MachineOperand(const MachineOperand &M) { + *this = M; } ~MachineOperand() {} @@ -143,7 +130,7 @@ contents = MO.contents; flags = MO.flags; opType = MO.opType; - extra = MO.extra; + offset = MO.offset; return *this; } @@ -197,7 +184,7 @@ int getOffset() const { assert((isGlobalAddress() || isExternalSymbol() || isConstantPoolIndex()) && "Wrong MachineOperand accessor"); - return extra.offset; + return offset; } const char *getSymbolName() const { assert(isExternalSymbol() && "Wrong MachineOperand accessor"); @@ -216,14 +203,14 @@ /// unsigned getReg() const { assert(isRegister() && "This is not a register operand!"); - return extra.regNum; + return contents.RegNo; } /// MachineOperand mutators. /// void setReg(unsigned Reg) { assert(isRegister() && "This is not a register operand!"); - extra.regNum = Reg; + contents.RegNo = Reg; } void setImmedValue(int64_t immVal) { @@ -235,7 +222,7 @@ assert((isGlobalAddress() || isExternalSymbol() || isConstantPoolIndex() || isJumpTableIndex()) && "Wrong MachineOperand accessor"); - extra.offset = Offset; + offset = Offset; } /// ChangeToImmediate - Replace this operand with a new immediate operand of @@ -251,7 +238,7 @@ /// the setReg method should be used. void ChangeToRegister(unsigned Reg) { opType = MO_Register; - extra.regNum = Reg; + contents.RegNo = Reg; } friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop); From lattner at cs.uiuc.edu Thu May 4 14:15:09 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 4 May 2006 14:15:09 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineInstr.h Message-ID: <200605041915.OAA03807@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineInstr.h updated: 1.179 -> 1.180 --- Log message: Remove redundancy and a level of indirection when creating machine operands --- Diffs of the changes: (+59 -68) MachineInstr.h | 127 ++++++++++++++++++++++++++------------------------------- 1 files changed, 59 insertions(+), 68 deletions(-) Index: llvm/include/llvm/CodeGen/MachineInstr.h diff -u llvm/include/llvm/CodeGen/MachineInstr.h:1.179 llvm/include/llvm/CodeGen/MachineInstr.h:1.180 --- llvm/include/llvm/CodeGen/MachineInstr.h:1.179 Thu May 4 13:25:20 2006 +++ llvm/include/llvm/CodeGen/MachineInstr.h Thu May 4 14:14:44 2006 @@ -85,40 +85,7 @@ /// MO_GlobalAddress, MO_ExternalSym and MO_ConstantPoolIndex int offset; - MachineOperand(int64_t ImmVal) : flags(0), opType(MO_Immediate) { - contents.immedVal = ImmVal; - offset = 0; - } - - MachineOperand(unsigned Idx, MachineOperandType OpTy): flags(0), opType(OpTy){ - contents.immedVal = Idx; - offset = 0; - } - - MachineOperand(int Reg, MachineOperandType OpTy, UseType UseTy) - : flags(UseTy), opType(OpTy) { - contents.RegNo = Reg; - offset = 0; - } - - MachineOperand(GlobalValue *V, int Offset = 0) - : flags(MachineOperand::Use), opType(MachineOperand::MO_GlobalAddress) { - contents.GV = V; - offset = Offset; - } - - MachineOperand(MachineBasicBlock *mbb) - : flags(0), opType(MO_MachineBasicBlock) { - contents.MBB = mbb; - offset = 0; - } - - MachineOperand(const char *SymName, int Offset) - : flags(0), opType(MO_ExternalSymbol) { - contents.SymbolName = SymName; - offset = Offset; - } - + MachineOperand() {} public: MachineOperand(const MachineOperand &M) { *this = M; @@ -252,7 +219,7 @@ /// class MachineInstr { short Opcode; // the opcode - std::vector operands; // the operands + std::vector Operands; // the operands MachineInstr* prev, *next; // links for our intrusive list MachineBasicBlock* parent; // pointer to the owning basic block @@ -288,21 +255,21 @@ /// Access to explicit operands of the instruction. /// - unsigned getNumOperands() const { return operands.size(); } + unsigned getNumOperands() const { return Operands.size(); } const MachineOperand& getOperand(unsigned i) const { assert(i < getNumOperands() && "getOperand() out of range!"); - return operands[i]; + return Operands[i]; } MachineOperand& getOperand(unsigned i) { assert(i < getNumOperands() && "getOperand() out of range!"); - return operands[i]; + return Operands[i]; } /// clone - Create a copy of 'this' instruction that is identical in /// all ways except the the instruction has no parent, prev, or next. - MachineInstr* clone() const; + MachineInstr* clone() const { return new MachineInstr(*this); } /// removeFromParent - This method unlinks 'this' from the containing basic /// block, and returns it, but does not delete it. @@ -322,70 +289,87 @@ friend std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr); //===--------------------------------------------------------------------===// - // Accessors to add operands when building up machine instructions + // Accessors to add operands when building up machine instructions. // - /// addRegOperand - Add a symbolic virtual register reference... + /// addRegOperand - Add a register operand. /// - void addRegOperand(int reg, + void addRegOperand(unsigned Reg, MachineOperand::UseType UTy = MachineOperand::Use) { - assert(!OperandsComplete() && - "Trying to add an operand to a machine instr that is already done!"); - operands.push_back( - MachineOperand(reg, MachineOperand::MO_Register, UTy)); + MachineOperand &Op = AddNewOperand(); + Op.opType = MachineOperand::MO_Register; + Op.flags = UTy; + Op.contents.RegNo = Reg; + Op.offset = 0; } /// addImmOperand - Add a zero extended constant argument to the /// machine instruction. /// void addImmOperand(int64_t Val) { - assert(!OperandsComplete() && - "Trying to add an operand to a machine instr that is already done!"); - operands.push_back(MachineOperand(Val)); + MachineOperand &Op = AddNewOperand(); + Op.opType = MachineOperand::MO_Immediate; + Op.flags = 0; + Op.contents.immedVal = Val; + Op.offset = 0; } void addMachineBasicBlockOperand(MachineBasicBlock *MBB) { - assert(!OperandsComplete() && - "Trying to add an operand to a machine instr that is already done!"); - operands.push_back(MachineOperand(MBB)); + MachineOperand &Op = AddNewOperand(); + Op.opType = MachineOperand::MO_MachineBasicBlock; + Op.flags = 0; + Op.contents.MBB = MBB; + Op.offset = 0; } /// addFrameIndexOperand - Add an abstract frame index to the instruction /// void addFrameIndexOperand(unsigned Idx) { - assert(!OperandsComplete() && - "Trying to add an operand to a machine instr that is already done!"); - operands.push_back(MachineOperand(Idx, MachineOperand::MO_FrameIndex)); + MachineOperand &Op = AddNewOperand(); + Op.opType = MachineOperand::MO_FrameIndex; + Op.flags = 0; + Op.contents.immedVal = Idx; + Op.offset = 0; } /// addConstantPoolndexOperand - Add a constant pool object index to the /// instruction. /// - void addConstantPoolIndexOperand(unsigned I, int Offset=0) { - assert(!OperandsComplete() && - "Trying to add an operand to a machine instr that is already done!"); - operands.push_back(MachineOperand(I, MachineOperand::MO_ConstantPoolIndex)); + void addConstantPoolIndexOperand(unsigned Idx, int Offset) { + MachineOperand &Op = AddNewOperand(); + Op.opType = MachineOperand::MO_ConstantPoolIndex; + Op.flags = 0; + Op.contents.immedVal = Idx; + Op.offset = Offset; } /// addJumpTableIndexOperand - Add a jump table object index to the /// instruction. /// - void addJumpTableIndexOperand(unsigned I) { - assert(!OperandsComplete() && - "Trying to add an operand to a machine instr that is already done!"); - operands.push_back(MachineOperand(I, MachineOperand::MO_JumpTableIndex)); + void addJumpTableIndexOperand(unsigned Idx) { + MachineOperand &Op = AddNewOperand(); + Op.opType = MachineOperand::MO_JumpTableIndex; + Op.flags = 0; + Op.contents.immedVal = Idx; + Op.offset = 0; } void addGlobalAddressOperand(GlobalValue *GV, int Offset) { - assert(!OperandsComplete() && - "Trying to add an operand to a machine instr that is already done!"); - operands.push_back(MachineOperand(GV, Offset)); + MachineOperand &Op = AddNewOperand(); + Op.opType = MachineOperand::MO_GlobalAddress; + Op.flags = 0; + Op.contents.GV = GV; + Op.offset = Offset; } /// addExternalSymbolOperand - Add an external symbol operand to this instr /// void addExternalSymbolOperand(const char *SymName) { - operands.push_back(MachineOperand(SymName, 0)); + MachineOperand &Op = AddNewOperand(); + Op.opType = MachineOperand::MO_ExternalSymbol; + Op.flags = 0; + Op.contents.SymbolName = SymName; + Op.offset = 0; } //===--------------------------------------------------------------------===// @@ -400,7 +384,14 @@ /// fewer operand than it started with. /// void RemoveOperand(unsigned i) { - operands.erase(operands.begin()+i); + Operands.erase(Operands.begin()+i); + } +private: + MachineOperand &AddNewOperand() { + assert(!OperandsComplete() && + "Trying to add an operand to a machine instr that is already done!"); + Operands.push_back(MachineOperand()); + return Operands.back(); } }; From lattner at cs.uiuc.edu Thu May 4 14:15:09 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 4 May 2006 14:15:09 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/MachineInstr.cpp Message-ID: <200605041915.OAA03808@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: MachineInstr.cpp updated: 1.120 -> 1.121 --- Log message: Remove redundancy and a level of indirection when creating machine operands --- Diffs of the changes: (+5 -21) MachineInstr.cpp | 26 +++++--------------------- 1 files changed, 5 insertions(+), 21 deletions(-) Index: llvm/lib/CodeGen/MachineInstr.cpp diff -u llvm/lib/CodeGen/MachineInstr.cpp:1.120 llvm/lib/CodeGen/MachineInstr.cpp:1.121 --- llvm/lib/CodeGen/MachineInstr.cpp:1.120 Thu May 4 13:16:01 2006 +++ llvm/lib/CodeGen/MachineInstr.cpp Thu May 4 14:14:44 2006 @@ -43,7 +43,7 @@ /// MachineInstr::MachineInstr(short opcode, unsigned numOperands) : Opcode(opcode), parent(0) { - operands.reserve(numOperands); + Operands.reserve(numOperands); // Make sure that we get added to a machine basicblock LeakDetector::addGarbageObject(this); } @@ -55,7 +55,7 @@ unsigned numOperands) : Opcode(opcode), parent(0) { assert(MBB && "Cannot use inserting ctor with null basic block!"); - operands.reserve(numOperands); + Operands.reserve(numOperands); // Make sure that we get added to a machine basicblock LeakDetector::addGarbageObject(this); MBB->push_back(this); // Add instruction to end of basic block! @@ -65,11 +65,11 @@ /// MachineInstr::MachineInstr(const MachineInstr &MI) { Opcode = MI.getOpcode(); - operands.reserve(MI.getNumOperands()); + Operands.reserve(MI.getNumOperands()); // Add operands - for (unsigned i = 0; i < MI.getNumOperands(); ++i) - operands.push_back(MachineOperand(MI.getOperand(i))); + for (unsigned i = 0; i != MI.getNumOperands(); ++i) + Operands.push_back(MI.getOperand(i)); // Set parent, next, and prev to null parent = 0; @@ -82,13 +82,6 @@ LeakDetector::removeGarbageObject(this); } -/// clone - Create a copy of 'this' instruction that is identical in all ways -/// except the following: the new instruction has no parent and it has no name -/// -MachineInstr* MachineInstr::clone() const { - return new MachineInstr(*this); -} - /// removeFromParent - This method unlinks 'this' from the containing basic /// block, and returns it, but does not delete it. MachineInstr *MachineInstr::removeFromParent() { @@ -111,15 +104,6 @@ std::cerr << " " << *this; } -static inline std::ostream& OutputValue(std::ostream &os, const Value* val) { - os << "(val "; - os << (void*) val; // print address always - if (val && val->hasName()) - os << " " << val->getName(); // print name also, if available - os << ")"; - return os; -} - static inline void OutputReg(std::ostream &os, unsigned RegNo, const MRegisterInfo *MRI = 0) { if (!RegNo || MRegisterInfo::isPhysicalRegister(RegNo)) { From evan.cheng at apple.com Thu May 4 14:16:51 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 4 May 2006 14:16:51 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Message-ID: <200605041916.OAA03832@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: ScheduleDAGList.cpp updated: 1.53 -> 1.54 --- Log message: Initial support for register pressure aware scheduling. The register reduction scheduler can go into a "vertical mode" (i.e. traversing up the two-address chain, etc.) when the register pressure is low. This does seem to reduce the number of spills in the cases I've looked at. But with x86, it's no guarantee the performance of the code improves. It can be turned on with -sched-vertically option. --- Diffs of the changes: (+238 -50) ScheduleDAGList.cpp | 288 ++++++++++++++++++++++++++++++++++++++++++---------- 1 files changed, 238 insertions(+), 50 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.53 llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.54 --- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.53 Tue May 2 21:10:45 2006 +++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Thu May 4 14:16:39 2006 @@ -20,6 +20,8 @@ #define DEBUG_TYPE "sched" #include "llvm/CodeGen/ScheduleDAG.h" +#include "llvm/CodeGen/SSARegMap.h" +#include "llvm/Target/MRegisterInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Support/Debug.h" @@ -33,6 +35,11 @@ using namespace llvm; namespace { + cl::opt + SchedVertically("sched-vertically", cl::Hidden); +} + +namespace { Statistic<> NumNoops ("scheduler", "Number of noops inserted"); Statistic<> NumStalls("scheduler", "Number of pipeline stalls"); @@ -63,10 +70,10 @@ SUnit(SDNode *node, unsigned nodenum) : Node(node), NumPredsLeft(0), NumSuccsLeft(0), - NumChainPredsLeft(0), NumChainSuccsLeft(0), - isTwoAddress(false), isDefNUseOperand(false), isPending(false), - isAvailable(false), isScheduled(false), - Latency(0), CycleBound(0), Cycle(0), NodeNum(nodenum) {} + NumChainPredsLeft(0), NumChainSuccsLeft(0), + isTwoAddress(false), isDefNUseOperand(false), + isPending(false), isAvailable(false), isScheduled(false), + Latency(0), CycleBound(0), Cycle(0), NodeNum(nodenum) {} void dump(const SelectionDAG *G) const; void dumpAll(const SelectionDAG *G) const; @@ -141,6 +148,8 @@ virtual void push_all(const std::vector &Nodes) = 0; virtual SUnit *pop() = 0; + + virtual void RemoveFromPriorityQueue(SUnit *SU) = 0; /// ScheduledNode - As each node is scheduled, this method is invoked. This /// allows the priority function to adjust the priority of node that have @@ -160,6 +169,7 @@ private: // SDNode to SUnit mapping (many to one). std::map SUnitMap; + // The schedule. Null SUnit*'s represent noop instructions. std::vector Sequence; @@ -180,10 +190,16 @@ /// added to the AvailableQueue. This keeps track of each SUnit and the /// number of cycles left to execute before the operation is available. std::vector > PendingQueue; - + /// HazardRec - The hazard recognizer to use. HazardRecognizer *HazardRec; - + + /// OpenNodes - Nodes with open live ranges, i.e. predecessors or successors + /// of scheduled nodes which are not themselves scheduled. + std::map > OpenNodes; + + std::map RegPressureLimits; + public: ScheduleDAGList(SelectionDAG &dag, MachineBasicBlock *bb, const TargetMachine &tm, bool isbottomup, @@ -206,7 +222,8 @@ SUnit *NewSUnit(SDNode *N); void ReleasePred(SUnit *PredSU, bool isChain, unsigned CurCycle); void ReleaseSucc(SUnit *SuccSU, bool isChain); - void ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle); + void ScheduleNodeBottomUp(SUnit *SU, unsigned& CurCycle, bool Veritical=true); + void ScheduleVertically(SUnit *SU, unsigned& CurCycle); void ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle); void ListScheduleTopDown(); void ListScheduleBottomUp(); @@ -424,6 +441,41 @@ // Bottom-Up Scheduling //===----------------------------------------------------------------------===// +static const TargetRegisterClass *getRegClass(SUnit *SU, + const TargetInstrInfo *TII, + const MRegisterInfo *MRI, + SSARegMap *RegMap) { + if (SU->Node->isTargetOpcode()) { + unsigned Opc = SU->Node->getTargetOpcode(); + const TargetInstrDescriptor &II = TII->get(Opc); + return II.OpInfo->RegClass; + } else { + assert(SU->Node->getOpcode() == ISD::CopyFromReg); + unsigned SrcReg = cast(SU->Node->getOperand(1))->getReg(); + if (MRegisterInfo::isVirtualRegister(SrcReg)) + return RegMap->getRegClass(SrcReg); + else { + for (MRegisterInfo::regclass_iterator I = MRI->regclass_begin(), + E = MRI->regclass_end(); I != E; ++I) + if ((*I)->hasType(SU->Node->getValueType(0)) && + (*I)->contains(SrcReg)) + return *I; + assert(false && "Couldn't find register class for reg copy!"); + } + return NULL; + } +} + +static unsigned getNumResults(SUnit *SU) { + unsigned NumResults = 0; + for (unsigned i = 0, e = SU->Node->getNumValues(); i != e; ++i) { + MVT::ValueType VT = SU->Node->getValueType(i); + if (VT != MVT::Other && VT != MVT::Flag) + NumResults++; + } + return NumResults; +} + /// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. Add it to /// the Available queue is the count reaches zero. Also update its cycle bound. void ScheduleDAGList::ReleasePred(SUnit *PredSU, bool isChain, @@ -455,11 +507,106 @@ AvailableQueue->push(PredSU); } } + + if (getNumResults(PredSU) > 0) { + const TargetRegisterClass *RegClass = getRegClass(PredSU, TII, MRI, RegMap); + OpenNodes[RegClass].insert(PredSU); + } +} + +/// SharesOperandWithTwoAddr - Check if there is a unscheduled two-address node +/// with which SU shares an operand. If so, returns the node. +static SUnit *SharesOperandWithTwoAddr(SUnit *SU) { + assert(!SU->isTwoAddress && "Node cannot be two-address op"); + for (std::set >::iterator I = SU->Preds.begin(), + E = SU->Preds.end(); I != E; ++I) { + if (I->second) continue; + SUnit *PredSU = I->first; + for (std::set >::iterator II = + PredSU->Succs.begin(), EE = PredSU->Succs.end(); II != EE; ++II) { + if (II->second) continue; + SUnit *SSU = II->first; + if (SSU->isTwoAddress && !SSU->isScheduled) { + return SSU; + } + } + } + return NULL; } + +static bool isFloater(const SUnit *SU) { + unsigned Opc = SU->Node->getOpcode(); + return (Opc != ISD::CopyFromReg && SU->NumPredsLeft == 0); +} + +static bool isSimpleFloaterUse(const SUnit *SU) { + unsigned NumOps = 0; + for (std::set >::iterator I = SU->Preds.begin(), + E = SU->Preds.end(); I != E; ++I) { + if (I->second) continue; + if (++NumOps > 1) + return false; + if (!isFloater(I->first)) + return false; + } + return true; +} + +/// ScheduleVertically - Schedule vertically. That is, follow up the D&U chain +/// (of two-address code) and schedule floaters aggressively. +void ScheduleDAGList::ScheduleVertically(SUnit *SU, unsigned& CurCycle) { + // Try scheduling Def&Use operand if register pressure is low. + const TargetRegisterClass *RegClass = getRegClass(SU, TII, MRI, RegMap); + unsigned Pressure = OpenNodes[RegClass].size(); + unsigned Limit = RegPressureLimits[RegClass]; + + // See if we can schedule any predecessor that takes no registers. + for (std::set >::iterator I = SU->Preds.begin(), + E = SU->Preds.end(); I != E; ++I) { + if (I->second) continue; + + SUnit *PredSU = I->first; + if (!PredSU->isAvailable || PredSU->isScheduled) + continue; + + if (isFloater(PredSU)) { + DEBUG(std::cerr<<"*** Scheduling floater\n"); + AvailableQueue->RemoveFromPriorityQueue(PredSU); + ScheduleNodeBottomUp(PredSU, CurCycle, false); + } + } + + SUnit *DUSU = NULL; + if (SU->isTwoAddress && Pressure < Limit) { + DUSU = SUnitMap[SU->Node->getOperand(0).Val]; + if (!DUSU->isAvailable || DUSU->isScheduled) + DUSU = NULL; + else if (!DUSU->isTwoAddress) { + SUnit *SSU = SharesOperandWithTwoAddr(DUSU); + if (SSU && SSU->isAvailable) { + AvailableQueue->RemoveFromPriorityQueue(SSU); + ScheduleNodeBottomUp(SSU, CurCycle, false); + Pressure = OpenNodes[RegClass].size(); + if (Pressure >= Limit) + DUSU = NULL; + } + } + } + + if (DUSU) { + DEBUG(std::cerr<<"*** Low register pressure: scheduling D&U operand\n"); + AvailableQueue->RemoveFromPriorityQueue(DUSU); + ScheduleNodeBottomUp(DUSU, CurCycle, false); + Pressure = OpenNodes[RegClass].size(); + ScheduleVertically(DUSU, CurCycle); + } +} + /// ScheduleNodeBottomUp - Add the node to the schedule. Decrement the pending /// count of its predecessors. If a predecessor pending count is zero, add it to /// the Available queue. -void ScheduleDAGList::ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle) { +void ScheduleDAGList::ScheduleNodeBottomUp(SUnit *SU, unsigned& CurCycle, + bool Vertical) { DEBUG(std::cerr << "*** Scheduling [" << CurCycle << "]: "); DEBUG(SU->dump(&DAG)); SU->Cycle = CurCycle; @@ -469,48 +616,66 @@ // Bottom up: release predecessors for (std::set >::iterator I = SU->Preds.begin(), - E = SU->Preds.end(); I != E; ++I) { + E = SU->Preds.end(); I != E; ++I) ReleasePred(I->first, I->second, CurCycle); - // FIXME: This is something used by the priority function that it should - // calculate directly. - if (!I->second) - SU->NumPredsLeft--; - else - SU->NumChainPredsLeft--; + SU->isScheduled = true; + CurCycle++; + + if (getNumResults(SU) != 0) { + const TargetRegisterClass *RegClass = getRegClass(SU, TII, MRI, RegMap); + OpenNodes[RegClass].erase(SU); + + if (SchedVertically && Vertical) + ScheduleVertically(SU, CurCycle); } } /// isReady - True if node's lower cycle bound is less or equal to the current /// scheduling cycle. Always true if all nodes have uniform latency 1. -static inline bool isReady(SUnit *SU, unsigned CurrCycle) { - return SU->CycleBound <= CurrCycle; +static inline bool isReady(SUnit *SU, unsigned CurCycle) { + return SU->CycleBound <= CurCycle; } /// ListScheduleBottomUp - The main loop of list scheduling for bottom-up /// schedulers. void ScheduleDAGList::ListScheduleBottomUp() { - unsigned CurrCycle = 0; + // Determine rough register pressure limit. + for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(), + E = MRI->regclass_end(); RCI != E; ++RCI) { + const TargetRegisterClass *RC = *RCI; + unsigned Limit = RC->getNumRegs(); + Limit = (Limit > 2) ? Limit - 2 : 0; + std::map::iterator RPI = + RegPressureLimits.find(RC); + if (RPI == RegPressureLimits.end()) + RegPressureLimits[RC] = Limit; + else { + unsigned &OldLimit = RegPressureLimits[RC]; + if (Limit < OldLimit) + OldLimit = Limit; + } + } + + unsigned CurCycle = 0; // Add root to Available queue. AvailableQueue->push(SUnitMap[DAG.getRoot().Val]); // While Available queue is not empty, grab the node with the highest // priority. If it is not ready put it back. Schedule the node. std::vector NotReady; - SUnit *CurrNode = NULL; + SUnit *CurNode = NULL; while (!AvailableQueue->empty()) { - SUnit *CurrNode = AvailableQueue->pop(); - while (!isReady(CurrNode, CurrCycle)) { - NotReady.push_back(CurrNode); - CurrNode = AvailableQueue->pop(); + SUnit *CurNode = AvailableQueue->pop(); + while (!isReady(CurNode, CurCycle)) { + NotReady.push_back(CurNode); + CurNode = AvailableQueue->pop(); } // Add the nodes that aren't ready back onto the available list. AvailableQueue->push_all(NotReady); NotReady.clear(); - ScheduleNodeBottomUp(CurrNode, CurrCycle); - CurrCycle++; - CurrNode->isScheduled = true; + ScheduleNodeBottomUp(CurNode, CurCycle); } // Add entry node last @@ -574,7 +739,6 @@ } PendingQueue.push_back(std::make_pair(AvailableCycle, SuccSU)); - SuccSU->isPending = true; } } @@ -782,6 +946,27 @@ return V; } + /// RemoveFromPriorityQueue - This is a really inefficient way to remove a + /// node from a priority queue. We should roll our own heap to make this + /// better or something. + void RemoveFromPriorityQueue(SUnit *SU) { + std::vector Temp; + + assert(!Queue.empty() && "Not in queue!"); + while (Queue.top() != SU) { + Temp.push_back(Queue.top()); + Queue.pop(); + assert(!Queue.empty() && "Not in queue!"); + } + + // Remove the node from the PQ. + Queue.pop(); + + // Add all the other nodes back. + for (unsigned i = 0, e = Temp.size(); i != e; ++i) + Queue.push(Temp[i]); + } + private: void CalculatePriorities(); int CalcNodePriority(const SUnit *SU); @@ -797,13 +982,16 @@ int RPriority = SPQ->getSethiUllmanNumber(RightNum); bool LIsFloater = LIsTarget && (LPriority == 1 || LPriority == 0); bool RIsFloater = RIsTarget && (RPriority == 1 || RPriority == 0); + int LBonus = 0; + int RBonus = 0; - // Schedule floaters (e.g. load from some constant address) and immediate use - // of floaters (with no other operands) just before the use. - if (LIsFloater && !RIsFloater) - LPriority += 2; - else if (!LIsFloater && RIsFloater) - RPriority += 2; + // Schedule floaters (e.g. load from some constant address) and those nodes + // with a single predecessor each first. They maintain / reduce register + // pressure. + if (LIsFloater) + LBonus += 2; + if (RIsFloater) + RBonus += 2; // Special tie breaker: if two nodes share a operand, the one that use it // as a def&use operand is preferred. @@ -811,21 +999,21 @@ if (left->isTwoAddress && !right->isTwoAddress) { SDNode *DUNode = left->Node->getOperand(0).Val; if (DUNode->isOperand(right->Node)) - LPriority += 2; + LBonus += 2; } if (!left->isTwoAddress && right->isTwoAddress) { SDNode *DUNode = right->Node->getOperand(0).Val; if (DUNode->isOperand(left->Node)) - RPriority += 2; + RBonus += 2; } } - if (LPriority < RPriority) + if (LPriority+LBonus < RPriority+RBonus) return true; - else if (LPriority == RPriority) + else if (LPriority+LBonus == RPriority+RBonus) if (left->NumPredsLeft > right->NumPredsLeft) return true; - else if (left->NumPredsLeft == right->NumPredsLeft) + else if (left->NumPredsLeft+LBonus == right->NumPredsLeft+RBonus) if (left->CycleBound > right->CycleBound) return true; return false; @@ -955,18 +1143,7 @@ Queue.pop(); return V; } - - // ScheduledNode - As nodes are scheduled, we look to see if there are any - // successor nodes that have a single unscheduled predecessor. If so, that - // single predecessor has a higher priority, since scheduling it will make - // the node available. - void ScheduledNode(SUnit *Node); - -private: - void CalculatePriorities(); - int CalcLatency(const SUnit &SU); - void AdjustPriorityOfUnscheduledPreds(SUnit *SU); - + /// RemoveFromPriorityQueue - This is a really inefficient way to remove a /// node from a priority queue. We should roll our own heap to make this /// better or something. @@ -987,6 +1164,17 @@ for (unsigned i = 0, e = Temp.size(); i != e; ++i) Queue.push(Temp[i]); } + + // ScheduledNode - As nodes are scheduled, we look to see if there are any + // successor nodes that have a single unscheduled predecessor. If so, that + // single predecessor has a higher priority, since scheduling it will make + // the node available. + void ScheduledNode(SUnit *Node); + +private: + void CalculatePriorities(); + int CalcLatency(const SUnit &SU); + void AdjustPriorityOfUnscheduledPreds(SUnit *SU); }; } From evan.cheng at apple.com Thu May 4 14:19:05 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 4 May 2006 14:19:05 -0500 Subject: [llvm-commits] CVS: llvm-test/Makefile.programs Message-ID: <200605041919.OAA03854@zion.cs.uiuc.edu> Changes in directory llvm-test: Makefile.programs updated: 1.209 -> 1.210 --- Log message: Set -sched-vertically for x86 llcbeta --- Diffs of the changes: (+1 -1) Makefile.programs | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm-test/Makefile.programs diff -u llvm-test/Makefile.programs:1.209 llvm-test/Makefile.programs:1.210 --- llvm-test/Makefile.programs:1.209 Tue May 2 21:17:13 2006 +++ llvm-test/Makefile.programs Thu May 4 14:18:53 2006 @@ -197,7 +197,7 @@ LLCBETAOPTION := -sched=simple endif ifeq ($(ARCH),x86) -LLCBETAOPTION := -enable-x86-fastcc +LLCBETAOPTION := -sched-vertically endif ifeq ($(ARCH),Sparc) LLCBETAOPTION := -enable-sparc-v9-insts From lattner at cs.uiuc.edu Thu May 4 14:36:23 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 4 May 2006 14:36:23 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/MachineInstr.cpp Message-ID: <200605041936.OAA03971@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: MachineInstr.cpp updated: 1.121 -> 1.122 --- Log message: Final pass of minor cleanups for MachineInstr --- Diffs of the changes: (+0 -4) MachineInstr.cpp | 4 ---- 1 files changed, 4 deletions(-) Index: llvm/lib/CodeGen/MachineInstr.cpp diff -u llvm/lib/CodeGen/MachineInstr.cpp:1.121 llvm/lib/CodeGen/MachineInstr.cpp:1.122 --- llvm/lib/CodeGen/MachineInstr.cpp:1.121 Thu May 4 14:14:44 2006 +++ llvm/lib/CodeGen/MachineInstr.cpp Thu May 4 14:36:09 2006 @@ -9,14 +9,10 @@ // // Methods common to all machine instructions. // -// FIXME: Now that MachineInstrs have parent pointers, they should always -// print themselves using their MachineFunction's TargetMachine. -// //===----------------------------------------------------------------------===// #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/Value.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/MRegisterInfo.h" From lattner at cs.uiuc.edu Thu May 4 14:36:23 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 4 May 2006 14:36:23 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineInstr.h Message-ID: <200605041936.OAA03967@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineInstr.h updated: 1.180 -> 1.181 --- Log message: Final pass of minor cleanups for MachineInstr --- Diffs of the changes: (+5 -5) MachineInstr.h | 10 +++++----- 1 files changed, 5 insertions(+), 5 deletions(-) Index: llvm/include/llvm/CodeGen/MachineInstr.h diff -u llvm/include/llvm/CodeGen/MachineInstr.h:1.180 llvm/include/llvm/CodeGen/MachineInstr.h:1.181 --- llvm/include/llvm/CodeGen/MachineInstr.h:1.180 Thu May 4 14:14:44 2006 +++ llvm/include/llvm/CodeGen/MachineInstr.h Thu May 4 14:36:09 2006 @@ -71,11 +71,11 @@ private: union { - GlobalValue *GV; // LLVM global for MO_GlobalAddress. - int64_t immedVal; // Constant value for an explicit constant - MachineBasicBlock *MBB; // For MO_MachineBasicBlock type - const char *SymbolName; // For MO_ExternalSymbol type - unsigned RegNo; // For MO_Register number for an explicit register + GlobalValue *GV; // For MO_GlobalAddress. + MachineBasicBlock *MBB; // For MO_MachineBasicBlock. + const char *SymbolName; // For MO_ExternalSymbol. + unsigned RegNo; // For MO_Register. + int64_t immedVal; // For MO_Immediate and MO_*Index. } contents; char flags; // see bit field definitions above From lattner at cs.uiuc.edu Thu May 4 16:17:47 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 4 May 2006 16:17:47 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetData.h Message-ID: <200605042117.QAA04577@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/Target: TargetData.h updated: 1.34 -> 1.35 --- Log message: Fix this to be a proper copy ctor --- Diffs of the changes: (+11 -11) TargetData.h | 22 +++++++++++----------- 1 files changed, 11 insertions(+), 11 deletions(-) Index: llvm/include/llvm/Target/TargetData.h diff -u llvm/include/llvm/Target/TargetData.h:1.34 llvm/include/llvm/Target/TargetData.h:1.35 --- llvm/include/llvm/Target/TargetData.h:1.34 Tue May 2 20:29:56 2006 +++ llvm/include/llvm/Target/TargetData.h Thu May 4 16:17:35 2006 @@ -54,18 +54,18 @@ unsigned char ByteAl = 1, unsigned char BoolAl = 1); // Copy constructor - TargetData (const TargetData *TD) : + TargetData (const TargetData &TD) : ImmutablePass(), - LittleEndian(TD->isLittleEndian()), - BoolAlignment(TD->getBoolAlignment()), - ByteAlignment(TD->getByteAlignment()), - ShortAlignment(TD->getShortAlignment()), - IntAlignment(TD->getIntAlignment()), - LongAlignment(TD->getLongAlignment()), - FloatAlignment(TD->getFloatAlignment()), - DoubleAlignment(TD->getDoubleAlignment()), - PointerSize(TD->getPointerSize()), - PointerAlignment(TD->getPointerAlignment()) { + LittleEndian(TD.isLittleEndian()), + BoolAlignment(TD.getBoolAlignment()), + ByteAlignment(TD.getByteAlignment()), + ShortAlignment(TD.getShortAlignment()), + IntAlignment(TD.getIntAlignment()), + LongAlignment(TD.getLongAlignment()), + FloatAlignment(TD.getFloatAlignment()), + DoubleAlignment(TD.getDoubleAlignment()), + PointerSize(TD.getPointerSize()), + PointerAlignment(TD.getPointerAlignment()) { } TargetData(const std::string &ToolName, const Module *M); From lattner at cs.uiuc.edu Thu May 4 16:18:53 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 4 May 2006 16:18:53 -0500 Subject: [llvm-commits] CVS: llvm/tools/llc/llc.cpp Message-ID: <200605042118.QAA04671@zion.cs.uiuc.edu> Changes in directory llvm/tools/llc: llc.cpp updated: 1.131 -> 1.132 --- Log message: Adjust to use proper TargetData copy ctor --- Diffs of the changes: (+1 -2) llc.cpp | 3 +-- 1 files changed, 1 insertion(+), 2 deletions(-) Index: llvm/tools/llc/llc.cpp diff -u llvm/tools/llc/llc.cpp:1.131 llvm/tools/llc/llc.cpp:1.132 --- llvm/tools/llc/llc.cpp:1.131 Tue May 2 20:29:57 2006 +++ llvm/tools/llc/llc.cpp Thu May 4 16:18:40 2006 @@ -143,11 +143,10 @@ std::auto_ptr target(MArch->CtorFn(mod, FeaturesStr)); assert(target.get() && "Could not allocate target machine!"); TargetMachine &Target = *target.get(); - const TargetData *TD = Target.getTargetData(); // Build up all of the passes that we want to do to the module... PassManager Passes; - Passes.add(new TargetData(TD)); + Passes.add(new TargetData(*Target.getTargetData())); #ifndef NDEBUG if(!NoVerify) From lattner at cs.uiuc.edu Thu May 4 16:18:53 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 4 May 2006 16:18:53 -0500 Subject: [llvm-commits] CVS: llvm/lib/ExecutionEngine/JIT/JIT.cpp Message-ID: <200605042118.QAA04675@zion.cs.uiuc.edu> Changes in directory llvm/lib/ExecutionEngine/JIT: JIT.cpp updated: 1.63 -> 1.64 --- Log message: Adjust to use proper TargetData copy ctor --- Diffs of the changes: (+1 -1) JIT.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/ExecutionEngine/JIT/JIT.cpp diff -u llvm/lib/ExecutionEngine/JIT/JIT.cpp:1.63 llvm/lib/ExecutionEngine/JIT/JIT.cpp:1.64 --- llvm/lib/ExecutionEngine/JIT/JIT.cpp:1.63 Tue May 2 20:29:56 2006 +++ llvm/lib/ExecutionEngine/JIT/JIT.cpp Thu May 4 16:18:40 2006 @@ -47,7 +47,7 @@ // Add target data MutexGuard locked(lock); FunctionPassManager& PM = state.getPM(locked); - PM.add(new TargetData(TM.getTargetData())); + PM.add(new TargetData(*TM.getTargetData())); // Compile LLVM Code down to machine code in the intermediate representation TJI.addPassesToJITCompile(PM); From lattner at cs.uiuc.edu Thu May 4 18:35:44 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 4 May 2006 18:35:44 -0500 Subject: [llvm-commits] CVS: llvm/tools/bugpoint/Miscompilation.cpp Message-ID: <200605042335.SAA21128@zion.cs.uiuc.edu> Changes in directory llvm/tools/bugpoint: Miscompilation.cpp updated: 1.74 -> 1.75 --- Log message: wrap long line --- Diffs of the changes: (+2 -1) Miscompilation.cpp | 3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index: llvm/tools/bugpoint/Miscompilation.cpp diff -u llvm/tools/bugpoint/Miscompilation.cpp:1.74 llvm/tools/bugpoint/Miscompilation.cpp:1.75 --- llvm/tools/bugpoint/Miscompilation.cpp:1.74 Wed Dec 14 16:01:07 2005 +++ llvm/tools/bugpoint/Miscompilation.cpp Thu May 4 18:35:31 2006 @@ -234,7 +234,8 @@ Mangler Mang(*M); // Agree with the CBE on symbol naming Mang.markCharUnacceptable('.'); - for (Module::global_iterator I = M->global_begin(), E = M->global_end(); I != E; ++I) + for (Module::global_iterator I = M->global_begin(), E = M->global_end(); + I != E; ++I) I->setName(Mang.getValueName(I)); for (Module::iterator I = M->begin(), E = M->end(); I != E; ++I) I->setName(Mang.getValueName(I)); From lattner at cs.uiuc.edu Thu May 4 19:51:54 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 4 May 2006 19:51:54 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Use.h Message-ID: <200605050051.TAA10039@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm: Use.h updated: 1.13 -> 1.14 --- Log message: Add a helper method. --- Diffs of the changes: (+6 -0) Use.h | 6 ++++++ 1 files changed, 6 insertions(+) Index: llvm/include/llvm/Use.h diff -u llvm/include/llvm/Use.h:1.13 llvm/include/llvm/Use.h:1.14 --- llvm/include/llvm/Use.h:1.13 Mon Mar 27 16:49:07 2006 +++ llvm/include/llvm/Use.h Thu May 4 19:51:42 2006 @@ -140,6 +140,12 @@ UserTy *operator->() const { return operator*(); } Use &getUse() const { return *U; } + + /// getOperandNo - Return the operand # of this use in its User. + /// + unsigned getOperandNo() const { + return U - U->getUser()->op_begin(); + } }; From lattner at cs.uiuc.edu Thu May 4 20:05:02 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 4 May 2006 20:05:02 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Message-ID: <200605050105.UAA10166@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAGISel.cpp updated: 1.233 -> 1.234 --- Log message: Sink noop copies into the basic block that uses them. This reduces the number of cross-block live ranges, and allows the bb-at-a-time selector to always coallesce these away, at isel time. This reduces the load on the coallescer and register allocator. For example on a codec on X86, we went from: 1643 asm-printer - Number of machine instrs printed 419 liveintervals - Number of loads/stores folded into instructions 1144 liveintervals - Number of identity moves eliminated after coalescing 1022 liveintervals - Number of interval joins performed 282 liveintervals - Number of intervals after coalescing 1304 liveintervals - Number of original intervals 86 regalloc - Number of times we had to backtrack 1.90232 regalloc - Ratio of intervals processed over total intervals 40 spiller - Number of values reused 182 spiller - Number of loads added 121 spiller - Number of stores added 132 spiller - Number of register spills 6 twoaddressinstruction - Number of instructions commuted to coalesce 360 twoaddressinstruction - Number of two-address instructions to: 1636 asm-printer - Number of machine instrs printed 403 liveintervals - Number of loads/stores folded into instructions 1155 liveintervals - Number of identity moves eliminated after coalescing 1033 liveintervals - Number of interval joins performed 279 liveintervals - Number of intervals after coalescing 1312 liveintervals - Number of original intervals 76 regalloc - Number of times we had to backtrack 1.88998 regalloc - Ratio of intervals processed over total intervals 1 spiller - Number of copies elided 41 spiller - Number of values reused 191 spiller - Number of loads added 114 spiller - Number of stores added 128 spiller - Number of register spills 4 twoaddressinstruction - Number of instructions commuted to coalesce 356 twoaddressinstruction - Number of two-address instructions On this testcase, this change provides a modest reduction in spill code, regalloc iterations, and total instructions emitted. It increases the number of register coallesces. --- Diffs of the changes: (+77 -4) SelectionDAGISel.cpp | 81 ++++++++++++++++++++++++++++++++++++++++++++++++--- 1 files changed, 77 insertions(+), 4 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.233 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.234 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.233 Tue May 2 22:48:02 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu May 4 20:04:50 2006 @@ -2763,6 +2763,49 @@ return V = Ptr; } +/// OptimizeNoopCopyExpression - We have determined that the specified cast +/// instruction is a noop copy (e.g. it's casting from one pointer type to +/// another, int->uint, or int->sbyte on PPC. +static void OptimizeNoopCopyExpression(CastInst *CI) { + BasicBlock *DefBB = CI->getParent(); + + /// InsertedCasts - Only insert a cast in each block once. + std::map InsertedCasts; + + for (Value::use_iterator UI = CI->use_begin(), E = CI->use_end(); + UI != E; ) { + Use &TheUse = UI.getUse(); + Instruction *User = cast(*UI); + + // Figure out which BB this cast is used in. For PHI's this is the + // appropriate predecessor block. + BasicBlock *UserBB = User->getParent(); + if (PHINode *PN = dyn_cast(User)) { + unsigned OpVal = UI.getOperandNo()/2; + UserBB = PN->getIncomingBlock(OpVal); + } + + // Preincrement use iterator so we don't invalidate it. + ++UI; + + // If this user is in the same block as the cast, don't change the cast. + if (UserBB == DefBB) continue; + + // If we have already inserted a cast into this block, use it. + CastInst *&InsertedCast = InsertedCasts[UserBB]; + + if (!InsertedCast) { + BasicBlock::iterator InsertPt = UserBB->begin(); + while (isa(InsertPt)) ++InsertPt; + + InsertedCast = + new CastInst(CI->getOperand(0), CI->getType(), "", InsertPt); + } + + // Replace a use of the cast with a use of the new casat. + TheUse = InsertedCast; + } +} /// OptimizeGEPExpression - Since we are doing basic-block-at-a-time instruction /// selection, we want to be a bit careful about some things. In particular, if @@ -2890,8 +2933,10 @@ // constants, this way the load of the constant into a vreg will not be placed // into MBBs that are used some other way. // - // In this pass we also look for GEP instructions that are used across basic - // blocks and rewrites them to improve basic-block-at-a-time selection. + // In this pass we also look for GEP and cast instructions that are used + // across basic blocks and rewrite them to improve basic-block-at-a-time + // selection. + // // for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { PHINode *PN; @@ -2901,9 +2946,37 @@ if (isa(PN->getIncomingValue(i))) SplitCriticalEdge(PN->getIncomingBlock(i), BB); - for (BasicBlock::iterator E = BB->end(); BBI != E; ) - if (GetElementPtrInst *GEPI = dyn_cast(BBI++)) + for (BasicBlock::iterator E = BB->end(); BBI != E; ) { + Instruction *I = BBI++; + if (GetElementPtrInst *GEPI = dyn_cast(I)) { OptimizeGEPExpression(GEPI, TLI.getTargetData()); + } else if (CastInst *CI = dyn_cast(I)) { + // If this is a noop copy, sink it into user blocks to reduce the number + // of virtual registers that must be created and coallesced. + MVT::ValueType SrcVT = TLI.getValueType(CI->getOperand(0)->getType()); + MVT::ValueType DstVT = TLI.getValueType(CI->getType()); + + // This is an fp<->int conversion? + if (MVT::isInteger(SrcVT) != MVT::isInteger(DstVT)) + continue; + + // If this is an extension, it will be a zero or sign extension, which + // isn't a noop. + if (SrcVT < DstVT) continue; + + // If these values will be promoted, find out what they will be promoted + // to. This helps us consider truncates on PPC as noop copies when they + // are. + if (TLI.getTypeAction(SrcVT) == TargetLowering::Promote) + SrcVT = TLI.getTypeToTransformTo(SrcVT); + if (TLI.getTypeAction(DstVT) == TargetLowering::Promote) + DstVT = TLI.getTypeToTransformTo(DstVT); + + // If, after promotion, these are the same types, this is a noop copy. + if (SrcVT == DstVT) + OptimizeNoopCopyExpression(CI); + } + } } FunctionLoweringInfo FuncInfo(TLI, Fn, MF); From natebegeman at mac.com Thu May 4 20:13:24 2006 From: natebegeman at mac.com (Nate Begeman) Date: Thu, 4 May 2006 20:13:24 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGISel.h Message-ID: <200605050113.UAA10208@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: SelectionDAGISel.h updated: 1.16 -> 1.17 --- Log message: Somehow, I missed this part of the checkin a couple days ago --- Diffs of the changes: (+0 -3) SelectionDAGISel.h | 3 --- 1 files changed, 3 deletions(-) Index: llvm/include/llvm/CodeGen/SelectionDAGISel.h diff -u llvm/include/llvm/CodeGen/SelectionDAGISel.h:1.16 llvm/include/llvm/CodeGen/SelectionDAGISel.h:1.17 --- llvm/include/llvm/CodeGen/SelectionDAGISel.h:1.16 Fri Apr 28 13:54:11 2006 +++ llvm/include/llvm/CodeGen/SelectionDAGISel.h Thu May 4 20:13:11 2006 @@ -101,9 +101,6 @@ // Default - the MBB of the default bb, which is a successor of the range // check MBB. This is when updating PHI nodes in successors. MachineBasicBlock *Default; - // SuccMBBs - a vector of unique successor MBBs used for updating CFG info - // and PHI nodes. - std::set SuccMBBs; }; protected: From jeffc at jolt-lang.org Thu May 4 20:47:17 2006 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Thu, 4 May 2006 20:47:17 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Message-ID: <200605050147.UAA10501@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: ScheduleDAGList.cpp updated: 1.54 -> 1.55 --- Log message: Fix VC++ compilation error. --- Diffs of the changes: (+1 -1) ScheduleDAGList.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.54 llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.55 --- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.54 Thu May 4 14:16:39 2006 +++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Thu May 4 20:47:05 2006 @@ -541,7 +541,7 @@ static bool isSimpleFloaterUse(const SUnit *SU) { unsigned NumOps = 0; - for (std::set >::iterator I = SU->Preds.begin(), + for (std::set >::const_iterator I = SU->Preds.begin(), E = SU->Preds.end(); I != E; ++I) { if (I->second) continue; if (++NumOps > 1) From lattner at cs.uiuc.edu Fri May 5 00:36:27 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 5 May 2006 00:36:27 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/README.txt Message-ID: <200605050536.AAA24083@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: README.txt updated: 1.85 -> 1.86 --- Log message: New note, Nate, please check to see if I'm full of it :) --- Diffs of the changes: (+33 -0) README.txt | 33 +++++++++++++++++++++++++++++++++ 1 files changed, 33 insertions(+) Index: llvm/lib/Target/PowerPC/README.txt diff -u llvm/lib/Target/PowerPC/README.txt:1.85 llvm/lib/Target/PowerPC/README.txt:1.86 --- llvm/lib/Target/PowerPC/README.txt:1.85 Thu Apr 13 11:48:00 2006 +++ llvm/lib/Target/PowerPC/README.txt Fri May 5 00:36:15 2006 @@ -559,3 +559,36 @@ // need to flag these together so that the value isn't live across a call. //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); +===-------------------------------------------------------------------------=== + +Another missed rlwimi case: + +void %foo(uint *%tmp) { + %tmp = load uint* %tmp ; [#uses=3] + %tmp1 = shr uint %tmp, ubyte 31 ; [#uses=1] + %tmp1 = cast uint %tmp1 to ubyte ; [#uses=1] + %tmp4.mask = shr uint %tmp, ubyte 30 ; [#uses=1] + %tmp4.mask = cast uint %tmp4.mask to ubyte ; [#uses=1] + %tmp = or ubyte %tmp4.mask, %tmp1 ; [#uses=1] + %tmp10 = cast ubyte %tmp to uint ; [#uses=1] + %tmp11 = shl uint %tmp10, ubyte 31 ; [#uses=1] + %tmp12 = and uint %tmp, 2147483647 ; [#uses=1] + %tmp13 = or uint %tmp11, %tmp12 ; [#uses=1] + store uint %tmp13, uint* %tmp + ret void +} + +We emit: + +_foo: + lwz r2, 0(r3) + srwi r4, r2, 30 + srwi r5, r2, 31 + or r4, r4, r5 + slwi r4, r4, 31 + rlwimi r4, r2, 0, 1, 31 + stw r4, 0(r3) + blr + +I *think* that could use another rlwimi. + From evan.cheng at apple.com Fri May 5 00:40:32 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 5 May 2006 00:40:32 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp X86ISelDAGToDAG.cpp X86InstrInfo.td X86IntelAsmPrinter.cpp X86RegisterInfo.cpp X86RegisterInfo.h Message-ID: <200605050540.AAA24160@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ATTAsmPrinter.cpp updated: 1.42 -> 1.43 X86ISelDAGToDAG.cpp updated: 1.57 -> 1.58 X86InstrInfo.td updated: 1.263 -> 1.264 X86IntelAsmPrinter.cpp updated: 1.41 -> 1.42 X86RegisterInfo.cpp updated: 1.149 -> 1.150 X86RegisterInfo.h updated: 1.37 -> 1.38 --- Log message: Better implementation of truncate. ISel matches it to a pseudo instruction that gets emitted as movl (for r32 to i16, i8) or a movw (for r16 to i8). And if the destination gets allocated a subregister of the source operand, then the instruction will not be emitted at all. --- Diffs of the changes: (+162 -240) X86ATTAsmPrinter.cpp | 136 ++++++++++++------------------------------------- X86ISelDAGToDAG.cpp | 39 -------------- X86InstrInfo.td | 11 +++ X86IntelAsmPrinter.cpp | 135 ++++++++++++------------------------------------ X86RegisterInfo.cpp | 76 +++++++++++++++++++++++++++ X86RegisterInfo.h | 5 + 6 files changed, 162 insertions(+), 240 deletions(-) Index: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp diff -u llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.42 llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.43 --- llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.42 Thu May 4 13:05:43 2006 +++ llvm/lib/Target/X86/X86ATTAsmPrinter.cpp Fri May 5 00:40:20 2006 @@ -108,13 +108,20 @@ const MachineOperand &MO = MI->getOperand(OpNo); const MRegisterInfo &RI = *TM.getRegisterInfo(); switch (MO.getType()) { - case MachineOperand::MO_Register: + case MachineOperand::MO_Register: { assert(MRegisterInfo::isPhysicalRegister(MO.getReg()) && "Virtual registers should not make it this far!"); O << '%'; - for (const char *Name = RI.get(MO.getReg()).Name; *Name; ++Name) + unsigned Reg = MO.getReg(); + if (Modifier && strncmp(Modifier, "trunc", strlen("trunc")) == 0) { + MVT::ValueType VT = (strcmp(Modifier,"trunc16") == 0) + ? MVT::i16 : MVT::i32; + Reg = getX86SubSuperRegister(Reg, VT); + } + for (const char *Name = RI.get(Reg).Name; *Name; ++Name) O << (char)tolower(*Name); return; + } case MachineOperand::MO_Immediate: if (!Modifier || strcmp(Modifier, "debug") != 0) @@ -263,116 +270,25 @@ const char Mode) { const MRegisterInfo &RI = *TM.getRegisterInfo(); unsigned Reg = MO.getReg(); - const char *Name = RI.get(Reg).Name; switch (Mode) { default: return true; // Unknown mode. case 'b': // Print QImode register - switch (Reg) { - default: return true; - case X86::AH: case X86::AL: case X86::AX: case X86::EAX: - Name = "al"; - break; - case X86::DH: case X86::DL: case X86::DX: case X86::EDX: - Name = "dl"; - break; - case X86::CH: case X86::CL: case X86::CX: case X86::ECX: - Name = "cl"; - break; - case X86::BH: case X86::BL: case X86::BX: case X86::EBX: - Name = "bl"; - break; - case X86::ESI: - Name = "sil"; - break; - case X86::EDI: - Name = "dil"; - break; - case X86::EBP: - Name = "bpl"; - break; - case X86::ESP: - Name = "spl"; - break; - } + Reg = getX86SubSuperRegister(Reg, MVT::i8); break; case 'h': // Print QImode high register - switch (Reg) { - default: return true; - case X86::AH: case X86::AL: case X86::AX: case X86::EAX: - Name = "al"; - break; - case X86::DH: case X86::DL: case X86::DX: case X86::EDX: - Name = "dl"; - break; - case X86::CH: case X86::CL: case X86::CX: case X86::ECX: - Name = "cl"; - break; - case X86::BH: case X86::BL: case X86::BX: case X86::EBX: - Name = "bl"; - break; - } + Reg = getX86SubSuperRegister(Reg, MVT::i8, true); break; case 'w': // Print HImode register - switch (Reg) { - default: return true; - case X86::AH: case X86::AL: case X86::AX: case X86::EAX: - Name = "ax"; - break; - case X86::DH: case X86::DL: case X86::DX: case X86::EDX: - Name = "dx"; - break; - case X86::CH: case X86::CL: case X86::CX: case X86::ECX: - Name = "cx"; - break; - case X86::BH: case X86::BL: case X86::BX: case X86::EBX: - Name = "bx"; - break; - case X86::ESI: - Name = "si"; - break; - case X86::EDI: - Name = "di"; - break; - case X86::EBP: - Name = "bp"; - break; - case X86::ESP: - Name = "sp"; - break; - } + Reg = getX86SubSuperRegister(Reg, MVT::i16); break; case 'k': // Print SImode register - switch (Reg) { - default: return true; - case X86::AH: case X86::AL: case X86::AX: case X86::EAX: - Name = "eax"; - break; - case X86::DH: case X86::DL: case X86::DX: case X86::EDX: - Name = "edx"; - break; - case X86::CH: case X86::CL: case X86::CX: case X86::ECX: - Name = "ecx"; - break; - case X86::BH: case X86::BL: case X86::BX: case X86::EBX: - Name = "ebx"; - break; - case X86::ESI: - Name = "esi"; - break; - case X86::EDI: - Name = "edi"; - break; - case X86::EBP: - Name = "ebp"; - break; - case X86::ESP: - Name = "esp"; - break; - } + Reg = getX86SubSuperRegister(Reg, MVT::i32); break; } - O << '%' << Name; + O << '%'; + for (const char *Name = RI.get(Reg).Name; *Name; ++Name) + O << (char)tolower(*Name); return false; } @@ -440,6 +356,26 @@ } } + // See if a truncate instruction can be turned into a nop. + switch (MI->getOpcode()) { + default: break; + case X86::TRUNC_R32_R16: + case X86::TRUNC_R32_R8: + case X86::TRUNC_R16_R8: { + const MachineOperand &MO0 = MI->getOperand(0); + const MachineOperand &MO1 = MI->getOperand(1); + unsigned Reg0 = MO0.getReg(); + unsigned Reg1 = MO1.getReg(); + if (MI->getOpcode() == X86::TRUNC_R16_R8) + Reg0 = getX86SubSuperRegister(Reg0, MVT::i16); + else + Reg0 = getX86SubSuperRegister(Reg0, MVT::i32); + if (Reg0 == Reg1) + O << CommentString << " TRUNCATE "; + break; + } + } + // Call the autogenerated instruction printer routines. printInstruction(MI); } Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.57 llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.58 --- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.57 Sat Mar 25 00:47:10 2006 +++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Fri May 5 00:40:20 2006 @@ -791,45 +791,6 @@ #endif return; } - - case ISD::TRUNCATE: { - unsigned Reg; - MVT::ValueType VT; - switch (Node->getOperand(0).getValueType()) { - default: assert(0 && "Unknown truncate!"); - case MVT::i16: Reg = X86::AX; Opc = X86::MOV16rr; VT = MVT::i16; break; - case MVT::i32: Reg = X86::EAX; Opc = X86::MOV32rr; VT = MVT::i32; break; - } - SDOperand Tmp0, Tmp1; - Select(Tmp0, Node->getOperand(0)); - Select(Tmp1, SDOperand(CurDAG->getTargetNode(Opc, VT, Tmp0), 0)); - SDOperand InFlag = SDOperand(0,0); - Result = CurDAG->getCopyToReg(CurDAG->getEntryNode(), Reg, Tmp1, InFlag); - SDOperand Chain = Result.getValue(0); - InFlag = Result.getValue(1); - - switch (NVT) { - default: assert(0 && "Unknown truncate!"); - case MVT::i8: Reg = X86::AL; Opc = X86::MOV8rr; VT = MVT::i8; break; - case MVT::i16: Reg = X86::AX; Opc = X86::MOV16rr; VT = MVT::i16; break; - } - - Result = CurDAG->getCopyFromReg(Chain, Reg, VT, InFlag); - if (N.Val->hasOneUse()) - Result = CurDAG->SelectNodeTo(N.Val, Opc, VT, Result); - else - Result = CodeGenMap[N] = - SDOperand(CurDAG->getTargetNode(Opc, VT, Result), 0); - -#ifndef NDEBUG - DEBUG(std::cerr << std::string(Indent-2, ' ')); - DEBUG(std::cerr << "== "); - DEBUG(Result.Val->dump(CurDAG)); - DEBUG(std::cerr << "\n"); - Indent -= 2; -#endif - return; - } } SelectCode(Result, N); Index: llvm/lib/Target/X86/X86InstrInfo.td diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.263 llvm/lib/Target/X86/X86InstrInfo.td:1.264 --- llvm/lib/Target/X86/X86InstrInfo.td:1.263 Thu Apr 27 03:40:39 2006 +++ llvm/lib/Target/X86/X86InstrInfo.td Fri May 5 00:40:20 2006 @@ -351,6 +351,17 @@ // Nop def NOOP : I<0x90, RawFrm, (ops), "nop", []>; +// Truncate +def TRUNC_R32_R8 : I<0x89, MRMDestReg, (ops R8:$dst, R32:$src), + "mov{l} {$src, ${dst:trunc32}|${dst:trunc32}, $src}", + [(set R8:$dst, (trunc R32:$src))]>; +def TRUNC_R32_R16 : I<0x89, MRMDestReg, (ops R16:$dst, R32:$src), + "mov{l} {$src, ${dst:trunc32}|${dst:trunc32}, $src}", + [(set R16:$dst, (trunc R32:$src))]>; +def TRUNC_R16_R8 : I<0x89, MRMDestReg, (ops R8:$dst, R16:$src), + "mov{w} {$src, ${dst:trunc16}|${dst:trunc16}, $src}", + [(set R8:$dst, (trunc R16:$src))]>; + //===----------------------------------------------------------------------===// // Control Flow Instructions... // Index: llvm/lib/Target/X86/X86IntelAsmPrinter.cpp diff -u llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.41 llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.42 --- llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.41 Thu May 4 13:05:43 2006 +++ llvm/lib/Target/X86/X86IntelAsmPrinter.cpp Fri May 5 00:40:20 2006 @@ -101,9 +101,15 @@ const MRegisterInfo &RI = *TM.getRegisterInfo(); switch (MO.getType()) { case MachineOperand::MO_Register: - if (MRegisterInfo::isPhysicalRegister(MO.getReg())) - O << RI.get(MO.getReg()).Name; - else + if (MRegisterInfo::isPhysicalRegister(MO.getReg())) { + unsigned Reg = MO.getReg(); + if (Modifier && strncmp(Modifier, "trunc", strlen("trunc")) == 0) { + MVT::ValueType VT = (strcmp(Modifier,"trunc16") == 0) + ? MVT::i16 : MVT::i32; + Reg = getX86SubSuperRegister(Reg, VT); + } + O << RI.get(Reg).Name; + } else O << "reg" << MO.getReg(); return; @@ -240,116 +246,23 @@ const char Mode) { const MRegisterInfo &RI = *TM.getRegisterInfo(); unsigned Reg = MO.getReg(); - const char *Name = RI.get(Reg).Name; switch (Mode) { default: return true; // Unknown mode. case 'b': // Print QImode register - switch (Reg) { - default: return true; - case X86::AH: case X86::AL: case X86::AX: case X86::EAX: - Name = "AL"; - break; - case X86::DH: case X86::DL: case X86::DX: case X86::EDX: - Name = "DL"; - break; - case X86::CH: case X86::CL: case X86::CX: case X86::ECX: - Name = "CL"; - break; - case X86::BH: case X86::BL: case X86::BX: case X86::EBX: - Name = "BL"; - break; - case X86::ESI: - Name = "SIL"; - break; - case X86::EDI: - Name = "DIL"; - break; - case X86::EBP: - Name = "BPL"; - break; - case X86::ESP: - Name = "SPL"; - break; - } + Reg = getX86SubSuperRegister(Reg, MVT::i8); break; case 'h': // Print QImode high register - switch (Reg) { - default: return true; - case X86::AH: case X86::AL: case X86::AX: case X86::EAX: - Name = "AL"; - break; - case X86::DH: case X86::DL: case X86::DX: case X86::EDX: - Name = "DL"; - break; - case X86::CH: case X86::CL: case X86::CX: case X86::ECX: - Name = "CL"; - break; - case X86::BH: case X86::BL: case X86::BX: case X86::EBX: - Name = "BL"; - break; - } + Reg = getX86SubSuperRegister(Reg, MVT::i8, true); break; case 'w': // Print HImode register - switch (Reg) { - default: return true; - case X86::AH: case X86::AL: case X86::AX: case X86::EAX: - Name = "AX"; - break; - case X86::DH: case X86::DL: case X86::DX: case X86::EDX: - Name = "DX"; - break; - case X86::CH: case X86::CL: case X86::CX: case X86::ECX: - Name = "CX"; - break; - case X86::BH: case X86::BL: case X86::BX: case X86::EBX: - Name = "BX"; - break; - case X86::ESI: - Name = "SI"; - break; - case X86::EDI: - Name = "DI"; - break; - case X86::EBP: - Name = "BP"; - break; - case X86::ESP: - Name = "SP"; - break; - } + Reg = getX86SubSuperRegister(Reg, MVT::i16); break; case 'k': // Print SImode register - switch (Reg) { - default: return true; - case X86::AH: case X86::AL: case X86::AX: case X86::EAX: - Name = "EAX"; - break; - case X86::DH: case X86::DL: case X86::DX: case X86::EDX: - Name = "EDX"; - break; - case X86::CH: case X86::CL: case X86::CX: case X86::ECX: - Name = "ECX"; - break; - case X86::BH: case X86::BL: case X86::BX: case X86::EBX: - Name = "EBX"; - break; - case X86::ESI: - Name = "ESI"; - break; - case X86::EDI: - Name = "EDI"; - break; - case X86::EBP: - Name = "EBP"; - break; - case X86::ESP: - Name = "ESP"; - break; - } + Reg = getX86SubSuperRegister(Reg, MVT::i32); break; } - O << Name; + O << '%' << RI.get(Reg).Name; return false; } @@ -392,6 +305,26 @@ void X86IntelAsmPrinter::printMachineInstruction(const MachineInstr *MI) { ++EmittedInsts; + // See if a truncate instruction can be turned into a nop. + switch (MI->getOpcode()) { + default: break; + case X86::TRUNC_R32_R16: + case X86::TRUNC_R32_R8: + case X86::TRUNC_R16_R8: { + const MachineOperand &MO0 = MI->getOperand(0); + const MachineOperand &MO1 = MI->getOperand(1); + unsigned Reg0 = MO0.getReg(); + unsigned Reg1 = MO1.getReg(); + if (MI->getOpcode() == X86::TRUNC_R16_R8) + Reg0 = getX86SubSuperRegister(Reg0, MVT::i16); + else + Reg0 = getX86SubSuperRegister(Reg0, MVT::i32); + if (Reg0 == Reg1) + O << CommentString << " TRUNCATE "; + break; + } + } + // Call the autogenerated instruction printer routines. printInstruction(MI); } Index: llvm/lib/Target/X86/X86RegisterInfo.cpp diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.149 llvm/lib/Target/X86/X86RegisterInfo.cpp:1.150 --- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.149 Thu May 4 13:16:01 2006 +++ llvm/lib/Target/X86/X86RegisterInfo.cpp Fri May 5 00:40:20 2006 @@ -811,5 +811,81 @@ return hasFP(MF) ? X86::EBP : X86::ESP; } +namespace llvm { +unsigned getX86SubSuperRegister(unsigned Reg, MVT::ValueType VT, bool High) { + switch (VT) { + default: return Reg; + case MVT::i8: + if (High) { + switch (Reg) { + default: return Reg; + case X86::AH: case X86::AL: case X86::AX: case X86::EAX: + return X86::AH; + case X86::DH: case X86::DL: case X86::DX: case X86::EDX: + return X86::DH; + case X86::CH: case X86::CL: case X86::CX: case X86::ECX: + return X86::CH; + case X86::BH: case X86::BL: case X86::BX: case X86::EBX: + return X86::BH; + } + } else { + switch (Reg) { + default: return Reg; + case X86::AH: case X86::AL: case X86::AX: case X86::EAX: + return X86::AL; + case X86::DH: case X86::DL: case X86::DX: case X86::EDX: + return X86::DL; + case X86::CH: case X86::CL: case X86::CX: case X86::ECX: + return X86::CL; + case X86::BH: case X86::BL: case X86::BX: case X86::EBX: + return X86::BL; + } + } + case MVT::i16: + switch (Reg) { + default: return Reg; + case X86::AH: case X86::AL: case X86::AX: case X86::EAX: + return X86::AX; + case X86::DH: case X86::DL: case X86::DX: case X86::EDX: + return X86::DX; + case X86::CH: case X86::CL: case X86::CX: case X86::ECX: + return X86::CX; + case X86::BH: case X86::BL: case X86::BX: case X86::EBX: + return X86::BX; + case X86::ESI: + return X86::SI; + case X86::EDI: + return X86::DI; + case X86::EBP: + return X86::BP; + case X86::ESP: + return X86::SP; + } + case MVT::i32: + switch (Reg) { + default: return true; + case X86::AH: case X86::AL: case X86::AX: case X86::EAX: + return X86::EAX; + case X86::DH: case X86::DL: case X86::DX: case X86::EDX: + return X86::EDX; + case X86::CH: case X86::CL: case X86::CX: case X86::ECX: + return X86::ECX; + case X86::BH: case X86::BL: case X86::BX: case X86::EBX: + return X86::EBX; + case X86::SI: + return X86::ESI; + case X86::DI: + return X86::EDI; + case X86::BP: + return X86::EBP; + case X86::SP: + return X86::ESP; + } + } + + return Reg; +} +} + #include "X86GenRegisterInfo.inc" Index: llvm/lib/Target/X86/X86RegisterInfo.h diff -u llvm/lib/Target/X86/X86RegisterInfo.h:1.37 llvm/lib/Target/X86/X86RegisterInfo.h:1.38 --- llvm/lib/Target/X86/X86RegisterInfo.h:1.37 Fri Apr 7 11:34:46 2006 +++ llvm/lib/Target/X86/X86RegisterInfo.h Fri May 5 00:40:20 2006 @@ -68,6 +68,11 @@ unsigned getFrameRegister(MachineFunction &MF) const; }; +// getX86SubSuperRegister - X86 utility function. It returns the sub or super +// register of a specific X86 register. +// e.g. getX86SubSuperRegister(X86::EAX, MVT::i16) return X86:AX +unsigned getX86SubSuperRegister(unsigned, MVT::ValueType, bool High=false); + } // End llvm namespace #endif From lattner at cs.uiuc.edu Fri May 5 00:52:02 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 5 May 2006 00:52:02 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <200605050552.AAA24324@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.151 -> 1.152 --- Log message: Factor some code, add these transformations: // fold (and (trunc x), (trunc y)) -> (trunc (and x, y)) // fold (or (trunc x), (trunc y)) -> (trunc (or x, y)) // fold (xor (trunc x), (trunc y)) -> (trunc (xor x, y)) --- Diffs of the changes: (+66 -55) DAGCombiner.cpp | 121 ++++++++++++++++++++++++++++++-------------------------- 1 files changed, 66 insertions(+), 55 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.151 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.152 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.151 Fri Apr 28 18:33:20 2006 +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri May 5 00:51:50 2006 @@ -222,6 +222,7 @@ SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS); bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS); + SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N); SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2); SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, SDOperand N3, ISD::CondCode CC); @@ -1035,6 +1036,53 @@ return SDOperand(); } +/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with +/// two operands of the same opcode, try to simplify it. +SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { + SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1); + MVT::ValueType VT = N0.getValueType(); + assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); + + // fold (and (zext x), (zext y)) -> (zext (and x, y)) + // fold (or (zext x), (zext y)) -> (zext (or x, y)) + // fold (xor (zext x), (zext y)) -> (zext (xor x, y)) + if (N0.getOpcode() == ISD::ZERO_EXTEND && + N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { + SDOperand ORNode = DAG.getNode(N->getOpcode(), + N0.getOperand(0).getValueType(), + N0.getOperand(0), N1.getOperand(0)); + AddToWorkList(ORNode.Val); + return DAG.getNode(ISD::ZERO_EXTEND, VT, ORNode); + } + + // fold (and (trunc x), (trunc y)) -> (trunc (and x, y)) + // fold (or (trunc x), (trunc y)) -> (trunc (or x, y)) + // fold (xor (trunc x), (trunc y)) -> (trunc (xor x, y)) + if (N0.getOpcode() == ISD::TRUNCATE && + N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { + SDOperand ORNode = DAG.getNode(N->getOpcode(), + N0.getOperand(0).getValueType(), + N0.getOperand(0), N1.getOperand(0)); + AddToWorkList(ORNode.Val); + return DAG.getNode(ISD::TRUNCATE, VT, ORNode); + } + + // fold (and (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (and x, y)) + // fold (or (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (or x, y)) + // fold (xor (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (xor x, y)) + if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || + N0.getOpcode() == ISD::SRA) && + N0.getOperand(1) == N1.getOperand(1)) { + SDOperand ORNode = DAG.getNode(N->getOpcode(), + N0.getOperand(0).getValueType(), + N0.getOperand(0), N1.getOperand(0)); + AddToWorkList(ORNode.Val); + return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); + } + + return SDOperand(); +} + SDOperand DAGCombiner::visitAND(SDNode *N) { SDOperand N0 = N->getOperand(0); SDOperand N1 = N->getOperand(1); @@ -1121,25 +1169,13 @@ return DAG.getSetCC(N0.getValueType(), LL, LR, Result); } } - // fold (and (zext x), (zext y)) -> (zext (and x, y)) - if (N0.getOpcode() == ISD::ZERO_EXTEND && - N1.getOpcode() == ISD::ZERO_EXTEND && - N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { - SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(), - N0.getOperand(0), N1.getOperand(0)); - AddToWorkList(ANDNode.Val); - return DAG.getNode(ISD::ZERO_EXTEND, VT, ANDNode); - } - // fold (and (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (and x, y)) - if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) || - (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) || - (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) && - N0.getOperand(1) == N1.getOperand(1)) { - SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(), - N0.getOperand(0), N1.getOperand(0)); - AddToWorkList(ANDNode.Val); - return DAG.getNode(N0.getOpcode(), VT, ANDNode, N0.getOperand(1)); + + // Simplify: and (op x...), (op y...) -> (op (and x, y)) + if (N0.getOpcode() == N1.getOpcode()) { + SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); + if (Tmp.Val) return Tmp; } + // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) // fold (and (sra)) -> (and (srl)) when possible. if (!MVT::isVector(VT) && @@ -1292,25 +1328,13 @@ return DAG.getSetCC(N0.getValueType(), LL, LR, Result); } } - // fold (or (zext x), (zext y)) -> (zext (or x, y)) - if (N0.getOpcode() == ISD::ZERO_EXTEND && - N1.getOpcode() == ISD::ZERO_EXTEND && - N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { - SDOperand ORNode = DAG.getNode(ISD::OR, N0.getOperand(0).getValueType(), - N0.getOperand(0), N1.getOperand(0)); - AddToWorkList(ORNode.Val); - return DAG.getNode(ISD::ZERO_EXTEND, VT, ORNode); - } - // fold (or (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (or x, y)) - if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) || - (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) || - (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) && - N0.getOperand(1) == N1.getOperand(1)) { - SDOperand ORNode = DAG.getNode(ISD::OR, N0.getOperand(0).getValueType(), - N0.getOperand(0), N1.getOperand(0)); - AddToWorkList(ORNode.Val); - return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); + + // Simplify: or (op x...), (op y...) -> (op (or x, y)) + if (N0.getOpcode() == N1.getOpcode()) { + SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); + if (Tmp.Val) return Tmp; } + // canonicalize shl to left side in a shl/srl pair, to match rotate if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) std::swap(N0, N1); @@ -1429,26 +1453,13 @@ return DAG.getNode(ISD::BUILD_VECTOR, VT, Ops); } } - // fold (xor (zext x), (zext y)) -> (zext (xor x, y)) - if (N0.getOpcode() == ISD::ZERO_EXTEND && - N1.getOpcode() == ISD::ZERO_EXTEND && - N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { - SDOperand XORNode = DAG.getNode(ISD::XOR, N0.getOperand(0).getValueType(), - N0.getOperand(0), N1.getOperand(0)); - AddToWorkList(XORNode.Val); - return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode); - } - // fold (xor (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (xor x, y)) - if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) || - (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) || - (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) && - N0.getOperand(1) == N1.getOperand(1)) { - SDOperand XORNode = DAG.getNode(ISD::XOR, N0.getOperand(0).getValueType(), - N0.getOperand(0), N1.getOperand(0)); - AddToWorkList(XORNode.Val); - return DAG.getNode(N0.getOpcode(), VT, XORNode, N0.getOperand(1)); + + // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) + if (N0.getOpcode() == N1.getOpcode()) { + SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); + if (Tmp.Val) return Tmp; } - + // Simplify the expression using non-local knowledge. if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0))) From lattner at cs.uiuc.edu Fri May 5 00:59:11 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 5 May 2006 00:59:11 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <200605050559.AAA24392@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.152 -> 1.153 --- Log message: Implement a variety of simplifications for ANY_EXTEND. --- Diffs of the changes: (+51 -0) DAGCombiner.cpp | 51 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 51 insertions(+) Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.152 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.153 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.152 Fri May 5 00:51:50 2006 +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri May 5 00:58:59 2006 @@ -188,6 +188,7 @@ SDOperand visitSETCC(SDNode *N); SDOperand visitSIGN_EXTEND(SDNode *N); SDOperand visitZERO_EXTEND(SDNode *N); + SDOperand visitANY_EXTEND(SDNode *N); SDOperand visitSIGN_EXTEND_INREG(SDNode *N); SDOperand visitTRUNCATE(SDNode *N); SDOperand visitBIT_CONVERT(SDNode *N); @@ -628,6 +629,7 @@ case ISD::SETCC: return visitSETCC(N); case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); + case ISD::ANY_EXTEND: return visitANY_EXTEND(N); case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); case ISD::TRUNCATE: return visitTRUNCATE(N); case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); @@ -1869,6 +1871,55 @@ return SDOperand(); } +SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) { + SDOperand N0 = N->getOperand(0); + ConstantSDNode *N0C = dyn_cast(N0); + MVT::ValueType VT = N->getValueType(0); + + // fold (aext c1) -> c1 + if (N0C) + return DAG.getNode(ISD::ANY_EXTEND, VT, N0); + // fold (aext (aext x)) -> (aext x) + // fold (aext (zext x)) -> (zext x) + // fold (aext (sext x)) -> (sext x) + if (N0.getOpcode() == ISD::ANY_EXTEND || + N0.getOpcode() == ISD::ZERO_EXTEND || + N0.getOpcode() == ISD::SIGN_EXTEND) + return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); + + // fold (aext (truncate x)) -> x iff x size == zext size. + if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT) + return N0.getOperand(0); + // fold (aext (load x)) -> (aext (truncate (extload x))) + if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() && + (!AfterLegalize||TLI.isOperationLegal(ISD::EXTLOAD, N0.getValueType()))) { + SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, N0.getOperand(0), + N0.getOperand(1), N0.getOperand(2), + N0.getValueType()); + CombineTo(N, ExtLoad); + CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), + ExtLoad.getValue(1)); + return SDOperand(N, 0); // Return N so it doesn't get rechecked! + } + + // fold (aext (zextload x)) -> (aext (truncate (zextload x))) + // fold (aext (sextload x)) -> (aext (truncate (sextload x))) + // fold (aext ( extload x)) -> (aext (truncate (extload x))) + if ((N0.getOpcode() == ISD::ZEXTLOAD || N0.getOpcode() == ISD::EXTLOAD || + N0.getOpcode() == ISD::SEXTLOAD) && + N0.hasOneUse()) { + SDOperand ExtLoad = DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0), + N0.getOperand(1), N0.getOperand(2), + N0.getOperand(3)); + CombineTo(N, ExtLoad); + CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), + ExtLoad.getValue(1)); + return SDOperand(N, 0); // Return N so it doesn't get rechecked! + } + return SDOperand(); +} + + SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { SDOperand N0 = N->getOperand(0); SDOperand N1 = N->getOperand(1); From lattner at cs.uiuc.edu Fri May 5 01:10:55 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 5 May 2006 01:10:55 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <200605050610.BAA24692@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.153 -> 1.154 --- Log message: Pull and through and/or/xor. This compiles some bitfield code to: mov EAX, DWORD PTR [ESP + 4] mov ECX, DWORD PTR [EAX] mov EDX, ECX add EDX, EDX or EDX, ECX and EDX, -2147483648 and ECX, 2147483647 or EDX, ECX mov DWORD PTR [EAX], EDX ret instead of: sub ESP, 4 mov DWORD PTR [ESP], ESI mov EAX, DWORD PTR [ESP + 8] mov ECX, DWORD PTR [EAX] mov EDX, ECX add EDX, EDX mov ESI, ECX and ESI, -2147483648 and EDX, -2147483648 or EDX, ESI and ECX, 2147483647 or EDX, ECX mov DWORD PTR [EAX], EDX mov ESI, DWORD PTR [ESP] add ESP, 4 ret --- Diffs of the changes: (+6 -4) DAGCombiner.cpp | 10 ++++++---- 1 files changed, 6 insertions(+), 4 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.153 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.154 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.153 Fri May 5 00:58:59 2006 +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri May 5 01:10:43 2006 @@ -1069,11 +1069,13 @@ return DAG.getNode(ISD::TRUNCATE, VT, ORNode); } - // fold (and (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (and x, y)) - // fold (or (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (or x, y)) - // fold (xor (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (xor x, y)) + + // For each of OP in SHL/SRL/SRA/AND... + // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) + // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) + // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || - N0.getOpcode() == ISD::SRA) && + N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && N0.getOperand(1) == N1.getOperand(1)) { SDOperand ORNode = DAG.getNode(N->getOpcode(), N0.getOperand(0).getValueType(), From lattner at cs.uiuc.edu Fri May 5 01:31:17 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 5 May 2006 01:31:17 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <200605050631.BAA24891@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.154 -> 1.155 --- Log message: Implement: // fold (and (sext x), (sext y)) -> (sext (and x, y)) // fold (or (sext x), (sext y)) -> (sext (or x, y)) // fold (xor (sext x), (sext y)) -> (sext (xor x, y)) // fold (and (aext x), (aext y)) -> (aext (and x, y)) // fold (or (aext x), (aext y)) -> (aext (or x, y)) // fold (xor (aext x), (aext y)) -> (aext (xor x, y)) --- Diffs of the changes: (+7 -5) DAGCombiner.cpp | 12 +++++++----- 1 files changed, 7 insertions(+), 5 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.154 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.155 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.154 Fri May 5 01:10:43 2006 +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri May 5 01:31:05 2006 @@ -1045,16 +1045,18 @@ MVT::ValueType VT = N0.getValueType(); assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); - // fold (and (zext x), (zext y)) -> (zext (and x, y)) - // fold (or (zext x), (zext y)) -> (zext (or x, y)) - // fold (xor (zext x), (zext y)) -> (zext (xor x, y)) - if (N0.getOpcode() == ISD::ZERO_EXTEND && + // For each of OP in AND/OR/XOR: + // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) + // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) + // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) + if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| + N0.getOpcode() == ISD::SIGN_EXTEND) && N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { SDOperand ORNode = DAG.getNode(N->getOpcode(), N0.getOperand(0).getValueType(), N0.getOperand(0), N1.getOperand(0)); AddToWorkList(ORNode.Val); - return DAG.getNode(ISD::ZERO_EXTEND, VT, ORNode); + return DAG.getNode(N0.getOpcode(), VT, ORNode); } // fold (and (trunc x), (trunc y)) -> (trunc (and x, y)) From lattner at cs.uiuc.edu Fri May 5 01:32:16 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 5 May 2006 01:32:16 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <200605050632.BAA24924@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.155 -> 1.156 --- Log message: Fold some common code. --- Diffs of the changes: (+2 -14) DAGCombiner.cpp | 16 ++-------------- 1 files changed, 2 insertions(+), 14 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.155 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.156 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.155 Fri May 5 01:31:05 2006 +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri May 5 01:32:04 2006 @@ -1049,8 +1049,9 @@ // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) + // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| - N0.getOpcode() == ISD::SIGN_EXTEND) && + N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { SDOperand ORNode = DAG.getNode(N->getOpcode(), N0.getOperand(0).getValueType(), @@ -1059,19 +1060,6 @@ return DAG.getNode(N0.getOpcode(), VT, ORNode); } - // fold (and (trunc x), (trunc y)) -> (trunc (and x, y)) - // fold (or (trunc x), (trunc y)) -> (trunc (or x, y)) - // fold (xor (trunc x), (trunc y)) -> (trunc (xor x, y)) - if (N0.getOpcode() == ISD::TRUNCATE && - N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { - SDOperand ORNode = DAG.getNode(N->getOpcode(), - N0.getOperand(0).getValueType(), - N0.getOperand(0), N1.getOperand(0)); - AddToWorkList(ORNode.Val); - return DAG.getNode(ISD::TRUNCATE, VT, ORNode); - } - - // For each of OP in SHL/SRL/SRA/AND... // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) From lattner at cs.uiuc.edu Fri May 5 01:38:53 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 5 May 2006 01:38:53 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/InstCombine/cast.ll Message-ID: <200605050638.BAA24996@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/InstCombine: cast.ll updated: 1.27 -> 1.28 --- Log message: New testcase --- Diffs of the changes: (+8 -0) cast.ll | 8 ++++++++ 1 files changed, 8 insertions(+) Index: llvm/test/Regression/Transforms/InstCombine/cast.ll diff -u llvm/test/Regression/Transforms/InstCombine/cast.ll:1.27 llvm/test/Regression/Transforms/InstCombine/cast.ll:1.28 --- llvm/test/Regression/Transforms/InstCombine/cast.ll:1.27 Wed Apr 12 13:07:41 2006 +++ llvm/test/Regression/Transforms/InstCombine/cast.ll Fri May 5 01:38:40 2006 @@ -177,3 +177,11 @@ ret float* %c } +uint %test29(uint %c1, uint %c2) { + %tmp1 = cast uint %c1 to ubyte + %tmp4.mask = cast uint %c2 to ubyte + %tmp = or ubyte %tmp4.mask, %tmp1 + %tmp10 = cast ubyte %tmp to uint + ret uint %tmp10 +} + From lattner at cs.uiuc.edu Fri May 5 01:39:19 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 5 May 2006 01:39:19 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp Message-ID: <200605050639.BAA25010@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: InstructionCombining.cpp updated: 1.474 -> 1.475 --- Log message: Implement InstCombine/cast.ll:test29 --- Diffs of the changes: (+40 -0) InstructionCombining.cpp | 40 ++++++++++++++++++++++++++++++++++++++++ 1 files changed, 40 insertions(+) Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.474 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.475 --- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.474 Thu May 4 12:33:35 2006 +++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Fri May 5 01:39:07 2006 @@ -2640,6 +2640,19 @@ } } + // fold (and (cast A), (cast B)) -> (cast (and A, B)) + if (CastInst *Op0C = dyn_cast(Op0)) { + if (CastInst *Op1C = dyn_cast(Op1)) + if (Op0C->getOperand(0)->getType() == Op1C->getOperand(0)->getType() && + Op0C->getOperand(0)->getType()->isIntegral()) { + Instruction *NewOp = BinaryOperator::createAnd(Op0C->getOperand(0), + Op1C->getOperand(0), + I.getName()); + InsertNewInstBefore(NewOp, I); + return new CastInst(NewOp, I.getType()); + } + } + return Changed ? &I : 0; } @@ -2865,6 +2878,20 @@ } } } + + // fold (or (cast A), (cast B)) -> (cast (or A, B)) + if (CastInst *Op0C = dyn_cast(Op0)) { + if (CastInst *Op1C = dyn_cast(Op1)) + if (Op0C->getOperand(0)->getType() == Op1C->getOperand(0)->getType() && + Op0C->getOperand(0)->getType()->isIntegral()) { + Instruction *NewOp = BinaryOperator::createOr(Op0C->getOperand(0), + Op1C->getOperand(0), + I.getName()); + InsertNewInstBefore(NewOp, I); + return new CastInst(NewOp, I.getType()); + } + } + return Changed ? &I : 0; } @@ -3030,6 +3057,19 @@ if (Instruction *R = AssociativeOpt(I, FoldSetCCLogical(*this, RHS))) return R; + // fold (xor (cast A), (cast B)) -> (cast (xor A, B)) + if (CastInst *Op0C = dyn_cast(Op0)) { + if (CastInst *Op1C = dyn_cast(Op1)) + if (Op0C->getOperand(0)->getType() == Op1C->getOperand(0)->getType() && + Op0C->getOperand(0)->getType()->isIntegral()) { + Instruction *NewOp = BinaryOperator::createXor(Op0C->getOperand(0), + Op1C->getOperand(0), + I.getName()); + InsertNewInstBefore(NewOp, I); + return new CastInst(NewOp, I.getType()); + } + } + return Changed ? &I : 0; } From evan.cheng at apple.com Fri May 5 03:23:20 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 5 May 2006 03:23:20 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.td Message-ID: <200605050823.DAA17159@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrInfo.td updated: 1.264 -> 1.265 --- Log message: Need extload patterns after Chris' DAG combiner changes --- Diffs of the changes: (+11 -1) X86InstrInfo.td | 12 +++++++++++- 1 files changed, 11 insertions(+), 1 deletion(-) Index: llvm/lib/Target/X86/X86InstrInfo.td diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.264 llvm/lib/Target/X86/X86InstrInfo.td:1.265 --- llvm/lib/Target/X86/X86InstrInfo.td:1.264 Fri May 5 00:40:20 2006 +++ llvm/lib/Target/X86/X86InstrInfo.td Fri May 5 03:23:07 2006 @@ -306,6 +306,11 @@ def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextload node:$ptr, i16))>; def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extload node:$ptr, i1))>; +def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extload node:$ptr, i1))>; +def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extload node:$ptr, i1))>; +def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extload node:$ptr, i8))>; +def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extload node:$ptr, i8))>; +def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extload node:$ptr, i16))>; //===----------------------------------------------------------------------===// // Instruction templates... @@ -2393,7 +2398,12 @@ def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; // extload bool -> extload byte -def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>; +def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>; +def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>; +def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; +def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>; +def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>; +def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>; // anyext -> zext def : Pat<(i16 (anyext R8 :$src)), (MOVZX16rr8 R8 :$src)>; From lattner at cs.uiuc.edu Fri May 5 15:51:44 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 5 May 2006 15:51:44 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp Message-ID: <200605052051.PAA25107@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: InstructionCombining.cpp updated: 1.475 -> 1.476 --- Log message: Fix an infinite loop compiling oggenc last night. --- Diffs of the changes: (+9 -6) InstructionCombining.cpp | 15 +++++++++------ 1 files changed, 9 insertions(+), 6 deletions(-) Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.475 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.476 --- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.475 Fri May 5 01:39:07 2006 +++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Fri May 5 15:51:30 2006 @@ -2642,9 +2642,10 @@ // fold (and (cast A), (cast B)) -> (cast (and A, B)) if (CastInst *Op0C = dyn_cast(Op0)) { + const Type *SrcTy = Op0C->getOperand(0)->getType(); if (CastInst *Op1C = dyn_cast(Op1)) - if (Op0C->getOperand(0)->getType() == Op1C->getOperand(0)->getType() && - Op0C->getOperand(0)->getType()->isIntegral()) { + if (SrcTy == Op1C->getOperand(0)->getType() && SrcTy->isIntegral() && + !SrcTy->isLosslesslyConvertibleTo(Op0C->getType())) { Instruction *NewOp = BinaryOperator::createAnd(Op0C->getOperand(0), Op1C->getOperand(0), I.getName()); @@ -2881,9 +2882,10 @@ // fold (or (cast A), (cast B)) -> (cast (or A, B)) if (CastInst *Op0C = dyn_cast(Op0)) { + const Type *SrcTy = Op0C->getOperand(0)->getType(); if (CastInst *Op1C = dyn_cast(Op1)) - if (Op0C->getOperand(0)->getType() == Op1C->getOperand(0)->getType() && - Op0C->getOperand(0)->getType()->isIntegral()) { + if (SrcTy == Op1C->getOperand(0)->getType() && SrcTy->isIntegral() && + !SrcTy->isLosslesslyConvertibleTo(Op0C->getType())) { Instruction *NewOp = BinaryOperator::createOr(Op0C->getOperand(0), Op1C->getOperand(0), I.getName()); @@ -3059,9 +3061,10 @@ // fold (xor (cast A), (cast B)) -> (cast (xor A, B)) if (CastInst *Op0C = dyn_cast(Op0)) { + const Type *SrcTy = Op0C->getOperand(0)->getType(); if (CastInst *Op1C = dyn_cast(Op1)) - if (Op0C->getOperand(0)->getType() == Op1C->getOperand(0)->getType() && - Op0C->getOperand(0)->getType()->isIntegral()) { + if (SrcTy == Op1C->getOperand(0)->getType() && SrcTy->isIntegral() && + !SrcTy->isLosslesslyConvertibleTo(Op0C->getType())) { Instruction *NewOp = BinaryOperator::createXor(Op0C->getOperand(0), Op1C->getOperand(0), I.getName()); From lattner at cs.uiuc.edu Fri May 5 16:18:02 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 5 May 2006 16:18:02 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Message-ID: <200605052118.QAA25254@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAGISel.cpp updated: 1.234 -> 1.235 --- Log message: More aggressively sink GEP offsets into loops. For example, before we generated: movl 8(%esp), %eax movl %eax, %edx addl $4316, %edx cmpb $1, %cl ja LBB1_2 #cond_false LBB1_1: #cond_true movl L_QuantizationTables720$non_lazy_ptr, %ecx movl %ecx, (%edx) movl L_QNOtoQuantTableShift720$non_lazy_ptr, %edx movl %edx, 4460(%eax) ret ... Now we generate: movl 8(%esp), %eax cmpb $1, %cl ja LBB1_2 #cond_false LBB1_1: #cond_true movl L_QuantizationTables720$non_lazy_ptr, %ecx movl %ecx, 4316(%eax) movl L_QNOtoQuantTableShift720$non_lazy_ptr, %ecx movl %ecx, 4460(%eax) ret ... which uses one fewer register. --- Diffs of the changes: (+115 -56) SelectionDAGISel.cpp | 171 ++++++++++++++++++++++++++++++++++----------------- 1 files changed, 115 insertions(+), 56 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.234 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.235 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.234 Thu May 4 20:04:50 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Fri May 5 16:17:49 2006 @@ -2733,45 +2733,18 @@ } -/// InsertGEPComputeCode - Insert code into BB to compute Ptr+PtrOffset, -/// casting to the type of GEPI. -static Value *InsertGEPComputeCode(Value *&V, BasicBlock *BB, Instruction *GEPI, - Value *Ptr, Value *PtrOffset) { - if (V) return V; // Already computed. - - BasicBlock::iterator InsertPt; - if (BB == GEPI->getParent()) { - // If insert into the GEP's block, insert right after the GEP. - InsertPt = GEPI; - ++InsertPt; - } else { - // Otherwise, insert at the top of BB, after any PHI nodes - InsertPt = BB->begin(); - while (isa(InsertPt)) ++InsertPt; - } - - // If Ptr is itself a cast, but in some other BB, emit a copy of the cast into - // BB so that there is only one value live across basic blocks (the cast - // operand). - if (CastInst *CI = dyn_cast(Ptr)) - if (CI->getParent() != BB && isa(CI->getOperand(0)->getType())) - Ptr = new CastInst(CI->getOperand(0), CI->getType(), "", InsertPt); - - // Add the offset, cast it to the right type. - Ptr = BinaryOperator::createAdd(Ptr, PtrOffset, "", InsertPt); - Ptr = new CastInst(Ptr, GEPI->getType(), "", InsertPt); - return V = Ptr; -} - /// OptimizeNoopCopyExpression - We have determined that the specified cast /// instruction is a noop copy (e.g. it's casting from one pointer type to /// another, int->uint, or int->sbyte on PPC. -static void OptimizeNoopCopyExpression(CastInst *CI) { +/// +/// Return true if any changes are made. +static bool OptimizeNoopCopyExpression(CastInst *CI) { BasicBlock *DefBB = CI->getParent(); /// InsertedCasts - Only insert a cast in each block once. std::map InsertedCasts; + bool MadeChange = false; for (Value::use_iterator UI = CI->use_begin(), E = CI->use_end(); UI != E; ) { Use &TheUse = UI.getUse(); @@ -2800,20 +2773,103 @@ InsertedCast = new CastInst(CI->getOperand(0), CI->getType(), "", InsertPt); + MadeChange = true; } // Replace a use of the cast with a use of the new casat. TheUse = InsertedCast; } + + // If we removed all uses, nuke the cast. + if (CI->use_empty()) + CI->eraseFromParent(); + + return MadeChange; } +/// InsertGEPComputeCode - Insert code into BB to compute Ptr+PtrOffset, +/// casting to the type of GEPI. +static Value *InsertGEPComputeCode(Value *&V, BasicBlock *BB, Instruction *GEPI, + Value *Ptr, Value *PtrOffset) { + if (V) return V; // Already computed. + + BasicBlock::iterator InsertPt; + if (BB == GEPI->getParent()) { + // If insert into the GEP's block, insert right after the GEP. + InsertPt = GEPI; + ++InsertPt; + } else { + // Otherwise, insert at the top of BB, after any PHI nodes + InsertPt = BB->begin(); + while (isa(InsertPt)) ++InsertPt; + } + + // If Ptr is itself a cast, but in some other BB, emit a copy of the cast into + // BB so that there is only one value live across basic blocks (the cast + // operand). + if (CastInst *CI = dyn_cast(Ptr)) + if (CI->getParent() != BB && isa(CI->getOperand(0)->getType())) + Ptr = new CastInst(CI->getOperand(0), CI->getType(), "", InsertPt); + + // Add the offset, cast it to the right type. + Ptr = BinaryOperator::createAdd(Ptr, PtrOffset, "", InsertPt); + Ptr = new CastInst(Ptr, GEPI->getType(), "", InsertPt); + return V = Ptr; +} + +/// ReplaceUsesOfGEPInst - Replace all uses of RepPtr with inserted code to +/// compute its value. The RepPtr value can be computed with Ptr+PtrOffset. One +/// trivial way of doing this would be to evaluate Ptr+PtrOffset in RepPtr's +/// block, then ReplaceAllUsesWith'ing everything. However, we would prefer to +/// sink PtrOffset into user blocks where doing so will likely allow us to fold +/// the constant add into a load or store instruction. Additionally, if a user +/// is a pointer-pointer cast, we look through it to find its users. +static void ReplaceUsesOfGEPInst(Instruction *RepPtr, Value *Ptr, + Constant *PtrOffset, BasicBlock *DefBB, + GetElementPtrInst *GEPI, + std::map &InsertedExprs) { + while (!RepPtr->use_empty()) { + Instruction *User = cast(RepPtr->use_back()); + + // If the user is a Pointer-Pointer cast, recurse. + if (isa(User) && isa(User->getType())) { + ReplaceUsesOfGEPInst(User, Ptr, PtrOffset, DefBB, GEPI, InsertedExprs); + + // Drop the use of RepPtr. The cast is dead. Don't delete it now, else we + // could invalidate an iterator. + User->setOperand(0, UndefValue::get(RepPtr->getType())); + continue; + } + + // If this is a load of the pointer, or a store through the pointer, emit + // the increment into the load/store block. + Value *NewVal; + if (isa(User) || + (isa(User) && User->getOperand(0) != RepPtr)) { + NewVal = InsertGEPComputeCode(InsertedExprs[User->getParent()], + User->getParent(), GEPI, + Ptr, PtrOffset); + } else { + // If this use is not foldable into the addressing mode, use a version + // emitted in the GEP block. + NewVal = InsertGEPComputeCode(InsertedExprs[DefBB], DefBB, GEPI, + Ptr, PtrOffset); + } + + if (GEPI->getType() != RepPtr->getType()) + NewVal = new CastInst(NewVal, RepPtr->getType(), "", User); + User->replaceUsesOfWith(RepPtr, NewVal); + } +} + + /// OptimizeGEPExpression - Since we are doing basic-block-at-a-time instruction /// selection, we want to be a bit careful about some things. In particular, if /// we have a GEP instruction that is used in a different block than it is /// defined, the addressing expression of the GEP cannot be folded into loads or /// stores that use it. In this case, decompose the GEP and move constant /// indices into blocks that use it. -static void OptimizeGEPExpression(GetElementPtrInst *GEPI, +static bool OptimizeGEPExpression(GetElementPtrInst *GEPI, const TargetData *TD) { // If this GEP is only used inside the block it is defined in, there is no // need to rewrite it. @@ -2826,21 +2882,36 @@ break; } } - if (!isUsedOutsideDefBB) return; + if (!isUsedOutsideDefBB) return false; // If this GEP has no non-zero constant indices, there is nothing we can do, // ignore it. bool hasConstantIndex = false; + bool hasVariableIndex = false; for (GetElementPtrInst::op_iterator OI = GEPI->op_begin()+1, E = GEPI->op_end(); OI != E; ++OI) { - if (ConstantInt *CI = dyn_cast(*OI)) + if (ConstantInt *CI = dyn_cast(*OI)) { if (CI->getRawValue()) { hasConstantIndex = true; break; } + } else { + hasVariableIndex = true; + } + } + + // If this is a "GEP X, 0, 0, 0", turn this into a cast. + if (!hasConstantIndex && !hasVariableIndex) { + Value *NC = new CastInst(GEPI->getOperand(0), GEPI->getType(), + GEPI->getName(), GEPI); + GEPI->replaceAllUsesWith(NC); + GEPI->eraseFromParent(); + return true; } + // If this is a GEP &Alloca, 0, 0, forward subst the frame index into uses. - if (!hasConstantIndex && !isa(GEPI->getOperand(0))) return; + if (!hasConstantIndex && !isa(GEPI->getOperand(0))) + return false; // Otherwise, decompose the GEP instruction into multiplies and adds. Sum the // constant offset (which we now know is non-zero) and deal with it later. @@ -2900,28 +2971,12 @@ // won't be foldable as addresses, so we might as well share the computation). std::map InsertedExprs; - while (!GEPI->use_empty()) { - Instruction *User = cast(GEPI->use_back()); - - // If this use is not foldable into the addressing mode, use a version - // emitted in the GEP block. - Value *NewVal; - if (!isa(User) && - (!isa(User) || User->getOperand(0) == GEPI)) { - NewVal = InsertGEPComputeCode(InsertedExprs[DefBB], DefBB, GEPI, - Ptr, PtrOffset); - } else { - // Otherwise, insert the code in the User's block so it can be folded into - // any users in that block. - NewVal = InsertGEPComputeCode(InsertedExprs[User->getParent()], - User->getParent(), GEPI, - Ptr, PtrOffset); - } - User->replaceUsesOfWith(GEPI, NewVal); - } + ReplaceUsesOfGEPInst(GEPI, Ptr, PtrOffset, DefBB, GEPI, InsertedExprs); // Finally, the GEP is dead, remove it. GEPI->eraseFromParent(); + + return true; } bool SelectionDAGISel::runOnFunction(Function &Fn) { @@ -2938,6 +2993,9 @@ // selection. // // + bool MadeChange = true; + while (MadeChange) { + MadeChange = false; for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { PHINode *PN; BasicBlock::iterator BBI; @@ -2949,7 +3007,7 @@ for (BasicBlock::iterator E = BB->end(); BBI != E; ) { Instruction *I = BBI++; if (GetElementPtrInst *GEPI = dyn_cast(I)) { - OptimizeGEPExpression(GEPI, TLI.getTargetData()); + MadeChange |= OptimizeGEPExpression(GEPI, TLI.getTargetData()); } else if (CastInst *CI = dyn_cast(I)) { // If this is a noop copy, sink it into user blocks to reduce the number // of virtual registers that must be created and coallesced. @@ -2974,10 +3032,11 @@ // If, after promotion, these are the same types, this is a noop copy. if (SrcVT == DstVT) - OptimizeNoopCopyExpression(CI); + MadeChange |= OptimizeNoopCopyExpression(CI); } } } + } FunctionLoweringInfo FuncInfo(TLI, Fn, MF); From lattner at cs.uiuc.edu Fri May 5 16:34:48 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 5 May 2006 16:34:48 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <200605052134.QAA25537@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.156 -> 1.157 --- Log message: Fold (fpext (load x)) -> (extload x) --- Diffs of the changes: (+14 -0) DAGCombiner.cpp | 14 ++++++++++++++ 1 files changed, 14 insertions(+) Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.156 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.157 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.156 Fri May 5 01:32:04 2006 +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri May 5 16:34:35 2006 @@ -2413,6 +2413,20 @@ // fold (fp_extend c1fp) -> c1fp if (N0CFP) return DAG.getNode(ISD::FP_EXTEND, VT, N0); + + // fold (fpext (load x)) -> (fpext (fpround (extload x))) + if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() && + (!AfterLegalize||TLI.isOperationLegal(ISD::EXTLOAD, N0.getValueType()))) { + SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, N0.getOperand(0), + N0.getOperand(1), N0.getOperand(2), + N0.getValueType()); + CombineTo(N, ExtLoad); + CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad), + ExtLoad.getValue(1)); + return SDOperand(N, 0); // Return N so it doesn't get rechecked! + } + + return SDOperand(); } From lattner at cs.uiuc.edu Fri May 5 16:35:31 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 5 May 2006 16:35:31 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86InstrSSE.td Message-ID: <200605052135.QAA25599@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.198 -> 1.199 X86InstrSSE.td updated: 1.115 -> 1.116 --- Log message: Teach the code generator to use cvtss2sd as extload f32 -> f64 --- Diffs of the changes: (+1 -5) X86ISelLowering.cpp | 4 ---- X86InstrSSE.td | 2 +- 2 files changed, 1 insertion(+), 5 deletions(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.198 llvm/lib/Target/X86/X86ISelLowering.cpp:1.199 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.198 Tue May 2 20:29:57 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Fri May 5 16:35:18 2006 @@ -207,10 +207,6 @@ addRegisterClass(MVT::f32, X86::FR32RegisterClass); addRegisterClass(MVT::f64, X86::FR64RegisterClass); - // SSE has no load+extend ops - setOperationAction(ISD::EXTLOAD, MVT::f32, Expand); - setOperationAction(ISD::ZEXTLOAD, MVT::f32, Expand); - // Use ANDPD to simulate FABS. setOperationAction(ISD::FABS , MVT::f64, Custom); setOperationAction(ISD::FABS , MVT::f32, Custom); Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.115 llvm/lib/Target/X86/X86InstrSSE.td:1.116 --- llvm/lib/Target/X86/X86InstrSSE.td:1.115 Wed May 3 15:32:03 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Fri May 5 16:35:18 2006 @@ -526,7 +526,7 @@ Requires<[HasSSE2]>; def CVTSS2SDrm: I<0x5A, MRMSrcMem, (ops FR64:$dst, f32mem:$src), "cvtss2sd {$src, $dst|$dst, $src}", - [(set FR64:$dst, (fextend (loadf32 addr:$src)))]>, XS, + [(set FR64:$dst, (extload addr:$src, f32))]>, XS, Requires<[HasSSE2]>; // Match intrinsics which expect XMM operand(s). From lattner at cs.uiuc.edu Fri May 5 16:47:18 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 5 May 2006 16:47:18 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/AsmPrinter.cpp Message-ID: <200605052147.QAA25684@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: AsmPrinter.cpp updated: 1.66 -> 1.67 --- Log message: Indent multiline asm strings more nicely --- Diffs of the changes: (+9 -5) AsmPrinter.cpp | 14 +++++++++----- 1 files changed, 9 insertions(+), 5 deletions(-) Index: llvm/lib/CodeGen/AsmPrinter.cpp diff -u llvm/lib/CodeGen/AsmPrinter.cpp:1.66 llvm/lib/CodeGen/AsmPrinter.cpp:1.67 --- llvm/lib/CodeGen/AsmPrinter.cpp:1.66 Tue May 2 20:29:56 2006 +++ llvm/lib/CodeGen/AsmPrinter.cpp Fri May 5 16:47:05 2006 @@ -34,8 +34,8 @@ GlobalVarAddrSuffix(""), FunctionAddrPrefix(""), FunctionAddrSuffix(""), - InlineAsmStart("#APP\n\t"), - InlineAsmEnd("\t#NO_APP\n"), + InlineAsmStart("#APP"), + InlineAsmEnd("#NO_APP"), ZeroDirective("\t.zero\t"), ZeroDirectiveSuffix(0), AsciiDirective("\t.ascii\t"), @@ -558,7 +558,7 @@ /// printInlineAsm - This method formats and prints the specified machine /// instruction that is an inline asm. void AsmPrinter::printInlineAsm(const MachineInstr *MI) const { - O << InlineAsmStart; + O << InlineAsmStart << "\n\t"; unsigned NumOperands = MI->getNumOperands(); // Count the number of register definitions. @@ -583,13 +583,17 @@ // Not a special case, emit the string section literally. const char *LiteralEnd = LastEmitted+1; while (*LiteralEnd && *LiteralEnd != '{' && *LiteralEnd != '|' && - *LiteralEnd != '}' && *LiteralEnd != '$') + *LiteralEnd != '}' && *LiteralEnd != '$' && *LiteralEnd != '\n') ++LiteralEnd; if (CurVariant == -1 || CurVariant == AsmPrinterVariant) O.write(LastEmitted, LiteralEnd-LastEmitted); LastEmitted = LiteralEnd; break; } + case '\n': + ++LastEmitted; // Consume newline character. + O << "\n\t"; // Indent code with newline. + break; case '$': { ++LastEmitted; // Consume '$' character. if (*LastEmitted == '$') { // $$ -> $ @@ -707,7 +711,7 @@ break; } } - O << "\n" << InlineAsmEnd; + O << "\n\t" << InlineAsmEnd << "\n"; } /// PrintAsmOperand - Print the specified operand of MI, an INLINEASM From lattner at cs.uiuc.edu Fri May 5 16:49:03 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 5 May 2006 16:49:03 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86AsmPrinter.cpp Message-ID: <200605052149.QAA25749@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86AsmPrinter.cpp updated: 1.177 -> 1.178 --- Log message: Print *some* grouping around inline asm blocks so we know where they are. --- Diffs of the changes: (+2 -1) X86AsmPrinter.cpp | 3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index: llvm/lib/Target/X86/X86AsmPrinter.cpp diff -u llvm/lib/Target/X86/X86AsmPrinter.cpp:1.177 llvm/lib/Target/X86/X86AsmPrinter.cpp:1.178 --- llvm/lib/Target/X86/X86AsmPrinter.cpp:1.177 Thu May 4 11:19:27 2006 +++ llvm/lib/Target/X86/X86AsmPrinter.cpp Fri May 5 16:48:50 2006 @@ -66,7 +66,8 @@ forDarwin = true; StaticCtorsSection = ".mod_init_func"; StaticDtorsSection = ".mod_term_func"; - InlineAsmStart = InlineAsmEnd = ""; // Don't use #APP/#NO_APP + InlineAsmStart = "# InlineAsm Start"; + InlineAsmEnd = "# InlineAsm End"; break; case X86Subtarget::isCygwin: GlobalPrefix = "_"; From lattner at cs.uiuc.edu Fri May 5 16:50:17 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 5 May 2006 16:50:17 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp Message-ID: <200605052150.QAA25792@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCAsmPrinter.cpp updated: 1.171 -> 1.172 --- Log message: Print a grouping around inline asm blocks so that we can tell when we are using them. --- Diffs of the changes: (+2 -1) PPCAsmPrinter.cpp | 3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp diff -u llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.171 llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.172 --- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.171 Thu May 4 13:05:43 2006 +++ llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp Fri May 5 16:50:04 2006 @@ -282,7 +282,8 @@ LCOMMDirective = "\t.lcomm\t"; StaticCtorsSection = ".mod_init_func"; StaticDtorsSection = ".mod_term_func"; - InlineAsmStart = InlineAsmEnd = ""; // Don't use #APP/#NO_APP + InlineAsmStart = "# InlineAsm Start"; + InlineAsmEnd = "# InlineAsm End"; } virtual const char *getPassName() const { From lattner at cs.uiuc.edu Fri May 5 17:32:25 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 5 May 2006 17:32:25 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp Message-ID: <200605052232.RAA26001@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target: TargetLowering.cpp updated: 1.54 -> 1.55 --- Log message: Implement ComputeMaskedBits/SimplifyDemandedBits for ISD::TRUNCATE --- Diffs of the changes: (+18 -0) TargetLowering.cpp | 18 ++++++++++++++++++ 1 files changed, 18 insertions(+) Index: llvm/lib/Target/TargetLowering.cpp diff -u llvm/lib/Target/TargetLowering.cpp:1.54 llvm/lib/Target/TargetLowering.cpp:1.55 --- llvm/lib/Target/TargetLowering.cpp:1.54 Tue May 2 20:29:56 2006 +++ llvm/lib/Target/TargetLowering.cpp Fri May 5 17:32:12 2006 @@ -607,6 +607,16 @@ assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); break; } + case ISD::TRUNCATE: { + if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask, + KnownZero, KnownOne, TLO, Depth+1)) + return true; + assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); + uint64_t OutMask = MVT::getIntVTBitMask(Op.getValueType()); + KnownZero &= OutMask; + KnownOne &= OutMask; + break; + } case ISD::AssertZext: { MVT::ValueType VT = cast(Op.getOperand(1))->getVT(); uint64_t InMask = MVT::getIntVTBitMask(VT); @@ -864,6 +874,14 @@ KnownZero, KnownOne, Depth+1); return; } + case ISD::TRUNCATE: { + ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); + assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); + uint64_t OutMask = MVT::getIntVTBitMask(Op.getValueType()); + KnownZero &= OutMask; + KnownOne &= OutMask; + break; + } case ISD::AssertZext: { MVT::ValueType VT = cast(Op.getOperand(1))->getVT(); uint64_t InMask = MVT::getIntVTBitMask(VT); From lattner at cs.uiuc.edu Fri May 5 17:53:30 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 5 May 2006 17:53:30 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <200605052253.RAA26128@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.157 -> 1.158 --- Log message: Shrink shifts when possible. --- Diffs of the changes: (+12 -0) DAGCombiner.cpp | 12 ++++++++++++ 1 files changed, 12 insertions(+) Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.157 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.158 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.157 Fri May 5 16:34:35 2006 +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri May 5 17:53:17 2006 @@ -1615,6 +1615,18 @@ DAG.getConstant(c1 + c2, N1.getValueType())); } + // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) + if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { + // Shifting in all undef bits? + MVT::ValueType SmallVT = N0.getOperand(0).getValueType(); + if (N1C->getValue() >= MVT::getSizeInBits(SmallVT)) + return DAG.getNode(ISD::UNDEF, VT); + + SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1); + AddToWorkList(SmallShift.Val); + return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift); + } + // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). if (N1C && N0.getOpcode() == ISD::CTLZ && N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) { From lattner at cs.uiuc.edu Fri May 5 17:56:38 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 5 May 2006 17:56:38 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <200605052256.RAA26199@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.158 -> 1.159 --- Log message: Fold trunc(any_ext). This gives stuff like: 27,28c27 < movzwl %di, %edi < movl %edi, %ebx --- > movw %di, %bx --- Diffs of the changes: (+2 -1) DAGCombiner.cpp | 3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.158 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.159 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.158 Fri May 5 17:53:17 2006 +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri May 5 17:56:26 2006 @@ -2005,7 +2005,8 @@ if (N0.getOpcode() == ISD::TRUNCATE) return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); // fold (truncate (ext x)) -> (ext x) or (truncate x) or x - if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND){ + if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| + N0.getOpcode() == ISD::ANY_EXTEND) { if (N0.getValueType() < VT) // if the source is smaller than the dest, we still need an extend return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); From lattner at cs.uiuc.edu Fri May 5 19:12:04 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 5 May 2006 19:12:04 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp Message-ID: <200605060012.TAA27767@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target: TargetLowering.cpp updated: 1.55 -> 1.56 --- Log message: Fold (trunc (srl x, c)) -> (srl (trunc x), c) --- Diffs of the changes: (+32 -0) TargetLowering.cpp | 32 ++++++++++++++++++++++++++++++++ 1 files changed, 32 insertions(+) Index: llvm/lib/Target/TargetLowering.cpp diff -u llvm/lib/Target/TargetLowering.cpp:1.55 llvm/lib/Target/TargetLowering.cpp:1.56 --- llvm/lib/Target/TargetLowering.cpp:1.55 Fri May 5 17:32:12 2006 +++ llvm/lib/Target/TargetLowering.cpp Fri May 5 19:11:52 2006 @@ -608,9 +608,41 @@ break; } case ISD::TRUNCATE: { + // Simplify the input, using demanded bit information, and compute the known + // zero/one bits live out. if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask, KnownZero, KnownOne, TLO, Depth+1)) return true; + + // If the input is only used by this truncate, see if we can shrink it based + // on the known demanded bits. + if (Op.getOperand(0).Val->hasOneUse()) { + SDOperand In = Op.getOperand(0); + switch (In.getOpcode()) { + default: break; + case ISD::SRL: + // Shrink SRL by a constant if none of the high bits shifted in are + // demanded. + if (ConstantSDNode *ShAmt = dyn_cast(In.getOperand(1))){ + uint64_t HighBits = MVT::getIntVTBitMask(In.getValueType()); + HighBits &= ~MVT::getIntVTBitMask(Op.getValueType()); + HighBits >>= ShAmt->getValue(); + + if (ShAmt->getValue() < MVT::getSizeInBits(Op.getValueType()) && + (DemandedMask & HighBits) == 0) { + // None of the shifted in bits are needed. Add a truncate of the + // shift input, then shift it. + SDOperand NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, + Op.getValueType(), + In.getOperand(0)); + return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL,Op.getValueType(), + NewTrunc, In.getOperand(1))); + } + } + break; + } + } + assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); uint64_t OutMask = MVT::getIntVTBitMask(Op.getValueType()); KnownZero &= OutMask; From lattner at cs.uiuc.edu Fri May 5 19:29:50 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 5 May 2006 19:29:50 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp Message-ID: <200605060029.TAA03425@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.199 -> 1.200 --- Log message: Teach the X86 backend about non-i32 inline asm register classes. --- Diffs of the changes: (+25 -5) X86ISelLowering.cpp | 30 +++++++++++++++++++++++++----- 1 files changed, 25 insertions(+), 5 deletions(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.199 llvm/lib/Target/X86/X86ISelLowering.cpp:1.200 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.199 Fri May 5 16:35:18 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Fri May 5 19:29:37 2006 @@ -3998,14 +3998,34 @@ default: break; // Unknown constriant letter case 'r': // GENERAL_REGS case 'R': // LEGACY_REGS - return make_vector(X86::EAX, X86::EBX, X86::ECX, X86::EDX, - X86::ESI, X86::EDI, X86::EBP, X86::ESP, 0); + if (VT == MVT::i32) + return make_vector(X86::EAX, X86::EDX, X86::ECX, X86::EBX, + X86::ESI, X86::EDI, X86::EBP, X86::ESP, 0); + else if (VT == MVT::i16) + return make_vector(X86::AX, X86::DX, X86::CX, X86::BX, + X86::SI, X86::DI, X86::BP, X86::SP, 0); + else if (VT == MVT::i8) + return make_vector(X86::AL, X86::DL, X86::CL, X86::DL, 0); + break; case 'l': // INDEX_REGS - return make_vector(X86::EAX, X86::EBX, X86::ECX, X86::EDX, - X86::ESI, X86::EDI, X86::EBP, 0); + if (VT == MVT::i32) + return make_vector(X86::EAX, X86::EDX, X86::ECX, X86::EBX, + X86::ESI, X86::EDI, X86::EBP, 0); + else if (VT == MVT::i16) + return make_vector(X86::AX, X86::DX, X86::CX, X86::BX, + X86::SI, X86::DI, X86::BP, 0); + else if (VT == MVT::i8) + return make_vector(X86::AL, X86::DL, X86::CL, X86::DL, 0); + break; case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode) case 'Q': // Q_REGS - return make_vector(X86::EAX, X86::EBX, X86::ECX, X86::EDX, 0); + if (VT == MVT::i32) + return make_vector(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0); + else if (VT == MVT::i16) + return make_vector(X86::AX, X86::DX, X86::CX, X86::BX, 0); + else if (VT == MVT::i8) + return make_vector(X86::AL, X86::DL, X86::CL, X86::DL, 0); + break; case 'x': // SSE_REGS if SSE1 allowed if (Subtarget->hasSSE1()) return make_vector(X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, From lattner at cs.uiuc.edu Sat May 6 03:58:19 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 6 May 2006 03:58:19 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/InstCombine/2006-05-06-Infloop.ll Message-ID: <200605060858.DAA22547@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/InstCombine: 2006-05-06-Infloop.ll added (r1.1) --- Log message: new testcase from ghostscript that inf looped instcombine --- Diffs of the changes: (+522 -0) 2006-05-06-Infloop.ll | 522 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 522 insertions(+) Index: llvm/test/Regression/Transforms/InstCombine/2006-05-06-Infloop.ll diff -c /dev/null llvm/test/Regression/Transforms/InstCombine/2006-05-06-Infloop.ll:1.1 *** /dev/null Sat May 6 03:58:16 2006 --- llvm/test/Regression/Transforms/InstCombine/2006-05-06-Infloop.ll Sat May 6 03:58:06 2006 *************** *** 0 **** --- 1,522 ---- + ; RUN: llvm-as < %s | opt -instcombine -disable-output + + %struct.gs_matrix = type { float, int, float, int, float, int, float, int, float, int, float, int } + %struct.gx_bitmap = type { ubyte*, int, int, int } + %struct.gx_device = type { int, %struct.gx_device_procs*, sbyte*, int, int, float, float, int, ushort, int, int } + %struct.gx_device_memory = type { int, %struct.gx_device_procs*, sbyte*, int, int, float, float, int, ushort, int, int, %struct.gs_matrix, int, ubyte*, ubyte**, int (%struct.gx_device_memory*, int, int, int, int, int)*, int, int, ubyte* } + %struct.gx_device_procs = type { int (%struct.gx_device*)*, void (%struct.gx_device*, %struct.gs_matrix*)*, int (%struct.gx_device*)*, int (%struct.gx_device*)*, int (%struct.gx_device*)*, uint (%struct.gx_device*, ushort, ushort, ushort)*, int (%struct.gx_device*, uint, ushort*)*, int (%struct.gx_device*, int, int, int, int, uint)*, int (%struct.gx_device*, %struct.gx_bitmap*, int, int, int, int, uint, uint)*, int (%struct.gx_device*, ubyte*, int, int, int, int, int, int, uint, uint)*, int (%struct.gx_device*, ubyte*, int, int, int, int, int, int)*, int (%struct.gx_device*, int, int, int, int, uint)*, int (%struct.gx_device*, int, int, int, int, int, int, uint)*, int (%struct.gx_device*, %struct.gx_bitmap*, int, int, int, int, int, int, uint, uint)* } + + implementation ; Functions: + + int %mem_mono_copy_mono(%struct.gx_device* %dev, ubyte* %base, int %sourcex, int %raster, int %x, int %y, int %w, int %h, uint %zero, uint %one) { + entry: + %raster = cast int %raster to uint ; [#uses=3] + %tmp = seteq uint %one, %zero ; [#uses=1] + br bool %tmp, label %cond_true, label %cond_next + + cond_true: ; preds = %entry + %tmp6 = tail call int %mem_mono_fill_rectangle( %struct.gx_device* %dev, int %x, int %y, int %w, int %h, uint %zero ) ; [#uses=1] + ret int %tmp6 + + cond_next: ; preds = %entry + %tmp8 = cast %struct.gx_device* %dev to %struct.gx_device_memory* ; <%struct.gx_device_memory*> [#uses=6] + %tmp = getelementptr %struct.gx_device_memory* %tmp8, int 0, uint 15 ; [#uses=1] + %tmp = load int (%struct.gx_device_memory*, int, int, int, int, int)** %tmp ; [#uses=2] + %tmp9 = seteq int (%struct.gx_device_memory*, int, int, int, int, int)* %tmp, %mem_no_fault_proc ; [#uses=1] + br bool %tmp9, label %cond_next46, label %cond_true10 + + cond_true10: ; preds = %cond_next + %tmp16 = add int %x, 7 ; [#uses=1] + %tmp17 = add int %tmp16, %w ; [#uses=1] + %tmp18 = shr int %tmp17, ubyte 3 ; [#uses=1] + %tmp20 = shr int %x, ubyte 3 ; [#uses=2] + %tmp21 = sub int %tmp18, %tmp20 ; [#uses=1] + %tmp27 = tail call int %tmp( %struct.gx_device_memory* %tmp8, int %tmp20, int %y, int %tmp21, int %h, int 1 ) ; [#uses=2] + %tmp29 = setlt int %tmp27, 0 ; [#uses=1] + br bool %tmp29, label %cond_true30, label %cond_next46 + + cond_true30: ; preds = %cond_true10 + %tmp41 = tail call int %mem_copy_mono_recover( %struct.gx_device* %dev, ubyte* %base, int %sourcex, int %raster, int %x, int %y, int %w, int %h, uint %zero, uint %one, int %tmp27 ) ; [#uses=1] + ret int %tmp41 + + cond_next46: ; preds = %cond_true10, %cond_next + %tmp48 = setgt int %w, 0 ; [#uses=1] + %tmp53 = setgt int %h, 0 ; [#uses=1] + %bothcond = and bool %tmp53, %tmp48 ; [#uses=1] + br bool %bothcond, label %bb58, label %return + + bb58: ; preds = %cond_next46 + %tmp60 = setlt int %x, 0 ; [#uses=1] + br bool %tmp60, label %return, label %cond_next63 + + cond_next63: ; preds = %bb58 + %tmp65 = getelementptr %struct.gx_device_memory* %tmp8, int 0, uint 3 ; [#uses=1] + %tmp66 = load int* %tmp65 ; [#uses=1] + %tmp68 = sub int %tmp66, %w ; [#uses=1] + %tmp70 = setlt int %tmp68, %x ; [#uses=1] + %tmp75 = setlt int %y, 0 ; [#uses=1] + %bothcond1 = or bool %tmp70, %tmp75 ; [#uses=1] + br bool %bothcond1, label %return, label %cond_next78 + + cond_next78: ; preds = %cond_next63 + %tmp80 = getelementptr %struct.gx_device_memory* %tmp8, int 0, uint 4 ; [#uses=1] + %tmp81 = load int* %tmp80 ; [#uses=1] + %tmp83 = sub int %tmp81, %h ; [#uses=1] + %tmp85 = setlt int %tmp83, %y ; [#uses=1] + br bool %tmp85, label %return, label %bb91 + + bb91: ; preds = %cond_next78 + %tmp93 = shr int %x, ubyte 3 ; [#uses=4] + %tmp = getelementptr %struct.gx_device_memory* %tmp8, int 0, uint 14 ; [#uses=1] + %tmp = load ubyte*** %tmp ; [#uses=1] + %tmp96 = getelementptr ubyte** %tmp, int %y ; [#uses=4] + %tmp98 = load ubyte** %tmp96 ; [#uses=1] + %tmp100 = getelementptr ubyte* %tmp98, int %tmp93 ; [#uses=3] + %tmp102 = shr int %sourcex, ubyte 3 ; [#uses=3] + %tmp106 = and int %sourcex, 7 ; [#uses=1] + %tmp107 = sub int 8, %tmp106 ; [#uses=4] + %tmp109 = and int %x, 7 ; [#uses=3] + %tmp110 = sub int 8, %tmp109 ; [#uses=8] + %tmp112 = sub int 8, %tmp110 ; [#uses=1] + %tmp112 = cast int %tmp112 to ubyte ; [#uses=1] + %tmp113464 = shr uint 255, ubyte %tmp112 ; [#uses=4] + %tmp116 = setgt int %tmp110, %w ; [#uses=1] + %tmp132 = getelementptr %struct.gx_device_memory* %tmp8, int 0, uint 16 ; [#uses=2] + br bool %tmp116, label %cond_true117, label %cond_false123 + + cond_true117: ; preds = %bb91 + %tmp119 = cast int %w to ubyte ; [#uses=1] + %tmp120 = shr uint %tmp113464, ubyte %tmp119 ; [#uses=1] + %tmp122 = sub uint %tmp113464, %tmp120 ; [#uses=2] + %tmp13315 = load int* %tmp132 ; [#uses=1] + %tmp13416 = seteq int %tmp13315, 0 ; [#uses=1] + br bool %tmp13416, label %cond_next151, label %cond_true135 + + cond_false123: ; preds = %bb91 + %tmp126 = sub int %w, %tmp110 ; [#uses=1] + %tmp126 = cast int %tmp126 to ubyte ; [#uses=1] + %tmp127 = and ubyte %tmp126, 7 ; [#uses=1] + %tmp128 = shr uint 255, ubyte %tmp127 ; [#uses=1] + %tmp1295 = sub uint 255, %tmp128 ; [#uses=2] + %tmp133 = load int* %tmp132 ; [#uses=1] + %tmp134 = seteq int %tmp133, 0 ; [#uses=1] + br bool %tmp134, label %cond_next151, label %cond_true135 + + cond_true135: ; preds = %cond_false123, %cond_true117 + %rmask.0.0 = phi uint [ undef, %cond_true117 ], [ %tmp1295, %cond_false123 ] ; [#uses=2] + %mask.1.0 = phi uint [ %tmp122, %cond_true117 ], [ %tmp113464, %cond_false123 ] ; [#uses=2] + %not.tmp137 = setne uint %zero, 4294967295 ; [#uses=1] + %tmp140 = cast bool %not.tmp137 to uint ; [#uses=1] + %zero_addr.0 = xor uint %tmp140, %zero ; [#uses=2] + %tmp144 = seteq uint %one, 4294967295 ; [#uses=1] + br bool %tmp144, label %cond_next151, label %cond_true145 + + cond_true145: ; preds = %cond_true135 + %tmp147 = xor uint %one, 1 ; [#uses=1] + br label %cond_next151 + + cond_next151: ; preds = %cond_true145, %cond_true135, %cond_false123, %cond_true117 + %rmask.0.1 = phi uint [ %rmask.0.0, %cond_true145 ], [ undef, %cond_true117 ], [ %tmp1295, %cond_false123 ], [ %rmask.0.0, %cond_true135 ] ; [#uses=4] + %mask.1.1 = phi uint [ %mask.1.0, %cond_true145 ], [ %tmp122, %cond_true117 ], [ %tmp113464, %cond_false123 ], [ %mask.1.0, %cond_true135 ] ; [#uses=4] + %one_addr.0 = phi uint [ %tmp147, %cond_true145 ], [ %one, %cond_true117 ], [ %one, %cond_false123 ], [ %one, %cond_true135 ] ; [#uses=2] + %zero_addr.1 = phi uint [ %zero_addr.0, %cond_true145 ], [ %zero, %cond_true117 ], [ %zero, %cond_false123 ], [ %zero_addr.0, %cond_true135 ] ; [#uses=2] + %tmp153 = seteq uint %zero_addr.1, 1 ; [#uses=2] + %tmp158 = seteq uint %one_addr.0, 0 ; [#uses=2] + %bothcond2 = or bool %tmp153, %tmp158 ; [#uses=1] + %iftmp.35.0 = select bool %bothcond2, uint 4294967295, uint 0 ; [#uses=8] + %tmp167 = seteq uint %zero_addr.1, 0 ; [#uses=1] + %bothcond3 = or bool %tmp167, %tmp158 ; [#uses=1] + %iftmp.36.0 = select bool %bothcond3, uint 0, uint 4294967295 ; [#uses=4] + %tmp186 = seteq uint %one_addr.0, 1 ; [#uses=1] + %bothcond4 = or bool %tmp153, %tmp186 ; [#uses=1] + %iftmp.37.0 = select bool %bothcond4, uint 4294967295, uint 0 ; [#uses=6] + %tmp196 = seteq int %tmp107, %tmp110 ; [#uses=1] + br bool %tmp196, label %cond_true197, label %cond_false299 + + cond_true197: ; preds = %cond_next151 + %tmp29222 = add int %h, -1 ; [#uses=3] + %tmp29424 = setlt int %tmp29222, 0 ; [#uses=1] + br bool %tmp29424, label %return, label %cond_true295.preheader + + cond_true249.preheader: ; preds = %cond_true295 + br label %cond_true249 + + cond_true249: ; preds = %cond_true249, %cond_true249.preheader + %indvar = phi uint [ 0, %cond_true249.preheader ], [ %indvar.next, %cond_true249 ] ; [#uses=2] + %optr.3.2 = phi ubyte* [ %tmp232, %cond_true249 ], [ %dest.1.0, %cond_true249.preheader ] ; [#uses=1] + %bptr.3.2 = phi ubyte* [ %tmp226, %cond_true249 ], [ %line.1.0, %cond_true249.preheader ] ; [#uses=1] + %tmp. = add int %tmp109, %w ; [#uses=1] + %indvar = cast uint %indvar to int ; [#uses=1] + %tmp.58 = mul int %indvar, -8 ; [#uses=1] + %tmp.57 = add int %tmp., -16 ; [#uses=1] + %tmp246.2 = add int %tmp.58, %tmp.57 ; [#uses=1] + %tmp225 = cast ubyte* %bptr.3.2 to uint ; [#uses=1] + %tmp226 = add uint %tmp225, 1 ; [#uses=1] + %tmp226 = cast uint %tmp226 to ubyte* ; [#uses=3] + %tmp228 = load ubyte* %tmp226 ; [#uses=1] + %tmp228 = cast ubyte %tmp228 to uint ; [#uses=1] + %tmp230 = xor uint %tmp228, %iftmp.35.0 ; [#uses=2] + %tmp231 = cast ubyte* %optr.3.2 to uint ; [#uses=1] + %tmp232 = add uint %tmp231, 1 ; [#uses=1] + %tmp232 = cast uint %tmp232 to ubyte* ; [#uses=4] + %tmp235 = or uint %tmp230, %iftmp.36.0 ; [#uses=1] + %tmp235 = cast uint %tmp235 to ubyte ; [#uses=1] + %tmp237 = load ubyte* %tmp232 ; [#uses=1] + %tmp238 = and ubyte %tmp235, %tmp237 ; [#uses=1] + %tmp241 = and uint %tmp230, %iftmp.37.0 ; [#uses=1] + %tmp241 = cast uint %tmp241 to ubyte ; [#uses=1] + %tmp242 = or ubyte %tmp238, %tmp241 ; [#uses=1] + store ubyte %tmp242, ubyte* %tmp232 + %tmp24629 = add int %tmp246.2, -8 ; [#uses=2] + %tmp24831 = setlt int %tmp24629, 0 ; [#uses=1] + %indvar.next = add uint %indvar, 1 ; [#uses=1] + br bool %tmp24831, label %bb252.loopexit, label %cond_true249 + + bb252.loopexit: ; preds = %cond_true249 + br label %bb252 + + bb252: ; preds = %cond_true295, %bb252.loopexit + %optr.3.3 = phi ubyte* [ %dest.1.0, %cond_true295 ], [ %tmp232, %bb252.loopexit ] ; [#uses=1] + %bptr.3.3 = phi ubyte* [ %line.1.0, %cond_true295 ], [ %tmp226, %bb252.loopexit ] ; [#uses=1] + %tmp246.3 = phi int [ %tmp246, %cond_true295 ], [ %tmp24629, %bb252.loopexit ] ; [#uses=1] + %tmp254 = setgt int %tmp246.3, -8 ; [#uses=1] + br bool %tmp254, label %cond_true255, label %cond_next280 + + cond_true255: ; preds = %bb252 + %tmp256 = cast ubyte* %bptr.3.3 to uint ; [#uses=1] + %tmp257 = add uint %tmp256, 1 ; [#uses=1] + %tmp257 = cast uint %tmp257 to ubyte* ; [#uses=1] + %tmp259 = load ubyte* %tmp257 ; [#uses=1] + %tmp259 = cast ubyte %tmp259 to uint ; [#uses=1] + %tmp261 = xor uint %tmp259, %iftmp.35.0 ; [#uses=2] + %tmp262 = cast ubyte* %optr.3.3 to uint ; [#uses=1] + %tmp263 = add uint %tmp262, 1 ; [#uses=1] + %tmp263 = cast uint %tmp263 to ubyte* ; [#uses=2] + %tmp265 = cast uint %tmp261 to ubyte ; [#uses=1] + %tmp268 = or ubyte %tmp266, %tmp265 ; [#uses=1] + %tmp270 = load ubyte* %tmp263 ; [#uses=1] + %tmp271 = and ubyte %tmp268, %tmp270 ; [#uses=1] + %tmp276 = and uint %tmp274, %tmp261 ; [#uses=1] + %tmp276 = cast uint %tmp276 to ubyte ; [#uses=1] + %tmp277 = or ubyte %tmp271, %tmp276 ; [#uses=1] + store ubyte %tmp277, ubyte* %tmp263 + br label %cond_next280 + + cond_next280: ; preds = %cond_true255, %bb252 + %tmp281 = cast ubyte** %dest_line.1.0 to uint ; [#uses=1] + %tmp282 = add uint %tmp281, 4 ; [#uses=1] + %tmp282 = cast uint %tmp282 to ubyte** ; [#uses=2] + %tmp284 = load ubyte** %tmp282 ; [#uses=1] + %tmp286 = getelementptr ubyte* %tmp284, int %tmp93 ; [#uses=1] + %tmp292 = add int %tmp292.0, -1 ; [#uses=1] + %tmp294 = setlt int %tmp292, 0 ; [#uses=1] + %indvar.next61 = add uint %indvar60, 1 ; [#uses=1] + br bool %tmp294, label %return.loopexit, label %cond_true295 + + cond_true295.preheader: ; preds = %cond_true197 + %tmp200 = sub int %w, %tmp110 ; [#uses=1] + %tmp209 = cast uint %mask.1.1 to ubyte ; [#uses=1] + %tmp209not = xor ubyte %tmp209, 255 ; [#uses=1] + %tmp212 = cast uint %iftmp.36.0 to ubyte ; [#uses=2] + %tmp211 = or ubyte %tmp212, %tmp209not ; [#uses=2] + %tmp219 = and uint %iftmp.37.0, %mask.1.1 ; [#uses=2] + %tmp246 = add int %tmp200, -8 ; [#uses=3] + %tmp248 = setlt int %tmp246, 0 ; [#uses=1] + %tmp264 = cast uint %rmask.0.1 to ubyte ; [#uses=1] + %tmp264not = xor ubyte %tmp264, 255 ; [#uses=1] + %tmp266 = or ubyte %tmp212, %tmp264not ; [#uses=2] + %tmp274 = and uint %iftmp.37.0, %rmask.0.1 ; [#uses=2] + br bool %tmp248, label %cond_true295.preheader.split.us, label %cond_true295.preheader.split + + cond_true295.preheader.split.us: ; preds = %cond_true295.preheader + br label %cond_true295.us + + cond_true295.us: ; preds = %cond_next280.us, %cond_true295.preheader.split.us + %indvar86 = phi uint [ 0, %cond_true295.preheader.split.us ], [ %indvar.next87, %cond_next280.us ] ; [#uses=3] + %dest.1.0.us = phi ubyte* [ %tmp286.us, %cond_next280.us ], [ %tmp100, %cond_true295.preheader.split.us ] ; [#uses=3] + %dest_line.1.0.us = phi ubyte** [ %tmp282.us, %cond_next280.us ], [ %tmp96, %cond_true295.preheader.split.us ] ; [#uses=1] + %tmp.89 = sub uint 0, %indvar86 ; [#uses=1] + %tmp.89 = cast uint %tmp.89 to int ; [#uses=1] + %tmp292.0.us = add int %tmp.89, %tmp29222 ; [#uses=1] + %tmp.91 = mul uint %indvar86, %raster ; [#uses=1] + %tmp.91 = cast uint %tmp.91 to int ; [#uses=1] + %tmp104.sum101 = add int %tmp102, %tmp.91 ; [#uses=1] + %line.1.0.us = getelementptr ubyte* %base, int %tmp104.sum101 ; [#uses=2] + %tmp.us = load ubyte* %line.1.0.us ; [#uses=1] + %tmp206.us = cast ubyte %tmp.us to uint ; [#uses=1] + %tmp208.us = xor uint %tmp206.us, %iftmp.35.0 ; [#uses=2] + %tmp210.us = cast uint %tmp208.us to ubyte ; [#uses=1] + %tmp213.us = or ubyte %tmp211, %tmp210.us ; [#uses=1] + %tmp215.us = load ubyte* %dest.1.0.us ; [#uses=1] + %tmp216.us = and ubyte %tmp213.us, %tmp215.us ; [#uses=1] + %tmp221.us = and uint %tmp219, %tmp208.us ; [#uses=1] + %tmp221.us = cast uint %tmp221.us to ubyte ; [#uses=1] + %tmp222.us = or ubyte %tmp216.us, %tmp221.us ; [#uses=1] + store ubyte %tmp222.us, ubyte* %dest.1.0.us + br bool true, label %bb252.us, label %cond_true249.preheader.us + + cond_next280.us: ; preds = %bb252.us, %cond_true255.us + %tmp281.us = cast ubyte** %dest_line.1.0.us to uint ; [#uses=1] + %tmp282.us = add uint %tmp281.us, 4 ; [#uses=1] + %tmp282.us = cast uint %tmp282.us to ubyte** ; [#uses=2] + %tmp284.us = load ubyte** %tmp282.us ; [#uses=1] + %tmp286.us = getelementptr ubyte* %tmp284.us, int %tmp93 ; [#uses=1] + %tmp292.us = add int %tmp292.0.us, -1 ; [#uses=1] + %tmp294.us = setlt int %tmp292.us, 0 ; [#uses=1] + %indvar.next87 = add uint %indvar86, 1 ; [#uses=1] + br bool %tmp294.us, label %return.loopexit.us, label %cond_true295.us + + cond_true255.us: ; preds = %bb252.us + %tmp256.us = cast ubyte* %bptr.3.3.us to uint ; [#uses=1] + %tmp257.us = add uint %tmp256.us, 1 ; [#uses=1] + %tmp257.us = cast uint %tmp257.us to ubyte* ; [#uses=1] + %tmp259.us = load ubyte* %tmp257.us ; [#uses=1] + %tmp259.us = cast ubyte %tmp259.us to uint ; [#uses=1] + %tmp261.us = xor uint %tmp259.us, %iftmp.35.0 ; [#uses=2] + %tmp262.us = cast ubyte* %optr.3.3.us to uint ; [#uses=1] + %tmp263.us = add uint %tmp262.us, 1 ; [#uses=1] + %tmp263.us = cast uint %tmp263.us to ubyte* ; [#uses=2] + %tmp265.us = cast uint %tmp261.us to ubyte ; [#uses=1] + %tmp268.us = or ubyte %tmp266, %tmp265.us ; [#uses=1] + %tmp270.us = load ubyte* %tmp263.us ; [#uses=1] + %tmp271.us = and ubyte %tmp268.us, %tmp270.us ; [#uses=1] + %tmp276.us = and uint %tmp274, %tmp261.us ; [#uses=1] + %tmp276.us = cast uint %tmp276.us to ubyte ; [#uses=1] + %tmp277.us = or ubyte %tmp271.us, %tmp276.us ; [#uses=1] + store ubyte %tmp277.us, ubyte* %tmp263.us + br label %cond_next280.us + + bb252.us: ; preds = %bb252.loopexit.us, %cond_true295.us + %optr.3.3.us = phi ubyte* [ %dest.1.0.us, %cond_true295.us ], [ undef, %bb252.loopexit.us ] ; [#uses=1] + %bptr.3.3.us = phi ubyte* [ %line.1.0.us, %cond_true295.us ], [ undef, %bb252.loopexit.us ] ; [#uses=1] + %tmp246.3.us = phi int [ %tmp246, %cond_true295.us ], [ undef, %bb252.loopexit.us ] ; [#uses=1] + %tmp254.us = setgt int %tmp246.3.us, -8 ; [#uses=1] + br bool %tmp254.us, label %cond_true255.us, label %cond_next280.us + + cond_true249.us: ; preds = %cond_true249.preheader.us, %cond_true249.us + br bool undef, label %bb252.loopexit.us, label %cond_true249.us + + cond_true249.preheader.us: ; preds = %cond_true295.us + br label %cond_true249.us + + bb252.loopexit.us: ; preds = %cond_true249.us + br label %bb252.us + + return.loopexit.us: ; preds = %cond_next280.us + br label %return.loopexit.split + + cond_true295.preheader.split: ; preds = %cond_true295.preheader + br label %cond_true295 + + cond_true295: ; preds = %cond_true295.preheader.split, %cond_next280 + %indvar60 = phi uint [ 0, %cond_true295.preheader.split ], [ %indvar.next61, %cond_next280 ] ; [#uses=3] + %dest.1.0 = phi ubyte* [ %tmp286, %cond_next280 ], [ %tmp100, %cond_true295.preheader.split ] ; [#uses=4] + %dest_line.1.0 = phi ubyte** [ %tmp282, %cond_next280 ], [ %tmp96, %cond_true295.preheader.split ] ; [#uses=1] + %tmp.63 = sub uint 0, %indvar60 ; [#uses=1] + %tmp.63 = cast uint %tmp.63 to int ; [#uses=1] + %tmp292.0 = add int %tmp.63, %tmp29222 ; [#uses=1] + %tmp.65 = mul uint %indvar60, %raster ; [#uses=1] + %tmp.65 = cast uint %tmp.65 to int ; [#uses=1] + %tmp104.sum97 = add int %tmp102, %tmp.65 ; [#uses=1] + %line.1.0 = getelementptr ubyte* %base, int %tmp104.sum97 ; [#uses=3] + %tmp = load ubyte* %line.1.0 ; [#uses=1] + %tmp206 = cast ubyte %tmp to uint ; [#uses=1] + %tmp208 = xor uint %tmp206, %iftmp.35.0 ; [#uses=2] + %tmp210 = cast uint %tmp208 to ubyte ; [#uses=1] + %tmp213 = or ubyte %tmp211, %tmp210 ; [#uses=1] + %tmp215 = load ubyte* %dest.1.0 ; [#uses=1] + %tmp216 = and ubyte %tmp213, %tmp215 ; [#uses=1] + %tmp221 = and uint %tmp219, %tmp208 ; [#uses=1] + %tmp221 = cast uint %tmp221 to ubyte ; [#uses=1] + %tmp222 = or ubyte %tmp216, %tmp221 ; [#uses=1] + store ubyte %tmp222, ubyte* %dest.1.0 + br bool false, label %bb252, label %cond_true249.preheader + + cond_false299: ; preds = %cond_next151 + %tmp302 = sub int %tmp107, %tmp110 ; [#uses=1] + %tmp303 = and int %tmp302, 7 ; [#uses=3] + %tmp305 = sub int 8, %tmp303 ; [#uses=1] + %tmp45438 = add int %h, -1 ; [#uses=2] + %tmp45640 = setlt int %tmp45438, 0 ; [#uses=1] + br bool %tmp45640, label %return, label %cond_true457.preheader + + cond_true316: ; preds = %cond_true457 + %tmp318 = cast ubyte %tmp318 to uint ; [#uses=1] + %tmp320 = shr uint %tmp318, ubyte %tmp319 ; [#uses=1] + br label %cond_next340 + + cond_false321: ; preds = %cond_true457 + %tmp3188 = cast ubyte %tmp318 to uint ; [#uses=1] + %tmp325 = shl uint %tmp3188, ubyte %tmp324 ; [#uses=2] + %tmp326 = cast ubyte* %line.3.0 to uint ; [#uses=1] + %tmp327 = add uint %tmp326, 1 ; [#uses=1] + %tmp327 = cast uint %tmp327 to ubyte* ; [#uses=3] + br bool %tmp330, label %cond_true331, label %cond_next340 + + cond_true331: ; preds = %cond_false321 + %tmp333 = load ubyte* %tmp327 ; [#uses=1] + %tmp333 = cast ubyte %tmp333 to uint ; [#uses=1] + %tmp335 = shr uint %tmp333, ubyte %tmp319 ; [#uses=1] + %tmp337 = add uint %tmp335, %tmp325 ; [#uses=1] + br label %cond_next340 + + cond_next340: ; preds = %cond_true331, %cond_false321, %cond_true316 + %bits.0 = phi uint [ %tmp320, %cond_true316 ], [ %tmp337, %cond_true331 ], [ %tmp325, %cond_false321 ] ; [#uses=1] + %bptr307.3 = phi ubyte* [ %line.3.0, %cond_true316 ], [ %tmp327, %cond_true331 ], [ %tmp327, %cond_false321 ] ; [#uses=2] + %tmp343 = xor uint %bits.0, %iftmp.35.0 ; [#uses=2] + %tmp345 = cast uint %tmp343 to ubyte ; [#uses=1] + %tmp348 = or ubyte %tmp346, %tmp345 ; [#uses=1] + %tmp350 = load ubyte* %dest.3.0 ; [#uses=1] + %tmp351 = and ubyte %tmp348, %tmp350 ; [#uses=1] + %tmp356 = and uint %tmp354, %tmp343 ; [#uses=1] + %tmp356 = cast uint %tmp356 to ubyte ; [#uses=1] + %tmp357 = or ubyte %tmp351, %tmp356 ; [#uses=1] + store ubyte %tmp357, ubyte* %dest.3.0 + %tmp362 = cast ubyte* %dest.3.0 to uint ; [#uses=1] + %optr309.3.in51 = add uint %tmp362, 1 ; [#uses=2] + %optr309.353 = cast uint %optr309.3.in51 to ubyte* ; [#uses=2] + br bool %tmp39755, label %cond_true398.preheader, label %bb401 + + cond_true398.preheader: ; preds = %cond_next340 + br label %cond_true398 + + cond_true398: ; preds = %cond_true398, %cond_true398.preheader + %indvar66 = phi uint [ 0, %cond_true398.preheader ], [ %indvar.next67, %cond_true398 ] ; [#uses=3] + %bptr307.4.0 = phi ubyte* [ %tmp370, %cond_true398 ], [ %bptr307.3, %cond_true398.preheader ] ; [#uses=2] + %optr309.3.0 = phi ubyte* [ %optr309.3, %cond_true398 ], [ %optr309.353, %cond_true398.preheader ] ; [#uses=2] + %optr309.3.in.0 = add uint %indvar66, %optr309.3.in51 ; [#uses=1] + %tmp.70 = add int %tmp109, %w ; [#uses=1] + %indvar66 = cast uint %indvar66 to int ; [#uses=1] + %tmp.72 = mul int %indvar66, -8 ; [#uses=1] + %tmp.71 = add int %tmp.70, -8 ; [#uses=1] + %count308.3.0 = add int %tmp.72, %tmp.71 ; [#uses=1] + %tmp366 = load ubyte* %bptr307.4.0 ; [#uses=1] + %tmp366 = cast ubyte %tmp366 to uint ; [#uses=1] + %tmp369 = cast ubyte* %bptr307.4.0 to uint ; [#uses=1] + %tmp370 = add uint %tmp369, 1 ; [#uses=1] + %tmp370 = cast uint %tmp370 to ubyte* ; [#uses=3] + %tmp372 = load ubyte* %tmp370 ; [#uses=1] + %tmp372 = cast ubyte %tmp372 to uint ; [#uses=1] + %tmp374463 = shr uint %tmp372, ubyte %tmp319 ; [#uses=1] + %tmp368 = shl uint %tmp366, ubyte %tmp324 ; [#uses=1] + %tmp377 = add uint %tmp374463, %tmp368 ; [#uses=1] + %tmp379 = xor uint %tmp377, %iftmp.35.0 ; [#uses=2] + %tmp382 = or uint %tmp379, %iftmp.36.0 ; [#uses=1] + %tmp382 = cast uint %tmp382 to ubyte ; [#uses=1] + %tmp384 = load ubyte* %optr309.3.0 ; [#uses=1] + %tmp385 = and ubyte %tmp382, %tmp384 ; [#uses=1] + %tmp388 = and uint %tmp379, %iftmp.37.0 ; [#uses=1] + %tmp388 = cast uint %tmp388 to ubyte ; [#uses=1] + %tmp389 = or ubyte %tmp385, %tmp388 ; [#uses=1] + store ubyte %tmp389, ubyte* %optr309.3.0 + %tmp392 = add int %count308.3.0, -8 ; [#uses=2] + %optr309.3.in = add uint %optr309.3.in.0, 1 ; [#uses=1] + %optr309.3 = cast uint %optr309.3.in to ubyte* ; [#uses=2] + %tmp397 = setgt int %tmp392, 7 ; [#uses=1] + %indvar.next67 = add uint %indvar66, 1 ; [#uses=1] + br bool %tmp397, label %cond_true398, label %bb401.loopexit + + bb401.loopexit: ; preds = %cond_true398 + br label %bb401 + + bb401: ; preds = %bb401.loopexit, %cond_next340 + %count308.3.1 = phi int [ %tmp361, %cond_next340 ], [ %tmp392, %bb401.loopexit ] ; [#uses=2] + %bptr307.4.1 = phi ubyte* [ %bptr307.3, %cond_next340 ], [ %tmp370, %bb401.loopexit ] ; [#uses=2] + %optr309.3.1 = phi ubyte* [ %optr309.353, %cond_next340 ], [ %optr309.3, %bb401.loopexit ] ; [#uses=2] + %tmp403 = setgt int %count308.3.1, 0 ; [#uses=1] + br bool %tmp403, label %cond_true404, label %cond_next442 + + cond_true404: ; preds = %bb401 + %tmp406 = load ubyte* %bptr307.4.1 ; [#uses=1] + %tmp406 = cast ubyte %tmp406 to int ; [#uses=1] + %tmp408 = shl int %tmp406, ubyte %tmp324 ; [#uses=2] + %tmp413 = setgt int %count308.3.1, %tmp303 ; [#uses=1] + br bool %tmp413, label %cond_true414, label %cond_next422 + + cond_true414: ; preds = %cond_true404 + %tmp409 = cast ubyte* %bptr307.4.1 to uint ; [#uses=1] + %tmp410 = add uint %tmp409, 1 ; [#uses=1] + %tmp410 = cast uint %tmp410 to ubyte* ; [#uses=1] + %tmp416 = load ubyte* %tmp410 ; [#uses=1] + %tmp416 = cast ubyte %tmp416 to uint ; [#uses=1] + %tmp418 = shr uint %tmp416, ubyte %tmp319 ; [#uses=1] + %tmp418 = cast uint %tmp418 to int ; [#uses=1] + %tmp420 = add int %tmp418, %tmp408 ; [#uses=1] + br label %cond_next422 + + cond_next422: ; preds = %cond_true414, %cond_true404 + %bits.6 = phi int [ %tmp420, %cond_true414 ], [ %tmp408, %cond_true404 ] ; [#uses=1] + %tmp425 = xor int %bits.6, %iftmp.35.0 ; [#uses=1] + %tmp427 = cast int %tmp425 to ubyte ; [#uses=2] + %tmp430 = or ubyte %tmp428, %tmp427 ; [#uses=1] + %tmp432 = load ubyte* %optr309.3.1 ; [#uses=1] + %tmp433 = and ubyte %tmp430, %tmp432 ; [#uses=1] + %tmp438 = and ubyte %tmp436, %tmp427 ; [#uses=1] + %tmp439 = or ubyte %tmp433, %tmp438 ; [#uses=1] + store ubyte %tmp439, ubyte* %optr309.3.1 + br label %cond_next442 + + cond_next442: ; preds = %cond_next422, %bb401 + %tmp443 = cast ubyte** %dest_line.3.0 to uint ; [#uses=1] + %tmp444 = add uint %tmp443, 4 ; [#uses=1] + %tmp444 = cast uint %tmp444 to ubyte** ; [#uses=2] + %tmp446 = load ubyte** %tmp444 ; [#uses=1] + %tmp448 = getelementptr ubyte* %tmp446, int %tmp93 ; [#uses=1] + %tmp454 = add int %tmp454.0, -1 ; [#uses=1] + %tmp456 = setlt int %tmp454, 0 ; [#uses=1] + %indvar.next75 = add uint %indvar74, 1 ; [#uses=1] + br bool %tmp456, label %return.loopexit56, label %cond_true457 + + cond_true457.preheader: ; preds = %cond_false299 + %tmp315 = setlt int %tmp107, %tmp110 ; [#uses=1] + %tmp319 = cast int %tmp303 to ubyte ; [#uses=4] + %tmp324 = cast int %tmp305 to ubyte ; [#uses=3] + %tmp330 = setlt int %tmp107, %w ; [#uses=1] + %tmp344 = cast uint %mask.1.1 to ubyte ; [#uses=1] + %tmp344not = xor ubyte %tmp344, 255 ; [#uses=1] + %tmp347 = cast uint %iftmp.36.0 to ubyte ; [#uses=2] + %tmp346 = or ubyte %tmp347, %tmp344not ; [#uses=1] + %tmp354 = and uint %iftmp.37.0, %mask.1.1 ; [#uses=1] + %tmp361 = sub int %w, %tmp110 ; [#uses=2] + %tmp39755 = setgt int %tmp361, 7 ; [#uses=1] + %iftmp.35.0 = cast uint %iftmp.35.0 to int ; [#uses=1] + %tmp426 = cast uint %rmask.0.1 to ubyte ; [#uses=1] + %tmp426not = xor ubyte %tmp426, 255 ; [#uses=1] + %tmp428 = or ubyte %tmp347, %tmp426not ; [#uses=1] + %tmp436 = and uint %iftmp.37.0, %rmask.0.1 ; [#uses=1] + %tmp436 = cast uint %tmp436 to ubyte ; [#uses=1] + br label %cond_true457 + + cond_true457: ; preds = %cond_true457.preheader, %cond_next442 + %indvar74 = phi uint [ 0, %cond_true457.preheader ], [ %indvar.next75, %cond_next442 ] ; [#uses=3] + %dest.3.0 = phi ubyte* [ %tmp448, %cond_next442 ], [ %tmp100, %cond_true457.preheader ] ; [#uses=3] + %dest_line.3.0 = phi ubyte** [ %tmp444, %cond_next442 ], [ %tmp96, %cond_true457.preheader ] ; [#uses=1] + %tmp.77 = sub uint 0, %indvar74 ; [#uses=1] + %tmp.77 = cast uint %tmp.77 to int ; [#uses=1] + %tmp454.0 = add int %tmp.77, %tmp45438 ; [#uses=1] + %tmp.79 = mul uint %indvar74, %raster ; [#uses=1] + %tmp.79 = cast uint %tmp.79 to int ; [#uses=1] + %tmp104.sum = add int %tmp102, %tmp.79 ; [#uses=1] + %line.3.0 = getelementptr ubyte* %base, int %tmp104.sum ; [#uses=3] + %tmp318 = load ubyte* %line.3.0 ; [#uses=2] + br bool %tmp315, label %cond_false321, label %cond_true316 + + return.loopexit: ; preds = %cond_next280 + br label %return.loopexit.split + + return.loopexit.split: ; preds = %return.loopexit, %return.loopexit.us + br label %return + + return.loopexit56: ; preds = %cond_next442 + br label %return + + return: ; preds = %return.loopexit56, %return.loopexit.split, %cond_false299, %cond_true197, %cond_next78, %cond_next63, %bb58, %cond_next46 + %retval.0 = phi int [ 0, %cond_next46 ], [ -1, %bb58 ], [ -1, %cond_next63 ], [ -1, %cond_next78 ], [ 0, %cond_true197 ], [ 0, %cond_false299 ], [ 0, %return.loopexit.split ], [ 0, %return.loopexit56 ] ; [#uses=1] + ret int %retval.0 + } + + declare int %mem_no_fault_proc(%struct.gx_device_memory*, int, int, int, int, int) + + declare int %mem_mono_fill_rectangle(%struct.gx_device*, int, int, int, int, uint) + + declare int %mem_copy_mono_recover(%struct.gx_device*, ubyte*, int, int, int, int, int, int, uint, uint, int) From lattner at cs.uiuc.edu Sat May 6 04:00:29 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 6 May 2006 04:00:29 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp Message-ID: <200605060900.EAA22642@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: InstructionCombining.cpp updated: 1.476 -> 1.477 --- Log message: Move some code around. Make the "fold (and (cast A), (cast B)) -> (cast (and A, B))" transformation only apply when both casts really will cause code to be generated. If one or both doesn't, then this xform doesn't remove a cast. This fixes Transforms/InstCombine/2006-05-06-Infloop.ll --- Diffs of the changes: (+140 -124) InstructionCombining.cpp | 264 ++++++++++++++++++++++++----------------------- 1 files changed, 140 insertions(+), 124 deletions(-) Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.476 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.477 --- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.476 Fri May 5 15:51:30 2006 +++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Sat May 6 04:00:16 2006 @@ -304,6 +304,137 @@ return 0; } +enum CastType { + Noop = 0, + Truncate = 1, + Signext = 2, + Zeroext = 3 +}; + +/// getCastType - In the future, we will split the cast instruction into these +/// various types. Until then, we have to do the analysis here. +static CastType getCastType(const Type *Src, const Type *Dest) { + assert(Src->isIntegral() && Dest->isIntegral() && + "Only works on integral types!"); + unsigned SrcSize = Src->getPrimitiveSizeInBits(); + unsigned DestSize = Dest->getPrimitiveSizeInBits(); + + if (SrcSize == DestSize) return Noop; + if (SrcSize > DestSize) return Truncate; + if (Src->isSigned()) return Signext; + return Zeroext; +} + + +// isEliminableCastOfCast - Return true if it is valid to eliminate the CI +// instruction. +// +static bool isEliminableCastOfCast(const Type *SrcTy, const Type *MidTy, + const Type *DstTy, TargetData *TD) { + + // It is legal to eliminate the instruction if casting A->B->A if the sizes + // are identical and the bits don't get reinterpreted (for example + // int->float->int would not be allowed). + if (SrcTy == DstTy && SrcTy->isLosslesslyConvertibleTo(MidTy)) + return true; + + // If we are casting between pointer and integer types, treat pointers as + // integers of the appropriate size for the code below. + if (isa(SrcTy)) SrcTy = TD->getIntPtrType(); + if (isa(MidTy)) MidTy = TD->getIntPtrType(); + if (isa(DstTy)) DstTy = TD->getIntPtrType(); + + // Allow free casting and conversion of sizes as long as the sign doesn't + // change... + if (SrcTy->isIntegral() && MidTy->isIntegral() && DstTy->isIntegral()) { + CastType FirstCast = getCastType(SrcTy, MidTy); + CastType SecondCast = getCastType(MidTy, DstTy); + + // Capture the effect of these two casts. If the result is a legal cast, + // the CastType is stored here, otherwise a special code is used. + static const unsigned CastResult[] = { + // First cast is noop + 0, 1, 2, 3, + // First cast is a truncate + 1, 1, 4, 4, // trunc->extend is not safe to eliminate + // First cast is a sign ext + 2, 5, 2, 4, // signext->zeroext never ok + // First cast is a zero ext + 3, 5, 3, 3, + }; + + unsigned Result = CastResult[FirstCast*4+SecondCast]; + switch (Result) { + default: assert(0 && "Illegal table value!"); + case 0: + case 1: + case 2: + case 3: + // FIXME: in the future, when LLVM has explicit sign/zeroextends and + // truncates, we could eliminate more casts. + return (unsigned)getCastType(SrcTy, DstTy) == Result; + case 4: + return false; // Not possible to eliminate this here. + case 5: + // Sign or zero extend followed by truncate is always ok if the result + // is a truncate or noop. + CastType ResultCast = getCastType(SrcTy, DstTy); + if (ResultCast == Noop || ResultCast == Truncate) + return true; + // Otherwise we are still growing the value, we are only safe if the + // result will match the sign/zeroextendness of the result. + return ResultCast == FirstCast; + } + } + + // If this is a cast from 'float -> double -> integer', cast from + // 'float -> integer' directly, as the value isn't changed by the + // float->double conversion. + if (SrcTy->isFloatingPoint() && MidTy->isFloatingPoint() && + DstTy->isIntegral() && + SrcTy->getPrimitiveSize() < MidTy->getPrimitiveSize()) + return true; + + // Packed type conversions don't modify bits. + if (isa(SrcTy) && isa(MidTy) &&isa(DstTy)) + return true; + + return false; +} + +/// ValueRequiresCast - Return true if the cast from "V to Ty" actually results +/// in any code being generated. It does not require codegen if V is simple +/// enough or if the cast can be folded into other casts. +static bool ValueRequiresCast(const Value *V, const Type *Ty, TargetData *TD) { + if (V->getType() == Ty || isa(V)) return false; + + // If this is a noop cast, it isn't real codegen. + if (V->getType()->isLosslesslyConvertibleTo(Ty)) + return false; + + // If this is another cast that can be elimianted, it isn't codegen either. + if (const CastInst *CI = dyn_cast(V)) + if (isEliminableCastOfCast(CI->getOperand(0)->getType(), CI->getType(), Ty, + TD)) + return false; + return true; +} + +/// InsertOperandCastBefore - This inserts a cast of V to DestTy before the +/// InsertBefore instruction. This is specialized a bit to avoid inserting +/// casts that are known to not do anything... +/// +Value *InstCombiner::InsertOperandCastBefore(Value *V, const Type *DestTy, + Instruction *InsertBefore) { + if (V->getType() == DestTy) return V; + if (Constant *C = dyn_cast(V)) + return ConstantExpr::getCast(C, DestTy); + + CastInst *CI = new CastInst(V, DestTy, V->getName()); + InsertNewInstBefore(CI, *InsertBefore); + return CI; +} + // SimplifyCommutative - This performs a few simplifications for commutative // operators: // @@ -2645,7 +2776,9 @@ const Type *SrcTy = Op0C->getOperand(0)->getType(); if (CastInst *Op1C = dyn_cast(Op1)) if (SrcTy == Op1C->getOperand(0)->getType() && SrcTy->isIntegral() && - !SrcTy->isLosslesslyConvertibleTo(Op0C->getType())) { + // Only do this if the casts both really cause code to be generated. + ValueRequiresCast(Op0C->getOperand(0), I.getType(), TD) && + ValueRequiresCast(Op1C->getOperand(0), I.getType(), TD)) { Instruction *NewOp = BinaryOperator::createAnd(Op0C->getOperand(0), Op1C->getOperand(0), I.getName()); @@ -2885,7 +3018,9 @@ const Type *SrcTy = Op0C->getOperand(0)->getType(); if (CastInst *Op1C = dyn_cast(Op1)) if (SrcTy == Op1C->getOperand(0)->getType() && SrcTy->isIntegral() && - !SrcTy->isLosslesslyConvertibleTo(Op0C->getType())) { + // Only do this if the casts both really cause code to be generated. + ValueRequiresCast(Op0C->getOperand(0), I.getType(), TD) && + ValueRequiresCast(Op1C->getOperand(0), I.getType(), TD)) { Instruction *NewOp = BinaryOperator::createOr(Op0C->getOperand(0), Op1C->getOperand(0), I.getName()); @@ -3064,7 +3199,9 @@ const Type *SrcTy = Op0C->getOperand(0)->getType(); if (CastInst *Op1C = dyn_cast(Op1)) if (SrcTy == Op1C->getOperand(0)->getType() && SrcTy->isIntegral() && - !SrcTy->isLosslesslyConvertibleTo(Op0C->getType())) { + // Only do this if the casts both really cause code to be generated. + ValueRequiresCast(Op0C->getOperand(0), I.getType(), TD) && + ValueRequiresCast(Op1C->getOperand(0), I.getType(), TD)) { Instruction *NewOp = BinaryOperator::createXor(Op0C->getOperand(0), Op1C->getOperand(0), I.getName()); @@ -4500,127 +4637,6 @@ return 0; } -enum CastType { - Noop = 0, - Truncate = 1, - Signext = 2, - Zeroext = 3 -}; - -/// getCastType - In the future, we will split the cast instruction into these -/// various types. Until then, we have to do the analysis here. -static CastType getCastType(const Type *Src, const Type *Dest) { - assert(Src->isIntegral() && Dest->isIntegral() && - "Only works on integral types!"); - unsigned SrcSize = Src->getPrimitiveSizeInBits(); - unsigned DestSize = Dest->getPrimitiveSizeInBits(); - - if (SrcSize == DestSize) return Noop; - if (SrcSize > DestSize) return Truncate; - if (Src->isSigned()) return Signext; - return Zeroext; -} - - -// isEliminableCastOfCast - Return true if it is valid to eliminate the CI -// instruction. -// -static bool isEliminableCastOfCast(const Type *SrcTy, const Type *MidTy, - const Type *DstTy, TargetData *TD) { - - // It is legal to eliminate the instruction if casting A->B->A if the sizes - // are identical and the bits don't get reinterpreted (for example - // int->float->int would not be allowed). - if (SrcTy == DstTy && SrcTy->isLosslesslyConvertibleTo(MidTy)) - return true; - - // If we are casting between pointer and integer types, treat pointers as - // integers of the appropriate size for the code below. - if (isa(SrcTy)) SrcTy = TD->getIntPtrType(); - if (isa(MidTy)) MidTy = TD->getIntPtrType(); - if (isa(DstTy)) DstTy = TD->getIntPtrType(); - - // Allow free casting and conversion of sizes as long as the sign doesn't - // change... - if (SrcTy->isIntegral() && MidTy->isIntegral() && DstTy->isIntegral()) { - CastType FirstCast = getCastType(SrcTy, MidTy); - CastType SecondCast = getCastType(MidTy, DstTy); - - // Capture the effect of these two casts. If the result is a legal cast, - // the CastType is stored here, otherwise a special code is used. - static const unsigned CastResult[] = { - // First cast is noop - 0, 1, 2, 3, - // First cast is a truncate - 1, 1, 4, 4, // trunc->extend is not safe to eliminate - // First cast is a sign ext - 2, 5, 2, 4, // signext->zeroext never ok - // First cast is a zero ext - 3, 5, 3, 3, - }; - - unsigned Result = CastResult[FirstCast*4+SecondCast]; - switch (Result) { - default: assert(0 && "Illegal table value!"); - case 0: - case 1: - case 2: - case 3: - // FIXME: in the future, when LLVM has explicit sign/zeroextends and - // truncates, we could eliminate more casts. - return (unsigned)getCastType(SrcTy, DstTy) == Result; - case 4: - return false; // Not possible to eliminate this here. - case 5: - // Sign or zero extend followed by truncate is always ok if the result - // is a truncate or noop. - CastType ResultCast = getCastType(SrcTy, DstTy); - if (ResultCast == Noop || ResultCast == Truncate) - return true; - // Otherwise we are still growing the value, we are only safe if the - // result will match the sign/zeroextendness of the result. - return ResultCast == FirstCast; - } - } - - // If this is a cast from 'float -> double -> integer', cast from - // 'float -> integer' directly, as the value isn't changed by the - // float->double conversion. - if (SrcTy->isFloatingPoint() && MidTy->isFloatingPoint() && - DstTy->isIntegral() && - SrcTy->getPrimitiveSize() < MidTy->getPrimitiveSize()) - return true; - - // Packed type conversions don't modify bits. - if (isa(SrcTy) && isa(MidTy) &&isa(DstTy)) - return true; - - return false; -} - -static bool ValueRequiresCast(const Value *V, const Type *Ty, TargetData *TD) { - if (V->getType() == Ty || isa(V)) return false; - if (const CastInst *CI = dyn_cast(V)) - if (isEliminableCastOfCast(CI->getOperand(0)->getType(), CI->getType(), Ty, - TD)) - return false; - return true; -} - -/// InsertOperandCastBefore - This inserts a cast of V to DestTy before the -/// InsertBefore instruction. This is specialized a bit to avoid inserting -/// casts that are known to not do anything... -/// -Value *InstCombiner::InsertOperandCastBefore(Value *V, const Type *DestTy, - Instruction *InsertBefore) { - if (V->getType() == DestTy) return V; - if (Constant *C = dyn_cast(V)) - return ConstantExpr::getCast(C, DestTy); - - CastInst *CI = new CastInst(V, DestTy, V->getName()); - InsertNewInstBefore(CI, *InsertBefore); - return CI; -} /// DecomposeSimpleLinearExpr - Analyze 'Val', seeing if it is a simple linear /// expression. If so, decompose it, returning some value X, such that Val is From lattner at cs.uiuc.edu Sat May 6 04:10:00 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 6 May 2006 04:10:00 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/Generic/2006-05-06-GEP-Cast-Sink-Crash.ll Message-ID: <200605060910.EAA22923@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/Generic: 2006-05-06-GEP-Cast-Sink-Crash.ll added (r1.1) --- Log message: new testcase --- Diffs of the changes: (+33 -0) 2006-05-06-GEP-Cast-Sink-Crash.ll | 33 +++++++++++++++++++++++++++++++++ 1 files changed, 33 insertions(+) Index: llvm/test/Regression/CodeGen/Generic/2006-05-06-GEP-Cast-Sink-Crash.ll diff -c /dev/null llvm/test/Regression/CodeGen/Generic/2006-05-06-GEP-Cast-Sink-Crash.ll:1.1 *** /dev/null Sat May 6 04:09:57 2006 --- llvm/test/Regression/CodeGen/Generic/2006-05-06-GEP-Cast-Sink-Crash.ll Sat May 6 04:09:47 2006 *************** *** 0 **** --- 1,33 ---- + ; RUN: llvm-as < %s | llc + + %struct.FILE = type { ubyte*, int, int, short, short, %struct.__sbuf, int, sbyte*, int (sbyte*)*, int (sbyte*, sbyte*, int)*, long (sbyte*, long, int)*, int (sbyte*, sbyte*, int)*, %struct.__sbuf, %struct.__sFILEX*, int, [3 x ubyte], [1 x ubyte], %struct.__sbuf, int, long } + %struct.SYMBOL_TABLE_ENTRY = type { [9 x sbyte], [9 x sbyte], int, int, uint, %struct.SYMBOL_TABLE_ENTRY* } + %struct.__sFILEX = type opaque + %struct.__sbuf = type { ubyte*, int } + %str14 = external global [6 x sbyte] ; <[6 x sbyte]*> [#uses=0] + + implementation ; Functions: + + declare void %fprintf(int, ...) + + void %OUTPUT_TABLE(%struct.SYMBOL_TABLE_ENTRY* %SYM_TAB) { + entry: + %tmp11 = getelementptr %struct.SYMBOL_TABLE_ENTRY* %SYM_TAB, int 0, uint 1, int 0 ; [#uses=2] + %tmp.i = cast sbyte* %tmp11 to ubyte* ; [#uses=1] + br label %bb.i + + bb.i: ; preds = %cond_next.i, %entry + %s1.0.i = phi ubyte* [ %tmp.i, %entry ], [ null, %cond_next.i ] ; [#uses=0] + br bool false, label %cond_true.i31, label %cond_next.i + + cond_true.i31: ; preds = %bb.i + call void (int, ...)* %fprintf( int 0, sbyte* %tmp11, sbyte* null ) + ret void + + cond_next.i: ; preds = %bb.i + br bool false, label %bb.i, label %bb19.i + + bb19.i: ; preds = %cond_next.i + ret void + } + From lattner at cs.uiuc.edu Sat May 6 04:10:50 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 6 May 2006 04:10:50 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Message-ID: <200605060910.EAA22956@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAGISel.cpp updated: 1.235 -> 1.236 --- Log message: When inserting casts, be careful of where we put them. We cannot insert a cast immediately before a PHI node. This fixes Regression/CodeGen/Generic/2006-05-06-GEP-Cast-Sink-Crash.ll --- Diffs of the changes: (+12 -9) SelectionDAGISel.cpp | 21 ++++++++++++--------- 1 files changed, 12 insertions(+), 9 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.235 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.236 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.235 Fri May 5 16:17:49 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sat May 6 04:10:37 2006 @@ -2789,8 +2789,9 @@ /// InsertGEPComputeCode - Insert code into BB to compute Ptr+PtrOffset, /// casting to the type of GEPI. -static Value *InsertGEPComputeCode(Value *&V, BasicBlock *BB, Instruction *GEPI, - Value *Ptr, Value *PtrOffset) { +static Instruction *InsertGEPComputeCode(Instruction *&V, BasicBlock *BB, + Instruction *GEPI, Value *Ptr, + Value *PtrOffset) { if (V) return V; // Already computed. BasicBlock::iterator InsertPt; @@ -2813,8 +2814,7 @@ // Add the offset, cast it to the right type. Ptr = BinaryOperator::createAdd(Ptr, PtrOffset, "", InsertPt); - Ptr = new CastInst(Ptr, GEPI->getType(), "", InsertPt); - return V = Ptr; + return V = new CastInst(Ptr, GEPI->getType(), "", InsertPt); } /// ReplaceUsesOfGEPInst - Replace all uses of RepPtr with inserted code to @@ -2827,7 +2827,7 @@ static void ReplaceUsesOfGEPInst(Instruction *RepPtr, Value *Ptr, Constant *PtrOffset, BasicBlock *DefBB, GetElementPtrInst *GEPI, - std::map &InsertedExprs) { + std::map &InsertedExprs) { while (!RepPtr->use_empty()) { Instruction *User = cast(RepPtr->use_back()); @@ -2843,7 +2843,7 @@ // If this is a load of the pointer, or a store through the pointer, emit // the increment into the load/store block. - Value *NewVal; + Instruction *NewVal; if (isa(User) || (isa(User) && User->getOperand(0) != RepPtr)) { NewVal = InsertGEPComputeCode(InsertedExprs[User->getParent()], @@ -2856,8 +2856,11 @@ Ptr, PtrOffset); } - if (GEPI->getType() != RepPtr->getType()) - NewVal = new CastInst(NewVal, RepPtr->getType(), "", User); + if (GEPI->getType() != RepPtr->getType()) { + BasicBlock::iterator IP = NewVal; + ++IP; + NewVal = new CastInst(NewVal, RepPtr->getType(), "", IP); + } User->replaceUsesOfWith(RepPtr, NewVal); } } @@ -2970,7 +2973,7 @@ // block, otherwise we use a canonical version right next to the gep (these // won't be foldable as addresses, so we might as well share the computation). - std::map InsertedExprs; + std::map InsertedExprs; ReplaceUsesOfGEPInst(GEPI, Ptr, PtrOffset, DefBB, GEPI, InsertedExprs); // Finally, the GEP is dead, remove it. From lattner at cs.uiuc.edu Sat May 6 04:26:34 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 6 May 2006 04:26:34 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetLowering.h Message-ID: <200605060926.EAA23078@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/Target: TargetLowering.h updated: 1.70 -> 1.71 --- Log message: Add some new methods for computing sign bit information. --- Diffs of the changes: (+13 -0) TargetLowering.h | 13 +++++++++++++ 1 files changed, 13 insertions(+) Index: llvm/include/llvm/Target/TargetLowering.h diff -u llvm/include/llvm/Target/TargetLowering.h:1.70 llvm/include/llvm/Target/TargetLowering.h:1.71 --- llvm/include/llvm/Target/TargetLowering.h:1.70 Tue May 2 20:29:56 2006 +++ llvm/include/llvm/Target/TargetLowering.h Sat May 6 04:26:22 2006 @@ -389,6 +389,19 @@ uint64_t &KnownOne, unsigned Depth = 0) const; + /// ComputeNumSignBits - Return the number of times the sign bit of the + /// register is replicated into the other bits. We know that at least 1 bit + /// is always equal to the sign bit (itself), but other cases can give us + /// information. For example, immediately after an "SRA X, 2", we know that + /// the top 3 bits are all equal to each other, so we return 3. + unsigned ComputeNumSignBits(SDOperand Op, unsigned Depth = 0) const; + + /// ComputeNumSignBitsForTargetNode - This method can be implemented by + /// targets that want to expose additional information about sign bits to the + /// DAG Combiner. + virtual unsigned ComputeNumSignBitsForTargetNode(SDOperand Op, + unsigned Depth = 0) const; + struct DAGCombinerInfo { void *DC; // The DAG Combiner object. bool BeforeLegalize; From lattner at cs.uiuc.edu Sat May 6 04:27:25 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 6 May 2006 04:27:25 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp Message-ID: <200605060927.EAA23135@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target: TargetLowering.cpp updated: 1.56 -> 1.57 --- Log message: Add some really really simple code for computing sign-bit propagation. This will certainly be enhanced in the future. --- Diffs of the changes: (+95 -0) TargetLowering.cpp | 95 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 95 insertions(+) Index: llvm/lib/Target/TargetLowering.cpp diff -u llvm/lib/Target/TargetLowering.cpp:1.56 llvm/lib/Target/TargetLowering.cpp:1.57 --- llvm/lib/Target/TargetLowering.cpp:1.56 Fri May 5 19:11:52 2006 +++ llvm/lib/Target/TargetLowering.cpp Sat May 6 04:27:13 2006 @@ -995,6 +995,101 @@ KnownOne = 0; } +/// ComputeNumSignBits - Return the number of times the sign bit of the +/// register is replicated into the other bits. We know that at least 1 bit +/// is always equal to the sign bit (itself), but other cases can give us +/// information. For example, immediately after an "SRA X, 2", we know that +/// the top 3 bits are all equal to each other, so we return 3. +unsigned TargetLowering::ComputeNumSignBits(SDOperand Op, unsigned Depth) const{ + MVT::ValueType VT = Op.getValueType(); + assert(MVT::isInteger(VT) && "Invalid VT!"); + unsigned VTBits = MVT::getSizeInBits(VT); + unsigned Tmp, Tmp2; + + if (Depth == 6) + return 1; // Limit search depth. + + switch (Op.getOpcode()) { + default: + // Allow the target to implement this method for its nodes. + if (Op.getOpcode() >= ISD::BUILTIN_OP_END) { + case ISD::INTRINSIC_WO_CHAIN: + case ISD::INTRINSIC_W_CHAIN: + case ISD::INTRINSIC_VOID: + unsigned NumBits = ComputeNumSignBitsForTargetNode(Op, Depth); + if (NumBits > 1) return NumBits; + } + + // FIXME: Should use computemaskedbits to look at the top bits. + return 1; + + case ISD::AssertSext: + Tmp = MVT::getSizeInBits(cast(Op.getOperand(1))->getVT()); + return VTBits-Tmp+1; + case ISD::AssertZext: + Tmp = MVT::getSizeInBits(cast(Op.getOperand(1))->getVT()); + return VTBits-Tmp; + + case ISD::SIGN_EXTEND_INREG: + // Max of the input and what this extends. + Tmp = MVT::getSizeInBits(cast(Op.getOperand(1))->getVT()); + Tmp = VTBits-Tmp+1; + + Tmp2 = ComputeNumSignBits(Op.getOperand(0), Depth+1); + return std::max(Tmp, Tmp2); + + case ISD::SRA: + Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); + // SRA X, C -> adds C sign bits. + if (ConstantSDNode *C = dyn_cast(Op.getOperand(1))) { + Tmp += C->getValue(); + if (Tmp > VTBits) Tmp = VTBits; + } + return Tmp; + + case ISD::ADD: + case ISD::SUB: + // Add and sub can have at most one carry bit. Thus we know that the output + // is, at worst, one more bit than the inputs. + Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); + if (Tmp == 1) return 1; + Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); + if (Tmp2 == 1) return 1; + return std::min(Tmp, Tmp2)-1; + + //case ISD::ZEXTLOAD: // 16 bits known + //case ISD::SEXTLOAD: // 17 bits known + //case ISD::Constant: + //case ISD::SIGN_EXTEND: + // + } + +#if 0 + // fold (sext_in_reg (setcc x)) -> setcc x iff (setcc x) == 0 or -1 + if (N0.getOpcode() == ISD::SETCC && + TLI.getSetCCResultContents() == + TargetLowering::ZeroOrNegativeOneSetCCResult) + return N0; +#endif +} + + + +/// ComputeNumSignBitsForTargetNode - This method can be implemented by +/// targets that want to expose additional information about sign bits to the +/// DAG Combiner. +unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDOperand Op, + unsigned Depth) const { + assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || + Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || + Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || + Op.getOpcode() == ISD::INTRINSIC_VOID) && + "Should use ComputeNumSignBits if you don't know whether Op" + " is a target node!"); + return 1; +} + + SDOperand TargetLowering:: PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { // Default implementation: no optimization. From lattner at cs.uiuc.edu Sat May 6 04:30:16 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 6 May 2006 04:30:16 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <200605060930.EAA23202@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.159 -> 1.160 --- Log message: Use the new TargetLowering::ComputeNumSignBits method to eliminate sign_extend_inreg operations. Though ComputeNumSignBits is still rudimentary, this is enough to compile this: short test(short X, short x) { int Y = X+x; return (Y >> 1); } short test2(short X, short x) { int Y = (short)(X+x); return Y >> 1; } into: _test: add r2, r3, r4 srawi r3, r2, 1 blr _test2: add r2, r3, r4 extsh r2, r2 srawi r3, r2, 1 blr instead of: _test: add r2, r3, r4 srawi r2, r2, 1 extsh r3, r2 blr _test2: add r2, r3, r4 extsh r2, r2 srawi r2, r2, 1 extsh r3, r2 blr --- Diffs of the changes: (+5 -5) DAGCombiner.cpp | 10 +++++----- 1 files changed, 5 insertions(+), 5 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.159 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.160 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.159 Fri May 5 17:56:26 2006 +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sat May 6 04:30:03 2006 @@ -1937,6 +1937,11 @@ SDOperand Truncate = DAG.getConstant(N0C->getValue(), EVT); return DAG.getNode(ISD::SIGN_EXTEND, VT, Truncate); } + + // If the input is already sign extended, just drop the extend. + if (TLI.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1) + return N0; + // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt1 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && cast(N0.getOperand(1))->getVT() <= EVT) { @@ -1947,11 +1952,6 @@ EVT < cast(N0.getOperand(1))->getVT()) { return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); } - // fold (sext_in_reg (assert_sext x)) -> (assert_sext x) - if (N0.getOpcode() == ISD::AssertSext && - cast(N0.getOperand(1))->getVT() <= EVT) { - return N0; - } // fold (sext_in_reg (sextload x)) -> (sextload x) if (N0.getOpcode() == ISD::SEXTLOAD && cast(N0.getOperand(3))->getVT() <= EVT) { From lattner at cs.uiuc.edu Sat May 6 13:16:02 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 6 May 2006 13:16:02 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/and_sext.ll Message-ID: <200605061816.NAA25379@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/PowerPC: and_sext.ll updated: 1.1 -> 1.2 --- Log message: new testcase we handle right now. --- Diffs of the changes: (+20 -6) and_sext.ll | 26 ++++++++++++++++++++------ 1 files changed, 20 insertions(+), 6 deletions(-) Index: llvm/test/Regression/CodeGen/PowerPC/and_sext.ll diff -u llvm/test/Regression/CodeGen/PowerPC/and_sext.ll:1.1 llvm/test/Regression/CodeGen/PowerPC/and_sext.ll:1.2 --- llvm/test/Regression/CodeGen/PowerPC/and_sext.ll:1.1 Fri Feb 17 15:22:08 2006 +++ llvm/test/Regression/CodeGen/PowerPC/and_sext.ll Sat May 6 13:15:50 2006 @@ -1,9 +1,23 @@ -; This test should not contain a sign extend -; RUN: llvm-as < %s | llc -march=ppc32 | not grep extsh +; These tests should not contain a sign extend. +; RUN: llvm-as < %s | llc -march=ppc32 && +; RUN: llvm-as < %s | llc -march=ppc32 | not grep extsh && +; RUN: llvm-as < %s | llc -march=ppc32 | not grep extsb -int %test(uint %mode.0.i.0) { - %tmp.79 = cast uint %mode.0.i.0 to short ; [#uses=1] - %tmp.80 = cast short %tmp.79 to int ; [#uses=1] - %tmp.81 = and int %tmp.80, 24 ; [#uses=1] +int %test1(uint %mode.0.i.0) { + %tmp.79 = cast uint %mode.0.i.0 to short + %tmp.80 = cast short %tmp.79 to int + %tmp.81 = and int %tmp.80, 24 ret int %tmp.81 } + +short %test2(short %X, short %x) { + %tmp = cast short %X to int + %tmp1 = cast short %x to int + %tmp2 = add int %tmp, %tmp1 + %tmp4 = shr int %tmp2, ubyte 1 + %tmp4 = cast int %tmp4 to short + %tmp45 = cast short %tmp4 to int + %retval = cast int %tmp45 to short + ret short %retval +} + From jeffc at jolt-lang.org Sat May 6 16:27:27 2006 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Sat, 6 May 2006 16:27:27 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/AsmPrinter.cpp Message-ID: <200605062127.QAA26364@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: AsmPrinter.cpp updated: 1.67 -> 1.68 --- Log message: Fix some loose ends in MASM support. --- Diffs of the changes: (+5 -5) AsmPrinter.cpp | 10 +++++----- 1 files changed, 5 insertions(+), 5 deletions(-) Index: llvm/lib/CodeGen/AsmPrinter.cpp diff -u llvm/lib/CodeGen/AsmPrinter.cpp:1.67 llvm/lib/CodeGen/AsmPrinter.cpp:1.68 --- llvm/lib/CodeGen/AsmPrinter.cpp:1.67 Fri May 5 16:47:05 2006 +++ llvm/lib/CodeGen/AsmPrinter.cpp Sat May 6 16:27:14 2006 @@ -71,9 +71,9 @@ if (MLSections) { if (*NewSection == 0) { // Simply end the current section, if any. - if (CurrentSection != "") { - O << CurrentSection << "\tends\n"; - CurrentSection = ""; + if (!CurrentSection.empty()) { + O << CurrentSection << "\tends\n\n"; + CurrentSection.clear(); } return; } @@ -88,8 +88,8 @@ NS = "_text"; if (CurrentSection != NS) { - if (CurrentSection != "") - O << CurrentSection << "\tends\n"; + if (!CurrentSection.empty()) + O << CurrentSection << "\tends\n\n"; CurrentSection = NS; O << CurrentSection << (isData ? "\tsegment 'DATA'\n" : "\tsegment 'CODE'\n"); From jeffc at jolt-lang.org Sat May 6 16:27:27 2006 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Sat, 6 May 2006 16:27:27 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86AsmPrinter.cpp X86IntelAsmPrinter.cpp Message-ID: <200605062127.QAA26360@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86AsmPrinter.cpp updated: 1.178 -> 1.179 X86IntelAsmPrinter.cpp updated: 1.42 -> 1.43 --- Log message: Fix some loose ends in MASM support. --- Diffs of the changes: (+72 -60) X86AsmPrinter.cpp | 3 + X86IntelAsmPrinter.cpp | 129 ++++++++++++++++++++++++++----------------------- 2 files changed, 72 insertions(+), 60 deletions(-) Index: llvm/lib/Target/X86/X86AsmPrinter.cpp diff -u llvm/lib/Target/X86/X86AsmPrinter.cpp:1.178 llvm/lib/Target/X86/X86AsmPrinter.cpp:1.179 --- llvm/lib/Target/X86/X86AsmPrinter.cpp:1.178 Fri May 5 16:48:50 2006 +++ llvm/lib/Target/X86/X86AsmPrinter.cpp Sat May 6 16:27:14 2006 @@ -90,6 +90,9 @@ } bool X86SharedAsmPrinter::doFinalization(Module &M) { + // Note: this code is not shared by the Intel printer as it is too different + // from how MASM does things. When making changes here don't forget to look + // at X86IntelAsmPrinter::doFinalization(). const TargetData *TD = TM.getTargetData(); // Print out module-level global variables here. Index: llvm/lib/Target/X86/X86IntelAsmPrinter.cpp diff -u llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.42 llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.43 --- llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.42 Fri May 5 00:40:20 2006 +++ llvm/lib/Target/X86/X86IntelAsmPrinter.cpp Sat May 6 16:27:14 2006 @@ -30,12 +30,6 @@ /// method to print assembly for each instruction. /// bool X86IntelAsmPrinter::runOnMachineFunction(MachineFunction &MF) { - if (forDarwin) { - // Let PassManager know we need debug information and relay - // the MachineDebugInfo address on to DwarfWriter. - DW.SetDebugInfo(&getAnalysis()); - } - SetupMachineFunction(MF); O << "\n\n"; @@ -49,11 +43,6 @@ O << "\tpublic " << CurrentFnName << "\n"; O << CurrentFnName << "\tproc near\n"; - if (forDarwin) { - // Emit pre-function debug information. - DW.BeginFunction(&MF); - } - // Print out code for the function. for (MachineFunction::const_iterator I = MF.begin(), E = MF.end(); I != E; ++I) { @@ -70,11 +59,6 @@ } } - if (forDarwin) { - // Emit post-function debug information. - DW.EndFunction(); - } - O << CurrentFnName << "\tendp\n"; // We didn't modify anything. @@ -124,8 +108,6 @@ if (!isMemOp) O << "OFFSET "; O << "[" << PrivateGlobalPrefix << "CPI" << getFunctionNumber() << "_" << MO.getConstantPoolIndex(); - if (forDarwin && TM.getRelocationModel() == Reloc::PIC) - O << "-\"L" << getFunctionNumber() << "$pb\""; int Offset = MO.getOffset(); if (Offset > 0) O << " + " << Offset; @@ -138,29 +120,7 @@ bool isCallOp = Modifier && !strcmp(Modifier, "call"); bool isMemOp = Modifier && !strcmp(Modifier, "mem"); if (!isMemOp && !isCallOp) O << "OFFSET "; - if (forDarwin && TM.getRelocationModel() != Reloc::Static) { - GlobalValue *GV = MO.getGlobal(); - std::string Name = Mang->getValueName(GV); - if (!isMemOp && !isCallOp) O << '$'; - // Link-once, External, or Weakly-linked global variables need - // non-lazily-resolved stubs - if (GV->isExternal() || GV->hasWeakLinkage() || - GV->hasLinkOnceLinkage()) { - // Dynamically-resolved functions need a stub for the function. - if (isCallOp && isa(GV) && cast(GV)->isExternal()) { - FnStubs.insert(Name); - O << "L" << Name << "$stub"; - } else { - GVStubs.insert(Name); - O << "L" << Name << "$non_lazy_ptr"; - } - } else { - O << Mang->getValueName(GV); - } - if (!isCallOp && TM.getRelocationModel() == Reloc::PIC) - O << "-\"L" << getFunctionNumber() << "$pb\""; - } else - O << Mang->getValueName(MO.getGlobal()); + O << Mang->getValueName(MO.getGlobal()); int Offset = MO.getOffset(); if (Offset > 0) O << " + " << Offset; @@ -170,13 +130,6 @@ } case MachineOperand::MO_ExternalSymbol: { bool isCallOp = Modifier && !strcmp(Modifier, "call"); - if (isCallOp && forDarwin && TM.getRelocationModel() != Reloc::Static) { - std::string Name(GlobalPrefix); - Name += MO.getSymbolName(); - FnStubs.insert(Name); - O << "L" << Name << "$stub"; - return; - } if (!isCallOp) O << "OFFSET "; O << GlobalPrefix << MO.getSymbolName(); return; @@ -330,20 +283,22 @@ } bool X86IntelAsmPrinter::doInitialization(Module &M) { - X86SharedAsmPrinter::doInitialization(M); - CommentString = ";"; + MLSections = true; GlobalPrefix = "_"; + CommentString = ";"; + + X86SharedAsmPrinter::doInitialization(M); + PrivateGlobalPrefix = "$"; AlignDirective = "\talign\t"; - MLSections = true; ZeroDirective = "\tdb\t"; ZeroDirectiveSuffix = " dup(0)"; AsciiDirective = "\tdb\t"; AscizDirective = 0; - Data8bitsDirective = "\t.db\t"; - Data16bitsDirective = "\t.dw\t"; - Data32bitsDirective = "\t.dd\t"; - Data64bitsDirective = "\t.dq\t"; + Data8bitsDirective = "\tdb\t"; + Data16bitsDirective = "\tdw\t"; + Data32bitsDirective = "\tdd\t"; + Data64bitsDirective = "\tdq\t"; HasDotTypeDotSizeDirective = false; Mang->markCharUnacceptable('.'); @@ -354,23 +309,77 @@ if (I->isExternal()) O << "\textern " << Mang->getValueName(I) << ":near\n"; - // Emit declarations for external globals. + // Emit declarations for external globals. Note that VC++ always declares + // external globals to have type byte, and if that's good enough for VC++... for (Module::const_global_iterator I = M.global_begin(), E = M.global_end(); I != E; ++I) { if (I->isExternal()) O << "\textern " << Mang->getValueName(I) << ":byte\n"; - else if (I->getLinkage() == GlobalValue::ExternalLinkage) - O << "\tpublic " << Mang->getValueName(I) << "\n"; } return false; } bool X86IntelAsmPrinter::doFinalization(Module &M) { - X86SharedAsmPrinter::doFinalization(M); + const TargetData *TD = TM.getTargetData(); + + // Print out module-level global variables here. + for (Module::const_global_iterator I = M.global_begin(), E = M.global_end(); + I != E; ++I) { + if (I->isExternal()) continue; // External global require no code + + // Check to see if this is a special global used by LLVM, if so, emit it. + if (EmitSpecialLLVMGlobal(I)) + continue; + + std::string name = Mang->getValueName(I); + Constant *C = I->getInitializer(); + unsigned Size = TD->getTypeSize(C->getType()); + unsigned Align = getPreferredAlignmentLog(I); + bool bCustomSegment = false; + + switch (I->getLinkage()) { + case GlobalValue::LinkOnceLinkage: + case GlobalValue::WeakLinkage: + SwitchSection("", 0); + O << name << "?\tsegment common 'COMMON'\n"; + bCustomSegment = true; + // FIXME: the default alignment is 16 bytes, but 1, 2, 4, and 256 + // are also available. + break; + case GlobalValue::AppendingLinkage: + SwitchSection("", 0); + O << name << "?\tsegment public 'DATA'\n"; + bCustomSegment = true; + // FIXME: the default alignment is 16 bytes, but 1, 2, 4, and 256 + // are also available. + break; + case GlobalValue::ExternalLinkage: + O << "\tpublic " << name << "\n"; + // FALL THROUGH + case GlobalValue::InternalLinkage: + SwitchSection(".data", I); + break; + default: + assert(0 && "Unknown linkage type!"); + } + + if (!bCustomSegment) + EmitAlignment(Align, I); + + O << name << ":\t\t\t\t" << CommentString << " " << I->getName() << '\n'; + + EmitGlobalConstant(C); + + if (bCustomSegment) + O << name << "?\tends\n"; + } + + // Bypass X86SharedAsmPrinter::doFinalization(). + AsmPrinter::doFinalization(M); SwitchSection("", 0); O << "\tend\n"; - return false; + return false; // success } void X86IntelAsmPrinter::EmitString(const ConstantArray *CVA) const { From lattner at cs.uiuc.edu Sat May 6 17:40:12 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 6 May 2006 17:40:12 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp Message-ID: <200605062240.RAA26673@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target: TargetLowering.cpp updated: 1.57 -> 1.58 --- Log message: Add some more simple sign bit propagation cases. --- Diffs of the changes: (+67 -27) TargetLowering.cpp | 94 +++++++++++++++++++++++++++++++++++++---------------- 1 files changed, 67 insertions(+), 27 deletions(-) Index: llvm/lib/Target/TargetLowering.cpp diff -u llvm/lib/Target/TargetLowering.cpp:1.57 llvm/lib/Target/TargetLowering.cpp:1.58 --- llvm/lib/Target/TargetLowering.cpp:1.57 Sat May 6 04:27:13 2006 +++ llvm/lib/Target/TargetLowering.cpp Sat May 6 17:39:59 2006 @@ -1010,19 +1010,7 @@ return 1; // Limit search depth. switch (Op.getOpcode()) { - default: - // Allow the target to implement this method for its nodes. - if (Op.getOpcode() >= ISD::BUILTIN_OP_END) { - case ISD::INTRINSIC_WO_CHAIN: - case ISD::INTRINSIC_W_CHAIN: - case ISD::INTRINSIC_VOID: - unsigned NumBits = ComputeNumSignBitsForTargetNode(Op, Depth); - if (NumBits > 1) return NumBits; - } - - // FIXME: Should use computemaskedbits to look at the top bits. - return 1; - + default: break; case ISD::AssertSext: Tmp = MVT::getSizeInBits(cast(Op.getOperand(1))->getVT()); return VTBits-Tmp+1; @@ -1030,6 +1018,31 @@ Tmp = MVT::getSizeInBits(cast(Op.getOperand(1))->getVT()); return VTBits-Tmp; + case ISD::SEXTLOAD: // '17' bits known + Tmp = MVT::getSizeInBits(cast(Op.getOperand(3))->getVT()); + return VTBits-Tmp+1; + case ISD::ZEXTLOAD: // '16' bits known + Tmp = MVT::getSizeInBits(cast(Op.getOperand(3))->getVT()); + return VTBits-Tmp; + + case ISD::Constant: { + uint64_t Val = cast(Op)->getValue(); + // If negative, invert the bits, then look at it. + if (Val & MVT::getIntVTSignBit(VT)) + Val = ~Val; + + // Shift the bits so they are the leading bits in the int64_t. + Val <<= 64-VTBits; + + // Return # leading zeros. We use 'min' here in case Val was zero before + // shifting. We don't want to return '64' as for an i32 "0". + return std::min(VTBits, CountLeadingZeros_64(Val)); + } + + case ISD::SIGN_EXTEND: + Tmp = VTBits-MVT::getSizeInBits(Op.getOperand(0).getValueType()); + return ComputeNumSignBits(Op.getOperand(0), Depth+1) + Tmp; + case ISD::SIGN_EXTEND_INREG: // Max of the input and what this extends. Tmp = MVT::getSizeInBits(cast(Op.getOperand(1))->getVT()); @@ -1046,31 +1059,58 @@ if (Tmp > VTBits) Tmp = VTBits; } return Tmp; - + case ISD::SHL: + if (ConstantSDNode *C = dyn_cast(Op.getOperand(1))) { + // shl destroys sign bits. + Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); + if (C->getValue() >= VTBits || // Bad shift. + C->getValue() >= Tmp) break; // Shifted all sign bits out. + return Tmp - C->getValue(); + } + break; case ISD::ADD: case ISD::SUB: // Add and sub can have at most one carry bit. Thus we know that the output // is, at worst, one more bit than the inputs. Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); - if (Tmp == 1) return 1; + if (Tmp == 1) return 1; // Early out. Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); if (Tmp2 == 1) return 1; return std::min(Tmp, Tmp2)-1; - //case ISD::ZEXTLOAD: // 16 bits known - //case ISD::SEXTLOAD: // 17 bits known - //case ISD::Constant: - //case ISD::SIGN_EXTEND: - // + case ISD::AND: + case ISD::OR: + case ISD::XOR: // NOT is handled here. + // Logical binary ops preserve the number of sign bits. + Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); + if (Tmp == 1) return 1; // Early out. + Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); + return std::min(Tmp, Tmp2); + + case ISD::SELECT: + Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); + if (Tmp == 1) return 1; // Early out. + Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); + return std::min(Tmp, Tmp2); + + case ISD::SETCC: + // If setcc returns 0/-1, all bits are sign bits. + if (getSetCCResultContents() == ZeroOrNegativeOneSetCCResult) + return VTBits; + break; } -#if 0 - // fold (sext_in_reg (setcc x)) -> setcc x iff (setcc x) == 0 or -1 - if (N0.getOpcode() == ISD::SETCC && - TLI.getSetCCResultContents() == - TargetLowering::ZeroOrNegativeOneSetCCResult) - return N0; -#endif + // Allow the target to implement this method for its nodes. + if (Op.getOpcode() >= ISD::BUILTIN_OP_END || + Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || + Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || + Op.getOpcode() == ISD::INTRINSIC_VOID) { + unsigned NumBits = ComputeNumSignBitsForTargetNode(Op, Depth); + if (NumBits > 1) return NumBits; + } + + // FIXME: Should use computemaskedbits to look at the top bits. + return 1; } From lattner at cs.uiuc.edu Sat May 6 17:43:56 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 6 May 2006 17:43:56 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <200605062243.RAA26738@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.160 -> 1.161 --- Log message: remove cases handled elsewhere --- Diffs of the changes: (+2 -16) DAGCombiner.cpp | 18 ++---------------- 1 files changed, 2 insertions(+), 16 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.160 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.161 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.160 Sat May 6 04:30:03 2006 +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sat May 6 17:43:44 2006 @@ -1938,30 +1938,16 @@ return DAG.getNode(ISD::SIGN_EXTEND, VT, Truncate); } - // If the input is already sign extended, just drop the extend. + // If the input is already sign extended, just drop the extension. if (TLI.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1) return N0; - // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt1 - if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && - cast(N0.getOperand(1))->getVT() <= EVT) { - return N0; - } // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && EVT < cast(N0.getOperand(1))->getVT()) { return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); } - // fold (sext_in_reg (sextload x)) -> (sextload x) - if (N0.getOpcode() == ISD::SEXTLOAD && - cast(N0.getOperand(3))->getVT() <= EVT) { - return N0; - } - // fold (sext_in_reg (setcc x)) -> setcc x iff (setcc x) == 0 or -1 - if (N0.getOpcode() == ISD::SETCC && - TLI.getSetCCResultContents() == - TargetLowering::ZeroOrNegativeOneSetCCResult) - return N0; + // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1))) return DAG.getZeroExtendInReg(N0, EVT); From lattner at cs.uiuc.edu Sat May 6 18:05:53 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 6 May 2006 18:05:53 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Message-ID: <200605062305.SAA26915@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAG.cpp updated: 1.303 -> 1.304 --- Log message: constant fold sign_extend_inreg --- Diffs of the changes: (+9 -1) SelectionDAG.cpp | 10 +++++++++- 1 files changed, 9 insertions(+), 1 deletion(-) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.303 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.304 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.303 Thu Apr 27 00:01:07 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Sat May 6 18:05:41 2006 @@ -1335,6 +1335,14 @@ ConstantSDNode *N1C = dyn_cast(N1.Val); ConstantSDNode *N2C = dyn_cast(N2.Val); if (N1C) { + if (Opcode == ISD::SIGN_EXTEND_INREG) { + int64_t Val = N1C->getValue(); + unsigned FromBits = MVT::getSizeInBits(cast(N2)->getVT()); + Val <<= 64-FromBits; + Val >>= 64-FromBits; + return getConstant(Val, VT); + } + if (N2C) { uint64_t C1 = N1C->getValue(), C2 = N2C->getValue(); switch (Opcode) { @@ -1441,7 +1449,7 @@ } } - // Fold a bunch of operators that + // Fold a bunch of operators when the RHS is undef. if (N2.getOpcode() == ISD::UNDEF) { switch (Opcode) { case ISD::ADD: From lattner at cs.uiuc.edu Sat May 6 18:06:39 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 6 May 2006 18:06:39 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <200605062306.SAA26972@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.161 -> 1.162 --- Log message: Simplify some code, add a couple minor missed folds --- Diffs of the changes: (+16 -21) DAGCombiner.cpp | 37 ++++++++++++++++--------------------- 1 files changed, 16 insertions(+), 21 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.161 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.162 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.161 Sat May 6 17:43:44 2006 +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sat May 6 18:06:26 2006 @@ -1664,33 +1664,30 @@ SDOperand DAGCombiner::visitCTLZ(SDNode *N) { SDOperand N0 = N->getOperand(0); - ConstantSDNode *N0C = dyn_cast(N0); MVT::ValueType VT = N->getValueType(0); // fold (ctlz c1) -> c2 - if (N0C) + if (isa(N0)) return DAG.getNode(ISD::CTLZ, VT, N0); return SDOperand(); } SDOperand DAGCombiner::visitCTTZ(SDNode *N) { SDOperand N0 = N->getOperand(0); - ConstantSDNode *N0C = dyn_cast(N0); MVT::ValueType VT = N->getValueType(0); // fold (cttz c1) -> c2 - if (N0C) + if (isa(N0)) return DAG.getNode(ISD::CTTZ, VT, N0); return SDOperand(); } SDOperand DAGCombiner::visitCTPOP(SDNode *N) { SDOperand N0 = N->getOperand(0); - ConstantSDNode *N0C = dyn_cast(N0); MVT::ValueType VT = N->getValueType(0); // fold (ctpop c1) -> c2 - if (N0C) + if (isa(N0)) return DAG.getNode(ISD::CTPOP, VT, N0); return SDOperand(); } @@ -1790,21 +1787,24 @@ SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { SDOperand N0 = N->getOperand(0); - ConstantSDNode *N0C = dyn_cast(N0); MVT::ValueType VT = N->getValueType(0); // fold (sext c1) -> c1 - if (N0C) + if (ConstantSDNode *N0C = dyn_cast(N0)) return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); + // fold (sext (sext x)) -> (sext x) - if (N0.getOpcode() == ISD::SIGN_EXTEND) + // fold (sext (aext x)) -> (sext x) + if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); + // fold (sext (truncate x)) -> (sextinreg x) iff x size == sext size. if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&& (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, N0.getValueType()))) return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), DAG.getValueType(N0.getValueType())); + // fold (sext (load x)) -> (sext (truncate (sextload x))) if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() && (!AfterLegalize||TLI.isOperationLegal(ISD::SEXTLOAD, N0.getValueType()))){ @@ -1835,14 +1835,14 @@ SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { SDOperand N0 = N->getOperand(0); - ConstantSDNode *N0C = dyn_cast(N0); MVT::ValueType VT = N->getValueType(0); // fold (zext c1) -> c1 - if (N0C) + if (ConstantSDNode *N0C = dyn_cast(N0)) return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); // fold (zext (zext x)) -> (zext x) - if (N0.getOpcode() == ISD::ZERO_EXTEND) + // fold (zext (aext x)) -> (zext x) + if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); // fold (zext (truncate x)) -> (zextinreg x) iff x size == zext size. if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&& @@ -1877,11 +1877,10 @@ SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) { SDOperand N0 = N->getOperand(0); - ConstantSDNode *N0C = dyn_cast(N0); MVT::ValueType VT = N->getValueType(0); // fold (aext c1) -> c1 - if (N0C) + if (isa(N0)) return DAG.getNode(ISD::ANY_EXTEND, VT, N0); // fold (aext (aext x)) -> (aext x) // fold (aext (zext x)) -> (zext x) @@ -1927,16 +1926,13 @@ SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { SDOperand N0 = N->getOperand(0); SDOperand N1 = N->getOperand(1); - ConstantSDNode *N0C = dyn_cast(N0); MVT::ValueType VT = N->getValueType(0); MVT::ValueType EVT = cast(N1)->getVT(); unsigned EVTBits = MVT::getSizeInBits(EVT); // fold (sext_in_reg c1) -> c1 - if (N0C) { - SDOperand Truncate = DAG.getConstant(N0C->getValue(), EVT); - return DAG.getNode(ISD::SIGN_EXTEND, VT, Truncate); - } + if (isa(N0)) + return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); // If the input is already sign extended, just drop the extension. if (TLI.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1) @@ -1978,14 +1974,13 @@ SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { SDOperand N0 = N->getOperand(0); - ConstantSDNode *N0C = dyn_cast(N0); MVT::ValueType VT = N->getValueType(0); // noop truncate if (N0.getValueType() == N->getValueType(0)) return N0; // fold (truncate c1) -> c1 - if (N0C) + if (isa(N0)) return DAG.getNode(ISD::TRUNCATE, VT, N0); // fold (truncate (truncate x)) -> (truncate x) if (N0.getOpcode() == ISD::TRUNCATE) From jeffc at jolt-lang.org Sat May 6 18:26:06 2006 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Sat, 6 May 2006 18:26:06 -0500 Subject: [llvm-commits] CVS: llvm/lib/Bytecode/Archive/Archive.cpp Message-ID: <200605062326.SAA27847@zion.cs.uiuc.edu> Changes in directory llvm/lib/Bytecode/Archive: Archive.cpp updated: 1.10 -> 1.11 --- Log message: Apply bug fix supplied by Greg Pettyjohn for a bug he found: '' is not a legal path on Windows. --- Diffs of the changes: (+1 -1) Archive.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Bytecode/Archive/Archive.cpp diff -u llvm/lib/Bytecode/Archive/Archive.cpp:1.10 llvm/lib/Bytecode/Archive/Archive.cpp:1.11 --- llvm/lib/Bytecode/Archive/Archive.cpp:1.10 Tue Nov 29 23:21:10 2005 +++ llvm/lib/Bytecode/Archive/Archive.cpp Sat May 6 18:25:53 2006 @@ -39,7 +39,7 @@ // This default constructor is only use by the ilist when it creates its // sentry node. We give it specific static values to make it stand out a bit. ArchiveMember::ArchiveMember() - : next(0), prev(0), parent(0), path(""), flags(0), data(0) + : next(0), prev(0), parent(0), path("--invalid--"), flags(0), data(0) { info.user = sys::Process::GetCurrentUserId(); info.group = sys::Process::GetCurrentGroupId(); From lattner at cs.uiuc.edu Sat May 6 18:40:42 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 6 May 2006 18:40:42 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp Message-ID: <200605062340.SAA28828@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target: TargetLowering.cpp updated: 1.58 -> 1.59 --- Log message: Add some more sign propagation cases --- Diffs of the changes: (+77 -10) TargetLowering.cpp | 87 ++++++++++++++++++++++++++++++++++++++++++++++------- 1 files changed, 77 insertions(+), 10 deletions(-) Index: llvm/lib/Target/TargetLowering.cpp diff -u llvm/lib/Target/TargetLowering.cpp:1.58 llvm/lib/Target/TargetLowering.cpp:1.59 --- llvm/lib/Target/TargetLowering.cpp:1.58 Sat May 6 17:39:59 2006 +++ llvm/lib/Target/TargetLowering.cpp Sat May 6 18:40:29 2006 @@ -1068,16 +1068,6 @@ return Tmp - C->getValue(); } break; - case ISD::ADD: - case ISD::SUB: - // Add and sub can have at most one carry bit. Thus we know that the output - // is, at worst, one more bit than the inputs. - Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); - if (Tmp == 1) return 1; // Early out. - Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); - if (Tmp2 == 1) return 1; - return std::min(Tmp, Tmp2)-1; - case ISD::AND: case ISD::OR: case ISD::XOR: // NOT is handled here. @@ -1098,6 +1088,83 @@ if (getSetCCResultContents() == ZeroOrNegativeOneSetCCResult) return VTBits; break; + case ISD::ROTL: + case ISD::ROTR: + if (ConstantSDNode *C = dyn_cast(Op.getOperand(1))) { + unsigned RotAmt = C->getValue() & (VTBits-1); + + // Handle rotate right by N like a rotate left by 32-N. + if (Op.getOpcode() == ISD::ROTR) + RotAmt = (VTBits-RotAmt) & (VTBits-1); + + // If we aren't rotating out all of the known-in sign bits, return the + // number that are left. This handles rotl(sext(x), 1) for example. + Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); + if (Tmp > RotAmt+1) return Tmp-RotAmt; + } + break; + case ISD::ADD: + // Add can have at most one carry bit. Thus we know that the output + // is, at worst, one more bit than the inputs. + Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); + if (Tmp == 1) return 1; // Early out. + + // Special case decrementing a value (ADD X, -1): + if (ConstantSDNode *CRHS = dyn_cast(Op.getOperand(0))) + if (CRHS->isAllOnesValue()) { + uint64_t KnownZero, KnownOne; + uint64_t Mask = MVT::getIntVTBitMask(VT); + ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); + + // If the input is known to be 0 or 1, the output is 0/-1, which is all + // sign bits set. + if ((KnownZero|1) == Mask) + return VTBits; + + // If we are subtracting one from a positive number, there is no carry + // out of the result. + if (KnownZero & MVT::getIntVTSignBit(VT)) + return Tmp; + } + + Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); + if (Tmp2 == 1) return 1; + return std::min(Tmp, Tmp2)-1; + break; + + case ISD::SUB: + Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); + if (Tmp2 == 1) return 1; + + // Handle NEG. + if (ConstantSDNode *CLHS = dyn_cast(Op.getOperand(0))) + if (CLHS->getValue() == 0) { + uint64_t KnownZero, KnownOne; + uint64_t Mask = MVT::getIntVTBitMask(VT); + ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); + // If the input is known to be 0 or 1, the output is 0/-1, which is all + // sign bits set. + if ((KnownZero|1) == Mask) + return VTBits; + + // If the input is known to be positive (the sign bit is known clear), + // the output of the NEG has the same number of sign bits as the input. + if (KnownZero & MVT::getIntVTSignBit(VT)) + return Tmp2; + + // Otherwise, we treat this like a SUB. + } + + // Sub can have at most one carry bit. Thus we know that the output + // is, at worst, one more bit than the inputs. + Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); + if (Tmp == 1) return 1; // Early out. + return std::min(Tmp, Tmp2)-1; + break; + case ISD::TRUNCATE: + // FIXME: it's tricky to do anything useful for this, but it is an important + // case for targets like X86. + break; } // Allow the target to implement this method for its nodes. From lattner at cs.uiuc.edu Sat May 6 18:48:26 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 6 May 2006 18:48:26 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp Message-ID: <200605062348.SAA29632@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target: TargetLowering.cpp updated: 1.59 -> 1.60 --- Log message: Use ComputeMaskedBits to determine # sign bits as a fallback. This allows us to handle all kinds of stuff, including silly things like: sextinreg(setcc,i16) -> setcc. --- Diffs of the changes: (+23 -2) TargetLowering.cpp | 25 +++++++++++++++++++++++-- 1 files changed, 23 insertions(+), 2 deletions(-) Index: llvm/lib/Target/TargetLowering.cpp diff -u llvm/lib/Target/TargetLowering.cpp:1.59 llvm/lib/Target/TargetLowering.cpp:1.60 --- llvm/lib/Target/TargetLowering.cpp:1.59 Sat May 6 18:40:29 2006 +++ llvm/lib/Target/TargetLowering.cpp Sat May 6 18:48:13 2006 @@ -1176,8 +1176,29 @@ if (NumBits > 1) return NumBits; } - // FIXME: Should use computemaskedbits to look at the top bits. - return 1; + // Finally, if we can prove that the top bits of the result are 0's or 1's, + // use this information. + uint64_t KnownZero, KnownOne; + uint64_t Mask = MVT::getIntVTBitMask(VT); + ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); + + uint64_t SignBit = MVT::getIntVTSignBit(VT); + if (KnownZero & SignBit) { // SignBit is 0 + Mask = KnownZero; + } else if (KnownOne & SignBit) { // SignBit is 1; + Mask = KnownOne; + } else { + // Nothing known. + return 1; + } + + // Okay, we know that the sign bit in Mask is set. Use CLZ to determine + // the number of identical bits in the top of the input value. + Mask ^= ~0ULL; + Mask <<= 64-VTBits; + // Return # leading zeros. We use 'min' here in case Val was zero before + // shifting. We don't want to return '64' as for an i32 "0". + return std::min(VTBits, CountLeadingZeros_64(Mask)); } From natebegeman at mac.com Sat May 6 19:23:51 2006 From: natebegeman at mac.com (Nate Begeman) Date: Sat, 6 May 2006 19:23:51 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Message-ID: <200605070023.TAA30389@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelDAGToDAG.cpp updated: 1.180 -> 1.181 --- Log message: New rlwimi implementation, which is superior to the old one. There are still a couple missed optimizations, but we now generate all the possible rlwimis for multiple inserts into the same bitfield. More regression tests to come. --- Diffs of the changes: (+47 -88) PPCISelDAGToDAG.cpp | 135 ++++++++++++++++++---------------------------------- 1 files changed, 47 insertions(+), 88 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.180 llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.181 --- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.180 Sat Apr 22 13:53:45 2006 +++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Sat May 6 19:23:38 2006 @@ -391,15 +391,7 @@ /// SelectBitfieldInsert - turn an or of two masked values into /// the rotate left word immediate then mask insert (rlwimi) instruction. -/// Returns true on success, false if the caller still needs to select OR. -/// -/// Patterns matched: -/// 1. or shl, and 5. or and, and -/// 2. or and, shl 6. or shl, shr -/// 3. or shr, and 7. or shr, shl -/// 4. or and, shr SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) { - bool IsRotate = false; unsigned TgtMask = 0xFFFFFFFF, InsMask = 0xFFFFFFFF, SH = 0; unsigned Value; @@ -409,90 +401,57 @@ unsigned Op0Opc = Op0.getOpcode(); unsigned Op1Opc = Op1.getOpcode(); - // Verify that we have the correct opcodes - if (ISD::SHL != Op0Opc && ISD::SRL != Op0Opc && ISD::AND != Op0Opc) - return false; - if (ISD::SHL != Op1Opc && ISD::SRL != Op1Opc && ISD::AND != Op1Opc) - return false; - - // Generate Mask value for Target - if (isIntImmediate(Op0.getOperand(1), Value)) { - switch(Op0Opc) { - case ISD::SHL: TgtMask <<= Value; break; - case ISD::SRL: TgtMask >>= Value; break; - case ISD::AND: TgtMask &= Value; break; + uint64_t LKZ, LKO, RKZ, RKO; + TLI.ComputeMaskedBits(Op0, TgtMask, LKZ, LKO); + TLI.ComputeMaskedBits(Op1, TgtMask, RKZ, RKO); + + // FIXME: rotrwi / rotlwi + if ((LKZ | RKZ) == 0x00000000FFFFFFFFULL) { + unsigned PInsMask = ~RKZ; + unsigned PTgtMask = ~LKZ; + + // If the LHS has a foldable shift, then swap it to the RHS so that we can + // fold the shift into the insert. + if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) { + if (Op0.getOperand(0).getOpcode() == ISD::SHL || + Op0.getOperand(0).getOpcode() == ISD::SRL) { + if (Op1.getOperand(0).getOpcode() != ISD::SHL && + Op1.getOperand(0).getOpcode() != ISD::SRL) { + std::swap(Op0, Op1); + std::swap(Op0Opc, Op1Opc); + std::swap(PInsMask, PTgtMask); + } + } } - } else { - return 0; - } - - // Generate Mask value for Insert - if (!isIntImmediate(Op1.getOperand(1), Value)) - return 0; - - switch(Op1Opc) { - case ISD::SHL: - SH = Value; - InsMask <<= SH; - if (Op0Opc == ISD::SRL) IsRotate = true; - break; - case ISD::SRL: - SH = Value; - InsMask >>= SH; - SH = 32-SH; - if (Op0Opc == ISD::SHL) IsRotate = true; - break; - case ISD::AND: - InsMask &= Value; - break; - } - - // If both of the inputs are ANDs and one of them has a logical shift by - // constant as its input, make that AND the inserted value so that we can - // combine the shift into the rotate part of the rlwimi instruction - bool IsAndWithShiftOp = false; - if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) { - if (Op1.getOperand(0).getOpcode() == ISD::SHL || - Op1.getOperand(0).getOpcode() == ISD::SRL) { - if (isIntImmediate(Op1.getOperand(0).getOperand(1), Value)) { - SH = Op1.getOperand(0).getOpcode() == ISD::SHL ? Value : 32 - Value; - IsAndWithShiftOp = true; - } - } else if (Op0.getOperand(0).getOpcode() == ISD::SHL || - Op0.getOperand(0).getOpcode() == ISD::SRL) { - if (isIntImmediate(Op0.getOperand(0).getOperand(1), Value)) { - std::swap(Op0, Op1); - std::swap(TgtMask, InsMask); - SH = Op1.getOperand(0).getOpcode() == ISD::SHL ? Value : 32 - Value; - IsAndWithShiftOp = true; + + unsigned MB, ME; + if (isRunOfOnes(PInsMask, MB, ME)) { + SDOperand Tmp1, Tmp2, Tmp3; + bool DisjointMask = (PTgtMask ^ PInsMask) == 0xFFFFFFFF; + + if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) && + isIntImmediate(Op1.getOperand(1), Value)) { + Op1 = Op1.getOperand(0); + SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value; + } + if (Op1Opc == ISD::AND) { + unsigned SHOpc = Op1.getOperand(0).getOpcode(); + if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) && + isIntImmediate(Op1.getOperand(0).getOperand(1), Value)) { + Op1 = Op1.getOperand(0).getOperand(0); + SH = (SHOpc == ISD::SHL) ? Value : 32 - Value; + } else { + Op1 = Op1.getOperand(0); + } } + + Tmp3 = (Op0Opc == ISD::AND && DisjointMask) ? Op0.getOperand(0) : Op0; + Select(Tmp1, Tmp3); + Select(Tmp2, Op1); + return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Tmp1, Tmp2, + getI32Imm(SH), getI32Imm(MB), getI32Imm(ME)); } } - - // Verify that the Target mask and Insert mask together form a full word mask - // and that the Insert mask is a run of set bits (which implies both are runs - // of set bits). Given that, Select the arguments and generate the rlwimi - // instruction. - unsigned MB, ME; - if (((TgtMask & InsMask) == 0) && isRunOfOnes(InsMask, MB, ME)) { - bool fullMask = (TgtMask ^ InsMask) == 0xFFFFFFFF; - bool Op0IsAND = Op0Opc == ISD::AND; - // Check for rotlwi / rotrwi here, a special case of bitfield insert - // where both bitfield halves are sourced from the same value. - if (IsRotate && fullMask && - N->getOperand(0).getOperand(0) == N->getOperand(1).getOperand(0)) { - SDOperand Tmp; - Select(Tmp, N->getOperand(0).getOperand(0)); - return CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Tmp, - getI32Imm(SH), getI32Imm(0), getI32Imm(31)); - } - SDOperand Tmp1, Tmp2; - Select(Tmp1, ((Op0IsAND && fullMask) ? Op0.getOperand(0) : Op0)); - Select(Tmp2, (IsAndWithShiftOp ? Op1.getOperand(0).getOperand(0) - : Op1.getOperand(0))); - return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Tmp1, Tmp2, - getI32Imm(SH), getI32Imm(MB), getI32Imm(ME)); - } return 0; } From jeffc at jolt-lang.org Sat May 6 21:52:03 2006 From: jeffc at jolt-lang.org (Jeff Cohen) Date: Sat, 6 May 2006 21:52:03 -0500 Subject: [llvm-commits] CVS: llvm/lib/System/Win32/Path.inc Message-ID: <200605070252.VAA32348@zion.cs.uiuc.edu> Changes in directory llvm/lib/System/Win32: Path.inc updated: 1.41 -> 1.42 --- Log message: Unlike Unix, Windows won't let a file be implicitly replaced via renaming without explicit permission. --- Diffs of the changes: (+1 -1) Path.inc | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/System/Win32/Path.inc diff -u llvm/lib/System/Win32/Path.inc:1.41 llvm/lib/System/Win32/Path.inc:1.42 --- llvm/lib/System/Win32/Path.inc:1.41 Sat Apr 29 13:41:44 2006 +++ llvm/lib/System/Win32/Path.inc Sat May 6 21:51:51 2006 @@ -682,7 +682,7 @@ bool Path::renamePathOnDisk(const Path& newName) { - if (!MoveFile(path.c_str(), newName.c_str())) + if (!MoveFileEx(path.c_str(), newName.c_str(), MOVEFILE_REPLACE_EXISTING)) ThrowError("Can't move '" + path + "' to '" + newName.path + "': "); return true; From evan.cheng at apple.com Sun May 7 05:10:44 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Sun, 7 May 2006 05:10:44 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.td Message-ID: <200605071010.FAA32115@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86RegisterInfo.td updated: 1.32 -> 1.33 --- Log message: Typo's --- Diffs of the changes: (+2 -2) X86RegisterInfo.td | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/Target/X86/X86RegisterInfo.td diff -u llvm/lib/Target/X86/X86RegisterInfo.td:1.32 llvm/lib/Target/X86/X86RegisterInfo.td:1.33 --- llvm/lib/Target/X86/X86RegisterInfo.td:1.32 Fri Mar 24 15:15:58 2006 +++ llvm/lib/Target/X86/X86RegisterInfo.td Sun May 7 05:10:20 2006 @@ -47,8 +47,8 @@ def AL : RegisterGroup<"AL", [AX,EAX]>, DwarfRegNum<0>; def CL : RegisterGroup<"CL", [CX,ECX]>, DwarfRegNum<2>; def DL : RegisterGroup<"DL", [DX,EDX]>, DwarfRegNum<1>; - def BL : RegisterGroup<"BL", [BX,EBX]>, DwarfRegNum<0>; - def AH : RegisterGroup<"AH", [AX,EAX]>, DwarfRegNum<2>; + def BL : RegisterGroup<"BL", [BX,EBX]>, DwarfRegNum<3>; + def AH : RegisterGroup<"AH", [AX,EAX]>, DwarfRegNum<0>; def CH : RegisterGroup<"CH", [CX,ECX]>, DwarfRegNum<2>; def DH : RegisterGroup<"DH", [DX,EDX]>, DwarfRegNum<1>; def BH : RegisterGroup<"BH", [BX,EBX]>, DwarfRegNum<3>; From lattner at cs.uiuc.edu Sun May 7 13:16:44 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sun, 7 May 2006 13:16:44 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/InstCombine/narrow.ll Message-ID: <200605071816.NAA07993@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/Transforms/InstCombine: narrow.ll updated: 1.1 -> 1.2 --- Log message: This test passes now, remove xfail marker Change test to be a positive test instead of a negative test --- Diffs of the changes: (+1 -2) narrow.ll | 3 +-- 1 files changed, 1 insertion(+), 2 deletions(-) Index: llvm/test/Regression/Transforms/InstCombine/narrow.ll diff -u llvm/test/Regression/Transforms/InstCombine/narrow.ll:1.1 llvm/test/Regression/Transforms/InstCombine/narrow.ll:1.2 --- llvm/test/Regression/Transforms/InstCombine/narrow.ll:1.1 Sat Feb 11 20:02:43 2006 +++ llvm/test/Regression/Transforms/InstCombine/narrow.ll Sun May 7 13:16:31 2006 @@ -1,8 +1,7 @@ ; This file contains various testcases that check to see that instcombine ; is narrowing computations when possible. -; RUN: llvm-as < %s | opt -instcombine | llvm-dis | not grep %ELIM -; XFAIL: * +; RUN: llvm-as < %s | opt -instcombine | llvm-dis | grep 'ret bool false' ; test1 - Eliminating the casts in this testcase (by narrowing the AND ; operation) allows instcombine to realize the function always returns false. From natebegeman at mac.com Sun May 7 20:33:23 2006 From: natebegeman at mac.com (Nate Begeman) Date: Sun, 7 May 2006 20:33:23 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGISel.h Message-ID: <200605080133.UAA11497@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: SelectionDAGISel.h updated: 1.17 -> 1.18 --- Log message: Remove unncessary include --- Diffs of the changes: (+0 -1) SelectionDAGISel.h | 1 - 1 files changed, 1 deletion(-) Index: llvm/include/llvm/CodeGen/SelectionDAGISel.h diff -u llvm/include/llvm/CodeGen/SelectionDAGISel.h:1.17 llvm/include/llvm/CodeGen/SelectionDAGISel.h:1.18 --- llvm/include/llvm/CodeGen/SelectionDAGISel.h:1.17 Thu May 4 20:13:11 2006 +++ llvm/include/llvm/CodeGen/SelectionDAGISel.h Sun May 7 20:33:11 2006 @@ -18,7 +18,6 @@ #include "llvm/Pass.h" #include "llvm/Constant.h" #include "llvm/CodeGen/SelectionDAGNodes.h" -#include namespace llvm { class SelectionDAG; From natebegeman at mac.com Sun May 7 20:35:14 2006 From: natebegeman at mac.com (Nate Begeman) Date: Sun, 7 May 2006 20:35:14 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <200605080135.UAA11516@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.162 -> 1.163 --- Log message: Fix PR772: http://llvm.cs.uiuc.edu/PR772 --- Diffs of the changes: (+9 -9) DAGCombiner.cpp | 18 +++++++++--------- 1 files changed, 9 insertions(+), 9 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.162 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.163 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.162 Sat May 6 18:06:26 2006 +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sun May 7 20:35:01 2006 @@ -1821,9 +1821,9 @@ // fold (sext ( extload x)) -> (sext (truncate (sextload x))) if ((N0.getOpcode() == ISD::SEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) && N0.hasOneUse()) { - SDOperand ExtLoad = DAG.getNode(ISD::SEXTLOAD, VT, N0.getOperand(0), - N0.getOperand(1), N0.getOperand(2), - N0.getOperand(3)); + MVT::ValueType EVT = cast(N0.getOperand(3))->getVT(); + SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), + N0.getOperand(1), N0.getOperand(2), EVT); CombineTo(N, ExtLoad); CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), ExtLoad.getValue(1)); @@ -1864,9 +1864,9 @@ // fold (zext ( extload x)) -> (zext (truncate (zextload x))) if ((N0.getOpcode() == ISD::ZEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) && N0.hasOneUse()) { - SDOperand ExtLoad = DAG.getNode(ISD::ZEXTLOAD, VT, N0.getOperand(0), - N0.getOperand(1), N0.getOperand(2), - N0.getOperand(3)); + MVT::ValueType EVT = cast(N0.getOperand(3))->getVT(); + SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), + N0.getOperand(1), N0.getOperand(2), EVT); CombineTo(N, ExtLoad); CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), ExtLoad.getValue(1)); @@ -1911,9 +1911,9 @@ if ((N0.getOpcode() == ISD::ZEXTLOAD || N0.getOpcode() == ISD::EXTLOAD || N0.getOpcode() == ISD::SEXTLOAD) && N0.hasOneUse()) { - SDOperand ExtLoad = DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0), - N0.getOperand(1), N0.getOperand(2), - N0.getOperand(3)); + MVT::ValueType EVT = cast(N0.getOperand(3))->getVT(); + SDOperand ExtLoad = DAG.getExtLoad(N0.getOpcode(), VT, N0.getOperand(0), + N0.getOperand(1), N0.getOperand(2), EVT); CombineTo(N, ExtLoad); CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), ExtLoad.getValue(1)); From natebegeman at mac.com Sun May 7 21:52:51 2006 From: natebegeman at mac.com (Nate Begeman) Date: Sun, 7 May 2006 21:52:51 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp README.txt Message-ID: <200605080252.VAA11786@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelDAGToDAG.cpp updated: 1.181 -> 1.182 README.txt updated: 1.86 -> 1.87 --- Log message: Update some stuff now that the new rlwimi code has gone in --- Diffs of the changes: (+0 -70) PPCISelDAGToDAG.cpp | 1 README.txt | 69 ---------------------------------------------------- 2 files changed, 70 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.181 llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.182 --- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.181 Sat May 6 19:23:38 2006 +++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Sun May 7 21:52:37 2006 @@ -405,7 +405,6 @@ TLI.ComputeMaskedBits(Op0, TgtMask, LKZ, LKO); TLI.ComputeMaskedBits(Op1, TgtMask, RKZ, RKO); - // FIXME: rotrwi / rotlwi if ((LKZ | RKZ) == 0x00000000FFFFFFFFULL) { unsigned PInsMask = ~RKZ; unsigned PTgtMask = ~LKZ; Index: llvm/lib/Target/PowerPC/README.txt diff -u llvm/lib/Target/PowerPC/README.txt:1.86 llvm/lib/Target/PowerPC/README.txt:1.87 --- llvm/lib/Target/PowerPC/README.txt:1.86 Fri May 5 00:36:15 2006 +++ llvm/lib/Target/PowerPC/README.txt Sun May 7 21:52:38 2006 @@ -85,75 +85,6 @@ ===-------------------------------------------------------------------------=== -#define ARRAY_LENGTH 16 - -union bitfield { - struct { -#ifndef __ppc__ - unsigned int field0 : 6; - unsigned int field1 : 6; - unsigned int field2 : 6; - unsigned int field3 : 6; - unsigned int field4 : 3; - unsigned int field5 : 4; - unsigned int field6 : 1; -#else - unsigned int field6 : 1; - unsigned int field5 : 4; - unsigned int field4 : 3; - unsigned int field3 : 6; - unsigned int field2 : 6; - unsigned int field1 : 6; - unsigned int field0 : 6; -#endif - } bitfields, bits; - unsigned int u32All; - signed int i32All; - float f32All; -}; - - -typedef struct program_t { - union bitfield array[ARRAY_LENGTH]; - int size; - int loaded; -} program; - - -void AdjustBitfields(program* prog, unsigned int fmt1) -{ - prog->array[0].bitfields.field0 = fmt1; - prog->array[0].bitfields.field1 = fmt1 + 1; -} - -We currently generate: - -_AdjustBitfields: - lwz r2, 0(r3) - addi r5, r4, 1 - rlwinm r2, r2, 0, 0, 19 - rlwinm r5, r5, 6, 20, 25 - rlwimi r2, r4, 0, 26, 31 - or r2, r2, r5 - stw r2, 0(r3) - blr - -We should teach someone that or (rlwimi, rlwinm) with disjoint masks can be -turned into rlwimi (rlwimi) - -The better codegen would be: - -_AdjustBitfields: - lwz r0,0(r3) - rlwinm r4,r4,0,0xff - rlwimi r0,r4,0,26,31 - addi r4,r4,1 - rlwimi r0,r4,6,20,25 - stw r0,0(r3) - blr - -===-------------------------------------------------------------------------=== - Compile this: int %f1(int %a, int %b) {