From resistor at mac.com Mon May 15 00:13:19 2006 From: resistor at mac.com (Owen Anderson) Date: Mon, 15 May 2006 00:13:19 -0500 Subject: [llvm-commits] CVS: llvm/CREDITS.TXT Message-ID: <200605150513.AAA20041@zion.cs.uiuc.edu> Changes in directory llvm: CREDITS.TXT updated: 1.52 -> 1.53 --- Log message: Add myself to the credits. --- Diffs of the changes: (+4 -0) CREDITS.TXT | 4 ++++ 1 files changed, 4 insertions(+) Index: llvm/CREDITS.TXT diff -u llvm/CREDITS.TXT:1.52 llvm/CREDITS.TXT:1.53 --- llvm/CREDITS.TXT:1.52 Sun May 14 15:29:25 2006 +++ llvm/CREDITS.TXT Mon May 15 00:13:07 2006 @@ -13,6 +13,10 @@ W: http://www.cs.uiuc.edu/~vadve/ D: The Sparc64 backend, provider of much wisdom, and motivator for LLVM +N: Owen Anderson +E: resistor at mac.com +D: TargetData refactoring, random improvements + N: Henrik Bach D: MingW Win32 API portability layer From lattner at cs.uiuc.edu Mon May 15 00:48:44 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 15 May 2006 00:48:44 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp Message-ID: <200605150548.AAA20181@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCAsmPrinter.cpp updated: 1.175 -> 1.176 --- Log message: Remove some dead code, identified by coverity. --- Diffs of the changes: (+0 -6) PPCAsmPrinter.cpp | 6 ------ 1 files changed, 6 deletions(-) Index: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp diff -u llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.175 llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.176 --- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.175 Fri May 12 12:33:59 2006 +++ llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp Mon May 15 00:48:32 2006 @@ -350,13 +350,7 @@ #include "PPCGenAsmWriter.inc" void PPCAsmPrinter::printOp(const MachineOperand &MO) { - const MRegisterInfo &RI = *TM.getRegisterInfo(); - int new_symbol; - switch (MO.getType()) { - O << RI.get(MO.getReg()).Name; - return; - case MachineOperand::MO_Immediate: std::cerr << "printOp() does not handle immediate values\n"; abort(); From reid at x10sys.com Mon May 15 11:12:25 2006 From: reid at x10sys.com (Reid Spencer) Date: Mon, 15 May 2006 11:12:25 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineConstantPool.h Message-ID: <200605151612.LAA02131@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: MachineConstantPool.h updated: 1.16 -> 1.17 --- Log message: Doxygenify the comments, bringing the file level comments down to be attached with the class that it documents. Patch suggested by Vladimir Prus. --- Diffs of the changes: (+22 -21) MachineConstantPool.h | 43 ++++++++++++++++++++++--------------------- 1 files changed, 22 insertions(+), 21 deletions(-) Index: llvm/include/llvm/CodeGen/MachineConstantPool.h diff -u llvm/include/llvm/CodeGen/MachineConstantPool.h:1.16 llvm/include/llvm/CodeGen/MachineConstantPool.h:1.17 --- llvm/include/llvm/CodeGen/MachineConstantPool.h:1.16 Tue May 2 20:29:56 2006 +++ llvm/include/llvm/CodeGen/MachineConstantPool.h Mon May 15 11:12:01 2006 @@ -7,15 +7,8 @@ // //===----------------------------------------------------------------------===// // -// The MachineConstantPool class keeps track of constants referenced by a -// function which must be spilled to memory. This is used for constants which -// are unable to be used directly as operands to instructions, which typically -// include floating point and large integer constants. -// -// Instructions reference the address of these constant pool constants through -// the use of MO_ConstantPoolIndex values. When emitting assembly or machine -// code, these virtual address references are converted to refer to the -// address of the function constant pool values. +/// @file This file declares the MachineConstantPool class which is an abstract +/// constant pool to keep track of constants referenced by a function. // //===----------------------------------------------------------------------===// @@ -30,22 +23,32 @@ class Constant; class TargetData; -/// MachineConstantPoolEntry - One entry in the constant pool. -/// +/// This class is a data container for one entry in a MachineConstantPool. +/// It contains a pointer to the value and an offset from the start of +/// the constant pool. +/// @brief An entry in a MachineConstantPool struct MachineConstantPoolEntry { - /// Val - The constant itself. - Constant *Val; - /// Offset - The offset of the constant from the start of the constant pool. - unsigned Offset; - + Constant *Val; ///< The constant itself. + unsigned Offset; ///< The offset of the constant from the start of the pool. MachineConstantPoolEntry(Constant *V, unsigned O) : Val(V), Offset(O) {} }; +/// The MachineConstantPool class keeps track of constants referenced by a +/// function which must be spilled to memory. This is used for constants which +/// are unable to be used directly as operands to instructions, which typically +/// include floating point and large integer constants. +/// +/// Instructions reference the address of these constant pool constants through +/// the use of MO_ConstantPoolIndex values. When emitting assembly or machine +/// code, these virtual address references are converted to refer to the +/// address of the function constant pool values. +/// @brief The machine constant pool. class MachineConstantPool { - const TargetData *TD; - unsigned PoolAlignment; - std::vector Constants; + const TargetData *TD; ///< The machine's TargetData. + unsigned PoolAlignment; ///< The alignment for the pool. + std::vector Constants; ///< The pool of constants. public: + /// @brief The only constructor. MachineConstantPool(const TargetData *td) : TD(td), PoolAlignment(1) {} /// getConstantPoolAlignment - Return the log2 of the alignment required by @@ -54,11 +57,9 @@ /// getConstantPoolIndex - Create a new entry in the constant pool or return /// an existing one. User must specify an alignment in bytes for the object. - /// unsigned getConstantPoolIndex(Constant *C, unsigned Alignment); /// isEmpty - Return true if this constant pool contains no constants. - /// bool isEmpty() const { return Constants.empty(); } const std::vector &getConstants() const { From lattner at cs.uiuc.edu Mon May 15 12:25:18 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 15 May 2006 12:25:18 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetMachineRegistry.h Message-ID: <200605151725.MAA02773@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/Target: TargetMachineRegistry.h updated: 1.8 -> 1.9 --- Log message: Improve comments, patch provided by Vladimir Prus! --- Diffs of the changes: (+7 -1) TargetMachineRegistry.h | 8 +++++++- 1 files changed, 7 insertions(+), 1 deletion(-) Index: llvm/include/llvm/Target/TargetMachineRegistry.h diff -u llvm/include/llvm/Target/TargetMachineRegistry.h:1.8 llvm/include/llvm/Target/TargetMachineRegistry.h:1.9 --- llvm/include/llvm/Target/TargetMachineRegistry.h:1.8 Wed Mar 22 23:41:41 2006 +++ llvm/include/llvm/Target/TargetMachineRegistry.h Mon May 15 12:25:05 2006 @@ -70,7 +70,13 @@ /// RegisterTarget - This class is used to make targets automatically register /// themselves with the tool they are linked. Targets should define an /// instance of this and implement the static methods described in the - /// TargetMachine comments.. + /// TargetMachine comments. + /// The type 'TargetMachineImpl' should provide a constructor with two + /// parameters: + /// - const Module& M: the module that is being compiled: + /// - const std::string& FS: target-specific string describing target + /// flavour. + template struct RegisterTarget : public TargetMachineRegistry::Entry { RegisterTarget(const char *Name, const char *ShortDesc) : From lattner at cs.uiuc.edu Mon May 15 12:26:58 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 15 May 2006 12:26:58 -0500 Subject: [llvm-commits] CVS: llvm/docs/LangRef.html Message-ID: <200605151726.MAA02838@zion.cs.uiuc.edu> Changes in directory llvm/docs: LangRef.html updated: 1.151 -> 1.152 --- Log message: Update dox, patch by Vladimir Prus! --- Diffs of the changes: (+2 -2) LangRef.html | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/docs/LangRef.html diff -u llvm/docs/LangRef.html:1.151 llvm/docs/LangRef.html:1.152 --- llvm/docs/LangRef.html:1.151 Sun May 14 13:23:06 2006 +++ llvm/docs/LangRef.html Mon May 15 12:26:46 2006 @@ -2862,7 +2862,7 @@ transformations should be prepared to handle intrinsics with any type used.

-

This example shows how the vanext +

This example shows how the va_arg instruction and the variable argument handling intrinsic functions are used.

@@ -3817,7 +3817,7 @@ Chris Lattner
The LLVM Compiler Infrastructure
- Last modified: $Date: 2006/05/14 18:23:06 $ + Last modified: $Date: 2006/05/15 17:26:46 $ From lattner at cs.uiuc.edu Mon May 15 13:35:14 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 15 May 2006 13:35:14 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Target.td Message-ID: <200605151835.NAA03794@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target: Target.td updated: 1.79 -> 1.80 --- Log message: Improve comment, patch provided by Vladimir Prus! --- Diffs of the changes: (+3 -1) Target.td | 4 +++- 1 files changed, 3 insertions(+), 1 deletion(-) Index: llvm/lib/Target/Target.td diff -u llvm/lib/Target/Target.td:1.79 llvm/lib/Target/Target.td:1.80 --- llvm/lib/Target/Target.td:1.79 Sat May 13 21:05:19 2006 +++ llvm/lib/Target/Target.td Mon May 15 13:35:02 2006 @@ -72,7 +72,9 @@ // RegType - Specify the list ValueType of the registers in this register // class. Note that all registers in a register class must have the same - // ValueTypes. + // ValueTypes. This is a list because some targets permit storing different + // types in same register, for example vector values with 128-bit total size, + // but different count/size of items, like SSE on x86. // list RegTypes = regTypes; From lattner at cs.uiuc.edu Mon May 15 14:54:10 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 15 May 2006 14:54:10 -0500 Subject: [llvm-commits] CVS: llvm-www/status/patches/coreutils-5.0-llvm.patch crafty-19.3-llvm.patch screen-3.9.15-llvm.patch siod-llvm.patch Message-ID: <200605151954.OAA04531@zion.cs.uiuc.edu> Changes in directory llvm-www/status/patches: coreutils-5.0-llvm.patch (r1.1) removed crafty-19.3-llvm.patch (r1.1) removed screen-3.9.15-llvm.patch (r1.1) removed siod-llvm.patch (r1.1) removed --- Log message: Remove old files --- Diffs of the changes: (+0 -0) 0 files changed From lattner at cs.uiuc.edu Mon May 15 14:54:44 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 15 May 2006 14:54:44 -0500 Subject: [llvm-commits] CVS: llvm-www/status/index.html status.css Message-ID: <200605151954.OAA04570@zion.cs.uiuc.edu> Changes in directory llvm-www/status: index.html (r1.43) removed status.css (r1.1) removed --- Log message: This information is out of date, and there is no maintainer, remove it. --- Diffs of the changes: (+0 -0) 0 files changed From reid at x10sys.com Mon May 15 16:36:26 2006 From: reid at x10sys.com (Reid Spencer) Date: Mon, 15 May 2006 16:36:26 -0500 Subject: [llvm-commits] CVS: llvm/docs/doxygen.cfg.in doxygen.css doxygen.footer Message-ID: <200605152136.QAA05060@zion.cs.uiuc.edu> Changes in directory llvm/docs: doxygen.cfg.in updated: 1.11 -> 1.12 doxygen.css updated: 1.3 -> 1.4 doxygen.footer updated: 1.4 -> 1.5 --- Log message: Upgrade in preparation for doxygen 1.4.4. The config file format changed, there are new/different css styles to support, and the footer was woefully out of date. --- Diffs of the changes: (+872 -218) doxygen.cfg.in | 663 ++++++++++++++++++++++++++++++++++++++++++++------------- doxygen.css | 416 ++++++++++++++++++++++++++++++----- doxygen.footer | 11 3 files changed, 872 insertions(+), 218 deletions(-) Index: llvm/docs/doxygen.cfg.in diff -u llvm/docs/doxygen.cfg.in:1.11 llvm/docs/doxygen.cfg.in:1.12 --- llvm/docs/doxygen.cfg.in:1.11 Sat May 14 15:06:31 2005 +++ llvm/docs/doxygen.cfg.in Mon May 15 16:36:13 2006 @@ -1,4 +1,4 @@ -# Doxyfile 1.2.13.1 +# Doxyfile 1.4.4 # This file describes the settings to be used by the documentation system # doxygen (www.doxygen.org) for a project @@ -11,7 +11,7 @@ # Values that contain spaces should be placed between quotes (" ") #--------------------------------------------------------------------------- -# General configuration options +# Project related configuration options #--------------------------------------------------------------------------- # The PROJECT_NAME tag is a single word (or a sequence of words surrounded @@ -32,16 +32,188 @@ OUTPUT_DIRECTORY = @abs_top_builddir@/docs/doxygen +# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create +# 4096 sub-directories (in 2 levels) under the output directory of each output +# format and will distribute the generated files over these directories. +# Enabling this option can be useful when feeding doxygen a huge amount of +# source files, where putting all generated files in the same directory would +# otherwise cause performance problems for the file system. + +CREATE_SUBDIRS = NO + # The OUTPUT_LANGUAGE tag is used to specify the language in which all # documentation generated by doxygen is written. Doxygen will use this # information to generate all constant output in the proper language. # The default language is English, other supported languages are: -# Brazilian, Chinese, Croatian, Czech, Danish, Dutch, Finnish, French, -# German, Greek, Hungarian, Italian, Japanese, Korean, Norwegian, Polish, -# Portuguese, Romanian, Russian, Slovak, Slovene, Spanish and Swedish. +# Brazilian, Catalan, Chinese, Chinese-Traditional, Croatian, Czech, Danish, +# Dutch, Finnish, French, German, Greek, Hungarian, Italian, Japanese, +# Japanese-en (Japanese with English messages), Korean, Korean-en, Norwegian, +# Polish, Portuguese, Romanian, Russian, Serbian, Slovak, Slovene, Spanish, +# Swedish, and Ukrainian. OUTPUT_LANGUAGE = English +# This tag can be used to specify the encoding used in the generated output. +# The encoding is not always determined by the language that is chosen, +# but also whether or not the output is meant for Windows or non-Windows users. +# In case there is a difference, setting the USE_WINDOWS_ENCODING tag to YES +# forces the Windows encoding (this is the default for the Windows binary), +# whereas setting the tag to NO uses a Unix-style encoding (the default for +# all platforms other than Windows). + +USE_WINDOWS_ENCODING = NO + +# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will +# include brief member descriptions after the members that are listed in +# the file and class documentation (similar to JavaDoc). +# Set to NO to disable this. + +BRIEF_MEMBER_DESC = YES + +# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend +# the brief description of a member or function before the detailed description. +# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the +# brief descriptions will be completely suppressed. + +REPEAT_BRIEF = YES + +# This tag implements a quasi-intelligent brief description abbreviator +# that is used to form the text in various listings. Each string +# in this list, if found as the leading text of the brief description, will be +# stripped from the text and the result after processing the whole list, is +# used as the annotated text. Otherwise, the brief description is used as-is. +# If left blank, the following values are used ("$name" is automatically +# replaced with the name of the entity): "The $name class" "The $name widget" +# "The $name file" "is" "provides" "specifies" "contains" +# "represents" "a" "an" "the" + +ABBREVIATE_BRIEF = + +# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then +# Doxygen will generate a detailed section even if there is only a brief +# description. + +ALWAYS_DETAILED_SEC = NO + +# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all +# inherited members of a class in the documentation of that class as if those +# members were ordinary class members. Constructors, destructors and assignment +# operators of the base classes will not be shown. + +INLINE_INHERITED_MEMB = NO + +# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full +# path before files name in the file list and in the header files. If set +# to NO the shortest path that makes the file name unique will be used. + +FULL_PATH_NAMES = NO + +# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag +# can be used to strip a user-defined part of the path. Stripping is +# only done if one of the specified strings matches the left-hand part of +# the path. The tag can be used to show relative paths in the file list. +# If left blank the directory from which doxygen is run is used as the +# path to strip. + +STRIP_FROM_PATH = ../.. + +# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of +# the path mentioned in the documentation of a class, which tells +# the reader which header file to include in order to use a class. +# If left blank only the name of the header file containing the class +# definition is used. Otherwise one should specify the include paths that +# are normally passed to the compiler using the -I flag. + +STRIP_FROM_INC_PATH = + +# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter +# (but less readable) file names. This can be useful is your file systems +# doesn't support long names like on DOS, Mac, or CD-ROM. + +SHORT_NAMES = NO + +# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen +# will interpret the first line (until the first dot) of a JavaDoc-style +# comment as the brief description. If set to NO, the JavaDoc +# comments will behave just like the Qt-style comments (thus requiring an +# explicit @brief command for a brief description. + +JAVADOC_AUTOBRIEF = NO + +# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen +# treat a multi-line C++ special comment block (i.e. a block of //! or /// +# comments) as a brief description. This used to be the default behaviour. +# The new default is to treat a multi-line C++ comment block as a detailed +# description. Set this tag to YES if you prefer the old behaviour instead. + +MULTILINE_CPP_IS_BRIEF = NO + +# If the DETAILS_AT_TOP tag is set to YES then Doxygen +# will output the detailed description near the top, like JavaDoc. +# If set to NO, the detailed description appears after the member +# documentation. + +DETAILS_AT_TOP = NO + +# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented +# member inherits the documentation from any documented member that it +# re-implements. + +INHERIT_DOCS = YES + +# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC +# tag is set to YES, then doxygen will reuse the documentation of the first +# member in the group (if any) for the other members of the group. By default +# all members of a group must be documented explicitly. + +DISTRIBUTE_GROUP_DOC = NO + +# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce +# a new page for each member. If set to NO, the documentation of a member will +# be part of the file/class/namespace that contains it. + +SEPARATE_MEMBER_PAGES = NO + +# The TAB_SIZE tag can be used to set the number of spaces in a tab. +# Doxygen uses this value to replace tabs by spaces in code fragments. + +TAB_SIZE = 2 + +# This tag can be used to specify a number of aliases that acts +# as commands in the documentation. An alias has the form "name=value". +# For example adding "sideeffect=\par Side Effects:\n" will allow you to +# put the command \sideeffect (or @sideeffect) in the documentation, which +# will result in a user-defined paragraph with heading "Side Effects:". +# You can put \n's in the value part of an alias to insert newlines. + +ALIASES = + +# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C +# sources only. Doxygen will then generate output that is more tailored for C. +# For instance, some of the names that are used will be different. The list +# of all members will be omitted, etc. + +OPTIMIZE_OUTPUT_FOR_C = NO + +# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java sources +# only. Doxygen will then generate output that is more tailored for Java. +# For instance, namespaces will be presented as packages, qualified scopes +# will look different, etc. + +OPTIMIZE_OUTPUT_JAVA = NO + +# Set the SUBGROUPING tag to YES (the default) to allow class member groups of +# the same type (for instance a group of public functions) to be put as a +# subgroup of that type (e.g. under the Public Functions section). Set it to +# NO to prevent subgrouping. Alternatively, this can be done per class using +# the \nosubgrouping command. + +SUBGROUPING = YES + +#--------------------------------------------------------------------------- +# Build related configuration options +#--------------------------------------------------------------------------- + # If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in # documentation are documented, even if no documentation was available. # Private class members and static file members will be hidden unless @@ -65,6 +237,13 @@ EXTRACT_LOCAL_CLASSES = YES +# This flag is only useful for Objective-C code. When set to YES local +# methods, which are defined in the implementation section but not in +# the interface are included in the documentation. +# If set to NO (the default) only methods in the interface are included. + +EXTRACT_LOCAL_METHODS = NO + # If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all # undocumented members of documented classes, files or namespaces. # If set to NO (the default) these members will be included in the @@ -75,50 +254,24 @@ # If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all # undocumented classes that are normally visible in the class hierarchy. -# If set to NO (the default) these class will be included in the various +# If set to NO (the default) these classes will be included in the various # overviews. This option has no effect if EXTRACT_ALL is enabled. HIDE_UNDOC_CLASSES = NO -# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will -# include brief member descriptions after the members that are listed in -# the file and class documentation (similar to JavaDoc). -# Set to NO to disable this. - -BRIEF_MEMBER_DESC = YES - -# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend -# the brief description of a member or function before the detailed description. -# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the -# brief descriptions will be completely suppressed. - -REPEAT_BRIEF = YES - -# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then -# Doxygen will generate a detailed section even if there is only a brief -# description. - -ALWAYS_DETAILED_SEC = NO +# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all +# friend (class|struct|union) declarations. +# If set to NO (the default) these declarations will be included in the +# documentation. + +HIDE_FRIEND_COMPOUNDS = NO + +# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any +# documentation blocks found inside the body of a function. +# If set to NO (the default) these blocks will be appended to the +# function's detailed documentation block. -# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all -# inherited members of a class in the documentation of that class as if those -# members were ordinary class members. Constructors, destructors and assignment -# operators of the base classes will not be shown. - -INLINE_INHERITED_MEMB = NO - -# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full -# path before files name in the file list and in the header files. If set -# to NO the shortest path that makes the file name unique will be used. - -FULL_PATH_NAMES = NO - -# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag -# can be used to strip a user defined part of the path. Stripping is -# only done if one of the specified strings matches the left-hand part of -# the path. It is allowed to use relative paths in the argument list. - -STRIP_FROM_PATH = ../.. +HIDE_IN_BODY_DOCS = NO # The INTERNAL_DOCS tag determines if documentation # that is typed after a \internal command is included. If the tag is set @@ -127,58 +280,26 @@ INTERNAL_DOCS = NO -# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct -# doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. - -STRIP_CODE_COMMENTS = NO - # If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate -# file names in lower case letters. If set to YES upper case letters are also +# file names in lower-case letters. If set to YES upper-case letters are also # allowed. This is useful if you have classes or files whose names only differ # in case and if your file system supports case sensitive file names. Windows -# users are adviced to set this option to NO. +# and Mac users are advised to set this option to NO. CASE_SENSE_NAMES = YES -# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter -# (but less readable) file names. This can be useful is your file systems -# doesn't support long names like on DOS, Mac, or CD-ROM. - -SHORT_NAMES = NO - # If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen # will show members with their full class and namespace scopes in the # documentation. If set to YES the scope will be hidden. HIDE_SCOPE_NAMES = NO -# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen -# will generate a verbatim copy of the header file for each class for -# which an include is specified. Set to NO to disable this. - -VERBATIM_HEADERS = YES - # If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen -# will put list of the files that are included by a file in the documentation +# will put a list of the files that are included by a file in the documentation # of that file. SHOW_INCLUDE_FILES = YES -# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen -# will interpret the first line (until the first dot) of a JavaDoc-style -# comment as the brief description. If set to NO, the JavaDoc -# comments will behave just like the Qt-style comments (thus requiring an -# explict @brief command for a brief description. - -JAVADOC_AUTOBRIEF = NO - -# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented -# member inherits the documentation from any documented member that it -# reimplements. - -INHERIT_DOCS = YES - # If the INLINE_INFO tag is set to YES (the default) then a tag [inline] # is inserted in the documentation for inline members. @@ -191,17 +312,22 @@ SORT_MEMBER_DOCS = YES -# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC -# tag is set to YES, then doxygen will reuse the documentation of the first -# member in the group (if any) for the other members of the group. By default -# all members of a group must be documented explicitly. +# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the +# brief documentation of file, namespace and class members alphabetically +# by member name. If set to NO (the default) the members will appear in +# declaration order. -DISTRIBUTE_GROUP_DOC = NO +SORT_BRIEF_DOCS = NO -# The TAB_SIZE tag can be used to set the number of spaces in a tab. -# Doxygen uses this value to replace tabs by spaces in code fragments. +# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be +# sorted by fully-qualified names, including namespaces. If set to +# NO (the default), the class list will be sorted only by class name, +# not including the namespace part. +# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. +# Note: This option applies only to the class list, not to the +# alphabetical list. -TAB_SIZE = 2 +SORT_BY_SCOPE_NAME = NO # The GENERATE_TODOLIST tag can be used to enable (YES) or # disable (NO) the todo list. This list is created by putting \todo @@ -221,14 +347,11 @@ GENERATE_BUGLIST = YES -# This tag can be used to specify a number of aliases that acts -# as commands in the documentation. An alias has the form "name=value". -# For example adding "sideeffect=\par Side Effects:\n" will allow you to -# put the command \sideeffect (or @sideeffect) in the documentation, which -# will result in a user defined paragraph with heading "Side Effects:". -# You can put \n's in the value part of an alias to insert newlines. +# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or +# disable (NO) the deprecated list. This list is created by putting +# \deprecated commands in the documentation. -ALIASES = +GENERATE_DEPRECATEDLIST= YES # The ENABLED_SECTIONS tag can be used to enable conditional # documentation sections, marked by \if sectionname ... \endif. @@ -236,7 +359,7 @@ ENABLED_SECTIONS = # The MAX_INITIALIZER_LINES tag determines the maximum number of lines -# the initial value of a variable or define consist of for it to appear in +# the initial value of a variable or define consists of for it to appear in # the documentation. If the initializer consists of more lines than specified # here it will be hidden. Use a value of 0 to hide initializers completely. # The appearance of the initializer of individual variables and defines in the @@ -245,19 +368,28 @@ MAX_INITIALIZER_LINES = 30 -# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C sources -# only. Doxygen will then generate output that is more tailored for C. -# For instance some of the names that are used will be different. The list -# of all members will be omitted, etc. - -OPTIMIZE_OUTPUT_FOR_C = NO - # Set the SHOW_USED_FILES tag to NO to disable the list of files generated # at the bottom of the documentation of classes and structs. If set to YES the # list will mention the files that were used to generate the documentation. SHOW_USED_FILES = YES +# If the sources in your project are distributed over multiple directories +# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy +# in the documentation. The default is YES. + +SHOW_DIRECTORIES = YES + +# The FILE_VERSION_FILTER tag can be used to specify a program or script that +# doxygen should invoke to get the current version for each file (typically from the +# version control system). Doxygen will invoke the program by executing (via +# popen()) the command , where is the value of +# the FILE_VERSION_FILTER tag, and is the name of an input file +# provided by doxygen. Whatever the progam writes to standard output +# is used as the file version. See the manual for examples. + +FILE_VERSION_FILTER = + #--------------------------------------------------------------------------- # configuration options related to warning and progress messages #--------------------------------------------------------------------------- @@ -279,10 +411,27 @@ WARN_IF_UNDOCUMENTED = NO +# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for +# potential errors in the documentation, such as not documenting some +# parameters in a documented function, or documenting parameters that +# don't exist or using markup commands wrongly. + +WARN_IF_DOC_ERROR = YES + +# This WARN_NO_PARAMDOC option can be abled to get warnings for +# functions that are documented, but have no documentation for their parameters +# or return value. If set to NO (the default) doxygen will only warn about +# wrong or incomplete parameter documentation, but not about the absence of +# documentation. + +WARN_NO_PARAMDOC = NO + # The WARN_FORMAT tag determines the format of the warning messages that # doxygen can produce. The string should contain the $file, $line, and $text # tags, which will be replaced by the file and line number from which the -# warning originated and the warning text. +# warning originated and the warning text. Optionally the format may contain +# $version, which will be replaced by the version of the file (if it could +# be obtained via FILE_VERSION_FILTER) WARN_FORMAT = @@ -296,19 +445,21 @@ # configuration options related to the input files #--------------------------------------------------------------------------- -# The INPUT tag can be used to specify the files and/or directories that contain -# documented source files. You may enter file names like "myfile.cpp" or -# directories like "/usr/src/myproject". Separate the files or directories with -# spaces. - -INPUT = @abs_top_srcdir@/include @abs_top_srcdir@/lib @abs_top_srcdir@/docs/doxygen.intro +# The INPUT tag can be used to specify the files and/or directories that contain +# documented source files. You may enter file names like "myfile.cpp" or +# directories like "/usr/src/myproject". Separate the files or directories +# with spaces. + +INPUT = @abs_top_srcdir@/include \ + @abs_top_srcdir@/lib \ + @abs_top_srcdir@/docs/doxygen.intro # If the value of the INPUT tag contains directories, you can use the # FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp # and *.h) to filter out the source-files in the directories. If left # blank the following patterns are tested: -# *.c *.cc *.cxx *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx *.hpp -# *.h++ *.idl +# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx +# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm FILE_PATTERNS = @@ -318,15 +469,23 @@ RECURSIVE = YES -# The EXCLUDE tag can be u sed to specify files and/or directories that should +# The EXCLUDE tag can be used to specify files and/or directories that should # excluded from the INPUT source files. This way you can easily exclude a # subdirectory from a directory tree whose root is specified with the INPUT tag. EXCLUDE = +# The EXCLUDE_SYMLINKS tag can be used select whether or not files or +# directories that are symbolic links (a Unix filesystem feature) are excluded +# from the input. + +EXCLUDE_SYMLINKS = NO + # If the value of the INPUT tag contains directories, you can use the # EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. +# certain files from those directories. Note that the wildcards are matched +# against the file with absolute path, so to exclude all test directories +# for example use the pattern */test/* EXCLUDE_PATTERNS = @@ -361,13 +520,23 @@ # by executing (via popen()) the command , where # is the value of the INPUT_FILTER tag, and is the name of an # input file. Doxygen will then use the output that the filter program writes -# to standard output. +# to standard output. If FILTER_PATTERNS is specified, this tag will be +# ignored. INPUT_FILTER = +# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern +# basis. Doxygen will compare the file name with each pattern and apply the +# filter if there is a match. The filters are a list of the form: +# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further +# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER +# is applied to all files. + +FILTER_PATTERNS = + # If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using # INPUT_FILTER) will be used to filter the input files when producing source -# files to browse. +# files to browse (i.e. when SOURCE_BROWSER is set to YES). FILTER_SOURCE_FILES = NO @@ -376,7 +545,9 @@ #--------------------------------------------------------------------------- # If the SOURCE_BROWSER tag is set to YES then a list of source files will -# be generated. Documented entities will be cross-referenced with these sources. +# be generated. Documented entities will be cross-referenced with these sources. +# Note: To get rid of all source code in the generated output, make sure also +# VERBATIM_HEADERS is set to NO. SOURCE_BROWSER = YES @@ -385,6 +556,12 @@ INLINE_SOURCES = NO +# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct +# doxygen to hide any special comment blocks from generated source code +# fragments. Normal C and C++ comments will always remain visible. + +STRIP_CODE_COMMENTS = NO + # If the REFERENCED_BY_RELATION tag is set to YES (the default) # then for each documented function all documented # functions referencing it will be listed. @@ -397,6 +574,20 @@ REFERENCES_RELATION = YES +# If the USE_HTAGS tag is set to YES then the references to source code +# will point to the HTML generated by the htags(1) tool instead of doxygen +# built-in source browser. The htags tool is part of GNU's global source +# tagging system (see http://www.gnu.org/software/global/global.html). You +# will need version 4.8.6 or higher. + +USE_HTAGS = NO + +# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen +# will generate a verbatim copy of the header file for each class for +# which an include is specified. Set to NO to disable this. + +VERBATIM_HEADERS = YES + #--------------------------------------------------------------------------- # configuration options related to the alphabetical class index #--------------------------------------------------------------------------- @@ -435,6 +626,12 @@ HTML_OUTPUT = html +# The HTML_FILE_EXTENSION tag can be used to specify the file extension for +# each generated HTML page (for example: .htm,.php,.asp). If it is left blank +# doxygen will generate files with .html extension. + +HTML_FILE_EXTENSION = .html + # The HTML_HEADER tag can be used to specify a personal HTML header for # each generated HTML page. If it is left blank doxygen will generate a # standard header. @@ -447,10 +644,12 @@ HTML_FOOTER = @abs_top_srcdir@/docs/doxygen.footer -# The HTML_STYLESHEET tag can be used to specify a user defined cascading +# The HTML_STYLESHEET tag can be used to specify a user-defined cascading # style sheet that is used by each HTML page. It can be used to # fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet +# will generate a default style sheet. Note that doxygen will try to copy +# the style sheet file to the HTML output directory, so don't put your own +# stylesheet in the HTML output directory as well, or it will be erased! HTML_STYLESHEET = @abs_top_srcdir@/docs/doxygen.css @@ -467,6 +666,20 @@ GENERATE_HTMLHELP = NO +# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can +# be used to specify the file name of the resulting .chm file. You +# can add a path in front of the file if the result should not be +# written to the html output directory. + +CHM_FILE = + +# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can +# be used to specify the location (absolute path including file name) of +# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run +# the HTML help compiler on the generated index.hhp. + +HHC_LOCATION = + # If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag # controls if a separate .chi index file is generated (YES) or that # it should be included in the master .chm file (NO). @@ -480,7 +693,7 @@ BINARY_TOC = NO # The TOC_EXPAND flag can be set to YES to add extra items for group members -# to the contents of the Html help documentation and to the tree view. +# to the contents of the HTML help documentation and to the tree view. TOC_EXPAND = NO @@ -498,10 +711,9 @@ # If the GENERATE_TREEVIEW tag is set to YES, a side panel will be # generated containing a tree-like index structure (just like the one that # is generated for HTML Help). For this to work a browser that supports -# JavaScript and frames is required (for instance Mozilla, Netscape 4.0+, -# or Internet explorer 4.0+). Note that for large projects the tree generation -# can take a very long time. In such cases it is better to disable this feature. -# Windows users are probably better off using the HTML help feature. +# JavaScript, DHTML, CSS and frames is required (for instance Mozilla 1.0+, +# Netscape 6.0+, Internet explorer 5.0+, or Konqueror). Windows users are +# probably better off using the HTML help feature. GENERATE_TREEVIEW = NO @@ -526,6 +738,17 @@ LATEX_OUTPUT = +# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be +# invoked. If left blank `latex' will be used as the default command name. + +LATEX_CMD_NAME = latex + +# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to +# generate index for LaTeX. If left blank `makeindex' will be used as the +# default command name. + +MAKEINDEX_CMD_NAME = makeindex + # If the COMPACT_LATEX tag is set to YES Doxygen generates more compact # LaTeX documents. This may be useful for small projects and may help to # save some trees in general. @@ -570,12 +793,18 @@ LATEX_BATCHMODE = NO +# If LATEX_HIDE_INDICES is set to YES then doxygen will not +# include the index chapters (such as File Index, Compound Index, etc.) +# in the output. + +LATEX_HIDE_INDICES = NO + #--------------------------------------------------------------------------- # configuration options related to the RTF output #--------------------------------------------------------------------------- # If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output -# The RTF output is optimised for Word 97 and may not look very pretty with +# The RTF output is optimized for Word 97 and may not look very pretty with # other RTF readers or editors. GENERATE_RTF = NO @@ -602,7 +831,7 @@ RTF_HYPERLINKS = NO # Load stylesheet definitions from file. Syntax is similar to doxygen's -# config file, i.e. a series of assigments. You only have to provide +# config file, i.e. a series of assignments. You only have to provide # replacements, missing definitions are set to their default value. RTF_STYLESHEET_FILE = @@ -646,12 +875,35 @@ # If the GENERATE_XML tag is set to YES Doxygen will # generate an XML file that captures the structure of -# the code including all documentation. Note that this -# feature is still experimental and incomplete at the -# moment. +# the code including all documentation. GENERATE_XML = NO +# The XML_OUTPUT tag is used to specify where the XML pages will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `xml' will be used as the default path. + +XML_OUTPUT = xml + +# The XML_SCHEMA tag can be used to specify an XML schema, +# which can be used by a validating XML parser to check the +# syntax of the XML files. + +XML_SCHEMA = + +# The XML_DTD tag can be used to specify an XML DTD, +# which can be used by a validating XML parser to check the +# syntax of the XML files. + +XML_DTD = + +# If the XML_PROGRAMLISTING tag is set to YES Doxygen will +# dump the program listings (including syntax highlighting +# and cross-referencing information) to the XML output. Note that +# enabling this will significantly increase the size of the XML output. + +XML_PROGRAMLISTING = YES + #--------------------------------------------------------------------------- # configuration options for the AutoGen Definitions output #--------------------------------------------------------------------------- @@ -665,6 +917,39 @@ GENERATE_AUTOGEN_DEF = NO #--------------------------------------------------------------------------- +# configuration options related to the Perl module output +#--------------------------------------------------------------------------- + +# If the GENERATE_PERLMOD tag is set to YES Doxygen will +# generate a Perl module file that captures the structure of +# the code including all documentation. Note that this +# feature is still experimental and incomplete at the +# moment. + +GENERATE_PERLMOD = NO + +# If the PERLMOD_LATEX tag is set to YES Doxygen will generate +# the necessary Makefile rules, Perl scripts and LaTeX code to be able +# to generate PDF and DVI output from the Perl module output. + +PERLMOD_LATEX = NO + +# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be +# nicely formatted so it can be parsed by a human reader. This is useful +# if you want to understand what is going on. On the other hand, if this +# tag is set to NO the size of the Perl module output will be much smaller +# and Perl will parse it just the same. + +PERLMOD_PRETTY = YES + +# The names of the make variables in the generated doxyrules.make file +# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. +# This is useful so different doxyrules.make files included by the same +# Makefile don't overwrite each other's variables. + +PERLMOD_MAKEVAR_PREFIX = + +#--------------------------------------------------------------------------- # Configuration options related to the preprocessor #--------------------------------------------------------------------------- @@ -709,11 +994,13 @@ # are defined before the preprocessor is started (similar to the -D option of # gcc). The argument of the tag is a list of macros of the form: name # or name=definition (no spaces). If the definition and the = are -# omitted =1 is assumed. +# omitted =1 is assumed. To prevent a macro definition from being +# undefined via #undef or recursively expanded use the := operator +# instead of the = operator. PREDEFINED = -# If the MACRO_EXPANSION and EXPAND_PREDEF_ONLY tags are set to YES then +# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then # this tag can be used to specify a list of macro names that should be expanded. # The macro definition that is found in the sources will be used. # Use the PREDEFINED tag if you want to use a different macro definition. @@ -722,16 +1009,30 @@ # If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then # doxygen's preprocessor will remove all function-like macros that are alone -# on a line and do not end with a semicolon. Such function macros are typically -# used for boiler-plate code, and will confuse the parser if not removed. +# on a line, have an all uppercase name, and do not end with a semicolon. Such +# function macros are typically used for boiler-plate code, and will confuse +# the parser if not removed. SKIP_FUNCTION_MACROS = YES #--------------------------------------------------------------------------- -# Configuration::addtions related to external references +# Configuration::additions related to external references #--------------------------------------------------------------------------- -# The TAGFILES tag can be used to specify one or more tagfiles. +# The TAGFILES option can be used to specify one or more tagfiles. +# Optionally an initial location of the external documentation +# can be added for each tagfile. The format of a tag file without +# this location is as follows: +# TAGFILES = file1 file2 ... +# Adding location for the tag files is done as follows: +# TAGFILES = file1=loc1 "file2 = loc2" ... +# where "loc1" and "loc2" can be relative or absolute paths or +# URLs. If a location is present for each tag, the installdox tool +# does not have to be run to correct the links. +# Note that each tag file must have a unique name +# (where the name does NOT include the path) +# If a tag file is not located in the directory in which doxygen +# is run, you must also specify the path to the tagfile here. TAGFILES = @@ -746,6 +1047,12 @@ ALLEXTERNALS = YES +# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed +# in the modules index. If set to NO, only the current project's groups will +# be listed. + +EXTERNAL_GROUPS = YES + # The PERL_PATH should be the absolute path and name of the perl script # interpreter (i.e. the result of `which perl'). @@ -755,14 +1062,21 @@ # Configuration options related to the dot tool #--------------------------------------------------------------------------- -# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will generate a -# inheritance diagram (in Html, RTF and LaTeX) for classes with base or super -# classes. Setting the tag to NO turns the diagrams off. Note that this option -# is superceded by the HAVE_DOT option below. This is only a fallback. It is -# recommended to install and use dot, since it yield more powerful graphs. +# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will +# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base +# or super classes. Setting the tag to NO turns the diagrams off. Note that +# this option is superseded by the HAVE_DOT option below. This is only a +# fallback. It is recommended to install and use dot, since it yields more +# powerful graphs. CLASS_DIAGRAMS = YES +# If set to YES, the inheritance and collaboration graphs will hide +# inheritance and usage relations if the target is undocumented +# or is not a class. + +HIDE_UNDOC_RELATIONS = NO + # If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is # available from the path. This tool is part of Graphviz, a graph visualization # toolkit from AT&T and Lucent Bell Labs. The other options in this section @@ -784,17 +1098,22 @@ COLLABORATION_GRAPH = YES +# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen +# will generate a graph for groups, showing the direct groups dependencies + +GROUP_GRAPHS = YES + +# If the UML_LOOK tag is set to YES doxygen will generate inheritance and +# collaboration diagrams in a style similar to the OMG's Unified Modeling +# Language. + +UML_LOOK = NO + # If set to YES, the inheritance and collaboration graphs will show the # relations between templates and their instances. TEMPLATE_RELATIONS = YES -# If set to YES, the inheritance and collaboration graphs will hide -# inheritance and usage relations if the target is undocumented -# or is not a class. - -HIDE_UNDOC_RELATIONS = NO - # If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT # tags are set to YES then doxygen will generate a graph for each documented # file showing the direct and indirect include dependencies of the file with @@ -809,13 +1128,34 @@ INCLUDED_BY_GRAPH = YES +# If the CALL_GRAPH and HAVE_DOT tags are set to YES then doxygen will +# generate a call dependency graph for every global function or class method. +# Note that enabling this option will significantly increase the time of a run. +# So in most cases it will be better to enable call graphs for selected +# functions only using the \callgraph command. + +CALL_GRAPH = NO + # If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen # will graphical hierarchy of all classes instead of a textual one. GRAPHICAL_HIERARCHY = YES +# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES +# then doxygen will show the dependencies a directory has on other directories +# in a graphical way. The dependency relations are determined by the #include +# relations between the files in the directories. + +DIRECTORY_GRAPH = YES + +# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images +# generated by dot. Possible values are png, jpg, or gif +# If left blank png will be used. + +DOT_IMAGE_FORMAT = png + # The tag DOT_PATH can be used to specify the path where the dot tool can be -# found. If left blank, it is assumed the dot tool can be found on the path. +# found. If left blank, it is assumed the dot tool can be found in the path. DOT_PATH = @DOT@ @@ -841,6 +1181,33 @@ MAX_DOT_GRAPH_HEIGHT = 1024 +# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the +# graphs generated by dot. A depth value of 3 means that only nodes reachable +# from the root by following a path via at most 3 edges will be shown. Nodes +# that lay further from the root node will be omitted. Note that setting this +# option to 1 or 2 may greatly reduce the computation time needed for large +# code bases. Also note that a graph may be further truncated if the graph's +# image dimensions are not sufficient to fit the graph (see MAX_DOT_GRAPH_WIDTH +# and MAX_DOT_GRAPH_HEIGHT). If 0 is used for the depth value (the default), +# the graph is not depth-constrained. + +MAX_DOT_GRAPH_DEPTH = 0 + +# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent +# background. This is disabled by default, which results in a white background. +# Warning: Depending on the platform used, enabling this option may lead to +# badly anti-aliased labels on the edges of a graph (i.e. they become hard to +# read). + +DOT_TRANSPARENT = NO + +# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output +# files in one run (i.e. multiple -o and -T options on the command line). This +# makes dot run faster, but since only newer versions of dot (>1.8.10) +# support this, this feature is disabled by default. + +DOT_MULTI_TARGETS = NO + # If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will # generate a legend page explaining the meaning of the various boxes and # arrows in the dot generated graphs. @@ -848,13 +1215,13 @@ GENERATE_LEGEND = YES # If the DOT_CLEANUP tag is set to YES (the default) Doxygen will -# remove the intermedate dot files that are used to generate +# remove the intermediate dot files that are used to generate # the various graphs. DOT_CLEANUP = YES #--------------------------------------------------------------------------- -# Configuration::addtions related to the search engine +# Configuration::additions related to the search engine #--------------------------------------------------------------------------- # The SEARCHENGINE tag specifies whether or not a search engine should be Index: llvm/docs/doxygen.css diff -u llvm/docs/doxygen.css:1.3 llvm/docs/doxygen.css:1.4 --- llvm/docs/doxygen.css:1.3 Tue Jun 1 13:19:28 2004 +++ llvm/docs/doxygen.css Mon May 15 16:36:13 2006 @@ -1,74 +1,323 @@ -BODY { background: white; color: black; font-family: Verdana,Arial,sans-serif; } -H1 { text-align: center; } -H2 { text-align: center; } -H3 { text-align: center; } +BODY,H1,H2,H3,H4,H5,H6,P,CENTER,TD,TH,UL,DL,DIV { + font-family: Verdana,Geneva,Arial,Helvetica,sans-serif; +} +BODY,TD { + font-size: 90%; +} +H1 { + text-align: center; + font-size: 140%; + font-weight: bold; +} +H2 { + font-size: 120%; + font-style: italic; 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See + * "doxygen --help" for details. What follows are CSS overrides for LLVM + * specific formatting. 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-Copyright © 2003,2004 University of Illinois at Urbana-Champaign. All -Rights Reserved.

- +Generated on $datetime for $projectname by +Doxygen$doxygenversion
+Copyright © 2003,2004,2005,2006 University of Illinois at Urbana-Champaign. +All Rights Reserved.

From reid at x10sys.com Mon May 15 17:12:54 2006 From: reid at x10sys.com (Reid Spencer) Date: Mon, 15 May 2006 17:12:54 -0500 Subject: [llvm-commits] CVS: llvm/lib/Support/FileUtilities.cpp Message-ID: <200605152212.RAA05276@zion.cs.uiuc.edu> Changes in directory llvm/lib/Support: FileUtilities.cpp updated: 1.46 -> 1.47 --- Log message: For PR777: http://llvm.cs.uiuc.edu/PR777 : Add an additional catch block to ensure that this function can't throw any exceptions, even one's we're not expecting. --- Diffs of the changes: (+3 -0) FileUtilities.cpp | 3 +++ 1 files changed, 3 insertions(+) Index: llvm/lib/Support/FileUtilities.cpp diff -u llvm/lib/Support/FileUtilities.cpp:1.46 llvm/lib/Support/FileUtilities.cpp:1.47 --- llvm/lib/Support/FileUtilities.cpp:1.46 Mon Aug 1 19:11:53 2005 +++ llvm/lib/Support/FileUtilities.cpp Mon May 15 17:12:42 2006 @@ -241,5 +241,8 @@ } catch (const std::string &Msg) { if (Error) *Error = Msg; return 2; + } catch (...) { + *Error = "Unknown Exception Occurred"; + return 2; } } From rafael.espindola at gmail.com Mon May 15 17:34:51 2006 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Mon, 15 May 2006 17:34:51 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp Message-ID: <200605152234.RAA05532@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/ARM: ARMISelDAGToDAG.cpp updated: 1.1 -> 1.2 --- Log message: add an abort after every assert(0) --- Diffs of the changes: (+2 -0) ARMISelDAGToDAG.cpp | 2 ++ 1 files changed, 2 insertions(+) Index: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp diff -u llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.1 llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.2 --- llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.1 Sun May 14 17:18:28 2006 +++ llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp Mon May 15 17:34:39 2006 @@ -62,6 +62,7 @@ bool isTailCall, SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG) { assert(0 && "Not implemented"); + abort(); } static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) { @@ -84,6 +85,7 @@ switch (Op.getOpcode()) { default: assert(0 && "Should not custom lower this!"); + abort(); case ISD::RET: return LowerRET(Op, DAG); } From lattner at cs.uiuc.edu Mon May 15 23:20:36 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Mon, 15 May 2006 23:20:36 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp Message-ID: <200605160420.XAA15275@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.170 -> 1.171 --- Log message: Fit in 80 cols --- Diffs of the changes: (+3 -3) PPCISelLowering.cpp | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.170 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.171 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.170 Fri May 12 16:09:57 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Mon May 15 23:20:24 2006 @@ -1307,7 +1307,7 @@ unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1); enum { - OP_COPY = 0, // Copy, used for things like to say it is <0,1,2,3> + OP_COPY = 0, // Copy, used for things like to say it is <0,1,2,3> OP_VMRGHW, OP_VMRGLW, OP_VSPLTISW0, @@ -1978,9 +1978,9 @@ // free GPRs, then we can pass both halves of the i64 in registers. if (GPR_remaining > 0) { SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, - Args[i].first, DAG.getConstant(1, MVT::i32)); + Args[i].first, DAG.getConstant(1, MVT::i32)); SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, - Args[i].first, DAG.getConstant(0, MVT::i32)); + Args[i].first, DAG.getConstant(0, MVT::i32)); args_to_use.push_back(Hi); --GPR_remaining; if (GPR_remaining > 0) { From ghost at cs.msu.su Tue May 16 00:36:27 2006 From: ghost at cs.msu.su (Vladimir Prus) Date: Tue, 16 May 2006 00:36:27 -0500 Subject: [llvm-commits] CVS: llvm/CREDITS.TXT Message-ID: <200605160536.AAA23301@zion.cs.uiuc.edu> Changes in directory llvm: CREDITS.TXT updated: 1.53 -> 1.54 --- Log message: Add my homepage, as a test that commit access works --- Diffs of the changes: (+1 -0) CREDITS.TXT | 1 + 1 files changed, 1 insertion(+) Index: llvm/CREDITS.TXT diff -u llvm/CREDITS.TXT:1.53 llvm/CREDITS.TXT:1.54 --- llvm/CREDITS.TXT:1.53 Mon May 15 00:13:07 2006 +++ llvm/CREDITS.TXT Tue May 16 00:36:15 2006 @@ -137,6 +137,7 @@ D: Visual C++ compatibility fixes N: Vladimir Prus +W: http://vladimir_prus.blogspot.com E: ghost at cs.msu.su D: Made inst_iterator behave like a proper iterator, LowerConstantExprs pass From lattner at cs.uiuc.edu Tue May 16 00:50:09 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 16 May 2006 00:50:09 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <200605160550.AAA24666@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.373 -> 1.374 --- Log message: Legalize FORMAL_ARGUMENTS nodes correctly, we don't want to legalize them once for each argument. --- Diffs of the changes: (+11 -2) LegalizeDAG.cpp | 13 +++++++++++-- 1 files changed, 11 insertions(+), 2 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.373 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.374 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.373 Fri May 12 21:11:14 2006 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue May 16 00:49:56 2006 @@ -819,9 +819,18 @@ case ISD::FORMAL_ARGUMENTS: // The only option for this is to custom lower it. - Result = TLI.LowerOperation(Result, DAG); + Result = TLI.LowerOperation(Result.getValue(0), DAG); assert(Result.Val && "Target didn't custom lower ISD::FORMAL_ARGUMENTS!"); - break; + + // Since FORMAL_ARGUMENTS nodes produce multiple values, make sure to + // remember that we legalized all of them, so it doesn't get relegalized. + for (unsigned i = 0, e = Result.Val->getNumValues(); i != e; ++i) { + Tmp1 = LegalizeOp(Result.getValue(i)); + if (Op.ResNo == i) + Tmp2 = Tmp1; + AddLegalizedOperand(SDOperand(Node, i), Tmp1); + } + return Tmp2; case ISD::BUILD_VECTOR: switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { From lattner at cs.uiuc.edu Tue May 16 00:55:42 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 16 May 2006 00:55:42 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/MachineFunction.cpp Message-ID: <200605160555.AAA25383@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: MachineFunction.cpp updated: 1.91 -> 1.92 --- Log message: Print the vreg that livein physregs are live in --- Diffs of the changes: (+3 -0) MachineFunction.cpp | 3 +++ 1 files changed, 3 insertions(+) Index: llvm/lib/CodeGen/MachineFunction.cpp diff -u llvm/lib/CodeGen/MachineFunction.cpp:1.91 llvm/lib/CodeGen/MachineFunction.cpp:1.92 --- llvm/lib/CodeGen/MachineFunction.cpp:1.91 Fri May 12 01:33:48 2006 +++ llvm/lib/CodeGen/MachineFunction.cpp Tue May 16 00:55:30 2006 @@ -152,6 +152,9 @@ OS << " " << MRI->getName(I->first); else OS << " Reg #" << I->first; + + if (I->second) + OS << " in VR#" << I->second << " "; } OS << "\n"; } From lattner at cs.uiuc.edu Tue May 16 01:11:10 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 16 May 2006 01:11:10 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp SelectionDAGISel.cpp Message-ID: <200605160611.BAA26711@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: ScheduleDAG.cpp updated: 1.91 -> 1.92 SelectionDAGISel.cpp updated: 1.240 -> 1.241 --- Log message: Move function-live-in-handling code from the sdisel code to the scheduler. This code should be emitted after legalize, so it can't be in sdisel. Note that the EmitFunctionEntryCode hook should be updated to operate on the DAG. The X86 backend is the only one currently using this hook. --- Diffs of the changes: (+15 -14) ScheduleDAG.cpp | 14 ++++++++++++++ SelectionDAGISel.cpp | 15 +-------------- 2 files changed, 15 insertions(+), 14 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.91 llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.92 --- llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.91 Sat May 13 03:22:24 2006 +++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Tue May 16 01:10:57 2006 @@ -539,6 +539,20 @@ /// EmitSchedule - Emit the machine code in scheduled order. void ScheduleDAG::EmitSchedule() { + // If this is the first basic block in the function, and if it has live ins + // that need to be copied into vregs, emit the copies into the top of the + // block before emitting the code for the block. + MachineFunction &MF = DAG.getMachineFunction(); + if (&MF.front() == BB && MF.livein_begin() != MF.livein_end()) { + for (MachineFunction::livein_iterator LI = MF.livein_begin(), + E = MF.livein_end(); LI != E; ++LI) + if (LI->second) + MRI->copyRegToReg(*MF.begin(), MF.begin()->end(), LI->second, + LI->first, RegMap->getRegClass(LI->second)); + } + + + // Finally, emit the code for all of the scheduled instructions. std::map VRBaseMap; for (unsigned i = 0, e = Sequence.size(); i != e; i++) { if (SUnit *SU = Sequence[i]) { Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.240 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.241 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.240 Sat May 13 00:53:47 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue May 16 01:10:58 2006 @@ -3150,24 +3150,11 @@ } } - // Next, if the function has live ins that need to be copied into vregs, - // emit the copies now, into the top of the block. - MachineFunction &MF = SDL.DAG.getMachineFunction(); - if (MF.livein_begin() != MF.livein_end()) { - SSARegMap *RegMap = MF.getSSARegMap(); - const MRegisterInfo &MRI = *MF.getTarget().getRegisterInfo(); - for (MachineFunction::livein_iterator LI = MF.livein_begin(), - E = MF.livein_end(); LI != E; ++LI) - if (LI->second) - MRI.copyRegToReg(*MF.begin(), MF.begin()->end(), LI->second, - LI->first, RegMap->getRegClass(LI->second)); - } - // Finally, if the target has anything special to do, allow it to do so. + // FIXME: this should insert code into the DAG! EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction()); } - void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB, std::vector > &PHINodesToUpdate, FunctionLoweringInfo &FuncInfo) { From reid at x10sys.com Tue May 16 01:25:26 2006 From: reid at x10sys.com (Reid Spencer) Date: Tue, 16 May 2006 01:25:26 -0500 Subject: [llvm-commits] CVS: llvm/Makefile.rules Message-ID: <200605160625.BAA28060@zion.cs.uiuc.edu> Changes in directory llvm: Makefile.rules updated: 1.366 -> 1.367 --- Log message: When linking, make sure the project libraries are linked before the LLVM libraries. This ensures that the project's libraries (which most likely depend on LLVM libraries) come first on the command line and can thus be resolved by the LLVM libraries that appear later. --- Diffs of the changes: (+3 -3) Makefile.rules | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) Index: llvm/Makefile.rules diff -u llvm/Makefile.rules:1.366 llvm/Makefile.rules:1.367 --- llvm/Makefile.rules:1.366 Wed May 10 22:10:15 2006 +++ llvm/Makefile.rules Tue May 16 01:25:14 2006 @@ -641,7 +641,7 @@ #--------------------------------------------------------- # Some versions of gcc on Alpha produce too many symbols, so use a .a file ifeq ($(ARCH),Alpha) -USEDLIBS := $(subst LLVMCore, LLVMCore.a, $(USEDLIBS)) +USEDLIBS := $(subst LLVMCore, LLVMCore.a, $(USEDLIBS)) LLVMLIBS := $(subst LLVMCore, LLVMCore.a, $(LLVMLIBS)) CORE_IS_ARCHIVE := 1 else @@ -950,8 +950,8 @@ $(ToolBuildPath): $(ObjectsO) $(ProjLibsPaths) $(LLVMLibsPaths) $(Echo) Linking $(BuildMode) executable $(TOOLNAME) $(StripWarnMsg) - $(Verb) $(Link) -o $@ $(TOOLLINKOPTS) $(ObjectsO) $(LLVMLibsOptions) \ - $(ProjLibsOptions) $(ExtraLibs) $(TOOLLINKOPTSB) $(LIBS) + $(Verb) $(Link) -o $@ $(TOOLLINKOPTS) $(ObjectsO) $(ProjLibsOptions) \ + $(LLVMLibsOptions) $(ExtraLibs) $(TOOLLINKOPTSB) $(LIBS) $(Echo) ======= Finished Linking $(BuildMode) Executable $(TOOLNAME) \ $(StripWarnMsg) From reid at x10sys.com Tue May 16 01:27:43 2006 From: reid at x10sys.com (Reid Spencer) Date: Tue, 16 May 2006 01:27:43 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Module.h Message-ID: <200605160627.BAA28276@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm: Module.h updated: 1.70 -> 1.71 --- Log message: For PR778: http://llvm.cs.uiuc.edu/PR778 : Improve doxygenification of this header file. --- Diffs of the changes: (+143 -91) Module.h | 234 ++++++++++++++++++++++++++++++++++++++------------------------- 1 files changed, 143 insertions(+), 91 deletions(-) Index: llvm/include/llvm/Module.h diff -u llvm/include/llvm/Module.h:1.70 llvm/include/llvm/Module.h:1.71 --- llvm/include/llvm/Module.h:1.70 Wed Mar 8 12:38:51 2006 +++ llvm/include/llvm/Module.h Tue May 16 01:27:31 2006 @@ -7,12 +7,7 @@ // //===----------------------------------------------------------------------===// // -// This file contains the declarations for the Module class that is used to -// maintain all the information related to a VM module. -// -// A module also maintains a GlobalValRefMap object that is used to hold all -// constant references to global variables in the module. When a global -// variable is destroyed, it should have no entries in the GlobalValueRefMap. +/// @file This file contains the declarations for the Module class. // //===----------------------------------------------------------------------===// @@ -46,65 +41,121 @@ static iplist &getList(Module *M); }; +/// A Module instance is used to store all the information related to an +/// LLVM module. Modules are the top level container of all other LLVM +/// Intermediate Representation (IR) objects. Each module directly contains a +/// list of globals variables, a list of functions, a list of libraries (or +/// other modules) this module depends on, a symbol table, and various data +/// about the target's characteristics. +/// +/// A module maintains a GlobalValRefMap object that is used to hold all +/// constant references to global variables in the module. When a global +/// variable is destroyed, it should have no entries in the GlobalValueRefMap. +/// @brief The main container class for the LLVM Intermediate Representation. class Module { +/// @name Types And Enumerations +/// @{ public: + /// The type for the list of global variables. typedef iplist GlobalListType; + /// The type for the list of functions. typedef iplist FunctionListType; + + /// The type for the list of dependent libraries. typedef SetVector LibraryListType; - // Global Variable iterators. + /// The Global Variable iterator. typedef GlobalListType::iterator global_iterator; + /// The Global Variable constant iterator. typedef GlobalListType::const_iterator const_global_iterator; - // Function iterators. + /// The Function iterators. typedef FunctionListType::iterator iterator; + /// The Function constant iterator typedef FunctionListType::const_iterator const_iterator; - // Library list iterators. + /// The Library list iterator. typedef LibraryListType::const_iterator lib_iterator; + /// An enumeration for describing the endianess of the target machine. enum Endianness { AnyEndianness, LittleEndian, BigEndian }; + + /// An enumeration for describing the size of a pointer on the target machine. enum PointerSize { AnyPointerSize, Pointer32, Pointer64 }; +/// @} +/// @name Member Variables +/// @{ private: - GlobalListType GlobalList; // The Global Variables in the module - FunctionListType FunctionList; // The Functions in the module - LibraryListType LibraryList; // The Libraries needed by the module - std::string GlobalScopeAsm; // Inline Asm at global scope. - SymbolTable *SymTab; // Symbol Table for the module - std::string ModuleID; // Human readable identifier for the module - std::string TargetTriple; // Platform target triple Module compiled on - Endianness Endian; // Endianness assumed in the module - PointerSize PtrSize; // Pointer size assumed in the module + GlobalListType GlobalList; ///< The Global Variables in the module + FunctionListType FunctionList; ///< The Functions in the module + LibraryListType LibraryList; ///< The Libraries needed by the module + std::string GlobalScopeAsm; ///< Inline Asm at global scope. + SymbolTable *SymTab; ///< Symbol Table for the module + std::string ModuleID; ///< Human readable identifier for the module + std::string TargetTriple; ///< Platform target triple Module compiled on + Endianness Endian; ///< Endianness assumed in the module + PointerSize PtrSize; ///< Pointer size assumed in the module friend class Constant; +/// @} +/// @name Constructors +/// @{ public: + /// The Module constructor. Note that there is no default constructor. You + /// must provide a name for the module upon construction. Module(const std::string &ModuleID); + /// The module destructor. This will dropAllReferences. ~Module(); +/// @} +/// @name Module Level Accessors +/// @{ +public: + /// Get the module identifier which is, essentially, the name of the module. + /// @returns the module identifier as a string const std::string &getModuleIdentifier() const { return ModuleID; } - void setModuleIdentifier(const std::string &ID) { ModuleID = ID; } + /// Get the target triple which is a string describing the target host. + /// @returns a string containing the target triple. const std::string &getTargetTriple() const { return TargetTriple; } - void setTargetTriple(const std::string &T) { TargetTriple = T; } - /// Target endian information... + /// Get the target endian information. + /// @returns Endianess - an enumeration for the endianess of the target Endianness getEndianness() const { return Endian; } - void setEndianness(Endianness E) { Endian = E; } - /// Target Pointer Size information... + /// Get the target pointer size. + /// @returns PointerSize - an enumeration for the size of the target's pointer PointerSize getPointerSize() const { return PtrSize; } - void setPointerSize(PointerSize PS) { PtrSize = PS; } - // Access to any module-scope inline asm blocks. + /// Get any module-scope inline assembly blocks. + /// @returns a string containing the module-scope inline assembly blocks. const std::string &getModuleInlineAsm() const { return GlobalScopeAsm; } +/// @} +/// @name Module Level Mutators +/// @{ +public: + + /// Set the module identifier. + void setModuleIdentifier(const std::string &ID) { ModuleID = ID; } + + /// Set the target triple. + void setTargetTriple(const std::string &T) { TargetTriple = T; } + + /// Set the target endian information. + void setEndianness(Endianness E) { Endian = E; } + + /// Set the target pointer size. + void setPointerSize(PointerSize PS) { PtrSize = PS; } + + /// Set the module-scope inline assembly blocks. void setModuleInlineAsm(const std::string &Asm) { GlobalScopeAsm = Asm; } - //===--------------------------------------------------------------------===// - // Methods for easy access to the functions in the module. - // - +/// @} +/// @name Function Accessors +/// @{ +public: /// getOrInsertFunction - Look up the specified function in the module symbol /// table. If it does not exist, add a prototype for the function and return /// it. @@ -119,139 +170,140 @@ /// getFunction - Look up the specified function in the module symbol table. /// If it does not exist, return null. - /// Function *getFunction(const std::string &Name, const FunctionType *Ty); /// getMainFunction - This function looks up main efficiently. This is such a /// common case, that it is a method in Module. If main cannot be found, a /// null pointer is returned. - /// Function *getMainFunction(); /// getNamedFunction - Return the first function in the module with the /// specified name, of arbitrary type. This method returns null if a function /// with the specified name is not found. - /// Function *getNamedFunction(const std::string &Name); - //===--------------------------------------------------------------------===// - // Methods for easy access to the global variables in the module. - // - +/// @} +/// @name Global Variable Accessors +/// @{ +public: /// getGlobalVariable - Look up the specified global variable in the module /// symbol table. If it does not exist, return null. The type argument /// should be the underlying type of the global, i.e., it should not have /// the top-level PointerType, which represents the address of the global. /// If AllowInternal is set to true, this function will return types that /// have InternalLinkage. By default, these types are not returned. - /// GlobalVariable *getGlobalVariable(const std::string &Name, const Type *Ty, bool AllowInternal = false); /// getNamedGlobal - Return the first global variable in the module with the /// specified name, of arbitrary type. This method returns null if a global /// with the specified name is not found. - /// GlobalVariable *getNamedGlobal(const std::string &Name); - - //===--------------------------------------------------------------------===// - // Methods for easy access to the types in the module. - // - +/// @} +/// @name Type Accessors +/// @{ +public: /// addTypeName - Insert an entry in the symbol table mapping Str to Type. If /// there is already an entry for this name, true is returned and the symbol /// table is not modified. - /// bool addTypeName(const std::string &Name, const Type *Ty); /// getTypeName - If there is at least one entry in the symbol table for the /// specified type, return it. - /// std::string getTypeName(const Type *Ty) const; /// getTypeByName - Return the type with the specified name in this module, or /// null if there is none by that name. const Type *getTypeByName(const std::string &Name) const; - - //===--------------------------------------------------------------------===// - // Methods for direct access to the globals list, functions list, and symbol - // table. - // - - // Get the underlying elements of the Module. - const GlobalListType &getGlobalList() const { return GlobalList; } - GlobalListType &getGlobalList() { return GlobalList; } - const FunctionListType &getFunctionList() const { return FunctionList; } - FunctionListType &getFunctionList() { return FunctionList; } - - /// getSymbolTable() - Get access to the symbol table for the module, where - /// global variables and functions are identified. - /// - SymbolTable &getSymbolTable() { return *SymTab; } - const SymbolTable &getSymbolTable() const { return *SymTab; } - - - //===--------------------------------------------------------------------===// - // Module iterator forwarding functions - // - // Globals list interface +/// @} +/// @name Direct access to the globals list, functions list, and symbol table +/// @{ +public: + /// Get the Module's list of global variables (constant). + const GlobalListType &getGlobalList() const { return GlobalList; } + /// Get the Module's list of global variables. + GlobalListType &getGlobalList() { return GlobalList; } + /// Get the Module's list of functions (constant). + const FunctionListType &getFunctionList() const { return FunctionList; } + /// Get the Module's list of functions. + FunctionListType &getFunctionList() { return FunctionList; } + /// Get the symbol table of global variable and function identifiers + const SymbolTable &getSymbolTable() const { return *SymTab; } + /// Get the Module's symbol table of global variable and function identifiers. + SymbolTable &getSymbolTable() { return *SymTab; } + +/// @} +/// @name Global Variable Iteration +/// @{ +public: + /// Get an iterator to the first global variable global_iterator global_begin() { return GlobalList.begin(); } + /// Get a constant iterator to the first global variable const_global_iterator global_begin() const { return GlobalList.begin(); } + /// Get an iterator to the last global variable global_iterator global_end () { return GlobalList.end(); } + /// Get a constant iterator to the last global variable const_global_iterator global_end () const { return GlobalList.end(); } + /// Determine if the list of globals is empty. bool global_empty() const { return GlobalList.empty(); } - // FunctionList interface +/// @} +/// @name Function Iteration +/// @{ +public: + /// Get an iterator to the first function. iterator begin() { return FunctionList.begin(); } + /// Get a constant iterator to the first function. const_iterator begin() const { return FunctionList.begin(); } + /// Get an iterator to the last function. iterator end () { return FunctionList.end(); } + /// Get a constant iterator to the last function. const_iterator end () const { return FunctionList.end(); } - + /// Determine how many functions are in the Module's list of functions. size_t size() const { return FunctionList.size(); } + /// Determine if the list of functions is empty. bool empty() const { return FunctionList.empty(); } - //===--------------------------------------------------------------------===// - // List of dependent library access functions - +/// @} +/// @name Dependent Library Iteration +/// @{ +public: /// @brief Get a constant iterator to beginning of dependent library list. inline lib_iterator lib_begin() const { return LibraryList.begin(); } - /// @brief Get a constant iterator to end of dependent library list. inline lib_iterator lib_end() const { return LibraryList.end(); } - /// @brief Returns the number of items in the list of libraries. inline size_t lib_size() const { return LibraryList.size(); } - /// @brief Add a library to the list of dependent libraries inline void addLibrary(const std::string& Lib){ LibraryList.insert(Lib); } - /// @brief Remove a library from the list of dependent libraries inline void removeLibrary(const std::string& Lib) { LibraryList.remove(Lib); } - /// @brief Get all the libraries inline const LibraryListType& getLibraries() const { return LibraryList; } - //===--------------------------------------------------------------------===// - // Utility functions for printing and dumping Module objects - +/// @} +/// @name Utility functions for printing and dumping Module objects +/// @{ +public: + /// Print the module to an output stream void print(std::ostream &OS) const { print(OS, 0); } + /// Print the module to an output stream with AssemblyAnnotationWriter. void print(std::ostream &OS, AssemblyAnnotationWriter *AAW) const; - + /// Dump the module to std::cerr (for debugging). void dump() const; - - /// dropAllReferences() - This function causes all the subinstructions to "let - /// go" of all references that they are maintaining. This allows one to - /// 'delete' a whole class at a time, even though there may be circular - /// references... first all references are dropped, and all use counts go to - /// zero. Then everything is delete'd for real. Note that no operations are - /// valid on an object that has "dropped all references", except operator - /// delete. - /// + /// This function causes all the subinstructions to "let go" of all references + /// that they are maintaining. This allows one to 'delete' a whole class at + /// a time, even though there may be circular references... first all + /// references are dropped, and all use counts go to zero. Then everything + /// is delete'd for real. Note that no operations are valid on an object + /// that has "dropped all references", except operator delete. void dropAllReferences(); +/// @} }; +/// An iostream inserter for modules. inline std::ostream &operator<<(std::ostream &O, const Module &M) { M.print(O); return O; From ghost at cs.msu.su Tue May 16 01:39:48 2006 From: ghost at cs.msu.su (Vladimir Prus) Date: Tue, 16 May 2006 01:39:48 -0500 Subject: [llvm-commits] CVS: llvm/Makefile.rules Message-ID: <200605160639.BAA29276@zion.cs.uiuc.edu> Changes in directory llvm: Makefile.rules updated: 1.367 -> 1.368 --- Log message: Replace "../whatever.td" with "whatever.td", so that out-of-tree backends can just add lib/Target to TableGen includes. --- Diffs of the changes: (+2 -1) Makefile.rules | 3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index: llvm/Makefile.rules diff -u llvm/Makefile.rules:1.367 llvm/Makefile.rules:1.368 --- llvm/Makefile.rules:1.367 Tue May 16 01:25:14 2006 +++ llvm/Makefile.rules Tue May 16 01:39:36 2006 @@ -404,7 +404,8 @@ ProgInstall = $(INSTALL) $(Install.StripFlag) -m 0755 ScriptInstall = $(INSTALL) -m 0755 DataInstall = $(INSTALL) -m 0644 -TableGen = $(TBLGEN) -I $(PROJ_SRC_DIR) -I$(PROJ_SRC_ROOT)/include +TableGen = $(TBLGEN) -I $(PROJ_SRC_DIR) -I$(PROJ_SRC_ROOT)/include \ + -I $(PROJ_SRC_ROOT)/lib/Target Archive = $(AR) $(AR.Flags) LArchive = $(LLVMToolDir)/llvm-ar rcsf ifdef RANLIB From ghost at cs.msu.su Tue May 16 01:39:49 2006 From: ghost at cs.msu.su (Vladimir Prus) Date: Tue, 16 May 2006 01:39:49 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Target.td Message-ID: <200605160639.BAA29280@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target: Target.td updated: 1.80 -> 1.81 --- Log message: Replace "../whatever.td" with "whatever.td", so that out-of-tree backends can just add lib/Target to TableGen includes. --- Diffs of the changes: (+2 -2) Target.td | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/Target/Target.td diff -u llvm/lib/Target/Target.td:1.80 llvm/lib/Target/Target.td:1.81 --- llvm/lib/Target/Target.td:1.80 Mon May 15 13:35:02 2006 +++ llvm/lib/Target/Target.td Tue May 16 01:39:36 2006 @@ -118,7 +118,7 @@ //===----------------------------------------------------------------------===// // Pull in the common support for scheduling // -include "../TargetSchedule.td" +include "TargetSchedule.td" class Predicate; // Forward def @@ -327,4 +327,4 @@ //===----------------------------------------------------------------------===// // Pull in the common support for DAG isel generation // -include "../TargetSelectionDAG.td" +include "TargetSelectionDAG.td" From lattner at cs.uiuc.edu Tue May 16 01:44:11 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 16 May 2006 01:44:11 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGNodes.h Message-ID: <200605160644.BAA29768@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: SelectionDAGNodes.h updated: 1.130 -> 1.131 --- Log message: Add a chain to FORMAL_ARGUMENTS. --- Diffs of the changes: (+4 -3) SelectionDAGNodes.h | 7 ++++--- 1 files changed, 4 insertions(+), 3 deletions(-) Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.130 llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.131 --- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.130 Sat Apr 22 13:53:45 2006 +++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h Tue May 16 01:43:59 2006 @@ -115,12 +115,13 @@ // UNDEF - An undefined node UNDEF, - /// FORMAL_ARGUMENTS(CC#, ISVARARG) - This node represents the formal + /// FORMAL_ARGUMENTS(CHAIN, CC#, ISVARARG) - This node represents the formal /// arguments for a function. CC# is a Constant value indicating the /// calling convention of the function, and ISVARARG is a flag that /// indicates whether the function is varargs or not. This node has one - /// result value for each incoming argument, and is typically custom - /// legalized. + /// result value for each incoming argument, plus one for the output chain. + /// It must be custom legalized. + /// FORMAL_ARGUMENTS, // EXTRACT_ELEMENT - This is used to get the first or second (determined by From lattner at cs.uiuc.edu Tue May 16 01:45:48 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 16 May 2006 01:45:48 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Message-ID: <200605160645.BAA30044@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAGISel.cpp updated: 1.241 -> 1.242 --- Log message: Add a chain to FORMAL_ARGUMENTS. This is a minimal port of the X86 backend, it doesn't currently use/maintain the chain properly. Also, make the X86ISelLowering.cpp file 80-col clean. --- Diffs of the changes: (+4 -2) SelectionDAGISel.cpp | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.241 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.242 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.241 Tue May 16 01:10:58 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue May 16 01:45:34 2006 @@ -2349,6 +2349,7 @@ TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node. std::vector Ops; + Ops.push_back(DAG.getRoot()); Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy())); Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy())); @@ -2393,11 +2394,12 @@ } } - if (RetVals.size() == 0) - RetVals.push_back(MVT::isVoid); + RetVals.push_back(MVT::Other); // Create the node. SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, RetVals, Ops).Val; + + DAG.setRoot(SDOperand(Result, Result->getNumValues()-1)); // Set up the return result vector. Ops.clear(); From lattner at cs.uiuc.edu Tue May 16 01:45:48 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 16 May 2006 01:45:48 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp Message-ID: <200605160645.BAA30048@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.201 -> 1.202 --- Log message: Add a chain to FORMAL_ARGUMENTS. This is a minimal port of the X86 backend, it doesn't currently use/maintain the chain properly. Also, make the X86ISelLowering.cpp file 80-col clean. --- Diffs of the changes: (+34 -22) X86ISelLowering.cpp | 56 +++++++++++++++++++++++++++++++--------------------- 1 files changed, 34 insertions(+), 22 deletions(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.201 llvm/lib/Target/X86/X86ISelLowering.cpp:1.202 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.201 Fri May 12 16:12:22 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Tue May 16 01:45:34 2006 @@ -365,8 +365,8 @@ FormalArgs.clear(); FormalArgLocs.clear(); - // This sets BytesToPopOnReturn, BytesCallerReserves, etc. which have to be set - // before the rest of the function can be lowered. + // This sets BytesToPopOnReturn, BytesCallerReserves, etc. which have to be + // set before the rest of the function can be lowered. if (F.getCallingConv() == CallingConv::Fast && EnableFastCC) PreprocessFastCCArguments(Args, F, DAG); else @@ -522,14 +522,15 @@ } void X86TargetLowering::LowerCCCArguments(SDOperand Op, SelectionDAG &DAG) { - unsigned NumArgs = Op.Val->getNumValues(); + unsigned NumArgs = Op.Val->getNumValues() - 1; MachineFunction &MF = DAG.getMachineFunction(); for (unsigned i = 0; i < NumArgs; ++i) { std::pair Loc = FormalArgLocs[i]; SDOperand ArgValue; if (Loc.first.Kind == FALocInfo::StackFrameLoc) { - // Create the SelectionDAG nodes corresponding to a load from this parameter + // Create the SelectionDAG nodes corresponding to a load from this + // parameter. unsigned FI = FormalArgLocs[i].first.Loc; SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); ArgValue = DAG.getLoad(Op.Val->getValueType(i), @@ -676,7 +677,8 @@ unsigned CCReg = XMMArgRegs[i]; SDOperand RegToPass = RegValuesToPass[i]; assert(RegToPass.getValueType() == MVT::Vector); - unsigned NumElems = cast(*(RegToPass.Val->op_end()-2))->getValue(); + unsigned NumElems = + cast(*(RegToPass.Val->op_end()-2))->getValue(); MVT::ValueType EVT = cast(*(RegToPass.Val->op_end()-1))->getVT(); MVT::ValueType PVT = getVectorType(EVT, NumElems); SDOperand CCRegNode = DAG.getRegister(CCReg, PVT); @@ -1043,7 +1045,7 @@ void X86TargetLowering::LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG) { - unsigned NumArgs = Op.Val->getNumValues(); + unsigned NumArgs = Op.Val->getNumValues()-1; MachineFunction &MF = DAG.getMachineFunction(); for (unsigned i = 0; i < NumArgs; ++i) { @@ -1051,9 +1053,10 @@ std::pair Loc = FormalArgLocs[i]; SDOperand ArgValue; if (Loc.first.Kind == FALocInfo::StackFrameLoc) { - // Create the SelectionDAG nodes corresponding to a load from this parameter + // Create the SelectionDAG nodes corresponding to a load from this + // parameter. SDOperand FIN = DAG.getFrameIndex(Loc.first.Loc, MVT::i32); - ArgValue = DAG.getLoad(Op.Val->getValueType(i),DAG.getEntryNode(), FIN, + ArgValue = DAG.getLoad(Op.Val->getValueType(i), DAG.getEntryNode(), FIN, DAG.getSrcValue(NULL)); } else { // Must be a CopyFromReg @@ -1064,10 +1067,11 @@ if (Loc.second.Kind != FALocInfo::None) { SDOperand ArgValue2; if (Loc.second.Kind == FALocInfo::StackFrameLoc) { - // Create the SelectionDAG nodes corresponding to a load from this parameter + // Create the SelectionDAG nodes corresponding to a load from this + // parameter. SDOperand FIN = DAG.getFrameIndex(Loc.second.Loc, MVT::i32); - ArgValue2 = DAG.getLoad(Op.Val->getValueType(i),DAG.getEntryNode(), FIN, - DAG.getSrcValue(NULL)); + ArgValue2 = DAG.getLoad(Op.Val->getValueType(i), DAG.getEntryNode(), + FIN, DAG.getSrcValue(NULL)); } else { // Must be a CopyFromReg ArgValue2 = DAG.getCopyFromReg(DAG.getEntryNode(), @@ -1263,7 +1267,8 @@ Ops.push_back(InFlag); // FIXME: Do not generate X86ISD::TAILCALL for now. - Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL, NodeTys, Ops); + Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL, + NodeTys, Ops); InFlag = Chain.getValue(1); NodeTys.clear(); @@ -2812,10 +2817,12 @@ } } - SDOperand LoShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, - DAG.getNode(ISD::BUILD_VECTOR, MaskVT, LoMask)); - SDOperand HiShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, - DAG.getNode(ISD::BUILD_VECTOR, MaskVT, HiMask)); + SDOperand LoShuffle = + DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, + DAG.getNode(ISD::BUILD_VECTOR, MaskVT, LoMask)); + SDOperand HiShuffle = + DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, + DAG.getNode(ISD::BUILD_VECTOR, MaskVT, HiMask)); std::vector MaskOps; for (unsigned i = 0; i != NumElems; ++i) { if (Locs[i].first == -1) { @@ -2978,12 +2985,14 @@ X86TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) { GlobalValue *GV = cast(Op)->getGlobal(); SDOperand Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), - DAG.getTargetGlobalAddress(GV, getPointerTy())); + DAG.getTargetGlobalAddress(GV, + getPointerTy())); if (Subtarget->isTargetDarwin()) { // With PIC, the address is actually $g + Offset. if (getTargetMachine().getRelocationModel() == Reloc::PIC) Result = DAG.getNode(ISD::ADD, getPointerTy(), - DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), Result); + DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), + Result); // For Darwin, external and weak symbols are indirect, so we want to load // the value at address GV, not the value of GV itself. This means that @@ -3002,12 +3011,14 @@ X86TargetLowering::LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG) { const char *Sym = cast(Op)->getSymbol(); SDOperand Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), - DAG.getTargetExternalSymbol(Sym, getPointerTy())); + DAG.getTargetExternalSymbol(Sym, + getPointerTy())); if (Subtarget->isTargetDarwin()) { // With PIC, the address is actually $g + Offset. if (getTargetMachine().getRelocationModel() == Reloc::PIC) Result = DAG.getNode(ISD::ADD, getPointerTy(), - DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), Result); + DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), + Result); } return Result; @@ -3391,7 +3402,8 @@ // With PIC, the address is actually $g + Offset. if (getTargetMachine().getRelocationModel() == Reloc::PIC) Result = DAG.getNode(ISD::ADD, getPointerTy(), - DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), Result); + DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), + Result); } return Result; @@ -3494,7 +3506,7 @@ SDOperand X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) { if (FormalArgs.size() == 0) { - unsigned CC = cast(Op.getOperand(0))->getValue(); + unsigned CC = cast(Op.getOperand(1))->getValue(); if (CC == CallingConv::Fast && EnableFastCC) LowerFastCCArguments(Op, DAG); else From lattner at cs.uiuc.edu Tue May 16 01:46:02 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 16 May 2006 01:46:02 -0500 Subject: [llvm-commits] CVS: llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp Message-ID: <200605160646.BAA30080@zion.cs.uiuc.edu> Changes in directory llvm/lib/ExecutionEngine/JIT: JITEmitter.cpp updated: 1.101 -> 1.102 --- Log message: Make this print the right start pointer --- Diffs of the changes: (+4 -2) JITEmitter.cpp | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-) Index: llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp diff -u llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.101 llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.102 --- llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.101 Fri May 12 13:10:12 2006 +++ llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp Tue May 16 01:45:50 2006 @@ -815,9 +815,11 @@ } } - DEBUG(std::cerr << "JIT: Finished CodeGen of [" << (void*)BufferBegin + DEBUG(void *FnStart = TheJIT->getPointerToGlobalIfAvailable(F.getFunction()); + char *FnEnd = (char*)getCurrentPCOffset(); + std::cerr << "JIT: Finished CodeGen of [" << FnStart << "] Function: " << F.getFunction()->getName() - << ": " << getCurrentPCOffset() << " bytes of text, " + << ": " << (FnEnd-(char*)FnStart) << " bytes of text, " << Relocations.size() << " relocations\n"); Relocations.clear(); return false; From reid at x10sys.com Tue May 16 01:51:14 2006 From: reid at x10sys.com (Reid Spencer) Date: Tue, 16 May 2006 01:51:14 -0500 Subject: [llvm-commits] CVS: llvm/Makefile.rules Message-ID: <200605160651.BAA30650@zion.cs.uiuc.edu> Changes in directory llvm: Makefile.rules updated: 1.368 -> 1.369 --- Log message: Make sure that $(CXX.Flags) is passed to the linker so that the same options with which source is compiled are used when linking. This matters when a project is using the LLVM makefiles and overrides CXXFLAGS to specify new flags to use. --- Diffs of the changes: (+2 -2) Makefile.rules | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/Makefile.rules diff -u llvm/Makefile.rules:1.368 llvm/Makefile.rules:1.369 --- llvm/Makefile.rules:1.368 Tue May 16 01:39:36 2006 +++ llvm/Makefile.rules Tue May 16 01:51:02 2006 @@ -396,9 +396,9 @@ $(CXX.Flags) Preprocess.CXX= $(CXX) $(CPP.Flags) $(CompileCommonOpts) $(CXX.Flags) -E Link = $(LIBTOOL) $(LibTool.Flags) --mode=link $(CXX) $(CPP.Flags) \ - $(CompileCommonOpts) $(LD.Flags) $(Strip) + $(CXX.Flags) $(CompileCommonOpts) $(LD.Flags) $(Strip) Relink = $(LIBTOOL) $(LibTool.Flags) --mode=link $(CXX) $(CPP.Flags) \ - $(CompileCommonOpts) $(Relink.Flags) + $(CXX.Flags) $(CompileCommonOpts) $(Relink.Flags) LTInstall = $(LIBTOOL) $(LibTool.Flags) --mode=install $(INSTALL) \ $(Install.Flags) ProgInstall = $(INSTALL) $(Install.StripFlag) -m 0755 From evan.cheng at apple.com Tue May 16 02:05:43 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 16 May 2006 02:05:43 -0500 Subject: [llvm-commits] CVS: llvm/utils/TableGen/CodeGenTarget.cpp CodeGenTarget.h DAGISelEmitter.cpp Message-ID: <200605160705.CAA31992@zion.cs.uiuc.edu> Changes in directory llvm/utils/TableGen: CodeGenTarget.cpp updated: 1.63 -> 1.64 CodeGenTarget.h updated: 1.25 -> 1.26 DAGISelEmitter.cpp updated: 1.202 -> 1.203 --- Log message: Allow patterns to refer to physical registers that belong to multiple register classes. --- Diffs of the changes: (+26 -6) CodeGenTarget.cpp | 17 +++++++++++++++++ CodeGenTarget.h | 4 ++++ DAGISelEmitter.cpp | 11 +++++------ 3 files changed, 26 insertions(+), 6 deletions(-) Index: llvm/utils/TableGen/CodeGenTarget.cpp diff -u llvm/utils/TableGen/CodeGenTarget.cpp:1.63 llvm/utils/TableGen/CodeGenTarget.cpp:1.64 --- llvm/utils/TableGen/CodeGenTarget.cpp:1.63 Mon Apr 10 17:02:59 2006 +++ llvm/utils/TableGen/CodeGenTarget.cpp Tue May 16 02:05:30 2006 @@ -163,6 +163,23 @@ RegisterClasses.assign(RegClasses.begin(), RegClasses.end()); } +std::vector CodeGenTarget::getRegisterVTs(Record *R) const { + std::vector Result; + const std::vector &RCs = getRegisterClasses(); + for (unsigned i = 0, e = RCs.size(); i != e; ++i) { + const CodeGenRegisterClass &RC = RegisterClasses[i]; + for (unsigned ei = 0, ee = RC.Elements.size(); ei != ee; ++ei) { + if (R == RC.Elements[ei]) { + const std::vector &InVTs = RC.getValueTypes(); + for (unsigned i = 0, e = InVTs.size(); i != e; ++i) + Result.push_back(InVTs[i]); + } + } + } + return Result; +} + + CodeGenRegisterClass::CodeGenRegisterClass(Record *R) : TheDef(R) { // Rename anonymous register classes. if (R->getName().size() > 9 && R->getName()[9] == '.') { Index: llvm/utils/TableGen/CodeGenTarget.h diff -u llvm/utils/TableGen/CodeGenTarget.h:1.25 llvm/utils/TableGen/CodeGenTarget.h:1.26 --- llvm/utils/TableGen/CodeGenTarget.h:1.25 Mon Mar 27 16:48:18 2006 +++ llvm/utils/TableGen/CodeGenTarget.h Tue May 16 02:05:30 2006 @@ -110,6 +110,10 @@ } return FoundRC; } + + /// getRegisterVTs - Find the union of all possible ValueTypes for the + /// specified physical register. + std::vector getRegisterVTs(Record *R) const; const std::vector &getLegalValueTypes() const { if (LegalValueTypes.empty()) ReadLegalValueTypes(); Index: llvm/utils/TableGen/DAGISelEmitter.cpp diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.202 llvm/utils/TableGen/DAGISelEmitter.cpp:1.203 --- llvm/utils/TableGen/DAGISelEmitter.cpp:1.202 Fri May 12 02:42:01 2006 +++ llvm/utils/TableGen/DAGISelEmitter.cpp Tue May 16 02:05:30 2006 @@ -565,12 +565,8 @@ } else if (R->isSubClassOf("Register")) { if (NotRegisters) return Unknown; - // If the register appears in exactly one regclass, and the regclass has one - // value type, use it as the known type. const CodeGenTarget &T = TP.getDAGISelEmitter().getTargetInfo(); - if (const CodeGenRegisterClass *RC = T.getRegisterClassForRegister(R)) - return ConvertVTs(RC->getValueTypes()); - return Unknown; + return T.getRegisterVTs(R); } else if (R->isSubClassOf("ValueType") || R->isSubClassOf("CondCode")) { // Using a VTSDNode or CondCodeSDNode. return Other; @@ -607,7 +603,10 @@ // At some point, it may make sense for this tree pattern to have // multiple types. Assert here that it does not, so we revisit this // code when appropriate. - assert(getExtTypes().size() == 1 && "TreePattern has too many types!"); + assert(getExtTypes().size() >= 1 && "TreePattern does not have a type!"); + MVT::ValueType VT = getTypeNum(0); + for (unsigned i = 1, e = getExtTypes().size(); i != e; ++i) + assert(getTypeNum(i) == VT && "TreePattern has too many types!"); unsigned Size = MVT::getSizeInBits(getTypeNum(0)); // Make sure that the value is representable for this type. From evan.cheng at apple.com Tue May 16 02:22:15 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 16 May 2006 02:22:15 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp X86CodeEmitter.cpp X86ISelDAGToDAG.cpp X86ISelLowering.cpp X86InstrInfo.td X86InstrMMX.td X86InstrSSE.td X86IntelAsmPrinter.cpp X86RegisterInfo.cpp X86RegisterInfo.td Message-ID: <200605160722.CAA06403@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ATTAsmPrinter.cpp updated: 1.46 -> 1.47 X86CodeEmitter.cpp updated: 1.106 -> 1.107 X86ISelDAGToDAG.cpp updated: 1.60 -> 1.61 X86ISelLowering.cpp updated: 1.202 -> 1.203 X86InstrInfo.td updated: 1.266 -> 1.267 X86InstrMMX.td updated: 1.11 -> 1.12 X86InstrSSE.td updated: 1.116 -> 1.117 X86IntelAsmPrinter.cpp updated: 1.49 -> 1.50 X86RegisterInfo.cpp updated: 1.152 -> 1.153 X86RegisterInfo.td updated: 1.34 -> 1.35 --- Log message: X86 integer register classes naming changes. Make them consistent with FP, vector classes. --- Diffs of the changes: (+854 -854) X86ATTAsmPrinter.cpp | 8 X86CodeEmitter.cpp | 6 X86ISelDAGToDAG.cpp | 6 X86ISelLowering.cpp | 24 X86InstrInfo.td | 1488 ++++++++++++++++++++++++------------------------- X86InstrMMX.td | 2 X86InstrSSE.td | 114 +-- X86IntelAsmPrinter.cpp | 8 X86RegisterInfo.cpp | 30 X86RegisterInfo.td | 22 10 files changed, 854 insertions(+), 854 deletions(-) Index: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp diff -u llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.46 llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.47 --- llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.46 Tue May 9 00:12:53 2006 +++ llvm/lib/Target/X86/X86ATTAsmPrinter.cpp Tue May 16 02:21:53 2006 @@ -360,14 +360,14 @@ // See if a truncate instruction can be turned into a nop. switch (MI->getOpcode()) { default: break; - case X86::TRUNC_R32_R16: - case X86::TRUNC_R32_R8: - case X86::TRUNC_R16_R8: { + case X86::TRUNC_GR32_GR16: + case X86::TRUNC_GR32_GR8: + case X86::TRUNC_GR16_GR8: { const MachineOperand &MO0 = MI->getOperand(0); const MachineOperand &MO1 = MI->getOperand(1); unsigned Reg0 = MO0.getReg(); unsigned Reg1 = MO1.getReg(); - if (MI->getOpcode() == X86::TRUNC_R32_R16) + if (MI->getOpcode() == X86::TRUNC_GR32_GR16) Reg1 = getX86SubSuperRegister(Reg1, MVT::i16); else Reg1 = getX86SubSuperRegister(Reg1, MVT::i8); Index: llvm/lib/Target/X86/X86CodeEmitter.cpp diff -u llvm/lib/Target/X86/X86CodeEmitter.cpp:1.106 llvm/lib/Target/X86/X86CodeEmitter.cpp:1.107 --- llvm/lib/Target/X86/X86CodeEmitter.cpp:1.106 Wed May 3 20:26:39 2006 +++ llvm/lib/Target/X86/X86CodeEmitter.cpp Tue May 16 02:21:53 2006 @@ -393,9 +393,9 @@ assert(0 && "psuedo instructions should be removed before code emission"); case X86::IMPLICIT_USE: case X86::IMPLICIT_DEF: - case X86::IMPLICIT_DEF_R8: - case X86::IMPLICIT_DEF_R16: - case X86::IMPLICIT_DEF_R32: + case X86::IMPLICIT_DEF_GR8: + case X86::IMPLICIT_DEF_GR16: + case X86::IMPLICIT_DEF_GR32: case X86::IMPLICIT_DEF_FR32: case X86::IMPLICIT_DEF_FR64: case X86::IMPLICIT_DEF_VR64: Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.60 llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.61 --- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.60 Fri May 12 14:03:56 2006 +++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Tue May 16 02:21:53 2006 @@ -509,7 +509,7 @@ SSARegMap *RegMap = BB->getParent()->getSSARegMap(); // FIXME: when we get to LP64, we will need to create the appropriate // type of register here. - GlobalBaseReg = RegMap->createVirtualRegister(X86::R32RegisterClass); + GlobalBaseReg = RegMap->createVirtualRegister(X86::GR32RegisterClass); BuildMI(FirstMBB, MBBI, X86::MovePCtoStack, 0); BuildMI(FirstMBB, MBBI, X86::POP32r, 1, GlobalBaseReg); } @@ -801,12 +801,12 @@ case MVT::i16: Opc = X86::MOV16to16_; VT = MVT::i16; - Opc2 = X86::TRUNC_R16_R8; + Opc2 = X86::TRUNC_GR16_GR8; break; case MVT::i32: Opc = X86::MOV32to32_; VT = MVT::i32; - Opc2 = X86::TRUNC_R32_R8; + Opc2 = X86::TRUNC_GR32_GR8; break; } Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.202 llvm/lib/Target/X86/X86ISelLowering.cpp:1.203 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.202 Tue May 16 01:45:34 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Tue May 16 02:21:53 2006 @@ -67,9 +67,9 @@ addLegalAddressScale(3); // Set up the register classes. - addRegisterClass(MVT::i8, X86::R8RegisterClass); - addRegisterClass(MVT::i16, X86::R16RegisterClass); - addRegisterClass(MVT::i32, X86::R32RegisterClass); + addRegisterClass(MVT::i8, X86::GR8RegisterClass); + addRegisterClass(MVT::i16, X86::GR16RegisterClass); + addRegisterClass(MVT::i32, X86::GR32RegisterClass); // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this // operation. @@ -940,33 +940,33 @@ case MVT::i1: case MVT::i8: Reg = AddLiveIn(MF, NumIntRegs ? X86::DL : X86::AL, - X86::R8RegisterClass); + X86::GR8RegisterClass); Loc.first.Kind = FALocInfo::LiveInRegLoc; Loc.first.Loc = Reg; Loc.first.Typ = MVT::i8; break; case MVT::i16: Reg = AddLiveIn(MF, NumIntRegs ? X86::DX : X86::AX, - X86::R16RegisterClass); + X86::GR16RegisterClass); Loc.first.Kind = FALocInfo::LiveInRegLoc; Loc.first.Loc = Reg; Loc.first.Typ = MVT::i16; break; case MVT::i32: Reg = AddLiveIn(MF, NumIntRegs ? X86::EDX : X86::EAX, - X86::R32RegisterClass); + X86::GR32RegisterClass); Loc.first.Kind = FALocInfo::LiveInRegLoc; Loc.first.Loc = Reg; Loc.first.Typ = MVT::i32; break; case MVT::i64: Reg = AddLiveIn(MF, NumIntRegs ? X86::EDX : X86::EAX, - X86::R32RegisterClass); + X86::GR32RegisterClass); Loc.first.Kind = FALocInfo::LiveInRegLoc; Loc.first.Loc = Reg; Loc.first.Typ = MVT::i32; if (ObjIntRegs == 2) { - Reg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass); + Reg = AddLiveIn(MF, X86::EDX, X86::GR32RegisterClass); Loc.second.Kind = FALocInfo::LiveInRegLoc; Loc.second.Loc = Reg; Loc.second.Typ = MVT::i32; @@ -1563,7 +1563,7 @@ // Load the old value of the high byte of the control word... unsigned OldCW = - F->getSSARegMap()->createVirtualRegister(X86::R16RegisterClass); + F->getSSARegMap()->createVirtualRegister(X86::GR16RegisterClass); addFrameReference(BuildMI(BB, X86::MOV16rm, 4, OldCW), CWFrameIdx); // Set the high part to be round to zero... @@ -2558,7 +2558,7 @@ } } - // Take advantage of the fact R32 to VR128 scalar_to_vector (i.e. movd) + // Take advantage of the fact GR32 to VR128 scalar_to_vector (i.e. movd) // clears the upper bits. // FIXME: we can do the same for v4f32 case when we know both parts of // the lower half come from scalar_to_vector (loadf32). We should do @@ -2899,7 +2899,7 @@ SDOperand X86TargetLowering::LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) { - // Transform it so it match pinsrw which expects a 16-bit value in a R32 + // Transform it so it match pinsrw which expects a 16-bit value in a GR32 // as its second argument. MVT::ValueType VT = Op.getValueType(); MVT::ValueType BaseVT = MVT::getVectorBaseType(VT); @@ -2930,7 +2930,7 @@ Idx <<= 1; if (MVT::isFloatingPoint(N1.getValueType())) { if (N1.getOpcode() == ISD::LOAD) { - // Just load directly from f32mem to R32. + // Just load directly from f32mem to GR32. N1 = DAG.getLoad(MVT::i32, N1.getOperand(0), N1.getOperand(1), N1.getOperand(2)); } else { Index: llvm/lib/Target/X86/X86InstrInfo.td diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.266 llvm/lib/Target/X86/X86InstrInfo.td:1.267 --- llvm/lib/Target/X86/X86InstrInfo.td:1.266 Mon May 8 03:01:26 2006 +++ llvm/lib/Target/X86/X86InstrInfo.td Tue May 16 02:21:53 2006 @@ -97,7 +97,7 @@ class X86MemOperand : Operand { let PrintMethod = printMethod; let NumMIOperands = 4; - let MIOperandInfo = (ops R32, i8imm, R32, i32imm); + let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm); } def i8mem : X86MemOperand<"printi8mem">; @@ -343,27 +343,27 @@ [(X86callseq_end imm:$amt1, imm:$amt2)]>; def IMPLICIT_USE : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_USE", []>; def IMPLICIT_DEF : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_DEF", []>; -def IMPLICIT_DEF_R8 : I<0, Pseudo, (ops R8:$dst), +def IMPLICIT_DEF_GR8 : I<0, Pseudo, (ops GR8:$dst), "#IMPLICIT_DEF $dst", - [(set R8:$dst, (undef))]>; -def IMPLICIT_DEF_R16 : I<0, Pseudo, (ops R16:$dst), + [(set GR8:$dst, (undef))]>; +def IMPLICIT_DEF_GR16 : I<0, Pseudo, (ops GR16:$dst), "#IMPLICIT_DEF $dst", - [(set R16:$dst, (undef))]>; -def IMPLICIT_DEF_R32 : I<0, Pseudo, (ops R32:$dst), + [(set GR16:$dst, (undef))]>; +def IMPLICIT_DEF_GR32 : I<0, Pseudo, (ops GR32:$dst), "#IMPLICIT_DEF $dst", - [(set R32:$dst, (undef))]>; + [(set GR32:$dst, (undef))]>; // Nop def NOOP : I<0x90, RawFrm, (ops), "nop", []>; // Truncate -def TRUNC_R32_R8 : I<0x88, MRMDestReg, (ops R8:$dst, R32_:$src), +def TRUNC_GR32_GR8 : I<0x88, MRMDestReg, (ops GR8:$dst, GR32_:$src), "mov{b} {${src:trunc8}, $dst|$dst, ${src:trunc8}", []>; -def TRUNC_R16_R8 : I<0x88, MRMDestReg, (ops R8:$dst, R16_:$src), +def TRUNC_GR16_GR8 : I<0x88, MRMDestReg, (ops GR8:$dst, GR16_:$src), "mov{b} {${src:trunc8}, $dst|$dst, ${src:trunc8}}", []>; -def TRUNC_R32_R16 : I<0x89, MRMDestReg, (ops R16:$dst, R32:$src), +def TRUNC_GR32_GR16 : I<0x89, MRMDestReg, (ops GR16:$dst, GR32:$src), "mov{w} {${src:trunc16}, $dst|$dst, ${src:trunc16}}", - [(set R16:$dst, (trunc R32:$src))]>; + [(set GR16:$dst, (trunc GR32:$src))]>; //===----------------------------------------------------------------------===// // Control Flow Instructions... @@ -387,8 +387,8 @@ def JMP : IBr<0xE9, (ops brtarget:$dst), "jmp $dst", [(br bb:$dst)]>; let isBranch = 1, isTerminator = 1, noResults = 1, isBarrier = 1 in { - def JMP32r : I<0xFF, MRM4r, (ops R32:$dst), "jmp{l} {*}$dst", - [(brind R32:$dst)]>; + def JMP32r : I<0xFF, MRM4r, (ops GR32:$dst), "jmp{l} {*}$dst", + [(brind GR32:$dst)]>; def JMP32m : I<0xFF, MRM4m, (ops i32mem:$dst), "jmp{l} {*}$dst", [(brind (loadi32 addr:$dst))]>; } @@ -438,8 +438,8 @@ XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7] in { def CALLpcrel32 : I<0xE8, RawFrm, (ops i32imm:$dst), "call ${dst:call}", []>; - def CALL32r : I<0xFF, MRM2r, (ops R32:$dst), "call {*}$dst", - [(X86call R32:$dst)]>; + def CALL32r : I<0xFF, MRM2r, (ops GR32:$dst), "call {*}$dst", + [(X86call GR32:$dst)]>; def CALL32m : I<0xFF, MRM2m, (ops i32mem:$dst), "call {*}$dst", [(X86call (loadi32 addr:$dst))]>; } @@ -448,7 +448,7 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in def TAILJMPd : IBr<0xE9, (ops i32imm:$dst), "jmp ${dst:call} # TAIL CALL", []>; let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in - def TAILJMPr : I<0xFF, MRM4r, (ops R32:$dst), "jmp {*}$dst # TAIL CALL", []>; + def TAILJMPr : I<0xFF, MRM4r, (ops GR32:$dst), "jmp {*}$dst # TAIL CALL", []>; let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in def TAILJMPm : I<0xFF, MRM4m, (ops i32mem:$dst), "jmp {*}$dst # TAIL CALL", []>; @@ -459,7 +459,7 @@ // this until we have a more accurate way of tracking where the stack pointer is // within a function. let isTerminator = 1, isTwoAddress = 1 in - def ADJSTACKPTRri : Ii32<0x81, MRM0r, (ops R32:$dst, R32:$src1, i32imm:$src2), + def ADJSTACKPTRri : Ii32<0x81, MRM0r, (ops GR32:$dst, GR32:$src1, i32imm:$src2), "add{l} {$src2, $dst|$dst, $src2}", []>; //===----------------------------------------------------------------------===// @@ -468,53 +468,53 @@ def LEAVE : I<0xC9, RawFrm, (ops), "leave", []>, Imp<[EBP,ESP],[EBP,ESP]>; def POP32r : I<0x58, AddRegFrm, - (ops R32:$reg), "pop{l} $reg", []>, Imp<[ESP],[ESP]>; + (ops GR32:$reg), "pop{l} $reg", []>, Imp<[ESP],[ESP]>; def MovePCtoStack : I<0, Pseudo, (ops piclabel:$label), "call $label", []>; -let isTwoAddress = 1 in // R32 = bswap R32 +let isTwoAddress = 1 in // GR32 = bswap GR32 def BSWAP32r : I<0xC8, AddRegFrm, - (ops R32:$dst, R32:$src), + (ops GR32:$dst, GR32:$src), "bswap{l} $dst", - [(set R32:$dst, (bswap R32:$src))]>, TB; + [(set GR32:$dst, (bswap GR32:$src))]>, TB; -def XCHG8rr : I<0x86, MRMDestReg, // xchg R8, R8 - (ops R8:$src1, R8:$src2), +def XCHG8rr : I<0x86, MRMDestReg, // xchg GR8, GR8 + (ops GR8:$src1, GR8:$src2), "xchg{b} {$src2|$src1}, {$src1|$src2}", []>; -def XCHG16rr : I<0x87, MRMDestReg, // xchg R16, R16 - (ops R16:$src1, R16:$src2), +def XCHG16rr : I<0x87, MRMDestReg, // xchg GR16, GR16 + (ops GR16:$src1, GR16:$src2), "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize; -def XCHG32rr : I<0x87, MRMDestReg, // xchg R32, R32 - (ops R32:$src1, R32:$src2), +def XCHG32rr : I<0x87, MRMDestReg, // xchg GR32, GR32 + (ops GR32:$src1, GR32:$src2), "xchg{l} {$src2|$src1}, {$src1|$src2}", []>; def XCHG8mr : I<0x86, MRMDestMem, - (ops i8mem:$src1, R8:$src2), + (ops i8mem:$src1, GR8:$src2), "xchg{b} {$src2|$src1}, {$src1|$src2}", []>; def XCHG16mr : I<0x87, MRMDestMem, - (ops i16mem:$src1, R16:$src2), + (ops i16mem:$src1, GR16:$src2), "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize; def XCHG32mr : I<0x87, MRMDestMem, - (ops i32mem:$src1, R32:$src2), + (ops i32mem:$src1, GR32:$src2), "xchg{l} {$src2|$src1}, {$src1|$src2}", []>; def XCHG8rm : I<0x86, MRMSrcMem, - (ops R8:$src1, i8mem:$src2), + (ops GR8:$src1, i8mem:$src2), "xchg{b} {$src2|$src1}, {$src1|$src2}", []>; def XCHG16rm : I<0x87, MRMSrcMem, - (ops R16:$src1, i16mem:$src2), + (ops GR16:$src1, i16mem:$src2), "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize; def XCHG32rm : I<0x87, MRMSrcMem, - (ops R32:$src1, i32mem:$src2), + (ops GR32:$src1, i32mem:$src2), "xchg{l} {$src2|$src1}, {$src1|$src2}", []>; def LEA16r : I<0x8D, MRMSrcMem, - (ops R16:$dst, i32mem:$src), + (ops GR16:$dst, i32mem:$src), "lea{w} {$src|$dst}, {$dst|$src}", []>, OpSize; def LEA32r : I<0x8D, MRMSrcMem, - (ops R32:$dst, i32mem:$src), + (ops GR32:$dst, i32mem:$src), "lea{l} {$src|$dst}, {$dst|$src}", - [(set R32:$dst, leaaddr:$src)]>; + [(set GR32:$dst, leaaddr:$src)]>; def REP_MOVSB : I<0xA4, RawFrm, (ops), "{rep;movsb|rep movsb}", [(X86rep_movs i8)]>, @@ -589,21 +589,21 @@ //===----------------------------------------------------------------------===// // Move Instructions... // -def MOV8rr : I<0x88, MRMDestReg, (ops R8 :$dst, R8 :$src), +def MOV8rr : I<0x88, MRMDestReg, (ops GR8 :$dst, GR8 :$src), "mov{b} {$src, $dst|$dst, $src}", []>; -def MOV16rr : I<0x89, MRMDestReg, (ops R16:$dst, R16:$src), +def MOV16rr : I<0x89, MRMDestReg, (ops GR16:$dst, GR16:$src), "mov{w} {$src, $dst|$dst, $src}", []>, OpSize; -def MOV32rr : I<0x89, MRMDestReg, (ops R32:$dst, R32:$src), +def MOV32rr : I<0x89, MRMDestReg, (ops GR32:$dst, GR32:$src), "mov{l} {$src, $dst|$dst, $src}", []>; -def MOV8ri : Ii8 <0xB0, AddRegFrm, (ops R8 :$dst, i8imm :$src), +def MOV8ri : Ii8 <0xB0, AddRegFrm, (ops GR8 :$dst, i8imm :$src), "mov{b} {$src, $dst|$dst, $src}", - [(set R8:$dst, imm:$src)]>; -def MOV16ri : Ii16<0xB8, AddRegFrm, (ops R16:$dst, i16imm:$src), + [(set GR8:$dst, imm:$src)]>; +def MOV16ri : Ii16<0xB8, AddRegFrm, (ops GR16:$dst, i16imm:$src), "mov{w} {$src, $dst|$dst, $src}", - [(set R16:$dst, imm:$src)]>, OpSize; -def MOV32ri : Ii32<0xB8, AddRegFrm, (ops R32:$dst, i32imm:$src), + [(set GR16:$dst, imm:$src)]>, OpSize; +def MOV32ri : Ii32<0xB8, AddRegFrm, (ops GR32:$dst, i32imm:$src), "mov{l} {$src, $dst|$dst, $src}", - [(set R32:$dst, imm:$src)]>; + [(set GR32:$dst, imm:$src)]>; def MOV8mi : Ii8 <0xC6, MRM0m, (ops i8mem :$dst, i8imm :$src), "mov{b} {$src, $dst|$dst, $src}", [(store (i8 imm:$src), addr:$dst)]>; @@ -614,41 +614,41 @@ "mov{l} {$src, $dst|$dst, $src}", [(store (i32 imm:$src), addr:$dst)]>; -def MOV8rm : I<0x8A, MRMSrcMem, (ops R8 :$dst, i8mem :$src), +def MOV8rm : I<0x8A, MRMSrcMem, (ops GR8 :$dst, i8mem :$src), "mov{b} {$src, $dst|$dst, $src}", - [(set R8:$dst, (load addr:$src))]>; -def MOV16rm : I<0x8B, MRMSrcMem, (ops R16:$dst, i16mem:$src), + [(set GR8:$dst, (load addr:$src))]>; +def MOV16rm : I<0x8B, MRMSrcMem, (ops GR16:$dst, i16mem:$src), "mov{w} {$src, $dst|$dst, $src}", - [(set R16:$dst, (load addr:$src))]>, OpSize; -def MOV32rm : I<0x8B, MRMSrcMem, (ops R32:$dst, i32mem:$src), + [(set GR16:$dst, (load addr:$src))]>, OpSize; +def MOV32rm : I<0x8B, MRMSrcMem, (ops GR32:$dst, i32mem:$src), "mov{l} {$src, $dst|$dst, $src}", - [(set R32:$dst, (load addr:$src))]>; + [(set GR32:$dst, (load addr:$src))]>; -def MOV8mr : I<0x88, MRMDestMem, (ops i8mem :$dst, R8 :$src), +def MOV8mr : I<0x88, MRMDestMem, (ops i8mem :$dst, GR8 :$src), "mov{b} {$src, $dst|$dst, $src}", - [(store R8:$src, addr:$dst)]>; -def MOV16mr : I<0x89, MRMDestMem, (ops i16mem:$dst, R16:$src), + [(store GR8:$src, addr:$dst)]>; +def MOV16mr : I<0x89, MRMDestMem, (ops i16mem:$dst, GR16:$src), "mov{w} {$src, $dst|$dst, $src}", - [(store R16:$src, addr:$dst)]>, OpSize; -def MOV32mr : I<0x89, MRMDestMem, (ops i32mem:$dst, R32:$src), + [(store GR16:$src, addr:$dst)]>, OpSize; +def MOV32mr : I<0x89, MRMDestMem, (ops i32mem:$dst, GR32:$src), "mov{l} {$src, $dst|$dst, $src}", - [(store R32:$src, addr:$dst)]>; + [(store GR32:$src, addr:$dst)]>; //===----------------------------------------------------------------------===// // Fixed-Register Multiplication and Division Instructions... // // Extra precision multiplication -def MUL8r : I<0xF6, MRM4r, (ops R8:$src), "mul{b} $src", +def MUL8r : I<0xF6, MRM4r, (ops GR8:$src), "mul{b} $src", // FIXME: Used for 8-bit mul, ignore result upper 8 bits. // This probably ought to be moved to a def : Pat<> if the // syntax can be accepted. - [(set AL, (mul AL, R8:$src))]>, - Imp<[AL],[AX]>; // AL,AH = AL*R8 -def MUL16r : I<0xF7, MRM4r, (ops R16:$src), "mul{w} $src", []>, - Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*R16 -def MUL32r : I<0xF7, MRM4r, (ops R32:$src), "mul{l} $src", []>, - Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*R32 + [(set AL, (mul AL, GR8:$src))]>, + Imp<[AL],[AX]>; // AL,AH = AL*GR8 +def MUL16r : I<0xF7, MRM4r, (ops GR16:$src), "mul{w} $src", []>, + Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*GR16 +def MUL32r : I<0xF7, MRM4r, (ops GR32:$src), "mul{l} $src", []>, + Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*GR32 def MUL8m : I<0xF6, MRM4m, (ops i8mem :$src), "mul{b} $src", // FIXME: Used for 8-bit mul, ignore result upper 8 bits. @@ -662,12 +662,12 @@ def MUL32m : I<0xF7, MRM4m, (ops i32mem:$src), "mul{l} $src", []>, Imp<[EAX],[EAX,EDX]>;// EAX,EDX = EAX*[mem32] -def IMUL8r : I<0xF6, MRM5r, (ops R8:$src), "imul{b} $src", []>, - Imp<[AL],[AX]>; // AL,AH = AL*R8 -def IMUL16r : I<0xF7, MRM5r, (ops R16:$src), "imul{w} $src", []>, - Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*R16 -def IMUL32r : I<0xF7, MRM5r, (ops R32:$src), "imul{l} $src", []>, - Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*R32 +def IMUL8r : I<0xF6, MRM5r, (ops GR8:$src), "imul{b} $src", []>, + Imp<[AL],[AX]>; // AL,AH = AL*GR8 +def IMUL16r : I<0xF7, MRM5r, (ops GR16:$src), "imul{w} $src", []>, + Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*GR16 +def IMUL32r : I<0xF7, MRM5r, (ops GR32:$src), "imul{l} $src", []>, + Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*GR32 def IMUL8m : I<0xF6, MRM5m, (ops i8mem :$src), "imul{b} $src", []>, Imp<[AL],[AX]>; // AL,AH = AL*[mem8] def IMUL16m : I<0xF7, MRM5m, (ops i16mem:$src), @@ -678,11 +678,11 @@ Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*[mem32] // unsigned division/remainder -def DIV8r : I<0xF6, MRM6r, (ops R8:$src), // AX/r8 = AL,AH +def DIV8r : I<0xF6, MRM6r, (ops GR8:$src), // AX/r8 = AL,AH "div{b} $src", []>, Imp<[AX],[AX]>; -def DIV16r : I<0xF7, MRM6r, (ops R16:$src), // DX:AX/r16 = AX,DX +def DIV16r : I<0xF7, MRM6r, (ops GR16:$src), // DX:AX/r16 = AX,DX "div{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize; -def DIV32r : I<0xF7, MRM6r, (ops R32:$src), // EDX:EAX/r32 = EAX,EDX +def DIV32r : I<0xF7, MRM6r, (ops GR32:$src), // EDX:EAX/r32 = EAX,EDX "div{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>; def DIV8m : I<0xF6, MRM6m, (ops i8mem:$src), // AX/[mem8] = AL,AH "div{b} $src", []>, Imp<[AX],[AX]>; @@ -692,11 +692,11 @@ "div{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>; // Signed division/remainder. -def IDIV8r : I<0xF6, MRM7r, (ops R8:$src), // AX/r8 = AL,AH +def IDIV8r : I<0xF6, MRM7r, (ops GR8:$src), // AX/r8 = AL,AH "idiv{b} $src", []>, Imp<[AX],[AX]>; -def IDIV16r: I<0xF7, MRM7r, (ops R16:$src), // DX:AX/r16 = AX,DX +def IDIV16r: I<0xF7, MRM7r, (ops GR16:$src), // DX:AX/r16 = AX,DX "idiv{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize; -def IDIV32r: I<0xF7, MRM7r, (ops R32:$src), // EDX:EAX/r32 = EAX,EDX +def IDIV32r: I<0xF7, MRM7r, (ops GR32:$src), // EDX:EAX/r32 = EAX,EDX "idiv{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>; def IDIV8m : I<0xF6, MRM7m, (ops i8mem:$src), // AX/[mem8] = AL,AH "idiv{b} $src", []>, Imp<[AX],[AX]>; @@ -720,364 +720,364 @@ let isTwoAddress = 1 in { // Conditional moves -def CMOVB16rr : I<0x42, MRMSrcReg, // if , TB, OpSize; -def CMOVB16rm : I<0x42, MRMSrcMem, // if , TB, OpSize; -def CMOVB32rr : I<0x42, MRMSrcReg, // if , TB; -def CMOVB32rm : I<0x42, MRMSrcMem, // if , TB; -def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, R16 = R16 - (ops R16:$dst, R16:$src1, R16:$src2), +def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16 + (ops GR16:$dst, GR16:$src1, GR16:$src2), "cmovae {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (X86cmov R16:$src1, R16:$src2, + [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, X86_COND_AE))]>, TB, OpSize; -def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, R16 = [mem16] - (ops R16:$dst, R16:$src1, i16mem:$src2), +def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16] + (ops GR16:$dst, GR16:$src1, i16mem:$src2), "cmovae {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2), + [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), X86_COND_AE))]>, TB, OpSize; -def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, R32 = R32 - (ops R32:$dst, R32:$src1, R32:$src2), +def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32 + (ops GR32:$dst, GR32:$src1, GR32:$src2), "cmovae {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, + [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, X86_COND_AE))]>, TB; -def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, R32 = [mem32] - (ops R32:$dst, R32:$src1, i32mem:$src2), +def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32] + (ops GR32:$dst, GR32:$src1, i32mem:$src2), "cmovae {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2), + [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), X86_COND_AE))]>, TB; -def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, R16 = R16 - (ops R16:$dst, R16:$src1, R16:$src2), +def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16 + (ops GR16:$dst, GR16:$src1, GR16:$src2), "cmove {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (X86cmov R16:$src1, R16:$src2, + [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, X86_COND_E))]>, TB, OpSize; -def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, R16 = [mem16] - (ops R16:$dst, R16:$src1, i16mem:$src2), +def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16] + (ops GR16:$dst, GR16:$src1, i16mem:$src2), "cmove {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2), + [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), X86_COND_E))]>, TB, OpSize; -def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, R32 = R32 - (ops R32:$dst, R32:$src1, R32:$src2), +def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32 + (ops GR32:$dst, GR32:$src1, GR32:$src2), "cmove {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, + [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, X86_COND_E))]>, TB; -def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, R32 = [mem32] - (ops R32:$dst, R32:$src1, i32mem:$src2), +def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32] + (ops GR32:$dst, GR32:$src1, i32mem:$src2), "cmove {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2), + [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), X86_COND_E))]>, TB; -def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, R16 = R16 - (ops R16:$dst, R16:$src1, R16:$src2), +def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16 + (ops GR16:$dst, GR16:$src1, GR16:$src2), "cmovne {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (X86cmov R16:$src1, R16:$src2, + [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, X86_COND_NE))]>, TB, OpSize; -def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, R16 = [mem16] - (ops R16:$dst, R16:$src1, i16mem:$src2), +def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16] + (ops GR16:$dst, GR16:$src1, i16mem:$src2), "cmovne {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2), + [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), X86_COND_NE))]>, TB, OpSize; -def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, R32 = R32 - (ops R32:$dst, R32:$src1, R32:$src2), +def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32 + (ops GR32:$dst, GR32:$src1, GR32:$src2), "cmovne {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, + [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, X86_COND_NE))]>, TB; -def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, R32 = [mem32] - (ops R32:$dst, R32:$src1, i32mem:$src2), +def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32] + (ops GR32:$dst, GR32:$src1, i32mem:$src2), "cmovne {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2), + [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), X86_COND_NE))]>, TB; -def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, R16 = R16 - (ops R16:$dst, R16:$src1, R16:$src2), +def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16 + (ops GR16:$dst, GR16:$src1, GR16:$src2), "cmovbe {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (X86cmov R16:$src1, R16:$src2, + [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, X86_COND_BE))]>, TB, OpSize; -def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, R16 = [mem16] - (ops R16:$dst, R16:$src1, i16mem:$src2), +def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16] + (ops GR16:$dst, GR16:$src1, i16mem:$src2), "cmovbe {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2), + [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), X86_COND_BE))]>, TB, OpSize; -def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, R32 = R32 - (ops R32:$dst, R32:$src1, R32:$src2), +def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32 + (ops GR32:$dst, GR32:$src1, GR32:$src2), "cmovbe {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, + [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, X86_COND_BE))]>, TB; -def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, R32 = [mem32] - (ops R32:$dst, R32:$src1, i32mem:$src2), +def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32] + (ops GR32:$dst, GR32:$src1, i32mem:$src2), "cmovbe {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2), + [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), X86_COND_BE))]>, TB; -def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, R16 = R16 - (ops R16:$dst, R16:$src1, R16:$src2), +def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16 + (ops GR16:$dst, GR16:$src1, GR16:$src2), "cmova {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (X86cmov R16:$src1, R16:$src2, + [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, X86_COND_A))]>, TB, OpSize; -def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, R16 = [mem16] - (ops R16:$dst, R16:$src1, i16mem:$src2), +def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16] + (ops GR16:$dst, GR16:$src1, i16mem:$src2), "cmova {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2), + [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), X86_COND_A))]>, TB, OpSize; -def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, R32 = R32 - (ops R32:$dst, R32:$src1, R32:$src2), +def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32 + (ops GR32:$dst, GR32:$src1, GR32:$src2), "cmova {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, + [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, X86_COND_A))]>, TB; -def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, R32 = [mem32] - (ops R32:$dst, R32:$src1, i32mem:$src2), +def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32] + (ops GR32:$dst, GR32:$src1, i32mem:$src2), "cmova {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2), + [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), X86_COND_A))]>, TB; -def CMOVL16rr : I<0x4C, MRMSrcReg, // if , TB, OpSize; -def CMOVL16rm : I<0x4C, MRMSrcMem, // if , TB, OpSize; -def CMOVL32rr : I<0x4C, MRMSrcReg, // if , TB; -def CMOVL32rm : I<0x4C, MRMSrcMem, // if , TB; -def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, R16 = R16 - (ops R16:$dst, R16:$src1, R16:$src2), +def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16 + (ops GR16:$dst, GR16:$src1, GR16:$src2), "cmovge {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (X86cmov R16:$src1, R16:$src2, + [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, X86_COND_GE))]>, TB, OpSize; -def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, R16 = [mem16] - (ops R16:$dst, R16:$src1, i16mem:$src2), +def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16] + (ops GR16:$dst, GR16:$src1, i16mem:$src2), "cmovge {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2), + [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), X86_COND_GE))]>, TB, OpSize; -def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, R32 = R32 - (ops R32:$dst, R32:$src1, R32:$src2), +def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32 + (ops GR32:$dst, GR32:$src1, GR32:$src2), "cmovge {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, + [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, X86_COND_GE))]>, TB; -def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, R32 = [mem32] - (ops R32:$dst, R32:$src1, i32mem:$src2), +def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32] + (ops GR32:$dst, GR32:$src1, i32mem:$src2), "cmovge {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2), + [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), X86_COND_GE))]>, TB; -def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, R16 = R16 - (ops R16:$dst, R16:$src1, R16:$src2), +def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16 + (ops GR16:$dst, GR16:$src1, GR16:$src2), "cmovle {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (X86cmov R16:$src1, R16:$src2, + [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, X86_COND_LE))]>, TB, OpSize; -def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, R16 = [mem16] - (ops R16:$dst, R16:$src1, i16mem:$src2), +def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16] + (ops GR16:$dst, GR16:$src1, i16mem:$src2), "cmovle {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2), + [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), X86_COND_LE))]>, TB, OpSize; -def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, R32 = R32 - (ops R32:$dst, R32:$src1, R32:$src2), +def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32 + (ops GR32:$dst, GR32:$src1, GR32:$src2), "cmovle {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, + [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, X86_COND_LE))]>, TB; -def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, R32 = [mem32] - (ops R32:$dst, R32:$src1, i32mem:$src2), +def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32] + (ops GR32:$dst, GR32:$src1, i32mem:$src2), "cmovle {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2), + [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), X86_COND_LE))]>, TB; -def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, R16 = R16 - (ops R16:$dst, R16:$src1, R16:$src2), +def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16 + (ops GR16:$dst, GR16:$src1, GR16:$src2), "cmovg {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (X86cmov R16:$src1, R16:$src2, + [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, X86_COND_G))]>, TB, OpSize; -def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, R16 = [mem16] - (ops R16:$dst, R16:$src1, i16mem:$src2), +def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16] + (ops GR16:$dst, GR16:$src1, i16mem:$src2), "cmovg {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2), + [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), X86_COND_G))]>, TB, OpSize; -def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, R32 = R32 - (ops R32:$dst, R32:$src1, R32:$src2), +def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32 + (ops GR32:$dst, GR32:$src1, GR32:$src2), "cmovg {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, + [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, X86_COND_G))]>, TB; -def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, R32 = [mem32] - (ops R32:$dst, R32:$src1, i32mem:$src2), +def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32] + (ops GR32:$dst, GR32:$src1, i32mem:$src2), "cmovg {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2), + [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), X86_COND_G))]>, TB; -def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, R16 = R16 - (ops R16:$dst, R16:$src1, R16:$src2), +def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16 + (ops GR16:$dst, GR16:$src1, GR16:$src2), "cmovs {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (X86cmov R16:$src1, R16:$src2, + [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, X86_COND_S))]>, TB, OpSize; -def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, R16 = [mem16] - (ops R16:$dst, R16:$src1, i16mem:$src2), +def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16] + (ops GR16:$dst, GR16:$src1, i16mem:$src2), "cmovs {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2), + [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), X86_COND_S))]>, TB, OpSize; -def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, R32 = R32 - (ops R32:$dst, R32:$src1, R32:$src2), +def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32 + (ops GR32:$dst, GR32:$src1, GR32:$src2), "cmovs {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, + [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, X86_COND_S))]>, TB; -def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, R32 = [mem32] - (ops R32:$dst, R32:$src1, i32mem:$src2), +def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32] + (ops GR32:$dst, GR32:$src1, i32mem:$src2), "cmovs {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2), + [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), X86_COND_S))]>, TB; -def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, R16 = R16 - (ops R16:$dst, R16:$src1, R16:$src2), +def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16 + (ops GR16:$dst, GR16:$src1, GR16:$src2), "cmovns {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (X86cmov R16:$src1, R16:$src2, + [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, X86_COND_NS))]>, TB, OpSize; -def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, R16 = [mem16] - (ops R16:$dst, R16:$src1, i16mem:$src2), +def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16] + (ops GR16:$dst, GR16:$src1, i16mem:$src2), "cmovns {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2), + [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), X86_COND_NS))]>, TB, OpSize; -def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, R32 = R32 - (ops R32:$dst, R32:$src1, R32:$src2), +def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32 + (ops GR32:$dst, GR32:$src1, GR32:$src2), "cmovns {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, + [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, X86_COND_NS))]>, TB; -def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, R32 = [mem32] - (ops R32:$dst, R32:$src1, i32mem:$src2), +def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32] + (ops GR32:$dst, GR32:$src1, i32mem:$src2), "cmovns {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2), + [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), X86_COND_NS))]>, TB; -def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, R16 = R16 - (ops R16:$dst, R16:$src1, R16:$src2), +def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16 + (ops GR16:$dst, GR16:$src1, GR16:$src2), "cmovp {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (X86cmov R16:$src1, R16:$src2, + [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, X86_COND_P))]>, TB, OpSize; -def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, R16 = [mem16] - (ops R16:$dst, R16:$src1, i16mem:$src2), +def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16] + (ops GR16:$dst, GR16:$src1, i16mem:$src2), "cmovp {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2), + [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), X86_COND_P))]>, TB, OpSize; -def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, R32 = R32 - (ops R32:$dst, R32:$src1, R32:$src2), +def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32 + (ops GR32:$dst, GR32:$src1, GR32:$src2), "cmovp {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, + [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, X86_COND_P))]>, TB; -def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, R32 = [mem32] - (ops R32:$dst, R32:$src1, i32mem:$src2), +def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32] + (ops GR32:$dst, GR32:$src1, i32mem:$src2), "cmovp {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2), + [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), X86_COND_P))]>, TB; -def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, R16 = R16 - (ops R16:$dst, R16:$src1, R16:$src2), +def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16 + (ops GR16:$dst, GR16:$src1, GR16:$src2), "cmovnp {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (X86cmov R16:$src1, R16:$src2, + [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2, X86_COND_NP))]>, TB, OpSize; -def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, R16 = [mem16] - (ops R16:$dst, R16:$src1, i16mem:$src2), +def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16] + (ops GR16:$dst, GR16:$src1, i16mem:$src2), "cmovnp {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2), + [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), X86_COND_NP))]>, TB, OpSize; -def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, R32 = R32 - (ops R32:$dst, R32:$src1, R32:$src2), +def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32 + (ops GR32:$dst, GR32:$src1, GR32:$src2), "cmovnp {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, + [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, X86_COND_NP))]>, TB; -def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, R32 = [mem32] - (ops R32:$dst, R32:$src1, i32mem:$src2), +def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32] + (ops GR32:$dst, GR32:$src1, i32mem:$src2), "cmovnp {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2), + [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), X86_COND_NP))]>, TB; // unary instructions -def NEG8r : I<0xF6, MRM3r, (ops R8 :$dst, R8 :$src), "neg{b} $dst", - [(set R8:$dst, (ineg R8:$src))]>; -def NEG16r : I<0xF7, MRM3r, (ops R16:$dst, R16:$src), "neg{w} $dst", - [(set R16:$dst, (ineg R16:$src))]>, OpSize; -def NEG32r : I<0xF7, MRM3r, (ops R32:$dst, R32:$src), "neg{l} $dst", - [(set R32:$dst, (ineg R32:$src))]>; +def NEG8r : I<0xF6, MRM3r, (ops GR8 :$dst, GR8 :$src), "neg{b} $dst", + [(set GR8:$dst, (ineg GR8:$src))]>; +def NEG16r : I<0xF7, MRM3r, (ops GR16:$dst, GR16:$src), "neg{w} $dst", + [(set GR16:$dst, (ineg GR16:$src))]>, OpSize; +def NEG32r : I<0xF7, MRM3r, (ops GR32:$dst, GR32:$src), "neg{l} $dst", + [(set GR32:$dst, (ineg GR32:$src))]>; let isTwoAddress = 0 in { def NEG8m : I<0xF6, MRM3m, (ops i8mem :$dst), "neg{b} $dst", [(store (ineg (loadi8 addr:$dst)), addr:$dst)]>; @@ -1088,12 +1088,12 @@ } -def NOT8r : I<0xF6, MRM2r, (ops R8 :$dst, R8 :$src), "not{b} $dst", - [(set R8:$dst, (not R8:$src))]>; -def NOT16r : I<0xF7, MRM2r, (ops R16:$dst, R16:$src), "not{w} $dst", - [(set R16:$dst, (not R16:$src))]>, OpSize; -def NOT32r : I<0xF7, MRM2r, (ops R32:$dst, R32:$src), "not{l} $dst", - [(set R32:$dst, (not R32:$src))]>; +def NOT8r : I<0xF6, MRM2r, (ops GR8 :$dst, GR8 :$src), "not{b} $dst", + [(set GR8:$dst, (not GR8:$src))]>; +def NOT16r : I<0xF7, MRM2r, (ops GR16:$dst, GR16:$src), "not{w} $dst", + [(set GR16:$dst, (not GR16:$src))]>, OpSize; +def NOT32r : I<0xF7, MRM2r, (ops GR32:$dst, GR32:$src), "not{l} $dst", + [(set GR32:$dst, (not GR32:$src))]>; let isTwoAddress = 0 in { def NOT8m : I<0xF6, MRM2m, (ops i8mem :$dst), "not{b} $dst", [(store (not (loadi8 addr:$dst)), addr:$dst)]>; @@ -1104,13 +1104,13 @@ } // TODO: inc/dec is slow for P4, but fast for Pentium-M. -def INC8r : I<0xFE, MRM0r, (ops R8 :$dst, R8 :$src), "inc{b} $dst", - [(set R8:$dst, (add R8:$src, 1))]>; +def INC8r : I<0xFE, MRM0r, (ops GR8 :$dst, GR8 :$src), "inc{b} $dst", + [(set GR8:$dst, (add GR8:$src, 1))]>; let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. -def INC16r : I<0xFF, MRM0r, (ops R16:$dst, R16:$src), "inc{w} $dst", - [(set R16:$dst, (add R16:$src, 1))]>, OpSize; -def INC32r : I<0xFF, MRM0r, (ops R32:$dst, R32:$src), "inc{l} $dst", - [(set R32:$dst, (add R32:$src, 1))]>; +def INC16r : I<0xFF, MRM0r, (ops GR16:$dst, GR16:$src), "inc{w} $dst", + [(set GR16:$dst, (add GR16:$src, 1))]>, OpSize; +def INC32r : I<0xFF, MRM0r, (ops GR32:$dst, GR32:$src), "inc{l} $dst", + [(set GR32:$dst, (add GR32:$src, 1))]>; } let isTwoAddress = 0 in { def INC8m : I<0xFE, MRM0m, (ops i8mem :$dst), "inc{b} $dst", @@ -1121,13 +1121,13 @@ [(store (add (loadi32 addr:$dst), 1), addr:$dst)]>; } -def DEC8r : I<0xFE, MRM1r, (ops R8 :$dst, R8 :$src), "dec{b} $dst", - [(set R8:$dst, (add R8:$src, -1))]>; +def DEC8r : I<0xFE, MRM1r, (ops GR8 :$dst, GR8 :$src), "dec{b} $dst", + [(set GR8:$dst, (add GR8:$src, -1))]>; let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. -def DEC16r : I<0xFF, MRM1r, (ops R16:$dst, R16:$src), "dec{w} $dst", - [(set R16:$dst, (add R16:$src, -1))]>, OpSize; -def DEC32r : I<0xFF, MRM1r, (ops R32:$dst, R32:$src), "dec{l} $dst", - [(set R32:$dst, (add R32:$src, -1))]>; +def DEC16r : I<0xFF, MRM1r, (ops GR16:$dst, GR16:$src), "dec{w} $dst", + [(set GR16:$dst, (add GR16:$src, -1))]>, OpSize; +def DEC32r : I<0xFF, MRM1r, (ops GR32:$dst, GR32:$src), "dec{l} $dst", + [(set GR32:$dst, (add GR32:$src, -1))]>; } let isTwoAddress = 0 in { @@ -1142,68 +1142,68 @@ // Logical operators... let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y def AND8rr : I<0x20, MRMDestReg, - (ops R8 :$dst, R8 :$src1, R8 :$src2), + (ops GR8 :$dst, GR8 :$src1, GR8 :$src2), "and{b} {$src2, $dst|$dst, $src2}", - [(set R8:$dst, (and R8:$src1, R8:$src2))]>; + [(set GR8:$dst, (and GR8:$src1, GR8:$src2))]>; def AND16rr : I<0x21, MRMDestReg, - (ops R16:$dst, R16:$src1, R16:$src2), + (ops GR16:$dst, GR16:$src1, GR16:$src2), "and{w} {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (and R16:$src1, R16:$src2))]>, OpSize; + [(set GR16:$dst, (and GR16:$src1, GR16:$src2))]>, OpSize; def AND32rr : I<0x21, MRMDestReg, - (ops R32:$dst, R32:$src1, R32:$src2), + (ops GR32:$dst, GR32:$src1, GR32:$src2), "and{l} {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (and R32:$src1, R32:$src2))]>; + [(set GR32:$dst, (and GR32:$src1, GR32:$src2))]>; } def AND8rm : I<0x22, MRMSrcMem, - (ops R8 :$dst, R8 :$src1, i8mem :$src2), + (ops GR8 :$dst, GR8 :$src1, i8mem :$src2), "and{b} {$src2, $dst|$dst, $src2}", - [(set R8:$dst, (and R8:$src1, (load addr:$src2)))]>; + [(set GR8:$dst, (and GR8:$src1, (load addr:$src2)))]>; def AND16rm : I<0x23, MRMSrcMem, - (ops R16:$dst, R16:$src1, i16mem:$src2), + (ops GR16:$dst, GR16:$src1, i16mem:$src2), "and{w} {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (and R16:$src1, (load addr:$src2)))]>, OpSize; + [(set GR16:$dst, (and GR16:$src1, (load addr:$src2)))]>, OpSize; def AND32rm : I<0x23, MRMSrcMem, - (ops R32:$dst, R32:$src1, i32mem:$src2), + (ops GR32:$dst, GR32:$src1, i32mem:$src2), "and{l} {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (and R32:$src1, (load addr:$src2)))]>; + [(set GR32:$dst, (and GR32:$src1, (load addr:$src2)))]>; def AND8ri : Ii8<0x80, MRM4r, - (ops R8 :$dst, R8 :$src1, i8imm :$src2), + (ops GR8 :$dst, GR8 :$src1, i8imm :$src2), "and{b} {$src2, $dst|$dst, $src2}", - [(set R8:$dst, (and R8:$src1, imm:$src2))]>; + [(set GR8:$dst, (and GR8:$src1, imm:$src2))]>; def AND16ri : Ii16<0x81, MRM4r, - (ops R16:$dst, R16:$src1, i16imm:$src2), + (ops GR16:$dst, GR16:$src1, i16imm:$src2), "and{w} {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (and R16:$src1, imm:$src2))]>, OpSize; + [(set GR16:$dst, (and GR16:$src1, imm:$src2))]>, OpSize; def AND32ri : Ii32<0x81, MRM4r, - (ops R32:$dst, R32:$src1, i32imm:$src2), + (ops GR32:$dst, GR32:$src1, i32imm:$src2), "and{l} {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (and R32:$src1, imm:$src2))]>; + [(set GR32:$dst, (and GR32:$src1, imm:$src2))]>; def AND16ri8 : Ii8<0x83, MRM4r, - (ops R16:$dst, R16:$src1, i16i8imm:$src2), + (ops GR16:$dst, GR16:$src1, i16i8imm:$src2), "and{w} {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (and R16:$src1, i16immSExt8:$src2))]>, + [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2))]>, OpSize; def AND32ri8 : Ii8<0x83, MRM4r, - (ops R32:$dst, R32:$src1, i32i8imm:$src2), + (ops GR32:$dst, GR32:$src1, i32i8imm:$src2), "and{l} {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (and R32:$src1, i32immSExt8:$src2))]>; + [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2))]>; let isTwoAddress = 0 in { def AND8mr : I<0x20, MRMDestMem, - (ops i8mem :$dst, R8 :$src), + (ops i8mem :$dst, GR8 :$src), "and{b} {$src, $dst|$dst, $src}", - [(store (and (load addr:$dst), R8:$src), addr:$dst)]>; + [(store (and (load addr:$dst), GR8:$src), addr:$dst)]>; def AND16mr : I<0x21, MRMDestMem, - (ops i16mem:$dst, R16:$src), + (ops i16mem:$dst, GR16:$src), "and{w} {$src, $dst|$dst, $src}", - [(store (and (load addr:$dst), R16:$src), addr:$dst)]>, + [(store (and (load addr:$dst), GR16:$src), addr:$dst)]>, OpSize; def AND32mr : I<0x21, MRMDestMem, - (ops i32mem:$dst, R32:$src), + (ops i32mem:$dst, GR32:$src), "and{l} {$src, $dst|$dst, $src}", - [(store (and (load addr:$dst), R32:$src), addr:$dst)]>; + [(store (and (load addr:$dst), GR32:$src), addr:$dst)]>; def AND8mi : Ii8<0x80, MRM4m, (ops i8mem :$dst, i8imm :$src), "and{b} {$src, $dst|$dst, $src}", @@ -1230,52 +1230,52 @@ let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y -def OR8rr : I<0x08, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2), +def OR8rr : I<0x08, MRMDestReg, (ops GR8 :$dst, GR8 :$src1, GR8 :$src2), "or{b} {$src2, $dst|$dst, $src2}", - [(set R8:$dst, (or R8:$src1, R8:$src2))]>; -def OR16rr : I<0x09, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), + [(set GR8:$dst, (or GR8:$src1, GR8:$src2))]>; +def OR16rr : I<0x09, MRMDestReg, (ops GR16:$dst, GR16:$src1, GR16:$src2), "or{w} {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (or R16:$src1, R16:$src2))]>, OpSize; -def OR32rr : I<0x09, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), + [(set GR16:$dst, (or GR16:$src1, GR16:$src2))]>, OpSize; +def OR32rr : I<0x09, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "or{l} {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (or R32:$src1, R32:$src2))]>; + [(set GR32:$dst, (or GR32:$src1, GR32:$src2))]>; } -def OR8rm : I<0x0A, MRMSrcMem , (ops R8 :$dst, R8 :$src1, i8mem :$src2), +def OR8rm : I<0x0A, MRMSrcMem , (ops GR8 :$dst, GR8 :$src1, i8mem :$src2), "or{b} {$src2, $dst|$dst, $src2}", - [(set R8:$dst, (or R8:$src1, (load addr:$src2)))]>; -def OR16rm : I<0x0B, MRMSrcMem , (ops R16:$dst, R16:$src1, i16mem:$src2), + [(set GR8:$dst, (or GR8:$src1, (load addr:$src2)))]>; +def OR16rm : I<0x0B, MRMSrcMem , (ops GR16:$dst, GR16:$src1, i16mem:$src2), "or{w} {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (or R16:$src1, (load addr:$src2)))]>, OpSize; -def OR32rm : I<0x0B, MRMSrcMem , (ops R32:$dst, R32:$src1, i32mem:$src2), + [(set GR16:$dst, (or GR16:$src1, (load addr:$src2)))]>, OpSize; +def OR32rm : I<0x0B, MRMSrcMem , (ops GR32:$dst, GR32:$src1, i32mem:$src2), "or{l} {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (or R32:$src1, (load addr:$src2)))]>; + [(set GR32:$dst, (or GR32:$src1, (load addr:$src2)))]>; -def OR8ri : Ii8 <0x80, MRM1r, (ops R8 :$dst, R8 :$src1, i8imm:$src2), +def OR8ri : Ii8 <0x80, MRM1r, (ops GR8 :$dst, GR8 :$src1, i8imm:$src2), "or{b} {$src2, $dst|$dst, $src2}", - [(set R8:$dst, (or R8:$src1, imm:$src2))]>; -def OR16ri : Ii16<0x81, MRM1r, (ops R16:$dst, R16:$src1, i16imm:$src2), + [(set GR8:$dst, (or GR8:$src1, imm:$src2))]>; +def OR16ri : Ii16<0x81, MRM1r, (ops GR16:$dst, GR16:$src1, i16imm:$src2), "or{w} {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (or R16:$src1, imm:$src2))]>, OpSize; -def OR32ri : Ii32<0x81, MRM1r, (ops R32:$dst, R32:$src1, i32imm:$src2), + [(set GR16:$dst, (or GR16:$src1, imm:$src2))]>, OpSize; +def OR32ri : Ii32<0x81, MRM1r, (ops GR32:$dst, GR32:$src1, i32imm:$src2), "or{l} {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (or R32:$src1, imm:$src2))]>; + [(set GR32:$dst, (or GR32:$src1, imm:$src2))]>; -def OR16ri8 : Ii8<0x83, MRM1r, (ops R16:$dst, R16:$src1, i16i8imm:$src2), +def OR16ri8 : Ii8<0x83, MRM1r, (ops GR16:$dst, GR16:$src1, i16i8imm:$src2), "or{w} {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (or R16:$src1, i16immSExt8:$src2))]>, OpSize; -def OR32ri8 : Ii8<0x83, MRM1r, (ops R32:$dst, R32:$src1, i32i8imm:$src2), + [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2))]>, OpSize; +def OR32ri8 : Ii8<0x83, MRM1r, (ops GR32:$dst, GR32:$src1, i32i8imm:$src2), "or{l} {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (or R32:$src1, i32immSExt8:$src2))]>; + [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2))]>; let isTwoAddress = 0 in { - def OR8mr : I<0x08, MRMDestMem, (ops i8mem:$dst, R8:$src), + def OR8mr : I<0x08, MRMDestMem, (ops i8mem:$dst, GR8:$src), "or{b} {$src, $dst|$dst, $src}", - [(store (or (load addr:$dst), R8:$src), addr:$dst)]>; - def OR16mr : I<0x09, MRMDestMem, (ops i16mem:$dst, R16:$src), + [(store (or (load addr:$dst), GR8:$src), addr:$dst)]>; + def OR16mr : I<0x09, MRMDestMem, (ops i16mem:$dst, GR16:$src), "or{w} {$src, $dst|$dst, $src}", - [(store (or (load addr:$dst), R16:$src), addr:$dst)]>, OpSize; - def OR32mr : I<0x09, MRMDestMem, (ops i32mem:$dst, R32:$src), + [(store (or (load addr:$dst), GR16:$src), addr:$dst)]>, OpSize; + def OR32mr : I<0x09, MRMDestMem, (ops i32mem:$dst, GR32:$src), "or{l} {$src, $dst|$dst, $src}", - [(store (or (load addr:$dst), R32:$src), addr:$dst)]>; + [(store (or (load addr:$dst), GR32:$src), addr:$dst)]>; def OR8mi : Ii8<0x80, MRM1m, (ops i8mem :$dst, i8imm:$src), "or{b} {$src, $dst|$dst, $src}", [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst)]>; @@ -1298,67 +1298,67 @@ let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y def XOR8rr : I<0x30, MRMDestReg, - (ops R8 :$dst, R8 :$src1, R8 :$src2), + (ops GR8 :$dst, GR8 :$src1, GR8 :$src2), "xor{b} {$src2, $dst|$dst, $src2}", - [(set R8:$dst, (xor R8:$src1, R8:$src2))]>; + [(set GR8:$dst, (xor GR8:$src1, GR8:$src2))]>; def XOR16rr : I<0x31, MRMDestReg, - (ops R16:$dst, R16:$src1, R16:$src2), + (ops GR16:$dst, GR16:$src1, GR16:$src2), "xor{w} {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (xor R16:$src1, R16:$src2))]>, OpSize; + [(set GR16:$dst, (xor GR16:$src1, GR16:$src2))]>, OpSize; def XOR32rr : I<0x31, MRMDestReg, - (ops R32:$dst, R32:$src1, R32:$src2), + (ops GR32:$dst, GR32:$src1, GR32:$src2), "xor{l} {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (xor R32:$src1, R32:$src2))]>; + [(set GR32:$dst, (xor GR32:$src1, GR32:$src2))]>; } def XOR8rm : I<0x32, MRMSrcMem , - (ops R8 :$dst, R8:$src1, i8mem :$src2), + (ops GR8 :$dst, GR8:$src1, i8mem :$src2), "xor{b} {$src2, $dst|$dst, $src2}", - [(set R8:$dst, (xor R8:$src1, (load addr:$src2)))]>; + [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2)))]>; def XOR16rm : I<0x33, MRMSrcMem , - (ops R16:$dst, R16:$src1, i16mem:$src2), + (ops GR16:$dst, GR16:$src1, i16mem:$src2), "xor{w} {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (xor R16:$src1, (load addr:$src2)))]>, OpSize; + [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2)))]>, OpSize; def XOR32rm : I<0x33, MRMSrcMem , - (ops R32:$dst, R32:$src1, i32mem:$src2), + (ops GR32:$dst, GR32:$src1, i32mem:$src2), "xor{l} {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (xor R32:$src1, (load addr:$src2)))]>; + [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2)))]>; def XOR8ri : Ii8<0x80, MRM6r, - (ops R8:$dst, R8:$src1, i8imm:$src2), + (ops GR8:$dst, GR8:$src1, i8imm:$src2), "xor{b} {$src2, $dst|$dst, $src2}", - [(set R8:$dst, (xor R8:$src1, imm:$src2))]>; + [(set GR8:$dst, (xor GR8:$src1, imm:$src2))]>; def XOR16ri : Ii16<0x81, MRM6r, - (ops R16:$dst, R16:$src1, i16imm:$src2), + (ops GR16:$dst, GR16:$src1, i16imm:$src2), "xor{w} {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (xor R16:$src1, imm:$src2))]>, OpSize; + [(set GR16:$dst, (xor GR16:$src1, imm:$src2))]>, OpSize; def XOR32ri : Ii32<0x81, MRM6r, - (ops R32:$dst, R32:$src1, i32imm:$src2), + (ops GR32:$dst, GR32:$src1, i32imm:$src2), "xor{l} {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (xor R32:$src1, imm:$src2))]>; + [(set GR32:$dst, (xor GR32:$src1, imm:$src2))]>; def XOR16ri8 : Ii8<0x83, MRM6r, - (ops R16:$dst, R16:$src1, i16i8imm:$src2), + (ops GR16:$dst, GR16:$src1, i16i8imm:$src2), "xor{w} {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (xor R16:$src1, i16immSExt8:$src2))]>, + [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2))]>, OpSize; def XOR32ri8 : Ii8<0x83, MRM6r, - (ops R32:$dst, R32:$src1, i32i8imm:$src2), + (ops GR32:$dst, GR32:$src1, i32i8imm:$src2), "xor{l} {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (xor R32:$src1, i32immSExt8:$src2))]>; + [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2))]>; let isTwoAddress = 0 in { def XOR8mr : I<0x30, MRMDestMem, - (ops i8mem :$dst, R8 :$src), + (ops i8mem :$dst, GR8 :$src), "xor{b} {$src, $dst|$dst, $src}", - [(store (xor (load addr:$dst), R8:$src), addr:$dst)]>; + [(store (xor (load addr:$dst), GR8:$src), addr:$dst)]>; def XOR16mr : I<0x31, MRMDestMem, - (ops i16mem:$dst, R16:$src), + (ops i16mem:$dst, GR16:$src), "xor{w} {$src, $dst|$dst, $src}", - [(store (xor (load addr:$dst), R16:$src), addr:$dst)]>, + [(store (xor (load addr:$dst), GR16:$src), addr:$dst)]>, OpSize; def XOR32mr : I<0x31, MRMDestMem, - (ops i32mem:$dst, R32:$src), + (ops i32mem:$dst, GR32:$src), "xor{l} {$src, $dst|$dst, $src}", - [(store (xor (load addr:$dst), R32:$src), addr:$dst)]>; + [(store (xor (load addr:$dst), GR32:$src), addr:$dst)]>; def XOR8mi : Ii8<0x80, MRM6m, (ops i8mem :$dst, i8imm :$src), "xor{b} {$src, $dst|$dst, $src}", @@ -1384,26 +1384,26 @@ } // Shift instructions -def SHL8rCL : I<0xD2, MRM4r, (ops R8 :$dst, R8 :$src), +def SHL8rCL : I<0xD2, MRM4r, (ops GR8 :$dst, GR8 :$src), "shl{b} {%cl, $dst|$dst, %CL}", - [(set R8:$dst, (shl R8:$src, CL))]>, Imp<[CL],[]>; -def SHL16rCL : I<0xD3, MRM4r, (ops R16:$dst, R16:$src), + [(set GR8:$dst, (shl GR8:$src, CL))]>, Imp<[CL],[]>; +def SHL16rCL : I<0xD3, MRM4r, (ops GR16:$dst, GR16:$src), "shl{w} {%cl, $dst|$dst, %CL}", - [(set R16:$dst, (shl R16:$src, CL))]>, Imp<[CL],[]>, OpSize; -def SHL32rCL : I<0xD3, MRM4r, (ops R32:$dst, R32:$src), + [(set GR16:$dst, (shl GR16:$src, CL))]>, Imp<[CL],[]>, OpSize; +def SHL32rCL : I<0xD3, MRM4r, (ops GR32:$dst, GR32:$src), "shl{l} {%cl, $dst|$dst, %CL}", - [(set R32:$dst, (shl R32:$src, CL))]>, Imp<[CL],[]>; + [(set GR32:$dst, (shl GR32:$src, CL))]>, Imp<[CL],[]>; -def SHL8ri : Ii8<0xC0, MRM4r, (ops R8 :$dst, R8 :$src1, i8imm:$src2), +def SHL8ri : Ii8<0xC0, MRM4r, (ops GR8 :$dst, GR8 :$src1, i8imm:$src2), "shl{b} {$src2, $dst|$dst, $src2}", - [(set R8:$dst, (shl R8:$src1, (i8 imm:$src2)))]>; + [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>; let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. -def SHL16ri : Ii8<0xC1, MRM4r, (ops R16:$dst, R16:$src1, i8imm:$src2), +def SHL16ri : Ii8<0xC1, MRM4r, (ops GR16:$dst, GR16:$src1, i8imm:$src2), "shl{w} {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (shl R16:$src1, (i8 imm:$src2)))]>, OpSize; -def SHL32ri : Ii8<0xC1, MRM4r, (ops R32:$dst, R32:$src1, i8imm:$src2), + [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize; +def SHL32ri : Ii8<0xC1, MRM4r, (ops GR32:$dst, GR32:$src1, i8imm:$src2), "shl{l} {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (shl R32:$src1, (i8 imm:$src2)))]>; + [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>; } let isTwoAddress = 0 in { @@ -1431,25 +1431,25 @@ [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; } -def SHR8rCL : I<0xD2, MRM5r, (ops R8 :$dst, R8 :$src), +def SHR8rCL : I<0xD2, MRM5r, (ops GR8 :$dst, GR8 :$src), "shr{b} {%cl, $dst|$dst, %CL}", - [(set R8:$dst, (srl R8:$src, CL))]>, Imp<[CL],[]>; -def SHR16rCL : I<0xD3, MRM5r, (ops R16:$dst, R16:$src), + [(set GR8:$dst, (srl GR8:$src, CL))]>, Imp<[CL],[]>; +def SHR16rCL : I<0xD3, MRM5r, (ops GR16:$dst, GR16:$src), "shr{w} {%cl, $dst|$dst, %CL}", - [(set R16:$dst, (srl R16:$src, CL))]>, Imp<[CL],[]>, OpSize; -def SHR32rCL : I<0xD3, MRM5r, (ops R32:$dst, R32:$src), + [(set GR16:$dst, (srl GR16:$src, CL))]>, Imp<[CL],[]>, OpSize; +def SHR32rCL : I<0xD3, MRM5r, (ops GR32:$dst, GR32:$src), "shr{l} {%cl, $dst|$dst, %CL}", - [(set R32:$dst, (srl R32:$src, CL))]>, Imp<[CL],[]>; + [(set GR32:$dst, (srl GR32:$src, CL))]>, Imp<[CL],[]>; -def SHR8ri : Ii8<0xC0, MRM5r, (ops R8:$dst, R8:$src1, i8imm:$src2), +def SHR8ri : Ii8<0xC0, MRM5r, (ops GR8:$dst, GR8:$src1, i8imm:$src2), "shr{b} {$src2, $dst|$dst, $src2}", - [(set R8:$dst, (srl R8:$src1, (i8 imm:$src2)))]>; -def SHR16ri : Ii8<0xC1, MRM5r, (ops R16:$dst, R16:$src1, i8imm:$src2), + [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>; +def SHR16ri : Ii8<0xC1, MRM5r, (ops GR16:$dst, GR16:$src1, i8imm:$src2), "shr{w} {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (srl R16:$src1, (i8 imm:$src2)))]>, OpSize; -def SHR32ri : Ii8<0xC1, MRM5r, (ops R32:$dst, R32:$src1, i8imm:$src2), + [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize; +def SHR32ri : Ii8<0xC1, MRM5r, (ops GR32:$dst, GR32:$src1, i8imm:$src2), "shr{l} {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (srl R32:$src1, (i8 imm:$src2)))]>; + [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>; let isTwoAddress = 0 in { def SHR8mCL : I<0xD2, MRM5m, (ops i8mem :$dst), @@ -1476,26 +1476,26 @@ [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; } -def SAR8rCL : I<0xD2, MRM7r, (ops R8 :$dst, R8 :$src), +def SAR8rCL : I<0xD2, MRM7r, (ops GR8 :$dst, GR8 :$src), "sar{b} {%cl, $dst|$dst, %CL}", - [(set R8:$dst, (sra R8:$src, CL))]>, Imp<[CL],[]>; -def SAR16rCL : I<0xD3, MRM7r, (ops R16:$dst, R16:$src), + [(set GR8:$dst, (sra GR8:$src, CL))]>, Imp<[CL],[]>; +def SAR16rCL : I<0xD3, MRM7r, (ops GR16:$dst, GR16:$src), "sar{w} {%cl, $dst|$dst, %CL}", - [(set R16:$dst, (sra R16:$src, CL))]>, Imp<[CL],[]>, OpSize; -def SAR32rCL : I<0xD3, MRM7r, (ops R32:$dst, R32:$src), + [(set GR16:$dst, (sra GR16:$src, CL))]>, Imp<[CL],[]>, OpSize; +def SAR32rCL : I<0xD3, MRM7r, (ops GR32:$dst, GR32:$src), "sar{l} {%cl, $dst|$dst, %CL}", - [(set R32:$dst, (sra R32:$src, CL))]>, Imp<[CL],[]>; + [(set GR32:$dst, (sra GR32:$src, CL))]>, Imp<[CL],[]>; -def SAR8ri : Ii8<0xC0, MRM7r, (ops R8 :$dst, R8 :$src1, i8imm:$src2), +def SAR8ri : Ii8<0xC0, MRM7r, (ops GR8 :$dst, GR8 :$src1, i8imm:$src2), "sar{b} {$src2, $dst|$dst, $src2}", - [(set R8:$dst, (sra R8:$src1, (i8 imm:$src2)))]>; -def SAR16ri : Ii8<0xC1, MRM7r, (ops R16:$dst, R16:$src1, i8imm:$src2), + [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>; +def SAR16ri : Ii8<0xC1, MRM7r, (ops GR16:$dst, GR16:$src1, i8imm:$src2), "sar{w} {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (sra R16:$src1, (i8 imm:$src2)))]>, + [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>, OpSize; -def SAR32ri : Ii8<0xC1, MRM7r, (ops R32:$dst, R32:$src1, i8imm:$src2), +def SAR32ri : Ii8<0xC1, MRM7r, (ops GR32:$dst, GR32:$src1, i8imm:$src2), "sar{l} {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (sra R32:$src1, (i8 imm:$src2)))]>; + [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>; let isTwoAddress = 0 in { def SAR8mCL : I<0xD2, MRM7m, (ops i8mem :$dst), "sar{b} {%cl, $dst|$dst, %CL}", @@ -1523,25 +1523,25 @@ // Rotate instructions // FIXME: provide shorter instructions when imm8 == 1 -def ROL8rCL : I<0xD2, MRM0r, (ops R8 :$dst, R8 :$src), +def ROL8rCL : I<0xD2, MRM0r, (ops GR8 :$dst, GR8 :$src), "rol{b} {%cl, $dst|$dst, %CL}", - [(set R8:$dst, (rotl R8:$src, CL))]>, Imp<[CL],[]>; -def ROL16rCL : I<0xD3, MRM0r, (ops R16:$dst, R16:$src), + [(set GR8:$dst, (rotl GR8:$src, CL))]>, Imp<[CL],[]>; +def ROL16rCL : I<0xD3, MRM0r, (ops GR16:$dst, GR16:$src), "rol{w} {%cl, $dst|$dst, %CL}", - [(set R16:$dst, (rotl R16:$src, CL))]>, Imp<[CL],[]>, OpSize; -def ROL32rCL : I<0xD3, MRM0r, (ops R32:$dst, R32:$src), + [(set GR16:$dst, (rotl GR16:$src, CL))]>, Imp<[CL],[]>, OpSize; +def ROL32rCL : I<0xD3, MRM0r, (ops GR32:$dst, GR32:$src), "rol{l} {%cl, $dst|$dst, %CL}", - [(set R32:$dst, (rotl R32:$src, CL))]>, Imp<[CL],[]>; + [(set GR32:$dst, (rotl GR32:$src, CL))]>, Imp<[CL],[]>; -def ROL8ri : Ii8<0xC0, MRM0r, (ops R8 :$dst, R8 :$src1, i8imm:$src2), +def ROL8ri : Ii8<0xC0, MRM0r, (ops GR8 :$dst, GR8 :$src1, i8imm:$src2), "rol{b} {$src2, $dst|$dst, $src2}", - [(set R8:$dst, (rotl R8:$src1, (i8 imm:$src2)))]>; -def ROL16ri : Ii8<0xC1, MRM0r, (ops R16:$dst, R16:$src1, i8imm:$src2), + [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>; +def ROL16ri : Ii8<0xC1, MRM0r, (ops GR16:$dst, GR16:$src1, i8imm:$src2), "rol{w} {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (rotl R16:$src1, (i8 imm:$src2)))]>, OpSize; -def ROL32ri : Ii8<0xC1, MRM0r, (ops R32:$dst, R32:$src1, i8imm:$src2), + [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, OpSize; +def ROL32ri : Ii8<0xC1, MRM0r, (ops GR32:$dst, GR32:$src1, i8imm:$src2), "rol{l} {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (rotl R32:$src1, (i8 imm:$src2)))]>; + [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>; let isTwoAddress = 0 in { def ROL8mCL : I<0xD2, MRM0m, (ops i8mem :$dst), @@ -1568,25 +1568,25 @@ [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; } -def ROR8rCL : I<0xD2, MRM1r, (ops R8 :$dst, R8 :$src), +def ROR8rCL : I<0xD2, MRM1r, (ops GR8 :$dst, GR8 :$src), "ror{b} {%cl, $dst|$dst, %CL}", - [(set R8:$dst, (rotr R8:$src, CL))]>, Imp<[CL],[]>; -def ROR16rCL : I<0xD3, MRM1r, (ops R16:$dst, R16:$src), + [(set GR8:$dst, (rotr GR8:$src, CL))]>, Imp<[CL],[]>; +def ROR16rCL : I<0xD3, MRM1r, (ops GR16:$dst, GR16:$src), "ror{w} {%cl, $dst|$dst, %CL}", - [(set R16:$dst, (rotr R16:$src, CL))]>, Imp<[CL],[]>, OpSize; -def ROR32rCL : I<0xD3, MRM1r, (ops R32:$dst, R32:$src), + [(set GR16:$dst, (rotr GR16:$src, CL))]>, Imp<[CL],[]>, OpSize; +def ROR32rCL : I<0xD3, MRM1r, (ops GR32:$dst, GR32:$src), "ror{l} {%cl, $dst|$dst, %CL}", - [(set R32:$dst, (rotr R32:$src, CL))]>, Imp<[CL],[]>; + [(set GR32:$dst, (rotr GR32:$src, CL))]>, Imp<[CL],[]>; -def ROR8ri : Ii8<0xC0, MRM1r, (ops R8 :$dst, R8 :$src1, i8imm:$src2), +def ROR8ri : Ii8<0xC0, MRM1r, (ops GR8 :$dst, GR8 :$src1, i8imm:$src2), "ror{b} {$src2, $dst|$dst, $src2}", - [(set R8:$dst, (rotr R8:$src1, (i8 imm:$src2)))]>; -def ROR16ri : Ii8<0xC1, MRM1r, (ops R16:$dst, R16:$src1, i8imm:$src2), + [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>; +def ROR16ri : Ii8<0xC1, MRM1r, (ops GR16:$dst, GR16:$src1, i8imm:$src2), "ror{w} {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (rotr R16:$src1, (i8 imm:$src2)))]>, OpSize; -def ROR32ri : Ii8<0xC1, MRM1r, (ops R32:$dst, R32:$src1, i8imm:$src2), + [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>, OpSize; +def ROR32ri : Ii8<0xC1, MRM1r, (ops GR32:$dst, GR32:$src1, i8imm:$src2), "ror{l} {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (rotr R32:$src1, (i8 imm:$src2)))]>; + [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>; let isTwoAddress = 0 in { def ROR8mCL : I<0xD2, MRM1m, (ops i8mem :$dst), "ror{b} {%cl, $dst|$dst, %CL}", @@ -1615,94 +1615,94 @@ // Double shift instructions (generalizations of rotate) -def SHLD32rrCL : I<0xA5, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), +def SHLD32rrCL : I<0xA5, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}", - [(set R32:$dst, (X86shld R32:$src1, R32:$src2, CL))]>, + [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, Imp<[CL],[]>, TB; -def SHRD32rrCL : I<0xAD, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), +def SHRD32rrCL : I<0xAD, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}", - [(set R32:$dst, (X86shrd R32:$src1, R32:$src2, CL))]>, + [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, Imp<[CL],[]>, TB; -def SHLD16rrCL : I<0xA5, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), +def SHLD16rrCL : I<0xA5, MRMDestReg, (ops GR16:$dst, GR16:$src1, GR16:$src2), "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}", - [(set R16:$dst, (X86shld R16:$src1, R16:$src2, CL))]>, + [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>, Imp<[CL],[]>, TB, OpSize; -def SHRD16rrCL : I<0xAD, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), +def SHRD16rrCL : I<0xAD, MRMDestReg, (ops GR16:$dst, GR16:$src1, GR16:$src2), "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}", - [(set R16:$dst, (X86shrd R16:$src1, R16:$src2, CL))]>, + [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>, Imp<[CL],[]>, TB, OpSize; let isCommutable = 1 in { // These instructions commute to each other. def SHLD32rri8 : Ii8<0xA4, MRMDestReg, - (ops R32:$dst, R32:$src1, R32:$src2, i8imm:$src3), + (ops GR32:$dst, GR32:$src1, GR32:$src2, i8imm:$src3), "shld{l} {$src3, $src2, $dst|$dst, $src2, $src3}", - [(set R32:$dst, (X86shld R32:$src1, R32:$src2, + [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, (i8 imm:$src3)))]>, TB; def SHRD32rri8 : Ii8<0xAC, MRMDestReg, - (ops R32:$dst, R32:$src1, R32:$src2, i8imm:$src3), + (ops GR32:$dst, GR32:$src1, GR32:$src2, i8imm:$src3), "shrd{l} {$src3, $src2, $dst|$dst, $src2, $src3}", - [(set R32:$dst, (X86shrd R32:$src1, R32:$src2, + [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, (i8 imm:$src3)))]>, TB; def SHLD16rri8 : Ii8<0xA4, MRMDestReg, - (ops R16:$dst, R16:$src1, R16:$src2, i8imm:$src3), + (ops GR16:$dst, GR16:$src1, GR16:$src2, i8imm:$src3), "shld{w} {$src3, $src2, $dst|$dst, $src2, $src3}", - [(set R16:$dst, (X86shld R16:$src1, R16:$src2, + [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, (i8 imm:$src3)))]>, TB, OpSize; def SHRD16rri8 : Ii8<0xAC, MRMDestReg, - (ops R16:$dst, R16:$src1, R16:$src2, i8imm:$src3), + (ops GR16:$dst, GR16:$src1, GR16:$src2, i8imm:$src3), "shrd{w} {$src3, $src2, $dst|$dst, $src2, $src3}", - [(set R16:$dst, (X86shrd R16:$src1, R16:$src2, + [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, (i8 imm:$src3)))]>, TB, OpSize; } let isTwoAddress = 0 in { - def SHLD32mrCL : I<0xA5, MRMDestMem, (ops i32mem:$dst, R32:$src2), + def SHLD32mrCL : I<0xA5, MRMDestMem, (ops i32mem:$dst, GR32:$src2), "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}", - [(store (X86shld (loadi32 addr:$dst), R32:$src2, CL), + [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL), addr:$dst)]>, Imp<[CL],[]>, TB; - def SHRD32mrCL : I<0xAD, MRMDestMem, (ops i32mem:$dst, R32:$src2), + def SHRD32mrCL : I<0xAD, MRMDestMem, (ops i32mem:$dst, GR32:$src2), "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}", - [(store (X86shrd (loadi32 addr:$dst), R32:$src2, CL), + [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL), addr:$dst)]>, Imp<[CL],[]>, TB; def SHLD32mri8 : Ii8<0xA4, MRMDestMem, - (ops i32mem:$dst, R32:$src2, i8imm:$src3), + (ops i32mem:$dst, GR32:$src2, i8imm:$src3), "shld{l} {$src3, $src2, $dst|$dst, $src2, $src3}", - [(store (X86shld (loadi32 addr:$dst), R32:$src2, + [(store (X86shld (loadi32 addr:$dst), GR32:$src2, (i8 imm:$src3)), addr:$dst)]>, TB; def SHRD32mri8 : Ii8<0xAC, MRMDestMem, - (ops i32mem:$dst, R32:$src2, i8imm:$src3), + (ops i32mem:$dst, GR32:$src2, i8imm:$src3), "shrd{l} {$src3, $src2, $dst|$dst, $src2, $src3}", - [(store (X86shrd (loadi32 addr:$dst), R32:$src2, + [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, (i8 imm:$src3)), addr:$dst)]>, TB; - def SHLD16mrCL : I<0xA5, MRMDestMem, (ops i16mem:$dst, R16:$src2), + def SHLD16mrCL : I<0xA5, MRMDestMem, (ops i16mem:$dst, GR16:$src2), "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}", - [(store (X86shld (loadi16 addr:$dst), R16:$src2, CL), + [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL), addr:$dst)]>, Imp<[CL],[]>, TB, OpSize; - def SHRD16mrCL : I<0xAD, MRMDestMem, (ops i16mem:$dst, R16:$src2), + def SHRD16mrCL : I<0xAD, MRMDestMem, (ops i16mem:$dst, GR16:$src2), "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}", - [(store (X86shrd (loadi16 addr:$dst), R16:$src2, CL), + [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL), addr:$dst)]>, Imp<[CL],[]>, TB, OpSize; def SHLD16mri8 : Ii8<0xA4, MRMDestMem, - (ops i16mem:$dst, R16:$src2, i8imm:$src3), + (ops i16mem:$dst, GR16:$src2, i8imm:$src3), "shld{w} {$src3, $src2, $dst|$dst, $src2, $src3}", - [(store (X86shld (loadi16 addr:$dst), R16:$src2, + [(store (X86shld (loadi16 addr:$dst), GR16:$src2, (i8 imm:$src3)), addr:$dst)]>, TB, OpSize; def SHRD16mri8 : Ii8<0xAC, MRMDestMem, - (ops i16mem:$dst, R16:$src2, i8imm:$src3), + (ops i16mem:$dst, GR16:$src2, i8imm:$src3), "shrd{w} {$src3, $src2, $dst|$dst, $src2, $src3}", - [(store (X86shrd (loadi16 addr:$dst), R16:$src2, + [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, (i8 imm:$src3)), addr:$dst)]>, TB, OpSize; } @@ -1710,60 +1710,60 @@ // Arithmetic. let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y -def ADD8rr : I<0x00, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2), +def ADD8rr : I<0x00, MRMDestReg, (ops GR8 :$dst, GR8 :$src1, GR8 :$src2), "add{b} {$src2, $dst|$dst, $src2}", - [(set R8:$dst, (add R8:$src1, R8:$src2))]>; + [(set GR8:$dst, (add GR8:$src1, GR8:$src2))]>; let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. -def ADD16rr : I<0x01, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), +def ADD16rr : I<0x01, MRMDestReg, (ops GR16:$dst, GR16:$src1, GR16:$src2), "add{w} {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (add R16:$src1, R16:$src2))]>, OpSize; -def ADD32rr : I<0x01, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), + [(set GR16:$dst, (add GR16:$src1, GR16:$src2))]>, OpSize; +def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (add R32:$src1, R32:$src2))]>; + [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; } // end isConvertibleToThreeAddress } // end isCommutable -def ADD8rm : I<0x02, MRMSrcMem, (ops R8 :$dst, R8 :$src1, i8mem :$src2), +def ADD8rm : I<0x02, MRMSrcMem, (ops GR8 :$dst, GR8 :$src1, i8mem :$src2), "add{b} {$src2, $dst|$dst, $src2}", - [(set R8:$dst, (add R8:$src1, (load addr:$src2)))]>; -def ADD16rm : I<0x03, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2), + [(set GR8:$dst, (add GR8:$src1, (load addr:$src2)))]>; +def ADD16rm : I<0x03, MRMSrcMem, (ops GR16:$dst, GR16:$src1, i16mem:$src2), "add{w} {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (add R16:$src1, (load addr:$src2)))]>, OpSize; -def ADD32rm : I<0x03, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), + [(set GR16:$dst, (add GR16:$src1, (load addr:$src2)))]>, OpSize; +def ADD32rm : I<0x03, MRMSrcMem, (ops GR32:$dst, GR32:$src1, i32mem:$src2), "add{l} {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (add R32:$src1, (load addr:$src2)))]>; + [(set GR32:$dst, (add GR32:$src1, (load addr:$src2)))]>; -def ADD8ri : Ii8<0x80, MRM0r, (ops R8:$dst, R8:$src1, i8imm:$src2), +def ADD8ri : Ii8<0x80, MRM0r, (ops GR8:$dst, GR8:$src1, i8imm:$src2), "add{b} {$src2, $dst|$dst, $src2}", - [(set R8:$dst, (add R8:$src1, imm:$src2))]>; + [(set GR8:$dst, (add GR8:$src1, imm:$src2))]>; let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. -def ADD16ri : Ii16<0x81, MRM0r, (ops R16:$dst, R16:$src1, i16imm:$src2), +def ADD16ri : Ii16<0x81, MRM0r, (ops GR16:$dst, GR16:$src1, i16imm:$src2), "add{w} {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (add R16:$src1, imm:$src2))]>, OpSize; -def ADD32ri : Ii32<0x81, MRM0r, (ops R32:$dst, R32:$src1, i32imm:$src2), + [(set GR16:$dst, (add GR16:$src1, imm:$src2))]>, OpSize; +def ADD32ri : Ii32<0x81, MRM0r, (ops GR32:$dst, GR32:$src1, i32imm:$src2), "add{l} {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (add R32:$src1, imm:$src2))]>; + [(set GR32:$dst, (add GR32:$src1, imm:$src2))]>; } -def ADD16ri8 : Ii8<0x83, MRM0r, (ops R16:$dst, R16:$src1, i16i8imm:$src2), +def ADD16ri8 : Ii8<0x83, MRM0r, (ops GR16:$dst, GR16:$src1, i16i8imm:$src2), "add{w} {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (add R16:$src1, i16immSExt8:$src2))]>, + [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2))]>, OpSize; -def ADD32ri8 : Ii8<0x83, MRM0r, (ops R32:$dst, R32:$src1, i32i8imm:$src2), +def ADD32ri8 : Ii8<0x83, MRM0r, (ops GR32:$dst, GR32:$src1, i32i8imm:$src2), "add{l} {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (add R32:$src1, i32immSExt8:$src2))]>; + [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2))]>; let isTwoAddress = 0 in { - def ADD8mr : I<0x00, MRMDestMem, (ops i8mem :$dst, R8 :$src2), + def ADD8mr : I<0x00, MRMDestMem, (ops i8mem :$dst, GR8 :$src2), "add{b} {$src2, $dst|$dst, $src2}", - [(store (add (load addr:$dst), R8:$src2), addr:$dst)]>; - def ADD16mr : I<0x01, MRMDestMem, (ops i16mem:$dst, R16:$src2), + [(store (add (load addr:$dst), GR8:$src2), addr:$dst)]>; + def ADD16mr : I<0x01, MRMDestMem, (ops i16mem:$dst, GR16:$src2), "add{w} {$src2, $dst|$dst, $src2}", - [(store (add (load addr:$dst), R16:$src2), addr:$dst)]>, + [(store (add (load addr:$dst), GR16:$src2), addr:$dst)]>, OpSize; - def ADD32mr : I<0x01, MRMDestMem, (ops i32mem:$dst, R32:$src2), + def ADD32mr : I<0x01, MRMDestMem, (ops i32mem:$dst, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", - [(store (add (load addr:$dst), R32:$src2), addr:$dst)]>; + [(store (add (load addr:$dst), GR32:$src2), addr:$dst)]>; def ADD8mi : Ii8<0x80, MRM0m, (ops i8mem :$dst, i8imm :$src2), "add{b} {$src2, $dst|$dst, $src2}", [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst)]>; @@ -1784,24 +1784,24 @@ } let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y -def ADC32rr : I<0x11, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), +def ADC32rr : I<0x11, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "adc{l} {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (adde R32:$src1, R32:$src2))]>; + [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>; } -def ADC32rm : I<0x13, MRMSrcMem , (ops R32:$dst, R32:$src1, i32mem:$src2), +def ADC32rm : I<0x13, MRMSrcMem , (ops GR32:$dst, GR32:$src1, i32mem:$src2), "adc{l} {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (adde R32:$src1, (load addr:$src2)))]>; -def ADC32ri : Ii32<0x81, MRM2r, (ops R32:$dst, R32:$src1, i32imm:$src2), + [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>; +def ADC32ri : Ii32<0x81, MRM2r, (ops GR32:$dst, GR32:$src1, i32imm:$src2), "adc{l} {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (adde R32:$src1, imm:$src2))]>; -def ADC32ri8 : Ii8<0x83, MRM2r, (ops R32:$dst, R32:$src1, i32i8imm:$src2), + [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>; +def ADC32ri8 : Ii8<0x83, MRM2r, (ops GR32:$dst, GR32:$src1, i32i8imm:$src2), "adc{l} {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (adde R32:$src1, i32immSExt8:$src2))]>; + [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>; let isTwoAddress = 0 in { - def ADC32mr : I<0x11, MRMDestMem, (ops i32mem:$dst, R32:$src2), + def ADC32mr : I<0x11, MRMDestMem, (ops i32mem:$dst, GR32:$src2), "adc{l} {$src2, $dst|$dst, $src2}", - [(store (adde (load addr:$dst), R32:$src2), addr:$dst)]>; + [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>; def ADC32mi : Ii32<0x81, MRM2m, (ops i32mem:$dst, i32imm:$src2), "adc{l} {$src2, $dst|$dst, $src2}", [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>; @@ -1810,52 +1810,52 @@ [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>; } -def SUB8rr : I<0x28, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2), +def SUB8rr : I<0x28, MRMDestReg, (ops GR8 :$dst, GR8 :$src1, GR8 :$src2), "sub{b} {$src2, $dst|$dst, $src2}", - [(set R8:$dst, (sub R8:$src1, R8:$src2))]>; -def SUB16rr : I<0x29, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), + [(set GR8:$dst, (sub GR8:$src1, GR8:$src2))]>; +def SUB16rr : I<0x29, MRMDestReg, (ops GR16:$dst, GR16:$src1, GR16:$src2), "sub{w} {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (sub R16:$src1, R16:$src2))]>, OpSize; -def SUB32rr : I<0x29, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), + [(set GR16:$dst, (sub GR16:$src1, GR16:$src2))]>, OpSize; +def SUB32rr : I<0x29, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "sub{l} {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (sub R32:$src1, R32:$src2))]>; -def SUB8rm : I<0x2A, MRMSrcMem, (ops R8 :$dst, R8 :$src1, i8mem :$src2), + [(set GR32:$dst, (sub GR32:$src1, GR32:$src2))]>; +def SUB8rm : I<0x2A, MRMSrcMem, (ops GR8 :$dst, GR8 :$src1, i8mem :$src2), "sub{b} {$src2, $dst|$dst, $src2}", - [(set R8:$dst, (sub R8:$src1, (load addr:$src2)))]>; -def SUB16rm : I<0x2B, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2), + [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2)))]>; +def SUB16rm : I<0x2B, MRMSrcMem, (ops GR16:$dst, GR16:$src1, i16mem:$src2), "sub{w} {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (sub R16:$src1, (load addr:$src2)))]>, OpSize; -def SUB32rm : I<0x2B, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), + [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2)))]>, OpSize; +def SUB32rm : I<0x2B, MRMSrcMem, (ops GR32:$dst, GR32:$src1, i32mem:$src2), "sub{l} {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (sub R32:$src1, (load addr:$src2)))]>; + [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2)))]>; -def SUB8ri : Ii8 <0x80, MRM5r, (ops R8:$dst, R8:$src1, i8imm:$src2), +def SUB8ri : Ii8 <0x80, MRM5r, (ops GR8:$dst, GR8:$src1, i8imm:$src2), "sub{b} {$src2, $dst|$dst, $src2}", - [(set R8:$dst, (sub R8:$src1, imm:$src2))]>; -def SUB16ri : Ii16<0x81, MRM5r, (ops R16:$dst, R16:$src1, i16imm:$src2), + [(set GR8:$dst, (sub GR8:$src1, imm:$src2))]>; +def SUB16ri : Ii16<0x81, MRM5r, (ops GR16:$dst, GR16:$src1, i16imm:$src2), "sub{w} {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (sub R16:$src1, imm:$src2))]>, OpSize; -def SUB32ri : Ii32<0x81, MRM5r, (ops R32:$dst, R32:$src1, i32imm:$src2), + [(set GR16:$dst, (sub GR16:$src1, imm:$src2))]>, OpSize; +def SUB32ri : Ii32<0x81, MRM5r, (ops GR32:$dst, GR32:$src1, i32imm:$src2), "sub{l} {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (sub R32:$src1, imm:$src2))]>; -def SUB16ri8 : Ii8<0x83, MRM5r, (ops R16:$dst, R16:$src1, i16i8imm:$src2), + [(set GR32:$dst, (sub GR32:$src1, imm:$src2))]>; +def SUB16ri8 : Ii8<0x83, MRM5r, (ops GR16:$dst, GR16:$src1, i16i8imm:$src2), "sub{w} {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (sub R16:$src1, i16immSExt8:$src2))]>, + [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2))]>, OpSize; -def SUB32ri8 : Ii8<0x83, MRM5r, (ops R32:$dst, R32:$src1, i32i8imm:$src2), +def SUB32ri8 : Ii8<0x83, MRM5r, (ops GR32:$dst, GR32:$src1, i32i8imm:$src2), "sub{l} {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (sub R32:$src1, i32immSExt8:$src2))]>; + [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2))]>; let isTwoAddress = 0 in { - def SUB8mr : I<0x28, MRMDestMem, (ops i8mem :$dst, R8 :$src2), + def SUB8mr : I<0x28, MRMDestMem, (ops i8mem :$dst, GR8 :$src2), "sub{b} {$src2, $dst|$dst, $src2}", - [(store (sub (load addr:$dst), R8:$src2), addr:$dst)]>; - def SUB16mr : I<0x29, MRMDestMem, (ops i16mem:$dst, R16:$src2), + [(store (sub (load addr:$dst), GR8:$src2), addr:$dst)]>; + def SUB16mr : I<0x29, MRMDestMem, (ops i16mem:$dst, GR16:$src2), "sub{w} {$src2, $dst|$dst, $src2}", - [(store (sub (load addr:$dst), R16:$src2), addr:$dst)]>, + [(store (sub (load addr:$dst), GR16:$src2), addr:$dst)]>, OpSize; - def SUB32mr : I<0x29, MRMDestMem, (ops i32mem:$dst, R32:$src2), + def SUB32mr : I<0x29, MRMDestMem, (ops i32mem:$dst, GR32:$src2), "sub{l} {$src2, $dst|$dst, $src2}", - [(store (sub (load addr:$dst), R32:$src2), addr:$dst)]>; + [(store (sub (load addr:$dst), GR32:$src2), addr:$dst)]>; def SUB8mi : Ii8<0x80, MRM5m, (ops i8mem :$dst, i8imm:$src2), "sub{b} {$src2, $dst|$dst, $src2}", [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst)]>; @@ -1875,14 +1875,14 @@ [(store (sub (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>; } -def SBB32rr : I<0x19, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), +def SBB32rr : I<0x19, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "sbb{l} {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (sube R32:$src1, R32:$src2))]>; + [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>; let isTwoAddress = 0 in { - def SBB32mr : I<0x19, MRMDestMem, (ops i32mem:$dst, R32:$src2), + def SBB32mr : I<0x19, MRMDestMem, (ops i32mem:$dst, GR32:$src2), "sbb{l} {$src2, $dst|$dst, $src2}", - [(store (sube (load addr:$dst), R32:$src2), addr:$dst)]>; + [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>; def SBB8mi : Ii32<0x80, MRM3m, (ops i8mem:$dst, i8imm:$src2), "sbb{b} {$src2, $dst|$dst, $src2}", [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>; @@ -1893,119 +1893,119 @@ "sbb{l} {$src2, $dst|$dst, $src2}", [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>; } -def SBB32rm : I<0x1B, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), +def SBB32rm : I<0x1B, MRMSrcMem, (ops GR32:$dst, GR32:$src1, i32mem:$src2), "sbb{l} {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (sube R32:$src1, (load addr:$src2)))]>; -def SBB32ri : Ii32<0x81, MRM3r, (ops R32:$dst, R32:$src1, i32imm:$src2), + [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>; +def SBB32ri : Ii32<0x81, MRM3r, (ops GR32:$dst, GR32:$src1, i32imm:$src2), "sbb{l} {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (sube R32:$src1, imm:$src2))]>; -def SBB32ri8 : Ii8<0x83, MRM3r, (ops R32:$dst, R32:$src1, i32i8imm:$src2), + [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>; +def SBB32ri8 : Ii8<0x83, MRM3r, (ops GR32:$dst, GR32:$src1, i32i8imm:$src2), "sbb{l} {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (sube R32:$src1, i32immSExt8:$src2))]>; + [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>; let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y -def IMUL16rr : I<0xAF, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2), +def IMUL16rr : I<0xAF, MRMSrcReg, (ops GR16:$dst, GR16:$src1, GR16:$src2), "imul{w} {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (mul R16:$src1, R16:$src2))]>, TB, OpSize; -def IMUL32rr : I<0xAF, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2), + [(set GR16:$dst, (mul GR16:$src1, GR16:$src2))]>, TB, OpSize; +def IMUL32rr : I<0xAF, MRMSrcReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "imul{l} {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (mul R32:$src1, R32:$src2))]>, TB; + [(set GR32:$dst, (mul GR32:$src1, GR32:$src2))]>, TB; } -def IMUL16rm : I<0xAF, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2), +def IMUL16rm : I<0xAF, MRMSrcMem, (ops GR16:$dst, GR16:$src1, i16mem:$src2), "imul{w} {$src2, $dst|$dst, $src2}", - [(set R16:$dst, (mul R16:$src1, (load addr:$src2)))]>, + [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2)))]>, TB, OpSize; -def IMUL32rm : I<0xAF, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), +def IMUL32rm : I<0xAF, MRMSrcMem, (ops GR32:$dst, GR32:$src1, i32mem:$src2), "imul{l} {$src2, $dst|$dst, $src2}", - [(set R32:$dst, (mul R32:$src1, (load addr:$src2)))]>, TB; + [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2)))]>, TB; } // end Two Address instructions // Suprisingly enough, these are not two address instructions! -def IMUL16rri : Ii16<0x69, MRMSrcReg, // R16 = R16*I16 - (ops R16:$dst, R16:$src1, i16imm:$src2), +def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16 + (ops GR16:$dst, GR16:$src1, i16imm:$src2), "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}", - [(set R16:$dst, (mul R16:$src1, imm:$src2))]>, OpSize; -def IMUL32rri : Ii32<0x69, MRMSrcReg, // R32 = R32*I32 - (ops R32:$dst, R32:$src1, i32imm:$src2), + [(set GR16:$dst, (mul GR16:$src1, imm:$src2))]>, OpSize; +def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32 + (ops GR32:$dst, GR32:$src1, i32imm:$src2), "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}", - [(set R32:$dst, (mul R32:$src1, imm:$src2))]>; -def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // R16 = R16*I8 - (ops R16:$dst, R16:$src1, i16i8imm:$src2), + [(set GR32:$dst, (mul GR32:$src1, imm:$src2))]>; +def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8 + (ops GR16:$dst, GR16:$src1, i16i8imm:$src2), "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}", - [(set R16:$dst, (mul R16:$src1, i16immSExt8:$src2))]>, + [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2))]>, OpSize; -def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // R32 = R32*I8 - (ops R32:$dst, R32:$src1, i32i8imm:$src2), +def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8 + (ops GR32:$dst, GR32:$src1, i32i8imm:$src2), "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}", - [(set R32:$dst, (mul R32:$src1, i32immSExt8:$src2))]>; + [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2))]>; -def IMUL16rmi : Ii16<0x69, MRMSrcMem, // R16 = [mem16]*I16 - (ops R16:$dst, i16mem:$src1, i16imm:$src2), +def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16 + (ops GR16:$dst, i16mem:$src1, i16imm:$src2), "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}", - [(set R16:$dst, (mul (load addr:$src1), imm:$src2))]>, + [(set GR16:$dst, (mul (load addr:$src1), imm:$src2))]>, OpSize; -def IMUL32rmi : Ii32<0x69, MRMSrcMem, // R32 = [mem32]*I32 - (ops R32:$dst, i32mem:$src1, i32imm:$src2), +def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32 + (ops GR32:$dst, i32mem:$src1, i32imm:$src2), "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}", - [(set R32:$dst, (mul (load addr:$src1), imm:$src2))]>; -def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // R16 = [mem16]*I8 - (ops R16:$dst, i16mem:$src1, i16i8imm :$src2), + [(set GR32:$dst, (mul (load addr:$src1), imm:$src2))]>; +def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8 + (ops GR16:$dst, i16mem:$src1, i16i8imm :$src2), "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}", - [(set R16:$dst, (mul (load addr:$src1), i16immSExt8:$src2))]>, + [(set GR16:$dst, (mul (load addr:$src1), i16immSExt8:$src2))]>, OpSize; -def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // R32 = [mem32]*I8 - (ops R32:$dst, i32mem:$src1, i32i8imm: $src2), +def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8 + (ops GR32:$dst, i32mem:$src1, i32i8imm: $src2), "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}", - [(set R32:$dst, (mul (load addr:$src1), i32immSExt8:$src2))]>; + [(set GR32:$dst, (mul (load addr:$src1), i32immSExt8:$src2))]>; //===----------------------------------------------------------------------===// // Test instructions are just like AND, except they don't generate a result. // let isCommutable = 1 in { // TEST X, Y --> TEST Y, X -def TEST8rr : I<0x84, MRMDestReg, (ops R8:$src1, R8:$src2), +def TEST8rr : I<0x84, MRMDestReg, (ops GR8:$src1, GR8:$src2), "test{b} {$src2, $src1|$src1, $src2}", - [(X86test R8:$src1, R8:$src2)]>; -def TEST16rr : I<0x85, MRMDestReg, (ops R16:$src1, R16:$src2), + [(X86test GR8:$src1, GR8:$src2)]>; +def TEST16rr : I<0x85, MRMDestReg, (ops GR16:$src1, GR16:$src2), "test{w} {$src2, $src1|$src1, $src2}", - [(X86test R16:$src1, R16:$src2)]>, OpSize; -def TEST32rr : I<0x85, MRMDestReg, (ops R32:$src1, R32:$src2), + [(X86test GR16:$src1, GR16:$src2)]>, OpSize; +def TEST32rr : I<0x85, MRMDestReg, (ops GR32:$src1, GR32:$src2), "test{l} {$src2, $src1|$src1, $src2}", - [(X86test R32:$src1, R32:$src2)]>; + [(X86test GR32:$src1, GR32:$src2)]>; } -def TEST8mr : I<0x84, MRMDestMem, (ops i8mem :$src1, R8 :$src2), +def TEST8mr : I<0x84, MRMDestMem, (ops i8mem :$src1, GR8 :$src2), "test{b} {$src2, $src1|$src1, $src2}", - [(X86test (loadi8 addr:$src1), R8:$src2)]>; -def TEST16mr : I<0x85, MRMDestMem, (ops i16mem:$src1, R16:$src2), + [(X86test (loadi8 addr:$src1), GR8:$src2)]>; +def TEST16mr : I<0x85, MRMDestMem, (ops i16mem:$src1, GR16:$src2), "test{w} {$src2, $src1|$src1, $src2}", - [(X86test (loadi16 addr:$src1), R16:$src2)]>, + [(X86test (loadi16 addr:$src1), GR16:$src2)]>, OpSize; -def TEST32mr : I<0x85, MRMDestMem, (ops i32mem:$src1, R32:$src2), +def TEST32mr : I<0x85, MRMDestMem, (ops i32mem:$src1, GR32:$src2), "test{l} {$src2, $src1|$src1, $src2}", - [(X86test (loadi32 addr:$src1), R32:$src2)]>; -def TEST8rm : I<0x84, MRMSrcMem, (ops R8 :$src1, i8mem :$src2), + [(X86test (loadi32 addr:$src1), GR32:$src2)]>; +def TEST8rm : I<0x84, MRMSrcMem, (ops GR8 :$src1, i8mem :$src2), "test{b} {$src2, $src1|$src1, $src2}", - [(X86test R8:$src1, (loadi8 addr:$src2))]>; -def TEST16rm : I<0x85, MRMSrcMem, (ops R16:$src1, i16mem:$src2), + [(X86test GR8:$src1, (loadi8 addr:$src2))]>; +def TEST16rm : I<0x85, MRMSrcMem, (ops GR16:$src1, i16mem:$src2), "test{w} {$src2, $src1|$src1, $src2}", - [(X86test R16:$src1, (loadi16 addr:$src2))]>, + [(X86test GR16:$src1, (loadi16 addr:$src2))]>, OpSize; -def TEST32rm : I<0x85, MRMSrcMem, (ops R32:$src1, i32mem:$src2), +def TEST32rm : I<0x85, MRMSrcMem, (ops GR32:$src1, i32mem:$src2), "test{l} {$src2, $src1|$src1, $src2}", - [(X86test R32:$src1, (loadi32 addr:$src2))]>; + [(X86test GR32:$src1, (loadi32 addr:$src2))]>; -def TEST8ri : Ii8 <0xF6, MRM0r, // flags = R8 & imm8 - (ops R8:$src1, i8imm:$src2), +def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8 + (ops GR8:$src1, i8imm:$src2), "test{b} {$src2, $src1|$src1, $src2}", - [(X86test R8:$src1, imm:$src2)]>; -def TEST16ri : Ii16<0xF7, MRM0r, // flags = R16 & imm16 - (ops R16:$src1, i16imm:$src2), + [(X86test GR8:$src1, imm:$src2)]>; +def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16 + (ops GR16:$src1, i16imm:$src2), "test{w} {$src2, $src1|$src1, $src2}", - [(X86test R16:$src1, imm:$src2)]>, OpSize; -def TEST32ri : Ii32<0xF7, MRM0r, // flags = R32 & imm32 - (ops R32:$src1, i32imm:$src2), + [(X86test GR16:$src1, imm:$src2)]>, OpSize; +def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32 + (ops GR32:$src1, i32imm:$src2), "test{l} {$src2, $src1|$src1, $src2}", - [(X86test R32:$src1, imm:$src2)]>; + [(X86test GR32:$src1, imm:$src2)]>; def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8 (ops i8mem:$src1, i8imm:$src2), "test{b} {$src2, $src1|$src1, $src2}", @@ -2026,60 +2026,60 @@ def LAHF : I<0x9F, RawFrm, (ops), "lahf", []>, Imp<[],[AH]>; // AH = flags def SETEr : I<0x94, MRM0r, - (ops R8 :$dst), + (ops GR8 :$dst), "sete $dst", - [(set R8:$dst, (X86setcc X86_COND_E))]>, - TB; // R8 = == + [(set GR8:$dst, (X86setcc X86_COND_E))]>, + TB; // GR8 = == def SETEm : I<0x94, MRM0m, (ops i8mem:$dst), "sete $dst", [(store (X86setcc X86_COND_E), addr:$dst)]>, TB; // [mem8] = == def SETNEr : I<0x95, MRM0r, - (ops R8 :$dst), + (ops GR8 :$dst), "setne $dst", - [(set R8:$dst, (X86setcc X86_COND_NE))]>, - TB; // R8 = != + [(set GR8:$dst, (X86setcc X86_COND_NE))]>, + TB; // GR8 = != def SETNEm : I<0x95, MRM0m, (ops i8mem:$dst), "setne $dst", [(store (X86setcc X86_COND_NE), addr:$dst)]>, TB; // [mem8] = != def SETLr : I<0x9C, MRM0r, - (ops R8 :$dst), + (ops GR8 :$dst), "setl $dst", - [(set R8:$dst, (X86setcc X86_COND_L))]>, - TB; // R8 = < signed + [(set GR8:$dst, (X86setcc X86_COND_L))]>, + TB; // GR8 = < signed def SETLm : I<0x9C, MRM0m, (ops i8mem:$dst), "setl $dst", [(store (X86setcc X86_COND_L), addr:$dst)]>, TB; // [mem8] = < signed def SETGEr : I<0x9D, MRM0r, - (ops R8 :$dst), + (ops GR8 :$dst), "setge $dst", - [(set R8:$dst, (X86setcc X86_COND_GE))]>, - TB; // R8 = >= signed + [(set GR8:$dst, (X86setcc X86_COND_GE))]>, + TB; // GR8 = >= signed def SETGEm : I<0x9D, MRM0m, (ops i8mem:$dst), "setge $dst", [(store (X86setcc X86_COND_GE), addr:$dst)]>, TB; // [mem8] = >= signed def SETLEr : I<0x9E, MRM0r, - (ops R8 :$dst), + (ops GR8 :$dst), "setle $dst", - [(set R8:$dst, (X86setcc X86_COND_LE))]>, - TB; // R8 = <= signed + [(set GR8:$dst, (X86setcc X86_COND_LE))]>, + TB; // GR8 = <= signed def SETLEm : I<0x9E, MRM0m, (ops i8mem:$dst), "setle $dst", [(store (X86setcc X86_COND_LE), addr:$dst)]>, TB; // [mem8] = <= signed def SETGr : I<0x9F, MRM0r, - (ops R8 :$dst), + (ops GR8 :$dst), "setg $dst", - [(set R8:$dst, (X86setcc X86_COND_G))]>, - TB; // R8 = > signed + [(set GR8:$dst, (X86setcc X86_COND_G))]>, + TB; // GR8 = > signed def SETGm : I<0x9F, MRM0m, (ops i8mem:$dst), "setg $dst", @@ -2087,40 +2087,40 @@ TB; // [mem8] = > signed def SETBr : I<0x92, MRM0r, - (ops R8 :$dst), + (ops GR8 :$dst), "setb $dst", - [(set R8:$dst, (X86setcc X86_COND_B))]>, - TB; // R8 = < unsign + [(set GR8:$dst, (X86setcc X86_COND_B))]>, + TB; // GR8 = < unsign def SETBm : I<0x92, MRM0m, (ops i8mem:$dst), "setb $dst", [(store (X86setcc X86_COND_B), addr:$dst)]>, TB; // [mem8] = < unsign def SETAEr : I<0x93, MRM0r, - (ops R8 :$dst), + (ops GR8 :$dst), "setae $dst", - [(set R8:$dst, (X86setcc X86_COND_AE))]>, - TB; // R8 = >= unsign + [(set GR8:$dst, (X86setcc X86_COND_AE))]>, + TB; // GR8 = >= unsign def SETAEm : I<0x93, MRM0m, (ops i8mem:$dst), "setae $dst", [(store (X86setcc X86_COND_AE), addr:$dst)]>, TB; // [mem8] = >= unsign def SETBEr : I<0x96, MRM0r, - (ops R8 :$dst), + (ops GR8 :$dst), "setbe $dst", - [(set R8:$dst, (X86setcc X86_COND_BE))]>, - TB; // R8 = <= unsign + [(set GR8:$dst, (X86setcc X86_COND_BE))]>, + TB; // GR8 = <= unsign def SETBEm : I<0x96, MRM0m, (ops i8mem:$dst), "setbe $dst", [(store (X86setcc X86_COND_BE), addr:$dst)]>, TB; // [mem8] = <= unsign def SETAr : I<0x97, MRM0r, - (ops R8 :$dst), + (ops GR8 :$dst), "seta $dst", - [(set R8:$dst, (X86setcc X86_COND_A))]>, - TB; // R8 = > signed + [(set GR8:$dst, (X86setcc X86_COND_A))]>, + TB; // GR8 = > signed def SETAm : I<0x97, MRM0m, (ops i8mem:$dst), "seta $dst", @@ -2128,40 +2128,40 @@ TB; // [mem8] = > signed def SETSr : I<0x98, MRM0r, - (ops R8 :$dst), + (ops GR8 :$dst), "sets $dst", - [(set R8:$dst, (X86setcc X86_COND_S))]>, - TB; // R8 = + [(set GR8:$dst, (X86setcc X86_COND_S))]>, + TB; // GR8 = def SETSm : I<0x98, MRM0m, (ops i8mem:$dst), "sets $dst", [(store (X86setcc X86_COND_S), addr:$dst)]>, TB; // [mem8] = def SETNSr : I<0x99, MRM0r, - (ops R8 :$dst), + (ops GR8 :$dst), "setns $dst", - [(set R8:$dst, (X86setcc X86_COND_NS))]>, - TB; // R8 = ! + [(set GR8:$dst, (X86setcc X86_COND_NS))]>, + TB; // GR8 = ! def SETNSm : I<0x99, MRM0m, (ops i8mem:$dst), "setns $dst", [(store (X86setcc X86_COND_NS), addr:$dst)]>, TB; // [mem8] = ! def SETPr : I<0x9A, MRM0r, - (ops R8 :$dst), + (ops GR8 :$dst), "setp $dst", - [(set R8:$dst, (X86setcc X86_COND_P))]>, - TB; // R8 = parity + [(set GR8:$dst, (X86setcc X86_COND_P))]>, + TB; // GR8 = parity def SETPm : I<0x9A, MRM0m, (ops i8mem:$dst), "setp $dst", [(store (X86setcc X86_COND_P), addr:$dst)]>, TB; // [mem8] = parity def SETNPr : I<0x9B, MRM0r, - (ops R8 :$dst), + (ops GR8 :$dst), "setnp $dst", - [(set R8:$dst, (X86setcc X86_COND_NP))]>, - TB; // R8 = not parity + [(set GR8:$dst, (X86setcc X86_COND_NP))]>, + TB; // GR8 = not parity def SETNPm : I<0x9B, MRM0m, (ops i8mem:$dst), "setnp $dst", @@ -2170,53 +2170,53 @@ // Integer comparisons def CMP8rr : I<0x38, MRMDestReg, - (ops R8 :$src1, R8 :$src2), + (ops GR8 :$src1, GR8 :$src2), "cmp{b} {$src2, $src1|$src1, $src2}", - [(X86cmp R8:$src1, R8:$src2)]>; + [(X86cmp GR8:$src1, GR8:$src2)]>; def CMP16rr : I<0x39, MRMDestReg, - (ops R16:$src1, R16:$src2), + (ops GR16:$src1, GR16:$src2), "cmp{w} {$src2, $src1|$src1, $src2}", - [(X86cmp R16:$src1, R16:$src2)]>, OpSize; + [(X86cmp GR16:$src1, GR16:$src2)]>, OpSize; def CMP32rr : I<0x39, MRMDestReg, - (ops R32:$src1, R32:$src2), + (ops GR32:$src1, GR32:$src2), "cmp{l} {$src2, $src1|$src1, $src2}", - [(X86cmp R32:$src1, R32:$src2)]>; + [(X86cmp GR32:$src1, GR32:$src2)]>; def CMP8mr : I<0x38, MRMDestMem, - (ops i8mem :$src1, R8 :$src2), + (ops i8mem :$src1, GR8 :$src2), "cmp{b} {$src2, $src1|$src1, $src2}", - [(X86cmp (loadi8 addr:$src1), R8:$src2)]>; + [(X86cmp (loadi8 addr:$src1), GR8:$src2)]>; def CMP16mr : I<0x39, MRMDestMem, - (ops i16mem:$src1, R16:$src2), + (ops i16mem:$src1, GR16:$src2), "cmp{w} {$src2, $src1|$src1, $src2}", - [(X86cmp (loadi16 addr:$src1), R16:$src2)]>, OpSize; + [(X86cmp (loadi16 addr:$src1), GR16:$src2)]>, OpSize; def CMP32mr : I<0x39, MRMDestMem, - (ops i32mem:$src1, R32:$src2), + (ops i32mem:$src1, GR32:$src2), "cmp{l} {$src2, $src1|$src1, $src2}", - [(X86cmp (loadi32 addr:$src1), R32:$src2)]>; + [(X86cmp (loadi32 addr:$src1), GR32:$src2)]>; def CMP8rm : I<0x3A, MRMSrcMem, - (ops R8 :$src1, i8mem :$src2), + (ops GR8 :$src1, i8mem :$src2), "cmp{b} {$src2, $src1|$src1, $src2}", - [(X86cmp R8:$src1, (loadi8 addr:$src2))]>; + [(X86cmp GR8:$src1, (loadi8 addr:$src2))]>; def CMP16rm : I<0x3B, MRMSrcMem, - (ops R16:$src1, i16mem:$src2), + (ops GR16:$src1, i16mem:$src2), "cmp{w} {$src2, $src1|$src1, $src2}", - [(X86cmp R16:$src1, (loadi16 addr:$src2))]>, OpSize; + [(X86cmp GR16:$src1, (loadi16 addr:$src2))]>, OpSize; def CMP32rm : I<0x3B, MRMSrcMem, - (ops R32:$src1, i32mem:$src2), + (ops GR32:$src1, i32mem:$src2), "cmp{l} {$src2, $src1|$src1, $src2}", - [(X86cmp R32:$src1, (loadi32 addr:$src2))]>; + [(X86cmp GR32:$src1, (loadi32 addr:$src2))]>; def CMP8ri : Ii8<0x80, MRM7r, - (ops R8:$src1, i8imm:$src2), + (ops GR8:$src1, i8imm:$src2), "cmp{b} {$src2, $src1|$src1, $src2}", - [(X86cmp R8:$src1, imm:$src2)]>; + [(X86cmp GR8:$src1, imm:$src2)]>; def CMP16ri : Ii16<0x81, MRM7r, - (ops R16:$src1, i16imm:$src2), + (ops GR16:$src1, i16imm:$src2), "cmp{w} {$src2, $src1|$src1, $src2}", - [(X86cmp R16:$src1, imm:$src2)]>, OpSize; + [(X86cmp GR16:$src1, imm:$src2)]>, OpSize; def CMP32ri : Ii32<0x81, MRM7r, - (ops R32:$src1, i32imm:$src2), + (ops GR32:$src1, i32imm:$src2), "cmp{l} {$src2, $src1|$src1, $src2}", - [(X86cmp R32:$src1, imm:$src2)]>; + [(X86cmp GR32:$src1, imm:$src2)]>; def CMP8mi : Ii8 <0x80, MRM7m, (ops i8mem :$src1, i8imm :$src2), "cmp{b} {$src2, $src1|$src1, $src2}", @@ -2230,9 +2230,9 @@ "cmp{l} {$src2, $src1|$src1, $src2}", [(X86cmp (loadi32 addr:$src1), imm:$src2)]>; def CMP16ri8 : Ii8<0x83, MRM7r, - (ops R16:$src1, i16i8imm:$src2), + (ops GR16:$src1, i16i8imm:$src2), "cmp{w} {$src2, $src1|$src1, $src2}", - [(X86cmp R16:$src1, i16immSExt8:$src2)]>, OpSize; + [(X86cmp GR16:$src1, i16immSExt8:$src2)]>, OpSize; def CMP16mi8 : Ii8<0x83, MRM7m, (ops i16mem:$src1, i16i8imm:$src2), "cmp{w} {$src2, $src1|$src1, $src2}", @@ -2242,48 +2242,48 @@ "cmp{l} {$src2, $src1|$src1, $src2}", [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2)]>; def CMP32ri8 : Ii8<0x83, MRM7r, - (ops R32:$src1, i32i8imm:$src2), + (ops GR32:$src1, i32i8imm:$src2), "cmp{l} {$src2, $src1|$src1, $src2}", - [(X86cmp R32:$src1, i32immSExt8:$src2)]>; + [(X86cmp GR32:$src1, i32immSExt8:$src2)]>; // Sign/Zero extenders -def MOVSX16rr8 : I<0xBE, MRMSrcReg, (ops R16:$dst, R8 :$src), +def MOVSX16rr8 : I<0xBE, MRMSrcReg, (ops GR16:$dst, GR8 :$src), "movs{bw|x} {$src, $dst|$dst, $src}", - [(set R16:$dst, (sext R8:$src))]>, TB, OpSize; -def MOVSX16rm8 : I<0xBE, MRMSrcMem, (ops R16:$dst, i8mem :$src), + [(set GR16:$dst, (sext GR8:$src))]>, TB, OpSize; +def MOVSX16rm8 : I<0xBE, MRMSrcMem, (ops GR16:$dst, i8mem :$src), "movs{bw|x} {$src, $dst|$dst, $src}", - [(set R16:$dst, (sextloadi16i8 addr:$src))]>, TB, OpSize; -def MOVSX32rr8 : I<0xBE, MRMSrcReg, (ops R32:$dst, R8 :$src), + [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB, OpSize; +def MOVSX32rr8 : I<0xBE, MRMSrcReg, (ops GR32:$dst, GR8 :$src), "movs{bl|x} {$src, $dst|$dst, $src}", - [(set R32:$dst, (sext R8:$src))]>, TB; -def MOVSX32rm8 : I<0xBE, MRMSrcMem, (ops R32:$dst, i8mem :$src), + [(set GR32:$dst, (sext GR8:$src))]>, TB; +def MOVSX32rm8 : I<0xBE, MRMSrcMem, (ops GR32:$dst, i8mem :$src), "movs{bl|x} {$src, $dst|$dst, $src}", - [(set R32:$dst, (sextloadi32i8 addr:$src))]>, TB; -def MOVSX32rr16: I<0xBF, MRMSrcReg, (ops R32:$dst, R16:$src), + [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB; +def MOVSX32rr16: I<0xBF, MRMSrcReg, (ops GR32:$dst, GR16:$src), "movs{wl|x} {$src, $dst|$dst, $src}", - [(set R32:$dst, (sext R16:$src))]>, TB; -def MOVSX32rm16: I<0xBF, MRMSrcMem, (ops R32:$dst, i16mem:$src), + [(set GR32:$dst, (sext GR16:$src))]>, TB; +def MOVSX32rm16: I<0xBF, MRMSrcMem, (ops GR32:$dst, i16mem:$src), "movs{wl|x} {$src, $dst|$dst, $src}", - [(set R32:$dst, (sextloadi32i16 addr:$src))]>, TB; + [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB; -def MOVZX16rr8 : I<0xB6, MRMSrcReg, (ops R16:$dst, R8 :$src), +def MOVZX16rr8 : I<0xB6, MRMSrcReg, (ops GR16:$dst, GR8 :$src), "movz{bw|x} {$src, $dst|$dst, $src}", - [(set R16:$dst, (zext R8:$src))]>, TB, OpSize; -def MOVZX16rm8 : I<0xB6, MRMSrcMem, (ops R16:$dst, i8mem :$src), + [(set GR16:$dst, (zext GR8:$src))]>, TB, OpSize; +def MOVZX16rm8 : I<0xB6, MRMSrcMem, (ops GR16:$dst, i8mem :$src), "movz{bw|x} {$src, $dst|$dst, $src}", - [(set R16:$dst, (zextloadi16i8 addr:$src))]>, TB, OpSize; -def MOVZX32rr8 : I<0xB6, MRMSrcReg, (ops R32:$dst, R8 :$src), + [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB, OpSize; +def MOVZX32rr8 : I<0xB6, MRMSrcReg, (ops GR32:$dst, GR8 :$src), "movz{bl|x} {$src, $dst|$dst, $src}", - [(set R32:$dst, (zext R8:$src))]>, TB; -def MOVZX32rm8 : I<0xB6, MRMSrcMem, (ops R32:$dst, i8mem :$src), + [(set GR32:$dst, (zext GR8:$src))]>, TB; +def MOVZX32rm8 : I<0xB6, MRMSrcMem, (ops GR32:$dst, i8mem :$src), "movz{bl|x} {$src, $dst|$dst, $src}", - [(set R32:$dst, (zextloadi32i8 addr:$src))]>, TB; -def MOVZX32rr16: I<0xB7, MRMSrcReg, (ops R32:$dst, R16:$src), + [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB; +def MOVZX32rr16: I<0xB7, MRMSrcReg, (ops GR32:$dst, GR16:$src), "movz{wl|x} {$src, $dst|$dst, $src}", - [(set R32:$dst, (zext R16:$src))]>, TB; -def MOVZX32rm16: I<0xB7, MRMSrcMem, (ops R32:$dst, i16mem:$src), + [(set GR32:$dst, (zext GR16:$src))]>, TB; +def MOVZX32rm16: I<0xB7, MRMSrcMem, (ops GR32:$dst, i16mem:$src), "movz{wl|x} {$src, $dst|$dst, $src}", - [(set R32:$dst, (zextloadi32i16 addr:$src))]>, TB; + [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB; //===----------------------------------------------------------------------===// // Miscellaneous Instructions @@ -2298,34 +2298,34 @@ // Alias instructions that map movr0 to xor. // FIXME: remove when we can teach regalloc that xor reg, reg is ok. -def MOV8r0 : I<0x30, MRMInitReg, (ops R8 :$dst), +def MOV8r0 : I<0x30, MRMInitReg, (ops GR8 :$dst), "xor{b} $dst, $dst", - [(set R8:$dst, 0)]>; -def MOV16r0 : I<0x31, MRMInitReg, (ops R16:$dst), + [(set GR8:$dst, 0)]>; +def MOV16r0 : I<0x31, MRMInitReg, (ops GR16:$dst), "xor{w} $dst, $dst", - [(set R16:$dst, 0)]>, OpSize; -def MOV32r0 : I<0x31, MRMInitReg, (ops R32:$dst), + [(set GR16:$dst, 0)]>, OpSize; +def MOV32r0 : I<0x31, MRMInitReg, (ops GR32:$dst), "xor{l} $dst, $dst", - [(set R32:$dst, 0)]>; + [(set GR32:$dst, 0)]>; -// Basic operations on R16 / R32 subclasses R16_ and R32_ which contains only -// those registers that have R8 sub-registers (i.e. AX - DX, EAX - EDX). -def MOV16to16_ : I<0x89, MRMDestReg, (ops R16_:$dst, R16:$src), +// Basic operations on GR16 / GR32 subclasses GR16_ and GR32_ which contains only +// those registers that have GR8 sub-registers (i.e. AX - DX, EAX - EDX). +def MOV16to16_ : I<0x89, MRMDestReg, (ops GR16_:$dst, GR16:$src), "mov{w} {$src, $dst|$dst, $src}", []>, OpSize; -def MOV32to32_ : I<0x89, MRMDestReg, (ops R32_:$dst, R32:$src), +def MOV32to32_ : I<0x89, MRMDestReg, (ops GR32_:$dst, GR32:$src), "mov{l} {$src, $dst|$dst, $src}", []>; -def MOV16_rr : I<0x89, MRMDestReg, (ops R16_:$dst, R16_:$src), +def MOV16_rr : I<0x89, MRMDestReg, (ops GR16_:$dst, GR16_:$src), "mov{w} {$src, $dst|$dst, $src}", []>, OpSize; -def MOV32_rr : I<0x89, MRMDestReg, (ops R32_:$dst, R32_:$src), +def MOV32_rr : I<0x89, MRMDestReg, (ops GR32_:$dst, GR32_:$src), "mov{l} {$src, $dst|$dst, $src}", []>; -def MOV16_rm : I<0x8B, MRMSrcMem, (ops R16_:$dst, i16mem:$src), +def MOV16_rm : I<0x8B, MRMSrcMem, (ops GR16_:$dst, i16mem:$src), "mov{w} {$src, $dst|$dst, $src}", []>, OpSize; -def MOV32_rm : I<0x8B, MRMSrcMem, (ops R32_:$dst, i32mem:$src), +def MOV32_rm : I<0x8B, MRMSrcMem, (ops GR32_:$dst, i32mem:$src), "mov{l} {$src, $dst|$dst, $src}", []>; -def MOV16_mr : I<0x89, MRMDestMem, (ops i16mem:$dst, R16_:$src), +def MOV16_mr : I<0x89, MRMDestMem, (ops i16mem:$dst, GR16_:$src), "mov{w} {$src, $dst|$dst, $src}", []>, OpSize; -def MOV32_mr : I<0x89, MRMDestMem, (ops i32mem:$dst, R32_:$src), +def MOV32_mr : I<0x89, MRMDestMem, (ops i32mem:$dst, GR32_:$src), "mov{l} {$src, $dst|$dst, $src}", []>; //===----------------------------------------------------------------------===// @@ -2351,14 +2351,14 @@ def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>; def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>; -def : Pat<(add R32:$src1, (X86Wrapper tconstpool:$src2)), - (ADD32ri R32:$src1, tconstpool:$src2)>; -def : Pat<(add R32:$src1, (X86Wrapper tjumptable:$src2)), - (ADD32ri R32:$src1, tjumptable:$src2)>; -def : Pat<(add R32:$src1, (X86Wrapper tglobaladdr :$src2)), - (ADD32ri R32:$src1, tglobaladdr:$src2)>; -def : Pat<(add R32:$src1, (X86Wrapper texternalsym:$src2)), - (ADD32ri R32:$src1, texternalsym:$src2)>; +def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)), + (ADD32ri GR32:$src1, tconstpool:$src2)>; +def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)), + (ADD32ri GR32:$src1, tjumptable:$src2)>; +def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)), + (ADD32ri GR32:$src1, tglobaladdr:$src2)>; +def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)), + (ADD32ri GR32:$src1, texternalsym:$src2)>; def : Pat<(store (X86Wrapper tglobaladdr:$src), addr:$dst), (MOV32mi addr:$dst, tglobaladdr:$src)>; @@ -2366,8 +2366,8 @@ (MOV32mi addr:$dst, texternalsym:$src)>; // Calls -def : Pat<(X86tailcall R32:$dst), - (CALL32r R32:$dst)>; +def : Pat<(X86tailcall GR32:$dst), + (CALL32r GR32:$dst)>; def : Pat<(X86tailcall (loadi32 addr:$dst)), (CALL32m addr:$dst)>; @@ -2385,28 +2385,28 @@ (CALLpcrel32 texternalsym:$dst)>; // X86 specific add which produces a flag. -def : Pat<(addc R32:$src1, R32:$src2), - (ADD32rr R32:$src1, R32:$src2)>; -def : Pat<(addc R32:$src1, (load addr:$src2)), - (ADD32rm R32:$src1, addr:$src2)>; -def : Pat<(addc R32:$src1, imm:$src2), - (ADD32ri R32:$src1, imm:$src2)>; -def : Pat<(addc R32:$src1, i32immSExt8:$src2), - (ADD32ri8 R32:$src1, i32immSExt8:$src2)>; - -def : Pat<(subc R32:$src1, R32:$src2), - (SUB32rr R32:$src1, R32:$src2)>; -def : Pat<(subc R32:$src1, (load addr:$src2)), - (SUB32rm R32:$src1, addr:$src2)>; -def : Pat<(subc R32:$src1, imm:$src2), - (SUB32ri R32:$src1, imm:$src2)>; -def : Pat<(subc R32:$src1, i32immSExt8:$src2), - (SUB32ri8 R32:$src1, i32immSExt8:$src2)>; +def : Pat<(addc GR32:$src1, GR32:$src2), + (ADD32rr GR32:$src1, GR32:$src2)>; +def : Pat<(addc GR32:$src1, (load addr:$src2)), + (ADD32rm GR32:$src1, addr:$src2)>; +def : Pat<(addc GR32:$src1, imm:$src2), + (ADD32ri GR32:$src1, imm:$src2)>; +def : Pat<(addc GR32:$src1, i32immSExt8:$src2), + (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>; + +def : Pat<(subc GR32:$src1, GR32:$src2), + (SUB32rr GR32:$src1, GR32:$src2)>; +def : Pat<(subc GR32:$src1, (load addr:$src2)), + (SUB32rm GR32:$src1, addr:$src2)>; +def : Pat<(subc GR32:$src1, imm:$src2), + (SUB32ri GR32:$src1, imm:$src2)>; +def : Pat<(subc GR32:$src1, i32immSExt8:$src2), + (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>; def : Pat<(truncstore (i8 imm:$src), addr:$dst, i1), (MOV8mi addr:$dst, imm:$src)>; -def : Pat<(truncstore R8:$src, addr:$dst, i1), - (MOV8mr addr:$dst, R8:$src)>; +def : Pat<(truncstore GR8:$src, addr:$dst, i1), + (MOV8mr addr:$dst, GR8:$src)>; // {s|z}extload bool -> {s|z}extload byte def : Pat<(sextloadi16i1 addr:$src), (MOVSX16rm8 addr:$src)>; @@ -2424,9 +2424,9 @@ def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>; // anyext -> zext -def : Pat<(i16 (anyext R8 :$src)), (MOVZX16rr8 R8 :$src)>; -def : Pat<(i32 (anyext R8 :$src)), (MOVZX32rr8 R8 :$src)>; -def : Pat<(i32 (anyext R16:$src)), (MOVZX32rr16 R16:$src)>; +def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>; +def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>; +def : Pat<(i32 (anyext GR16:$src)), (MOVZX32rr16 GR16:$src)>; def : Pat<(i16 (anyext (loadi8 addr:$src))), (MOVZX16rm8 addr:$src)>; def : Pat<(i32 (anyext (loadi8 addr:$src))), (MOVZX32rm8 addr:$src)>; def : Pat<(i32 (anyext (loadi16 addr:$src))), (MOVZX32rm16 addr:$src)>; @@ -2436,45 +2436,45 @@ //===----------------------------------------------------------------------===// // (shl x, 1) ==> (add x, x) -def : Pat<(shl R8 :$src1, (i8 1)), (ADD8rr R8 :$src1, R8 :$src1)>; -def : Pat<(shl R16:$src1, (i8 1)), (ADD16rr R16:$src1, R16:$src1)>; -def : Pat<(shl R32:$src1, (i8 1)), (ADD32rr R32:$src1, R32:$src1)>; +def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>; +def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>; +def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>; // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c) -def : Pat<(or (srl R32:$src1, CL:$amt), - (shl R32:$src2, (sub 32, CL:$amt))), - (SHRD32rrCL R32:$src1, R32:$src2)>; +def : Pat<(or (srl GR32:$src1, CL:$amt), + (shl GR32:$src2, (sub 32, CL:$amt))), + (SHRD32rrCL GR32:$src1, GR32:$src2)>; def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt), - (shl R32:$src2, (sub 32, CL:$amt))), addr:$dst), - (SHRD32mrCL addr:$dst, R32:$src2)>; + (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst), + (SHRD32mrCL addr:$dst, GR32:$src2)>; // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c) -def : Pat<(or (shl R32:$src1, CL:$amt), - (srl R32:$src2, (sub 32, CL:$amt))), - (SHLD32rrCL R32:$src1, R32:$src2)>; +def : Pat<(or (shl GR32:$src1, CL:$amt), + (srl GR32:$src2, (sub 32, CL:$amt))), + (SHLD32rrCL GR32:$src1, GR32:$src2)>; def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt), - (srl R32:$src2, (sub 32, CL:$amt))), addr:$dst), - (SHLD32mrCL addr:$dst, R32:$src2)>; + (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst), + (SHLD32mrCL addr:$dst, GR32:$src2)>; // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c) -def : Pat<(or (srl R16:$src1, CL:$amt), - (shl R16:$src2, (sub 16, CL:$amt))), - (SHRD16rrCL R16:$src1, R16:$src2)>; +def : Pat<(or (srl GR16:$src1, CL:$amt), + (shl GR16:$src2, (sub 16, CL:$amt))), + (SHRD16rrCL GR16:$src1, GR16:$src2)>; def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt), - (shl R16:$src2, (sub 16, CL:$amt))), addr:$dst), - (SHRD16mrCL addr:$dst, R16:$src2)>; + (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst), + (SHRD16mrCL addr:$dst, GR16:$src2)>; // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c) -def : Pat<(or (shl R16:$src1, CL:$amt), - (srl R16:$src2, (sub 16, CL:$amt))), - (SHLD16rrCL R16:$src1, R16:$src2)>; +def : Pat<(or (shl GR16:$src1, CL:$amt), + (srl GR16:$src2, (sub 16, CL:$amt))), + (SHLD16rrCL GR16:$src1, GR16:$src2)>; def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt), - (srl R16:$src2, (sub 16, CL:$amt))), addr:$dst), - (SHLD16mrCL addr:$dst, R16:$src2)>; + (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst), + (SHLD16mrCL addr:$dst, GR16:$src2)>; //===----------------------------------------------------------------------===// Index: llvm/lib/Target/X86/X86InstrMMX.td diff -u llvm/lib/Target/X86/X86InstrMMX.td:1.11 llvm/lib/Target/X86/X86InstrMMX.td:1.12 --- llvm/lib/Target/X86/X86InstrMMX.td:1.11 Wed Apr 12 18:42:44 2006 +++ llvm/lib/Target/X86/X86InstrMMX.td Tue May 16 02:21:53 2006 @@ -36,7 +36,7 @@ def : Pat<(v2i32 (undef)), (IMPLICIT_DEF_VR64)>, Requires<[HasMMX]>; // Move Instructions -def MOVD64rr : I<0x6E, MRMSrcReg, (ops VR64:$dst, R32:$src), +def MOVD64rr : I<0x6E, MRMSrcReg, (ops VR64:$dst, GR32:$src), "movd {$src, $dst|$dst, $src}", []>, TB, Requires<[HasMMX]>; def MOVD64rm : I<0x6E, MRMSrcMem, (ops VR64:$dst, i32mem:$src), Index: llvm/lib/Target/X86/X86InstrSSE.td diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.116 llvm/lib/Target/X86/X86InstrSSE.td:1.117 --- llvm/lib/Target/X86/X86InstrSSE.td:1.116 Fri May 5 16:35:18 2006 +++ llvm/lib/Target/X86/X86InstrSSE.td Tue May 16 02:21:53 2006 @@ -488,33 +488,33 @@ } // Conversion instructions -def CVTTSS2SIrr: SSI<0x2C, MRMSrcReg, (ops R32:$dst, FR32:$src), +def CVTTSS2SIrr: SSI<0x2C, MRMSrcReg, (ops GR32:$dst, FR32:$src), "cvttss2si {$src, $dst|$dst, $src}", - [(set R32:$dst, (fp_to_sint FR32:$src))]>; -def CVTTSS2SIrm: SSI<0x2C, MRMSrcMem, (ops R32:$dst, f32mem:$src), + [(set GR32:$dst, (fp_to_sint FR32:$src))]>; +def CVTTSS2SIrm: SSI<0x2C, MRMSrcMem, (ops GR32:$dst, f32mem:$src), "cvttss2si {$src, $dst|$dst, $src}", - [(set R32:$dst, (fp_to_sint (loadf32 addr:$src)))]>; -def CVTTSD2SIrr: SDI<0x2C, MRMSrcReg, (ops R32:$dst, FR64:$src), + [(set GR32:$dst, (fp_to_sint (loadf32 addr:$src)))]>; +def CVTTSD2SIrr: SDI<0x2C, MRMSrcReg, (ops GR32:$dst, FR64:$src), "cvttsd2si {$src, $dst|$dst, $src}", - [(set R32:$dst, (fp_to_sint FR64:$src))]>; -def CVTTSD2SIrm: SDI<0x2C, MRMSrcMem, (ops R32:$dst, f64mem:$src), + [(set GR32:$dst, (fp_to_sint FR64:$src))]>; +def CVTTSD2SIrm: SDI<0x2C, MRMSrcMem, (ops GR32:$dst, f64mem:$src), "cvttsd2si {$src, $dst|$dst, $src}", - [(set R32:$dst, (fp_to_sint (loadf64 addr:$src)))]>; + [(set GR32:$dst, (fp_to_sint (loadf64 addr:$src)))]>; def CVTSD2SSrr: SDI<0x5A, MRMSrcReg, (ops FR32:$dst, FR64:$src), "cvtsd2ss {$src, $dst|$dst, $src}", [(set FR32:$dst, (fround FR64:$src))]>; def CVTSD2SSrm: SDI<0x5A, MRMSrcMem, (ops FR32:$dst, f64mem:$src), "cvtsd2ss {$src, $dst|$dst, $src}", [(set FR32:$dst, (fround (loadf64 addr:$src)))]>; -def CVTSI2SSrr: SSI<0x2A, MRMSrcReg, (ops FR32:$dst, R32:$src), +def CVTSI2SSrr: SSI<0x2A, MRMSrcReg, (ops FR32:$dst, GR32:$src), "cvtsi2ss {$src, $dst|$dst, $src}", - [(set FR32:$dst, (sint_to_fp R32:$src))]>; + [(set FR32:$dst, (sint_to_fp GR32:$src))]>; def CVTSI2SSrm: SSI<0x2A, MRMSrcMem, (ops FR32:$dst, i32mem:$src), "cvtsi2ss {$src, $dst|$dst, $src}", [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>; -def CVTSI2SDrr: SDI<0x2A, MRMSrcReg, (ops FR64:$dst, R32:$src), +def CVTSI2SDrr: SDI<0x2A, MRMSrcReg, (ops FR64:$dst, GR32:$src), "cvtsi2sd {$src, $dst|$dst, $src}", - [(set FR64:$dst, (sint_to_fp R32:$src))]>; + [(set FR64:$dst, (sint_to_fp GR32:$src))]>; def CVTSI2SDrm: SDI<0x2A, MRMSrcMem, (ops FR64:$dst, i32mem:$src), "cvtsi2sd {$src, $dst|$dst, $src}", [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>; @@ -530,43 +530,43 @@ Requires<[HasSSE2]>; // Match intrinsics which expect XMM operand(s). -def CVTSS2SIrr: SSI<0x2D, MRMSrcReg, (ops R32:$dst, VR128:$src), +def CVTSS2SIrr: SSI<0x2D, MRMSrcReg, (ops GR32:$dst, VR128:$src), "cvtss2si {$src, $dst|$dst, $src}", - [(set R32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>; -def CVTSS2SIrm: SSI<0x2D, MRMSrcMem, (ops R32:$dst, f32mem:$src), + [(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>; +def CVTSS2SIrm: SSI<0x2D, MRMSrcMem, (ops GR32:$dst, f32mem:$src), "cvtss2si {$src, $dst|$dst, $src}", - [(set R32:$dst, (int_x86_sse_cvtss2si + [(set GR32:$dst, (int_x86_sse_cvtss2si (loadv4f32 addr:$src)))]>; -def CVTSD2SIrr: SDI<0x2D, MRMSrcReg, (ops R32:$dst, VR128:$src), +def CVTSD2SIrr: SDI<0x2D, MRMSrcReg, (ops GR32:$dst, VR128:$src), "cvtsd2si {$src, $dst|$dst, $src}", - [(set R32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>; -def CVTSD2SIrm: SDI<0x2D, MRMSrcMem, (ops R32:$dst, f128mem:$src), + [(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>; +def CVTSD2SIrm: SDI<0x2D, MRMSrcMem, (ops GR32:$dst, f128mem:$src), "cvtsd2si {$src, $dst|$dst, $src}", - [(set R32:$dst, (int_x86_sse2_cvtsd2si + [(set GR32:$dst, (int_x86_sse2_cvtsd2si (loadv2f64 addr:$src)))]>; // Aliases for intrinsics -def Int_CVTTSS2SIrr: SSI<0x2C, MRMSrcReg, (ops R32:$dst, VR128:$src), +def Int_CVTTSS2SIrr: SSI<0x2C, MRMSrcReg, (ops GR32:$dst, VR128:$src), "cvttss2si {$src, $dst|$dst, $src}", - [(set R32:$dst, (int_x86_sse_cvttss2si VR128:$src))]>; -def Int_CVTTSS2SIrm: SSI<0x2C, MRMSrcMem, (ops R32:$dst, f32mem:$src), + [(set GR32:$dst, (int_x86_sse_cvttss2si VR128:$src))]>; +def Int_CVTTSS2SIrm: SSI<0x2C, MRMSrcMem, (ops GR32:$dst, f32mem:$src), "cvttss2si {$src, $dst|$dst, $src}", - [(set R32:$dst, (int_x86_sse_cvttss2si + [(set GR32:$dst, (int_x86_sse_cvttss2si (loadv4f32 addr:$src)))]>; -def Int_CVTTSD2SIrr: SDI<0x2C, MRMSrcReg, (ops R32:$dst, VR128:$src), +def Int_CVTTSD2SIrr: SDI<0x2C, MRMSrcReg, (ops GR32:$dst, VR128:$src), "cvttsd2si {$src, $dst|$dst, $src}", - [(set R32:$dst, (int_x86_sse2_cvttsd2si VR128:$src))]>; -def Int_CVTTSD2SIrm: SDI<0x2C, MRMSrcMem, (ops R32:$dst, f128mem:$src), + [(set GR32:$dst, (int_x86_sse2_cvttsd2si VR128:$src))]>; +def Int_CVTTSD2SIrm: SDI<0x2C, MRMSrcMem, (ops GR32:$dst, f128mem:$src), "cvttsd2si {$src, $dst|$dst, $src}", - [(set R32:$dst, (int_x86_sse2_cvttsd2si + [(set GR32:$dst, (int_x86_sse2_cvttsd2si (loadv2f64 addr:$src)))]>; let isTwoAddress = 1 in { def Int_CVTSI2SSrr: SSI<0x2A, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, R32:$src2), + (ops VR128:$dst, VR128:$src1, GR32:$src2), "cvtsi2ss {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1, - R32:$src2))]>; + GR32:$src2))]>; def Int_CVTSI2SSrm: SSI<0x2A, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i32mem:$src2), "cvtsi2ss {$src2, $dst|$dst, $src2}", @@ -960,10 +960,10 @@ // Aliases for intrinsics let isTwoAddress = 1 in { def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, R32:$src2), + (ops VR128:$dst, VR128:$src1, GR32:$src2), "cvtsi2sd {$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1, - R32:$src2))]>; + GR32:$src2))]>; def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i32mem:$src2), "cvtsi2sd {$src2, $dst|$dst, $src2}", @@ -2003,16 +2003,16 @@ // Extract / Insert def PEXTRWri : PDIi8<0xC5, MRMSrcReg, - (ops R32:$dst, VR128:$src1, i32i8imm:$src2), + (ops GR32:$dst, VR128:$src1, i32i8imm:$src2), "pextrw {$src2, $src1, $dst|$dst, $src1, $src2}", - [(set R32:$dst, (X86pextrw (v8i16 VR128:$src1), + [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1), (i32 imm:$src2)))]>; let isTwoAddress = 1 in { def PINSRWrri : PDIi8<0xC4, MRMSrcReg, - (ops VR128:$dst, VR128:$src1, R32:$src2, i32i8imm:$src3), + (ops VR128:$dst, VR128:$src1, GR32:$src2, i32i8imm:$src3), "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}", [(set VR128:$dst, (v8i16 (X86pinsrw (v8i16 VR128:$src1), - R32:$src2, (i32 imm:$src3))))]>; + GR32:$src2, (i32 imm:$src3))))]>; def PINSRWrmi : PDIi8<0xC4, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i16mem:$src2, i32i8imm:$src3), "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}", @@ -2027,16 +2027,16 @@ //===----------------------------------------------------------------------===// // Mask creation -def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (ops R32:$dst, VR128:$src), +def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (ops GR32:$dst, VR128:$src), "movmskps {$src, $dst|$dst, $src}", - [(set R32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>; -def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (ops R32:$dst, VR128:$src), + [(set GR32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>; +def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (ops GR32:$dst, VR128:$src), "movmskpd {$src, $dst|$dst, $src}", - [(set R32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>; + [(set GR32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>; -def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (ops R32:$dst, VR128:$src), +def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (ops GR32:$dst, VR128:$src), "pmovmskb {$src, $dst|$dst, $src}", - [(set R32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>; + [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>; // Conditional store def MASKMOVDQU : PDI<0xF7, RawFrm, (ops VR128:$src, VR128:$mask), @@ -2064,9 +2064,9 @@ def MOVNTDQmr : PDI<0xE7, MRMDestMem, (ops f128mem:$dst, VR128:$src), "movntdq {$src, $dst|$dst, $src}", [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>; -def MOVNTImr : I<0xC3, MRMDestMem, (ops i32mem:$dst, R32:$src), +def MOVNTImr : I<0xC3, MRMDestMem, (ops i32mem:$dst, GR32:$src), "movnti {$src, $dst|$dst, $src}", - [(int_x86_sse2_movnt_i addr:$dst, R32:$src)]>, + [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>, TB, Requires<[HasSSE2]>; // Flush cache @@ -2136,10 +2136,10 @@ [(set VR128:$dst, (v2f64 (scalar_to_vector (loadf64 addr:$src))))]>; -def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, R32:$src), +def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, GR32:$src), "movd {$src, $dst|$dst, $src}", [(set VR128:$dst, - (v4i32 (scalar_to_vector R32:$src)))]>; + (v4i32 (scalar_to_vector GR32:$src)))]>; def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (ops VR128:$dst, i32mem:$src), "movd {$src, $dst|$dst, $src}", [(set VR128:$dst, @@ -2176,9 +2176,9 @@ "movsd {$src, $dst|$dst, $src}", [(store (f64 (vector_extract (v2f64 VR128:$src), (i32 0))), addr:$dst)]>; -def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (ops R32:$dst, VR128:$src), +def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (ops GR32:$dst, VR128:$src), "movd {$src, $dst|$dst, $src}", - [(set R32:$dst, (vector_extract (v4i32 VR128:$src), + [(set GR32:$dst, (vector_extract (v4i32 VR128:$src), (i32 0)))]>; def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (ops i32mem:$dst, VR128:$src), "movd {$src, $dst|$dst, $src}", @@ -2226,10 +2226,10 @@ (v2f64 (scalar_to_vector (loadf64 addr:$src))), MOVL_shuffle_mask)))]>; // movd / movq to XMM register zero-extends -def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, R32:$src), +def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, GR32:$src), "movd {$src, $dst|$dst, $src}", [(set VR128:$dst, (v4i32 (vector_shuffle immAllZerosV, - (v4i32 (scalar_to_vector R32:$src)), + (v4i32 (scalar_to_vector GR32:$src)), MOVL_shuffle_mask)))]>; def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (ops VR128:$dst, i32mem:$src), "movd {$src, $dst|$dst, $src}", @@ -2279,11 +2279,11 @@ def : Pat<(store (v4i32 VR128:$src), addr:$dst), (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>; -// Scalar to v8i16 / v16i8. The source may be a R32, but only the lower 8 or +// Scalar to v8i16 / v16i8. The source may be a GR32, but only the lower 8 or // 16-bits matter. -def : Pat<(v8i16 (X86s2vec R32:$src)), (v8i16 (MOVDI2PDIrr R32:$src))>, +def : Pat<(v8i16 (X86s2vec GR32:$src)), (v8i16 (MOVDI2PDIrr GR32:$src))>, Requires<[HasSSE2]>; -def : Pat<(v16i8 (X86s2vec R32:$src)), (v16i8 (MOVDI2PDIrr R32:$src))>, +def : Pat<(v16i8 (X86s2vec GR32:$src)), (v16i8 (MOVDI2PDIrr GR32:$src))>, Requires<[HasSSE2]>; // bit_convert @@ -2352,11 +2352,11 @@ // movd to XMM register zero-extends let AddedComplexity = 20 in { def : Pat<(v8i16 (vector_shuffle immAllZerosV, - (v8i16 (X86s2vec R32:$src)), MOVL_shuffle_mask)), - (v8i16 (MOVZDI2PDIrr R32:$src))>, Requires<[HasSSE2]>; + (v8i16 (X86s2vec GR32:$src)), MOVL_shuffle_mask)), + (v8i16 (MOVZDI2PDIrr GR32:$src))>, Requires<[HasSSE2]>; def : Pat<(v16i8 (vector_shuffle immAllZerosV, - (v16i8 (X86s2vec R32:$src)), MOVL_shuffle_mask)), - (v16i8 (MOVZDI2PDIrr R32:$src))>, Requires<[HasSSE2]>; + (v16i8 (X86s2vec GR32:$src)), MOVL_shuffle_mask)), + (v16i8 (MOVZDI2PDIrr GR32:$src))>, Requires<[HasSSE2]>; // Zeroing a VR128 then do a MOVS{S|D} to the lower bits. def : Pat<(v2f64 (vector_shuffle immAllZerosV, (v2f64 (scalar_to_vector FR64:$src)), MOVL_shuffle_mask)), Index: llvm/lib/Target/X86/X86IntelAsmPrinter.cpp diff -u llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.49 llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.50 --- llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.49 Tue May 9 00:33:48 2006 +++ llvm/lib/Target/X86/X86IntelAsmPrinter.cpp Tue May 16 02:21:53 2006 @@ -261,14 +261,14 @@ // See if a truncate instruction can be turned into a nop. switch (MI->getOpcode()) { default: break; - case X86::TRUNC_R32_R16: - case X86::TRUNC_R32_R8: - case X86::TRUNC_R16_R8: { + case X86::TRUNC_GR32_GR16: + case X86::TRUNC_GR32_GR8: + case X86::TRUNC_GR16_GR8: { const MachineOperand &MO0 = MI->getOperand(0); const MachineOperand &MO1 = MI->getOperand(1); unsigned Reg0 = MO0.getReg(); unsigned Reg1 = MO1.getReg(); - if (MI->getOpcode() == X86::TRUNC_R32_R16) + if (MI->getOpcode() == X86::TRUNC_GR32_GR16) Reg1 = getX86SubSuperRegister(Reg1, MVT::i16); else Reg1 = getX86SubSuperRegister(Reg1, MVT::i8); Index: llvm/lib/Target/X86/X86RegisterInfo.cpp diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.152 llvm/lib/Target/X86/X86RegisterInfo.cpp:1.153 --- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.152 Fri May 12 16:14:20 2006 +++ llvm/lib/Target/X86/X86RegisterInfo.cpp Tue May 16 02:21:53 2006 @@ -50,15 +50,15 @@ unsigned SrcReg, int FrameIdx, const TargetRegisterClass *RC) const { unsigned Opc; - if (RC == &X86::R32RegClass) { + if (RC == &X86::GR32RegClass) { Opc = X86::MOV32mr; - } else if (RC == &X86::R16RegClass) { + } else if (RC == &X86::GR16RegClass) { Opc = X86::MOV16mr; - } else if (RC == &X86::R8RegClass) { + } else if (RC == &X86::GR8RegClass) { Opc = X86::MOV8mr; - } else if (RC == &X86::R32_RegClass) { + } else if (RC == &X86::GR32_RegClass) { Opc = X86::MOV32_mr; - } else if (RC == &X86::R16_RegClass) { + } else if (RC == &X86::GR16_RegClass) { Opc = X86::MOV16_mr; } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) { Opc = X86::FpST64m; @@ -80,15 +80,15 @@ unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC) const{ unsigned Opc; - if (RC == &X86::R32RegClass) { + if (RC == &X86::GR32RegClass) { Opc = X86::MOV32rm; - } else if (RC == &X86::R16RegClass) { + } else if (RC == &X86::GR16RegClass) { Opc = X86::MOV16rm; - } else if (RC == &X86::R8RegClass) { + } else if (RC == &X86::GR8RegClass) { Opc = X86::MOV8rm; - } else if (RC == &X86::R32_RegClass) { + } else if (RC == &X86::GR32_RegClass) { Opc = X86::MOV32_rm; - } else if (RC == &X86::R16_RegClass) { + } else if (RC == &X86::GR16_RegClass) { Opc = X86::MOV16_rm; } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) { Opc = X86::FpLD64m; @@ -110,15 +110,15 @@ unsigned DestReg, unsigned SrcReg, const TargetRegisterClass *RC) const { unsigned Opc; - if (RC == &X86::R32RegClass) { + if (RC == &X86::GR32RegClass) { Opc = X86::MOV32rr; - } else if (RC == &X86::R16RegClass) { + } else if (RC == &X86::GR16RegClass) { Opc = X86::MOV16rr; - } else if (RC == &X86::R8RegClass) { + } else if (RC == &X86::GR8RegClass) { Opc = X86::MOV8rr; - } else if (RC == &X86::R32_RegClass) { + } else if (RC == &X86::GR32_RegClass) { Opc = X86::MOV32_rr; - } else if (RC == &X86::R16_RegClass) { + } else if (RC == &X86::GR16_RegClass) { Opc = X86::MOV16_rr; } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) { Opc = X86::FpMOV; Index: llvm/lib/Target/X86/X86RegisterInfo.td diff -u llvm/lib/Target/X86/X86RegisterInfo.td:1.34 llvm/lib/Target/X86/X86RegisterInfo.td:1.35 --- llvm/lib/Target/X86/X86RegisterInfo.td:1.34 Mon May 8 03:01:26 2006 +++ llvm/lib/Target/X86/X86RegisterInfo.td Tue May 16 02:21:53 2006 @@ -103,15 +103,15 @@ // dependences between upper and lower parts of the register. BL and BH are // last because they are call clobbered. Both Athlon and P4 chips suffer this // issue. -def R8 : RegisterClass<"X86", [i8], 8, [AL, CL, DL, AH, CH, DH, BL, BH]>; +def GR8 : RegisterClass<"X86", [i8], 8, [AL, CL, DL, AH, CH, DH, BL, BH]>; -def R16 : RegisterClass<"X86", [i16], 16, [AX, CX, DX, SI, DI, BX, BP, SP]> { +def GR16 : RegisterClass<"X86", [i16], 16, [AX, CX, DX, SI, DI, BX, BP, SP]> { let MethodProtos = [{ iterator allocation_order_end(MachineFunction &MF) const; }]; let MethodBodies = [{ - R16Class::iterator - R16Class::allocation_order_end(MachineFunction &MF) const { + GR16Class::iterator + GR16Class::allocation_order_end(MachineFunction &MF) const { if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr? return end()-2; // If so, don't allocate SP or BP else @@ -120,14 +120,14 @@ }]; } -def R32 : RegisterClass<"X86", [i32], 32, - [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP]> { +def GR32 : RegisterClass<"X86", [i32], 32, + [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP]> { let MethodProtos = [{ iterator allocation_order_end(MachineFunction &MF) const; }]; let MethodBodies = [{ - R32Class::iterator - R32Class::allocation_order_end(MachineFunction &MF) const { + GR32Class::iterator + GR32Class::allocation_order_end(MachineFunction &MF) const { if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr? return end()-2; // If so, don't allocate ESP or EBP else @@ -136,9 +136,9 @@ }]; } -// R16, R32 subclasses which contain registers that have R8 sub-registers. -def R16_ : RegisterClass<"X86", [i16], 16, [AX, CX, DX, BX]>; -def R32_ : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, EBX]>; +// GR16, GR32 subclasses which contain registers that have R8 sub-registers. +def GR16_ : RegisterClass<"X86", [i16], 16, [AX, CX, DX, BX]>; +def GR32_ : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, EBX]>; // Scalar SSE2 floating point registers. def FR32 : RegisterClass<"X86", [f32], 32, From reid at x10sys.com Tue May 16 03:53:47 2006 From: reid at x10sys.com (Reid Spencer) Date: Tue, 16 May 2006 03:53:47 -0500 Subject: [llvm-commits] CVS: llvm/configure Message-ID: <200605160853.DAA14015@zion.cs.uiuc.edu> Changes in directory llvm: configure updated: 1.228 -> 1.229 --- Log message: Make sure to default ${prefix} to /usr/local if the user didn't specify it. This assists with getting around configure's late binding values so that our LLVM variables don't end up with a "NONE" prefix. --- Diffs of the changes: (+3 -0) configure | 3 +++ 1 files changed, 3 insertions(+) Index: llvm/configure diff -u llvm/configure:1.228 llvm/configure:1.229 --- llvm/configure:1.228 Sun May 14 17:18:28 2006 +++ llvm/configure Tue May 16 03:53:32 2006 @@ -30739,6 +30739,9 @@ # Translate the various configuration directories and other basic # information into substitutions that will end up in Makefile.config.in # that these configured values can be used by the makefiles +if test "${prefix}" == "NONE" ; then + prefix="/usr/local" +fi eval LLVM_PREFIX="${prefix}"; eval LLVM_BINDIR="${prefix}/bin"; eval LLVM_LIBDIR="${prefix}/lib"; From reid at x10sys.com Tue May 16 03:53:46 2006 From: reid at x10sys.com (Reid Spencer) Date: Tue, 16 May 2006 03:53:46 -0500 Subject: [llvm-commits] CVS: llvm/autoconf/configure.ac Message-ID: <200605160853.DAA14011@zion.cs.uiuc.edu> Changes in directory llvm/autoconf: configure.ac updated: 1.225 -> 1.226 --- Log message: Make sure to default ${prefix} to /usr/local if the user didn't specify it. This assists with getting around configure's late binding values so that our LLVM variables don't end up with a "NONE" prefix. --- Diffs of the changes: (+3 -0) configure.ac | 3 +++ 1 files changed, 3 insertions(+) Index: llvm/autoconf/configure.ac diff -u llvm/autoconf/configure.ac:1.225 llvm/autoconf/configure.ac:1.226 --- llvm/autoconf/configure.ac:1.225 Sun May 14 17:18:28 2006 +++ llvm/autoconf/configure.ac Tue May 16 03:53:32 2006 @@ -632,6 +632,9 @@ # Translate the various configuration directories and other basic # information into substitutions that will end up in Makefile.config.in # that these configured values can be used by the makefiles +if test "${prefix}" == "NONE" ; then + prefix="/usr/local" +fi eval LLVM_PREFIX="${prefix}"; eval LLVM_BINDIR="${prefix}/bin"; eval LLVM_LIBDIR="${prefix}/lib"; From lattner at cs.uiuc.edu Tue May 16 12:09:00 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 16 May 2006 12:09:00 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp Message-ID: <200605161709.MAA16117@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.203 -> 1.204 --- Log message: Fix a bug I introduced yesterday, which broke functions with *no* arguments. --- Diffs of the changes: (+7 -0) X86ISelLowering.cpp | 7 +++++++ 1 files changed, 7 insertions(+) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.203 llvm/lib/Target/X86/X86ISelLowering.cpp:1.204 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.203 Tue May 16 02:21:53 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Tue May 16 12:08:35 2006 @@ -542,6 +542,9 @@ } FormalArgs.push_back(ArgValue); } + // Provide a chain. Note that this isn't the right one, but it works as well + // as before. + FormalArgs.push_back(DAG.getEntryNode()); } std::pair @@ -1081,6 +1084,10 @@ } FormalArgs.push_back(ArgValue); } + + // Provide a chain. Note that this isn't the right one, but it works as well + // as before. + FormalArgs.push_back(DAG.getEntryNode()); } std::pair From lattner at cs.uiuc.edu Tue May 16 12:14:38 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 16 May 2006 12:14:38 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp Message-ID: <200605161714.MAA16471@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.204 -> 1.205 --- Log message: Implement the custom lowering hook right, returning values for all of the arguments at once. --- Diffs of the changes: (+5 -1) X86ISelLowering.cpp | 6 +++++- 1 files changed, 5 insertions(+), 1 deletion(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.204 llvm/lib/Target/X86/X86ISelLowering.cpp:1.205 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.204 Tue May 16 12:08:35 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Tue May 16 12:14:26 2006 @@ -3519,7 +3519,11 @@ else LowerCCCArguments(Op, DAG); } - return FormalArgs[Op.ResNo]; + + // Return the new list of results. + std::vector RetVTs(Op.Val->value_begin(), + Op.Val->value_end()); + return DAG.getNode(ISD::MERGE_VALUES, RetVTs, FormalArgs); } SDOperand X86TargetLowering::LowerMEMSET(SDOperand Op, SelectionDAG &DAG) { From lattner at cs.uiuc.edu Tue May 16 12:22:54 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 16 May 2006 12:22:54 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/X86/lea.ll Message-ID: <200605161722.MAA17093@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/X86: lea.ll (r1.2) removed --- Log message: Remove this xfail-d test, which doesn't make any sense --- Diffs of the changes: (+0 -0) 0 files changed From alenhar2 at cs.uiuc.edu Tue May 16 12:42:29 2006 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Tue, 16 May 2006 12:42:29 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <200605161742.MAA17615@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.169 -> 1.170 --- Log message: Move this code to a common place --- Diffs of the changes: (+14 -238) DAGCombiner.cpp | 252 +++----------------------------------------------------- 1 files changed, 14 insertions(+), 238 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.169 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.170 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.169 Fri May 12 12:57:54 2006 +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue May 16 12:42:15 2006 @@ -271,178 +271,6 @@ //===----------------------------------------------------------------------===// -struct ms { - int64_t m; // magic number - int64_t s; // shift amount -}; - -struct mu { - uint64_t m; // magic number - int64_t a; // add indicator - int64_t s; // shift amount -}; - -/// magic - calculate the magic numbers required to codegen an integer sdiv as -/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, -/// or -1. -static ms magic32(int32_t d) { - int32_t p; - uint32_t ad, anc, delta, q1, r1, q2, r2, t; - const uint32_t two31 = 0x80000000U; - struct ms mag; - - ad = abs(d); - t = two31 + ((uint32_t)d >> 31); - anc = t - 1 - t%ad; // absolute value of nc - p = 31; // initialize p - q1 = two31/anc; // initialize q1 = 2p/abs(nc) - r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc)) - q2 = two31/ad; // initialize q2 = 2p/abs(d) - r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d)) - do { - p = p + 1; - q1 = 2*q1; // update q1 = 2p/abs(nc) - r1 = 2*r1; // update r1 = rem(2p/abs(nc)) - if (r1 >= anc) { // must be unsigned comparison - q1 = q1 + 1; - r1 = r1 - anc; - } - q2 = 2*q2; // update q2 = 2p/abs(d) - r2 = 2*r2; // update r2 = rem(2p/abs(d)) - if (r2 >= ad) { // must be unsigned comparison - q2 = q2 + 1; - r2 = r2 - ad; - } - delta = ad - r2; - } while (q1 < delta || (q1 == delta && r1 == 0)); - - mag.m = (int32_t)(q2 + 1); // make sure to sign extend - if (d < 0) mag.m = -mag.m; // resulting magic number - mag.s = p - 32; // resulting shift - return mag; -} - -/// magicu - calculate the magic numbers required to codegen an integer udiv as -/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. -static mu magicu32(uint32_t d) { - int32_t p; - uint32_t nc, delta, q1, r1, q2, r2; - struct mu magu; - magu.a = 0; // initialize "add" indicator - nc = - 1 - (-d)%d; - p = 31; // initialize p - q1 = 0x80000000/nc; // initialize q1 = 2p/nc - r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc) - q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d - r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d) - do { - p = p + 1; - if (r1 >= nc - r1 ) { - q1 = 2*q1 + 1; // update q1 - r1 = 2*r1 - nc; // update r1 - } - else { - q1 = 2*q1; // update q1 - r1 = 2*r1; // update r1 - } - if (r2 + 1 >= d - r2) { - if (q2 >= 0x7FFFFFFF) magu.a = 1; - q2 = 2*q2 + 1; // update q2 - r2 = 2*r2 + 1 - d; // update r2 - } - else { - if (q2 >= 0x80000000) magu.a = 1; - q2 = 2*q2; // update q2 - r2 = 2*r2 + 1; // update r2 - } - delta = d - 1 - r2; - } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0))); - magu.m = q2 + 1; // resulting magic number - magu.s = p - 32; // resulting shift - return magu; -} - -/// magic - calculate the magic numbers required to codegen an integer sdiv as -/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, -/// or -1. -static ms magic64(int64_t d) { - int64_t p; - uint64_t ad, anc, delta, q1, r1, q2, r2, t; - const uint64_t two63 = 9223372036854775808ULL; // 2^63 - struct ms mag; - - ad = d >= 0 ? d : -d; - t = two63 + ((uint64_t)d >> 63); - anc = t - 1 - t%ad; // absolute value of nc - p = 63; // initialize p - q1 = two63/anc; // initialize q1 = 2p/abs(nc) - r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc)) - q2 = two63/ad; // initialize q2 = 2p/abs(d) - r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d)) - do { - p = p + 1; - q1 = 2*q1; // update q1 = 2p/abs(nc) - r1 = 2*r1; // update r1 = rem(2p/abs(nc)) - if (r1 >= anc) { // must be unsigned comparison - q1 = q1 + 1; - r1 = r1 - anc; - } - q2 = 2*q2; // update q2 = 2p/abs(d) - r2 = 2*r2; // update r2 = rem(2p/abs(d)) - if (r2 >= ad) { // must be unsigned comparison - q2 = q2 + 1; - r2 = r2 - ad; - } - delta = ad - r2; - } while (q1 < delta || (q1 == delta && r1 == 0)); - - mag.m = q2 + 1; - if (d < 0) mag.m = -mag.m; // resulting magic number - mag.s = p - 64; // resulting shift - return mag; -} - -/// magicu - calculate the magic numbers required to codegen an integer udiv as -/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. -static mu magicu64(uint64_t d) -{ - int64_t p; - uint64_t nc, delta, q1, r1, q2, r2; - struct mu magu; - magu.a = 0; // initialize "add" indicator - nc = - 1 - (-d)%d; - p = 63; // initialize p - q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc - r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc) - q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d - r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d) - do { - p = p + 1; - if (r1 >= nc - r1 ) { - q1 = 2*q1 + 1; // update q1 - r1 = 2*r1 - nc; // update r1 - } - else { - q1 = 2*q1; // update q1 - r1 = 2*r1; // update r1 - } - if (r2 + 1 >= d - r2) { - if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1; - q2 = 2*q2 + 1; // update q2 - r2 = 2*r2 + 1 - d; // update r2 - } - else { - if (q2 >= 0x8000000000000000ull) magu.a = 1; - q2 = 2*q2; // update q2 - r2 = 2*r2 + 1; // update r2 - } - delta = d - 1 - r2; - } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0))); - magu.m = q2 + 1; // resulting magic number - magu.s = p - 64; // resulting shift - return magu; -} - // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc // that selects between the values 1 and 0, making it equivalent to a setcc. // Also, set the incoming LHS, RHS, and CC references to the appropriate @@ -3607,42 +3435,13 @@ /// multiplying by a magic number. See: /// SDOperand DAGCombiner::BuildSDIV(SDNode *N) { - MVT::ValueType VT = N->getValueType(0); - - // Check to see if we can do this. - if (!TLI.isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) - return SDOperand(); // BuildSDIV only operates on i32 or i64 - if (!TLI.isOperationLegal(ISD::MULHS, VT)) - return SDOperand(); // Make sure the target supports MULHS. - - int64_t d = cast(N->getOperand(1))->getSignExtended(); - ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d); - - // Multiply the numerator (operand 0) by the magic value - SDOperand Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0), - DAG.getConstant(magics.m, VT)); - // If d > 0 and m < 0, add the numerator - if (d > 0 && magics.m < 0) { - Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0)); - AddToWorkList(Q.Val); - } - // If d < 0 and m > 0, subtract the numerator. - if (d < 0 && magics.m > 0) { - Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0)); - AddToWorkList(Q.Val); - } - // Shift right algebraic if shift value is nonzero - if (magics.s > 0) { - Q = DAG.getNode(ISD::SRA, VT, Q, - DAG.getConstant(magics.s, TLI.getShiftAmountTy())); - AddToWorkList(Q.Val); - } - // Extract the sign bit and add it to the quotient - SDOperand T = - DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(MVT::getSizeInBits(VT)-1, - TLI.getShiftAmountTy())); - AddToWorkList(T.Val); - return DAG.getNode(ISD::ADD, VT, Q, T); + std::list Built; + SDOperand S = TLI.BuildSDIV(N, DAG, &Built); + + for (std::list::iterator ii = Built.begin(), ee = Built.end(); + ii != ee; ++ii) + AddToWorkList(*ii); + return S; } /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, @@ -3650,36 +3449,13 @@ /// multiplying by a magic number. See: /// SDOperand DAGCombiner::BuildUDIV(SDNode *N) { - MVT::ValueType VT = N->getValueType(0); - - // Check to see if we can do this. - if (!TLI.isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) - return SDOperand(); // BuildUDIV only operates on i32 or i64 - if (!TLI.isOperationLegal(ISD::MULHU, VT)) - return SDOperand(); // Make sure the target supports MULHU. - - uint64_t d = cast(N->getOperand(1))->getValue(); - mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d); - - // Multiply the numerator (operand 0) by the magic value - SDOperand Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0), - DAG.getConstant(magics.m, VT)); - AddToWorkList(Q.Val); - - if (magics.a == 0) { - return DAG.getNode(ISD::SRL, VT, Q, - DAG.getConstant(magics.s, TLI.getShiftAmountTy())); - } else { - SDOperand NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q); - AddToWorkList(NPQ.Val); - NPQ = DAG.getNode(ISD::SRL, VT, NPQ, - DAG.getConstant(1, TLI.getShiftAmountTy())); - AddToWorkList(NPQ.Val); - NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q); - AddToWorkList(NPQ.Val); - return DAG.getNode(ISD::SRL, VT, NPQ, - DAG.getConstant(magics.s-1, TLI.getShiftAmountTy())); - } + std::list Built; + SDOperand S = TLI.BuildUDIV(N, DAG, &Built); + + for (std::list::iterator ii = Built.begin(), ee = Built.end(); + ii != ee; ++ii) + AddToWorkList(*ii); + return S; } // SelectionDAG::Combine - This is the entry point for the file. From alenhar2 at cs.uiuc.edu Tue May 16 12:42:30 2006 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Tue, 16 May 2006 12:42:30 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Message-ID: <200605161742.MAA17619@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/IA64: IA64ISelDAGToDAG.cpp updated: 1.39 -> 1.40 --- Log message: Move this code to a common place --- Diffs of the changes: (+0 -3) IA64ISelDAGToDAG.cpp | 3 --- 1 files changed, 3 deletions(-) Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.39 llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.40 --- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.39 Sat Mar 25 00:47:10 2006 +++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Tue May 16 12:42:15 2006 @@ -81,9 +81,6 @@ /// operation. bool SelectAddr(SDOperand Addr, SDOperand &Op1, SDOperand &Op2); - SDOperand BuildSDIVSequence(SDNode *N); - SDOperand BuildUDIVSequence(SDNode *N); - /// InstructionSelectBasicBlock - This callback is invoked by /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. virtual void InstructionSelectBasicBlock(SelectionDAG &DAG); From alenhar2 at cs.uiuc.edu Tue May 16 12:42:31 2006 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Tue, 16 May 2006 12:42:31 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelLowering.cpp Message-ID: <200605161742.MAA17623@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Alpha: AlphaISelLowering.cpp updated: 1.48 -> 1.49 --- Log message: Move this code to a common place --- Diffs of the changes: (+4 -148) AlphaISelLowering.cpp | 152 +------------------------------------------------- 1 files changed, 4 insertions(+), 148 deletions(-) Index: llvm/lib/Target/Alpha/AlphaISelLowering.cpp diff -u llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.48 llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.49 --- llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.48 Fri May 12 13:17:25 2006 +++ llvm/lib/Target/Alpha/AlphaISelLowering.cpp Tue May 16 12:42:15 2006 @@ -25,151 +25,6 @@ #include using namespace llvm; -//Shamelessly adapted from PPC32 -// Structure used to return the necessary information to codegen an SDIV as -// a multiply. -struct ms { - int64_t m; // magic number - int64_t s; // shift amount -}; - -struct mu { - uint64_t m; // magic number - int64_t a; // add indicator - int64_t s; // shift amount -}; - -/// magic - calculate the magic numbers required to codegen an integer sdiv as -/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, -/// or -1. -static struct ms magic(int64_t d) { - int64_t p; - uint64_t ad, anc, delta, q1, r1, q2, r2, t; - const uint64_t two63 = 9223372036854775808ULL; // 2^63 - struct ms mag; - - ad = llabs(d); - t = two63 + ((uint64_t)d >> 63); - anc = t - 1 - t%ad; // absolute value of nc - p = 63; // initialize p - q1 = two63/anc; // initialize q1 = 2p/abs(nc) - r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc)) - q2 = two63/ad; // initialize q2 = 2p/abs(d) - r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d)) - do { - p = p + 1; - q1 = 2*q1; // update q1 = 2p/abs(nc) - r1 = 2*r1; // update r1 = rem(2p/abs(nc)) - if (r1 >= anc) { // must be unsigned comparison - q1 = q1 + 1; - r1 = r1 - anc; - } - q2 = 2*q2; // update q2 = 2p/abs(d) - r2 = 2*r2; // update r2 = rem(2p/abs(d)) - if (r2 >= ad) { // must be unsigned comparison - q2 = q2 + 1; - r2 = r2 - ad; - } - delta = ad - r2; - } while (q1 < delta || (q1 == delta && r1 == 0)); - - mag.m = q2 + 1; - if (d < 0) mag.m = -mag.m; // resulting magic number - mag.s = p - 64; // resulting shift - return mag; -} - -/// magicu - calculate the magic numbers required to codegen an integer udiv as -/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. -static struct mu magicu(uint64_t d) -{ - int64_t p; - uint64_t nc, delta, q1, r1, q2, r2; - struct mu magu; - magu.a = 0; // initialize "add" indicator - nc = - 1 - (-d)%d; - p = 63; // initialize p - q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc - r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc) - q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d - r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d) - do { - p = p + 1; - if (r1 >= nc - r1 ) { - q1 = 2*q1 + 1; // update q1 - r1 = 2*r1 - nc; // update r1 - } - else { - q1 = 2*q1; // update q1 - r1 = 2*r1; // update r1 - } - if (r2 + 1 >= d - r2) { - if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1; - q2 = 2*q2 + 1; // update q2 - r2 = 2*r2 + 1 - d; // update r2 - } - else { - if (q2 >= 0x8000000000000000ull) magu.a = 1; - q2 = 2*q2; // update q2 - r2 = 2*r2 + 1; // update r2 - } - delta = d - 1 - r2; - } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0))); - magu.m = q2 + 1; // resulting magic number - magu.s = p - 64; // resulting shift - return magu; -} - -/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, -/// return a DAG expression to select that will generate the same value by -/// multiplying by a magic number. See: -/// -static SDOperand BuildSDIVSequence(SDOperand N, SelectionDAG* ISelDAG) { - int64_t d = (int64_t)cast(N.getOperand(1))->getSignExtended(); - ms magics = magic(d); - // Multiply the numerator (operand 0) by the magic value - SDOperand Q = ISelDAG->getNode(ISD::MULHS, MVT::i64, N.getOperand(0), - ISelDAG->getConstant(magics.m, MVT::i64)); - // If d > 0 and m < 0, add the numerator - if (d > 0 && magics.m < 0) - Q = ISelDAG->getNode(ISD::ADD, MVT::i64, Q, N.getOperand(0)); - // If d < 0 and m > 0, subtract the numerator. - if (d < 0 && magics.m > 0) - Q = ISelDAG->getNode(ISD::SUB, MVT::i64, Q, N.getOperand(0)); - // Shift right algebraic if shift value is nonzero - if (magics.s > 0) - Q = ISelDAG->getNode(ISD::SRA, MVT::i64, Q, - ISelDAG->getConstant(magics.s, MVT::i64)); - // Extract the sign bit and add it to the quotient - SDOperand T = - ISelDAG->getNode(ISD::SRL, MVT::i64, Q, ISelDAG->getConstant(63, MVT::i64)); - return ISelDAG->getNode(ISD::ADD, MVT::i64, Q, T); -} - -/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, -/// return a DAG expression to select that will generate the same value by -/// multiplying by a magic number. See: -/// -static SDOperand BuildUDIVSequence(SDOperand N, SelectionDAG* ISelDAG) { - unsigned d = - (unsigned)cast(N.getOperand(1))->getSignExtended(); - mu magics = magicu(d); - // Multiply the numerator (operand 0) by the magic value - SDOperand Q = ISelDAG->getNode(ISD::MULHU, MVT::i64, N.getOperand(0), - ISelDAG->getConstant(magics.m, MVT::i64)); - if (magics.a == 0) { - Q = ISelDAG->getNode(ISD::SRL, MVT::i64, Q, - ISelDAG->getConstant(magics.s, MVT::i64)); - } else { - SDOperand NPQ = ISelDAG->getNode(ISD::SUB, MVT::i64, N.getOperand(0), Q); - NPQ = ISelDAG->getNode(ISD::SRL, MVT::i64, NPQ, - ISelDAG->getConstant(1, MVT::i64)); - NPQ = ISelDAG->getNode(ISD::ADD, MVT::i64, NPQ, Q); - Q = ISelDAG->getNode(ISD::SRL, MVT::i64, NPQ, - ISelDAG->getConstant(magics.s-1, MVT::i64)); - } - return Q; -} /// AddLiveIn - This helper function adds the specified physical register to the /// MachineFunction as a live in value. It also creates a corresponding virtual @@ -593,8 +448,8 @@ MVT::ValueType VT = Op.Val->getValueType(0); unsigned Opc = Op.Val->getOpcode() == ISD::UREM ? ISD::UDIV : ISD::SDIV; SDOperand Tmp1 = Op.Val->getOpcode() == ISD::UREM ? - BuildUDIVSequence(Op, &DAG) : - BuildSDIVSequence(Op, &DAG); + BuildUDIV(Op.Val, DAG, NULL) : + BuildSDIV(Op.Val, DAG, NULL); Tmp1 = DAG.getNode(ISD::MUL, VT, Tmp1, Op.getOperand(1)); Tmp1 = DAG.getNode(ISD::SUB, VT, Op.getOperand(0), Tmp1); return Tmp1; @@ -604,7 +459,8 @@ case ISD::UDIV: if (MVT::isInteger(Op.getValueType())) { if (Op.getOperand(1).getOpcode() == ISD::Constant) - return Op.getOpcode() == ISD::SDIV ? BuildSDIVSequence(Op, &DAG) : BuildUDIVSequence(Op, &DAG); + return Op.getOpcode() == ISD::SDIV ? BuildSDIV(Op.Val, DAG, NULL) + : BuildUDIV(Op.Val, DAG, NULL); const char* opstr = 0; switch(Op.getOpcode()) { case ISD::UREM: opstr = "__remqu"; break; From alenhar2 at cs.uiuc.edu Tue May 16 12:42:31 2006 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Tue, 16 May 2006 12:42:31 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetLowering.h Message-ID: <200605161742.MAA17627@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/Target: TargetLowering.h updated: 1.71 -> 1.72 --- Log message: Move this code to a common place --- Diffs of the changes: (+10 -0) TargetLowering.h | 10 ++++++++++ 1 files changed, 10 insertions(+) Index: llvm/include/llvm/Target/TargetLowering.h diff -u llvm/include/llvm/Target/TargetLowering.h:1.71 llvm/include/llvm/Target/TargetLowering.h:1.72 --- llvm/include/llvm/Target/TargetLowering.h:1.71 Sat May 6 04:26:22 2006 +++ llvm/include/llvm/Target/TargetLowering.h Tue May 16 12:42:15 2006 @@ -25,6 +25,7 @@ #include "llvm/Type.h" #include "llvm/CodeGen/SelectionDAGNodes.h" #include +#include namespace llvm { class Value; @@ -649,6 +650,15 @@ return LegalAddressScales.end(); } + //===--------------------------------------------------------------------===// + // Div utility functions + // + SDOperand BuildSDIV(SDNode *N, SelectionDAG &DAG, + std::list* Created) const; + SDOperand BuildUDIV(SDNode *N, SelectionDAG &DAG, + std::list* Created) const; + + protected: /// addLegalAddressScale - Add a integer (> 1) value which can be used as /// scale in the target addressing mode. Note: the ordering matters so the From alenhar2 at cs.uiuc.edu Tue May 16 12:42:31 2006 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Tue, 16 May 2006 12:42:31 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp Message-ID: <200605161742.MAA17629@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target: TargetLowering.cpp updated: 1.62 -> 1.63 --- Log message: Move this code to a common place --- Diffs of the changes: (+265 -0) TargetLowering.cpp | 265 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 265 insertions(+) Index: llvm/lib/Target/TargetLowering.cpp diff -u llvm/lib/Target/TargetLowering.cpp:1.62 llvm/lib/Target/TargetLowering.cpp:1.63 --- llvm/lib/Target/TargetLowering.cpp:1.62 Fri May 12 01:33:48 2006 +++ llvm/lib/Target/TargetLowering.cpp Tue May 16 12:42:15 2006 @@ -1330,3 +1330,268 @@ bool TargetLowering::isLegalAddressImmediate(GlobalValue *GV) const { return false; } + + +// Magic for divide replacement + +struct ms { + int64_t m; // magic number + int64_t s; // shift amount +}; + +struct mu { + uint64_t m; // magic number + int64_t a; // add indicator + int64_t s; // shift amount +}; + +/// magic - calculate the magic numbers required to codegen an integer sdiv as +/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, +/// or -1. +static ms magic32(int32_t d) { + int32_t p; + uint32_t ad, anc, delta, q1, r1, q2, r2, t; + const uint32_t two31 = 0x80000000U; + struct ms mag; + + ad = abs(d); + t = two31 + ((uint32_t)d >> 31); + anc = t - 1 - t%ad; // absolute value of nc + p = 31; // initialize p + q1 = two31/anc; // initialize q1 = 2p/abs(nc) + r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc)) + q2 = two31/ad; // initialize q2 = 2p/abs(d) + r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d)) + do { + p = p + 1; + q1 = 2*q1; // update q1 = 2p/abs(nc) + r1 = 2*r1; // update r1 = rem(2p/abs(nc)) + if (r1 >= anc) { // must be unsigned comparison + q1 = q1 + 1; + r1 = r1 - anc; + } + q2 = 2*q2; // update q2 = 2p/abs(d) + r2 = 2*r2; // update r2 = rem(2p/abs(d)) + if (r2 >= ad) { // must be unsigned comparison + q2 = q2 + 1; + r2 = r2 - ad; + } + delta = ad - r2; + } while (q1 < delta || (q1 == delta && r1 == 0)); + + mag.m = (int32_t)(q2 + 1); // make sure to sign extend + if (d < 0) mag.m = -mag.m; // resulting magic number + mag.s = p - 32; // resulting shift + return mag; +} + +/// magicu - calculate the magic numbers required to codegen an integer udiv as +/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. +static mu magicu32(uint32_t d) { + int32_t p; + uint32_t nc, delta, q1, r1, q2, r2; + struct mu magu; + magu.a = 0; // initialize "add" indicator + nc = - 1 - (-d)%d; + p = 31; // initialize p + q1 = 0x80000000/nc; // initialize q1 = 2p/nc + r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc) + q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d + r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d) + do { + p = p + 1; + if (r1 >= nc - r1 ) { + q1 = 2*q1 + 1; // update q1 + r1 = 2*r1 - nc; // update r1 + } + else { + q1 = 2*q1; // update q1 + r1 = 2*r1; // update r1 + } + if (r2 + 1 >= d - r2) { + if (q2 >= 0x7FFFFFFF) magu.a = 1; + q2 = 2*q2 + 1; // update q2 + r2 = 2*r2 + 1 - d; // update r2 + } + else { + if (q2 >= 0x80000000) magu.a = 1; + q2 = 2*q2; // update q2 + r2 = 2*r2 + 1; // update r2 + } + delta = d - 1 - r2; + } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0))); + magu.m = q2 + 1; // resulting magic number + magu.s = p - 32; // resulting shift + return magu; +} + +/// magic - calculate the magic numbers required to codegen an integer sdiv as +/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, +/// or -1. +static ms magic64(int64_t d) { + int64_t p; + uint64_t ad, anc, delta, q1, r1, q2, r2, t; + const uint64_t two63 = 9223372036854775808ULL; // 2^63 + struct ms mag; + + ad = d >= 0 ? d : -d; + t = two63 + ((uint64_t)d >> 63); + anc = t - 1 - t%ad; // absolute value of nc + p = 63; // initialize p + q1 = two63/anc; // initialize q1 = 2p/abs(nc) + r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc)) + q2 = two63/ad; // initialize q2 = 2p/abs(d) + r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d)) + do { + p = p + 1; + q1 = 2*q1; // update q1 = 2p/abs(nc) + r1 = 2*r1; // update r1 = rem(2p/abs(nc)) + if (r1 >= anc) { // must be unsigned comparison + q1 = q1 + 1; + r1 = r1 - anc; + } + q2 = 2*q2; // update q2 = 2p/abs(d) + r2 = 2*r2; // update r2 = rem(2p/abs(d)) + if (r2 >= ad) { // must be unsigned comparison + q2 = q2 + 1; + r2 = r2 - ad; + } + delta = ad - r2; + } while (q1 < delta || (q1 == delta && r1 == 0)); + + mag.m = q2 + 1; + if (d < 0) mag.m = -mag.m; // resulting magic number + mag.s = p - 64; // resulting shift + return mag; +} + +/// magicu - calculate the magic numbers required to codegen an integer udiv as +/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. +static mu magicu64(uint64_t d) +{ + int64_t p; + uint64_t nc, delta, q1, r1, q2, r2; + struct mu magu; + magu.a = 0; // initialize "add" indicator + nc = - 1 - (-d)%d; + p = 63; // initialize p + q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc + r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc) + q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d + r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d) + do { + p = p + 1; + if (r1 >= nc - r1 ) { + q1 = 2*q1 + 1; // update q1 + r1 = 2*r1 - nc; // update r1 + } + else { + q1 = 2*q1; // update q1 + r1 = 2*r1; // update r1 + } + if (r2 + 1 >= d - r2) { + if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1; + q2 = 2*q2 + 1; // update q2 + r2 = 2*r2 + 1 - d; // update r2 + } + else { + if (q2 >= 0x8000000000000000ull) magu.a = 1; + q2 = 2*q2; // update q2 + r2 = 2*r2 + 1; // update r2 + } + delta = d - 1 - r2; + } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0))); + magu.m = q2 + 1; // resulting magic number + magu.s = p - 64; // resulting shift + return magu; +} + +/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, +/// return a DAG expression to select that will generate the same value by +/// multiplying by a magic number. See: +/// +SDOperand TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, + std::list* Created) const { + MVT::ValueType VT = N->getValueType(0); + + // Check to see if we can do this. + if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) + return SDOperand(); // BuildSDIV only operates on i32 or i64 + if (!isOperationLegal(ISD::MULHS, VT)) + return SDOperand(); // Make sure the target supports MULHS. + + int64_t d = cast(N->getOperand(1))->getSignExtended(); + ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d); + + // Multiply the numerator (operand 0) by the magic value + SDOperand Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0), + DAG.getConstant(magics.m, VT)); + // If d > 0 and m < 0, add the numerator + if (d > 0 && magics.m < 0) { + Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0)); + if (Created) + Created->push_back(Q.Val); + } + // If d < 0 and m > 0, subtract the numerator. + if (d < 0 && magics.m > 0) { + Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0)); + if (Created) + Created->push_back(Q.Val); + } + // Shift right algebraic if shift value is nonzero + if (magics.s > 0) { + Q = DAG.getNode(ISD::SRA, VT, Q, + DAG.getConstant(magics.s, getShiftAmountTy())); + if (Created) + Created->push_back(Q.Val); + } + // Extract the sign bit and add it to the quotient + SDOperand T = + DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(MVT::getSizeInBits(VT)-1, + getShiftAmountTy())); + if (Created) + Created->push_back(T.Val); + return DAG.getNode(ISD::ADD, VT, Q, T); +} + +/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, +/// return a DAG expression to select that will generate the same value by +/// multiplying by a magic number. See: +/// +SDOperand TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, + std::list* Created) const { + MVT::ValueType VT = N->getValueType(0); + + // Check to see if we can do this. + if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) + return SDOperand(); // BuildUDIV only operates on i32 or i64 + if (!isOperationLegal(ISD::MULHU, VT)) + return SDOperand(); // Make sure the target supports MULHU. + + uint64_t d = cast(N->getOperand(1))->getValue(); + mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d); + + // Multiply the numerator (operand 0) by the magic value + SDOperand Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0), + DAG.getConstant(magics.m, VT)); + if (Created) + Created->push_back(Q.Val); + + if (magics.a == 0) { + return DAG.getNode(ISD::SRL, VT, Q, + DAG.getConstant(magics.s, getShiftAmountTy())); + } else { + SDOperand NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q); + if (Created) + Created->push_back(NPQ.Val); + NPQ = DAG.getNode(ISD::SRL, VT, NPQ, + DAG.getConstant(1, getShiftAmountTy())); + if (Created) + Created->push_back(NPQ.Val); + NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q); + if (Created) + Created->push_back(NPQ.Val); + return DAG.getNode(ISD::SRL, VT, NPQ, + DAG.getConstant(magics.s-1, getShiftAmountTy())); + } +} From alenhar2 at cs.uiuc.edu Tue May 16 12:45:35 2006 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Tue, 16 May 2006 12:45:35 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp Message-ID: <200605161745.MAA17745@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target: TargetLowering.cpp updated: 1.63 -> 1.64 --- Log message: this should be 128 I think --- Diffs of the changes: (+1 -1) TargetLowering.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/TargetLowering.cpp diff -u llvm/lib/Target/TargetLowering.cpp:1.63 llvm/lib/Target/TargetLowering.cpp:1.64 --- llvm/lib/Target/TargetLowering.cpp:1.63 Tue May 16 12:42:15 2006 +++ llvm/lib/Target/TargetLowering.cpp Tue May 16 12:45:23 2006 @@ -1500,7 +1500,7 @@ r2 = 2*r2 + 1; // update r2 } delta = d - 1 - r2; - } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0))); + } while (p < 128 && (q1 < delta || (q1 == delta && r1 == 0))); magu.m = q2 + 1; // resulting magic number magu.s = p - 64; // resulting shift return magu; From lattner at cs.uiuc.edu Tue May 16 13:19:02 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 16 May 2006 13:19:02 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCISelLowering.h Message-ID: <200605161819.NAA19182@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.171 -> 1.172 PPCISelLowering.h updated: 1.47 -> 1.48 --- Log message: Switch the PPC backend over to using FORMAL_ARGUMENTS for formal argument handling. This makes the lower argument code significantly simpler (we only need to handle legal argument types). Incidentally, this also implements support for vector argument registers, so long as they are not on the stack. --- Diffs of the changes: (+157 -172) PPCISelLowering.cpp | 325 +++++++++++++++++++++++++--------------------------- PPCISelLowering.h | 4 2 files changed, 157 insertions(+), 172 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.171 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.172 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.171 Mon May 15 23:20:24 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Tue May 16 13:18:50 2006 @@ -727,6 +727,161 @@ Op.getOperand(1), Op.getOperand(2)); } +static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, + int &VarArgsFrameIndex) { + // TODO: add description of PPC stack frame format, or at least some docs. + // + MachineFunction &MF = DAG.getMachineFunction(); + MachineFrameInfo *MFI = MF.getFrameInfo(); + SSARegMap *RegMap = MF.getSSARegMap(); + std::vector ArgValues; + SDOperand Root = Op.getOperand(0); + + unsigned ArgOffset = 24; + unsigned GPR_remaining = 8; + unsigned FPR_remaining = 13; + unsigned VR_remaining = 12; + unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; + static const unsigned GPR[] = { + PPC::R3, PPC::R4, PPC::R5, PPC::R6, + PPC::R7, PPC::R8, PPC::R9, PPC::R10, + }; + static const unsigned FPR[] = { + PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, + PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13 + }; + static const unsigned VR[] = { + PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, + PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 + }; + + // Add DAG nodes to load the arguments or copy them out of registers. On + // entry to a function on PPC, the arguments start at offset 24, although the + // first ones are often in registers. + for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) { + SDOperand ArgVal; + bool needsLoad = false; + bool ArgLive = !Op.Val->hasNUsesOfValue(0, ArgNo); + MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType(); + unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8; + + switch (ObjectVT) { + default: assert(0 && "Unhandled argument type!"); + case MVT::i32: + if (!ArgLive) break; + if (GPR_remaining > 0) { + unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); + MF.addLiveIn(GPR[GPR_idx], VReg); + ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32); + } else { + needsLoad = true; + } + break; + case MVT::f32: + case MVT::f64: + if (!ArgLive) { + if (FPR_remaining > 0) { + --FPR_remaining; + ++FPR_idx; + } + break; + } + if (FPR_remaining > 0) { + unsigned VReg; + if (ObjectVT == MVT::f32) + VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass); + else + VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass); + MF.addLiveIn(FPR[FPR_idx], VReg); + ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT); + --FPR_remaining; + ++FPR_idx; + } else { + needsLoad = true; + } + break; + case MVT::v4f32: + case MVT::v4i32: + case MVT::v8i16: + case MVT::v16i8: + if (!ArgLive) { + if (VR_remaining > 0) { + --VR_remaining; + ++VR_idx; + } + break; + } + if (VR_remaining > 0) { + unsigned VReg = RegMap->createVirtualRegister(&PPC::VRRCRegClass); + MF.addLiveIn(VR[VR_idx], VReg); + ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT); + --VR_remaining; + ++VR_idx; + } else { + // This should be simple, but requires getting 16-byte aligned stack + // values. + assert(0 && "Loading VR argument not implemented yet!"); + needsLoad = true; + } + break; + } + + // We need to load the argument to a virtual register if we determined above + // that we ran out of physical registers of the appropriate type + if (needsLoad) { + int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); + SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); + ArgVal = DAG.getLoad(ObjectVT, Root, FIN, + DAG.getSrcValue(NULL)); + } + + // Every 4 bytes of argument space consumes one of the GPRs available for + // argument passing. + if (GPR_remaining > 0) { + unsigned delta = (GPR_remaining > 1 && ObjSize == 8) ? 2 : 1; + GPR_remaining -= delta; + GPR_idx += delta; + } + ArgOffset += ObjSize; + + if (ArgVal.Val == 0) + ArgVal = DAG.getNode(ISD::UNDEF, ObjectVT); + ArgValues.push_back(ArgVal); + } + + // If the function takes variable number of arguments, make a frame index for + // the start of the first vararg value... for expansion of llvm.va_start. + bool isVarArg = cast(Op.getOperand(2))->getValue() != 0; + if (isVarArg) { + VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset); + SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32); + // If this function is vararg, store any remaining integer argument regs + // to their spots on the stack so that they may be loaded by deferencing the + // result of va_next. + std::vector MemOps; + for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) { + unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); + MF.addLiveIn(GPR[GPR_idx], VReg); + SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i32); + SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1), + Val, FIN, DAG.getSrcValue(NULL)); + MemOps.push_back(Store); + // Increment the address by four for the next argument to store + SDOperand PtrOff = DAG.getConstant(4, MVT::i32); + FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, PtrOff); + } + if (!MemOps.empty()) + Root = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps); + } + + ArgValues.push_back(Root); + + // Return the new list of results. + std::vector RetVT(Op.Val->value_begin(), + Op.Val->value_end()); + return DAG.getNode(ISD::MERGE_VALUES, RetVT, ArgValues); +} + static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) { SDOperand Copy; switch(Op.getNumOperands()) { @@ -1690,6 +1845,8 @@ case ISD::JumpTable: return LowerJumpTable(Op, DAG); case ISD::SETCC: return LowerSETCC(Op, DAG); case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex); + case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG, + VarArgsFrameIndex); case ISD::RET: return LowerRET(Op, DAG); case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); @@ -1715,174 +1872,6 @@ // Other Lowering Code //===----------------------------------------------------------------------===// -std::vector -PPCTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { - // - // add beautiful description of PPC stack frame format, or at least some docs - // - MachineFunction &MF = DAG.getMachineFunction(); - MachineFrameInfo *MFI = MF.getFrameInfo(); - SSARegMap *RegMap = MF.getSSARegMap(); - std::vector ArgValues; - - unsigned ArgOffset = 24; - unsigned GPR_remaining = 8; - unsigned FPR_remaining = 13; - unsigned GPR_idx = 0, FPR_idx = 0; - static const unsigned GPR[] = { - PPC::R3, PPC::R4, PPC::R5, PPC::R6, - PPC::R7, PPC::R8, PPC::R9, PPC::R10, - }; - static const unsigned FPR[] = { - PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, - PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13 - }; - - // Add DAG nodes to load the arguments... On entry to a function on PPC, - // the arguments start at offset 24, although they are likely to be passed - // in registers. - for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { - SDOperand newroot, argt; - unsigned ObjSize; - bool needsLoad = false; - bool ArgLive = !I->use_empty(); - MVT::ValueType ObjectVT = getValueType(I->getType()); - - switch (ObjectVT) { - default: assert(0 && "Unhandled argument type!"); - case MVT::i1: - case MVT::i8: - case MVT::i16: - case MVT::i32: - ObjSize = 4; - if (!ArgLive) break; - if (GPR_remaining > 0) { - unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); - MF.addLiveIn(GPR[GPR_idx], VReg); - argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); - if (ObjectVT != MVT::i32) { - unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext - : ISD::AssertZext; - argt = DAG.getNode(AssertOp, MVT::i32, argt, - DAG.getValueType(ObjectVT)); - argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, argt); - } - } else { - needsLoad = true; - } - break; - case MVT::i64: - ObjSize = 8; - if (!ArgLive) break; - if (GPR_remaining > 0) { - SDOperand argHi, argLo; - unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); - MF.addLiveIn(GPR[GPR_idx], VReg); - argHi = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); - // If we have two or more remaining argument registers, then both halves - // of the i64 can be sourced from there. Otherwise, the lower half will - // have to come off the stack. This can happen when an i64 is preceded - // by 28 bytes of arguments. - if (GPR_remaining > 1) { - unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); - MF.addLiveIn(GPR[GPR_idx+1], VReg); - argLo = DAG.getCopyFromReg(argHi, VReg, MVT::i32); - } else { - int FI = MFI->CreateFixedObject(4, ArgOffset+4); - SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); - argLo = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN, - DAG.getSrcValue(NULL)); - } - // Build the outgoing arg thingy - argt = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, argLo, argHi); - newroot = argLo; - } else { - needsLoad = true; - } - break; - case MVT::f32: - case MVT::f64: - ObjSize = (ObjectVT == MVT::f64) ? 8 : 4; - if (!ArgLive) { - if (FPR_remaining > 0) { - --FPR_remaining; - ++FPR_idx; - } - break; - } - if (FPR_remaining > 0) { - unsigned VReg; - if (ObjectVT == MVT::f32) - VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass); - else - VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass); - MF.addLiveIn(FPR[FPR_idx], VReg); - argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), VReg, ObjectVT); - --FPR_remaining; - ++FPR_idx; - } else { - needsLoad = true; - } - break; - } - - // We need to load the argument to a virtual register if we determined above - // that we ran out of physical registers of the appropriate type - if (needsLoad) { - unsigned SubregOffset = 0; - if (ObjectVT == MVT::i8 || ObjectVT == MVT::i1) SubregOffset = 3; - if (ObjectVT == MVT::i16) SubregOffset = 2; - int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); - SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); - FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, - DAG.getConstant(SubregOffset, MVT::i32)); - argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN, - DAG.getSrcValue(NULL)); - } - - // Every 4 bytes of argument space consumes one of the GPRs available for - // argument passing. - if (GPR_remaining > 0) { - unsigned delta = (GPR_remaining > 1 && ObjSize == 8) ? 2 : 1; - GPR_remaining -= delta; - GPR_idx += delta; - } - ArgOffset += ObjSize; - if (newroot.Val) - DAG.setRoot(newroot.getValue(1)); - - ArgValues.push_back(argt); - } - - // If the function takes variable number of arguments, make a frame index for - // the start of the first vararg value... for expansion of llvm.va_start. - if (F.isVarArg()) { - VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset); - SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32); - // If this function is vararg, store any remaining integer argument regs - // to their spots on the stack so that they may be loaded by deferencing the - // result of va_next. - std::vector MemOps; - for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) { - unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); - MF.addLiveIn(GPR[GPR_idx], VReg); - SDOperand Val = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); - SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1), - Val, FIN, DAG.getSrcValue(NULL)); - MemOps.push_back(Store); - // Increment the address by four for the next argument to store - SDOperand PtrOff = DAG.getConstant(4, getPointerTy()); - FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, PtrOff); - } - if (!MemOps.empty()) { - MemOps.push_back(DAG.getRoot()); - DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps)); - } - } - - return ArgValues; -} - std::pair PPCTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, Index: llvm/lib/Target/PowerPC/PPCISelLowering.h diff -u llvm/lib/Target/PowerPC/PPCISelLowering.h:1.47 llvm/lib/Target/PowerPC/PPCISelLowering.h:1.48 --- llvm/lib/Target/PowerPC/PPCISelLowering.h:1.47 Tue Apr 18 12:59:36 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.h Tue May 16 13:18:50 2006 @@ -166,10 +166,6 @@ uint64_t &KnownZero, uint64_t &KnownOne, unsigned Depth = 0) const; - /// LowerArguments - This hook must be implemented to indicate how we should - /// lower the arguments for the specified function, into the specified DAG. - virtual std::vector - LowerArguments(Function &F, SelectionDAG &DAG); /// LowerCallTo - This hook lowers an abstract call to a function into an /// actual call. From lattner at cs.uiuc.edu Tue May 16 13:24:07 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 16 May 2006 13:24:07 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/vec_vrsave.ll Message-ID: <200605161824.NAA19427@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/PowerPC: vec_vrsave.ll updated: 1.1 -> 1.2 --- Log message: Another testcase that shouldn't need vrsave twiddling --- Diffs of the changes: (+7 -1) vec_vrsave.ll | 8 +++++++- 1 files changed, 7 insertions(+), 1 deletion(-) Index: llvm/test/Regression/CodeGen/PowerPC/vec_vrsave.ll diff -u llvm/test/Regression/CodeGen/PowerPC/vec_vrsave.ll:1.1 llvm/test/Regression/CodeGen/PowerPC/vec_vrsave.ll:1.2 --- llvm/test/Regression/CodeGen/PowerPC/vec_vrsave.ll:1.1 Mon Apr 17 16:48:03 2006 +++ llvm/test/Regression/CodeGen/PowerPC/vec_vrsave.ll Tue May 16 13:23:55 2006 @@ -1,7 +1,13 @@ ; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vrlw && -; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | not grep spr +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | not grep spr && +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | not grep vrsave <4 x int> %test_rol() { ret <4 x int> < int -11534337, int -11534337, int -11534337, int -11534337 > } +<4 x int> %test_arg(<4 x int> %A, <4 x int> %B) { + %C = add <4 x int> %A, %B + ret <4 x int> %C +} + From lattner at cs.uiuc.edu Tue May 16 13:52:05 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 16 May 2006 13:52:05 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp Message-ID: <200605161852.NAA22526@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.172 -> 1.173 --- Log message: Vector args passed in registers don't reserve stack space. --- Diffs of the changes: (+26 -11) PPCISelLowering.cpp | 37 ++++++++++++++++++++++++++----------- 1 files changed, 26 insertions(+), 11 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.172 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.173 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.172 Tue May 16 13:18:50 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Tue May 16 13:51:52 2006 @@ -765,20 +765,43 @@ MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType(); unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8; + unsigned CurArgOffset = ArgOffset; + switch (ObjectVT) { default: assert(0 && "Unhandled argument type!"); case MVT::i32: - if (!ArgLive) break; + // All int arguments reserve stack space. + ArgOffset += 4; + + if (!ArgLive) { + if (GPR_remaining > 0) { + --GPR_remaining; + ++GPR_idx; + } + break; + } if (GPR_remaining > 0) { unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); MF.addLiveIn(GPR[GPR_idx], VReg); ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32); + --GPR_remaining; + ++GPR_idx; } else { needsLoad = true; } break; case MVT::f32: case MVT::f64: + // All FP arguments reserve stack space. + ArgOffset += ObjSize; + + // Every 4 bytes of argument space consumes one of the GPRs available for + // argument passing. + if (GPR_remaining > 0) { + unsigned delta = (GPR_remaining > 1 && ObjSize == 8) ? 2 : 1; + GPR_remaining -= delta; + GPR_idx += delta; + } if (!ArgLive) { if (FPR_remaining > 0) { --FPR_remaining; @@ -804,6 +827,7 @@ case MVT::v4i32: case MVT::v8i16: case MVT::v16i8: + // Note that vector arguments in registers don't reserve stack space. if (!ArgLive) { if (VR_remaining > 0) { --VR_remaining; @@ -829,21 +853,12 @@ // We need to load the argument to a virtual register if we determined above // that we ran out of physical registers of the appropriate type if (needsLoad) { - int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); + int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset); SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); ArgVal = DAG.getLoad(ObjectVT, Root, FIN, DAG.getSrcValue(NULL)); } - // Every 4 bytes of argument space consumes one of the GPRs available for - // argument passing. - if (GPR_remaining > 0) { - unsigned delta = (GPR_remaining > 1 && ObjSize == 8) ? 2 : 1; - GPR_remaining -= delta; - GPR_idx += delta; - } - ArgOffset += ObjSize; - if (ArgVal.Val == 0) ArgVal = DAG.getNode(ISD::UNDEF, ObjectVT); ArgValues.push_back(ArgVal); From lattner at cs.uiuc.edu Tue May 16 13:54:44 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 16 May 2006 13:54:44 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp Message-ID: <200605161854.NAA22650@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.173 -> 1.174 --- Log message: Simplify the dead argument handling code. --- Diffs of the changes: (+11 -28) PPCISelLowering.cpp | 39 +++++++++++---------------------------- 1 files changed, 11 insertions(+), 28 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.173 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.174 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.173 Tue May 16 13:51:52 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Tue May 16 13:54:32 2006 @@ -761,7 +761,6 @@ for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) { SDOperand ArgVal; bool needsLoad = false; - bool ArgLive = !Op.Val->hasNUsesOfValue(0, ArgNo); MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType(); unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8; @@ -773,13 +772,6 @@ // All int arguments reserve stack space. ArgOffset += 4; - if (!ArgLive) { - if (GPR_remaining > 0) { - --GPR_remaining; - ++GPR_idx; - } - break; - } if (GPR_remaining > 0) { unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); MF.addLiveIn(GPR[GPR_idx], VReg); @@ -802,13 +794,6 @@ GPR_remaining -= delta; GPR_idx += delta; } - if (!ArgLive) { - if (FPR_remaining > 0) { - --FPR_remaining; - ++FPR_idx; - } - break; - } if (FPR_remaining > 0) { unsigned VReg; if (ObjectVT == MVT::f32) @@ -828,13 +813,6 @@ case MVT::v8i16: case MVT::v16i8: // Note that vector arguments in registers don't reserve stack space. - if (!ArgLive) { - if (VR_remaining > 0) { - --VR_remaining; - ++VR_idx; - } - break; - } if (VR_remaining > 0) { unsigned VReg = RegMap->createVirtualRegister(&PPC::VRRCRegClass); MF.addLiveIn(VR[VR_idx], VReg); @@ -853,14 +831,19 @@ // We need to load the argument to a virtual register if we determined above // that we ran out of physical registers of the appropriate type if (needsLoad) { - int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset); - SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); - ArgVal = DAG.getLoad(ObjectVT, Root, FIN, - DAG.getSrcValue(NULL)); + // If the argument is actually used, emit a load from the right stack + // slot. + if (!Op.Val->hasNUsesOfValue(0, ArgNo)) { + int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset); + SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); + ArgVal = DAG.getLoad(ObjectVT, Root, FIN, + DAG.getSrcValue(NULL)); + } else { + // Don't emit a dead load. + ArgVal = DAG.getNode(ISD::UNDEF, ObjectVT); + } } - if (ArgVal.Val == 0) - ArgVal = DAG.getNode(ISD::UNDEF, ObjectVT); ArgValues.push_back(ArgVal); } From lattner at cs.uiuc.edu Tue May 16 13:58:27 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 16 May 2006 13:58:27 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp Message-ID: <200605161858.NAA22797@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.174 -> 1.175 --- Log message: Simplify the argument counting logic by only incrementing the index. --- Diffs of the changes: (+11 -14) PPCISelLowering.cpp | 25 +++++++++++-------------- 1 files changed, 11 insertions(+), 14 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.174 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.175 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.174 Tue May 16 13:54:32 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Tue May 16 13:58:15 2006 @@ -738,9 +738,9 @@ SDOperand Root = Op.getOperand(0); unsigned ArgOffset = 24; - unsigned GPR_remaining = 8; - unsigned FPR_remaining = 13; - unsigned VR_remaining = 12; + const unsigned Num_GPR_Regs = 8; + const unsigned Num_FPR_Regs = 13; + const unsigned Num_VR_Regs = 12; unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; static const unsigned GPR[] = { PPC::R3, PPC::R4, PPC::R5, PPC::R6, @@ -772,11 +772,10 @@ // All int arguments reserve stack space. ArgOffset += 4; - if (GPR_remaining > 0) { + if (GPR_idx != Num_GPR_Regs) { unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); MF.addLiveIn(GPR[GPR_idx], VReg); ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32); - --GPR_remaining; ++GPR_idx; } else { needsLoad = true; @@ -789,12 +788,12 @@ // Every 4 bytes of argument space consumes one of the GPRs available for // argument passing. - if (GPR_remaining > 0) { - unsigned delta = (GPR_remaining > 1 && ObjSize == 8) ? 2 : 1; - GPR_remaining -= delta; - GPR_idx += delta; + if (GPR_idx != Num_GPR_Regs) { + ++GPR_idx; + if (ObjSize == 8 && GPR_idx != Num_GPR_Regs) + ++GPR_idx; } - if (FPR_remaining > 0) { + if (FPR_idx != Num_FPR_Regs) { unsigned VReg; if (ObjectVT == MVT::f32) VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass); @@ -802,7 +801,6 @@ VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass); MF.addLiveIn(FPR[FPR_idx], VReg); ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT); - --FPR_remaining; ++FPR_idx; } else { needsLoad = true; @@ -813,11 +811,10 @@ case MVT::v8i16: case MVT::v16i8: // Note that vector arguments in registers don't reserve stack space. - if (VR_remaining > 0) { + if (VR_idx != Num_VR_Regs) { unsigned VReg = RegMap->createVirtualRegister(&PPC::VRRCRegClass); MF.addLiveIn(VR[VR_idx], VReg); ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT); - --VR_remaining; ++VR_idx; } else { // This should be simple, but requires getting 16-byte aligned stack @@ -857,7 +854,7 @@ // to their spots on the stack so that they may be loaded by deferencing the // result of va_next. std::vector MemOps; - for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) { + for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) { unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); MF.addLiveIn(GPR[GPR_idx], VReg); SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i32); From lattner at cs.uiuc.edu Tue May 16 17:52:24 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 16 May 2006 17:52:24 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetLowering.h Message-ID: <200605162252.RAA32671@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/Target: TargetLowering.h updated: 1.72 -> 1.73 --- Log message: There is now a default impl of this method --- Diffs of the changes: (+1 -1) TargetLowering.h | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/include/llvm/Target/TargetLowering.h diff -u llvm/include/llvm/Target/TargetLowering.h:1.72 llvm/include/llvm/Target/TargetLowering.h:1.73 --- llvm/include/llvm/Target/TargetLowering.h:1.72 Tue May 16 12:42:15 2006 +++ llvm/include/llvm/Target/TargetLowering.h Tue May 16 17:52:11 2006 @@ -558,7 +558,7 @@ virtual std::pair LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, unsigned CallingConv, bool isTailCall, SDOperand Callee, - ArgListTy &Args, SelectionDAG &DAG) = 0; + ArgListTy &Args, SelectionDAG &DAG); /// LowerFrameReturnAddress - This hook lowers a call to llvm.returnaddress or /// llvm.frameaddress (depending on the value of the first argument). The From lattner at cs.uiuc.edu Tue May 16 17:52:40 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 16 May 2006 17:52:40 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGNodes.h Message-ID: <200605162252.RAA32713@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: SelectionDAGNodes.h updated: 1.131 -> 1.132 --- Log message: Add a new CALL node. --- Diffs of the changes: (+7 -0) SelectionDAGNodes.h | 7 +++++++ 1 files changed, 7 insertions(+) Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.131 llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.132 --- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.131 Tue May 16 01:43:59 2006 +++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h Tue May 16 17:52:27 2006 @@ -123,6 +123,13 @@ /// It must be custom legalized. /// FORMAL_ARGUMENTS, + + /// RV1, RV2...RVn, CHAIN = CALL(CHAIN, CC#, ISVARARG, ISTAILCALL, CALLEE, + /// ARG0, ARG1, ... ARGn) + /// This node represents a fully general function call, before the legalizer + /// runs. This has one result value for each argument, plus a chain result. + /// It must be custom legalized. + CALL, // EXTRACT_ELEMENT - This is used to get the first or second (determined by // a Constant, which is required to be operand #1), element of the aggregate From lattner at cs.uiuc.edu Tue May 16 17:53:32 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 16 May 2006 17:53:32 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp Message-ID: <200605162253.RAA32766@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.374 -> 1.375 SelectionDAG.cpp updated: 1.307 -> 1.308 SelectionDAGISel.cpp updated: 1.242 -> 1.243 --- Log message: Add a new ISD::CALL node, make the default impl of TargetLowering::LowerCallTo produce it. --- Diffs of the changes: (+143 -3) LegalizeDAG.cpp | 5 + SelectionDAG.cpp | 1 SelectionDAGISel.cpp | 140 ++++++++++++++++++++++++++++++++++++++++++++++++++- 3 files changed, 143 insertions(+), 3 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.374 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.375 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.374 Tue May 16 00:49:56 2006 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue May 16 17:53:20 2006 @@ -818,11 +818,12 @@ break; case ISD::FORMAL_ARGUMENTS: + case ISD::CALL: // The only option for this is to custom lower it. Result = TLI.LowerOperation(Result.getValue(0), DAG); - assert(Result.Val && "Target didn't custom lower ISD::FORMAL_ARGUMENTS!"); + assert(Result.Val && "Target didn't custom lower this node!"); - // Since FORMAL_ARGUMENTS nodes produce multiple values, make sure to + // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to // remember that we legalized all of them, so it doesn't get relegalized. for (unsigned i = 0, e = Result.Val->getNumValues(); i != e; ++i) { Tmp1 = LegalizeOp(Result.getValue(i)); Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.307 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.308 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.307 Fri May 12 13:04:28 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue May 16 17:53:20 2006 @@ -2841,6 +2841,7 @@ case ISD::INLINEASM: return "inlineasm"; case ISD::HANDLENODE: return "handlenode"; case ISD::FORMAL_ARGUMENTS: return "formal_arguments"; + case ISD::CALL: return "call"; // Unary operators case ISD::FABS: return "fabs"; Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.242 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.243 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.242 Tue May 16 01:45:34 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue May 16 17:53:20 2006 @@ -2344,7 +2344,8 @@ /// TargetLowering::LowerArguments - This is the default LowerArguments /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all -/// targets are migrated to using FORMAL_ARGUMENTS, this hook should be removed. +/// targets are migrated to using FORMAL_ARGUMENTS, this hook should be +/// integrated into SDISel. std::vector TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node. @@ -2477,8 +2478,145 @@ return Ops; } + +/// TargetLowering::LowerCallTo - This is the default LowerCallTo +/// implementation, which just inserts an ISD::CALL node, which is later custom +/// lowered by the target to something concrete. FIXME: When all targets are +/// migrated to using ISD::CALL, this hook should be integrated into SDISel. +std::pair +TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, + unsigned CallingConv, bool isTailCall, + SDOperand Callee, + ArgListTy &Args, SelectionDAG &DAG) { + std::vector Ops; + Ops.push_back(Chain); // Op#0 - Chain + Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC + Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg + Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail + Ops.push_back(Callee); + + // Handle all of the outgoing arguments. + for (unsigned i = 0, e = Args.size(); i != e; ++i) { + MVT::ValueType VT = getValueType(Args[i].second); + SDOperand Op = Args[i].first; + switch (getTypeAction(VT)) { + default: assert(0 && "Unknown type action!"); + case Legal: + Ops.push_back(Op); + break; + case Promote: + if (MVT::isInteger(VT)) { + unsigned ExtOp = Args[i].second->isSigned() ? + ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; + Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op); + } else { + assert(MVT::isFloatingPoint(VT) && "Not int or FP?"); + Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op); + } + Ops.push_back(Op); + break; + case Expand: + if (VT != MVT::Vector) { + // If this is a large integer, it needs to be broken down into small + // integers. Figure out what the source elt type is and how many small + // integers it is. + MVT::ValueType NVT = getTypeToTransformTo(VT); + unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT); + if (NumVals == 2) { + SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, NVT, Op, + DAG.getConstant(0, getPointerTy())); + SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, NVT, Op, + DAG.getConstant(1, getPointerTy())); + if (!isLittleEndian()) + std::swap(Lo, Hi); + + Ops.push_back(Lo); + Ops.push_back(Hi); + } else { + // Value scalarized into many values. Unimp for now. + assert(0 && "Cannot expand i64 -> i16 yet!"); + } + } else { + assert(0 && "Doesn't handle vectors yet!"); + } + break; + } + } + + // Figure out the result value types. + std::vector RetTys; + + if (RetTy != Type::VoidTy) { + MVT::ValueType VT = getValueType(RetTy); + switch (getTypeAction(VT)) { + default: assert(0 && "Unknown type action!"); + case Legal: + RetTys.push_back(VT); + break; + case Promote: + RetTys.push_back(getTypeToTransformTo(VT)); + break; + case Expand: + if (VT != MVT::Vector) { + // If this is a large integer, it needs to be reassembled from small + // integers. Figure out what the source elt type is and how many small + // integers it is. + MVT::ValueType NVT = getTypeToTransformTo(VT); + unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT); + for (unsigned i = 0; i != NumVals; ++i) + RetTys.push_back(NVT); + } else { + assert(0 && "Doesn't handle vectors yet!"); + } + } + } + + RetTys.push_back(MVT::Other); // Always has a chain. + + // Finally, create the CALL node. + SDOperand Res = DAG.getNode(ISD::CALL, RetTys, Ops); + + // This returns a pair of operands. The first element is the + // return value for the function (if RetTy is not VoidTy). The second + // element is the outgoing token chain. + SDOperand ResVal; + if (RetTys.size() != 1) { + MVT::ValueType VT = getValueType(RetTy); + if (RetTys.size() == 2) { + ResVal = Res; + + // If this value was promoted, truncate it down. + if (ResVal.getValueType() != VT) { + if (MVT::isInteger(VT)) { + unsigned AssertOp = RetTy->isSigned() ? + ISD::AssertSext : ISD::AssertZext; + ResVal = DAG.getNode(AssertOp, ResVal.getValueType(), ResVal, + DAG.getValueType(VT)); + ResVal = DAG.getNode(ISD::TRUNCATE, VT, ResVal); + } else { + assert(MVT::isFloatingPoint(VT)); + ResVal = DAG.getNode(ISD::FP_ROUND, VT, ResVal); + } + } + } else if (RetTys.size() == 3) { + ResVal = DAG.getNode(ISD::BUILD_PAIR, VT, + Res.getValue(0), Res.getValue(1)); + + } else { + assert(0 && "Case not handled yet!"); + } + } + + return std::make_pair(ResVal, Res.getValue(Res.Val->getNumValues()-1)); +} + + + // It is always conservatively correct for llvm.returnaddress and // llvm.frameaddress to return 0. +// +// FIXME: Change this to insert a FRAMEADDR/RETURNADDR node, and have that be +// expanded to 0 if the target wants. std::pair TargetLowering::LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth, SelectionDAG &DAG) { From lattner at cs.uiuc.edu Tue May 16 17:56:20 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 16 May 2006 17:56:20 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCISelLowering.h Message-ID: <200605162256.RAA00444@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.175 -> 1.176 PPCISelLowering.h updated: 1.48 -> 1.49 --- Log message: Instead of implementing LowerCallTo directly, let the default impl produce an ISD::CALL node, then custom lower that. This means that we only have to handle LEGAL call operands/results, not every possible type. This allows us to simplify the call code, shrinking it by about 1/3. --- Diffs of the changes: (+147 -219) PPCISelLowering.cpp | 358 +++++++++++++++++++++------------------------------- PPCISelLowering.h | 8 - 2 files changed, 147 insertions(+), 219 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.175 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.176 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.175 Tue May 16 13:58:15 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Tue May 16 17:56:08 2006 @@ -877,6 +877,152 @@ return DAG.getNode(ISD::MERGE_VALUES, RetVT, ArgValues); } +static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) { + SDOperand Chain = Op.getOperand(0); + unsigned CallingConv= cast(Op.getOperand(1))->getValue(); + bool isVarArg = cast(Op.getOperand(2))->getValue() != 0; + bool isTailCall = cast(Op.getOperand(3))->getValue() != 0; + SDOperand Callee = Op.getOperand(4); + + // args_to_use will accumulate outgoing args for the PPCISD::CALL case in + // SelectExpr to use to put the arguments in the appropriate registers. + std::vector args_to_use; + + // Count how many bytes are to be pushed on the stack, including the linkage + // area, and parameter passing area. + unsigned NumBytes = 24; + + if (Op.getNumOperands() == 5) { + Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes, MVT::i32)); + } else { + for (unsigned i = 5, e = Op.getNumOperands(); i != e; ++i) + NumBytes += MVT::getSizeInBits(Op.getOperand(i).getValueType())/8; + + // Just to be safe, we'll always reserve the full 24 bytes of linkage area + // plus 32 bytes of argument space in case any called code gets funky on us. + // (Required by ABI to support var arg) + if (NumBytes < 56) NumBytes = 56; + + // Adjust the stack pointer for the new arguments... + // These operations are automatically eliminated by the prolog/epilog pass + Chain = DAG.getCALLSEQ_START(Chain, + DAG.getConstant(NumBytes, MVT::i32)); + + // Set up a copy of the stack pointer for use loading and storing any + // arguments that may not fit in the registers available for argument + // passing. + SDOperand StackPtr = DAG.getRegister(PPC::R1, MVT::i32); + + // Figure out which arguments are going to go in registers, and which in + // memory. Also, if this is a vararg function, floating point operations + // must be stored to our stack, and loaded into integer regs as well, if + // any integer regs are available for argument passing. + unsigned ArgOffset = 24; + unsigned GPR_remaining = 8; + unsigned FPR_remaining = 13; + + std::vector MemOps; + for (unsigned i = 5, e = Op.getNumOperands(); i != e; ++i) { + SDOperand Arg = Op.getOperand(i); + + // PtrOff will be used to store the current argument to the stack if a + // register cannot be found for it. + SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); + PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); + switch (Arg.getValueType()) { + default: assert(0 && "Unexpected ValueType for argument!"); + case MVT::i32: + if (GPR_remaining > 0) { + args_to_use.push_back(Arg); + --GPR_remaining; + } else { + MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, + Arg, PtrOff, DAG.getSrcValue(NULL))); + } + ArgOffset += 4; + break; + case MVT::f32: + case MVT::f64: + if (FPR_remaining > 0) { + args_to_use.push_back(Arg); + --FPR_remaining; + if (isVarArg) { + SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain, + Arg, PtrOff, + DAG.getSrcValue(NULL)); + MemOps.push_back(Store); + // Float varargs are always shadowed in available integer registers + if (GPR_remaining > 0) { + SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff, + DAG.getSrcValue(NULL)); + MemOps.push_back(Load.getValue(1)); + args_to_use.push_back(Load); + --GPR_remaining; + } + if (GPR_remaining > 0 && Arg.getValueType() == MVT::f64) { + SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType()); + PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour); + SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff, + DAG.getSrcValue(NULL)); + MemOps.push_back(Load.getValue(1)); + args_to_use.push_back(Load); + --GPR_remaining; + } + } else { + // If we have any FPRs remaining, we may also have GPRs remaining. + // Args passed in FPRs consume either 1 (f32) or 2 (f64) available + // GPRs. + if (GPR_remaining > 0) { + args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); + --GPR_remaining; + } + if (GPR_remaining > 0 && Arg.getValueType() == MVT::f64) { + args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); + --GPR_remaining; + } + } + } else { + MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, + Arg, PtrOff, DAG.getSrcValue(NULL))); + } + ArgOffset += (Arg.getValueType() == MVT::f32) ? 4 : 8; + break; + } + } + if (!MemOps.empty()) + Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps); + } + + std::vector RetVals(Op.Val->value_begin(), + Op.Val->value_end()); + + // If the callee is a GlobalAddress node (quite common, every direct call is) + // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. + if (GlobalAddressSDNode *G = dyn_cast(Callee)) + Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32); + + std::vector Ops; + Ops.push_back(Chain); + Ops.push_back(Callee); + Ops.insert(Ops.end(), args_to_use.begin(), args_to_use.end()); + SDOperand TheCall = DAG.getNode(PPCISD::CALL, RetVals, Ops); + + Chain = TheCall.getValue(TheCall.Val->getNumValues()-1); + Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, + DAG.getConstant(NumBytes, MVT::i32)); + + std::vector RetVT(Op.Val->value_begin(), + Op.Val->value_end()); + Ops.clear(); + + for (unsigned i = 0, e = TheCall.Val->getNumValues()-1; i != e; ++i) + Ops.push_back(SDOperand(TheCall.Val, i)); + Ops.push_back(Chain); + SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, RetVT, Ops); + + return Res.getValue(Op.ResNo); +} + static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) { SDOperand Copy; switch(Op.getNumOperands()) { @@ -1842,6 +1988,7 @@ case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex); case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex); + case ISD::CALL: return LowerCALL(Op, DAG); case ISD::RET: return LowerRET(Op, DAG); case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); @@ -1867,217 +2014,6 @@ // Other Lowering Code //===----------------------------------------------------------------------===// -std::pair -PPCTargetLowering::LowerCallTo(SDOperand Chain, - const Type *RetTy, bool isVarArg, - unsigned CallingConv, bool isTailCall, - SDOperand Callee, ArgListTy &Args, - SelectionDAG &DAG) { - // args_to_use will accumulate outgoing args for the PPCISD::CALL case in - // SelectExpr to use to put the arguments in the appropriate registers. - std::vector args_to_use; - - // Count how many bytes are to be pushed on the stack, including the linkage - // area, and parameter passing area. - unsigned NumBytes = 24; - - if (Args.empty()) { - Chain = DAG.getCALLSEQ_START(Chain, - DAG.getConstant(NumBytes, getPointerTy())); - } else { - for (unsigned i = 0, e = Args.size(); i != e; ++i) { - switch (getValueType(Args[i].second)) { - default: assert(0 && "Unknown value type!"); - case MVT::i1: - case MVT::i8: - case MVT::i16: - case MVT::i32: - case MVT::f32: - NumBytes += 4; - break; - case MVT::i64: - case MVT::f64: - NumBytes += 8; - break; - } - } - - // Just to be safe, we'll always reserve the full 24 bytes of linkage area - // plus 32 bytes of argument space in case any called code gets funky on us. - // (Required by ABI to support var arg) - if (NumBytes < 56) NumBytes = 56; - - // Adjust the stack pointer for the new arguments... - // These operations are automatically eliminated by the prolog/epilog pass - Chain = DAG.getCALLSEQ_START(Chain, - DAG.getConstant(NumBytes, getPointerTy())); - - // Set up a copy of the stack pointer for use loading and storing any - // arguments that may not fit in the registers available for argument - // passing. - SDOperand StackPtr = DAG.getRegister(PPC::R1, MVT::i32); - - // Figure out which arguments are going to go in registers, and which in - // memory. Also, if this is a vararg function, floating point operations - // must be stored to our stack, and loaded into integer regs as well, if - // any integer regs are available for argument passing. - unsigned ArgOffset = 24; - unsigned GPR_remaining = 8; - unsigned FPR_remaining = 13; - - std::vector MemOps; - for (unsigned i = 0, e = Args.size(); i != e; ++i) { - // PtrOff will be used to store the current argument to the stack if a - // register cannot be found for it. - SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); - PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); - MVT::ValueType ArgVT = getValueType(Args[i].second); - - switch (ArgVT) { - default: assert(0 && "Unexpected ValueType for argument!"); - case MVT::i1: - case MVT::i8: - case MVT::i16: - // Promote the integer to 32 bits. If the input type is signed use a - // sign extend, otherwise use a zero extend. - if (Args[i].second->isSigned()) - Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first); - else - Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first); - // FALL THROUGH - case MVT::i32: - if (GPR_remaining > 0) { - args_to_use.push_back(Args[i].first); - --GPR_remaining; - } else { - MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, - Args[i].first, PtrOff, - DAG.getSrcValue(NULL))); - } - ArgOffset += 4; - break; - case MVT::i64: - // If we have one free GPR left, we can place the upper half of the i64 - // in it, and store the other half to the stack. If we have two or more - // free GPRs, then we can pass both halves of the i64 in registers. - if (GPR_remaining > 0) { - SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, - Args[i].first, DAG.getConstant(1, MVT::i32)); - SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, - Args[i].first, DAG.getConstant(0, MVT::i32)); - args_to_use.push_back(Hi); - --GPR_remaining; - if (GPR_remaining > 0) { - args_to_use.push_back(Lo); - --GPR_remaining; - } else { - SDOperand ConstFour = DAG.getConstant(4, getPointerTy()); - PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour); - MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, - Lo, PtrOff, DAG.getSrcValue(NULL))); - } - } else { - MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, - Args[i].first, PtrOff, - DAG.getSrcValue(NULL))); - } - ArgOffset += 8; - break; - case MVT::f32: - case MVT::f64: - if (FPR_remaining > 0) { - args_to_use.push_back(Args[i].first); - --FPR_remaining; - if (isVarArg) { - SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain, - Args[i].first, PtrOff, - DAG.getSrcValue(NULL)); - MemOps.push_back(Store); - // Float varargs are always shadowed in available integer registers - if (GPR_remaining > 0) { - SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff, - DAG.getSrcValue(NULL)); - MemOps.push_back(Load.getValue(1)); - args_to_use.push_back(Load); - --GPR_remaining; - } - if (GPR_remaining > 0 && MVT::f64 == ArgVT) { - SDOperand ConstFour = DAG.getConstant(4, getPointerTy()); - PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour); - SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff, - DAG.getSrcValue(NULL)); - MemOps.push_back(Load.getValue(1)); - args_to_use.push_back(Load); - --GPR_remaining; - } - } else { - // If we have any FPRs remaining, we may also have GPRs remaining. - // Args passed in FPRs consume either 1 (f32) or 2 (f64) available - // GPRs. - if (GPR_remaining > 0) { - args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); - --GPR_remaining; - } - if (GPR_remaining > 0 && MVT::f64 == ArgVT) { - args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); - --GPR_remaining; - } - } - } else { - MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, - Args[i].first, PtrOff, - DAG.getSrcValue(NULL))); - } - ArgOffset += (ArgVT == MVT::f32) ? 4 : 8; - break; - } - } - if (!MemOps.empty()) - Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps); - } - - std::vector RetVals; - MVT::ValueType RetTyVT = getValueType(RetTy); - MVT::ValueType ActualRetTyVT = RetTyVT; - if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i16) - ActualRetTyVT = MVT::i32; // Promote result to i32. - - if (RetTyVT == MVT::i64) { - RetVals.push_back(MVT::i32); - RetVals.push_back(MVT::i32); - } else if (RetTyVT != MVT::isVoid) { - RetVals.push_back(ActualRetTyVT); - } - RetVals.push_back(MVT::Other); - - // If the callee is a GlobalAddress node (quite common, every direct call is) - // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. - if (GlobalAddressSDNode *G = dyn_cast(Callee)) - Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32); - - std::vector Ops; - Ops.push_back(Chain); - Ops.push_back(Callee); - Ops.insert(Ops.end(), args_to_use.begin(), args_to_use.end()); - SDOperand TheCall = DAG.getNode(PPCISD::CALL, RetVals, Ops); - Chain = TheCall.getValue(TheCall.Val->getNumValues()-1); - Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, - DAG.getConstant(NumBytes, getPointerTy())); - SDOperand RetVal = TheCall; - - // If the result is a small value, add a note so that we keep track of the - // information about whether it is sign or zero extended. - if (RetTyVT != ActualRetTyVT) { - RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext : ISD::AssertZext, - MVT::i32, RetVal, DAG.getValueType(RetTyVT)); - RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal); - } else if (RetTyVT == MVT::i64) { - RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, RetVal, RetVal.getValue(1)); - } - - return std::make_pair(RetVal, Chain); -} - MachineBasicBlock * PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, MachineBasicBlock *BB) { Index: llvm/lib/Target/PowerPC/PPCISelLowering.h diff -u llvm/lib/Target/PowerPC/PPCISelLowering.h:1.48 llvm/lib/Target/PowerPC/PPCISelLowering.h:1.49 --- llvm/lib/Target/PowerPC/PPCISelLowering.h:1.48 Tue May 16 13:18:50 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.h Tue May 16 17:56:08 2006 @@ -166,14 +166,6 @@ uint64_t &KnownZero, uint64_t &KnownOne, unsigned Depth = 0) const; - - /// LowerCallTo - This hook lowers an abstract call to a function into an - /// actual call. - virtual std::pair - LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, - unsigned CC, - bool isTailCall, SDOperand Callee, ArgListTy &Args, - SelectionDAG &DAG); virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI, MachineBasicBlock *MBB); From lattner at cs.uiuc.edu Tue May 16 18:39:56 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 16 May 2006 18:39:56 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Message-ID: <200605162339.SAA02411@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAGISel.cpp updated: 1.243 -> 1.244 --- Log message: Add support for calls that pass and return legal vectors. --- Diffs of the changes: (+60 -3) SelectionDAGISel.cpp | 63 ++++++++++++++++++++++++++++++++++++++++++++++++--- 1 files changed, 60 insertions(+), 3 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.243 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.244 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.243 Tue May 16 17:53:20 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue May 16 18:39:44 2006 @@ -2470,6 +2470,7 @@ Ops.push_back(N); } else { assert(0 && "Don't support illegal by-val vector arguments yet!"); + abort(); } } break; @@ -2537,7 +2538,26 @@ assert(0 && "Cannot expand i64 -> i16 yet!"); } } else { - assert(0 && "Doesn't handle vectors yet!"); + // Otherwise, this is a vector type. We only support legal vectors + // right now. + const PackedType *PTy = cast(Args[i].second); + unsigned NumElems = PTy->getNumElements(); + const Type *EltTy = PTy->getElementType(); + + // Figure out if there is a Packed type corresponding to this Vector + // type. If so, convert to the packed type. + MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems); + if (TVT != MVT::Other && isTypeLegal(TVT)) { + // Handle copies from generic vectors to registers. + MVT::ValueType PTyElementVT, PTyLegalElementVT; + unsigned NE = getPackedTypeBreakdown(PTy, PTyElementVT, + PTyLegalElementVT); + // Insert a VBIT_CONVERT of the MVT::Vector type to the packed type. + Ops.push_back(DAG.getNode(ISD::VBIT_CONVERT, TVT, Op)); + } else { + assert(0 && "Don't support illegal by-val vector call args yet!"); + abort(); + } } break; } @@ -2566,7 +2586,21 @@ for (unsigned i = 0; i != NumVals; ++i) RetTys.push_back(NVT); } else { - assert(0 && "Doesn't handle vectors yet!"); + // Otherwise, this is a vector type. We only support legal vectors + // right now. + const PackedType *PTy = cast(RetTy); + unsigned NumElems = PTy->getNumElements(); + const Type *EltTy = PTy->getElementType(); + + // Figure out if there is a Packed type corresponding to this Vector + // type. If so, convert to the packed type. + MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems); + if (TVT != MVT::Other && isTypeLegal(TVT)) { + RetTys.push_back(TVT); + } else { + assert(0 && "Don't support illegal by-val vector call results yet!"); + abort(); + } } } } @@ -2587,7 +2621,30 @@ // If this value was promoted, truncate it down. if (ResVal.getValueType() != VT) { - if (MVT::isInteger(VT)) { + if (VT == MVT::Vector) { + // Insert a VBITCONVERT to convert from the packed result type to the + // MVT::Vector type. + unsigned NumElems = cast(RetTy)->getNumElements(); + const Type *EltTy = cast(RetTy)->getElementType(); + + // Figure out if there is a Packed type corresponding to this Vector + // type. If so, convert to the packed type. + MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems); + if (TVT != MVT::Other && isTypeLegal(TVT)) { + // Handle copies from generic vectors to registers. + MVT::ValueType PTyElementVT, PTyLegalElementVT; + unsigned NE = getPackedTypeBreakdown(cast(RetTy), + PTyElementVT, + PTyLegalElementVT); + // Insert a VBIT_CONVERT of the FORMAL_ARGUMENTS to a + // "N x PTyElementVT" MVT::Vector type. + ResVal = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, ResVal, + DAG.getConstant(NE, MVT::i32), + DAG.getValueType(PTyElementVT)); + } else { + abort(); + } + } else if (MVT::isInteger(VT)) { unsigned AssertOp = RetTy->isSigned() ? ISD::AssertSext : ISD::AssertZext; ResVal = DAG.getNode(AssertOp, ResVal.getValueType(), ResVal, From lattner at cs.uiuc.edu Tue May 16 18:54:37 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 16 May 2006 18:54:37 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp PPCISelLowering.cpp Message-ID: <200605162354.SAA03202@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelDAGToDAG.cpp updated: 1.184 -> 1.185 PPCISelLowering.cpp updated: 1.176 -> 1.177 --- Log message: implement passing/returning vector regs to calls, at least non-varargs calls. --- Diffs of the changes: (+54 -29) PPCISelDAGToDAG.cpp | 70 +++++++++++++++++++++++++++++++--------------------- PPCISelLowering.cpp | 13 ++++++++- 2 files changed, 54 insertions(+), 29 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.184 llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.185 --- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.184 Fri May 12 11:29:37 2006 +++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Tue May 16 18:54:25 2006 @@ -137,8 +137,8 @@ return "PowerPC DAG->DAG Pattern Instruction Selection"; } - /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for this - /// target when scheduling the DAG. + /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for + /// this target when scheduling the DAG. virtual HazardRecognizer *CreateTargetHazardRecognizer() { // Should use subtarget info to pick the right hazard recognizer. For // now, always return a PPC970 recognizer. @@ -813,8 +813,8 @@ Op = SDOperand(CurDAG->getTargetNode(PPC::NOR, MVT::i32, Op, Op), 0); SDNode *AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag, Op, getI32Imm(~0U)); - return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDOperand(AD, 0), Op, - SDOperand(AD, 1)); + return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDOperand(AD, 0), + Op, SDOperand(AD, 1)); } case ISD::SETLT: { SDOperand AD = SDOperand(CurDAG->getTargetNode(PPC::ADDI, MVT::i32, Op, @@ -908,7 +908,7 @@ CallOpcode = PPC::BCTRL; } - unsigned GPR_idx = 0, FPR_idx = 0; + unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; static const unsigned GPR[] = { PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, @@ -917,6 +917,10 @@ PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13 }; + static const unsigned VR[] = { + PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, + PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 + }; SDOperand InFlag; // Null incoming flag value. @@ -926,11 +930,13 @@ if (RegTy == MVT::i32) { assert(GPR_idx < 8 && "Too many int args"); DestReg = GPR[GPR_idx++]; - } else { - assert(MVT::isFloatingPoint(N->getOperand(i).getValueType()) && - "Unpromoted integer arg?"); + } else if (MVT::isFloatingPoint(N->getOperand(i).getValueType())) { assert(FPR_idx < 13 && "Too many fp args"); DestReg = FPR[FPR_idx++]; + } else { + assert(MVT::isVector(N->getOperand(i).getValueType()) && "unknown arg!"); + assert(VR_idx < 12 && "Too many vector args"); + DestReg = VR[VR_idx++]; } if (N->getOperand(i).getOpcode() != ISD::UNDEF) { @@ -955,28 +961,36 @@ // If the call has results, copy the values out of the ret val registers. switch (N->getValueType(0)) { - default: assert(0 && "Unexpected ret value!"); - case MVT::Other: break; - case MVT::i32: - if (N->getValueType(1) == MVT::i32) { - Chain = CurDAG->getCopyFromReg(Chain, PPC::R4, MVT::i32, - Chain.getValue(1)).getValue(1); - CallResults.push_back(Chain.getValue(0)); - Chain = CurDAG->getCopyFromReg(Chain, PPC::R3, MVT::i32, - Chain.getValue(2)).getValue(1); - CallResults.push_back(Chain.getValue(0)); - } else { - Chain = CurDAG->getCopyFromReg(Chain, PPC::R3, MVT::i32, - Chain.getValue(1)).getValue(1); - CallResults.push_back(Chain.getValue(0)); - } - break; - case MVT::f32: - case MVT::f64: - Chain = CurDAG->getCopyFromReg(Chain, PPC::F1, N->getValueType(0), + default: assert(0 && "Unexpected ret value!"); + case MVT::Other: break; + case MVT::i32: + if (N->getValueType(1) == MVT::i32) { + Chain = CurDAG->getCopyFromReg(Chain, PPC::R4, MVT::i32, Chain.getValue(1)).getValue(1); CallResults.push_back(Chain.getValue(0)); - break; + Chain = CurDAG->getCopyFromReg(Chain, PPC::R3, MVT::i32, + Chain.getValue(2)).getValue(1); + CallResults.push_back(Chain.getValue(0)); + } else { + Chain = CurDAG->getCopyFromReg(Chain, PPC::R3, MVT::i32, + Chain.getValue(1)).getValue(1); + CallResults.push_back(Chain.getValue(0)); + } + break; + case MVT::f32: + case MVT::f64: + Chain = CurDAG->getCopyFromReg(Chain, PPC::F1, N->getValueType(0), + Chain.getValue(1)).getValue(1); + CallResults.push_back(Chain.getValue(0)); + break; + case MVT::v4f32: + case MVT::v4i32: + case MVT::v8i16: + case MVT::v16i8: + Chain = CurDAG->getCopyFromReg(Chain, PPC::V2, N->getValueType(0), + Chain.getValue(1)).getValue(1); + CallResults.push_back(Chain.getValue(0)); + break; } CallResults.push_back(Chain); Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.176 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.177 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.176 Tue May 16 17:56:08 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Tue May 16 18:54:25 2006 @@ -920,7 +920,8 @@ unsigned ArgOffset = 24; unsigned GPR_remaining = 8; unsigned FPR_remaining = 13; - + unsigned VR_remaining = 12; + std::vector MemOps; for (unsigned i = 5, e = Op.getNumOperands(); i != e; ++i) { SDOperand Arg = Op.getOperand(i); @@ -987,6 +988,16 @@ } ArgOffset += (Arg.getValueType() == MVT::f32) ? 4 : 8; break; + case MVT::v4f32: + case MVT::v4i32: + case MVT::v8i16: + case MVT::v16i8: + assert(!isVarArg && "Don't support passing vectors to varargs yet!"); + assert(VR_remaining && + "Don't support passing more than 12 vector args yet!"); + args_to_use.push_back(Arg); + --VR_remaining; + break; } } if (!MemOps.empty()) From lattner at cs.uiuc.edu Tue May 16 19:15:52 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 16 May 2006 19:15:52 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp Message-ID: <200605170015.TAA04026@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.177 -> 1.178 --- Log message: 3 changes, 2 of which are cleanup one of which changes codegen: 1. Rearrange code a bit so that the special case doesn't require indenting lots of code. 2. Add comments describing PPC calling convention. 3. Only round up to 56-bytes of stack space for an outgoing call if the callee is varargs. This saves a bit of stack space. --- Diffs of the changes: (+112 -106) PPCISelLowering.cpp | 218 ++++++++++++++++++++++++++-------------------------- 1 files changed, 112 insertions(+), 106 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.177 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.178 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.177 Tue May 16 18:54:25 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Tue May 16 19:15:40 2006 @@ -889,120 +889,126 @@ std::vector args_to_use; // Count how many bytes are to be pushed on the stack, including the linkage - // area, and parameter passing area. + // area, and parameter passing area. We start with 24 bytes, which is + // prereserved space for [SP][CR][LR][3 x unused]. unsigned NumBytes = 24; - if (Op.getNumOperands() == 5) { - Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes, MVT::i32)); - } else { - for (unsigned i = 5, e = Op.getNumOperands(); i != e; ++i) - NumBytes += MVT::getSizeInBits(Op.getOperand(i).getValueType())/8; - - // Just to be safe, we'll always reserve the full 24 bytes of linkage area - // plus 32 bytes of argument space in case any called code gets funky on us. - // (Required by ABI to support var arg) - if (NumBytes < 56) NumBytes = 56; - - // Adjust the stack pointer for the new arguments... - // These operations are automatically eliminated by the prolog/epilog pass - Chain = DAG.getCALLSEQ_START(Chain, - DAG.getConstant(NumBytes, MVT::i32)); - - // Set up a copy of the stack pointer for use loading and storing any - // arguments that may not fit in the registers available for argument - // passing. - SDOperand StackPtr = DAG.getRegister(PPC::R1, MVT::i32); - - // Figure out which arguments are going to go in registers, and which in - // memory. Also, if this is a vararg function, floating point operations - // must be stored to our stack, and loaded into integer regs as well, if - // any integer regs are available for argument passing. - unsigned ArgOffset = 24; - unsigned GPR_remaining = 8; - unsigned FPR_remaining = 13; - unsigned VR_remaining = 12; - - std::vector MemOps; - for (unsigned i = 5, e = Op.getNumOperands(); i != e; ++i) { - SDOperand Arg = Op.getOperand(i); - - // PtrOff will be used to store the current argument to the stack if a - // register cannot be found for it. - SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); - PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); - switch (Arg.getValueType()) { - default: assert(0 && "Unexpected ValueType for argument!"); - case MVT::i32: - if (GPR_remaining > 0) { - args_to_use.push_back(Arg); - --GPR_remaining; - } else { - MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, - Arg, PtrOff, DAG.getSrcValue(NULL))); - } - ArgOffset += 4; - break; - case MVT::f32: - case MVT::f64: - if (FPR_remaining > 0) { - args_to_use.push_back(Arg); - --FPR_remaining; - if (isVarArg) { - SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain, - Arg, PtrOff, - DAG.getSrcValue(NULL)); - MemOps.push_back(Store); - // Float varargs are always shadowed in available integer registers - if (GPR_remaining > 0) { - SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff, - DAG.getSrcValue(NULL)); - MemOps.push_back(Load.getValue(1)); - args_to_use.push_back(Load); - --GPR_remaining; - } - if (GPR_remaining > 0 && Arg.getValueType() == MVT::f64) { - SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType()); - PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour); - SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff, - DAG.getSrcValue(NULL)); - MemOps.push_back(Load.getValue(1)); - args_to_use.push_back(Load); - --GPR_remaining; - } - } else { - // If we have any FPRs remaining, we may also have GPRs remaining. - // Args passed in FPRs consume either 1 (f32) or 2 (f64) available - // GPRs. - if (GPR_remaining > 0) { - args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); - --GPR_remaining; - } - if (GPR_remaining > 0 && Arg.getValueType() == MVT::f64) { - args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); - --GPR_remaining; - } + // Add up all the space actually used. + for (unsigned i = 5, e = Op.getNumOperands(); i != e; ++i) + NumBytes += MVT::getSizeInBits(Op.getOperand(i).getValueType())/8; + + // If we are calling what looks like a varargs function on the caller side, + // there are two cases: + // 1) The callee uses va_start. + // 2) The callee doesn't use va_start. + // + // In the case of #1, the prolog code will store up to 8 GPR argument + // registers to the stack, allowing va_start to index over them in memory. + // Because we cannot tell the difference (on the caller side) between #1/#2, + // we have to conservatively assume we have #1. As such, make sure we have + // at least enough stack space for the caller to store the 8 GPRs. + if (isVarArg && Op.getNumOperands() > 5 && NumBytes < 56) + NumBytes = 56; + + // Adjust the stack pointer for the new arguments... + // These operations are automatically eliminated by the prolog/epilog pass + Chain = DAG.getCALLSEQ_START(Chain, + DAG.getConstant(NumBytes, MVT::i32)); + + // Set up a copy of the stack pointer for use loading and storing any + // arguments that may not fit in the registers available for argument + // passing. + SDOperand StackPtr = DAG.getRegister(PPC::R1, MVT::i32); + + // Figure out which arguments are going to go in registers, and which in + // memory. Also, if this is a vararg function, floating point operations + // must be stored to our stack, and loaded into integer regs as well, if + // any integer regs are available for argument passing. + unsigned ArgOffset = 24; + unsigned GPR_remaining = 8; + unsigned FPR_remaining = 13; + unsigned VR_remaining = 12; + + std::vector MemOps; + for (unsigned i = 5, e = Op.getNumOperands(); i != e; ++i) { + SDOperand Arg = Op.getOperand(i); + + // PtrOff will be used to store the current argument to the stack if a + // register cannot be found for it. + SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); + PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); + switch (Arg.getValueType()) { + default: assert(0 && "Unexpected ValueType for argument!"); + case MVT::i32: + if (GPR_remaining > 0) { + args_to_use.push_back(Arg); + --GPR_remaining; + } else { + MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, + Arg, PtrOff, DAG.getSrcValue(NULL))); + } + ArgOffset += 4; + break; + case MVT::f32: + case MVT::f64: + if (FPR_remaining > 0) { + args_to_use.push_back(Arg); + --FPR_remaining; + if (isVarArg) { + SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain, + Arg, PtrOff, + DAG.getSrcValue(NULL)); + MemOps.push_back(Store); + // Float varargs are always shadowed in available integer registers + if (GPR_remaining > 0) { + SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff, + DAG.getSrcValue(NULL)); + MemOps.push_back(Load.getValue(1)); + args_to_use.push_back(Load); + --GPR_remaining; + } + if (GPR_remaining > 0 && Arg.getValueType() == MVT::f64) { + SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType()); + PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour); + SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff, + DAG.getSrcValue(NULL)); + MemOps.push_back(Load.getValue(1)); + args_to_use.push_back(Load); + --GPR_remaining; } } else { - MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, - Arg, PtrOff, DAG.getSrcValue(NULL))); + // If we have any FPRs remaining, we may also have GPRs remaining. + // Args passed in FPRs consume either 1 (f32) or 2 (f64) available + // GPRs. + if (GPR_remaining > 0) { + args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); + --GPR_remaining; + } + if (GPR_remaining > 0 && Arg.getValueType() == MVT::f64) { + args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); + --GPR_remaining; + } } - ArgOffset += (Arg.getValueType() == MVT::f32) ? 4 : 8; - break; - case MVT::v4f32: - case MVT::v4i32: - case MVT::v8i16: - case MVT::v16i8: - assert(!isVarArg && "Don't support passing vectors to varargs yet!"); - assert(VR_remaining && - "Don't support passing more than 12 vector args yet!"); - args_to_use.push_back(Arg); - --VR_remaining; - break; + } else { + MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, + Arg, PtrOff, DAG.getSrcValue(NULL))); } + ArgOffset += (Arg.getValueType() == MVT::f32) ? 4 : 8; + break; + case MVT::v4f32: + case MVT::v4i32: + case MVT::v8i16: + case MVT::v16i8: + assert(!isVarArg && "Don't support passing vectors to varargs yet!"); + assert(VR_remaining && + "Don't support passing more than 12 vector args yet!"); + args_to_use.push_back(Arg); + --VR_remaining; + break; } - if (!MemOps.empty()) - Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps); } + if (!MemOps.empty()) + Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps); std::vector RetVals(Op.Val->value_begin(), Op.Val->value_end()); From lattner at cs.uiuc.edu Tue May 16 19:18:35 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 16 May 2006 19:18:35 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/vec_call.ll Message-ID: <200605170018.TAA04228@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/PowerPC: vec_call.ll added (r1.1) --- Log message: test for support to pass/return vectors to calls. --- Diffs of the changes: (+11 -0) vec_call.ll | 11 +++++++++++ 1 files changed, 11 insertions(+) Index: llvm/test/Regression/CodeGen/PowerPC/vec_call.ll diff -c /dev/null llvm/test/Regression/CodeGen/PowerPC/vec_call.ll:1.1 *** /dev/null Tue May 16 19:18:33 2006 --- llvm/test/Regression/CodeGen/PowerPC/vec_call.ll Tue May 16 19:18:23 2006 *************** *** 0 **** --- 1,11 ---- + ; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 + + <4 x int> %test_arg(<4 x int> %A, <4 x int> %B) { + %C = add <4 x int> %A, %B + ret <4 x int> %C + } + + <4 x int> %foo() { + %X = call <4 x int> %test_arg(<4 x int> zeroinitializer, <4 x int> zeroinitializer) + ret <4 x int> %X + } From lattner at cs.uiuc.edu Tue May 16 22:57:43 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 16 May 2006 22:57:43 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/calls.ll Message-ID: <200605170357.WAA11626@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/PowerPC: calls.ll added (r1.1) --- Log message: new test for various forms of calls --- Diffs of the changes: (+23 -0) calls.ll | 23 +++++++++++++++++++++++ 1 files changed, 23 insertions(+) Index: llvm/test/Regression/CodeGen/PowerPC/calls.ll diff -c /dev/null llvm/test/Regression/CodeGen/PowerPC/calls.ll:1.1 *** /dev/null Tue May 16 22:57:41 2006 --- llvm/test/Regression/CodeGen/PowerPC/calls.ll Tue May 16 22:57:31 2006 *************** *** 0 **** --- 1,23 ---- + ; Test various forms of calls. + + ; RUN: llvm-as < %s | llc -march=ppc32 | grep 'bl ' | wc -l | grep 1 && + ; RUN: llvm-as < %s | llc -march=ppc32 | grep 'bctrl' | wc -l | grep 1 && + ; RUN: llvm-as < %s | llc -march=ppc32 | grep 'bla ' | wc -l | grep 1 + + declare void %foo() + + void %test_direct() { + call void %foo() + ret void + } + + void %test_indirect(void()* %fp) { + call void %fp() + ret void + } + + void %test_abs() { + %fp = cast int 400 to void()* + call void %fp() + ret void + } From lattner at cs.uiuc.edu Tue May 16 23:20:25 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Tue, 16 May 2006 23:20:25 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/calls.ll Message-ID: <200605170420.XAA12293@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/PowerPC: calls.ll updated: 1.1 -> 1.2 --- Log message: add an external symbol testcase --- Diffs of the changes: (+6 -1) calls.ll | 7 ++++++- 1 files changed, 6 insertions(+), 1 deletion(-) Index: llvm/test/Regression/CodeGen/PowerPC/calls.ll diff -u llvm/test/Regression/CodeGen/PowerPC/calls.ll:1.1 llvm/test/Regression/CodeGen/PowerPC/calls.ll:1.2 --- llvm/test/Regression/CodeGen/PowerPC/calls.ll:1.1 Tue May 16 22:57:31 2006 +++ llvm/test/Regression/CodeGen/PowerPC/calls.ll Tue May 16 23:20:13 2006 @@ -1,6 +1,6 @@ ; Test various forms of calls. -; RUN: llvm-as < %s | llc -march=ppc32 | grep 'bl ' | wc -l | grep 1 && +; RUN: llvm-as < %s | llc -march=ppc32 | grep 'bl ' | wc -l | grep 2 && ; RUN: llvm-as < %s | llc -march=ppc32 | grep 'bctrl' | wc -l | grep 1 && ; RUN: llvm-as < %s | llc -march=ppc32 | grep 'bla ' | wc -l | grep 1 @@ -11,6 +11,11 @@ ret void } +void %test_extsym(sbyte *%P) { + free sbyte* %P + ret void +} + void %test_indirect(void()* %fp) { call void %fp() ret void From lattner at cs.uiuc.edu Wed May 17 01:01:45 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 17 May 2006 01:01:45 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp PPCISelLowering.cpp PPCInstrInfo.td Message-ID: <200605170601.BAA14369@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelDAGToDAG.cpp updated: 1.185 -> 1.186 PPCISelLowering.cpp updated: 1.178 -> 1.179 PPCInstrInfo.td updated: 1.218 -> 1.219 --- Log message: Switch PPC over to a call-selection model where the lowering code creates the copyto/fromregs instead of making the PPCISD::CALL selection code create them. This vastly simplifies the selection code, and moves the ABI handling parts into one place. --- Diffs of the changes: (+136 -155) PPCISelDAGToDAG.cpp | 124 ++++++++--------------------------------- PPCISelLowering.cpp | 157 ++++++++++++++++++++++++++++++++++------------------ PPCInstrInfo.td | 10 ++- 3 files changed, 136 insertions(+), 155 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.185 llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.186 --- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.185 Tue May 16 18:54:25 2006 +++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Wed May 17 01:01:33 2006 @@ -874,129 +874,55 @@ SDOperand PPCDAGToDAGISel::SelectCALL(SDOperand Op) { SDNode *N = Op.Val; - SDOperand Chain; + SDOperand Chain, Flag; Select(Chain, N->getOperand(0)); + if (N->getNumOperands() == 3) // input flag + Select(Flag, N->getOperand(2)); unsigned CallOpcode; - std::vector CallOperands; - + + std::vector CallArgs; if (GlobalAddressSDNode *GASD = dyn_cast(N->getOperand(1))) { CallOpcode = PPC::BL; - CallOperands.push_back(N->getOperand(1)); + CallArgs.push_back(N->getOperand(1)); } else if (ExternalSymbolSDNode *ESSDN = dyn_cast(N->getOperand(1))) { CallOpcode = PPC::BL; - CallOperands.push_back(N->getOperand(1)); + CallArgs.push_back(N->getOperand(1)); } else if (isa(N->getOperand(1)) && isCallCompatibleAddress(cast(N->getOperand(1)))) { ConstantSDNode *C = cast(N->getOperand(1)); CallOpcode = PPC::BLA; - CallOperands.push_back(getI32Imm((int)C->getValue() >> 2)); + CallArgs.push_back(getI32Imm((int)C->getValue() >> 2)); } else { // Copy the callee address into the CTR register. SDOperand Callee; Select(Callee, N->getOperand(1)); - Chain = SDOperand(CurDAG->getTargetNode(PPC::MTCTR, MVT::Other, Callee, - Chain), 0); + if (Flag.Val) + Chain = SDOperand(CurDAG->getTargetNode(PPC::MTCTR, MVT::Other, MVT::Flag, + Callee, Chain, Flag), 0); + else + Chain = SDOperand(CurDAG->getTargetNode(PPC::MTCTR, MVT::Other, MVT::Flag, + Callee, Chain), 0); + Flag = Chain.getValue(1); // Copy the callee address into R12 on darwin. - SDOperand R12 = CurDAG->getRegister(PPC::R12, MVT::i32); - Chain = CurDAG->getNode(ISD::CopyToReg, MVT::Other, Chain, R12, Callee); + Chain = CurDAG->getCopyToReg(Chain, PPC::R12, Callee, Flag); + Flag = Chain.getValue(1); - CallOperands.push_back(R12); CallOpcode = PPC::BCTRL; } - unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; - static const unsigned GPR[] = { - PPC::R3, PPC::R4, PPC::R5, PPC::R6, - PPC::R7, PPC::R8, PPC::R9, PPC::R10, - }; - static const unsigned FPR[] = { - PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, - PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13 - }; - static const unsigned VR[] = { - PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, - PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 - }; - - SDOperand InFlag; // Null incoming flag value. - - for (unsigned i = 2, e = N->getNumOperands(); i != e; ++i) { - unsigned DestReg = 0; - MVT::ValueType RegTy = N->getOperand(i).getValueType(); - if (RegTy == MVT::i32) { - assert(GPR_idx < 8 && "Too many int args"); - DestReg = GPR[GPR_idx++]; - } else if (MVT::isFloatingPoint(N->getOperand(i).getValueType())) { - assert(FPR_idx < 13 && "Too many fp args"); - DestReg = FPR[FPR_idx++]; - } else { - assert(MVT::isVector(N->getOperand(i).getValueType()) && "unknown arg!"); - assert(VR_idx < 12 && "Too many vector args"); - DestReg = VR[VR_idx++]; - } - - if (N->getOperand(i).getOpcode() != ISD::UNDEF) { - SDOperand Val; - Select(Val, N->getOperand(i)); - Chain = CurDAG->getCopyToReg(Chain, DestReg, Val, InFlag); - InFlag = Chain.getValue(1); - CallOperands.push_back(CurDAG->getRegister(DestReg, RegTy)); - } - } - - // Finally, once everything is in registers to pass to the call, emit the - // call itself. - if (InFlag.Val) - CallOperands.push_back(InFlag); // Strong dep on register copies. - else - CallOperands.push_back(Chain); // Weak dep on whatever occurs before + // Emit the call itself. + CallArgs.push_back(Chain); + if (Flag.Val) + CallArgs.push_back(Flag); Chain = SDOperand(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag, - CallOperands), 0); - - std::vector CallResults; - - // If the call has results, copy the values out of the ret val registers. - switch (N->getValueType(0)) { - default: assert(0 && "Unexpected ret value!"); - case MVT::Other: break; - case MVT::i32: - if (N->getValueType(1) == MVT::i32) { - Chain = CurDAG->getCopyFromReg(Chain, PPC::R4, MVT::i32, - Chain.getValue(1)).getValue(1); - CallResults.push_back(Chain.getValue(0)); - Chain = CurDAG->getCopyFromReg(Chain, PPC::R3, MVT::i32, - Chain.getValue(2)).getValue(1); - CallResults.push_back(Chain.getValue(0)); - } else { - Chain = CurDAG->getCopyFromReg(Chain, PPC::R3, MVT::i32, - Chain.getValue(1)).getValue(1); - CallResults.push_back(Chain.getValue(0)); - } - break; - case MVT::f32: - case MVT::f64: - Chain = CurDAG->getCopyFromReg(Chain, PPC::F1, N->getValueType(0), - Chain.getValue(1)).getValue(1); - CallResults.push_back(Chain.getValue(0)); - break; - case MVT::v4f32: - case MVT::v4i32: - case MVT::v8i16: - case MVT::v16i8: - Chain = CurDAG->getCopyFromReg(Chain, PPC::V2, N->getValueType(0), - Chain.getValue(1)).getValue(1); - CallResults.push_back(Chain.getValue(0)); - break; - } - - CallResults.push_back(Chain); - for (unsigned i = 0, e = CallResults.size(); i != e; ++i) - CodeGenMap[Op.getValue(i)] = CallResults[i]; - return CallResults[Op.ResNo]; + CallArgs), 0); + CodeGenMap[Op.getValue(0)] = Chain; + CodeGenMap[Op.getValue(1)] = Chain.getValue(1); + return Chain.getValue(Op.ResNo); } // Select - Convert the specified operand from a target-independent to a Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.178 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.179 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.178 Tue May 16 19:15:40 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Wed May 17 01:01:33 2006 @@ -925,11 +925,25 @@ // must be stored to our stack, and loaded into integer regs as well, if // any integer regs are available for argument passing. unsigned ArgOffset = 24; - unsigned GPR_remaining = 8; - unsigned FPR_remaining = 13; - unsigned VR_remaining = 12; - - std::vector MemOps; + unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; + static const unsigned GPR[] = { + PPC::R3, PPC::R4, PPC::R5, PPC::R6, + PPC::R7, PPC::R8, PPC::R9, PPC::R10, + }; + static const unsigned FPR[] = { + PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, + PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13 + }; + static const unsigned VR[] = { + PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, + PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 + }; + const unsigned NumGPRs = sizeof(GPR)/sizeof(GPR[0]); + const unsigned NumFPRs = sizeof(FPR)/sizeof(FPR[0]); + const unsigned NumVRs = sizeof( VR)/sizeof( VR[0]); + + std::vector > RegsToPass; + std::vector MemOpChains; for (unsigned i = 5, e = Op.getNumOperands(); i != e; ++i) { SDOperand Arg = Op.getOperand(i); @@ -940,58 +954,52 @@ switch (Arg.getValueType()) { default: assert(0 && "Unexpected ValueType for argument!"); case MVT::i32: - if (GPR_remaining > 0) { - args_to_use.push_back(Arg); - --GPR_remaining; + if (GPR_idx != NumGPRs) { + RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg)); } else { - MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, - Arg, PtrOff, DAG.getSrcValue(NULL))); + MemOpChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, + Arg, PtrOff, DAG.getSrcValue(NULL))); } ArgOffset += 4; break; case MVT::f32: case MVT::f64: - if (FPR_remaining > 0) { - args_to_use.push_back(Arg); - --FPR_remaining; + if (FPR_idx != NumFPRs) { + RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg)); + if (isVarArg) { SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain, Arg, PtrOff, DAG.getSrcValue(NULL)); - MemOps.push_back(Store); + MemOpChains.push_back(Store); + // Float varargs are always shadowed in available integer registers - if (GPR_remaining > 0) { + if (GPR_idx != NumGPRs) { SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff, DAG.getSrcValue(NULL)); - MemOps.push_back(Load.getValue(1)); - args_to_use.push_back(Load); - --GPR_remaining; + MemOpChains.push_back(Load.getValue(1)); + RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); } - if (GPR_remaining > 0 && Arg.getValueType() == MVT::f64) { + if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64) { SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType()); PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour); SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff, DAG.getSrcValue(NULL)); - MemOps.push_back(Load.getValue(1)); - args_to_use.push_back(Load); - --GPR_remaining; + MemOpChains.push_back(Load.getValue(1)); + RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); } } else { // If we have any FPRs remaining, we may also have GPRs remaining. // Args passed in FPRs consume either 1 (f32) or 2 (f64) available // GPRs. - if (GPR_remaining > 0) { - args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); - --GPR_remaining; - } - if (GPR_remaining > 0 && Arg.getValueType() == MVT::f64) { - args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); - --GPR_remaining; - } + if (GPR_idx != NumGPRs) + ++GPR_idx; + if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64) + ++GPR_idx; } } else { - MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, - Arg, PtrOff, DAG.getSrcValue(NULL))); + MemOpChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, + Arg, PtrOff, DAG.getSrcValue(NULL))); } ArgOffset += (Arg.getValueType() == MVT::f32) ? 4 : 8; break; @@ -1000,43 +1008,86 @@ case MVT::v8i16: case MVT::v16i8: assert(!isVarArg && "Don't support passing vectors to varargs yet!"); - assert(VR_remaining && + assert(VR_idx != NumVRs && "Don't support passing more than 12 vector args yet!"); - args_to_use.push_back(Arg); - --VR_remaining; + RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg)); break; } } - if (!MemOps.empty()) - Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps); + if (!MemOpChains.empty()) + Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOpChains); - std::vector RetVals(Op.Val->value_begin(), - Op.Val->value_end()); + // Build a sequence of copy-to-reg nodes chained together with token chain + // and flag operands which copy the outgoing args into the appropriate regs. + SDOperand InFlag; + for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { + Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, + InFlag); + InFlag = Chain.getValue(1); + } // If the callee is a GlobalAddress node (quite common, every direct call is) // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. if (GlobalAddressSDNode *G = dyn_cast(Callee)) - Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32); - + Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType()); + + // Create the PPCISD::CALL node itself. + std::vector NodeTys; + NodeTys.push_back(MVT::Other); // Returns a chain + NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. std::vector Ops; Ops.push_back(Chain); Ops.push_back(Callee); - Ops.insert(Ops.end(), args_to_use.begin(), args_to_use.end()); - SDOperand TheCall = DAG.getNode(PPCISD::CALL, RetVals, Ops); + if (InFlag.Val) + Ops.push_back(InFlag); + Chain = DAG.getNode(PPCISD::CALL, NodeTys, Ops); + InFlag = Chain.getValue(1); + + std::vector ResultVals; + NodeTys.clear(); + + // If the call has results, copy the values out of the ret val registers. + switch (Op.Val->getValueType(0)) { + default: assert(0 && "Unexpected ret value!"); + case MVT::Other: break; + case MVT::i32: + if (Op.Val->getValueType(1) == MVT::i32) { + Chain = DAG.getCopyFromReg(Chain, PPC::R4, MVT::i32, InFlag).getValue(1); + ResultVals.push_back(Chain.getValue(0)); + Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, + Chain.getValue(2)).getValue(1); + ResultVals.push_back(Chain.getValue(0)); + NodeTys.push_back(MVT::i32); + } else { + Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1); + ResultVals.push_back(Chain.getValue(0)); + } + NodeTys.push_back(MVT::i32); + break; + case MVT::f32: + case MVT::f64: + Chain = DAG.getCopyFromReg(Chain, PPC::F1, Op.Val->getValueType(0), + InFlag).getValue(1); + ResultVals.push_back(Chain.getValue(0)); + NodeTys.push_back(Op.Val->getValueType(0)); + break; + case MVT::v4f32: + case MVT::v4i32: + case MVT::v8i16: + case MVT::v16i8: + Chain = DAG.getCopyFromReg(Chain, PPC::V2, Op.Val->getValueType(0), + InFlag).getValue(1); + ResultVals.push_back(Chain.getValue(0)); + NodeTys.push_back(Op.Val->getValueType(0)); + break; + } - Chain = TheCall.getValue(TheCall.Val->getNumValues()-1); Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, DAG.getConstant(NumBytes, MVT::i32)); + NodeTys.push_back(MVT::Other); - std::vector RetVT(Op.Val->value_begin(), - Op.Val->value_end()); - Ops.clear(); - - for (unsigned i = 0, e = TheCall.Val->getNumValues()-1; i != e; ++i) - Ops.push_back(SDOperand(TheCall.Val, i)); - Ops.push_back(Chain); - SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, RetVT, Ops); - + ResultVals.push_back(Chain); + SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, ResultVals); return Res.getValue(Op.ResNo); } Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.218 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.219 --- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.218 Sat Apr 22 13:53:45 2006 +++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Wed May 17 01:01:33 2006 @@ -72,6 +72,10 @@ def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeq,[SDNPHasChain]>; def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeq,[SDNPHasChain]>; +def SDT_PPCCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; +def call : SDNode<"PPCISD::CALL", SDT_PPCCall, + [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; + def retflag : SDNode<"PPCISD::RET_FLAG", SDT_PPCRetFlag, [SDNPHasChain, SDNPOptInFlag]>; @@ -303,11 +307,11 @@ LR,CTR, CR0,CR1,CR5,CR6,CR7] in { // Convenient aliases for call instructions - def BL : IForm<18, 0, 1, (ops calltarget:$func, variable_ops), + def BL : IForm<18, 0, 1, (ops calltarget:$func), "bl $func", BrB, []>; - def BLA : IForm<18, 1, 1, (ops aaddr:$func, variable_ops), + def BLA : IForm<18, 1, 1, (ops aaddr:$func), "bla $func", BrB, []>; - def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (ops variable_ops), "bctrl", BrB, + def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (ops), "bctrl", BrB, []>; } From lattner at cs.uiuc.edu Wed May 17 12:56:11 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 17 May 2006 12:56:11 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <200605171756.MAA29189@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.375 -> 1.376 --- Log message: Add an assertion, avoid some unneeded work for each call. No functionality change. --- Diffs of the changes: (+10 -6) LegalizeDAG.cpp | 16 ++++++++++------ 1 files changed, 10 insertions(+), 6 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.375 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.376 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.375 Tue May 16 17:53:20 2006 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed May 17 12:55:45 2006 @@ -820,13 +820,15 @@ case ISD::FORMAL_ARGUMENTS: case ISD::CALL: // The only option for this is to custom lower it. - Result = TLI.LowerOperation(Result.getValue(0), DAG); - assert(Result.Val && "Target didn't custom lower this node!"); + Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG); + assert(Tmp3.Val && "Target didn't custom lower this node!"); + assert(Tmp3.Val->getNumValues() == Result.Val->getNumValues() && + "Lowering call/formal_arguments produced unexpected # results!"); // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to // remember that we legalized all of them, so it doesn't get relegalized. - for (unsigned i = 0, e = Result.Val->getNumValues(); i != e; ++i) { - Tmp1 = LegalizeOp(Result.getValue(i)); + for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) { + Tmp1 = LegalizeOp(Tmp3.getValue(i)); if (Op.ResNo == i) Tmp2 = Tmp1; AddLegalizedOperand(SDOperand(Node, i), Tmp1); @@ -1056,8 +1058,10 @@ // Merge in the last call, to ensure that this call start after the last // call ended. - Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); - Tmp1 = LegalizeOp(Tmp1); + if (LastCALLSEQ_END.getOpcode() != ISD::EntryNode) { + Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); + Tmp1 = LegalizeOp(Tmp1); + } // Do not try to legalize the target-specific arguments (#1+). if (Tmp1 != Node->getOperand(0)) { From lattner at cs.uiuc.edu Wed May 17 13:00:20 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 17 May 2006 13:00:20 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <200605171800.NAA29266@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.376 -> 1.377 --- Log message: When we legalize target nodes, do not use getNode to create a new node, use UpdateNodeOperands to just update the operands! This is important because getNode will allocate a new node if the node returns a flag and this breaks assumptions in the legalizer that you can legalize some things multiple times and get exactly the same results. This latent bug was exposed by my ppc patch last night, and this fixes gsm/toast. --- Diffs of the changes: (+4 -13) LegalizeDAG.cpp | 17 ++++------------- 1 files changed, 4 insertions(+), 13 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.376 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.377 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.376 Wed May 17 12:55:45 2006 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed May 17 13:00:08 2006 @@ -529,19 +529,10 @@ // If this is a target node, legalize it by legalizing the operands then // passing it through. std::vector Ops; - bool Changed = false; - for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { + for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) Ops.push_back(LegalizeOp(Node->getOperand(i))); - Changed = Changed || Node->getOperand(i) != Ops.back(); - } - if (Changed) - if (Node->getNumValues() == 1) - Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Ops); - else { - std::vector VTs(Node->value_begin(), - Node->value_end()); - Result = DAG.getNode(Node->getOpcode(), VTs, Ops); - } + + Result = DAG.UpdateNodeOperands(Result.getValue(0), Ops); for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); @@ -1058,7 +1049,7 @@ // Merge in the last call, to ensure that this call start after the last // call ended. - if (LastCALLSEQ_END.getOpcode() != ISD::EntryNode) { + if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); Tmp1 = LegalizeOp(Tmp1); } From lattner at cs.uiuc.edu Wed May 17 13:05:47 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 17 May 2006 13:05:47 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Transforms/Utils/Cloning.h Message-ID: <200605171805.NAA29352@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/Transforms/Utils: Cloning.h updated: 1.18 -> 1.19 --- Log message: Add a CloneModule call that exposes the mapping of values from the old module to the new module. Patch provided by Nick Lewycky! --- Diffs of the changes: (+1 -0) Cloning.h | 1 + 1 files changed, 1 insertion(+) Index: llvm/include/llvm/Transforms/Utils/Cloning.h diff -u llvm/include/llvm/Transforms/Utils/Cloning.h:1.18 llvm/include/llvm/Transforms/Utils/Cloning.h:1.19 --- llvm/include/llvm/Transforms/Utils/Cloning.h:1.18 Sat Jan 14 14:05:06 2006 +++ llvm/include/llvm/Transforms/Utils/Cloning.h Wed May 17 13:05:35 2006 @@ -37,6 +37,7 @@ /// CloneModule - Return an exact copy of the specified module /// Module *CloneModule(const Module *M); +Module *CloneModule(const Module *M, std::map &ValueMap); /// ClonedCodeInfo - This struct can be used to capture information about code /// being cloned, while it is being cloned. From lattner at cs.uiuc.edu Wed May 17 13:05:48 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 17 May 2006 13:05:48 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Utils/CloneModule.cpp Message-ID: <200605171805.NAA29356@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Utils: CloneModule.cpp updated: 1.17 -> 1.18 --- Log message: Add a CloneModule call that exposes the mapping of values from the old module to the new module. Patch provided by Nick Lewycky! --- Diffs of the changes: (+8 -4) CloneModule.cpp | 12 ++++++++---- 1 files changed, 8 insertions(+), 4 deletions(-) Index: llvm/lib/Transforms/Utils/CloneModule.cpp diff -u llvm/lib/Transforms/Utils/CloneModule.cpp:1.17 llvm/lib/Transforms/Utils/CloneModule.cpp:1.18 --- llvm/lib/Transforms/Utils/CloneModule.cpp:1.17 Mon Jan 23 22:16:34 2006 +++ llvm/lib/Transforms/Utils/CloneModule.cpp Wed May 17 13:05:35 2006 @@ -26,6 +26,14 @@ /// respectively) refer to the right globals. /// Module *llvm::CloneModule(const Module *M) { + // Create the value map that maps things from the old module over to the new + // module. + std::map ValueMap; + + return CloneModule(M, ValueMap); +} + +Module *llvm::CloneModule(const Module *M, std::map &ValueMap) { // First off, we need to create the new module... Module *New = new Module(M->getModuleIdentifier()); New->setEndianness(M->getEndianness()); @@ -44,10 +52,6 @@ for (Module::lib_iterator I = M->lib_begin(), E = M->lib_end(); I != E; ++I) New->addLibrary(*I); - // Create the value map that maps things from the old module over to the new - // module. - std::map ValueMap; - // Loop over all of the global variables, making corresponding globals in the // new module. Here we add them to the ValueMap and to the new Module. We // don't worry about attributes or initializers, they will come later. From evan.cheng at apple.com Wed May 17 13:08:32 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 17 May 2006 13:08:32 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetLowering.h Message-ID: <200605171808.NAA29392@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/Target: TargetLowering.h updated: 1.73 -> 1.74 --- Log message: Fix a mis-leading comment. --- Diffs of the changes: (+1 -1) TargetLowering.h | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/include/llvm/Target/TargetLowering.h diff -u llvm/include/llvm/Target/TargetLowering.h:1.73 llvm/include/llvm/Target/TargetLowering.h:1.74 --- llvm/include/llvm/Target/TargetLowering.h:1.73 Tue May 16 17:52:11 2006 +++ llvm/include/llvm/Target/TargetLowering.h Wed May 17 13:08:20 2006 @@ -173,7 +173,7 @@ } /// getPackedTypeBreakdown - Packed types are broken down into some number of - /// legal scalar types. For example, <8 x float> maps to 2 MVT::v2f32 values + /// legal first class types. For example, <8 x float> maps to 2 MVT::v2f32 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. /// Similarly, <2 x long> turns into 4 MVT::i32 values with both PPC and X86. /// From evan.cheng at apple.com Wed May 17 13:10:18 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 17 May 2006 13:10:18 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp Message-ID: <200605171810.NAA29420@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target: TargetLowering.cpp updated: 1.64 -> 1.65 --- Log message: Fix an obvious bug in getPackedTypeBreakdown. Return 1 if type is legal. --- Diffs of the changes: (+2 -2) TargetLowering.cpp | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/Target/TargetLowering.cpp diff -u llvm/lib/Target/TargetLowering.cpp:1.64 llvm/lib/Target/TargetLowering.cpp:1.65 --- llvm/lib/Target/TargetLowering.cpp:1.64 Tue May 16 12:45:23 2006 +++ llvm/lib/Target/TargetLowering.cpp Wed May 17 13:10:06 2006 @@ -144,7 +144,7 @@ } /// getPackedTypeBreakdown - Packed types are broken down into some number of -/// legal scalar types. For example, <8 x float> maps to 2 MVT::v2f32 values +/// legal first class types. For example, <8 x float> maps to 2 MVT::v2f32 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. /// /// This method returns the number and type of the resultant breakdown. @@ -184,7 +184,7 @@ return NumVectorRegs; } - return DestVT; + return 1; } //===----------------------------------------------------------------------===// From evan.cheng at apple.com Wed May 17 13:16:51 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 17 May 2006 13:16:51 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Message-ID: <200605171816.NAA29472@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAGISel.cpp updated: 1.244 -> 1.245 --- Log message: Fixed a LowerCallTo and LowerArguments bug. They were introducing illegal VBIT_VECTOR nodes. There were some confusion about the semantics of getPackedTypeBreakdown(). e.g. for <4 x f32> it returns 1 and v4f32, not 4, and f32. --- Diffs of the changes: (+27 -12) SelectionDAGISel.cpp | 39 +++++++++++++++++++++++++++------------ 1 files changed, 27 insertions(+), 12 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.244 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.245 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.244 Tue May 16 18:39:44 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed May 17 13:16:39 2006 @@ -2455,20 +2455,25 @@ // Figure out if there is a Packed type corresponding to this Vector // type. If so, convert to the packed type. + bool Supported = false; MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems); - if (TVT != MVT::Other && isTypeLegal(TVT)) { + if (TVT != MVT::Other) { SDOperand N = SDOperand(Result, i++); // Handle copies from generic vectors to registers. MVT::ValueType PTyElementVT, PTyLegalElementVT; unsigned NE = getPackedTypeBreakdown(PTy, PTyElementVT, PTyLegalElementVT); - // Insert a VBIT_CONVERT of the FORMAL_ARGUMENTS to a - // "N x PTyElementVT" MVT::Vector type. - N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N, - DAG.getConstant(NE, MVT::i32), - DAG.getValueType(PTyElementVT)); - Ops.push_back(N); - } else { + // FIXME: handle NE > 1 cases. + if (NE == 1) { + N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N, + DAG.getConstant(NumElems, MVT::i32), + DAG.getValueType(getValueType(EltTy))); + Ops.push_back(N); + Supported = true; + } + } + + if (!Supported) { assert(0 && "Don't support illegal by-val vector arguments yet!"); abort(); } @@ -2546,15 +2551,25 @@ // Figure out if there is a Packed type corresponding to this Vector // type. If so, convert to the packed type. + bool Supported = false; MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems); - if (TVT != MVT::Other && isTypeLegal(TVT)) { + if (TVT != MVT::Other) { // Handle copies from generic vectors to registers. MVT::ValueType PTyElementVT, PTyLegalElementVT; unsigned NE = getPackedTypeBreakdown(PTy, PTyElementVT, PTyLegalElementVT); - // Insert a VBIT_CONVERT of the MVT::Vector type to the packed type. - Ops.push_back(DAG.getNode(ISD::VBIT_CONVERT, TVT, Op)); - } else { + // FIXME: handle NE > 1 cases. + if (NE == 1) { + // Insert a VBIT_CONVERT of the MVT::Vector type to the packed type. + Op = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Op, + DAG.getConstant(NumElems, MVT::i32), + DAG.getValueType(getValueType(EltTy))); + Ops.push_back(Op); + Supported = true; + } + } + + if (!Supported) { assert(0 && "Don't support illegal by-val vector call args yet!"); abort(); } From evan.cheng at apple.com Wed May 17 13:22:27 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 17 May 2006 13:22:27 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp Message-ID: <200605171822.NAA29522@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target: TargetLowering.cpp updated: 1.65 -> 1.66 --- Log message: Another typo. Pointed out by Nate Begeman. --- Diffs of the changes: (+1 -1) TargetLowering.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/TargetLowering.cpp diff -u llvm/lib/Target/TargetLowering.cpp:1.65 llvm/lib/Target/TargetLowering.cpp:1.66 --- llvm/lib/Target/TargetLowering.cpp:1.65 Wed May 17 13:10:06 2006 +++ llvm/lib/Target/TargetLowering.cpp Wed May 17 13:22:14 2006 @@ -144,7 +144,7 @@ } /// getPackedTypeBreakdown - Packed types are broken down into some number of -/// legal first class types. For example, <8 x float> maps to 2 MVT::v2f32 +/// legal first class types. For example, <8 x float> maps to 2 MVT::v4f32 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. /// /// This method returns the number and type of the resultant breakdown. From evan.cheng at apple.com Wed May 17 13:22:27 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 17 May 2006 13:22:27 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetLowering.h Message-ID: <200605171822.NAA29526@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/Target: TargetLowering.h updated: 1.74 -> 1.75 --- Log message: Another typo. Pointed out by Nate Begeman. --- Diffs of the changes: (+1 -1) TargetLowering.h | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/include/llvm/Target/TargetLowering.h diff -u llvm/include/llvm/Target/TargetLowering.h:1.74 llvm/include/llvm/Target/TargetLowering.h:1.75 --- llvm/include/llvm/Target/TargetLowering.h:1.74 Wed May 17 13:08:20 2006 +++ llvm/include/llvm/Target/TargetLowering.h Wed May 17 13:22:14 2006 @@ -173,7 +173,7 @@ } /// getPackedTypeBreakdown - Packed types are broken down into some number of - /// legal first class types. For example, <8 x float> maps to 2 MVT::v2f32 + /// legal first class types. For example, <8 x float> maps to 2 MVT::v4f32 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. /// Similarly, <2 x long> turns into 4 MVT::i32 values with both PPC and X86. /// From lattner at cs.uiuc.edu Wed May 17 14:00:58 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 17 May 2006 14:00:58 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp PPCISelLowering.cpp PPCISelLowering.h PPCInstrInfo.td Message-ID: <200605171900.OAA29866@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelDAGToDAG.cpp updated: 1.186 -> 1.187 PPCISelLowering.cpp updated: 1.179 -> 1.180 PPCISelLowering.h updated: 1.49 -> 1.50 PPCInstrInfo.td updated: 1.219 -> 1.220 --- Log message: Make PPC call lowering more aggressive, making the isel matching code simple enough to be autogenerated. --- Diffs of the changes: (+98 -84) PPCISelDAGToDAG.cpp | 64 ---------------------------------------- PPCISelLowering.cpp | 83 ++++++++++++++++++++++++++++++++++++++++++++-------- PPCISelLowering.h | 10 +++++- PPCInstrInfo.td | 25 +++++++++++---- 4 files changed, 98 insertions(+), 84 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.186 llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.187 --- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.186 Wed May 17 01:01:33 2006 +++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Wed May 17 14:00:46 2006 @@ -152,7 +152,6 @@ private: SDOperand SelectSETCC(SDOperand Op); - SDOperand SelectCALL(SDOperand Op); }; } @@ -864,66 +863,6 @@ } } -/// isCallCompatibleAddress - Return true if the specified 32-bit value is -/// representable in the immediate field of a Bx instruction. -static bool isCallCompatibleAddress(ConstantSDNode *C) { - int Addr = C->getValue(); - if (Addr & 3) return false; // Low 2 bits are implicitly zero. - return (Addr << 6 >> 6) == Addr; // Top 6 bits have to be sext of immediate. -} - -SDOperand PPCDAGToDAGISel::SelectCALL(SDOperand Op) { - SDNode *N = Op.Val; - SDOperand Chain, Flag; - Select(Chain, N->getOperand(0)); - if (N->getNumOperands() == 3) // input flag - Select(Flag, N->getOperand(2)); - - unsigned CallOpcode; - - std::vector CallArgs; - if (GlobalAddressSDNode *GASD = - dyn_cast(N->getOperand(1))) { - CallOpcode = PPC::BL; - CallArgs.push_back(N->getOperand(1)); - } else if (ExternalSymbolSDNode *ESSDN = - dyn_cast(N->getOperand(1))) { - CallOpcode = PPC::BL; - CallArgs.push_back(N->getOperand(1)); - } else if (isa(N->getOperand(1)) && - isCallCompatibleAddress(cast(N->getOperand(1)))) { - ConstantSDNode *C = cast(N->getOperand(1)); - CallOpcode = PPC::BLA; - CallArgs.push_back(getI32Imm((int)C->getValue() >> 2)); - } else { - // Copy the callee address into the CTR register. - SDOperand Callee; - Select(Callee, N->getOperand(1)); - if (Flag.Val) - Chain = SDOperand(CurDAG->getTargetNode(PPC::MTCTR, MVT::Other, MVT::Flag, - Callee, Chain, Flag), 0); - else - Chain = SDOperand(CurDAG->getTargetNode(PPC::MTCTR, MVT::Other, MVT::Flag, - Callee, Chain), 0); - Flag = Chain.getValue(1); - - // Copy the callee address into R12 on darwin. - Chain = CurDAG->getCopyToReg(Chain, PPC::R12, Callee, Flag); - Flag = Chain.getValue(1); - - CallOpcode = PPC::BCTRL; - } - - // Emit the call itself. - CallArgs.push_back(Chain); - if (Flag.Val) - CallArgs.push_back(Flag); - Chain = SDOperand(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag, - CallArgs), 0); - CodeGenMap[Op.getValue(0)] = Chain; - CodeGenMap[Op.getValue(1)] = Chain.getValue(1); - return Chain.getValue(Op.ResNo); -} // Select - Convert the specified operand from a target-independent to a // target-specific node if it hasn't already been changed. @@ -947,9 +886,6 @@ case ISD::SETCC: Result = SelectSETCC(Op); return; - case PPCISD::CALL: - Result = SelectCALL(Op); - return; case PPCISD::GlobalBaseReg: Result = getGlobalBaseReg(); return; Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.179 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.180 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.179 Wed May 17 01:01:33 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Wed May 17 14:00:46 2006 @@ -276,6 +276,8 @@ case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32"; case PPCISD::STD_32: return "PPCISD::STD_32"; case PPCISD::CALL: return "PPCISD::CALL"; + case PPCISD::MTCTR: return "PPCISD::MTCTR"; + case PPCISD::BCTRL: return "PPCISD::BCTRL"; case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG"; case PPCISD::MFCR: return "PPCISD::MFCR"; case PPCISD::VCMP: return "PPCISD::VCMP"; @@ -877,6 +879,21 @@ return DAG.getNode(ISD::MERGE_VALUES, RetVT, ArgValues); } +/// isCallCompatibleAddress - Return the immediate to use if the specified +/// 32-bit value is representable in the immediate field of a BxA instruction. +static SDNode *isBLACompatibleAddress(SDOperand Op, SelectionDAG &DAG) { + ConstantSDNode *C = dyn_cast(Op); + if (!C) return 0; + + int Addr = C->getValue(); + if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero. + (Addr << 6 >> 6) != Addr) + return 0; // Top 6 bits have to be sext of immediate. + + return DAG.getConstant((int)C->getValue() >> 2, MVT::i32).Val; +} + + static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) { SDOperand Chain = Op.getOperand(0); unsigned CallingConv= cast(Op.getOperand(1))->getValue(); @@ -1026,22 +1043,59 @@ InFlag = Chain.getValue(1); } - // If the callee is a GlobalAddress node (quite common, every direct call is) - // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. + std::vector NodeTys; + + // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every + // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol + // node so that legalize doesn't hack it. if (GlobalAddressSDNode *G = dyn_cast(Callee)) Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType()); + else if (ExternalSymbolSDNode *S = dyn_cast(Callee)) + Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType()); + else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) + // If this is an absolute destination address, use the munged value. + Callee = SDOperand(Dest, 0); + else { + // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair + // to do the call, we can't use PPCISD::CALL. + std::vector Ops; + Ops.push_back(Chain); + Ops.push_back(Callee); + NodeTys.push_back(MVT::Other); + NodeTys.push_back(MVT::Flag); + + if (InFlag.Val) + Ops.push_back(InFlag); + Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, Ops); + InFlag = Chain.getValue(1); + + // Copy the callee address into R12 on darwin. + Chain = DAG.getCopyToReg(Chain, PPC::R12, Callee, InFlag); + InFlag = Chain.getValue(1); - // Create the PPCISD::CALL node itself. - std::vector NodeTys; - NodeTys.push_back(MVT::Other); // Returns a chain - NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. - std::vector Ops; - Ops.push_back(Chain); - Ops.push_back(Callee); - if (InFlag.Val) + NodeTys.clear(); + NodeTys.push_back(MVT::Other); + NodeTys.push_back(MVT::Flag); + Ops.clear(); + Ops.push_back(Chain); Ops.push_back(InFlag); - Chain = DAG.getNode(PPCISD::CALL, NodeTys, Ops); - InFlag = Chain.getValue(1); + Chain = DAG.getNode(PPCISD::BCTRL, NodeTys, Ops); + InFlag = Chain.getValue(1); + Callee.Val = 0; + } + + // Create the PPCISD::CALL node itself. + if (Callee.Val) { + NodeTys.push_back(MVT::Other); // Returns a chain + NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. + std::vector Ops; + Ops.push_back(Chain); + Ops.push_back(Callee); + if (InFlag.Val) + Ops.push_back(InFlag); + Chain = DAG.getNode(PPCISD::CALL, NodeTys, Ops); + InFlag = Chain.getValue(1); + } std::vector ResultVals; NodeTys.clear(); @@ -1086,6 +1140,11 @@ DAG.getConstant(NumBytes, MVT::i32)); NodeTys.push_back(MVT::Other); + // If the function returns void, just return the chain. + if (ResultVals.empty()) + return Chain; + + // Otherwise, merge everything together with a MERGE_VALUES node. ResultVals.push_back(Chain); SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, ResultVals); return Res.getValue(Op.ResNo); Index: llvm/lib/Target/PowerPC/PPCISelLowering.h diff -u llvm/lib/Target/PowerPC/PPCISelLowering.h:1.49 llvm/lib/Target/PowerPC/PPCISelLowering.h:1.50 --- llvm/lib/Target/PowerPC/PPCISelLowering.h:1.49 Tue May 16 17:56:08 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.h Wed May 17 14:00:46 2006 @@ -75,9 +75,17 @@ /// STD_32 - This is the STD instruction for use with "32-bit" registers. STD_32, - /// CALL - A function call. + /// CALL - A direct function call. CALL, + /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a + /// MTCTR instruction. + MTCTR, + + /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a + /// BCTRL instruction. + BCTRL, + /// Return with a flag operand, matched by 'blr' RET_FLAG, Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.219 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.220 --- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.219 Wed May 17 01:01:33 2006 +++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Wed May 17 14:00:46 2006 @@ -24,7 +24,6 @@ SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32> ]>; def SDT_PPCCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>; -def SDT_PPCRetFlag : SDTypeProfile<0, 0, []>; def SDT_PPCvperm : SDTypeProfile<1, 3, [ SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2> @@ -73,10 +72,14 @@ def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeq,[SDNPHasChain]>; def SDT_PPCCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; -def call : SDNode<"PPCISD::CALL", SDT_PPCCall, +def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall, [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; +def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall, + [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; +def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTRet, + [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; -def retflag : SDNode<"PPCISD::RET_FLAG", SDT_PPCRetFlag, +def retflag : SDNode<"PPCISD::RET_FLAG", SDTRet, [SDNPHasChain, SDNPOptInFlag]>; def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>; @@ -308,11 +311,11 @@ CR0,CR1,CR5,CR6,CR7] in { // Convenient aliases for call instructions def BL : IForm<18, 0, 1, (ops calltarget:$func), - "bl $func", BrB, []>; + "bl $func", BrB, []>; // See Pat patterns below. def BLA : IForm<18, 1, 1, (ops aaddr:$func), - "bla $func", BrB, []>; + "bla $func", BrB, [(PPCcall imm:$func)]>; def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (ops), "bctrl", BrB, - []>; + [(PPCbctrl)]>; } // D-Form instructions. Most instructions that perform an operation on a @@ -701,8 +704,10 @@ // def MFCTR : XFXForm_1_ext<31, 339, 9, (ops GPRC:$rT), "mfctr $rT", SprMFSPR>, PPC970_DGroup_First, PPC970_Unit_FXU; +let Pattern = [(PPCmtctr GPRC:$rS)] in { def MTCTR : XFXForm_7_ext<31, 467, 9, (ops GPRC:$rS), "mtctr $rS", SprMTSPR>, PPC970_DGroup_First, PPC970_Unit_FXU; +} def MTLR : XFXForm_7_ext<31, 467, 8, (ops GPRC:$rS), "mtlr $rS", SprMTSPR>, PPC970_DGroup_First, PPC970_Unit_FXU; @@ -1013,7 +1018,13 @@ (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>; def : Pat<(rotl GPRC:$in, (i32 imm:$imm)), (RLWINM GPRC:$in, imm:$imm, 0, 31)>; - + +// Calls +def : Pat<(PPCcall tglobaladdr:$dst), + (BL tglobaladdr:$dst)>; +def : Pat<(PPCcall texternalsym:$dst), + (BL texternalsym:$dst)>; + // Hi and Lo for Darwin Global Addresses. def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>; def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>; From lattner at cs.uiuc.edu Wed May 17 14:02:38 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 17 May 2006 14:02:38 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/README.txt Message-ID: <200605171902.OAA29909@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: README.txt updated: 1.91 -> 1.92 --- Log message: Add a note about a note --- Diffs of the changes: (+4 -0) README.txt | 4 ++++ 1 files changed, 4 insertions(+) Index: llvm/lib/Target/PowerPC/README.txt diff -u llvm/lib/Target/PowerPC/README.txt:1.91 llvm/lib/Target/PowerPC/README.txt:1.92 --- llvm/lib/Target/PowerPC/README.txt:1.91 Mon May 8 15:54:02 2006 +++ llvm/lib/Target/PowerPC/README.txt Wed May 17 14:02:25 2006 @@ -490,6 +490,10 @@ // need to flag these together so that the value isn't live across a call. //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); +Also, if the registers are spilled to the stack, we have to ensure that all +64-bits of them are save/restored, otherwise we will miscompile the code. It +sounds like we need to get the 64-bit register classes going. + ===-------------------------------------------------------------------------=== %struct.B = type { ubyte, [3 x ubyte] } From evan.cheng at apple.com Wed May 17 14:05:43 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 17 May 2006 14:05:43 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/README.txt Message-ID: <200605171905.OAA29956@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: README.txt updated: 1.104 -> 1.105 --- Log message: Another entry --- Diffs of the changes: (+12 -0) README.txt | 12 ++++++++++++ 1 files changed, 12 insertions(+) Index: llvm/lib/Target/X86/README.txt diff -u llvm/lib/Target/X86/README.txt:1.104 llvm/lib/Target/X86/README.txt:1.105 --- llvm/lib/Target/X86/README.txt:1.104 Tue May 9 01:54:05 2006 +++ llvm/lib/Target/X86/README.txt Wed May 17 14:05:31 2006 @@ -1171,3 +1171,15 @@ ret or use pxor (to make a zero vector) and shuffle (to insert it). + +//===---------------------------------------------------------------------===// + +Bad codegen: + +char foo(int x) { return x; } + +_foo: + movl 4(%esp), %eax + shll $24, %eax + sarl $24, %eax + ret From evan.cheng at apple.com Wed May 17 14:07:52 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 17 May 2006 14:07:52 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h Message-ID: <200605171907.OAA29985@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.205 -> 1.206 X86ISelLowering.h updated: 1.61 -> 1.62 --- Log message: Should pass by reference. --- Diffs of the changes: (+4 -4) X86ISelLowering.cpp | 4 ++-- X86ISelLowering.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.205 llvm/lib/Target/X86/X86ISelLowering.cpp:1.206 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.205 Tue May 16 12:14:26 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Wed May 17 14:07:40 2006 @@ -461,7 +461,7 @@ return Objs; } -void X86TargetLowering::PreprocessCCCArguments(std::vectorArgs, +void X86TargetLowering::PreprocessCCCArguments(std::vector &Args, Function &F, SelectionDAG &DAG) { unsigned NumArgs = Args.size(); MachineFunction &MF = DAG.getMachineFunction(); @@ -895,7 +895,7 @@ } void -X86TargetLowering::PreprocessFastCCArguments(std::vectorArgs, +X86TargetLowering::PreprocessFastCCArguments(std::vector &Args, Function &F, SelectionDAG &DAG) { unsigned NumArgs = Args.size(); MachineFunction &MF = DAG.getMachineFunction(); Index: llvm/lib/Target/X86/X86ISelLowering.h diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.61 llvm/lib/Target/X86/X86ISelLowering.h:1.62 --- llvm/lib/Target/X86/X86ISelLowering.h:1.61 Wed Apr 26 20:32:22 2006 +++ llvm/lib/Target/X86/X86ISelLowering.h Wed May 17 14:07:40 2006 @@ -369,7 +369,7 @@ std::vector > FormalArgLocs; // C Calling Convention implementation. - void PreprocessCCCArguments(std::vectorArgs, Function &F, + void PreprocessCCCArguments(std::vector &Args, Function &F, SelectionDAG &DAG); void LowerCCCArguments(SDOperand Op, SelectionDAG &DAG); std::pair @@ -379,7 +379,7 @@ // Fast Calling Convention implementation. void - PreprocessFastCCArguments(std::vectorArgs, Function &F, + PreprocessFastCCArguments(std::vector &Args, Function &F, SelectionDAG &DAG); void LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG); From alenhar2 at cs.uiuc.edu Wed May 17 14:23:43 2006 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Wed, 17 May 2006 14:23:43 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/Alpha/call_adj.ll Message-ID: <200605171923.OAA30888@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/Alpha: call_adj.ll added (r1.1) --- Log message: Added regression that breaks gcc4 build --- Diffs of the changes: (+15 -0) call_adj.ll | 15 +++++++++++++++ 1 files changed, 15 insertions(+) Index: llvm/test/Regression/CodeGen/Alpha/call_adj.ll diff -c /dev/null llvm/test/Regression/CodeGen/Alpha/call_adj.ll:1.1 *** /dev/null Wed May 17 14:23:41 2006 --- llvm/test/Regression/CodeGen/Alpha/call_adj.ll Wed May 17 14:23:31 2006 *************** *** 0 **** --- 1,15 ---- + ;All this should do is not crash + ;RUN: llvm-as < %s | llc -march=alpha + + target endian = little + target pointersize = 64 + target triple = "alphaev67-unknown-linux-gnu" + + implementation ; Functions: + + void %_ZNSt13basic_filebufIcSt11char_traitsIcEE22_M_convert_to_externalEPcl(uint %f) { + entry: + %tmp49 = alloca sbyte, uint %f ; [#uses=1] + %tmp = call uint null( sbyte* null, sbyte* null, sbyte* null, sbyte* null, sbyte* null, sbyte* null, sbyte* null) + ret void + } From alenhar2 at cs.uiuc.edu Wed May 17 14:24:44 2006 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Wed, 17 May 2006 14:24:44 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp Message-ID: <200605171924.OAA31005@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Alpha: AlphaAsmPrinter.cpp updated: 1.42 -> 1.43 --- Log message: Added sanity check for obviously bogus immediates --- Diffs of the changes: (+1 -0) AlphaAsmPrinter.cpp | 1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp diff -u llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.42 llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.43 --- llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.42 Mon May 8 23:59:56 2006 +++ llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp Wed May 17 14:24:31 2006 @@ -82,6 +82,7 @@ O << TM.getRegisterInfo()->get(MO.getReg()).Name; } else if (MO.isImmediate()) { O << MO.getImmedValue(); + assert(MO.getImmedValue() < (1 << 30)); } else { printOp(MO); } From alenhar2 at cs.uiuc.edu Wed May 17 14:25:01 2006 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Wed, 17 May 2006 14:25:01 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp Message-ID: <200605171925.OAA31059@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Alpha: AlphaRegisterInfo.cpp updated: 1.43 -> 1.44 --- Log message: Fix call_adj.ll --- Diffs of the changes: (+1 -1) AlphaRegisterInfo.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp diff -u llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.43 llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.44 --- llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.43 Thu May 4 12:52:23 2006 +++ llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp Wed May 17 14:24:49 2006 @@ -166,7 +166,7 @@ // 'sub ESP, ' and the adjcallstackdown instruction into 'add ESP, // ' MachineInstr *Old = I; - unsigned Amount = Old->getOperand(0).getImmedValue(); + uint64_t Amount = Old->getOperand(0).getImmedValue(); if (Amount != 0) { // We need to keep the stack aligned properly. To do this, we round the // amount of space needed for the outgoing arguments up to the next From evan.cheng at apple.com Wed May 17 15:20:18 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 17 May 2006 15:20:18 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/X86/2006-05-17-VectorArg.ll Message-ID: <200605172020.PAA31974@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CodeGen/X86: 2006-05-17-VectorArg.ll added (r1.1) --- Log message: New test case for vector type argument pass by value. --- Diffs of the changes: (+14 -0) 2006-05-17-VectorArg.ll | 14 ++++++++++++++ 1 files changed, 14 insertions(+) Index: llvm/test/Regression/CodeGen/X86/2006-05-17-VectorArg.ll diff -c /dev/null llvm/test/Regression/CodeGen/X86/2006-05-17-VectorArg.ll:1.1 *** /dev/null Wed May 17 15:20:14 2006 --- llvm/test/Regression/CodeGen/X86/2006-05-17-VectorArg.ll Wed May 17 15:20:04 2006 *************** *** 0 **** --- 1,14 ---- + ; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 + + <4 x float> %opRSQ(<4 x float> %a) { + entry: + %tmp2 = extractelement <4 x float> %a, uint 3 + %abscond = setge float %tmp2, -0.000000e+00 + %abs = select bool %abscond, float %tmp2, float 0.000000e+00 + %tmp3 = tail call float %llvm.sqrt.f32( float %abs ) + %tmp4 = div float 1.000000e+00, %tmp3 + %tmp11 = insertelement <4 x float> zeroinitializer, float %tmp4, uint 3 + ret <4 x float> %tmp11 + } + + declare float %llvm.sqrt.f32(float) From evan.cheng at apple.com Wed May 17 15:21:56 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 17 May 2006 15:21:56 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/ExecutionEngine/2005-12-02-TailCallBug.ll Message-ID: <200605172021.PAA31994@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/ExecutionEngine: 2005-12-02-TailCallBug.ll updated: 1.3 -> 1.4 --- Log message: PR736: http://llvm.cs.uiuc.edu/PR736 has already been fixed. Remove XFAIL marker. --- Diffs of the changes: (+0 -3) 2005-12-02-TailCallBug.ll | 3 --- 1 files changed, 3 deletions(-) Index: llvm/test/Regression/ExecutionEngine/2005-12-02-TailCallBug.ll diff -u llvm/test/Regression/ExecutionEngine/2005-12-02-TailCallBug.ll:1.3 llvm/test/Regression/ExecutionEngine/2005-12-02-TailCallBug.ll:1.4 --- llvm/test/Regression/ExecutionEngine/2005-12-02-TailCallBug.ll:1.3 Thu Apr 13 13:15:24 2006 +++ llvm/test/Regression/ExecutionEngine/2005-12-02-TailCallBug.ll Wed May 17 15:21:44 2006 @@ -1,9 +1,6 @@ ; PR672 ; RUN: llvm-as < %s | lli -; This doesn't work on darwin/x86, xfail until PR736 is resolved. -; XFAIL: i686-apple-darwin - int %main(){ %f = cast int (int, int*, int)* %check_tail to int* %res = tail call fastcc int %check_tail( int 10, int* %f,int 10) From evan.cheng at apple.com Wed May 17 15:38:11 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 17 May 2006 15:38:11 -0500 Subject: [llvm-commits] CVS: llvm/utils/TableGen/CodeGenTarget.cpp CodeGenTarget.h DAGISelEmitter.cpp DAGISelEmitter.h Message-ID: <200605172038.PAA32096@zion.cs.uiuc.edu> Changes in directory llvm/utils/TableGen: CodeGenTarget.cpp updated: 1.64 -> 1.65 CodeGenTarget.h updated: 1.26 -> 1.27 DAGISelEmitter.cpp updated: 1.203 -> 1.204 DAGISelEmitter.h updated: 1.63 -> 1.64 --- Log message: Remove PointerType from target definition. Use abstract type MVT::iPTR to represent pointer type. --- Diffs of the changes: (+93 -65) CodeGenTarget.cpp | 58 ++++++++++++++++------------------ CodeGenTarget.h | 3 - DAGISelEmitter.cpp | 88 +++++++++++++++++++++++++++++++++++------------------ DAGISelEmitter.h | 9 ++++- 4 files changed, 93 insertions(+), 65 deletions(-) Index: llvm/utils/TableGen/CodeGenTarget.cpp diff -u llvm/utils/TableGen/CodeGenTarget.cpp:1.64 llvm/utils/TableGen/CodeGenTarget.cpp:1.65 --- llvm/utils/TableGen/CodeGenTarget.cpp:1.64 Tue May 16 02:05:30 2006 +++ llvm/utils/TableGen/CodeGenTarget.cpp Wed May 17 15:37:59 2006 @@ -30,12 +30,7 @@ /// getValueType - Return the MCV::ValueType that the specified TableGen record /// corresponds to. MVT::ValueType llvm::getValueType(Record *Rec, const CodeGenTarget *CGT) { - MVT::ValueType VT = (MVT::ValueType)Rec->getValueAsInt("Value"); - if (VT == MVT::iPTR) { - assert(CGT && "Use a pointer type in a place that isn't supported yet!"); - VT = CGT->getPointerType(); - } - return VT; + return (MVT::ValueType)Rec->getValueAsInt("Value"); } std::string llvm::getName(MVT::ValueType T) { @@ -63,35 +58,37 @@ case MVT::v2f32: return "v2f32"; case MVT::v4f32: return "v4f32"; case MVT::v2f64: return "v2f64"; + case MVT::iPTR: return "TLI.getPointetTy()"; default: assert(0 && "ILLEGAL VALUE TYPE!"); return ""; } } std::string llvm::getEnumName(MVT::ValueType T) { switch (T) { - case MVT::Other: return "Other"; - case MVT::i1: return "i1"; - case MVT::i8: return "i8"; - case MVT::i16: return "i16"; - case MVT::i32: return "i32"; - case MVT::i64: return "i64"; - case MVT::i128: return "i128"; - case MVT::f32: return "f32"; - case MVT::f64: return "f64"; - case MVT::f80: return "f80"; - case MVT::f128: return "f128"; - case MVT::Flag: return "Flag"; - case MVT::isVoid:return "isVoid"; - case MVT::v8i8: return "v8i8"; - case MVT::v4i16: return "v4i16"; - case MVT::v2i32: return "v2i32"; - case MVT::v16i8: return "v16i8"; - case MVT::v8i16: return "v8i16"; - case MVT::v4i32: return "v4i32"; - case MVT::v2i64: return "v2i64"; - case MVT::v2f32: return "v2f32"; - case MVT::v4f32: return "v4f32"; - case MVT::v2f64: return "v2f64"; + case MVT::Other: return "MVT::Other"; + case MVT::i1: return "MVT::i1"; + case MVT::i8: return "MVT::i8"; + case MVT::i16: return "MVT::i16"; + case MVT::i32: return "MVT::i32"; + case MVT::i64: return "MVT::i64"; + case MVT::i128: return "MVT::i128"; + case MVT::f32: return "MVT::f32"; + case MVT::f64: return "MVT::f64"; + case MVT::f80: return "MVT::f80"; + case MVT::f128: return "MVT::f128"; + case MVT::Flag: return "MVT::Flag"; + case MVT::isVoid:return "MVT::isVoid"; + case MVT::v8i8: return "MVT::v8i8"; + case MVT::v4i16: return "MVT::v4i16"; + case MVT::v2i32: return "MVT::v2i32"; + case MVT::v16i8: return "MVT::v16i8"; + case MVT::v8i16: return "MVT::v8i16"; + case MVT::v4i32: return "MVT::v4i32"; + case MVT::v2i64: return "MVT::v2i64"; + case MVT::v2f32: return "MVT::v2f32"; + case MVT::v4f32: return "MVT::v4f32"; + case MVT::v2f64: return "MVT::v2f64"; + case MVT::iPTR: return "TLI.getPointetTy()"; default: assert(0 && "ILLEGAL VALUE TYPE!"); return ""; } } @@ -104,7 +101,7 @@ /// getTarget - Return the current instance of the Target class. /// -CodeGenTarget::CodeGenTarget() : PointerType(MVT::Other) { +CodeGenTarget::CodeGenTarget() { std::vector Targets = Records.getAllDerivedDefinitions("Target"); if (Targets.size() == 0) throw std::string("ERROR: No 'Target' subclasses defined!"); @@ -114,7 +111,6 @@ // Read in all of the CalleeSavedRegisters. CalleeSavedRegisters =TargetRec->getValueAsListOfDefs("CalleeSavedRegisters"); - PointerType = getValueType(TargetRec->getValueAsDef("PointerType")); } Index: llvm/utils/TableGen/CodeGenTarget.h diff -u llvm/utils/TableGen/CodeGenTarget.h:1.26 llvm/utils/TableGen/CodeGenTarget.h:1.27 --- llvm/utils/TableGen/CodeGenTarget.h:1.26 Tue May 16 02:05:30 2006 +++ llvm/utils/TableGen/CodeGenTarget.h Wed May 17 15:37:59 2006 @@ -43,7 +43,6 @@ class CodeGenTarget { Record *TargetRec; std::vector CalleeSavedRegisters; - MVT::ValueType PointerType; mutable std::map Instructions; mutable std::vector Registers; @@ -63,8 +62,6 @@ return CalleeSavedRegisters; } - MVT::ValueType getPointerType() const { return PointerType; } - /// getInstructionSet - Return the InstructionSet object. /// Record *getInstructionSet() const; Index: llvm/utils/TableGen/DAGISelEmitter.cpp diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.203 llvm/utils/TableGen/DAGISelEmitter.cpp:1.204 --- llvm/utils/TableGen/DAGISelEmitter.cpp:1.203 Tue May 16 02:05:30 2006 +++ llvm/utils/TableGen/DAGISelEmitter.cpp Wed May 17 15:37:59 2006 @@ -156,7 +156,7 @@ return NodeToApply->UpdateNodeType(x.SDTCisVT_Info.VT, TP); case SDTCisPtrTy: { // Operand must be same as target pointer type. - return NodeToApply->UpdateNodeType(CGT.getPointerType(), TP); + return NodeToApply->UpdateNodeType(MVT::iPTR, TP); } case SDTCisInt: { // If there is only one integer type supported, this must be it. @@ -346,6 +346,18 @@ setTypes(ExtVTs); return true; } + + if (getExtTypeNum(0) == MVT::iPTR) { + if (ExtVTs[0] == MVT::iPTR || ExtVTs[0] == MVT::isInt) + return false; + if (isExtIntegerInVTs(ExtVTs)) { + std::vector FVTs = FilterEVTs(ExtVTs, MVT::isInteger); + if (FVTs.size()) { + setTypes(ExtVTs); + return true; + } + } + } if (ExtVTs[0] == MVT::isInt && isExtIntegerInVTs(getExtTypes())) { assert(hasTypeSet() && "should be handled above!"); @@ -355,6 +367,16 @@ setTypes(FVTs); return true; } + if (ExtVTs[0] == MVT::iPTR && isExtIntegerInVTs(getExtTypes())) { + //assert(hasTypeSet() && "should be handled above!"); + std::vector FVTs = FilterEVTs(getExtTypes(), MVT::isInteger); + if (getExtTypes() == FVTs) + return false; + if (FVTs.size()) { + setTypes(FVTs); + return true; + } + } if (ExtVTs[0] == MVT::isFP && isExtFloatingPointInVTs(getExtTypes())) { assert(hasTypeSet() && "should be handled above!"); std::vector FVTs = @@ -374,7 +396,11 @@ (getExtTypeNum(0) == MVT::isFP && isExtFloatingPointInVTs(ExtVTs))) { setTypes(ExtVTs); return true; - } + } + if (getExtTypeNum(0) == MVT::isInt && ExtVTs[0] == MVT::iPTR) { + setTypes(ExtVTs); + return true; + } if (isLeaf()) { dump(); @@ -402,6 +428,7 @@ case MVT::isInt: OS << ":isInt"; break; case MVT::isFP : OS << ":isFP"; break; case MVT::isUnknown: ; /*OS << ":?";*/ break; + case MVT::iPTR: OS << ":iPTR"; break; default: OS << ":" << getTypeNum(0); break; } @@ -603,19 +630,22 @@ // At some point, it may make sense for this tree pattern to have // multiple types. Assert here that it does not, so we revisit this // code when appropriate. - assert(getExtTypes().size() >= 1 && "TreePattern does not have a type!"); + assert(getExtTypes().size() >= 1 && "TreePattern doesn't have a type!"); MVT::ValueType VT = getTypeNum(0); for (unsigned i = 1, e = getExtTypes().size(); i != e; ++i) assert(getTypeNum(i) == VT && "TreePattern has too many types!"); - unsigned Size = MVT::getSizeInBits(getTypeNum(0)); - // Make sure that the value is representable for this type. - if (Size < 32) { - int Val = (II->getValue() << (32-Size)) >> (32-Size); - if (Val != II->getValue()) - TP.error("Sign-extended integer value '" + itostr(II->getValue()) + - "' is out of range for type 'MVT::" + - getEnumName(getTypeNum(0)) + "'!"); + VT = getTypeNum(0); + if (VT != MVT::iPTR) { + unsigned Size = MVT::getSizeInBits(VT); + // Make sure that the value is representable for this type. + if (Size < 32) { + int Val = (II->getValue() << (32-Size)) >> (32-Size); + if (Val != II->getValue()) + TP.error("Sign-extended integer value '" + itostr(II->getValue())+ + "' is out of range for type '" + + getEnumName(getTypeNum(0)) + "'!"); + } } } @@ -652,8 +682,7 @@ utostr(getNumChildren()-1) + " operands!"); // Apply type info to the intrinsic ID. - MVT::ValueType PtrTy = ISE.getTargetInfo().getPointerType(); - MadeChange |= getChild(0)->UpdateNodeType(PtrTy, TP); + MadeChange |= getChild(0)->UpdateNodeType(MVT::iPTR, TP); for (unsigned i = 1, e = getNumChildren(); i != e; ++i) { MVT::ValueType OpVT = Int.ArgVTs[i]; @@ -1862,10 +1891,11 @@ /// patterns before small ones. This is used to determine the size of a /// pattern. static unsigned getPatternSize(TreePatternNode *P, DAGISelEmitter &ISE) { - assert(isExtIntegerInVTs(P->getExtTypes()) || - isExtFloatingPointInVTs(P->getExtTypes()) || - P->getExtTypeNum(0) == MVT::isVoid || - P->getExtTypeNum(0) == MVT::Flag && + assert((isExtIntegerInVTs(P->getExtTypes()) || + isExtFloatingPointInVTs(P->getExtTypes()) || + P->getExtTypeNum(0) == MVT::isVoid || + P->getExtTypeNum(0) == MVT::Flag || + P->getExtTypeNum(0) == MVT::iPTR) && "Not a valid pattern node to size!"); unsigned Size = 2; // The node itself. // If the root node is a ConstantSDNode, increases its size. @@ -2340,7 +2370,7 @@ emitDecl("Tmp" + utostr(ResNo)); emitCode("Tmp" + utostr(ResNo) + " = CurDAG->getTargetConstant(Tmp" + utostr(ResNo) + - "C, MVT::" + getEnumName(N->getTypeNum(0)) + ");"); + "C, " + getEnumName(N->getTypeNum(0)) + ");"); } else if (!N->isLeaf() && N->getOperator()->getName() == "texternalsym"){ Record *Op = OperatorMap[N->getName()]; // Transform ExternalSymbol to TargetExternalSymbol @@ -2348,7 +2378,7 @@ emitDecl("Tmp" + utostr(ResNo)); emitCode("Tmp" + utostr(ResNo) + " = CurDAG->getTarget" "ExternalSymbol(cast(" + - Val + ")->getSymbol(), MVT::" + + Val + ")->getSymbol(), " + getEnumName(N->getTypeNum(0)) + ");"); } else { emitDecl("Tmp" + utostr(ResNo)); @@ -2361,7 +2391,7 @@ emitDecl("Tmp" + utostr(ResNo)); emitCode("Tmp" + utostr(ResNo) + " = CurDAG->getTarget" "GlobalAddress(cast(" + Val + - ")->getGlobal(), MVT::" + getEnumName(N->getTypeNum(0)) + + ")->getGlobal(), " + getEnumName(N->getTypeNum(0)) + ");"); } else { emitDecl("Tmp" + utostr(ResNo)); @@ -2420,7 +2450,7 @@ if (DI->getDef()->isSubClassOf("Register")) { emitDecl("Tmp" + utostr(ResNo)); emitCode("Tmp" + utostr(ResNo) + " = CurDAG->getRegister(" + - ISE.getQualifiedName(DI->getDef()) + ", MVT::" + + ISE.getQualifiedName(DI->getDef()) + ", " + getEnumName(N->getTypeNum(0)) + ");"); return std::make_pair(1, ResNo); } @@ -2430,7 +2460,7 @@ emitDecl("Tmp" + utostr(ResNo)); emitCode("Tmp" + utostr(ResNo) + " = CurDAG->getTargetConstant(" + itostr(II->getValue()) + - ", MVT::" + getEnumName(N->getTypeNum(0)) + ");"); + ", " + getEnumName(N->getTypeNum(0)) + ");"); return std::make_pair(1, ResNo); } @@ -2552,7 +2582,7 @@ // Result types. if (PatResults > 0) { if (N->getTypeNum(0) != MVT::isVoid) - Code += ", MVT::" + getEnumName(N->getTypeNum(0)); + Code += ", " + getEnumName(N->getTypeNum(0)); } if (NodeHasChain) Code += ", MVT::Other"; @@ -2572,7 +2602,7 @@ // Output order: results, chain, flags // Result types. if (PatResults > 0 && N->getTypeNum(0) != MVT::isVoid) - Code += ", MVT::" + getEnumName(N->getTypeNum(0)); + Code += ", " + getEnumName(N->getTypeNum(0)); if (NodeHasChain) Code += ", MVT::Other"; if (NodeHasOutFlag) @@ -2606,7 +2636,7 @@ // Output order: results, chain, flags // Result types. if (NumResults > 0 && N->getTypeNum(0) != MVT::isVoid) - Code += ", MVT::" + getEnumName(N->getTypeNum(0)); + Code += ", " + getEnumName(N->getTypeNum(0)); if (NodeHasChain) Code += ", MVT::Other"; if (NodeHasOutFlag) @@ -2717,7 +2747,7 @@ std::string Code = " Result = CurDAG->SelectNodeTo(N.Val, " + II.Namespace + "::" + II.TheDef->getName(); if (N->getTypeNum(0) != MVT::isVoid) - Code += ", MVT::" + getEnumName(N->getTypeNum(0)); + Code += ", " + getEnumName(N->getTypeNum(0)); if (NodeHasOutFlag) Code += ", MVT::Flag"; for (unsigned i = 0, e = Ops.size(); i != e; ++i) @@ -2730,7 +2760,7 @@ Code = " ResNode = CurDAG->getTargetNode(" + II.Namespace + "::" + II.TheDef->getName(); if (N->getTypeNum(0) != MVT::isVoid) - Code += ", MVT::" + getEnumName(N->getTypeNum(0)); + Code += ", " + getEnumName(N->getTypeNum(0)); if (NodeHasOutFlag) Code += ", MVT::Flag"; for (unsigned i = 0, e = Ops.size(); i != e; ++i) @@ -2834,7 +2864,7 @@ RootName + utostr(OpNo) + ");"); emitCode("ResNode = CurDAG->getCopyToReg(" + ChainName + ", CurDAG->getRegister(" + ISE.getQualifiedName(RR) + - ", MVT::" + getEnumName(RVT) + "), " + + ", " + getEnumName(RVT) + "), " + RootName + utostr(OpNo) + ", InFlag).Val;"); emitCode(ChainName + " = SDOperand(ResNode, 0);"); emitCode("InFlag = SDOperand(ResNode, 1);"); @@ -2882,7 +2912,7 @@ ChainName = "Chain"; } emitCode("ResNode = CurDAG->getCopyFromReg(" + ChainName + ", " + - ISE.getQualifiedName(RR) + ", MVT::" + getEnumName(RVT) + + ISE.getQualifiedName(RR) + ", " + getEnumName(RVT) + ", InFlag).Val;"); emitCode(ChainName + " = SDOperand(ResNode, 1);"); emitCode("InFlag = SDOperand(ResNode, 2);"); Index: llvm/utils/TableGen/DAGISelEmitter.h diff -u llvm/utils/TableGen/DAGISelEmitter.h:1.63 llvm/utils/TableGen/DAGISelEmitter.h:1.64 --- llvm/utils/TableGen/DAGISelEmitter.h:1.63 Wed Apr 19 15:36:09 2006 +++ llvm/utils/TableGen/DAGISelEmitter.h Wed May 17 15:37:59 2006 @@ -169,10 +169,15 @@ void setName(const std::string &N) { Name = N; } bool isLeaf() const { return Val != 0; } - bool hasTypeSet() const { return Types[0] < MVT::LAST_VALUETYPE; } + bool hasTypeSet() const { + return (Types[0] < MVT::LAST_VALUETYPE) || (Types[0] == MVT::iPTR); + } bool isTypeCompletelyUnknown() const { return Types[0] == MVT::isUnknown; } + bool isTypeDynamicallyResolved() const { + return Types[0] == MVT::iPTR; + } MVT::ValueType getTypeNum(unsigned Num) const { assert(hasTypeSet() && "Doesn't have a type yet!"); assert(Types.size() > Num && "Type num out of range!"); @@ -247,7 +252,7 @@ /// ContainsUnresolvedType - Return true if this tree contains any /// unresolved types. bool ContainsUnresolvedType() const { - if (!hasTypeSet()) return true; + if (!hasTypeSet() && !isTypeDynamicallyResolved()) return true; for (unsigned i = 0, e = getNumChildren(); i != e; ++i) if (getChild(i)->ContainsUnresolvedType()) return true; return false; From lattner at cs.uiuc.edu Wed May 17 15:43:34 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 17 May 2006 15:43:34 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Message-ID: <200605172043.PAA32173@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAGISel.cpp updated: 1.245 -> 1.246 --- Log message: Correct a previous patch which broke CodeGen/PowerPC/vec_call.ll --- Diffs of the changes: (+5 -18) SelectionDAGISel.cpp | 23 +++++------------------ 1 files changed, 5 insertions(+), 18 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.245 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.246 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.245 Wed May 17 13:16:39 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed May 17 15:43:21 2006 @@ -2551,25 +2551,12 @@ // Figure out if there is a Packed type corresponding to this Vector // type. If so, convert to the packed type. - bool Supported = false; MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems); - if (TVT != MVT::Other) { - // Handle copies from generic vectors to registers. - MVT::ValueType PTyElementVT, PTyLegalElementVT; - unsigned NE = getPackedTypeBreakdown(PTy, PTyElementVT, - PTyLegalElementVT); - // FIXME: handle NE > 1 cases. - if (NE == 1) { - // Insert a VBIT_CONVERT of the MVT::Vector type to the packed type. - Op = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Op, - DAG.getConstant(NumElems, MVT::i32), - DAG.getValueType(getValueType(EltTy))); - Ops.push_back(Op); - Supported = true; - } - } - - if (!Supported) { + if (TVT != MVT::Other && isTypeLegal(TVT)) { + // Insert a VBIT_CONVERT of the MVT::Vector type to the packed type. + Op = DAG.getNode(ISD::VBIT_CONVERT, TVT, Op); + Ops.push_back(Op); + } else { assert(0 && "Don't support illegal by-val vector call args yet!"); abort(); } From lattner at cs.uiuc.edu Wed May 17 15:49:49 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 17 May 2006 15:49:49 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Message-ID: <200605172049.PAA32284@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAGISel.cpp updated: 1.246 -> 1.247 --- Log message: Fix the result of the call to use a correct vbitconvert. There is no need to use getPackedTypeBreakdown at all here. --- Diffs of the changes: (+8 -23) SelectionDAGISel.cpp | 31 ++++++++----------------------- 1 files changed, 8 insertions(+), 23 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.246 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.247 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.246 Wed May 17 15:43:21 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed May 17 15:49:36 2006 @@ -2455,25 +2455,15 @@ // Figure out if there is a Packed type corresponding to this Vector // type. If so, convert to the packed type. - bool Supported = false; MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems); - if (TVT != MVT::Other) { + if (TVT != MVT::Other && isTypeLegal(TVT)) { SDOperand N = SDOperand(Result, i++); // Handle copies from generic vectors to registers. - MVT::ValueType PTyElementVT, PTyLegalElementVT; - unsigned NE = getPackedTypeBreakdown(PTy, PTyElementVT, - PTyLegalElementVT); - // FIXME: handle NE > 1 cases. - if (NE == 1) { - N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N, - DAG.getConstant(NumElems, MVT::i32), - DAG.getValueType(getValueType(EltTy))); - Ops.push_back(N); - Supported = true; - } - } - - if (!Supported) { + N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N, + DAG.getConstant(NumElems, MVT::i32), + DAG.getValueType(getValueType(EltTy))); + Ops.push_back(N); + } else { assert(0 && "Don't support illegal by-val vector arguments yet!"); abort(); } @@ -2633,16 +2623,11 @@ // type. If so, convert to the packed type. MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems); if (TVT != MVT::Other && isTypeLegal(TVT)) { - // Handle copies from generic vectors to registers. - MVT::ValueType PTyElementVT, PTyLegalElementVT; - unsigned NE = getPackedTypeBreakdown(cast(RetTy), - PTyElementVT, - PTyLegalElementVT); // Insert a VBIT_CONVERT of the FORMAL_ARGUMENTS to a // "N x PTyElementVT" MVT::Vector type. ResVal = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, ResVal, - DAG.getConstant(NE, MVT::i32), - DAG.getValueType(PTyElementVT)); + DAG.getConstant(NumElems, MVT::i32), + DAG.getValueType(getValueType(EltTy))); } else { abort(); } From evan.cheng at apple.com Wed May 17 15:56:03 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 17 May 2006 15:56:03 -0500 Subject: [llvm-commits] CVS: llvm/utils/TableGen/CodeGenTarget.cpp Message-ID: <200605172056.PAA32345@zion.cs.uiuc.edu> Changes in directory llvm/utils/TableGen: CodeGenTarget.cpp updated: 1.65 -> 1.66 --- Log message: Typo --- Diffs of the changes: (+2 -2) CodeGenTarget.cpp | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/utils/TableGen/CodeGenTarget.cpp diff -u llvm/utils/TableGen/CodeGenTarget.cpp:1.65 llvm/utils/TableGen/CodeGenTarget.cpp:1.66 --- llvm/utils/TableGen/CodeGenTarget.cpp:1.65 Wed May 17 15:37:59 2006 +++ llvm/utils/TableGen/CodeGenTarget.cpp Wed May 17 15:55:51 2006 @@ -58,7 +58,7 @@ case MVT::v2f32: return "v2f32"; case MVT::v4f32: return "v4f32"; case MVT::v2f64: return "v2f64"; - case MVT::iPTR: return "TLI.getPointetTy()"; + case MVT::iPTR: return "TLI.getPointerTy()"; default: assert(0 && "ILLEGAL VALUE TYPE!"); return ""; } } @@ -88,7 +88,7 @@ case MVT::v2f32: return "MVT::v2f32"; case MVT::v4f32: return "MVT::v4f32"; case MVT::v2f64: return "MVT::v2f64"; - case MVT::iPTR: return "TLI.getPointetTy()"; + case MVT::iPTR: return "TLI.getPointerTy()"; default: assert(0 && "ILLEGAL VALUE TYPE!"); return ""; } } From lattner at cs.uiuc.edu Wed May 17 16:05:41 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 17 May 2006 16:05:41 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/LowerAllocations.cpp LowerInvoke.cpp LowerSelect.cpp LowerSwitch.cpp Mem2Reg.cpp Message-ID: <200605172105.QAA32479@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: LowerAllocations.cpp updated: 1.57 -> 1.58 LowerInvoke.cpp updated: 1.35 -> 1.36 LowerSelect.cpp updated: 1.5 -> 1.6 LowerSwitch.cpp updated: 1.20 -> 1.21 Mem2Reg.cpp updated: 1.16 -> 1.17 --- Log message: Declare that lowerinvoke doesn't interact with other lowering passes. Patch written by Domagoj Babic! --- Diffs of the changes: (+22 -7) LowerAllocations.cpp | 3 ++- LowerInvoke.cpp | 10 +++++++++- LowerSelect.cpp | 4 +++- LowerSwitch.cpp | 8 +++++--- Mem2Reg.cpp | 4 +++- 5 files changed, 22 insertions(+), 7 deletions(-) Index: llvm/lib/Transforms/Scalar/LowerAllocations.cpp diff -u llvm/lib/Transforms/Scalar/LowerAllocations.cpp:1.57 llvm/lib/Transforms/Scalar/LowerAllocations.cpp:1.58 --- llvm/lib/Transforms/Scalar/LowerAllocations.cpp:1.57 Mon May 8 23:13:41 2006 +++ llvm/lib/Transforms/Scalar/LowerAllocations.cpp Wed May 17 16:05:27 2006 @@ -41,11 +41,12 @@ AU.addRequired(); AU.setPreservesCFG(); - // This is a cluster of orthogonal Transforms: + // This is a cluster of orthogonal Transforms: AU.addPreserved(); AU.addPreservedID(PromoteMemoryToRegisterID); AU.addPreservedID(LowerSelectID); AU.addPreservedID(LowerSwitchID); + AU.addPreservedID(LowerInvokePassID); } /// doPassInitialization - For the lower allocations pass, this ensures that Index: llvm/lib/Transforms/Scalar/LowerInvoke.cpp diff -u llvm/lib/Transforms/Scalar/LowerInvoke.cpp:1.35 llvm/lib/Transforms/Scalar/LowerInvoke.cpp:1.36 --- llvm/lib/Transforms/Scalar/LowerInvoke.cpp:1.35 Sat Nov 5 03:21:28 2005 +++ llvm/lib/Transforms/Scalar/LowerInvoke.cpp Wed May 17 16:05:27 2006 @@ -71,7 +71,15 @@ JumpBufAlign(Align) {} bool doInitialization(Module &M); bool runOnFunction(Function &F); - + + virtual void getAnalysisUsage(AnalysisUsage &AU) const { + // This is a cluster of orthogonal Transforms + AU.addPreservedID(PromoteMemoryToRegisterID); + AU.addPreservedID(LowerSelectID); + AU.addPreservedID(LowerSwitchID); + AU.addPreservedID(LowerAllocationsID); + } + private: void createAbortMessage(); void writeAbortMessage(Instruction *IB); Index: llvm/lib/Transforms/Scalar/LowerSelect.cpp diff -u llvm/lib/Transforms/Scalar/LowerSelect.cpp:1.5 llvm/lib/Transforms/Scalar/LowerSelect.cpp:1.6 --- llvm/lib/Transforms/Scalar/LowerSelect.cpp:1.5 Mon May 8 23:13:41 2006 +++ llvm/lib/Transforms/Scalar/LowerSelect.cpp Wed May 17 16:05:27 2006 @@ -39,10 +39,12 @@ virtual void getAnalysisUsage(AnalysisUsage &AU) const { // This certainly destroys the CFG. - // This is a cluster of orthogonal Transforms: + // This is a cluster of orthogonal Transforms: AU.addPreserved(); AU.addPreservedID(PromoteMemoryToRegisterID); AU.addPreservedID(LowerSwitchID); + AU.addPreservedID(LowerInvokePassID); + AU.addPreservedID(LowerAllocationsID); } bool runOnFunction(Function &F); Index: llvm/lib/Transforms/Scalar/LowerSwitch.cpp diff -u llvm/lib/Transforms/Scalar/LowerSwitch.cpp:1.20 llvm/lib/Transforms/Scalar/LowerSwitch.cpp:1.21 --- llvm/lib/Transforms/Scalar/LowerSwitch.cpp:1.20 Mon May 8 23:13:41 2006 +++ llvm/lib/Transforms/Scalar/LowerSwitch.cpp Wed May 17 16:05:27 2006 @@ -34,14 +34,16 @@ class LowerSwitch : public FunctionPass { public: virtual bool runOnFunction(Function &F); - + virtual void getAnalysisUsage(AnalysisUsage &AU) const { - // This is a cluster of orthogonal Transforms + // This is a cluster of orthogonal Transforms AU.addPreserved(); AU.addPreservedID(PromoteMemoryToRegisterID); AU.addPreservedID(LowerSelectID); + AU.addPreservedID(LowerInvokePassID); + AU.addPreservedID(LowerAllocationsID); } - + typedef std::pair Case; typedef std::vector::iterator CaseItr; private: Index: llvm/lib/Transforms/Scalar/Mem2Reg.cpp diff -u llvm/lib/Transforms/Scalar/Mem2Reg.cpp:1.16 llvm/lib/Transforms/Scalar/Mem2Reg.cpp:1.17 --- llvm/lib/Transforms/Scalar/Mem2Reg.cpp:1.16 Mon May 8 23:13:41 2006 +++ llvm/lib/Transforms/Scalar/Mem2Reg.cpp Wed May 17 16:05:27 2006 @@ -38,10 +38,12 @@ AU.addRequired(); AU.addRequired(); AU.setPreservesCFG(); - // This is a cluster of orthogonal Transforms + // This is a cluster of orthogonal Transforms AU.addPreserved(); AU.addPreservedID(LowerSelectID); AU.addPreservedID(LowerSwitchID); + AU.addPreservedID(LowerInvokePassID); + AU.addPreservedID(LowerAllocationsID); } }; From evan.cheng at apple.com Wed May 17 16:18:20 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 17 May 2006 16:18:20 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Target.td Message-ID: <200605172118.QAA32535@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target: Target.td updated: 1.81 -> 1.82 --- Log message: Remove PointerType from class Target --- Diffs of the changes: (+0 -4) Target.td | 4 ---- 1 files changed, 4 deletions(-) Index: llvm/lib/Target/Target.td diff -u llvm/lib/Target/Target.td:1.81 llvm/lib/Target/Target.td:1.82 --- llvm/lib/Target/Target.td:1.81 Tue May 16 01:39:36 2006 +++ llvm/lib/Target/Target.td Wed May 17 16:18:07 2006 @@ -271,10 +271,6 @@ // saved registers for a target. list CalleeSavedRegisters = []; - // PointerType - Specify the value type to be used to represent pointers in - // this target. Typically this is an i32 or i64 type. - ValueType PointerType; - // InstructionSet - Instruction set description for this target. InstrInfo InstructionSet; From evan.cheng at apple.com Wed May 17 16:19:02 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 17 May 2006 16:19:02 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/ARM/ARM.td Message-ID: <200605172119.QAA32562@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/ARM: ARM.td updated: 1.1 -> 1.2 --- Log message: Remove PointerType from class Target --- Diffs of the changes: (+0 -3) ARM.td | 3 --- 1 files changed, 3 deletions(-) Index: llvm/lib/Target/ARM/ARM.td diff -u llvm/lib/Target/ARM/ARM.td:1.1 llvm/lib/Target/ARM/ARM.td:1.2 --- llvm/lib/Target/ARM/ARM.td:1.1 Sun May 14 17:18:28 2006 +++ llvm/lib/Target/ARM/ARM.td Wed May 17 16:18:48 2006 @@ -40,9 +40,6 @@ //===----------------------------------------------------------------------===// def ARM : Target { - // Pointers are 32-bits in size. - let PointerType = i32; - // FIXME: Specify callee-saved registers let CalleeSavedRegisters = []; From evan.cheng at apple.com Wed May 17 16:19:02 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 17 May 2006 16:19:02 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/IA64/IA64.td Message-ID: <200605172119.QAA32568@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/IA64: IA64.td updated: 1.7 -> 1.8 --- Log message: Remove PointerType from class Target --- Diffs of the changes: (+0 -4) IA64.td | 4 ---- 1 files changed, 4 deletions(-) Index: llvm/lib/Target/IA64/IA64.td diff -u llvm/lib/Target/IA64/IA64.td:1.7 llvm/lib/Target/IA64/IA64.td:1.8 --- llvm/lib/Target/IA64/IA64.td:1.7 Thu Jan 26 19:46:15 2006 +++ llvm/lib/Target/IA64/IA64.td Wed May 17 16:18:48 2006 @@ -91,10 +91,6 @@ */ ]; - // We don't go anywhere near the LP32 variant of IA64 as - // sometimes seen in (for example) HP-UX - let PointerType = i64; - // Our instruction set let InstructionSet = IA64InstrInfo; From evan.cheng at apple.com Wed May 17 16:19:02 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 17 May 2006 16:19:02 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/Alpha.td Message-ID: <200605172119.QAA32574@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Alpha: Alpha.td updated: 1.9 -> 1.10 --- Log message: Remove PointerType from class Target --- Diffs of the changes: (+0 -3) Alpha.td | 3 --- 1 files changed, 3 deletions(-) Index: llvm/lib/Target/Alpha/Alpha.td diff -u llvm/lib/Target/Alpha/Alpha.td:1.9 llvm/lib/Target/Alpha/Alpha.td:1.10 --- llvm/lib/Target/Alpha/Alpha.td:1.9 Thu Mar 9 11:16:45 2006 +++ llvm/lib/Target/Alpha/Alpha.td Wed May 17 16:18:48 2006 @@ -65,9 +65,6 @@ def Alpha : Target { - // Pointers on Alpha are 64-bits in size. - let PointerType = i64; - let CalleeSavedRegisters = //saved regs [R9, R10, R11, R12, R13, R14, From evan.cheng at apple.com Wed May 17 16:19:02 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 17 May 2006 16:19:02 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/Sparc.td Message-ID: <200605172119.QAA32566@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Sparc: Sparc.td updated: 1.11 -> 1.12 --- Log message: Remove PointerType from class Target --- Diffs of the changes: (+0 -3) Sparc.td | 3 --- 1 files changed, 3 deletions(-) Index: llvm/lib/Target/Sparc/Sparc.td diff -u llvm/lib/Target/Sparc/Sparc.td:1.11 llvm/lib/Target/Sparc/Sparc.td:1.12 --- llvm/lib/Target/Sparc/Sparc.td:1.11 Sat Feb 4 23:50:24 2006 +++ llvm/lib/Target/Sparc/Sparc.td Wed May 17 16:18:48 2006 @@ -75,9 +75,6 @@ //===----------------------------------------------------------------------===// def Sparc : Target { - // Pointers are 32-bits in size. - let PointerType = i32; - // FIXME: Specify callee-saved registers let CalleeSavedRegisters = []; From evan.cheng at apple.com Wed May 17 16:19:50 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 17 May 2006 16:19:50 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC.td Message-ID: <200605172119.QAA32592@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPC.td updated: 1.15 -> 1.16 --- Log message: Remove PointerType from class Target --- Diffs of the changes: (+0 -3) PPC.td | 3 --- 1 files changed, 3 deletions(-) Index: llvm/lib/Target/PowerPC/PPC.td diff -u llvm/lib/Target/PowerPC/PPC.td:1.15 llvm/lib/Target/PowerPC/PPC.td:1.16 --- llvm/lib/Target/PowerPC/PPC.td:1.15 Thu Mar 16 16:07:06 2006 +++ llvm/lib/Target/PowerPC/PPC.td Wed May 17 16:19:38 2006 @@ -81,9 +81,6 @@ def PPC : Target { - // Pointers on PPC are 32-bits in size. - let PointerType = i32; - // Information about the instructions. let InstructionSet = PPCInstrInfo; From evan.cheng at apple.com Wed May 17 16:20:39 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 17 May 2006 16:20:39 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86.td Message-ID: <200605172120.QAA32623@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86.td updated: 1.22 -> 1.23 --- Log message: Remove PointerType from class Target --- Diffs of the changes: (+0 -3) X86.td | 3 --- 1 files changed, 3 deletions(-) Index: llvm/lib/Target/X86/X86.td diff -u llvm/lib/Target/X86/X86.td:1.22 llvm/lib/Target/X86/X86.td:1.23 --- llvm/lib/Target/X86/X86.td:1.22 Wed Feb 1 00:13:50 2006 +++ llvm/lib/Target/X86/X86.td Wed May 17 16:20:27 2006 @@ -133,9 +133,6 @@ // Specify the callee saved registers. let CalleeSavedRegisters = [ESI, EDI, EBX, EBP]; - // Yes, pointers are 32-bits in size. - let PointerType = i32; - // Information about the instructions... let InstructionSet = X86InstrInfo; From reid at x10sys.com Wed May 17 16:21:03 2006 From: reid at x10sys.com (Reid Spencer) Date: Wed, 17 May 2006 16:21:03 -0500 Subject: [llvm-commits] CVS: llvm/tools/Makefile Message-ID: <200605172121.QAA32641@zion.cs.uiuc.edu> Changes in directory llvm/tools: Makefile updated: 1.46 -> 1.47 --- Log message: Remove the llvm-db and bugpoint restrictions from the win32 platform so they can be compiled with ming32. The use of fork(2) has been removed. --- Diffs of the changes: (+1 -11) Makefile | 12 +----------- 1 files changed, 1 insertion(+), 11 deletions(-) Index: llvm/tools/Makefile diff -u llvm/tools/Makefile:1.46 llvm/tools/Makefile:1.47 --- llvm/tools/Makefile:1.46 Thu Apr 20 16:14:39 2006 +++ llvm/tools/Makefile Wed May 17 16:20:50 2006 @@ -12,14 +12,4 @@ analyze llvm-extract llvm-nm llvm-prof llvm-ar llvm-ranlib \ llvm-bcanalyzer llvmc llvm-ld llvm-db bugpoint llvm-config -include $(LEVEL)/Makefile.config - -# The bugpoint and llvm-db tools are not portable to Win32 because they depend -# on fork(2) behavior that Win32 doesn't have. At some point they'll be -# rewritten to not depend on fork at which time they should be added back to -# the list above. -ifneq ($(LLVM_ON_UNIX),1) -PARALLEL_DIRS := $(filter-out bugpoint llvm-db,$(PARALLEL_DIRS)) -endif - -include $(LLVM_SRC_ROOT)/Makefile.rules +include $(LEVEL)/Makefile.common From evan.cheng at apple.com Wed May 17 16:21:04 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 17 May 2006 16:21:04 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/README.txt Message-ID: <200605172121.QAA32645@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: README.txt updated: 1.105 -> 1.106 --- Log message: Another entry --- Diffs of the changes: (+9 -0) README.txt | 9 +++++++++ 1 files changed, 9 insertions(+) Index: llvm/lib/Target/X86/README.txt diff -u llvm/lib/Target/X86/README.txt:1.105 llvm/lib/Target/X86/README.txt:1.106 --- llvm/lib/Target/X86/README.txt:1.105 Wed May 17 14:05:31 2006 +++ llvm/lib/Target/X86/README.txt Wed May 17 16:20:51 2006 @@ -1183,3 +1183,12 @@ shll $24, %eax sarl $24, %eax ret + +//===---------------------------------------------------------------------===// + +Some useful information in the Apple Altivec / SSE Migration Guide: + +http://developer.apple.com/documentation/Performance/Conceptual/ +Accelerate_sse_migration/index.html + +e.g. SSE select using and, andnot, or. Various SSE compare translations. From evan.cheng at apple.com Wed May 17 16:21:54 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 17 May 2006 16:21:54 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.td Message-ID: <200605172121.QAA32672@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrInfo.td updated: 1.267 -> 1.268 --- Log message: Use generic iPTR instead i32 to represent pointer type. --- Diffs of the changes: (+3 -3) X86InstrInfo.td | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) Index: llvm/lib/Target/X86/X86InstrInfo.td diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.267 llvm/lib/Target/X86/X86InstrInfo.td:1.268 --- llvm/lib/Target/X86/X86InstrInfo.td:1.267 Tue May 16 02:21:53 2006 +++ llvm/lib/Target/X86/X86InstrInfo.td Wed May 17 16:21:41 2006 @@ -94,7 +94,7 @@ // *mem - Operand definitions for the funky X86 addressing mode operands. // -class X86MemOperand : Operand { +class X86MemOperand : Operand { let PrintMethod = printMethod; let NumMIOperands = 4; let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm); @@ -131,8 +131,8 @@ // // Define X86 specific addressing mode. -def addr : ComplexPattern; -def leaaddr : ComplexPattern; +def leaaddr : ComplexPattern; //===----------------------------------------------------------------------===// From lattner at cs.uiuc.edu Wed May 17 16:55:00 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 17 May 2006 16:55:00 -0500 Subject: [llvm-commits] CVS: llvm/lib/Makefile Message-ID: <200605172155.QAA00464@zion.cs.uiuc.edu> Changes in directory llvm/lib: Makefile updated: 1.20 -> 1.21 --- Log message: Use DIRS here instead of PARALLEL_DIRS, as VMCore has to be built before the other dirs (for Intrinsics.gen). :( --- Diffs of the changes: (+2 -2) Makefile | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/Makefile diff -u llvm/lib/Makefile:1.20 llvm/lib/Makefile:1.21 --- llvm/lib/Makefile:1.20 Sun Nov 14 15:54:41 2004 +++ llvm/lib/Makefile Wed May 17 16:54:48 2006 @@ -8,8 +8,8 @@ ##===----------------------------------------------------------------------===## LEVEL = .. -PARALLEL_DIRS = VMCore Analysis Transforms AsmParser Bytecode CodeGen Target \ - ExecutionEngine Debugger Linker +DIRS = VMCore Analysis Transforms AsmParser Bytecode CodeGen Target \ + ExecutionEngine Debugger Linker include $(LEVEL)/Makefile.common From resistor at mac.com Wed May 17 16:56:14 2006 From: resistor at mac.com (Owen Anderson) Date: Wed, 17 May 2006 16:56:14 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/TargetData.cpp Message-ID: <200605172156.QAA00485@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target: TargetData.cpp updated: 1.64 -> 1.65 --- Log message: Fix a stupid bug when parsing TargetData strings. --- Diffs of the changes: (+3 -1) TargetData.cpp | 4 +++- 1 files changed, 3 insertions(+), 1 deletion(-) Index: llvm/lib/Target/TargetData.cpp diff -u llvm/lib/Target/TargetData.cpp:1.64 llvm/lib/Target/TargetData.cpp:1.65 --- llvm/lib/Target/TargetData.cpp:1.64 Fri May 12 02:01:44 2006 +++ llvm/lib/Target/TargetData.cpp Wed May 17 16:56:02 2006 @@ -139,7 +139,9 @@ while (temp.length() > 0) { std::string token = getToken(temp, "-"); - switch(token[0]) { + char signal = getToken(token, ":")[0]; + + switch(signal) { case 'E': LittleEndian = false; break; From reid at x10sys.com Wed May 17 17:55:48 2006 From: reid at x10sys.com (Reid Spencer) Date: Wed, 17 May 2006 17:55:48 -0500 Subject: [llvm-commits] CVS: llvm/lib/Makefile Message-ID: <200605172255.RAA00974@zion.cs.uiuc.edu> Changes in directory llvm/lib: Makefile updated: 1.21 -> 1.22 --- Log message: Make some changes suggested by Chris: 1. Remove the LLVM_DO_NOT_BUILD feature (not needed any more) 2. Ensure that lib/VMCore gets built first. This needs to be done because VMCore now uses tblgen to generate the Intrinsics header which are needed in other libraries. In parallel builds, this can cause problems. --- Diffs of the changes: (+2 -2) Makefile | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/Makefile diff -u llvm/lib/Makefile:1.21 llvm/lib/Makefile:1.22 --- llvm/lib/Makefile:1.21 Wed May 17 16:54:48 2006 +++ llvm/lib/Makefile Wed May 17 17:55:35 2006 @@ -8,8 +8,8 @@ ##===----------------------------------------------------------------------===## LEVEL = .. -DIRS = VMCore Analysis Transforms AsmParser Bytecode CodeGen Target \ - ExecutionEngine Debugger Linker +PARALLEL_DIRS = VMCore Analysis Transforms AsmParser Bytecode CodeGen Target \ + ExecutionEngine Debugger Linker include $(LEVEL)/Makefile.common From reid at x10sys.com Wed May 17 17:55:48 2006 From: reid at x10sys.com (Reid Spencer) Date: Wed, 17 May 2006 17:55:48 -0500 Subject: [llvm-commits] CVS: llvm/Makefile Makefile.rules Message-ID: <200605172255.RAA00980@zion.cs.uiuc.edu> Changes in directory llvm: Makefile updated: 1.58 -> 1.59 Makefile.rules updated: 1.369 -> 1.370 --- Log message: Make some changes suggested by Chris: 1. Remove the LLVM_DO_NOT_BUILD feature (not needed any more) 2. Ensure that lib/VMCore gets built first. This needs to be done because VMCore now uses tblgen to generate the Intrinsics header which are needed in other libraries. In parallel builds, this can cause problems. --- Diffs of the changes: (+5 -13) Makefile | 2 +- Makefile.rules | 16 ++++------------ 2 files changed, 5 insertions(+), 13 deletions(-) Index: llvm/Makefile diff -u llvm/Makefile:1.58 llvm/Makefile:1.59 --- llvm/Makefile:1.58 Wed Apr 12 15:53:14 2006 +++ llvm/Makefile Wed May 17 17:55:35 2006 @@ -7,7 +7,7 @@ # #===------------------------------------------------------------------------===# LEVEL = . -DIRS = lib/System lib/Support utils lib +DIRS = lib/System lib/Support utils lib/VMCore lib include $(LEVEL)/Makefile.config Index: llvm/Makefile.rules diff -u llvm/Makefile.rules:1.369 llvm/Makefile.rules:1.370 --- llvm/Makefile.rules:1.369 Tue May 16 01:51:02 2006 +++ llvm/Makefile.rules Wed May 17 17:55:35 2006 @@ -472,9 +472,7 @@ $(MKDIR) $$dir; \ $(CP) $(PROJ_SRC_DIR)/$$dir/Makefile $$dir/Makefile; \ fi; \ - if [ ! -f $$dir/LLVM_DO_NOT_BUILD ]; then \ - ($(MAKE) -C $$dir $@ ) || exit 1; \ - fi ; \ + ($(MAKE) -C $$dir $@ ) || exit 1; \ done endif @@ -489,9 +487,7 @@ $(MKDIR) $$dir; \ $(CP) $(PROJ_SRC_DIR)/$$dir/Makefile $$dir/Makefile; \ fi; \ - if [ ! -f $$dir/LLVM_DO_NOT_BUILD ]; then \ - ($(MAKE) -C $$dir $@ ) || exit 0; \ - fi ; \ + ($(MAKE) -C $$dir $@ ) || exit 0; \ done endif @@ -517,9 +513,7 @@ $(MKDIR) $(@D); \ $(CP) $(PROJ_SRC_DIR)/$(@D)/Makefile $(@D)/Makefile; \ fi; \ - if [ ! -f $$dir/LLVM_DO_NOT_BUILD ]; then \ - $(MAKE) -C $(@D) $(subst $(@D)/.make,,$@) ; \ - fi + $(MAKE) -C $(@D) $(subst $(@D)/.make,,$@) ; endif #--------------------------------------------------------- @@ -537,9 +531,7 @@ $(MKDIR) $$dir; \ $(CP) $(PROJ_SRC_DIR)/$$dir/Makefile $$dir/Makefile; \ fi; \ - if [ ! -f $$dir/LLVM_DO_NOT_BUILD ]; then \ - ($(MAKE) -C$$dir $@ ) || exit 1; \ - fi ; \ + ($(MAKE) -C$$dir $@ ) || exit 1; \ fi \ done endif From lattner at cs.uiuc.edu Wed May 17 18:44:08 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Wed, 17 May 2006 18:44:08 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/ExecutionEngine/hello2.ll Message-ID: <200605172344.SAA01302@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/ExecutionEngine: hello2.ll updated: 1.2 -> 1.3 --- Log message: This test is buggy: printf is a varargs function. This fixes the test with the PPC JIT --- Diffs of the changes: (+2 -2) hello2.ll | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/test/Regression/ExecutionEngine/hello2.ll diff -u llvm/test/Regression/ExecutionEngine/hello2.ll:1.2 llvm/test/Regression/ExecutionEngine/hello2.ll:1.3 --- llvm/test/Regression/ExecutionEngine/hello2.ll:1.2 Sat Nov 6 17:32:43 2004 +++ llvm/test/Regression/ExecutionEngine/hello2.ll Wed May 17 18:43:56 2006 @@ -8,10 +8,10 @@ implementation -declare void %printf([13 x sbyte]*) +declare void %printf([13 x sbyte]*,...) void %bar() { - call void %printf([13 x sbyte]* %msg) + call void([13 x sbyte]*,...)* %printf([13 x sbyte]* %msg) ret void } From evan.cheng at apple.com Wed May 17 19:08:59 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 17 May 2006 19:08:59 -0500 Subject: [llvm-commits] CVS: llvm/utils/TableGen/CodeGenTarget.cpp CodeGenTarget.h RegisterInfoEmitter.cpp Message-ID: <200605180008.TAA01433@zion.cs.uiuc.edu> Changes in directory llvm/utils/TableGen: CodeGenTarget.cpp updated: 1.66 -> 1.67 CodeGenTarget.h updated: 1.27 -> 1.28 RegisterInfoEmitter.cpp updated: 1.42 -> 1.43 --- Log message: Don't generate getCalleeSaveReg and getCalleeSaveRegClasses anymore. --- Diffs of the changes: (+0 -40) CodeGenTarget.cpp | 3 --- CodeGenTarget.h | 5 ----- RegisterInfoEmitter.cpp | 32 -------------------------------- 3 files changed, 40 deletions(-) Index: llvm/utils/TableGen/CodeGenTarget.cpp diff -u llvm/utils/TableGen/CodeGenTarget.cpp:1.66 llvm/utils/TableGen/CodeGenTarget.cpp:1.67 --- llvm/utils/TableGen/CodeGenTarget.cpp:1.66 Wed May 17 15:55:51 2006 +++ llvm/utils/TableGen/CodeGenTarget.cpp Wed May 17 19:08:46 2006 @@ -108,9 +108,6 @@ if (Targets.size() != 1) throw std::string("ERROR: Multiple subclasses of Target defined!"); TargetRec = Targets[0]; - - // Read in all of the CalleeSavedRegisters. - CalleeSavedRegisters =TargetRec->getValueAsListOfDefs("CalleeSavedRegisters"); } Index: llvm/utils/TableGen/CodeGenTarget.h diff -u llvm/utils/TableGen/CodeGenTarget.h:1.27 llvm/utils/TableGen/CodeGenTarget.h:1.28 --- llvm/utils/TableGen/CodeGenTarget.h:1.27 Wed May 17 15:37:59 2006 +++ llvm/utils/TableGen/CodeGenTarget.h Wed May 17 19:08:46 2006 @@ -42,7 +42,6 @@ /// class CodeGenTarget { Record *TargetRec; - std::vector CalleeSavedRegisters; mutable std::map Instructions; mutable std::vector Registers; @@ -58,10 +57,6 @@ Record *getTargetRecord() const { return TargetRec; } const std::string &getName() const; - const std::vector &getCalleeSavedRegisters() const { - return CalleeSavedRegisters; - } - /// getInstructionSet - Return the InstructionSet object. /// Record *getInstructionSet() const; Index: llvm/utils/TableGen/RegisterInfoEmitter.cpp diff -u llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.42 llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.43 --- llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.42 Thu May 11 02:30:26 2006 +++ llvm/utils/TableGen/RegisterInfoEmitter.cpp Wed May 17 19:08:46 2006 @@ -59,8 +59,6 @@ OS << "struct " << ClassName << " : public MRegisterInfo {\n" << " " << ClassName << "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n" - << " const unsigned* getCalleeSaveRegs() const;\n" - << " const TargetRegisterClass* const *getCalleeSaveRegClasses() const;\n" << " int getDwarfRegNum(unsigned RegNum) const;\n" << "};\n\n"; @@ -333,36 +331,6 @@ << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n " << " CallFrameSetupOpcode, CallFrameDestroyOpcode) {}\n\n"; - // Emit the getCalleeSaveRegs method. - OS << "const unsigned* " << ClassName << "::getCalleeSaveRegs() const {\n" - << " static const unsigned CalleeSaveRegs[] = {\n "; - - const std::vector &CSR = Target.getCalleeSavedRegisters(); - for (unsigned i = 0, e = CSR.size(); i != e; ++i) - OS << getQualifiedName(CSR[i]) << ", "; - OS << " 0\n };\n return CalleeSaveRegs;\n}\n\n"; - - // Emit information about the callee saved register classes. - OS << "const TargetRegisterClass* const*\n" << ClassName - << "::getCalleeSaveRegClasses() const {\n" - << " static const TargetRegisterClass * const " - << "CalleeSaveRegClasses[] = {\n "; - - for (unsigned i = 0, e = CSR.size(); i != e; ++i) { - Record *R = CSR[i]; - std::multimap::iterator I, E; - tie(I, E) = RegClassesBelongedTo.equal_range(R); - if (I == E) - throw "Callee saved register '" + R->getName() + - "' must belong to a register class for spilling.\n"; - const CodeGenRegisterClass *RC = (I++)->second; - for (; I != E; ++I) - if (RC->SpillSize < I->second->SpillSize) - RC = I->second; - OS << "&" << getQualifiedName(RC->TheDef) << "RegClass, "; - } - OS << " 0\n };\n return CalleeSaveRegClasses;\n}\n\n"; - // Emit information about the dwarf register numbers. OS << "int " << ClassName << "::getDwarfRegNum(unsigned RegNum) const {\n"; OS << " static const int DwarfRegNums[] = { -1, // NoRegister"; From evan.cheng at apple.com Wed May 17 19:10:05 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 17 May 2006 19:10:05 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Target.td Message-ID: <200605180010.TAA01461@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target: Target.td updated: 1.82 -> 1.83 --- Log message: Remove CalleeSavedRegisters from class Target. --- Diffs of the changes: (+0 -4) Target.td | 4 ---- 1 files changed, 4 deletions(-) Index: llvm/lib/Target/Target.td diff -u llvm/lib/Target/Target.td:1.82 llvm/lib/Target/Target.td:1.83 --- llvm/lib/Target/Target.td:1.82 Wed May 17 16:18:07 2006 +++ llvm/lib/Target/Target.td Wed May 17 19:09:53 2006 @@ -267,10 +267,6 @@ // Target - This class contains the "global" target information // class Target { - // CalleeSavedRegisters - As you might guess, this is a list of the callee - // saved registers for a target. - list CalleeSavedRegisters = []; - // InstructionSet - Instruction set description for this target. InstrInfo InstructionSet; From evan.cheng at apple.com Wed May 17 19:11:38 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 17 May 2006 19:11:38 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/ARM/ARM.td ARMRegisterInfo.cpp ARMRegisterInfo.h Message-ID: <200605180011.TAA01485@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/ARM: ARM.td updated: 1.2 -> 1.3 ARMRegisterInfo.cpp updated: 1.1 -> 1.2 ARMRegisterInfo.h updated: 1.1 -> 1.2 --- Log message: getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd. --- Diffs of the changes: (+15 -3) ARM.td | 3 --- ARMRegisterInfo.cpp | 11 +++++++++++ ARMRegisterInfo.h | 4 ++++ 3 files changed, 15 insertions(+), 3 deletions(-) Index: llvm/lib/Target/ARM/ARM.td diff -u llvm/lib/Target/ARM/ARM.td:1.2 llvm/lib/Target/ARM/ARM.td:1.3 --- llvm/lib/Target/ARM/ARM.td:1.2 Wed May 17 16:18:48 2006 +++ llvm/lib/Target/ARM/ARM.td Wed May 17 19:11:26 2006 @@ -40,9 +40,6 @@ //===----------------------------------------------------------------------===// def ARM : Target { - // FIXME: Specify callee-saved registers - let CalleeSavedRegisters = []; - // Pull in Instruction Info: let InstructionSet = ARMInstrInfo; } Index: llvm/lib/Target/ARM/ARMRegisterInfo.cpp diff -u llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.1 llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.2 --- llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.1 Sun May 14 17:18:28 2006 +++ llvm/lib/Target/ARM/ARMRegisterInfo.cpp Wed May 17 19:11:26 2006 @@ -58,6 +58,17 @@ return NULL; } +const unsigned* ARMRegisterInfo::getCalleeSaveRegs() const { + static const unsigned CalleeSaveRegs[] = { 0 }; + return CalleeSaveRegs; +} + +const TargetRegisterClass* const * +ARMRegisterInfo::getCalleeSaveRegClasses() const { + static const TargetRegisterClass * const CalleeSaveRegClasses[] = { 0 }; + return CalleeSaveRegClasses; +} + void ARMRegisterInfo:: eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { Index: llvm/lib/Target/ARM/ARMRegisterInfo.h diff -u llvm/lib/Target/ARM/ARMRegisterInfo.h:1.1 llvm/lib/Target/ARM/ARMRegisterInfo.h:1.2 --- llvm/lib/Target/ARM/ARMRegisterInfo.h:1.1 Sun May 14 17:18:28 2006 +++ llvm/lib/Target/ARM/ARMRegisterInfo.h Wed May 17 19:11:26 2006 @@ -45,6 +45,10 @@ unsigned OpNum, int FrameIndex) const; + const unsigned *getCalleeSaveRegs() const; + + const TargetRegisterClass* const* getCalleeSaveRegClasses() const; + void eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const; From evan.cheng at apple.com Wed May 17 19:12:05 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 17 May 2006 19:12:05 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/Alpha.td AlphaRegisterInfo.cpp AlphaRegisterInfo.h Message-ID: <200605180012.TAA01501@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Alpha: Alpha.td updated: 1.10 -> 1.11 AlphaRegisterInfo.cpp updated: 1.44 -> 1.45 AlphaRegisterInfo.h updated: 1.12 -> 1.13 --- Log message: getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd. --- Diffs of the changes: (+31 -11) Alpha.td | 11 ----------- AlphaRegisterInfo.cpp | 27 +++++++++++++++++++++++++++ AlphaRegisterInfo.h | 4 ++++ 3 files changed, 31 insertions(+), 11 deletions(-) Index: llvm/lib/Target/Alpha/Alpha.td diff -u llvm/lib/Target/Alpha/Alpha.td:1.10 llvm/lib/Target/Alpha/Alpha.td:1.11 --- llvm/lib/Target/Alpha/Alpha.td:1.10 Wed May 17 16:18:48 2006 +++ llvm/lib/Target/Alpha/Alpha.td Wed May 17 19:11:53 2006 @@ -65,17 +65,6 @@ def Alpha : Target { - let CalleeSavedRegisters = - //saved regs - [R9, R10, R11, R12, R13, R14, - //Frame pointer -// R15, - //return address -// R26, - //Stack Pointer -// R30, - F2, F3, F4, F5, F6, F7, F8, F9]; - // Pull in Instruction Info: let InstructionSet = AlphaInstrInfo; } Index: llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp diff -u llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.44 llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.45 --- llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.44 Wed May 17 14:24:49 2006 +++ llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp Wed May 17 19:11:53 2006 @@ -145,6 +145,33 @@ } } +const unsigned* AlphaRegisterInfo::getCalleeSaveRegs() const { + static const unsigned CalleeSaveRegs[] = { + Alpha::R9, Alpha::R10, + Alpha::R11, Alpha::R12, + Alpha::R13, Alpha::R14, + Alpha::F2, Alpha::F3, + Alpha::F4, Alpha::F5, + Alpha::F6, Alpha::F7, + Alpha::F8, Alpha::F9, 0 + }; + return CalleeSaveRegs; +} + +const TargetRegisterClass* const* +AlphaRegisterInfo::getCalleeSaveRegClasses() const { + static const TargetRegisterClass * const CalleeSaveRegClasses[] = { + &Alpha::GPRCRegClass, &Alpha::GPRCRegClass, + &Alpha::GPRCRegClass, &Alpha::GPRCRegClass, + &Alpha::GPRCRegClass, &Alpha::GPRCRegClass, + &Alpha::F8RCRegClass, &Alpha::F8RCRegClass, + &Alpha::F8RCRegClass, &Alpha::F8RCRegClass, + &Alpha::F8RCRegClass, &Alpha::F8RCRegClass, + &Alpha::F8RCRegClass, &Alpha::F8RCRegClass, 0 + }; + return CalleeSaveRegClasses; +} + //===----------------------------------------------------------------------===// // Stack Frame Processing methods //===----------------------------------------------------------------------===// Index: llvm/lib/Target/Alpha/AlphaRegisterInfo.h diff -u llvm/lib/Target/Alpha/AlphaRegisterInfo.h:1.12 llvm/lib/Target/Alpha/AlphaRegisterInfo.h:1.13 --- llvm/lib/Target/Alpha/AlphaRegisterInfo.h:1.12 Fri Apr 7 11:34:45 2006 +++ llvm/lib/Target/Alpha/AlphaRegisterInfo.h Wed May 17 19:11:53 2006 @@ -42,6 +42,10 @@ unsigned DestReg, unsigned SrcReg, const TargetRegisterClass *RC) const; + const unsigned *getCalleeSaveRegs() const; + + const TargetRegisterClass* const* getCalleeSaveRegClasses() const; + void eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const; From evan.cheng at apple.com Wed May 17 19:12:24 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 17 May 2006 19:12:24 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/IA64/IA64.td IA64RegisterInfo.cpp IA64RegisterInfo.h Message-ID: <200605180012.TAA01518@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/IA64: IA64.td updated: 1.8 -> 1.9 IA64RegisterInfo.cpp updated: 1.19 -> 1.20 IA64RegisterInfo.h updated: 1.7 -> 1.8 --- Log message: getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd. --- Diffs of the changes: (+19 -60) IA64.td | 60 --------------------------------------------------- IA64RegisterInfo.cpp | 15 ++++++++++++ IA64RegisterInfo.h | 4 +++ 3 files changed, 19 insertions(+), 60 deletions(-) Index: llvm/lib/Target/IA64/IA64.td diff -u llvm/lib/Target/IA64/IA64.td:1.8 llvm/lib/Target/IA64/IA64.td:1.9 --- llvm/lib/Target/IA64/IA64.td:1.8 Wed May 17 16:18:48 2006 +++ llvm/lib/Target/IA64/IA64.td Wed May 17 19:12:11 2006 @@ -31,66 +31,6 @@ def IA64InstrInfo : InstrInfo { } def IA64 : Target { - // The following registers are always saved across calls: - let CalleeSavedRegisters = - - //'preserved' GRs: - - [ - r5 // the 'frame pointer' (base pointer) reg - - // We never generate references to these regs, so we don't need to declare - // that they are saved. In fact, we could just remove them entirely. - //r4, r6, r7, - - //'special' GRs: - -// r1, // global data pointer (GP) - XXX NOT callee saved, we do it ourselves -// r12, // memory stack pointer (SP)- XXX NOT callee saved, we do it ourselves -// rp, // return branch register (rp/b0) - we do this ourselves - // **** r13 (thread pointer) we do not touch, ever. it's not here. ****// - - //'stacked' GRs the RSE takes care of, we don't worry about -/* We don't want PEI::calculateCallerSavedRegisters to worry about them, - since the RSE takes care of them (and we determinethe appropriate - 'alloc' instructions and save/restore ar.pfs ourselves, in instruction - selection) - -************************************************************************** -* r32, r33, r34, r35, -* r36, r37, r38, r39, r40, r41, r42, r43, r44, r45, r46, r47, -* r48, r49, r50, r51, r52, r53, r54, r55, r56, r57, r58, r59, -* r60, r61, r62, r63, r64, r65, r66, r67, r68, r69, r70, r71, -* r72, r73, r74, r75, r76, r77, r78, r79, r80, r81, r82, r83, -* r84, r85, r86, r87, r88, r89, r90, r91, r92, r93, r94, r95, -* r96, r97, r98, r99, r100, r101, r102, r103, r104, r105, r106, r107, -* r108, r109, r110, r111, r112, r113, r114, r115, r116, r117, r118, r119, -* r120, r121, r122, r123, r124, r125, r126, r127, -************************************************************************** -*/ - //'preserved' FP regs: - - /* We never generate references to these regs, so we don't need to declare - * that they are saved. In fact, we could just remove them entirely. - * F2,F3,F4, F5, - * F16,F17,F18,F19,F20,F21,F22,F23, - * F24,F25,F26,F27,F28,F29,F30,F31, - */ - - //'preserved' predicate regs: - - /* We never generate references to these regs, so we don't need to declare - that they are saved. In fact, we could just remove them entirely. - p1, p2, p3, p4, p5, - p16, p17, p18, p19, p20, p21, p22, p23, - p24, p25, p26, p27, p28, p29, p30, p31, - p32, p33, p34, p35, p36, p37, p38, p39, - p40, p41, p42, p43, p44, p45, p46, p47, - p48, p49, p50, p51, p52, p53, p54, p55, - p56, p57, p58, p59, p60, p61, p62, p63 - */ - ]; - // Our instruction set let InstructionSet = IA64InstrInfo; Index: llvm/lib/Target/IA64/IA64RegisterInfo.cpp diff -u llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.19 llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.20 --- llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.19 Thu May 4 12:52:23 2006 +++ llvm/lib/Target/IA64/IA64RegisterInfo.cpp Wed May 17 19:12:11 2006 @@ -90,6 +90,21 @@ BuildMI(MBB, MI, IA64::MOV, 1, DestReg).addReg(SrcReg); } +const unsigned* IA64RegisterInfo::getCalleeSaveRegs() const { + static const unsigned CalleeSaveRegs[] = { + IA64::r5, 0 + }; + return CalleeSaveRegs; +} + +const TargetRegisterClass* const* +IA64RegisterInfo::getCalleeSaveRegClasses() const { + static const TargetRegisterClass * const CalleeSaveRegClasses[] = { + &IA64::GRRegClass, 0 + }; + return CalleeSaveRegClasses; +} + //===----------------------------------------------------------------------===// // Stack Frame Processing methods //===----------------------------------------------------------------------===// Index: llvm/lib/Target/IA64/IA64RegisterInfo.h diff -u llvm/lib/Target/IA64/IA64RegisterInfo.h:1.7 llvm/lib/Target/IA64/IA64RegisterInfo.h:1.8 --- llvm/lib/Target/IA64/IA64RegisterInfo.h:1.7 Fri Apr 7 11:34:45 2006 +++ llvm/lib/Target/IA64/IA64RegisterInfo.h Wed May 17 19:12:11 2006 @@ -40,6 +40,10 @@ unsigned DestReg, unsigned SrcReg, const TargetRegisterClass *RC) const; + const unsigned *getCalleeSaveRegs() const; + + const TargetRegisterClass* const* getCalleeSaveRegClasses() const; + void eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const; From evan.cheng at apple.com Wed May 17 19:12:38 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 17 May 2006 19:12:38 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC.td PPCRegisterInfo.cpp PPCRegisterInfo.h Message-ID: <200605180012.TAA01535@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPC.td updated: 1.16 -> 1.17 PPCRegisterInfo.cpp updated: 1.66 -> 1.67 PPCRegisterInfo.h updated: 1.14 -> 1.15 --- Log message: getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd. --- Diffs of the changes: (+71 -9) PPC.td | 9 ------ PPCRegisterInfo.cpp | 67 ++++++++++++++++++++++++++++++++++++++++++++++++++++ PPCRegisterInfo.h | 4 +++ 3 files changed, 71 insertions(+), 9 deletions(-) Index: llvm/lib/Target/PowerPC/PPC.td diff -u llvm/lib/Target/PowerPC/PPC.td:1.16 llvm/lib/Target/PowerPC/PPC.td:1.17 --- llvm/lib/Target/PowerPC/PPC.td:1.16 Wed May 17 16:19:38 2006 +++ llvm/lib/Target/PowerPC/PPC.td Wed May 17 19:12:25 2006 @@ -83,13 +83,4 @@ def PPC : Target { // Information about the instructions. let InstructionSet = PPCInstrInfo; - - - // According to the Mach-O Runtime ABI, these regs are nonvolatile across - // calls - let CalleeSavedRegisters = [R1, R13, R14, R15, R16, R17, R18, R19, - R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, F14, F15, - F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, - F30, F31, CR2, CR3, CR4, V20, V21, V22, V23, V24, V25, V26, V27, V28, - V29, V30, V31, LR]; } Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.66 llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.67 --- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.66 Wed May 10 01:38:32 2006 +++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Wed May 17 19:12:25 2006 @@ -182,6 +182,73 @@ } } +const unsigned* PPCRegisterInfo::getCalleeSaveRegs() const { + static const unsigned CalleeSaveRegs[] = { + PPC::R1, PPC::R13, + PPC::R14, PPC::R15, + PPC::R16, PPC::R17, + PPC::R18, PPC::R19, + PPC::R20, PPC::R21, + PPC::R22, PPC::R23, + PPC::R24, PPC::R25, + PPC::R26, PPC::R27, + PPC::R28, PPC::R29, + PPC::R30, PPC::R31, + PPC::F14, PPC::F15, + PPC::F16, PPC::F17, + PPC::F18, PPC::F19, + PPC::F20, PPC::F21, + PPC::F22, PPC::F23, + PPC::F24, PPC::F25, + PPC::F26, PPC::F27, + PPC::F28, PPC::F29, + PPC::F30, PPC::F31, + PPC::CR2, PPC::CR3, + PPC::CR4, PPC::V20, + PPC::V21, PPC::V22, + PPC::V23, PPC::V24, + PPC::V25, PPC::V26, + PPC::V27, PPC::V28, + PPC::V29, PPC::V30, + PPC::V31, PPC::LR, 0 + }; + return CalleeSaveRegs; +} + +const TargetRegisterClass* const* +PPCRegisterInfo::getCalleeSaveRegClasses() const { + static const TargetRegisterClass * const CalleeSaveRegClasses[] = { + &PPC::GPRCRegClass, &PPC::GPRCRegClass, + &PPC::GPRCRegClass, &PPC::GPRCRegClass, + &PPC::GPRCRegClass, &PPC::GPRCRegClass, + &PPC::GPRCRegClass, &PPC::GPRCRegClass, + &PPC::GPRCRegClass, &PPC::GPRCRegClass, + &PPC::GPRCRegClass, &PPC::GPRCRegClass, + &PPC::GPRCRegClass, &PPC::GPRCRegClass, + &PPC::GPRCRegClass, &PPC::GPRCRegClass, + &PPC::GPRCRegClass, &PPC::GPRCRegClass, + &PPC::GPRCRegClass, &PPC::GPRCRegClass, + &PPC::F8RCRegClass, &PPC::F8RCRegClass, + &PPC::F8RCRegClass, &PPC::F8RCRegClass, + &PPC::F8RCRegClass, &PPC::F8RCRegClass, + &PPC::F8RCRegClass, &PPC::F8RCRegClass, + &PPC::F8RCRegClass, &PPC::F8RCRegClass, + &PPC::F8RCRegClass, &PPC::F8RCRegClass, + &PPC::F8RCRegClass, &PPC::F8RCRegClass, + &PPC::F8RCRegClass, &PPC::F8RCRegClass, + &PPC::F8RCRegClass, &PPC::F8RCRegClass, + &PPC::CRRCRegClass, &PPC::CRRCRegClass, + &PPC::CRRCRegClass, &PPC::VRRCRegClass, + &PPC::VRRCRegClass, &PPC::VRRCRegClass, + &PPC::VRRCRegClass, &PPC::VRRCRegClass, + &PPC::VRRCRegClass, &PPC::VRRCRegClass, + &PPC::VRRCRegClass, &PPC::VRRCRegClass, + &PPC::VRRCRegClass, &PPC::VRRCRegClass, + &PPC::VRRCRegClass, &PPC::GPRCRegClass, 0 + }; + return CalleeSaveRegClasses; +} + /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into /// copy instructions, turning them into load/store instructions. MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI, Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.h diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.14 llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.15 --- llvm/lib/Target/PowerPC/PPCRegisterInfo.h:1.14 Mon Apr 17 16:07:20 2006 +++ llvm/lib/Target/PowerPC/PPCRegisterInfo.h Wed May 17 19:12:25 2006 @@ -51,6 +51,10 @@ virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, unsigned OpNum, int FrameIndex) const; + const unsigned *getCalleeSaveRegs() const; + + const TargetRegisterClass* const* getCalleeSaveRegClasses() const; + void eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const; From evan.cheng at apple.com Wed May 17 19:12:57 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 17 May 2006 19:12:57 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/Sparc.td SparcRegisterInfo.cpp SparcRegisterInfo.h Message-ID: <200605180012.TAA01554@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Sparc: Sparc.td updated: 1.12 -> 1.13 SparcRegisterInfo.cpp updated: 1.43 -> 1.44 SparcRegisterInfo.h updated: 1.12 -> 1.13 --- Log message: getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd. --- Diffs of the changes: (+16 -3) Sparc.td | 3 --- SparcRegisterInfo.cpp | 12 ++++++++++++ SparcRegisterInfo.h | 4 ++++ 3 files changed, 16 insertions(+), 3 deletions(-) Index: llvm/lib/Target/Sparc/Sparc.td diff -u llvm/lib/Target/Sparc/Sparc.td:1.12 llvm/lib/Target/Sparc/Sparc.td:1.13 --- llvm/lib/Target/Sparc/Sparc.td:1.12 Wed May 17 16:18:48 2006 +++ llvm/lib/Target/Sparc/Sparc.td Wed May 17 19:12:45 2006 @@ -75,9 +75,6 @@ //===----------------------------------------------------------------------===// def Sparc : Target { - // FIXME: Specify callee-saved registers - let CalleeSavedRegisters = []; - // Pull in Instruction Info: let InstructionSet = SparcInstrInfo; } Index: llvm/lib/Target/Sparc/SparcRegisterInfo.cpp diff -u llvm/lib/Target/Sparc/SparcRegisterInfo.cpp:1.43 llvm/lib/Target/Sparc/SparcRegisterInfo.cpp:1.44 --- llvm/lib/Target/Sparc/SparcRegisterInfo.cpp:1.43 Thu May 4 12:52:23 2006 +++ llvm/lib/Target/Sparc/SparcRegisterInfo.cpp Wed May 17 19:12:45 2006 @@ -103,6 +103,18 @@ return 0; } +const unsigned* SparcRegisterInfo::getCalleeSaveRegs() const { + static const unsigned CalleeSaveRegs[] = { 0 }; + return CalleeSaveRegs; +} + +const TargetRegisterClass* const* +SparcRegisterInfo::getCalleeSaveRegClasses() const { + static const TargetRegisterClass * const CalleeSaveRegClasses[] = { 0 }; + return CalleeSaveRegClasses; +} + + void SparcRegisterInfo:: eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { Index: llvm/lib/Target/Sparc/SparcRegisterInfo.h diff -u llvm/lib/Target/Sparc/SparcRegisterInfo.h:1.12 llvm/lib/Target/Sparc/SparcRegisterInfo.h:1.13 --- llvm/lib/Target/Sparc/SparcRegisterInfo.h:1.12 Fri Apr 7 11:34:45 2006 +++ llvm/lib/Target/Sparc/SparcRegisterInfo.h Wed May 17 19:12:45 2006 @@ -46,6 +46,10 @@ unsigned OpNum, int FrameIndex) const; + const unsigned *getCalleeSaveRegs() const; + + const TargetRegisterClass* const* getCalleeSaveRegClasses() const; + void eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const; From evan.cheng at apple.com Wed May 17 19:13:11 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 17 May 2006 19:13:11 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86.td X86RegisterInfo.cpp X86RegisterInfo.h Message-ID: <200605180013.TAA01571@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86.td updated: 1.23 -> 1.24 X86RegisterInfo.cpp updated: 1.153 -> 1.154 X86RegisterInfo.h updated: 1.38 -> 1.39 --- Log message: getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd. --- Diffs of the changes: (+28 -7) X86.td | 3 --- X86RegisterInfo.cpp | 16 ++++++++++++++++ X86RegisterInfo.h | 16 ++++++++++++---- 3 files changed, 28 insertions(+), 7 deletions(-) Index: llvm/lib/Target/X86/X86.td diff -u llvm/lib/Target/X86/X86.td:1.23 llvm/lib/Target/X86/X86.td:1.24 --- llvm/lib/Target/X86/X86.td:1.23 Wed May 17 16:20:27 2006 +++ llvm/lib/Target/X86/X86.td Wed May 17 19:12:58 2006 @@ -130,9 +130,6 @@ def X86 : Target { - // Specify the callee saved registers. - let CalleeSavedRegisters = [ESI, EDI, EBX, EBP]; - // Information about the instructions... let InstructionSet = X86InstrInfo; Index: llvm/lib/Target/X86/X86RegisterInfo.cpp diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.153 llvm/lib/Target/X86/X86RegisterInfo.cpp:1.154 --- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.153 Tue May 16 02:21:53 2006 +++ llvm/lib/Target/X86/X86RegisterInfo.cpp Wed May 17 19:12:58 2006 @@ -600,6 +600,22 @@ return NULL; } +const unsigned *X86RegisterInfo::getCalleeSaveRegs() const { + static const unsigned CalleeSaveRegs[] = { + X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0 + }; + return CalleeSaveRegs; +} + +const TargetRegisterClass* const* +X86RegisterInfo::getCalleeSaveRegClasses() const { + static const TargetRegisterClass * const CalleeSaveRegClasses[] = { + &X86::GR32RegClass, &X86::GR32RegClass, + &X86::GR32RegClass, &X86::GR32RegClass, 0 + }; + return CalleeSaveRegClasses; +} + //===----------------------------------------------------------------------===// // Stack Frame Processing methods //===----------------------------------------------------------------------===// Index: llvm/lib/Target/X86/X86RegisterInfo.h diff -u llvm/lib/Target/X86/X86RegisterInfo.h:1.38 llvm/lib/Target/X86/X86RegisterInfo.h:1.39 --- llvm/lib/Target/X86/X86RegisterInfo.h:1.38 Fri May 5 00:40:20 2006 +++ llvm/lib/Target/X86/X86RegisterInfo.h Wed May 17 19:12:58 2006 @@ -47,10 +47,18 @@ /// folding and return true, otherwise it should return false. If it folds /// the instruction, it is likely that the MachineInstruction the iterator /// references has been changed. - virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, - unsigned OpNum, - int FrameIndex) const; - + MachineInstr* foldMemoryOperand(MachineInstr* MI, + unsigned OpNum, + int FrameIndex) const; + + /// getCalleeSaveRegs - Return a null-terminated list of all of the + /// callee-save registers on this target. + const unsigned *getCalleeSaveRegs() const; + + /// getCalleeSaveRegClasses - Return a null-terminated list of the preferred + /// register classes to spill each callee-saved register with. The order and + /// length of this list match the getCalleeSaveRegs() list. + const TargetRegisterClass* const* getCalleeSaveRegClasses() const; void eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, From resistor at mac.com Wed May 17 21:10:43 2006 From: resistor at mac.com (Owen Anderson) Date: Wed, 17 May 2006 21:10:43 -0500 Subject: [llvm-commits] CVS: llvm/lib/VMCore/Module.cpp Message-ID: <200605180210.VAA02013@zion.cs.uiuc.edu> Changes in directory llvm/lib/VMCore: Module.cpp updated: 1.65 -> 1.66 --- Log message: Change Module to use TargetData-compatible strings internally. This is part of the on-going work on PR 761: http://llvm.cs.uiuc.edu/PR761 . --- Diffs of the changes: (+60 -1) Module.cpp | 61 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 files changed, 60 insertions(+), 1 deletion(-) Index: llvm/lib/VMCore/Module.cpp diff -u llvm/lib/VMCore/Module.cpp:1.65 llvm/lib/VMCore/Module.cpp:1.66 --- llvm/lib/VMCore/Module.cpp:1.65 Wed Mar 8 12:39:13 2006 +++ llvm/lib/VMCore/Module.cpp Wed May 17 21:10:31 2006 @@ -16,10 +16,12 @@ #include "llvm/Constants.h" #include "llvm/DerivedTypes.h" #include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/StringExtras.h" #include "llvm/Support/LeakDetector.h" #include "SymbolTableListTraitsImpl.h" #include #include +#include #include #include using namespace llvm; @@ -61,7 +63,7 @@ // Module::Module(const std::string &MID) - : ModuleID(MID), Endian(AnyEndianness), PtrSize(AnyPointerSize) { + : ModuleID(MID), DataLayout("") { FunctionList.setItemParent(this); FunctionList.setParent(this); GlobalList.setItemParent(this); @@ -84,6 +86,63 @@ print(std::cerr); } +/// Target endian information... +Module::Endianness Module::getEndianness() const { + std::string temp = DataLayout; + + while (temp.length() > 0) { + std::string token = getToken(temp, "-"); + + if (token[0] == 'e') { + return LittleEndian; + } else if (token[0] == 'E') { + return BigEndian; + } + } + + return AnyEndianness; +} + +void Module::setEndianness(Endianness E) { + if (DataLayout.compare("") != 0 && E != AnyEndianness) + DataLayout.insert(0, "-"); + + if (E == LittleEndian) + DataLayout.insert(0, "e"); + else if (E == BigEndian) + DataLayout.insert(0, "E"); +} + +/// Target Pointer Size information... +Module::PointerSize Module::getPointerSize() const { + std::string temp = DataLayout; + + while (temp.length() > 0) { + std::string token = getToken(temp, "-"); + char signal = getToken(token, ":")[0]; + + if (signal == 'p') { + int size = atoi(getToken(token, ":").c_str()); + if (size == 32) + return Pointer32; + else if (size == 64) + return Pointer64; + } + } + + return AnyPointerSize; +} + +void Module::setPointerSize(PointerSize PS) { + if (DataLayout.compare("") != 0 && PS != AnyPointerSize) + DataLayout.insert(0, "-"); + + if (PS == Pointer32) + DataLayout.insert(0, "p:32:32"); + else if (PS == Pointer64) + DataLayout.insert(0, "p:64:64"); +} + //===----------------------------------------------------------------------===// // Methods for easy access to the functions in the module. // From resistor at mac.com Wed May 17 21:10:44 2006 From: resistor at mac.com (Owen Anderson) Date: Wed, 17 May 2006 21:10:44 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Module.h Message-ID: <200605180210.VAA02017@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm: Module.h updated: 1.71 -> 1.72 --- Log message: Change Module to use TargetData-compatible strings internally. This is part of the on-going work on PR 761: http://llvm.cs.uiuc.edu/PR761 . --- Diffs of the changes: (+5 -6) Module.h | 11 +++++------ 1 files changed, 5 insertions(+), 6 deletions(-) Index: llvm/include/llvm/Module.h diff -u llvm/include/llvm/Module.h:1.71 llvm/include/llvm/Module.h:1.72 --- llvm/include/llvm/Module.h:1.71 Tue May 16 01:27:31 2006 +++ llvm/include/llvm/Module.h Wed May 17 21:10:31 2006 @@ -94,8 +94,7 @@ SymbolTable *SymTab; ///< Symbol Table for the module std::string ModuleID; ///< Human readable identifier for the module std::string TargetTriple; ///< Platform target triple Module compiled on - Endianness Endian; ///< Endianness assumed in the module - PointerSize PtrSize; ///< Pointer size assumed in the module + std::string DataLayout; ///< Target data description friend class Constant; @@ -123,11 +122,11 @@ /// Get the target endian information. /// @returns Endianess - an enumeration for the endianess of the target - Endianness getEndianness() const { return Endian; } + Endianness getEndianness() const; /// Get the target pointer size. /// @returns PointerSize - an enumeration for the size of the target's pointer - PointerSize getPointerSize() const { return PtrSize; } + PointerSize getPointerSize() const; /// Get any module-scope inline assembly blocks. /// @returns a string containing the module-scope inline assembly blocks. @@ -144,10 +143,10 @@ void setTargetTriple(const std::string &T) { TargetTriple = T; } /// Set the target endian information. - void setEndianness(Endianness E) { Endian = E; } + void setEndianness(Endianness E); /// Set the target pointer size. - void setPointerSize(PointerSize PS) { PtrSize = PS; } + void setPointerSize(PointerSize PS); /// Set the module-scope inline assembly blocks. void setModuleInlineAsm(const std::string &Asm) { GlobalScopeAsm = Asm; } From resistor at mac.com Thu May 18 00:46:20 2006 From: resistor at mac.com (Owen Anderson) Date: Thu, 18 May 2006 00:46:20 -0500 Subject: [llvm-commits] CVS: llvm/lib/VMCore/Module.cpp Message-ID: <200605180546.AAA02915@zion.cs.uiuc.edu> Changes in directory llvm/lib/VMCore: Module.cpp updated: 1.66 -> 1.67 --- Log message: Fix some think-o's in my last commit. Thanks to Chris for pointing them out. --- Diffs of the changes: (+18 -16) Module.cpp | 34 ++++++++++++++++++---------------- 1 files changed, 18 insertions(+), 16 deletions(-) Index: llvm/lib/VMCore/Module.cpp diff -u llvm/lib/VMCore/Module.cpp:1.66 llvm/lib/VMCore/Module.cpp:1.67 --- llvm/lib/VMCore/Module.cpp:1.66 Wed May 17 21:10:31 2006 +++ llvm/lib/VMCore/Module.cpp Thu May 18 00:46:08 2006 @@ -89,58 +89,60 @@ /// Target endian information... Module::Endianness Module::getEndianness() const { std::string temp = DataLayout; + Module::Endianness ret = AnyEndianness; - while (temp.length() > 0) { + while (!temp.empty()) { std::string token = getToken(temp, "-"); if (token[0] == 'e') { - return LittleEndian; + ret = LittleEndian; } else if (token[0] == 'E') { - return BigEndian; + ret = BigEndian; } } - return AnyEndianness; + return ret; } void Module::setEndianness(Endianness E) { - if (DataLayout.compare("") != 0 && E != AnyEndianness) - DataLayout.insert(0, "-"); + if (!DataLayout.empty() && E != AnyEndianness) + DataLayout += "-"; if (E == LittleEndian) - DataLayout.insert(0, "e"); + DataLayout += "e"; else if (E == BigEndian) - DataLayout.insert(0, "E"); + DataLayout += "E"; } /// Target Pointer Size information... Module::PointerSize Module::getPointerSize() const { std::string temp = DataLayout; + Module::PointerSize ret = AnyPointerSize; - while (temp.length() > 0) { + while (!temp.empty()) { std::string token = getToken(temp, "-"); char signal = getToken(token, ":")[0]; if (signal == 'p') { int size = atoi(getToken(token, ":").c_str()); if (size == 32) - return Pointer32; + ret = Pointer32; else if (size == 64) - return Pointer64; + ret = Pointer64; } } - return AnyPointerSize; + return ret; } void Module::setPointerSize(PointerSize PS) { - if (DataLayout.compare("") != 0 && PS != AnyPointerSize) - DataLayout.insert(0, "-"); + if (!DataLayout.empty() && PS != AnyPointerSize) + DataLayout += "-"; if (PS == Pointer32) - DataLayout.insert(0, "p:32:32"); + DataLayout += "p:32:32"; else if (PS == Pointer64) - DataLayout.insert(0, "p:64:64"); + DataLayout += "p:64:64"; } //===----------------------------------------------------------------------===// From evan.cheng at apple.com Thu May 18 01:27:27 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 18 May 2006 01:27:27 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86.td X86InstrInfo.h Message-ID: <200605180627.BAA03044@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86.td updated: 1.24 -> 1.25 X86InstrInfo.h updated: 1.50 -> 1.51 --- Log message: ImmMask should be 3 for a two-bit field; Compact X86II --- Diffs of the changes: (+3 -4) X86.td | 2 +- X86InstrInfo.h | 5 ++--- 2 files changed, 3 insertions(+), 4 deletions(-) Index: llvm/lib/Target/X86/X86.td diff -u llvm/lib/Target/X86/X86.td:1.24 llvm/lib/Target/X86/X86.td:1.25 --- llvm/lib/Target/X86/X86.td:1.24 Wed May 17 19:12:58 2006 +++ llvm/lib/Target/X86/X86.td Thu May 18 01:27:15 2006 @@ -114,7 +114,7 @@ 7, 11, 13, - 17]; + 16]; } // The X86 target supports two different syntaxes for emitting machine code. Index: llvm/lib/Target/X86/X86InstrInfo.h diff -u llvm/lib/Target/X86/X86InstrInfo.h:1.50 llvm/lib/Target/X86/X86InstrInfo.h:1.51 --- llvm/lib/Target/X86/X86InstrInfo.h:1.50 Thu Feb 2 14:12:32 2006 +++ llvm/lib/Target/X86/X86InstrInfo.h Thu May 18 01:27:15 2006 @@ -120,7 +120,7 @@ // This two-bit field describes the size of an immediate operand. Zero is // unused so that we can tell if we forgot to set a value. ImmShift = 11, - ImmMask = 7 << ImmShift, + ImmMask = 3 << ImmShift, Imm8 = 1 << ImmShift, Imm16 = 2 << ImmShift, Imm32 = 3 << ImmShift, @@ -161,8 +161,7 @@ // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. SpecialFP = 7 << FPTypeShift, - // Bit 15 is unused. - OpcodeShift = 17, + OpcodeShift = 16, OpcodeMask = 0xFF << OpcodeShift, // Bits 25 -> 31 are unused }; From alenhar2 at cs.uiuc.edu Thu May 18 12:29:58 2006 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Thu, 18 May 2006 12:29:58 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp Message-ID: <200605181729.MAA17442@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Alpha: AlphaISelDAGToDAG.cpp updated: 1.39 -> 1.40 --- Log message: Fix a bogus gcc warning --- Diffs of the changes: (+2 -2) AlphaISelDAGToDAG.cpp | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp diff -u llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.39 llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.40 --- llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.39 Sat Apr 8 00:38:03 2006 +++ llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp Thu May 18 12:29:34 2006 @@ -377,8 +377,8 @@ break; case ISD::AND: { - ConstantSDNode* SC; - ConstantSDNode* MC; + ConstantSDNode* SC = NULL; + ConstantSDNode* MC = NULL; if (N->getOperand(0).getOpcode() == ISD::SRL && (MC = dyn_cast(N->getOperand(1))) && (SC = dyn_cast(N->getOperand(0).getOperand(1)))) From lattner at cs.uiuc.edu Thu May 18 12:38:28 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 18 May 2006 12:38:28 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/README.txt Message-ID: <200605181738.MAA17545@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: README.txt updated: 1.106 -> 1.107 --- Log message: add a note --- Diffs of the changes: (+15 -0) README.txt | 15 +++++++++++++++ 1 files changed, 15 insertions(+) Index: llvm/lib/Target/X86/README.txt diff -u llvm/lib/Target/X86/README.txt:1.106 llvm/lib/Target/X86/README.txt:1.107 --- llvm/lib/Target/X86/README.txt:1.106 Wed May 17 16:20:51 2006 +++ llvm/lib/Target/X86/README.txt Thu May 18 12:38:16 2006 @@ -380,6 +380,21 @@ This may just be a matter of using 'test' to write bigger patterns for X86cmp. +An important case is comparison against zero: + +if (X == 0) ... + +instead of: + + cmpl $0, %eax + je LBB4_2 #cond_next + +use: + test %eax, %eax + jz LBB4_2 + +which is smaller. + //===---------------------------------------------------------------------===// SSE should implement 'select_cc' using 'emulated conditional moves' that use From lattner at cs.uiuc.edu Thu May 18 13:26:25 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Thu, 18 May 2006 13:26:25 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/README.txt Message-ID: <200605181826.NAA17769@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target: README.txt updated: 1.29 -> 1.30 --- Log message: add a note --- Diffs of the changes: (+18 -0) README.txt | 18 ++++++++++++++++++ 1 files changed, 18 insertions(+) Index: llvm/lib/Target/README.txt diff -u llvm/lib/Target/README.txt:1.29 llvm/lib/Target/README.txt:1.30 --- llvm/lib/Target/README.txt:1.29 Thu Apr 20 13:49:28 2006 +++ llvm/lib/Target/README.txt Thu May 18 13:26:13 2006 @@ -190,3 +190,21 @@ better than that to see this. //===---------------------------------------------------------------------===// + +Add support for conditional increments, and other related patterns. Instead +of: + + movl 136(%esp), %eax + cmpl $0, %eax + je LBB16_2 #cond_next +LBB16_1: #cond_true + incl _foo +LBB16_2: #cond_next + +emit: + movl _foo, %eax + cmpl $1, %edi + sbbl $-1, %eax + movl %eax, _foo + +//===---------------------------------------------------------------------===// From reid at x10sys.com Thu May 18 14:42:29 2006 From: reid at x10sys.com (Reid Spencer) Date: Thu, 18 May 2006 14:42:29 -0500 Subject: [llvm-commits] CVS: llvm/test/lib/llvm-dg.exp Message-ID: <200605181942.OAA18259@zion.cs.uiuc.edu> Changes in directory llvm/test/lib: llvm-dg.exp updated: 1.13 -> 1.14 --- Log message: Improve error output. Use the third parameter of the "catch" command to capture the error output from the exec option. This generally will capture the stderr messages generated by the tools. This information is then printed if the test fails. This helps to recognize more quickly what the error was. Otherwise, this information is lost. --- Diffs of the changes: (+3 -3) llvm-dg.exp | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) Index: llvm/test/lib/llvm-dg.exp diff -u llvm/test/lib/llvm-dg.exp:1.13 llvm/test/lib/llvm-dg.exp:1.14 --- llvm/test/lib/llvm-dg.exp:1.13 Wed Apr 12 16:57:40 2006 +++ llvm/test/lib/llvm-dg.exp Thu May 18 14:42:16 2006 @@ -93,7 +93,7 @@ } else { #run script and catch errors - set retval [ catch {exec /bin/sh $script >& $output} ] + set retval [ catch {exec /bin/sh $script >& $output} errmsg ] if { $retval == 1 } { #Get output @@ -105,10 +105,10 @@ switch $outcome { PASS { file delete $output - fail "$test: \n$result" + fail "$test: \n$errmsg\n$result" } XFAIL { - xfail "$test: \n$result" + xfail "$test: \n$errmsg\n$result" } default { file delete $output From evan.cheng at apple.com Thu May 18 15:42:20 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 18 May 2006 15:42:20 -0500 Subject: [llvm-commits] CVS: llvm/utils/TableGen/InstrInfoEmitter.cpp Message-ID: <200605182042.PAA18668@zion.cs.uiuc.edu> Changes in directory llvm/utils/TableGen: InstrInfoEmitter.cpp updated: 1.41 -> 1.42 --- Log message: lib/Target/Target.td --- Diffs of the changes: (+7 -5) InstrInfoEmitter.cpp | 12 +++++++----- 1 files changed, 7 insertions(+), 5 deletions(-) Index: llvm/utils/TableGen/InstrInfoEmitter.cpp diff -u llvm/utils/TableGen/InstrInfoEmitter.cpp:1.41 llvm/utils/TableGen/InstrInfoEmitter.cpp:1.42 --- llvm/utils/TableGen/InstrInfoEmitter.cpp:1.41 Fri May 12 02:47:00 2006 +++ llvm/utils/TableGen/InstrInfoEmitter.cpp Thu May 18 15:42:07 2006 @@ -139,11 +139,13 @@ for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i) { Record *RC = OperandInfo[i]; // FIXME: We only care about register operands for now. - if (RC && RC->isSubClassOf("RegisterClass")) { - OS << "{ &" << getQualifiedName(RC) << "RegClass }, "; - } else { - OS << "{ 0 }, "; - } + if (RC && RC->isSubClassOf("RegisterClass")) + OS << "{ &" << getQualifiedName(RC) << "RegClass, 0 }, "; + else if (RC && RC->getName() == "ptr_rc") + // Ptr value whose register class is resolved via callback. + OS << "{ 0, 1 }, "; + else + OS << "{ 0, 0 }, "; } OS << "};\n"; } From evan.cheng at apple.com Thu May 18 15:42:20 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 18 May 2006 15:42:20 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetInstrInfo.h Message-ID: <200605182042.PAA18673@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/Target: TargetInstrInfo.h updated: 1.86 -> 1.87 --- Log message: lib/Target/Target.td --- Diffs of the changes: (+20 -1) TargetInstrInfo.h | 21 ++++++++++++++++++++- 1 files changed, 20 insertions(+), 1 deletion(-) Index: llvm/include/llvm/Target/TargetInstrInfo.h diff -u llvm/include/llvm/Target/TargetInstrInfo.h:1.86 llvm/include/llvm/Target/TargetInstrInfo.h:1.87 --- llvm/include/llvm/Target/TargetInstrInfo.h:1.86 Thu May 11 20:58:24 2006 +++ llvm/include/llvm/Target/TargetInstrInfo.h Thu May 18 15:42:07 2006 @@ -76,6 +76,11 @@ // block. const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 11; +// Machine operand flags +// M_LOOK_UP_PTR_REG_CLASS - Set if this operand is a pointer value and it +// requires a callback to look up its register class. +const unsigned M_LOOK_UP_PTR_REG_CLASS = 1 << 0; + /// TargetOperandInfo - This holds information about one operand of a machine /// instruction, indicating the register class for register operands, etc. /// @@ -84,7 +89,7 @@ /// RegClass - This specifies the register class of the operand if the /// operand is a register. If not, this contains null. const TargetRegisterClass *RegClass; - + unsigned Flags; /// Currently no other information. }; @@ -137,6 +142,13 @@ return get(Opcode).Name; } + const TargetRegisterClass + *getInstrOperandRegClass(const TargetInstrDescriptor *II, unsigned Op) const { + const TargetOperandInfo &toi = II->OpInfo[Op]; + return (toi.Flags & M_LOOK_UP_PTR_REG_CLASS) + ? getPointerRegClass() : toi.RegClass; + } + int getNumOperands(MachineOpCode Opcode) const { return get(Opcode).numOperands; } @@ -275,6 +287,13 @@ assert(0 && "Target didn't implement insertNoop!"); abort(); } + + /// getPointerRegClass - Returns a TargetRegisterClass used for pointer + /// values. + virtual const TargetRegisterClass *getPointerRegClass() const { + assert(0 && "Target didn't implement getPointerRegClass!"); + abort(); + } /// hasDelaySlot - Returns true if the specified instruction has a delay slot /// which must be filled by the code generator. From evan.cheng at apple.com Thu May 18 15:42:21 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 18 May 2006 15:42:21 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Message-ID: <200605182042.PAA18677@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: ScheduleDAG.cpp updated: 1.92 -> 1.93 --- Log message: lib/Target/Target.td --- Diffs of the changes: (+13 -12) ScheduleDAG.cpp | 25 +++++++++++++------------ 1 files changed, 13 insertions(+), 12 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.92 llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.93 --- llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.92 Tue May 16 01:10:57 2006 +++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Thu May 18 15:42:07 2006 @@ -229,16 +229,17 @@ static unsigned CreateVirtualRegisters(MachineInstr *MI, unsigned NumResults, SSARegMap *RegMap, + const TargetInstrInfo *TII, const TargetInstrDescriptor &II) { // Create the result registers for this node and add the result regs to // the machine instruction. - const TargetOperandInfo *OpInfo = II.OpInfo; - unsigned ResultReg = RegMap->createVirtualRegister(OpInfo[0].RegClass); + unsigned ResultReg = + RegMap->createVirtualRegister(TII->getInstrOperandRegClass(&II, 0)); MI->addRegOperand(ResultReg, MachineOperand::Def); for (unsigned i = 1; i != NumResults; ++i) { - assert(OpInfo[i].RegClass && "Isn't a register operand!"); - MI->addRegOperand(RegMap->createVirtualRegister(OpInfo[i].RegClass), - MachineOperand::Def); + const TargetRegisterClass *RC = TII->getInstrOperandRegClass(&II, i); + assert(RC && "Isn't a register operand!"); + MI->addRegOperand(RegMap->createVirtualRegister(RC), MachineOperand::Def); } return ResultReg; } @@ -275,9 +276,9 @@ // Verify that it is right. assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); if (II) { - assert(II->OpInfo[IIOpNum].RegClass && - "Don't have operand info for this instruction!"); - assert(RegMap->getRegClass(VReg) == II->OpInfo[IIOpNum].RegClass && + const TargetRegisterClass *RC = TII->getInstrOperandRegClass(II, IIOpNum); + assert(RC && "Don't have operand info for this instruction!"); + assert(RegMap->getRegClass(VReg) == RC && "Register class of operand and regclass of use don't agree!"); } } else if (ConstantSDNode *C = @@ -332,9 +333,9 @@ // Verify that it is right. assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); if (II) { - assert(II->OpInfo[IIOpNum].RegClass && - "Don't have operand info for this instruction!"); - assert(RegMap->getRegClass(VReg) == II->OpInfo[IIOpNum].RegClass && + const TargetRegisterClass *RC = TII->getInstrOperandRegClass(II, IIOpNum); + assert(RC && "Don't have operand info for this instruction!"); + assert(RegMap->getRegClass(VReg) == RC && "Register class of operand and regclass of use don't agree!"); } } @@ -387,7 +388,7 @@ // Otherwise, create new virtual registers. if (NumResults && VRBase == 0) - VRBase = CreateVirtualRegisters(MI, NumResults, RegMap, II); + VRBase = CreateVirtualRegisters(MI, NumResults, RegMap, TII, II); // Emit all of the actual operands of this instruction, adding them to the // instruction as appropriate. From evan.cheng at apple.com Thu May 18 15:44:38 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 18 May 2006 15:44:38 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Target.td Message-ID: <200605182044.PAA18694@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target: Target.td updated: 1.83 -> 1.84 --- Log message: Added a Flags field to TargetOperandInfo. Currently the only flag is M_LOOK_UP_PTR_REG_CLASS which allows the register class of the operand to be resolved via a callback at runtime. --- Diffs of the changes: (+6 -0) Target.td | 6 ++++++ 1 files changed, 6 insertions(+) Index: llvm/lib/Target/Target.td diff -u llvm/lib/Target/Target.td:1.83 llvm/lib/Target/Target.td:1.84 --- llvm/lib/Target/Target.td:1.83 Wed May 17 19:09:53 2006 +++ llvm/lib/Target/Target.td Thu May 18 15:44:26 2006 @@ -189,6 +189,12 @@ /// of operands. def variable_ops; +/// ptr_rc definition - Mark this operand as being a pointer value whose +/// register class is resolved dynamically via a callback to TargetInstrInfo. +/// FIXME: We should probably change this to a class which contain a list of +/// flags. But currently we have but one flag. +def ptr_rc; + /// Operand Types - These provide the built-in operand types that may be used /// by a target. Targets can optionally provide their own operand types as /// needed, though this should not be needed for RISC targets. From rafael.espindola at gmail.com Thu May 18 16:46:02 2006 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Thu, 18 May 2006 16:46:02 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp ARMInstrInfo.td ARMRegisterInfo.cpp Message-ID: <200605182146.QAA19279@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/ARM: ARMISelDAGToDAG.cpp updated: 1.2 -> 1.3 ARMInstrInfo.td updated: 1.1 -> 1.2 ARMRegisterInfo.cpp updated: 1.2 -> 1.3 --- Log message: implement movri add a stub LowerFORMAL_ARGUMENTS --- Diffs of the changes: (+14 -3) ARMISelDAGToDAG.cpp | 6 ++++++ ARMInstrInfo.td | 9 +++++++-- ARMRegisterInfo.cpp | 2 +- 3 files changed, 14 insertions(+), 3 deletions(-) Index: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp diff -u llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.2 llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.3 --- llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.2 Mon May 15 17:34:39 2006 +++ llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp Thu May 18 16:45:49 2006 @@ -81,11 +81,17 @@ return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); } +static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) { + assert(0 && "Not implemented"); +} + SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { switch (Op.getOpcode()) { default: assert(0 && "Should not custom lower this!"); abort(); + case ISD::FORMAL_ARGUMENTS: + return LowerFORMAL_ARGUMENTS(Op, DAG); case ISD::RET: return LowerRET(Op, DAG); } Index: llvm/lib/Target/ARM/ARMInstrInfo.td diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.1 llvm/lib/Target/ARM/ARMInstrInfo.td:1.2 --- llvm/lib/Target/ARM/ARMInstrInfo.td:1.1 Sun May 14 17:18:28 2006 +++ llvm/lib/Target/ARM/ARMInstrInfo.td Thu May 18 16:45:49 2006 @@ -42,6 +42,8 @@ "!ADJCALLSTACKDOWN $amt", [(callseq_start imm:$amt)]>; +def BX: InstARM<(ops), "bx", [(retflag)]>; + def ldr : InstARM<(ops IntRegs:$dst, IntRegs:$addr), "ldr $dst, [$addr]", [(set IntRegs:$dst, (load IntRegs:$addr))]>; @@ -50,5 +52,8 @@ "str $src, [$addr]", [(store IntRegs:$src, IntRegs:$addr)]>; -def mov : InstARM<(ops IntRegs:$dst, IntRegs:$b), - "mov $dst, $b", []>; +def movrr : InstARM<(ops IntRegs:$dst, IntRegs:$src), + "mov $dst, $src", []>; + +def movri : InstARM<(ops IntRegs:$dst, i32imm:$src), + "mov $dst, $src", [(set IntRegs:$dst, imm:$src)]>; Index: llvm/lib/Target/ARM/ARMRegisterInfo.cpp diff -u llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.2 llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.3 --- llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.2 Wed May 17 19:11:26 2006 +++ llvm/lib/Target/ARM/ARMRegisterInfo.cpp Thu May 18 16:45:49 2006 @@ -49,7 +49,7 @@ unsigned DestReg, unsigned SrcReg, const TargetRegisterClass *RC) const { assert (RC == ARM::IntRegsRegisterClass); - BuildMI(MBB, I, ARM::mov, 1, DestReg).addReg(SrcReg); + BuildMI(MBB, I, ARM::movrr, 1, DestReg).addReg(SrcReg); } MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr* MI, From evan.cheng at apple.com Fri May 19 02:24:44 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 19 May 2006 02:24:44 -0500 Subject: [llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp Message-ID: <200605190724.CAA26820@zion.cs.uiuc.edu> Changes in directory llvm/utils/TableGen: DAGISelEmitter.cpp updated: 1.204 -> 1.205 --- Log message: Now that iPTR is a fully resolved type. We end up losing the type check for patterns that look like this: def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>; InsertOneTypeCheck should copy the type from the resolved pattern to the unresolved one as long as there types are different. --- Diffs of the changes: (+1 -1) DAGISelEmitter.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/utils/TableGen/DAGISelEmitter.cpp diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.204 llvm/utils/TableGen/DAGISelEmitter.cpp:1.205 --- llvm/utils/TableGen/DAGISelEmitter.cpp:1.204 Wed May 17 15:37:59 2006 +++ llvm/utils/TableGen/DAGISelEmitter.cpp Fri May 19 02:24:32 2006 @@ -2808,7 +2808,7 @@ bool InsertOneTypeCheck(TreePatternNode *Pat, TreePatternNode *Other, const std::string &Prefix) { // Did we find one? - if (!Pat->hasTypeSet()) { + if (Pat->getExtTypes() != Other->getExtTypes()) { // Move a type over from 'other' to 'pat'. Pat->setTypes(Other->getExtTypes()); emitCheck(Prefix + ".Val->getValueType(0) == MVT::" + From evan.cheng at apple.com Fri May 19 02:30:51 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 19 May 2006 02:30:51 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.td Message-ID: <200605190730.CAA29009@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrInfo.td updated: 1.268 -> 1.269 --- Log message: Explicitly specify MOV32mi can only be used store 32-bit GV, etc. --- Diffs of the changes: (+2 -2) X86InstrInfo.td | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/Target/X86/X86InstrInfo.td diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.268 llvm/lib/Target/X86/X86InstrInfo.td:1.269 --- llvm/lib/Target/X86/X86InstrInfo.td:1.268 Wed May 17 16:21:41 2006 +++ llvm/lib/Target/X86/X86InstrInfo.td Fri May 19 02:30:36 2006 @@ -2360,9 +2360,9 @@ def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)), (ADD32ri GR32:$src1, texternalsym:$src2)>; -def : Pat<(store (X86Wrapper tglobaladdr:$src), addr:$dst), +def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst), (MOV32mi addr:$dst, tglobaladdr:$src)>; -def : Pat<(store (X86Wrapper texternalsym:$src), addr:$dst), +def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst), (MOV32mi addr:$dst, texternalsym:$src)>; // Calls From lattner at cs.uiuc.edu Fri May 19 12:17:37 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 19 May 2006 12:17:37 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Analysis/Dominators.h Message-ID: <200605191717.MAA03614@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/Analysis: Dominators.h updated: 1.54 -> 1.55 --- Log message: Use class tags instead of struct tags. The coding standards specify this for public classes for improved win32 compatibility. --- Diffs of the changes: (+18 -9) Dominators.h | 27 ++++++++++++++++++--------- 1 files changed, 18 insertions(+), 9 deletions(-) Index: llvm/include/llvm/Analysis/Dominators.h diff -u llvm/include/llvm/Analysis/Dominators.h:1.54 llvm/include/llvm/Analysis/Dominators.h:1.55 --- llvm/include/llvm/Analysis/Dominators.h:1.54 Mon Mar 20 13:32:48 2006 +++ llvm/include/llvm/Analysis/Dominators.h Fri May 19 12:17:12 2006 @@ -140,7 +140,8 @@ /// ImmediateDominators Class - Concrete subclass of ImmediateDominatorsBase /// that is used to compute a normal immediate dominator set. /// -struct ImmediateDominators : public ImmediateDominatorsBase { +class ImmediateDominators : public ImmediateDominatorsBase { +public: ImmediateDominators() : ImmediateDominatorsBase(false) {} BasicBlock *getRoot() const { @@ -169,7 +170,8 @@ /// is unreachable in this function, the set will be empty. This cannot happen /// for reachable code, because every block dominates at least itself. /// -struct DominatorSetBase : public DominatorBase { +class DominatorSetBase : public DominatorBase { +public: typedef std::set DomSetType; // Dom set for a bb // Map of dom sets typedef std::map DomSetMapType; @@ -255,7 +257,8 @@ /// DominatorSet Class - Concrete subclass of DominatorSetBase that is used to /// compute a normal dominator set. /// -struct DominatorSet : public DominatorSetBase { +class DominatorSet : public DominatorSetBase { +public: DominatorSet() : DominatorSetBase(false) {} virtual bool runOnFunction(Function &F); @@ -280,7 +283,8 @@ //===----------------------------------------------------------------------===// /// DominatorTree - Calculate the immediate dominator tree for a function. /// -struct DominatorTreeBase : public DominatorBase { +class DominatorTreeBase : public DominatorBase { +public: class Node; protected: std::map Nodes; @@ -395,7 +399,8 @@ /// ET-Forest Class - Class used to construct forwards and backwards /// ET-Forests /// -struct ETForestBase : public DominatorBase { +class ETForestBase : public DominatorBase { +public: ETForestBase(bool isPostDom) : DominatorBase(isPostDom), Nodes(), DFSInfoValid(false), SlowQueries(0) {} @@ -491,7 +496,8 @@ /// ETForest Class - Concrete subclass of ETForestBase that is used to /// compute a forwards ET-Forest. -struct ETForest : public ETForestBase { +class ETForest : public ETForestBase { +public: ETForest() : ETForestBase(false) {} BasicBlock *getRoot() const { @@ -515,7 +521,8 @@ /// DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to /// compute a normal dominator tree. /// -struct DominatorTree : public DominatorTreeBase { +class DominatorTree : public DominatorTreeBase { +public: DominatorTree() : DominatorTreeBase(false) {} BasicBlock *getRoot() const { @@ -569,7 +576,8 @@ //===----------------------------------------------------------------------===// /// DominanceFrontier - Calculate the dominance frontiers for a function. /// -struct DominanceFrontierBase : public DominatorBase { +class DominanceFrontierBase : public DominatorBase { +public: typedef std::set DomSetType; // Dom set for a bb typedef std::map DomSetMapType; // Dom set map protected: @@ -615,7 +623,8 @@ /// DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to /// compute a normal dominator tree. /// -struct DominanceFrontier : public DominanceFrontierBase { +class DominanceFrontier : public DominanceFrontierBase { +public: DominanceFrontier() : DominanceFrontierBase(false) {} BasicBlock *getRoot() const { From evan.cheng at apple.com Fri May 19 13:41:07 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 19 May 2006 13:41:07 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.td Message-ID: <200605191841.NAA01117@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrInfo.td updated: 1.269 -> 1.270 --- Log message: - Use exact-width integer types, e.g. int32_t, to avoid confusion. - Fix a couple of minor bugs in i16immSExt8 and i16immZExt8. - Added loadiPTR fragment used for indirect jumps and calls. --- Diffs of the changes: (+9 -8) X86InstrInfo.td | 17 +++++++++-------- 1 files changed, 9 insertions(+), 8 deletions(-) Index: llvm/lib/Target/X86/X86InstrInfo.td diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.269 llvm/lib/Target/X86/X86InstrInfo.td:1.270 --- llvm/lib/Target/X86/X86InstrInfo.td:1.269 Fri May 19 02:30:36 2006 +++ llvm/lib/Target/X86/X86InstrInfo.td Fri May 19 13:40:54 2006 @@ -268,22 +268,24 @@ def i16immSExt8 : PatLeaf<(i16 imm), [{ // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit // sign extended field. - return (int)N->getValue() == (signed char)N->getValue(); + return (int16_t)N->getValue() == (int8_t)N->getValue(); }]>; def i32immSExt8 : PatLeaf<(i32 imm), [{ // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit // sign extended field. - return (int)N->getValue() == (signed char)N->getValue(); + return (int32_t)N->getValue() == (int8_t)N->getValue(); }]>; def i16immZExt8 : PatLeaf<(i16 imm), [{ // i16immZExt8 predicate - True if the 16-bit immediate fits in a 8-bit zero // extended field. - return (unsigned)N->getValue() == (unsigned char)N->getValue(); + return (uint16_t)N->getValue() == (uint8_t)N->getValue(); }]>; // Helper fragments for loads. +def loadiPTR : PatFrag<(ops node:$ptr), (iPTR (load node:$ptr))>; + def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>; def loadi16 : PatFrag<(ops node:$ptr), (i16 (load node:$ptr))>; def loadi32 : PatFrag<(ops node:$ptr), (i32 (load node:$ptr))>; @@ -390,7 +392,7 @@ def JMP32r : I<0xFF, MRM4r, (ops GR32:$dst), "jmp{l} {*}$dst", [(brind GR32:$dst)]>; def JMP32m : I<0xFF, MRM4m, (ops i32mem:$dst), "jmp{l} {*}$dst", - [(brind (loadi32 addr:$dst))]>; + [(brind (loadiPTR addr:$dst))]>; } // Conditional branches @@ -441,7 +443,7 @@ def CALL32r : I<0xFF, MRM2r, (ops GR32:$dst), "call {*}$dst", [(X86call GR32:$dst)]>; def CALL32m : I<0xFF, MRM2m, (ops i32mem:$dst), "call {*}$dst", - [(X86call (loadi32 addr:$dst))]>; + [(X86call (loadiPTR addr:$dst))]>; } // Tail call stuff. @@ -1743,8 +1745,6 @@ def ADD32ri : Ii32<0x81, MRM0r, (ops GR32:$dst, GR32:$src1, i32imm:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, imm:$src2))]>; -} - def ADD16ri8 : Ii8<0x83, MRM0r, (ops GR16:$dst, GR16:$src1, i16i8imm:$src2), "add{w} {$src2, $dst|$dst, $src2}", [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2))]>, @@ -1752,6 +1752,7 @@ def ADD32ri8 : Ii8<0x83, MRM0r, (ops GR32:$dst, GR32:$src1, i32i8imm:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2))]>; +} let isTwoAddress = 0 in { def ADD8mr : I<0x00, MRMDestMem, (ops i8mem :$dst, GR8 :$src2), @@ -2369,7 +2370,7 @@ def : Pat<(X86tailcall GR32:$dst), (CALL32r GR32:$dst)>; -def : Pat<(X86tailcall (loadi32 addr:$dst)), +def : Pat<(X86tailcall (loadiPTR addr:$dst)), (CALL32m addr:$dst)>; def : Pat<(X86tailcall tglobaladdr:$dst), From evan.cheng at apple.com Fri May 19 13:43:53 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 19 May 2006 13:43:53 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.cpp Message-ID: <200605191843.NAA01149@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrInfo.cpp updated: 1.51 -> 1.52 --- Log message: These can be transformed into lea as well. Not that we use this feature currently... --- Diffs of the changes: (+2 -0) X86InstrInfo.cpp | 2 ++ 1 files changed, 2 insertions(+) Index: llvm/lib/Target/X86/X86InstrInfo.cpp diff -u llvm/lib/Target/X86/X86InstrInfo.cpp:1.51 llvm/lib/Target/X86/X86InstrInfo.cpp:1.52 --- llvm/lib/Target/X86/X86InstrInfo.cpp:1.51 Thu May 11 02:33:49 2006 +++ llvm/lib/Target/X86/X86InstrInfo.cpp Fri May 19 13:43:41 2006 @@ -152,12 +152,14 @@ return addRegReg(BuildMI(X86::LEA16r, 5, Dest), Src, MI->getOperand(2).getReg()); case X86::ADD32ri: + case X86::ADD32ri8: assert(MI->getNumOperands() == 3 && "Unknown add instruction!"); if (MI->getOperand(2).isImmediate()) return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src, MI->getOperand(2).getImmedValue()); return 0; case X86::ADD16ri: + case X86::ADD16ri8: if (DisableLEA16) return 0; assert(MI->getNumOperands() == 3 && "Unknown add instruction!"); if (MI->getOperand(2).isImmediate()) From reid at x10sys.com Fri May 19 14:08:08 2006 From: reid at x10sys.com (Reid Spencer) Date: Fri, 19 May 2006 14:08:08 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Instructions.h Message-ID: <200605191908.OAA01300@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm: Instructions.h updated: 1.35 -> 1.36 --- Log message: Fix some doxygen usage in these headers. --- Diffs of the changes: (+2 -2) Instructions.h | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/include/llvm/Instructions.h diff -u llvm/include/llvm/Instructions.h:1.35 llvm/include/llvm/Instructions.h:1.36 --- llvm/include/llvm/Instructions.h:1.35 Tue May 9 23:38:35 2006 +++ llvm/include/llvm/Instructions.h Fri May 19 14:07:54 2006 @@ -927,7 +927,7 @@ /// unsigned getNumIncomingValues() const { return getNumOperands()/2; } - /// getIncomingValue - Return incoming value #x + /// getIncomingValue - Return incoming value number x /// Value *getIncomingValue(unsigned i) const { assert(i*2 < getNumOperands() && "Invalid value number!"); @@ -941,7 +941,7 @@ return i*2; } - /// getIncomingBlock - Return incoming basic block #x + /// getIncomingBlock - Return incoming basic block number x /// BasicBlock *getIncomingBlock(unsigned i) const { return reinterpret_cast(getOperand(i*2+1)); From reid at x10sys.com Fri May 19 14:08:09 2006 From: reid at x10sys.com (Reid Spencer) Date: Fri, 19 May 2006 14:08:09 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/System/DynamicLibrary.h Program.h Message-ID: <200605191908.OAA01306@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/System: DynamicLibrary.h updated: 1.5 -> 1.6 Program.h updated: 1.8 -> 1.9 --- Log message: Fix some doxygen usage in these headers. --- Diffs of the changes: (+4 -5) DynamicLibrary.h | 2 +- Program.h | 7 +++---- 2 files changed, 4 insertions(+), 5 deletions(-) Index: llvm/include/llvm/System/DynamicLibrary.h diff -u llvm/include/llvm/System/DynamicLibrary.h:1.5 llvm/include/llvm/System/DynamicLibrary.h:1.6 --- llvm/include/llvm/System/DynamicLibrary.h:1.5 Sun Jan 29 22:33:51 2006 +++ llvm/include/llvm/System/DynamicLibrary.h Fri May 19 14:07:54 2006 @@ -45,7 +45,7 @@ DynamicLibrary(); /// This is the constructor for DynamicLibrary instances. It will open - /// the dynamic library specified by the \filename Path. + /// the dynamic library specified by the filename Path. /// @throws std::string indicating why the library couldn't be opened. /// @brief Open a dynamic library. DynamicLibrary(const char* filename); Index: llvm/include/llvm/System/Program.h diff -u llvm/include/llvm/System/Program.h:1.8 llvm/include/llvm/System/Program.h:1.9 --- llvm/include/llvm/System/Program.h:1.8 Sun Jan 8 16:41:22 2006 +++ llvm/include/llvm/System/Program.h Fri May 19 14:07:54 2006 @@ -46,9 +46,6 @@ /// environment and other configuration settings of the invoking program. /// If Path::executable() does not return true when this function is /// called then a std::string is thrown. - /// @param path A sys::Path object providing the path of the program to be - /// executed. It is presumed this is the result of the FindProgramByName - /// method. /// @returns an integer result code indicating the status of the program. /// A zero or positive value indicates the result code of the program. A /// negative value is the signal number on which it terminated. @@ -57,7 +54,9 @@ /// @see FindProgrambyName /// @brief Executes the program with the given set of \p args. static int ExecuteAndWait( - const Path& path, ///< The path to the program to execute + const Path& path, ///< sys::Path object providing the path of the + ///< program to be executed. It is presumed this is the result of + ///< the FindProgramByName method. const char** args, ///< A vector of strings that are passed to the ///< program. The first element should be the name of the program. ///< The list *must* be terminated by a null char* entry. From reid at x10sys.com Fri May 19 14:08:09 2006 From: reid at x10sys.com (Reid Spencer) Date: Fri, 19 May 2006 14:08:09 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Assembly/AutoUpgrade.h Message-ID: <200605191908.OAA01310@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/Assembly: AutoUpgrade.h updated: 1.6 -> 1.7 --- Log message: Fix some doxygen usage in these headers. --- Diffs of the changes: (+4 -2) AutoUpgrade.h | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-) Index: llvm/include/llvm/Assembly/AutoUpgrade.h diff -u llvm/include/llvm/Assembly/AutoUpgrade.h:1.6 llvm/include/llvm/Assembly/AutoUpgrade.h:1.7 --- llvm/include/llvm/Assembly/AutoUpgrade.h:1.6 Sat Mar 25 12:42:45 2006 +++ llvm/include/llvm/Assembly/AutoUpgrade.h Fri May 19 14:07:54 2006 @@ -43,9 +43,11 @@ /// if it is a call to an old overloaded intrinsic. If it is, a new CallInst /// is created that uses the correct Function and possibly casts the /// argument and result to an unsigned type. - /// @param CI The CallInst to potentially auto-upgrade. /// @brief Get replacement instruction for overloaded intrinsic function call. - void UpgradeIntrinsicCall(CallInst* CI, Function* newF = 0); + void UpgradeIntrinsicCall( + CallInst* CI, ///< The CallInst to potentially auto-upgrade. + Function* newF = 0 ///< The new function for the call replacement. + ); /// Upgrade both the function and all the calls made to it, if that function /// needs to be upgraded. This is like a combination of the above two From reid at x10sys.com Fri May 19 14:08:10 2006 From: reid at x10sys.com (Reid Spencer) Date: Fri, 19 May 2006 14:08:10 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Analysis/DataStructure/DSNode.h Message-ID: <200605191908.OAA01314@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/Analysis/DataStructure: DSNode.h updated: 1.57 -> 1.58 --- Log message: Fix some doxygen usage in these headers. --- Diffs of the changes: (+1 -1) DSNode.h | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/include/llvm/Analysis/DataStructure/DSNode.h diff -u llvm/include/llvm/Analysis/DataStructure/DSNode.h:1.57 llvm/include/llvm/Analysis/DataStructure/DSNode.h:1.58 --- llvm/include/llvm/Analysis/DataStructure/DSNode.h:1.57 Wed Feb 22 10:23:42 2006 +++ llvm/include/llvm/Analysis/DataStructure/DSNode.h Fri May 19 14:07:54 2006 @@ -182,7 +182,7 @@ delete this; } - /// hasLink - Return true if this memory object has a link in slot #LinkNo + /// hasLink - Return true if this memory object has a link in slot LinkNo /// bool hasLink(unsigned Offset) const { assert((Offset & ((1 << DS::PointerShift)-1)) == 0 && From reid at x10sys.com Fri May 19 14:08:10 2006 From: reid at x10sys.com (Reid Spencer) Date: Fri, 19 May 2006 14:08:10 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/AsmPrinter.h DwarfWriter.h Message-ID: <200605191908.OAA01320@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: AsmPrinter.h updated: 1.39 -> 1.40 DwarfWriter.h updated: 1.35 -> 1.36 --- Log message: Fix some doxygen usage in these headers. --- Diffs of the changes: (+6 -3) AsmPrinter.h | 6 ++++-- DwarfWriter.h | 3 ++- 2 files changed, 6 insertions(+), 3 deletions(-) Index: llvm/include/llvm/CodeGen/AsmPrinter.h diff -u llvm/include/llvm/CodeGen/AsmPrinter.h:1.39 llvm/include/llvm/CodeGen/AsmPrinter.h:1.40 --- llvm/include/llvm/CodeGen/AsmPrinter.h:1.39 Tue May 9 00:33:28 2006 +++ llvm/include/llvm/CodeGen/AsmPrinter.h Fri May 19 14:07:54 2006 @@ -82,7 +82,8 @@ /// will enclose any GlobalVariable that points to a function. /// For example, this is used by the IA64 backend to materialize /// function descriptors, by decorating the ".data8" object with the - /// @fptr( ) link-relocation operator. + /// \literal @fptr( ) \endliteral + /// link-relocation operator. /// const char *FunctionAddrPrefix; // Defaults to "" const char *FunctionAddrSuffix; // Defaults to "" @@ -173,7 +174,8 @@ /// LCOMMDirective - This is the name of a directive (if supported) that can /// be used to efficiently declare a local (internal) block of zero /// initialized data in the .bss/.data section. The syntax expected is: - /// SYMBOLNAME LENGTHINBYTES, ALIGNMENT + /// \literal SYMBOLNAME LENGTHINBYTES, ALIGNMENT + /// \endliteral const char *LCOMMDirective; // Defaults to null. const char *COMMDirective; // Defaults to "\t.comm\t". Index: llvm/include/llvm/CodeGen/DwarfWriter.h diff -u llvm/include/llvm/CodeGen/DwarfWriter.h:1.35 llvm/include/llvm/CodeGen/DwarfWriter.h:1.36 --- llvm/include/llvm/CodeGen/DwarfWriter.h:1.35 Tue May 2 20:29:56 2006 +++ llvm/include/llvm/CodeGen/DwarfWriter.h Fri May 19 14:07:54 2006 @@ -279,7 +279,8 @@ void EmitInt64(uint64_t Value) const; /// EmitString - Emit a string with quotes and a null terminator. - /// Special characters are emitted properly. (Eg. '\t') + /// Special characters are emitted properly. + /// \literal (Eg. '\t') \endliteral void EmitString(const std::string &String) const; /// PrintLabelName - Print label name in form used by Dwarf writer. From reid at x10sys.com Fri May 19 14:09:58 2006 From: reid at x10sys.com (Reid Spencer) Date: Fri, 19 May 2006 14:09:58 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Utils/BasicBlockUtils.cpp Message-ID: <200605191909.OAA01332@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Utils: BasicBlockUtils.cpp updated: 1.14 -> 1.15 --- Log message: Fix a doxygen problem and break lines at 80 columns --- Diffs of the changes: (+3 -3) BasicBlockUtils.cpp | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) Index: llvm/lib/Transforms/Utils/BasicBlockUtils.cpp diff -u llvm/lib/Transforms/Utils/BasicBlockUtils.cpp:1.14 llvm/lib/Transforms/Utils/BasicBlockUtils.cpp:1.15 --- llvm/lib/Transforms/Utils/BasicBlockUtils.cpp:1.14 Thu Apr 21 18:45:33 2005 +++ llvm/lib/Transforms/Utils/BasicBlockUtils.cpp Fri May 19 14:09:46 2006 @@ -68,10 +68,10 @@ } /// RemoveSuccessor - Change the specified terminator instruction such that its -/// successor #SuccNum no longer exists. Because this reduces the outgoing +/// successor SuccNum no longer exists. Because this reduces the outgoing /// degree of the current basic block, the actual terminator instruction itself -/// may have to be changed. In the case where the last successor of the block is -/// deleted, a return instruction is inserted in its place which can cause a +/// may have to be changed. In the case where the last successor of the block +/// is deleted, a return instruction is inserted in its place which can cause a /// surprising change in program behavior if it is not expected. /// void llvm::RemoveSuccessor(TerminatorInst *TI, unsigned SuccNum) { From lattner at cs.uiuc.edu Fri May 19 14:34:21 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 19 May 2006 14:34:21 -0500 Subject: [llvm-commits] CVS: llvm/test/Regression/CFrontend/2006-05-19-SingleEltReturn.c Message-ID: <200605191934.OAA01463@zion.cs.uiuc.edu> Changes in directory llvm/test/Regression/CFrontend: 2006-05-19-SingleEltReturn.c added (r1.1) --- Log message: new testcase --- Diffs of the changes: (+23 -0) 2006-05-19-SingleEltReturn.c | 23 +++++++++++++++++++++++ 1 files changed, 23 insertions(+) Index: llvm/test/Regression/CFrontend/2006-05-19-SingleEltReturn.c diff -c /dev/null llvm/test/Regression/CFrontend/2006-05-19-SingleEltReturn.c:1.1 *** /dev/null Fri May 19 14:34:19 2006 --- llvm/test/Regression/CFrontend/2006-05-19-SingleEltReturn.c Fri May 19 14:34:09 2006 *************** *** 0 **** --- 1,23 ---- + // Test returning a single element aggregate value containing a double. + // RUN: %llvmgcc %s -S -o - + + struct X { + double D; + }; + + struct Y { + struct X x; + }; + + struct Y bar(); + + void foo(struct Y *P) { + *P = bar(); + } + + struct Y bar() { + struct Y a; + a.x.D = 0; + return a; + } + From lattner at cs.uiuc.edu Fri May 19 14:41:46 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 19 May 2006 14:41:46 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/README.txt Message-ID: <200605191941.OAA01595@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: README.txt updated: 1.107 -> 1.108 --- Log message: Particularly ugly code. --- Diffs of the changes: (+14 -0) README.txt | 14 ++++++++++++++ 1 files changed, 14 insertions(+) Index: llvm/lib/Target/X86/README.txt diff -u llvm/lib/Target/X86/README.txt:1.107 llvm/lib/Target/X86/README.txt:1.108 --- llvm/lib/Target/X86/README.txt:1.107 Thu May 18 12:38:16 2006 +++ llvm/lib/Target/X86/README.txt Fri May 19 14:41:33 2006 @@ -36,6 +36,20 @@ //===---------------------------------------------------------------------===// +On darwin/x86, we should codegen: + + ret double 0.000000e+00 + +as fld0/ret, not as: + + movl $0, 4(%esp) + movl $0, (%esp) + fldl (%esp) + ... + ret + +//===---------------------------------------------------------------------===// + This should use fiadd on chips where it is profitable: double foo(double P, int *I) { return P+*I; } From lattner at cs.uiuc.edu Fri May 19 15:45:20 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 19 May 2006 15:45:20 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/README.txt Message-ID: <200605192045.PAA01826@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target: README.txt updated: 1.30 -> 1.31 --- Log message: Move a target-independent note out of the X86 readme. --- Diffs of the changes: (+12 -0) README.txt | 12 ++++++++++++ 1 files changed, 12 insertions(+) Index: llvm/lib/Target/README.txt diff -u llvm/lib/Target/README.txt:1.30 llvm/lib/Target/README.txt:1.31 --- llvm/lib/Target/README.txt:1.30 Thu May 18 13:26:13 2006 +++ llvm/lib/Target/README.txt Fri May 19 15:45:08 2006 @@ -208,3 +208,15 @@ movl %eax, _foo //===---------------------------------------------------------------------===// + +Combine: a = sin(x), b = cos(x) into a,b = sincos(x). + +Expand these to calls of sin/cos and stores: + double sincos(double x, double *sin, double *cos); + float sincosf(float x, float *sin, float *cos); + long double sincosl(long double x, long double *sin, long double *cos); + +Doing so could allow SROA of the destination pointers. See also: +http://gcc.gnu.org/bugzilla/show_bug.cgi?id=17687 + +//===---------------------------------------------------------------------===// From lattner at cs.uiuc.edu Fri May 19 15:46:05 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 19 May 2006 15:46:05 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/README-FPStack.txt README.txt Message-ID: <200605192046.PAA01910@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: README-FPStack.txt added (r1.1) README.txt updated: 1.108 -> 1.109 --- Log message: Split FP-stack notes out of the main readme. Next up: splitting out SSE. --- Diffs of the changes: (+99 -100) README-FPStack.txt | 99 ++++++++++++++++++++++++++++++++++++++++++++++++++++ README.txt | 100 ----------------------------------------------------- 2 files changed, 99 insertions(+), 100 deletions(-) Index: llvm/lib/Target/X86/README-FPStack.txt diff -c /dev/null llvm/lib/Target/X86/README-FPStack.txt:1.1 *** /dev/null Fri May 19 15:46:02 2006 --- llvm/lib/Target/X86/README-FPStack.txt Fri May 19 15:45:52 2006 *************** *** 0 **** --- 1,99 ---- + //===---------------------------------------------------------------------===// + // Random ideas for the X86 backend: FP stack related stuff + //===---------------------------------------------------------------------===// + + //===---------------------------------------------------------------------===// + + Some targets (e.g. athlons) prefer freep to fstp ST(0): + http://gcc.gnu.org/ml/gcc-patches/2004-04/msg00659.html + + //===---------------------------------------------------------------------===// + + On darwin/x86, we should codegen: + + ret double 0.000000e+00 + + as fld0/ret, not as: + + movl $0, 4(%esp) + movl $0, (%esp) + fldl (%esp) + ... + ret + + //===---------------------------------------------------------------------===// + + This should use fiadd on chips where it is profitable: + double foo(double P, int *I) { return P+*I; } + + We have fiadd patterns now but the followings have the same cost and + complexity. We need a way to specify the later is more profitable. + + def FpADD32m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW, + [(set RFP:$dst, (fadd RFP:$src1, + (extloadf64f32 addr:$src2)))]>; + // ST(0) = ST(0) + [mem32] + + def FpIADD32m : FpI<(ops RFP:$dst, RFP:$src1, i32mem:$src2), OneArgFPRW, + [(set RFP:$dst, (fadd RFP:$src1, + (X86fild addr:$src2, i32)))]>; + // ST(0) = ST(0) + [mem32int] + + //===---------------------------------------------------------------------===// + + The FP stackifier needs to be global. Also, it should handle simple permutates + to reduce number of shuffle instructions, e.g. turning: + + fld P -> fld Q + fld Q fld P + fxch + + or: + + fxch -> fucomi + fucomi jl X + jg X + + Ideas: + http://gcc.gnu.org/ml/gcc-patches/2004-11/msg02410.html + + + //===---------------------------------------------------------------------===// + + Add a target specific hook to DAG combiner to handle SINT_TO_FP and + FP_TO_SINT when the source operand is already in memory. + + //===---------------------------------------------------------------------===// + + Open code rint,floor,ceil,trunc: + http://gcc.gnu.org/ml/gcc-patches/2004-08/msg02006.html + http://gcc.gnu.org/ml/gcc-patches/2004-08/msg02011.html + + Opencode the sincos[f] libcall. + + //===---------------------------------------------------------------------===// + + None of the FPStack instructions are handled in + X86RegisterInfo::foldMemoryOperand, which prevents the spiller from + folding spill code into the instructions. + + //===---------------------------------------------------------------------===// + + Currently the x86 codegen isn't very good at mixing SSE and FPStack + code: + + unsigned int foo(double x) { return x; } + + foo: + subl $20, %esp + movsd 24(%esp), %xmm0 + movsd %xmm0, 8(%esp) + fldl 8(%esp) + fisttpll (%esp) + movl (%esp), %eax + addl $20, %esp + ret + + This will be solved when we go to a dynamic programming based isel. + + //===---------------------------------------------------------------------===// Index: llvm/lib/Target/X86/README.txt diff -u llvm/lib/Target/X86/README.txt:1.108 llvm/lib/Target/X86/README.txt:1.109 --- llvm/lib/Target/X86/README.txt:1.108 Fri May 19 14:41:33 2006 +++ llvm/lib/Target/X86/README.txt Fri May 19 15:45:52 2006 @@ -31,62 +31,6 @@ //===---------------------------------------------------------------------===// -Some targets (e.g. athlons) prefer freep to fstp ST(0): -http://gcc.gnu.org/ml/gcc-patches/2004-04/msg00659.html - -//===---------------------------------------------------------------------===// - -On darwin/x86, we should codegen: - - ret double 0.000000e+00 - -as fld0/ret, not as: - - movl $0, 4(%esp) - movl $0, (%esp) - fldl (%esp) - ... - ret - -//===---------------------------------------------------------------------===// - -This should use fiadd on chips where it is profitable: -double foo(double P, int *I) { return P+*I; } - -We have fiadd patterns now but the followings have the same cost and -complexity. We need a way to specify the later is more profitable. - -def FpADD32m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW, - [(set RFP:$dst, (fadd RFP:$src1, - (extloadf64f32 addr:$src2)))]>; - // ST(0) = ST(0) + [mem32] - -def FpIADD32m : FpI<(ops RFP:$dst, RFP:$src1, i32mem:$src2), OneArgFPRW, - [(set RFP:$dst, (fadd RFP:$src1, - (X86fild addr:$src2, i32)))]>; - // ST(0) = ST(0) + [mem32int] - -//===---------------------------------------------------------------------===// - -The FP stackifier needs to be global. Also, it should handle simple permutates -to reduce number of shuffle instructions, e.g. turning: - -fld P -> fld Q -fld Q fld P -fxch - -or: - -fxch -> fucomi -fucomi jl X -jg X - -Ideas: -http://gcc.gnu.org/ml/gcc-patches/2004-11/msg02410.html - - -//===---------------------------------------------------------------------===// - Improvements to the multiply -> shift/add algorithm: http://gcc.gnu.org/ml/gcc-patches/2004-08/msg01590.html @@ -136,11 +80,6 @@ //===---------------------------------------------------------------------===// -Add a target specific hook to DAG combiner to handle SINT_TO_FP and -FP_TO_SINT when the source operand is already in memory. - -//===---------------------------------------------------------------------===// - Model X86 EFLAGS as a real register to avoid redudant cmp / test. e.g. cmpl $1, %eax @@ -181,24 +120,6 @@ //===---------------------------------------------------------------------===// -Open code rint,floor,ceil,trunc: -http://gcc.gnu.org/ml/gcc-patches/2004-08/msg02006.html -http://gcc.gnu.org/ml/gcc-patches/2004-08/msg02011.html - -//===---------------------------------------------------------------------===// - -Combine: a = sin(x), b = cos(x) into a,b = sincos(x). - -Expand these to calls of sin/cos and stores: - double sincos(double x, double *sin, double *cos); - float sincosf(float x, float *sin, float *cos); - long double sincosl(long double x, long double *sin, long double *cos); - -Doing so could allow SROA of the destination pointers. See also: -http://gcc.gnu.org/bugzilla/show_bug.cgi?id=17687 - -//===---------------------------------------------------------------------===// - The instruction selector sometimes misses folding a load into a compare. The pattern is written as (cmp reg, (load p)). Because the compare isn't commutative, it is not matched with the load on both sides. The dag combiner @@ -219,11 +140,6 @@ //===---------------------------------------------------------------------===// -LSR should be turned on for the X86 backend and tuned to take advantage of its -addressing modes. - -//===---------------------------------------------------------------------===// - When compiled with unsafemath enabled, "main" should enable SSE DAZ mode and other fast SSE modes. @@ -293,11 +209,6 @@ //===---------------------------------------------------------------------===// -We need to lower switch statements to tablejumps when appropriate instead of -always into binary branch trees. - -//===---------------------------------------------------------------------===// - SSE doesn't have [mem] op= reg instructions. If we have an SSE instruction like this: @@ -351,12 +262,6 @@ //===---------------------------------------------------------------------===// -None of the FPStack instructions are handled in -X86RegisterInfo::foldMemoryOperand, which prevents the spiller from -folding spill code into the instructions. - -//===---------------------------------------------------------------------===// - In many cases, LLVM generates code like this: _test: @@ -827,11 +732,6 @@ //===---------------------------------------------------------------------===// -A Mac OS X IA-32 specific ABI bug wrt returning value > 8 bytes: -http://llvm.org/bugs/show_bug.cgi?id=729 - -//===---------------------------------------------------------------------===// - X86RegisterInfo::copyRegToReg() returns X86::MOVAPSrr for VR128. Is it possible to choose between movaps, movapd, and movdqa based on types of source and destination? From lattner at cs.uiuc.edu Fri May 19 15:51:55 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 19 May 2006 15:51:55 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/README-SSE.txt README.txt Message-ID: <200605192051.PAA01981@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: README-SSE.txt added (r1.1) README.txt updated: 1.109 -> 1.110 --- Log message: Split the SSE readme items out into their own README. --- Diffs of the changes: (+662 -582) README-SSE.txt | 662 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ README.txt | 582 -------------------------------------------------- 2 files changed, 662 insertions(+), 582 deletions(-) Index: llvm/lib/Target/X86/README-SSE.txt diff -c /dev/null llvm/lib/Target/X86/README-SSE.txt:1.1 *** /dev/null Fri May 19 15:51:53 2006 --- llvm/lib/Target/X86/README-SSE.txt Fri May 19 15:51:43 2006 *************** *** 0 **** --- 1,662 ---- + //===---------------------------------------------------------------------===// + // Random ideas for the X86 backend: SSE-specific stuff. + //===---------------------------------------------------------------------===// + + //===---------------------------------------------------------------------===// + + When compiled with unsafemath enabled, "main" should enable SSE DAZ mode and + other fast SSE modes. + + //===---------------------------------------------------------------------===// + + Think about doing i64 math in SSE regs. + + //===---------------------------------------------------------------------===// + + This testcase should have no SSE instructions in it, and only one load from + a constant pool: + + double %test3(bool %B) { + %C = select bool %B, double 123.412, double 523.01123123 + ret double %C + } + + Currently, the select is being lowered, which prevents the dag combiner from + turning 'select (load CPI1), (load CPI2)' -> 'load (select CPI1, CPI2)' + + The pattern isel got this one right. + + //===---------------------------------------------------------------------===// + + SSE doesn't have [mem] op= reg instructions. If we have an SSE instruction + like this: + + X += y + + and the register allocator decides to spill X, it is cheaper to emit this as: + + Y += [xslot] + store Y -> [xslot] + + than as: + + tmp = [xslot] + tmp += y + store tmp -> [xslot] + + ..and this uses one fewer register (so this should be done at load folding + time, not at spiller time). *Note* however that this can only be done + if Y is dead. Here's a testcase: + + %.str_3 = external global [15 x sbyte] ; <[15 x sbyte]*> [#uses=0] + implementation ; Functions: + declare void %printf(int, ...) + void %main() { + build_tree.exit: + br label %no_exit.i7 + no_exit.i7: ; preds = %no_exit.i7, %build_tree.exit + %tmp.0.1.0.i9 = phi double [ 0.000000e+00, %build_tree.exit ], [ %tmp.34.i18, %no_exit.i7 ] ; [#uses=1] + %tmp.0.0.0.i10 = phi double [ 0.000000e+00, %build_tree.exit ], [ %tmp.28.i16, %no_exit.i7 ] ; [#uses=1] + %tmp.28.i16 = add double %tmp.0.0.0.i10, 0.000000e+00 + %tmp.34.i18 = add double %tmp.0.1.0.i9, 0.000000e+00 + br bool false, label %Compute_Tree.exit23, label %no_exit.i7 + Compute_Tree.exit23: ; preds = %no_exit.i7 + tail call void (int, ...)* %printf( int 0 ) + store double %tmp.34.i18, double* null + ret void + } + + We currently emit: + + .BBmain_1: + xorpd %XMM1, %XMM1 + addsd %XMM0, %XMM1 + *** movsd %XMM2, QWORD PTR [%ESP + 8] + *** addsd %XMM2, %XMM1 + *** movsd QWORD PTR [%ESP + 8], %XMM2 + jmp .BBmain_1 # no_exit.i7 + + This is a bugpoint reduced testcase, which is why the testcase doesn't make + much sense (e.g. its an infinite loop). :) + + //===---------------------------------------------------------------------===// + + SSE should implement 'select_cc' using 'emulated conditional moves' that use + pcmp/pand/pandn/por to do a selection instead of a conditional branch: + + double %X(double %Y, double %Z, double %A, double %B) { + %C = setlt double %A, %B + %z = add double %Z, 0.0 ;; select operand is not a load + %D = select bool %C, double %Y, double %z + ret double %D + } + + We currently emit: + + _X: + subl $12, %esp + xorpd %xmm0, %xmm0 + addsd 24(%esp), %xmm0 + movsd 32(%esp), %xmm1 + movsd 16(%esp), %xmm2 + ucomisd 40(%esp), %xmm1 + jb LBB_X_2 + LBB_X_1: + movsd %xmm0, %xmm2 + LBB_X_2: + movsd %xmm2, (%esp) + fldl (%esp) + addl $12, %esp + ret + + //===---------------------------------------------------------------------===// + + It's not clear whether we should use pxor or xorps / xorpd to clear XMM + registers. The choice may depend on subtarget information. We should do some + more experiments on different x86 machines. + + //===---------------------------------------------------------------------===// + + Currently the x86 codegen isn't very good at mixing SSE and FPStack + code: + + unsigned int foo(double x) { return x; } + + foo: + subl $20, %esp + movsd 24(%esp), %xmm0 + movsd %xmm0, 8(%esp) + fldl 8(%esp) + fisttpll (%esp) + movl (%esp), %eax + addl $20, %esp + ret + + This will be solved when we go to a dynamic programming based isel. + + //===---------------------------------------------------------------------===// + + Should generate min/max for stuff like: + + void minf(float a, float b, float *X) { + *X = a <= b ? a : b; + } + + Make use of floating point min / max instructions. Perhaps introduce ISD::FMIN + and ISD::FMAX node types? + + //===---------------------------------------------------------------------===// + + The first BB of this code: + + declare bool %foo() + int %bar() { + %V = call bool %foo() + br bool %V, label %T, label %F + T: + ret int 1 + F: + call bool %foo() + ret int 12 + } + + compiles to: + + _bar: + subl $12, %esp + call L_foo$stub + xorb $1, %al + testb %al, %al + jne LBB_bar_2 # F + + It would be better to emit "cmp %al, 1" than a xor and test. + + //===---------------------------------------------------------------------===// + + Lower memcpy / memset to a series of SSE 128 bit move instructions when it's + feasible. + + //===---------------------------------------------------------------------===// + + Teach the coalescer to commute 2-addr instructions, allowing us to eliminate + the reg-reg copy in this example: + + float foo(int *x, float *y, unsigned c) { + float res = 0.0; + unsigned i; + for (i = 0; i < c; i++) { + float xx = (float)x[i]; + xx = xx * y[i]; + xx += res; + res = xx; + } + return res; + } + + LBB_foo_3: # no_exit + cvtsi2ss %XMM0, DWORD PTR [%EDX + 4*%ESI] + mulss %XMM0, DWORD PTR [%EAX + 4*%ESI] + addss %XMM0, %XMM1 + inc %ESI + cmp %ESI, %ECX + **** movaps %XMM1, %XMM0 + jb LBB_foo_3 # no_exit + + //===---------------------------------------------------------------------===// + + Codegen: + if (copysign(1.0, x) == copysign(1.0, y)) + into: + if (x^y & mask) + when using SSE. + + //===---------------------------------------------------------------------===// + + Use movhps to update upper 64-bits of a v4sf value. Also movlps on lower half + of a v4sf value. + + //===---------------------------------------------------------------------===// + + Better codegen for vector_shuffles like this { x, 0, 0, 0 } or { x, 0, x, 0}. + Perhaps use pxor / xorp* to clear a XMM register first? + + //===---------------------------------------------------------------------===// + + Better codegen for: + + void f(float a, float b, vector float * out) { *out = (vector float){ a, 0.0, 0.0, b}; } + void f(float a, float b, vector float * out) { *out = (vector float){ a, b, 0.0, 0}; } + + For the later we generate: + + _f: + pxor %xmm0, %xmm0 + movss 8(%esp), %xmm1 + movaps %xmm0, %xmm2 + unpcklps %xmm1, %xmm2 + movss 4(%esp), %xmm1 + unpcklps %xmm0, %xmm1 + unpcklps %xmm2, %xmm1 + movl 12(%esp), %eax + movaps %xmm1, (%eax) + ret + + This seems like it should use shufps, one for each of a & b. + + //===---------------------------------------------------------------------===// + + How to decide when to use the "floating point version" of logical ops? Here are + some code fragments: + + movaps LCPI5_5, %xmm2 + divps %xmm1, %xmm2 + mulps %xmm2, %xmm3 + mulps 8656(%ecx), %xmm3 + addps 8672(%ecx), %xmm3 + andps LCPI5_6, %xmm2 + andps LCPI5_1, %xmm3 + por %xmm2, %xmm3 + movdqa %xmm3, (%edi) + + movaps LCPI5_5, %xmm1 + divps %xmm0, %xmm1 + mulps %xmm1, %xmm3 + mulps 8656(%ecx), %xmm3 + addps 8672(%ecx), %xmm3 + andps LCPI5_6, %xmm1 + andps LCPI5_1, %xmm3 + orps %xmm1, %xmm3 + movaps %xmm3, 112(%esp) + movaps %xmm3, (%ebx) + + Due to some minor source change, the later case ended up using orps and movaps + instead of por and movdqa. Does it matter? + + //===---------------------------------------------------------------------===// + + Use movddup to splat a v2f64 directly from a memory source. e.g. + + #include + + void test(__m128d *r, double A) { + *r = _mm_set1_pd(A); + } + + llc: + + _test: + movsd 8(%esp), %xmm0 + unpcklpd %xmm0, %xmm0 + movl 4(%esp), %eax + movapd %xmm0, (%eax) + ret + + icc: + + _test: + movl 4(%esp), %eax + movddup 8(%esp), %xmm0 + movapd %xmm0, (%eax) + ret + + //===---------------------------------------------------------------------===// + + X86RegisterInfo::copyRegToReg() returns X86::MOVAPSrr for VR128. Is it possible + to choose between movaps, movapd, and movdqa based on types of source and + destination? + + How about andps, andpd, and pand? Do we really care about the type of the packed + elements? If not, why not always use the "ps" variants which are likely to be + shorter. + + //===---------------------------------------------------------------------===// + + We are emitting bad code for this: + + float %test(float* %V, int %I, int %D, float %V) { + entry: + %tmp = seteq int %D, 0 + br bool %tmp, label %cond_true, label %cond_false23 + + cond_true: + %tmp3 = getelementptr float* %V, int %I + %tmp = load float* %tmp3 + %tmp5 = setgt float %tmp, %V + %tmp6 = tail call bool %llvm.isunordered.f32( float %tmp, float %V ) + %tmp7 = or bool %tmp5, %tmp6 + br bool %tmp7, label %UnifiedReturnBlock, label %cond_next + + cond_next: + %tmp10 = add int %I, 1 + %tmp12 = getelementptr float* %V, int %tmp10 + %tmp13 = load float* %tmp12 + %tmp15 = setle float %tmp13, %V + %tmp16 = tail call bool %llvm.isunordered.f32( float %tmp13, float %V ) + %tmp17 = or bool %tmp15, %tmp16 + %retval = select bool %tmp17, float 0.000000e+00, float 1.000000e+00 + ret float %retval + + cond_false23: + %tmp28 = tail call float %foo( float* %V, int %I, int %D, float %V ) + ret float %tmp28 + + UnifiedReturnBlock: ; preds = %cond_true + ret float 0.000000e+00 + } + + declare bool %llvm.isunordered.f32(float, float) + + declare float %foo(float*, int, int, float) + + + It exposes a known load folding problem: + + movss (%edx,%ecx,4), %xmm1 + ucomiss %xmm1, %xmm0 + + As well as this: + + LBB_test_2: # cond_next + movss LCPI1_0, %xmm2 + pxor %xmm3, %xmm3 + ucomiss %xmm0, %xmm1 + jbe LBB_test_6 # cond_next + LBB_test_5: # cond_next + movaps %xmm2, %xmm3 + LBB_test_6: # cond_next + movss %xmm3, 40(%esp) + flds 40(%esp) + addl $44, %esp + ret + + Clearly it's unnecessary to clear %xmm3. It's also not clear why we are emitting + three moves (movss, movaps, movss). + + //===---------------------------------------------------------------------===// + + External test Nurbs exposed some problems. Look for + __ZN15Nurbs_SSE_Cubic17TessellateSurfaceE, bb cond_next140. This is what icc + emits: + + movaps (%edx), %xmm2 #59.21 + movaps (%edx), %xmm5 #60.21 + movaps (%edx), %xmm4 #61.21 + movaps (%edx), %xmm3 #62.21 + movl 40(%ecx), %ebp #69.49 + shufps $0, %xmm2, %xmm5 #60.21 + movl 100(%esp), %ebx #69.20 + movl (%ebx), %edi #69.20 + imull %ebp, %edi #69.49 + addl (%eax), %edi #70.33 + shufps $85, %xmm2, %xmm4 #61.21 + shufps $170, %xmm2, %xmm3 #62.21 + shufps $255, %xmm2, %xmm2 #63.21 + lea (%ebp,%ebp,2), %ebx #69.49 + negl %ebx #69.49 + lea -3(%edi,%ebx), %ebx #70.33 + shll $4, %ebx #68.37 + addl 32(%ecx), %ebx #68.37 + testb $15, %bl #91.13 + jne L_B1.24 # Prob 5% #91.13 + + This is the llvm code after instruction scheduling: + + cond_next140 (0xa910740, LLVM BB @0xa90beb0): + %reg1078 = MOV32ri -3 + %reg1079 = ADD32rm %reg1078, %reg1068, 1, %NOREG, 0 + %reg1037 = MOV32rm %reg1024, 1, %NOREG, 40 + %reg1080 = IMUL32rr %reg1079, %reg1037 + %reg1081 = MOV32rm %reg1058, 1, %NOREG, 0 + %reg1038 = LEA32r %reg1081, 1, %reg1080, -3 + %reg1036 = MOV32rm %reg1024, 1, %NOREG, 32 + %reg1082 = SHL32ri %reg1038, 4 + %reg1039 = ADD32rr %reg1036, %reg1082 + %reg1083 = MOVAPSrm %reg1059, 1, %NOREG, 0 + %reg1034 = SHUFPSrr %reg1083, %reg1083, 170 + %reg1032 = SHUFPSrr %reg1083, %reg1083, 0 + %reg1035 = SHUFPSrr %reg1083, %reg1083, 255 + %reg1033 = SHUFPSrr %reg1083, %reg1083, 85 + %reg1040 = MOV32rr %reg1039 + %reg1084 = AND32ri8 %reg1039, 15 + CMP32ri8 %reg1084, 0 + JE mbb + + Still ok. After register allocation: + + cond_next140 (0xa910740, LLVM BB @0xa90beb0): + %EAX = MOV32ri -3 + %EDX = MOV32rm , 1, %NOREG, 0 + ADD32rm %EAX, %EDX, 1, %NOREG, 0 + %EDX = MOV32rm , 1, %NOREG, 0 + %EDX = MOV32rm %EDX, 1, %NOREG, 40 + IMUL32rr %EAX, %EDX + %ESI = MOV32rm , 1, %NOREG, 0 + %ESI = MOV32rm %ESI, 1, %NOREG, 0 + MOV32mr , 1, %NOREG, 0, %ESI + %EAX = LEA32r %ESI, 1, %EAX, -3 + %ESI = MOV32rm , 1, %NOREG, 0 + %ESI = MOV32rm %ESI, 1, %NOREG, 32 + %EDI = MOV32rr %EAX + SHL32ri %EDI, 4 + ADD32rr %EDI, %ESI + %XMM0 = MOVAPSrm %ECX, 1, %NOREG, 0 + %XMM1 = MOVAPSrr %XMM0 + SHUFPSrr %XMM1, %XMM1, 170 + %XMM2 = MOVAPSrr %XMM0 + SHUFPSrr %XMM2, %XMM2, 0 + %XMM3 = MOVAPSrr %XMM0 + SHUFPSrr %XMM3, %XMM3, 255 + SHUFPSrr %XMM0, %XMM0, 85 + %EBX = MOV32rr %EDI + AND32ri8 %EBX, 15 + CMP32ri8 %EBX, 0 + JE mbb + + This looks really bad. The problem is shufps is a destructive opcode. Since it + appears as operand two in more than one shufps ops. It resulted in a number of + copies. Note icc also suffers from the same problem. Either the instruction + selector should select pshufd or The register allocator can made the two-address + to three-address transformation. + + It also exposes some other problems. See MOV32ri -3 and the spills. + + //===---------------------------------------------------------------------===// + + http://gcc.gnu.org/bugzilla/show_bug.cgi?id=25500 + + LLVM is producing bad code. + + LBB_main_4: # cond_true44 + addps %xmm1, %xmm2 + subps %xmm3, %xmm2 + movaps (%ecx), %xmm4 + movaps %xmm2, %xmm1 + addps %xmm4, %xmm1 + addl $16, %ecx + incl %edx + cmpl $262144, %edx + movaps %xmm3, %xmm2 + movaps %xmm4, %xmm3 + jne LBB_main_4 # cond_true44 + + There are two problems. 1) No need to two loop induction variables. We can + compare against 262144 * 16. 2) Known register coalescer issue. We should + be able eliminate one of the movaps: + + addps %xmm2, %xmm1 <=== Commute! + subps %xmm3, %xmm1 + movaps (%ecx), %xmm4 + movaps %xmm1, %xmm1 <=== Eliminate! + addps %xmm4, %xmm1 + addl $16, %ecx + incl %edx + cmpl $262144, %edx + movaps %xmm3, %xmm2 + movaps %xmm4, %xmm3 + jne LBB_main_4 # cond_true44 + + //===---------------------------------------------------------------------===// + + Consider: + + __m128 test(float a) { + return _mm_set_ps(0.0, 0.0, 0.0, a*a); + } + + This compiles into: + + movss 4(%esp), %xmm1 + mulss %xmm1, %xmm1 + xorps %xmm0, %xmm0 + movss %xmm1, %xmm0 + ret + + Because mulss doesn't modify the top 3 elements, the top elements of + xmm1 are already zero'd. We could compile this to: + + movss 4(%esp), %xmm0 + mulss %xmm0, %xmm0 + ret + + //===---------------------------------------------------------------------===// + + Here's a sick and twisted idea. Consider code like this: + + __m128 test(__m128 a) { + float b = *(float*)&A; + ... + return _mm_set_ps(0.0, 0.0, 0.0, b); + } + + This might compile to this code: + + movaps c(%esp), %xmm1 + xorps %xmm0, %xmm0 + movss %xmm1, %xmm0 + ret + + Now consider if the ... code caused xmm1 to get spilled. This might produce + this code: + + movaps c(%esp), %xmm1 + movaps %xmm1, c2(%esp) + ... + + xorps %xmm0, %xmm0 + movaps c2(%esp), %xmm1 + movss %xmm1, %xmm0 + ret + + However, since the reload is only used by these instructions, we could + "fold" it into the uses, producing something like this: + + movaps c(%esp), %xmm1 + movaps %xmm1, c2(%esp) + ... + + movss c2(%esp), %xmm0 + ret + + ... saving two instructions. + + The basic idea is that a reload from a spill slot, can, if only one 4-byte + chunk is used, bring in 3 zeros the the one element instead of 4 elements. + This can be used to simplify a variety of shuffle operations, where the + elements are fixed zeros. + + //===---------------------------------------------------------------------===// + + For this: + + #include + void test(__m128d *r, __m128d *A, double B) { + *r = _mm_loadl_pd(*A, &B); + } + + We generates: + + subl $12, %esp + movsd 24(%esp), %xmm0 + movsd %xmm0, (%esp) + movl 20(%esp), %eax + movapd (%eax), %xmm0 + movlpd (%esp), %xmm0 + movl 16(%esp), %eax + movapd %xmm0, (%eax) + addl $12, %esp + ret + + icc generates: + + movl 4(%esp), %edx #3.6 + movl 8(%esp), %eax #3.6 + movapd (%eax), %xmm0 #4.22 + movlpd 12(%esp), %xmm0 #4.8 + movapd %xmm0, (%edx) #4.3 + ret #5.1 + + So icc is smart enough to know that B is in memory so it doesn't load it and + store it back to stack. + + //===---------------------------------------------------------------------===// + + __m128d test1( __m128d A, __m128d B) { + return _mm_shuffle_pd(A, B, 0x3); + } + + compiles to + + shufpd $3, %xmm1, %xmm0 + + Perhaps it's better to use unpckhpd instead? + + unpckhpd %xmm1, %xmm0 + + Don't know if unpckhpd is faster. But it is shorter. + + //===---------------------------------------------------------------------===// + + This code generates ugly code, probably due to costs being off or something: + + void %test(float* %P, <4 x float>* %P2 ) { + %xFloat0.688 = load float* %P + %loadVector37.712 = load <4 x float>* %P2 + %inFloat3.713 = insertelement <4 x float> %loadVector37.712, float 0.000000e+00, uint 3 + store <4 x float> %inFloat3.713, <4 x float>* %P2 + ret void + } + + Generates: + + _test: + pxor %xmm0, %xmm0 + movd %xmm0, %eax ;; EAX = 0! + movl 8(%esp), %ecx + movaps (%ecx), %xmm0 + pinsrw $6, %eax, %xmm0 + shrl $16, %eax ;; EAX = 0 again! + pinsrw $7, %eax, %xmm0 + movaps %xmm0, (%ecx) + ret + + It would be better to generate: + + _test: + movl 8(%esp), %ecx + movaps (%ecx), %xmm0 + xor %eax, %eax + pinsrw $6, %eax, %xmm0 + pinsrw $7, %eax, %xmm0 + movaps %xmm0, (%ecx) + ret + + or use pxor (to make a zero vector) and shuffle (to insert it). + + //===---------------------------------------------------------------------===// + + Some useful information in the Apple Altivec / SSE Migration Guide: + + http://developer.apple.com/documentation/Performance/Conceptual/ + Accelerate_sse_migration/index.html + + e.g. SSE select using and, andnot, or. Various SSE compare translations. Index: llvm/lib/Target/X86/README.txt diff -u llvm/lib/Target/X86/README.txt:1.109 llvm/lib/Target/X86/README.txt:1.110 --- llvm/lib/Target/X86/README.txt:1.109 Fri May 19 15:45:52 2006 +++ llvm/lib/Target/X86/README.txt Fri May 19 15:51:43 2006 @@ -140,15 +140,6 @@ //===---------------------------------------------------------------------===// -When compiled with unsafemath enabled, "main" should enable SSE DAZ mode and -other fast SSE modes. - -//===---------------------------------------------------------------------===// - -Think about doing i64 math in SSE regs. - -//===---------------------------------------------------------------------===// - The DAG Isel doesn't fold the loads into the adds in this testcase. The pattern selector does. This is because the chain value of the load gets selected first, and the loads aren't checking to see if they are only used by @@ -194,74 +185,6 @@ //===---------------------------------------------------------------------===// -This testcase should have no SSE instructions in it, and only one load from -a constant pool: - -double %test3(bool %B) { - %C = select bool %B, double 123.412, double 523.01123123 - ret double %C -} - -Currently, the select is being lowered, which prevents the dag combiner from -turning 'select (load CPI1), (load CPI2)' -> 'load (select CPI1, CPI2)' - -The pattern isel got this one right. - -//===---------------------------------------------------------------------===// - -SSE doesn't have [mem] op= reg instructions. If we have an SSE instruction -like this: - - X += y - -and the register allocator decides to spill X, it is cheaper to emit this as: - -Y += [xslot] -store Y -> [xslot] - -than as: - -tmp = [xslot] -tmp += y -store tmp -> [xslot] - -..and this uses one fewer register (so this should be done at load folding -time, not at spiller time). *Note* however that this can only be done -if Y is dead. Here's a testcase: - -%.str_3 = external global [15 x sbyte] ; <[15 x sbyte]*> [#uses=0] -implementation ; Functions: -declare void %printf(int, ...) -void %main() { -build_tree.exit: - br label %no_exit.i7 -no_exit.i7: ; preds = %no_exit.i7, %build_tree.exit - %tmp.0.1.0.i9 = phi double [ 0.000000e+00, %build_tree.exit ], [ %tmp.34.i18, %no_exit.i7 ] ; [#uses=1] - %tmp.0.0.0.i10 = phi double [ 0.000000e+00, %build_tree.exit ], [ %tmp.28.i16, %no_exit.i7 ] ; [#uses=1] - %tmp.28.i16 = add double %tmp.0.0.0.i10, 0.000000e+00 - %tmp.34.i18 = add double %tmp.0.1.0.i9, 0.000000e+00 - br bool false, label %Compute_Tree.exit23, label %no_exit.i7 -Compute_Tree.exit23: ; preds = %no_exit.i7 - tail call void (int, ...)* %printf( int 0 ) - store double %tmp.34.i18, double* null - ret void -} - -We currently emit: - -.BBmain_1: - xorpd %XMM1, %XMM1 - addsd %XMM0, %XMM1 -*** movsd %XMM2, QWORD PTR [%ESP + 8] -*** addsd %XMM2, %XMM1 -*** movsd QWORD PTR [%ESP + 8], %XMM2 - jmp .BBmain_1 # no_exit.i7 - -This is a bugpoint reduced testcase, which is why the testcase doesn't make -much sense (e.g. its an infinite loop). :) - -//===---------------------------------------------------------------------===// - In many cases, LLVM generates code like this: _test: @@ -316,36 +239,6 @@ //===---------------------------------------------------------------------===// -SSE should implement 'select_cc' using 'emulated conditional moves' that use -pcmp/pand/pandn/por to do a selection instead of a conditional branch: - -double %X(double %Y, double %Z, double %A, double %B) { - %C = setlt double %A, %B - %z = add double %Z, 0.0 ;; select operand is not a load - %D = select bool %C, double %Y, double %z - ret double %D -} - -We currently emit: - -_X: - subl $12, %esp - xorpd %xmm0, %xmm0 - addsd 24(%esp), %xmm0 - movsd 32(%esp), %xmm1 - movsd 16(%esp), %xmm2 - ucomisd 40(%esp), %xmm1 - jb LBB_X_2 -LBB_X_1: - movsd %xmm0, %xmm2 -LBB_X_2: - movsd %xmm2, (%esp) - fldl (%esp) - addl $12, %esp - ret - -//===---------------------------------------------------------------------===// - We should generate bts/btr/etc instructions on targets where they are cheap or when codesize is important. e.g., for: @@ -375,12 +268,6 @@ //===---------------------------------------------------------------------===// -It's not clear whether we should use pxor or xorps / xorpd to clear XMM -registers. The choice may depend on subtarget information. We should do some -more experiments on different x86 machines. - -//===---------------------------------------------------------------------===// - Evaluate what the best way to codegen sdiv X, (2^C) is. For X/8, we currently get this: @@ -412,25 +299,6 @@ //===---------------------------------------------------------------------===// -Currently the x86 codegen isn't very good at mixing SSE and FPStack -code: - -unsigned int foo(double x) { return x; } - -foo: - subl $20, %esp - movsd 24(%esp), %xmm0 - movsd %xmm0, 8(%esp) - fldl 8(%esp) - fisttpll (%esp) - movl (%esp), %eax - addl $20, %esp - ret - -This will be solved when we go to a dynamic programming based isel. - -//===---------------------------------------------------------------------===// - Should generate min/max for stuff like: void minf(float a, float b, float *X) { @@ -495,45 +363,6 @@ //===---------------------------------------------------------------------===// -Lower memcpy / memset to a series of SSE 128 bit move instructions when it's -feasible. - -//===---------------------------------------------------------------------===// - -Teach the coalescer to commute 2-addr instructions, allowing us to eliminate -the reg-reg copy in this example: - -float foo(int *x, float *y, unsigned c) { - float res = 0.0; - unsigned i; - for (i = 0; i < c; i++) { - float xx = (float)x[i]; - xx = xx * y[i]; - xx += res; - res = xx; - } - return res; -} - -LBB_foo_3: # no_exit - cvtsi2ss %XMM0, DWORD PTR [%EDX + 4*%ESI] - mulss %XMM0, DWORD PTR [%EAX + 4*%ESI] - addss %XMM0, %XMM1 - inc %ESI - cmp %ESI, %ECX -**** movaps %XMM1, %XMM0 - jb LBB_foo_3 # no_exit - -//===---------------------------------------------------------------------===// - -Codegen: - if (copysign(1.0, x) == copysign(1.0, y)) -into: - if (x^y & mask) -when using SSE. - -//===---------------------------------------------------------------------===// - Optimize this into something reasonable: x * copysign(1.0, y) * copysign(1.0, z) @@ -611,39 +440,6 @@ //===---------------------------------------------------------------------===// -Use movhps to update upper 64-bits of a v4sf value. Also movlps on lower half -of a v4sf value. - -//===---------------------------------------------------------------------===// - -Better codegen for vector_shuffles like this { x, 0, 0, 0 } or { x, 0, x, 0}. -Perhaps use pxor / xorp* to clear a XMM register first? - -//===---------------------------------------------------------------------===// - -Better codegen for: - -void f(float a, float b, vector float * out) { *out = (vector float){ a, 0.0, 0.0, b}; } -void f(float a, float b, vector float * out) { *out = (vector float){ a, b, 0.0, 0}; } - -For the later we generate: - -_f: - pxor %xmm0, %xmm0 - movss 8(%esp), %xmm1 - movaps %xmm0, %xmm2 - unpcklps %xmm1, %xmm2 - movss 4(%esp), %xmm1 - unpcklps %xmm0, %xmm1 - unpcklps %xmm2, %xmm1 - movl 12(%esp), %eax - movaps %xmm1, (%eax) - ret - -This seems like it should use shufps, one for each of a & b. - -//===---------------------------------------------------------------------===// - Adding to the list of cmp / test poor codegen issues: int test(__m128 *A, __m128 *B) { @@ -676,327 +472,6 @@ //===---------------------------------------------------------------------===// -How to decide when to use the "floating point version" of logical ops? Here are -some code fragments: - - movaps LCPI5_5, %xmm2 - divps %xmm1, %xmm2 - mulps %xmm2, %xmm3 - mulps 8656(%ecx), %xmm3 - addps 8672(%ecx), %xmm3 - andps LCPI5_6, %xmm2 - andps LCPI5_1, %xmm3 - por %xmm2, %xmm3 - movdqa %xmm3, (%edi) - - movaps LCPI5_5, %xmm1 - divps %xmm0, %xmm1 - mulps %xmm1, %xmm3 - mulps 8656(%ecx), %xmm3 - addps 8672(%ecx), %xmm3 - andps LCPI5_6, %xmm1 - andps LCPI5_1, %xmm3 - orps %xmm1, %xmm3 - movaps %xmm3, 112(%esp) - movaps %xmm3, (%ebx) - -Due to some minor source change, the later case ended up using orps and movaps -instead of por and movdqa. Does it matter? - -//===---------------------------------------------------------------------===// - -Use movddup to splat a v2f64 directly from a memory source. e.g. - -#include - -void test(__m128d *r, double A) { - *r = _mm_set1_pd(A); -} - -llc: - -_test: - movsd 8(%esp), %xmm0 - unpcklpd %xmm0, %xmm0 - movl 4(%esp), %eax - movapd %xmm0, (%eax) - ret - -icc: - -_test: - movl 4(%esp), %eax - movddup 8(%esp), %xmm0 - movapd %xmm0, (%eax) - ret - -//===---------------------------------------------------------------------===// - -X86RegisterInfo::copyRegToReg() returns X86::MOVAPSrr for VR128. Is it possible -to choose between movaps, movapd, and movdqa based on types of source and -destination? - -How about andps, andpd, and pand? Do we really care about the type of the packed -elements? If not, why not always use the "ps" variants which are likely to be -shorter. - -//===---------------------------------------------------------------------===// - -We are emitting bad code for this: - -float %test(float* %V, int %I, int %D, float %V) { -entry: - %tmp = seteq int %D, 0 - br bool %tmp, label %cond_true, label %cond_false23 - -cond_true: - %tmp3 = getelementptr float* %V, int %I - %tmp = load float* %tmp3 - %tmp5 = setgt float %tmp, %V - %tmp6 = tail call bool %llvm.isunordered.f32( float %tmp, float %V ) - %tmp7 = or bool %tmp5, %tmp6 - br bool %tmp7, label %UnifiedReturnBlock, label %cond_next - -cond_next: - %tmp10 = add int %I, 1 - %tmp12 = getelementptr float* %V, int %tmp10 - %tmp13 = load float* %tmp12 - %tmp15 = setle float %tmp13, %V - %tmp16 = tail call bool %llvm.isunordered.f32( float %tmp13, float %V ) - %tmp17 = or bool %tmp15, %tmp16 - %retval = select bool %tmp17, float 0.000000e+00, float 1.000000e+00 - ret float %retval - -cond_false23: - %tmp28 = tail call float %foo( float* %V, int %I, int %D, float %V ) - ret float %tmp28 - -UnifiedReturnBlock: ; preds = %cond_true - ret float 0.000000e+00 -} - -declare bool %llvm.isunordered.f32(float, float) - -declare float %foo(float*, int, int, float) - - -It exposes a known load folding problem: - - movss (%edx,%ecx,4), %xmm1 - ucomiss %xmm1, %xmm0 - -As well as this: - -LBB_test_2: # cond_next - movss LCPI1_0, %xmm2 - pxor %xmm3, %xmm3 - ucomiss %xmm0, %xmm1 - jbe LBB_test_6 # cond_next -LBB_test_5: # cond_next - movaps %xmm2, %xmm3 -LBB_test_6: # cond_next - movss %xmm3, 40(%esp) - flds 40(%esp) - addl $44, %esp - ret - -Clearly it's unnecessary to clear %xmm3. It's also not clear why we are emitting -three moves (movss, movaps, movss). - -//===---------------------------------------------------------------------===// - -External test Nurbs exposed some problems. Look for -__ZN15Nurbs_SSE_Cubic17TessellateSurfaceE, bb cond_next140. This is what icc -emits: - - movaps (%edx), %xmm2 #59.21 - movaps (%edx), %xmm5 #60.21 - movaps (%edx), %xmm4 #61.21 - movaps (%edx), %xmm3 #62.21 - movl 40(%ecx), %ebp #69.49 - shufps $0, %xmm2, %xmm5 #60.21 - movl 100(%esp), %ebx #69.20 - movl (%ebx), %edi #69.20 - imull %ebp, %edi #69.49 - addl (%eax), %edi #70.33 - shufps $85, %xmm2, %xmm4 #61.21 - shufps $170, %xmm2, %xmm3 #62.21 - shufps $255, %xmm2, %xmm2 #63.21 - lea (%ebp,%ebp,2), %ebx #69.49 - negl %ebx #69.49 - lea -3(%edi,%ebx), %ebx #70.33 - shll $4, %ebx #68.37 - addl 32(%ecx), %ebx #68.37 - testb $15, %bl #91.13 - jne L_B1.24 # Prob 5% #91.13 - -This is the llvm code after instruction scheduling: - -cond_next140 (0xa910740, LLVM BB @0xa90beb0): - %reg1078 = MOV32ri -3 - %reg1079 = ADD32rm %reg1078, %reg1068, 1, %NOREG, 0 - %reg1037 = MOV32rm %reg1024, 1, %NOREG, 40 - %reg1080 = IMUL32rr %reg1079, %reg1037 - %reg1081 = MOV32rm %reg1058, 1, %NOREG, 0 - %reg1038 = LEA32r %reg1081, 1, %reg1080, -3 - %reg1036 = MOV32rm %reg1024, 1, %NOREG, 32 - %reg1082 = SHL32ri %reg1038, 4 - %reg1039 = ADD32rr %reg1036, %reg1082 - %reg1083 = MOVAPSrm %reg1059, 1, %NOREG, 0 - %reg1034 = SHUFPSrr %reg1083, %reg1083, 170 - %reg1032 = SHUFPSrr %reg1083, %reg1083, 0 - %reg1035 = SHUFPSrr %reg1083, %reg1083, 255 - %reg1033 = SHUFPSrr %reg1083, %reg1083, 85 - %reg1040 = MOV32rr %reg1039 - %reg1084 = AND32ri8 %reg1039, 15 - CMP32ri8 %reg1084, 0 - JE mbb - -Still ok. After register allocation: - -cond_next140 (0xa910740, LLVM BB @0xa90beb0): - %EAX = MOV32ri -3 - %EDX = MOV32rm , 1, %NOREG, 0 - ADD32rm %EAX, %EDX, 1, %NOREG, 0 - %EDX = MOV32rm , 1, %NOREG, 0 - %EDX = MOV32rm %EDX, 1, %NOREG, 40 - IMUL32rr %EAX, %EDX - %ESI = MOV32rm , 1, %NOREG, 0 - %ESI = MOV32rm %ESI, 1, %NOREG, 0 - MOV32mr , 1, %NOREG, 0, %ESI - %EAX = LEA32r %ESI, 1, %EAX, -3 - %ESI = MOV32rm , 1, %NOREG, 0 - %ESI = MOV32rm %ESI, 1, %NOREG, 32 - %EDI = MOV32rr %EAX - SHL32ri %EDI, 4 - ADD32rr %EDI, %ESI - %XMM0 = MOVAPSrm %ECX, 1, %NOREG, 0 - %XMM1 = MOVAPSrr %XMM0 - SHUFPSrr %XMM1, %XMM1, 170 - %XMM2 = MOVAPSrr %XMM0 - SHUFPSrr %XMM2, %XMM2, 0 - %XMM3 = MOVAPSrr %XMM0 - SHUFPSrr %XMM3, %XMM3, 255 - SHUFPSrr %XMM0, %XMM0, 85 - %EBX = MOV32rr %EDI - AND32ri8 %EBX, 15 - CMP32ri8 %EBX, 0 - JE mbb - -This looks really bad. The problem is shufps is a destructive opcode. Since it -appears as operand two in more than one shufps ops. It resulted in a number of -copies. Note icc also suffers from the same problem. Either the instruction -selector should select pshufd or The register allocator can made the two-address -to three-address transformation. - -It also exposes some other problems. See MOV32ri -3 and the spills. - -//===---------------------------------------------------------------------===// - -http://gcc.gnu.org/bugzilla/show_bug.cgi?id=25500 - -LLVM is producing bad code. - -LBB_main_4: # cond_true44 - addps %xmm1, %xmm2 - subps %xmm3, %xmm2 - movaps (%ecx), %xmm4 - movaps %xmm2, %xmm1 - addps %xmm4, %xmm1 - addl $16, %ecx - incl %edx - cmpl $262144, %edx - movaps %xmm3, %xmm2 - movaps %xmm4, %xmm3 - jne LBB_main_4 # cond_true44 - -There are two problems. 1) No need to two loop induction variables. We can -compare against 262144 * 16. 2) Known register coalescer issue. We should -be able eliminate one of the movaps: - - addps %xmm2, %xmm1 <=== Commute! - subps %xmm3, %xmm1 - movaps (%ecx), %xmm4 - movaps %xmm1, %xmm1 <=== Eliminate! - addps %xmm4, %xmm1 - addl $16, %ecx - incl %edx - cmpl $262144, %edx - movaps %xmm3, %xmm2 - movaps %xmm4, %xmm3 - jne LBB_main_4 # cond_true44 - -//===---------------------------------------------------------------------===// - -Consider: - -__m128 test(float a) { - return _mm_set_ps(0.0, 0.0, 0.0, a*a); -} - -This compiles into: - -movss 4(%esp), %xmm1 -mulss %xmm1, %xmm1 -xorps %xmm0, %xmm0 -movss %xmm1, %xmm0 -ret - -Because mulss doesn't modify the top 3 elements, the top elements of -xmm1 are already zero'd. We could compile this to: - -movss 4(%esp), %xmm0 -mulss %xmm0, %xmm0 -ret - -//===---------------------------------------------------------------------===// - -Here's a sick and twisted idea. Consider code like this: - -__m128 test(__m128 a) { - float b = *(float*)&A; - ... - return _mm_set_ps(0.0, 0.0, 0.0, b); -} - -This might compile to this code: - -movaps c(%esp), %xmm1 -xorps %xmm0, %xmm0 -movss %xmm1, %xmm0 -ret - -Now consider if the ... code caused xmm1 to get spilled. This might produce -this code: - -movaps c(%esp), %xmm1 -movaps %xmm1, c2(%esp) -... - -xorps %xmm0, %xmm0 -movaps c2(%esp), %xmm1 -movss %xmm1, %xmm0 -ret - -However, since the reload is only used by these instructions, we could -"fold" it into the uses, producing something like this: - -movaps c(%esp), %xmm1 -movaps %xmm1, c2(%esp) -... - -movss c2(%esp), %xmm0 -ret - -... saving two instructions. - -The basic idea is that a reload from a spill slot, can, if only one 4-byte -chunk is used, bring in 3 zeros the the one element instead of 4 elements. -This can be used to simplify a variety of shuffle operations, where the -elements are fixed zeros. - -//===---------------------------------------------------------------------===// - We generate significantly worse code for this than GCC: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=21150 http://gcc.gnu.org/bugzilla/attachment.cgi?id=8701 @@ -1005,56 +480,6 @@ //===---------------------------------------------------------------------===// -For this: - -#include -void test(__m128d *r, __m128d *A, double B) { - *r = _mm_loadl_pd(*A, &B); -} - -We generates: - - subl $12, %esp - movsd 24(%esp), %xmm0 - movsd %xmm0, (%esp) - movl 20(%esp), %eax - movapd (%eax), %xmm0 - movlpd (%esp), %xmm0 - movl 16(%esp), %eax - movapd %xmm0, (%eax) - addl $12, %esp - ret - -icc generates: - - movl 4(%esp), %edx #3.6 - movl 8(%esp), %eax #3.6 - movapd (%eax), %xmm0 #4.22 - movlpd 12(%esp), %xmm0 #4.8 - movapd %xmm0, (%edx) #4.3 - ret #5.1 - -So icc is smart enough to know that B is in memory so it doesn't load it and -store it back to stack. - -//===---------------------------------------------------------------------===// - -__m128d test1( __m128d A, __m128d B) { - return _mm_shuffle_pd(A, B, 0x3); -} - -compiles to - -shufpd $3, %xmm1, %xmm0 - -Perhaps it's better to use unpckhpd instead? - -unpckhpd %xmm1, %xmm0 - -Don't know if unpckhpd is faster. But it is shorter. - -//===---------------------------------------------------------------------===// - If shorter, we should use things like: movzwl %ax, %eax instead of: @@ -1114,10 +539,3 @@ ret //===---------------------------------------------------------------------===// - -Some useful information in the Apple Altivec / SSE Migration Guide: - -http://developer.apple.com/documentation/Performance/Conceptual/ -Accelerate_sse_migration/index.html - -e.g. SSE select using and, andnot, or. Various SSE compare translations. From lattner at cs.uiuc.edu Fri May 19 15:55:43 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 19 May 2006 15:55:43 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/README.txt Message-ID: <200605192055.PAA02048@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: README.txt updated: 1.110 -> 1.111 --- Log message: Add a note --- Diffs of the changes: (+38 -0) README.txt | 38 ++++++++++++++++++++++++++++++++++++++ 1 files changed, 38 insertions(+) Index: llvm/lib/Target/X86/README.txt diff -u llvm/lib/Target/X86/README.txt:1.110 llvm/lib/Target/X86/README.txt:1.111 --- llvm/lib/Target/X86/README.txt:1.110 Fri May 19 15:51:43 2006 +++ llvm/lib/Target/X86/README.txt Fri May 19 15:55:31 2006 @@ -539,3 +539,41 @@ ret //===---------------------------------------------------------------------===// + +Consider this: + +typedef struct pair { float A, B; } pair; +void pairtest(pair P, float *FP) { + *FP = P.A+P.B; +} + +We currently generate this code with llvmgcc4: + +_pairtest: + subl $12, %esp + movl 20(%esp), %eax + movl %eax, 4(%esp) + movl 16(%esp), %eax + movl %eax, (%esp) + movss (%esp), %xmm0 + addss 4(%esp), %xmm0 + movl 24(%esp), %eax + movss %xmm0, (%eax) + addl $12, %esp + ret + +we should be able to generate: +_pairtest: + movss 4(%esp), %xmm0 + movl 12(%esp), %eax + addss 8(%esp), %xmm0 + movss %xmm0, (%eax) + ret + +The issue is that llvmgcc4 is forcing the struct to memory, then passing it as +integer chunks. It does this so that structs like {short,short} are passed in +a single 32-bit integer stack slot. We should handle the safe cases above much +nicer, while still handling the hard cases. + +//===---------------------------------------------------------------------===// + From lattner at cs.uiuc.edu Fri May 19 16:01:50 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 19 May 2006 16:01:50 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/README.txt Message-ID: <200605192101.QAA02226@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target: README.txt updated: 1.31 -> 1.32 --- Log message: Add a note --- Diffs of the changes: (+19 -0) README.txt | 19 +++++++++++++++++++ 1 files changed, 19 insertions(+) Index: llvm/lib/Target/README.txt diff -u llvm/lib/Target/README.txt:1.31 llvm/lib/Target/README.txt:1.32 --- llvm/lib/Target/README.txt:1.31 Fri May 19 15:45:08 2006 +++ llvm/lib/Target/README.txt Fri May 19 16:01:38 2006 @@ -220,3 +220,22 @@ http://gcc.gnu.org/bugzilla/show_bug.cgi?id=17687 //===---------------------------------------------------------------------===// + +Scalar Repl cannot currently promote this testcase to 'ret long cst': + + %struct.X = type { int, int } + %struct.Y = type { %struct.X } +ulong %bar() { + %retval = alloca %struct.Y, align 8 ; <%struct.Y*> [#uses=3] + %tmp12 = getelementptr %struct.Y* %retval, int 0, uint 0, uint 0 ; [#uses=1] + store int 0, int* %tmp12 + %tmp15 = getelementptr %struct.Y* %retval, int 0, uint 0, uint 1 ; [#uses=1] + store int 1, int* %tmp15 + %retval = cast %struct.Y* %retval to ulong* ; [#uses=1] + %retval = load ulong* %retval ; [#uses=1] + ret ulong %retval +} + +it should be extended to do so. + +//===---------------------------------------------------------------------===// From lattner at cs.uiuc.edu Fri May 19 16:15:48 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 19 May 2006 16:15:48 -0500 Subject: [llvm-commits] CVS: llvm/docs/LangRef.html Message-ID: <200605192115.QAA02414@zion.cs.uiuc.edu> Changes in directory llvm/docs: LangRef.html updated: 1.152 -> 1.153 --- Log message: New calling convention I will be adding shortly. --- Diffs of the changes: (+14 -1) LangRef.html | 15 ++++++++++++++- 1 files changed, 14 insertions(+), 1 deletion(-) Index: llvm/docs/LangRef.html diff -u llvm/docs/LangRef.html:1.152 llvm/docs/LangRef.html:1.153 --- llvm/docs/LangRef.html:1.152 Mon May 15 12:26:46 2006 +++ llvm/docs/LangRef.html Fri May 19 16:15:36 2006 @@ -464,6 +464,19 @@ prototype and implemented declaration of the function (as does normal C). +
"csretcc" - The C struct return calling convention:
+ +
This calling convention matches the target C calling conventions, except + that functions with this convention are required to take a pointer as their + first argument, and the return type of the function must be void. This is + used for C functions that return aggregates by-value. In this case, the + function has been transformed to take a pointer to the struct as the first + argument to the function. For targets where the ABI specifies specific + behavior for structure-return calls, the calling convention can be used to + distinguish between struct return functions and other functions that take a + pointer to a struct as the first argument. +
+
"fastcc" - The fast calling convention:
This calling convention attempts to make calls as fast as possible @@ -3817,7 +3830,7 @@ Chris Lattner
The LLVM Compiler Infrastructure
- Last modified: $Date: 2006/05/15 17:26:46 $ + Last modified: $Date: 2006/05/19 21:15:36 $ From lattner at cs.uiuc.edu Fri May 19 16:19:14 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 19 May 2006 16:19:14 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CallingConv.h Message-ID: <200605192119.QAA02481@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm: CallingConv.h updated: 1.2 -> 1.3 --- Log message: Add new calling convention, as documented in LangRef.html --- Diffs of the changes: (+7 -0) CallingConv.h | 7 +++++++ 1 files changed, 7 insertions(+) Index: llvm/include/llvm/CallingConv.h diff -u llvm/include/llvm/CallingConv.h:1.2 llvm/include/llvm/CallingConv.h:1.3 --- llvm/include/llvm/CallingConv.h:1.2 Wed Feb 22 10:23:42 2006 +++ llvm/include/llvm/CallingConv.h Fri May 19 16:19:02 2006 @@ -27,6 +27,13 @@ // As with typical C calling conventions, the callee/caller have to tolerate // certain amounts of prototype mismatch. C = 0, + + /// CSRet - C Struct Return calling convention. This convention requires + /// that the function return void and take a pointer as the first argument + /// of the struct. This is used by targets which need to distinguish + /// between C functions returning a structure, and C functions taking a + /// structure pointer as the first argument to the function. + CSRet = 1, // Generic LLVM calling conventions. None of these calling conventions From lattner at cs.uiuc.edu Fri May 19 16:25:29 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 19 May 2006 16:25:29 -0500 Subject: [llvm-commits] CVS: llvm/lib/VMCore/Verifier.cpp Message-ID: <200605192125.QAA02534@zion.cs.uiuc.edu> Changes in directory llvm/lib/VMCore: Verifier.cpp updated: 1.155 -> 1.156 --- Log message: csret functions can be varargs (as can target cc's). Verify restrictions on csret functions. --- Diffs of the changes: (+18 -3) Verifier.cpp | 21 ++++++++++++++++++--- 1 files changed, 18 insertions(+), 3 deletions(-) Index: llvm/lib/VMCore/Verifier.cpp diff -u llvm/lib/VMCore/Verifier.cpp:1.155 llvm/lib/VMCore/Verifier.cpp:1.156 --- llvm/lib/VMCore/Verifier.cpp:1.155 Sun May 14 13:34:36 2006 +++ llvm/lib/VMCore/Verifier.cpp Fri May 19 16:25:17 2006 @@ -302,9 +302,6 @@ // visitFunction - Verify that a function is ok. // void Verifier::visitFunction(Function &F) { - Assert1(!F.isVarArg() || F.getCallingConv() == CallingConv::C, - "Varargs functions must have C calling conventions!", &F); - // Check function arguments. const FunctionType *FT = F.getFunctionType(); unsigned NumArgs = F.getArgumentList().size(); @@ -316,6 +313,24 @@ F.getReturnType() == Type::VoidTy, "Functions cannot return aggregate values!", &F); + // Check that this function meets the restrictions on this calling convention. + switch (F.getCallingConv()) { + default: + break; + case CallingConv::C: + break; + case CallingConv::CSRet: + Assert1(FT->getReturnType() == Type::VoidTy && + FT->getNumParams() > 0 && isa(FT->getParamType(0)), + "Invalid struct-return function!", &F); + break; + case CallingConv::Fast: + case CallingConv::Cold: + Assert1(!F.isVarArg(), + "Varargs functions must have C calling conventions!", &F); + break; + } + // Check that the argument values match the function type for this function... unsigned i = 0; for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I, ++i) { From lattner at cs.uiuc.edu Fri May 19 16:28:46 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 19 May 2006 16:28:46 -0500 Subject: [llvm-commits] CVS: llvm/lib/AsmParser/llvmAsmParser.y Lexer.l Message-ID: <200605192128.QAA02603@zion.cs.uiuc.edu> Changes in directory llvm/lib/AsmParser: llvmAsmParser.y updated: 1.253 -> 1.254 Lexer.l updated: 1.73 -> 1.74 --- Log message: Add support for parsing csret --- Diffs of the changes: (+3 -1) Lexer.l | 1 + llvmAsmParser.y | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) Index: llvm/lib/AsmParser/llvmAsmParser.y diff -u llvm/lib/AsmParser/llvmAsmParser.y:1.253 llvm/lib/AsmParser/llvmAsmParser.y:1.254 --- llvm/lib/AsmParser/llvmAsmParser.y:1.253 Fri Apr 7 23:08:32 2006 +++ llvm/lib/AsmParser/llvmAsmParser.y Fri May 19 16:28:34 2006 @@ -981,7 +981,7 @@ %token TO DOTDOTDOT NULL_TOK UNDEF CONST INTERNAL LINKONCE WEAK APPENDING %token OPAQUE NOT EXTERNAL TARGET TRIPLE ENDIAN POINTERSIZE LITTLE BIG ALIGN %token DEPLIBS CALL TAIL ASM_TOK MODULE SIDEEFFECT -%token CC_TOK CCC_TOK FASTCC_TOK COLDCC_TOK +%token CC_TOK CCC_TOK CSRETCC_TOK FASTCC_TOK COLDCC_TOK %type OptCallingConv // Basic Block Terminating Operators @@ -1054,6 +1054,7 @@ OptCallingConv : /*empty*/ { $$ = CallingConv::C; } | CCC_TOK { $$ = CallingConv::C; } | + CSRETCC_TOK { $$ = CallingConv::CSRet; } | FASTCC_TOK { $$ = CallingConv::Fast; } | COLDCC_TOK { $$ = CallingConv::Cold; } | CC_TOK EUINT64VAL { Index: llvm/lib/AsmParser/Lexer.l diff -u llvm/lib/AsmParser/Lexer.l:1.73 llvm/lib/AsmParser/Lexer.l:1.74 --- llvm/lib/AsmParser/Lexer.l:1.73 Fri Apr 7 20:18:35 2006 +++ llvm/lib/AsmParser/Lexer.l Fri May 19 16:28:34 2006 @@ -218,6 +218,7 @@ cc { return CC_TOK; } ccc { return CCC_TOK; } +csretcc { return CSRETCC_TOK; } fastcc { return FASTCC_TOK; } coldcc { return COLDCC_TOK; } From lattner at cs.uiuc.edu Fri May 19 16:29:06 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 19 May 2006 16:29:06 -0500 Subject: [llvm-commits] CVS: llvm/lib/AsmParser/Lexer.cpp.cvs Lexer.l.cvs llvmAsmParser.cpp.cvs llvmAsmParser.h.cvs llvmAsmParser.y.cvs Message-ID: <200605192129.QAA02644@zion.cs.uiuc.edu> Changes in directory llvm/lib/AsmParser: Lexer.cpp.cvs updated: 1.4 -> 1.5 Lexer.l.cvs updated: 1.3 -> 1.4 llvmAsmParser.cpp.cvs updated: 1.5 -> 1.6 llvmAsmParser.h.cvs updated: 1.2 -> 1.3 llvmAsmParser.y.cvs updated: 1.5 -> 1.6 --- Log message: Regenerate --- Diffs of the changes: (+1451 -1438) Lexer.cpp.cvs | 939 ++++++++++++------------- Lexer.l.cvs | 1 llvmAsmParser.cpp.cvs | 1842 +++++++++++++++++++++++++------------------------- llvmAsmParser.h.cvs | 79 +- llvmAsmParser.y.cvs | 3 5 files changed, 1451 insertions(+), 1413 deletions(-) Index: llvm/lib/AsmParser/Lexer.cpp.cvs diff -u llvm/lib/AsmParser/Lexer.cpp.cvs:1.4 llvm/lib/AsmParser/Lexer.cpp.cvs:1.5 --- llvm/lib/AsmParser/Lexer.cpp.cvs:1.4 Fri Apr 7 20:18:56 2006 +++ llvm/lib/AsmParser/Lexer.cpp.cvs Fri May 19 16:28:53 2006 @@ -20,7 +20,7 @@ /* A lexical scanner generated by flex */ /* Scanner skeleton version: - * $Header: /var/cvs/llvm/llvm/lib/AsmParser/Lexer.cpp.cvs,v 1.4 2006/04/08 01:18:56 lattner Exp $ + * $Header: /var/cvs/llvm/llvm/lib/AsmParser/Lexer.cpp.cvs,v 1.5 2006/05/19 21:28:53 lattner Exp $ */ #define FLEX_SCANNER @@ -308,33 +308,33 @@ *yy_cp = '\0'; \ yy_c_buf_p = yy_cp; -#define YY_NUM_RULES 107 -#define YY_END_OF_BUFFER 108 -static yyconst short int yy_acclist[185] = +#define YY_NUM_RULES 108 +#define YY_END_OF_BUFFER 109 +static yyconst short int yy_acclist[186] = { 0, - 108, 106, 107, 105, 106, 107, 105, 107, 106, 107, - 106, 107, 106, 107, 106, 107, 106, 107, 106, 107, - 98, 106, 107, 98, 106, 107, 1, 106, 107, 106, - 107, 106, 107, 106, 107, 106, 107, 106, 107, 106, - 107, 106, 107, 106, 107, 106, 107, 106, 107, 106, - 107, 106, 107, 106, 107, 106, 107, 106, 107, 106, - 107, 106, 107, 106, 107, 106, 107, 106, 107, 106, - 107, 97, 95, 94, 94, 101, 99, 103, 98, 1, - 80, 37, 62, 20, 97, 94, 94, 102, 103, 17, - 103, 104, 56, 61, 35, 30, 38, 59, 3, 47, - - 58, 22, 70, 60, 79, 74, 75, 57, 63, 96, - 103, 103, 42, 71, 72, 87, 88, 49, 19, 100, - 23, 4, 54, 48, 41, 11, 103, 32, 2, 5, - 51, 53, 43, 65, 69, 67, 68, 66, 64, 45, - 89, 44, 50, 18, 77, 86, 40, 52, 27, 21, - 39, 7, 82, 29, 85, 34, 55, 73, 81, 24, - 25, 83, 46, 78, 76, 6, 26, 33, 8, 14, - 9, 10, 31, 12, 36, 28, 84, 90, 92, 93, - 13, 91, 15, 16 + 109, 107, 108, 106, 107, 108, 106, 108, 107, 108, + 107, 108, 107, 108, 107, 108, 107, 108, 107, 108, + 99, 107, 108, 99, 107, 108, 1, 107, 108, 107, + 108, 107, 108, 107, 108, 107, 108, 107, 108, 107, + 108, 107, 108, 107, 108, 107, 108, 107, 108, 107, + 108, 107, 108, 107, 108, 107, 108, 107, 108, 107, + 108, 107, 108, 107, 108, 107, 108, 107, 108, 107, + 108, 98, 96, 95, 95, 102, 100, 104, 99, 1, + 81, 37, 63, 20, 98, 95, 95, 103, 104, 17, + 104, 105, 57, 62, 35, 30, 38, 60, 3, 48, + + 59, 22, 71, 61, 80, 75, 76, 58, 64, 97, + 104, 104, 43, 72, 73, 88, 89, 50, 19, 101, + 23, 4, 55, 49, 42, 11, 104, 32, 2, 5, + 52, 54, 44, 66, 70, 68, 69, 67, 65, 46, + 90, 45, 51, 18, 78, 87, 41, 53, 27, 21, + 40, 7, 83, 29, 86, 34, 56, 74, 82, 24, + 25, 84, 47, 79, 77, 39, 6, 26, 33, 8, + 14, 9, 10, 31, 12, 36, 28, 85, 91, 93, + 94, 13, 92, 15, 16 } ; -static yyconst short int yy_accept[455] = +static yyconst short int yy_accept[461] = { 0, 1, 1, 1, 2, 4, 7, 9, 11, 13, 15, 17, 19, 21, 24, 27, 30, 32, 34, 36, 38, @@ -344,48 +344,48 @@ 81, 81, 81, 81, 81, 81, 81, 81, 81, 82, 82, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, - 83, 83, 83, 83, 84, 84, 84, 84, 84, 84, - 84, 84, 84, 84, 84, 84, 84, 85, 85, 85, + 83, 83, 83, 83, 83, 84, 84, 84, 84, 84, + 84, 84, 84, 84, 84, 84, 84, 84, 85, 85, 85, 85, 85, 85, 85, 85, 85, 85, 85, 85, - 86, 87, 89, 90, 91, 92, 92, 93, 94, 94, - 94, 95, 95, 96, 96, 97, 97, 97, 97, 98, - 98, 98, 98, 98, 99, 99, 100, 100, 100, 100, - 100, 100, 100, 100, 100, 100, 100, 101, 101, 101, - 101, 101, 101, 101, 101, 101, 102, 103, 103, 103, - 104, 104, 105, 106, 106, 106, 106, 106, 106, 107, - 107, 108, 108, 108, 108, 109, 109, 109, 109, 109, + 85, 86, 87, 89, 90, 91, 92, 92, 93, 94, + 94, 94, 95, 95, 96, 96, 97, 97, 97, 97, + 98, 98, 98, 98, 98, 98, 99, 99, 100, 100, + 100, 100, 100, 100, 100, 100, 100, 100, 100, 101, + 101, 101, 101, 101, 101, 101, 101, 101, 102, 103, + 103, 103, 104, 104, 105, 106, 106, 106, 106, 106, + 106, 107, 107, 108, 108, 108, 108, 109, 109, 109, 109, 109, 109, 109, 109, 109, 109, 109, 109, 109, - 109, 109, 109, 109, 109, 109, 110, 110, 111, 112, + 109, 109, 109, 109, 109, 109, 109, 109, 110, 110, - 112, 112, 112, 113, 113, 113, 113, 113, 114, 115, - 116, 116, 116, 116, 116, 116, 116, 116, 116, 116, - 116, 116, 116, 117, 117, 117, 117, 117, 117, 117, - 117, 117, 117, 118, 119, 119, 119, 120, 120, 120, - 121, 121, 121, 121, 121, 121, 121, 121, 121, 121, - 121, 121, 121, 122, 122, 122, 123, 124, 124, 125, - 125, 125, 125, 125, 125, 125, 125, 125, 125, 126, - 126, 127, 127, 128, 129, 129, 129, 130, 130, 130, - 130, 130, 130, 130, 130, 130, 130, 131, 131, 132, - 132, 132, 132, 132, 132, 132, 133, 133, 133, 133, - - 133, 133, 133, 134, 134, 134, 135, 136, 137, 138, - 139, 140, 141, 141, 141, 142, 142, 142, 142, 143, - 144, 145, 145, 145, 145, 145, 145, 146, 146, 146, - 146, 147, 147, 148, 148, 148, 148, 149, 150, 151, - 151, 151, 152, 152, 153, 153, 153, 153, 154, 154, - 155, 156, 157, 158, 158, 158, 159, 159, 159, 160, - 161, 162, 162, 162, 163, 164, 165, 166, 166, 166, - 166, 166, 167, 168, 168, 168, 168, 168, 168, 168, - 168, 168, 169, 169, 169, 169, 169, 169, 169, 169, - 170, 171, 171, 171, 171, 171, 172, 173, 173, 173, - - 173, 173, 173, 174, 174, 175, 175, 175, 175, 175, - 175, 175, 175, 175, 175, 175, 175, 175, 175, 175, - 175, 175, 176, 176, 176, 176, 176, 176, 176, 176, - 177, 177, 177, 178, 178, 178, 178, 178, 178, 178, - 178, 178, 178, 179, 179, 180, 181, 182, 182, 183, - 184, 184, 185, 185 + 111, 112, 112, 112, 112, 113, 113, 113, 113, 113, + 114, 115, 116, 116, 116, 116, 116, 116, 116, 116, + 116, 116, 116, 116, 116, 116, 117, 117, 117, 117, + 117, 117, 117, 117, 117, 117, 118, 119, 119, 119, + 120, 120, 120, 121, 121, 121, 121, 121, 121, 121, + 121, 121, 121, 121, 121, 121, 122, 122, 122, 123, + 124, 124, 125, 125, 125, 125, 125, 125, 125, 125, + 125, 125, 126, 126, 127, 127, 128, 129, 129, 129, + 130, 130, 130, 130, 130, 130, 130, 130, 130, 130, + 130, 131, 131, 132, 132, 132, 132, 132, 132, 132, + + 133, 133, 133, 133, 133, 133, 133, 134, 134, 134, + 135, 136, 137, 138, 139, 140, 141, 141, 141, 142, + 142, 142, 142, 143, 144, 145, 145, 145, 145, 145, + 145, 146, 146, 146, 146, 147, 147, 148, 148, 148, + 148, 148, 149, 150, 151, 151, 151, 152, 152, 153, + 153, 153, 153, 154, 154, 155, 156, 157, 158, 158, + 158, 159, 159, 159, 160, 161, 162, 162, 162, 163, + 164, 165, 166, 166, 166, 166, 166, 167, 168, 169, + 169, 169, 169, 169, 169, 169, 169, 169, 170, 170, + 170, 170, 170, 170, 170, 170, 171, 172, 172, 172, + + 172, 172, 173, 174, 174, 174, 174, 174, 174, 175, + 175, 176, 176, 176, 176, 176, 176, 176, 176, 176, + 176, 176, 176, 176, 176, 176, 176, 176, 177, 177, + 177, 177, 177, 177, 177, 177, 178, 178, 178, 179, + 179, 179, 179, 179, 179, 179, 179, 179, 179, 180, + 180, 181, 182, 183, 183, 184, 185, 185, 186, 186 } ; static yyconst int yy_ec[256] = @@ -429,115 +429,117 @@ 3 } ; -static yyconst short int yy_base[459] = +static yyconst short int yy_base[465] = { 0, - 0, 0, 948, 949, 949, 949, 943, 934, 34, 36, + 0, 0, 960, 961, 961, 961, 955, 946, 34, 36, 38, 42, 46, 50, 0, 52, 57, 54, 68, 62, - 80, 82, 76, 94, 98, 40, 83, 88, 56, 125, - 108, 154, 109, 87, 110, 111, 941, 949, 932, 949, - 0, 119, 134, 142, 145, 124, 159, 166, 179, 0, - 55, 180, 147, 153, 119, 150, 183, 156, 931, 175, - 191, 192, 196, 90, 146, 200, 199, 201, 202, 204, - 205, 211, 212, 210, 218, 217, 221, 227, 236, 230, - 214, 239, 241, 930, 243, 247, 248, 225, 249, 250, - 251, 253, 258, 262, 267, 270, 929, 274, 259, 279, - - 282, 263, 284, 41, 285, 288, 295, 84, 293, 928, - 0, 310, 313, 927, 320, 332, 0, 926, 304, 306, - 925, 317, 924, 321, 923, 325, 333, 313, 922, 286, - 335, 337, 338, 921, 339, 341, 342, 346, 343, 347, - 344, 350, 360, 356, 358, 363, 366, 361, 368, 364, - 371, 374, 376, 380, 381, 920, 919, 383, 31, 918, - 384, 917, 916, 408, 385, 386, 388, 412, 915, 399, - 914, 390, 393, 403, 913, 396, 389, 422, 425, 426, - 428, 430, 431, 432, 434, 438, 436, 439, 440, 441, - 442, 447, 451, 457, 450, 912, 448, 949, 462, 474, - - 393, 476, 479, 467, 480, 468, 481, 911, 910, 909, - 482, 483, 486, 488, 490, 492, 493, 494, 495, 499, - 496, 502, 908, 504, 509, 507, 510, 511, 513, 518, - 517, 521, 907, 906, 520, 522, 905, 523, 526, 0, - 530, 528, 543, 524, 542, 545, 546, 529, 548, 553, - 557, 556, 904, 560, 559, 903, 902, 561, 901, 564, - 567, 571, 573, 572, 576, 579, 580, 581, 900, 582, - 899, 583, 587, 898, 587, 590, 897, 588, 594, 593, - 534, 601, 602, 603, 604, 606, 896, 609, 895, 611, - 607, 612, 615, 617, 618, 894, 623, 624, 625, 630, - - 635, 636, 893, 629, 631, 892, 891, 890, 889, 888, - 887, 886, 637, 641, 885, 643, 642, 648, 884, 883, - 882, 646, 649, 650, 653, 659, 881, 660, 661, 662, - 880, 664, 879, 663, 666, 667, 878, 877, 876, 668, - 671, 875, 672, 874, 678, 681, 686, 873, 685, 872, - 871, 870, 869, 682, 684, 868, 693, 695, 867, 866, - 865, 696, 698, 864, 863, 862, 861, 697, 700, 699, - 704, 860, 857, 706, 708, 711, 707, 714, 715, 719, - 718, 848, 722, 723, 726, 733, 725, 735, 737, 847, - 845, 736, 739, 741, 743, 843, 842, 742, 744, 750, - - 745, 759, 841, 749, 840, 754, 746, 761, 767, 768, - 770, 771, 772, 773, 774, 775, 776, 778, 780, 781, - 782, 838, 784, 787, 792, 793, 786, 798, 799, 835, - 800, 803, 834, 804, 806, 808, 810, 814, 815, 819, - 820, 821, 832, 822, 831, 830, 826, 824, 296, 255, - 825, 219, 949, 861, 863, 182, 867, 139 + 80, 82, 83, 93, 102, 40, 84, 92, 56, 129, + 112, 158, 113, 87, 90, 114, 953, 961, 944, 961, + 0, 117, 123, 146, 149, 128, 163, 170, 183, 0, + 55, 119, 151, 157, 178, 139, 154, 177, 943, 184, + 196, 187, 88, 198, 197, 136, 200, 207, 201, 209, + 210, 211, 213, 218, 220, 215, 212, 233, 224, 228, + 225, 226, 232, 174, 942, 124, 241, 244, 246, 248, + 251, 257, 253, 252, 256, 255, 264, 941, 269, 265, + + 259, 263, 271, 283, 41, 290, 286, 292, 279, 298, + 940, 0, 304, 307, 939, 314, 326, 0, 938, 318, + 315, 937, 311, 936, 327, 935, 328, 330, 308, 934, + 334, 332, 335, 336, 337, 933, 341, 346, 339, 349, + 338, 350, 356, 353, 355, 357, 365, 366, 367, 368, + 369, 371, 372, 374, 377, 379, 381, 932, 931, 383, + 31, 930, 384, 929, 928, 408, 389, 396, 390, 420, + 927, 387, 926, 392, 391, 403, 925, 404, 421, 422, + 409, 423, 425, 426, 430, 438, 439, 440, 441, 443, + 442, 446, 444, 445, 458, 447, 459, 924, 461, 961, + + 465, 482, 471, 484, 487, 471, 489, 475, 476, 923, + 922, 921, 490, 472, 491, 462, 494, 498, 499, 500, + 501, 503, 502, 505, 506, 920, 509, 510, 516, 517, + 518, 520, 521, 523, 527, 919, 918, 526, 528, 917, + 530, 532, 0, 531, 533, 545, 537, 547, 549, 550, + 548, 551, 553, 560, 566, 916, 565, 563, 915, 914, + 567, 913, 564, 577, 568, 579, 580, 582, 583, 585, + 586, 912, 588, 911, 589, 592, 910, 593, 592, 909, + 594, 605, 599, 595, 608, 609, 607, 612, 615, 619, + 908, 620, 907, 621, 622, 617, 623, 625, 629, 906, + + 628, 631, 634, 639, 643, 644, 905, 636, 647, 904, + 903, 902, 901, 900, 899, 898, 649, 650, 897, 651, + 655, 656, 896, 895, 894, 657, 659, 661, 658, 662, + 893, 667, 671, 668, 892, 674, 891, 672, 675, 677, + 676, 890, 889, 888, 683, 679, 887, 691, 886, 692, + 694, 695, 885, 697, 884, 883, 882, 881, 693, 696, + 880, 699, 705, 879, 878, 877, 706, 709, 876, 875, + 874, 873, 710, 711, 712, 716, 872, 871, 868, 717, + 718, 722, 720, 723, 726, 733, 728, 858, 730, 734, + 735, 744, 736, 746, 747, 857, 856, 748, 751, 752, + + 753, 854, 853, 754, 756, 757, 759, 760, 851, 770, + 850, 771, 761, 772, 773, 776, 778, 779, 781, 782, + 786, 787, 788, 790, 792, 795, 793, 848, 796, 799, + 800, 809, 798, 806, 810, 846, 811, 814, 844, 817, + 820, 812, 822, 824, 828, 826, 831, 832, 843, 835, + 842, 841, 839, 836, 535, 397, 838, 393, 961, 872, + 874, 297, 878, 103 } ; -static yyconst short int yy_def[459] = +static yyconst short int yy_def[465] = { 0, - 453, 1, 453, 453, 453, 453, 454, 455, 456, 453, - 455, 455, 455, 455, 457, 455, 455, 455, 455, 455, - 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, - 455, 455, 455, 455, 455, 455, 454, 453, 455, 453, - 458, 458, 453, 453, 455, 455, 455, 455, 455, 457, - 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, - 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, - 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, - 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, - 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, - - 455, 455, 455, 455, 455, 455, 455, 455, 455, 453, - 458, 458, 453, 455, 455, 455, 49, 455, 455, 455, - 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, - 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, - 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, - 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, - 455, 455, 455, 49, 455, 455, 455, 455, 455, 455, - 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, - 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, - 455, 455, 455, 455, 455, 455, 455, 453, 453, 453, - - 453, 455, 455, 455, 455, 455, 455, 455, 455, 455, - 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, - 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, - 455, 455, 455, 455, 455, 455, 455, 455, 455, 164, - 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, - 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, - 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, - 455, 455, 453, 455, 455, 455, 455, 455, 455, 455, - 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, - 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, - - 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, - 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, - 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, - 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, - 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, - 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, - 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, - 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, - 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, - 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, - - 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, - 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, - 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, - 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, - 455, 455, 455, 455, 455, 455, 455, 455, 455, 455, - 455, 455, 0, 453, 453, 453, 453, 453 + 459, 1, 459, 459, 459, 459, 460, 461, 462, 459, + 461, 461, 461, 461, 463, 461, 461, 461, 461, 461, + 461, 461, 461, 461, 461, 461, 461, 461, 461, 461, + 461, 461, 461, 461, 461, 461, 460, 459, 461, 459, + 464, 464, 459, 459, 461, 461, 461, 461, 461, 463, + 461, 461, 461, 461, 461, 461, 461, 461, 461, 461, + 461, 461, 461, 461, 461, 461, 461, 461, 461, 461, + 461, 461, 461, 461, 461, 461, 461, 461, 461, 461, + 461, 461, 461, 461, 461, 461, 461, 461, 461, 461, + 461, 461, 461, 461, 461, 461, 461, 461, 461, 461, + + 461, 461, 461, 461, 461, 461, 461, 461, 461, 461, + 459, 464, 464, 459, 461, 461, 461, 49, 461, 461, + 461, 461, 461, 461, 461, 461, 461, 461, 461, 461, + 461, 461, 461, 461, 461, 461, 461, 461, 461, 461, + 461, 461, 461, 461, 461, 461, 461, 461, 461, 461, + 461, 461, 461, 461, 461, 461, 461, 461, 461, 461, + 461, 461, 461, 461, 461, 49, 461, 461, 461, 461, + 461, 461, 461, 461, 461, 461, 461, 461, 461, 461, + 461, 461, 461, 461, 461, 461, 461, 461, 461, 461, + 461, 461, 461, 461, 461, 461, 461, 461, 461, 459, + + 459, 459, 459, 461, 461, 461, 461, 461, 461, 461, + 461, 461, 461, 461, 461, 461, 461, 461, 461, 461, + 461, 461, 461, 461, 461, 461, 461, 461, 461, 461, + 461, 461, 461, 461, 461, 461, 461, 461, 461, 461, + 461, 461, 166, 461, 461, 461, 461, 461, 461, 461, + 461, 461, 461, 461, 461, 461, 461, 461, 461, 461, + 461, 461, 461, 461, 461, 461, 461, 461, 461, 461, + 461, 461, 461, 461, 461, 459, 461, 461, 461, 461, + 461, 461, 461, 461, 461, 461, 461, 461, 461, 461, + 461, 461, 461, 461, 461, 461, 461, 461, 461, 461, + + 461, 461, 461, 461, 461, 461, 461, 461, 461, 461, + 461, 461, 461, 461, 461, 461, 461, 461, 461, 461, + 461, 461, 461, 461, 461, 461, 461, 461, 461, 461, + 461, 461, 461, 461, 461, 461, 461, 461, 461, 461, + 461, 461, 461, 461, 461, 461, 461, 461, 461, 461, + 461, 461, 461, 461, 461, 461, 461, 461, 461, 461, + 461, 461, 461, 461, 461, 461, 461, 461, 461, 461, + 461, 461, 461, 461, 461, 461, 461, 461, 461, 461, + 461, 461, 461, 461, 461, 461, 461, 461, 461, 461, + 461, 461, 461, 461, 461, 461, 461, 461, 461, 461, + + 461, 461, 461, 461, 461, 461, 461, 461, 461, 461, + 461, 461, 461, 461, 461, 461, 461, 461, 461, 461, + 461, 461, 461, 461, 461, 461, 461, 461, 461, 461, + 461, 461, 461, 461, 461, 461, 461, 461, 461, 461, + 461, 461, 461, 461, 461, 461, 461, 461, 461, 461, + 461, 461, 461, 461, 461, 461, 461, 461, 0, 459, + 459, 459, 459, 459 } ; -static yyconst short int yy_nxt[991] = +static yyconst short int yy_nxt[1003] = { 0, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 4, 15, 8, 8, 8, 16, 17, 18, 19, @@ -545,220 +547,226 @@ 28, 8, 29, 30, 31, 32, 33, 34, 35, 8, 36, 42, 40, 43, 43, 44, 44, 45, 45, 40, 46, 40, 40, 40, 47, 48, 48, 40, 47, 48, - 48, 40, 238, 40, 189, 40, 40, 40, 40, 81, - 60, 51, 61, 40, 118, 82, 87, 56, 52, 40, - 53, 57, 54, 62, 49, 55, 58, 40, 63, 59, - 66, 40, 64, 40, 40, 40, 68, 65, 40, 40, - - 67, 40, 71, 73, 74, 40, 69, 107, 72, 40, - 75, 85, 70, 83, 78, 84, 196, 86, 76, 40, - 40, 40, 40, 77, 96, 105, 134, 79, 112, 112, - 40, 109, 114, 80, 88, 40, 40, 97, 106, 108, - 98, 111, 89, 43, 43, 90, 123, 99, 91, 92, - 113, 44, 44, 47, 45, 45, 40, 40, 40, 93, - 94, 40, 95, 88, 40, 40, 121, 40, 115, 115, - 40, 100, 124, 116, 47, 48, 48, 40, 101, 116, - 102, 135, 103, 122, 41, 126, 40, 104, 117, 117, - 40, 40, 117, 117, 40, 117, 117, 117, 117, 117, - - 117, 127, 40, 40, 119, 125, 120, 40, 128, 129, - 40, 40, 40, 40, 132, 40, 40, 137, 130, 136, - 131, 40, 40, 40, 142, 40, 133, 139, 40, 40, - 40, 141, 40, 138, 140, 149, 40, 152, 40, 143, - 144, 40, 145, 146, 147, 150, 148, 40, 157, 153, - 40, 151, 40, 154, 40, 155, 156, 159, 40, 40, - 40, 40, 40, 164, 40, 158, 40, 160, 166, 40, - 40, 161, 173, 40, 40, 162, 167, 169, 40, 175, - 170, 40, 163, 171, 168, 40, 172, 174, 165, 181, - 40, 176, 184, 40, 177, 40, 40, 40, 179, 40, - - 190, 191, 178, 185, 40, 211, 40, 40, 186, 180, - 183, 195, 193, 192, 194, 40, 187, 40, 182, 112, - 112, 188, 199, 199, 40, 197, 204, 200, 40, 115, - 115, 40, 40, 200, 116, 205, 40, 206, 201, 202, - 116, 203, 203, 40, 40, 207, 40, 210, 40, 40, - 40, 208, 40, 40, 40, 40, 215, 40, 40, 209, - 222, 40, 217, 213, 214, 216, 218, 40, 212, 40, - 223, 40, 40, 225, 40, 40, 220, 40, 219, 40, - 224, 221, 40, 227, 226, 40, 228, 40, 230, 231, - 229, 40, 40, 233, 40, 40, 40, 40, 234, 40, - - 40, 40, 273, 273, 40, 232, 235, 40, 243, 237, - 40, 249, 239, 250, 40, 253, 236, 240, 240, 241, - 242, 240, 240, 40, 240, 240, 240, 240, 240, 240, - 252, 248, 244, 40, 245, 251, 40, 40, 246, 40, - 247, 40, 40, 40, 254, 40, 256, 40, 257, 40, - 40, 40, 40, 40, 261, 255, 263, 266, 40, 40, - 260, 40, 40, 264, 258, 259, 262, 268, 40, 265, - 269, 199, 199, 270, 267, 271, 200, 272, 40, 40, - 201, 201, 200, 273, 273, 203, 203, 40, 203, 203, - 40, 40, 40, 40, 40, 274, 276, 40, 275, 40, - - 278, 40, 280, 40, 40, 40, 40, 40, 283, 277, - 40, 286, 281, 40, 288, 40, 282, 279, 40, 287, - 40, 40, 40, 284, 40, 291, 285, 292, 40, 40, - 290, 40, 40, 40, 40, 40, 289, 40, 295, 40, - 40, 40, 293, 294, 296, 40, 297, 298, 300, 299, - 303, 336, 304, 40, 40, 306, 40, 40, 301, 40, - 302, 305, 307, 312, 40, 309, 311, 40, 40, 313, - 40, 40, 40, 314, 316, 40, 308, 315, 40, 310, - 317, 319, 40, 40, 40, 318, 320, 40, 321, 323, - 40, 40, 40, 40, 40, 322, 273, 273, 40, 40, - - 324, 40, 327, 331, 40, 40, 333, 330, 325, 332, - 334, 326, 40, 40, 40, 40, 329, 40, 40, 328, - 40, 337, 40, 40, 341, 335, 40, 342, 40, 40, - 338, 343, 340, 344, 40, 40, 40, 339, 348, 345, - 40, 40, 40, 351, 350, 347, 40, 40, 40, 346, - 352, 349, 40, 40, 40, 353, 354, 40, 355, 40, - 40, 40, 358, 357, 40, 356, 359, 363, 361, 364, - 40, 40, 40, 40, 40, 40, 360, 40, 40, 40, - 362, 366, 40, 40, 374, 368, 372, 365, 370, 40, - 369, 371, 40, 40, 367, 40, 40, 40, 377, 376, - - 373, 378, 379, 380, 40, 375, 40, 40, 40, 40, - 40, 40, 382, 383, 381, 40, 384, 40, 40, 40, - 385, 386, 40, 387, 388, 40, 40, 389, 392, 40, - 40, 393, 391, 40, 40, 394, 40, 40, 390, 397, - 395, 396, 401, 400, 40, 403, 40, 40, 40, 402, - 40, 398, 40, 40, 40, 40, 40, 40, 399, 405, - 40, 40, 406, 409, 411, 40, 410, 407, 412, 404, - 40, 413, 40, 415, 416, 408, 414, 418, 40, 40, - 417, 40, 40, 40, 40, 40, 40, 40, 421, 40, - 425, 40, 40, 40, 419, 40, 423, 40, 40, 424, - - 429, 430, 426, 40, 40, 422, 427, 433, 420, 40, - 40, 40, 428, 435, 40, 40, 431, 40, 434, 40, - 436, 40, 437, 440, 432, 40, 40, 438, 441, 439, - 40, 40, 40, 40, 442, 40, 40, 40, 447, 444, - 443, 40, 40, 40, 451, 40, 40, 446, 445, 40, - 450, 40, 40, 40, 40, 449, 40, 452, 40, 40, - 448, 37, 37, 37, 37, 39, 39, 50, 40, 50, - 50, 40, 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 48, 40, 241, 40, 191, 40, 40, 40, 40, 82, + 60, 51, 61, 40, 119, 83, 88, 56, 52, 40, + 53, 57, 54, 62, 49, 55, 58, 63, 64, 59, + 67, 40, 65, 40, 40, 40, 69, 66, 40, 40, + + 68, 40, 72, 40, 40, 112, 70, 108, 73, 76, + 74, 75, 71, 40, 84, 86, 85, 77, 79, 109, + 133, 87, 78, 40, 40, 40, 113, 113, 97, 106, + 40, 80, 43, 43, 110, 40, 115, 81, 89, 40, + 40, 98, 107, 120, 99, 121, 90, 40, 162, 91, + 40, 100, 92, 93, 114, 44, 44, 47, 45, 45, + 40, 125, 40, 94, 95, 40, 96, 89, 40, 40, + 122, 137, 116, 116, 40, 101, 126, 117, 47, 48, + 48, 40, 102, 117, 103, 40, 104, 123, 40, 40, + 161, 105, 118, 118, 40, 40, 118, 118, 40, 118, + + 118, 118, 118, 118, 118, 124, 127, 40, 40, 40, + 128, 40, 40, 131, 130, 132, 134, 129, 40, 138, + 40, 40, 40, 40, 40, 139, 40, 141, 135, 40, + 144, 40, 151, 136, 142, 40, 40, 40, 143, 40, + 152, 140, 146, 40, 40, 145, 153, 157, 147, 154, + 156, 158, 40, 148, 149, 40, 150, 40, 160, 40, + 159, 155, 40, 40, 40, 163, 40, 40, 40, 168, + 40, 164, 175, 177, 40, 40, 40, 169, 165, 178, + 40, 176, 40, 171, 166, 170, 172, 167, 179, 173, + 40, 185, 174, 181, 40, 183, 180, 40, 184, 41, + + 186, 40, 187, 40, 182, 192, 193, 188, 197, 40, + 195, 198, 196, 113, 113, 189, 201, 201, 194, 40, + 190, 202, 40, 116, 116, 40, 40, 202, 117, 40, + 199, 208, 203, 204, 117, 205, 205, 40, 40, 40, + 206, 40, 212, 40, 207, 40, 40, 40, 40, 40, + 40, 209, 40, 213, 210, 215, 211, 40, 218, 220, + 40, 40, 216, 217, 40, 214, 40, 40, 40, 221, + 219, 223, 225, 226, 228, 227, 40, 40, 40, 40, + 40, 222, 40, 40, 224, 40, 230, 231, 40, 233, + 40, 229, 40, 236, 40, 40, 234, 232, 40, 237, + + 40, 40, 40, 40, 40, 238, 235, 40, 40, 240, + 246, 253, 242, 252, 40, 40, 239, 243, 243, 251, + 40, 243, 243, 244, 243, 243, 243, 243, 243, 243, + 245, 40, 40, 40, 40, 254, 40, 40, 255, 258, + 247, 40, 248, 259, 257, 260, 249, 256, 250, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 264, + 261, 266, 269, 273, 262, 271, 263, 267, 265, 40, + 40, 268, 40, 40, 201, 201, 270, 272, 284, 202, + 276, 276, 40, 40, 274, 202, 40, 40, 203, 203, + 275, 276, 276, 205, 205, 40, 205, 205, 40, 277, + + 40, 40, 40, 279, 280, 40, 282, 278, 281, 40, + 40, 40, 40, 40, 40, 287, 40, 40, 285, 290, + 40, 40, 291, 292, 286, 283, 295, 40, 40, 40, + 288, 40, 40, 289, 40, 294, 296, 40, 40, 40, + 293, 40, 40, 40, 40, 299, 40, 300, 40, 297, + 298, 307, 301, 302, 304, 303, 40, 308, 40, 40, + 40, 40, 40, 309, 40, 305, 306, 311, 310, 313, + 315, 40, 317, 318, 40, 40, 40, 40, 40, 40, + 319, 312, 316, 314, 320, 321, 324, 323, 40, 322, + 40, 40, 326, 40, 40, 327, 40, 40, 325, 40, + + 40, 276, 276, 40, 40, 40, 40, 331, 328, 335, + 40, 336, 337, 334, 329, 330, 40, 339, 40, 40, + 40, 338, 333, 40, 332, 341, 40, 340, 40, 342, + 40, 40, 40, 40, 40, 343, 40, 346, 347, 40, + 40, 348, 40, 345, 350, 40, 344, 40, 349, 353, + 40, 355, 356, 352, 40, 40, 354, 351, 40, 357, + 40, 40, 40, 358, 359, 360, 40, 40, 40, 40, + 40, 363, 40, 40, 364, 362, 366, 368, 40, 40, + 369, 361, 40, 40, 371, 40, 40, 40, 40, 365, + 40, 367, 370, 377, 40, 373, 374, 378, 375, 380, + + 376, 372, 40, 40, 40, 40, 40, 40, 40, 379, + 40, 385, 383, 381, 384, 386, 40, 40, 382, 389, + 40, 40, 40, 40, 388, 387, 390, 40, 40, 40, + 391, 40, 392, 40, 40, 394, 393, 40, 398, 40, + 395, 40, 399, 397, 40, 40, 40, 40, 400, 401, + 396, 407, 402, 403, 406, 40, 409, 40, 40, 40, + 408, 404, 40, 40, 40, 40, 405, 40, 40, 411, + 40, 40, 40, 415, 412, 418, 417, 420, 416, 413, + 410, 40, 40, 40, 40, 419, 414, 40, 424, 40, + 40, 422, 40, 40, 421, 423, 427, 40, 40, 40, + + 425, 40, 431, 40, 40, 429, 40, 40, 430, 40, + 40, 40, 435, 428, 432, 436, 426, 40, 433, 439, + 40, 40, 40, 40, 434, 40, 440, 437, 40, 441, + 443, 40, 442, 40, 446, 40, 438, 40, 444, 40, + 445, 447, 40, 40, 449, 453, 40, 40, 448, 40, + 40, 450, 40, 40, 40, 40, 457, 40, 451, 40, + 452, 40, 40, 456, 40, 40, 455, 40, 40, 40, + 458, 454, 37, 37, 37, 37, 39, 39, 50, 40, + 50, 50, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, 40, 198, - 40, 40, 40, 40, 110, 40, 38, 453, 3, 453, - 453, 453, 453, 453, 453, 453, 453, 453, 453, 453, - 453, 453, 453, 453, 453, 453, 453, 453, 453, 453, - 453, 453, 453, 453, 453, 453, 453, 453, 453, 453, - 453, 453, 453, 453, 453, 453, 453, 453, 453, 453 + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 200, 40, 40, 40, 40, 111, 40, 38, 459, + 3, 459, 459, 459, 459, 459, 459, 459, 459, 459, + 459, 459, 459, 459, 459, 459, 459, 459, 459, 459, + 459, 459, 459, 459, 459, 459, 459, 459, 459, 459, + 459, 459, 459, 459, 459, 459, 459, 459, 459, 459, + + 459, 459 } ; -static yyconst short int yy_chk[991] = +static yyconst short int yy_chk[1003] = { 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 9, 159, 9, 9, 10, 10, 11, 11, 11, - 12, 26, 104, 12, 13, 13, 13, 13, 14, 14, - 14, 14, 159, 16, 104, 18, 51, 29, 17, 26, + 1, 9, 161, 9, 9, 10, 10, 11, 11, 11, + 12, 26, 105, 12, 13, 13, 13, 13, 14, 14, + 14, 14, 161, 16, 105, 18, 51, 29, 17, 26, 18, 16, 18, 20, 51, 26, 29, 17, 16, 19, - 16, 17, 16, 18, 13, 16, 17, 23, 19, 17, - 20, 21, 19, 22, 27, 108, 21, 19, 34, 28, + 16, 17, 16, 18, 13, 16, 17, 18, 19, 17, + 20, 21, 19, 22, 23, 27, 21, 19, 34, 63, + + 20, 35, 22, 28, 24, 464, 21, 34, 22, 24, + 23, 23, 21, 25, 27, 28, 27, 24, 25, 35, + 63, 28, 24, 31, 33, 36, 42, 42, 31, 33, + 52, 25, 43, 43, 36, 86, 46, 25, 30, 46, + 30, 31, 33, 52, 31, 52, 30, 66, 86, 30, + 56, 31, 30, 30, 44, 44, 44, 45, 45, 45, + 45, 56, 53, 30, 30, 57, 30, 32, 54, 32, + 53, 66, 47, 47, 47, 32, 57, 47, 48, 48, + 48, 48, 32, 47, 32, 84, 32, 54, 58, 55, + 84, 32, 49, 49, 49, 60, 49, 49, 62, 49, + + 49, 49, 49, 49, 49, 55, 58, 61, 65, 64, + 60, 67, 69, 62, 61, 62, 64, 60, 68, 67, + 70, 71, 72, 77, 73, 68, 76, 69, 64, 74, + 71, 75, 76, 65, 69, 79, 81, 82, 70, 80, + 77, 68, 73, 83, 78, 72, 77, 80, 74, 78, + 79, 81, 87, 75, 75, 88, 75, 89, 83, 90, + 82, 78, 91, 94, 93, 87, 96, 95, 92, 91, + 101, 88, 93, 95, 102, 97, 100, 91, 88, 96, + 99, 94, 103, 92, 89, 91, 92, 90, 97, 92, + 109, 102, 92, 99, 104, 100, 97, 107, 101, 462, + + 103, 106, 104, 108, 99, 106, 106, 104, 108, 110, + 107, 109, 107, 113, 113, 104, 114, 114, 106, 129, + 104, 114, 123, 116, 116, 116, 121, 114, 116, 120, + 110, 123, 117, 117, 116, 117, 117, 117, 125, 127, + 120, 128, 129, 132, 121, 131, 133, 134, 135, 141, + 139, 125, 137, 131, 127, 133, 128, 138, 137, 139, + 140, 142, 134, 135, 144, 132, 145, 143, 146, 140, + 138, 141, 143, 144, 146, 145, 147, 148, 149, 150, + 151, 140, 152, 153, 142, 154, 148, 149, 155, 151, + 156, 147, 157, 154, 160, 163, 152, 150, 172, 155, + + 167, 169, 175, 174, 458, 156, 153, 168, 456, 160, + 169, 175, 163, 174, 176, 178, 157, 166, 166, 172, + 181, 166, 166, 167, 166, 166, 166, 166, 166, 166, + 168, 170, 179, 180, 182, 176, 183, 184, 178, 181, + 170, 185, 170, 182, 180, 183, 170, 179, 170, 186, + 187, 188, 189, 191, 190, 193, 194, 192, 196, 187, + 184, 189, 192, 196, 185, 194, 186, 190, 188, 195, + 197, 191, 199, 216, 201, 201, 193, 195, 216, 201, + 203, 203, 206, 214, 197, 201, 208, 209, 202, 202, + 199, 202, 202, 204, 204, 204, 205, 205, 205, 206, + + 207, 213, 215, 208, 209, 217, 214, 207, 213, 218, + 219, 220, 221, 223, 222, 219, 224, 225, 217, 222, + 227, 228, 223, 224, 218, 215, 228, 229, 230, 231, + 220, 232, 233, 221, 234, 227, 229, 238, 235, 239, + 225, 241, 244, 242, 245, 232, 455, 233, 247, 230, + 231, 244, 234, 235, 239, 238, 246, 245, 248, 251, + 249, 250, 252, 246, 253, 241, 242, 248, 247, 249, + 250, 254, 252, 253, 258, 263, 257, 255, 261, 265, + 254, 248, 251, 249, 255, 257, 263, 261, 264, 258, + 266, 267, 265, 268, 269, 266, 270, 271, 264, 273, + + 275, 276, 276, 279, 278, 281, 284, 270, 267, 278, + 283, 279, 281, 275, 268, 269, 282, 283, 287, 285, + 286, 282, 273, 288, 271, 285, 289, 284, 296, 286, + 290, 292, 294, 295, 297, 287, 298, 290, 292, 301, + 299, 294, 302, 289, 296, 303, 288, 308, 295, 299, + 304, 302, 303, 298, 305, 306, 301, 297, 309, 304, + 317, 318, 320, 305, 306, 308, 321, 322, 326, 329, + 327, 318, 328, 330, 320, 317, 322, 327, 332, 334, + 328, 309, 333, 338, 330, 336, 339, 341, 340, 321, + 346, 326, 329, 339, 345, 333, 334, 340, 336, 345, + + 338, 332, 348, 350, 359, 351, 352, 360, 354, 341, + 362, 352, 350, 346, 351, 354, 363, 367, 348, 362, + 368, 373, 374, 375, 360, 359, 363, 376, 380, 381, + 367, 383, 368, 382, 384, 374, 373, 385, 381, 387, + 375, 389, 382, 380, 386, 390, 391, 393, 383, 384, + 376, 391, 385, 386, 390, 392, 393, 394, 395, 398, + 392, 387, 399, 400, 401, 404, 389, 405, 406, 395, + 407, 408, 413, 401, 398, 406, 405, 408, 404, 399, + 394, 410, 412, 414, 415, 407, 400, 416, 414, 417, + 418, 412, 419, 420, 410, 413, 417, 421, 422, 423, + + 415, 424, 421, 425, 427, 419, 426, 429, 420, 433, + 430, 431, 425, 418, 422, 426, 416, 434, 423, 430, + 432, 435, 437, 442, 424, 438, 431, 427, 440, 432, + 434, 441, 433, 443, 438, 444, 429, 446, 435, 445, + 437, 440, 447, 448, 442, 446, 450, 454, 441, 457, + 453, 443, 452, 451, 449, 439, 454, 436, 444, 428, + 445, 411, 409, 450, 403, 402, 448, 397, 396, 388, + 457, 447, 460, 460, 460, 460, 461, 461, 463, 379, + 463, 463, 378, 377, 372, 371, 370, 369, 366, 365, + 364, 361, 358, 357, 356, 355, 353, 349, 347, 344, + + 343, 342, 337, 335, 331, 325, 324, 323, 319, 316, + 315, 314, 313, 312, 311, 310, 307, 300, 293, 291, + 280, 277, 274, 272, 262, 260, 259, 256, 240, 237, + 236, 226, 212, 211, 210, 198, 177, 173, 171, 165, + 164, 162, 159, 158, 136, 130, 126, 124, 122, 119, + 115, 111, 98, 85, 59, 39, 37, 8, 7, 3, + 459, 459, 459, 459, 459, 459, 459, 459, 459, 459, + 459, 459, 459, 459, 459, 459, 459, 459, 459, 459, + 459, 459, 459, 459, 459, 459, 459, 459, 459, 459, + 459, 459, 459, 459, 459, 459, 459, 459, 459, 459, - 20, 64, 22, 23, 23, 24, 21, 34, 22, 25, - 24, 28, 21, 27, 25, 27, 108, 28, 24, 31, - 33, 35, 36, 24, 31, 33, 64, 25, 42, 42, - 55, 36, 46, 25, 30, 46, 30, 31, 33, 35, - 31, 458, 30, 43, 43, 30, 55, 31, 30, 30, - 44, 44, 44, 45, 45, 45, 45, 65, 53, 30, - 30, 56, 30, 32, 54, 32, 53, 58, 47, 47, - 47, 32, 56, 47, 48, 48, 48, 48, 32, 47, - 32, 65, 32, 54, 456, 58, 60, 32, 49, 49, - 49, 52, 49, 49, 57, 49, 49, 49, 49, 49, - - 49, 60, 61, 62, 52, 57, 52, 63, 60, 61, - 67, 66, 68, 69, 63, 70, 71, 67, 62, 66, - 62, 74, 72, 73, 70, 81, 63, 68, 76, 75, - 452, 69, 77, 67, 68, 75, 88, 77, 78, 71, - 72, 80, 73, 74, 74, 76, 74, 79, 81, 77, - 82, 76, 83, 78, 85, 79, 80, 83, 86, 87, - 89, 90, 91, 88, 92, 82, 450, 85, 90, 93, - 99, 86, 92, 94, 102, 87, 90, 91, 95, 94, - 91, 96, 87, 91, 90, 98, 91, 93, 89, 99, - 100, 95, 102, 101, 96, 103, 105, 130, 98, 106, - - 105, 105, 96, 103, 109, 130, 107, 449, 103, 98, - 101, 107, 106, 105, 106, 119, 103, 120, 100, 112, - 112, 103, 113, 113, 128, 109, 119, 113, 122, 115, - 115, 115, 124, 113, 115, 120, 126, 122, 116, 116, - 115, 116, 116, 116, 127, 124, 131, 128, 132, 133, - 135, 126, 136, 137, 139, 141, 135, 138, 140, 127, - 141, 142, 137, 132, 133, 136, 138, 144, 131, 145, - 142, 143, 148, 144, 146, 150, 139, 147, 138, 149, - 143, 140, 151, 146, 145, 152, 147, 153, 149, 150, - 148, 154, 155, 152, 158, 161, 165, 166, 153, 167, - - 177, 172, 201, 201, 173, 151, 154, 176, 167, 158, - 170, 172, 161, 173, 174, 177, 155, 164, 164, 165, - 166, 164, 164, 168, 164, 164, 164, 164, 164, 164, - 176, 170, 168, 178, 168, 174, 179, 180, 168, 181, - 168, 182, 183, 184, 178, 185, 180, 187, 181, 186, - 188, 189, 190, 191, 185, 179, 187, 190, 192, 197, - 184, 195, 193, 188, 182, 183, 186, 192, 194, 189, - 193, 199, 199, 194, 191, 195, 199, 197, 204, 206, - 200, 200, 199, 200, 200, 202, 202, 202, 203, 203, - 203, 205, 207, 211, 212, 204, 206, 213, 205, 214, - - 211, 215, 213, 216, 217, 218, 219, 221, 216, 207, - 220, 219, 214, 222, 221, 224, 215, 212, 226, 220, - 225, 227, 228, 217, 229, 225, 218, 226, 231, 230, - 224, 235, 232, 236, 238, 244, 222, 239, 229, 242, - 248, 241, 227, 228, 230, 281, 231, 232, 236, 235, - 241, 281, 242, 245, 243, 244, 246, 247, 238, 249, - 239, 243, 245, 248, 250, 246, 247, 252, 251, 249, - 255, 254, 258, 250, 252, 260, 245, 251, 261, 246, - 254, 258, 262, 264, 263, 255, 260, 265, 261, 263, - 266, 267, 268, 270, 272, 262, 273, 273, 275, 278, - - 264, 276, 267, 275, 280, 279, 278, 272, 265, 276, - 279, 266, 282, 283, 284, 285, 270, 286, 291, 268, - 288, 282, 290, 292, 286, 280, 293, 288, 294, 295, - 283, 290, 285, 291, 297, 298, 299, 284, 295, 292, - 304, 300, 305, 299, 298, 294, 301, 302, 313, 293, - 300, 297, 314, 317, 316, 301, 302, 322, 304, 318, - 323, 324, 314, 313, 325, 305, 316, 323, 318, 324, - 326, 328, 329, 330, 334, 332, 317, 335, 336, 340, - 322, 326, 341, 343, 340, 329, 335, 325, 332, 345, - 330, 334, 346, 354, 328, 355, 349, 347, 345, 343, - - 336, 346, 347, 349, 357, 341, 358, 362, 368, 363, - 370, 369, 355, 357, 354, 371, 358, 374, 377, 375, - 362, 363, 376, 368, 369, 378, 379, 370, 375, 381, - 380, 376, 374, 383, 384, 377, 387, 385, 371, 380, - 378, 379, 385, 384, 386, 387, 388, 392, 389, 386, - 393, 381, 394, 398, 395, 399, 401, 407, 383, 389, - 404, 400, 392, 395, 399, 406, 398, 393, 400, 388, - 402, 401, 408, 404, 406, 394, 402, 408, 409, 410, - 407, 411, 412, 413, 414, 415, 416, 417, 411, 418, - 415, 419, 420, 421, 409, 423, 413, 427, 424, 414, - - 419, 420, 416, 425, 426, 412, 417, 424, 410, 428, - 429, 431, 418, 426, 432, 434, 421, 435, 425, 436, - 427, 437, 428, 432, 423, 438, 439, 429, 434, 431, - 440, 441, 442, 444, 435, 448, 451, 447, 440, 437, - 436, 446, 445, 443, 448, 433, 430, 439, 438, 422, - 444, 405, 403, 397, 396, 442, 391, 451, 390, 382, - 441, 454, 454, 454, 454, 455, 455, 457, 373, 457, - 457, 372, 367, 366, 365, 364, 361, 360, 359, 356, - 353, 352, 351, 350, 348, 344, 342, 339, 338, 337, - 333, 331, 327, 321, 320, 319, 315, 312, 311, 310, - - 309, 308, 307, 306, 303, 296, 289, 287, 277, 274, - 271, 269, 259, 257, 256, 253, 237, 234, 233, 223, - 210, 209, 208, 196, 175, 171, 169, 163, 162, 160, - 157, 156, 134, 129, 125, 123, 121, 118, 114, 110, - 97, 84, 59, 39, 37, 8, 7, 3, 453, 453, - 453, 453, 453, 453, 453, 453, 453, 453, 453, 453, - 453, 453, 453, 453, 453, 453, 453, 453, 453, 453, - 453, 453, 453, 453, 453, 453, 453, 453, 453, 453, - 453, 453, 453, 453, 453, 453, 453, 453, 453, 453 + 459, 459 } ; static yy_state_type yy_state_buf[YY_BUF_SIZE + 2], *yy_state_ptr; @@ -916,7 +924,7 @@ /* HexIntConstant - Hexadecimal constant generated by the CFE to avoid forcing * it to deal with 64 bit numbers. */ -#line 920 "Lexer.cpp" +#line 928 "Lexer.cpp" /* Macros after this point can all be overridden by user definitions in * section 1. @@ -1070,7 +1078,7 @@ #line 179 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -#line 1074 "Lexer.cpp" +#line 1082 "Lexer.cpp" if ( yy_init ) { @@ -1118,14 +1126,14 @@ while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 454 ) + if ( yy_current_state >= 460 ) yy_c = yy_meta[(unsigned int) yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c]; *yy_state_ptr++ = yy_current_state; ++yy_cp; } - while ( yy_current_state != 453 ); + while ( yy_current_state != 459 ); yy_find_action: yy_current_state = *--yy_state_ptr; @@ -1354,290 +1362,295 @@ case 39: YY_RULE_SETUP #line 221 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ return FASTCC_TOK; } +{ return CSRETCC_TOK; } YY_BREAK case 40: YY_RULE_SETUP #line 222 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ return COLDCC_TOK; } +{ return FASTCC_TOK; } YY_BREAK case 41: YY_RULE_SETUP -#line 224 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ llvmAsmlval.PrimType = Type::VoidTy ; return VOID; } +#line 223 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" +{ return COLDCC_TOK; } YY_BREAK case 42: YY_RULE_SETUP #line 225 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ llvmAsmlval.PrimType = Type::BoolTy ; return BOOL; } +{ llvmAsmlval.PrimType = Type::VoidTy ; return VOID; } YY_BREAK case 43: YY_RULE_SETUP #line 226 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ llvmAsmlval.PrimType = Type::SByteTy ; return SBYTE; } +{ llvmAsmlval.PrimType = Type::BoolTy ; return BOOL; } YY_BREAK case 44: YY_RULE_SETUP #line 227 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ llvmAsmlval.PrimType = Type::UByteTy ; return UBYTE; } +{ llvmAsmlval.PrimType = Type::SByteTy ; return SBYTE; } YY_BREAK case 45: YY_RULE_SETUP #line 228 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ llvmAsmlval.PrimType = Type::ShortTy ; return SHORT; } +{ llvmAsmlval.PrimType = Type::UByteTy ; return UBYTE; } YY_BREAK case 46: YY_RULE_SETUP #line 229 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ llvmAsmlval.PrimType = Type::UShortTy; return USHORT; } +{ llvmAsmlval.PrimType = Type::ShortTy ; return SHORT; } YY_BREAK case 47: YY_RULE_SETUP #line 230 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ llvmAsmlval.PrimType = Type::IntTy ; return INT; } +{ llvmAsmlval.PrimType = Type::UShortTy; return USHORT; } YY_BREAK case 48: YY_RULE_SETUP #line 231 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ llvmAsmlval.PrimType = Type::UIntTy ; return UINT; } +{ llvmAsmlval.PrimType = Type::IntTy ; return INT; } YY_BREAK case 49: YY_RULE_SETUP #line 232 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ llvmAsmlval.PrimType = Type::LongTy ; return LONG; } +{ llvmAsmlval.PrimType = Type::UIntTy ; return UINT; } YY_BREAK case 50: YY_RULE_SETUP #line 233 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ llvmAsmlval.PrimType = Type::ULongTy ; return ULONG; } +{ llvmAsmlval.PrimType = Type::LongTy ; return LONG; } YY_BREAK case 51: YY_RULE_SETUP #line 234 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ llvmAsmlval.PrimType = Type::FloatTy ; return FLOAT; } +{ llvmAsmlval.PrimType = Type::ULongTy ; return ULONG; } YY_BREAK case 52: YY_RULE_SETUP #line 235 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ llvmAsmlval.PrimType = Type::DoubleTy; return DOUBLE; } +{ llvmAsmlval.PrimType = Type::FloatTy ; return FLOAT; } YY_BREAK case 53: YY_RULE_SETUP #line 236 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ llvmAsmlval.PrimType = Type::LabelTy ; return LABEL; } +{ llvmAsmlval.PrimType = Type::DoubleTy; return DOUBLE; } YY_BREAK case 54: YY_RULE_SETUP #line 237 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ return TYPE; } +{ llvmAsmlval.PrimType = Type::LabelTy ; return LABEL; } YY_BREAK case 55: YY_RULE_SETUP #line 238 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ return OPAQUE; } +{ return TYPE; } YY_BREAK case 56: YY_RULE_SETUP -#line 240 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ RET_TOK(BinaryOpVal, Add, ADD); } +#line 239 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" +{ return OPAQUE; } YY_BREAK case 57: YY_RULE_SETUP #line 241 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ RET_TOK(BinaryOpVal, Sub, SUB); } +{ RET_TOK(BinaryOpVal, Add, ADD); } YY_BREAK case 58: YY_RULE_SETUP #line 242 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ RET_TOK(BinaryOpVal, Mul, MUL); } +{ RET_TOK(BinaryOpVal, Sub, SUB); } YY_BREAK case 59: YY_RULE_SETUP #line 243 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ RET_TOK(BinaryOpVal, Div, DIV); } +{ RET_TOK(BinaryOpVal, Mul, MUL); } YY_BREAK case 60: YY_RULE_SETUP #line 244 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ RET_TOK(BinaryOpVal, Rem, REM); } +{ RET_TOK(BinaryOpVal, Div, DIV); } YY_BREAK case 61: YY_RULE_SETUP #line 245 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ RET_TOK(BinaryOpVal, And, AND); } +{ RET_TOK(BinaryOpVal, Rem, REM); } YY_BREAK case 62: YY_RULE_SETUP #line 246 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ RET_TOK(BinaryOpVal, Or , OR ); } +{ RET_TOK(BinaryOpVal, And, AND); } YY_BREAK case 63: YY_RULE_SETUP #line 247 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ RET_TOK(BinaryOpVal, Xor, XOR); } +{ RET_TOK(BinaryOpVal, Or , OR ); } YY_BREAK case 64: YY_RULE_SETUP #line 248 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ RET_TOK(BinaryOpVal, SetNE, SETNE); } +{ RET_TOK(BinaryOpVal, Xor, XOR); } YY_BREAK case 65: YY_RULE_SETUP #line 249 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ RET_TOK(BinaryOpVal, SetEQ, SETEQ); } +{ RET_TOK(BinaryOpVal, SetNE, SETNE); } YY_BREAK case 66: YY_RULE_SETUP #line 250 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ RET_TOK(BinaryOpVal, SetLT, SETLT); } +{ RET_TOK(BinaryOpVal, SetEQ, SETEQ); } YY_BREAK case 67: YY_RULE_SETUP #line 251 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ RET_TOK(BinaryOpVal, SetGT, SETGT); } +{ RET_TOK(BinaryOpVal, SetLT, SETLT); } YY_BREAK case 68: YY_RULE_SETUP #line 252 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ RET_TOK(BinaryOpVal, SetLE, SETLE); } +{ RET_TOK(BinaryOpVal, SetGT, SETGT); } YY_BREAK case 69: YY_RULE_SETUP #line 253 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ RET_TOK(BinaryOpVal, SetGE, SETGE); } +{ RET_TOK(BinaryOpVal, SetLE, SETLE); } YY_BREAK case 70: YY_RULE_SETUP -#line 255 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ RET_TOK(OtherOpVal, PHI, PHI_TOK); } +#line 254 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" +{ RET_TOK(BinaryOpVal, SetGE, SETGE); } YY_BREAK case 71: YY_RULE_SETUP #line 256 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ RET_TOK(OtherOpVal, Call, CALL); } +{ RET_TOK(OtherOpVal, PHI, PHI_TOK); } YY_BREAK case 72: YY_RULE_SETUP #line 257 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ RET_TOK(OtherOpVal, Cast, CAST); } +{ RET_TOK(OtherOpVal, Call, CALL); } YY_BREAK case 73: YY_RULE_SETUP #line 258 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ RET_TOK(OtherOpVal, Select, SELECT); } +{ RET_TOK(OtherOpVal, Cast, CAST); } YY_BREAK case 74: YY_RULE_SETUP #line 259 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ RET_TOK(OtherOpVal, Shl, SHL); } +{ RET_TOK(OtherOpVal, Select, SELECT); } YY_BREAK case 75: YY_RULE_SETUP #line 260 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ RET_TOK(OtherOpVal, Shr, SHR); } +{ RET_TOK(OtherOpVal, Shl, SHL); } YY_BREAK case 76: YY_RULE_SETUP #line 261 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ return VANEXT_old; } +{ RET_TOK(OtherOpVal, Shr, SHR); } YY_BREAK case 77: YY_RULE_SETUP #line 262 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ return VAARG_old; } +{ return VANEXT_old; } YY_BREAK case 78: YY_RULE_SETUP #line 263 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ RET_TOK(OtherOpVal, VAArg , VAARG); } +{ return VAARG_old; } YY_BREAK case 79: YY_RULE_SETUP #line 264 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ RET_TOK(TermOpVal, Ret, RET); } +{ RET_TOK(OtherOpVal, VAArg , VAARG); } YY_BREAK case 80: YY_RULE_SETUP #line 265 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ RET_TOK(TermOpVal, Br, BR); } +{ RET_TOK(TermOpVal, Ret, RET); } YY_BREAK case 81: YY_RULE_SETUP #line 266 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ RET_TOK(TermOpVal, Switch, SWITCH); } +{ RET_TOK(TermOpVal, Br, BR); } YY_BREAK case 82: YY_RULE_SETUP #line 267 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ RET_TOK(TermOpVal, Invoke, INVOKE); } +{ RET_TOK(TermOpVal, Switch, SWITCH); } YY_BREAK case 83: YY_RULE_SETUP #line 268 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ RET_TOK(TermOpVal, Unwind, UNWIND); } +{ RET_TOK(TermOpVal, Invoke, INVOKE); } YY_BREAK case 84: YY_RULE_SETUP #line 269 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ RET_TOK(TermOpVal, Unreachable, UNREACHABLE); } +{ RET_TOK(TermOpVal, Unwind, UNWIND); } YY_BREAK case 85: YY_RULE_SETUP -#line 271 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ RET_TOK(MemOpVal, Malloc, MALLOC); } +#line 270 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" +{ RET_TOK(TermOpVal, Unreachable, UNREACHABLE); } YY_BREAK case 86: YY_RULE_SETUP #line 272 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ RET_TOK(MemOpVal, Alloca, ALLOCA); } +{ RET_TOK(MemOpVal, Malloc, MALLOC); } YY_BREAK case 87: YY_RULE_SETUP #line 273 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ RET_TOK(MemOpVal, Free, FREE); } +{ RET_TOK(MemOpVal, Alloca, ALLOCA); } YY_BREAK case 88: YY_RULE_SETUP #line 274 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ RET_TOK(MemOpVal, Load, LOAD); } +{ RET_TOK(MemOpVal, Free, FREE); } YY_BREAK case 89: YY_RULE_SETUP #line 275 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ RET_TOK(MemOpVal, Store, STORE); } +{ RET_TOK(MemOpVal, Load, LOAD); } YY_BREAK case 90: YY_RULE_SETUP #line 276 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ RET_TOK(MemOpVal, GetElementPtr, GETELEMENTPTR); } +{ RET_TOK(MemOpVal, Store, STORE); } YY_BREAK case 91: YY_RULE_SETUP -#line 278 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ RET_TOK(OtherOpVal, ExtractElement, EXTRACTELEMENT); } +#line 277 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" +{ RET_TOK(MemOpVal, GetElementPtr, GETELEMENTPTR); } YY_BREAK case 92: YY_RULE_SETUP #line 279 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ RET_TOK(OtherOpVal, InsertElement, INSERTELEMENT); } +{ RET_TOK(OtherOpVal, ExtractElement, EXTRACTELEMENT); } YY_BREAK case 93: YY_RULE_SETUP #line 280 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" -{ RET_TOK(OtherOpVal, ShuffleVector, SHUFFLEVECTOR); } +{ RET_TOK(OtherOpVal, InsertElement, INSERTELEMENT); } YY_BREAK case 94: YY_RULE_SETUP -#line 283 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" +#line 281 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" +{ RET_TOK(OtherOpVal, ShuffleVector, SHUFFLEVECTOR); } + YY_BREAK +case 95: +YY_RULE_SETUP +#line 284 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { UnEscapeLexed(yytext+1); llvmAsmlval.StrVal = strdup(yytext+1); // Skip % return VAR_ID; } YY_BREAK -case 95: +case 96: YY_RULE_SETUP -#line 288 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" +#line 289 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { yytext[strlen(yytext)-1] = 0; // nuke colon UnEscapeLexed(yytext); @@ -1645,9 +1658,9 @@ return LABELSTR; } YY_BREAK -case 96: +case 97: YY_RULE_SETUP -#line 294 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" +#line 295 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { yytext[strlen(yytext)-2] = 0; // nuke colon, end quote UnEscapeLexed(yytext+1); @@ -1655,9 +1668,9 @@ return LABELSTR; } YY_BREAK -case 97: +case 98: YY_RULE_SETUP -#line 301 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" +#line 302 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { // Note that we cannot unescape a string constant here! The // string constant might contain a \00 which would not be // understood by the string stuff. It is valid to make a @@ -1668,14 +1681,14 @@ return STRINGCONSTANT; } YY_BREAK -case 98: +case 99: YY_RULE_SETUP -#line 312 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" +#line 313 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { llvmAsmlval.UInt64Val = atoull(yytext); return EUINT64VAL; } YY_BREAK -case 99: +case 100: YY_RULE_SETUP -#line 313 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" +#line 314 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { uint64_t Val = atoull(yytext+1); // +1: we have bigger negative range @@ -1685,17 +1698,17 @@ return ESINT64VAL; } YY_BREAK -case 100: +case 101: YY_RULE_SETUP -#line 321 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" +#line 322 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { llvmAsmlval.UInt64Val = HexIntToVal(yytext+3); return yytext[0] == 's' ? ESINT64VAL : EUINT64VAL; } YY_BREAK -case 101: +case 102: YY_RULE_SETUP -#line 326 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" +#line 327 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { uint64_t Val = atoull(yytext+1); if ((unsigned)Val != Val) @@ -1704,9 +1717,9 @@ return UINTVAL; } YY_BREAK -case 102: +case 103: YY_RULE_SETUP -#line 333 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" +#line 334 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { uint64_t Val = atoull(yytext+2); // +1: we have bigger negative range @@ -1716,18 +1729,18 @@ return SINTVAL; } YY_BREAK -case 103: +case 104: YY_RULE_SETUP -#line 342 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" +#line 343 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { llvmAsmlval.FPVal = atof(yytext); return FPVAL; } YY_BREAK -case 104: +case 105: YY_RULE_SETUP -#line 343 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" +#line 344 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { llvmAsmlval.FPVal = HexToFP(yytext); return FPVAL; } YY_BREAK case YY_STATE_EOF(INITIAL): -#line 345 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" +#line 346 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { /* Make sure to free the internal buffers for flex when we are * done reading our input! @@ -1736,22 +1749,22 @@ return EOF; } YY_BREAK -case 105: +case 106: YY_RULE_SETUP -#line 353 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" +#line 354 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { /* Ignore whitespace */ } YY_BREAK -case 106: +case 107: YY_RULE_SETUP -#line 354 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" +#line 355 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" { return yytext[0]; } YY_BREAK -case 107: +case 108: YY_RULE_SETUP -#line 356 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" +#line 357 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" YY_FATAL_ERROR( "flex scanner jammed" ); YY_BREAK -#line 1755 "Lexer.cpp" +#line 1768 "Lexer.cpp" case YY_END_OF_BUFFER: { @@ -2038,7 +2051,7 @@ while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 454 ) + if ( yy_current_state >= 460 ) yy_c = yy_meta[(unsigned int) yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c]; @@ -2068,11 +2081,11 @@ while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 454 ) + if ( yy_current_state >= 460 ) yy_c = yy_meta[(unsigned int) yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c]; - yy_is_jam = (yy_current_state == 453); + yy_is_jam = (yy_current_state == 459); if ( ! yy_is_jam ) *yy_state_ptr++ = yy_current_state; @@ -2173,7 +2186,7 @@ case EOB_ACT_END_OF_FILE: { if ( yywrap() ) - return EOF; + return 0; if ( ! yy_did_buffer_switch_on_eof ) YY_NEW_FILE; @@ -2633,6 +2646,6 @@ return 0; } #endif -#line 356 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" +#line 357 "/Volumes/Projects/cvs/llvm/lib/AsmParser/Lexer.l" Index: llvm/lib/AsmParser/Lexer.l.cvs diff -u llvm/lib/AsmParser/Lexer.l.cvs:1.3 llvm/lib/AsmParser/Lexer.l.cvs:1.4 --- llvm/lib/AsmParser/Lexer.l.cvs:1.3 Fri Apr 7 20:18:56 2006 +++ llvm/lib/AsmParser/Lexer.l.cvs Fri May 19 16:28:53 2006 @@ -218,6 +218,7 @@ cc { return CC_TOK; } ccc { return CCC_TOK; } +csretcc { return CSRETCC_TOK; } fastcc { return FASTCC_TOK; } coldcc { return COLDCC_TOK; } Index: llvm/lib/AsmParser/llvmAsmParser.cpp.cvs diff -u llvm/lib/AsmParser/llvmAsmParser.cpp.cvs:1.5 llvm/lib/AsmParser/llvmAsmParser.cpp.cvs:1.6 --- llvm/lib/AsmParser/llvmAsmParser.cpp.cvs:1.5 Fri Apr 7 23:09:02 2006 +++ llvm/lib/AsmParser/llvmAsmParser.cpp.cvs Fri May 19 16:28:53 2006 @@ -1,5 +1,5 @@ -/* A Bison parser, made from /Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y +/* A Bison parser, made from /Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y by GNU Bison version 1.28 */ #define YYBISON 1 /* Identify Bison output. */ @@ -71,47 +71,48 @@ #define SIDEEFFECT 314 #define CC_TOK 315 #define CCC_TOK 316 -#define FASTCC_TOK 317 -#define COLDCC_TOK 318 -#define RET 319 -#define BR 320 -#define SWITCH 321 -#define INVOKE 322 -#define UNWIND 323 -#define UNREACHABLE 324 -#define ADD 325 -#define SUB 326 -#define MUL 327 -#define DIV 328 -#define REM 329 -#define AND 330 -#define OR 331 -#define XOR 332 -#define SETLE 333 -#define SETGE 334 -#define SETLT 335 -#define SETGT 336 -#define SETEQ 337 -#define SETNE 338 -#define MALLOC 339 -#define ALLOCA 340 -#define FREE 341 -#define LOAD 342 -#define STORE 343 -#define GETELEMENTPTR 344 -#define PHI_TOK 345 -#define CAST 346 -#define SELECT 347 -#define SHL 348 -#define SHR 349 -#define VAARG 350 -#define EXTRACTELEMENT 351 -#define INSERTELEMENT 352 -#define SHUFFLEVECTOR 353 -#define VAARG_old 354 -#define VANEXT_old 355 +#define CSRETCC_TOK 317 +#define FASTCC_TOK 318 +#define COLDCC_TOK 319 +#define RET 320 +#define BR 321 +#define SWITCH 322 +#define INVOKE 323 +#define UNWIND 324 +#define UNREACHABLE 325 +#define ADD 326 +#define SUB 327 +#define MUL 328 +#define DIV 329 +#define REM 330 +#define AND 331 +#define OR 332 +#define XOR 333 +#define SETLE 334 +#define SETGE 335 +#define SETLT 336 +#define SETGT 337 +#define SETEQ 338 +#define SETNE 339 +#define MALLOC 340 +#define ALLOCA 341 +#define FREE 342 +#define LOAD 343 +#define STORE 344 +#define GETELEMENTPTR 345 +#define PHI_TOK 346 +#define CAST 347 +#define SELECT 348 +#define SHL 349 +#define SHR 350 +#define VAARG 351 +#define EXTRACTELEMENT 352 +#define INSERTELEMENT 353 +#define SHUFFLEVECTOR 354 +#define VAARG_old 355 +#define VANEXT_old 356 -#line 14 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 14 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" #include "ParserInternals.h" #include "llvm/CallingConv.h" @@ -987,7 +988,7 @@ } -#line 890 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 890 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" typedef union { llvm::Module *ModuleVal; llvm::Function *FunctionVal; @@ -1037,26 +1038,26 @@ -#define YYFINAL 495 +#define YYFINAL 496 #define YYFLAG -32768 -#define YYNTBASE 116 +#define YYNTBASE 117 -#define YYTRANSLATE(x) ((unsigned)(x) <= 355 ? yytranslate[x] : 187) +#define YYTRANSLATE(x) ((unsigned)(x) <= 356 ? yytranslate[x] : 188) static const char yytranslate[] = { 0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, - 2, 2, 2, 2, 2, 2, 2, 2, 2, 105, - 106, 114, 2, 103, 2, 2, 2, 2, 2, 2, - 2, 2, 2, 2, 2, 2, 2, 2, 2, 110, - 102, 111, 2, 2, 2, 2, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 2, 2, 2, 2, 106, + 107, 115, 2, 104, 2, 2, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 2, 2, 2, 2, 111, + 103, 112, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, - 107, 104, 109, 2, 2, 2, 2, 2, 115, 2, + 108, 105, 110, 2, 2, 2, 2, 2, 116, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, - 2, 2, 2, 2, 2, 2, 2, 2, 2, 108, - 2, 2, 112, 2, 113, 2, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 2, 2, 2, 2, 109, + 2, 2, 113, 2, 114, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, @@ -1079,7 +1080,7 @@ 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, - 97, 98, 99, 100, 101 + 97, 98, 99, 100, 101, 102 }; #if YYDEBUG != 0 @@ -1088,107 +1089,107 @@ 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 67, 68, 70, 72, 74, 76, 77, - 78, 80, 82, 84, 87, 88, 91, 92, 96, 99, - 100, 102, 103, 107, 109, 112, 114, 116, 118, 120, + 78, 80, 82, 84, 86, 89, 90, 93, 94, 98, + 101, 102, 104, 105, 109, 111, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, - 142, 144, 146, 148, 150, 152, 154, 157, 162, 168, - 174, 178, 181, 184, 186, 190, 192, 196, 198, 199, - 204, 208, 212, 217, 222, 226, 229, 232, 235, 238, - 241, 244, 247, 250, 253, 256, 263, 269, 278, 285, - 292, 299, 306, 313, 322, 331, 335, 337, 339, 341, - 343, 346, 349, 354, 357, 359, 364, 367, 372, 373, - 381, 382, 390, 394, 399, 400, 402, 404, 406, 410, - 414, 418, 422, 426, 428, 429, 431, 433, 435, 436, - 439, 443, 445, 447, 451, 453, 454, 463, 465, 467, - 471, 473, 475, 478, 479, 483, 484, 486, 488, 490, - 492, 494, 496, 498, 500, 502, 506, 508, 514, 516, - 518, 520, 522, 525, 528, 531, 535, 538, 539, 541, - 544, 547, 551, 561, 571, 580, 594, 596, 598, 605, - 611, 614, 621, 629, 631, 635, 637, 638, 641, 643, - 649, 655, 661, 664, 669, 674, 681, 686, 691, 696, - 701, 708, 715, 718, 726, 728, 731, 732, 734, 735, - 739, 746, 750, 757, 760, 765, 772 + 142, 144, 146, 148, 150, 152, 154, 156, 159, 164, + 170, 176, 180, 183, 186, 188, 192, 194, 198, 200, + 201, 206, 210, 214, 219, 224, 228, 231, 234, 237, + 240, 243, 246, 249, 252, 255, 258, 265, 271, 280, + 287, 294, 301, 308, 315, 324, 333, 337, 339, 341, + 343, 345, 348, 351, 356, 359, 361, 366, 369, 374, + 375, 383, 384, 392, 396, 401, 402, 404, 406, 408, + 412, 416, 420, 424, 428, 430, 431, 433, 435, 437, + 438, 441, 445, 447, 449, 453, 455, 456, 465, 467, + 469, 473, 475, 477, 480, 481, 485, 486, 488, 490, + 492, 494, 496, 498, 500, 502, 504, 508, 510, 516, + 518, 520, 522, 524, 527, 530, 533, 537, 540, 541, + 543, 546, 549, 553, 563, 573, 582, 596, 598, 600, + 607, 613, 616, 623, 631, 633, 637, 639, 640, 643, + 645, 651, 657, 663, 666, 671, 676, 683, 688, 693, + 698, 703, 710, 717, 720, 728, 730, 733, 734, 736, + 737, 741, 748, 752, 759, 762, 767, 774 }; static const short yyrhs[] = { 5, - 0, 6, 0, 3, 0, 4, 0, 71, 0, 72, - 0, 73, 0, 74, 0, 75, 0, 76, 0, 77, - 0, 78, 0, 79, 0, 80, 0, 81, 0, 82, - 0, 83, 0, 84, 0, 94, 0, 95, 0, 16, + 0, 6, 0, 3, 0, 4, 0, 72, 0, 73, + 0, 74, 0, 75, 0, 76, 0, 77, 0, 78, + 0, 79, 0, 80, 0, 81, 0, 82, 0, 83, + 0, 84, 0, 85, 0, 95, 0, 96, 0, 16, 0, 14, 0, 12, 0, 10, 0, 17, 0, 15, - 0, 13, 0, 11, 0, 122, 0, 123, 0, 18, - 0, 19, 0, 156, 102, 0, 0, 41, 0, 42, + 0, 13, 0, 11, 0, 123, 0, 124, 0, 18, + 0, 19, 0, 157, 103, 0, 0, 41, 0, 42, 0, 43, 0, 44, 0, 0, 0, 62, 0, 63, - 0, 64, 0, 61, 4, 0, 0, 54, 4, 0, - 0, 103, 54, 4, 0, 34, 24, 0, 0, 131, - 0, 0, 103, 134, 133, 0, 131, 0, 54, 4, - 0, 137, 0, 8, 0, 139, 0, 8, 0, 139, - 0, 9, 0, 10, 0, 11, 0, 12, 0, 13, - 0, 14, 0, 15, 0, 16, 0, 17, 0, 18, - 0, 19, 0, 20, 0, 21, 0, 45, 0, 138, - 0, 170, 0, 104, 4, 0, 136, 105, 141, 106, - 0, 107, 4, 108, 139, 109, 0, 110, 4, 108, - 139, 111, 0, 112, 140, 113, 0, 112, 113, 0, - 139, 114, 0, 139, 0, 140, 103, 139, 0, 140, - 0, 140, 103, 37, 0, 37, 0, 0, 137, 107, - 144, 109, 0, 137, 107, 109, 0, 137, 115, 24, - 0, 137, 110, 144, 111, 0, 137, 112, 144, 113, - 0, 137, 112, 113, 0, 137, 38, 0, 137, 39, - 0, 137, 170, 0, 137, 143, 0, 137, 26, 0, - 122, 117, 0, 123, 4, 0, 9, 27, 0, 9, - 28, 0, 125, 7, 0, 92, 105, 142, 36, 137, - 106, 0, 90, 105, 142, 184, 106, 0, 93, 105, - 142, 103, 142, 103, 142, 106, 0, 118, 105, 142, - 103, 142, 106, 0, 119, 105, 142, 103, 142, 106, - 0, 120, 105, 142, 103, 142, 106, 0, 121, 105, - 142, 103, 142, 106, 0, 97, 105, 142, 103, 142, - 106, 0, 98, 105, 142, 103, 142, 103, 142, 106, - 0, 99, 105, 142, 103, 142, 103, 142, 106, 0, - 144, 103, 142, 0, 142, 0, 32, 0, 33, 0, - 147, 0, 147, 165, 0, 147, 166, 0, 147, 59, - 58, 151, 0, 147, 25, 0, 148, 0, 148, 126, - 20, 135, 0, 148, 166, 0, 148, 59, 58, 151, - 0, 0, 148, 126, 127, 145, 142, 149, 133, 0, - 0, 148, 126, 47, 145, 137, 150, 133, 0, 148, - 48, 153, 0, 148, 55, 102, 154, 0, 0, 24, - 0, 53, 0, 52, 0, 50, 102, 152, 0, 51, - 102, 4, 0, 49, 102, 24, 0, 107, 155, 109, - 0, 155, 103, 24, 0, 24, 0, 0, 22, 0, - 24, 0, 156, 0, 0, 137, 157, 0, 159, 103, - 158, 0, 158, 0, 159, 0, 159, 103, 37, 0, - 37, 0, 0, 128, 135, 156, 105, 160, 106, 132, - 129, 0, 29, 0, 112, 0, 127, 161, 162, 0, - 30, 0, 113, 0, 173, 164, 0, 0, 31, 167, - 161, 0, 0, 60, 0, 3, 0, 4, 0, 7, - 0, 27, 0, 28, 0, 38, 0, 39, 0, 26, - 0, 110, 144, 111, 0, 143, 0, 58, 168, 24, - 103, 24, 0, 116, 0, 156, 0, 170, 0, 169, - 0, 137, 171, 0, 173, 174, 0, 163, 174, 0, - 175, 126, 176, 0, 175, 178, 0, 0, 23, 0, - 65, 172, 0, 65, 8, 0, 66, 21, 171, 0, - 66, 9, 171, 103, 21, 171, 103, 21, 171, 0, - 67, 124, 171, 103, 21, 171, 107, 177, 109, 0, - 67, 124, 171, 103, 21, 171, 107, 109, 0, 68, - 128, 135, 171, 105, 181, 106, 36, 21, 171, 69, - 21, 171, 0, 69, 0, 70, 0, 177, 124, 169, - 103, 21, 171, 0, 124, 169, 103, 21, 171, 0, - 126, 183, 0, 137, 107, 171, 103, 171, 109, 0, - 179, 103, 107, 171, 103, 171, 109, 0, 172, 0, - 180, 103, 172, 0, 180, 0, 0, 57, 56, 0, - 56, 0, 118, 137, 171, 103, 171, 0, 119, 137, - 171, 103, 171, 0, 120, 137, 171, 103, 171, 0, - 46, 172, 0, 121, 172, 103, 172, 0, 92, 172, - 36, 137, 0, 93, 172, 103, 172, 103, 172, 0, - 96, 172, 103, 137, 0, 100, 172, 103, 137, 0, - 101, 172, 103, 137, 0, 97, 172, 103, 172, 0, - 98, 172, 103, 172, 103, 172, 0, 99, 172, 103, - 172, 103, 172, 0, 91, 179, 0, 182, 128, 135, - 171, 105, 181, 106, 0, 186, 0, 103, 180, 0, - 0, 35, 0, 0, 85, 137, 130, 0, 85, 137, - 103, 15, 171, 130, 0, 86, 137, 130, 0, 86, - 137, 103, 15, 171, 130, 0, 87, 172, 0, 185, - 88, 137, 171, 0, 185, 89, 172, 103, 137, 171, - 0, 90, 137, 171, 184, 0 + 0, 64, 0, 65, 0, 61, 4, 0, 0, 54, + 4, 0, 0, 104, 54, 4, 0, 34, 24, 0, + 0, 132, 0, 0, 104, 135, 134, 0, 132, 0, + 54, 4, 0, 138, 0, 8, 0, 140, 0, 8, + 0, 140, 0, 9, 0, 10, 0, 11, 0, 12, + 0, 13, 0, 14, 0, 15, 0, 16, 0, 17, + 0, 18, 0, 19, 0, 20, 0, 21, 0, 45, + 0, 139, 0, 171, 0, 105, 4, 0, 137, 106, + 142, 107, 0, 108, 4, 109, 140, 110, 0, 111, + 4, 109, 140, 112, 0, 113, 141, 114, 0, 113, + 114, 0, 140, 115, 0, 140, 0, 141, 104, 140, + 0, 141, 0, 141, 104, 37, 0, 37, 0, 0, + 138, 108, 145, 110, 0, 138, 108, 110, 0, 138, + 116, 24, 0, 138, 111, 145, 112, 0, 138, 113, + 145, 114, 0, 138, 113, 114, 0, 138, 38, 0, + 138, 39, 0, 138, 171, 0, 138, 144, 0, 138, + 26, 0, 123, 118, 0, 124, 4, 0, 9, 27, + 0, 9, 28, 0, 126, 7, 0, 93, 106, 143, + 36, 138, 107, 0, 91, 106, 143, 185, 107, 0, + 94, 106, 143, 104, 143, 104, 143, 107, 0, 119, + 106, 143, 104, 143, 107, 0, 120, 106, 143, 104, + 143, 107, 0, 121, 106, 143, 104, 143, 107, 0, + 122, 106, 143, 104, 143, 107, 0, 98, 106, 143, + 104, 143, 107, 0, 99, 106, 143, 104, 143, 104, + 143, 107, 0, 100, 106, 143, 104, 143, 104, 143, + 107, 0, 145, 104, 143, 0, 143, 0, 32, 0, + 33, 0, 148, 0, 148, 166, 0, 148, 167, 0, + 148, 59, 58, 152, 0, 148, 25, 0, 149, 0, + 149, 127, 20, 136, 0, 149, 167, 0, 149, 59, + 58, 152, 0, 0, 149, 127, 128, 146, 143, 150, + 134, 0, 0, 149, 127, 47, 146, 138, 151, 134, + 0, 149, 48, 154, 0, 149, 55, 103, 155, 0, + 0, 24, 0, 53, 0, 52, 0, 50, 103, 153, + 0, 51, 103, 4, 0, 49, 103, 24, 0, 108, + 156, 110, 0, 156, 104, 24, 0, 24, 0, 0, + 22, 0, 24, 0, 157, 0, 0, 138, 158, 0, + 160, 104, 159, 0, 159, 0, 160, 0, 160, 104, + 37, 0, 37, 0, 0, 129, 136, 157, 106, 161, + 107, 133, 130, 0, 29, 0, 113, 0, 128, 162, + 163, 0, 30, 0, 114, 0, 174, 165, 0, 0, + 31, 168, 162, 0, 0, 60, 0, 3, 0, 4, + 0, 7, 0, 27, 0, 28, 0, 38, 0, 39, + 0, 26, 0, 111, 145, 112, 0, 144, 0, 58, + 169, 24, 104, 24, 0, 117, 0, 157, 0, 171, + 0, 170, 0, 138, 172, 0, 174, 175, 0, 164, + 175, 0, 176, 127, 177, 0, 176, 179, 0, 0, + 23, 0, 66, 173, 0, 66, 8, 0, 67, 21, + 172, 0, 67, 9, 172, 104, 21, 172, 104, 21, + 172, 0, 68, 125, 172, 104, 21, 172, 108, 178, + 110, 0, 68, 125, 172, 104, 21, 172, 108, 110, + 0, 69, 129, 136, 172, 106, 182, 107, 36, 21, + 172, 70, 21, 172, 0, 70, 0, 71, 0, 178, + 125, 170, 104, 21, 172, 0, 125, 170, 104, 21, + 172, 0, 127, 184, 0, 138, 108, 172, 104, 172, + 110, 0, 180, 104, 108, 172, 104, 172, 110, 0, + 173, 0, 181, 104, 173, 0, 181, 0, 0, 57, + 56, 0, 56, 0, 119, 138, 172, 104, 172, 0, + 120, 138, 172, 104, 172, 0, 121, 138, 172, 104, + 172, 0, 46, 173, 0, 122, 173, 104, 173, 0, + 93, 173, 36, 138, 0, 94, 173, 104, 173, 104, + 173, 0, 97, 173, 104, 138, 0, 101, 173, 104, + 138, 0, 102, 173, 104, 138, 0, 98, 173, 104, + 173, 0, 99, 173, 104, 173, 104, 173, 0, 100, + 173, 104, 173, 104, 173, 0, 92, 180, 0, 183, + 129, 136, 172, 106, 182, 107, 0, 187, 0, 104, + 181, 0, 0, 35, 0, 0, 86, 138, 131, 0, + 86, 138, 104, 15, 172, 131, 0, 87, 138, 131, + 0, 87, 138, 104, 15, 172, 131, 0, 88, 173, + 0, 186, 89, 138, 172, 0, 186, 90, 173, 104, + 138, 172, 0, 91, 138, 172, 185, 0 }; #endif @@ -1199,26 +1200,26 @@ 1029, 1029, 1030, 1030, 1030, 1030, 1030, 1030, 1032, 1032, 1036, 1036, 1036, 1036, 1037, 1037, 1037, 1037, 1038, 1038, 1039, 1039, 1042, 1045, 1049, 1049, 1050, 1051, 1052, 1055, - 1055, 1056, 1057, 1058, 1067, 1067, 1073, 1073, 1081, 1088, - 1088, 1094, 1094, 1096, 1100, 1113, 1113, 1114, 1114, 1116, - 1125, 1125, 1125, 1125, 1125, 1125, 1125, 1126, 1126, 1126, - 1126, 1126, 1126, 1127, 1130, 1133, 1139, 1146, 1158, 1162, - 1173, 1182, 1185, 1193, 1197, 1202, 1203, 1206, 1209, 1219, - 1244, 1257, 1286, 1311, 1331, 1343, 1352, 1356, 1415, 1421, - 1429, 1434, 1439, 1442, 1445, 1452, 1462, 1493, 1500, 1521, - 1531, 1536, 1543, 1548, 1553, 1561, 1564, 1571, 1571, 1581, - 1588, 1592, 1595, 1598, 1601, 1614, 1634, 1636, 1638, 1641, - 1644, 1648, 1651, 1653, 1655, 1659, 1671, 1672, 1674, 1677, - 1685, 1690, 1692, 1696, 1700, 1708, 1708, 1709, 1709, 1711, - 1717, 1722, 1728, 1731, 1736, 1740, 1744, 1830, 1830, 1832, - 1840, 1840, 1842, 1846, 1846, 1855, 1858, 1862, 1865, 1868, - 1871, 1874, 1877, 1880, 1883, 1886, 1910, 1913, 1926, 1929, - 1934, 1934, 1940, 1944, 1947, 1955, 1964, 1968, 1978, 1989, - 1992, 1995, 1998, 2001, 2015, 2019, 2072, 2075, 2081, 2089, - 2099, 2106, 2111, 2118, 2122, 2128, 2128, 2130, 2133, 2139, - 2151, 2162, 2172, 2184, 2191, 2198, 2205, 2210, 2229, 2251, - 2256, 2261, 2266, 2280, 2337, 2343, 2345, 2349, 2352, 2358, - 2362, 2366, 2370, 2374, 2381, 2391, 2404 + 1055, 1056, 1057, 1058, 1059, 1068, 1068, 1074, 1074, 1082, + 1089, 1089, 1095, 1095, 1097, 1101, 1114, 1114, 1115, 1115, + 1117, 1126, 1126, 1126, 1126, 1126, 1126, 1126, 1127, 1127, + 1127, 1127, 1127, 1127, 1128, 1131, 1134, 1140, 1147, 1159, + 1163, 1174, 1183, 1186, 1194, 1198, 1203, 1204, 1207, 1210, + 1220, 1245, 1258, 1287, 1312, 1332, 1344, 1353, 1357, 1416, + 1422, 1430, 1435, 1440, 1443, 1446, 1453, 1463, 1494, 1501, + 1522, 1532, 1537, 1544, 1549, 1554, 1562, 1565, 1572, 1572, + 1582, 1589, 1593, 1596, 1599, 1602, 1615, 1635, 1637, 1639, + 1642, 1645, 1649, 1652, 1654, 1656, 1660, 1672, 1673, 1675, + 1678, 1686, 1691, 1693, 1697, 1701, 1709, 1709, 1710, 1710, + 1712, 1718, 1723, 1729, 1732, 1737, 1741, 1745, 1831, 1831, + 1833, 1841, 1841, 1843, 1847, 1847, 1856, 1859, 1863, 1866, + 1869, 1872, 1875, 1878, 1881, 1884, 1887, 1911, 1914, 1927, + 1930, 1935, 1935, 1941, 1945, 1948, 1956, 1965, 1969, 1979, + 1990, 1993, 1996, 1999, 2002, 2016, 2020, 2073, 2076, 2082, + 2090, 2100, 2107, 2112, 2119, 2123, 2129, 2129, 2131, 2134, + 2140, 2152, 2163, 2173, 2185, 2192, 2199, 2206, 2211, 2230, + 2252, 2257, 2262, 2267, 2281, 2338, 2344, 2346, 2350, 2353, + 2359, 2363, 2367, 2371, 2375, 2382, 2392, 2405 }; #endif @@ -1233,51 +1234,51 @@ "DOTDOTDOT","NULL_TOK","UNDEF","CONST","INTERNAL","LINKONCE","WEAK","APPENDING", "OPAQUE","NOT","EXTERNAL","TARGET","TRIPLE","ENDIAN","POINTERSIZE","LITTLE", "BIG","ALIGN","DEPLIBS","CALL","TAIL","ASM_TOK","MODULE","SIDEEFFECT","CC_TOK", -"CCC_TOK","FASTCC_TOK","COLDCC_TOK","RET","BR","SWITCH","INVOKE","UNWIND","UNREACHABLE", -"ADD","SUB","MUL","DIV","REM","AND","OR","XOR","SETLE","SETGE","SETLT","SETGT", -"SETEQ","SETNE","MALLOC","ALLOCA","FREE","LOAD","STORE","GETELEMENTPTR","PHI_TOK", -"CAST","SELECT","SHL","SHR","VAARG","EXTRACTELEMENT","INSERTELEMENT","SHUFFLEVECTOR", -"VAARG_old","VANEXT_old","'='","','","'\\\\'","'('","')'","'['","'x'","']'", -"'<'","'>'","'{'","'}'","'*'","'c'","INTVAL","EINT64VAL","ArithmeticOps","LogicalOps", -"SetCondOps","ShiftOps","SIntType","UIntType","IntType","FPType","OptAssign", -"OptLinkage","OptCallingConv","OptAlign","OptCAlign","SectionString","OptSection", -"GlobalVarAttributes","GlobalVarAttribute","TypesV","UpRTypesV","Types","PrimType", -"UpRTypes","TypeListI","ArgTypeListI","ConstVal","ConstExpr","ConstVector","GlobalType", -"Module","FunctionList","ConstPool","@1","@2","AsmBlock","BigOrLittle","TargetDefinition", -"LibrariesDefinition","LibList","Name","OptName","ArgVal","ArgListH","ArgList", -"FunctionHeaderH","BEGIN","FunctionHeader","END","Function","FunctionProto", -"@3","OptSideEffect","ConstValueRef","SymbolicValueRef","ValueRef","ResolvedVal", -"BasicBlockList","BasicBlock","InstructionList","BBTerminatorInst","JumpTable", -"Inst","PHIList","ValueRefList","ValueRefListE","OptTailCall","InstVal","IndexList", -"OptVolatile","MemoryInst", NULL +"CCC_TOK","CSRETCC_TOK","FASTCC_TOK","COLDCC_TOK","RET","BR","SWITCH","INVOKE", +"UNWIND","UNREACHABLE","ADD","SUB","MUL","DIV","REM","AND","OR","XOR","SETLE", +"SETGE","SETLT","SETGT","SETEQ","SETNE","MALLOC","ALLOCA","FREE","LOAD","STORE", +"GETELEMENTPTR","PHI_TOK","CAST","SELECT","SHL","SHR","VAARG","EXTRACTELEMENT", +"INSERTELEMENT","SHUFFLEVECTOR","VAARG_old","VANEXT_old","'='","','","'\\\\'", +"'('","')'","'['","'x'","']'","'<'","'>'","'{'","'}'","'*'","'c'","INTVAL","EINT64VAL", +"ArithmeticOps","LogicalOps","SetCondOps","ShiftOps","SIntType","UIntType","IntType", +"FPType","OptAssign","OptLinkage","OptCallingConv","OptAlign","OptCAlign","SectionString", +"OptSection","GlobalVarAttributes","GlobalVarAttribute","TypesV","UpRTypesV", +"Types","PrimType","UpRTypes","TypeListI","ArgTypeListI","ConstVal","ConstExpr", +"ConstVector","GlobalType","Module","FunctionList","ConstPool","@1","@2","AsmBlock", +"BigOrLittle","TargetDefinition","LibrariesDefinition","LibList","Name","OptName", +"ArgVal","ArgListH","ArgList","FunctionHeaderH","BEGIN","FunctionHeader","END", +"Function","FunctionProto","@3","OptSideEffect","ConstValueRef","SymbolicValueRef", +"ValueRef","ResolvedVal","BasicBlockList","BasicBlock","InstructionList","BBTerminatorInst", +"JumpTable","Inst","PHIList","ValueRefList","ValueRefListE","OptTailCall","InstVal", +"IndexList","OptVolatile","MemoryInst", NULL }; #endif static const short yyr1[] = { 0, - 116, 116, 117, 117, 118, 118, 118, 118, 118, 119, - 119, 119, 120, 120, 120, 120, 120, 120, 121, 121, - 122, 122, 122, 122, 123, 123, 123, 123, 124, 124, - 125, 125, 126, 126, 127, 127, 127, 127, 127, 128, - 128, 128, 128, 128, 129, 129, 130, 130, 131, 132, - 132, 133, 133, 134, 134, 135, 135, 136, 136, 137, - 138, 138, 138, 138, 138, 138, 138, 138, 138, 138, - 138, 138, 138, 139, 139, 139, 139, 139, 139, 139, - 139, 139, 139, 140, 140, 141, 141, 141, 141, 142, - 142, 142, 142, 142, 142, 142, 142, 142, 142, 142, - 142, 142, 142, 142, 142, 143, 143, 143, 143, 143, - 143, 143, 143, 143, 143, 144, 144, 145, 145, 146, - 147, 147, 147, 147, 147, 148, 148, 148, 149, 148, - 150, 148, 148, 148, 148, 151, 152, 152, 153, 153, - 153, 154, 155, 155, 155, 156, 156, 157, 157, 158, - 159, 159, 160, 160, 160, 160, 161, 162, 162, 163, - 164, 164, 165, 167, 166, 168, 168, 169, 169, 169, - 169, 169, 169, 169, 169, 169, 169, 169, 170, 170, - 171, 171, 172, 173, 173, 174, 175, 175, 175, 176, - 176, 176, 176, 176, 176, 176, 176, 176, 177, 177, - 178, 179, 179, 180, 180, 181, 181, 182, 182, 183, - 183, 183, 183, 183, 183, 183, 183, 183, 183, 183, - 183, 183, 183, 183, 183, 184, 184, 185, 185, 186, - 186, 186, 186, 186, 186, 186, 186 + 117, 117, 118, 118, 119, 119, 119, 119, 119, 120, + 120, 120, 121, 121, 121, 121, 121, 121, 122, 122, + 123, 123, 123, 123, 124, 124, 124, 124, 125, 125, + 126, 126, 127, 127, 128, 128, 128, 128, 128, 129, + 129, 129, 129, 129, 129, 130, 130, 131, 131, 132, + 133, 133, 134, 134, 135, 135, 136, 136, 137, 137, + 138, 139, 139, 139, 139, 139, 139, 139, 139, 139, + 139, 139, 139, 139, 140, 140, 140, 140, 140, 140, + 140, 140, 140, 140, 141, 141, 142, 142, 142, 142, + 143, 143, 143, 143, 143, 143, 143, 143, 143, 143, + 143, 143, 143, 143, 143, 143, 144, 144, 144, 144, + 144, 144, 144, 144, 144, 144, 145, 145, 146, 146, + 147, 148, 148, 148, 148, 148, 149, 149, 149, 150, + 149, 151, 149, 149, 149, 149, 152, 153, 153, 154, + 154, 154, 155, 156, 156, 156, 157, 157, 158, 158, + 159, 160, 160, 161, 161, 161, 161, 162, 163, 163, + 164, 165, 165, 166, 168, 167, 169, 169, 170, 170, + 170, 170, 170, 170, 170, 170, 170, 170, 170, 171, + 171, 172, 172, 173, 174, 174, 175, 176, 176, 176, + 177, 177, 177, 177, 177, 177, 177, 177, 177, 178, + 178, 179, 180, 180, 181, 181, 182, 182, 183, 183, + 184, 184, 184, 184, 184, 184, 184, 184, 184, 184, + 184, 184, 184, 184, 184, 184, 185, 185, 186, 186, + 187, 187, 187, 187, 187, 187, 187, 187 }; static const short yyr2[] = { 0, @@ -1285,426 +1286,418 @@ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 0, 1, 1, 1, 1, 0, 0, - 1, 1, 1, 2, 0, 2, 0, 3, 2, 0, - 1, 0, 3, 1, 2, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 2, 0, 2, 0, 3, 2, + 0, 1, 0, 3, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 2, 4, 5, 5, - 3, 2, 2, 1, 3, 1, 3, 1, 0, 4, - 3, 3, 4, 4, 3, 2, 2, 2, 2, 2, - 2, 2, 2, 2, 2, 6, 5, 8, 6, 6, - 6, 6, 6, 8, 8, 3, 1, 1, 1, 1, - 2, 2, 4, 2, 1, 4, 2, 4, 0, 7, - 0, 7, 3, 4, 0, 1, 1, 1, 3, 3, - 3, 3, 3, 1, 0, 1, 1, 1, 0, 2, - 3, 1, 1, 3, 1, 0, 8, 1, 1, 3, - 1, 1, 2, 0, 3, 0, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 3, 1, 5, 1, 1, - 1, 1, 2, 2, 2, 3, 2, 0, 1, 2, - 2, 3, 9, 9, 8, 13, 1, 1, 6, 5, - 2, 6, 7, 1, 3, 1, 0, 2, 1, 5, - 5, 5, 2, 4, 4, 6, 4, 4, 4, 4, - 6, 6, 2, 7, 1, 2, 0, 1, 0, 3, - 6, 3, 6, 2, 4, 6, 4 + 1, 1, 1, 1, 1, 1, 1, 2, 4, 5, + 5, 3, 2, 2, 1, 3, 1, 3, 1, 0, + 4, 3, 3, 4, 4, 3, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 2, 6, 5, 8, 6, + 6, 6, 6, 6, 8, 8, 3, 1, 1, 1, + 1, 2, 2, 4, 2, 1, 4, 2, 4, 0, + 7, 0, 7, 3, 4, 0, 1, 1, 1, 3, + 3, 3, 3, 3, 1, 0, 1, 1, 1, 0, + 2, 3, 1, 1, 3, 1, 0, 8, 1, 1, + 3, 1, 1, 2, 0, 3, 0, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 3, 1, 5, 1, + 1, 1, 1, 2, 2, 2, 3, 2, 0, 1, + 2, 2, 3, 9, 9, 8, 13, 1, 1, 6, + 5, 2, 6, 7, 1, 3, 1, 0, 2, 1, + 5, 5, 5, 2, 4, 4, 6, 4, 4, 4, + 4, 6, 6, 2, 7, 1, 2, 0, 1, 0, + 3, 6, 3, 6, 2, 4, 6, 4 }; -static const short yydefact[] = { 135, - 39, 125, 124, 164, 35, 36, 37, 38, 0, 40, - 188, 121, 122, 188, 146, 147, 0, 0, 0, 39, - 0, 127, 40, 0, 0, 41, 42, 43, 0, 0, - 189, 185, 34, 161, 162, 163, 184, 0, 0, 0, - 133, 0, 0, 0, 0, 0, 33, 165, 136, 123, - 44, 1, 2, 57, 61, 62, 63, 64, 65, 66, - 67, 68, 69, 70, 71, 72, 73, 74, 0, 0, - 0, 0, 179, 0, 0, 56, 75, 60, 180, 76, - 158, 159, 160, 229, 187, 0, 0, 0, 145, 134, - 128, 126, 118, 119, 0, 0, 77, 0, 0, 59, - 82, 84, 0, 0, 89, 83, 228, 0, 209, 0, - 0, 0, 0, 40, 197, 198, 5, 6, 7, 8, - 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, - 0, 0, 0, 0, 0, 0, 0, 19, 20, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 186, - 40, 201, 0, 225, 141, 138, 137, 139, 140, 144, - 0, 131, 61, 62, 63, 64, 65, 66, 67, 68, - 69, 70, 71, 0, 0, 0, 0, 129, 0, 0, - 0, 81, 156, 88, 86, 0, 0, 213, 208, 191, - 190, 0, 0, 24, 28, 23, 27, 22, 26, 21, - 25, 29, 30, 0, 0, 47, 47, 234, 0, 0, - 223, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 142, 52, 103, - 104, 3, 4, 101, 102, 105, 100, 96, 97, 0, +static const short yydefact[] = { 136, + 39, 126, 125, 165, 35, 36, 37, 38, 0, 40, + 189, 122, 123, 189, 147, 148, 0, 0, 0, 39, + 0, 128, 40, 0, 0, 41, 42, 43, 44, 0, + 0, 190, 186, 34, 162, 163, 164, 185, 0, 0, + 0, 134, 0, 0, 0, 0, 0, 33, 166, 137, + 124, 45, 1, 2, 58, 62, 63, 64, 65, 66, + 67, 68, 69, 70, 71, 72, 73, 74, 75, 0, + 0, 0, 0, 180, 0, 0, 57, 76, 61, 181, + 77, 159, 160, 161, 230, 188, 0, 0, 0, 146, + 135, 129, 127, 119, 120, 0, 0, 78, 0, 0, + 60, 83, 85, 0, 0, 90, 84, 229, 0, 210, + 0, 0, 0, 0, 40, 198, 199, 5, 6, 7, + 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, + 18, 0, 0, 0, 0, 0, 0, 0, 19, 20, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 187, 40, 202, 0, 226, 142, 139, 138, 140, 141, + 145, 0, 132, 62, 63, 64, 65, 66, 67, 68, + 69, 70, 71, 72, 0, 0, 0, 0, 130, 0, + 0, 0, 82, 157, 89, 87, 0, 0, 214, 209, + 192, 191, 0, 0, 24, 28, 23, 27, 22, 26, + 21, 25, 29, 30, 0, 0, 48, 48, 235, 0, + 0, 224, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 143, 53, + 104, 105, 3, 4, 102, 103, 106, 101, 97, 98, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 99, 98, 52, 58, 58, 85, 155, - 149, 152, 153, 0, 0, 78, 168, 169, 170, 175, - 171, 172, 173, 174, 166, 0, 177, 182, 181, 183, - 0, 192, 0, 0, 0, 230, 0, 232, 227, 0, + 0, 0, 0, 0, 100, 99, 53, 59, 59, 86, + 156, 150, 153, 154, 0, 0, 79, 169, 170, 171, + 176, 172, 173, 174, 175, 167, 0, 178, 183, 182, + 184, 0, 193, 0, 0, 0, 231, 0, 233, 228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 143, 0, 132, 0, - 0, 0, 0, 0, 0, 91, 117, 0, 0, 95, - 0, 92, 0, 0, 0, 0, 130, 79, 80, 148, - 150, 0, 50, 87, 167, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 237, 0, 0, 215, 0, 217, - 220, 0, 0, 218, 219, 0, 0, 0, 214, 0, - 235, 0, 0, 0, 54, 52, 227, 0, 0, 0, - 0, 0, 0, 90, 93, 94, 0, 0, 0, 0, - 154, 151, 51, 45, 0, 176, 0, 0, 207, 47, - 48, 47, 204, 226, 0, 0, 0, 0, 0, 210, - 211, 212, 207, 0, 49, 55, 53, 0, 0, 0, - 0, 0, 0, 116, 0, 0, 0, 0, 0, 157, - 0, 0, 0, 206, 0, 0, 231, 233, 0, 0, - 0, 216, 221, 222, 0, 236, 107, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 46, 178, 0, 0, - 0, 205, 202, 0, 224, 106, 0, 113, 0, 0, - 109, 110, 111, 112, 0, 195, 0, 0, 0, 203, - 0, 0, 0, 193, 0, 194, 0, 0, 108, 114, - 115, 0, 0, 0, 0, 0, 0, 200, 0, 0, - 199, 196, 0, 0, 0 + 0, 0, 0, 0, 0, 0, 0, 144, 0, 133, + 0, 0, 0, 0, 0, 0, 92, 118, 0, 0, + 96, 0, 93, 0, 0, 0, 0, 131, 80, 81, + 149, 151, 0, 51, 88, 168, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 238, 0, 0, 216, 0, + 218, 221, 0, 0, 219, 220, 0, 0, 0, 215, + 0, 236, 0, 0, 0, 55, 53, 228, 0, 0, + 0, 0, 0, 0, 91, 94, 95, 0, 0, 0, + 0, 155, 152, 52, 46, 0, 177, 0, 0, 208, + 48, 49, 48, 205, 227, 0, 0, 0, 0, 0, + 211, 212, 213, 208, 0, 50, 56, 54, 0, 0, + 0, 0, 0, 0, 117, 0, 0, 0, 0, 0, + 158, 0, 0, 0, 207, 0, 0, 232, 234, 0, + 0, 0, 217, 222, 223, 0, 237, 108, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 47, 179, 0, + 0, 0, 206, 203, 0, 225, 107, 0, 114, 0, + 0, 110, 111, 112, 113, 0, 196, 0, 0, 0, + 204, 0, 0, 0, 194, 0, 195, 0, 0, 109, + 115, 116, 0, 0, 0, 0, 0, 0, 201, 0, + 0, 200, 197, 0, 0, 0 }; -static const short yydefgoto[] = { 73, - 234, 250, 251, 252, 253, 174, 175, 204, 176, 20, - 10, 29, 420, 286, 365, 384, 309, 366, 74, 75, - 177, 77, 78, 103, 186, 317, 277, 318, 95, 493, - 1, 2, 256, 229, 50, 158, 41, 90, 161, 79, - 331, 262, 263, 264, 30, 83, 11, 36, 12, 13, - 23, 336, 278, 80, 280, 393, 14, 32, 33, 150, - 468, 85, 211, 424, 425, 151, 152, 345, 153, 154 +static const short yydefgoto[] = { 74, + 235, 251, 252, 253, 254, 175, 176, 205, 177, 20, + 10, 30, 421, 287, 366, 385, 310, 367, 75, 76, + 178, 78, 79, 104, 187, 318, 278, 319, 96, 494, + 1, 2, 257, 230, 51, 159, 42, 91, 162, 80, + 332, 263, 264, 265, 31, 84, 11, 37, 12, 13, + 23, 337, 279, 81, 281, 394, 14, 33, 34, 151, + 469, 86, 212, 425, 426, 152, 153, 346, 154, 155 }; static const short yypact[] = {-32768, - 181, 364,-32768,-32768,-32768,-32768,-32768,-32768, 6, -1, - 60,-32768,-32768, -14,-32768,-32768, 47, -22, 72, 45, - 33,-32768, -1, 125, 157,-32768,-32768,-32768, 1050, -21, --32768,-32768, 22,-32768,-32768,-32768,-32768, 61, 67, 68, --32768, 55, 125, 1050, -6, -6,-32768,-32768,-32768,-32768, --32768,-32768,-32768, 66,-32768,-32768,-32768,-32768,-32768,-32768, --32768,-32768,-32768,-32768,-32768,-32768,-32768,-32768, 168, 170, - 171, 566,-32768, 22, 73,-32768,-32768, -24,-32768,-32768, --32768,-32768,-32768, 1213,-32768, 149, 57, 173, 155,-32768, --32768,-32768,-32768,-32768, 1088, 1126,-32768, 74, 75,-32768, --32768, -24, -82, 79, 860,-32768,-32768, 1088,-32768, 124, - 1164, 14, 128, -1,-32768,-32768,-32768,-32768,-32768,-32768, + 181, 372,-32768,-32768,-32768,-32768,-32768,-32768, -32, 94, + 38,-32768,-32768, -14,-32768,-32768, 45, -40, 18, 44, + -25,-32768, 94, 57, 79,-32768,-32768,-32768,-32768, 1012, + -21,-32768,-32768, 22,-32768,-32768,-32768,-32768, -6, -4, + 27,-32768, 26, 57, 1012, 77, 77,-32768,-32768,-32768, +-32768,-32768,-32768,-32768, 46,-32768,-32768,-32768,-32768,-32768, +-32768,-32768,-32768,-32768,-32768,-32768,-32768,-32768,-32768, 167, + 170, 171, 524,-32768, 22, 71,-32768,-32768, -17,-32768, +-32768,-32768,-32768,-32768, 1176,-32768, 154, 76, 175, 156, +-32768,-32768,-32768,-32768,-32768, 1050, 1088,-32768, 73, 74, +-32768,-32768, -17, -83, 78, 819,-32768,-32768, 1050,-32768, + 129, 1126, 56, 128, 94,-32768,-32768,-32768,-32768,-32768, +-32768,-32768,-32768,-32768,-32768,-32768,-32768,-32768,-32768,-32768, +-32768, 1050, 1050, 1050, 1050, 1050, 1050, 1050,-32768,-32768, + 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1050, +-32768, 94,-32768, 43,-32768,-32768,-32768,-32768,-32768,-32768, +-32768, -82,-32768, 119, 146, 183, 157, 190, 159, 194, + 166, 196, 195, 197, 169, 199, 198, 406,-32768, 1050, + 1050, 1050,-32768, 857,-32768, 97, 100, 617,-32768,-32768, + 46,-32768, 617, 617,-32768,-32768,-32768,-32768,-32768,-32768, +-32768,-32768,-32768,-32768, 617, 1012, 104, 105,-32768, 617, + 103, 109, 178, 111, 122, 123, 131, 132, 133, 134, + 617, 617, 617, 135, 1012, 1050, 1050, 209,-32768, 137, -32768,-32768,-32768,-32768,-32768,-32768,-32768,-32768,-32768,-32768, - 1088, 1088, 1088, 1088, 1088, 1088, 1088,-32768,-32768, 1088, - 1088, 1088, 1088, 1088, 1088, 1088, 1088, 1088, 1088,-32768, - -1,-32768, 40,-32768,-32768,-32768,-32768,-32768,-32768,-32768, - -9,-32768, 106, 143, 183, 148, 190, 152, 194, 154, - 196, 178, 195, 156, 197, 198, 425,-32768, 1088, 1088, - 1088,-32768, 898,-32768, 100, 98, 660,-32768,-32768, 66, --32768, 660, 660,-32768,-32768,-32768,-32768,-32768,-32768,-32768, --32768,-32768,-32768, 660, 1050, 104, 105,-32768, 660, 102, - 108, 177, 111, 112, 123, 130, 132, 133, 134, 660, - 660, 660, 135, 1050, 1088, 1088, 203,-32768, 136,-32768, --32768,-32768,-32768,-32768,-32768,-32768,-32768,-32768,-32768, 137, - 138, 139, 140, 141, 142, 936, 1126, 604, 217, 145, - 146, 147, 150,-32768,-32768, 136, 18, -86, -24,-32768, - 22,-32768, 151, 153, 974,-32768,-32768,-32768,-32768,-32768, --32768,-32768,-32768,-32768, 193, 1126,-32768,-32768,-32768,-32768, - 158,-32768, 159, 660, -5,-32768, 5,-32768, 172, 660, - 165, 1088, 1088, 1088, 1088, 1088, 1088, 1088, 1088, 174, - 175, 179, 1088, 660, 660, 180,-32768, -20,-32768, 1126, - 1126, 1126, 1126, 1126, 1126,-32768,-32768, -8, -81,-32768, - -36,-32768, 1126, 1126, 1126, 1126,-32768,-32768,-32768,-32768, --32768, 1012, 222,-32768,-32768, 233, -18, 237, 239, 176, - 660, 269, 660, 1088,-32768, 185, 660,-32768, 186,-32768, --32768, 187, 189,-32768,-32768, 660, 660, 660,-32768, 191, --32768, 1088, 252, 276,-32768, 136, 172, 248, 201, 202, - 204, 205, 1126,-32768,-32768,-32768, 206, 207, 208, 209, --32768,-32768,-32768, 232, 210,-32768, 660, 660, 1088, 211, --32768, 211,-32768, 223, 660, 224, 1088, 1088, 1088,-32768, --32768,-32768, 1088, 660,-32768,-32768,-32768, 192, 1088, 1126, - 1126, 1126, 1126,-32768, 1126, 1126, 1126, 1126, 293,-32768, - 275, 225, 199, 223, 214, 280,-32768,-32768, 1088, 220, - 660,-32768,-32768,-32768, 229,-32768,-32768, 230, 227, 231, - 238, 240, 236, 241, 243, 244,-32768,-32768, 323, 41, - 309,-32768,-32768, 242,-32768,-32768, 1126,-32768, 1126, 1126, --32768,-32768,-32768,-32768, 660,-32768, 757, 59, 325,-32768, - 246, 247, 249,-32768, 251,-32768, 757, 660,-32768,-32768, --32768, 336, 256, 295, 660, 346, 350,-32768, 660, 660, --32768,-32768, 372, 376,-32768 + 136, 138, 139, 140, 141, 144, 895, 1088, 566, 219, + 145, 147, 148, 149,-32768,-32768, 137, -48, -88, -17, +-32768, 22,-32768, 152, 150, 936,-32768,-32768,-32768,-32768, +-32768,-32768,-32768,-32768,-32768, 192, 1088,-32768,-32768,-32768, +-32768, 155,-32768, 158, 617, -5,-32768, 5,-32768, 172, + 617, 153, 1050, 1050, 1050, 1050, 1050, 1050, 1050, 1050, + 173, 174, 176, 1050, 617, 617, 177,-32768, -20,-32768, + 1088, 1088, 1088, 1088, 1088, 1088,-32768,-32768, -62, -11, +-32768, -79,-32768, 1088, 1088, 1088, 1088,-32768,-32768,-32768, +-32768,-32768, 974, 224,-32768,-32768, 236, 23, 251, 252, + 180, 617, 271, 617, 1050,-32768, 179, 617,-32768, 184, +-32768,-32768, 185, 186,-32768,-32768, 617, 617, 617,-32768, + 191,-32768, 1050, 258, 280,-32768, 137, 172, 256, 200, + 201, 202, 203, 1088,-32768,-32768,-32768, 204, 205, 206, + 207,-32768,-32768,-32768, 242, 208,-32768, 617, 617, 1050, + 210,-32768, 210,-32768, 216, 617, 222, 1050, 1050, 1050, +-32768,-32768,-32768, 1050, 617,-32768,-32768,-32768, 220, 1050, + 1088, 1088, 1088, 1088,-32768, 1088, 1088, 1088, 1088, 294, +-32768, 275, 225, 226, 216, 221, 259,-32768,-32768, 1050, + 227, 617,-32768,-32768,-32768, 223,-32768,-32768, 228, 232, + 234, 238, 239, 237, 240, 243, 244,-32768,-32768, 324, + 41, 310,-32768,-32768, 245,-32768,-32768, 1088,-32768, 1088, + 1088,-32768,-32768,-32768,-32768, 617,-32768, 715, 58, 328, +-32768, 246, 247, 250,-32768, 248,-32768, 715, 617,-32768, +-32768,-32768, 338, 260, 297, 617, 350, 351,-32768, 617, + 617,-32768,-32768, 376, 377,-32768 }; static const short yypgoto[] = {-32768, --32768, 297, 298, 299, 301, -112, -110, -426,-32768, 344, - 359, -103,-32768, -202, 54,-32768, -243,-32768, -38,-32768, - -29,-32768, -55, 287,-32768, -94, 216, -229, 348,-32768, --32768,-32768,-32768,-32768, 355,-32768,-32768,-32768,-32768, 10, --32768, 69,-32768,-32768, 379,-32768,-32768,-32768,-32768, 397, --32768,-32768, -399, -56, 169, -104,-32768, 389,-32768,-32768, --32768,-32768,-32768, 70, 1,-32768,-32768, 43,-32768,-32768 +-32768, 296, 298, 299, 300, -113, -111, -439,-32768, 345, + 362, -92,-32768, -203, 52,-32768, -244,-32768, -39,-32768, + -30,-32768, -56, 281,-32768, -95, 215, -230, 341,-32768, +-32768,-32768,-32768,-32768, 353,-32768,-32768,-32768,-32768, 9, +-32768, 62,-32768,-32768, 375,-32768,-32768,-32768,-32768, 397, +-32768,-32768, -388, -57, 168, -105,-32768, 387,-32768,-32768, +-32768,-32768,-32768, 61, -2,-32768,-32768, 39,-32768,-32768 }; -#define YYLAST 1314 +#define YYLAST 1278 -static const short yytable[] = { 76, - 202, 178, 203, 188, 288, 92, 191, 81, 31, 341, - 205, 21, 327, 363, 76, 34, 102, 319, 321, 343, - 181, 373, 192, 467, 329, 93, 94, 106, 208, 375, - 182, 212, 213, 364, 193, 214, 215, 216, 217, 218, - 219, 477, 21, 15, 223, 16, 337, 224, 342, 102, - 194, 195, 196, 197, 198, 199, 200, 201, 342, 25, - 26, 27, 28, 24, 44, 162, 373, 475, 194, 195, - 196, 197, 198, 199, 200, 201, 376, 483, 187, 42, - -58, 187, 31, 104, 373, 5, 6, 7, 8, 106, - 82, 45, 386, 227, 373, 38, 39, 40, 35, 228, - 374, 206, 207, 187, 209, 210, 187, 187, 156, 157, - 187, 187, 187, 187, 187, 187, 220, 221, 222, 187, - 255, 306, 407, 257, 258, 259, 328, 225, 226, 43, - 279, 106, 230, 231, 47, 279, 279, 194, 195, 196, - 197, 198, 199, 200, 201, -24, -24, 279, 49, 466, - -23, -23, 279, 261, -22, -22, -21, -21, 232, 233, - 51, 89, 86, 279, 279, 279, 284, 476, 87, 88, - -59, 97, 155, 98, 99, 76, 159, 105, 160, 189, - -120, 179, 180, 183, -31, 304, -28, 427, 349, 428, - 351, 352, 353, -27, 76, 305, 187, -26, 359, -25, - 235, -32, 265, 266, 236, 3, 285, 287, 290, 259, - 291, 4, 292, 293, 294, 367, 368, 369, 370, 371, - 372, 5, 6, 7, 8, 295, 307, 279, 377, 378, - 379, 380, 296, 279, 297, 298, 299, 303, 308, 9, - 322, 310, 311, 312, 313, 314, 315, 279, 279, 323, - 324, 325, 335, 332, 326, 363, 385, 387, 333, 388, - 338, 339, 348, 187, 350, 187, 187, 187, 354, 355, - 330, 347, 391, 187, 344, 405, 356, 357, 414, 406, - 389, 358, 362, 409, 279, 419, 279, 395, 397, 398, - 279, 399, 432, 433, 434, 403, 447, 437, 448, 279, - 279, 279, 261, 410, 411, 450, 412, 413, 415, 416, - 417, 418, 421, 426, 187, 439, 440, 441, 442, 451, - 443, 444, 445, 446, 452, 429, 431, 449, 453, 457, - 279, 279, 404, 342, 455, 456, 458, 202, 279, 203, - 459, 461, 460, 465, 469, 478, 462, 279, 463, 464, - 470, 479, 480, 482, 481, 202, 485, 203, 486, 187, - 281, 282, 471, 487, 472, 473, 489, 187, 187, 187, - 490, 494, 283, 187, 279, 495, 84, 289, 46, 438, - 146, 147, 148, -34, 149, 15, 383, 16, 300, 301, - 302, 185, 254, 96, 4, -34, -34, 91, 22, 187, - 382, 48, 37, 435, -34, -34, -34, -34, 279, 408, - -34, 17, 0, 394, 0, 0, 0, 0, 18, 0, - 0, 279, 19, 0, 0, 0, 0, 0, 279, 52, - 53, 0, 279, 279, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 15, 0, 16, 0, - 237, 0, 340, 0, 0, 0, 0, 0, 346, 0, - 0, 0, 238, 239, 0, 0, 0, 0, 0, 0, - 0, 0, 360, 361, 0, 0, 0, 0, 0, 0, +static const short yytable[] = { 77, + 203, 179, 204, 189, 289, 93, 192, 82, 32, 342, + 21, 468, 328, 364, 77, 35, 103, 320, 322, 344, + 182, 228, 206, 330, 374, 24, 107, 229, 209, 478, + 183, 213, 214, 365, 377, 215, 216, 217, 218, 219, + 220, 374, 21, 15, 224, 16, 338, 375, 343, 103, + 195, 196, 197, 198, 199, 200, 201, 202, 343, 225, + 32, 329, 43, 45, 193, 163, 107, 195, 196, 197, + 198, 199, 200, 201, 202, 44, 194, 48, 188, 476, + 50, 188, 52, 105, 5, 6, 7, 8, -59, 484, + 46, 83, 374, 39, 40, 41, 87, 107, 88, 36, + 376, 207, 208, 188, 210, 211, 188, 188, 94, 95, + 188, 188, 188, 188, 188, 188, 221, 222, 223, 188, + 256, 307, 408, 258, 259, 260, 374, 157, 158, 89, + 280, 226, 227, 90, 387, 280, 280, 195, 196, 197, + 198, 199, 200, 201, 202, 231, 232, 280, -24, -24, + 467, -60, 280, 262, 25, 26, 27, 28, 29, -23, + -23, -22, -22, 280, 280, 280, 285, 477, -21, -21, + 98, 233, 234, 99, 100, 77, 106, 156, 160, 161, + -121, 180, 181, 184, 190, 305, -28, 428, 350, 429, + 352, 353, 354, -27, 77, 306, 188, -26, 360, -25, + 266, -31, 236, -32, 237, 3, 267, 286, 288, 260, + 291, 4, 292, 293, 294, 368, 369, 370, 371, 372, + 373, 5, 6, 7, 8, 295, 296, 280, 378, 379, + 380, 381, 308, 280, 297, 298, 299, 300, 304, 9, + 309, 311, 323, 312, 313, 314, 315, 280, 280, 316, + 324, 336, 325, 326, 327, 333, 334, 364, 339, 386, + 348, 340, 349, 188, 351, 188, 188, 188, 355, 356, + 331, 388, 389, 188, 392, 345, 357, 358, 415, 359, + 363, 406, 396, 407, 280, 390, 280, 398, 399, 400, + 280, 410, 433, 434, 435, 420, 404, 448, 449, 280, + 280, 280, 262, 411, 412, 413, 414, 416, 417, 418, + 419, 422, 343, 427, 188, 440, 441, 442, 443, 430, + 444, 445, 446, 447, 453, 432, 438, 452, 450, 456, + 280, 280, 405, 451, 457, 458, 454, 203, 280, 204, + 459, 460, 461, 462, 466, 470, 463, 280, 479, 464, + 465, 483, 480, 481, 471, 203, 482, 204, 486, 188, + 282, 283, 472, 487, 473, 474, 488, 188, 188, 188, + 490, 491, 284, 188, 280, 495, 496, 290, 85, 439, + 147, 47, 148, 149, 150, 384, 186, 97, 301, 302, + 303, -34, 255, 15, 383, 16, 92, 49, 22, 188, + 38, 436, 4, -34, -34, 395, 409, 0, 280, 0, + 53, 54, -34, -34, -34, -34, 0, 0, -34, 17, + 0, 280, 0, 0, 0, 0, 18, 15, 280, 16, + 19, 238, 280, 280, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 239, 240, 0, 0, 0, 0, 0, + 0, 0, 341, 0, 0, 0, 0, 0, 347, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 117, 118, 119, 120, 121, - 122, 123, 124, 125, 126, 127, 128, 129, 130, 390, - 0, 392, 0, 0, 240, 396, 241, 242, 138, 139, - 0, 243, 244, 245, 400, 401, 402, 0, 0, 0, - 0, 246, 0, 0, 247, 0, 248, 0, 0, 249, + 0, 0, 361, 362, 0, 0, 0, 118, 119, 120, + 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, + 131, 0, 0, 0, 0, 0, 241, 0, 242, 243, + 139, 140, 0, 244, 245, 246, 0, 0, 0, 391, + 0, 393, 0, 247, 0, 397, 248, 0, 249, 0, + 0, 250, 0, 0, 401, 402, 403, 0, 53, 54, + 0, 101, 56, 57, 58, 59, 60, 61, 62, 63, + 64, 65, 66, 67, 68, 15, 0, 16, 0, 0, + 0, 0, 0, 0, 0, 423, 424, 0, 0, 0, + 0, 0, 0, 431, 0, 0, 0, 0, 69, 0, + 53, 54, 437, 101, 164, 165, 166, 167, 168, 169, + 170, 171, 172, 173, 174, 67, 68, 15, 0, 16, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 455, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 422, 423, 0, 0, 0, - 0, 0, 0, 430, 0, 0, 0, 0, 0, 0, - 52, 53, 436, 100, 55, 56, 57, 58, 59, 60, - 61, 62, 63, 64, 65, 66, 67, 15, 0, 16, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 454, - 0, 0, 0, 0, 0, 0, 0, 0, 52, 53, - 68, 100, 163, 164, 165, 166, 167, 168, 169, 170, - 171, 172, 173, 66, 67, 15, 0, 16, 0, 0, - 0, 0, 0, 474, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 484, 0, 68, 0, - 0, 0, 0, 488, 0, 0, 0, 491, 492, 0, - 0, 0, 267, 268, 52, 53, 269, 0, 0, 69, - 0, 0, 70, 0, 0, 71, 0, 72, 101, 0, - 0, 15, 0, 16, 0, 270, 271, 272, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 273, 274, 0, - 0, 0, 0, 0, 0, 0, 0, 69, 0, 0, - 70, 0, 0, 71, 0, 72, 320, 275, 0, 0, + 69, 0, 0, 0, 0, 0, 0, 0, 0, 268, + 269, 53, 54, 270, 0, 0, 0, 0, 70, 0, + 0, 71, 0, 475, 72, 0, 73, 102, 15, 0, + 16, 0, 271, 272, 273, 0, 485, 0, 0, 0, + 0, 0, 0, 489, 274, 275, 0, 492, 493, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, - 127, 128, 129, 130, 0, 0, 0, 0, 0, 240, - 0, 241, 242, 138, 139, 0, 243, 244, 245, 267, - 268, 0, 0, 269, 0, 0, 0, 0, 0, 276, + 70, 0, 0, 71, 276, 0, 72, 0, 73, 321, + 0, 0, 0, 0, 0, 0, 0, 0, 118, 119, + 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, + 130, 131, 0, 0, 0, 0, 0, 241, 0, 242, + 243, 139, 140, 0, 244, 245, 246, 268, 269, 0, + 0, 270, 0, 0, 0, 0, 0, 277, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 270, 271, 272, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 273, 274, 0, 0, 0, 0, + 271, 272, 273, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 274, 275, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 275, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 117, 118, 119, - 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, - 130, 0, 0, 0, 0, 0, 240, 0, 241, 242, - 138, 139, 0, 243, 244, 245, 0, 0, 0, 0, - 0, 0, 0, 0, 52, 53, 276, 100, 55, 56, - 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, - 67, 15, 0, 16, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 184, 0, 0, 0, - 0, 0, 52, 53, 68, 100, 55, 56, 57, 58, - 59, 60, 61, 62, 63, 64, 65, 66, 67, 15, - 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 260, 0, 0, 0, 0, 0, - 52, 53, 68, 100, 163, 164, 165, 166, 167, 168, - 169, 170, 171, 172, 173, 66, 67, 15, 0, 16, - 0, 0, 0, 69, 0, 0, 70, 0, 0, 71, - 0, 72, 0, 0, 0, 0, 0, 0, 52, 53, - 68, 100, 55, 56, 57, 58, 59, 60, 61, 62, - 63, 64, 65, 66, 67, 15, 0, 16, 0, 0, - 0, 69, 0, 0, 70, 0, 0, 71, 0, 72, - 334, 0, 0, 0, 0, 0, 52, 53, 68, 100, - 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, - 65, 66, 67, 15, 0, 16, 0, 0, 0, 69, - 0, 0, 70, 0, 316, 71, 0, 72, 381, 0, - 0, 0, 0, 0, 52, 53, 68, 54, 55, 56, - 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, - 67, 15, 0, 16, 0, 0, 0, 69, 0, 0, - 70, 0, 0, 71, 0, 72, 0, 0, 0, 0, - 0, 0, 52, 53, 68, 100, 55, 56, 57, 58, - 59, 60, 61, 62, 63, 64, 65, 66, 67, 15, - 0, 16, 0, 0, 0, 69, 0, 0, 70, 0, - 0, 71, 0, 72, 0, 0, 0, 0, 0, 0, - 52, 53, 68, 100, 163, 164, 165, 166, 167, 168, - 169, 170, 171, 172, 173, 66, 67, 15, 0, 16, - 0, 0, 0, 69, 0, 0, 70, 0, 0, 71, - 0, 72, 0, 0, 0, 0, 0, 0, 52, 53, - 68, 190, 55, 56, 57, 58, 59, 60, 61, 62, - 63, 64, 65, 66, 67, 15, 0, 16, 0, 0, - 0, 69, 0, 0, 70, 0, 0, 71, 0, 72, - 0, 0, 0, 0, 0, 0, 0, 0, 68, 0, + 0, 0, 276, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 118, 119, 120, 121, + 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, + 0, 0, 0, 0, 0, 241, 0, 242, 243, 139, + 140, 0, 244, 245, 246, 0, 0, 0, 0, 0, + 0, 0, 0, 53, 54, 277, 101, 56, 57, 58, + 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, + 15, 0, 16, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 185, 0, 0, 0, 0, + 0, 53, 54, 69, 101, 56, 57, 58, 59, 60, + 61, 62, 63, 64, 65, 66, 67, 68, 15, 0, + 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 261, 0, 0, 0, 0, 0, 53, + 54, 69, 101, 164, 165, 166, 167, 168, 169, 170, + 171, 172, 173, 174, 67, 68, 15, 0, 16, 0, + 0, 0, 0, 70, 0, 0, 71, 0, 0, 72, + 0, 73, 0, 0, 0, 0, 0, 0, 0, 69, + 53, 54, 0, 101, 56, 57, 58, 59, 60, 61, + 62, 63, 64, 65, 66, 67, 68, 15, 0, 16, + 0, 70, 0, 0, 71, 0, 0, 72, 0, 73, + 0, 0, 335, 0, 0, 0, 0, 0, 53, 54, + 69, 101, 56, 57, 58, 59, 60, 61, 62, 63, + 64, 65, 66, 67, 68, 15, 0, 16, 0, 70, + 0, 0, 71, 0, 317, 72, 0, 73, 0, 0, + 382, 0, 0, 0, 0, 0, 53, 54, 69, 55, + 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, + 66, 67, 68, 15, 0, 16, 0, 0, 0, 0, + 70, 0, 0, 71, 0, 0, 72, 0, 73, 0, + 0, 0, 0, 0, 53, 54, 69, 101, 56, 57, + 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, + 68, 15, 0, 16, 0, 0, 0, 0, 70, 0, + 0, 71, 0, 0, 72, 0, 73, 0, 0, 0, + 0, 0, 53, 54, 69, 101, 164, 165, 166, 167, + 168, 169, 170, 171, 172, 173, 174, 67, 68, 15, + 0, 16, 0, 0, 0, 0, 70, 0, 0, 71, + 0, 0, 72, 0, 73, 0, 0, 0, 0, 0, + 53, 54, 69, 191, 56, 57, 58, 59, 60, 61, + 62, 63, 64, 65, 66, 67, 68, 15, 0, 16, + 0, 0, 0, 0, 70, 0, 0, 71, 0, 0, + 72, 0, 73, 0, 0, 0, 0, 0, 0, 0, + 69, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 69, - 0, 0, 70, 0, 0, 71, 0, 72, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 107, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 108, 0, - 0, 0, 0, 0, 0, 0, 0, 69, 109, 110, - 70, 0, 0, 71, 0, 72, 0, 111, 112, 113, - 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, - 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, - 0, 0, 134, 135, 136, 137, 138, 139, 140, 141, - 142, 143, 144, 145 + 0, 0, 70, 0, 0, 71, 0, 0, 72, 0, + 73, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 108, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 109, 0, 0, 0, 0, 0, 0, 0, 0, + 70, 110, 111, 71, 0, 0, 72, 0, 73, 0, + 0, 112, 113, 114, 115, 116, 117, 118, 119, 120, + 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, + 131, 132, 133, 134, 0, 0, 135, 136, 137, 138, + 139, 140, 141, 142, 143, 144, 145, 146 }; -static const short yycheck[] = { 29, - 113, 96, 113, 108, 207, 44, 111, 29, 23, 15, - 114, 2, 256, 34, 44, 30, 72, 247, 248, 15, - 103, 103, 9, 450, 111, 32, 33, 114, 133, 111, - 113, 136, 137, 54, 21, 140, 141, 142, 143, 144, - 145, 468, 33, 22, 149, 24, 276, 151, 54, 105, - 10, 11, 12, 13, 14, 15, 16, 17, 54, 61, - 62, 63, 64, 58, 20, 95, 103, 467, 10, 11, - 12, 13, 14, 15, 16, 17, 113, 477, 108, 102, - 105, 111, 23, 74, 103, 41, 42, 43, 44, 114, - 112, 47, 111, 103, 103, 49, 50, 51, 113, 109, - 109, 131, 132, 133, 134, 135, 136, 137, 52, 53, - 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, - 177, 226, 366, 179, 180, 181, 109, 88, 89, 58, - 187, 114, 27, 28, 102, 192, 193, 10, 11, 12, - 13, 14, 15, 16, 17, 3, 4, 204, 24, 109, - 3, 4, 209, 183, 3, 4, 3, 4, 3, 4, - 4, 107, 102, 220, 221, 222, 205, 109, 102, 102, - 105, 4, 24, 4, 4, 205, 4, 105, 24, 56, - 0, 108, 108, 105, 7, 224, 4, 390, 293, 392, - 295, 296, 297, 4, 224, 225, 226, 4, 303, 4, - 4, 7, 103, 106, 7, 25, 103, 103, 107, 265, - 103, 31, 36, 103, 103, 310, 311, 312, 313, 314, - 315, 41, 42, 43, 44, 103, 24, 284, 323, 324, - 325, 326, 103, 290, 103, 103, 103, 103, 103, 59, - 24, 105, 105, 105, 105, 105, 105, 304, 305, 105, - 105, 105, 60, 103, 105, 34, 24, 21, 106, 21, - 103, 103, 292, 293, 294, 295, 296, 297, 298, 299, - 261, 107, 4, 303, 103, 24, 103, 103, 373, 4, - 105, 103, 103, 36, 341, 54, 343, 103, 103, 103, - 347, 103, 397, 398, 399, 105, 4, 106, 24, 356, - 357, 358, 332, 103, 103, 107, 103, 103, 103, 103, - 103, 103, 103, 103, 344, 410, 411, 412, 413, 106, - 415, 416, 417, 418, 429, 103, 103, 103, 109, 103, - 387, 388, 362, 54, 106, 106, 106, 450, 395, 450, - 103, 106, 103, 21, 36, 21, 106, 404, 106, 106, - 109, 106, 106, 103, 106, 468, 21, 468, 103, 389, - 192, 193, 457, 69, 459, 460, 21, 397, 398, 399, - 21, 0, 204, 403, 431, 0, 33, 209, 20, 409, - 84, 84, 84, 20, 84, 22, 333, 24, 220, 221, - 222, 105, 177, 46, 31, 32, 33, 43, 2, 429, - 332, 23, 14, 403, 41, 42, 43, 44, 465, 367, - 47, 48, -1, 344, -1, -1, -1, -1, 55, -1, - -1, 478, 59, -1, -1, -1, -1, -1, 485, 5, - 6, -1, 489, 490, -1, -1, -1, -1, -1, -1, - -1, -1, -1, -1, -1, -1, 22, -1, 24, -1, - 26, -1, 284, -1, -1, -1, -1, -1, 290, -1, - -1, -1, 38, 39, -1, -1, -1, -1, -1, -1, - -1, -1, 304, 305, -1, -1, -1, -1, -1, -1, - -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, -1, -1, -1, 71, 72, 73, 74, 75, - 76, 77, 78, 79, 80, 81, 82, 83, 84, 341, - -1, 343, -1, -1, 90, 347, 92, 93, 94, 95, - -1, 97, 98, 99, 356, 357, 358, -1, -1, -1, - -1, 107, -1, -1, 110, -1, 112, -1, -1, 115, +static const short yycheck[] = { 30, + 114, 97, 114, 109, 208, 45, 112, 29, 23, 15, + 2, 451, 257, 34, 45, 30, 73, 248, 249, 15, + 104, 104, 115, 112, 104, 58, 115, 110, 134, 469, + 114, 137, 138, 54, 114, 141, 142, 143, 144, 145, + 146, 104, 34, 22, 150, 24, 277, 110, 54, 106, + 10, 11, 12, 13, 14, 15, 16, 17, 54, 152, + 23, 110, 103, 20, 9, 96, 115, 10, 11, 12, + 13, 14, 15, 16, 17, 58, 21, 103, 109, 468, + 24, 112, 4, 75, 41, 42, 43, 44, 106, 478, + 47, 113, 104, 49, 50, 51, 103, 115, 103, 114, + 112, 132, 133, 134, 135, 136, 137, 138, 32, 33, + 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, + 178, 227, 367, 180, 181, 182, 104, 52, 53, 103, + 188, 89, 90, 108, 112, 193, 194, 10, 11, 12, + 13, 14, 15, 16, 17, 27, 28, 205, 3, 4, + 110, 106, 210, 184, 61, 62, 63, 64, 65, 3, + 4, 3, 4, 221, 222, 223, 206, 110, 3, 4, + 4, 3, 4, 4, 4, 206, 106, 24, 4, 24, + 0, 109, 109, 106, 56, 225, 4, 391, 294, 393, + 296, 297, 298, 4, 225, 226, 227, 4, 304, 4, + 104, 7, 4, 7, 7, 25, 107, 104, 104, 266, + 108, 31, 104, 36, 104, 311, 312, 313, 314, 315, + 316, 41, 42, 43, 44, 104, 104, 285, 324, 325, + 326, 327, 24, 291, 104, 104, 104, 104, 104, 59, + 104, 106, 24, 106, 106, 106, 106, 305, 306, 106, + 106, 60, 106, 106, 106, 104, 107, 34, 104, 24, + 108, 104, 293, 294, 295, 296, 297, 298, 299, 300, + 262, 21, 21, 304, 4, 104, 104, 104, 374, 104, + 104, 24, 104, 4, 342, 106, 344, 104, 104, 104, + 348, 36, 398, 399, 400, 54, 106, 4, 24, 357, + 358, 359, 333, 104, 104, 104, 104, 104, 104, 104, + 104, 104, 54, 104, 345, 411, 412, 413, 414, 104, + 416, 417, 418, 419, 430, 104, 107, 107, 104, 107, + 388, 389, 363, 108, 107, 104, 110, 451, 396, 451, + 107, 104, 104, 107, 21, 36, 107, 405, 21, 107, + 107, 104, 107, 107, 110, 469, 107, 469, 21, 390, + 193, 194, 458, 104, 460, 461, 70, 398, 399, 400, + 21, 21, 205, 404, 432, 0, 0, 210, 34, 410, + 85, 20, 85, 85, 85, 334, 106, 47, 221, 222, + 223, 20, 178, 22, 333, 24, 44, 23, 2, 430, + 14, 404, 31, 32, 33, 345, 368, -1, 466, -1, + 5, 6, 41, 42, 43, 44, -1, -1, 47, 48, + -1, 479, -1, -1, -1, -1, 55, 22, 486, 24, + 59, 26, 490, 491, -1, -1, -1, -1, -1, -1, + -1, -1, -1, 38, 39, -1, -1, -1, -1, -1, + -1, -1, 285, -1, -1, -1, -1, -1, 291, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, -1, -1, -1, 387, 388, -1, -1, -1, - -1, -1, -1, 395, -1, -1, -1, -1, -1, -1, - 5, 6, 404, 8, 9, 10, 11, 12, 13, 14, - 15, 16, 17, 18, 19, 20, 21, 22, -1, 24, - -1, -1, -1, -1, -1, -1, -1, -1, -1, 431, - -1, -1, -1, -1, -1, -1, -1, -1, 5, 6, - 45, 8, 9, 10, 11, 12, 13, 14, 15, 16, + -1, -1, 305, 306, -1, -1, -1, 72, 73, 74, + 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, + 85, -1, -1, -1, -1, -1, 91, -1, 93, 94, + 95, 96, -1, 98, 99, 100, -1, -1, -1, 342, + -1, 344, -1, 108, -1, 348, 111, -1, 113, -1, + -1, 116, -1, -1, 357, 358, 359, -1, 5, 6, + -1, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, -1, 24, -1, -1, - -1, -1, -1, 465, -1, -1, -1, -1, -1, -1, - -1, -1, -1, -1, -1, -1, 478, -1, 45, -1, - -1, -1, -1, 485, -1, -1, -1, 489, 490, -1, - -1, -1, 3, 4, 5, 6, 7, -1, -1, 104, - -1, -1, 107, -1, -1, 110, -1, 112, 113, -1, - -1, 22, -1, 24, -1, 26, 27, 28, -1, -1, - -1, -1, -1, -1, -1, -1, -1, 38, 39, -1, - -1, -1, -1, -1, -1, -1, -1, 104, -1, -1, - 107, -1, -1, 110, -1, 112, 113, 58, -1, -1, - -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, - 81, 82, 83, 84, -1, -1, -1, -1, -1, 90, - -1, 92, 93, 94, 95, -1, 97, 98, 99, 3, - 4, -1, -1, 7, -1, -1, -1, -1, -1, 110, + -1, -1, -1, -1, -1, 388, 389, -1, -1, -1, + -1, -1, -1, 396, -1, -1, -1, -1, 45, -1, + 5, 6, 405, 8, 9, 10, 11, 12, 13, 14, + 15, 16, 17, 18, 19, 20, 21, 22, -1, 24, + -1, -1, -1, -1, -1, -1, -1, -1, -1, 432, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, 26, 27, 28, -1, -1, -1, -1, -1, - -1, -1, -1, -1, 38, 39, -1, -1, -1, -1, + 45, -1, -1, -1, -1, -1, -1, -1, -1, 3, + 4, 5, 6, 7, -1, -1, -1, -1, 105, -1, + -1, 108, -1, 466, 111, -1, 113, 114, 22, -1, + 24, -1, 26, 27, 28, -1, 479, -1, -1, -1, + -1, -1, -1, 486, 38, 39, -1, 490, 491, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, -1, -1, 58, -1, -1, -1, -1, -1, - -1, -1, -1, -1, -1, -1, -1, 71, 72, 73, + 105, -1, -1, 108, 58, -1, 111, -1, 113, 114, + -1, -1, -1, -1, -1, -1, -1, -1, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, - 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98, 99, 100, 101 + -1, -1, 105, -1, -1, 108, -1, -1, 111, -1, + 113, -1, -1, -1, -1, -1, -1, -1, -1, -1, + 35, -1, -1, -1, -1, -1, -1, -1, -1, -1, + -1, 46, -1, -1, -1, -1, -1, -1, -1, -1, + 105, 56, 57, 108, -1, -1, 111, -1, 113, -1, + -1, 66, 67, 68, 69, 70, 71, 72, 73, 74, + 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, + 85, 86, 87, 88, -1, -1, 91, 92, 93, 94, + 95, 96, 97, 98, 99, 100, 101, 102 }; /* -*-C-*- Note some compilers choke on comments on `#line' lines. */ #line 3 "/usr/share/bison.simple" @@ -2250,7 +2243,7 @@ switch (yyn) { case 2: -#line 1011 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1011 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (yyvsp[0].UIntVal > (uint32_t)INT32_MAX) // Outside of my range! ThrowException("Value too large for type!"); @@ -2258,7 +2251,7 @@ ; break;} case 4: -#line 1019 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1019 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (yyvsp[0].UInt64Val > (uint64_t)INT64_MAX) // Outside of my range! ThrowException("Value too large for type!"); @@ -2266,87 +2259,91 @@ ; break;} case 33: -#line 1042 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1042 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.StrVal = yyvsp[-1].StrVal; ; break;} case 34: -#line 1045 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1045 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.StrVal = 0; ; break;} case 35: -#line 1049 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1049 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.Linkage = GlobalValue::InternalLinkage; ; break;} case 36: -#line 1050 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1050 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.Linkage = GlobalValue::LinkOnceLinkage; ; break;} case 37: -#line 1051 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1051 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.Linkage = GlobalValue::WeakLinkage; ; break;} case 38: -#line 1052 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1052 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.Linkage = GlobalValue::AppendingLinkage; ; break;} case 39: -#line 1053 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1053 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.Linkage = GlobalValue::ExternalLinkage; ; break;} case 40: -#line 1055 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1055 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.UIntVal = CallingConv::C; ; break;} case 41: -#line 1056 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1056 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.UIntVal = CallingConv::C; ; break;} case 42: -#line 1057 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" -{ yyval.UIntVal = CallingConv::Fast; ; +#line 1057 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +{ yyval.UIntVal = CallingConv::CSRet; ; break;} case 43: -#line 1058 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" -{ yyval.UIntVal = CallingConv::Cold; ; +#line 1058 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +{ yyval.UIntVal = CallingConv::Fast; ; break;} case 44: -#line 1059 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1059 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +{ yyval.UIntVal = CallingConv::Cold; ; + break;} +case 45: +#line 1060 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if ((unsigned)yyvsp[0].UInt64Val != yyvsp[0].UInt64Val) ThrowException("Calling conv too large!"); yyval.UIntVal = yyvsp[0].UInt64Val; ; break;} -case 45: -#line 1067 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 46: +#line 1068 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.UIntVal = 0; ; break;} -case 46: -#line 1068 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 47: +#line 1069 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.UIntVal = yyvsp[0].UInt64Val; if (yyval.UIntVal != 0 && !isPowerOf2_32(yyval.UIntVal)) ThrowException("Alignment must be a power of two!"); ; break;} -case 47: -#line 1073 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 48: +#line 1074 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.UIntVal = 0; ; break;} -case 48: -#line 1074 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 49: +#line 1075 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.UIntVal = yyvsp[0].UInt64Val; if (yyval.UIntVal != 0 && !isPowerOf2_32(yyval.UIntVal)) ThrowException("Alignment must be a power of two!"); ; break;} -case 49: -#line 1081 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 50: +#line 1082 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { for (unsigned i = 0, e = strlen(yyvsp[0].StrVal); i != e; ++i) if (yyvsp[0].StrVal[i] == '"' || yyvsp[0].StrVal[i] == '\\') @@ -2354,73 +2351,73 @@ yyval.StrVal = yyvsp[0].StrVal; ; break;} -case 50: -#line 1088 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" -{ yyval.StrVal = 0; ; - break;} case 51: -#line 1089 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" -{ yyval.StrVal = yyvsp[0].StrVal; ; +#line 1089 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +{ yyval.StrVal = 0; ; break;} case 52: -#line 1094 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" -{; +#line 1090 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +{ yyval.StrVal = yyvsp[0].StrVal; ; break;} case 53: -#line 1095 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1095 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" {; break;} case 54: -#line 1096 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1096 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +{; + break;} +case 55: +#line 1097 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { CurGV->setSection(yyvsp[0].StrVal); free(yyvsp[0].StrVal); ; break;} -case 55: -#line 1100 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 56: +#line 1101 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (yyvsp[0].UInt64Val != 0 && !isPowerOf2_32(yyvsp[0].UInt64Val)) ThrowException("Alignment must be a power of two!"); CurGV->setAlignment(yyvsp[0].UInt64Val); ; break;} -case 57: -#line 1113 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 58: +#line 1114 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.TypeVal = new PATypeHolder(yyvsp[0].PrimType); ; break;} -case 59: -#line 1114 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 60: +#line 1115 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.TypeVal = new PATypeHolder(yyvsp[0].PrimType); ; break;} -case 60: -#line 1116 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 61: +#line 1117 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) ThrowException("Invalid upreference in type: " + (*yyvsp[0].TypeVal)->getDescription()); yyval.TypeVal = yyvsp[0].TypeVal; ; break;} -case 74: -#line 1127 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 75: +#line 1128 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.TypeVal = new PATypeHolder(OpaqueType::get()); ; break;} -case 75: -#line 1130 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 76: +#line 1131 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.TypeVal = new PATypeHolder(yyvsp[0].PrimType); ; break;} -case 76: -#line 1133 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 77: +#line 1134 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Named types are also simple types... yyval.TypeVal = new PATypeHolder(getTypeVal(yyvsp[0].ValIDVal)); ; break;} -case 77: -#line 1139 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 78: +#line 1140 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Type UpReference if (yyvsp[0].UInt64Val > (uint64_t)~0U) ThrowException("Value out of range!"); OpaqueType *OT = OpaqueType::get(); // Use temporary placeholder @@ -2429,8 +2426,8 @@ UR_OUT("New Upreference!\n"); ; break;} -case 78: -#line 1146 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 79: +#line 1147 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Function derived type? std::vector Params; for (std::list::iterator I = yyvsp[-1].TypeList->begin(), @@ -2444,15 +2441,15 @@ delete yyvsp[-3].TypeVal; // Delete the return type handle ; break;} -case 79: -#line 1158 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 80: +#line 1159 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Sized array type? yyval.TypeVal = new PATypeHolder(HandleUpRefs(ArrayType::get(*yyvsp[-1].TypeVal, (unsigned)yyvsp[-3].UInt64Val))); delete yyvsp[-1].TypeVal; ; break;} -case 80: -#line 1162 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 81: +#line 1163 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Packed array type? const llvm::Type* ElemTy = yyvsp[-1].TypeVal->get(); if ((unsigned)yyvsp[-3].UInt64Val != yyvsp[-3].UInt64Val) @@ -2465,8 +2462,8 @@ delete yyvsp[-1].TypeVal; ; break;} -case 81: -#line 1173 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 82: +#line 1174 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Structure type? std::vector Elements; for (std::list::iterator I = yyvsp[-1].TypeList->begin(), @@ -2477,52 +2474,52 @@ delete yyvsp[-1].TypeList; ; break;} -case 82: -#line 1182 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 83: +#line 1183 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Empty structure type? yyval.TypeVal = new PATypeHolder(StructType::get(std::vector())); ; break;} -case 83: -#line 1185 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 84: +#line 1186 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Pointer type? yyval.TypeVal = new PATypeHolder(HandleUpRefs(PointerType::get(*yyvsp[-1].TypeVal))); delete yyvsp[-1].TypeVal; ; break;} -case 84: -#line 1193 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 85: +#line 1194 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.TypeList = new std::list(); yyval.TypeList->push_back(*yyvsp[0].TypeVal); delete yyvsp[0].TypeVal; ; break;} -case 85: -#line 1197 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 86: +#line 1198 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.TypeList=yyvsp[-2].TypeList)->push_back(*yyvsp[0].TypeVal); delete yyvsp[0].TypeVal; ; break;} -case 87: -#line 1203 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 88: +#line 1204 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.TypeList=yyvsp[-2].TypeList)->push_back(Type::VoidTy); ; break;} -case 88: -#line 1206 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 89: +#line 1207 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.TypeList = new std::list())->push_back(Type::VoidTy); ; break;} -case 89: -#line 1209 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 90: +#line 1210 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.TypeList = new std::list(); ; break;} -case 90: -#line 1219 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 91: +#line 1220 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Nonempty unsized arr const ArrayType *ATy = dyn_cast(yyvsp[-3].TypeVal->get()); if (ATy == 0) @@ -2549,8 +2546,8 @@ delete yyvsp[-3].TypeVal; delete yyvsp[-1].ConstVector; ; break;} -case 91: -#line 1244 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 92: +#line 1245 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { const ArrayType *ATy = dyn_cast(yyvsp[-2].TypeVal->get()); if (ATy == 0) @@ -2565,8 +2562,8 @@ delete yyvsp[-2].TypeVal; ; break;} -case 92: -#line 1257 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 93: +#line 1258 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { const ArrayType *ATy = dyn_cast(yyvsp[-2].TypeVal->get()); if (ATy == 0) @@ -2597,8 +2594,8 @@ delete yyvsp[-2].TypeVal; ; break;} -case 93: -#line 1286 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 94: +#line 1287 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Nonempty unsized arr const PackedType *PTy = dyn_cast(yyvsp[-3].TypeVal->get()); if (PTy == 0) @@ -2625,8 +2622,8 @@ delete yyvsp[-3].TypeVal; delete yyvsp[-1].ConstVector; ; break;} -case 94: -#line 1311 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 95: +#line 1312 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { const StructType *STy = dyn_cast(yyvsp[-3].TypeVal->get()); if (STy == 0) @@ -2648,8 +2645,8 @@ delete yyvsp[-3].TypeVal; delete yyvsp[-1].ConstVector; ; break;} -case 95: -#line 1331 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 96: +#line 1332 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { const StructType *STy = dyn_cast(yyvsp[-2].TypeVal->get()); if (STy == 0) @@ -2663,8 +2660,8 @@ delete yyvsp[-2].TypeVal; ; break;} -case 96: -#line 1343 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 97: +#line 1344 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { const PointerType *PTy = dyn_cast(yyvsp[-1].TypeVal->get()); if (PTy == 0) @@ -2675,15 +2672,15 @@ delete yyvsp[-1].TypeVal; ; break;} -case 97: -#line 1352 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 98: +#line 1353 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ConstVal = UndefValue::get(yyvsp[-1].TypeVal->get()); delete yyvsp[-1].TypeVal; ; break;} -case 98: -#line 1356 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 99: +#line 1357 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { const PointerType *Ty = dyn_cast(yyvsp[-1].TypeVal->get()); if (Ty == 0) @@ -2744,8 +2741,8 @@ delete yyvsp[-1].TypeVal; // Free the type handle ; break;} -case 99: -#line 1415 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 100: +#line 1416 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (yyvsp[-1].TypeVal->get() != yyvsp[0].ConstVal->getType()) ThrowException("Mismatched types for constant expression!"); @@ -2753,8 +2750,8 @@ delete yyvsp[-1].TypeVal; ; break;} -case 100: -#line 1421 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 101: +#line 1422 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { const Type *Ty = yyvsp[-1].TypeVal->get(); if (isa(Ty) || Ty == Type::LabelTy || isa(Ty)) @@ -2763,44 +2760,44 @@ delete yyvsp[-1].TypeVal; ; break;} -case 101: -#line 1429 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 102: +#line 1430 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // integral constants if (!ConstantSInt::isValueValidForType(yyvsp[-1].PrimType, yyvsp[0].SInt64Val)) ThrowException("Constant value doesn't fit in type!"); yyval.ConstVal = ConstantSInt::get(yyvsp[-1].PrimType, yyvsp[0].SInt64Val); ; break;} -case 102: -#line 1434 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 103: +#line 1435 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // integral constants if (!ConstantUInt::isValueValidForType(yyvsp[-1].PrimType, yyvsp[0].UInt64Val)) ThrowException("Constant value doesn't fit in type!"); yyval.ConstVal = ConstantUInt::get(yyvsp[-1].PrimType, yyvsp[0].UInt64Val); ; break;} -case 103: -#line 1439 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 104: +#line 1440 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Boolean constants yyval.ConstVal = ConstantBool::True; ; break;} -case 104: -#line 1442 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 105: +#line 1443 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Boolean constants yyval.ConstVal = ConstantBool::False; ; break;} -case 105: -#line 1445 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 106: +#line 1446 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Float & Double constants if (!ConstantFP::isValueValidForType(yyvsp[-1].PrimType, yyvsp[0].FPVal)) ThrowException("Floating point constant invalid for type!!"); yyval.ConstVal = ConstantFP::get(yyvsp[-1].PrimType, yyvsp[0].FPVal); ; break;} -case 106: -#line 1452 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 107: +#line 1453 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (!yyvsp[-3].ConstVal->getType()->isFirstClassType()) ThrowException("cast constant expression from a non-primitive type: '" + @@ -2812,8 +2809,8 @@ delete yyvsp[-1].TypeVal; ; break;} -case 107: -#line 1462 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 108: +#line 1463 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (!isa(yyvsp[-2].ConstVal->getType())) ThrowException("GetElementPtr requires a pointer operand!"); @@ -2846,8 +2843,8 @@ yyval.ConstVal = ConstantExpr::getGetElementPtr(yyvsp[-2].ConstVal, IdxVec); ; break;} -case 108: -#line 1493 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 109: +#line 1494 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (yyvsp[-5].ConstVal->getType() != Type::BoolTy) ThrowException("Select condition must be of boolean type!"); @@ -2856,8 +2853,8 @@ yyval.ConstVal = ConstantExpr::getSelect(yyvsp[-5].ConstVal, yyvsp[-3].ConstVal, yyvsp[-1].ConstVal); ; break;} -case 109: -#line 1500 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 110: +#line 1501 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (yyvsp[-3].ConstVal->getType() != yyvsp[-1].ConstVal->getType()) ThrowException("Binary operator types must match!"); @@ -2880,8 +2877,8 @@ } ; break;} -case 110: -#line 1521 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 111: +#line 1522 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (yyvsp[-3].ConstVal->getType() != yyvsp[-1].ConstVal->getType()) ThrowException("Logical operator types must match!"); @@ -2893,16 +2890,16 @@ yyval.ConstVal = ConstantExpr::get(yyvsp[-5].BinaryOpVal, yyvsp[-3].ConstVal, yyvsp[-1].ConstVal); ; break;} -case 111: -#line 1531 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 112: +#line 1532 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (yyvsp[-3].ConstVal->getType() != yyvsp[-1].ConstVal->getType()) ThrowException("setcc operand types must match!"); yyval.ConstVal = ConstantExpr::get(yyvsp[-5].BinaryOpVal, yyvsp[-3].ConstVal, yyvsp[-1].ConstVal); ; break;} -case 112: -#line 1536 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 113: +#line 1537 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (yyvsp[-1].ConstVal->getType() != Type::UByteTy) ThrowException("Shift count for shift constant must be unsigned byte!"); @@ -2911,85 +2908,85 @@ yyval.ConstVal = ConstantExpr::get(yyvsp[-5].OtherOpVal, yyvsp[-3].ConstVal, yyvsp[-1].ConstVal); ; break;} -case 113: -#line 1543 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 114: +#line 1544 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (!ExtractElementInst::isValidOperands(yyvsp[-3].ConstVal, yyvsp[-1].ConstVal)) ThrowException("Invalid extractelement operands!"); yyval.ConstVal = ConstantExpr::getExtractElement(yyvsp[-3].ConstVal, yyvsp[-1].ConstVal); ; break;} -case 114: -#line 1548 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 115: +#line 1549 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (!InsertElementInst::isValidOperands(yyvsp[-5].ConstVal, yyvsp[-3].ConstVal, yyvsp[-1].ConstVal)) ThrowException("Invalid insertelement operands!"); yyval.ConstVal = ConstantExpr::getInsertElement(yyvsp[-5].ConstVal, yyvsp[-3].ConstVal, yyvsp[-1].ConstVal); ; break;} -case 115: -#line 1553 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 116: +#line 1554 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (!ShuffleVectorInst::isValidOperands(yyvsp[-5].ConstVal, yyvsp[-3].ConstVal, yyvsp[-1].ConstVal)) ThrowException("Invalid shufflevector operands!"); yyval.ConstVal = ConstantExpr::getShuffleVector(yyvsp[-5].ConstVal, yyvsp[-3].ConstVal, yyvsp[-1].ConstVal); ; break;} -case 116: -#line 1561 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 117: +#line 1562 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.ConstVector = yyvsp[-2].ConstVector)->push_back(yyvsp[0].ConstVal); ; break;} -case 117: -#line 1564 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 118: +#line 1565 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ConstVector = new std::vector(); yyval.ConstVector->push_back(yyvsp[0].ConstVal); ; break;} -case 118: -#line 1571 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 119: +#line 1572 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.BoolVal = false; ; break;} -case 119: -#line 1571 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 120: +#line 1572 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.BoolVal = true; ; break;} -case 120: -#line 1581 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 121: +#line 1582 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ModuleVal = ParserResult = yyvsp[0].ModuleVal; CurModule.ModuleDone(); ; break;} -case 121: -#line 1588 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 122: +#line 1589 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ModuleVal = yyvsp[-1].ModuleVal; CurFun.FunctionDone(); ; break;} -case 122: -#line 1592 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 123: +#line 1593 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ModuleVal = yyvsp[-1].ModuleVal; ; break;} -case 123: -#line 1595 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 124: +#line 1596 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ModuleVal = yyvsp[-3].ModuleVal; ; break;} -case 124: -#line 1598 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 125: +#line 1599 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ModuleVal = yyvsp[-1].ModuleVal; ; break;} -case 125: -#line 1601 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 126: +#line 1602 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ModuleVal = CurModule.CurrentModule; // Emit an error if there are any unresolved types left. @@ -3002,8 +2999,8 @@ } ; break;} -case 126: -#line 1614 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 127: +#line 1615 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Eagerly resolve types. This is not an optimization, this is a // requirement that is due to the fact that we could have this: @@ -3025,60 +3022,60 @@ delete yyvsp[0].TypeVal; ; break;} -case 127: -#line 1634 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 128: +#line 1635 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Function prototypes can be in const pool ; break;} -case 128: -#line 1636 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 129: +#line 1637 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Asm blocks can be in the const pool ; break;} -case 129: -#line 1638 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 130: +#line 1639 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (yyvsp[0].ConstVal == 0) ThrowException("Global value initializer is not a constant!"); CurGV = ParseGlobalVariable(yyvsp[-3].StrVal, yyvsp[-2].Linkage, yyvsp[-1].BoolVal, yyvsp[0].ConstVal->getType(), yyvsp[0].ConstVal); ; break;} -case 130: -#line 1641 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 131: +#line 1642 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { CurGV = 0; ; break;} -case 131: -#line 1644 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 132: +#line 1645 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { CurGV = ParseGlobalVariable(yyvsp[-3].StrVal, GlobalValue::ExternalLinkage, yyvsp[-1].BoolVal, *yyvsp[0].TypeVal, 0); delete yyvsp[0].TypeVal; ; break;} -case 132: -#line 1648 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 133: +#line 1649 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { CurGV = 0; ; break;} -case 133: -#line 1651 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 134: +#line 1652 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { ; break;} -case 134: -#line 1653 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 135: +#line 1654 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { ; break;} -case 135: -#line 1655 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 136: +#line 1656 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { ; break;} -case 136: -#line 1659 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 137: +#line 1660 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { const std::string &AsmSoFar = CurModule.CurrentModule->getModuleInlineAsm(); char *EndStr = UnEscapeLexed(yyvsp[0].StrVal, true); @@ -3091,22 +3088,22 @@ CurModule.CurrentModule->setModuleInlineAsm(AsmSoFar+"\n"+NewAsm); ; break;} -case 137: -#line 1671 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 138: +#line 1672 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.Endianness = Module::BigEndian; ; break;} -case 138: -#line 1672 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 139: +#line 1673 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.Endianness = Module::LittleEndian; ; break;} -case 139: -#line 1674 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 140: +#line 1675 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { CurModule.CurrentModule->setEndianness(yyvsp[0].Endianness); ; break;} -case 140: -#line 1677 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 141: +#line 1678 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (yyvsp[0].UInt64Val == 32) CurModule.CurrentModule->setPointerSize(Module::Pointer32); @@ -3116,89 +3113,89 @@ ThrowException("Invalid pointer size: '" + utostr(yyvsp[0].UInt64Val) + "'!"); ; break;} -case 141: -#line 1685 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 142: +#line 1686 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { CurModule.CurrentModule->setTargetTriple(yyvsp[0].StrVal); free(yyvsp[0].StrVal); ; break;} -case 143: -#line 1692 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 144: +#line 1693 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { CurModule.CurrentModule->addLibrary(yyvsp[0].StrVal); free(yyvsp[0].StrVal); ; break;} -case 144: -#line 1696 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 145: +#line 1697 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { CurModule.CurrentModule->addLibrary(yyvsp[0].StrVal); free(yyvsp[0].StrVal); ; break;} -case 145: -#line 1700 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 146: +#line 1701 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { ; break;} -case 149: -#line 1709 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 150: +#line 1710 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.StrVal = 0; ; break;} -case 150: -#line 1711 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 151: +#line 1712 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (*yyvsp[-1].TypeVal == Type::VoidTy) ThrowException("void typed arguments are invalid!"); yyval.ArgVal = new std::pair(yyvsp[-1].TypeVal, yyvsp[0].StrVal); ; break;} -case 151: -#line 1717 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 152: +#line 1718 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ArgList = yyvsp[-2].ArgList; yyvsp[-2].ArgList->push_back(*yyvsp[0].ArgVal); delete yyvsp[0].ArgVal; ; break;} -case 152: -#line 1722 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 153: +#line 1723 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ArgList = new std::vector >(); yyval.ArgList->push_back(*yyvsp[0].ArgVal); delete yyvsp[0].ArgVal; ; break;} -case 153: -#line 1728 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 154: +#line 1729 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ArgList = yyvsp[0].ArgList; ; break;} -case 154: -#line 1731 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 155: +#line 1732 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ArgList = yyvsp[-2].ArgList; yyval.ArgList->push_back(std::pair(new PATypeHolder(Type::VoidTy), 0)); ; break;} -case 155: -#line 1736 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 156: +#line 1737 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ArgList = new std::vector >(); yyval.ArgList->push_back(std::make_pair(new PATypeHolder(Type::VoidTy), (char*)0)); ; break;} -case 156: -#line 1740 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 157: +#line 1741 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ArgList = 0; ; break;} -case 157: -#line 1745 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 158: +#line 1746 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { UnEscapeLexed(yyvsp[-5].StrVal); std::string FunctionName(yyvsp[-5].StrVal); @@ -3284,8 +3281,8 @@ } ; break;} -case 160: -#line 1832 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 161: +#line 1833 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.FunctionVal = CurFun.CurrentFunction; @@ -3294,85 +3291,85 @@ yyval.FunctionVal->setLinkage(yyvsp[-2].Linkage); ; break;} -case 163: -#line 1842 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 164: +#line 1843 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.FunctionVal = yyvsp[-1].FunctionVal; ; break;} -case 164: -#line 1846 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 165: +#line 1847 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { CurFun.isDeclare = true; ; break;} -case 165: -#line 1846 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 166: +#line 1847 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.FunctionVal = CurFun.CurrentFunction; CurFun.FunctionDone(); ; break;} -case 166: -#line 1855 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 167: +#line 1856 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.BoolVal = false; ; break;} -case 167: -#line 1858 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 168: +#line 1859 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.BoolVal = true; ; break;} -case 168: -#line 1862 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 169: +#line 1863 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // A reference to a direct constant yyval.ValIDVal = ValID::create(yyvsp[0].SInt64Val); ; break;} -case 169: -#line 1865 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 170: +#line 1866 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ValIDVal = ValID::create(yyvsp[0].UInt64Val); ; break;} -case 170: -#line 1868 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 171: +#line 1869 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Perhaps it's an FP constant? yyval.ValIDVal = ValID::create(yyvsp[0].FPVal); ; break;} -case 171: -#line 1871 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 172: +#line 1872 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ValIDVal = ValID::create(ConstantBool::True); ; break;} -case 172: -#line 1874 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 173: +#line 1875 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ValIDVal = ValID::create(ConstantBool::False); ; break;} -case 173: -#line 1877 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 174: +#line 1878 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ValIDVal = ValID::createNull(); ; break;} -case 174: -#line 1880 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 175: +#line 1881 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ValIDVal = ValID::createUndef(); ; break;} -case 175: -#line 1883 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 176: +#line 1884 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // A vector zero constant. yyval.ValIDVal = ValID::createZeroInit(); ; break;} -case 176: -#line 1886 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 177: +#line 1887 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Nonempty unsized packed vector const Type *ETy = (*yyvsp[-1].ConstVector)[0]->getType(); int NumElements = yyvsp[-1].ConstVector->size(); @@ -3398,14 +3395,14 @@ delete PTy; delete yyvsp[-1].ConstVector; ; break;} -case 177: -#line 1910 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 178: +#line 1911 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ValIDVal = ValID::create(yyvsp[0].ConstVal); ; break;} -case 178: -#line 1913 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 179: +#line 1914 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { char *End = UnEscapeLexed(yyvsp[-2].StrVal, true); std::string AsmStr = std::string(yyvsp[-2].StrVal, End); @@ -3416,38 +3413,38 @@ free(yyvsp[0].StrVal); ; break;} -case 179: -#line 1926 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 180: +#line 1927 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Is it an integer reference...? yyval.ValIDVal = ValID::create(yyvsp[0].SIntVal); ; break;} -case 180: -#line 1929 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 181: +#line 1930 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Is it a named reference...? yyval.ValIDVal = ValID::create(yyvsp[0].StrVal); ; break;} -case 183: -#line 1940 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 184: +#line 1941 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ValueVal = getVal(*yyvsp[-1].TypeVal, yyvsp[0].ValIDVal); delete yyvsp[-1].TypeVal; ; break;} -case 184: -#line 1944 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 185: +#line 1945 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.FunctionVal = yyvsp[-1].FunctionVal; ; break;} -case 185: -#line 1947 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 186: +#line 1948 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Do not allow functions with 0 basic blocks yyval.FunctionVal = yyvsp[-1].FunctionVal; ; break;} -case 186: -#line 1955 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 187: +#line 1956 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { setValueName(yyvsp[0].TermInstVal, yyvsp[-1].StrVal); InsertValue(yyvsp[0].TermInstVal); @@ -3457,15 +3454,15 @@ yyval.BasicBlockVal = yyvsp[-2].BasicBlockVal; ; break;} -case 187: -#line 1964 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 188: +#line 1965 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyvsp[-1].BasicBlockVal->getInstList().push_back(yyvsp[0].InstVal); yyval.BasicBlockVal = yyvsp[-1].BasicBlockVal; ; break;} -case 188: -#line 1968 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 189: +#line 1969 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.BasicBlockVal = CurBB = getBBVal(ValID::create((int)CurFun.NextBBNum++), true); @@ -3477,8 +3474,8 @@ BBL.splice(BBL.end(), BBL, yyval.BasicBlockVal); ; break;} -case 189: -#line 1978 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 190: +#line 1979 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.BasicBlockVal = CurBB = getBBVal(ValID::create(yyvsp[0].StrVal), true); @@ -3490,32 +3487,32 @@ BBL.splice(BBL.end(), BBL, yyval.BasicBlockVal); ; break;} -case 190: -#line 1989 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 191: +#line 1990 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Return with a result... yyval.TermInstVal = new ReturnInst(yyvsp[0].ValueVal); ; break;} -case 191: -#line 1992 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 192: +#line 1993 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Return with no result... yyval.TermInstVal = new ReturnInst(); ; break;} -case 192: -#line 1995 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 193: +#line 1996 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Unconditional Branch... yyval.TermInstVal = new BranchInst(getBBVal(yyvsp[0].ValIDVal)); ; break;} -case 193: -#line 1998 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 194: +#line 1999 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.TermInstVal = new BranchInst(getBBVal(yyvsp[-3].ValIDVal), getBBVal(yyvsp[0].ValIDVal), getVal(Type::BoolTy, yyvsp[-6].ValIDVal)); ; break;} -case 194: -#line 2001 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 195: +#line 2002 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { SwitchInst *S = new SwitchInst(getVal(yyvsp[-7].PrimType, yyvsp[-6].ValIDVal), getBBVal(yyvsp[-3].ValIDVal), yyvsp[-1].JumpTable->size()); yyval.TermInstVal = S; @@ -3531,15 +3528,15 @@ delete yyvsp[-1].JumpTable; ; break;} -case 195: -#line 2015 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 196: +#line 2016 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { SwitchInst *S = new SwitchInst(getVal(yyvsp[-6].PrimType, yyvsp[-5].ValIDVal), getBBVal(yyvsp[-2].ValIDVal), 0); yyval.TermInstVal = S; ; break;} -case 196: -#line 2020 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 197: +#line 2021 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { const PointerType *PFTy; const FunctionType *Ty; @@ -3593,20 +3590,20 @@ delete yyvsp[-7].ValueList; ; break;} -case 197: -#line 2072 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 198: +#line 2073 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.TermInstVal = new UnwindInst(); ; break;} -case 198: -#line 2075 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 199: +#line 2076 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.TermInstVal = new UnreachableInst(); ; break;} -case 199: -#line 2081 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 200: +#line 2082 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.JumpTable = yyvsp[-5].JumpTable; Constant *V = cast(getValNonImprovising(yyvsp[-4].PrimType, yyvsp[-3].ValIDVal)); @@ -3616,8 +3613,8 @@ yyval.JumpTable->push_back(std::make_pair(V, getBBVal(yyvsp[0].ValIDVal))); ; break;} -case 200: -#line 2089 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 201: +#line 2090 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.JumpTable = new std::vector >(); Constant *V = cast(getValNonImprovising(yyvsp[-4].PrimType, yyvsp[-3].ValIDVal)); @@ -3628,8 +3625,8 @@ yyval.JumpTable->push_back(std::make_pair(V, getBBVal(yyvsp[0].ValIDVal))); ; break;} -case 201: -#line 2099 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 202: +#line 2100 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Is this definition named?? if so, assign the name... setValueName(yyvsp[0].InstVal, yyvsp[-1].StrVal); @@ -3637,54 +3634,54 @@ yyval.InstVal = yyvsp[0].InstVal; ; break;} -case 202: -#line 2106 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 203: +#line 2107 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Used for PHI nodes yyval.PHIList = new std::list >(); yyval.PHIList->push_back(std::make_pair(getVal(*yyvsp[-5].TypeVal, yyvsp[-3].ValIDVal), getBBVal(yyvsp[-1].ValIDVal))); delete yyvsp[-5].TypeVal; ; break;} -case 203: -#line 2111 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 204: +#line 2112 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.PHIList = yyvsp[-6].PHIList; yyvsp[-6].PHIList->push_back(std::make_pair(getVal(yyvsp[-6].PHIList->front().first->getType(), yyvsp[-3].ValIDVal), getBBVal(yyvsp[-1].ValIDVal))); ; break;} -case 204: -#line 2118 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 205: +#line 2119 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { // Used for call statements, and memory insts... yyval.ValueList = new std::vector(); yyval.ValueList->push_back(yyvsp[0].ValueVal); ; break;} -case 205: -#line 2122 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 206: +#line 2123 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ValueList = yyvsp[-2].ValueList; yyvsp[-2].ValueList->push_back(yyvsp[0].ValueVal); ; break;} -case 207: -#line 2128 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 208: +#line 2129 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ValueList = 0; ; break;} -case 208: -#line 2130 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 209: +#line 2131 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.BoolVal = true; ; break;} -case 209: -#line 2133 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 210: +#line 2134 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.BoolVal = false; ; break;} -case 210: -#line 2139 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 211: +#line 2140 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (!(*yyvsp[-3].TypeVal)->isInteger() && !(*yyvsp[-3].TypeVal)->isFloatingPoint() && !isa((*yyvsp[-3].TypeVal).get())) @@ -3698,8 +3695,8 @@ delete yyvsp[-3].TypeVal; ; break;} -case 211: -#line 2151 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 212: +#line 2152 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (!(*yyvsp[-3].TypeVal)->isIntegral()) { if (!isa(yyvsp[-3].TypeVal->get()) || @@ -3712,8 +3709,8 @@ delete yyvsp[-3].TypeVal; ; break;} -case 212: -#line 2162 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 213: +#line 2163 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if(isa((*yyvsp[-3].TypeVal).get())) { ThrowException( @@ -3725,8 +3722,8 @@ delete yyvsp[-3].TypeVal; ; break;} -case 213: -#line 2172 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 214: +#line 2173 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { std::cerr << "WARNING: Use of eliminated 'not' instruction:" << " Replacing with 'xor'.\n"; @@ -3740,8 +3737,8 @@ ThrowException("Could not create a xor instruction!"); ; break;} -case 214: -#line 2184 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 215: +#line 2185 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (yyvsp[0].ValueVal->getType() != Type::UByteTy) ThrowException("Shift amount must be ubyte!"); @@ -3750,8 +3747,8 @@ yyval.InstVal = new ShiftInst(yyvsp[-3].OtherOpVal, yyvsp[-2].ValueVal, yyvsp[0].ValueVal); ; break;} -case 215: -#line 2191 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 216: +#line 2192 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (!yyvsp[0].TypeVal->get()->isFirstClassType()) ThrowException("cast instruction to a non-primitive type: '" + @@ -3760,8 +3757,8 @@ delete yyvsp[0].TypeVal; ; break;} -case 216: -#line 2198 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 217: +#line 2199 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (yyvsp[-4].ValueVal->getType() != Type::BoolTy) ThrowException("select condition must be boolean!"); @@ -3770,16 +3767,16 @@ yyval.InstVal = new SelectInst(yyvsp[-4].ValueVal, yyvsp[-2].ValueVal, yyvsp[0].ValueVal); ; break;} -case 217: -#line 2205 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 218: +#line 2206 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { NewVarArgs = true; yyval.InstVal = new VAArgInst(yyvsp[-2].ValueVal, *yyvsp[0].TypeVal); delete yyvsp[0].TypeVal; ; break;} -case 218: -#line 2210 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 219: +#line 2211 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { ObsoleteVarArgs = true; const Type* ArgTy = yyvsp[-2].ValueVal->getType(); @@ -3800,8 +3797,8 @@ delete yyvsp[0].TypeVal; ; break;} -case 219: -#line 2229 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 220: +#line 2230 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { ObsoleteVarArgs = true; const Type* ArgTy = yyvsp[-2].ValueVal->getType(); @@ -3825,32 +3822,32 @@ delete yyvsp[0].TypeVal; ; break;} -case 220: -#line 2251 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 221: +#line 2252 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (!ExtractElementInst::isValidOperands(yyvsp[-2].ValueVal, yyvsp[0].ValueVal)) ThrowException("Invalid extractelement operands!"); yyval.InstVal = new ExtractElementInst(yyvsp[-2].ValueVal, yyvsp[0].ValueVal); ; break;} -case 221: -#line 2256 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 222: +#line 2257 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (!InsertElementInst::isValidOperands(yyvsp[-4].ValueVal, yyvsp[-2].ValueVal, yyvsp[0].ValueVal)) ThrowException("Invalid insertelement operands!"); yyval.InstVal = new InsertElementInst(yyvsp[-4].ValueVal, yyvsp[-2].ValueVal, yyvsp[0].ValueVal); ; break;} -case 222: -#line 2261 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 223: +#line 2262 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (!ShuffleVectorInst::isValidOperands(yyvsp[-4].ValueVal, yyvsp[-2].ValueVal, yyvsp[0].ValueVal)) ThrowException("Invalid shufflevector operands!"); yyval.InstVal = new ShuffleVectorInst(yyvsp[-4].ValueVal, yyvsp[-2].ValueVal, yyvsp[0].ValueVal); ; break;} -case 223: -#line 2266 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 224: +#line 2267 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { const Type *Ty = yyvsp[0].PHIList->front().first->getType(); if (!Ty->isFirstClassType()) @@ -3866,8 +3863,8 @@ delete yyvsp[0].PHIList; // Free the list... ; break;} -case 224: -#line 2280 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 225: +#line 2281 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { const PointerType *PFTy; const FunctionType *Ty; @@ -3926,66 +3923,66 @@ delete yyvsp[-1].ValueList; ; break;} -case 225: -#line 2337 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 226: +#line 2338 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.InstVal = yyvsp[0].InstVal; ; break;} -case 226: -#line 2343 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 227: +#line 2344 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ValueList = yyvsp[0].ValueList; ; break;} -case 227: -#line 2345 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 228: +#line 2346 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.ValueList = new std::vector(); ; break;} -case 228: -#line 2349 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 229: +#line 2350 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.BoolVal = true; ; break;} -case 229: -#line 2352 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 230: +#line 2353 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.BoolVal = false; ; break;} -case 230: -#line 2358 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 231: +#line 2359 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.InstVal = new MallocInst(*yyvsp[-1].TypeVal, 0, yyvsp[0].UIntVal); delete yyvsp[-1].TypeVal; ; break;} -case 231: -#line 2362 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 232: +#line 2363 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.InstVal = new MallocInst(*yyvsp[-4].TypeVal, getVal(yyvsp[-2].PrimType, yyvsp[-1].ValIDVal), yyvsp[0].UIntVal); delete yyvsp[-4].TypeVal; ; break;} -case 232: -#line 2366 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 233: +#line 2367 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.InstVal = new AllocaInst(*yyvsp[-1].TypeVal, 0, yyvsp[0].UIntVal); delete yyvsp[-1].TypeVal; ; break;} -case 233: -#line 2370 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 234: +#line 2371 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { yyval.InstVal = new AllocaInst(*yyvsp[-4].TypeVal, getVal(yyvsp[-2].PrimType, yyvsp[-1].ValIDVal), yyvsp[0].UIntVal); delete yyvsp[-4].TypeVal; ; break;} -case 234: -#line 2374 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 235: +#line 2375 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (!isa(yyvsp[0].ValueVal->getType())) ThrowException("Trying to free nonpointer type " + @@ -3993,8 +3990,8 @@ yyval.InstVal = new FreeInst(yyvsp[0].ValueVal); ; break;} -case 235: -#line 2381 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 236: +#line 2382 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (!isa(yyvsp[-1].TypeVal->get())) ThrowException("Can't load from nonpointer type: " + @@ -4006,8 +4003,8 @@ delete yyvsp[-1].TypeVal; ; break;} -case 236: -#line 2391 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 237: +#line 2392 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { const PointerType *PT = dyn_cast(yyvsp[-1].TypeVal->get()); if (!PT) @@ -4022,8 +4019,8 @@ delete yyvsp[-1].TypeVal; ; break;} -case 237: -#line 2404 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +case 238: +#line 2405 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" { if (!isa(yyvsp[-2].TypeVal->get())) ThrowException("getelementptr insn requires pointer operand!"); @@ -4268,7 +4265,7 @@ } return 1; } -#line 2427 "/Users/sabre/cvs/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2428 "/Volumes/Projects/cvs/llvm/lib/AsmParser/llvmAsmParser.y" int yyerror(const char *ErrorMsg) { std::string where Index: llvm/lib/AsmParser/llvmAsmParser.h.cvs diff -u llvm/lib/AsmParser/llvmAsmParser.h.cvs:1.2 llvm/lib/AsmParser/llvmAsmParser.h.cvs:1.3 --- llvm/lib/AsmParser/llvmAsmParser.h.cvs:1.2 Fri Apr 7 20:18:56 2006 +++ llvm/lib/AsmParser/llvmAsmParser.h.cvs Fri May 19 16:28:53 2006 @@ -97,45 +97,46 @@ #define SIDEEFFECT 314 #define CC_TOK 315 #define CCC_TOK 316 -#define FASTCC_TOK 317 -#define COLDCC_TOK 318 -#define RET 319 -#define BR 320 -#define SWITCH 321 -#define INVOKE 322 -#define UNWIND 323 -#define UNREACHABLE 324 -#define ADD 325 -#define SUB 326 -#define MUL 327 -#define DIV 328 -#define REM 329 -#define AND 330 -#define OR 331 -#define XOR 332 -#define SETLE 333 -#define SETGE 334 -#define SETLT 335 -#define SETGT 336 -#define SETEQ 337 -#define SETNE 338 -#define MALLOC 339 -#define ALLOCA 340 -#define FREE 341 -#define LOAD 342 -#define STORE 343 -#define GETELEMENTPTR 344 -#define PHI_TOK 345 -#define CAST 346 -#define SELECT 347 -#define SHL 348 -#define SHR 349 -#define VAARG 350 -#define EXTRACTELEMENT 351 -#define INSERTELEMENT 352 -#define SHUFFLEVECTOR 353 -#define VAARG_old 354 -#define VANEXT_old 355 +#define CSRETCC_TOK 317 +#define FASTCC_TOK 318 +#define COLDCC_TOK 319 +#define RET 320 +#define BR 321 +#define SWITCH 322 +#define INVOKE 323 +#define UNWIND 324 +#define UNREACHABLE 325 +#define ADD 326 +#define SUB 327 +#define MUL 328 +#define DIV 329 +#define REM 330 +#define AND 331 +#define OR 332 +#define XOR 333 +#define SETLE 334 +#define SETGE 335 +#define SETLT 336 +#define SETGT 337 +#define SETEQ 338 +#define SETNE 339 +#define MALLOC 340 +#define ALLOCA 341 +#define FREE 342 +#define LOAD 343 +#define STORE 344 +#define GETELEMENTPTR 345 +#define PHI_TOK 346 +#define CAST 347 +#define SELECT 348 +#define SHL 349 +#define SHR 350 +#define VAARG 351 +#define EXTRACTELEMENT 352 +#define INSERTELEMENT 353 +#define SHUFFLEVECTOR 354 +#define VAARG_old 355 +#define VANEXT_old 356 extern YYSTYPE llvmAsmlval; Index: llvm/lib/AsmParser/llvmAsmParser.y.cvs diff -u llvm/lib/AsmParser/llvmAsmParser.y.cvs:1.5 llvm/lib/AsmParser/llvmAsmParser.y.cvs:1.6 --- llvm/lib/AsmParser/llvmAsmParser.y.cvs:1.5 Fri Apr 7 23:09:02 2006 +++ llvm/lib/AsmParser/llvmAsmParser.y.cvs Fri May 19 16:28:53 2006 @@ -981,7 +981,7 @@ %token TO DOTDOTDOT NULL_TOK UNDEF CONST INTERNAL LINKONCE WEAK APPENDING %token OPAQUE NOT EXTERNAL TARGET TRIPLE ENDIAN POINTERSIZE LITTLE BIG ALIGN %token DEPLIBS CALL TAIL ASM_TOK MODULE SIDEEFFECT -%token CC_TOK CCC_TOK FASTCC_TOK COLDCC_TOK +%token CC_TOK CCC_TOK CSRETCC_TOK FASTCC_TOK COLDCC_TOK %type OptCallingConv // Basic Block Terminating Operators @@ -1054,6 +1054,7 @@ OptCallingConv : /*empty*/ { $$ = CallingConv::C; } | CCC_TOK { $$ = CallingConv::C; } | + CSRETCC_TOK { $$ = CallingConv::CSRet; } | FASTCC_TOK { $$ = CallingConv::Fast; } | COLDCC_TOK { $$ = CallingConv::Cold; } | CC_TOK EUINT64VAL { From lattner at cs.uiuc.edu Fri May 19 16:30:09 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 19 May 2006 16:30:09 -0500 Subject: [llvm-commits] CVS: llvm/lib/VMCore/AsmWriter.cpp Message-ID: <200605192130.QAA02689@zion.cs.uiuc.edu> Changes in directory llvm/lib/VMCore: AsmWriter.cpp updated: 1.198 -> 1.199 --- Log message: Asmprint csret nicely --- Diffs of the changes: (+1 -0) AsmWriter.cpp | 1 + 1 files changed, 1 insertion(+) Index: llvm/lib/VMCore/AsmWriter.cpp diff -u llvm/lib/VMCore/AsmWriter.cpp:1.198 llvm/lib/VMCore/AsmWriter.cpp:1.199 --- llvm/lib/VMCore/AsmWriter.cpp:1.198 Sun May 14 13:46:52 2006 +++ llvm/lib/VMCore/AsmWriter.cpp Fri May 19 16:29:57 2006 @@ -953,6 +953,7 @@ // Print the calling convention. switch (F->getCallingConv()) { case CallingConv::C: break; // default + case CallingConv::CSRet: Out << "csretcc "; break; case CallingConv::Fast: Out << "fastcc "; break; case CallingConv::Cold: Out << "coldcc "; break; default: Out << "cc" << F->getCallingConv() << " "; break; From lattner at cs.uiuc.edu Fri May 19 16:34:16 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 19 May 2006 16:34:16 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp Message-ID: <200605192134.QAA02821@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.206 -> 1.207 --- Log message: CSRet allows varargs --- Diffs of the changes: (+3 -2) X86ISelLowering.cpp | 5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.206 llvm/lib/Target/X86/X86ISelLowering.cpp:1.207 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.206 Wed May 17 14:07:40 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Fri May 19 16:34:04 2006 @@ -380,8 +380,9 @@ bool isTailCall, SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG) { - assert((!isVarArg || CallingConv == CallingConv::C) && - "Only C takes varargs!"); + assert((!isVarArg || CallingConv == CallingConv::C || + CallingConv == CallingConv::CSRet) && + "Only CCC/CSRet takes varargs!"); // If the callee is a GlobalAddress node (quite common, every direct call is) // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. From lattner at cs.uiuc.edu Fri May 19 16:54:15 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 19 May 2006 16:54:15 -0500 Subject: [llvm-commits] CVS: llvm/lib/VMCore/AsmWriter.cpp Message-ID: <200605192154.QAA02930@zion.cs.uiuc.edu> Changes in directory llvm/lib/VMCore: AsmWriter.cpp updated: 1.199 -> 1.200 --- Log message: pretty print csretcc for calls --- Diffs of the changes: (+2 -0) AsmWriter.cpp | 2 ++ 1 files changed, 2 insertions(+) Index: llvm/lib/VMCore/AsmWriter.cpp diff -u llvm/lib/VMCore/AsmWriter.cpp:1.199 llvm/lib/VMCore/AsmWriter.cpp:1.200 --- llvm/lib/VMCore/AsmWriter.cpp:1.199 Fri May 19 16:29:57 2006 +++ llvm/lib/VMCore/AsmWriter.cpp Fri May 19 16:54:03 2006 @@ -1143,6 +1143,7 @@ // Print the calling convention being used. switch (CI->getCallingConv()) { case CallingConv::C: break; // default + case CallingConv::CSRet: Out << "csretcc "; break; case CallingConv::Fast: Out << " fastcc"; break; case CallingConv::Cold: Out << " coldcc"; break; default: Out << " cc" << CI->getCallingConv(); break; @@ -1180,6 +1181,7 @@ // Print the calling convention being used. switch (II->getCallingConv()) { case CallingConv::C: break; // default + case CallingConv::CSRet: Out << "csretcc "; break; case CallingConv::Fast: Out << " fastcc"; break; case CallingConv::Cold: Out << " coldcc"; break; default: Out << " cc" << II->getCallingConv(); break; From lattner at cs.uiuc.edu Fri May 19 16:57:50 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 19 May 2006 16:57:50 -0500 Subject: [llvm-commits] CVS: llvm/lib/Bytecode/Writer/Writer.cpp Message-ID: <200605192157.QAA02987@zion.cs.uiuc.edu> Changes in directory llvm/lib/Bytecode/Writer: Writer.cpp updated: 1.119 -> 1.120 --- Log message: Fix misencoding of calling conventions --- Diffs of the changes: (+3 -2) Writer.cpp | 5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) Index: llvm/lib/Bytecode/Writer/Writer.cpp diff -u llvm/lib/Bytecode/Writer/Writer.cpp:1.119 llvm/lib/Bytecode/Writer/Writer.cpp:1.120 --- llvm/lib/Bytecode/Writer/Writer.cpp:1.119 Wed Jan 25 17:08:15 2006 +++ llvm/lib/Bytecode/Writer/Writer.cpp Fri May 19 16:57:37 2006 @@ -734,8 +734,9 @@ // If this is the escape sequence for call, emit the tailcall/cc info. const CallInst &CI = cast(I); ++NumOperands; - if (NumOperands < 3) { - Slots[NumOperands-1] = (CI.getCallingConv() << 1)|unsigned(CI.isTailCall()); + if (NumOperands <= 3) { + Slots[NumOperands-1] = + (CI.getCallingConv() << 1)|unsigned(CI.isTailCall()); if (Slots[NumOperands-1] > MaxOpSlot) MaxOpSlot = Slots[NumOperands-1]; } From lattner at cs.uiuc.edu Fri May 19 16:59:05 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 19 May 2006 16:59:05 -0500 Subject: [llvm-commits] CVS: llvm/lib/VMCore/AsmWriter.cpp Message-ID: <200605192159.QAA03036@zion.cs.uiuc.edu> Changes in directory llvm/lib/VMCore: AsmWriter.cpp updated: 1.200 -> 1.201 --- Log message: Print csretcc calls like this: call csretcc void %structret( { sbyte }* %P ) instead of this: callcsretcc void %structret( { sbyte }* %P ) --- Diffs of the changes: (+8 -8) AsmWriter.cpp | 16 ++++++++-------- 1 files changed, 8 insertions(+), 8 deletions(-) Index: llvm/lib/VMCore/AsmWriter.cpp diff -u llvm/lib/VMCore/AsmWriter.cpp:1.200 llvm/lib/VMCore/AsmWriter.cpp:1.201 --- llvm/lib/VMCore/AsmWriter.cpp:1.200 Fri May 19 16:54:03 2006 +++ llvm/lib/VMCore/AsmWriter.cpp Fri May 19 16:58:52 2006 @@ -954,8 +954,8 @@ switch (F->getCallingConv()) { case CallingConv::C: break; // default case CallingConv::CSRet: Out << "csretcc "; break; - case CallingConv::Fast: Out << "fastcc "; break; - case CallingConv::Cold: Out << "coldcc "; break; + case CallingConv::Fast: Out << "fastcc "; break; + case CallingConv::Cold: Out << "coldcc "; break; default: Out << "cc" << F->getCallingConv() << " "; break; } @@ -1143,9 +1143,9 @@ // Print the calling convention being used. switch (CI->getCallingConv()) { case CallingConv::C: break; // default - case CallingConv::CSRet: Out << "csretcc "; break; - case CallingConv::Fast: Out << " fastcc"; break; - case CallingConv::Cold: Out << " coldcc"; break; + case CallingConv::CSRet: Out << " csretcc"; break; + case CallingConv::Fast: Out << " fastcc"; break; + case CallingConv::Cold: Out << " coldcc"; break; default: Out << " cc" << CI->getCallingConv(); break; } @@ -1181,9 +1181,9 @@ // Print the calling convention being used. switch (II->getCallingConv()) { case CallingConv::C: break; // default - case CallingConv::CSRet: Out << "csretcc "; break; - case CallingConv::Fast: Out << " fastcc"; break; - case CallingConv::Cold: Out << " coldcc"; break; + case CallingConv::CSRet: Out << " csretcc"; break; + case CallingConv::Fast: Out << " fastcc"; break; + case CallingConv::Cold: Out << " coldcc"; break; default: Out << " cc" << II->getCallingConv(); break; } From lattner at cs.uiuc.edu Fri May 19 17:01:06 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Fri, 19 May 2006 17:01:06 -0500 Subject: [llvm-commits] CVS: llvm/test/Feature/callingconventions.ll Message-ID: <200605192201.RAA03195@zion.cs.uiuc.edu> Changes in directory llvm/test/Feature: callingconventions.ll updated: 1.1 -> 1.2 --- Log message: new testcase for csretcc --- Diffs of the changes: (+5 -0) callingconventions.ll | 5 +++++ 1 files changed, 5 insertions(+) Index: llvm/test/Feature/callingconventions.ll diff -u llvm/test/Feature/callingconventions.ll:1.1 llvm/test/Feature/callingconventions.ll:1.2 --- llvm/test/Feature/callingconventions.ll:1.1 Fri May 6 17:33:44 2005 +++ llvm/test/Feature/callingconventions.ll Fri May 19 17:00:54 2006 @@ -11,6 +11,11 @@ ret void } +csretcc void %structret({sbyte}* %P) { + call csretcc void %structret({sbyte}* %P) + ret void +} + cc0 void %foo2() { ret void From resistor at mac.com Fri May 19 19:25:12 2006 From: resistor at mac.com (Owen Anderson) Date: Fri, 19 May 2006 19:25:12 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/ARM/ARMTargetMachine.cpp Message-ID: <200605200025.TAA04042@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/ARM: ARMTargetMachine.cpp updated: 1.1 -> 1.2 --- Log message: Make all of the TargetMachine subclasses use the new string TargetData methods. This is part of the on-going work on PR 761: http://llvm.cs.uiuc.edu/PR761 . --- Diffs of the changes: (+1 -1) ARMTargetMachine.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/ARM/ARMTargetMachine.cpp diff -u llvm/lib/Target/ARM/ARMTargetMachine.cpp:1.1 llvm/lib/Target/ARM/ARMTargetMachine.cpp:1.2 --- llvm/lib/Target/ARM/ARMTargetMachine.cpp:1.1 Sun May 14 17:18:28 2006 +++ llvm/lib/Target/ARM/ARMTargetMachine.cpp Fri May 19 19:24:56 2006 @@ -33,7 +33,7 @@ /// ARMTargetMachine::ARMTargetMachine(const Module &M, const std::string &FS) : TargetMachine("ARM"), - DataLayout("ARM", false, 4, 4), + DataLayout(std::string("ARM"), std::string("E-p:32:32")), InstrInfo(), FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0) { } From resistor at mac.com Fri May 19 19:25:13 2006 From: resistor at mac.com (Owen Anderson) Date: Fri, 19 May 2006 19:25:13 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/TargetData.cpp Message-ID: <200605200025.TAA04048@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target: TargetData.cpp updated: 1.65 -> 1.66 --- Log message: Make all of the TargetMachine subclasses use the new string TargetData methods. This is part of the on-going work on PR 761: http://llvm.cs.uiuc.edu/PR761 . --- Diffs of the changes: (+5 -1) TargetData.cpp | 6 +++++- 1 files changed, 5 insertions(+), 1 deletion(-) Index: llvm/lib/Target/TargetData.cpp diff -u llvm/lib/Target/TargetData.cpp:1.65 llvm/lib/Target/TargetData.cpp:1.66 --- llvm/lib/Target/TargetData.cpp:1.65 Wed May 17 16:56:02 2006 +++ llvm/lib/Target/TargetData.cpp Fri May 19 19:24:56 2006 @@ -123,6 +123,10 @@ TargetData::TargetData(const std::string &TargetName, const std::string &TargetDescription) { + assert(!TargetName.empty() && + "ERROR: Tool did not specify a target data to use!"); + + std::string temp = TargetDescription; LittleEndian = false; @@ -136,7 +140,7 @@ ByteAlignment = 1; BoolAlignment = 1; - while (temp.length() > 0) { + while (!temp.empty()) { std::string token = getToken(temp, "-"); char signal = getToken(token, ":")[0]; From resistor at mac.com Fri May 19 19:25:13 2006 From: resistor at mac.com (Owen Anderson) Date: Fri, 19 May 2006 19:25:13 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/IA64/IA64TargetMachine.cpp Message-ID: <200605200025.TAA04046@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/IA64: IA64TargetMachine.cpp updated: 1.15 -> 1.16 --- Log message: Make all of the TargetMachine subclasses use the new string TargetData methods. This is part of the on-going work on PR 761: http://llvm.cs.uiuc.edu/PR761 . --- Diffs of the changes: (+1 -1) IA64TargetMachine.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/IA64/IA64TargetMachine.cpp diff -u llvm/lib/Target/IA64/IA64TargetMachine.cpp:1.15 llvm/lib/Target/IA64/IA64TargetMachine.cpp:1.16 --- llvm/lib/Target/IA64/IA64TargetMachine.cpp:1.15 Tue May 2 20:29:57 2006 +++ llvm/lib/Target/IA64/IA64TargetMachine.cpp Fri May 19 19:24:56 2006 @@ -76,7 +76,7 @@ /// IA64TargetMachine ctor - Create an LP64 architecture model /// IA64TargetMachine::IA64TargetMachine(const Module &M, const std::string &FS) - : TargetMachine("IA64"), DataLayout("IA64", true), + : TargetMachine("IA64"), DataLayout(std::string("IA64"), std::string("e")), FrameInfo(TargetFrameInfo::StackGrowsDown, 16, 0), TLInfo(*this) { // FIXME? check this stuff } From resistor at mac.com Fri May 19 19:25:14 2006 From: resistor at mac.com (Owen Anderson) Date: Fri, 19 May 2006 19:25:14 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCTargetMachine.cpp Message-ID: <200605200025.TAA04058@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCTargetMachine.cpp updated: 1.89 -> 1.90 --- Log message: Make all of the TargetMachine subclasses use the new string TargetData methods. This is part of the on-going work on PR 761: http://llvm.cs.uiuc.edu/PR761 . --- Diffs of the changes: (+1 -1) PPCTargetMachine.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/PowerPC/PPCTargetMachine.cpp diff -u llvm/lib/Target/PowerPC/PPCTargetMachine.cpp:1.89 llvm/lib/Target/PowerPC/PPCTargetMachine.cpp:1.90 --- llvm/lib/Target/PowerPC/PPCTargetMachine.cpp:1.89 Tue May 2 20:29:57 2006 +++ llvm/lib/Target/PowerPC/PPCTargetMachine.cpp Fri May 19 19:24:56 2006 @@ -59,7 +59,7 @@ PPCTargetMachine::PPCTargetMachine(const Module &M, const std::string &FS) : TargetMachine("PowerPC"), - DataLayout("PowerPC", false, 4, 4, 4, 4, 4), + DataLayout(std::string("PowerPC"), std::string("E-p:32:32-d:64:32-l:64:32")), Subtarget(M, FS), FrameInfo(*this, false), JITInfo(*this), TLInfo(*this), InstrItins(Subtarget.getInstrItineraryData()) { if (TargetDefault == PPCTarget) { From resistor at mac.com Fri May 19 19:25:14 2006 From: resistor at mac.com (Owen Anderson) Date: Fri, 19 May 2006 19:25:14 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86TargetMachine.cpp Message-ID: <200605200025.TAA04066@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86TargetMachine.cpp updated: 1.113 -> 1.114 --- Log message: Make all of the TargetMachine subclasses use the new string TargetData methods. This is part of the on-going work on PR 761: http://llvm.cs.uiuc.edu/PR761 . --- Diffs of the changes: (+1 -1) X86TargetMachine.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/X86/X86TargetMachine.cpp diff -u llvm/lib/Target/X86/X86TargetMachine.cpp:1.113 llvm/lib/Target/X86/X86TargetMachine.cpp:1.114 --- llvm/lib/Target/X86/X86TargetMachine.cpp:1.113 Tue May 2 20:29:57 2006 +++ llvm/lib/Target/X86/X86TargetMachine.cpp Fri May 19 19:24:56 2006 @@ -69,7 +69,7 @@ /// X86TargetMachine::X86TargetMachine(const Module &M, const std::string &FS) : TargetMachine("X86"), - DataLayout("X86", true, 4, 4, 4, 4, 4), + DataLayout(std::string("X86"), std::string("e-p:32:32-d:64:32-l:64:32")), Subtarget(M, FS), FrameInfo(TargetFrameInfo::StackGrowsDown, Subtarget.getStackAlignment(), -4), From resistor at mac.com Fri May 19 19:25:13 2006 From: resistor at mac.com (Owen Anderson) Date: Fri, 19 May 2006 19:25:13 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcTargetMachine.cpp Message-ID: <200605200025.TAA04054@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Sparc: SparcTargetMachine.cpp updated: 1.45 -> 1.46 --- Log message: Make all of the TargetMachine subclasses use the new string TargetData methods. This is part of the on-going work on PR 761: http://llvm.cs.uiuc.edu/PR761 . --- Diffs of the changes: (+1 -1) SparcTargetMachine.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/Sparc/SparcTargetMachine.cpp diff -u llvm/lib/Target/Sparc/SparcTargetMachine.cpp:1.45 llvm/lib/Target/Sparc/SparcTargetMachine.cpp:1.46 --- llvm/lib/Target/Sparc/SparcTargetMachine.cpp:1.45 Tue May 2 20:29:57 2006 +++ llvm/lib/Target/Sparc/SparcTargetMachine.cpp Fri May 19 19:24:56 2006 @@ -32,7 +32,7 @@ /// SparcTargetMachine::SparcTargetMachine(const Module &M, const std::string &FS) : TargetMachine("Sparc"), - DataLayout("Sparc", false, 4, 4), + DataLayout(std::string("Sparc"), std::string("e-p:32:32")), Subtarget(M, FS), InstrInfo(Subtarget), FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0) { } From resistor at mac.com Fri May 19 19:25:14 2006 From: resistor at mac.com (Owen Anderson) Date: Fri, 19 May 2006 19:25:14 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaTargetMachine.cpp Message-ID: <200605200025.TAA04062@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Alpha: AlphaTargetMachine.cpp updated: 1.24 -> 1.25 --- Log message: Make all of the TargetMachine subclasses use the new string TargetData methods. This is part of the on-going work on PR 761: http://llvm.cs.uiuc.edu/PR761 . --- Diffs of the changes: (+1 -1) AlphaTargetMachine.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/Alpha/AlphaTargetMachine.cpp diff -u llvm/lib/Target/Alpha/AlphaTargetMachine.cpp:1.24 llvm/lib/Target/Alpha/AlphaTargetMachine.cpp:1.25 --- llvm/lib/Target/Alpha/AlphaTargetMachine.cpp:1.24 Tue May 2 20:29:57 2006 +++ llvm/lib/Target/Alpha/AlphaTargetMachine.cpp Fri May 19 19:24:56 2006 @@ -55,7 +55,7 @@ AlphaTargetMachine::AlphaTargetMachine(const Module &M, const std::string &FS) : TargetMachine("alpha"), - DataLayout("alpha", true), + DataLayout(std::string("alpha"), std::string("e")), FrameInfo(TargetFrameInfo::StackGrowsDown, 16, 0), JITInfo(*this), Subtarget(M, FS) From resistor at mac.com Fri May 19 19:49:42 2006 From: resistor at mac.com (Owen Anderson) Date: Fri, 19 May 2006 19:49:42 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcTargetMachine.cpp Message-ID: <200605200049.TAA04161@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Sparc: SparcTargetMachine.cpp updated: 1.46 -> 1.47 --- Log message: Sparc is big-endian. --- Diffs of the changes: (+1 -1) SparcTargetMachine.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/Sparc/SparcTargetMachine.cpp diff -u llvm/lib/Target/Sparc/SparcTargetMachine.cpp:1.46 llvm/lib/Target/Sparc/SparcTargetMachine.cpp:1.47 --- llvm/lib/Target/Sparc/SparcTargetMachine.cpp:1.46 Fri May 19 19:24:56 2006 +++ llvm/lib/Target/Sparc/SparcTargetMachine.cpp Fri May 19 19:49:30 2006 @@ -32,7 +32,7 @@ /// SparcTargetMachine::SparcTargetMachine(const Module &M, const std::string &FS) : TargetMachine("Sparc"), - DataLayout(std::string("Sparc"), std::string("e-p:32:32")), + DataLayout(std::string("Sparc"), std::string("E-p:32:32")), Subtarget(M, FS), InstrInfo(Subtarget), FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0) { } From evan.cheng at apple.com Fri May 19 20:37:04 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 19 May 2006 20:37:04 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Message-ID: <200605200137.UAA04324@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ISelDAGToDAG.cpp updated: 1.61 -> 1.62 --- Log message: Handle indirect call which folds a load manually. This never matches by the TableGen generated code since the load's chain result is read by the callseq_start node. --- Diffs of the changes: (+58 -0) X86ISelDAGToDAG.cpp | 58 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 58 insertions(+) Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.61 llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.62 --- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.61 Tue May 16 02:21:53 2006 +++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Fri May 19 20:36:52 2006 @@ -516,6 +516,13 @@ return CurDAG->getRegister(GlobalBaseReg, MVT::i32); } +static SDNode *FindCallStartFromCall(SDNode *Node) { + if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; + assert(Node->getOperand(0).getValueType() == MVT::Other && + "Node doesn't have a token chain argument!"); + return FindCallStartFromCall(Node->getOperand(0).Val); +} + void X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) { SDNode *Node = N.Val; MVT::ValueType NVT = Node->getValueType(0); @@ -826,6 +833,57 @@ return; } } + + case X86ISD::CALL: { + // Handle indirect call which folds a load here. This never matches by + // the TableGen generated code since the load's chain result is read by + // the callseq_start node. + SDOperand N1 = Node->getOperand(1); + if (N1.getOpcode() == ISD::LOAD && N1.hasOneUse() && + !CodeGenMap.count(N1.getValue(0))) { + SDOperand Chain = Node->getOperand(0); + SDNode *CallStart = FindCallStartFromCall(Chain.Val); + if (!CallStart || CallStart->getOperand(0).Val != N1.Val) + break; + SDOperand Base, Scale, Index, Disp; + if (SelectAddr(N1.getOperand(1), Base, Scale, Index, Disp)) { + Select(Base, Base); + Select(Scale, Scale); + Select(Index, Index); + Select(Disp, Disp); + Select(Chain, Chain); + bool HasOptInFlag = false; + SDOperand InFlag; + if (N.getNumOperands() == 3) { + Select(InFlag, N.getOperand(2)); + HasOptInFlag = true; + } + SDNode *ResNode; + if (HasOptInFlag) + ResNode = CurDAG->getTargetNode(X86::CALL32m, MVT::Other, MVT::Flag, + Base, Scale, Index, Disp, Chain, + InFlag); + else + ResNode = CurDAG->getTargetNode(X86::CALL32m, MVT::Other, MVT::Flag, + Base, Scale, Index, Disp, Chain); + + SelectionDAG::InsertISelMapEntry(CodeGenMap, N.Val, 0, Chain.Val, + Chain.ResNo); + SelectionDAG::InsertISelMapEntry(CodeGenMap, N1.Val, 1, ResNode, 0); + SelectionDAG::InsertISelMapEntry(CodeGenMap, N.Val, 1, ResNode, 1); + Result = SDOperand(ResNode, 0); + +#ifndef NDEBUG + DEBUG(std::cerr << std::string(Indent-2, ' ')); + DEBUG(std::cerr << "== "); + DEBUG(Result.Val->dump(CurDAG)); + DEBUG(std::cerr << "\n"); + Indent -= 2; +#endif + return; + } + } + } } SelectCode(Result, N); From evan.cheng at apple.com Fri May 19 20:40:28 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 19 May 2006 20:40:28 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp X86InstrInfo.td Message-ID: <200605200140.UAA04380@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ISelDAGToDAG.cpp updated: 1.62 -> 1.63 X86InstrInfo.td updated: 1.270 -> 1.271 --- Log message: Remove unused patterns. --- Diffs of the changes: (+4 -7) X86ISelDAGToDAG.cpp | 3 ++- X86InstrInfo.td | 8 ++------ 2 files changed, 4 insertions(+), 7 deletions(-) Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.62 llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.63 --- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.62 Fri May 19 20:36:52 2006 +++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Fri May 19 20:40:16 2006 @@ -834,7 +834,8 @@ } } - case X86ISD::CALL: { + case X86ISD::CALL: + case X86ISD::TAILCALL: { // Handle indirect call which folds a load here. This never matches by // the TableGen generated code since the load's chain result is read by // the callseq_start node. Index: llvm/lib/Target/X86/X86InstrInfo.td diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.270 llvm/lib/Target/X86/X86InstrInfo.td:1.271 --- llvm/lib/Target/X86/X86InstrInfo.td:1.270 Fri May 19 13:40:54 2006 +++ llvm/lib/Target/X86/X86InstrInfo.td Fri May 19 20:40:16 2006 @@ -75,7 +75,7 @@ def X86call : SDNode<"X86ISD::CALL", SDT_X86Call, [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>; -def X86tailcall : SDNode<"X86ISD::TAILCALL", SDT_X86Call, +def X86tailcall: SDNode<"X86ISD::TAILCALL", SDT_X86Call, [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>; def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr, @@ -442,8 +442,7 @@ []>; def CALL32r : I<0xFF, MRM2r, (ops GR32:$dst), "call {*}$dst", [(X86call GR32:$dst)]>; - def CALL32m : I<0xFF, MRM2m, (ops i32mem:$dst), "call {*}$dst", - [(X86call (loadiPTR addr:$dst))]>; + def CALL32m : I<0xFF, MRM2m, (ops i32mem:$dst), "call {*}$dst", []>; } // Tail call stuff. @@ -2370,9 +2369,6 @@ def : Pat<(X86tailcall GR32:$dst), (CALL32r GR32:$dst)>; -def : Pat<(X86tailcall (loadiPTR addr:$dst)), - (CALL32m addr:$dst)>; - def : Pat<(X86tailcall tglobaladdr:$dst), (CALLpcrel32 tglobaladdr:$dst)>; def : Pat<(X86tailcall texternalsym:$dst), From evan.cheng at apple.com Sat May 20 02:44:40 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Sat, 20 May 2006 02:44:40 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Message-ID: <200605200744.CAA15146@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ISelDAGToDAG.cpp updated: 1.63 -> 1.64 --- Log message: Missing break statements. --- Diffs of the changes: (+3 -0) X86ISelDAGToDAG.cpp | 3 +++ 1 files changed, 3 insertions(+) Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.63 llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.64 --- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.63 Fri May 19 20:40:16 2006 +++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Sat May 20 02:44:28 2006 @@ -832,6 +832,8 @@ #endif return; } + + break; } case X86ISD::CALL: @@ -884,6 +886,7 @@ return; } } + break; } } From evan.cheng at apple.com Sat May 20 02:45:05 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Sat, 20 May 2006 02:45:05 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/README.txt Message-ID: <200605200745.CAA15177@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: README.txt updated: 1.111 -> 1.112 --- Log message: A new entry --- Diffs of the changes: (+10 -0) README.txt | 10 ++++++++++ 1 files changed, 10 insertions(+) Index: llvm/lib/Target/X86/README.txt diff -u llvm/lib/Target/X86/README.txt:1.111 llvm/lib/Target/X86/README.txt:1.112 --- llvm/lib/Target/X86/README.txt:1.111 Fri May 19 15:55:31 2006 +++ llvm/lib/Target/X86/README.txt Sat May 20 02:44:53 2006 @@ -577,3 +577,13 @@ //===---------------------------------------------------------------------===// +Some ideas for instruction selection code simplification: 1. A pre-pass to +determine which chain producing node can or cannot be folded. The generated +isel code would then use the information. 2. The same pre-pass can force +ordering of TokenFactor operands to allow load / store folding. 3. During isel, +instead of recursively going up the chain operand chain, mark the chain operand +as available and put it in some work list. Select other nodes in the normal +manner. The chain operands are selected after all other nodes are selected. Uses +of chain nodes are modified after instruction selection is completed. + + From evan.cheng at apple.com Sat May 20 04:22:20 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Sat, 20 May 2006 04:22:20 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Message-ID: <200605200922.EAA12606@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ISelDAGToDAG.cpp updated: 1.64 -> 1.65 --- Log message: - Use of load's chain result should be redirected to load's chain operand. If it reads the chain result of the call, then the use, callseq_start, and call would form a cycle! - Don't forget handle node replacement! - There could also be a TokenFactor between the load and the callseq_start. --- Diffs of the changes: (+13 -3) X86ISelDAGToDAG.cpp | 16 +++++++++++++--- 1 files changed, 13 insertions(+), 3 deletions(-) Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.64 llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.65 --- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.64 Sat May 20 02:44:28 2006 +++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Sat May 20 04:21:39 2006 @@ -840,13 +840,18 @@ case X86ISD::TAILCALL: { // Handle indirect call which folds a load here. This never matches by // the TableGen generated code since the load's chain result is read by - // the callseq_start node. + // the callseq_start node or by a TokenFactor which feeds into the + // callseq_start. SDOperand N1 = Node->getOperand(1); if (N1.getOpcode() == ISD::LOAD && N1.hasOneUse() && !CodeGenMap.count(N1.getValue(0))) { SDOperand Chain = Node->getOperand(0); SDNode *CallStart = FindCallStartFromCall(Chain.Val); - if (!CallStart || CallStart->getOperand(0).Val != N1.Val) + if (!CallStart) break; + SDNode *CSOp0 = CallStart->getOperand(0).Val; + if (! (CSOp0 == N1.Val || + (CSOp0->getOpcode() == ISD::TokenFactor && + N1.Val->isOperand(CSOp0)))) break; SDOperand Base, Scale, Index, Disp; if (SelectAddr(N1.getOperand(1), Base, Scale, Index, Disp)) { @@ -872,8 +877,13 @@ SelectionDAG::InsertISelMapEntry(CodeGenMap, N.Val, 0, Chain.Val, Chain.ResNo); - SelectionDAG::InsertISelMapEntry(CodeGenMap, N1.Val, 1, ResNode, 0); SelectionDAG::InsertISelMapEntry(CodeGenMap, N.Val, 1, ResNode, 1); + // CALLSEQ_START needs a chain! It can't be ResNode, that would cause + // a cycle. It should be the chain of the load. + Select(Chain, N1.getOperand(0)); + SelectionDAG::InsertISelMapEntry(CodeGenMap, N1.Val, 1, Chain.Val, + Chain.ResNo); + AddHandleReplacement(N1.Val, 1, Chain.Val, Chain.ResNo); Result = SDOperand(ResNode, 0); #ifndef NDEBUG From lattner at cs.uiuc.edu Sat May 20 16:17:11 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 20 May 2006 16:17:11 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/TargetData.cpp Message-ID: <200605202117.QAA17793@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target: TargetData.cpp updated: 1.66 -> 1.67 --- Log message: Fix a parsing bug that caused 7 llvm-test regressions on PPC last night. I'm suprised it didn't cause more! --- Diffs of the changes: (+7 -7) TargetData.cpp | 14 +++++++------- 1 files changed, 7 insertions(+), 7 deletions(-) Index: llvm/lib/Target/TargetData.cpp diff -u llvm/lib/Target/TargetData.cpp:1.66 llvm/lib/Target/TargetData.cpp:1.67 --- llvm/lib/Target/TargetData.cpp:1.66 Fri May 19 19:24:56 2006 +++ llvm/lib/Target/TargetData.cpp Sat May 20 16:16:59 2006 @@ -157,31 +157,31 @@ PointerAlignment = atoi(getToken(token,":").c_str()) / 8; break; case 'd': - token = getToken(token,":"); //Ignore the size + getToken(token,":"); //Ignore the size DoubleAlignment = atoi(getToken(token,":").c_str()) / 8; break; case 'f': - token = getToken(token, ":"); //Ignore the size + getToken(token, ":"); //Ignore the size FloatAlignment = atoi(getToken(token, ":").c_str()) / 8; break; case 'l': - token = getToken(token, ":"); //Ignore the size + getToken(token, ":"); //Ignore the size LongAlignment = atoi(getToken(token, ":").c_str()) / 8; break; case 'i': - token = getToken(token, ":"); //Ignore the size + getToken(token, ":"); //Ignore the size IntAlignment = atoi(getToken(token, ":").c_str()) / 8; break; case 's': - token = getToken(token, ":"); //Ignore the size + getToken(token, ":"); //Ignore the size ShortAlignment = atoi(getToken(token, ":").c_str()) / 8; break; case 'b': - token = getToken(token, ":"); //Ignore the size + getToken(token, ":"); //Ignore the size ByteAlignment = atoi(getToken(token, ":").c_str()) / 8; break; case 'B': - token = getToken(token, ":"); //Ignore the size + getToken(token, ":"); //Ignore the size BoolAlignment = atoi(getToken(token, ":").c_str()) / 8; break; default: From lattner at cs.uiuc.edu Sat May 20 18:14:16 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 20 May 2006 18:14:16 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp Message-ID: <200605202314.SAA18116@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: InstructionCombining.cpp updated: 1.482 -> 1.483 --- Log message: Silence a bogus gcc warning --- Diffs of the changes: (+1 -1) InstructionCombining.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.482 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.483 --- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.482 Sun May 14 01:46:03 2006 +++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Sat May 20 18:14:03 2006 @@ -4822,7 +4822,7 @@ // Otherwise, it must be an instruction. Instruction *I = cast(V); - Instruction *Res; + Instruction *Res = 0; switch (I->getOpcode()) { case Instruction::And: case Instruction::Or: From resistor at mac.com Sat May 20 18:29:07 2006 From: resistor at mac.com (Owen Anderson) Date: Sat, 20 May 2006 18:29:07 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/TargetData.cpp Message-ID: <200605202329.SAA18191@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target: TargetData.cpp updated: 1.67 -> 1.68 --- Log message: Make TargetData strings less redundant. --- Diffs of the changes: (+0 -7) TargetData.cpp | 7 ------- 1 files changed, 7 deletions(-) Index: llvm/lib/Target/TargetData.cpp diff -u llvm/lib/Target/TargetData.cpp:1.67 llvm/lib/Target/TargetData.cpp:1.68 --- llvm/lib/Target/TargetData.cpp:1.67 Sat May 20 16:16:59 2006 +++ llvm/lib/Target/TargetData.cpp Sat May 20 18:28:54 2006 @@ -157,31 +157,24 @@ PointerAlignment = atoi(getToken(token,":").c_str()) / 8; break; case 'd': - getToken(token,":"); //Ignore the size DoubleAlignment = atoi(getToken(token,":").c_str()) / 8; break; case 'f': - getToken(token, ":"); //Ignore the size FloatAlignment = atoi(getToken(token, ":").c_str()) / 8; break; case 'l': - getToken(token, ":"); //Ignore the size LongAlignment = atoi(getToken(token, ":").c_str()) / 8; break; case 'i': - getToken(token, ":"); //Ignore the size IntAlignment = atoi(getToken(token, ":").c_str()) / 8; break; case 's': - getToken(token, ":"); //Ignore the size ShortAlignment = atoi(getToken(token, ":").c_str()) / 8; break; case 'b': - getToken(token, ":"); //Ignore the size ByteAlignment = atoi(getToken(token, ":").c_str()) / 8; break; case 'B': - getToken(token, ":"); //Ignore the size BoolAlignment = atoi(getToken(token, ":").c_str()) / 8; break; default: From resistor at mac.com Sat May 20 18:29:08 2006 From: resistor at mac.com (Owen Anderson) Date: Sat, 20 May 2006 18:29:08 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86TargetMachine.cpp Message-ID: <200605202329.SAA18195@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86TargetMachine.cpp updated: 1.114 -> 1.115 --- Log message: Make TargetData strings less redundant. --- Diffs of the changes: (+1 -1) X86TargetMachine.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/X86/X86TargetMachine.cpp diff -u llvm/lib/Target/X86/X86TargetMachine.cpp:1.114 llvm/lib/Target/X86/X86TargetMachine.cpp:1.115 --- llvm/lib/Target/X86/X86TargetMachine.cpp:1.114 Fri May 19 19:24:56 2006 +++ llvm/lib/Target/X86/X86TargetMachine.cpp Sat May 20 18:28:54 2006 @@ -69,7 +69,7 @@ /// X86TargetMachine::X86TargetMachine(const Module &M, const std::string &FS) : TargetMachine("X86"), - DataLayout(std::string("X86"), std::string("e-p:32:32-d:64:32-l:64:32")), + DataLayout(std::string("X86"), std::string("e-p:32:32-d:32-l:32")), Subtarget(M, FS), FrameInfo(TargetFrameInfo::StackGrowsDown, Subtarget.getStackAlignment(), -4), From resistor at mac.com Sat May 20 18:29:08 2006 From: resistor at mac.com (Owen Anderson) Date: Sat, 20 May 2006 18:29:08 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCTargetMachine.cpp Message-ID: <200605202329.SAA18199@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCTargetMachine.cpp updated: 1.90 -> 1.91 --- Log message: Make TargetData strings less redundant. --- Diffs of the changes: (+1 -1) PPCTargetMachine.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/PowerPC/PPCTargetMachine.cpp diff -u llvm/lib/Target/PowerPC/PPCTargetMachine.cpp:1.90 llvm/lib/Target/PowerPC/PPCTargetMachine.cpp:1.91 --- llvm/lib/Target/PowerPC/PPCTargetMachine.cpp:1.90 Fri May 19 19:24:56 2006 +++ llvm/lib/Target/PowerPC/PPCTargetMachine.cpp Sat May 20 18:28:54 2006 @@ -59,7 +59,7 @@ PPCTargetMachine::PPCTargetMachine(const Module &M, const std::string &FS) : TargetMachine("PowerPC"), - DataLayout(std::string("PowerPC"), std::string("E-p:32:32-d:64:32-l:64:32")), + DataLayout(std::string("PowerPC"), std::string("E-p:32:32-d:32-l:32")), Subtarget(M, FS), FrameInfo(*this, false), JITInfo(*this), TLInfo(*this), InstrItins(Subtarget.getInstrItineraryData()) { if (TargetDefault == PPCTarget) { From resistor at mac.com Sat May 20 18:29:09 2006 From: resistor at mac.com (Owen Anderson) Date: Sat, 20 May 2006 18:29:09 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetData.h Message-ID: <200605202329.SAA18203@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/Target: TargetData.h updated: 1.37 -> 1.38 --- Log message: Make TargetData strings less redundant. --- Diffs of the changes: (+1 -1) TargetData.h | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/include/llvm/Target/TargetData.h diff -u llvm/include/llvm/Target/TargetData.h:1.37 llvm/include/llvm/Target/TargetData.h:1.38 --- llvm/include/llvm/Target/TargetData.h:1.37 Fri May 12 02:01:44 2006 +++ llvm/include/llvm/Target/TargetData.h Sat May 20 18:28:54 2006 @@ -54,7 +54,7 @@ unsigned char ByteAl = 1, unsigned char BoolAl = 1); /// Constructs a TargetData from a string of the following format: - /// "E-p:64:64-d:64:64-f:32:32-l:64:64-i:32:32-s:16:16-b:8:8-B:8:8" + /// "E-p:64:64-d:64-f:32-l:64-i:32-s:16-b:8-B:8" /// The above string is considered the default, and any values not specified /// in the string will be assumed to be as above. TargetData(const std::string &TargetName, From lattner at cs.uiuc.edu Sat May 20 22:57:19 2006 From: lattner at cs.uiuc.edu (Chris Lattner) Date: Sat, 20 May 2006 22:57:19 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/README.txt Message-ID: <200605210357.WAA19069@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target: README.txt updated: 1.32 -> 1.33 --- Log message: Add a note --- Diffs of the changes: (+12 -0) README.txt | 12 ++++++++++++ 1 files changed, 12 insertions(+) Index: llvm/lib/Target/README.txt diff -u llvm/lib/Target/README.txt:1.32 llvm/lib/Target/README.txt:1.33 --- llvm/lib/Target/README.txt:1.32 Fri May 19 16:01:38 2006 +++ llvm/lib/Target/README.txt Sat May 20 22:57:07 2006 @@ -239,3 +239,15 @@ it should be extended to do so. //===---------------------------------------------------------------------===// + +Turn this into a single byte store with no load (the other 3 bytes are +unmodified): + +void %test(uint* %P) { + %tmp = load uint* %P + %tmp14 = or uint %tmp, 3305111552 + %tmp15 = and uint %tmp14, 3321888767 + store uint %tmp15, uint* %P + ret void +} + From evan.cheng at apple.com Sun May 21 01:29:03 2006 From: evan.cheng at apple.com (Evan Cheng) Date: Sun, 21 May 2006 01:29:03 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Message-ID: <200605210629.BAA19573@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ISelDAGToDAG.cpp updated: 1.65 -> 1.66 --- Log message: Back out indirect branch load folding hack. It broke some tests. --- Diffs of the changes: (+0 -63) X86ISelDAGToDAG.cpp | 63 ---------------------------------------------------- 1 files changed, 63 deletions(-) Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.65 llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.66 --- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.65 Sat May 20 04:21:39 2006 +++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Sun May 21 01:28:50 2006 @@ -835,69 +835,6 @@ break; } - - case X86ISD::CALL: - case X86ISD::TAILCALL: { - // Handle indirect call which folds a load here. This never matches by - // the TableGen generated code since the load's chain result is read by - // the callseq_start node or by a TokenFactor which feeds into the - // callseq_start. - SDOperand N1 = Node->getOperand(1); - if (N1.getOpcode() == ISD::LOAD && N1.hasOneUse() && - !CodeGenMap.count(N1.getValue(0))) { - SDOperand Chain = Node->getOperand(0); - SDNode *CallStart = FindCallStartFromCall(Chain.Val); - if (!CallStart) break; - SDNode *CSOp0 = CallStart->getOperand(0).Val; - if (! (CSOp0 == N1.Val || - (CSOp0->getOpcode() == ISD::TokenFactor && - N1.Val->isOperand(CSOp0)))) - break; - SDOperand Base, Scale, Index, Disp; - if (SelectAddr(N1.getOperand(1), Base, Scale, Index, Disp)) { - Select(Base, Base); - Select(Scale, Scale); - Select(Index, Index); - Select(Disp, Disp); - Select(Chain, Chain); - bool HasOptInFlag = false; - SDOperand InFlag; - if (N.getNumOperands() == 3) { - Select(InFlag, N.getOperand(2)); - HasOptInFlag = true; - } - SDNode *ResNode; - if (HasOptInFlag) - ResNode = CurDAG->getTargetNode(X86::CALL32m, MVT::Other, MVT::Flag, - Base, Scale, Index, Disp, Chain, - InFlag); - else - ResNode = CurDAG->getTargetNode(X86::CALL32m, MVT::Other, MVT::Flag, - Base, Scale, Index, Disp, Chain); - - SelectionDAG::InsertISelMapEntry(CodeGenMap, N.Val, 0, Chain.Val, - Chain.ResNo); - SelectionDAG::InsertISelMapEntry(CodeGenMap, N.Val, 1, ResNode, 1); - // CALLSEQ_START needs a chain! It can't be ResNode, that would cause - // a cycle. It should be the chain of the load. - Select(Chain, N1.getOperand(0)); - SelectionDAG::InsertISelMapEntry(CodeGenMap, N1.Val, 1, Chain.Val, - Chain.ResNo); - AddHandleReplacement(N1.Val, 1, Chain.Val, Chain.ResNo); - Result = SDOperand(ResNode, 0); - -#ifndef NDEBUG - DEBUG(std::cerr << std::string(Indent-2, ' ')); - DEBUG(std::cerr << "== "); - DEBUG(Result.Val->dump(CurDAG)); - DEBUG(std::cerr << "\n"); - Indent -= 2; -#endif - return; - } - } - break; - } } SelectCode(Result, N); From reid at x10sys.com Sun May 21 05:40:45 2006 From: reid at x10sys.com (Reid Spencer) Date: Sun, 21 May 2006 05:40:45 -0500 Subject: [llvm-commits] CVS: llvm/autoconf/configure.ac Message-ID: <200605211040.FAA03343@zion.cs.uiuc.edu> Changes in directory llvm/autoconf: configure.ac updated: 1.226 -> 1.227 --- Log message: For PR784: http://llvm.cs.uiuc.edu/PR784 : Support Win32 platforms for llvm-gcc path. Patch by Anton Korobeynikov --- Diffs of the changes: (+1 -1) configure.ac | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/autoconf/configure.ac diff -u llvm/autoconf/configure.ac:1.226 llvm/autoconf/configure.ac:1.227 --- llvm/autoconf/configure.ac:1.226 Tue May 16 03:53:32 2006 +++ llvm/autoconf/configure.ac Sun May 21 05:40:20 2006 @@ -320,7 +320,7 @@ withval=default) case "$withval" in default) WITH_LLVMGCCDIR=default ;; - /*) WITH_LLVMGCCDIR=$withval ;; + /* | [[A-Za-z]]:[[\\/]]*) WITH_LLVMGCCDIR=$withval ;; *) AC_MSG_ERROR([Invalid path for --with-llvmgccdir. Provide full path]) ;; esac From reid at x10sys.com Sun May 21 05:40:45 2006 From: reid at x10sys.com (Reid Spencer) Date: Sun, 21 May 2006 05:40:45 -0500 Subject: [llvm-commits] CVS: llvm/configure Message-ID: <200605211040.FAA03344@zion.cs.uiuc.edu> Changes in directory llvm: configure updated: 1.229 -> 1.230 --- Log message: For PR784: http://llvm.cs.uiuc.edu/PR784 : Support Win32 platforms for llvm-gcc path. Patch by Anton Korobeynikov --- Diffs of the changes: (+1 -1) configure | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/configure diff -u llvm/configure:1.229 llvm/configure:1.230 --- llvm/configure:1.229 Tue May 16 03:53:32 2006 +++ llvm/configure Sun May 21 05:40:20 2006 @@ -3150,7 +3150,7 @@ fi; case "$withval" in default) WITH_LLVMGCCDIR=default ;; - /*) WITH_LLVMGCCDIR=$withval ;; + /* | [A-Za-z]:[\\/]*) WITH_LLVMGCCDIR=$withval ;; *) { { echo "$as_me:$LINENO: error: Invalid path for --with-llvmgccdir. Provide full path" >&5 echo "$as_me: error: Invalid path for --with-llvmgccdir. Provide full path" >&2;} { (exit 1); exit 1; }; } ;;