From lattner at cs.uiuc.edu  Mon Sep  4 00:23:34 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 4 Sep 2006 00:23:34 -0500
Subject: [llvm-commits] CVS: llvm/Makefile.rules
Message-ID: <200609040523.k845NYpT014482@zion.cs.uiuc.edu>



Changes in directory llvm:

Makefile.rules updated: 1.402 -> 1.403
---
Log message:

Bugfix for llvm-config support


---
Diffs of the changes:  (+16 -13)

 Makefile.rules |   29 ++++++++++++++++-------------
 1 files changed, 16 insertions(+), 13 deletions(-)


Index: llvm/Makefile.rules
diff -u llvm/Makefile.rules:1.402 llvm/Makefile.rules:1.403
--- llvm/Makefile.rules:1.402	Sun Sep  3 23:50:10 2006
+++ llvm/Makefile.rules	Mon Sep  4 00:23:20 2006
@@ -73,6 +73,7 @@
 ifneq ($(MakefileCommonIn),)
 PreConditions      += $(MakefileCommon)
 endif
+
 ifneq ($(MakefileConfigIn),)
 PreConditions      += $(MakefileConfig)
 endif
@@ -304,7 +305,7 @@
 ifndef GCCLD
 GCCLD    := $(LLVMToolDir)/gccld$(EXEEXT)
 endif
-ifndef LDIS
+ifndef LLVMDIS
 LLVMDIS  := $(LLVMToolDir)/llvm-dis$(EXEEXT)
 endif
 ifndef LLI
@@ -707,10 +708,19 @@
 LLVMLibsPaths   := $(addprefix $(LLVMLibDir)/,$(LLVMUsedLibs))
 endif
 
-ifneq ($(strip($(filter-out clean clean-local dist-clean,$(MAKECMDGOALS)))),)
+ifeq ($(strip $(filter clean clean-local dist-clean,$(MAKECMDGOALS))),)
 ifdef LINK_COMPONENTS
-ProjLibsOptions := $(shell $(LLVM_CONFIG) --libs     $(LINK_COMPONENTS))
-ProjLibsPaths   := $(shell $(LLVM_CONFIG) --libfiles $(LINK_COMPONENTS))
+
+# If LLVM_CONFIG doesn't exist, build it.  This can happen if you do a make
+# clean in tools, then do a make in tools (instead of at the top level).
+$(LLVM_CONFIG):
+	@echo "*** llvm-config doesn't exist - rebuilding it."
+	@$(MAKE) -C $(PROJ_OBJ_ROOT)/tools/llvm-config
+        
+$(ToolDir)/$(strip $(TOOLNAME))$(EXEEXT): $(LLVM_CONFIG)
+
+ProjLibsOptions = $(shell $(LLVM_CONFIG) --libs     $(LINK_COMPONENTS))
+ProjLibsPaths   = $(shell $(LLVM_CONFIG) --libfiles $(LINK_COMPONENTS))
 endif
 endif
 
@@ -990,13 +1000,6 @@
 endif
 
 #---------------------------------------------------------
-# Tell make that we need to rebuild subdirectories before 
-# we can link the tool. This affects things like LLI which 
-# has library subdirectories.
-#---------------------------------------------------------
-$(ToolBuildPath): $(addsuffix /.makeall, $(PARALLEL_DIRS))
-
-#---------------------------------------------------------
 # Provide targets for building the tools
 #---------------------------------------------------------
 all-local:: $(ToolBuildPath)
@@ -1012,7 +1015,7 @@
 $(ToolBuildPath): $(ToolDir)/.dir
 endif
 
-$(ToolBuildPath): $(ObjectsO) $(ProjLibsPaths) $(LLVMLibsPaths)
+$(ToolBuildPath): $(ObjectsO) $(LLVM_CONFIG) $(ProjLibsPaths) $(LLVMLibsPaths)
 	$(Echo) Linking $(BuildMode) executable $(TOOLNAME) $(StripWarnMsg)
 	$(Verb) $(LTLink) -o $@ $(TOOLLINKOPTS) $(ObjectsO) $(ProjLibsOptions) \
 	$(LLVMLibsOptions) $(ExtraLibs) $(TOOLLINKOPTSB) $(LIBS)
@@ -1417,7 +1420,7 @@
 ifndef DISABLE_AUTO_DEPENDENCIES
 
 # If its not one of the cleaning targets
-ifneq ($(strip($(filter-out clean clean-local dist-clean,$(MAKECMDGOALS)))),)
+ifneq ($(strip $(filter-out clean clean-local dist-clean,$(MAKECMDGOALS)))),)
 
 # Get the list of dependency files
 DependFiles := $(basename $(filter %.cpp %.c %.cc, $(Sources)))





From lattner at cs.uiuc.edu  Mon Sep  4 00:24:30 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 4 Sep 2006 00:24:30 -0500
Subject: [llvm-commits] CVS: llvm/tools/llvm-dis/Makefile
Message-ID: <200609040524.k845OUfP014524@zion.cs.uiuc.edu>



Changes in directory llvm/tools/llvm-dis:

Makefile updated: 1.19 -> 1.20
---
Log message:

Switch to using llvm-config to build


---
Diffs of the changes:  (+1 -1)

 Makefile |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/tools/llvm-dis/Makefile
diff -u llvm/tools/llvm-dis/Makefile:1.19 llvm/tools/llvm-dis/Makefile:1.20
--- llvm/tools/llvm-dis/Makefile:1.19	Thu Jul  6 19:46:18 2006
+++ llvm/tools/llvm-dis/Makefile	Mon Sep  4 00:24:16 2006
@@ -9,7 +9,7 @@
 LEVEL = ../..
 
 TOOLNAME = llvm-dis
-USEDLIBS = LLVMBCReader.a LLVMCore.a LLVMSupport.a LLVMbzip2.a LLVMSystem.a
+LINK_COMPONENTS := bcreader
 REQUIRES_EH := 1
 
 include $(LEVEL)/Makefile.common





From lattner at cs.uiuc.edu  Mon Sep  4 00:35:37 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 4 Sep 2006 00:35:37 -0500
Subject: [llvm-commits] CVS: llvm/tools/llvm-config/llvm-config.in.in
Message-ID: <200609040535.k845ZbkD014735@zion.cs.uiuc.edu>



Changes in directory llvm/tools/llvm-config:

llvm-config.in.in updated: 1.22 -> 1.23
---
Log message:

Allow things like --libs CBackend


---
Diffs of the changes:  (+3 -0)

 llvm-config.in.in |    3 +++
 1 files changed, 3 insertions(+)


Index: llvm/tools/llvm-config/llvm-config.in.in
diff -u llvm/tools/llvm-config/llvm-config.in.in:1.22 llvm/tools/llvm-config/llvm-config.in.in:1.23
--- llvm/tools/llvm-config/llvm-config.in.in:1.22	Fri Aug 11 16:50:24 2006
+++ llvm/tools/llvm-config/llvm-config.in.in	Mon Sep  4 00:35:23 2006
@@ -143,6 +143,9 @@
     push @components, 'all';
 }
 
+# Force component names to lower case.
+ at components = map lc, @components;
+
 # Handle any arguments which require building our dependency graph.
 if ($want_libs || $want_libnames || $want_libfiles) {
     my @libs = expand_dependencies(@components);





From lattner at cs.uiuc.edu  Mon Sep  4 00:59:46 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 4 Sep 2006 00:59:46 -0500
Subject: [llvm-commits] CVS: llvm/tools/llvm-ar/Makefile
Message-ID: <200609040559.k845xkkr015221@zion.cs.uiuc.edu>



Changes in directory llvm/tools/llvm-ar:

Makefile updated: 1.10 -> 1.11
---
Log message:

Use LINK_COMPONENTS to specify *components* to link against instead of
using USED_LIBS to specify *libraries* to link against.


---
Diffs of the changes:  (+1 -2)

 Makefile |    3 +--
 1 files changed, 1 insertion(+), 2 deletions(-)


Index: llvm/tools/llvm-ar/Makefile
diff -u llvm/tools/llvm-ar/Makefile:1.10 llvm/tools/llvm-ar/Makefile:1.11
--- llvm/tools/llvm-ar/Makefile:1.10	Thu Jul  6 19:46:18 2006
+++ llvm/tools/llvm-ar/Makefile	Mon Sep  4 00:59:09 2006
@@ -9,8 +9,7 @@
 LEVEL = ../..
 
 TOOLNAME = llvm-ar
-USEDLIBS = LLVMArchive.a LLVMBCReader.a \
-	   LLVMCore.a LLVMSupport.a LLVMbzip2.a LLVMSystem.a
+LINK_COMPONENTS = archive bcreader
 REQUIRES_EH := 1
 
 include $(LEVEL)/Makefile.common





From lattner at cs.uiuc.edu  Mon Sep  4 00:59:46 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 4 Sep 2006 00:59:46 -0500
Subject: [llvm-commits] CVS: llvm/tools/llvm-ranlib/Makefile
Message-ID: <200609040559.k845xkO2015226@zion.cs.uiuc.edu>



Changes in directory llvm/tools/llvm-ranlib:

Makefile updated: 1.5 -> 1.6
---
Log message:

Use LINK_COMPONENTS to specify *components* to link against instead of
using USED_LIBS to specify *libraries* to link against.


---
Diffs of the changes:  (+1 -2)

 Makefile |    3 +--
 1 files changed, 1 insertion(+), 2 deletions(-)


Index: llvm/tools/llvm-ranlib/Makefile
diff -u llvm/tools/llvm-ranlib/Makefile:1.5 llvm/tools/llvm-ranlib/Makefile:1.6
--- llvm/tools/llvm-ranlib/Makefile:1.5	Thu Jul  6 19:46:19 2006
+++ llvm/tools/llvm-ranlib/Makefile	Mon Sep  4 00:59:09 2006
@@ -9,8 +9,7 @@
 
 LEVEL = ../..
 TOOLNAME = llvm-ranlib
-USEDLIBS = LLVMArchive.a LLVMBCReader.a \
-	   LLVMCore.a LLVMSupport.a LLVMbzip2.a LLVMSystem.a
+LINK_COMPONENTS = archive bcreader
 REQUIRES_EH := 1
 
 include $(LEVEL)/Makefile.common





From lattner at cs.uiuc.edu  Mon Sep  4 00:59:46 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 4 Sep 2006 00:59:46 -0500
Subject: [llvm-commits] CVS: llvm/tools/bugpoint/Makefile
Message-ID: <200609040559.k845xkbY015230@zion.cs.uiuc.edu>



Changes in directory llvm/tools/bugpoint:

Makefile updated: 1.18 -> 1.19
---
Log message:

Use LINK_COMPONENTS to specify *components* to link against instead of
using USED_LIBS to specify *libraries* to link against.


---
Diffs of the changes:  (+2 -7)

 Makefile |    9 ++-------
 1 files changed, 2 insertions(+), 7 deletions(-)


Index: llvm/tools/bugpoint/Makefile
diff -u llvm/tools/bugpoint/Makefile:1.18 llvm/tools/bugpoint/Makefile:1.19
--- llvm/tools/bugpoint/Makefile:1.18	Thu Jul  6 19:46:18 2006
+++ llvm/tools/bugpoint/Makefile	Mon Sep  4 00:59:09 2006
@@ -10,13 +10,8 @@
 
 TOOLNAME = bugpoint
 
-OPTLIBS  = LLVMTransforms.a LLVMInstrumentation.a
-ANALIBS  = LLVMDataStructure LLVMipa.a LLVMTarget.a 
-
-USEDLIBS = LLVMipo.a LLVMScalarOpts.a $(OPTLIBS) $(ANALIBS) LLVMAnalysis.a \
-	   LLVMTransformUtils.a \
-	   LLVMAsmParser.a LLVMLinker.a LLVMBCReader.a LLVMBCWriter.a \
-	   LLVMCore.a LLVMSupport.a LLVMbzip2.a LLVMSystem.a
+LINK_COMPONENTS := bcreader bcwriter asmparser instrumentation scalaropts ipo \
+                   datastructure transforms linker
 REQUIRES_EH := 1
 
 include $(LEVEL)/Makefile.common





From lattner at cs.uiuc.edu  Mon Sep  4 00:59:46 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 4 Sep 2006 00:59:46 -0500
Subject: [llvm-commits] CVS: llvm/tools/opt/Makefile
Message-ID: <200609040559.k845xk8I015231@zion.cs.uiuc.edu>



Changes in directory llvm/tools/opt:

Makefile updated: 1.58 -> 1.59
---
Log message:

Use LINK_COMPONENTS to specify *components* to link against instead of
using USED_LIBS to specify *libraries* to link against.


---
Diffs of the changes:  (+2 -4)

 Makefile |    6 ++----
 1 files changed, 2 insertions(+), 4 deletions(-)


Index: llvm/tools/opt/Makefile
diff -u llvm/tools/opt/Makefile:1.58 llvm/tools/opt/Makefile:1.59
--- llvm/tools/opt/Makefile:1.58	Sun Aug 27 17:07:01 2006
+++ llvm/tools/opt/Makefile	Mon Sep  4 00:59:09 2006
@@ -10,9 +10,7 @@
 TOOLNAME = opt
 REQUIRES_EH := 1
 
-USEDLIBS = LLVMBCReader.a LLVMBCWriter.a LLVMInstrumentation.a \
-	   LLVMScalarOpts.a LLVMipo.a LLVMipa.a LLVMDataStructure \
-	   LLVMTransforms.a LLVMTarget.a LLVMTransformUtils.a LLVMAnalysis.a \
-	   LLVMCore.a LLVMSupport.a LLVMbzip2.a LLVMSystem.a 
+LINK_COMPONENTS := bcreader bcwriter instrumentation scalaropts ipo \
+                   datastructure transforms
 
 include $(LEVEL)/Makefile.common





From lattner at cs.uiuc.edu  Mon Sep  4 00:59:47 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 4 Sep 2006 00:59:47 -0500
Subject: [llvm-commits] CVS: llvm/tools/llvm-link/Makefile
Message-ID: <200609040559.k845xlwk015241@zion.cs.uiuc.edu>



Changes in directory llvm/tools/llvm-link:

Makefile updated: 1.14 -> 1.15
---
Log message:

Use LINK_COMPONENTS to specify *components* to link against instead of
using USED_LIBS to specify *libraries* to link against.


---
Diffs of the changes:  (+1 -2)

 Makefile |    3 +--
 1 files changed, 1 insertion(+), 2 deletions(-)


Index: llvm/tools/llvm-link/Makefile
diff -u llvm/tools/llvm-link/Makefile:1.14 llvm/tools/llvm-link/Makefile:1.15
--- llvm/tools/llvm-link/Makefile:1.14	Thu Jul  6 19:46:18 2006
+++ llvm/tools/llvm-link/Makefile	Mon Sep  4 00:59:09 2006
@@ -9,8 +9,7 @@
 LEVEL = ../..
 
 TOOLNAME = llvm-link
-USEDLIBS = LLVMLinker.a LLVMBCReader.a LLVMBCWriter.a \
-	   LLVMCore.a LLVMSupport.a LLVMbzip2.a LLVMSystem.a
+LINK_COMPONENTS = linker bcreader bcwriter
 REQUIRES_EH := 1
 
 include $(LEVEL)/Makefile.common





From lattner at cs.uiuc.edu  Mon Sep  4 00:59:47 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 4 Sep 2006 00:59:47 -0500
Subject: [llvm-commits] CVS: llvm/tools/llvm-ld/Makefile
Message-ID: <200609040559.k845xlid015247@zion.cs.uiuc.edu>



Changes in directory llvm/tools/llvm-ld:

Makefile updated: 1.9 -> 1.10
---
Log message:

Use LINK_COMPONENTS to specify *components* to link against instead of
using USED_LIBS to specify *libraries* to link against.


---
Diffs of the changes:  (+1 -4)

 Makefile |    5 +----
 1 files changed, 1 insertion(+), 4 deletions(-)


Index: llvm/tools/llvm-ld/Makefile
diff -u llvm/tools/llvm-ld/Makefile:1.9 llvm/tools/llvm-ld/Makefile:1.10
--- llvm/tools/llvm-ld/Makefile:1.9	Thu Jul  6 19:46:18 2006
+++ llvm/tools/llvm-ld/Makefile	Mon Sep  4 00:59:09 2006
@@ -10,10 +10,7 @@
 LEVEL = ../..
 
 TOOLNAME = llvm-ld
-USEDLIBS = LLVMipo.a LLVMTransforms.a LLVMScalarOpts.a LLVMAnalysis.a \
-	   LLVMipa.a LLVMTransformUtils.a LLVMTarget.a LLVMLinker.a \
-	   LLVMArchive.a LLVMBCReader.a LLVMBCWriter.a \
-	   LLVMCore.a LLVMSupport.a LLVMbzip2.a LLVMSystem.a
+LINK_COMPONENTS = ipo scalaropts linker archive bcreader bcwriter
 REQUIRES_EH := 1
 
 include $(LEVEL)/Makefile.common





From lattner at cs.uiuc.edu  Mon Sep  4 00:59:48 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 4 Sep 2006 00:59:48 -0500
Subject: [llvm-commits] CVS: llvm/tools/gccas/Makefile
Message-ID: <200609040559.k845xmmn015257@zion.cs.uiuc.edu>



Changes in directory llvm/tools/gccas:

Makefile updated: 1.26 -> 1.27
---
Log message:

Use LINK_COMPONENTS to specify *components* to link against instead of
using USED_LIBS to specify *libraries* to link against.


---
Diffs of the changes:  (+1 -3)

 Makefile |    4 +---
 1 files changed, 1 insertion(+), 3 deletions(-)


Index: llvm/tools/gccas/Makefile
diff -u llvm/tools/gccas/Makefile:1.26 llvm/tools/gccas/Makefile:1.27
--- llvm/tools/gccas/Makefile:1.26	Thu Jul  6 19:46:18 2006
+++ llvm/tools/gccas/Makefile	Mon Sep  4 00:59:09 2006
@@ -9,9 +9,7 @@
 LEVEL = ../..
 
 TOOLNAME = gccas
-USEDLIBS = LLVMAsmParser.a LLVMBCWriter.a LLVMTransforms.a LLVMipo.a LLVMipa.a \
-           LLVMScalarOpts.a LLVMAnalysis.a LLVMTarget.a LLVMTransformUtils.a \
-           LLVMCore.a LLVMSupport.a LLVMbzip2.a LLVMSystem.a
+LINK_COMPONENTS = asmparser bcwriter scalaropts ipo ipa transforms
 REQUIRES_EH := 1
 
 include $(LEVEL)/Makefile.common





From lattner at cs.uiuc.edu  Mon Sep  4 00:59:49 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 4 Sep 2006 00:59:49 -0500
Subject: [llvm-commits] CVS: llvm/tools/llvm2cpp/Makefile
Message-ID: <200609040559.k845xnVW015262@zion.cs.uiuc.edu>



Changes in directory llvm/tools/llvm2cpp:

Makefile updated: 1.7 -> 1.8
---
Log message:

Use LINK_COMPONENTS to specify *components* to link against instead of
using USED_LIBS to specify *libraries* to link against.


---
Diffs of the changes:  (+1 -2)

 Makefile |    3 +--
 1 files changed, 1 insertion(+), 2 deletions(-)


Index: llvm/tools/llvm2cpp/Makefile
diff -u llvm/tools/llvm2cpp/Makefile:1.7 llvm/tools/llvm2cpp/Makefile:1.8
--- llvm/tools/llvm2cpp/Makefile:1.7	Thu Jul  6 19:46:19 2006
+++ llvm/tools/llvm2cpp/Makefile	Mon Sep  4 00:59:09 2006
@@ -8,10 +8,9 @@
 ##===----------------------------------------------------------------------===##
 LEVEL = ../..
 TOOLNAME = llvm2cpp
-USEDLIBS = LLVMBCReader.a LLVMCore.a LLVMSupport.a LLVMbzip2.a LLVMSystem.a
+LINK_COMPONENTS = bcreader
 REQUIRES_EH := 1
 
 include $(LEVEL)/Makefile.common
 
 CompileCommonOpts := $(filter-out -pedantic,$(CompileCommonOpts))
-CompileCommonOpts := $(filter-out -Wno-long-long,$(CompileCommonOpts))





From lattner at cs.uiuc.edu  Mon Sep  4 00:59:50 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 4 Sep 2006 00:59:50 -0500
Subject: [llvm-commits] CVS: llvm/tools/llc/Makefile
Message-ID: <200609040559.k845xol2015267@zion.cs.uiuc.edu>



Changes in directory llvm/tools/llc:

Makefile updated: 1.89 -> 1.90
---
Log message:

Use LINK_COMPONENTS to specify *components* to link against instead of
using USED_LIBS to specify *libraries* to link against.


---
Diffs of the changes:  (+2 -16)

 Makefile |   18 ++----------------
 1 files changed, 2 insertions(+), 16 deletions(-)


Index: llvm/tools/llc/Makefile
diff -u llvm/tools/llc/Makefile:1.89 llvm/tools/llc/Makefile:1.90
--- llvm/tools/llc/Makefile:1.89	Sun Sep  3 23:04:41 2006
+++ llvm/tools/llc/Makefile	Mon Sep  4 00:59:09 2006
@@ -13,24 +13,10 @@
 
 # Include this here so we can get the configuration of the targets
 # that have been configured for construction. We have to do this 
-# early so we can set up USEDLIBS properly before includeing Makefile.rules
+# early so we can set up LINK_COMPONENTS before including Makefile.rules
 include $(LEVEL)/Makefile.config
 
-USEDLIBS := $(addprefix LLVM,$(TARGETS_TO_BUILD)) \
-	LLVMTarget.a \
-	LLVMCodeGen.a \
-	LLVMSelectionDAG.a \
-	LLVMipa.a \
-	LLVMTransforms.a \
-	LLVMScalarOpts.a \
-	LLVMTransformUtils.a \
-	LLVMAnalysis.a \
-	LLVMBCReader.a \
-	LLVMBCWriter.a \
-	LLVMCore.a \
-	LLVMSupport.a \
-	LLVMbzip2.a \
-	LLVMSystem.a
+LINK_COMPONENTS := $(TARGETS_TO_BUILD) bcreader
 
 include $(LLVM_SRC_ROOT)/Makefile.rules
 





From lattner at cs.uiuc.edu  Mon Sep  4 00:59:50 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 4 Sep 2006 00:59:50 -0500
Subject: [llvm-commits] CVS: llvm/tools/gccld/Makefile
Message-ID: <200609040559.k845xol0015282@zion.cs.uiuc.edu>



Changes in directory llvm/tools/gccld:

Makefile updated: 1.16 -> 1.17
---
Log message:

Use LINK_COMPONENTS to specify *components* to link against instead of
using USED_LIBS to specify *libraries* to link against.


---
Diffs of the changes:  (+1 -4)

 Makefile |    5 +----
 1 files changed, 1 insertion(+), 4 deletions(-)


Index: llvm/tools/gccld/Makefile
diff -u llvm/tools/gccld/Makefile:1.16 llvm/tools/gccld/Makefile:1.17
--- llvm/tools/gccld/Makefile:1.16	Thu Jul  6 19:46:18 2006
+++ llvm/tools/gccld/Makefile	Mon Sep  4 00:59:09 2006
@@ -10,10 +10,7 @@
 LEVEL = ../..
 
 TOOLNAME = gccld
-USEDLIBS = LLVMipo.a LLVMTransforms.a LLVMScalarOpts.a LLVMAnalysis.a \
-           LLVMipa.a LLVMTransformUtils.a LLVMTarget.a LLVMLinker.a \
-           LLVMArchive.a LLVMBCReader.a LLVMBCWriter.a \
-           LLVMCore.a LLVMSupport.a LLVMbzip2.a LLVMSystem.a
+LINK_COMPONENTS = bcreader bcwriter ipo scalaropts ipa linker
 REQUIRES_EH := 1
 
 include $(LEVEL)/Makefile.common





From lattner at cs.uiuc.edu  Mon Sep  4 00:59:48 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 4 Sep 2006 00:59:48 -0500
Subject: [llvm-commits] CVS: llvm/tools/llvm-nm/Makefile
Message-ID: <200609040559.k845xmuo015252@zion.cs.uiuc.edu>



Changes in directory llvm/tools/llvm-nm:

Makefile updated: 1.8 -> 1.9
---
Log message:

Use LINK_COMPONENTS to specify *components* to link against instead of
using USED_LIBS to specify *libraries* to link against.


---
Diffs of the changes:  (+1 -2)

 Makefile |    3 +--
 1 files changed, 1 insertion(+), 2 deletions(-)


Index: llvm/tools/llvm-nm/Makefile
diff -u llvm/tools/llvm-nm/Makefile:1.8 llvm/tools/llvm-nm/Makefile:1.9
--- llvm/tools/llvm-nm/Makefile:1.8	Thu Jul  6 19:46:18 2006
+++ llvm/tools/llvm-nm/Makefile	Mon Sep  4 00:59:09 2006
@@ -9,8 +9,7 @@
 LEVEL = ../..
 
 TOOLNAME = llvm-nm
-USEDLIBS = LLVMArchive.a LLVMBCReader.a \
-	   LLVMCore.a LLVMSupport.a LLVMbzip2.a LLVMSystem.a
+LINK_COMPONENTS = archive bcreader
 REQUIRES_EH := 1
 
 include $(LEVEL)/Makefile.common





From lattner at cs.uiuc.edu  Mon Sep  4 00:59:50 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 4 Sep 2006 00:59:50 -0500
Subject: [llvm-commits] CVS: llvm/tools/llvm-db/Makefile
Message-ID: <200609040559.k845xo3c015277@zion.cs.uiuc.edu>



Changes in directory llvm/tools/llvm-db:

Makefile updated: 1.12 -> 1.13
---
Log message:

Use LINK_COMPONENTS to specify *components* to link against instead of
using USED_LIBS to specify *libraries* to link against.


---
Diffs of the changes:  (+1 -2)

 Makefile |    3 +--
 1 files changed, 1 insertion(+), 2 deletions(-)


Index: llvm/tools/llvm-db/Makefile
diff -u llvm/tools/llvm-db/Makefile:1.12 llvm/tools/llvm-db/Makefile:1.13
--- llvm/tools/llvm-db/Makefile:1.12	Thu Jul 20 19:10:47 2006
+++ llvm/tools/llvm-db/Makefile	Mon Sep  4 00:59:09 2006
@@ -9,8 +9,7 @@
 
 LEVEL = ../..
 TOOLNAME = llvm-db
-USEDLIBS = LLVMDebugger.a LLVMBCReader.a LLVMCore.a LLVMSupport.a \
-	  LLVMbzip2.a LLVMSystem.a
+LINK_COMPONENTS := debugger bcreader
 REQUIRES_EH := 1
 
 include $(LEVEL)/Makefile.common





From lattner at cs.uiuc.edu  Mon Sep  4 00:59:50 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 4 Sep 2006 00:59:50 -0500
Subject: [llvm-commits] CVS: llvm/tools/llvm-prof/Makefile
Message-ID: <200609040559.k845xo7T015272@zion.cs.uiuc.edu>



Changes in directory llvm/tools/llvm-prof:

Makefile updated: 1.8 -> 1.9
---
Log message:

Use LINK_COMPONENTS to specify *components* to link against instead of
using USED_LIBS to specify *libraries* to link against.


---
Diffs of the changes:  (+1 -2)

 Makefile |    3 +--
 1 files changed, 1 insertion(+), 2 deletions(-)


Index: llvm/tools/llvm-prof/Makefile
diff -u llvm/tools/llvm-prof/Makefile:1.8 llvm/tools/llvm-prof/Makefile:1.9
--- llvm/tools/llvm-prof/Makefile:1.8	Thu Jul  6 19:46:18 2006
+++ llvm/tools/llvm-prof/Makefile	Mon Sep  4 00:59:09 2006
@@ -9,8 +9,7 @@
 LEVEL = ../..
 
 TOOLNAME = llvm-prof
-USEDLIBS = LLVMAnalysis.a LLVMBCReader.a \
-           LLVMCore.a LLVMSupport.a LLVMbzip2.a LLVMSystem.a
+LINK_COMPONENTS = bcreader analysis
 REQUIRES_EH := 1
 
 include $(LEVEL)/Makefile.common





From lattner at cs.uiuc.edu  Mon Sep  4 00:59:51 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 4 Sep 2006 00:59:51 -0500
Subject: [llvm-commits] CVS: llvm/tools/llvm-bcanalyzer/Makefile
Message-ID: <200609040559.k845xpAJ015295@zion.cs.uiuc.edu>



Changes in directory llvm/tools/llvm-bcanalyzer:

Makefile updated: 1.6 -> 1.7
---
Log message:

Use LINK_COMPONENTS to specify *components* to link against instead of
using USED_LIBS to specify *libraries* to link against.


---
Diffs of the changes:  (+1 -1)

 Makefile |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/tools/llvm-bcanalyzer/Makefile
diff -u llvm/tools/llvm-bcanalyzer/Makefile:1.6 llvm/tools/llvm-bcanalyzer/Makefile:1.7
--- llvm/tools/llvm-bcanalyzer/Makefile:1.6	Thu Jul  6 19:46:18 2006
+++ llvm/tools/llvm-bcanalyzer/Makefile	Mon Sep  4 00:59:09 2006
@@ -9,7 +9,7 @@
 LEVEL = ../..
 
 TOOLNAME = llvm-bcanalyzer
-USEDLIBS = LLVMBCReader.a LLVMCore.a LLVMSupport.a LLVMbzip2.a LLVMSystem.a
+LINK_COMPONENTS := bcreader
 REQUIRES_EH := 1
 
 include $(LEVEL)/Makefile.common





From lattner at cs.uiuc.edu  Mon Sep  4 00:59:51 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 4 Sep 2006 00:59:51 -0500
Subject: [llvm-commits] CVS: llvm/tools/lto/Makefile
Message-ID: <200609040559.k845xprX015287@zion.cs.uiuc.edu>



Changes in directory llvm/tools/lto:

Makefile updated: 1.4 -> 1.5
---
Log message:

Use LINK_COMPONENTS to specify *components* to link against instead of
using USED_LIBS to specify *libraries* to link against.


---
Diffs of the changes:  (+2 -6)

 Makefile |    8 ++------
 1 files changed, 2 insertions(+), 6 deletions(-)


Index: llvm/tools/lto/Makefile
diff -u llvm/tools/lto/Makefile:1.4 llvm/tools/lto/Makefile:1.5
--- llvm/tools/lto/Makefile:1.4	Thu Aug  3 12:26:30 2006
+++ llvm/tools/lto/Makefile	Mon Sep  4 00:59:09 2006
@@ -17,14 +17,10 @@
 
 # Include this here so we can get the configuration of the targets
 # that have been configured for construction. We have to do this 
-# early so we can set up USEDLIBS properly before includeing Makefile.rules
+# early so we can set up LINK_COMPONENTS before includeing Makefile.rules
 include $(LEVEL)/Makefile.config
 
-USEDLIBS := $(addprefix LLVM,$(TARGETS_TO_BUILD)) \
-	LLVMSelectionDAG.a LLVMCodeGen.a LLVMipo.a LLVMTransforms.a \
-	LLVMScalarOpts.a LLVMipa.a LLVMTransformUtils.a LLVMAnalysis.a \
-	LLVMTarget.a LLVMBCReader.a LLVMBCWriter.a LLVMSystem.a LLVMLinker.a \
-	LLVMCore.a LLVMSupport.a LLVMbzip2.a
+LINK_COMPONENTS := $(TARGETS_TO_BUILD) ipo scalaropts bcreader bcwriter
 
 include $(LEVEL)/Makefile.common
 





From lattner at cs.uiuc.edu  Mon Sep  4 00:59:51 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 4 Sep 2006 00:59:51 -0500
Subject: [llvm-commits] CVS: llvm/tools/llvm-extract/Makefile
Message-ID: <200609040559.k845xpXe015300@zion.cs.uiuc.edu>



Changes in directory llvm/tools/llvm-extract:

Makefile updated: 1.5 -> 1.6
---
Log message:

Use LINK_COMPONENTS to specify *components* to link against instead of
using USED_LIBS to specify *libraries* to link against.


---
Diffs of the changes:  (+1 -3)

 Makefile |    4 +---
 1 files changed, 1 insertion(+), 3 deletions(-)


Index: llvm/tools/llvm-extract/Makefile
diff -u llvm/tools/llvm-extract/Makefile:1.5 llvm/tools/llvm-extract/Makefile:1.6
--- llvm/tools/llvm-extract/Makefile:1.5	Thu Jul  6 19:46:18 2006
+++ llvm/tools/llvm-extract/Makefile	Mon Sep  4 00:59:09 2006
@@ -9,9 +9,7 @@
 LEVEL = ../..
 
 TOOLNAME = llvm-extract
-USEDLIBS = LLVMBCReader.a LLVMBCWriter.a LLVMTransforms.a LLVMipo.a \
-	   LLVMTarget.a LLVMAnalysis.a LLVMTransformUtils.a LLVMipa.a \
-           LLVMCore.a LLVMSupport.a LLVMbzip2.a LLVMSystem.a
+LINK_COMPONENTS := bcreader bcwriter ipo
 REQUIRES_EH := 1
 
 include $(LEVEL)/Makefile.common





From lattner at cs.uiuc.edu  Mon Sep  4 00:59:51 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 4 Sep 2006 00:59:51 -0500
Subject: [llvm-commits] CVS: llvm/tools/llvmc/Makefile llvmc.cpp
Message-ID: <200609040559.k845xpxu015291@zion.cs.uiuc.edu>



Changes in directory llvm/tools/llvmc:

Makefile updated: 1.21 -> 1.22
llvmc.cpp updated: 1.30 -> 1.31
---
Log message:

Use LINK_COMPONENTS to specify *components* to link against instead of
using USED_LIBS to specify *libraries* to link against.


---
Diffs of the changes:  (+1 -2)

 Makefile  |    2 +-
 llvmc.cpp |    1 -
 2 files changed, 1 insertion(+), 2 deletions(-)


Index: llvm/tools/llvmc/Makefile
diff -u llvm/tools/llvmc/Makefile:1.21 llvm/tools/llvmc/Makefile:1.22
--- llvm/tools/llvmc/Makefile:1.21	Wed Aug 16 15:31:44 2006
+++ llvm/tools/llvmc/Makefile	Mon Sep  4 00:59:09 2006
@@ -8,7 +8,7 @@
 ##===----------------------------------------------------------------------===##
 LEVEL = ../..
 TOOLNAME = llvmc
-USEDLIBS = LLVMCore.a LLVMSupport.a LLVMSystem.a
+LINK_COMPONENTS = support system
 CONFIG_FILES = c cpp ll
 EXTRA_DIST = c cpp ll ConfigLexer.cpp.cvs ConfigLexer.l.cvs
 REQUIRES_EH := 1


Index: llvm/tools/llvmc/llvmc.cpp
diff -u llvm/tools/llvmc/llvmc.cpp:1.30 llvm/tools/llvmc/llvmc.cpp:1.31
--- llvm/tools/llvmc/llvmc.cpp:1.30	Mon Aug 21 01:04:45 2006
+++ llvm/tools/llvmc/llvmc.cpp	Mon Sep  4 00:59:09 2006
@@ -295,7 +295,6 @@
     if (KeepTemps)      flags |= CompilerDriver::KEEP_TEMPS_FLAG;
     if (ShowStats)      flags |= CompilerDriver::SHOW_STATS_FLAG;
     if (TimeActions)    flags |= CompilerDriver::TIME_ACTIONS_FLAG;
-    if (TimePassesIsEnabled) flags |= CompilerDriver::TIME_PASSES_FLAG;
     if (StripOutput)    flags |= CompilerDriver::STRIP_OUTPUT_FLAG;
     CD->setDriverFlags(flags);
 





From lattner at cs.uiuc.edu  Mon Sep  4 01:01:57 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 4 Sep 2006 01:01:57 -0500
Subject: [llvm-commits] CVS: llvm/tools/lli/Makefile
Message-ID: <200609040601.k8461v9r015372@zion.cs.uiuc.edu>



Changes in directory llvm/tools/lli:

Makefile updated: 1.49 -> 1.50
---
Log message:

Use llvm-config instead of magic JIT thing to link in libs


---
Diffs of the changes:  (+1 -1)

 Makefile |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/tools/lli/Makefile
diff -u llvm/tools/lli/Makefile:1.49 llvm/tools/lli/Makefile:1.50
--- llvm/tools/lli/Makefile:1.49	Thu Jul  6 19:46:18 2006
+++ llvm/tools/lli/Makefile	Mon Sep  4 01:01:43 2006
@@ -8,7 +8,7 @@
 ##===----------------------------------------------------------------------===##
 LEVEL    := ../..
 TOOLNAME := lli
-LLVMLIBS := JIT
+LINK_COMPONENTS := jit interpreter native bcreader
 REQUIRES_EH := 1
 
 # Enable JIT support





From lattner at cs.uiuc.edu  Mon Sep  4 01:04:19 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 4 Sep 2006 01:04:19 -0500
Subject: [llvm-commits] CVS: llvm/examples/ModuleMaker/Makefile
Message-ID: <200609040604.k8464JfM015445@zion.cs.uiuc.edu>



Changes in directory llvm/examples/ModuleMaker:

Makefile updated: 1.11 -> 1.12
---
Log message:

Use llvm-config to determine what to link in


---
Diffs of the changes:  (+1 -1)

 Makefile |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/examples/ModuleMaker/Makefile
diff -u llvm/examples/ModuleMaker/Makefile:1.11 llvm/examples/ModuleMaker/Makefile:1.12
--- llvm/examples/ModuleMaker/Makefile:1.11	Fri Jul 28 17:08:23 2006
+++ llvm/examples/ModuleMaker/Makefile	Mon Sep  4 01:04:03 2006
@@ -9,6 +9,6 @@
 LEVEL=../..
 TOOLNAME=ModuleMaker
 EXAMPLE_TOOL = 1
-USEDLIBS= LLVMBCWriter.a LLVMCore.a LLVMSupport.a LLVMbzip2.a LLVMSystem.a
+LINK_COMPONENTS := bcwriter
 
 include $(LEVEL)/Makefile.common





From lattner at cs.uiuc.edu  Mon Sep  4 01:04:20 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 4 Sep 2006 01:04:20 -0500
Subject: [llvm-commits] CVS: llvm/examples/Fibonacci/Makefile
Message-ID: <200609040604.k8464K7Q015450@zion.cs.uiuc.edu>



Changes in directory llvm/examples/Fibonacci:

Makefile updated: 1.7 -> 1.8
---
Log message:

Use llvm-config to determine what to link in


---
Diffs of the changes:  (+2 -2)

 Makefile |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/examples/Fibonacci/Makefile
diff -u llvm/examples/Fibonacci/Makefile:1.7 llvm/examples/Fibonacci/Makefile:1.8
--- llvm/examples/Fibonacci/Makefile:1.7	Mon Nov 29 01:17:19 2004
+++ llvm/examples/Fibonacci/Makefile	Mon Sep  4 01:04:03 2006
@@ -11,7 +11,7 @@
 TOOLNAME = Fibonacci
 EXAMPLE_TOOL = 1
 
-# Enable JIT support
-LLVMLIBS := JIT
+# Link in JIT support
+LINK_COMPONENTS := jit interpreter native
 
 include $(LEVEL)/Makefile.common





From lattner at cs.uiuc.edu  Mon Sep  4 01:04:22 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 4 Sep 2006 01:04:22 -0500
Subject: [llvm-commits] CVS: llvm/examples/ParallelJIT/Makefile
Message-ID: <200609040604.k8464MnW015455@zion.cs.uiuc.edu>



Changes in directory llvm/examples/ParallelJIT:

Makefile updated: 1.3 -> 1.4
---
Log message:

Use llvm-config to determine what to link in


---
Diffs of the changes:  (+1 -2)

 Makefile |    3 +--
 1 files changed, 1 insertion(+), 2 deletions(-)


Index: llvm/examples/ParallelJIT/Makefile
diff -u llvm/examples/ParallelJIT/Makefile:1.3 llvm/examples/ParallelJIT/Makefile:1.4
--- llvm/examples/ParallelJIT/Makefile:1.3	Wed Aug 24 05:07:21 2005
+++ llvm/examples/ParallelJIT/Makefile	Mon Sep  4 01:04:03 2006
@@ -10,8 +10,7 @@
 TOOLNAME = ParallelJIT
 EXAMPLE_TOOL = 1
 
-# Enable JIT support
-LLVMLIBS := JIT
+LINK_COMPONENTS := jit interpreter native
 
 include $(LEVEL)/Makefile.common
 





From lattner at cs.uiuc.edu  Mon Sep  4 01:04:22 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 4 Sep 2006 01:04:22 -0500
Subject: [llvm-commits] CVS: llvm/examples/HowToUseJIT/Makefile
Message-ID: <200609040604.k8464Mt3015460@zion.cs.uiuc.edu>



Changes in directory llvm/examples/HowToUseJIT:

Makefile updated: 1.8 -> 1.9
---
Log message:

Use llvm-config to determine what to link in


---
Diffs of the changes:  (+1 -2)

 Makefile |    3 +--
 1 files changed, 1 insertion(+), 2 deletions(-)


Index: llvm/examples/HowToUseJIT/Makefile
diff -u llvm/examples/HowToUseJIT/Makefile:1.8 llvm/examples/HowToUseJIT/Makefile:1.9
--- llvm/examples/HowToUseJIT/Makefile:1.8	Mon Nov 29 01:17:19 2004
+++ llvm/examples/HowToUseJIT/Makefile	Mon Sep  4 01:04:03 2006
@@ -10,7 +10,6 @@
 TOOLNAME = HowToUseJIT
 EXAMPLE_TOOL = 1
 
-# Enable JIT support
-LLVMLIBS := JIT
+LINK_COMPONENTS := jit interpreter native
 
 include $(LEVEL)/Makefile.common





From lattner at cs.uiuc.edu  Mon Sep  4 01:07:26 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 4 Sep 2006 01:07:26 -0500
Subject: [llvm-commits] CVS: llvm/Makefile.rules
Message-ID: <200609040607.k8467QfE015547@zion.cs.uiuc.edu>



Changes in directory llvm:

Makefile.rules updated: 1.403 -> 1.404
---
Log message:

Remove some dead makefilery


---
Diffs of the changes:  (+0 -62)

 Makefile.rules |   62 ---------------------------------------------------------
 1 files changed, 62 deletions(-)


Index: llvm/Makefile.rules
diff -u llvm/Makefile.rules:1.403 llvm/Makefile.rules:1.404
--- llvm/Makefile.rules:1.403	Mon Sep  4 00:23:20 2006
+++ llvm/Makefile.rules	Mon Sep  4 01:07:12 2006
@@ -626,68 +626,6 @@
 ###############################################################################
 
 #---------------------------------------------------------
-# Handle the special "JIT" value for LLVM_LIBS which is a
-# shorthand for a bunch of libraries that get the correct
-# JIT support for a library or a tool that runs JIT.
-#---------------------------------------------------------
-ifeq ($(firstword $(LLVMLIBS)),config)
-LLVMLIBS := $(shell $(LLVM_CONFIG) --libnames $(wordlist 2,9999,$(LLVMLIBS)))
-LLVMLIBS := $(patsubst lib%.a,%.a,$(LLVMLIBS))
-LLVMLIBS := $(patsubst %.o,%,$(LLVMLIBS))
-endif
-
-ifeq ($(LLVMLIBS),JIT)
-
-# Make sure we can get our own symbols in the tool
-Link += -dlopen self
-
-# Generic JIT libraries
-JIT_LIBS := LLVMInterpreter LLVMJIT
-
-# You can enable the X86 JIT on a non-X86 host by setting the flag
-# ENABLE_X86_JIT on the make command line. If not, it will still be
-# enabled automagically on an X86 host.
-ifeq ($(ARCH), x86)
-  ENABLE_X86_JIT = 1
-endif
-
-# What the X86 JIT requires
-ifdef ENABLE_X86_JIT
-  JIT_LIBS += LLVMX86 
-endif
-
-# You can enable the PowerPC JIT on a non-PowerPC host by setting the flag
-# ENABLE_PPC_JIT on the make command line. If not, it will still be
-# enabled automagically on an PowerPC host.
-ifeq ($(ARCH), PowerPC)
-  ENABLE_PPC_JIT = 1
-endif
-
-# What the PowerPC JIT requires
-ifdef ENABLE_PPC_JIT
-  JIT_LIBS += LLVMPowerPC 
-endif
-
-# You can enable the Alpha JIT on a non-Alpha host by setting the flag
-# ENABLE_ALPHA_JIT on the make command line. If not, it will still be
-# enabled automagically on an Alpha host.
-ifeq ($(ARCH), Alpha)
-  ENABLE_ALPHA_JIT = 1
-endif
-
-# What the Alpha JIT requires
-ifdef ENABLE_ALPHA_JIT
-  JIT_LIBS += LLVMAlpha 
-endif
-
-JIT_LIBS +=  LLVMTarget.a LLVMSelectionDAG.a LLVMCodeGen.a LLVMExecutionEngine
-
-LLVMLIBS := $(JIT_LIBS) LLVMScalarOpts.a LLVMTransformUtils.a LLVMAnalysis.a \
-            LLVMBCReader.a LLVMCore.a LLVMSupport.a LLVMbzip2.a \
-            LLVMSystem.a $(PLATFORMLIBDL)
-endif
-
-#---------------------------------------------------------
 # Define various command line options pertaining to the
 # libraries needed when linking. There are "Proj" libs 
 # (defined by the user's project) and "LLVM" libs (defined 





From lattner at cs.uiuc.edu  Mon Sep  4 01:12:29 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 4 Sep 2006 01:12:29 -0500
Subject: [llvm-commits] CVS: llvm/docs/MakefileGuide.html
Message-ID: <200609040612.k846CTNK015688@zion.cs.uiuc.edu>



Changes in directory llvm/docs:

MakefileGuide.html updated: 1.37 -> 1.38
---
Log message:

Update this to reflect llvm-config usage


---
Diffs of the changes:  (+11 -25)

 MakefileGuide.html |   36 +++++++++++-------------------------
 1 files changed, 11 insertions(+), 25 deletions(-)


Index: llvm/docs/MakefileGuide.html
diff -u llvm/docs/MakefileGuide.html:1.37 llvm/docs/MakefileGuide.html:1.38
--- llvm/docs/MakefileGuide.html:1.37	Mon Aug  7 18:44:59 2006
+++ llvm/docs/MakefileGuide.html	Mon Sep  4 01:12:14 2006
@@ -297,7 +297,7 @@
   <pre><tt>
      LIBRARYNAME := MyMod
      LOADABLE_MODULE := 1
-     USEDLIBS := LLVMSupport.a LLVMSystem.a
+     LINK_COMPONENTS := support system
   </tt></pre>
   <p>Use of the <tt>LOADABLE_MODULE</tt> facility implies several things:</p>
   <ol>
@@ -323,7 +323,7 @@
   <pre><tt>
       TOOLNAME = mytool
       USEDLIBS = mylib
-      LLVMLIBS = LLVMSupport.a LLVMSystem.a
+      LINK_COMPONENTS = support system
   </tt></pre>
   <p>says that we are to build a tool name <tt>mytool</tt> and that it requires
   three libraries: <tt>mylib</tt>, <tt>LLVMSupport.a</tt> and
@@ -352,36 +352,22 @@
 <!-- ======================================================================= -->
 <div class="doc_subsubsection"><a name="JIT">JIT Tools</a></div>
 <div class="doc_text">
-  <p>Many tools will want to use the JIT features of LLVM. However, getting the
-  right set of libraries to link with is tedious, platform specific, and error 
-  prone. Additionally, the JIT has special linker switch options that it needs.
-  Consequently, to make it easier to build tools that use the JIT, you can 
-  use a special value for the <tt>LLVMLIBS</tt> variable:</p>
+  <p>Many tools will want to use the JIT features of LLVM.  To do this, you
+     simply specify that you want an execution 'engine', and the makefiles will
+     automatically link in the appropriate JIT for the host or an interpreter
+     if none is available:</p>
   <pre><tt>
       TOOLNAME = my_jit_tool
       USEDLIBS = mylib
-      LLVMLIBS = JIT
+      LINK_COMPONENTS = engine
   </tt></pre>
-  <p>Using a value of <tt>JIT</tt> for <tt>LLVMLIBS</tt> tells the makefile
-  system to construct a special value for LLVMLIBS that gives the program all
-  the LLVM libraries needed to run the JIT. Any additional libraries needed can
-  still be specified with <tt>USEDLIBS</tt>. To get a full understanding of how
-  this changes the linker command, it is recommended that you:</p>
+  <p>Of course, any additional libraries may be listed as other components.  To
+  get a full understanding of how this changes the linker command, it is
+  recommended that you:</p>
   <pre><tt>
       cd examples/Fibonacci
       make VERBOSE=1
   </tt></pre>
-  <p>By default, using <tt>LLVMLIBS=JIT</tt> will link in enough to support JIT
-  code generation for the architecture on which the tool is linked. If you need
-  additional target architectures linked in, you may specify them on the command
-  line or in your <tt>Makefile</tt>. For example:</p>
-  <pre><tt>
-      ENABLE_X86_JIT=1
-      ENABLE_SPARCV9_JIT=1
-      ENALBE_PPC_JIT=1
-  </tt></pre>
-  <p>will cause the tool to be able to generate code for all three platforms.
-  </p>
 </div>
 
 <!-- *********************************************************************** -->
@@ -1039,7 +1025,7 @@
 
   <a href="mailto:rspencer at x10sys.com">Reid Spencer</a><br>
   <a href="http://llvm.org">The LLVM Compiler Infrastructure</a><br>
-  Last modified: $Date: 2006/08/07 23:44:59 $
+  Last modified: $Date: 2006/09/04 06:12:14 $
 </address>
 </body>
 </html>





From duraid at octopus.com.au  Mon Sep  4 01:21:53 2006
From: duraid at octopus.com.au (Duraid Madina)
Date: Mon, 4 Sep 2006 01:21:53 -0500
Subject: [llvm-commits] CVS: llvm/lib/Transforms/Utils/LowerInvoke.cpp
Message-ID: <200609040621.k846Lrjx015894@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/Utils:

LowerInvoke.cpp updated: 1.39 -> 1.40
---
Log message:

add setJumpBufSize() and setJumpBufAlignment() to target-lowering.
Call these from your backend to enjoy setjmp/longjmp goodness, see
lib/Target/IA64/IA64ISelLowering.cpp for an example




---
Diffs of the changes:  (+10 -10)

 LowerInvoke.cpp |   20 ++++++++++----------
 1 files changed, 10 insertions(+), 10 deletions(-)


Index: llvm/lib/Transforms/Utils/LowerInvoke.cpp
diff -u llvm/lib/Transforms/Utils/LowerInvoke.cpp:1.39 llvm/lib/Transforms/Utils/LowerInvoke.cpp:1.40
--- llvm/lib/Transforms/Utils/LowerInvoke.cpp:1.39	Sun Aug 27 17:42:52 2006
+++ llvm/lib/Transforms/Utils/LowerInvoke.cpp	Mon Sep  4 01:21:35 2006
@@ -45,6 +45,7 @@
 #include "llvm/ADT/Statistic.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Compiler.h"
+#include "llvm/Target/TargetLowering.h"
 #include <csetjmp>
 using namespace llvm;
 
@@ -67,9 +68,12 @@
     const Type *JBLinkTy;
     GlobalVariable *JBListHead;
     Function *SetJmpFn, *LongJmpFn;
+    
+    // We peek in TLI to grab the target's jmp_buf size and alignment
+    const TargetLowering *TLI;
+    
   public:
-    LowerInvoke(unsigned Size = 200, unsigned Align = 0) : JumpBufSize(Size),
-      JumpBufAlign(Align) {}
+    LowerInvoke(const TargetLowering *tli = NULL) : TLI(tli) { }
     bool doInitialization(Module &M);
     bool runOnFunction(Function &F);
  
@@ -89,9 +93,6 @@
     void rewriteExpensiveInvoke(InvokeInst *II, unsigned InvokeNo,
                                 AllocaInst *InvokeNum, SwitchInst *CatchSwitch);
     bool insertExpensiveEHSupport(Function &F);
-    
-    unsigned JumpBufSize;
-    unsigned JumpBufAlign;
   };
 
   RegisterPass<LowerInvoke>
@@ -101,9 +102,8 @@
 const PassInfo *llvm::LowerInvokePassID = X.getPassInfo();
 
 // Public Interface To the LowerInvoke pass.
-FunctionPass *llvm::createLowerInvokePass(unsigned JumpBufSize, 
-                                          unsigned JumpBufAlign) { 
-  return new LowerInvoke(JumpBufSize, JumpBufAlign); 
+FunctionPass *llvm::createLowerInvokePass(const TargetLowering *TLI) { 
+  return new LowerInvoke(TLI); 
 }
 
 // doInitialization - Make sure that there is a prototype for abort in the
@@ -113,7 +113,7 @@
   AbortMessage = 0;
   if (ExpensiveEHSupport) {
     // Insert a type for the linked list of jump buffers.
-    const Type *JmpBufTy = ArrayType::get(VoidPtrTy, JumpBufSize);
+    const Type *JmpBufTy = ArrayType::get(VoidPtrTy, TLI->getJumpBufSize());
 
     { // The type is recursive, so use a type holder.
       std::vector<const Type*> Elements;
@@ -453,7 +453,7 @@
     // that needs to be restored on all exits from the function.  This is an
     // alloca because the value needs to be live across invokes.
     AllocaInst *JmpBuf = 
-      new AllocaInst(JBLinkTy, 0, JumpBufAlign, "jblink", F.begin()->begin());
+      new AllocaInst(JBLinkTy, 0, TLI->getJumpBufAlignment(), "jblink", F.begin()->begin());
     
     std::vector<Value*> Idx;
     Idx.push_back(Constant::getNullValue(Type::IntTy));





From duraid at octopus.com.au  Mon Sep  4 01:21:51 2006
From: duraid at octopus.com.au (Duraid Madina)
Date: Mon, 4 Sep 2006 01:21:51 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/LLVMTargetMachine.cpp
Message-ID: <200609040621.k846LpuT015889@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen:

LLVMTargetMachine.cpp updated: 1.1 -> 1.2
---
Log message:

add setJumpBufSize() and setJumpBufAlignment() to target-lowering.
Call these from your backend to enjoy setjmp/longjmp goodness, see
lib/Target/IA64/IA64ISelLowering.cpp for an example




---
Diffs of the changes:  (+2 -2)

 LLVMTargetMachine.cpp |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/lib/CodeGen/LLVMTargetMachine.cpp
diff -u llvm/lib/CodeGen/LLVMTargetMachine.cpp:1.1 llvm/lib/CodeGen/LLVMTargetMachine.cpp:1.2
--- llvm/lib/CodeGen/LLVMTargetMachine.cpp:1.1	Sun Sep  3 23:16:09 2006
+++ llvm/lib/CodeGen/LLVMTargetMachine.cpp	Mon Sep  4 01:21:35 2006
@@ -33,7 +33,7 @@
   PM.add(createLowerGCPass());
   
   // FIXME: Implement the invoke/unwind instructions!
-  PM.add(createLowerInvokePass());
+  PM.add(createLowerInvokePass(getTargetLowering()));
   
   // Make sure that no unreachable blocks are instruction selected.
   PM.add(createUnreachableBlockEliminationPass());
@@ -107,7 +107,7 @@
   PM.add(createLowerGCPass());
   
   // FIXME: Implement the invoke/unwind instructions!
-  PM.add(createLowerInvokePass());
+  PM.add(createLowerInvokePass(getTargetLowering()));
   
   // Make sure that no unreachable blocks are instruction selected.
   PM.add(createUnreachableBlockEliminationPass());





From duraid at octopus.com.au  Mon Sep  4 01:21:55 2006
From: duraid at octopus.com.au (Duraid Madina)
Date: Mon, 4 Sep 2006 01:21:55 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetLowering.h
Message-ID: <200609040621.k846LtSp015905@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/Target:

TargetLowering.h updated: 1.77 -> 1.78
---
Log message:

add setJumpBufSize() and setJumpBufAlignment() to target-lowering.
Call these from your backend to enjoy setjmp/longjmp goodness, see
lib/Target/IA64/IA64ISelLowering.cpp for an example




---
Diffs of the changes:  (+31 -0)

 TargetLowering.h |   31 +++++++++++++++++++++++++++++++
 1 files changed, 31 insertions(+)


Index: llvm/include/llvm/Target/TargetLowering.h
diff -u llvm/include/llvm/Target/TargetLowering.h:1.77 llvm/include/llvm/Target/TargetLowering.h:1.78
--- llvm/include/llvm/Target/TargetLowering.h:1.77	Mon Jun 12 11:06:08 2006
+++ llvm/include/llvm/Target/TargetLowering.h	Mon Sep  4 01:21:35 2006
@@ -327,6 +327,18 @@
     return StackPointerRegisterToSaveRestore;
   }
 
+  /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never
+  /// set, the default is 200)
+  unsigned getJumpBufSize() const {
+    return JumpBufSize;
+  }
+
+  /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes
+  /// (if never set, the default is 0)
+  unsigned getJumpBufAlignment() const {
+    return JumpBufAlignment;
+  }
+  
   //===--------------------------------------------------------------------===//
   // TargetLowering Optimization Methods
   //
@@ -537,6 +549,18 @@
     TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
   }
   
+  /// setJumpBufSize - Set the target's required jmp_buf buffer size (in
+  /// bytes); default is 200
+  void setJumpBufSize(unsigned Size) {
+    JumpBufSize = Size;
+  }
+
+  /// setJumpBufAlignment - Set the target's required jmp_buf buffer
+  /// alignment (in bytes); default is 0
+  void setJumpBufAlignment(unsigned Align) {
+    JumpBufAlignment = Align;
+  }
+  
 public:
 
   //===--------------------------------------------------------------------===//
@@ -718,6 +742,13 @@
   /// _longjmp to implement llvm.setjmp/llvm.longjmp.  Defaults to false.
   bool UseUnderscoreSetJmpLongJmp;
   
+  /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers
+  unsigned JumpBufSize;
+  
+  /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf
+  /// buffers
+  unsigned JumpBufAlignment;
+  
   /// StackPointerRegisterToSaveRestore - If set to a physical register, this
   /// specifies the register that llvm.savestack/llvm.restorestack should save
   /// and restore.





From duraid at octopus.com.au  Mon Sep  4 01:21:54 2006
From: duraid at octopus.com.au (Duraid Madina)
Date: Mon, 4 Sep 2006 01:21:54 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/Transforms/Scalar.h
Message-ID: <200609040621.k846LsS8015900@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/Transforms:

Scalar.h updated: 1.67 -> 1.68
---
Log message:

add setJumpBufSize() and setJumpBufAlignment() to target-lowering.
Call these from your backend to enjoy setjmp/longjmp goodness, see
lib/Target/IA64/IA64ISelLowering.cpp for an example




---
Diffs of the changes:  (+1 -2)

 Scalar.h |    3 +--
 1 files changed, 1 insertion(+), 2 deletions(-)


Index: llvm/include/llvm/Transforms/Scalar.h
diff -u llvm/include/llvm/Transforms/Scalar.h:1.67 llvm/include/llvm/Transforms/Scalar.h:1.68
--- llvm/include/llvm/Transforms/Scalar.h:1.67	Mon Aug 28 17:44:55 2006
+++ llvm/include/llvm/Transforms/Scalar.h	Mon Sep  4 01:21:35 2006
@@ -286,8 +286,7 @@
 // "my LLVM-to-LLVM pass doesn't support the invoke instruction yet" lowering
 // pass.
 //
-FunctionPass *createLowerInvokePass(unsigned JumBufSize = 200, 
-                                    unsigned JumpBufAlign = 0);
+FunctionPass *createLowerInvokePass(const TargetLowering *TLI = NULL);
 extern const PassInfo *LowerInvokePassID;
 
 





From duraid at octopus.com.au  Mon Sep  4 01:21:56 2006
From: duraid at octopus.com.au (Duraid Madina)
Date: Mon, 4 Sep 2006 01:21:56 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelLowering.cpp
Message-ID: <200609040621.k846LuJ9015910@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/IA64:

IA64ISelLowering.cpp updated: 1.41 -> 1.42
---
Log message:

add setJumpBufSize() and setJumpBufAlignment() to target-lowering.
Call these from your backend to enjoy setjmp/longjmp goodness, see
lib/Target/IA64/IA64ISelLowering.cpp for an example




---
Diffs of the changes:  (+3 -0)

 IA64ISelLowering.cpp |    3 +++
 1 files changed, 3 insertions(+)


Index: llvm/lib/Target/IA64/IA64ISelLowering.cpp
diff -u llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.41 llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.42
--- llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.41	Wed Aug 16 02:28:58 2006
+++ llvm/lib/Target/IA64/IA64ISelLowering.cpp	Mon Sep  4 01:21:35 2006
@@ -109,6 +109,9 @@
 
       setStackPointerRegisterToSaveRestore(IA64::r12);
 
+      setJumpBufSize(704); // on ia64-linux, jmp_bufs are 704 bytes..
+      setJumpBufAlignment(16); // ...and must be 16-byte aligned
+      
       computeRegisterProperties();
 
       setOperationAction(ISD::ConstantFP, MVT::f64, Expand);





From lattner at cs.uiuc.edu  Mon Sep  4 01:40:07 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 4 Sep 2006 01:40:07 -0500
Subject: [llvm-commits] CVS: llvm/Makefile.rules
Message-ID: <200609040640.k846e7fe016239@zion.cs.uiuc.edu>



Changes in directory llvm:

Makefile.rules updated: 1.404 -> 1.405
---
Log message:

Fix a build problem


---
Diffs of the changes:  (+3 -2)

 Makefile.rules |    5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)


Index: llvm/Makefile.rules
diff -u llvm/Makefile.rules:1.404 llvm/Makefile.rules:1.405
--- llvm/Makefile.rules:1.404	Mon Sep  4 01:07:12 2006
+++ llvm/Makefile.rules	Mon Sep  4 01:39:52 2006
@@ -658,7 +658,8 @@
 $(ToolDir)/$(strip $(TOOLNAME))$(EXEEXT): $(LLVM_CONFIG)
 
 ProjLibsOptions = $(shell $(LLVM_CONFIG) --libs     $(LINK_COMPONENTS))
-ProjLibsPaths   = $(shell $(LLVM_CONFIG) --libfiles $(LINK_COMPONENTS))
+ProjLibsPaths   = $(LLVM_CONFIG) \
+                  $(shell $(LLVM_CONFIG) --libfiles $(LINK_COMPONENTS))
 endif
 endif
 
@@ -953,7 +954,7 @@
 $(ToolBuildPath): $(ToolDir)/.dir
 endif
 
-$(ToolBuildPath): $(ObjectsO) $(LLVM_CONFIG) $(ProjLibsPaths) $(LLVMLibsPaths)
+$(ToolBuildPath): $(ObjectsO) $(ProjLibsPaths) $(LLVMLibsPaths)
 	$(Echo) Linking $(BuildMode) executable $(TOOLNAME) $(StripWarnMsg)
 	$(Verb) $(LTLink) -o $@ $(TOOLLINKOPTS) $(ObjectsO) $(ProjLibsOptions) \
 	$(LLVMLibsOptions) $(ExtraLibs) $(TOOLLINKOPTSB) $(LIBS)





From duraid at octopus.com.au  Mon Sep  4 02:44:25 2006
From: duraid at octopus.com.au (Duraid Madina)
Date: Mon, 4 Sep 2006 02:44:25 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Message-ID: <200609040744.k847iP4c025517@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

TargetLowering.cpp updated: 1.70 -> 1.71
---
Log message:

forgot this



---
Diffs of the changes:  (+2 -0)

 TargetLowering.cpp |    2 ++
 1 files changed, 2 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.70 llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.71
--- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.70	Fri Jul  7 16:37:21 2006
+++ llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp	Mon Sep  4 02:44:11 2006
@@ -41,6 +41,8 @@
   Pow2DivIsCheap = false;
   StackPointerRegisterToSaveRestore = 0;
   SchedPreferenceInfo = SchedulingForLatency;
+  JumpBufSize = 200;
+  JumpBufAlignment = 0;
 }
 
 TargetLowering::~TargetLowering() {}





From lattner at cs.uiuc.edu  Mon Sep  4 13:20:29 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 4 Sep 2006 13:20:29 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/LiveIntervalAnalysis.cpp
Message-ID: <200609041820.k84IKTSJ011889@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen:

LiveIntervalAnalysis.cpp updated: 1.183 -> 1.184
---
Log message:

Hack around a regression I introduced yesterday


---
Diffs of the changes:  (+3 -0)

 LiveIntervalAnalysis.cpp |    3 +++
 1 files changed, 3 insertions(+)


Index: llvm/lib/CodeGen/LiveIntervalAnalysis.cpp
diff -u llvm/lib/CodeGen/LiveIntervalAnalysis.cpp:1.183 llvm/lib/CodeGen/LiveIntervalAnalysis.cpp:1.184
--- llvm/lib/CodeGen/LiveIntervalAnalysis.cpp:1.183	Sun Sep  3 03:07:11 2006
+++ llvm/lib/CodeGen/LiveIntervalAnalysis.cpp	Mon Sep  4 13:20:15 2006
@@ -619,6 +619,9 @@
         tm_->getInstrInfo()->get(mi->getOpcode());
       DEBUG(std::cerr << MIIndex << "\t" << *mi);
 
+      // FIXME: Why is  this needed?
+      MIIndex = getInstructionIndex(mi);
+      
       // handle implicit defs
       if (tid.ImplicitDefs) {
         for (const unsigned* id = tid.ImplicitDefs; *id; ++id)





From lattner at cs.uiuc.edu  Mon Sep  4 13:27:55 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 4 Sep 2006 13:27:55 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/LiveIntervalAnalysis.cpp
Message-ID: <200609041827.k84IRtPX012055@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen:

LiveIntervalAnalysis.cpp updated: 1.184 -> 1.185
---
Log message:

Correct fix for a crasher on functions with live in values


---
Diffs of the changes:  (+6 -4)

 LiveIntervalAnalysis.cpp |   10 ++++++----
 1 files changed, 6 insertions(+), 4 deletions(-)


Index: llvm/lib/CodeGen/LiveIntervalAnalysis.cpp
diff -u llvm/lib/CodeGen/LiveIntervalAnalysis.cpp:1.184 llvm/lib/CodeGen/LiveIntervalAnalysis.cpp:1.185
--- llvm/lib/CodeGen/LiveIntervalAnalysis.cpp:1.184	Mon Sep  4 13:20:15 2006
+++ llvm/lib/CodeGen/LiveIntervalAnalysis.cpp	Mon Sep  4 13:27:40 2006
@@ -613,15 +613,17 @@
     DEBUG(std::cerr << ((Value*)mbb->getBasicBlock())->getName() << ":\n");
 
     MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end();
-    if (IgnoreFirstInstr) { ++mi; IgnoreFirstInstr = false; }
+    if (IgnoreFirstInstr) {
+      ++mi;
+      IgnoreFirstInstr = false;
+      MIIndex += InstrSlots::NUM;
+    }
+    
     for (; mi != miEnd; ++mi) {
       const TargetInstrDescriptor& tid =
         tm_->getInstrInfo()->get(mi->getOpcode());
       DEBUG(std::cerr << MIIndex << "\t" << *mi);
 
-      // FIXME: Why is  this needed?
-      MIIndex = getInstructionIndex(mi);
-      
       // handle implicit defs
       if (tid.ImplicitDefs) {
         for (const unsigned* id = tid.ImplicitDefs; *id; ++id)





From lattner at cs.uiuc.edu  Mon Sep  4 13:34:30 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 4 Sep 2006 13:34:30 -0500
Subject: [llvm-commits] CVS: llvm/tools/lli/Makefile
Message-ID: <200609041834.k84IYUqJ012181@zion.cs.uiuc.edu>



Changes in directory llvm/tools/lli:

Makefile updated: 1.50 -> 1.51
---
Log message:

lli uses LinkAllCodegenComponents, so it needs this.  Thanks to 
Rafael Esp?ndola for pointing this out


---
Diffs of the changes:  (+2 -1)

 Makefile |    3 ++-
 1 files changed, 2 insertions(+), 1 deletion(-)


Index: llvm/tools/lli/Makefile
diff -u llvm/tools/lli/Makefile:1.50 llvm/tools/lli/Makefile:1.51
--- llvm/tools/lli/Makefile:1.50	Mon Sep  4 01:01:43 2006
+++ llvm/tools/lli/Makefile	Mon Sep  4 13:34:16 2006
@@ -6,9 +6,10 @@
 # the University of Illinois Open Source License. See LICENSE.TXT for details.
 # 
 ##===----------------------------------------------------------------------===##
+
 LEVEL    := ../..
 TOOLNAME := lli
-LINK_COMPONENTS := jit interpreter native bcreader
+LINK_COMPONENTS := jit interpreter native bcreader selectiondag
 REQUIRES_EH := 1
 
 # Enable JIT support





From lattner at cs.uiuc.edu  Mon Sep  4 13:39:00 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 4 Sep 2006 13:39:00 -0500
Subject: [llvm-commits] CVS: nightlytest-serverside/NightlyTestAccept.cgi
Message-ID: <200609041839.k84Id0K4012312@zion.cs.uiuc.edu>



Changes in directory nightlytest-serverside:

NightlyTestAccept.cgi updated: 1.53 -> 1.54
---
Log message:

add missing newline, which makes the link not work.


---
Diffs of the changes:  (+1 -1)

 NightlyTestAccept.cgi |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: nightlytest-serverside/NightlyTestAccept.cgi
diff -u nightlytest-serverside/NightlyTestAccept.cgi:1.53 nightlytest-serverside/NightlyTestAccept.cgi:1.54
--- nightlytest-serverside/NightlyTestAccept.cgi:1.53	Tue Aug 22 12:31:26 2006
+++ nightlytest-serverside/NightlyTestAccept.cgi	Mon Sep  4 13:38:46 2006
@@ -867,7 +867,7 @@
   $temp_date = $db_date;
   $temp_date =~s/ /\_/g;
   $email .= "\nBuildlog available at http://llvm.org/nightlytest/".
-            "machines/$machine_id/$temp_date-Build-Log.txt";
+            "machines/$machine_id/$temp_date-Build-Log.txt\n";
 }
 
 $email_addr = "llvm-testresults\@cs.uiuc.edu";





From lattner at cs.uiuc.edu  Mon Sep  4 13:48:55 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 4 Sep 2006 13:48:55 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86TargetMachine.cpp
Message-ID: <200609041848.k84Imte8012517@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86TargetMachine.cpp updated: 1.124 -> 1.125
---
Log message:

Fix some X86 JIT failures.  This should really come from TargetJITInfo.


---
Diffs of the changes:  (+3 -0)

 X86TargetMachine.cpp |    3 +++
 1 files changed, 3 insertions(+)


Index: llvm/lib/Target/X86/X86TargetMachine.cpp
diff -u llvm/lib/Target/X86/X86TargetMachine.cpp:1.124 llvm/lib/Target/X86/X86TargetMachine.cpp:1.125
--- llvm/lib/Target/X86/X86TargetMachine.cpp:1.124	Sun Sep  3 23:14:57 2006
+++ llvm/lib/Target/X86/X86TargetMachine.cpp	Mon Sep  4 13:48:41 2006
@@ -106,6 +106,9 @@
 
 bool X86TargetMachine::addCodeEmitter(FunctionPassManager &PM, bool Fast,
                                       MachineCodeEmitter &MCE) {
+  // FIXME: Move this to TargetJITInfo!
+  setRelocationModel(Reloc::Static);
+  
   PM.add(createX86CodeEmitterPass(*this, MCE));
   return false;
 }





From rafael.espindola at gmail.com  Mon Sep  4 14:05:17 2006
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Mon, 4 Sep 2006 14:05:17 -0500
Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/ARM/long.ll
Message-ID: <200609041905.k84J5Hsf012890@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CodeGen/ARM:

long.ll added (r1.1)
---
Log message:

add support for returning 64bit values


---
Diffs of the changes:  (+32 -0)

 long.ll |   32 ++++++++++++++++++++++++++++++++
 1 files changed, 32 insertions(+)


Index: llvm/test/Regression/CodeGen/ARM/long.ll
diff -c /dev/null llvm/test/Regression/CodeGen/ARM/long.ll:1.1
*** /dev/null	Mon Sep  4 14:05:11 2006
--- llvm/test/Regression/CodeGen/ARM/long.ll	Mon Sep  4 14:05:01 2006
***************
*** 0 ****
--- 1,32 ----
+ ; RUN: llvm-as < %s | llc -march=arm &&
+ ; RUN: llvm-as < %s | llc -march=arm | grep "mov r1, #0" | wc -l | grep 4 &&
+ ; RUN: llvm-as < %s | llc -march=arm | grep "mov r0, #1" | wc -l | grep 1 &&
+ ; RUN: llvm-as < %s | llc -march=arm | grep "mov r0, #2147483647" | wc -l | grep 1 &&
+ ; RUN: llvm-as < %s | llc -march=arm | grep "mov r0, #-2147483648" | wc -l | grep 1 &&
+ ; RUN: llvm-as < %s | llc -march=arm | grep "mov r0, #-1" | wc -l | grep 1 &&
+ ; RUN: llvm-as < %s | llc -march=arm | grep "mov r1, #2147483647" | wc -l | grep 1
+ 
+ long %f1() {
+ entry:
+ 	ret long 0
+ }
+ 
+ long %f2() {
+ entry:
+ 	ret long 1
+ }
+ 
+ long %f3() {
+ entry:
+ 	ret long 2147483647
+ }
+ 
+ long %f4() {
+ entry:
+ 	ret long 2147483648
+ }
+ 
+ long %f5() {
+ entry:
+ 	ret long 9223372036854775807
+ }





From rafael.espindola at gmail.com  Mon Sep  4 14:05:16 2006
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Mon, 4 Sep 2006 14:05:16 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
Message-ID: <200609041905.k84J5GMi012884@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/ARM:

ARMISelDAGToDAG.cpp updated: 1.40 -> 1.41
---
Log message:

add support for returning 64bit values


---
Diffs of the changes:  (+9 -0)

 ARMISelDAGToDAG.cpp |    9 +++++++++
 1 files changed, 9 insertions(+)


Index: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
diff -u llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.40 llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.41
--- llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.40	Sun Sep  3 08:19:15 2006
+++ llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp	Mon Sep  4 14:05:01 2006
@@ -238,6 +238,15 @@
     if (DAG.getMachineFunction().liveout_empty())
       DAG.getMachineFunction().addLiveOut(ARM::R0);
     break;
+  case 5:
+    Copy = DAG.getCopyToReg(Chain, ARM::R1, Op.getOperand(3), SDOperand());
+    Copy = DAG.getCopyToReg(Copy, ARM::R0, Op.getOperand(1), Copy.getValue(1));
+    // If we haven't noted the R0+R1 are live out, do so now.
+    if (DAG.getMachineFunction().liveout_empty()) {
+      DAG.getMachineFunction().addLiveOut(ARM::R0);
+      DAG.getMachineFunction().addLiveOut(ARM::R1);
+    }
+    break;
   }
 
   //We must use RET_FLAG instead of BRIND because BRIND doesn't have a flag





From lattner at cs.uiuc.edu  Mon Sep  4 18:05:43 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 4 Sep 2006 18:05:43 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineInstr.h
Message-ID: <200609042305.k84N5hEP016449@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

MachineInstr.h updated: 1.182 -> 1.183
---
Log message:

Add some short-hand accessors


---
Diffs of the changes:  (+4 -0)

 MachineInstr.h |    4 ++++
 1 files changed, 4 insertions(+)


Index: llvm/include/llvm/CodeGen/MachineInstr.h
diff -u llvm/include/llvm/CodeGen/MachineInstr.h:1.182 llvm/include/llvm/CodeGen/MachineInstr.h:1.183
--- llvm/include/llvm/CodeGen/MachineInstr.h:1.182	Wed May 24 12:04:03 2006
+++ llvm/include/llvm/CodeGen/MachineInstr.h	Mon Sep  4 18:05:29 2006
@@ -111,6 +111,10 @@
 
   /// Accessors that tell you what kind of MachineOperand you're looking at.
   ///
+  bool isReg() const { return opType == MO_Register; }
+  bool isImm() const { return opType == MO_Immediate; }
+  bool isMBB() const { return opType == MO_MachineBasicBlock; }
+  
   bool isRegister() const { return opType == MO_Register; }
   bool isImmediate() const { return opType == MO_Immediate; }
   bool isMachineBasicBlock() const { return opType == MO_MachineBasicBlock; }





From lattner at cs.uiuc.edu  Mon Sep  4 18:35:37 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 4 Sep 2006 18:35:37 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineInstr.h
Message-ID: <200609042335.k84NZb5X016895@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

MachineInstr.h updated: 1.183 -> 1.184
---
Log message:

ADd getImm/setImm methods


---
Diffs of the changes:  (+15 -6)

 MachineInstr.h |   21 +++++++++++++++------
 1 files changed, 15 insertions(+), 6 deletions(-)


Index: llvm/include/llvm/CodeGen/MachineInstr.h
diff -u llvm/include/llvm/CodeGen/MachineInstr.h:1.183 llvm/include/llvm/CodeGen/MachineInstr.h:1.184
--- llvm/include/llvm/CodeGen/MachineInstr.h:1.183	Mon Sep  4 18:05:29 2006
+++ llvm/include/llvm/CodeGen/MachineInstr.h	Mon Sep  4 18:35:22 2006
@@ -124,8 +124,13 @@
   bool isGlobalAddress() const { return opType == MO_GlobalAddress; }
   bool isExternalSymbol() const { return opType == MO_ExternalSymbol; }
 
+  int64_t getImm() const {
+    assert(isImm() && "Wrong MachineOperand accessor");
+    return contents.immedVal;
+  }
+  
   int64_t getImmedValue() const {
-    assert(isImmediate() && "Wrong MachineOperand accessor");
+    assert(isImm() && "Wrong MachineOperand accessor");
     return contents.immedVal;
   }
   MachineBasicBlock *getMachineBasicBlock() const {
@@ -165,10 +170,10 @@
   /// MachineOperand methods for testing that work on any kind of
   /// MachineOperand...
   ///
-  bool            isUse           () const { return flags & USEFLAG; }
-  MachineOperand& setUse          ()       { flags |= USEFLAG; return *this; }
-  bool            isDef           () const { return flags & DEFFLAG; }
-  MachineOperand& setDef          ()       { flags |= DEFFLAG; return *this; }
+  bool isUse() const { return flags & USEFLAG; }
+  bool isDef() const { return flags & DEFFLAG; }
+  MachineOperand &setUse() { flags |= USEFLAG; return *this; }
+  MachineOperand &setDef() { flags |= DEFFLAG; return *this; }
 
   /// getReg - Returns the register number.
   ///
@@ -185,7 +190,11 @@
   }
 
   void setImmedValue(int64_t immVal) {
-    assert(isImmediate() && "Wrong MachineOperand mutator");
+    assert(isImm() && "Wrong MachineOperand mutator");
+    contents.immedVal = immVal;
+  }
+  void setImm(int64_t immVal) {
+    assert(isImm() && "Wrong MachineOperand mutator");
     contents.immedVal = immVal;
   }
 





From isanbard at gmail.com  Mon Sep  4 18:36:06 2006
From: isanbard at gmail.com (Bill Wendling)
Date: Mon, 4 Sep 2006 18:36:06 -0500
Subject: [llvm-commits] CVS: llvm/docs/CodeGenerator.html
Message-ID: <200609042336.k84Na62D016959@zion.cs.uiuc.edu>



Changes in directory llvm/docs:

CodeGenerator.html updated: 1.35 -> 1.36
---
Log message:

First draft of the "Live Interval Analysis" section. This is the "Live
Variable Analysis" pass.


---
Diffs of the changes:  (+189 -1)

 CodeGenerator.html |  190 ++++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 files changed, 189 insertions(+), 1 deletion(-)


Index: llvm/docs/CodeGenerator.html
diff -u llvm/docs/CodeGenerator.html:1.35 llvm/docs/CodeGenerator.html:1.36
--- llvm/docs/CodeGenerator.html:1.35	Fri Sep  1 16:47:10 2006
+++ llvm/docs/CodeGenerator.html	Mon Sep  4 18:35:52 2006
@@ -58,6 +58,10 @@
       <li><a href="#selectiondag_future">Future directions for the
                                          SelectionDAG</a></li>
       </ul></li>
+     <li><a href="#liveinterval_analysis">Live Interval Analysis</a>
+       <ul>
+       <li><a href="#livevariable_analysis">Live Variable Analysis</a></li>
+       </ul></li>
     <li><a href="#regalloc">Register Allocation</a>
       <ul>
       <li><a href="#regAlloc_represent">How registers are represented in
@@ -1156,6 +1160,190 @@
 
 <!-- ======================================================================= -->
 <div class="doc_subsection">
+  <a name="liveinterval_analysis">Live Interval Analysis</a>
+</div>
+
+<div class="doc_text">
+
+<p>Live Interval Analysis identifies the ranges where a variable is <i>live</i>.
+It's used by the <a href="#regalloc">register allocator pass</a> to determine
+if two or more virtual registers which require the same register are live at
+the same point in the program (conflict). When this situation occurs, one
+virtual register must be <i>spilt</i>.</p>
+
+</div>
+
+<!-- _______________________________________________________________________ -->
+<div class="doc_subsubsection">
+  <a name="livevariable_analysis">Live Variable Analysis</a>
+</div>
+
+<div class="doc_text">
+
+<p>The first step to determining the live intervals of variables is to
+calculate the set of registers that are immediately dead after the
+instruction (i.e., the instruction calculates the value, but it is never
+used) and the set of registers that are used by the instruction, but are
+never used after the instruction (i.e., they are killed). Live variable
+information is computed for each <i>virtual</i> and <i>register
+allocatable</i> physical register in the function.  LLVM assumes that
+physical registers are only live within a single basic block.  This allows
+it to do a single, local analysis to resolve physical register lifetimes in
+each basic block. If a physical register is not register allocatable (e.g.,
+a stack pointer or condition codes), it is not tracked.</p>
+
+<p>Physical registers may be live in to or out of a function. Live in values
+are typically arguments in register. Live out values are typically return
+values in registers. Live in values are marked as such, and are given a dummy
+"defining" instruction during live interval analysis. If the last basic block
+of a function is a <tt>return</tt>, then it's marked as using all live-out
+values in the function.</p>
+
+<p><tt>PHI</tt> nodes need to be handled specially, because the calculation
+of the live variable information from a depth first traversal of the CFG of
+the function won't guarantee that a virtual register is defined before it's
+used. When a <tt>PHI</tt> node is encounted, only the definition is
+handled, because the uses will be handled in other basic blocks.</p>
+
+<p>For each <tt>PHI</tt> node of the current basic block, we simulate an
+assignment at the end of the current basic block and traverse the successor
+basic blocks. If a successor basic block has a <tt>PHI</tt> node and one of
+the <tt>PHI</tt> node's operands is coming from the current basic block,
+then the variable is marked as <i>alive</i> within the current basic block
+and all of its predecessor basic blocks, until the basic block with the
+defining instruction is encountered.</p>
+
+</div>
+
+<!-- FIXME:
+
+A. General Overview
+B. Describe Default RA (Linear Scan)
+   1. LiveVariable Analysis
+      a. All physical register references presumed dead across BBs
+      b. Mark live-in regs as live-in
+      c. Calculate LV info in DFS order
+         1) We'll see def of vreg before its uses
+         2) PHI nodes are treated specially
+            a) Only handle its def
+            b) Uses handled in other BBs
+         3) Handle all uses and defs
+            a) Handle implicit preg uses
+               (1) "TargetInstrDescriptor" from "TargetInstructionInfo"
+            b) Handle explicit preg and vreg uses
+            c) Handle implicit preg defs
+               (1) "TargetInstrDescriptor" from "TargetInstructionInfo"
+            d) Handle explicit preg and vreg defs
+         4) Use of vreg marks it killed (last use in BB)
+            a) Updates (expands) live range
+            b) Marks vreg as alive in dominating blocks
+         5) Use of preg updates info and used tables
+         6) Def of vreg defaults to "dead"
+            a) Expanded later (see B.1.c.4)
+         7) Def of preg updates info, used, RegsKilled, and RegsDead tables.
+         8) Handle virt assigns from PHI nodes at the bottom of the BB
+            a) If successor block has PHI nodes
+               (1) Simulate an assignment at the end of current BB
+                   (i.e., mark it as alive in current BB)
+         9) If last block is a "return"
+            a) Mark it as using all live-out values
+         10) Kill all pregs available at the end of the BB
+      d. Update "RegistersDead" and "RegistersKilled"
+         1) RegistersDead - This map keeps track of all of the registers that
+            are dead immediately after an instruction executes, which are not
+            dead after the operands are evaluated.  In practice, this only
+            contains registers which are defined by an instruction, but never
+            used.
+         2) RegistersKilled - This map keeps track of all of the registers that
+            are dead immediately after an instruction reads its operands.  If an
+            instruction does not have an entry in this map, it kills no
+            registers.
+   2. LiveInterval Analysis
+      a. Use LV pass to conservatively compute live intervals for vregs and pregs
+      b. For some ordering of the machine instrs [1,N], a live interval is an
+         interval [i,j) where 1 <= i <= j < N for which a variable is live
+      c. Function has live ins
+         1) Insert dummy instr at beginning
+         2) Pretend dummy instr "defines" values
+      d. Number each machine instruction -- depth-first order
+         1) An interval [i, j) == Live interval for reg v if there is no
+            instr with num j' > j s.t. v is live at j' and there is no instr
+            with number i' < i s.t. v is live at i'
+         2) Intervals can have holes: [1,20), [50,65), [1000,1001)
+      e. Handle line-in values
+      f. Compute live intervals
+         1) Each live range is assigned a value num within the live interval
+         2) vreg
+            a) May be defined multiple times (due to phi and 2-addr elimination)
+            b) Live only within defining BB
+               (1) Single kill after def in BB
+            c) Lives to end of defining BB, potentially across some BBs
+               (1) Add range that goes from def to end of defining BB
+               (2) Iterate over all BBs that the var is completely live in
+                   (a) add [instrIndex(begin), InstrIndex(end)+4) to LI
+               (3) Vreg is live from start of any killing block to 'use'
+            d) If seeing vreg again (because of phi or 2-addr elimination)
+               (1) If 2-addr elim, then vreg is 1st op and a def-and-use
+                   (a) Didn't realize there are 2 values in LI
+                   (b) Need to take LR that defs vreg and split it into 2 vals
+                       (1) Delete initial value (from first def to redef)
+                       (2) Get new value num (#1)
+                       (3) Value#0 is now defined by the 2-addr instr
+                       (4) Add new LR which replaces the range for input copy
+               (2) Else phi-elimination
+                   (a) If first redef of vreg, change LR in PHI block to be
+                       a different Value Number
+                   (b) Each variable def is only live until the end of the BB
+         3) preg
+            a) Cannot be live across BB
+            b) Lifetime must end somewhere in its defining BB
+            c) Dead at def instr, if not used after def
+               (1) Interval: [defSlot(def), defSlot(def) + 1)
+            d) Killed by subsequent instr, if not dead on def
+               (1) Interval: [defSlot(def), useSlot(kill) + 1)
+            e) If neither, then it's live-in to func and never used
+               (1) Interval: [start, start + 1)
+      e. Join intervals
+      f. Compute spill weights
+      g. Coalesce vregs
+      h. Remove identity moves
+   3. Linear Scan RA
+      a. 
+
+
+  /// VarInfo - This represents the regions where a virtual register is live in
+  /// the program.  We represent this with three different pieces of
+  /// information: the instruction that uniquely defines the value, the set of
+  /// blocks the instruction is live into and live out of, and the set of 
+  /// non-phi instructions that are the last users of the value.
+  ///
+  /// In the common case where a value is defined and killed in the same block,
+  /// DefInst is the defining inst, there is one killing instruction, and 
+  /// AliveBlocks is empty.
+  ///
+  /// Otherwise, the value is live out of the block.  If the value is live
+  /// across any blocks, these blocks are listed in AliveBlocks.  Blocks where
+  /// the liveness range ends are not included in AliveBlocks, instead being
+  /// captured by the Kills set.  In these blocks, the value is live into the
+  /// block (unless the value is defined and killed in the same block) and lives
+  /// until the specified instruction.  Note that there cannot ever be a value
+  /// whose Kills set contains two instructions from the same basic block.
+  ///
+  /// PHI nodes complicate things a bit.  If a PHI node is the last user of a
+  /// value in one of its predecessor blocks, it is not listed in the kills set,
+  /// but does include the predecessor block in the AliveBlocks set (unless that
+  /// block also defines the value).  This leads to the (perfectly sensical)
+  /// situation where a value is defined in a block, and the last use is a phi
+  /// node in the successor.  In this case, DefInst will be the defining
+  /// instruction, AliveBlocks is empty (the value is not live across any 
+  /// blocks) and Kills is empty (phi nodes are not included).  This is sensical
+  /// because the value must be live to the end of the block, but is not live in
+  /// any successor blocks.
+
+ -->
+
+<!-- ======================================================================= -->
+<div class="doc_subsection">
   <a name="regalloc">Register Allocation</a>
 </div>
 
@@ -1624,7 +1812,7 @@
 
   <a href="mailto:sabre at nondot.org">Chris Lattner</a><br>
   <a href="http://llvm.org">The LLVM Compiler Infrastructure</a><br>
-  Last modified: $Date: 2006/09/01 21:47:10 $
+  Last modified: $Date: 2006/09/04 23:35:52 $
 </address>
 
 </body>





From alenhar2 at cs.uiuc.edu  Mon Sep  4 19:22:39 2006
From: alenhar2 at cs.uiuc.edu (Andrew Lenharth)
Date: Mon, 4 Sep 2006 19:22:39 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelLowering.cpp
Message-ID: <200609050022.k850MdLV017644@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaISelLowering.cpp updated: 1.58 -> 1.59
---
Log message:

jmp_bufs are this big on alpha.

---
Diffs of the changes:  (+3 -0)

 AlphaISelLowering.cpp |    3 +++
 1 files changed, 3 insertions(+)


Index: llvm/lib/Target/Alpha/AlphaISelLowering.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.58 llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.59
--- llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.58	Fri Aug 11 12:38:39 2006
+++ llvm/lib/Target/Alpha/AlphaISelLowering.cpp	Mon Sep  4 19:22:25 2006
@@ -135,6 +135,9 @@
   addLegalFPImmediate(+0.0); //F31
   addLegalFPImmediate(-0.0); //-F31
 
+  setJumpBufSize(272);
+  setJumpBufAlignment(16);
+
   computeRegisterProperties();
 
   useITOF = TM.getSubtarget<AlphaSubtarget>().hasF2I();





From lattner at cs.uiuc.edu  Mon Sep  4 21:12:19 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 4 Sep 2006 21:12:19 -0500
Subject: [llvm-commits] CVS: llvm/utils/TableGen/AsmWriterEmitter.cpp
Message-ID: <200609050212.k852CJ7G019676@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

AsmWriterEmitter.cpp updated: 1.40 -> 1.41
---
Log message:

Fix a long-standing wart in the code generator: two-address instruction lowering
actually *removes* one of the operands, instead of just assigning both operands
the same register.  This make reasoning about instructions unnecessarily complex,
because you need to know if you are before or after register allocation to match
up operand #'s with the target description file.

Changing this also gets rid of a bunch of hacky code in various places.

This patch also includes changes to fold loads into cmp/test instructions in
the X86 backend, along with a significant simplification to the X86 spill 
folding code.


---
Diffs of the changes:  (+5 -8)

 AsmWriterEmitter.cpp |   13 +++++--------
 1 files changed, 5 insertions(+), 8 deletions(-)


Index: llvm/utils/TableGen/AsmWriterEmitter.cpp
diff -u llvm/utils/TableGen/AsmWriterEmitter.cpp:1.40 llvm/utils/TableGen/AsmWriterEmitter.cpp:1.41
--- llvm/utils/TableGen/AsmWriterEmitter.cpp:1.40	Tue Jul 18 20:39:06 2006
+++ llvm/utils/TableGen/AsmWriterEmitter.cpp	Mon Sep  4 21:12:02 2006
@@ -211,15 +211,12 @@
       unsigned OpNo = CGI.getOperandNamed(VarName);
       CodeGenInstruction::OperandInfo OpInfo = CGI.OperandList[OpNo];
 
-      // If this is a two-address instruction and we are not accessing the
-      // 0th operand, remove an operand.
+      // If this is a two-address instruction, verify the second operand isn't
+      // used.
       unsigned MIOp = OpInfo.MIOperandNo;
-      if (CGI.isTwoAddress && MIOp != 0) {
-        if (MIOp == 1)
-          throw "Should refer to operand #0 instead of #1 for two-address"
-            " instruction '" + CGI.TheDef->getName() + "'!";
-        --MIOp;
-      }
+      if (CGI.isTwoAddress && MIOp == 1)
+        throw "Should refer to operand #0 instead of #1 for two-address"
+              " instruction '" + CGI.TheDef->getName() + "'!";
 
       if (CurVariant == Variant || CurVariant == ~0U) 
         Operands.push_back(AsmWriterOperand(OpInfo.PrinterMethodName, MIOp,





From lattner at cs.uiuc.edu  Mon Sep  4 21:12:18 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 4 Sep 2006 21:12:18 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/LiveIntervalAnalysis.cpp
	RegAllocSimple.cpp TwoAddressInstructionPass.cpp
	VirtRegMap.cpp VirtRegMap.h
Message-ID: <200609050212.k852CI65019671@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen:

LiveIntervalAnalysis.cpp updated: 1.185 -> 1.186
RegAllocSimple.cpp updated: 1.73 -> 1.74
TwoAddressInstructionPass.cpp updated: 1.37 -> 1.38
VirtRegMap.cpp updated: 1.72 -> 1.73
VirtRegMap.h updated: 1.21 -> 1.22
---
Log message:

Fix a long-standing wart in the code generator: two-address instruction lowering
actually *removes* one of the operands, instead of just assigning both operands
the same register.  This make reasoning about instructions unnecessarily complex,
because you need to know if you are before or after register allocation to match
up operand #'s with the target description file.

Changing this also gets rid of a bunch of hacky code in various places.

This patch also includes changes to fold loads into cmp/test instructions in
the X86 backend, along with a significant simplification to the X86 spill 
folding code.


---
Diffs of the changes:  (+99 -109)

 LiveIntervalAnalysis.cpp      |   90 ++++++++++++++++++++------------------
 RegAllocSimple.cpp            |    6 --
 TwoAddressInstructionPass.cpp |    5 --
 VirtRegMap.cpp                |   99 ++++++++++++++++++------------------------
 VirtRegMap.h                  |    8 +--
 5 files changed, 99 insertions(+), 109 deletions(-)


Index: llvm/lib/CodeGen/LiveIntervalAnalysis.cpp
diff -u llvm/lib/CodeGen/LiveIntervalAnalysis.cpp:1.185 llvm/lib/CodeGen/LiveIntervalAnalysis.cpp:1.186
--- llvm/lib/CodeGen/LiveIntervalAnalysis.cpp:1.185	Mon Sep  4 13:27:40 2006
+++ llvm/lib/CodeGen/LiveIntervalAnalysis.cpp	Mon Sep  4 21:12:02 2006
@@ -262,23 +262,11 @@
 
       MachineInstr *MI = getInstructionFromIndex(index);
 
-      // NewRegLiveIn - This instruction might have multiple uses of the spilled
-      // register.  In this case, for the first use, keep track of the new vreg
-      // that we reload it into.  If we see a second use, reuse this vreg
-      // instead of creating live ranges for two reloads.
-      unsigned NewRegLiveIn = 0;
-
-    for_operand:
+    RestartInstruction:
       for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
         MachineOperand& mop = MI->getOperand(i);
         if (mop.isRegister() && mop.getReg() == li.reg) {
-          if (NewRegLiveIn && mop.isUse()) {
-            // We already emitted a reload of this value, reuse it for
-            // subsequent operands.
-            MI->getOperand(i).setReg(NewRegLiveIn);
-            DEBUG(std::cerr << "\t\t\t\treused reload into reg" << NewRegLiveIn
-                            << " for operand #" << i << '\n');
-          } else if (MachineInstr* fmi = mri_->foldMemoryOperand(MI, i, slot)) {
+          if (MachineInstr *fmi = mri_->foldMemoryOperand(MI, i, slot)) {
             // Attempt to fold the memory reference into the instruction.  If we
             // can do this, we don't need to insert spill code.
             if (lv_)
@@ -292,47 +280,63 @@
             ++numFolded;
             // Folding the load/store can completely change the instruction in
             // unpredictable ways, rescan it from the beginning.
-            goto for_operand;
+            goto RestartInstruction;
           } else {
-            // This is tricky. We need to add information in the interval about
-            // the spill code so we have to use our extra load/store slots.
+            // Create a new virtual register for the spill interval.
+            unsigned NewVReg = mf_->getSSARegMap()->createVirtualRegister(rc);
+            
+            // Scan all of the operands of this instruction rewriting operands
+            // to use NewVReg instead of li.reg as appropriate.  We do this for
+            // two reasons:
             //
-            // If we have a use we are going to have a load so we start the
-            // interval from the load slot onwards. Otherwise we start from the
-            // def slot.
-            unsigned start = (mop.isUse() ?
-                              getLoadIndex(index) :
-                              getDefIndex(index));
-            // If we have a def we are going to have a store right after it so
-            // we end the interval after the use of the next
-            // instruction. Otherwise we end after the use of this instruction.
-            unsigned end = 1 + (mop.isDef() ?
-                                getStoreIndex(index) :
-                                getUseIndex(index));
+            //   1. If the instr reads the same spilled vreg multiple times, we
+            //      want to reuse the NewVReg.
+            //   2. If the instr is a two-addr instruction, we are required to
+            //      keep the src/dst regs pinned.
+            //
+            // Keep track of whether we replace a use and/or def so that we can
+            // create the spill interval with the appropriate range. 
+            mop.setReg(NewVReg);
+            
+            bool HasUse = mop.isUse();
+            bool HasDef = mop.isDef();
+            for (unsigned j = i+1, e = MI->getNumOperands(); j != e; ++j) {
+              if (MI->getOperand(j).isReg() &&
+                  MI->getOperand(j).getReg() == li.reg) {
+                MI->getOperand(j).setReg(NewVReg);
+                HasUse |= MI->getOperand(j).isUse();
+                HasDef |= MI->getOperand(j).isDef();
+              }
+            }
 
             // create a new register for this spill
-            NewRegLiveIn = mf_->getSSARegMap()->createVirtualRegister(rc);
-            MI->getOperand(i).setReg(NewRegLiveIn);
             vrm.grow();
-            vrm.assignVirt2StackSlot(NewRegLiveIn, slot);
-            LiveInterval& nI = getOrCreateInterval(NewRegLiveIn);
+            vrm.assignVirt2StackSlot(NewVReg, slot);
+            LiveInterval &nI = getOrCreateInterval(NewVReg);
             assert(nI.empty());
 
             // the spill weight is now infinity as it
             // cannot be spilled again
             nI.weight = float(HUGE_VAL);
-            LiveRange LR(start, end, nI.getNextValue(~0U, 0));
-            DEBUG(std::cerr << " +" << LR);
-            nI.addRange(LR);
+
+            if (HasUse) {
+              LiveRange LR(getLoadIndex(index), getUseIndex(index),
+                           nI.getNextValue(~0U, 0));
+              DEBUG(std::cerr << " +" << LR);
+              nI.addRange(LR);
+            }
+            if (HasDef) {
+              LiveRange LR(getDefIndex(index), getStoreIndex(index),
+                           nI.getNextValue(~0U, 0));
+              DEBUG(std::cerr << " +" << LR);
+              nI.addRange(LR);
+            }
+            
             added.push_back(&nI);
 
             // update live variables if it is available
             if (lv_)
-              lv_->addVirtualRegisterKilled(NewRegLiveIn, MI);
-            
-            // If this is a live in, reuse it for subsequent live-ins.  If it's
-            // a def, we can't do this.
-            if (!mop.isUse()) NewRegLiveIn = 0;
+              lv_->addVirtualRegisterKilled(NewVReg, MI);
             
             DEBUG(std::cerr << "\t\t\t\tadded new interval: ";
                   nI.print(std::cerr, mri_); std::cerr << '\n');
@@ -445,7 +449,9 @@
     // operand, and is a def-and-use.
     if (mi->getOperand(0).isRegister() &&
         mi->getOperand(0).getReg() == interval.reg &&
-        mi->getOperand(0).isDef() && mi->getOperand(0).isUse()) {
+        mi->getNumOperands() > 1 && mi->getOperand(1).isRegister() && 
+        mi->getOperand(1).getReg() == interval.reg &&
+        mi->getOperand(0).isDef() && mi->getOperand(1).isUse()) {
       // If this is a two-address definition, then we have already processed
       // the live range.  The only problem is that we didn't realize there
       // are actually two values in the live interval.  Because of this we


Index: llvm/lib/CodeGen/RegAllocSimple.cpp
diff -u llvm/lib/CodeGen/RegAllocSimple.cpp:1.73 llvm/lib/CodeGen/RegAllocSimple.cpp:1.74
--- llvm/lib/CodeGen/RegAllocSimple.cpp:1.73	Sun Aug 27 07:54:01 2006
+++ llvm/lib/CodeGen/RegAllocSimple.cpp	Mon Sep  4 21:12:02 2006
@@ -203,17 +203,13 @@
               physReg = getFreeReg(virtualReg);
             } else {
               // must be same register number as the first operand
-              // This maps a = b + c into b += c, and saves b into a's spot
+              // This maps a = b + c into b = b + c, and saves b into a's spot.
               assert(MI->getOperand(1).isRegister()  &&
                      MI->getOperand(1).getReg() &&
                      MI->getOperand(1).isUse() &&
                      "Two address instruction invalid!");
 
               physReg = MI->getOperand(1).getReg();
-              spillVirtReg(MBB, next(MI), virtualReg, physReg);
-              MI->getOperand(1).setDef();
-              MI->RemoveOperand(0);
-              break; // This is the last operand to process
             }
             spillVirtReg(MBB, next(MI), virtualReg, physReg);
           } else {


Index: llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
diff -u llvm/lib/CodeGen/TwoAddressInstructionPass.cpp:1.37 llvm/lib/CodeGen/TwoAddressInstructionPass.cpp:1.38
--- llvm/lib/CodeGen/TwoAddressInstructionPass.cpp:1.37	Sun Aug 27 07:54:01 2006
+++ llvm/lib/CodeGen/TwoAddressInstructionPass.cpp	Mon Sep  4 21:12:02 2006
@@ -206,9 +206,8 @@
         }
       }
 
-      assert(mi->getOperand(0).isDef());
-      mi->getOperand(0).setUse();
-      mi->RemoveOperand(1);
+      assert(mi->getOperand(0).isDef() && mi->getOperand(1).isUse());
+      mi->getOperand(1).setReg(mi->getOperand(0).getReg());
       MadeChange = true;
 
       DEBUG(std::cerr << "\t\trewrite to:\t"; mi->print(std::cerr, &TM));


Index: llvm/lib/CodeGen/VirtRegMap.cpp
diff -u llvm/lib/CodeGen/VirtRegMap.cpp:1.72 llvm/lib/CodeGen/VirtRegMap.cpp:1.73
--- llvm/lib/CodeGen/VirtRegMap.cpp:1.72	Sun Aug 27 07:54:01 2006
+++ llvm/lib/CodeGen/VirtRegMap.cpp	Mon Sep  4 21:12:02 2006
@@ -57,6 +57,12 @@
 //  VirtRegMap implementation
 //===----------------------------------------------------------------------===//
 
+VirtRegMap::VirtRegMap(MachineFunction &mf)
+  : TII(*mf.getTarget().getInstrInfo()), MF(mf), 
+    Virt2PhysMap(NO_PHYS_REG), Virt2StackSlotMap(NO_STACK_SLOT) {
+  grow();
+}
+
 void VirtRegMap::grow() {
   Virt2PhysMap.grow(MF.getSSARegMap()->getLastVirtReg());
   Virt2StackSlotMap.grow(MF.getSSARegMap()->getLastVirtReg());
@@ -92,11 +98,13 @@
   }
 
   ModRef MRInfo;
-  if (!OldMI->getOperand(OpNo).isDef()) {
-    assert(OldMI->getOperand(OpNo).isUse() && "Operand is not use or def?");
-    MRInfo = isRef;
+  if (OpNo < 2 && TII.isTwoAddrInstr(OldMI->getOpcode())) {
+    // Folded a two-address operand.
+    MRInfo = isModRef;
+  } else if (OldMI->getOperand(OpNo).isDef()) {
+    MRInfo = isMod;
   } else {
-    MRInfo = OldMI->getOperand(OpNo).isUse() ? isModRef : isMod;
+    MRInfo = isRef;
   }
 
   // add new memory reference
@@ -492,11 +500,6 @@
   // that we can choose to reuse the physregs instead of emitting reloads.
   AvailableSpills Spills(MRI, TII);
   
-  // DefAndUseVReg - When we see a def&use operand that is spilled, keep track
-  // of it.  ".first" is the machine operand index (should always be 0 for now),
-  // and ".second" is the virtual register that is spilled.
-  std::vector<std::pair<unsigned, unsigned> > DefAndUseVReg;
-
   // MaybeDeadStores - When we need to write a value back into a stack slot,
   // keep track of the inserted store.  If the stack slot value is never read
   // (because the value was used from some available register, for example), and
@@ -516,8 +519,6 @@
     /// reuse.
     ReuseInfo ReusedOperands(MI);
     
-    DefAndUseVReg.clear();
-
     // Process all of the spilled uses and all non spilled reg references.
     for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
       MachineOperand &MO = MI.getOperand(i);
@@ -547,24 +548,27 @@
       if (!MO.isUse())
         continue;  // Handle defs in the loop below (handle use&def here though)
 
-      // If this is both a def and a use, we need to emit a store to the
-      // stack slot after the instruction.  Keep track of D&U operands
-      // because we are about to change it to a physreg here.
-      if (MO.isDef()) {
-        // Remember that this was a def-and-use operand, and that the
-        // stack slot is live after this instruction executes.
-        DefAndUseVReg.push_back(std::make_pair(i, VirtReg));
-      }
-      
       int StackSlot = VRM.getStackSlot(VirtReg);
       unsigned PhysReg;
 
       // Check to see if this stack slot is available.
       if ((PhysReg = Spills.getSpillSlotPhysReg(StackSlot))) {
 
-        // Don't reuse it for a def&use operand if we aren't allowed to change
-        // the physreg!
-        if (!MO.isDef() || Spills.canClobberPhysReg(StackSlot)) {
+        // This spilled operand might be part of a two-address operand.  If this
+        // is the case, then changing it will necessarily require changing the 
+        // def part of the instruction as well.  However, in some cases, we
+        // aren't allowed to modify the reused register.  If none of these cases
+        // apply, reuse it.
+        bool CanReuse = true;
+        if (i == 1 && MI.getOperand(0).isReg() && 
+            MI.getOperand(0).getReg() == VirtReg &&
+            TII->isTwoAddrInstr(MI.getOpcode())) {
+          // Okay, we have a two address operand.  We can reuse this physreg as
+          // long as we are allowed to clobber the value.
+          CanReuse = Spills.canClobberPhysReg(StackSlot);
+        }
+        
+        if (CanReuse) {
           // If this stack slot value is already available, reuse it!
           DEBUG(std::cerr << "Reusing SS#" << StackSlot << " from physreg "
                           << MRI->getName(PhysReg) << " for vreg"
@@ -777,47 +781,32 @@
         unsigned VirtReg = MO.getReg();
 
         if (!MRegisterInfo::isVirtualRegister(VirtReg)) {
-          // Check to see if this is a def-and-use vreg operand that we do need
-          // to insert a store for.
-          bool OpTakenCareOf = false;
-          if (MO.isUse() && !DefAndUseVReg.empty()) {
-            for (unsigned dau = 0, e = DefAndUseVReg.size(); dau != e; ++dau)
-              if (DefAndUseVReg[dau].first == i) {
-                VirtReg = DefAndUseVReg[dau].second;
-                OpTakenCareOf = true;
-                break;
-              }
-          }
-
-          if (!OpTakenCareOf) {
-            // Check to see if this is a noop copy.  If so, eliminate the
-            // instruction before considering the dest reg to be changed.
-            unsigned Src, Dst;
-            if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
-              ++NumDCE;
-              DEBUG(std::cerr << "Removing now-noop copy: " << MI);
-              MBB.erase(&MI);
-              VRM.RemoveFromFoldedVirtMap(&MI);
-              goto ProcessNextInst;
-            }
-            Spills.ClobberPhysReg(VirtReg);
-            continue;
+          // Check to see if this is a noop copy.  If so, eliminate the
+          // instruction before considering the dest reg to be changed.
+          unsigned Src, Dst;
+          if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
+            ++NumDCE;
+            DEBUG(std::cerr << "Removing now-noop copy: " << MI);
+            MBB.erase(&MI);
+            VRM.RemoveFromFoldedVirtMap(&MI);
+            goto ProcessNextInst;
           }
+          Spills.ClobberPhysReg(VirtReg);
+          continue;
         }
 
         // The only vregs left are stack slot definitions.
         int StackSlot = VRM.getStackSlot(VirtReg);
         const TargetRegisterClass *RC =
           MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
-        unsigned PhysReg;
 
-        // If this is a def&use operand, and we used a different physreg for
-        // it than the one assigned, make sure to execute the store from the
-        // correct physical register.
-        if (MO.getReg() == VirtReg)
-          PhysReg = VRM.getPhys(VirtReg);
+        // If this def is part of a two-address operand, make sure to execute
+        // the store from the correct physical register.
+        unsigned PhysReg;
+        if (i == 0 && TII->isTwoAddrInstr(MI.getOpcode()))
+          PhysReg = MI.getOperand(1).getReg();
         else
-          PhysReg = MO.getReg();
+          PhysReg = VRM.getPhys(VirtReg);
 
         PhysRegsUsed[PhysReg] = true;
         MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);


Index: llvm/lib/CodeGen/VirtRegMap.h
diff -u llvm/lib/CodeGen/VirtRegMap.h:1.21 llvm/lib/CodeGen/VirtRegMap.h:1.22
--- llvm/lib/CodeGen/VirtRegMap.h:1.21	Mon May  1 17:03:24 2006
+++ llvm/lib/CodeGen/VirtRegMap.h	Mon Sep  4 21:12:02 2006
@@ -23,6 +23,7 @@
 
 namespace llvm {
   class MachineInstr;
+  class TargetInstrInfo;
 
   class VirtRegMap {
   public:
@@ -31,6 +32,8 @@
                           std::pair<unsigned, ModRef> > MI2VirtMapTy;
 
   private:
+    const TargetInstrInfo &TII;
+
     MachineFunction &MF;
     /// Virt2PhysMap - This is a virtual to physical register
     /// mapping. Each virtual register is required to have an entry in
@@ -58,10 +61,7 @@
     };
 
   public:
-    VirtRegMap(MachineFunction &mf)
-      : MF(mf), Virt2PhysMap(NO_PHYS_REG), Virt2StackSlotMap(NO_STACK_SLOT) {
-      grow();
-    }
+    VirtRegMap(MachineFunction &mf);
 
     void grow();
 





From lattner at cs.uiuc.edu  Mon Sep  4 21:12:19 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 4 Sep 2006 21:12:19 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.cpp
	X86RegisterInfo.cpp X86RegisterInfo.h
Message-ID: <200609050212.k852CJwf019685@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86InstrInfo.cpp updated: 1.58 -> 1.59
X86RegisterInfo.cpp updated: 1.163 -> 1.164
X86RegisterInfo.h updated: 1.39 -> 1.40
---
Log message:

Fix a long-standing wart in the code generator: two-address instruction lowering
actually *removes* one of the operands, instead of just assigning both operands
the same register.  This make reasoning about instructions unnecessarily complex,
because you need to know if you are before or after register allocation to match
up operand #'s with the target description file.

Changing this also gets rid of a bunch of hacky code in various places.

This patch also includes changes to fold loads into cmp/test instructions in
the X86 backend, along with a significant simplification to the X86 spill 
folding code.


---
Diffs of the changes:  (+472 -486)

 X86InstrInfo.cpp    |    2 
 X86RegisterInfo.cpp |  948 +++++++++++++++++++++++++---------------------------
 X86RegisterInfo.h   |    8 
 3 files changed, 472 insertions(+), 486 deletions(-)


Index: llvm/lib/Target/X86/X86InstrInfo.cpp
diff -u llvm/lib/Target/X86/X86InstrInfo.cpp:1.58 llvm/lib/Target/X86/X86InstrInfo.cpp:1.59
--- llvm/lib/Target/X86/X86InstrInfo.cpp:1.58	Tue Jul 25 15:25:40 2006
+++ llvm/lib/Target/X86/X86InstrInfo.cpp	Mon Sep  4 21:12:02 2006
@@ -22,7 +22,7 @@
 
 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
   : TargetInstrInfo(X86Insts, sizeof(X86Insts)/sizeof(X86Insts[0])),
-    TM(tm) {
+    TM(tm), RI(*this) {
 }
 
 


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.163 llvm/lib/Target/X86/X86RegisterInfo.cpp:1.164
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.163	Thu Aug 17 17:00:08 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp	Mon Sep  4 21:12:02 2006
@@ -46,8 +46,8 @@
                     cl::Hidden);
 }
 
-X86RegisterInfo::X86RegisterInfo()
-  : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP) {}
+X86RegisterInfo::X86RegisterInfo(const TargetInstrInfo &tii)
+  : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP), TII(tii) {}
 
 void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
                                           MachineBasicBlock::iterator MI,
@@ -139,39 +139,46 @@
   BuildMI(MBB, MI, Opc, 1, DestReg).addReg(SrcReg);
 }
 
-
-static MachineInstr *MakeMInst(unsigned Opcode, unsigned FrameIndex,
-                               MachineInstr *MI) {
-  return addFrameReference(BuildMI(Opcode, 4), FrameIndex);
-}
-
-static MachineInstr *MakeMRInst(unsigned Opcode, unsigned FrameIndex,
-                                MachineInstr *MI) {
-  return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
-                 .addReg(MI->getOperand(1).getReg());
-}
-
-static MachineInstr *MakeMRIInst(unsigned Opcode, unsigned FrameIndex,
-                                 MachineInstr *MI) {
-  return addFrameReference(BuildMI(Opcode, 6), FrameIndex)
-      .addReg(MI->getOperand(1).getReg())
-      .addImm(MI->getOperand(2).getImmedValue());
+static MachineInstr *FuseTwoAddrInst(unsigned Opcode, unsigned FrameIndex,
+                                     MachineInstr *MI) {
+  unsigned NumOps = MI->getNumOperands()-2;
+  // Create the base instruction with the memory operand as the first part.
+  MachineInstrBuilder MIB = addFrameReference(BuildMI(Opcode, 4+NumOps),
+                                              FrameIndex);
+  
+  // Loop over the rest of the ri operands, converting them over.
+  for (unsigned i = 0; i != NumOps; ++i) {
+    if (MI->getOperand(i+2).isReg())
+      MIB = MIB.addReg(MI->getOperand(i+2).getReg());
+    else {
+      assert(MI->getOperand(i+2).isImm() && "Unknown operand type!");
+      MIB = MIB.addImm(MI->getOperand(i+2).getImm());
+    }
+  }
+  return MIB;
 }
 
-static MachineInstr *MakeMIInst(unsigned Opcode, unsigned FrameIndex,
-                                MachineInstr *MI) {
-  if (MI->getOperand(1).isImmediate())
-    return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
-      .addImm(MI->getOperand(1).getImmedValue());
-  else if (MI->getOperand(1).isGlobalAddress())
-    return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
-      .addGlobalAddress(MI->getOperand(1).getGlobal(),
-                        MI->getOperand(1).getOffset());
-  else if (MI->getOperand(1).isJumpTableIndex())
-    return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
-      .addJumpTableIndex(MI->getOperand(1).getJumpTableIndex());
-  assert(0 && "Unknown operand for MakeMI!");
-  return 0;
+static MachineInstr *FuseInst(unsigned Opcode, unsigned OpNo,
+                              unsigned FrameIndex, MachineInstr *MI) {
+  MachineInstrBuilder MIB = BuildMI(Opcode, MI->getNumOperands()+3);
+  
+  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+    MachineOperand &MO = MI->getOperand(i);
+    if (i == OpNo) {
+      assert(MO.isReg() && "Expected to fold into reg operand!");
+      MIB = addFrameReference(MIB, FrameIndex);
+    } else if (MO.isReg())
+      MIB = MIB.addReg(MO.getReg(), MO.getUseType());
+    else if (MO.isImm())
+      MIB = MIB.addImm(MO.getImm());
+    else if (MO.isGlobalAddress())
+      MIB = MIB.addGlobalAddress(MO.getGlobal(), MO.getOffset());
+    else if (MO.isJumpTableIndex())
+      MIB = MIB.addJumpTableIndex(MO.getJumpTableIndex());
+    else
+      assert(0 && "Unknown operand for FuseInst!");
+  }
+  return MIB;
 }
 
 static MachineInstr *MakeM0Inst(unsigned Opcode, unsigned FrameIndex,
@@ -179,20 +186,6 @@
   return addFrameReference(BuildMI(Opcode, 5), FrameIndex).addImm(0);
 }
 
-static MachineInstr *MakeRMInst(unsigned Opcode, unsigned FrameIndex,
-                                MachineInstr *MI) {
-  const MachineOperand& op = MI->getOperand(0);
-  return addFrameReference(BuildMI(Opcode, 5, op.getReg(), op.getUseType()),
-                           FrameIndex);
-}
-
-static MachineInstr *MakeRMIInst(unsigned Opcode, unsigned FrameIndex,
-                                 MachineInstr *MI) {
-  const MachineOperand& op = MI->getOperand(0);
-  return addFrameReference(BuildMI(Opcode, 6, op.getReg(), op.getUseType()),
-                        FrameIndex).addImm(MI->getOperand(2).getImmedValue());
-}
-
 
 //===----------------------------------------------------------------------===//
 // Efficient Lookup Table Support
@@ -204,8 +197,6 @@
   struct TableEntry {
     unsigned from;                      // Original opcode.
     unsigned to;                        // New opcode.
-    unsigned make;                      // Form of make required to produce the
-                                        // new instruction.
                                         
     // less operators used by STL search.                                    
     bool operator<(const TableEntry &TE) const { return from < TE.from; }
@@ -257,451 +248,451 @@
 #endif
 
 
-MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr* MI,
+MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr *MI,
                                                  unsigned i,
                                                  int FrameIndex) const {
   // Check switch flag 
   if (NoFusing) return NULL;
 
-  // Selection of instruction makes
-  enum {
-    makeM0Inst,
-    makeMIInst,
-    makeMInst,
-    makeMRIInst,
-    makeMRInst,
-    makeRMIInst,
-    makeRMInst
-  };
-  
   // Table (and size) to search
   const TableEntry *OpcodeTablePtr = NULL;
   unsigned OpcodeTableSize = 0;
+  bool isTwoAddrFold = false;
 
-  if (i == 0) { // If operand 0
+  // Folding a memory location into the two-address part of a two-address
+  // instruction is different than folding it other places.  It requires
+  // replacing the *two* registers with the memory location.
+  if (MI->getNumOperands() >= 2 && MI->getOperand(0).isReg() && 
+      MI->getOperand(1).isReg() && i < 2 &&
+      MI->getOperand(0).getReg() == MI->getOperand(1).getReg() &&
+      TII.isTwoAddrInstr(MI->getOpcode())) {
+    static const TableEntry OpcodeTable[] = {
+      { X86::ADC32ri,     X86::ADC32mi },
+      { X86::ADC32ri8,    X86::ADC32mi8 },
+      { X86::ADC32rr,     X86::ADC32mr },
+      { X86::ADD16ri,     X86::ADD16mi },
+      { X86::ADD16ri8,    X86::ADD16mi8 },
+      { X86::ADD16rr,     X86::ADD16mr },
+      { X86::ADD32ri,     X86::ADD32mi },
+      { X86::ADD32ri8,    X86::ADD32mi8 },
+      { X86::ADD32rr,     X86::ADD32mr },
+      { X86::ADD8ri,      X86::ADD8mi },
+      { X86::ADD8rr,      X86::ADD8mr },
+      { X86::AND16ri,     X86::AND16mi },
+      { X86::AND16ri8,    X86::AND16mi8 },
+      { X86::AND16rr,     X86::AND16mr },
+      { X86::AND32ri,     X86::AND32mi },
+      { X86::AND32ri8,    X86::AND32mi8 },
+      { X86::AND32rr,     X86::AND32mr },
+      { X86::AND8ri,      X86::AND8mi },
+      { X86::AND8rr,      X86::AND8mr },
+      { X86::DEC16r,      X86::DEC16m },
+      { X86::DEC32r,      X86::DEC32m },
+      { X86::DEC8r,       X86::DEC8m },
+      { X86::INC16r,      X86::INC16m },
+      { X86::INC32r,      X86::INC32m },
+      { X86::INC8r,       X86::INC8m },
+      { X86::NEG16r,      X86::NEG16m },
+      { X86::NEG32r,      X86::NEG32m },
+      { X86::NEG8r,       X86::NEG8m },
+      { X86::NOT16r,      X86::NOT16m },
+      { X86::NOT32r,      X86::NOT32m },
+      { X86::NOT8r,       X86::NOT8m },
+      { X86::OR16ri,      X86::OR16mi },
+      { X86::OR16ri8,     X86::OR16mi8 },
+      { X86::OR16rr,      X86::OR16mr },
+      { X86::OR32ri,      X86::OR32mi },
+      { X86::OR32ri8,     X86::OR32mi8 },
+      { X86::OR32rr,      X86::OR32mr },
+      { X86::OR8ri,       X86::OR8mi },
+      { X86::OR8rr,       X86::OR8mr },
+      { X86::ROL16r1,     X86::ROL16m1 },
+      { X86::ROL16rCL,    X86::ROL16mCL },
+      { X86::ROL16ri,     X86::ROL16mi },
+      { X86::ROL32r1,     X86::ROL32m1 },
+      { X86::ROL32rCL,    X86::ROL32mCL },
+      { X86::ROL32ri,     X86::ROL32mi },
+      { X86::ROL8r1,      X86::ROL8m1 },
+      { X86::ROL8rCL,     X86::ROL8mCL },
+      { X86::ROL8ri,      X86::ROL8mi },
+      { X86::ROR16r1,     X86::ROR16m1 },
+      { X86::ROR16rCL,    X86::ROR16mCL },
+      { X86::ROR16ri,     X86::ROR16mi },
+      { X86::ROR32r1,     X86::ROR32m1 },
+      { X86::ROR32rCL,    X86::ROR32mCL },
+      { X86::ROR32ri,     X86::ROR32mi },
+      { X86::ROR8r1,      X86::ROR8m1 },
+      { X86::ROR8rCL,     X86::ROR8mCL },
+      { X86::ROR8ri,      X86::ROR8mi },
+      { X86::SAR16r1,     X86::SAR16m1 },
+      { X86::SAR16rCL,    X86::SAR16mCL },
+      { X86::SAR16ri,     X86::SAR16mi },
+      { X86::SAR32r1,     X86::SAR32m1 },
+      { X86::SAR32rCL,    X86::SAR32mCL },
+      { X86::SAR32ri,     X86::SAR32mi },
+      { X86::SAR8r1,      X86::SAR8m1 },
+      { X86::SAR8rCL,     X86::SAR8mCL },
+      { X86::SAR8ri,      X86::SAR8mi },
+      { X86::SBB32ri,     X86::SBB32mi },
+      { X86::SBB32ri8,    X86::SBB32mi8 },
+      { X86::SBB32rr,     X86::SBB32mr },
+      { X86::SHL16r1,     X86::SHL16m1 },
+      { X86::SHL16rCL,    X86::SHL16mCL },
+      { X86::SHL16ri,     X86::SHL16mi },
+      { X86::SHL32r1,     X86::SHL32m1 },
+      { X86::SHL32rCL,    X86::SHL32mCL },
+      { X86::SHL32ri,     X86::SHL32mi },
+      { X86::SHL8r1,      X86::SHL8m1 },
+      { X86::SHL8rCL,     X86::SHL8mCL },
+      { X86::SHL8ri,      X86::SHL8mi },
+      { X86::SHLD16rrCL,  X86::SHLD16mrCL },
+      { X86::SHLD16rri8,  X86::SHLD16mri8 },
+      { X86::SHLD32rrCL,  X86::SHLD32mrCL },
+      { X86::SHLD32rri8,  X86::SHLD32mri8 },
+      { X86::SHR16r1,     X86::SHR16m1 },
+      { X86::SHR16rCL,    X86::SHR16mCL },
+      { X86::SHR16ri,     X86::SHR16mi },
+      { X86::SHR32r1,     X86::SHR32m1 },
+      { X86::SHR32rCL,    X86::SHR32mCL },
+      { X86::SHR32ri,     X86::SHR32mi },
+      { X86::SHR8r1,      X86::SHR8m1 },
+      { X86::SHR8rCL,     X86::SHR8mCL },
+      { X86::SHR8ri,      X86::SHR8mi },
+      { X86::SHRD16rrCL,  X86::SHRD16mrCL },
+      { X86::SHRD16rri8,  X86::SHRD16mri8 },
+      { X86::SHRD32rrCL,  X86::SHRD32mrCL },
+      { X86::SHRD32rri8,  X86::SHRD32mri8 },
+      { X86::SUB16ri,     X86::SUB16mi },
+      { X86::SUB16ri8,    X86::SUB16mi8 },
+      { X86::SUB16rr,     X86::SUB16mr },
+      { X86::SUB32ri,     X86::SUB32mi },
+      { X86::SUB32ri8,    X86::SUB32mi8 },
+      { X86::SUB32rr,     X86::SUB32mr },
+      { X86::SUB8ri,      X86::SUB8mi },
+      { X86::SUB8rr,      X86::SUB8mr },
+      { X86::XOR16ri,     X86::XOR16mi },
+      { X86::XOR16ri8,    X86::XOR16mi8 },
+      { X86::XOR16rr,     X86::XOR16mr },
+      { X86::XOR32ri,     X86::XOR32mi },
+      { X86::XOR32ri8,    X86::XOR32mi8 },
+      { X86::XOR32rr,     X86::XOR32mr },
+      { X86::XOR8ri,      X86::XOR8mi },
+      { X86::XOR8rr,      X86::XOR8mr }
+    };
+    ASSERT_SORTED(OpcodeTable);
+    OpcodeTablePtr = OpcodeTable;
+    OpcodeTableSize = ARRAY_SIZE(OpcodeTable);
+    isTwoAddrFold = true;
+  } else if (i == 0) { // If operand 0
+    if (MI->getOpcode() == X86::MOV16r0)
+      return MakeM0Inst(X86::MOV16mi, FrameIndex, MI);
+    else if (MI->getOpcode() == X86::MOV32r0)
+      return MakeM0Inst(X86::MOV32mi, FrameIndex, MI);
+    else if (MI->getOpcode() == X86::MOV8r0)
+      return MakeM0Inst(X86::MOV8mi, FrameIndex, MI);
+    
     static const TableEntry OpcodeTable[] = {
-      { X86::ADC32ri,     X86::ADC32mi,     makeMIInst },
-      { X86::ADC32ri8,    X86::ADC32mi8,    makeMIInst },
-      { X86::ADC32rr,     X86::ADC32mr,     makeMRInst },
-      { X86::ADD16ri,     X86::ADD16mi,     makeMIInst },
-      { X86::ADD16ri8,    X86::ADD16mi8,    makeMIInst },
-      { X86::ADD16rr,     X86::ADD16mr,     makeMRInst },
-      { X86::ADD32ri,     X86::ADD32mi,     makeMIInst },
-      { X86::ADD32ri8,    X86::ADD32mi8,    makeMIInst },
-      { X86::ADD32rr,     X86::ADD32mr,     makeMRInst },
-      { X86::ADD8ri,      X86::ADD8mi,      makeMIInst },
-      { X86::ADD8rr,      X86::ADD8mr,      makeMRInst },
-      { X86::AND16ri,     X86::AND16mi,     makeMIInst },
-      { X86::AND16ri8,    X86::AND16mi8,    makeMIInst },
-      { X86::AND16rr,     X86::AND16mr,     makeMRInst },
-      { X86::AND32ri,     X86::AND32mi,     makeMIInst },
-      { X86::AND32ri8,    X86::AND32mi8,    makeMIInst },
-      { X86::AND32rr,     X86::AND32mr,     makeMRInst },
-      { X86::AND8ri,      X86::AND8mi,      makeMIInst },
-      { X86::AND8rr,      X86::AND8mr,      makeMRInst },
-      { X86::DEC16r,      X86::DEC16m,      makeMInst },
-      { X86::DEC32r,      X86::DEC32m,      makeMInst },
-      { X86::DEC8r,       X86::DEC8m,       makeMInst },
-      { X86::DIV16r,      X86::DIV16m,      makeMInst },
-      { X86::DIV32r,      X86::DIV32m,      makeMInst },
-      { X86::DIV8r,       X86::DIV8m,       makeMInst },
-      { X86::FsMOVAPDrr,  X86::MOVSDmr,     makeMRInst },
-      { X86::FsMOVAPSrr,  X86::MOVSSmr,     makeMRInst },
-      { X86::IDIV16r,     X86::IDIV16m,     makeMInst },
-      { X86::IDIV32r,     X86::IDIV32m,     makeMInst },
-      { X86::IDIV8r,      X86::IDIV8m,      makeMInst },
-      { X86::IMUL16r,     X86::IMUL16m,     makeMInst },
-      { X86::IMUL32r,     X86::IMUL32m,     makeMInst },
-      { X86::IMUL8r,      X86::IMUL8m,      makeMInst },
-      { X86::INC16r,      X86::INC16m,      makeMInst },
-      { X86::INC32r,      X86::INC32m,      makeMInst },
-      { X86::INC8r,       X86::INC8m,       makeMInst },
-      { X86::MOV16r0,     X86::MOV16mi,     makeM0Inst },
-      { X86::MOV16ri,     X86::MOV16mi,     makeMIInst },
-      { X86::MOV16rr,     X86::MOV16mr,     makeMRInst },
-      { X86::MOV32r0,     X86::MOV32mi,     makeM0Inst },
-      { X86::MOV32ri,     X86::MOV32mi,     makeMIInst },
-      { X86::MOV32rr,     X86::MOV32mr,     makeMRInst },
-      { X86::MOV8r0,      X86::MOV8mi,      makeM0Inst },
-      { X86::MOV8ri,      X86::MOV8mi,      makeMIInst },
-      { X86::MOV8rr,      X86::MOV8mr,      makeMRInst },
-      { X86::MOVAPDrr,    X86::MOVAPDmr,    makeMRInst },
-      { X86::MOVAPSrr,    X86::MOVAPSmr,    makeMRInst },
-      { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, makeMRInst },
-      { X86::MOVPS2SSrr,  X86::MOVPS2SSmr,  makeMRInst },
-      { X86::MOVSDrr,     X86::MOVSDmr,     makeMRInst },
-      { X86::MOVSSrr,     X86::MOVSSmr,     makeMRInst },
-      { X86::MOVUPDrr,    X86::MOVUPDmr,    makeMRInst },
-      { X86::MOVUPSrr,    X86::MOVUPSmr,    makeMRInst },
-      { X86::MUL16r,      X86::MUL16m,      makeMInst },
-      { X86::MUL32r,      X86::MUL32m,      makeMInst },
-      { X86::MUL8r,       X86::MUL8m,       makeMInst },
-      { X86::NEG16r,      X86::NEG16m,      makeMInst },
-      { X86::NEG32r,      X86::NEG32m,      makeMInst },
-      { X86::NEG8r,       X86::NEG8m,       makeMInst },
-      { X86::NOT16r,      X86::NOT16m,      makeMInst },
-      { X86::NOT32r,      X86::NOT32m,      makeMInst },
-      { X86::NOT8r,       X86::NOT8m,       makeMInst },
-      { X86::OR16ri,      X86::OR16mi,      makeMIInst },
-      { X86::OR16ri8,     X86::OR16mi8,     makeMIInst },
-      { X86::OR16rr,      X86::OR16mr,      makeMRInst },
-      { X86::OR32ri,      X86::OR32mi,      makeMIInst },
-      { X86::OR32ri8,     X86::OR32mi8,     makeMIInst },
-      { X86::OR32rr,      X86::OR32mr,      makeMRInst },
-      { X86::OR8ri,       X86::OR8mi,       makeMIInst },
-      { X86::OR8rr,       X86::OR8mr,       makeMRInst },
-      { X86::ROL16r1,     X86::ROL16m1,     makeMInst },
-      { X86::ROL16rCL,    X86::ROL16mCL,    makeMInst },
-      { X86::ROL16ri,     X86::ROL16mi,     makeMIInst },
-      { X86::ROL32r1,     X86::ROL32m1,     makeMInst },
-      { X86::ROL32rCL,    X86::ROL32mCL,    makeMInst },
-      { X86::ROL32ri,     X86::ROL32mi,     makeMIInst },
-      { X86::ROL8r1,      X86::ROL8m1,      makeMInst },
-      { X86::ROL8rCL,     X86::ROL8mCL,     makeMInst },
-      { X86::ROL8ri,      X86::ROL8mi,      makeMIInst },
-      { X86::ROR16r1,     X86::ROR16m1,     makeMInst },
-      { X86::ROR16rCL,    X86::ROR16mCL,    makeMInst },
-      { X86::ROR16ri,     X86::ROR16mi,     makeMIInst },
-      { X86::ROR32r1,     X86::ROR32m1,     makeMInst },
-      { X86::ROR32rCL,    X86::ROR32mCL,    makeMInst },
-      { X86::ROR32ri,     X86::ROR32mi,     makeMIInst },
-      { X86::ROR8r1,      X86::ROR8m1,      makeMInst },
-      { X86::ROR8rCL,     X86::ROR8mCL,     makeMInst },
-      { X86::ROR8ri,      X86::ROR8mi,      makeMIInst },
-      { X86::SAR16r1,     X86::SAR16m1,     makeMInst },
-      { X86::SAR16rCL,    X86::SAR16mCL,    makeMInst },
-      { X86::SAR16ri,     X86::SAR16mi,     makeMIInst },
-      { X86::SAR32r1,     X86::SAR32m1,     makeMInst },
-      { X86::SAR32rCL,    X86::SAR32mCL,    makeMInst },
-      { X86::SAR32ri,     X86::SAR32mi,     makeMIInst },
-      { X86::SAR8r1,      X86::SAR8m1,      makeMInst },
-      { X86::SAR8rCL,     X86::SAR8mCL,     makeMInst },
-      { X86::SAR8ri,      X86::SAR8mi,      makeMIInst },
-      { X86::SBB32ri,     X86::SBB32mi,     makeMIInst },
-      { X86::SBB32ri8,    X86::SBB32mi8,    makeMIInst },
-      { X86::SBB32rr,     X86::SBB32mr,     makeMRInst },
-      { X86::SETAEr,      X86::SETAEm,      makeMInst },
-      { X86::SETAr,       X86::SETAm,       makeMInst },
-      { X86::SETBEr,      X86::SETBEm,      makeMInst },
-      { X86::SETBr,       X86::SETBm,       makeMInst },
-      { X86::SETEr,       X86::SETEm,       makeMInst },
-      { X86::SETGEr,      X86::SETGEm,      makeMInst },
-      { X86::SETGr,       X86::SETGm,       makeMInst },
-      { X86::SETLEr,      X86::SETLEm,      makeMInst },
-      { X86::SETLr,       X86::SETLm,       makeMInst },
-      { X86::SETNEr,      X86::SETNEm,      makeMInst },
-      { X86::SETNPr,      X86::SETNPm,      makeMInst },
-      { X86::SETNSr,      X86::SETNSm,      makeMInst },
-      { X86::SETPr,       X86::SETPm,       makeMInst },
-      { X86::SETSr,       X86::SETSm,       makeMInst },
-      { X86::SHL16r1,     X86::SHL16m1,     makeMInst },
-      { X86::SHL16rCL,    X86::SHL16mCL,    makeMInst },
-      { X86::SHL16ri,     X86::SHL16mi,     makeMIInst },
-      { X86::SHL32r1,     X86::SHL32m1,     makeMInst },
-      { X86::SHL32rCL,    X86::SHL32mCL,    makeMInst },
-      { X86::SHL32ri,     X86::SHL32mi,     makeMIInst },
-      { X86::SHL8r1,      X86::SHL8m1,      makeMInst },
-      { X86::SHL8rCL,     X86::SHL8mCL,     makeMInst },
-      { X86::SHL8ri,      X86::SHL8mi,      makeMIInst },
-      { X86::SHLD16rrCL,  X86::SHLD16mrCL,  makeMRInst },
-      { X86::SHLD16rri8,  X86::SHLD16mri8,  makeMRIInst },
-      { X86::SHLD32rrCL,  X86::SHLD32mrCL,  makeMRInst },
-      { X86::SHLD32rri8,  X86::SHLD32mri8,  makeMRIInst },
-      { X86::SHR16r1,     X86::SHR16m1,     makeMInst },
-      { X86::SHR16rCL,    X86::SHR16mCL,    makeMInst },
-      { X86::SHR16ri,     X86::SHR16mi,     makeMIInst },
-      { X86::SHR32r1,     X86::SHR32m1,     makeMInst },
-      { X86::SHR32rCL,    X86::SHR32mCL,    makeMInst },
-      { X86::SHR32ri,     X86::SHR32mi,     makeMIInst },
-      { X86::SHR8r1,      X86::SHR8m1,      makeMInst },
-      { X86::SHR8rCL,     X86::SHR8mCL,     makeMInst },
-      { X86::SHR8ri,      X86::SHR8mi,      makeMIInst },
-      { X86::SHRD16rrCL,  X86::SHRD16mrCL,  makeMRInst },
-      { X86::SHRD16rri8,  X86::SHRD16mri8,  makeMRIInst },
-      { X86::SHRD32rrCL,  X86::SHRD32mrCL,  makeMRInst },
-      { X86::SHRD32rri8,  X86::SHRD32mri8,  makeMRIInst },
-      { X86::SUB16ri,     X86::SUB16mi,     makeMIInst },
-      { X86::SUB16ri8,    X86::SUB16mi8,    makeMIInst },
-      { X86::SUB16rr,     X86::SUB16mr,     makeMRInst },
-      { X86::SUB32ri,     X86::SUB32mi,     makeMIInst },
-      { X86::SUB32ri8,    X86::SUB32mi8,    makeMIInst },
-      { X86::SUB32rr,     X86::SUB32mr,     makeMRInst },
-      { X86::SUB8ri,      X86::SUB8mi,      makeMIInst },
-      { X86::SUB8rr,      X86::SUB8mr,      makeMRInst },
-      { X86::XCHG16rr,    X86::XCHG16mr,    makeMRInst },
-      { X86::XCHG32rr,    X86::XCHG32mr,    makeMRInst },
-      { X86::XCHG8rr,     X86::XCHG8mr,     makeMRInst },
-      { X86::XOR16ri,     X86::XOR16mi,     makeMIInst },
-      { X86::XOR16ri8,    X86::XOR16mi8,    makeMIInst },
-      { X86::XOR16rr,     X86::XOR16mr,     makeMRInst },
-      { X86::XOR32ri,     X86::XOR32mi,     makeMIInst },
-      { X86::XOR32ri8,    X86::XOR32mi8,    makeMIInst },
-      { X86::XOR32rr,     X86::XOR32mr,     makeMRInst },
-      { X86::XOR8ri,      X86::XOR8mi,      makeMIInst },
-      { X86::XOR8rr,      X86::XOR8mr,      makeMRInst }
+      { X86::CMP16ri,     X86::CMP16mi },
+      { X86::CMP16ri8,    X86::CMP16mi8 },
+      { X86::CMP32ri,     X86::CMP32mi },
+      { X86::CMP32ri8,    X86::CMP32mi8 },
+      { X86::CMP8ri,      X86::CMP8mi },
+      { X86::DIV16r,      X86::DIV16m },
+      { X86::DIV32r,      X86::DIV32m },
+      { X86::DIV8r,       X86::DIV8m },
+      { X86::FsMOVAPDrr,  X86::MOVSDmr },
+      { X86::FsMOVAPSrr,  X86::MOVSSmr },
+      { X86::IDIV16r,     X86::IDIV16m },
+      { X86::IDIV32r,     X86::IDIV32m },
+      { X86::IDIV8r,      X86::IDIV8m },
+      { X86::IMUL16r,     X86::IMUL16m },
+      { X86::IMUL32r,     X86::IMUL32m },
+      { X86::IMUL8r,      X86::IMUL8m },
+      { X86::MOV16ri,     X86::MOV16mi },
+      { X86::MOV16rr,     X86::MOV16mr },
+      { X86::MOV32ri,     X86::MOV32mi },
+      { X86::MOV32rr,     X86::MOV32mr },
+      { X86::MOV8ri,      X86::MOV8mi },
+      { X86::MOV8rr,      X86::MOV8mr },
+      { X86::MOVAPDrr,    X86::MOVAPDmr },
+      { X86::MOVAPSrr,    X86::MOVAPSmr },
+      { X86::MOVPDI2DIrr, X86::MOVPDI2DImr },
+      { X86::MOVPS2SSrr,  X86::MOVPS2SSmr },
+      { X86::MOVSDrr,     X86::MOVSDmr },
+      { X86::MOVSSrr,     X86::MOVSSmr },
+      { X86::MOVUPDrr,    X86::MOVUPDmr },
+      { X86::MOVUPSrr,    X86::MOVUPSmr },
+      { X86::MUL16r,      X86::MUL16m },
+      { X86::MUL32r,      X86::MUL32m },
+      { X86::MUL8r,       X86::MUL8m },
+      { X86::SETAEr,      X86::SETAEm },
+      { X86::SETAr,       X86::SETAm },
+      { X86::SETBEr,      X86::SETBEm },
+      { X86::SETBr,       X86::SETBm },
+      { X86::SETEr,       X86::SETEm },
+      { X86::SETGEr,      X86::SETGEm },
+      { X86::SETGr,       X86::SETGm },
+      { X86::SETLEr,      X86::SETLEm },
+      { X86::SETLr,       X86::SETLm },
+      { X86::SETNEr,      X86::SETNEm },
+      { X86::SETNPr,      X86::SETNPm },
+      { X86::SETNSr,      X86::SETNSm },
+      { X86::SETPr,       X86::SETPm },
+      { X86::SETSr,       X86::SETSm },
+      { X86::TEST16ri,    X86::TEST16mi },
+      { X86::TEST32ri,    X86::TEST32mi },
+      { X86::TEST8ri,     X86::TEST8mi },
+      { X86::XCHG16rr,    X86::XCHG16mr },
+      { X86::XCHG32rr,    X86::XCHG32mr },
+      { X86::XCHG8rr,     X86::XCHG8mr }
     };
     ASSERT_SORTED(OpcodeTable);
     OpcodeTablePtr = OpcodeTable;
     OpcodeTableSize = ARRAY_SIZE(OpcodeTable);
   } else if (i == 1) {
     static const TableEntry OpcodeTable[] = {
-      { X86::ADC32rr,         X86::ADC32rm,         makeRMInst },
-      { X86::ADD16rr,         X86::ADD16rm,         makeRMInst },
-      { X86::ADD32rr,         X86::ADD32rm,         makeRMInst },
-      { X86::ADD8rr,          X86::ADD8rm,          makeRMInst },
-      { X86::ADDPDrr,         X86::ADDPDrm,         makeRMInst },
-      { X86::ADDPSrr,         X86::ADDPSrm,         makeRMInst },
-      { X86::ADDSDrr,         X86::ADDSDrm,         makeRMInst },
-      { X86::ADDSSrr,         X86::ADDSSrm,         makeRMInst },
-      { X86::ADDSUBPDrr,      X86::ADDSUBPDrm,      makeRMInst },
-      { X86::ADDSUBPSrr,      X86::ADDSUBPSrm,      makeRMInst },
-      { X86::AND16rr,         X86::AND16rm,         makeRMInst },
-      { X86::AND32rr,         X86::AND32rm,         makeRMInst },
-      { X86::AND8rr,          X86::AND8rm,          makeRMInst },
-      { X86::ANDNPDrr,        X86::ANDNPDrm,        makeRMInst },
-      { X86::ANDNPSrr,        X86::ANDNPSrm,        makeRMInst },
-      { X86::ANDPDrr,         X86::ANDPDrm,         makeRMInst },
-      { X86::ANDPSrr,         X86::ANDPSrm,         makeRMInst },
-      { X86::CMOVA16rr,       X86::CMOVA16rm,       makeRMInst },
-      { X86::CMOVA32rr,       X86::CMOVA32rm,       makeRMInst },
-      { X86::CMOVAE16rr,      X86::CMOVAE16rm,      makeRMInst },
-      { X86::CMOVAE32rr,      X86::CMOVAE32rm,      makeRMInst },
-      { X86::CMOVB16rr,       X86::CMOVB16rm,       makeRMInst },
-      { X86::CMOVB32rr,       X86::CMOVB32rm,       makeRMInst },
-      { X86::CMOVBE16rr,      X86::CMOVBE16rm,      makeRMInst },
-      { X86::CMOVBE32rr,      X86::CMOVBE32rm,      makeRMInst },
-      { X86::CMOVE16rr,       X86::CMOVE16rm,       makeRMInst },
-      { X86::CMOVE32rr,       X86::CMOVE32rm,       makeRMInst },
-      { X86::CMOVG16rr,       X86::CMOVG16rm,       makeRMInst },
-      { X86::CMOVG32rr,       X86::CMOVG32rm,       makeRMInst },
-      { X86::CMOVGE16rr,      X86::CMOVGE16rm,      makeRMInst },
-      { X86::CMOVGE32rr,      X86::CMOVGE32rm,      makeRMInst },
-      { X86::CMOVL16rr,       X86::CMOVL16rm,       makeRMInst },
-      { X86::CMOVL32rr,       X86::CMOVL32rm,       makeRMInst },
-      { X86::CMOVLE16rr,      X86::CMOVLE16rm,      makeRMInst },
-      { X86::CMOVLE32rr,      X86::CMOVLE32rm,      makeRMInst },
-      { X86::CMOVNE16rr,      X86::CMOVNE16rm,      makeRMInst },
-      { X86::CMOVNE32rr,      X86::CMOVNE32rm,      makeRMInst },
-      { X86::CMOVNP16rr,      X86::CMOVNP16rm,      makeRMInst },
-      { X86::CMOVNP32rr,      X86::CMOVNP32rm,      makeRMInst },
-      { X86::CMOVNS16rr,      X86::CMOVNS16rm,      makeRMInst },
-      { X86::CMOVNS32rr,      X86::CMOVNS32rm,      makeRMInst },
-      { X86::CMOVP16rr,       X86::CMOVP16rm,       makeRMInst },
-      { X86::CMOVP32rr,       X86::CMOVP32rm,       makeRMInst },
-      { X86::CMOVS16rr,       X86::CMOVS16rm,       makeRMInst },
-      { X86::CMOVS32rr,       X86::CMOVS32rm,       makeRMInst },
-      { X86::CMP16ri,         X86::CMP16mi,         makeMIInst },
-      { X86::CMP16ri8,        X86::CMP16mi8,        makeMIInst },
-      { X86::CMP16rr,         X86::CMP16rm,         makeRMInst },
-      { X86::CMP32ri,         X86::CMP32mi,         makeMIInst },
-      { X86::CMP32ri8,        X86::CMP32mi8,        makeRMInst },
-      { X86::CMP32rr,         X86::CMP32rm,         makeRMInst },
-      { X86::CMP8ri,          X86::CMP8mi,          makeRMInst },
-      { X86::CMP8rr,          X86::CMP8rm,          makeRMInst },
-      { X86::CMPPDrri,        X86::CMPPDrmi,        makeRMIInst },
-      { X86::CMPPSrri,        X86::CMPPSrmi,        makeRMIInst },
-      { X86::CMPSDrr,         X86::CMPSDrm,         makeRMInst },
-      { X86::CMPSSrr,         X86::CMPSSrm,         makeRMInst },
-      { X86::CVTSD2SSrr,      X86::CVTSD2SSrm,      makeRMInst },
-      { X86::CVTSI2SDrr,      X86::CVTSI2SDrm,      makeRMInst },
-      { X86::CVTSI2SSrr,      X86::CVTSI2SSrm,      makeRMInst },
-      { X86::CVTSS2SDrr,      X86::CVTSS2SDrm,      makeRMInst },
-      { X86::CVTTSD2SIrr,     X86::CVTTSD2SIrm,     makeRMInst },
-      { X86::CVTTSS2SIrr,     X86::CVTTSS2SIrm,     makeRMInst },
-      { X86::DIVPDrr,         X86::DIVPDrm,         makeRMInst },
-      { X86::DIVPSrr,         X86::DIVPSrm,         makeRMInst },
-      { X86::DIVSDrr,         X86::DIVSDrm,         makeRMInst },
-      { X86::DIVSSrr,         X86::DIVSSrm,         makeRMInst },
-      { X86::FsMOVAPDrr,      X86::MOVSDrm,         makeRMInst },
-      { X86::FsMOVAPSrr,      X86::MOVSSrm,         makeRMInst },
-      { X86::HADDPDrr,        X86::HADDPDrm,        makeRMInst },
-      { X86::HADDPSrr,        X86::HADDPSrm,        makeRMInst },
-      { X86::HSUBPDrr,        X86::HSUBPDrm,        makeRMInst },
-      { X86::HSUBPSrr,        X86::HSUBPSrm,        makeRMInst },
-      { X86::IMUL16rr,        X86::IMUL16rm,        makeRMInst },
-      { X86::IMUL16rri,       X86::IMUL16rmi,       makeRMIInst },
-      { X86::IMUL16rri8,      X86::IMUL16rmi8,      makeRMIInst },
-      { X86::IMUL32rr,        X86::IMUL32rm,        makeRMInst },
-      { X86::IMUL32rri,       X86::IMUL32rmi,       makeRMIInst },
-      { X86::IMUL32rri8,      X86::IMUL32rmi8,      makeRMIInst },
-      { X86::Int_CMPSDrr,     X86::Int_CMPSDrm,     makeRMInst },
-      { X86::Int_CMPSSrr,     X86::Int_CMPSSrm,     makeRMInst },
-      { X86::Int_COMISDrr,    X86::Int_COMISDrm,    makeRMInst },
-      { X86::Int_COMISSrr,    X86::Int_COMISSrm,    makeRMInst },
-      { X86::Int_CVTDQ2PDrr,  X86::Int_CVTDQ2PDrm,  makeRMInst },
-      { X86::Int_CVTDQ2PSrr,  X86::Int_CVTDQ2PSrm,  makeRMInst },
-      { X86::Int_CVTPD2DQrr,  X86::Int_CVTPD2DQrm,  makeRMInst },
-      { X86::Int_CVTPD2PSrr,  X86::Int_CVTPD2PSrm,  makeRMInst },
-      { X86::Int_CVTPS2DQrr,  X86::Int_CVTPS2DQrm,  makeRMInst },
-      { X86::Int_CVTPS2PDrr,  X86::Int_CVTPS2PDrm,  makeRMInst },
-      { X86::Int_CVTSD2SIrr,  X86::Int_CVTSD2SIrm,  makeRMInst },
-      { X86::Int_CVTSD2SSrr,  X86::Int_CVTSD2SSrm,  makeRMInst },
-      { X86::Int_CVTSI2SDrr,  X86::Int_CVTSI2SDrm,  makeRMInst },
-      { X86::Int_CVTSI2SSrr,  X86::Int_CVTSI2SSrm,  makeRMInst },
-      { X86::Int_CVTSS2SDrr,  X86::Int_CVTSS2SDrm,  makeRMInst },
-      { X86::Int_CVTSS2SIrr,  X86::Int_CVTSS2SIrm,  makeRMInst },
-      { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm, makeRMInst },
-      { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm, makeRMInst },
-      { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, makeRMInst },
-      { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, makeRMInst },
-      { X86::Int_UCOMISDrr,   X86::Int_UCOMISDrm,   makeRMInst },
-      { X86::Int_UCOMISSrr,   X86::Int_UCOMISSrm,   makeRMInst },
-      { X86::MAXPDrr,         X86::MAXPDrm,         makeRMInst },
-      { X86::MAXPSrr,         X86::MAXPSrm,         makeRMInst },
-      { X86::MINPDrr,         X86::MINPDrm,         makeRMInst },
-      { X86::MINPSrr,         X86::MINPSrm,         makeRMInst },
-      { X86::MOV16rr,         X86::MOV16rm,         makeRMInst },
-      { X86::MOV32rr,         X86::MOV32rm,         makeRMInst },
-      { X86::MOV8rr,          X86::MOV8rm,          makeRMInst },
-      { X86::MOVAPDrr,        X86::MOVAPDrm,        makeRMInst },
-      { X86::MOVAPSrr,        X86::MOVAPSrm,        makeRMInst },
-      { X86::MOVDDUPrr,       X86::MOVDDUPrm,       makeRMInst },
-      { X86::MOVDI2PDIrr,     X86::MOVDI2PDIrm,     makeRMInst },
-      { X86::MOVQI2PQIrr,     X86::MOVQI2PQIrm,     makeRMInst },
-      { X86::MOVSD2PDrr,      X86::MOVSD2PDrm,      makeRMInst },
-      { X86::MOVSDrr,         X86::MOVSDrm,         makeRMInst },
-      { X86::MOVSHDUPrr,      X86::MOVSHDUPrm,      makeRMInst },
-      { X86::MOVSLDUPrr,      X86::MOVSLDUPrm,      makeRMInst },
-      { X86::MOVSS2PSrr,      X86::MOVSS2PSrm,      makeRMInst },
-      { X86::MOVSSrr,         X86::MOVSSrm,         makeRMInst },
-      { X86::MOVSX16rr8,      X86::MOVSX16rm8,      makeRMInst },
-      { X86::MOVSX32rr16,     X86::MOVSX32rm16,     makeRMInst },
-      { X86::MOVSX32rr8,      X86::MOVSX32rm8,      makeRMInst },
-      { X86::MOVUPDrr,        X86::MOVUPDrm,        makeRMInst },
-      { X86::MOVUPSrr,        X86::MOVUPSrm,        makeRMInst },
-      { X86::MOVZX16rr8,      X86::MOVZX16rm8,      makeRMInst },
-      { X86::MOVZX32rr16,     X86::MOVZX32rm16,     makeRMInst },
-      { X86::MOVZX32rr8,      X86::MOVZX32rm8,      makeRMInst },
-      { X86::MULPDrr,         X86::MULPDrm,         makeRMInst },
-      { X86::MULPSrr,         X86::MULPSrm,         makeRMInst },
-      { X86::MULSDrr,         X86::MULSDrm,         makeRMInst },
-      { X86::MULSSrr,         X86::MULSSrm,         makeRMInst },
-      { X86::OR16rr,          X86::OR16rm,          makeRMInst },
-      { X86::OR32rr,          X86::OR32rm,          makeRMInst },
-      { X86::OR8rr,           X86::OR8rm,           makeRMInst },
-      { X86::ORPDrr,          X86::ORPDrm,          makeRMInst },
-      { X86::ORPSrr,          X86::ORPSrm,          makeRMInst },
-      { X86::PACKSSDWrr,      X86::PACKSSDWrm,      makeRMInst },
-      { X86::PACKSSWBrr,      X86::PACKSSWBrm,      makeRMInst },
-      { X86::PACKUSWBrr,      X86::PACKUSWBrm,      makeRMInst },
-      { X86::PADDBrr,         X86::PADDBrm,         makeRMInst },
-      { X86::PADDDrr,         X86::PADDDrm,         makeRMInst },
-      { X86::PADDSBrr,        X86::PADDSBrm,        makeRMInst },
-      { X86::PADDSWrr,        X86::PADDSWrm,        makeRMInst },
-      { X86::PADDWrr,         X86::PADDWrm,         makeRMInst },
-      { X86::PANDNrr,         X86::PANDNrm,         makeRMInst },
-      { X86::PANDrr,          X86::PANDrm,          makeRMInst },
-      { X86::PAVGBrr,         X86::PAVGBrm,         makeRMInst },
-      { X86::PAVGWrr,         X86::PAVGWrm,         makeRMInst },
-      { X86::PCMPEQBrr,       X86::PCMPEQBrm,       makeRMInst },
-      { X86::PCMPEQDrr,       X86::PCMPEQDrm,       makeRMInst },
-      { X86::PCMPEQWrr,       X86::PCMPEQWrm,       makeRMInst },
-      { X86::PCMPGTBrr,       X86::PCMPGTBrm,       makeRMInst },
-      { X86::PCMPGTDrr,       X86::PCMPGTDrm,       makeRMInst },
-      { X86::PCMPGTWrr,       X86::PCMPGTWrm,       makeRMInst },
-      { X86::PINSRWrri,       X86::PINSRWrmi,       makeRMIInst },
-      { X86::PMADDWDrr,       X86::PMADDWDrm,       makeRMInst },
-      { X86::PMAXSWrr,        X86::PMAXSWrm,        makeRMInst },
-      { X86::PMAXUBrr,        X86::PMAXUBrm,        makeRMInst },
-      { X86::PMINSWrr,        X86::PMINSWrm,        makeRMInst },
-      { X86::PMINUBrr,        X86::PMINUBrm,        makeRMInst },
-      { X86::PMULHUWrr,       X86::PMULHUWrm,       makeRMInst },
-      { X86::PMULHWrr,        X86::PMULHWrm,        makeRMInst },
-      { X86::PMULLWrr,        X86::PMULLWrm,        makeRMInst },
-      { X86::PMULUDQrr,       X86::PMULUDQrm,       makeRMInst },
-      { X86::PORrr,           X86::PORrm,           makeRMInst },
-      { X86::PSADBWrr,        X86::PSADBWrm,        makeRMInst },
-      { X86::PSHUFDri,        X86::PSHUFDmi,        makeRMIInst },
-      { X86::PSHUFHWri,       X86::PSHUFHWmi,       makeRMIInst },
-      { X86::PSHUFLWri,       X86::PSHUFLWmi,       makeRMIInst },
-      { X86::PSLLDrr,         X86::PSLLDrm,         makeRMInst },
-      { X86::PSLLQrr,         X86::PSLLQrm,         makeRMInst },
-      { X86::PSLLWrr,         X86::PSLLWrm,         makeRMInst },
-      { X86::PSRADrr,         X86::PSRADrm,         makeRMInst },
-      { X86::PSRAWrr,         X86::PSRAWrm,         makeRMInst },
-      { X86::PSRLDrr,         X86::PSRLDrm,         makeRMInst },
-      { X86::PSRLQrr,         X86::PSRLQrm,         makeRMInst },
-      { X86::PSRLWrr,         X86::PSRLWrm,         makeRMInst },
-      { X86::PSUBBrr,         X86::PSUBBrm,         makeRMInst },
-      { X86::PSUBDrr,         X86::PSUBDrm,         makeRMInst },
-      { X86::PSUBSBrr,        X86::PSUBSBrm,        makeRMInst },
-      { X86::PSUBSWrr,        X86::PSUBSWrm,        makeRMInst },
-      { X86::PSUBWrr,         X86::PSUBWrm,         makeRMInst },
-      { X86::PUNPCKHBWrr,     X86::PUNPCKHBWrm,     makeRMInst },
-      { X86::PUNPCKHDQrr,     X86::PUNPCKHDQrm,     makeRMInst },
-      { X86::PUNPCKHQDQrr,    X86::PUNPCKHQDQrm,    makeRMInst },
-      { X86::PUNPCKHWDrr,     X86::PUNPCKHWDrm,     makeRMInst },
-      { X86::PUNPCKLBWrr,     X86::PUNPCKLBWrm,     makeRMInst },
-      { X86::PUNPCKLDQrr,     X86::PUNPCKLDQrm,     makeRMInst },
-      { X86::PUNPCKLQDQrr,    X86::PUNPCKLQDQrm,    makeRMInst },
-      { X86::PUNPCKLWDrr,     X86::PUNPCKLWDrm,     makeRMInst },
-      { X86::PXORrr,          X86::PXORrm,          makeRMInst },
-      { X86::RCPPSr,          X86::RCPPSm,          makeRMInst },
-      { X86::RSQRTPSr,        X86::RSQRTPSm,        makeRMInst },
-      { X86::SBB32rr,         X86::SBB32rm,         makeRMInst },
-      { X86::SHUFPDrri,       X86::SHUFPDrmi,       makeRMIInst },
-      { X86::SHUFPSrri,       X86::SHUFPSrmi,       makeRMIInst },
-      { X86::SQRTPDr,         X86::SQRTPDm,         makeRMInst },
-      { X86::SQRTPSr,         X86::SQRTPSm,         makeRMInst },
-      { X86::SQRTSDr,         X86::SQRTSDm,         makeRMInst },
-      { X86::SQRTSSr,         X86::SQRTSSm,         makeRMInst },
-      { X86::SUB16rr,         X86::SUB16rm,         makeRMInst },
-      { X86::SUB32rr,         X86::SUB32rm,         makeRMInst },
-      { X86::SUB8rr,          X86::SUB8rm,          makeRMInst },
-      { X86::SUBPDrr,         X86::SUBPDrm,         makeRMInst },
-      { X86::SUBPSrr,         X86::SUBPSrm,         makeRMInst },
-      { X86::SUBSDrr,         X86::SUBSDrm,         makeRMInst },
-      { X86::SUBSSrr,         X86::SUBSSrm,         makeRMInst },
-      { X86::TEST16ri,        X86::TEST16mi,        makeMIInst },
-      { X86::TEST16rr,        X86::TEST16rm,        makeRMInst },
-      { X86::TEST32ri,        X86::TEST32mi,        makeMIInst },
-      { X86::TEST32rr,        X86::TEST32rm,        makeRMInst },
-      { X86::TEST8ri,         X86::TEST8mi,         makeMIInst },
-      { X86::TEST8rr,         X86::TEST8rm,         makeRMInst },
-      { X86::UCOMISDrr,       X86::UCOMISDrm,       makeRMInst },
-      { X86::UCOMISSrr,       X86::UCOMISSrm,       makeRMInst },
-      { X86::UNPCKHPDrr,      X86::UNPCKHPDrm,      makeRMInst },
-      { X86::UNPCKHPSrr,      X86::UNPCKHPSrm,      makeRMInst },
-      { X86::UNPCKLPDrr,      X86::UNPCKLPDrm,      makeRMInst },
-      { X86::UNPCKLPSrr,      X86::UNPCKLPSrm,      makeRMInst },
-      { X86::XCHG16rr,        X86::XCHG16rm,        makeRMInst },
-      { X86::XCHG32rr,        X86::XCHG32rm,        makeRMInst },
-      { X86::XCHG8rr,         X86::XCHG8rm,         makeRMInst },
-      { X86::XOR16rr,         X86::XOR16rm,         makeRMInst },
-      { X86::XOR32rr,         X86::XOR32rm,         makeRMInst },
-      { X86::XOR8rr,          X86::XOR8rm,          makeRMInst },
-      { X86::XORPDrr,         X86::XORPDrm,         makeRMInst },
-      { X86::XORPSrr,         X86::XORPSrm,         makeRMInst }
+      { X86::CMP16rr,         X86::CMP16rm },
+      { X86::CMP32rr,         X86::CMP32rm },
+      { X86::CMP8rr,          X86::CMP8rm },
+      { X86::CMPPDrri,        X86::CMPPDrmi },
+      { X86::CMPPSrri,        X86::CMPPSrmi },
+      { X86::CMPSDrr,         X86::CMPSDrm },
+      { X86::CMPSSrr,         X86::CMPSSrm },
+      { X86::CVTSD2SSrr,      X86::CVTSD2SSrm },
+      { X86::CVTSI2SDrr,      X86::CVTSI2SDrm },
+      { X86::CVTSI2SSrr,      X86::CVTSI2SSrm },
+      { X86::CVTSS2SDrr,      X86::CVTSS2SDrm },
+      { X86::CVTTSD2SIrr,     X86::CVTTSD2SIrm },
+      { X86::CVTTSS2SIrr,     X86::CVTTSS2SIrm },
+      { X86::FsMOVAPDrr,      X86::MOVSDrm },
+      { X86::FsMOVAPSrr,      X86::MOVSSrm },
+      { X86::IMUL16rri,       X86::IMUL16rmi },
+      { X86::IMUL16rri8,      X86::IMUL16rmi8 },
+      { X86::IMUL32rri,       X86::IMUL32rmi },
+      { X86::IMUL32rri8,      X86::IMUL32rmi8 },
+      { X86::Int_CMPSDrr,     X86::Int_CMPSDrm },
+      { X86::Int_CMPSSrr,     X86::Int_CMPSSrm },
+      { X86::Int_COMISDrr,    X86::Int_COMISDrm },
+      { X86::Int_COMISSrr,    X86::Int_COMISSrm },
+      { X86::Int_CVTDQ2PDrr,  X86::Int_CVTDQ2PDrm },
+      { X86::Int_CVTDQ2PSrr,  X86::Int_CVTDQ2PSrm },
+      { X86::Int_CVTPD2DQrr,  X86::Int_CVTPD2DQrm },
+      { X86::Int_CVTPD2PSrr,  X86::Int_CVTPD2PSrm },
+      { X86::Int_CVTPS2DQrr,  X86::Int_CVTPS2DQrm },
+      { X86::Int_CVTPS2PDrr,  X86::Int_CVTPS2PDrm },
+      { X86::Int_CVTSD2SIrr,  X86::Int_CVTSD2SIrm },
+      { X86::Int_CVTSD2SSrr,  X86::Int_CVTSD2SSrm },
+      { X86::Int_CVTSI2SDrr,  X86::Int_CVTSI2SDrm },
+      { X86::Int_CVTSI2SSrr,  X86::Int_CVTSI2SSrm },
+      { X86::Int_CVTSS2SDrr,  X86::Int_CVTSS2SDrm },
+      { X86::Int_CVTSS2SIrr,  X86::Int_CVTSS2SIrm },
+      { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm },
+      { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm },
+      { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm },
+      { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm },
+      { X86::Int_UCOMISDrr,   X86::Int_UCOMISDrm },
+      { X86::Int_UCOMISSrr,   X86::Int_UCOMISSrm },
+      { X86::MOV16rr,         X86::MOV16rm },
+      { X86::MOV32rr,         X86::MOV32rm },
+      { X86::MOV8rr,          X86::MOV8rm },
+      { X86::MOVAPDrr,        X86::MOVAPDrm },
+      { X86::MOVAPSrr,        X86::MOVAPSrm },
+      { X86::MOVDDUPrr,       X86::MOVDDUPrm },
+      { X86::MOVDI2PDIrr,     X86::MOVDI2PDIrm },
+      { X86::MOVQI2PQIrr,     X86::MOVQI2PQIrm },
+      { X86::MOVSD2PDrr,      X86::MOVSD2PDrm },
+      { X86::MOVSDrr,         X86::MOVSDrm },
+      { X86::MOVSHDUPrr,      X86::MOVSHDUPrm },
+      { X86::MOVSLDUPrr,      X86::MOVSLDUPrm },
+      { X86::MOVSS2PSrr,      X86::MOVSS2PSrm },
+      { X86::MOVSSrr,         X86::MOVSSrm },
+      { X86::MOVSX16rr8,      X86::MOVSX16rm8 },
+      { X86::MOVSX32rr16,     X86::MOVSX32rm16 },
+      { X86::MOVSX32rr8,      X86::MOVSX32rm8 },
+      { X86::MOVUPDrr,        X86::MOVUPDrm },
+      { X86::MOVUPSrr,        X86::MOVUPSrm },
+      { X86::MOVZX16rr8,      X86::MOVZX16rm8 },
+      { X86::MOVZX32rr16,     X86::MOVZX32rm16 },
+      { X86::MOVZX32rr8,      X86::MOVZX32rm8 },
+      { X86::PSHUFDri,        X86::PSHUFDmi },
+      { X86::PSHUFHWri,       X86::PSHUFHWmi },
+      { X86::PSHUFLWri,       X86::PSHUFLWmi },
+      { X86::TEST16rr,        X86::TEST16rm },
+      { X86::TEST32rr,        X86::TEST32rm },
+      { X86::TEST8rr,         X86::TEST8rm },
+      { X86::UCOMISDrr,       X86::UCOMISDrm },
+      { X86::UCOMISSrr,       X86::UCOMISSrm },
+      { X86::XCHG16rr,        X86::XCHG16rm },
+      { X86::XCHG32rr,        X86::XCHG32rm },
+      { X86::XCHG8rr,         X86::XCHG8rm }
+    };
+    ASSERT_SORTED(OpcodeTable);
+    OpcodeTablePtr = OpcodeTable;
+    OpcodeTableSize = ARRAY_SIZE(OpcodeTable);
+  } else if (i == 2) {
+    static const TableEntry OpcodeTable[] = {
+      { X86::ADC32rr,         X86::ADC32rm },
+      { X86::ADD16rr,         X86::ADD16rm },
+      { X86::ADD32rr,         X86::ADD32rm },
+      { X86::ADD8rr,          X86::ADD8rm },
+      { X86::ADDPDrr,         X86::ADDPDrm },
+      { X86::ADDPSrr,         X86::ADDPSrm },
+      { X86::ADDSDrr,         X86::ADDSDrm },
+      { X86::ADDSSrr,         X86::ADDSSrm },
+      { X86::ADDSUBPDrr,      X86::ADDSUBPDrm },
+      { X86::ADDSUBPSrr,      X86::ADDSUBPSrm },
+      { X86::AND16rr,         X86::AND16rm },
+      { X86::AND32rr,         X86::AND32rm },
+      { X86::AND8rr,          X86::AND8rm },
+      { X86::ANDNPDrr,        X86::ANDNPDrm },
+      { X86::ANDNPSrr,        X86::ANDNPSrm },
+      { X86::ANDPDrr,         X86::ANDPDrm },
+      { X86::ANDPSrr,         X86::ANDPSrm },
+      { X86::CMOVA16rr,       X86::CMOVA16rm },
+      { X86::CMOVA32rr,       X86::CMOVA32rm },
+      { X86::CMOVAE16rr,      X86::CMOVAE16rm },
+      { X86::CMOVAE32rr,      X86::CMOVAE32rm },
+      { X86::CMOVB16rr,       X86::CMOVB16rm },
+      { X86::CMOVB32rr,       X86::CMOVB32rm },
+      { X86::CMOVBE16rr,      X86::CMOVBE16rm },
+      { X86::CMOVBE32rr,      X86::CMOVBE32rm },
+      { X86::CMOVE16rr,       X86::CMOVE16rm },
+      { X86::CMOVE32rr,       X86::CMOVE32rm },
+      { X86::CMOVG16rr,       X86::CMOVG16rm },
+      { X86::CMOVG32rr,       X86::CMOVG32rm },
+      { X86::CMOVGE16rr,      X86::CMOVGE16rm },
+      { X86::CMOVGE32rr,      X86::CMOVGE32rm },
+      { X86::CMOVL16rr,       X86::CMOVL16rm },
+      { X86::CMOVL32rr,       X86::CMOVL32rm },
+      { X86::CMOVLE16rr,      X86::CMOVLE16rm },
+      { X86::CMOVLE32rr,      X86::CMOVLE32rm },
+      { X86::CMOVNE16rr,      X86::CMOVNE16rm },
+      { X86::CMOVNE32rr,      X86::CMOVNE32rm },
+      { X86::CMOVNP16rr,      X86::CMOVNP16rm },
+      { X86::CMOVNP32rr,      X86::CMOVNP32rm },
+      { X86::CMOVNS16rr,      X86::CMOVNS16rm },
+      { X86::CMOVNS32rr,      X86::CMOVNS32rm },
+      { X86::CMOVP16rr,       X86::CMOVP16rm },
+      { X86::CMOVP32rr,       X86::CMOVP32rm },
+      { X86::CMOVS16rr,       X86::CMOVS16rm },
+      { X86::CMOVS32rr,       X86::CMOVS32rm },
+      { X86::DIVPDrr,         X86::DIVPDrm },
+      { X86::DIVPSrr,         X86::DIVPSrm },
+      { X86::DIVSDrr,         X86::DIVSDrm },
+      { X86::DIVSSrr,         X86::DIVSSrm },
+      { X86::HADDPDrr,        X86::HADDPDrm },
+      { X86::HADDPSrr,        X86::HADDPSrm },
+      { X86::HSUBPDrr,        X86::HSUBPDrm },
+      { X86::HSUBPSrr,        X86::HSUBPSrm },
+      { X86::IMUL16rr,        X86::IMUL16rm },
+      { X86::IMUL32rr,        X86::IMUL32rm },
+      { X86::MAXPDrr,         X86::MAXPDrm },
+      { X86::MAXPSrr,         X86::MAXPSrm },
+      { X86::MINPDrr,         X86::MINPDrm },
+      { X86::MINPSrr,         X86::MINPSrm },
+      { X86::MULPDrr,         X86::MULPDrm },
+      { X86::MULPSrr,         X86::MULPSrm },
+      { X86::MULSDrr,         X86::MULSDrm },
+      { X86::MULSSrr,         X86::MULSSrm },
+      { X86::OR16rr,          X86::OR16rm },
+      { X86::OR32rr,          X86::OR32rm },
+      { X86::OR8rr,           X86::OR8rm },
+      { X86::ORPDrr,          X86::ORPDrm },
+      { X86::ORPSrr,          X86::ORPSrm },
+      { X86::PACKSSDWrr,      X86::PACKSSDWrm },
+      { X86::PACKSSWBrr,      X86::PACKSSWBrm },
+      { X86::PACKUSWBrr,      X86::PACKUSWBrm },
+      { X86::PADDBrr,         X86::PADDBrm },
+      { X86::PADDDrr,         X86::PADDDrm },
+      { X86::PADDSBrr,        X86::PADDSBrm },
+      { X86::PADDSWrr,        X86::PADDSWrm },
+      { X86::PADDWrr,         X86::PADDWrm },
+      { X86::PANDNrr,         X86::PANDNrm },
+      { X86::PANDrr,          X86::PANDrm },
+      { X86::PAVGBrr,         X86::PAVGBrm },
+      { X86::PAVGWrr,         X86::PAVGWrm },
+      { X86::PCMPEQBrr,       X86::PCMPEQBrm },
+      { X86::PCMPEQDrr,       X86::PCMPEQDrm },
+      { X86::PCMPEQWrr,       X86::PCMPEQWrm },
+      { X86::PCMPGTBrr,       X86::PCMPGTBrm },
+      { X86::PCMPGTDrr,       X86::PCMPGTDrm },
+      { X86::PCMPGTWrr,       X86::PCMPGTWrm },
+      { X86::PINSRWrri,       X86::PINSRWrmi },
+      { X86::PMADDWDrr,       X86::PMADDWDrm },
+      { X86::PMAXSWrr,        X86::PMAXSWrm },
+      { X86::PMAXUBrr,        X86::PMAXUBrm },
+      { X86::PMINSWrr,        X86::PMINSWrm },
+      { X86::PMINUBrr,        X86::PMINUBrm },
+      { X86::PMULHUWrr,       X86::PMULHUWrm },
+      { X86::PMULHWrr,        X86::PMULHWrm },
+      { X86::PMULLWrr,        X86::PMULLWrm },
+      { X86::PMULUDQrr,       X86::PMULUDQrm },
+      { X86::PORrr,           X86::PORrm },
+      { X86::PSADBWrr,        X86::PSADBWrm },
+      { X86::PSLLDrr,         X86::PSLLDrm },
+      { X86::PSLLQrr,         X86::PSLLQrm },
+      { X86::PSLLWrr,         X86::PSLLWrm },
+      { X86::PSRADrr,         X86::PSRADrm },
+      { X86::PSRAWrr,         X86::PSRAWrm },
+      { X86::PSRLDrr,         X86::PSRLDrm },
+      { X86::PSRLQrr,         X86::PSRLQrm },
+      { X86::PSRLWrr,         X86::PSRLWrm },
+      { X86::PSUBBrr,         X86::PSUBBrm },
+      { X86::PSUBDrr,         X86::PSUBDrm },
+      { X86::PSUBSBrr,        X86::PSUBSBrm },
+      { X86::PSUBSWrr,        X86::PSUBSWrm },
+      { X86::PSUBWrr,         X86::PSUBWrm },
+      { X86::PUNPCKHBWrr,     X86::PUNPCKHBWrm },
+      { X86::PUNPCKHDQrr,     X86::PUNPCKHDQrm },
+      { X86::PUNPCKHQDQrr,    X86::PUNPCKHQDQrm },
+      { X86::PUNPCKHWDrr,     X86::PUNPCKHWDrm },
+      { X86::PUNPCKLBWrr,     X86::PUNPCKLBWrm },
+      { X86::PUNPCKLDQrr,     X86::PUNPCKLDQrm },
+      { X86::PUNPCKLQDQrr,    X86::PUNPCKLQDQrm },
+      { X86::PUNPCKLWDrr,     X86::PUNPCKLWDrm },
+      { X86::PXORrr,          X86::PXORrm },
+      { X86::RCPPSr,          X86::RCPPSm },
+      { X86::RSQRTPSr,        X86::RSQRTPSm },
+      { X86::SBB32rr,         X86::SBB32rm },
+      { X86::SHUFPDrri,       X86::SHUFPDrmi },
+      { X86::SHUFPSrri,       X86::SHUFPSrmi },
+      { X86::SQRTPDr,         X86::SQRTPDm },
+      { X86::SQRTPSr,         X86::SQRTPSm },
+      { X86::SQRTSDr,         X86::SQRTSDm },
+      { X86::SQRTSSr,         X86::SQRTSSm },
+      { X86::SUB16rr,         X86::SUB16rm },
+      { X86::SUB32rr,         X86::SUB32rm },
+      { X86::SUB8rr,          X86::SUB8rm },
+      { X86::SUBPDrr,         X86::SUBPDrm },
+      { X86::SUBPSrr,         X86::SUBPSrm },
+      { X86::SUBSDrr,         X86::SUBSDrm },
+      { X86::SUBSSrr,         X86::SUBSSrm },
+      { X86::UNPCKHPDrr,      X86::UNPCKHPDrm },
+      { X86::UNPCKHPSrr,      X86::UNPCKHPSrm },
+      { X86::UNPCKLPDrr,      X86::UNPCKLPDrm },
+      { X86::UNPCKLPSrr,      X86::UNPCKLPSrm },
+      { X86::XOR16rr,         X86::XOR16rm },
+      { X86::XOR32rr,         X86::XOR32rm },
+      { X86::XOR8rr,          X86::XOR8rm },
+      { X86::XORPDrr,         X86::XORPDrm },
+      { X86::XORPSrr,         X86::XORPSrm }
     };
     ASSERT_SORTED(OpcodeTable);
     OpcodeTablePtr = OpcodeTable;
     OpcodeTableSize = ARRAY_SIZE(OpcodeTable);
   }
   
-  // If table selected
+  // If table selected...
   if (OpcodeTablePtr) {
-    // Opcode to fuse
+    // Find the Opcode to fuse
     unsigned fromOpcode = MI->getOpcode();
     // Lookup fromOpcode in table
-    const TableEntry *entry = TableLookup(OpcodeTablePtr, OpcodeTableSize,
-                                          fromOpcode);
-    
-    // If opcode found in table
-    if (entry) {
-      // Fused opcode
-      unsigned toOpcode = entry->to;
+    if (const TableEntry *Entry = TableLookup(OpcodeTablePtr, OpcodeTableSize,
+                                              fromOpcode)) {
+      if (isTwoAddrFold)
+        return FuseTwoAddrInst(Entry->to, FrameIndex, MI);
       
-      // Make new instruction
-      switch (entry->make) {
-      case makeM0Inst:  return MakeM0Inst(toOpcode, FrameIndex, MI);
-      case makeMIInst:  return MakeMIInst(toOpcode, FrameIndex, MI);
-      case makeMInst:   return MakeMInst(toOpcode, FrameIndex, MI);
-      case makeMRIInst: return MakeMRIInst(toOpcode, FrameIndex, MI);
-      case makeMRInst:  return MakeMRInst(toOpcode, FrameIndex, MI);
-      case makeRMIInst: return MakeRMIInst(toOpcode, FrameIndex, MI);
-      case makeRMInst:  return MakeRMInst(toOpcode, FrameIndex, MI);
-      default: assert(0 && "Unknown instruction make");
-      }
+      return FuseInst(Entry->to, i, FrameIndex, MI);
     }
   }
   
@@ -761,8 +752,7 @@
 
       MachineInstr *New = 0;
       if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
-        New=BuildMI(X86::SUB32ri, 1, X86::ESP, MachineOperand::UseAndDef)
-              .addImm(Amount);
+        New=BuildMI(X86::SUB32ri, 2, X86::ESP).addReg(X86::ESP).addImm(Amount);
       } else {
         assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
         // factor out the amount the callee already popped.
@@ -770,8 +760,7 @@
         Amount -= CalleeAmt;
         if (Amount) {
           unsigned Opc = Amount < 128 ? X86::ADD32ri8 : X86::ADD32ri;
-          New = BuildMI(Opc, 1, X86::ESP,
-                        MachineOperand::UseAndDef).addImm(Amount);
+          New = BuildMI(Opc, 2, X86::ESP).addReg(X86::ESP).addImm(Amount);
         }
       }
 
@@ -785,8 +774,7 @@
     if (unsigned CalleeAmt = I->getOperand(1).getImmedValue()) {
       unsigned Opc = CalleeAmt < 128 ? X86::SUB32ri8 : X86::SUB32ri;
       MachineInstr *New =
-        BuildMI(Opc, 1, X86::ESP,
-                MachineOperand::UseAndDef).addImm(CalleeAmt);
+        BuildMI(Opc, 1, X86::ESP).addReg(X86::ESP).addImm(CalleeAmt);
       MBB.insert(I, New);
     }
   }
@@ -870,7 +858,7 @@
       MBB.insert(MBBI, MI);
     } else {
       unsigned Opc = NumBytes < 128 ? X86::SUB32ri8 : X86::SUB32ri;
-      MI = BuildMI(Opc, 1, X86::ESP,MachineOperand::UseAndDef).addImm(NumBytes);
+      MI = BuildMI(Opc, 2, X86::ESP).addReg(X86::ESP).addImm(NumBytes);
       MBB.insert(MBBI, MI);
     }
   }
@@ -897,7 +885,7 @@
   // If it's main() on Cygwin\Mingw32 we should align stack as well
   if (Fn->hasExternalLinkage() && Fn->getName() == "main" &&
       Subtarget->TargetType == X86Subtarget::isCygwin) {
-    MI = BuildMI(X86::AND32ri, 2, X86::ESP).addImm(-Align);
+    MI = BuildMI(X86::AND32ri, 2, X86::ESP).addReg(X86::ESP).addImm(-Align);
     MBB.insert(MBBI, MI);
 
     // Probe the stack
@@ -929,7 +917,7 @@
     int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexEnd()-1)+4;
 
     // mov ESP, EBP
-    BuildMI(MBB, MBBI, X86::MOV32rr, 1,X86::ESP).addReg(X86::EBP);
+    BuildMI(MBB, MBBI, X86::MOV32rr, 1, X86::ESP).addReg(X86::EBP);
 
     // pop EBP
     BuildMI(MBB, MBBI, X86::POP32r, 0, X86::EBP);
@@ -960,12 +948,10 @@
 
       if (NumBytes > 0) {
         unsigned Opc = NumBytes < 128 ? X86::ADD32ri8 : X86::ADD32ri;
-        BuildMI(MBB, MBBI, Opc, 2)
-          .addReg(X86::ESP, MachineOperand::UseAndDef).addImm(NumBytes);
+        BuildMI(MBB, MBBI, Opc, 2, X86::ESP).addReg(X86::ESP).addImm(NumBytes);
       } else if ((int)NumBytes < 0) {
         unsigned Opc = -NumBytes < 128 ? X86::SUB32ri8 : X86::SUB32ri;
-        BuildMI(MBB, MBBI, Opc, 2)
-          .addReg(X86::ESP, MachineOperand::UseAndDef).addImm(-NumBytes);
+        BuildMI(MBB, MBBI, Opc, 2, X86::ESP).addReg(X86::ESP).addImm(-NumBytes);
       }
     }
   }


Index: llvm/lib/Target/X86/X86RegisterInfo.h
diff -u llvm/lib/Target/X86/X86RegisterInfo.h:1.39 llvm/lib/Target/X86/X86RegisterInfo.h:1.40
--- llvm/lib/Target/X86/X86RegisterInfo.h:1.39	Wed May 17 19:12:58 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.h	Mon Sep  4 21:12:02 2006
@@ -15,15 +15,15 @@
 #define X86REGISTERINFO_H
 
 #include "llvm/Target/MRegisterInfo.h"
-
-class llvm::Type;
-
 #include "X86GenRegisterInfo.h.inc"
 
 namespace llvm {
+  class Type;
+  class TargetInstrInfo;
 
 struct X86RegisterInfo : public X86GenRegisterInfo {
-  X86RegisterInfo();
+  const TargetInstrInfo &TII;
+  X86RegisterInfo(const TargetInstrInfo &tii);
 
   /// Code Generation virtual methods...
   void storeRegToStackSlot(MachineBasicBlock &MBB,





From lattner at cs.uiuc.edu  Mon Sep  4 21:31:37 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 4 Sep 2006 21:31:37 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
Message-ID: <200609050231.k852Vb8m020042@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaRegisterInfo.cpp updated: 1.47 -> 1.48
---
Log message:

Completely eliminate def&use operands.  Now a register operand is EITHER a
def operand or a use operand.


---
Diffs of the changes:  (+28 -16)

 AlphaRegisterInfo.cpp |   44 ++++++++++++++++++++++++++++----------------
 1 files changed, 28 insertions(+), 16 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
diff -u llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.47 llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.48
--- llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.47	Thu Aug 17 17:00:07 2006
+++ llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp	Mon Sep  4 21:31:13 2006
@@ -67,14 +67,18 @@
                                        MachineBasicBlock::iterator MI,
                                        unsigned SrcReg, int FrameIdx,
                                        const TargetRegisterClass *RC) const {
-  //std::cerr << "Trying to store " << getPrettyName(SrcReg) << " to " << FrameIdx << "\n";
+  //std::cerr << "Trying to store " << getPrettyName(SrcReg) << " to "
+  //<< FrameIdx << "\n";
   //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
   if (RC == Alpha::F4RCRegisterClass)
-    BuildMI(MBB, MI, Alpha::STS, 3).addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
+    BuildMI(MBB, MI, Alpha::STS, 3)
+      .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
   else if (RC == Alpha::F8RCRegisterClass)
-    BuildMI(MBB, MI, Alpha::STT, 3).addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
+    BuildMI(MBB, MI, Alpha::STT, 3)
+      .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
   else if (RC == Alpha::GPRCRegisterClass)
-    BuildMI(MBB, MI, Alpha::STQ, 3).addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
+    BuildMI(MBB, MI, Alpha::STQ, 3)
+      .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
   else
     abort();
 }
@@ -84,13 +88,17 @@
                                         MachineBasicBlock::iterator MI,
                                         unsigned DestReg, int FrameIdx,
                                         const TargetRegisterClass *RC) const {
-  //std::cerr << "Trying to load " << getPrettyName(DestReg) << " to " << FrameIdx << "\n";
+  //std::cerr << "Trying to load " << getPrettyName(DestReg) << " to "
+  //<< FrameIdx << "\n";
   if (RC == Alpha::F4RCRegisterClass)
-    BuildMI(MBB, MI, Alpha::LDS, 2, DestReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
+    BuildMI(MBB, MI, Alpha::LDS, 2, DestReg)
+      .addFrameIndex(FrameIdx).addReg(Alpha::F31);
   else if (RC == Alpha::F8RCRegisterClass)
-    BuildMI(MBB, MI, Alpha::LDT, 2, DestReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
+    BuildMI(MBB, MI, Alpha::LDT, 2, DestReg)
+      .addFrameIndex(FrameIdx).addReg(Alpha::F31);
   else if (RC == Alpha::GPRCRegisterClass)
-    BuildMI(MBB, MI, Alpha::LDQ, 2, DestReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
+    BuildMI(MBB, MI, Alpha::LDQ, 2, DestReg)
+      .addFrameIndex(FrameIdx).addReg(Alpha::F31);
   else
     abort();
 }
@@ -243,7 +251,7 @@
   int FrameIndex = MI.getOperand(i).getFrameIndex();
 
   // Add the base register of R30 (SP) or R15 (FP).
-  MI.getOperand(i + 1).ChangeToRegister(FP ? Alpha::R15 : Alpha::R30);
+  MI.getOperand(i + 1).ChangeToRegister(FP ? Alpha::R15 : Alpha::R30, false);
 
   // Now add the frame object offset to the offset from the virtual frame index.
   int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
@@ -256,11 +264,12 @@
         " for stack size: " << MF.getFrameInfo()->getStackSize() << "\n");
 
   if (Offset > IMM_HIGH || Offset < IMM_LOW) {
-    DEBUG(std::cerr << "Unconditionally using R28 for evil purposes Offset: " << Offset << "\n");
-    //so in this case, we need to use a temporary register, and move the original
-    //inst off the SP/FP
+    DEBUG(std::cerr << "Unconditionally using R28 for evil purposes Offset: "
+          << Offset << "\n");
+    //so in this case, we need to use a temporary register, and move the
+    //original inst off the SP/FP
     //fix up the old:
-    MI.getOperand(i + 1).ChangeToRegister(Alpha::R28);
+    MI.getOperand(i + 1).ChangeToRegister(Alpha::R28, false);
     MI.getOperand(i).ChangeToImmediate(getLower16(Offset));
     //insert the new
     MachineInstr* nMI=BuildMI(Alpha::LDAH, 2, Alpha::R28)
@@ -335,9 +344,11 @@
   //now if we need to, save the old FP and set the new
   if (FP)
   {
-    BuildMI(MBB, MBBI, Alpha::STQ, 3).addReg(Alpha::R15).addImm(0).addReg(Alpha::R30);
+    BuildMI(MBB, MBBI, Alpha::STQ, 3)
+      .addReg(Alpha::R15).addImm(0).addReg(Alpha::R30);
     //this must be the last instr in the prolog
-    BuildMI(MBB, MBBI, Alpha::BIS, 2, Alpha::R15).addReg(Alpha::R30).addReg(Alpha::R30);
+    BuildMI(MBB, MBBI, Alpha::BIS, 2, Alpha::R15)
+      .addReg(Alpha::R30).addReg(Alpha::R30);
   }
 
 }
@@ -346,7 +357,8 @@
                                      MachineBasicBlock &MBB) const {
   const MachineFrameInfo *MFI = MF.getFrameInfo();
   MachineBasicBlock::iterator MBBI = prior(MBB.end());
-  assert(MBBI->getOpcode() == Alpha::RETDAG || MBBI->getOpcode() == Alpha::RETDAGp
+  assert(MBBI->getOpcode() == Alpha::RETDAG ||
+         MBBI->getOpcode() == Alpha::RETDAGp
          && "Can only insert epilog into returning blocks");
 
   bool FP = hasFP(MF);





From lattner at cs.uiuc.edu  Mon Sep  4 21:31:38 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 4 Sep 2006 21:31:38 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineInstr.h
	MachineInstrBuilder.h
Message-ID: <200609050231.k852Vcrr020057@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

MachineInstr.h updated: 1.184 -> 1.185
MachineInstrBuilder.h updated: 1.36 -> 1.37
---
Log message:

Completely eliminate def&use operands.  Now a register operand is EITHER a
def operand or a use operand.


---
Diffs of the changes:  (+17 -55)

 MachineInstr.h        |   56 +++++++++-----------------------------------------
 MachineInstrBuilder.h |   16 +++++---------
 2 files changed, 17 insertions(+), 55 deletions(-)


Index: llvm/include/llvm/CodeGen/MachineInstr.h
diff -u llvm/include/llvm/CodeGen/MachineInstr.h:1.184 llvm/include/llvm/CodeGen/MachineInstr.h:1.185
--- llvm/include/llvm/CodeGen/MachineInstr.h:1.184	Mon Sep  4 18:35:22 2006
+++ llvm/include/llvm/CodeGen/MachineInstr.h	Mon Sep  4 21:31:13 2006
@@ -38,26 +38,6 @@
 //   Representation of each machine instruction operand.
 //
 struct MachineOperand {
-private:
-  // Bit fields of the flags variable used for different operand properties
-  enum {
-    DEFFLAG     = 0x01,       // this is a def of the operand
-    USEFLAG     = 0x02        // this is a use of the operand
-  };
-
-public:
-  // UseType - This enum describes how the machine operand is used by
-  // the instruction. Note that the MachineInstr/Operator class
-  // currently uses bool arguments to represent this information
-  // instead of an enum.  Eventually this should change over to use
-  // this _easier to read_ representation instead.
-  //
-  enum UseType {
-    Use = USEFLAG,        /// only read
-    Def = DEFFLAG,        /// only written
-    UseAndDef = Use | Def /// read AND written
-  };
-
   enum MachineOperandType {
     MO_Register,                // Register operand.
     MO_Immediate,               // Immediate Operand
@@ -78,8 +58,8 @@
     int64_t immedVal;         // For MO_Immediate and MO_*Index.
   } contents;
 
-  char flags;                   // see bit field definitions above
-  MachineOperandType opType:8;  // Pack into 8 bits efficiently after flags.
+  MachineOperandType opType:8; // Discriminate the union.
+  bool IsDef : 1;              // True if this is a def, false if this is a use.
   
   /// offset - Offset to address of global or external, only valid for
   /// MO_GlobalAddress, MO_ExternalSym and MO_ConstantPoolIndex
@@ -95,7 +75,7 @@
 
   const MachineOperand &operator=(const MachineOperand &MO) {
     contents = MO.contents;
-    flags    = MO.flags;
+    IsDef    = MO.IsDef;
     opType   = MO.opType;
     offset   = MO.offset;
     return *this;
@@ -105,10 +85,6 @@
   ///
   MachineOperandType getType() const { return opType; }
 
-  /// getUseType - Returns the MachineOperandUseType of this operand.
-  ///
-  UseType getUseType() const { return UseType(flags & (USEFLAG|DEFFLAG)); }
-
   /// Accessors that tell you what kind of MachineOperand you're looking at.
   ///
   bool isReg() const { return opType == MO_Register; }
@@ -167,13 +143,10 @@
     return contents.SymbolName;
   }
 
-  /// MachineOperand methods for testing that work on any kind of
-  /// MachineOperand...
-  ///
-  bool isUse() const { return flags & USEFLAG; }
-  bool isDef() const { return flags & DEFFLAG; }
-  MachineOperand &setUse() { flags |= USEFLAG; return *this; }
-  MachineOperand &setDef() { flags |= DEFFLAG; return *this; }
+  bool isUse() const { return !IsDef; }
+  bool isDef() const { return IsDef; }
+  void setIsUse() { IsDef = false; }
+  void setIsDef() { IsDef = true; }
 
   /// getReg - Returns the register number.
   ///
@@ -216,9 +189,10 @@
   /// ChangeToRegister - Replace this operand with a new register operand of
   /// the specified value.  If an operand is known to be an register already,
   /// the setReg method should be used.
-  void ChangeToRegister(unsigned Reg) {
+  void ChangeToRegister(unsigned Reg, bool isDef) {
     opType = MO_Register;
     contents.RegNo = Reg;
+    IsDef = isDef;
   }
 
   friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
@@ -307,11 +281,10 @@
 
   /// addRegOperand - Add a register operand.
   ///
-  void addRegOperand(unsigned Reg,
-                     MachineOperand::UseType UTy = MachineOperand::Use) {
+  void addRegOperand(unsigned Reg, bool IsDef) {
     MachineOperand &Op = AddNewOperand();
     Op.opType = MachineOperand::MO_Register;
-    Op.flags = UTy;
+    Op.IsDef = IsDef;
     Op.contents.RegNo = Reg;
     Op.offset = 0;
   }
@@ -322,7 +295,6 @@
   void addImmOperand(int64_t Val) {
     MachineOperand &Op = AddNewOperand();
     Op.opType = MachineOperand::MO_Immediate;
-    Op.flags = 0;
     Op.contents.immedVal = Val;
     Op.offset = 0;
   }
@@ -330,7 +302,6 @@
   void addMachineBasicBlockOperand(MachineBasicBlock *MBB) {
     MachineOperand &Op = AddNewOperand();
     Op.opType = MachineOperand::MO_MachineBasicBlock;
-    Op.flags = 0;
     Op.contents.MBB = MBB;
     Op.offset = 0;
   }
@@ -340,7 +311,6 @@
   void addFrameIndexOperand(unsigned Idx) {
     MachineOperand &Op = AddNewOperand();
     Op.opType = MachineOperand::MO_FrameIndex;
-    Op.flags = 0;
     Op.contents.immedVal = Idx;
     Op.offset = 0;
   }
@@ -351,7 +321,6 @@
   void addConstantPoolIndexOperand(unsigned Idx, int Offset) {
     MachineOperand &Op = AddNewOperand();
     Op.opType = MachineOperand::MO_ConstantPoolIndex;
-    Op.flags = 0;
     Op.contents.immedVal = Idx;
     Op.offset = Offset;
   }
@@ -362,7 +331,6 @@
   void addJumpTableIndexOperand(unsigned Idx) {
     MachineOperand &Op = AddNewOperand();
     Op.opType = MachineOperand::MO_JumpTableIndex;
-    Op.flags = 0;
     Op.contents.immedVal = Idx;
     Op.offset = 0;
   }
@@ -370,7 +338,6 @@
   void addGlobalAddressOperand(GlobalValue *GV, int Offset) {
     MachineOperand &Op = AddNewOperand();
     Op.opType = MachineOperand::MO_GlobalAddress;
-    Op.flags = 0;
     Op.contents.GV = GV;
     Op.offset = Offset;
   }
@@ -380,7 +347,6 @@
   void addExternalSymbolOperand(const char *SymName) {
     MachineOperand &Op = AddNewOperand();
     Op.opType = MachineOperand::MO_ExternalSymbol;
-    Op.flags = 0;
     Op.contents.SymbolName = SymName;
     Op.offset = 0;
   }


Index: llvm/include/llvm/CodeGen/MachineInstrBuilder.h
diff -u llvm/include/llvm/CodeGen/MachineInstrBuilder.h:1.36 llvm/include/llvm/CodeGen/MachineInstrBuilder.h:1.37
--- llvm/include/llvm/CodeGen/MachineInstrBuilder.h:1.36	Thu May  4 13:16:01 2006
+++ llvm/include/llvm/CodeGen/MachineInstrBuilder.h	Mon Sep  4 21:31:13 2006
@@ -33,10 +33,8 @@
 
   /// addReg - Add a new virtual register operand...
   ///
-  const MachineInstrBuilder &addReg(
-    int RegNo,
-    MachineOperand::UseType Ty = MachineOperand::Use) const {
-    MI->addRegOperand(RegNo, Ty);
+  const MachineInstrBuilder &addReg(int RegNo, bool isDef = false) const {
+    MI->addRegOperand(RegNo, isDef);
     return *this;
   }
 
@@ -92,12 +90,10 @@
 /// destination virtual register.  NumOperands is the number of additional add*
 /// calls that are expected, not including the destination register.
 ///
-inline MachineInstrBuilder BuildMI(
-  int Opcode, unsigned NumOperands,
-  unsigned DestReg,
-  MachineOperand::UseType useType = MachineOperand::Def) {
+inline MachineInstrBuilder 
+BuildMI(int Opcode, unsigned NumOperands, unsigned DestReg) {
   return MachineInstrBuilder(new MachineInstr(Opcode, NumOperands+1))
-               .addReg(DestReg, useType);
+               .addReg(DestReg, true);
 }
 
 /// BuildMI - This version of the builder inserts the newly-built
@@ -112,7 +108,7 @@
                                    unsigned DestReg) {
   MachineInstr *MI = new MachineInstr(Opcode, NumOperands+1);
   BB.insert(I, MI);
-  return MachineInstrBuilder(MI).addReg(DestReg, MachineOperand::Def);
+  return MachineInstrBuilder(MI).addReg(DestReg, true);
 }
 
 /// BuildMI - This version of the builder inserts the newly-built





From lattner at cs.uiuc.edu  Mon Sep  4 21:31:38 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 4 Sep 2006 21:31:38 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcRegisterInfo.cpp
Message-ID: <200609050231.k852Vcfl020054@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Sparc:

SparcRegisterInfo.cpp updated: 1.44 -> 1.45
---
Log message:

Completely eliminate def&use operands.  Now a register operand is EITHER a
def operand or a use operand.


---
Diffs of the changes:  (+2 -2)

 SparcRegisterInfo.cpp |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/Sparc/SparcRegisterInfo.cpp
diff -u llvm/lib/Target/Sparc/SparcRegisterInfo.cpp:1.44 llvm/lib/Target/Sparc/SparcRegisterInfo.cpp:1.45
--- llvm/lib/Target/Sparc/SparcRegisterInfo.cpp:1.44	Wed May 17 19:12:45 2006
+++ llvm/lib/Target/Sparc/SparcRegisterInfo.cpp	Mon Sep  4 21:31:13 2006
@@ -147,7 +147,7 @@
   if (Offset >= -4096 && Offset <= 4095) {
     // If the offset is small enough to fit in the immediate field, directly
     // encode it.
-    MI.getOperand(i).ChangeToRegister(SP::I6);
+    MI.getOperand(i).ChangeToRegister(SP::I6, false);
     MI.getOperand(i+1).ChangeToImmediate(Offset);
   } else {
     // Otherwise, emit a G1 = SETHI %hi(offset).  FIXME: it would be better to 
@@ -158,7 +158,7 @@
     BuildMI(*MI.getParent(), II, SP::ADDrr, 2, 
             SP::G1).addReg(SP::G1).addReg(SP::I6);
     // Insert: G1+%lo(offset) into the user.
-    MI.getOperand(i).ChangeToRegister(SP::G1);
+    MI.getOperand(i).ChangeToRegister(SP::G1, false);
     MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
   }
 }





From lattner at cs.uiuc.edu  Mon Sep  4 21:31:37 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 4 Sep 2006 21:31:37 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
Message-ID: <200609050231.k852VbBT020043@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCRegisterInfo.cpp updated: 1.75 -> 1.76
---
Log message:

Completely eliminate def&use operands.  Now a register operand is EITHER a
def operand or a use operand.


---
Diffs of the changes:  (+3 -3)

 PPCRegisterInfo.cpp |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.75 llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.76
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.75	Tue Aug 29 11:24:26 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp	Mon Sep  4 21:31:13 2006
@@ -421,7 +421,7 @@
   int FrameIndex = MI.getOperand(i).getFrameIndex();
 
   // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
-  MI.getOperand(i).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1);
+  MI.getOperand(i).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1, false);
 
   // Take into account whether it's an add or mem instruction
   unsigned OffIdx = (i == 2) ? 1 : 2;
@@ -466,8 +466,8 @@
            "No indexed form of load or store available!");
     unsigned NewOpcode = ImmToIdxMap.find(MI.getOpcode())->second;
     MI.setOpcode(NewOpcode);
-    MI.getOperand(1).ChangeToRegister(MI.getOperand(i).getReg());
-    MI.getOperand(2).ChangeToRegister(PPC::R0);
+    MI.getOperand(1).ChangeToRegister(MI.getOperand(i).getReg(), false);
+    MI.getOperand(2).ChangeToRegister(PPC::R0, false);
   } else {
     if (isIXAddr) {
       assert((Offset & 3) == 0 && "Invalid frame offset!");





From lattner at cs.uiuc.edu  Mon Sep  4 21:31:38 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 4 Sep 2006 21:31:38 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
	SelectionDAGISel.cpp
Message-ID: <200609050231.k852VcKi020060@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

ScheduleDAG.cpp updated: 1.101 -> 1.102
SelectionDAGISel.cpp updated: 1.271 -> 1.272
---
Log message:

Completely eliminate def&use operands.  Now a register operand is EITHER a
def operand or a use operand.


---
Diffs of the changes:  (+12 -12)

 ScheduleDAG.cpp      |   16 ++++++++--------
 SelectionDAGISel.cpp |    8 ++++----
 2 files changed, 12 insertions(+), 12 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.101 llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.102
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.101	Wed Aug 16 19:09:56 2006
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp	Mon Sep  4 21:31:13 2006
@@ -255,11 +255,11 @@
   // the machine instruction.
   unsigned ResultReg =
     RegMap->createVirtualRegister(getInstrOperandRegClass(MRI, TII, &II, 0));
-  MI->addRegOperand(ResultReg, MachineOperand::Def);
+  MI->addRegOperand(ResultReg, true);
   for (unsigned i = 1; i != NumResults; ++i) {
     const TargetRegisterClass *RC = getInstrOperandRegClass(MRI, TII, &II, i);
     assert(RC && "Isn't a register operand!");
-    MI->addRegOperand(RegMap->createVirtualRegister(RC), MachineOperand::Def);
+    MI->addRegOperand(RegMap->createVirtualRegister(RC), true);
   }
   return ResultReg;
 }
@@ -291,7 +291,7 @@
     
     // Get/emit the operand.
     unsigned VReg = getVR(Op, VRBaseMap);
-    MI->addRegOperand(VReg, MachineOperand::Use);
+    MI->addRegOperand(VReg, false);
     
     // Verify that it is right.
     assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
@@ -307,7 +307,7 @@
     MI->addImmOperand(C->getValue());
   } else if (RegisterSDNode*R =
              dyn_cast<RegisterSDNode>(Op)) {
-    MI->addRegOperand(R->getReg(), MachineOperand::Use);
+    MI->addRegOperand(R->getReg(), false);
   } else if (GlobalAddressSDNode *TGA =
              dyn_cast<GlobalAddressSDNode>(Op)) {
     MI->addGlobalAddressOperand(TGA->getGlobal(), TGA->getOffset());
@@ -349,7 +349,7 @@
            Op.getValueType() != MVT::Flag &&
            "Chain and flag operands should occur at end of operand list!");
     unsigned VReg = getVR(Op, VRBaseMap);
-    MI->addRegOperand(VReg, MachineOperand::Use);
+    MI->addRegOperand(VReg, false);
     
     // Verify that it is right.
     assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
@@ -402,7 +402,7 @@
           unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
           if (MRegisterInfo::isVirtualRegister(Reg)) {
             VRBase = Reg;
-            MI->addRegOperand(Reg, MachineOperand::Def);
+            MI->addRegOperand(Reg, true);
             break;
           }
         }
@@ -529,13 +529,13 @@
         case 1:  // Use of register.
           for (; NumVals; --NumVals, ++i) {
             unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
-            MI->addRegOperand(Reg, MachineOperand::Use);
+            MI->addRegOperand(Reg, false);
           }
           break;
         case 2:   // Def of register.
           for (; NumVals; --NumVals, ++i) {
             unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
-            MI->addRegOperand(Reg, MachineOperand::Def);
+            MI->addRegOperand(Reg, true);
           }
           break;
         case 3: { // Immediate.


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.271 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.272
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.271	Sun Aug 27 07:54:01 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	Mon Sep  4 21:31:13 2006
@@ -3547,7 +3547,7 @@
       MachineInstr *PHI = PHINodesToUpdate[i].first;
       assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
              "This is not a machine PHI node that we are updating!");
-      PHI->addRegOperand(PHINodesToUpdate[i].second);
+      PHI->addRegOperand(PHINodesToUpdate[i].second, false);
       PHI->addMachineBasicBlockOperand(BB);
     }
     return;
@@ -3576,11 +3576,11 @@
       assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
              "This is not a machine PHI node that we are updating!");
       if (PHIBB == JT.Default) {
-        PHI->addRegOperand(PHINodesToUpdate[pi].second);
+        PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
         PHI->addMachineBasicBlockOperand(RangeBB);
       }
       if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
-        PHI->addRegOperand(PHINodesToUpdate[pi].second);
+        PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
         PHI->addMachineBasicBlockOperand(BB);
       }
     }
@@ -3610,7 +3610,7 @@
       assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
              "This is not a machine PHI node that we are updating!");
       if (PHIBB == SwitchCases[i].LHSBB || PHIBB == SwitchCases[i].RHSBB) {
-        PHI->addRegOperand(PHINodesToUpdate[pi].second);
+        PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
         PHI->addMachineBasicBlockOperand(BB);
       }
     }





From lattner at cs.uiuc.edu  Mon Sep  4 21:31:39 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 4 Sep 2006 21:31:39 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp
Message-ID: <200609050231.k852VdFu020071@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.164 -> 1.165
---
Log message:

Completely eliminate def&use operands.  Now a register operand is EITHER a
def operand or a use operand.


---
Diffs of the changes:  (+2 -2)

 X86RegisterInfo.cpp |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.164 llvm/lib/Target/X86/X86RegisterInfo.cpp:1.165
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.164	Mon Sep  4 21:12:02 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp	Mon Sep  4 21:31:13 2006
@@ -168,7 +168,7 @@
       assert(MO.isReg() && "Expected to fold into reg operand!");
       MIB = addFrameReference(MIB, FrameIndex);
     } else if (MO.isReg())
-      MIB = MIB.addReg(MO.getReg(), MO.getUseType());
+      MIB = MIB.addReg(MO.getReg(), MO.isDef());
     else if (MO.isImm())
       MIB = MIB.addImm(MO.getImm());
     else if (MO.isGlobalAddress())
@@ -795,7 +795,7 @@
 
   // This must be part of a four operand memory reference.  Replace the
   // FrameIndex with base register with EBP.  Add add an offset to the offset.
-  MI.getOperand(i).ChangeToRegister(hasFP(MF) ? X86::EBP : X86::ESP);
+  MI.getOperand(i).ChangeToRegister(hasFP(MF) ? X86::EBP : X86::ESP, false);
 
   // Now add the frame object offset to the offset from EBP.
   int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +





From lattner at cs.uiuc.edu  Mon Sep  4 21:31:39 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 4 Sep 2006 21:31:39 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/ARM/ARMRegisterInfo.cpp
Message-ID: <200609050231.k852Vdgo020079@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/ARM:

ARMRegisterInfo.cpp updated: 1.16 -> 1.17
---
Log message:

Completely eliminate def&use operands.  Now a register operand is EITHER a
def operand or a use operand.


---
Diffs of the changes:  (+2 -2)

 ARMRegisterInfo.cpp |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/ARM/ARMRegisterInfo.cpp
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.16 llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.17
--- llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.16	Thu Aug 17 12:09:40 2006
+++ llvm/lib/Target/ARM/ARMRegisterInfo.cpp	Mon Sep  4 21:31:13 2006
@@ -107,7 +107,7 @@
   assert (Offset >= 0);
   if (Offset < 4096) {
     // Replace the FrameIndex with r13
-    MI.getOperand(FrameIdx).ChangeToRegister(ARM::R13);
+    MI.getOperand(FrameIdx).ChangeToRegister(ARM::R13, false);
     // Replace the ldr offset with Offset
     MI.getOperand(OffIdx).ChangeToImmediate(Offset);
   } else {
@@ -117,7 +117,7 @@
     BuildMI(*MBB2, II, ARM::addri, 2, ARM::R12).addReg(ARM::R13).addImm(Offset);
 
     // Replace the FrameIndex with r12
-    MI.getOperand(FrameIdx).ChangeToRegister(ARM::R12);
+    MI.getOperand(FrameIdx).ChangeToRegister(ARM::R12, false);
   }
 }
 





From lattner at cs.uiuc.edu  Mon Sep  4 21:31:39 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 4 Sep 2006 21:31:39 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/IA64/IA64RegisterInfo.cpp
Message-ID: <200609050231.k852Vdbc020076@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/IA64:

IA64RegisterInfo.cpp updated: 1.21 -> 1.22
---
Log message:

Completely eliminate def&use operands.  Now a register operand is EITHER a
def operand or a use operand.


---
Diffs of the changes:  (+12 -14)

 IA64RegisterInfo.cpp |   26 ++++++++++++--------------
 1 files changed, 12 insertions(+), 14 deletions(-)


Index: llvm/lib/Target/IA64/IA64RegisterInfo.cpp
diff -u llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.21 llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.22
--- llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.21	Thu Aug 17 17:00:08 2006
+++ llvm/lib/Target/IA64/IA64RegisterInfo.cpp	Mon Sep  4 21:31:13 2006
@@ -85,7 +85,8 @@
 
   if(RC == IA64::PRRegisterClass ) // if a bool, we use pseudocode
     // (SrcReg) DestReg = cmp.eq.unc(r0, r0)
-    BuildMI(MBB, MI, IA64::PCMPEQUNC, 3, DestReg).addReg(IA64::r0).addReg(IA64::r0).addReg(SrcReg);
+    BuildMI(MBB, MI, IA64::PCMPEQUNC, 3, DestReg)
+      .addReg(IA64::r0).addReg(IA64::r0).addReg(SrcReg);
   else // otherwise, MOV works (for both gen. regs and FP regs)
     BuildMI(MBB, MI, IA64::MOV, 1, DestReg).addReg(SrcReg);
 }
@@ -152,7 +153,7 @@
   MBB.erase(I);
 }
 
-void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{
+void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II)const{
   unsigned i = 0;
   MachineInstr &MI = *II;
   MachineBasicBlock &MBB = *MI.getParent();
@@ -170,7 +171,7 @@
   // choose a base register: ( hasFP? framepointer : stack pointer )
   unsigned BaseRegister = FP ? IA64::r5 : IA64::r12;
   // Add the base register
-  MI.getOperand(i).ChangeToRegister(BaseRegister);
+  MI.getOperand(i).ChangeToRegister(BaseRegister, false);
 
   // Now add the frame object offset to the offset from r1.
   int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
@@ -181,20 +182,16 @@
   Offset += MF.getFrameInfo()->getStackSize();
 
   // XXX: we use 'r22' as another hack+slash temporary register here :(
-  if ( Offset <= 8191 && Offset >= -8192) { // smallish offset
-    //fix up the old:
-    MI.getOperand(i).ChangeToRegister(IA64::r22);
-    MI.getOperand(i).setUse(); // mark r22 as being used
-                               // (the bundler wants to know this)
+  if (Offset <= 8191 && Offset >= -8192) { // smallish offset
+    // Fix up the old:
+    MI.getOperand(i).ChangeToRegister(IA64::r22, false);
     //insert the new
     MachineInstr* nMI=BuildMI(IA64::ADDIMM22, 2, IA64::r22)
       .addReg(BaseRegister).addImm(Offset);
     MBB.insert(II, nMI);
   } else { // it's big
     //fix up the old:
-    MI.getOperand(i).ChangeToRegister(IA64::r22);
-    MI.getOperand(i).setUse(); // mark r22 as being used
-                               // (the bundler wants to know this)
+    MI.getOperand(i).ChangeToRegister(IA64::r22, false);
     MachineInstr* nMI;
     nMI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addImm(Offset);
     MBB.insert(II, nMI);
@@ -242,7 +239,8 @@
 
   unsigned numOutRegsUsed=MF.getInfo<IA64FunctionInfo>()->outRegsUsed;
 
-  // XXX FIXME : this code should be a bit more reliable (in case there _isn't_ a pseudo_alloc in the MBB)
+  // XXX FIXME : this code should be a bit more reliable (in case there _isn't_
+  // a pseudo_alloc in the MBB)
   unsigned dstRegOfPseudoAlloc;
   for(MBBI = MBB.begin(); /*MBBI->getOpcode() != IA64::PSEUDO_ALLOC*/; ++MBBI) {
     assert(MBBI != MBB.end());
@@ -284,7 +282,7 @@
 
   // adjust stack pointer: r12 -= numbytes
   if (NumBytes <= 8191) {
-    MI=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12).addImm(-NumBytes);
+    MI=BuildMI(IA64::ADDIMM22,2,IA64::r12).addReg(IA64::r12).addImm(-NumBytes);
     MBB.insert(MBBI, MI);
   } else { // we use r22 as a scratch register here
     MI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addImm(-NumBytes);
@@ -332,7 +330,7 @@
   if (NumBytes != 0)
   {
     if (NumBytes <= 8191) {
-      MI=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12).addImm(NumBytes);
+      MI=BuildMI(IA64::ADDIMM22,2,IA64::r12).addReg(IA64::r12).addImm(NumBytes);
       MBB.insert(MBBI, MI);
     } else {
       MI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addImm(NumBytes);





From lattner at cs.uiuc.edu  Mon Sep  4 21:52:49 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 4 Sep 2006 21:52:49 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86CodeEmitter.cpp
Message-ID: <200609050252.k852qnx4020444@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86CodeEmitter.cpp updated: 1.114 -> 1.115
---
Log message:

Update the X86 JIT to make it work with the new two-addr changes.  This also
adds assertions that check to make sure every operand gets emitted.


---
Diffs of the changes:  (+51 -40)

 X86CodeEmitter.cpp |   91 +++++++++++++++++++++++++++++------------------------
 1 files changed, 51 insertions(+), 40 deletions(-)


Index: llvm/lib/Target/X86/X86CodeEmitter.cpp
diff -u llvm/lib/Target/X86/X86CodeEmitter.cpp:1.114 llvm/lib/Target/X86/X86CodeEmitter.cpp:1.115
--- llvm/lib/Target/X86/X86CodeEmitter.cpp:1.114	Sun Aug 27 07:54:01 2006
+++ llvm/lib/Target/X86/X86CodeEmitter.cpp	Mon Sep  4 21:52:35 2006
@@ -246,7 +246,7 @@
   } else if (Op3.isJumpTableIndex()) {
     DispVal += MCE.getJumpTableEntryAddress(Op3.getJumpTableIndex());
   } else {
-    DispVal = Op3.getImmedValue();
+    DispVal = Op3.getImm();
   }
 
   const MachineOperand &Base     = MI.getOperand(Op);
@@ -306,7 +306,7 @@
 
     // Calculate what the SS field value should be...
     static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
-    unsigned SS = SSTable[Scale.getImmedValue()];
+    unsigned SS = SSTable[Scale.getImm()];
 
     if (BaseReg == 0) {
       // Handle the SIB byte for the case where there is no base.  The
@@ -377,6 +377,10 @@
   case 0: break;  // No prefix!
   }
 
+  // If this is a two-address instruction, skip one of the register operands.
+  unsigned CurOp = 0;
+  CurOp += (Desc.Flags & M_2_ADDR_FLAG) != 0;
+  
   unsigned char BaseOpcode = II->getBaseOpcodeFor(Opcode);
   switch (Desc.TSFlags & X86II::FormMask) {
   default: assert(0 && "Unknown FormMask value in X86 MachineCodeEmitter!");
@@ -401,12 +405,13 @@
       break;
     }
 #endif
+    CurOp = MI.getNumOperands();
     break;
 
   case X86II::RawFrm:
     MCE.emitByte(BaseOpcode);
-    if (Desc.numOperands == 1) {
-      const MachineOperand &MO = MI.getOperand(0);
+    if (CurOp != MI.getNumOperands()) {
+      const MachineOperand &MO = MI.getOperand(CurOp++);
       if (MO.isMachineBasicBlock()) {
         emitPCRelativeBlockAddress(MO.getMachineBasicBlock());
       } else if (MO.isGlobalAddress()) {
@@ -416,7 +421,7 @@
       } else if (MO.isExternalSymbol()) {
         emitExternalSymbolAddress(MO.getSymbolName(), true);
       } else if (MO.isImmediate()) {
-        emitConstant(MO.getImmedValue(), sizeOfImm(Desc));
+        emitConstant(MO.getImm(), sizeOfImm(Desc));
       } else {
         assert(0 && "Unknown RawFrm operand!");
       }
@@ -424,9 +429,10 @@
     break;
 
   case X86II::AddRegFrm:
-    MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(0).getReg()));
-    if (MI.getNumOperands() == 2) {
-      const MachineOperand &MO1 = MI.getOperand(1);
+    MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++).getReg()));
+    
+    if (CurOp != MI.getNumOperands()) {
+      const MachineOperand &MO1 = MI.getOperand(CurOp++);
       if (MO1.isGlobalAddress()) {
         assert(sizeOfImm(Desc) == 4 &&
                "Don't know how to emit non-pointer values!");
@@ -440,39 +446,43 @@
                "Don't know how to emit non-pointer values!");
         emitConstant(MCE.getJumpTableEntryAddress(MO1.getJumpTableIndex()), 4);
       } else {
-        emitConstant(MO1.getImmedValue(), sizeOfImm(Desc));
+        emitConstant(MO1.getImm(), sizeOfImm(Desc));
       }
     }
     break;
 
   case X86II::MRMDestReg: {
     MCE.emitByte(BaseOpcode);
-    emitRegModRMByte(MI.getOperand(0).getReg(),
-                     getX86RegNum(MI.getOperand(1).getReg()));
-    if (MI.getNumOperands() == 3)
-      emitConstant(MI.getOperand(2).getImmedValue(), sizeOfImm(Desc));
+    emitRegModRMByte(MI.getOperand(CurOp).getReg(),
+                     getX86RegNum(MI.getOperand(CurOp+1).getReg()));
+    CurOp += 2;
+    if (CurOp != MI.getNumOperands())
+      emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
     break;
   }
   case X86II::MRMDestMem:
     MCE.emitByte(BaseOpcode);
-    emitMemModRMByte(MI, 0, getX86RegNum(MI.getOperand(4).getReg()));
-    if (MI.getNumOperands() == 6)
-      emitConstant(MI.getOperand(5).getImmedValue(), sizeOfImm(Desc));
+    emitMemModRMByte(MI, CurOp, getX86RegNum(MI.getOperand(CurOp+4).getReg()));
+    CurOp += 5;
+    if (CurOp != MI.getNumOperands())
+      emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
     break;
 
   case X86II::MRMSrcReg:
     MCE.emitByte(BaseOpcode);
-    emitRegModRMByte(MI.getOperand(1).getReg(),
-                     getX86RegNum(MI.getOperand(0).getReg()));
-    if (MI.getNumOperands() == 3)
-      emitConstant(MI.getOperand(2).getImmedValue(), sizeOfImm(Desc));
+    emitRegModRMByte(MI.getOperand(CurOp+1).getReg(),
+                     getX86RegNum(MI.getOperand(CurOp).getReg()));
+    CurOp += 2;
+    if (CurOp != MI.getNumOperands())
+      emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
     break;
 
   case X86II::MRMSrcMem:
     MCE.emitByte(BaseOpcode);
-    emitMemModRMByte(MI, 1, getX86RegNum(MI.getOperand(0).getReg()));
-    if (MI.getNumOperands() == 2+4)
-      emitConstant(MI.getOperand(5).getImmedValue(), sizeOfImm(Desc));
+    emitMemModRMByte(MI, CurOp+1, getX86RegNum(MI.getOperand(CurOp).getReg()));
+    CurOp += 5;
+    if (CurOp != MI.getNumOperands())
+      emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
     break;
 
   case X86II::MRM0r: case X86II::MRM1r:
@@ -480,13 +490,11 @@
   case X86II::MRM4r: case X86II::MRM5r:
   case X86II::MRM6r: case X86II::MRM7r:
     MCE.emitByte(BaseOpcode);
-    emitRegModRMByte(MI.getOperand(0).getReg(),
+    emitRegModRMByte(MI.getOperand(CurOp++).getReg(),
                      (Desc.TSFlags & X86II::FormMask)-X86II::MRM0r);
 
-    if (MI.getOperand(MI.getNumOperands()-1).isImmediate()) {
-      emitConstant(MI.getOperand(MI.getNumOperands()-1).getImmedValue(),
-                   sizeOfImm(Desc));
-    }
+    if (CurOp != MI.getNumOperands())
+      emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
     break;
 
   case X86II::MRM0m: case X86II::MRM1m:
@@ -494,17 +502,17 @@
   case X86II::MRM4m: case X86II::MRM5m:
   case X86II::MRM6m: case X86II::MRM7m:
     MCE.emitByte(BaseOpcode);
-    emitMemModRMByte(MI, 0, (Desc.TSFlags & X86II::FormMask)-X86II::MRM0m);
+    emitMemModRMByte(MI, CurOp, (Desc.TSFlags & X86II::FormMask)-X86II::MRM0m);
+    CurOp += 4;
 
-    if (MI.getNumOperands() == 5) {
-      if (MI.getOperand(4).isImmediate())
-        emitConstant(MI.getOperand(4).getImmedValue(), sizeOfImm(Desc));
-      else if (MI.getOperand(4).isGlobalAddress())
-        emitGlobalAddressForPtr(MI.getOperand(4).getGlobal(),
-                                MI.getOperand(4).getOffset());
-      else if (MI.getOperand(4).isJumpTableIndex())
-        emitConstant(MCE.getJumpTableEntryAddress(MI.getOperand(4)
-                                                    .getJumpTableIndex()), 4);
+    if (CurOp != MI.getNumOperands()) {
+      const MachineOperand &MO = MI.getOperand(CurOp++);
+      if (MO.isImmediate())
+        emitConstant(MO.getImm(), sizeOfImm(Desc));
+      else if (MO.isGlobalAddress())
+        emitGlobalAddressForPtr(MO.getGlobal(), MO.getOffset());
+      else if (MO.isJumpTableIndex())
+        emitConstant(MCE.getJumpTableEntryAddress(MO.getJumpTableIndex()), 4);
       else
         assert(0 && "Unknown operand!");
     }
@@ -512,8 +520,11 @@
 
   case X86II::MRMInitReg:
     MCE.emitByte(BaseOpcode);
-    emitRegModRMByte(MI.getOperand(0).getReg(),
-                     getX86RegNum(MI.getOperand(0).getReg()));
+    // Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
+    emitRegModRMByte(MI.getOperand(CurOp).getReg(),
+                     getX86RegNum(MI.getOperand(CurOp).getReg()));
+    ++CurOp;
     break;
   }
+  assert(CurOp == MI.getNumOperands() && "Unknown encoding!");
 }





From lattner at cs.uiuc.edu  Mon Sep  4 22:02:06 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Mon, 4 Sep 2006 22:02:06 -0500
Subject: [llvm-commits] CVS: llvm/utils/TableGen/CodeEmitterGen.cpp
Message-ID: <200609050302.k853262g020647@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

CodeEmitterGen.cpp updated: 1.48 -> 1.49
---
Log message:

Fix JIT encoding of two-addr instructions.


---
Diffs of the changes:  (+5 -0)

 CodeEmitterGen.cpp |    5 +++++
 1 files changed, 5 insertions(+)


Index: llvm/utils/TableGen/CodeEmitterGen.cpp
diff -u llvm/utils/TableGen/CodeEmitterGen.cpp:1.48 llvm/utils/TableGen/CodeEmitterGen.cpp:1.49
--- llvm/utils/TableGen/CodeEmitterGen.cpp:1.48	Thu Jul 13 17:17:08 2006
+++ llvm/utils/TableGen/CodeEmitterGen.cpp	Mon Sep  4 22:01:52 2006
@@ -161,6 +161,11 @@
                    +  utostr(op++)
                    +  "));\n";
               gotOp = true;
+              
+              // If this is a two-address instruction and we just got the dest
+              // op, skip the src op.
+              if (op == 1 && Target.getInstruction(InstName).isTwoAddress)
+                ++op;
             }
             
             unsigned opMask = (1 << N) - 1;





From evan.cheng at apple.com  Tue Sep  5 00:59:39 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 5 Sep 2006 00:59:39 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td
Message-ID: <200609050559.k855xdgW023350@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86InstrSSE.td updated: 1.130 -> 1.131
---
Log message:

JIT encoding bug.

---
Diffs of the changes:  (+1 -1)

 X86InstrSSE.td |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.130 llvm/lib/Target/X86/X86InstrSSE.td:1.131
--- llvm/lib/Target/X86/X86InstrSSE.td:1.130	Tue Jul 25 15:25:40 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td	Tue Sep  5 00:59:25 2006
@@ -2045,7 +2045,7 @@
                      [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
 
 // Conditional store
-def MASKMOVDQU : PDI<0xF7, RawFrm, (ops VR128:$src, VR128:$mask),
+def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (ops VR128:$src, VR128:$mask),
                      "maskmovdqu {$mask, $src|$src, $mask}",
                      [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>,
                  Imp<[EDI],[]>;





From evan.cheng at apple.com  Tue Sep  5 03:33:04 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 5 Sep 2006 03:33:04 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp
Message-ID: <200609050833.k858X4Un001939@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.165 -> 1.166
---
Log message:

Fix a few dejagnu failures. e.g. fast-cc-merge-stack-adj.ll

---
Diffs of the changes:  (+2 -2)

 X86RegisterInfo.cpp |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.165 llvm/lib/Target/X86/X86RegisterInfo.cpp:1.166
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.165	Mon Sep  4 21:31:13 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp	Tue Sep  5 03:32:49 2006
@@ -933,12 +933,12 @@
         if ((PI->getOpcode() == X86::ADD32ri || 
              PI->getOpcode() == X86::ADD32ri8) &&
             PI->getOperand(0).getReg() == X86::ESP) {
-          NumBytes += PI->getOperand(1).getImmedValue();
+          NumBytes += PI->getOperand(2).getImmedValue();
           MBB.erase(PI);
         } else if ((PI->getOpcode() == X86::SUB32ri ||
                     PI->getOpcode() == X86::SUB32ri8) &&
                    PI->getOperand(0).getReg() == X86::ESP) {
-          NumBytes -= PI->getOperand(1).getImmedValue();
+          NumBytes -= PI->getOperand(2).getImmedValue();
           MBB.erase(PI);
         } else if (PI->getOpcode() == X86::ADJSTACKPTRri) {
           NumBytes += PI->getOperand(1).getImmedValue();





From lattner at cs.uiuc.edu  Tue Sep  5 12:39:35 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 5 Sep 2006 12:39:35 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Message-ID: <200609051739.k85HdZ9c018596@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

TargetLowering.cpp updated: 1.71 -> 1.72
---
Log message:

Change the default to 0, which means 'default'.


---
Diffs of the changes:  (+1 -1)

 TargetLowering.cpp |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.71 llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.72
--- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.71	Mon Sep  4 02:44:11 2006
+++ llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp	Tue Sep  5 12:39:15 2006
@@ -41,7 +41,7 @@
   Pow2DivIsCheap = false;
   StackPointerRegisterToSaveRestore = 0;
   SchedPreferenceInfo = SchedulingForLatency;
-  JumpBufSize = 200;
+  JumpBufSize = 0;
   JumpBufAlignment = 0;
 }
 





From lattner at cs.uiuc.edu  Tue Sep  5 12:48:21 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 5 Sep 2006 12:48:21 -0500
Subject: [llvm-commits] CVS: llvm/lib/Transforms/Utils/LowerInvoke.cpp
Message-ID: <200609051748.k85HmLXE018810@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/Utils:

LowerInvoke.cpp updated: 1.40 -> 1.41
---
Log message:

Fix Duraid's changes to work when TLI is null.  This fixes the failing 
lowerinvoke regtests.


---
Diffs of the changes:  (+7 -3)

 LowerInvoke.cpp |   10 +++++++---
 1 files changed, 7 insertions(+), 3 deletions(-)


Index: llvm/lib/Transforms/Utils/LowerInvoke.cpp
diff -u llvm/lib/Transforms/Utils/LowerInvoke.cpp:1.40 llvm/lib/Transforms/Utils/LowerInvoke.cpp:1.41
--- llvm/lib/Transforms/Utils/LowerInvoke.cpp:1.40	Mon Sep  4 01:21:35 2006
+++ llvm/lib/Transforms/Utils/LowerInvoke.cpp	Tue Sep  5 12:48:07 2006
@@ -113,7 +113,9 @@
   AbortMessage = 0;
   if (ExpensiveEHSupport) {
     // Insert a type for the linked list of jump buffers.
-    const Type *JmpBufTy = ArrayType::get(VoidPtrTy, TLI->getJumpBufSize());
+    unsigned JBSize = TLI ? TLI->getJumpBufSize() : 0;
+    JBSize = JBSize ? JBSize : 200;
+    const Type *JmpBufTy = ArrayType::get(VoidPtrTy, JBSize);
 
     { // The type is recursive, so use a type holder.
       std::vector<const Type*> Elements;
@@ -130,11 +132,12 @@
 
     // Now that we've done that, insert the jmpbuf list head global, unless it
     // already exists.
-    if (!(JBListHead = M.getGlobalVariable("llvm.sjljeh.jblist", PtrJBList)))
+    if (!(JBListHead = M.getGlobalVariable("llvm.sjljeh.jblist", PtrJBList))) {
       JBListHead = new GlobalVariable(PtrJBList, false,
                                       GlobalValue::LinkOnceLinkage,
                                       Constant::getNullValue(PtrJBList),
                                       "llvm.sjljeh.jblist", &M);
+    }
     SetJmpFn = M.getOrInsertFunction("llvm.setjmp", Type::IntTy,
                                      PointerType::get(JmpBufTy), (Type *)0);
     LongJmpFn = M.getOrInsertFunction("llvm.longjmp", Type::VoidTy,
@@ -452,8 +455,9 @@
     // Create an alloca for the incoming jump buffer ptr and the new jump buffer
     // that needs to be restored on all exits from the function.  This is an
     // alloca because the value needs to be live across invokes.
+    unsigned Align = TLI ? TLI->getJumpBufAlignment() : 0;
     AllocaInst *JmpBuf = 
-      new AllocaInst(JBLinkTy, 0, TLI->getJumpBufAlignment(), "jblink", F.begin()->begin());
+      new AllocaInst(JBLinkTy, 0, Align, "jblink", F.begin()->begin());
     
     std::vector<Value*> Idx;
     Idx.push_back(Constant::getNullValue(Type::IntTy));





From evan.cheng at apple.com  Tue Sep  5 13:56:16 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 5 Sep 2006 13:56:16 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineInstr.h
Message-ID: <200609051856.k85IuGEM019881@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

MachineInstr.h updated: 1.185 -> 1.186
---
Log message:

Initialize IsDef of all non-register MachineOperand to false.


---
Diffs of the changes:  (+7 -0)

 MachineInstr.h |    7 +++++++
 1 files changed, 7 insertions(+)


Index: llvm/include/llvm/CodeGen/MachineInstr.h
diff -u llvm/include/llvm/CodeGen/MachineInstr.h:1.185 llvm/include/llvm/CodeGen/MachineInstr.h:1.186
--- llvm/include/llvm/CodeGen/MachineInstr.h:1.185	Mon Sep  4 21:31:13 2006
+++ llvm/include/llvm/CodeGen/MachineInstr.h	Tue Sep  5 13:56:02 2006
@@ -295,6 +295,7 @@
   void addImmOperand(int64_t Val) {
     MachineOperand &Op = AddNewOperand();
     Op.opType = MachineOperand::MO_Immediate;
+    Op.IsDef = false;
     Op.contents.immedVal = Val;
     Op.offset = 0;
   }
@@ -302,6 +303,7 @@
   void addMachineBasicBlockOperand(MachineBasicBlock *MBB) {
     MachineOperand &Op = AddNewOperand();
     Op.opType = MachineOperand::MO_MachineBasicBlock;
+    Op.IsDef = false;
     Op.contents.MBB = MBB;
     Op.offset = 0;
   }
@@ -311,6 +313,7 @@
   void addFrameIndexOperand(unsigned Idx) {
     MachineOperand &Op = AddNewOperand();
     Op.opType = MachineOperand::MO_FrameIndex;
+    Op.IsDef = false;
     Op.contents.immedVal = Idx;
     Op.offset = 0;
   }
@@ -321,6 +324,7 @@
   void addConstantPoolIndexOperand(unsigned Idx, int Offset) {
     MachineOperand &Op = AddNewOperand();
     Op.opType = MachineOperand::MO_ConstantPoolIndex;
+    Op.IsDef = false;
     Op.contents.immedVal = Idx;
     Op.offset = Offset;
   }
@@ -331,6 +335,7 @@
   void addJumpTableIndexOperand(unsigned Idx) {
     MachineOperand &Op = AddNewOperand();
     Op.opType = MachineOperand::MO_JumpTableIndex;
+    Op.IsDef = false;
     Op.contents.immedVal = Idx;
     Op.offset = 0;
   }
@@ -338,6 +343,7 @@
   void addGlobalAddressOperand(GlobalValue *GV, int Offset) {
     MachineOperand &Op = AddNewOperand();
     Op.opType = MachineOperand::MO_GlobalAddress;
+    Op.IsDef = false;
     Op.contents.GV = GV;
     Op.offset = Offset;
   }
@@ -347,6 +353,7 @@
   void addExternalSymbolOperand(const char *SymName) {
     MachineOperand &Op = AddNewOperand();
     Op.opType = MachineOperand::MO_ExternalSymbol;
+    Op.IsDef = false;
     Op.contents.SymbolName = SymName;
     Op.offset = 0;
   }





From lattner at cs.uiuc.edu  Tue Sep  5 15:03:05 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 5 Sep 2006 15:03:05 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/AsmPrinter.cpp
Message-ID: <200609052003.k85K35lj020911@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen:

AsmPrinter.cpp updated: 1.89 -> 1.90
---
Log message:

Don't call isDef on non-registers


---
Diffs of the changes:  (+2 -1)

 AsmPrinter.cpp |    3 ++-
 1 files changed, 2 insertions(+), 1 deletion(-)


Index: llvm/lib/CodeGen/AsmPrinter.cpp
diff -u llvm/lib/CodeGen/AsmPrinter.cpp:1.89 llvm/lib/CodeGen/AsmPrinter.cpp:1.90
--- llvm/lib/CodeGen/AsmPrinter.cpp:1.89	Sat Aug 12 16:29:52 2006
+++ llvm/lib/CodeGen/AsmPrinter.cpp	Tue Sep  5 15:02:51 2006
@@ -647,7 +647,8 @@
   
   // Count the number of register definitions.
   unsigned NumDefs = 0;
-  for (; MI->getOperand(NumDefs).isDef(); ++NumDefs)
+  for (; MI->getOperand(NumDefs).isReg() && MI->getOperand(NumDefs).isDef();
+       ++NumDefs)
     assert(NumDefs != NumOperands-1 && "No asm string?");
   
   assert(MI->getOperand(NumDefs).isExternalSymbol() && "No asm string?");





From lattner at cs.uiuc.edu  Tue Sep  5 15:19:41 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 5 Sep 2006 15:19:41 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/LiveVariables.cpp
	MachineInstr.cpp
Message-ID: <200609052019.k85KJfAv021217@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen:

LiveVariables.cpp updated: 1.58 -> 1.59
MachineInstr.cpp updated: 1.124 -> 1.125
---
Log message:

Only call isUse/isDef on register operands


---
Diffs of the changes:  (+7 -13)

 LiveVariables.cpp |    4 ++--
 MachineInstr.cpp  |   16 +++++-----------
 2 files changed, 7 insertions(+), 13 deletions(-)


Index: llvm/lib/CodeGen/LiveVariables.cpp
diff -u llvm/lib/CodeGen/LiveVariables.cpp:1.58 llvm/lib/CodeGen/LiveVariables.cpp:1.59
--- llvm/lib/CodeGen/LiveVariables.cpp:1.58	Sat Sep  2 19:05:09 2006
+++ llvm/lib/CodeGen/LiveVariables.cpp	Tue Sep  5 15:19:27 2006
@@ -248,7 +248,7 @@
       // Process all explicit uses...
       for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
         MachineOperand &MO = MI->getOperand(i);
-        if (MO.isUse() && MO.isRegister() && MO.getReg()) {
+        if (MO.isRegister() && MO.isUse() && MO.getReg()) {
           if (MRegisterInfo::isVirtualRegister(MO.getReg())){
             HandleVirtRegUse(getVarInfo(MO.getReg()), MBB, MI);
           } else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
@@ -268,7 +268,7 @@
       // Process all explicit defs...
       for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
         MachineOperand &MO = MI->getOperand(i);
-        if (MO.isDef() && MO.isRegister() && MO.getReg()) {
+        if (MO.isRegister() && MO.isDef() && MO.getReg()) {
           if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
             VarInfo &VRInfo = getVarInfo(MO.getReg());
 


Index: llvm/lib/CodeGen/MachineInstr.cpp
diff -u llvm/lib/CodeGen/MachineInstr.cpp:1.124 llvm/lib/CodeGen/MachineInstr.cpp:1.125
--- llvm/lib/CodeGen/MachineInstr.cpp:1.124	Thu Jun 15 02:22:16 2006
+++ llvm/lib/CodeGen/MachineInstr.cpp	Tue Sep  5 15:19:27 2006
@@ -158,7 +158,7 @@
   unsigned StartOp = 0;
 
    // Specialize printing if op#0 is definition
-  if (getNumOperands() && getOperand(0).isDef() && !getOperand(0).isUse()) {
+  if (getNumOperands() && getOperand(0).isReg() && getOperand(0).isDef()) {
     ::print(getOperand(0), OS, TM);
     OS << " = ";
     ++StartOp;   // Don't print this operand again!
@@ -176,11 +176,8 @@
     OS << " ";
     ::print(mop, OS, TM);
 
-    if (mop.isDef())
-      if (mop.isUse())
-        OS << "<def&use>";
-      else
-        OS << "<def>";
+    if (mop.isReg() && mop.isDef())
+      OS << "<def>";
   }
 
   OS << "\n";
@@ -204,11 +201,8 @@
 
   for (unsigned i = 0, N = MI.getNumOperands(); i < N; i++) {
     os << "\t" << MI.getOperand(i);
-    if (MI.getOperand(i).isDef())
-      if (MI.getOperand(i).isUse())
-        os << "<d&u>";
-      else
-        os << "<d>";
+    if (MI.getOperand(i).isReg() && MI.getOperand(i).isDef())
+      os << "<d>";
   }
 
   return os << "\n";





From evan.cheng at apple.com  Tue Sep  5 15:20:18 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 5 Sep 2006 15:20:18 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachineInstr.h
Message-ID: <200609052020.k85KKIgM021245@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

MachineInstr.h updated: 1.186 -> 1.187
---
Log message:

IsDef can only be accessed / set if operand is a register.


---
Diffs of the changes:  (+16 -11)

 MachineInstr.h |   27 ++++++++++++++++-----------
 1 files changed, 16 insertions(+), 11 deletions(-)


Index: llvm/include/llvm/CodeGen/MachineInstr.h
diff -u llvm/include/llvm/CodeGen/MachineInstr.h:1.186 llvm/include/llvm/CodeGen/MachineInstr.h:1.187
--- llvm/include/llvm/CodeGen/MachineInstr.h:1.186	Tue Sep  5 13:56:02 2006
+++ llvm/include/llvm/CodeGen/MachineInstr.h	Tue Sep  5 15:20:04 2006
@@ -143,10 +143,22 @@
     return contents.SymbolName;
   }
 
-  bool isUse() const { return !IsDef; }
-  bool isDef() const { return IsDef; }
-  void setIsUse() { IsDef = false; }
-  void setIsDef() { IsDef = true; }
+  bool isUse() const { 
+    assert(isRegister() && "Wrong MachineOperand accessor");
+    return !IsDef;
+  }
+  bool isDef() const {
+    assert(isRegister() && "Wrong MachineOperand accessor");
+    return IsDef;
+  }
+  void setIsUse() {
+    assert(isRegister() && "Wrong MachineOperand accessor");
+    IsDef = false;
+  }
+  void setIsDef() {
+    assert(isRegister() && "Wrong MachineOperand accessor");
+    IsDef = true;
+  }
 
   /// getReg - Returns the register number.
   ///
@@ -295,7 +307,6 @@
   void addImmOperand(int64_t Val) {
     MachineOperand &Op = AddNewOperand();
     Op.opType = MachineOperand::MO_Immediate;
-    Op.IsDef = false;
     Op.contents.immedVal = Val;
     Op.offset = 0;
   }
@@ -303,7 +314,6 @@
   void addMachineBasicBlockOperand(MachineBasicBlock *MBB) {
     MachineOperand &Op = AddNewOperand();
     Op.opType = MachineOperand::MO_MachineBasicBlock;
-    Op.IsDef = false;
     Op.contents.MBB = MBB;
     Op.offset = 0;
   }
@@ -313,7 +323,6 @@
   void addFrameIndexOperand(unsigned Idx) {
     MachineOperand &Op = AddNewOperand();
     Op.opType = MachineOperand::MO_FrameIndex;
-    Op.IsDef = false;
     Op.contents.immedVal = Idx;
     Op.offset = 0;
   }
@@ -324,7 +333,6 @@
   void addConstantPoolIndexOperand(unsigned Idx, int Offset) {
     MachineOperand &Op = AddNewOperand();
     Op.opType = MachineOperand::MO_ConstantPoolIndex;
-    Op.IsDef = false;
     Op.contents.immedVal = Idx;
     Op.offset = Offset;
   }
@@ -335,7 +343,6 @@
   void addJumpTableIndexOperand(unsigned Idx) {
     MachineOperand &Op = AddNewOperand();
     Op.opType = MachineOperand::MO_JumpTableIndex;
-    Op.IsDef = false;
     Op.contents.immedVal = Idx;
     Op.offset = 0;
   }
@@ -343,7 +350,6 @@
   void addGlobalAddressOperand(GlobalValue *GV, int Offset) {
     MachineOperand &Op = AddNewOperand();
     Op.opType = MachineOperand::MO_GlobalAddress;
-    Op.IsDef = false;
     Op.contents.GV = GV;
     Op.offset = Offset;
   }
@@ -353,7 +359,6 @@
   void addExternalSymbolOperand(const char *SymName) {
     MachineOperand &Op = AddNewOperand();
     Op.opType = MachineOperand::MO_ExternalSymbol;
-    Op.IsDef = false;
     Op.contents.SymbolName = SymName;
     Op.offset = 0;
   }





From lattner at cs.uiuc.edu  Tue Sep  5 15:27:20 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 5 Sep 2006 15:27:20 -0500
Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/X86/select.ll
Message-ID: <200609052027.k85KRKZ2021407@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CodeGen/X86:

select.ll updated: 1.3 -> 1.4
---
Log message:

make this harder


---
Diffs of the changes:  (+2 -1)

 select.ll |    3 ++-
 1 files changed, 2 insertions(+), 1 deletion(-)


Index: llvm/test/Regression/CodeGen/X86/select.ll
diff -u llvm/test/Regression/CodeGen/X86/select.ll:1.3 llvm/test/Regression/CodeGen/X86/select.ll:1.4
--- llvm/test/Regression/CodeGen/X86/select.ll:1.3	Wed Mar 31 21:47:56 2004
+++ llvm/test/Regression/CodeGen/X86/select.ll	Tue Sep  5 15:27:06 2006
@@ -1,4 +1,5 @@
-; RUN: llvm-as < %s | llc -march=x86
+; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah &&
+; RUN: llvm-as < %s | llc -march=x86 -mcpu=pentium
 
 bool %boolSel(bool %A, bool %B, bool %C) {
 	%X = select bool %A, bool %B, bool %C





From lattner at cs.uiuc.edu  Tue Sep  5 15:27:46 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Tue, 5 Sep 2006 15:27:46 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86FloatingPoint.cpp
Message-ID: <200609052027.k85KRkGL021426@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86FloatingPoint.cpp updated: 1.53 -> 1.54
---
Log message:

Bugfix to work with the two-addr changes that have been made in the tree recently


---
Diffs of the changes:  (+2 -1)

 X86FloatingPoint.cpp |    3 ++-
 1 files changed, 2 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/X86/X86FloatingPoint.cpp
diff -u llvm/lib/Target/X86/X86FloatingPoint.cpp:1.53 llvm/lib/Target/X86/X86FloatingPoint.cpp:1.54
--- llvm/lib/Target/X86/X86FloatingPoint.cpp:1.53	Sun Aug 27 07:54:01 2006
+++ llvm/lib/Target/X86/X86FloatingPoint.cpp	Tue Sep  5 15:27:32 2006
@@ -752,7 +752,7 @@
   MachineInstr *MI = I;
 
   unsigned Op0 = getFPReg(MI->getOperand(0));
-  unsigned Op1 = getFPReg(MI->getOperand(1));
+  unsigned Op1 = getFPReg(MI->getOperand(2));
 
   // The first operand *must* be on the top of the stack.
   moveToTop(Op0, I);
@@ -760,6 +760,7 @@
   // Change the second operand to the stack register that the operand is in.
   // Change from the pseudo instruction to the concrete instruction.
   MI->RemoveOperand(0);
+  MI->RemoveOperand(1);
   MI->getOperand(0).setReg(getSTReg(Op1));
   MI->setOpcode(getConcreteOpcode(MI->getOpcode()));
   





From evan.cheng at apple.com  Tue Sep  5 15:32:20 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 5 Sep 2006 15:32:20 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/RegAllocLocal.cpp
Message-ID: <200609052032.k85KWKBl021505@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen:

RegAllocLocal.cpp updated: 1.88 -> 1.89
---
Log message:

Only call isUse/isDef on register operands


---
Diffs of the changes:  (+3 -3)

 RegAllocLocal.cpp |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)


Index: llvm/lib/CodeGen/RegAllocLocal.cpp
diff -u llvm/lib/CodeGen/RegAllocLocal.cpp:1.88 llvm/lib/CodeGen/RegAllocLocal.cpp:1.89
--- llvm/lib/CodeGen/RegAllocLocal.cpp:1.88	Sun Sep  3 02:15:37 2006
+++ llvm/lib/CodeGen/RegAllocLocal.cpp	Tue Sep  5 15:32:06 2006
@@ -552,7 +552,7 @@
     for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
       MachineOperand& MO = MI->getOperand(i);
       // here we are looking for only used operands (never def&use)
-      if (!MO.isDef() && MO.isRegister() && MO.getReg() &&
+      if (MO.isRegister() && !MO.isDef() && MO.getReg() &&
           MRegisterInfo::isVirtualRegister(MO.getReg()))
         MI = reloadVirtReg(MBB, MI, i);
     }
@@ -584,7 +584,7 @@
     // are defined, and marking explicit destinations in the PhysRegsUsed map.
     for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
       MachineOperand& MO = MI->getOperand(i);
-      if (MO.isDef() && MO.isRegister() && MO.getReg() &&
+      if (MO.isRegister() && MO.isDef() && MO.getReg() &&
           MRegisterInfo::isPhysicalRegister(MO.getReg())) {
         unsigned Reg = MO.getReg();
         PhysRegsEverUsed[Reg] = true;
@@ -626,7 +626,7 @@
     //
     for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
       MachineOperand& MO = MI->getOperand(i);
-      if (MO.isDef() && MO.isRegister() && MO.getReg() &&
+      if (MO.isRegister() && MO.isDef() && MO.getReg() &&
           MRegisterInfo::isVirtualRegister(MO.getReg())) {
         unsigned DestVirtReg = MO.getReg();
         unsigned DestPhysReg;





From dpatel at apple.com  Tue Sep  5 19:28:38 2006
From: dpatel at apple.com (Devang Patel)
Date: Tue, 5 Sep 2006 19:28:38 -0500
Subject: [llvm-commits] CVS: llvm/tools/lto/lto.cpp
Message-ID: <200609060028.k860ScB4025099@zion.cs.uiuc.edu>



Changes in directory llvm/tools/lto:

lto.cpp updated: 1.8 -> 1.9
---
Log message:

Extract target triplet from optimized module.
Untabify.


---
Diffs of the changes:  (+4 -1)

 lto.cpp |    5 ++++-
 1 files changed, 4 insertions(+), 1 deletion(-)


Index: llvm/tools/lto/lto.cpp
diff -u llvm/tools/lto/lto.cpp:1.8 llvm/tools/lto/lto.cpp:1.9
--- llvm/tools/lto/lto.cpp:1.8	Wed Aug 23 11:59:25 2006
+++ llvm/tools/lto/lto.cpp	Tue Sep  5 19:28:22 2006
@@ -266,7 +266,8 @@
 /// Return appropriate LTOStatus.
 enum LTOStatus
 LinkTimeOptimizer::optimizeModules(const std::string &OutputFilename,
-                                   std::vector<const char *> &exportList)
+                                   std::vector<const char *> &exportList,
+                                   std::string &targetTriple)
 {
   if (modules.empty())
     return LTO_NO_WORK;
@@ -316,6 +317,8 @@
     return status;
   }
 
+  targetTriple = bigOne->getTargetTriple();
+
   // Run GCC to assemble and link the program into native code.
   //
   // Note:





From dpatel at apple.com  Tue Sep  5 19:28:38 2006
From: dpatel at apple.com (Devang Patel)
Date: Tue, 5 Sep 2006 19:28:38 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/LinkTimeOptimizer.h
Message-ID: <200609060028.k860ScRP025104@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm:

LinkTimeOptimizer.h updated: 1.4 -> 1.5
---
Log message:

Extract target triplet from optimized module.
Untabify.


---
Diffs of the changes:  (+7 -6)

 LinkTimeOptimizer.h |   13 +++++++------
 1 files changed, 7 insertions(+), 6 deletions(-)


Index: llvm/include/llvm/LinkTimeOptimizer.h
diff -u llvm/include/llvm/LinkTimeOptimizer.h:1.4 llvm/include/llvm/LinkTimeOptimizer.h:1.5
--- llvm/include/llvm/LinkTimeOptimizer.h:1.4	Mon Aug 14 18:27:36 2006
+++ llvm/include/llvm/LinkTimeOptimizer.h	Tue Sep  5 19:28:22 2006
@@ -56,8 +56,8 @@
     void mayBeNotUsed();
 
     LLVMSymbol (enum LTOLinkageTypes lt, GlobalValue *g, const std::string &n, 
-		const std::string &m) : linkage(lt), gv(g), name(n), 
-					mangledName(m) {}
+                const std::string &m) : linkage(lt), gv(g), name(n), 
+                                        mangledName(m) {}
 
     const char *getName() { return name.c_str(); }
     const char *getMangledName() { return mangledName.c_str(); }
@@ -82,13 +82,14 @@
 
   public:
     typedef hash_map<const char*, LLVMSymbol*, hash<const char*>, 
-		     string_compare> NameToSymbolMap;
+                     string_compare> NameToSymbolMap;
 
     enum LTOStatus readLLVMObjectFile(const std::string &InputFilename,
-				      NameToSymbolMap &symbols,
-				      std::set<std::string> &references);
+                                      NameToSymbolMap &symbols,
+                                      std::set<std::string> &references);
     enum LTOStatus optimizeModules(const std::string &OutputFilename,
-				   std::vector<const char*> &exportList);
+                                   std::vector<const char*> &exportList,
+                                   std::string &targetTriple);
 
   private:
     std::vector<Module *> modules;





From dpatel at apple.com  Tue Sep  5 19:46:06 2006
From: dpatel at apple.com (Devang Patel)
Date: Tue, 5 Sep 2006 19:46:06 -0500
Subject: [llvm-commits] CVS: llvm/tools/lto/lto.cpp
Message-ID: <200609060046.k860k6kV025367@zion.cs.uiuc.edu>



Changes in directory llvm/tools/lto:

lto.cpp updated: 1.9 -> 1.10
---
Log message:

Instead of demangling symbol name by hand, use original name, which was
used to mangle symbol name, directly.


---
Diffs of the changes:  (+4 -2)

 lto.cpp |    6 ++++--
 1 files changed, 4 insertions(+), 2 deletions(-)


Index: llvm/tools/lto/lto.cpp
diff -u llvm/tools/lto/lto.cpp:1.9 llvm/tools/lto/lto.cpp:1.10
--- llvm/tools/lto/lto.cpp:1.9	Tue Sep  5 19:28:22 2006
+++ llvm/tools/lto/lto.cpp	Tue Sep  5 19:45:52 2006
@@ -147,6 +147,7 @@
       LLVMSymbol *newSymbol = new LLVMSymbol(lt, v, v->getName(), 
                                              mangler.getValueName(v));
       symbols[newSymbol->getMangledName()] = newSymbol;
+      allSymbols[newSymbol->getMangledName()] = newSymbol;
 
       for (unsigned count = 0, total = v->getNumOperands(); 
            count != total; ++count)
@@ -291,8 +292,9 @@
   // seen by linker.
   for (unsigned i = 0, e = exportList.size(); i != e; ++i) {
     const char *name = exportList[i];
-    if (strlen(name) > 2 && name[0] == '_')
-      exportList[i] = &name[1];
+    NameToSymbolMap::iterator itr = allSymbols.find(name);
+    if (itr != allSymbols.end())
+      exportList[i] = allSymbols[name]->getName();
   }
 
   sys::Path tmpAsmFilePath("/tmp/");





From rafael.espindola at gmail.com  Wed Sep  6 13:03:26 2006
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Wed, 6 Sep 2006 13:03:26 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.td
Message-ID: <200609061803.k86I3Q2X031074@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/ARM:

ARMInstrInfo.td updated: 1.21 -> 1.22
---
Log message:

add the orr instruction


---
Diffs of the changes:  (+4 -0)

 ARMInstrInfo.td |    4 ++++
 1 files changed, 4 insertions(+)


Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.21 llvm/lib/Target/ARM/ARMInstrInfo.td:1.22
--- llvm/lib/Target/ARM/ARMInstrInfo.td:1.21	Thu Aug 24 12:19:08 2006
+++ llvm/lib/Target/ARM/ARMInstrInfo.td	Wed Sep  6 13:03:12 2006
@@ -113,6 +113,10 @@
 		       "and $dst, $a, $b",
 		       [(set IntRegs:$dst, (and IntRegs:$a, IntRegs:$b))]>;
 
+def orr_rr    : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
+		       "orr $dst, $a, $b",
+		       [(set IntRegs:$dst, (or IntRegs:$a, IntRegs:$b))]>;
+
 let isTwoAddress = 1 in {
   def movcond : InstARM<(ops IntRegs:$dst, IntRegs:$false, IntRegs:$true, CCOp:$cc),
 	                 "mov$cc $dst, $true",





From jlaskey at apple.com  Wed Sep  6 13:34:58 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Wed, 6 Sep 2006 13:34:58 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/ARM/ARMAsmPrinter.cpp
Message-ID: <200609061834.k86IYwPh031743@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/ARM:

ARMAsmPrinter.cpp updated: 1.14 -> 1.15
---
Log message:

Separate target specific asm properties from the asm printers.


---
Diffs of the changes:  (+12 -4)

 ARMAsmPrinter.cpp |   16 ++++++++++++----
 1 files changed, 12 insertions(+), 4 deletions(-)


Index: llvm/lib/Target/ARM/ARMAsmPrinter.cpp
diff -u llvm/lib/Target/ARM/ARMAsmPrinter.cpp:1.14 llvm/lib/Target/ARM/ARMAsmPrinter.cpp:1.15
--- llvm/lib/Target/ARM/ARMAsmPrinter.cpp:1.14	Fri Aug 25 12:55:16 2006
+++ llvm/lib/Target/ARM/ARMAsmPrinter.cpp	Wed Sep  6 13:34:40 2006
@@ -23,6 +23,7 @@
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineConstantPool.h"
 #include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/Target/TargetAsmInfo.h"
 #include "llvm/Target/TargetData.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Support/Mangler.h"
@@ -37,8 +38,8 @@
 namespace {
   Statistic<> EmittedInsts("asm-printer", "Number of machine instrs printed");
 
-  struct ARMAsmPrinter : public AsmPrinter {
-    ARMAsmPrinter(std::ostream &O, TargetMachine &TM) : AsmPrinter(O, TM) {
+  struct VISIBILITY_HIDDEN ARMTargetAsmInfo : public TargetAsmInfo {
+    ARMTargetAsmInfo() {
       Data16bitsDirective = "\t.half\t";
       Data32bitsDirective = "\t.word\t";
       Data64bitsDirective = 0;
@@ -47,6 +48,12 @@
       ConstantPoolSection = "\t.text\n";
       AlignmentIsInBytes = false;
     }
+  };
+
+  struct VISIBILITY_HIDDEN ARMAsmPrinter : public AsmPrinter {
+    ARMAsmPrinter(std::ostream &O, TargetMachine &TM, TargetAsmInfo *T)
+      : AsmPrinter(O, TM, T) {
+    }
 
     /// We name each basic block in a Function with a unique number, so
     /// that we can consistently refer to them later. This is cleared
@@ -106,7 +113,8 @@
 ///
 FunctionPass *llvm::createARMCodePrinterPass(std::ostream &o,
                                                TargetMachine &tm) {
-  return new ARMAsmPrinter(o, tm);
+  ARMTargetAsmInfo *TAI = new ARMTargetAsmInfo();
+  return new ARMAsmPrinter(o, tm, TAI);
 }
 
 /// runOnMachineFunction - This uses the printMachineInstruction()
@@ -187,7 +195,7 @@
     abort();
     break;
   case MachineOperand::MO_ConstantPoolIndex:
-    O << PrivateGlobalPrefix << "CPI" << getFunctionNumber()
+    O << TAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
       << '_' << MO.getConstantPoolIndex();
     break;
   default:





From jlaskey at apple.com  Wed Sep  6 13:35:04 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Wed, 6 Sep 2006 13:35:04 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/AsmPrinter.h
	DwarfWriter.h
Message-ID: <200609061835.k86IZ4Y9031751@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

AsmPrinter.h updated: 1.45 -> 1.46
DwarfWriter.h updated: 1.38 -> 1.39
---
Log message:

Separate target specific asm properties from the asm printers.


---
Diffs of the changes:  (+25 -237)

 AsmPrinter.h  |  168 ++++------------------------------------------------------
 DwarfWriter.h |   94 ++++----------------------------
 2 files changed, 25 insertions(+), 237 deletions(-)


Index: llvm/include/llvm/CodeGen/AsmPrinter.h
diff -u llvm/include/llvm/CodeGen/AsmPrinter.h:1.45 llvm/include/llvm/CodeGen/AsmPrinter.h:1.46
--- llvm/include/llvm/CodeGen/AsmPrinter.h:1.45	Sat Aug 12 16:29:52 2006
+++ llvm/include/llvm/CodeGen/AsmPrinter.h	Wed Sep  6 13:34:40 2006
@@ -7,9 +7,9 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This class is intended to be used as a base class for target-specific
-// asmwriters.  This class primarily takes care of printing global constants,
-// which are printed in a very similar way across all targets.
+// This file contains a class to be used as the base class for target specific
+// asm writers.  This class primarily handles common functionality used by
+// all asm writers.
 //
 //===----------------------------------------------------------------------===//
 
@@ -22,10 +22,14 @@
 namespace llvm {
   class Constant;
   class ConstantArray;
-  class Mangler;
   class GlobalVariable;
   class MachineConstantPoolEntry;
+  class Mangler;
+  class TargetAsmInfo;
+  
 
+  /// AsmPrinter - This class is intended to be used as a driving class for all
+  /// asm writers.
   class AsmPrinter : public MachineFunctionPass {
     /// FunctionNumber - This provides a unique ID for each function emitted in
     /// this translation unit.  It is autoincremented by SetupMachineFunction,
@@ -42,6 +46,10 @@
     /// Target machine description.
     ///
     TargetMachine &TM;
+    
+    /// Target Asm Printer information.
+    ///
+    TargetAsmInfo *TAI;
 
     /// Name-mangler for global names.
     ///
@@ -51,163 +59,13 @@
     /// beginning of each call to runOnMachineFunction().
     ///
     std::string CurrentFnName;
-
-    //===------------------------------------------------------------------===//
-    // Properties to be set by the derived class ctor, used to configure the
-    // asmwriter.
-
-    /// CommentString - This indicates the comment character used by the
-    /// assembler.
-    const char *CommentString;     // Defaults to "#"
-
-    /// GlobalPrefix - If this is set to a non-empty string, it is prepended
-    /// onto all global symbols.  This is often used for "_" or ".".
-    const char *GlobalPrefix;    // Defaults to ""
-
-    /// PrivateGlobalPrefix - This prefix is used for globals like constant
-    /// pool entries that are completely private to the .o file and should not
-    /// have names in the .o file.  This is often "." or "L".
-    const char *PrivateGlobalPrefix;   // Defaults to "."
-    
-    /// GlobalVarAddrPrefix/Suffix - If these are nonempty, these strings
-    /// will enclose any GlobalVariable (that isn't a function)
-    ///
-    const char *GlobalVarAddrPrefix;       // Defaults to ""
-    const char *GlobalVarAddrSuffix;       // Defaults to ""
-
-    /// FunctionAddrPrefix/Suffix - If these are nonempty, these strings
-    /// will enclose any GlobalVariable that points to a function.
-    /// For example, this is used by the IA64 backend to materialize
-    /// function descriptors, by decorating the ".data8" object with the
-    /// \literal @fptr( ) \endliteral
-    /// link-relocation operator.
-    ///
-    const char *FunctionAddrPrefix;       // Defaults to ""
-    const char *FunctionAddrSuffix;       // Defaults to ""
-
-    /// InlineAsmStart/End - If these are nonempty, they contain a directive to
-    /// emit before and after an inline assmebly statement.
-    const char *InlineAsmStart;           // Defaults to "#APP\n"
-    const char *InlineAsmEnd;             // Defaults to "#NO_APP\n"
-    
-    //===--- Data Emission Directives -------------------------------------===//
-
-    /// ZeroDirective - this should be set to the directive used to get some
-    /// number of zero bytes emitted to the current section.  Common cases are
-    /// "\t.zero\t" and "\t.space\t".  If this is set to null, the
-    /// Data*bitsDirective's will be used to emit zero bytes.
-    const char *ZeroDirective;   // Defaults to "\t.zero\t"
-    const char *ZeroDirectiveSuffix;  // Defaults to ""
-
-    /// AsciiDirective - This directive allows emission of an ascii string with
-    /// the standard C escape characters embedded into it.
-    const char *AsciiDirective;  // Defaults to "\t.ascii\t"
-    
-    /// AscizDirective - If not null, this allows for special handling of
-    /// zero terminated strings on this target.  This is commonly supported as
-    /// ".asciz".  If a target doesn't support this, it can be set to null.
-    const char *AscizDirective;  // Defaults to "\t.asciz\t"
-
-    /// DataDirectives - These directives are used to output some unit of
-    /// integer data to the current section.  If a data directive is set to
-    /// null, smaller data directives will be used to emit the large sizes.
-    const char *Data8bitsDirective;   // Defaults to "\t.byte\t"
-    const char *Data16bitsDirective;  // Defaults to "\t.short\t"
-    const char *Data32bitsDirective;  // Defaults to "\t.long\t"
-    const char *Data64bitsDirective;  // Defaults to "\t.quad\t"
-
-    //===--- Alignment Information ----------------------------------------===//
-
-    /// AlignDirective - The directive used to emit round up to an alignment
-    /// boundary.
-    ///
-    const char *AlignDirective;       // Defaults to "\t.align\t"
-
-    /// AlignmentIsInBytes - If this is true (the default) then the asmprinter
-    /// emits ".align N" directives, where N is the number of bytes to align to.
-    /// Otherwise, it emits ".align log2(N)", e.g. 3 to align to an 8 byte
-    /// boundary.
-    bool AlignmentIsInBytes;          // Defaults to true
-    
-    //===--- Section Switching Directives ---------------------------------===//
     
     /// CurrentSection - The current section we are emitting to.  This is
     /// controlled and used by the SwitchSection method.
     std::string CurrentSection;
-    
-    /// SwitchToSectionDirective - This is the directive used when we want to
-    /// emit a global to an arbitrary section.  The section name is emited after
-    /// this.
-    const char *SwitchToSectionDirective;  // Defaults to "\t.section\t"
-    
-    /// TextSectionStartSuffix - This is printed after each start of section
-    /// directive for text sections.
-    const char *TextSectionStartSuffix;        // Defaults to "".
-
-    /// DataSectionStartSuffix - This is printed after each start of section
-    /// directive for data sections.
-    const char *DataSectionStartSuffix;        // Defaults to "".
-    
-    /// SectionEndDirectiveSuffix - If non-null, the asm printer will close each
-    /// section with the section name and this suffix printed.
-    const char *SectionEndDirectiveSuffix; // Defaults to null.
-    
-    /// ConstantPoolSection - This is the section that we SwitchToSection right
-    /// before emitting the constant pool for a function.
-    const char *ConstantPoolSection;     // Defaults to "\t.section .rodata\n"
-
-    /// JumpTableDataSection - This is the section that we SwitchToSection right
-    /// before emitting the jump tables for a function when the relocation model
-    /// is not PIC.
-    const char *JumpTableDataSection;     // Defaults to "\t.section .rodata\n"
-    
-    /// JumpTableTextSection - This is the section that we SwitchToSection right
-    /// before emitting the jump tables for a function when the relocation model
-    /// is PIC.
-    const char *JumpTableTextSection;     // Defaults to "\t.text\n"
-    
-    /// StaticCtorsSection - This is the directive that is emitted to switch to
-    /// a section to emit the static constructor list.
-    /// Defaults to "\t.section .ctors,\"aw\", at progbits".
-    const char *StaticCtorsSection;
-
-    /// StaticDtorsSection - This is the directive that is emitted to switch to
-    /// a section to emit the static destructor list.
-    /// Defaults to "\t.section .dtors,\"aw\", at progbits".
-    const char *StaticDtorsSection;
-
-    /// FourByteConstantSection, EightByteConstantSection,
-    /// SixteenByteConstantSection - These are special sections where we place
-    /// 4-, 8-, and 16- byte constant literals.
-    const char *FourByteConstantSection;
-    const char *EightByteConstantSection;
-    const char *SixteenByteConstantSection;
-    
-    //===--- Global Variable Emission Directives --------------------------===//
-    
-    /// SetDirective - This is the name of a directive that can be used to tell
-    /// the assembler to set the value of a variable to some expression.
-    const char *SetDirective;            // Defaults to null.
-    
-    /// LCOMMDirective - This is the name of a directive (if supported) that can
-    /// be used to efficiently declare a local (internal) block of zero
-    /// initialized data in the .bss/.data section.  The syntax expected is:
-    /// \literal <LCOMMDirective> SYMBOLNAME LENGTHINBYTES, ALIGNMENT
-    /// \endliteral
-    const char *LCOMMDirective;          // Defaults to null.
-    
-    const char *COMMDirective;           // Defaults to "\t.comm\t".
-
-    /// COMMDirectiveTakesAlignment - True if COMMDirective take a third
-    /// argument that specifies the alignment of the declaration.
-    bool COMMDirectiveTakesAlignment;    // Defaults to true.
-    
-    /// HasDotTypeDotSizeDirective - True if the target has .type and .size
-    /// directives, this is true for most ELF targets.
-    bool HasDotTypeDotSizeDirective;     // Defaults to true.
   
   protected:
-    AsmPrinter(std::ostream &o, TargetMachine &TM);
+    AsmPrinter(std::ostream &o, TargetMachine &TM, TargetAsmInfo *T);
     
   public:
     /// SwitchToTextSection - Switch to the specified section of the executable


Index: llvm/include/llvm/CodeGen/DwarfWriter.h
diff -u llvm/include/llvm/CodeGen/DwarfWriter.h:1.38 llvm/include/llvm/CodeGen/DwarfWriter.h:1.39
--- llvm/include/llvm/CodeGen/DwarfWriter.h:1.38	Fri Jun 23 07:51:53 2006
+++ llvm/include/llvm/CodeGen/DwarfWriter.h	Wed Sep  6 13:34:40 2006
@@ -48,6 +48,7 @@
 class MRegisterInfo;
 class SubprogramDesc;
 class SourceLineInfo;
+class TargetAsmInfo;
 class TargetData;
 class Type;
 class TypeDesc;
@@ -70,7 +71,8 @@
 // DwarfWriter - Emits Dwarf debug and exception handling directives.
 //
 class DwarfWriter {
-protected:
+
+private:
 
   //===--------------------------------------------------------------------===//
   // Core attributes used by the Dwarf  writer.
@@ -85,6 +87,9 @@
   ///
   AsmPrinter *Asm;
   
+  /// TAI - Target Asm Printer.
+  TargetAsmInfo *TAI;
+  
   /// TD - Target data.
   const TargetData *TD;
   
@@ -147,93 +152,14 @@
   /// SectionSourceLines - Tracks line numbers per text section.
   ///
   std::vector<std::vector<SourceLineInfo *> > SectionSourceLines;
-  
-  //===--------------------------------------------------------------------===//
-  // Properties to be set by the derived class ctor, used to configure the
-  // Dwarf writer.
-  //
-  
-  /// AddressSize - Size of addresses used in file.
-  ///
-  unsigned AddressSize;
 
-  /// hasLEB128 - True if target asm supports leb128 directives.
-  ///
-  bool hasLEB128; /// Defaults to false.
-  
-  /// hasDotLoc - True if target asm supports .loc directives.
-  ///
-  bool hasDotLoc; /// Defaults to false.
-  
-  /// hasDotFile - True if target asm supports .file directives.
-  ///
-  bool hasDotFile; /// Defaults to false.
-  
-  /// needsSet - True if target asm can't compute addresses on data
-  /// directives.
-  bool needsSet; /// Defaults to false.
-  
-  /// DwarfAbbrevSection - Section directive for Dwarf abbrev.
-  ///
-  const char *DwarfAbbrevSection; /// Defaults to ".debug_abbrev".
-
-  /// DwarfInfoSection - Section directive for Dwarf info.
-  ///
-  const char *DwarfInfoSection; /// Defaults to ".debug_info".
 
-  /// DwarfLineSection - Section directive for Dwarf info.
-  ///
-  const char *DwarfLineSection; /// Defaults to ".debug_line".
-  
-  /// DwarfFrameSection - Section directive for Dwarf info.
-  ///
-  const char *DwarfFrameSection; /// Defaults to ".debug_frame".
-  
-  /// DwarfPubNamesSection - Section directive for Dwarf info.
-  ///
-  const char *DwarfPubNamesSection; /// Defaults to ".debug_pubnames".
-  
-  /// DwarfPubTypesSection - Section directive for Dwarf info.
-  ///
-  const char *DwarfPubTypesSection; /// Defaults to ".debug_pubtypes".
-  
-  /// DwarfStrSection - Section directive for Dwarf info.
-  ///
-  const char *DwarfStrSection; /// Defaults to ".debug_str".
-
-  /// DwarfLocSection - Section directive for Dwarf info.
-  ///
-  const char *DwarfLocSection; /// Defaults to ".debug_loc".
-
-  /// DwarfARangesSection - Section directive for Dwarf info.
-  ///
-  const char *DwarfARangesSection; /// Defaults to ".debug_aranges".
-
-  /// DwarfRangesSection - Section directive for Dwarf info.
-  ///
-  const char *DwarfRangesSection; /// Defaults to ".debug_ranges".
-
-  /// DwarfMacInfoSection - Section directive for Dwarf info.
-  ///
-  const char *DwarfMacInfoSection; /// Defaults to ".debug_macinfo".
-
-  /// TextSection - Section directive for standard text.
-  ///
-  const char *TextSection; /// Defaults to ".text".
-  
-  /// DataSection - Section directive for standard data.
-  ///
-  const char *DataSection; /// Defaults to ".data".
+public:
 
   //===--------------------------------------------------------------------===//
   // Emission and print routines
   //
 
-public:
-  /// getAddressSize - Return the size of a target address in bytes.
-  ///
-  unsigned getAddressSize() const { return AddressSize; }
-
   /// PrintHex - Print a value as a hexidecimal value.
   ///
   void PrintHex(int Value) const;
@@ -461,9 +387,13 @@
 
 public:
   
-  DwarfWriter(std::ostream &OS, AsmPrinter *A);
+  DwarfWriter(std::ostream &OS, AsmPrinter *A, TargetAsmInfo *T);
   virtual ~DwarfWriter();
   
+  // Accessors.
+  //
+  TargetAsmInfo *getTargetAsmInfo() const { return TAI; }
+  
   /// SetDebugInfo - Set DebugInfo when it's known that pass manager has
   /// created it.  Set by the target AsmPrinter.
   void SetDebugInfo(MachineDebugInfo *DI);





From jlaskey at apple.com  Wed Sep  6 13:35:06 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Wed, 6 Sep 2006 13:35:06 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcAsmPrinter.cpp
Message-ID: <200609061835.k86IZ6a9031797@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Sparc:

SparcAsmPrinter.cpp updated: 1.66 -> 1.67
---
Log message:

Separate target specific asm properties from the asm printers.


---
Diffs of the changes:  (+12 -4)

 SparcAsmPrinter.cpp |   16 ++++++++++++----
 1 files changed, 12 insertions(+), 4 deletions(-)


Index: llvm/lib/Target/Sparc/SparcAsmPrinter.cpp
diff -u llvm/lib/Target/Sparc/SparcAsmPrinter.cpp:1.66 llvm/lib/Target/Sparc/SparcAsmPrinter.cpp:1.67
--- llvm/lib/Target/Sparc/SparcAsmPrinter.cpp:1.66	Fri May 12 01:33:48 2006
+++ llvm/lib/Target/Sparc/SparcAsmPrinter.cpp	Wed Sep  6 13:34:40 2006
@@ -22,6 +22,7 @@
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineConstantPool.h"
 #include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/Target/TargetAsmInfo.h"
 #include "llvm/Target/TargetData.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Support/Mangler.h"
@@ -36,8 +37,8 @@
 namespace {
   Statistic<> EmittedInsts("asm-printer", "Number of machine instrs printed");
 
-  struct SparcAsmPrinter : public AsmPrinter {
-    SparcAsmPrinter(std::ostream &O, TargetMachine &TM) : AsmPrinter(O, TM) {
+  struct VISIBILITY_HIDDEN SparcTargetAsmInfo : public TargetAsmInfo {
+    SparcTargetAsmInfo() {
       Data16bitsDirective = "\t.half\t";
       Data32bitsDirective = "\t.word\t";
       Data64bitsDirective = 0;  // .xword is only supported by V9.
@@ -45,6 +46,12 @@
       CommentString = "!";
       ConstantPoolSection = "\t.section \".rodata\",#alloc\n";
     }
+  };
+
+  struct VISIBILITY_HIDDEN SparcAsmPrinter : public AsmPrinter {
+    SparcAsmPrinter(std::ostream &O, TargetMachine &TM, TargetAsmInfo *T)
+      : AsmPrinter(O, TM, T) {
+    }
 
     /// We name each basic block in a Function with a unique number, so
     /// that we can consistently refer to them later. This is cleared
@@ -78,7 +85,8 @@
 ///
 FunctionPass *llvm::createSparcCodePrinterPass(std::ostream &o,
                                                TargetMachine &tm) {
-  return new SparcAsmPrinter(o, tm);
+  SparcTargetAsmInfo *TAI = new SparcTargetAsmInfo();
+  return new SparcAsmPrinter(o, tm, TAI);
 }
 
 /// runOnMachineFunction - This uses the printMachineInstruction()
@@ -167,7 +175,7 @@
     O << MO.getSymbolName();
     break;
   case MachineOperand::MO_ConstantPoolIndex:
-    O << PrivateGlobalPrefix << "CPI" << getFunctionNumber() << "_"
+    O << TAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber() << "_"
       << MO.getConstantPoolIndex();
     break;
   default:





From jlaskey at apple.com  Wed Sep  6 13:35:04 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Wed, 6 Sep 2006 13:35:04 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC.h PPCAsmPrinter.cpp
	PPCTargetMachine.cpp
Message-ID: <200609061835.k86IZ4RC031760@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPC.h updated: 1.32 -> 1.33
PPCAsmPrinter.cpp updated: 1.192 -> 1.193
PPCTargetMachine.cpp updated: 1.103 -> 1.104
---
Log message:

Separate target specific asm properties from the asm printers.


---
Diffs of the changes:  (+43 -47)

 PPC.h                |    3 +
 PPCAsmPrinter.cpp    |   85 ++++++++++++++++++++++++---------------------------
 PPCTargetMachine.cpp |    2 -
 3 files changed, 43 insertions(+), 47 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC.h
diff -u llvm/lib/Target/PowerPC/PPC.h:1.32 llvm/lib/Target/PowerPC/PPC.h:1.33
--- llvm/lib/Target/PowerPC/PPC.h:1.32	Sun Sep  3 23:14:57 2006
+++ llvm/lib/Target/PowerPC/PPC.h	Wed Sep  6 13:34:40 2006
@@ -26,7 +26,8 @@
 
 FunctionPass *createPPCBranchSelectionPass();
 FunctionPass *createPPCISelDag(PPCTargetMachine &TM);
-FunctionPass *createDarwinAsmPrinter(std::ostream &OS, PPCTargetMachine &TM);
+FunctionPass *createDarwinCodePrinterPass(std::ostream &OS,
+                                          PPCTargetMachine &TM);
 FunctionPass *createPPCCodeEmitterPass(PPCTargetMachine &TM,
                                        MachineCodeEmitter &MCE);
 void addPPCMachOObjectWriterPass(FunctionPassManager &FPM, std::ostream &o, 


Index: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
diff -u llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.192 llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.193
--- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.192	Sun Aug 27 07:54:01 2006
+++ llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp	Wed Sep  6 13:34:40 2006
@@ -34,6 +34,7 @@
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/Compiler.h"
+#include "llvm/Target/TargetAsmInfo.h"
 #include "llvm/Target/MRegisterInfo.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetOptions.h"
@@ -46,12 +47,11 @@
 namespace {
   Statistic<> EmittedInsts("asm-printer", "Number of machine instrs printed");
 
-  class VISIBILITY_HIDDEN PPCAsmPrinter : public AsmPrinter {
-  public:
+  struct VISIBILITY_HIDDEN PPCAsmPrinter : public AsmPrinter {
     std::set<std::string> FnStubs, GVStubs;
     
-    PPCAsmPrinter(std::ostream &O, TargetMachine &TM)
-      : AsmPrinter(O, TM) {}
+    PPCAsmPrinter(std::ostream &O, TargetMachine &TM, TargetAsmInfo *T)
+      : AsmPrinter(O, TM, T) {}
 
     virtual const char *getPassName() const {
       return "PowerPC Assembly Printer";
@@ -151,7 +151,7 @@
           }
         }
         if (MO.getType() == MachineOperand::MO_ExternalSymbol) {
-          std::string Name(GlobalPrefix); Name += MO.getSymbolName();
+          std::string Name(TAI->getGlobalPrefix()); Name += MO.getSymbolName();
           FnStubs.insert(Name);
           O << "L" << Name << "$stub";
           return;
@@ -239,14 +239,28 @@
     
   };
 
-  /// DarwinDwarfWriter - Dwarf debug info writer customized for Darwin/Mac OS X
-  ///
-  struct VISIBILITY_HIDDEN DarwinDwarfWriter : public DwarfWriter {
-    // Ctor.
-    DarwinDwarfWriter(std::ostream &o, AsmPrinter *ap)
-    : DwarfWriter(o, ap)
-    {
-      needsSet = true;
+  struct VISIBILITY_HIDDEN DarwinTargetAsmInfo : public TargetAsmInfo {
+    DarwinTargetAsmInfo(PPCTargetMachine &TM) {
+      bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
+
+      CommentString = ";";
+      GlobalPrefix = "_";
+      PrivateGlobalPrefix = "L";
+      ZeroDirective = "\t.space\t";
+      SetDirective = "\t.set";
+      Data64bitsDirective = isPPC64 ? ".quad\t" : 0;  
+      AlignmentIsInBytes = false;
+      ConstantPoolSection = "\t.const\t";
+      JumpTableDataSection = ".const";
+      JumpTableTextSection = "\t.text";
+      LCOMMDirective = "\t.lcomm\t";
+      StaticCtorsSection = ".mod_init_func";
+      StaticDtorsSection = ".mod_term_func";
+      InlineAsmStart = "# InlineAsm Start";
+      InlineAsmEnd = "# InlineAsm End";
+      
+      NeedsSet = true;
+      AddressSize = isPPC64 ? 8 : 4;
       DwarfAbbrevSection = ".section __DWARF,__debug_abbrev";
       DwarfInfoSection = ".section __DWARF,__debug_info";
       DwarfLineSection = ".section __DWARF,__debug_line";
@@ -258,8 +272,6 @@
       DwarfARangesSection = ".section __DWARF,__debug_aranges";
       DwarfRangesSection = ".section __DWARF,__debug_ranges";
       DwarfMacInfoSection = ".section __DWARF,__debug_macinfo";
-      TextSection = ".text";
-      DataSection = ".data";
     }
   };
 
@@ -267,29 +279,11 @@
   /// X
   struct VISIBILITY_HIDDEN DarwinAsmPrinter : public PPCAsmPrinter {
   
-    DarwinDwarfWriter DW;
+    DwarfWriter DW;
 
-    DarwinAsmPrinter(std::ostream &O, PPCTargetMachine &TM)
-      : PPCAsmPrinter(O, TM), DW(O, this) {
+    DarwinAsmPrinter(std::ostream &O, PPCTargetMachine &TM, TargetAsmInfo *T)
+      : PPCAsmPrinter(O, TM, T), DW(O, this, T) {
       bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
-      CommentString = ";";
-      GlobalPrefix = "_";
-      PrivateGlobalPrefix = "L";     // Marker for constant pool idxs
-      ZeroDirective = "\t.space\t";  // ".space N" emits N zeros.
-      SetDirective = "\t.set";
-      if (isPPC64)
-        Data64bitsDirective = ".quad\t";       // we can't emit a 64-bit unit
-      else
-        Data64bitsDirective = 0;       // we can't emit a 64-bit unit
-      AlignmentIsInBytes = false;    // Alignment is by power of 2.
-      ConstantPoolSection = "\t.const\t";
-      JumpTableDataSection = ".const";
-      JumpTableTextSection = "\t.text";
-      LCOMMDirective = "\t.lcomm\t";
-      StaticCtorsSection = ".mod_init_func";
-      StaticDtorsSection = ".mod_term_func";
-      InlineAsmStart = "# InlineAsm Start";
-      InlineAsmEnd = "# InlineAsm End";
     }
 
     virtual const char *getPassName() const {
@@ -309,13 +303,14 @@
   };
 } // end of anonymous namespace
 
-/// createDarwinAsmPrinterPass - Returns a pass that prints the PPC assembly
+/// createDarwinCodePrinterPass - Returns a pass that prints the PPC assembly
 /// code for a MachineFunction to the given output stream, in a format that the
 /// Darwin assembler can deal with.
 ///
-FunctionPass *llvm::createDarwinAsmPrinter(std::ostream &o,
-                                           PPCTargetMachine &tm) {
-  return new DarwinAsmPrinter(o, tm);
+FunctionPass *llvm::createDarwinCodePrinterPass(std::ostream &o,
+                                                PPCTargetMachine &tm) {
+  TargetAsmInfo *TAI = new DarwinTargetAsmInfo(tm);
+  return new DarwinAsmPrinter(o, tm, TAI);
 }
 
 // Include the auto-generated portion of the assembly writer
@@ -332,23 +327,23 @@
     printBasicBlockLabel(MO.getMachineBasicBlock());
     return;
   case MachineOperand::MO_JumpTableIndex:
-    O << PrivateGlobalPrefix << "JTI" << getFunctionNumber()
+    O << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
       << '_' << MO.getJumpTableIndex();
     // FIXME: PIC relocation model
     return;
   case MachineOperand::MO_ConstantPoolIndex:
-    O << PrivateGlobalPrefix << "CPI" << getFunctionNumber()
+    O << TAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
       << '_' << MO.getConstantPoolIndex();
     return;
   case MachineOperand::MO_ExternalSymbol:
     // Computing the address of an external symbol, not calling it.
     if (TM.getRelocationModel() != Reloc::Static) {
-      std::string Name(GlobalPrefix); Name += MO.getSymbolName();
+      std::string Name(TAI->getGlobalPrefix()); Name += MO.getSymbolName();
       GVStubs.insert(Name);
       O << "L" << Name << "$non_lazy_ptr";
       return;
     }
-    O << GlobalPrefix << MO.getSymbolName();
+    O << TAI->getGlobalPrefix() << MO.getSymbolName();
     return;
   case MachineOperand::MO_GlobalAddress: {
     // Computing the address of a global symbol, not calling it.
@@ -561,7 +556,7 @@
           << Size << ", " << Align;
       } else if (I->hasInternalLinkage()) {
         SwitchToDataSection("\t.data", I);
-        O << LCOMMDirective << name << "," << Size << "," << Align;
+        O << TAI->getLCOMMDirective() << name << "," << Size << "," << Align;
       } else {
         SwitchToDataSection("\t.data", I);
         O << ".comm " << name << "," << Size;


Index: llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
diff -u llvm/lib/Target/PowerPC/PPCTargetMachine.cpp:1.103 llvm/lib/Target/PowerPC/PPCTargetMachine.cpp:1.104
--- llvm/lib/Target/PowerPC/PPCTargetMachine.cpp:1.103	Sun Sep  3 23:14:57 2006
+++ llvm/lib/Target/PowerPC/PPCTargetMachine.cpp	Wed Sep  6 13:34:40 2006
@@ -117,7 +117,7 @@
 
 bool PPCTargetMachine::addAssemblyEmitter(FunctionPassManager &PM, bool Fast, 
                                           std::ostream &Out) {
-  PM.add(createDarwinAsmPrinter(Out, *this));
+  PM.add(createDarwinCodePrinterPass(Out, *this));
   return false;
 }
 





From jlaskey at apple.com  Wed Sep  6 13:35:05 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Wed, 6 Sep 2006 13:35:05 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp
Message-ID: <200609061835.k86IZ51r031770@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaAsmPrinter.cpp updated: 1.46 -> 1.47
---
Log message:

Separate target specific asm properties from the asm printers.


---
Diffs of the changes:  (+14 -7)

 AlphaAsmPrinter.cpp |   21 ++++++++++++++-------
 1 files changed, 14 insertions(+), 7 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp
diff -u llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.46 llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.47
--- llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.46	Mon Jul  3 12:57:34 2006
+++ llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp	Wed Sep  6 13:34:40 2006
@@ -19,6 +19,7 @@
 #include "llvm/Type.h"
 #include "llvm/Assembly/Writer.h"
 #include "llvm/CodeGen/AsmPrinter.h"
+#include "llvm/Target/TargetAsmInfo.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Support/Mangler.h"
 #include "llvm/ADT/Statistic.h"
@@ -27,17 +28,22 @@
 
 namespace {
   Statistic<> EmittedInsts("asm-printer", "Number of machine instrs printed");
+  
+  struct VISIBILITY_HIDDEN AlphaTargetAsmInfo : public TargetAsmInfo {
+    AlphaTargetAsmInfo() {
+      AlignmentIsInBytes = false;
+      PrivateGlobalPrefix = "$";
+    }
+  };
 
-  struct AlphaAsmPrinter : public AsmPrinter {
+  struct VISIBILITY_HIDDEN AlphaAsmPrinter : public AsmPrinter {
 
     /// Unique incrementer for label values for referencing Global values.
     ///
     unsigned LabelNumber;
 
-     AlphaAsmPrinter(std::ostream &o, TargetMachine &tm)
-       : AsmPrinter(o, tm), LabelNumber(0) {
-      AlignmentIsInBytes = false;
-      PrivateGlobalPrefix = "$";
+    AlphaAsmPrinter(std::ostream &o, TargetMachine &tm, TargetAsmInfo *T)
+       : AsmPrinter(o, tm, T), LabelNumber(0) {
     }
 
     /// We name each basic block in a Function with a unique number, so
@@ -76,7 +82,8 @@
 ///
 FunctionPass *llvm::createAlphaCodePrinterPass (std::ostream &o,
                                                   TargetMachine &tm) {
-  return new AlphaAsmPrinter(o, tm);
+  AlphaTargetAsmInfo *TAI = new AlphaTargetAsmInfo();
+  return new AlphaAsmPrinter(o, tm, TAI);
 }
 
 #include "AlphaGenAsmWriter.inc"
@@ -115,7 +122,7 @@
     return;
 
   case MachineOperand::MO_ConstantPoolIndex:
-    O << PrivateGlobalPrefix << "CPI" << getFunctionNumber() << "_"
+    O << TAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber() << "_"
       << MO.getConstantPoolIndex();
     return;
 





From jlaskey at apple.com  Wed Sep  6 13:35:05 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Wed, 6 Sep 2006 13:35:05 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/IA64/IA64AsmPrinter.cpp
Message-ID: <200609061835.k86IZ5eo031765@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/IA64:

IA64AsmPrinter.cpp updated: 1.33 -> 1.34
---
Log message:

Separate target specific asm properties from the asm printers.


---
Diffs of the changes:  (+15 -6)

 IA64AsmPrinter.cpp |   21 +++++++++++++++------
 1 files changed, 15 insertions(+), 6 deletions(-)


Index: llvm/lib/Target/IA64/IA64AsmPrinter.cpp
diff -u llvm/lib/Target/IA64/IA64AsmPrinter.cpp:1.33 llvm/lib/Target/IA64/IA64AsmPrinter.cpp:1.34
--- llvm/lib/Target/IA64/IA64AsmPrinter.cpp:1.33	Mon May  8 23:59:56 2006
+++ llvm/lib/Target/IA64/IA64AsmPrinter.cpp	Wed Sep  6 13:34:40 2006
@@ -24,6 +24,7 @@
 #include "llvm/CodeGen/AsmPrinter.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/TargetAsmInfo.h"
 #include "llvm/Support/Mangler.h"
 #include "llvm/ADT/Statistic.h"
 #include <iostream>
@@ -32,10 +33,8 @@
 namespace {
   Statistic<> EmittedInsts("asm-printer", "Number of machine instrs printed");
 
-  struct IA64AsmPrinter : public AsmPrinter {
-    std::set<std::string> ExternalFunctionNames, ExternalObjectNames;
-
-    IA64AsmPrinter(std::ostream &O, TargetMachine &TM) : AsmPrinter(O, TM) {
+  struct VISIBILITY_HIDDEN IA64TargetAsmInfo : public TargetAsmInfo {
+    IA64TargetAsmInfo() {
       CommentString = "//";
       Data8bitsDirective = "\tdata1\t";     // FIXME: check that we are
       Data16bitsDirective = "\tdata2.ua\t"; // disabling auto-alignment
@@ -52,6 +51,14 @@
       // FIXME: would be nice to have rodata (no 'w') when appropriate?
       ConstantPoolSection = "\n\t.section .data, \"aw\", \"progbits\"\n";
     }
+  };
+  
+  struct IA64AsmPrinter : public AsmPrinter {
+    std::set<std::string> ExternalFunctionNames, ExternalObjectNames;
+
+    IA64AsmPrinter(std::ostream &O, TargetMachine &TM, TargetAsmInfo *T)
+      : AsmPrinter(O, TM, T) {
+    }
 
     virtual const char *getPassName() const {
       return "IA64 Assembly Printer";
@@ -185,7 +192,8 @@
     printBasicBlockLabel(MO.getMachineBasicBlock());
     return;
   case MachineOperand::MO_ConstantPoolIndex: {
-    O << "@gprel(" << PrivateGlobalPrefix << "CPI" << getFunctionNumber() << "_"
+    O << "@gprel(" << TAI->getPrivateGlobalPrefix()
+      << "CPI" << getFunctionNumber() << "_"
       << MO.getConstantPoolIndex() << ")";
     return;
   }
@@ -358,7 +366,8 @@
 ///
 FunctionPass *llvm::createIA64CodePrinterPass(std::ostream &o,
                                               IA64TargetMachine &tm) {
-  return new IA64AsmPrinter(o, tm);
+  IA64TargetAsmInfo *TAI = new IA64TargetAsmInfo();
+  return new IA64AsmPrinter(o, tm, TAI);
 }
 
 





From jlaskey at apple.com  Wed Sep  6 13:35:06 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Wed, 6 Sep 2006 13:35:06 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp
	X86ATTAsmPrinter.h X86AsmPrinter.cpp X86AsmPrinter.h
	X86IntelAsmPrinter.cpp X86IntelAsmPrinter.h
Message-ID: <200609061835.k86IZ6aN031792@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86ATTAsmPrinter.cpp updated: 1.58 -> 1.59
X86ATTAsmPrinter.h updated: 1.13 -> 1.14
X86AsmPrinter.cpp updated: 1.192 -> 1.193
X86AsmPrinter.h updated: 1.27 -> 1.28
X86IntelAsmPrinter.cpp updated: 1.52 -> 1.53
X86IntelAsmPrinter.h updated: 1.21 -> 1.22
---
Log message:

Separate target specific asm properties from the asm printers.


---
Diffs of the changes:  (+92 -96)

 X86ATTAsmPrinter.cpp   |   16 ++++----
 X86ATTAsmPrinter.h     |    4 +-
 X86AsmPrinter.cpp      |   90 ++++++++++++++++++++++++++++++++++---------------
 X86AsmPrinter.h        |   34 ++++--------------
 X86IntelAsmPrinter.cpp |   40 ++++-----------------
 X86IntelAsmPrinter.h   |    4 +-
 6 files changed, 92 insertions(+), 96 deletions(-)


Index: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp
diff -u llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.58 llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.59
--- llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.58	Tue Aug 29 17:13:10 2006
+++ llvm/lib/Target/X86/X86ATTAsmPrinter.cpp	Wed Sep  6 13:34:40 2006
@@ -43,11 +43,11 @@
   switch (F->getLinkage()) {
   default: assert(0 && "Unknown linkage type!");
   case Function::InternalLinkage:  // Symbols default to internal.
-    SwitchToTextSection(DefaultTextSection, F);
+    SwitchToTextSection(TAI->getTextSection(), F);
     EmitAlignment(4, F);     // FIXME: This should be parameterized somewhere.
     break;
   case Function::ExternalLinkage:
-    SwitchToTextSection(DefaultTextSection, F);
+    SwitchToTextSection(TAI->getTextSection(), F);
     EmitAlignment(4, F);     // FIXME: This should be parameterized somewhere.
     O << "\t.globl\t" << CurrentFnName << "\n";
     break;
@@ -101,7 +101,7 @@
   // lables that are used in jump table expressions (e.g. LBB1_1-LJT1_0).
   EmitJumpTableInfo(MF.getJumpTableInfo());
   
-  if (HasDotTypeDotSizeDirective)
+  if (TAI->hasDotTypeDotSizeDirective())
     O << "\t.size " << CurrentFnName << ", .-" << CurrentFnName << "\n";
 
   if (Subtarget->isTargetDarwin()) {
@@ -144,7 +144,7 @@
   case MachineOperand::MO_JumpTableIndex: {
     bool isMemOp  = Modifier && !strcmp(Modifier, "mem");
     if (!isMemOp) O << '$';
-    O << PrivateGlobalPrefix << "JTI" << getFunctionNumber() << "_"
+    O << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber() << "_"
       << MO.getJumpTableIndex();
     if (Subtarget->isTargetDarwin() && 
         TM.getRelocationModel() == Reloc::PIC_)
@@ -154,7 +154,7 @@
   case MachineOperand::MO_ConstantPoolIndex: {
     bool isMemOp  = Modifier && !strcmp(Modifier, "mem");
     if (!isMemOp) O << '$';
-    O << PrivateGlobalPrefix << "CPI" << getFunctionNumber() << "_"
+    O << TAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber() << "_"
       << MO.getConstantPoolIndex();
     if (Subtarget->isTargetDarwin() && 
         TM.getRelocationModel() == Reloc::PIC_)
@@ -206,14 +206,14 @@
     if (isCallOp && 
         Subtarget->isTargetDarwin() && 
         TM.getRelocationModel() != Reloc::Static) {
-      std::string Name(GlobalPrefix);
+      std::string Name(TAI->getGlobalPrefix());
       Name += MO.getSymbolName();
       FnStubs.insert(Name);
       O << "L" << Name << "$stub";
       return;
     }
     if (!isCallOp) O << '$';
-    O << GlobalPrefix << MO.getSymbolName();
+    O << TAI->getGlobalPrefix() << MO.getSymbolName();
     return;
   }
   default:
@@ -388,7 +388,7 @@
       Reg1 = getX86SubSuperRegister(Reg1, MVT::i16);
     else
       Reg1 = getX86SubSuperRegister(Reg1, MVT::i8);
-    O << CommentString << " TRUNCATE ";
+    O << TAI->getCommentString() << " TRUNCATE ";
     if (Reg0 != Reg1)
       O << "\n\t";
     break;


Index: llvm/lib/Target/X86/X86ATTAsmPrinter.h
diff -u llvm/lib/Target/X86/X86ATTAsmPrinter.h:1.13 llvm/lib/Target/X86/X86ATTAsmPrinter.h:1.14
--- llvm/lib/Target/X86/X86ATTAsmPrinter.h:1.13	Fri Apr 28 18:19:39 2006
+++ llvm/lib/Target/X86/X86ATTAsmPrinter.h	Wed Sep  6 13:34:40 2006
@@ -20,8 +20,8 @@
 namespace llvm {
 
 struct X86ATTAsmPrinter : public X86SharedAsmPrinter {
- X86ATTAsmPrinter(std::ostream &O, X86TargetMachine &TM)
-    : X86SharedAsmPrinter(O, TM) { }
+ X86ATTAsmPrinter(std::ostream &O, X86TargetMachine &TM, TargetAsmInfo *T)
+    : X86SharedAsmPrinter(O, TM, T) { }
 
   virtual const char *getPassName() const {
     return "X86 AT&T-Style Assembly Printer";


Index: llvm/lib/Target/X86/X86AsmPrinter.cpp
diff -u llvm/lib/Target/X86/X86AsmPrinter.cpp:1.192 llvm/lib/Target/X86/X86AsmPrinter.cpp:1.193
--- llvm/lib/Target/X86/X86AsmPrinter.cpp:1.192	Sat Aug 12 16:29:52 2006
+++ llvm/lib/Target/X86/X86AsmPrinter.cpp	Wed Sep  6 13:34:40 2006
@@ -26,10 +26,11 @@
 #include "llvm/Support/CommandLine.h"
 using namespace llvm;
 
+enum AsmWriterFlavorTy { att, intel };
+
 Statistic<> llvm::EmittedInsts("asm-printer",
                                "Number of machine instrs printed");
 
-enum AsmWriterFlavorTy { att, intel };
 cl::opt<AsmWriterFlavorTy>
 AsmWriterFlavor("x86-asm-syntax",
                 cl::desc("Choose style of code to emit from X86 backend:"),
@@ -44,16 +45,11 @@
 #endif
                 );
 
-// Out of line virtual function to home classes.
-void X86DwarfWriter::virtfn() {}
-
-
-/// doInitialization
-bool X86SharedAsmPrinter::doInitialization(Module &M) {
-  PrivateGlobalPrefix = ".L";
-  DefaultTextSection = ".text";
-  DefaultDataSection = ".data";
+X86TargetAsmInfo::X86TargetAsmInfo(X86TargetMachine &TM) {
+  const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
   
+  //FIXME - Should to be simplified.
+   
   switch (Subtarget->TargetType) {
   case X86Subtarget::isDarwin:
     AlignmentIsInBytes = false;
@@ -73,6 +69,19 @@
     InlineAsmStart = "# InlineAsm Start";
     InlineAsmEnd = "# InlineAsm End";
     SetDirective = "\t.set";
+    
+    NeedsSet = true;
+    DwarfAbbrevSection = ".section __DWARF,__debug_abbrev,regular,debug";
+    DwarfInfoSection = ".section __DWARF,__debug_info,regular,debug";
+    DwarfLineSection = ".section __DWARF,__debug_line,regular,debug";
+    DwarfFrameSection = ".section __DWARF,__debug_frame,regular,debug";
+    DwarfPubNamesSection = ".section __DWARF,__debug_pubnames,regular,debug";
+    DwarfPubTypesSection = ".section __DWARF,__debug_pubtypes,regular,debug";
+    DwarfStrSection = ".section __DWARF,__debug_str,regular,debug";
+    DwarfLocSection = ".section __DWARF,__debug_loc,regular,debug";
+    DwarfARangesSection = ".section __DWARF,__debug_aranges,regular,debug";
+    DwarfRangesSection = ".section __DWARF,__debug_ranges,regular,debug";
+    DwarfMacInfoSection = ".section __DWARF,__debug_macinfo,regular,debug";
     break;
   case X86Subtarget::isCygwin:
     GlobalPrefix = "_";
@@ -88,6 +97,33 @@
   default: break;
   }
   
+  if (AsmWriterFlavor == intel) {
+    GlobalPrefix = "_";
+    CommentString = ";";
+  
+    PrivateGlobalPrefix = "$";
+    AlignDirective = "\talign\t";
+    ZeroDirective = "\tdb\t";
+    ZeroDirectiveSuffix = " dup(0)";
+    AsciiDirective = "\tdb\t";
+    AscizDirective = 0;
+    Data8bitsDirective = "\tdb\t";
+    Data16bitsDirective = "\tdw\t";
+    Data32bitsDirective = "\tdd\t";
+    Data64bitsDirective = "\tdq\t";
+    HasDotTypeDotSizeDirective = false;
+    
+    TextSection = "_text";
+    DataSection = "_data";
+    SwitchToSectionDirective = "";
+    TextSectionStartSuffix = "\tsegment 'CODE'";
+    DataSectionStartSuffix = "\tsegment 'DATA'";
+    SectionEndDirectiveSuffix = "\tends\n";
+  }
+}
+
+/// doInitialization
+bool X86SharedAsmPrinter::doInitialization(Module &M) {  
   if (Subtarget->isTargetDarwin()) {
     // Emit initial debug information.
     DW.BeginModule(&M);
@@ -127,25 +163,25 @@
           O << "\t.zerofill __DATA__, __common, " << name << ", "
             << Size << ", " << Align;
       } else {
-        SwitchToDataSection(DefaultDataSection, I);
-        if (LCOMMDirective != NULL) {
+        SwitchToDataSection(TAI->getDataSection(), I);
+        if (TAI->getLCOMMDirective() != NULL) {
           if (I->hasInternalLinkage()) {
-            O << LCOMMDirective << name << "," << Size;
+            O << TAI->getLCOMMDirective() << name << "," << Size;
             if (Subtarget->isTargetDarwin())
-              O << "," << (AlignmentIsInBytes ? (1 << Align) : Align);
+              O << "," << (TAI->getAlignmentIsInBytes() ? (1 << Align) : Align);
           } else
-            O << COMMDirective  << name << "," << Size;
+            O << TAI->getCOMMDirective()  << name << "," << Size;
         } else {
           if (Subtarget->TargetType != X86Subtarget::isCygwin) {
             if (I->hasInternalLinkage())
               O << "\t.local\t" << name << "\n";
           }
-          O << COMMDirective  << name << "," << Size;
-          if (COMMDirectiveTakesAlignment)
-            O << "," << (AlignmentIsInBytes ? (1 << Align) : Align);
+          O << TAI->getCOMMDirective()  << name << "," << Size;
+          if (TAI->getCOMMDirectiveTakesAlignment())
+            O << "," << (TAI->getAlignmentIsInBytes() ? (1 << Align) : Align);
         }
       }
-      O << "\t\t" << CommentString << " " << I->getName() << "\n";
+      O << "\t\t" << TAI->getCommentString() << " " << I->getName() << "\n";
     } else {
       switch (I->getLinkage()) {
       case GlobalValue::LinkOnceLinkage:
@@ -170,16 +206,16 @@
         O << "\t.globl " << name << "\n";
         // FALL THROUGH
       case GlobalValue::InternalLinkage:
-        SwitchToDataSection(DefaultDataSection, I);
+        SwitchToDataSection(TAI->getDataSection(), I);
         break;
       default:
         assert(0 && "Unknown linkage type!");
       }
 
       EmitAlignment(Align, I);
-      O << name << ":\t\t\t\t" << CommentString << " " << I->getName()
+      O << name << ":\t\t\t\t" << TAI->getCommentString() << " " << I->getName()
         << "\n";
-      if (HasDotTypeDotSizeDirective)
+      if (TAI->hasDotTypeDotSizeDirective())
         O << "\t.size " << name << ", " << Size << "\n";
 
       EmitGlobalConstant(C);
@@ -234,13 +270,13 @@
 /// machine description.
 ///
 FunctionPass *llvm::createX86CodePrinterPass(std::ostream &o,
-                                             X86TargetMachine &tm){
+                                             X86TargetMachine &tm) {
+  TargetAsmInfo *TAI = new X86TargetAsmInfo(tm);
+
   switch (AsmWriterFlavor) {
   default:
     assert(0 && "Unknown asm flavor!");
-  case intel:
-    return new X86IntelAsmPrinter(o, tm);
-  case att:
-    return new X86ATTAsmPrinter(o, tm);
+  case intel: return new X86IntelAsmPrinter(o, tm, TAI);
+  case att: return new X86ATTAsmPrinter(o, tm, TAI);
   }
 }


Index: llvm/lib/Target/X86/X86AsmPrinter.h
diff -u llvm/lib/Target/X86/X86AsmPrinter.h:1.27 llvm/lib/Target/X86/X86AsmPrinter.h:1.28
--- llvm/lib/Target/X86/X86AsmPrinter.h:1.27	Tue Aug 29 17:14:48 2006
+++ llvm/lib/Target/X86/X86AsmPrinter.h	Wed Sep  6 13:34:40 2006
@@ -22,6 +22,7 @@
 #include "llvm/CodeGen/DwarfWriter.h"
 #include "llvm/CodeGen/MachineDebugInfo.h"
 #include "llvm/ADT/Statistic.h"
+#include "llvm/Target/TargetAsmInfo.h"
 #include <set>
 
 
@@ -29,33 +30,16 @@
 
 extern Statistic<> EmittedInsts;
 
-/// X86DwarfWriter - Dwarf debug info writer customized for Darwin/Mac OS X
-///
-struct X86DwarfWriter : public DwarfWriter {
-  X86DwarfWriter(std::ostream &o, AsmPrinter *ap) : DwarfWriter(o, ap) {
-      needsSet = true;
-      DwarfAbbrevSection = ".section __DWARF,__debug_abbrev,regular,debug";
-      DwarfInfoSection = ".section __DWARF,__debug_info,regular,debug";
-      DwarfLineSection = ".section __DWARF,__debug_line,regular,debug";
-      DwarfFrameSection = ".section __DWARF,__debug_frame,regular,debug";
-      DwarfPubNamesSection = ".section __DWARF,__debug_pubnames,regular,debug";
-      DwarfPubTypesSection = ".section __DWARF,__debug_pubtypes,regular,debug";
-      DwarfStrSection = ".section __DWARF,__debug_str,regular,debug";
-      DwarfLocSection = ".section __DWARF,__debug_loc,regular,debug";
-      DwarfARangesSection = ".section __DWARF,__debug_aranges,regular,debug";
-      DwarfRangesSection = ".section __DWARF,__debug_ranges,regular,debug";
-      DwarfMacInfoSection = ".section __DWARF,__debug_macinfo,regular,debug";
-      TextSection = ".text";
-      DataSection = ".data";
-  }
-  virtual void virtfn();  // out of line virtual fn.
+struct VISIBILITY_HIDDEN X86TargetAsmInfo : public TargetAsmInfo {
+  X86TargetAsmInfo(X86TargetMachine &TM);
 };
 
-struct X86SharedAsmPrinter : public AsmPrinter {
-  X86DwarfWriter DW;
+struct VISIBILITY_HIDDEN X86SharedAsmPrinter : public AsmPrinter {
+  DwarfWriter DW;
 
-  X86SharedAsmPrinter(std::ostream &O, X86TargetMachine &TM)
-    : AsmPrinter(O, TM), DW(O, this) {
+  X86SharedAsmPrinter(std::ostream &O, X86TargetMachine &TM,
+                      TargetAsmInfo *T)
+    : AsmPrinter(O, TM, T), DW(O, this, T) {
     Subtarget = &TM.getSubtarget<X86Subtarget>();
   }
 
@@ -70,8 +54,6 @@
     MachineFunctionPass::getAnalysisUsage(AU);
   }
 
-  const char *DefaultTextSection;   // "_text" for MASM, ".text" for others.
-  const char *DefaultDataSection;   // "_data" for MASM, ".data" for others.
   const X86Subtarget *Subtarget;
 
   // Necessary for Darwin to print out the apprioriate types of linker stubs


Index: llvm/lib/Target/X86/X86IntelAsmPrinter.cpp
diff -u llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.52 llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.53
--- llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.52	Wed May 31 17:34:26 2006
+++ llvm/lib/Target/X86/X86IntelAsmPrinter.cpp	Wed Sep  6 13:34:40 2006
@@ -22,10 +22,6 @@
 #include "llvm/Target/TargetOptions.h"
 using namespace llvm;
 
-X86IntelAsmPrinter::X86IntelAsmPrinter(std::ostream &O, X86TargetMachine &TM)
-    : X86SharedAsmPrinter(O, TM) {
-}
-
 /// runOnMachineFunction - This uses the printMachineInstruction()
 /// method to print assembly for each instruction.
 ///
@@ -106,8 +102,8 @@
   case MachineOperand::MO_ConstantPoolIndex: {
     bool isMemOp  = Modifier && !strcmp(Modifier, "mem");
     if (!isMemOp) O << "OFFSET ";
-    O << "[" << PrivateGlobalPrefix << "CPI" << getFunctionNumber() << "_"
-      << MO.getConstantPoolIndex();
+    O << "[" << TAI->getPrivateGlobalPrefix() << "CPI"
+      << getFunctionNumber() << "_" << MO.getConstantPoolIndex();
     int Offset = MO.getOffset();
     if (Offset > 0)
       O << " + " << Offset;
@@ -131,7 +127,7 @@
   case MachineOperand::MO_ExternalSymbol: {
     bool isCallOp = Modifier && !strcmp(Modifier, "call");
     if (!isCallOp) O << "OFFSET ";
-    O << GlobalPrefix << MO.getSymbolName();
+    O << TAI->getGlobalPrefix() << MO.getSymbolName();
     return;
   }
   default:
@@ -272,7 +268,7 @@
       Reg1 = getX86SubSuperRegister(Reg1, MVT::i16);
     else
       Reg1 = getX86SubSuperRegister(Reg1, MVT::i8);
-    O << CommentString << " TRUNCATE ";
+    O << TAI->getCommentString() << " TRUNCATE ";
     if (Reg0 != Reg1)
       O << "\n\t";
     break;
@@ -284,30 +280,9 @@
 }
 
 bool X86IntelAsmPrinter::doInitialization(Module &M) {
-  GlobalPrefix = "_";
-  CommentString = ";";
-
   X86SharedAsmPrinter::doInitialization(M);
-
-  PrivateGlobalPrefix = "$";
-  AlignDirective = "\talign\t";
-  ZeroDirective = "\tdb\t";
-  ZeroDirectiveSuffix = " dup(0)";
-  AsciiDirective = "\tdb\t";
-  AscizDirective = 0;
-  Data8bitsDirective = "\tdb\t";
-  Data16bitsDirective = "\tdw\t";
-  Data32bitsDirective = "\tdd\t";
-  Data64bitsDirective = "\tdq\t";
-  HasDotTypeDotSizeDirective = false;
-  Mang->markCharUnacceptable('.');
   
-  DefaultTextSection = "_text";
-  DefaultDataSection = "_data";
-  SwitchToSectionDirective = "";
-  TextSectionStartSuffix = "\tsegment 'CODE'";
-  DataSectionStartSuffix = "\tsegment 'DATA'";
-  SectionEndDirectiveSuffix = "\tends\n";
+  Mang->markCharUnacceptable('.');
 
   O << "\t.686\n\t.model flat\n\n";
 
@@ -365,7 +340,7 @@
       O << "\tpublic " << name << "\n";
       // FALL THROUGH
     case GlobalValue::InternalLinkage:
-      SwitchToDataSection(DefaultDataSection, I);
+      SwitchToDataSection(TAI->getDataSection(), I);
       break;
     default:
       assert(0 && "Unknown linkage type!");
@@ -374,7 +349,8 @@
     if (!bCustomSegment)
       EmitAlignment(Align, I);
 
-    O << name << ":\t\t\t\t" << CommentString << " " << I->getName() << '\n';
+    O << name << ":\t\t\t\t" << TAI->getCommentString()
+      << " " << I->getName() << '\n';
 
     EmitGlobalConstant(C);
 


Index: llvm/lib/Target/X86/X86IntelAsmPrinter.h
diff -u llvm/lib/Target/X86/X86IntelAsmPrinter.h:1.21 llvm/lib/Target/X86/X86IntelAsmPrinter.h:1.22
--- llvm/lib/Target/X86/X86IntelAsmPrinter.h:1.21	Thu May  4 13:05:43 2006
+++ llvm/lib/Target/X86/X86IntelAsmPrinter.h	Wed Sep  6 13:34:40 2006
@@ -21,7 +21,9 @@
 namespace llvm {
 
 struct X86IntelAsmPrinter : public X86SharedAsmPrinter {
-  X86IntelAsmPrinter(std::ostream &O, X86TargetMachine &TM);
+  X86IntelAsmPrinter(std::ostream &O, X86TargetMachine &TM, TargetAsmInfo *T)
+      : X86SharedAsmPrinter(O, TM, T) {
+  }
 
   virtual const char *getPassName() const {
     return "X86 Intel-Style Assembly Printer";





From jlaskey at apple.com  Wed Sep  6 13:35:06 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Wed, 6 Sep 2006 13:35:06 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/AsmPrinter.cpp DwarfWriter.cpp
Message-ID: <200609061835.k86IZ6r3031777@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen:

AsmPrinter.cpp updated: 1.90 -> 1.91
DwarfWriter.cpp updated: 1.73 -> 1.74
---
Log message:

Separate target specific asm properties from the asm printers.


---
Diffs of the changes:  (+169 -212)

 AsmPrinter.cpp  |  237 ++++++++++++++++++++++++--------------------------------
 DwarfWriter.cpp |  144 +++++++++++++++-------------------
 2 files changed, 169 insertions(+), 212 deletions(-)


Index: llvm/lib/CodeGen/AsmPrinter.cpp
diff -u llvm/lib/CodeGen/AsmPrinter.cpp:1.90 llvm/lib/CodeGen/AsmPrinter.cpp:1.91
--- llvm/lib/CodeGen/AsmPrinter.cpp:1.90	Tue Sep  5 15:02:51 2006
+++ llvm/lib/CodeGen/AsmPrinter.cpp	Wed Sep  6 13:34:40 2006
@@ -20,51 +20,16 @@
 #include "llvm/CodeGen/MachineJumpTableInfo.h"
 #include "llvm/Support/Mangler.h"
 #include "llvm/Support/MathExtras.h"
+#include "llvm/Target/TargetAsmInfo.h"
 #include "llvm/Target/TargetData.h"
 #include "llvm/Target/TargetMachine.h"
 #include <iostream>
 #include <cerrno>
 using namespace llvm;
 
-AsmPrinter::AsmPrinter(std::ostream &o, TargetMachine &tm)
-: FunctionNumber(0), O(o), TM(tm),
-  CommentString("#"),
-  GlobalPrefix(""),
-  PrivateGlobalPrefix("."),
-  GlobalVarAddrPrefix(""),
-  GlobalVarAddrSuffix(""),
-  FunctionAddrPrefix(""),
-  FunctionAddrSuffix(""),
-  InlineAsmStart("#APP"),
-  InlineAsmEnd("#NO_APP"),
-  ZeroDirective("\t.zero\t"),
-  ZeroDirectiveSuffix(0),
-  AsciiDirective("\t.ascii\t"),
-  AscizDirective("\t.asciz\t"),
-  Data8bitsDirective("\t.byte\t"),
-  Data16bitsDirective("\t.short\t"),
-  Data32bitsDirective("\t.long\t"),
-  Data64bitsDirective("\t.quad\t"),
-  AlignDirective("\t.align\t"),
-  AlignmentIsInBytes(true),
-  SwitchToSectionDirective("\t.section\t"),
-  TextSectionStartSuffix(""),
-  DataSectionStartSuffix(""),
-  SectionEndDirectiveSuffix(0),
-  ConstantPoolSection("\t.section .rodata\n"),
-  JumpTableDataSection("\t.section .rodata\n"),
-  JumpTableTextSection("\t.text\n"),
-  StaticCtorsSection("\t.section .ctors,\"aw\", at progbits"),
-  StaticDtorsSection("\t.section .dtors,\"aw\", at progbits"),
-  FourByteConstantSection(0),
-  EightByteConstantSection(0),
-  SixteenByteConstantSection(0),
-  SetDirective(0),
-  LCOMMDirective(0),
-  COMMDirective("\t.comm\t"),
-  COMMDirectiveTakesAlignment(true),
-  HasDotTypeDotSizeDirective(true) {
-}
+AsmPrinter::AsmPrinter(std::ostream &o, TargetMachine &tm, TargetAsmInfo *T)
+: FunctionNumber(0), O(o), TM(tm), TAI(T)
+{}
 
 
 /// SwitchToTextSection - Switch to the specified text section of the executable
@@ -74,7 +39,7 @@
                                      const GlobalValue *GV) {
   std::string NS;
   if (GV && GV->hasSection())
-    NS = SwitchToSectionDirective + GV->getSection();
+    NS = TAI->getSwitchToSectionDirective() + GV->getSection();
   else
     NS = NewSection;
   
@@ -82,13 +47,13 @@
   if (CurrentSection == NS) return;
 
   // Close the current section, if applicable.
-  if (SectionEndDirectiveSuffix && !CurrentSection.empty())
-    O << CurrentSection << SectionEndDirectiveSuffix << "\n";
+  if (TAI->getSectionEndDirectiveSuffix() && !CurrentSection.empty())
+    O << CurrentSection << TAI->getSectionEndDirectiveSuffix() << "\n";
 
   CurrentSection = NS;
 
   if (!CurrentSection.empty())
-    O << CurrentSection << TextSectionStartSuffix << '\n';
+    O << CurrentSection << TAI->getTextSectionStartSuffix() << '\n';
 }
 
 /// SwitchToDataSection - Switch to the specified data section of the executable
@@ -98,7 +63,7 @@
                                      const GlobalValue *GV) {
   std::string NS;
   if (GV && GV->hasSection())
-    NS = SwitchToSectionDirective + GV->getSection();
+    NS = TAI->getSwitchToSectionDirective() + GV->getSection();
   else
     NS = NewSection;
   
@@ -106,23 +71,24 @@
   if (CurrentSection == NS) return;
 
   // Close the current section, if applicable.
-  if (SectionEndDirectiveSuffix && !CurrentSection.empty())
-    O << CurrentSection << SectionEndDirectiveSuffix << "\n";
+  if (TAI->getSectionEndDirectiveSuffix() && !CurrentSection.empty())
+    O << CurrentSection << TAI->getSectionEndDirectiveSuffix() << "\n";
 
   CurrentSection = NS;
   
   if (!CurrentSection.empty())
-    O << CurrentSection << DataSectionStartSuffix << '\n';
+    O << CurrentSection << TAI->getDataSectionStartSuffix() << '\n';
 }
 
 
 bool AsmPrinter::doInitialization(Module &M) {
-  Mang = new Mangler(M, GlobalPrefix);
+  Mang = new Mangler(M, TAI->getGlobalPrefix());
   
   if (!M.getModuleInlineAsm().empty())
-    O << CommentString << " Start of file scope inline assembly\n"
+    O << TAI->getCommentString() << " Start of file scope inline assembly\n"
       << M.getModuleInlineAsm()
-      << "\n" << CommentString << " End of file scope inline assembly\n";
+      << "\n" << TAI->getCommentString()
+      << " End of file scope inline assembly\n";
 
   SwitchToDataSection("", 0);   // Reset back to no section.
   
@@ -163,13 +129,13 @@
     MachineConstantPoolEntry CPE = CP[i];
     const Constant *CV = CPE.Val;
     const Type *Ty = CV->getType();
-    if (FourByteConstantSection &&
+    if (TAI->getFourByteConstantSection() &&
         TM.getTargetData()->getTypeSize(Ty) == 4)
       FourByteCPs.push_back(std::make_pair(CPE, i));
-    else if (EightByteConstantSection &&
+    else if (TAI->getSectionEndDirectiveSuffix() &&
              TM.getTargetData()->getTypeSize(Ty) == 8)
       EightByteCPs.push_back(std::make_pair(CPE, i));
-    else if (SixteenByteConstantSection &&
+    else if (TAI->getSectionEndDirectiveSuffix() &&
              TM.getTargetData()->getTypeSize(Ty) == 16)
       SixteenByteCPs.push_back(std::make_pair(CPE, i));
     else
@@ -177,10 +143,11 @@
   }
 
   unsigned Alignment = MCP->getConstantPoolAlignment();
-  EmitConstantPool(Alignment, FourByteConstantSection,    FourByteCPs);
-  EmitConstantPool(Alignment, EightByteConstantSection,   EightByteCPs);
-  EmitConstantPool(Alignment, SixteenByteConstantSection, SixteenByteCPs);
-  EmitConstantPool(Alignment, ConstantPoolSection,        OtherCPs);
+  EmitConstantPool(Alignment, TAI->getFourByteConstantSection(), FourByteCPs);
+  EmitConstantPool(Alignment, TAI->getEightByteConstantSection(), EightByteCPs);
+  EmitConstantPool(Alignment, TAI->getSixteenByteConstantSection(),
+                   SixteenByteCPs);
+  EmitConstantPool(Alignment, TAI->getConstantPoolSection(), OtherCPs);
 }
 
 void AsmPrinter::EmitConstantPool(unsigned Alignment, const char *Section,
@@ -190,8 +157,8 @@
   SwitchToDataSection(Section, 0);
   EmitAlignment(Alignment);
   for (unsigned i = 0, e = CP.size(); i != e; ++i) {
-    O << PrivateGlobalPrefix << "CPI" << getFunctionNumber() << '_'
-      << CP[i].second << ":\t\t\t\t\t" << CommentString << " ";
+    O << TAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber() << '_'
+      << CP[i].second << ":\t\t\t\t\t" << TAI->getCommentString() << " ";
     WriteTypeSymbolic(O, CP[i].first.Val->getType(), 0) << '\n';
     EmitGlobalConstant(CP[i].first.Val);
     if (i != e-1) {
@@ -215,16 +182,16 @@
   // JTEntryDirective is a string to print sizeof(ptr) for non-PIC jump tables,
   // and 32 bits for PIC since PIC jump table entries are differences, not
   // pointers to blocks.
-  const char *JTEntryDirective = Data32bitsDirective;
+  const char *JTEntryDirective = TAI->getData32bitsDirective();
   
   // Pick the directive to use to print the jump table entries, and switch to 
   // the appropriate section.
   if (TM.getRelocationModel() == Reloc::PIC_) {
-    SwitchToTextSection(JumpTableTextSection, 0);
+    SwitchToTextSection(TAI->getJumpTableTextSection(), 0);
   } else {
-    SwitchToDataSection(JumpTableDataSection, 0);
+    SwitchToDataSection(TAI->getJumpTableDataSection(), 0);
     if (TD->getPointerSize() == 8)
-      JTEntryDirective = Data64bitsDirective;
+      JTEntryDirective = TAI->getData64bitsDirective();
   }
   EmitAlignment(Log2_32(TD->getPointerAlignment()));
   
@@ -235,13 +202,13 @@
     // the number of relocations the assembler will generate for the jump table.
     // Set directives are all printed before the jump table itself.
     std::set<MachineBasicBlock*> EmittedSets;
-    if (SetDirective && TM.getRelocationModel() == Reloc::PIC_)
+    if (TAI->getSetDirective() && TM.getRelocationModel() == Reloc::PIC_)
       for (unsigned ii = 0, ee = JTBBs.size(); ii != ee; ++ii)
         if (EmittedSets.insert(JTBBs[ii]).second)
           printSetLabel(i, JTBBs[ii]);
     
-    O << PrivateGlobalPrefix << "JTI" << getFunctionNumber() << '_' << i 
-      << ":\n";
+    O << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber() 
+      << '_' << i << ":\n";
     
     for (unsigned ii = 0, ee = JTBBs.size(); ii != ee; ++ii) {
       O << JTEntryDirective << ' ';
@@ -251,12 +218,12 @@
       // If we're emitting non-PIC code, then emit the entries as direct
       // references to the target basic blocks.
       if (!EmittedSets.empty()) {
-        O << PrivateGlobalPrefix << getFunctionNumber() << '_' << i << "_set_"
-          << JTBBs[ii]->getNumber();
+        O << TAI->getPrivateGlobalPrefix() << getFunctionNumber()
+          << '_' << i << "_set_" << JTBBs[ii]->getNumber();
       } else if (TM.getRelocationModel() == Reloc::PIC_) {
         printBasicBlockLabel(JTBBs[ii], false, false);
-        O << '-' << PrivateGlobalPrefix << "JTI" << getFunctionNumber() 
-          << '_' << i;
+        O << '-' << TAI->getPrivateGlobalPrefix() << "JTI"
+          << getFunctionNumber() << '_' << i;
       } else {
         printBasicBlockLabel(JTBBs[ii], false, false);
       }
@@ -280,14 +247,14 @@
     return true;  // No need to emit this at all.
 
   if (GV->getName() == "llvm.global_ctors" && GV->use_empty()) {
-    SwitchToDataSection(StaticCtorsSection, 0);
+    SwitchToDataSection(TAI->getStaticCtorsSection(), 0);
     EmitAlignment(2, 0);
     EmitXXStructorList(GV->getInitializer());
     return true;
   } 
   
   if (GV->getName() == "llvm.global_dtors" && GV->use_empty()) {
-    SwitchToDataSection(StaticDtorsSection, 0);
+    SwitchToDataSection(TAI->getStaticDtorsSection(), 0);
     EmitAlignment(2, 0);
     EmitXXStructorList(GV->getInitializer());
     return true;
@@ -342,22 +309,22 @@
   if (GV && GV->getAlignment())
     NumBits = Log2_32(GV->getAlignment());
   if (NumBits == 0) return;   // No need to emit alignment.
-  if (AlignmentIsInBytes) NumBits = 1 << NumBits;
-  O << AlignDirective << NumBits << "\n";
+  if (TAI->getAlignmentIsInBytes()) NumBits = 1 << NumBits;
+  O << TAI->getAlignDirective() << NumBits << "\n";
 }
 
 /// EmitZeros - Emit a block of zeros.
 ///
 void AsmPrinter::EmitZeros(uint64_t NumZeros) const {
   if (NumZeros) {
-    if (ZeroDirective) {
-      O << ZeroDirective << NumZeros;
-      if (ZeroDirectiveSuffix)
-        O << ZeroDirectiveSuffix;
+    if (TAI->getZeroDirective()) {
+      O << TAI->getZeroDirective() << NumZeros;
+      if (TAI->getZeroDirectiveSuffix())
+        O << TAI->getZeroDirectiveSuffix();
       O << "\n";
     } else {
       for (; NumZeros; --NumZeros)
-        O << Data8bitsDirective << "0\n";
+        O << TAI->getData8bitsDirective() << "0\n";
     }
   }
 }
@@ -382,10 +349,15 @@
     // name of the variable or function as the address value, possibly
     // decorating it with GlobalVarAddrPrefix/Suffix or
     // FunctionAddrPrefix/Suffix (these all default to "" )
-    if (isa<Function>(GV))
-      O << FunctionAddrPrefix << Mang->getValueName(GV) << FunctionAddrSuffix;
-    else
-      O << GlobalVarAddrPrefix << Mang->getValueName(GV) << GlobalVarAddrSuffix;
+    if (isa<Function>(GV)) {
+      O << TAI->getFunctionAddrPrefix()
+        << Mang->getValueName(GV)
+        << TAI->getFunctionAddrSuffix();
+    } else {
+      O << TAI->getGlobalVarAddrPrefix()
+        << Mang->getValueName(GV)
+        << TAI->getGlobalVarAddrSuffix();
+    }
   } else if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(CV)) {
     const TargetData *TD = TM.getTargetData();
     switch(CE->getOpcode()) {
@@ -495,12 +467,12 @@
 ///
 void AsmPrinter::EmitString(const ConstantArray *CVA) const {
   unsigned NumElts = CVA->getNumOperands();
-  if (AscizDirective && NumElts && 
+  if (TAI->getAscizDirective() && NumElts && 
       cast<ConstantInt>(CVA->getOperand(NumElts-1))->getRawValue() == 0) {
-    O << AscizDirective;
+    O << TAI->getAscizDirective();
     printAsCString(O, CVA, NumElts-1);
   } else {
-    O << AsciiDirective;
+    O << TAI->getAsciiDirective();
     printAsCString(O, CVA, NumElts);
   }
   O << "\n";
@@ -550,50 +522,50 @@
     // precision...
     double Val = CFP->getValue();
     if (CFP->getType() == Type::DoubleTy) {
-      if (Data64bitsDirective)
-        O << Data64bitsDirective << DoubleToBits(Val) << "\t" << CommentString
-          << " double value: " << Val << "\n";
+      if (TAI->getData64bitsDirective())
+        O << TAI->getData64bitsDirective() << DoubleToBits(Val) << "\t"
+          << TAI->getCommentString() << " double value: " << Val << "\n";
       else if (TD->isBigEndian()) {
-        O << Data32bitsDirective << unsigned(DoubleToBits(Val) >> 32)
-          << "\t" << CommentString << " double most significant word "
-          << Val << "\n";
-        O << Data32bitsDirective << unsigned(DoubleToBits(Val))
-          << "\t" << CommentString << " double least significant word "
-          << Val << "\n";
+        O << TAI->getData32bitsDirective() << unsigned(DoubleToBits(Val) >> 32)
+          << "\t" << TAI->getCommentString()
+          << " double most significant word " << Val << "\n";
+        O << TAI->getData32bitsDirective() << unsigned(DoubleToBits(Val))
+          << "\t" << TAI->getCommentString()
+          << " double least significant word " << Val << "\n";
       } else {
-        O << Data32bitsDirective << unsigned(DoubleToBits(Val))
-          << "\t" << CommentString << " double least significant word " << Val
-          << "\n";
-        O << Data32bitsDirective << unsigned(DoubleToBits(Val) >> 32)
-          << "\t" << CommentString << " double most significant word " << Val
-          << "\n";
+        O << TAI->getData32bitsDirective() << unsigned(DoubleToBits(Val))
+          << "\t" << TAI->getCommentString()
+          << " double least significant word " << Val << "\n";
+        O << TAI->getData32bitsDirective() << unsigned(DoubleToBits(Val) >> 32)
+          << "\t" << TAI->getCommentString()
+          << " double most significant word " << Val << "\n";
       }
       return;
     } else {
-      O << Data32bitsDirective << FloatToBits(Val) << "\t" << CommentString
-        << " float " << Val << "\n";
+      O << TAI->getData32bitsDirective() << FloatToBits(Val)
+        << "\t" << TAI->getCommentString() << " float " << Val << "\n";
       return;
     }
   } else if (CV->getType() == Type::ULongTy || CV->getType() == Type::LongTy) {
     if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
       uint64_t Val = CI->getRawValue();
 
-      if (Data64bitsDirective)
-        O << Data64bitsDirective << Val << "\n";
+      if (TAI->getData64bitsDirective())
+        O << TAI->getData64bitsDirective() << Val << "\n";
       else if (TD->isBigEndian()) {
-        O << Data32bitsDirective << unsigned(Val >> 32)
-          << "\t" << CommentString << " Double-word most significant word "
-          << Val << "\n";
-        O << Data32bitsDirective << unsigned(Val)
-          << "\t" << CommentString << " Double-word least significant word "
-          << Val << "\n";
+        O << TAI->getData32bitsDirective() << unsigned(Val >> 32)
+          << "\t" << TAI->getCommentString()
+          << " Double-word most significant word " << Val << "\n";
+        O << TAI->getData32bitsDirective() << unsigned(Val)
+          << "\t" << TAI->getCommentString()
+          << " Double-word least significant word " << Val << "\n";
       } else {
-        O << Data32bitsDirective << unsigned(Val)
-          << "\t" << CommentString << " Double-word least significant word "
-          << Val << "\n";
-        O << Data32bitsDirective << unsigned(Val >> 32)
-          << "\t" << CommentString << " Double-word most significant word "
-          << Val << "\n";
+        O << TAI->getData32bitsDirective() << unsigned(Val)
+          << "\t" << TAI->getCommentString()
+          << " Double-word least significant word " << Val << "\n";
+        O << TAI->getData32bitsDirective() << unsigned(Val >> 32)
+          << "\t" << TAI->getCommentString()
+          << " Double-word most significant word " << Val << "\n";
       }
       return;
     }
@@ -610,25 +582,26 @@
   switch (type->getTypeID()) {
   case Type::BoolTyID:
   case Type::UByteTyID: case Type::SByteTyID:
-    O << Data8bitsDirective;
+    O << TAI->getData8bitsDirective();
     break;
   case Type::UShortTyID: case Type::ShortTyID:
-    O << Data16bitsDirective;
+    O << TAI->getData16bitsDirective();
     break;
   case Type::PointerTyID:
     if (TD->getPointerSize() == 8) {
-      assert(Data64bitsDirective &&
+      assert(TAI->getData64bitsDirective() &&
              "Target cannot handle 64-bit pointer exprs!");
-      O << Data64bitsDirective;
+      O << TAI->getData64bitsDirective();
       break;
     }
     //Fall through for pointer size == int size
   case Type::UIntTyID: case Type::IntTyID:
-    O << Data32bitsDirective;
+    O << TAI->getData32bitsDirective();
     break;
   case Type::ULongTyID: case Type::LongTyID:
-    assert(Data64bitsDirective &&"Target cannot handle 64-bit constant exprs!");
-    O << Data64bitsDirective;
+    assert(TAI->getData64bitsDirective() &&
+           "Target cannot handle 64-bit constant exprs!");
+    O << TAI->getData64bitsDirective();
     break;
   case Type::FloatTyID: case Type::DoubleTyID:
     assert (0 && "Should have already output floating point constant.");
@@ -662,7 +635,7 @@
     return;
   }
   
-  O << InlineAsmStart << "\n\t";
+  O << TAI->getInlineAsmStart() << "\n\t";
 
   // The variant of the current asmprinter: FIXME: change.
   int AsmPrinterVariant = 0;
@@ -810,7 +783,7 @@
       break;
     }
   }
-  O << "\n\t" << InlineAsmEnd << "\n";
+  O << "\n\t" << TAI->getInlineAsmEnd() << "\n";
 }
 
 /// PrintAsmOperand - Print the specified operand of MI, an INLINEASM
@@ -834,24 +807,24 @@
 void AsmPrinter::printBasicBlockLabel(const MachineBasicBlock *MBB,
                                       bool printColon,
                                       bool printComment) const {
-  O << PrivateGlobalPrefix << "BB" << FunctionNumber << "_"
+  O << TAI->getPrivateGlobalPrefix() << "BB" << FunctionNumber << "_"
     << MBB->getNumber();
   if (printColon)
     O << ':';
   if (printComment)
-    O << '\t' << CommentString << MBB->getBasicBlock()->getName();
+    O << '\t' << TAI->getCommentString() << MBB->getBasicBlock()->getName();
 }
 
 /// printSetLabel - This method prints a set label for the specified
 /// MachineBasicBlock
 void AsmPrinter::printSetLabel(unsigned uid, 
                                const MachineBasicBlock *MBB) const {
-  if (!SetDirective)
+  if (!TAI->getSetDirective())
     return;
   
-  O << SetDirective << ' ' << PrivateGlobalPrefix << getFunctionNumber() 
-    << '_' << uid << "_set_" << MBB->getNumber() << ',';
+  O << TAI->getSetDirective() << ' ' << TAI->getPrivateGlobalPrefix()
+    << getFunctionNumber() << '_' << uid << "_set_" << MBB->getNumber() << ',';
   printBasicBlockLabel(MBB, false, false);
-  O << '-' << PrivateGlobalPrefix << "JTI" << getFunctionNumber() 
+  O << '-' << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber() 
     << '_' << uid << '\n';
 }


Index: llvm/lib/CodeGen/DwarfWriter.cpp
diff -u llvm/lib/CodeGen/DwarfWriter.cpp:1.73 llvm/lib/CodeGen/DwarfWriter.cpp:1.74
--- llvm/lib/CodeGen/DwarfWriter.cpp:1.73	Fri Sep  1 07:55:05 2006
+++ llvm/lib/CodeGen/DwarfWriter.cpp	Wed Sep  6 13:34:40 2006
@@ -23,6 +23,7 @@
 #include "llvm/Support/Dwarf.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Mangler.h"
+#include "llvm/Target/TargetAsmInfo.h"
 #include "llvm/Target/MRegisterInfo.h"
 #include "llvm/Target/TargetData.h"
 #include "llvm/Target/TargetMachine.h"
@@ -674,7 +675,7 @@
 /// SizeOf - Determine size of label value in bytes.
 ///
 unsigned DIEDwarfLabel::SizeOf(const DwarfWriter &DW, unsigned Form) const {
-  return DW.getAddressSize();
+  return DW.getTargetAsmInfo()->getAddressSize();
 }
     
 //===----------------------------------------------------------------------===//
@@ -688,7 +689,7 @@
 /// SizeOf - Determine size of label value in bytes.
 ///
 unsigned DIEObjectLabel::SizeOf(const DwarfWriter &DW, unsigned Form) const {
-  return DW.getAddressSize();
+  return DW.getTargetAsmInfo()->getAddressSize();
 }
     
 //===----------------------------------------------------------------------===//
@@ -702,7 +703,7 @@
 /// SizeOf - Determine size of delta value in bytes.
 ///
 unsigned DIEDelta::SizeOf(const DwarfWriter &DW, unsigned Form) const {
-  return DW.getAddressSize();
+  return DW.getTargetAsmInfo()->getAddressSize();
 }
 
 //===----------------------------------------------------------------------===//
@@ -957,7 +958,7 @@
 void DwarfWriter::EOL(const std::string &Comment) const {
   if (DwarfVerbose && !Comment.empty()) {
     O << "\t"
-      << Asm->CommentString
+      << TAI->getCommentString()
       << " "
       << Comment;
   }
@@ -967,17 +968,17 @@
 /// EmitAlign - Print a align directive.
 ///
 void DwarfWriter::EmitAlign(unsigned Alignment) const {
-  O << Asm->AlignDirective << Alignment << "\n";
+  O << TAI->getAlignDirective() << Alignment << "\n";
 }
 
 /// EmitULEB128Bytes - Emit an assembler byte data directive to compose an
 /// unsigned leb128 value.
 void DwarfWriter::EmitULEB128Bytes(unsigned Value) const {
-  if (hasLEB128) {
+  if (TAI->hasLEB128()) {
     O << "\t.uleb128\t"
       << Value;
   } else {
-    O << Asm->Data8bitsDirective;
+    O << TAI->getData8bitsDirective();
     PrintULEB128(Value);
   }
 }
@@ -985,11 +986,11 @@
 /// EmitSLEB128Bytes - Emit an assembler byte data directive to compose a
 /// signed leb128 value.
 void DwarfWriter::EmitSLEB128Bytes(int Value) const {
-  if (hasLEB128) {
+  if (TAI->hasLEB128()) {
     O << "\t.sleb128\t"
       << Value;
   } else {
-    O << Asm->Data8bitsDirective;
+    O << TAI->getData8bitsDirective();
     PrintSLEB128(Value);
   }
 }
@@ -1052,29 +1053,29 @@
 /// EmitInt8 - Emit a byte directive and value.
 ///
 void DwarfWriter::EmitInt8(int Value) const {
-  O << Asm->Data8bitsDirective;
+  O << TAI->getData8bitsDirective();
   PrintHex(Value & 0xFF);
 }
 
 /// EmitInt16 - Emit a short directive and value.
 ///
 void DwarfWriter::EmitInt16(int Value) const {
-  O << Asm->Data16bitsDirective;
+  O << TAI->getData16bitsDirective();
   PrintHex(Value & 0xFFFF);
 }
 
 /// EmitInt32 - Emit a long directive and value.
 ///
 void DwarfWriter::EmitInt32(int Value) const {
-  O << Asm->Data32bitsDirective;
+  O << TAI->getData32bitsDirective();
   PrintHex(Value);
 }
 
 /// EmitInt64 - Emit a long long directive and value.
 ///
 void DwarfWriter::EmitInt64(uint64_t Value) const {
-  if (Asm->Data64bitsDirective) {
-    O << Asm->Data64bitsDirective << "0x" << std::hex << Value << std::dec;
+  if (TAI->getData64bitsDirective()) {
+    O << TAI->getData64bitsDirective() << "0x" << std::hex << Value << std::dec;
   } else {
     if (TD->isBigEndian()) {
       EmitInt32(unsigned(Value >> 32)); O << "\n";
@@ -1089,7 +1090,7 @@
 /// EmitString - Emit a string with quotes and a null terminator.
 /// Special characters are emitted properly. (Eg. '\t')
 void DwarfWriter::EmitString(const std::string &String) const {
-  O << Asm->AsciiDirective
+  O << TAI->getAsciiDirective()
     << "\"";
   for (unsigned i = 0, N = String.size(); i < N; ++i) {
     unsigned char C = String[i];
@@ -1122,7 +1123,7 @@
 /// PrintLabelName - Print label name in form used by Dwarf writer.
 ///
 void DwarfWriter::PrintLabelName(const char *Tag, unsigned Number) const {
-  O << Asm->PrivateGlobalPrefix
+  O << TAI->getPrivateGlobalPrefix()
     << "debug_"
     << Tag;
   if (Number) O << Number;
@@ -1138,18 +1139,18 @@
 /// EmitReference - Emit a reference to a label.
 ///
 void DwarfWriter::EmitReference(const char *Tag, unsigned Number) const {
-  if (AddressSize == 4)
-    O << Asm->Data32bitsDirective;
+  if (TAI->getAddressSize() == 4)
+    O << TAI->getData32bitsDirective();
   else
-    O << Asm->Data64bitsDirective;
+    O << TAI->getData64bitsDirective();
     
   PrintLabelName(Tag, Number);
 }
 void DwarfWriter::EmitReference(const std::string &Name) const {
-  if (AddressSize == 4)
-    O << Asm->Data32bitsDirective;
+  if (TAI->getAddressSize() == 4)
+    O << TAI->getData32bitsDirective();
   else
-    O << Asm->Data64bitsDirective;
+    O << TAI->getData64bitsDirective();
     
   O << Name;
 }
@@ -1159,7 +1160,7 @@
 /// is an option (needsSet) to use an intermediary 'set' expression.
 void DwarfWriter::EmitDifference(const char *TagHi, unsigned NumberHi,
                                  const char *TagLo, unsigned NumberLo) const {
-  if (needsSet) {
+  if (TAI->getNeedsSet()) {
     static unsigned SetCounter = 0;
     
     O << "\t.set\t";
@@ -1170,19 +1171,19 @@
     PrintLabelName(TagLo, NumberLo);
     O << "\n";
     
-    if (AddressSize == sizeof(int32_t))
-      O << Asm->Data32bitsDirective;
+    if (TAI->getAddressSize() == sizeof(int32_t))
+      O << TAI->getData32bitsDirective();
     else
-      O << Asm->Data64bitsDirective;
+      O << TAI->getData64bitsDirective();
       
     PrintLabelName("set", SetCounter);
     
     ++SetCounter;
   } else {
-    if (AddressSize == sizeof(int32_t))
-      O << Asm->Data32bitsDirective;
+    if (TAI->getAddressSize() == sizeof(int32_t))
+      O << TAI->getData32bitsDirective();
     else
-      O << Asm->Data64bitsDirective;
+      O << TAI->getData64bitsDirective();
       
     PrintLabelName(TagHi, NumberHi);
     O << "-";
@@ -1782,33 +1783,33 @@
   didInitial = true;
   
   // Dwarf sections base addresses.
-  Asm->SwitchToDataSection(DwarfFrameSection, 0);
+  Asm->SwitchToDataSection(TAI->getDwarfFrameSection(), 0);
   EmitLabel("section_frame", 0);
-  Asm->SwitchToDataSection(DwarfInfoSection, 0);
+  Asm->SwitchToDataSection(TAI->getDwarfInfoSection(), 0);
   EmitLabel("section_info", 0);
   EmitLabel("info", 0);
-  Asm->SwitchToDataSection(DwarfAbbrevSection, 0);
+  Asm->SwitchToDataSection(TAI->getDwarfAbbrevSection(), 0);
   EmitLabel("section_abbrev", 0);
   EmitLabel("abbrev", 0);
-  Asm->SwitchToDataSection(DwarfARangesSection, 0);
+  Asm->SwitchToDataSection(TAI->getDwarfARangesSection(), 0);
   EmitLabel("section_aranges", 0);
-  Asm->SwitchToDataSection(DwarfMacInfoSection, 0);
+  Asm->SwitchToDataSection(TAI->getDwarfMacInfoSection(), 0);
   EmitLabel("section_macinfo", 0);
-  Asm->SwitchToDataSection(DwarfLineSection, 0);
+  Asm->SwitchToDataSection(TAI->getDwarfLineSection(), 0);
   EmitLabel("section_line", 0);
   EmitLabel("line", 0);
-  Asm->SwitchToDataSection(DwarfLocSection, 0);
+  Asm->SwitchToDataSection(TAI->getDwarfLocSection(), 0);
   EmitLabel("section_loc", 0);
-  Asm->SwitchToDataSection(DwarfPubNamesSection, 0);
+  Asm->SwitchToDataSection(TAI->getDwarfPubNamesSection(), 0);
   EmitLabel("section_pubnames", 0);
-  Asm->SwitchToDataSection(DwarfStrSection, 0);
+  Asm->SwitchToDataSection(TAI->getDwarfStrSection(), 0);
   EmitLabel("section_str", 0);
-  Asm->SwitchToDataSection(DwarfRangesSection, 0);
+  Asm->SwitchToDataSection(TAI->getDwarfRangesSection(), 0);
   EmitLabel("section_ranges", 0);
 
-  Asm->SwitchToTextSection(TextSection, 0);
+  Asm->SwitchToTextSection(TAI->getTextSection(), 0);
   EmitLabel("text_begin", 0);
-  Asm->SwitchToDataSection(DataSection, 0);
+  Asm->SwitchToDataSection(TAI->getDataSection(), 0);
   EmitLabel("data_begin", 0);
 
   // Emit common frame information.
@@ -1958,7 +1959,7 @@
     int stackGrowth =
         Asm->TM.getFrameInfo()->getStackGrowthDirection() ==
           TargetFrameInfo::StackGrowsUp ?
-            AddressSize : -AddressSize;
+            TAI->getAddressSize() : -TAI->getAddressSize();
 
     // If advancing cfa.
     if (Dst.isRegister() && Dst.getRegister() == MachineLocation::VirtualFP) {
@@ -2013,7 +2014,7 @@
 ///
 void DwarfWriter::EmitDebugInfo() const {
   // Start debug info section.
-  Asm->SwitchToDataSection(DwarfInfoSection, 0);
+  Asm->SwitchToDataSection(TAI->getDwarfInfoSection(), 0);
   
   // Process each compile unit.
   for (unsigned i = 0, N = CompileUnits.size(); i < N; ++i) {
@@ -2033,7 +2034,7 @@
       EmitInt16(DWARF_VERSION); EOL("DWARF version number");
       EmitDifference("abbrev_begin", 0, "section_abbrev", 0);
       EOL("Offset Into Abbrev. Section");
-      EmitInt8(AddressSize); EOL("Address Size (in bytes)");
+      EmitInt8(TAI->getAddressSize()); EOL("Address Size (in bytes)");
     
       EmitDIE(Die);
       EmitLabel("info_end", Unit->getID());
@@ -2049,7 +2050,7 @@
   // Check to see if it is worth the effort.
   if (!Abbreviations.empty()) {
     // Start the debug abbrev section.
-    Asm->SwitchToDataSection(DwarfAbbrevSection, 0);
+    Asm->SwitchToDataSection(TAI->getDwarfAbbrevSection(), 0);
     
     EmitLabel("abbrev_begin", 0);
     
@@ -2083,7 +2084,7 @@
   const int MaxLineDelta = 255 + MinLineDelta;
 
   // Start the dwarf line section.
-  Asm->SwitchToDataSection(DwarfLineSection, 0);
+  Asm->SwitchToDataSection(TAI->getDwarfLineSection(), 0);
   
   // Construct the section header.
   
@@ -2148,7 +2149,7 @@
     
     if (DwarfVerbose) {
       O << "\t"
-        << Asm->CommentString << " "
+        << TAI->getCommentString() << " "
         << "Section "
         << SectionMap[j + 1].c_str() << "\n";
     }
@@ -2166,7 +2167,7 @@
         const SourceFileInfo &SourceFile = SourceFiles[SourceID];
         unsigned DirectoryID = SourceFile.getDirectoryID();
         O << "\t"
-          << Asm->CommentString << " "
+          << TAI->getCommentString() << " "
           << Directories[DirectoryID]
           << SourceFile.getName() << ":"
           << LineInfo->getLine() << "\n"; 
@@ -2233,10 +2234,10 @@
   int stackGrowth =
       Asm->TM.getFrameInfo()->getStackGrowthDirection() ==
         TargetFrameInfo::StackGrowsUp ?
-      AddressSize : -AddressSize;
+      TAI->getAddressSize() : -TAI->getAddressSize();
 
   // Start the dwarf frame section.
-  Asm->SwitchToDataSection(DwarfFrameSection, 0);
+  Asm->SwitchToDataSection(TAI->getDwarfFrameSection(), 0);
 
   EmitLabel("frame_common", 0);
   EmitDifference("frame_common_end", 0,
@@ -2266,7 +2267,7 @@
 /// section.
 void DwarfWriter::EmitFunctionDebugFrame() {
   // Start the dwarf frame section.
-  Asm->SwitchToDataSection(DwarfFrameSection, 0);
+  Asm->SwitchToDataSection(TAI->getDwarfFrameSection(), 0);
   
   EmitDifference("frame_end", SubprogramCount,
                  "frame_begin", SubprogramCount);
@@ -2296,7 +2297,7 @@
 ///
 void DwarfWriter::EmitDebugPubNames() {
   // Start the dwarf pubnames section.
-  Asm->SwitchToDataSection(DwarfPubNamesSection, 0);
+  Asm->SwitchToDataSection(TAI->getDwarfPubNamesSection(), 0);
     
   // Process each compile unit.
   for (unsigned i = 0, N = CompileUnits.size(); i < N; ++i) {
@@ -2343,7 +2344,7 @@
   // Check to see if it is worth the effort.
   if (!StringPool.empty()) {
     // Start the dwarf str section.
-    Asm->SwitchToDataSection(DwarfStrSection, 0);
+    Asm->SwitchToDataSection(TAI->getDwarfStrSection(), 0);
     
     // For each of strings in the string pool.
     for (unsigned StringID = 1, N = StringPool.size();
@@ -2363,7 +2364,7 @@
 ///
 void DwarfWriter::EmitDebugLoc() {
   // Start the dwarf loc section.
-  Asm->SwitchToDataSection(DwarfLocSection, 0);
+  Asm->SwitchToDataSection(TAI->getDwarfLocSection(), 0);
   
   O << "\n";
 }
@@ -2372,7 +2373,7 @@
 ///
 void DwarfWriter::EmitDebugARanges() {
   // Start the dwarf aranges section.
-  Asm->SwitchToDataSection(DwarfARangesSection, 0);
+  Asm->SwitchToDataSection(TAI->getDwarfARangesSection(), 0);
   
   // FIXME - Mock up
 #if 0
@@ -2389,7 +2390,7 @@
       EmitReference("info_begin", Unit->getID());
       EOL("Offset of Compilation Unit Info");
 
-      EmitInt8(AddressSize); EOL("Size of Address");
+      EmitInt8(TAI->getAddressSize()); EOL("Size of Address");
 
       EmitInt8(0); EOL("Size of Segment Descriptor");
 
@@ -2413,7 +2414,7 @@
 ///
 void DwarfWriter::EmitDebugRanges() {
   // Start the dwarf ranges section.
-  Asm->SwitchToDataSection(DwarfRangesSection, 0);
+  Asm->SwitchToDataSection(TAI->getDwarfRangesSection(), 0);
   
   O << "\n";
 }
@@ -2422,7 +2423,7 @@
 ///
 void DwarfWriter::EmitDebugMacInfo() {
   // Start the dwarf macinfo section.
-  Asm->SwitchToDataSection(DwarfMacInfoSection, 0);
+  Asm->SwitchToDataSection(TAI->getDwarfMacInfoSection(), 0);
   
   O << "\n";
 }
@@ -2466,9 +2467,10 @@
 // Main entry points.
 //
   
-DwarfWriter::DwarfWriter(std::ostream &OS, AsmPrinter *A)
+DwarfWriter::DwarfWriter(std::ostream &OS, AsmPrinter *A, TargetAsmInfo *T)
 : O(OS)
 , Asm(A)
+, TAI(T)
 , TD(Asm->TM.getTargetData())
 , RI(Asm->TM.getRegisterInfo())
 , M(NULL)
@@ -2484,24 +2486,6 @@
 , DescToDieMap()
 , SectionMap()
 , SectionSourceLines()
-, AddressSize(sizeof(int32_t))
-, hasLEB128(false)
-, hasDotLoc(false)
-, hasDotFile(false)
-, needsSet(false)
-, DwarfAbbrevSection(".debug_abbrev")
-, DwarfInfoSection(".debug_info")
-, DwarfLineSection(".debug_line")
-, DwarfFrameSection(".debug_frame")
-, DwarfPubNamesSection(".debug_pubnames")
-, DwarfPubTypesSection(".debug_pubtypes")
-, DwarfStrSection(".debug_str")
-, DwarfLocSection(".debug_loc")
-, DwarfARangesSection(".debug_aranges")
-, DwarfRangesSection(".debug_ranges")
-, DwarfMacInfoSection(".debug_macinfo")
-, TextSection(".text")
-, DataSection(".data")
 {}
 DwarfWriter::~DwarfWriter() {
   for (unsigned i = 0, N = CompileUnits.size(); i < N; ++i) {
@@ -2530,7 +2514,7 @@
     ConstructSubprogramDIEs();
     
     // Prime section data.
-    SectionMap.insert(std::string("\t") + TextSection);
+    SectionMap.insert(std::string("\t") + TAI->getTextSection());
   }
 }
 
@@ -2550,9 +2534,9 @@
   EOL("Dwarf End Module");
   
   // Standard sections final addresses.
-  Asm->SwitchToTextSection(TextSection, 0);
+  Asm->SwitchToTextSection(TAI->getTextSection(), 0);
   EmitLabel("text_end", 0);
-  Asm->SwitchToDataSection(DataSection, 0);
+  Asm->SwitchToDataSection(TAI->getDataSection(), 0);
   EmitLabel("data_end", 0);
   
   // End text sections.





From jlaskey at apple.com  Wed Sep  6 13:35:50 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Wed, 6 Sep 2006 13:35:50 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetAsmInfo.h
Message-ID: <200609061835.k86IZoYA031828@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/Target:

TargetAsmInfo.h added (r1.1)
---
Log message:

Separate target specifc asm properties from asm printers.


---
Diffs of the changes:  (+427 -0)

 TargetAsmInfo.h |  427 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 427 insertions(+)


Index: llvm/include/llvm/Target/TargetAsmInfo.h
diff -c /dev/null llvm/include/llvm/Target/TargetAsmInfo.h:1.1
*** /dev/null	Wed Sep  6 13:35:43 2006
--- llvm/include/llvm/Target/TargetAsmInfo.h	Wed Sep  6 13:35:33 2006
***************
*** 0 ****
--- 1,427 ----
+ //===-- llvm/Target/TargetAsmInfo.h - Asm info ------------------*- C++ -*-===//
+ //
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by James M. Laskey and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file contains a class to be used as the basis for target specific
+ // asm writers.  This class primarily takes care of global printing constants,
+ // which are used in very similar ways across all targets.
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ #ifndef LLVM_TARGET_ASM_INFO_H
+ #define LLVM_TARGET_ASM_INFO_H
+ 
+ #include "llvm/CodeGen/MachineFunctionPass.h"
+ #include "llvm/Support/DataTypes.h"
+ 
+ namespace llvm {
+ 
+   /// TargetAsmInfo - This class is intended to be used as a base class for asm
+   /// properties and features specific to the target.
+   class TargetAsmInfo {
+   
+   protected:
+     //===------------------------------------------------------------------===//
+     // Properties to be set by the target writer, used to configure asm printer.
+     // 
+     
+     /// TextSection - Section directive for standard text.
+     ///
+     const char *TextSection;              // Defaults to ".text".
+     
+     /// DataSection - Section directive for standard data.
+     ///
+     const char *DataSection;              // Defaults to ".data".
+     
+     /// AddressSize - Size of addresses used in file.
+     ///
+     unsigned AddressSize;                 // Defaults to 4.
+ 
+     /// NeedsSet - True if target asm can't compute addresses on data
+     /// directives.
+     bool NeedsSet;                        // Defaults to false.
+ 
+     /// CommentString - This indicates the comment character used by the
+     /// assembler.
+     const char *CommentString;            // Defaults to "#"
+ 
+     /// GlobalPrefix - If this is set to a non-empty string, it is prepended
+     /// onto all global symbols.  This is often used for "_" or ".".
+     const char *GlobalPrefix;             // Defaults to ""
+ 
+     /// PrivateGlobalPrefix - This prefix is used for globals like constant
+     /// pool entries that are completely private to the .o file and should not
+     /// have names in the .o file.  This is often "." or "L".
+     const char *PrivateGlobalPrefix;      // Defaults to "."
+     
+     /// GlobalVarAddrPrefix/Suffix - If these are nonempty, these strings
+     /// will enclose any GlobalVariable (that isn't a function)
+     ///
+     const char *GlobalVarAddrPrefix;      // Defaults to ""
+     const char *GlobalVarAddrSuffix;      // Defaults to ""
+ 
+     /// FunctionAddrPrefix/Suffix - If these are nonempty, these strings
+     /// will enclose any GlobalVariable that points to a function.
+     /// For example, this is used by the IA64 backend to materialize
+     /// function descriptors, by decorating the ".data8" object with the
+     /// \literal @fptr( ) \endliteral
+     /// link-relocation operator.
+     ///
+     const char *FunctionAddrPrefix;       // Defaults to ""
+     const char *FunctionAddrSuffix;       // Defaults to ""
+ 
+     /// InlineAsmStart/End - If these are nonempty, they contain a directive to
+     /// emit before and after an inline assembly statement.
+     const char *InlineAsmStart;           // Defaults to "#APP\n"
+     const char *InlineAsmEnd;             // Defaults to "#NO_APP\n"
+     
+     //===--- Data Emission Directives -------------------------------------===//
+ 
+     /// ZeroDirective - this should be set to the directive used to get some
+     /// number of zero bytes emitted to the current section.  Common cases are
+     /// "\t.zero\t" and "\t.space\t".  If this is set to null, the
+     /// Data*bitsDirective's will be used to emit zero bytes.
+     const char *ZeroDirective;            // Defaults to "\t.zero\t"
+     const char *ZeroDirectiveSuffix;      // Defaults to ""
+ 
+     /// AsciiDirective - This directive allows emission of an ascii string with
+     /// the standard C escape characters embedded into it.
+     const char *AsciiDirective;           // Defaults to "\t.ascii\t"
+     
+     /// AscizDirective - If not null, this allows for special handling of
+     /// zero terminated strings on this target.  This is commonly supported as
+     /// ".asciz".  If a target doesn't support this, it can be set to null.
+     const char *AscizDirective;           // Defaults to "\t.asciz\t"
+ 
+     /// DataDirectives - These directives are used to output some unit of
+     /// integer data to the current section.  If a data directive is set to
+     /// null, smaller data directives will be used to emit the large sizes.
+     const char *Data8bitsDirective;       // Defaults to "\t.byte\t"
+     const char *Data16bitsDirective;      // Defaults to "\t.short\t"
+     const char *Data32bitsDirective;      // Defaults to "\t.long\t"
+     const char *Data64bitsDirective;      // Defaults to "\t.quad\t"
+ 
+     //===--- Alignment Information ----------------------------------------===//
+ 
+     /// AlignDirective - The directive used to emit round up to an alignment
+     /// boundary.
+     ///
+     const char *AlignDirective;           // Defaults to "\t.align\t"
+ 
+     /// AlignmentIsInBytes - If this is true (the default) then the asmprinter
+     /// emits ".align N" directives, where N is the number of bytes to align to.
+     /// Otherwise, it emits ".align log2(N)", e.g. 3 to align to an 8 byte
+     /// boundary.
+     bool AlignmentIsInBytes;              // Defaults to true
+     
+     //===--- Section Switching Directives ---------------------------------===//
+     
+     /// SwitchToSectionDirective - This is the directive used when we want to
+     /// emit a global to an arbitrary section.  The section name is emited after
+     /// this.
+     const char *SwitchToSectionDirective; // Defaults to "\t.section\t"
+     
+     /// TextSectionStartSuffix - This is printed after each start of section
+     /// directive for text sections.
+     const char *TextSectionStartSuffix;   // Defaults to "".
+ 
+     /// DataSectionStartSuffix - This is printed after each start of section
+     /// directive for data sections.
+     const char *DataSectionStartSuffix;   // Defaults to "".
+     
+     /// SectionEndDirectiveSuffix - If non-null, the asm printer will close each
+     /// section with the section name and this suffix printed.
+     const char *SectionEndDirectiveSuffix;// Defaults to null.
+     
+     /// ConstantPoolSection - This is the section that we SwitchToSection right
+     /// before emitting the constant pool for a function.
+     const char *ConstantPoolSection;      // Defaults to "\t.section .rodata\n"
+ 
+     /// JumpTableDataSection - This is the section that we SwitchToSection right
+     /// before emitting the jump tables for a function when the relocation model
+     /// is not PIC.
+     const char *JumpTableDataSection;     // Defaults to "\t.section .rodata\n"
+     
+     /// JumpTableTextSection - This is the section that we SwitchToSection right
+     /// before emitting the jump tables for a function when the relocation model
+     /// is PIC.
+     const char *JumpTableTextSection;     // Defaults to "\t.text\n"
+     
+     /// StaticCtorsSection - This is the directive that is emitted to switch to
+     /// a section to emit the static constructor list.
+     /// Defaults to "\t.section .ctors,\"aw\", at progbits".
+     const char *StaticCtorsSection;
+ 
+     /// StaticDtorsSection - This is the directive that is emitted to switch to
+     /// a section to emit the static destructor list.
+     /// Defaults to "\t.section .dtors,\"aw\", at progbits".
+     const char *StaticDtorsSection;
+ 
+     /// FourByteConstantSection, EightByteConstantSection,
+     /// SixteenByteConstantSection - These are special sections where we place
+     /// 4-, 8-, and 16- byte constant literals.
+     const char *FourByteConstantSection;
+     const char *EightByteConstantSection;
+     const char *SixteenByteConstantSection;
+     
+     //===--- Global Variable Emission Directives --------------------------===//
+     
+     /// SetDirective - This is the name of a directive that can be used to tell
+     /// the assembler to set the value of a variable to some expression.
+     const char *SetDirective;             // Defaults to null.
+     
+     /// LCOMMDirective - This is the name of a directive (if supported) that can
+     /// be used to efficiently declare a local (internal) block of zero
+     /// initialized data in the .bss/.data section.  The syntax expected is:
+     /// \literal <LCOMMDirective> SYMBOLNAME LENGTHINBYTES, ALIGNMENT
+     /// \endliteral
+     const char *LCOMMDirective;           // Defaults to null.
+     
+     const char *COMMDirective;            // Defaults to "\t.comm\t".
+ 
+     /// COMMDirectiveTakesAlignment - True if COMMDirective take a third
+     /// argument that specifies the alignment of the declaration.
+     bool COMMDirectiveTakesAlignment;     // Defaults to true.
+     
+     /// HasDotTypeDotSizeDirective - True if the target has .type and .size
+     /// directives, this is true for most ELF targets.
+     bool HasDotTypeDotSizeDirective;      // Defaults to true.
+     
+     //===--- Dwarf Emission Directives -----------------------------------===//
+ 
+     /// HasLEB128 - True if target asm supports leb128 directives.
+     ///
+     bool HasLEB128; // Defaults to false.
+     
+     /// hasDotLoc - True if target asm supports .loc directives.
+     ///
+     bool HasDotLoc; // Defaults to false.
+     
+     /// HasDotFile - True if target asm supports .file directives.
+     ///
+     bool HasDotFile; // Defaults to false.
+     
+     /// DwarfAbbrevSection - Section directive for Dwarf abbrev.
+     ///
+     const char *DwarfAbbrevSection; // Defaults to ".debug_abbrev".
+ 
+     /// DwarfInfoSection - Section directive for Dwarf info.
+     ///
+     const char *DwarfInfoSection; // Defaults to ".debug_info".
+ 
+     /// DwarfLineSection - Section directive for Dwarf info.
+     ///
+     const char *DwarfLineSection; // Defaults to ".debug_line".
+     
+     /// DwarfFrameSection - Section directive for Dwarf info.
+     ///
+     const char *DwarfFrameSection; // Defaults to ".debug_frame".
+     
+     /// DwarfPubNamesSection - Section directive for Dwarf info.
+     ///
+     const char *DwarfPubNamesSection; // Defaults to ".debug_pubnames".
+     
+     /// DwarfPubTypesSection - Section directive for Dwarf info.
+     ///
+     const char *DwarfPubTypesSection; // Defaults to ".debug_pubtypes".
+     
+     /// DwarfStrSection - Section directive for Dwarf info.
+     ///
+     const char *DwarfStrSection; // Defaults to ".debug_str".
+ 
+     /// DwarfLocSection - Section directive for Dwarf info.
+     ///
+     const char *DwarfLocSection; // Defaults to ".debug_loc".
+ 
+     /// DwarfARangesSection - Section directive for Dwarf info.
+     ///
+     const char *DwarfARangesSection; // Defaults to ".debug_aranges".
+ 
+     /// DwarfRangesSection - Section directive for Dwarf info.
+     ///
+     const char *DwarfRangesSection; // Defaults to ".debug_ranges".
+ 
+     /// DwarfMacInfoSection - Section directive for Dwarf info.
+     ///
+     const char *DwarfMacInfoSection; // Defaults to ".debug_macinfo".
+ 
+ 
+   public:
+     TargetAsmInfo();
+         
+     //
+     // Accessors.
+     //
+     const char *getTextSection() const {
+       return TextSection;
+     }
+     const char *getDataSection() const {
+       return DataSection;
+     }
+     unsigned getAddressSize() const {
+       return AddressSize;
+     }
+     bool getNeedsSet() const {
+       return NeedsSet;
+     }
+     const char *getCommentString() const {
+       return CommentString;
+     }
+     const char *getGlobalPrefix() const {
+       return GlobalPrefix;
+     }
+     const char *getPrivateGlobalPrefix() const {
+       return PrivateGlobalPrefix;
+     }
+     const char *getGlobalVarAddrPrefix() const {
+       return GlobalVarAddrPrefix;
+     }
+     const char *getGlobalVarAddrSuffix() const {
+       return GlobalVarAddrSuffix;
+     }
+     const char *getFunctionAddrPrefix() const {
+       return FunctionAddrPrefix;
+     }
+     const char *getFunctionAddrSuffix() const {
+       return FunctionAddrSuffix;
+     }
+     const char *getInlineAsmStart() const {
+       return InlineAsmStart;
+     }
+     const char *getInlineAsmEnd() const {
+       return InlineAsmEnd;
+     }
+     const char *getZeroDirective() const {
+       return ZeroDirective;
+     }
+     const char *getZeroDirectiveSuffix() const {
+       return ZeroDirectiveSuffix;
+     }
+     const char *getAsciiDirective() const {
+       return AsciiDirective;
+     }
+     const char *getAscizDirective() const {
+       return AscizDirective;
+     }
+     const char *getData8bitsDirective() const {
+       return Data8bitsDirective;
+     }
+     const char *getData16bitsDirective() const {
+       return Data16bitsDirective;
+     }
+     const char *getData32bitsDirective() const {
+       return Data32bitsDirective;
+     }
+     const char *getData64bitsDirective() const {
+       return Data64bitsDirective;
+     }
+     const char *getAlignDirective() const {
+       return AlignDirective;
+     }
+     bool getAlignmentIsInBytes() const {
+       return AlignmentIsInBytes;
+     }
+     const char *getSwitchToSectionDirective() const {
+       return SwitchToSectionDirective;
+     }
+     const char *getTextSectionStartSuffix() const {
+       return TextSectionStartSuffix;
+     }
+     const char *getDataSectionStartSuffix() const {
+       return DataSectionStartSuffix;
+     }
+     const char *getSectionEndDirectiveSuffix() const {
+       return SectionEndDirectiveSuffix;
+     }
+     const char *getConstantPoolSection() const {
+       return ConstantPoolSection;
+     }
+     const char *getJumpTableDataSection() const {
+       return JumpTableDataSection;
+     }
+     const char *getJumpTableTextSection() const {
+       return JumpTableTextSection;
+     }
+     const char *getStaticCtorsSection() const {
+       return StaticCtorsSection;
+     }
+     const char *getStaticDtorsSection() const {
+       return StaticDtorsSection;
+     }
+     const char *getFourByteConstantSection() const {
+       return FourByteConstantSection;
+     }
+     const char *getEightByteConstantSection() const {
+       return EightByteConstantSection;
+     }
+     const char *getSixteenByteConstantSection() const {
+       return SixteenByteConstantSection;
+     }
+     const char *getSetDirective() const {
+       return SetDirective;
+     }
+     const char *getLCOMMDirective() const {
+       return LCOMMDirective;
+     }
+     const char *getCOMMDirective() const {
+       return COMMDirective;
+     }
+     bool getCOMMDirectiveTakesAlignment() const {
+       return COMMDirectiveTakesAlignment;
+     }
+     bool hasDotTypeDotSizeDirective() const {
+       return HasDotTypeDotSizeDirective;
+     }
+     bool hasLEB128() const {
+       return HasLEB128;
+     }
+     bool hasDotLoc() const {
+       return HasDotLoc;
+     }
+     bool hasDotFile() const {
+       return HasDotFile;
+     }
+     const char *getDwarfAbbrevSection() const {
+       return DwarfAbbrevSection;
+     }
+     const char *getDwarfInfoSection() const {
+       return DwarfInfoSection;
+     }
+     const char *getDwarfLineSection() const {
+       return DwarfLineSection;
+     }
+     const char *getDwarfFrameSection() const {
+       return DwarfFrameSection;
+     }
+     const char *getDwarfPubNamesSection() const {
+       return DwarfPubNamesSection;
+     }
+     const char *getDwarfPubTypesSection() const {
+       return DwarfPubTypesSection;
+     }
+     const char *getDwarfStrSection() const {
+       return DwarfStrSection;
+     }
+     const char *getDwarfLocSection() const {
+       return DwarfLocSection;
+     }
+     const char *getDwarfARangesSection() const {
+       return DwarfARangesSection;
+     }
+     const char *getDwarfRangesSection() const {
+       return DwarfRangesSection;
+     }
+     const char *getDwarfMacInfoSection() const {
+       return DwarfMacInfoSection;
+     }
+   };
+   
+ }
+ 
+ #endif
+ 





From jlaskey at apple.com  Wed Sep  6 13:35:50 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Wed, 6 Sep 2006 13:35:50 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/TargetAsmInfo.cpp
Message-ID: <200609061835.k86IZoUk031825@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target:

TargetAsmInfo.cpp added (r1.1)
---
Log message:

Separate target specifc asm properties from asm printers.


---
Diffs of the changes:  (+74 -0)

 TargetAsmInfo.cpp |   74 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 74 insertions(+)


Index: llvm/lib/Target/TargetAsmInfo.cpp
diff -c /dev/null llvm/lib/Target/TargetAsmInfo.cpp:1.1
*** /dev/null	Wed Sep  6 13:35:43 2006
--- llvm/lib/Target/TargetAsmInfo.cpp	Wed Sep  6 13:35:33 2006
***************
*** 0 ****
--- 1,74 ----
+ //===-- TargetData.cpp - Data size & alignment routines --------------------==//
+ //
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by James M. Laskey and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file defines target asm properties related what form asm statements
+ // should take.
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ #include "llvm/Target/TargetAsmInfo.h"
+ 
+ using namespace llvm;
+ 
+ TargetAsmInfo::TargetAsmInfo() :
+   TextSection(".text"),
+   DataSection(".data"),
+   AddressSize(4),
+   NeedsSet(false),
+   CommentString("#"),
+   GlobalPrefix(""),
+   PrivateGlobalPrefix("."),
+   GlobalVarAddrPrefix(""),
+   GlobalVarAddrSuffix(""),
+   FunctionAddrPrefix(""),
+   FunctionAddrSuffix(""),
+   InlineAsmStart("#APP"),
+   InlineAsmEnd("#NO_APP"),
+   ZeroDirective("\t.zero\t"),
+   ZeroDirectiveSuffix(0),
+   AsciiDirective("\t.ascii\t"),
+   AscizDirective("\t.asciz\t"),
+   Data8bitsDirective("\t.byte\t"),
+   Data16bitsDirective("\t.short\t"),
+   Data32bitsDirective("\t.long\t"),
+   Data64bitsDirective("\t.quad\t"),
+   AlignDirective("\t.align\t"),
+   AlignmentIsInBytes(true),
+   SwitchToSectionDirective("\t.section\t"),
+   TextSectionStartSuffix(""),
+   DataSectionStartSuffix(""),
+   SectionEndDirectiveSuffix(0),
+   ConstantPoolSection("\t.section .rodata\n"),
+   JumpTableDataSection("\t.section .rodata\n"),
+   JumpTableTextSection("\t.text\n"),
+   StaticCtorsSection("\t.section .ctors,\"aw\", at progbits"),
+   StaticDtorsSection("\t.section .dtors,\"aw\", at progbits"),
+   FourByteConstantSection(0),
+   EightByteConstantSection(0),
+   SixteenByteConstantSection(0),
+   SetDirective(0),
+   LCOMMDirective(0),
+   COMMDirective("\t.comm\t"),
+   COMMDirectiveTakesAlignment(true),
+   HasDotTypeDotSizeDirective(true),
+   HasLEB128(false),
+   HasDotLoc(false),
+   HasDotFile(false),
+   DwarfAbbrevSection(".debug_abbrev"),
+   DwarfInfoSection(".debug_info"),
+   DwarfLineSection(".debug_line"),
+   DwarfFrameSection(".debug_frame"),
+   DwarfPubNamesSection(".debug_pubnames"),
+   DwarfPubTypesSection(".debug_pubtypes"),
+   DwarfStrSection(".debug_str"),
+   DwarfLocSection(".debug_loc"),
+   DwarfARangesSection(".debug_aranges"),
+   DwarfRangesSection(".debug_ranges"),
+   DwarfMacInfoSection(".debug_macinfo")
+ {}





From jlaskey at apple.com  Wed Sep  6 13:39:12 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Wed, 6 Sep 2006 13:39:12 -0500
Subject: [llvm-commits] CVS: llvm/Xcode/LLVM.xcodeproj/project.pbxproj
Message-ID: <200609061839.k86IdCLS031887@zion.cs.uiuc.edu>



Changes in directory llvm/Xcode/LLVM.xcodeproj:

project.pbxproj updated: 1.22 -> 1.23
---
Log message:

Update project with new files.


---
Diffs of the changes:  (+5 -3)

 project.pbxproj |    8 +++++---
 1 files changed, 5 insertions(+), 3 deletions(-)


Index: llvm/Xcode/LLVM.xcodeproj/project.pbxproj
diff -u llvm/Xcode/LLVM.xcodeproj/project.pbxproj:1.22 llvm/Xcode/LLVM.xcodeproj/project.pbxproj:1.23
--- llvm/Xcode/LLVM.xcodeproj/project.pbxproj:1.22	Fri Aug 25 09:16:49 2006
+++ llvm/Xcode/LLVM.xcodeproj/project.pbxproj	Wed Sep  6 13:38:54 2006
@@ -41,6 +41,8 @@
 /* Begin PBXFileReference section */
 		CF1ACC9709C9DE4400D3C5EB /* IntrinsicInst.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; name = IntrinsicInst.cpp; path = ../lib/VMCore/IntrinsicInst.cpp; sourceTree = "<group>"; };
 		CF26835B09178F5500C5F253 /* TargetInstrItineraries.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = TargetInstrItineraries.h; sourceTree = "<group>"; };
+		CF47BD380AAF40BC00A8B13E /* TargetAsmInfo.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = TargetAsmInfo.h; sourceTree = "<group>"; };
+		CF47BD860AAF487E00A8B13E /* TargetAsmInfo.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; path = TargetAsmInfo.cpp; sourceTree = "<group>"; };
 		CF490D14090541D30072DB1C /* TargetSchedule.td */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = text; path = TargetSchedule.td; sourceTree = "<group>"; };
 		CF490D15090541D30072DB1C /* TargetSelectionDAG.td */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = text; path = TargetSelectionDAG.td; sourceTree = "<group>"; };
 		CF490E2F0907BBF80072DB1C /* SubtargetEmitter.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = SubtargetEmitter.h; sourceTree = "<group>"; };
@@ -893,7 +895,6 @@
 		DE8170AA08CFB44D0093BDEF /* TableGen.cpp */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.cpp.cpp; path = TableGen.cpp; sourceTree = "<group>"; };
 		DE8170AB08CFB44D0093BDEF /* TableGenBackend.cpp */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.cpp.cpp; path = TableGenBackend.cpp; sourceTree = "<group>"; };
 		DE8170AC08CFB44D0093BDEF /* TableGenBackend.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = TableGenBackend.h; sourceTree = "<group>"; };
-		DEFAB19C0959E97F00E0AB42 /* DwarfWriter.cpp */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.cpp.cpp; name = DwarfWriter.cpp; path = ../lib/CodeGen/DwarfWriter.cpp; sourceTree = SOURCE_ROOT; };
 		DEFAB19D0959E9A100E0AB42 /* DwarfWriter.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; name = DwarfWriter.h; path = ../include/llvm/CodeGen/DwarfWriter.h; sourceTree = SOURCE_ROOT; };
 /* End PBXFileReference section */
 
@@ -1113,7 +1114,6 @@
 				DE66ED3F08ABEC2A00323D32 /* AsmPrinter.cpp */,
 				DE66ED4008ABEC2A00323D32 /* BranchFolding.cpp */,
 				CFC244570959DEF2009F8C47 /* DwarfWriter.cpp */,
-				DEFAB19C0959E97F00E0AB42 /* DwarfWriter.cpp */,
 				DE66ED6F08ABEC2B00323D32 /* ELFWriter.cpp */,
 				DE66ED7008ABEC2B00323D32 /* IntrinsicLowering.cpp */,
 				DE66ED7108ABEC2B00323D32 /* LiveInterval.cpp */,
@@ -1338,6 +1338,7 @@
 		DE66EE9608ABEE5D00323D32 /* lib/Target */ = {
 			isa = PBXGroup;
 			children = (
+				CF47BD860AAF487E00A8B13E /* TargetAsmInfo.cpp */,
 				DE66EE9708ABEE5D00323D32 /* Alpha */,
 				CF9720380A9F3BBC002CEEDD /* ARM */,
 				DE66EEC908ABEE5E00323D32 /* CBackend */,
@@ -1999,6 +2000,7 @@
 			children = (
 				DE66F2A008ABF03200323D32 /* MRegisterInfo.h */,
 				CF9BCD0808C74DE0001E7011 /* SubtargetFeature.h */,
+				CF47BD380AAF40BC00A8B13E /* TargetAsmInfo.h */,
 				DE66F2A108ABF03200323D32 /* TargetData.h */,
 				DE66F2A208ABF03200323D32 /* TargetFrameInfo.h */,
 				DE66F2A308ABF03200323D32 /* TargetInstrInfo.h */,
@@ -2287,7 +2289,7 @@
 /* Begin PBXLegacyTarget section */
 		CF0329B608D1BE110030FD33 /* LLVM lib */ = {
 			isa = PBXLegacyTarget;
-			buildArgumentsString = "$(ACTION) -j 4";
+			buildArgumentsString = "$(ACTION) -j4 ";
 			buildConfigurationList = CF0329B708D1BE530030FD33 /* Build configuration list for PBXLegacyTarget "LLVM lib" */;
 			buildPhases = (
 			);





From isanbard at gmail.com  Wed Sep  6 13:42:55 2006
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 6 Sep 2006 13:42:55 -0500
Subject: [llvm-commits] CVS: llvm/docs/CodeGenerator.html
Message-ID: <200609061842.k86Igth8032008@zion.cs.uiuc.edu>



Changes in directory llvm/docs:

CodeGenerator.html updated: 1.36 -> 1.37
---
Log message:

Cleaned up some of the grammar in the Live Intervals section. Removed the
huge honking FIXME comment. I'll address the "Live Intervals Analysis"
section soon.


---
Diffs of the changes:  (+36 -146)

 CodeGenerator.html |  182 ++++++++++-------------------------------------------
 1 files changed, 36 insertions(+), 146 deletions(-)


Index: llvm/docs/CodeGenerator.html
diff -u llvm/docs/CodeGenerator.html:1.36 llvm/docs/CodeGenerator.html:1.37
--- llvm/docs/CodeGenerator.html:1.36	Mon Sep  4 18:35:52 2006
+++ llvm/docs/CodeGenerator.html	Wed Sep  6 13:42:41 2006
@@ -58,9 +58,10 @@
       <li><a href="#selectiondag_future">Future directions for the
                                          SelectionDAG</a></li>
       </ul></li>
-     <li><a href="#liveinterval_analysis">Live Interval Analysis</a>
+     <li><a href="#liveintervals">Live Intervals</a>
        <ul>
        <li><a href="#livevariable_analysis">Live Variable Analysis</a></li>
+       <li><a href="#liveintervals_analysis">Live Intervals Analysis</a></li>
        </ul></li>
     <li><a href="#regalloc">Register Allocation</a>
       <ul>
@@ -1160,16 +1161,16 @@
 
 <!-- ======================================================================= -->
 <div class="doc_subsection">
-  <a name="liveinterval_analysis">Live Interval Analysis</a>
+  <a name="liveintervals">Live Intervals</a>
 </div>
 
 <div class="doc_text">
 
-<p>Live Interval Analysis identifies the ranges where a variable is <i>live</i>.
-It's used by the <a href="#regalloc">register allocator pass</a> to determine
-if two or more virtual registers which require the same register are live at
-the same point in the program (conflict). When this situation occurs, one
-virtual register must be <i>spilt</i>.</p>
+<p>Live Intervals are the ranges (intervals) where a variable is <i>live</i>.
+They are used by some <a href="#regalloc">register allocator</a> passes to
+determine if two or more virtual registers which require the same register are
+live at the same point in the program (conflict).  When this situation occurs,
+one virtual register must be <i>spilled</i>.</p>
 
 </div>
 
@@ -1180,30 +1181,35 @@
 
 <div class="doc_text">
 
-<p>The first step to determining the live intervals of variables is to
+<p>The first step in determining the live intervals of variables is to
 calculate the set of registers that are immediately dead after the
-instruction (i.e., the instruction calculates the value, but it is never
-used) and the set of registers that are used by the instruction, but are
-never used after the instruction (i.e., they are killed). Live variable
-information is computed for each <i>virtual</i> and <i>register
-allocatable</i> physical register in the function.  LLVM assumes that
-physical registers are only live within a single basic block.  This allows
-it to do a single, local analysis to resolve physical register lifetimes in
-each basic block. If a physical register is not register allocatable (e.g.,
+instruction (i.e., the instruction calculates the value, but it is
+never used) and the set of registers that are used by the instruction,
+but are never used after the instruction (i.e., they are killed). Live
+variable information is computed for each <i>virtual</i> and
+<i>register allocatable</i> physical register in the function.  This
+is done in a very efficient manner because it uses SSA to sparsely
+computer lifetime information for virtual registers (which are in SSA
+form) and only has to track physical registers within a block.  Before
+register allocation, LLVM can assume that physical registers are only
+live within a single basic block.  This allows it to do a single,
+local analysis to resolve physical register lifetimes within each
+basic block. If a physical register is not register allocatable (e.g.,
 a stack pointer or condition codes), it is not tracked.</p>
 
 <p>Physical registers may be live in to or out of a function. Live in values
-are typically arguments in register. Live out values are typically return
+are typically arguments in registers. Live out values are typically return
 values in registers. Live in values are marked as such, and are given a dummy
 "defining" instruction during live interval analysis. If the last basic block
-of a function is a <tt>return</tt>, then it's marked as using all live-out
+of a function is a <tt>return</tt>, then it's marked as using all live out
 values in the function.</p>
 
 <p><tt>PHI</tt> nodes need to be handled specially, because the calculation
 of the live variable information from a depth first traversal of the CFG of
-the function won't guarantee that a virtual register is defined before it's
-used. When a <tt>PHI</tt> node is encounted, only the definition is
-handled, because the uses will be handled in other basic blocks.</p>
+the function won't guarantee that a virtual register used by the <tt>PHI</tt>
+node is defined before it's used. When a <tt>PHI</tt> node is encounted, only
+the definition is handled, because the uses will be handled in other basic
+blocks.</p>
 
 <p>For each <tt>PHI</tt> node of the current basic block, we simulate an
 assignment at the end of the current basic block and traverse the successor
@@ -1215,132 +1221,16 @@
 
 </div>
 
-<!-- FIXME:
+<!-- _______________________________________________________________________ -->
+<div class="doc_subsubsection">
+  <a name="liveintervals_analysis">Live Intervals Analysis</a>
+</div>
 
-A. General Overview
-B. Describe Default RA (Linear Scan)
-   1. LiveVariable Analysis
-      a. All physical register references presumed dead across BBs
-      b. Mark live-in regs as live-in
-      c. Calculate LV info in DFS order
-         1) We'll see def of vreg before its uses
-         2) PHI nodes are treated specially
-            a) Only handle its def
-            b) Uses handled in other BBs
-         3) Handle all uses and defs
-            a) Handle implicit preg uses
-               (1) "TargetInstrDescriptor" from "TargetInstructionInfo"
-            b) Handle explicit preg and vreg uses
-            c) Handle implicit preg defs
-               (1) "TargetInstrDescriptor" from "TargetInstructionInfo"
-            d) Handle explicit preg and vreg defs
-         4) Use of vreg marks it killed (last use in BB)
-            a) Updates (expands) live range
-            b) Marks vreg as alive in dominating blocks
-         5) Use of preg updates info and used tables
-         6) Def of vreg defaults to "dead"
-            a) Expanded later (see B.1.c.4)
-         7) Def of preg updates info, used, RegsKilled, and RegsDead tables.
-         8) Handle virt assigns from PHI nodes at the bottom of the BB
-            a) If successor block has PHI nodes
-               (1) Simulate an assignment at the end of current BB
-                   (i.e., mark it as alive in current BB)
-         9) If last block is a "return"
-            a) Mark it as using all live-out values
-         10) Kill all pregs available at the end of the BB
-      d. Update "RegistersDead" and "RegistersKilled"
-         1) RegistersDead - This map keeps track of all of the registers that
-            are dead immediately after an instruction executes, which are not
-            dead after the operands are evaluated.  In practice, this only
-            contains registers which are defined by an instruction, but never
-            used.
-         2) RegistersKilled - This map keeps track of all of the registers that
-            are dead immediately after an instruction reads its operands.  If an
-            instruction does not have an entry in this map, it kills no
-            registers.
-   2. LiveInterval Analysis
-      a. Use LV pass to conservatively compute live intervals for vregs and pregs
-      b. For some ordering of the machine instrs [1,N], a live interval is an
-         interval [i,j) where 1 <= i <= j < N for which a variable is live
-      c. Function has live ins
-         1) Insert dummy instr at beginning
-         2) Pretend dummy instr "defines" values
-      d. Number each machine instruction -- depth-first order
-         1) An interval [i, j) == Live interval for reg v if there is no
-            instr with num j' > j s.t. v is live at j' and there is no instr
-            with number i' < i s.t. v is live at i'
-         2) Intervals can have holes: [1,20), [50,65), [1000,1001)
-      e. Handle line-in values
-      f. Compute live intervals
-         1) Each live range is assigned a value num within the live interval
-         2) vreg
-            a) May be defined multiple times (due to phi and 2-addr elimination)
-            b) Live only within defining BB
-               (1) Single kill after def in BB
-            c) Lives to end of defining BB, potentially across some BBs
-               (1) Add range that goes from def to end of defining BB
-               (2) Iterate over all BBs that the var is completely live in
-                   (a) add [instrIndex(begin), InstrIndex(end)+4) to LI
-               (3) Vreg is live from start of any killing block to 'use'
-            d) If seeing vreg again (because of phi or 2-addr elimination)
-               (1) If 2-addr elim, then vreg is 1st op and a def-and-use
-                   (a) Didn't realize there are 2 values in LI
-                   (b) Need to take LR that defs vreg and split it into 2 vals
-                       (1) Delete initial value (from first def to redef)
-                       (2) Get new value num (#1)
-                       (3) Value#0 is now defined by the 2-addr instr
-                       (4) Add new LR which replaces the range for input copy
-               (2) Else phi-elimination
-                   (a) If first redef of vreg, change LR in PHI block to be
-                       a different Value Number
-                   (b) Each variable def is only live until the end of the BB
-         3) preg
-            a) Cannot be live across BB
-            b) Lifetime must end somewhere in its defining BB
-            c) Dead at def instr, if not used after def
-               (1) Interval: [defSlot(def), defSlot(def) + 1)
-            d) Killed by subsequent instr, if not dead on def
-               (1) Interval: [defSlot(def), useSlot(kill) + 1)
-            e) If neither, then it's live-in to func and never used
-               (1) Interval: [start, start + 1)
-      e. Join intervals
-      f. Compute spill weights
-      g. Coalesce vregs
-      h. Remove identity moves
-   3. Linear Scan RA
-      a. 
-
-
-  /// VarInfo - This represents the regions where a virtual register is live in
-  /// the program.  We represent this with three different pieces of
-  /// information: the instruction that uniquely defines the value, the set of
-  /// blocks the instruction is live into and live out of, and the set of 
-  /// non-phi instructions that are the last users of the value.
-  ///
-  /// In the common case where a value is defined and killed in the same block,
-  /// DefInst is the defining inst, there is one killing instruction, and 
-  /// AliveBlocks is empty.
-  ///
-  /// Otherwise, the value is live out of the block.  If the value is live
-  /// across any blocks, these blocks are listed in AliveBlocks.  Blocks where
-  /// the liveness range ends are not included in AliveBlocks, instead being
-  /// captured by the Kills set.  In these blocks, the value is live into the
-  /// block (unless the value is defined and killed in the same block) and lives
-  /// until the specified instruction.  Note that there cannot ever be a value
-  /// whose Kills set contains two instructions from the same basic block.
-  ///
-  /// PHI nodes complicate things a bit.  If a PHI node is the last user of a
-  /// value in one of its predecessor blocks, it is not listed in the kills set,
-  /// but does include the predecessor block in the AliveBlocks set (unless that
-  /// block also defines the value).  This leads to the (perfectly sensical)
-  /// situation where a value is defined in a block, and the last use is a phi
-  /// node in the successor.  In this case, DefInst will be the defining
-  /// instruction, AliveBlocks is empty (the value is not live across any 
-  /// blocks) and Kills is empty (phi nodes are not included).  This is sensical
-  /// because the value must be live to the end of the block, but is not live in
-  /// any successor blocks.
+<div class="doc_text">
+<p>To Be Written</p>
+</ol>
 
- -->
+</div>
 
 <!-- ======================================================================= -->
 <div class="doc_subsection">
@@ -1812,7 +1702,7 @@
 
   <a href="mailto:sabre at nondot.org">Chris Lattner</a><br>
   <a href="http://llvm.org">The LLVM Compiler Infrastructure</a><br>
-  Last modified: $Date: 2006/09/04 23:35:52 $
+  Last modified: $Date: 2006/09/06 18:42:41 $
 </address>
 
 </body>





From dpatel at apple.com  Wed Sep  6 13:50:41 2006
From: dpatel at apple.com (Devang Patel)
Date: Wed, 6 Sep 2006 13:50:41 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/LinkTimeOptimizer.h
Message-ID: <200609061850.k86IofJt032191@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm:

LinkTimeOptimizer.h updated: 1.5 -> 1.6
---
Log message:

Keep track of all modules crated using a name to module map.
Add private member function getMoudle().


---
Diffs of the changes:  (+6 -0)

 LinkTimeOptimizer.h |    6 ++++++
 1 files changed, 6 insertions(+)


Index: llvm/include/llvm/LinkTimeOptimizer.h
diff -u llvm/include/llvm/LinkTimeOptimizer.h:1.5 llvm/include/llvm/LinkTimeOptimizer.h:1.6
--- llvm/include/llvm/LinkTimeOptimizer.h:1.5	Tue Sep  5 19:28:22 2006
+++ llvm/include/llvm/LinkTimeOptimizer.h	Wed Sep  6 13:50:26 2006
@@ -83,6 +83,8 @@
   public:
     typedef hash_map<const char*, LLVMSymbol*, hash<const char*>, 
                      string_compare> NameToSymbolMap;
+    typedef hash_map<const char*, Module*, hash<const char*>, 
+                     string_compare> NameToModuleMap;
 
     enum LTOStatus readLLVMObjectFile(const std::string &InputFilename,
                                       NameToSymbolMap &symbols,
@@ -92,8 +94,12 @@
                                    std::string &targetTriple);
 
   private:
+    Module *getModule (const std::string &InputFilename);
+
+  private:
     std::vector<Module *> modules;
     NameToSymbolMap allSymbols;
+    NameToModuleMap allModules;
   };
 
 } // End llvm namespace





From dpatel at apple.com  Wed Sep  6 13:50:42 2006
From: dpatel at apple.com (Devang Patel)
Date: Wed, 6 Sep 2006 13:50:42 -0500
Subject: [llvm-commits] CVS: llvm/tools/lto/lto.cpp
Message-ID: <200609061850.k86IogmY032196@zion.cs.uiuc.edu>



Changes in directory llvm/tools/lto:

lto.cpp updated: 1.10 -> 1.11
---
Log message:

Keep track of all modules crated using a name to module map.
Add private member function getMoudle().


---
Diffs of the changes:  (+18 -1)

 lto.cpp |   19 ++++++++++++++++++-
 1 files changed, 18 insertions(+), 1 deletion(-)


Index: llvm/tools/lto/lto.cpp
diff -u llvm/tools/lto/lto.cpp:1.10 llvm/tools/lto/lto.cpp:1.11
--- llvm/tools/lto/lto.cpp:1.10	Tue Sep  5 19:45:52 2006
+++ llvm/tools/lto/lto.cpp	Wed Sep  6 13:50:26 2006
@@ -99,6 +99,23 @@
       findExternalRefs(c->getOperand(i), references, mangler);
 }
 
+/// InputFilename is a LLVM bytecode file. If Module with InputFilename is
+/// available then return it. Otherwise parseInputFilename.
+Module *
+LinkTimeOptimizer::getModule(const std::string &InputFilename)
+{
+  Module *m = NULL;
+
+  NameToModuleMap::iterator pos = allModules.find(InputFilename.c_str());
+  if (pos != allModules.end())
+    m = allModules[InputFilename.c_str()];
+  else {
+    m = ParseBytecodeFile(InputFilename);
+    allModules[InputFilename.c_str()] = m;
+  }
+  return m;
+}
+
 /// InputFilename is a LLVM bytecode file. Read it using bytecode reader.
 /// Collect global functions and symbol names in symbols vector.
 /// Collect external references in references vector.
@@ -108,7 +125,7 @@
                                       NameToSymbolMap &symbols,
                                       std::set<std::string> &references)
 {
-  Module *m = ParseBytecodeFile(InputFilename);
+  Module *m = getModule(InputFilename);
   if (!m)
     return LTO_READ_FAILURE;
 





From jlaskey at apple.com  Wed Sep  6 14:21:55 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Wed, 6 Sep 2006 14:21:55 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/TargetAsmInfo.cpp
Message-ID: <200609061921.k86JLtZU000311@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target:

TargetAsmInfo.cpp updated: 1.1 -> 1.2
---
Log message:

Oops - forgot to update banner.



---
Diffs of the changes:  (+1 -1)

 TargetAsmInfo.cpp |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/TargetAsmInfo.cpp
diff -u llvm/lib/Target/TargetAsmInfo.cpp:1.1 llvm/lib/Target/TargetAsmInfo.cpp:1.2
--- llvm/lib/Target/TargetAsmInfo.cpp:1.1	Wed Sep  6 13:35:33 2006
+++ llvm/lib/Target/TargetAsmInfo.cpp	Wed Sep  6 14:21:41 2006
@@ -1,4 +1,4 @@
-//===-- TargetData.cpp - Data size & alignment routines --------------------==//
+//===-- TargetAsmInfo.cpp - Asm Info ---------------------------------------==//
 //
 //                     The LLVM Compiler Infrastructure
 //





From dpatel at apple.com  Wed Sep  6 15:16:43 2006
From: dpatel at apple.com (Devang Patel)
Date: Wed, 6 Sep 2006 15:16:43 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/LinkTimeOptimizer.h
Message-ID: <200609062016.k86KGhsb001146@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm:

LinkTimeOptimizer.h updated: 1.6 -> 1.7
---
Log message:

Add getTargetTriple() that linker can use to query target architecture.


---
Diffs of the changes:  (+1 -0)

 LinkTimeOptimizer.h |    1 +
 1 files changed, 1 insertion(+)


Index: llvm/include/llvm/LinkTimeOptimizer.h
diff -u llvm/include/llvm/LinkTimeOptimizer.h:1.6 llvm/include/llvm/LinkTimeOptimizer.h:1.7
--- llvm/include/llvm/LinkTimeOptimizer.h:1.6	Wed Sep  6 13:50:26 2006
+++ llvm/include/llvm/LinkTimeOptimizer.h	Wed Sep  6 15:16:28 2006
@@ -92,6 +92,7 @@
     enum LTOStatus optimizeModules(const std::string &OutputFilename,
                                    std::vector<const char*> &exportList,
                                    std::string &targetTriple);
+    void getTargetTriple(const std::string &InputFilename, std::string &targetTriple);
 
   private:
     Module *getModule (const std::string &InputFilename);





From dpatel at apple.com  Wed Sep  6 15:16:43 2006
From: dpatel at apple.com (Devang Patel)
Date: Wed, 6 Sep 2006 15:16:43 -0500
Subject: [llvm-commits] CVS: llvm/tools/lto/lto.cpp
Message-ID: <200609062016.k86KGhpc001151@zion.cs.uiuc.edu>



Changes in directory llvm/tools/lto:

lto.cpp updated: 1.11 -> 1.12
---
Log message:

Add getTargetTriple() that linker can use to query target architecture.


---
Diffs of the changes:  (+11 -0)

 lto.cpp |   11 +++++++++++
 1 files changed, 11 insertions(+)


Index: llvm/tools/lto/lto.cpp
diff -u llvm/tools/lto/lto.cpp:1.11 llvm/tools/lto/lto.cpp:1.12
--- llvm/tools/lto/lto.cpp:1.11	Wed Sep  6 13:50:26 2006
+++ llvm/tools/lto/lto.cpp	Wed Sep  6 15:16:28 2006
@@ -116,6 +116,17 @@
   return m;
 }
 
+/// InputFilename is a LLVM bytecode file. Reade this bytecode file and 
+/// set corresponding target triplet string.
+void
+LinkTimeOptimizer::getTargetTriple(const std::string &InputFilename, 
+				   std::string &targetTriple)
+{
+  Module *m = getModule(InputFilename);
+  if (m)
+    targetTriple = m->getTargetTriple();
+}
+
 /// InputFilename is a LLVM bytecode file. Read it using bytecode reader.
 /// Collect global functions and symbol names in symbols vector.
 /// Collect external references in references vector.





From dpatel at apple.com  Wed Sep  6 15:23:10 2006
From: dpatel at apple.com (Devang Patel)
Date: Wed, 6 Sep 2006 15:23:10 -0500
Subject: [llvm-commits] CVS: llvm/docs/LinkTimeOptimization.html
Message-ID: <200609062023.k86KNAAZ001320@zion.cs.uiuc.edu>



Changes in directory llvm/docs:

LinkTimeOptimization.html updated: 1.6 -> 1.7
---
Log message:

Document getTargetTriple().


---
Diffs of the changes:  (+12 -1)

 LinkTimeOptimization.html |   13 ++++++++++++-
 1 files changed, 12 insertions(+), 1 deletion(-)


Index: llvm/docs/LinkTimeOptimization.html
diff -u llvm/docs/LinkTimeOptimization.html:1.6 llvm/docs/LinkTimeOptimization.html:1.7
--- llvm/docs/LinkTimeOptimization.html:1.6	Mon Aug 14 15:07:50 2006
+++ llvm/docs/LinkTimeOptimization.html	Wed Sep  6 15:22:55 2006
@@ -29,6 +29,7 @@
     <li><a href="#llvmsymbol">LLVMSymbol</a></li>
     <li><a href="#readllvmobjectfile">readLLVMObjectFile()</a></li>
     <li><a href="#optimizemodules">optimizeModules()</a></li>
+    <li><a href="#gettargettriple">getTargetTriple()</a></li>
   </ul></li>
   <li><a href="#debug">Debugging Information</a></li>
 </ul>
@@ -326,6 +327,16 @@
   linker.</p>
 </div>
 
+<!-- ======================================================================= -->
+<div class="doc_subsection">
+  <a name="gettargettriple">getTargetTriple()</a>
+</div>
+
+<div class="doc_text">
+  <p>The linker may use <tt>getTargetTriple()</tt> to query target architecture
+  while validating LLVM bytecode file.</p>
+</div>
+
 <!-- *********************************************************************** -->
 <div class="doc_section">
   <a name="debug">Debugging Information</a>
@@ -349,7 +360,7 @@
 
   Devang Patel<br>
   <a href="http://llvm.org">LLVM Compiler Infrastructure</a><br>
-  Last modified: $Date: 2006/08/14 20:07:50 $
+  Last modified: $Date: 2006/09/06 20:22:55 $
 </address>
 
 </body>





From evan.cheng at apple.com  Wed Sep  6 15:24:28 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 6 Sep 2006 15:24:28 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86CodeEmitter.cpp
Message-ID: <200609062024.k86KOSqo001353@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86CodeEmitter.cpp updated: 1.115 -> 1.116
---
Log message:

Variable ops instructions may ignore the last few operands for code emission.

---
Diffs of the changes:  (+3 -1)

 X86CodeEmitter.cpp |    4 +++-
 1 files changed, 3 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/X86/X86CodeEmitter.cpp
diff -u llvm/lib/Target/X86/X86CodeEmitter.cpp:1.115 llvm/lib/Target/X86/X86CodeEmitter.cpp:1.116
--- llvm/lib/Target/X86/X86CodeEmitter.cpp:1.115	Mon Sep  4 21:52:35 2006
+++ llvm/lib/Target/X86/X86CodeEmitter.cpp	Wed Sep  6 15:24:14 2006
@@ -526,5 +526,7 @@
     ++CurOp;
     break;
   }
-  assert(CurOp == MI.getNumOperands() && "Unknown encoding!");
+
+  if ((Desc.Flags & M_VARIABLE_OPS) == 0)
+    assert(CurOp == MI.getNumOperands() && "Unknown encoding!");
 }





From evan.cheng at apple.com  Wed Sep  6 15:33:00 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 6 Sep 2006 15:33:00 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86CodeEmitter.cpp
Message-ID: <200609062033.k86KX0p5001492@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86CodeEmitter.cpp updated: 1.116 -> 1.117
---
Log message:

Watch out for variable_ops instructions.

---
Diffs of the changes:  (+1 -1)

 X86CodeEmitter.cpp |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/X86/X86CodeEmitter.cpp
diff -u llvm/lib/Target/X86/X86CodeEmitter.cpp:1.116 llvm/lib/Target/X86/X86CodeEmitter.cpp:1.117
--- llvm/lib/Target/X86/X86CodeEmitter.cpp:1.116	Wed Sep  6 15:24:14 2006
+++ llvm/lib/Target/X86/X86CodeEmitter.cpp	Wed Sep  6 15:32:45 2006
@@ -493,7 +493,7 @@
     emitRegModRMByte(MI.getOperand(CurOp++).getReg(),
                      (Desc.TSFlags & X86II::FormMask)-X86II::MRM0r);
 
-    if (CurOp != MI.getNumOperands())
+    if (CurOp != MI.getNumOperands() && MI.getOperand(CurOp).isImmediate())
       emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
     break;
 





From isanbard at gmail.com  Wed Sep  6 15:41:43 2006
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 6 Sep 2006 15:41:43 -0500
Subject: [llvm-commits] CVS: llvm-test/External/SPEC/CFP2006/470.lbm/Makefile
Message-ID: <200609062041.k86KfhQa001722@zion.cs.uiuc.edu>



Changes in directory llvm-test/External/SPEC/CFP2006/470.lbm:

Makefile updated: 1.1 -> 1.2
---
Log message:

Modified Makefiles to handle multiple directories.


---
Diffs of the changes:  (+1 -1)

 Makefile |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm-test/External/SPEC/CFP2006/470.lbm/Makefile
diff -u llvm-test/External/SPEC/CFP2006/470.lbm/Makefile:1.1 llvm-test/External/SPEC/CFP2006/470.lbm/Makefile:1.2
--- llvm-test/External/SPEC/CFP2006/470.lbm/Makefile:1.1	Fri Sep  1 18:27:13 2006
+++ llvm-test/External/SPEC/CFP2006/470.lbm/Makefile	Wed Sep  6 15:41:12 2006
@@ -10,5 +10,5 @@
 
 include ../../Makefile.spec2006
 
-RUN_OPTIONS     := `cat $(REF_IN_DIR)lbm.in`
+RUN_OPTIONS      = `cat $(REF_IN_DIR)lbm.in`
 STDOUT_FILENAME := lbm.out





From isanbard at gmail.com  Wed Sep  6 15:41:43 2006
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 6 Sep 2006 15:41:43 -0500
Subject: [llvm-commits] CVS: llvm-test/External/SPEC/CFP2006/481.wrf/Makefile
Message-ID: <200609062041.k86KfhxX001700@zion.cs.uiuc.edu>



Changes in directory llvm-test/External/SPEC/CFP2006/481.wrf:

Makefile updated: 1.1 -> 1.2
---
Log message:

Modified Makefiles to handle multiple directories.


---
Diffs of the changes:  (+56 -7)

 Makefile |   63 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++-------
 1 files changed, 56 insertions(+), 7 deletions(-)


Index: llvm-test/External/SPEC/CFP2006/481.wrf/Makefile
diff -u llvm-test/External/SPEC/CFP2006/481.wrf/Makefile:1.1 llvm-test/External/SPEC/CFP2006/481.wrf/Makefile:1.2
--- llvm-test/External/SPEC/CFP2006/481.wrf/Makefile:1.1	Fri Sep  1 18:27:13 2006
+++ llvm-test/External/SPEC/CFP2006/481.wrf/Makefile	Wed Sep  6 15:41:12 2006
@@ -9,16 +9,65 @@
 FP_TOLERANCE    = 5e-2
 FP_ABSTOLERANCE = 1.0e-2
 
+Source = wrf_num_bytes_between.c pack_utils.c module_driver_constants.F90      \
+         module_domain.F90 module_integrate.F90 module_timing.F90              \
+         module_configure.F90 module_tiles.F90 module_machine.F90              \
+         module_nesting.F90 module_wrf_error.F90 module_state_description.F90  \
+         module_sm.F90 module_io.F90 module_dm_stubs.F90                       \
+         module_quilt_outbuf_ops.F90 module_io_quilt.F90 module_bc.F90	       \
+         module_io_wrf.F90 module_date_time.F90 module_io_domain.F90           \
+         module_bc_time_utilities.F90 module_model_constants.F90               \
+         module_soil_pre.F90 module_bl_mrf.F90 module_sf_myjsfc.F90            \
+         module_bl_myjpbl.F90 module_bl_ysu.F90 module_cu_bmj.F90              \
+         module_mp_kessler.F90 module_mp_ncloud5.F90 module_ra_sw.F90          \
+         module_sf_sfclay.F90 module_cu_kf.F90 module_cu_kfeta.F90             \
+         module_mp_lin.F90 module_mp_wsm3.F90 module_mp_wsm5.F90               \
+         module_mp_wsm6.F90 module_surface_driver.F90 module_cu_gd.F90         \
+         module_sf_sfcdiags.F90 module_ra_gsfcsw.F90 module_sf_slab.F90        \
+         module_sf_noahlsm.F90 module_sf_ruclsm.F90 module_mp_ncloud3.F90      \
+         module_mp_etanew.F90 module_ra_rrtm.F90 module_ra_gfdleta.F90         \
+         module_physics_init.F90 module_physics_addtendc.F90                   \
+         module_solvedebug_em.F90 module_bc_em.F90 module_advect_em.F90        \
+         module_diffusion_em.F90 module_small_step_em.F90                      \
+         module_big_step_utilities_em.F90 module_em.F90                        \
+         module_init_utilities.F90 module_optional_si_input.F90                \
+         ESMF_Alarm.F90 ESMF_Base.F90 ESMF_BaseTime.F90 ESMF_Calendar.F90      \
+         ESMF_Clock.F90 ESMF_Fraction.F90 ESMF_Mod.F90 ESMF_Time.F90           \
+         ESMF_TimeInterval.F90 Meat.F90 wrf_shutdown.F90 collect_on_comm.c     \
+         mediation_integrate.F90 mediation_feedback_domain.F90                 \
+         mediation_force_domain.F90 mediation_interp_domain.F90                \
+         mediation_wrfmain.F90 wrf_auxhist1in.F90 wrf_auxhist1out.F90          \
+         wrf_auxhist2in.F90 wrf_auxhist2out.F90 wrf_auxhist3in.F90             \
+         wrf_auxhist3out.F90 wrf_auxhist4in.F90 wrf_auxhist4out.F90            \
+         wrf_auxhist5in.F90 wrf_auxhist5out.F90 wrf_auxinput1in.F90            \
+         wrf_auxinput1out.F90 wrf_auxinput2in.F90 wrf_auxinput2out.F90         \
+         wrf_auxinput3in.F90 wrf_auxinput3out.F90 wrf_auxinput4in.F90          \
+         wrf_auxinput4out.F90 wrf_auxinput5in.F90 wrf_auxinput5out.F90         \
+         wrf_bdyin.F90 wrf_bdyout.F90 wrf_histin.F90 wrf_histout.F90           \
+         wrf_inputin.F90 wrf_inputout.F90 wrf_restartin.F90 wrf_restartout.F90 \
+         couple_or_uncouple_em.F90 interp_domain_em.F90 interp_fcn.F90         \
+         nest_init_utils.F90 set_timekeeping.F90 sint.F90 solve_interface.F90  \
+         start_domain.F90 module_pbl_driver.F90 module_radiation_driver.F90    \
+         module_cumulus_driver.F90 module_microphysics_driver.F90              \
+         solve_em.F90 start_em.F90 internal_header_util.F90 io_int.F90         \
+         init_modules_em.F90 init_modules.F90 wrf_io.f90 field_routines.f90    \
+         wrf.F90                                                               \
+         $(addprefix $(SPEC_BENCH_DIR)/src/netcdf/,                            \
+           attr.c dim.c error.c fort-attio.c fort-control.c fort-dim.c         \
+           fort-genatt.c fort-geninq.c fort-genvar.c fort-lib.c fort-misc.c    \
+           fort-v2compat.c fort-var1io.c fort-varaio.c fort-vario.c            \
+           fort-varmio.c fort-varsio.c libvers.c nc.c ncx.c posixio.c putget.c \
+           string.c v1hpg.c v2i.c var.c typeSizes.f90 netcdf.f90)
+
 include ../../Makefile.spec2006
 include $(PROJ_SRC_ROOT)/Makefile.FORTRAN
 
-FPPFLAGS += -w -m literal.pm \
-            -DINTIO -DIWORDSIZE=4 -DDWORDSIZE=8 -DRWORDSIZE=4 -DLWORDSIZE=4   \
-            -DNETCDF  -DTRIEDNTRUE -DLIMIT_ARGS -DEM_CORE=1  -DNMM_CORE=0     \
-            -DNMM_MAX_DIM=1000 -DCOAMPS_CORE=0  -DEXP_CORE=0 -DF90_STANDALONE \
-            -DCONFIG_BUF_LEN=8192 -DMAX_DOMAINS_F=21 -DNO_NAMELIST_PRINT      \
-            -I$(SPEC_BENCH_DIR)/src
+FPPFLAGS += -w -m literal.pm                                                   \
+            -DINTIO -DIWORDSIZE=4 -DDWORDSIZE=8 -DRWORDSIZE=4 -DLWORDSIZE=4    \
+            -DNETCDF  -DTRIEDNTRUE -DLIMIT_ARGS -DEM_CORE=1  -DNMM_CORE=0      \
+            -DNMM_MAX_DIM=1000 -DCOAMPS_CORE=0  -DEXP_CORE=0 -DF90_STANDALONE  \
+            -DCONFIG_BUF_LEN=8192 -DMAX_DOMAINS_F=21 -DNO_NAMELIST_PRINT
 
-CPPFLAGS += -I$(SPEC_BENCH_DIR)/src -I$(SPEC_BENCH_DIR)/src/netcdf/include
+CPPFLAGS += -I$(SPEC_BENCH_DIR)/src/netcdf/include
 
 STDOUT_FILENAME := rsl.out.0000





From isanbard at gmail.com  Wed Sep  6 15:41:42 2006
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 6 Sep 2006 15:41:42 -0500
Subject: [llvm-commits] CVS:
	llvm-test/External/SPEC/CFP2006/444.namd/Makefile
Message-ID: <200609062041.k86Kfgrw001695@zion.cs.uiuc.edu>



Changes in directory llvm-test/External/SPEC/CFP2006/444.namd:

Makefile updated: 1.1 -> 1.2
---
Log message:

Modified Makefiles to handle multiple directories.


---
Diffs of the changes:  (+2 -7)

 Makefile |    9 ++-------
 1 files changed, 2 insertions(+), 7 deletions(-)


Index: llvm-test/External/SPEC/CFP2006/444.namd/Makefile
diff -u llvm-test/External/SPEC/CFP2006/444.namd/Makefile:1.1 llvm-test/External/SPEC/CFP2006/444.namd/Makefile:1.2
--- llvm-test/External/SPEC/CFP2006/444.namd/Makefile:1.1	Fri Sep  1 18:27:13 2006
+++ llvm-test/External/SPEC/CFP2006/444.namd/Makefile	Wed Sep  6 15:41:12 2006
@@ -10,13 +10,8 @@
 
 include ../../Makefile.spec2006
 
-ifeq ($(RUN_TYPE),test)
-  RUN_OPTIONS     := --input namd.input --iterations 1 --output namd.out
-  STDOUT_FILENAME := namd.stdout
-else
-  RUN_OPTIONS     := --input namd.input --iterations 1 --output namd.out
-  STDOUT_FILENAME := namd.stdout
-endif
+RUN_OPTIONS      = --input namd.input --iterations 1 --output namd.out
+STDOUT_FILENAME := namd.out
 
 LDFLAGS = -lstdc++ -lm
 LIBS    = -lstdc++ -lm





From isanbard at gmail.com  Wed Sep  6 15:41:45 2006
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 6 Sep 2006 15:41:45 -0500
Subject: [llvm-commits] CVS:
	llvm-test/External/SPEC/CINT2006/471.omnetpp/Makefile
Message-ID: <200609062041.k86KfjTh001748@zion.cs.uiuc.edu>



Changes in directory llvm-test/External/SPEC/CINT2006/471.omnetpp:

Makefile updated: 1.2 -> 1.3
---
Log message:

Modified Makefiles to handle multiple directories.


---
Diffs of the changes:  (+3 -0)

 Makefile |    3 +++
 1 files changed, 3 insertions(+)


Index: llvm-test/External/SPEC/CINT2006/471.omnetpp/Makefile
diff -u llvm-test/External/SPEC/CINT2006/471.omnetpp/Makefile:1.2 llvm-test/External/SPEC/CINT2006/471.omnetpp/Makefile:1.3
--- llvm-test/External/SPEC/CINT2006/471.omnetpp/Makefile:1.2	Fri Sep  1 20:31:50 2006
+++ llvm-test/External/SPEC/CINT2006/471.omnetpp/Makefile	Wed Sep  6 15:41:12 2006
@@ -41,3 +41,6 @@
 
 RUN_OPTIONS      = omnetpp.ini
 STDOUT_FILENAME := omnetpp.log
+
+LDFLAGS = -lstdc++ -lm
+LIBS    = -lstdc++ -lm





From isanbard at gmail.com  Wed Sep  6 15:41:44 2006
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 6 Sep 2006 15:41:44 -0500
Subject: [llvm-commits] CVS: llvm-test/External/SPEC/CFP2006/Makefile
Message-ID: <200609062041.k86KfiXV001738@zion.cs.uiuc.edu>



Changes in directory llvm-test/External/SPEC/CFP2006:

Makefile updated: 1.1 -> 1.2
---
Log message:

Modified Makefiles to handle multiple directories.


---
Diffs of the changes:  (+1 -1)

 Makefile |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm-test/External/SPEC/CFP2006/Makefile
diff -u llvm-test/External/SPEC/CFP2006/Makefile:1.1 llvm-test/External/SPEC/CFP2006/Makefile:1.2
--- llvm-test/External/SPEC/CFP2006/Makefile:1.1	Fri Sep  1 18:27:13 2006
+++ llvm-test/External/SPEC/CFP2006/Makefile	Wed Sep  6 15:41:12 2006
@@ -14,6 +14,7 @@
     435.gromacs  \
     437.leslie3d \
     444.namd     \
+    447.dealII   \
     459.GemsFDTD \
     470.lbm
 
@@ -24,7 +25,6 @@
 #   482.sphinx3   - generates control file at run time
 # These don't compile
 #   436.cactusADM - multiple dirs
-#   447.dealII    - multiple dirs
 #   454.calculix  - multiple dirs
 #   481.wrf       - multiple dirs
 





From isanbard at gmail.com  Wed Sep  6 15:41:43 2006
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 6 Sep 2006 15:41:43 -0500
Subject: [llvm-commits] CVS:
	llvm-test/External/SPEC/CFP2006/482.sphinx3/Makefile
Message-ID: <200609062041.k86KfhNJ001702@zion.cs.uiuc.edu>



Changes in directory llvm-test/External/SPEC/CFP2006/482.sphinx3:

Makefile updated: 1.1 -> 1.2
---
Log message:

Modified Makefiles to handle multiple directories.


---
Diffs of the changes:  (+2 -2)

 Makefile |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm-test/External/SPEC/CFP2006/482.sphinx3/Makefile
diff -u llvm-test/External/SPEC/CFP2006/482.sphinx3/Makefile:1.1 llvm-test/External/SPEC/CFP2006/482.sphinx3/Makefile:1.2
--- llvm-test/External/SPEC/CFP2006/482.sphinx3/Makefile:1.1	Fri Sep  1 18:27:13 2006
+++ llvm-test/External/SPEC/CFP2006/482.sphinx3/Makefile	Wed Sep  6 15:41:12 2006
@@ -13,12 +13,12 @@
 CPPFLAGS += -I$(SPEC_BENCH_DIR)/src/libutil -DHAVE_CONFIG_H -DSPEC_CPU
 
 ifeq ($(RUN_TYPE),test)
-  RUN_OPTIONS     := `cp an406-fcaw-b.be.raw an406-fcaw-b.raw` \
+  RUN_OPTIONS      = `cp an406-fcaw-b.be.raw an406-fcaw-b.raw` \
                      `cp an407-fcaw-b.be.raw an407-fcaw-b.raw` \
                      `echo "an406-fcaw-b 128000" > ctlfile`    \
                      `echo "an407-fcaw-b 131200" >> ctlfile` ctlfile . args.an4
   STDOUT_FILENAME := an4.log
 else
-  RUN_OPTIONS     := leng100.hmm
+  RUN_OPTIONS      = leng100.hmm
   STDOUT_FILENAME := leng100.out
 endif





From isanbard at gmail.com  Wed Sep  6 15:41:43 2006
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 6 Sep 2006 15:41:43 -0500
Subject: [llvm-commits] CVS:
	llvm-test/External/SPEC/CFP2006/454.calculix/Makefile
Message-ID: <200609062041.k86Kfhbk001718@zion.cs.uiuc.edu>



Changes in directory llvm-test/External/SPEC/CFP2006/454.calculix:

Makefile updated: 1.1 -> 1.2
---
Log message:

Modified Makefiles to handle multiple directories.


---
Diffs of the changes:  (+129 -2)

 Makefile |  131 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 files changed, 129 insertions(+), 2 deletions(-)


Index: llvm-test/External/SPEC/CFP2006/454.calculix/Makefile
diff -u llvm-test/External/SPEC/CFP2006/454.calculix/Makefile:1.1 llvm-test/External/SPEC/CFP2006/454.calculix/Makefile:1.2
--- llvm-test/External/SPEC/CFP2006/454.calculix/Makefile:1.1	Fri Sep  1 18:27:13 2006
+++ llvm-test/External/SPEC/CFP2006/454.calculix/Makefile	Wed Sep  6 15:41:12 2006
@@ -6,8 +6,135 @@
 
 LEVEL = ../../../..
 
-FP_TOLERANCE    = 5e-2
-FP_ABSTOLERANCE = 1.0e-2
+FP_TOLERANCE    = 1.0e-9
+FP_ABSTOLERANCE = 1.0e-9
+
+Source = CalculiX.c add_pr.f add_sm_ei.f add_sm_st.f allocation.f amplitudes.f \
+         anisotropic.f beamsections.f bounadd.f boundaries.f buckles.f         \
+         calinput.f cfluxes.f changedepterm.f cloads.f conductivities.f        \
+         controlss.f couptempdisps.f creeps.f cychards.f cycsymmods.f dasol.f  \
+         datest.f datri.f defplasticities.f defplas.f densities.f depvars.f    \
+         deuldlag.f dfluxes.f dgesv.f diamtr.f dloads.f dot.f dredu.f dsort.f  \
+         dynamics.f dynsolv.f el.f elastics.f elements.f elprints.f envtemp.f  \
+         equations.f expansions.f extrapolate.f e_c3d.f e_c3d_th.f e_c3d_rhs.f \
+         fcrit.f films.f finpro.f forcadd.f frd.F frdclose.f frequencies.f     \
+         fsub.f fsuper.f gen3delem.f genran.f getnewline.f graph.f headings.f  \
+         heattransfers.f hyperel.f hyperelastics.f hyperfoams.f ident.f        \
+         ident2.f include.f incplas.f initialconditions.f inputerror.f         \
+         isorti.f isortid.f isortidc.f isortii.f isortiid.f label.f linel.f    \
+         lintemp.f lintemp_th.f loadadd.f loadaddt.f mafillpr.f mafillsm.f     \
+         mafillsmcs.f massflowrates.f matdata_co.f matdata_he.f matdata_tg.f   \
+         materialdata.f materials.f modaldampings.f modaldynamics.f mpcs.f     \
+         nident.f nident2.f near2d.f noanalysis.f nodalthicknesses.f           \
+         nodeprints.f nodes.f noelfiles.f noelsets.f nonlinmpc.f normals.f     \
+         norshell.f number.f onf.f op.f openfile.f orientations.f orthonl.f    \
+         orthotropic.f out.f parser.f physicalconstants.f planempc.f           \
+         plastics.f plcopy.f plinterpol.f plmix.f polynom.f profil.f           \
+         radflowload.f radiates.f ranewr.f rearrange.f rectcyl.f renumber.f    \
+         restartread.f restarts.f restartshort.f restartwrite.f results.f      \
+         rhs.f rigidbodies.f rigidmpc.f rootls.f rubber.f saxpb.f              \
+         selcycsymmods.f shape3tri.f shape4q.f shape4tet.f shape6tri.f         \
+         shape6w.f shape8h.f shape8q.f shape10tet.f shape15w.f shape20h.f      \
+         shellsections.f skip.f solidsections.f spcmatch.f specificheats.f     \
+         statics.f steps.f stiff2mat.f stop.f str2mat.f straightmpc.f          \
+         surfaces.f temperatures.f tempload.f ties.f transformatrix.f          \
+         transforms.f ucreep.f uhardening.f umat.f umat_aniso_creep.f          \
+         umat_aniso_plas.f umat_elastic_fiber.f umat_ideal_gas.f               \
+         umat_lin_iso_el.f umat_single_crystal.f umat_tension_only.f           \
+         umat_user.f umpc_mean_rot.f umpc_user.f usermaterials.f usermpc.f     \
+         viscos.f wcoef.f writebv.f writeev.f writeevcs.f writempc.f           \
+         writesummary.f cascade.c frdcyc.c insert.c mastruct.c mastructcs.c    \
+         nonlingeo.c pcgsolver.c preiter.c prespooles.c profile.c remastruct.c \
+         spooles.c strcmp1.c strcpy1.c u_calloc.c                              \
+         $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/A2/src/,                    \
+           A2_IO.c A2_basics.c A2_init.c A2_instance.c A2_norms.c A2_sort.c    \
+           A2_util.c)                                                          \
+         $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/BKL/src/,                   \
+           BKL_basics.c BKL_evalfcn.c BKL_exhSearch.c BKL_fidmat.c BKL_init.c  \
+           BKL_util.c)                                                         \
+         $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/BPG/src/,                   \
+           BPG_IO.c BPG_basics.c BPG_init.c BPG_makeGraphs.c BPG_pseudo.c)     \
+         $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/Chv/src/,                   \
+           Chv_IO.c Chv_assemble.c Chv_basics.c Chv_copy.c Chv_factor.c        \
+           Chv_findPivot.c Chv_init.c Chv_instance.c Chv_search.c Chv_swap.c   \
+           Chv_update.c Chv_util.c)                                            \
+         $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/ChvList/src/,               \
+           ChvList_basics.c ChvList_init.c ChvList_util.c)                     \
+         $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/ChvManager/src/,            \
+           ChvManager_basics.c ChvManager_init.c ChvManager_util.c)            \
+         $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/DSTree/src/,                \
+           DSTree_basics.c DSTree_init.c DSTree_instance.c DSTree_stages.c     \
+           DSTree_util.c)                                                      \
+         $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/DV/src/,                    \
+           DV_IO.c DV_basics.c DV_init.c DV_instance.c DV_util.c)              \
+         $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/DenseMtx/src/,              \
+           DenseMtx_IO.c DenseMtx_basics.c DenseMtx_init.c DenseMtx_instance.c \
+           DenseMtx_permute.c DenseMtx_util.c)                                 \
+         $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/Drand/src/,                 \
+           Drand_basics.c Drand_init.c Drand_util.c)                           \
+         $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/ETree/src/,                 \
+           ETree_IO.c ETree_basics.c ETree_compress.c ETree_init.c             \
+           ETree_instance.c ETree_permute.c ETree_transform.c ETree_util.c)    \
+         $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/FrontMtx/src/,              \
+           FrontMtx_IO.c FrontMtx_basics.c FrontMtx_factor.c                   \
+           FrontMtx_factorUtil.c FrontMtx_init.c FrontMtx_instance.c           \
+           FrontMtx_loadEntries.c FrontMtx_permute.c FrontMtx_postProcess.c    \
+           FrontMtx_postponed.c FrontMtx_solve.c FrontMtx_solveUtil.c          \
+           FrontMtx_split.c FrontMtx_storeFront.c FrontMtx_update.c            \
+           FrontMtx_util.c)                                                    \
+         $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/GPart/src/,                 \
+           GPart_DDsepInfo.c GPart_DDviaFishnet.c GPart_DDviaProjection.c      \
+           GPart_RBviaDDsep.c GPart_TwoSetViaBKL.c GPart_basics.c              \
+           GPart_domSegMap.c GPart_identifyWideSep.c GPart_init.c              \
+           GPart_makeYCmap.c GPart_smoothBisector.c GPart_smoothBy2layers.c    \
+           GPart_smoothYSep.c GPart_split.c GPart_util.c)                      \
+         $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/Graph/src/,                 \
+           Graph_IO.c Graph_basics.c Graph_compress.c Graph_equivMap.c         \
+           Graph_init.c Graph_util.c)                                          \
+         $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/I2Ohash/src/,               \
+           I2Ohash_basics.c I2Ohash_init.c I2Ohash_util.c)                     \
+         $(SPEC_BENCH_DIR)/src/SPOOLES/IIheap/src/IIheap_basics.c              \
+         $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/IV/src/,                    \
+           IV_IO.c IV_basics.c IV_init.c IV_instance.c IV_util.c)              \
+         $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/IVL/src/,                   \
+           IVL_IO.c IVL_basics.c IVL_init.c IVL_instance.c IVL_listmanip.c     \
+           IVL_util.c)                                                         \
+         $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/Ideq/src/,                  \
+           Ideq_basics.c Ideq_resize.c Ideq_util.c)                            \
+         $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/InpMtx/src/,                \
+           InpMtx_IO.c InpMtx_basics.c InpMtx_fullAdj.c InpMtx_init.c          \
+           InpMtx_input.c InpMtx_instance.c InpMtx_permute.c InpMtx_util.c)    \
+         $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/Lock/src/,                  \
+           Lock_basics.c Lock_init.c Lock_util.c)                              \
+         $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/MSMD/src/,                  \
+           MSMD_MSMDinfo.c MSMD_MSMDvtx.c MSMD_basics.c MSMD_cleanReachSet.c   \
+           MSMD_eliminate.c MSMD_findInodes.c MSMD_frontETree.c MSMD_init.c    \
+           MSMD_order.c MSMD_update.c)                                         \
+         $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/Network/src/,               \
+           Network_IO.c Network_addArc.c Network_augmentPath.c                 \
+           Network_basics.c Network_findAugmentingPath.c Network_findMaxFlow.c \
+           Network_findMincut.c Network_init.c)                                \
+         $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/Pencil/src/,                \
+           Pencil_IO.c Pencil_basics.c Pencil_init.c)                          \
+         $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/SubMtx/src/,                \
+           SubMtx_IO.c SubMtx_basics.c SubMtx_init.c SubMtx_instance.c         \
+           SubMtx_scalevec.c SubMtx_solve.c SubMtx_solveH.c SubMtx_solveT.c    \
+           SubMtx_solveupd.c SubMtx_solveupdH.c SubMtx_solveupdT.c             \
+           SubMtx_sort.c SubMtx_util.c)                                        \
+         $(SPEC_BENCH_DIR)/src/SPOOLES/SubMtxList/src/SubMtxList_util.c        \
+         $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/SubMtxManager/src/,         \
+           SubMtxManager_basics.c SubMtxManager_init.c SubMtxManager_util.c)   \
+         $(SPEC_BENCH_DIR)/src/SPOOLES/SymbFac/src/SymbFac_symbfac.c           \
+         $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/Tree/src/,                  \
+           Tree_IO.c Tree_basics.c Tree_compress.c Tree_init.c Tree_metrics.c  \
+           Tree_perms.c Tree_util.c)                                           \
+         $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/Utilities/src/,             \
+           Utilities_CV.c Utilities_DV.c Utilities_I2OP.c Utilities_IP.c       \
+           Utilities_IV.c Utilities_PIV.c Utilities_ZV.c Utilities_iohb.c      \
+           Utilities_newsort.c Utilities_sortAndCompress.c)                    \
+         $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/ZV/src/,                    \
+           ZV_basics.c ZV_init.c ZV_instance.c)                                \
+         $(SPEC_BENCH_DIR)/src/SPOOLES/misc/src/misc_orderViaBestOfNDandMS.c
 
 include ../../Makefile.spec2006
 include $(PROJ_SRC_ROOT)/Makefile.FORTRAN





From isanbard at gmail.com  Wed Sep  6 15:41:43 2006
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 6 Sep 2006 15:41:43 -0500
Subject: [llvm-commits] CVS:
	llvm-test/External/SPEC/CFP2006/436.cactusADM/Makefile
Message-ID: <200609062041.k86KfhtB001712@zion.cs.uiuc.edu>



Changes in directory llvm-test/External/SPEC/CFP2006/436.cactusADM:

Makefile updated: 1.1 -> 1.2
---
Log message:

Modified Makefiles to handle multiple directories.


---
Diffs of the changes:  (+103 -2)

 Makefile |  105 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++--
 1 files changed, 103 insertions(+), 2 deletions(-)


Index: llvm-test/External/SPEC/CFP2006/436.cactusADM/Makefile
diff -u llvm-test/External/SPEC/CFP2006/436.cactusADM/Makefile:1.1 llvm-test/External/SPEC/CFP2006/436.cactusADM/Makefile:1.2
--- llvm-test/External/SPEC/CFP2006/436.cactusADM/Makefile:1.1	Fri Sep  1 18:27:13 2006
+++ llvm-test/External/SPEC/CFP2006/436.cactusADM/Makefile	Wed Sep  6 15:41:12 2006
@@ -6,9 +6,110 @@
 
 LEVEL = ../../../..
 
+Source = PreLoop.F StaggeredLeapfrog1a.F StaggeredLeapfrog1a_TS.F              \
+         StaggeredLeapfrog2.F planewaves.F teukwaves.F datestamp.c regex.c     \
+         $(addprefix $(SPEC_BENCH_DIR)/src/PUGH/,                              \
+           GHExtension.c FinishReceiveGA.c Startup.c Evolve.c Storage.c        \
+           SetupGroup.c PostSendGA.c SetupPGH.c SetupPGV.c LoadAware.c Comm.c  \
+           cctk_ThornBindings.c Overloadables.c PughUtils.c PostReceiveGA.c)   \
+         $(addprefix $(SPEC_BENCH_DIR)/src/Time/,                              \
+           Courant.c Initialise.c cctk_ThornBindings.c Given.c Simple.c)       \
+         $(addprefix $(SPEC_BENCH_DIR)/src/Cactus/,                            \
+           ScheduleTraverse.c Groups.c Dummies.c File.c CactusDefaultEvolve.c  \
+           BinaryTree.c Hash.c Malloc.c CactusTimers.c CallStartupFunctions.c  \
+           FortranBindingsIO.c ConfigData.c CactusDefaultMainLoopIndex.c       \
+           Misc.c CactusDefaultComm.c Cache.c RegisterKeyedFunction.c          \
+           Subsystems.c FortranWrappers.c Network.c Stagger.c                  \
+           CactusDefaultInitialise.c Time.c Expression.c CactusSync.c          \
+           ProcessCommandLine.c WarnLevel.c CommandLine.c Coord.c              \
+           ScheduleInterface.c MainUtils.c Reduction.c GHExtensions.c          \
+           StoreHandledData.c ShutdownCactus.c ProcessEnvironment.c getopt.c   \
+           ParseFile.c OverloadIO.c StoreKeyedData.c getopt1.c                 \
+           CactusDefaultShutdown.c Banner.c Termination.c                      \
+           ProcessParameterDatabase.c ActiveThorns.c String.c SetupCache.c     \
+           Table.c DebugDefines.c Interp.c Parameters.c GroupsOnGH.c           \
+           InitialiseCactus.c IOMethods.c flesh.c ScheduleCreater.c            \
+           SetParams.c cctk_ThornBindings.c OverloadComm.c Names.c             \
+           InitialiseDataStructures.c StringList.c DefaultTimers.c             \
+           StoreNamedData.c ScheduleSorter.c Complex.c OverloadMain.c          \
+           Traverse.c SKBinTree.c snprintf.c)                                  \
+         $(addprefix $(SPEC_BENCH_DIR)/src/IOUtil/,                            \
+           CheckpointRecovery.c Utils.c AdvertisedFiles.c Startup.c            \
+           cctk_ThornBindings.c)                                               \
+         $(SPEC_BENCH_DIR)/src/IDLinearWaves/cctk_ThornBindings.c              \
+         $(addprefix $(SPEC_BENCH_DIR)/src/BenchADMsrc/,                       \
+           Startup.c ParamCheck.c cctk_ThornBindings.c)                        \
+         $(addprefix $(SPEC_BENCH_DIR)/src/CactusBindings/,                    \
+           ParameterRecoveryEinstein.c ParameterRecoveryCactus.c               \
+           TIME_private.c OverloadThorns.c Cactus.c PUGH_Register.c            \
+           EINSTEIN_restricted.c ParameterRecoveryIOASCII.c IOASCII.c          \
+           CreateTimeParameters.c BOUNDARY_restricted.c                        \
+           CreateIOBasicParameters.c Global.c ParameterRecoveryPUGH.c          \
+           EINSTEIN_private.c CARTGRID3D_private.c                             \
+           BindingsParameterRecovery.c PUGH.c ParameterRecoveryPUGHSlab.c      \
+           SchedulePUGH.c IOUtil_Register.c TIME_restricted.c                  \
+           Cactus_FortranWrapper.c ParameterRecoveryTime.c                     \
+           BenchADM_FortranWrapper.c IOASCII_private.c PUGHReduce.c            \
+           CACTUS_private.c Time.c ScheduleTime.c Boundary_Register.c          \
+           PUGHReduce_Register.c CreateEinsteinParameters.c BindingsSchedule.c \
+           CreateIOASCIIParameters.c CreatePUGHParameters.c BENCHADM_private.c \
+           CreateBenchADMParameters.c CreateIOUtilParameters.c                 \
+           CreateCartGrid3DParameters.c IDLINEARWAVES_private.c Boundary.c     \
+           Einstein.c CreateIDLinearWavesParameters.c                          \
+           ParameterRecoveryBenchADM.c ParameterRecoveryIOBasic.c              \
+           PUGH_private.c ScheduleIOASCII.c PUGHSlab_Register.c                \
+           ScheduleBoundary.c CreatePUGHReduceParameters.c IOBasic.c           \
+           ScheduleEinstein.c ParameterRecoveryPUGHReduce.c CartGrid3D.c       \
+           IOASCII_Register.c IDLinearWaves_FortranWrapper.c                   \
+           PUGH_FortranWrapper.c ScheduleIDLinearWaves.c DummyThornFunctions.c \
+           CreateBoundaryParameters.c IO_restricted.c PUGHSlab.c               \
+           BenchADM_Register.c CartGrid3D_Register.c SchedulePUGHSlab.c        \
+           ParameterRecoveryIDLinearWaves.c IOBASIC_private.c                  \
+           SchedulePUGHReduce.c PUGHReduce_FortranWrapper.c ScheduleIOUtil.c   \
+           Einstein_Register.c CreateCactusParameters.c Time_Register.c        \
+           IOBasic_FortranWrapper.c CreatePUGHSlabParameters.c                 \
+           CACTUS_restricted.c BindingsVariables.c IsOverloaded.c              \
+           Cactus_Register.c Einstein_FortranWrapper.c                         \
+           ParameterRecoveryIOUtil.c IOUtil.c ParameterRecoveryCartGrid3D.c    \
+           PUGHSlab_FortranWrapper.c BENCHADM_restricted.c                     \
+           BindingsParameters.c CartGrid3D_FortranWrapper.c                    \
+           RegisterThornFunctions.c Boundary_FortranWrapper.c                  \
+           ScheduleIOBasic.c BenchADM.c IOBasic_Register.c IDLinearWaves.c     \
+           Time_FortranWrapper.c IDLinearWaves_Register.c                      \
+           IOASCII_FortranWrapper.c ScheduleBenchADM.c ScheduleCactus.c        \
+           ImplementationBindings.c DRIVER_restricted.c                        \
+           IOUtil_FortranWrapper.c ScheduleCartGrid3D.c                        \
+           FortranThornFunctions.c GRID_restricted.c                           \
+           ParameterRecoveryBoundary.c)                                        \
+         $(addprefix $(SPEC_BENCH_DIR)/src/CartGrid3D/,                        \
+           SymmetryWrappers.c GHExtension.c DecodeSymParameters.c              \
+           SetSymmetry.c Startup.c CartGrid3D.c Symmetry.c ParamCheck.c        \
+           cctk_ThornBindings.c)                                               \
+         $(addprefix $(SPEC_BENCH_DIR)/src/Einstein/,                          \
+           Courant.c InitialEinstein.c MaskInit.c Slicing.c InitialFlat.c      \
+           carttosphere.c InitSymBound.c LapseInits.c cctk_ThornBindings.c     \
+           ShiftInits.c evaltrK.c ConfPhys.c)                                  \
+         $(addprefix $(SPEC_BENCH_DIR)/src/PUGHReduce/,                        \
+           ReductionNormInf.c ReductionMax.c ReductionMin.c ReductionSum.c     \
+           Startup.c Reduction.c ReductionNorm1.c ReductionNorm2.c             \
+           cctk_ThornBindings.c)                                               \
+         $(addprefix $(SPEC_BENCH_DIR)/src/Boundary/,                          \
+           FlatBoundary.c ScalarBoundary.c RadiationBoundary.c RobinBoundary.c \
+           CopyBoundary.c cctk_ThornBindings.c)                                \
+         $(addprefix $(SPEC_BENCH_DIR)/src/PUGHSlab/,                          \
+           DatatypeConversion.c GetHyperslab.c Mapping.c Hyperslab.c           \
+           cctk_ThornBindings.c NewHyperslab.c)                                \
+         $(addprefix $(SPEC_BENCH_DIR)/src/IOASCII/,                           \
+           Output1D.c Output2D.c Output3D.c Startup.c cctk_ThornBindings.c     \
+           ChooseOutput.c Write1D.c Write2D.c Write3D.c)                       \
+         $(addprefix $(SPEC_BENCH_DIR)/src/IOBasic/,                           \
+           WriteScalar.c OutputScalar.c OutputInfo.c Startup.c WriteInfo.c     \
+           cctk_ThornBindings.c)
+
 include ../../Makefile.spec2006
 include $(PROJ_SRC_ROOT)/Makefile.FORTRAN
 
-CPPFLAGS += -DCCODE -I$(SPEC_BENCH_DIR)/src/include
+CFLAGS += -DCCODE
 
-STDOUT_FILENAME := cactusADM.out
+RUN_OPTIONS      = benchADM
+STDOUT_FILENAME := benchADM.out





From isanbard at gmail.com  Wed Sep  6 15:41:45 2006
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 6 Sep 2006 15:41:45 -0500
Subject: [llvm-commits] CVS:
	llvm-test/External/SPEC/CFP2006/465.tonto/Makefile
Message-ID: <200609062041.k86KfjbY001743@zion.cs.uiuc.edu>



Changes in directory llvm-test/External/SPEC/CFP2006/465.tonto:

Makefile updated: 1.1 -> 1.2
---
Log message:

Modified Makefiles to handle multiple directories.


---
Diffs of the changes:  (+2 -2)

 Makefile |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm-test/External/SPEC/CFP2006/465.tonto/Makefile
diff -u llvm-test/External/SPEC/CFP2006/465.tonto/Makefile:1.1 llvm-test/External/SPEC/CFP2006/465.tonto/Makefile:1.2
--- llvm-test/External/SPEC/CFP2006/465.tonto/Makefile:1.1	Fri Sep  1 18:27:13 2006
+++ llvm-test/External/SPEC/CFP2006/465.tonto/Makefile	Wed Sep  6 15:41:12 2006
@@ -14,10 +14,10 @@
 FPPFLAGS += -w -DUSE_PRE_AND_POST_CONDITIONS -DUSE_ERROR_MANAGEMENT \
             -m literal.pm -m tonto.pm
 
+STDIN_FILENAME := stdin
+
 ifeq ($(RUN_TYPE),test)
-  RUN_OPTIONS     := stdin
   STDOUT_FILENAME := test.out
 else
-  RUN_OPTIONS     := stdin
   STDOUT_FILENAME := train.out
 endif





From isanbard at gmail.com  Wed Sep  6 15:41:43 2006
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 6 Sep 2006 15:41:43 -0500
Subject: [llvm-commits] CVS:
	llvm-test/External/SPEC/CFP2006/450.soplex/Makefile
Message-ID: <200609062041.k86Kfh71001711@zion.cs.uiuc.edu>



Changes in directory llvm-test/External/SPEC/CFP2006/450.soplex:

Makefile updated: 1.1 -> 1.2
---
Log message:

Modified Makefiles to handle multiple directories.


---
Diffs of the changes:  (+4 -3)

 Makefile |    7 ++++---
 1 files changed, 4 insertions(+), 3 deletions(-)


Index: llvm-test/External/SPEC/CFP2006/450.soplex/Makefile
diff -u llvm-test/External/SPEC/CFP2006/450.soplex/Makefile:1.1 llvm-test/External/SPEC/CFP2006/450.soplex/Makefile:1.2
--- llvm-test/External/SPEC/CFP2006/450.soplex/Makefile:1.1	Fri Sep  1 18:27:13 2006
+++ llvm-test/External/SPEC/CFP2006/450.soplex/Makefile	Wed Sep  6 15:41:12 2006
@@ -6,7 +6,6 @@
 
 LEVEL = ../../../..
 
-FP_TOLERANCE    = 0.0001
 FP_ABSTOLERANCE = 1.0e-5
 
 include ../../Makefile.spec2006
@@ -14,10 +13,12 @@
 CPPFLAGS += -DNDEBUG
 
 ifeq ($(RUN_TYPE),test)
-  RUN_OPTIONS     := -s1 -e -m10000 test.mps
+  FP_TOLERANCE     = 0.0001
+  RUN_OPTIONS      = -s1 -e -m10000 test.mps
   STDOUT_FILENAME := test.out
 else
-  RUN_OPTIONS     := -s1 -e -m1200 train.mps
+  FP_TOLERANCE     = 20
+  RUN_OPTIONS      = -s1 -e -m1200 train.mps
   STDOUT_FILENAME := train.out
 endif
 





From isanbard at gmail.com  Wed Sep  6 15:41:43 2006
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 6 Sep 2006 15:41:43 -0500
Subject: [llvm-commits] CVS:
	llvm-test/External/SPEC/CFP2006/453.povray/Makefile
Message-ID: <200609062041.k86Kfhdg001724@zion.cs.uiuc.edu>



Changes in directory llvm-test/External/SPEC/CFP2006/453.povray:

Makefile updated: 1.1 -> 1.2
---
Log message:

Modified Makefiles to handle multiple directories.


---
Diffs of the changes:  (+4 -2)

 Makefile |    6 ++++--
 1 files changed, 4 insertions(+), 2 deletions(-)


Index: llvm-test/External/SPEC/CFP2006/453.povray/Makefile
diff -u llvm-test/External/SPEC/CFP2006/453.povray/Makefile:1.1 llvm-test/External/SPEC/CFP2006/453.povray/Makefile:1.2
--- llvm-test/External/SPEC/CFP2006/453.povray/Makefile:1.1	Fri Sep  1 18:27:13 2006
+++ llvm-test/External/SPEC/CFP2006/453.povray/Makefile	Wed Sep  6 15:41:12 2006
@@ -6,15 +6,17 @@
 
 LEVEL = ../../../..
 
+FP_ABSTOLERANCE = 0
+
 include ../../Makefile.spec2006
 
 ifeq ($(RUN_TYPE),test)
   FP_TOLERANCE     = 0.0002
-  RUN_OPTIONS     := SPEC-benchmark-test
+  RUN_OPTIONS      = SPEC-benchmark-test
   STDOUT_FILENAME := test.out
 else
   FP_TOLERANCE     = 0.00005
-  RUN_OPTIONS     := SPEC-benchmark-train
+  RUN_OPTIONS      = SPEC-benchmark-train
   STDOUT_FILENAME := train.out
 endif
 





From isanbard at gmail.com  Wed Sep  6 15:41:45 2006
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 6 Sep 2006 15:41:45 -0500
Subject: [llvm-commits] CVS:
	llvm-test/External/SPEC/CFP2006/459.GemsFDTD/Makefile
Message-ID: <200609062041.k86Kfj2K001753@zion.cs.uiuc.edu>



Changes in directory llvm-test/External/SPEC/CFP2006/459.GemsFDTD:

Makefile updated: 1.1 -> 1.2
---
Log message:

Modified Makefiles to handle multiple directories.


---
Diffs of the changes:  (+2 -4)

 Makefile |    6 ++----
 1 files changed, 2 insertions(+), 4 deletions(-)


Index: llvm-test/External/SPEC/CFP2006/459.GemsFDTD/Makefile
diff -u llvm-test/External/SPEC/CFP2006/459.GemsFDTD/Makefile:1.1 llvm-test/External/SPEC/CFP2006/459.GemsFDTD/Makefile:1.2
--- llvm-test/External/SPEC/CFP2006/459.GemsFDTD/Makefile:1.1	Fri Sep  1 18:27:13 2006
+++ llvm-test/External/SPEC/CFP2006/459.GemsFDTD/Makefile	Wed Sep  6 15:41:12 2006
@@ -6,16 +6,14 @@
 
 LEVEL = ../../../..
 
-FP_TOLERANCE    = 1e-10
-FP_ABSTOLERANCE = 1e-9
+FP_TOLERANCE    = 1.0e-9
+FP_ABSTOLERANCE = 1.0e-10
 
 include ../../Makefile.spec2006
 include $(PROJ_SRC_ROOT)/Makefile.FORTRAN
 
 ifeq ($(RUN_TYPE),test)
-  RUN_OPTIONS     := test.in
   STDOUT_FILENAME := test.log
 else
-  RUN_OPTIONS     := train.in
   STDOUT_FILENAME := train.log
 endif





From lattner at cs.uiuc.edu  Wed Sep  6 16:55:14 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 6 Sep 2006 16:55:14 -0500
Subject: [llvm-commits] CVS:
	llvm/test/Regression/CodeGen/X86/test-load-fold.ll
Message-ID: <200609062155.k86LtESY003139@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CodeGen/X86:

test-load-fold.ll added (r1.1)
---
Log message:

testcase, ensure this never breaks.


---
Diffs of the changes:  (+29 -0)

 test-load-fold.ll |   29 +++++++++++++++++++++++++++++
 1 files changed, 29 insertions(+)


Index: llvm/test/Regression/CodeGen/X86/test-load-fold.ll
diff -c /dev/null llvm/test/Regression/CodeGen/X86/test-load-fold.ll:1.1
*** /dev/null	Wed Sep  6 16:55:09 2006
--- llvm/test/Regression/CodeGen/X86/test-load-fold.ll	Wed Sep  6 16:54:59 2006
***************
*** 0 ****
--- 1,29 ----
+ ; RUN: llvm-as < %s | llc
+ 	%struct._obstack_chunk = type { sbyte*, %struct._obstack_chunk*, [4 x sbyte] }
+ 	%struct.obstack = type { int, %struct._obstack_chunk*, sbyte*, sbyte*, sbyte*, int, int, %struct._obstack_chunk* (...)*, void (...)*, sbyte*, ubyte }
+ %stmt_obstack = external global %struct.obstack		; <%struct.obstack*> [#uses=1]
+ 
+ implementation   ; Functions:
+ 
+ void %expand_start_bindings() {
+ entry:
+ 	br bool false, label %cond_true, label %cond_next
+ 
+ cond_true:		; preds = %entry
+ 	%new_size.0.i = select bool false, int 0, int 0		; <int> [#uses=1]
+ 	%tmp.i = load uint* cast (ubyte* getelementptr (%struct.obstack* %stmt_obstack, int 0, uint 10) to uint*)		; <uint> [#uses=1]
+ 	%tmp.i = cast uint %tmp.i to ubyte		; <ubyte> [#uses=1]
+ 	%tmp21.i = and ubyte %tmp.i, 1		; <ubyte> [#uses=1]
+ 	%tmp22.i = seteq ubyte %tmp21.i, 0		; <bool> [#uses=1]
+ 	br bool %tmp22.i, label %cond_false30.i, label %cond_true23.i
+ 
+ cond_true23.i:		; preds = %cond_true
+ 	ret void
+ 
+ cond_false30.i:		; preds = %cond_true
+ 	%tmp35.i = tail call %struct._obstack_chunk* null( int %new_size.0.i )		; <%struct._obstack_chunk*> [#uses=0]
+ 	ret void
+ 
+ cond_next:		; preds = %entry
+ 	ret void
+ }





From isanbard at gmail.com  Wed Sep  6 16:55:51 2006
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 6 Sep 2006 16:55:51 -0500
Subject: [llvm-commits] CVS:
	llvm-test/External/SPEC/CINT2006/400.perlbench/Makefile
Message-ID: <200609062155.k86LtpHr003172@zion.cs.uiuc.edu>



Changes in directory llvm-test/External/SPEC/CINT2006/400.perlbench:

Makefile updated: 1.2 -> 1.3
---
Log message:

Add the "perlbench" benchmark test to the SPEC2006 testing thingy.


---
Diffs of the changes:  (+13 -8)

 Makefile |   21 +++++++++++++--------
 1 files changed, 13 insertions(+), 8 deletions(-)


Index: llvm-test/External/SPEC/CINT2006/400.perlbench/Makefile
diff -u llvm-test/External/SPEC/CINT2006/400.perlbench/Makefile:1.2 llvm-test/External/SPEC/CINT2006/400.perlbench/Makefile:1.3
--- llvm-test/External/SPEC/CINT2006/400.perlbench/Makefile:1.2	Fri Sep  1 20:29:28 2006
+++ llvm-test/External/SPEC/CINT2006/400.perlbench/Makefile	Wed Sep  6 16:55:34 2006
@@ -7,19 +7,14 @@
 
 LEVEL = ../../../..
 
-include ../../Makefile.spec2006
-
 CPPFLAGS += -DPERL_CORE
 
-ifeq ($(OS),Darwin)
 ifeq ($(ARCH),PowerPC)
   CPPFLAGS += -DSPEC_CPU_MACOSX_PPC
-else
+endif
 ifeq ($(ARCH),x86)
   CPPFLAGS += -DSPEC_CPU_MACOSX_IA32
 endif
-endif
-endif
 
 ifeq ($(ENDIAN),little)
   CPPFLAGS += -D__LITTLE_ENDIAN__
@@ -27,11 +22,21 @@
   CPPFLAGS += -D__BIG_ENDIAN__
 endif
 
+Source = av.c deb.c doio.c doop.c dump.c globals.c gv.c hv.c locale.c mg.c     \
+         numeric.c op.c pad.c perl.c perlapi.c perlio.c perlmain.c perly.c     \
+         pp.c pp_ctl.c pp_hot.c pp_pack.c pp_sort.c pp_sys.c regcomp.c         \
+         regexec.c run.c scope.c sv.c taint.c toke.c universal.c utf8.c util.c \
+         xsutils.c Base64.c Cwd.c Dumper.c HiRes.c IO.c Peek.c attrs.c poll.c  \
+         stdio.c DynaLoader.c MD5.c Storable.c Parser.c specrand.c Hostname.c  \
+         Opcode.c
+
+include ../../Makefile.spec2006
+
 ifeq ($(RUN_TYPE),test)
-  RUN_OPTIONS      = test.pl
+  RUN_OPTIONS      = -I./lib test.pl
   STDOUT_FILENAME := test.out
 else
-  RUN_OPTIONS      = scrabbl.pl
+  RUN_OPTIONS      = -I./lib scrabbl.pl
   STDIN_FILENAME  := scrabbl.in
   STDOUT_FILENAME := scrabbl.out
 endif





From isanbard at gmail.com  Wed Sep  6 16:55:51 2006
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 6 Sep 2006 16:55:51 -0500
Subject: [llvm-commits] CVS: llvm-test/External/SPEC/CINT2006/Makefile
Message-ID: <200609062155.k86LtpgY003167@zion.cs.uiuc.edu>



Changes in directory llvm-test/External/SPEC/CINT2006:

Makefile updated: 1.1 -> 1.2
---
Log message:

Add the "perlbench" benchmark test to the SPEC2006 testing thingy.


---
Diffs of the changes:  (+1 -1)

 Makefile |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm-test/External/SPEC/CINT2006/Makefile
diff -u llvm-test/External/SPEC/CINT2006/Makefile:1.1 llvm-test/External/SPEC/CINT2006/Makefile:1.2
--- llvm-test/External/SPEC/CINT2006/Makefile:1.1	Thu Aug 31 14:26:35 2006
+++ llvm-test/External/SPEC/CINT2006/Makefile	Wed Sep  6 16:55:34 2006
@@ -6,6 +6,7 @@
 
 LEVEL = ../../..
 PARALLEL_DIRS := \
+        400.perlbench  \
 	401.bzip2      \
 	403.gcc        \
 	429.mcf        \
@@ -15,7 +16,6 @@
         464.h264ref    \
         473.astar
 
-# 400.perlbench -- Need Makefile Help
 # 445.gobmk     -- Multiple Dirs
 # 471.omnetpp   -- Multiple Dirs
 # 483.xalancbmk -- Needs C++ Exceptions





From isanbard at gmail.com  Wed Sep  6 19:09:03 2006
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 6 Sep 2006 19:09:03 -0500
Subject: [llvm-commits] CVS:
	llvm-test/External/SPEC/CINT2006/400.perlbench/Makefile
Message-ID: <200609070009.k87093Ld005675@zion.cs.uiuc.edu>



Changes in directory llvm-test/External/SPEC/CINT2006/400.perlbench:

Makefile updated: 1.3 -> 1.4
---
Log message:

Change STDOUT_FILENAME to one which exists in the data/test/output
directory so that we don't get an error during testing.


---
Diffs of the changes:  (+5 -1)

 Makefile |    6 +++++-
 1 files changed, 5 insertions(+), 1 deletion(-)


Index: llvm-test/External/SPEC/CINT2006/400.perlbench/Makefile
diff -u llvm-test/External/SPEC/CINT2006/400.perlbench/Makefile:1.3 llvm-test/External/SPEC/CINT2006/400.perlbench/Makefile:1.4
--- llvm-test/External/SPEC/CINT2006/400.perlbench/Makefile:1.3	Wed Sep  6 16:55:34 2006
+++ llvm-test/External/SPEC/CINT2006/400.perlbench/Makefile	Wed Sep  6 19:08:49 2006
@@ -33,10 +33,14 @@
 include ../../Makefile.spec2006
 
 ifeq ($(RUN_TYPE),test)
+  # test.out isn't specified in the REF_IN_DIR/test/data/output directory, so
+  # use one of the .out files that does exist in that directory.
   RUN_OPTIONS      = -I./lib test.pl
-  STDOUT_FILENAME := test.out
+  STDOUT_FILENAME := append.out
+  STDERR_FILENAME := append.err
 else
   RUN_OPTIONS      = -I./lib scrabbl.pl
   STDIN_FILENAME  := scrabbl.in
   STDOUT_FILENAME := scrabbl.out
+  STDERR_FILENAME := scrabbl.err
 endif





From evan.cheng at apple.com  Wed Sep  6 20:18:11 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Wed, 6 Sep 2006 20:18:11 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86CodeEmitter.cpp
Message-ID: <200609070118.k871IB25006712@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86CodeEmitter.cpp updated: 1.117 -> 1.118
---
Log message:

Clean up.

---
Diffs of the changes:  (+2 -2)

 X86CodeEmitter.cpp |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/X86/X86CodeEmitter.cpp
diff -u llvm/lib/Target/X86/X86CodeEmitter.cpp:1.117 llvm/lib/Target/X86/X86CodeEmitter.cpp:1.118
--- llvm/lib/Target/X86/X86CodeEmitter.cpp:1.117	Wed Sep  6 15:32:45 2006
+++ llvm/lib/Target/X86/X86CodeEmitter.cpp	Wed Sep  6 20:17:57 2006
@@ -527,6 +527,6 @@
     break;
   }
 
-  if ((Desc.Flags & M_VARIABLE_OPS) == 0)
-    assert(CurOp == MI.getNumOperands() && "Unknown encoding!");
+  assert((Desc.Flags & M_VARIABLE_OPS) != 0 ||
+         CurOp == MI.getNumOperands() && "Unknown encoding!");
 }





From lattner at cs.uiuc.edu  Wed Sep  6 20:59:19 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 6 Sep 2006 20:59:19 -0500
Subject: [llvm-commits] CVS:
	llvm/test/Regression/CodeGen/Generic/2006-09-06-SwitchLowering.ll
Message-ID: <200609070159.k871xJPQ007360@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CodeGen/Generic:

2006-09-06-SwitchLowering.ll added (r1.1)
---
Log message:

New testcase for a switch lowering bug.


---
Diffs of the changes:  (+96 -0)

 2006-09-06-SwitchLowering.ll |   96 +++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 96 insertions(+)


Index: llvm/test/Regression/CodeGen/Generic/2006-09-06-SwitchLowering.ll
diff -c /dev/null llvm/test/Regression/CodeGen/Generic/2006-09-06-SwitchLowering.ll:1.1
*** /dev/null	Wed Sep  6 20:59:15 2006
--- llvm/test/Regression/CodeGen/Generic/2006-09-06-SwitchLowering.ll	Wed Sep  6 20:59:05 2006
***************
*** 0 ****
--- 1,96 ----
+ ; RUN: llvm-as < %s | llc
+ 
+ void %foo() {
+ 	br label %cond_true813.i
+ 
+ cond_true813.i:		; preds = %0
+ 	br bool false, label %cond_true818.i, label %cond_next1146.i
+ 
+ cond_true818.i:		; preds = %cond_true813.i
+ 	br bool false, label %recog_memoized.exit52, label %cond_next1146.i
+ 
+ recog_memoized.exit52:		; preds = %cond_true818.i
+ 	switch int 0, label %bb886.i.preheader [
+ 		 int 0, label %bb907.i
+ 		 int 44, label %bb866.i
+ 		 int 103, label %bb874.i
+ 		 int 114, label %bb874.i
+ 	]
+ 
+ bb857.i:		; preds = %bb886.i, %bb866.i
+ 	%tmp862.i494.24 = phi sbyte* [ null, %bb866.i ], [ %tmp862.i494.26, %bb886.i ]		; <sbyte*> [#uses=4]
+ 	switch int 0, label %bb886.i.preheader [
+ 		 int 0, label %bb907.i
+ 		 int 44, label %bb866.i
+ 		 int 103, label %bb874.i
+ 		 int 114, label %bb874.i
+ 	]
+ 
+ bb866.i.loopexit:		; preds = %bb874.i
+ 	br label %bb866.i
+ 
+ bb866.i.loopexit31:		; preds = %cond_true903.i
+ 	br label %bb866.i
+ 
+ bb866.i:		; preds = %bb866.i.loopexit31, %bb866.i.loopexit, %bb857.i, %recog_memoized.exit52
+ 	br bool false, label %bb907.i, label %bb857.i
+ 
+ bb874.i.preheader.loopexit:		; preds = %cond_true903.i, %cond_true903.i
+ 	ret void
+ 
+ bb874.i:		; preds = %bb857.i, %bb857.i, %recog_memoized.exit52, %recog_memoized.exit52
+ 	%tmp862.i494.25 = phi sbyte* [ %tmp862.i494.24, %bb857.i ], [ %tmp862.i494.24, %bb857.i ], [ undef, %recog_memoized.exit52 ], [ undef, %recog_memoized.exit52 ]		; <sbyte*> [#uses=1]
+ 	switch int 0, label %bb886.i.preheader.loopexit [
+ 		 int 0, label %bb907.i
+ 		 int 44, label %bb866.i.loopexit
+ 		 int 103, label %bb874.i.backedge
+ 		 int 114, label %bb874.i.backedge
+ 	]
+ 
+ bb874.i.backedge:		; preds = %bb874.i, %bb874.i
+ 	ret void
+ 
+ bb886.i.preheader.loopexit:		; preds = %bb874.i
+ 	ret void
+ 
+ bb886.i.preheader:		; preds = %bb857.i, %recog_memoized.exit52
+ 	%tmp862.i494.26 = phi sbyte* [ undef, %recog_memoized.exit52 ], [ %tmp862.i494.24, %bb857.i ]		; <sbyte*> [#uses=1]
+ 	br label %bb886.i
+ 
+ bb886.i:		; preds = %cond_true903.i, %bb886.i.preheader
+ 	br bool false, label %bb857.i, label %cond_true903.i
+ 
+ cond_true903.i:		; preds = %bb886.i
+ 	switch int 0, label %bb886.i [
+ 		 int 0, label %bb907.i
+ 		 int 44, label %bb866.i.loopexit31
+ 		 int 103, label %bb874.i.preheader.loopexit
+ 		 int 114, label %bb874.i.preheader.loopexit
+ 	]
+ 
+ bb907.i:		; preds = %cond_true903.i, %bb874.i, %bb866.i, %bb857.i, %recog_memoized.exit52
+ 	%tmp862.i494.0 = phi sbyte* [ %tmp862.i494.24, %bb857.i ], [ null, %bb866.i ], [ undef, %recog_memoized.exit52 ], [ %tmp862.i494.25, %bb874.i ], [ null, %cond_true903.i ]		; <sbyte*> [#uses=1]
+ 	br bool false, label %cond_next1146.i, label %cond_true910.i
+ 
+ cond_true910.i:		; preds = %bb907.i
+ 	ret void
+ 
+ cond_next1146.i:		; preds = %bb907.i, %cond_true818.i, %cond_true813.i
+ 	%tmp862.i494.1 = phi sbyte* [ %tmp862.i494.0, %bb907.i ], [ undef, %cond_true818.i ], [ undef, %cond_true813.i ]		; <sbyte*> [#uses=0]
+ 	ret void
+ 
+ bb2060.i:		; No predecessors!
+ 	br bool false, label %cond_true2064.i, label %bb2067.i
+ 
+ cond_true2064.i:		; preds = %bb2060.i
+ 	unreachable
+ 
+ bb2067.i:		; preds = %bb2060.i
+ 	ret void
+ 
+ cond_next3473:		; No predecessors!
+ 	ret void
+ 
+ cond_next3521:		; No predecessors!
+ 	ret void
+ }





From lattner at cs.uiuc.edu  Wed Sep  6 20:59:48 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 6 Sep 2006 20:59:48 -0500
Subject: [llvm-commits] CVS:
	llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Message-ID: <200609070159.k871xmfP007396@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAGISel.cpp updated: 1.272 -> 1.273
---
Log message:

Fix CodeGen/Generic/2006-09-06-SwitchLowering.ll, a bug where SDIsel inserted
too many phi operands when lowering a switch to branches in some cases.


---
Diffs of the changes:  (+32 -15)

 SelectionDAGISel.cpp |   47 ++++++++++++++++++++++++++++++++---------------
 1 files changed, 32 insertions(+), 15 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.272 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.273
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.272	Mon Sep  4 21:31:13 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	Wed Sep  6 20:59:34 2006
@@ -922,7 +922,6 @@
   // If the switch has more than 5 blocks, and at least 31.25% dense, and the 
   // target supports indirect branches, then emit a jump table rather than 
   // lowering the switch to a binary tree of conditional branches.
-  // FIXME: Make this work with PIC code
   if (TLI.isOperationLegal(ISD::BRIND, TLI.getPointerTy()) &&
       Cases.size() > 5) {
     uint64_t First = cast<ConstantIntegral>(Cases.front().first)->getRawValue();
@@ -3412,12 +3411,14 @@
 
   // Emit constants only once even if used by multiple PHI nodes.
   std::map<Constant*, unsigned> ConstantsOut;
-
+  
   // Check successor nodes PHI nodes that expect a constant to be available from
   // this block.
   TerminatorInst *TI = LLVMBB->getTerminator();
   for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
     BasicBlock *SuccBB = TI->getSuccessor(succ);
+    if (!isa<PHINode>(SuccBB->begin())) continue;
+    
     MachineBasicBlock::iterator MBBI = FuncInfo.MBBMap[SuccBB]->begin();
     PHINode *PN;
 
@@ -3589,31 +3590,47 @@
   
   // If we generated any switch lowering information, build and codegen any
   // additional DAGs necessary.
-  for(unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
+  for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
     SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>());
     CurDAG = &SDAG;
     SelectionDAGLowering SDL(SDAG, TLI, FuncInfo);
+    
     // Set the current basic block to the mbb we wish to insert the code into
     BB = SwitchCases[i].ThisBB;
     SDL.setCurrentBasicBlock(BB);
+    
     // Emit the code
     SDL.visitSwitchCase(SwitchCases[i]);
     SDAG.setRoot(SDL.getRoot());
     CodeGenAndEmitDAG(SDAG);
-    // Iterate over the phi nodes, if there is a phi node in a successor of this
-    // block (for instance, the default block), then add a pair of operands to
-    // the phi node for this block, as if we were coming from the original
-    // BB before switch expansion.
-    for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
-      MachineInstr *PHI = PHINodesToUpdate[pi].first;
-      MachineBasicBlock *PHIBB = PHI->getParent();
-      assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
-             "This is not a machine PHI node that we are updating!");
-      if (PHIBB == SwitchCases[i].LHSBB || PHIBB == SwitchCases[i].RHSBB) {
-        PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
-        PHI->addMachineBasicBlockOperand(BB);
+    
+    // Handle any PHI nodes in successors of this chunk, as if we were coming
+    // from the original BB before switch expansion.  Note that PHI nodes can
+    // occur multiple times in PHINodesToUpdate.  We have to be very careful to
+    // handle them the right number of times.
+    while ((BB = SwitchCases[i].LHSBB)) {  // Handle LHS and RHS.
+      for (MachineBasicBlock::iterator Phi = BB->begin();
+           Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
+        // This value for this PHI node is recorded in PHINodesToUpdate, get it.
+        for (unsigned pn = 0; ; ++pn) {
+          assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!");
+          if (PHINodesToUpdate[pn].first == Phi) {
+            Phi->addRegOperand(PHINodesToUpdate[pn].second, false);
+            Phi->addMachineBasicBlockOperand(SwitchCases[i].ThisBB);
+            break;
+          }
+        }
       }
+      
+      // Don't process RHS if same block as LHS.
+      if (BB == SwitchCases[i].RHSBB)
+        SwitchCases[i].RHSBB = 0;
+      
+      // If we haven't handled the RHS, do so now.  Otherwise, we're done.
+      SwitchCases[i].LHSBB = SwitchCases[i].RHSBB;
+      SwitchCases[i].RHSBB = 0;
     }
+    assert(SwitchCases[i].LHSBB == 0 && SwitchCases[i].RHSBB == 0);
   }
 }
 





From lattner at cs.uiuc.edu  Wed Sep  6 23:19:23 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed, 6 Sep 2006 23:19:23 -0500
Subject: [llvm-commits] CVS: llvm/docs/GettingStarted.html
Message-ID: <200609070419.k874JNgT009937@zion.cs.uiuc.edu>



Changes in directory llvm/docs:

GettingStarted.html updated: 1.144 -> 1.145
---
Log message:

cleanups and updates to the GSG, patch by B Scott Michel, thanks!
This is PR899: http://llvm.org/PR899 


---
Diffs of the changes:  (+53 -42)

 GettingStarted.html |   95 +++++++++++++++++++++++++++++-----------------------
 1 files changed, 53 insertions(+), 42 deletions(-)


Index: llvm/docs/GettingStarted.html
diff -u llvm/docs/GettingStarted.html:1.144 llvm/docs/GettingStarted.html:1.145
--- llvm/docs/GettingStarted.html:1.144	Sun Aug 27 19:34:18 2006
+++ llvm/docs/GettingStarted.html	Wed Sep  6 23:19:09 2006
@@ -52,6 +52,10 @@
     </ol></li>
 
   <li><a href="#tutorial">An Example Using the LLVM Tool Chain</a>
+      <ol>
+         <li><a href="#tutorial4">Example with llvm-gcc4</a></li>
+         <li><a href="#tutorial3">Example with llvm-gcc3</a></li>
+      </ol>
   <li><a href="#problems">Common Problems</a>
   <li><a href="#links">Links</a>
 </ul>
@@ -206,7 +210,7 @@
 
 <p>LLVM is known to work on the following platforms:</p>
 
-<table cellpadding="3">
+<table cellpadding="3" summary="Known LLVM platforms">
 <tr>
   <th>OS</th>
   <th>Arch</th>
@@ -257,7 +261,7 @@
 
 <p>LLVM has partial support for the following platforms:</p>
 
-<table>
+<table summary="LLVM partial platform support">
 <tr>
   <th>OS</th>
   <th>Arch</th>
@@ -347,7 +351,7 @@
   is the usual name for the software package that LLVM depends on. The Version
   column provides "known to work" versions of the package. The Notes column
   describes how LLVM uses the package and provides other details.</p>
-  <table>
+  <table summary="Packages required to compile LLVM">
     <tr><th>Package</th><th>Version</th><th>Notes</th></tr>
 
     <tr>
@@ -439,7 +443,7 @@
   <p><b>Notes:</b></p>
   <div class="doc_notes">
   <ol>
-    <li><a name="sf3">Only the C and C++ languages are needed so there's no
+    <li><a name="sf1">Only the C and C++ languages are needed so there's no
       need to build the other languages for LLVM's purposes.</a> See 
       <a href="#brokengcc">below</a> for specific version info.</li>
     <li><a name="sf2">You only need CVS if you intend to build from the 
@@ -566,14 +570,14 @@
     <dt>SRC_ROOT
     <dd>
     This is the top level directory of the LLVM source tree.
-    <p>
+    <br><br>
 
     <dt>OBJ_ROOT
     <dd>
     This is the top level directory of the LLVM object tree (i.e. the
     tree where object files and compiled programs will be placed.  It
     can be the same as SRC_ROOT).
-    <p>
+    <br><br>
 
     <dt>LLVMGCCDIR
     <dd>
@@ -765,7 +769,7 @@
 <p>The following environment variables are used by the <tt>configure</tt>
 script to configure the build system:</p>
 
-<table>
+<table summary="LLVM configure script environment variables">
   <tr><th>Variable</th><th>Purpose</th></tr>
   <tr>
     <td>CC</td>
@@ -807,14 +811,14 @@
   dejagnu based test suite in <tt>llvm/test</tt>. If you don't specify this
   option, the LLVM configure script will search for the tcl 8.4 and 8.3
   releases.
-  <p></p>
+  <br><br>
   </dd>
   <dt><i>--enable-optimized</i></dt>
   <dd>
     Enables optimized compilation by default (debugging symbols are removed
     and GCC optimization flags are enabled).  The default is to use an
     unoptimized build (also known as a debug build).
-    <p></p>
+    <br><br>
   </dd>
   <dt><i>--enable-debug-runtime</i></dt>
   <dd>
@@ -827,7 +831,7 @@
     available
     on all platforms.  The default is dependent on platform, so it is best
     to explicitly enable it if you want it.
-    <p></p>
+    <br><br>
   </dd>
   <dt><i>--enable-targets=</i><tt>target-option</tt></dt>
   <dd>Controls which targets will be built and linked into llc. The default 
@@ -838,7 +842,7 @@
   separated list of target names that you want available in llc. The target 
   names use all lower case. The current set of targets is: <br/>
   <tt>alpha, ia64, powerpc, skeleton, sparc, x86</tt>.
-  <p></p></dd>
+  <br><br></dd>
   <dt><i>--enable-doxygen</i></dt>
   <dd>Look for the doxygen program and enable construction of doxygen based
   documentation from the source code. This is disabled by default because 
@@ -852,12 +856,12 @@
     <li>Change directory into the object root directory:
     <br>
     <tt>cd <i>OBJ_ROOT</i></tt>
-    <p>
+    <br><br>
 
     <li>Run the <tt>configure</tt> script located in the LLVM source tree:
     <br>
     <tt><i>SRC_ROOT</i>/configure --prefix=/install/path [other options]</tt>
-    <p>
+    <br><br>
 </ol>
 
 </div>
@@ -879,7 +883,7 @@
     <tt>--enable-optimized</tt> option was used during configuration).  The
     build system will compile the tools and libraries with debugging
     information.
-    <p>
+    <br><br>
 
     <dt>Release (Optimized) Builds
     <dd>
@@ -888,7 +892,7 @@
     <tt>gmake</tt> command line.  For these builds, the build system will
     compile the tools and libraries with GCC optimizations enabled and strip
     debugging information from the libraries and executables it generates. 
-    <p>
+    <br><br>
 
     <dt>Profile Builds
     <dd>
@@ -921,14 +925,14 @@
   <dd>
   Removes all files generated by the build.  This includes object files,
   generated C/C++ files, libraries, and executables.
-  <p>
+  <br><br>
 
   <dt><tt>gmake dist-clean</tt>
   <dd>
   Removes everything that <tt>gmake clean</tt> does, but also removes files
   generated by <tt>configure</tt>.  It attempts to return the source tree to the
   original state in which it was shipped.
-  <p>
+  <br><br>
 
   <dt><tt>gmake install</tt>
   <dd>
@@ -936,15 +940,15 @@
   hierarchy 
   under $PREFIX, specified with <tt>./configure --prefix=[dir]</tt>, which 
   defaults to <tt>/usr/local</tt>.
-  <p>
-  
+  <br><br>
+
   <dt><tt>gmake -C runtime install-bytecode</tt>
   <dd>
   Assuming you built LLVM into $OBJDIR, when this command is run, it will 
   install bytecode libraries into the GCC front end's bytecode library 
   directory.  If you need to update your bytecode libraries,
   this is the target to use once you've built them.
-  <p>
+  <br><br>
 </dl>
 
 <p>Please see the <a href="MakefileGuide.html">Makefile Guide</a> for further
@@ -958,27 +962,27 @@
   <dt><tt>gmake ENABLE_OPTIMIZED=1</tt>
   <dd>
   Perform a Release (Optimized) build.
-  <p>
+  <br><br>
 
   <dt><tt>gmake ENABLE_OPTIMIZED=1 DISABLE_ASSERTIONS=1</tt>
   <dd>
   Perform a Release (Optimized) build without assertions enabled.
-  <p>
+  <br><br>
 
   <dt><tt>gmake ENABLE_PROFILING=1</tt>
   <dd>
   Perform a Profiling build.
-  <p>
+  <br><br>
 
   <dt><tt>gmake VERBOSE=1</tt>
   <dd>
   Print what <tt>gmake</tt> is doing on standard output.
-  <p>
+  <br><br>
 
   <dt><tt>gmake TOOL_VERBOSE=1</tt></dt>
   <dd>Ask each tool invoked by the makefiles to print out what it is doing on 
   the standard output. This also implies <tt>VERBOSE=1</tt>.
-  <p></dd>
+  <br><br></dd>
 </dl>
 
 <p>Every directory in the LLVM object tree includes a <tt>Makefile</tt> to build
@@ -1069,7 +1073,7 @@
     <dt>Libraries
     <dd><tt><i>OBJ_ROOT</i>/Debug/lib</tt>
   </dl>
-  <p>
+  <br><br>
 
   <dt>Release Builds
   <dd>
@@ -1079,7 +1083,7 @@
     <dt>Libraries
     <dd><tt><i>OBJ_ROOT</i>/Release/lib</tt>
   </dl>
-  <p>
+  <br><br>
 
   <dt>Profile Builds
   <dd>
@@ -1413,7 +1417,7 @@
   that finds differences between code that LLC generates and code that LLI
   generates. This is a useful tool if you are debugging one of them,
   assuming that the other generates correct output. For the full user
-  manual, run <tt>`perldoc codegen-diff'</tt>.<p>
+  manual, run <tt>`perldoc codegen-diff'</tt>.<br><br>
 
   <dt><tt><b>cvsupdate</b></tt> <dd><tt>cvsupdate</tt> is a script that will
   update your CVS tree, but produce a much cleaner and more organized output
@@ -1421,21 +1425,21 @@
   together all the new and updated files and modified files in separate
   sections, so you can see at a glance what has changed. If you are at the
   top of your LLVM CVS tree, running <tt>utils/cvsupdate</tt> is the
-  preferred way of updating the tree.<p>
+  preferred way of updating the tree.<br><br>
 
   <dt><tt><b>emacs/</b></tt> <dd>The <tt>emacs</tt> directory contains
   syntax-highlighting files which will work with Emacs and XEmacs editors,
   providing syntax highlighting support for LLVM assembly files and TableGen
   description files. For information on how to use the syntax files, consult
-  the <tt>README</tt> file in that directory.<p>
+  the <tt>README</tt> file in that directory.<br><br>
 
   <dt><tt><b>getsrcs.sh</b></tt> <dd>The <tt>getsrcs.sh</tt> script finds
   and outputs all non-generated source files, which is useful if one wishes
   to do a lot of development across directories and does not want to
   individually find each file. One way to use it is to run, for example:
   <tt>xemacs `utils/getsources.sh`</tt> from the top of your LLVM source
-  tree.<p>
-  
+  tree.<br><br>
+
   <dt><tt><b>llvmgrep</b></tt></dt>
   <dd>This little tool performs an "egrep -H -n" on each source file in LLVM and
   passes to it a regular expression provided on <tt>llvmgrep</tt>'s command
@@ -1448,24 +1452,24 @@
   <tt>llvm/lib/Target/Sparc</tt>, if <tt>makellvm</tt> is in your path,
   simply running <tt>makellvm llc</tt> will make a build of the current
   directory, switch to directory <tt>llvm/tools/llc</tt> and build it,
-  causing a re-linking of LLC.<p>
+  causing a re-linking of LLC.<br><br>
 
   <dt><tt><b>NightlyTest.pl</b></tt> and
   <tt><b>NightlyTestTemplate.html</b></tt> <dd>These files are used in a
   cron script to generate nightly status reports of the functionality of
   tools, and the results can be seen by following the appropriate link on
-  the <a href="http://llvm.org/">LLVM homepage</a>.<p>
+  the <a href="http://llvm.org/">LLVM homepage</a>.<br><br>
 
   <dt><tt><b>TableGen/</b></tt> <dd>The <tt>TableGen</tt> directory contains
   the tool used to generate register descriptions, instruction set
   descriptions, and even assemblers from common TableGen description
-  files.<p>
+  files.<br><br>
 
   <dt><tt><b>vim/</b></tt> <dd>The <tt>vim</tt> directory contains
   syntax-highlighting files which will work with the VIM editor, providing
   syntax highlighting support for LLVM assembly files and TableGen
   description files. For information on how to use the syntax files, consult
-  the <tt>README</tt> file in that directory.<p>
+  the <tt>README</tt> file in that directory.<br><br>
 
 </dl>
 
@@ -1490,10 +1494,17 @@
 <p>This section gives an example of using LLVM.  Since we are currently 
 transitioning from llvm-gcc3 to llvm-gcc4, we include examples for both.
 </p>
+
+<p><b>Note:</b> The <i>gcc4</i> frontend's invocation is <b><i>considerably different</i></b>
+from the previous <i>gcc3</i> frontend. In particular, the <i>gcc4</i> frontend <b><i>does not</i></b>
+create bytecode by default: <i>gcc4</i> produces native code. As the example below illustrates,
+the '--emit-llvm' flag is needed to produce LLVM bytecode output. For <i>makefiles</i> and
+<i>configure</i> scripts, the CFLAGS variable needs '--emit-llvm' to produce bytecode
+output.</p>
 </div>
 
 <!-- ======================================================================= -->
-<div class="doc_subsection"><a name="tutorial3">Example with llvm-gcc4</a></div>
+<div class="doc_subsection"><a name="tutorial4">Example with llvm-gcc4</a></div>
 
 <div class="doc_text">
 
@@ -1540,7 +1551,7 @@
   <li><p>Use the <tt>llvm-dis</tt> utility to take a look at the LLVM assembly
       code:</p>
 
-      <p><tt>% llvm-dis &lt; hello.bc | less</tt><p></li>
+      <p><tt>% llvm-dis &lt; hello.bc | less</tt><br><br></li>
 
   <li><p>Compile the program to native assembly using the LLC code
       generator:</p>
@@ -1595,9 +1606,9 @@
 
   <li><p>Run the program. To make sure the program ran, execute one of the
       following commands:</p>
-      
+
       <p><tt>% ./hello</tt></p>
- 
+
       <p>or</p>
 
       <p><tt>% lli hello.bc</tt></p></li>
@@ -1605,7 +1616,7 @@
   <li><p>Use the <tt>llvm-dis</tt> utility to take a look at the LLVM assembly
       code:</p>
 
-      <p><tt>% llvm-dis &lt; hello.bc | less</tt><p></li>
+      <p><tt>% llvm-dis &lt; hello.bc | less</tt><br><br></li>
 
   <li><p>Compile the program to native assembly using the LLC code
       generator:</p>
@@ -1674,7 +1685,7 @@
   <a href="mailto:sabre at nondot.org">Chris Lattner</a><br>
   <a href="http://llvm.x10sys.com/rspencer/">Reid Spencer</a><br>
   <a href="http://llvm.org">The LLVM Compiler Infrastructure</a><br>
-  Last modified: $Date: 2006/08/28 00:34:18 $
+  Last modified: $Date: 2006/09/07 04:19:09 $
 </address>
 </body>
 </html>





From llvm at cs.uiuc.edu  Wed Sep  6 23:49:24 2006
From: llvm at cs.uiuc.edu (LLVM)
Date: Wed, 6 Sep 2006 23:49:24 -0500
Subject: [llvm-commits] CVS: llvm/lib/Assembly/Parser/
Message-ID: <200609070449.k874nOdN010412@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Assembly/Parser:

---
Log message:

Directory /var/cvs/llvm/llvm/lib/Assembly/Parser added to the repository


---
Diffs of the changes:  (+0 -0)

 0 files changed





From isanbard at gmail.com  Thu Sep  7 03:36:48 2006
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 7 Sep 2006 03:36:48 -0500
Subject: [llvm-commits] CVS: llvm/docs/CodeGenerator.html
Message-ID: <200609070836.k878amGK022216@zion.cs.uiuc.edu>



Changes in directory llvm/docs:

CodeGenerator.html updated: 1.37 -> 1.38
---
Log message:

Fixed my rotten Engrish grammar.


---
Diffs of the changes:  (+7 -7)

 CodeGenerator.html |   14 +++++++-------
 1 files changed, 7 insertions(+), 7 deletions(-)


Index: llvm/docs/CodeGenerator.html
diff -u llvm/docs/CodeGenerator.html:1.37 llvm/docs/CodeGenerator.html:1.38
--- llvm/docs/CodeGenerator.html:1.37	Wed Sep  6 13:42:41 2006
+++ llvm/docs/CodeGenerator.html	Thu Sep  7 03:36:28 2006
@@ -1168,9 +1168,9 @@
 
 <p>Live Intervals are the ranges (intervals) where a variable is <i>live</i>.
 They are used by some <a href="#regalloc">register allocator</a> passes to
-determine if two or more virtual registers which require the same register are
-live at the same point in the program (conflict).  When this situation occurs,
-one virtual register must be <i>spilled</i>.</p>
+determine if two or more virtual registers which require the same physical
+register are live at the same point in the program (i.e., theyconflict).  When
+this situation occurs, one virtual register must be <i>spilled</i>.</p>
 
 </div>
 
@@ -1186,10 +1186,10 @@
 instruction (i.e., the instruction calculates the value, but it is
 never used) and the set of registers that are used by the instruction,
 but are never used after the instruction (i.e., they are killed). Live
-variable information is computed for each <i>virtual</i> and
+variable information is computed for each <i>virtual</i> register and
 <i>register allocatable</i> physical register in the function.  This
 is done in a very efficient manner because it uses SSA to sparsely
-computer lifetime information for virtual registers (which are in SSA
+compute lifetime information for virtual registers (which are in SSA
 form) and only has to track physical registers within a block.  Before
 register allocation, LLVM can assume that physical registers are only
 live within a single basic block.  This allows it to do a single,
@@ -1200,7 +1200,7 @@
 <p>Physical registers may be live in to or out of a function. Live in values
 are typically arguments in registers. Live out values are typically return
 values in registers. Live in values are marked as such, and are given a dummy
-"defining" instruction during live interval analysis. If the last basic block
+"defining" instruction during live intervals analysis. If the last basic block
 of a function is a <tt>return</tt>, then it's marked as using all live out
 values in the function.</p>
 
@@ -1702,7 +1702,7 @@
 
   <a href="mailto:sabre at nondot.org">Chris Lattner</a><br>
   <a href="http://llvm.org">The LLVM Compiler Infrastructure</a><br>
-  Last modified: $Date: 2006/09/06 18:42:41 $
+  Last modified: $Date: 2006/09/07 08:36:28 $
 </address>
 
 </body>





From isanbard at gmail.com  Thu Sep  7 03:39:49 2006
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 7 Sep 2006 03:39:49 -0500
Subject: [llvm-commits] CVS: llvm/docs/CodeGenerator.html
Message-ID: <200609070839.k878dnKO022326@zion.cs.uiuc.edu>



Changes in directory llvm/docs:

CodeGenerator.html updated: 1.38 -> 1.39
---
Log message:



---
Diffs of the changes:  (+2 -2)

 CodeGenerator.html |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/docs/CodeGenerator.html
diff -u llvm/docs/CodeGenerator.html:1.38 llvm/docs/CodeGenerator.html:1.39
--- llvm/docs/CodeGenerator.html:1.38	Thu Sep  7 03:36:28 2006
+++ llvm/docs/CodeGenerator.html	Thu Sep  7 03:39:35 2006
@@ -1169,7 +1169,7 @@
 <p>Live Intervals are the ranges (intervals) where a variable is <i>live</i>.
 They are used by some <a href="#regalloc">register allocator</a> passes to
 determine if two or more virtual registers which require the same physical
-register are live at the same point in the program (i.e., theyconflict).  When
+register are live at the same point in the program (i.e., they conflict).  When
 this situation occurs, one virtual register must be <i>spilled</i>.</p>
 
 </div>
@@ -1702,7 +1702,7 @@
 
   <a href="mailto:sabre at nondot.org">Chris Lattner</a><br>
   <a href="http://llvm.org">The LLVM Compiler Infrastructure</a><br>
-  Last modified: $Date: 2006/09/07 08:36:28 $
+  Last modified: $Date: 2006/09/07 08:39:35 $
 </address>
 
 </body>





From jlaskey at apple.com  Thu Sep  7 07:24:07 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Thu, 7 Sep 2006 07:24:07 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86AsmPrinter.cpp
	X86Subtarget.h X86Subtarget.cpp
Message-ID: <200609071224.k87CO7ln001689@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86AsmPrinter.cpp updated: 1.193 -> 1.194
X86Subtarget.h updated: 1.13 -> 1.14
X86Subtarget.cpp updated: 1.28 -> 1.29
---
Log message:

Make the x86 asm flavor part of the subtarget info.


---
Diffs of the changes:  (+34 -24)

 X86AsmPrinter.cpp |   29 ++++++-----------------------
 X86Subtarget.cpp  |   16 ++++++++++++++++
 X86Subtarget.h    |   13 ++++++++++++-
 3 files changed, 34 insertions(+), 24 deletions(-)


Index: llvm/lib/Target/X86/X86AsmPrinter.cpp
diff -u llvm/lib/Target/X86/X86AsmPrinter.cpp:1.193 llvm/lib/Target/X86/X86AsmPrinter.cpp:1.194
--- llvm/lib/Target/X86/X86AsmPrinter.cpp:1.193	Wed Sep  6 13:34:40 2006
+++ llvm/lib/Target/X86/X86AsmPrinter.cpp	Thu Sep  7 07:23:47 2006
@@ -23,28 +23,11 @@
 #include "llvm/Type.h"
 #include "llvm/Assembly/Writer.h"
 #include "llvm/Support/Mangler.h"
-#include "llvm/Support/CommandLine.h"
 using namespace llvm;
 
-enum AsmWriterFlavorTy { att, intel };
-
 Statistic<> llvm::EmittedInsts("asm-printer",
                                "Number of machine instrs printed");
 
-cl::opt<AsmWriterFlavorTy>
-AsmWriterFlavor("x86-asm-syntax",
-                cl::desc("Choose style of code to emit from X86 backend:"),
-                cl::values(
-                           clEnumVal(att,   "  Emit AT&T-style assembly"),
-                           clEnumVal(intel, "  Emit Intel-style assembly"),
-                           clEnumValEnd),
-#ifdef _MSC_VER
-                cl::init(intel)
-#else
-                cl::init(att)
-#endif
-                );
-
 X86TargetAsmInfo::X86TargetAsmInfo(X86TargetMachine &TM) {
   const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
   
@@ -97,7 +80,7 @@
   default: break;
   }
   
-  if (AsmWriterFlavor == intel) {
+  if (Subtarget->isFlavorIntel()) {
     GlobalPrefix = "_";
     CommentString = ";";
   
@@ -271,12 +254,12 @@
 ///
 FunctionPass *llvm::createX86CodePrinterPass(std::ostream &o,
                                              X86TargetMachine &tm) {
+  const X86Subtarget *Subtarget = &tm.getSubtarget<X86Subtarget>();
   TargetAsmInfo *TAI = new X86TargetAsmInfo(tm);
 
-  switch (AsmWriterFlavor) {
-  default:
-    assert(0 && "Unknown asm flavor!");
-  case intel: return new X86IntelAsmPrinter(o, tm, TAI);
-  case att: return new X86ATTAsmPrinter(o, tm, TAI);
+  if (Subtarget->isFlavorIntel()) {
+    return new X86IntelAsmPrinter(o, tm, TAI);
+  } else {
+    return new X86ATTAsmPrinter(o, tm, TAI);
   }
 }


Index: llvm/lib/Target/X86/X86Subtarget.h
diff -u llvm/lib/Target/X86/X86Subtarget.h:1.13 llvm/lib/Target/X86/X86Subtarget.h:1.14
--- llvm/lib/Target/X86/X86Subtarget.h:1.13	Sun Sep  3 23:08:58 2006
+++ llvm/lib/Target/X86/X86Subtarget.h	Thu Sep  7 07:23:47 2006
@@ -22,6 +22,11 @@
 class Module;
 
 class X86Subtarget : public TargetSubtarget {
+public:
+  enum AsmWriterFlavorTy {
+    att, intel
+  };
+
 protected:
   enum X86SSEEnum {
     NoMMXSSE, MMX, SSE1, SSE2, SSE3
@@ -31,12 +36,15 @@
     NoThreeDNow, ThreeDNow, ThreeDNowA
   };
 
+  /// AsmFlavor - Which x86 asm dialect to use.
+  AsmWriterFlavorTy AsmFlavor;
+
   /// X86SSELevel - MMX, SSE1, SSE2, SSE3, or none supported.
   X86SSEEnum X86SSELevel;
 
   /// X863DNowLevel - 3DNow or 3DNow Athlon, or none supported.
   X863DNowEnum X863DNowLevel;
-
+  
   /// Is64Bit - True if the processor supports Em64T.
   bool Is64Bit;
 
@@ -80,6 +88,9 @@
   bool hasSSE3() const { return X86SSELevel >= SSE3; }
   bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
   bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
+  
+  bool isFlavorAtt() const { return AsmFlavor == att; }
+  bool isFlavorIntel() const { return AsmFlavor == intel; }
 
   bool isTargetDarwin() const { return TargetType == isDarwin; }
   bool isTargetELF() const { return TargetType == isELF; }


Index: llvm/lib/Target/X86/X86Subtarget.cpp
diff -u llvm/lib/Target/X86/X86Subtarget.cpp:1.28 llvm/lib/Target/X86/X86Subtarget.cpp:1.29
--- llvm/lib/Target/X86/X86Subtarget.cpp:1.28	Fri Jun 16 16:58:49 2006
+++ llvm/lib/Target/X86/X86Subtarget.cpp	Thu Sep  7 07:23:47 2006
@@ -13,9 +13,24 @@
 
 #include "X86Subtarget.h"
 #include "llvm/Module.h"
+#include "llvm/Support/CommandLine.h"
 #include "X86GenSubtarget.inc"
 using namespace llvm;
 
+cl::opt<X86Subtarget::AsmWriterFlavorTy>
+AsmWriterFlavor("x86-asm-syntax",
+  cl::desc("Choose style of code to emit from X86 backend:"),
+  cl::values(
+    clEnumValN(X86Subtarget::att,   "att",   "  Emit AT&T-style assembly"),
+    clEnumValN(X86Subtarget::intel, "intel", "  Emit Intel-style assembly"),
+    clEnumValEnd),
+#ifdef _MSC_VER
+  cl::init(X86Subtarget::intel)
+#else
+  cl::init(X86Subtarget::att)
+#endif
+                );
+
 /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
 /// specified arguments.  If we can't run cpuid on the host, return true.
 static bool GetCpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
@@ -151,6 +166,7 @@
   MinRepStrSizeThreshold = 128;
   X86SSELevel = NoMMXSSE;
   X863DNowLevel = NoThreeDNow;
+  AsmFlavor = AsmWriterFlavor;
   Is64Bit = false;
 
   // Determine default and user specified characteristics





From lattner at cs.uiuc.edu  Thu Sep  7 12:34:41 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 7 Sep 2006 12:34:41 -0500
Subject: [llvm-commits] CVS: llvm/docs/GettingStarted.html
Message-ID: <200609071734.k87HYf5P007429@zion.cs.uiuc.edu>



Changes in directory llvm/docs:

GettingStarted.html updated: 1.145 -> 1.146
---
Log message:

Warn people not to use GCC 4.1.1.


---
Diffs of the changes:  (+4 -1)

 GettingStarted.html |    5 ++++-
 1 files changed, 4 insertions(+), 1 deletion(-)


Index: llvm/docs/GettingStarted.html
diff -u llvm/docs/GettingStarted.html:1.145 llvm/docs/GettingStarted.html:1.146
--- llvm/docs/GettingStarted.html:1.145	Wed Sep  6 23:19:09 2006
+++ llvm/docs/GettingStarted.html	Thu Sep  7 12:34:27 2006
@@ -530,6 +530,9 @@
 <p><b>Apple Xcode 2.3</b>: GCC crashes when compiling LLVM at -O3 (which is the
    default with ENABLE_OPTIMIZED=1.  To work around this, build with 
    "ENABLE_OPTIMIZED=1 OPTIMIZE_OPTION=-O2".</p>
+<p><b>GCC 4.1.1</b>: GCC fails to build LLVM with template concept check errors
+      compiling some files.  At the time of this writing, GCC mainline (4.2)
+      did not share the problem.</p>
 </div>
 
 
@@ -1685,7 +1688,7 @@
   <a href="mailto:sabre at nondot.org">Chris Lattner</a><br>
   <a href="http://llvm.x10sys.com/rspencer/">Reid Spencer</a><br>
   <a href="http://llvm.org">The LLVM Compiler Infrastructure</a><br>
-  Last modified: $Date: 2006/09/07 04:19:09 $
+  Last modified: $Date: 2006/09/07 17:34:27 $
 </address>
 </body>
 </html>





From lattner at cs.uiuc.edu  Thu Sep  7 12:44:13 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 7 Sep 2006 12:44:13 -0500
Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/ARM/select.ll
Message-ID: <200609071744.k87HiDS7007594@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CodeGen/ARM:

select.ll updated: 1.5 -> 1.6
---
Log message:

This fails


---
Diffs of the changes:  (+1 -0)

 select.ll |    1 +
 1 files changed, 1 insertion(+)


Index: llvm/test/Regression/CodeGen/ARM/select.ll
diff -u llvm/test/Regression/CodeGen/ARM/select.ll:1.5 llvm/test/Regression/CodeGen/ARM/select.ll:1.6
--- llvm/test/Regression/CodeGen/ARM/select.ll:1.5	Tue Aug 22 11:19:54 2006
+++ llvm/test/Regression/CodeGen/ARM/select.ll	Thu Sep  7 12:43:59 2006
@@ -1,4 +1,5 @@
 ; RUN: llvm-as < %s | llc -march=arm
+; XFAIL: *
 
 int %f(int %a) {
 entry:





From lattner at cs.uiuc.edu  Thu Sep  7 13:20:59 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 7 Sep 2006 13:20:59 -0500
Subject: [llvm-commits] CVS: llvm/lib/VMCore/Mangler.cpp
Message-ID: <200609071820.k87IKxac008269@zion.cs.uiuc.edu>



Changes in directory llvm/lib/VMCore:

Mangler.cpp updated: 1.28 -> 1.29
---
Log message:

Add new option to leave asm names alone


---
Diffs of the changes:  (+6 -1)

 Mangler.cpp |    7 ++++++-
 1 files changed, 6 insertions(+), 1 deletion(-)


Index: llvm/lib/VMCore/Mangler.cpp
diff -u llvm/lib/VMCore/Mangler.cpp:1.28 llvm/lib/VMCore/Mangler.cpp:1.29
--- llvm/lib/VMCore/Mangler.cpp:1.28	Wed Jun  7 18:03:13 2006
+++ llvm/lib/VMCore/Mangler.cpp	Thu Sep  7 13:20:41 2006
@@ -33,6 +33,10 @@
   std::string Result;
   if (X.empty()) return X;  // Empty names are uniqued by the caller.
   
+  // If PreserveAsmNames is set, names with asm identifiers are not modified. 
+  if (PreserveAsmNames && X[0] == 1)
+    return X;
+  
   if (!UseQuotes) {
     // If X does not start with (char)1, add the prefix.
     std::string::const_iterator I = X.begin();
@@ -174,7 +178,8 @@
 
 
 Mangler::Mangler(Module &M, const char *prefix)
-  : Prefix(prefix), UseQuotes(false), Count(0), TypeCounter(0) {
+  : Prefix(prefix), UseQuotes(false), PreserveAsmNames(false),
+    Count(0), TypeCounter(0) {
   std::fill(AcceptableChars, 
           AcceptableChars+sizeof(AcceptableChars)/sizeof(AcceptableChars[0]),
             0);





From lattner at cs.uiuc.edu  Thu Sep  7 13:20:59 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 7 Sep 2006 13:20:59 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/Support/Mangler.h
Message-ID: <200609071820.k87IKxDq008271@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/Support:

Mangler.h updated: 1.21 -> 1.22
---
Log message:

Add new option to leave asm names alone


---
Diffs of the changes:  (+8 -0)

 Mangler.h |    8 ++++++++
 1 files changed, 8 insertions(+)


Index: llvm/include/llvm/Support/Mangler.h
diff -u llvm/include/llvm/Support/Mangler.h:1.21 llvm/include/llvm/Support/Mangler.h:1.22
--- llvm/include/llvm/Support/Mangler.h:1.21	Wed Jul 26 11:18:00 2006
+++ llvm/include/llvm/Support/Mangler.h	Thu Sep  7 13:20:41 2006
@@ -35,6 +35,10 @@
   /// the space character.  By default, this is false.
   bool UseQuotes;
   
+  /// PreserveAsmNames - If this is set, the asm escape character is not removed
+  /// from names with 'asm' specifiers. 
+  bool PreserveAsmNames;
+  
   /// Memo - This is used to remember the name that we assign a value.
   ///
   std::map<const Value*, std::string> Memo;
@@ -66,6 +70,10 @@
   /// strings for assembler labels.
   void setUseQuotes(bool Val) { UseQuotes = Val; }
   
+  /// setPreserveAsmNames - If the mangler should not strip off the asm name
+  /// identifier (\001), this should be set.
+  void setPreserveAsmNames(bool Val) { PreserveAsmNames = Val; }
+  
   /// Acceptable Characters - This allows the target to specify which characters
   /// are acceptable to the assembler without being mangled.  By default we
   /// allow letters, numbers, '_', '$', and '.', which is what GAS accepts.





From lattner at cs.uiuc.edu  Thu Sep  7 13:21:21 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 7 Sep 2006 13:21:21 -0500
Subject: [llvm-commits] CVS: llvm/tools/bugpoint/Miscompilation.cpp
Message-ID: <200609071821.k87ILL48008292@zion.cs.uiuc.edu>



Changes in directory llvm/tools/bugpoint:

Miscompilation.cpp updated: 1.76 -> 1.77
---
Log message:

Change DisambiguateGlobalSymbols to not rename asm globals, which breaks
bugpoint on leopard.


---
Diffs of the changes:  (+1 -0)

 Miscompilation.cpp |    1 +
 1 files changed, 1 insertion(+)


Index: llvm/tools/bugpoint/Miscompilation.cpp
diff -u llvm/tools/bugpoint/Miscompilation.cpp:1.76 llvm/tools/bugpoint/Miscompilation.cpp:1.77
--- llvm/tools/bugpoint/Miscompilation.cpp:1.76	Wed Aug 23 15:34:57 2006
+++ llvm/tools/bugpoint/Miscompilation.cpp	Thu Sep  7 13:21:07 2006
@@ -234,6 +234,7 @@
   Mangler Mang(*M);
   // Agree with the CBE on symbol naming
   Mang.markCharUnacceptable('.');
+  Mang.setPreserveAsmNames(true);
   for (Module::global_iterator I = M->global_begin(), E = M->global_end();
        I != E; ++I)
     I->setName(Mang.getValueName(I));





From evan.cheng at apple.com  Thu Sep  7 13:50:35 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 7 Sep 2006 13:50:35 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/AsmPrinter.cpp
Message-ID: <200609071850.k87IoZAj008772@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen:

AsmPrinter.cpp updated: 1.91 -> 1.92
---
Log message:

Fix pasto that was breaking x86 tests.

---
Diffs of the changes:  (+2 -2)

 AsmPrinter.cpp |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/lib/CodeGen/AsmPrinter.cpp
diff -u llvm/lib/CodeGen/AsmPrinter.cpp:1.91 llvm/lib/CodeGen/AsmPrinter.cpp:1.92
--- llvm/lib/CodeGen/AsmPrinter.cpp:1.91	Wed Sep  6 13:34:40 2006
+++ llvm/lib/CodeGen/AsmPrinter.cpp	Thu Sep  7 13:50:20 2006
@@ -132,10 +132,10 @@
     if (TAI->getFourByteConstantSection() &&
         TM.getTargetData()->getTypeSize(Ty) == 4)
       FourByteCPs.push_back(std::make_pair(CPE, i));
-    else if (TAI->getSectionEndDirectiveSuffix() &&
+    else if (TAI->getEightByteConstantSection() &&
              TM.getTargetData()->getTypeSize(Ty) == 8)
       EightByteCPs.push_back(std::make_pair(CPE, i));
-    else if (TAI->getSectionEndDirectiveSuffix() &&
+    else if (TAI->getSixteenByteConstantSection() &&
              TM.getTargetData()->getTypeSize(Ty) == 16)
       SixteenByteCPs.push_back(std::make_pair(CPE, i));
     else





From evan.cheng at apple.com  Thu Sep  7 14:04:02 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 7 Sep 2006 14:04:02 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.td
Message-ID: <200609071904.k87J42q7009074@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86InstrInfo.td updated: 1.282 -> 1.283
---
Log message:

Consistency.

---
Diffs of the changes:  (+1 -1)

 X86InstrInfo.td |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.282 llvm/lib/Target/X86/X86InstrInfo.td:1.283
--- llvm/lib/Target/X86/X86InstrInfo.td:1.282	Fri Aug 11 04:03:33 2006
+++ llvm/lib/Target/X86/X86InstrInfo.td	Thu Sep  7 14:03:48 2006
@@ -383,7 +383,7 @@
         I<opcode, RawFrm, ops, asm, pattern>;
 
 // Indirect branches
-let isBarrier = 1 in
+let isBranch = 1, isBarrier = 1 in
   def JMP : IBr<0xE9, (ops brtarget:$dst), "jmp $dst", [(br bb:$dst)]>;
 
 let isBranch = 1, isTerminator = 1, noResults = 1, isBarrier = 1 in {





From dpatel at apple.com  Thu Sep  7 15:21:11 2006
From: dpatel at apple.com (Devang Patel)
Date: Thu, 7 Sep 2006 15:21:11 -0500
Subject: [llvm-commits] CVS: llvm/tools/lto/lto.cpp
Message-ID: <200609072021.k87KLBcB010339@zion.cs.uiuc.edu>



Changes in directory llvm/tools/lto:

lto.cpp updated: 1.12 -> 1.13
---
Log message:

Use addPassesToEmitWholeFile() instead of addPassesToEmitFile()


---
Diffs of the changes:  (+1 -1)

 lto.cpp |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/tools/lto/lto.cpp
diff -u llvm/tools/lto/lto.cpp:1.12 llvm/tools/lto/lto.cpp:1.13
--- llvm/tools/lto/lto.cpp:1.12	Wed Sep  6 15:16:28 2006
+++ llvm/tools/lto/lto.cpp	Thu Sep  7 15:20:56 2006
@@ -282,7 +282,7 @@
   // Make sure everything is still good.
   Passes.add(createVerifierPass());
 
-  Target.addPassesToEmitFile(Passes, Out, TargetMachine::AssemblyFile, true);
+  Target.addPassesToEmitWholeFile(Passes, Out, TargetMachine::AssemblyFile, true);
 
   // Run our queue of passes all at once now, efficiently.
   Passes.run(*M);





From dpatel at apple.com  Thu Sep  7 15:22:12 2006
From: dpatel at apple.com (Devang Patel)
Date: Thu, 7 Sep 2006 15:22:12 -0500
Subject: [llvm-commits] CVS: llvm/tools/Makefile
Message-ID: <200609072022.k87KMCWd010373@zion.cs.uiuc.edu>



Changes in directory llvm/tools:

Makefile updated: 1.54 -> 1.55
---
Log message:

Add lto into the list of PARALLEL_DIRS


---
Diffs of the changes:  (+2 -1)

 Makefile |    3 ++-
 1 files changed, 2 insertions(+), 1 deletion(-)


Index: llvm/tools/Makefile
diff -u llvm/tools/Makefile:1.54 llvm/tools/Makefile:1.55
--- llvm/tools/Makefile:1.54	Tue Aug 22 19:12:11 2006
+++ llvm/tools/Makefile	Thu Sep  7 15:21:58 2006
@@ -18,6 +18,7 @@
 		 bugpoint llvm-db llvm-extract \
                  gccas llvm-bcanalyzer llvm-stub \
 		 gccld llvm2cpp \
-                 llvm-ld llvmc llvm-prof
+                 llvm-ld llvmc llvm-prof \
+                 lto
 
 include $(LEVEL)/Makefile.common





From lattner at cs.uiuc.edu  Thu Sep  7 15:32:15 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 7 Sep 2006 15:32:15 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp
Message-ID: <200609072032.k87KWFQI010571@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.166 -> 1.167
---
Log message:

Some notes on better load folding we could do


---
Diffs of the changes:  (+2 -0)

 X86RegisterInfo.cpp |    2 ++
 1 files changed, 2 insertions(+)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.166 llvm/lib/Target/X86/X86RegisterInfo.cpp:1.167
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.166	Tue Sep  5 03:32:49 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp	Thu Sep  7 15:32:01 2006
@@ -520,6 +520,7 @@
       { X86::TEST16rr,        X86::TEST16rm },
       { X86::TEST32rr,        X86::TEST32rm },
       { X86::TEST8rr,         X86::TEST8rm },
+      // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
       { X86::UCOMISDrr,       X86::UCOMISDrm },
       { X86::UCOMISSrr,       X86::UCOMISSrm },
       { X86::XCHG16rr,        X86::XCHG16rm },
@@ -667,6 +668,7 @@
       { X86::SUBPSrr,         X86::SUBPSrm },
       { X86::SUBSDrr,         X86::SUBSDrm },
       { X86::SUBSSrr,         X86::SUBSSrm },
+      // FIXME: TEST*rr -> swapped operand of TEST*mr.
       { X86::UNPCKHPDrr,      X86::UNPCKHPDrm },
       { X86::UNPCKHPSrr,      X86::UNPCKHPSrm },
       { X86::UNPCKLPDrr,      X86::UNPCKLPDrm },





From lattner at cs.uiuc.edu  Thu Sep  7 15:33:59 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 7 Sep 2006 15:33:59 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
	X86InstrInfo.td
Message-ID: <200609072033.k87KXxdh010661@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86ISelLowering.cpp updated: 1.250 -> 1.251
X86InstrInfo.td updated: 1.283 -> 1.284
---
Log message:

Eliminate X86ISD::TEST, using X86ISD::CMP instead.  Match X86ISD::CMP patterns
using test, which provides nice simplifications like:

-       movl %edi, %ecx
-       andl $2, %ecx
-       cmpl $0, %ecx
+       testl $2, %edi
        je LBB1_11      #cond_next90

There are a couple of dagiselemitter deficiencies that this exposes, they will
be handled later.



---
Diffs of the changes:  (+35 -29)

 X86ISelLowering.cpp |   14 +++++++++-----
 X86InstrInfo.td     |   50 ++++++++++++++++++++++++++------------------------
 2 files changed, 35 insertions(+), 29 deletions(-)


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.250 llvm/lib/Target/X86/X86ISelLowering.cpp:1.251
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.250	Thu Aug 17 13:43:24 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp	Thu Sep  7 15:33:45 2006
@@ -2836,8 +2836,11 @@
       Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, MVT::i32, ShOpHi, ShAmt);
     }
 
-    SDOperand InFlag = DAG.getNode(X86ISD::TEST, MVT::Flag,
-                                   ShAmt, DAG.getConstant(32, MVT::i8));
+    SDOperand InFlag =
+      DAG.getNode(X86ISD::CMP, MVT::Flag,
+                  DAG.getNode(ISD::AND, MVT::i8, 
+                              ShAmt, DAG.getConstant(32, MVT::i8)),
+                  DAG.getConstant(0, MVT::i8));
 
     SDOperand Hi, Lo;
     SDOperand CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8);
@@ -3134,7 +3137,8 @@
 
   if (addTest) {
     CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8);
-    Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Op0, Op0);
+    Cond = DAG.getNode(X86ISD::CMP, MVT::Flag, Op0,
+                       DAG.getConstant(0, MVT::i8));
   }
 
   std::vector<MVT::ValueType> Tys;
@@ -3190,7 +3194,8 @@
 
   if (addTest) {
     CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8);
-    Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Cond, Cond);
+    Cond = DAG.getNode(X86ISD::CMP, MVT::Flag, Cond,
+                       DAG.getConstant(0, MVT::i8));
   }
   return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
                      Op.getOperand(0), Op.getOperand(2), CC, Cond);
@@ -3774,7 +3779,6 @@
   case X86ISD::TAILCALL:           return "X86ISD::TAILCALL";
   case X86ISD::RDTSC_DAG:          return "X86ISD::RDTSC_DAG";
   case X86ISD::CMP:                return "X86ISD::CMP";
-  case X86ISD::TEST:               return "X86ISD::TEST";
   case X86ISD::COMI:               return "X86ISD::COMI";
   case X86ISD::UCOMI:              return "X86ISD::UCOMI";
   case X86ISD::SETCC:              return "X86ISD::SETCC";


Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.283 llvm/lib/Target/X86/X86InstrInfo.td:1.284
--- llvm/lib/Target/X86/X86InstrInfo.td:1.283	Thu Sep  7 14:03:48 2006
+++ llvm/lib/Target/X86/X86InstrInfo.td	Thu Sep  7 15:33:45 2006
@@ -52,8 +52,6 @@
 
 def X86cmp     : SDNode<"X86ISD::CMP" ,     SDTX86CmpTest,
                         [SDNPOutFlag]>;
-def X86test    : SDNode<"X86ISD::TEST",     SDTX86CmpTest,
-                        [SDNPOutFlag]>;
 
 def X86cmov    : SDNode<"X86ISD::CMOV",     SDTX86Cmov,    
                         [SDNPInFlag, SDNPOutFlag]>;
@@ -2073,60 +2071,54 @@
 let isCommutable = 1 in {   // TEST X, Y   --> TEST Y, X
 def TEST8rr  : I<0x84, MRMDestReg, (ops GR8:$src1, GR8:$src2),
                  "test{b} {$src2, $src1|$src1, $src2}",
-                 [(X86test GR8:$src1, GR8:$src2)]>;
+                 [(X86cmp (and GR8:$src1, GR8:$src2), 0)]>;
 def TEST16rr : I<0x85, MRMDestReg, (ops GR16:$src1, GR16:$src2),
                  "test{w} {$src2, $src1|$src1, $src2}",
-                 [(X86test GR16:$src1, GR16:$src2)]>, OpSize;
+                 [(X86cmp (and GR16:$src1, GR16:$src2), 0)]>, OpSize;
 def TEST32rr : I<0x85, MRMDestReg, (ops GR32:$src1, GR32:$src2),
                  "test{l} {$src2, $src1|$src1, $src2}",
-                 [(X86test GR32:$src1, GR32:$src2)]>;
+                 [(X86cmp (and GR32:$src1, GR32:$src2), 0)]>;
 }
-def TEST8mr  : I<0x84, MRMDestMem, (ops i8mem :$src1, GR8 :$src2),
-                 "test{b} {$src2, $src1|$src1, $src2}",
-                 [(X86test (loadi8 addr:$src1), GR8:$src2)]>;
-def TEST16mr : I<0x85, MRMDestMem, (ops i16mem:$src1, GR16:$src2),
-                 "test{w} {$src2, $src1|$src1, $src2}",
-                 [(X86test (loadi16 addr:$src1), GR16:$src2)]>,
-               OpSize;
-def TEST32mr : I<0x85, MRMDestMem, (ops i32mem:$src1, GR32:$src2),
-                 "test{l} {$src2, $src1|$src1, $src2}",
-                 [(X86test (loadi32 addr:$src1), GR32:$src2)]>;
+// FIXME: These patterns are disabled until isel issue surrounding
+//CodeGen/X86/test-load-fold.ll is fixed.
 def TEST8rm  : I<0x84, MRMSrcMem, (ops GR8 :$src1, i8mem :$src2),
                  "test{b} {$src2, $src1|$src1, $src2}",
-                 [(X86test GR8:$src1, (loadi8 addr:$src2))]>;
+                 [/*(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0)*/]>;
 def TEST16rm : I<0x85, MRMSrcMem, (ops GR16:$src1, i16mem:$src2),
                  "test{w} {$src2, $src1|$src1, $src2}",
-                 [(X86test GR16:$src1, (loadi16 addr:$src2))]>,
+                 [/*(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0)*/]>,
                OpSize;
 def TEST32rm : I<0x85, MRMSrcMem, (ops GR32:$src1, i32mem:$src2),
                  "test{l} {$src2, $src1|$src1, $src2}",
-                 [(X86test GR32:$src1, (loadi32 addr:$src2))]>;
+                 [/*(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0)*/]>;
 
 def TEST8ri  : Ii8 <0xF6, MRM0r,                     // flags = GR8  & imm8
                     (ops GR8:$src1, i8imm:$src2),
                     "test{b} {$src2, $src1|$src1, $src2}",
-                    [(X86test GR8:$src1, imm:$src2)]>;
+                    [(X86cmp (and GR8:$src1, imm:$src2), 0)]>;
 def TEST16ri : Ii16<0xF7, MRM0r,                     // flags = GR16 & imm16
                     (ops GR16:$src1, i16imm:$src2),
                     "test{w} {$src2, $src1|$src1, $src2}",
-                    [(X86test GR16:$src1, imm:$src2)]>, OpSize;
+                    [(X86cmp (and GR16:$src1, imm:$src2), 0)]>, OpSize;
 def TEST32ri : Ii32<0xF7, MRM0r,                     // flags = GR32 & imm32
                     (ops GR32:$src1, i32imm:$src2),
                     "test{l} {$src2, $src1|$src1, $src2}",
-                    [(X86test GR32:$src1, imm:$src2)]>;
+                    [(X86cmp (and GR32:$src1, imm:$src2), 0)]>;
+// FIXME: These patterns are disabled until isel issue surrounding
+//CodeGen/X86/test-load-fold.ll is fixed.
 def TEST8mi  : Ii8 <0xF6, MRM0m,                     // flags = [mem8]  & imm8
                     (ops i8mem:$src1, i8imm:$src2),
                     "test{b} {$src2, $src1|$src1, $src2}",
-                    [(X86test (loadi8 addr:$src1), imm:$src2)]>;
+                    [/*(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0)*/]>;
 def TEST16mi : Ii16<0xF7, MRM0m,                     // flags = [mem16] & imm16
                     (ops i16mem:$src1, i16imm:$src2),
                     "test{w} {$src2, $src1|$src1, $src2}",
-                    [(X86test (loadi16 addr:$src1), imm:$src2)]>,
+                    [/*(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0)*/]>,
                OpSize;
 def TEST32mi : Ii32<0xF7, MRM0m,                     // flags = [mem32] & imm32
                     (ops i32mem:$src1, i32imm:$src2),
                     "test{l} {$src2, $src1|$src1, $src2}",
-                    [(X86test (loadi32 addr:$src1), imm:$src2)]>;
+                    [/*(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0)*/]>;
 
 
 // Condition code ops, incl. set if equal/not equal/...
@@ -2523,6 +2515,16 @@
 def : Pat<(truncstore GR8:$src, addr:$dst, i1), 
           (MOV8mr addr:$dst, GR8:$src)>;
 
+// Comparisons.
+
+// TEST R,R is smaller than CMP R,0
+def : Pat<(X86cmp GR8:$src1, 0),
+          (TEST8rr GR8:$src1, GR8:$src1)>;
+def : Pat<(X86cmp GR16:$src1, 0),
+          (TEST16rr GR16:$src1, GR16:$src1)>;
+def : Pat<(X86cmp GR32:$src1, 0),
+          (TEST32rr GR32:$src1, GR32:$src1)>;
+
 // {s|z}extload bool -> {s|z}extload byte
 def : Pat<(sextloadi16i1 addr:$src), (MOVSX16rm8 addr:$src)>;
 def : Pat<(sextloadi32i1 addr:$src), (MOVSX32rm8 addr:$src)>;





From lattner at cs.uiuc.edu  Thu Sep  7 16:29:46 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 7 Sep 2006 16:29:46 -0500
Subject: [llvm-commits] CVS:
	llvm/test/Regression/Transforms/TailDup/if-tail-dup.ll
Message-ID: <200609072129.k87LTkxq011624@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/Transforms/TailDup:

if-tail-dup.ll added (r1.1)
---
Log message:

new testcase


---
Diffs of the changes:  (+57 -0)

 if-tail-dup.ll |   57 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 57 insertions(+)


Index: llvm/test/Regression/Transforms/TailDup/if-tail-dup.ll
diff -c /dev/null llvm/test/Regression/Transforms/TailDup/if-tail-dup.ll:1.1
*** /dev/null	Thu Sep  7 16:29:42 2006
--- llvm/test/Regression/Transforms/TailDup/if-tail-dup.ll	Thu Sep  7 16:29:32 2006
***************
*** 0 ****
--- 1,57 ----
+ ; RUN: llvm-as < %s | opt -tailduplicate | llc -march=x86 | grep 'je ' &&
+ ; RUN: llvm-as < %s | opt -tailduplicate | llc -march=x86 | not grep jmp
+ ; This should have no unconditional jumps in it.  The C source is:
+ 
+ ;void foo(int c, int* P) {
+ ;  if (c & 1)  P[0] = 1;
+ ;  if (c & 2)  P[1] = 1;
+ ;  if (c & 4)  P[2] = 1;
+ ;  if (c & 8)  P[3] = 1;
+ ;}
+ 
+ 
+ void %foo(int %c, int* %P) {
+ entry:
+         %tmp1 = and int %c, 1           ; <int> [#uses=1]
+         %tmp1 = seteq int %tmp1, 0              ; <bool> [#uses=1]
+         br bool %tmp1, label %cond_next, label %cond_true
+ 
+ cond_true:              ; preds = %entry
+         store int 1, int* %P
+         br label %cond_next
+ 
+ cond_next:              ; preds = %entry, %cond_true
+         %tmp5 = and int %c, 2           ; <int> [#uses=1]
+         %tmp5 = seteq int %tmp5, 0              ; <bool> [#uses=1]
+         br bool %tmp5, label %cond_next10, label %cond_true6
+ 
+ cond_true6:             ; preds = %cond_next
+         %tmp8 = getelementptr int* %P, int 1            ; <int*> [#uses=1]
+         store int 1, int* %tmp8
+         br label %cond_next10
+ 
+ cond_next10:            ; preds = %cond_next, %cond_true6
+         %tmp13 = and int %c, 4          ; <int> [#uses=1]
+         %tmp13 = seteq int %tmp13, 0            ; <bool> [#uses=1]
+         br bool %tmp13, label %cond_next18, label %cond_true14
+ 
+ cond_true14:            ; preds = %cond_next10
+         %tmp16 = getelementptr int* %P, int 2           ; <int*> [#uses=1]
+         store int 1, int* %tmp16
+         br label %cond_next18
+ 
+ cond_next18:            ; preds = %cond_next10, %cond_true14
+         %tmp21 = and int %c, 8          ; <int> [#uses=1]
+         %tmp21 = seteq int %tmp21, 0            ; <bool> [#uses=1]
+         br bool %tmp21, label %return, label %cond_true22
+ 
+ cond_true22:            ; preds = %cond_next18
+         %tmp24 = getelementptr int* %P, int 3           ; <int*> [#uses=1]
+         store int 1, int* %tmp24
+         ret void
+ 
+ return:         ; preds = %cond_next18
+         ret void
+ }
+ 
+ 





From lattner at cs.uiuc.edu  Thu Sep  7 16:30:29 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 7 Sep 2006 16:30:29 -0500
Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/TailDuplication.cpp
Message-ID: <200609072130.k87LUT3x011651@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/Scalar:

TailDuplication.cpp updated: 1.30 -> 1.31
---
Log message:

Throttle back tail duplication to avoid creating really ugly sequences of code.
For Transforms/TailDup/if-tail-dup.ll, f.e., it produces:

_foo:
        movl 8(%esp), %eax
        movl 4(%esp), %ecx
        testl $1, %ecx
        je LBB1_2       #cond_next
LBB1_1: #cond_true
        movl $1, (%eax)
LBB1_2: #cond_next
        testl $2, %ecx
        je LBB1_4       #cond_next10
LBB1_3: #cond_true6
        movl $1, 4(%eax)
LBB1_4: #cond_next10
        testl $4, %ecx
        je LBB1_6       #cond_next18
LBB1_5: #cond_true14
        movl $1, 8(%eax)
LBB1_6: #cond_next18
        testl $8, %ecx
        je LBB1_8       #return
LBB1_7: #cond_true22
        movl $1, 12(%eax)
        ret
LBB1_8: #return
        ret

instead of:

_foo:
        movl 4(%esp), %eax
        testl $2, %eax
        sete %cl
        movl 8(%esp), %edx
        testl $1, %eax
        je LBB1_2       #cond_next
LBB1_1: #cond_true
        movl $1, (%edx)
        testb %cl, %cl
        jne LBB1_4      #cond_next10
        jmp LBB1_3      #cond_true6
LBB1_2: #cond_next
        testb %cl, %cl
        jne LBB1_4      #cond_next10
LBB1_3: #cond_true6
        movl $1, 4(%edx)
        testl $4, %eax
        je LBB1_6       #cond_next18
        jmp LBB1_5      #cond_true14
LBB1_4: #cond_next10
        testl $4, %eax
        je LBB1_6       #cond_next18
LBB1_5: #cond_true14
        movl $1, 8(%edx)
        testl $8, %eax
        je LBB1_8       #return
        jmp LBB1_7      #cond_true22
LBB1_6: #cond_next18
        testl $8, %eax
        je LBB1_8       #return
LBB1_7: #cond_true22
        movl $1, 12(%edx)
        ret
LBB1_8: #return
        ret



---
Diffs of the changes:  (+19 -0)

 TailDuplication.cpp |   19 +++++++++++++++++++
 1 files changed, 19 insertions(+)


Index: llvm/lib/Transforms/Scalar/TailDuplication.cpp
diff -u llvm/lib/Transforms/Scalar/TailDuplication.cpp:1.30 llvm/lib/Transforms/Scalar/TailDuplication.cpp:1.31
--- llvm/lib/Transforms/Scalar/TailDuplication.cpp:1.30	Sun Aug 27 17:42:52 2006
+++ llvm/lib/Transforms/Scalar/TailDuplication.cpp	Thu Sep  7 16:30:15 2006
@@ -127,6 +127,25 @@
     for (; PI != PE; ++PI)
       if (TooMany-- == 0) return false;
   }
+  
+  // Finally, if this unconditional branch is a fall-through, be careful about
+  // tail duplicating it.  In particular, we don't want to taildup it if the
+  // original block will still be there after taildup is completed: doing so
+  // would eliminate the fall-through, requiring unconditional branches.
+  Function::iterator DestI = Dest;
+  if (&*--DestI == BI->getParent()) {
+    // The uncond branch is a fall-through.  Tail duplication of the block is
+    // will eliminate the fall-through-ness and end up cloning the terminator
+    // at the end of the Dest block.  Since the original Dest block will
+    // continue to exist, this means that one or the other will not be able to
+    // fall through.  One typical example that this helps with is code like:
+    // if (a)
+    //   foo();
+    // if (b)
+    //   foo();
+    // Cloning the 'if b' block into the end of the first foo block is messy.
+    return false;
+  }
 
   return true;
 }





From dpatel at apple.com  Thu Sep  7 16:37:09 2006
From: dpatel at apple.com (Devang Patel)
Date: Thu, 7 Sep 2006 16:37:09 -0500
Subject: [llvm-commits] CVS: llvm/tools/lto/Makefile
Message-ID: <200609072137.k87Lb93c011761@zion.cs.uiuc.edu>



Changes in directory llvm/tools/lto:

Makefile updated: 1.5 -> 1.6
---
Log message:

Add linker into list of LINK_COMPONENTS.


---
Diffs of the changes:  (+1 -1)

 Makefile |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/tools/lto/Makefile
diff -u llvm/tools/lto/Makefile:1.5 llvm/tools/lto/Makefile:1.6
--- llvm/tools/lto/Makefile:1.5	Mon Sep  4 00:59:09 2006
+++ llvm/tools/lto/Makefile	Thu Sep  7 16:36:55 2006
@@ -20,7 +20,7 @@
 # early so we can set up LINK_COMPONENTS before includeing Makefile.rules
 include $(LEVEL)/Makefile.config
 
-LINK_COMPONENTS := $(TARGETS_TO_BUILD) ipo scalaropts bcreader bcwriter
+LINK_COMPONENTS := $(TARGETS_TO_BUILD) ipo scalaropts linker bcreader bcwriter
 
 include $(LEVEL)/Makefile.common
 





From dpatel at apple.com  Thu Sep  7 16:41:25 2006
From: dpatel at apple.com (Devang Patel)
Date: Thu, 7 Sep 2006 16:41:25 -0500
Subject: [llvm-commits] CVS: llvm/tools/lto/lto.cpp
Message-ID: <200609072141.k87LfPdt011854@zion.cs.uiuc.edu>



Changes in directory llvm/tools/lto:

lto.cpp updated: 1.13 -> 1.14
---
Log message:

Using addPassesToEmitWholeFile is not a good idea here.
Use FunctionPassManager to do the job.


---
Diffs of the changes:  (+14 -1)

 lto.cpp |   15 ++++++++++++++-
 1 files changed, 14 insertions(+), 1 deletion(-)


Index: llvm/tools/lto/lto.cpp
diff -u llvm/tools/lto/lto.cpp:1.13 llvm/tools/lto/lto.cpp:1.14
--- llvm/tools/lto/lto.cpp:1.13	Thu Sep  7 15:20:56 2006
+++ llvm/tools/lto/lto.cpp	Thu Sep  7 16:41:11 2006
@@ -282,11 +282,24 @@
   // Make sure everything is still good.
   Passes.add(createVerifierPass());
 
-  Target.addPassesToEmitWholeFile(Passes, Out, TargetMachine::AssemblyFile, true);
+  FunctionPassManager *CodeGenPasses =
+    new FunctionPassManager(new ExistingModuleProvider(M));
+
+  CodeGenPasses->add(new TargetData(*Target.getTargetData()));
+  Target.addPassesToEmitFile(*CodeGenPasses, Out, TargetMachine::AssemblyFile, 
+			     true);
 
   // Run our queue of passes all at once now, efficiently.
   Passes.run(*M);
 
+  // Run the code generator, if present.
+  CodeGenPasses->doInitialization();
+  for (Module::iterator I = M->begin(), E = M->end(); I != E; ++I) {
+    if (!I->isExternal())
+      CodeGenPasses->run(*I);
+  }
+  CodeGenPasses->doFinalization();
+
   return LTO_OPT_SUCCESS;
 }
 





From jlaskey at apple.com  Thu Sep  7 17:05:20 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Thu, 7 Sep 2006 17:05:20 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86TargetAsmInfo.cpp
	X86TargetAsmInfo.h
Message-ID: <200609072205.k87M5K2T012241@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86TargetAsmInfo.cpp added (r1.1)
X86TargetAsmInfo.h added (r1.1)
---
Log message:

Break out target asm info into separate files.


---
Diffs of the changes:  (+126 -0)

 X86TargetAsmInfo.cpp |   95 +++++++++++++++++++++++++++++++++++++++++++++++++++
 X86TargetAsmInfo.h   |   31 ++++++++++++++++
 2 files changed, 126 insertions(+)


Index: llvm/lib/Target/X86/X86TargetAsmInfo.cpp
diff -c /dev/null llvm/lib/Target/X86/X86TargetAsmInfo.cpp:1.1
*** /dev/null	Thu Sep  7 17:05:12 2006
--- llvm/lib/Target/X86/X86TargetAsmInfo.cpp	Thu Sep  7 17:05:02 2006
***************
*** 0 ****
--- 1,95 ----
+ //===-- X86TargetAsmInfo.cpp - X86 asm properties ---------------*- C++ -*-===//
+ //
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by James M. Laskey and is distributed under the
+ // University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file contains the declarations of the X86TargetAsmInfo properties.
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ #include "X86TargetAsmInfo.h"
+ #include "X86TargetMachine.h"
+ #include "X86Subtarget.h"
+ 
+ using namespace llvm;
+ 
+ X86TargetAsmInfo::X86TargetAsmInfo(const X86TargetMachine &TM) {
+   const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
+   
+   //FIXME - Should to be simplified.
+    
+   switch (Subtarget->TargetType) {
+   case X86Subtarget::isDarwin:
+     AlignmentIsInBytes = false;
+     GlobalPrefix = "_";
+     Data64bitsDirective = 0;       // we can't emit a 64-bit unit
+     ZeroDirective = "\t.space\t";  // ".space N" emits N zeros.
+     PrivateGlobalPrefix = "L";     // Marker for constant pool idxs
+     ConstantPoolSection = "\t.const\n";
+     JumpTableDataSection = "\t.const\n"; // FIXME: depends on PIC mode
+     FourByteConstantSection = "\t.literal4\n";
+     EightByteConstantSection = "\t.literal8\n";
+     LCOMMDirective = "\t.lcomm\t";
+     COMMDirectiveTakesAlignment = false;
+     HasDotTypeDotSizeDirective = false;
+     StaticCtorsSection = ".mod_init_func";
+     StaticDtorsSection = ".mod_term_func";
+     InlineAsmStart = "# InlineAsm Start";
+     InlineAsmEnd = "# InlineAsm End";
+     SetDirective = "\t.set";
+     
+     NeedsSet = true;
+     DwarfAbbrevSection = ".section __DWARF,__debug_abbrev,regular,debug";
+     DwarfInfoSection = ".section __DWARF,__debug_info,regular,debug";
+     DwarfLineSection = ".section __DWARF,__debug_line,regular,debug";
+     DwarfFrameSection = ".section __DWARF,__debug_frame,regular,debug";
+     DwarfPubNamesSection = ".section __DWARF,__debug_pubnames,regular,debug";
+     DwarfPubTypesSection = ".section __DWARF,__debug_pubtypes,regular,debug";
+     DwarfStrSection = ".section __DWARF,__debug_str,regular,debug";
+     DwarfLocSection = ".section __DWARF,__debug_loc,regular,debug";
+     DwarfARangesSection = ".section __DWARF,__debug_aranges,regular,debug";
+     DwarfRangesSection = ".section __DWARF,__debug_ranges,regular,debug";
+     DwarfMacInfoSection = ".section __DWARF,__debug_macinfo,regular,debug";
+     break;
+   case X86Subtarget::isCygwin:
+     GlobalPrefix = "_";
+     COMMDirectiveTakesAlignment = false;
+     HasDotTypeDotSizeDirective = false;
+     StaticCtorsSection = "\t.section .ctors,\"aw\"";
+     StaticDtorsSection = "\t.section .dtors,\"aw\"";
+     break;
+   case X86Subtarget::isWindows:
+     GlobalPrefix = "_";
+     HasDotTypeDotSizeDirective = false;
+     break;
+   default: break;
+   }
+   
+   if (Subtarget->isFlavorIntel()) {
+     GlobalPrefix = "_";
+     CommentString = ";";
+   
+     PrivateGlobalPrefix = "$";
+     AlignDirective = "\talign\t";
+     ZeroDirective = "\tdb\t";
+     ZeroDirectiveSuffix = " dup(0)";
+     AsciiDirective = "\tdb\t";
+     AscizDirective = 0;
+     Data8bitsDirective = "\tdb\t";
+     Data16bitsDirective = "\tdw\t";
+     Data32bitsDirective = "\tdd\t";
+     Data64bitsDirective = "\tdq\t";
+     HasDotTypeDotSizeDirective = false;
+     
+     TextSection = "_text";
+     DataSection = "_data";
+     SwitchToSectionDirective = "";
+     TextSectionStartSuffix = "\tsegment 'CODE'";
+     DataSectionStartSuffix = "\tsegment 'DATA'";
+     SectionEndDirectiveSuffix = "\tends\n";
+   }
+ }


Index: llvm/lib/Target/X86/X86TargetAsmInfo.h
diff -c /dev/null llvm/lib/Target/X86/X86TargetAsmInfo.h:1.1
*** /dev/null	Thu Sep  7 17:05:20 2006
--- llvm/lib/Target/X86/X86TargetAsmInfo.h	Thu Sep  7 17:05:02 2006
***************
*** 0 ****
--- 1,31 ----
+ //=====-- X86TargetAsmInfo.h - X86 asm properties -------------*- C++ -*--====//
+ //
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by James M. Laskey and is distributed under the
+ // University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file contains the declaration of the X86TargetAsmInfo class.
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ #ifndef X86TARGETASMINFO_H
+ #define X86TARGETASMINFO_H
+ 
+ #include "llvm/Target/TargetAsmInfo.h"
+ 
+ namespace llvm {
+   
+   // Forward declaration.
+   class X86TargetMachine;
+ 
+   struct X86TargetAsmInfo : public TargetAsmInfo {
+     X86TargetAsmInfo(const X86TargetMachine &TM);
+   };
+ 
+ 
+ } // namespace llvm
+ 
+ #endif





From jlaskey at apple.com  Thu Sep  7 17:05:23 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Thu, 7 Sep 2006 17:05:23 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/ARM/ARMTargetAsmInfo.cpp
	ARMTargetAsmInfo.h
Message-ID: <200609072205.k87M5NUp012263@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/ARM:

ARMTargetAsmInfo.cpp added (r1.1)
ARMTargetAsmInfo.h added (r1.1)
---
Log message:

Break out target asm info into separate files.


---
Diffs of the changes:  (+57 -0)

 ARMTargetAsmInfo.cpp |   26 ++++++++++++++++++++++++++
 ARMTargetAsmInfo.h   |   31 +++++++++++++++++++++++++++++++
 2 files changed, 57 insertions(+)


Index: llvm/lib/Target/ARM/ARMTargetAsmInfo.cpp
diff -c /dev/null llvm/lib/Target/ARM/ARMTargetAsmInfo.cpp:1.1
*** /dev/null	Thu Sep  7 17:05:12 2006
--- llvm/lib/Target/ARM/ARMTargetAsmInfo.cpp	Thu Sep  7 17:05:01 2006
***************
*** 0 ****
--- 1,26 ----
+ //===-- ARMTargetAsmInfo.cpp - ARM asm properties ---------------*- C++ -*-===//
+ //
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by James M. Laskey and is distributed under the
+ // University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file contains the declarations of the ARMTargetAsmInfo properties.
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ #include "ARMTargetAsmInfo.h"
+ 
+ using namespace llvm;
+ 
+ ARMTargetAsmInfo::ARMTargetAsmInfo(const ARMTargetMachine &TM) {
+   Data16bitsDirective = "\t.half\t";
+   Data32bitsDirective = "\t.word\t";
+   Data64bitsDirective = 0;
+   ZeroDirective = "\t.skip\t";
+   CommentString = "@";
+   ConstantPoolSection = "\t.text\n";
+   AlignmentIsInBytes = false;
+ }


Index: llvm/lib/Target/ARM/ARMTargetAsmInfo.h
diff -c /dev/null llvm/lib/Target/ARM/ARMTargetAsmInfo.h:1.1
*** /dev/null	Thu Sep  7 17:05:23 2006
--- llvm/lib/Target/ARM/ARMTargetAsmInfo.h	Thu Sep  7 17:05:01 2006
***************
*** 0 ****
--- 1,31 ----
+ //=====-- ARMTargetAsmInfo.h - ARM asm properties -------------*- C++ -*--====//
+ //
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by James M. Laskey and is distributed under the
+ // University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file contains the declaration of the ARMTargetAsmInfo class.
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ #ifndef ARMTARGETASMINFO_H
+ #define ARMTARGETASMINFO_H
+ 
+ #include "llvm/Target/TargetAsmInfo.h"
+ 
+ namespace llvm {
+ 
+   // Forward declaration.
+   class ARMTargetMachine;
+ 
+   struct ARMTargetAsmInfo : public TargetAsmInfo {
+     ARMTargetAsmInfo(const ARMTargetMachine &TM);
+   };
+ 
+ 
+ } // namespace llvm
+ 
+ #endif





From jlaskey at apple.com  Thu Sep  7 17:05:23 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Thu, 7 Sep 2006 17:05:23 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/IA64/IA64TargetAsmInfo.cpp
	IA64TargetAsmInfo.h
Message-ID: <200609072205.k87M5Npq012249@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/IA64:

IA64TargetAsmInfo.cpp added (r1.1)
IA64TargetAsmInfo.h added (r1.1)
---
Log message:

Break out target asm info into separate files.


---
Diffs of the changes:  (+65 -0)

 IA64TargetAsmInfo.cpp |   34 ++++++++++++++++++++++++++++++++++
 IA64TargetAsmInfo.h   |   31 +++++++++++++++++++++++++++++++
 2 files changed, 65 insertions(+)


Index: llvm/lib/Target/IA64/IA64TargetAsmInfo.cpp
diff -c /dev/null llvm/lib/Target/IA64/IA64TargetAsmInfo.cpp:1.1
*** /dev/null	Thu Sep  7 17:05:12 2006
--- llvm/lib/Target/IA64/IA64TargetAsmInfo.cpp	Thu Sep  7 17:05:02 2006
***************
*** 0 ****
--- 1,34 ----
+ //===-- IA64TargetAsmInfo.cpp - IA64 asm properties -------------*- C++ -*-===//
+ //
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by James M. Laskey and is distributed under the
+ // University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file contains the declarations of the IA64TargetAsmInfo properties.
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ #include "IA64TargetAsmInfo.h"
+ 
+ using namespace llvm;
+ 
+ IA64TargetAsmInfo::IA64TargetAsmInfo(const IA64TargetMachine &TM) {
+   CommentString = "//";
+   Data8bitsDirective = "\tdata1\t";     // FIXME: check that we are
+   Data16bitsDirective = "\tdata2.ua\t"; // disabling auto-alignment
+   Data32bitsDirective = "\tdata4.ua\t"; // properly
+   Data64bitsDirective = "\tdata8.ua\t";
+   ZeroDirective = "\t.skip\t";
+   AsciiDirective = "\tstring\t";
+ 
+   GlobalVarAddrPrefix="";
+   GlobalVarAddrSuffix="";
+   FunctionAddrPrefix="@fptr(";
+   FunctionAddrSuffix=")";
+   
+   // FIXME: would be nice to have rodata (no 'w') when appropriate?
+   ConstantPoolSection = "\n\t.section .data, \"aw\", \"progbits\"\n";
+ }


Index: llvm/lib/Target/IA64/IA64TargetAsmInfo.h
diff -c /dev/null llvm/lib/Target/IA64/IA64TargetAsmInfo.h:1.1
*** /dev/null	Thu Sep  7 17:05:23 2006
--- llvm/lib/Target/IA64/IA64TargetAsmInfo.h	Thu Sep  7 17:05:02 2006
***************
*** 0 ****
--- 1,31 ----
+ //=====-- IA64TargetAsmInfo.h - IA64 asm properties -----------*- C++ -*--====//
+ //
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by James M. Laskey and is distributed under the
+ // University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file contains the declaration of the IA64TargetAsmInfo class.
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ #ifndef IA64TARGETASMINFO_H
+ #define IA64TARGETASMINFO_H
+ 
+ #include "llvm/Target/TargetAsmInfo.h"
+ 
+ namespace llvm {
+ 
+   // Forward declaration.
+   class IA64TargetMachine;
+ 
+   struct IA64TargetAsmInfo : public TargetAsmInfo {
+     IA64TargetAsmInfo(const IA64TargetMachine &TM);
+   };
+ 
+ 
+ } // namespace llvm
+ 
+ #endif





From jlaskey at apple.com  Thu Sep  7 17:05:23 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Thu, 7 Sep 2006 17:05:23 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaTargetAsmInfo.cpp
	AlphaTargetAsmInfo.h
Message-ID: <200609072205.k87M5NIf012254@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaTargetAsmInfo.cpp added (r1.1)
AlphaTargetAsmInfo.h added (r1.1)
---
Log message:

Break out target asm info into separate files.


---
Diffs of the changes:  (+51 -0)

 AlphaTargetAsmInfo.cpp |   21 +++++++++++++++++++++
 AlphaTargetAsmInfo.h   |   30 ++++++++++++++++++++++++++++++
 2 files changed, 51 insertions(+)


Index: llvm/lib/Target/Alpha/AlphaTargetAsmInfo.cpp
diff -c /dev/null llvm/lib/Target/Alpha/AlphaTargetAsmInfo.cpp:1.1
*** /dev/null	Thu Sep  7 17:05:12 2006
--- llvm/lib/Target/Alpha/AlphaTargetAsmInfo.cpp	Thu Sep  7 17:05:02 2006
***************
*** 0 ****
--- 1,21 ----
+ //===-- AlphaTargetAsmInfo.cpp - Alpha asm properties -----------*- C++ -*-===//
+ //
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by James M. Laskey and is distributed under the
+ // University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file contains the declarations of the AlphaTargetAsmInfo properties.
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ #include "AlphaTargetAsmInfo.h"
+ 
+ using namespace llvm;
+ 
+ AlphaTargetAsmInfo::AlphaTargetAsmInfo(const AlphaTargetMachine &TM) {
+   AlignmentIsInBytes = false;
+   PrivateGlobalPrefix = "$";
+ }


Index: llvm/lib/Target/Alpha/AlphaTargetAsmInfo.h
diff -c /dev/null llvm/lib/Target/Alpha/AlphaTargetAsmInfo.h:1.1
*** /dev/null	Thu Sep  7 17:05:23 2006
--- llvm/lib/Target/Alpha/AlphaTargetAsmInfo.h	Thu Sep  7 17:05:02 2006
***************
*** 0 ****
--- 1,30 ----
+ //=====-- AlphaTargetAsmInfo.h - Alpha asm properties ---------*- C++ -*--====//
+ //
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by James M. Laskey and is distributed under the
+ // University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file contains the declaration of the AlphaTargetAsmInfo class.
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ #ifndef ALPHATARGETASMINFO_H
+ #define ALPHATARGETASMINFO_H
+ 
+ #include "llvm/Target/TargetAsmInfo.h"
+ 
+ namespace llvm {
+ 
+   // Forward declaration.
+   class AlphaTargetMachine;
+ 
+   struct AlphaTargetAsmInfo : public TargetAsmInfo {
+     AlphaTargetAsmInfo(const AlphaTargetMachine &TM);
+   };
+ 
+ } // namespace llvm
+ 
+ #endif





From jlaskey at apple.com  Thu Sep  7 17:05:24 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Thu, 7 Sep 2006 17:05:24 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcTargetAsmInfo.cpp
	SparcTargetAsmInfo.h
Message-ID: <200609072205.k87M5O2f012277@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Sparc:

SparcTargetAsmInfo.cpp added (r1.1)
SparcTargetAsmInfo.h added (r1.1)
---
Log message:

Break out target asm info into separate files.


---
Diffs of the changes:  (+56 -0)

 SparcTargetAsmInfo.cpp |   25 +++++++++++++++++++++++++
 SparcTargetAsmInfo.h   |   31 +++++++++++++++++++++++++++++++
 2 files changed, 56 insertions(+)


Index: llvm/lib/Target/Sparc/SparcTargetAsmInfo.cpp
diff -c /dev/null llvm/lib/Target/Sparc/SparcTargetAsmInfo.cpp:1.1
*** /dev/null	Thu Sep  7 17:05:12 2006
--- llvm/lib/Target/Sparc/SparcTargetAsmInfo.cpp	Thu Sep  7 17:05:02 2006
***************
*** 0 ****
--- 1,25 ----
+ //===-- SparcTargetAsmInfo.cpp - Sparc asm properties -----------*- C++ -*-===//
+ //
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by James M. Laskey and is distributed under the
+ // University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file contains the declarations of the SparcTargetAsmInfo properties.
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ #include "SparcTargetAsmInfo.h"
+ 
+ using namespace llvm;
+ 
+ SparcTargetAsmInfo::SparcTargetAsmInfo(const SparcTargetMachine &TM) {
+   Data16bitsDirective = "\t.half\t";
+   Data32bitsDirective = "\t.word\t";
+   Data64bitsDirective = 0;  // .xword is only supported by V9.
+   ZeroDirective = "\t.skip\t";
+   CommentString = "!";
+   ConstantPoolSection = "\t.section \".rodata\",#alloc\n";
+ }


Index: llvm/lib/Target/Sparc/SparcTargetAsmInfo.h
diff -c /dev/null llvm/lib/Target/Sparc/SparcTargetAsmInfo.h:1.1
*** /dev/null	Thu Sep  7 17:05:24 2006
--- llvm/lib/Target/Sparc/SparcTargetAsmInfo.h	Thu Sep  7 17:05:02 2006
***************
*** 0 ****
--- 1,31 ----
+ //=====-- SparcTargetAsmInfo.h - Sparc asm properties ---------*- C++ -*--====//
+ //
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by James M. Laskey and is distributed under the
+ // University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file contains the declaration of the SparcTargetAsmInfo class.
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ #ifndef SPARCTARGETASMINFO_H
+ #define SPARCTARGETASMINFO_H
+ 
+ #include "llvm/Target/TargetAsmInfo.h"
+ 
+ namespace llvm {
+ 
+   // Forward declaration.
+   class SparcTargetMachine;
+ 
+   struct SparcTargetAsmInfo : public TargetAsmInfo {
+     SparcTargetAsmInfo(const SparcTargetMachine &TM);
+   };
+ 
+ 
+ } // namespace llvm
+ 
+ #endif





From jlaskey at apple.com  Thu Sep  7 17:05:24 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Thu, 7 Sep 2006 17:05:24 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCTargetAsmInfo.cpp
	PPCTargetAsmInfo.h
Message-ID: <200609072205.k87M5OTu012270@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCTargetAsmInfo.cpp added (r1.1)
PPCTargetAsmInfo.h added (r1.1)
---
Log message:

Break out target asm info into separate files.


---
Diffs of the changes:  (+82 -0)

 PPCTargetAsmInfo.cpp |   51 +++++++++++++++++++++++++++++++++++++++++++++++++++
 PPCTargetAsmInfo.h   |   31 +++++++++++++++++++++++++++++++
 2 files changed, 82 insertions(+)


Index: llvm/lib/Target/PowerPC/PPCTargetAsmInfo.cpp
diff -c /dev/null llvm/lib/Target/PowerPC/PPCTargetAsmInfo.cpp:1.1
*** /dev/null	Thu Sep  7 17:05:12 2006
--- llvm/lib/Target/PowerPC/PPCTargetAsmInfo.cpp	Thu Sep  7 17:05:02 2006
***************
*** 0 ****
--- 1,51 ----
+ //===-- PPCTargetAsmInfo.cpp - PPC asm properties ---------------*- C++ -*-===//
+ //
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by James M. Laskey and is distributed under the
+ // University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file contains the declarations of the DarwinTargetAsmInfo properties.
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ #include "PPCTargetAsmInfo.h"
+ #include "PPCTargetMachine.h"
+ 
+ using namespace llvm;
+ 
+ DarwinTargetAsmInfo::DarwinTargetAsmInfo(const PPCTargetMachine &TM) {
+   bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
+ 
+   CommentString = ";";
+   GlobalPrefix = "_";
+   PrivateGlobalPrefix = "L";
+   ZeroDirective = "\t.space\t";
+   SetDirective = "\t.set";
+   Data64bitsDirective = isPPC64 ? ".quad\t" : 0;  
+   AlignmentIsInBytes = false;
+   ConstantPoolSection = "\t.const\t";
+   JumpTableDataSection = ".const";
+   JumpTableTextSection = "\t.text";
+   LCOMMDirective = "\t.lcomm\t";
+   StaticCtorsSection = ".mod_init_func";
+   StaticDtorsSection = ".mod_term_func";
+   InlineAsmStart = "# InlineAsm Start";
+   InlineAsmEnd = "# InlineAsm End";
+   
+   NeedsSet = true;
+   AddressSize = isPPC64 ? 8 : 4;
+   DwarfAbbrevSection = ".section __DWARF,__debug_abbrev";
+   DwarfInfoSection = ".section __DWARF,__debug_info";
+   DwarfLineSection = ".section __DWARF,__debug_line";
+   DwarfFrameSection = ".section __DWARF,__debug_frame";
+   DwarfPubNamesSection = ".section __DWARF,__debug_pubnames";
+   DwarfPubTypesSection = ".section __DWARF,__debug_pubtypes";
+   DwarfStrSection = ".section __DWARF,__debug_str";
+   DwarfLocSection = ".section __DWARF,__debug_loc";
+   DwarfARangesSection = ".section __DWARF,__debug_aranges";
+   DwarfRangesSection = ".section __DWARF,__debug_ranges";
+   DwarfMacInfoSection = ".section __DWARF,__debug_macinfo";
+ }


Index: llvm/lib/Target/PowerPC/PPCTargetAsmInfo.h
diff -c /dev/null llvm/lib/Target/PowerPC/PPCTargetAsmInfo.h:1.1
*** /dev/null	Thu Sep  7 17:05:24 2006
--- llvm/lib/Target/PowerPC/PPCTargetAsmInfo.h	Thu Sep  7 17:05:02 2006
***************
*** 0 ****
--- 1,31 ----
+ //=====-- PPCTargetAsmInfo.h - PPC asm properties -------------*- C++ -*--====//
+ //
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by James M. Laskey and is distributed under the
+ // University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This file contains the declaration of the DarwinTargetAsmInfo class.
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ #ifndef PPCTARGETASMINFO_H
+ #define PPCTARGETASMINFO_H
+ 
+ #include "llvm/Target/TargetAsmInfo.h"
+ 
+ namespace llvm {
+ 
+   // Forward declaration.
+   class PPCTargetMachine;
+ 
+   struct DarwinTargetAsmInfo : public TargetAsmInfo {
+     DarwinTargetAsmInfo(const PPCTargetMachine &TM);
+   };
+ 
+ 
+ } // namespace llvm
+ 
+ #endif





From jlaskey at apple.com  Thu Sep  7 17:07:04 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Thu, 7 Sep 2006 17:07:04 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcAsmPrinter.cpp
	SparcTargetMachine.h
Message-ID: <200609072207.k87M74FE012365@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Sparc:

SparcAsmPrinter.cpp updated: 1.67 -> 1.68
SparcTargetMachine.h updated: 1.15 -> 1.16
---
Log message:

Make target asm info a property of the target machine.


---
Diffs of the changes:  (+6 -14)

 SparcAsmPrinter.cpp  |   16 ++--------------
 SparcTargetMachine.h |    4 ++++
 2 files changed, 6 insertions(+), 14 deletions(-)


Index: llvm/lib/Target/Sparc/SparcAsmPrinter.cpp
diff -u llvm/lib/Target/Sparc/SparcAsmPrinter.cpp:1.67 llvm/lib/Target/Sparc/SparcAsmPrinter.cpp:1.68
--- llvm/lib/Target/Sparc/SparcAsmPrinter.cpp:1.67	Wed Sep  6 13:34:40 2006
+++ llvm/lib/Target/Sparc/SparcAsmPrinter.cpp	Thu Sep  7 17:06:40 2006
@@ -37,19 +37,8 @@
 namespace {
   Statistic<> EmittedInsts("asm-printer", "Number of machine instrs printed");
 
-  struct VISIBILITY_HIDDEN SparcTargetAsmInfo : public TargetAsmInfo {
-    SparcTargetAsmInfo() {
-      Data16bitsDirective = "\t.half\t";
-      Data32bitsDirective = "\t.word\t";
-      Data64bitsDirective = 0;  // .xword is only supported by V9.
-      ZeroDirective = "\t.skip\t";
-      CommentString = "!";
-      ConstantPoolSection = "\t.section \".rodata\",#alloc\n";
-    }
-  };
-
   struct VISIBILITY_HIDDEN SparcAsmPrinter : public AsmPrinter {
-    SparcAsmPrinter(std::ostream &O, TargetMachine &TM, TargetAsmInfo *T)
+    SparcAsmPrinter(std::ostream &O, TargetMachine &TM, const TargetAsmInfo *T)
       : AsmPrinter(O, TM, T) {
     }
 
@@ -85,8 +74,7 @@
 ///
 FunctionPass *llvm::createSparcCodePrinterPass(std::ostream &o,
                                                TargetMachine &tm) {
-  SparcTargetAsmInfo *TAI = new SparcTargetAsmInfo();
-  return new SparcAsmPrinter(o, tm, TAI);
+  return new SparcAsmPrinter(o, tm, tm.getTargetAsmInfo());
 }
 
 /// runOnMachineFunction - This uses the printMachineInstruction()


Index: llvm/lib/Target/Sparc/SparcTargetMachine.h
diff -u llvm/lib/Target/Sparc/SparcTargetMachine.h:1.15 llvm/lib/Target/Sparc/SparcTargetMachine.h:1.16
--- llvm/lib/Target/Sparc/SparcTargetMachine.h:1.15	Sun Sep  3 23:14:57 2006
+++ llvm/lib/Target/Sparc/SparcTargetMachine.h	Thu Sep  7 17:06:40 2006
@@ -19,6 +19,7 @@
 #include "llvm/Target/TargetFrameInfo.h"
 #include "SparcInstrInfo.h"
 #include "SparcSubtarget.h"
+#include "SparcTargetAsmInfo.h"
 
 namespace llvm {
 
@@ -41,6 +42,9 @@
   virtual const TargetData       *getTargetData() const { return &DataLayout; }
   static unsigned getModuleMatchQuality(const Module &M);
 
+  virtual const TargetAsmInfo *createTargetAsmInfo() const {
+    return static_cast<const TargetAsmInfo *>(new SparcTargetAsmInfo(*this));
+  }
   
   // Pass Pipeline Configuration
   virtual bool addInstSelector(FunctionPassManager &PM, bool Fast);





From jlaskey at apple.com  Thu Sep  7 17:07:04 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Thu, 7 Sep 2006 17:07:04 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp
	X86ATTAsmPrinter.h X86AsmPrinter.cpp X86AsmPrinter.h
	X86IntelAsmPrinter.cpp X86IntelAsmPrinter.h X86TargetMachine.h
Message-ID: <200609072207.k87M740f012378@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86ATTAsmPrinter.cpp updated: 1.59 -> 1.60
X86ATTAsmPrinter.h updated: 1.14 -> 1.15
X86AsmPrinter.cpp updated: 1.194 -> 1.195
X86AsmPrinter.h updated: 1.28 -> 1.29
X86IntelAsmPrinter.cpp updated: 1.53 -> 1.54
X86IntelAsmPrinter.h updated: 1.22 -> 1.23
X86TargetMachine.h updated: 1.38 -> 1.39
---
Log message:

Make target asm info a property of the target machine.


---
Diffs of the changes:  (+15 -88)

 X86ATTAsmPrinter.cpp   |    2 +
 X86ATTAsmPrinter.h     |    2 -
 X86AsmPrinter.cpp      |   83 +------------------------------------------------
 X86AsmPrinter.h        |    7 ----
 X86IntelAsmPrinter.cpp |    2 +
 X86IntelAsmPrinter.h   |    3 +
 X86TargetMachine.h     |    4 ++
 7 files changed, 15 insertions(+), 88 deletions(-)


Index: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp
diff -u llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.59 llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.60
--- llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.59	Wed Sep  6 13:34:40 2006
+++ llvm/lib/Target/X86/X86ATTAsmPrinter.cpp	Thu Sep  7 17:06:40 2006
@@ -16,8 +16,10 @@
 #include "X86ATTAsmPrinter.h"
 #include "X86.h"
 #include "X86TargetMachine.h"
+#include "X86TargetAsmInfo.h"
 #include "llvm/Module.h"
 #include "llvm/Support/Mangler.h"
+#include "llvm/Target/TargetAsmInfo.h"
 #include "llvm/Target/TargetOptions.h"
 #include <iostream>
 using namespace llvm;


Index: llvm/lib/Target/X86/X86ATTAsmPrinter.h
diff -u llvm/lib/Target/X86/X86ATTAsmPrinter.h:1.14 llvm/lib/Target/X86/X86ATTAsmPrinter.h:1.15
--- llvm/lib/Target/X86/X86ATTAsmPrinter.h:1.14	Wed Sep  6 13:34:40 2006
+++ llvm/lib/Target/X86/X86ATTAsmPrinter.h	Thu Sep  7 17:06:40 2006
@@ -20,7 +20,7 @@
 namespace llvm {
 
 struct X86ATTAsmPrinter : public X86SharedAsmPrinter {
- X86ATTAsmPrinter(std::ostream &O, X86TargetMachine &TM, TargetAsmInfo *T)
+ X86ATTAsmPrinter(std::ostream &O, X86TargetMachine &TM, const TargetAsmInfo *T)
     : X86SharedAsmPrinter(O, TM, T) { }
 
   virtual const char *getPassName() const {


Index: llvm/lib/Target/X86/X86AsmPrinter.cpp
diff -u llvm/lib/Target/X86/X86AsmPrinter.cpp:1.194 llvm/lib/Target/X86/X86AsmPrinter.cpp:1.195
--- llvm/lib/Target/X86/X86AsmPrinter.cpp:1.194	Thu Sep  7 07:23:47 2006
+++ llvm/lib/Target/X86/X86AsmPrinter.cpp	Thu Sep  7 17:06:40 2006
@@ -23,88 +23,12 @@
 #include "llvm/Type.h"
 #include "llvm/Assembly/Writer.h"
 #include "llvm/Support/Mangler.h"
+#include "llvm/Target/TargetAsmInfo.h"
 using namespace llvm;
 
 Statistic<> llvm::EmittedInsts("asm-printer",
                                "Number of machine instrs printed");
 
-X86TargetAsmInfo::X86TargetAsmInfo(X86TargetMachine &TM) {
-  const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
-  
-  //FIXME - Should to be simplified.
-   
-  switch (Subtarget->TargetType) {
-  case X86Subtarget::isDarwin:
-    AlignmentIsInBytes = false;
-    GlobalPrefix = "_";
-    Data64bitsDirective = 0;       // we can't emit a 64-bit unit
-    ZeroDirective = "\t.space\t";  // ".space N" emits N zeros.
-    PrivateGlobalPrefix = "L";     // Marker for constant pool idxs
-    ConstantPoolSection = "\t.const\n";
-    JumpTableDataSection = "\t.const\n"; // FIXME: depends on PIC mode
-    FourByteConstantSection = "\t.literal4\n";
-    EightByteConstantSection = "\t.literal8\n";
-    LCOMMDirective = "\t.lcomm\t";
-    COMMDirectiveTakesAlignment = false;
-    HasDotTypeDotSizeDirective = false;
-    StaticCtorsSection = ".mod_init_func";
-    StaticDtorsSection = ".mod_term_func";
-    InlineAsmStart = "# InlineAsm Start";
-    InlineAsmEnd = "# InlineAsm End";
-    SetDirective = "\t.set";
-    
-    NeedsSet = true;
-    DwarfAbbrevSection = ".section __DWARF,__debug_abbrev,regular,debug";
-    DwarfInfoSection = ".section __DWARF,__debug_info,regular,debug";
-    DwarfLineSection = ".section __DWARF,__debug_line,regular,debug";
-    DwarfFrameSection = ".section __DWARF,__debug_frame,regular,debug";
-    DwarfPubNamesSection = ".section __DWARF,__debug_pubnames,regular,debug";
-    DwarfPubTypesSection = ".section __DWARF,__debug_pubtypes,regular,debug";
-    DwarfStrSection = ".section __DWARF,__debug_str,regular,debug";
-    DwarfLocSection = ".section __DWARF,__debug_loc,regular,debug";
-    DwarfARangesSection = ".section __DWARF,__debug_aranges,regular,debug";
-    DwarfRangesSection = ".section __DWARF,__debug_ranges,regular,debug";
-    DwarfMacInfoSection = ".section __DWARF,__debug_macinfo,regular,debug";
-    break;
-  case X86Subtarget::isCygwin:
-    GlobalPrefix = "_";
-    COMMDirectiveTakesAlignment = false;
-    HasDotTypeDotSizeDirective = false;
-    StaticCtorsSection = "\t.section .ctors,\"aw\"";
-    StaticDtorsSection = "\t.section .dtors,\"aw\"";
-    break;
-  case X86Subtarget::isWindows:
-    GlobalPrefix = "_";
-    HasDotTypeDotSizeDirective = false;
-    break;
-  default: break;
-  }
-  
-  if (Subtarget->isFlavorIntel()) {
-    GlobalPrefix = "_";
-    CommentString = ";";
-  
-    PrivateGlobalPrefix = "$";
-    AlignDirective = "\talign\t";
-    ZeroDirective = "\tdb\t";
-    ZeroDirectiveSuffix = " dup(0)";
-    AsciiDirective = "\tdb\t";
-    AscizDirective = 0;
-    Data8bitsDirective = "\tdb\t";
-    Data16bitsDirective = "\tdw\t";
-    Data32bitsDirective = "\tdd\t";
-    Data64bitsDirective = "\tdq\t";
-    HasDotTypeDotSizeDirective = false;
-    
-    TextSection = "_text";
-    DataSection = "_data";
-    SwitchToSectionDirective = "";
-    TextSectionStartSuffix = "\tsegment 'CODE'";
-    DataSectionStartSuffix = "\tsegment 'DATA'";
-    SectionEndDirectiveSuffix = "\tends\n";
-  }
-}
-
 /// doInitialization
 bool X86SharedAsmPrinter::doInitialization(Module &M) {  
   if (Subtarget->isTargetDarwin()) {
@@ -255,11 +179,10 @@
 FunctionPass *llvm::createX86CodePrinterPass(std::ostream &o,
                                              X86TargetMachine &tm) {
   const X86Subtarget *Subtarget = &tm.getSubtarget<X86Subtarget>();
-  TargetAsmInfo *TAI = new X86TargetAsmInfo(tm);
 
   if (Subtarget->isFlavorIntel()) {
-    return new X86IntelAsmPrinter(o, tm, TAI);
+    return new X86IntelAsmPrinter(o, tm, tm.getTargetAsmInfo());
   } else {
-    return new X86ATTAsmPrinter(o, tm, TAI);
+    return new X86ATTAsmPrinter(o, tm, tm.getTargetAsmInfo());
   }
 }


Index: llvm/lib/Target/X86/X86AsmPrinter.h
diff -u llvm/lib/Target/X86/X86AsmPrinter.h:1.28 llvm/lib/Target/X86/X86AsmPrinter.h:1.29
--- llvm/lib/Target/X86/X86AsmPrinter.h:1.28	Wed Sep  6 13:34:40 2006
+++ llvm/lib/Target/X86/X86AsmPrinter.h	Thu Sep  7 17:06:40 2006
@@ -22,7 +22,6 @@
 #include "llvm/CodeGen/DwarfWriter.h"
 #include "llvm/CodeGen/MachineDebugInfo.h"
 #include "llvm/ADT/Statistic.h"
-#include "llvm/Target/TargetAsmInfo.h"
 #include <set>
 
 
@@ -30,15 +29,11 @@
 
 extern Statistic<> EmittedInsts;
 
-struct VISIBILITY_HIDDEN X86TargetAsmInfo : public TargetAsmInfo {
-  X86TargetAsmInfo(X86TargetMachine &TM);
-};
-
 struct VISIBILITY_HIDDEN X86SharedAsmPrinter : public AsmPrinter {
   DwarfWriter DW;
 
   X86SharedAsmPrinter(std::ostream &O, X86TargetMachine &TM,
-                      TargetAsmInfo *T)
+                      const TargetAsmInfo *T)
     : AsmPrinter(O, TM, T), DW(O, this, T) {
     Subtarget = &TM.getSubtarget<X86Subtarget>();
   }


Index: llvm/lib/Target/X86/X86IntelAsmPrinter.cpp
diff -u llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.53 llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.54
--- llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.53	Wed Sep  6 13:34:40 2006
+++ llvm/lib/Target/X86/X86IntelAsmPrinter.cpp	Thu Sep  7 17:06:40 2006
@@ -14,11 +14,13 @@
 //===----------------------------------------------------------------------===//
 
 #include "X86IntelAsmPrinter.h"
+#include "X86TargetAsmInfo.h"
 #include "X86.h"
 #include "llvm/Constants.h"
 #include "llvm/Module.h"
 #include "llvm/Assembly/Writer.h"
 #include "llvm/Support/Mangler.h"
+#include "llvm/Target/TargetAsmInfo.h"
 #include "llvm/Target/TargetOptions.h"
 using namespace llvm;
 


Index: llvm/lib/Target/X86/X86IntelAsmPrinter.h
diff -u llvm/lib/Target/X86/X86IntelAsmPrinter.h:1.22 llvm/lib/Target/X86/X86IntelAsmPrinter.h:1.23
--- llvm/lib/Target/X86/X86IntelAsmPrinter.h:1.22	Wed Sep  6 13:34:40 2006
+++ llvm/lib/Target/X86/X86IntelAsmPrinter.h	Thu Sep  7 17:06:40 2006
@@ -21,7 +21,8 @@
 namespace llvm {
 
 struct X86IntelAsmPrinter : public X86SharedAsmPrinter {
-  X86IntelAsmPrinter(std::ostream &O, X86TargetMachine &TM, TargetAsmInfo *T)
+  X86IntelAsmPrinter(std::ostream &O, X86TargetMachine &TM,
+                     const TargetAsmInfo *T)
       : X86SharedAsmPrinter(O, TM, T) {
   }
 


Index: llvm/lib/Target/X86/X86TargetMachine.h
diff -u llvm/lib/Target/X86/X86TargetMachine.h:1.38 llvm/lib/Target/X86/X86TargetMachine.h:1.39
--- llvm/lib/Target/X86/X86TargetMachine.h:1.38	Sun Sep  3 23:14:57 2006
+++ llvm/lib/Target/X86/X86TargetMachine.h	Thu Sep  7 17:06:40 2006
@@ -21,6 +21,7 @@
 #include "X86InstrInfo.h"
 #include "X86JITInfo.h"
 #include "X86Subtarget.h"
+#include "X86TargetAsmInfo.h"
 #include "X86ISelLowering.h"
 
 namespace llvm {
@@ -50,6 +51,9 @@
   static unsigned getModuleMatchQuality(const Module &M);
   static unsigned getJITMatchQuality();
   
+  virtual const TargetAsmInfo *createTargetAsmInfo() const {
+    return static_cast<const TargetAsmInfo *>(new X86TargetAsmInfo(*this));
+  }
   
   // Set up the pass pipeline.
   virtual bool addInstSelector(FunctionPassManager &PM, bool Fast);  





From jlaskey at apple.com  Thu Sep  7 17:07:08 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Thu, 7 Sep 2006 17:07:08 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/AsmPrinter.cpp DwarfWriter.cpp
Message-ID: <200609072207.k87M78Q9012397@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen:

AsmPrinter.cpp updated: 1.92 -> 1.93
DwarfWriter.cpp updated: 1.74 -> 1.75
---
Log message:

Make target asm info a property of the target machine.


---
Diffs of the changes:  (+20 -18)

 AsmPrinter.cpp  |    3 ++-
 DwarfWriter.cpp |   35 ++++++++++++++++++-----------------
 2 files changed, 20 insertions(+), 18 deletions(-)


Index: llvm/lib/CodeGen/AsmPrinter.cpp
diff -u llvm/lib/CodeGen/AsmPrinter.cpp:1.92 llvm/lib/CodeGen/AsmPrinter.cpp:1.93
--- llvm/lib/CodeGen/AsmPrinter.cpp:1.92	Thu Sep  7 13:50:20 2006
+++ llvm/lib/CodeGen/AsmPrinter.cpp	Thu Sep  7 17:06:40 2006
@@ -27,7 +27,8 @@
 #include <cerrno>
 using namespace llvm;
 
-AsmPrinter::AsmPrinter(std::ostream &o, TargetMachine &tm, TargetAsmInfo *T)
+AsmPrinter::AsmPrinter(std::ostream &o, TargetMachine &tm,
+                       const TargetAsmInfo *T)
 : FunctionNumber(0), O(o), TM(tm), TAI(T)
 {}
 


Index: llvm/lib/CodeGen/DwarfWriter.cpp
diff -u llvm/lib/CodeGen/DwarfWriter.cpp:1.74 llvm/lib/CodeGen/DwarfWriter.cpp:1.75
--- llvm/lib/CodeGen/DwarfWriter.cpp:1.74	Wed Sep  6 13:34:40 2006
+++ llvm/lib/CodeGen/DwarfWriter.cpp	Thu Sep  7 17:06:40 2006
@@ -574,24 +574,24 @@
 }
 
 #ifndef NDEBUG
-  void DIEAbbrev::print(std::ostream &O) {
-    O << "Abbreviation @"
-      << std::hex << (intptr_t)this << std::dec
+void DIEAbbrev::print(std::ostream &O) {
+  O << "Abbreviation @"
+    << std::hex << (intptr_t)this << std::dec
+    << "  "
+    << TagString(Tag)
+    << " "
+    << ChildrenString(ChildrenFlag)
+    << "\n";
+  
+  for (unsigned i = 0, N = Data.size(); i < N; ++i) {
+    O << "  "
+      << AttributeString(Data[i].getAttribute())
       << "  "
-      << TagString(Tag)
-      << " "
-      << ChildrenString(ChildrenFlag)
+      << FormEncodingString(Data[i].getForm())
       << "\n";
-    
-    for (unsigned i = 0, N = Data.size(); i < N; ++i) {
-      O << "  "
-        << AttributeString(Data[i].getAttribute())
-        << "  "
-        << FormEncodingString(Data[i].getForm())
-        << "\n";
-    }
   }
-  void DIEAbbrev::dump() { print(std::cerr); }
+}
+void DIEAbbrev::dump() { print(std::cerr); }
 #endif
 
 //===----------------------------------------------------------------------===//
@@ -1160,7 +1160,7 @@
 /// is an option (needsSet) to use an intermediary 'set' expression.
 void DwarfWriter::EmitDifference(const char *TagHi, unsigned NumberHi,
                                  const char *TagLo, unsigned NumberLo) const {
-  if (TAI->getNeedsSet()) {
+  if (TAI->needsSet()) {
     static unsigned SetCounter = 0;
     
     O << "\t.set\t";
@@ -2467,7 +2467,8 @@
 // Main entry points.
 //
   
-DwarfWriter::DwarfWriter(std::ostream &OS, AsmPrinter *A, TargetAsmInfo *T)
+DwarfWriter::DwarfWriter(std::ostream &OS, AsmPrinter *A,
+  const TargetAsmInfo *T)
 : O(OS)
 , Asm(A)
 , TAI(T)





From jlaskey at apple.com  Thu Sep  7 17:07:09 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Thu, 7 Sep 2006 17:07:09 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
	PPCTargetMachine.h
Message-ID: <200609072207.k87M79X0012416@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCAsmPrinter.cpp updated: 1.193 -> 1.194
PPCTargetMachine.h updated: 1.23 -> 1.24
---
Log message:

Make target asm info a property of the target machine.


---
Diffs of the changes:  (+8 -40)

 PPCAsmPrinter.cpp  |   44 ++++----------------------------------------
 PPCTargetMachine.h |    4 ++++
 2 files changed, 8 insertions(+), 40 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
diff -u llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.193 llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.194
--- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.193	Wed Sep  6 13:34:40 2006
+++ llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp	Thu Sep  7 17:06:40 2006
@@ -50,7 +50,7 @@
   struct VISIBILITY_HIDDEN PPCAsmPrinter : public AsmPrinter {
     std::set<std::string> FnStubs, GVStubs;
     
-    PPCAsmPrinter(std::ostream &O, TargetMachine &TM, TargetAsmInfo *T)
+    PPCAsmPrinter(std::ostream &O, TargetMachine &TM, const TargetAsmInfo *T)
       : AsmPrinter(O, TM, T) {}
 
     virtual const char *getPassName() const {
@@ -239,49 +239,14 @@
     
   };
 
-  struct VISIBILITY_HIDDEN DarwinTargetAsmInfo : public TargetAsmInfo {
-    DarwinTargetAsmInfo(PPCTargetMachine &TM) {
-      bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
-
-      CommentString = ";";
-      GlobalPrefix = "_";
-      PrivateGlobalPrefix = "L";
-      ZeroDirective = "\t.space\t";
-      SetDirective = "\t.set";
-      Data64bitsDirective = isPPC64 ? ".quad\t" : 0;  
-      AlignmentIsInBytes = false;
-      ConstantPoolSection = "\t.const\t";
-      JumpTableDataSection = ".const";
-      JumpTableTextSection = "\t.text";
-      LCOMMDirective = "\t.lcomm\t";
-      StaticCtorsSection = ".mod_init_func";
-      StaticDtorsSection = ".mod_term_func";
-      InlineAsmStart = "# InlineAsm Start";
-      InlineAsmEnd = "# InlineAsm End";
-      
-      NeedsSet = true;
-      AddressSize = isPPC64 ? 8 : 4;
-      DwarfAbbrevSection = ".section __DWARF,__debug_abbrev";
-      DwarfInfoSection = ".section __DWARF,__debug_info";
-      DwarfLineSection = ".section __DWARF,__debug_line";
-      DwarfFrameSection = ".section __DWARF,__debug_frame";
-      DwarfPubNamesSection = ".section __DWARF,__debug_pubnames";
-      DwarfPubTypesSection = ".section __DWARF,__debug_pubtypes";
-      DwarfStrSection = ".section __DWARF,__debug_str";
-      DwarfLocSection = ".section __DWARF,__debug_loc";
-      DwarfARangesSection = ".section __DWARF,__debug_aranges";
-      DwarfRangesSection = ".section __DWARF,__debug_ranges";
-      DwarfMacInfoSection = ".section __DWARF,__debug_macinfo";
-    }
-  };
-
   /// DarwinAsmPrinter - PowerPC assembly printer, customized for Darwin/Mac OS
   /// X
   struct VISIBILITY_HIDDEN DarwinAsmPrinter : public PPCAsmPrinter {
   
     DwarfWriter DW;
 
-    DarwinAsmPrinter(std::ostream &O, PPCTargetMachine &TM, TargetAsmInfo *T)
+    DarwinAsmPrinter(std::ostream &O, PPCTargetMachine &TM,
+                     const TargetAsmInfo *T)
       : PPCAsmPrinter(O, TM, T), DW(O, this, T) {
       bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
     }
@@ -309,8 +274,7 @@
 ///
 FunctionPass *llvm::createDarwinCodePrinterPass(std::ostream &o,
                                                 PPCTargetMachine &tm) {
-  TargetAsmInfo *TAI = new DarwinTargetAsmInfo(tm);
-  return new DarwinAsmPrinter(o, tm, TAI);
+  return new DarwinAsmPrinter(o, tm, tm.getTargetAsmInfo());
 }
 
 // Include the auto-generated portion of the assembly writer


Index: llvm/lib/Target/PowerPC/PPCTargetMachine.h
diff -u llvm/lib/Target/PowerPC/PPCTargetMachine.h:1.23 llvm/lib/Target/PowerPC/PPCTargetMachine.h:1.24
--- llvm/lib/Target/PowerPC/PPCTargetMachine.h:1.23	Sun Sep  3 23:14:57 2006
+++ llvm/lib/Target/PowerPC/PPCTargetMachine.h	Thu Sep  7 17:06:40 2006
@@ -19,6 +19,7 @@
 #include "PPCJITInfo.h"
 #include "PPCInstrInfo.h"
 #include "PPCISelLowering.h"
+#include "PPCTargetAsmInfo.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetData.h"
 
@@ -55,6 +56,9 @@
     return InstrItins;
   }
   
+  virtual const TargetAsmInfo *createTargetAsmInfo() const {
+    return static_cast<const TargetAsmInfo *>(new DarwinTargetAsmInfo(*this));
+  }
   
   // Pass Pipeline Configuration
   virtual bool addInstSelector(FunctionPassManager &PM, bool Fast);





From jlaskey at apple.com  Thu Sep  7 17:07:09 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Thu, 7 Sep 2006 17:07:09 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp
	AlphaTargetMachine.cpp AlphaTargetMachine.h
Message-ID: <200609072207.k87M79g8012408@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaAsmPrinter.cpp updated: 1.47 -> 1.48
AlphaTargetMachine.cpp updated: 1.29 -> 1.30
AlphaTargetMachine.h updated: 1.15 -> 1.16
---
Log message:

Make target asm info a property of the target machine.


---
Diffs of the changes:  (+13 -11)

 AlphaAsmPrinter.cpp    |   12 ++----------
 AlphaTargetMachine.cpp |    3 ++-
 AlphaTargetMachine.h   |    9 +++++++++
 3 files changed, 13 insertions(+), 11 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp
diff -u llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.47 llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.48
--- llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.47	Wed Sep  6 13:34:40 2006
+++ llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp	Thu Sep  7 17:06:40 2006
@@ -29,20 +29,13 @@
 namespace {
   Statistic<> EmittedInsts("asm-printer", "Number of machine instrs printed");
   
-  struct VISIBILITY_HIDDEN AlphaTargetAsmInfo : public TargetAsmInfo {
-    AlphaTargetAsmInfo() {
-      AlignmentIsInBytes = false;
-      PrivateGlobalPrefix = "$";
-    }
-  };
-
   struct VISIBILITY_HIDDEN AlphaAsmPrinter : public AsmPrinter {
 
     /// Unique incrementer for label values for referencing Global values.
     ///
     unsigned LabelNumber;
 
-    AlphaAsmPrinter(std::ostream &o, TargetMachine &tm, TargetAsmInfo *T)
+    AlphaAsmPrinter(std::ostream &o, TargetMachine &tm, const TargetAsmInfo *T)
        : AsmPrinter(o, tm, T), LabelNumber(0) {
     }
 
@@ -82,8 +75,7 @@
 ///
 FunctionPass *llvm::createAlphaCodePrinterPass (std::ostream &o,
                                                   TargetMachine &tm) {
-  AlphaTargetAsmInfo *TAI = new AlphaTargetAsmInfo();
-  return new AlphaAsmPrinter(o, tm, TAI);
+  return new AlphaAsmPrinter(o, tm, tm.getTargetAsmInfo());
 }
 
 #include "AlphaGenAsmWriter.inc"


Index: llvm/lib/Target/Alpha/AlphaTargetMachine.cpp
diff -u llvm/lib/Target/Alpha/AlphaTargetMachine.cpp:1.29 llvm/lib/Target/Alpha/AlphaTargetMachine.cpp:1.30
--- llvm/lib/Target/Alpha/AlphaTargetMachine.cpp:1.29	Sun Sep  3 23:14:57 2006
+++ llvm/lib/Target/Alpha/AlphaTargetMachine.cpp	Thu Sep  7 17:06:40 2006
@@ -53,7 +53,8 @@
   : DataLayout("e"),
     FrameInfo(TargetFrameInfo::StackGrowsDown, 16, 0),
     JITInfo(*this),
-    Subtarget(M, FS) {
+    Subtarget(M, FS),
+    AsmInfo(NULL) {
 }
 
 


Index: llvm/lib/Target/Alpha/AlphaTargetMachine.h
diff -u llvm/lib/Target/Alpha/AlphaTargetMachine.h:1.15 llvm/lib/Target/Alpha/AlphaTargetMachine.h:1.16
--- llvm/lib/Target/Alpha/AlphaTargetMachine.h:1.15	Sun Sep  3 23:14:57 2006
+++ llvm/lib/Target/Alpha/AlphaTargetMachine.h	Thu Sep  7 17:06:40 2006
@@ -20,6 +20,7 @@
 #include "AlphaInstrInfo.h"
 #include "AlphaJITInfo.h"
 #include "AlphaSubtarget.h"
+#include "AlphaTargetAsmInfo.h"
 
 namespace llvm {
 
@@ -31,9 +32,13 @@
   TargetFrameInfo FrameInfo;
   AlphaJITInfo JITInfo;
   AlphaSubtarget Subtarget;
+  AlphaTargetAsmInfo *AsmInfo;
   
 public:
   AlphaTargetMachine(const Module &M, const std::string &FS);
+  ~AlphaTargetMachine() {
+    if (AsmInfo) delete AsmInfo;
+  }
 
   virtual const AlphaInstrInfo *getInstrInfo() const { return &InstrInfo; }
   virtual const TargetFrameInfo  *getFrameInfo() const { return &FrameInfo; }
@@ -46,6 +51,10 @@
     return &JITInfo;
   }
 
+  virtual const TargetAsmInfo *createTargetAsmInfo() const {
+    return static_cast<const TargetAsmInfo *>(new AlphaTargetAsmInfo(*this));
+  }
+
   static unsigned getJITMatchQuality();
   static unsigned getModuleMatchQuality(const Module &M);
   





From jlaskey at apple.com  Thu Sep  7 17:07:09 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Thu, 7 Sep 2006 17:07:09 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/AsmPrinter.h
	DwarfWriter.h
Message-ID: <200609072207.k87M79p9012410@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

AsmPrinter.h updated: 1.46 -> 1.47
DwarfWriter.h updated: 1.39 -> 1.40
---
Log message:

Make target asm info a property of the target machine.


---
Diffs of the changes:  (+5 -5)

 AsmPrinter.h  |    4 ++--
 DwarfWriter.h |    6 +++---
 2 files changed, 5 insertions(+), 5 deletions(-)


Index: llvm/include/llvm/CodeGen/AsmPrinter.h
diff -u llvm/include/llvm/CodeGen/AsmPrinter.h:1.46 llvm/include/llvm/CodeGen/AsmPrinter.h:1.47
--- llvm/include/llvm/CodeGen/AsmPrinter.h:1.46	Wed Sep  6 13:34:40 2006
+++ llvm/include/llvm/CodeGen/AsmPrinter.h	Thu Sep  7 17:06:40 2006
@@ -49,7 +49,7 @@
     
     /// Target Asm Printer information.
     ///
-    TargetAsmInfo *TAI;
+    const TargetAsmInfo *TAI;
 
     /// Name-mangler for global names.
     ///
@@ -65,7 +65,7 @@
     std::string CurrentSection;
   
   protected:
-    AsmPrinter(std::ostream &o, TargetMachine &TM, TargetAsmInfo *T);
+    AsmPrinter(std::ostream &o, TargetMachine &TM, const TargetAsmInfo *T);
     
   public:
     /// SwitchToTextSection - Switch to the specified section of the executable


Index: llvm/include/llvm/CodeGen/DwarfWriter.h
diff -u llvm/include/llvm/CodeGen/DwarfWriter.h:1.39 llvm/include/llvm/CodeGen/DwarfWriter.h:1.40
--- llvm/include/llvm/CodeGen/DwarfWriter.h:1.39	Wed Sep  6 13:34:40 2006
+++ llvm/include/llvm/CodeGen/DwarfWriter.h	Thu Sep  7 17:06:40 2006
@@ -88,7 +88,7 @@
   AsmPrinter *Asm;
   
   /// TAI - Target Asm Printer.
-  TargetAsmInfo *TAI;
+  const TargetAsmInfo *TAI;
   
   /// TD - Target data.
   const TargetData *TD;
@@ -387,12 +387,12 @@
 
 public:
   
-  DwarfWriter(std::ostream &OS, AsmPrinter *A, TargetAsmInfo *T);
+  DwarfWriter(std::ostream &OS, AsmPrinter *A, const TargetAsmInfo *T);
   virtual ~DwarfWriter();
   
   // Accessors.
   //
-  TargetAsmInfo *getTargetAsmInfo() const { return TAI; }
+  const TargetAsmInfo *getTargetAsmInfo() const { return TAI; }
   
   /// SetDebugInfo - Set DebugInfo when it's known that pass manager has
   /// created it.  Set by the target AsmPrinter.





From jlaskey at apple.com  Thu Sep  7 17:07:08 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Thu, 7 Sep 2006 17:07:08 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/IA64/IA64AsmPrinter.cpp
	IA64TargetMachine.h
Message-ID: <200609072207.k87M7835012390@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/IA64:

IA64AsmPrinter.cpp updated: 1.34 -> 1.35
IA64TargetMachine.h updated: 1.13 -> 1.14
---
Log message:

Make target asm info a property of the target machine.


---
Diffs of the changes:  (+8 -24)

 IA64AsmPrinter.cpp  |   27 +++------------------------
 IA64TargetMachine.h |    5 +++++
 2 files changed, 8 insertions(+), 24 deletions(-)


Index: llvm/lib/Target/IA64/IA64AsmPrinter.cpp
diff -u llvm/lib/Target/IA64/IA64AsmPrinter.cpp:1.34 llvm/lib/Target/IA64/IA64AsmPrinter.cpp:1.35
--- llvm/lib/Target/IA64/IA64AsmPrinter.cpp:1.34	Wed Sep  6 13:34:40 2006
+++ llvm/lib/Target/IA64/IA64AsmPrinter.cpp	Thu Sep  7 17:06:40 2006
@@ -23,8 +23,8 @@
 #include "llvm/Assembly/Writer.h"
 #include "llvm/CodeGen/AsmPrinter.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
-#include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetAsmInfo.h"
+#include "llvm/Target/TargetMachine.h"
 #include "llvm/Support/Mangler.h"
 #include "llvm/ADT/Statistic.h"
 #include <iostream>
@@ -32,31 +32,11 @@
 
 namespace {
   Statistic<> EmittedInsts("asm-printer", "Number of machine instrs printed");
-
-  struct VISIBILITY_HIDDEN IA64TargetAsmInfo : public TargetAsmInfo {
-    IA64TargetAsmInfo() {
-      CommentString = "//";
-      Data8bitsDirective = "\tdata1\t";     // FIXME: check that we are
-      Data16bitsDirective = "\tdata2.ua\t"; // disabling auto-alignment
-      Data32bitsDirective = "\tdata4.ua\t"; // properly
-      Data64bitsDirective = "\tdata8.ua\t";
-      ZeroDirective = "\t.skip\t";
-      AsciiDirective = "\tstring\t";
-
-      GlobalVarAddrPrefix="";
-      GlobalVarAddrSuffix="";
-      FunctionAddrPrefix="@fptr(";
-      FunctionAddrSuffix=")";
-      
-      // FIXME: would be nice to have rodata (no 'w') when appropriate?
-      ConstantPoolSection = "\n\t.section .data, \"aw\", \"progbits\"\n";
-    }
-  };
   
   struct IA64AsmPrinter : public AsmPrinter {
     std::set<std::string> ExternalFunctionNames, ExternalObjectNames;
 
-    IA64AsmPrinter(std::ostream &O, TargetMachine &TM, TargetAsmInfo *T)
+    IA64AsmPrinter(std::ostream &O, TargetMachine &TM, const TargetAsmInfo *T)
       : AsmPrinter(O, TM, T) {
     }
 
@@ -366,8 +346,7 @@
 ///
 FunctionPass *llvm::createIA64CodePrinterPass(std::ostream &o,
                                               IA64TargetMachine &tm) {
-  IA64TargetAsmInfo *TAI = new IA64TargetAsmInfo();
-  return new IA64AsmPrinter(o, tm, TAI);
+  return new IA64AsmPrinter(o, tm, tm.getTargetAsmInfo());
 }
 
 


Index: llvm/lib/Target/IA64/IA64TargetMachine.h
diff -u llvm/lib/Target/IA64/IA64TargetMachine.h:1.13 llvm/lib/Target/IA64/IA64TargetMachine.h:1.14
--- llvm/lib/Target/IA64/IA64TargetMachine.h:1.13	Sun Sep  3 23:14:57 2006
+++ llvm/lib/Target/IA64/IA64TargetMachine.h	Thu Sep  7 17:06:40 2006
@@ -19,6 +19,7 @@
 #include "llvm/Target/TargetFrameInfo.h"
 #include "IA64InstrInfo.h"
 #include "IA64ISelLowering.h"
+#include "IA64TargetAsmInfo.h"
 
 namespace llvm {
 
@@ -40,6 +41,10 @@
     return &InstrInfo.getRegisterInfo();
   }
   virtual const TargetData       *getTargetData() const { return &DataLayout; }
+  
+  virtual const TargetAsmInfo *createTargetAsmInfo() const {
+    return static_cast<const TargetAsmInfo *>(new IA64TargetAsmInfo(*this));
+  }
 
   static unsigned getModuleMatchQuality(const Module &M);
 





From jlaskey at apple.com  Thu Sep  7 17:07:09 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Thu, 7 Sep 2006 17:07:09 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetAsmInfo.h
	TargetMachine.h
Message-ID: <200609072207.k87M79qY012427@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/Target:

TargetAsmInfo.h updated: 1.1 -> 1.2
TargetMachine.h updated: 1.69 -> 1.70
---
Log message:

Make target asm info a property of the target machine.


---
Diffs of the changes:  (+23 -2)

 TargetAsmInfo.h |    5 ++++-
 TargetMachine.h |   20 +++++++++++++++++++-
 2 files changed, 23 insertions(+), 2 deletions(-)


Index: llvm/include/llvm/Target/TargetAsmInfo.h
diff -u llvm/include/llvm/Target/TargetAsmInfo.h:1.1 llvm/include/llvm/Target/TargetAsmInfo.h:1.2
--- llvm/include/llvm/Target/TargetAsmInfo.h:1.1	Wed Sep  6 13:35:33 2006
+++ llvm/include/llvm/Target/TargetAsmInfo.h	Thu Sep  7 17:06:40 2006
@@ -21,6 +21,9 @@
 
 namespace llvm {
 
+  // Forward declaration.
+  class TargetMachine;
+
   /// TargetAsmInfo - This class is intended to be used as a base class for asm
   /// properties and features specific to the target.
   class TargetAsmInfo {
@@ -266,7 +269,7 @@
     unsigned getAddressSize() const {
       return AddressSize;
     }
-    bool getNeedsSet() const {
+    bool needsSet() const {
       return NeedsSet;
     }
     const char *getCommentString() const {


Index: llvm/include/llvm/Target/TargetMachine.h
diff -u llvm/include/llvm/Target/TargetMachine.h:1.69 llvm/include/llvm/Target/TargetMachine.h:1.70
--- llvm/include/llvm/Target/TargetMachine.h:1.69	Sun Sep  3 23:14:57 2006
+++ llvm/include/llvm/Target/TargetMachine.h	Thu Sep  7 17:06:40 2006
@@ -20,6 +20,7 @@
 
 namespace llvm {
 
+class TargetAsmInfo;
 class TargetData;
 class TargetSubtarget;
 class TargetInstrInfo;
@@ -65,11 +66,16 @@
   TargetMachine(const TargetMachine &);   // DO NOT IMPLEMENT
   void operator=(const TargetMachine &);  // DO NOT IMPLEMENT
 protected: // Can only create subclasses.
-  TargetMachine() { }
+  TargetMachine() : AsmInfo(NULL) { }
 
   /// getSubtargetImpl - virtual method implemented by subclasses that returns
   /// a reference to that target's TargetSubtarget-derived member variable.
   virtual const TargetSubtarget *getSubtargetImpl() const { return 0; }
+  
+  /// AsmInfo - Contains target specific asm information.
+  ///
+  mutable const TargetAsmInfo *AsmInfo;
+  
 public:
   virtual ~TargetMachine();
 
@@ -96,6 +102,18 @@
   virtual const TargetFrameInfo        *getFrameInfo() const { return 0; }
   virtual       TargetLowering    *getTargetLowering() const { return 0; }
   virtual const TargetData            *getTargetData() const { return 0; }
+  
+  
+  /// getTargetAsmInfo - Return target specific asm information.
+  ///
+  const TargetAsmInfo *getTargetAsmInfo() const {
+    if (!AsmInfo) AsmInfo = createTargetAsmInfo();
+    return AsmInfo;
+  }
+  
+  /// createTargetAsmInfo - Create a new instance of target specific asm
+  /// information.
+  virtual const TargetAsmInfo *createTargetAsmInfo() const { return NULL; }
 
   /// getSubtarget - This method returns a pointer to the specified type of
   /// TargetSubtarget.  In debug builds, it verifies that the object being





From jlaskey at apple.com  Thu Sep  7 17:07:10 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Thu, 7 Sep 2006 17:07:10 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/ARM/ARMAsmPrinter.cpp
	ARMTargetMachine.h
Message-ID: <200609072207.k87M7ATZ012437@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/ARM:

ARMAsmPrinter.cpp updated: 1.15 -> 1.16
ARMTargetMachine.h updated: 1.3 -> 1.4
---
Log message:

Make target asm info a property of the target machine.


---
Diffs of the changes:  (+7 -15)

 ARMAsmPrinter.cpp  |   17 ++---------------
 ARMTargetMachine.h |    5 +++++
 2 files changed, 7 insertions(+), 15 deletions(-)


Index: llvm/lib/Target/ARM/ARMAsmPrinter.cpp
diff -u llvm/lib/Target/ARM/ARMAsmPrinter.cpp:1.15 llvm/lib/Target/ARM/ARMAsmPrinter.cpp:1.16
--- llvm/lib/Target/ARM/ARMAsmPrinter.cpp:1.15	Wed Sep  6 13:34:40 2006
+++ llvm/lib/Target/ARM/ARMAsmPrinter.cpp	Thu Sep  7 17:06:40 2006
@@ -38,20 +38,8 @@
 namespace {
   Statistic<> EmittedInsts("asm-printer", "Number of machine instrs printed");
 
-  struct VISIBILITY_HIDDEN ARMTargetAsmInfo : public TargetAsmInfo {
-    ARMTargetAsmInfo() {
-      Data16bitsDirective = "\t.half\t";
-      Data32bitsDirective = "\t.word\t";
-      Data64bitsDirective = 0;
-      ZeroDirective = "\t.skip\t";
-      CommentString = "@";
-      ConstantPoolSection = "\t.text\n";
-      AlignmentIsInBytes = false;
-    }
-  };
-
   struct VISIBILITY_HIDDEN ARMAsmPrinter : public AsmPrinter {
-    ARMAsmPrinter(std::ostream &O, TargetMachine &TM, TargetAsmInfo *T)
+    ARMAsmPrinter(std::ostream &O, TargetMachine &TM, const TargetAsmInfo *T)
       : AsmPrinter(O, TM, T) {
     }
 
@@ -113,8 +101,7 @@
 ///
 FunctionPass *llvm::createARMCodePrinterPass(std::ostream &o,
                                                TargetMachine &tm) {
-  ARMTargetAsmInfo *TAI = new ARMTargetAsmInfo();
-  return new ARMAsmPrinter(o, tm, TAI);
+  return new ARMAsmPrinter(o, tm, tm.getTargetAsmInfo());
 }
 
 /// runOnMachineFunction - This uses the printMachineInstruction()


Index: llvm/lib/Target/ARM/ARMTargetMachine.h
diff -u llvm/lib/Target/ARM/ARMTargetMachine.h:1.3 llvm/lib/Target/ARM/ARMTargetMachine.h:1.4
--- llvm/lib/Target/ARM/ARMTargetMachine.h:1.3	Sun Sep  3 23:14:57 2006
+++ llvm/lib/Target/ARM/ARMTargetMachine.h	Thu Sep  7 17:06:40 2006
@@ -20,6 +20,7 @@
 #include "llvm/Target/TargetFrameInfo.h"
 #include "ARMInstrInfo.h"
 #include "ARMFrameInfo.h"
+#include "ARMTargetAsmInfo.h"
 
 namespace llvm {
 
@@ -40,6 +41,10 @@
   virtual const TargetData       *getTargetData() const { return &DataLayout; }
   static unsigned getModuleMatchQuality(const Module &M);
 
+  virtual const TargetAsmInfo *createTargetAsmInfo() const {
+    return static_cast<const TargetAsmInfo *>(new ARMTargetAsmInfo(*this));
+  }
+
   // Pass Pipeline Configuration
   virtual bool addInstSelector(FunctionPassManager &PM, bool Fast);
   virtual bool addAssemblyEmitter(FunctionPassManager &PM, bool Fast, 





From jlaskey at apple.com  Thu Sep  7 17:07:10 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Thu, 7 Sep 2006 17:07:10 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/TargetMachine.cpp
Message-ID: <200609072207.k87M7AOv012432@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target:

TargetMachine.cpp updated: 1.53 -> 1.54
---
Log message:

Make target asm info a property of the target machine.


---
Diffs of the changes:  (+2 -0)

 TargetMachine.cpp |    2 ++
 1 files changed, 2 insertions(+)


Index: llvm/lib/Target/TargetMachine.cpp
diff -u llvm/lib/Target/TargetMachine.cpp:1.53 llvm/lib/Target/TargetMachine.cpp:1.54
--- llvm/lib/Target/TargetMachine.cpp:1.53	Sun Sep  3 23:06:01 2006
+++ llvm/lib/Target/TargetMachine.cpp	Thu Sep  7 17:06:40 2006
@@ -11,6 +11,7 @@
 //
 //===----------------------------------------------------------------------===//
 
+#include "llvm/Target/TargetAsmInfo.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetOptions.h"
 #include "llvm/Support/CommandLine.h"
@@ -95,6 +96,7 @@
 //
 
 TargetMachine::~TargetMachine() {
+  if (AsmInfo) delete AsmInfo;
 }
 
 /// getRelocationModel - Returns the code generation relocation model. The





From jlaskey at apple.com  Thu Sep  7 17:08:11 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Thu, 7 Sep 2006 17:08:11 -0500
Subject: [llvm-commits] CVS: llvm/Xcode/LLVM.xcodeproj/project.pbxproj
Message-ID: <200609072208.k87M8BPQ012468@zion.cs.uiuc.edu>



Changes in directory llvm/Xcode/LLVM.xcodeproj:

project.pbxproj updated: 1.23 -> 1.24
---
Log message:

Adding new files.


---
Diffs of the changes:  (+24 -0)

 project.pbxproj |   24 ++++++++++++++++++++++++
 1 files changed, 24 insertions(+)


Index: llvm/Xcode/LLVM.xcodeproj/project.pbxproj
diff -u llvm/Xcode/LLVM.xcodeproj/project.pbxproj:1.23 llvm/Xcode/LLVM.xcodeproj/project.pbxproj:1.24
--- llvm/Xcode/LLVM.xcodeproj/project.pbxproj:1.23	Wed Sep  6 13:38:54 2006
+++ llvm/Xcode/LLVM.xcodeproj/project.pbxproj	Thu Sep  7 17:07:57 2006
@@ -41,6 +41,18 @@
 /* Begin PBXFileReference section */
 		CF1ACC9709C9DE4400D3C5EB /* IntrinsicInst.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; name = IntrinsicInst.cpp; path = ../lib/VMCore/IntrinsicInst.cpp; sourceTree = "<group>"; };
 		CF26835B09178F5500C5F253 /* TargetInstrItineraries.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = TargetInstrItineraries.h; sourceTree = "<group>"; };
+		CF341DAD0AB07A8B0099B064 /* AlphaTargetAsmInfo.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = AlphaTargetAsmInfo.h; sourceTree = "<group>"; };
+		CF341DAE0AB07A8B0099B064 /* AlphaTargetAsmInfo.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; path = AlphaTargetAsmInfo.cpp; sourceTree = "<group>"; };
+		CF341DC30AB07E6B0099B064 /* ARMTargetAsmInfo.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = ARMTargetAsmInfo.h; sourceTree = "<group>"; };
+		CF341DC40AB07E6B0099B064 /* ARMTargetAsmInfo.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; path = ARMTargetAsmInfo.cpp; sourceTree = "<group>"; };
+		CF341DE80AB07F890099B064 /* IA64TargetAsmInfo.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = IA64TargetAsmInfo.h; sourceTree = "<group>"; };
+		CF341DE90AB07F890099B064 /* IA64TargetAsmInfo.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; path = IA64TargetAsmInfo.cpp; sourceTree = "<group>"; };
+		CF341E010AB080220099B064 /* PPCTargetAsmInfo.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = PPCTargetAsmInfo.h; sourceTree = "<group>"; };
+		CF341E020AB080220099B064 /* PPCTargetAsmInfo.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; path = PPCTargetAsmInfo.cpp; sourceTree = "<group>"; };
+		CF341E220AB0814B0099B064 /* SparcTargetAsmInfo.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = SparcTargetAsmInfo.h; sourceTree = "<group>"; };
+		CF341E230AB0814B0099B064 /* SparcTargetAsmInfo.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; path = SparcTargetAsmInfo.cpp; sourceTree = "<group>"; };
+		CF341E320AB082D60099B064 /* X86TargetAsmInfo.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = X86TargetAsmInfo.h; sourceTree = "<group>"; };
+		CF341E330AB082D60099B064 /* X86TargetAsmInfo.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; path = X86TargetAsmInfo.cpp; sourceTree = "<group>"; };
 		CF47BD380AAF40BC00A8B13E /* TargetAsmInfo.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = TargetAsmInfo.h; sourceTree = "<group>"; };
 		CF47BD860AAF487E00A8B13E /* TargetAsmInfo.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; path = TargetAsmInfo.cpp; sourceTree = "<group>"; };
 		CF490D14090541D30072DB1C /* TargetSchedule.td */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = text; path = TargetSchedule.td; sourceTree = "<group>"; };
@@ -938,6 +950,8 @@
 				CF9720490A9F3BBC002CEEDD /* ARMRegisterInfo.cpp */,
 				CF97204A0A9F3BBC002CEEDD /* ARMRegisterInfo.h */,
 				CF97204B0A9F3BBC002CEEDD /* ARMRegisterInfo.td */,
+				CF341DC40AB07E6B0099B064 /* ARMTargetAsmInfo.cpp */,
+				CF341DC30AB07E6B0099B064 /* ARMTargetAsmInfo.h */,
 				CF97204C0A9F3BBC002CEEDD /* ARMTargetMachine.cpp */,
 				CF97204D0A9F3BBC002CEEDD /* ARMTargetMachine.h */,
 			);
@@ -1394,6 +1408,8 @@
 				DE66EEAC08ABEE5E00323D32 /* AlphaRegisterInfo.h */,
 				DE66EEAD08ABEE5E00323D32 /* AlphaRegisterInfo.td */,
 				DE66EEAE08ABEE5E00323D32 /* AlphaRelocations.h */,
+				CF341DAE0AB07A8B0099B064 /* AlphaTargetAsmInfo.cpp */,
+				CF341DAD0AB07A8B0099B064 /* AlphaTargetAsmInfo.h */,
 				DE66EEAF08ABEE5E00323D32 /* AlphaTargetMachine.cpp */,
 				DE66EEB008ABEE5E00323D32 /* AlphaTargetMachine.h */,
 			);
@@ -1435,6 +1451,8 @@
 				DE66EF0808ABEE5E00323D32 /* IA64RegisterInfo.cpp */,
 				DE66EF0908ABEE5E00323D32 /* IA64RegisterInfo.h */,
 				DE66EF0A08ABEE5E00323D32 /* IA64RegisterInfo.td */,
+				CF341DE90AB07F890099B064 /* IA64TargetAsmInfo.cpp */,
+				CF341DE80AB07F890099B064 /* IA64TargetAsmInfo.h */,
 				DE66EF0B08ABEE5E00323D32 /* IA64TargetMachine.cpp */,
 				DE66EF0C08ABEE5E00323D32 /* IA64TargetMachine.h */,
 				DE66EF0E08ABEE5E00323D32 /* README */,
@@ -1488,6 +1506,8 @@
 				CFE421310A66FA2D00AB4BF6 /* PPCScheduleG5.td */,
 				CFE421320A66FA2E00AB4BF6 /* PPCSubtarget.cpp */,
 				CFE421330A66FA2E00AB4BF6 /* PPCSubtarget.h */,
+				CF341E020AB080220099B064 /* PPCTargetAsmInfo.cpp */,
+				CF341E010AB080220099B064 /* PPCTargetAsmInfo.h */,
 				CFE421340A66FA2E00AB4BF6 /* PPCTargetMachine.cpp */,
 				CFE421350A66FA2E00AB4BF6 /* PPCTargetMachine.h */,
 				CFE421360A66FA2E00AB4BF6 /* README_ALTIVEC.txt */,
@@ -1524,6 +1544,8 @@
 				CF65281009D1BA3800C4B521 /* SparcRegisterInfo.td */,
 				CF65281109D1BA3800C4B521 /* SparcSubtarget.cpp */,
 				CF65281209D1BA3800C4B521 /* SparcSubtarget.h */,
+				CF341E230AB0814B0099B064 /* SparcTargetAsmInfo.cpp */,
+				CF341E220AB0814B0099B064 /* SparcTargetAsmInfo.h */,
 				CF65281309D1BA3800C4B521 /* SparcTargetMachine.cpp */,
 				CF65281409D1BA3800C4B521 /* SparcTargetMachine.h */,
 			);
@@ -1575,6 +1597,8 @@
 				CFC244BD0959F24C009F8C47 /* X86ISelLowering.h */,
 				DE66F0DC08ABEE6100323D32 /* X86Subtarget.cpp */,
 				DE66F0DD08ABEE6100323D32 /* X86Subtarget.h */,
+				CF341E330AB082D60099B064 /* X86TargetAsmInfo.cpp */,
+				CF341E320AB082D60099B064 /* X86TargetAsmInfo.h */,
 				DE66F0DE08ABEE6100323D32 /* X86TargetMachine.cpp */,
 				DE66F0DF08ABEE6100323D32 /* X86TargetMachine.h */,
 			);





From lattner at cs.uiuc.edu  Thu Sep  7 17:29:55 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 7 Sep 2006 17:29:55 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86Subtarget.cpp
Message-ID: <200609072229.k87MTtDg012895@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86Subtarget.cpp updated: 1.29 -> 1.30
---
Log message:

Fix a cross-build issue.  The asmsyntax shouldn't be affected by the build 
host, it should be affected by the target.  Allow the command line option to
override in either case.


---
Diffs of the changes:  (+12 -8)

 X86Subtarget.cpp |   20 ++++++++++++--------
 1 files changed, 12 insertions(+), 8 deletions(-)


Index: llvm/lib/Target/X86/X86Subtarget.cpp
diff -u llvm/lib/Target/X86/X86Subtarget.cpp:1.29 llvm/lib/Target/X86/X86Subtarget.cpp:1.30
--- llvm/lib/Target/X86/X86Subtarget.cpp:1.29	Thu Sep  7 07:23:47 2006
+++ llvm/lib/Target/X86/X86Subtarget.cpp	Thu Sep  7 17:29:41 2006
@@ -18,18 +18,12 @@
 using namespace llvm;
 
 cl::opt<X86Subtarget::AsmWriterFlavorTy>
-AsmWriterFlavor("x86-asm-syntax",
+AsmWriterFlavor("x86-asm-syntax", cl::init(X86Subtarget::unset),
   cl::desc("Choose style of code to emit from X86 backend:"),
   cl::values(
     clEnumValN(X86Subtarget::att,   "att",   "  Emit AT&T-style assembly"),
     clEnumValN(X86Subtarget::intel, "intel", "  Emit Intel-style assembly"),
-    clEnumValEnd),
-#ifdef _MSC_VER
-  cl::init(X86Subtarget::intel)
-#else
-  cl::init(X86Subtarget::att)
-#endif
-                );
+    clEnumValEnd));
 
 /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
 /// specified arguments.  If we can't run cpuid on the host, return true.
@@ -199,6 +193,16 @@
 #endif
   }
 
+  // If the asm syntax hasn't been overridden on the command line, use whatever
+  // the target wants.
+  if (AsmFlavor == X86Subtarget::unset) {
+    if (TargetType == isWindows) {
+      AsmFlavor = X86Subtarget::intel;
+    } else {
+      AsmFlavor = X86Subtarget::att;
+    }
+  }
+
   if (TargetType == isDarwin || TargetType == isCygwin)
     stackAlignment = 16;
 }





From lattner at cs.uiuc.edu  Thu Sep  7 17:32:42 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Thu, 7 Sep 2006 17:32:42 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86Subtarget.h
Message-ID: <200609072232.k87MWgCG012971@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86Subtarget.h updated: 1.14 -> 1.15
---
Log message:

add a new value for the command line optn



---
Diffs of the changes:  (+1 -1)

 X86Subtarget.h |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/X86/X86Subtarget.h
diff -u llvm/lib/Target/X86/X86Subtarget.h:1.14 llvm/lib/Target/X86/X86Subtarget.h:1.15
--- llvm/lib/Target/X86/X86Subtarget.h:1.14	Thu Sep  7 07:23:47 2006
+++ llvm/lib/Target/X86/X86Subtarget.h	Thu Sep  7 17:32:28 2006
@@ -24,7 +24,7 @@
 class X86Subtarget : public TargetSubtarget {
 public:
   enum AsmWriterFlavorTy {
-    att, intel
+    att, intel, unset
   };
 
 protected:





From isanbard at gmail.com  Thu Sep  7 18:17:34 2006
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 7 Sep 2006 18:17:34 -0500
Subject: [llvm-commits] CVS: llvm-test/External/SPEC/CINT2006/Makefile
Message-ID: <200609072317.k87NHY9K013664@zion.cs.uiuc.edu>



Changes in directory llvm-test/External/SPEC/CINT2006:

Makefile updated: 1.2 -> 1.3
---
Log message:

Added support for multi-directories: go benchmark and omnetpp (whatever
that is)


---
Diffs of the changes:  (+5 -5)

 Makefile |   10 +++++-----
 1 files changed, 5 insertions(+), 5 deletions(-)


Index: llvm-test/External/SPEC/CINT2006/Makefile
diff -u llvm-test/External/SPEC/CINT2006/Makefile:1.2 llvm-test/External/SPEC/CINT2006/Makefile:1.3
--- llvm-test/External/SPEC/CINT2006/Makefile:1.2	Wed Sep  6 16:55:34 2006
+++ llvm-test/External/SPEC/CINT2006/Makefile	Thu Sep  7 18:17:18 2006
@@ -7,17 +7,17 @@
 LEVEL = ../../..
 PARALLEL_DIRS := \
         400.perlbench  \
-	401.bzip2      \
-	403.gcc        \
-	429.mcf        \
+        401.bzip2      \
+        403.gcc        \
+        429.mcf        \
+        445.gobmk      \
         456.hmmer      \
         458.sjeng      \
         462.libquantum \
         464.h264ref    \
+        471.omnetpp    \
         473.astar
 
-# 445.gobmk     -- Multiple Dirs
-# 471.omnetpp   -- Multiple Dirs
 # 483.xalancbmk -- Needs C++ Exceptions
 
 # Get the $(ARCH) setting





From isanbard at gmail.com  Thu Sep  7 18:17:37 2006
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 7 Sep 2006 18:17:37 -0500
Subject: [llvm-commits] CVS:
	llvm-test/External/SPEC/CINT2006/471.omnetpp/Makefile
Message-ID: <200609072317.k87NHbTZ013681@zion.cs.uiuc.edu>



Changes in directory llvm-test/External/SPEC/CINT2006/471.omnetpp:

Makefile updated: 1.3 -> 1.4
---
Log message:

Added support for multi-directories: go benchmark and omnetpp (whatever
that is)


---
Diffs of the changes:  (+50 -7)

 Makefile |   57 ++++++++++++++++++++++++++++++++++++++++++++++++++-------
 1 files changed, 50 insertions(+), 7 deletions(-)


Index: llvm-test/External/SPEC/CINT2006/471.omnetpp/Makefile
diff -u llvm-test/External/SPEC/CINT2006/471.omnetpp/Makefile:1.3 llvm-test/External/SPEC/CINT2006/471.omnetpp/Makefile:1.4
--- llvm-test/External/SPEC/CINT2006/471.omnetpp/Makefile:1.3	Wed Sep  6 15:41:12 2006
+++ llvm-test/External/SPEC/CINT2006/471.omnetpp/Makefile	Thu Sep  7 18:17:18 2006
@@ -9,7 +9,8 @@
 FP_TOLERANCE    = 0.00001
 FP_ABSTOLERANCE = 0.000001
 
-Source = $(addprefix $(SPEC_BENCH_DIR)/src/,                                   \
+TOPSources    := \
+         $(addprefix $(SPEC_BENCH_DIR)/src/,                                   \
            EtherAppCli.cc EtherAppCli_n.cc EtherAppSrv.cc EtherAppSrv_n.cc     \
            EtherApp_m.cc EtherBus.cc EtherBus_n.cc EtherCtrl_m.cc              \
            EtherEncap.cc EtherEncap_n.cc EtherFrame_m.cc EtherHost_n.cc        \
@@ -17,12 +18,15 @@
            EtherMAC_n.cc EtherSwitch_n.cc LargeNet_n.cc MACAddress.cc          \
            MACAddress_m.cc MACRelayUnitBase.cc MACRelayUnitNP.cc               \
            MACRelayUnitNP_n.cc MACRelayUnitPP.cc MACRelayUnitPP_n.cc           \
-           MACRelayUnit_n.cc Networks_n.cc eth-index_n.cc utils.cc)            \
+           MACRelayUnit_n.cc Networks_n.cc eth-index_n.cc utils.cc)
+CMDENVSources := \
          $(addprefix $(SPEC_BENCH_DIR)/src/libs/cmdenv/,                       \
-           cmdenv.cc enumstr.cc heap.cc)                                       \
+           cmdenv.cc enumstr.cc heap.cc)
+ENVIRSources  := \
          $(addprefix $(SPEC_BENCH_DIR)/src/libs/envir/,                        \
            akoutvectormgr.cc args.cc cenvir.cc cinifile.cc filemgrs.cc main.cc \
-           omnetapp.cc patmatch.cc platdep.cc seeds.cc slaveapp.cc speedmtr.cc)\
+           omnetapp.cc patmatch.cc platdep.cc seeds.cc slaveapp.cc speedmtr.cc)
+SIMSources    := \
          $(addprefix $(SPEC_BENCH_DIR)/src/libs/sim/,                          \
            carray.cc cexception.cc cmessage.cc cpar.cc ctypes.cc task.cc       \
            cchannel.cc cfsm.cc cmodule.cc cpsquare.cc cvarhist.cc util.cc      \
@@ -30,12 +34,24 @@
            chead.cc cnetmod.cc csimul.cc distrib.cc cdetect.cc chist.cc        \
            cobject.cc cstat.cc errmsg.cc cdispstr.cc cksplit.cc coutvect.cc    \
            cstruct.cc onstartup.cc cenum.cc cllist.cc cpacket.cc ctopo.cc      \
-           random.cc std/netpack.cc)                                           \
-           $(SPEC_BENCH_DIR)/src/libs/spec/spec_qsort.cc
+           random.cc std/netpack.cc)
+SPECSources   := \
+         $(SPEC_BENCH_DIR)/src/libs/spec/spec_qsort.cc
+
+Source := $(notdir $(TOPSources))                           \
+          $(addprefix cmdenv_,$(notdir $(CMDENVSources)))   \
+          $(addprefix envir_,$(notdir $(ENVIRSources)))     \
+          $(addprefix sim_,$(notdir $(SIMSources)))         \
+          $(addprefix spec_,$(notdir $(SPECSources)))
 
 CPPFLAGS += -DNDEBUG=1                            \
             -I$(SPEC_BENCH_DIR)/src/omnet_include \
-            -I$(SPEC_BENCH_DIR)/src/libs/envir
+            -I$(SPEC_BENCH_DIR)/src/libs/cmdenv   \
+            -I$(SPEC_BENCH_DIR)/src/libs/envir    \
+            -I$(SPEC_BENCH_DIR)/src/libs/sim      \
+            -I$(SPEC_BENCH_DIR)/src/libs/spec     \
+            -I$(SPEC_BENCH_DIR)/src               \
+            -I$(SPEC_BENCH_DIR)/src/include
 
 include ../../Makefile.spec2006
 
@@ -44,3 +60,30 @@
 
 LDFLAGS = -lstdc++ -lm
 LIBS    = -lstdc++ -lm
+
+##===----------------------------------------------------------------------===##
+# Copy the source files to the working directory. Some files may have
+# the same names but are in different directories, so we add a prefix
+# to the filenames to prevent overwriting files.
+##===----------------------------------------------------------------------===##
+
+$(notdir $(TOPSources)) : % : $(SPEC_BENCH_DIR)/src/%
+	cp $< $@
+$(addprefix cmdenv_,$(notdir $(CMDENVSources))) : cmdenv_% : \
+$(SPEC_BENCH_DIR)/src/libs/cmdenv/%
+	cp $< $@
+$(addprefix envir_,$(notdir $(ENVIRSources))) : envir_% : \
+$(SPEC_BENCH_DIR)/src/libs/envir/%
+	cp $< $@
+$(addprefix sim_,$(notdir $(SIMSources))) : sim_% : \
+$(SPEC_BENCH_DIR)/src/libs/sim/%
+	cp $< $@
+$(notdir $(SPECSources)) : % : $(SPEC_BENCH_DIR)/src/libs/spec/%
+	cp $< $@
+
+##===----------------------------------------------------------------------===##
+# Clean up all of the copied source files.
+##===----------------------------------------------------------------------===##
+
+clean::
+	$(RM) -f $(Source)





From isanbard at gmail.com  Thu Sep  7 18:17:37 2006
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 7 Sep 2006 18:17:37 -0500
Subject: [llvm-commits] CVS:
	llvm-test/External/SPEC/CINT2006/445.gobmk/Makefile
Message-ID: <200609072317.k87NHb0Y013676@zion.cs.uiuc.edu>



Changes in directory llvm-test/External/SPEC/CINT2006/445.gobmk:

Makefile updated: 1.2 -> 1.3
---
Log message:

Added support for multi-directories: go benchmark and omnetpp (whatever
that is)


---
Diffs of the changes:  (+55 -8)

 Makefile |   63 +++++++++++++++++++++++++++++++++++++++++++++++++++++++--------
 1 files changed, 55 insertions(+), 8 deletions(-)


Index: llvm-test/External/SPEC/CINT2006/445.gobmk/Makefile
diff -u llvm-test/External/SPEC/CINT2006/445.gobmk/Makefile:1.2 llvm-test/External/SPEC/CINT2006/445.gobmk/Makefile:1.3
--- llvm-test/External/SPEC/CINT2006/445.gobmk/Makefile:1.2	Fri Sep  1 20:31:50 2006
+++ llvm-test/External/SPEC/CINT2006/445.gobmk/Makefile	Thu Sep  7 18:17:18 2006
@@ -6,30 +6,48 @@
 
 LEVEL = ../../../..
 
-Source = $(addprefix $(SPEC_BENCH_DIR)/src/sgf/,                               \
-           sgf_utils.c sgftree.c sgfnode.c)                                    \
+include $(LEVEL)/Makefile.config
+
+SGFSources       := \
+         $(addprefix $(SPEC_BENCH_DIR)/src/sgf/,                               \
+           sgf_utils.c sgftree.c sgfnode.c)
+ENGINESources    := \
          $(addprefix $(SPEC_BENCH_DIR)/src/engine/,                            \
            aftermath.c board.c cache.c combination.c dragon.c filllib.c        \
            fuseki.c genmove.c hash.c influence.c interface.c matchpat.c        \
            move_reasons.c movelist.c optics.c owl.c printutils.c readconnect.c \
            reading.c score.c semeai.c sgfdecide.c sgffile.c shapes.c           \
            showbord.c utils.c value_moves.c worm.c globals.c persistent.c      \
-           handicap.c surround.c)                                              \
+           handicap.c surround.c)
+INTERFACESources := \
          $(addprefix $(SPEC_BENCH_DIR)/src/interface/,                         \
-           gtp.c main.c play_ascii.c play_gtp.c play_solo.c play_test.c)       \
+           gtp.c main.c play_ascii.c play_gtp.c play_solo.c play_test.c)
+PATTERNSSources  := \
          $(addprefix $(SPEC_BENCH_DIR)/src/patterns/,                          \
            connections.c dfa.c helpers.c transform.c owl_attackpat.c conn.c    \
            patterns.c apatterns.c dpatterns.c owl_vital_apat.c eyes.c          \
            influence.c barriers.c endgame.c aa_attackpat.c owl_defendpat.c     \
-           fusekipat.c fuseki9.c fuseki13.c fuseki19.c josekidb.c handipat.c)  \
+           fusekipat.c fuseki9.c fuseki13.c fuseki19.c josekidb.c handipat.c)
+UTILSSources     := \
          $(addprefix $(SPEC_BENCH_DIR)/src/utils/,                             \
            getopt.c getopt1.c gg_utils.c random.c)
 
-include ../../Makefile.spec2006
+Source := $(addprefix sgf_,$(notdir $(SGFSources)))             \
+          $(addprefix engine_,$(notdir $(ENGINESources)))       \
+          $(addprefix interface_,$(notdir $(INTERFACESources))) \
+          $(addprefix patterns_,$(notdir $(PATTERNSSources)))   \
+          $(addprefix utils_,$(notdir $(UTILSSources)))
 
-CPPFLAGS += -DHAVE_CONFIG_H
+CPPFLAGS += -DHAVE_CONFIG_H                   \
+            -I$(SPEC_BENCH_DIR)/src/sgf       \
+            -I$(SPEC_BENCH_DIR)/src/engine    \
+            -I$(SPEC_BENCH_DIR)/src/interface \
+            -I$(SPEC_BENCH_DIR)/src/patterns  \
+            -I$(SPEC_BENCH_DIR)/src/utils     \
+            -I$(SPEC_BENCH_DIR)/src           \
+            -I$(SPEC_BENCH_DIR)/src/include 
 
-## FIXME: Multiple *.tst files
+include ../../Makefile.spec2006
 
 ifeq ($(RUN_TYPE),test)
   RUN_OPTIONS     := --quiet --mode gtp
@@ -40,3 +58,32 @@
   STDIN_FILENAME  := arb.tst
   STDOUT_FILENAME := arb.out
 endif
+
+##===----------------------------------------------------------------------===##
+# Copy the source files to the working directory. Some files have the
+# same names but are in different directories, so we add a prefix to
+# the filenames to prevent overwriting files.
+##===----------------------------------------------------------------------===##
+
+$(addprefix sgf_,$(notdir $(SGFSources))) : sgf_% : \
+$(SPEC_BENCH_DIR)/src/sgf/%
+	cp $< $@
+$(addprefix engine_,$(notdir $(ENGINESources))) : engine_% : \
+$(SPEC_BENCH_DIR)/src/engine/%
+	cp $< $@
+$(addprefix interface_,$(notdir $(INTERFACESources))) : interface_% : \
+$(SPEC_BENCH_DIR)/src/interface/%
+	cp $< $@
+$(addprefix patterns_,$(notdir $(PATTERNSSources))) : patterns_% : \
+$(SPEC_BENCH_DIR)/src/patterns/%
+	cp $< $@
+$(addprefix utils_,$(notdir $(UTILSSources))) : utils_% : \
+$(SPEC_BENCH_DIR)/src/utils/%
+	cp $< $@
+
+##===----------------------------------------------------------------------===##
+# Clean up all of the copied source files.
+##===----------------------------------------------------------------------===##
+
+clean::
+	$(RM) -f $(Source)





From isanbard at gmail.com  Thu Sep  7 18:17:35 2006
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 7 Sep 2006 18:17:35 -0500
Subject: [llvm-commits] CVS:
	llvm-test/External/SPEC/CINT2006/400.perlbench/Makefile
Message-ID: <200609072317.k87NHZmX013669@zion.cs.uiuc.edu>



Changes in directory llvm-test/External/SPEC/CINT2006/400.perlbench:

Makefile updated: 1.4 -> 1.5
---
Log message:

Added support for multi-directories: go benchmark and omnetpp (whatever
that is)


---
Diffs of the changes:  (+4 -0)

 Makefile |    4 ++++
 1 files changed, 4 insertions(+)


Index: llvm-test/External/SPEC/CINT2006/400.perlbench/Makefile
diff -u llvm-test/External/SPEC/CINT2006/400.perlbench/Makefile:1.4 llvm-test/External/SPEC/CINT2006/400.perlbench/Makefile:1.5
--- llvm-test/External/SPEC/CINT2006/400.perlbench/Makefile:1.4	Wed Sep  6 19:08:49 2006
+++ llvm-test/External/SPEC/CINT2006/400.perlbench/Makefile	Thu Sep  7 18:17:18 2006
@@ -7,14 +7,18 @@
 
 LEVEL = ../../../..
 
+include $(LEVEL)/Makefile.config
+
 CPPFLAGS += -DPERL_CORE
 
+ifeq ($(OS),Darwin)
 ifeq ($(ARCH),PowerPC)
   CPPFLAGS += -DSPEC_CPU_MACOSX_PPC
 endif
 ifeq ($(ARCH),x86)
   CPPFLAGS += -DSPEC_CPU_MACOSX_IA32
 endif
+endif
 
 ifeq ($(ENDIAN),little)
   CPPFLAGS += -D__LITTLE_ENDIAN__





From dpatel at apple.com  Thu Sep  7 18:22:51 2006
From: dpatel at apple.com (Devang Patel)
Date: Thu, 7 Sep 2006 18:22:51 -0500
Subject: [llvm-commits] CVS: llvm/lib/Analysis/PostDominators.cpp
Message-ID: <200609072322.k87NMptF013770@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Analysis:

PostDominators.cpp updated: 1.58 -> 1.59
---
Log message:

Use iterative do-while loop instead of recursive DFSPass calls to
reduce amount of stack space used at runtime.


---
Diffs of the changes:  (+29 -16)

 PostDominators.cpp |   45 +++++++++++++++++++++++++++++----------------
 1 files changed, 29 insertions(+), 16 deletions(-)


Index: llvm/lib/Analysis/PostDominators.cpp
diff -u llvm/lib/Analysis/PostDominators.cpp:1.58 llvm/lib/Analysis/PostDominators.cpp:1.59
--- llvm/lib/Analysis/PostDominators.cpp:1.58	Sun Aug 27 17:30:17 2006
+++ llvm/lib/Analysis/PostDominators.cpp	Thu Sep  7 18:22:37 2006
@@ -28,23 +28,36 @@
 
 unsigned ImmediatePostDominators::DFSPass(BasicBlock *V, InfoRec &VInfo,
                                           unsigned N) {
-  VInfo.Semi = ++N;
-  VInfo.Label = V;
-  
-  Vertex.push_back(V);        // Vertex[n] = V;
-                              //Info[V].Ancestor = 0;     // Ancestor[n] = 0
-                              //Child[V] = 0;             // Child[v] = 0
-  VInfo.Size = 1;             // Size[v] = 1
-  
-  // For PostDominators, we want to walk predecessors rather than successors
-  // as we do in forward Dominators.
-  for (pred_iterator PI = pred_begin(V), PE = pred_end(V); PI != PE; ++PI) {
-    InfoRec &SuccVInfo = Info[*PI];
-    if (SuccVInfo.Semi == 0) {
-      SuccVInfo.Parent = V;
-      N = DFSPass(*PI, SuccVInfo, N);
+
+  std::vector<std::pair<BasicBlock *, InfoRec *> > workStack;
+  workStack.push_back(std::make_pair(V, &VInfo));
+
+  do {
+    BasicBlock *currentBB = workStack.back().first; 
+    InfoRec *currentVInfo = workStack.back().second;
+    workStack.pop_back();
+
+    currentVInfo->Semi = ++N;
+    currentVInfo->Label = currentBB;
+
+    Vertex.push_back(currentBB);  // Vertex[n] = current;
+                                  // Info[currentBB].Ancestor = 0;     
+                                  // Ancestor[n] = 0
+                                  // Child[currentBB] = 0;
+    currentVInfo->Size = 1;       // Size[currentBB] = 1
+
+    // For PostDominators, we want to walk predecessors rather than successors
+    // as we do in forward Dominators.
+    for (pred_iterator PI = pred_begin(currentBB), PE = pred_end(currentBB); 
+	 PI != PE; ++PI) {
+      InfoRec &SuccVInfo = Info[*PI];
+      if (SuccVInfo.Semi == 0) {
+	SuccVInfo.Parent = currentBB;
+
+	workStack.push_back(std::make_pair(*PI, &SuccVInfo));	
+      }
     }
-  }
+  } while (!workStack.empty());
   return N;
 }
 





From dpatel at apple.com  Thu Sep  7 18:29:33 2006
From: dpatel at apple.com (Devang Patel)
Date: Thu, 7 Sep 2006 18:29:33 -0500
Subject: [llvm-commits] CVS: llvm/lib/Analysis/PostDominators.cpp
Message-ID: <200609072329.k87NTXOX013871@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Analysis:

PostDominators.cpp updated: 1.59 -> 1.60
---
Log message:

Untabify.


---
Diffs of the changes:  (+3 -3)

 PostDominators.cpp |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)


Index: llvm/lib/Analysis/PostDominators.cpp
diff -u llvm/lib/Analysis/PostDominators.cpp:1.59 llvm/lib/Analysis/PostDominators.cpp:1.60
--- llvm/lib/Analysis/PostDominators.cpp:1.59	Thu Sep  7 18:22:37 2006
+++ llvm/lib/Analysis/PostDominators.cpp	Thu Sep  7 18:29:19 2006
@@ -49,12 +49,12 @@
     // For PostDominators, we want to walk predecessors rather than successors
     // as we do in forward Dominators.
     for (pred_iterator PI = pred_begin(currentBB), PE = pred_end(currentBB); 
-	 PI != PE; ++PI) {
+         PI != PE; ++PI) {
       InfoRec &SuccVInfo = Info[*PI];
       if (SuccVInfo.Semi == 0) {
-	SuccVInfo.Parent = currentBB;
+        SuccVInfo.Parent = currentBB;
 
-	workStack.push_back(std::make_pair(*PI, &SuccVInfo));	
+        workStack.push_back(std::make_pair(*PI, &SuccVInfo));   
       }
     }
   } while (!workStack.empty());





From jlaskey at apple.com  Thu Sep  7 18:39:50 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Thu, 7 Sep 2006 18:39:50 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/IA64/IA64TargetMachine.cpp
	IA64TargetMachine.h
Message-ID: <200609072339.k87NdoS7014071@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/IA64:

IA64TargetMachine.cpp updated: 1.20 -> 1.21
IA64TargetMachine.h updated: 1.14 -> 1.15
---
Log message:

1. Remove condition on delete.

2. Protect and outline createTargetAsmInfo.

3. Misc. kruft.


---
Diffs of the changes:  (+9 -5)

 IA64TargetMachine.cpp |    5 +++++
 IA64TargetMachine.h   |    9 ++++-----
 2 files changed, 9 insertions(+), 5 deletions(-)


Index: llvm/lib/Target/IA64/IA64TargetMachine.cpp
diff -u llvm/lib/Target/IA64/IA64TargetMachine.cpp:1.20 llvm/lib/Target/IA64/IA64TargetMachine.cpp:1.21
--- llvm/lib/Target/IA64/IA64TargetMachine.cpp:1.20	Sun Sep  3 23:14:57 2006
+++ llvm/lib/Target/IA64/IA64TargetMachine.cpp	Thu Sep  7 18:39:26 2006
@@ -11,6 +11,7 @@
 //
 //===----------------------------------------------------------------------===//
 
+#include "IA64TargetAsmInfo.h"
 #include "IA64TargetMachine.h"
 #include "IA64.h"
 #include "llvm/Module.h"
@@ -29,6 +30,10 @@
   RegisterTarget<IA64TargetMachine> X("ia64", "  IA-64 (Itanium)");
 }
 
+const TargetAsmInfo *IA64TargetMachine::createTargetAsmInfo() const {
+  return new IA64TargetAsmInfo(*this);
+}
+
 unsigned IA64TargetMachine::getModuleMatchQuality(const Module &M) {
   // we match [iI][aA]*64
   bool seenIA64=false;


Index: llvm/lib/Target/IA64/IA64TargetMachine.h
diff -u llvm/lib/Target/IA64/IA64TargetMachine.h:1.14 llvm/lib/Target/IA64/IA64TargetMachine.h:1.15
--- llvm/lib/Target/IA64/IA64TargetMachine.h:1.14	Thu Sep  7 17:06:40 2006
+++ llvm/lib/Target/IA64/IA64TargetMachine.h	Thu Sep  7 18:39:26 2006
@@ -19,7 +19,6 @@
 #include "llvm/Target/TargetFrameInfo.h"
 #include "IA64InstrInfo.h"
 #include "IA64ISelLowering.h"
-#include "IA64TargetAsmInfo.h"
 
 namespace llvm {
 
@@ -29,6 +28,10 @@
   TargetFrameInfo    FrameInfo;
   //IA64JITInfo      JITInfo;
   IA64TargetLowering TLInfo;
+  
+protected:
+  virtual const TargetAsmInfo *createTargetAsmInfo() const;
+
 public:
   IA64TargetMachine(const Module &M, const std::string &FS);
 
@@ -42,10 +45,6 @@
   }
   virtual const TargetData       *getTargetData() const { return &DataLayout; }
   
-  virtual const TargetAsmInfo *createTargetAsmInfo() const {
-    return static_cast<const TargetAsmInfo *>(new IA64TargetAsmInfo(*this));
-  }
-
   static unsigned getModuleMatchQuality(const Module &M);
 
   // Pass Pipeline Configuration





From jlaskey at apple.com  Thu Sep  7 18:39:50 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Thu, 7 Sep 2006 18:39:50 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcTargetMachine.cpp
	SparcTargetMachine.h
Message-ID: <200609072339.k87Ndo78014076@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Sparc:

SparcTargetMachine.cpp updated: 1.50 -> 1.51
SparcTargetMachine.h updated: 1.16 -> 1.17
---
Log message:

1. Remove condition on delete.

2. Protect and outline createTargetAsmInfo.

3. Misc. kruft.


---
Diffs of the changes:  (+9 -5)

 SparcTargetMachine.cpp |    5 +++++
 SparcTargetMachine.h   |    9 ++++-----
 2 files changed, 9 insertions(+), 5 deletions(-)


Index: llvm/lib/Target/Sparc/SparcTargetMachine.cpp
diff -u llvm/lib/Target/Sparc/SparcTargetMachine.cpp:1.50 llvm/lib/Target/Sparc/SparcTargetMachine.cpp:1.51
--- llvm/lib/Target/Sparc/SparcTargetMachine.cpp:1.50	Sun Sep  3 23:14:57 2006
+++ llvm/lib/Target/Sparc/SparcTargetMachine.cpp	Thu Sep  7 18:39:26 2006
@@ -10,6 +10,7 @@
 //
 //===----------------------------------------------------------------------===//
 
+#include "SparcTargetAsmInfo.h"
 #include "SparcTargetMachine.h"
 #include "Sparc.h"
 #include "llvm/Module.h"
@@ -23,6 +24,10 @@
   RegisterTarget<SparcTargetMachine> X("sparc", "  SPARC");
 }
 
+const TargetAsmInfo *SparcTargetMachine::createTargetAsmInfo() const {
+  return new SparcTargetAsmInfo(*this);
+}
+
 /// SparcTargetMachine ctor - Create an ILP32 architecture model
 ///
 SparcTargetMachine::SparcTargetMachine(const Module &M, const std::string &FS)


Index: llvm/lib/Target/Sparc/SparcTargetMachine.h
diff -u llvm/lib/Target/Sparc/SparcTargetMachine.h:1.16 llvm/lib/Target/Sparc/SparcTargetMachine.h:1.17
--- llvm/lib/Target/Sparc/SparcTargetMachine.h:1.16	Thu Sep  7 17:06:40 2006
+++ llvm/lib/Target/Sparc/SparcTargetMachine.h	Thu Sep  7 18:39:26 2006
@@ -19,7 +19,6 @@
 #include "llvm/Target/TargetFrameInfo.h"
 #include "SparcInstrInfo.h"
 #include "SparcSubtarget.h"
-#include "SparcTargetAsmInfo.h"
 
 namespace llvm {
 
@@ -30,6 +29,10 @@
   SparcSubtarget Subtarget;
   SparcInstrInfo InstrInfo;
   TargetFrameInfo FrameInfo;
+  
+protected:
+  virtual const TargetAsmInfo *createTargetAsmInfo() const;
+  
 public:
   SparcTargetMachine(const Module &M, const std::string &FS);
 
@@ -42,10 +45,6 @@
   virtual const TargetData       *getTargetData() const { return &DataLayout; }
   static unsigned getModuleMatchQuality(const Module &M);
 
-  virtual const TargetAsmInfo *createTargetAsmInfo() const {
-    return static_cast<const TargetAsmInfo *>(new SparcTargetAsmInfo(*this));
-  }
-  
   // Pass Pipeline Configuration
   virtual bool addInstSelector(FunctionPassManager &PM, bool Fast);
   virtual bool addPreEmitPass(FunctionPassManager &PM, bool Fast);





From jlaskey at apple.com  Thu Sep  7 18:39:45 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Thu, 7 Sep 2006 18:39:45 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/ARM/ARMTargetMachine.cpp
	ARMTargetMachine.h
Message-ID: <200609072339.k87NdjQG014063@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/ARM:

ARMTargetMachine.cpp updated: 1.8 -> 1.9
ARMTargetMachine.h updated: 1.4 -> 1.5
---
Log message:

1. Remove condition on delete.

2. Protect and outline createTargetAsmInfo.

3. Misc. kruft.


---
Diffs of the changes:  (+11 -5)

 ARMTargetMachine.cpp |    7 +++++++
 ARMTargetMachine.h   |    9 ++++-----
 2 files changed, 11 insertions(+), 5 deletions(-)


Index: llvm/lib/Target/ARM/ARMTargetMachine.cpp
diff -u llvm/lib/Target/ARM/ARMTargetMachine.cpp:1.8 llvm/lib/Target/ARM/ARMTargetMachine.cpp:1.9
--- llvm/lib/Target/ARM/ARMTargetMachine.cpp:1.8	Sun Sep  3 23:14:57 2006
+++ llvm/lib/Target/ARM/ARMTargetMachine.cpp	Thu Sep  7 18:39:26 2006
@@ -11,6 +11,7 @@
 //
 //===----------------------------------------------------------------------===//
 
+#include "ARMTargetAsmInfo.h"
 #include "ARMTargetMachine.h"
 #include "ARMFrameInfo.h"
 #include "ARM.h"
@@ -24,6 +25,12 @@
   RegisterTarget<ARMTargetMachine> X("arm", "  ARM");
 }
 
+
+const TargetAsmInfo *ARMTargetMachine::createTargetAsmInfo() const {
+  return new ARMTargetAsmInfo(*this);
+}
+
+
 /// TargetMachine ctor - Create an ILP32 architecture model
 ///
 ARMTargetMachine::ARMTargetMachine(const Module &M, const std::string &FS)


Index: llvm/lib/Target/ARM/ARMTargetMachine.h
diff -u llvm/lib/Target/ARM/ARMTargetMachine.h:1.4 llvm/lib/Target/ARM/ARMTargetMachine.h:1.5
--- llvm/lib/Target/ARM/ARMTargetMachine.h:1.4	Thu Sep  7 17:06:40 2006
+++ llvm/lib/Target/ARM/ARMTargetMachine.h	Thu Sep  7 18:39:26 2006
@@ -20,7 +20,6 @@
 #include "llvm/Target/TargetFrameInfo.h"
 #include "ARMInstrInfo.h"
 #include "ARMFrameInfo.h"
-#include "ARMTargetAsmInfo.h"
 
 namespace llvm {
 
@@ -30,6 +29,10 @@
   const TargetData DataLayout;       // Calculates type size & alignment
   ARMInstrInfo InstrInfo;
   ARMFrameInfo FrameInfo;
+  
+protected:
+  virtual const TargetAsmInfo *createTargetAsmInfo() const;
+
 public:
   ARMTargetMachine(const Module &M, const std::string &FS);
 
@@ -41,10 +44,6 @@
   virtual const TargetData       *getTargetData() const { return &DataLayout; }
   static unsigned getModuleMatchQuality(const Module &M);
 
-  virtual const TargetAsmInfo *createTargetAsmInfo() const {
-    return static_cast<const TargetAsmInfo *>(new ARMTargetAsmInfo(*this));
-  }
-
   // Pass Pipeline Configuration
   virtual bool addInstSelector(FunctionPassManager &PM, bool Fast);
   virtual bool addAssemblyEmitter(FunctionPassManager &PM, bool Fast, 





From jlaskey at apple.com  Thu Sep  7 18:39:52 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Thu, 7 Sep 2006 18:39:52 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetMachine.h
Message-ID: <200609072339.k87NdqVq014104@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/Target:

TargetMachine.h updated: 1.70 -> 1.71
---
Log message:

1. Remove condition on delete.

2. Protect and outline createTargetAsmInfo.

3. Misc. kruft.


---
Diffs of the changes:  (+4 -4)

 TargetMachine.h |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)


Index: llvm/include/llvm/Target/TargetMachine.h
diff -u llvm/include/llvm/Target/TargetMachine.h:1.70 llvm/include/llvm/Target/TargetMachine.h:1.71
--- llvm/include/llvm/Target/TargetMachine.h:1.70	Thu Sep  7 17:06:40 2006
+++ llvm/include/llvm/Target/TargetMachine.h	Thu Sep  7 18:39:26 2006
@@ -76,6 +76,10 @@
   ///
   mutable const TargetAsmInfo *AsmInfo;
   
+  /// createTargetAsmInfo - Create a new instance of target specific asm
+  /// information.
+  virtual const TargetAsmInfo *createTargetAsmInfo() const { return NULL; }
+
 public:
   virtual ~TargetMachine();
 
@@ -111,10 +115,6 @@
     return AsmInfo;
   }
   
-  /// createTargetAsmInfo - Create a new instance of target specific asm
-  /// information.
-  virtual const TargetAsmInfo *createTargetAsmInfo() const { return NULL; }
-
   /// getSubtarget - This method returns a pointer to the specified type of
   /// TargetSubtarget.  In debug builds, it verifies that the object being
   /// returned is of the correct type.





From jlaskey at apple.com  Thu Sep  7 18:39:51 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Thu, 7 Sep 2006 18:39:51 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
	PPCTargetMachine.h
Message-ID: <200609072339.k87NdplY014099@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCTargetMachine.cpp updated: 1.104 -> 1.105
PPCTargetMachine.h updated: 1.24 -> 1.25
---
Log message:

1. Remove condition on delete.

2. Protect and outline createTargetAsmInfo.

3. Misc. kruft.


---
Diffs of the changes:  (+9 -5)

 PPCTargetMachine.cpp |    5 +++++
 PPCTargetMachine.h   |    9 ++++-----
 2 files changed, 9 insertions(+), 5 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
diff -u llvm/lib/Target/PowerPC/PPCTargetMachine.cpp:1.104 llvm/lib/Target/PowerPC/PPCTargetMachine.cpp:1.105
--- llvm/lib/Target/PowerPC/PPCTargetMachine.cpp:1.104	Wed Sep  6 13:34:40 2006
+++ llvm/lib/Target/PowerPC/PPCTargetMachine.cpp	Thu Sep  7 18:39:26 2006
@@ -12,6 +12,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "PPC.h"
+#include "PPCTargetAsmInfo.h"
 #include "PPCTargetMachine.h"
 #include "llvm/Module.h"
 #include "llvm/PassManager.h"
@@ -26,6 +27,10 @@
   Y("ppc64", "  PowerPC 64");
 }
 
+const TargetAsmInfo *PPCTargetMachine::createTargetAsmInfo() const {
+  return new DarwinTargetAsmInfo(*this);
+}
+
 unsigned PPC32TargetMachine::getJITMatchQuality() {
 #if defined(__POWERPC__) || defined (__ppc__) || defined(_POWER)
   if (sizeof(void*) == 4)


Index: llvm/lib/Target/PowerPC/PPCTargetMachine.h
diff -u llvm/lib/Target/PowerPC/PPCTargetMachine.h:1.24 llvm/lib/Target/PowerPC/PPCTargetMachine.h:1.25
--- llvm/lib/Target/PowerPC/PPCTargetMachine.h:1.24	Thu Sep  7 17:06:40 2006
+++ llvm/lib/Target/PowerPC/PPCTargetMachine.h	Thu Sep  7 18:39:26 2006
@@ -19,7 +19,6 @@
 #include "PPCJITInfo.h"
 #include "PPCInstrInfo.h"
 #include "PPCISelLowering.h"
-#include "PPCTargetAsmInfo.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetData.h"
 
@@ -37,6 +36,10 @@
   PPCJITInfo          JITInfo;
   PPCTargetLowering   TLInfo;
   InstrItineraryData  InstrItins;
+  
+protected:
+  virtual const TargetAsmInfo *createTargetAsmInfo() const;
+  
 public:
   PPCTargetMachine(const Module &M, const std::string &FS, bool is64Bit);
 
@@ -56,10 +59,6 @@
     return InstrItins;
   }
   
-  virtual const TargetAsmInfo *createTargetAsmInfo() const {
-    return static_cast<const TargetAsmInfo *>(new DarwinTargetAsmInfo(*this));
-  }
-  
   // Pass Pipeline Configuration
   virtual bool addInstSelector(FunctionPassManager &PM, bool Fast);
   virtual bool addPreEmitPass(FunctionPassManager &PM, bool Fast);





From jlaskey at apple.com  Thu Sep  7 18:39:52 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Thu, 7 Sep 2006 18:39:52 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86TargetMachine.cpp
	X86TargetMachine.h
Message-ID: <200609072339.k87NdqCt014111@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86TargetMachine.cpp updated: 1.125 -> 1.126
X86TargetMachine.h updated: 1.39 -> 1.40
---
Log message:

1. Remove condition on delete.

2. Protect and outline createTargetAsmInfo.

3. Misc. kruft.


---
Diffs of the changes:  (+9 -5)

 X86TargetMachine.cpp |    5 +++++
 X86TargetMachine.h   |    9 ++++-----
 2 files changed, 9 insertions(+), 5 deletions(-)


Index: llvm/lib/Target/X86/X86TargetMachine.cpp
diff -u llvm/lib/Target/X86/X86TargetMachine.cpp:1.125 llvm/lib/Target/X86/X86TargetMachine.cpp:1.126
--- llvm/lib/Target/X86/X86TargetMachine.cpp:1.125	Mon Sep  4 13:48:41 2006
+++ llvm/lib/Target/X86/X86TargetMachine.cpp	Thu Sep  7 18:39:26 2006
@@ -11,6 +11,7 @@
 //
 //===----------------------------------------------------------------------===//
 
+#include "X86TargetAsmInfo.h"
 #include "X86TargetMachine.h"
 #include "X86.h"
 #include "llvm/Module.h"
@@ -35,6 +36,10 @@
   RegisterTarget<X86TargetMachine> X("x86", "  IA-32 (Pentium and above)");
 }
 
+const TargetAsmInfo *X86TargetMachine::createTargetAsmInfo() const {
+  return new X86TargetAsmInfo(*this);
+}
+
 unsigned X86TargetMachine::getJITMatchQuality() {
 #if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
   return 10;


Index: llvm/lib/Target/X86/X86TargetMachine.h
diff -u llvm/lib/Target/X86/X86TargetMachine.h:1.39 llvm/lib/Target/X86/X86TargetMachine.h:1.40
--- llvm/lib/Target/X86/X86TargetMachine.h:1.39	Thu Sep  7 17:06:40 2006
+++ llvm/lib/Target/X86/X86TargetMachine.h	Thu Sep  7 18:39:26 2006
@@ -21,7 +21,6 @@
 #include "X86InstrInfo.h"
 #include "X86JITInfo.h"
 #include "X86Subtarget.h"
-#include "X86TargetAsmInfo.h"
 #include "X86ISelLowering.h"
 
 namespace llvm {
@@ -33,6 +32,10 @@
   X86InstrInfo      InstrInfo;
   X86JITInfo        JITInfo;
   X86TargetLowering TLInfo;
+
+protected:
+  virtual const TargetAsmInfo *createTargetAsmInfo() const;
+  
 public:
   X86TargetMachine(const Module &M, const std::string &FS);
 
@@ -51,10 +54,6 @@
   static unsigned getModuleMatchQuality(const Module &M);
   static unsigned getJITMatchQuality();
   
-  virtual const TargetAsmInfo *createTargetAsmInfo() const {
-    return static_cast<const TargetAsmInfo *>(new X86TargetAsmInfo(*this));
-  }
-  
   // Set up the pass pipeline.
   virtual bool addInstSelector(FunctionPassManager &PM, bool Fast);  
   virtual bool addPostRegAlloc(FunctionPassManager &PM, bool Fast);





From jlaskey at apple.com  Thu Sep  7 18:39:50 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Thu, 7 Sep 2006 18:39:50 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaTargetMachine.cpp
	AlphaTargetMachine.h
Message-ID: <200609072339.k87Ndog8014085@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/Alpha:

AlphaTargetMachine.cpp updated: 1.30 -> 1.31
AlphaTargetMachine.h updated: 1.16 -> 1.17
---
Log message:

1. Remove condition on delete.

2. Protect and outline createTargetAsmInfo.

3. Misc. kruft.


---
Diffs of the changes:  (+9 -11)

 AlphaTargetMachine.cpp |    8 ++++++--
 AlphaTargetMachine.h   |   12 +++---------
 2 files changed, 9 insertions(+), 11 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaTargetMachine.cpp
diff -u llvm/lib/Target/Alpha/AlphaTargetMachine.cpp:1.30 llvm/lib/Target/Alpha/AlphaTargetMachine.cpp:1.31
--- llvm/lib/Target/Alpha/AlphaTargetMachine.cpp:1.30	Thu Sep  7 17:06:40 2006
+++ llvm/lib/Target/Alpha/AlphaTargetMachine.cpp	Thu Sep  7 18:39:26 2006
@@ -12,6 +12,7 @@
 
 #include "Alpha.h"
 #include "AlphaJITInfo.h"
+#include "AlphaTargetAsmInfo.h"
 #include "AlphaTargetMachine.h"
 #include "llvm/Module.h"
 #include "llvm/PassManager.h"
@@ -24,6 +25,10 @@
   RegisterTarget<AlphaTargetMachine> X("alpha", "  Alpha (incomplete)");
 }
 
+const TargetAsmInfo *AlphaTargetMachine::createTargetAsmInfo() const {
+  return new AlphaTargetAsmInfo(*this);
+}
+
 unsigned AlphaTargetMachine::getModuleMatchQuality(const Module &M) {
   // We strongly match "alpha*".
   std::string TT = M.getTargetTriple();
@@ -53,8 +58,7 @@
   : DataLayout("e"),
     FrameInfo(TargetFrameInfo::StackGrowsDown, 16, 0),
     JITInfo(*this),
-    Subtarget(M, FS),
-    AsmInfo(NULL) {
+    Subtarget(M, FS) {
 }
 
 


Index: llvm/lib/Target/Alpha/AlphaTargetMachine.h
diff -u llvm/lib/Target/Alpha/AlphaTargetMachine.h:1.16 llvm/lib/Target/Alpha/AlphaTargetMachine.h:1.17
--- llvm/lib/Target/Alpha/AlphaTargetMachine.h:1.16	Thu Sep  7 17:06:40 2006
+++ llvm/lib/Target/Alpha/AlphaTargetMachine.h	Thu Sep  7 18:39:26 2006
@@ -20,7 +20,6 @@
 #include "AlphaInstrInfo.h"
 #include "AlphaJITInfo.h"
 #include "AlphaSubtarget.h"
-#include "AlphaTargetAsmInfo.h"
 
 namespace llvm {
 
@@ -32,13 +31,12 @@
   TargetFrameInfo FrameInfo;
   AlphaJITInfo JITInfo;
   AlphaSubtarget Subtarget;
-  AlphaTargetAsmInfo *AsmInfo;
+  
+protected:
+  virtual const TargetAsmInfo *createTargetAsmInfo() const;
   
 public:
   AlphaTargetMachine(const Module &M, const std::string &FS);
-  ~AlphaTargetMachine() {
-    if (AsmInfo) delete AsmInfo;
-  }
 
   virtual const AlphaInstrInfo *getInstrInfo() const { return &InstrInfo; }
   virtual const TargetFrameInfo  *getFrameInfo() const { return &FrameInfo; }
@@ -51,10 +49,6 @@
     return &JITInfo;
   }
 
-  virtual const TargetAsmInfo *createTargetAsmInfo() const {
-    return static_cast<const TargetAsmInfo *>(new AlphaTargetAsmInfo(*this));
-  }
-
   static unsigned getJITMatchQuality();
   static unsigned getModuleMatchQuality(const Module &M);
   





From jlaskey at apple.com  Thu Sep  7 18:39:50 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Thu, 7 Sep 2006 18:39:50 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/TargetMachine.cpp
Message-ID: <200609072339.k87Ndo83014088@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target:

TargetMachine.cpp updated: 1.54 -> 1.55
---
Log message:

1. Remove condition on delete.

2. Protect and outline createTargetAsmInfo.

3. Misc. kruft.


---
Diffs of the changes:  (+1 -1)

 TargetMachine.cpp |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/TargetMachine.cpp
diff -u llvm/lib/Target/TargetMachine.cpp:1.54 llvm/lib/Target/TargetMachine.cpp:1.55
--- llvm/lib/Target/TargetMachine.cpp:1.54	Thu Sep  7 17:06:40 2006
+++ llvm/lib/Target/TargetMachine.cpp	Thu Sep  7 18:39:26 2006
@@ -96,7 +96,7 @@
 //
 
 TargetMachine::~TargetMachine() {
-  if (AsmInfo) delete AsmInfo;
+  delete AsmInfo;
 }
 
 /// getRelocationModel - Returns the code generation relocation model. The





From isanbard at gmail.com  Thu Sep  7 19:59:31 2006
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 7 Sep 2006 19:59:31 -0500
Subject: [llvm-commits] CVS:
	llvm-test/External/SPEC/CFP2006/436.cactusADM/Makefile
Message-ID: <200609080059.k880xVbP015428@zion.cs.uiuc.edu>



Changes in directory llvm-test/External/SPEC/CFP2006/436.cactusADM:

Makefile updated: 1.2 -> 1.3
---
Log message:

Added support for SPEC benchmarks with mutiple directories. Stolen from the
POVRay way of doing things.


---
Diffs of the changes:  (+124 -17)

 Makefile |  141 +++++++++++++++++++++++++++++++++++++++++++++++++++++++--------
 1 files changed, 124 insertions(+), 17 deletions(-)


Index: llvm-test/External/SPEC/CFP2006/436.cactusADM/Makefile
diff -u llvm-test/External/SPEC/CFP2006/436.cactusADM/Makefile:1.2 llvm-test/External/SPEC/CFP2006/436.cactusADM/Makefile:1.3
--- llvm-test/External/SPEC/CFP2006/436.cactusADM/Makefile:1.2	Wed Sep  6 15:41:12 2006
+++ llvm-test/External/SPEC/CFP2006/436.cactusADM/Makefile	Thu Sep  7 19:59:14 2006
@@ -6,14 +6,18 @@
 
 LEVEL = ../../../..
 
-Source = PreLoop.F StaggeredLeapfrog1a.F StaggeredLeapfrog1a_TS.F              \
-         StaggeredLeapfrog2.F planewaves.F teukwaves.F datestamp.c regex.c     \
+TOPSources            := \
+         PreLoop.F StaggeredLeapfrog1a.F StaggeredLeapfrog1a_TS.F              \
+         StaggeredLeapfrog2.F planewaves.F teukwaves.F datestamp.c regex.c
+PUGHSources           := \
          $(addprefix $(SPEC_BENCH_DIR)/src/PUGH/,                              \
            GHExtension.c FinishReceiveGA.c Startup.c Evolve.c Storage.c        \
            SetupGroup.c PostSendGA.c SetupPGH.c SetupPGV.c LoadAware.c Comm.c  \
-           cctk_ThornBindings.c Overloadables.c PughUtils.c PostReceiveGA.c)   \
+           cctk_ThornBindings.c Overloadables.c PughUtils.c PostReceiveGA.c)
+TIMESources           := \
          $(addprefix $(SPEC_BENCH_DIR)/src/Time/,                              \
-           Courant.c Initialise.c cctk_ThornBindings.c Given.c Simple.c)       \
+           Courant.c Initialise.c cctk_ThornBindings.c Given.c Simple.c)
+CACTUSSources         := \
          $(addprefix $(SPEC_BENCH_DIR)/src/Cactus/,                            \
            ScheduleTraverse.c Groups.c Dummies.c File.c CactusDefaultEvolve.c  \
            BinaryTree.c Hash.c Malloc.c CactusTimers.c CallStartupFunctions.c  \
@@ -32,13 +36,17 @@
            SetParams.c cctk_ThornBindings.c OverloadComm.c Names.c             \
            InitialiseDataStructures.c StringList.c DefaultTimers.c             \
            StoreNamedData.c ScheduleSorter.c Complex.c OverloadMain.c          \
-           Traverse.c SKBinTree.c snprintf.c)                                  \
+           Traverse.c SKBinTree.c snprintf.c)
+IOUTILSources         := \
          $(addprefix $(SPEC_BENCH_DIR)/src/IOUtil/,                            \
            CheckpointRecovery.c Utils.c AdvertisedFiles.c Startup.c            \
-           cctk_ThornBindings.c)                                               \
-         $(SPEC_BENCH_DIR)/src/IDLinearWaves/cctk_ThornBindings.c              \
+           cctk_ThornBindings.c)
+IDLINEARWAVESSources  := \
+         $(SPEC_BENCH_DIR)/src/IDLinearWaves/cctk_ThornBindings.c
+BENCHADMSRCSources    := \
          $(addprefix $(SPEC_BENCH_DIR)/src/BenchADMsrc/,                       \
-           Startup.c ParamCheck.c cctk_ThornBindings.c)                        \
+           Startup.c ParamCheck.c cctk_ThornBindings.c)
+CACTUSBINDINGSSources := \
          $(addprefix $(SPEC_BENCH_DIR)/src/CactusBindings/,                    \
            ParameterRecoveryEinstein.c ParameterRecoveryCactus.c               \
            TIME_private.c OverloadThorns.c Cactus.c PUGH_Register.c            \
@@ -80,36 +88,135 @@
            ImplementationBindings.c DRIVER_restricted.c                        \
            IOUtil_FortranWrapper.c ScheduleCartGrid3D.c                        \
            FortranThornFunctions.c GRID_restricted.c                           \
-           ParameterRecoveryBoundary.c)                                        \
+           ParameterRecoveryBoundary.c)
+CARTGRID3DSources     := \
          $(addprefix $(SPEC_BENCH_DIR)/src/CartGrid3D/,                        \
            SymmetryWrappers.c GHExtension.c DecodeSymParameters.c              \
            SetSymmetry.c Startup.c CartGrid3D.c Symmetry.c ParamCheck.c        \
-           cctk_ThornBindings.c)                                               \
+           cctk_ThornBindings.c)
+EINSTEINSources       := \
          $(addprefix $(SPEC_BENCH_DIR)/src/Einstein/,                          \
            Courant.c InitialEinstein.c MaskInit.c Slicing.c InitialFlat.c      \
            carttosphere.c InitSymBound.c LapseInits.c cctk_ThornBindings.c     \
-           ShiftInits.c evaltrK.c ConfPhys.c)                                  \
+           ShiftInits.c evaltrK.c ConfPhys.c)
+PUGHREDUCESources     := \
          $(addprefix $(SPEC_BENCH_DIR)/src/PUGHReduce/,                        \
            ReductionNormInf.c ReductionMax.c ReductionMin.c ReductionSum.c     \
            Startup.c Reduction.c ReductionNorm1.c ReductionNorm2.c             \
-           cctk_ThornBindings.c)                                               \
+           cctk_ThornBindings.c)
+BOUNDARYSources       := \
          $(addprefix $(SPEC_BENCH_DIR)/src/Boundary/,                          \
            FlatBoundary.c ScalarBoundary.c RadiationBoundary.c RobinBoundary.c \
-           CopyBoundary.c cctk_ThornBindings.c)                                \
+           CopyBoundary.c cctk_ThornBindings.c)
+PUGHSLABSources       := \
          $(addprefix $(SPEC_BENCH_DIR)/src/PUGHSlab/,                          \
            DatatypeConversion.c GetHyperslab.c Mapping.c Hyperslab.c           \
-           cctk_ThornBindings.c NewHyperslab.c)                                \
+           cctk_ThornBindings.c NewHyperslab.c)
+IOASCIISources        := \
          $(addprefix $(SPEC_BENCH_DIR)/src/IOASCII/,                           \
            Output1D.c Output2D.c Output3D.c Startup.c cctk_ThornBindings.c     \
-           ChooseOutput.c Write1D.c Write2D.c Write3D.c)                       \
+           ChooseOutput.c Write1D.c Write2D.c Write3D.c)
+IOBASICSources        := \
          $(addprefix $(SPEC_BENCH_DIR)/src/IOBasic/,                           \
            WriteScalar.c OutputScalar.c OutputInfo.c Startup.c WriteInfo.c     \
            cctk_ThornBindings.c)
 
+Source := $(notdir $(TOPSources))                                 \
+          $(addprefix pugh_,$(notdir $(PUGHSources)))             \
+          $(addprefix time_,$(notdir $(TIMESources)))             \
+          $(addprefix cactus_,$(notdir $(CACTUSSources)))         \
+          $(addprefix ioutil_,$(notdir $(IOUTILSources)))         \
+          $(addprefix idlw_,$(notdir $(IDLINEARWAVESSources)))    \
+          $(addprefix badmsrc_,$(notdir $(BENCHADMSRCSources)))   \
+          $(addprefix cbnds_,$(notdir $(CACTUSBINDINGSSources)))  \
+          $(addprefix cg3d_,$(notdir $(CARTGRID3DSources)))       \
+          $(addprefix einstein_,$(notdir $(EINSTEINSources)))     \
+          $(addprefix pughreduce_,$(notdir $(PUGHREDUCESources))) \
+          $(addprefix boundary_,$(notdir $(BOUNDARYSources)))     \
+          $(addprefix pughslab_,$(notdir $(PUGHSLABSources)))     \
+          $(addprefix ioascii_,$(notdir $(IOASCIISources)))       \
+          $(addprefix iobasic_,$(notdir $(IOBASICSources)))
+
+CPPFLAGS += \
+          -DCCODE                                 \
+          -I$(SPEC_BENCH_DIR)/src/PUGH            \
+          -I$(SPEC_BENCH_DIR)/src/Time            \
+          -I$(SPEC_BENCH_DIR)/src/Cactus          \
+          -I$(SPEC_BENCH_DIR)/src/IOUtil          \
+          -I$(SPEC_BENCH_DIR)/src/IDLinearWaves   \
+          -I$(SPEC_BENCH_DIR)/src/BenchADMsrc     \
+          -I$(SPEC_BENCH_DIR)/src/CactusBindings  \
+          -I$(SPEC_BENCH_DIR)/src/CartGrid3D      \
+          -I$(SPEC_BENCH_DIR)/src/Einstein        \
+          -I$(SPEC_BENCH_DIR)/src/PUGHReduce      \
+          -I$(SPEC_BENCH_DIR)/src/Boundary        \
+          -I$(SPEC_BENCH_DIR)/src/PUGHSlab        \
+          -I$(SPEC_BENCH_DIR)/src/IOASCII         \
+          -I$(SPEC_BENCH_DIR)/src/IOBasic         \
+          -I$(SPEC_BENCH_DIR)/src                 \
+          -I$(SPEC_BENCH_DIR)/src/include 
+
 include ../../Makefile.spec2006
 include $(PROJ_SRC_ROOT)/Makefile.FORTRAN
 
-CFLAGS += -DCCODE
-
 RUN_OPTIONS      = benchADM
 STDOUT_FILENAME := benchADM.out
+
+##===----------------------------------------------------------------------===##
+# Copy the source files to the working directory. Some files may have the
+# same names but are in different directories, so we add a prefix to
+# the filenames to prevent overwriting files.
+##===----------------------------------------------------------------------===##
+
+$(notdir $(TOPSources)) : % : \
+$(SPEC_BENCH_DIR)/src/%
+	cp $< $@
+$(addprefix pugh_,$(notdir $(PUGHSources))) : pugh_% : \
+$(SPEC_BENCH_DIR)/src/PUGH/%
+	cp $< $@
+$(addprefix time_,$(notdir $(TIMESources))) : time_% : \
+$(SPEC_BENCH_DIR)/src/Time/%
+	cp $< $@
+$(addprefix cactus_,$(notdir $(CACTUSSources))) : cactus_% : \
+$(SPEC_BENCH_DIR)/src/Cactus/%
+	cp $< $@
+$(addprefix ioutil_,$(notdir $(IOUTILSources))) : ioutil_% : \
+$(SPEC_BENCH_DIR)/src/IOUtil/%
+	cp $< $@
+$(addprefix idlw_,$(notdir $(IDLINEARWAVESSources))) : idlw_% : \
+$(SPEC_BENCH_DIR)/src/IDLinearWaves/%
+	cp $< $@
+$(addprefix badmsrc_,$(notdir $(BENCHADMSRCSources))) : badmsrc_% : \
+$(SPEC_BENCH_DIR)/src/BenchADMsrc/%
+	cp $< $@
+$(addprefix cbnds_,$(notdir $(CACTUSBINDINGSSources))) : cbnds_% : \
+$(SPEC_BENCH_DIR)/src/CactusBindings/%
+	cp $< $@
+$(addprefix cg3d_,$(notdir $(CARTGRID3DSources))) : cg3d_% : \
+$(SPEC_BENCH_DIR)/src/CartGrid3D/%
+	cp $< $@
+$(addprefix einstein_,$(notdir $(EINSTEINSources))) : einstein_% : \
+$(SPEC_BENCH_DIR)/src/Einstein/%
+	cp $< $@
+$(addprefix pughreduce_,$(notdir $(PUGHREDUCESources))) : pughreduce_% : \
+$(SPEC_BENCH_DIR)/src/PUGHReduce/%
+	cp $< $@
+$(addprefix boundary_,$(notdir $(BOUNDARYSources))) : boundary_% : \
+$(SPEC_BENCH_DIR)/src/Boundary/%
+	cp $< $@
+$(addprefix pughslab_,$(notdir $(PUGHSLABSources))) : pughslab_% : \
+$(SPEC_BENCH_DIR)/src/PUGHSlab/%
+	cp $< $@
+$(addprefix ioascii_,$(notdir $(IOASCIISources))) : ioascii_% : \
+$(SPEC_BENCH_DIR)/src/IOASCII/%
+	cp $< $@
+$(addprefix iobasic_,$(notdir $(IOBASICSources))) : iobasic_% : \
+$(SPEC_BENCH_DIR)/src/IOBasic/%
+	cp $< $@
+
+##===----------------------------------------------------------------------===##
+# Clean up all of the copied source files.
+##===----------------------------------------------------------------------===##
+
+clean::
+	$(RM) -f $(Source)





From isanbard at gmail.com  Thu Sep  7 19:59:31 2006
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 7 Sep 2006 19:59:31 -0500
Subject: [llvm-commits] CVS:
	llvm-test/External/SPEC/CFP2006/454.calculix/Makefile
Message-ID: <200609080059.k880xV4X015423@zion.cs.uiuc.edu>



Changes in directory llvm-test/External/SPEC/CFP2006/454.calculix:

Makefile updated: 1.2 -> 1.3
---
Log message:

Added support for SPEC benchmarks with mutiple directories. Stolen from the
POVRay way of doing things.


---
Diffs of the changes:  (+248 -35)

 Makefile |  283 +++++++++++++++++++++++++++++++++++++++++++++++++++++++--------
 1 files changed, 248 insertions(+), 35 deletions(-)


Index: llvm-test/External/SPEC/CFP2006/454.calculix/Makefile
diff -u llvm-test/External/SPEC/CFP2006/454.calculix/Makefile:1.2 llvm-test/External/SPEC/CFP2006/454.calculix/Makefile:1.3
--- llvm-test/External/SPEC/CFP2006/454.calculix/Makefile:1.2	Wed Sep  6 15:41:12 2006
+++ llvm-test/External/SPEC/CFP2006/454.calculix/Makefile	Thu Sep  7 19:59:14 2006
@@ -9,7 +9,8 @@
 FP_TOLERANCE    = 1.0e-9
 FP_ABSTOLERANCE = 1.0e-9
 
-Source = CalculiX.c add_pr.f add_sm_ei.f add_sm_st.f allocation.f amplitudes.f \
+TOPSources := \
+         CalculiX.c add_pr.f add_sm_ei.f add_sm_st.f allocation.f amplitudes.f \
          anisotropic.f beamsections.f bounadd.f boundaries.f buckles.f         \
          calinput.f cfluxes.f changedepterm.f cloads.f conductivities.f        \
          controlss.f couptempdisps.f creeps.f cychards.f cycsymmods.f dasol.f  \
@@ -45,102 +46,204 @@
          viscos.f wcoef.f writebv.f writeev.f writeevcs.f writempc.f           \
          writesummary.f cascade.c frdcyc.c insert.c mastruct.c mastructcs.c    \
          nonlingeo.c pcgsolver.c preiter.c prespooles.c profile.c remastruct.c \
-         spooles.c strcmp1.c strcpy1.c u_calloc.c                              \
+         spooles.c strcmp1.c strcpy1.c u_calloc.c
+A2Sources := \
          $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/A2/src/,                    \
            A2_IO.c A2_basics.c A2_init.c A2_instance.c A2_norms.c A2_sort.c    \
-           A2_util.c)                                                          \
+           A2_util.c)
+BKLSources := \
          $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/BKL/src/,                   \
            BKL_basics.c BKL_evalfcn.c BKL_exhSearch.c BKL_fidmat.c BKL_init.c  \
-           BKL_util.c)                                                         \
+           BKL_util.c)
+BPGSources := \
          $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/BPG/src/,                   \
-           BPG_IO.c BPG_basics.c BPG_init.c BPG_makeGraphs.c BPG_pseudo.c)     \
+           BPG_IO.c BPG_basics.c BPG_init.c BPG_makeGraphs.c BPG_pseudo.c)
+CHVSources := \
          $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/Chv/src/,                   \
            Chv_IO.c Chv_assemble.c Chv_basics.c Chv_copy.c Chv_factor.c        \
            Chv_findPivot.c Chv_init.c Chv_instance.c Chv_search.c Chv_swap.c   \
-           Chv_update.c Chv_util.c)                                            \
+           Chv_update.c Chv_util.c)
+CHVLISTSources := \
          $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/ChvList/src/,               \
-           ChvList_basics.c ChvList_init.c ChvList_util.c)                     \
+           ChvList_basics.c ChvList_init.c ChvList_util.c)
+CHVMANAGERSources := \
          $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/ChvManager/src/,            \
-           ChvManager_basics.c ChvManager_init.c ChvManager_util.c)            \
+           ChvManager_basics.c ChvManager_init.c ChvManager_util.c)
+DSTREESources := \
          $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/DSTree/src/,                \
            DSTree_basics.c DSTree_init.c DSTree_instance.c DSTree_stages.c     \
-           DSTree_util.c)                                                      \
+           DSTree_util.c)
+DVSources := \
          $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/DV/src/,                    \
-           DV_IO.c DV_basics.c DV_init.c DV_instance.c DV_util.c)              \
+           DV_IO.c DV_basics.c DV_init.c DV_instance.c DV_util.c)
+DENSEMTXSources := \
          $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/DenseMtx/src/,              \
            DenseMtx_IO.c DenseMtx_basics.c DenseMtx_init.c DenseMtx_instance.c \
-           DenseMtx_permute.c DenseMtx_util.c)                                 \
+           DenseMtx_permute.c DenseMtx_util.c)
+DRANDSources := \
          $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/Drand/src/,                 \
-           Drand_basics.c Drand_init.c Drand_util.c)                           \
+           Drand_basics.c Drand_init.c Drand_util.c)
+ETREESources := \
          $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/ETree/src/,                 \
            ETree_IO.c ETree_basics.c ETree_compress.c ETree_init.c             \
-           ETree_instance.c ETree_permute.c ETree_transform.c ETree_util.c)    \
+           ETree_instance.c ETree_permute.c ETree_transform.c ETree_util.c)
+FRONTMTXSources := \
          $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/FrontMtx/src/,              \
            FrontMtx_IO.c FrontMtx_basics.c FrontMtx_factor.c                   \
            FrontMtx_factorUtil.c FrontMtx_init.c FrontMtx_instance.c           \
            FrontMtx_loadEntries.c FrontMtx_permute.c FrontMtx_postProcess.c    \
            FrontMtx_postponed.c FrontMtx_solve.c FrontMtx_solveUtil.c          \
            FrontMtx_split.c FrontMtx_storeFront.c FrontMtx_update.c            \
-           FrontMtx_util.c)                                                    \
+           FrontMtx_util.c)
+GPARTSources := \
          $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/GPart/src/,                 \
            GPart_DDsepInfo.c GPart_DDviaFishnet.c GPart_DDviaProjection.c      \
            GPart_RBviaDDsep.c GPart_TwoSetViaBKL.c GPart_basics.c              \
            GPart_domSegMap.c GPart_identifyWideSep.c GPart_init.c              \
            GPart_makeYCmap.c GPart_smoothBisector.c GPart_smoothBy2layers.c    \
-           GPart_smoothYSep.c GPart_split.c GPart_util.c)                      \
+           GPart_smoothYSep.c GPart_split.c GPart_util.c)
+GRAPHSources := \
          $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/Graph/src/,                 \
            Graph_IO.c Graph_basics.c Graph_compress.c Graph_equivMap.c         \
-           Graph_init.c Graph_util.c)                                          \
+           Graph_init.c Graph_util.c)
+I2OHASHSources := \
          $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/I2Ohash/src/,               \
-           I2Ohash_basics.c I2Ohash_init.c I2Ohash_util.c)                     \
-         $(SPEC_BENCH_DIR)/src/SPOOLES/IIheap/src/IIheap_basics.c              \
+           I2Ohash_basics.c I2Ohash_init.c I2Ohash_util.c)
+IIHEAPSources := \
+         $(SPEC_BENCH_DIR)/src/SPOOLES/IIheap/src/IIheap_basics.c
+IVSources := \
          $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/IV/src/,                    \
-           IV_IO.c IV_basics.c IV_init.c IV_instance.c IV_util.c)              \
+           IV_IO.c IV_basics.c IV_init.c IV_instance.c IV_util.c)
+IVLSources := \
          $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/IVL/src/,                   \
            IVL_IO.c IVL_basics.c IVL_init.c IVL_instance.c IVL_listmanip.c     \
-           IVL_util.c)                                                         \
+           IVL_util.c)
+IDEQSources := \
          $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/Ideq/src/,                  \
-           Ideq_basics.c Ideq_resize.c Ideq_util.c)                            \
+           Ideq_basics.c Ideq_resize.c Ideq_util.c)
+INPMTXSources := \
          $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/InpMtx/src/,                \
            InpMtx_IO.c InpMtx_basics.c InpMtx_fullAdj.c InpMtx_init.c          \
-           InpMtx_input.c InpMtx_instance.c InpMtx_permute.c InpMtx_util.c)    \
+           InpMtx_input.c InpMtx_instance.c InpMtx_permute.c InpMtx_util.c)
+LOCKSources := \
          $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/Lock/src/,                  \
-           Lock_basics.c Lock_init.c Lock_util.c)                              \
+           Lock_basics.c Lock_init.c Lock_util.c)
+MSMDSources := \
          $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/MSMD/src/,                  \
            MSMD_MSMDinfo.c MSMD_MSMDvtx.c MSMD_basics.c MSMD_cleanReachSet.c   \
            MSMD_eliminate.c MSMD_findInodes.c MSMD_frontETree.c MSMD_init.c    \
-           MSMD_order.c MSMD_update.c)                                         \
+           MSMD_order.c MSMD_update.c)
+NETWORKSources := \
          $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/Network/src/,               \
            Network_IO.c Network_addArc.c Network_augmentPath.c                 \
            Network_basics.c Network_findAugmentingPath.c Network_findMaxFlow.c \
-           Network_findMincut.c Network_init.c)                                \
+           Network_findMincut.c Network_init.c)
+PENCILSources := \
          $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/Pencil/src/,                \
-           Pencil_IO.c Pencil_basics.c Pencil_init.c)                          \
+           Pencil_IO.c Pencil_basics.c Pencil_init.c)
+SUBMTXSources := \
          $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/SubMtx/src/,                \
            SubMtx_IO.c SubMtx_basics.c SubMtx_init.c SubMtx_instance.c         \
            SubMtx_scalevec.c SubMtx_solve.c SubMtx_solveH.c SubMtx_solveT.c    \
            SubMtx_solveupd.c SubMtx_solveupdH.c SubMtx_solveupdT.c             \
-           SubMtx_sort.c SubMtx_util.c)                                        \
-         $(SPEC_BENCH_DIR)/src/SPOOLES/SubMtxList/src/SubMtxList_util.c        \
+           SubMtx_sort.c SubMtx_util.c)
+SUBMTXLISTSources := \
+         $(SPEC_BENCH_DIR)/src/SPOOLES/SubMtxList/src/SubMtxList_util.c
+SUBMTXMANAGERSources := \
          $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/SubMtxManager/src/,         \
-           SubMtxManager_basics.c SubMtxManager_init.c SubMtxManager_util.c)   \
-         $(SPEC_BENCH_DIR)/src/SPOOLES/SymbFac/src/SymbFac_symbfac.c           \
+           SubMtxManager_basics.c SubMtxManager_init.c SubMtxManager_util.c)
+SYMBFACSources := \
+         $(SPEC_BENCH_DIR)/src/SPOOLES/SymbFac/src/SymbFac_symbfac.c
+TREESources := \
          $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/Tree/src/,                  \
            Tree_IO.c Tree_basics.c Tree_compress.c Tree_init.c Tree_metrics.c  \
-           Tree_perms.c Tree_util.c)                                           \
+           Tree_perms.c Tree_util.c)
+UTILITIESSources := \
          $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/Utilities/src/,             \
            Utilities_CV.c Utilities_DV.c Utilities_I2OP.c Utilities_IP.c       \
            Utilities_IV.c Utilities_PIV.c Utilities_ZV.c Utilities_iohb.c      \
-           Utilities_newsort.c Utilities_sortAndCompress.c)                    \
+           Utilities_newsort.c Utilities_sortAndCompress.c)
+ZVSources := \
          $(addprefix $(SPEC_BENCH_DIR)/src/SPOOLES/ZV/src/,                    \
-           ZV_basics.c ZV_init.c ZV_instance.c)                                \
+           ZV_basics.c ZV_init.c ZV_instance.c)
+MISCSources := \
          $(SPEC_BENCH_DIR)/src/SPOOLES/misc/src/misc_orderViaBestOfNDandMS.c
 
+Source := \
+         $(notdir $(TOPSources))                               \
+         $(addprefix a2_,$(notdir $(A2Sources)))               \
+         $(addprefix bkl_,$(notdir $(BKLSources)))             \
+         $(addprefix bpg_,$(notdir $(BPGSources)))             \
+         $(addprefix chv_,$(notdir $(CHVSources)))             \
+         $(addprefix chvl_,$(notdir $(CHVLISTSources)))        \
+         $(addprefix chvm_,$(notdir $(CHVMANAGERSources)))     \
+         $(addprefix dstree_,$(notdir $(DSTREESources)))       \
+         $(addprefix dv_,$(notdir $(DVSources)))               \
+         $(addprefix dmtx_,$(notdir $(DENSEMTXSources)))       \
+         $(addprefix drand_,$(notdir $(DRANDSources)))         \
+         $(addprefix etree_,$(notdir $(ETREESources)))         \
+         $(addprefix fmtx_,$(notdir $(FRONTMTXSources)))       \
+         $(addprefix gpart_,$(notdir $(GPARTSources)))         \
+         $(addprefix graph_,$(notdir $(GRAPHSources)))         \
+         $(addprefix i2oh_,$(notdir $(I2OHASHSources)))        \
+         $(addprefix iiheap_,$(notdir $(IIHEAPSources)))       \
+         $(addprefix iv_,$(notdir $(IVSources)))               \
+         $(addprefix ivl_,$(notdir $(IVLSources)))             \
+         $(addprefix ideq_,$(notdir $(IDEQSources)))           \
+         $(addprefix inpmtx_,$(notdir $(INPMTXSources)))       \
+         $(addprefix lock_,$(notdir $(LOCKSources)))           \
+         $(addprefix msmd_,$(notdir $(MSMDSources)))           \
+         $(addprefix network_,$(notdir $(NETWORKSources)))     \
+         $(addprefix pencil_,$(notdir $(PENCILSources)))       \
+         $(addprefix smtx_,$(notdir $(SUBMTXSources)))         \
+         $(addprefix smtxl_,$(notdir $(SUBMTXLISTSources)))    \
+         $(addprefix smtxm_,$(notdir $(SUBMTXMANAGERSources))) \
+         $(addprefix symbfac_,$(notdir $(SYMBFACSources)))     \
+         $(addprefix tree_,$(notdir $(TREESources)))           \
+         $(addprefix utils_,$(notdir $(UTILITIESSources)))     \
+         $(addprefix zv_,$(notdir $(ZVSources)))               \
+         $(addprefix misc_,$(notdir $(MISCSources)))
+
+CPPFLAGS += \
+         -I$(SPEC_BENCH_DIR)/src/SPOOLES/A2/src                \
+         -I$(SPEC_BENCH_DIR)/src/SPOOLES/BKL/src               \
+         -I$(SPEC_BENCH_DIR)/src/SPOOLES/BPG/src               \
+         -I$(SPEC_BENCH_DIR)/src/SPOOLES/Chv/src               \
+         -I$(SPEC_BENCH_DIR)/src/SPOOLES/ChvList/src           \
+         -I$(SPEC_BENCH_DIR)/src/SPOOLES/ChvManager/src        \
+         -I$(SPEC_BENCH_DIR)/src/SPOOLES/DSTree/src            \
+         -I$(SPEC_BENCH_DIR)/src/SPOOLES/DV/src                \
+         -I$(SPEC_BENCH_DIR)/src/SPOOLES/DenseMtx/src          \
+         -I$(SPEC_BENCH_DIR)/src/SPOOLES/Drand/src             \
+         -I$(SPEC_BENCH_DIR)/src/SPOOLES/ETree/src             \
+         -I$(SPEC_BENCH_DIR)/src/SPOOLES/FrontMtx/src          \
+         -I$(SPEC_BENCH_DIR)/src/SPOOLES/GPart/src             \
+         -I$(SPEC_BENCH_DIR)/src/SPOOLES/Graph/src             \
+         -I$(SPEC_BENCH_DIR)/src/SPOOLES/I2Ohash/src           \
+         -I$(SPEC_BENCH_DIR)/src/SPOOLES/IIheap/src            \
+         -I$(SPEC_BENCH_DIR)/src/SPOOLES/IV/src                \
+         -I$(SPEC_BENCH_DIR)/src/SPOOLES/IVL/src               \
+         -I$(SPEC_BENCH_DIR)/src/SPOOLES/Ideq/src              \
+         -I$(SPEC_BENCH_DIR)/src/SPOOLES/InpMtx/src            \
+         -I$(SPEC_BENCH_DIR)/src/SPOOLES/Lock/src              \
+         -I$(SPEC_BENCH_DIR)/src/SPOOLES/MSMD/src              \
+         -I$(SPEC_BENCH_DIR)/src/SPOOLES/Network/src           \
+         -I$(SPEC_BENCH_DIR)/src/SPOOLES/Pencil/src            \
+         -I$(SPEC_BENCH_DIR)/src/SPOOLES/SubMtx/src            \
+         -I$(SPEC_BENCH_DIR)/src/SPOOLES/SubMtxList/src        \
+         -I$(SPEC_BENCH_DIR)/src/SPOOLES/SubMtxManager/src     \
+         -I$(SPEC_BENCH_DIR)/src/SPOOLES/SymbFac/src           \
+         -I$(SPEC_BENCH_DIR)/src/SPOOLES/Tree/src              \
+         -I$(SPEC_BENCH_DIR)/src/SPOOLES/Utilities/src         \
+         -I$(SPEC_BENCH_DIR)/src/SPOOLES/ZV/src                \
+         -I$(SPEC_BENCH_DIR)/src/SPOOLES/misc/src              \
+         -I$(SPEC_BENCH_DIR)/src/SPOOLES                       \
+         -I$(SPEC_BENCH_DIR)/src                               \
+         -I$(SPEC_BENCH_DIR)/src/include 
+
 include ../../Makefile.spec2006
 include $(PROJ_SRC_ROOT)/Makefile.FORTRAN
 
-CPPFLAGS += -I$(SPEC_BENCH_DIR)/src/SPOOLES
-
 ifeq ($(RUN_TYPE),test)
   RUN_OPTIONS     := -i beampic
   STDOUT_FILENAME := beampic.log
@@ -148,3 +251,113 @@
   RUN_OPTIONS     := -i stairs
   STDOUT_FILENAME := stairs.log
 endif
+
+##===----------------------------------------------------------------------===##
+# Copy the source files to the working directory. Some files may have the
+# same names but are in different directories, so we add a prefix to
+# the filenames to prevent overwriting files.
+##===----------------------------------------------------------------------===##
+
+$(notdir $(TOPSources)) : % : \
+$(SPEC_BENCH_DIR)/src/%
+	cp $< $@
+$(addprefix a2_,$(notdir $(A2Sources))) : a2_% : \
+$(SPEC_BENCH_DIR)/src/SPOOLES/A2/src/%
+	cp $< $@
+$(addprefix bkl_,$(notdir $(BKLSources))) : bkl_% : \
+$(SPEC_BENCH_DIR)/src/SPOOLES/BKL/src/%
+	cp $< $@
+$(addprefix bpg_,$(notdir $(BPGSources))) : bpg_% : \
+$(SPEC_BENCH_DIR)/src/SPOOLES/BPG/src/%
+	cp $< $@
+$(addprefix chv_,$(notdir $(CHVSources))) : chv_% : \
+$(SPEC_BENCH_DIR)/src/SPOOLES/Chv/src/%
+	cp $< $@
+$(addprefix chvl_,$(notdir $(CHVLISTSources))) : chvl_% : \
+$(SPEC_BENCH_DIR)/src/SPOOLES/ChvList/src/%
+	cp $< $@
+$(addprefix chvm_,$(notdir $(CHVMANAGERSources))) : chvm_% : \
+$(SPEC_BENCH_DIR)/src/SPOOLES/ChvManager/src/%
+	cp $< $@
+$(addprefix dstree_,$(notdir $(DSTREESources))) : dstree_% : \
+$(SPEC_BENCH_DIR)/src/SPOOLES/DSTree/src/%
+	cp $< $@
+$(addprefix dmtx_,$(notdir $(DENSEMTXSources))) : dmtx_% : \
+$(SPEC_BENCH_DIR)/src/SPOOLES/DenseMtx/src/%
+	cp $< $@
+$(addprefix drand_,$(notdir $(DRANDSources))) : drand_% : \
+$(SPEC_BENCH_DIR)/src/SPOOLES/Drand/src/%
+	cp $< $@
+$(addprefix etree_,$(notdir $(ETREESources))) : etree_% : \
+$(SPEC_BENCH_DIR)/src/SPOOLES/ETree/src/%
+	cp $< $@
+$(addprefix fmtx_,$(notdir $(FRONTMTXSources))) : fmtx_% : \
+$(SPEC_BENCH_DIR)/src/SPOOLES/FrontMtx/src/%
+	cp $< $@
+$(addprefix gpart_,$(notdir $(GPARTSources))) : gpart_% : \
+$(SPEC_BENCH_DIR)/src/SPOOLES/GPart/src/%
+	cp $< $@
+$(addprefix graph_,$(notdir $(GRAPHSources))) : graph_% : \
+$(SPEC_BENCH_DIR)/src/SPOOLES/Graph/src/%
+	cp $< $@
+$(addprefix i2oh_,$(notdir $(I2OHASHSources))) : i2oh_% : \
+$(SPEC_BENCH_DIR)/src/SPOOLES/I2Ohash/src/%
+	cp $< $@
+$(addprefix iiheap_,$(notdir $(IIHEAPSources))) : iiheap_% : \
+$(SPEC_BENCH_DIR)/src/SPOOLES/IIheap/src/%
+	cp $< $@
+$(addprefix iv_,$(notdir $(IVSources))) : iv_% : \
+$(SPEC_BENCH_DIR)/src/SPOOLES/IV/src/%
+	cp $< $@
+$(addprefix ivl_,$(notdir $(IVLSources))) : ivl_% : \
+$(SPEC_BENCH_DIR)/src/SPOOLES/IVL/src/%
+	cp $< $@
+$(addprefix ideq_,$(notdir $(IEQSources))) : ideq_% : \
+$(SPEC_BENCH_DIR)/src/SPOOLES/Ideq/src/%
+	cp $< $@
+$(addprefix inpmtx_,$(notdir $(INPMTXSources))) : inpmtx_% : \
+$(SPEC_BENCH_DIR)/src/SPOOLES/InpMtx/src/%
+	cp $< $@
+$(addprefix lock_,$(notdir $(LOCKSources))) : lock_% : \
+$(SPEC_BENCH_DIR)/src/SPOOLES/Lock/src/%
+	cp $< $@
+$(addprefix msmd_,$(notdir $(MSMDSources))) : msmd_% : \
+$(SPEC_BENCH_DIR)/src/SPOOLES/MSMD/src/%
+	cp $< $@
+$(addprefix network_,$(notdir $(NETWORKSources))) : network_% : \
+$(SPEC_BENCH_DIR)/src/SPOOLES/Network/src/%
+	cp $< $@
+$(addprefix pencil_,$(notdir $(PENCILSources))) : pencil_% : \
+$(SPEC_BENCH_DIR)/src/SPOOLES/Pencil/src/%
+	cp $< $@
+$(addprefix smtx_,$(notdir $(SUBMTXSources))) : smtx_% : \
+$(SPEC_BENCH_DIR)/src/SPOOLES/SubMtx/src/%
+	cp $< $@
+$(addprefix smtxl_,$(notdir $(SUBMTXLISTSources))) : smtxl_% : \
+$(SPEC_BENCH_DIR)/src/SPOOLES/SubMtxList/src/%
+	cp $< $@
+$(addprefix smtxm_,$(notdir $(SUBMTXMANAGERSources))) : smtxm_% : \
+$(SPEC_BENCH_DIR)/src/SPOOLES/SubMtxManager/src/%
+	cp $< $@
+$(addprefix symbfac_,$(notdir $(SYMBFACSources))) : symbfac_% : \
+$(SPEC_BENCH_DIR)/src/SPOOLES/SymbFac/src/%
+	cp $< $@
+$(addprefix tree_,$(notdir $(TREESources))) : tree_% : \
+$(SPEC_BENCH_DIR)/src/SPOOLES/Tree/src/%
+	cp $< $@
+$(addprefix utils_,$(notdir $(UTILITIESSources))) : utils_% : \
+$(SPEC_BENCH_DIR)/src/SPOOLES/Utilities/src/%
+	cp $< $@
+$(addprefix zv_,$(notdir $(ZVSources))) : zv_% : \
+$(SPEC_BENCH_DIR)/src/SPOOLES/ZV/src/%
+	cp $< $@
+$(addprefix misc_,$(notdir $(MISCSources))) : misc_% : \
+$(SPEC_BENCH_DIR)/src/SPOOLES/misc/src/%
+	cp $< $@
+
+##===----------------------------------------------------------------------===##
+# Clean up all of the copied source files.
+##===----------------------------------------------------------------------===##
+
+clean::
+	$(RM) -f $(Source)





From isanbard at gmail.com  Thu Sep  7 19:59:31 2006
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 7 Sep 2006 19:59:31 -0500
Subject: [llvm-commits] CVS: llvm-test/External/SPEC/CFP2006/Makefile
Message-ID: <200609080059.k880xVuQ015433@zion.cs.uiuc.edu>



Changes in directory llvm-test/External/SPEC/CFP2006:

Makefile updated: 1.2 -> 1.3
---
Log message:

Added support for SPEC benchmarks with mutiple directories. Stolen from the
POVRay way of doing things.


---
Diffs of the changes:  (+15 -15)

 Makefile |   30 +++++++++++++++---------------
 1 files changed, 15 insertions(+), 15 deletions(-)


Index: llvm-test/External/SPEC/CFP2006/Makefile
diff -u llvm-test/External/SPEC/CFP2006/Makefile:1.2 llvm-test/External/SPEC/CFP2006/Makefile:1.3
--- llvm-test/External/SPEC/CFP2006/Makefile:1.2	Wed Sep  6 15:41:12 2006
+++ llvm-test/External/SPEC/CFP2006/Makefile	Thu Sep  7 19:59:14 2006
@@ -6,27 +6,27 @@
 
 LEVEL = ../../..
 
-PARALLEL_DIRS := \
-    410.bwaves   \
-    416.gamess   \
-    433.milc     \
-    434.zeusmp   \
-    435.gromacs  \
-    437.leslie3d \
-    444.namd     \
-    447.dealII   \
-    459.GemsFDTD \
-    470.lbm
+PARALLEL_DIRS :=  \
+    410.bwaves    \
+    416.gamess    \
+    433.milc      \
+    434.zeusmp    \
+    435.gromacs   \
+    436.cactusADM \
+    437.leslie3d  \
+    444.namd      \
+    447.dealII    \
+    454.calculix  \
+    459.GemsFDTD  \
+    470.lbm       \
+    481.wrf
+
 
 # These compile but need other things to run:
 #   450.soplex    - enter.cc:535, works at -O0, not at -O2
 #   453.povray    - c++ exceptions
 #   465.tonto     - infinite loop, works at -O0, not at -O2
 #   482.sphinx3   - generates control file at run time
-# These don't compile
-#   436.cactusADM - multiple dirs
-#   454.calculix  - multiple dirs
-#   481.wrf       - multiple dirs
 
 # Get the $(ARCH) setting
 include $(LEVEL)/Makefile.config





From isanbard at gmail.com  Thu Sep  7 19:59:33 2006
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 7 Sep 2006 19:59:33 -0500
Subject: [llvm-commits] CVS: llvm-test/External/SPEC/CFP2006/481.wrf/Makefile
Message-ID: <200609080059.k880xXuW015438@zion.cs.uiuc.edu>



Changes in directory llvm-test/External/SPEC/CFP2006/481.wrf:

Makefile updated: 1.2 -> 1.3
---
Log message:

Added support for SPEC benchmarks with mutiple directories. Stolen from the
POVRay way of doing things.


---
Diffs of the changes:  (+36 -5)

 Makefile |   41 ++++++++++++++++++++++++++++++++++++-----
 1 files changed, 36 insertions(+), 5 deletions(-)


Index: llvm-test/External/SPEC/CFP2006/481.wrf/Makefile
diff -u llvm-test/External/SPEC/CFP2006/481.wrf/Makefile:1.2 llvm-test/External/SPEC/CFP2006/481.wrf/Makefile:1.3
--- llvm-test/External/SPEC/CFP2006/481.wrf/Makefile:1.2	Wed Sep  6 15:41:12 2006
+++ llvm-test/External/SPEC/CFP2006/481.wrf/Makefile	Thu Sep  7 19:59:14 2006
@@ -9,7 +9,8 @@
 FP_TOLERANCE    = 5e-2
 FP_ABSTOLERANCE = 1.0e-2
 
-Source = wrf_num_bytes_between.c pack_utils.c module_driver_constants.F90      \
+TOPSources := \
+         wrf_num_bytes_between.c pack_utils.c module_driver_constants.F90      \
          module_domain.F90 module_integrate.F90 module_timing.F90              \
          module_configure.F90 module_tiles.F90 module_machine.F90              \
          module_nesting.F90 module_wrf_error.F90 module_state_description.F90  \
@@ -51,7 +52,8 @@
          module_cumulus_driver.F90 module_microphysics_driver.F90              \
          solve_em.F90 start_em.F90 internal_header_util.F90 io_int.F90         \
          init_modules_em.F90 init_modules.F90 wrf_io.f90 field_routines.f90    \
-         wrf.F90                                                               \
+         wrf.F90
+NETCDFSources := \
          $(addprefix $(SPEC_BENCH_DIR)/src/netcdf/,                            \
            attr.c dim.c error.c fort-attio.c fort-control.c fort-dim.c         \
            fort-genatt.c fort-geninq.c fort-genvar.c fort-lib.c fort-misc.c    \
@@ -59,8 +61,9 @@
            fort-varmio.c fort-varsio.c libvers.c nc.c ncx.c posixio.c putget.c \
            string.c v1hpg.c v2i.c var.c typeSizes.f90 netcdf.f90)
 
-include ../../Makefile.spec2006
-include $(PROJ_SRC_ROOT)/Makefile.FORTRAN
+Source := \
+         $(notdir $(TOPSources)) \
+         $(addprefix netcdf_,$(notdir $(NETCDFSources)))
 
 FPPFLAGS += -w -m literal.pm                                                   \
             -DINTIO -DIWORDSIZE=4 -DDWORDSIZE=8 -DRWORDSIZE=4 -DLWORDSIZE=4    \
@@ -68,6 +71,34 @@
             -DNMM_MAX_DIM=1000 -DCOAMPS_CORE=0  -DEXP_CORE=0 -DF90_STANDALONE  \
             -DCONFIG_BUF_LEN=8192 -DMAX_DOMAINS_F=21 -DNO_NAMELIST_PRINT
 
-CPPFLAGS += -I$(SPEC_BENCH_DIR)/src/netcdf/include
+CPPFLAGS += \
+         -I$(SPEC_BENCH_DIR)/src/netcdf         \
+         -I$(SPEC_BENCH_DIR)/src/netcdf/include \
+         -I$(SPEC_BENCH_DIR)/src                \
+         -I$(SPEC_BENCH_DIR)/src/include 
+
+
+include ../../Makefile.spec2006
+include $(PROJ_SRC_ROOT)/Makefile.FORTRAN
 
 STDOUT_FILENAME := rsl.out.0000
+
+##===----------------------------------------------------------------------===##
+# Copy the source files to the working directory. Some files may have the
+# same names but are in different directories, so we add a prefix to
+# the filenames to prevent overwriting files.
+##===----------------------------------------------------------------------===##
+
+$(notdir $(TOPSources)) : % : \
+$(SPEC_BENCH_DIR)/src/%
+	cp $< $@
+$(addprefix netcdf_,$(notdir $(NETCDFSources))) : netcdf_% : \
+$(SPEC_BENCH_DIR)/src/netcdf/%
+	cp $< $@
+
+##===----------------------------------------------------------------------===##
+# Clean up all of the copied source files.
+##===----------------------------------------------------------------------===##
+
+clean::
+	$(RM) -f $(Source)





From evan.cheng at apple.com  Thu Sep  7 20:50:20 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 7 Sep 2006 20:50:20 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
Message-ID: <200609080150.k881oKQC016284@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86ISelLowering.cpp updated: 1.251 -> 1.252
---
Log message:

- Identify a vector_shuffle that can be turned into an undef, e.g.
  shuffle V1, <undef>, <undef, undef, 4, 5>
- Fix some suspicious logic into LowerVectorShuffle that cause less than
  optimal code by failing to identify MOVL (move to lowest element of a
  vector).


---
Diffs of the changes:  (+41 -15)

 X86ISelLowering.cpp |   56 ++++++++++++++++++++++++++++++++++++++--------------
 1 files changed, 41 insertions(+), 15 deletions(-)


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.251 llvm/lib/Target/X86/X86ISelLowering.cpp:1.252
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.251	Thu Sep  7 15:33:45 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp	Thu Sep  7 20:50:06 2006
@@ -1719,7 +1719,8 @@
 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
 /// of what x86 movss want. X86 movs requires the lowest  element to be lowest
 /// element of vector 2 and the other elements to come from vector 1 in order.
-static bool isCommutedMOVL(std::vector<SDOperand> &Ops, bool V2IsSplat = false) {
+static bool isCommutedMOVL(std::vector<SDOperand> &Ops, bool V2IsSplat = false,
+                           bool V2IsUndef = false) {
   unsigned NumElems = Ops.size();
   if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
     return false;
@@ -1729,22 +1730,20 @@
 
   for (unsigned i = 1; i < NumElems; ++i) {
     SDOperand Arg = Ops[i];
-    if (V2IsSplat) {
-      if (!isUndefOrEqual(Arg, NumElems))
-        return false;
-    } else {
-      if (!isUndefOrEqual(Arg, i+NumElems))
-        return false;
-    }
+    if (!(isUndefOrEqual(Arg, i+NumElems) ||
+          (V2IsUndef && isUndefOrInRange(Arg, NumElems, NumElems*2)) ||
+          (V2IsSplat && isUndefOrEqual(Arg, NumElems))))
+      return false;
   }
 
   return true;
 }
 
-static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false) {
+static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false,
+                           bool V2IsUndef = false) {
   assert(N->getOpcode() == ISD::BUILD_VECTOR);
   std::vector<SDOperand> Ops(N->op_begin(), N->op_end());
-  return isCommutedMOVL(Ops, V2IsSplat);
+  return isCommutedMOVL(Ops, V2IsSplat, V2IsUndef);
 }
 
 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
@@ -2034,6 +2033,29 @@
   return true;
 }
 
+/// isUndefShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
+/// to an undef.
+static bool isUndefShuffle(SDNode *N) {
+  if (N->getOpcode() != ISD::BUILD_VECTOR)
+    return false;
+
+  SDOperand V1 = N->getOperand(0);
+  SDOperand V2 = N->getOperand(1);
+  SDOperand Mask = N->getOperand(2);
+  unsigned NumElems = Mask.getNumOperands();
+  for (unsigned i = 0; i != NumElems; ++i) {
+    SDOperand Arg = Mask.getOperand(i);
+    if (Arg.getOpcode() != ISD::UNDEF) {
+      unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
+      if (Val < NumElems && V1.getOpcode() != ISD::UNDEF)
+        return false;
+      else if (Val >= NumElems && V2.getOpcode() != ISD::UNDEF)
+        return false;
+    }
+  }
+  return true;
+}
+
 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
 /// that point to V2 points to its first element.
 static SDOperand NormalizeMask(SDOperand Mask, SelectionDAG &DAG) {
@@ -2402,6 +2424,9 @@
   bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
   bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
 
+  if (isUndefShuffle(Op.Val))
+    return DAG.getNode(ISD::UNDEF, VT);
+
   if (isSplatMask(PermMask.Val)) {
     if (NumElems <= 4) return Op;
     // Promote it to a v4i32 splat.
@@ -2422,17 +2447,18 @@
       ShouldXformToMOVLP(V1.Val, PermMask.Val))
     return CommuteVectorShuffle(Op, DAG);
 
-  bool V1IsSplat = isSplatVector(V1.Val) || V1.getOpcode() == ISD::UNDEF;
-  bool V2IsSplat = isSplatVector(V2.Val) || V2.getOpcode() == ISD::UNDEF;
-  if (V1IsSplat && !V2IsSplat) {
+  bool V1IsSplat = isSplatVector(V1.Val);
+  bool V2IsSplat = isSplatVector(V2.Val);
+  if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
     Op = CommuteVectorShuffle(Op, DAG);
     V1 = Op.getOperand(0);
     V2 = Op.getOperand(1);
     PermMask = Op.getOperand(2);
-    V2IsSplat = true;
+    std::swap(V1IsSplat, V2IsSplat);
+    std::swap(V1IsUndef, V2IsUndef);
   }
 
-  if (isCommutedMOVL(PermMask.Val, V2IsSplat)) {
+  if (isCommutedMOVL(PermMask.Val, V2IsSplat, V2IsUndef)) {
     if (V2IsUndef) return V1;
     Op = CommuteVectorShuffle(Op, DAG);
     V1 = Op.getOperand(0);





From evan.cheng at apple.com  Thu Sep  7 20:54:46 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 7 Sep 2006 20:54:46 -0500
Subject: [llvm-commits] CVS:
	llvm/test/Regression/CodeGen/X86/vec_shuffle-8.ll
Message-ID: <200609080154.k881skWv016363@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CodeGen/X86:

vec_shuffle-8.ll added (r1.1)
---
Log message:

Add a new test case for 'undef' shuffles.


---
Diffs of the changes:  (+9 -0)

 vec_shuffle-8.ll |    9 +++++++++
 1 files changed, 9 insertions(+)


Index: llvm/test/Regression/CodeGen/X86/vec_shuffle-8.ll
diff -c /dev/null llvm/test/Regression/CodeGen/X86/vec_shuffle-8.ll:1.1
*** /dev/null	Thu Sep  7 20:54:42 2006
--- llvm/test/Regression/CodeGen/X86/vec_shuffle-8.ll	Thu Sep  7 20:54:32 2006
***************
*** 0 ****
--- 1,9 ----
+ ; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 &&
+ ; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | not grep shufps
+ 
+ void %test(<4 x float>* %res, <4 x float>* %A) {
+ 	%tmp1 = load <4 x float>* %A
+ 	%tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x uint> < uint 0, uint 5, uint 6, uint 7 >
+ 	store <4 x float> %tmp2, <4 x float>* %res
+ 	ret void
+ }





From natebegeman at mac.com  Thu Sep  7 22:42:29 2006
From: natebegeman at mac.com (Nate Begeman)
Date: Thu, 7 Sep 2006 22:42:29 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
Message-ID: <200609080342.k883gTcZ017947@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCTargetMachine.cpp updated: 1.105 -> 1.106
---
Log message:

We actually do support object file writing, so don't return true (error)


---
Diffs of the changes:  (+1 -3)

 PPCTargetMachine.cpp |    4 +---
 1 files changed, 1 insertion(+), 3 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
diff -u llvm/lib/Target/PowerPC/PPCTargetMachine.cpp:1.105 llvm/lib/Target/PowerPC/PPCTargetMachine.cpp:1.106
--- llvm/lib/Target/PowerPC/PPCTargetMachine.cpp:1.105	Thu Sep  7 18:39:26 2006
+++ llvm/lib/Target/PowerPC/PPCTargetMachine.cpp	Thu Sep  7 22:42:15 2006
@@ -130,7 +130,7 @@
                                        std::ostream &Out) {
   // FIXME: support PPC ELF files at some point
   addPPCMachOObjectWriterPass(PM, Out, *this);
-  return true;
+  return false;
 }
 
 bool PPCTargetMachine::addCodeEmitter(FunctionPassManager &PM, bool Fast,
@@ -138,8 +138,6 @@
   // The JIT should use the static relocation model.
   // FIXME: This should be moved to TargetJITInfo!!
   setRelocationModel(Reloc::Static);
-
-  
   
   // Machine code emitter pass for PowerPC.
   PM.add(createPPCCodeEmitterPass(*this, MCE));





From lattner at cs.uiuc.edu  Fri Sep  8 01:19:01 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 8 Sep 2006 01:19:01 -0500
Subject: [llvm-commits] CVS:
	llvm-test/External/SPEC/CINT2006/471.omnetpp/Makefile
Message-ID: <200609080619.k886J1ks020331@zion.cs.uiuc.edu>



Changes in directory llvm-test/External/SPEC/CINT2006/471.omnetpp:

Makefile updated: 1.4 -> 1.5
---
Log message:

bugfixes, allowing this program to find all its sources


---
Diffs of the changes:  (+10 -2)

 Makefile |   12 ++++++++++--
 1 files changed, 10 insertions(+), 2 deletions(-)


Index: llvm-test/External/SPEC/CINT2006/471.omnetpp/Makefile
diff -u llvm-test/External/SPEC/CINT2006/471.omnetpp/Makefile:1.4 llvm-test/External/SPEC/CINT2006/471.omnetpp/Makefile:1.5
--- llvm-test/External/SPEC/CINT2006/471.omnetpp/Makefile:1.4	Thu Sep  7 18:17:18 2006
+++ llvm-test/External/SPEC/CINT2006/471.omnetpp/Makefile	Fri Sep  8 01:18:47 2006
@@ -34,7 +34,9 @@
            chead.cc cnetmod.cc csimul.cc distrib.cc cdetect.cc chist.cc        \
            cobject.cc cstat.cc errmsg.cc cdispstr.cc cksplit.cc coutvect.cc    \
            cstruct.cc onstartup.cc cenum.cc cllist.cc cpacket.cc ctopo.cc      \
-           random.cc std/netpack.cc)
+           random.cc)
+SIMSTDSources := \
+         $(SPEC_BENCH_DIR)/src/libs/sim/std/netpack.cc
 SPECSources   := \
          $(SPEC_BENCH_DIR)/src/libs/spec/spec_qsort.cc
 
@@ -42,6 +44,7 @@
           $(addprefix cmdenv_,$(notdir $(CMDENVSources)))   \
           $(addprefix envir_,$(notdir $(ENVIRSources)))     \
           $(addprefix sim_,$(notdir $(SIMSources)))         \
+          $(addprefix simstd_,$(notdir $(SIMSTDSources)))   \
           $(addprefix spec_,$(notdir $(SPECSources)))
 
 CPPFLAGS += -DNDEBUG=1                            \
@@ -78,7 +81,12 @@
 $(addprefix sim_,$(notdir $(SIMSources))) : sim_% : \
 $(SPEC_BENCH_DIR)/src/libs/sim/%
 	cp $< $@
-$(notdir $(SPECSources)) : % : $(SPEC_BENCH_DIR)/src/libs/spec/%
+$(addprefix simstd_,$(notdir $(SIMSTDSources))) : simstd_% : \
+$(SPEC_BENCH_DIR)/src/libs/sim/std/%
+	cp $< $@
+
+
+$(addprefix spec_,$(notdir $(SPECSources)) ): spec_% : $(SPEC_BENCH_DIR)/src/libs/spec/%
 	cp $< $@
 
 ##===----------------------------------------------------------------------===##





From lattner at cs.uiuc.edu  Fri Sep  8 01:34:16 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 8 Sep 2006 01:34:16 -0500
Subject: [llvm-commits] CVS: llvm/docs/LangRef.html
Message-ID: <200609080634.k886YGG7020589@zion.cs.uiuc.edu>



Changes in directory llvm/docs:

LangRef.html updated: 1.155 -> 1.156
---
Log message:

new powi intrinsic


---
Diffs of the changes:  (+40 -4)

 LangRef.html |   44 ++++++++++++++++++++++++++++++++++++++++----
 1 files changed, 40 insertions(+), 4 deletions(-)


Index: llvm/docs/LangRef.html
diff -u llvm/docs/LangRef.html:1.155 llvm/docs/LangRef.html:1.156
--- llvm/docs/LangRef.html:1.155	Mon Aug 14 19:45:58 2006
+++ llvm/docs/LangRef.html	Fri Sep  8 01:34:02 2006
@@ -156,7 +156,7 @@
           <li><a href="#i_memset">'<tt>llvm.memset.*</tt>' Intrinsic</a></li>
           <li><a href="#i_isunordered">'<tt>llvm.isunordered.*</tt>' Intrinsic</a></li>
           <li><a href="#i_sqrt">'<tt>llvm.sqrt.*</tt>' Intrinsic</a></li>
-
+          <li><a href="#i_powi">'<tt>llvm.powi.*</tt>' Intrinsic</a></li>
         </ol>
       </li>
       <li><a href="#int_manip">Bit Manipulation Intrinsics</a>
@@ -3630,8 +3630,8 @@
 
 <h5>Syntax:</h5>
 <pre>
-  declare double %llvm.sqrt.f32(float Val)
-  declare double %llvm.sqrt.f64(double Val)
+  declare float %llvm.sqrt.f32(float %Val)
+  declare double %llvm.sqrt.f64(double %Val)
 </pre>
 
 <h5>Overview:</h5>
@@ -3657,6 +3657,42 @@
 </p>
 </div>
 
+<!-- _______________________________________________________________________ -->
+<div class="doc_subsubsection">
+  <a name="i_powi">'<tt>llvm.powi.*</tt>' Intrinsic</a>
+</div>
+
+<div class="doc_text">
+
+<h5>Syntax:</h5>
+<pre>
+  declare float  %llvm.powi.f32(float  %Val, int %power)
+  declare double %llvm.powi.f64(double %Val, int %power)
+</pre>
+
+<h5>Overview:</h5>
+
+<p>
+The '<tt>llvm.powi.*</tt>' intrinsics return the first operand raised to the
+specified (positive or negative) power.  The order of evaluation of
+multiplications is not defined.
+</p>
+
+<h5>Arguments:</h5>
+
+<p>
+The second argument is an integer power, and the first is a value to raise to
+that power.
+</p>
+
+<h5>Semantics:</h5>
+
+<p>
+This function returns the first value raised to the second power with an
+unspecified sequence of rounding operations.</p>
+</div>
+
+
 <!-- ======================================================================= -->
 <div class="doc_subsection">
   <a name="int_manip">Bit Manipulation Intrinsics</a>
@@ -3844,7 +3880,7 @@
 
   <a href="mailto:sabre at nondot.org">Chris Lattner</a><br>
   <a href="http://llvm.org">The LLVM Compiler Infrastructure</a><br>
-  Last modified: $Date: 2006/08/15 00:45:58 $
+  Last modified: $Date: 2006/09/08 06:34:02 $
 </address>
 </body>
 </html>





From lattner at cs.uiuc.edu  Fri Sep  8 01:43:14 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 8 Sep 2006 01:43:14 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/Intrinsics.td
Message-ID: <200609080643.k886hEUR020799@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm:

Intrinsics.td updated: 1.34 -> 1.35
---
Log message:

add powi intrinsics.


---
Diffs of the changes:  (+3 -0)

 Intrinsics.td |    3 +++
 1 files changed, 3 insertions(+)


Index: llvm/include/llvm/Intrinsics.td
diff -u llvm/include/llvm/Intrinsics.td:1.34 llvm/include/llvm/Intrinsics.td:1.35
--- llvm/include/llvm/Intrinsics.td:1.34	Thu Apr 13 13:23:48 2006
+++ llvm/include/llvm/Intrinsics.td	Fri Sep  8 01:43:00 2006
@@ -171,6 +171,9 @@
                                        llvm_double_ty, llvm_double_ty]>;
   def int_sqrt_f32 : Intrinsic<[llvm_float_ty , llvm_float_ty]>;
   def int_sqrt_f64 : Intrinsic<[llvm_double_ty, llvm_double_ty]>;
+
+  def int_powi_f32 : Intrinsic<[llvm_float_ty , llvm_float_ty, llvm_int_ty]>;
+  def int_powi_f64 : Intrinsic<[llvm_double_ty, llvm_double_ty, llvm_int_ty]>;
 }
 
 // NOTE: these are internal interfaces.





From evan.cheng at apple.com  Fri Sep  8 01:48:44 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 8 Sep 2006 01:48:44 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/README-X86-64.txt
	X86InstrX86-64.td X86.td X86ATTAsmPrinter.cpp
	X86ATTAsmPrinter.h X86AsmPrinter.cpp X86AsmPrinter.h
	X86CodeEmitter.cpp X86ISelDAGToDAG.cpp X86ISelLowering.cpp
	X86ISelLowering.h X86InstrInfo.cpp X86InstrInfo.h
	X86InstrInfo.td X86IntelAsmPrinter.cpp X86IntelAsmPrinter.h
	X86JITInfo.cpp X86RegisterInfo.cpp X86RegisterInfo.h
	X86RegisterInfo.td X86Subtarget.cpp X86Subtarget.h
	X86TargetAsmInfo.cpp X86TargetMachine.cpp X86TargetMachine.h
Message-ID: <200609080648.k886mi37020938@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

README-X86-64.txt added (r1.1)
X86InstrX86-64.td added (r1.1)
X86.td updated: 1.25 -> 1.26
X86ATTAsmPrinter.cpp updated: 1.60 -> 1.61
X86ATTAsmPrinter.h updated: 1.15 -> 1.16
X86AsmPrinter.cpp updated: 1.195 -> 1.196
X86AsmPrinter.h updated: 1.29 -> 1.30
X86CodeEmitter.cpp updated: 1.118 -> 1.119
X86ISelDAGToDAG.cpp updated: 1.104 -> 1.105
X86ISelLowering.cpp updated: 1.252 -> 1.253
X86ISelLowering.h updated: 1.70 -> 1.71
X86InstrInfo.cpp updated: 1.59 -> 1.60
X86InstrInfo.h updated: 1.53 -> 1.54
X86InstrInfo.td updated: 1.284 -> 1.285
X86IntelAsmPrinter.cpp updated: 1.54 -> 1.55
X86IntelAsmPrinter.h updated: 1.23 -> 1.24
X86JITInfo.cpp updated: 1.25 -> 1.26
X86RegisterInfo.cpp updated: 1.167 -> 1.168
X86RegisterInfo.h updated: 1.40 -> 1.41
X86RegisterInfo.td updated: 1.38 -> 1.39
X86Subtarget.cpp updated: 1.30 -> 1.31
X86Subtarget.h updated: 1.15 -> 1.16
X86TargetAsmInfo.cpp updated: 1.1 -> 1.2
X86TargetMachine.cpp updated: 1.126 -> 1.127
X86TargetMachine.h updated: 1.40 -> 1.41
---
Log message:

Committing X86-64 support.

---
Diffs of the changes:  (+3603 -462)

 README-X86-64.txt      |  269 ++++++++++++
 X86.td                 |   14 
 X86ATTAsmPrinter.cpp   |  107 ++--
 X86ATTAsmPrinter.h     |    6 
 X86AsmPrinter.cpp      |    6 
 X86AsmPrinter.h        |   11 
 X86CodeEmitter.cpp     |  350 +++++++++++++--
 X86ISelDAGToDAG.cpp    |  166 +++++--
 X86ISelLowering.cpp    |  849 ++++++++++++++++++++++++++++++++++----
 X86ISelLowering.h      |   10 
 X86InstrInfo.cpp       |   18 
 X86InstrInfo.h         |   33 +
 X86InstrInfo.td        |   94 ++--
 X86InstrX86-64.td      | 1084 +++++++++++++++++++++++++++++++++++++++++++++++++
 X86IntelAsmPrinter.cpp |   30 -
 X86IntelAsmPrinter.h   |    7 
 X86JITInfo.cpp         |   79 +++
 X86RegisterInfo.cpp    |  388 ++++++++++++++---
 X86RegisterInfo.h      |   18 
 X86RegisterInfo.td     |  377 ++++++++++++++---
 X86Subtarget.cpp       |   47 +-
 X86Subtarget.h         |   13 
 X86TargetAsmInfo.cpp   |    5 
 X86TargetMachine.cpp   |   60 ++
 X86TargetMachine.h     |   24 +
 25 files changed, 3603 insertions(+), 462 deletions(-)


Index: llvm/lib/Target/X86/README-X86-64.txt
diff -c /dev/null llvm/lib/Target/X86/README-X86-64.txt:1.1
*** /dev/null	Fri Sep  8 01:48:39 2006
--- llvm/lib/Target/X86/README-X86-64.txt	Fri Sep  8 01:48:29 2006
***************
*** 0 ****
--- 1,269 ----
+ //===- README_X86_64.txt - Notes for X86-64 code gen ----------------------===//
+ 
+ Implement different PIC models? Right now we only support Mac OS X with small
+ PIC code model.
+ 
+ //===---------------------------------------------------------------------===//
+ 
+ Make use of "Red Zone".
+ 
+ //===---------------------------------------------------------------------===//
+ 
+ Implement __int128 and long double support.
+ 
+ //===---------------------------------------------------------------------===//
+ 
+ For this:
+ 
+ extern void xx(void);
+ void bar(void) {
+   xx();
+ }
+ 
+ gcc compiles to:
+ 
+ .globl _bar
+ _bar:
+ 	jmp	_xx
+ 
+ We need to do the tailcall optimization as well.
+ 
+ //===---------------------------------------------------------------------===//
+ 
+ For this:
+ 
+ int test(int a)
+ {
+   return a * 3;
+ }
+ 
+ We generates
+ 	leal (%edi,%edi,2), %eax
+ 
+ We should be generating 
+ 	leal (%rdi,%rdi,2), %eax
+ 
+ instead. The later form does not require an address-size prefix 67H.
+ 
+ It's probably ok to simply emit the corresponding 64-bit super class registers
+ in this case?
+ 
+ 
+ //===---------------------------------------------------------------------===//
+ 
+ AMD64 Optimization Manual 8.2 has some nice information about optimizing integer
+ multiplication by a constant. How much of it applies to Intel's X86-64
+ implementation? There are definite trade-offs to consider: latency vs. register
+ pressure vs. code size.
+ 
+ //===---------------------------------------------------------------------===//
+ 
+ Are we better off using branches instead of cmove to implement FP to
+ unsigned i64?
+ 
+ _conv:
+ 	ucomiss	LC0(%rip), %xmm0
+ 	cvttss2siq	%xmm0, %rdx
+ 	jb	L3
+ 	subss	LC0(%rip), %xmm0
+ 	movabsq	$-9223372036854775808, %rax
+ 	cvttss2siq	%xmm0, %rdx
+ 	xorq	%rax, %rdx
+ L3:
+ 	movq	%rdx, %rax
+ 	ret
+ 
+ instead of
+ 
+ _conv:
+ 	movss LCPI1_0(%rip), %xmm1
+ 	cvttss2siq %xmm0, %rcx
+ 	movaps %xmm0, %xmm2
+ 	subss %xmm1, %xmm2
+ 	cvttss2siq %xmm2, %rax
+ 	movabsq $-9223372036854775808, %rdx
+ 	xorq %rdx, %rax
+ 	ucomiss %xmm1, %xmm0
+ 	cmovb %rcx, %rax
+ 	ret
+ 
+ Seems like the jb branch has high likelyhood of being taken. It would have
+ saved a few instructions.
+ 
+ //===---------------------------------------------------------------------===//
+ 
+ Poor codegen:
+ 
+ int X[2];
+ int b;
+ void test(void) {
+   memset(X, b, 2*sizeof(X[0]));
+ }
+ 
+ llc:
+ 	movq _b at GOTPCREL(%rip), %rax
+ 	movzbq (%rax), %rax
+ 	movq %rax, %rcx
+ 	shlq $8, %rcx
+ 	orq %rax, %rcx
+ 	movq %rcx, %rax
+ 	shlq $16, %rax
+ 	orq %rcx, %rax
+ 	movq %rax, %rcx
+ 	shlq $32, %rcx
+ 	movq _X at GOTPCREL(%rip), %rdx
+ 	orq %rax, %rcx
+ 	movq %rcx, (%rdx)
+ 	ret
+ 
+ gcc:
+ 	movq	_b at GOTPCREL(%rip), %rax
+ 	movabsq	$72340172838076673, %rdx
+ 	movzbq	(%rax), %rax
+ 	imulq	%rdx, %rax
+ 	movq	_X at GOTPCREL(%rip), %rdx
+ 	movq	%rax, (%rdx)
+ 	ret
+ 
+ //===---------------------------------------------------------------------===//
+ 
+ Vararg function prologue can be further optimized. Currently all XMM registers
+ are stored into register save area. Most of them can be eliminated since the
+ upper bound of the number of XMM registers used are passed in %al. gcc produces
+ something like the following:
+ 
+ 	movzbl	%al, %edx
+ 	leaq	0(,%rdx,4), %rax
+ 	leaq	4+L2(%rip), %rdx
+ 	leaq	239(%rsp), %rax
+        	jmp	*%rdx
+ 	movaps	%xmm7, -15(%rax)
+ 	movaps	%xmm6, -31(%rax)
+ 	movaps	%xmm5, -47(%rax)
+ 	movaps	%xmm4, -63(%rax)
+ 	movaps	%xmm3, -79(%rax)
+ 	movaps	%xmm2, -95(%rax)
+ 	movaps	%xmm1, -111(%rax)
+ 	movaps	%xmm0, -127(%rax)
+ L2:
+ 
+ It jumps over the movaps that do not need to be stored. Hard to see this being
+ significant as it added 5 instruciton (including a indirect branch) to avoid
+ executing 0 to 8 stores in the function prologue.
+ 
+ Perhaps we can optimize for the common case where no XMM registers are used for
+ parameter passing. i.e. is %al == 0 jump over all stores. Or in the case of a
+ leaf function where we can determine that no XMM input parameter is need, avoid
+ emitting the stores at all.
+ 
+ //===---------------------------------------------------------------------===//
+ 
+ AMD64 has a complex calling convention for aggregate passing by value:
+ 
+ 1. If the size of an object is larger than two eightbytes, or in C++, is a non- 
+    POD structure or union type, or contains unaligned fields, it has class 
+    MEMORY.
+ 2. Both eightbytes get initialized to class NO_CLASS. 
+ 3. Each field of an object is classified recursively so that always two fields
+    are considered. The resulting class is calculated according to the classes
+    of the fields in the eightbyte: 
+    (a) If both classes are equal, this is the resulting class. 
+    (b) If one of the classes is NO_CLASS, the resulting class is the other 
+        class. 
+    (c) If one of the classes is MEMORY, the result is the MEMORY class. 
+    (d) If one of the classes is INTEGER, the result is the INTEGER. 
+    (e) If one of the classes is X87, X87UP, COMPLEX_X87 class, MEMORY is used as
+       class. 
+    (f) Otherwise class SSE is used. 
+ 4. Then a post merger cleanup is done: 
+    (a) If one of the classes is MEMORY, the whole argument is passed in memory. 
+    (b) If SSEUP is not preceeded by SSE, it is converted to SSE.
+ 
+ Currently llvm frontend does not handle this correctly.
+ 
+ Problem 1:
+     typedef struct { int i; double d; } QuadWordS;
+ It is currently passed in two i64 integer registers. However, gcc compiled
+ callee expects the second element 'd' to be passed in XMM0.
+ 
+ Problem 2:
+     typedef struct { int32_t i; float j; double d; } QuadWordS;
+ The size of the first two fields == i64 so they will be combined and passed in
+ a integer register RDI. The third field is still passed in XMM0.
+ 
+ Problem 3:
+     typedef struct { int64_t i; int8_t j; int64_t d; } S;
+     void test(S s)
+ The size of this aggregate is greater than two i64 so it should be passed in 
+ memory. Currently llvm breaks this down and passed it in three integer
+ registers.
+ 
+ Problem 4:
+ Taking problem 3 one step ahead where a function expects a aggregate value
+ in memory followed by more parameter(s) passed in register(s).
+     void test(S s, int b)
+ 
+ LLVM IR does not allow parameter passing by aggregates, therefore it must break
+ the aggregates value (in problem 3 and 4) into a number of scalar values:
+     void %test(long %s.i, byte %s.j, long %s.d);
+ 
+ However, if the backend were to lower this code literally it would pass the 3
+ values in integer registers. To force it be passed in memory, the frontend
+ should change the function signiture to:
+     void %test(long %undef1, long %undef2, long %undef3, long %undef4, 
+                long %undef5, long %undef6,
+                long %s.i, byte %s.j, long %s.d);
+ And the callee would look something like this:
+     call void %test( undef, undef, undef, undef, undef, undef,
+                      %tmp.s.i, %tmp.s.j, %tmp.s.d );
+ The first 6 undef parameters would exhaust the 6 integer registers used for
+ parameter passing. The following three integer values would then be forced into
+ memory.
+ 
+ For problem 4, the parameter 'd' would be moved to the front of the parameter
+ list so it will be passed in register:
+     void %test(int %d,
+                long %undef1, long %undef2, long %undef3, long %undef4, 
+                long %undef5, long %undef6,
+                long %s.i, byte %s.j, long %s.d);
+ 
+ //===---------------------------------------------------------------------===//
+ 
+ For this:
+ 
+ extern int dst[]; 
+ extern int* ptr; 
+ 
+ void test(void) {
+   ptr = dst;
+ }
+ 
+ We generate this code for static relocation model:
+ 
+ _test:
+ 	leaq _dst(%rip), %rax
+ 	movq %rax, _ptr(%rip)
+ 	ret
+ 
+ If we are in small code model, they we can treat _dst as a 32-bit constant.
+         movq $_dst, _ptr(%rip)
+ 
+ Note, however, we should continue to use RIP relative addressing mode as much as
+ possible. The above is actually one byte shorter than
+         movq $_dst, _ptr
+ 
+ //===---------------------------------------------------------------------===//
+ 
+ Right now the asm printer assumes GlobalAddress are accessed via RIP relative
+ addressing. Therefore, it is not possible to generate this:
+         movabsq $__ZTV10polynomialIdE+16, %rax
+ 
+ That is ok for now since we currently only support small model. So the above
+ is selected as
+         leaq __ZTV10polynomialIdE+16(%rip), %rax
+ 
+ This is probably slightly slower but is much shorter than movabsq. However, if
+ we were to support medium or larger code models, we need to use the movabs
+ instruction. We should probably introduce something like AbsoluteAddress to
+ distinguish it from GlobalAddress so the asm printer and JIT code emitter can
+ do the right thing.


Index: llvm/lib/Target/X86/X86InstrX86-64.td
diff -c /dev/null llvm/lib/Target/X86/X86InstrX86-64.td:1.1
*** /dev/null	Fri Sep  8 01:48:43 2006
--- llvm/lib/Target/X86/X86InstrX86-64.td	Fri Sep  8 01:48:29 2006
***************
*** 0 ****
--- 1,1084 ----
+ //====- X86InstrX86-64.td - Describe the X86 Instruction Set ----*- C++ -*-===//
+ // 
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by the Evan Cheng and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ // 
+ //===----------------------------------------------------------------------===//
+ //
+ // This file describes the X86-64 instruction set, defining the instructions,
+ // and properties of the instructions which are needed for code generation,
+ // machine code emission, and analysis.
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ //===----------------------------------------------------------------------===//
+ // Operand Definitions...
+ //
+ 
+ // 64-bits but only 32 bits are significant.
+ def i64i32imm  : Operand<i64>;
+ // 64-bits but only 8 bits are significant.
+ def i64i8imm   : Operand<i64>;
+ 
+ def lea64mem : Operand<i64> {
+   let PrintMethod = "printi64mem";
+   let NumMIOperands = 4;
+   let MIOperandInfo = (ops GR64, i8imm, GR64, i32imm);
+ }
+ 
+ def lea64_32mem : Operand<i32> {
+   let PrintMethod = "printlea64_32mem";
+   let NumMIOperands = 4;
+   let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
+ }
+ 
+ //===----------------------------------------------------------------------===//
+ // Complex Pattern Definitions...
+ //
+ def lea64addr : ComplexPattern<i64, 4, "SelectLEAAddr",
+                                [add, mul, shl, or, frameindex, X86Wrapper]>;
+ 
+ //===----------------------------------------------------------------------===//
+ // Instruction templates...
+ //
+ 
+ class RI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
+       : I<o, F, ops, asm, pattern>, REX_W;
+ class RIi8 <bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
+       : Ii8<o, F, ops, asm, pattern>, REX_W;
+ class RIi32 <bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
+       : Ii32<o, F, ops, asm, pattern>, REX_W;
+ 
+ class RIi64<bits<8> o, Format f, dag ops, string asm, list<dag> pattern>
+   : X86Inst<o, f, Imm64, ops, asm>, REX_W {
+   let Pattern = pattern;
+   let CodeSize = 3;
+ }
+ 
+ class RSSI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
+       : SSI<o, F, ops, asm, pattern>, REX_W;
+ class RSDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
+       : SDI<o, F, ops, asm, pattern>, REX_W;
+ 
+ //===----------------------------------------------------------------------===//
+ // Pattern fragments...
+ //
+ 
+ def i64immSExt32  : PatLeaf<(i64 imm), [{
+   // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
+   // sign extended field.
+   return (int64_t)N->getValue() == (int32_t)N->getValue();
+ }]>;
+ 
+ def i64immZExt32  : PatLeaf<(i64 imm), [{
+   // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
+   // unsignedsign extended field.
+   return (uint64_t)N->getValue() == (uint32_t)N->getValue();
+ }]>;
+ 
+ def i64immSExt8  : PatLeaf<(i64 imm), [{
+   // i64immSExt8 predicate - True if the 64-bit immediate fits in a 8-bit
+   // sign extended field.
+   return (int64_t)N->getValue() == (int8_t)N->getValue();
+ }]>;
+ 
+ def sextloadi64i1  : PatFrag<(ops node:$ptr), (i64 (sextload node:$ptr, i1))>;
+ def sextloadi64i8  : PatFrag<(ops node:$ptr), (i64 (sextload node:$ptr, i8))>;
+ def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextload node:$ptr, i16))>;
+ def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextload node:$ptr, i32))>;
+ 
+ def zextloadi64i1  : PatFrag<(ops node:$ptr), (i64 (zextload node:$ptr, i1))>;
+ def zextloadi64i8  : PatFrag<(ops node:$ptr), (i64 (zextload node:$ptr, i8))>;
+ def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextload node:$ptr, i16))>;
+ def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextload node:$ptr, i32))>;
+ 
+ def extloadi64i1   : PatFrag<(ops node:$ptr), (i64 (extload node:$ptr, i1))>;
+ def extloadi64i8   : PatFrag<(ops node:$ptr), (i64 (extload node:$ptr, i8))>;
+ def extloadi64i16  : PatFrag<(ops node:$ptr), (i64 (extload node:$ptr, i16))>;
+ def extloadi64i32  : PatFrag<(ops node:$ptr), (i64 (extload node:$ptr, i32))>;
+ 
+ //===----------------------------------------------------------------------===//
+ // Instruction list...
+ //
+ 
+ def IMPLICIT_DEF_GR64  : I<0, Pseudo, (ops GR64:$dst),
+                          "#IMPLICIT_DEF $dst",
+                          [(set GR64:$dst, (undef))]>;
+ 
+ //===----------------------------------------------------------------------===//
+ //  Call Instructions...
+ //
+ let isCall = 1, noResults = 1 in
+   // All calls clobber the non-callee saved registers...
+   let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
+               FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
+               XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
+               XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15] in {
+     def CALL64pcrel32 : I<0xE8, RawFrm, (ops i64imm:$dst, variable_ops),
+                           "call ${dst:call}", []>;
+     def CALL64r       : I<0xFF, MRM2r, (ops GR64:$dst, variable_ops),
+                           "call {*}$dst", [(X86call GR64:$dst)]>;
+     def CALL64m       : I<0xFF, MRM2m, (ops i64mem:$dst, variable_ops),
+                           "call {*}$dst", []>;
+   }
+ 
+ // Branches
+ let isBranch = 1, isTerminator = 1, noResults = 1, isBarrier = 1 in {
+   def JMP64r     : I<0xFF, MRM4r, (ops GR64:$dst), "jmp{q} {*}$dst",
+                      [(brind GR64:$dst)]>;
+   def JMP64m     : I<0xFF, MRM4m, (ops i64mem:$dst), "jmp{q} {*}$dst",
+                      [(brind (loadi64 addr:$dst))]>;
+ }
+ 
+ //===----------------------------------------------------------------------===//
+ //  Miscellaneous Instructions...
+ //
+ def LEAVE64  : I<0xC9, RawFrm,
+                  (ops), "leave", []>, Imp<[RBP,RSP],[RBP,RSP]>;
+ def POP64r   : I<0x58, AddRegFrm,
+                  (ops GR64:$reg), "pop{q} $reg", []>, Imp<[RSP],[RSP]>;
+ 
+ def LEA64_32r : I<0x8D, MRMSrcMem,
+                   (ops GR32:$dst, lea64_32mem:$src),
+                   "lea{l} {$src|$dst}, {$dst|$src}",
+                   [(set GR32:$dst, lea32addr:$src)]>, Requires<[In64BitMode]>;
+ 
+ def LEA64r   : RI<0x8D, MRMSrcMem, (ops GR64:$dst, lea64mem:$src),
+                   "lea{q} {$src|$dst}, {$dst|$src}",
+                   [(set GR64:$dst, lea64addr:$src)]>;
+ 
+ let isTwoAddress = 1 in
+ def BSWAP64r : RI<0xC8, AddRegFrm, (ops GR64:$dst, GR64:$src),
+                   "bswap{q} $dst", 
+                   [(set GR64:$dst, (bswap GR64:$src))]>, TB;
+ // Exchange
+ def XCHG64rr : RI<0x87, MRMDestReg, (ops GR64:$src1, GR64:$src2),
+                   "xchg{q} {$src2|$src1}, {$src1|$src2}", []>;
+ def XCHG64mr : RI<0x87, MRMDestMem, (ops i64mem:$src1, GR64:$src2),
+                   "xchg{q} {$src2|$src1}, {$src1|$src2}", []>;
+ def XCHG64rm : RI<0x87, MRMSrcMem, (ops GR64:$src1, i64mem:$src2),
+                   "xchg{q} {$src2|$src1}, {$src1|$src2}", []>;
+ 
+ // Repeat string ops
+ def REP_MOVSQ : RI<0xA5, RawFrm, (ops), "{rep;movsq|rep movsq}",
+                    [(X86rep_movs i64)]>,
+                 Imp<[RCX,RDI,RSI], [RCX,RDI,RSI]>, REP;
+ def REP_STOSQ : RI<0xAB, RawFrm, (ops), "{rep;stosq|rep stosq}",
+                    [(X86rep_stos i64)]>,
+                 Imp<[RAX,RCX,RDI], [RCX,RDI]>, REP;
+ 
+ //===----------------------------------------------------------------------===//
+ //  Move Instructions...
+ //
+ 
+ def MOV64rr : RI<0x89, MRMDestReg, (ops GR64:$dst, GR64:$src),
+                  "mov{q} {$src, $dst|$dst, $src}", []>;
+ 
+ def MOV64ri : RIi64<0xB8, AddRegFrm, (ops GR64:$dst, i64imm:$src),
+                     "movabs{q} {$src, $dst|$dst, $src}",
+                     [(set GR64:$dst, imm:$src)]>;
+ def MOV64ri32 : RIi32<0xC7, MRM0r, (ops GR64:$dst, i64i32imm:$src),
+                       "mov{q} {$src, $dst|$dst, $src}",
+                       [(set GR64:$dst, i64immSExt32:$src)]>;
+ 
+ def MOV64rm : RI<0x8B, MRMSrcMem, (ops GR64:$dst, i64mem:$src),
+                  "mov{q} {$src, $dst|$dst, $src}",
+                  [(set GR64:$dst, (load addr:$src))]>;
+ 
+ def MOV64mr : RI<0x89, MRMDestMem, (ops i64mem:$dst, GR64:$src),
+                  "mov{q} {$src, $dst|$dst, $src}",
+                  [(store GR64:$src, addr:$dst)]>;
+ def MOV64mi32 : RIi32<0xC7, MRM0m, (ops i64mem:$dst, i64i32imm:$src),
+                       "mov{q} {$src, $dst|$dst, $src}",
+                       [(store i64immSExt32:$src, addr:$dst)]>;
+ 
+ // Sign/Zero extenders
+ 
+ def MOVSX64rr8 : RI<0xBE, MRMSrcReg, (ops GR64:$dst, GR8 :$src),
+                     "movs{bq|x} {$src, $dst|$dst, $src}",
+                     [(set GR64:$dst, (sext GR8:$src))]>, TB;
+ def MOVSX64rm8 : RI<0xBE, MRMSrcMem, (ops GR64:$dst, i8mem :$src),
+                     "movs{bq|x} {$src, $dst|$dst, $src}",
+                     [(set GR64:$dst, (sextloadi64i8 addr:$src))]>, TB;
+ def MOVSX64rr16: RI<0xBF, MRMSrcReg, (ops GR64:$dst, GR16:$src),
+                     "movs{wq|x} {$src, $dst|$dst, $src}",
+                     [(set GR64:$dst, (sext GR16:$src))]>, TB;
+ def MOVSX64rm16: RI<0xBF, MRMSrcMem, (ops GR64:$dst, i16mem:$src),
+                     "movs{wq|x} {$src, $dst|$dst, $src}",
+                     [(set GR64:$dst, (sextloadi64i16 addr:$src))]>, TB;
+ def MOVSX64rr32: RI<0x63, MRMSrcReg, (ops GR64:$dst, GR32:$src),
+                     "movs{lq|xd} {$src, $dst|$dst, $src}",
+                     [(set GR64:$dst, (sext GR32:$src))]>;
+ def MOVSX64rm32: RI<0x63, MRMSrcMem, (ops GR64:$dst, i32mem:$src),
+                     "movs{lq|xd} {$src, $dst|$dst, $src}",
+                     [(set GR64:$dst, (sextloadi64i32 addr:$src))]>;
+ 
+ def MOVZX64rr8 : RI<0xB6, MRMSrcReg, (ops GR64:$dst, GR8 :$src),
+                     "movz{bq|x} {$src, $dst|$dst, $src}",
+                     [(set GR64:$dst, (zext GR8:$src))]>, TB;
+ def MOVZX64rm8 : RI<0xB6, MRMSrcMem, (ops GR64:$dst, i8mem :$src),
+                     "movz{bq|x} {$src, $dst|$dst, $src}",
+                     [(set GR64:$dst, (zextloadi64i8 addr:$src))]>, TB;
+ def MOVZX64rr16: RI<0xB7, MRMSrcReg, (ops GR64:$dst, GR16:$src),
+                     "movz{wq|x} {$src, $dst|$dst, $src}",
+                     [(set GR64:$dst, (zext GR16:$src))]>, TB;
+ def MOVZX64rm16: RI<0xB7, MRMSrcMem, (ops GR64:$dst, i16mem:$src),
+                     "movz{wq|x} {$src, $dst|$dst, $src}",
+                     [(set GR64:$dst, (zextloadi64i16 addr:$src))]>, TB;
+ 
+ def CDQE : RI<0x98, RawFrm, (ops),
+              "{cltq|cdqe}", []>, Imp<[EAX],[RAX]>;     // RAX = signext(EAX)
+ 
+ def CQO  : RI<0x99, RawFrm, (ops),
+               "{cqto|cqo}", []>, Imp<[RAX],[RAX,RDX]>; // RDX:RAX = signext(RAX)
+ 
+ //===----------------------------------------------------------------------===//
+ //  Arithmetic Instructions...
+ //
+ 
+ let isTwoAddress = 1 in {
+ let isConvertibleToThreeAddress = 1 in {
+ let isCommutable = 1 in
+ def ADD64rr  : RI<0x01, MRMDestReg, (ops GR64:$dst, GR64:$src1, GR64:$src2),
+                   "add{q} {$src2, $dst|$dst, $src2}",
+                   [(set GR64:$dst, (add GR64:$src1, GR64:$src2))]>;
+ 
+ def ADD64ri32 : RIi32<0x81, MRM0r, (ops GR64:$dst, GR64:$src1, i64i32imm:$src2),
+                       "add{q} {$src2, $dst|$dst, $src2}",
+                       [(set GR64:$dst, (add GR64:$src1, i64immSExt32:$src2))]>;
+ def ADD64ri8 : RIi8<0x83, MRM0r, (ops GR64:$dst, GR64:$src1, i64i8imm:$src2),
+                     "add{q} {$src2, $dst|$dst, $src2}",
+                     [(set GR64:$dst, (add GR64:$src1, i64immSExt8:$src2))]>;
+ } // isConvertibleToThreeAddress
+ 
+ def ADD64rm  : RI<0x03, MRMSrcMem, (ops GR64:$dst, GR64:$src1, i64mem:$src2),
+                   "add{q} {$src2, $dst|$dst, $src2}",
+                   [(set GR64:$dst, (add GR64:$src1, (load addr:$src2)))]>;
+ } // isTwoAddress
+ 
+ def ADD64mr  : RI<0x01, MRMDestMem, (ops i64mem:$dst, GR64:$src2),
+                   "add{q} {$src2, $dst|$dst, $src2}",
+                   [(store (add (load addr:$dst), GR64:$src2), addr:$dst)]>;
+ def ADD64mi32 : RIi32<0x81, MRM0m, (ops i64mem:$dst, i64i32imm :$src2),
+                       "add{q} {$src2, $dst|$dst, $src2}",
+                [(store (add (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>;
+ def ADD64mi8 : RIi8<0x83, MRM0m, (ops i64mem:$dst, i64i8imm :$src2),
+                     "add{q} {$src2, $dst|$dst, $src2}",
+                 [(store (add (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
+ 
+ let isTwoAddress = 1 in {
+ let isCommutable = 1 in
+ def ADC64rr  : RI<0x11, MRMDestReg, (ops GR64:$dst, GR64:$src1, GR64:$src2),
+                   "adc{q} {$src2, $dst|$dst, $src2}",
+                   [(set GR64:$dst, (adde GR64:$src1, GR64:$src2))]>;
+ 
+ def ADC64rm  : RI<0x13, MRMSrcMem , (ops GR64:$dst, GR64:$src1, i64mem:$src2),
+                   "adc{q} {$src2, $dst|$dst, $src2}",
+                   [(set GR64:$dst, (adde GR64:$src1, (load addr:$src2)))]>;
+ 
+ def ADC64ri32 : RIi32<0x81, MRM2r, (ops GR64:$dst, GR64:$src1, i64i32imm:$src2),
+                       "adc{q} {$src2, $dst|$dst, $src2}",
+                       [(set GR64:$dst, (adde GR64:$src1, i64immSExt32:$src2))]>;
+ def ADC64ri8 : RIi8<0x83, MRM2r, (ops GR64:$dst, GR64:$src1, i64i8imm:$src2),
+                     "adc{q} {$src2, $dst|$dst, $src2}",
+                     [(set GR64:$dst, (adde GR64:$src1, i64immSExt8:$src2))]>;
+ } // isTwoAddress
+ 
+ def ADC64mr  : RI<0x11, MRMDestMem, (ops i64mem:$dst, GR64:$src2),
+                   "adc{q} {$src2, $dst|$dst, $src2}",
+                   [(store (adde (load addr:$dst), GR64:$src2), addr:$dst)]>;
+ def ADC64mi32 : RIi32<0x81, MRM2m, (ops i64mem:$dst, i64i32imm:$src2),
+                       "adc{q} {$src2, $dst|$dst, $src2}",
+                [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
+ def ADC64mi8 : RIi8<0x83, MRM2m, (ops i64mem:$dst, i64i8imm :$src2),
+                     "adc{q} {$src2, $dst|$dst, $src2}",
+                [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
+ 
+ let isTwoAddress = 1 in {
+ def SUB64rr  : RI<0x29, MRMDestReg, (ops GR64:$dst, GR64:$src1, GR64:$src2),
+                   "sub{q} {$src2, $dst|$dst, $src2}",
+                   [(set GR64:$dst, (sub GR64:$src1, GR64:$src2))]>;
+ 
+ def SUB64rm  : RI<0x2B, MRMSrcMem, (ops GR64:$dst, GR64:$src1, i64mem:$src2),
+                   "sub{q} {$src2, $dst|$dst, $src2}",
+                   [(set GR64:$dst, (sub GR64:$src1, (load addr:$src2)))]>;
+ 
+ def SUB64ri32 : RIi32<0x81, MRM5r, (ops GR64:$dst, GR64:$src1, i64i32imm:$src2),
+                       "sub{q} {$src2, $dst|$dst, $src2}",
+                       [(set GR64:$dst, (sub GR64:$src1, i64immSExt32:$src2))]>;
+ def SUB64ri8 : RIi8<0x83, MRM5r, (ops GR64:$dst, GR64:$src1, i64i8imm:$src2),
+                     "sub{q} {$src2, $dst|$dst, $src2}",
+                     [(set GR64:$dst, (sub GR64:$src1, i64immSExt8:$src2))]>;
+ } // isTwoAddress
+ 
+ def SUB64mr  : RI<0x29, MRMDestMem, (ops i64mem:$dst, GR64:$src2), 
+                   "sub{q} {$src2, $dst|$dst, $src2}",
+                   [(store (sub (load addr:$dst), GR64:$src2), addr:$dst)]>;
+ def SUB64mi32 : RIi32<0x81, MRM5m, (ops i64mem:$dst, i64i32imm:$src2), 
+                       "sub{q} {$src2, $dst|$dst, $src2}",
+                [(store (sub (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>;
+ def SUB64mi8 : RIi8<0x83, MRM5m, (ops i64mem:$dst, i64i8imm :$src2), 
+                     "sub{q} {$src2, $dst|$dst, $src2}",
+                 [(store (sub (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
+ 
+ let isTwoAddress = 1 in {
+ def SBB64rr    : RI<0x19, MRMDestReg, (ops GR64:$dst, GR64:$src1, GR64:$src2),
+                     "sbb{q} {$src2, $dst|$dst, $src2}",
+                     [(set GR64:$dst, (sube GR64:$src1, GR64:$src2))]>;
+ 
+ def SBB64rm  : RI<0x1B, MRMSrcMem, (ops GR64:$dst, GR64:$src1, i64mem:$src2),
+                   "sbb{q} {$src2, $dst|$dst, $src2}",
+                   [(set GR64:$dst, (sube GR64:$src1, (load addr:$src2)))]>;
+ 
+ def SBB64ri32 : RIi32<0x81, MRM3r, (ops GR64:$dst, GR64:$src1, i64i32imm:$src2),
+                       "sbb{q} {$src2, $dst|$dst, $src2}",
+                       [(set GR64:$dst, (sube GR64:$src1, i64immSExt32:$src2))]>;
+ def SBB64ri8 : RIi8<0x83, MRM3r, (ops GR64:$dst, GR64:$src1, i64i8imm:$src2),
+                     "sbb{q} {$src2, $dst|$dst, $src2}",
+                     [(set GR64:$dst, (sube GR64:$src1, i64immSExt8:$src2))]>;
+ } // isTwoAddress
+ 
+ def SBB64mr  : RI<0x19, MRMDestMem, (ops i64mem:$dst, GR64:$src2), 
+                   "sbb{q} {$src2, $dst|$dst, $src2}",
+                   [(store (sube (load addr:$dst), GR64:$src2), addr:$dst)]>;
+ def SBB64mi32 : RIi32<0x81, MRM3m, (ops i64mem:$dst, i64i32imm:$src2), 
+                       "sbb{q} {$src2, $dst|$dst, $src2}",
+               [(store (sube (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>;
+ def SBB64mi8 : RIi8<0x83, MRM3m, (ops i64mem:$dst, i64i8imm :$src2), 
+                     "sbb{q} {$src2, $dst|$dst, $src2}",
+                [(store (sube (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
+ 
+ // Unsigned multiplication
+ def MUL64r : RI<0xF7, MRM4r, (ops GR64:$src),
+                 "mul{q} $src", []>,
+              Imp<[RAX],[RAX,RDX]>;         // RAX,RDX = RAX*GR64
+ def MUL64m : RI<0xF7, MRM4m, (ops i64mem:$src),
+                 "mul{q} $src", []>,
+              Imp<[RAX],[RAX,RDX]>;         // RAX,RDX = RAX*[mem64]
+ 
+ // Signed multiplication
+ def IMUL64r : RI<0xF7, MRM5r, (ops GR64:$src),
+                  "imul{q} $src", []>,
+               Imp<[RAX],[RAX,RDX]>;         // RAX,RDX = RAX*GR64
+ def IMUL64m : RI<0xF7, MRM5m, (ops i64mem:$src),
+                  "imul{q} $src", []>,
+               Imp<[RAX],[RAX,RDX]>;         // RAX,RDX = RAX*[mem64]
+ 
+ let isTwoAddress = 1 in {
+ let isCommutable = 1 in
+ def IMUL64rr : RI<0xAF, MRMSrcReg, (ops GR64:$dst, GR64:$src1, GR64:$src2),
+                   "imul{q} {$src2, $dst|$dst, $src2}",
+                   [(set GR64:$dst, (mul GR64:$src1, GR64:$src2))]>, TB;
+ 
+ def IMUL64rm : RI<0xAF, MRMSrcMem, (ops GR64:$dst, GR64:$src1, i64mem:$src2),
+                   "imul{q} {$src2, $dst|$dst, $src2}",
+                  [(set GR64:$dst, (mul GR64:$src1, (load addr:$src2)))]>, TB;
+ } // isTwoAddress
+ 
+ // Suprisingly enough, these are not two address instructions!
+ def IMUL64rri32 : RIi32<0x69, MRMSrcReg,                    // GR64 = GR64*I32
+                         (ops GR64:$dst, GR64:$src1, i64i32imm:$src2),
+                         "imul{q} {$src2, $src1, $dst|$dst, $src1, $src2}",
+                        [(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2))]>;
+ def IMUL64rri8 : RIi8<0x6B, MRMSrcReg,                      // GR64 = GR64*I8
+                       (ops GR64:$dst, GR64:$src1, i64i8imm:$src2),
+                       "imul{q} {$src2, $src1, $dst|$dst, $src1, $src2}",
+                       [(set GR64:$dst, (mul GR64:$src1, i64immSExt8:$src2))]>;
+ def IMUL64rmi32 : RIi32<0x69, MRMSrcMem,                   // GR64 = [mem64]*I32
+                         (ops GR64:$dst, i64mem:$src1, i64i32imm:$src2),
+                         "imul{q} {$src2, $src1, $dst|$dst, $src1, $src2}",
+                 [(set GR64:$dst, (mul (load addr:$src1), i64immSExt32:$src2))]>;
+ def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem,                      // GR64 = [mem64]*I8
+                       (ops GR64:$dst, i64mem:$src1, i64i8imm: $src2),
+                       "imul{q} {$src2, $src1, $dst|$dst, $src1, $src2}",
+                  [(set GR64:$dst, (mul (load addr:$src1), i64immSExt8:$src2))]>;
+ 
+ // Unsigned division / remainder
+ def DIV64r : RI<0xF7, MRM6r, (ops GR64:$src),        // RDX:RAX/r64 = RAX,RDX
+                 "div{q} $src", []>, Imp<[RAX,RDX],[RAX,RDX]>;
+ def DIV64m : RI<0xF7, MRM6m, (ops i64mem:$src),      // RDX:RAX/[mem64] = RAX,RDX
+                 "div{q} $src", []>, Imp<[RAX,RDX],[RAX,RDX]>;
+ 
+ // Signed division / remainder
+ def IDIV64r: RI<0xF7, MRM7r, (ops GR64:$src),        // RDX:RAX/r64 = RAX,RDX
+                 "idiv{q} $src", []>, Imp<[RAX,RDX],[RAX,RDX]>;
+ def IDIV64m: RI<0xF7, MRM7m, (ops i64mem:$src),      // RDX:RAX/[mem64] = RAX,RDX
+                 "idiv{q} $src", []>, Imp<[RAX,RDX],[RAX,RDX]>;
+ 
+ // Unary instructions
+ let CodeSize = 2 in {
+ let isTwoAddress = 1 in
+ def NEG64r : RI<0xF7, MRM3r, (ops GR64:$dst, GR64:$src), "neg{q} $dst",
+                 [(set GR64:$dst, (ineg GR64:$src))]>;
+ def NEG64m : RI<0xF7, MRM3m, (ops i64mem:$dst), "neg{q} $dst",
+                 [(store (ineg (loadi64 addr:$dst)), addr:$dst)]>;
+ 
+ let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
+ def INC64r : RI<0xFF, MRM0r, (ops GR64:$dst, GR64:$src), "inc{q} $dst",
+                 [(set GR64:$dst, (add GR64:$src, 1))]>;
+ def INC64m : RI<0xFF, MRM0m, (ops i64mem:$dst), "inc{q} $dst",
+                 [(store (add (loadi64 addr:$dst), 1), addr:$dst)]>;
+ 
+ let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
+ def DEC64r : RI<0xFF, MRM1r, (ops GR64:$dst, GR64:$src), "dec{q} $dst",
+                 [(set GR64:$dst, (add GR64:$src, -1))]>;
+ def DEC64m : RI<0xFF, MRM1m, (ops i64mem:$dst), "dec{q} $dst",
+                 [(store (add (loadi64 addr:$dst), -1), addr:$dst)]>;
+ 
+ // In 64-bit mode, single byte INC and DEC cannot be encoded.
+ let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in {
+ // Can transform into LEA.
+ def INC64_16r : I<0xFF, MRM0r, (ops GR16:$dst, GR16:$src), "inc{w} $dst",
+                   [(set GR16:$dst, (add GR16:$src, 1))]>,
+                 OpSize, Requires<[In64BitMode]>;
+ def INC64_32r : I<0xFF, MRM0r, (ops GR32:$dst, GR32:$src), "inc{l} $dst",
+                   [(set GR32:$dst, (add GR32:$src, 1))]>,
+                 Requires<[In64BitMode]>;
+ def DEC64_16r : I<0xFF, MRM1r, (ops GR16:$dst, GR16:$src), "dec{w} $dst",
+                   [(set GR16:$dst, (add GR16:$src, -1))]>,
+                 OpSize, Requires<[In64BitMode]>;
+ def DEC64_32r : I<0xFF, MRM1r, (ops GR32:$dst, GR32:$src), "dec{l} $dst",
+                   [(set GR32:$dst, (add GR32:$src, -1))]>,
+                 Requires<[In64BitMode]>;
+ } // isConvertibleToThreeAddress
+ } // CodeSize
+ 
+ 
+ // Shift instructions
+ let isTwoAddress = 1 in {
+ def SHL64rCL : RI<0xD3, MRM4r, (ops GR64:$dst, GR64:$src),
+                   "shl{q} {%cl, $dst|$dst, %CL}",
+                   [(set GR64:$dst, (shl GR64:$src, CL))]>,
+                Imp<[CL],[]>;
+ def SHL64ri  : RIi8<0xC1, MRM4r, (ops GR64:$dst, GR64:$src1, i8imm:$src2),
+                     "shl{q} {$src2, $dst|$dst, $src2}",
+                     [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>;
+ def SHL64r1  : RI<0xD1, MRM4r, (ops GR64:$dst, GR64:$src1),
+                  "shl{q} $dst", []>;
+ } // isTwoAddress
+ 
+ def SHL64mCL : RI<0xD3, MRM4m, (ops i64mem:$dst),
+                   "shl{q} {%cl, $dst|$dst, %CL}",
+                   [(store (shl (loadi64 addr:$dst), CL), addr:$dst)]>,
+                Imp<[CL],[]>;
+ def SHL64mi : RIi8<0xC1, MRM4m, (ops i64mem:$dst, i8imm:$src),
+                   "shl{q} {$src, $dst|$dst, $src}",
+                  [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
+ def SHL64m1 : RI<0xC1, MRM4m, (ops i64mem:$dst),
+                   "shl{q} $dst",
+                  [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
+ 
+ let isTwoAddress = 1 in {
+ def SHR64rCL : RI<0xD3, MRM5r, (ops GR64:$dst, GR64:$src),
+                   "shr{q} {%cl, $dst|$dst, %CL}",
+                   [(set GR64:$dst, (srl GR64:$src, CL))]>,
+                Imp<[CL],[]>;
+ def SHR64ri : RIi8<0xC1, MRM5r, (ops GR64:$dst, GR64:$src1, i8imm:$src2),
+                   "shr{q} {$src2, $dst|$dst, $src2}",
+                   [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))]>;
+ def SHR64r1  : RI<0xD1, MRM5r, (ops GR64:$dst, GR64:$src1),
+                  "shr{q} $dst",
+                  [(set GR64:$dst, (srl GR64:$src1, (i8 1)))]>;
+ } // isTwoAddress
+ 
+ def SHR64mCL : RI<0xD3, MRM5m, (ops i64mem:$dst),
+                   "shr{q} {%cl, $dst|$dst, %CL}",
+                   [(store (srl (loadi64 addr:$dst), CL), addr:$dst)]>,
+                Imp<[CL],[]>;
+ def SHR64mi : RIi8<0xC1, MRM5m, (ops i64mem:$dst, i8imm:$src),
+                   "shr{q} {$src, $dst|$dst, $src}",
+                  [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
+ def SHR64m1 : RI<0xC1, MRM5m, (ops i64mem:$dst),
+                   "shr{q} $dst",
+                  [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
+ 
+ let isTwoAddress = 1 in {
+ def SAR64rCL : RI<0xD3, MRM7r, (ops GR64:$dst, GR64:$src),
+                  "sar{q} {%cl, $dst|$dst, %CL}",
+                  [(set GR64:$dst, (sra GR64:$src, CL))]>, Imp<[CL],[]>;
+ def SAR64ri  : RIi8<0xC1, MRM7r, (ops GR64:$dst, GR64:$src1, i8imm:$src2),
+                    "sar{q} {$src2, $dst|$dst, $src2}",
+                    [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))]>;
+ def SAR64r1  : RI<0xD1, MRM7r, (ops GR64:$dst, GR64:$src1),
+                  "sar{q} $dst",
+                  [(set GR64:$dst, (sra GR64:$src1, (i8 1)))]>;
+ } // isTwoAddress
+ 
+ def SAR64mCL : RI<0xD3, MRM7m, (ops i64mem:$dst), 
+                  "sar{q} {%cl, $dst|$dst, %CL}",
+                  [(store (sra (loadi64 addr:$dst), CL), addr:$dst)]>,
+                Imp<[CL],[]>;
+ def SAR64mi  : RIi8<0xC1, MRM7m, (ops i64mem:$dst, i8imm:$src),
+                     "sar{q} {$src, $dst|$dst, $src}",
+                  [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
+ def SAR64m1 : RI<0xC1, MRM7m, (ops i64mem:$dst),
+                   "sar{q} $dst",
+                  [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
+ 
+ // Rotate instructions
+ let isTwoAddress = 1 in {
+ def ROL64rCL : RI<0xD3, MRM0r, (ops GR64:$dst, GR64:$src),
+                   "rol{q} {%cl, $dst|$dst, %CL}",
+                   [(set GR64:$dst, (rotl GR64:$src, CL))]>, Imp<[CL],[]>;
+ def ROL64ri  : RIi8<0xC1, MRM0r, (ops GR64:$dst, GR64:$src1, i8imm:$src2),
+                     "rol{q} {$src2, $dst|$dst, $src2}",
+                     [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))]>;
+ def ROL64r1  : RI<0xC1, MRM0r, (ops GR64:$dst, GR64:$src1),
+                   "rol{q} $dst",
+                   [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))]>;
+ } // isTwoAddress
+ 
+ def ROL64mCL :  I<0xD3, MRM0m, (ops i64mem:$dst),
+                   "rol{q} {%cl, $dst|$dst, %CL}",
+                   [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)]>,
+                Imp<[CL],[]>;
+ def ROL64mi  : RIi8<0xC1, MRM0m, (ops i64mem:$dst, i8imm:$src),
+                     "rol{q} {$src, $dst|$dst, $src}",
+                 [(store (rotl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
+ def ROL64m1  : RI<0xD1, MRM0m, (ops i64mem:$dst),
+                  "rol{q} $dst",
+                [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
+ 
+ let isTwoAddress = 1 in {
+ def ROR64rCL : RI<0xD3, MRM1r, (ops GR64:$dst, GR64:$src),
+                   "ror{q} {%cl, $dst|$dst, %CL}",
+                   [(set GR64:$dst, (rotr GR64:$src, CL))]>, Imp<[CL],[]>;
+ def ROR64ri  : RIi8<0xC1, MRM1r, (ops GR64:$dst, GR64:$src1, i8imm:$src2),
+                     "ror{q} {$src2, $dst|$dst, $src2}",
+                     [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))]>;
+ def ROR64r1  : RI<0xC1, MRM1r, (ops GR64:$dst, GR64:$src1),
+                   "ror{q} $dst",
+                   [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))]>;
+ } // isTwoAddress
+ 
+ def ROR64mCL : RI<0xD3, MRM1m, (ops i64mem:$dst), 
+                   "ror{q} {%cl, $dst|$dst, %CL}",
+                   [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)]>,
+                Imp<[CL],[]>;
+ def ROR64mi  : RIi8<0xC1, MRM1m, (ops i64mem:$dst, i8imm:$src),
+                     "ror{q} {$src, $dst|$dst, $src}",
+                 [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
+ def ROR64m1  : RI<0xD1, MRM1m, (ops i64mem:$dst),
+                  "ror{q} $dst",
+                [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
+ 
+ // Double shift instructions (generalizations of rotate)
+ let isTwoAddress = 1 in {
+ def SHLD64rrCL : RI<0xA5, MRMDestReg, (ops GR64:$dst, GR64:$src1, GR64:$src2),
+                     "shld{q} {%cl, $src2, $dst|$dst, $src2, %CL}", []>,
+                  Imp<[CL],[]>, TB;
+ def SHRD64rrCL : RI<0xAD, MRMDestReg, (ops GR64:$dst, GR64:$src1, GR64:$src2),
+                     "shrd{q} {%cl, $src2, $dst|$dst, $src2, %CL}", []>,
+                  Imp<[CL],[]>, TB;
+ 
+ let isCommutable = 1 in {  // FIXME: Update X86InstrInfo::commuteInstruction
+ def SHLD64rri8 : RIi8<0xA4, MRMDestReg,
+                       (ops GR64:$dst, GR64:$src1, GR64:$src2, i8imm:$src3),
+                       "shld{q} {$src3, $src2, $dst|$dst, $src2, $src3}", []>,
+                       TB;
+ def SHRD64rri8 : RIi8<0xAC, MRMDestReg,
+                       (ops GR64:$dst, GR64:$src1, GR64:$src2, i8imm:$src3),
+                       "shrd{q} {$src3, $src2, $dst|$dst, $src2, $src3}", []>,
+                  TB;
+ } // isCommutable
+ } // isTwoAddress
+ 
+ // Temporary hack: there is no patterns associated with these instructions
+ // so we have to tell tblgen that these do not produce results.
+ let noResults = 1 in {
+ def SHLD64mrCL : RI<0xA5, MRMDestMem, (ops i64mem:$dst, GR64:$src2),
+                     "shld{q} {%cl, $src2, $dst|$dst, $src2, %CL}", []>,
+                  Imp<[CL],[]>, TB;
+ def SHRD64mrCL : RI<0xAD, MRMDestMem, (ops i64mem:$dst, GR64:$src2),
+                     "shrd{q} {%cl, $src2, $dst|$dst, $src2, %CL}", []>,
+                  Imp<[CL],[]>, TB;
+ def SHLD64mri8 : RIi8<0xA4, MRMDestMem,
+                       (ops i64mem:$dst, GR64:$src2, i8imm:$src3),
+                       "shld{q} {$src3, $src2, $dst|$dst, $src2, $src3}", []>,
+                  TB;
+ def SHRD64mri8 : RIi8<0xAC, MRMDestMem, 
+                       (ops i64mem:$dst, GR64:$src2, i8imm:$src3),
+                       "shrd{q} {$src3, $src2, $dst|$dst, $src2, $src3}", []>,
+                  TB;
+ } // noResults
+ 
+ //===----------------------------------------------------------------------===//
+ //  Logical Instructions...
+ //
+ 
+ let isTwoAddress = 1 in
+ def NOT64r : RI<0xF7, MRM2r, (ops GR64:$dst, GR64:$src), "not{q} $dst",
+                 [(set GR64:$dst, (not GR64:$src))]>;
+ def NOT64m : RI<0xF7, MRM2m, (ops i64mem:$dst), "not{q} $dst",
+                 [(store (not (loadi64 addr:$dst)), addr:$dst)]>;
+ 
+ let isTwoAddress = 1 in {
+ let isCommutable = 1 in
+ def AND64rr  : RI<0x21, MRMDestReg, 
+                   (ops GR64:$dst, GR64:$src1, GR64:$src2),
+                   "and{q} {$src2, $dst|$dst, $src2}",
+                   [(set GR64:$dst, (and GR64:$src1, GR64:$src2))]>;
+ def AND64rm  : RI<0x23, MRMSrcMem,
+                   (ops GR64:$dst, GR64:$src1, i64mem:$src2),
+                   "and{q} {$src2, $dst|$dst, $src2}",
+                   [(set GR64:$dst, (and GR64:$src1, (load addr:$src2)))]>;
+ def AND64ri32  : RIi32<0x81, MRM4r, 
+                        (ops GR64:$dst, GR64:$src1, i64i32imm:$src2),
+                        "and{q} {$src2, $dst|$dst, $src2}",
+                        [(set GR64:$dst, (and GR64:$src1, i64immSExt32:$src2))]>;
+ def AND64ri8 : RIi8<0x83, MRM4r, 
+                     (ops GR64:$dst, GR64:$src1, i64i8imm:$src2),
+                     "and{q} {$src2, $dst|$dst, $src2}",
+                     [(set GR64:$dst, (and GR64:$src1, i64immSExt8:$src2))]>;
+ } // isTwoAddress
+ 
+ def AND64mr  : RI<0x21, MRMDestMem,
+                   (ops i64mem:$dst, GR64:$src),
+                   "and{q} {$src, $dst|$dst, $src}",
+                   [(store (and (load addr:$dst), GR64:$src), addr:$dst)]>;
+ def AND64mi32  : RIi32<0x81, MRM4m,
+                        (ops i64mem:$dst, i64i32imm:$src),
+                        "and{q} {$src, $dst|$dst, $src}",
+              [(store (and (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst)]>;
+ def AND64mi8 : RIi8<0x83, MRM4m,
+                     (ops i64mem:$dst, i64i8imm :$src),
+                     "and{q} {$src, $dst|$dst, $src}",
+                  [(store (and (load addr:$dst), i64immSExt8:$src), addr:$dst)]>;
+ 
+ let isTwoAddress = 1 in {
+ let isCommutable = 1 in
+ def OR64rr   : RI<0x09, MRMDestReg, (ops GR64:$dst, GR64:$src1, GR64:$src2),
+                   "or{q} {$src2, $dst|$dst, $src2}",
+                   [(set GR64:$dst, (or GR64:$src1, GR64:$src2))]>;
+ def OR64rm   : RI<0x0B, MRMSrcMem , (ops GR64:$dst, GR64:$src1, i64mem:$src2),
+                   "or{q} {$src2, $dst|$dst, $src2}",
+                   [(set GR64:$dst, (or GR64:$src1, (load addr:$src2)))]>;
+ def OR64ri32 : RIi32<0x81, MRM1r, (ops GR64:$dst, GR64:$src1, i64i32imm:$src2),
+                      "or{q} {$src2, $dst|$dst, $src2}",
+                      [(set GR64:$dst, (or GR64:$src1, i64immSExt32:$src2))]>;
+ def OR64ri8  : RIi8<0x83, MRM1r, (ops GR64:$dst, GR64:$src1, i64i8imm:$src2),
+                     "or{q} {$src2, $dst|$dst, $src2}",
+                     [(set GR64:$dst, (or GR64:$src1, i64immSExt8:$src2))]>;
+ } // isTwoAddress
+ 
+ def OR64mr : RI<0x09, MRMDestMem, (ops i64mem:$dst, GR64:$src),
+                 "or{q} {$src, $dst|$dst, $src}",
+                 [(store (or (load addr:$dst), GR64:$src), addr:$dst)]>;
+ def OR64mi32 : RIi32<0x81, MRM1m, (ops i64mem:$dst, i64i32imm:$src),
+                      "or{q} {$src, $dst|$dst, $src}",
+               [(store (or (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst)]>;
+ def OR64mi8  : RIi8<0x83, MRM1m, (ops i64mem:$dst, i64i8imm:$src),
+                     "or{q} {$src, $dst|$dst, $src}",
+                   [(store (or (load addr:$dst), i64immSExt8:$src), addr:$dst)]>;
+ 
+ let isTwoAddress = 1 in {
+ let isCommutable = 1 in
+ def XOR64rr  : RI<0x31, MRMDestReg,  (ops GR64:$dst, GR64:$src1, GR64:$src2), 
+                   "xor{q} {$src2, $dst|$dst, $src2}",
+                   [(set GR64:$dst, (xor GR64:$src1, GR64:$src2))]>;
+ def XOR64rm  : RI<0x33, MRMSrcMem, (ops GR64:$dst, GR64:$src1, i64mem:$src2), 
+                   "xor{q} {$src2, $dst|$dst, $src2}",
+                   [(set GR64:$dst, (xor GR64:$src1, (load addr:$src2)))]>;
+ def XOR64ri32 : RIi32<0x81, MRM6r, 
+                       (ops GR64:$dst, GR64:$src1, i64i32imm:$src2), 
+                       "xor{q} {$src2, $dst|$dst, $src2}",
+                       [(set GR64:$dst, (xor GR64:$src1, i64immSExt32:$src2))]>;
+ def XOR64ri8 : RIi8<0x83, MRM6r,  (ops GR64:$dst, GR64:$src1, i64i8imm:$src2),
+                     "xor{q} {$src2, $dst|$dst, $src2}",
+                     [(set GR64:$dst, (xor GR64:$src1, i64immSExt8:$src2))]>;
+ } // isTwoAddress
+ 
+ def XOR64mr  : RI<0x31, MRMDestMem, (ops i64mem:$dst, GR64:$src),
+                   "xor{q} {$src, $dst|$dst, $src}",
+                   [(store (xor (load addr:$dst), GR64:$src), addr:$dst)]>;
+ def XOR64mi32 : RIi32<0x81, MRM6m, (ops i64mem:$dst, i64i32imm:$src),
+                       "xor{q} {$src, $dst|$dst, $src}",
+              [(store (xor (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst)]>;
+ def XOR64mi8 : RIi8<0x83, MRM6m, (ops i64mem:$dst, i64i8imm :$src),
+                     "xor{q} {$src, $dst|$dst, $src}",
+                  [(store (xor (load addr:$dst), i64immSExt8:$src), addr:$dst)]>;
+ 
+ //===----------------------------------------------------------------------===//
+ //  Comparison Instructions...
+ //
+ 
+ // Integer comparison
+ let isCommutable = 1 in
+ def TEST64rr : RI<0x85, MRMDestReg, (ops GR64:$src1, GR64:$src2),
+                   "test{q} {$src2, $src1|$src1, $src2}",
+                   [(X86cmp (and GR64:$src1, GR64:$src2), 0)]>;
+ def TEST64mr : RI<0x85, MRMDestMem, (ops i64mem:$src1, GR64:$src2),
+                   "test{q} {$src2, $src1|$src1, $src2}",
+                   [/*(X86cmp (and (loadi64 addr:$src1), GR64:$src2), 0)*/]>;
+ def TEST64rm : RI<0x85, MRMSrcMem, (ops GR64:$src1, i64mem:$src2),
+                   "test{q} {$src2, $src1|$src1, $src2}",
+                   [/*(X86cmp (and GR64:$src1, (loadi64 addr:$src2)), 0)*/]>;
+ def TEST64ri32 : RIi32<0xF7, MRM0r, (ops GR64:$src1, i64i32imm:$src2),
+                        "test{q} {$src2, $src1|$src1, $src2}",
+                        [(X86cmp (and GR64:$src1, i64immSExt32:$src2), 0)]>;
+ def TEST64mi32 : RIi32<0xF7, MRM0m, (ops i64mem:$src1, i64i32imm:$src2),
+                        "test{q} {$src2, $src1|$src1, $src2}",
+                       [/*(X86cmp (and (loadi64 addr:$src1), i64immSExt32:$src2),
+                          0)*/]>;
+ 
+ def CMP64rr : RI<0x39, MRMDestReg, (ops GR64:$src1, GR64:$src2),
+                  "cmp{q} {$src2, $src1|$src1, $src2}",
+                  [(X86cmp GR64:$src1, GR64:$src2)]>;
+ def CMP64mr : RI<0x39, MRMDestMem, (ops i64mem:$src1, GR64:$src2),
+                  "cmp{q} {$src2, $src1|$src1, $src2}",
+                  [(X86cmp (loadi64 addr:$src1), GR64:$src2)]>;
+ def CMP64rm : RI<0x3B, MRMSrcMem, (ops GR64:$src1, i64mem:$src2),
+                  "cmp{q} {$src2, $src1|$src1, $src2}",
+                  [(X86cmp GR64:$src1, (loadi64 addr:$src2))]>;
+ def CMP64ri32 : RIi32<0x81, MRM7r, (ops GR64:$src1, i64i32imm:$src2),
+                       "cmp{q} {$src2, $src1|$src1, $src2}",
+                       [(X86cmp GR64:$src1, i64immSExt32:$src2)]>;
+ def CMP64mi32 : RIi32<0x81, MRM7m, (ops i64mem:$src1, i64i32imm:$src2),
+                       "cmp{q} {$src2, $src1|$src1, $src2}",
+                       [(X86cmp (loadi64 addr:$src1), i64immSExt32:$src2)]>;
+ def CMP64mi8 : RIi8<0x83, MRM7m, (ops i64mem:$src1, i64i8imm:$src2),
+                     "cmp{q} {$src2, $src1|$src1, $src2}",
+                     [(X86cmp (loadi64 addr:$src1), i64immSExt8:$src2)]>;
+ def CMP64ri8 : RIi8<0x83, MRM7r, (ops GR64:$src1, i64i8imm:$src2),
+                     "cmp{q} {$src2, $src1|$src1, $src2}",
+                     [(X86cmp GR64:$src1, i64immSExt8:$src2)]>;
+ 
+ // Conditional moves
+ let isTwoAddress = 1 in {
+ def CMOVB64rr : RI<0x42, MRMSrcReg,       // if <u, GR64 = GR64
+                    (ops GR64:$dst, GR64:$src1, GR64:$src2),
+                    "cmovb {$src2, $dst|$dst, $src2}",
+                    [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
+                                      X86_COND_B))]>, TB;
+ def CMOVB64rm : RI<0x42, MRMSrcMem,       // if <u, GR64 = [mem64]
+                    (ops GR64:$dst, GR64:$src1, i64mem:$src2),
+                    "cmovb {$src2, $dst|$dst, $src2}",
+                    [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
+                                      X86_COND_B))]>, TB;
+ def CMOVAE64rr: RI<0x43, MRMSrcReg,       // if >=u, GR64 = GR64
+                    (ops GR64:$dst, GR64:$src1, GR64:$src2),
+                    "cmovae {$src2, $dst|$dst, $src2}",
+                    [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
+                                      X86_COND_AE))]>, TB;
+ def CMOVAE64rm: RI<0x43, MRMSrcMem,       // if >=u, GR64 = [mem64]
+                    (ops GR64:$dst, GR64:$src1, i64mem:$src2),
+                    "cmovae {$src2, $dst|$dst, $src2}",
+                    [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
+                                      X86_COND_AE))]>, TB;
+ def CMOVE64rr : RI<0x44, MRMSrcReg,       // if ==, GR64 = GR64
+                    (ops GR64:$dst, GR64:$src1, GR64:$src2),
+                    "cmove {$src2, $dst|$dst, $src2}",
+                    [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
+                                      X86_COND_E))]>, TB;
+ def CMOVE64rm : RI<0x44, MRMSrcMem,       // if ==, GR64 = [mem64]
+                    (ops GR64:$dst, GR64:$src1, i64mem:$src2),
+                    "cmove {$src2, $dst|$dst, $src2}",
+                    [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
+                                      X86_COND_E))]>, TB;
+ def CMOVNE64rr: RI<0x45, MRMSrcReg,       // if !=, GR64 = GR64
+                    (ops GR64:$dst, GR64:$src1, GR64:$src2),
+                    "cmovne {$src2, $dst|$dst, $src2}",
+                    [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
+                                     X86_COND_NE))]>, TB;
+ def CMOVNE64rm: RI<0x45, MRMSrcMem,       // if !=, GR64 = [mem64]
+                    (ops GR64:$dst, GR64:$src1, i64mem:$src2),
+                    "cmovne {$src2, $dst|$dst, $src2}",
+                    [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
+                                     X86_COND_NE))]>, TB;
+ def CMOVBE64rr: RI<0x46, MRMSrcReg,       // if <=u, GR64 = GR64
+                    (ops GR64:$dst, GR64:$src1, GR64:$src2),
+                    "cmovbe {$src2, $dst|$dst, $src2}",
+                    [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
+                                     X86_COND_BE))]>, TB;
+ def CMOVBE64rm: RI<0x46, MRMSrcMem,       // if <=u, GR64 = [mem64]
+                    (ops GR64:$dst, GR64:$src1, i64mem:$src2),
+                    "cmovbe {$src2, $dst|$dst, $src2}",
+                    [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
+                                     X86_COND_BE))]>, TB;
+ def CMOVA64rr : RI<0x47, MRMSrcReg,       // if >u, GR64 = GR64
+                    (ops GR64:$dst, GR64:$src1, GR64:$src2),
+                    "cmova {$src2, $dst|$dst, $src2}",
+                    [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
+                                     X86_COND_A))]>, TB;
+ def CMOVA64rm : RI<0x47, MRMSrcMem,       // if >u, GR64 = [mem64]
+                    (ops GR64:$dst, GR64:$src1, i64mem:$src2),
+                    "cmova {$src2, $dst|$dst, $src2}",
+                    [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
+                                     X86_COND_A))]>, TB;
+ def CMOVL64rr : RI<0x4C, MRMSrcReg,       // if <s, GR64 = GR64
+                    (ops GR64:$dst, GR64:$src1, GR64:$src2),
+                    "cmovl {$src2, $dst|$dst, $src2}",
+                    [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
+                                     X86_COND_L))]>, TB;
+ def CMOVL64rm : RI<0x4C, MRMSrcMem,       // if <s, GR64 = [mem64]
+                    (ops GR64:$dst, GR64:$src1, i64mem:$src2),
+                    "cmovl {$src2, $dst|$dst, $src2}",
+                    [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
+                                     X86_COND_L))]>, TB;
+ def CMOVGE64rr: RI<0x4D, MRMSrcReg,       // if >=s, GR64 = GR64
+                    (ops GR64:$dst, GR64:$src1, GR64:$src2),
+                    "cmovge {$src2, $dst|$dst, $src2}",
+                    [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
+                                     X86_COND_GE))]>, TB;
+ def CMOVGE64rm: RI<0x4D, MRMSrcMem,       // if >=s, GR64 = [mem64]
+                    (ops GR64:$dst, GR64:$src1, i64mem:$src2),
+                    "cmovge {$src2, $dst|$dst, $src2}",
+                    [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
+                                     X86_COND_GE))]>, TB;
+ def CMOVLE64rr: RI<0x4E, MRMSrcReg,       // if <=s, GR64 = GR64
+                    (ops GR64:$dst, GR64:$src1, GR64:$src2),
+                    "cmovle {$src2, $dst|$dst, $src2}",
+                    [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
+                                     X86_COND_LE))]>, TB;
+ def CMOVLE64rm: RI<0x4E, MRMSrcMem,       // if <=s, GR64 = [mem64]
+                    (ops GR64:$dst, GR64:$src1, i64mem:$src2),
+                    "cmovle {$src2, $dst|$dst, $src2}",
+                    [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
+                                     X86_COND_LE))]>, TB;
+ def CMOVG64rr : RI<0x4F, MRMSrcReg,       // if >s, GR64 = GR64
+                    (ops GR64:$dst, GR64:$src1, GR64:$src2),
+                    "cmovg {$src2, $dst|$dst, $src2}",
+                    [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
+                                     X86_COND_G))]>, TB;
+ def CMOVG64rm : RI<0x4F, MRMSrcMem,       // if >s, GR64 = [mem64]
+                    (ops GR64:$dst, GR64:$src1, i64mem:$src2),
+                    "cmovg {$src2, $dst|$dst, $src2}",
+                    [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
+                                     X86_COND_G))]>, TB;
+ def CMOVS64rr : RI<0x48, MRMSrcReg,       // if signed, GR64 = GR64
+                    (ops GR64:$dst, GR64:$src1, GR64:$src2),
+                    "cmovs {$src2, $dst|$dst, $src2}",
+                    [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
+                                     X86_COND_S))]>, TB;
+ def CMOVS64rm : RI<0x48, MRMSrcMem,       // if signed, GR64 = [mem64]
+                    (ops GR64:$dst, GR64:$src1, i64mem:$src2),
+                    "cmovs {$src2, $dst|$dst, $src2}",
+                    [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
+                                     X86_COND_S))]>, TB;
+ def CMOVNS64rr: RI<0x49, MRMSrcReg,       // if !signed, GR64 = GR64
+                    (ops GR64:$dst, GR64:$src1, GR64:$src2),
+                    "cmovns {$src2, $dst|$dst, $src2}",
+                    [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
+                                     X86_COND_NS))]>, TB;
+ def CMOVNS64rm: RI<0x49, MRMSrcMem,       // if !signed, GR64 = [mem64]
+                    (ops GR64:$dst, GR64:$src1, i64mem:$src2),
+                    "cmovns {$src2, $dst|$dst, $src2}",
+                    [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
+                                     X86_COND_NS))]>, TB;
+ def CMOVP64rr : RI<0x4A, MRMSrcReg,       // if parity, GR64 = GR64
+                    (ops GR64:$dst, GR64:$src1, GR64:$src2),
+                    "cmovp {$src2, $dst|$dst, $src2}",
+                    [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
+                                     X86_COND_P))]>, TB;
+ def CMOVP64rm : RI<0x4A, MRMSrcMem,       // if parity, GR64 = [mem64]
+                    (ops GR64:$dst, GR64:$src1, i64mem:$src2),
+                    "cmovp {$src2, $dst|$dst, $src2}",
+                    [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
+                                     X86_COND_P))]>, TB;
+ def CMOVNP64rr : RI<0x4B, MRMSrcReg,       // if !parity, GR64 = GR64
+                    (ops GR64:$dst, GR64:$src1, GR64:$src2),
+                    "cmovnp {$src2, $dst|$dst, $src2}",
+                     [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
+                                      X86_COND_NP))]>, TB;
+ def CMOVNP64rm : RI<0x4B, MRMSrcMem,       // if !parity, GR64 = [mem64]
+                    (ops GR64:$dst, GR64:$src1, i64mem:$src2),
+                    "cmovnp {$src2, $dst|$dst, $src2}",
+                     [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
+                                      X86_COND_NP))]>, TB;
+ } // isTwoAddress
+ 
+ //===----------------------------------------------------------------------===//
+ //  Conversion Instructions...
+ //
+ 
+ // f64 -> signed i64
+ def Int_CVTSD2SI64rr: RSDI<0x2D, MRMSrcReg, (ops GR64:$dst, VR128:$src),
+                            "cvtsd2si{q} {$src, $dst|$dst, $src}",
+                            []>; // TODO: add intrinsic
+ def Int_CVTSD2SI64rm: RSDI<0x2D, MRMSrcMem, (ops GR64:$dst, f128mem:$src),
+                            "cvtsd2si{q} {$src, $dst|$dst, $src}",
+                            []>; // TODO: add intrinsic
+ def CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (ops GR64:$dst, FR64:$src),
+                         "cvttsd2si{q} {$src, $dst|$dst, $src}",
+                         [(set GR64:$dst, (fp_to_sint FR64:$src))]>;
+ def CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (ops GR64:$dst, f64mem:$src),
+                         "cvttsd2si{q} {$src, $dst|$dst, $src}",
+                         [(set GR64:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
+ def Int_CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (ops GR64:$dst, VR128:$src),
+                             "cvttsd2si{q} {$src, $dst|$dst, $src}",
+                             []>; // TODO: add intrinsic
+ def Int_CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (ops GR64:$dst, f128mem:$src),
+                             "cvttsd2si{q} {$src, $dst|$dst, $src}",
+                             []>; // TODO: add intrinsic
+ 
+ // Signed i64 -> f64
+ def CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg, (ops FR64:$dst, GR64:$src),
+                        "cvtsi2sd{q} {$src, $dst|$dst, $src}",
+                        [(set FR64:$dst, (sint_to_fp GR64:$src))]>;
+ def CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem, (ops FR64:$dst, i64mem:$src),
+                        "cvtsi2sd{q} {$src, $dst|$dst, $src}",
+                        [(set FR64:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
+ let isTwoAddress = 1 in {
+ def Int_CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg,
+                            (ops VR128:$dst, VR128:$src1, GR64:$src2),
+                            "cvtsi2sd{q} {$src2, $dst|$dst, $src2}",
+                            []>; // TODO: add intrinsic
+ def Int_CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem,
+                            (ops VR128:$dst, VR128:$src1, i64mem:$src2),
+                            "cvtsi2sd{q} {$src2, $dst|$dst, $src2}",
+                            []>; // TODO: add intrinsic
+ } // isTwoAddress
+ 
+ // Signed i64 -> f32
+ def CVTSI2SS64rr: RSSI<0x2A, MRMSrcReg, (ops FR32:$dst, GR64:$src),
+                        "cvtsi2ss{q} {$src, $dst|$dst, $src}",
+                        [(set FR32:$dst, (sint_to_fp GR64:$src))]>;
+ def CVTSI2SS64rm: RSSI<0x2A, MRMSrcMem, (ops FR32:$dst, i64mem:$src),
+                        "cvtsi2ss{q} {$src, $dst|$dst, $src}",
+                        [(set FR32:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
+ let isTwoAddress = 1 in {
+ def Int_CVTSI2SS64rr: RSSI<0x2A, MRMSrcReg,
+                            (ops VR128:$dst, VR128:$src1, GR64:$src2),
+                            "cvtsi2ss{q} {$src2, $dst|$dst, $src2}",
+                            []>; // TODO: add intrinsic
+ def Int_CVTSI2SS64rm: RSSI<0x2A, MRMSrcMem,
+                            (ops VR128:$dst, VR128:$src1, i64mem:$src2),
+                            "cvtsi2ss{q} {$src2, $dst|$dst, $src2}",
+                            []>; // TODO: add intrinsic
+ } // isTwoAddress
+ 
+ // f32 -> signed i64
+ def Int_CVTSS2SI64rr: RSSI<0x2D, MRMSrcReg, (ops GR64:$dst, VR128:$src),
+                            "cvtss2si{q} {$src, $dst|$dst, $src}",
+                            []>; // TODO: add intrinsic
+ def Int_CVTSS2SI64rm: RSSI<0x2D, MRMSrcMem, (ops GR64:$dst, f32mem:$src),
+                            "cvtss2si{q} {$src, $dst|$dst, $src}",
+                            []>; // TODO: add intrinsic
+ def CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (ops GR64:$dst, FR32:$src),
+                         "cvttss2si{q} {$src, $dst|$dst, $src}",
+                         [(set GR64:$dst, (fp_to_sint FR32:$src))]>;
+ def CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (ops GR64:$dst, f32mem:$src),
+                         "cvttss2si{q} {$src, $dst|$dst, $src}",
+                         [(set GR64:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
+ def Int_CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (ops GR64:$dst, VR128:$src),
+                             "cvttss2si{q} {$src, $dst|$dst, $src}",
+                             []>; // TODO: add intrinsic
+ def Int_CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (ops GR64:$dst, f32mem:$src),
+                             "cvttss2si{q} {$src, $dst|$dst, $src}",
+                             []>; // TODO: add intrinsic
+ 
+ //===----------------------------------------------------------------------===//
+ // Alias Instructions
+ //===----------------------------------------------------------------------===//
+ 
+ // Truncate
+ // In 64-mode, each 64-bit and 32-bit registers has a low 8-bit sub-register.
+ def TRUNC_64to8  : I<0x88, MRMDestReg, (ops GR8:$dst, GR64:$src),
+                      "mov{b} {${src:subreg8}, $dst|$dst, ${src:subreg8}",
+                      [(set GR8:$dst, (trunc GR64:$src))]>;
+ def TRUNC_32to8  : I<0x88, MRMDestReg, (ops GR8:$dst, GR32:$src),
+                      "mov{b} {${src:subreg8}, $dst|$dst, ${src:subreg8}",
+                      [(set GR8:$dst, (trunc GR32:$src))]>,
+                    Requires<[In64BitMode]>;
+ def TRUNC_16to8  : I<0x88, MRMDestReg, (ops GR8:$dst, GR16:$src),
+                      "mov{b} {${src:subreg8}, $dst|$dst, ${src:subreg8}}",
+                      [(set GR8:$dst, (trunc GR16:$src))]>,
+                    Requires<[In64BitMode]>;
+ 
+ def TRUNC_64to16 : I<0x89, MRMDestReg, (ops GR16:$dst, GR64:$src),
+                      "mov{w} {${src:subreg16}, $dst|$dst, ${src:subreg16}}",
+                      [(set GR16:$dst, (trunc GR64:$src))]>;
+ 
+ def TRUNC_64to32 : I<0x89, MRMDestReg, (ops GR32:$dst, GR64:$src),
+                      "mov{l} {${src:subreg32}, $dst|$dst, ${src:subreg32}}",
+                      [(set GR32:$dst, (trunc GR64:$src))]>;
+ 
+ // Zero-extension
+ // TODO: Remove this after proper i32 -> i64 zext support.
+ def PsMOVZX64rr32: I<0x89, MRMDestReg, (ops GR64:$dst, GR32:$src),
+                      "mov{l} {$src, ${dst:subreg32}|${dst:subreg32}, $src}",
+                      [(set GR64:$dst, (zext GR32:$src))]>;
+ def PsMOVZX64rm32: I<0x8B, MRMSrcMem, (ops GR64:$dst, i32mem:$src),
+                      "mov{l} {$src, ${dst:subreg32}|${dst:subreg32}, $src}",
+                      [(set GR64:$dst, (zextloadi64i32 addr:$src))]>;
+ 
+ 
+ // Alias instructions that map movr0 to xor.
+ // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
+ // FIXME: AddedComplexity gives MOV64r0 a higher priority than MOV64ri32. Remove
+ // when we have a better way to specify isel priority.
+ let AddedComplexity = 1 in
+ def MOV64r0  : RI<0x31, MRMInitReg,  (ops GR64:$dst), 
+                  "xor{q} $dst, $dst",
+                  [(set GR64:$dst, 0)]>;
+ 
+ // Materialize i64 constant where top 32-bits are zero.
+ let AddedComplexity = 1 in
+ def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (ops GR64:$dst, i64i32imm:$src),
+                         "mov{l} {$src, ${dst:subreg32}|${dst:subreg32}, $src}",
+                         [(set GR64:$dst, i64immZExt32:$src)]>;
+ 
+ //===----------------------------------------------------------------------===//
+ // Non-Instruction Patterns
+ //===----------------------------------------------------------------------===//
+ 
+ // Calls
+ // Direct PC relative function call for small code model. 32-bit displacement
+ // sign extended to 64-bit.
+ def : Pat<(X86call (i64 tglobaladdr:$dst)),
+           (CALL64pcrel32 tglobaladdr:$dst)>;
+ def : Pat<(X86call (i64 texternalsym:$dst)),
+           (CALL64pcrel32 texternalsym:$dst)>;
+ 
+ def : Pat<(X86tailcall (i64 tglobaladdr:$dst)),
+           (CALL64pcrel32 tglobaladdr:$dst)>;
+ def : Pat<(X86tailcall (i64 texternalsym:$dst)),
+           (CALL64pcrel32 texternalsym:$dst)>;
+ 
+ def : Pat<(X86tailcall GR64:$dst),
+           (CALL64r GR64:$dst)>;
+ 
+ // {s|z}extload bool -> {s|z}extload byte
+ def : Pat<(sextloadi64i1 addr:$src), (MOVSX64rm8 addr:$src)>;
+ def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
+ 
+ // extload
+ def : Pat<(extloadi64i1 addr:$src),  (MOVZX64rm8  addr:$src)>;
+ def : Pat<(extloadi64i8 addr:$src),  (MOVZX64rm8  addr:$src)>;
+ def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>;
+ def : Pat<(extloadi64i32 addr:$src), (PsMOVZX64rm32 addr:$src)>;
+ 
+ // anyext -> zext
+ def : Pat<(i64 (anyext GR8 :$src)), (MOVZX64rr8  GR8 :$src)>;
+ def : Pat<(i64 (anyext GR16:$src)), (MOVZX64rr16 GR16:$src)>;
+ def : Pat<(i64 (anyext GR32:$src)), (PsMOVZX64rr32 GR32:$src)>;
+ def : Pat<(i64 (anyext (loadi8  addr:$src))), (MOVZX64rm8  addr:$src)>;
+ def : Pat<(i64 (anyext (loadi16 addr:$src))), (MOVZX64rm16 addr:$src)>;
+ def : Pat<(i64 (anyext (loadi32 addr:$src))), (PsMOVZX64rm32 addr:$src)>;
+ 
+ //===----------------------------------------------------------------------===//
+ // Some peepholes
+ //===----------------------------------------------------------------------===//
+ 
+ // (shl x, 1) ==> (add x, x)
+ def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
+ 
+ // (or (x >> c) | (y << (64 - c))) ==> (shrd64 x, y, c)
+ def : Pat<(or (srl GR64:$src1, CL:$amt),
+               (shl GR64:$src2, (sub 64, CL:$amt))),
+           (SHRD64rrCL GR64:$src1, GR64:$src2)>;
+ 
+ def : Pat<(store (or (srl (loadi64 addr:$dst), CL:$amt),
+                      (shl GR64:$src2, (sub 64, CL:$amt))), addr:$dst),
+           (SHRD64mrCL addr:$dst, GR64:$src2)>;
+ 
+ // (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
+ def : Pat<(or (shl GR64:$src1, CL:$amt),
+               (srl GR64:$src2, (sub 64, CL:$amt))),
+           (SHLD64rrCL GR64:$src1, GR64:$src2)>;
+ 
+ def : Pat<(store (or (shl (loadi64 addr:$dst), CL:$amt),
+                      (srl GR64:$src2, (sub 64, CL:$amt))), addr:$dst),
+           (SHLD64mrCL addr:$dst, GR64:$src2)>;


Index: llvm/lib/Target/X86/X86.td
diff -u llvm/lib/Target/X86/X86.td:1.25 llvm/lib/Target/X86/X86.td:1.26
--- llvm/lib/Target/X86/X86.td:1.25	Thu May 18 01:27:15 2006
+++ llvm/lib/Target/X86/X86.td	Fri Sep  8 01:48:29 2006
@@ -20,8 +20,8 @@
 // X86 Subtarget features.
 //
  
-def Feature64Bit     : SubtargetFeature<"64bit", "Is64Bit", "true",
-                                        "Enable 64-bit instructions">;
+def Feature64Bit     : SubtargetFeature<"64bit", "HasX86_64", "true",
+                                        "Support 64-bit instructions">;
 def FeatureMMX       : SubtargetFeature<"mmx","X86SSELevel", "MMX",
                                         "Enable MMX instructions">;
 def FeatureSSE1      : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
@@ -61,6 +61,8 @@
                                FeatureSSE3]>;
 def : Proc<"nocona",          [FeatureMMX, FeatureSSE1, FeatureSSE2,
                                FeatureSSE3, Feature64Bit]>;
+def : Proc<"core2",           [FeatureMMX, FeatureSSE1, FeatureSSE2,
+                               FeatureSSE3,  Feature64Bit]>;
 
 def : Proc<"k6",              [FeatureMMX]>;
 def : Proc<"k6-2",            [FeatureMMX, Feature3DNow]>;
@@ -105,16 +107,20 @@
   // should be kept up-to-date with the fields in the X86InstrInfo.h file.
   let TSFlagsFields = ["FormBits",
                        "hasOpSizePrefix",
+                       "hasAdSizePrefix",
                        "Prefix",
+                       "hasREX_WPrefix",
                        "ImmTypeBits",
                        "FPFormBits",
                        "Opcode"];
   let TSFlagsShifts = [0,
                        6,
                        7,
-                       11,
+                       8,
+                       12,
                        13,
-                       16];
+                       16,
+                       24];
 }
 
 // The X86 target supports two different syntaxes for emitting machine code.


Index: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp
diff -u llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.60 llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.61
--- llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.60	Thu Sep  7 17:06:40 2006
+++ llvm/lib/Target/X86/X86ATTAsmPrinter.cpp	Fri Sep  8 01:48:29 2006
@@ -126,8 +126,9 @@
     O << '%';
     unsigned Reg = MO.getReg();
     if (Modifier && strncmp(Modifier, "subreg", strlen("subreg")) == 0) {
-      MVT::ValueType VT = (strcmp(Modifier,"subreg16") == 0)
-        ? MVT::i16 : MVT::i8;
+      MVT::ValueType VT = (strcmp(Modifier+6,"64") == 0) ?
+        MVT::i64 : ((strcmp(Modifier+6, "32") == 0) ? MVT::i32 :
+                    ((strcmp(Modifier+6,"16") == 0) ? MVT::i16 : MVT::i8));
       Reg = getX86SubSuperRegister(Reg, VT);
     }
     for (const char *Name = RI.get(Reg).Name; *Name; ++Name)
@@ -148,9 +149,11 @@
     if (!isMemOp) O << '$';
     O << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber() << "_"
       << MO.getJumpTableIndex();
-    if (Subtarget->isTargetDarwin() && 
+    if (X86PICStyle == PICStyle::Stub &&
         TM.getRelocationModel() == Reloc::PIC_)
       O << "-\"L" << getFunctionNumber() << "$pb\"";
+    if (Subtarget->is64Bit())
+      O << "(%rip)";
     return;
   }
   case MachineOperand::MO_ConstantPoolIndex: {
@@ -158,7 +161,7 @@
     if (!isMemOp) O << '$';
     O << TAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber() << "_"
       << MO.getConstantPoolIndex();
-    if (Subtarget->isTargetDarwin() && 
+    if (X86PICStyle == PICStyle::Stub &&
         TM.getRelocationModel() == Reloc::PIC_)
       O << "-\"L" << getFunctionNumber() << "$pb\"";
     int Offset = MO.getOffset();
@@ -166,47 +169,59 @@
       O << "+" << Offset;
     else if (Offset < 0)
       O << Offset;
+
+    if (Subtarget->is64Bit())
+      O << "(%rip)";
     return;
   }
   case MachineOperand::MO_GlobalAddress: {
     bool isCallOp = Modifier && !strcmp(Modifier, "call");
     bool isMemOp  = Modifier && !strcmp(Modifier, "mem");
     if (!isMemOp && !isCallOp) O << '$';
-    // Darwin block shameless ripped from PPCAsmPrinter.cpp
-    if (Subtarget->isTargetDarwin() && 
+
+    GlobalValue *GV = MO.getGlobal();
+    std::string Name = Mang->getValueName(GV);
+    bool isExt = (GV->isExternal() || GV->hasWeakLinkage() ||
+                  GV->hasLinkOnceLinkage());
+    if (X86PICStyle == PICStyle::Stub &&
         TM.getRelocationModel() != Reloc::Static) {
-      GlobalValue *GV = MO.getGlobal();
-      std::string Name = Mang->getValueName(GV);
       // Link-once, External, or Weakly-linked global variables need
       // non-lazily-resolved stubs
-      if (GV->isExternal() || GV->hasWeakLinkage() ||
-          GV->hasLinkOnceLinkage()) {
+      if (isExt) {
         // Dynamically-resolved functions need a stub for the function.
-        if (isCallOp && isa<Function>(GV) && cast<Function>(GV)->isExternal()) {
+        if (isCallOp && isa<Function>(GV)) {
           FnStubs.insert(Name);
           O << "L" << Name << "$stub";
         } else {
           GVStubs.insert(Name);
           O << "L" << Name << "$non_lazy_ptr";
         }
-      } else {
-        O << Mang->getValueName(GV);
-      } 
+      } else
+        O << Name;
       if (!isCallOp && TM.getRelocationModel() == Reloc::PIC_)
         O << "-\"L" << getFunctionNumber() << "$pb\"";
-   } else
-      O << Mang->getValueName(MO.getGlobal());
+    } else
+      O << Name;
+
     int Offset = MO.getOffset();
     if (Offset > 0)
       O << "+" << Offset;
     else if (Offset < 0)
       O << Offset;
+
+    if (!isCallOp &&
+        Subtarget->is64Bit()) {
+      if (isExt && TM.getRelocationModel() != Reloc::Static)
+        O << "@GOTPCREL";
+      O << "(%rip)";
+    }
+
     return;
   }
   case MachineOperand::MO_ExternalSymbol: {
     bool isCallOp = Modifier && !strcmp(Modifier, "call");
     if (isCallOp && 
-        Subtarget->isTargetDarwin() && 
+        X86PICStyle == PICStyle::Stub &&
         TM.getRelocationModel() != Reloc::Static) {
       std::string Name(TAI->getGlobalPrefix());
       Name += MO.getSymbolName();
@@ -216,6 +231,11 @@
     }
     if (!isCallOp) O << '$';
     O << TAI->getGlobalPrefix() << MO.getSymbolName();
+
+    if (!isCallOp &&
+        Subtarget->is64Bit())
+      O << "(%rip)";
+
     return;
   }
   default:
@@ -238,7 +258,8 @@
   }
 }
 
-void X86ATTAsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op){
+void X86ATTAsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op,
+                                         const char *Modifier){
   assert(isMem(MI, Op) && "Invalid memory reference!");
 
   const MachineOperand &BaseReg  = MI->getOperand(Op);
@@ -266,12 +287,13 @@
 
   if (IndexReg.getReg() || BaseReg.getReg()) {
     O << "(";
-    if (BaseReg.getReg())
-      printOperand(MI, Op);
+    if (BaseReg.getReg()) {
+      printOperand(MI, Op, Modifier);
+    }
 
     if (IndexReg.getReg()) {
       O << ",";
-      printOperand(MI, Op+2);
+      printOperand(MI, Op+2, Modifier);
       if (ScaleVal != 1)
         O << "," << ScaleVal;
     }
@@ -350,43 +372,25 @@
 ///
 void X86ATTAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
   ++EmittedInsts;
-  // This works around some Darwin assembler bugs.
-  if (Subtarget->isTargetDarwin()) {
-    switch (MI->getOpcode()) {
-    case X86::REP_MOVSB:
-      O << "rep/movsb (%esi),(%edi)\n";
-      return;
-    case X86::REP_MOVSD:
-      O << "rep/movsl (%esi),(%edi)\n";
-      return;
-    case X86::REP_MOVSW:
-      O << "rep/movsw (%esi),(%edi)\n";
-      return;
-    case X86::REP_STOSB:
-      O << "rep/stosb\n";
-      return;
-    case X86::REP_STOSD:
-      O << "rep/stosl\n";
-      return;
-    case X86::REP_STOSW:
-      O << "rep/stosw\n";
-      return;
-    default:
-      break;
-    }
-  }
 
   // See if a truncate instruction can be turned into a nop.
   switch (MI->getOpcode()) {
   default: break;
-  case X86::TRUNC_GR32_GR16:
-  case X86::TRUNC_GR32_GR8:
-  case X86::TRUNC_GR16_GR8: {
+  case X86::TRUNC_64to32:
+  case X86::TRUNC_64to16:
+  case X86::TRUNC_32to16:
+  case X86::TRUNC_32to8:
+  case X86::TRUNC_16to8:
+  case X86::TRUNC_32_to8:
+  case X86::TRUNC_16_to8: {
     const MachineOperand &MO0 = MI->getOperand(0);
     const MachineOperand &MO1 = MI->getOperand(1);
     unsigned Reg0 = MO0.getReg();
     unsigned Reg1 = MO1.getReg();
-    if (MI->getOpcode() == X86::TRUNC_GR32_GR16)
+    unsigned Opc = MI->getOpcode();
+    if (Opc == X86::TRUNC_64to32)
+      Reg1 = getX86SubSuperRegister(Reg1, MVT::i32);
+    else if (Opc == X86::TRUNC_32to16 || Opc == X86::TRUNC_64to16)
       Reg1 = getX86SubSuperRegister(Reg1, MVT::i16);
     else
       Reg1 = getX86SubSuperRegister(Reg1, MVT::i8);
@@ -395,6 +399,9 @@
       O << "\n\t";
     break;
   }
+  case X86::PsMOVZX64rr32:
+    O << TAI->getCommentString() << " ZERO-EXTEND " << "\n\t";
+    break;
   }
 
   // Call the autogenerated instruction printer routines.


Index: llvm/lib/Target/X86/X86ATTAsmPrinter.h
diff -u llvm/lib/Target/X86/X86ATTAsmPrinter.h:1.15 llvm/lib/Target/X86/X86ATTAsmPrinter.h:1.16
--- llvm/lib/Target/X86/X86ATTAsmPrinter.h:1.15	Thu Sep  7 17:06:40 2006
+++ llvm/lib/Target/X86/X86ATTAsmPrinter.h	Fri Sep  8 01:48:29 2006
@@ -60,6 +60,9 @@
   void printf128mem(const MachineInstr *MI, unsigned OpNo) {
     printMemReference(MI, OpNo);
   }
+  void printlea64_32mem(const MachineInstr *MI, unsigned OpNo) {
+    printMemReference(MI, OpNo, "subreg64");
+  }
   
   bool printAsmMRegister(const MachineOperand &MO, const char Mode);
   bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
@@ -69,7 +72,8 @@
   
   void printMachineInstruction(const MachineInstr *MI);
   void printSSECC(const MachineInstr *MI, unsigned Op);
-  void printMemReference(const MachineInstr *MI, unsigned Op);
+  void printMemReference(const MachineInstr *MI, unsigned Op,
+                         const char *Modifier=NULL);
   void printPICLabel(const MachineInstr *MI, unsigned Op);
   bool runOnMachineFunction(MachineFunction &F);
 };


Index: llvm/lib/Target/X86/X86AsmPrinter.cpp
diff -u llvm/lib/Target/X86/X86AsmPrinter.cpp:1.195 llvm/lib/Target/X86/X86AsmPrinter.cpp:1.196
--- llvm/lib/Target/X86/X86AsmPrinter.cpp:1.195	Thu Sep  7 17:06:40 2006
+++ llvm/lib/Target/X86/X86AsmPrinter.cpp	Fri Sep  8 01:48:29 2006
@@ -30,8 +30,12 @@
                                "Number of machine instrs printed");
 
 /// doInitialization
-bool X86SharedAsmPrinter::doInitialization(Module &M) {  
+bool X86SharedAsmPrinter::doInitialization(Module &M) {
   if (Subtarget->isTargetDarwin()) {
+    const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
+    if (!Subtarget->is64Bit())
+      X86PICStyle = PICStyle::Stub;
+
     // Emit initial debug information.
     DW.BeginModule(&M);
   }


Index: llvm/lib/Target/X86/X86AsmPrinter.h
diff -u llvm/lib/Target/X86/X86AsmPrinter.h:1.29 llvm/lib/Target/X86/X86AsmPrinter.h:1.30
--- llvm/lib/Target/X86/X86AsmPrinter.h:1.29	Thu Sep  7 17:06:40 2006
+++ llvm/lib/Target/X86/X86AsmPrinter.h	Fri Sep  8 01:48:29 2006
@@ -29,12 +29,19 @@
 
 extern Statistic<> EmittedInsts;
 
+// FIXME: Move this to CodeGen/AsmPrinter.h
+namespace PICStyle {
+  enum X86AsmPICStyle {
+    Stub, GOT
+  };
+}
+
 struct VISIBILITY_HIDDEN X86SharedAsmPrinter : public AsmPrinter {
   DwarfWriter DW;
 
   X86SharedAsmPrinter(std::ostream &O, X86TargetMachine &TM,
                       const TargetAsmInfo *T)
-    : AsmPrinter(O, TM, T), DW(O, this, T) {
+    : AsmPrinter(O, TM, T), DW(O, this, T), X86PICStyle(PICStyle::GOT) {
     Subtarget = &TM.getSubtarget<X86Subtarget>();
   }
 
@@ -49,6 +56,8 @@
     MachineFunctionPass::getAnalysisUsage(AU);
   }
 
+  PICStyle::X86AsmPICStyle X86PICStyle;
+  
   const X86Subtarget *Subtarget;
 
   // Necessary for Darwin to print out the apprioriate types of linker stubs


Index: llvm/lib/Target/X86/X86CodeEmitter.cpp
diff -u llvm/lib/Target/X86/X86CodeEmitter.cpp:1.118 llvm/lib/Target/X86/X86CodeEmitter.cpp:1.119
--- llvm/lib/Target/X86/X86CodeEmitter.cpp:1.118	Wed Sep  6 20:17:57 2006
+++ llvm/lib/Target/X86/X86CodeEmitter.cpp	Fri Sep  8 01:48:29 2006
@@ -12,6 +12,8 @@
 //
 //===----------------------------------------------------------------------===//
 
+#include "X86InstrInfo.h"
+#include "X86Subtarget.h"
 #include "X86TargetMachine.h"
 #include "X86Relocations.h"
 #include "X86.h"
@@ -35,14 +37,16 @@
 namespace {
   class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass {
     const X86InstrInfo  *II;
-    TargetMachine &TM;
+    const TargetData    *TD;
+    TargetMachine       &TM;
     MachineCodeEmitter  &MCE;
+    bool Is64BitMode;
   public:
     explicit Emitter(TargetMachine &tm, MachineCodeEmitter &mce)
-      : II(0), TM(tm), MCE(mce) {}
+      : II(0), TD(0), TM(tm), MCE(mce), Is64BitMode(false) {}
     Emitter(TargetMachine &tm, MachineCodeEmitter &mce,
-            const X86InstrInfo& ii)
-      : II(&ii), TM(tm), MCE(mce) {}
+            const X86InstrInfo &ii, const TargetData &td, bool is64)
+      : II(&ii), TD(&td), TM(tm), MCE(mce), Is64BitMode(is64) {}
 
     bool runOnMachineFunction(MachineFunction &MF);
 
@@ -54,20 +58,29 @@
 
   private:
     void emitPCRelativeBlockAddress(MachineBasicBlock *MBB);
-    void emitPCRelativeValue(unsigned Address);
-    void emitGlobalAddressForCall(GlobalValue *GV, bool isTailCall);
-    void emitGlobalAddressForPtr(GlobalValue *GV, int Disp = 0);
+    void emitPCRelativeValue(intptr_t Address);
+    void emitGlobalAddressForCall(GlobalValue *GV, bool DoesntNeedStub);
+    void emitGlobalAddressForPtr(GlobalValue *GV, bool isPCRelative,
+                                 int Disp = 0, unsigned PCAdj = 0);
     void emitExternalSymbolAddress(const char *ES, bool isPCRelative);
+    void emitPCRelativeConstPoolAddress(unsigned CPI, int Disp = 0,
+                                        unsigned PCAdj = 0);
+    void emitPCRelativeJumpTableAddress(unsigned JTI, unsigned PCAdj = 0);
 
-    void emitDisplacementField(const MachineOperand *RelocOp, int DispVal);
+    void emitDisplacementField(const MachineOperand *RelocOp, int DispVal,
+                               unsigned PCAdj = 0);
 
     void emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeField);
     void emitSIBByte(unsigned SS, unsigned Index, unsigned Base);
-    void emitConstant(unsigned Val, unsigned Size);
+    void emitConstant(uint64_t Val, unsigned Size);
 
     void emitMemModRMByte(const MachineInstr &MI,
-                          unsigned Op, unsigned RegOpcodeField);
+                          unsigned Op, unsigned RegOpcodeField,
+                          unsigned PCAdj = 0);
 
+    unsigned getX86RegNum(unsigned RegNo);
+    bool isX86_64ExtendedReg(const MachineOperand &MO);
+    unsigned determineREX(const MachineInstr &MI);
   };
 }
 
@@ -83,6 +96,9 @@
           MF.getTarget().getRelocationModel() != Reloc::Static) &&
          "JIT relocation model must be set to static or default!");
   II = ((X86TargetMachine&)MF.getTarget()).getInstrInfo();
+  TD = ((X86TargetMachine&)MF.getTarget()).getTargetData();
+  Is64BitMode =
+    ((X86TargetMachine&)MF.getTarget()).getSubtarget<X86Subtarget>().is64Bit();
 
   do {
     MCE.startFunction(MF);
@@ -98,9 +114,9 @@
   return false;
 }
 
-/// emitPCRelativeValue - Emit a 32-bit PC relative address.
+/// emitPCRelativeValue - Emit a PC relative address.
 ///
-void Emitter::emitPCRelativeValue(unsigned Address) {
+void Emitter::emitPCRelativeValue(intptr_t Address) {
   MCE.emitWordLE(Address-MCE.getCurrentPCValue()-4);
 }
 
@@ -119,20 +135,22 @@
 /// emitGlobalAddressForCall - Emit the specified address to the code stream
 /// assuming this is part of a function call, which is PC relative.
 ///
-void Emitter::emitGlobalAddressForCall(GlobalValue *GV, bool isTailCall) {
+void Emitter::emitGlobalAddressForCall(GlobalValue *GV, bool DoesntNeedStub) {
   MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
                                       X86::reloc_pcrel_word, GV, 0,
-                                      !isTailCall /*Doesn'tNeedStub*/));
+                                      DoesntNeedStub));
   MCE.emitWordLE(0);
 }
 
 /// emitGlobalAddress - Emit the specified address to the code stream assuming
-/// this is part of a "take the address of a global" instruction, which is not
-/// PC relative.
+/// this is part of a "take the address of a global" instruction.
 ///
-void Emitter::emitGlobalAddressForPtr(GlobalValue *GV, int Disp /* = 0 */) {
-  MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
-                                      X86::reloc_absolute_word, GV));
+void Emitter::emitGlobalAddressForPtr(GlobalValue *GV, bool isPCRelative,
+                                      int Disp /* = 0 */,
+                                      unsigned PCAdj /* = 0 */) {
+  unsigned rt = isPCRelative ? X86::reloc_pcrel_word : X86::reloc_absolute_word;
+  MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), rt,
+                                             GV, PCAdj));
   MCE.emitWordLE(Disp); // The relocated value will be added to the displacement
 }
 
@@ -145,6 +163,26 @@
   MCE.emitWordLE(0);
 }
 
+/// emitPCRelativeConstPoolAddress - Arrange for the address of an constant pool
+/// to be emitted to the current location in the function, and allow it to be PC
+/// relative.
+void Emitter::emitPCRelativeConstPoolAddress(unsigned CPI, int Disp /* = 0 */,
+                                             unsigned PCAdj /* = 0 */) {
+  MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
+                                            X86::reloc_pcrel_word, CPI, PCAdj));
+  MCE.emitWordLE(Disp); // The relocated value will be added to the displacement
+}
+
+/// emitPCRelativeJumpTableAddress - Arrange for the address of a jump table to
+/// be emitted to the current location in the function, and allow it to be PC
+/// relative.
+void Emitter::emitPCRelativeJumpTableAddress(unsigned JTI,
+                                             unsigned PCAdj /* = 0 */) {
+  MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
+                                            X86::reloc_pcrel_word, JTI, PCAdj));
+  MCE.emitWordLE(0); // The relocated value will be added to the displacement
+}
+
 /// N86 namespace - Native X86 Register numbers... used by X86 backend.
 ///
 namespace N86 {
@@ -153,28 +191,53 @@
   };
 }
 
-
 // getX86RegNum - This function maps LLVM register identifiers to their X86
 // specific numbering, which is used in various places encoding instructions.
 //
-static unsigned getX86RegNum(unsigned RegNo) {
+unsigned Emitter::getX86RegNum(unsigned RegNo) {
   switch(RegNo) {
-  case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
-  case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
-  case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
-  case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
-  case X86::ESP: case X86::SP: case X86::AH: return N86::ESP;
-  case X86::EBP: case X86::BP: case X86::CH: return N86::EBP;
-  case X86::ESI: case X86::SI: case X86::DH: return N86::ESI;
-  case X86::EDI: case X86::DI: case X86::BH: return N86::EDI;
+  case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
+  case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
+  case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
+  case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
+  case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
+    return N86::ESP;
+  case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
+    return N86::EBP;
+  case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
+    return N86::ESI;
+  case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
+    return N86::EDI;
+
+  case X86::R8:  case X86::R8D:  case X86::R8W:  case X86::R8B:
+    return N86::EAX;
+  case X86::R9:  case X86::R9D:  case X86::R9W:  case X86::R9B:
+    return N86::ECX;
+  case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
+    return N86::EDX;
+  case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
+    return N86::EBX;
+  case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
+    return N86::ESP;
+  case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
+    return N86::EBP;
+  case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
+    return N86::ESI;
+  case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
+    return N86::EDI;
 
   case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
   case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
     return RegNo-X86::ST0;
 
-  case X86::XMM0: case X86::XMM1: case X86::XMM2: case X86::XMM3:
-  case X86::XMM4: case X86::XMM5: case X86::XMM6: case X86::XMM7:
-    return RegNo-X86::XMM0;
+  case X86::XMM0:  case X86::XMM1:  case X86::XMM2:  case X86::XMM3:
+  case X86::XMM4:  case X86::XMM5:  case X86::XMM6:  case X86::XMM7:
+    return II->getRegisterInfo().getDwarfRegNum(RegNo) -
+           II->getRegisterInfo().getDwarfRegNum(X86::XMM0);
+  case X86::XMM8:  case X86::XMM9:  case X86::XMM10: case X86::XMM11:
+  case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
+    return II->getRegisterInfo().getDwarfRegNum(RegNo) -
+           II->getRegisterInfo().getDwarfRegNum(X86::XMM8);
 
   default:
     assert(MRegisterInfo::isVirtualRegister(RegNo) &&
@@ -199,7 +262,7 @@
   MCE.emitByte(ModRMByte(SS, Index, Base));
 }
 
-void Emitter::emitConstant(unsigned Val, unsigned Size) {
+void Emitter::emitConstant(uint64_t Val, unsigned Size) {
   // Output the constant in little endian byte order...
   for (unsigned i = 0; i != Size; ++i) {
     MCE.emitByte(Val & 255);
@@ -214,7 +277,7 @@
 }
 
 void Emitter::emitDisplacementField(const MachineOperand *RelocOp,
-                                    int DispVal) {
+                                    int DispVal, unsigned PCAdj) {
   // If this is a simple integer displacement that doesn't require a relocation,
   // emit it now.
   if (!RelocOp) {
@@ -225,14 +288,27 @@
   // Otherwise, this is something that requires a relocation.  Emit it as such
   // now.
   if (RelocOp->isGlobalAddress()) {
-    emitGlobalAddressForPtr(RelocOp->getGlobal(), RelocOp->getOffset());
+    // In 64-bit static small code model, we could potentially emit absolute.
+    // But it's probably not beneficial.
+    //  89 05 00 00 00 00    	mov    %eax,0(%rip)  # PC-relative
+    //	89 04 25 00 00 00 00 	mov    %eax,0x0      # Absolute
+    emitGlobalAddressForPtr(RelocOp->getGlobal(), Is64BitMode,
+                            RelocOp->getOffset(), PCAdj);
+  } else if (RelocOp->isConstantPoolIndex()) {
+    // Must be in 64-bit mode.
+    emitPCRelativeConstPoolAddress(RelocOp->getConstantPoolIndex(),
+                                   RelocOp->getOffset(), PCAdj);
+  } else if (RelocOp->isJumpTableIndex()) {
+    // Must be in 64-bit mode.
+    emitPCRelativeJumpTableAddress(RelocOp->getJumpTableIndex(), PCAdj);
   } else {
     assert(0 && "Unknown value to relocate!");
   }
 }
 
 void Emitter::emitMemModRMByte(const MachineInstr &MI,
-                               unsigned Op, unsigned RegOpcodeField) {
+                               unsigned Op, unsigned RegOpcodeField,
+                               unsigned PCAdj) {
   const MachineOperand &Op3 = MI.getOperand(Op+3);
   int DispVal = 0;
   const MachineOperand *DispForReloc = 0;
@@ -241,10 +317,18 @@
   if (Op3.isGlobalAddress()) {
     DispForReloc = &Op3;
   } else if (Op3.isConstantPoolIndex()) {
-    DispVal += MCE.getConstantPoolEntryAddress(Op3.getConstantPoolIndex());
-    DispVal += Op3.getOffset();
+    if (Is64BitMode) {
+      DispForReloc = &Op3;
+    } else {
+      DispVal += MCE.getConstantPoolEntryAddress(Op3.getConstantPoolIndex());
+      DispVal += Op3.getOffset();
+    }
   } else if (Op3.isJumpTableIndex()) {
-    DispVal += MCE.getJumpTableEntryAddress(Op3.getJumpTableIndex());
+    if (Is64BitMode) {
+      DispForReloc = &Op3;
+    } else {
+      DispVal += MCE.getJumpTableEntryAddress(Op3.getJumpTableIndex());
+    }
   } else {
     DispVal = Op3.getImm();
   }
@@ -256,12 +340,13 @@
   unsigned BaseReg = Base.getReg();
 
   // Is a SIB byte needed?
-  if (IndexReg.getReg() == 0 && BaseReg != X86::ESP) {
+  if (IndexReg.getReg() == 0 &&
+      (BaseReg == 0 || getX86RegNum(BaseReg) != N86::ESP)) {
     if (BaseReg == 0) {  // Just a displacement?
       // Emit special case [disp32] encoding
       MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
       
-      emitDisplacementField(DispForReloc, DispVal);
+      emitDisplacementField(DispForReloc, DispVal, PCAdj);
     } else {
       unsigned BaseRegNo = getX86RegNum(BaseReg);
       if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
@@ -274,12 +359,13 @@
       } else {
         // Emit the most general non-SIB encoding: [REG+disp32]
         MCE.emitByte(ModRMByte(2, RegOpcodeField, BaseRegNo));
-        emitDisplacementField(DispForReloc, DispVal);
+        emitDisplacementField(DispForReloc, DispVal, PCAdj);
       }
     }
 
   } else {  // We need a SIB byte, so start by outputting the ModR/M byte first
-    assert(IndexReg.getReg() != X86::ESP && "Cannot use ESP as index reg!");
+    assert(IndexReg.getReg() != X86::ESP &&
+           IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
 
     bool ForceDisp32 = false;
     bool ForceDisp8  = false;
@@ -292,7 +378,7 @@
       // Emit the normal disp32 encoding.
       MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
       ForceDisp32 = true;
-    } else if (DispVal == 0 && BaseReg != X86::EBP) {
+    } else if (DispVal == 0 && getX86RegNum(BaseReg) != N86::EBP) {
       // Emit no displacement ModR/M byte
       MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
     } else if (isDisp8(DispVal)) {
@@ -327,7 +413,7 @@
     if (ForceDisp8) {
       emitConstant(DispVal, 1);
     } else if (DispVal != 0 || ForceDisp32) {
-      emitDisplacementField(DispForReloc, DispVal);
+      emitDisplacementField(DispForReloc, DispVal, PCAdj);
     }
   }
 }
@@ -337,11 +423,131 @@
   case X86II::Imm8:   return 1;
   case X86II::Imm16:  return 2;
   case X86II::Imm32:  return 4;
+  case X86II::Imm64:  return 8;
   default: assert(0 && "Immediate size not set!");
     return 0;
   }
 }
 
+/// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended register?
+/// e.g. r8, xmm8, etc.
+bool Emitter::isX86_64ExtendedReg(const MachineOperand &MO) {
+  if (!MO.isRegister()) return false;
+  unsigned RegNo = MO.getReg();
+  int DWNum = II->getRegisterInfo().getDwarfRegNum(RegNo);
+  if (DWNum >= II->getRegisterInfo().getDwarfRegNum(X86::R8) &&
+      DWNum <= II->getRegisterInfo().getDwarfRegNum(X86::R15))
+    return true;
+  if (DWNum >= II->getRegisterInfo().getDwarfRegNum(X86::XMM8) &&
+      DWNum <= II->getRegisterInfo().getDwarfRegNum(X86::XMM15))
+    return true;
+  return false;
+}
+
+inline static bool isX86_64TruncToByte(unsigned oc) {
+  return (oc == X86::TRUNC_64to8 || oc == X86::TRUNC_32to8 ||
+          oc == X86::TRUNC_16to8);
+}
+
+
+inline static bool isX86_64NonExtLowByteReg(unsigned reg) {
+  return (reg == X86::SPL || reg == X86::BPL ||
+          reg == X86::SIL || reg == X86::DIL);
+}
+
+/// determineREX - Determine if the MachineInstr has to be encoded with a X86-64
+/// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
+/// size, and 3) use of X86-64 extended registers.
+unsigned Emitter::determineREX(const MachineInstr &MI) {
+  unsigned REX = 0;
+  unsigned Opcode = MI.getOpcode();
+  const TargetInstrDescriptor &Desc = II->get(Opcode);
+
+  // Pseudo instructions do not need REX prefix byte.
+  if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo)
+    return 0;
+  if (Desc.TSFlags & X86II::REX_W)
+    REX |= 1 << 3;
+
+  if (MI.getNumOperands()) {
+    // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
+    bool isTrunc8 = isX86_64TruncToByte(Opcode);
+    for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
+      const MachineOperand& MO = MI.getOperand(i);
+      if (MO.isRegister()) {
+	unsigned Reg = MO.getReg();
+	// Trunc to byte are actually movb. The real source operand is the low
+	// byte of the register.
+	if (isTrunc8 && i == 1)
+	  Reg = getX86SubSuperRegister(Reg, MVT::i8);
+	if (isX86_64NonExtLowByteReg(Reg))
+	  REX |= 0x40;
+      }
+    }
+
+    switch (Desc.TSFlags & X86II::FormMask) {
+    case X86II::MRMInitReg:
+      if (isX86_64ExtendedReg(MI.getOperand(0)))
+        REX |= (1 << 0) | (1 << 2);
+      break;
+    case X86II::MRMSrcReg: {
+      if (isX86_64ExtendedReg(MI.getOperand(0)))
+        REX |= 1 << 2;
+      for (unsigned i = 1, e = MI.getNumOperands(); i != e; ++i) {
+        const MachineOperand& MO = MI.getOperand(i);
+        if (isX86_64ExtendedReg(MO))
+          REX |= 1 << 0;
+      }
+      break;
+    }
+    case X86II::MRMSrcMem: {
+      if (isX86_64ExtendedReg(MI.getOperand(0)))
+        REX |= 1 << 2;
+      unsigned Bit = 0;
+      for (unsigned i = 1; i != 5; ++i) {
+        const MachineOperand& MO = MI.getOperand(i);
+        if (MO.isRegister()) {
+          if (isX86_64ExtendedReg(MO))
+            REX |= 1 << Bit;
+          Bit++;
+        }
+      }
+      break;
+    }
+    case X86II::MRM0m: case X86II::MRM1m:
+    case X86II::MRM2m: case X86II::MRM3m:
+    case X86II::MRM4m: case X86II::MRM5m:
+    case X86II::MRM6m: case X86II::MRM7m:
+    case X86II::MRMDestMem: {
+      if (MI.getNumOperands() >= 5 &&
+          isX86_64ExtendedReg(MI.getOperand(4)))
+        REX |= 1 << 2;
+      unsigned Bit = 0;
+      for (unsigned i = 0; i != 4; ++i) {
+        const MachineOperand& MO = MI.getOperand(i);
+        if (MO.isRegister()) {
+          if (isX86_64ExtendedReg(MO))
+            REX |= 1 << Bit;
+          Bit++;
+        }
+      }
+      break;
+    }
+    default: {
+      if (isX86_64ExtendedReg(MI.getOperand(0)))
+        REX |= 1 << 0;
+      for (unsigned i = 1, e = MI.getNumOperands(); i != e; ++i) {
+        const MachineOperand& MO = MI.getOperand(i);
+        if (isX86_64ExtendedReg(MO))
+          REX |= 1 << 2;
+      }
+      break;
+    }
+    }
+  }
+  return REX;
+}
+
 void Emitter::emitInstruction(const MachineInstr &MI) {
   NumEmitted++;  // Keep track of the # of mi's emitted
 
@@ -354,18 +560,22 @@
   // Emit the operand size opcode prefix as needed.
   if (Desc.TSFlags & X86II::OpSize) MCE.emitByte(0x66);
 
+  // Emit the address size opcode prefix as needed.
+  if (Desc.TSFlags & X86II::AdSize) MCE.emitByte(0x67);
+
+  bool Need0FPrefix = false;
   switch (Desc.TSFlags & X86II::Op0Mask) {
   case X86II::TB:
-    MCE.emitByte(0x0F);   // Two-byte opcode prefix
+    Need0FPrefix = true;   // Two-byte opcode prefix
     break;
   case X86II::REP: break; // already handled.
   case X86II::XS:   // F3 0F
     MCE.emitByte(0xF3);
-    MCE.emitByte(0x0F);
+    Need0FPrefix = true;
     break;
   case X86II::XD:   // F2 0F
     MCE.emitByte(0xF2);
-    MCE.emitByte(0x0F);
+    Need0FPrefix = true;
     break;
   case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
   case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
@@ -377,6 +587,17 @@
   case 0: break;  // No prefix!
   }
 
+  if (Is64BitMode) {
+    // REX prefix
+    unsigned REX = determineREX(MI);
+    if (REX)
+      MCE.emitByte(0x40 | REX);
+  }
+
+  // 0x0F escape code must be emitted just before the opcode.
+  if (Need0FPrefix)
+    MCE.emitByte(0x0F);
+
   // If this is a two-address instruction, skip one of the register operands.
   unsigned CurOp = 0;
   CurOp += (Desc.Flags & M_2_ADDR_FLAG) != 0;
@@ -397,6 +618,7 @@
     case X86::IMPLICIT_DEF_GR8:
     case X86::IMPLICIT_DEF_GR16:
     case X86::IMPLICIT_DEF_GR32:
+    case X86::IMPLICIT_DEF_GR64:
     case X86::IMPLICIT_DEF_FR32:
     case X86::IMPLICIT_DEF_FR64:
     case X86::IMPLICIT_DEF_VR64:
@@ -417,7 +639,7 @@
       } else if (MO.isGlobalAddress()) {
         bool isTailCall = Opcode == X86::TAILJMPd ||
                           Opcode == X86::TAILJMPr || Opcode == X86::TAILJMPm;
-        emitGlobalAddressForCall(MO.getGlobal(), isTailCall);
+        emitGlobalAddressForCall(MO.getGlobal(), !isTailCall);
       } else if (MO.isExternalSymbol()) {
         emitExternalSymbolAddress(MO.getSymbolName(), true);
       } else if (MO.isImmediate()) {
@@ -434,15 +656,15 @@
     if (CurOp != MI.getNumOperands()) {
       const MachineOperand &MO1 = MI.getOperand(CurOp++);
       if (MO1.isGlobalAddress()) {
-        assert(sizeOfImm(Desc) == 4 &&
+        assert(sizeOfImm(Desc) == TD->getPointerSize() &&
                "Don't know how to emit non-pointer values!");
-        emitGlobalAddressForPtr(MO1.getGlobal(), MO1.getOffset());
+        emitGlobalAddressForPtr(MO1.getGlobal(), Is64BitMode, MO1.getOffset());
       } else if (MO1.isExternalSymbol()) {
-        assert(sizeOfImm(Desc) == 4 &&
+        assert(sizeOfImm(Desc) == TD->getPointerSize() &&
                "Don't know how to emit non-pointer values!");
         emitExternalSymbolAddress(MO1.getSymbolName(), false);
       } else if (MO1.isJumpTableIndex()) {
-        assert(sizeOfImm(Desc) == 4 &&
+        assert(sizeOfImm(Desc) == TD->getPointerSize() &&
                "Don't know how to emit non-pointer values!");
         emitConstant(MCE.getJumpTableEntryAddress(MO1.getJumpTableIndex()), 4);
       } else {
@@ -460,13 +682,14 @@
       emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
     break;
   }
-  case X86II::MRMDestMem:
+  case X86II::MRMDestMem: {
     MCE.emitByte(BaseOpcode);
     emitMemModRMByte(MI, CurOp, getX86RegNum(MI.getOperand(CurOp+4).getReg()));
     CurOp += 5;
     if (CurOp != MI.getNumOperands())
       emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
     break;
+  }
 
   case X86II::MRMSrcReg:
     MCE.emitByte(BaseOpcode);
@@ -477,13 +700,17 @@
       emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
     break;
 
-  case X86II::MRMSrcMem:
+  case X86II::MRMSrcMem: {
+    unsigned PCAdj = (CurOp+5 != MI.getNumOperands()) ? sizeOfImm(Desc) : 0;
+
     MCE.emitByte(BaseOpcode);
-    emitMemModRMByte(MI, CurOp+1, getX86RegNum(MI.getOperand(CurOp).getReg()));
+    emitMemModRMByte(MI, CurOp+1, getX86RegNum(MI.getOperand(CurOp).getReg()),
+                     PCAdj);
     CurOp += 5;
     if (CurOp != MI.getNumOperands())
       emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
     break;
+  }
 
   case X86II::MRM0r: case X86II::MRM1r:
   case X86II::MRM2r: case X86II::MRM3r:
@@ -500,9 +727,13 @@
   case X86II::MRM0m: case X86II::MRM1m:
   case X86II::MRM2m: case X86II::MRM3m:
   case X86II::MRM4m: case X86II::MRM5m:
-  case X86II::MRM6m: case X86II::MRM7m:
+  case X86II::MRM6m: case X86II::MRM7m: {
+    unsigned PCAdj = (CurOp+4 != MI.getNumOperands()) ?
+      (MI.getOperand(CurOp+4).isImmediate() ? sizeOfImm(Desc) : 4) : 0;
+
     MCE.emitByte(BaseOpcode);
-    emitMemModRMByte(MI, CurOp, (Desc.TSFlags & X86II::FormMask)-X86II::MRM0m);
+    emitMemModRMByte(MI, CurOp, (Desc.TSFlags & X86II::FormMask)-X86II::MRM0m,
+                     PCAdj);
     CurOp += 4;
 
     if (CurOp != MI.getNumOperands()) {
@@ -510,13 +741,14 @@
       if (MO.isImmediate())
         emitConstant(MO.getImm(), sizeOfImm(Desc));
       else if (MO.isGlobalAddress())
-        emitGlobalAddressForPtr(MO.getGlobal(), MO.getOffset());
+        emitGlobalAddressForPtr(MO.getGlobal(), Is64BitMode, MO.getOffset());
       else if (MO.isJumpTableIndex())
         emitConstant(MCE.getJumpTableEntryAddress(MO.getJumpTableIndex()), 4);
       else
         assert(0 && "Unknown operand!");
     }
     break;
+  }
 
   case X86II::MRMInitReg:
     MCE.emitByte(BaseOpcode);


Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.104 llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.105
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.104	Fri Sep  1 17:52:28 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp	Fri Sep  8 01:48:29 2006
@@ -30,8 +30,9 @@
 #include "llvm/CodeGen/SSARegMap.h"
 #include "llvm/CodeGen/SelectionDAGISel.h"
 #include "llvm/Target/TargetMachine.h"
-#include "llvm/Support/Debug.h"
 #include "llvm/Support/Compiler.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/MathExtras.h"
 #include "llvm/ADT/Statistic.h"
 #include <deque>
 #include <iostream>
@@ -58,16 +59,19 @@
       int FrameIndex;
     } Base;
 
+    bool isRIPRel;     // RIP relative?
     unsigned Scale;
     SDOperand IndexReg; 
     unsigned Disp;
     GlobalValue *GV;
     Constant *CP;
+    const char *ES;
+    int JT;
     unsigned Align;    // CP alignment.
 
     X86ISelAddressMode()
-      : BaseType(RegBase), Scale(1), IndexReg(), Disp(0), GV(0),
-        CP(0), Align(0) {
+      : BaseType(RegBase), isRIPRel(false), Scale(1), IndexReg(), Disp(0),
+        GV(0), CP(0), ES(0), JT(-1), Align(0) {
     }
   };
 }
@@ -92,6 +96,10 @@
     ///
     bool FastISel;
 
+    /// TM - Keep a reference to X86TargetMachine.
+    ///
+    X86TargetMachine &TM;
+
     /// X86Lowering - This object fully describes how to lower LLVM code to an
     /// X86-specific SelectionDAG.
     X86TargetLowering X86Lowering;
@@ -100,12 +108,14 @@
     /// make the right decision when generating code for different targets.
     const X86Subtarget *Subtarget;
 
+    /// GlobalBaseReg - keeps track of the virtual register mapped onto global
+    /// base register.
     unsigned GlobalBaseReg;
 
   public:
-    X86DAGToDAGISel(X86TargetMachine &TM, bool fast)
+    X86DAGToDAGISel(X86TargetMachine &tm, bool fast)
       : SelectionDAGISel(X86Lowering),
-        ContainsFPCode(false), FastISel(fast), 
+        ContainsFPCode(false), FastISel(fast), TM(tm),
         X86Lowering(*TM.getTargetLowering()),
         Subtarget(&TM.getSubtarget<X86Subtarget>()) {}
 
@@ -156,13 +166,22 @@
                                    SDOperand &Scale, SDOperand &Index,
                                    SDOperand &Disp) {
       Base  = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ?
-        CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, MVT::i32) : AM.Base.Reg;
+        CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, TLI.getPointerTy()) :
+        AM.Base.Reg;
       Scale = getI8Imm(AM.Scale);
       Index = AM.IndexReg;
-      Disp  = AM.GV ? CurDAG->getTargetGlobalAddress(AM.GV, MVT::i32, AM.Disp)
-        : (AM.CP ?
-           CurDAG->getTargetConstantPool(AM.CP, MVT::i32, AM.Align, AM.Disp)
-           : getI32Imm(AM.Disp));
+      // These are 32-bit even in 64-bit mode since RIP relative offset
+      // is 32-bit.
+      if (AM.GV)
+        Disp = CurDAG->getTargetGlobalAddress(AM.GV, MVT::i32, AM.Disp);
+      else if (AM.CP)
+        Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32, AM.Align, AM.Disp);
+      else if (AM.ES)
+        Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32);
+      else if (AM.JT != -1)
+        Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32);
+      else
+        Disp = getI32Imm(AM.Disp);
     }
 
     /// getI8Imm - Return a target constant with the specified value, of type
@@ -476,26 +495,56 @@
 /// addressing mode
 bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM,
                                    bool isRoot) {
+  // RIP relative addressing: %rip + 32-bit displacement!
+  if (AM.isRIPRel) {
+    if (!AM.ES && AM.JT != -1 && N.getOpcode() == ISD::Constant) {
+      uint64_t Val = cast<ConstantSDNode>(N)->getValue();
+      if (isInt32(AM.Disp + Val)) {
+        AM.Disp += Val;
+        return false;
+      }
+    }
+    return true;
+  }
+
   int id = N.Val->getNodeId();
   bool Available = isSelected(id);
 
   switch (N.getOpcode()) {
   default: break;
-  case ISD::Constant:
-    AM.Disp += cast<ConstantSDNode>(N)->getValue();
-    return false;
+  case ISD::Constant: {
+    uint64_t Val = cast<ConstantSDNode>(N)->getValue();
+    if (isInt32(AM.Disp + Val)) {
+      AM.Disp += Val;
+      return false;
+    }
+    break;
+  }
 
   case X86ISD::Wrapper:
-    // If both base and index components have been picked, we can't fit
-    // the result available in the register in the addressing mode. Duplicate
-    // GlobalAddress or ConstantPool as displacement.
-    if (!Available || (AM.Base.Reg.Val && AM.IndexReg.Val)) {
+    // If value is available in a register both base and index components have
+    // been picked, we can't fit the result available in the register in the
+    // addressing mode. Duplicate GlobalAddress or ConstantPool as displacement.
+
+    // Can't fit GV or CP in addressing mode for X86-64 medium or large code
+    // model since the displacement field is 32-bit. Ok for small code model.
+
+    // For X86-64 PIC code, only allow GV / CP + displacement so we can use RIP
+    // relative addressing mode.
+    if ((!Subtarget->is64Bit() || TM.getCodeModel() == CodeModel::Small) &&
+        (!Available || (AM.Base.Reg.Val && AM.IndexReg.Val))) {
+      bool isRIP = Subtarget->is64Bit();
+      if (isRIP && (AM.Base.Reg.Val || AM.Scale > 1 || AM.IndexReg.Val ||
+                    AM.BaseType == X86ISelAddressMode::FrameIndexBase))
+        break;
       if (ConstantPoolSDNode *CP =
           dyn_cast<ConstantPoolSDNode>(N.getOperand(0))) {
         if (AM.CP == 0) {
           AM.CP = CP->get();
           AM.Align = CP->getAlignment();
           AM.Disp += CP->getOffset();
+          if (isRIP)
+            AM.isRIPRel = true;
           return false;
         }
       } else if (GlobalAddressSDNode *G =
@@ -503,6 +552,20 @@
         if (AM.GV == 0) {
           AM.GV = G->getGlobal();
           AM.Disp += G->getOffset();
+          if (isRIP)
+            AM.isRIPRel = true;
+          return false;
+        }
+      } else if (isRoot && isRIP) {
+        if (ExternalSymbolSDNode *S =
+            dyn_cast<ExternalSymbolSDNode>(N.getOperand(0))) {
+          AM.ES = S->getSymbol();
+          AM.isRIPRel = true;
+          return false;
+        } else if (JumpTableSDNode *J =
+                   dyn_cast<JumpTableSDNode>(N.getOperand(0))) {
+          AM.JT = J->getIndex();
+          AM.isRIPRel = true;
           return false;
         }
       }
@@ -533,7 +596,11 @@
             AM.IndexReg = ShVal.Val->getOperand(0);
             ConstantSDNode *AddVal =
               cast<ConstantSDNode>(ShVal.Val->getOperand(1));
-            AM.Disp += AddVal->getValue() << Val;
+            uint64_t Disp = AM.Disp + AddVal->getValue() << Val;
+            if (isInt32(Disp))
+              AM.Disp = Disp;
+            else
+              AM.IndexReg = ShVal;
           } else {
             AM.IndexReg = ShVal;
           }
@@ -563,7 +630,11 @@
             Reg = MulVal.Val->getOperand(0);
             ConstantSDNode *AddVal =
               cast<ConstantSDNode>(MulVal.Val->getOperand(1));
-            AM.Disp += AddVal->getValue() * CN->getValue();
+            uint64_t Disp = AM.Disp + AddVal->getValue() * CN->getValue();
+            if (isInt32(Disp))
+              AM.Disp = Disp;
+            else
+              Reg = N.Val->getOperand(0);
           } else {
             Reg = N.Val->getOperand(0);
           }
@@ -641,13 +712,14 @@
   if (MatchAddress(N, AM))
     return false;
 
+  MVT::ValueType VT = N.getValueType();
   if (AM.BaseType == X86ISelAddressMode::RegBase) {
     if (!AM.Base.Reg.Val)
-      AM.Base.Reg = CurDAG->getRegister(0, MVT::i32);
+      AM.Base.Reg = CurDAG->getRegister(0, VT);
   }
 
   if (!AM.IndexReg.Val)
-    AM.IndexReg = CurDAG->getRegister(0, MVT::i32);
+    AM.IndexReg = CurDAG->getRegister(0, VT);
 
   getAddressOperands(AM, Base, Scale, Index, Disp);
   return true;
@@ -662,19 +734,20 @@
   if (MatchAddress(N, AM))
     return false;
 
+  MVT::ValueType VT = N.getValueType();
   unsigned Complexity = 0;
   if (AM.BaseType == X86ISelAddressMode::RegBase)
     if (AM.Base.Reg.Val)
       Complexity = 1;
     else
-      AM.Base.Reg = CurDAG->getRegister(0, MVT::i32);
+      AM.Base.Reg = CurDAG->getRegister(0, VT);
   else if (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
     Complexity = 4;
 
   if (AM.IndexReg.Val)
     Complexity++;
   else
-    AM.IndexReg = CurDAG->getRegister(0, MVT::i32);
+    AM.IndexReg = CurDAG->getRegister(0, VT);
 
   if (AM.Scale > 2) 
     Complexity += 2;
@@ -687,8 +760,14 @@
   // optimal (especially for code size consideration). LEA is nice because of
   // its three-address nature. Tweak the cost function again when we can run
   // convertToThreeAddress() at register allocation time.
-  if (AM.GV || AM.CP)
-    Complexity += 2;
+  if (AM.GV || AM.CP || AM.ES || AM.JT != -1) {
+    // For X86-64, we should always use lea to materialize RIP relative
+    // addresses.
+    if (Subtarget->is64Bit())
+      Complexity = 4;
+    else
+      Complexity += 2;
+  }
 
   if (AM.Disp && (AM.Base.Reg.Val || AM.IndexReg.Val))
     Complexity++;
@@ -721,6 +800,7 @@
 /// base address to use for accessing globals into a register.
 ///
 SDNode *X86DAGToDAGISel::getGlobalBaseReg() {
+  assert(!Subtarget->is64Bit() && "X86-64 PIC uses RIP relative addressing");
   if (!GlobalBaseReg) {
     // Insert the set of GlobalBaseReg into the first MBB of the function
     MachineBasicBlock &FirstMBB = BB->getParent()->front();
@@ -732,7 +812,7 @@
     BuildMI(FirstMBB, MBBI, X86::MovePCtoStack, 0);
     BuildMI(FirstMBB, MBBI, X86::POP32r, 1, GlobalBaseReg);
   }
-  return CurDAG->getRegister(GlobalBaseReg, MVT::i32).Val;
+  return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).Val;
 }
 
 static SDNode *FindCallStartFromCall(SDNode *Node) {
@@ -776,9 +856,11 @@
       // Turn ADD X, c to MOV32ri X+c. This cannot be done with tblgen'd
       // code and is matched first so to prevent it from being turned into
       // LEA32r X+c.
+      // In 64-bit mode, use LEA to take advantage of RIP-relative addressing.
+      MVT::ValueType PtrVT = TLI.getPointerTy();
       SDOperand N0 = N.getOperand(0);
       SDOperand N1 = N.getOperand(1);
-      if (N.Val->getValueType(0) == MVT::i32 &&
+      if (N.Val->getValueType(0) == PtrVT &&
           N0.getOpcode() == X86ISD::Wrapper &&
           N1.getOpcode() == ISD::Constant) {
         unsigned Offset = (unsigned)cast<ConstantSDNode>(N1)->getValue();
@@ -786,17 +868,23 @@
         // TODO: handle ExternalSymbolSDNode.
         if (GlobalAddressSDNode *G =
             dyn_cast<GlobalAddressSDNode>(N0.getOperand(0))) {
-          C = CurDAG->getTargetGlobalAddress(G->getGlobal(), MVT::i32,
+          C = CurDAG->getTargetGlobalAddress(G->getGlobal(), PtrVT,
                                              G->getOffset() + Offset);
         } else if (ConstantPoolSDNode *CP =
                    dyn_cast<ConstantPoolSDNode>(N0.getOperand(0))) {
-          C = CurDAG->getTargetConstantPool(CP->get(), MVT::i32,
+          C = CurDAG->getTargetConstantPool(CP->get(), PtrVT,
                                             CP->getAlignment(),
                                             CP->getOffset()+Offset);
         }
 
-        if (C.Val)
-          return CurDAG->SelectNodeTo(N.Val, X86::MOV32ri, MVT::i32, C);
+        if (C.Val) {
+          if (Subtarget->is64Bit()) {
+            SDOperand Ops[] = { CurDAG->getRegister(0, PtrVT), getI8Imm(1),
+                                CurDAG->getRegister(0, PtrVT), C };
+            return CurDAG->SelectNodeTo(N.Val, X86::LEA64r, MVT::i64, Ops, 4);
+          } else
+            return CurDAG->SelectNodeTo(N.Val, X86::MOV32ri, PtrVT, C);
+        }
       }
 
       // Other cases are handled by auto-generated code.
@@ -811,6 +899,7 @@
         case MVT::i8:  Opc = X86::MUL8r;  MOpc = X86::MUL8m;  break;
         case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
         case MVT::i32: Opc = X86::MUL32r; MOpc = X86::MUL32m; break;
+        case MVT::i64: Opc = X86::MUL64r; MOpc = X86::MUL64m; break;
         }
       else
         switch (NVT) {
@@ -818,6 +907,7 @@
         case MVT::i8:  Opc = X86::IMUL8r;  MOpc = X86::IMUL8m;  break;
         case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
         case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
+        case MVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break;
         }
 
       unsigned LoReg, HiReg;
@@ -826,6 +916,7 @@
       case MVT::i8:  LoReg = X86::AL;  HiReg = X86::AH;  break;
       case MVT::i16: LoReg = X86::AX;  HiReg = X86::DX;  break;
       case MVT::i32: LoReg = X86::EAX; HiReg = X86::EDX; break;
+      case MVT::i64: LoReg = X86::RAX; HiReg = X86::RDX; break;
       }
 
       SDOperand N0 = Node->getOperand(0);
@@ -899,6 +990,7 @@
         case MVT::i8:  Opc = X86::DIV8r;  MOpc = X86::DIV8m;  break;
         case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
         case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
+        case MVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break;
         }
       else
         switch (NVT) {
@@ -906,6 +998,7 @@
         case MVT::i8:  Opc = X86::IDIV8r;  MOpc = X86::IDIV8m;  break;
         case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
         case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
+        case MVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break;
         }
 
       unsigned LoReg, HiReg;
@@ -927,6 +1020,11 @@
         ClrOpcode  = X86::MOV32r0;
         SExtOpcode = X86::CDQ;
         break;
+      case MVT::i64:
+        LoReg = X86::RAX; HiReg = X86::RDX;
+        ClrOpcode  = X86::MOV64r0;
+        SExtOpcode = X86::CQO;
+        break;
       }
 
       SDOperand N0 = Node->getOperand(0);
@@ -994,7 +1092,7 @@
     }
 
     case ISD::TRUNCATE: {
-      if (NVT == MVT::i8) {
+      if (!Subtarget->is64Bit() && NVT == MVT::i8) {
         unsigned Opc2;
         MVT::ValueType VT;
         switch (Node->getOperand(0).getValueType()) {
@@ -1002,12 +1100,12 @@
         case MVT::i16:
           Opc = X86::MOV16to16_;
           VT = MVT::i16;
-          Opc2 = X86::TRUNC_GR16_GR8;
+          Opc2 = X86::TRUNC_16_to8;
           break;
         case MVT::i32:
           Opc = X86::MOV32to32_;
           VT = MVT::i32;
-          Opc2 = X86::TRUNC_GR32_GR8;
+          Opc2 = X86::TRUNC_32_to8;
           break;
         }
 


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.252 llvm/lib/Target/X86/X86ISelLowering.cpp:1.253
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.252	Thu Sep  7 20:50:06 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp	Fri Sep  8 01:48:29 2006
@@ -42,6 +42,7 @@
   : TargetLowering(TM) {
   Subtarget = &TM.getSubtarget<X86Subtarget>();
   X86ScalarSSE = Subtarget->hasSSE2();
+  X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
 
   // Set up the TargetLowering object.
 
@@ -51,7 +52,7 @@
   setSetCCResultContents(ZeroOrOneSetCCResult);
   setSchedulingPreference(SchedulingForRegPressure);
   setShiftAmountFlavor(Mask);   // shl X, 32 == shl X, 0
-  setStackPointerRegisterToSaveRestore(X86::ESP);
+  setStackPointerRegisterToSaveRestore(X86StackPtr);
 
   if (!Subtarget->isTargetDarwin())
     // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
@@ -71,6 +72,8 @@
   addRegisterClass(MVT::i8, X86::GR8RegisterClass);
   addRegisterClass(MVT::i16, X86::GR16RegisterClass);
   addRegisterClass(MVT::i32, X86::GR32RegisterClass);
+  if (Subtarget->is64Bit())
+    addRegisterClass(MVT::i64, X86::GR64RegisterClass);
 
   // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
   // operation.
@@ -78,11 +81,16 @@
   setOperationAction(ISD::UINT_TO_FP       , MVT::i8   , Promote);
   setOperationAction(ISD::UINT_TO_FP       , MVT::i16  , Promote);
 
-  if (X86ScalarSSE)
-    // No SSE i64 SINT_TO_FP, so expand i32 UINT_TO_FP instead.
-    setOperationAction(ISD::UINT_TO_FP     , MVT::i32  , Expand);
-  else
+  if (Subtarget->is64Bit()) {
+    setOperationAction(ISD::UINT_TO_FP     , MVT::i64  , Expand);
     setOperationAction(ISD::UINT_TO_FP     , MVT::i32  , Promote);
+  } else {
+    if (X86ScalarSSE)
+      // If SSE i64 SINT_TO_FP is not available, expand i32 UINT_TO_FP.
+      setOperationAction(ISD::UINT_TO_FP   , MVT::i32  , Expand);
+    else
+      setOperationAction(ISD::UINT_TO_FP   , MVT::i32  , Promote);
+  }
 
   // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
   // this operation.
@@ -96,10 +104,11 @@
     setOperationAction(ISD::SINT_TO_FP     , MVT::i32  , Custom);
   }
 
-  // We can handle SINT_TO_FP and FP_TO_SINT from/to i64 even though i64
-  // isn't legal.
-  setOperationAction(ISD::SINT_TO_FP       , MVT::i64  , Custom);
-  setOperationAction(ISD::FP_TO_SINT       , MVT::i64  , Custom);
+  if (!Subtarget->is64Bit()) {
+    // Custom lower SINT_TO_FP and FP_TO_SINT from/to i64 in 32-bit mode.
+    setOperationAction(ISD::SINT_TO_FP     , MVT::i64  , Custom);
+    setOperationAction(ISD::FP_TO_SINT     , MVT::i64  , Custom);
+  }
 
   // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
   // this operation.
@@ -119,14 +128,19 @@
   setOperationAction(ISD::FP_TO_UINT       , MVT::i8   , Promote);
   setOperationAction(ISD::FP_TO_UINT       , MVT::i16  , Promote);
 
-  if (X86ScalarSSE && !Subtarget->hasSSE3())
-    // Expand FP_TO_UINT into a select.
-    // FIXME: We would like to use a Custom expander here eventually to do
-    // the optimal thing for SSE vs. the default expansion in the legalizer.
-    setOperationAction(ISD::FP_TO_UINT     , MVT::i32  , Expand);
-  else
-    // With SSE3 we can use fisttpll to convert to a signed i64.
+  if (Subtarget->is64Bit()) {
+    setOperationAction(ISD::FP_TO_UINT     , MVT::i64  , Expand);
     setOperationAction(ISD::FP_TO_UINT     , MVT::i32  , Promote);
+  } else {
+    if (X86ScalarSSE && !Subtarget->hasSSE3())
+      // Expand FP_TO_UINT into a select.
+      // FIXME: We would like to use a Custom expander here eventually to do
+      // the optimal thing for SSE vs. the default expansion in the legalizer.
+      setOperationAction(ISD::FP_TO_UINT   , MVT::i32  , Expand);
+    else
+      // With SSE3 we can use fisttpll to convert to a signed i64.
+      setOperationAction(ISD::FP_TO_UINT   , MVT::i32  , Promote);
+  }
 
   setOperationAction(ISD::BIT_CONVERT      , MVT::f32  , Expand);
   setOperationAction(ISD::BIT_CONVERT      , MVT::i32  , Expand);
@@ -135,12 +149,15 @@
   setOperationAction(ISD::BR_CC            , MVT::Other, Expand);
   setOperationAction(ISD::SELECT_CC        , MVT::Other, Expand);
   setOperationAction(ISD::MEMMOVE          , MVT::Other, Expand);
+  if (Subtarget->is64Bit())
+    setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Expand);
   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16  , Expand);
   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8   , Expand);
   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1   , Expand);
   setOperationAction(ISD::FP_ROUND_INREG   , MVT::f32  , Expand);
   setOperationAction(ISD::SEXTLOAD         , MVT::i1   , Expand);
   setOperationAction(ISD::FREM             , MVT::f64  , Expand);
+
   setOperationAction(ISD::CTPOP            , MVT::i8   , Expand);
   setOperationAction(ISD::CTTZ             , MVT::i8   , Expand);
   setOperationAction(ISD::CTLZ             , MVT::i8   , Expand);
@@ -150,13 +167,18 @@
   setOperationAction(ISD::CTPOP            , MVT::i32  , Expand);
   setOperationAction(ISD::CTTZ             , MVT::i32  , Expand);
   setOperationAction(ISD::CTLZ             , MVT::i32  , Expand);
+  if (Subtarget->is64Bit()) {
+    setOperationAction(ISD::CTPOP          , MVT::i64  , Expand);
+    setOperationAction(ISD::CTTZ           , MVT::i64  , Expand);
+    setOperationAction(ISD::CTLZ           , MVT::i64  , Expand);
+  }
+
   setOperationAction(ISD::READCYCLECOUNTER , MVT::i64  , Custom);
   setOperationAction(ISD::BSWAP            , MVT::i16  , Expand);
 
   // These should be promoted to a larger select which is supported.
   setOperationAction(ISD::SELECT           , MVT::i1   , Promote);
   setOperationAction(ISD::SELECT           , MVT::i8   , Promote);
-
   // X86 wants to expand cmov itself.
   setOperationAction(ISD::SELECT          , MVT::i16  , Custom);
   setOperationAction(ISD::SELECT          , MVT::i32  , Custom);
@@ -167,6 +189,10 @@
   setOperationAction(ISD::SETCC           , MVT::i32  , Custom);
   setOperationAction(ISD::SETCC           , MVT::f32  , Custom);
   setOperationAction(ISD::SETCC           , MVT::f64  , Custom);
+  if (Subtarget->is64Bit()) {
+    setOperationAction(ISD::SELECT        , MVT::i64  , Custom);
+    setOperationAction(ISD::SETCC         , MVT::i64  , Custom);
+  }
   // X86 ret instruction may pop stack.
   setOperationAction(ISD::RET             , MVT::Other, Custom);
   // Darwin ABI issue.
@@ -174,6 +200,12 @@
   setOperationAction(ISD::JumpTable       , MVT::i32  , Custom);
   setOperationAction(ISD::GlobalAddress   , MVT::i32  , Custom);
   setOperationAction(ISD::ExternalSymbol  , MVT::i32  , Custom);
+  if (Subtarget->is64Bit()) {
+    setOperationAction(ISD::ConstantPool  , MVT::i64  , Custom);
+    setOperationAction(ISD::JumpTable     , MVT::i64  , Custom);
+    setOperationAction(ISD::GlobalAddress , MVT::i64  , Custom);
+    setOperationAction(ISD::ExternalSymbol, MVT::i64  , Custom);
+  }
   // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
   setOperationAction(ISD::SHL_PARTS       , MVT::i32  , Custom);
   setOperationAction(ISD::SRA_PARTS       , MVT::i32  , Custom);
@@ -198,6 +230,8 @@
   setOperationAction(ISD::VAEND             , MVT::Other, Expand);
   setOperationAction(ISD::STACKSAVE,          MVT::Other, Expand); 
   setOperationAction(ISD::STACKRESTORE,       MVT::Other, Expand);
+  if (Subtarget->is64Bit())
+    setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32  , Expand);
 
   setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
@@ -441,7 +475,7 @@
     if (ObjXMMRegs) {
       // Passed in a XMM register.
       unsigned Reg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
-                                 X86::VR128RegisterClass);
+                               X86::VR128RegisterClass);
       ArgValue= DAG.getCopyFromReg(Root, Reg, ObjectVT);
       ArgValues.push_back(ArgValue);
       NumXMMRegs += ObjXMMRegs;
@@ -466,8 +500,9 @@
   bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
   if (isVarArg)
     VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
-  ReturnAddrIndex = 0;     // No return address slot generated yet.
-  BytesToPopOnReturn = 0;  // Callee pops nothing.
+  RegSaveFrameIndex = 0xAAAAAAA;  // X86-64 only.
+  ReturnAddrIndex = 0;            // No return address slot generated yet.
+  BytesToPopOnReturn = 0;         // Callee pops nothing.
   BytesCallerReserves = ArgOffset;
 
   // If this is a struct return on Darwin/X86, the callee pops the hidden struct
@@ -539,7 +574,7 @@
   NumXMMRegs = 0;
   std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
   std::vector<SDOperand> MemOpChains;
-  SDOperand StackPtr = DAG.getRegister(X86::ESP, getPointerTy());
+  SDOperand StackPtr = DAG.getRegister(X86StackPtr, getPointerTy());
   for (unsigned i = 0; i != NumOps; ++i) {
     SDOperand Arg = Op.getOperand(5+2*i);
 
@@ -751,6 +786,507 @@
   return Res.getValue(Op.ResNo);
 }
 
+
+//===----------------------------------------------------------------------===//
+//                 X86-64 C Calling Convention implementation
+//===----------------------------------------------------------------------===//
+
+/// HowToPassX86_64CCCArgument - Returns how an formal argument of the specified
+/// type should be passed. If it is through stack, returns the size of the stack
+/// slot; if it is through integer or XMM register, returns the number of
+/// integer or XMM registers are needed.
+static void
+HowToPassX86_64CCCArgument(MVT::ValueType ObjectVT,
+                           unsigned NumIntRegs, unsigned NumXMMRegs,
+                           unsigned &ObjSize, unsigned &ObjIntRegs,
+                           unsigned &ObjXMMRegs) {
+  ObjSize = 0;
+  ObjIntRegs = 0;
+  ObjXMMRegs = 0;
+
+  switch (ObjectVT) {
+  default: assert(0 && "Unhandled argument type!");
+  case MVT::i8:
+  case MVT::i16:
+  case MVT::i32:
+  case MVT::i64:
+    if (NumIntRegs < 6)
+      ObjIntRegs = 1;
+    else {
+      switch (ObjectVT) {
+      default: break;
+      case MVT::i8:  ObjSize = 1; break;
+      case MVT::i16: ObjSize = 2; break;
+      case MVT::i32: ObjSize = 4; break;
+      case MVT::i64: ObjSize = 8; break;
+      }
+    }
+    break;
+  case MVT::f32:
+  case MVT::f64:
+  case MVT::v16i8:
+  case MVT::v8i16:
+  case MVT::v4i32:
+  case MVT::v2i64:
+  case MVT::v4f32:
+  case MVT::v2f64:
+    if (NumXMMRegs < 8)
+      ObjXMMRegs = 1;
+    else {
+      switch (ObjectVT) {
+      default: break;
+      case MVT::f32:  ObjSize = 4; break;
+      case MVT::f64:  ObjSize = 8; break;
+      case MVT::v16i8:
+      case MVT::v8i16:
+      case MVT::v4i32:
+      case MVT::v2i64:
+      case MVT::v4f32:
+      case MVT::v2f64: ObjSize = 16; break;
+    }
+    break;
+  }
+  }
+}
+
+SDOperand
+X86TargetLowering::LowerX86_64CCCArguments(SDOperand Op, SelectionDAG &DAG) {
+  unsigned NumArgs = Op.Val->getNumValues() - 1;
+  MachineFunction &MF = DAG.getMachineFunction();
+  MachineFrameInfo *MFI = MF.getFrameInfo();
+  SDOperand Root = Op.getOperand(0);
+  bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
+  std::vector<SDOperand> ArgValues;
+
+  // Add DAG nodes to load the arguments...  On entry to a function on the X86,
+  // the stack frame looks like this:
+  //
+  // [RSP] -- return address
+  // [RSP + 8] -- first nonreg argument (leftmost lexically)
+  // [RSP +16] -- second nonreg argument, if 1st argument is <= 8 bytes in size
+  //    ...
+  //
+  unsigned ArgOffset = 0;   // Frame mechanisms handle retaddr slot
+  unsigned NumIntRegs = 0;  // Int regs used for parameter passing.
+  unsigned NumXMMRegs = 0;  // XMM regs used for parameter passing.
+
+  static const unsigned GPR8ArgRegs[] = {
+    X86::DIL, X86::SIL, X86::DL,  X86::CL,  X86::R8B, X86::R9B
+  };
+  static const unsigned GPR16ArgRegs[] = {
+    X86::DI,  X86::SI,  X86::DX,  X86::CX,  X86::R8W, X86::R9W
+  };
+  static const unsigned GPR32ArgRegs[] = {
+    X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D
+  };
+  static const unsigned GPR64ArgRegs[] = {
+    X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8,  X86::R9
+  };
+  static const unsigned XMMArgRegs[] = {
+    X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
+    X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
+  };
+
+  for (unsigned i = 0; i < NumArgs; ++i) {
+    MVT::ValueType ObjectVT = Op.getValue(i).getValueType();
+    unsigned ArgIncrement = 8;
+    unsigned ObjSize = 0;
+    unsigned ObjIntRegs = 0;
+    unsigned ObjXMMRegs = 0;
+
+    // FIXME: __int128 and long double support?
+    HowToPassX86_64CCCArgument(ObjectVT, NumIntRegs, NumXMMRegs,
+                               ObjSize, ObjIntRegs, ObjXMMRegs);
+    if (ObjSize > 8)
+      ArgIncrement = ObjSize;
+
+    unsigned Reg = 0;
+    SDOperand ArgValue;
+    if (ObjIntRegs || ObjXMMRegs) {
+      switch (ObjectVT) {
+      default: assert(0 && "Unhandled argument type!");
+      case MVT::i8:
+      case MVT::i16:
+      case MVT::i32:
+      case MVT::i64: {
+        TargetRegisterClass *RC = NULL;
+        switch (ObjectVT) {
+        default: break;
+        case MVT::i8: 
+          RC = X86::GR8RegisterClass;
+          Reg = GPR8ArgRegs[NumIntRegs];
+          break;
+        case MVT::i16:
+          RC = X86::GR16RegisterClass;
+          Reg = GPR16ArgRegs[NumIntRegs];
+          break;
+        case MVT::i32:
+          RC = X86::GR32RegisterClass;
+          Reg = GPR32ArgRegs[NumIntRegs];
+          break;
+        case MVT::i64:
+          RC = X86::GR64RegisterClass;
+          Reg = GPR64ArgRegs[NumIntRegs];
+          break;
+        }
+        Reg = AddLiveIn(MF, Reg, RC);
+        ArgValue = DAG.getCopyFromReg(Root, Reg, ObjectVT);
+        break;
+      }
+      case MVT::f32:
+      case MVT::f64:
+      case MVT::v16i8:
+      case MVT::v8i16:
+      case MVT::v4i32:
+      case MVT::v2i64:
+      case MVT::v4f32:
+      case MVT::v2f64: {
+        TargetRegisterClass *RC= (ObjectVT == MVT::f32) ?
+          X86::FR32RegisterClass : ((ObjectVT == MVT::f64) ?
+                              X86::FR64RegisterClass : X86::VR128RegisterClass);
+        Reg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs], RC);
+        ArgValue = DAG.getCopyFromReg(Root, Reg, ObjectVT);
+        break;
+      }
+      }
+      NumIntRegs += ObjIntRegs;
+      NumXMMRegs += ObjXMMRegs;
+    } else if (ObjSize) {
+      // XMM arguments have to be aligned on 16-byte boundary.
+      if (ObjSize == 16)
+        ArgOffset = ((ArgOffset + 15) / 16) * 16;
+      // Create the SelectionDAG nodes corresponding to a load from this
+      // parameter.
+      int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
+      SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
+      ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN,
+                             DAG.getSrcValue(NULL));
+      ArgOffset += ArgIncrement;   // Move on to the next argument.
+    }
+
+    ArgValues.push_back(ArgValue);
+  }
+
+  // If the function takes variable number of arguments, make a frame index for
+  // the start of the first vararg value... for expansion of llvm.va_start.
+  if (isVarArg) {
+    // For X86-64, if there are vararg parameters that are passed via
+    // registers, then we must store them to their spots on the stack so they
+    // may be loaded by deferencing the result of va_next.
+    VarArgsGPOffset = NumIntRegs * 8;
+    VarArgsFPOffset = 6 * 8 + NumXMMRegs * 16;
+    VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
+    RegSaveFrameIndex = MFI->CreateStackObject(6 * 8 + 8 * 16, 16);
+
+    // Store the integer parameter registers.
+    std::vector<SDOperand> MemOps;
+    SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
+    SDOperand FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
+                              DAG.getConstant(VarArgsGPOffset, getPointerTy()));
+    for (; NumIntRegs != 6; ++NumIntRegs) {
+      unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs],
+                                X86::GR64RegisterClass);
+      SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i64);
+      SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
+                                    Val, FIN, DAG.getSrcValue(NULL));
+      MemOps.push_back(Store);
+      FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
+                        DAG.getConstant(8, getPointerTy()));
+    }
+
+    // Now store the XMM (fp + vector) parameter registers.
+    FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
+                      DAG.getConstant(VarArgsFPOffset, getPointerTy()));
+    for (; NumXMMRegs != 8; ++NumXMMRegs) {
+      unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
+                                X86::VR128RegisterClass);
+      SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32);
+      SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
+                                    Val, FIN, DAG.getSrcValue(NULL));
+      MemOps.push_back(Store);
+      FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
+                        DAG.getConstant(16, getPointerTy()));
+    }
+    if (!MemOps.empty())
+        Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
+                           &MemOps[0], MemOps.size());
+  }
+
+  ArgValues.push_back(Root);
+
+  ReturnAddrIndex = 0;     // No return address slot generated yet.
+  BytesToPopOnReturn = 0;  // Callee pops nothing.
+  BytesCallerReserves = ArgOffset;
+
+  // Return the new list of results.
+  std::vector<MVT::ValueType> RetVTs(Op.Val->value_begin(),
+                                     Op.Val->value_end());
+  return DAG.getNode(ISD::MERGE_VALUES, RetVTs, &ArgValues[0],ArgValues.size());
+}
+
+SDOperand
+X86TargetLowering::LowerX86_64CCCCallTo(SDOperand Op, SelectionDAG &DAG) {
+  SDOperand Chain     = Op.getOperand(0);
+  unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue();
+  bool isVarArg       = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
+  bool isTailCall     = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
+  SDOperand Callee    = Op.getOperand(4);
+  MVT::ValueType RetVT= Op.Val->getValueType(0);
+  unsigned NumOps     = (Op.getNumOperands() - 5) / 2;
+
+  // Count how many bytes are to be pushed on the stack.
+  unsigned NumBytes = 0;
+  unsigned NumIntRegs = 0;  // Int regs used for parameter passing.
+  unsigned NumXMMRegs = 0;  // XMM regs used for parameter passing.
+
+  static const unsigned GPR8ArgRegs[] = {
+    X86::DIL, X86::SIL, X86::DL,  X86::CL,  X86::R8B, X86::R9B
+  };
+  static const unsigned GPR16ArgRegs[] = {
+    X86::DI,  X86::SI,  X86::DX,  X86::CX,  X86::R8W, X86::R9W
+  };
+  static const unsigned GPR32ArgRegs[] = {
+    X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D
+  };
+  static const unsigned GPR64ArgRegs[] = {
+    X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8,  X86::R9
+  };
+  static const unsigned XMMArgRegs[] = {
+    X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
+    X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
+  };
+
+  for (unsigned i = 0; i != NumOps; ++i) {
+    SDOperand Arg = Op.getOperand(5+2*i);
+    MVT::ValueType ArgVT = Arg.getValueType();
+
+    switch (ArgVT) {
+    default: assert(0 && "Unknown value type!");
+    case MVT::i8:
+    case MVT::i16:
+    case MVT::i32:
+    case MVT::i64:
+      if (NumIntRegs < 6)
+        ++NumIntRegs;
+      else
+        NumBytes += 8;
+      break;
+    case MVT::f32:
+    case MVT::f64:
+    case MVT::v16i8:
+    case MVT::v8i16:
+    case MVT::v4i32:
+    case MVT::v2i64:
+    case MVT::v4f32:
+    case MVT::v2f64:
+      if (NumXMMRegs < 8)
+        NumXMMRegs++;
+      else if (ArgVT == MVT::f32 || ArgVT == MVT::f64)
+        NumBytes += 8;
+      else {
+        // XMM arguments have to be aligned on 16-byte boundary.
+        NumBytes = ((NumBytes + 15) / 16) * 16;
+        NumBytes += 16;
+      }
+      break;
+    }
+  }
+
+  Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
+
+  // Arguments go on the stack in reverse order, as specified by the ABI.
+  unsigned ArgOffset = 0;
+  NumIntRegs = 0;
+  NumXMMRegs = 0;
+  std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
+  std::vector<SDOperand> MemOpChains;
+  SDOperand StackPtr = DAG.getRegister(X86StackPtr, getPointerTy());
+  for (unsigned i = 0; i != NumOps; ++i) {
+    SDOperand Arg = Op.getOperand(5+2*i);
+    MVT::ValueType ArgVT = Arg.getValueType();
+
+    switch (ArgVT) {
+    default: assert(0 && "Unexpected ValueType for argument!");
+    case MVT::i8:
+    case MVT::i16:
+    case MVT::i32:
+    case MVT::i64:
+      if (NumIntRegs < 6) {
+        unsigned Reg = 0;
+        switch (ArgVT) {
+        default: break;
+        case MVT::i8:  Reg = GPR8ArgRegs[NumIntRegs];  break;
+        case MVT::i16: Reg = GPR16ArgRegs[NumIntRegs]; break;
+        case MVT::i32: Reg = GPR32ArgRegs[NumIntRegs]; break;
+        case MVT::i64: Reg = GPR64ArgRegs[NumIntRegs]; break;
+        }
+        RegsToPass.push_back(std::make_pair(Reg, Arg));
+        ++NumIntRegs;
+      } else {
+        SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
+        PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
+        MemOpChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
+                                          Arg, PtrOff, DAG.getSrcValue(NULL)));
+        ArgOffset += 8;
+      }
+      break;
+    case MVT::f32:
+    case MVT::f64:
+    case MVT::v16i8:
+    case MVT::v8i16:
+    case MVT::v4i32:
+    case MVT::v2i64:
+    case MVT::v4f32:
+    case MVT::v2f64:
+      if (NumXMMRegs < 8) {
+        RegsToPass.push_back(std::make_pair(XMMArgRegs[NumXMMRegs], Arg));
+        NumXMMRegs++;
+      } else {
+        if (ArgVT != MVT::f32 && ArgVT != MVT::f64) {
+          // XMM arguments have to be aligned on 16-byte boundary.
+          ArgOffset = ((ArgOffset + 15) / 16) * 16;
+        }
+        SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
+        PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
+        MemOpChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
+                                          Arg, PtrOff, DAG.getSrcValue(NULL)));
+        if (ArgVT == MVT::f32 || ArgVT == MVT::f64)
+          ArgOffset += 8;
+        else
+          ArgOffset += 16;
+      }
+    }
+  }
+
+  if (!MemOpChains.empty())
+    Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
+                        &MemOpChains[0], MemOpChains.size());
+
+  // Build a sequence of copy-to-reg nodes chained together with token chain
+  // and flag operands which copy the outgoing args into registers.
+  SDOperand InFlag;
+  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
+    Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
+                             InFlag);
+    InFlag = Chain.getValue(1);
+  }
+
+  if (isVarArg) {
+    // From AMD64 ABI document:
+    // For calls that may call functions that use varargs or stdargs
+    // (prototype-less calls or calls to functions containing ellipsis (...) in
+    // the declaration) %al is used as hidden argument to specify the number
+    // of SSE registers used. The contents of %al do not need to match exactly
+    // the number of registers, but must be an ubound on the number of SSE
+    // registers used and is in the range 0 - 8 inclusive.
+    Chain = DAG.getCopyToReg(Chain, X86::AL,
+                             DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
+    InFlag = Chain.getValue(1);
+  }
+
+  // If the callee is a GlobalAddress node (quite common, every direct call is)
+  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
+  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
+    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
+  else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
+    Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
+
+  std::vector<MVT::ValueType> NodeTys;
+  NodeTys.push_back(MVT::Other);   // Returns a chain
+  NodeTys.push_back(MVT::Flag);    // Returns a flag for retval copy to use.
+  std::vector<SDOperand> Ops;
+  Ops.push_back(Chain);
+  Ops.push_back(Callee);
+
+  // Add argument registers to the end of the list so that they are known live
+  // into the call.
+  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
+    Ops.push_back(DAG.getRegister(RegsToPass[i].first, 
+                                  RegsToPass[i].second.getValueType()));
+
+  if (InFlag.Val)
+    Ops.push_back(InFlag);
+
+  // FIXME: Do not generate X86ISD::TAILCALL for now.
+  Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
+                      NodeTys, &Ops[0], Ops.size());
+  InFlag = Chain.getValue(1);
+
+  NodeTys.clear();
+  NodeTys.push_back(MVT::Other);   // Returns a chain
+  if (RetVT != MVT::Other)
+    NodeTys.push_back(MVT::Flag);  // Returns a flag for retval copy to use.
+  Ops.clear();
+  Ops.push_back(Chain);
+  Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
+  Ops.push_back(DAG.getConstant(0, getPointerTy()));
+  Ops.push_back(InFlag);
+  Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
+  if (RetVT != MVT::Other)
+    InFlag = Chain.getValue(1);
+  
+  std::vector<SDOperand> ResultVals;
+  NodeTys.clear();
+  switch (RetVT) {
+  default: assert(0 && "Unknown value type to return!");
+  case MVT::Other: break;
+  case MVT::i8:
+    Chain = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag).getValue(1);
+    ResultVals.push_back(Chain.getValue(0));
+    NodeTys.push_back(MVT::i8);
+    break;
+  case MVT::i16:
+    Chain = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag).getValue(1);
+    ResultVals.push_back(Chain.getValue(0));
+    NodeTys.push_back(MVT::i16);
+    break;
+  case MVT::i32:
+    Chain = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag).getValue(1);
+    ResultVals.push_back(Chain.getValue(0));
+    NodeTys.push_back(MVT::i32);
+    break;
+  case MVT::i64:
+    if (Op.Val->getValueType(1) == MVT::i64) {
+      // FIXME: __int128 support?
+      Chain = DAG.getCopyFromReg(Chain, X86::RAX, MVT::i64, InFlag).getValue(1);
+      ResultVals.push_back(Chain.getValue(0));
+      Chain = DAG.getCopyFromReg(Chain, X86::RDX, MVT::i64,
+                                 Chain.getValue(2)).getValue(1);
+      ResultVals.push_back(Chain.getValue(0));
+      NodeTys.push_back(MVT::i64);
+    } else {
+      Chain = DAG.getCopyFromReg(Chain, X86::RAX, MVT::i64, InFlag).getValue(1);
+      ResultVals.push_back(Chain.getValue(0));
+    }
+    NodeTys.push_back(MVT::i64);
+    break;
+  case MVT::f32:
+  case MVT::f64:
+  case MVT::v16i8:
+  case MVT::v8i16:
+  case MVT::v4i32:
+  case MVT::v2i64:
+  case MVT::v4f32:
+  case MVT::v2f64:
+    // FIXME: long double support?
+    Chain = DAG.getCopyFromReg(Chain, X86::XMM0, RetVT, InFlag).getValue(1);
+    ResultVals.push_back(Chain.getValue(0));
+    NodeTys.push_back(RetVT);
+    break;
+  }
+
+  // If the function returns void, just return the chain.
+  if (ResultVals.empty())
+    return Chain;
+  
+  // Otherwise, merge everything together with a MERGE_VALUES node.
+  NodeTys.push_back(MVT::Other);
+  ResultVals.push_back(Chain);
+  SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys,
+                              &ResultVals[0], ResultVals.size());
+  return Res.getValue(Op.ResNo);
+}
+
 //===----------------------------------------------------------------------===//
 //                    Fast Calling Convention implementation
 //===----------------------------------------------------------------------===//
@@ -949,6 +1485,7 @@
     ArgOffset += 4;
 
   VarArgsFrameIndex = 0xAAAAAAA;   // fastcc functions can't have varargs.
+  RegSaveFrameIndex = 0xAAAAAAA;   // X86-64 only.
   ReturnAddrIndex = 0;             // No return address slot generated yet.
   BytesToPopOnReturn = ArgOffset;  // Callee pops all stack arguments.
   BytesCallerReserves = 0;
@@ -1063,7 +1600,7 @@
   NumIntRegs = 0;
   std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
   std::vector<SDOperand> MemOpChains;
-  SDOperand StackPtr = DAG.getRegister(X86::ESP, getPointerTy());
+  SDOperand StackPtr = DAG.getRegister(X86StackPtr, getPointerTy());
   for (unsigned i = 0; i != NumOps; ++i) {
     SDOperand Arg = Op.getOperand(5+2*i);
 
@@ -1273,10 +1810,13 @@
   if (ReturnAddrIndex == 0) {
     // Set up a frame object for the return address.
     MachineFunction &MF = DAG.getMachineFunction();
-    ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4);
+    if (Subtarget->is64Bit())
+      ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(8, -8);
+    else
+      ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4);
   }
 
-  return DAG.getFrameIndex(ReturnAddrIndex, MVT::i32);
+  return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
 }
 
 
@@ -1291,11 +1831,11 @@
     SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
     if (!isFrameAddress)
       // Just load the return address
-      Result = DAG.getLoad(MVT::i32, DAG.getEntryNode(), RetAddrFI,
+      Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI,
                            DAG.getSrcValue(NULL));
     else
-      Result = DAG.getNode(ISD::SUB, MVT::i32, RetAddrFI,
-                           DAG.getConstant(4, MVT::i32));
+      Result = DAG.getNode(ISD::SUB, getPointerTy(), RetAddrFI,
+                           DAG.getConstant(4, getPointerTy()));
   }
   return std::make_pair(Result, Chain);
 }
@@ -2184,7 +2724,7 @@
 ///
 static SDOperand LowerBuildVectorv16i8(SDOperand Op, unsigned NonZeros,
                                        unsigned NumNonZero, unsigned NumZero,
-                                       SelectionDAG &DAG) {
+                                       SelectionDAG &DAG, TargetLowering &TLI) {
   if (NumNonZero > 8)
     return SDOperand();
 
@@ -2217,7 +2757,7 @@
 
       if (ThisElt.Val)
         V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, ThisElt,
-                        DAG.getConstant(i/2, MVT::i32));
+                        DAG.getConstant(i/2, TLI.getPointerTy()));
     }
   }
 
@@ -2228,7 +2768,7 @@
 ///
 static SDOperand LowerBuildVectorv8i16(SDOperand Op, unsigned NonZeros,
                                        unsigned NumNonZero, unsigned NumZero,
-                                       SelectionDAG &DAG) {
+                                       SelectionDAG &DAG, TargetLowering &TLI) {
   if (NumNonZero > 4)
     return SDOperand();
 
@@ -2245,7 +2785,7 @@
         First = false;
       }
       V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, Op.getOperand(i),
-                      DAG.getConstant(i, MVT::i32));
+                      DAG.getConstant(i, TLI.getPointerTy()));
     }
   }
 
@@ -2324,12 +2864,14 @@
 
   // If element VT is < 32 bits, convert it to inserts into a zero vector.
   if (EVTBits == 8) {
-    SDOperand V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG);
+    SDOperand V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
+                                        *this);
     if (V.Val) return V;
   }
 
   if (EVTBits == 16) {
-    SDOperand V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG);
+    SDOperand V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
+                                        *this);
     if (V.Val) return V;
   }
 
@@ -2791,7 +3333,8 @@
                                                       CP->getAlignment()));
   if (Subtarget->isTargetDarwin()) {
     // With PIC, the address is actually $g + Offset.
-    if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
+    if (!Subtarget->is64Bit() &&
+        getTargetMachine().getRelocationModel() == Reloc::PIC_)
       Result = DAG.getNode(ISD::ADD, getPointerTy(),
                     DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), Result);
   }
@@ -2807,7 +3350,8 @@
                                                             getPointerTy()));
   if (Subtarget->isTargetDarwin()) {
     // With PIC, the address is actually $g + Offset.
-    if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
+    if (!Subtarget->is64Bit() &&
+        getTargetMachine().getRelocationModel() == Reloc::PIC_)
       Result = DAG.getNode(ISD::ADD, getPointerTy(),
                            DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
                            Result);
@@ -2818,7 +3362,7 @@
     // not the GV offset field.
     if (getTargetMachine().getRelocationModel() != Reloc::Static &&
         DarwinGVRequiresExtraLoad(GV))
-      Result = DAG.getLoad(MVT::i32, DAG.getEntryNode(),
+      Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(),
                            Result, DAG.getSrcValue(NULL));
   }
 
@@ -2833,7 +3377,8 @@
                                                              getPointerTy()));
   if (Subtarget->isTargetDarwin()) {
     // With PIC, the address is actually $g + Offset.
-    if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
+    if (!Subtarget->is64Bit() &&
+        getTargetMachine().getRelocationModel() == Reloc::PIC_)
       Result = DAG.getNode(ISD::ADD, getPointerTy(),
                            DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
                            Result);
@@ -3234,7 +3779,8 @@
                                                         getPointerTy()));
   if (Subtarget->isTargetDarwin()) {
     // With PIC, the address is actually $g + Offset.
-    if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
+    if (!Subtarget->is64Bit() &&
+        getTargetMachine().getRelocationModel() == Reloc::PIC_)
       Result = DAG.getNode(ISD::ADD, getPointerTy(),
                            DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
                            Result);    
@@ -3245,7 +3791,9 @@
 
 SDOperand X86TargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
   unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue();
-  if (CallingConv == CallingConv::Fast && EnableFastCC)
+  if (Subtarget->is64Bit())
+    return LowerX86_64CCCCallTo(Op, DAG);
+  else if (CallingConv == CallingConv::Fast && EnableFastCC)
     return LowerFastCCCallTo(Op, DAG);
   else
     return LowerCCCCallTo(Op, DAG);
@@ -3264,18 +3812,25 @@
     case 3: {
       MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
       
-      if (MVT::isVector(ArgVT)) {
+      if (MVT::isVector(ArgVT) ||
+          (Subtarget->is64Bit() && MVT::isFloatingPoint(ArgVT))) {
         // Integer or FP vector result -> XMM0.
         if (DAG.getMachineFunction().liveout_empty())
           DAG.getMachineFunction().addLiveOut(X86::XMM0);
         Copy = DAG.getCopyToReg(Op.getOperand(0), X86::XMM0, Op.getOperand(1),
                                 SDOperand());
       } else if (MVT::isInteger(ArgVT)) {
-        // Integer result -> EAX
+        // Integer result -> EAX / RAX.
+        // The C calling convention guarantees the return value has been
+        // promoted to at least MVT::i32. The X86-64 ABI doesn't require the
+        // value to be promoted MVT::i64. So we don't have to extend it to
+        // 64-bit. Return the value in EAX, but mark RAX as liveout.
+        unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
         if (DAG.getMachineFunction().liveout_empty())
-          DAG.getMachineFunction().addLiveOut(X86::EAX);
+          DAG.getMachineFunction().addLiveOut(Reg);
 
-        Copy = DAG.getCopyToReg(Op.getOperand(0), X86::EAX, Op.getOperand(1),
+        Reg = (ArgVT == MVT::i64) ? X86::RAX : X86::EAX;
+        Copy = DAG.getCopyToReg(Op.getOperand(0), Reg, Op.getOperand(1),
                                 SDOperand());
       } else if (!X86ScalarSSE) {
         // FP return with fp-stack value.
@@ -3329,19 +3884,22 @@
       }
       break;
     }
-    case 5:
+    case 5: {
+      unsigned Reg1 = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
+      unsigned Reg2 = Subtarget->is64Bit() ? X86::RDX : X86::EDX;
       if (DAG.getMachineFunction().liveout_empty()) {
-        DAG.getMachineFunction().addLiveOut(X86::EAX);
-        DAG.getMachineFunction().addLiveOut(X86::EDX);
+        DAG.getMachineFunction().addLiveOut(Reg1);
+        DAG.getMachineFunction().addLiveOut(Reg2);
       }
 
-      Copy = DAG.getCopyToReg(Op.getOperand(0), X86::EDX, Op.getOperand(3), 
+      Copy = DAG.getCopyToReg(Op.getOperand(0), Reg2, Op.getOperand(3), 
                               SDOperand());
-      Copy = DAG.getCopyToReg(Copy, X86::EAX,Op.getOperand(1),Copy.getValue(1));
+      Copy = DAG.getCopyToReg(Copy, Reg1, Op.getOperand(1), Copy.getValue(1));
       break;
+    }
   }
   return DAG.getNode(X86ISD::RET_FLAG, MVT::Other,
-                   Copy, DAG.getConstant(getBytesToPopOnReturn(), MVT::i16),
+                     Copy, DAG.getConstant(getBytesToPopOnReturn(), MVT::i16),
                      Copy.getValue(1));
 }
 
@@ -3355,7 +3913,9 @@
     MF.getInfo<X86FunctionInfo>()->setForceFramePointer(true);
 
   unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
-  if (CC == CallingConv::Fast && EnableFastCC)
+  if (Subtarget->is64Bit())
+    return LowerX86_64CCCArguments(Op, DAG);
+  else if (CC == CallingConv::Fast && EnableFastCC)
     return LowerFastCCArguments(Op, DAG);
   else
     return LowerCCCArguments(Op, DAG);
@@ -3394,38 +3954,47 @@
   bool TwoRepStos = false;
   if (ValC) {
     unsigned ValReg;
-    unsigned Val = ValC->getValue() & 255;
+    uint64_t Val = ValC->getValue() & 255;
 
     // If the value is a constant, then we can potentially use larger sets.
     switch (Align & 3) {
       case 2:   // WORD aligned
         AVT = MVT::i16;
-        Count = DAG.getConstant(I->getValue() / 2, MVT::i32);
-        BytesLeft = I->getValue() % 2;
-        Val    = (Val << 8) | Val;
         ValReg = X86::AX;
+        Val = (Val << 8) | Val;
         break;
-      case 0:   // DWORD aligned
+      case 0:  // DWORD aligned
         AVT = MVT::i32;
-        if (I) {
-          Count = DAG.getConstant(I->getValue() / 4, MVT::i32);
-          BytesLeft = I->getValue() % 4;
-        } else {
-          Count = DAG.getNode(ISD::SRL, MVT::i32, Op.getOperand(3),
-                              DAG.getConstant(2, MVT::i8));
-          TwoRepStos = true;
-        }
+        ValReg = X86::EAX;
         Val = (Val << 8)  | Val;
         Val = (Val << 16) | Val;
-        ValReg = X86::EAX;
+        if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) {  // QWORD aligned
+          AVT = MVT::i64;
+          ValReg = X86::RAX;
+          Val = (Val << 32) | Val;
+        }
         break;
       default:  // Byte aligned
         AVT = MVT::i8;
-        Count = Op.getOperand(3);
         ValReg = X86::AL;
+        Count = Op.getOperand(3);
         break;
     }
 
+    if (AVT > MVT::i8) {
+      if (I) {
+        unsigned UBytes = MVT::getSizeInBits(AVT) / 8;
+        Count = DAG.getConstant(I->getValue() / UBytes, getPointerTy());
+        BytesLeft = I->getValue() % UBytes;
+      } else {
+        assert(AVT >= MVT::i32 &&
+               "Do not use rep;stos if not at least DWORD aligned");
+        Count = DAG.getNode(ISD::SRL, Op.getOperand(3).getValueType(),
+                            Op.getOperand(3), DAG.getConstant(2, MVT::i8));
+        TwoRepStos = true;
+      }
+    }
+
     Chain  = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT),
                               InFlag);
     InFlag = Chain.getValue(1);
@@ -3436,9 +4005,11 @@
     InFlag = Chain.getValue(1);
   }
 
-  Chain  = DAG.getCopyToReg(Chain, X86::ECX, Count, InFlag);
+  Chain  = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
+                            Count, InFlag);
   InFlag = Chain.getValue(1);
-  Chain  = DAG.getCopyToReg(Chain, X86::EDI, Op.getOperand(1), InFlag);
+  Chain  = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
+                            Op.getOperand(1), InFlag);
   InFlag = Chain.getValue(1);
 
   std::vector<MVT::ValueType> Tys;
@@ -3455,8 +4026,9 @@
     Count = Op.getOperand(3);
     MVT::ValueType CVT = Count.getValueType();
     SDOperand Left = DAG.getNode(ISD::AND, CVT, Count,
-                                 DAG.getConstant(3, CVT));
-    Chain  = DAG.getCopyToReg(Chain, X86::ECX, Left, InFlag);
+                               DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
+    Chain  = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX,
+                              Left, InFlag);
     InFlag = Chain.getValue(1);
     Tys.clear();
     Tys.push_back(MVT::Other);
@@ -3467,12 +4039,23 @@
     Ops.push_back(InFlag);
     Chain  = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
   } else if (BytesLeft) {
-    // Issue stores for the last 1 - 3 bytes.
+    // Issue stores for the last 1 - 7 bytes.
     SDOperand Value;
     unsigned Val = ValC->getValue() & 255;
     unsigned Offset = I->getValue() - BytesLeft;
     SDOperand DstAddr = Op.getOperand(1);
     MVT::ValueType AddrVT = DstAddr.getValueType();
+    if (BytesLeft >= 4) {
+      Val = (Val << 8)  | Val;
+      Val = (Val << 16) | Val;
+      Value = DAG.getConstant(Val, MVT::i32);
+      Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Value,
+                          DAG.getNode(ISD::ADD, AddrVT, DstAddr,
+                                      DAG.getConstant(Offset, AddrVT)),
+                          DAG.getSrcValue(NULL));
+      BytesLeft -= 4;
+      Offset += 4;
+    }
     if (BytesLeft >= 2) {
       Value = DAG.getConstant((Val << 8) | Val, MVT::i16);
       Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Value,
@@ -3482,7 +4065,6 @@
       BytesLeft -= 2;
       Offset += 2;
     }
-
     if (BytesLeft == 1) {
       Value = DAG.getConstant(Val, MVT::i8);
       Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Value,
@@ -3525,19 +4107,11 @@
   switch (Align & 3) {
     case 2:   // WORD aligned
       AVT = MVT::i16;
-      Count = DAG.getConstant(I->getValue() / 2, MVT::i32);
-      BytesLeft = I->getValue() % 2;
       break;
-    case 0:   // DWORD aligned
+    case 0:  // DWORD aligned
       AVT = MVT::i32;
-      if (I) {
-        Count = DAG.getConstant(I->getValue() / 4, MVT::i32);
-        BytesLeft = I->getValue() % 4;
-      } else {
-        Count = DAG.getNode(ISD::SRL, MVT::i32, Op.getOperand(3),
-                            DAG.getConstant(2, MVT::i8));
-        TwoRepMovs = true;
-      }
+      if (Subtarget->is64Bit() && ((Align & 0xF) == 0))  // QWORD aligned
+        AVT = MVT::i64;
       break;
     default:  // Byte aligned
       AVT = MVT::i8;
@@ -3545,12 +4119,29 @@
       break;
   }
 
+  if (AVT > MVT::i8) {
+    if (I) {
+      unsigned UBytes = MVT::getSizeInBits(AVT) / 8;
+      Count = DAG.getConstant(I->getValue() / UBytes, getPointerTy());
+      BytesLeft = I->getValue() % UBytes;
+    } else {
+      assert(AVT >= MVT::i32 &&
+             "Do not use rep;movs if not at least DWORD aligned");
+      Count = DAG.getNode(ISD::SRL, Op.getOperand(3).getValueType(),
+                          Op.getOperand(3), DAG.getConstant(2, MVT::i8));
+      TwoRepMovs = true;
+    }
+  }
+
   SDOperand InFlag(0, 0);
-  Chain  = DAG.getCopyToReg(Chain, X86::ECX, Count, InFlag);
+  Chain  = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
+                            Count, InFlag);
   InFlag = Chain.getValue(1);
-  Chain  = DAG.getCopyToReg(Chain, X86::EDI, Op.getOperand(1), InFlag);
+  Chain  = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
+                            Op.getOperand(1), InFlag);
   InFlag = Chain.getValue(1);
-  Chain  = DAG.getCopyToReg(Chain, X86::ESI, Op.getOperand(2), InFlag);
+  Chain  = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RSI : X86::ESI,
+                            Op.getOperand(2), InFlag);
   InFlag = Chain.getValue(1);
 
   std::vector<MVT::ValueType> Tys;
@@ -3567,8 +4158,9 @@
     Count = Op.getOperand(3);
     MVT::ValueType CVT = Count.getValueType();
     SDOperand Left = DAG.getNode(ISD::AND, CVT, Count,
-                                 DAG.getConstant(3, CVT));
-    Chain  = DAG.getCopyToReg(Chain, X86::ECX, Left, InFlag);
+                               DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
+    Chain  = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX,
+                              Left, InFlag);
     InFlag = Chain.getValue(1);
     Tys.clear();
     Tys.push_back(MVT::Other);
@@ -3579,13 +4171,26 @@
     Ops.push_back(InFlag);
     Chain = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size());
   } else if (BytesLeft) {
-    // Issue loads and stores for the last 1 - 3 bytes.
+    // Issue loads and stores for the last 1 - 7 bytes.
     unsigned Offset = I->getValue() - BytesLeft;
     SDOperand DstAddr = Op.getOperand(1);
     MVT::ValueType DstVT = DstAddr.getValueType();
     SDOperand SrcAddr = Op.getOperand(2);
     MVT::ValueType SrcVT = SrcAddr.getValueType();
     SDOperand Value;
+    if (BytesLeft >= 4) {
+      Value = DAG.getLoad(MVT::i32, Chain,
+                          DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
+                                      DAG.getConstant(Offset, SrcVT)),
+                          DAG.getSrcValue(NULL));
+      Chain = Value.getValue(1);
+      Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Value,
+                          DAG.getNode(ISD::ADD, DstVT, DstAddr,
+                                      DAG.getConstant(Offset, DstVT)),
+                          DAG.getSrcValue(NULL));
+      BytesLeft -= 4;
+      Offset += 4;
+    }
     if (BytesLeft >= 2) {
       Value = DAG.getLoad(MVT::i16, Chain,
                           DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
@@ -3635,12 +4240,51 @@
 }
 
 SDOperand X86TargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG) {
-  // vastart just stores the address of the VarArgsFrameIndex slot into the
-  // memory location argument.
-  // FIXME: Replace MVT::i32 with PointerTy
-  SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
-  return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), FR, 
-                     Op.getOperand(1), Op.getOperand(2));
+  if (!Subtarget->is64Bit()) {
+    // vastart just stores the address of the VarArgsFrameIndex slot into the
+    // memory location argument.
+    SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
+    return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), FR, 
+                       Op.getOperand(1), Op.getOperand(2));
+  }
+
+  // __va_list_tag:
+  //   gp_offset         (0 - 6 * 8)
+  //   fp_offset         (48 - 48 + 8 * 16)
+  //   overflow_arg_area (point to parameters coming in memory).
+  //   reg_save_area
+  std::vector<SDOperand> MemOps;
+  SDOperand FIN = Op.getOperand(1);
+  // Store gp_offset
+  SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0),
+                                DAG.getConstant(VarArgsGPOffset, MVT::i32),
+                                FIN, Op.getOperand(2));
+  MemOps.push_back(Store);
+
+  // Store fp_offset
+  FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
+                    DAG.getConstant(4, getPointerTy()));
+  Store = DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0),
+                      DAG.getConstant(VarArgsFPOffset, MVT::i32),
+                      FIN, Op.getOperand(2));
+  MemOps.push_back(Store);
+
+  // Store ptr to overflow_arg_area
+  FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
+                    DAG.getConstant(4, getPointerTy()));
+  SDOperand OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
+  Store = DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0),
+                      OVFIN, FIN, Op.getOperand(2));
+  MemOps.push_back(Store);
+
+  // Store ptr to reg_save_area.
+  FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
+                    DAG.getConstant(8, getPointerTy()));
+  SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
+  Store = DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0),
+                      RSFIN, FIN, Op.getOperand(2));
+  MemOps.push_back(Store);
+  return DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOps[0], MemOps.size());
 }
 
 SDOperand
@@ -4333,6 +4977,23 @@
       Res.first = DestReg;
       Res.second = Res.second = X86::GR32RegisterClass;
     }
+  } else if (VT == MVT::i64) {
+    unsigned DestReg = 0;
+    switch (Res.first) {
+    default: break;
+    case X86::AX: DestReg = X86::RAX; break;
+    case X86::DX: DestReg = X86::RDX; break;
+    case X86::CX: DestReg = X86::RCX; break;
+    case X86::BX: DestReg = X86::RBX; break;
+    case X86::SI: DestReg = X86::RSI; break;
+    case X86::DI: DestReg = X86::RDI; break;
+    case X86::BP: DestReg = X86::RBP; break;
+    case X86::SP: DestReg = X86::RSP; break;
+    }
+    if (DestReg) {
+      Res.first = DestReg;
+      Res.second = Res.second = X86::GR64RegisterClass;
+    }
   }
   
   return Res;


Index: llvm/lib/Target/X86/X86ISelLowering.h
diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.70 llvm/lib/Target/X86/X86ISelLowering.h:1.71
--- llvm/lib/Target/X86/X86ISelLowering.h:1.70	Mon Jul 31 18:26:50 2006
+++ llvm/lib/Target/X86/X86ISelLowering.h	Fri Sep  8 01:48:29 2006
@@ -267,6 +267,9 @@
   //  X86TargetLowering - X86 Implementation of the TargetLowering interface
   class X86TargetLowering : public TargetLowering {
     int VarArgsFrameIndex;            // FrameIndex for start of varargs area.
+    int RegSaveFrameIndex;            // X86-64 vararg func register save area.
+    unsigned VarArgsGPOffset;         // X86-64 vararg func int reg offset.
+    unsigned VarArgsFPOffset;         // X86-64 vararg func fp reg offset.
     int ReturnAddrIndex;              // FrameIndex for return slot.
     int BytesToPopOnReturn;           // Number of arg bytes ret should pop.
     int BytesCallerReserves;          // Number of arg bytes caller makes.
@@ -347,6 +350,9 @@
     /// make the right decision when generating code for different targets.
     const X86Subtarget *Subtarget;
 
+    /// X86StackPtr - X86 physical register used as stack ptr.
+    unsigned X86StackPtr;
+
     /// X86ScalarSSE - Select between SSE2 or x87 floating point ops.
     bool X86ScalarSSE;
 
@@ -354,6 +360,10 @@
     SDOperand LowerCCCArguments(SDOperand Op, SelectionDAG &DAG);
     SDOperand LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG);
 
+    // X86-64 C Calling Convention implementation.
+    SDOperand LowerX86_64CCCArguments(SDOperand Op, SelectionDAG &DAG);
+    SDOperand LowerX86_64CCCCallTo(SDOperand Op, SelectionDAG &DAG);
+
     // Fast Calling Convention implementation.
     SDOperand LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG);
     SDOperand LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG);


Index: llvm/lib/Target/X86/X86InstrInfo.cpp
diff -u llvm/lib/Target/X86/X86InstrInfo.cpp:1.59 llvm/lib/Target/X86/X86InstrInfo.cpp:1.60
--- llvm/lib/Target/X86/X86InstrInfo.cpp:1.59	Mon Sep  4 21:12:02 2006
+++ llvm/lib/Target/X86/X86InstrInfo.cpp	Fri Sep  8 01:48:29 2006
@@ -22,7 +22,7 @@
 
 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
   : TargetInstrInfo(X86Insts, sizeof(X86Insts)/sizeof(X86Insts[0])),
-    TM(tm), RI(*this) {
+    TM(tm), RI(tm, *this) {
 }
 
 
@@ -30,7 +30,8 @@
                                unsigned& sourceReg,
                                unsigned& destReg) const {
   MachineOpCode oc = MI.getOpcode();
-  if (oc == X86::MOV8rr || oc == X86::MOV16rr || oc == X86::MOV32rr ||
+  if (oc == X86::MOV8rr || oc == X86::MOV16rr ||
+      oc == X86::MOV32rr || oc == X86::MOV64rr ||
       oc == X86::MOV16to16_ || oc == X86::MOV32to32_ ||
       oc == X86::FpMOV  || oc == X86::MOVSSrr || oc == X86::MOVSDrr ||
       oc == X86::FsMOVAPSrr || oc == X86::FsMOVAPDrr ||
@@ -59,6 +60,7 @@
   case X86::MOV16_rm:
   case X86::MOV32rm:
   case X86::MOV32_rm:
+  case X86::MOV64rm:
   case X86::FpLD64m:
   case X86::MOVSSrm:
   case X86::MOVSDrm:
@@ -86,6 +88,7 @@
   case X86::MOV16_mr:
   case X86::MOV32mr:
   case X86::MOV32_mr:
+  case X86::MOV64mr:
   case X86::FpSTP64m:
   case X86::MOVSSmr:
   case X86::MOVSDmr:
@@ -145,16 +148,20 @@
 
   switch (MI->getOpcode()) {
   case X86::INC32r:
+  case X86::INC64_32r:
     assert(MI->getNumOperands() == 2 && "Unknown inc instruction!");
     return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src, 1);
   case X86::INC16r:
+  case X86::INC64_16r:
     if (DisableLEA16) return 0;
     assert(MI->getNumOperands() == 2 && "Unknown inc instruction!");
     return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src, 1);
   case X86::DEC32r:
+  case X86::DEC64_32r:
     assert(MI->getNumOperands() == 2 && "Unknown dec instruction!");
     return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src, -1);
   case X86::DEC16r:
+  case X86::DEC64_16r:
     if (DisableLEA16) return 0;
     assert(MI->getNumOperands() == 2 && "Unknown dec instruction!");
     return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src, -1);
@@ -264,3 +271,10 @@
   return BuildMI(*MBB, MBB->erase(MI), ROpcode, 1).addMBB(TMBB);
 }
 
+const TargetRegisterClass *X86InstrInfo::getPointerRegClass() const {
+  const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
+  if (Subtarget->is64Bit())
+    return &X86::GR64RegClass;
+  else
+    return &X86::GR32RegClass;
+}


Index: llvm/lib/Target/X86/X86InstrInfo.h
diff -u llvm/lib/Target/X86/X86InstrInfo.h:1.53 llvm/lib/Target/X86/X86InstrInfo.h:1.54
--- llvm/lib/Target/X86/X86InstrInfo.h:1.53	Tue May 30 16:45:53 2006
+++ llvm/lib/Target/X86/X86InstrInfo.h	Fri Sep  8 01:48:29 2006
@@ -18,6 +18,7 @@
 #include "X86RegisterInfo.h"
 
 namespace llvm {
+  class X86RegisterInfo;
   class X86TargetMachine;
 
 /// X86II - This namespace holds all of the target specific flags that
@@ -90,12 +91,18 @@
     // instead of 32 bit data.
     OpSize      = 1 << 6,
 
+    // AsSize - Set if this instruction requires an operand size prefix (0x67),
+    // which most often indicates that the instruction address 16 bit address
+    // instead of 32 bit address (or 32 bit address in 64 bit mode).
+    AdSize      = 1 << 7,
+
+    //===------------------------------------------------------------------===//
     // Op0Mask - There are several prefix bytes that are used to form two byte
     // opcodes.  These are currently 0x0F, 0xF3, and 0xD8-0xDF.  This mask is
     // used to obtain the setting of this field.  If no bits in this field is
     // set, there is no prefix byte for obtaining a multibyte opcode.
     //
-    Op0Shift    = 7,
+    Op0Shift    = 8,
     Op0Mask     = 0xF << Op0Shift,
 
     // TB - TwoByte - Set if this instruction has a two byte opcode, which
@@ -118,19 +125,29 @@
     XD = 11 << Op0Shift,   XS = 12 << Op0Shift,
 
     //===------------------------------------------------------------------===//
-    // This two-bit field describes the size of an immediate operand.  Zero is
+    // REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
+    // They are used to specify GPRs and SSE registers, 64-bit operand size,
+    // etc. We only cares about REX.W and REX.R bits and only the former is
+    // statically determined.
+    //
+    REXShift    = 12,
+    REX_W       = 1 << REXShift,
+
+    //===------------------------------------------------------------------===//
+    // This three-bit field describes the size of an immediate operand.  Zero is
     // unused so that we can tell if we forgot to set a value.
-    ImmShift = 11,
-    ImmMask  = 3 << ImmShift,
+    ImmShift = 13,
+    ImmMask  = 7 << ImmShift,
     Imm8     = 1 << ImmShift,
     Imm16    = 2 << ImmShift,
     Imm32    = 3 << ImmShift,
+    Imm64    = 4 << ImmShift,
 
     //===------------------------------------------------------------------===//
     // FP Instruction Classification...  Zero is non-fp instruction.
 
     // FPTypeMask - Mask for all of the FP types...
-    FPTypeShift = 13,
+    FPTypeShift = 16,
     FPTypeMask  = 7 << FPTypeShift,
 
     // NotFP - The default, set for instructions that do not use FP registers.
@@ -162,9 +179,9 @@
     // SpecialFP - Special instruction forms.  Dispatch by opcode explicitly.
     SpecialFP  = 7 << FPTypeShift,
 
-    OpcodeShift   = 16,
+    // Bits 19 -> 23 are unused
+    OpcodeShift   = 24,
     OpcodeMask    = 0xFF << OpcodeShift
-    // Bits 25 -> 31 are unused
   };
 }
 
@@ -216,6 +233,8 @@
   virtual MachineBasicBlock::iterator
   reverseBranchCondition(MachineBasicBlock::iterator MI) const;
 
+  const TargetRegisterClass *getPointerRegClass() const;
+
   // getBaseOpcodeFor - This function returns the "base" X86 opcode for the
   // specified opcode number.
   //


Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.284 llvm/lib/Target/X86/X86InstrInfo.td:1.285
--- llvm/lib/Target/X86/X86InstrInfo.td:1.284	Thu Sep  7 15:33:45 2006
+++ llvm/lib/Target/X86/X86InstrInfo.td	Fri Sep  8 01:48:29 2006
@@ -39,7 +39,7 @@
 def SDT_X86CallSeqEnd   : SDTypeProfile<0, 2, [ SDTCisVT<0, i32>,
                                                 SDTCisVT<1, i32> ]>;
 
-def SDT_X86Call   : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
+def SDT_X86Call   : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
 
 def SDTX86RepStr  : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
 
@@ -95,7 +95,7 @@
 class X86MemOperand<string printMethod> : Operand<iPTR> {
   let PrintMethod = printMethod;
   let NumMIOperands = 4;
-  let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
+  let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
 }
 
 def i8mem   : X86MemOperand<"printi8mem">;
@@ -107,6 +107,12 @@
 def f64mem  : X86MemOperand<"printf64mem">;
 def f128mem : X86MemOperand<"printf128mem">;
 
+def lea32mem : Operand<i32> {
+  let PrintMethod = "printi32mem";
+  let NumMIOperands = 4;
+  let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
+}
+
 def SSECC : Operand<i8> {
   let PrintMethod = "printSSECC";
 }
@@ -129,9 +135,9 @@
 //
 
 // Define X86 specific addressing mode.
-def addr    : ComplexPattern<iPTR, 4, "SelectAddr", []>;
-def leaaddr : ComplexPattern<iPTR, 4, "SelectLEAAddr",
-                             [add, mul, shl, or, frameindex]>;
+def addr      : ComplexPattern<iPTR, 4, "SelectAddr", []>;
+def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
+                               [add, mul, shl, or, frameindex]>;
 
 //===----------------------------------------------------------------------===//
 // X86 Instruction Format Definitions.
@@ -158,11 +164,13 @@
 
 //===----------------------------------------------------------------------===//
 // X86 Instruction Predicate Definitions.
-def HasMMX  : Predicate<"Subtarget->hasMMX()">;
-def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
-def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
-def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
-def FPStack : Predicate<"!Subtarget->hasSSE2()">;
+def HasMMX   : Predicate<"Subtarget->hasMMX()">;
+def HasSSE1  : Predicate<"Subtarget->hasSSE1()">;
+def HasSSE2  : Predicate<"Subtarget->hasSSE2()">;
+def HasSSE3  : Predicate<"Subtarget->hasSSE3()">;
+def FPStack  : Predicate<"!Subtarget->hasSSE2()">;
+def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
+def In64BitMode : Predicate<"Subtarget->is64Bit()">;
 
 //===----------------------------------------------------------------------===//
 // X86 specific pattern fragments.
@@ -171,13 +179,14 @@
 // ImmType - This specifies the immediate type used by an instruction. This is
 // part of the ad-hoc solution used to emit machine instruction encodings by our
 // machine code emitter.
-class ImmType<bits<2> val> {
-  bits<2> Value = val;
+class ImmType<bits<3> val> {
+  bits<3> Value = val;
 }
 def NoImm  : ImmType<0>;
 def Imm8   : ImmType<1>;
 def Imm16  : ImmType<2>;
 def Imm32  : ImmType<3>;
+def Imm64  : ImmType<4>;
 
 // FPFormat - This specifies what form this FP instruction has.  This is used by
 // the Floating-Point stackifier pass.
@@ -202,7 +211,7 @@
   Format Form = f;
   bits<6> FormBits = Form.Value;
   ImmType ImmT = i;
-  bits<2> ImmTypeBits = ImmT.Value;
+  bits<3> ImmTypeBits = ImmT.Value;
 
   dag OperandList = ops;
   string AsmString = AsmStr;
@@ -210,9 +219,11 @@
   //
   // Attributes specific to X86 instructions...
   //
-  bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
+  bit hasOpSizePrefix = 0;  // Does this inst have a 0x66 prefix?
+  bit hasAdSizePrefix = 0;  // Does this inst have a 0x67 prefix?
 
   bits<4> Prefix = 0;       // Which prefix byte does this inst have?
+  bit hasREX_WPrefix  = 0;  // Does this inst requires the REX.W prefix?
   FPFormat FPForm;          // What flavor of FP instruction is this?
   bits<3> FPFormBits = 0;
 }
@@ -226,6 +237,8 @@
 // Prefix byte classes which are used to indicate to the ad-hoc machine code
 // emitter that various prefix bytes are required.
 class OpSize { bit hasOpSizePrefix = 1; }
+class AdSize { bit hasAdSizePrefix = 1; }
+class REX_W  { bit hasREX_WPrefix = 1; }
 class TB     { bits<4> Prefix = 1; }
 class REP    { bits<4> Prefix = 2; }
 class D8     { bits<4> Prefix = 3; }
@@ -276,8 +289,6 @@
 }]>;
 
 // Helper fragments for loads.
-def loadiPTR : PatFrag<(ops node:$ptr), (iPTR (load node:$ptr))>;
-
 def loadi8  : PatFrag<(ops node:$ptr), (i8  (load node:$ptr))>;
 def loadi16 : PatFrag<(ops node:$ptr), (i16 (load node:$ptr))>;
 def loadi32 : PatFrag<(ops node:$ptr), (i32 (load node:$ptr))>;
@@ -308,6 +319,7 @@
 
 //===----------------------------------------------------------------------===//
 // Instruction templates...
+//
 
 class I<bits<8> o, Format f, dag ops, string asm, list<dag> pattern>
   : X86Inst<o, f, NoImm, ops, asm> {
@@ -355,13 +367,13 @@
 def NOOP : I<0x90, RawFrm, (ops), "nop", []>;
 
 // Truncate
-def TRUNC_GR32_GR8  : I<0x88, MRMDestReg, (ops GR8:$dst, GR32_:$src),
-                      "mov{b} {${src:subreg8}, $dst|$dst, ${src:subreg8}", []>;
-def TRUNC_GR16_GR8  : I<0x88, MRMDestReg, (ops GR8:$dst, GR16_:$src),
-                      "mov{b} {${src:subreg8}, $dst|$dst, ${src:subreg8}}", []>;
-def TRUNC_GR32_GR16 : I<0x89, MRMDestReg, (ops GR16:$dst, GR32:$src),
-                      "mov{w} {${src:subreg16}, $dst|$dst, ${src:subreg16}}",
-                      [(set GR16:$dst, (trunc GR32:$src))]>;
+def TRUNC_32_to8 : I<0x88, MRMDestReg, (ops GR8:$dst, GR32_:$src),
+                     "mov{b} {${src:subreg8}, $dst|$dst, ${src:subreg8}", []>;
+def TRUNC_16_to8 : I<0x88, MRMDestReg, (ops GR8:$dst, GR16_:$src),
+                     "mov{b} {${src:subreg8}, $dst|$dst, ${src:subreg8}}", []>;
+def TRUNC_32to16 : I<0x89, MRMDestReg, (ops GR16:$dst, GR32:$src),
+                     "mov{w} {${src:subreg16}, $dst|$dst, ${src:subreg16}}",
+                     [(set GR16:$dst, (trunc GR32:$src))]>;
 
 //===----------------------------------------------------------------------===//
 //  Control Flow Instructions...
@@ -388,7 +400,7 @@
   def JMP32r     : I<0xFF, MRM4r, (ops GR32:$dst), "jmp{l} {*}$dst",
                      [(brind GR32:$dst)]>;
   def JMP32m     : I<0xFF, MRM4m, (ops i32mem:$dst), "jmp{l} {*}$dst",
-                     [(brind (loadiPTR addr:$dst))]>;
+                     [(brind (loadi32 addr:$dst))]>;
 }
 
 // Conditional branches
@@ -510,9 +522,9 @@
                  (ops GR16:$dst, i32mem:$src),
                  "lea{w} {$src|$dst}, {$dst|$src}", []>, OpSize;
 def LEA32r   : I<0x8D, MRMSrcMem,
-                 (ops GR32:$dst, i32mem:$src),
+                 (ops GR32:$dst, lea32mem:$src),
                  "lea{l} {$src|$dst}, {$dst|$src}",
-                 [(set GR32:$dst, leaaddr:$src)]>;
+                 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
 
 def REP_MOVSB : I<0xA4, RawFrm, (ops), "{rep;movsb|rep movsb}",
                   [(X86rep_movs i8)]>,
@@ -1101,9 +1113,10 @@
                [(set GR8:$dst, (add GR8:$src, 1))]>;
 let isConvertibleToThreeAddress = 1, CodeSize = 1 in {  // Can xform into LEA.
 def INC16r : I<0x40, AddRegFrm, (ops GR16:$dst, GR16:$src), "inc{w} $dst",
-               [(set GR16:$dst, (add GR16:$src, 1))]>, OpSize;
+               [(set GR16:$dst, (add GR16:$src, 1))]>,
+             OpSize, Requires<[In32BitMode]>;
 def INC32r : I<0x40, AddRegFrm, (ops GR32:$dst, GR32:$src), "inc{l} $dst",
-               [(set GR32:$dst, (add GR32:$src, 1))]>;
+               [(set GR32:$dst, (add GR32:$src, 1))]>, Requires<[In32BitMode]>;
 }
 let isTwoAddress = 0, CodeSize = 2 in {
   def INC8m  : I<0xFE, MRM0m, (ops i8mem :$dst), "inc{b} $dst",
@@ -1119,9 +1132,10 @@
                [(set GR8:$dst, (add GR8:$src, -1))]>;
 let isConvertibleToThreeAddress = 1, CodeSize = 1 in {   // Can xform into LEA.
 def DEC16r : I<0x48, AddRegFrm, (ops GR16:$dst, GR16:$src), "dec{w} $dst",
-               [(set GR16:$dst, (add GR16:$src, -1))]>, OpSize;
+               [(set GR16:$dst, (add GR16:$src, -1))]>,
+             OpSize, Requires<[In32BitMode]>;
 def DEC32r : I<0x48, AddRegFrm, (ops GR32:$dst, GR32:$src), "dec{l} $dst",
-               [(set GR32:$dst, (add GR32:$src, -1))]>;
+               [(set GR32:$dst, (add GR32:$src, -1))]>, Requires<[In32BitMode]>;
 }
 
 let isTwoAddress = 0, CodeSize = 2 in {
@@ -2455,7 +2469,7 @@
 // Non-Instruction Patterns
 //===----------------------------------------------------------------------===//
 
-// ConstantPool GlobalAddress, ExternalSymbol
+// ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
 def : Pat<(i32 (X86Wrapper tconstpool  :$dst)), (MOV32ri tconstpool  :$dst)>;
 def : Pat<(i32 (X86Wrapper tjumptable  :$dst)), (MOV32ri tjumptable  :$dst)>;
 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
@@ -2477,18 +2491,16 @@
 
 // Calls
 def : Pat<(X86tailcall GR32:$dst),
-      (CALL32r     GR32:$dst)>;
+          (CALL32r     GR32:$dst)>;
 
-def : Pat<(X86tailcall tglobaladdr:$dst),
+def : Pat<(X86tailcall (i32 tglobaladdr:$dst)),
           (CALLpcrel32 tglobaladdr:$dst)>;
-def : Pat<(X86tailcall texternalsym:$dst),
+def : Pat<(X86tailcall (i32 texternalsym:$dst)),
           (CALLpcrel32 texternalsym:$dst)>;
 
-
-
-def : Pat<(X86call tglobaladdr:$dst),
+def : Pat<(X86call (i32 tglobaladdr:$dst)),
           (CALLpcrel32 tglobaladdr:$dst)>;
-def : Pat<(X86call texternalsym:$dst),
+def : Pat<(X86call (i32 texternalsym:$dst)),
           (CALLpcrel32 texternalsym:$dst)>;
 
 // X86 specific add which produces a flag.
@@ -2611,3 +2623,9 @@
 //===----------------------------------------------------------------------===//
 
 include "X86InstrSSE.td"
+
+//===----------------------------------------------------------------------===//
+// X86-64 Support
+//===----------------------------------------------------------------------===//
+
+include "X86InstrX86-64.td"


Index: llvm/lib/Target/X86/X86IntelAsmPrinter.cpp
diff -u llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.54 llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.55
--- llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.54	Thu Sep  7 17:06:40 2006
+++ llvm/lib/Target/X86/X86IntelAsmPrinter.cpp	Fri Sep  8 01:48:29 2006
@@ -86,8 +86,9 @@
     if (MRegisterInfo::isPhysicalRegister(MO.getReg())) {
       unsigned Reg = MO.getReg();
       if (Modifier && strncmp(Modifier, "subreg", strlen("subreg")) == 0) {
-        MVT::ValueType VT = (strcmp(Modifier,"subreg16") == 0)
-          ? MVT::i16 : MVT::i8;
+        MVT::ValueType VT = (strcmp(Modifier,"subreg64") == 0) ?
+          MVT::i64 : ((strcmp(Modifier, "subreg32") == 0) ? MVT::i32 :
+                      ((strcmp(Modifier,"subreg16") == 0) ? MVT::i16 :MVT::i8));
         Reg = getX86SubSuperRegister(Reg, VT);
       }
       O << RI.get(Reg).Name;
@@ -137,7 +138,8 @@
   }
 }
 
-void X86IntelAsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op){
+void X86IntelAsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op,
+                                           const char *Modifier) {
   assert(isMem(MI, Op) && "Invalid memory reference!");
 
   const MachineOperand &BaseReg  = MI->getOperand(Op);
@@ -156,7 +158,7 @@
   O << "[";
   bool NeedPlus = false;
   if (BaseReg.getReg()) {
-    printOp(BaseReg, "mem");
+    printOp(BaseReg, Modifier);
     NeedPlus = true;
   }
 
@@ -164,7 +166,7 @@
     if (NeedPlus) O << " + ";
     if (ScaleVal != 1)
       O << ScaleVal << "*";
-    printOp(IndexReg);
+    printOp(IndexReg, Modifier);
     NeedPlus = true;
   }
 
@@ -259,14 +261,21 @@
   // See if a truncate instruction can be turned into a nop.
   switch (MI->getOpcode()) {
   default: break;
-  case X86::TRUNC_GR32_GR16:
-  case X86::TRUNC_GR32_GR8:
-  case X86::TRUNC_GR16_GR8: {
+  case X86::TRUNC_64to32:
+  case X86::TRUNC_64to16:
+  case X86::TRUNC_32to16:
+  case X86::TRUNC_32to8:
+  case X86::TRUNC_16to8:
+  case X86::TRUNC_32_to8:
+  case X86::TRUNC_16_to8: {
     const MachineOperand &MO0 = MI->getOperand(0);
     const MachineOperand &MO1 = MI->getOperand(1);
     unsigned Reg0 = MO0.getReg();
     unsigned Reg1 = MO1.getReg();
-    if (MI->getOpcode() == X86::TRUNC_GR32_GR16)
+    unsigned Opc = MI->getOpcode();
+    if (Opc == X86::TRUNC_64to32)
+      Reg1 = getX86SubSuperRegister(Reg1, MVT::i32);
+    else if (Opc == X86::TRUNC_32to16 || Opc == X86::TRUNC_64to16)
       Reg1 = getX86SubSuperRegister(Reg1, MVT::i16);
     else
       Reg1 = getX86SubSuperRegister(Reg1, MVT::i8);
@@ -275,6 +284,9 @@
       O << "\n\t";
     break;
   }
+  case X86::PsMOVZX64rr32:
+    O << TAI->getCommentString() << " ZERO-EXTEND " << "\n\t";
+    break;
   }
 
   // Call the autogenerated instruction printer routines.


Index: llvm/lib/Target/X86/X86IntelAsmPrinter.h
diff -u llvm/lib/Target/X86/X86IntelAsmPrinter.h:1.23 llvm/lib/Target/X86/X86IntelAsmPrinter.h:1.24
--- llvm/lib/Target/X86/X86IntelAsmPrinter.h:1.23	Thu Sep  7 17:06:40 2006
+++ llvm/lib/Target/X86/X86IntelAsmPrinter.h	Fri Sep  8 01:48:29 2006
@@ -80,6 +80,10 @@
     O << "XMMWORD PTR ";
     printMemReference(MI, OpNo);
   }
+  void printlea64_32mem(const MachineInstr *MI, unsigned OpNo) {
+    O << "QWORD PTR ";
+    printMemReference(MI, OpNo, "subreg64");
+  }
 
   bool printAsmMRegister(const MachineOperand &MO, const char Mode);
   bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
@@ -89,7 +93,8 @@
   void printMachineInstruction(const MachineInstr *MI);
   void printOp(const MachineOperand &MO, const char *Modifier = 0);
   void printSSECC(const MachineInstr *MI, unsigned Op);
-  void printMemReference(const MachineInstr *MI, unsigned Op);
+  void printMemReference(const MachineInstr *MI, unsigned Op,
+                         const char *Modifier=NULL);
   void printPICLabel(const MachineInstr *MI, unsigned Op);
   bool runOnMachineFunction(MachineFunction &F);
   bool doInitialization(Module &M);


Index: llvm/lib/Target/X86/X86JITInfo.cpp
diff -u llvm/lib/Target/X86/X86JITInfo.cpp:1.25 llvm/lib/Target/X86/X86JITInfo.cpp:1.26
--- llvm/lib/Target/X86/X86JITInfo.cpp:1.25	Thu Jul 27 13:21:10 2006
+++ llvm/lib/Target/X86/X86JITInfo.cpp	Fri Sep  8 01:48:29 2006
@@ -42,7 +42,65 @@
 // Provide a wrapper for X86CompilationCallback2 that saves non-traditional
 // callee saved registers, for the fastcc calling convention.
 extern "C" {
-#if defined(__i386__) || defined(i386) || defined(_M_IX86)
+#if defined(__x86_64__)
+  // No need to save EAX/EDX for X86-64.
+  void X86CompilationCallback(void);
+  asm(
+    ".text\n"
+    ".align 8\n"
+    ".globl _X86CompilationCallback\n"
+  "_X86CompilationCallback:\n"
+    // Save RBP
+    "pushq   %rbp\n"
+    // Save RSP
+    "movq    %rsp, %rbp\n"
+    // Save all int arg registers
+    "pushq   %rdi\n"
+    "pushq   %rsi\n"
+    "pushq   %rdx\n"
+    "pushq   %rcx\n"
+    "pushq   %r8\n"
+    "pushq   %r9\n"
+    // Align stack on 16-byte boundary. ESP might not be properly aligned
+    // (8 byte) if this is called from an indirect stub.
+    "andq    $-16, %rsp\n"
+    // Save all XMM arg registers
+    "subq    $128, %rsp\n"
+    "movaps  %xmm0, (%rsp)\n"
+    "movaps  %xmm1, 16(%rsp)\n"
+    "movaps  %xmm2, 32(%rsp)\n"
+    "movaps  %xmm3, 48(%rsp)\n"
+    "movaps  %xmm4, 64(%rsp)\n"
+    "movaps  %xmm5, 80(%rsp)\n"
+    "movaps  %xmm6, 96(%rsp)\n"
+    "movaps  %xmm7, 112(%rsp)\n"
+    // JIT callee
+    "movq    %rbp, %rdi\n"    // Pass prev frame and return address
+    "movq    8(%rbp), %rsi\n"
+    "call    _X86CompilationCallback2\n"
+    // Restore all XMM arg registers
+    "movaps  112(%rsp), %xmm7\n"
+    "movaps  96(%rsp), %xmm6\n"
+    "movaps  80(%rsp), %xmm5\n"
+    "movaps  64(%rsp), %xmm4\n"
+    "movaps  48(%rsp), %xmm3\n"
+    "movaps  32(%rsp), %xmm2\n"
+    "movaps  16(%rsp), %xmm1\n"
+    "movaps  (%rsp), %xmm0\n"
+    // Restore RSP
+    "movq    %rbp, %rsp\n"
+    // Restore all int arg registers
+    "subq    $48, %rsp\n"
+    "popq    %r9\n"
+    "popq    %r8\n"
+    "popq    %rcx\n"
+    "popq    %rdx\n"
+    "popq    %rsi\n"
+    "popq    %rdi\n"
+    // Restore RBP
+    "popq    %rbp\n"
+    "ret\n");
+#elif defined(__i386__) || defined(i386) || defined(_M_IX86)
 #ifndef _MSC_VER
   void X86CompilationCallback(void);
   asm(
@@ -122,7 +180,7 @@
          "Could not find return address on the stack!");
 
   // It's a stub if there is an interrupt marker after the call.
-  bool isStub = ((unsigned char*)(intptr_t)RetAddr)[0] == 0xCD;
+  bool isStub = ((unsigned char*)RetAddr)[0] == 0xCD;
 
   // The call instruction should have pushed the return value onto the stack...
   RetAddr -= 4;  // Backtrack to the reference itself...
@@ -135,20 +193,20 @@
 #endif
 
   // Sanity check to make sure this really is a call instruction.
-  assert(((unsigned char*)(intptr_t)RetAddr)[-1] == 0xE8 &&"Not a call instr!");
+  assert(((unsigned char*)RetAddr)[-1] == 0xE8 &&"Not a call instr!");
 
-  unsigned NewVal = (intptr_t)JITCompilerFunction((void*)(intptr_t)RetAddr);
+  intptr_t NewVal = (intptr_t)JITCompilerFunction((void*)RetAddr);
 
   // Rewrite the call target... so that we don't end up here every time we
   // execute the call.
-  *(unsigned*)(intptr_t)RetAddr = NewVal-RetAddr-4;
+  *(unsigned *)RetAddr = (unsigned)(NewVal-RetAddr-4);
 
   if (isStub) {
     // If this is a stub, rewrite the call into an unconditional branch
     // instruction so that two return addresses are not pushed onto the stack
     // when the requested function finally gets called.  This also makes the
     // 0xCD byte (interrupt) dead, so the marker doesn't effect anything.
-    ((unsigned char*)(intptr_t)RetAddr)[-1] = 0xE9;
+    ((unsigned char*)RetAddr)[-1] = 0xE9;
   }
 
   // Change the return address to reexecute the call instruction...
@@ -189,16 +247,17 @@
     void *RelocPos = (char*)Function + MR->getMachineCodeOffset();
     intptr_t ResultPtr = (intptr_t)MR->getResultPointer();
     switch ((X86::RelocationType)MR->getRelocationType()) {
-    case X86::reloc_pcrel_word:
+    case X86::reloc_pcrel_word: {
       // PC relative relocation, add the relocated value to the value already in
       // memory, after we adjust it for where the PC is.
-      ResultPtr = ResultPtr-(intptr_t)RelocPos-4;
-      *((intptr_t*)RelocPos) += ResultPtr;
+      ResultPtr = ResultPtr-(intptr_t)RelocPos-4-MR->getConstantVal();
+      *((unsigned*)RelocPos) += (unsigned)ResultPtr;
       break;
+    }
     case X86::reloc_absolute_word:
       // Absolute relocation, just add the relocated value to the value already
       // in memory.
-      *((intptr_t*)RelocPos) += ResultPtr;
+      *((unsigned*)RelocPos) += (unsigned)ResultPtr;
       break;
     }
   }


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.167 llvm/lib/Target/X86/X86RegisterInfo.cpp:1.168
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.167	Thu Sep  7 15:32:01 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp	Fri Sep  8 01:48:29 2006
@@ -14,13 +14,13 @@
 
 #include "X86.h"
 #include "X86RegisterInfo.h"
-#include "X86Subtarget.h"
 #include "X86InstrBuilder.h"
 #include "X86MachineFunctionInfo.h"
+#include "X86Subtarget.h"
 #include "X86TargetMachine.h"
 #include "llvm/Constants.h"
-#include "llvm/Type.h"
 #include "llvm/Function.h"
+#include "llvm/Type.h"
 #include "llvm/CodeGen/ValueTypes.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineFunction.h"
@@ -46,15 +46,32 @@
                     cl::Hidden);
 }
 
-X86RegisterInfo::X86RegisterInfo(const TargetInstrInfo &tii)
-  : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP), TII(tii) {}
+X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
+                                 const TargetInstrInfo &tii)
+  : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP),
+    TM(tm), TII(tii) {
+  // Cache some information.
+  const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
+  Is64Bit = Subtarget->is64Bit();
+  if (Is64Bit) {
+    SlotSize = 8;
+    StackPtr = X86::RSP;
+    FramePtr = X86::RBP;
+  } else {
+    SlotSize = 4;
+    StackPtr = X86::ESP;
+    FramePtr = X86::EBP;
+  }
+}
 
 void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
                                           MachineBasicBlock::iterator MI,
                                           unsigned SrcReg, int FrameIdx,
                                           const TargetRegisterClass *RC) const {
   unsigned Opc;
-  if (RC == &X86::GR32RegClass) {
+  if (RC == &X86::GR64RegClass) {
+    Opc = X86::MOV64mr;
+  } else if (RC == &X86::GR32RegClass) {
     Opc = X86::MOV32mr;
   } else if (RC == &X86::GR16RegClass) {
     Opc = X86::MOV16mr;
@@ -84,7 +101,9 @@
                                            unsigned DestReg, int FrameIdx,
                                            const TargetRegisterClass *RC) const{
   unsigned Opc;
-  if (RC == &X86::GR32RegClass) {
+  if (RC == &X86::GR64RegClass) {
+    Opc = X86::MOV64rm;
+  } else if (RC == &X86::GR32RegClass) {
     Opc = X86::MOV32rm;
   } else if (RC == &X86::GR16RegClass) {
     Opc = X86::MOV16rm;
@@ -114,7 +133,9 @@
                                    unsigned DestReg, unsigned SrcReg,
                                    const TargetRegisterClass *RC) const {
   unsigned Opc;
-  if (RC == &X86::GR32RegClass) {
+  if (RC == &X86::GR64RegClass) {
+    Opc = X86::MOV64rr;
+  } else if (RC == &X86::GR32RegClass) {
     Opc = X86::MOV32rr;
   } else if (RC == &X86::GR16RegClass) {
     Opc = X86::MOV16rr;
@@ -270,12 +291,18 @@
       { X86::ADC32ri,     X86::ADC32mi },
       { X86::ADC32ri8,    X86::ADC32mi8 },
       { X86::ADC32rr,     X86::ADC32mr },
+      { X86::ADC64ri32,   X86::ADC64mi32 },
+      { X86::ADC64ri8,    X86::ADC64mi8 },
+      { X86::ADC64rr,     X86::ADC64mr },
       { X86::ADD16ri,     X86::ADD16mi },
       { X86::ADD16ri8,    X86::ADD16mi8 },
       { X86::ADD16rr,     X86::ADD16mr },
       { X86::ADD32ri,     X86::ADD32mi },
       { X86::ADD32ri8,    X86::ADD32mi8 },
       { X86::ADD32rr,     X86::ADD32mr },
+      { X86::ADD64ri32,   X86::ADD64mi32 },
+      { X86::ADD64ri8,    X86::ADD64mi8 },
+      { X86::ADD64rr,     X86::ADD64mr },
       { X86::ADD8ri,      X86::ADD8mi },
       { X86::ADD8rr,      X86::ADD8mr },
       { X86::AND16ri,     X86::AND16mi },
@@ -284,19 +311,30 @@
       { X86::AND32ri,     X86::AND32mi },
       { X86::AND32ri8,    X86::AND32mi8 },
       { X86::AND32rr,     X86::AND32mr },
+      { X86::AND64ri32,   X86::AND64mi32 },
+      { X86::AND64ri8,    X86::AND64mi8 },
+      { X86::AND64rr,     X86::AND64mr },
       { X86::AND8ri,      X86::AND8mi },
       { X86::AND8rr,      X86::AND8mr },
       { X86::DEC16r,      X86::DEC16m },
       { X86::DEC32r,      X86::DEC32m },
+      { X86::DEC64_16r,   X86::DEC16m },
+      { X86::DEC64_32r,   X86::DEC32m },
+      { X86::DEC64r,      X86::DEC64m },
       { X86::DEC8r,       X86::DEC8m },
       { X86::INC16r,      X86::INC16m },
       { X86::INC32r,      X86::INC32m },
+      { X86::INC64_16r,   X86::INC16m },
+      { X86::INC64_32r,   X86::INC32m },
+      { X86::INC64r,      X86::INC64m },
       { X86::INC8r,       X86::INC8m },
       { X86::NEG16r,      X86::NEG16m },
       { X86::NEG32r,      X86::NEG32m },
+      { X86::NEG64r,      X86::NEG64m },
       { X86::NEG8r,       X86::NEG8m },
       { X86::NOT16r,      X86::NOT16m },
       { X86::NOT32r,      X86::NOT32m },
+      { X86::NOT64r,      X86::NOT64m },
       { X86::NOT8r,       X86::NOT8m },
       { X86::OR16ri,      X86::OR16mi },
       { X86::OR16ri8,     X86::OR16mi8 },
@@ -304,6 +342,9 @@
       { X86::OR32ri,      X86::OR32mi },
       { X86::OR32ri8,     X86::OR32mi8 },
       { X86::OR32rr,      X86::OR32mr },
+      { X86::OR64ri32,    X86::OR64mi32 },
+      { X86::OR64ri8,     X86::OR64mi8 },
+      { X86::OR64rr,      X86::OR64mr },
       { X86::OR8ri,       X86::OR8mi },
       { X86::OR8rr,       X86::OR8mr },
       { X86::ROL16r1,     X86::ROL16m1 },
@@ -312,6 +353,9 @@
       { X86::ROL32r1,     X86::ROL32m1 },
       { X86::ROL32rCL,    X86::ROL32mCL },
       { X86::ROL32ri,     X86::ROL32mi },
+      { X86::ROL64r1,     X86::ROL64m1 },
+      { X86::ROL64rCL,    X86::ROL64mCL },
+      { X86::ROL64ri,     X86::ROL64mi },
       { X86::ROL8r1,      X86::ROL8m1 },
       { X86::ROL8rCL,     X86::ROL8mCL },
       { X86::ROL8ri,      X86::ROL8mi },
@@ -321,6 +365,9 @@
       { X86::ROR32r1,     X86::ROR32m1 },
       { X86::ROR32rCL,    X86::ROR32mCL },
       { X86::ROR32ri,     X86::ROR32mi },
+      { X86::ROR64r1,     X86::ROR64m1 },
+      { X86::ROR64rCL,    X86::ROR64mCL },
+      { X86::ROR64ri,     X86::ROR64mi },
       { X86::ROR8r1,      X86::ROR8m1 },
       { X86::ROR8rCL,     X86::ROR8mCL },
       { X86::ROR8ri,      X86::ROR8mi },
@@ -330,18 +377,27 @@
       { X86::SAR32r1,     X86::SAR32m1 },
       { X86::SAR32rCL,    X86::SAR32mCL },
       { X86::SAR32ri,     X86::SAR32mi },
+      { X86::SAR64r1,     X86::SAR64m1 },
+      { X86::SAR64rCL,    X86::SAR64mCL },
+      { X86::SAR64ri,     X86::SAR64mi },
       { X86::SAR8r1,      X86::SAR8m1 },
       { X86::SAR8rCL,     X86::SAR8mCL },
       { X86::SAR8ri,      X86::SAR8mi },
       { X86::SBB32ri,     X86::SBB32mi },
       { X86::SBB32ri8,    X86::SBB32mi8 },
       { X86::SBB32rr,     X86::SBB32mr },
+      { X86::SBB64ri32,   X86::SBB64mi32 },
+      { X86::SBB64ri8,    X86::SBB64mi8 },
+      { X86::SBB64rr,     X86::SBB64mr },
       { X86::SHL16r1,     X86::SHL16m1 },
       { X86::SHL16rCL,    X86::SHL16mCL },
       { X86::SHL16ri,     X86::SHL16mi },
       { X86::SHL32r1,     X86::SHL32m1 },
       { X86::SHL32rCL,    X86::SHL32mCL },
       { X86::SHL32ri,     X86::SHL32mi },
+      { X86::SHL64r1,     X86::SHL64m1 },
+      { X86::SHL64rCL,    X86::SHL64mCL },
+      { X86::SHL64ri,     X86::SHL64mi },
       { X86::SHL8r1,      X86::SHL8m1 },
       { X86::SHL8rCL,     X86::SHL8mCL },
       { X86::SHL8ri,      X86::SHL8mi },
@@ -349,12 +405,17 @@
       { X86::SHLD16rri8,  X86::SHLD16mri8 },
       { X86::SHLD32rrCL,  X86::SHLD32mrCL },
       { X86::SHLD32rri8,  X86::SHLD32mri8 },
+      { X86::SHLD64rrCL,  X86::SHLD64mrCL },
+      { X86::SHLD64rri8,  X86::SHLD64mri8 },
       { X86::SHR16r1,     X86::SHR16m1 },
       { X86::SHR16rCL,    X86::SHR16mCL },
       { X86::SHR16ri,     X86::SHR16mi },
       { X86::SHR32r1,     X86::SHR32m1 },
       { X86::SHR32rCL,    X86::SHR32mCL },
       { X86::SHR32ri,     X86::SHR32mi },
+      { X86::SHR64r1,     X86::SHR64m1 },
+      { X86::SHR64rCL,    X86::SHR64mCL },
+      { X86::SHR64ri,     X86::SHR64mi },
       { X86::SHR8r1,      X86::SHR8m1 },
       { X86::SHR8rCL,     X86::SHR8mCL },
       { X86::SHR8ri,      X86::SHR8mi },
@@ -362,12 +423,17 @@
       { X86::SHRD16rri8,  X86::SHRD16mri8 },
       { X86::SHRD32rrCL,  X86::SHRD32mrCL },
       { X86::SHRD32rri8,  X86::SHRD32mri8 },
+      { X86::SHRD64rrCL,  X86::SHRD64mrCL },
+      { X86::SHRD64rri8,  X86::SHRD64mri8 },
       { X86::SUB16ri,     X86::SUB16mi },
       { X86::SUB16ri8,    X86::SUB16mi8 },
       { X86::SUB16rr,     X86::SUB16mr },
       { X86::SUB32ri,     X86::SUB32mi },
       { X86::SUB32ri8,    X86::SUB32mi8 },
       { X86::SUB32rr,     X86::SUB32mr },
+      { X86::SUB64ri32,   X86::SUB64mi32 },
+      { X86::SUB64ri8,    X86::SUB64mi8 },
+      { X86::SUB64rr,     X86::SUB64mr },
       { X86::SUB8ri,      X86::SUB8mi },
       { X86::SUB8rr,      X86::SUB8mr },
       { X86::XOR16ri,     X86::XOR16mi },
@@ -376,6 +442,9 @@
       { X86::XOR32ri,     X86::XOR32mi },
       { X86::XOR32ri8,    X86::XOR32mi8 },
       { X86::XOR32rr,     X86::XOR32mr },
+      { X86::XOR64ri32,   X86::XOR64mi32 },
+      { X86::XOR64ri8,    X86::XOR64mi8 },
+      { X86::XOR64rr,     X86::XOR64mr },
       { X86::XOR8ri,      X86::XOR8mi },
       { X86::XOR8rr,      X86::XOR8mr }
     };
@@ -388,6 +457,8 @@
       return MakeM0Inst(X86::MOV16mi, FrameIndex, MI);
     else if (MI->getOpcode() == X86::MOV32r0)
       return MakeM0Inst(X86::MOV32mi, FrameIndex, MI);
+    else if (MI->getOpcode() == X86::MOV64r0)
+      return MakeM0Inst(X86::MOV64mi32, FrameIndex, MI);
     else if (MI->getOpcode() == X86::MOV8r0)
       return MakeM0Inst(X86::MOV8mi, FrameIndex, MI);
     
@@ -399,19 +470,24 @@
       { X86::CMP8ri,      X86::CMP8mi },
       { X86::DIV16r,      X86::DIV16m },
       { X86::DIV32r,      X86::DIV32m },
+      { X86::DIV64r,      X86::DIV64m },
       { X86::DIV8r,       X86::DIV8m },
       { X86::FsMOVAPDrr,  X86::MOVSDmr },
       { X86::FsMOVAPSrr,  X86::MOVSSmr },
       { X86::IDIV16r,     X86::IDIV16m },
       { X86::IDIV32r,     X86::IDIV32m },
+      { X86::IDIV64r,     X86::IDIV64m },
       { X86::IDIV8r,      X86::IDIV8m },
       { X86::IMUL16r,     X86::IMUL16m },
       { X86::IMUL32r,     X86::IMUL32m },
+      { X86::IMUL64r,     X86::IMUL64m },
       { X86::IMUL8r,      X86::IMUL8m },
       { X86::MOV16ri,     X86::MOV16mi },
       { X86::MOV16rr,     X86::MOV16mr },
       { X86::MOV32ri,     X86::MOV32mi },
       { X86::MOV32rr,     X86::MOV32mr },
+      { X86::MOV64ri32,   X86::MOV64mi32 },
+      { X86::MOV64rr,     X86::MOV64mr },
       { X86::MOV8ri,      X86::MOV8mi },
       { X86::MOV8rr,      X86::MOV8mr },
       { X86::MOVAPDrr,    X86::MOVAPDmr },
@@ -424,6 +500,7 @@
       { X86::MOVUPSrr,    X86::MOVUPSmr },
       { X86::MUL16r,      X86::MUL16m },
       { X86::MUL32r,      X86::MUL32m },
+      { X86::MUL64r,      X86::MUL64m },
       { X86::MUL8r,       X86::MUL8m },
       { X86::SETAEr,      X86::SETAEm },
       { X86::SETAr,       X86::SETAm },
@@ -441,9 +518,11 @@
       { X86::SETSr,       X86::SETSm },
       { X86::TEST16ri,    X86::TEST16mi },
       { X86::TEST32ri,    X86::TEST32mi },
+      { X86::TEST64ri32,  X86::TEST64mi32 },
       { X86::TEST8ri,     X86::TEST8mi },
       { X86::XCHG16rr,    X86::XCHG16mr },
       { X86::XCHG32rr,    X86::XCHG32mr },
+      { X86::XCHG64rr,    X86::XCHG64mr },
       { X86::XCHG8rr,     X86::XCHG8mr }
     };
     ASSERT_SORTED(OpcodeTable);
@@ -453,16 +532,23 @@
     static const TableEntry OpcodeTable[] = {
       { X86::CMP16rr,         X86::CMP16rm },
       { X86::CMP32rr,         X86::CMP32rm },
+      { X86::CMP64ri32,       X86::CMP64mi32 },
+      { X86::CMP64ri8,        X86::CMP64mi8 },
+      { X86::CMP64rr,         X86::CMP64rm },
       { X86::CMP8rr,          X86::CMP8rm },
       { X86::CMPPDrri,        X86::CMPPDrmi },
       { X86::CMPPSrri,        X86::CMPPSrmi },
       { X86::CMPSDrr,         X86::CMPSDrm },
       { X86::CMPSSrr,         X86::CMPSSrm },
       { X86::CVTSD2SSrr,      X86::CVTSD2SSrm },
+      { X86::CVTSI2SD64rr,    X86::CVTSI2SD64rm },
       { X86::CVTSI2SDrr,      X86::CVTSI2SDrm },
+      { X86::CVTSI2SS64rr,    X86::CVTSI2SS64rm },
       { X86::CVTSI2SSrr,      X86::CVTSI2SSrm },
       { X86::CVTSS2SDrr,      X86::CVTSS2SDrm },
+      { X86::CVTTSD2SI64rr,   X86::CVTTSD2SI64rm },
       { X86::CVTTSD2SIrr,     X86::CVTTSD2SIrm },
+      { X86::CVTTSS2SI64rr,   X86::CVTTSS2SI64rm },
       { X86::CVTTSS2SIrr,     X86::CVTTSS2SIrm },
       { X86::FsMOVAPDrr,      X86::MOVSDrm },
       { X86::FsMOVAPSrr,      X86::MOVSSrm },
@@ -470,6 +556,9 @@
       { X86::IMUL16rri8,      X86::IMUL16rmi8 },
       { X86::IMUL32rri,       X86::IMUL32rmi },
       { X86::IMUL32rri8,      X86::IMUL32rmi8 },
+      { X86::IMUL64rr,        X86::IMUL64rm },
+      { X86::IMUL64rri32,     X86::IMUL64rmi32 },
+      { X86::IMUL64rri8,      X86::IMUL64rmi8 },
       { X86::Int_CMPSDrr,     X86::Int_CMPSDrm },
       { X86::Int_CMPSSrr,     X86::Int_CMPSSrm },
       { X86::Int_COMISDrr,    X86::Int_COMISDrm },
@@ -480,20 +569,27 @@
       { X86::Int_CVTPD2PSrr,  X86::Int_CVTPD2PSrm },
       { X86::Int_CVTPS2DQrr,  X86::Int_CVTPS2DQrm },
       { X86::Int_CVTPS2PDrr,  X86::Int_CVTPS2PDrm },
+      { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm },
       { X86::Int_CVTSD2SIrr,  X86::Int_CVTSD2SIrm },
       { X86::Int_CVTSD2SSrr,  X86::Int_CVTSD2SSrm },
+      { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm },
       { X86::Int_CVTSI2SDrr,  X86::Int_CVTSI2SDrm },
+      { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm },
       { X86::Int_CVTSI2SSrr,  X86::Int_CVTSI2SSrm },
       { X86::Int_CVTSS2SDrr,  X86::Int_CVTSS2SDrm },
+      { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm },
       { X86::Int_CVTSS2SIrr,  X86::Int_CVTSS2SIrm },
       { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm },
       { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm },
+      { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm },
       { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm },
+      { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm },
       { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm },
       { X86::Int_UCOMISDrr,   X86::Int_UCOMISDrm },
       { X86::Int_UCOMISSrr,   X86::Int_UCOMISSrm },
       { X86::MOV16rr,         X86::MOV16rm },
       { X86::MOV32rr,         X86::MOV32rm },
+      { X86::MOV64rr,         X86::MOV64rm },
       { X86::MOV8rr,          X86::MOV8rm },
       { X86::MOVAPDrr,        X86::MOVAPDrm },
       { X86::MOVAPSrr,        X86::MOVAPSrm },
@@ -509,22 +605,30 @@
       { X86::MOVSX16rr8,      X86::MOVSX16rm8 },
       { X86::MOVSX32rr16,     X86::MOVSX32rm16 },
       { X86::MOVSX32rr8,      X86::MOVSX32rm8 },
+      { X86::MOVSX64rr16,     X86::MOVSX64rm16 },
+      { X86::MOVSX64rr32,     X86::MOVSX64rm32 },
+      { X86::MOVSX64rr8,      X86::MOVSX64rm8 },
       { X86::MOVUPDrr,        X86::MOVUPDrm },
       { X86::MOVUPSrr,        X86::MOVUPSrm },
       { X86::MOVZX16rr8,      X86::MOVZX16rm8 },
       { X86::MOVZX32rr16,     X86::MOVZX32rm16 },
       { X86::MOVZX32rr8,      X86::MOVZX32rm8 },
+      { X86::MOVZX64rr16,     X86::MOVZX64rm16 },
+      { X86::MOVZX64rr8,      X86::MOVZX64rm8 },
       { X86::PSHUFDri,        X86::PSHUFDmi },
       { X86::PSHUFHWri,       X86::PSHUFHWmi },
       { X86::PSHUFLWri,       X86::PSHUFLWmi },
+      { X86::PsMOVZX64rr32,   X86::PsMOVZX64rm32 },
       { X86::TEST16rr,        X86::TEST16rm },
       { X86::TEST32rr,        X86::TEST32rm },
+      { X86::TEST64rr,        X86::TEST64rm },
       { X86::TEST8rr,         X86::TEST8rm },
       // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
       { X86::UCOMISDrr,       X86::UCOMISDrm },
       { X86::UCOMISSrr,       X86::UCOMISSrm },
       { X86::XCHG16rr,        X86::XCHG16rm },
       { X86::XCHG32rr,        X86::XCHG32rm },
+      { X86::XCHG64rr,        X86::XCHG64rm },
       { X86::XCHG8rr,         X86::XCHG8rm }
     };
     ASSERT_SORTED(OpcodeTable);
@@ -533,8 +637,10 @@
   } else if (i == 2) {
     static const TableEntry OpcodeTable[] = {
       { X86::ADC32rr,         X86::ADC32rm },
+      { X86::ADC64rr,         X86::ADC64rm },
       { X86::ADD16rr,         X86::ADD16rm },
       { X86::ADD32rr,         X86::ADD32rm },
+      { X86::ADD64rr,         X86::ADD64rm },
       { X86::ADD8rr,          X86::ADD8rm },
       { X86::ADDPDrr,         X86::ADDPDrm },
       { X86::ADDPSrr,         X86::ADDPSrm },
@@ -544,6 +650,7 @@
       { X86::ADDSUBPSrr,      X86::ADDSUBPSrm },
       { X86::AND16rr,         X86::AND16rm },
       { X86::AND32rr,         X86::AND32rm },
+      { X86::AND64rr,         X86::AND64rm },
       { X86::AND8rr,          X86::AND8rm },
       { X86::ANDNPDrr,        X86::ANDNPDrm },
       { X86::ANDNPSrr,        X86::ANDNPSrm },
@@ -551,32 +658,46 @@
       { X86::ANDPSrr,         X86::ANDPSrm },
       { X86::CMOVA16rr,       X86::CMOVA16rm },
       { X86::CMOVA32rr,       X86::CMOVA32rm },
+      { X86::CMOVA64rr,       X86::CMOVA64rm },
       { X86::CMOVAE16rr,      X86::CMOVAE16rm },
       { X86::CMOVAE32rr,      X86::CMOVAE32rm },
+      { X86::CMOVAE64rr,      X86::CMOVAE64rm },
       { X86::CMOVB16rr,       X86::CMOVB16rm },
       { X86::CMOVB32rr,       X86::CMOVB32rm },
+      { X86::CMOVB64rr,       X86::CMOVB64rm },
       { X86::CMOVBE16rr,      X86::CMOVBE16rm },
       { X86::CMOVBE32rr,      X86::CMOVBE32rm },
+      { X86::CMOVBE64rr,      X86::CMOVBE64rm },
       { X86::CMOVE16rr,       X86::CMOVE16rm },
       { X86::CMOVE32rr,       X86::CMOVE32rm },
+      { X86::CMOVE64rr,       X86::CMOVE64rm },
       { X86::CMOVG16rr,       X86::CMOVG16rm },
       { X86::CMOVG32rr,       X86::CMOVG32rm },
+      { X86::CMOVG64rr,       X86::CMOVG64rm },
       { X86::CMOVGE16rr,      X86::CMOVGE16rm },
       { X86::CMOVGE32rr,      X86::CMOVGE32rm },
+      { X86::CMOVGE64rr,      X86::CMOVGE64rm },
       { X86::CMOVL16rr,       X86::CMOVL16rm },
       { X86::CMOVL32rr,       X86::CMOVL32rm },
+      { X86::CMOVL64rr,       X86::CMOVL64rm },
       { X86::CMOVLE16rr,      X86::CMOVLE16rm },
       { X86::CMOVLE32rr,      X86::CMOVLE32rm },
+      { X86::CMOVLE64rr,      X86::CMOVLE64rm },
       { X86::CMOVNE16rr,      X86::CMOVNE16rm },
       { X86::CMOVNE32rr,      X86::CMOVNE32rm },
+      { X86::CMOVNE64rr,      X86::CMOVNE64rm },
       { X86::CMOVNP16rr,      X86::CMOVNP16rm },
       { X86::CMOVNP32rr,      X86::CMOVNP32rm },
+      { X86::CMOVNP64rr,      X86::CMOVNP64rm },
       { X86::CMOVNS16rr,      X86::CMOVNS16rm },
       { X86::CMOVNS32rr,      X86::CMOVNS32rm },
+      { X86::CMOVNS64rr,      X86::CMOVNS64rm },
       { X86::CMOVP16rr,       X86::CMOVP16rm },
       { X86::CMOVP32rr,       X86::CMOVP32rm },
+      { X86::CMOVP64rr,       X86::CMOVP64rm },
       { X86::CMOVS16rr,       X86::CMOVS16rm },
       { X86::CMOVS32rr,       X86::CMOVS32rm },
+      { X86::CMOVS64rr,       X86::CMOVS64rm },
       { X86::DIVPDrr,         X86::DIVPDrm },
       { X86::DIVPSrr,         X86::DIVPSrm },
       { X86::DIVSDrr,         X86::DIVSDrm },
@@ -597,6 +718,7 @@
       { X86::MULSSrr,         X86::MULSSrm },
       { X86::OR16rr,          X86::OR16rm },
       { X86::OR32rr,          X86::OR32rm },
+      { X86::OR64rr,          X86::OR64rm },
       { X86::OR8rr,           X86::OR8rm },
       { X86::ORPDrr,          X86::ORPDrm },
       { X86::ORPSrr,          X86::ORPSrm },
@@ -655,6 +777,7 @@
       { X86::RCPPSr,          X86::RCPPSm },
       { X86::RSQRTPSr,        X86::RSQRTPSm },
       { X86::SBB32rr,         X86::SBB32rm },
+      { X86::SBB64rr,         X86::SBB64rm },
       { X86::SHUFPDrri,       X86::SHUFPDrmi },
       { X86::SHUFPSrri,       X86::SHUFPSrmi },
       { X86::SQRTPDr,         X86::SQRTPDm },
@@ -663,6 +786,7 @@
       { X86::SQRTSSr,         X86::SQRTSSm },
       { X86::SUB16rr,         X86::SUB16rm },
       { X86::SUB32rr,         X86::SUB32rm },
+      { X86::SUB64rr,         X86::SUB64rm },
       { X86::SUB8rr,          X86::SUB8rm },
       { X86::SUBPDrr,         X86::SUBPDrm },
       { X86::SUBPSrr,         X86::SUBPSrm },
@@ -675,6 +799,7 @@
       { X86::UNPCKLPSrr,      X86::UNPCKLPSrm },
       { X86::XOR16rr,         X86::XOR16rm },
       { X86::XOR32rr,         X86::XOR32rm },
+      { X86::XOR64rr,         X86::XOR64rm },
       { X86::XOR8rr,          X86::XOR8rm },
       { X86::XORPDrr,         X86::XORPDrm },
       { X86::XORPSrr,         X86::XORPSrm }
@@ -707,19 +832,29 @@
 
 
 const unsigned *X86RegisterInfo::getCalleeSaveRegs() const {
-  static const unsigned CalleeSaveRegs[] = {
+  static const unsigned CalleeSaveRegs32Bit[] = {
     X86::ESI, X86::EDI, X86::EBX, X86::EBP,  0
   };
-  return CalleeSaveRegs;
+  static const unsigned CalleeSaveRegs64Bit[] = {
+    X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
+  };
+
+  return Is64Bit ? CalleeSaveRegs64Bit : CalleeSaveRegs32Bit;
 }
 
 const TargetRegisterClass* const*
 X86RegisterInfo::getCalleeSaveRegClasses() const {
-  static const TargetRegisterClass * const CalleeSaveRegClasses[] = {
+  static const TargetRegisterClass * const CalleeSaveRegClasses32Bit[] = {
     &X86::GR32RegClass, &X86::GR32RegClass,
     &X86::GR32RegClass, &X86::GR32RegClass,  0
   };
-  return CalleeSaveRegClasses;
+  static const TargetRegisterClass * const CalleeSaveRegClasses64Bit[] = {
+    &X86::GR64RegClass, &X86::GR64RegClass,
+    &X86::GR64RegClass, &X86::GR64RegClass,
+    &X86::GR64RegClass, &X86::GR64RegClass, 0
+  };
+
+  return Is64Bit ? CalleeSaveRegClasses64Bit : CalleeSaveRegClasses32Bit;
 }
 
 //===----------------------------------------------------------------------===//
@@ -754,15 +889,18 @@
 
       MachineInstr *New = 0;
       if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
-        New=BuildMI(X86::SUB32ri, 2, X86::ESP).addReg(X86::ESP).addImm(Amount);
+        New=BuildMI(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri, 1, StackPtr)
+          .addReg(StackPtr).addImm(Amount);
       } else {
         assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
         // factor out the amount the callee already popped.
         unsigned CalleeAmt = Old->getOperand(1).getImmedValue();
         Amount -= CalleeAmt;
         if (Amount) {
-          unsigned Opc = Amount < 128 ? X86::ADD32ri8 : X86::ADD32ri;
-          New = BuildMI(Opc, 2, X86::ESP).addReg(X86::ESP).addImm(Amount);
+          unsigned Opc = (Amount < 128) ?
+            (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
+            (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
+          New = BuildMI(Opc, 1,  StackPtr).addReg(StackPtr).addImm(Amount);
         }
       }
 
@@ -774,9 +912,11 @@
     // something off the stack pointer, add it back.  We do this until we have
     // more advanced stack pointer tracking ability.
     if (unsigned CalleeAmt = I->getOperand(1).getImmedValue()) {
-      unsigned Opc = CalleeAmt < 128 ? X86::SUB32ri8 : X86::SUB32ri;
+      unsigned Opc = (CalleeAmt < 128) ?
+        (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
+        (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
       MachineInstr *New =
-        BuildMI(Opc, 1, X86::ESP).addReg(X86::ESP).addImm(CalleeAmt);
+        BuildMI(Opc, 1, StackPtr).addReg(StackPtr).addImm(CalleeAmt);
       MBB.insert(I, New);
     }
   }
@@ -794,19 +934,18 @@
   }
 
   int FrameIndex = MI.getOperand(i).getFrameIndex();
-
   // This must be part of a four operand memory reference.  Replace the
-  // FrameIndex with base register with EBP.  Add add an offset to the offset.
-  MI.getOperand(i).ChangeToRegister(hasFP(MF) ? X86::EBP : X86::ESP, false);
+  // FrameIndex with base register with EBP.  Add an offset to the offset.
+  MI.getOperand(i).ChangeToRegister(hasFP(MF) ? FramePtr : StackPtr, false);
 
   // Now add the frame object offset to the offset from EBP.
   int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
-               MI.getOperand(i+3).getImmedValue()+4;
+               MI.getOperand(i+3).getImmedValue()+SlotSize;
 
   if (!hasFP(MF))
     Offset += MF.getFrameInfo()->getStackSize();
   else
-    Offset += 4;  // Skip the saved EBP
+    Offset += SlotSize;  // Skip the saved EBP
 
   MI.getOperand(i+3).ChangeToImmediate(Offset);
 }
@@ -815,7 +954,7 @@
 X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
   if (hasFP(MF)) {
     // Create a frame entry for the EBP register that must be saved.
-    int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, -8);
+    int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize,SlotSize * -2);
     assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
            "Slot for EBP register must be last in order to be found!");
   }
@@ -840,9 +979,9 @@
     if (!hasFP(MF))
       NumBytes += MFI->getMaxCallFrameSize();
 
-    // Round the size to a multiple of the alignment (don't forget the 4 byte
+    // Round the size to a multiple of the alignment (don't forget the 4/8 byte
     // offset though).
-    NumBytes = ((NumBytes+4)+Align-1)/Align*Align - 4;
+    NumBytes = ((NumBytes+SlotSize)+Align-1)/Align*Align - SlotSize;
   }
 
   // Update frame info to pretend that this is part of the stack...
@@ -859,8 +998,10 @@
       MI = BuildMI(X86::CALLpcrel32, 1).addExternalSymbol("_alloca");
       MBB.insert(MBBI, MI);
     } else {
-      unsigned Opc = NumBytes < 128 ? X86::SUB32ri8 : X86::SUB32ri;
-      MI = BuildMI(Opc, 2, X86::ESP).addReg(X86::ESP).addImm(NumBytes);
+      unsigned Opc = (NumBytes < 128) ?
+        (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
+        (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
+      MI= BuildMI(Opc, 1, StackPtr).addReg(StackPtr).addImm(NumBytes);
       MBB.insert(MBBI, MI);
     }
   }
@@ -868,18 +1009,21 @@
   if (hasFP(MF)) {
     // Get the offset of the stack slot for the EBP register... which is
     // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
-    int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexBegin())+4;
+    int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexBegin())+SlotSize;
 
     // Save EBP into the appropriate stack slot...
-    MI = addRegOffset(BuildMI(X86::MOV32mr, 5),    // mov [ESP-<offset>], EBP
-                      X86::ESP, EBPOffset+NumBytes).addReg(X86::EBP);
+    // mov [ESP-<offset>], EBP
+    MI = addRegOffset(BuildMI(Is64Bit ? X86::MOV64mr : X86::MOV32mr, 5),
+                      StackPtr, EBPOffset+NumBytes).addReg(FramePtr);
     MBB.insert(MBBI, MI);
 
     // Update EBP with the new base value...
-    if (NumBytes == 4)    // mov EBP, ESP
-      MI = BuildMI(X86::MOV32rr, 2, X86::EBP).addReg(X86::ESP);
+    if (NumBytes == SlotSize)    // mov EBP, ESP
+      MI = BuildMI(Is64Bit ? X86::MOV64rr : X86::MOV32rr, 2, FramePtr).
+        addReg(StackPtr);
     else                  // lea EBP, [ESP+StackSize]
-      MI = addRegOffset(BuildMI(X86::LEA32r, 5, X86::EBP), X86::ESP,NumBytes-4);
+      MI = addRegOffset(BuildMI(Is64Bit ? X86::LEA64r : X86::LEA32r,
+                               5, FramePtr), StackPtr, NumBytes-SlotSize);
 
     MBB.insert(MBBI, MI);
   }
@@ -916,13 +1060,14 @@
   if (hasFP(MF)) {
     // Get the offset of the stack slot for the EBP register... which is
     // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
-    int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexEnd()-1)+4;
+    int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexEnd()-1)+SlotSize;
 
     // mov ESP, EBP
-    BuildMI(MBB, MBBI, X86::MOV32rr, 1, X86::ESP).addReg(X86::EBP);
+    BuildMI(MBB, MBBI, Is64Bit ? X86::MOV64rr : X86::MOV32rr, 1, StackPtr).
+      addReg(FramePtr);
 
     // pop EBP
-    BuildMI(MBB, MBBI, X86::POP32r, 0, X86::EBP);
+    BuildMI(MBB, MBBI, Is64Bit ? X86::POP64r : X86::POP32r, 0, FramePtr);
   } else {
     // Get the number of bytes allocated from the FrameInfo...
     unsigned NumBytes = MFI->getStackSize();
@@ -932,14 +1077,15 @@
       // instruction, merge the two instructions.
       if (MBBI != MBB.begin()) {
         MachineBasicBlock::iterator PI = prior(MBBI);
-        if ((PI->getOpcode() == X86::ADD32ri || 
-             PI->getOpcode() == X86::ADD32ri8) &&
-            PI->getOperand(0).getReg() == X86::ESP) {
+        unsigned Opc = PI->getOpcode();
+        if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
+             Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
+            PI->getOperand(0).getReg() == StackPtr) {
           NumBytes += PI->getOperand(2).getImmedValue();
           MBB.erase(PI);
-        } else if ((PI->getOpcode() == X86::SUB32ri ||
-                    PI->getOpcode() == X86::SUB32ri8) &&
-                   PI->getOperand(0).getReg() == X86::ESP) {
+        } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
+                    Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
+                   PI->getOperand(0).getReg() == StackPtr) {
           NumBytes -= PI->getOperand(2).getImmedValue();
           MBB.erase(PI);
         } else if (PI->getOpcode() == X86::ADJSTACKPTRri) {
@@ -949,11 +1095,15 @@
       }
 
       if (NumBytes > 0) {
-        unsigned Opc = NumBytes < 128 ? X86::ADD32ri8 : X86::ADD32ri;
-        BuildMI(MBB, MBBI, Opc, 2, X86::ESP).addReg(X86::ESP).addImm(NumBytes);
+        unsigned Opc = (NumBytes < 128) ?
+          (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
+          (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
+        BuildMI(MBB, MBBI, Opc, 2, StackPtr).addReg(StackPtr).addImm(NumBytes);
       } else if ((int)NumBytes < 0) {
-        unsigned Opc = -NumBytes < 128 ? X86::SUB32ri8 : X86::SUB32ri;
-        BuildMI(MBB, MBBI, Opc, 2, X86::ESP).addReg(X86::ESP).addImm(-NumBytes);
+        unsigned Opc = (-NumBytes < 128) ?
+          (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
+          (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
+        BuildMI(MBB, MBBI, Opc, 2, StackPtr).addReg(StackPtr).addImm(-NumBytes);
       }
     }
   }
@@ -964,7 +1114,7 @@
 }
 
 unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
-  return hasFP(MF) ? X86::EBP : X86::ESP;
+  return hasFP(MF) ? FramePtr : StackPtr;
 }
 
 namespace llvm {
@@ -974,68 +1124,160 @@
   case MVT::i8:
     if (High) {
       switch (Reg) {
-      default: return Reg;
-      case X86::AH: case X86::AL: case X86::AX: case X86::EAX:
+      default: return 0;
+      case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
         return X86::AH;
-      case X86::DH: case X86::DL: case X86::DX: case X86::EDX:
+      case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
         return X86::DH;
-      case X86::CH: case X86::CL: case X86::CX: case X86::ECX:
+      case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
         return X86::CH;
-      case X86::BH: case X86::BL: case X86::BX: case X86::EBX:
+      case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
         return X86::BH;
       }
     } else {
       switch (Reg) {
-      default: return Reg;
-      case X86::AH: case X86::AL: case X86::AX: case X86::EAX:
+      default: return 0;
+      case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
         return X86::AL;
-      case X86::DH: case X86::DL: case X86::DX: case X86::EDX:
+      case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
         return X86::DL;
-      case X86::CH: case X86::CL: case X86::CX: case X86::ECX:
+      case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
         return X86::CL;
-      case X86::BH: case X86::BL: case X86::BX: case X86::EBX:
+      case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
         return X86::BL;
+      case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
+        return X86::SIL;
+      case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
+        return X86::DIL;
+      case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
+        return X86::BPL;
+      case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
+        return X86::SPL;
+      case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
+        return X86::R8B;
+      case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
+        return X86::R9B;
+      case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
+        return X86::R10B;
+      case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
+        return X86::R11B;
+      case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
+        return X86::R12B;
+      case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
+        return X86::R13B;
+      case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
+        return X86::R14B;
+      case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
+        return X86::R15B;
       }
     }
   case MVT::i16:
     switch (Reg) {
     default: return Reg;
-    case X86::AH: case X86::AL: case X86::AX: case X86::EAX:
+    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
       return X86::AX;
-    case X86::DH: case X86::DL: case X86::DX: case X86::EDX:
+    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
       return X86::DX;
-    case X86::CH: case X86::CL: case X86::CX: case X86::ECX:
+    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
       return X86::CX;
-    case X86::BH: case X86::BL: case X86::BX: case X86::EBX:
+    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
       return X86::BX;
-    case X86::ESI:
+    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
       return X86::SI;
-    case X86::EDI:
+    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
       return X86::DI;
-    case X86::EBP:
+    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
       return X86::BP;
-    case X86::ESP:
+    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
       return X86::SP;
+    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
+      return X86::R8W;
+    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
+      return X86::R9W;
+    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
+      return X86::R10W;
+    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
+      return X86::R11W;
+    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
+      return X86::R12W;
+    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
+      return X86::R13W;
+    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
+      return X86::R14W;
+    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
+      return X86::R15W;
     }
   case MVT::i32:
     switch (Reg) {
-    default: return true;
-    case X86::AH: case X86::AL: case X86::AX: case X86::EAX:
+    default: return Reg;
+    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
       return X86::EAX;
-    case X86::DH: case X86::DL: case X86::DX: case X86::EDX:
+    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
       return X86::EDX;
-    case X86::CH: case X86::CL: case X86::CX: case X86::ECX:
+    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
       return X86::ECX;
-    case X86::BH: case X86::BL: case X86::BX: case X86::EBX:
+    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
       return X86::EBX;
-    case X86::SI:
+    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
       return X86::ESI;
-    case X86::DI:
+    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
       return X86::EDI;
-    case X86::BP:
+    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
       return X86::EBP;
-    case X86::SP:
+    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
       return X86::ESP;
+    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
+      return X86::R8D;
+    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
+      return X86::R9D;
+    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
+      return X86::R10D;
+    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
+      return X86::R11D;
+    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
+      return X86::R12D;
+    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
+      return X86::R13D;
+    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
+      return X86::R14D;
+    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
+      return X86::R15D;
+    }
+  case MVT::i64:
+    switch (Reg) {
+    default: return Reg;
+    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
+      return X86::RAX;
+    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
+      return X86::RDX;
+    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
+      return X86::RCX;
+    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
+      return X86::RBX;
+    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
+      return X86::RSI;
+    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
+      return X86::RDI;
+    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
+      return X86::RBP;
+    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
+      return X86::RSP;
+    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
+      return X86::R8;
+    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
+      return X86::R9;
+    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
+      return X86::R10;
+    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
+      return X86::R11;
+    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
+      return X86::R12;
+    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
+      return X86::R13;
+    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
+      return X86::R14;
+    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
+      return X86::R15;
     }
   }
 


Index: llvm/lib/Target/X86/X86RegisterInfo.h
diff -u llvm/lib/Target/X86/X86RegisterInfo.h:1.40 llvm/lib/Target/X86/X86RegisterInfo.h:1.41
--- llvm/lib/Target/X86/X86RegisterInfo.h:1.40	Mon Sep  4 21:12:02 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.h	Fri Sep  8 01:48:29 2006
@@ -20,10 +20,26 @@
 namespace llvm {
   class Type;
   class TargetInstrInfo;
+  class X86TargetMachine;
 
 struct X86RegisterInfo : public X86GenRegisterInfo {
+  X86TargetMachine &TM;
   const TargetInstrInfo &TII;
-  X86RegisterInfo(const TargetInstrInfo &tii);
+private:
+  /// Is64Bit - Is the target 64-bits.
+  bool Is64Bit;
+
+  /// SlotSize - Stack slot size in bytes.
+  unsigned SlotSize;
+
+  /// StackPtr - X86 physical register used as stack ptr.
+  unsigned StackPtr;
+
+  /// FramePtr - X86 physical register used as frame ptr.
+  unsigned FramePtr;
+
+public:
+  X86RegisterInfo(X86TargetMachine &tm, const TargetInstrInfo &tii);
 
   /// Code Generation virtual methods...
   void storeRegToStackSlot(MachineBasicBlock &MBB,


Index: llvm/lib/Target/X86/X86RegisterInfo.td
diff -u llvm/lib/Target/X86/X86RegisterInfo.td:1.38 llvm/lib/Target/X86/X86RegisterInfo.td:1.39
--- llvm/lib/Target/X86/X86RegisterInfo.td:1.38	Thu Aug 17 17:00:08 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.td	Fri Sep  8 01:48:29 2006
@@ -23,35 +23,92 @@
   // because the register file generator is smart enough to figure out that
   // AL aliases AX if we tell it that AX aliased AL (for example).
 
+  // FIXME: X86-64 have different Dwarf numbers.
+  // 64-bit registers, X86-64 only
+  def RAX : Register<"RAX">, DwarfRegNum<0>;
+  def RDX : Register<"RDX">, DwarfRegNum<1>;
+  def RCX : Register<"RCX">, DwarfRegNum<2>;
+  def RBX : Register<"RBX">, DwarfRegNum<3>;
+  def RSI : Register<"RSI">, DwarfRegNum<4>;
+  def RDI : Register<"RDI">, DwarfRegNum<5>;
+  def RBP : Register<"RBP">, DwarfRegNum<6>;
+  def RSP : Register<"RSP">, DwarfRegNum<7>;
+
+  def R8  : Register<"R8">,  DwarfRegNum<8>;
+  def R9  : Register<"R9">,  DwarfRegNum<9>;
+  def R10 : Register<"R10">, DwarfRegNum<10>;
+  def R11 : Register<"R11">, DwarfRegNum<11>;
+  def R12 : Register<"R12">, DwarfRegNum<12>;
+  def R13 : Register<"R13">, DwarfRegNum<13>;
+  def R14 : Register<"R14">, DwarfRegNum<14>;
+  def R15 : Register<"R15">, DwarfRegNum<15>;
+
   // 32-bit registers
-  def EAX : Register<"EAX">, DwarfRegNum<0>;
-  def ECX : Register<"ECX">, DwarfRegNum<1>;
-  def EDX : Register<"EDX">, DwarfRegNum<2>;
-  def EBX : Register<"EBX">, DwarfRegNum<3>;
-  def ESP : Register<"ESP">, DwarfRegNum<4>;
-  def EBP : Register<"EBP">, DwarfRegNum<5>;
-  def ESI : Register<"ESI">, DwarfRegNum<6>;
-  def EDI : Register<"EDI">, DwarfRegNum<7>;
+  def EAX : RegisterGroup<"EAX", [RAX]>, DwarfRegNum<0>;
+  def ECX : RegisterGroup<"ECX", [RCX]>, DwarfRegNum<1>;
+  def EDX : RegisterGroup<"EDX", [RDX]>, DwarfRegNum<2>;
+  def EBX : RegisterGroup<"EBX", [RBX]>, DwarfRegNum<3>;
+  def ESP : RegisterGroup<"ESP", [RSP]>, DwarfRegNum<4>;
+  def EBP : RegisterGroup<"EBP", [RBP]>, DwarfRegNum<5>;
+  def ESI : RegisterGroup<"ESI", [RSI]>, DwarfRegNum<6>;
+  def EDI : RegisterGroup<"EDI", [RDI]>, DwarfRegNum<7>;
   
+  // X86-64 only
+  def R8D  : RegisterGroup<"R8D",  [R8]>,  DwarfRegNum<8>;
+  def R9D  : RegisterGroup<"R9D",  [R9]>,  DwarfRegNum<9>;
+  def R10D : RegisterGroup<"R10D", [R10]>, DwarfRegNum<10>;
+  def R11D : RegisterGroup<"R11D", [R11]>, DwarfRegNum<11>;
+  def R12D : RegisterGroup<"R12D", [R12]>, DwarfRegNum<12>;
+  def R13D : RegisterGroup<"R13D", [R13]>, DwarfRegNum<13>;
+  def R14D : RegisterGroup<"R14D", [R14]>, DwarfRegNum<14>;
+  def R15D : RegisterGroup<"R15D", [R15]>, DwarfRegNum<15>;
+
   // 16-bit registers
-  def AX : RegisterGroup<"AX", [EAX]>, DwarfRegNum<0>;
-  def CX : RegisterGroup<"CX", [ECX]>, DwarfRegNum<1>;
-  def DX : RegisterGroup<"DX", [EDX]>, DwarfRegNum<2>;
-  def BX : RegisterGroup<"BX", [EBX]>, DwarfRegNum<3>;
-  def SP : RegisterGroup<"SP", [ESP]>, DwarfRegNum<4>;
-  def BP : RegisterGroup<"BP", [EBP]>, DwarfRegNum<5>;
-  def SI : RegisterGroup<"SI", [ESI]>, DwarfRegNum<6>;
-  def DI : RegisterGroup<"DI", [EDI]>, DwarfRegNum<7>;
+  def AX : RegisterGroup<"AX", [EAX,RAX]>, DwarfRegNum<0>;
+  def CX : RegisterGroup<"CX", [ECX,RCX]>, DwarfRegNum<1>;
+  def DX : RegisterGroup<"DX", [EDX,RDX]>, DwarfRegNum<2>;
+  def BX : RegisterGroup<"BX", [EBX,RBX]>, DwarfRegNum<3>;
+  def SP : RegisterGroup<"SP", [ESP,RSP]>, DwarfRegNum<4>;
+  def BP : RegisterGroup<"BP", [EBP,RBP]>, DwarfRegNum<5>;
+  def SI : RegisterGroup<"SI", [ESI,RSI]>, DwarfRegNum<6>;
+  def DI : RegisterGroup<"DI", [EDI,RDI]>, DwarfRegNum<7>;
   
+  // X86-64 only
+  def R8W  : RegisterGroup<"R8W",  [R8D,R8]>,   DwarfRegNum<8>;
+  def R9W  : RegisterGroup<"R9W",  [R9D,R9]>,   DwarfRegNum<9>;
+  def R10W : RegisterGroup<"R10W", [R10D,R10]>, DwarfRegNum<10>;
+  def R11W : RegisterGroup<"R11W", [R11D,R11]>, DwarfRegNum<11>;
+  def R12W : RegisterGroup<"R12W", [R12D,R12]>, DwarfRegNum<12>;
+  def R13W : RegisterGroup<"R13W", [R13D,R13]>, DwarfRegNum<13>;
+  def R14W : RegisterGroup<"R14W", [R14D,R14]>, DwarfRegNum<14>;
+  def R15W : RegisterGroup<"R15W", [R15D,R15]>, DwarfRegNum<15>;
+
   // 8-bit registers
-  def AL : RegisterGroup<"AL", [AX,EAX]>, DwarfRegNum<0>;
-  def CL : RegisterGroup<"CL", [CX,ECX]>, DwarfRegNum<1>;
-  def DL : RegisterGroup<"DL", [DX,EDX]>, DwarfRegNum<2>;
-  def BL : RegisterGroup<"BL", [BX,EBX]>, DwarfRegNum<3>;
-  def AH : RegisterGroup<"AH", [AX,EAX]>, DwarfRegNum<0>;
-  def CH : RegisterGroup<"CH", [CX,ECX]>, DwarfRegNum<1>;
-  def DH : RegisterGroup<"DH", [DX,EDX]>, DwarfRegNum<2>;
-  def BH : RegisterGroup<"BH", [BX,EBX]>, DwarfRegNum<3>;
+  // Low registers
+  def AL : RegisterGroup<"AL", [AX,EAX,RAX]>, DwarfRegNum<0>;
+  def CL : RegisterGroup<"CL", [CX,ECX,RCX]>, DwarfRegNum<1>;
+  def DL : RegisterGroup<"DL", [DX,EDX,RDX]>, DwarfRegNum<2>;
+  def BL : RegisterGroup<"BL", [BX,EBX,RBX]>, DwarfRegNum<3>;
+
+  // X86-64 only
+  def SIL : RegisterGroup<"SIL", [SI,ESI,RSI]>, DwarfRegNum<4>;
+  def DIL : RegisterGroup<"DIL", [DI,EDI,RDI]>, DwarfRegNum<5>;
+  def BPL : RegisterGroup<"BPL", [BP,EBP,RBP]>, DwarfRegNum<6>;
+  def SPL : RegisterGroup<"SPL", [SP,ESP,RSP]>, DwarfRegNum<7>;
+  def R8B  : RegisterGroup<"R8B",  [R8W,R8D,R8]>,    DwarfRegNum<8>;
+  def R9B  : RegisterGroup<"R9B",  [R9W,R9D,R9]>,    DwarfRegNum<9>;
+  def R10B : RegisterGroup<"R10B", [R10W,R10D,R10]>, DwarfRegNum<10>;
+  def R11B : RegisterGroup<"R11B", [R11W,R11D,R11]>, DwarfRegNum<11>;
+  def R12B : RegisterGroup<"R12B", [R12W,R12D,R12]>, DwarfRegNum<12>;
+  def R13B : RegisterGroup<"R13B", [R13W,R13D,R13]>, DwarfRegNum<13>;
+  def R14B : RegisterGroup<"R14B", [R14W,R14D,R14]>, DwarfRegNum<14>;
+  def R15B : RegisterGroup<"R15B", [R15W,R15D,R15]>, DwarfRegNum<15>;
+
+  // High registers X86-32 only
+  def AH : RegisterGroup<"AH", [AX,EAX,RAX]>, DwarfRegNum<0>;
+  def CH : RegisterGroup<"CH", [CX,ECX,RCX]>, DwarfRegNum<1>;
+  def DH : RegisterGroup<"DH", [DX,EDX,RDX]>, DwarfRegNum<2>;
+  def BH : RegisterGroup<"BH", [BX,EBX,RBX]>, DwarfRegNum<3>;
 
   // MMX Registers. These are actually aliased to ST0 .. ST7
   def MM0 : Register<"MM0">, DwarfRegNum<29>;
@@ -73,14 +130,24 @@
   def FP6 : Register<"FP6">, DwarfRegNum<-1>; 
 
   // XMM Registers, used by the various SSE instruction set extensions
-  def XMM0: Register<"XMM0">, DwarfRegNum<21>;
-  def XMM1: Register<"XMM1">, DwarfRegNum<22>;
-  def XMM2: Register<"XMM2">, DwarfRegNum<23>;
-  def XMM3: Register<"XMM3">, DwarfRegNum<24>;
-  def XMM4: Register<"XMM4">, DwarfRegNum<25>;
-  def XMM5: Register<"XMM5">, DwarfRegNum<26>;
-  def XMM6: Register<"XMM6">, DwarfRegNum<27>;
-  def XMM7: Register<"XMM7">, DwarfRegNum<28>;
+  def XMM0: Register<"XMM0">, DwarfRegNum<17>;
+  def XMM1: Register<"XMM1">, DwarfRegNum<18>;
+  def XMM2: Register<"XMM2">, DwarfRegNum<19>;
+  def XMM3: Register<"XMM3">, DwarfRegNum<20>;
+  def XMM4: Register<"XMM4">, DwarfRegNum<21>;
+  def XMM5: Register<"XMM5">, DwarfRegNum<22>;
+  def XMM6: Register<"XMM6">, DwarfRegNum<23>;
+  def XMM7: Register<"XMM7">, DwarfRegNum<24>;
+
+  // X86-64 only
+  def XMM8:  Register<"XMM8">,  DwarfRegNum<25>;
+  def XMM9:  Register<"XMM9">,  DwarfRegNum<26>;
+  def XMM10: Register<"XMM10">, DwarfRegNum<27>;
+  def XMM11: Register<"XMM11">, DwarfRegNum<28>;
+  def XMM12: Register<"XMM12">, DwarfRegNum<29>;
+  def XMM13: Register<"XMM13">, DwarfRegNum<30>;
+  def XMM14: Register<"XMM14">, DwarfRegNum<31>;
+  def XMM15: Register<"XMM15">, DwarfRegNum<32>;
 
   // Floating point stack registers
   def ST0 : Register<"ST(0)">, DwarfRegNum<11>;
@@ -99,52 +166,247 @@
 // implicitly defined to be the register allocation order.
 //
 
-// List AL,CL,DL before AH,CH,DH, as X86 processors often suffer from false
-// dependences between upper and lower parts of the register.  BL and BH are
-// last because they are call clobbered. Both Athlon and P4 chips suffer this
-// issue.
-def GR8  : RegisterClass<"X86", [i8],  8, [AL, CL, DL, AH, CH, DH, BL, BH]>;
+// List call-clobbered registers before callee-save registers. RBX, RBP, (and 
+// R12, R13, R14, and R15 for X86-64) are callee-save registers.
+// In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and
+// R8B, ... R15B. 
+// FIXME: Allow AH, CH, DH, BH in 64-mode for non-REX instructions,
+def GR8 : RegisterClass<"X86", [i8],  8,
+                        [AL, CL, DL, BL, AH, CH, DH, BH, SIL, DIL, BPL, SPL,
+                         R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]> {
+  let MethodProtos = [{
+    iterator allocation_order_begin(const MachineFunction &MF) const;
+    iterator allocation_order_end(const MachineFunction &MF) const;
+  }];
+  let MethodBodies = [{
+      // Does the function dedicate RBP / EBP to being a frame ptr?
+      // If so, don't allocate SPL or BPL.
+      static const unsigned X86_GR8_AO_64_fp[] =
+      {X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL,
+       X86::R8B, X86::R9B, X86::R10B, X86::R11B,
+       X86::BL, X86::R14B, X86::R15B, X86::R12B, X86::R13B};
+      // If not, just don't allocate SPL.
+      static const unsigned X86_GR8_AO_64[] =
+      {X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL,
+       X86::R8B, X86::R9B, X86::R10B, X86::R11B,
+       X86::BL, X86::R14B, X86::R15B, X86::R12B, X86::R13B, X86::BPL};
+      // In 32-mode, none of the 8-bit registers aliases EBP or ESP.
+      static const unsigned X86_GR8_AO_32[] =
+      {X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH};
+
+    GR8Class::iterator
+    GR8Class::allocation_order_begin(const MachineFunction &MF) const {
+      const TargetMachine &TM = MF.getTarget();
+      const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
+      if (!Subtarget.is64Bit())
+        return X86_GR8_AO_32;
+      else if (hasFP(MF))
+        return X86_GR8_AO_64_fp;
+      else
+        return X86_GR8_AO_64;
+    }
+
+    GR8Class::iterator
+    GR8Class::allocation_order_end(const MachineFunction &MF) const {
+      const TargetMachine &TM = MF.getTarget();
+      const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
+      if (!Subtarget.is64Bit())
+        return X86_GR8_AO_32 + (sizeof(X86_GR8_AO_32) / sizeof(unsigned));
+      else if (hasFP(MF))
+        return X86_GR8_AO_64_fp + (sizeof(X86_GR8_AO_64_fp) / sizeof(unsigned));
+      else
+        return X86_GR8_AO_64 + (sizeof(X86_GR8_AO_64) / sizeof(unsigned));
+    }
+  }];
+}
+
 
-def GR16 : RegisterClass<"X86", [i16], 16, [AX, CX, DX, SI, DI, BX, BP, SP]> {
+def GR16 : RegisterClass<"X86", [i16], 16,
+                         [AX, CX, DX, SI, DI, BX, BP, SP,
+                          R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]> {
   let MethodProtos = [{
+    iterator allocation_order_begin(const MachineFunction &MF) const;
     iterator allocation_order_end(const MachineFunction &MF) const;
   }];
   let MethodBodies = [{
+      // Does the function dedicate RBP / EBP to being a frame ptr?
+      // If so, don't allocate SP or BP.
+      static const unsigned X86_GR16_AO_64_fp[] =
+      {X86::AX, X86::CX, X86::DX, X86::SI, X86::DI,
+       X86::R8W, X86::R9W, X86::R10W, X86::R11W,
+       X86::BX, X86::R14W, X86::R15W, X86::R12W, X86::R13W};
+      static const unsigned X86_GR16_AO_32_fp[] =
+      {X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX};
+      // If not, just don't allocate SPL.
+      static const unsigned X86_GR16_AO_64[] =
+      {X86::AX, X86::CX, X86::DX, X86::SI, X86::DI,
+       X86::R8W, X86::R9W, X86::R10W, X86::R11W,
+       X86::BX, X86::R14W, X86::R15W, X86::R12W, X86::R13W, X86::BP};
+      static const unsigned X86_GR16_AO_32[] =
+      {X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP};
+
+    GR16Class::iterator
+    GR16Class::allocation_order_begin(const MachineFunction &MF) const {
+      const TargetMachine &TM = MF.getTarget();
+      const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
+      if (Subtarget.is64Bit()) {
+        if (hasFP(MF))
+          return X86_GR16_AO_64_fp;
+        else
+          return X86_GR16_AO_64;
+      } else {
+        if (hasFP(MF))
+          return X86_GR16_AO_32_fp;
+        else
+          return X86_GR16_AO_32;
+      }
+    }
+
     GR16Class::iterator
     GR16Class::allocation_order_end(const MachineFunction &MF) const {
-      if (hasFP(MF))     // Does the function dedicate EBP to being a frame ptr?
-        return end()-2;  // If so, don't allocate SP or BP
-      else
-        return end()-1;  // If not, just don't allocate SP
+      const TargetMachine &TM = MF.getTarget();
+      const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
+      if (Subtarget.is64Bit()) {
+        if (hasFP(MF))
+          return X86_GR16_AO_64_fp+(sizeof(X86_GR16_AO_64_fp)/sizeof(unsigned));
+        else
+          return X86_GR16_AO_64 + (sizeof(X86_GR16_AO_64) / sizeof(unsigned));
+      } else {
+        if (hasFP(MF))
+          return X86_GR16_AO_32_fp+(sizeof(X86_GR16_AO_32_fp)/sizeof(unsigned));
+        else
+          return X86_GR16_AO_32 + (sizeof(X86_GR16_AO_32) / sizeof(unsigned));
+      }
     }
   }];
 }
 
+
 def GR32 : RegisterClass<"X86", [i32], 32, 
-                         [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP]> {
+                         [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP,
+                          R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D]> {
   let MethodProtos = [{
+    iterator allocation_order_begin(const MachineFunction &MF) const;
     iterator allocation_order_end(const MachineFunction &MF) const;
   }];
   let MethodBodies = [{
+      // Does the function dedicate RBP / EBP to being a frame ptr?
+      // If so, don't allocate ESP or EBP.
+      static const unsigned X86_GR32_AO_64_fp[] =
+      {X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI,
+       X86::R8D, X86::R9D, X86::R10D, X86::R11D,
+       X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D};
+      static const unsigned X86_GR32_AO_32_fp[] =
+      {X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX};
+      // If not, just don't allocate SPL.
+      static const unsigned X86_GR32_AO_64[] =
+      {X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI,
+       X86::R8D, X86::R9D, X86::R10D, X86::R11D,
+       X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::EBP};
+      static const unsigned X86_GR32_AO_32[] =
+      {X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP};
+
+    GR32Class::iterator
+    GR32Class::allocation_order_begin(const MachineFunction &MF) const {
+      const TargetMachine &TM = MF.getTarget();
+      const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
+      if (Subtarget.is64Bit()) {
+        if (hasFP(MF))
+          return X86_GR32_AO_64_fp;
+        else
+          return X86_GR32_AO_64;
+      } else {
+        if (hasFP(MF))
+          return X86_GR32_AO_32_fp;
+        else
+          return X86_GR32_AO_32;
+      }
+    }
+
     GR32Class::iterator
     GR32Class::allocation_order_end(const MachineFunction &MF) const {
-      if (hasFP(MF))     // Does the function dedicate EBP to being a frame ptr?
-        return end()-2;  // If so, don't allocate ESP or EBP
+      const TargetMachine &TM = MF.getTarget();
+      const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
+      if (Subtarget.is64Bit()) {
+        if (hasFP(MF))
+          return X86_GR32_AO_64_fp+(sizeof(X86_GR32_AO_64_fp)/sizeof(unsigned));
+        else
+          return X86_GR32_AO_64 + (sizeof(X86_GR32_AO_64) / sizeof(unsigned));
+      } else {
+        if (hasFP(MF))
+          return X86_GR32_AO_32_fp+(sizeof(X86_GR32_AO_32_fp)/sizeof(unsigned));
+        else
+          return X86_GR32_AO_32 + (sizeof(X86_GR32_AO_32) / sizeof(unsigned));
+      }
+    }
+  }];
+}
+
+
+def GR64 : RegisterClass<"X86", [i64], 64, 
+                         [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
+                          RBX, R14, R15, R12, R13, RBP, RSP]> {
+  let MethodProtos = [{
+    iterator allocation_order_end(const MachineFunction &MF) const;
+  }];
+  let MethodBodies = [{
+    GR64Class::iterator
+    GR64Class::allocation_order_end(const MachineFunction &MF) const {
+      if (hasFP(MF))     // Does the function dedicate RBP to being a frame ptr?
+        return end()-2;  // If so, don't allocate RSP or RBP
       else
-        return end()-1;  // If not, just don't allocate ESP
+        return end()-1;  // If not, just don't allocate RSP
     }
   }];
 }
 
+
 // GR16, GR32 subclasses which contain registers that have R8 sub-registers.
+// These should only be used for 32-bit mode.
 def GR16_ : RegisterClass<"X86", [i16], 16, [AX, CX, DX, BX]>;
 def GR32_ : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, EBX]>;
 
 // Scalar SSE2 floating point registers.
 def FR32 : RegisterClass<"X86", [f32], 32,
-                         [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
+                         [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
+                          XMM8, XMM9, XMM10, XMM11,
+                          XMM12, XMM13, XMM14, XMM15]> {
+  let MethodProtos = [{
+    iterator allocation_order_end(const MachineFunction &MF) const;
+  }];
+  let MethodBodies = [{
+    FR32Class::iterator
+    FR32Class::allocation_order_end(const MachineFunction &MF) const {
+      const TargetMachine &TM = MF.getTarget();
+      const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
+      if (!Subtarget.is64Bit())
+        return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
+      else
+        return end();
+    }
+  }];
+}
+
 def FR64 : RegisterClass<"X86", [f64], 64,
-                         [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
+                         [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
+                          XMM8, XMM9, XMM10, XMM11,
+                          XMM12, XMM13, XMM14, XMM15]> {
+  let MethodProtos = [{
+    iterator allocation_order_end(const MachineFunction &MF) const;
+  }];
+  let MethodBodies = [{
+    FR64Class::iterator
+    FR64Class::allocation_order_end(const MachineFunction &MF) const {
+      const TargetMachine &TM = MF.getTarget();
+      const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
+      if (!Subtarget.is64Bit())
+        return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
+      else
+        return end();
+    }
+  }];
+}
+
 
 // FIXME: This sets up the floating point register files as though they are f64
 // values, though they really are f80 values.  This will cause us to spill
@@ -174,4 +436,21 @@
 def VR64  : RegisterClass<"X86", [v8i8, v4i16, v2i32], 64,
                           [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7]>;
 def VR128 : RegisterClass<"X86", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],128,
-                         [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
+                          [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
+                           XMM8, XMM9, XMM10, XMM11,
+                           XMM12, XMM13, XMM14, XMM15]> {
+  let MethodProtos = [{
+    iterator allocation_order_end(const MachineFunction &MF) const;
+  }];
+  let MethodBodies = [{
+    VR128Class::iterator
+    VR128Class::allocation_order_end(const MachineFunction &MF) const {
+      const TargetMachine &TM = MF.getTarget();
+      const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
+      if (!Subtarget.is64Bit())
+        return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
+      else
+        return end();
+    }
+  }];
+}


Index: llvm/lib/Target/X86/X86Subtarget.cpp
diff -u llvm/lib/Target/X86/X86Subtarget.cpp:1.30 llvm/lib/Target/X86/X86Subtarget.cpp:1.31
--- llvm/lib/Target/X86/X86Subtarget.cpp:1.30	Thu Sep  7 17:29:41 2006
+++ llvm/lib/Target/X86/X86Subtarget.cpp	Fri Sep  8 01:48:29 2006
@@ -12,9 +12,10 @@
 //===----------------------------------------------------------------------===//
 
 #include "X86Subtarget.h"
+#include "X86GenSubtarget.inc"
 #include "llvm/Module.h"
 #include "llvm/Support/CommandLine.h"
-#include "X86GenSubtarget.inc"
+#include <iostream>
 using namespace llvm;
 
 cl::opt<X86Subtarget::AsmWriterFlavorTy>
@@ -29,7 +30,18 @@
 /// specified arguments.  If we can't run cpuid on the host, return true.
 static bool GetCpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
                             unsigned *rECX, unsigned *rEDX) {
-#if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
+#if defined(__x86_64__)
+  asm ("pushq\t%%rbx\n\t"
+       "cpuid\n\t"
+       "movl\t%%ebx, %%esi\n\t"
+       "popq\t%%rbx"
+       : "=a" (*rEAX),
+         "=S" (*rEBX),
+         "=c" (*rECX),
+         "=d" (*rEDX)
+       :  "a" (value));
+  return false;
+#elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
 #if defined(__GNUC__)
   asm ("pushl\t%%ebx\n\t"
        "cpuid\n\t"
@@ -99,8 +111,8 @@
         case 9:
         case 13: return "pentium-m";
         case 14: return "yonah";
-        default:
-          return (Model > 14) ? "yonah" : "i686";
+        case 15: return "core2";
+        default: return "i686";
         }
       case 15: {
         switch (Model) {
@@ -154,14 +166,16 @@
   }
 }
 
-X86Subtarget::X86Subtarget(const Module &M, const std::string &FS) {
-  stackAlignment = 8;
-  // FIXME: this is a known good value for Yonah. Not sure about others.
-  MinRepStrSizeThreshold = 128;
-  X86SSELevel = NoMMXSSE;
-  X863DNowLevel = NoThreeDNow;
-  AsmFlavor = AsmWriterFlavor;
-  Is64Bit = false;
+X86Subtarget::X86Subtarget(const Module &M, const std::string &FS, bool is64Bit)
+  :  AsmFlavor(AsmWriterFlavor)
+  , X86SSELevel(NoMMXSSE)
+  , X863DNowLevel(NoThreeDNow)
+  , HasX86_64(false)
+  , stackAlignment(8)
+  // FIXME: this is a known good value for Yonah. How about others?
+  , MinRepStrSizeThreshold(128)
+  , Is64Bit(is64Bit)
+  , TargetType(isELF) { // Default to ELF unless otherwise specified.
 
   // Determine default and user specified characteristics
   std::string CPU = GetCurrentX86CPU();
@@ -169,9 +183,12 @@
   // Parse features string.
   ParseSubtargetFeatures(FS, CPU);
 
-  // Default to ELF unless otherwise specified.
-  TargetType = isELF;
-  
+  if (Is64Bit && !HasX86_64) {
+      std::cerr << "Warning: Generation of 64-bit code for a 32-bit processor "
+                   "requested.\n";
+      HasX86_64 = true;
+  }
+
   // Set the boolean corresponding to the current target triple, or the default
   // if one cannot be determined, to true.
   const std::string& TT = M.getTargetTriple();


Index: llvm/lib/Target/X86/X86Subtarget.h
diff -u llvm/lib/Target/X86/X86Subtarget.h:1.15 llvm/lib/Target/X86/X86Subtarget.h:1.16
--- llvm/lib/Target/X86/X86Subtarget.h:1.15	Thu Sep  7 17:32:28 2006
+++ llvm/lib/Target/X86/X86Subtarget.h	Fri Sep  8 01:48:29 2006
@@ -44,9 +44,9 @@
 
   /// X863DNowLevel - 3DNow or 3DNow Athlon, or none supported.
   X863DNowEnum X863DNowLevel;
-  
-  /// Is64Bit - True if the processor supports Em64T.
-  bool Is64Bit;
+
+  /// HasX86_64 - True if the processor supports X86-64 instructions.
+  bool HasX86_64;
 
   /// stackAlignment - The minimum alignment known to hold of the stack frame on
   /// entry to the function and which must be maintained by every function.
@@ -55,6 +55,11 @@
   /// Min. memset / memcpy size that is turned into rep/movs, rep/stos ops.
   unsigned MinRepStrSizeThreshold;
 
+private:
+  /// Is64Bit - True if the processor supports 64-bit instructions and module
+  /// pointer size is 64 bit.
+  bool Is64Bit;
+
 public:
   enum {
     isELF, isCygwin, isDarwin, isWindows
@@ -63,7 +68,7 @@
   /// This constructor initializes the data members to match that
   /// of the specified module.
   ///
-  X86Subtarget(const Module &M, const std::string &FS);
+  X86Subtarget(const Module &M, const std::string &FS, bool is64Bit);
 
   /// getStackAlignment - Returns the minimum alignment known to hold of the
   /// stack frame on entry to the function and which must be maintained by every


Index: llvm/lib/Target/X86/X86TargetAsmInfo.cpp
diff -u llvm/lib/Target/X86/X86TargetAsmInfo.cpp:1.1 llvm/lib/Target/X86/X86TargetAsmInfo.cpp:1.2
--- llvm/lib/Target/X86/X86TargetAsmInfo.cpp:1.1	Thu Sep  7 17:05:02 2006
+++ llvm/lib/Target/X86/X86TargetAsmInfo.cpp	Fri Sep  8 01:48:29 2006
@@ -26,13 +26,16 @@
   case X86Subtarget::isDarwin:
     AlignmentIsInBytes = false;
     GlobalPrefix = "_";
-    Data64bitsDirective = 0;       // we can't emit a 64-bit unit
+    if (!Subtarget->is64Bit())
+      Data64bitsDirective = 0;       // we can't emit a 64-bit unit
     ZeroDirective = "\t.space\t";  // ".space N" emits N zeros.
     PrivateGlobalPrefix = "L";     // Marker for constant pool idxs
     ConstantPoolSection = "\t.const\n";
     JumpTableDataSection = "\t.const\n"; // FIXME: depends on PIC mode
     FourByteConstantSection = "\t.literal4\n";
     EightByteConstantSection = "\t.literal8\n";
+    if (Subtarget->is64Bit())
+      SixteenByteConstantSection = "\t.literal16\n";
     LCOMMDirective = "\t.lcomm\t";
     COMMDirectiveTakesAlignment = false;
     HasDotTypeDotSizeDirective = false;


Index: llvm/lib/Target/X86/X86TargetMachine.cpp
diff -u llvm/lib/Target/X86/X86TargetMachine.cpp:1.126 llvm/lib/Target/X86/X86TargetMachine.cpp:1.127
--- llvm/lib/Target/X86/X86TargetMachine.cpp:1.126	Thu Sep  7 18:39:26 2006
+++ llvm/lib/Target/X86/X86TargetMachine.cpp	Fri Sep  8 01:48:29 2006
@@ -33,22 +33,31 @@
 
 namespace {
   // Register the target.
-  RegisterTarget<X86TargetMachine> X("x86", "  IA-32 (Pentium and above)");
+  RegisterTarget<X86_32TargetMachine>
+  X("x86",    "  32-bit X86: Pentium-Pro and above");
+  RegisterTarget<X86_64TargetMachine>
+  Y("x86-64", "  64-bit X86: EM64T and AMD64");
 }
 
 const TargetAsmInfo *X86TargetMachine::createTargetAsmInfo() const {
   return new X86TargetAsmInfo(*this);
 }
 
-unsigned X86TargetMachine::getJITMatchQuality() {
+unsigned X86_32TargetMachine::getJITMatchQuality() {
 #if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
   return 10;
-#else
+#endif
   return 0;
+}
+
+unsigned X86_64TargetMachine::getJITMatchQuality() {
+#if defined(__x86_64__)
+  return 10;
 #endif
+  return 0;
 }
 
-unsigned X86TargetMachine::getModuleMatchQuality(const Module &M) {
+unsigned X86_32TargetMachine::getModuleMatchQuality(const Module &M) {
   // We strongly match "i[3-9]86-*".
   std::string TT = M.getTargetTriple();
   if (TT.size() >= 5 && TT[0] == 'i' && TT[2] == '8' && TT[3] == '6' &&
@@ -65,18 +74,55 @@
   return getJITMatchQuality()/2;
 }
 
+unsigned X86_64TargetMachine::getModuleMatchQuality(const Module &M) {
+  // We strongly match "x86_64-*".
+  std::string TT = M.getTargetTriple();
+  if (TT.size() >= 7 && TT[0] == 'x' && TT[1] == '8' && TT[2] == '6' &&
+      TT[3] == '_' && TT[4] == '6' && TT[5] == '4' && TT[6] == '-')
+    return 20;
+
+  if (M.getEndianness()  == Module::LittleEndian &&
+      M.getPointerSize() == Module::Pointer64)
+    return 10;                                   // Weak match
+  else if (M.getEndianness() != Module::AnyEndianness ||
+           M.getPointerSize() != Module::AnyPointerSize)
+    return 0;                                    // Match for some other target
+
+  return getJITMatchQuality()/2;
+}
+
+X86_32TargetMachine::X86_32TargetMachine(const Module &M, const std::string &FS) 
+  : X86TargetMachine(M, FS, false) {
+}
+
+
+X86_64TargetMachine::X86_64TargetMachine(const Module &M, const std::string &FS)
+  : X86TargetMachine(M, FS, true) {
+}
+
 /// X86TargetMachine ctor - Create an ILP32 architecture model
 ///
-X86TargetMachine::X86TargetMachine(const Module &M, const std::string &FS)
-  : Subtarget(M, FS), DataLayout("e-p:32:32-d:32-l:32"),
+X86TargetMachine::X86TargetMachine(const Module &M, const std::string &FS, bool is64Bit)
+  : Subtarget(M, FS, is64Bit),
+    DataLayout(Subtarget.is64Bit() ?
+               std::string("e-p:64:64-d:32-l:32") :
+               std::string("e-p:32:32-d:32-l:32")),
     FrameInfo(TargetFrameInfo::StackGrowsDown,
-              Subtarget.getStackAlignment(), -4),
+              Subtarget.getStackAlignment(), Subtarget.is64Bit() ? -8 : -4),
     InstrInfo(*this), JITInfo(*this), TLInfo(*this) {
   if (getRelocationModel() == Reloc::Default)
     if (Subtarget.isTargetDarwin())
       setRelocationModel(Reloc::DynamicNoPIC);
     else
       setRelocationModel(Reloc::PIC_);
+  if (Subtarget.is64Bit()) {
+    // No DynamicNoPIC support under X86-64.
+    if (getRelocationModel() == Reloc::DynamicNoPIC)
+      setRelocationModel(Reloc::PIC_);
+    // Default X86-64 code model is small.
+    if (getCodeModel() == CodeModel::Default)
+      setCodeModel(CodeModel::Small);
+  }
 }
 
 //===----------------------------------------------------------------------===//


Index: llvm/lib/Target/X86/X86TargetMachine.h
diff -u llvm/lib/Target/X86/X86TargetMachine.h:1.40 llvm/lib/Target/X86/X86TargetMachine.h:1.41
--- llvm/lib/Target/X86/X86TargetMachine.h:1.40	Thu Sep  7 18:39:26 2006
+++ llvm/lib/Target/X86/X86TargetMachine.h	Fri Sep  8 01:48:29 2006
@@ -37,7 +37,7 @@
   virtual const TargetAsmInfo *createTargetAsmInfo() const;
   
 public:
-  X86TargetMachine(const Module &M, const std::string &FS);
+  X86TargetMachine(const Module &M, const std::string &FS, bool is64Bit);
 
   virtual const X86InstrInfo     *getInstrInfo() const { return &InstrInfo; }
   virtual const TargetFrameInfo  *getFrameInfo() const { return &FrameInfo; }
@@ -54,6 +54,7 @@
   static unsigned getModuleMatchQuality(const Module &M);
   static unsigned getJITMatchQuality();
   
+  
   // Set up the pass pipeline.
   virtual bool addInstSelector(FunctionPassManager &PM, bool Fast);  
   virtual bool addPostRegAlloc(FunctionPassManager &PM, bool Fast);
@@ -64,6 +65,27 @@
   virtual bool addCodeEmitter(FunctionPassManager &PM, bool Fast,
                               MachineCodeEmitter &MCE);
 };
+
+/// X86_32TargetMachine - X86 32-bit target machine.
+///
+class X86_32TargetMachine : public X86TargetMachine {
+public:
+  X86_32TargetMachine(const Module &M, const std::string &FS);
+  
+  static unsigned getJITMatchQuality();
+  static unsigned getModuleMatchQuality(const Module &M);
+};
+
+/// X86_64TargetMachine - X86 64-bit target machine.
+///
+class X86_64TargetMachine : public X86TargetMachine {
+public:
+  X86_64TargetMachine(const Module &M, const std::string &FS);
+  
+  static unsigned getJITMatchQuality();
+  static unsigned getModuleMatchQuality(const Module &M);
+};
+
 } // End llvm namespace
 
 #endif





From evan.cheng at apple.com  Fri Sep  8 01:57:09 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 8 Sep 2006 01:57:09 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrX86-64.td
Message-ID: <200609080657.k886v9au021095@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86InstrX86-64.td updated: 1.1 -> 1.2
---
Log message:

Remove TEST64mr. It's same as TEST64rm since and is commutative.

---
Diffs of the changes:  (+0 -3)

 X86InstrX86-64.td |    3 ---
 1 files changed, 3 deletions(-)


Index: llvm/lib/Target/X86/X86InstrX86-64.td
diff -u llvm/lib/Target/X86/X86InstrX86-64.td:1.1 llvm/lib/Target/X86/X86InstrX86-64.td:1.2
--- llvm/lib/Target/X86/X86InstrX86-64.td:1.1	Fri Sep  8 01:48:29 2006
+++ llvm/lib/Target/X86/X86InstrX86-64.td	Fri Sep  8 01:56:55 2006
@@ -709,9 +709,6 @@
 def TEST64rr : RI<0x85, MRMDestReg, (ops GR64:$src1, GR64:$src2),
                   "test{q} {$src2, $src1|$src1, $src2}",
                   [(X86cmp (and GR64:$src1, GR64:$src2), 0)]>;
-def TEST64mr : RI<0x85, MRMDestMem, (ops i64mem:$src1, GR64:$src2),
-                  "test{q} {$src2, $src1|$src1, $src2}",
-                  [/*(X86cmp (and (loadi64 addr:$src1), GR64:$src2), 0)*/]>;
 def TEST64rm : RI<0x85, MRMSrcMem, (ops GR64:$src1, i64mem:$src2),
                   "test{q} {$src2, $src1|$src1, $src2}",
                   [/*(X86cmp (and GR64:$src1, (loadi64 addr:$src2)), 0)*/]>;





From evan.cheng at apple.com  Fri Sep  8 02:24:34 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 8 Sep 2006 02:24:34 -0500
Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/X86/test-not-cmp.ll
Message-ID: <200609080724.k887OYuE029897@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CodeGen/X86:

test-not-cmp.ll added (r1.1)
---
Log message:

New test case.

---
Diffs of the changes:  (+14 -0)

 test-not-cmp.ll |   14 ++++++++++++++
 1 files changed, 14 insertions(+)


Index: llvm/test/Regression/CodeGen/X86/test-not-cmp.ll
diff -c /dev/null llvm/test/Regression/CodeGen/X86/test-not-cmp.ll:1.1
*** /dev/null	Fri Sep  8 02:24:30 2006
--- llvm/test/Regression/CodeGen/X86/test-not-cmp.ll	Fri Sep  8 02:24:20 2006
***************
*** 0 ****
--- 1,14 ----
+ ; RUN: llvm-as < %s | llc -march=x86
+ ; RUN: llvm-as < %s | llc -march=x86 | grep test
+ 
+ int %test(int %X, int* %y) {
+ 	%tmp = load int* %y
+ 	%tmp = seteq int %tmp, 0
+ 	br bool %tmp, label %ReturnBlock, label %cond_true
+ 
+ cond_true:
+ 	ret int 1
+ 
+ ReturnBlock:
+ 	ret int 0
+ }





From evan.cheng at apple.com  Fri Sep  8 02:26:53 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 8 Sep 2006 02:26:53 -0500
Subject: [llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp
Message-ID: <200609080726.k887QrIC029947@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

DAGISelEmitter.cpp updated: 1.253 -> 1.254
---
Log message:

Generated isel should favors explicit constant operand (+2) over an operand with a predicate (+1).

---
Diffs of the changes:  (+4 -5)

 DAGISelEmitter.cpp |    9 ++++-----
 1 files changed, 4 insertions(+), 5 deletions(-)


Index: llvm/utils/TableGen/DAGISelEmitter.cpp
diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.253 llvm/utils/TableGen/DAGISelEmitter.cpp:1.254
--- llvm/utils/TableGen/DAGISelEmitter.cpp:1.253	Sun Aug 27 08:16:24 2006
+++ llvm/utils/TableGen/DAGISelEmitter.cpp	Fri Sep  8 02:26:39 2006
@@ -768,7 +768,6 @@
       if (OperandNode->isSubClassOf("RegisterClass")) {
         const CodeGenRegisterClass &RC = 
           ISE.getTargetInfo().getRegisterClass(OperandNode);
-        //VT = RC.getValueTypeNum(0);
         MadeChange |=getChild(i)->UpdateNodeType(ConvertVTs(RC.getValueTypes()),
                                                  TP);
       } else if (OperandNode->isSubClassOf("Operand")) {
@@ -1944,11 +1943,11 @@
           P->getExtTypeNum(0) == MVT::Flag ||
           P->getExtTypeNum(0) == MVT::iPTR) && 
          "Not a valid pattern node to size!");
-  unsigned Size = 2;  // The node itself.
+  unsigned Size = 3;  // The node itself.
   // If the root node is a ConstantSDNode, increases its size.
   // e.g. (set R32:$dst, 0).
   if (P->isLeaf() && dynamic_cast<IntInit*>(P->getLeafValue()))
-    Size++;
+    Size += 2;
 
   // FIXME: This is a hack to statically increase the priority of patterns
   // which maps a sub-dag to a complex pattern. e.g. favors LEA over ADD.
@@ -1957,7 +1956,7 @@
   // calculate the complexity of all patterns a dag can potentially map to.
   const ComplexPattern *AM = NodeGetComplexPattern(P, ISE);
   if (AM)
-    Size += AM->getNumOperands() * 2;
+    Size += AM->getNumOperands() * 3;
 
   // If this node has some predicate function that must match, it adds to the
   // complexity of this node.
@@ -1971,7 +1970,7 @@
       Size += getPatternSize(Child, ISE);
     else if (Child->isLeaf()) {
       if (dynamic_cast<IntInit*>(Child->getLeafValue())) 
-        Size += 3;  // Matches a ConstantSDNode (+2) and a specific value (+1).
+        Size += 5;  // Matches a ConstantSDNode (+3) and a specific value (+2).
       else if (NodeIsComplexPattern(Child))
         Size += getPatternSize(Child, ISE);
       else if (!Child->getPredicateFn().empty())





From jlaskey at apple.com  Fri Sep  8 06:27:15 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Fri, 8 Sep 2006 06:27:15 -0500
Subject: [llvm-commits] CVS: nightlytest-serverside/ProgramResults.php
Message-ID: <200609081127.k88BRFY8031840@zion.cs.uiuc.edu>



Changes in directory nightlytest-serverside:

ProgramResults.php updated: 1.34 -> 1.35
---
Log message:

Adding reasons to newly passing/failing step #1.


---
Diffs of the changes:  (+31 -17)

 ProgramResults.php |   48 +++++++++++++++++++++++++++++++-----------------
 1 files changed, 31 insertions(+), 17 deletions(-)


Index: nightlytest-serverside/ProgramResults.php
diff -u nightlytest-serverside/ProgramResults.php:1.34 nightlytest-serverside/ProgramResults.php:1.35
--- nightlytest-serverside/ProgramResults.php:1.34	Fri Sep  1 05:53:35 2006
+++ nightlytest-serverside/ProgramResults.php	Fri Sep  8 06:26:54 2006
@@ -387,6 +387,33 @@
   }
 }
 
+
+/*
+ * Return reason why a llvm test failed.
+ */
+function getFailReasons($test_result) {
+  $result = "";
+  $phases = split(", ", $test_result);
+  
+  for ($i = 0; $i < count($phases); $i++) {
+    $phase = $phases[$i];
+    if (strpos($phase, "*") !== false) {
+      list($tool, $tool_result) = split(": ", $phase);
+      if (strcmp($result, "") != 0) {
+        $result .= ", ";
+      }
+      $result .= $tool;
+    }
+  }
+  
+  if (strcmp($result, "") != 0) {
+    $result = " [" . $result . "]";
+  }
+  
+  return $result;
+}
+ 
+ 
 /*
  * Get failing tests
  *
@@ -408,21 +435,8 @@
     while($row = mysql_fetch_array($program_query)) {
       $test_result = $row['result'];
       if (!isTestPass($test_result)) {
-        $failing_tools = "";
-        $phases = split(", ", $test_result);
-        
-        for ($i = 0; $i < count($phases); $i++) {
-          $phase = $phases[$i];
-          if (!isTestPass($phase)) {
-            list($tool, $tool_result) = split(": ", $phase);
-            if (strcmp($failing_tools, "") != 0) {
-              $failing_tools .= ", ";
-            }
-            $failing_tools .= $tool;
-          }
-        }
-        
-        $result .= "{$row['program']} [{$failing_tools}]<br>\n";
+        $reasons = getFailReasons($test_result);        
+        $result .= "{$row['program']}{$reasons}<br>\n";
       }
     }
     mysql_free_result($program_query);
@@ -467,7 +481,7 @@
   $query = "SELECT * FROM $table WHERE night=$id";
   $program_query = mysql_query($query) or die (mysql_error());
   while ($row = mysql_fetch_array($program_query)) {
-    $test_hash[$row['program']]=1;
+    $test_hash[$row['program']] = $row['result'];
   }
   mysql_free_result($program_query);
   return $test_hash;
@@ -575,7 +589,7 @@
   $program_query = mysql_query($query) or die (mysql_error());
   while ($row = mysql_fetch_array($program_query)) {
     if (!isTestPass($row['result'])) {
-      $test_hash[$row['program']]=1;
+      $test_hash[$row['program']] = $row['result'];
     }
   }
   mysql_free_result($program_query);





From jlaskey at apple.com  Fri Sep  8 06:32:40 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Fri, 8 Sep 2006 06:32:40 -0500
Subject: [llvm-commits] CVS: nightlytest-serverside/ProgramResults.php
Message-ID: <200609081132.k88BWe8V002109@zion.cs.uiuc.edu>



Changes in directory nightlytest-serverside:

ProgramResults.php updated: 1.35 -> 1.36
---
Log message:

Adding reasons to newly passing/failing step #2

---
Diffs of the changes:  (+1 -1)

 ProgramResults.php |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: nightlytest-serverside/ProgramResults.php
diff -u nightlytest-serverside/ProgramResults.php:1.35 nightlytest-serverside/ProgramResults.php:1.36
--- nightlytest-serverside/ProgramResults.php:1.35	Fri Sep  8 06:26:54 2006
+++ nightlytest-serverside/ProgramResults.php	Fri Sep  8 06:32:25 2006
@@ -407,7 +407,7 @@
   }
   
   if (strcmp($result, "") != 0) {
-    $result = " [" . $result . "]";
+    $result = " <i>[" . $result . "]</i>";
   }
   
   return $result;





From jlaskey at apple.com  Fri Sep  8 06:36:25 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Fri, 8 Sep 2006 06:36:25 -0500
Subject: [llvm-commits] CVS: nightlytest-serverside/ProgramResults.php
Message-ID: <200609081136.k88BaPdx004162@zion.cs.uiuc.edu>



Changes in directory nightlytest-serverside:

ProgramResults.php updated: 1.36 -> 1.37
---
Log message:

Adding reasons to newly passing/failing step #3

---
Diffs of the changes:  (+1 -1)

 ProgramResults.php |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: nightlytest-serverside/ProgramResults.php
diff -u nightlytest-serverside/ProgramResults.php:1.36 nightlytest-serverside/ProgramResults.php:1.37
--- nightlytest-serverside/ProgramResults.php:1.36	Fri Sep  8 06:32:25 2006
+++ nightlytest-serverside/ProgramResults.php	Fri Sep  8 06:36:10 2006
@@ -407,7 +407,7 @@
   }
   
   if (strcmp($result, "") != 0) {
-    $result = " <i>[" . $result . "]</i>";
+    $result = " <font color=\"grey\">[" . $result . "]</font>";
   }
   
   return $result;





From jlaskey at apple.com  Fri Sep  8 06:42:14 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Fri, 8 Sep 2006 06:42:14 -0500
Subject: [llvm-commits] CVS: nightlytest-serverside/ProgramResults.php
Message-ID: <200609081142.k88BgEHJ006166@zion.cs.uiuc.edu>



Changes in directory nightlytest-serverside:

ProgramResults.php updated: 1.37 -> 1.38
---
Log message:

Adding reasons to newly passing/failing step #4

---
Diffs of the changes:  (+3 -2)

 ProgramResults.php |    5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)


Index: nightlytest-serverside/ProgramResults.php
diff -u nightlytest-serverside/ProgramResults.php:1.37 nightlytest-serverside/ProgramResults.php:1.38
--- nightlytest-serverside/ProgramResults.php:1.37	Fri Sep  8 06:36:10 2006
+++ nightlytest-serverside/ProgramResults.php	Fri Sep  8 06:41:58 2006
@@ -599,7 +599,7 @@
 /*
  * Get list of newly passing tests
  *
- * Returns a list of tests for a given night that were excluded from the
+ * Returns a list of tests for a given night that were included in the
  * hash and now pass.
  */
 function getPassingTests($id, $table, $test_hash){
@@ -609,7 +609,8 @@
   while ($row = mysql_fetch_array($program_query)) {
     $test_key = $row['program'];
     if (isset($test_hash[$test_key]) && isTestPass($row['result'])) {
-      $result .= $test_key . "<br>\n";
+      $reasons = getFailReasons($test_hash[$test_key]);
+      $result .= "{$test_key}{$reasons)<br>\n";
     }
   }
   mysql_free_result($program_query);





From jlaskey at apple.com  Fri Sep  8 06:45:00 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Fri, 8 Sep 2006 06:45:00 -0500
Subject: [llvm-commits] CVS: nightlytest-serverside/ProgramResults.php
Message-ID: <200609081145.k88Bj0s9007353@zion.cs.uiuc.edu>



Changes in directory nightlytest-serverside:

ProgramResults.php updated: 1.38 -> 1.39
---
Log message:

Adding reasons to newly passing/failing step #5

---
Diffs of the changes:  (+1 -1)

 ProgramResults.php |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: nightlytest-serverside/ProgramResults.php
diff -u nightlytest-serverside/ProgramResults.php:1.38 nightlytest-serverside/ProgramResults.php:1.39
--- nightlytest-serverside/ProgramResults.php:1.38	Fri Sep  8 06:41:58 2006
+++ nightlytest-serverside/ProgramResults.php	Fri Sep  8 06:44:44 2006
@@ -610,7 +610,7 @@
     $test_key = $row['program'];
     if (isset($test_hash[$test_key]) && isTestPass($row['result'])) {
       $reasons = getFailReasons($test_hash[$test_key]);
-      $result .= "{$test_key}{$reasons)<br>\n";
+      $result .= "{$test_key}{$reasons}<br>\n";
     }
   }
   mysql_free_result($program_query);





From rafael.espindola at gmail.com  Fri Sep  8 07:47:20 2006
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Fri, 8 Sep 2006 07:47:20 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.td
Message-ID: <200609081247.k88ClKfi012786@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/ARM:

ARMInstrInfo.td updated: 1.22 -> 1.23
---
Log message:

implement unconditional branches
fix select.ll



---
Diffs of the changes:  (+4 -0)

 ARMInstrInfo.td |    4 ++++
 1 files changed, 4 insertions(+)


Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.22 llvm/lib/Target/ARM/ARMInstrInfo.td:1.23
--- llvm/lib/Target/ARM/ARMInstrInfo.td:1.22	Wed Sep  6 13:03:12 2006
+++ llvm/lib/Target/ARM/ARMInstrInfo.td	Fri Sep  8 07:47:03 2006
@@ -127,6 +127,10 @@
 		         "b$cc $dst",
 		         [(armbr bb:$dst, imm:$cc)]>;
 
+def b      : InstARM<(ops brtarget:$dst),
+		         "b $dst",
+		         [(br bb:$dst)]>;
+
 def cmp      : InstARM<(ops IntRegs:$a, IntRegs:$b),
 	               "cmp $a, $b",
 		       [(armcmp IntRegs:$a, IntRegs:$b)]>;





From rafael.espindola at gmail.com  Fri Sep  8 07:53:05 2006
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Fri, 8 Sep 2006 07:53:05 -0500
Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/ARM/select.ll
Message-ID: <200609081253.k88Cr5T1012965@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CodeGen/ARM:

select.ll updated: 1.7 -> 1.8
---
Log message:

fix select.ll to always test a select node


---
Diffs of the changes:  (+2 -11)

 select.ll |   13 ++-----------
 1 files changed, 2 insertions(+), 11 deletions(-)


Index: llvm/test/Regression/CodeGen/ARM/select.ll
diff -u llvm/test/Regression/CodeGen/ARM/select.ll:1.7 llvm/test/Regression/CodeGen/ARM/select.ll:1.8
--- llvm/test/Regression/CodeGen/ARM/select.ll:1.7	Fri Sep  8 07:47:03 2006
+++ llvm/test/Regression/CodeGen/ARM/select.ll	Fri Sep  8 07:52:50 2006
@@ -3,15 +3,6 @@
 int %f(int %a) {
 entry:
 	%tmp = seteq int %a, 4		; <bool> [#uses=1]
-	br bool %tmp, label %cond_false, label %cond_true
-
-cond_true:		; preds = %entry
-	br label %return
-
-cond_false:		; preds = %entry
-	br label %return
-
-return:		; preds = %cond_false, %cond_true
-	%retval.0 = phi int [ 2, %cond_true ], [ 3, %cond_false ]		; <int> [#uses=1]
-	ret int %retval.0
+	%tmp1 = select bool %tmp, int 2, int 3
+	ret int %tmp1
 }





From jlaskey at apple.com  Fri Sep  8 08:07:10 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Fri, 8 Sep 2006 08:07:10 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCTargetAsmInfo.cpp
Message-ID: <200609081307.k88D7ASa013382@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCTargetAsmInfo.cpp updated: 1.1 -> 1.2
---
Log message:

Missing tab

---
Diffs of the changes:  (+1 -1)

 PPCTargetAsmInfo.cpp |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/Target/PowerPC/PPCTargetAsmInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCTargetAsmInfo.cpp:1.1 llvm/lib/Target/PowerPC/PPCTargetAsmInfo.cpp:1.2
--- llvm/lib/Target/PowerPC/PPCTargetAsmInfo.cpp:1.1	Thu Sep  7 17:05:02 2006
+++ llvm/lib/Target/PowerPC/PPCTargetAsmInfo.cpp	Fri Sep  8 08:06:56 2006
@@ -24,7 +24,7 @@
   PrivateGlobalPrefix = "L";
   ZeroDirective = "\t.space\t";
   SetDirective = "\t.set";
-  Data64bitsDirective = isPPC64 ? ".quad\t" : 0;  
+  Data64bitsDirective = isPPC64 ? "\t.quad\t" : 0;  
   AlignmentIsInBytes = false;
   ConstantPoolSection = "\t.const\t";
   JumpTableDataSection = ".const";





From rafael.espindola at gmail.com  Fri Sep  8 12:00:01 2006
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Fri, 8 Sep 2006 12:00:01 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.td
Message-ID: <200609081700.k88H01KO017920@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/ARM:

ARMInstrInfo.td updated: 1.23 -> 1.24
---
Log message:

add the eor (xor) instruction


---
Diffs of the changes:  (+5 -0)

 ARMInstrInfo.td |    5 +++++
 1 files changed, 5 insertions(+)


Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.23 llvm/lib/Target/ARM/ARMInstrInfo.td:1.24
--- llvm/lib/Target/ARM/ARMInstrInfo.td:1.23	Fri Sep  8 07:47:03 2006
+++ llvm/lib/Target/ARM/ARMInstrInfo.td	Fri Sep  8 11:59:47 2006
@@ -113,10 +113,15 @@
 		       "and $dst, $a, $b",
 		       [(set IntRegs:$dst, (and IntRegs:$a, IntRegs:$b))]>;
 
+def eor_rr     : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
+		       "eor $dst, $a, $b",
+		       [(set IntRegs:$dst, (xor IntRegs:$a, IntRegs:$b))]>;
+
 def orr_rr    : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
 		       "orr $dst, $a, $b",
 		       [(set IntRegs:$dst, (or IntRegs:$a, IntRegs:$b))]>;
 
+
 let isTwoAddress = 1 in {
   def movcond : InstARM<(ops IntRegs:$dst, IntRegs:$false, IntRegs:$true, CCOp:$cc),
 	                 "mov$cc $dst, $true",





From lattner at cs.uiuc.edu  Fri Sep  8 12:04:10 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 8 Sep 2006 12:04:10 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86JITInfo.cpp
Message-ID: <200609081704.k88H4Aoe018015@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86JITInfo.cpp updated: 1.26 -> 1.27
---
Log message:

Use __USER_LABEL_PREFIX__ to get the prefix added by the current host.



---
Diffs of the changes:  (+14 -15)

 X86JITInfo.cpp |   29 ++++++++++++++---------------
 1 files changed, 14 insertions(+), 15 deletions(-)


Index: llvm/lib/Target/X86/X86JITInfo.cpp
diff -u llvm/lib/Target/X86/X86JITInfo.cpp:1.26 llvm/lib/Target/X86/X86JITInfo.cpp:1.27
--- llvm/lib/Target/X86/X86JITInfo.cpp:1.26	Fri Sep  8 01:48:29 2006
+++ llvm/lib/Target/X86/X86JITInfo.cpp	Fri Sep  8 12:03:56 2006
@@ -39,6 +39,14 @@
 /// compile a function lazily.
 static TargetJITInfo::JITCompilerFn JITCompilerFunction;
 
+// Get the ASMPREFIX for the current host.  This is often '_'.
+#ifndef __USER_LABEL_PREFIX__
+#define __USER_LABEL_PREFIX__
+#endif
+#define GETASMPREFIX2(X) #X
+#define GETASMPREFIX(X) GETASMPREFIX2(X)
+#define ASMPREFIX GETASMPREFIX(__USER_LABEL_PREFIX__)
+
 // Provide a wrapper for X86CompilationCallback2 that saves non-traditional
 // callee saved registers, for the fastcc calling convention.
 extern "C" {
@@ -48,8 +56,8 @@
   asm(
     ".text\n"
     ".align 8\n"
-    ".globl _X86CompilationCallback\n"
-  "_X86CompilationCallback:\n"
+    ".globl " ASMPREFIX "X86CompilationCallback\n"
+  ASMPREFIX "X86CompilationCallback:\n"
     // Save RBP
     "pushq   %rbp\n"
     // Save RSP
@@ -77,7 +85,7 @@
     // JIT callee
     "movq    %rbp, %rdi\n"    // Pass prev frame and return address
     "movq    8(%rbp), %rsi\n"
-    "call    _X86CompilationCallback2\n"
+    "call    " ASMPREFIX "X86CompilationCallback2\n"
     // Restore all XMM arg registers
     "movaps  112(%rsp), %xmm7\n"
     "movaps  96(%rsp), %xmm6\n"
@@ -106,13 +114,8 @@
   asm(
     ".text\n"
     ".align 8\n"
-#if defined(__CYGWIN__) || defined(__APPLE__) || defined(__MINGW32__)
-    ".globl _X86CompilationCallback\n"
-  "_X86CompilationCallback:\n"
-#else
-    ".globl X86CompilationCallback\n"
-  "X86CompilationCallback:\n"
-#endif
+    ".globl " ASMPREFIX  "X86CompilationCallback\n"
+  ASMPREFIX "X86CompilationCallback:\n"
     "pushl   %ebp\n"
     "movl    %esp, %ebp\n"    // Standard prologue
 #if FASTCC_NUM_INT_ARGS_INREGS > 0
@@ -126,11 +129,7 @@
     "movl    4(%ebp), %eax\n" // Pass prev frame and return address
     "movl    %eax, 4(%esp)\n"
     "movl    %ebp, (%esp)\n"
-#if defined(__CYGWIN__) || defined(__MINGW32__) || defined(__APPLE__)
-    "call    _X86CompilationCallback2\n"
-#else
-    "call    X86CompilationCallback2\n"
-#endif
+    "call    " ASMPREFIX "X86CompilationCallback2\n"
     "movl    %ebp, %esp\n"    // Restore ESP
 #if FASTCC_NUM_INT_ARGS_INREGS > 0
     "subl    $8, %esp\n"





From rafael.espindola at gmail.com  Fri Sep  8 12:36:39 2006
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Fri, 8 Sep 2006 12:36:39 -0500
Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/ARM/bits.ll
Message-ID: <200609081736.k88Had3i018615@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CodeGen/ARM:

bits.ll added (r1.1)
---
Log message:

implement shl and sra


---
Diffs of the changes:  (+36 -0)

 bits.ll |   36 ++++++++++++++++++++++++++++++++++++
 1 files changed, 36 insertions(+)


Index: llvm/test/Regression/CodeGen/ARM/bits.ll
diff -c /dev/null llvm/test/Regression/CodeGen/ARM/bits.ll:1.1
*** /dev/null	Fri Sep  8 12:36:33 2006
--- llvm/test/Regression/CodeGen/ARM/bits.ll	Fri Sep  8 12:36:23 2006
***************
*** 0 ****
--- 1,36 ----
+ ; RUN: llvm-as < %s | llc -march=arm &&
+ ; RUN: llvm-as < %s | llc -march=arm | grep and      | wc -l | grep 1 &&
+ ; RUN: llvm-as < %s | llc -march=arm | grep orr      | wc -l | grep 1 &&
+ ; RUN: llvm-as < %s | llc -march=arm | grep eor      | wc -l | grep 1 &&
+ ; RUN: llvm-as < %s | llc -march=arm | grep mov.*lsl | wc -l | grep 1 &&
+ ; RUN: llvm-as < %s | llc -march=arm | grep mov.*asr | wc -l | grep 1
+ 
+ int %f1(int %a, int %b) {
+ entry:
+ 	%tmp2 = and int %b, %a		; <int> [#uses=1]
+ 	ret int %tmp2
+ }
+ 
+ int %f2(int %a, int %b) {
+ entry:
+ 	%tmp2 = or int %b, %a		; <int> [#uses=1]
+ 	ret int %tmp2
+ }
+ 
+ int %f3(int %a, int %b) {
+ entry:
+ 	%tmp2 = xor int %b, %a		; <int> [#uses=1]
+ 	ret int %tmp2
+ }
+ 
+ int %f4(int %a, ubyte %b) {
+ entry:
+ 	%tmp3 = shl int %a, ubyte %b		; <int> [#uses=1]
+ 	ret int %tmp3
+ }
+ 
+ int %f5(int %a, ubyte %b) {
+ entry:
+ 	%tmp3 = shr int %a, ubyte %b		; <int> [#uses=1]
+ 	ret int %tmp3
+ }





From rafael.espindola at gmail.com  Fri Sep  8 12:36:38 2006
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Fri, 8 Sep 2006 12:36:38 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.td
Message-ID: <200609081736.k88HacHW018610@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/ARM:

ARMInstrInfo.td updated: 1.24 -> 1.25
---
Log message:

implement shl and sra


---
Diffs of the changes:  (+12 -0)

 ARMInstrInfo.td |   12 ++++++++++++
 1 files changed, 12 insertions(+)


Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.24 llvm/lib/Target/ARM/ARMInstrInfo.td:1.25
--- llvm/lib/Target/ARM/ARMInstrInfo.td:1.24	Fri Sep  8 11:59:47 2006
+++ llvm/lib/Target/ARM/ARMInstrInfo.td	Fri Sep  8 12:36:23 2006
@@ -113,6 +113,18 @@
 		       "and $dst, $a, $b",
 		       [(set IntRegs:$dst, (and IntRegs:$a, IntRegs:$b))]>;
 
+
+// All arm data processing instructions have a shift. Maybe we don't have
+// to implement this
+def SHL : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
+		       "mov $dst, $a, lsl $b",
+		       [(set IntRegs:$dst, (shl IntRegs:$a, IntRegs:$b))]>;
+
+def SRA : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
+		       "mov $dst, $a, asr $b",
+		       [(set IntRegs:$dst, (sra IntRegs:$a, IntRegs:$b))]>;
+
+
 def eor_rr     : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
 		       "eor $dst, $a, $b",
 		       [(set IntRegs:$dst, (xor IntRegs:$a, IntRegs:$b))]>;





From asl at math.spbu.ru  Fri Sep  8 13:00:57 2006
From: asl at math.spbu.ru (Anton Korobeynikov)
Date: Fri, 8 Sep 2006 13:00:57 -0500
Subject: [llvm-commits] CVS: llvm/tools/Makefile
Message-ID: <200609081800.k88I0vUu019164@zion.cs.uiuc.edu>



Changes in directory llvm/tools:

Makefile updated: 1.55 -> 1.56
---
Log message:

Enabling LTO building on Darwin only right now. This probably should be 
removed after 'PIC vs non-PIC' problem solution


---
Diffs of the changes:  (+4 -2)

 Makefile |    6 ++++--
 1 files changed, 4 insertions(+), 2 deletions(-)


Index: llvm/tools/Makefile
diff -u llvm/tools/Makefile:1.55 llvm/tools/Makefile:1.56
--- llvm/tools/Makefile:1.55	Thu Sep  7 15:21:58 2006
+++ llvm/tools/Makefile	Fri Sep  8 13:00:43 2006
@@ -18,7 +18,9 @@
 		 bugpoint llvm-db llvm-extract \
                  gccas llvm-bcanalyzer llvm-stub \
 		 gccld llvm2cpp \
-                 llvm-ld llvmc llvm-prof \
-                 lto
+                 llvm-ld llvmc llvm-prof
+ifeq ($(OS), Darwin)
+PARALLEL_DIRS += lto
+endif
 
 include $(LEVEL)/Makefile.common





From lattner at cs.uiuc.edu  Fri Sep  8 13:09:04 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 8 Sep 2006 13:09:04 -0500
Subject: [llvm-commits] CVS: llvm/tools/Makefile
Message-ID: <200609081809.k88I94lr019405@zion.cs.uiuc.edu>



Changes in directory llvm/tools:

Makefile updated: 1.56 -> 1.57
---
Log message:

Need to include Makefile.config to get the value of $(OS).  Add a comment.


---
Diffs of the changes:  (+4 -0)

 Makefile |    4 ++++
 1 files changed, 4 insertions(+)


Index: llvm/tools/Makefile
diff -u llvm/tools/Makefile:1.56 llvm/tools/Makefile:1.57
--- llvm/tools/Makefile:1.56	Fri Sep  8 13:00:43 2006
+++ llvm/tools/Makefile	Fri Sep  8 13:08:50 2006
@@ -19,6 +19,10 @@
                  gccas llvm-bcanalyzer llvm-stub \
 		 gccld llvm2cpp \
                  llvm-ld llvmc llvm-prof
+
+include $(LEVEL)/Makefile.common
+
+# Disable liblto on non-darwin platforms right now until LLVM is built PIC.
 ifeq ($(OS), Darwin)
 PARALLEL_DIRS += lto
 endif





From dpatel at apple.com  Fri Sep  8 13:20:39 2006
From: dpatel at apple.com (Devang Patel)
Date: Fri, 8 Sep 2006 13:20:39 -0500
Subject: [llvm-commits] CVS: llvm/tools/Makefile
Message-ID: <200609081820.k88IKd8Y019645@zion.cs.uiuc.edu>



Changes in directory llvm/tools:

Makefile updated: 1.57 -> 1.58
---
Log message:

Remove redundant include.


---
Diffs of the changes:  (+0 -1)

 Makefile |    1 -
 1 files changed, 1 deletion(-)


Index: llvm/tools/Makefile
diff -u llvm/tools/Makefile:1.57 llvm/tools/Makefile:1.58
--- llvm/tools/Makefile:1.57	Fri Sep  8 13:08:50 2006
+++ llvm/tools/Makefile	Fri Sep  8 13:20:25 2006
@@ -27,4 +27,3 @@
 PARALLEL_DIRS += lto
 endif
 
-include $(LEVEL)/Makefile.common





From lattner at cs.uiuc.edu  Fri Sep  8 13:34:04 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 8 Sep 2006 13:34:04 -0500
Subject: [llvm-commits] CVS: llvm/tools/Makefile
Message-ID: <200609081834.k88IY4oS019917@zion.cs.uiuc.edu>



Changes in directory llvm/tools:

Makefile updated: 1.58 -> 1.59
---
Log message:

ok this really works :)


---
Diffs of the changes:  (+2 -1)

 Makefile |    3 ++-
 1 files changed, 2 insertions(+), 1 deletion(-)


Index: llvm/tools/Makefile
diff -u llvm/tools/Makefile:1.58 llvm/tools/Makefile:1.59
--- llvm/tools/Makefile:1.58	Fri Sep  8 13:20:25 2006
+++ llvm/tools/Makefile	Fri Sep  8 13:33:49 2006
@@ -20,10 +20,11 @@
 		 gccld llvm2cpp \
                  llvm-ld llvmc llvm-prof
 
-include $(LEVEL)/Makefile.common
+include $(LEVEL)/Makefile.config
 
 # Disable liblto on non-darwin platforms right now until LLVM is built PIC.
 ifeq ($(OS), Darwin)
 PARALLEL_DIRS += lto
 endif
 
+include $(LEVEL)/Makefile.common





From evan.cheng at apple.com  Fri Sep  8 13:54:36 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 8 Sep 2006 13:54:36 -0500
Subject: [llvm-commits] CVS: llvm-test/MultiSource/Applications/treecc/main.c
Message-ID: <200609081854.k88IsaqO020258@zion.cs.uiuc.edu>



Changes in directory llvm-test/MultiSource/Applications/treecc:

main.c updated: 1.1 -> 1.2
---
Log message:

Temporarily disable treecc for X86-64.

---
Diffs of the changes:  (+4 -0)

 main.c |    4 ++++
 1 files changed, 4 insertions(+)


Index: llvm-test/MultiSource/Applications/treecc/main.c
diff -u llvm-test/MultiSource/Applications/treecc/main.c:1.1 llvm-test/MultiSource/Applications/treecc/main.c:1.2
--- llvm-test/MultiSource/Applications/treecc/main.c:1.1	Tue Apr  6 12:53:30 2004
+++ llvm-test/MultiSource/Applications/treecc/main.c	Fri Sep  8 13:54:22 2006
@@ -27,6 +27,10 @@
 extern	"C" {
 #endif
 
+#ifdef __x86_64__
+#error "Temporarily disabled for X86-64!"
+#endif
+
 static void Usage(char *progname);
 static void Version(void);
 static int ExtraOptions(TreeCCContext *context, char **options, int num);





From lattner at cs.uiuc.edu  Fri Sep  8 14:03:45 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 8 Sep 2006 14:03:45 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/RegAllocLocal.cpp
Message-ID: <200609081903.k88J3jms020482@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen:

RegAllocLocal.cpp updated: 1.89 -> 1.90
---
Log message:

Fix a bunch of llc-beta failures on x86 yesterday.  Don't allow selection
of unallocatable registers, just because an alias is allocatable.  We were
picking registers like SIL just because ESI was being used.


---
Diffs of the changes:  (+42 -17)

 RegAllocLocal.cpp |   59 ++++++++++++++++++++++++++++++++++++++----------------
 1 files changed, 42 insertions(+), 17 deletions(-)


Index: llvm/lib/CodeGen/RegAllocLocal.cpp
diff -u llvm/lib/CodeGen/RegAllocLocal.cpp:1.89 llvm/lib/CodeGen/RegAllocLocal.cpp:1.90
--- llvm/lib/CodeGen/RegAllocLocal.cpp:1.89	Tue Sep  5 15:32:06 2006
+++ llvm/lib/CodeGen/RegAllocLocal.cpp	Fri Sep  8 14:03:30 2006
@@ -66,8 +66,9 @@
     // Virt2PhysRegMap).  The value mapped to is the virtual register
     // corresponding to the physical register (the inverse of the
     // Virt2PhysRegMap), or 0.  The value is set to 0 if this register is pinned
-    // because it is used by a future instruction.  If the entry for a physical
-    // register is -1, then the physical register is "not in the map".
+    // because it is used by a future instruction, and to -2 if it is not
+    // allocatable.  If the entry for a physical register is -1, then the
+    // physical register is "not in the map".
     //
     std::vector<int> PhysRegsUsed;
 
@@ -298,14 +299,16 @@
 void RA::spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I,
                       unsigned PhysReg, bool OnlyVirtRegs) {
   if (PhysRegsUsed[PhysReg] != -1) {            // Only spill it if it's used!
+    assert(PhysRegsUsed[PhysReg] != -2 && "Non allocable reg used!");
     if (PhysRegsUsed[PhysReg] || !OnlyVirtRegs)
       spillVirtReg(MBB, I, PhysRegsUsed[PhysReg], PhysReg);
   } else {
     // If the selected register aliases any other registers, we must make
-    // sure that one of the aliases isn't alive...
+    // sure that one of the aliases isn't alive.
     for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg);
          *AliasSet; ++AliasSet)
-      if (PhysRegsUsed[*AliasSet] != -1)     // Spill aliased register...
+      if (PhysRegsUsed[*AliasSet] != -1 &&     // Spill aliased register.
+          PhysRegsUsed[*AliasSet] != -2)       // If allocatable.
         if (PhysRegsUsed[*AliasSet] || !OnlyVirtRegs)
           spillVirtReg(MBB, I, PhysRegsUsed[*AliasSet], *AliasSet);
   }
@@ -400,7 +403,7 @@
       // physical register!
       assert(PhysRegsUsed[R] != -1 &&
              "PhysReg in PhysRegsUseOrder, but is not allocated?");
-      if (PhysRegsUsed[R]) {
+      if (PhysRegsUsed[R] && PhysRegsUsed[R] != -2) {
         // If the current register is compatible, use it.
         if (RC->contains(R)) {
           PhysReg = R;
@@ -415,7 +418,11 @@
                 // example, if CL is pinned, and we run across CH, don't use
                 // CH as justification for using scavenging ECX (which will
                 // fail).
-                PhysRegsUsed[*AliasIt] != 0) {
+                PhysRegsUsed[*AliasIt] != 0 &&
+                
+                // Make sure the register is allocatable.  Don't allocate SIL on
+                // x86-32.
+                PhysRegsUsed[*AliasIt] != -2) {
               PhysReg = *AliasIt;    // Take an aliased register
               break;
             }
@@ -516,9 +523,11 @@
       PhysRegsUseOrder.push_back(Reg);
       for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
            *AliasSet; ++AliasSet) {
-        PhysRegsUseOrder.push_back(*AliasSet);
-        PhysRegsUsed[*AliasSet] = 0;  // It is free and reserved now
-        PhysRegsEverUsed[*AliasSet] = true;
+        if (PhysRegsUsed[*AliasSet] != -2) {
+          PhysRegsUseOrder.push_back(*AliasSet);
+          PhysRegsUsed[*AliasSet] = 0;  // It is free and reserved now
+          PhysRegsEverUsed[*AliasSet] = true;
+        }
       }
     }    
   }
@@ -530,7 +539,7 @@
     DEBUG(std::cerr << "\nStarting RegAlloc of: " << *MI;
           std::cerr << "  Regs have values: ";
           for (unsigned i = 0; i != RegInfo->getNumRegs(); ++i)
-            if (PhysRegsUsed[i] != -1)
+            if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2)
                std::cerr << "[" << RegInfo->getName(i)
                          << ",%reg" << PhysRegsUsed[i] << "] ";
           std::cerr << "\n");
@@ -593,9 +602,11 @@
         PhysRegsUseOrder.push_back(Reg);
         for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
              *AliasSet; ++AliasSet) {
-          PhysRegsUseOrder.push_back(*AliasSet);
-          PhysRegsUsed[*AliasSet] = 0;  // It is free and reserved now
-          PhysRegsEverUsed[*AliasSet] = true;
+          if (PhysRegsUsed[*AliasSet] != -2) {
+            PhysRegsUseOrder.push_back(*AliasSet);
+            PhysRegsUsed[*AliasSet] = 0;  // It is free and reserved now
+            PhysRegsEverUsed[*AliasSet] = true;
+          }
         }
       }
     }
@@ -605,6 +616,8 @@
       for (const unsigned *ImplicitDefs = TID.ImplicitDefs;
            *ImplicitDefs; ++ImplicitDefs) {
         unsigned Reg = *ImplicitDefs;
+        if (PhysRegsUsed[Reg] == -2) continue;
+
         spillPhysReg(MBB, MI, Reg, true);
         PhysRegsUseOrder.push_back(Reg);
         PhysRegsUsed[Reg] = 0;            // It is free and reserved now
@@ -612,9 +625,11 @@
 
         for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
              *AliasSet; ++AliasSet) {
-          PhysRegsUseOrder.push_back(*AliasSet);
-          PhysRegsUsed[*AliasSet] = 0;  // It is free and reserved now
-          PhysRegsEverUsed[*AliasSet] = true;
+          if (PhysRegsUsed[*AliasSet] != -2) {
+            PhysRegsUseOrder.push_back(*AliasSet);
+            PhysRegsUsed[*AliasSet] = 0;  // It is free and reserved now
+            PhysRegsEverUsed[*AliasSet] = true;
+          }
         }
       }
     }
@@ -675,7 +690,7 @@
 
   // Spill all physical registers holding virtual registers now.
   for (unsigned i = 0, e = RegInfo->getNumRegs(); i != e; ++i)
-    if (PhysRegsUsed[i] != -1)
+    if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2)
       if (unsigned VirtReg = PhysRegsUsed[i])
         spillVirtReg(MBB, MI, VirtReg, i);
       else
@@ -714,6 +729,16 @@
   Fn.setUsedPhysRegs(PhysRegsEverUsed);
 
   PhysRegsUsed.assign(RegInfo->getNumRegs(), -1);
+  
+  // At various places we want to efficiently check to see whether a register
+  // is allocatable.  To handle this, we mark all unallocatable registers as
+  // being pinned down, permanently.
+  {
+    std::vector<bool> Allocable = RegInfo->getAllocatableSet(Fn);
+    for (unsigned i = 0, e = Allocable.size(); i != e; ++i)
+      if (!Allocable[i])
+        PhysRegsUsed[i] = -2;  // Mark the reg unallocable.
+  }
 
   // initialize the virtual->physical register map to have a 'null'
   // mapping for all virtual registers





From lattner at cs.uiuc.edu  Fri Sep  8 14:11:25 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 8 Sep 2006 14:11:25 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/RegAllocLocal.cpp
Message-ID: <200609081911.k88JBP4l020610@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen:

RegAllocLocal.cpp updated: 1.90 -> 1.91
---
Log message:

This fixes Benchmarks/Prolangs-C/unix-smail


---
Diffs of the changes:  (+2 -0)

 RegAllocLocal.cpp |    2 ++
 1 files changed, 2 insertions(+)


Index: llvm/lib/CodeGen/RegAllocLocal.cpp
diff -u llvm/lib/CodeGen/RegAllocLocal.cpp:1.90 llvm/lib/CodeGen/RegAllocLocal.cpp:1.91
--- llvm/lib/CodeGen/RegAllocLocal.cpp:1.90	Fri Sep  8 14:03:30 2006
+++ llvm/lib/CodeGen/RegAllocLocal.cpp	Fri Sep  8 14:11:11 2006
@@ -596,6 +596,8 @@
       if (MO.isRegister() && MO.isDef() && MO.getReg() &&
           MRegisterInfo::isPhysicalRegister(MO.getReg())) {
         unsigned Reg = MO.getReg();
+        if (PhysRegsUsed[Reg] == -2) continue;  // Something like ESP.
+            
         PhysRegsEverUsed[Reg] = true;
         spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in the reg
         PhysRegsUsed[Reg] = 0;            // It is free and reserved now





From jlaskey at apple.com  Fri Sep  8 14:14:12 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Fri, 8 Sep 2006 14:14:12 -0500
Subject: [llvm-commits] CVS: nightlytest-serverside/ProgramResults.php
Message-ID: <200609081914.k88JECdM020725@zion.cs.uiuc.edu>



Changes in directory nightlytest-serverside:

ProgramResults.php updated: 1.39 -> 1.40
---
Log message:

reuse code for e-mail report #1

---
Diffs of the changes:  (+6 -6)

 ProgramResults.php |   12 ++++++------
 1 files changed, 6 insertions(+), 6 deletions(-)


Index: nightlytest-serverside/ProgramResults.php
diff -u nightlytest-serverside/ProgramResults.php:1.39 nightlytest-serverside/ProgramResults.php:1.40
--- nightlytest-serverside/ProgramResults.php:1.39	Fri Sep  8 06:44:44 2006
+++ nightlytest-serverside/ProgramResults.php	Fri Sep  8 14:13:57 2006
@@ -500,7 +500,7 @@
   while ($row = mysql_fetch_array($program_query)) {
     $test_key = $row['program'];
     if (!isset($test_hash[$test_key])) {
-      $result .= $test_key . "<br>\n";
+      $result .= $test_key . "\n";
     }
   }
   mysql_free_result($program_query);
@@ -524,7 +524,6 @@
     $program_query = mysql_query($query) or die (mysql_error());
     $row = mysql_fetch_array($program_query);
     $result = $row['new_tests'];
-    $result = preg_replace("/\n/","<br>\n", $result);
     mysql_free_result($program_query);
   } else {
     $test_hash = getTestSet($prev_id, "tests");
@@ -533,6 +532,7 @@
     $test_hash = getTestSet($prev_id, "program");
     $result .= getExcludedTests($cur_id, "program", $test_hash);
   }
+  $result = preg_replace("/\n/","<br>\n", $result);
   return $result;
 }
 
@@ -553,7 +553,6 @@
     $program_query = mysql_query($query) or die (mysql_error());
     $row = mysql_fetch_array($program_query);
     $result = $row['removed_tests'];
-    $result = preg_replace("/\n/","<br>\n", $result);
     mysql_free_result($program_query);
   } else {
     $test_hash = getTestSet($cur_id, "tests");
@@ -562,6 +561,7 @@
     $test_hash = getTestSet($cur_id, "program");
     $result .= getExcludedTests($prev_id, "program", $test_hash);
   }
+  $result = preg_replace("/\n/","<br>\n", $result);
   return $result;
 }
 
@@ -610,7 +610,7 @@
     $test_key = $row['program'];
     if (isset($test_hash[$test_key]) && isTestPass($row['result'])) {
       $reasons = getFailReasons($test_hash[$test_key]);
-      $result .= "{$test_key}{$reasons}<br>\n";
+      $result .= "{$test_key}{$reasons}\n";
     }
   }
   mysql_free_result($program_query);
@@ -634,7 +634,6 @@
     $program_query = mysql_query($query) or die (mysql_error());
     $row = mysql_fetch_array($program_query);
     $result = $row['newly_passing_tests'];
-    $result = preg_replace("/\n/","<br>\n", $result);
     mysql_free_result($program_query);
   } else {
     $test_hash = getTestFailSet($prev_id, "tests");
@@ -643,6 +642,7 @@
     $test_hash = getTestFailSet($prev_id, "program");
     $result .= getPassingTests($cur_id, "program", $test_hash);
   }
+  $result = preg_replace("/\n/","<br>\n", $result);
   return $result;
 }
 
@@ -663,7 +663,6 @@
     $program_query = mysql_query($query) or die (mysql_error());
     $row = mysql_fetch_array($program_query);
     $result = $row['newly_failing_tests'];
-    $result = preg_replace("/\n/","<br>\n", $result);
     mysql_free_result($program_query);
   } else {
     $test_hash = getTestFailSet($cur_id, "tests");
@@ -672,6 +671,7 @@
     $test_hash = getTestFailSet($cur_id, "program");
     $result .= getPassingTests($prev_id, "program", $test_hash);
   }
+  $result = preg_replace("/\n/","<br>\n", $result);
   return $result;
 }
 





From jlaskey at apple.com  Fri Sep  8 14:23:09 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Fri, 8 Sep 2006 14:23:09 -0500
Subject: [llvm-commits] CVS: nightlytest-serverside/ProgramResults.php
Message-ID: <200609081923.k88JN9Ks020957@zion.cs.uiuc.edu>



Changes in directory nightlytest-serverside:

ProgramResults.php updated: 1.40 -> 1.41
---
Log message:

reuse code for e-mail report #2

---
Diffs of the changes:  (+16 -5)

 ProgramResults.php |   21 ++++++++++++++++-----
 1 files changed, 16 insertions(+), 5 deletions(-)


Index: nightlytest-serverside/ProgramResults.php
diff -u nightlytest-serverside/ProgramResults.php:1.40 nightlytest-serverside/ProgramResults.php:1.41
--- nightlytest-serverside/ProgramResults.php:1.40	Fri Sep  8 14:13:57 2006
+++ nightlytest-serverside/ProgramResults.php	Fri Sep  8 14:22:55 2006
@@ -407,7 +407,7 @@
   }
   
   if (strcmp($result, "") != 0) {
-    $result = " <font color=\"grey\">[" . $result . "]</font>";
+    $result = " [" . $result . "]";
   }
   
   return $result;
@@ -472,6 +472,17 @@
 }
 
 /*
+ * HTMLify test results
+ *
+ */
+function htmlifyTestResults($result) {
+  $result = preg_replace("/\n/", "<br>\n", $result);
+  $result = preg_replace("/\[/", "<font color=\"grey\">[", $result);
+  $result = preg_replace("/\]/", "]</font>", $result);
+  return $result;
+ }
+
+/*
  * Get set of tests
  *
  * Returns a hash of tests for a given night.
@@ -532,7 +543,7 @@
     $test_hash = getTestSet($prev_id, "program");
     $result .= getExcludedTests($cur_id, "program", $test_hash);
   }
-  $result = preg_replace("/\n/","<br>\n", $result);
+  $result = htmlifyTestResults($result);
   return $result;
 }
 
@@ -561,7 +572,7 @@
     $test_hash = getTestSet($cur_id, "program");
     $result .= getExcludedTests($prev_id, "program", $test_hash);
   }
-  $result = preg_replace("/\n/","<br>\n", $result);
+  $result = htmlifyTestResults($result);
   return $result;
 }
 
@@ -642,7 +653,7 @@
     $test_hash = getTestFailSet($prev_id, "program");
     $result .= getPassingTests($cur_id, "program", $test_hash);
   }
-  $result = preg_replace("/\n/","<br>\n", $result);
+  $result = htmlifyTestResults($result);
   return $result;
 }
 
@@ -671,7 +682,7 @@
     $test_hash = getTestFailSet($cur_id, "program");
     $result .= getPassingTests($prev_id, "program", $test_hash);
   }
-  $result = preg_replace("/\n/","<br>\n", $result);
+  $result = htmlifyTestResults($result);
   return $result;
 }
 





From jlaskey at apple.com  Fri Sep  8 14:34:05 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Fri, 8 Sep 2006 14:34:05 -0500
Subject: [llvm-commits] CVS: nightlytest-serverside/ProgramResults.php
Message-ID: <200609081934.k88JY5Pp021213@zion.cs.uiuc.edu>



Changes in directory nightlytest-serverside:

ProgramResults.php updated: 1.41 -> 1.42
---
Log message:

reuse code for e-mail report #3

---
Diffs of the changes:  (+5 -4)

 ProgramResults.php |    9 +++++----
 1 files changed, 5 insertions(+), 4 deletions(-)


Index: nightlytest-serverside/ProgramResults.php
diff -u nightlytest-serverside/ProgramResults.php:1.41 nightlytest-serverside/ProgramResults.php:1.42
--- nightlytest-serverside/ProgramResults.php:1.41	Fri Sep  8 14:22:55 2006
+++ nightlytest-serverside/ProgramResults.php	Fri Sep  8 14:33:51 2006
@@ -426,7 +426,7 @@
     $query = "SELECT * FROM tests WHERE night=$night_id AND result=\"FAIL\" ORDER BY program ASC";
     $program_query = mysql_query($query) or die (mysql_error());
     while($row = mysql_fetch_array($program_query)) {
-      $result .= $row['program'] . "<br>\n";
+      $result .= $row['program'] . "\n";
     }
     mysql_free_result($program_query);
 
@@ -436,11 +436,12 @@
       $test_result = $row['result'];
       if (!isTestPass($test_result)) {
         $reasons = getFailReasons($test_result);        
-        $result .= "{$row['program']}{$reasons}<br>\n";
+        $result .= "{$row['program']}{$reasons}\n";
       }
     }
     mysql_free_result($program_query);
   }
+  $result = htmlifyTestResults($result);
   return $result;
 }
 
@@ -457,17 +458,17 @@
     $program_query = mysql_query($query) or die (mysql_error());
     $row = mysql_fetch_array($program_query);
     $result= $row['unexpfail_tests'];
-    $result=preg_replace("/\n/","<br>\n",$result);
     mysql_free_result($program_query);
   }
   else{
     $query = "SELECT * FROM tests WHERE night=$night_id AND result=\"FAIL\"";
     $program_query = mysql_query($query) or die (mysql_error());
     while($row = mysql_fetch_array($program_query)){
-      $result .= $row['program'] . "<br>\n";
+      $result .= $row['program'] . "\n";
     }
     mysql_free_result($program_query);
   }
+  $result = htmlifyTestResults($result);
   return $result;
 }
 





From jlaskey at apple.com  Fri Sep  8 14:45:52 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Fri, 8 Sep 2006 14:45:52 -0500
Subject: [llvm-commits] CVS: nightlytest-serverside/NightlyTestAccept.cgi
	ProgramResults.php fulltest.php test.php
Message-ID: <200609081945.k88Jjqqf021459@zion.cs.uiuc.edu>



Changes in directory nightlytest-serverside:

NightlyTestAccept.cgi updated: 1.54 -> 1.55
ProgramResults.php updated: 1.42 -> 1.43
fulltest.php updated: 1.17 -> 1.18
test.php updated: 1.19 -> 1.20
---
Log message:

reuse code for e-mail report #4

---
Diffs of the changes:  (+13 -19)

 NightlyTestAccept.cgi |    2 +-
 ProgramResults.php    |    6 ------
 fulltest.php          |   12 ++++++------
 test.php              |   12 ++++++------
 4 files changed, 13 insertions(+), 19 deletions(-)


Index: nightlytest-serverside/NightlyTestAccept.cgi
diff -u nightlytest-serverside/NightlyTestAccept.cgi:1.54 nightlytest-serverside/NightlyTestAccept.cgi:1.55
--- nightlytest-serverside/NightlyTestAccept.cgi:1.54	Mon Sep  4 13:38:46 2006
+++ nightlytest-serverside/NightlyTestAccept.cgi	Fri Sep  8 14:45:37 2006
@@ -839,7 +839,7 @@
 
 if($buildstatus eq "OK") {
   if ($passing eq "") {
-    $pasing = "None";
+    $passing = "None";
   } 
   $email .= "\nNew Test Passes: $passing\n";
   if ($failing eq "") {


Index: nightlytest-serverside/ProgramResults.php
diff -u nightlytest-serverside/ProgramResults.php:1.42 nightlytest-serverside/ProgramResults.php:1.43
--- nightlytest-serverside/ProgramResults.php:1.42	Fri Sep  8 14:33:51 2006
+++ nightlytest-serverside/ProgramResults.php	Fri Sep  8 14:45:37 2006
@@ -441,7 +441,6 @@
     }
     mysql_free_result($program_query);
   }
-  $result = htmlifyTestResults($result);
   return $result;
 }
 
@@ -468,7 +467,6 @@
     }
     mysql_free_result($program_query);
   }
-  $result = htmlifyTestResults($result);
   return $result;
 }
 
@@ -544,7 +542,6 @@
     $test_hash = getTestSet($prev_id, "program");
     $result .= getExcludedTests($cur_id, "program", $test_hash);
   }
-  $result = htmlifyTestResults($result);
   return $result;
 }
 
@@ -573,7 +570,6 @@
     $test_hash = getTestSet($cur_id, "program");
     $result .= getExcludedTests($prev_id, "program", $test_hash);
   }
-  $result = htmlifyTestResults($result);
   return $result;
 }
 
@@ -654,7 +650,6 @@
     $test_hash = getTestFailSet($prev_id, "program");
     $result .= getPassingTests($cur_id, "program", $test_hash);
   }
-  $result = htmlifyTestResults($result);
   return $result;
 }
 
@@ -683,7 +678,6 @@
     $test_hash = getTestFailSet($cur_id, "program");
     $result .= getPassingTests($prev_id, "program", $test_hash);
   }
-  $result = htmlifyTestResults($result);
   return $result;
 }
 


Index: nightlytest-serverside/fulltest.php
diff -u nightlytest-serverside/fulltest.php:1.17 nightlytest-serverside/fulltest.php:1.18
--- nightlytest-serverside/fulltest.php:1.17	Fri Sep  1 05:48:04 2006
+++ nightlytest-serverside/fulltest.php	Fri Sep  8 14:45:37 2006
@@ -132,19 +132,19 @@
  * Printing changes in test suite
  *
  ******************************************************/
-$new_tests=getNewTests($night_id, $previous_succesful_id, $mysql_link);
+$new_tests=htmlifyTestResults(getNewTests($night_id, $previous_succesful_id, $mysql_link));
 if(strcmp($new_tests,"")===0){
   $new_tests="None";
 }
-$removed_tests=getRemovedTests($night_id, $previous_succesful_id, $mysql_link);
+$removed_tests=htmlifyTestResults(getRemovedTests($night_id, $previous_succesful_id, $mysql_link));
 if(strcmp($removed_tests,"")===0){
   $removed_tests="None";
 }
-$newly_passing_tests=getFixedTests($night_id, $previous_succesful_id, $mysql_link);
+$newly_passing_tests=htmlifyTestResults(getFixedTests($night_id, $previous_succesful_id, $mysql_link));
 if(strcmp($newly_passing_tests,"")===0){
   $newly_passing_tests="None";
 }
-$newly_failing_tests=getBrokenTests($night_id, $previous_succesful_id, $mysql_link);
+$newly_failing_tests=htmlifyTestResults(getBrokenTests($night_id, $previous_succesful_id, $mysql_link));
 if(strcmp($newly_failing_tests,"")===0){
   $newly_failing_tests="None";
 }
@@ -179,7 +179,7 @@
  * Printing failures in test suite
  *
  ******************************************************/
-$failing_tests=getFailures($night_id);
+$failing_tests=htmlifyTestResults(getFailures($night_id));
 if(strcmp($failing_tests,"")===0){
   $newly_failing_tests="None";
 }
@@ -200,7 +200,7 @@
 $delta_exppass = $today_row['teststats_exppass']-$yesterday_row['teststats_exppass'];
 $delta_expfail = $today_row['teststats_expfail']-$yesterday_row['teststats_expfail'];
 $delta_unexpfail = $today_row['teststats_unexpfail']-$yesterday_row['teststats_unexpfail'];
-$unexpected_failures = getUnexpectedFailures($night_id);
+$unexpected_failures = htmlifyTestResults(getUnexpectedFailures($night_id));
 
 if($delta_exppass==0 && $delta_expfail==0 && 
    $delta_unexpfail==0 && strcmp($unexpected_failures, "")===0){


Index: nightlytest-serverside/test.php
diff -u nightlytest-serverside/test.php:1.19 nightlytest-serverside/test.php:1.20
--- nightlytest-serverside/test.php:1.19	Fri Sep  1 05:48:04 2006
+++ nightlytest-serverside/test.php	Fri Sep  8 14:45:37 2006
@@ -144,19 +144,19 @@
  * Printing changes in test suite
  *
  ******************************************************/
-$new_tests=getNewTests($night_id, $previous_succesful_id, $mysql_link);
+$new_tests=htmlifyTestResults(getNewTests($night_id, $previous_succesful_id, $mysql_link));
 if(strcmp($new_tests,"")===0){
   $new_tests="None";
 }
-$removed_tests=getRemovedTests($night_id, $previous_succesful_id, $mysql_link);
+$removed_tests=htmlifyTestResults(getRemovedTests($night_id, $previous_succesful_id, $mysql_link));
 if(strcmp($removed_tests,"")===0){
   $removed_tests="None";
 }
-$newly_passing_tests=getFixedTests($night_id, $previous_succesful_id, $mysql_link);
+$newly_passing_tests=htmlifyTestResults(getFixedTests($night_id, $previous_succesful_id, $mysql_link));
 if(strcmp($newly_passing_tests,"")===0){
   $newly_passing_tests="None";
 }
-$newly_failing_tests=getBrokenTests($night_id, $previous_succesful_id, $mysql_link);
+$newly_failing_tests=htmlifyTestResults(getBrokenTests($night_id, $previous_succesful_id, $mysql_link));
 if(strcmp($newly_failing_tests,"")===0){
   $newly_failing_tests="None";
 }
@@ -191,7 +191,7 @@
  * Printing failures in test suite
  *
  ******************************************************/
-$failing_tests=getFailures($night_id);
+$failing_tests=htmlifyTestResultsgetFailures($night_id));
 if(strcmp($failing_tests,"")===0){
   $newly_failing_tests="None";
 }
@@ -212,7 +212,7 @@
 $delta_exppass = $today_row['teststats_exppass']-$yesterday_row['teststats_exppass'];
 $delta_expfail = $today_row['teststats_expfail']-$yesterday_row['teststats_expfail'];
 $delta_unexpfail = $today_row['teststats_unexpfail']-$yesterday_row['teststats_unexpfail'];
-$unexpected_failures = getUnexpectedFailures($night_id);
+$unexpected_failures = htmlifyTestResults(getUnexpectedFailures($night_id));
 
 if($delta_exppass==0 && $delta_expfail==0 && 
    $delta_unexpfail==0 && strcmp($unexpected_failures,"")===0){





From jlaskey at apple.com  Fri Sep  8 14:48:05 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Fri, 8 Sep 2006 14:48:05 -0500
Subject: [llvm-commits] CVS: nightlytest-serverside/test.php
Message-ID: <200609081948.k88Jm59h021549@zion.cs.uiuc.edu>



Changes in directory nightlytest-serverside:

test.php updated: 1.20 -> 1.21
---
Log message:

reuse code for e-mail report #5

---
Diffs of the changes:  (+1 -1)

 test.php |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: nightlytest-serverside/test.php
diff -u nightlytest-serverside/test.php:1.20 nightlytest-serverside/test.php:1.21
--- nightlytest-serverside/test.php:1.20	Fri Sep  8 14:45:37 2006
+++ nightlytest-serverside/test.php	Fri Sep  8 14:47:51 2006
@@ -191,7 +191,7 @@
  * Printing failures in test suite
  *
  ******************************************************/
-$failing_tests=htmlifyTestResultsgetFailures($night_id));
+$failing_tests=htmlifyTestResults(getFailures($night_id));
 if(strcmp($failing_tests,"")===0){
   $newly_failing_tests="None";
 }





From lattner at cs.uiuc.edu  Fri Sep  8 15:21:45 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 8 Sep 2006 15:21:45 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/RegAllocLocal.cpp
Message-ID: <200609082021.k88KLjx2022152@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen:

RegAllocLocal.cpp updated: 1.91 -> 1.92
---
Log message:

Non-allocatable physregs can be killed and dead, but don't treat them as
safe for later allocation.  This fixes McCat/18-imp with llc-beta.


---
Diffs of the changes:  (+6 -0)

 RegAllocLocal.cpp |    6 ++++++
 1 files changed, 6 insertions(+)


Index: llvm/lib/CodeGen/RegAllocLocal.cpp
diff -u llvm/lib/CodeGen/RegAllocLocal.cpp:1.91 llvm/lib/CodeGen/RegAllocLocal.cpp:1.92
--- llvm/lib/CodeGen/RegAllocLocal.cpp:1.91	Fri Sep  8 14:11:11 2006
+++ llvm/lib/CodeGen/RegAllocLocal.cpp	Fri Sep  8 15:21:31 2006
@@ -580,6 +580,9 @@
         unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg);
         PhysReg = PhysRegSlot;
         PhysRegSlot = 0;
+      } else if (PhysRegsUsed[PhysReg] == -2) {
+        // Unallocatable register dead, ignore.
+        continue;
       }
 
       if (PhysReg) {
@@ -669,6 +672,9 @@
         PhysReg = PhysRegSlot;
         assert(PhysReg != 0);
         PhysRegSlot = 0;
+      } else if (PhysRegsUsed[PhysReg] == -2) {
+        // Unallocatable register dead, ignore.
+        continue;
       }
 
       if (PhysReg) {





From evan.cheng at apple.com  Fri Sep  8 16:08:28 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 8 Sep 2006 16:08:28 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp
Message-ID: <200609082108.k88L8SVV023127@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86RegisterInfo.cpp updated: 1.168 -> 1.169
---
Log message:

Fixed a FuseTwoAddrInst() bug: consider GlobalAddress and JumpTableIndex
in addition to immediate operands.


---
Diffs of the changes:  (+11 -6)

 X86RegisterInfo.cpp |   17 +++++++++++------
 1 files changed, 11 insertions(+), 6 deletions(-)


Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.168 llvm/lib/Target/X86/X86RegisterInfo.cpp:1.169
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.168	Fri Sep  8 01:48:29 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp	Fri Sep  8 16:08:13 2006
@@ -169,12 +169,17 @@
   
   // Loop over the rest of the ri operands, converting them over.
   for (unsigned i = 0; i != NumOps; ++i) {
-    if (MI->getOperand(i+2).isReg())
-      MIB = MIB.addReg(MI->getOperand(i+2).getReg());
-    else {
-      assert(MI->getOperand(i+2).isImm() && "Unknown operand type!");
-      MIB = MIB.addImm(MI->getOperand(i+2).getImm());
-    }
+    MachineOperand &MO = MI->getOperand(i+2);
+    if (MO.isReg())
+      MIB = MIB.addReg(MO.getReg());
+    else if (MO.isImm())
+      MIB = MIB.addImm(MO.getImm());
+    else if (MO.isGlobalAddress())
+      MIB = MIB.addGlobalAddress(MO.getGlobal(), MO.getOffset());
+    else if (MO.isJumpTableIndex())
+      MIB = MIB.addJumpTableIndex(MO.getJumpTableIndex());
+    else
+      assert(0 && "Unknown operand type!");
   }
   return MIB;
 }





From jlaskey at apple.com  Fri Sep  8 17:28:02 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Fri, 8 Sep 2006 17:28:02 -0500
Subject: [llvm-commits] CVS: nightlytest-serverside/ProgramResults.php
	fulltest.php test.php
Message-ID: <200609082228.k88MS2M1024362@zion.cs.uiuc.edu>



Changes in directory nightlytest-serverside:

ProgramResults.php updated: 1.43 -> 1.44
fulltest.php updated: 1.18 -> 1.19
test.php updated: 1.21 -> 1.22
---
Log message:

reuse code for e-mail report #6

---
Diffs of the changes:  (+42 -12)

 ProgramResults.php |   38 ++++++++++++++++++++++++++++++++++----
 fulltest.php       |    8 ++++----
 test.php           |    8 ++++----
 3 files changed, 42 insertions(+), 12 deletions(-)


Index: nightlytest-serverside/ProgramResults.php
diff -u nightlytest-serverside/ProgramResults.php:1.43 nightlytest-serverside/ProgramResults.php:1.44
--- nightlytest-serverside/ProgramResults.php:1.43	Fri Sep  8 14:45:37 2006
+++ nightlytest-serverside/ProgramResults.php	Fri Sep  8 17:27:47 2006
@@ -523,7 +523,7 @@
  * This is somewhat of a hack because from night 684 forward we now store the test 
  * in their own table as opposed in the night table.
  */
-function getNewTests($cur_id, $prev_id, $mysql_link){
+function getNewTests($cur_id, $prev_id){
   if (strcmp($prev_id, "") === 0 || strcmp($cur_id, "") === 0) {
     return "";
   }
@@ -551,7 +551,7 @@
  * This is somewhat of a hack because from night 684 forward we now store the test 
  * in their own table as opposed in the night table.
  */
-function getRemovedTests($cur_id, $prev_id, $mysql_link){
+function getRemovedTests($cur_id, $prev_id){
   if (strcmp($prev_id, "") === 0 || strcmp($cur_id, "") === 0) {
     return "";
   }
@@ -631,7 +631,7 @@
  * This is somewhat of a hack because from night 684 forward we now store the test 
  * in their own table as opposed in the night table.
  */
-function getFixedTests($cur_id, $prev_id, $mysql_link){
+function getFixedTests($cur_id, $prev_id){
   if (strcmp($prev_id, "") === 0 || strcmp($cur_id, "") === 0) {
     return "";
   }
@@ -659,7 +659,7 @@
  * This is somewhat of a hack because from night 684 forward we now store the test
  * in their own table as oppoesd in the night table.
  */
-function getBrokenTests($cur_id, $prev_id, $mysql_link){
+function getBrokenTests($cur_id, $prev_id){
   if (strcmp($prev_id, "") === 0 || strcmp($cur_id, "") === 0) {
     return "";
   }
@@ -704,6 +704,36 @@
   return $prev_id;
 }
 
+/*
+ * Email report.
+ *
+ */
+function getEmailReport($cur_id, $prev_id) {
+  $added = getNewTests($cur_id, $prev_id);
+  $removed = getRemovedTests($cur_id, $prev_id);
+  $passing = getFixedTests($cur_id, $prev_id);
+  $failing = getBrokenTests($cur_id, $prev_id);
+  
+  $email = "";
+  if (strcmp($passing, "") == 0) {
+    $passing = "None";
+  } 
+  $email .= "\nNew Test Passes:\n$passing\n";
+  if (strcmp($failing, "") == 0) {
+    $failing = "None";
+  } 
+  $email .= "\nNew Test Failures:\n$failing\n";
+  if (strcmp($added, "") == 0) {
+    $added = "None";
+  } 
+  $email .= "\nAdded Tests:\n$added\n";
+  if (strcmp($removed, "") == 0) {
+    $removed = "None";
+  } 
+  $email .= "\nRemoved Tests:\n$removed\n";
+  
+  return $email;
+}
 
 
 /*$programs=array("Benchmarks/CoyoteBench/huffbench","Benchmarks/CoyoteBench/lpbench");


Index: nightlytest-serverside/fulltest.php
diff -u nightlytest-serverside/fulltest.php:1.18 nightlytest-serverside/fulltest.php:1.19
--- nightlytest-serverside/fulltest.php:1.18	Fri Sep  8 14:45:37 2006
+++ nightlytest-serverside/fulltest.php	Fri Sep  8 17:27:47 2006
@@ -132,19 +132,19 @@
  * Printing changes in test suite
  *
  ******************************************************/
-$new_tests=htmlifyTestResults(getNewTests($night_id, $previous_succesful_id, $mysql_link));
+$new_tests=htmlifyTestResults(getNewTests($night_id, $previous_succesful_id));
 if(strcmp($new_tests,"")===0){
   $new_tests="None";
 }
-$removed_tests=htmlifyTestResults(getRemovedTests($night_id, $previous_succesful_id, $mysql_link));
+$removed_tests=htmlifyTestResults(getRemovedTests($night_id, $previous_succesful_id));
 if(strcmp($removed_tests,"")===0){
   $removed_tests="None";
 }
-$newly_passing_tests=htmlifyTestResults(getFixedTests($night_id, $previous_succesful_id, $mysql_link));
+$newly_passing_tests=htmlifyTestResults(getFixedTests($night_id, $previous_succesful_id));
 if(strcmp($newly_passing_tests,"")===0){
   $newly_passing_tests="None";
 }
-$newly_failing_tests=htmlifyTestResults(getBrokenTests($night_id, $previous_succesful_id, $mysql_link));
+$newly_failing_tests=htmlifyTestResults(getBrokenTests($night_id, $previous_succesful_id));
 if(strcmp($newly_failing_tests,"")===0){
   $newly_failing_tests="None";
 }


Index: nightlytest-serverside/test.php
diff -u nightlytest-serverside/test.php:1.21 nightlytest-serverside/test.php:1.22
--- nightlytest-serverside/test.php:1.21	Fri Sep  8 14:47:51 2006
+++ nightlytest-serverside/test.php	Fri Sep  8 17:27:47 2006
@@ -144,19 +144,19 @@
  * Printing changes in test suite
  *
  ******************************************************/
-$new_tests=htmlifyTestResults(getNewTests($night_id, $previous_succesful_id, $mysql_link));
+$new_tests=htmlifyTestResults(getNewTests($night_id, $previous_succesful_id));
 if(strcmp($new_tests,"")===0){
   $new_tests="None";
 }
-$removed_tests=htmlifyTestResults(getRemovedTests($night_id, $previous_succesful_id, $mysql_link));
+$removed_tests=htmlifyTestResults(getRemovedTests($night_id, $previous_succesful_id));
 if(strcmp($removed_tests,"")===0){
   $removed_tests="None";
 }
-$newly_passing_tests=htmlifyTestResults(getFixedTests($night_id, $previous_succesful_id, $mysql_link));
+$newly_passing_tests=htmlifyTestResults(getFixedTests($night_id, $previous_succesful_id));
 if(strcmp($newly_passing_tests,"")===0){
   $newly_passing_tests="None";
 }
-$newly_failing_tests=htmlifyTestResults(getBrokenTests($night_id, $previous_succesful_id, $mysql_link));
+$newly_failing_tests=htmlifyTestResults(getBrokenTests($night_id, $previous_succesful_id));
 if(strcmp($newly_failing_tests,"")===0){
   $newly_failing_tests="None";
 }





From natebegeman at mac.com  Fri Sep  8 17:42:26 2006
From: natebegeman at mac.com (Nate Begeman)
Date: Fri, 8 Sep 2006 17:42:26 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/MachOWriter.cpp
Message-ID: <200609082242.k88MgQml024595@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen:

MachOWriter.cpp updated: 1.4 -> 1.5
---
Log message:

First pass at supporting relocations.  Relocations are written correctly to
the file now, however the relocated address is currently wrong.  Fixing
that will require some deep pondering.


---
Diffs of the changes:  (+75 -43)

 MachOWriter.cpp |  118 +++++++++++++++++++++++++++++++++++---------------------
 1 files changed, 75 insertions(+), 43 deletions(-)


Index: llvm/lib/CodeGen/MachOWriter.cpp
diff -u llvm/lib/CodeGen/MachOWriter.cpp:1.4 llvm/lib/CodeGen/MachOWriter.cpp:1.5
--- llvm/lib/CodeGen/MachOWriter.cpp:1.4	Sat Sep  2 12:37:30 2006
+++ llvm/lib/CodeGen/MachOWriter.cpp	Fri Sep  8 17:42:09 2006
@@ -25,8 +25,8 @@
 #include "llvm/Module.h"
 #include "llvm/CodeGen/MachineCodeEmitter.h"
 #include "llvm/CodeGen/MachineConstantPool.h"
-#include "llvm/CodeGen/MachineRelocation.h"
 #include "llvm/CodeGen/MachOWriter.h"
+#include "llvm/ExecutionEngine/ExecutionEngine.h"
 #include "llvm/Target/TargetJITInfo.h"
 #include "llvm/Support/Mangler.h"
 #include "llvm/Support/MathExtras.h"
@@ -130,19 +130,10 @@
   
   // Get a symbol for the function to add to the symbol table
   const GlobalValue *FuncV = F.getFunction();
-  MachOWriter::MachOSym FnSym(FuncV, MOW.Mang->getValueName(FuncV), MOS->Index);
-  
-  // Figure out the binding (linkage) of the symbol.
-  switch (FuncV->getLinkage()) {
-  default:
-    // appending linkage is illegal for functions.
-    assert(0 && "Unknown linkage type!");
-  case GlobalValue::ExternalLinkage:
-    FnSym.n_type |=  MachOWriter::MachOSym::N_EXT;
-    break;
-  case GlobalValue::InternalLinkage:
-    break;
-  }
+  MachOSym FnSym(FuncV, MOW.Mang->getValueName(FuncV), MOS->Index);
+
+  // FIXME: emit constant pool to appropriate section(s)
+  // FIXME: emit jump table to appropriate section
   
   // Resolve the function's relocations either to concrete pointers in the case
   // of branches from one block to another, or to target relocation entries.
@@ -152,15 +143,14 @@
       void *MBBAddr = (void *)getMachineBasicBlockAddress(MR.getBasicBlock());
       MR.setResultPointer(MBBAddr);
       MOW.TM.getJITInfo()->relocate(BufferBegin, &MR, 1, 0);
-      // FIXME: we basically want the JITInfo relocate() function to rewrite
-      //        this guy right now, so we just write the correct displacement
-      //        to the file.
+    } else if (MR.isConstantPoolIndex() || MR.isJumpTableIndex()) {
+      // Get the address of the index.
+      uint64_t Addr = 0;
+      // Generate the relocation(s) for the index.
+      MOW.GetTargetRelocation(*MOS, MR, Addr);
     } else {
-      // isString | isGV | isCPI | isJTI
-      // FIXME: do something smart here.  We won't be able to relocate these
-      //        until the sections are all layed out, but we still need to
-      //        record them.  Maybe emit TargetRelocations and then resolve
-      //        those at file writing time?
+      // Handle other types later once we've finalized the sections in the file.
+      MOS->Relocations.push_back(MR);
     }
   }
   Relocations.clear();
@@ -175,7 +165,6 @@
 //===----------------------------------------------------------------------===//
 
 MachOWriter::MachOWriter(std::ostream &o, TargetMachine &tm) : O(o), TM(tm) {
-  // FIXME: set cpu type and cpu subtype somehow from TM
   is64Bit = TM.getTargetData()->getPointerSizeInBits() == 64;
   isLittleEndian = TM.getTargetData()->isLittleEndian();
 
@@ -228,9 +217,7 @@
     // part of the common block if they are zero initialized and allowed to be
     // merged with other symbols.
     if (NoInit || GV->hasLinkOnceLinkage() || GV->hasWeakLinkage()) {
-      MachOWriter::MachOSym ExtOrCommonSym(GV, Mang->getValueName(GV), 
-                                           MachOSym::NO_SECT);
-      ExtOrCommonSym.n_type |= MachOSym::N_EXT;
+      MachOSym ExtOrCommonSym(GV, Mang->getValueName(GV), MachOSym::NO_SECT);
       // For undefined (N_UNDF) external (N_EXT) types, n_value is the size in
       // bytes of the symbol.
       ExtOrCommonSym.n_value = Size;
@@ -254,9 +241,20 @@
   MachOSection &Sec = GV->isConstant() ? getConstSection(Ty) : getDataSection();
   AddSymbolToSection(Sec, GV);
   
-  // FIXME: actually write out the initializer to the section.  This will
-  // require ExecutionEngine's InitializeMemory() function, which will need to
-  // be enhanced to support relocations.
+  // FIXME: A couple significant changes are required for this to work, even for
+  //        trivial cases such as a constant integer:
+  //   0. InitializeMemory needs to be split out of ExecutionEngine.  We don't
+  //      want to have to create an ExecutionEngine such as JIT just to write
+  //      some bytes into a buffer.  The only thing necessary for
+  //      InitializeMemory to function properly should be TargetData.
+  //
+  //   1. InitializeMemory needs to be enhanced to return MachineRelocations 
+  //      rather than accessing the address of objects such basic blocks, 
+  //      constant pools, and jump tables.  The client of InitializeMemory such
+  //      as an object writer or jit emitter should then handle these relocs
+  //      appropriately.
+  //
+  // FIXME: need to allocate memory for the global initializer.
 }
 
 
@@ -292,7 +290,7 @@
   // Emit the symbol table to temporary buffers, so that we know the size of
   // the string table when we write the load commands in the next phase.
   BufferSymbolAndStringTable();
-
+  
   // Emit the header and load commands.
   EmitHeaderAndLoadCommands();
 
@@ -300,9 +298,7 @@
   EmitSections();
 
   // Emit the relocation entry data for each section.
-  // FIXME: presumably this should be a virtual method, since different targets
-  //        have different relocation types.
-  EmitRelocations();
+  O.write((char*)&RelocBuffer[0], RelocBuffer.size());
 
   // Write the symbol table and the string table to the end of the file.
   O.write((char*)&SymT[0], SymT.size());
@@ -368,10 +364,32 @@
   outword(FH, SEG.nsects);
   outword(FH, SEG.flags);
   
-  // Step #5: Write out the section commands for each section
+  // Step #5: Finish filling in the fields of the MachOSections 
+  uint64_t currentAddr = 0;
   for (std::list<MachOSection>::iterator I = SectionList.begin(),
          E = SectionList.end(); I != E; ++I) {
-    I->offset = SEG.fileoff;  // FIXME: separate offset
+    I->addr = currentAddr;
+    I->offset = currentAddr + SEG.fileoff;
+    // FIXME: do we need to do something with alignment here?
+    currentAddr += I->size;
+  }
+  
+  // Step #6: Calculate the number of relocations for each section and write out
+  // the section commands for each section
+  currentAddr += SEG.fileoff;
+  for (std::list<MachOSection>::iterator I = SectionList.begin(),
+         E = SectionList.end(); I != E; ++I) {
+    // calculate the relocation info for this section command
+    // FIXME: this could get complicated calculating the address argument, we 
+    // should probably split this out into its own function.
+    for (unsigned i = 0, e = I->Relocations.size(); i != e; ++i)
+      GetTargetRelocation(*I, I->Relocations[i], 0);
+    if (I->nreloc != 0) {
+      I->reloff = currentAddr;
+      currentAddr += I->nreloc * 8;
+    }
+    
+    // write the finalized section command to the output buffer
     outstring(FH, I->sectname, 16);
     outstring(FH, I->segname, 16);
     outaddr(FH, I->addr);
@@ -387,9 +405,9 @@
       outword(FH, I->reserved3);
   }
   
-  // Step #6: Emit LC_SYMTAB/LC_DYSYMTAB load commands
+  // Step #7: Emit LC_SYMTAB/LC_DYSYMTAB load commands
   // FIXME: add size of relocs
-  SymTab.symoff  = SEG.fileoff + SEG.filesize;
+  SymTab.symoff  = currentAddr;
   SymTab.nsyms   = SymbolTable.size();
   SymTab.stroff  = SymTab.symoff + SymT.size();
   SymTab.strsize = StrT.size();
@@ -436,12 +454,6 @@
   }
 }
 
-void MachOWriter::EmitRelocations() {
-  // FIXME: this should probably be a pure virtual function, since the
-  // relocation types and layout of the relocations themselves are target
-  // specific.
-}
-
 /// PartitionByLocal - Simple boolean predicate that returns true if Sym is
 /// a local symbol rather than an external symbol.
 bool MachOWriter::PartitionByLocal(const MachOSym &Sym) {
@@ -513,3 +525,23 @@
     outaddr(SymT, I->n_value);
   }
 }
+
+MachOSym::MachOSym(const GlobalValue *gv, std::string name, uint8_t sect) :
+  GV(gv), GVName(name), n_strx(0), n_type(sect == NO_SECT ? N_UNDF : N_SECT), 
+  n_sect(sect), n_desc(0), n_value(0) {
+  // FIXME: take a target machine, and then add the appropriate prefix for
+  //        the linkage type based on the TargetAsmInfo
+  switch (GV->getLinkage()) {
+  default:
+    assert(0 && "Unexpected linkage type!");
+    break;
+  case GlobalValue::WeakLinkage:
+  case GlobalValue::LinkOnceLinkage:
+    assert(!isa<Function>(gv) && "Unexpected linkage type for Function!");
+  case GlobalValue::ExternalLinkage:
+    n_type |= N_EXT;
+    break;
+  case GlobalValue::InternalLinkage:
+    break;
+  }
+}





From natebegeman at mac.com  Fri Sep  8 17:42:26 2006
From: natebegeman at mac.com (Nate Begeman)
Date: Fri, 8 Sep 2006 17:42:26 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachOWriter.h
Message-ID: <200609082242.k88MgQLC024592@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

MachOWriter.h updated: 1.5 -> 1.6
---
Log message:

First pass at supporting relocations.  Relocations are written correctly to
the file now, however the relocated address is currently wrong.  Fixing
that will require some deep pondering.


---
Diffs of the changes:  (+86 -54)

 MachOWriter.h |  140 +++++++++++++++++++++++++++++++++++-----------------------
 1 files changed, 86 insertions(+), 54 deletions(-)


Index: llvm/include/llvm/CodeGen/MachOWriter.h
diff -u llvm/include/llvm/CodeGen/MachOWriter.h:1.5 llvm/include/llvm/CodeGen/MachOWriter.h:1.6
--- llvm/include/llvm/CodeGen/MachOWriter.h:1.5	Sat Aug 26 10:46:34 2006
+++ llvm/include/llvm/CodeGen/MachOWriter.h	Fri Sep  8 17:42:09 2006
@@ -16,6 +16,7 @@
 
 #include "llvm/DerivedTypes.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineRelocation.h"
 #include "llvm/Target/TargetData.h"
 #include "llvm/Target/TargetMachine.h"
 #include <list>
@@ -26,6 +27,53 @@
   class MachineCodeEmitter;
   class MachOCodeEmitter;
 
+  /// MachOSym - This struct contains information about each symbol that is
+  /// added to logical symbol table for the module.  This is eventually
+  /// turned into a real symbol table in the file.
+  struct MachOSym {
+    const GlobalValue *GV;    // The global value this corresponds to.
+    std::string GVName;       // The mangled name of the global value.
+    uint32_t    n_strx;       // index into the string table
+    uint8_t     n_type;       // type flag
+    uint8_t     n_sect;       // section number or NO_SECT
+    int16_t     n_desc;       // see <mach-o/stab.h>
+    uint64_t    n_value;      // value for this symbol (or stab offset)
+    
+    // Constants for the n_sect field
+    // see <mach-o/nlist.h>
+    enum { NO_SECT = 0 };   // symbol is not in any section
+
+    // Constants for the n_type field
+    // see <mach-o/nlist.h>
+    enum { N_UNDF  = 0x0,  // undefined, n_sect == NO_SECT
+           N_ABS   = 0x2,  // absolute, n_sect == NO_SECT
+           N_SECT  = 0xe,  // defined in section number n_sect
+           N_PBUD  = 0xc,  // prebound undefined (defined in a dylib)
+           N_INDR  = 0xa   // indirect
+    };
+    // The following bits are OR'd into the types above. For example, a type
+    // of 0x0f would be an external N_SECT symbol (0x0e | 0x01).
+    enum { N_EXT  = 0x01,   // external symbol bit
+           N_PEXT = 0x10    // private external symbol bit
+    };
+    
+    // Constants for the n_desc field
+    // see <mach-o/loader.h>
+    enum { REFERENCE_FLAG_UNDEFINED_NON_LAZY          = 0,
+           REFERENCE_FLAG_UNDEFINED_LAZY              = 1,
+           REFERENCE_FLAG_DEFINED                     = 2,
+           REFERENCE_FLAG_PRIVATE_DEFINED             = 3,
+           REFERENCE_FLAG_PRIVATE_UNDEFINED_NON_LAZY  = 4,
+           REFERENCE_FLAG_PRIVATE_UNDEFINED_LAZY      = 5
+    };
+    enum { N_NO_DEAD_STRIP = 0x0020, // symbol is not to be dead stripped
+           N_WEAK_REF      = 0x0040, // symbol is weak referenced
+           N_WEAK_DEF      = 0x0080  // coalesced symbol is a weak definition
+    };
+    
+    MachOSym(const GlobalValue *gv, std::string name, uint8_t sect);
+  };
+      
   /// MachOWriter - This class implements the common target-independent code for
   /// writing Mach-O files.  Targets should derive a class from this to
   /// parameterize the output format.
@@ -55,7 +103,7 @@
     /// Mang - The object used to perform name mangling for this module.
     ///
     Mangler *Mang;
-
+    
     /// MCE - The MachineCodeEmitter object that we are exposing to emit machine
     /// code for functions to the .o file.
     MachOCodeEmitter *MCE;
@@ -249,6 +297,28 @@
           initprot(VM_PROT_ALL), nsects(0), flags(0) { }
     };
 
+    /// MachORelocation - This struct contains information about each relocation
+    /// that needs to be emitted to the file.
+    /// see <mach-o/reloc.h>
+    struct MachORelocation {
+      uint32_t r_address;   // offset in the section to what is being  relocated
+      uint32_t r_symbolnum; // symbol index if r_extern == 1 else section index
+      bool     r_pcrel;     // was relocated pc-relative already
+      uint8_t  r_length;    // length = 2 ^ r_length
+      bool     r_extern;    // 
+      uint8_t  r_type;      // if not 0, machine-specific relocation type.
+      
+      uint32_t getPackedFields() { 
+        return (r_symbolnum << 8) | (r_pcrel << 7) | ((r_length & 3) << 5) |
+               (r_extern << 4) | (r_type & 15);
+      }
+      
+      MachORelocation(uint32_t addr, uint32_t index, bool pcrel, uint8_t len,
+                      bool ext, uint8_t type) : r_address(addr),
+        r_symbolnum(index), r_pcrel(pcrel), r_length(len), r_extern(ext),
+        r_type(type) {}
+    };
+
     /// MachOSection - This struct contains information about each section in a 
     /// particular segment that is emitted to the file.  This is eventually
     /// turned into the SectionCommand in the load command for a particlar
@@ -275,6 +345,11 @@
       /// up for emission to the file.
       DataBuffer SectionData;
       
+      /// Relocations - The relocations that we have encountered so far in this 
+      /// section that we will need to convert to MachORelocation entries when
+      /// the file is written.
+      std::vector<MachineRelocation> Relocations;
+      
       // Constants for the section types (low 8 bits of flags field)
       // see <mach-o/loader.h>
       enum { S_REGULAR = 0,
@@ -467,57 +542,6 @@
     /// DySymTab - symbol table info for the dynamic link editor
     MachODySymTab DySymTab;
 
-    /// MachOSym - This struct contains information about each symbol that is
-    /// added to logical symbol table for the module.  This is eventually
-    /// turned into a real symbol table in the file.
-    struct MachOSym {
-      const GlobalValue *GV;    // The global value this corresponds to.
-      std::string GVName;       // The mangled name of the global value.
-      uint32_t    n_strx;       // index into the string table
-      uint8_t     n_type;       // type flag
-      uint8_t     n_sect;       // section number or NO_SECT
-      int16_t     n_desc;       // see <mach-o/stab.h>
-      uint64_t    n_value;      // value for this symbol (or stab offset)
-      
-      // Constants for the n_sect field
-      // see <mach-o/nlist.h>
-      enum { NO_SECT = 0 };   // symbol is not in any section
-
-      // Constants for the n_type field
-      // see <mach-o/nlist.h>
-      enum { N_UNDF  = 0x0,  // undefined, n_sect == NO_SECT
-             N_ABS   = 0x2,  // absolute, n_sect == NO_SECT
-             N_SECT  = 0xe,  // defined in section number n_sect
-             N_PBUD  = 0xc,  // prebound undefined (defined in a dylib)
-             N_INDR  = 0xa   // indirect
-      };
-      // The following bits are OR'd into the types above. For example, a type
-      // of 0x0f would be an external N_SECT symbol (0x0e | 0x01).
-      enum { N_EXT  = 0x01,   // external symbol bit
-             N_PEXT = 0x10    // private external symbol bit
-      };
-      
-      // Constants for the n_desc field
-      // see <mach-o/loader.h>
-      enum { REFERENCE_FLAG_UNDEFINED_NON_LAZY          = 0,
-             REFERENCE_FLAG_UNDEFINED_LAZY              = 1,
-             REFERENCE_FLAG_DEFINED                     = 2,
-             REFERENCE_FLAG_PRIVATE_DEFINED             = 3,
-             REFERENCE_FLAG_PRIVATE_UNDEFINED_NON_LAZY  = 4,
-             REFERENCE_FLAG_PRIVATE_UNDEFINED_LAZY      = 5
-      };
-      enum { N_NO_DEAD_STRIP = 0x0020, // symbol is not to be dead stripped
-             N_WEAK_REF      = 0x0040, // symbol is weak referenced
-             N_WEAK_DEF      = 0x0080  // coalesced symbol is a weak definition
-      };
-      
-      MachOSym(const GlobalValue *gv, std::string name, uint8_t sect) : GV(gv), 
-        GVName(name), n_strx(0), n_type(sect == NO_SECT ? N_UNDF : N_SECT), 
-        n_sect(sect), n_desc(0), n_value(0) {
-        // FIXME: names aren't getting the proper global/local prefix
-      }
-    };
-
     struct MachOSymCmp {
       bool operator()(const MachOSym &LHS, const MachOSym &RHS) {
         return LHS.GVName < RHS.GVName;
@@ -530,13 +554,19 @@
 
     /// PartitionByDefined - Simple boolean predicate that returns true if Sym 
     /// is defined in this module.
-    static bool PartitionByDefined(const MachOWriter::MachOSym &Sym);
+    static bool PartitionByDefined(const MachOSym &Sym);
 
+  protected:
+  
     /// SymbolTable - This is the list of symbols we have emitted to the file.
     /// This actually gets rearranged before emission to the file (to put the
     /// local symbols first in the list).
     std::vector<MachOSym> SymbolTable;
     
+    /// RelocBuffer - A buffer to hold the mach-o relocations before we write
+    /// them out at the appropriate location in the file.
+    DataBuffer RelocBuffer;
+    
     /// SymT - A buffer to hold the symbol table before we write it out at the
     /// appropriate location in the file.
     DataBuffer SymT;
@@ -641,8 +671,10 @@
     void EmitGlobal(GlobalVariable *GV);
     void EmitHeaderAndLoadCommands();
     void EmitSections();
-    void EmitRelocations();
     void BufferSymbolAndStringTable();
+
+    virtual void GetTargetRelocation(MachOSection &MOS, MachineRelocation &MR, 
+                                     uint64_t Addr) = 0;
   };
 }
 





From natebegeman at mac.com  Fri Sep  8 17:42:25 2006
From: natebegeman at mac.com (Nate Begeman)
Date: Fri, 8 Sep 2006 17:42:25 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCJITInfo.cpp
	PPCMachOWriter.cpp PPCRelocations.h
Message-ID: <200609082242.k88MgPMj024587@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCJITInfo.cpp updated: 1.28 -> 1.29
PPCMachOWriter.cpp updated: 1.3 -> 1.4
PPCRelocations.h updated: 1.9 -> 1.10
---
Log message:

First pass at supporting relocations.  Relocations are written correctly to
the file now, however the relocated address is currently wrong.  Fixing
that will require some deep pondering.


---
Diffs of the changes:  (+437 -370)

 PPCJITInfo.cpp     |  703 ++++++++++++++++++++++++++---------------------------
 PPCMachOWriter.cpp |   88 ++++++
 PPCRelocations.h   |   16 -
 3 files changed, 437 insertions(+), 370 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCJITInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCJITInfo.cpp:1.28 llvm/lib/Target/PowerPC/PPCJITInfo.cpp:1.29
--- llvm/lib/Target/PowerPC/PPCJITInfo.cpp:1.28	Mon Aug 28 21:30:59 2006
+++ llvm/lib/Target/PowerPC/PPCJITInfo.cpp	Fri Sep  8 17:42:09 2006
@@ -1,353 +1,350 @@
-//===-- PPCJITInfo.cpp - Implement the JIT interfaces for the PowerPC -----===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file implements the JIT interfaces for the 32-bit PowerPC target.
-//
-//===----------------------------------------------------------------------===//
-
-#define DEBUG_TYPE "jit"
-#include "PPCJITInfo.h"
-#include "PPCRelocations.h"
-#include "llvm/CodeGen/MachineCodeEmitter.h"
-#include "llvm/Config/alloca.h"
-#include "llvm/Support/Debug.h"
-#include <set>
-#include <iostream>
-using namespace llvm;
-
-static TargetJITInfo::JITCompilerFn JITCompilerFunction;
-
-#define BUILD_ADDIS(RD,RS,IMM16) \
-  ((15 << 26) | ((RD) << 21) | ((RS) << 16) | ((IMM16) & 65535))
-#define BUILD_ORI(RD,RS,UIMM16) \
-  ((24 << 26) | ((RS) << 21) | ((RD) << 16) | ((UIMM16) & 65535))
-#define BUILD_ORIS(RD,RS,UIMM16) \
-  ((25 << 26) | ((RS) << 21) | ((RD) << 16) | ((UIMM16) & 65535))
-#define BUILD_RLDICR(RD,RS,SH,ME) \
-  ((30 << 26) | ((RS) << 21) | ((RD) << 16) | (((SH) & 31) << 11) | \
-   (((ME) & 63) << 6) | (1 << 3) | (((SH) >> 5) & 1))
-#define BUILD_MTSPR(RS,SPR)      \
-  ((31 << 26) | ((RS) << 21) | ((SPR) << 16) | (467 << 1))
-#define BUILD_BCCTRx(BO,BI,LINK) \
-  ((19 << 26) | ((BO) << 21) | ((BI) << 16) | (528 << 1) | ((LINK) & 1))
-#define BUILD_B(TARGET, LINK) \
-  ((18 << 26) | (((TARGET) & 0x00FFFFFF) << 2) | ((LINK) & 1))
-
-// Pseudo-ops
-#define BUILD_LIS(RD,IMM16)    BUILD_ADDIS(RD,0,IMM16)
-#define BUILD_SLDI(RD,RS,IMM6) BUILD_RLDICR(RD,RS,IMM6,63-IMM6)
-#define BUILD_MTCTR(RS)        BUILD_MTSPR(RS,9)
-#define BUILD_BCTR(LINK)       BUILD_BCCTRx(20,0,LINK)
-
-static void EmitBranchToAt(uint64_t At, uint64_t To, bool isCall, bool is64Bit){
-  intptr_t Offset = ((intptr_t)To - (intptr_t)At) >> 2;
-  unsigned *AtI = (unsigned*)(intptr_t)At;
-
-  if (Offset >= -(1 << 23) && Offset < (1 << 23)) {   // In range?
-    AtI[0] = BUILD_B(Offset, isCall);     // b/bl target
-  } else if (!is64Bit) {
-    AtI[0] = BUILD_LIS(12, To >> 16);     // lis r12, hi16(address)
-    AtI[1] = BUILD_ORI(12, 12, To);       // ori r12, r12, lo16(address)
-    AtI[2] = BUILD_MTCTR(12);             // mtctr r12
-    AtI[3] = BUILD_BCTR(isCall);          // bctr/bctrl
-  } else {
-    AtI[0] = BUILD_LIS(12, To >> 48);      // lis r12, hi16(address)
-    AtI[1] = BUILD_ORI(12, 12, To >> 32);  // ori r12, r12, lo16(address)
-    AtI[2] = BUILD_SLDI(12, 12, 32);       // sldi r12, r12, 32
-    AtI[3] = BUILD_ORIS(12, 12, To >> 16); // oris r12, r12, hi16(address)
-    AtI[4] = BUILD_ORI(12, 12, To);        // ori r12, r12, lo16(address)
-    AtI[5] = BUILD_MTCTR(12);              // mtctr r12
-    AtI[6] = BUILD_BCTR(isCall);           // bctr/bctrl
-  }
-}
-
-extern "C" void PPC32CompilationCallback();
-extern "C" void PPC64CompilationCallback();
-
-#if (defined(__POWERPC__) || defined (__ppc__) || defined(_POWER)) && !defined(__ppc64__)
-// CompilationCallback stub - We can't use a C function with inline assembly in
-// it, because we the prolog/epilog inserted by GCC won't work for us.  Instead,
-// write our own wrapper, which does things our way, so we have complete control
-// over register saving and restoring.
-asm(
-    ".text\n"
-    ".align 2\n"
-    ".globl _PPC32CompilationCallback\n"
-"_PPC32CompilationCallback:\n"
-    // Make space for 8 ints r[3-10] and 13 doubles f[1-13] and the 
-    // FIXME: need to save v[0-19] for altivec?
-    // FIXME: could shrink frame
-    // Set up a proper stack frame
-    "stwu r1, -208(r1)\n"
-    "mflr r0\n"
-    "stw r0,  216(r1)\n"
-    // Save all int arg registers
-    "stw r10, 204(r1)\n"    "stw r9,  200(r1)\n"
-    "stw r8,  196(r1)\n"    "stw r7,  192(r1)\n"
-    "stw r6,  188(r1)\n"    "stw r5,  184(r1)\n"
-    "stw r4,  180(r1)\n"    "stw r3,  176(r1)\n"
-    // Save all call-clobbered FP regs.
-    "stfd f13, 168(r1)\n"   "stfd f12, 160(r1)\n"
-    "stfd f11, 152(r1)\n"   "stfd f10, 144(r1)\n"
-    "stfd f9,  136(r1)\n"   "stfd f8,  128(r1)\n"
-    "stfd f7,  120(r1)\n"   "stfd f6,  112(r1)\n"
-    "stfd f5,  104(r1)\n"   "stfd f4,   96(r1)\n"
-    "stfd f3,   88(r1)\n"   "stfd f2,   80(r1)\n"
-    "stfd f1,   72(r1)\n"
-    // Arguments to Compilation Callback:
-    // r3 - our lr (address of the call instruction in stub plus 4)
-    // r4 - stub's lr (address of instruction that called the stub plus 4)
-    "mr   r3, r0\n"
-    "lwz  r2, 208(r1)\n" // stub's frame
-    "lwz  r4, 8(r2)\n" // stub's lr
-    "li   r5, 0\n"       // 0 == 32 bit
-    "bl _PPCCompilationCallbackC\n"
-    "mtctr r3\n"
-    // Restore all int arg registers
-    "lwz r10, 204(r1)\n"    "lwz r9,  200(r1)\n"
-    "lwz r8,  196(r1)\n"    "lwz r7,  192(r1)\n"
-    "lwz r6,  188(r1)\n"    "lwz r5,  184(r1)\n"
-    "lwz r4,  180(r1)\n"    "lwz r3,  176(r1)\n"
-    // Restore all FP arg registers
-    "lfd f13, 168(r1)\n"    "lfd f12, 160(r1)\n"
-    "lfd f11, 152(r1)\n"    "lfd f10, 144(r1)\n"
-    "lfd f9,  136(r1)\n"    "lfd f8,  128(r1)\n"
-    "lfd f7,  120(r1)\n"    "lfd f6,  112(r1)\n"
-    "lfd f5,  104(r1)\n"    "lfd f4,   96(r1)\n"
-    "lfd f3,   88(r1)\n"    "lfd f2,   80(r1)\n"
-    "lfd f1,   72(r1)\n"
-    // Pop 3 frames off the stack and branch to target
-    "lwz  r1, 208(r1)\n"
-    "lwz  r2, 8(r1)\n"
-    "mtlr r2\n"
-    "bctr\n"
-    );
-#else
-void PPC32CompilationCallback() {
-  assert(0 && "This is not a power pc, you can't execute this!");
-  abort();
-}
-#endif
-
-#if (defined(__POWERPC__) || defined (__ppc__) || defined(_POWER)) && defined(__ppc64__)
-asm(
-    ".text\n"
-    ".align 2\n"
-    ".globl _PPC64CompilationCallback\n"
-"_PPC64CompilationCallback:\n"
-    // Make space for 8 ints r[3-10] and 13 doubles f[1-13] and the 
-    // FIXME: need to save v[0-19] for altivec?
-    // Set up a proper stack frame
-    "stdu r1, -208(r1)\n"
-    "mflr r0\n"
-    "std r0,  224(r1)\n"
-    // Save all int arg registers
-    "std r10, 200(r1)\n"    "std r9,  192(r1)\n"
-    "std r8,  184(r1)\n"    "std r7,  176(r1)\n"
-    "std r6,  168(r1)\n"    "std r5,  160(r1)\n"
-    "std r4,  152(r1)\n"    "std r3,  144(r1)\n"
-    // Save all call-clobbered FP regs.
-    "stfd f13, 136(r1)\n"   "stfd f12, 128(r1)\n"
-    "stfd f11, 120(r1)\n"   "stfd f10, 112(r1)\n"
-    "stfd f9,  104(r1)\n"   "stfd f8,   96(r1)\n"
-    "stfd f7,   88(r1)\n"   "stfd f6,   80(r1)\n"
-    "stfd f5,   72(r1)\n"   "stfd f4,   64(r1)\n"
-    "stfd f3,   56(r1)\n"   "stfd f2,   48(r1)\n"
-    "stfd f1,   40(r1)\n"
-    // Arguments to Compilation Callback:
-    // r3 - our lr (address of the call instruction in stub plus 4)
-    // r4 - stub's lr (address of instruction that called the stub plus 4)
-    "mr   r3, r0\n"
-    "ld   r2, 208(r1)\n" // stub's frame
-    "ld   r4, 16(r2)\n"  // stub's lr
-    "li   r5, 1\n"       // 1 == 64 bit
-    "bl _PPCCompilationCallbackC\n"
-    "mtctr r3\n"
-    // Restore all int arg registers
-    "ld r10, 200(r1)\n"    "ld r9,  192(r1)\n"
-    "ld r8,  184(r1)\n"    "ld r7,  176(r1)\n"
-    "ld r6,  168(r1)\n"    "ld r5,  160(r1)\n"
-    "ld r4,  152(r1)\n"    "ld r3,  144(r1)\n"
-    // Restore all FP arg registers
-    "lfd f13, 136(r1)\n"    "lfd f12, 128(r1)\n"
-    "lfd f11, 120(r1)\n"    "lfd f10, 112(r1)\n"
-    "lfd f9,  104(r1)\n"    "lfd f8,   96(r1)\n"
-    "lfd f7,   88(r1)\n"    "lfd f6,   80(r1)\n"
-    "lfd f5,   72(r1)\n"    "lfd f4,   64(r1)\n"
-    "lfd f3,   56(r1)\n"    "lfd f2,   48(r1)\n"
-    "lfd f1,   40(r1)\n"
-    // Pop 3 frames off the stack and branch to target
-    "ld  r1, 208(r1)\n"
-    "ld  r2, 16(r1)\n"
-    "mtlr r2\n"
-    "bctr\n"
-    );
-#else
-void PPC64CompilationCallback() {
-  assert(0 && "This is not a power pc, you can't execute this!");
-  abort();
-}
-#endif
-
-extern "C" void *PPCCompilationCallbackC(unsigned *StubCallAddrPlus4,
-                                         unsigned *OrigCallAddrPlus4,
-                                         bool is64Bit) {
-  // Adjust the pointer to the address of the call instruction in the stub
-  // emitted by emitFunctionStub, rather than the instruction after it.
-  unsigned *StubCallAddr = StubCallAddrPlus4 - 1;
-  unsigned *OrigCallAddr = OrigCallAddrPlus4 - 1;
-
-  void *Target = JITCompilerFunction(StubCallAddr);
-
-  // Check to see if *OrigCallAddr is a 'bl' instruction, and if we can rewrite
-  // it to branch directly to the destination.  If so, rewrite it so it does not
-  // need to go through the stub anymore.
-  unsigned OrigCallInst = *OrigCallAddr;
-  if ((OrigCallInst >> 26) == 18) {     // Direct call.
-    intptr_t Offset = ((intptr_t)Target - (intptr_t)OrigCallAddr) >> 2;
-    
-    if (Offset >= -(1 << 23) && Offset < (1 << 23)) {   // In range?
-      // Clear the original target out.
-      OrigCallInst &= (63 << 26) | 3;
-      // Fill in the new target.
-      OrigCallInst |= (Offset & ((1 << 24)-1)) << 2;
-      // Replace the call.
-      *OrigCallAddr = OrigCallInst;
-    }
-  }
-
-  // Assert that we are coming from a stub that was created with our
-  // emitFunctionStub.
-  if ((*StubCallAddr >> 26) == 18)
-    StubCallAddr -= 3;
-  else {
-  assert((*StubCallAddr >> 26) == 19 && "Call in stub is not indirect!");
-    StubCallAddr -= is64Bit ? 9 : 6;
-  }
-
-  // Rewrite the stub with an unconditional branch to the target, for any users
-  // who took the address of the stub.
-  EmitBranchToAt((intptr_t)StubCallAddr, (intptr_t)Target, false, is64Bit);
-
-  // Put the address of the target function to call and the address to return to
-  // after calling the target function in a place that is easy to get on the
-  // stack after we restore all regs.
-  return Target;
-}
-
-
-
-TargetJITInfo::LazyResolverFn
-PPCJITInfo::getLazyResolverFunction(JITCompilerFn Fn) {
-  JITCompilerFunction = Fn;
-  return is64Bit ? PPC64CompilationCallback : PPC32CompilationCallback;
-}
-
-void *PPCJITInfo::emitFunctionStub(void *Fn, MachineCodeEmitter &MCE) {
-  // If this is just a call to an external function, emit a branch instead of a
-  // call.  The code is the same except for one bit of the last instruction.
-  if (Fn != (void*)(intptr_t)PPC32CompilationCallback && 
-      Fn != (void*)(intptr_t)PPC64CompilationCallback) {
-    MCE.startFunctionStub(7*4);
-    intptr_t Addr = (intptr_t)MCE.getCurrentPCValue();
-    MCE.emitWordBE(0);
-    MCE.emitWordBE(0);
-    MCE.emitWordBE(0);
-    MCE.emitWordBE(0);
-    MCE.emitWordBE(0);
-    MCE.emitWordBE(0);
-    MCE.emitWordBE(0);
-    EmitBranchToAt(Addr, (intptr_t)Fn, false, is64Bit);
-    return MCE.finishFunctionStub(0);
-  }
-
-  MCE.startFunctionStub(10*4);
-  if (is64Bit) {
-    MCE.emitWordBE(0xf821ffb1);     // stdu r1,-80(r1)
-    MCE.emitWordBE(0x7d6802a6);     // mflr r11
-    MCE.emitWordBE(0xf9610060);     // std r11, 96(r1)
-  } else {
-    MCE.emitWordBE(0x9421ffe0);     // stwu r1,-32(r1)
-    MCE.emitWordBE(0x7d6802a6);     // mflr r11
-    MCE.emitWordBE(0x91610028);     // stw r11, 40(r1)
-  }
-  intptr_t Addr = (intptr_t)MCE.getCurrentPCValue();
-  MCE.emitWordBE(0);
-  MCE.emitWordBE(0);
-  MCE.emitWordBE(0);
-  MCE.emitWordBE(0);
-  MCE.emitWordBE(0);
-  MCE.emitWordBE(0);
-  MCE.emitWordBE(0);
-  EmitBranchToAt(Addr, (intptr_t)Fn, true, is64Bit);
-  return MCE.finishFunctionStub(0);
-}
-
-
-void PPCJITInfo::relocate(void *Function, MachineRelocation *MR,
-                          unsigned NumRelocs, unsigned char* GOTBase) {
-  for (unsigned i = 0; i != NumRelocs; ++i, ++MR) {
-    unsigned *RelocPos = (unsigned*)Function + MR->getMachineCodeOffset()/4;
-    intptr_t ResultPtr = (intptr_t)MR->getResultPointer();
-    switch ((PPC::RelocationType)MR->getRelocationType()) {
-    default: assert(0 && "Unknown relocation type!");
-    case PPC::reloc_pcrel_bx:
-      // PC-relative relocation for b and bl instructions.
-      ResultPtr = (ResultPtr-(intptr_t)RelocPos) >> 2;
-      assert(ResultPtr >= -(1 << 23) && ResultPtr < (1 << 23) &&
-             "Relocation out of range!");
-      *RelocPos |= (ResultPtr & ((1 << 24)-1))  << 2;
-      break;
-    case PPC::reloc_pcrel_bcx:
-      // PC-relative relocation for BLT,BLE,BEQ,BGE,BGT,BNE, or other
-      // bcx instructions.
-      ResultPtr = (ResultPtr-(intptr_t)RelocPos) >> 2;
-      assert(ResultPtr >= -(1 << 13) && ResultPtr < (1 << 13) &&
-             "Relocation out of range!");
-      *RelocPos |= (ResultPtr & ((1 << 14)-1))  << 2;
-      break;
-    case PPC::reloc_absolute_ptr_high: // Pointer relocations.
-    case PPC::reloc_absolute_ptr_low:
-    case PPC::reloc_absolute_high:     // high bits of ref -> low 16 of instr
-    case PPC::reloc_absolute_low: {    // low bits of ref  -> low 16 of instr
-      ResultPtr += MR->getConstantVal();
-
-      // If this is a high-part access, get the high-part.
-      if (MR->getRelocationType() == PPC::reloc_absolute_high ||
-          MR->getRelocationType() == PPC::reloc_absolute_ptr_high) {
-        // If the low part will have a carry (really a borrow) from the low
-        // 16-bits into the high 16, add a bit to borrow from.
-        if (((int)ResultPtr << 16) < 0)
-          ResultPtr += 1 << 16;
-        ResultPtr >>= 16;
-      }
-
-      // Do the addition then mask, so the addition does not overflow the 16-bit
-      // immediate section of the instruction.
-      unsigned LowBits  = (*RelocPos + ResultPtr) & 65535;
-      unsigned HighBits = *RelocPos & ~65535;
-      *RelocPos = LowBits | HighBits;  // Slam into low 16-bits
-      break;
-    }
-    case PPC::reloc_absolute_low_ix: {  // low bits of ref  -> low 14 of instr
-      ResultPtr += MR->getConstantVal();
-      // Do the addition then mask, so the addition does not overflow the 16-bit
-      // immediate section of the instruction.
-      unsigned LowBits  = (*RelocPos + ResultPtr) & 0xFFFC;
-      unsigned HighBits = *RelocPos & 0xFFFF0003;
-      *RelocPos = LowBits | HighBits;  // Slam into low 14-bits.
-      break;
-    }
-    }
-  }
-}
-
-void PPCJITInfo::replaceMachineCodeForFunction(void *Old, void *New) {
-  EmitBranchToAt((intptr_t)Old, (intptr_t)New, false, is64Bit);
-}
+//===-- PPCJITInfo.cpp - Implement the JIT interfaces for the PowerPC -----===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the JIT interfaces for the 32-bit PowerPC target.
+//
+//===----------------------------------------------------------------------===//
+
+#define DEBUG_TYPE "jit"
+#include "PPCJITInfo.h"
+#include "PPCRelocations.h"
+#include "llvm/CodeGen/MachineCodeEmitter.h"
+#include "llvm/Config/alloca.h"
+#include "llvm/Support/Debug.h"
+#include <set>
+#include <iostream>
+using namespace llvm;
+
+static TargetJITInfo::JITCompilerFn JITCompilerFunction;
+
+#define BUILD_ADDIS(RD,RS,IMM16) \
+  ((15 << 26) | ((RD) << 21) | ((RS) << 16) | ((IMM16) & 65535))
+#define BUILD_ORI(RD,RS,UIMM16) \
+  ((24 << 26) | ((RS) << 21) | ((RD) << 16) | ((UIMM16) & 65535))
+#define BUILD_ORIS(RD,RS,UIMM16) \
+  ((25 << 26) | ((RS) << 21) | ((RD) << 16) | ((UIMM16) & 65535))
+#define BUILD_RLDICR(RD,RS,SH,ME) \
+  ((30 << 26) | ((RS) << 21) | ((RD) << 16) | (((SH) & 31) << 11) | \
+   (((ME) & 63) << 6) | (1 << 3) | (((SH) >> 5) & 1))
+#define BUILD_MTSPR(RS,SPR)      \
+  ((31 << 26) | ((RS) << 21) | ((SPR) << 16) | (467 << 1))
+#define BUILD_BCCTRx(BO,BI,LINK) \
+  ((19 << 26) | ((BO) << 21) | ((BI) << 16) | (528 << 1) | ((LINK) & 1))
+#define BUILD_B(TARGET, LINK) \
+  ((18 << 26) | (((TARGET) & 0x00FFFFFF) << 2) | ((LINK) & 1))
+
+// Pseudo-ops
+#define BUILD_LIS(RD,IMM16)    BUILD_ADDIS(RD,0,IMM16)
+#define BUILD_SLDI(RD,RS,IMM6) BUILD_RLDICR(RD,RS,IMM6,63-IMM6)
+#define BUILD_MTCTR(RS)        BUILD_MTSPR(RS,9)
+#define BUILD_BCTR(LINK)       BUILD_BCCTRx(20,0,LINK)
+
+static void EmitBranchToAt(uint64_t At, uint64_t To, bool isCall, bool is64Bit){
+  intptr_t Offset = ((intptr_t)To - (intptr_t)At) >> 2;
+  unsigned *AtI = (unsigned*)(intptr_t)At;
+
+  if (Offset >= -(1 << 23) && Offset < (1 << 23)) {   // In range?
+    AtI[0] = BUILD_B(Offset, isCall);     // b/bl target
+  } else if (!is64Bit) {
+    AtI[0] = BUILD_LIS(12, To >> 16);     // lis r12, hi16(address)
+    AtI[1] = BUILD_ORI(12, 12, To);       // ori r12, r12, lo16(address)
+    AtI[2] = BUILD_MTCTR(12);             // mtctr r12
+    AtI[3] = BUILD_BCTR(isCall);          // bctr/bctrl
+  } else {
+    AtI[0] = BUILD_LIS(12, To >> 48);      // lis r12, hi16(address)
+    AtI[1] = BUILD_ORI(12, 12, To >> 32);  // ori r12, r12, lo16(address)
+    AtI[2] = BUILD_SLDI(12, 12, 32);       // sldi r12, r12, 32
+    AtI[3] = BUILD_ORIS(12, 12, To >> 16); // oris r12, r12, hi16(address)
+    AtI[4] = BUILD_ORI(12, 12, To);        // ori r12, r12, lo16(address)
+    AtI[5] = BUILD_MTCTR(12);              // mtctr r12
+    AtI[6] = BUILD_BCTR(isCall);           // bctr/bctrl
+  }
+}
+
+extern "C" void PPC32CompilationCallback();
+extern "C" void PPC64CompilationCallback();
+
+#if (defined(__POWERPC__) || defined (__ppc__) || defined(_POWER)) && !defined(__ppc64__)
+// CompilationCallback stub - We can't use a C function with inline assembly in
+// it, because we the prolog/epilog inserted by GCC won't work for us.  Instead,
+// write our own wrapper, which does things our way, so we have complete control
+// over register saving and restoring.
+asm(
+    ".text\n"
+    ".align 2\n"
+    ".globl _PPC32CompilationCallback\n"
+"_PPC32CompilationCallback:\n"
+    // Make space for 8 ints r[3-10] and 13 doubles f[1-13] and the 
+    // FIXME: need to save v[0-19] for altivec?
+    // FIXME: could shrink frame
+    // Set up a proper stack frame
+    "stwu r1, -208(r1)\n"
+    "mflr r0\n"
+    "stw r0,  216(r1)\n"
+    // Save all int arg registers
+    "stw r10, 204(r1)\n"    "stw r9,  200(r1)\n"
+    "stw r8,  196(r1)\n"    "stw r7,  192(r1)\n"
+    "stw r6,  188(r1)\n"    "stw r5,  184(r1)\n"
+    "stw r4,  180(r1)\n"    "stw r3,  176(r1)\n"
+    // Save all call-clobbered FP regs.
+    "stfd f13, 168(r1)\n"   "stfd f12, 160(r1)\n"
+    "stfd f11, 152(r1)\n"   "stfd f10, 144(r1)\n"
+    "stfd f9,  136(r1)\n"   "stfd f8,  128(r1)\n"
+    "stfd f7,  120(r1)\n"   "stfd f6,  112(r1)\n"
+    "stfd f5,  104(r1)\n"   "stfd f4,   96(r1)\n"
+    "stfd f3,   88(r1)\n"   "stfd f2,   80(r1)\n"
+    "stfd f1,   72(r1)\n"
+    // Arguments to Compilation Callback:
+    // r3 - our lr (address of the call instruction in stub plus 4)
+    // r4 - stub's lr (address of instruction that called the stub plus 4)
+    "mr   r3, r0\n"
+    "lwz  r2, 208(r1)\n" // stub's frame
+    "lwz  r4, 8(r2)\n" // stub's lr
+    "li   r5, 0\n"       // 0 == 32 bit
+    "bl _PPCCompilationCallbackC\n"
+    "mtctr r3\n"
+    // Restore all int arg registers
+    "lwz r10, 204(r1)\n"    "lwz r9,  200(r1)\n"
+    "lwz r8,  196(r1)\n"    "lwz r7,  192(r1)\n"
+    "lwz r6,  188(r1)\n"    "lwz r5,  184(r1)\n"
+    "lwz r4,  180(r1)\n"    "lwz r3,  176(r1)\n"
+    // Restore all FP arg registers
+    "lfd f13, 168(r1)\n"    "lfd f12, 160(r1)\n"
+    "lfd f11, 152(r1)\n"    "lfd f10, 144(r1)\n"
+    "lfd f9,  136(r1)\n"    "lfd f8,  128(r1)\n"
+    "lfd f7,  120(r1)\n"    "lfd f6,  112(r1)\n"
+    "lfd f5,  104(r1)\n"    "lfd f4,   96(r1)\n"
+    "lfd f3,   88(r1)\n"    "lfd f2,   80(r1)\n"
+    "lfd f1,   72(r1)\n"
+    // Pop 3 frames off the stack and branch to target
+    "lwz  r1, 208(r1)\n"
+    "lwz  r2, 8(r1)\n"
+    "mtlr r2\n"
+    "bctr\n"
+    );
+#else
+void PPC32CompilationCallback() {
+  assert(0 && "This is not a power pc, you can't execute this!");
+  abort();
+}
+#endif
+
+#if (defined(__POWERPC__) || defined (__ppc__) || defined(_POWER)) && defined(__ppc64__)
+asm(
+    ".text\n"
+    ".align 2\n"
+    ".globl _PPC64CompilationCallback\n"
+"_PPC64CompilationCallback:\n"
+    // Make space for 8 ints r[3-10] and 13 doubles f[1-13] and the 
+    // FIXME: need to save v[0-19] for altivec?
+    // Set up a proper stack frame
+    "stdu r1, -208(r1)\n"
+    "mflr r0\n"
+    "std r0,  224(r1)\n"
+    // Save all int arg registers
+    "std r10, 200(r1)\n"    "std r9,  192(r1)\n"
+    "std r8,  184(r1)\n"    "std r7,  176(r1)\n"
+    "std r6,  168(r1)\n"    "std r5,  160(r1)\n"
+    "std r4,  152(r1)\n"    "std r3,  144(r1)\n"
+    // Save all call-clobbered FP regs.
+    "stfd f13, 136(r1)\n"   "stfd f12, 128(r1)\n"
+    "stfd f11, 120(r1)\n"   "stfd f10, 112(r1)\n"
+    "stfd f9,  104(r1)\n"   "stfd f8,   96(r1)\n"
+    "stfd f7,   88(r1)\n"   "stfd f6,   80(r1)\n"
+    "stfd f5,   72(r1)\n"   "stfd f4,   64(r1)\n"
+    "stfd f3,   56(r1)\n"   "stfd f2,   48(r1)\n"
+    "stfd f1,   40(r1)\n"
+    // Arguments to Compilation Callback:
+    // r3 - our lr (address of the call instruction in stub plus 4)
+    // r4 - stub's lr (address of instruction that called the stub plus 4)
+    "mr   r3, r0\n"
+    "ld   r2, 208(r1)\n" // stub's frame
+    "ld   r4, 16(r2)\n"  // stub's lr
+    "li   r5, 1\n"       // 1 == 64 bit
+    "bl _PPCCompilationCallbackC\n"
+    "mtctr r3\n"
+    // Restore all int arg registers
+    "ld r10, 200(r1)\n"    "ld r9,  192(r1)\n"
+    "ld r8,  184(r1)\n"    "ld r7,  176(r1)\n"
+    "ld r6,  168(r1)\n"    "ld r5,  160(r1)\n"
+    "ld r4,  152(r1)\n"    "ld r3,  144(r1)\n"
+    // Restore all FP arg registers
+    "lfd f13, 136(r1)\n"    "lfd f12, 128(r1)\n"
+    "lfd f11, 120(r1)\n"    "lfd f10, 112(r1)\n"
+    "lfd f9,  104(r1)\n"    "lfd f8,   96(r1)\n"
+    "lfd f7,   88(r1)\n"    "lfd f6,   80(r1)\n"
+    "lfd f5,   72(r1)\n"    "lfd f4,   64(r1)\n"
+    "lfd f3,   56(r1)\n"    "lfd f2,   48(r1)\n"
+    "lfd f1,   40(r1)\n"
+    // Pop 3 frames off the stack and branch to target
+    "ld  r1, 208(r1)\n"
+    "ld  r2, 16(r1)\n"
+    "mtlr r2\n"
+    "bctr\n"
+    );
+#else
+void PPC64CompilationCallback() {
+  assert(0 && "This is not a power pc, you can't execute this!");
+  abort();
+}
+#endif
+
+extern "C" void *PPCCompilationCallbackC(unsigned *StubCallAddrPlus4,
+                                         unsigned *OrigCallAddrPlus4,
+                                         bool is64Bit) {
+  // Adjust the pointer to the address of the call instruction in the stub
+  // emitted by emitFunctionStub, rather than the instruction after it.
+  unsigned *StubCallAddr = StubCallAddrPlus4 - 1;
+  unsigned *OrigCallAddr = OrigCallAddrPlus4 - 1;
+
+  void *Target = JITCompilerFunction(StubCallAddr);
+
+  // Check to see if *OrigCallAddr is a 'bl' instruction, and if we can rewrite
+  // it to branch directly to the destination.  If so, rewrite it so it does not
+  // need to go through the stub anymore.
+  unsigned OrigCallInst = *OrigCallAddr;
+  if ((OrigCallInst >> 26) == 18) {     // Direct call.
+    intptr_t Offset = ((intptr_t)Target - (intptr_t)OrigCallAddr) >> 2;
+    
+    if (Offset >= -(1 << 23) && Offset < (1 << 23)) {   // In range?
+      // Clear the original target out.
+      OrigCallInst &= (63 << 26) | 3;
+      // Fill in the new target.
+      OrigCallInst |= (Offset & ((1 << 24)-1)) << 2;
+      // Replace the call.
+      *OrigCallAddr = OrigCallInst;
+    }
+  }
+
+  // Assert that we are coming from a stub that was created with our
+  // emitFunctionStub.
+  if ((*StubCallAddr >> 26) == 18)
+    StubCallAddr -= 3;
+  else {
+  assert((*StubCallAddr >> 26) == 19 && "Call in stub is not indirect!");
+    StubCallAddr -= is64Bit ? 9 : 6;
+  }
+
+  // Rewrite the stub with an unconditional branch to the target, for any users
+  // who took the address of the stub.
+  EmitBranchToAt((intptr_t)StubCallAddr, (intptr_t)Target, false, is64Bit);
+
+  // Put the address of the target function to call and the address to return to
+  // after calling the target function in a place that is easy to get on the
+  // stack after we restore all regs.
+  return Target;
+}
+
+
+
+TargetJITInfo::LazyResolverFn
+PPCJITInfo::getLazyResolverFunction(JITCompilerFn Fn) {
+  JITCompilerFunction = Fn;
+  return is64Bit ? PPC64CompilationCallback : PPC32CompilationCallback;
+}
+
+void *PPCJITInfo::emitFunctionStub(void *Fn, MachineCodeEmitter &MCE) {
+  // If this is just a call to an external function, emit a branch instead of a
+  // call.  The code is the same except for one bit of the last instruction.
+  if (Fn != (void*)(intptr_t)PPC32CompilationCallback && 
+      Fn != (void*)(intptr_t)PPC64CompilationCallback) {
+    MCE.startFunctionStub(7*4);
+    intptr_t Addr = (intptr_t)MCE.getCurrentPCValue();
+    MCE.emitWordBE(0);
+    MCE.emitWordBE(0);
+    MCE.emitWordBE(0);
+    MCE.emitWordBE(0);
+    MCE.emitWordBE(0);
+    MCE.emitWordBE(0);
+    MCE.emitWordBE(0);
+    EmitBranchToAt(Addr, (intptr_t)Fn, false, is64Bit);
+    return MCE.finishFunctionStub(0);
+  }
+
+  MCE.startFunctionStub(10*4);
+  if (is64Bit) {
+    MCE.emitWordBE(0xf821ffb1);     // stdu r1,-80(r1)
+    MCE.emitWordBE(0x7d6802a6);     // mflr r11
+    MCE.emitWordBE(0xf9610060);     // std r11, 96(r1)
+  } else {
+    MCE.emitWordBE(0x9421ffe0);     // stwu r1,-32(r1)
+    MCE.emitWordBE(0x7d6802a6);     // mflr r11
+    MCE.emitWordBE(0x91610028);     // stw r11, 40(r1)
+  }
+  intptr_t Addr = (intptr_t)MCE.getCurrentPCValue();
+  MCE.emitWordBE(0);
+  MCE.emitWordBE(0);
+  MCE.emitWordBE(0);
+  MCE.emitWordBE(0);
+  MCE.emitWordBE(0);
+  MCE.emitWordBE(0);
+  MCE.emitWordBE(0);
+  EmitBranchToAt(Addr, (intptr_t)Fn, true, is64Bit);
+  return MCE.finishFunctionStub(0);
+}
+
+
+void PPCJITInfo::relocate(void *Function, MachineRelocation *MR,
+                          unsigned NumRelocs, unsigned char* GOTBase) {
+  for (unsigned i = 0; i != NumRelocs; ++i, ++MR) {
+    unsigned *RelocPos = (unsigned*)Function + MR->getMachineCodeOffset()/4;
+    intptr_t ResultPtr = (intptr_t)MR->getResultPointer();
+    switch ((PPC::RelocationType)MR->getRelocationType()) {
+    default: assert(0 && "Unknown relocation type!");
+    case PPC::reloc_pcrel_bx:
+      // PC-relative relocation for b and bl instructions.
+      ResultPtr = (ResultPtr-(intptr_t)RelocPos) >> 2;
+      assert(ResultPtr >= -(1 << 23) && ResultPtr < (1 << 23) &&
+             "Relocation out of range!");
+      *RelocPos |= (ResultPtr & ((1 << 24)-1))  << 2;
+      break;
+    case PPC::reloc_pcrel_bcx:
+      // PC-relative relocation for BLT,BLE,BEQ,BGE,BGT,BNE, or other
+      // bcx instructions.
+      ResultPtr = (ResultPtr-(intptr_t)RelocPos) >> 2;
+      assert(ResultPtr >= -(1 << 13) && ResultPtr < (1 << 13) &&
+             "Relocation out of range!");
+      *RelocPos |= (ResultPtr & ((1 << 14)-1))  << 2;
+      break;
+    case PPC::reloc_absolute_high:     // high bits of ref -> low 16 of instr
+    case PPC::reloc_absolute_low: {    // low bits of ref  -> low 16 of instr
+      ResultPtr += MR->getConstantVal();
+
+      // If this is a high-part access, get the high-part.
+      if (MR->getRelocationType() == PPC::reloc_absolute_high) {
+        // If the low part will have a carry (really a borrow) from the low
+        // 16-bits into the high 16, add a bit to borrow from.
+        if (((int)ResultPtr << 16) < 0)
+          ResultPtr += 1 << 16;
+        ResultPtr >>= 16;
+      }
+
+      // Do the addition then mask, so the addition does not overflow the 16-bit
+      // immediate section of the instruction.
+      unsigned LowBits  = (*RelocPos + ResultPtr) & 65535;
+      unsigned HighBits = *RelocPos & ~65535;
+      *RelocPos = LowBits | HighBits;  // Slam into low 16-bits
+      break;
+    }
+    case PPC::reloc_absolute_low_ix: {  // low bits of ref  -> low 14 of instr
+      ResultPtr += MR->getConstantVal();
+      // Do the addition then mask, so the addition does not overflow the 16-bit
+      // immediate section of the instruction.
+      unsigned LowBits  = (*RelocPos + ResultPtr) & 0xFFFC;
+      unsigned HighBits = *RelocPos & 0xFFFF0003;
+      *RelocPos = LowBits | HighBits;  // Slam into low 14-bits.
+      break;
+    }
+    }
+  }
+}
+
+void PPCJITInfo::replaceMachineCodeForFunction(void *Old, void *New) {
+  EmitBranchToAt((intptr_t)Old, (intptr_t)New, false, is64Bit);
+}


Index: llvm/lib/Target/PowerPC/PPCMachOWriter.cpp
diff -u llvm/lib/Target/PowerPC/PPCMachOWriter.cpp:1.3 llvm/lib/Target/PowerPC/PPCMachOWriter.cpp:1.4
--- llvm/lib/Target/PowerPC/PPCMachOWriter.cpp:1.3	Sun Sep  3 23:14:57 2006
+++ llvm/lib/Target/PowerPC/PPCMachOWriter.cpp	Fri Sep  8 17:42:09 2006
@@ -12,6 +12,7 @@
 //
 //===----------------------------------------------------------------------===//
 
+#include "PPCRelocations.h"
 #include "PPCTargetMachine.h"
 #include "llvm/PassManager.h"
 #include "llvm/CodeGen/MachOWriter.h"
@@ -22,11 +23,28 @@
   class VISIBILITY_HIDDEN PPCMachOWriter : public MachOWriter {
   public:
     PPCMachOWriter(std::ostream &O, PPCTargetMachine &TM) : MachOWriter(O, TM) {
-      // FIMXE: choose ppc64 when appropriate
-      Header.cputype = MachOHeader::CPU_TYPE_POWERPC;
+      if (TM.getTargetData()->getPointerSizeInBits() == 64) {
+        Header.cputype = MachOHeader::CPU_TYPE_POWERPC64;
+      } else {
+        Header.cputype = MachOHeader::CPU_TYPE_POWERPC;
+      }
       Header.cpusubtype = MachOHeader::CPU_SUBTYPE_POWERPC_ALL;
     }
 
+    virtual void GetTargetRelocation(MachOSection &MOS, MachineRelocation &MR,
+                                     uint64_t Addr);
+    
+    // Constants for the relocation r_type field.
+    // see <mach-o/ppc/reloc.h>
+    enum { PPC_RELOC_VANILLA, // generic relocation
+           PPC_RELOC_PAIR,    // the second relocation entry of a pair
+           PPC_RELOC_BR14,    // 14 bit branch displacement to word address
+           PPC_RELOC_BR24,    // 24 bit branch displacement to word address
+           PPC_RELOC_HI16,    // a PAIR follows with the low 16 bits
+           PPC_RELOC_LO16,    // a PAIR follows with the high 16 bits
+           PPC_RELOC_HA16,    // a PAIR follows, which is sign extended to 32b
+           PPC_RELOC_LO14     // LO16 with low 2 bits implicitly zero
+    };
   };
 }
 
@@ -39,3 +57,69 @@
   FPM.add(EW);
   FPM.add(createPPCCodeEmitterPass(TM, EW->getMachineCodeEmitter()));
 }
+
+/// GetTargetRelocation - For the MachineRelocation MR, convert it to one or
+/// more PowerPC MachORelocation(s), add the new relocations to the
+/// MachOSection, and rewrite the instruction at the section offset if required 
+/// by that relocation type.
+void PPCMachOWriter::GetTargetRelocation(MachOSection &MOS,
+                                         MachineRelocation &MR,
+                                         uint64_t Addr) {
+  // Keep track of whether or not this is an externally defined relocation.
+  uint32_t index = MOS.Index;
+  bool     isExtern = false;
+  
+  // Get the address of the instruction to rewrite
+  unsigned char *RelocPos = &MOS.SectionData[0] + MR.getMachineCodeOffset();
+  
+  // Get the address of whatever it is we're relocating, if possible.
+  if (MR.isGlobalValue()) {
+    // determine whether or not its external and then figure out what section
+    // we put it in if it's a locally defined symbol.
+  } else if (MR.isString()) {
+    // lookup in global values?
+  } else {
+    assert((MR.isConstantPoolIndex() || MR.isJumpTableIndex()) &&
+           "Unhandled MachineRelocation type!");
+  }
+  
+  switch ((PPC::RelocationType)MR.getRelocationType()) {
+  default: assert(0 && "Unknown PPC relocation type!");
+  case PPC::reloc_pcrel_bx:
+  case PPC::reloc_pcrel_bcx:
+  case PPC::reloc_absolute_low_ix:
+    assert(0 && "Unhandled PPC relocation type!");
+    break;
+  case PPC::reloc_absolute_high:
+    {
+      MachORelocation HA16(MR.getMachineCodeOffset(), index, false, 2, isExtern, 
+                           PPC_RELOC_HA16);
+      MachORelocation PAIR(Addr & 0xFFFF, 0xFFFFFF, false, 2, isExtern,
+                           PPC_RELOC_PAIR);
+      outword(RelocBuffer, HA16.r_address);
+      outword(RelocBuffer, HA16.getPackedFields());
+      outword(RelocBuffer, PAIR.r_address);
+      outword(RelocBuffer, PAIR.getPackedFields());
+    }
+    MOS.nreloc += 2;
+    Addr += 0x8000;
+    *(unsigned *)RelocPos &= 0xFFFF0000;
+    *(unsigned *)RelocPos |= ((Addr >> 16) & 0xFFFF);
+    break;
+  case PPC::reloc_absolute_low:
+    {
+      MachORelocation LO16(MR.getMachineCodeOffset(), index, false, 2, isExtern, 
+                           PPC_RELOC_LO16);
+      MachORelocation PAIR(Addr >> 16, 0xFFFFFF, false, 2, isExtern,
+                           PPC_RELOC_PAIR);
+      outword(RelocBuffer, LO16.r_address);
+      outword(RelocBuffer, LO16.getPackedFields());
+      outword(RelocBuffer, PAIR.r_address);
+      outword(RelocBuffer, PAIR.getPackedFields());
+    }
+    MOS.nreloc += 2;
+    *(unsigned *)RelocPos &= 0xFFFF0000;
+    *(unsigned *)RelocPos |= (Addr & 0xFFFF);
+    break;
+  }
+}


Index: llvm/lib/Target/PowerPC/PPCRelocations.h
diff -u llvm/lib/Target/PowerPC/PPCRelocations.h:1.9 llvm/lib/Target/PowerPC/PPCRelocations.h:1.10
--- llvm/lib/Target/PowerPC/PPCRelocations.h:1.9	Thu Jul 27 13:20:32 2006
+++ llvm/lib/Target/PowerPC/PPCRelocations.h	Fri Sep  8 17:42:09 2006
@@ -44,21 +44,7 @@
       
       // reloc_absolute_low_ix - Absolute relocation for the 64-bit load/store
       // instruction which have two implicit zero bits.
-      reloc_absolute_low_ix,
-
-      // reloc_absolute_ptr_high - Absolute relocation for references to lazy
-      // pointer stubs.  In this case, the relocated instruction should be
-      // relocated to point to a POINTER to the indicated global.  The low-16
-      // bits of the instruction are rewritten with the high 16-bits of the
-      // address of the pointer.
-      reloc_absolute_ptr_high,
-
-      // reloc_absolute_ptr_low - Absolute relocation for references to lazy
-      // pointer stubs.  In this case, the relocated instruction should be
-      // relocated to point to a POINTER to the indicated global.  The low-16
-      // bits of the instruction are rewritten with the low 16-bits of the
-      // address of the pointer.
-      reloc_absolute_ptr_low
+      reloc_absolute_low_ix
     };
   }
 }





From jlaskey at apple.com  Fri Sep  8 17:47:39 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Fri, 8 Sep 2006 17:47:39 -0500
Subject: [llvm-commits] CVS: nightlytest-serverside/NightlyTester.php
	ProgramResults.php drawfilesizegraph.php fulltest.php
	index.php individualfilesizegraph.php individualgraph.php
	machine.php multiplemachinegraph.php multipleresultsgraph.php
	sidebar.php test.php testers.php
Message-ID: <200609082247.k88Mld9H024755@zion.cs.uiuc.edu>



Changes in directory nightlytest-serverside:

NightlyTester.php updated: 1.19 -> 1.20
ProgramResults.php updated: 1.44 -> 1.45
drawfilesizegraph.php updated: 1.3 -> 1.4
fulltest.php updated: 1.19 -> 1.20
index.php updated: 1.8 -> 1.9
individualfilesizegraph.php updated: 1.3 -> 1.4
individualgraph.php updated: 1.2 -> 1.3
machine.php updated: 1.5 -> 1.6
multiplemachinegraph.php updated: 1.1.1.1 -> 1.2
multipleresultsgraph.php updated: 1.1.1.1 -> 1.2
sidebar.php updated: 1.9 -> 1.10
test.php updated: 1.22 -> 1.23
testers.php updated: 1.1.1.1 -> 1.2
---
Log message:

reuse code for e-mail report #7

---
Diffs of the changes:  (+81 -81)

 NightlyTester.php           |   46 ++++++++++++++++++++++----------------------
 ProgramResults.php          |   16 +++++++--------
 drawfilesizegraph.php       |    4 +--
 fulltest.php                |   10 ++++-----
 index.php                   |    6 ++---
 individualfilesizegraph.php |    2 -
 individualgraph.php         |    6 ++---
 machine.php                 |   12 +++++------
 multiplemachinegraph.php    |    6 ++---
 multipleresultsgraph.php    |    6 ++---
 sidebar.php                 |   26 ++++++++++++------------
 test.php                    |   16 +++++++--------
 testers.php                 |    6 ++---
 13 files changed, 81 insertions(+), 81 deletions(-)


Index: nightlytest-serverside/NightlyTester.php
diff -u nightlytest-serverside/NightlyTester.php:1.19 nightlytest-serverside/NightlyTester.php:1.20
--- nightlytest-serverside/NightlyTester.php:1.19	Tue Aug 29 15:48:07 2006
+++ nightlytest-serverside/NightlyTester.php	Fri Sep  8 17:47:25 2006
@@ -19,9 +19,9 @@
  *          being the column names 
  *
  *****************************************************/
-function getMachineInfo($machine_id, $mysql_link){
+function getMachineInfo($machine_id){
   $query="SELECT * FROM machine WHERE id=$machine_id";
-  $machine_query = mysql_query($query, $mysql_link) or die ("$night failed! " . mysql_error());
+  $machine_query = mysql_query($query) or die ("$night failed! " . mysql_error());
   $row = mysql_fetch_array($machine_query);
   mysql_free_result($machine_query);
   return $row;
@@ -34,7 +34,7 @@
  *          rows.
  *
  *****************************************************/
-function getMachineResource($mysql_link){
+function getMachineResource(){
   $machine_query = mysql_query("SELECT * FROM machine ORDER BY nickname ASC") or die (mysql_error());
   return $machine_query;
 }
@@ -47,7 +47,7 @@
  *          rows.
  *
  *****************************************************/
-function getRecentMachineResource($mysql_link){
+function getRecentMachineResource(){
   $night_query = mysql_query("SELECT machine FROM night where DATE_SUB(NOW(), INTERVAL 14 DAY) <= added") or die (mysql_error());
   $machines="where id=0";
   $machine_arr = array();
@@ -71,7 +71,7 @@
  *          rows.
  *
  *****************************************************/
-function getOldMachineResource($mysql_link){
+function getOldMachineResource(){
   $night_query = mysql_query("SELECT machine FROM night where DATE_SUB(NOW(), INTERVAL 1 MONTH) > added") or die (mysql_error());
   $machines="where id=0";
   $machine_arr = array();
@@ -94,7 +94,7 @@
  *          being the column names 
  *
  *****************************************************/
-function getNightInfo($night_id, $mysql_link){
+function getNightInfo($night_id){
  $query="SELECT * FROM night WHERE id=$night_id";
  $today_query = mysql_query("SELECT * FROM night WHERE id=$night_id") or die ("$query failed! " . mysql_error());
  $today_row = mysql_fetch_array($today_query);
@@ -110,7 +110,7 @@
  *          mysql_fetch_array on.
  *
  *****************************************************/
-function getNightsResource($machine_id, $mysql_link, $start="2000-01-01 01:01:01", $end="2020-12-30 01:01:01", $order="DESC"){
+function getNightsResource($machine_id, $start="2000-01-01 01:01:01", $end="2020-12-30 01:01:01", $order="DESC"){
  $query = mysql_query("SELECT * FROM night WHERE machine=$machine_id and added<=\"$end\" and added>=\"$start\" order by added $order") or die (mysql_error());
  return $query;
 }
@@ -123,7 +123,7 @@
  * Returns: A mysql result
  *
  *****************************************************/
-function getNightsIDs($machine_id, $mysql_link, $start="2000-01-01 01:01:01", $end="2020-12-30 01:01:01", $order="DESC"){
+function getNightsIDs($machine_id, $start="2000-01-01 01:01:01", $end="2020-12-30 01:01:01", $order="DESC"){
  $query = mysql_query("SELECT id, added FROM night WHERE machine=$machine_id and added<=\"$end\" and added>=\"$start\" ORDER BY added $order") or die (mysql_error());
  return $query;
 }
@@ -136,7 +136,7 @@
  *          mysql_fetch_array on.
  *
  *****************************************************/
-function getSuccessfulNightsHistory($machine_id, $mysql_link, $night_id, $order="DESC"){
+function getSuccessfulNightsHistory($machine_id, $night_id, $order="DESC"){
   $query="SELECT * FROM night WHERE machine=$machine_id and id<=$night_id and buildstatus=\"OK\" order by added $order";
   $query = mysql_query($query) or die (mysql_error());
   return $query;
@@ -149,7 +149,7 @@
  * Returns: A mysql query resource.
  *
  *****************************************************/
-function getRecentTests($hours="24", $mysql_link){
+function getRecentTests($hours="24"){
  $result = mysql_query("select * from night where DATE_SUB(NOW(),INTERVAL $hours HOUR)<=added ORDER BY added DESC") or die (mysql_error());
  return $result;
 }
@@ -161,7 +161,7 @@
  * Returns: A string formatted as "Year-month-day H:M:S" 
  *
  *****************************************************/
-function calculateDate($mysql_link, $time_frame="1 YEAR", $origin_date="CURDATE()"){
+function calculateDate($time_frame="1 YEAR", $origin_date="CURDATE()"){
  if(strpos($origin_date, "CURDATE")===false){
   $query=mysql_query("SELECT \"$origin_date\" - INTERVAL $time_frame") or die(mysql_error());
  }
@@ -182,7 +182,7 @@
  * file and the value being the size of the file.
  *
  *****************************************************/
-function getAllFileSizes($mysql_link, $night_id){
+function getAllFileSizes($night_id){
   $select = "select * from file WHERE night=$night_id";
   $query = mysql_query($select) or die (mysql_error());
   $result=array();
@@ -202,7 +202,7 @@
  * night, and build type
  *
  *****************************************************/
-function get_file_history($mysql_link, $machine_id, $file_name){
+function get_file_history($machine_id, $file_name){
   $nights_select = "select id, added from night WHERE machine=$machine_id ".
                    "order by added desc";
   $nights_query = mysql_query($nights_select) 
@@ -240,7 +240,7 @@
  * not available the array will contain -.
  *
  *****************************************************/
-function buildFileSizeTable($mysql_link, $machine_id, $night_id){
+function buildFileSizeTable($machine_id, $night_id){
   $result=array();
 
   //setting up the night ids
@@ -255,9 +255,9 @@
   $old_night=$row['id'];
   mysql_free_result($query);
   
-  if($cur_night>0) { $cur_data=getAllFileSizes($mysql_link, $cur_night); }
-  if($prev_night>0) { $prev_data=getAllFileSizes($mysql_link, $prev_night); }
-  if($old_night>0) { $old_data=getAllFileSizes($mysql_link, $old_night); }
+  if($cur_night>0) { $cur_data=getAllFileSizes($cur_night); }
+  if($prev_night>0) { $prev_data=getAllFileSizes($prev_night); }
+  if($old_night>0) { $old_data=getAllFileSizes($old_night); }
 
   $cur_sum=0;
   $prev_sum=0;
@@ -319,20 +319,20 @@
 $machine_id = 8;
 $file="./test/Regression/Archive/xpg4.a";
 
-$files = get_file_history($mysql_link, $machine_id, $file);
+$files = get_file_history($machine_id, $file);
 
 foreach (array_keys($files) as $f){
  print "$f = > {$files["$f"][0]}<br>\n";
 }
 
-$machine_info = getMachineInfo(21, $mysql_link);
+$machine_info = getMachineInfo(21);
 foreach (array_keys($machine_info) as $key){
  print "$key => {$machine_info["$key"]}<br>\n";
 }
 print "<br><br><br>\n";
 
 $night_id=-1;
-$night_resource = getNightsResource($machine_info['id'], $mysql_link);
+$night_resource = getNightsResource($machine_info['id']);
  while($row = mysql_fetch_array($night_resource)){
  print "added => {$row['added']}<br>\n";
  $night_id=$row['id'];
@@ -341,11 +341,11 @@
 print "<br><br><br>\n";
 
 
-$night_info = getNightInfo($night_id, $mysql_link);
+$night_info = getNightInfo($night_id);
 print "buildstatus => {$night_info['buildstatus']}<br>\n";
 print "<br><br><br>\n";
 
-$recent_resource = getRecentTests($machine_info['id'], $mysql_link);
+$recent_resource = getRecentTests($machine_info['id']);
  while($row = mysql_fetch_array($recent_resource)){
  print "added => {$row['added']}<br>\n";
  $night_id=$row['id'];
@@ -353,7 +353,7 @@
 mysql_free_result($recent_resource);
 print "<br><br><br>\n";
 
-$my_day = calculateDate($mysql_link,"30 WEEK");
+$my_day = calculateDate("30 WEEK");
 print "today's date - 30 weeks = $my_day<br>\n";
 print "<br><br><br>\n";
 */


Index: nightlytest-serverside/ProgramResults.php
diff -u nightlytest-serverside/ProgramResults.php:1.44 nightlytest-serverside/ProgramResults.php:1.45
--- nightlytest-serverside/ProgramResults.php:1.44	Fri Sep  8 17:27:47 2006
+++ nightlytest-serverside/ProgramResults.php	Fri Sep  8 17:47:25 2006
@@ -133,7 +133,7 @@
  * "extenal." 
  *
  */
-function GetDayResults($night_id, $array_of_measures, $mysql_link){
+function GetDayResults($night_id, $array_of_measures ){
   $result=array();
   #print "SELECT * FROM program WHERE night=$night_id ORDER BY program ASC<br>\n";
   $program_query = mysql_query("SELECT * FROM program WHERE night=$night_id ORDER BY program ASC") or die (mysql_error());
@@ -337,12 +337,12 @@
  * being an array containing (date in seconds since epoch, program[0], program[1], ... , 
  * program[n]) for all the data between the two dates
  */
-function buildResultsHistory($machine_id, $programs, $measure, $mysql_link, $start="2000-01-01 01:01:01", $end="2020-01-01 01:01:01"){
+function buildResultsHistory($machine_id, $programs, $measure , $start="2000-01-01 01:01:01", $end="2020-01-01 01:01:01"){
   $preg_measure = str_replace("/","\/", $measure);
   $results_arr=array();
   $night_table_statement = "SELECT id, added FROM night WHERE machine=$machine_id ". 
   "AND added >= \"$start\" AND added <= \"$end\" ORDER BY added DESC";
-  $night_table_query = mysql_query($night_table_statement, $mysql_link) or die(mysql_error());
+  $night_table_query = mysql_query($night_table_statement ) or die(mysql_error());
   $night_arr=array();
   $night_query="(";
   while($row = mysql_fetch_array($night_table_query)){
@@ -687,7 +687,7 @@
  * Returns the night id for the machine of the night passed in
  * where build status = OK
  */
-function getPreviousWorkingNight($night_id, $mysql_link){
+function getPreviousWorkingNight($night_id ){
   $query = "SELECT machine FROM night WHERE id=$night_id";
   $program_query = mysql_query($query) or die (mysql_error());
   $row = mysql_fetch_array($program_query);
@@ -737,7 +737,7 @@
 
 
 /*$programs=array("Benchmarks/CoyoteBench/huffbench","Benchmarks/CoyoteBench/lpbench");
-$history = buildResultsHistory(18, $programs,"GCCAS",$mysql_link);
+$history = buildResultsHistory(18, $programs,"GCCAS" );
 foreach (array_keys($history) as $date){
   print "$date => ";
   foreach($history["$date"] as $data){
@@ -747,9 +747,9 @@
 }*/
 
 if($DEBUG){
-  $today_results = GetDayResults(565, $category_array, $mysql_link);
-  $yesterday_results = GetDayResults(564, $category_array, $mysql_link);
-  $oldday_results = GetDayResults(563, $category_array, $mysql_link);
+  $today_results = GetDayResults(565, $category_array );
+  $yesterday_results = GetDayResults(564, $category_array );
+  $oldday_results = GetDayResults(563, $category_array );
   $percent_difference = CalculateChangeBetweenDays($yesterday_results, $today_results, .2);
   $twoday_difference = CalculateChangeBetweenDays($oldday_results, $today_results, .01);
   $count = CountSignifigantDifferences($percent_difference, 1, 25);


Index: nightlytest-serverside/drawfilesizegraph.php
diff -u nightlytest-serverside/drawfilesizegraph.php:1.3 nightlytest-serverside/drawfilesizegraph.php:1.4
--- nightlytest-serverside/drawfilesizegraph.php:1.3	Tue Aug  1 18:35:41 2006
+++ nightlytest-serverside/drawfilesizegraph.php	Fri Sep  8 17:47:25 2006
@@ -185,10 +185,10 @@
 $index=0;
 foreach ($files as $file){
 
-  $data = get_file_history($mysql_link, $machine_id, $file);
+  $data = get_file_history($machine_id, $file);
 
   if($DEBUG){
-    print "get_file_history($mysql_link, $machine_id, $file) returned...<br>\n";
+    print "get_file_history($machine_id, $file) returned...<br>\n";
     foreach (array_keys($data) as $x){
       print "$x {$data["$x"][0]} {$data["$x"][1]} {$data["$x"][2]}<br>\n";
     }


Index: nightlytest-serverside/fulltest.php
diff -u nightlytest-serverside/fulltest.php:1.19 nightlytest-serverside/fulltest.php:1.20
--- nightlytest-serverside/fulltest.php:1.19	Fri Sep  8 17:27:47 2006
+++ nightlytest-serverside/fulltest.php	Fri Sep  8 17:47:25 2006
@@ -18,14 +18,14 @@
 $row = mysql_fetch_array($machine_query);
 mysql_free_result($machine_query);
 
-$today_query = getSuccessfulNightsHistory($machine_id, $mysql_link, $night_id);
+$today_query = getSuccessfulNightsHistory($machine_id, $night_id);
 $today_row = mysql_fetch_array($today_query);
 $yesterday_row = mysql_fetch_array($today_query);
 $oldday_row = mysql_fetch_array($today_query);
 mysql_free_result($today_query);
 $cur_date=$today_row['added'];
 
-$previous_succesful_id = getPreviousWorkingNight($night_id, $mysql_link);
+$previous_succesful_id = getPreviousWorkingNight($night_id);
 
 ?>
 
@@ -507,7 +507,7 @@
 print "<input type=hidden name=night value=\"$night_id\">\n";
 print "<input type=hidden name=end value=\"$cur_date\">\n";
 
-$all_data=buildFileSizeTable($mysql_link, $machine_id, $night_id);
+$all_data=buildFileSizeTable($machine_id, $night_id);
 
 $formatted_num=number_format($all_data['Total Sum'][0],0,".",",");
 print "<b>Total size</b>: $formatted_num bytes<br>\n";
@@ -591,9 +591,9 @@
  ******************************************************/
 print"<h3><u>Program tests:</u></h3><br>\n";
 
-$today_results = GetDayResults($today_row['id'], $category_array, $mysql_link);
+$today_results = GetDayResults($today_row['id'], $category_array);
 if(isset($yesterday_row['id'])){
-  $yesterday_results = GetDayResults($yesterday_row['id'], $category_array, $mysql_link);
+  $yesterday_results = GetDayResults($yesterday_row['id'], $category_array);
   $percent_difference = CalculateChangeBetweenDays($yesterday_results, $today_results,.2);  
 }
 /********************** external table **********************/


Index: nightlytest-serverside/index.php
diff -u nightlytest-serverside/index.php:1.8 nightlytest-serverside/index.php:1.9
--- nightlytest-serverside/index.php:1.8	Thu Jul 27 16:02:42 2006
+++ nightlytest-serverside/index.php	Fri Sep  8 17:47:25 2006
@@ -38,7 +38,7 @@
 	print "\t\t<td></td>\n";
 print "\t</tr>";
 
-$result = getRecentTests("24",$mysql_link);
+$result = getRecentTests("24");
 $line=1;
 if(mysql_num_rows($result)==0){
 	print "\t<tr bgcolor='white'>";
@@ -55,7 +55,7 @@
 while($row = mysql_fetch_array($result)){
 	$cur_machine_id = $row['machine'];
 	$cur_night_id   = $row['id'];
-	$cur_machine_row = getMachineInfo($cur_machine_id,$mysql_link);
+	$cur_machine_row = getMachineInfo($cur_machine_id);
 	if(strcmp($cur_machine_row['nickname'], "")!=0){$machine_name = $cur_machine_row['nickname'];}
 	else{$machine_name = $cur_machine_row['name'];}
         
@@ -95,4 +95,4 @@
         </tr>
 </table>
 </body>
-</html>
\ No newline at end of file
+</html>


Index: nightlytest-serverside/individualfilesizegraph.php
diff -u nightlytest-serverside/individualfilesizegraph.php:1.3 nightlytest-serverside/individualfilesizegraph.php:1.4
--- nightlytest-serverside/individualfilesizegraph.php:1.3	Tue Aug  1 19:30:05 2006
+++ nightlytest-serverside/individualfilesizegraph.php	Fri Sep  8 17:47:25 2006
@@ -400,7 +400,7 @@
 print "\t\t<td>Date</td>\n";
 foreach ($files_arr as $m){	
   print "\t\t<td>$m</td>\n";
-  $file_data=get_file_history($mysql_link, $machine_id, $m);
+  $file_data=get_file_history($machine_id, $m);
   array_push($all_data, $file_data);
 }
 print "\t</tr>\n";


Index: nightlytest-serverside/individualgraph.php
diff -u nightlytest-serverside/individualgraph.php:1.2 nightlytest-serverside/individualgraph.php:1.3
--- nightlytest-serverside/individualgraph.php:1.2	Thu Aug 17 22:50:18 2006
+++ nightlytest-serverside/individualgraph.php	Fri Sep  8 17:47:25 2006
@@ -392,13 +392,13 @@
 print "<div id=\"dataTable\" style=\"display: none;\">\n";
 
 if(strcmp($start,"")!=0 && strcmp($end,"")!=0){
-    $history = buildResultsHistory($machine_id, $program,$measure,$mysql_link,$start,$end);
+    $history = buildResultsHistory($machine_id, $program,$measure,$start,$end);
 }
 else if(strcmp($start,"")!=0){
-    $history = buildResultsHistory($machine_id, $program,$measure,$mysql_link,$start);
+    $history = buildResultsHistory($machine_id, $program,$measure,$start);
 }
 else{
-    $history = buildResultsHistory($machine_id, $program,$measure,$mysql_link);
+    $history = buildResultsHistory($machine_id, $program,$measure);
 }
 
 print "<table border=1 cellspacing=0 cellpadding=6>\n";


Index: nightlytest-serverside/machine.php
diff -u nightlytest-serverside/machine.php:1.5 nightlytest-serverside/machine.php:1.6
--- nightlytest-serverside/machine.php:1.5	Thu Jul 27 14:29:35 2006
+++ nightlytest-serverside/machine.php	Fri Sep  8 17:47:25 2006
@@ -18,7 +18,7 @@
 $mysql_link=mysql_connect("127.0.0.1","llvm","ll2002vm") or die("Error: could not connect to database!\n");
 mysql_select_db("nightlytestresults");
 
-$row = getMachineInfo($machine,$mysql_link);
+$row = getMachineInfo($machine);
 $machine_name = $row['name'];
 if(strcmp($row['nickname'],"")!=0){
 	$machine_name=$row['nickname'];
@@ -87,7 +87,7 @@
 print "</table>\n<br>\n";
 
 
-$result = getNightsResource($machine,$mysql_link);
+$result = getNightsResource($machine);
 $recent=mysql_fetch_array($result);
 $recent_id=$recent['id'];
 $cur_date = $recent['added'];
@@ -97,8 +97,8 @@
 
 include("ProgramResults.php");
 if(is_numeric($recent_id) && is_numeric($old_id)){
-	$today_results = GetDayResults($recent_id, $category_array, $mysql_link);
-	$yesterday_results = GetDayResults($old_id, $category_array, $mysql_link);
+	$today_results = GetDayResults($recent_id, $category_array);
+	$yesterday_results = GetDayResults($old_id, $category_array);
 	$percent_difference = CalculateChangeBetweenDays($yesterday_results, $today_results);
 
 	/* note: $medium_change, $large_change, and $crazy_change are defined in ProgramResult.php */
@@ -179,7 +179,7 @@
 	echo "</td>";
 echo "</tr>";
 
-$result = getNightsResource($machine,$mysql_link);
+$result = getNightsResource($machine);
 $line=1;
 $row = mysql_fetch_array($result);
 $x=0;
@@ -453,4 +453,4 @@
 </table>
 
 </body>
-</html>
\ No newline at end of file
+</html>


Index: nightlytest-serverside/multiplemachinegraph.php
diff -u nightlytest-serverside/multiplemachinegraph.php:1.1.1.1 nightlytest-serverside/multiplemachinegraph.php:1.2
--- nightlytest-serverside/multiplemachinegraph.php:1.1.1.1	Wed Jul  5 15:56:33 2006
+++ nightlytest-serverside/multiplemachinegraph.php	Fri Sep  8 17:47:25 2006
@@ -50,8 +50,8 @@
 $mysql_link=mysql_connect("127.0.0.1","llvm","ll2002vm") or die("Error: could not connect to database!\n");
 mysql_select_db("nightlytestresults");
 
-$row = getMachineInfo($machine_id,$mysql_link);
-$today_row = getNightInfo($night_id,$mysql_link);
+$row = getMachineInfo($machine_id);
+$today_row = getNightInfo($night_id);
 $cur_date=$today_row['added'];
 
 ?>
@@ -88,4 +88,4 @@
 			
 
 </td></tr></table>
-</body></html>
\ No newline at end of file
+</body></html>


Index: nightlytest-serverside/multipleresultsgraph.php
diff -u nightlytest-serverside/multipleresultsgraph.php:1.1.1.1 nightlytest-serverside/multipleresultsgraph.php:1.2
--- nightlytest-serverside/multipleresultsgraph.php:1.1.1.1	Wed Jul  5 15:56:33 2006
+++ nightlytest-serverside/multipleresultsgraph.php	Fri Sep  8 17:47:25 2006
@@ -55,8 +55,8 @@
 $mysql_link=mysql_connect("127.0.0.1","llvm","ll2002vm") or die("Error: could not connect to database!\n");
 mysql_select_db("nightlytestresults");
 
-$row = getMachineInfo($machine_id,$mysql_link);
-$today_row = getNightInfo($night_id,$mysql_link);
+$row = getMachineInfo($machine_id);
+$today_row = getNightInfo($night_id);
 $cur_date=$today_row['added'];
 
 ?>
@@ -99,4 +99,4 @@
 			
 
 </td></tr></table>
-</body></html>
\ No newline at end of file
+</body></html>


Index: nightlytest-serverside/sidebar.php
diff -u nightlytest-serverside/sidebar.php:1.9 nightlytest-serverside/sidebar.php:1.10
--- nightlytest-serverside/sidebar.php:1.9	Thu Aug 17 22:50:18 2006
+++ nightlytest-serverside/sidebar.php	Fri Sep  8 17:47:25 2006
@@ -6,8 +6,8 @@
  *
  ******************************************************/
 if(isset($measure_arr) && isset($program_arr)){
-	$machine_row=getMachineInfo($machine,$mysql_link);
-	$today_row = getNightInfo($night,$mysql_link);
+	$machine_row=getMachineInfo($machine);
+	$today_row = getNightInfo($night);
 	$cur_date = $today_row['added'];
 
 	print "<a href=\"index.php\">Homepage</a><br><br>\n";
@@ -32,7 +32,7 @@
 	/********************** Creating list to future and past tests **********************/
 	
 	$next_stack = array();
-	$next_query = getNightsResource($machine,$mysql_link,$cur_date,"2020-12-30 01:01:01");
+	$next_query = getNightsResource($machine,$cur_date,"2020-12-30 01:01:01");
 	$x=0;
 	while($x<7 && $x<mysql_affected_rows()-1 && $next = mysql_fetch_array($next_query)){
 		array_push($next_stack, $next);
@@ -48,7 +48,7 @@
 	$date = preg_replace("/\s\d\d:\d\d:\d\d/","",$today_row['added']);
 	print "\t<li><h3><a href=\"test.php?machine=$machine&night=$night\">$date</a></h3>\n"; 
 	
-	$previous_query = getNightsResource($machine,$mysql_link,"2000-01-01 01:01:01","$cur_date");
+	$previous_query = getNightsResource($machine,"2000-01-01 01:01:01","$cur_date");
 	$x=0;
 	$prev=mysql_fetch_array($previous_query); //eliminates current date
 	while($x<7 && $prev=mysql_fetch_array($previous_query)){
@@ -71,8 +71,8 @@
  *
  ******************************************************/
 else if($machine!=-1 && $night !=-1){
-	$machine_row=getMachineInfo($machine,$mysql_link);
-	$today_row = getNightInfo($night,$mysql_link);
+	$machine_row=getMachineInfo($machine);
+	$today_row = getNightInfo($night);
 	$cur_date = $today_row['added'];
 
 	print "<a href=\"index.php\">Homepage</a><br><br>\n";
@@ -88,7 +88,7 @@
 	/********************** Creating list to future and past tests **********************/
 	
 	$next_stack = array();
-	$next_query = getNightsIDs($machine,$mysql_link,$cur_date,"2020-12-30 01:01:01","ASC");
+	$next_query = getNightsIDs($machine,$cur_date,"2020-12-30 01:01:01","ASC");
 	$next = mysql_fetch_array($next_query);
 	$x=0;
 	while($x<7 && $x<mysql_affected_rows()-1 && $next = mysql_fetch_array($next_query)){
@@ -105,7 +105,7 @@
 	$date = preg_replace("/\s\d\d:\d\d:\d\d/","",$today_row['added']);
 	print "\t<li><h3><a href=\"test.php?machine=$machine&night=$night\">$date</a></h3>\n"; 
 	
-	$previous_query = getNightsIDs($machine,$mysql_link,"2000-01-01 01:01:01","$cur_date");
+	$previous_query = getNightsIDs($machine,"2000-01-01 01:01:01","$cur_date");
 	$x=0;
 	$prev=mysql_fetch_array($previous_query); //eliminates current date
 	while($x<7 && $prev=mysql_fetch_array($previous_query)){
@@ -116,7 +116,7 @@
 	print "</ul>\n";
 	mysql_free_result($previous_query);
        
-	$next_query = getNightsIDs($machine,$mysql_link);
+	$next_query = getNightsIDs($machine);
 	print "<form method=GET action=\"test.php\">\n";
         print "<input type=hidden name=\"machine\" value=\"$machine\">\n";
 	print "<select name=night>\n";
@@ -146,7 +146,7 @@
 	print "<a href=\"index.php\">Homepage</a><br><br>\n";
 	print "Test dates:<br>\n<ul>\n";
 	$x=0;
-	$machine_nights = getNightsResource($machine, $mysql_link); 
+	$machine_nights = getNightsResource($machine); 
 	while($x<20 && $temp_row=mysql_fetch_array($machine_nights)){
 		$date = preg_replace("/\s\d\d:\d\d:\d\d/","",$temp_row['added']);
 		print "<li><a href=\"test.php?machine=$machine&night={$temp_row['id']}\">$date</a>\n";
@@ -155,7 +155,7 @@
 	print "</ul>\n";
 	mysql_free_result($machine_nights);	
 
-	$next_query = getNightsResource($machine,$mysql_link);
+	$next_query = getNightsResource($machine);
         print "<form method=GET action=\"test.php\">\n";
         print "<input type=hidden name=machine value=\"$machine\">\n";
         print "<select name=night>\n";
@@ -181,7 +181,7 @@
 else{ /*if($machine ==-1 && night ==-1)*/
 
 	print "<a href=\"index.php\">Homepage</a><br><br>\n";
-	$list_o_machines = getRecentMachineResource($mysql_link);
+	$list_o_machines = getRecentMachineResource();
 	print "Test Machines With<br> Recent Submissions:<br>\n<ul>\n";
 	while($temp_row = mysql_fetch_array($list_o_machines)){
 		if(strcmp($temp_row['nickname'],"")==0){
@@ -195,7 +195,7 @@
 	mysql_free_result($list_o_machines);
 
 	print "<a href='testers.php'>All Test Machines:</a><br>\n<ul>\n";
-	$list_o_machines = getMachineResource($mysql_link);
+	$list_o_machines = getMachineResource();
         while($temp_row = mysql_fetch_array($list_o_machines)){
                 if(strcmp($temp_row['nickname'],"")==0){
                         print "<li><a href=\"machine.php?machine={$temp_row['id']}\">{$temp_row['name']}</a>\n";


Index: nightlytest-serverside/test.php
diff -u nightlytest-serverside/test.php:1.22 nightlytest-serverside/test.php:1.23
--- nightlytest-serverside/test.php:1.22	Fri Sep  8 17:27:47 2006
+++ nightlytest-serverside/test.php	Fri Sep  8 17:47:25 2006
@@ -30,11 +30,11 @@
 $mysql_link=mysql_connect("127.0.0.1","llvm","ll2002vm") or die("Error: could not connect to database!\n");
 mysql_select_db("nightlytestresults");
 
-$row = getMachineInfo($machine_id,$mysql_link);
-$today_row = getNightInfo($night_id,$mysql_link);
+$row = getMachineInfo($machine_id);
+$today_row = getNightInfo($night_id);
 $cur_date=$today_row['added'];
 
-$today_query = getSuccessfulNightsHistory($machine_id,$mysql_link,$night_id);
+$today_query = getSuccessfulNightsHistory($machine_id,$night_id);
 $today_row = mysql_fetch_array($today_query);
 $yesterday_row = mysql_fetch_array($today_query);
 $oldday_row = mysql_fetch_array($today_query);
@@ -445,7 +445,7 @@
 
 print"<h3><u>CVS information:</u></h3><br>\n";
 
-$row = getNightInfo($night_id,$mysql_link);
+$row = getNightInfo($night_id);
 $com_users = $row['cvs_usersadd'];
 $co_users  = $row['cvs_usersco'];
 $com_users = str_replace("\n","<br>",$com_users);
@@ -514,7 +514,7 @@
  * Printing file size information
  *
  ******************************************************/
-$all_data=buildFileSizeTable($mysql_link, $machine_id, $night_id);
+$all_data=buildFileSizeTable($machine_id, $night_id);
 
 $num_sig_changes=0;
 foreach (array_keys($all_data) as $d){
@@ -613,13 +613,13 @@
  *
  ******************************************************/
 
-$today_results = GetDayResults($today_row['id'], $category_array, $mysql_link);
+$today_results = GetDayResults($today_row['id'], $category_array);
 if(isset($yesterday_row['id'])){
-  $yesterday_results = GetDayResults($yesterday_row['id'], $category_array, $mysql_link);
+  $yesterday_results = GetDayResults($yesterday_row['id'], $category_array);
   $percent_difference = CalculateChangeBetweenDays($yesterday_results, $today_results, .2);
 }
 if(isset($oldday_row['id'])){
-  $oldday_results = GetDayResults($oldday_row['id'], $category_array, $mysql_link);
+  $oldday_results = GetDayResults($oldday_row['id'], $category_array);
   $twoday_difference = CalculateChangeBetweenDays($oldday_results, $today_results, .01);
 }
 


Index: nightlytest-serverside/testers.php
diff -u nightlytest-serverside/testers.php:1.1.1.1 nightlytest-serverside/testers.php:1.2
--- nightlytest-serverside/testers.php:1.1.1.1	Wed Jul  5 15:56:34 2006
+++ nightlytest-serverside/testers.php	Fri Sep  8 17:47:25 2006
@@ -42,10 +42,10 @@
         print "\t\t<td>Build status of last test</td>\n";
 print "\t</tr>\n";
 
-$result = getMachineResource($mysql_link);
+$result = getMachineResource();
 $line=1;
 while($row = mysql_fetch_array($result)){
-	$query = getNightsResource($row['id'],$mysql_link);
+	$query = getNightsResource($row['id']);
 	$latest_test = mysql_fetch_array($query);
 	mysql_free_result($query);      
 
@@ -74,4 +74,4 @@
 </td></tr></table>
 
 </body>
-</html>
\ No newline at end of file
+</html>





From jlaskey at apple.com  Fri Sep  8 17:55:38 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Fri, 8 Sep 2006 17:55:38 -0500
Subject: [llvm-commits] CVS: nightlytest-serverside/test.php
Message-ID: <200609082255.k88MtcdE024947@zion.cs.uiuc.edu>



Changes in directory nightlytest-serverside:

test.php updated: 1.23 -> 1.24
---
Log message:

reuse code for e-mail report #8

---
Diffs of the changes:  (+17 -0)

 test.php |   17 +++++++++++++++++
 1 files changed, 17 insertions(+)


Index: nightlytest-serverside/test.php
diff -u nightlytest-serverside/test.php:1.23 nightlytest-serverside/test.php:1.24
--- nightlytest-serverside/test.php:1.23	Fri Sep  8 17:47:25 2006
+++ nightlytest-serverside/test.php	Fri Sep  8 17:55:24 2006
@@ -186,6 +186,23 @@
 print "$newly_failing_tests<br><br>\n";
 print "</div><br><br>\n";
 
+
+/*****************************************************
+ *
+ * Testing email report.
+ *
+ ******************************************************/
+$email = htmlifyTestResults(getEmailReport($night_id, $previous_succesful_id));
+$disp="";
+$sign="(+)";
+
+print "<font size=\"-1\"><a href=\"javascript://\"onclick=\"toggleLayer('testEmail');\", id=\"testEmail_\">$sign Test Email</a></font>\n";
+print "<div id=\"testEmail\" style=\"display: $disp;\" class=\"hideable\">\n";
+print"<h3><u>Test Email:</u></h3>\n";
+print"$email\n";
+print "</div><br><br>\n";
+
+
 /*****************************************************
  *
  * Printing failures in test suite





From isanbard at gmail.com  Fri Sep  8 17:56:00 2006
From: isanbard at gmail.com (Bill Wendling)
Date: Fri, 8 Sep 2006 17:56:00 -0500
Subject: [llvm-commits] CVS:
	llvm-test/External/SPEC/CINT2006/403.gcc/Makefile
Message-ID: <200609082256.k88Mu0sZ024967@zion.cs.uiuc.edu>



Changes in directory llvm-test/External/SPEC/CINT2006/403.gcc:

Makefile updated: 1.2 -> 1.3
---
Log message:

The -DINLINE=__inline__ flag is needed.


---
Diffs of the changes:  (+3 -1)

 Makefile |    4 +++-
 1 files changed, 3 insertions(+), 1 deletion(-)


Index: llvm-test/External/SPEC/CINT2006/403.gcc/Makefile
diff -u llvm-test/External/SPEC/CINT2006/403.gcc/Makefile:1.2 llvm-test/External/SPEC/CINT2006/403.gcc/Makefile:1.3
--- llvm-test/External/SPEC/CINT2006/403.gcc/Makefile:1.2	Fri Sep  1 20:30:39 2006
+++ llvm-test/External/SPEC/CINT2006/403.gcc/Makefile	Fri Sep  8 17:55:45 2006
@@ -6,7 +6,7 @@
 
 LEVEL = ../../../..
 
-include ../../Makefile.spec2006
+CPPFLAGS += -DSPEC_CPU_MACOSX -DINLINE=__inline__
 
 ifeq ($(OS),Darwin)
   CPPFLAGS += -DSPEC_CPU_MACOSX
@@ -16,6 +16,8 @@
   CPPFLAGS += -DHOST_WORDS_BIG_ENDIAN
 endif
 
+include ../../Makefile.spec2006
+
 ifeq ($(RUN_TYPE),test)
   RUN_OPTIONS      = cccp.i -o cccp.s
   STDOUT_FILENAME := cccp.s





From jlaskey at apple.com  Fri Sep  8 17:56:36 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Fri, 8 Sep 2006 17:56:36 -0500
Subject: [llvm-commits] CVS: nightlytest-serverside/test.php
Message-ID: <200609082256.k88Muals025038@zion.cs.uiuc.edu>



Changes in directory nightlytest-serverside:

test.php updated: 1.24 -> 1.25
---
Log message:

reuse code for e-mail report #9

---
Diffs of the changes:  (+0 -16)

 test.php |   16 ----------------
 1 files changed, 16 deletions(-)


Index: nightlytest-serverside/test.php
diff -u nightlytest-serverside/test.php:1.24 nightlytest-serverside/test.php:1.25
--- nightlytest-serverside/test.php:1.24	Fri Sep  8 17:55:24 2006
+++ nightlytest-serverside/test.php	Fri Sep  8 17:56:22 2006
@@ -189,22 +189,6 @@
 
 /*****************************************************
  *
- * Testing email report.
- *
- ******************************************************/
-$email = htmlifyTestResults(getEmailReport($night_id, $previous_succesful_id));
-$disp="";
-$sign="(+)";
-
-print "<font size=\"-1\"><a href=\"javascript://\"onclick=\"toggleLayer('testEmail');\", id=\"testEmail_\">$sign Test Email</a></font>\n";
-print "<div id=\"testEmail\" style=\"display: $disp;\" class=\"hideable\">\n";
-print"<h3><u>Test Email:</u></h3>\n";
-print"$email\n";
-print "</div><br><br>\n";
-
-
-/*****************************************************
- *
  * Printing failures in test suite
  *
  ******************************************************/





From jlaskey at apple.com  Fri Sep  8 18:09:15 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Fri, 8 Sep 2006 18:09:15 -0500
Subject: [llvm-commits] CVS: nightlytest-serverside/EmailReport.php
Message-ID: <200609082309.k88N9FLo025303@zion.cs.uiuc.edu>



Changes in directory nightlytest-serverside:

EmailReport.php added (r1.1)
---
Log message:

reuse code for e-mail report #10

---
Diffs of the changes:  (+61 -0)

 EmailReport.php |   61 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 61 insertions(+)


Index: nightlytest-serverside/EmailReport.php
diff -c /dev/null nightlytest-serverside/EmailReport.php:1.1
*** /dev/null	Fri Sep  8 18:09:11 2006
--- nightlytest-serverside/EmailReport.php	Fri Sep  8 18:09:01 2006
***************
*** 0 ****
--- 1,61 ----
+ <?php
+ 
+ if(!isset($HTTP_GET_VARS['machine']) || !is_numeric($HTTP_GET_VARS['machine'])){
+         print "Error: Incorrect URL!\n";
+         die();
+ }
+ $machine_id = $HTTP_GET_VARS['machine'];
+ 
+ if(!isset($HTTP_GET_VARS['night']) || !is_numeric($HTTP_GET_VARS['night'])){
+         print "Error: Incorrect URL!\n";
+         die();
+ }
+ $night_id = $HTTP_GET_VARS['night'];
+ 
+ 
+ if(!(include "NightlyTester.php")){
+         print "Error: could not load necessary files!\n";
+         die();
+ }
+ 
+ if(!(include"ProgramResults.php")){
+         print "Error: could not load necessary files!\n";
+         die();
+ }
+ 
+ $mysql_link=mysql_connect("127.0.0.1","llvm","ll2002vm") or die("Error: could not connect to database!\n");
+ mysql_select_db("nightlytestresults");
+ 
+ $row = getMachineInfo($machine_id);
+ $today_row = getNightInfo($night_id);
+ $cur_date=$today_row['added'];
+ 
+ $today_query = getSuccessfulNightsHistory($machine_id,$night_id);
+ $today_row = mysql_fetch_array($today_query);
+ $yesterday_row = mysql_fetch_array($today_query);
+ mysql_free_result($today_query);
+ $previous_succesful_id = $yesterday_row['id'];
+ 
+ $email = htmlifyTestResults(getEmailReport($night_id, $previous_succesful_id));
+ 
+ ?>
+ <html>
+ <head>
+ <title>Testing Email Report</title>
+ <STYLE TYPE="text/css">
+ <!--
+   @import url(style.css);
+ -->
+ </STYLE>
+ </head>
+ <body>
+ <?php
+ print $email;
+ ?>
+ 
+ </body>
+ <?php
+ 
+ mysql_close($mysql_link);
+ ?>
+ 





From jlaskey at apple.com  Fri Sep  8 18:45:28 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Fri, 8 Sep 2006 18:45:28 -0500
Subject: [llvm-commits] CVS: nightlytest-serverside/EmailReport.php
Message-ID: <200609082345.k88NjSPc025900@zion.cs.uiuc.edu>



Changes in directory nightlytest-serverside:

EmailReport.php updated: 1.1 -> 1.2
---
Log message:

reuse code for e-mail report #11

---
Diffs of the changes:  (+12 -28)

 EmailReport.php |   39 ++++++++++++---------------------------
 1 files changed, 12 insertions(+), 27 deletions(-)


Index: nightlytest-serverside/EmailReport.php
diff -u nightlytest-serverside/EmailReport.php:1.1 nightlytest-serverside/EmailReport.php:1.2
--- nightlytest-serverside/EmailReport.php:1.1	Fri Sep  8 18:09:01 2006
+++ nightlytest-serverside/EmailReport.php	Fri Sep  8 18:45:13 2006
@@ -1,26 +1,26 @@
 <?php
 
-if(!isset($HTTP_GET_VARS['machine']) || !is_numeric($HTTP_GET_VARS['machine'])){
-        print "Error: Incorrect URL!\n";
-        die();
+$machine_id = $argv[0];
+if(!isset($machine_id) || !is_numeric($machine_id)){
+  print "Incorrect machine id\n";
+  die();
 }
-$machine_id = $HTTP_GET_VARS['machine'];
 
-if(!isset($HTTP_GET_VARS['night']) || !is_numeric($HTTP_GET_VARS['night'])){
-        print "Error: Incorrect URL!\n";
-        die();
+$night_id = $argv[1];
+if(!isset($night_id) || !is_numeric($night_id)){
+  print "Incorrect night id\n";
+  die();
 }
-$night_id = $HTTP_GET_VARS['night'];
 
 
 if(!(include "NightlyTester.php")){
-        print "Error: could not load necessary files!\n";
-        die();
+  print "Error: could not load necessary files!\n";
+  die();
 }
 
 if(!(include"ProgramResults.php")){
-        print "Error: could not load necessary files!\n";
-        die();
+  print "Error: could not load necessary files!\n";
+  die();
 }
 
 $mysql_link=mysql_connect("127.0.0.1","llvm","ll2002vm") or die("Error: could not connect to database!\n");
@@ -38,23 +38,7 @@
 
 $email = htmlifyTestResults(getEmailReport($night_id, $previous_succesful_id));
 
-?>
-<html>
-<head>
-<title>Testing Email Report</title>
-<STYLE TYPE="text/css">
-<!--
-  @import url(style.css);
--->
-</STYLE>
-</head>
-<body>
-<?php
 print $email;
-?>
-
-</body>
-<?php
 
 mysql_close($mysql_link);
 ?>





From jlaskey at apple.com  Fri Sep  8 18:49:27 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Fri, 8 Sep 2006 18:49:27 -0500
Subject: [llvm-commits] CVS: nightlytest-serverside/EmailReport.php
Message-ID: <200609082349.k88NnR5v026015@zion.cs.uiuc.edu>



Changes in directory nightlytest-serverside:

EmailReport.php updated: 1.2 -> 1.3
---
Log message:

reuse code for e-mail report #12

---
Diffs of the changes:  (+11 -6)

 EmailReport.php |   17 +++++++++++------
 1 files changed, 11 insertions(+), 6 deletions(-)


Index: nightlytest-serverside/EmailReport.php
diff -u nightlytest-serverside/EmailReport.php:1.2 nightlytest-serverside/EmailReport.php:1.3
--- nightlytest-serverside/EmailReport.php:1.2	Fri Sep  8 18:45:13 2006
+++ nightlytest-serverside/EmailReport.php	Fri Sep  8 18:49:13 2006
@@ -1,24 +1,29 @@
 <?php
 
-$machine_id = $argv[0];
-if(!isset($machine_id) || !is_numeric($machine_id)){
+if ($argc != 3) {
+  print "Not enough arguments\n";
+  die();
+}
+
+$machine_id = $argv[1];
+if(!is_numeric($machine_id)) {
   print "Incorrect machine id\n";
   die();
 }
 
-$night_id = $argv[1];
-if(!isset($night_id) || !is_numeric($night_id)){
+$night_id = $argv[2];
+if(!is_numeric($night_id)) {
   print "Incorrect night id\n";
   die();
 }
 
 
-if(!(include "NightlyTester.php")){
+if(!(include "NightlyTester.php")) {
   print "Error: could not load necessary files!\n";
   die();
 }
 
-if(!(include"ProgramResults.php")){
+if(!(include"ProgramResults.php")) {
   print "Error: could not load necessary files!\n";
   die();
 }





From jlaskey at apple.com  Fri Sep  8 18:55:06 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Fri, 8 Sep 2006 18:55:06 -0500
Subject: [llvm-commits] CVS: nightlytest-serverside/NightlyTestAccept.cgi
	test.php
Message-ID: <200609082355.k88Nt6Qs026161@zion.cs.uiuc.edu>



Changes in directory nightlytest-serverside:

NightlyTestAccept.cgi updated: 1.55 -> 1.56
test.php updated: 1.25 -> 1.26
---
Log message:

reuse code for e-mail report #13

---
Diffs of the changes:  (+3 -50)

 NightlyTestAccept.cgi |   51 +-------------------------------------------------
 test.php              |    2 -
 2 files changed, 3 insertions(+), 50 deletions(-)


Index: nightlytest-serverside/NightlyTestAccept.cgi
diff -u nightlytest-serverside/NightlyTestAccept.cgi:1.55 nightlytest-serverside/NightlyTestAccept.cgi:1.56
--- nightlytest-serverside/NightlyTestAccept.cgi:1.55	Fri Sep  8 14:45:37 2006
+++ nightlytest-serverside/NightlyTestAccept.cgi	Fri Sep  8 18:54:52 2006
@@ -792,39 +792,6 @@
     $program_hash{$key}=1;
 }
 
-my ($num_removed, $num_added, $num_new_passing, $num_new_failing)=0;
-my ($removed, $added, $passing, $failing) = "";
-my $j = $dbh->prepare("SELECT program, measure, result FROM tests WHERE ".
-                      "night=$prev_night");
-$j->execute;
-while(my @row=$j->fetchrow_array){
-    my $key = $row[1]." - ".$row[0];
-    if($result_hash{$key} and $result_hash{$key} ne $row[2] and
-       $row[2] eq "PASS"){
-	$failing .= "changed: from $row[2] to $result_hash{$key} - $key\n";
-	$num_new_failing++;
-    }
-    if($result_hash{$key} and $result_hash{$key} ne $row[2] and 
-       $result_hash{$key} eq "PASS" ){
-        $passing .= "changed: from $row[2] to $result_hash{$key} - $key\n";
-        $num_new_passing++;
-    }
-
-    if(!$program_hash{$key}){
-        $removed .= "REMOVED: $key\n";
-        $num_removed++;
-    }
-    else{
-        $program_hash{$key}++;
-    }
-}
-foreach $x(keys(%program_hash)){
-    if($program_hash{$x}==1){
-        $added .= "ADDED: $x\n";
-        $num_added++;
-    }
-}
-
 ################################################################################
 #
 # Sending email to nightly test email archive
@@ -837,23 +804,9 @@
 $email .= "Nickname: $nickname\n";
 $email .= "Buildstatus: $buildstatus\n";
 
+
 if($buildstatus eq "OK") {
-  if ($passing eq "") {
-    $passing = "None";
-  } 
-  $email .= "\nNew Test Passes: $passing\n";
-  if ($failing eq "") {
-    $failing = "None";
-  } 
-  $email .= "\nNew Test Failures: $failing\n";
-  if ($added eq "") {
-    $added = "None";
-  } 
-  $email .= "\nAdded Tests: $added\n";
-  if ($removed eq "") {
-    $removed= "None";
-  } 
-  $email .= "\nRemoved Tests: $removed\n";
+  $email .= `php Emailreport.php $machine_id $night_id`;
 
   $email .= "\nSignificant changes in test results:\n";
   foreach my $meas(keys(%output_big_changes)){


Index: nightlytest-serverside/test.php
diff -u nightlytest-serverside/test.php:1.25 nightlytest-serverside/test.php:1.26
--- nightlytest-serverside/test.php:1.25	Fri Sep  8 17:56:22 2006
+++ nightlytest-serverside/test.php	Fri Sep  8 18:54:52 2006
@@ -218,7 +218,7 @@
 if($delta_exppass==0 && $delta_expfail==0 && 
    $delta_unexpfail==0 && strcmp($unexpected_failures,"")===0){
   $disp="none";
-        $sign="(-)";
+  $sign="(-)";
 }
 else{
   $disp="";





From jlaskey at apple.com  Fri Sep  8 19:13:18 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Fri, 8 Sep 2006 19:13:18 -0500
Subject: [llvm-commits] CVS: nightlytest-serverside/EmailReport.php
Message-ID: <200609090013.k890DIpv026517@zion.cs.uiuc.edu>



Changes in directory nightlytest-serverside:

EmailReport.php updated: 1.3 -> 1.4
---
Log message:

reuse code for e-mail report #14

---
Diffs of the changes:  (+1 -1)

 EmailReport.php |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: nightlytest-serverside/EmailReport.php
diff -u nightlytest-serverside/EmailReport.php:1.3 nightlytest-serverside/EmailReport.php:1.4
--- nightlytest-serverside/EmailReport.php:1.3	Fri Sep  8 18:49:13 2006
+++ nightlytest-serverside/EmailReport.php	Fri Sep  8 19:13:04 2006
@@ -41,7 +41,7 @@
 mysql_free_result($today_query);
 $previous_succesful_id = $yesterday_row['id'];
 
-$email = htmlifyTestResults(getEmailReport($night_id, $previous_succesful_id));
+$email = getEmailReport($night_id, $previous_succesful_id);
 
 print $email;
 





From lattner at cs.uiuc.edu  Fri Sep  8 19:20:41 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Fri, 8 Sep 2006 19:20:41 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Message-ID: <200609090020.k890Kfn5026776@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.390 -> 1.391
---
Log message:

Allow targets to custom lower expanded BIT_CONVERT's


---
Diffs of the changes:  (+15 -2)

 LegalizeDAG.cpp |   17 +++++++++++++++--
 1 files changed, 15 insertions(+), 2 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.390 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.391
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.390	Fri Sep  1 13:17:58 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Fri Sep  8 19:20:27 2006
@@ -4457,8 +4457,21 @@
     break;
     
   case ISD::BIT_CONVERT: {
-    SDOperand Tmp = ExpandBIT_CONVERT(Node->getValueType(0), 
-                                      Node->getOperand(0));
+    SDOperand Tmp;
+    if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
+      // If the target wants to, allow it to lower this itself.
+      switch (getTypeAction(Node->getOperand(0).getValueType())) {
+      case Expand: assert(0 && "cannot expand FP!");
+      case Legal:   Tmp = LegalizeOp(Node->getOperand(0)); break;
+      case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
+      }
+      Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
+    }
+
+    // Turn this into a load/store pair by default.
+    if (Tmp.Val == 0)
+      Tmp = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
+    
     ExpandOp(Tmp, Lo, Hi);
     break;
   }





From jlaskey at apple.com  Fri Sep  8 19:22:23 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Fri, 8 Sep 2006 19:22:23 -0500
Subject: [llvm-commits] CVS: nightlytest-serverside/EmailReport.php
Message-ID: <200609090022.k890MN6S026863@zion.cs.uiuc.edu>



Changes in directory nightlytest-serverside:

EmailReport.php updated: 1.4 -> 1.5
---
Log message:

reuse code for e-mail report #15

---
Diffs of the changes:  (+2 -0)

 EmailReport.php |    2 ++
 1 files changed, 2 insertions(+)


Index: nightlytest-serverside/EmailReport.php
diff -u nightlytest-serverside/EmailReport.php:1.4 nightlytest-serverside/EmailReport.php:1.5
--- nightlytest-serverside/EmailReport.php:1.4	Fri Sep  8 19:13:04 2006
+++ nightlytest-serverside/EmailReport.php	Fri Sep  8 19:22:09 2006
@@ -41,6 +41,8 @@
 mysql_free_result($today_query);
 $previous_succesful_id = $yesterday_row['id'];
 
+$new_schema_id = 684;
+
 $email = getEmailReport($night_id, $previous_succesful_id);
 
 print $email;





From jlaskey at apple.com  Fri Sep  8 19:24:18 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Fri, 8 Sep 2006 19:24:18 -0500
Subject: [llvm-commits] CVS: nightlytest-serverside/EmailReport.php
	ProgramResults.php
Message-ID: <200609090024.k890OITm026957@zion.cs.uiuc.edu>



Changes in directory nightlytest-serverside:

EmailReport.php updated: 1.5 -> 1.6
ProgramResults.php updated: 1.45 -> 1.46
---
Log message:

reuse code for e-mail report #16

---
Diffs of the changes:  (+6 -10)

 EmailReport.php    |    2 --
 ProgramResults.php |   14 ++++++--------
 2 files changed, 6 insertions(+), 10 deletions(-)


Index: nightlytest-serverside/EmailReport.php
diff -u nightlytest-serverside/EmailReport.php:1.5 nightlytest-serverside/EmailReport.php:1.6
--- nightlytest-serverside/EmailReport.php:1.5	Fri Sep  8 19:22:09 2006
+++ nightlytest-serverside/EmailReport.php	Fri Sep  8 19:24:04 2006
@@ -41,8 +41,6 @@
 mysql_free_result($today_query);
 $previous_succesful_id = $yesterday_row['id'];
 
-$new_schema_id = 684;
-
 $email = getEmailReport($night_id, $previous_succesful_id);
 
 print $email;


Index: nightlytest-serverside/ProgramResults.php
diff -u nightlytest-serverside/ProgramResults.php:1.45 nightlytest-serverside/ProgramResults.php:1.46
--- nightlytest-serverside/ProgramResults.php:1.45	Fri Sep  8 17:47:25 2006
+++ nightlytest-serverside/ProgramResults.php	Fri Sep  8 19:24:04 2006
@@ -29,8 +29,6 @@
 $large_decrease="#90FF90";
 $crazy_decrease="#20FF20";
 
-$new_schema_id = 684;
-
 $category_match=array("GCCAS","Bytecode","LLC\<br\>compile",
           "LLC-BETA\<br\>compile","JIT\<br\>codegen","GCC",
           "CBE","LLC","LLC-BETA","JIT","GCC\/\<br\>CBE",
@@ -422,7 +420,7 @@
  */
 function getFailures($night_id) {
   $result="";
-  if ($night_id >= $new_schema_id) {
+  if ($night_id >= 684) {
     $query = "SELECT * FROM tests WHERE night=$night_id AND result=\"FAIL\" ORDER BY program ASC";
     $program_query = mysql_query($query) or die (mysql_error());
     while($row = mysql_fetch_array($program_query)) {
@@ -452,7 +450,7 @@
  */
 function getUnexpectedFailures($night_id){
   $result="";
-  if($night_id<$new_schema_id){
+  if($night_id<684){
     $query = "SELECT unexpfail_tests FROM night WHERE id = $night_id";
     $program_query = mysql_query($query) or die (mysql_error());
     $row = mysql_fetch_array($program_query);
@@ -529,7 +527,7 @@
   }
   
   $result="";
-  if($cur_id<$new_schema_id){
+  if($cur_id<684){
     $query = "SELECT new_tests FROM night WHERE id = $cur_id";
     $program_query = mysql_query($query) or die (mysql_error());
     $row = mysql_fetch_array($program_query);
@@ -557,7 +555,7 @@
   }
   
   $result="";
-  if($cur_id<$new_schema_id){
+  if($cur_id<684){
     $query = "SELECT removed_tests FROM night WHERE id = $cur_id";
     $program_query = mysql_query($query) or die (mysql_error());
     $row = mysql_fetch_array($program_query);
@@ -637,7 +635,7 @@
   }
   
   $result="";
-  if($cur_id<$new_schema_id){
+  if($cur_id<684){
     $query = "SELECT newly_passing_tests FROM night WHERE id = $cur_id";
     $program_query = mysql_query($query) or die (mysql_error());
     $row = mysql_fetch_array($program_query);
@@ -665,7 +663,7 @@
   }
 
   $result="";
-  if($cur_id<$new_schema_id){
+  if($cur_id<684){
     $query = "SELECT newly_failing_tests FROM night WHERE id = $cur_id";
     $program_query = mysql_query($query) or die (mysql_error());
     $row = mysql_fetch_array($program_query);





From jlaskey at apple.com  Fri Sep  8 19:26:40 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Fri, 8 Sep 2006 19:26:40 -0500
Subject: [llvm-commits] CVS: nightlytest-serverside/NightlyTestAccept.cgi
Message-ID: <200609090026.k890Qewf027069@zion.cs.uiuc.edu>



Changes in directory nightlytest-serverside:

NightlyTestAccept.cgi updated: 1.56 -> 1.57
---
Log message:

reuse code for e-mail report #17

---
Diffs of the changes:  (+1 -1)

 NightlyTestAccept.cgi |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: nightlytest-serverside/NightlyTestAccept.cgi
diff -u nightlytest-serverside/NightlyTestAccept.cgi:1.56 nightlytest-serverside/NightlyTestAccept.cgi:1.57
--- nightlytest-serverside/NightlyTestAccept.cgi:1.56	Fri Sep  8 18:54:52 2006
+++ nightlytest-serverside/NightlyTestAccept.cgi	Fri Sep  8 19:26:26 2006
@@ -806,7 +806,7 @@
 
 
 if($buildstatus eq "OK") {
-  $email .= `php Emailreport.php $machine_id $night_id`;
+  $email .= `php -q Emailreport.php $machine_id $night_id`;
 
   $email .= "\nSignificant changes in test results:\n";
   foreach my $meas(keys(%output_big_changes)){





From isanbard at gmail.com  Fri Sep  8 20:40:13 2006
From: isanbard at gmail.com (Bill Wendling)
Date: Fri, 8 Sep 2006 20:40:13 -0500
Subject: [llvm-commits] CVS:
	llvm-test/External/SPEC/CINT2006/400.perlbench/Makefile
Message-ID: <200609090140.k891eD9f028400@zion.cs.uiuc.edu>



Changes in directory llvm-test/External/SPEC/CINT2006/400.perlbench:

Makefile updated: 1.5 -> 1.6
---
Log message:

Run only the "train" run. This is because the test.pl script the test
run runs outputs a timestamp to STDERR. However, the RunSafely.sh script
dups STDERR to STDOUT, making comparisons useless. If we want to in the
future, we could apply an ugly hack to make it actually work.


---
Diffs of the changes:  (+9 -1)

 Makefile |   10 +++++++++-
 1 files changed, 9 insertions(+), 1 deletion(-)


Index: llvm-test/External/SPEC/CINT2006/400.perlbench/Makefile
diff -u llvm-test/External/SPEC/CINT2006/400.perlbench/Makefile:1.5 llvm-test/External/SPEC/CINT2006/400.perlbench/Makefile:1.6
--- llvm-test/External/SPEC/CINT2006/400.perlbench/Makefile:1.5	Thu Sep  7 18:17:18 2006
+++ llvm-test/External/SPEC/CINT2006/400.perlbench/Makefile	Fri Sep  8 20:39:58 2006
@@ -7,9 +7,17 @@
 
 LEVEL = ../../../..
 
+# FIXME: The "test" run type outputs timestamps to STDERR. However, the
+# RunSafely.sh script dups STDERR to STDOUT. So testing the difference between
+# the two outputs would require ugly hacks. Let's just run the "train" right
+# now. If we need to run "test" later, we can apply some type of hack to get it
+# to work.
+
+RUN_TYPE := train
+
 include $(LEVEL)/Makefile.config
 
-CPPFLAGS += -DPERL_CORE
+CPPFLAGS += -DPERL_CORE -DI_TIME
 
 ifeq ($(OS),Darwin)
 ifeq ($(ARCH),PowerPC)





From isanbard at gmail.com  Fri Sep  8 21:34:46 2006
From: isanbard at gmail.com (Bill Wendling)
Date: Fri, 8 Sep 2006 21:34:46 -0500
Subject: [llvm-commits] CVS:
	llvm-test/External/SPEC/CINT2006/403.gcc/Makefile
Message-ID: <200609090234.k892YkZY029244@zion.cs.uiuc.edu>



Changes in directory llvm-test/External/SPEC/CINT2006/403.gcc:

Makefile updated: 1.3 -> 1.4
---
Log message:

The -DSPEC_CPU_MACOSX needs to be in the conditional section.


---
Diffs of the changes:  (+1 -1)

 Makefile |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm-test/External/SPEC/CINT2006/403.gcc/Makefile
diff -u llvm-test/External/SPEC/CINT2006/403.gcc/Makefile:1.3 llvm-test/External/SPEC/CINT2006/403.gcc/Makefile:1.4
--- llvm-test/External/SPEC/CINT2006/403.gcc/Makefile:1.3	Fri Sep  8 17:55:45 2006
+++ llvm-test/External/SPEC/CINT2006/403.gcc/Makefile	Fri Sep  8 21:34:29 2006
@@ -6,7 +6,7 @@
 
 LEVEL = ../../../..
 
-CPPFLAGS += -DSPEC_CPU_MACOSX -DINLINE=__inline__
+CPPFLAGS += -DINLINE=__inline__
 
 ifeq ($(OS),Darwin)
   CPPFLAGS += -DSPEC_CPU_MACOSX





From lattner at cs.uiuc.edu  Sat Sep  9 00:56:05 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 9 Sep 2006 00:56:05 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGNodes.h
Message-ID: <200609090556.k895u5C9032349@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

SelectionDAGNodes.h updated: 1.144 -> 1.145
---
Log message:

Implement new fpowi node


---
Diffs of the changes:  (+4 -3)

 SelectionDAGNodes.h |    7 ++++---
 1 files changed, 4 insertions(+), 3 deletions(-)


Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h
diff -u llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.144 llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.145
--- llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1.144	Sun Aug 27 03:07:55 2006
+++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h	Sat Sep  9 00:55:44 2006
@@ -361,9 +361,10 @@
     // conversions, but that is a noop, deleted by getNode().
     BIT_CONVERT,
     
-    // FNEG, FABS, FSQRT, FSIN, FCOS - Perform unary floating point negation,
-    // absolute value, square root, sine and cosine operations.
-    FNEG, FABS, FSQRT, FSIN, FCOS,
+    // FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI - Perform unary floating point
+    // negation, absolute value, square root, sine and cosine, and powi
+    // operations.
+    FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI,
     
     // Other operators.  LOAD and STORE have token chains as their first
     // operand, then the same operands as an LLVM load/store instruction, then a





From lattner at cs.uiuc.edu  Sat Sep  9 01:02:30 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 9 Sep 2006 01:02:30 -0500
Subject: [llvm-commits] CVS:
	llvm/test/Regression/C++Frontend/2006-09-08-powi.cpp
Message-ID: <200609090602.k8962UA0032531@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/C++Frontend:

2006-09-08-powi.cpp added (r1.1)
---
Log message:

(indirect) test for the __builtin_powi builtin which we now support.


---
Diffs of the changes:  (+7 -0)

 2006-09-08-powi.cpp |    7 +++++++
 1 files changed, 7 insertions(+)


Index: llvm/test/Regression/C++Frontend/2006-09-08-powi.cpp
diff -c /dev/null llvm/test/Regression/C++Frontend/2006-09-08-powi.cpp:1.1
*** /dev/null	Sat Sep  9 01:02:26 2006
--- llvm/test/Regression/C++Frontend/2006-09-08-powi.cpp	Sat Sep  9 01:02:16 2006
***************
*** 0 ****
--- 1,7 ----
+ // RUN: llvm-g++ -O3 -S -o - %s
+ 
+ #include <cmath>
+ 
+ double foo(double X, int Y) {
+   return std::pow(X, Y);
+ }





From lattner at cs.uiuc.edu  Sat Sep  9 01:03:44 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 9 Sep 2006 01:03:44 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
	SelectionDAG.cpp SelectionDAGISel.cpp
Message-ID: <200609090603.k8963i08032618@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.391 -> 1.392
SelectionDAG.cpp updated: 1.336 -> 1.337
SelectionDAGISel.cpp updated: 1.273 -> 1.274
---
Log message:

Implement the fpowi now by lowering to a libcall


---
Diffs of the changes:  (+16 -1)

 LegalizeDAG.cpp      |    9 ++++++++-
 SelectionDAG.cpp     |    1 +
 SelectionDAGISel.cpp |    7 +++++++
 3 files changed, 16 insertions(+), 1 deletion(-)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.391 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.392
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.391	Fri Sep  8 19:20:27 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Sat Sep  9 01:03:30 2006
@@ -2581,7 +2581,14 @@
       break;
     }
     break;
-    
+  case ISD::FPOWI: {
+    // We always lower FPOWI into a libcall.  No target support it yet.
+    const char *FnName = Node->getValueType(0) == MVT::f32
+                            ? "__powisf2" : "__powidf2";
+    SDOperand Dummy;
+    Result = ExpandLibCall(FnName, Node, Dummy);
+    break;
+  }
   case ISD::BIT_CONVERT:
     if (!isTypeLegal(Node->getOperand(0).getValueType())) {
       Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.336 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.337
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.336	Tue Aug 29 01:42:35 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Sat Sep  9 01:03:30 2006
@@ -2404,6 +2404,7 @@
   case ISD::FSQRT:  return "fsqrt";
   case ISD::FSIN:   return "fsin";
   case ISD::FCOS:   return "fcos";
+  case ISD::FPOWI:  return "fpowi";
 
   // Binary operators
   case ISD::ADD:    return "add";


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.273 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.274
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.273	Wed Sep  6 20:59:34 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	Sat Sep  9 01:03:30 2006
@@ -1620,6 +1620,13 @@
                              getValue(I.getOperand(1)).getValueType(),
                              getValue(I.getOperand(1))));
     return 0;
+  case Intrinsic::powi_f32:
+  case Intrinsic::powi_f64:
+    setValue(&I, DAG.getNode(ISD::FPOWI,
+                             getValue(I.getOperand(1)).getValueType(),
+                             getValue(I.getOperand(1)),
+                             getValue(I.getOperand(2))));
+    return 0;
   case Intrinsic::pcmarker: {
     SDOperand Tmp = getValue(I.getOperand(1));
     DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));





From lattner at cs.uiuc.edu  Sat Sep  9 01:17:26 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 9 Sep 2006 01:17:26 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/CBackend/Writer.cpp
Message-ID: <200609090617.k896HQVD000372@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/CBackend:

Writer.cpp updated: 1.268 -> 1.269
---
Log message:

Add cbe support for powi


---
Diffs of the changes:  (+10 -0)

 Writer.cpp |   10 ++++++++++
 1 files changed, 10 insertions(+)


Index: llvm/lib/Target/CBackend/Writer.cpp
diff -u llvm/lib/Target/CBackend/Writer.cpp:1.268 llvm/lib/Target/CBackend/Writer.cpp:1.269
--- llvm/lib/Target/CBackend/Writer.cpp:1.268	Sun Sep  3 23:14:57 2006
+++ llvm/lib/Target/CBackend/Writer.cpp	Sat Sep  9 01:17:12 2006
@@ -1693,6 +1693,8 @@
           case Intrinsic::longjmp:
           case Intrinsic::prefetch:
           case Intrinsic::dbg_stoppoint:
+          case Intrinsic::powi_f32:
+          case Intrinsic::powi_f64:
             // We directly implement these intrinsics
             break;
           default:
@@ -1785,6 +1787,14 @@
         writeOperand(I.getOperand(1));
         Out << ')';
         return;
+      case Intrinsic::powi_f32:
+      case Intrinsic::powi_f64:
+        Out << "__builtin_powi(";
+        writeOperand(I.getOperand(1));
+        Out << ", ";
+        writeOperand(I.getOperand(2));
+        Out << ')';
+        return;
       case Intrinsic::setjmp:
 #if defined(HAVE__SETJMP) && defined(HAVE__LONGJMP)
         Out << "_";  // Use _setjmp on systems that support it!





From jlaskey at apple.com  Sat Sep  9 04:11:04 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Sat, 9 Sep 2006 04:11:04 -0500
Subject: [llvm-commits] CVS: llvm/docs/TableGenFundamentals.html
Message-ID: <200609090911.k899B4s8010332@zion.cs.uiuc.edu>



Changes in directory llvm/docs:

TableGenFundamentals.html updated: 1.18 -> 1.19
---
Log message:

Missing anchor

---
Diffs of the changes:  (+2 -2)

 TableGenFundamentals.html |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/docs/TableGenFundamentals.html
diff -u llvm/docs/TableGenFundamentals.html:1.18 llvm/docs/TableGenFundamentals.html:1.19
--- llvm/docs/TableGenFundamentals.html:1.18	Fri Sep  1 17:01:36 2006
+++ llvm/docs/TableGenFundamentals.html	Sat Sep  9 04:10:37 2006
@@ -75,7 +75,7 @@
 </div>
 
 <!-- ======================================================================= -->
-<div class="doc_subsection"><a name="running">Basic concepts</a></div>
+<div class="doc_subsection"><a name="concepts">Basic concepts</a></div>
 
 <div class="doc_text">
 
@@ -639,7 +639,7 @@
 
   <a href="mailto:sabre at nondot.org">Chris Lattner</a><br>
   <a href="http://llvm.org">LLVM Compiler Infrastructure</a><br>
-  Last modified: $Date: 2006/09/01 22:01:36 $
+  Last modified: $Date: 2006/09/09 09:10:37 $
 </address>
 
 </body>





From jlaskey at apple.com  Sat Sep  9 14:28:29 2006
From: jlaskey at apple.com (Jim Laskey)
Date: Sat, 9 Sep 2006 14:28:29 -0500
Subject: [llvm-commits] CVS: nightlytest-serverside/NightlyTestAccept.cgi
Message-ID: <200609091928.k89JSTWH028939@zion.cs.uiuc.edu>



Changes in directory nightlytest-serverside:

NightlyTestAccept.cgi updated: 1.57 -> 1.58
---
Log message:

revert to old until security issues are addressed

---
Diffs of the changes:  (+49 -2)

 NightlyTestAccept.cgi |   51 ++++++++++++++++++++++++++++++++++++++++++++++++--
 1 files changed, 49 insertions(+), 2 deletions(-)


Index: nightlytest-serverside/NightlyTestAccept.cgi
diff -u nightlytest-serverside/NightlyTestAccept.cgi:1.57 nightlytest-serverside/NightlyTestAccept.cgi:1.58
--- nightlytest-serverside/NightlyTestAccept.cgi:1.57	Fri Sep  8 19:26:26 2006
+++ nightlytest-serverside/NightlyTestAccept.cgi	Sat Sep  9 14:28:15 2006
@@ -792,6 +792,39 @@
     $program_hash{$key}=1;
 }
 
+my ($num_removed, $num_added, $num_new_passing, $num_new_failing)=0;
+my ($removed, $added, $passing, $failing) = "";
+my $j = $dbh->prepare("SELECT program, measure, result FROM tests WHERE ".
+                      "night=$prev_night");
+$j->execute;
+while(my @row=$j->fetchrow_array){
+    my $key = $row[1]." - ".$row[0];
+    if($result_hash{$key} and $result_hash{$key} ne $row[2] and
+       $row[2] eq "PASS"){
+	$failing .= "changed: from $row[2] to $result_hash{$key} - $key\n";
+	$num_new_failing++;
+    }
+    if($result_hash{$key} and $result_hash{$key} ne $row[2] and 
+       $result_hash{$key} eq "PASS" ){
+        $passing .= "changed: from $row[2] to $result_hash{$key} - $key\n";
+        $num_new_passing++;
+    }
+
+    if(!$program_hash{$key}){
+        $removed .= "REMOVED: $key\n";
+        $num_removed++;
+    }
+    else{
+        $program_hash{$key}++;
+    }
+}
+foreach $x(keys(%program_hash)){
+    if($program_hash{$x}==1){
+        $added .= "ADDED: $x\n";
+        $num_added++;
+    }
+}
+
 ################################################################################
 #
 # Sending email to nightly test email archive
@@ -804,9 +837,23 @@
 $email .= "Nickname: $nickname\n";
 $email .= "Buildstatus: $buildstatus\n";
 
-
 if($buildstatus eq "OK") {
-  $email .= `php -q Emailreport.php $machine_id $night_id`;
+  if ($passing eq "") {
+    $passing = "None";
+  } 
+  $email .= "\nNew Test Passes: $passing\n";
+  if ($failing eq "") {
+    $failing = "None";
+  } 
+  $email .= "\nNew Test Failures: $failing\n";
+  if ($added eq "") {
+    $added = "None";
+  } 
+  $email .= "\nAdded Tests: $added\n";
+  if ($removed eq "") {
+    $removed= "None";
+  } 
+  $email .= "\nRemoved Tests: $removed\n";
 
   $email .= "\nSignificant changes in test results:\n";
   foreach my $meas(keys(%output_big_changes)){





From lattner at cs.uiuc.edu  Sat Sep  9 15:26:18 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 9 Sep 2006 15:26:18 -0500
Subject: [llvm-commits] CVS:
	llvm/test/Regression/Transforms/InstCombine/select.ll
Message-ID: <200609092026.k89KQIvg029890@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/Transforms/InstCombine:

select.ll updated: 1.10 -> 1.11
---
Log message:

new testcase


---
Diffs of the changes:  (+6 -0)

 select.ll |    6 ++++++
 1 files changed, 6 insertions(+)


Index: llvm/test/Regression/Transforms/InstCombine/select.ll
diff -u llvm/test/Regression/Transforms/InstCombine/select.ll:1.10 llvm/test/Regression/Transforms/InstCombine/select.ll:1.11
--- llvm/test/Regression/Transforms/InstCombine/select.ll:1.10	Sat Apr 23 10:31:03 2005
+++ llvm/test/Regression/Transforms/InstCombine/select.ll	Sat Sep  9 15:26:04 2006
@@ -148,3 +148,9 @@
 	%RV = seteq int* %R, null
 	ret bool %RV
 }
+
+int %test18(int %X, int %Y, bool %C) {
+	%R = select bool %C, int %X, int 0
+	%V = div int %Y, %R   ; div Y,X
+	ret int %V
+}





From lattner at cs.uiuc.edu  Sat Sep  9 15:26:46 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 9 Sep 2006 15:26:46 -0500
Subject: [llvm-commits] CVS:
	llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Message-ID: <200609092026.k89KQkSX029923@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/Scalar:

InstructionCombining.cpp updated: 1.501 -> 1.502
---
Log message:

Turn div X, (Cond ? Y : 0) -> div X, Y
This implements select.ll::test18.



---
Diffs of the changes:  (+68 -19)

 InstructionCombining.cpp |   87 ++++++++++++++++++++++++++++++++++++-----------
 1 files changed, 68 insertions(+), 19 deletions(-)


Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.501 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.502
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.501	Sun Aug 27 17:42:52 2006
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp	Sat Sep  9 15:26:32 2006
@@ -1894,19 +1894,42 @@
     }
   }
 
-  // If this is 'udiv X, (Cond ? C1, C2)' where C1&C2 are powers of two,
-  // transform this into: '(Cond ? (udiv X, C1) : (udiv X, C2))'.
-  if (SelectInst *SI = dyn_cast<SelectInst>(Op1))
+  // Handle div X, Cond?Y:Z
+  if (SelectInst *SI = dyn_cast<SelectInst>(Op1)) {
+    // div X, (Cond ? 0 : Y) -> div X, Y.  If the div and the select are in the
+    // same basic block, then we replace the select with Y, and the condition of
+    // the select with false (if the cond value is in the same BB).  If the
+    // select has uses other than the div, this allows them to be simplified
+    // also.
+    if (Constant *ST = dyn_cast<Constant>(SI->getOperand(1)))
+      if (ST->isNullValue()) {
+        Instruction *CondI = dyn_cast<Instruction>(SI->getOperand(0));
+        if (CondI && CondI->getParent() == I.getParent())
+          UpdateValueUsesWith(CondI, ConstantBool::False);
+        else if (I.getParent() != SI->getParent() || SI->hasOneUse())
+          I.setOperand(1, SI->getOperand(2));
+        else
+          UpdateValueUsesWith(SI, SI->getOperand(2));
+        return &I;
+      }
+    // Likewise for: div X, (Cond ? Y : 0) -> div X, Y
+    if (Constant *ST = dyn_cast<Constant>(SI->getOperand(2)))
+      if (ST->isNullValue()) {
+        Instruction *CondI = dyn_cast<Instruction>(SI->getOperand(0));
+        if (CondI && CondI->getParent() == I.getParent())
+          UpdateValueUsesWith(CondI, ConstantBool::True);
+        else if (I.getParent() != SI->getParent() || SI->hasOneUse())
+          I.setOperand(1, SI->getOperand(1));
+        else
+          UpdateValueUsesWith(SI, SI->getOperand(1));
+        return &I;
+      }
+
+    // If this is 'udiv X, (Cond ? C1, C2)' where C1&C2 are powers of two,
+    // transform this into: '(Cond ? (udiv X, C1) : (udiv X, C2))'.
     if (ConstantUInt *STO = dyn_cast<ConstantUInt>(SI->getOperand(1)))
       if (ConstantUInt *SFO = dyn_cast<ConstantUInt>(SI->getOperand(2))) {
-        if (STO->getValue() == 0) { // Couldn't be this argument.
-          I.setOperand(1, SFO);
-          return &I;
-        } else if (SFO->getValue() == 0) {
-          I.setOperand(1, STO);
-          return &I;
-        }
-
+        // STO == 0 and SFO == 0 handled above.
         uint64_t TVA = STO->getValue(), FVA = SFO->getValue();
         if (isPowerOf2_64(TVA) && isPowerOf2_64(FVA)) {
           unsigned TSA = Log2_64(TVA), FSA = Log2_64(FVA);
@@ -1922,6 +1945,7 @@
           return new SelectInst(SI->getOperand(0), TSI, FSI);
         }
       }
+  }
 
   // 0 / X == 0, we don't need to preserve faults!
   if (ConstantInt *LHS = dyn_cast<ConstantInt>(Op0))
@@ -2095,16 +2119,40 @@
     
     // If this is 'urem X, (Cond ? C1, C2)' where C1&C2 are powers of two,
     // transform this into: '(Cond ? (urem X, C1) : (urem X, C2))'.
-    if (SelectInst *SI = dyn_cast<SelectInst>(Op1))
+    if (SelectInst *SI = dyn_cast<SelectInst>(Op1)) {
+      // rem X, (Cond ? 0 : Y) -> rem X, Y.  If the rem and the select are in
+      // the same basic block, then we replace the select with Y, and the
+      // condition of the select with false (if the cond value is in the same
+      // BB).  If the select has uses other than the div, this allows them to be
+      // simplified also.
+      if (Constant *ST = dyn_cast<Constant>(SI->getOperand(1)))
+        if (ST->isNullValue()) {
+          Instruction *CondI = dyn_cast<Instruction>(SI->getOperand(0));
+          if (CondI && CondI->getParent() == I.getParent())
+            UpdateValueUsesWith(CondI, ConstantBool::False);
+          else if (I.getParent() != SI->getParent() || SI->hasOneUse())
+            I.setOperand(1, SI->getOperand(2));
+          else
+            UpdateValueUsesWith(SI, SI->getOperand(2));
+          return &I;
+        }
+      // Likewise for: rem X, (Cond ? Y : 0) -> rem X, Y
+      if (Constant *ST = dyn_cast<Constant>(SI->getOperand(2)))
+        if (ST->isNullValue()) {
+          Instruction *CondI = dyn_cast<Instruction>(SI->getOperand(0));
+          if (CondI && CondI->getParent() == I.getParent())
+            UpdateValueUsesWith(CondI, ConstantBool::True);
+          else if (I.getParent() != SI->getParent() || SI->hasOneUse())
+            I.setOperand(1, SI->getOperand(1));
+          else
+            UpdateValueUsesWith(SI, SI->getOperand(1));
+          return &I;
+        }
+
+      
       if (ConstantUInt *STO = dyn_cast<ConstantUInt>(SI->getOperand(1)))
         if (ConstantUInt *SFO = dyn_cast<ConstantUInt>(SI->getOperand(2))) {
-          if (STO->getValue() == 0) { // Couldn't be this argument.
-            I.setOperand(1, SFO);
-            return &I;
-          } else if (SFO->getValue() == 0) {
-            I.setOperand(1, STO);
-            return &I;
-          }
+          // STO == 0 and SFO == 0 handled above.
           
           if (isPowerOf2_64(STO->getValue()) && isPowerOf2_64(SFO->getValue())){
             Value *TrueAnd = InsertNewInstBefore(BinaryOperator::createAnd(Op0,
@@ -2114,6 +2162,7 @@
             return new SelectInst(SI->getOperand(0), TrueAnd, FalseAnd);
           }
         }
+    }
   }
   
   return 0;





From lattner at cs.uiuc.edu  Sat Sep  9 15:40:58 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 9 Sep 2006 15:40:58 -0500
Subject: [llvm-commits] CVS: llvm/lib/Transforms/IPO/InlineSimple.cpp
Message-ID: <200609092040.k89Kewuh030166@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/IPO:

InlineSimple.cpp updated: 1.73 -> 1.74
---
Log message:

Make inlining costs more accurate.


---
Diffs of the changes:  (+26 -3)

 InlineSimple.cpp |   29 ++++++++++++++++++++++++++---
 1 files changed, 26 insertions(+), 3 deletions(-)


Index: llvm/lib/Transforms/IPO/InlineSimple.cpp
diff -u llvm/lib/Transforms/IPO/InlineSimple.cpp:1.73 llvm/lib/Transforms/IPO/InlineSimple.cpp:1.74
--- llvm/lib/Transforms/IPO/InlineSimple.cpp:1.73	Sun Aug 27 17:42:52 2006
+++ llvm/lib/Transforms/IPO/InlineSimple.cpp	Sat Sep  9 15:40:44 2006
@@ -138,9 +138,32 @@
   // each instruction counts as 10.
   for (Function::const_iterator BB = F->begin(), E = F->end(); BB != E; ++BB) {
     for (BasicBlock::const_iterator II = BB->begin(), E = BB->end();
-         II != E; ++II)
-      if (!isa<DbgInfoIntrinsic>(II)) 
-        ++NumInsts;
+         II != E; ++II) {
+      if (isa<DbgInfoIntrinsic>(II)) continue;  // Debug intrinsics don't count.
+      
+      // Noop casts don't count.
+      if (const CastInst *CI = dyn_cast<CastInst>(II)) {
+        const Type *OpTy = CI->getOperand(0)->getType();
+        if (CI->getType()->isLosslesslyConvertibleTo(OpTy))
+          continue;
+        if ((isa<PointerType>(CI->getType()) && OpTy->isInteger()) ||
+            (isa<PointerType>(OpTy) && CI->getType()->isInteger()))
+          continue;  // ptr <-> int is *probably* noop cast.
+      } else if (const GetElementPtrInst *GEPI =
+                         dyn_cast<GetElementPtrInst>(II)) {
+        // If a GEP has all constant indices, it will probably be folded with
+        // a load/store.
+        bool AllConstant = true;
+        for (unsigned i = 1, e = GEPI->getNumOperands(); i != e; ++i)
+          if (!isa<ConstantInt>(GEPI->getOperand(i))) {
+            AllConstant = false;
+            break;
+          }
+        if (AllConstant) continue;
+      }
+      
+      ++NumInsts;
+    }
 
     ++NumBlocks;
   }





From lattner at cs.uiuc.edu  Sat Sep  9 16:30:27 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 9 Sep 2006 16:30:27 -0500
Subject: [llvm-commits] CVS: llvm/tools/gccld/GenerateCode.cpp
Message-ID: <200609092130.k89LURsw031000@zion.cs.uiuc.edu>



Changes in directory llvm/tools/gccld:

GenerateCode.cpp updated: 1.61 -> 1.62
---
Log message:

Move ipsccp pass earlier to clean up obvious bogosities


---
Diffs of the changes:  (+5 -3)

 GenerateCode.cpp |    8 +++++---
 1 files changed, 5 insertions(+), 3 deletions(-)


Index: llvm/tools/gccld/GenerateCode.cpp
diff -u llvm/tools/gccld/GenerateCode.cpp:1.61 llvm/tools/gccld/GenerateCode.cpp:1.62
--- llvm/tools/gccld/GenerateCode.cpp:1.61	Wed Aug 23 01:56:27 2006
+++ llvm/tools/gccld/GenerateCode.cpp	Sat Sep  9 16:30:13 2006
@@ -220,6 +220,11 @@
     // internal.
     addPass(Passes, createInternalizePass(Internalize));
 
+    // Propagate constants at call sites into the functions they call.  This
+    // opens opportunities for globalopt (and inlining) by substituting function
+    // pointers passed as arguments to direct uses of functions.
+    addPass(Passes, createIPSCCPPass());
+    
     // Now that we internalized some globals, see if we can hack on them!
     addPass(Passes, createGlobalOptimizerPass());
 
@@ -227,9 +232,6 @@
     // keep one copy of each constant...
     addPass(Passes, createConstantMergePass());
 
-    // Propagate constants at call sites into the functions they call.
-    addPass(Passes, createIPSCCPPass());
-
     // Remove unused arguments from functions...
     addPass(Passes, createDeadArgEliminationPass());
 





From lattner at cs.uiuc.edu  Sat Sep  9 17:02:39 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 9 Sep 2006 17:02:39 -0500
Subject: [llvm-commits] CVS:
	llvm/test/Regression/Transforms/InstCombine/hoist_instr.ll
Message-ID: <200609092202.k89M2d09031520@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/Transforms/InstCombine:

hoist_instr.ll added (r1.1)
---
Log message:

new testcase


---
Diffs of the changes:  (+16 -0)

 hoist_instr.ll |   16 ++++++++++++++++
 1 files changed, 16 insertions(+)


Index: llvm/test/Regression/Transforms/InstCombine/hoist_instr.ll
diff -c /dev/null llvm/test/Regression/Transforms/InstCombine/hoist_instr.ll:1.1
*** /dev/null	Sat Sep  9 17:02:35 2006
--- llvm/test/Regression/Transforms/InstCombine/hoist_instr.ll	Sat Sep  9 17:02:25 2006
***************
*** 0 ****
--- 1,16 ----
+ ; RUN: llvm-as < %s | opt -instcombine | llvm-dis | %prcontext div 1 | grep then:
+ 
+ ;; This tests that the div is hoisted into the then block.
+ 
+ int %foo(bool %C, int %A, int %B) {
+ entry:
+ 	br bool %C, label %then, label %endif
+ 
+ then:
+ 	br label %endif
+ 
+ endif:
+ 	%X = phi int [%A, %then], [15, %entry]
+ 	%Y = div int %X, 42
+ 	ret int %Y
+ }





From lattner at cs.uiuc.edu  Sat Sep  9 17:03:10 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sat, 9 Sep 2006 17:03:10 -0500
Subject: [llvm-commits] CVS:
	llvm/lib/Transforms/Scalar/InstructionCombining.cpp
Message-ID: <200609092203.k89M3A6U031555@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/Scalar:

InstructionCombining.cpp updated: 1.502 -> 1.503
---
Log message:

Implement Transforms/InstCombine/hoist_instr.ll


---
Diffs of the changes:  (+53 -13)

 InstructionCombining.cpp |   66 +++++++++++++++++++++++++++++++++++++----------
 1 files changed, 53 insertions(+), 13 deletions(-)


Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.502 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.503
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.502	Sat Sep  9 15:26:32 2006
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp	Sat Sep  9 17:02:56 2006
@@ -1330,14 +1330,31 @@
 Instruction *InstCombiner::FoldOpIntoPhi(Instruction &I) {
   PHINode *PN = cast<PHINode>(I.getOperand(0));
   unsigned NumPHIValues = PN->getNumIncomingValues();
-  if (!PN->hasOneUse() || NumPHIValues == 0 ||
-      !isa<Constant>(PN->getIncomingValue(0))) return 0;
+  if (!PN->hasOneUse() || NumPHIValues == 0) return 0;
 
-  // Check to see if all of the operands of the PHI are constants.  If not, we
-  // cannot do the transformation.
-  for (unsigned i = 1; i != NumPHIValues; ++i)
-    if (!isa<Constant>(PN->getIncomingValue(i)))
-      return 0;
+  // Check to see if all of the operands of the PHI are constants.  If there is
+  // one non-constant value, remember the BB it is.  If there is more than one
+  // bail out.
+  BasicBlock *NonConstBB = 0;
+  for (unsigned i = 0; i != NumPHIValues; ++i)
+    if (!isa<Constant>(PN->getIncomingValue(i))) {
+      if (NonConstBB) return 0;  // More than one non-const value.
+      NonConstBB = PN->getIncomingBlock(i);
+      
+      // If the incoming non-constant value is in I's block, we have an infinite
+      // loop.
+      if (NonConstBB == I.getParent())
+        return 0;
+    }
+  
+  // If there is exactly one non-constant value, we can insert a copy of the
+  // operation in that block.  However, if this is a critical edge, we would be
+  // inserting the computation one some other paths (e.g. inside a loop).  Only
+  // do this if the pred block is unconditionally branching into the phi block.
+  if (NonConstBB) {
+    BranchInst *BI = dyn_cast<BranchInst>(NonConstBB->getTerminator());
+    if (!BI || !BI->isUnconditional()) return 0;
+  }
 
   // Okay, we can do the transformation: create the new PHI node.
   PHINode *NewPN = new PHINode(I.getType(), I.getName());
@@ -1349,17 +1366,40 @@
   if (I.getNumOperands() == 2) {
     Constant *C = cast<Constant>(I.getOperand(1));
     for (unsigned i = 0; i != NumPHIValues; ++i) {
-      Constant *InV = cast<Constant>(PN->getIncomingValue(i));
-      NewPN->addIncoming(ConstantExpr::get(I.getOpcode(), InV, C),
-                         PN->getIncomingBlock(i));
+      Value *InV;
+      if (Constant *InC = dyn_cast<Constant>(PN->getIncomingValue(i))) {
+        InV = ConstantExpr::get(I.getOpcode(), InC, C);
+      } else {
+        assert(PN->getIncomingBlock(i) == NonConstBB);
+        if (BinaryOperator *BO = dyn_cast<BinaryOperator>(&I)) 
+          InV = BinaryOperator::create(BO->getOpcode(),
+                                       PN->getIncomingValue(i), C, "phitmp",
+                                       NonConstBB->getTerminator());
+        else if (ShiftInst *SI = dyn_cast<ShiftInst>(&I))
+          InV = new ShiftInst(SI->getOpcode(),
+                              PN->getIncomingValue(i), C, "phitmp",
+                              NonConstBB->getTerminator());
+        else
+          assert(0 && "Unknown binop!");
+        
+        WorkList.push_back(cast<Instruction>(InV));
+      }
+      NewPN->addIncoming(InV, PN->getIncomingBlock(i));
     }
   } else {
     assert(isa<CastInst>(I) && "Unary op should be a cast!");
     const Type *RetTy = I.getType();
     for (unsigned i = 0; i != NumPHIValues; ++i) {
-      Constant *InV = cast<Constant>(PN->getIncomingValue(i));
-      NewPN->addIncoming(ConstantExpr::getCast(InV, RetTy),
-                         PN->getIncomingBlock(i));
+      Value *InV;
+      if (Constant *InC = dyn_cast<Constant>(PN->getIncomingValue(i))) {
+        InV = ConstantExpr::getCast(InC, RetTy);
+      } else {
+        assert(PN->getIncomingBlock(i) == NonConstBB);
+        InV = new CastInst(PN->getIncomingValue(i), I.getType(), "phitmp",
+                           NonConstBB->getTerminator());
+        WorkList.push_back(cast<Instruction>(InV));
+      }
+      NewPN->addIncoming(InV, PN->getIncomingBlock(i));
     }
   }
   return ReplaceInstUsesWith(I, NewPN);





From nicholas at mxc.ca  Sat Sep  9 21:27:22 2006
From: nicholas at mxc.ca (Nick Lewycky)
Date: Sat, 9 Sep 2006 21:27:22 -0500
Subject: [llvm-commits] CVS:
	llvm/test/Regression/Transforms/PredicateSimplifier/2006-08-07-LeaderOffByOne.ll
Message-ID: <200609100227.k8A2RMO0002861@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/Transforms/PredicateSimplifier:

2006-08-07-LeaderOffByOne.ll added (r1.1)
---
Log message:

Replace EquivalenceClasses with a custom-built data structure. Many common
operations (like findProperties) should be faster, at the expense of
unionSets being slower in cases that are rare in practise.

Don't erase a dead Instruction. This fixes a memory corruption issue.



---
Diffs of the changes:  (+28 -0)

 2006-08-07-LeaderOffByOne.ll |   28 ++++++++++++++++++++++++++++
 1 files changed, 28 insertions(+)


Index: llvm/test/Regression/Transforms/PredicateSimplifier/2006-08-07-LeaderOffByOne.ll
diff -c /dev/null llvm/test/Regression/Transforms/PredicateSimplifier/2006-08-07-LeaderOffByOne.ll:1.1
*** /dev/null	Sat Sep  9 21:27:17 2006
--- llvm/test/Regression/Transforms/PredicateSimplifier/2006-08-07-LeaderOffByOne.ll	Sat Sep  9 21:27:07 2006
***************
*** 0 ****
--- 1,28 ----
+ ; RUN: llvm-as < %s | opt -predsimplify -disable-output
+ 
+ void %safe_strcpy(uint %size1) {
+ entry:
+ 	%tmp = seteq uint %size1, 0		; <bool> [#uses=1]
+ 	br bool %tmp, label %return, label %strlen.exit
+ 
+ strlen.exit:		; preds = %entry
+ 	%tmp = cast ulong 0 to uint		; <uint> [#uses=2]
+ 	%tmp6 = setlt uint %tmp, %size1		; <bool> [#uses=1]
+ 	br bool %tmp6, label %cond_true7, label %cond_false19
+ 
+ cond_true7:		; preds = %strlen.exit
+ 	%tmp9 = seteq uint %tmp, 0		; <bool> [#uses=1]
+ 	br bool %tmp9, label %cond_next15, label %cond_true10
+ 
+ cond_true10:		; preds = %cond_true7
+ 	ret void
+ 
+ cond_next15:		; preds = %cond_true7
+ 	ret void
+ 
+ cond_false19:		; preds = %strlen.exit
+ 	ret void
+ 
+ return:		; preds = %entry
+ 	ret void
+ }





From nicholas at mxc.ca  Sat Sep  9 21:27:22 2006
From: nicholas at mxc.ca (Nick Lewycky)
Date: Sat, 9 Sep 2006 21:27:22 -0500
Subject: [llvm-commits] CVS:
	llvm/lib/Transforms/Scalar/PredicateSimplifier.cpp
Message-ID: <200609100227.k8A2RM2o002866@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/Scalar:

PredicateSimplifier.cpp updated: 1.5 -> 1.6
---
Log message:

Replace EquivalenceClasses with a custom-built data structure. Many common
operations (like findProperties) should be faster, at the expense of
unionSets being slower in cases that are rare in practise.

Don't erase a dead Instruction. This fixes a memory corruption issue.



---
Diffs of the changes:  (+261 -135)

 PredicateSimplifier.cpp |  396 +++++++++++++++++++++++++++++++-----------------
 1 files changed, 261 insertions(+), 135 deletions(-)


Index: llvm/lib/Transforms/Scalar/PredicateSimplifier.cpp
diff -u llvm/lib/Transforms/Scalar/PredicateSimplifier.cpp:1.5 llvm/lib/Transforms/Scalar/PredicateSimplifier.cpp:1.6
--- llvm/lib/Transforms/Scalar/PredicateSimplifier.cpp:1.5	Sat Sep  2 14:40:37 2006
+++ llvm/lib/Transforms/Scalar/PredicateSimplifier.cpp	Sat Sep  9 21:27:07 2006
@@ -33,7 +33,6 @@
 #include "llvm/Constants.h"
 #include "llvm/Instructions.h"
 #include "llvm/Pass.h"
-#include "llvm/ADT/EquivalenceClasses.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/Analysis/Dominators.h"
@@ -42,6 +41,8 @@
 #include <iostream>
 using namespace llvm;
 
+typedef DominatorTree::Node DTNodeType;
+
 namespace {
   Statistic<>
   NumVarsReplaced("predsimplify", "Number of argument substitutions");
@@ -52,40 +53,167 @@
   Statistic<>
   NumBranches("predsimplify", "Number of branches made unconditional");
 
-  /// Used for choosing the canonical Value in a synonym set.
-  /// Leaves the better one in V1. Returns whether a swap took place.
-  static void order(Value *&V1, Value *&V2) {
-    if (isa<Constant>(V2)) {
-      if (!isa<Constant>(V1)) {
-        std::swap(V1, V2);
-        return;
-      }
-    } else if (isa<Argument>(V2)) {
-      if (!isa<Constant>(V1) && !isa<Argument>(V1)) {
-        std::swap(V1, V2);
-        return;
-      }
-    }
-    if (User *U1 = dyn_cast<User>(V1)) {
-      for (User::const_op_iterator I = U1->op_begin(), E = U1->op_end();
-           I != E; ++I) {
-        if (*I == V2) {
-          std::swap(V1, V2);
-          return;
+  /// Returns true if V1 is a better choice than V2. Note that it is
+  /// not a total ordering.
+  struct compare {
+    bool operator()(Value *V1, Value *V2) const {
+      if (isa<Constant>(V2)) {
+        if (!isa<Constant>(V1)) {
+          return true;
+        }
+      } else if (isa<Argument>(V2)) {
+        if (!isa<Constant>(V1) && !isa<Argument>(V1)) {
+          return true;
+        }
+      }
+      if (User *U1 = dyn_cast<User>(V1)) {
+        for (User::const_op_iterator I = U1->op_begin(), E = U1->op_end();
+             I != E; ++I) {
+          if (*I == V2) {
+            return true;
+          }
         }
       }
+      return false;
     }
-    return;
+  };
+
+  /// Used for choosing the canonical Value in a synonym set.
+  /// Leaves the better one in V1.
+  static void order(Value *&V1, Value *&V2) {
+    static compare c;
+    if (c(V1, V2))
+      std::swap(V1, V2);
   }
 
+  /// Similar to EquivalenceClasses, this stores the set of equivalent
+  /// types. Beyond EquivalenceClasses, it allows the user to specify
+  /// which element will act as leader through a StrictWeakOrdering
+  /// function.
+  template<typename ElemTy, typename StrictWeak>
+  class VISIBILITY_HIDDEN Synonyms {
+    std::map<ElemTy, unsigned> mapping;
+    std::vector<ElemTy> leaders;
+    StrictWeak swo;
+
+  public:
+    typedef unsigned iterator;
+    typedef const unsigned const_iterator;
+
+    // Inspection
+
+    bool empty() const {
+      return leaders.empty();
+    }
+
+    iterator findLeader(ElemTy e) {
+      typename std::map<ElemTy, unsigned>::iterator MI = mapping.find(e);
+      if (MI == mapping.end()) return 0;
+
+      return MI->second;
+    }
+
+    const_iterator findLeader(ElemTy e) const {
+      typename std::map<ElemTy, unsigned>::const_iterator MI =
+          mapping.find(e);
+      if (MI == mapping.end()) return 0;
+
+      return MI->second;
+    }
+
+    ElemTy &getLeader(iterator I) {
+      assert(I != 0 && "Element zero is out of range.");
+      return leaders[I-1];
+    }
+
+    const ElemTy &getLeader(const_iterator I) const {
+      assert(I != 0 && "Element zero is out of range.");
+      return leaders[I-1];
+    }
+
+#ifdef DEBUG
+    void debug(std::ostream &os) const {
+      for (unsigned i = 1, e = leaders.size()+1; i != e; ++i) {
+        os << i << ". " << *leaders[i-1] << ": [";
+        for (std::map<Value *, unsigned>::const_iterator
+             I = mapping.begin(), E = mapping.end(); I != E; ++I) {
+          if ((*I).second == i && (*I).first != leaders[i-1]) {
+            os << *(*I).first << "  ";
+	  }
+	}
+        os << "]\n";
+      }
+    }
+#endif
+
+    // Mutators
+
+    /// Combine two sets referring to the same element, inserting the
+    /// elements as needed. Returns a valid iterator iff two already
+    /// existing disjoint synonym sets were combined. The iterator
+    /// points to the removed element.
+    iterator unionSets(ElemTy E1, ElemTy E2) {
+      if (swo(E1, E2)) std::swap(E1, E2);
+
+      iterator I1 = findLeader(E1);
+      iterator I2 = findLeader(E2);
+
+      if (!I1 && !I2) { // neither entry is in yet
+        leaders.push_back(E1);
+        I1 = leaders.size();
+        mapping[E1] = I1;
+        mapping[E2] = I1;
+        return false;
+      }
+
+      if (!I1 && I2) {
+        mapping[E1] = I2;
+        return false;
+      }
+
+      if (I1 && !I2) {
+        mapping[E2] = I1;
+        return false;
+      }
+
+      // This is the case where we have two sets, [%a1, %a2, %a3] and
+      // [%p1, %p2, %p3] and someone says that %a2 == %p3. We need to
+      // combine the two synsets.
+
+      for (std::map<Value *, unsigned>::iterator I = mapping.begin(),
+           E = mapping.end(); I != E; ++I) {
+        if (I->second == I2) I->second = I1;
+        else if (I->second > I2) --I->second;
+      }
+
+      leaders.erase(leaders.begin() + I2 - 1);
+
+      return true;
+    }
+
+    /// Returns an iterator pointing to the synonym set containing
+    /// element e. If none exists, a new one is created and returned.
+    iterator findOrInsert(ElemTy e) {
+      iterator I = findLeader(e);
+      if (I) return I;
+
+      leaders.push_back(e);
+      I = leaders.size();
+      mapping[e] = I;
+      return I;
+    }
+  };
+
   /// Represents the set of equivalent Value*s and provides insertion
   /// and fast lookup. Also stores the set of inequality relationships.
   class PropertySet {
     struct Property;
-    class EquivalenceClasses<Value *> union_find;
   public:
+    class Synonyms<Value *, compare> union_find;
+
     typedef std::vector<Property>::iterator       PropertyIterator;
     typedef std::vector<Property>::const_iterator ConstPropertyIterator;
+    typedef Synonyms<Value *, compare>::iterator  SynonymIterator;
 
     enum Ops {
       EQ,
@@ -98,10 +226,9 @@
     }
 
     Value *lookup(Value *V) const {
-      EquivalenceClasses<Value *>::member_iterator SI =
-          union_find.findLeader(V);
-      if (SI == union_find.member_end()) return NULL;
-      return *SI;
+      Synonyms<Value *, compare>::iterator SI = union_find.findLeader(V);
+      if (!SI) return NULL;
+      return union_find.getLeader(SI);
     }
 
     bool empty() const {
@@ -117,7 +244,18 @@
       if (isa<Constant>(V2)) return; // refuse to set false == true.
 
       DEBUG(std::cerr << "equal: " << *V1 << " and " << *V2 << "\n");
-      union_find.unionSets(V1, V2);
+      SynonymIterator deleted = union_find.unionSets(V1, V2);
+      if (deleted) {
+        SynonymIterator replacement = union_find.findLeader(V1);
+        // Move Properties
+        for (PropertyIterator I = Properties.begin(), E = Properties.end();
+             I != E; ++I) {
+          if (I->I1 == deleted) I->I1 = replacement;
+          else if (I->I1 > deleted) --I->I1;
+          if (I->I2 == deleted) I->I2 = replacement;
+          else if (I->I2 > deleted) --I->I2;
+        }
+      }
       addImpliedProperties(EQ, V1, V2);
     }
 
@@ -130,7 +268,9 @@
         return; // found.
 
       // Add the property.
-      Properties.push_back(Property(NE, V1, V2));
+      SynonymIterator I1 = union_find.findOrInsert(V1),
+                      I2 = union_find.findOrInsert(V2);
+      Properties.push_back(Property(NE, I1, I2));
       addImpliedProperties(NE, V1, V2);
     }
 
@@ -138,22 +278,12 @@
       assert(Opcode != EQ && "Can't findProperty on EQ."
              "Use the lookup method instead.");
 
-      V1 = canonicalize(V1);
-      V2 = canonicalize(V2);
+      SynonymIterator I1 = union_find.findLeader(V1),
+                      I2 = union_find.findLeader(V2);
+      if (!I1 || !I2) return Properties.end();
 
-      // Does the property already exist?
-      for (PropertyIterator I = Properties.begin(), E = Properties.end();
-           I != E; ++I) {
-        if (I->Opcode != Opcode) continue;
-
-        I->V1 = canonicalize(I->V1);
-        I->V2 = canonicalize(I->V2);
-        if ((I->V1 == V1 && I->V2 == V2) ||
-            (I->V1 == V2 && I->V2 == V1)) {
-          return I; // Found.
-        }
-      }
-      return Properties.end();
+      return
+      find(Properties.begin(), Properties.end(), Property(Opcode, I1, I2));
     }
 
     ConstPropertyIterator
@@ -161,35 +291,33 @@
       assert(Opcode != EQ && "Can't findProperty on EQ."
              "Use the lookup method instead.");
 
-      V1 = canonicalize(V1);
-      V2 = canonicalize(V2);
-
-      // Does the property already exist?
-      for (ConstPropertyIterator I = Properties.begin(),
-           E = Properties.end(); I != E; ++I) {
-        if (I->Opcode != Opcode) continue;
+      SynonymIterator I1 = union_find.findLeader(V1),
+                      I2 = union_find.findLeader(V2);
+      if (!I1 || !I2) return Properties.end();
 
-        Value *v1 = canonicalize(I->V1),
-              *v2 = canonicalize(I->V2);
-        if ((v1 == V1 && v2 == V2) ||
-            (v1 == V2 && v2 == V1)) {
-          return I; // Found.
-        }
-      }
-      return Properties.end();
+      return
+      find(Properties.begin(), Properties.end(), Property(Opcode, I1, I2));
     }
 
   private:
     // Represents Head OP [Tail1, Tail2, ...]
     // For example: %x != %a, %x != %b.
-    struct Property {
-      Property(Ops opcode, Value *v1, Value *v2)
-        : Opcode(opcode), V1(v1), V2(v2)
+    struct VISIBILITY_HIDDEN Property {
+      typedef Synonyms<Value *, compare>::iterator Iter;
+
+      Property(Ops opcode, Iter i1, Iter i2)
+        : Opcode(opcode), I1(i1), I2(i2)
       { assert(opcode != EQ && "Equality belongs in the synonym set, "
-               "not a property."); }
+                               "not a property."); }
+
+      bool operator==(const Property &P) const {
+        return (Opcode == P.Opcode) &&
+               ((I1 == P.I1 && I2 == P.I2) ||
+                (I1 == P.I2 && I2 == P.I1));
+      }
 
       Ops Opcode;
-      Value *V1, *V2;
+      Iter I1, I2;
     };
 
     void add(Ops Opcode, Value *V1, Value *V2, bool invert) {
@@ -207,7 +335,7 @@
       }
     }
 
-    // Finds the properties implied by a equivalence and adds them too.
+    // Finds the properties implied by an equivalence and adds them too.
     // Example: ("seteq %a, %b", true,  EQ) --> (%a, %b, EQ)
     //          ("seteq %a, %b", false, EQ) --> (%a, %b, NE)
     void addImpliedProperties(Ops Opcode, Value *V1, Value *V2) {
@@ -286,14 +414,15 @@
   public:
 #ifdef DEBUG
     void debug(std::ostream &os) const {
-      for (EquivalenceClasses<Value*>::iterator I = union_find.begin(),
-           E = union_find.end(); I != E; ++I) {
-        if (!I->isLeader()) continue;
-        for (EquivalenceClasses<Value*>::member_iterator MI =
-             union_find.member_begin(I); MI != union_find.member_end(); ++MI)
-          std::cerr << **MI << " ";
-        std::cerr << "\n--\n";
+      static const char *OpcodeTable[] = { "EQ", "NE" };
+
+      union_find.debug(os);
+      for (std::vector<Property>::const_iterator I = Properties.begin(),
+           E = Properties.end(); I != E; ++I) {
+        os << (*I).I1 << " " << OpcodeTable[(*I).Opcode] << " "
+           << (*I).I2 << "\n";
       }
+      os << "\n";
     }
 #endif
 
@@ -319,22 +448,24 @@
     // block to the next. Verifies that "current" dominates "next",
     // then calls visitBasicBlock.
     void proceedToSuccessor(PropertySet &CurrentPS, PropertySet &NextPS,
-                  DominatorTree::Node *Current, DominatorTree::Node *Next);
+                            DTNodeType *Current, DTNodeType *Next);
     void proceedToSuccessor(PropertySet &CurrentPS,
-                  DominatorTree::Node *Current, DominatorTree::Node *Next);
+                            DTNodeType *Current, DTNodeType *Next);
 
     // Visits each instruction in the basic block.
-    void visitBasicBlock(DominatorTree::Node *DTNode,
-                         PropertySet &KnownProperties);
+    void visitBasicBlock(DTNodeType *DTNode, PropertySet &KnownProperties);
 
+    // Tries to simplify each Instruction and add new properties to
+    // the PropertySet. Returns true if it erase the instruction.
+    void visitInstruction(Instruction *I, DTNodeType *, PropertySet &);
     // For each instruction, add the properties to KnownProperties.
-    void visit(Instruction *I, DominatorTree::Node *, PropertySet &);
-    void visit(TerminatorInst *TI, DominatorTree::Node *, PropertySet &);
-    void visit(BranchInst *BI, DominatorTree::Node *, PropertySet &);
-    void visit(SwitchInst *SI, DominatorTree::Node *, PropertySet);
-    void visit(LoadInst *LI, DominatorTree::Node *, PropertySet &);
-    void visit(StoreInst *SI, DominatorTree::Node *, PropertySet &);
-    void visit(BinaryOperator *BO, DominatorTree::Node *, PropertySet &);
+
+    void visit(TerminatorInst *TI, DTNodeType *, PropertySet &);
+    void visit(BranchInst *BI, DTNodeType *, PropertySet &);
+    void visit(SwitchInst *SI, DTNodeType *, PropertySet);
+    void visit(LoadInst *LI, DTNodeType *, PropertySet &);
+    void visit(StoreInst *SI, DTNodeType *, PropertySet &);
+    void visit(BinaryOperator *BO, DTNodeType *, PropertySet &);
 
     DominatorTree *DT;
     bool modified;
@@ -421,18 +552,11 @@
   if (SetCondInst *SCI = dyn_cast<SetCondInst>(BO))
     return resolve(SCI, KP);
 
-  DEBUG(std::cerr << "BO->getOperand(1) = " << *BO->getOperand(1) << "\n");
-
   Value *lhs = resolve(BO->getOperand(0), KP),
         *rhs = resolve(BO->getOperand(1), KP);
   ConstantIntegral *CI1 = dyn_cast<ConstantIntegral>(lhs);
   ConstantIntegral *CI2 = dyn_cast<ConstantIntegral>(rhs);
 
-  DEBUG(std::cerr << "resolveBO: lhs = " << *lhs
-                  << ", rhs = " << *rhs << "\n");
-  if (CI1) DEBUG(std::cerr << "CI1 = " << *CI1);
-  if (CI2) DEBUG(std::cerr << "CI2 = " << *CI2);
-
   if (!CI1 || !CI2) return BO;
 
   Value *V = ConstantExpr::get(BO->getOpcode(), CI1, CI2);
@@ -464,27 +588,28 @@
   return V;
 }
 
-void PredicateSimplifier::visitBasicBlock(DominatorTree::Node *DTNode,
+void PredicateSimplifier::visitBasicBlock(DTNodeType *DTNode,
                                           PropertySet &KnownProperties) {
   BasicBlock *BB = DTNode->getBlock();
   for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) {
-    visit(I, DTNode, KnownProperties);
+    visitInstruction(I, DTNode, KnownProperties);
   }
 }
 
-void PredicateSimplifier::visit(Instruction *I, DominatorTree::Node *DTNode,
-                                PropertySet &KnownProperties) {
+void PredicateSimplifier::visitInstruction(Instruction *I,
+                                           DTNodeType *DTNode,
+                                           PropertySet &KnownProperties) {
+
   DEBUG(std::cerr << "Considering instruction " << *I << "\n");
   DEBUG(KnownProperties.debug(std::cerr));
 
-  // Try to replace whole instruction.
+  // Try to replace the whole instruction.
   Value *V = resolve(I, KnownProperties);
   assert(V && "resolve not supposed to return NULL.");
   if (V != I) {
     modified = true;
     ++NumInstruction;
     I->replaceAllUsesWith(V);
-    I->eraseFromParent();
     return;
   }
 
@@ -513,8 +638,9 @@
 }
 
 void PredicateSimplifier::proceedToSuccessor(PropertySet &CurrentPS,
-    PropertySet &NextPS, DominatorTree::Node *Current,
-    DominatorTree::Node *Next) {
+                                             PropertySet &NextPS,
+                                             DTNodeType *Current,
+                                             DTNodeType *Next) {
   if (Next->getBlock()->getSinglePredecessor() == Current->getBlock())
     proceedToSuccessor(NextPS, Current, Next);
   else
@@ -522,13 +648,14 @@
 }
 
 void PredicateSimplifier::proceedToSuccessor(PropertySet &KP,
-    DominatorTree::Node *Current, DominatorTree::Node *Next) {
+                                             DTNodeType *Current,
+                                             DTNodeType *Next) {
   if (Current->properlyDominates(Next))
     visitBasicBlock(Next, KP);
 }
 
-void PredicateSimplifier::visit(TerminatorInst *TI,
-                                DominatorTree::Node *Node, PropertySet &KP){
+void PredicateSimplifier::visit(TerminatorInst *TI, DTNodeType *Node,
+                                PropertySet &KP) {
   if (BranchInst *BI = dyn_cast<BranchInst>(TI)) {
     visit(BI, Node, KP);
     return;
@@ -545,8 +672,8 @@
   }
 }
 
-void PredicateSimplifier::visit(BranchInst *BI,
-                                DominatorTree::Node *Node, PropertySet &KP){
+void PredicateSimplifier::visit(BranchInst *BI, DTNodeType *Node,
+                                PropertySet &KP) {
   if (BI->isUnconditional()) {
     proceedToSuccessor(KP, Node, DT->getNode(BI->getSuccessor(0)));
     return;
@@ -586,33 +713,36 @@
   proceedToSuccessor(KPcopy, FalseProperties, Node, DT->getNode(FalseDest));
 }
 
-void PredicateSimplifier::visit(SwitchInst *SI,
-                             DominatorTree::Node *DTNode, PropertySet KP) {
+void PredicateSimplifier::visit(SwitchInst *SI, DTNodeType *DTNode,
+                                PropertySet KP) {
   Value *Condition = SI->getCondition();
-  DEBUG(assert(Condition == KP.canonicalize(Condition) &&
-               "Instruction wasn't already canonicalized?"));
+  assert(Condition == KP.canonicalize(Condition) &&
+         "Instruction wasn't already canonicalized?");
 
   // If there's an NEProperty covering this SwitchInst, we may be able to
   // eliminate one of the cases.
   for (PropertySet::ConstPropertyIterator I = KP.Properties.begin(),
        E = KP.Properties.end(); I != E; ++I) {
     if (I->Opcode != PropertySet::NE) continue;
-    Value *V1 = KP.canonicalize(I->V1),
-          *V2 = KP.canonicalize(I->V2);
-    if (V1 != Condition && V2 != Condition) continue;
-
-    // Is one side a number?
-    ConstantInt *CI = dyn_cast<ConstantInt>(KP.canonicalize(I->V1));
-    if (!CI)     CI = dyn_cast<ConstantInt>(KP.canonicalize(I->V2));
-
-    if (CI) {
-      unsigned i = SI->findCaseValue(CI);
-      if (i != 0) {
-        SI->getSuccessor(i)->removePredecessor(SI->getParent());
-        SI->removeCase(i);
-        modified = true;
-        ++NumSwitchCases;
-      }
+    Value *V1 = KP.union_find.getLeader(I->I1),
+          *V2 = KP.union_find.getLeader(I->I2);
+
+    // Find a Property with a ConstantInt on one side and our
+    // Condition on the other.
+    ConstantInt *CI = NULL;
+    if (V1 == Condition)
+      CI = dyn_cast<ConstantInt>(V2);
+    else if (V2 == Condition)
+      CI = dyn_cast<ConstantInt>(V1);
+
+    if (!CI) continue;
+
+    unsigned i = SI->findCaseValue(CI);
+    if (i != 0) { // zero is reserved for the default case.
+      SI->getSuccessor(i)->removePredecessor(SI->getParent());
+      SI->removeCase(i);
+      modified = true;
+      ++NumSwitchCases;
     }
   }
 
@@ -620,8 +750,8 @@
   // and the NEProperties in the default BB.
   PropertySet DefaultProperties(KP);
 
-  DominatorTree::Node *Node        = DT->getNode(SI->getParent()),
-                      *DefaultNode = DT->getNode(SI->getSuccessor(0));
+  DTNodeType *Node        = DT->getNode(SI->getParent()),
+             *DefaultNode = DT->getNode(SI->getSuccessor(0));
   if (!Node->dominates(DefaultNode)) DefaultNode = NULL;
 
   for (unsigned I = 1, E = SI->getNumCases(); I < E; ++I) {
@@ -644,20 +774,20 @@
     proceedToSuccessor(DefaultProperties, DTNode, DefaultNode);
 }
 
-void PredicateSimplifier::visit(LoadInst *LI,
-                                DominatorTree::Node *, PropertySet &KP) {
+void PredicateSimplifier::visit(LoadInst *LI, DTNodeType *,
+                                PropertySet &KP) {
   Value *Ptr = LI->getPointerOperand();
   KP.addNotEqual(Constant::getNullValue(Ptr->getType()), Ptr);
 }
 
-void PredicateSimplifier::visit(StoreInst *SI,
-                                DominatorTree::Node *, PropertySet &KP) {
+void PredicateSimplifier::visit(StoreInst *SI, DTNodeType *,
+                                PropertySet &KP) {
   Value *Ptr = SI->getPointerOperand();
   KP.addNotEqual(Constant::getNullValue(Ptr->getType()), Ptr);
 }
 
-void PredicateSimplifier::visit(BinaryOperator *BO,
-                                DominatorTree::Node *, PropertySet &KP) {
+void PredicateSimplifier::visit(BinaryOperator *BO, DTNodeType *,
+                                PropertySet &KP) {
   Instruction::BinaryOps ops = BO->getOpcode();
 
   switch (ops) {
@@ -670,8 +800,4 @@
     default:
       break;
   }
-
-  // Some other things we could do:
-  // In f=x*y, if x != 1 && y != 1 then f != x && f != y.
-  // In f=x+y, if x != 0 then f != y and if y != 0 then f != x.
 }





From lattner at cs.uiuc.edu  Sun Sep 10 01:37:11 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 10 Sep 2006 01:37:11 -0500
Subject: [llvm-commits] CVS:
	llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Message-ID: <200609100637.k8A6bBuB006605@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAGISel.cpp updated: 1.274 -> 1.275
---
Log message:

This code was trying too hard.  By eliminating redundant edges in the CFG
due to switch cases going to the same place, it make #pred != #phi entries,
breaking live interval analysis.

This fixes 458.sjeng on x86 with llc.


---
Diffs of the changes:  (+3 -6)

 SelectionDAGISel.cpp |    9 +++------
 1 files changed, 3 insertions(+), 6 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.274 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.275
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.274	Sat Sep  9 01:03:30 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	Sun Sep 10 01:36:57 2006
@@ -970,24 +970,21 @@
       // of the jump table.  If the value of the jump table slot corresponds to
       // a case statement, push the case's BB onto the vector, otherwise, push
       // the default BB.
-      std::set<MachineBasicBlock*> UniqueBBs;
       std::vector<MachineBasicBlock*> DestBBs;
       uint64_t TEI = First;
       for (CaseItr ii = Cases.begin(), ee = Cases.end(); ii != ee; ++TEI) {
         if (cast<ConstantIntegral>(ii->first)->getRawValue() == TEI) {
           DestBBs.push_back(ii->second);
-          UniqueBBs.insert(ii->second);
           ++ii;
         } else {
           DestBBs.push_back(Default);
-          UniqueBBs.insert(Default);
         }
       }
       
       // Update successor info
-      for (std::set<MachineBasicBlock*>::iterator ii = UniqueBBs.begin(), 
-           ee = UniqueBBs.end(); ii != ee; ++ii)
-        JumpTableBB->addSuccessor(*ii);
+      for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 
+           E = DestBBs.end(); I != E; ++I)
+        JumpTableBB->addSuccessor(*I);
       
       // Create a jump table index for this jump table, or return an existing
       // one.





From lattner at cs.uiuc.edu  Sun Sep 10 13:18:12 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 10 Sep 2006 13:18:12 -0500
Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/TailDuplication.cpp
Message-ID: <200609101818.k8AIICAX020226@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Transforms/Scalar:

TailDuplication.cpp updated: 1.31 -> 1.32
---
Log message:

Allow tail duplication in more cases, relaxing the previous restriction a
bit.  This fixes Regression/Transforms/TailDup/MergeTest.ll


---
Diffs of the changes:  (+12 -1)

 TailDuplication.cpp |   13 ++++++++++++-
 1 files changed, 12 insertions(+), 1 deletion(-)


Index: llvm/lib/Transforms/Scalar/TailDuplication.cpp
diff -u llvm/lib/Transforms/Scalar/TailDuplication.cpp:1.31 llvm/lib/Transforms/Scalar/TailDuplication.cpp:1.32
--- llvm/lib/Transforms/Scalar/TailDuplication.cpp:1.31	Thu Sep  7 16:30:15 2006
+++ llvm/lib/Transforms/Scalar/TailDuplication.cpp	Sun Sep 10 13:17:58 2006
@@ -144,7 +144,18 @@
     // if (b)
     //   foo();
     // Cloning the 'if b' block into the end of the first foo block is messy.
-    return false;
+    
+    // The messy case is when the fall-through block falls through to other
+    // blocks.  This is what we would be preventing if we cloned the block.
+    DestI = Dest;
+    if (++DestI != Dest->getParent()->end()) {
+      BasicBlock *DestSucc = DestI;
+      // If any of Dest's successors are fall-throughs, don't do this xform.
+      for (succ_iterator SI = succ_begin(Dest), SE = succ_end(Dest);
+           SI != SE; ++SI)
+        if (*SI == DestSucc)
+          return false;
+    }
   }
 
   return true;





From lattner at cs.uiuc.edu  Sun Sep 10 13:52:39 2006
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Sun, 10 Sep 2006 13:52:39 -0500
Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/rlwimi3.ll
Message-ID: <200609101852.k8AIqd5K020767@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CodeGen/PowerPC:

rlwimi3.ll added (r1.1)
---
Log message:

add a testcase for this commit: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20050606/026673.html


---
Diffs of the changes:  (+25 -0)

 rlwimi3.ll |   25 +++++++++++++++++++++++++
 1 files changed, 25 insertions(+)


Index: llvm/test/Regression/CodeGen/PowerPC/rlwimi3.ll
diff -c /dev/null llvm/test/Regression/CodeGen/PowerPC/rlwimi3.ll:1.1
*** /dev/null	Sun Sep 10 13:52:35 2006
--- llvm/test/Regression/CodeGen/PowerPC/rlwimi3.ll	Sun Sep 10 13:52:25 2006
***************
*** 0 ****
--- 1,25 ----
+ ; RUN: llvm-as < %s | llc -march=ppc32 -stats 2>&1 | grep 'Number of machine instrs printed' | grep 12
+ 
+ ushort %Trans16Bit(uint %srcA, uint %srcB, uint %alpha) {
+         %tmp1 = shl uint %srcA, ubyte 15                ; <uint> [#uses=1]
+         %tmp2 = and uint %tmp1, 32505856                ; <uint> [#uses=1]
+         %tmp4 = and uint %srcA, 31775           ; <uint> [#uses=1]
+         %tmp5 = or uint %tmp2, %tmp4            ; <uint> [#uses=1]
+         %tmp7 = shl uint %srcB, ubyte 15                ; <uint> [#uses=1]
+         %tmp8 = and uint %tmp7, 32505856                ; <uint> [#uses=1]
+         %tmp10 = and uint %srcB, 31775          ; <uint> [#uses=1]
+         %tmp11 = or uint %tmp8, %tmp10          ; <uint> [#uses=1]
+         %tmp14 = mul uint %tmp5, %alpha         ; <uint> [#uses=1]
+         %tmp16 = sub uint 32, %alpha            ; <uint> [#uses=1]
+         %tmp18 = mul uint %tmp11, %tmp16                ; <uint> [#uses=1]
+         %tmp19 = add uint %tmp18, %tmp14                ; <uint> [#uses=2]
+         %tmp21 = shr uint %tmp19, ubyte 5               ; <uint> [#uses=1]
+         %tmp21 = cast uint %tmp21 to ushort             ; <ushort> [#uses=1]
+         %tmp = and ushort %tmp21, 31775         ; <ushort> [#uses=1]
+         %tmp23 = shr uint %tmp19, ubyte 20              ; <uint> [#uses=1]
+         %tmp23 = cast uint %tmp23 to ushort             ; <ushort> [#uses=1]
+         %tmp24 = and ushort %tmp23, 992         ; <ushort> [#uses=1]
+         %tmp25 = or ushort %tmp, %tmp24         ; <ushort> [#uses=1]
+         ret ushort %tmp25
+ }
+ 





From asl at math.spbu.ru  Sun Sep 10 16:17:17 2006
From: asl at math.spbu.ru (Anton Korobeynikov)
Date: Sun, 10 Sep 2006 16:17:17 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/ARM/ARMAsmPrinter.cpp
Message-ID: <200609102117.k8ALHHYN022978@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/ARM:

ARMAsmPrinter.cpp updated: 1.16 -> 1.17
---
Log message:

Removed unnecessary Mangler creation.


---
Diffs of the changes:  (+0 -1)

 ARMAsmPrinter.cpp |    1 -
 1 files changed, 1 deletion(-)


Index: llvm/lib/Target/ARM/ARMAsmPrinter.cpp
diff -u llvm/lib/Target/ARM/ARMAsmPrinter.cpp:1.16 llvm/lib/Target/ARM/ARMAsmPrinter.cpp:1.17
--- llvm/lib/Target/ARM/ARMAsmPrinter.cpp:1.16	Thu Sep  7 17:06:40 2006
+++ llvm/lib/Target/ARM/ARMAsmPrinter.cpp	Sun Sep 10 16:17:03 2006
@@ -201,7 +201,6 @@
 }
 
 bool ARMAsmPrinter::doInitialization(Module &M) {
-  Mang = new Mangler(M);
   return false; // success
 }
 





From natebegeman at mac.com  Sun Sep 10 18:04:01 2006
From: natebegeman at mac.com (Nate Begeman)
Date: Sun, 10 Sep 2006 18:04:01 -0500
Subject: [llvm-commits] CVS: llvm/lib/CodeGen/MachOWriter.cpp
Message-ID: <200609102304.k8AN41HW024549@zion.cs.uiuc.edu>



Changes in directory llvm/lib/CodeGen:

MachOWriter.cpp updated: 1.5 -> 1.6
---
Log message:

Behold, more work on relocations.  Things are looking pretty good now.


---
Diffs of the changes:  (+106 -38)

 MachOWriter.cpp |  144 +++++++++++++++++++++++++++++++++++++++++---------------
 1 files changed, 106 insertions(+), 38 deletions(-)


Index: llvm/lib/CodeGen/MachOWriter.cpp
diff -u llvm/lib/CodeGen/MachOWriter.cpp:1.5 llvm/lib/CodeGen/MachOWriter.cpp:1.6
--- llvm/lib/CodeGen/MachOWriter.cpp:1.5	Fri Sep  8 17:42:09 2006
+++ llvm/lib/CodeGen/MachOWriter.cpp	Sun Sep 10 18:03:44 2006
@@ -25,6 +25,7 @@
 #include "llvm/Module.h"
 #include "llvm/CodeGen/MachineCodeEmitter.h"
 #include "llvm/CodeGen/MachineConstantPool.h"
+#include "llvm/CodeGen/MachineJumpTableInfo.h"
 #include "llvm/CodeGen/MachOWriter.h"
 #include "llvm/ExecutionEngine/ExecutionEngine.h"
 #include "llvm/Target/TargetJITInfo.h"
@@ -50,6 +51,14 @@
     /// Relocations - These are the relocations that the function needs, as
     /// emitted.
     std::vector<MachineRelocation> Relocations;
+    
+    /// CPLocations - This is a map of constant pool indices to offsets from the
+    /// start of the section for that constant pool index.
+    std::vector<intptr_t> CPLocations;
+
+    /// JTLocations - This is a map of jump table indices to offsets from the
+    /// start of the section for that jump table index.
+    std::vector<intptr_t> JTLocations;
 
     /// MBBLocations - This vector is a mapping from MBB ID's to their address.
     /// It is filled in by the StartMachineBasicBlock callback and queried by
@@ -66,19 +75,22 @@
       Relocations.push_back(MR);
     }
     
-    virtual void StartMachineBasicBlock(MachineBasicBlock *MBB) {
-      if (MBBLocations.size() <= (unsigned)MBB->getNumber())
-        MBBLocations.resize((MBB->getNumber()+1)*2);
-      MBBLocations[MBB->getNumber()] = getCurrentPCValue();
-    }
-
+    void emitConstantPool(MachineConstantPool *MCP);
+    void emitJumpTables(MachineJumpTableInfo *MJTI);
+    
     virtual intptr_t getConstantPoolEntryAddress(unsigned Index) const {
       assert(0 && "CP not implementated yet!");
       return 0;
     }
     virtual intptr_t getJumpTableEntryAddress(unsigned Index) const {
-      assert(0 && "JT not implementated yet!");
-      return 0;
+      assert(JTLocations.size() > Index && "JT not emitted!");
+      return JTLocations[Index];
+    }
+
+    virtual void StartMachineBasicBlock(MachineBasicBlock *MBB) {
+      if (MBBLocations.size() <= (unsigned)MBB->getNumber())
+        MBBLocations.resize((MBB->getNumber()+1)*2);
+      MBBLocations[MBB->getNumber()] = getCurrentPCOffset();
     }
 
     virtual intptr_t getMachineBasicBlockAddress(MachineBasicBlock *MBB) const {
@@ -119,7 +131,9 @@
   // Upgrade the section alignment if required.
   if (MOS->align < Align) MOS->align = Align;
 
-  // Make sure we only relocate to this function's MBBs.
+  // Clear per-function data structures.
+  CPLocations.clear();
+  JTLocations.clear();
   MBBLocations.clear();
 }
 
@@ -132,26 +146,31 @@
   const GlobalValue *FuncV = F.getFunction();
   MachOSym FnSym(FuncV, MOW.Mang->getValueName(FuncV), MOS->Index);
 
-  // FIXME: emit constant pool to appropriate section(s)
-  // FIXME: emit jump table to appropriate section
+  // Emit constant pool to appropriate section(s)
+  emitConstantPool(F.getConstantPool());
+
+  // Emit jump tables to appropriate section
+  emitJumpTables(F.getJumpTableInfo());
   
-  // Resolve the function's relocations either to concrete pointers in the case
-  // of branches from one block to another, or to target relocation entries.
+  // If we have emitted any relocations to function-specific objects such as 
+  // basic blocks, constant pools entries, or jump tables, record their
+  // addresses now so that we can rewrite them with the correct addresses
+  // later.
   for (unsigned i = 0, e = Relocations.size(); i != e; ++i) {
     MachineRelocation &MR = Relocations[i];
+    intptr_t Addr;
     if (MR.isBasicBlock()) {
-      void *MBBAddr = (void *)getMachineBasicBlockAddress(MR.getBasicBlock());
-      MR.setResultPointer(MBBAddr);
-      MOW.TM.getJITInfo()->relocate(BufferBegin, &MR, 1, 0);
-    } else if (MR.isConstantPoolIndex() || MR.isJumpTableIndex()) {
-      // Get the address of the index.
-      uint64_t Addr = 0;
-      // Generate the relocation(s) for the index.
-      MOW.GetTargetRelocation(*MOS, MR, Addr);
-    } else {
-      // Handle other types later once we've finalized the sections in the file.
-      MOS->Relocations.push_back(MR);
+      Addr = getMachineBasicBlockAddress(MR.getBasicBlock());
+      MR.setResultPointer((void *)Addr);
+    } else if (MR.isConstantPoolIndex()) {
+      Addr = getConstantPoolEntryAddress(MR.getConstantPoolIndex());
+      MR.setResultPointer((void *)Addr);
+    } else if (MR.isJumpTableIndex()) {
+      // FIXME: handle PIC codegen
+      Addr = getJumpTableEntryAddress(MR.getJumpTableIndex());
+      MR.setResultPointer((void *)Addr);
     }
+    MOS->Relocations.push_back(MR);
   }
   Relocations.clear();
   
@@ -160,6 +179,42 @@
   return false;
 }
 
+/// emitConstantPool - For each constant pool entry, figure out which section
+/// the constant should live in, allocate space for it, and emit it to the 
+/// Section data buffer.
+void MachOCodeEmitter::emitConstantPool(MachineConstantPool *MCP) {
+}
+
+/// emitJumpTables - Emit all the jump tables for a given jump table info
+/// record to the appropriate section.
+void MachOCodeEmitter::emitJumpTables(MachineJumpTableInfo *MJTI) {
+  const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
+  if (JT.empty()) return;
+
+  bool isPIC = MOW.TM.getRelocationModel() == Reloc::PIC_;
+  assert(!isPIC && "PIC codegen not yet handled for mach-o jump tables!");
+
+  MachOWriter::MachOSection &Sec = MOW.getJumpTableSection();
+
+  for (unsigned i = 0, e = JT.size(); i != e; ++i) {
+    // For each jump table, record its offset from the start of the section,
+    // reserve space for the relocations to the MBBs, and add the relocations.
+    const std::vector<MachineBasicBlock*> &MBBs = JT[i].MBBs;
+    JTLocations.push_back(Sec.SectionData.size());
+    for (unsigned mi = 0, me = MBBs.size(); mi != me; ++mi) {
+      MachineRelocation MR(MOW.GetJTRelocation(Sec.SectionData.size(),
+                                               MBBs[mi]));
+      MR.setResultPointer((void *)JTLocations[i]);
+      Sec.Relocations.push_back(MR);
+      MOW.outaddr(Sec.SectionData, 0);
+    }
+  }
+  // FIXME: it really seems like keeping these in sync is redundant, someone
+  // should do something about that (never access section size directly, only
+  // look at buffer size).
+  Sec.size = Sec.SectionData.size();
+}
+
 //===----------------------------------------------------------------------===//
 //                          MachOWriter Implementation
 //===----------------------------------------------------------------------===//
@@ -294,12 +349,9 @@
   // Emit the header and load commands.
   EmitHeaderAndLoadCommands();
 
-  // Emit the text and data sections.
+  // Emit the various sections and their relocation info.
   EmitSections();
 
-  // Emit the relocation entry data for each section.
-  O.write((char*)&RelocBuffer[0], RelocBuffer.size());
-
   // Write the symbol table and the string table to the end of the file.
   O.write((char*)&SymT[0], SymT.size());
   O.write((char*)&StrT[0], StrT.size());
@@ -370,6 +422,7 @@
          E = SectionList.end(); I != E; ++I) {
     I->addr = currentAddr;
     I->offset = currentAddr + SEG.fileoff;
+
     // FIXME: do we need to do something with alignment here?
     currentAddr += I->size;
   }
@@ -380,14 +433,8 @@
   for (std::list<MachOSection>::iterator I = SectionList.begin(),
          E = SectionList.end(); I != E; ++I) {
     // calculate the relocation info for this section command
-    // FIXME: this could get complicated calculating the address argument, we 
-    // should probably split this out into its own function.
-    for (unsigned i = 0, e = I->Relocations.size(); i != e; ++i)
-      GetTargetRelocation(*I, I->Relocations[i], 0);
-    if (I->nreloc != 0) {
-      I->reloff = currentAddr;
-      currentAddr += I->nreloc * 8;
-    }
+    CalculateRelocations(*I, currentAddr);
+    currentAddr += I->nreloc * 8;
     
     // write the finalized section command to the output buffer
     outstring(FH, I->sectname, 16);
@@ -449,9 +496,13 @@
 /// commands, emit the data for each section to the file.
 void MachOWriter::EmitSections() {
   for (std::list<MachOSection>::iterator I = SectionList.begin(),
-         E = SectionList.end(); I != E; ++I) {
+         E = SectionList.end(); I != E; ++I)
+    // Emit the contents of each section
     O.write((char*)&I->SectionData[0], I->size);
-  }
+  for (std::list<MachOSection>::iterator I = SectionList.begin(),
+         E = SectionList.end(); I != E; ++I)
+    // Emit the relocation entry data for each section.
+    O.write((char*)&I->RelocBuffer[0], I->RelocBuffer.size());
 }
 
 /// PartitionByLocal - Simple boolean predicate that returns true if Sym is
@@ -526,6 +577,23 @@
   }
 }
 
+/// CalculateRelocations - For each MachineRelocation in the current section,
+/// calculate the index of the section containing the object to be relocated,
+/// and the offset into that section.  From this information, create the
+/// appropriate target-specific MachORelocation type and add buffer it to be
+/// written out after we are finished writing out sections.
+void MachOWriter::CalculateRelocations(MachOSection &MOS, unsigned RelOffset) {
+  for (unsigned i = 0, e = MOS.Relocations.size(); i != e; ++i) {
+    // FIXME: calculate the correct offset and section index for relocated
+    // object.
+    // FIXME: somehow convey the fact that the relocation might be external
+    // to the relocating code.
+    GetTargetRelocation(MOS.Relocations[i], MOS, MOS.Index);
+  }
+  if (MOS.nreloc != 0)
+    MOS.reloff = RelOffset;
+}
+
 MachOSym::MachOSym(const GlobalValue *gv, std::string name, uint8_t sect) :
   GV(gv), GVName(name), n_strx(0), n_type(sect == NO_SECT ? N_UNDF : N_SECT), 
   n_sect(sect), n_desc(0), n_value(0) {





From natebegeman at mac.com  Sun Sep 10 18:04:03 2006
From: natebegeman at mac.com (Nate Begeman)
Date: Sun, 10 Sep 2006 18:04:03 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCMachOWriter.cpp
	PPCRelocations.h
Message-ID: <200609102304.k8AN43U4024556@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/PowerPC:

PPCMachOWriter.cpp updated: 1.4 -> 1.5
PPCRelocations.h updated: 1.10 -> 1.11
---
Log message:

Behold, more work on relocations.  Things are looking pretty good now.


---
Diffs of the changes:  (+70 -40)

 PPCMachOWriter.cpp |  106 +++++++++++++++++++++++++++++++++--------------------
 PPCRelocations.h   |    4 ++
 2 files changed, 70 insertions(+), 40 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCMachOWriter.cpp
diff -u llvm/lib/Target/PowerPC/PPCMachOWriter.cpp:1.4 llvm/lib/Target/PowerPC/PPCMachOWriter.cpp:1.5
--- llvm/lib/Target/PowerPC/PPCMachOWriter.cpp:1.4	Fri Sep  8 17:42:09 2006
+++ llvm/lib/Target/PowerPC/PPCMachOWriter.cpp	Sun Sep 10 18:03:44 2006
@@ -31,9 +31,15 @@
       Header.cpusubtype = MachOHeader::CPU_SUBTYPE_POWERPC_ALL;
     }
 
-    virtual void GetTargetRelocation(MachOSection &MOS, MachineRelocation &MR,
-                                     uint64_t Addr);
+    virtual void GetTargetRelocation(MachineRelocation &MR, MachOSection &MOS,
+                                     unsigned ToIndex);
+    virtual MachineRelocation GetJTRelocation(unsigned Offset,
+                                              MachineBasicBlock *MBB);
     
+    virtual const char *getPassName() const {
+      return "PowerPC Mach-O Writer";
+    }
+
     // Constants for the relocation r_type field.
     // see <mach-o/ppc/reloc.h>
     enum { PPC_RELOC_VANILLA, // generic relocation
@@ -53,73 +59,93 @@
 ///
 void llvm::addPPCMachOObjectWriterPass(FunctionPassManager &FPM,
                                        std::ostream &O, PPCTargetMachine &TM) {
-  PPCMachOWriter *EW = new PPCMachOWriter(O, TM);
-  FPM.add(EW);
-  FPM.add(createPPCCodeEmitterPass(TM, EW->getMachineCodeEmitter()));
+  PPCMachOWriter *MOW = new PPCMachOWriter(O, TM);
+  FPM.add(MOW);
+  FPM.add(createPPCCodeEmitterPass(TM, MOW->getMachineCodeEmitter()));
 }
 
 /// GetTargetRelocation - For the MachineRelocation MR, convert it to one or
 /// more PowerPC MachORelocation(s), add the new relocations to the
 /// MachOSection, and rewrite the instruction at the section offset if required 
 /// by that relocation type.
-void PPCMachOWriter::GetTargetRelocation(MachOSection &MOS,
-                                         MachineRelocation &MR,
-                                         uint64_t Addr) {
+void PPCMachOWriter::GetTargetRelocation(MachineRelocation &MR,
+                                         MachOSection &MOS,
+                                         unsigned ToIndex) {
+  uint64_t Addr = 0;
+  
   // Keep track of whether or not this is an externally defined relocation.
-  uint32_t index = MOS.Index;
   bool     isExtern = false;
   
-  // Get the address of the instruction to rewrite
-  unsigned char *RelocPos = &MOS.SectionData[0] + MR.getMachineCodeOffset();
-  
   // Get the address of whatever it is we're relocating, if possible.
-  if (MR.isGlobalValue()) {
-    // determine whether or not its external and then figure out what section
-    // we put it in if it's a locally defined symbol.
-  } else if (MR.isString()) {
-    // lookup in global values?
-  } else {
-    assert((MR.isConstantPoolIndex() || MR.isJumpTableIndex()) &&
-           "Unhandled MachineRelocation type!");
-  }
-  
+  if (!isExtern)
+    Addr = (uintptr_t)MR.getResultPointer();
+    
   switch ((PPC::RelocationType)MR.getRelocationType()) {
   default: assert(0 && "Unknown PPC relocation type!");
-  case PPC::reloc_pcrel_bx:
-  case PPC::reloc_pcrel_bcx:
   case PPC::reloc_absolute_low_ix:
     assert(0 && "Unhandled PPC relocation type!");
     break;
+  case PPC::reloc_vanilla:
+    {
+      // FIXME: need to handle 64 bit vanilla relocs
+      MachORelocation VANILLA(MR.getMachineCodeOffset(), ToIndex, false, 2, 
+                              isExtern, PPC_RELOC_VANILLA);
+      outword(MOS.RelocBuffer, VANILLA.r_address);
+      outword(MOS.RelocBuffer, VANILLA.getPackedFields());
+    }
+    MOS.nreloc += 1;
+    fixword(MOS.SectionData, Addr, MR.getMachineCodeOffset());
+    break;
+  case PPC::reloc_pcrel_bx:
+    Addr -= MR.getMachineCodeOffset();
+    Addr >>= 2;
+    Addr & 0xFFFFFF;
+    Addr <<= 2;
+    Addr |= (MOS.SectionData[MR.getMachineCodeOffset()] << 24);
+    fixword(MOS.SectionData, Addr, MR.getMachineCodeOffset());
+    break;
+  case PPC::reloc_pcrel_bcx:
+    Addr -= MR.getMachineCodeOffset();
+    Addr &= 0xFFFC;
+    fixhalf(MOS.SectionData, Addr, MR.getMachineCodeOffset() + 2);
+    break;
   case PPC::reloc_absolute_high:
     {
-      MachORelocation HA16(MR.getMachineCodeOffset(), index, false, 2, isExtern, 
-                           PPC_RELOC_HA16);
+      MachORelocation HA16(MR.getMachineCodeOffset(), ToIndex, false, 2,
+                           isExtern, PPC_RELOC_HA16);
       MachORelocation PAIR(Addr & 0xFFFF, 0xFFFFFF, false, 2, isExtern,
                            PPC_RELOC_PAIR);
-      outword(RelocBuffer, HA16.r_address);
-      outword(RelocBuffer, HA16.getPackedFields());
-      outword(RelocBuffer, PAIR.r_address);
-      outword(RelocBuffer, PAIR.getPackedFields());
+      outword(MOS.RelocBuffer, HA16.r_address);
+      outword(MOS.RelocBuffer, HA16.getPackedFields());
+      outword(MOS.RelocBuffer, PAIR.r_address);
+      outword(MOS.RelocBuffer, PAIR.getPackedFields());
     }
+    printf("ha16: %x\n", (unsigned)Addr);
     MOS.nreloc += 2;
     Addr += 0x8000;
-    *(unsigned *)RelocPos &= 0xFFFF0000;
-    *(unsigned *)RelocPos |= ((Addr >> 16) & 0xFFFF);
+    fixhalf(MOS.SectionData, Addr >> 16, MR.getMachineCodeOffset() + 2);
     break;
   case PPC::reloc_absolute_low:
     {
-      MachORelocation LO16(MR.getMachineCodeOffset(), index, false, 2, isExtern, 
-                           PPC_RELOC_LO16);
+      MachORelocation LO16(MR.getMachineCodeOffset(), ToIndex, false, 2,
+                           isExtern, PPC_RELOC_LO16);
       MachORelocation PAIR(Addr >> 16, 0xFFFFFF, false, 2, isExtern,
                            PPC_RELOC_PAIR);
-      outword(RelocBuffer, LO16.r_address);
-      outword(RelocBuffer, LO16.getPackedFields());
-      outword(RelocBuffer, PAIR.r_address);
-      outword(RelocBuffer, PAIR.getPackedFields());
+      outword(MOS.RelocBuffer, LO16.r_address);
+      outword(MOS.RelocBuffer, LO16.getPackedFields());
+      outword(MOS.RelocBuffer, PAIR.r_address);
+      outword(MOS.RelocBuffer, PAIR.getPackedFields());
     }
+    printf("lo16: %x\n", (unsigned)Addr);
     MOS.nreloc += 2;
-    *(unsigned *)RelocPos &= 0xFFFF0000;
-    *(unsigned *)RelocPos |= (Addr & 0xFFFF);
+    fixhalf(MOS.SectionData, Addr, MR.getMachineCodeOffset() + 2);
     break;
   }
 }
+
+MachineRelocation PPCMachOWriter::GetJTRelocation(unsigned Offset,
+                                                  MachineBasicBlock *MBB) {
+  // FIXME: do something about PIC
+  return MachineRelocation::getBB(Offset, PPC::reloc_vanilla, MBB);
+}
+


Index: llvm/lib/Target/PowerPC/PPCRelocations.h
diff -u llvm/lib/Target/PowerPC/PPCRelocations.h:1.10 llvm/lib/Target/PowerPC/PPCRelocations.h:1.11
--- llvm/lib/Target/PowerPC/PPCRelocations.h:1.10	Fri Sep  8 17:42:09 2006
+++ llvm/lib/Target/PowerPC/PPCRelocations.h	Sun Sep 10 18:03:44 2006
@@ -25,6 +25,10 @@
 namespace llvm {
   namespace PPC {
     enum RelocationType {
+      // reloc_vanilla - A standard relocation, where the address of the
+      // relocated object completely overwrites the address of the relocation.
+      reloc_vanilla,
+    
       // reloc_pcrel_bx - PC relative relocation, for the b or bl instructions.
       reloc_pcrel_bx,
 





From natebegeman at mac.com  Sun Sep 10 18:04:00 2006
From: natebegeman at mac.com (Nate Begeman)
Date: Sun, 10 Sep 2006 18:04:00 -0500
Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/MachOWriter.h
Message-ID: <200609102304.k8AN40c4024543@zion.cs.uiuc.edu>



Changes in directory llvm/include/llvm/CodeGen:

MachOWriter.h updated: 1.6 -> 1.7
---
Log message:

Behold, more work on relocations.  Things are looking pretty good now.


---
Diffs of the changes:  (+36 -11)

 MachOWriter.h |   47 ++++++++++++++++++++++++++++++++++++-----------
 1 files changed, 36 insertions(+), 11 deletions(-)


Index: llvm/include/llvm/CodeGen/MachOWriter.h
diff -u llvm/include/llvm/CodeGen/MachOWriter.h:1.6 llvm/include/llvm/CodeGen/MachOWriter.h:1.7
--- llvm/include/llvm/CodeGen/MachOWriter.h:1.6	Fri Sep  8 17:42:09 2006
+++ llvm/include/llvm/CodeGen/MachOWriter.h	Sun Sep 10 18:03:44 2006
@@ -344,6 +344,10 @@
       /// SectionData - The actual data for this section which we are building
       /// up for emission to the file.
       DataBuffer SectionData;
+
+      /// RelocBuffer - A buffer to hold the mach-o relocations before we write
+      /// them out at the appropriate location in the file.
+      DataBuffer RelocBuffer;
       
       /// Relocations - The relocations that we have encountered so far in this 
       /// section that we will need to convert to MachORelocation entries when
@@ -421,7 +425,7 @@
       }
 
       MachOSection(const std::string &seg, const std::string &sect)
-        : sectname(sect), segname(seg), addr(0), size(0), offset(0), align(0),
+        : sectname(sect), segname(seg), addr(0), size(0), offset(0), align(2),
           reloff(0), nreloc(0), flags(0), reserved1(0), reserved2(0),
           reserved3(0) { }
     };
@@ -449,10 +453,13 @@
       SN->flags = MachOSection::S_REGULAR | Flags;
       return *SN;
     }
-    MachOSection &getTextSection() {
-      return getSection("__TEXT", "__text", 
-                        MachOSection::S_ATTR_PURE_INSTRUCTIONS |
-                        MachOSection::S_ATTR_SOME_INSTRUCTIONS);
+    MachOSection &getTextSection(bool isCode = true) {
+      if (isCode)
+        return getSection("__TEXT", "__text", 
+                          MachOSection::S_ATTR_PURE_INSTRUCTIONS |
+                          MachOSection::S_ATTR_SOME_INSTRUCTIONS);
+      else
+        return getSection("__TEXT", "__text");
     }
     MachOSection &getBSSSection() {
       return getSection("__DATA", "__bss", MachOSection::S_ZEROFILL);
@@ -479,6 +486,12 @@
       }
       return getSection("__TEXT", "__const");
     }
+    MachOSection &getJumpTableSection() {
+      if (TM.getRelocationModel() == Reloc::PIC_)
+        return getTextSection(false);
+      else
+        return getSection("__TEXT", "__const");
+    }
     
     /// MachOSymTab - This struct contains information about the offsets and 
     /// size of symbol table information.
@@ -563,10 +576,6 @@
     /// local symbols first in the list).
     std::vector<MachOSym> SymbolTable;
     
-    /// RelocBuffer - A buffer to hold the mach-o relocations before we write
-    /// them out at the appropriate location in the file.
-    DataBuffer RelocBuffer;
-    
     /// SymT - A buffer to hold the symbol table before we write it out at the
     /// appropriate location in the file.
     DataBuffer SymT;
@@ -666,15 +675,31 @@
         outbyte(Output, 0);
       
     }
+    void fixhalf(DataBuffer &Output, unsigned short X, unsigned Offset) {
+      unsigned char *P = &Output[Offset];
+      P[0] = (X >> (isLittleEndian ?  0 : 8)) & 255;
+      P[1] = (X >> (isLittleEndian ?  8 : 0)) & 255;
+    }
+    void fixword(DataBuffer &Output, unsigned X, unsigned Offset) {
+      unsigned char *P = &Output[Offset];
+      P[0] = (X >> (isLittleEndian ?  0 : 24)) & 255;
+      P[1] = (X >> (isLittleEndian ?  8 : 16)) & 255;
+      P[2] = (X >> (isLittleEndian ? 16 :  8)) & 255;
+      P[3] = (X >> (isLittleEndian ? 24 :  0)) & 255;
+    }
+
   private:
     void AddSymbolToSection(MachOSection &MOS, GlobalVariable *GV);
     void EmitGlobal(GlobalVariable *GV);
     void EmitHeaderAndLoadCommands();
     void EmitSections();
     void BufferSymbolAndStringTable();
+    void CalculateRelocations(MachOSection &MOS, unsigned RelOffset);
 
-    virtual void GetTargetRelocation(MachOSection &MOS, MachineRelocation &MR, 
-                                     uint64_t Addr) = 0;
+    virtual MachineRelocation GetJTRelocation(unsigned Offset,
+                                              MachineBasicBlock *MBB) = 0;
+    virtual void GetTargetRelocation(MachineRelocation &MR, MachOSection &MOS,
+                                     unsigned ToIndex) = 0;
   };
 }
 





From natebegeman at mac.com  Sun Sep 10 18:04:03 2006
From: natebegeman at mac.com (Nate Begeman)
Date: Sun, 10 Sep 2006 18:04:03 -0500
Subject: [llvm-commits] CVS: llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp
Message-ID: <200609102304.k8AN432Q024561@zion.cs.uiuc.edu>



Changes in directory llvm/lib/ExecutionEngine/JIT:

JITEmitter.cpp updated: 1.111 -> 1.112
---
Log message:

Behold, more work on relocations.  Things are looking pretty good now.


---
Diffs of the changes:  (+1 -1)

 JITEmitter.cpp |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)


Index: llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp
diff -u llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.111 llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.112
--- llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:1.111	Tue Aug 15 20:24:12 2006
+++ llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp	Sun Sep 10 18:03:44 2006
@@ -673,7 +673,7 @@
     ///
     void *ConstantPoolBase;
 
-    /// ConstantPool - The constant pool for the current function.
+    /// JumpTable - The jump tables for the current function.
     ///
     MachineJumpTableInfo *JumpTable;
     





From evan.cheng at apple.com  Sun Sep 10 21:20:11 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Sun, 10 Sep 2006 21:20:11 -0500
Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp
	X86ISelLowering.h X86InstrInfo.td X86InstrSSE.td X86InstrX86-64.td
Message-ID: <200609110220.k8B2KBm2027549@zion.cs.uiuc.edu>



Changes in directory llvm/lib/Target/X86:

X86ISelLowering.cpp updated: 1.253 -> 1.254
X86ISelLowering.h updated: 1.71 -> 1.72
X86InstrInfo.td updated: 1.285 -> 1.286
X86InstrSSE.td updated: 1.131 -> 1.132
X86InstrX86-64.td updated: 1.2 -> 1.3
---
Log message:

X86ISD::CMP now produces a chain as well as a flag. Make that the chain
operand of a conditional branch to allow load folding into CMP / TEST
instructions.


---
Diffs of the changes:  (+132 -158)

 X86ISelLowering.cpp |  259 +++++++++++++++++++++++-----------------------------
 X86ISelLowering.h   |    2 
 X86InstrInfo.td     |   20 +---
 X86InstrSSE.td      |    4 
 X86InstrX86-64.td   |    5 -
 5 files changed, 132 insertions(+), 158 deletions(-)


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.253 llvm/lib/Target/X86/X86ISelLowering.cpp:1.254
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.253	Fri Sep  8 01:48:29 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp	Sun Sep 10 21:19:56 2006
@@ -3394,9 +3394,9 @@
     SDOperand ShOpLo = Op.getOperand(0);
     SDOperand ShOpHi = Op.getOperand(1);
     SDOperand ShAmt  = Op.getOperand(2);
-    SDOperand Tmp1 = isSRA ? DAG.getNode(ISD::SRA, MVT::i32, ShOpHi,
-                                         DAG.getConstant(31, MVT::i8))
-                           : DAG.getConstant(0, MVT::i32);
+    SDOperand Tmp1 = isSRA ?
+      DAG.getNode(ISD::SRA, MVT::i32, ShOpHi, DAG.getConstant(31, MVT::i8)) :
+      DAG.getConstant(0, MVT::i32);
 
     SDOperand Tmp2, Tmp3;
     if (Op.getOpcode() == ISD::SHL_PARTS) {
@@ -3407,25 +3407,23 @@
       Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, MVT::i32, ShOpHi, ShAmt);
     }
 
-    SDOperand InFlag =
-      DAG.getNode(X86ISD::CMP, MVT::Flag,
-                  DAG.getNode(ISD::AND, MVT::i8, 
-                              ShAmt, DAG.getConstant(32, MVT::i8)),
-                  DAG.getConstant(0, MVT::i8));
+    const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
+    SDOperand AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt,
+                                    DAG.getConstant(32, MVT::i8));
+    SDOperand COps[]={DAG.getEntryNode(), AndNode, DAG.getConstant(0, MVT::i8)};
+    SDOperand InFlag = DAG.getNode(X86ISD::CMP, VTs, 2, COps, 3).getValue(1);
 
     SDOperand Hi, Lo;
     SDOperand CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8);
 
-    std::vector<MVT::ValueType> Tys;
-    Tys.push_back(MVT::i32);
-    Tys.push_back(MVT::Flag);
-    std::vector<SDOperand> Ops;
+    VTs = DAG.getNodeValueTypes(MVT::i32, MVT::Flag);
+    SmallVector<SDOperand, 4> Ops;
     if (Op.getOpcode() == ISD::SHL_PARTS) {
       Ops.push_back(Tmp2);
       Ops.push_back(Tmp3);
       Ops.push_back(CC);
       Ops.push_back(InFlag);
-      Hi = DAG.getNode(X86ISD::CMOV, Tys, &Ops[0], Ops.size());
+      Hi = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
       InFlag = Hi.getValue(1);
 
       Ops.clear();
@@ -3433,13 +3431,13 @@
       Ops.push_back(Tmp1);
       Ops.push_back(CC);
       Ops.push_back(InFlag);
-      Lo = DAG.getNode(X86ISD::CMOV, Tys, &Ops[0], Ops.size());
+      Lo = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
     } else {
       Ops.push_back(Tmp2);
       Ops.push_back(Tmp3);
       Ops.push_back(CC);
       Ops.push_back(InFlag);
-      Lo = DAG.getNode(X86ISD::CMOV, Tys, &Ops[0], Ops.size());
+      Lo = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
       InFlag = Lo.getValue(1);
 
       Ops.clear();
@@ -3447,16 +3445,14 @@
       Ops.push_back(Tmp1);
       Ops.push_back(CC);
       Ops.push_back(InFlag);
-      Hi = DAG.getNode(X86ISD::CMOV, Tys, &Ops[0], Ops.size());
+      Hi = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
     }
 
-    Tys.clear();
-    Tys.push_back(MVT::i32);
-    Tys.push_back(MVT::i32);
+    VTs = DAG.getNodeValueTypes(MVT::i32, MVT::i32);
     Ops.clear();
     Ops.push_back(Lo);
     Ops.push_back(Hi);
-    return DAG.getNode(ISD::MERGE_VALUES, Tys, &Ops[0], Ops.size());
+    return DAG.getNode(ISD::MERGE_VALUES, VTs, 2, &Ops[0], Ops.size());
 }
 
 SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
@@ -3613,163 +3609,139 @@
   return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask);
 }
 
-SDOperand X86TargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
+SDOperand X86TargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG,
+                                        SDOperand Chain) {
   assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
   SDOperand Cond;
+  SDOperand Op0 = Op.getOperand(0);
+  SDOperand Op1 = Op.getOperand(1);
   SDOperand CC = Op.getOperand(2);
   ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
+  const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
   bool isFP = MVT::isFloatingPoint(Op.getOperand(1).getValueType());
   bool Flip;
   unsigned X86CC;
-  if (translateX86CC(CC, isFP, X86CC, Flip)) {
-    if (Flip)
-      Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
-                         Op.getOperand(1), Op.getOperand(0));
-    else
-      Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
-                         Op.getOperand(0), Op.getOperand(1));
-    return DAG.getNode(X86ISD::SETCC, MVT::i8, 
-                       DAG.getConstant(X86CC, MVT::i8), Cond);
-  } else {
-    assert(isFP && "Illegal integer SetCC!");
 
-    Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
-                       Op.getOperand(0), Op.getOperand(1));
-    std::vector<MVT::ValueType> Tys;
-    std::vector<SDOperand> Ops;
-    switch (SetCCOpcode) {
-      default: assert(false && "Illegal floating point SetCC!");
-      case ISD::SETOEQ: {  // !PF & ZF
-        Tys.push_back(MVT::i8);
-        Tys.push_back(MVT::Flag);
-        Ops.push_back(DAG.getConstant(X86ISD::COND_NP, MVT::i8));
-        Ops.push_back(Cond);
-        SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, &Ops[0], Ops.size());
-        SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
-                                     DAG.getConstant(X86ISD::COND_E, MVT::i8),
-                                     Tmp1.getValue(1));
-        return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
-      }
-      case ISD::SETUNE: {  // PF | !ZF
-        Tys.push_back(MVT::i8);
-        Tys.push_back(MVT::Flag);
-        Ops.push_back(DAG.getConstant(X86ISD::COND_P, MVT::i8));
-        Ops.push_back(Cond);
-        SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, &Ops[0], Ops.size());
-        SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
-                                     DAG.getConstant(X86ISD::COND_NE, MVT::i8),
-                                     Tmp1.getValue(1));
-        return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
-      }
-    }
+  VTs = DAG.getNodeValueTypes(MVT::i8, MVT::Flag);
+  if (translateX86CC(CC, isFP, X86CC, Flip)) {
+    if (Flip) std::swap(Op0, Op1);
+    SDOperand Ops1[] = { Chain, Op0, Op1 };
+    Cond = DAG.getNode(X86ISD::CMP, VTs, 2, Ops1, 3).getValue(1);
+    SDOperand Ops2[] = { DAG.getConstant(X86CC, MVT::i8), Cond };
+    return DAG.getNode(X86ISD::SETCC, VTs, 2, Ops2, 2);
+  }
+
+  assert(isFP && "Illegal integer SetCC!");
+
+  SDOperand COps[] = { Chain, Op0, Op1 };
+  Cond = DAG.getNode(X86ISD::CMP, VTs, 2, COps, 3).getValue(1);
+
+  switch (SetCCOpcode) {
+  default: assert(false && "Illegal floating point SetCC!");
+  case ISD::SETOEQ: {  // !PF & ZF
+    SDOperand Ops1[] = { DAG.getConstant(X86ISD::COND_NP, MVT::i8), Cond };
+    SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, VTs, 2, Ops1, 2);
+    SDOperand Ops2[] = { DAG.getConstant(X86ISD::COND_E, MVT::i8),
+                         Tmp1.getValue(1) };
+    SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, VTs, 2, Ops2, 2);
+    return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
+  }
+  case ISD::SETUNE: {  // PF | !ZF
+    SDOperand Ops1[] = { DAG.getConstant(X86ISD::COND_P, MVT::i8), Cond };
+    SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, VTs, 2, Ops1, 2);
+    SDOperand Ops2[] = { DAG.getConstant(X86ISD::COND_NE, MVT::i8),
+                         Tmp1.getValue(1) };
+    SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, VTs, 2, Ops2, 2);
+    return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
+  }
   }
 }
 
 SDOperand X86TargetLowering::LowerSELECT(SDOperand Op, SelectionDAG &DAG) {
-  MVT::ValueType VT = Op.getValueType();
-  bool isFPStack = MVT::isFloatingPoint(VT) && !X86ScalarSSE;
-  bool addTest   = false;
-  SDOperand Op0 = Op.getOperand(0);
-  SDOperand Cond, CC;
-  if (Op0.getOpcode() == ISD::SETCC)
-    Op0 = LowerOperation(Op0, DAG);
+  bool addTest = true;
+  SDOperand Chain = DAG.getEntryNode();
+  SDOperand Cond  = Op.getOperand(0);
+  SDOperand CC;
+  const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
+
+  if (Cond.getOpcode() == ISD::SETCC)
+    Cond = LowerSETCC(Cond, DAG, Chain);
+
+  if (Cond.getOpcode() == X86ISD::SETCC) {
+    CC = Cond.getOperand(0);
 
-  if (Op0.getOpcode() == X86ISD::SETCC) {
     // If condition flag is set by a X86ISD::CMP, then make a copy of it
-    // (since flag operand cannot be shared). If the X86ISD::SETCC does not
-    // have another use it will be eliminated.
-    // If the X86ISD::SETCC has more than one use, then it's probably better
+    // (since flag operand cannot be shared). Use it as the condition setting
+    // operand in place of the X86ISD::SETCC.
+    // If the X86ISD::SETCC has more than one use, then perhaps it's better
     // to use a test instead of duplicating the X86ISD::CMP (for register
-    // pressure reason).
-    unsigned CmpOpc = Op0.getOperand(1).getOpcode();
-    if (CmpOpc == X86ISD::CMP || CmpOpc == X86ISD::COMI ||
-        CmpOpc == X86ISD::UCOMI) {
-      if (!Op0.hasOneUse()) {
-        std::vector<MVT::ValueType> Tys;
-        for (unsigned i = 0; i < Op0.Val->getNumValues(); ++i)
-          Tys.push_back(Op0.Val->getValueType(i));
-        std::vector<SDOperand> Ops;
-        for (unsigned i = 0; i < Op0.getNumOperands(); ++i)
-          Ops.push_back(Op0.getOperand(i));
-        Op0 = DAG.getNode(X86ISD::SETCC, Tys, &Ops[0], Ops.size());
-      }
-
-      CC   = Op0.getOperand(0);
-      Cond = Op0.getOperand(1);
-      // Make a copy as flag result cannot be used by more than one.
-      Cond = DAG.getNode(CmpOpc, MVT::Flag,
-                         Cond.getOperand(0), Cond.getOperand(1));
-      addTest =
-        isFPStack && !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
-    } else
-      addTest = true;
-  } else
-    addTest = true;
+    // pressure reason)?
+    SDOperand Cmp = Cond.getOperand(1);
+    unsigned Opc = Cmp.getOpcode();
+    bool IllegalFPCMov = !X86ScalarSSE &&
+      MVT::isFloatingPoint(Op.getValueType()) &&
+      !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
+    if ((Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) &&
+        !IllegalFPCMov) {
+      SDOperand Ops[] = { Chain, Cmp.getOperand(1), Cmp.getOperand(2) };
+      Cond = DAG.getNode(Opc, VTs, 2, Ops, 3);
+      addTest = false;
+    }
+  }
 
   if (addTest) {
     CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8);
-    Cond = DAG.getNode(X86ISD::CMP, MVT::Flag, Op0,
-                       DAG.getConstant(0, MVT::i8));
+    SDOperand Ops[] = { Chain, Cond, DAG.getConstant(0, MVT::i8) };
+    Cond = DAG.getNode(X86ISD::CMP, VTs, 2, Ops, 3);
   }
 
-  std::vector<MVT::ValueType> Tys;
-  Tys.push_back(Op.getValueType());
-  Tys.push_back(MVT::Flag);
-  std::vector<SDOperand> Ops;
+  VTs = DAG.getNodeValueTypes(Op.getValueType(), MVT::Flag);
+  SmallVector<SDOperand, 4> Ops;
   // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
   // condition is true.
   Ops.push_back(Op.getOperand(2));
   Ops.push_back(Op.getOperand(1));
   Ops.push_back(CC);
-  Ops.push_back(Cond);
-  return DAG.getNode(X86ISD::CMOV, Tys, &Ops[0], Ops.size());
+  Ops.push_back(Cond.getValue(1));
+  return DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
 }
 
 SDOperand X86TargetLowering::LowerBRCOND(SDOperand Op, SelectionDAG &DAG) {
-  bool addTest = false;
+  bool addTest = true;
+  SDOperand Chain = Op.getOperand(0);
   SDOperand Cond  = Op.getOperand(1);
   SDOperand Dest  = Op.getOperand(2);
   SDOperand CC;
+  const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
+
   if (Cond.getOpcode() == ISD::SETCC)
-    Cond = LowerOperation(Cond, DAG);
+    Cond = LowerSETCC(Cond, DAG, Chain);
 
   if (Cond.getOpcode() == X86ISD::SETCC) {
+    CC = Cond.getOperand(0);
+
     // If condition flag is set by a X86ISD::CMP, then make a copy of it
-    // (since flag operand cannot be shared). If the X86ISD::SETCC does not
-    // have another use it will be eliminated.
-    // If the X86ISD::SETCC has more than one use, then it's probably better
+    // (since flag operand cannot be shared). Use it as the condition setting
+    // operand in place of the X86ISD::SETCC.
+    // If the X86ISD::SETCC has more than one use, then perhaps it's better
     // to use a test instead of duplicating the X86ISD::CMP (for register
-    // pressure reason).
-    unsigned CmpOpc = Cond.getOperand(1).getOpcode();
-    if (CmpOpc == X86ISD::CMP || CmpOpc == X86ISD::COMI ||
-        CmpOpc == X86ISD::UCOMI) {
-      if (!Cond.hasOneUse()) {
-        std::vector<MVT::ValueType> Tys;
-        for (unsigned i = 0; i < Cond.Val->getNumValues(); ++i)
-          Tys.push_back(Cond.Val->getValueType(i));
-        std::vector<SDOperand> Ops;
-        for (unsigned i = 0; i < Cond.getNumOperands(); ++i)
-          Ops.push_back(Cond.getOperand(i));
-        Cond = DAG.getNode(X86ISD::SETCC, Tys, &Ops[0], Ops.size());
-      }
-
-      CC   = Cond.getOperand(0);
-      Cond = Cond.getOperand(1);
-      // Make a copy as flag result cannot be used by more than one.
-      Cond = DAG.getNode(CmpOpc, MVT::Flag,
-                         Cond.getOperand(0), Cond.getOperand(1));
-    } else
-      addTest = true;
-  } else
-    addTest = true;
+    // pressure reason)?
+    SDOperand Cmp = Cond.getOperand(1);
+    unsigned Opc = Cmp.getOpcode();
+    if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) {
+      SDOperand Ops[] = { Chain, Cmp.getOperand(1), Cmp.getOperand(2) };
+      Cond = DAG.getNode(Opc, VTs, 2, Ops, 3);
+      addTest = false;
+    }
+  }
 
   if (addTest) {
     CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8);
-    Cond = DAG.getNode(X86ISD::CMP, MVT::Flag, Cond,
-                       DAG.getConstant(0, MVT::i8));
+    SDOperand Ops[] = { Chain, Cond, DAG.getConstant(0, MVT::i8) };
+    Cond = DAG.getNode(X86ISD::CMP, VTs, 2, Ops, 3);
   }
   return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
-                     Op.getOperand(0), Op.getOperand(2), CC, Cond);
+                     Cond, Op.getOperand(2), CC, Cond.getValue(1));
 }
 
 SDOperand X86TargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
@@ -4382,13 +4354,18 @@
       CC = ISD::SETNE;
       break;
     }
+
     bool Flip;
     unsigned X86CC;
     translateX86CC(CC, true, X86CC, Flip);
-    SDOperand Cond = DAG.getNode(Opc, MVT::Flag, Op.getOperand(Flip?2:1),
-                                 Op.getOperand(Flip?1:2));
-    SDOperand SetCC = DAG.getNode(X86ISD::SETCC, MVT::i8, 
-                                  DAG.getConstant(X86CC, MVT::i8), Cond);
+
+    const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
+    SDOperand Ops1[] = { DAG.getEntryNode(), Op.getOperand(Flip?2:1),
+                         Op.getOperand(Flip?1:2) };
+    SDOperand Cond = DAG.getNode(Opc, VTs, 2, Ops1, 3);
+    VTs = DAG.getNodeValueTypes(MVT::i8, MVT::Flag);
+    SDOperand Ops2[] = { DAG.getConstant(X86CC, MVT::i8), Cond };
+    SDOperand SetCC = DAG.getNode(X86ISD::SETCC, VTs, 2, Ops2, 2);
     return DAG.getNode(ISD::ANY_EXTEND, MVT::i32, SetCC);
   }
   }
@@ -4414,7 +4391,7 @@
   case ISD::FP_TO_SINT:         return LowerFP_TO_SINT(Op, DAG);
   case ISD::FABS:               return LowerFABS(Op, DAG);
   case ISD::FNEG:               return LowerFNEG(Op, DAG);
-  case ISD::SETCC:              return LowerSETCC(Op, DAG);
+  case ISD::SETCC:              return LowerSETCC(Op, DAG, DAG.getEntryNode());
   case ISD::SELECT:             return LowerSELECT(Op, DAG);
   case ISD::BRCOND:             return LowerBRCOND(Op, DAG);
   case ISD::JumpTable:          return LowerJumpTable(Op, DAG);


Index: llvm/lib/Target/X86/X86ISelLowering.h
diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.71 llvm/lib/Target/X86/X86ISelLowering.h:1.72
--- llvm/lib/Target/X86/X86ISelLowering.h:1.71	Fri Sep  8 01:48:29 2006
+++ llvm/lib/Target/X86/X86ISelLowering.h	Sun Sep 10 21:19:56 2006
@@ -381,7 +381,7 @@
     SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG);
     SDOperand LowerFABS(SDOperand Op, SelectionDAG &DAG);
     SDOperand LowerFNEG(SDOperand Op, SelectionDAG &DAG);
-    SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG);
+    SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG, SDOperand Chain);
     SDOperand LowerSELECT(SDOperand Op, SelectionDAG &DAG);
     SDOperand LowerBRCOND(SDOperand Op, SelectionDAG &DAG);
     SDOperand LowerMEMSET(SDOperand Op, SelectionDAG &DAG);


Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.285 llvm/lib/Target/X86/X86InstrInfo.td:1.286
--- llvm/lib/Target/X86/X86InstrInfo.td:1.285	Fri Sep  8 01:48:29 2006
+++ llvm/lib/Target/X86/X86InstrInfo.td	Sun Sep 10 21:19:56 2006
@@ -51,7 +51,7 @@
 def X86shrd    : SDNode<"X86ISD::SHRD",     SDTIntShiftDOp>;
 
 def X86cmp     : SDNode<"X86ISD::CMP" ,     SDTX86CmpTest,
-                        [SDNPOutFlag]>;
+                        [SDNPHasChain, SDNPOutFlag]>;
 
 def X86cmov    : SDNode<"X86ISD::CMOV",     SDTX86Cmov,    
                         [SDNPInFlag, SDNPOutFlag]>;
@@ -2093,18 +2093,17 @@
                  "test{l} {$src2, $src1|$src1, $src2}",
                  [(X86cmp (and GR32:$src1, GR32:$src2), 0)]>;
 }
-// FIXME: These patterns are disabled until isel issue surrounding
-//CodeGen/X86/test-load-fold.ll is fixed.
+
 def TEST8rm  : I<0x84, MRMSrcMem, (ops GR8 :$src1, i8mem :$src2),
                  "test{b} {$src2, $src1|$src1, $src2}",
-                 [/*(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0)*/]>;
+                 [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0)]>;
 def TEST16rm : I<0x85, MRMSrcMem, (ops GR16:$src1, i16mem:$src2),
                  "test{w} {$src2, $src1|$src1, $src2}",
-                 [/*(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0)*/]>,
+                 [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0)]>,
                OpSize;
 def TEST32rm : I<0x85, MRMSrcMem, (ops GR32:$src1, i32mem:$src2),
                  "test{l} {$src2, $src1|$src1, $src2}",
-                 [/*(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0)*/]>;
+                 [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0)]>;
 
 def TEST8ri  : Ii8 <0xF6, MRM0r,                     // flags = GR8  & imm8
                     (ops GR8:$src1, i8imm:$src2),
@@ -2118,21 +2117,20 @@
                     (ops GR32:$src1, i32imm:$src2),
                     "test{l} {$src2, $src1|$src1, $src2}",
                     [(X86cmp (and GR32:$src1, imm:$src2), 0)]>;
-// FIXME: These patterns are disabled until isel issue surrounding
-//CodeGen/X86/test-load-fold.ll is fixed.
+
 def TEST8mi  : Ii8 <0xF6, MRM0m,                     // flags = [mem8]  & imm8
                     (ops i8mem:$src1, i8imm:$src2),
                     "test{b} {$src2, $src1|$src1, $src2}",
-                    [/*(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0)*/]>;
+                    [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0)]>;
 def TEST16mi : Ii16<0xF7, MRM0m,                     // flags = [mem16] & imm16
                     (ops i16mem:$src1, i16imm:$src2),
                     "test{w} {$src2, $src1|$src1, $src2}",
-                    [/*(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0)*/]>,
+                    [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0)]>,
                OpSize;
 def TEST32mi : Ii32<0xF7, MRM0m,                     // flags = [mem32] & imm32
                     (ops i32mem:$src1, i32imm:$src2),
                     "test{l} {$src2, $src1|$src1, $src2}",
-                    [/*(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0)*/]>;
+                    [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0)]>;
 
 
 // Condition code ops, incl. set if equal/not equal/...


Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.131 llvm/lib/Target/X86/X86InstrSSE.td:1.132
--- llvm/lib/Target/X86/X86InstrSSE.td:1.131	Tue Sep  5 00:59:25 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td	Sun Sep 10 21:19:56 2006
@@ -26,9 +26,9 @@
 def X86fxor    : SDNode<"X86ISD::FXOR",      SDTFPBinOp,
                         [SDNPCommutative, SDNPAssociative]>;
 def X86comi    : SDNode<"X86ISD::COMI",      SDTX86CmpTest,
-                        [SDNPOutFlag]>;
+                        [SDNPHasChain, SDNPOutFlag]>;
 def X86ucomi   : SDNode<"X86ISD::UCOMI",     SDTX86CmpTest,
-                        [SDNPOutFlag]>;
+                        [SDNPHasChain, SDNPOutFlag]>;
 def X86s2vec   : SDNode<"X86ISD::S2VEC",
                         SDTypeProfile<1, 1, []>, []>;
 def X86pextrw  : SDNode<"X86ISD::PEXTRW",


Index: llvm/lib/Target/X86/X86InstrX86-64.td
diff -u llvm/lib/Target/X86/X86InstrX86-64.td:1.2 llvm/lib/Target/X86/X86InstrX86-64.td:1.3
--- llvm/lib/Target/X86/X86InstrX86-64.td:1.2	Fri Sep  8 01:56:55 2006
+++ llvm/lib/Target/X86/X86InstrX86-64.td	Sun Sep 10 21:19:56 2006
@@ -711,14 +711,13 @@
                   [(X86cmp (and GR64:$src1, GR64:$src2), 0)]>;
 def TEST64rm : RI<0x85, MRMSrcMem, (ops GR64:$src1, i64mem:$src2),
                   "test{q} {$src2, $src1|$src1, $src2}",
-                  [/*(X86cmp (and GR64:$src1, (loadi64 addr:$src2)), 0)*/]>;
+                  [(X86cmp (and GR64:$src1, (loadi64 addr:$src2)), 0)]>;
 def TEST64ri32 : RIi32<0xF7, MRM0r, (ops GR64:$src1, i64i32imm:$src2),
                        "test{q} {$src2, $src1|$src1, $src2}",
                        [(X86cmp (and GR64:$src1, i64immSExt32:$src2), 0)]>;
 def TEST64mi32 : RIi32<0xF7, MRM0m, (ops i64mem:$src1, i64i32imm:$src2),
                        "test{q} {$src2, $src1|$src1, $src2}",
-                      [/*(X86cmp (and (loadi64 addr:$src1), i64immSExt32:$src2),
-                         0)*/]>;
+                  [(X86cmp (and (loadi64 addr:$src1), i64immSExt32:$src2), 0)]>;
 
 def CMP64rr : RI<0x39, MRMDestReg, (ops GR64:$src1, GR64:$src2),
                  "cmp{q} {$src2, $src1|$src1, $src2}",





From evan.cheng at apple.com  Sun Sep 10 21:24:57 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Sun, 10 Sep 2006 21:24:57 -0500
Subject: [llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp
Message-ID: <200609110224.k8B2Oved027631@zion.cs.uiuc.edu>



Changes in directory llvm/utils/TableGen:

DAGISelEmitter.cpp updated: 1.254 -> 1.255
---
Log message:

1) With X86 lowering change, the following can no longer happen since 
   the branch's chain is also produced by cmp.
          [ch, r : ld]
             ^ ^
             | |
      [XX]--/   \- [flag : cmp]
       ^             ^
       |             |
       \---[br flag]-

Remove an isel check which prevents loads from being folded into cmp / test
instructions.

2) Whenever possible, delete a selected node to allow more load folding
opportunities. Note not all nodes can be deleted after it has been
selected. Some may have simply morphed; some have not changed at all (e.g.
EntryToken).


---
Diffs of the changes:  (+16 -19)

 DAGISelEmitter.cpp |   35 ++++++++++++++++-------------------
 1 files changed, 16 insertions(+), 19 deletions(-)


Index: llvm/utils/TableGen/DAGISelEmitter.cpp
diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.254 llvm/utils/TableGen/DAGISelEmitter.cpp:1.255
--- llvm/utils/TableGen/DAGISelEmitter.cpp:1.254	Fri Sep  8 02:26:39 2006
+++ llvm/utils/TableGen/DAGISelEmitter.cpp	Sun Sep 10 21:24:43 2006
@@ -2246,24 +2246,6 @@
         emitCheck(RootName + ".hasOneUse()");
         EmittedUseCheck = true;
         if (NodeHasChain) {
-          // FIXME: Don't fold if 1) the parent node writes a flag, 2) the node
-          // has a chain use.
-          // This a workaround for this problem:
-          //
-          //          [ch, r : ld]
-          //             ^ ^
-          //             | |
-          //      [XX]--/   \- [flag : cmp]
-          //       ^             ^
-          //       |             |
-          //       \---[br flag]-
-          //
-          // cmp + br should be considered as a single node as they are flagged
-          // together. So, if the ld is folded into the cmp, the XX node in the
-          // graph is now both an operand and a use of the ld/cmp/br node.
-          if (NodeHasProperty(P, SDNodeInfo::SDNPOutFlag, ISE))
-            emitCheck(ParentName + ".Val->isOnlyUse(" +  RootName + ".Val)");
-
           // If the immediate use can somehow reach this node through another
           // path, then can't fold it either or it will create a cycle.
           // e.g. In the following diagram, XX can reach ld through YY. If
@@ -3629,6 +3611,16 @@
   OS << "  RemoveKilled();\n";
   OS << "}\n\n";
 
+  OS << "void DeleteNode(SDNode *N) {\n";
+  OS << "  CurDAG->DeleteNode(N);\n";
+  OS << "  for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); "
+     << "I != E; ++I) {\n";
+  OS << "    SDNode *Operand = I->Val;\n";
+  OS << "    if (Operand->use_empty())\n";
+  OS << "      DeleteNode(Operand);\n";
+  OS << "  }\n";
+  OS << "}\n";
+
   OS << "// SelectRoot - Top level entry to DAG isel.\n";
   OS << "SDOperand SelectRoot(SDOperand Root) {\n";
   OS << "  SelectRootInit();\n";
@@ -3649,7 +3641,12 @@
   OS << "    ISelQueue.pop_back();\n";
   OS << "    if (!isSelected(Node->getNodeId())) {\n";
   OS << "      SDNode *ResNode = Select(SDOperand(Node, 0));\n";
-  OS << "      if (ResNode && ResNode != Node) ReplaceUses(Node, ResNode);\n";
+  OS << "      if (ResNode != Node) {\n";
+  OS << "        if (ResNode)\n";
+  OS << "          ReplaceUses(Node, ResNode);\n";
+  OS << "        if (Node->use_empty()) // Don't delete EntryToken, etc.\n";
+  OS << "          DeleteNode(Node);\n";
+  OS << "      }\n";
   OS << "    }\n";
   OS << "  }\n";
   OS << "\n";





From evan.cheng at apple.com  Sun Sep 10 21:33:44 2006
From: evan.cheng at apple.com (Evan Cheng)
Date: Sun, 10 Sep 2006 21:33:44 -0500
Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/X86/cmp-test.ll
	test-not-cmp.ll
Message-ID: <200609110233.k8B2Xi6U027792@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CodeGen/X86:

cmp-test.ll added (r1.1)
test-not-cmp.ll (r1.1) removed
---
Log message:

Rename a test-not-cmp.ll to cmp-test.ll; add a test.

---
Diffs of the changes:  (+28 -0)

 cmp-test.ll |   28 ++++++++++++++++++++++++++++
 1 files changed, 28 insertions(+)


Index: llvm/test/Regression/CodeGen/X86/cmp-test.ll
diff -c /dev/null llvm/test/Regression/CodeGen/X86/cmp-test.ll:1.1
*** /dev/null	Sun Sep 10 21:33:39 2006
--- llvm/test/Regression/CodeGen/X86/cmp-test.ll	Sun Sep 10 21:33:29 2006
***************
*** 0 ****
--- 1,28 ----
+ ; RUN: llvm-as < %s | llc -march=x86 &&
+ ; RUN: llvm-as < %s | llc -march=x86 | grep cmp  | wc -l | grep 1 &&
+ ; RUN: llvm-as < %s | llc -march=x86 | grep test | wc -l | grep 1
+ 
+ int %f1(int %X, int* %y) {
+ 	%tmp = load int* %y
+ 	%tmp = seteq int %tmp, 0
+ 	br bool %tmp, label %ReturnBlock, label %cond_true
+ 
+ cond_true:
+ 	ret int 1
+ 
+ ReturnBlock:
+ 	ret int 0
+ }
+ 
+ int %f2(int %X, int* %y) {
+ 	%tmp = load int* %y
+         %tmp1 = shl int %tmp, ubyte 3
+ 	%tmp1 = seteq int %tmp1, 0
+ 	br bool %tmp1, label %ReturnBlock, label %cond_true
+ 
+ cond_true:
+ 	ret int 1
+ 
+ ReturnBlock:
+ 	ret int 0
+ }





From rafael.espindola at gmail.com  Fri Sep  8 07:47:20 2006
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Fri, 8 Sep 2006 07:47:20 -0500
Subject: [llvm-commits] CVS: llvm/test/Regression/CodeGen/ARM/select.ll
Message-ID: <200609081247.k88ClKDe012787@zion.cs.uiuc.edu>



Changes in directory llvm/test/Regression/CodeGen/ARM:

select.ll updated: 1.6 -> 1.7
---
Log message:

implement unconditional branches
fix select.ll



---
Diffs of the changes:  (+0 -1)

 select.ll |    1 -
 1 files changed, 1 deletion(-)


Index: llvm/test/Regression/CodeGen/ARM/select.ll
diff -u llvm/test/Regression/CodeGen/ARM/select.ll:1.6 llvm/test/Regression/CodeGen/ARM/select.ll:1.7
--- llvm/test/Regression/CodeGen/ARM/select.ll:1.6	Thu Sep  7 12:43:59 2006
+++ llvm/test/Regression/CodeGen/ARM/select.ll	Fri Sep  8 07:47:03 2006
@@ -1,5 +1,4 @@
 ; RUN: llvm-as < %s | llc -march=arm
-; XFAIL: *
 
 int %f(int %a) {
 entry: