From evan.cheng at apple.com Mon Mar 19 00:12:13 2007 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 19 Mar 2007 00:12:13 -0500 Subject: [llvm-commits] CVS: llvm-test/Makefile.programs Message-ID: <200703190512.l2J5CDgT022981@zion.cs.uiuc.edu> Changes in directory llvm-test: Makefile.programs updated: 1.261 -> 1.262 --- Log message: Reset x86 llcbeta to -enable-tail-merge. --- Diffs of the changes: (+1 -2) Makefile.programs | 3 +-- 1 files changed, 1 insertion(+), 2 deletions(-) Index: llvm-test/Makefile.programs diff -u llvm-test/Makefile.programs:1.261 llvm-test/Makefile.programs:1.262 --- llvm-test/Makefile.programs:1.261 Sat Mar 17 04:31:11 2007 +++ llvm-test/Makefile.programs Mon Mar 19 00:11:53 2007 @@ -223,8 +223,7 @@ LLCBETAOPTION := -sched=simple endif ifeq ($(ARCH),x86) -LLCBETAOPTION := -reduce-joining-phy-regs -#--enable-tail-merge +LLCBETAOPTION := -enable-tail-merge #-regalloc=local -fast endif ifeq ($(ARCH),Sparc) From zhousheng00 at gmail.com Mon Mar 19 00:22:37 2007 From: zhousheng00 at gmail.com (Zhou Sheng) Date: Mon, 19 Mar 2007 00:22:37 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/ADT/APInt.h Message-ID: <200703190522.l2J5Mb3D023519@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/ADT: APInt.h updated: 1.42 -> 1.43 --- Log message: Add isStrictPositive() to APInt to determine if this APInt Value > 0. --- Diffs of the changes: (+6 -0) APInt.h | 6 ++++++ 1 files changed, 6 insertions(+) Index: llvm/include/llvm/ADT/APInt.h diff -u llvm/include/llvm/ADT/APInt.h:1.42 llvm/include/llvm/ADT/APInt.h:1.43 --- llvm/include/llvm/ADT/APInt.h:1.42 Tue Mar 13 01:16:26 2007 +++ llvm/include/llvm/ADT/APInt.h Mon Mar 19 00:22:18 2007 @@ -374,6 +374,12 @@ return !isNegative(); } + /// This just tests if the value of this APInt is strictly positive (> 0). + /// @brief Determine if this APInt Value is strictly positive. + inline bool isStrictPositive() const { + return isPositive() && (*this) != 0; + } + /// Arithmetic right-shift this APInt by shiftAmt. /// @brief Arithmetic right-shift function. APInt ashr(uint32_t shiftAmt) const; From criswell at cs.uiuc.edu Mon Mar 19 00:38:01 2007 From: criswell at cs.uiuc.edu (John Criswell) Date: Mon, 19 Mar 2007 00:38:01 -0500 Subject: [llvm-commits] [see] CVS: llvm/lib/Target/CBackend/Writer.cpp Message-ID: <200703190538.l2J5c1VX024132@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/CBackend: Writer.cpp updated: 1.280.4.1 -> 1.280.4.2 --- Log message: Make the given functions with the const attribute. No, this should never be folded into a non-experimental LLVM branch. --- Diffs of the changes: (+8 -0) Writer.cpp | 8 ++++++++ 1 files changed, 8 insertions(+) Index: llvm/lib/Target/CBackend/Writer.cpp diff -u llvm/lib/Target/CBackend/Writer.cpp:1.280.4.1 llvm/lib/Target/CBackend/Writer.cpp:1.280.4.2 --- llvm/lib/Target/CBackend/Writer.cpp:1.280.4.1 Tue Feb 20 12:21:25 2007 +++ llvm/lib/Target/CBackend/Writer.cpp Mon Mar 19 00:37:44 2007 @@ -1246,6 +1246,14 @@ if (StaticDtors.count(I)) Out << " __ATTRIBUTE_DTOR__"; +#if 1 + if ((I->getName() == "exactcheck") || (I->getName() == "exactcheck2") || + (I->getName() == "poolcheck") || + (I->getName() == "poolcheckarray") || (I->getName() == "poolcheckarray_i") || + (I->getName() == "pchk_bounds") || (I->getName() == "pchk_bounds_i")) { + Out << " __attribute__ ((const))"; + } +#endif if (I->hasName() && I->getName()[0] == 1) Out << " LLVM_ASM(\"" << I->getName().c_str()+1 << "\")"; From evan.cheng at apple.com Mon Mar 19 01:19:45 2007 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 19 Mar 2007 01:19:45 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetInstrInfo.h Message-ID: <200703190619.l2J6JjHN031960@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/Target: TargetInstrInfo.h updated: 1.113 -> 1.114 --- Log message: Add a TargetInstrDescriptor flag to mark an instruction as "re-materializable". It means the instruction can be easily re-materialized at any point. e.g. constant generation, load from constantpool. --- Diffs of the changes: (+7 -0) TargetInstrInfo.h | 7 +++++++ 1 files changed, 7 insertions(+) Index: llvm/include/llvm/Target/TargetInstrInfo.h diff -u llvm/include/llvm/Target/TargetInstrInfo.h:1.113 llvm/include/llvm/Target/TargetInstrInfo.h:1.114 --- llvm/include/llvm/Target/TargetInstrInfo.h:1.113 Fri Mar 16 03:41:06 2007 +++ llvm/include/llvm/Target/TargetInstrInfo.h Mon Mar 19 01:19:16 2007 @@ -78,6 +78,10 @@ // execution. const unsigned M_PREDICATED = 1 << 12; +// M_REMATERIALIZIBLE - Set if this instruction can be trivally re-materialized +// at any time, e.g. constant generation, load from constant pool. +const unsigned M_REMATERIALIZIBLE = 1 << 13; + // Machine operand flags // M_LOOK_UP_PTR_REG_CLASS - Set if this operand is a pointer value and it @@ -207,6 +211,9 @@ bool isPredicated(MachineOpCode Opcode) const { return get(Opcode).Flags & M_PREDICATED; } + bool isReMaterializable(MachineOpCode Opcode) const { + return get(Opcode).Flags & M_REMATERIALIZIBLE; + } bool isCommutableInstr(MachineOpCode Opcode) const { return get(Opcode).Flags & M_COMMUTABLE; } From evan.cheng at apple.com Mon Mar 19 01:20:58 2007 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 19 Mar 2007 01:20:58 -0500 Subject: [llvm-commits] CVS: llvm/utils/TableGen/CodeGenInstruction.h CodeGenTarget.cpp InstrInfoEmitter.cpp Message-ID: <200703190620.l2J6Kw1A032001@zion.cs.uiuc.edu> Changes in directory llvm/utils/TableGen: CodeGenInstruction.h updated: 1.25 -> 1.26 CodeGenTarget.cpp updated: 1.85 -> 1.86 InstrInfoEmitter.cpp updated: 1.56 -> 1.57 --- Log message: Recognize target instruction flag 'isReMaterializable'. --- Diffs of the changes: (+3 -0) CodeGenInstruction.h | 1 + CodeGenTarget.cpp | 1 + InstrInfoEmitter.cpp | 1 + 3 files changed, 3 insertions(+) Index: llvm/utils/TableGen/CodeGenInstruction.h diff -u llvm/utils/TableGen/CodeGenInstruction.h:1.25 llvm/utils/TableGen/CodeGenInstruction.h:1.26 --- llvm/utils/TableGen/CodeGenInstruction.h:1.25 Wed Nov 15 17:23:02 2006 +++ llvm/utils/TableGen/CodeGenInstruction.h Mon Mar 19 01:20:37 2007 @@ -91,6 +91,7 @@ bool isConvertibleToThreeAddress; bool isCommutable; bool isTerminator; + bool isReMaterializable; bool hasDelaySlot; bool usesCustomDAGSchedInserter; bool hasVariableNumberOfOperands; Index: llvm/utils/TableGen/CodeGenTarget.cpp diff -u llvm/utils/TableGen/CodeGenTarget.cpp:1.85 llvm/utils/TableGen/CodeGenTarget.cpp:1.86 --- llvm/utils/TableGen/CodeGenTarget.cpp:1.85 Tue Feb 27 16:08:27 2007 +++ llvm/utils/TableGen/CodeGenTarget.cpp Mon Mar 19 01:20:37 2007 @@ -356,6 +356,7 @@ isConvertibleToThreeAddress = R->getValueAsBit("isConvertibleToThreeAddress"); isCommutable = R->getValueAsBit("isCommutable"); isTerminator = R->getValueAsBit("isTerminator"); + isReMaterializable = R->getValueAsBit("isReMaterializable"); hasDelaySlot = R->getValueAsBit("hasDelaySlot"); usesCustomDAGSchedInserter = R->getValueAsBit("usesCustomDAGSchedInserter"); hasCtrlDep = R->getValueAsBit("hasCtrlDep"); Index: llvm/utils/TableGen/InstrInfoEmitter.cpp diff -u llvm/utils/TableGen/InstrInfoEmitter.cpp:1.56 llvm/utils/TableGen/InstrInfoEmitter.cpp:1.57 --- llvm/utils/TableGen/InstrInfoEmitter.cpp:1.56 Fri Jan 26 11:29:20 2007 +++ llvm/utils/TableGen/InstrInfoEmitter.cpp Mon Mar 19 01:20:37 2007 @@ -240,6 +240,7 @@ if (Inst.isConvertibleToThreeAddress) OS << "|M_CONVERTIBLE_TO_3_ADDR"; if (Inst.isCommutable) OS << "|M_COMMUTABLE"; if (Inst.isTerminator) OS << "|M_TERMINATOR_FLAG"; + if (Inst.isReMaterializable) OS << "|M_REMATERIALIZIBLE"; if (Inst.usesCustomDAGSchedInserter) OS << "|M_USES_CUSTOM_DAG_SCHED_INSERTION"; if (Inst.hasVariableNumberOfOperands) From evan.cheng at apple.com Mon Mar 19 01:22:28 2007 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 19 Mar 2007 01:22:28 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Target.td Message-ID: <200703190622.l2J6MS69032746@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target: Target.td updated: 1.94 -> 1.95 --- Log message: Added isReMaterializable. --- Diffs of the changes: (+1 -0) Target.td | 1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Target/Target.td diff -u llvm/lib/Target/Target.td:1.94 llvm/lib/Target/Target.td:1.95 --- llvm/lib/Target/Target.td:1.94 Tue Feb 27 00:59:52 2007 +++ llvm/lib/Target/Target.td Mon Mar 19 01:22:07 2007 @@ -165,6 +165,7 @@ bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote? bit isCommutable = 0; // Is this 3 operand instruction commutable? bit isTerminator = 0; // Is this part of the terminator for a basic block? + bit isReMaterializable = 0; // Is this instruction re-materializable? bit hasDelaySlot = 0; // Does this instruction have an delay slot? bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help. bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains? From evan.cheng at apple.com Mon Mar 19 02:09:49 2007 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 19 Mar 2007 02:09:49 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.td ARMInstrThumb.td Message-ID: <200703190709.l2J79ntm004346@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/ARM: ARMInstrInfo.td updated: 1.88 -> 1.89 ARMInstrThumb.td updated: 1.14 -> 1.15 --- Log message: Constant generation instructions are re-materializable. --- Diffs of the changes: (+11 -5) ARMInstrInfo.td | 15 ++++++++++----- ARMInstrThumb.td | 1 + 2 files changed, 11 insertions(+), 5 deletions(-) Index: llvm/lib/Target/ARM/ARMInstrInfo.td diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.88 llvm/lib/Target/ARM/ARMInstrInfo.td:1.89 --- llvm/lib/Target/ARM/ARMInstrInfo.td:1.88 Sat Feb 3 03:11:58 2007 +++ llvm/lib/Target/ARM/ARMInstrInfo.td Mon Mar 19 02:09:02 2007 @@ -137,7 +137,7 @@ PatLeaf<(imm), [{ return ARM_AM::getSOImmVal(-(int)N->getValue()) != -1; }], so_imm_neg_XFORM>; -def so_imm_not : +def so_imm_not : PatLeaf<(imm), [{ return ARM_AM::getSOImmVal(~(int)N->getValue()) != -1; }], so_imm_not_XFORM>; @@ -709,6 +709,8 @@ "mov $dst, $src", []>; def MOVrs : AI1<(ops GPR:$dst, so_reg:$src), "mov $dst, $src", [(set GPR:$dst, so_reg:$src)]>; + +let isReMaterializable = 1 in def MOVri : AI1<(ops GPR:$dst, so_imm:$src), "mov $dst, $src", [(set GPR:$dst, so_imm:$src)]>; @@ -806,10 +808,13 @@ defm EOR : AI1_bin_irs<"eor", BinOpFrag<(xor node:$LHS, node:$RHS)>>; defm BIC : AI1_bin_irs<"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>; -defm MVN : AI1_unary_irs<"mvn", not>; - -def : ARMPat<(i32 so_imm_not:$imm), - (MVNi so_imm_not:$imm)>; +def MVNr : AI<(ops GPR:$dst, GPR:$src), + "mvn $dst, $src", [(set GPR:$dst, (not GPR:$src))]>; +def MVNs : AI<(ops GPR:$dst, so_reg:$src), + "mvn $dst, $src", [(set GPR:$dst, (not so_reg:$src))]>; +let isReMaterializable = 1 in +def MVNi : AI<(ops GPR:$dst, so_imm:$imm), + "mvn $dst, $imm", [(set GPR:$dst, so_imm_not:$imm)]>; def : ARMPat<(and GPR:$src, so_imm_not:$imm), (BICri GPR:$src, so_imm_not:$imm)>; Index: llvm/lib/Target/ARM/ARMInstrThumb.td diff -u llvm/lib/Target/ARM/ARMInstrThumb.td:1.14 llvm/lib/Target/ARM/ARMInstrThumb.td:1.15 --- llvm/lib/Target/ARM/ARMInstrThumb.td:1.14 Tue Feb 6 18:06:56 2007 +++ llvm/lib/Target/ARM/ARMInstrThumb.td Mon Mar 19 02:09:02 2007 @@ -374,6 +374,7 @@ "lsr $dst, $rhs", [(set GPR:$dst, (srl GPR:$lhs, GPR:$rhs))]>; +let isReMaterializable = 1 in def tMOVri8 : TI<(ops GPR:$dst, i32imm:$src), "mov $dst, $src", [(set GPR:$dst, imm0_255:$src)]>; From evan.cheng at apple.com Mon Mar 19 02:20:21 2007 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 19 Mar 2007 02:20:21 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp ARMInstrInfo.td ARMInstrThumb.td Message-ID: <200703190720.l2J7KLBt005231@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/ARM: ARMISelDAGToDAG.cpp updated: 1.108 -> 1.109 ARMInstrInfo.td updated: 1.89 -> 1.90 ARMInstrThumb.td updated: 1.15 -> 1.16 --- Log message: Special LDR instructions to load from non-pc-relative constantpools. These are rematerializable. Only used for constant generation for now. --- Diffs of the changes: (+12 -2) ARMISelDAGToDAG.cpp | 4 ++-- ARMInstrInfo.td | 5 +++++ ARMInstrThumb.td | 5 +++++ 3 files changed, 12 insertions(+), 2 deletions(-) Index: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp diff -u llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.108 llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.109 --- llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.108 Tue Mar 13 16:05:54 2007 +++ llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp Mon Mar 19 02:20:03 2007 @@ -551,7 +551,7 @@ SDNode *ResNode; if (Subtarget->isThumb()) - ResNode = CurDAG->getTargetNode(ARM::tLDRpci, MVT::i32, MVT::Other, + ResNode = CurDAG->getTargetNode(ARM::tLDRcp, MVT::i32, MVT::Other, CPIdx, CurDAG->getEntryNode()); else { SDOperand Ops[] = { @@ -560,7 +560,7 @@ CurDAG->getTargetConstant(0, MVT::i32), CurDAG->getEntryNode() }; - ResNode = CurDAG->getTargetNode(ARM::LDR, MVT::i32, MVT::Other, Ops, 4); + ResNode=CurDAG->getTargetNode(ARM::LDRcp, MVT::i32, MVT::Other, Ops, 4); } ReplaceUses(Op, SDOperand(ResNode, 0)); return NULL; Index: llvm/lib/Target/ARM/ARMInstrInfo.td diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.89 llvm/lib/Target/ARM/ARMInstrInfo.td:1.90 --- llvm/lib/Target/ARM/ARMInstrInfo.td:1.89 Mon Mar 19 02:09:02 2007 +++ llvm/lib/Target/ARM/ARMInstrInfo.td Mon Mar 19 02:20:03 2007 @@ -580,6 +580,11 @@ "ldr $dst, $addr", [(set GPR:$dst, (load addrmode2:$addr))]>; +// Special LDR for loads from non-pc-relative constpools. +let isReMaterializable = 1 in +def LDRcp : AI2<(ops GPR:$dst, addrmode2:$addr), + "ldr $dst, $addr", []>; + // Loads with zero extension def LDRH : AI3<(ops GPR:$dst, addrmode3:$addr), "ldrh $dst, $addr", Index: llvm/lib/Target/ARM/ARMInstrThumb.td diff -u llvm/lib/Target/ARM/ARMInstrThumb.td:1.15 llvm/lib/Target/ARM/ARMInstrThumb.td:1.16 --- llvm/lib/Target/ARM/ARMInstrThumb.td:1.15 Mon Mar 19 02:09:02 2007 +++ llvm/lib/Target/ARM/ARMInstrThumb.td Mon Mar 19 02:20:03 2007 @@ -248,6 +248,11 @@ def tLDRpci : TIs<(ops GPR:$dst, i32imm:$addr), "ldr $dst, $addr", [(set GPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>; + +// Special LDR for loads from non-pc-relative constpools. +let isReMaterializable = 1 in +def tLDRcp : TIs<(ops GPR:$dst, i32imm:$addr), + "ldr $dst, $addr", []>; } // isLoad let isStore = 1 in { From evan.cheng at apple.com Mon Mar 19 02:48:19 2007 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 19 Mar 2007 02:48:19 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp ARMISelLowering.cpp ARMInstrInfo.cpp ARMInstrInfo.td ARMInstrThumb.td ARMRegisterInfo.cpp Message-ID: <200703190748.l2J7mJRf005712@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/ARM: ARMISelDAGToDAG.cpp updated: 1.109 -> 1.110 ARMISelLowering.cpp updated: 1.24 -> 1.25 ARMInstrInfo.cpp updated: 1.16 -> 1.17 ARMInstrInfo.td updated: 1.90 -> 1.91 ARMInstrThumb.td updated: 1.16 -> 1.17 ARMRegisterInfo.cpp updated: 1.82 -> 1.83 --- Log message: Fix naming inconsistencies. --- Diffs of the changes: (+30 -30) ARMISelDAGToDAG.cpp | 2 +- ARMISelLowering.cpp | 2 +- ARMInstrInfo.cpp | 4 ++-- ARMInstrInfo.td | 10 +++++----- ARMInstrThumb.td | 8 ++++---- ARMRegisterInfo.cpp | 34 +++++++++++++++++----------------- 6 files changed, 30 insertions(+), 30 deletions(-) Index: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp diff -u llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.109 llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.110 --- llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.109 Mon Mar 19 02:20:03 2007 +++ llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp Mon Mar 19 02:48:02 2007 @@ -384,7 +384,7 @@ // We must materialize a zero in a reg! Returning an constant here won't // work since its node is -1 so it won't get added to the selection queue. // Explicitly issue a tMOVri8 node! - Offset = SDOperand(CurDAG->getTargetNode(ARM::tMOVri8, MVT::i32, + Offset = SDOperand(CurDAG->getTargetNode(ARM::tMOVi8, MVT::i32, CurDAG->getTargetConstant(0, MVT::i32)), 0); return true; } Index: llvm/lib/Target/ARM/ARMISelLowering.cpp diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.24 llvm/lib/Target/ARM/ARMISelLowering.cpp:1.25 --- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.24 Fri Mar 16 17:54:16 2007 +++ llvm/lib/Target/ARM/ARMISelLowering.cpp Mon Mar 19 02:48:02 2007 @@ -672,7 +672,7 @@ // one of the above mentioned nodes. It has to be wrapped because otherwise // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only // be used to form addressing mode. These wrapped nodes will be selected -// into MOVri. +// into MOVi. static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) { MVT::ValueType PtrVT = Op.getValueType(); ConstantPoolSDNode *CP = cast(Op); Index: llvm/lib/Target/ARM/ARMInstrInfo.cpp diff -u llvm/lib/Target/ARM/ARMInstrInfo.cpp:1.16 llvm/lib/Target/ARM/ARMInstrInfo.cpp:1.17 --- llvm/lib/Target/ARM/ARMInstrInfo.cpp:1.16 Tue Feb 6 18:06:56 2007 +++ llvm/lib/Target/ARM/ARMInstrInfo.cpp Mon Mar 19 02:48:02 2007 @@ -50,8 +50,8 @@ SrcReg = MI.getOperand(1).getReg(); DstReg = MI.getOperand(0).getReg(); return true; - case ARM::MOVrr: - case ARM::tMOVrr: + case ARM::MOVr: + case ARM::tMOVr: assert(MI.getNumOperands() == 2 && MI.getOperand(0).isRegister() && MI.getOperand(1).isRegister() && "Invalid ARM MOV instruction"); Index: llvm/lib/Target/ARM/ARMInstrInfo.td diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.90 llvm/lib/Target/ARM/ARMInstrInfo.td:1.91 --- llvm/lib/Target/ARM/ARMInstrInfo.td:1.90 Mon Mar 19 02:20:03 2007 +++ llvm/lib/Target/ARM/ARMInstrInfo.td Mon Mar 19 02:48:02 2007 @@ -710,13 +710,13 @@ // Move Instructions. // -def MOVrr : AI1<(ops GPR:$dst, GPR:$src), +def MOVr : AI1<(ops GPR:$dst, GPR:$src), "mov $dst, $src", []>; -def MOVrs : AI1<(ops GPR:$dst, so_reg:$src), +def MOVs : AI1<(ops GPR:$dst, so_reg:$src), "mov $dst, $src", [(set GPR:$dst, so_reg:$src)]>; let isReMaterializable = 1 in -def MOVri : AI1<(ops GPR:$dst, so_imm:$src), +def MOVi : AI1<(ops GPR:$dst, so_imm:$src), "mov $dst, $src", [(set GPR:$dst, so_imm:$src)]>; // These aren't really mov instructions, but we have to define them this way @@ -728,7 +728,7 @@ def MOVsra_flag : AI1<(ops GPR:$dst, GPR:$src), "movs $dst, $src, asr #1", [(set GPR:$dst, (ARMsra_flag GPR:$src))]>; -def MOVrrx : AI1<(ops GPR:$dst, GPR:$src), +def MOVrx : AI1<(ops GPR:$dst, GPR:$src), "mov $dst, $src, rrx", [(set GPR:$dst, (ARMrrx GPR:$src))]>; @@ -1070,7 +1070,7 @@ // Two piece so_imms. def : ARMPat<(i32 so_imm2part:$src), - (ORRri (MOVri (so_imm2part_1 imm:$src)), + (ORRri (MOVi (so_imm2part_1 imm:$src)), (so_imm2part_2 imm:$src))>; def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS), Index: llvm/lib/Target/ARM/ARMInstrThumb.td diff -u llvm/lib/Target/ARM/ARMInstrThumb.td:1.16 llvm/lib/Target/ARM/ARMInstrThumb.td:1.17 --- llvm/lib/Target/ARM/ARMInstrThumb.td:1.16 Mon Mar 19 02:20:03 2007 +++ llvm/lib/Target/ARM/ARMInstrThumb.td Mon Mar 19 02:48:02 2007 @@ -380,7 +380,7 @@ [(set GPR:$dst, (srl GPR:$lhs, GPR:$rhs))]>; let isReMaterializable = 1 in -def tMOVri8 : TI<(ops GPR:$dst, i32imm:$src), +def tMOVi8 : TI<(ops GPR:$dst, i32imm:$src), "mov $dst, $src", [(set GPR:$dst, imm0_255:$src)]>; @@ -389,7 +389,7 @@ // Note: MOV(2) of two low regs updates the flags, so we emit this as 'cpy', // which is MOV(3). This also supports high registers. -def tMOVrr : TI<(ops GPR:$dst, GPR:$src), +def tMOVr : TI<(ops GPR:$dst, GPR:$src), "cpy $dst, $src", []>; def tMUL : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs), @@ -544,8 +544,8 @@ // Two piece imms. def : ThumbPat<(i32 thumb_immshifted:$src), - (tLSLri (tMOVri8 (thumb_immshifted_val imm:$src)), + (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)), (thumb_immshifted_shamt imm:$src))>; def : ThumbPat<(i32 imm0_255_comp:$src), - (tMVN (tMOVri8 (imm_comp_XFORM imm:$src)))>; + (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>; Index: llvm/lib/Target/ARM/ARMRegisterInfo.cpp diff -u llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.82 llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.83 --- llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.82 Tue Mar 6 18:12:18 2007 +++ llvm/lib/Target/ARM/ARMRegisterInfo.cpp Mon Mar 19 02:48:02 2007 @@ -185,7 +185,7 @@ if (RC == ARM::GPRRegisterClass) { MachineFunction &MF = *MBB.getParent(); ARMFunctionInfo *AFI = MF.getInfo(); - BuildMI(MBB, I, TII.get(AFI->isThumbFunction() ? ARM::tMOVrr : ARM::MOVrr), + BuildMI(MBB, I, TII.get(AFI->isThumbFunction() ? ARM::tMOVr : ARM::MOVr), DestReg).addReg(SrcReg); } else if (RC == ARM::SPRRegisterClass) BuildMI(MBB, I, TII.get(ARM::FCPYS), DestReg).addReg(SrcReg); @@ -214,7 +214,7 @@ MachineInstr *NewMI = NULL; switch (Opc) { default: break; - case ARM::MOVrr: { + case ARM::MOVr: { if (OpNum == 0) { // move -> store unsigned SrcReg = MI->getOperand(1).getReg(); NewMI = BuildMI(TII.get(ARM::STR)).addReg(SrcReg).addFrameIndex(FI) @@ -226,7 +226,7 @@ } break; } - case ARM::tMOVrr: { + case ARM::tMOVr: { if (OpNum == 0) { // move -> store unsigned SrcReg = MI->getOperand(1).getReg(); if (isPhysicalRegister(SrcReg) && !isLowRegister(SrcReg)) @@ -448,14 +448,14 @@ if (DestReg == ARM::SP) { assert(BaseReg == ARM::SP && "Unexpected!"); LdReg = ARM::R3; - BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::R12) + BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::R12) .addReg(ARM::R3, false, false, true); } if (NumBytes <= 255 && NumBytes >= 0) - BuildMI(MBB, MBBI, TII.get(ARM::tMOVri8), LdReg).addImm(NumBytes); + BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes); else if (NumBytes < 0 && NumBytes >= -255) { - BuildMI(MBB, MBBI, TII.get(ARM::tMOVri8), LdReg).addImm(NumBytes); + BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes); BuildMI(MBB, MBBI, TII.get(ARM::tNEG), LdReg) .addReg(LdReg, false, false, true); } else @@ -469,7 +469,7 @@ else MIB.addReg(LdReg).addReg(BaseReg, false, false, true); if (DestReg == ARM::SP) - BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::R3) + BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::R3) .addReg(ARM::R12, false, false, true); } @@ -538,7 +538,7 @@ BuildMI(MBB, MBBI, TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg) .addReg(BaseReg, false, false, true).addImm(ThisVal); } else { - BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), DestReg) + BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), DestReg) .addReg(BaseReg, false, false, true); } BaseReg = DestReg; @@ -627,7 +627,7 @@ int Chunk = (1 << 8) - 1; int ThisVal = (Imm > Chunk) ? Chunk : Imm; Imm -= ThisVal; - BuildMI(MBB, MBBI, TII.get(ARM::tMOVri8), DestReg).addImm(ThisVal); + BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), DestReg).addImm(ThisVal); if (Imm > 0) emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII); if (isSub) @@ -690,7 +690,7 @@ Offset += MI.getOperand(i+1).getImm(); if (Offset == 0) { // Turn it into a move. - MI.setInstrDescriptor(TII.get(ARM::MOVrr)); + MI.setInstrDescriptor(TII.get(ARM::MOVr)); MI.getOperand(i).ChangeToRegister(FrameReg, false); MI.RemoveOperand(i+1); return; @@ -741,7 +741,7 @@ if (Offset == 0) { // Turn it into a move. - MI.setInstrDescriptor(TII.get(ARM::tMOVrr)); + MI.setInstrDescriptor(TII.get(ARM::tMOVr)); MI.getOperand(i).ChangeToRegister(FrameReg, false); MI.RemoveOperand(i+1); return; @@ -909,12 +909,12 @@ unsigned TmpReg = ARM::R3; bool UseRR = false; if (ValReg == ARM::R3) { - BuildMI(MBB, II, TII.get(ARM::tMOVrr), ARM::R12) + BuildMI(MBB, II, TII.get(ARM::tMOVr), ARM::R12) .addReg(ARM::R2, false, false, true); TmpReg = ARM::R2; } if (TmpReg == ARM::R3 && AFI->isR3LiveIn()) - BuildMI(MBB, II, TII.get(ARM::tMOVrr), ARM::R12) + BuildMI(MBB, II, TII.get(ARM::tMOVr), ARM::R12) .addReg(ARM::R3, false, false, true); if (Opcode == ARM::tSpill) { if (FrameReg == ARM::SP) @@ -934,10 +934,10 @@ MachineBasicBlock::iterator NII = next(II); if (ValReg == ARM::R3) - BuildMI(MBB, NII, TII.get(ARM::tMOVrr), ARM::R2) + BuildMI(MBB, NII, TII.get(ARM::tMOVr), ARM::R2) .addReg(ARM::R12, false, false, true); if (TmpReg == ARM::R3 && AFI->isR3LiveIn()) - BuildMI(MBB, NII, TII.get(ARM::tMOVrr), ARM::R3) + BuildMI(MBB, NII, TII.get(ARM::tMOVr), ARM::R3) .addReg(ARM::R12, false, false, true); } else assert(false && "Unexpected opcode!"); @@ -1391,7 +1391,7 @@ if (NumBytes) emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes, TII); else - BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::SP).addReg(FramePtr); + BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::SP).addReg(FramePtr); } else { if (MBBI->getOpcode() == ARM::tBX_RET && &MBB.front() != MBBI && @@ -1416,7 +1416,7 @@ BuildMI(MBB, MBBI, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr) .addImm(NumBytes); else - BuildMI(MBB, MBBI, TII.get(ARM::MOVrr), ARM::SP).addReg(FramePtr); + BuildMI(MBB, MBBI, TII.get(ARM::MOVr), ARM::SP).addReg(FramePtr); } else if (NumBytes) { emitSPUpdate(MBB, MBBI, NumBytes, false, TII); } From baldrick at free.fr Mon Mar 19 04:11:24 2007 From: baldrick at free.fr (Duncan Sands) Date: Mon, 19 Mar 2007 10:11:24 +0100 Subject: [llvm-commits] CVS: llvm/include/llvm/ADT/APInt.h In-Reply-To: <200703190522.l2J5Mb3D023519@zion.cs.uiuc.edu> References: <200703190522.l2J5Mb3D023519@zion.cs.uiuc.edu> Message-ID: <200703191011.26098.baldrick@free.fr> > Add isStrictPositive() to APInt to determine if this APInt Value > 0. Shouldn't this be "isStrictlyPositive"? Duncan. From baldrick at free.fr Mon Mar 19 09:25:19 2007 From: baldrick at free.fr (Duncan Sands) Date: Mon, 19 Mar 2007 09:25:19 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetData.h Message-ID: <200703191425.l2JEPJYd012657@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/Target: TargetData.h updated: 1.58 -> 1.59 --- Log message: Fix obvious typo in comment. --- Diffs of the changes: (+1 -1) TargetData.h | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/include/llvm/Target/TargetData.h diff -u llvm/include/llvm/Target/TargetData.h:1.58 llvm/include/llvm/Target/TargetData.h:1.59 --- llvm/include/llvm/Target/TargetData.h:1.58 Mon Feb 19 16:35:00 2007 +++ llvm/include/llvm/Target/TargetData.h Mon Mar 19 09:25:02 2007 @@ -157,7 +157,7 @@ /// type. uint64_t getTypeSize(const Type *Ty) const; - /// getTypeSizeInBits - Return the number of bytes necessary to hold the + /// getTypeSizeInBits - Return the number of bits necessary to hold the /// specified type. uint64_t getTypeSizeInBits(const Type* Ty) const; From rspencer at reidspencer.com Mon Mar 19 09:48:02 2007 From: rspencer at reidspencer.com (Reid Spencer) Date: Mon, 19 Mar 2007 07:48:02 -0700 Subject: [llvm-commits] CVS: llvm/include/llvm/ADT/APInt.h In-Reply-To: <200703191011.26098.baldrick@free.fr> References: <200703190522.l2J5Mb3D023519@zion.cs.uiuc.edu> <200703191011.26098.baldrick@free.fr> Message-ID: <1174315682.13912.206.camel@bashful.x10sys.com> On Mon, 2007-03-19 at 10:11 +0100, Duncan Sands wrote: > > Add isStrictPositive() to APInt to determine if this APInt Value > 0. > > Shouldn't this be "isStrictlyPositive"? Yes, it Should. Sheng, please correct the name of this function as Duncan suggested. Thanks, Reid. > > Duncan. > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From evan.cheng at apple.com Mon Mar 19 13:08:43 2007 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 19 Mar 2007 13:08:43 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/LiveIntervalAnalysis.cpp Message-ID: <200703191808.l2JI8h5B016400@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: LiveIntervalAnalysis.cpp updated: 1.224 -> 1.225 --- Log message: Remove -reduce-joining-phys-regs options. Make it on by default. --- Diffs of the changes: (+1 -3) LiveIntervalAnalysis.cpp | 4 +--- 1 files changed, 1 insertion(+), 3 deletions(-) Index: llvm/lib/CodeGen/LiveIntervalAnalysis.cpp diff -u llvm/lib/CodeGen/LiveIntervalAnalysis.cpp:1.224 llvm/lib/CodeGen/LiveIntervalAnalysis.cpp:1.225 --- llvm/lib/CodeGen/LiveIntervalAnalysis.cpp:1.224 Sun Mar 18 23:22:35 2007 +++ llvm/lib/CodeGen/LiveIntervalAnalysis.cpp Mon Mar 19 13:08:26 2007 @@ -42,7 +42,6 @@ STATISTIC(numPeep , "Number of identity moves eliminated after coalescing"); STATISTIC(numFolded , "Number of loads/stores folded into instructions"); STATISTIC(numAborts , "Number of times interval joining aborted"); -static cl::opt ReduceJoinPhys("reduce-joining-phy-regs", cl::Hidden); namespace { RegisterPass X("liveintervals", "Live Interval Analysis"); @@ -937,8 +936,7 @@ // virtual register. Once the coalescing is done, it cannot be broken and // these are not spillable! If the destination interval uses are far away, // think twice about coalescing them! - if (ReduceJoinPhys && !mopd->isDead() && - MRegisterInfo::isPhysicalRegister(repSrcReg)) { + if (!mopd->isDead() && MRegisterInfo::isPhysicalRegister(repSrcReg)) { // Small function. No need to worry! unsigned Threshold = allocatableRegs_.count() * 2; if (r2iMap_.size() <= Threshold) From reid at x10sys.com Mon Mar 19 13:08:59 2007 From: reid at x10sys.com (Reid Spencer) Date: Mon, 19 Mar 2007 13:08:59 -0500 Subject: [llvm-commits] CVS: llvm/test/BugPoint/crash-basictest.ll crash-narrowfunctiontest.ll remove_arguments_test.ll Message-ID: <200703191808.l2JI8x7S016417@zion.cs.uiuc.edu> Changes in directory llvm/test/BugPoint: crash-basictest.ll updated: 1.2 -> 1.3 crash-narrowfunctiontest.ll updated: 1.2 -> 1.3 remove_arguments_test.ll updated: 1.2 -> 1.3 --- Log message: Don't upgrade these. --- Diffs of the changes: (+18 -20) crash-basictest.ll | 9 ++++----- crash-narrowfunctiontest.ll | 14 ++++++-------- remove_arguments_test.ll | 15 ++++++++------- 3 files changed, 18 insertions(+), 20 deletions(-) Index: llvm/test/BugPoint/crash-basictest.ll diff -u llvm/test/BugPoint/crash-basictest.ll:1.2 llvm/test/BugPoint/crash-basictest.ll:1.3 --- llvm/test/BugPoint/crash-basictest.ll:1.2 Fri Dec 29 14:01:32 2006 +++ llvm/test/BugPoint/crash-basictest.ll Mon Mar 19 13:08:42 2007 @@ -1,9 +1,8 @@ ; Basic test for bugpoint. -; RUN: llvm-upgrade < %s > %t1.ll -; RUN: bugpoint %t1.ll -domset -idom -domset -bugpoint-crashcalls \ +; RUN: bugpoint %s -domset -idom -domset -bugpoint-crashcalls \ ; RUN: -domset -idom -domset -int %test() { - call int %test() - ret int %0 +define i32 @test() { + call i32 @test() + ret i32 %1 } Index: llvm/test/BugPoint/crash-narrowfunctiontest.ll diff -u llvm/test/BugPoint/crash-narrowfunctiontest.ll:1.2 llvm/test/BugPoint/crash-narrowfunctiontest.ll:1.3 --- llvm/test/BugPoint/crash-narrowfunctiontest.ll:1.2 Fri Dec 29 14:01:32 2006 +++ llvm/test/BugPoint/crash-narrowfunctiontest.ll Mon Mar 19 13:08:42 2007 @@ -1,14 +1,12 @@ ; Test that bugpoint can narrow down the testcase to the important function ; -; RUN: llvm-upgrade < %s > %t1.ll -; RUN: bugpoint %t1.ll -bugpoint-crashcalls +; RUN: bugpoint %s -bugpoint-crashcalls -int %foo() { ret int 1 } +define i32 @foo() { ret i32 1 } -int %test() { - call int %test() - ret int %0 +define i32 @test() { + call i32 @test() + ret i32 %1 } -int %bar() { ret int 2 } - +define i32 @bar() { ret i32 2 } Index: llvm/test/BugPoint/remove_arguments_test.ll diff -u llvm/test/BugPoint/remove_arguments_test.ll:1.2 llvm/test/BugPoint/remove_arguments_test.ll:1.3 --- llvm/test/BugPoint/remove_arguments_test.ll:1.2 Fri Dec 29 14:01:32 2006 +++ llvm/test/BugPoint/remove_arguments_test.ll Mon Mar 19 13:08:42 2007 @@ -1,10 +1,11 @@ -; RUN: llvm-upgrade < %s > %t1.ll -; RUN: bugpoint %t1.ll -bugpoint-crashcalls +; RUN: bugpoint %s -bugpoint-crashcalls -; Test to make sure that arguments are removed from the function if they are unnecessary. +; Test to make sure that arguments are removed from the function if they are +; unnecessary. -declare int %test2() -int %test(int %A, int %B, float %C) { - call int %test2() - ret int %0 +declare i32 @test2() + +define i32 @test(i32 %A, i32 %B, float %C) { + call i32 @test2() + ret i32 %1 } From sabre at nondot.org Mon Mar 19 13:26:09 2007 From: sabre at nondot.org (Chris Lattner) Date: Mon, 19 Mar 2007 13:26:09 -0500 Subject: [llvm-commits] CVS: llvm/test/Transforms/ScalarRepl/2007-03-19-CanonicalizeMemcpy.ll Message-ID: <200703191826.l2JIQ9C0016842@zion.cs.uiuc.edu> Changes in directory llvm/test/Transforms/ScalarRepl: 2007-03-19-CanonicalizeMemcpy.ll added (r1.1) --- Log message: add a testcase the resent patches fail on. --- Diffs of the changes: (+45 -0) 2007-03-19-CanonicalizeMemcpy.ll | 45 +++++++++++++++++++++++++++++++++++++++ 1 files changed, 45 insertions(+) Index: llvm/test/Transforms/ScalarRepl/2007-03-19-CanonicalizeMemcpy.ll diff -c /dev/null llvm/test/Transforms/ScalarRepl/2007-03-19-CanonicalizeMemcpy.ll:1.1 *** /dev/null Mon Mar 19 13:25:58 2007 --- llvm/test/Transforms/ScalarRepl/2007-03-19-CanonicalizeMemcpy.ll Mon Mar 19 13:25:48 2007 *************** *** 0 **** --- 1,45 ---- + ; RUN: llvm-as < %s | opt -scalarrepl -disable-output + + target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64" + target triple = "arm-apple-darwin8" + %struct.CGPoint = type { float, float } + %struct.aal_big_range_t = type { i32, i32 } + %struct.aal_callback_t = type { i8* (i8*, i32)*, void (i8*, i8*)* } + %struct.aal_edge_pool_t = type { %struct.aal_edge_pool_t*, i32, i32, [0 x %struct.aal_edge_t] } + %struct.aal_edge_t = type { %struct.CGPoint, %struct.CGPoint, i32 } + %struct.aal_range_t = type { i16, i16 } + %struct.aal_span_pool_t = type { %struct.aal_span_pool_t*, [341 x %struct.aal_span_t] } + %struct.aal_span_t = type { %struct.aal_span_t*, %struct.aal_big_range_t } + %struct.aal_spanarray_t = type { [2 x %struct.aal_range_t] } + %struct.aal_spanbucket_t = type { i16, [2 x i8], %struct.anon } + %struct.aal_state_t = type { %struct.CGPoint, %struct.CGPoint, %struct.CGPoint, i32, float, float, float, float, %struct.CGPoint, %struct.CGPoint, float, float, float, float, i32, i32, i32, i32, float, float, i8*, i32, i32, %struct.aal_edge_pool_t*, %struct.aal_edge_pool_t*, i8*, %struct.aal_callback_t*, i32, %struct.aal_span_t*, %struct.aal_span_t*, %struct.aal_span_t*, %struct.aal_span_pool_t*, i8, float, i8, i32 } + %struct.anon = type { %struct.aal_spanarray_t } + + implementation ; Functions: + + declare void @llvm.memcpy.i32(i8*, i8*, i32, i32) + + define fastcc void @aal_insert_span() { + entry: + %SB = alloca %struct.aal_spanbucket_t, align 4 ; <%struct.aal_spanbucket_t*> [#uses=2] + br i1 false, label %cond_true, label %cond_next79 + + cond_true: ; preds = %entry + br i1 false, label %cond_next, label %cond_next114.i + + cond_next114.i: ; preds = %cond_true + ret void + + cond_next: ; preds = %cond_true + %SB19 = bitcast %struct.aal_spanbucket_t* %SB to i8* ; [#uses=1] + call void @llvm.memcpy.i32( i8* %SB19, i8* null, i32 12, i32 0 ) + br i1 false, label %cond_next34, label %cond_next79 + + cond_next34: ; preds = %cond_next + %i.2.reload22 = load i32* null ; [#uses=1] + %tmp51 = getelementptr %struct.aal_spanbucket_t* %SB, i32 0, i32 2, i32 0, i32 0, i32 %i.2.reload22, i32 1 ; [#uses=0] + ret void + + cond_next79: ; preds = %cond_next, %entry + ret void + } From reid at x10sys.com Mon Mar 19 13:26:17 2007 From: reid at x10sys.com (Reid Spencer) Date: Mon, 19 Mar 2007 13:26:17 -0500 Subject: [llvm-commits] CVS: llvm/test/CFrontend/2005-06-15-ExpandGotoInternalProblem.c Message-ID: <200703191826.l2JIQHJO016848@zion.cs.uiuc.edu> Changes in directory llvm/test/CFrontend: 2005-06-15-ExpandGotoInternalProblem.c updated: 1.1 -> 1.2 --- Log message: Use opt instead of gccas. --- Diffs of the changes: (+2 -1) 2005-06-15-ExpandGotoInternalProblem.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index: llvm/test/CFrontend/2005-06-15-ExpandGotoInternalProblem.c diff -u llvm/test/CFrontend/2005-06-15-ExpandGotoInternalProblem.c:1.1 llvm/test/CFrontend/2005-06-15-ExpandGotoInternalProblem.c:1.2 --- llvm/test/CFrontend/2005-06-15-ExpandGotoInternalProblem.c:1.1 Wed Jun 15 17:42:53 2005 +++ llvm/test/CFrontend/2005-06-15-ExpandGotoInternalProblem.c Mon Mar 19 13:25:55 2007 @@ -1,4 +1,5 @@ -// RUN: %llvmgcc -std=c99 %s -S -o - | gccas -o /dev/null +// RUN: %llvmgcc -std=c99 %s -S -o - | llvm-as | \ +// RUN: opt -std-compile-opts -disable-output // PR580 int X, Y; From sabre at nondot.org Mon Mar 19 13:26:18 2007 From: sabre at nondot.org (Chris Lattner) Date: Mon, 19 Mar 2007 13:26:18 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp Message-ID: <200703191826.l2JIQIuZ016855@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: ScalarReplAggregates.cpp updated: 1.79 -> 1.80 --- Log message: fix ScalarRepl/2007-03-19-CanonicalizeMemcpy.ll --- Diffs of the changes: (+2 -1) ScalarReplAggregates.cpp | 3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index: llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp diff -u llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp:1.79 llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp:1.80 --- llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp:1.79 Sun Mar 18 19:16:43 2007 +++ llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp Mon Mar 19 13:25:57 2007 @@ -661,7 +661,8 @@ // up. for (Value::use_iterator UI = AI->use_begin(), E = AI->use_end(); UI != E; ) { - GetElementPtrInst *GEPI = cast(*UI++); + GetElementPtrInst *GEPI = dyn_cast(*UI++); + if (!GEPI) continue; gep_type_iterator I = gep_type_begin(GEPI); ++I; From reid at x10sys.com Mon Mar 19 13:27:56 2007 From: reid at x10sys.com (Reid Spencer) Date: Mon, 19 Mar 2007 13:27:56 -0500 Subject: [llvm-commits] CVS: llvm/test/CodeGen/X86/2007-03-01-SpillerCrash.ll Message-ID: <200703191827.l2JIRuLr016913@zion.cs.uiuc.edu> Changes in directory llvm/test/CodeGen/X86: 2007-03-01-SpillerCrash.ll updated: 1.1 -> 1.2 --- Log message: For PR1258: http://llvm.org/PR1258 : Revise numeric value references to accommodate collapsed type planes. --- Diffs of the changes: (+56 -56) 2007-03-01-SpillerCrash.ll | 112 ++++++++++++++++++++++----------------------- 1 files changed, 56 insertions(+), 56 deletions(-) Index: llvm/test/CodeGen/X86/2007-03-01-SpillerCrash.ll diff -u llvm/test/CodeGen/X86/2007-03-01-SpillerCrash.ll:1.1 llvm/test/CodeGen/X86/2007-03-01-SpillerCrash.ll:1.2 --- llvm/test/CodeGen/X86/2007-03-01-SpillerCrash.ll:1.1 Fri Mar 2 04:37:19 2007 +++ llvm/test/CodeGen/X86/2007-03-01-SpillerCrash.ll Mon Mar 19 13:27:35 2007 @@ -8,78 +8,78 @@ mul <4 x float> %0, %2 ; <<4 x float>>:3 [#uses=1] sub <4 x float> zeroinitializer, %3 ; <<4 x float>>:4 [#uses=1] mul <4 x float> %4, zeroinitializer ; <<4 x float>>:5 [#uses=2] - bitcast <4 x float> zeroinitializer to <4 x i32> ; <<4 x i32>>:0 [#uses=1] - and <4 x i32> %0, < i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647 > ; <<4 x i32>>:1 [#uses=1] - bitcast <4 x i32> %1 to <4 x float> ; <<4 x float>>:6 [#uses=2] - extractelement <4 x float> %6, i32 0 ; :0 [#uses=1] - extractelement <4 x float> %6, i32 1 ; :1 [#uses=2] - br i1 false, label %0, label %5 + bitcast <4 x float> zeroinitializer to <4 x i32> ; <<4 x i32>>:6 [#uses=1] + and <4 x i32> %6, < i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647 > ; <<4 x i32>>:7 [#uses=1] + bitcast <4 x i32> %7 to <4 x float> ; <<4 x float>>:8 [#uses=2] + extractelement <4 x float> %8, i32 0 ; :9 [#uses=1] + extractelement <4 x float> %8, i32 1 ; :10 [#uses=2] + br i1 false, label %11, label %19 -;