From sabre at nondot.org Mon May 21 00:08:23 2007 From: sabre at nondot.org (Chris Lattner) Date: Mon, 21 May 2007 00:08:23 -0500 Subject: [llvm-commits] CVS: llvm-www/DevMtgMay2007.html Message-ID: <200705210508.l4L58NuX001849@zion.cs.uiuc.edu> Changes in directory llvm-www: DevMtgMay2007.html updated: 1.145 -> 1.146 --- Log message: patch from Nick Lewycky --- Diffs of the changes: (+2 -2) DevMtgMay2007.html | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm-www/DevMtgMay2007.html diff -u llvm-www/DevMtgMay2007.html:1.145 llvm-www/DevMtgMay2007.html:1.146 --- llvm-www/DevMtgMay2007.html:1.145 Fri May 18 00:41:43 2007 +++ llvm-www/DevMtgMay2007.html Mon May 21 00:08:04 2007 @@ -124,7 +124,7 @@

Lunch

12:0013:00Everyone Thanks to a generous sponsor, lunch will be catered. -

Session 2:
Using LLVM

+

Session 2:
Using LLVM

StartStopSpeakerDescription 13:0013:20Sarah Thompson @@ -352,6 +352,6 @@ src="http://jigsaw.w3.org/css-validator/images/vcss" alt="Valid CSS!"> Valid HTML 4.01! -
Last modified: $Date: 2007/05/18 05:41:43 $ +
Last modified: $Date: 2007/05/21 05:08:04 $ From evan.cheng at apple.com Mon May 21 13:43:22 2007 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 21 May 2007 13:43:22 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.cpp Message-ID: <200705211843.l4LIhMF5026124@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86InstrInfo.cpp updated: 1.86 -> 1.87 --- Log message: BlockHasNoFallThrough() now returns true if block ends with a return instruction. --- Diffs of the changes: (+5 -0) X86InstrInfo.cpp | 5 +++++ 1 files changed, 5 insertions(+) Index: llvm/lib/Target/X86/X86InstrInfo.cpp diff -u llvm/lib/Target/X86/X86InstrInfo.cpp:1.86 llvm/lib/Target/X86/X86InstrInfo.cpp:1.87 --- llvm/lib/Target/X86/X86InstrInfo.cpp:1.86 Thu May 17 19:17:09 2007 +++ llvm/lib/Target/X86/X86InstrInfo.cpp Mon May 21 13:43:02 2007 @@ -486,6 +486,11 @@ if (MBB.empty()) return false; switch (MBB.back().getOpcode()) { + case X86::RET: // Return. + case X86::RETI: + case X86::TAILJMPd: + case X86::TAILJMPr: + case X86::TAILJMPm: case X86::JMP: // Uncond branch. case X86::JMP32r: // Indirect branch. case X86::JMP32m: // Indirect branch through mem. From evan.cheng at apple.com Mon May 21 13:43:45 2007 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 21 May 2007 13:43:45 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp Message-ID: <200705211843.l4LIhjTI026146@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCInstrInfo.cpp updated: 1.38 -> 1.39 --- Log message: BlockHasNoFallThrough() now returns true if block ends with a return instruction. --- Diffs of the changes: (+1 -0) PPCInstrInfo.cpp | 1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.38 llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.39 --- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.38 Thu May 17 19:05:48 2007 +++ llvm/lib/Target/PowerPC/PPCInstrInfo.cpp Mon May 21 13:43:25 2007 @@ -276,6 +276,7 @@ if (MBB.empty()) return false; switch (MBB.back().getOpcode()) { + case PPC::BLR: // Return. case PPC::B: // Uncond branch. case PPC::BCTR: // Indirect branch. return true; From evan.cheng at apple.com Mon May 21 13:44:35 2007 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 21 May 2007 13:44:35 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaInstrInfo.cpp Message-ID: <200705211844.l4LIiZht026175@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Alpha: AlphaInstrInfo.cpp updated: 1.18 -> 1.19 --- Log message: BlockHasNoFallThrough() now returns true if block ends with a return instruction. --- Diffs of the changes: (+2 -0) AlphaInstrInfo.cpp | 2 ++ 1 files changed, 2 insertions(+) Index: llvm/lib/Target/Alpha/AlphaInstrInfo.cpp diff -u llvm/lib/Target/Alpha/AlphaInstrInfo.cpp:1.18 llvm/lib/Target/Alpha/AlphaInstrInfo.cpp:1.19 --- llvm/lib/Target/Alpha/AlphaInstrInfo.cpp:1.18 Thu May 17 19:02:59 2007 +++ llvm/lib/Target/Alpha/AlphaInstrInfo.cpp Mon May 21 13:44:17 2007 @@ -239,6 +239,8 @@ if (MBB.empty()) return false; switch (MBB.back().getOpcode()) { + case Alpha::RETDAG: // Return. + case Alpha::RETDAGp: case Alpha::BR: // Uncond branch. case Alpha::JMP: // Indirect branch. return true; From baldrick at free.fr Mon May 21 13:50:46 2007 From: baldrick at free.fr (Duncan Sands) Date: Mon, 21 May 2007 13:50:46 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/DwarfWriter.cpp Message-ID: <200705211850.l4LIoke9026355@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: DwarfWriter.cpp updated: 1.146 -> 1.147 --- Log message: Only emit one entry in the exception action table for each action, even if it occurs for multiple landing pads. --- Diffs of the changes: (+116 -65) DwarfWriter.cpp | 181 +++++++++++++++++++++++++++++++++++--------------------- 1 files changed, 116 insertions(+), 65 deletions(-) Index: llvm/lib/CodeGen/DwarfWriter.cpp diff -u llvm/lib/CodeGen/DwarfWriter.cpp:1.146 llvm/lib/CodeGen/DwarfWriter.cpp:1.147 --- llvm/lib/CodeGen/DwarfWriter.cpp:1.146 Wed May 16 07:12:23 2007 +++ llvm/lib/CodeGen/DwarfWriter.cpp Mon May 21 13:50:28 2007 @@ -2893,7 +2893,46 @@ if (const char *UsedDirective = TAI->getUsedDirective()) O << UsedDirective << EHFrameInfo.FnName << ".eh\n\n"; } - + + /// EquivPads - Whether two landing pads have equivalent actions. + static bool EquivPads(const LandingPadInfo *L, const LandingPadInfo *R) { + const std::vector &LIds = L->TypeIds; + const std::vector &RIds = R->TypeIds; + unsigned LSize = LIds.size(), RSize = RIds.size(); + + if (L->IsFilter != R->IsFilter) + return false; + + if (LSize != RSize) + return false; + + for (unsigned i = 0; i != LSize; ++i) + if (LIds[i] != RIds[i]) + return false; + + return true; + } + + /// PadLT - An order on landing pads, with EquivPads as order equivalence. + static bool PadLT(const LandingPadInfo *L, const LandingPadInfo *R) { + const std::vector &LIds = L->TypeIds; + const std::vector &RIds = R->TypeIds; + unsigned LSize = LIds.size(), RSize = RIds.size(); + + if (L->IsFilter != R->IsFilter) + // Make filters come last + return L->IsFilter < R->IsFilter; + + if (LSize != RSize) + return LSize < RSize; + + for (unsigned i = 0; i != LSize; ++i) + if (LIds[i] != RIds[i]) + return LIds[i] < RIds[i]; + + return false; // Equivalent + } + /// EmitExceptionTable - Emit landpads and actions. /// /// The general organization of the table is complex, but the basic concepts @@ -2931,16 +2970,21 @@ void EmitExceptionTable() { // Map all labels and get rid of any dead landing pads. MMI->TidyLandingPads(); - + const std::vector &TypeInfos = MMI->getTypeInfos(); - const std::vector &LandingPads = MMI->getLandingPads(); - if (LandingPads.empty()) return; - - // FIXME - Should fold actions for multiple landing pads. - + const std::vector &PadInfos = MMI->getLandingPads(); + if (PadInfos.empty()) return; + + // Sort the landing pads in order of their type ids. This is used to fold + // duplicate actions. + SmallVector LandingPads(PadInfos.size(), NULL); + for (unsigned i = 0, N = PadInfos.size(); i != N; ++i) + LandingPads[i] = &PadInfos[i]; + std::sort(LandingPads.begin(), LandingPads.end(), PadLT); + // Gather first action index for each landing pad site. - SmallVector Actions; - + SmallVector Actions; + // FIXME - Assume there is only one filter typeinfo list per function // time being. I.E., Each call to eh_filter will have the same list. // This can change if a function is inlined. @@ -2952,43 +2996,47 @@ // Look at each landing pad site to compute size. We need the size of each // landing pad site info and the size of the landing pad's actions. + signed FirstAction; + for (unsigned i = 0, N = LandingPads.size(); i != N; ++i) { - const LandingPadInfo &LandingPad = LandingPads[i]; - bool IsFilter = LandingPad.IsFilter; + const LandingPadInfo *LandingPad = LandingPads[i]; unsigned SizeSiteActions = 0; - const std::vector &TypeIds = LandingPad.TypeIds; - unsigned SizeAction = 0; - signed FirstAction; - - if (IsFilter) { - // FIXME - Assume there is only one filter typeinfo list per function - // time being. I.E., Each call to eh_filter will have the same list. - // This can change if a function is inlined. - Filter = &LandingPad; - SizeAction = Asm->SizeSLEB128(-1) + Asm->SizeSLEB128(0); - SizeSiteActions += SizeAction; - // Record the first action of the landing pad site. - FirstAction = SizeActions + SizeSiteActions - SizeAction + 1; - } else if (TypeIds.empty()) { - FirstAction = 0; - } else { - // Gather the action sizes - for (unsigned j = 0, M = TypeIds.size(); j != M; ++j) { - unsigned TypeID = TypeIds[j]; - unsigned SizeTypeID = Asm->SizeSLEB128(TypeID); - signed Action = j ? -(SizeAction + SizeTypeID) : 0; - SizeAction = SizeTypeID + Asm->SizeSLEB128(Action); + + if (!i || !EquivPads(LandingPad, LandingPads[i-1])) { + const std::vector &TypeIds = LandingPad->TypeIds; + unsigned SizeAction = 0; + + if (LandingPad->IsFilter) { + // FIXME - Assume there is only one filter typeinfo list per function + // time being. I.E., Each call to eh_filter will have the same list. + // This can change if a function is inlined. + Filter = LandingPad; + SizeAction = Asm->SizeSLEB128(-1) + Asm->SizeSLEB128(0); SizeSiteActions += SizeAction; + // Record the first action of the landing pad site. + FirstAction = SizeActions + SizeSiteActions - SizeAction + 1; + } else if (TypeIds.empty()) { + FirstAction = 0; + } else { + // Gather the action sizes + for (unsigned j = 0, M = TypeIds.size(); j != M; ++j) { + unsigned TypeID = TypeIds[j]; + unsigned SizeTypeID = Asm->SizeSLEB128(TypeID); + signed Action = j ? -(SizeAction + SizeTypeID) : 0; + SizeAction = SizeTypeID + Asm->SizeSLEB128(Action); + SizeSiteActions += SizeAction; + } + + // Record the first action of the landing pad site. + FirstAction = SizeActions + SizeSiteActions - SizeAction + 1; } - - // Record the first action of the landing pad site. - FirstAction = SizeActions + SizeSiteActions - SizeAction + 1; - } + } // else re-use previous FirstAction + Actions.push_back(FirstAction); - + // Compute this sites contribution to size. SizeActions += SizeSiteActions; - unsigned M = LandingPad.BeginLabels.size(); + unsigned M = LandingPad->BeginLabels.size(); SizeSites += M*(sizeof(int32_t) + // Site start. sizeof(int32_t) + // Site length. sizeof(int32_t) + // Landing pad. @@ -3035,9 +3083,9 @@ PadMapType PadMap; for (unsigned i = 0, N = LandingPads.size(); i != N; ++i) { - const LandingPadInfo &LandingPad = LandingPads[i]; - for (unsigned j=0, E = LandingPad.BeginLabels.size(); j != E; ++j) { - unsigned BeginLabel = LandingPad.BeginLabels[j]; + const LandingPadInfo *LandingPad = LandingPads[i]; + for (unsigned j=0, E = LandingPad->BeginLabels.size(); j != E; ++j) { + unsigned BeginLabel = LandingPad->BeginLabels[j]; assert(!PadMap.count(BeginLabel) && "duplicate landing pad labels!"); PadSite P = { i, j }; PadMap[BeginLabel] = P; @@ -3058,27 +3106,28 @@ continue; PadSite P = L->second; - const LandingPadInfo &LandingPad = LandingPads[P.PadIndex]; + const LandingPadInfo *LandingPad = LandingPads[P.PadIndex]; - assert(BeginLabel == LandingPad.BeginLabels[P.SiteIndex] && + assert(BeginLabel == LandingPad->BeginLabels[P.SiteIndex] && "Inconsistent landing pad map!"); EmitSectionOffset("label", "eh_func_begin", BeginLabel, SubprogramCount, false, true); Asm->EOL("Region start"); - EmitDifference("label", LandingPad.EndLabels[P.SiteIndex], + EmitDifference("label", LandingPad->EndLabels[P.SiteIndex], "label", BeginLabel); Asm->EOL("Region length"); - if (LandingPad.TypeIds.empty()) { + if (LandingPad->TypeIds.empty()) { if (TAI->getAddressSize() == sizeof(int32_t)) Asm->EmitInt32(0); else Asm->EmitInt64(0); } else { - EmitSectionOffset("label", "eh_func_begin", LandingPad.LandingPadLabel, - SubprogramCount, false, true); + EmitSectionOffset("label", "eh_func_begin", + LandingPad->LandingPadLabel, SubprogramCount, + false, true); } Asm->EOL("Landing pad"); @@ -3089,25 +3138,27 @@ // Emit the actions. for (unsigned i = 0, N = LandingPads.size(); i != N; ++i) { - const LandingPadInfo &LandingPad = LandingPads[i]; - const std::vector &TypeIds = LandingPad.TypeIds; - unsigned SizeAction = 0; - - if (LandingPad.IsFilter) { - Asm->EmitSLEB128Bytes(-1); - Asm->EOL("TypeInfo index"); - Asm->EmitSLEB128Bytes(0); - Asm->EOL("Next action"); - } else { - for (unsigned j = 0, M = TypeIds.size(); j < M; ++j) { - unsigned TypeID = TypeIds[j]; - unsigned SizeTypeID = Asm->SizeSLEB128(TypeID); - Asm->EmitSLEB128Bytes(TypeID); + if (!i || Actions[i] != Actions[i-1]) { + const LandingPadInfo *LandingPad = LandingPads[i]; + const std::vector &TypeIds = LandingPad->TypeIds; + unsigned SizeAction = 0; + + if (LandingPad->IsFilter) { + Asm->EmitSLEB128Bytes(-1); Asm->EOL("TypeInfo index"); - signed Action = j ? -(SizeAction + SizeTypeID) : 0; - SizeAction = SizeTypeID + Asm->SizeSLEB128(Action); - Asm->EmitSLEB128Bytes(Action); + Asm->EmitSLEB128Bytes(0); Asm->EOL("Next action"); + } else { + for (unsigned j = 0, M = TypeIds.size(); j < M; ++j) { + unsigned TypeID = TypeIds[j]; + unsigned SizeTypeID = Asm->SizeSLEB128(TypeID); + Asm->EmitSLEB128Bytes(TypeID); + Asm->EOL("TypeInfo index"); + signed Action = j ? -(SizeAction + SizeTypeID) : 0; + SizeAction = SizeTypeID + Asm->SizeSLEB128(Action); + Asm->EmitSLEB128Bytes(Action); + Asm->EOL("Next action"); + } } } } From evan.cheng at apple.com Mon May 21 13:56:51 2007 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 21 May 2007 13:56:51 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.cpp Message-ID: <200705211856.l4LIupA5026535@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/ARM: ARMInstrInfo.cpp updated: 1.28 -> 1.29 --- Log message: BlockHasNoFallThrough() now returns true if block ends with a return instruction; AnalyzeBranch() should ignore predicated instructionsd. --- Diffs of the changes: (+13 -2) ARMInstrInfo.cpp | 15 +++++++++++++-- 1 files changed, 13 insertions(+), 2 deletions(-) Index: llvm/lib/Target/ARM/ARMInstrInfo.cpp diff -u llvm/lib/Target/ARM/ARMInstrInfo.cpp:1.28 llvm/lib/Target/ARM/ARMInstrInfo.cpp:1.29 --- llvm/lib/Target/ARM/ARMInstrInfo.cpp:1.28 Thu May 17 19:18:17 2007 +++ llvm/lib/Target/ARM/ARMInstrInfo.cpp Mon May 21 13:56:31 2007 @@ -298,6 +298,11 @@ return NewMIs[0]; } +static bool isPredicated(MachineInstr *MI) { + MachineOperand *PMO = MI->findFirstPredOperand(); + return PMO && PMO->getImmedValue() != ARMCC::AL; +} + // Branch analysis. bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, @@ -312,7 +317,8 @@ // If there is only one terminator instruction, process it. unsigned LastOpc = LastInst->getOpcode(); - if (I == MBB.begin() || !isTerminatorInstr((--I)->getOpcode())) { + if (I == MBB.begin() || + isPredicated(--I) || !isTerminatorInstr(I->getOpcode())) { if (LastOpc == ARM::B || LastOpc == ARM::tB) { TBB = LastInst->getOperand(0).getMachineBasicBlock(); return false; @@ -331,7 +337,7 @@ // If there are three terminators, we don't know what sort of block this is. if (SecondLastInst && I != MBB.begin() && - isTerminatorInstr((--I)->getOpcode())) + !isPredicated(--I) && isTerminatorInstr(I->getOpcode())) return true; // If the block ends with ARM::B/ARM::tB and a ARM::Bcc/ARM::tBcc, handle it. @@ -407,6 +413,11 @@ if (MBB.empty()) return false; switch (MBB.back().getOpcode()) { + case ARM::BX_RET: // Return. + case ARM::LDM_RET: + case ARM::tBX_RET: + case ARM::tBX_RET_vararg: + case ARM::tPOP_RET: case ARM::B: case ARM::tB: // Uncond branch. case ARM::tBR_JTr: From dalej at apple.com Mon May 21 14:01:01 2007 From: dalej at apple.com (Dale Johannesen) Date: Mon, 21 May 2007 12:01:01 -0700 Subject: [llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.cpp In-Reply-To: <200705211856.l4LIupA5026535@zion.cs.uiuc.edu> References: <200705211856.l4LIupA5026535@zion.cs.uiuc.edu> Message-ID: <5FCC976C-143F-452F-86E3-D5CF2AE7600A@apple.com> On May 21, 2007, at 11:56 AM, Evan Cheng wrote: > - isTerminatorInstr((--I)->getOpcode())) > + !isPredicated(--I) && isTerminatorInstr(I->getOpcode())) Wouldn't it be better to have isTerminatorInst return false on predicated things? From dalej at apple.com Mon May 21 17:14:51 2007 From: dalej at apple.com (Dale Johannesen) Date: Mon, 21 May 2007 17:14:51 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.td Message-ID: <200705212214.l4LMEpbw030229@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/ARM: ARMInstrInfo.td updated: 1.104 -> 1.105 --- Log message: Add some patterns for PIC PC-relative loads and stores. --- Diffs of the changes: (+41 -2) ARMInstrInfo.td | 43 +++++++++++++++++++++++++++++++++++++++++-- 1 files changed, 41 insertions(+), 2 deletions(-) Index: llvm/lib/Target/ARM/ARMInstrInfo.td diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.104 llvm/lib/Target/ARM/ARMInstrInfo.td:1.105 --- llvm/lib/Target/ARM/ARMInstrInfo.td:1.104 Thu May 17 20:53:54 2007 +++ llvm/lib/Target/ARM/ARMInstrInfo.td Mon May 21 17:14:33 2007 @@ -554,11 +554,50 @@ def PICADD : AXI1<(ops GPR:$dst, GPR:$a, pclabel:$cp, pred:$p), "$cp:\n\tadd$p $dst, pc, $a", [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>; -let AddedComplexity = 10 in -def PICLD : AXI2<(ops GPR:$dst, addrmodepc:$addr, pred:$p), + +let isLoad = 1, AddedComplexity = 10 in { +def PICLD : AXI2<(ops GPR:$dst, addrmodepc:$addr, pred:$p), "${addr:label}:\n\tldr$p $dst, $addr", [(set GPR:$dst, (load addrmodepc:$addr))]>; +def PICLDZH : AXI2<(ops GPR:$dst, addrmodepc:$addr, pred:$p), + "${addr:label}:\n\tldr${p}h $dst, $addr", + [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>; + +def PICLDZB : AXI2<(ops GPR:$dst, addrmodepc:$addr, pred:$p), + "${addr:label}:\n\tldr${p}b $dst, $addr", + [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>; + +def PICLDH : AXI2<(ops GPR:$dst, addrmodepc:$addr, pred:$p), + "${addr:label}:\n\tldr${p}h $dst, $addr", + [(set GPR:$dst, (extloadi16 addrmodepc:$addr))]>; + +def PICLDB : AXI2<(ops GPR:$dst, addrmodepc:$addr, pred:$p), + "${addr:label}:\n\tldr${p}b $dst, $addr", + [(set GPR:$dst, (extloadi8 addrmodepc:$addr))]>; + +def PICLDSH : AXI2<(ops GPR:$dst, addrmodepc:$addr, pred:$p), + "${addr:label}:\n\tldr${p}sh $dst, $addr", + [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>; + +def PICLDSB : AXI2<(ops GPR:$dst, addrmodepc:$addr, pred:$p), + "${addr:label}:\n\tldr${p}sb $dst, $addr", + [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>; +} +let isStore = 1, AddedComplexity = 10 in { +def PICSTR : AXI2<(ops GPR:$src, addrmodepc:$addr, pred:$p), + "${addr:label}:\n\tstr$p $src, $addr", + [(store GPR:$src, addrmodepc:$addr)]>; + +def PICSTRH : AXI2<(ops GPR:$src, addrmodepc:$addr, pred:$p), + "${addr:label}:\n\tstr${p}h $src, $addr", + [(truncstorei16 GPR:$src, addrmodepc:$addr)]>; + +def PICSTRB : AXI2<(ops GPR:$src, addrmodepc:$addr, pred:$p), + "${addr:label}:\n\tstr${p}b $src, $addr", + [(truncstorei8 GPR:$src, addrmodepc:$addr)]>; +} + //===----------------------------------------------------------------------===// // Control Flow Instructions. // From evan.cheng at apple.com Mon May 21 17:23:16 2007 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 21 May 2007 17:23:16 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/IfConversion.cpp Message-ID: <200705212223.l4LMNG6V030431@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: IfConversion.cpp updated: 1.10 -> 1.11 --- Log message: If-convert early exit blocks (returns, etc.); bug fixes, etc. --- Diffs of the changes: (+226 -141) IfConversion.cpp | 367 +++++++++++++++++++++++++++++++++---------------------- 1 files changed, 226 insertions(+), 141 deletions(-) Index: llvm/lib/CodeGen/IfConversion.cpp diff -u llvm/lib/CodeGen/IfConversion.cpp:1.10 llvm/lib/CodeGen/IfConversion.cpp:1.11 --- llvm/lib/CodeGen/IfConversion.cpp:1.10 Fri May 18 14:32:08 2007 +++ llvm/lib/CodeGen/IfConversion.cpp Mon May 21 17:22:58 2007 @@ -30,10 +30,11 @@ enum BBICKind { ICInvalid, // BB data invalid. ICNotClassfied, // BB data valid, but not classified. - ICTriangle, // BB is part of a triangle sub-CFG. - ICDiamond, // BB is part of a diamond sub-CFG. - ICTriangleEntry, // BB is entry of a triangle sub-CFG. - ICDiamondEntry // BB is entry of a diamond sub-CFG. + ICEarlyExit, // BB is entry of an early-exit sub-CFG. + ICTriangle, // BB is entry of a triangle sub-CFG. + ICDiamond, // BB is entry of a diamond sub-CFG. + ICChild, // BB is part of the sub-CFG that'll be predicated. + ICDead // BB has been converted and merged, it's now dead. }; /// BBInfo - One per MachineBasicBlock, this is used to cache the result @@ -47,13 +48,15 @@ unsigned Size; bool isPredicable; bool ClobbersPred; + bool hasEarlyExit; MachineBasicBlock *BB; MachineBasicBlock *TrueBB; MachineBasicBlock *FalseBB; MachineBasicBlock *TailBB; std::vector Cond; BBInfo() : Kind(ICInvalid), Size(0), isPredicable(false), - ClobbersPred(false), BB(0), TrueBB(0), FalseBB(0), TailBB(0) {} + ClobbersPred(false), hasEarlyExit(false), + BB(0), TrueBB(0), FalseBB(0), TailBB(0) {} }; /// BBAnalysis - Results of if-conversion feasibility analysis indexed by @@ -75,6 +78,7 @@ void FeasibilityAnalysis(BBInfo &BBI); void InitialFunctionAnalysis(MachineFunction &MF, std::vector &Candidates); + bool IfConvertEarlyExit(BBInfo &BBI); bool IfConvertTriangle(BBInfo &BBI); bool IfConvertDiamond(BBInfo &BBI); void PredicateBlock(MachineBasicBlock *BB, @@ -107,10 +111,13 @@ switch (BBI.Kind) { default: assert(false && "Unexpected!"); break; - case ICTriangleEntry: + case ICEarlyExit: + MadeChange |= IfConvertEarlyExit(BBI); + break; + case ICTriangle: MadeChange |= IfConvertTriangle(BBI); break; - case ICDiamondEntry: + case ICDiamond: MadeChange |= IfConvertDiamond(BBI); break; } @@ -139,19 +146,16 @@ BBInfo &BBI = BBAnalysis[BB->getNumber()]; if (BBI.Kind != ICInvalid) - return; // Always analyzed. + return; // Already analyzed. BBI.BB = BB; BBI.Size = std::distance(BB->begin(), BB->end()); // Look for 'root' of a simple (non-nested) triangle or diamond. BBI.Kind = ICNotClassfied; - if (TII->AnalyzeBranch(*BB, BBI.TrueBB, BBI.FalseBB, BBI.Cond) - || !BBI.TrueBB || BBI.Cond.size() == 0) - return; - - // Not a candidate if 'true' block has another predecessor. - // FIXME: Use or'd predicate or predicated cmp. - if (BBI.TrueBB->pred_size() > 1) + bool CanAnalyze = !TII->AnalyzeBranch(*BB, BBI.TrueBB, BBI.FalseBB, BBI.Cond); + // Does it end with a return, indirect jump, or jumptable branch? + BBI.hasEarlyExit = TII->BlockHasNoFallThrough(*BB) && !BBI.TrueBB; + if (!CanAnalyze || !BBI.TrueBB || BBI.Cond.size() == 0) return; // Not a candidate if 'true' block is going to be if-converted. @@ -170,11 +174,6 @@ BBI.FalseBB = findFalseBlock(BB, BBI.TrueBB); assert(BBI.FalseBB && "Expected to find the fallthrough block!"); - // Not a candidate if 'false' block has another predecessor. - // FIXME: Invert condition and swap 'true' / 'false' blocks? - if (BBI.FalseBB->pred_size() > 1) - return; - // Not a candidate if 'false' block is going to be if-converted. StructuralAnalysis(BBI.FalseBB); BBInfo &FalseBBI = BBAnalysis[BBI.FalseBB->getNumber()]; @@ -185,7 +184,17 @@ if (FalseBBI.FalseBB || FalseBBI.Cond.size()) return; - if (TrueBBI.TrueBB && TrueBBI.TrueBB == BBI.FalseBB) { + unsigned TrueNumPreds = BBI.TrueBB->pred_size(); + unsigned FalseNumPreds = BBI.FalseBB->pred_size(); + if ((TrueBBI.hasEarlyExit && TrueNumPreds <= 1) && + !(FalseBBI.hasEarlyExit && FalseNumPreds <=1)) { + BBI.Kind = ICEarlyExit; + TrueBBI.Kind = ICChild; + } else if (!(TrueBBI.hasEarlyExit && TrueNumPreds <= 1) && + (FalseBBI.hasEarlyExit && FalseNumPreds <=1)) { + BBI.Kind = ICEarlyExit; + FalseBBI.Kind = ICChild; + } else if (TrueBBI.TrueBB && TrueBBI.TrueBB == BBI.FalseBB) { // Triangle: // EBB // | \_ @@ -193,9 +202,10 @@ // | TBB // | / // FBB - BBI.Kind = ICTriangleEntry; - TrueBBI.Kind = FalseBBI.Kind = ICTriangle; - } else if (TrueBBI.TrueBB == FalseBBI.TrueBB) { + BBI.Kind = ICTriangle; + TrueBBI.Kind = FalseBBI.Kind = ICChild; + } else if (TrueBBI.TrueBB == FalseBBI.TrueBB && + TrueNumPreds <= 1 && FalseNumPreds <= 1) { // Diamond: // EBB // / \_ @@ -204,8 +214,8 @@ // \ / // TailBB // Note MBB can be empty in case both TBB and FBB are return blocks. - BBI.Kind = ICDiamondEntry; - TrueBBI.Kind = FalseBBI.Kind = ICDiamond; + BBI.Kind = ICDiamond; + TrueBBI.Kind = FalseBBI.Kind = ICChild; BBI.TailBB = TrueBBI.TrueBB; } return; @@ -245,8 +255,14 @@ MachineBasicBlock *BB = *DFI; StructuralAnalysis(BB); BBInfo &BBI = BBAnalysis[BB->getNumber()]; - if (BBI.Kind == ICTriangleEntry || BBI.Kind == ICDiamondEntry) + switch (BBI.Kind) { + default: break; + case ICEarlyExit: + case ICTriangle: + case ICDiamond: Candidates.push_back(&BBI); + break; + } } } @@ -276,54 +292,107 @@ } } +/// isNextBlock - Returns true if ToBB the next basic block after BB. +/// +static bool isNextBlock(MachineBasicBlock *BB, MachineBasicBlock *ToBB) { + MachineFunction::iterator Fallthrough = BB; + return MachineFunction::iterator(ToBB) == ++Fallthrough; +} + +/// IfConvertEarlyExit - If convert a early exit sub-CFG. +/// +bool IfConverter::IfConvertEarlyExit(BBInfo &BBI) { + BBInfo &TrueBBI = BBAnalysis[BBI.TrueBB->getNumber()]; + BBInfo &FalseBBI = BBAnalysis[BBI.FalseBB->getNumber()]; + BBInfo *CvtBBI = &TrueBBI; + BBInfo *NextBBI = &FalseBBI; + bool ReserveCond = false; + if (TrueBBI.Kind != ICChild) { + std::swap(CvtBBI, NextBBI); + ReserveCond = true; + } + + FeasibilityAnalysis(*CvtBBI); + if (!CvtBBI->isPredicable) { + BBI.Kind = ICNotClassfied; + return false; + } + + std::vector NewCond(BBI.Cond); + if (ReserveCond) + TII->ReverseBranchCondition(NewCond); + PredicateBlock(CvtBBI->BB, NewCond); + + // Merge converted block into entry block. Also convert the end of the + // block conditional branch (to the non-converted block) into an + // unconditional one. + BBI.Size -= TII->RemoveBranch(*BBI.BB); + BBI.BB->removeSuccessor(CvtBBI->BB); + MergeBlocks(BBI, *CvtBBI); + if (!isNextBlock(BBI.BB, NextBBI->BB)) { + std::vector NoCond; + TII->InsertBranch(*BBI.BB, NextBBI->BB, NULL, NoCond); + } + + // Update block info. + CvtBBI->Kind = ICDead; + + // FIXME: Must maintain LiveIns. + NumIfConvBBs++; + return true; +} + /// IfConvertTriangle - If convert a triangle sub-CFG. /// bool IfConverter::IfConvertTriangle(BBInfo &BBI) { BBInfo &TrueBBI = BBAnalysis[BBI.TrueBB->getNumber()]; FeasibilityAnalysis(TrueBBI); - if (TrueBBI.isPredicable) { - BBInfo &FalseBBI = BBAnalysis[BBI.FalseBB->getNumber()]; + if (!TrueBBI.isPredicable) { + BBI.Kind = ICNotClassfied; + return false; + } - // Predicate the 'true' block after removing its branch. - TrueBBI.Size -= TII->RemoveBranch(*BBI.TrueBB); - PredicateBlock(BBI.TrueBB, BBI.Cond); - - // Join the 'true' and 'false' blocks by copying the instructions - // from the 'false' block to the 'true' block. - BBI.TrueBB->removeSuccessor(BBI.FalseBB); - MergeBlocks(TrueBBI, FalseBBI); + // Predicate the 'true' block after removing its branch. + TrueBBI.Size -= TII->RemoveBranch(*BBI.TrueBB); + PredicateBlock(BBI.TrueBB, BBI.Cond); + + // Join the 'true' and 'false' blocks by copying the instructions + // from the 'false' block to the 'true' block. + BBI.TrueBB->removeSuccessor(BBI.FalseBB); + BBInfo &FalseBBI = BBAnalysis[BBI.FalseBB->getNumber()]; + MergeBlocks(TrueBBI, FalseBBI); - // Now merge the entry of the triangle with the true block. - BBI.Size -= TII->RemoveBranch(*BBI.BB); - MergeBlocks(BBI, TrueBBI); - - // Update block info. - TrueBBI.Kind = ICInvalid; - FalseBBI.Kind = ICInvalid; - - // FIXME: Must maintain LiveIns. - NumIfConvBBs++; - return true; - } - return false; + // Now merge the entry of the triangle with the true block. + BBI.Size -= TII->RemoveBranch(*BBI.BB); + MergeBlocks(BBI, TrueBBI); + + // Update block info. + TrueBBI.Kind = ICDead; + + // FIXME: Must maintain LiveIns. + NumIfConvBBs++; + return true; } /// IfConvertDiamond - If convert a diamond sub-CFG. /// bool IfConverter::IfConvertDiamond(BBInfo &BBI) { + bool TrueNeedCBr; + bool FalseNeedCBr; BBInfo &TrueBBI = BBAnalysis[BBI.TrueBB->getNumber()]; BBInfo &FalseBBI = BBAnalysis[BBI.FalseBB->getNumber()]; FeasibilityAnalysis(TrueBBI); FeasibilityAnalysis(FalseBBI); - if (TrueBBI.isPredicable && FalseBBI.isPredicable) { + SmallVector Dups; + bool Proceed = TrueBBI.isPredicable && FalseBBI.isPredicable; + if (Proceed) { // Check the 'true' and 'false' blocks if either isn't ended with a branch. // Either the block fallthrough to another block or it ends with a // return. If it's the former, add a conditional branch to its successor. - bool Proceed = true; - bool TrueNeedCBr = !TrueBBI.TrueBB && BBI.TrueBB->succ_size(); - bool FalseNeedCBr = !FalseBBI.TrueBB && BBI.FalseBB->succ_size(); + TrueNeedCBr = !TrueBBI.TrueBB && BBI.TrueBB->succ_size(); + FalseNeedCBr = !FalseBBI.TrueBB && BBI.FalseBB->succ_size(); if (TrueNeedCBr && TrueBBI.ClobbersPred) { TrueBBI.isPredicable = false; Proceed = false; @@ -332,102 +401,118 @@ FalseBBI.isPredicable = false; Proceed = false; } - if (!Proceed) - return false; - std::vector Dups; - if (!BBI.TailBB) { - // No common merge block. Check if the terminators (e.g. return) are - // the same or predicable. - MachineBasicBlock::iterator TT = BBI.TrueBB->getFirstTerminator(); - MachineBasicBlock::iterator FT = BBI.FalseBB->getFirstTerminator(); - while (TT != BBI.TrueBB->end() && FT != BBI.FalseBB->end()) { - if (TT->isIdenticalTo(FT)) - Dups.push_back(TT); // Will erase these later. - else if (!TT->isPredicable() && !FT->isPredicable()) - return false; // Can't if-convert. Abort! - ++TT; - ++FT; + if (Proceed) { + if (!BBI.TailBB) { + // No common merge block. Check if the terminators (e.g. return) are + // the same or predicable. + MachineBasicBlock::iterator TT = BBI.TrueBB->getFirstTerminator(); + MachineBasicBlock::iterator FT = BBI.FalseBB->getFirstTerminator(); + while (TT != BBI.TrueBB->end() && FT != BBI.FalseBB->end()) { + if (TT->isIdenticalTo(FT)) + Dups.push_back(TT); // Will erase these later. + else if (!TT->isPredicable() && !FT->isPredicable()) { + Proceed = false; + break; // Can't if-convert. Abort! + } + ++TT; + ++FT; + } + + // One of the two pathes have more terminators, make sure they are + // all predicable. + while (Proceed && TT != BBI.TrueBB->end()) + if (!TT->isPredicable()) { + Proceed = false; + break; // Can't if-convert. Abort! + } + while (Proceed && FT != BBI.FalseBB->end()) + if (!FT->isPredicable()) { + Proceed = false; + break; // Can't if-convert. Abort! + } } - // One of the two pathes have more terminators, make sure they are all - // predicable. - while (TT != BBI.TrueBB->end()) - if (!TT->isPredicable()) - return false; // Can't if-convert. Abort! - while (FT != BBI.FalseBB->end()) - if (!FT->isPredicable()) - return false; // Can't if-convert. Abort! } + } - // Remove the duplicated instructions from the 'true' block. - for (unsigned i = 0, e = Dups.size(); i != e; ++i) { - Dups[i]->eraseFromParent(); - --TrueBBI.Size; - } - - // Predicate the 'true' block after removing its branch. - TrueBBI.Size -= TII->RemoveBranch(*BBI.TrueBB); - PredicateBlock(BBI.TrueBB, BBI.Cond); - - // Add a conditional branch to 'true' successor if needed. - if (TrueNeedCBr) - TII->InsertBranch(*BBI.TrueBB, *BBI.TrueBB->succ_begin(), NULL, BBI.Cond); - - // Predicate the 'false' block. - std::vector NewCond(BBI.Cond); - TII->ReverseBranchCondition(NewCond); - PredicateBlock(BBI.FalseBB, NewCond, true); - - // Add a conditional branch to 'false' successor if needed. - if (FalseNeedCBr) - TII->InsertBranch(*BBI.FalseBB, *BBI.FalseBB->succ_begin(), NULL,NewCond); - - // Merge the 'true' and 'false' blocks by copying the instructions - // from the 'false' block to the 'true' block. That is, unless the true - // block would clobber the predicate, in that case, do the opposite. - BBInfo *CvtBBI; - if (!TrueBBI.ClobbersPred) { - MergeBlocks(TrueBBI, FalseBBI); - CvtBBI = &TrueBBI; - } else { - MergeBlocks(FalseBBI, TrueBBI); - CvtBBI = &FalseBBI; - } + if (!Proceed) { + BBI.Kind = ICNotClassfied; + return false; + } - // Remove the conditional branch from entry to the blocks. - BBI.Size -= TII->RemoveBranch(*BBI.BB); + // Remove the duplicated instructions from the 'true' block. + for (unsigned i = 0, e = Dups.size(); i != e; ++i) { + Dups[i]->eraseFromParent(); + --TrueBBI.Size; + } + + // Predicate the 'true' block after removing its branch. + TrueBBI.Size -= TII->RemoveBranch(*BBI.TrueBB); + PredicateBlock(BBI.TrueBB, BBI.Cond); + + // Add a conditional branch to 'true' successor if needed. + if (TrueNeedCBr && TrueBBI.ClobbersPred && + isNextBlock(BBI.TrueBB, *BBI.TrueBB->succ_begin())) + TrueNeedCBr = false; + if (TrueNeedCBr) + TII->InsertBranch(*BBI.TrueBB, *BBI.TrueBB->succ_begin(), NULL, BBI.Cond); + + // Predicate the 'false' block. + std::vector NewCond(BBI.Cond); + TII->ReverseBranchCondition(NewCond); + PredicateBlock(BBI.FalseBB, NewCond, true); + + // Add a conditional branch to 'false' successor if needed. + if (FalseNeedCBr && !TrueBBI.ClobbersPred && + isNextBlock(BBI.FalseBB, *BBI.FalseBB->succ_begin())) + FalseNeedCBr = false; + if (FalseNeedCBr) + TII->InsertBranch(*BBI.FalseBB, *BBI.FalseBB->succ_begin(), NULL,NewCond); + + // Merge the 'true' and 'false' blocks by copying the instructions + // from the 'false' block to the 'true' block. That is, unless the true + // block would clobber the predicate, in that case, do the opposite. + BBInfo *CvtBBI; + if (!TrueBBI.ClobbersPred) { + MergeBlocks(TrueBBI, FalseBBI); + CvtBBI = &TrueBBI; + } else { + MergeBlocks(FalseBBI, TrueBBI); + CvtBBI = &FalseBBI; + } - // Merge the combined block into the entry of the diamond if the entry - // block is its only predecessor. Otherwise, insert an unconditional - // branch from entry to the if-converted block. - if (CvtBBI->BB->pred_size() == 1) { - BBI.BB->removeSuccessor(CvtBBI->BB); - MergeBlocks(BBI, *CvtBBI); - CvtBBI = &BBI; - } else { - std::vector NoCond; - TII->InsertBranch(*BBI.BB, CvtBBI->BB, NULL, NoCond); - } + // Remove the conditional branch from entry to the blocks. + BBI.Size -= TII->RemoveBranch(*BBI.BB); - // If the if-converted block fallthrough into the tail block, then - // fold the tail block in as well. - if (BBI.TailBB && CvtBBI->BB->succ_size() == 1) { - CvtBBI->Size -= TII->RemoveBranch(*CvtBBI->BB); - CvtBBI->BB->removeSuccessor(BBI.TailBB); - BBInfo TailBBI = BBAnalysis[BBI.TailBB->getNumber()]; - MergeBlocks(*CvtBBI, TailBBI); - TailBBI.Kind = ICInvalid; - } + // Merge the combined block into the entry of the diamond if the entry + // block is its only predecessor. Otherwise, insert an unconditional + // branch from entry to the if-converted block. + if (CvtBBI->BB->pred_size() == 1) { + BBI.BB->removeSuccessor(CvtBBI->BB); + MergeBlocks(BBI, *CvtBBI); + CvtBBI = &BBI; + } else { + std::vector NoCond; + TII->InsertBranch(*BBI.BB, CvtBBI->BB, NULL, NoCond); + } - // Update block info. - TrueBBI.Kind = ICInvalid; - FalseBBI.Kind = ICInvalid; - - // FIXME: Must maintain LiveIns. - NumIfConvBBs += 2; - return true; + // If the if-converted block fallthrough into the tail block, then + // fold the tail block in as well. + if (BBI.TailBB && CvtBBI->BB->succ_size() == 1) { + CvtBBI->Size -= TII->RemoveBranch(*CvtBBI->BB); + CvtBBI->BB->removeSuccessor(BBI.TailBB); + BBInfo TailBBI = BBAnalysis[BBI.TailBB->getNumber()]; + MergeBlocks(*CvtBBI, TailBBI); + TailBBI.Kind = ICDead; } - return false; + + // Update block info. + TrueBBI.Kind = ICDead; + FalseBBI.Kind = ICDead; + + // FIXME: Must maintain LiveIns. + NumIfConvBBs += 2; + return true; } /// PredicateBlock - Predicate every instruction in the block with the specified From dalej at apple.com Mon May 21 17:42:22 2007 From: dalej at apple.com (Dale Johannesen) Date: Mon, 21 May 2007 17:42:22 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.td Message-ID: <200705212242.l4LMgM4P030782@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/ARM: ARMInstrInfo.td updated: 1.105 -> 1.106 --- Log message: Use AXI3 not AXI2 for appropriate PIC PC-relative loads and stores. Cosmetic. --- Diffs of the changes: (+7 -5) ARMInstrInfo.td | 12 +++++++----- 1 files changed, 7 insertions(+), 5 deletions(-) Index: llvm/lib/Target/ARM/ARMInstrInfo.td diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.105 llvm/lib/Target/ARM/ARMInstrInfo.td:1.106 --- llvm/lib/Target/ARM/ARMInstrInfo.td:1.105 Mon May 21 17:14:33 2007 +++ llvm/lib/Target/ARM/ARMInstrInfo.td Mon May 21 17:42:04 2007 @@ -508,6 +508,8 @@ : XI; class AXI2 pattern> : XI; +class AXI3 pattern> + : XI; class AXI4 pattern> : XI; @@ -560,7 +562,7 @@ "${addr:label}:\n\tldr$p $dst, $addr", [(set GPR:$dst, (load addrmodepc:$addr))]>; -def PICLDZH : AXI2<(ops GPR:$dst, addrmodepc:$addr, pred:$p), +def PICLDZH : AXI3<(ops GPR:$dst, addrmodepc:$addr, pred:$p), "${addr:label}:\n\tldr${p}h $dst, $addr", [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>; @@ -568,7 +570,7 @@ "${addr:label}:\n\tldr${p}b $dst, $addr", [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>; -def PICLDH : AXI2<(ops GPR:$dst, addrmodepc:$addr, pred:$p), +def PICLDH : AXI3<(ops GPR:$dst, addrmodepc:$addr, pred:$p), "${addr:label}:\n\tldr${p}h $dst, $addr", [(set GPR:$dst, (extloadi16 addrmodepc:$addr))]>; @@ -576,11 +578,11 @@ "${addr:label}:\n\tldr${p}b $dst, $addr", [(set GPR:$dst, (extloadi8 addrmodepc:$addr))]>; -def PICLDSH : AXI2<(ops GPR:$dst, addrmodepc:$addr, pred:$p), +def PICLDSH : AXI3<(ops GPR:$dst, addrmodepc:$addr, pred:$p), "${addr:label}:\n\tldr${p}sh $dst, $addr", [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>; -def PICLDSB : AXI2<(ops GPR:$dst, addrmodepc:$addr, pred:$p), +def PICLDSB : AXI3<(ops GPR:$dst, addrmodepc:$addr, pred:$p), "${addr:label}:\n\tldr${p}sb $dst, $addr", [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>; } @@ -589,7 +591,7 @@ "${addr:label}:\n\tstr$p $src, $addr", [(store GPR:$src, addrmodepc:$addr)]>; -def PICSTRH : AXI2<(ops GPR:$src, addrmodepc:$addr, pred:$p), +def PICSTRH : AXI3<(ops GPR:$src, addrmodepc:$addr, pred:$p), "${addr:label}:\n\tstr${p}h $src, $addr", [(truncstorei16 GPR:$src, addrmodepc:$addr)]>; From evan.cheng at apple.com Mon May 21 18:17:51 2007 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 21 May 2007 18:17:51 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.cpp Message-ID: <200705212317.l4LNHpdp031340@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/ARM: ARMInstrInfo.cpp updated: 1.29 -> 1.30 --- Log message: Fix some -march=thumb regressions. tBR_JTr is not predicable. --- Diffs of the changes: (+3 -1) ARMInstrInfo.cpp | 4 +++- 1 files changed, 3 insertions(+), 1 deletion(-) Index: llvm/lib/Target/ARM/ARMInstrInfo.cpp diff -u llvm/lib/Target/ARM/ARMInstrInfo.cpp:1.29 llvm/lib/Target/ARM/ARMInstrInfo.cpp:1.30 --- llvm/lib/Target/ARM/ARMInstrInfo.cpp:1.29 Mon May 21 13:56:31 2007 +++ llvm/lib/Target/ARM/ARMInstrInfo.cpp Mon May 21 18:17:32 2007 @@ -498,7 +498,9 @@ // These are jumptable branches, i.e. a branch followed by an inlined // jumptable. The size is 4 + 4 * number of entries. unsigned NumOps = TID->numOperands; - unsigned JTI = MI->getOperand(NumOps-3).getJumpTableIndex(); + MachineOperand JTOP = + MI->getOperand(NumOps - ((TID->Flags & M_PREDICABLE) ? 3 : 2)); + unsigned JTI = JTOP.getJumpTableIndex(); MachineJumpTableInfo *MJTI = MF->getJumpTableInfo(); const std::vector &JT = MJTI->getJumpTables(); assert(JTI < JT.size()); From evan.cheng at apple.com Mon May 21 18:19:51 2007 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 21 May 2007 16:19:51 -0700 Subject: [llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.cpp In-Reply-To: <5FCC976C-143F-452F-86E3-D5CF2AE7600A@apple.com> References: <200705211856.l4LIupA5026535@zion.cs.uiuc.edu> <5FCC976C-143F-452F-86E3-D5CF2AE7600A@apple.com> Message-ID: No. IsTerminatorInstr() simply checks opcode flag, it's not target dependent. Evan On May 21, 2007, at 12:01 PM, Dale Johannesen wrote: > > On May 21, 2007, at 11:56 AM, Evan Cheng wrote: > >> - isTerminatorInstr((--I)->getOpcode())) >> + !isPredicated(--I) && isTerminatorInstr(I->getOpcode())) > > Wouldn't it be better to have isTerminatorInst return false on > predicated things? > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From evan.cheng at apple.com Mon May 21 18:30:51 2007 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 21 May 2007 18:30:51 -0500 Subject: [llvm-commits] CVS: llvm/test/CodeGen/X86/2007-03-18-LiveIntervalAssert.ll Message-ID: <200705212330.l4LNUp0P031591@zion.cs.uiuc.edu> Changes in directory llvm/test/CodeGen/X86: 2007-03-18-LiveIntervalAssert.ll added (r1.1) --- Log message: Add test for PR1259: http://llvm.org/PR1259 . --- Diffs of the changes: (+7 -0) 2007-03-18-LiveIntervalAssert.ll | 7 +++++++ 1 files changed, 7 insertions(+) Index: llvm/test/CodeGen/X86/2007-03-18-LiveIntervalAssert.ll diff -c /dev/null llvm/test/CodeGen/X86/2007-03-18-LiveIntervalAssert.ll:1.1 *** /dev/null Mon May 21 18:30:43 2007 --- llvm/test/CodeGen/X86/2007-03-18-LiveIntervalAssert.ll Mon May 21 18:30:33 2007 *************** *** 0 **** --- 1,7 ---- + ; RUN: llvm-as < %s | llc -march=x86 + ; PR1259 + + define void @test() { + %tmp2 = call i32 asm "...", "=r,~{dirflag},~{fpsr},~{flags},~{dx},~{cx},~{ax}"( ) + unreachable + } From evan.cheng at apple.com Mon May 21 20:22:18 2007 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 21 May 2007 20:22:18 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetInstrInfo.h Message-ID: <200705220122.l4M1MIG1001288@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/Target: TargetInstrInfo.h updated: 1.122 -> 1.123 --- Log message: Consistency. --- Diffs of the changes: (+3 -3) TargetInstrInfo.h | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) Index: llvm/include/llvm/Target/TargetInstrInfo.h diff -u llvm/include/llvm/Target/TargetInstrInfo.h:1.122 llvm/include/llvm/Target/TargetInstrInfo.h:1.123 --- llvm/include/llvm/Target/TargetInstrInfo.h:1.122 Thu May 17 19:01:09 2007 +++ llvm/include/llvm/Target/TargetInstrInfo.h Mon May 21 20:21:58 2007 @@ -217,7 +217,7 @@ bool isCommutableInstr(MachineOpCode Opcode) const { return get(Opcode).Flags & M_COMMUTABLE; } - bool isTerminatorInstr(unsigned Opcode) const { + bool isTerminatorInstr(MachineOpCode Opcode) const { return get(Opcode).Flags & M_TERMINATOR_FLAG; } @@ -244,14 +244,14 @@ /// hasDelaySlot - Returns true if the specified instruction has a delay slot /// which must be filled by the code generator. - bool hasDelaySlot(unsigned Opcode) const { + bool hasDelaySlot(MachineOpCode Opcode) const { return get(Opcode).Flags & M_DELAY_SLOT_FLAG; } /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires /// custom insertion support when the DAG scheduler is inserting it into a /// machine basic block. - bool usesCustomDAGSchedInsertionHook(unsigned Opcode) const { + bool usesCustomDAGSchedInsertionHook(MachineOpCode Opcode) const { return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION; } From clattner at apple.com Mon May 21 20:30:09 2007 From: clattner at apple.com (Chris Lattner) Date: Mon, 21 May 2007 18:30:09 -0700 Subject: [llvm-commits] CVS: llvm/lib/VMCore/AsmWriter.cpp In-Reply-To: <200705190725.l4J7PdY9026973@zion.cs.uiuc.edu> References: <200705190725.l4J7PdY9026973@zion.cs.uiuc.edu> Message-ID: <99B29007-A1AA-4174-A52B-CEA49DEC079B@apple.com> On May 19, 2007, at 12:25 AM, Reid Spencer wrote: > > Adjust how LLVM names are produced: > 1. Always use % for local and @ for global. > 2. Replace NameNeedsQuotes with QuoteNameIfNeeded so that any > adjustments > to the name can be done in one pass. > 3. Implement generation of hex escapes so we don't get "wonky" > characters > in the output. Cool, thanks Reid! > +static std::string QuoteNameIfNeeded(const std::string &Name) { > + std::string result; > + bool needsQuotes = Name[0] >= '0' && Name[0] <= '9'; > + // Scan the name to see if it needs quotes and to replace funky > chars with > + // their octal equivalent. > for (unsigned i = 0, e = Name.size(); i != e; ++i) { > char C = Name[i]; > assert(C != '"' && "Illegal character in LLVM value name!"); > + if (isalnum(C) || C == '-' || C == '.' || C == '_') > + result += C; > + else if (isprint(C)) { Shouldn't this be "isprint(c) && C != '\\' ? Otherwise, you won't escape the quote in "\10" correctly. -Chris > + needsQuotes = true; > + result += C; > + } else { > + needsQuotes = true; > + result += "\\"; > + char hex1 = C & 0x0F; > + if (hex1 < 10) > + result += hex1 + '0'; > + else > + result += hex1 - 10 + 'A'; > + char hex2 = (C >> 4) & 0x0F; > + if (hex2 < 10) > + result += hex2 + '0'; > + else > + result += hex2 - 10 + 'A'; > + } > + } > + if (needsQuotes) { > + result.insert(0,"\""); > + result += '"'; > } > - return false; > + return result; > } > > enum PrefixType { > @@ -202,20 +225,11 @@ > /// surrounded with ""'s (if it has special chars in it). > static std::string getLLVMName(const std::string &Name, PrefixType > Prefix) { > assert(!Name.empty() && "Cannot get empty name!"); > - > - // First character cannot start with a number... > - if (NameNeedsQuotes(Name)) { > - if (Prefix == GlobalPrefix) > - return "@\"" + Name + "\""; > - return "\"" + Name + "\""; > - } > - > - // If we get here, then the identifier is legal to use as a > "VarID". > switch (Prefix) { > default: assert(0 && "Bad prefix!"); > - case GlobalPrefix: return '@' + Name; > - case LabelPrefix: return Name; > - case LocalPrefix: return '%' + Name; > + case GlobalPrefix: return '@' + QuoteNameIfNeeded(Name); > + case LabelPrefix: return QuoteNameIfNeeded(Name); > + case LocalPrefix: return '%' + QuoteNameIfNeeded(Name); > } > } > > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From bruno.cardoso at gmail.com Mon May 21 21:14:37 2007 From: bruno.cardoso at gmail.com (bruno cardoso) Date: Mon, 21 May 2007 23:14:37 -0300 Subject: [llvm-commits] initial mips support! Message-ID: <275e64e40705211914g8cd6283q6c20f93c455e3f98@mail.gmail.com> Hello, With the files on attachment LLVM has now initial support for MIPS. =) The support is still simple and experimental. The status is: x - Mips I instructions, without (coprocessor) float point support. x - Mips o32 ABI calling convention implemented. x - .s files generated by LLC can be compiled with Mips GCC/GAS. x - Simple test programs are working on Linux in a Mips emulated QEMU machine. x - AsmPrinter does not yet generate all Mips GAS pseudo-instructions (such as .cpload, .fmask, .mask) I hope you enjoy! =) Cheers, -- Bruno Cardoso Lopes http://www.brunocardoso.org "The Man in Black fled across the desert and the gunslinger followed" - Childe Roland to the Dark Tower Came -------------- next part -------------- An HTML attachment was scrubbed... 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Name: MipsAsmPrinter.cpp Type: text/x-c++src Size: 9166 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20070521/d82f1817/attachment-0012.bin -------------- next part -------------- A non-text attachment was scrubbed... Name: MipsISelLowering.h Type: text/x-chdr Size: 2749 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20070521/d82f1817/attachment-0013.bin -------------- next part -------------- A non-text attachment was scrubbed... Name: MipsTargetMachine.h Type: text/x-chdr Size: 2223 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20070521/d82f1817/attachment-0014.bin From isanbard at gmail.com Tue May 22 00:15:57 2007 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 22 May 2007 00:15:57 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86.td Message-ID: <200705220515.l4M5Fv0X005697@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86.td updated: 1.33 -> 1.34 --- Log message: We only need to specify the most-implied feature for an architecture. --- Diffs of the changes: (+21 -33) X86.td | 54 +++++++++++++++++++++--------------------------------- 1 files changed, 21 insertions(+), 33 deletions(-) Index: llvm/lib/Target/X86/X86.td diff -u llvm/lib/Target/X86/X86.td:1.33 llvm/lib/Target/X86/X86.td:1.34 --- llvm/lib/Target/X86/X86.td:1.33 Sun May 6 02:56:19 2007 +++ llvm/lib/Target/X86/X86.td Tue May 22 00:15:37 2007 @@ -41,7 +41,7 @@ [Feature3DNow]>; def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true", "Support 64-bit instructions", - [FeatureMMX, FeatureSSE1, FeatureSSE2]>; + [FeatureSSE2]>; //===----------------------------------------------------------------------===// // X86 processors supported. @@ -58,44 +58,32 @@ def : Proc<"i686", []>; def : Proc<"pentiumpro", []>; def : Proc<"pentium2", [FeatureMMX]>; -def : Proc<"pentium3", [FeatureMMX, FeatureSSE1]>; -def : Proc<"pentium-m", [FeatureMMX, FeatureSSE1, FeatureSSE2]>; -def : Proc<"pentium4", [FeatureMMX, FeatureSSE1, FeatureSSE2]>; -def : Proc<"x86-64", [FeatureMMX, FeatureSSE1, FeatureSSE2, - Feature64Bit]>; -def : Proc<"yonah", [FeatureMMX, FeatureSSE1, FeatureSSE2, - FeatureSSE3]>; -def : Proc<"prescott", [FeatureMMX, FeatureSSE1, FeatureSSE2, - FeatureSSE3]>; -def : Proc<"nocona", [FeatureMMX, FeatureSSE1, FeatureSSE2, - FeatureSSE3, Feature64Bit]>; -def : Proc<"core2", [FeatureMMX, FeatureSSE1, FeatureSSE2, - FeatureSSE3, FeatureSSSE3, Feature64Bit]>; +def : Proc<"pentium3", [FeatureSSE1]>; +def : Proc<"pentium-m", [FeatureSSE2]>; +def : Proc<"pentium4", [FeatureSSE2]>; +def : Proc<"x86-64", [Feature64Bit]>; +def : Proc<"yonah", [FeatureSSE3]>; +def : Proc<"prescott", [FeatureSSE3]>; +def : Proc<"nocona", [FeatureSSE3]>; +def : Proc<"core2", [FeatureSSSE3]>; def : Proc<"k6", [FeatureMMX]>; -def : Proc<"k6-2", [FeatureMMX, Feature3DNow]>; -def : Proc<"k6-3", [FeatureMMX, Feature3DNow]>; -def : Proc<"athlon", [FeatureMMX, Feature3DNow, Feature3DNowA]>; -def : Proc<"athlon-tbird", [FeatureMMX, Feature3DNow, Feature3DNowA]>; -def : Proc<"athlon-4", [FeatureMMX, FeatureSSE1, Feature3DNow, - Feature3DNowA]>; -def : Proc<"athlon-xp", [FeatureMMX, FeatureSSE1, Feature3DNow, - Feature3DNowA]>; -def : Proc<"athlon-mp", [FeatureMMX, FeatureSSE1, Feature3DNow, - Feature3DNowA]>; -def : Proc<"k8", [FeatureMMX, FeatureSSE1, FeatureSSE2, - Feature3DNow, Feature3DNowA, Feature64Bit]>; -def : Proc<"opteron", [FeatureMMX, FeatureSSE1, FeatureSSE2, - Feature3DNow, Feature3DNowA, Feature64Bit]>; -def : Proc<"athlon64", [FeatureMMX, FeatureSSE1, FeatureSSE2, - Feature3DNow, Feature3DNowA, Feature64Bit]>; -def : Proc<"athlon-fx", [FeatureMMX, FeatureSSE1, FeatureSSE2, - Feature3DNow, Feature3DNowA, Feature64Bit]>; +def : Proc<"k6-2", [FeatureMMX, Feature3DNow]>; +def : Proc<"k6-3", [FeatureMMX, Feature3DNow]>; +def : Proc<"athlon", [FeatureMMX, Feature3DNowA]>; +def : Proc<"athlon-tbird", [FeatureMMX, Feature3DNowA]>; +def : Proc<"athlon-4", [FeatureSSE1, Feature3DNowA]>; +def : Proc<"athlon-xp", [FeatureSSE1, Feature3DNowA]>; +def : Proc<"athlon-mp", [FeatureSSE1, Feature3DNowA]>; +def : Proc<"k8", [Feature3DNowA, Feature64Bit]>; +def : Proc<"opteron", [Feature3DNowA, Feature64Bit]>; +def : Proc<"athlon64", [Feature3DNowA, Feature64Bit]>; +def : Proc<"athlon-fx", [Feature3DNowA, Feature64Bit]>; def : Proc<"winchip-c6", [FeatureMMX]>; def : Proc<"winchip2", [FeatureMMX, Feature3DNow]>; def : Proc<"c3", [FeatureMMX, Feature3DNow]>; -def : Proc<"c3-2", [FeatureMMX, FeatureSSE1]>; +def : Proc<"c3-2", [FeatureSSE1]>; //===----------------------------------------------------------------------===// // Register File Description From tonic at nondot.org Tue May 22 00:38:59 2007 From: tonic at nondot.org (Tanya Lattner) Date: Tue, 22 May 2007 00:38:59 -0500 Subject: [llvm-commits] [release_20] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp Message-ID: <200705220538.l4M5cx4J006368@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: InstructionCombining.cpp updated: 1.762.2.1 -> 1.762.2.2 --- Log message: Merge from mainline --- Diffs of the changes: (+8 -0) InstructionCombining.cpp | 8 ++++++++ 1 files changed, 8 insertions(+) Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.762.2.1 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.762.2.2 --- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.762.2.1 Fri May 18 01:03:55 2007 +++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Tue May 22 00:38:40 2007 @@ -7773,6 +7773,14 @@ if (Callee->isDeclaration() && !Caller->use_empty() && // Conversion is ok if changing from pointer to int of same size. !(isa(FT->getReturnType()) && + const FunctionType *ActualFT = + cast(cast(CE->getType())->getElementType()); + + // If the parameter attributes don't match up, don't do the xform. We don't + // want to lose an sret attribute or something. + if (FT->getParamAttrs() != ActualFT->getParamAttrs()) + return false; + TD->getIntPtrType() == OldRetTy)) return false; // Cannot transform this return value. From tonic at nondot.org Tue May 22 01:06:40 2007 From: tonic at nondot.org (Tanya Lattner) Date: Tue, 22 May 2007 01:06:40 -0500 Subject: [llvm-commits] CVS: llvm/docs/GettingStarted.html Message-ID: <200705220606.l4M66ebg006823@zion.cs.uiuc.edu> Changes in directory llvm/docs: GettingStarted.html updated: 1.160 -> 1.161 --- Log message: Adding 2.0 release --- Diffs of the changes: (+2 -1) GettingStarted.html | 3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index: llvm/docs/GettingStarted.html diff -u llvm/docs/GettingStarted.html:1.160 llvm/docs/GettingStarted.html:1.161 --- llvm/docs/GettingStarted.html:1.160 Thu May 10 01:42:21 2007 +++ llvm/docs/GettingStarted.html Tue May 22 01:06:22 2007 @@ -701,6 +701,7 @@ labels: