Deleting a global variable from a module is similar to deleting an -instruction. First, you must have a pointer to the global variable that you wish - to delete. Second, you must have a pointer to the module the global variable - belongs to. You use the pointer to the module to get its list of global - variables and then use the erase function to remove your global variable. +

Deleting a global variable from a module is just as easy as deleting an +Instruction. First, you must have a pointer to the global variable that you wish + to delete. You use this pointer to erase it from its parent, the module. For example:

 GlobalVariable *GV = .. ;
-Module *M = GV->getParent();
 
-M->getGlobaleList().erase(GV);
+GV->eraseFromParent();

@@ -3086,7 +3083,7 @@ Dinakar Dhurjati and Chris Lattner
The LLVM Compiler Infrastructure
- Last modified: $Date: 2007/06/20 18:33:15 $ + Last modified: $Date: 2007/06/20 20:46:37 $ From evan.cheng at apple.com Wed Jun 20 15:50:09 2007 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 20 Jun 2007 15:50:09 -0500 Subject: [llvm-commits] CVS: llvm-test/MultiSource/Applications/spiff/Makefile spiff.c Message-ID: <200706202050.l5KKo9ou021547@zion.cs.uiuc.edu> Changes in directory llvm-test/MultiSource/Applications/spiff: Makefile updated: 1.3 -> 1.4 spiff.c updated: 1.2 -> 1.3 --- Log message: Increase test size to something reasonable. --- Diffs of the changes: (+18 -8) Makefile | 3 ++- spiff.c | 23 ++++++++++++++++------- 2 files changed, 18 insertions(+), 8 deletions(-) Index: llvm-test/MultiSource/Applications/spiff/Makefile diff -u llvm-test/MultiSource/Applications/spiff/Makefile:1.3 llvm-test/MultiSource/Applications/spiff/Makefile:1.4 --- llvm-test/MultiSource/Applications/spiff/Makefile:1.3 Fri Jul 29 13:08:48 2005 +++ llvm-test/MultiSource/Applications/spiff/Makefile Wed Jun 20 15:49:47 2007 @@ -4,7 +4,8 @@ CFLAGS = LDFLAGS = -RUN_OPTIONS = $(PROJ_SRC_DIR)/Sample.1 $(PROJ_SRC_DIR)/Sample.2 +#RUN_OPTIONS = $(PROJ_SRC_DIR)/Sample.1 $(PROJ_SRC_DIR)/Sample.2 +RUN_OPTIONS = $(PROJ_SRC_DIR)/Sample.3 $(PROJ_SRC_DIR)/Sample.4 #RUN_OPTIONS = ./Sample.3 ./Sample.4 #RUN_OPTIONS = ./one ./two # you get the idea... Index: llvm-test/MultiSource/Applications/spiff/spiff.c diff -u llvm-test/MultiSource/Applications/spiff/spiff.c:1.2 llvm-test/MultiSource/Applications/spiff/spiff.c:1.3 --- llvm-test/MultiSource/Applications/spiff/spiff.c:1.2 Wed Sep 1 09:33:21 2004 +++ llvm-test/MultiSource/Applications/spiff/spiff.c Wed Jun 20 15:49:47 2007 @@ -8,7 +8,7 @@ #ifndef lint -static char rcsid[]= "$Header: /var/cvs/llvm/llvm-test/MultiSource/Applications/spiff/spiff.c,v 1.2 2004/09/01 14:33:21 criswell Exp $"; +static char rcsid[]= "$Header: /var/cvs/llvm/llvm-test/MultiSource/Applications/spiff/spiff.c,v 1.3 2007/06/20 20:49:47 evancheng Exp $"; #endif @@ -38,6 +38,12 @@ */ static int _Y_flags; +#ifdef SMALL_PROBLEM_SIZE +#define SPIFF_ITER 1000 +#else +#define SPIFF_ITER 30000 +#endif + int main(argc,argv) int argc; @@ -107,16 +113,19 @@ if (-1 == max_d) max_d = K_gettmax(0) + K_gettmax(1); - if (_Y_eflag) - { + for(i=0;i<=SPIFF_ITER;i++) + { + if (_Y_eflag) + { edit_end = Q_do_exact(K_gettmax(0),K_gettmax(1), max_d,_Y_flags); - } - else - { + } + else + { edit_end = G_do_miller(K_gettmax(0), K_gettmax(1), max_d,_Y_flags); - } + } + } if (E_NULL != edit_end) { From resistor at mac.com Wed Jun 20 17:10:25 2007 From: resistor at mac.com (Owen Anderson) Date: Wed, 20 Jun 2007 17:10:25 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/GVNPRE.cpp Message-ID: <200706202210.l5KMAPMv023106@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: GVNPRE.cpp updated: 1.45 -> 1.46 --- Log message: Split runOnFunction into many smaller functions. This make it easier to get accurate performance analysis of GVNPRE. --- Diffs of the changes: (+329 -279) GVNPRE.cpp | 608 +++++++++++++++++++++++++++++++++---------------------------- 1 files changed, 329 insertions(+), 279 deletions(-) Index: llvm/lib/Transforms/Scalar/GVNPRE.cpp diff -u llvm/lib/Transforms/Scalar/GVNPRE.cpp:1.45 llvm/lib/Transforms/Scalar/GVNPRE.cpp:1.46 --- llvm/lib/Transforms/Scalar/GVNPRE.cpp:1.45 Wed Jun 20 13:30:20 2007 +++ llvm/lib/Transforms/Scalar/GVNPRE.cpp Wed Jun 20 17:10:02 2007 @@ -327,7 +327,6 @@ std::map > availableOut; std::map > anticipatedIn; - std::map invokeDep; virtual void getAnalysisUsage(AnalysisUsage &AU) const { AU.setPreservesCFG(); @@ -348,14 +347,34 @@ void topo_sort(std::set& set, std::vector& vec); - // For a given block, calculate the generated expressions, temporaries, - // and the AVAIL_OUT set void cleanup(); - void elimination(bool& changed_function); + bool elimination(); void val_insert(std::set& s, Value* v); void val_replace(std::set& s, Value* v); bool dependsOnInvoke(Value* V); + void buildsets_availout(BasicBlock::iterator I, + std::set& currAvail, + std::set& currPhis, + std::set& currExps, + std::set& currTemps); + void buildsets_anticout(BasicBlock* BB, + std::set& anticOut, + std::set& visited); + bool buildsets_anticin(BasicBlock* BB, + std::set& anticOut, + std::set& currExps, + std::set& currTemps, + std::set& visited); + unsigned buildsets(Function& F); + + void insertion_pre(Value* e, BasicBlock* BB, + std::map& avail, + std::set& new_set); + unsigned insertion_mergepoint(std::vector& workList, + df_iterator D, + std::set& new_set); + bool insertion(Function& F); }; @@ -656,9 +675,11 @@ DOUT << "}\n\n"; } -void GVNPRE::elimination(bool& changed_function) { +bool GVNPRE::elimination() { DOUT << "\n\nPhase 3: Elimination\n\n"; + bool changed_function = false; + std::vector > replace; std::vector erase; @@ -699,6 +720,8 @@ for (std::vector::iterator I = erase.begin(), E = erase.end(); I != E; ++I) (*I)->eraseFromParent(); + + return changed_function; } @@ -711,24 +734,132 @@ } } -bool GVNPRE::runOnFunction(Function &F) { - VN.clear(); - createdExpressions.clear(); - availableOut.clear(); - anticipatedIn.clear(); - invokeDep.clear(); +void GVNPRE::buildsets_availout(BasicBlock::iterator I, + std::set& currAvail, + std::set& currPhis, + std::set& currExps, + std::set& currTemps) { + // Handle PHI nodes... + if (PHINode* p = dyn_cast(I)) { + VN.lookup_or_add(p); + currPhis.insert(p); + + // Handle binary ops... + } else if (BinaryOperator* BO = dyn_cast(I)) { + Value* leftValue = BO->getOperand(0); + Value* rightValue = BO->getOperand(1); + + VN.lookup_or_add(BO); + + if (isa(leftValue)) + val_insert(currExps, leftValue); + if (isa(rightValue)) + val_insert(currExps, rightValue); + val_insert(currExps, BO); + + // Handle cmp ops... + } else if (CmpInst* C = dyn_cast(I)) { + Value* leftValue = C->getOperand(0); + Value* rightValue = C->getOperand(1); + + VN.lookup_or_add(C); + + if (isa(leftValue)) + val_insert(currExps, leftValue); + if (isa(rightValue)) + val_insert(currExps, rightValue); + val_insert(currExps, C); + + // Handle unsupported ops + } else if (!I->isTerminator()){ + VN.lookup_or_add(I); + currTemps.insert(I); + } + + if (!I->isTerminator()) + val_insert(currAvail, I); +} + +void GVNPRE::buildsets_anticout(BasicBlock* BB, + std::set& anticOut, + std::set& visited) { + if (BB->getTerminator()->getNumSuccessors() == 1) { + if (visited.find(BB->getTerminator()->getSuccessor(0)) == visited.end()) + phi_translate_set(VN.getMaximalValues(), BB, + BB->getTerminator()->getSuccessor(0), anticOut); + else + phi_translate_set(anticipatedIn[BB->getTerminator()->getSuccessor(0)], + BB, BB->getTerminator()->getSuccessor(0), anticOut); + } else if (BB->getTerminator()->getNumSuccessors() > 1) { + BasicBlock* first = BB->getTerminator()->getSuccessor(0); + anticOut.insert(anticipatedIn[first].begin(), anticipatedIn[first].end()); + + for (unsigned i = 1; i < BB->getTerminator()->getNumSuccessors(); ++i) { + BasicBlock* currSucc = BB->getTerminator()->getSuccessor(i); + std::set& succAnticIn = anticipatedIn[currSucc]; + + std::set temp; + std::insert_iterator > temp_ins(temp, temp.begin()); + std::set_intersection(anticOut.begin(), anticOut.end(), + succAnticIn.begin(), succAnticIn.end(), temp_ins); + + anticOut.clear(); + anticOut.insert(temp.begin(), temp.end()); + } + } +} + +bool GVNPRE::buildsets_anticin(BasicBlock* BB, + std::set& anticOut, + std::set& currExps, + std::set& currTemps, + std::set& visited) { + std::set& anticIn = anticipatedIn[BB]; + std::set old (anticIn.begin(), anticIn.end()); + + buildsets_anticout(BB, anticOut, visited); + + std::set S; + std::insert_iterator > s_ins(S, S.begin()); + std::set_difference(anticOut.begin(), anticOut.end(), + currTemps.begin(), currTemps.end(), s_ins); + + anticIn.clear(); + std::insert_iterator > ai_ins(anticIn, anticIn.begin()); + std::set_difference(currExps.begin(), currExps.end(), + currTemps.begin(), currTemps.end(), ai_ins); + + for (std::set::iterator I = S.begin(), E = S.end(); + I != E; ++I) { + // For non-opaque values, we should already have a value numbering. + // However, for opaques, such as constants within PHI nodes, it is + // possible that they have not yet received a number. Make sure they do + // so now. + uint32_t valNum = 0; + if (isa(*I) || isa(*I)) + valNum = VN.lookup(*I); + else + valNum = VN.lookup_or_add(*I); + if (find_leader(anticIn, valNum) == 0) + val_insert(anticIn, *I); + } + + clean(anticIn); + anticOut.clear(); - bool changed_function = false; + if (old.size() != anticIn.size()) + return true; + else + return false; +} +unsigned GVNPRE::buildsets(Function& F) { std::map > generatedExpressions; std::map > generatedPhis; std::map > generatedTemporaries; - - + DominatorTree &DT = getAnalysis(); - // Phase 1: BuildSets - // Phase 1, Part 1: calculate AVAIL_OUT // Top-down walk of the dominator tree @@ -750,61 +881,21 @@ for (BasicBlock::iterator BI = BB->begin(), BE = BB->end(); - BI != BE; ++BI) { - - // Handle PHI nodes... - if (PHINode* p = dyn_cast(BI)) { - VN.lookup_or_add(p); - currPhis.insert(p); - - // Handle binary ops... - } else if (BinaryOperator* BO = dyn_cast(BI)) { - Value* leftValue = BO->getOperand(0); - Value* rightValue = BO->getOperand(1); - - VN.lookup_or_add(BO); - - if (isa(leftValue)) - val_insert(currExps, leftValue); - if (isa(rightValue)) - val_insert(currExps, rightValue); - val_insert(currExps, BO); - - // Handle cmp ops... - } else if (CmpInst* C = dyn_cast(BI)) { - Value* leftValue = C->getOperand(0); - Value* rightValue = C->getOperand(1); - - VN.lookup_or_add(C); - - if (isa(leftValue)) - val_insert(currExps, leftValue); - if (isa(rightValue)) - val_insert(currExps, rightValue); - val_insert(currExps, C); + BI != BE; ++BI) + buildsets_availout(BI, currAvail, currPhis, currExps, currTemps); - // Handle unsupported ops - } else if (!BI->isTerminator()){ - VN.lookup_or_add(BI); - currTemps.insert(BI); - } - - if (!BI->isTerminator()) - val_insert(currAvail, BI); - } } - DOUT << "Maximal Set: "; - dump(VN.getMaximalValues()); - DOUT << "\n"; - // If function has no exit blocks, only perform GVN PostDominatorTree &PDT = getAnalysis(); if (PDT[&F.getEntryBlock()] == 0) { - elimination(changed_function); + bool changed_function = elimination(); cleanup(); - return true; + if (changed_function) + return 2; // Bailed early, made changes + else + return 1; // Bailed early, no changes } @@ -826,92 +917,10 @@ if (BB == 0) continue; - DOUT << "Block: " << BB->getName() << "\n"; - DOUT << "TMP_GEN: "; - dump(generatedTemporaries[BB]); - DOUT << "\n"; - - DOUT << "EXP_GEN: "; - dump(generatedExpressions[BB]); visited.insert(BB); - std::set& anticIn = anticipatedIn[BB]; - std::set old (anticIn.begin(), anticIn.end()); - - if (BB->getTerminator()->getNumSuccessors() == 1) { - if (visited.find(BB->getTerminator()->getSuccessor(0)) == - visited.end()) - phi_translate_set(VN.getMaximalValues(), BB, - BB->getTerminator()->getSuccessor(0), - anticOut); - else - phi_translate_set(anticipatedIn[BB->getTerminator()->getSuccessor(0)], - BB, BB->getTerminator()->getSuccessor(0), - anticOut); - } else if (BB->getTerminator()->getNumSuccessors() > 1) { - BasicBlock* first = BB->getTerminator()->getSuccessor(0); - anticOut.insert(anticipatedIn[first].begin(), - anticipatedIn[first].end()); - for (unsigned i = 1; i < BB->getTerminator()->getNumSuccessors(); ++i) { - BasicBlock* currSucc = BB->getTerminator()->getSuccessor(i); - std::set& succAnticIn = anticipatedIn[currSucc]; - - std::set temp; - std::insert_iterator > temp_ins(temp, - temp.begin()); - std::set_intersection(anticOut.begin(), anticOut.end(), - succAnticIn.begin(), succAnticIn.end(), - temp_ins); - - anticOut.clear(); - anticOut.insert(temp.begin(), temp.end()); - } - } - - DOUT << "ANTIC_OUT: "; - dump(anticOut); - DOUT << "\n"; - - std::set S; - std::insert_iterator > s_ins(S, S.begin()); - std::set_difference(anticOut.begin(), anticOut.end(), - generatedTemporaries[BB].begin(), - generatedTemporaries[BB].end(), - s_ins); - - anticIn.clear(); - std::insert_iterator > ai_ins(anticIn, anticIn.begin()); - std::set_difference(generatedExpressions[BB].begin(), - generatedExpressions[BB].end(), - generatedTemporaries[BB].begin(), - generatedTemporaries[BB].end(), - ai_ins); - - for (std::set::iterator I = S.begin(), E = S.end(); - I != E; ++I) { - // For non-opaque values, we should already have a value numbering. - // However, for opaques, such as constants within PHI nodes, it is - // possible that they have not yet received a number. Make sure they do - // so now. - uint32_t valNum = 0; - if (isa(*I) || isa(*I)) - valNum = VN.lookup(*I); - else - valNum = VN.lookup_or_add(*I); - if (find_leader(anticIn, valNum) == 0) - val_insert(anticIn, *I); - } - - clean(anticIn); - - DOUT << "ANTIC_IN: "; - dump(anticIn); - DOUT << "\n"; - - if (old.size() != anticIn.size()) - changed = true; - - anticOut.clear(); + changed |= buildsets_anticin(BB, anticOut, generatedTemporaries[BB], + generatedExpressions[BB], visited); } iterations++; @@ -939,15 +948,156 @@ DOUT << "\n"; } - // Phase 2: Insert - DOUT<< "\nPhase 2: Insertion\n"; + return 0; // No bail, no changes +} + +void GVNPRE::insertion_pre(Value* e, BasicBlock* BB, + std::map& avail, + std::set& new_set) { + DOUT << "Processing Value: "; + DEBUG(e->dump()); + DOUT << "\n\n"; + + for (pred_iterator PI = pred_begin(BB), PE = pred_end(BB); PI != PE; ++PI) { + Value* e2 = avail[*PI]; + if (!find_leader(availableOut[*PI], VN.lookup(e2))) { + User* U = cast(e2); + + Value* s1 = 0; + if (isa(U->getOperand(0)) || + isa(U->getOperand(0))) + s1 = find_leader(availableOut[*PI], VN.lookup(U->getOperand(0))); + else + s1 = U->getOperand(0); + + Value* s2 = 0; + if (isa(U->getOperand(1)) || + isa(U->getOperand(1))) + s2 = find_leader(availableOut[*PI], VN.lookup(U->getOperand(1))); + else + s2 = U->getOperand(1); + + Value* newVal = 0; + if (BinaryOperator* BO = dyn_cast(U)) + newVal = BinaryOperator::create(BO->getOpcode(), s1, s2, + BO->getName()+".gvnpre", + (*PI)->getTerminator()); + else if (CmpInst* C = dyn_cast(U)) + newVal = CmpInst::create(C->getOpcode(), C->getPredicate(), s1, s2, + C->getName()+".gvnpre", + (*PI)->getTerminator()); + + VN.add(newVal, VN.lookup(U)); + + std::set& predAvail = availableOut[*PI]; + val_replace(predAvail, newVal); + + DOUT << "Creating value: " << std::hex << newVal << std::dec << "\n"; + + std::map::iterator av = avail.find(*PI); + if (av != avail.end()) + avail.erase(av); + avail.insert(std::make_pair(*PI, newVal)); + + ++NumInsertedVals; + } + } + + PHINode* p = 0; + + for (pred_iterator PI = pred_begin(BB), PE = pred_end(BB); PI != PE; ++PI) { + if (p == 0) + p = new PHINode(avail[*PI]->getType(), "gvnpre-join", BB->begin()); + + p->addIncoming(avail[*PI], *PI); + } + + VN.add(p, VN.lookup(e)); + DOUT << "Creating value: " << std::hex << p << std::dec << "\n"; + + val_replace(availableOut[BB], p); + + DOUT << "Preds After Processing: "; + for (pred_iterator PI = pred_begin(BB), PE = pred_end(BB); PI != PE; ++PI) + DEBUG((*PI)->dump()); + DOUT << "\n\n"; + + DOUT << "Merge Block After Processing: "; + DEBUG(BB->dump()); + DOUT << "\n\n"; + + new_set.insert(p); + + ++NumInsertedPhis; +} + +unsigned GVNPRE::insertion_mergepoint(std::vector& workList, + df_iterator D, + std::set& new_set) { + bool changed_function = false; + bool new_stuff = false; + + BasicBlock* BB = D->getBlock(); + for (unsigned i = 0; i < workList.size(); ++i) { + Value* e = workList[i]; + + if (isa(e) || isa(e)) { + if (find_leader(availableOut[D->getIDom()->getBlock()], + VN.lookup(e)) != 0) + continue; + + std::map avail; + bool by_some = false; + int num_avail = 0; + + for (pred_iterator PI = pred_begin(BB), PE = pred_end(BB); PI != PE; + ++PI) { + Value *e2 = phi_translate(e, *PI, BB); + Value *e3 = find_leader(availableOut[*PI], VN.lookup(e2)); + + if (e3 == 0) { + std::map::iterator av = avail.find(*PI); + if (av != avail.end()) + avail.erase(av); + avail.insert(std::make_pair(*PI, e2)); + } else { + std::map::iterator av = avail.find(*PI); + if (av != avail.end()) + avail.erase(av); + avail.insert(std::make_pair(*PI, e3)); + + by_some = true; + num_avail++; + } + } + + if (by_some && num_avail < std::distance(pred_begin(BB), pred_end(BB))) { + insertion_pre(e, BB, avail, new_set); + + changed_function = true; + new_stuff = true; + } + } + } + + unsigned retval = 0; + if (changed_function) + retval += 1; + if (new_stuff) + retval += 2; + + return retval; +} + +bool GVNPRE::insertion(Function& F) { + bool changed_function = false; + + DominatorTree &DT = getAnalysis(); std::map > new_sets; - unsigned i_iterations = 0; bool new_stuff = true; while (new_stuff) { new_stuff = false; - DOUT << "Iteration: " << i_iterations << "\n\n"; for (df_iterator DI = df_begin(DT.getRootNode()), E = df_end(DT.getRootNode()); DI != E; ++DI) { BasicBlock* BB = DI->getBlock(); @@ -981,139 +1131,39 @@ dump(anticIn); DOUT << "\n"; - for (unsigned i = 0; i < workList.size(); ++i) { - Value* e = workList[i]; - - if (isa(e) || isa(e)) { - if (find_leader(availableOut[DI->getIDom()->getBlock()], VN.lookup(e)) != 0) - continue; - - std::map avail; - bool by_some = false; - int num_avail = 0; - - for (pred_iterator PI = pred_begin(BB), PE = pred_end(BB); PI != PE; - ++PI) { - Value *e2 = phi_translate(e, *PI, BB); - Value *e3 = find_leader(availableOut[*PI], VN.lookup(e2)); - - if (e3 == 0) { - std::map::iterator av = avail.find(*PI); - if (av != avail.end()) - avail.erase(av); - avail.insert(std::make_pair(*PI, e2)); - } else { - std::map::iterator av = avail.find(*PI); - if (av != avail.end()) - avail.erase(av); - avail.insert(std::make_pair(*PI, e3)); - - by_some = true; - num_avail++; - } - } - - if (by_some && - num_avail < std::distance(pred_begin(BB), pred_end(BB))) { - DOUT << "Processing Value: "; - DEBUG(e->dump()); - DOUT << "\n\n"; - - for (pred_iterator PI = pred_begin(BB), PE = pred_end(BB); - PI != PE; ++PI) { - Value* e2 = avail[*PI]; - if (!find_leader(availableOut[*PI], VN.lookup(e2))) { - User* U = cast(e2); - - Value* s1 = 0; - if (isa(U->getOperand(0)) || - isa(U->getOperand(0))) - s1 = find_leader(availableOut[*PI], VN.lookup(U->getOperand(0))); - else - s1 = U->getOperand(0); - - Value* s2 = 0; - if (isa(U->getOperand(1)) || - isa(U->getOperand(1))) - s2 = find_leader(availableOut[*PI], VN.lookup(U->getOperand(1))); - else - s2 = U->getOperand(1); - - Value* newVal = 0; - if (BinaryOperator* BO = dyn_cast(U)) - newVal = BinaryOperator::create(BO->getOpcode(), - s1, s2, - BO->getName()+".gvnpre", - (*PI)->getTerminator()); - else if (CmpInst* C = dyn_cast(U)) - newVal = CmpInst::create(C->getOpcode(), - C->getPredicate(), - s1, s2, - C->getName()+".gvnpre", - (*PI)->getTerminator()); - - changed_function = true; - - VN.add(newVal, VN.lookup(U)); - - std::set& predAvail = availableOut[*PI]; - val_replace(predAvail, newVal); - - DOUT << "Creating value: " << std::hex << newVal << std::dec << "\n"; - - std::map::iterator av = avail.find(*PI); - if (av != avail.end()) - avail.erase(av); - avail.insert(std::make_pair(*PI, newVal)); - - ++NumInsertedVals; - } - } - - PHINode* p = 0; - - for (pred_iterator PI = pred_begin(BB), PE = pred_end(BB); - PI != PE; ++PI) { - if (p == 0) - p = new PHINode(avail[*PI]->getType(), "gvnpre-join", - BB->begin()); - - p->addIncoming(avail[*PI], *PI); - } - - changed_function = true; - - VN.add(p, VN.lookup(e)); - DOUT << "Creating value: " << std::hex << p << std::dec << "\n"; - - val_replace(availOut, p); - availOut.insert(p); - - new_stuff = true; - - DOUT << "Preds After Processing: "; - for (pred_iterator PI = pred_begin(BB), PE = pred_end(BB); - PI != PE; ++PI) - DEBUG((*PI)->dump()); - DOUT << "\n\n"; - - DOUT << "Merge Block After Processing: "; - DEBUG(BB->dump()); - DOUT << "\n\n"; - - new_set.insert(p); - - ++NumInsertedPhis; - } - } - } + unsigned result = insertion_mergepoint(workList, DI, new_set); + if (result & 1) + changed_function = true; + if (result & 2) + new_stuff = true; } } - i_iterations++; } + return changed_function; +} + +bool GVNPRE::runOnFunction(Function &F) { + VN.clear(); + createdExpressions.clear(); + availableOut.clear(); + anticipatedIn.clear(); + + bool changed_function = false; + + // Phase 1: BuildSets + unsigned bail = buildsets(F); + //If a bail occurred, terminate early + if (bail != 0) + return (bail == 2); + + // Phase 2: Insert + DOUT<< "\nPhase 2: Insertion\n"; + + changed_function |= insertion(F); + // Phase 3: Eliminate - elimination(changed_function); + changed_function |= elimination(); // Phase 4: Cleanup cleanup(); From sabre at nondot.org Wed Jun 20 18:46:48 2007 From: sabre at nondot.org (Chris Lattner) Date: Wed, 20 Jun 2007 18:46:48 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp Message-ID: <200706202346.l5KNkmtj025054@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: InstructionCombining.cpp updated: 1.773 -> 1.774 --- Log message: refactor a bunch of code out of visitICmpInstWithInstAndIntCst into its own routine. --- Diffs of the changes: (+134 -123) InstructionCombining.cpp | 257 ++++++++++++++++++++++++----------------------- 1 files changed, 134 insertions(+), 123 deletions(-) Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.773 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.774 --- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.773 Tue Jun 19 00:43:49 2007 +++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Wed Jun 20 18:46:26 2007 @@ -189,6 +189,8 @@ Instruction *visitICmpInstWithInstAndIntCst(ICmpInst &ICI, Instruction *LHS, ConstantInt *RHS); + Instruction *FoldICmpDivCst(ICmpInst &ICI, BinaryOperator *DivI, + ConstantInt *DivRHS); Instruction *FoldGEPICmp(User *GEPLHS, Value *RHS, ICmpInst::Predicate Cond, Instruction &I); @@ -5109,6 +5111,134 @@ return Changed ? &I : 0; } + +/// FoldICmpDivCst - Fold "icmp pred, ([su]div X, DivRHS), CmpRHS" where DivRHS +/// and CmpRHS are both known to be integer constants. +Instruction *InstCombiner::FoldICmpDivCst(ICmpInst &ICI, BinaryOperator *DivI, + ConstantInt *DivRHS) { + ConstantInt *CmpRHS = cast(ICI.getOperand(1)); + const APInt &CmpRHSV = CmpRHS->getValue(); + + // FIXME: If the operand types don't match the type of the divide + // then don't attempt this transform. The code below doesn't have the + // logic to deal with a signed divide and an unsigned compare (and + // vice versa). This is because (x /s C1) getOpcode() == Instruction::SDiv; + if (!ICI.isEquality() && DivIsSigned != ICI.isSignedPredicate()) + return 0; + if (DivRHS->isZero()) + return 0; // Don't hack on div by zero + + // Initialize the variables that will indicate the nature of the + // range check. + bool LoOverflow = false, HiOverflow = false; + ConstantInt *LoBound = 0, *HiBound = 0; + + // Compute Prod = CI * DivRHS. We are essentially solving an equation + // of form X/C1=C2. We solve for X by multiplying C1 (DivRHS) and + // C2 (CI). By solving for X we can turn this into a range check + // instead of computing a divide. + ConstantInt *Prod = Multiply(CmpRHS, DivRHS); + + // Determine if the product overflows by seeing if the product is + // not equal to the divide. Make sure we do the same kind of divide + // as in the LHS instruction that we're folding. + bool ProdOV = (DivIsSigned ? ConstantExpr::getSDiv(Prod, DivRHS) : + ConstantExpr::getUDiv(Prod, DivRHS)) != CmpRHS; + + // Get the ICmp opcode + ICmpInst::Predicate predicate = ICI.getPredicate(); + + if (!DivIsSigned) { // udiv + LoBound = Prod; + LoOverflow = ProdOV; + HiOverflow = ProdOV || AddWithOverflow(HiBound, LoBound, DivRHS, false); + } else if (DivRHS->getValue().isPositive()) { // Divisor is > 0. + if (CmpRHSV == 0) { // (X / pos) op 0 + // Can't overflow. + LoBound = cast(ConstantExpr::getNeg(SubOne(DivRHS))); + HiBound = DivRHS; + } else if (CmpRHSV.isPositive()) { // (X / pos) op pos + LoBound = Prod; + LoOverflow = ProdOV; + HiOverflow = ProdOV || AddWithOverflow(HiBound, Prod, DivRHS, true); + } else { // (X / pos) op neg + Constant *DivRHSH = ConstantExpr::getNeg(SubOne(DivRHS)); + LoOverflow = AddWithOverflow(LoBound, Prod, + cast(DivRHSH), true); + HiBound = AddOne(Prod); + HiOverflow = ProdOV; + } + } else { // Divisor is < 0. + if (CmpRHSV == 0) { // (X / neg) op 0 + LoBound = AddOne(DivRHS); + HiBound = cast(ConstantExpr::getNeg(DivRHS)); + if (HiBound == DivRHS) + return 0; // - INTMIN = INTMIN + } else if (CmpRHSV.isPositive()) { // (X / neg) op pos + HiOverflow = LoOverflow = ProdOV; + if (!LoOverflow) + LoOverflow = AddWithOverflow(LoBound, Prod, AddOne(DivRHS), + true); + HiBound = AddOne(Prod); + } else { // (X / neg) op neg + LoBound = Prod; + LoOverflow = HiOverflow = ProdOV; + HiBound = Subtract(Prod, DivRHS); + } + + // Dividing by a negate swaps the condition. + predicate = ICmpInst::getSwappedPredicate(predicate); + } + + Value *X = DivI->getOperand(0); + switch (predicate) { + default: assert(0 && "Unhandled icmp opcode!"); + case ICmpInst::ICMP_EQ: + if (LoOverflow && HiOverflow) + return ReplaceInstUsesWith(ICI, ConstantInt::getFalse()); + else if (HiOverflow) + return new ICmpInst(DivIsSigned ? ICmpInst::ICMP_SGE : + ICmpInst::ICMP_UGE, X, LoBound); + else if (LoOverflow) + return new ICmpInst(DivIsSigned ? ICmpInst::ICMP_SLT : + ICmpInst::ICMP_ULT, X, HiBound); + else + return InsertRangeTest(X, LoBound, HiBound, DivIsSigned, + true, ICI); + case ICmpInst::ICMP_NE: + if (LoOverflow && HiOverflow) + return ReplaceInstUsesWith(ICI, ConstantInt::getTrue()); + else if (HiOverflow) + return new ICmpInst(DivIsSigned ? ICmpInst::ICMP_SLT : + ICmpInst::ICMP_ULT, X, LoBound); + else if (LoOverflow) + return new ICmpInst(DivIsSigned ? ICmpInst::ICMP_SGE : + ICmpInst::ICMP_UGE, X, HiBound); + else + return InsertRangeTest(X, LoBound, HiBound, DivIsSigned, + false, ICI); + case ICmpInst::ICMP_ULT: + case ICmpInst::ICMP_SLT: + if (LoOverflow) + return ReplaceInstUsesWith(ICI, ConstantInt::getFalse()); + return new ICmpInst(predicate, X, LoBound); + case ICmpInst::ICMP_UGT: + case ICmpInst::ICMP_SGT: + if (HiOverflow) + return ReplaceInstUsesWith(ICI, ConstantInt::getFalse()); + if (predicate == ICmpInst::ICMP_UGT) + return new ICmpInst(ICmpInst::ICMP_UGE, X, HiBound); + else + return new ICmpInst(ICmpInst::ICMP_SGE, X, HiBound); + } +} + + /// visitICmpInstWithInstAndIntCst - Handle "icmp (instr, intcst)". /// Instruction *InstCombiner::visitICmpInstWithInstAndIntCst(ICmpInst &ICI, @@ -5357,129 +5487,10 @@ // checked. If there is an overflow on the low or high side, remember // it, otherwise compute the range [low, hi) bounding the new value. // See: InsertRangeTest above for the kinds of replacements possible. - if (ConstantInt *DivRHS = dyn_cast(LHSI->getOperand(1))) { - // FIXME: If the operand types don't match the type of the divide - // then don't attempt this transform. The code below doesn't have the - // logic to deal with a signed divide and an unsigned compare (and - // vice versa). This is because (x /s C1) getOpcode() == Instruction::SDiv; - if (!ICI.isEquality() && DivIsSigned != ICI.isSignedPredicate()) - break; - if (DivRHS->isZero()) - break; // Don't hack on div by zero - - // Initialize the variables that will indicate the nature of the - // range check. - bool LoOverflow = false, HiOverflow = false; - ConstantInt *LoBound = 0, *HiBound = 0; - - // Compute Prod = CI * DivRHS. We are essentially solving an equation - // of form X/C1=C2. We solve for X by multiplying C1 (DivRHS) and - // C2 (CI). By solving for X we can turn this into a range check - // instead of computing a divide. - ConstantInt *Prod = Multiply(RHS, DivRHS); - - // Determine if the product overflows by seeing if the product is - // not equal to the divide. Make sure we do the same kind of divide - // as in the LHS instruction that we're folding. - bool ProdOV = (DivIsSigned ? ConstantExpr::getSDiv(Prod, DivRHS) : - ConstantExpr::getUDiv(Prod, DivRHS)) != RHS; - - // Get the ICmp opcode - ICmpInst::Predicate predicate = ICI.getPredicate(); - - if (!DivIsSigned) { // udiv - LoBound = Prod; - LoOverflow = ProdOV; - HiOverflow = ProdOV || - AddWithOverflow(HiBound, LoBound, DivRHS, false); - } else if (DivRHS->getValue().isPositive()) { // Divisor is > 0. - if (RHSV == 0) { // (X / pos) op 0 - // Can't overflow. - LoBound = cast(ConstantExpr::getNeg(SubOne(DivRHS))); - HiBound = DivRHS; - } else if (RHSV.isPositive()) { // (X / pos) op pos - LoBound = Prod; - LoOverflow = ProdOV; - HiOverflow = ProdOV || - AddWithOverflow(HiBound, Prod, DivRHS, true); - } else { // (X / pos) op neg - Constant *DivRHSH = ConstantExpr::getNeg(SubOne(DivRHS)); - LoOverflow = AddWithOverflow(LoBound, Prod, - cast(DivRHSH), true); - HiBound = AddOne(Prod); - HiOverflow = ProdOV; - } - } else { // Divisor is < 0. - if (RHSV == 0) { // (X / neg) op 0 - LoBound = AddOne(DivRHS); - HiBound = cast(ConstantExpr::getNeg(DivRHS)); - if (HiBound == DivRHS) - LoBound = 0; // - INTMIN = INTMIN - } else if (RHSV.isPositive()) { // (X / neg) op pos - HiOverflow = LoOverflow = ProdOV; - if (!LoOverflow) - LoOverflow = AddWithOverflow(LoBound, Prod, AddOne(DivRHS), - true); - HiBound = AddOne(Prod); - } else { // (X / neg) op neg - LoBound = Prod; - LoOverflow = HiOverflow = ProdOV; - HiBound = Subtract(Prod, DivRHS); - } - - // Dividing by a negate swaps the condition. - predicate = ICmpInst::getSwappedPredicate(predicate); - } - - if (LoBound) { - Value *X = LHSI->getOperand(0); - switch (predicate) { - default: assert(0 && "Unhandled icmp opcode!"); - case ICmpInst::ICMP_EQ: - if (LoOverflow && HiOverflow) - return ReplaceInstUsesWith(ICI, ConstantInt::getFalse()); - else if (HiOverflow) - return new ICmpInst(DivIsSigned ? ICmpInst::ICMP_SGE : - ICmpInst::ICMP_UGE, X, LoBound); - else if (LoOverflow) - return new ICmpInst(DivIsSigned ? ICmpInst::ICMP_SLT : - ICmpInst::ICMP_ULT, X, HiBound); - else - return InsertRangeTest(X, LoBound, HiBound, DivIsSigned, - true, ICI); - case ICmpInst::ICMP_NE: - if (LoOverflow && HiOverflow) - return ReplaceInstUsesWith(ICI, ConstantInt::getTrue()); - else if (HiOverflow) - return new ICmpInst(DivIsSigned ? ICmpInst::ICMP_SLT : - ICmpInst::ICMP_ULT, X, LoBound); - else if (LoOverflow) - return new ICmpInst(DivIsSigned ? ICmpInst::ICMP_SGE : - ICmpInst::ICMP_UGE, X, HiBound); - else - return InsertRangeTest(X, LoBound, HiBound, DivIsSigned, - false, ICI); - case ICmpInst::ICMP_ULT: - case ICmpInst::ICMP_SLT: - if (LoOverflow) - return ReplaceInstUsesWith(ICI, ConstantInt::getFalse()); - return new ICmpInst(predicate, X, LoBound); - case ICmpInst::ICMP_UGT: - case ICmpInst::ICMP_SGT: - if (HiOverflow) - return ReplaceInstUsesWith(ICI, ConstantInt::getFalse()); - if (predicate == ICmpInst::ICMP_UGT) - return new ICmpInst(ICmpInst::ICMP_UGE, X, HiBound); - else - return new ICmpInst(ICmpInst::ICMP_SGE, X, HiBound); - } - } - } + if (ConstantInt *DivRHS = dyn_cast(LHSI->getOperand(1))) + if (Instruction *R = FoldICmpDivCst(ICI, cast(LHSI), + DivRHS)) + return R; break; } From resistor at mac.com Wed Jun 20 18:48:24 2007 From: resistor at mac.com (Owen Anderson) Date: Wed, 20 Jun 2007 18:48:24 -0500 Subject: [llvm-commits] CVS: llvm-test/Makefile.programs TEST.nightly.Makefile Message-ID: <200706202348.l5KNmOMC025115@zion.cs.uiuc.edu> Changes in directory llvm-test: Makefile.programs updated: 1.268 -> 1.269 TEST.nightly.Makefile updated: 1.47 -> 1.48 --- Log message: Don't run the optimizations twice when performing a nightly build. Just record the results the first time. --- Diffs of the changes: (+2 -4) Makefile.programs | 2 +- TEST.nightly.Makefile | 4 +--- 2 files changed, 2 insertions(+), 4 deletions(-) Index: llvm-test/Makefile.programs diff -u llvm-test/Makefile.programs:1.268 llvm-test/Makefile.programs:1.269 --- llvm-test/Makefile.programs:1.268 Wed May 30 12:49:53 2007 +++ llvm-test/Makefile.programs Wed Jun 20 18:48:01 2007 @@ -256,7 +256,7 @@ # standard compilation optimizations. $(PROGRAMS_TO_TEST:%=Output/%.linked.bc): \ Output/%.linked.bc: Output/%.linked.rbc $(LOPT) - -$(LOPT) -std-compile-opts $(STATS) $(EXTRA_LOPT_OPTIONS) $< -o $@ -f + -$(LOPT) -std-compile-opts -time-passes -info-output-file=$(CURDIR)/$@.info $(STATS) $(EXTRA_LOPT_OPTIONS) $< -o $@ -f $(PROGRAMS_TO_TEST:%=Output/%.llvm.stripped.bc): \ Output/%.llvm.stripped.bc: Output/%.llvm.bc $(LOPT) Index: llvm-test/TEST.nightly.Makefile diff -u llvm-test/TEST.nightly.Makefile:1.47 llvm-test/TEST.nightly.Makefile:1.48 --- llvm-test/TEST.nightly.Makefile:1.47 Wed Jun 20 13:06:48 2007 +++ llvm-test/TEST.nightly.Makefile Wed Jun 20 18:48:01 2007 @@ -33,9 +33,7 @@ $(PROGRAMS_TO_TEST:%=Output/%.nightly.compile.report.txt): \ Output/%.nightly.compile.report.txt: Output/%.llvm.bc $(LOPT) @echo > $@ - @echo '$(LOPT) -std-compile-opts Output/$*.linked.rbc -f -o /dev/null $(TIMEOPT) $(EXTRA_LOPT_OPTIONS) >>$@ 2>&1' - @-if ($(LOPT) -std-compile-opts Output/$*.linked.rbc -f -o /dev/null $(TIMEOPT) $(EXTRA_LOPT_OPTIONS) >>$@ 2>&1)\ - ;then \ + @-if test -f Output/$@.info; then \ echo "TEST-PASS: compile $(RELDIR)/$*" >> $@;\ printf "TEST-RESULT-compile: " >> $@;\ grep "Total Execution Time" $@.info >> $@;\ From resistor at mac.com Wed Jun 20 19:19:27 2007 From: resistor at mac.com (Owen Anderson) Date: Wed, 20 Jun 2007 19:19:27 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/GVNPRE.cpp Message-ID: <200706210019.l5L0JR0o025767@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: GVNPRE.cpp updated: 1.46 -> 1.47 --- Log message: Comment-ize the functions in GVNPRE. --- Diffs of the changes: (+108 -76) GVNPRE.cpp | 184 +++++++++++++++++++++++++++++++++++-------------------------- 1 files changed, 108 insertions(+), 76 deletions(-) Index: llvm/lib/Transforms/Scalar/GVNPRE.cpp diff -u llvm/lib/Transforms/Scalar/GVNPRE.cpp:1.46 llvm/lib/Transforms/Scalar/GVNPRE.cpp:1.47 --- llvm/lib/Transforms/Scalar/GVNPRE.cpp:1.46 Wed Jun 20 17:10:02 2007 +++ llvm/lib/Transforms/Scalar/GVNPRE.cpp Wed Jun 20 19:19:05 2007 @@ -42,7 +42,9 @@ // ValueTable Class //===----------------------------------------------------------------------===// -/// This class holds the mapping between values and value numbers. +/// This class holds the mapping between values and value numbers. It is used +/// as an efficient mechanism to determine the expression-wise equivalence of +/// two values. namespace { class VISIBILITY_HIDDEN ValueTable { @@ -89,6 +91,8 @@ Expression::ExpressionOpcode getOpcode(BinaryOperator* BO); Expression::ExpressionOpcode getOpcode(CmpInst* C); + Expression create_expression(BinaryOperator* BO); + Expression create_expression(CmpInst* C); public: ValueTable() { nextValueNumber = 1; } uint32_t lookup_or_add(Value* V); @@ -100,14 +104,15 @@ } std::set& getMaximalValues() { return maximalValues; } - Expression create_expression(BinaryOperator* BO); - Expression create_expression(CmpInst* C); void erase(Value* v); }; } +//===----------------------------------------------------------------------===// +// ValueTable Internal Functions +//===----------------------------------------------------------------------===// ValueTable::Expression::ExpressionOpcode - ValueTable::getOpcode(BinaryOperator* BO) { + ValueTable::getOpcode(BinaryOperator* BO) { switch(BO->getOpcode()) { case Instruction::Add: return Expression::ADD; @@ -215,6 +220,36 @@ } } +ValueTable::Expression ValueTable::create_expression(BinaryOperator* BO) { + Expression e; + + e.leftVN = lookup_or_add(BO->getOperand(0)); + e.rightVN = lookup_or_add(BO->getOperand(1)); + e.opcode = getOpcode(BO); + + maximalExpressions.insert(e); + + return e; +} + +ValueTable::Expression ValueTable::create_expression(CmpInst* C) { + Expression e; + + e.leftVN = lookup_or_add(C->getOperand(0)); + e.rightVN = lookup_or_add(C->getOperand(1)); + e.opcode = getOpcode(C); + + maximalExpressions.insert(e); + + return e; +} + +//===----------------------------------------------------------------------===// +// ValueTable External Functions +//===----------------------------------------------------------------------===// + +/// lookup_or_add - Returns the value number for the specified value, assigning +/// it a new number if it did not have one before. uint32_t ValueTable::lookup_or_add(Value* V) { maximalValues.insert(V); @@ -255,6 +290,8 @@ } } +/// lookup - Returns the value number of the specified value. Fails if +/// the value has not yet been numbered. uint32_t ValueTable::lookup(Value* V) { DenseMap::iterator VI = valueNumbering.find(V); if (VI != valueNumbering.end()) @@ -265,6 +302,8 @@ return 0; } +/// add - Add the specified value with the given value number, removing +/// its old number, if any void ValueTable::add(Value* V, uint32_t num) { DenseMap::iterator VI = valueNumbering.find(V); if (VI != valueNumbering.end()) @@ -272,30 +311,7 @@ valueNumbering.insert(std::make_pair(V, num)); } -ValueTable::Expression ValueTable::create_expression(BinaryOperator* BO) { - Expression e; - - e.leftVN = lookup_or_add(BO->getOperand(0)); - e.rightVN = lookup_or_add(BO->getOperand(1)); - e.opcode = getOpcode(BO); - - maximalExpressions.insert(e); - - return e; -} - -ValueTable::Expression ValueTable::create_expression(CmpInst* C) { - Expression e; - - e.leftVN = lookup_or_add(C->getOperand(0)); - e.rightVN = lookup_or_add(C->getOperand(1)); - e.opcode = getOpcode(C); - - maximalExpressions.insert(e); - - return e; -} - +/// clear - Remove all entries from the ValueTable and the maximal sets void ValueTable::clear() { valueNumbering.clear(); expressionNumbering.clear(); @@ -304,6 +320,7 @@ nextValueNumber = 1; } +/// erase - Remove a value from the value numbering and maximal sets void ValueTable::erase(Value* V) { maximalValues.erase(V); valueNumbering.erase(V); @@ -313,6 +330,10 @@ maximalExpressions.erase(create_expression(C)); } +//===----------------------------------------------------------------------===// +// GVNPRE Pass +//===----------------------------------------------------------------------===// + namespace { class VISIBILITY_HIDDEN GVNPRE : public FunctionPass { @@ -328,6 +349,7 @@ std::map > availableOut; std::map > anticipatedIn; + // This transformation requires dominator postdominator info virtual void getAnalysisUsage(AnalysisUsage &AU) const { AU.setPreservesCFG(); AU.addRequired(); @@ -382,6 +404,7 @@ } +// createGVNPREPass - The public interface to this file... FunctionPass *llvm::createGVNPREPass() { return new GVNPRE(); } RegisterPass X("gvnpre", @@ -392,6 +415,9 @@ STATISTIC(NumInsertedPhis, "Number of PHI nodes inserted"); STATISTIC(NumEliminated, "Number of redundant instructions eliminated"); +/// find_leader - Given a set and a value number, return the first +/// element of the set with that value number, or 0 if no such element +/// is present Value* GVNPRE::find_leader(std::set& vals, uint32_t v) { for (std::set::iterator I = vals.begin(), E = vals.end(); I != E; ++I) @@ -401,6 +427,8 @@ return 0; } +/// val_insert - Insert a value into a set only if there is not a value +/// with the same value number already in the set void GVNPRE::val_insert(std::set& s, Value* v) { uint32_t num = VN.lookup(v); Value* leader = find_leader(s, num); @@ -408,6 +436,8 @@ s.insert(v); } +/// val_replace - Insert a value into a set, replacing any values already in +/// the set that have the same value number void GVNPRE::val_replace(std::set& s, Value* v) { uint32_t num = VN.lookup(v); Value* leader = find_leader(s, num); @@ -418,6 +448,10 @@ s.insert(v); } +/// phi_translate - Given a value, its parent block, and a predecessor of its +/// parent, translate the value into legal for the predecessor block. This +/// means translating its operands (and recursively, their operands) through +/// any phi nodes in the parent into values available in the predecessor Value* GVNPRE::phi_translate(Value* V, BasicBlock* pred, BasicBlock* succ) { if (V == 0) return 0; @@ -511,6 +545,7 @@ return V; } +/// phi_translate_set - Perform phi translation on every element of a set void GVNPRE::phi_translate_set(std::set& anticIn, BasicBlock* pred, BasicBlock* succ, std::set& out) { @@ -522,6 +557,9 @@ } } +/// dependsOnInvoke - Test if a value has an phi node as an operand, any of +/// whose inputs is an invoke instruction. If this is true, we cannot safely +/// PRE the instruction or anything that depends on it. bool GVNPRE::dependsOnInvoke(Value* V) { if (PHINode* p = dyn_cast(V)) { for (PHINode::op_iterator I = p->op_begin(), E = p->op_end(); I != E; ++I) @@ -533,7 +571,9 @@ } } -// Remove all expressions whose operands are not themselves in the set +/// clean - Remove all non-opaque values from the set whose operands are not +/// themselves in the set, as well as all values that depend on invokes (see +/// above) void GVNPRE::clean(std::set& set) { std::vector worklist; topo_sort(set, worklist); @@ -595,8 +635,9 @@ } } -void GVNPRE::topo_sort(std::set& set, - std::vector& vec) { +/// topo_sort - Given a set of values, sort them by topological +/// order into the provided vector. +void GVNPRE::topo_sort(std::set& set, std::vector& vec) { std::set toErase; for (std::set::iterator I = set.begin(), E = set.end(); I != E; ++I) { @@ -665,7 +706,7 @@ } } - +/// dump - Dump a set of values to standard error void GVNPRE::dump(const std::set& s) const { DOUT << "{ "; for (std::set::iterator I = s.begin(), E = s.end(); @@ -675,6 +716,9 @@ DOUT << "}\n\n"; } +/// elimination - Phase 3 of the main algorithm. Perform full redundancy +/// elimination by walking the dominator tree and removing any instruction that +/// is dominated by another instruction with the same value number. bool GVNPRE::elimination() { DOUT << "\n\nPhase 3: Elimination\n\n"; @@ -724,7 +768,8 @@ return changed_function; } - +/// cleanup - Delete any extraneous values that were created to represent +/// expressions without leaders. void GVNPRE::cleanup() { while (!createdExpressions.empty()) { Instruction* I = createdExpressions.back(); @@ -734,6 +779,8 @@ } } +/// buildsets_availout - When calculating availability, handle an instruction +/// by inserting it into the appropriate sets void GVNPRE::buildsets_availout(BasicBlock::iterator I, std::set& currAvail, std::set& currPhis, @@ -780,6 +827,8 @@ val_insert(currAvail, I); } +/// buildsets_anticout - When walking the postdom tree, calculate the ANTIC_OUT +/// set as a function of the ANTIC_IN set of the block's predecessors void GVNPRE::buildsets_anticout(BasicBlock* BB, std::set& anticOut, std::set& visited) { @@ -809,6 +858,9 @@ } } +/// buildsets_anticin - Walk the postdom tree, calculating ANTIC_OUT for +/// each block. ANTIC_IN is then a function of ANTIC_OUT and the GEN +/// sets populated in buildsets_availout bool GVNPRE::buildsets_anticin(BasicBlock* BB, std::set& anticOut, std::set& currExps, @@ -853,6 +905,8 @@ return false; } +/// buildsets - Phase 1 of the main algorithm. Construct the AVAIL_OUT +/// and the ANTIC_IN sets. unsigned GVNPRE::buildsets(Function& F) { std::map > generatedExpressions; std::map > generatedPhis; @@ -926,38 +980,15 @@ iterations++; } - DOUT << "Iterations: " << iterations << "\n"; - - for (Function::iterator I = F.begin(), E = F.end(); I != E; ++I) { - DOUT << "Name: " << I->getName().c_str() << "\n"; - - DOUT << "TMP_GEN: "; - dump(generatedTemporaries[I]); - DOUT << "\n"; - - DOUT << "EXP_GEN: "; - dump(generatedExpressions[I]); - DOUT << "\n"; - - DOUT << "ANTIC_IN: "; - dump(anticipatedIn[I]); - DOUT << "\n"; - - DOUT << "AVAIL_OUT: "; - dump(availableOut[I]); - DOUT << "\n"; - } - return 0; // No bail, no changes } +/// insertion_pre - When a partial redundancy has been identified, eliminate it +/// by inserting appropriate values into the predecessors and a phi node in +/// the main block void GVNPRE::insertion_pre(Value* e, BasicBlock* BB, std::map& avail, std::set& new_set) { - DOUT << "Processing Value: "; - DEBUG(e->dump()); - DOUT << "\n\n"; - for (pred_iterator PI = pred_begin(BB), PE = pred_end(BB); PI != PE; ++PI) { Value* e2 = avail[*PI]; if (!find_leader(availableOut[*PI], VN.lookup(e2))) { @@ -991,9 +1022,7 @@ std::set& predAvail = availableOut[*PI]; val_replace(predAvail, newVal); - - DOUT << "Creating value: " << std::hex << newVal << std::dec << "\n"; - + std::map::iterator av = avail.find(*PI); if (av != avail.end()) avail.erase(av); @@ -1013,24 +1042,14 @@ } VN.add(p, VN.lookup(e)); - DOUT << "Creating value: " << std::hex << p << std::dec << "\n"; - val_replace(availableOut[BB], p); - - DOUT << "Preds After Processing: "; - for (pred_iterator PI = pred_begin(BB), PE = pred_end(BB); PI != PE; ++PI) - DEBUG((*PI)->dump()); - DOUT << "\n\n"; - - DOUT << "Merge Block After Processing: "; - DEBUG(BB->dump()); - DOUT << "\n\n"; - new_set.insert(p); ++NumInsertedPhis; } +/// insertion_mergepoint - When walking the dom tree, check at each merge +/// block for the possibility of a partial redundancy. If present, eliminate it unsigned GVNPRE::insertion_mergepoint(std::vector& workList, df_iterator D, std::set& new_set) { @@ -1089,6 +1108,9 @@ return retval; } +/// insert - Phase 2 of the main algorithm. Walk the dominator tree looking for +/// merge points. When one is found, check for a partial redundancy. If one is +/// present, eliminate it. Repeat this walk until no changes are made. bool GVNPRE::insertion(Function& F) { bool changed_function = false; @@ -1143,7 +1165,11 @@ return changed_function; } +// GVNPRE::runOnFunction - This is the main transformation entry point for a +// function. +// bool GVNPRE::runOnFunction(Function &F) { + // Clean out global sets from any previous functions VN.clear(); createdExpressions.clear(); availableOut.clear(); @@ -1152,20 +1178,26 @@ bool changed_function = false; // Phase 1: BuildSets + // This phase calculates the AVAIL_OUT and ANTIC_IN sets + // NOTE: If full postdom information is no available, this will bail + // early, performing GVN but not PRE unsigned bail = buildsets(F); //If a bail occurred, terminate early if (bail != 0) return (bail == 2); // Phase 2: Insert - DOUT<< "\nPhase 2: Insertion\n"; - + // This phase inserts values to make partially redundant values + // fully redundant changed_function |= insertion(F); // Phase 3: Eliminate + // This phase performs trivial full redundancy elimination changed_function |= elimination(); // Phase 4: Cleanup + // This phase cleans up values that were created solely + // as leaders for expressions cleanup(); return changed_function; From evan.cheng at apple.com Wed Jun 20 19:48:02 2007 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 20 Jun 2007 19:48:02 -0500 Subject: [llvm-commits] CVS: llvm-test/MultiSource/Benchmarks/MiBench/consumer-typeset/Makefile Message-ID: <200706210048.l5L0m2TC026394@zion.cs.uiuc.edu> Changes in directory llvm-test/MultiSource/Benchmarks/MiBench/consumer-typeset: Makefile updated: 1.3 -> 1.4 --- Log message: Fix test. --- Diffs of the changes: (+1 -1) Makefile | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm-test/MultiSource/Benchmarks/MiBench/consumer-typeset/Makefile diff -u llvm-test/MultiSource/Benchmarks/MiBench/consumer-typeset/Makefile:1.3 llvm-test/MultiSource/Benchmarks/MiBench/consumer-typeset/Makefile:1.4 --- llvm-test/MultiSource/Benchmarks/MiBench/consumer-typeset/Makefile:1.3 Thu Mar 29 19:56:51 2007 +++ llvm-test/MultiSource/Benchmarks/MiBench/consumer-typeset/Makefile Wed Jun 20 19:47:39 2007 @@ -3,5 +3,5 @@ PROG = consumer-typeset CPPFLAGS = -DOS_UNIX=1 -DOS_DOS=0 -DOS_MAC=0 -DDB_FIX=0 -DUSE_STAT=1 -DSAFE_DFT=0 -DCOLLATE=1 -DLIB_DIR=\"lout.lib\" -DFONT_DIR=\"font\" -DMAPS_DIR=\"maps\" -DINCL_DIR=\"include\" -DDATA_DIR=\"data\" -DHYPH_DIR=\"hyph\" -DLOCALE_DIR=\"locale\" -DCHAR_IN=1 -DCHAR_OUT=0 -DLOCALE_ON=1 -DASSERT_ON=1 -DDEBUG_ON=0 -DPDF_COMPRESSION=0 LDFLAGS = -lm -RUN_OPTIONS = -I $(PROJ_SRC_DIR)/data/include -D $(PROJ_SRC_DIR)/data/data -F $(PROJ_SRC_DIR)/data/font -C $(PROJ_SRC_DIR)/data/maps -H $(PROJ_SRC_DIR)/data/hyph $(PROJ_SRC_DIR)/large.lout +RUN_OPTIONS = -x -I $(PROJ_SRC_DIR)/data/include -D $(PROJ_SRC_DIR)/data/data -F $(PROJ_SRC_DIR)/data/font -C $(PROJ_SRC_DIR)/data/maps -H $(PROJ_SRC_DIR)/data/hyph $(PROJ_SRC_DIR)/large.lout include $(LEVEL)/MultiSource/Makefile.multisrc From resistor at mac.com Wed Jun 20 20:59:27 2007 From: resistor at mac.com (Owen Anderson) Date: Wed, 20 Jun 2007 20:59:27 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/GVNPRE.cpp Message-ID: <200706210159.l5L1xRia027464@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: GVNPRE.cpp updated: 1.47 -> 1.48 --- Log message: Eliminate a redundant check. This speeds up optimization of 253.perlbmk from 13.5 seconds to 10.9 seconds. --- Diffs of the changes: (+3 -7) GVNPRE.cpp | 10 +++------- 1 files changed, 3 insertions(+), 7 deletions(-) Index: llvm/lib/Transforms/Scalar/GVNPRE.cpp diff -u llvm/lib/Transforms/Scalar/GVNPRE.cpp:1.47 llvm/lib/Transforms/Scalar/GVNPRE.cpp:1.48 --- llvm/lib/Transforms/Scalar/GVNPRE.cpp:1.47 Wed Jun 20 19:19:05 2007 +++ llvm/lib/Transforms/Scalar/GVNPRE.cpp Wed Jun 20 20:59:05 2007 @@ -887,13 +887,9 @@ // However, for opaques, such as constants within PHI nodes, it is // possible that they have not yet received a number. Make sure they do // so now. - uint32_t valNum = 0; - if (isa(*I) || isa(*I)) - valNum = VN.lookup(*I); - else - valNum = VN.lookup_or_add(*I); - if (find_leader(anticIn, valNum) == 0) - val_insert(anticIn, *I); + if (!isa(*I) && !isa(*I)) + VN.lookup_or_add(*I); + val_insert(anticIn, *I); } clean(anticIn); From rspencer at reidspencer.com Wed Jun 20 21:30:01 2007 From: rspencer at reidspencer.com (Reid Spencer) Date: Wed, 20 Jun 2007 22:30:01 -0400 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/GVNPRE.cpp In-Reply-To: <200706210159.l5L1xRia027464@zion.cs.uiuc.edu> References: <200706210159.l5L1xRia027464@zion.cs.uiuc.edu> Message-ID: <4679E2A9.3010603@reidspencer.com> Owen Anderson wrote: >Changes in directory llvm/lib/Transforms/Scalar: > >GVNPRE.cpp updated: 1.47 -> 1.48 >--- >Log message: > >Eliminate a redundant check. This speeds up optimization of 253.perlbmk from 13.5 seconds to 10.9 seconds. > > This is speeding up run time of GVNPRE not run time of 253.perlbmk, right? Reid > >--- >Diffs of the changes: (+3 -7) > > GVNPRE.cpp | 10 +++------- > 1 files changed, 3 insertions(+), 7 deletions(-) > > >Index: llvm/lib/Transforms/Scalar/GVNPRE.cpp >diff -u llvm/lib/Transforms/Scalar/GVNPRE.cpp:1.47 llvm/lib/Transforms/Scalar/GVNPRE.cpp:1.48 >--- llvm/lib/Transforms/Scalar/GVNPRE.cpp:1.47 Wed Jun 20 19:19:05 2007 >+++ llvm/lib/Transforms/Scalar/GVNPRE.cpp Wed Jun 20 20:59:05 2007 >@@ -887,13 +887,9 @@ > // However, for opaques, such as constants within PHI nodes, it is > // possible that they have not yet received a number. Make sure they do > // so now. >- uint32_t valNum = 0; >- if (isa(*I) || isa(*I)) >- valNum = VN.lookup(*I); >- else >- valNum = VN.lookup_or_add(*I); >- if (find_leader(anticIn, valNum) == 0) >- val_insert(anticIn, *I); >+ if (!isa(*I) && !isa(*I)) >+ VN.lookup_or_add(*I); >+ val_insert(anticIn, *I); > } > > clean(anticIn); > > > >_______________________________________________ >llvm-commits mailing list >llvm-commits at cs.uiuc.edu >http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > > From resistor at mac.com Wed Jun 20 23:55:00 2007 From: resistor at mac.com (Owen Anderson) Date: Wed, 20 Jun 2007 23:55:00 -0500 Subject: [llvm-commits] CVS: llvm-test/TEST.nightly.Makefile Message-ID: <200706210455.l5L4t08t030485@zion.cs.uiuc.edu> Changes in directory llvm-test: TEST.nightly.Makefile updated: 1.48 -> 1.49 --- Log message: Try again at getting these patterns right. --- Diffs of the changes: (+2 -2) TEST.nightly.Makefile | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm-test/TEST.nightly.Makefile diff -u llvm-test/TEST.nightly.Makefile:1.48 llvm-test/TEST.nightly.Makefile:1.49 --- llvm-test/TEST.nightly.Makefile:1.48 Wed Jun 20 18:48:01 2007 +++ llvm-test/TEST.nightly.Makefile Wed Jun 20 23:54:38 2007 @@ -33,10 +33,10 @@ $(PROGRAMS_TO_TEST:%=Output/%.nightly.compile.report.txt): \ Output/%.nightly.compile.report.txt: Output/%.llvm.bc $(LOPT) @echo > $@ - @-if test -f Output/$@.info; then \ + @-if test -f Output/$*.linked.bc.info; then \ echo "TEST-PASS: compile $(RELDIR)/$*" >> $@;\ printf "TEST-RESULT-compile: " >> $@;\ - grep "Total Execution Time" $@.info >> $@;\ + grep "Total Execution Time" Output/$*.linked.bc.info >> $@;\ echo >> $@;\ printf "TEST-RESULT-compile: " >> $@;\ wc -c $< >> $@;\ From evan.cheng at apple.com Thu Jun 21 02:39:48 2007 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 21 Jun 2007 02:39:48 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <200706210739.l5L7dmDW010446@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.313 -> 1.314 --- Log message: Xforms: (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) --- Diffs of the changes: (+64 -0) DAGCombiner.cpp | 64 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 64 insertions(+) Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.313 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.314 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.313 Tue Jun 19 09:13:56 2007 +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Jun 21 02:39:16 2007 @@ -801,6 +801,55 @@ return SDOperand(); } +static +SDOperand combineSelectAndUse(SDNode *N, SDOperand Slct, SDOperand OtherOp, + SelectionDAG &DAG) { + MVT::ValueType VT = N->getValueType(0); + unsigned Opc = N->getOpcode(); + bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC; + SDOperand LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1); + SDOperand RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2); + ISD::CondCode CC = ISD::SETCC_INVALID; + if (isSlctCC) + CC = cast(Slct.getOperand(4))->get(); + else { + SDOperand CCOp = Slct.getOperand(0); + if (CCOp.getOpcode() == ISD::SETCC) + CC = cast(CCOp.getOperand(2))->get(); + } + + bool DoXform = false; + bool InvCC = false; + assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) && + "Bad input!"); + if (LHS.getOpcode() == ISD::Constant && + cast(LHS)->isNullValue()) + DoXform = true; + else if (CC != ISD::SETCC_INVALID && + RHS.getOpcode() == ISD::Constant && + cast(RHS)->isNullValue()) { + std::swap(LHS, RHS); + bool isInt = MVT::isInteger(isSlctCC ? Slct.getOperand(0).getValueType() + : Slct.getOperand(0).getOperand(0).getValueType()); + CC = ISD::getSetCCInverse(CC, isInt); + DoXform = true; + InvCC = true; + } + + if (DoXform) { + SDOperand Result = DAG.getNode(Opc, VT, OtherOp, RHS); + if (isSlctCC) + return DAG.getSelectCC(OtherOp, Result, + Slct.getOperand(0), Slct.getOperand(1), CC); + SDOperand CCOp = Slct.getOperand(0); + if (InvCC) + CCOp = DAG.getSetCC(CCOp.getValueType(), CCOp.getOperand(0), + CCOp.getOperand(1), CC); + return DAG.getNode(ISD::SELECT, VT, CCOp, OtherOp, Result); + } + return SDOperand(); +} + SDOperand DAGCombiner::visitADD(SDNode *N) { SDOperand N0 = N->getOperand(0); SDOperand N1 = N->getOperand(1); @@ -869,6 +918,16 @@ if (Result.Val) return Result; } + // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) + if (N0.getOpcode() == ISD::SELECT && N0.Val->hasOneUse()) { + SDOperand Result = combineSelectAndUse(N, N0, N1, DAG); + if (Result.Val) return Result; + } + if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) { + SDOperand Result = combineSelectAndUse(N, N1, N0, DAG); + if (Result.Val) return Result; + } + return SDOperand(); } @@ -960,6 +1019,11 @@ // fold (A+B)-B -> A if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) return N0.getOperand(0); + // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) + if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) { + SDOperand Result = combineSelectAndUse(N, N1, N0, DAG); + if (Result.Val) return Result; + } return SDOperand(); } From evan.cheng at apple.com Thu Jun 21 02:40:23 2007 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 21 Jun 2007 02:40:23 -0500 Subject: [llvm-commits] CVS: llvm/test/CodeGen/ARM/select_xform.ll Message-ID: <200706210740.l5L7eNKd010472@zion.cs.uiuc.edu> Changes in directory llvm/test/CodeGen/ARM: select_xform.ll added (r1.1) --- Log message: New tests. --- Diffs of the changes: (+16 -0) select_xform.ll | 16 ++++++++++++++++ 1 files changed, 16 insertions(+) Index: llvm/test/CodeGen/ARM/select_xform.ll diff -c /dev/null llvm/test/CodeGen/ARM/select_xform.ll:1.1 *** /dev/null Thu Jun 21 02:40:10 2007 --- llvm/test/CodeGen/ARM/select_xform.ll Thu Jun 21 02:40:00 2007 *************** *** 0 **** --- 1,16 ---- + ; RUN: llvm-as < %s | llc -march=arm + ; RUN: llvm-as < %s | llc -march=arm | grep mov | wc -l | grep 2 + + define i32 @t1(i32 %a, i32 %b, i32 %c) { + %tmp1 = icmp sgt i32 %c, 10 + %tmp2 = select i1 %tmp1, i32 0, i32 2147483647 + %tmp3 = add i32 %tmp2, %b + ret i32 %tmp3 + } + + define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d) { + %tmp1 = icmp sgt i32 %c, 10 + %tmp2 = select i1 %tmp1, i32 0, i32 10 + %tmp3 = sub i32 %b, %tmp2 + ret i32 %tmp3 + } From djg at cray.com Thu Jun 21 09:42:44 2007 From: djg at cray.com (Dan Gohman) Date: Thu, 21 Jun 2007 09:42:44 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetLowering.h Message-ID: <200706211442.l5LEgiwL018997@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/Target: TargetLowering.h updated: 1.127 -> 1.128 --- Log message: Rename TargetLowering::getNumElements and friends to TargetLowering::getNumRegisters and similar, to avoid confusion with the actual number of elements for vector types. --- Diffs of the changes: (+4 -4) TargetLowering.h | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) Index: llvm/include/llvm/Target/TargetLowering.h diff -u llvm/include/llvm/Target/TargetLowering.h:1.127 llvm/include/llvm/Target/TargetLowering.h:1.128 --- llvm/include/llvm/Target/TargetLowering.h:1.127 Fri Jun 1 03:25:24 2007 +++ llvm/include/llvm/Target/TargetLowering.h Thu Jun 21 09:42:22 2007 @@ -347,12 +347,12 @@ return VT == MVT::iPTR ? PointerTy : VT; } - /// getNumElements - Return the number of registers that this ValueType will + /// getNumRegisters - Return the number of registers that this ValueType will /// eventually require. This is one for any types promoted to live in larger /// registers, but may be more than one for types (like i64) that are split /// into pieces. - unsigned getNumElements(MVT::ValueType VT) const { - return NumElementsForVT[VT]; + unsigned getNumRegisters(MVT::ValueType VT) const { + return NumRegistersForVT[VT]; } /// hasTargetDAGCombine - If true, the target has custom DAG combine @@ -1035,7 +1035,7 @@ /// RegClassForVT - This indicates the default register class to use for /// each ValueType the target supports natively. TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE]; - unsigned char NumElementsForVT[MVT::LAST_VALUETYPE]; + unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE]; /// TransformToType - For any value types we are promoting or expanding, this /// contains the value type that we are changing to. For Expanded types, this From djg at cray.com Thu Jun 21 09:42:45 2007 From: djg at cray.com (Dan Gohman) Date: Thu, 21 Jun 2007 09:42:45 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp TargetLowering.cpp Message-ID: <200706211442.l5LEgjRM019004@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAGISel.cpp updated: 1.466 -> 1.467 TargetLowering.cpp updated: 1.119 -> 1.120 --- Log message: Rename TargetLowering::getNumElements and friends to TargetLowering::getNumRegisters and similar, to avoid confusion with the actual number of elements for vector types. --- Diffs of the changes: (+19 -19) SelectionDAGISel.cpp | 28 ++++++++++++++-------------- TargetLowering.cpp | 10 +++++----- 2 files changed, 19 insertions(+), 19 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.466 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.467 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.466 Fri Jun 15 17:26:58 2007 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Jun 21 09:42:22 2007 @@ -290,19 +290,19 @@ if (PN->use_empty()) continue; MVT::ValueType VT = TLI.getValueType(PN->getType()); - unsigned NumElements; + unsigned NumRegisters; if (VT != MVT::Vector) - NumElements = TLI.getNumElements(VT); + NumRegisters = TLI.getNumRegisters(VT); else { MVT::ValueType VT1,VT2; - NumElements = + NumRegisters = TLI.getVectorTypeBreakdown(cast(PN->getType()), VT1, VT2); } unsigned PHIReg = ValueMap[PN]; assert(PHIReg && "PHI node does not have an assigned virtual register!"); const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo(); - for (unsigned i = 0; i != NumElements; ++i) + for (unsigned i = 0; i != NumRegisters; ++i) BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i); } } @@ -343,7 +343,7 @@ // The common case is that we will only create one register for this // value. If we have that case, create and return the virtual register. - unsigned NV = TLI.getNumElements(VT); + unsigned NV = TLI.getNumRegisters(VT); if (NV == 1) { // If we are promoting this value, pick the next largest supported type. MVT::ValueType PromotedType = TLI.getTypeToTransformTo(VT); @@ -750,7 +750,7 @@ // Source must be expanded. This input value is actually coming from the // register pair InReg and InReg+1. MVT::ValueType DestVT = TLI.getTypeToExpandTo(VT); - unsigned NumVals = TLI.getNumElements(VT); + unsigned NumVals = TLI.getNumRegisters(VT); N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT); if (NumVals == 1) N = DAG.getNode(ISD::BIT_CONVERT, VT, N); @@ -3185,7 +3185,7 @@ unsigned NumRegs = 1; if (OpInfo.ConstraintVT != MVT::Other) - NumRegs = TLI.getNumElements(OpInfo.ConstraintVT); + NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT); MVT::ValueType RegVT; MVT::ValueType ValueVT = OpInfo.ConstraintVT; @@ -3831,7 +3831,7 @@ // integers. Figure out what the destination type is and how many small // integers it turns into. MVT::ValueType NVT = getTypeToExpandTo(VT); - unsigned NumVals = getNumElements(VT); + unsigned NumVals = getNumRegisters(VT); for (unsigned i = 0; i != NumVals; ++i) { RetVals.push_back(NVT); // if it isn't first piece, alignment must be 1 @@ -4088,7 +4088,7 @@ // integers. Figure out what the source elt type is and how many small // integers it is. MVT::ValueType NVT = getTypeToExpandTo(VT); - unsigned NumVals = getNumElements(VT); + unsigned NumVals = getNumRegisters(VT); for (unsigned i = 0; i != NumVals; ++i) RetTys.push_back(NVT); } else { @@ -4507,7 +4507,7 @@ return DAG.getCopyToReg(getRoot(), Reg, Op); } else { DestVT = TLI.getTypeToExpandTo(SrcVT); - unsigned NumVals = TLI.getNumElements(SrcVT); + unsigned NumVals = TLI.getNumRegisters(SrcVT); if (NumVals == 1) return DAG.getCopyToReg(getRoot(), Reg, DAG.getNode(ISD::BIT_CONVERT, DestVT, Op)); @@ -4695,16 +4695,16 @@ // Remember that this register needs to added to the machine PHI node as // the input for this MBB. MVT::ValueType VT = TLI.getValueType(PN->getType()); - unsigned NumElements; + unsigned NumRegisters; if (VT != MVT::Vector) - NumElements = TLI.getNumElements(VT); + NumRegisters = TLI.getNumRegisters(VT); else { MVT::ValueType VT1,VT2; - NumElements = + NumRegisters = TLI.getVectorTypeBreakdown(cast(PN->getType()), VT1, VT2); } - for (unsigned i = 0, e = NumElements; i != e; ++i) + for (unsigned i = 0, e = NumRegisters; i != e; ++i) PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); } } Index: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp diff -u llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.119 llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.120 --- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.119 Wed May 30 11:30:06 2007 +++ llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp Thu Jun 21 09:42:22 2007 @@ -216,7 +216,7 @@ // Everything defaults to one. for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) - NumElementsForVT[i] = 1; + NumRegistersForVT[i] = 1; // Find the largest integer register class. unsigned LargestIntReg = MVT::i128; @@ -227,12 +227,12 @@ // many registers to represent as the previous ValueType. unsigned ExpandedReg = LargestIntReg; ++LargestIntReg; for (++ExpandedReg; MVT::isInteger((MVT::ValueType)ExpandedReg);++ExpandedReg) - NumElementsForVT[ExpandedReg] = 2*NumElementsForVT[ExpandedReg-1]; + NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; // Inspect all of the ValueType's possible, deciding how to process them. for (unsigned IntReg = MVT::i1; IntReg <= MVT::i128; ++IntReg) // If we are expanding this type, expand it! - if (getNumElements((MVT::ValueType)IntReg) != 1) + if (getNumRegisters((MVT::ValueType)IntReg) != 1) SetValueTypeAction((MVT::ValueType)IntReg, Expand, *this, TransformToType, ValueTypeActions); else if (!isTypeLegal((MVT::ValueType)IntReg)) @@ -250,7 +250,7 @@ if (isTypeLegal(MVT::f64)) TransformToType[MVT::f64] = MVT::f64; else { - NumElementsForVT[MVT::f64] = NumElementsForVT[MVT::i64]; + NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; SetValueTypeAction(MVT::f64, Expand, *this, TransformToType, ValueTypeActions); } @@ -260,7 +260,7 @@ SetValueTypeAction(MVT::f32, Promote, *this, TransformToType, ValueTypeActions); else { - NumElementsForVT[MVT::f32] = NumElementsForVT[MVT::i32]; + NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; SetValueTypeAction(MVT::f32, Expand, *this, TransformToType, ValueTypeActions); } From djg at cray.com Thu Jun 21 09:48:49 2007 From: djg at cray.com (Dan Gohman) Date: Thu, 21 Jun 2007 09:48:49 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp TargetLowering.cpp Message-ID: <200706211448.l5LEmn1l019119@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.498 -> 1.499 TargetLowering.cpp updated: 1.120 -> 1.121 --- Log message: Tidy up ValueType names in comments. --- Diffs of the changes: (+5 -5) LegalizeDAG.cpp | 4 ++-- TargetLowering.cpp | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.498 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.499 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.498 Mon Jun 18 16:28:10 2007 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Jun 21 09:48:26 2007 @@ -5649,8 +5649,8 @@ /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the -/// equivalent operation that returns a scalar (e.g. F32) or packed value -/// (e.g. MVT::V4F32). When this is called, we know that PackedVT is the right +/// equivalent operation that returns a scalar (e.g. MVT::f32) or packed value +/// (e.g. MVT::v4f32). When this is called, we know that PackedVT is the right /// type for the result. SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op, MVT::ValueType NewVT) { Index: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp diff -u llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.120 llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.121 --- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.120 Thu Jun 21 09:42:22 2007 +++ llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp Thu Jun 21 09:48:26 2007 @@ -243,10 +243,10 @@ else TransformToType[(MVT::ValueType)IntReg] = (MVT::ValueType)IntReg; - // If the target does not have native F64 support, expand it to I64. We will + // If the target does not have native f64 support, expand it to i64. We will // be generating soft float library calls. If the target does not have native - // support for F32, promote it to F64 if it is legal. Otherwise, expand it to - // I32. + // support for f32, promote it to f64 if it is legal. Otherwise, expand it to + // i32. if (isTypeLegal(MVT::f64)) TransformToType[MVT::f64] = MVT::f64; else { From duraid at kinoko.c.u-tokyo.ac.jp Thu Jun 21 10:20:46 2007 From: duraid at kinoko.c.u-tokyo.ac.jp (Duraid Madina) Date: Fri, 22 Jun 2007 00:20:46 +0900 Subject: [llvm-commits] New "BigBlock" local register allocator Message-ID: <20070621152046.GA10368@kinoko.c.u-tokyo.ac.jp> Hi all, Attached is a new local register allocator tuned for big basic blocks. It is fast and doesn't use much memory, but it is *slightly* slower and does use more memory than the existing local allocator. Having said that, it quickly gets close-to-optimal allocations on very large basic blocks, and it doesn't give *terrible* results on complex functions, so it might make sense to use this allocator by default in a JIT context. I haven't yet been able to narrow down a case where the existing local allocator produces better code than this one. Anyway, to play with it, just drop it into lib/Codegen, but you'll also need to declare it in: include/CodeGen/Passes.h include/CodeGen/LinkAllCodegenComponents.h and for testing, you might want to edit lib/Codegen/Passes.cpp to make it the default allocator. I've built llvm-gcc in this way, and the results are pretty reasonable. The allocator hasn't choked on anything so far. As you'll quickly notice, the file is basically a copy of RegAllocLocal.cpp. The only bits changed are the bits implementing the new algorithm, which is very simple. It's just: "At every instruction, if you have to spill a register, greedily spill the one whose value isn't going to be read again for the longest amount of time." To do this, two passes over each basic block are performed. The first pass builds a table which lists the times that each virtual register is read. The second pass does the allocation proper, spilling registers according to the "won't be needed longest" rule. The only thing I am not happy about is the "InsnTimes" map, which just maps all (unallocated) instructions in the basic-block to the integers 0,1,2... Surely there is some way I can do without this map? (I guess I just need to thread a "currentTime" value through to chooseReg() and reloadVirtReg()?) I tried this but messed it up, I probably just need more coffee. ;) Seriously though, if anyone can find any problems or suggest any improvements, I'd be really happy to hear them. Well, the only other question I have is: can I check this in as a seperate allocator, or should we "upgrade" the existing local allocator to this one? This allocator will never be as fast, or use as little memory as the "simple" local allocator, and for those reasons alone I'm thinking we may as well keep the existing local allocator. However, compared to linearscan, or almost any other imaginable "heavy duty" allocator, any difference in the efficiency is probably going to be imperceptible. (On my own JIT workload, BigBlock is >30% slower than Local, but even so, it is still <1% of the total codegen time.) OK, enough rambling: please take a look - flames welcome!! Duraid -------------- next part -------------- A non-text attachment was scrubbed... Name: RegAllocBigBlock.cpp Type: text/x-c++src Size: 34156 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20070622/d721f803/attachment.bin From dpatel at apple.com Thu Jun 21 12:24:08 2007 From: dpatel at apple.com (Devang Patel) Date: Thu, 21 Jun 2007 12:24:08 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Analysis/Dominators.h Message-ID: <200706211724.l5LHO8xL022175@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/Analysis: Dominators.h updated: 1.105 -> 1.106 --- Log message: Move code to update dominator information after basic block is split from LoopSimplify.cpp to Dominator.cpp --- Diffs of the changes: (+10 -0) Dominators.h | 10 ++++++++++ 1 files changed, 10 insertions(+) Index: llvm/include/llvm/Analysis/Dominators.h diff -u llvm/include/llvm/Analysis/Dominators.h:1.105 llvm/include/llvm/Analysis/Dominators.h:1.106 --- llvm/include/llvm/Analysis/Dominators.h:1.105 Tue Jun 12 12:30:56 2007 +++ llvm/include/llvm/Analysis/Dominators.h Thu Jun 21 12:23:45 2007 @@ -302,6 +302,11 @@ virtual void getAnalysisUsage(AnalysisUsage &AU) const { AU.setPreservesAll(); } + + /// splitBlock + /// BB is split and now it has one successor. Update dominator tree to + /// reflect this change. + void splitBlock(BasicBlock *BB); private: void calculate(Function& F); DomTreeNode *getNodeForBlock(BasicBlock *BB); @@ -587,6 +592,11 @@ AU.addRequired(); } + /// splitBlock + /// BB is split and now it has one successor. Update dominace frontier to + /// reflect this change. + void splitBlock(BasicBlock *BB); + private: const DomSetType &calculate(const DominatorTree &DT, const DomTreeNode *Node); From dpatel at apple.com Thu Jun 21 12:24:14 2007 From: dpatel at apple.com (Devang Patel) Date: Thu, 21 Jun 2007 12:24:14 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Utils/CodeExtractor.cpp LoopSimplify.cpp Message-ID: <200706211724.l5LHOElg022184@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Utils: CodeExtractor.cpp updated: 1.57 -> 1.58 LoopSimplify.cpp updated: 1.104 -> 1.105 --- Log message: Move code to update dominator information after basic block is split from LoopSimplify.cpp to Dominator.cpp --- Diffs of the changes: (+22 -202) CodeExtractor.cpp | 15 --- LoopSimplify.cpp | 209 +++++------------------------------------------------- 2 files changed, 22 insertions(+), 202 deletions(-) Index: llvm/lib/Transforms/Utils/CodeExtractor.cpp diff -u llvm/lib/Transforms/Utils/CodeExtractor.cpp:1.57 llvm/lib/Transforms/Utils/CodeExtractor.cpp:1.58 --- llvm/lib/Transforms/Utils/CodeExtractor.cpp:1.57 Thu Jun 7 17:17:16 2007 +++ llvm/lib/Transforms/Utils/CodeExtractor.cpp Thu Jun 21 12:23:45 2007 @@ -140,19 +140,8 @@ // Okay, update dominator sets. The blocks that dominate the new one are the // blocks that dominate TIBB plus the new block itself. - if (DT) { - DomTreeNode *OPNode = DT->getNode(OldPred); - DomTreeNode *IDomNode = OPNode->getIDom(); - BasicBlock* idom = IDomNode->getBlock(); - DT->addNewBlock(NewBB, idom); - - // Additionally, NewBB replaces OldPred as the immediate dominator of blocks - Function *F = Header->getParent(); - for (Function::iterator I = F->begin(), E = F->end(); I != E; ++I) - if (DT->getIDomBlock(I) == OldPred) { - DT->changeImmediateDominator(I, NewBB); - } - } + if (DT) + DT->splitBlock(NewBB); // Okay, now we need to adjust the PHI nodes and any branches from within the // region to go to the new header block instead of the old header block. Index: llvm/lib/Transforms/Utils/LoopSimplify.cpp diff -u llvm/lib/Transforms/Utils/LoopSimplify.cpp:1.104 llvm/lib/Transforms/Utils/LoopSimplify.cpp:1.105 --- llvm/lib/Transforms/Utils/LoopSimplify.cpp:1.104 Mon Jun 11 18:31:22 2007 +++ llvm/lib/Transforms/Utils/LoopSimplify.cpp Thu Jun 21 12:23:45 2007 @@ -61,7 +61,7 @@ // this is null. AliasAnalysis *AA; LoopInfo *LI; - + DominatorTree *DT; virtual bool runOnFunction(Function &F); virtual void getAnalysisUsage(AnalysisUsage &AU) const { @@ -85,9 +85,6 @@ void PlaceSplitBlockCarefully(BasicBlock *NewBB, std::vector &SplitPreds, Loop *L); - - void UpdateDomInfoForRevectoredPreds(BasicBlock *NewBB, - std::vector &PredBlocks); }; char LoopSimplify::ID = 0; @@ -106,6 +103,7 @@ bool Changed = false; LI = &getAnalysis(); AA = getAnalysisToUpdate(); + DT = &getAnalysis(); // Check to see that no blocks (other than the header) in loops have // predecessors that are not in loops. This is not valid for natural loops, @@ -341,6 +339,7 @@ PN->addIncoming(Constant::getNullValue(PN->getType()), NewBB); } } + return NewBB; } @@ -371,8 +370,10 @@ if (Loop *Parent = L->getParentLoop()) Parent->addBasicBlockToLoop(NewBB, *LI); - UpdateDomInfoForRevectoredPreds(NewBB, OutsideBlocks); - + DT->splitBlock(NewBB); + if (DominanceFrontier *DF = getAnalysisToUpdate()) + DF->splitBlock(NewBB); + // Make sure that NewBB is put someplace intelligent, which doesn't mess up // code layout too horribly. PlaceSplitBlockCarefully(NewBB, OutsideBlocks, L); @@ -401,8 +402,11 @@ if (SuccLoop) SuccLoop->addBasicBlockToLoop(NewBB, *LI); - // Update dominator information (set, immdom, domtree, and domfrontier) - UpdateDomInfoForRevectoredPreds(NewBB, LoopBlocks); + // Update Dominator Information + DT->splitBlock(NewBB); + if (DominanceFrontier *DF = getAnalysisToUpdate()) + DF->splitBlock(NewBB); + return NewBB; } @@ -507,7 +511,6 @@ /// created. /// Loop *LoopSimplify::SeparateNestedLoop(Loop *L) { - DominatorTree *DT = getAnalysisToUpdate(); PHINode *PN = FindPHIToPartitionLoops(L, DT, AA); if (PN == 0) return 0; // No known way to partition. @@ -523,8 +526,10 @@ BasicBlock *Header = L->getHeader(); BasicBlock *NewBB = SplitBlockPredecessors(Header, ".outer", OuterLoopPreds); - // Update dominator information (set, immdom, domtree, and domfrontier) - UpdateDomInfoForRevectoredPreds(NewBB, OuterLoopPreds); + // Update dominator information + DT->splitBlock(NewBB); + if (DominanceFrontier *DF = getAnalysisToUpdate()) + DF->splitBlock(NewBB); // Make sure that NewBB is put someplace intelligent, which doesn't mess up // code layout too horribly. @@ -677,184 +682,10 @@ // loop and all parent loops. L->addBasicBlockToLoop(BEBlock, *LI); - // Update dominator information (set, immdom, domtree, and domfrontier) - UpdateDomInfoForRevectoredPreds(BEBlock, BackedgeBlocks); -} - -// Returns true if BasicBlock A dominates at least one block in vector B -// Helper function for UpdateDomInfoForRevectoredPreds -static bool BlockDominatesAny(BasicBlock* A, const std::vector& B, - DominatorTree &DT) { - for (std::vector::const_iterator BI = B.begin(), BE = B.end(); - BI != BE; ++BI) { - if (DT.dominates(A, *BI)) - return true; - } - return false; -} - -/// UpdateDomInfoForRevectoredPreds - This method is used to update -/// dominator trees and dominance frontiers after a new block has -/// been added to the CFG. -/// -/// This only supports the case when an existing block (known as "NewBBSucc"), -/// had some of its predecessors factored into a new basic block. This -/// transformation inserts a new basic block ("NewBB"), with a single -/// unconditional branch to NewBBSucc, and moves some predecessors of -/// "NewBBSucc" to now branch to NewBB. These predecessors are listed in -/// PredBlocks, even though they are the same as -/// pred_begin(NewBB)/pred_end(NewBB). -/// -void LoopSimplify::UpdateDomInfoForRevectoredPreds(BasicBlock *NewBB, - std::vector &PredBlocks) { - assert(!PredBlocks.empty() && "No predblocks??"); - assert(NewBB->getTerminator()->getNumSuccessors() == 1 - && "NewBB should have a single successor!"); - BasicBlock *NewBBSucc = NewBB->getTerminator()->getSuccessor(0); - DominatorTree &DT = getAnalysis(); - - // The newly inserted basic block will dominate existing basic blocks iff the - // PredBlocks dominate all of the non-pred blocks. If all predblocks dominate - // the non-pred blocks, then they all must be the same block! - // - bool NewBBDominatesNewBBSucc = true; - { - BasicBlock *OnePred = PredBlocks[0]; - unsigned i = 1, e = PredBlocks.size(); - for (i = 1; !DT.isReachableFromEntry(OnePred); ++i) { - assert(i != e && "Didn't find reachable pred?"); - OnePred = PredBlocks[i]; - } - - for (; i != e; ++i) - if (PredBlocks[i] != OnePred && DT.isReachableFromEntry(OnePred)){ - NewBBDominatesNewBBSucc = false; - break; - } - - if (NewBBDominatesNewBBSucc) - for (pred_iterator PI = pred_begin(NewBBSucc), E = pred_end(NewBBSucc); - PI != E; ++PI) - if (*PI != NewBB && !DT.dominates(NewBBSucc, *PI)) { - NewBBDominatesNewBBSucc = false; - break; - } - } - - // The other scenario where the new block can dominate its successors are when - // all predecessors of NewBBSucc that are not NewBB are dominated by NewBBSucc - // already. - if (!NewBBDominatesNewBBSucc) { - NewBBDominatesNewBBSucc = true; - for (pred_iterator PI = pred_begin(NewBBSucc), E = pred_end(NewBBSucc); - PI != E; ++PI) - if (*PI != NewBB && !DT.dominates(NewBBSucc, *PI)) { - NewBBDominatesNewBBSucc = false; - break; - } - } - - - // Update DominatorTree information if it is active. - - // Find NewBB's immediate dominator and create new dominator tree node for NewBB. - BasicBlock *NewBBIDom = 0; - unsigned i = 0; - for (i = 0; i < PredBlocks.size(); ++i) - if (DT.isReachableFromEntry(PredBlocks[i])) { - NewBBIDom = PredBlocks[i]; - break; - } - assert(i != PredBlocks.size() && "No reachable preds?"); - for (i = i + 1; i < PredBlocks.size(); ++i) { - if (DT.isReachableFromEntry(PredBlocks[i])) - NewBBIDom = DT.findNearestCommonDominator(NewBBIDom, PredBlocks[i]); - } - assert(NewBBIDom && "No immediate dominator found??"); - - // Create the new dominator tree node... and set the idom of NewBB. - DomTreeNode *NewBBNode = DT.addNewBlock(NewBB, NewBBIDom); - - // If NewBB strictly dominates other blocks, then it is now the immediate - // dominator of NewBBSucc. Update the dominator tree as appropriate. - if (NewBBDominatesNewBBSucc) { - DomTreeNode *NewBBSuccNode = DT.getNode(NewBBSucc); - DT.changeImmediateDominator(NewBBSuccNode, NewBBNode); - } - - // Update dominance frontier information... - if (DominanceFrontier *DF = getAnalysisToUpdate()) { - // If NewBB dominates NewBBSucc, then DF(NewBB) is now going to be the - // DF(PredBlocks[0]) without the stuff that the new block does not dominate - // a predecessor of. - if (NewBBDominatesNewBBSucc) { - DominanceFrontier::iterator DFI = DF->find(PredBlocks[0]); - if (DFI != DF->end()) { - DominanceFrontier::DomSetType Set = DFI->second; - // Filter out stuff in Set that we do not dominate a predecessor of. - for (DominanceFrontier::DomSetType::iterator SetI = Set.begin(), - E = Set.end(); SetI != E;) { - bool DominatesPred = false; - for (pred_iterator PI = pred_begin(*SetI), E = pred_end(*SetI); - PI != E; ++PI) - if (DT.dominates(NewBB, *PI)) - DominatesPred = true; - if (!DominatesPred) - Set.erase(SetI++); - else - ++SetI; - } - - DF->addBasicBlock(NewBB, Set); - } - - } else { - // DF(NewBB) is {NewBBSucc} because NewBB does not strictly dominate - // NewBBSucc, but it does dominate itself (and there is an edge (NewBB -> - // NewBBSucc)). NewBBSucc is the single successor of NewBB. - DominanceFrontier::DomSetType NewDFSet; - NewDFSet.insert(NewBBSucc); - DF->addBasicBlock(NewBB, NewDFSet); - } - - // Now we must loop over all of the dominance frontiers in the function, - // replacing occurrences of NewBBSucc with NewBB in some cases. All - // blocks that dominate a block in PredBlocks and contained NewBBSucc in - // their dominance frontier must be updated to contain NewBB instead. - // - for (Function::iterator FI = NewBB->getParent()->begin(), - FE = NewBB->getParent()->end(); FI != FE; ++FI) { - DominanceFrontier::iterator DFI = DF->find(FI); - if (DFI == DF->end()) continue; // unreachable block. - - // Only consider dominators of NewBBSucc - if (!DFI->second.count(NewBBSucc)) continue; - - if (BlockDominatesAny(FI, PredBlocks, DT)) { - // If NewBBSucc should not stay in our dominator frontier, remove it. - // We remove it unless there is a predecessor of NewBBSucc that we - // dominate, but we don't strictly dominate NewBBSucc. - bool ShouldRemove = true; - if ((BasicBlock*)FI == NewBBSucc - || !DT.dominates(FI, NewBBSucc)) { - // Okay, we know that PredDom does not strictly dominate NewBBSucc. - // Check to see if it dominates any predecessors of NewBBSucc. - for (pred_iterator PI = pred_begin(NewBBSucc), - E = pred_end(NewBBSucc); PI != E; ++PI) - if (DT.dominates(FI, *PI)) { - ShouldRemove = false; - break; - } - - if (ShouldRemove) - DF->removeFromFrontier(DFI, NewBBSucc); - DF->addToFrontier(DFI, NewBB); - - break; - } - } - } - } + // Update dominator information + DT->splitBlock(BEBlock); + if (DominanceFrontier *DF = getAnalysisToUpdate()) + DF->splitBlock(BEBlock); } From dpatel at apple.com Thu Jun 21 12:24:15 2007 From: dpatel at apple.com (Devang Patel) Date: Thu, 21 Jun 2007 12:24:15 -0500 Subject: [llvm-commits] CVS: llvm/lib/VMCore/Dominators.cpp Message-ID: <200706211724.l5LHOFWB022189@zion.cs.uiuc.edu> Changes in directory llvm/lib/VMCore: Dominators.cpp updated: 1.117 -> 1.118 --- Log message: Move code to update dominator information after basic block is split from LoopSimplify.cpp to Dominator.cpp --- Diffs of the changes: (+184 -0) Dominators.cpp | 184 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 184 insertions(+) Index: llvm/lib/VMCore/Dominators.cpp diff -u llvm/lib/VMCore/Dominators.cpp:1.117 llvm/lib/VMCore/Dominators.cpp:1.118 --- llvm/lib/VMCore/Dominators.cpp:1.117 Tue Jun 12 12:50:25 2007 +++ llvm/lib/VMCore/Dominators.cpp Thu Jun 21 12:23:45 2007 @@ -63,6 +63,89 @@ static RegisterPass E("domtree", "Dominator Tree Construction", true); +// NewBB is split and now it has one successor. Update dominator tree to +// reflect this change. +void DominatorTree::splitBlock(BasicBlock *NewBB) { + + assert(NewBB->getTerminator()->getNumSuccessors() == 1 + && "NewBB should have a single successor!"); + BasicBlock *NewBBSucc = NewBB->getTerminator()->getSuccessor(0); + + std::vector PredBlocks; + for (pred_iterator PI = pred_begin(NewBB), PE = pred_end(NewBB); + PI != PE; ++PI) + PredBlocks.push_back(*PI); + + assert(!PredBlocks.empty() && "No predblocks??"); + + // The newly inserted basic block will dominate existing basic blocks iff the + // PredBlocks dominate all of the non-pred blocks. If all predblocks dominate + // the non-pred blocks, then they all must be the same block! + // + bool NewBBDominatesNewBBSucc = true; + { + BasicBlock *OnePred = PredBlocks[0]; + unsigned i = 1, e = PredBlocks.size(); + for (i = 1; !isReachableFromEntry(OnePred); ++i) { + assert(i != e && "Didn't find reachable pred?"); + OnePred = PredBlocks[i]; + } + + for (; i != e; ++i) + if (PredBlocks[i] != OnePred && isReachableFromEntry(OnePred)){ + NewBBDominatesNewBBSucc = false; + break; + } + + if (NewBBDominatesNewBBSucc) + for (pred_iterator PI = pred_begin(NewBBSucc), E = pred_end(NewBBSucc); + PI != E; ++PI) + if (*PI != NewBB && !dominates(NewBBSucc, *PI)) { + NewBBDominatesNewBBSucc = false; + break; + } + } + + // The other scenario where the new block can dominate its successors are when + // all predecessors of NewBBSucc that are not NewBB are dominated by NewBBSucc + // already. + if (!NewBBDominatesNewBBSucc) { + NewBBDominatesNewBBSucc = true; + for (pred_iterator PI = pred_begin(NewBBSucc), E = pred_end(NewBBSucc); + PI != E; ++PI) + if (*PI != NewBB && !dominates(NewBBSucc, *PI)) { + NewBBDominatesNewBBSucc = false; + break; + } + } + + + // Find NewBB's immediate dominator and create new dominator tree node for NewBB. + BasicBlock *NewBBIDom = 0; + unsigned i = 0; + for (i = 0; i < PredBlocks.size(); ++i) + if (isReachableFromEntry(PredBlocks[i])) { + NewBBIDom = PredBlocks[i]; + break; + } + assert(i != PredBlocks.size() && "No reachable preds?"); + for (i = i + 1; i < PredBlocks.size(); ++i) { + if (isReachableFromEntry(PredBlocks[i])) + NewBBIDom = findNearestCommonDominator(NewBBIDom, PredBlocks[i]); + } + assert(NewBBIDom && "No immediate dominator found??"); + + // Create the new dominator tree node... and set the idom of NewBB. + DomTreeNode *NewBBNode = addNewBlock(NewBB, NewBBIDom); + + // If NewBB strictly dominates other blocks, then it is now the immediate + // dominator of NewBBSucc. Update the dominator tree as appropriate. + if (NewBBDominatesNewBBSucc) { + DomTreeNode *NewBBSuccNode = getNode(NewBBSucc); + changeImmediateDominator(NewBBSuccNode, NewBBNode); + } +} + unsigned DominatorTree::DFSPass(BasicBlock *V, InfoRec &VInfo, unsigned N) { // This is more understandable as a recursive algorithm, but we can't use the @@ -520,6 +603,107 @@ static RegisterPass G("domfrontier", "Dominance Frontier Construction", true); +// NewBB is split and now it has one successor. Update dominace frontier to +// reflect this change. +void DominanceFrontier::splitBlock(BasicBlock *NewBB) { + + assert(NewBB->getTerminator()->getNumSuccessors() == 1 + && "NewBB should have a single successor!"); + BasicBlock *NewBBSucc = NewBB->getTerminator()->getSuccessor(0); + + std::vector PredBlocks; + for (pred_iterator PI = pred_begin(NewBB), PE = pred_end(NewBB); + PI != PE; ++PI) + PredBlocks.push_back(*PI); + + assert(!PredBlocks.empty() && "No predblocks??"); + + DominatorTree &DT = getAnalysis(); + bool NewBBDominatesNewBBSucc = true; + if (!DT.dominates(NewBB, NewBBSucc)) + NewBBDominatesNewBBSucc = false; + + // If NewBB dominates NewBBSucc, then DF(NewBB) is now going to be the + // DF(PredBlocks[0]) without the stuff that the new block does not dominate + // a predecessor of. + if (NewBBDominatesNewBBSucc) { + DominanceFrontier::iterator DFI = find(PredBlocks[0]); + if (DFI != end()) { + DominanceFrontier::DomSetType Set = DFI->second; + // Filter out stuff in Set that we do not dominate a predecessor of. + for (DominanceFrontier::DomSetType::iterator SetI = Set.begin(), + E = Set.end(); SetI != E;) { + bool DominatesPred = false; + for (pred_iterator PI = pred_begin(*SetI), E = pred_end(*SetI); + PI != E; ++PI) + if (DT.dominates(NewBB, *PI)) + DominatesPred = true; + if (!DominatesPred) + Set.erase(SetI++); + else + ++SetI; + } + + addBasicBlock(NewBB, Set); + } + + } else { + // DF(NewBB) is {NewBBSucc} because NewBB does not strictly dominate + // NewBBSucc, but it does dominate itself (and there is an edge (NewBB -> + // NewBBSucc)). NewBBSucc is the single successor of NewBB. + DominanceFrontier::DomSetType NewDFSet; + NewDFSet.insert(NewBBSucc); + addBasicBlock(NewBB, NewDFSet); + } + + // Now we must loop over all of the dominance frontiers in the function, + // replacing occurrences of NewBBSucc with NewBB in some cases. All + // blocks that dominate a block in PredBlocks and contained NewBBSucc in + // their dominance frontier must be updated to contain NewBB instead. + // + for (Function::iterator FI = NewBB->getParent()->begin(), + FE = NewBB->getParent()->end(); FI != FE; ++FI) { + DominanceFrontier::iterator DFI = find(FI); + if (DFI == end()) continue; // unreachable block. + + // Only consider dominators of NewBBSucc + if (!DFI->second.count(NewBBSucc)) continue; + + bool BlockDominatesAny = false; + for (std::vector::const_iterator BI = PredBlocks.begin(), + BE = PredBlocks.end(); BI != BE; ++BI) { + if (DT.dominates(FI, *BI)) { + BlockDominatesAny = true; + break; + } + } + + if (BlockDominatesAny) { + // If NewBBSucc should not stay in our dominator frontier, remove it. + // We remove it unless there is a predecessor of NewBBSucc that we + // dominate, but we don't strictly dominate NewBBSucc. + bool ShouldRemove = true; + if ((BasicBlock*)FI == NewBBSucc + || !DT.dominates(FI, NewBBSucc)) { + // Okay, we know that PredDom does not strictly dominate NewBBSucc. + // Check to see if it dominates any predecessors of NewBBSucc. + for (pred_iterator PI = pred_begin(NewBBSucc), + E = pred_end(NewBBSucc); PI != E; ++PI) + if (DT.dominates(FI, *PI)) { + ShouldRemove = false; + break; + } + + if (ShouldRemove) + removeFromFrontier(DFI, NewBBSucc); + addToFrontier(DFI, NewBB); + + break; + } + } + } +} + namespace { class DFCalculateWorkObject { public: From resistor at mac.com Thu Jun 21 12:58:15 2007 From: resistor at mac.com (Owen Anderson) Date: Thu, 21 Jun 2007 12:58:15 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/GVNPRE.cpp Message-ID: <200706211758.l5LHwF3O022797@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: GVNPRE.cpp updated: 1.48 -> 1.49 --- Log message: Change lots of sets from std::set to SmallPtrSet. This reduces the time required to optimize 253.perlbmk from 10.9s to 5.3s. --- Diffs of the changes: (+99 -92) GVNPRE.cpp | 191 +++++++++++++++++++++++++++++++------------------------------ 1 files changed, 99 insertions(+), 92 deletions(-) Index: llvm/lib/Transforms/Scalar/GVNPRE.cpp diff -u llvm/lib/Transforms/Scalar/GVNPRE.cpp:1.48 llvm/lib/Transforms/Scalar/GVNPRE.cpp:1.49 --- llvm/lib/Transforms/Scalar/GVNPRE.cpp:1.48 Wed Jun 20 20:59:05 2007 +++ llvm/lib/Transforms/Scalar/GVNPRE.cpp Thu Jun 21 12:57:53 2007 @@ -27,6 +27,7 @@ #include "llvm/Analysis/PostDominators.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/DepthFirstIterator.h" +#include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/Statistic.h" #include "llvm/Support/CFG.h" #include "llvm/Support/Compiler.h" @@ -85,7 +86,7 @@ std::map expressionNumbering; std::set maximalExpressions; - std::set maximalValues; + SmallPtrSet maximalValues; uint32_t nextValueNumber; @@ -103,7 +104,7 @@ return maximalExpressions; } - std::set& getMaximalValues() { return maximalValues; } + SmallPtrSet& getMaximalValues() { return maximalValues; } void erase(Value* v); }; } @@ -346,8 +347,8 @@ ValueTable VN; std::vector createdExpressions; - std::map > availableOut; - std::map > anticipatedIn; + std::map > availableOut; + std::map > anticipatedIn; // This transformation requires dominator postdominator info virtual void getAnalysisUsage(AnalysisUsage &AU) const { @@ -358,44 +359,44 @@ // Helper fuctions // FIXME: eliminate or document these better - void dump(const std::set& s) const; - void clean(std::set& set); - Value* find_leader(std::set& vals, + void dump(const SmallPtrSet& s) const; + void clean(SmallPtrSet& set); + Value* find_leader(SmallPtrSet& vals, uint32_t v); Value* phi_translate(Value* V, BasicBlock* pred, BasicBlock* succ); - void phi_translate_set(std::set& anticIn, BasicBlock* pred, - BasicBlock* succ, std::set& out); + void phi_translate_set(SmallPtrSet& anticIn, BasicBlock* pred, + BasicBlock* succ, SmallPtrSet& out); - void topo_sort(std::set& set, + void topo_sort(SmallPtrSet& set, std::vector& vec); void cleanup(); bool elimination(); - void val_insert(std::set& s, Value* v); - void val_replace(std::set& s, Value* v); + void val_insert(SmallPtrSet& s, Value* v); + void val_replace(SmallPtrSet& s, Value* v); bool dependsOnInvoke(Value* V); void buildsets_availout(BasicBlock::iterator I, - std::set& currAvail, - std::set& currPhis, - std::set& currExps, - std::set& currTemps); + SmallPtrSet& currAvail, + SmallPtrSet& currPhis, + SmallPtrSet& currExps, + SmallPtrSet& currTemps); void buildsets_anticout(BasicBlock* BB, - std::set& anticOut, + SmallPtrSet& anticOut, std::set& visited); bool buildsets_anticin(BasicBlock* BB, - std::set& anticOut, - std::set& currExps, - std::set& currTemps, + SmallPtrSet& anticOut, + SmallPtrSet& currExps, + SmallPtrSet& currTemps, std::set& visited); unsigned buildsets(Function& F); void insertion_pre(Value* e, BasicBlock* BB, std::map& avail, - std::set& new_set); + SmallPtrSet& new_set); unsigned insertion_mergepoint(std::vector& workList, df_iterator D, - std::set& new_set); + SmallPtrSet& new_set); bool insertion(Function& F); }; @@ -418,8 +419,8 @@ /// find_leader - Given a set and a value number, return the first /// element of the set with that value number, or 0 if no such element /// is present -Value* GVNPRE::find_leader(std::set& vals, uint32_t v) { - for (std::set::iterator I = vals.begin(), E = vals.end(); +Value* GVNPRE::find_leader(SmallPtrSet& vals, uint32_t v) { + for (SmallPtrSet::iterator I = vals.begin(), E = vals.end(); I != E; ++I) if (v == VN.lookup(*I)) return *I; @@ -429,7 +430,7 @@ /// val_insert - Insert a value into a set only if there is not a value /// with the same value number already in the set -void GVNPRE::val_insert(std::set& s, Value* v) { +void GVNPRE::val_insert(SmallPtrSet& s, Value* v) { uint32_t num = VN.lookup(v); Value* leader = find_leader(s, num); if (leader == 0) @@ -438,7 +439,7 @@ /// val_replace - Insert a value into a set, replacing any values already in /// the set that have the same value number -void GVNPRE::val_replace(std::set& s, Value* v) { +void GVNPRE::val_replace(SmallPtrSet& s, Value* v) { uint32_t num = VN.lookup(v); Value* leader = find_leader(s, num); while (leader != 0) { @@ -546,10 +547,10 @@ } /// phi_translate_set - Perform phi translation on every element of a set -void GVNPRE::phi_translate_set(std::set& anticIn, +void GVNPRE::phi_translate_set(SmallPtrSet& anticIn, BasicBlock* pred, BasicBlock* succ, - std::set& out) { - for (std::set::iterator I = anticIn.begin(), + SmallPtrSet& out) { + for (SmallPtrSet::iterator I = anticIn.begin(), E = anticIn.end(); I != E; ++I) { Value* V = phi_translate(*I, pred, succ); if (V != 0) @@ -574,7 +575,7 @@ /// clean - Remove all non-opaque values from the set whose operands are not /// themselves in the set, as well as all values that depend on invokes (see /// above) -void GVNPRE::clean(std::set& set) { +void GVNPRE::clean(SmallPtrSet& set) { std::vector worklist; topo_sort(set, worklist); @@ -584,7 +585,7 @@ if (BinaryOperator* BO = dyn_cast(v)) { bool lhsValid = !isa(BO->getOperand(0)); if (!lhsValid) - for (std::set::iterator I = set.begin(), E = set.end(); + for (SmallPtrSet::iterator I = set.begin(), E = set.end(); I != E; ++I) if (VN.lookup(*I) == VN.lookup(BO->getOperand(0))) { lhsValid = true; @@ -595,7 +596,7 @@ bool rhsValid = !isa(BO->getOperand(1)); if (!rhsValid) - for (std::set::iterator I = set.begin(), E = set.end(); + for (SmallPtrSet::iterator I = set.begin(), E = set.end(); I != E; ++I) if (VN.lookup(*I) == VN.lookup(BO->getOperand(1))) { rhsValid = true; @@ -609,7 +610,7 @@ } else if (CmpInst* C = dyn_cast(v)) { bool lhsValid = !isa(C->getOperand(0)); if (!lhsValid) - for (std::set::iterator I = set.begin(), E = set.end(); + for (SmallPtrSet::iterator I = set.begin(), E = set.end(); I != E; ++I) if (VN.lookup(*I) == VN.lookup(C->getOperand(0))) { lhsValid = true; @@ -620,7 +621,7 @@ bool rhsValid = !isa(C->getOperand(1)); if (!rhsValid) - for (std::set::iterator I = set.begin(), E = set.end(); + for (SmallPtrSet::iterator I = set.begin(), E = set.end(); I != E; ++I) if (VN.lookup(*I) == VN.lookup(C->getOperand(1))) { rhsValid = true; @@ -637,19 +638,19 @@ /// topo_sort - Given a set of values, sort them by topological /// order into the provided vector. -void GVNPRE::topo_sort(std::set& set, std::vector& vec) { - std::set toErase; - for (std::set::iterator I = set.begin(), E = set.end(); +void GVNPRE::topo_sort(SmallPtrSet& set, std::vector& vec) { + SmallPtrSet toErase; + for (SmallPtrSet::iterator I = set.begin(), E = set.end(); I != E; ++I) { if (BinaryOperator* BO = dyn_cast(*I)) - for (std::set::iterator SI = set.begin(); SI != E; ++SI) { + for (SmallPtrSet::iterator SI = set.begin(); SI != E; ++SI) { if (VN.lookup(BO->getOperand(0)) == VN.lookup(*SI) || VN.lookup(BO->getOperand(1)) == VN.lookup(*SI)) { toErase.insert(*SI); } } else if (CmpInst* C = dyn_cast(*I)) - for (std::set::iterator SI = set.begin(); SI != E; ++SI) { + for (SmallPtrSet::iterator SI = set.begin(); SI != E; ++SI) { if (VN.lookup(C->getOperand(0)) == VN.lookup(*SI) || VN.lookup(C->getOperand(1)) == VN.lookup(*SI)) { toErase.insert(*SI); @@ -658,13 +659,13 @@ } std::vector Q; - for (std::set::iterator I = set.begin(), E = set.end(); + for (SmallPtrSet::iterator I = set.begin(), E = set.end(); I != E; ++I) { - if (toErase.find(*I) == toErase.end()) + if (toErase.count(*I) == 0) Q.push_back(*I); } - std::set visited; + SmallPtrSet visited; while (!Q.empty()) { Value* e = Q.back(); @@ -673,10 +674,10 @@ Value* r = find_leader(set, VN.lookup(BO->getOperand(1))); if (l != 0 && isa(l) && - visited.find(l) == visited.end()) + visited.count(l) == 0) Q.push_back(l); else if (r != 0 && isa(r) && - visited.find(r) == visited.end()) + visited.count(r) == 0) Q.push_back(r); else { vec.push_back(e); @@ -688,10 +689,10 @@ Value* r = find_leader(set, VN.lookup(C->getOperand(1))); if (l != 0 && isa(l) && - visited.find(l) == visited.end()) + visited.count(l) == 0) Q.push_back(l); else if (r != 0 && isa(r) && - visited.find(r) == visited.end()) + visited.count(r) == 0) Q.push_back(r); else { vec.push_back(e); @@ -707,9 +708,9 @@ } /// dump - Dump a set of values to standard error -void GVNPRE::dump(const std::set& s) const { +void GVNPRE::dump(const SmallPtrSet& s) const { DOUT << "{ "; - for (std::set::iterator I = s.begin(), E = s.end(); + for (SmallPtrSet::iterator I = s.begin(), E = s.end(); I != E; ++I) { DEBUG((*I)->dump()); } @@ -782,10 +783,10 @@ /// buildsets_availout - When calculating availability, handle an instruction /// by inserting it into the appropriate sets void GVNPRE::buildsets_availout(BasicBlock::iterator I, - std::set& currAvail, - std::set& currPhis, - std::set& currExps, - std::set& currTemps) { + SmallPtrSet& currAvail, + SmallPtrSet& currPhis, + SmallPtrSet& currExps, + SmallPtrSet& currTemps) { // Handle PHI nodes... if (PHINode* p = dyn_cast(I)) { VN.lookup_or_add(p); @@ -830,7 +831,7 @@ /// buildsets_anticout - When walking the postdom tree, calculate the ANTIC_OUT /// set as a function of the ANTIC_IN set of the block's predecessors void GVNPRE::buildsets_anticout(BasicBlock* BB, - std::set& anticOut, + SmallPtrSet& anticOut, std::set& visited) { if (BB->getTerminator()->getNumSuccessors() == 1) { if (visited.find(BB->getTerminator()->getSuccessor(0)) == visited.end()) @@ -845,15 +846,18 @@ for (unsigned i = 1; i < BB->getTerminator()->getNumSuccessors(); ++i) { BasicBlock* currSucc = BB->getTerminator()->getSuccessor(i); - std::set& succAnticIn = anticipatedIn[currSucc]; + SmallPtrSet& succAnticIn = anticipatedIn[currSucc]; - std::set temp; - std::insert_iterator > temp_ins(temp, temp.begin()); - std::set_intersection(anticOut.begin(), anticOut.end(), - succAnticIn.begin(), succAnticIn.end(), temp_ins); - - anticOut.clear(); - anticOut.insert(temp.begin(), temp.end()); + std::vector temp; + + for (SmallPtrSet::iterator I = anticOut.begin(), + E = anticOut.end(); I != E; ++I) + if (succAnticIn.count(*I) == 0) + temp.push_back(*I); + + for (std::vector::iterator I = temp.begin(), E = temp.end(); + I != E; ++I) + anticOut.erase(*I); } } } @@ -862,26 +866,29 @@ /// each block. ANTIC_IN is then a function of ANTIC_OUT and the GEN /// sets populated in buildsets_availout bool GVNPRE::buildsets_anticin(BasicBlock* BB, - std::set& anticOut, - std::set& currExps, - std::set& currTemps, + SmallPtrSet& anticOut, + SmallPtrSet& currExps, + SmallPtrSet& currTemps, std::set& visited) { - std::set& anticIn = anticipatedIn[BB]; - std::set old (anticIn.begin(), anticIn.end()); + SmallPtrSet& anticIn = anticipatedIn[BB]; + SmallPtrSet old (anticIn.begin(), anticIn.end()); buildsets_anticout(BB, anticOut, visited); - std::set S; - std::insert_iterator > s_ins(S, S.begin()); - std::set_difference(anticOut.begin(), anticOut.end(), - currTemps.begin(), currTemps.end(), s_ins); - + SmallPtrSet S; + for (SmallPtrSet::iterator I = anticOut.begin(), + E = anticOut.end(); I != E; ++I) + if (currTemps.count(*I) == 0) + S.insert(*I); + anticIn.clear(); - std::insert_iterator > ai_ins(anticIn, anticIn.begin()); - std::set_difference(currExps.begin(), currExps.end(), - currTemps.begin(), currTemps.end(), ai_ins); + + for (SmallPtrSet::iterator I = currExps.begin(), + E = currExps.end(); I != E; ++I) + if (currTemps.count(*I) == 0) + anticIn.insert(*I); - for (std::set::iterator I = S.begin(), E = S.end(); + for (SmallPtrSet::iterator I = S.begin(), E = S.end(); I != E; ++I) { // For non-opaque values, we should already have a value numbering. // However, for opaques, such as constants within PHI nodes, it is @@ -904,9 +911,9 @@ /// buildsets - Phase 1 of the main algorithm. Construct the AVAIL_OUT /// and the ANTIC_IN sets. unsigned GVNPRE::buildsets(Function& F) { - std::map > generatedExpressions; - std::map > generatedPhis; - std::map > generatedTemporaries; + std::map > generatedExpressions; + std::map > generatedPhis; + std::map > generatedTemporaries; DominatorTree &DT = getAnalysis(); @@ -917,10 +924,10 @@ E = df_end(DT.getRootNode()); DI != E; ++DI) { // Get the sets to update for this block - std::set& currExps = generatedExpressions[DI->getBlock()]; - std::set& currPhis = generatedPhis[DI->getBlock()]; - std::set& currTemps = generatedTemporaries[DI->getBlock()]; - std::set& currAvail = availableOut[DI->getBlock()]; + SmallPtrSet& currExps = generatedExpressions[DI->getBlock()]; + SmallPtrSet& currPhis = generatedPhis[DI->getBlock()]; + SmallPtrSet& currTemps = generatedTemporaries[DI->getBlock()]; + SmallPtrSet& currAvail = availableOut[DI->getBlock()]; BasicBlock* BB = DI->getBlock(); @@ -957,7 +964,7 @@ unsigned iterations = 0; while (changed) { changed = false; - std::set anticOut; + SmallPtrSet anticOut; // Top-down walk of the postdominator tree for (df_iterator PDI = @@ -984,7 +991,7 @@ /// the main block void GVNPRE::insertion_pre(Value* e, BasicBlock* BB, std::map& avail, - std::set& new_set) { + SmallPtrSet& new_set) { for (pred_iterator PI = pred_begin(BB), PE = pred_end(BB); PI != PE; ++PI) { Value* e2 = avail[*PI]; if (!find_leader(availableOut[*PI], VN.lookup(e2))) { @@ -1016,7 +1023,7 @@ VN.add(newVal, VN.lookup(U)); - std::set& predAvail = availableOut[*PI]; + SmallPtrSet& predAvail = availableOut[*PI]; val_replace(predAvail, newVal); std::map::iterator av = avail.find(*PI); @@ -1048,7 +1055,7 @@ /// block for the possibility of a partial redundancy. If present, eliminate it unsigned GVNPRE::insertion_mergepoint(std::vector& workList, df_iterator D, - std::set& new_set) { + SmallPtrSet& new_set) { bool changed_function = false; bool new_stuff = false; @@ -1112,7 +1119,7 @@ DominatorTree &DT = getAnalysis(); - std::map > new_sets; + std::map > new_sets; bool new_stuff = true; while (new_stuff) { new_stuff = false; @@ -1123,16 +1130,16 @@ if (BB == 0) continue; - std::set& new_set = new_sets[BB]; - std::set& availOut = availableOut[BB]; - std::set& anticIn = anticipatedIn[BB]; + SmallPtrSet& new_set = new_sets[BB]; + SmallPtrSet& availOut = availableOut[BB]; + SmallPtrSet& anticIn = anticipatedIn[BB]; new_set.clear(); // Replace leaders with leaders inherited from dominator if (DI->getIDom() != 0) { - std::set& dom_set = new_sets[DI->getIDom()->getBlock()]; - for (std::set::iterator I = dom_set.begin(), + SmallPtrSet& dom_set = new_sets[DI->getIDom()->getBlock()]; + for (SmallPtrSet::iterator I = dom_set.begin(), E = dom_set.end(); I != E; ++I) { new_set.insert(*I); val_replace(availOut, *I); From sabre at nondot.org Thu Jun 21 13:09:47 2007 From: sabre at nondot.org (Chris Lattner) Date: Thu, 21 Jun 2007 13:09:47 -0500 Subject: [llvm-commits] CVS: llvm/test/Transforms/InstCombine/2007-06-21-DivCompareMiscomp.ll Message-ID: <200706211809.l5LI9lks023109@zion.cs.uiuc.edu> Changes in directory llvm/test/Transforms/InstCombine: 2007-06-21-DivCompareMiscomp.ll added (r1.1) --- Log message: new testcase miscompiled by instcombine, reduced from perl --- Diffs of the changes: (+9 -0) 2007-06-21-DivCompareMiscomp.ll | 9 +++++++++ 1 files changed, 9 insertions(+) Index: llvm/test/Transforms/InstCombine/2007-06-21-DivCompareMiscomp.ll diff -c /dev/null llvm/test/Transforms/InstCombine/2007-06-21-DivCompareMiscomp.ll:1.1 *** /dev/null Thu Jun 21 13:09:35 2007 --- llvm/test/Transforms/InstCombine/2007-06-21-DivCompareMiscomp.ll Thu Jun 21 13:09:25 2007 *************** *** 0 **** --- 1,9 ---- + ; RUN: llvm-as < %s | opt -instcombine | llvm-dis | grep {ret i1 true} + ; rdar://5278853 + + define i1 @test(i32 %tmp468) { + %tmp470 = udiv i32 %tmp468, 4 ; [#uses=2] + %tmp475 = icmp ult i32 %tmp470, 1073741824 ; [#uses=1] + ret i1 %tmp475 + } + From sabre at nondot.org Thu Jun 21 13:11:42 2007 From: sabre at nondot.org (Chris Lattner) Date: Thu, 21 Jun 2007 13:11:42 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp Message-ID: <200706211811.l5LIBgQG023159@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: InstructionCombining.cpp updated: 1.774 -> 1.775 --- Log message: Significantly improve the documentation of the instcombine divide/compare transformation. Also, keep track of which end of the integer interval overflows occur on. This fixes Transforms/InstCombine/2007-06-21-DivCompareMiscomp.ll and rdar://5278853, a miscompilation of perl. --- Diffs of the changes: (+50 -34) InstructionCombining.cpp | 84 +++++++++++++++++++++++++++-------------------- 1 files changed, 50 insertions(+), 34 deletions(-) Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.774 llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.775 --- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.774 Wed Jun 20 18:46:26 2007 +++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Thu Jun 21 13:11:19 2007 @@ -5131,12 +5131,7 @@ if (!ICI.isEquality() && DivIsSigned != ICI.isSignedPredicate()) return 0; if (DivRHS->isZero()) - return 0; // Don't hack on div by zero - - // Initialize the variables that will indicate the nature of the - // range check. - bool LoOverflow = false, HiOverflow = false; - ConstantInt *LoBound = 0, *HiBound = 0; + return 0; // The ProdOV computation fails on divide by zero. // Compute Prod = CI * DivRHS. We are essentially solving an equation // of form X/C1=C2. We solve for X by multiplying C1 (DivRHS) and @@ -5151,87 +5146,108 @@ ConstantExpr::getUDiv(Prod, DivRHS)) != CmpRHS; // Get the ICmp opcode - ICmpInst::Predicate predicate = ICI.getPredicate(); + ICmpInst::Predicate Pred = ICI.getPredicate(); + // Figure out the interval that is being checked. For example, a comparison + // like "X /u 5 == 0" is really checking that X is in the interval [0, 5). + // Compute this interval based on the constants involved and the signedness of + // the compare/divide. This computes a half-open interval, keeping track of + // whether either value in the interval overflows. After analysis each + // overflow variable is set to 0 if it's corresponding bound variable is valid + // -1 if overflowed off the bottom end, or +1 if overflowed off the top end. + int LoOverflow = 0, HiOverflow = 0; + ConstantInt *LoBound = 0, *HiBound = 0; + + if (!DivIsSigned) { // udiv + // e.g. X/5 op 3 --> [15, 20) LoBound = Prod; - LoOverflow = ProdOV; - HiOverflow = ProdOV || AddWithOverflow(HiBound, LoBound, DivRHS, false); + HiOverflow = LoOverflow = ProdOV; + if (!HiOverflow) + HiOverflow = AddWithOverflow(HiBound, LoBound, DivRHS, false); } else if (DivRHS->getValue().isPositive()) { // Divisor is > 0. if (CmpRHSV == 0) { // (X / pos) op 0 - // Can't overflow. + // Can't overflow. e.g. X/2 op 0 --> [-1, 2) LoBound = cast(ConstantExpr::getNeg(SubOne(DivRHS))); HiBound = DivRHS; } else if (CmpRHSV.isPositive()) { // (X / pos) op pos - LoBound = Prod; - LoOverflow = ProdOV; - HiOverflow = ProdOV || AddWithOverflow(HiBound, Prod, DivRHS, true); + LoBound = Prod; // e.g. X/5 op 3 --> [15, 20) + HiOverflow = LoOverflow = ProdOV; + if (!HiOverflow) + HiOverflow = AddWithOverflow(HiBound, Prod, DivRHS, true); } else { // (X / pos) op neg + // e.g. X/5 op -3 --> [-15-4, -15+1) --> [-19, -14) Constant *DivRHSH = ConstantExpr::getNeg(SubOne(DivRHS)); LoOverflow = AddWithOverflow(LoBound, Prod, - cast(DivRHSH), true); + cast(DivRHSH), true) ? -1 : 0; HiBound = AddOne(Prod); - HiOverflow = ProdOV; + HiOverflow = ProdOV ? -1 : 0; } } else { // Divisor is < 0. if (CmpRHSV == 0) { // (X / neg) op 0 + // e.g. X/-5 op 0 --> [-4, 5) LoBound = AddOne(DivRHS); HiBound = cast(ConstantExpr::getNeg(DivRHS)); - if (HiBound == DivRHS) - return 0; // - INTMIN = INTMIN + if (HiBound == DivRHS) { // -INTMIN = INTMIN + HiOverflow = 1; // [INTMIN+1, overflow) + HiBound = 0; // e.g. X/INTMIN = 0 --> X > INTMIN + } } else if (CmpRHSV.isPositive()) { // (X / neg) op pos - HiOverflow = LoOverflow = ProdOV; + // e.g. X/-5 op 3 --> [-19, -14) + HiOverflow = LoOverflow = ProdOV ? -1 : 0; if (!LoOverflow) - LoOverflow = AddWithOverflow(LoBound, Prod, AddOne(DivRHS), - true); + LoOverflow = AddWithOverflow(LoBound, Prod, AddOne(DivRHS), true) ?-1:0; HiBound = AddOne(Prod); } else { // (X / neg) op neg + // e.g. X/-5 op -3 --> [15, 20) LoBound = Prod; - LoOverflow = HiOverflow = ProdOV; + LoOverflow = HiOverflow = ProdOV ? 1 : 0; HiBound = Subtract(Prod, DivRHS); } - // Dividing by a negate swaps the condition. - predicate = ICmpInst::getSwappedPredicate(predicate); + // Dividing by a negative swaps the condition. LT <-> GT + Pred = ICmpInst::getSwappedPredicate(Pred); } Value *X = DivI->getOperand(0); - switch (predicate) { + switch (Pred) { default: assert(0 && "Unhandled icmp opcode!"); case ICmpInst::ICMP_EQ: if (LoOverflow && HiOverflow) return ReplaceInstUsesWith(ICI, ConstantInt::getFalse()); else if (HiOverflow) - return new ICmpInst(DivIsSigned ? ICmpInst::ICMP_SGE : + return new ICmpInst(DivIsSigned ? ICmpInst::ICMP_SGE : ICmpInst::ICMP_UGE, X, LoBound); else if (LoOverflow) return new ICmpInst(DivIsSigned ? ICmpInst::ICMP_SLT : ICmpInst::ICMP_ULT, X, HiBound); else - return InsertRangeTest(X, LoBound, HiBound, DivIsSigned, - true, ICI); + return InsertRangeTest(X, LoBound, HiBound, DivIsSigned, true, ICI); case ICmpInst::ICMP_NE: if (LoOverflow && HiOverflow) return ReplaceInstUsesWith(ICI, ConstantInt::getTrue()); else if (HiOverflow) - return new ICmpInst(DivIsSigned ? ICmpInst::ICMP_SLT : + return new ICmpInst(DivIsSigned ? ICmpInst::ICMP_SLT : ICmpInst::ICMP_ULT, X, LoBound); else if (LoOverflow) return new ICmpInst(DivIsSigned ? ICmpInst::ICMP_SGE : ICmpInst::ICMP_UGE, X, HiBound); else - return InsertRangeTest(X, LoBound, HiBound, DivIsSigned, - false, ICI); + return InsertRangeTest(X, LoBound, HiBound, DivIsSigned, false, ICI); case ICmpInst::ICMP_ULT: case ICmpInst::ICMP_SLT: - if (LoOverflow) + if (LoOverflow == +1) // Low bound is greater than input range. + return ReplaceInstUsesWith(ICI, ConstantInt::getTrue()); + if (LoOverflow == -1) // Low bound is less than input range. return ReplaceInstUsesWith(ICI, ConstantInt::getFalse()); - return new ICmpInst(predicate, X, LoBound); + return new ICmpInst(Pred, X, LoBound); case ICmpInst::ICMP_UGT: case ICmpInst::ICMP_SGT: - if (HiOverflow) + if (HiOverflow == +1) // High bound greater than input range. return ReplaceInstUsesWith(ICI, ConstantInt::getFalse()); - if (predicate == ICmpInst::ICMP_UGT) + else if (HiOverflow == -1) // High bound less than input range. + return ReplaceInstUsesWith(ICI, ConstantInt::getTrue()); + if (Pred == ICmpInst::ICMP_UGT) return new ICmpInst(ICmpInst::ICMP_UGE, X, HiBound); else return new ICmpInst(ICmpInst::ICMP_SGE, X, HiBound); From evan.cheng at apple.com Thu Jun 21 13:23:04 2007 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 21 Jun 2007 13:23:04 -0500 Subject: [llvm-commits] CVS: llvm/test/CodeGen/ARM/ifcvt2.ll ifcvt6.ll Message-ID: <200706211823.l5LIN4PA023387@zion.cs.uiuc.edu> Changes in directory llvm/test/CodeGen/ARM: ifcvt2.ll updated: 1.1 -> 1.2 ifcvt6.ll updated: 1.1 -> 1.2 --- Log message: Fix tests. --- Diffs of the changes: (+3 -1) ifcvt2.ll | 2 +- ifcvt6.ll | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) Index: llvm/test/CodeGen/ARM/ifcvt2.ll diff -u llvm/test/CodeGen/ARM/ifcvt2.ll:1.1 llvm/test/CodeGen/ARM/ifcvt2.ll:1.2 --- llvm/test/CodeGen/ARM/ifcvt2.ll:1.1 Wed Jun 20 13:26:15 2007 +++ llvm/test/CodeGen/ARM/ifcvt2.ll Thu Jun 21 13:22:42 2007 @@ -1,5 +1,5 @@ ; RUN: llvm-as < %s | llc -march=arm -enable-arm-if-conversion -; RUN: llvm-as < %s | llc -march=arm -enable-arm-if-conversion | grep bxlt | wc -l | grep 2 +; RUN: llvm-as < %s | llc -march=arm -enable-arm-if-conversion | grep bxlt | wc -l | grep 1 ; RUN: llvm-as < %s | llc -march=arm -enable-arm-if-conversion | grep bxgt | wc -l | grep 1 ; RUN: llvm-as < %s | llc -march=arm -enable-arm-if-conversion | grep bxge | wc -l | grep 1 Index: llvm/test/CodeGen/ARM/ifcvt6.ll diff -u llvm/test/CodeGen/ARM/ifcvt6.ll:1.1 llvm/test/CodeGen/ARM/ifcvt6.ll:1.2 --- llvm/test/CodeGen/ARM/ifcvt6.ll:1.1 Wed Jun 20 13:26:15 2007 +++ llvm/test/CodeGen/ARM/ifcvt6.ll Thu Jun 21 13:22:42 2007 @@ -16,3 +16,5 @@ UnifiedReturnBlock: ; preds = %entry ret void } + +declare i32 @bar(...) From resistor at mac.com Thu Jun 21 16:26:04 2007 From: resistor at mac.com (Owen Anderson) Date: Thu, 21 Jun 2007 16:26:04 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/ADT/DepthFirstIterator.h Message-ID: <200706212126.l5LLQ45x027311@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/ADT: DepthFirstIterator.h updated: 1.14 -> 1.15 --- Log message: Have internal df_iterator's use SmallPtrSet instead of std::set. This provides compile time speedups to any pass using df_iterator. --- Diffs of the changes: (+5 -3) DepthFirstIterator.h | 8 +++++--- 1 files changed, 5 insertions(+), 3 deletions(-) Index: llvm/include/llvm/ADT/DepthFirstIterator.h diff -u llvm/include/llvm/ADT/DepthFirstIterator.h:1.14 llvm/include/llvm/ADT/DepthFirstIterator.h:1.15 --- llvm/include/llvm/ADT/DepthFirstIterator.h:1.14 Thu Apr 21 15:13:50 2005 +++ llvm/include/llvm/ADT/DepthFirstIterator.h Thu Jun 21 16:25:36 2007 @@ -35,6 +35,7 @@ #include "llvm/ADT/GraphTraits.h" #include "llvm/ADT/iterator" +#include "llvm/ADT/SmallPtrSet.h" #include #include @@ -58,8 +59,8 @@ // Generic Depth First Iterator -template::NodeType*>, +template::NodeType*, 8>, bool ExtStorage = false, class GT = GraphTraits > class df_iterator : public forward_iterator, public df_iterator_storage { @@ -189,7 +190,8 @@ // Provide global definitions of inverse depth first iterators... -template ::NodeType*>, +template ::NodeType*, 8>, bool External = false> struct idf_iterator : public df_iterator, SetTy, External> { idf_iterator(const df_iterator, SetTy, External> &V) From clattner at apple.com Thu Jun 21 16:38:19 2007 From: clattner at apple.com (Chris Lattner) Date: Thu, 21 Jun 2007 14:38:19 -0700 Subject: [llvm-commits] CVS: llvm/include/llvm/ADT/DepthFirstIterator.h In-Reply-To: <200706212126.l5LLQ45x027311@zion.cs.uiuc.edu> References: <200706212126.l5LLQ45x027311@zion.cs.uiuc.edu> Message-ID: <9C55FBC4-2BA5-4DF7-829B-1F6BAD2A7B40@apple.com> > Have internal df_iterator's use SmallPtrSet instead of std::set. > This provides compile time speedups to any pass using df_iterator. Can you remove the #include of now? -Chris > > > --- > Diffs of the changes: (+5 -3) > > DepthFirstIterator.h | 8 +++++--- > 1 files changed, 5 insertions(+), 3 deletions(-) > > > Index: llvm/include/llvm/ADT/DepthFirstIterator.h > diff -u llvm/include/llvm/ADT/DepthFirstIterator.h:1.14 llvm/ > include/llvm/ADT/DepthFirstIterator.h:1.15 > --- llvm/include/llvm/ADT/DepthFirstIterator.h:1.14 Thu Apr 21 > 15:13:50 2005 > +++ llvm/include/llvm/ADT/DepthFirstIterator.h Thu Jun 21 16:25:36 > 2007 > @@ -35,6 +35,7 @@ > > #include "llvm/ADT/GraphTraits.h" > #include "llvm/ADT/iterator" > +#include "llvm/ADT/SmallPtrSet.h" > #include > #include > > @@ -58,8 +59,8 @@ > > > // Generic Depth First Iterator > -template - std::set GraphTraits::NodeType*>, > +template +class SetType = llvm::SmallPtrSet GraphTraits::NodeType*, 8>, > bool ExtStorage = false, class GT = GraphTraits > > class df_iterator : public forward_iterator ptrdiff_t>, > public df_iterator_storage { > @@ -189,7 +190,8 @@ > > > // Provide global definitions of inverse depth first iterators... > -template GraphTraits::NodeType*>, > +template + class SetTy = llvm::SmallPtrSet GraphTraits::NodeType*, 8>, > bool External = false> > struct idf_iterator : public df_iterator, SetTy, > External> { > idf_iterator(const df_iterator, SetTy, External> &V) > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From djg at cray.com Thu Jun 21 16:56:21 2007 From: djg at cray.com (Dan Gohman) Date: Thu, 21 Jun 2007 16:56:21 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrFPStack.td X86InstrInfo.cpp X86InstrInfo.h X86InstrInfo.td X86InstrMMX.td X86InstrSSE.td Message-ID: <20070621215621.GR5693@village.us.cray.com> > I'm sorry to be such a pain, but this seems like a step backward. > We've gone from having an explicit flag in the .td files to having > another magic table in the .cpp file (somewhat amusing because > 'duplicable' just made the opposite transition). > > How about this proposal (Obviously feel free to pick better names for > these things): > > 1. Reintroduce the 'isremat-able' flag, set it to true for all the > instructions that are *potentially* rematerializable. > 2. Add a virtual target hook that can override the flag: > "TII::isReallyRematerializable(Machineinstr*)". > 3. Introduce a new non-virtual method: > bool TII::isRematerializable(Machineinstr *MI) { > return MI->flags->isrematable && isReallyRematerializable(MI); > } I tried this, and got circular dependencies between libLLVMAnalysis.a, libLLVMTarget.a, and libLLVMCodeGen.a. I think it's because the actual code for 3. uses MachineInstr::getOpcode. > > This achieves two things: > > 1. Just looking at the .td file, you can tell which instructions are > candidates for remat. > 2. The isRematerializable predicate is faster for instructions that > are not remat-able. > 3. The isReallyRematerializable only needs to be implemented by > targets with instructions that are remat-able only in some cases > (like the x86 instructions). > > To me, #1 is the killer feature. In general, I'd like to move away > from having tables (either explicit, like the one in > X86RegisterInfo::foldMemoryOperand, or just big switch stmts) to > having properties on .td file entries. That makes it much more clear > what is going on when inspecting the .td files. > > I'm sorry I didn't look at your patch when you asked for comments, > but does this proposal sound sane? *shrug*. Adding isReMaterializable flags to all the load instructions in the X86 files isn't unambiguously prettier though. But I've already strayed from my tangent here :-}. Attached is a patch which does points 1 and 2 of what you describe above. Dan -- Dan Gohman, Cray Inc. -------------- next part -------------- Index: include/llvm/Target/TargetInstrInfo.h =================================================================== RCS file: /var/cvs/llvm/llvm/include/llvm/Target/TargetInstrInfo.h,v retrieving revision 1.132 diff -u -r1.132 TargetInstrInfo.h --- include/llvm/Target/TargetInstrInfo.h +++ include/llvm/Target/TargetInstrInfo.h @@ -78,6 +78,10 @@ // controls execution. It may be set to 'always'. const unsigned M_PREDICABLE = 1 << 12; +// M_REMATERIALIZIBLE - Set if this instruction can be trivally re-materialized +// at any time, e.g. constant generation, load from constant pool. +const unsigned M_REMATERIALIZIBLE = 1 << 13; + // M_CLOBBERS_PRED - Set if this instruction may clobbers the condition code // register and / or registers that are used to predicate instructions. const unsigned M_CLOBBERS_PRED = 1 << 14; @@ -260,6 +264,13 @@ return get(Opcode).Flags & M_PREDICABLE; } + /// isReMaterializableOpcode - Return true if this opcode can ever be trivially + /// rematerializable. Use use isReallyReMaterializable to test the specific + /// instructions for trivial rematerializability, considering their operands. + bool isReMaterializableOpcode(MachineOpCode Opcode) const { + return get(Opcode).Flags & M_REMATERIALIZIBLE; + } + bool clobbersPredicate(MachineOpCode Opcode) const { return get(Opcode).Flags & M_CLOBBERS_PRED; } @@ -301,14 +312,16 @@ return 0; } - /// isTriviallyReMaterializable - If the specified machine instruction can - /// be trivally re-materialized at any time, e.g. constant generation or - /// loads from constant pools. If not, return false. This predicate must + /// isReallyReMaterializable - For instructions with opcodes for which + /// the M_REMATERIALIZABLE flag is set, this function tests whether the + /// instruction itself is actually trivially rematerializable, considering + /// its operands. This is used for targets that have instructions that are + /// only trivially rematerializable for specific uses. This predicate must /// return false if the instruction has any side effects other than /// producing the value from the load, or if it requres any address /// registers that are not always available. - virtual bool isTriviallyReMaterializable(MachineInstr *MI) const { - return false; + virtual bool isReallyReMaterializable(MachineInstr *MI) const { + return true; } /// convertToThreeAddress - This method must be implemented by targets that Index: lib/CodeGen/LiveIntervalAnalysis.cpp =================================================================== RCS file: /var/cvs/llvm/llvm/lib/CodeGen/LiveIntervalAnalysis.cpp,v retrieving revision 1.248 diff -u -r1.248 LiveIntervalAnalysis.cpp --- lib/CodeGen/LiveIntervalAnalysis.cpp +++ lib/CodeGen/LiveIntervalAnalysis.cpp @@ -340,7 +340,8 @@ // instructions to be re-materialized as well. int FrameIdx = 0; if (vi.DefInst && - (tii_->isTriviallyReMaterializable(vi.DefInst) || + ((tii_->isReMaterializableOpcode(vi.DefInst->getOpcode()) && + tii_->isReallyReMaterializable(vi.DefInst)) || (tii_->isLoadFromStackSlot(vi.DefInst, FrameIdx) && mf_->getFrameInfo()->isFixedObjectIndex(FrameIdx)))) interval.remat = vi.DefInst; Index: lib/CodeGen/VirtRegMap.cpp =================================================================== RCS file: /var/cvs/llvm/llvm/lib/CodeGen/VirtRegMap.cpp,v retrieving revision 1.113 diff -u -r1.113 VirtRegMap.cpp --- lib/CodeGen/VirtRegMap.cpp +++ lib/CodeGen/VirtRegMap.cpp @@ -663,7 +663,8 @@ // If this instruction is being rematerialized, just remove it! int FrameIdx; - if (TII->isTriviallyReMaterializable(&MI) || + if ((TII->isReMaterializableOpcode(MI.getOpcode()) && + TII->isReallyReMaterializable(&MI)) || TII->isLoadFromStackSlot(&MI, FrameIdx)) { bool Remove = true; for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { Index: lib/Target/Target.td =================================================================== RCS file: /var/cvs/llvm/llvm/lib/Target/Target.td,v retrieving revision 1.105 diff -u -r1.105 Target.td --- lib/Target/Target.td +++ lib/Target/Target.td @@ -186,6 +186,7 @@ bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote? bit isCommutable = 0; // Is this 3 operand instruction commutable? bit isTerminator = 0; // Is this part of the terminator for a basic block? + bit isReMaterializable = 0; // Is this instruction re-materializable? bit isPredicable = 0; // Is this instruction predicable? bit hasDelaySlot = 0; // Does this instruction have an delay slot? bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help. Index: lib/Target/ARM/ARMInstrInfo.cpp =================================================================== RCS file: /var/cvs/llvm/llvm/lib/Target/ARM/ARMInstrInfo.cpp,v retrieving revision 1.39 diff -u -r1.39 ARMInstrInfo.cpp --- lib/Target/ARM/ARMInstrInfo.cpp +++ lib/Target/ARM/ARMInstrInfo.cpp @@ -130,20 +130,6 @@ return 0; } -bool ARMInstrInfo::isTriviallyReMaterializable(MachineInstr *MI) const { - switch (MI->getOpcode()) { - default: break; - case ARM::LDRcp: - case ARM::MOVi: - case ARM::MVNi: - case ARM::MOVi2pieces: - case ARM::tLDRcp: - // These instructions are always trivially rematerializable. - return true; - } - return false; -} - static unsigned getUnindexedOpcode(unsigned Opc) { switch (Opc) { default: break; Index: lib/Target/ARM/ARMInstrInfo.h =================================================================== RCS file: /var/cvs/llvm/llvm/lib/Target/ARM/ARMInstrInfo.h,v retrieving revision 1.16 diff -u -r1.16 ARMInstrInfo.h --- lib/Target/ARM/ARMInstrInfo.h +++ lib/Target/ARM/ARMInstrInfo.h @@ -87,7 +87,6 @@ unsigned &SrcReg, unsigned &DstReg) const; virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const; virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const; - virtual bool isTriviallyReMaterializable(MachineInstr *MI) const; virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, MachineBasicBlock::iterator &MBBI, Index: lib/Target/ARM/ARMInstrInfo.td =================================================================== RCS file: /var/cvs/llvm/llvm/lib/Target/ARM/ARMInstrInfo.td,v retrieving revision 1.113 diff -u -r1.113 ARMInstrInfo.td --- lib/Target/ARM/ARMInstrInfo.td +++ lib/Target/ARM/ARMInstrInfo.td @@ -677,6 +677,7 @@ [(set GPR:$dst, (load addrmode2:$addr))]>; // Special LDR for loads from non-pc-relative constpools. +let isReMaterializable = 1 in def LDRcp : AI2<(ops GPR:$dst, addrmode2:$addr), "ldr", " $dst, $addr", []>; @@ -810,6 +811,7 @@ def MOVs : AI1<(ops GPR:$dst, so_reg:$src), "mov", " $dst, $src", [(set GPR:$dst, so_reg:$src)]>; +let isReMaterializable = 1 in def MOVi : AI1<(ops GPR:$dst, so_imm:$src), "mov", " $dst, $src", [(set GPR:$dst, so_imm:$src)]>; @@ -917,6 +919,7 @@ "mvn", " $dst, $src", [(set GPR:$dst, (not GPR:$src))]>; def MVNs : AI<(ops GPR:$dst, so_reg:$src), "mvn", " $dst, $src", [(set GPR:$dst, (not so_reg:$src))]>; +let isReMaterializable = 1 in def MVNi : AI<(ops GPR:$dst, so_imm:$imm), "mvn", " $dst, $imm", [(set GPR:$dst, so_imm_not:$imm)]>; @@ -1187,6 +1190,7 @@ // Large immediate handling. // Two piece so_imms. +let isReMaterializable = 1 in def MOVi2pieces : AI1x2<(ops GPR:$dst, so_imm2part:$src), "mov", " $dst, $src", [(set GPR:$dst, so_imm2part:$src)]>; Index: lib/Target/ARM/ARMInstrThumb.td =================================================================== RCS file: /var/cvs/llvm/llvm/lib/Target/ARM/ARMInstrThumb.td,v retrieving revision 1.32 diff -u -r1.32 ARMInstrThumb.td --- lib/Target/ARM/ARMInstrThumb.td +++ lib/Target/ARM/ARMInstrThumb.td @@ -267,6 +267,7 @@ [(set GPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>; // Special LDR for loads from non-pc-relative constpools. +let isReMaterializable = 1 in def tLDRcp : TIs<(ops GPR:$dst, i32imm:$addr), "ldr $dst, $addr", []>; } // isLoad Index: lib/Target/X86/X86InstrFPStack.td =================================================================== RCS file: /var/cvs/llvm/llvm/lib/Target/X86/X86InstrFPStack.td,v retrieving revision 1.10 diff -u -r1.10 X86InstrFPStack.td --- lib/Target/X86/X86InstrFPStack.td +++ lib/Target/X86/X86InstrFPStack.td @@ -356,6 +356,7 @@ // Floating point loads & stores. def FpLD32m : FpI<(ops RFP:$dst, f32mem:$src), ZeroArgFP, [(set RFP:$dst, (extloadf64f32 addr:$src))]>; +let isReMaterializable = 1 in def FpLD64m : FpI<(ops RFP:$dst, f64mem:$src), ZeroArgFP, [(set RFP:$dst, (loadf64 addr:$src))]>; def FpILD16m : FpI<(ops RFP:$dst, i16mem:$src), ZeroArgFP, @@ -413,10 +414,12 @@ def FXCH : FPI<0xC8, AddRegFrm, (ops RST:$op), "fxch $op">, D9; // Floating point constant loads. +let isReMaterializable = 1 in { def FpLD0 : FpI<(ops RFP:$dst), ZeroArgFP, [(set RFP:$dst, fp64imm0)]>; def FpLD1 : FpI<(ops RFP:$dst), ZeroArgFP, [(set RFP:$dst, fp64imm1)]>; +} def FLD0 : FPI<0xEE, RawFrm, (ops), "fldz">, D9; def FLD1 : FPI<0xE8, RawFrm, (ops), "fld1">, D9; Index: lib/Target/X86/X86InstrInfo.cpp =================================================================== RCS file: /var/cvs/llvm/llvm/lib/Target/X86/X86InstrInfo.cpp,v retrieving revision 1.92 diff -u -r1.92 X86InstrInfo.cpp --- lib/Target/X86/X86InstrInfo.cpp +++ lib/Target/X86/X86InstrInfo.cpp @@ -112,20 +112,11 @@ } -bool X86InstrInfo::isTriviallyReMaterializable(MachineInstr *MI) const { +bool X86InstrInfo::isReallyReMaterializable(MachineInstr *MI) const { + assert(isReMaterializableOpcode(MI->getOpcode()) && + "Check isReMaterializableOpcode before checking isReallyReMaterializable"); switch (MI->getOpcode()) { default: break; - case X86::FpLD0: - case X86::FpLD1: - case X86::MOV8ri: - case X86::MOV16ri: - case X86::MOV32ri: - case X86::MMX_V_SET0: - case X86::MMX_V_SETALLONES: - case X86::V_SET0: - case X86::V_SETALLONES: - // These instructions are always trivially rematerializable. - return true; case X86::MOV8rm: case X86::MOV16rm: case X86::MOV16_rm: @@ -146,7 +137,9 @@ MI->getOperand(2).getImmedValue() == 1 && MI->getOperand(3).getReg() == 0; } - return false; + // All other isReMaterializable instructions are always trivially + // rematerializable. + return true; } /// convertToThreeAddress - This method must be implemented by targets that Index: lib/Target/X86/X86InstrInfo.h =================================================================== RCS file: /var/cvs/llvm/llvm/lib/Target/X86/X86InstrInfo.h,v retrieving revision 1.67 diff -u -r1.67 X86InstrInfo.h --- lib/Target/X86/X86InstrInfo.h +++ lib/Target/X86/X86InstrInfo.h @@ -239,7 +239,7 @@ unsigned& destReg) const; unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const; unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const; - bool isTriviallyReMaterializable(MachineInstr *MI) const; + bool isReallyReMaterializable(MachineInstr *MI) const; /// convertToThreeAddress - This method must be implemented by targets that /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target Index: lib/Target/X86/X86InstrInfo.td =================================================================== RCS file: /var/cvs/llvm/llvm/lib/Target/X86/X86InstrInfo.td,v retrieving revision 1.308 diff -u -r1.308 X86InstrInfo.td --- lib/Target/X86/X86InstrInfo.td +++ lib/Target/X86/X86InstrInfo.td @@ -617,6 +617,7 @@ "mov{w} {$src, $dst|$dst, $src}", []>, OpSize; def MOV32rr : I<0x89, MRMDestReg, (ops GR32:$dst, GR32:$src), "mov{l} {$src, $dst|$dst, $src}", []>; +let isReMaterializable = 1 in { def MOV8ri : Ii8 <0xB0, AddRegFrm, (ops GR8 :$dst, i8imm :$src), "mov{b} {$src, $dst|$dst, $src}", [(set GR8:$dst, imm:$src)]>; @@ -626,6 +627,7 @@ def MOV32ri : Ii32<0xB8, AddRegFrm, (ops GR32:$dst, i32imm:$src), "mov{l} {$src, $dst|$dst, $src}", [(set GR32:$dst, imm:$src)]>; +} def MOV8mi : Ii8 <0xC6, MRM0m, (ops i8mem :$dst, i8imm :$src), "mov{b} {$src, $dst|$dst, $src}", [(store (i8 imm:$src), addr:$dst)]>; @@ -636,6 +638,7 @@ "mov{l} {$src, $dst|$dst, $src}", [(store (i32 imm:$src), addr:$dst)]>; +let isReMaterializable = 1 in { def MOV8rm : I<0x8A, MRMSrcMem, (ops GR8 :$dst, i8mem :$src), "mov{b} {$src, $dst|$dst, $src}", [(set GR8:$dst, (load addr:$src))]>; @@ -645,6 +648,7 @@ def MOV32rm : I<0x8B, MRMSrcMem, (ops GR32:$dst, i32mem:$src), "mov{l} {$src, $dst|$dst, $src}", [(set GR32:$dst, (load addr:$src))]>; +} def MOV8mr : I<0x88, MRMDestMem, (ops i8mem :$dst, GR8 :$src), "mov{b} {$src, $dst|$dst, $src}", @@ -2447,10 +2451,12 @@ "mov{w} {$src, $dst|$dst, $src}", []>, OpSize; def MOV32_rr : I<0x89, MRMDestReg, (ops GR32_:$dst, GR32_:$src), "mov{l} {$src, $dst|$dst, $src}", []>; +let isReMaterializable = 1 in { def MOV16_rm : I<0x8B, MRMSrcMem, (ops GR16_:$dst, i16mem:$src), "mov{w} {$src, $dst|$dst, $src}", []>, OpSize; def MOV32_rm : I<0x8B, MRMSrcMem, (ops GR32_:$dst, i32mem:$src), "mov{l} {$src, $dst|$dst, $src}", []>; +} def MOV16_mr : I<0x89, MRMDestMem, (ops i16mem:$dst, GR16_:$src), "mov{w} {$src, $dst|$dst, $src}", []>, OpSize; def MOV32_mr : I<0x89, MRMDestMem, (ops i32mem:$dst, GR32_:$src), Index: lib/Target/X86/X86InstrMMX.td =================================================================== RCS file: /var/cvs/llvm/llvm/lib/Target/X86/X86InstrMMX.td,v retrieving revision 1.33 diff -u -r1.33 X86InstrMMX.td --- lib/Target/X86/X86InstrMMX.td +++ lib/Target/X86/X86InstrMMX.td @@ -178,6 +178,7 @@ // Data Transfer Instructions def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (ops VR64:$dst, GR32:$src), "movd {$src, $dst|$dst, $src}", []>; +let isReMaterializable = 1 in def MMX_MOVD64rm : MMXI<0x6E, MRMSrcMem, (ops VR64:$dst, i32mem:$src), "movd {$src, $dst|$dst, $src}", []>; def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (ops i32mem:$dst, VR64:$src), @@ -185,6 +186,7 @@ def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (ops VR64:$dst, VR64:$src), "movq {$src, $dst|$dst, $src}", []>; +let isReMaterializable = 1 in def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (ops VR64:$dst, i64mem:$src), "movq {$src, $dst|$dst, $src}", [(set VR64:$dst, (load_mmx addr:$src))]>; @@ -503,12 +505,14 @@ // Alias instructions that map zero vector to pxor. // FIXME: remove when we can teach regalloc that xor reg, reg is ok. -def MMX_V_SET0 : MMXI<0xEF, MRMInitReg, (ops VR64:$dst), - "pxor $dst, $dst", - [(set VR64:$dst, (v1i64 immAllZerosV))]>; -def MMX_V_SETALLONES : MMXI<0x76, MRMInitReg, (ops VR64:$dst), - "pcmpeqd $dst, $dst", - [(set VR64:$dst, (v1i64 immAllOnesV))]>; +let isReMaterializable = 1 in { + def MMX_V_SET0 : MMXI<0xEF, MRMInitReg, (ops VR64:$dst), + "pxor $dst, $dst", + [(set VR64:$dst, (v1i64 immAllZerosV))]>; + def MMX_V_SETALLONES : MMXI<0x76, MRMInitReg, (ops VR64:$dst), + "pcmpeqd $dst, $dst", + [(set VR64:$dst, (v1i64 immAllOnesV))]>; +} //===----------------------------------------------------------------------===// // Non-Instruction Patterns Index: lib/Target/X86/X86InstrSSE.td =================================================================== RCS file: /var/cvs/llvm/llvm/lib/Target/X86/X86InstrSSE.td,v retrieving revision 1.184 diff -u -r1.184 X86InstrSSE.td --- lib/Target/X86/X86InstrSSE.td +++ lib/Target/X86/X86InstrSSE.td @@ -260,6 +260,7 @@ // Move Instructions def MOVSSrr : SSI<0x10, MRMSrcReg, (ops FR32:$dst, FR32:$src), "movss {$src, $dst|$dst, $src}", []>; +let isReMaterializable = 1 in def MOVSSrm : SSI<0x10, MRMSrcMem, (ops FR32:$dst, f32mem:$src), "movss {$src, $dst|$dst, $src}", [(set FR32:$dst, (loadf32 addr:$src))]>; @@ -480,6 +481,7 @@ // Move Instructions def MOVAPSrr : PSI<0x28, MRMSrcReg, (ops VR128:$dst, VR128:$src), "movaps {$src, $dst|$dst, $src}", []>; +let isReMaterializable = 1 in def MOVAPSrm : PSI<0x28, MRMSrcMem, (ops VR128:$dst, f128mem:$src), "movaps {$src, $dst|$dst, $src}", [(set VR128:$dst, (loadv4f32 addr:$src))]>; @@ -759,6 +761,7 @@ // Alias instructions that map zero vector to pxor / xorp* for sse. // FIXME: remove when we can teach regalloc that xor reg, reg is ok. +let isReMaterializable = 1 in def V_SET0 : PSI<0x57, MRMInitReg, (ops VR128:$dst), "xorps $dst, $dst", [(set VR128:$dst, (v4f32 immAllZerosV))]>; @@ -844,6 +847,7 @@ // Move Instructions def MOVSDrr : SDI<0x10, MRMSrcReg, (ops FR64:$dst, FR64:$src), "movsd {$src, $dst|$dst, $src}", []>; +let isReMaterializable = 1 in def MOVSDrm : SDI<0x10, MRMSrcMem, (ops FR64:$dst, f64mem:$src), "movsd {$src, $dst|$dst, $src}", [(set FR64:$dst, (loadf64 addr:$src))]>; @@ -1065,6 +1069,7 @@ // Move Instructions def MOVAPDrr : PDI<0x28, MRMSrcReg, (ops VR128:$dst, VR128:$src), "movapd {$src, $dst|$dst, $src}", []>; +let isReMaterializable = 1 in def MOVAPDrm : PDI<0x28, MRMSrcMem, (ops VR128:$dst, f128mem:$src), "movapd {$src, $dst|$dst, $src}", [(set VR128:$dst, (loadv2f64 addr:$src))]>; @@ -1818,9 +1823,10 @@ // Alias instructions that map zero vector to pxor / xorp* for sse. // FIXME: remove when we can teach regalloc that xor reg, reg is ok. -def V_SETALLONES : PDI<0x76, MRMInitReg, (ops VR128:$dst), - "pcmpeqd $dst, $dst", - [(set VR128:$dst, (v2f64 immAllOnesV))]>; +let isReMaterializable = 1 in + def V_SETALLONES : PDI<0x76, MRMInitReg, (ops VR128:$dst), + "pcmpeqd $dst, $dst", + [(set VR128:$dst, (v2f64 immAllOnesV))]>; // FR64 to 128-bit vector conversion. def MOVSD2PDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, FR64:$src), Index: lib/Target/X86/X86InstrX86-64.td =================================================================== RCS file: /var/cvs/llvm/llvm/lib/Target/X86/X86InstrX86-64.td,v retrieving revision 1.17 diff -u -r1.17 X86InstrX86-64.td --- lib/Target/X86/X86InstrX86-64.td +++ lib/Target/X86/X86InstrX86-64.td @@ -187,6 +187,7 @@ "mov{q} {$src, $dst|$dst, $src}", [(set GR64:$dst, i64immSExt32:$src)]>; +let isReMaterializable = 1 in def MOV64rm : RI<0x8B, MRMSrcMem, (ops GR64:$dst, i64mem:$src), "mov{q} {$src, $dst|$dst, $src}", [(set GR64:$dst, (load addr:$src))]>; Index: utils/TableGen/CodeGenInstruction.h =================================================================== RCS file: /var/cvs/llvm/llvm/utils/TableGen/CodeGenInstruction.h,v retrieving revision 1.30 diff -u -r1.30 CodeGenInstruction.h --- utils/TableGen/CodeGenInstruction.h +++ utils/TableGen/CodeGenInstruction.h @@ -91,6 +91,7 @@ bool isConvertibleToThreeAddress; bool isCommutable; bool isTerminator; + bool isReMaterializable; bool hasDelaySlot; bool usesCustomDAGSchedInserter; bool hasVariableNumberOfOperands; Index: utils/TableGen/CodeGenTarget.cpp =================================================================== RCS file: /var/cvs/llvm/llvm/utils/TableGen/CodeGenTarget.cpp,v retrieving revision 1.94 diff -u -r1.94 CodeGenTarget.cpp --- utils/TableGen/CodeGenTarget.cpp +++ utils/TableGen/CodeGenTarget.cpp @@ -365,6 +365,7 @@ isConvertibleToThreeAddress = R->getValueAsBit("isConvertibleToThreeAddress"); isCommutable = R->getValueAsBit("isCommutable"); isTerminator = R->getValueAsBit("isTerminator"); + isReMaterializable = R->getValueAsBit("isReMaterializable"); hasDelaySlot = R->getValueAsBit("hasDelaySlot"); usesCustomDAGSchedInserter = R->getValueAsBit("usesCustomDAGSchedInserter"); hasCtrlDep = R->getValueAsBit("hasCtrlDep"); Index: utils/TableGen/InstrInfoEmitter.cpp =================================================================== RCS file: /var/cvs/llvm/llvm/utils/TableGen/InstrInfoEmitter.cpp,v retrieving revision 1.62 diff -u -r1.62 InstrInfoEmitter.cpp --- utils/TableGen/InstrInfoEmitter.cpp +++ utils/TableGen/InstrInfoEmitter.cpp @@ -240,6 +240,7 @@ if (Inst.isConvertibleToThreeAddress) OS << "|M_CONVERTIBLE_TO_3_ADDR"; if (Inst.isCommutable) OS << "|M_COMMUTABLE"; if (Inst.isTerminator) OS << "|M_TERMINATOR_FLAG"; + if (Inst.isReMaterializable) OS << "|M_REMATERIALIZIBLE"; if (Inst.clobbersPred) OS << "|M_CLOBBERS_PRED"; if (Inst.isNotDuplicable) OS << "|M_NOT_DUPLICABLE"; if (Inst.usesCustomDAGSchedInserter) From dpatel at apple.com Thu Jun 21 17:29:25 2007 From: dpatel at apple.com (Devang Patel) Date: Thu, 21 Jun 2007 17:29:25 -0500 Subject: [llvm-commits] CVS: llvm/lib/Analysis/IPA/CallGraphSCCPass.cpp Message-ID: <200706212229.l5LMTPnl028512@zion.cs.uiuc.edu> Changes in directory llvm/lib/Analysis/IPA: CallGraphSCCPass.cpp updated: 1.24 -> 1.25 --- Log message: CallGraphSCCPass manager may require other passes. Use schedulePass() to accomodate these requirement instead of directly assigning a manager to new CallGraph PassManager. --- Diffs of the changes: (+1 -1) CallGraphSCCPass.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Analysis/IPA/CallGraphSCCPass.cpp diff -u llvm/lib/Analysis/IPA/CallGraphSCCPass.cpp:1.24 llvm/lib/Analysis/IPA/CallGraphSCCPass.cpp:1.25 --- llvm/lib/Analysis/IPA/CallGraphSCCPass.cpp:1.24 Wed May 2 20:11:53 2007 +++ llvm/lib/Analysis/IPA/CallGraphSCCPass.cpp Thu Jun 21 17:29:02 2007 @@ -178,7 +178,7 @@ // [3] Assign manager to manage this new manager. This may create // and push new managers into PMS Pass *P = dynamic_cast(CGP); - P->assignPassManager(PMS); + TPM->schedulePass(P); // [4] Push new manager into PMS PMS.push(CGP); From sabre at nondot.org Thu Jun 21 18:23:54 2007 From: sabre at nondot.org (Chris Lattner) Date: Thu, 21 Jun 2007 18:23:54 -0500 Subject: [llvm-commits] CVS: llvm/lib/Support/SmallPtrSet.cpp Message-ID: <200706212323.l5LNNsC9029521@zion.cs.uiuc.edu> Changes in directory llvm/lib/Support: SmallPtrSet.cpp updated: 1.6 -> 1.7 --- Log message: Two changes: 1. Make SmallPtrSet::erase faster in the small case by replacing a memmove with a pointer copy. 2. Fix a bug where the null terminator at the end of the array in the small case was not copied --- Diffs of the changes: (+5 -4) SmallPtrSet.cpp | 9 +++++---- 1 files changed, 5 insertions(+), 4 deletions(-) Index: llvm/lib/Support/SmallPtrSet.cpp diff -u llvm/lib/Support/SmallPtrSet.cpp:1.6 llvm/lib/Support/SmallPtrSet.cpp:1.7 --- llvm/lib/Support/SmallPtrSet.cpp:1.6 Sat Apr 14 16:50:21 2007 +++ llvm/lib/Support/SmallPtrSet.cpp Thu Jun 21 18:23:32 2007 @@ -54,9 +54,8 @@ for (void **APtr = SmallArray, **E = SmallArray+NumElements; APtr != E; ++APtr) if (*APtr == Ptr) { - // If it is in the set, move everything over, replacing this element. - memmove(APtr, APtr+1, sizeof(void*)*(E-APtr-1)); - // Clear the end element. + // If it is in the set, replace this element. + *APtr = E[-1]; E[-1] = getEmptyMarker(); --NumElements; return true; @@ -151,7 +150,9 @@ if (that.isSmall()) { CurArraySize = that.CurArraySize; CurArray = &SmallArray[0]; - memcpy(CurArray, that.CurArray, sizeof(void*)*CurArraySize); + // Copy the entire contents of the array, including the -1's and the null + // terminator. + memcpy(CurArray, that.CurArray, sizeof(void*)*(CurArraySize+1)); } else { CurArraySize = that.NumElements < 64 ? 128 : that.NumElements*2; CurArray = new void*[CurArraySize+1]; From dpatel at apple.com Thu Jun 21 18:28:14 2007 From: dpatel at apple.com (dpatel at apple.com) Date: Thu, 21 Jun 2007 16:28:14 -0700 (PDT) Subject: [llvm-commits] [128706] Fix 1519. Message-ID: <20070621232814.6918AA0C5AC0@src> Revision: 128706 Author: dpatel Date: 2007-06-21 16:28:14 -0700 (Thu, 21 Jun 2007) Log Message: ----------- Fix 1519. Patch by Rafael Espindola. Modified Paths: -------------- apple-local/branches/llvm/gcc/llvm-types.cpp Modified: apple-local/branches/llvm/gcc/llvm-types.cpp =================================================================== --- apple-local/branches/llvm/gcc/llvm-types.cpp 2007-06-21 22:36:49 UTC (rev 128705) +++ apple-local/branches/llvm/gcc/llvm-types.cpp 2007-06-21 23:28:14 UTC (rev 128706) @@ -1070,6 +1070,8 @@ void allFieldsAreNotBitFields() { AllBitFields = false; + // Next field is not a bitfield. + LastFieldStartsAtNonByteBoundry = false; } unsigned getGCCStructAlignmentInBytes() const { From clattner at apple.com Thu Jun 21 18:49:17 2007 From: clattner at apple.com (clattner at apple.com) Date: Thu, 21 Jun 2007 16:49:17 -0700 (PDT) Subject: [llvm-commits] [128707] Check in Rafael's hack that works around PR1521, allowing bootstrap on x86-64. Message-ID: <20070621234917.5AE13A0EF8D0@src> Revision: 128707 Author: clattner Date: 2007-06-21 16:49:16 -0700 (Thu, 21 Jun 2007) Log Message: ----------- Check in Rafael's hack that works around PR1521, allowing bootstrap on x86-64. This should be reverted when PR1521 is fixed. Modified Paths: -------------- apple-local/branches/llvm/gcc/c-lex.c Modified: apple-local/branches/llvm/gcc/c-lex.c =================================================================== --- apple-local/branches/llvm/gcc/c-lex.c 2007-06-21 23:28:14 UTC (rev 128706) +++ apple-local/branches/llvm/gcc/c-lex.c 2007-06-21 23:49:16 UTC (rev 128707) @@ -818,6 +818,36 @@ return itk_none; } +/* APPLE LOCAL begin llvm hack for PR1521 */ +#define PART_PRECISION (sizeof (cpp_num_part) * CHAR_BIT) +/* Sign extend a number, with PRECISION significant bits and all + others assumed clear, to fill out a cpp_num structure. */ +static cpp_num +my_cpp_num_sign_extend (cpp_num num, size_t precision) +{ + if (num.high) + printf("%lu\n", num.high); + if (!num.unsignedp) + { + if (precision > PART_PRECISION) + { + precision -= PART_PRECISION; + if (precision < PART_PRECISION + && (num.high & (cpp_num_part) 1 << (precision - 1))) + num.high |= ~(~(cpp_num_part) 0 >> (PART_PRECISION - precision)); + } + else if (num.low & (cpp_num_part) 1 << (precision - 1)) + { + if (precision < PART_PRECISION) + num.low |= ~(~(cpp_num_part) 0 >> (PART_PRECISION - precision)); + num.high = ~(cpp_num_part) 0; + } + } + + return num; +} +/* APPLE LOCAL llvm end */ + /* Interpret TOKEN, an integer with FLAGS as classified by cpplib. */ static tree interpret_integer (const cpp_token *token, unsigned int flags) @@ -828,7 +858,8 @@ cpp_options *options = cpp_get_options (parse_in); integer = cpp_interpret_integer (parse_in, token, flags); - integer = cpp_num_sign_extend (integer, options->precision); + /* APPLE LOCAL llvm hack for PR1521 */ + integer = my_cpp_num_sign_extend (integer, options->precision); /* The type of a constant with a U suffix is straightforward. */ if (flags & CPP_N_UNSIGNED) From resistor at mac.com Thu Jun 21 19:11:40 2007 From: resistor at mac.com (Owen Anderson) Date: Thu, 21 Jun 2007 19:11:40 -0500 Subject: [llvm-commits] CVS: llvm/lib/Support/SmallPtrSet.cpp Message-ID: <200706220011.l5M0BeA0030375@zion.cs.uiuc.edu> Changes in directory llvm/lib/Support: SmallPtrSet.cpp updated: 1.7 -> 1.8 --- Log message: Fix a bug in SmallPtrSet that was causing GVNPRE to enter an infinite loop. --- Diffs of the changes: (+1 -1) SmallPtrSet.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Support/SmallPtrSet.cpp diff -u llvm/lib/Support/SmallPtrSet.cpp:1.7 llvm/lib/Support/SmallPtrSet.cpp:1.8 --- llvm/lib/Support/SmallPtrSet.cpp:1.7 Thu Jun 21 18:23:32 2007 +++ llvm/lib/Support/SmallPtrSet.cpp Thu Jun 21 19:11:18 2007 @@ -154,7 +154,7 @@ // terminator. memcpy(CurArray, that.CurArray, sizeof(void*)*(CurArraySize+1)); } else { - CurArraySize = that.NumElements < 64 ? 128 : that.NumElements*2; + CurArraySize = that.NumElements < 64 ? 128 : that.CurArraySize*2; CurArray = new void*[CurArraySize+1]; memset(CurArray, -1, CurArraySize*sizeof(void*)); From resistor at mac.com Thu Jun 21 19:20:52 2007 From: resistor at mac.com (Owen Anderson) Date: Thu, 21 Jun 2007 19:20:52 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/GVNPRE.cpp Message-ID: <200706220020.l5M0KqfY030774@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: GVNPRE.cpp updated: 1.49 -> 1.50 --- Log message: Make a bunch of optimizations for compile time to GVNPRE, including smarter set unions, deferring blocks rather than computing maximal sets, and smarter use of sets. With these enhancements, the time to optimize 273.perlbmk goes from 5.3s to 2.7s. --- Diffs of the changes: (+41 -17) GVNPRE.cpp | 58 +++++++++++++++++++++++++++++++++++++++++----------------- 1 files changed, 41 insertions(+), 17 deletions(-) Index: llvm/lib/Transforms/Scalar/GVNPRE.cpp diff -u llvm/lib/Transforms/Scalar/GVNPRE.cpp:1.49 llvm/lib/Transforms/Scalar/GVNPRE.cpp:1.50 --- llvm/lib/Transforms/Scalar/GVNPRE.cpp:1.49 Thu Jun 21 12:57:53 2007 +++ llvm/lib/Transforms/Scalar/GVNPRE.cpp Thu Jun 21 19:20:30 2007 @@ -25,6 +25,7 @@ #include "llvm/Function.h" #include "llvm/Analysis/Dominators.h" #include "llvm/Analysis/PostDominators.h" +#include "llvm/ADT/BitVector.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/DepthFirstIterator.h" #include "llvm/ADT/SmallPtrSet.h" @@ -106,6 +107,7 @@ } SmallPtrSet& getMaximalValues() { return maximalValues; } void erase(Value* v); + unsigned size(); }; } @@ -331,6 +333,12 @@ maximalExpressions.erase(create_expression(C)); } +/// size - Return the number of assigned value numbers +unsigned ValueTable::size() { + // NOTE: zero is never assigned + return nextValueNumber; +} + //===----------------------------------------------------------------------===// // GVNPRE Pass //===----------------------------------------------------------------------===// @@ -365,7 +373,7 @@ uint32_t v); Value* phi_translate(Value* V, BasicBlock* pred, BasicBlock* succ); void phi_translate_set(SmallPtrSet& anticIn, BasicBlock* pred, - BasicBlock* succ, SmallPtrSet& out); + BasicBlock* succ, SmallPtrSet& out) ; void topo_sort(SmallPtrSet& set, std::vector& vec); @@ -381,10 +389,10 @@ SmallPtrSet& currPhis, SmallPtrSet& currExps, SmallPtrSet& currTemps); - void buildsets_anticout(BasicBlock* BB, + bool buildsets_anticout(BasicBlock* BB, SmallPtrSet& anticOut, std::set& visited); - bool buildsets_anticin(BasicBlock* BB, + unsigned buildsets_anticin(BasicBlock* BB, SmallPtrSet& anticOut, SmallPtrSet& currExps, SmallPtrSet& currTemps, @@ -395,7 +403,7 @@ std::map& avail, SmallPtrSet& new_set); unsigned insertion_mergepoint(std::vector& workList, - df_iterator D, + df_iterator& D, SmallPtrSet& new_set); bool insertion(Function& F); @@ -830,13 +838,12 @@ /// buildsets_anticout - When walking the postdom tree, calculate the ANTIC_OUT /// set as a function of the ANTIC_IN set of the block's predecessors -void GVNPRE::buildsets_anticout(BasicBlock* BB, +bool GVNPRE::buildsets_anticout(BasicBlock* BB, SmallPtrSet& anticOut, std::set& visited) { if (BB->getTerminator()->getNumSuccessors() == 1) { - if (visited.find(BB->getTerminator()->getSuccessor(0)) == visited.end()) - phi_translate_set(VN.getMaximalValues(), BB, - BB->getTerminator()->getSuccessor(0), anticOut); + if (visited.count(BB->getTerminator()->getSuccessor(0)) == 0) + return true; else phi_translate_set(anticipatedIn[BB->getTerminator()->getSuccessor(0)], BB, BB->getTerminator()->getSuccessor(0), anticOut); @@ -860,12 +867,14 @@ anticOut.erase(*I); } } + + return false; } /// buildsets_anticin - Walk the postdom tree, calculating ANTIC_OUT for /// each block. ANTIC_IN is then a function of ANTIC_OUT and the GEN /// sets populated in buildsets_availout -bool GVNPRE::buildsets_anticin(BasicBlock* BB, +unsigned GVNPRE::buildsets_anticin(BasicBlock* BB, SmallPtrSet& anticOut, SmallPtrSet& currExps, SmallPtrSet& currTemps, @@ -873,7 +882,9 @@ SmallPtrSet& anticIn = anticipatedIn[BB]; SmallPtrSet old (anticIn.begin(), anticIn.end()); - buildsets_anticout(BB, anticOut, visited); + bool defer = buildsets_anticout(BB, anticOut, visited); + if (defer) + return 0; SmallPtrSet S; for (SmallPtrSet::iterator I = anticOut.begin(), @@ -887,7 +898,11 @@ E = currExps.end(); I != E; ++I) if (currTemps.count(*I) == 0) anticIn.insert(*I); - + + BitVector numbers(VN.size()); + for (SmallPtrSet::iterator I = anticIn.begin(), + E = anticIn.end(); I != E; ++I) + numbers.set(VN.lookup(*I)-1); for (SmallPtrSet::iterator I = S.begin(), E = S.end(); I != E; ++I) { // For non-opaque values, we should already have a value numbering. @@ -896,16 +911,17 @@ // so now. if (!isa(*I) && !isa(*I)) VN.lookup_or_add(*I); - val_insert(anticIn, *I); + if (!numbers.test(VN.lookup(*I)-1)) + anticIn.insert(*I); } clean(anticIn); anticOut.clear(); if (old.size() != anticIn.size()) - return true; + return 2; else - return false; + return 1; } /// buildsets - Phase 1 of the main algorithm. Construct the AVAIL_OUT @@ -974,10 +990,18 @@ if (BB == 0) continue; - visited.insert(BB); - changed |= buildsets_anticin(BB, anticOut, generatedTemporaries[BB], + + unsigned ret = buildsets_anticin(BB, anticOut, generatedTemporaries[BB], generatedExpressions[BB], visited); + + if (ret == 0) { + changed = true; + break; + } else { + visited.insert(BB); + changed |= (ret == 2); + } } iterations++; @@ -1054,7 +1078,7 @@ /// insertion_mergepoint - When walking the dom tree, check at each merge /// block for the possibility of a partial redundancy. If present, eliminate it unsigned GVNPRE::insertion_mergepoint(std::vector& workList, - df_iterator D, + df_iterator& D, SmallPtrSet& new_set) { bool changed_function = false; bool new_stuff = false; From resistor at mac.com Thu Jun 21 19:43:44 2007 From: resistor at mac.com (Owen Anderson) Date: Thu, 21 Jun 2007 19:43:44 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/GVNPRE.cpp Message-ID: <200706220043.l5M0hiKs031277@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: GVNPRE.cpp updated: 1.50 -> 1.51 --- Log message: Reserve space in vectors before topologically sorting into them. This improves the time to optimize 403.gcc from 28s to 23.5s. --- Diffs of the changes: (+2 -0) GVNPRE.cpp | 2 ++ 1 files changed, 2 insertions(+) Index: llvm/lib/Transforms/Scalar/GVNPRE.cpp diff -u llvm/lib/Transforms/Scalar/GVNPRE.cpp:1.50 llvm/lib/Transforms/Scalar/GVNPRE.cpp:1.51 --- llvm/lib/Transforms/Scalar/GVNPRE.cpp:1.50 Thu Jun 21 19:20:30 2007 +++ llvm/lib/Transforms/Scalar/GVNPRE.cpp Thu Jun 21 19:43:22 2007 @@ -585,6 +585,7 @@ /// above) void GVNPRE::clean(SmallPtrSet& set) { std::vector worklist; + worklist.reserve(set.size()); topo_sort(set, worklist); for (unsigned i = 0; i < worklist.size(); ++i) { @@ -1173,6 +1174,7 @@ // If there is more than one predecessor... if (pred_begin(BB) != pred_end(BB) && ++pred_begin(BB) != pred_end(BB)) { std::vector workList; + workList.reserve(anticIn.size()); topo_sort(anticIn, workList); DOUT << "Merge Block: " << BB->getName() << "\n"; From dalej at apple.com Thu Jun 21 19:55:19 2007 From: dalej at apple.com (Dale Johannesen) Date: Thu, 21 Jun 2007 19:55:19 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86AsmPrinter.cpp Message-ID: <200706220055.l5M0tJFs031535@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86AsmPrinter.cpp updated: 1.243 -> 1.244 --- Log message: Quote complex names for Darwin X86 and ARM. --- Diffs of the changes: (+7 -1) X86AsmPrinter.cpp | 8 +++++++- 1 files changed, 7 insertions(+), 1 deletion(-) Index: llvm/lib/Target/X86/X86AsmPrinter.cpp diff -u llvm/lib/Target/X86/X86AsmPrinter.cpp:1.243 llvm/lib/Target/X86/X86AsmPrinter.cpp:1.244 --- llvm/lib/Target/X86/X86AsmPrinter.cpp:1.243 Thu Jun 14 10:00:27 2007 +++ llvm/lib/Target/X86/X86AsmPrinter.cpp Thu Jun 21 19:54:56 2007 @@ -120,7 +120,13 @@ DW.BeginModule(&M); } - return AsmPrinter::doInitialization(M); + AsmPrinter::doInitialization(M); + + // Darwin wants symbols to be quoted if they have complex names. + if (Subtarget->isTargetDarwin()) + Mang->setUseQuotes(true); + + return false; } bool X86SharedAsmPrinter::doFinalization(Module &M) { From evan.cheng at apple.com Thu Jun 21 20:36:14 2007 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 21 Jun 2007 20:36:14 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Message-ID: <200706220136.l5M1aEb0032141@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: ScheduleDAGRRList.cpp updated: 1.30 -> 1.31 --- Log message: std::set is really really terrible. Switch to SmallPtrSet to reduce compile time. For Duraid's example. The overall isel time is reduced from 0.6255 sec to 0.1876 sec. --- Diffs of the changes: (+4 -4) ScheduleDAGRRList.cpp | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp:1.30 llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp:1.31 --- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp:1.30 Thu Apr 26 14:40:56 2007 +++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Thu Jun 21 20:35:51 2007 @@ -118,7 +118,7 @@ /// it is not the last use of its first operand, add it to the CommuteSet if /// possible. It will be commuted when it is translated to a MI. void ScheduleDAGRRList::CommuteNodesToReducePressure() { - std::set OperandSeen; + SmallPtrSet OperandSeen; for (unsigned i = Sequence.size()-1; i != 0; --i) { // Ignore first node. SUnit *SU = Sequence[i]; if (!SU) continue; @@ -680,13 +680,13 @@ // FIXME: This is probably too slow! static void isReachable(SUnit *SU, SUnit *TargetSU, - std::set &Visited, bool &Reached) { + SmallPtrSet &Visited, bool &Reached) { if (Reached) return; if (SU == TargetSU) { Reached = true; return; } - if (!Visited.insert(SU).second) return; + if (!Visited.insert(SU)) return; for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); I != E; ++I) @@ -694,7 +694,7 @@ } static bool isReachable(SUnit *SU, SUnit *TargetSU) { - std::set Visited; + SmallPtrSet Visited; bool Reached = false; isReachable(SU, TargetSU, Visited, Reached); return Reached; From resistor at mac.com Thu Jun 21 22:14:26 2007 From: resistor at mac.com (Owen Anderson) Date: Thu, 21 Jun 2007 22:14:26 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/GVNPRE.cpp Message-ID: <200706220314.l5M3EQbW001173@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: GVNPRE.cpp updated: 1.51 -> 1.52 --- Log message: Avoid excessive calls to find_leader when calculating AVAIL_OUT. This reduces the time to optimize 403.gcc from 23.5s to 21.9s. --- Diffs of the changes: (+76 -30) GVNPRE.cpp | 106 +++++++++++++++++++++++++++++++++++++++++++------------------ 1 files changed, 76 insertions(+), 30 deletions(-) Index: llvm/lib/Transforms/Scalar/GVNPRE.cpp diff -u llvm/lib/Transforms/Scalar/GVNPRE.cpp:1.51 llvm/lib/Transforms/Scalar/GVNPRE.cpp:1.52 --- llvm/lib/Transforms/Scalar/GVNPRE.cpp:1.51 Thu Jun 21 19:43:22 2007 +++ llvm/lib/Transforms/Scalar/GVNPRE.cpp Thu Jun 21 22:14:03 2007 @@ -367,45 +367,47 @@ // Helper fuctions // FIXME: eliminate or document these better - void dump(const SmallPtrSet& s) const; - void clean(SmallPtrSet& set); + void dump(const SmallPtrSet& s) const __attribute__((noinline)); + void clean(SmallPtrSet& set) __attribute__((noinline)); Value* find_leader(SmallPtrSet& vals, - uint32_t v); - Value* phi_translate(Value* V, BasicBlock* pred, BasicBlock* succ); + uint32_t v) __attribute__((noinline)); + Value* phi_translate(Value* V, BasicBlock* pred, BasicBlock* succ) __attribute__((noinline)); void phi_translate_set(SmallPtrSet& anticIn, BasicBlock* pred, - BasicBlock* succ, SmallPtrSet& out) ; + BasicBlock* succ, SmallPtrSet& out) __attribute__((noinline)); void topo_sort(SmallPtrSet& set, - std::vector& vec); + std::vector& vec) __attribute__((noinline)); - void cleanup(); - bool elimination(); + void cleanup() __attribute__((noinline)); + bool elimination() __attribute__((noinline)); - void val_insert(SmallPtrSet& s, Value* v); - void val_replace(SmallPtrSet& s, Value* v); - bool dependsOnInvoke(Value* V); + void val_insert(SmallPtrSet& s, Value* v) __attribute__((noinline)); + void val_replace(SmallPtrSet& s, Value* v) __attribute__((noinline)); + bool dependsOnInvoke(Value* V) __attribute__((noinline)); void buildsets_availout(BasicBlock::iterator I, SmallPtrSet& currAvail, SmallPtrSet& currPhis, SmallPtrSet& currExps, - SmallPtrSet& currTemps); + SmallPtrSet& currTemps, + BitVector& availNumbers, + BitVector& expNumbers) __attribute__((noinline)); bool buildsets_anticout(BasicBlock* BB, SmallPtrSet& anticOut, - std::set& visited); + std::set& visited) __attribute__((noinline)); unsigned buildsets_anticin(BasicBlock* BB, SmallPtrSet& anticOut, SmallPtrSet& currExps, SmallPtrSet& currTemps, - std::set& visited); - unsigned buildsets(Function& F); + std::set& visited) __attribute__((noinline)); + unsigned buildsets(Function& F) __attribute__((noinline)); void insertion_pre(Value* e, BasicBlock* BB, std::map& avail, - SmallPtrSet& new_set); + SmallPtrSet& new_set) __attribute__((noinline)); unsigned insertion_mergepoint(std::vector& workList, df_iterator& D, - SmallPtrSet& new_set); - bool insertion(Function& F); + SmallPtrSet& new_set) __attribute__((noinline)); + bool insertion(Function& F) __attribute__((noinline)); }; @@ -795,10 +797,15 @@ SmallPtrSet& currAvail, SmallPtrSet& currPhis, SmallPtrSet& currExps, - SmallPtrSet& currTemps) { + SmallPtrSet& currTemps, + BitVector& availNumbers, + BitVector& expNumbers) { // Handle PHI nodes... if (PHINode* p = dyn_cast(I)) { VN.lookup_or_add(p); + expNumbers.resize(VN.size()); + availNumbers.resize(VN.size()); + currPhis.insert(p); // Handle binary ops... @@ -806,13 +813,26 @@ Value* leftValue = BO->getOperand(0); Value* rightValue = BO->getOperand(1); - VN.lookup_or_add(BO); + unsigned num = VN.lookup_or_add(BO); + expNumbers.resize(VN.size()); + availNumbers.resize(VN.size()); if (isa(leftValue)) - val_insert(currExps, leftValue); + if (!expNumbers.test(VN.lookup(leftValue)-1)) { + currExps.insert(leftValue); + expNumbers.set(VN.lookup(leftValue)-1); + } + if (isa(rightValue)) - val_insert(currExps, rightValue); - val_insert(currExps, BO); + if (!expNumbers.test(VN.lookup(rightValue)-1)) { + currExps.insert(rightValue); + expNumbers.set(VN.lookup(rightValue)-1); + } + + if (!expNumbers.test(VN.lookup(BO)-1)) { + currExps.insert(BO); + expNumbers.set(num-1); + } // Handle cmp ops... } else if (CmpInst* C = dyn_cast(I)) { @@ -820,21 +840,41 @@ Value* rightValue = C->getOperand(1); VN.lookup_or_add(C); - + + unsigned num = VN.lookup_or_add(C); + expNumbers.resize(VN.size()); + availNumbers.resize(VN.size()); + if (isa(leftValue)) - val_insert(currExps, leftValue); + if (!expNumbers.test(VN.lookup(leftValue)-1)) { + currExps.insert(leftValue); + expNumbers.set(VN.lookup(leftValue)-1); + } if (isa(rightValue)) - val_insert(currExps, rightValue); - val_insert(currExps, C); - + if (!expNumbers.test(VN.lookup(rightValue)-1)) { + currExps.insert(rightValue); + expNumbers.set(VN.lookup(rightValue)-1); + } + + if (!expNumbers.test(VN.lookup(C)-1)) { + currExps.insert(C); + expNumbers.set(num-1); + } + // Handle unsupported ops } else if (!I->isTerminator()){ VN.lookup_or_add(I); + expNumbers.resize(VN.size()); + availNumbers.resize(VN.size()); + currTemps.insert(I); } if (!I->isTerminator()) - val_insert(currAvail, I); + if (!availNumbers.test(VN.lookup(I)-1)) { + currAvail.insert(I); + availNumbers.set(VN.lookup(I)-1); + } } /// buildsets_anticout - When walking the postdom tree, calculate the ANTIC_OUT @@ -953,10 +993,16 @@ currAvail.insert(availableOut[DI->getIDom()->getBlock()].begin(), availableOut[DI->getIDom()->getBlock()].end()); + BitVector availNumbers(VN.size()); + for (SmallPtrSet::iterator I = currAvail.begin(), + E = currAvail.end(); I != E; ++I) + availNumbers.set(VN.lookup(*I)); + BitVector expNumbers(VN.size()); for (BasicBlock::iterator BI = BB->begin(), BE = BB->end(); BI != BE; ++BI) - buildsets_availout(BI, currAvail, currPhis, currExps, currTemps); + buildsets_availout(BI, currAvail, currPhis, currExps, + currTemps, availNumbers, expNumbers); } From duraid at octopus.com.au Fri Jun 22 03:27:41 2007 From: duraid at octopus.com.au (Duraid Madina) Date: Fri, 22 Jun 2007 03:27:41 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/Passes.h LinkAllCodegenComponents.h Message-ID: <200706220827.l5M8Rfcl016629@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: Passes.h updated: 1.27 -> 1.28 LinkAllCodegenComponents.h updated: 1.5 -> 1.6 --- Log message: check in the BigBlock local register allocator --- Diffs of the changes: (+10 -0) LinkAllCodegenComponents.h | 1 + Passes.h | 9 +++++++++ 2 files changed, 10 insertions(+) Index: llvm/include/llvm/CodeGen/Passes.h diff -u llvm/include/llvm/CodeGen/Passes.h:1.27 llvm/include/llvm/CodeGen/Passes.h:1.28 --- llvm/include/llvm/CodeGen/Passes.h:1.27 Fri Jun 8 12:18:56 2007 +++ llvm/include/llvm/CodeGen/Passes.h Fri Jun 22 03:27:12 2007 @@ -70,6 +70,15 @@ /// FunctionPass *createLocalRegisterAllocator(); + /// BigBlockRegisterAllocation Pass - The BigBlock register allocator + /// munches single basic blocks at a time, like the local register + /// allocator. While the BigBlock allocator is a little slower, and uses + /// somewhat more memory than the local register allocator, it tends to + /// yield the best allocations (of any of the allocators) for blocks that + /// have hundreds or thousands of instructions in sequence. + /// + FunctionPass *createBigBlockRegisterAllocator(); + /// LinearScanRegisterAllocation Pass - This pass implements the linear scan /// register allocation algorithm, a global register allocator. /// Index: llvm/include/llvm/CodeGen/LinkAllCodegenComponents.h diff -u llvm/include/llvm/CodeGen/LinkAllCodegenComponents.h:1.5 llvm/include/llvm/CodeGen/LinkAllCodegenComponents.h:1.6 --- llvm/include/llvm/CodeGen/LinkAllCodegenComponents.h:1.5 Sun Dec 17 05:13:13 2006 +++ llvm/include/llvm/CodeGen/LinkAllCodegenComponents.h Fri Jun 22 03:27:12 2007 @@ -30,6 +30,7 @@ (void) llvm::createSimpleRegisterAllocator(); (void) llvm::createLocalRegisterAllocator(); + (void) llvm::createBigBlockRegisterAllocator(); (void) llvm::createLinearScanRegisterAllocator(); (void) llvm::createBFS_DAGScheduler(NULL, NULL, NULL); From duraid at octopus.com.au Fri Jun 22 03:27:41 2007 From: duraid at octopus.com.au (Duraid Madina) Date: Fri, 22 Jun 2007 03:27:41 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/RegAllocBigBlock.cpp Message-ID: <200706220827.l5M8RfGi016628@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen: RegAllocBigBlock.cpp added (r1.1) --- Log message: check in the BigBlock local register allocator --- Diffs of the changes: (+852 -0) RegAllocBigBlock.cpp | 852 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 852 insertions(+) Index: llvm/lib/CodeGen/RegAllocBigBlock.cpp diff -c /dev/null llvm/lib/CodeGen/RegAllocBigBlock.cpp:1.1 *** /dev/null Fri Jun 22 03:27:22 2007 --- llvm/lib/CodeGen/RegAllocBigBlock.cpp Fri Jun 22 03:27:12 2007 *************** *** 0 **** --- 1,852 ---- + //===- RegAllocBigBlock.cpp - A register allocator for large basic blocks -===// + // + // The LLVM Compiler Infrastructure + // + // This file was developed by the LLVM research group and is distributed under + // the University of Illinois Open Source License. See LICENSE.TXT for details. + // + //===----------------------------------------------------------------------===// + // + // This register allocator is derived from RegAllocLocal.cpp. Like it, this + // allocator works on one basic block at a time, oblivious to others. + // However, the algorithm used here is suited for long blocks of + // instructions - registers are spilled by greedily choosing those holding + // values that will not be needed for the longest amount of time. This works + // particularly well for blocks with 10 or more times as many instructions + // as machine registers, but can be used for general code. + // + //===----------------------------------------------------------------------===// + // + // TODO: - automagically invoke linearscan for (groups of) small BBs? + // - break ties when picking regs? (probably not worth it in a + // JIT context) + // + //===----------------------------------------------------------------------===// + + #define DEBUG_TYPE "regalloc" + #include "llvm/BasicBlock.h" + #include "llvm/CodeGen/Passes.h" + #include "llvm/CodeGen/MachineFunctionPass.h" + #include "llvm/CodeGen/MachineInstr.h" + #include "llvm/CodeGen/SSARegMap.h" + #include "llvm/CodeGen/MachineFrameInfo.h" + #include "llvm/CodeGen/LiveVariables.h" + #include "llvm/CodeGen/RegAllocRegistry.h" + #include "llvm/Target/TargetInstrInfo.h" + #include "llvm/Target/TargetMachine.h" + #include "llvm/Support/CommandLine.h" + #include "llvm/Support/Debug.h" + #include "llvm/Support/Compiler.h" + #include "llvm/ADT/IndexedMap.h" + #include "llvm/ADT/DenseMap.h" + #include "llvm/ADT/SmallVector.h" + #include "llvm/ADT/Statistic.h" + #include + using namespace llvm; + + STATISTIC(NumStores, "Number of stores added"); + STATISTIC(NumLoads , "Number of loads added"); + STATISTIC(NumFolded, "Number of loads/stores folded into instructions"); + + namespace { + static RegisterRegAlloc + bigBlockRegAlloc("bigblock", " Big-block register allocator", + createBigBlockRegisterAllocator); + + struct VRegKeyInfo { + static inline unsigned getEmptyKey() { return -1U; } + static inline unsigned getTombstoneKey() { return -2U; } + static unsigned getHashValue(const unsigned &Key) { return Key; } + }; + + class VISIBILITY_HIDDEN RABigBlock : public MachineFunctionPass { + public: + static char ID; + RABigBlock() : MachineFunctionPass((intptr_t)&ID) {} + private: + const TargetMachine *TM; + MachineFunction *MF; + const MRegisterInfo *RegInfo; + LiveVariables *LV; + + // InsnTimes - maps machine instructions to their "execute times" + std::map InsnTimes; + + // VRegReadTable - maps VRegs in a BB to the set of times they are read + DenseMap*, VRegKeyInfo> VRegReadTable; + + // StackSlotForVirtReg - Maps virtual regs to the frame index where these + // values are spilled. + std::map StackSlotForVirtReg; + + // Virt2PhysRegMap - This map contains entries for each virtual register + // that is currently available in a physical register. + IndexedMap Virt2PhysRegMap; + + unsigned &getVirt2PhysRegMapSlot(unsigned VirtReg) { + return Virt2PhysRegMap[VirtReg]; + } + + // PhysRegsUsed - This array is effectively a map, containing entries for + // each physical register that currently has a value (ie, it is in + // Virt2PhysRegMap). The value mapped to is the virtual register + // corresponding to the physical register (the inverse of the + // Virt2PhysRegMap), or 0. The value is set to 0 if this register is pinned + // because it is used by a future instruction, and to -2 if it is not + // allocatable. If the entry for a physical register is -1, then the + // physical register is "not in the map". + // + std::vector PhysRegsUsed; + + // PhysRegsUseOrder - This contains a list of the physical registers that + // currently have a virtual register value in them. This list provides an + // ordering of registers, imposing a reallocation order. This list is only + // used if all registers are allocated and we have to spill one, in which + // case we spill the least recently used register. Entries at the front of + // the list are the least recently used registers, entries at the back are + // the most recently used. + // + std::vector PhysRegsUseOrder; + + // VirtRegModified - This bitset contains information about which virtual + // registers need to be spilled back to memory when their registers are + // scavenged. If a virtual register has simply been rematerialized, there + // is no reason to spill it to memory when we need the register back. + // + std::vector VirtRegModified; + + void markVirtRegModified(unsigned Reg, bool Val = true) { + assert(MRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!"); + Reg -= MRegisterInfo::FirstVirtualRegister; + if (VirtRegModified.size() <= Reg) VirtRegModified.resize(Reg+1); + VirtRegModified[Reg] = Val; + } + + bool isVirtRegModified(unsigned Reg) const { + assert(MRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!"); + assert(Reg - MRegisterInfo::FirstVirtualRegister < VirtRegModified.size() + && "Illegal virtual register!"); + return VirtRegModified[Reg - MRegisterInfo::FirstVirtualRegister]; + } + + void MarkPhysRegRecentlyUsed(unsigned Reg) { + if (PhysRegsUseOrder.empty() || + PhysRegsUseOrder.back() == Reg) return; // Already most recently used + + for (unsigned i = PhysRegsUseOrder.size(); i != 0; --i) + if (areRegsEqual(Reg, PhysRegsUseOrder[i-1])) { + unsigned RegMatch = PhysRegsUseOrder[i-1]; // remove from middle + PhysRegsUseOrder.erase(PhysRegsUseOrder.begin()+i-1); + // Add it to the end of the list + PhysRegsUseOrder.push_back(RegMatch); + if (RegMatch == Reg) + return; // Found an exact match, exit early + } + } + + public: + virtual const char *getPassName() const { + return "BigBlock Register Allocator"; + } + + virtual void getAnalysisUsage(AnalysisUsage &AU) const { + AU.addRequired(); + AU.addRequiredID(PHIEliminationID); + AU.addRequiredID(TwoAddressInstructionPassID); + MachineFunctionPass::getAnalysisUsage(AU); + } + + private: + /// runOnMachineFunction - Register allocate the whole function + bool runOnMachineFunction(MachineFunction &Fn); + + /// AllocateBasicBlock - Register allocate the specified basic block. + void AllocateBasicBlock(MachineBasicBlock &MBB); + + /// FillVRegReadTable - Fill out the table of vreg read times given a BB + void FillVRegReadTable(MachineBasicBlock &MBB); + + /// areRegsEqual - This method returns true if the specified registers are + /// related to each other. To do this, it checks to see if they are equal + /// or if the first register is in the alias set of the second register. + /// + bool areRegsEqual(unsigned R1, unsigned R2) const { + if (R1 == R2) return true; + for (const unsigned *AliasSet = RegInfo->getAliasSet(R2); + *AliasSet; ++AliasSet) { + if (*AliasSet == R1) return true; + } + return false; + } + + /// getStackSpaceFor - This returns the frame index of the specified virtual + /// register on the stack, allocating space if necessary. + int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC); + + /// removePhysReg - This method marks the specified physical register as no + /// longer being in use. + /// + void removePhysReg(unsigned PhysReg); + + /// spillVirtReg - This method spills the value specified by PhysReg into + /// the virtual register slot specified by VirtReg. It then updates the RA + /// data structures to indicate the fact that PhysReg is now available. + /// + void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, + unsigned VirtReg, unsigned PhysReg); + + /// spillPhysReg - This method spills the specified physical register into + /// the virtual register slot associated with it. If OnlyVirtRegs is set to + /// true, then the request is ignored if the physical register does not + /// contain a virtual register. + /// + void spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I, + unsigned PhysReg, bool OnlyVirtRegs = false); + + /// assignVirtToPhysReg - This method updates local state so that we know + /// that PhysReg is the proper container for VirtReg now. The physical + /// register must not be used for anything else when this is called. + /// + void assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg); + + /// liberatePhysReg - Make sure the specified physical register is available + /// for use. If there is currently a value in it, it is either moved out of + /// the way or spilled to memory. + /// + void liberatePhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I, + unsigned PhysReg); + + /// isPhysRegAvailable - Return true if the specified physical register is + /// free and available for use. This also includes checking to see if + /// aliased registers are all free... + /// + bool isPhysRegAvailable(unsigned PhysReg) const; + + /// getFreeReg - Look to see if there is a free register available in the + /// specified register class. If not, return 0. + /// + unsigned getFreeReg(const TargetRegisterClass *RC); + + /// chooseReg - Pick a physical register to hold the specified + /// virtual register by choosing the one which will be read furthest + /// in the future. + /// + unsigned chooseReg(MachineBasicBlock &MBB, MachineInstr *MI, + unsigned VirtReg); + + /// reloadVirtReg - This method transforms the specified specified virtual + /// register use to refer to a physical register. This method may do this + /// in one of several ways: if the register is available in a physical + /// register already, it uses that physical register. If the value is not + /// in a physical register, and if there are physical registers available, + /// it loads it into a register. If register pressure is high, and it is + /// possible, it tries to fold the load of the virtual register into the + /// instruction itself. It avoids doing this if register pressure is low to + /// improve the chance that subsequent instructions can use the reloaded + /// value. This method returns the modified instruction. + /// + MachineInstr *reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI, + unsigned OpNum); + + }; + char RABigBlock::ID = 0; + } + + /// getStackSpaceFor - This allocates space for the specified virtual register + /// to be held on the stack. + int RABigBlock::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) { + // Find the location Reg would belong... + std::map::iterator I =StackSlotForVirtReg.lower_bound(VirtReg); + + if (I != StackSlotForVirtReg.end() && I->first == VirtReg) + return I->second; // Already has space allocated? + + // Allocate a new stack object for this spill location... + int FrameIdx = MF->getFrameInfo()->CreateStackObject(RC->getSize(), + RC->getAlignment()); + + // Assign the slot... + StackSlotForVirtReg.insert(I, std::make_pair(VirtReg, FrameIdx)); + return FrameIdx; + } + + + /// removePhysReg - This method marks the specified physical register as no + /// longer being in use. + /// + void RABigBlock::removePhysReg(unsigned PhysReg) { + PhysRegsUsed[PhysReg] = -1; // PhyReg no longer used + + std::vector::iterator It = + std::find(PhysRegsUseOrder.begin(), PhysRegsUseOrder.end(), PhysReg); + if (It != PhysRegsUseOrder.end()) + PhysRegsUseOrder.erase(It); + } + + + /// spillVirtReg - This method spills the value specified by PhysReg into the + /// virtual register slot specified by VirtReg. It then updates the RA data + /// structures to indicate the fact that PhysReg is now available. + /// + void RABigBlock::spillVirtReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator I, + unsigned VirtReg, unsigned PhysReg) { + assert(VirtReg && "Spilling a physical register is illegal!" + " Must not have appropriate kill for the register or use exists beyond" + " the intended one."); + DOUT << " Spilling register " << RegInfo->getName(PhysReg) + << " containing %reg" << VirtReg; + if (!isVirtRegModified(VirtReg)) + DOUT << " which has not been modified, so no store necessary!"; + + // Otherwise, there is a virtual register corresponding to this physical + // register. We only need to spill it into its stack slot if it has been + // modified. + if (isVirtRegModified(VirtReg)) { + const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg); + int FrameIndex = getStackSpaceFor(VirtReg, RC); + DOUT << " to stack slot #" << FrameIndex; + RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIndex, RC); + ++NumStores; // Update statistics + } + + getVirt2PhysRegMapSlot(VirtReg) = 0; // VirtReg no longer available + + DOUT << "\n"; + removePhysReg(PhysReg); + } + + + /// spillPhysReg - This method spills the specified physical register into the + /// virtual register slot associated with it. If OnlyVirtRegs is set to true, + /// then the request is ignored if the physical register does not contain a + /// virtual register. + /// + void RABigBlock::spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I, + unsigned PhysReg, bool OnlyVirtRegs) { + if (PhysRegsUsed[PhysReg] != -1) { // Only spill it if it's used! + assert(PhysRegsUsed[PhysReg] != -2 && "Non allocable reg used!"); + if (PhysRegsUsed[PhysReg] || !OnlyVirtRegs) + spillVirtReg(MBB, I, PhysRegsUsed[PhysReg], PhysReg); + } else { + // If the selected register aliases any other registers, we must make + // sure that one of the aliases isn't alive. + for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg); + *AliasSet; ++AliasSet) + if (PhysRegsUsed[*AliasSet] != -1 && // Spill aliased register. + PhysRegsUsed[*AliasSet] != -2) // If allocatable. + if (PhysRegsUsed[*AliasSet] == 0) { + // This must have been a dead def due to something like this: + // %EAX := + // := op %AL + // No more use of %EAX, %AH, etc. + // %EAX isn't dead upon definition, but %AH is. However %AH isn't + // an operand of definition MI so it's not marked as such. + DOUT << " Register " << RegInfo->getName(*AliasSet) + << " [%reg" << *AliasSet + << "] is never used, removing it frame live list\n"; + removePhysReg(*AliasSet); + } else + spillVirtReg(MBB, I, PhysRegsUsed[*AliasSet], *AliasSet); + } + } + + + /// assignVirtToPhysReg - This method updates local state so that we know + /// that PhysReg is the proper container for VirtReg now. The physical + /// register must not be used for anything else when this is called. + /// + void RABigBlock::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) { + assert(PhysRegsUsed[PhysReg] == -1 && "Phys reg already assigned!"); + // Update information to note the fact that this register was just used, and + // it holds VirtReg. + PhysRegsUsed[PhysReg] = VirtReg; + getVirt2PhysRegMapSlot(VirtReg) = PhysReg; + PhysRegsUseOrder.push_back(PhysReg); // New use of PhysReg + } + + + /// isPhysRegAvailable - Return true if the specified physical register is free + /// and available for use. This also includes checking to see if aliased + /// registers are all free... + /// + bool RABigBlock::isPhysRegAvailable(unsigned PhysReg) const { + if (PhysRegsUsed[PhysReg] != -1) return false; + + // If the selected register aliases any other allocated registers, it is + // not free! + for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg); + *AliasSet; ++AliasSet) + if (PhysRegsUsed[*AliasSet] != -1) // Aliased register in use? + return false; // Can't use this reg then. + return true; + } + + + //////// FIX THIS: + /// getFreeReg - Look to see if there is a free register available in the + /// specified register class. If not, return 0. + /// + unsigned RABigBlock::getFreeReg(const TargetRegisterClass *RC) { + // Get iterators defining the range of registers that are valid to allocate in + // this class, which also specifies the preferred allocation order. + TargetRegisterClass::iterator RI = RC->allocation_order_begin(*MF); + TargetRegisterClass::iterator RE = RC->allocation_order_end(*MF); + + for (; RI != RE; ++RI) + if (isPhysRegAvailable(*RI)) { // Is reg unused? + assert(*RI != 0 && "Cannot use register!"); + return *RI; // Found an unused register! + } + return 0; + } + + + /// liberatePhysReg - Make sure the specified physical register is available for + /// use. If there is currently a value in it, it is either moved out of the way + /// or spilled to memory. + /// + void RABigBlock::liberatePhysReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator &I, + unsigned PhysReg) { + spillPhysReg(MBB, I, PhysReg); + } + + /// chooseReg - Pick a physical register to hold the specified + /// virtual register by choosing the one whose value will be read + /// furthest in the future. + /// + unsigned RABigBlock::chooseReg(MachineBasicBlock &MBB, MachineInstr *I, + unsigned VirtReg) { + const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg); + // First check to see if we have a free register of the requested type... + unsigned PhysReg = getFreeReg(RC); + + // If we didn't find an unused register, find the one which will be + // read at the most distant point in time. + if (PhysReg == 0) { + unsigned delay=0, longest_delay=0; + SmallVector *ReadTimes; + + unsigned curTime = InsnTimes[I]; + + // for all physical regs in the RC, + for(TargetRegisterClass::iterator pReg = RC->begin(); + pReg != RC->end(); ++pReg) { + // how long until they're read? + if(PhysRegsUsed[*pReg]>0) { // ignore non-allocatable regs + ReadTimes = VRegReadTable[PhysRegsUsed[*pReg]]; + SmallVector::iterator pt = + std::lower_bound(ReadTimes->begin(), + ReadTimes->end(), + curTime); + delay = *pt - curTime; + + if(delay > longest_delay) { + longest_delay = delay; + PhysReg = *pReg; + } + } + } + + assert(PhysReg && "couldn't grab a register from the table?"); + // TODO: assert that RC->contains(PhysReg) / handle aliased registers + + // since we needed to look in the table we need to spill this register. + spillPhysReg(MBB, I, PhysReg); + } + + // assign the vreg to our chosen physical register + assignVirtToPhysReg(VirtReg, PhysReg); + return PhysReg; // and return it + } + + + /// reloadVirtReg - This method transforms an instruction with a virtual + /// register use to one that references a physical register. It does this as + /// follows: + /// + /// 1) If the register is already in a physical register, it uses it. + /// 2) Otherwise, if there is a free physical register, it uses that. + /// 3) Otherwise, it calls chooseReg() to get the physical register + /// holding the most distantly needed value, generating a spill in + /// the process. + /// + /// This method returns the modified instruction. + MachineInstr *RABigBlock::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI, + unsigned OpNum) { + unsigned VirtReg = MI->getOperand(OpNum).getReg(); + + // If the virtual register is already available in a physical register, + // just update the instruction and return. + if (unsigned PR = getVirt2PhysRegMapSlot(VirtReg)) { + MI->getOperand(OpNum).setReg(PR); + return MI; + } + + // Otherwise, if we have free physical registers available to hold the + // value, use them. + const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg); + unsigned PhysReg = getFreeReg(RC); + int FrameIndex = getStackSpaceFor(VirtReg, RC); + + if (PhysReg) { // we have a free register, so use it. + assignVirtToPhysReg(VirtReg, PhysReg); + } else { // no free registers available. + // try to fold the spill into the instruction + if(MachineInstr* FMI = RegInfo->foldMemoryOperand(MI, OpNum, FrameIndex)) { + ++NumFolded; + // Since we changed the address of MI, make sure to update live variables + // to know that the new instruction has the properties of the old one. + LV->instructionChanged(MI, FMI); + return MBB.insert(MBB.erase(MI), FMI); + } + + // determine which of the physical registers we'll kill off, since we + // couldn't fold. + PhysReg = chooseReg(MBB, MI, VirtReg); + } + + // this virtual register is now unmodified (since we just reloaded it) + markVirtRegModified(VirtReg, false); + + DOUT << " Reloading %reg" << VirtReg << " into " + << RegInfo->getName(PhysReg) << "\n"; + + // Add move instruction(s) + RegInfo->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC); + ++NumLoads; // Update statistics + + MF->setPhysRegUsed(PhysReg); + MI->getOperand(OpNum).setReg(PhysReg); // Assign the input register + return MI; + } + + /// Fill out the vreg read timetable. Since ReadTime increases + /// monotonically, the individual readtime sets will be sorted + /// in ascending order. + void RABigBlock::FillVRegReadTable(MachineBasicBlock &MBB) { + // loop over each instruction + MachineBasicBlock::iterator MII; + unsigned ReadTime; + + for(ReadTime=0, MII = MBB.begin(); MII != MBB.end(); ++ReadTime, ++MII) { + MachineInstr *MI = MII; + + InsnTimes[MI] = ReadTime; + + for (unsigned i = 0; i != MI->getNumOperands(); ++i) { + MachineOperand& MO = MI->getOperand(i); + // look for vreg reads.. + if (MO.isRegister() && !MO.isDef() && MO.getReg() && + MRegisterInfo::isVirtualRegister(MO.getReg())) { + // ..and add them to the read table. + if(!VRegReadTable[MO.getReg()]) + VRegReadTable[MO.getReg()] = new SmallVector; + + VRegReadTable[MO.getReg()]->push_back(ReadTime); + } + } + + } + + } + + void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) { + // loop over each instruction + MachineBasicBlock::iterator MII = MBB.begin(); + const TargetInstrInfo &TII = *TM->getInstrInfo(); + + DEBUG(const BasicBlock *LBB = MBB.getBasicBlock(); + if (LBB) DOUT << "\nStarting RegAlloc of BB: " << LBB->getName()); + + // If this is the first basic block in the machine function, add live-in + // registers as active. + if (&MBB == &*MF->begin()) { + for (MachineFunction::livein_iterator I = MF->livein_begin(), + E = MF->livein_end(); I != E; ++I) { + unsigned Reg = I->first; + MF->setPhysRegUsed(Reg); + PhysRegsUsed[Reg] = 0; // It is free and reserved now + PhysRegsUseOrder.push_back(Reg); + for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg); + *AliasSet; ++AliasSet) { + if (PhysRegsUsed[*AliasSet] != -2) { + PhysRegsUseOrder.push_back(*AliasSet); + PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now + MF->setPhysRegUsed(*AliasSet); + } + } + } + } + + // Otherwise, sequentially allocate each instruction in the MBB. + while (MII != MBB.end()) { + MachineInstr *MI = MII++; + const TargetInstrDescriptor &TID = TII.get(MI->getOpcode()); + DEBUG(DOUT << "\nStarting RegAlloc of: " << *MI; + DOUT << " Regs have values: "; + for (unsigned i = 0; i != RegInfo->getNumRegs(); ++i) + if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2) + DOUT << "[" << RegInfo->getName(i) + << ",%reg" << PhysRegsUsed[i] << "] "; + DOUT << "\n"); + + // Loop over the implicit uses, making sure that they are at the head of the + // use order list, so they don't get reallocated. + if (TID.ImplicitUses) { + for (const unsigned *ImplicitUses = TID.ImplicitUses; + *ImplicitUses; ++ImplicitUses) + MarkPhysRegRecentlyUsed(*ImplicitUses); + } + + SmallVector Kills; + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + MachineOperand& MO = MI->getOperand(i); + if (MO.isRegister() && MO.isKill()) + Kills.push_back(MO.getReg()); + } + + // Get the used operands into registers. This has the potential to spill + // incoming values if we are out of registers. Note that we completely + // ignore physical register uses here. We assume that if an explicit + // physical register is referenced by the instruction, that it is guaranteed + // to be live-in, or the input is badly hosed. + // + for (unsigned i = 0; i != MI->getNumOperands(); ++i) { + MachineOperand& MO = MI->getOperand(i); + // here we are looking for only used operands (never def&use) + if (MO.isRegister() && !MO.isDef() && MO.getReg() && !MO.isImplicit() && + MRegisterInfo::isVirtualRegister(MO.getReg())) + MI = reloadVirtReg(MBB, MI, i); + } + + // If this instruction is the last user of this register, kill the + // value, freeing the register being used, so it doesn't need to be + // spilled to memory. + // + for (unsigned i = 0, e = Kills.size(); i != e; ++i) { + unsigned VirtReg = Kills[i]; + unsigned PhysReg = VirtReg; + if (MRegisterInfo::isVirtualRegister(VirtReg)) { + // If the virtual register was never materialized into a register, it + // might not be in the map, but it won't hurt to zero it out anyway. + unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg); + PhysReg = PhysRegSlot; + PhysRegSlot = 0; + } else if (PhysRegsUsed[PhysReg] == -2) { + // Unallocatable register dead, ignore. + continue; + } + + if (PhysReg) { + DOUT << " Last use of " << RegInfo->getName(PhysReg) + << "[%reg" << VirtReg <<"], removing it from live set\n"; + removePhysReg(PhysReg); + for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg); + *AliasSet; ++AliasSet) { + if (PhysRegsUsed[*AliasSet] != -2) { + DOUT << " Last use of " + << RegInfo->getName(*AliasSet) + << "[%reg" << VirtReg <<"], removing it from live set\n"; + removePhysReg(*AliasSet); + } + } + } + } + + // Loop over all of the operands of the instruction, spilling registers that + // are defined, and marking explicit destinations in the PhysRegsUsed map. + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + MachineOperand& MO = MI->getOperand(i); + if (MO.isRegister() && MO.isDef() && !MO.isImplicit() && MO.getReg() && + MRegisterInfo::isPhysicalRegister(MO.getReg())) { + unsigned Reg = MO.getReg(); + if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP. + + MF->setPhysRegUsed(Reg); + spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in reg + PhysRegsUsed[Reg] = 0; // It is free and reserved now + PhysRegsUseOrder.push_back(Reg); + for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg); + *AliasSet; ++AliasSet) { + if (PhysRegsUsed[*AliasSet] != -2) { + PhysRegsUseOrder.push_back(*AliasSet); + PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now + MF->setPhysRegUsed(*AliasSet); + } + } + } + } + + // Loop over the implicit defs, spilling them as well. + if (TID.ImplicitDefs) { + for (const unsigned *ImplicitDefs = TID.ImplicitDefs; + *ImplicitDefs; ++ImplicitDefs) { + unsigned Reg = *ImplicitDefs; + bool IsNonAllocatable = PhysRegsUsed[Reg] == -2; + if (!IsNonAllocatable) { + spillPhysReg(MBB, MI, Reg, true); + PhysRegsUseOrder.push_back(Reg); + PhysRegsUsed[Reg] = 0; // It is free and reserved now + } + MF->setPhysRegUsed(Reg); + + for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg); + *AliasSet; ++AliasSet) { + if (PhysRegsUsed[*AliasSet] != -2) { + if (!IsNonAllocatable) { + PhysRegsUseOrder.push_back(*AliasSet); + PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now + } + MF->setPhysRegUsed(*AliasSet); + } + } + } + } + + SmallVector DeadDefs; + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + MachineOperand& MO = MI->getOperand(i); + if (MO.isRegister() && MO.isDead()) + DeadDefs.push_back(MO.getReg()); + } + + // Okay, we have allocated all of the source operands and spilled any values + // that would be destroyed by defs of this instruction. Loop over the + // explicit defs and assign them to a register, spilling incoming values if + // we need to scavenge a register. + // + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + MachineOperand& MO = MI->getOperand(i); + if (MO.isRegister() && MO.isDef() && MO.getReg() && + MRegisterInfo::isVirtualRegister(MO.getReg())) { + unsigned DestVirtReg = MO.getReg(); + unsigned DestPhysReg; + + // If DestVirtReg already has a value, use it. + if (!(DestPhysReg = getVirt2PhysRegMapSlot(DestVirtReg))) + DestPhysReg = chooseReg(MBB, MI, DestVirtReg); + MF->setPhysRegUsed(DestPhysReg); + markVirtRegModified(DestVirtReg); + MI->getOperand(i).setReg(DestPhysReg); // Assign the output register + } + } + + // If this instruction defines any registers that are immediately dead, + // kill them now. + // + for (unsigned i = 0, e = DeadDefs.size(); i != e; ++i) { + unsigned VirtReg = DeadDefs[i]; + unsigned PhysReg = VirtReg; + if (MRegisterInfo::isVirtualRegister(VirtReg)) { + unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg); + PhysReg = PhysRegSlot; + assert(PhysReg != 0); + PhysRegSlot = 0; + } else if (PhysRegsUsed[PhysReg] == -2) { + // Unallocatable register dead, ignore. + continue; + } + + if (PhysReg) { + DOUT << " Register " << RegInfo->getName(PhysReg) + << " [%reg" << VirtReg + << "] is never used, removing it frame live list\n"; + removePhysReg(PhysReg); + for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg); + *AliasSet; ++AliasSet) { + if (PhysRegsUsed[*AliasSet] != -2) { + DOUT << " Register " << RegInfo->getName(*AliasSet) + << " [%reg" << *AliasSet + << "] is never used, removing it frame live list\n"; + removePhysReg(*AliasSet); + } + } + } + } + + // Finally, if this is a noop copy instruction, zap it. + unsigned SrcReg, DstReg; + if (TII.isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == DstReg) { + LV->removeVirtualRegistersKilled(MI); + LV->removeVirtualRegistersDead(MI); + MBB.erase(MI); + } + } + + MachineBasicBlock::iterator MI = MBB.getFirstTerminator(); + + // Spill all physical registers holding virtual registers now. + for (unsigned i = 0, e = RegInfo->getNumRegs(); i != e; ++i) + if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2) + if (unsigned VirtReg = PhysRegsUsed[i]) + spillVirtReg(MBB, MI, VirtReg, i); + else + removePhysReg(i); + + #if 0 + // This checking code is very expensive. + bool AllOk = true; + for (unsigned i = MRegisterInfo::FirstVirtualRegister, + e = MF->getSSARegMap()->getLastVirtReg(); i <= e; ++i) + if (unsigned PR = Virt2PhysRegMap[i]) { + cerr << "Register still mapped: " << i << " -> " << PR << "\n"; + AllOk = false; + } + assert(AllOk && "Virtual registers still in phys regs?"); + #endif + + // Clear any physical register which appear live at the end of the basic + // block, but which do not hold any virtual registers. e.g., the stack + // pointer. + PhysRegsUseOrder.clear(); + } + + /// runOnMachineFunction - Register allocate the whole function + /// + bool RABigBlock::runOnMachineFunction(MachineFunction &Fn) { + DOUT << "Machine Function " << "\n"; + MF = &Fn; + TM = &Fn.getTarget(); + RegInfo = TM->getRegisterInfo(); + LV = &getAnalysis(); + + PhysRegsUsed.assign(RegInfo->getNumRegs(), -1); + + // At various places we want to efficiently check to see whether a register + // is allocatable. To handle this, we mark all unallocatable registers as + // being pinned down, permanently. + { + BitVector Allocable = RegInfo->getAllocatableSet(Fn); + for (unsigned i = 0, e = Allocable.size(); i != e; ++i) + if (!Allocable[i]) + PhysRegsUsed[i] = -2; // Mark the reg unallocable. + } + + // initialize the virtual->physical register map to have a 'null' + // mapping for all virtual registers + Virt2PhysRegMap.grow(MF->getSSARegMap()->getLastVirtReg()); + + // Loop over all of the basic blocks, eliminating virtual register references + for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end(); + MBB != MBBe; ++MBB) { + // fill out the read timetable + FillVRegReadTable(*MBB); + // use it to allocate the BB + AllocateBasicBlock(*MBB); + // clear it + VRegReadTable.clear(); + } + + StackSlotForVirtReg.clear(); + PhysRegsUsed.clear(); + VirtRegModified.clear(); + Virt2PhysRegMap.clear(); + return true; + } + + FunctionPass *llvm::createBigBlockRegisterAllocator() { + return new RABigBlock(); + } + From rspencer at reidspencer.com Fri Jun 22 05:22:09 2007 From: rspencer at reidspencer.com (Reid Spencer) Date: Fri, 22 Jun 2007 06:22:09 -0400 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/RegAllocBigBlock.cpp In-Reply-To: <200706220827.l5M8RfGi016628@zion.cs.uiuc.edu> References: <200706220827.l5M8RfGi016628@zion.cs.uiuc.edu> Message-ID: <467BA2D1.2050406@reidspencer.com> Hi Duraid .. This looks nifty. Thanks for adding it. Some minor comments ... Reid. Duraid Madina wrote: >Changes in directory llvm/lib/CodeGen: > >RegAllocBigBlock.cpp added (r1.1) >--- >Log message: > >check in the BigBlock local register allocator > > > >--- >Diffs of the changes: (+852 -0) > > RegAllocBigBlock.cpp | 852 +++++++++++++++++++++++++++++++++++++++++++++++++++ > 1 files changed, 852 insertions(+) > > >Index: llvm/lib/CodeGen/RegAllocBigBlock.cpp >diff -c /dev/null llvm/lib/CodeGen/RegAllocBigBlock.cpp:1.1 >*** /dev/null Fri Jun 22 03:27:22 2007 >--- llvm/lib/CodeGen/RegAllocBigBlock.cpp Fri Jun 22 03:27:12 2007 >*************** >*** 0 **** >--- 1,852 ---- >+ //===- RegAllocBigBlock.cpp - A register allocator for large basic blocks -===// >+ // >+ // The LLVM Compiler Infrastructure >+ // >+ // This file was developed by the LLVM research group and is distributed under > > Really? Wasn't the author Duraid? >+ // the University of Illinois Open Source License. See LICENSE.TXT for details. >+ // >+ //===----------------------------------------------------------------------===// >+ // >+ // This register allocator is derived from RegAllocLocal.cpp. Like it, this >+ // allocator works on one basic block at a time, oblivious to others. >+ // However, the algorithm used here is suited for long blocks of >+ // instructions - registers are spilled by greedily choosing those holding >+ // values that will not be needed for the longest amount of time. This works >+ // particularly well for blocks with 10 or more times as many instructions >+ // as machine registers, but can be used for general code. >+ // >+ //===----------------------------------------------------------------------===// >+ // >+ // TODO: - automagically invoke linearscan for (groups of) small BBs? >+ // - break ties when picking regs? (probably not worth it in a >+ // JIT context) >+ // >+ //===----------------------------------------------------------------------===// > > This entire comment block belongs above the RABigBlock class and should be a doxygen comment (3 /). At this file level the comment should just say "This file implements the RABigBlock class". >+ >+ #define DEBUG_TYPE "regalloc" > > >+ #include "llvm/BasicBlock.h" >+ #include "llvm/CodeGen/Passes.h" >+ #include "llvm/CodeGen/MachineFunctionPass.h" >+ #include "llvm/CodeGen/MachineInstr.h" >+ #include "llvm/CodeGen/SSARegMap.h" >+ #include "llvm/CodeGen/MachineFrameInfo.h" >+ #include "llvm/CodeGen/LiveVariables.h" >+ #include "llvm/CodeGen/RegAllocRegistry.h" >+ #include "llvm/Target/TargetInstrInfo.h" >+ #include "llvm/Target/TargetMachine.h" >+ #include "llvm/Support/CommandLine.h" >+ #include "llvm/Support/Debug.h" >+ #include "llvm/Support/Compiler.h" >+ #include "llvm/ADT/IndexedMap.h" >+ #include "llvm/ADT/DenseMap.h" >+ #include "llvm/ADT/SmallVector.h" >+ #include "llvm/ADT/Statistic.h" >+ #include >+ using namespace llvm; >+ >+ STATISTIC(NumStores, "Number of stores added"); >+ STATISTIC(NumLoads , "Number of loads added"); >+ STATISTIC(NumFolded, "Number of loads/stores folded into instructions"); > > >+ >+ namespace { >+ static RegisterRegAlloc >+ bigBlockRegAlloc("bigblock", " Big-block register allocator", >+ createBigBlockRegisterAllocator); >+ >+ struct VRegKeyInfo { >+ static inline unsigned getEmptyKey() { return -1U; } >+ static inline unsigned getTombstoneKey() { return -2U; } >+ static unsigned getHashValue(const unsigned &Key) { return Key; } >+ }; > > This struct needs a doxygen comment >+ >+ class VISIBILITY_HIDDEN RABigBlock : public MachineFunctionPass { > > This is where you need to move the big comment at the start of the file to. >+ public: >+ static char ID; > > Please add a doxygen comment for this variable. >+ RABigBlock() : MachineFunctionPass((intptr_t)&ID) {} >+ private: >+ const TargetMachine *TM; >+ MachineFunction *MF; >+ const MRegisterInfo *RegInfo; >+ LiveVariables *LV; > > Please use a ///< comment to describe each of these member variables like you do for the ones that follow. >+ >+ // InsnTimes - maps machine instructions to their "execute times" >+ std::map InsnTimes; >+ >+ // VRegReadTable - maps VRegs in a BB to the set of times they are read >+ DenseMap*, VRegKeyInfo> VRegReadTable; >+ >+ // StackSlotForVirtReg - Maps virtual regs to the frame index where these >+ // values are spilled. >+ std::map StackSlotForVirtReg; >+ >+ // Virt2PhysRegMap - This map contains entries for each virtual register >+ // that is currently available in a physical register. >+ IndexedMap Virt2PhysRegMap; > > Please make the above comments into doxygen comments by using /// >+ >+ unsigned &getVirt2PhysRegMapSlot(unsigned VirtReg) { >+ return Virt2PhysRegMap[VirtReg]; >+ } > > This is mis-placed. Please move this function down to where the other functions are located. >+ >+ // PhysRegsUsed - This array is effectively a map, containing entries for >+ // each physical register that currently has a value (ie, it is in >+ // Virt2PhysRegMap). The value mapped to is the virtual register >+ // corresponding to the physical register (the inverse of the >+ // Virt2PhysRegMap), or 0. The value is set to 0 if this register is pinned >+ // because it is used by a future instruction, and to -2 if it is not >+ // allocatable. If the entry for a physical register is -1, then the >+ // physical register is "not in the map". >+ // >+ std::vector PhysRegsUsed; >+ >+ // PhysRegsUseOrder - This contains a list of the physical registers that >+ // currently have a virtual register value in them. This list provides an >+ // ordering of registers, imposing a reallocation order. This list is only >+ // used if all registers are allocated and we have to spill one, in which >+ // case we spill the least recently used register. Entries at the front of >+ // the list are the least recently used registers, entries at the back are >+ // the most recently used. >+ // >+ std::vector PhysRegsUseOrder; >+ >+ // VirtRegModified - This bitset contains information about which virtual >+ // registers need to be spilled back to memory when their registers are >+ // scavenged. If a virtual register has simply been rematerialized, there >+ // is no reason to spill it to memory when we need the register back. >+ // >+ std::vector VirtRegModified; > > Again, these member vars need to use /// insead of // in order for these comments to be picked up by doxygen. >+ >+ void markVirtRegModified(unsigned Reg, bool Val = true) { > > This function needs a doxygen comment. >+ assert(MRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!"); >+ Reg -= MRegisterInfo::FirstVirtualRegister; >+ if (VirtRegModified.size() <= Reg) VirtRegModified.resize(Reg+1); > > It helps readability and debugging if you put the body of the if on a separate line from the condition. >+ VirtRegModified[Reg] = Val; >+ } >+ >+ bool isVirtRegModified(unsigned Reg) const { > > This function needs a doxygen comment >+ assert(MRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!"); >+ assert(Reg - MRegisterInfo::FirstVirtualRegister < VirtRegModified.size() >+ && "Illegal virtual register!"); >+ return VirtRegModified[Reg - MRegisterInfo::FirstVirtualRegister]; >+ } >+ >+ void MarkPhysRegRecentlyUsed(unsigned Reg) { > > This function needs a doxygen comment. >+ if (PhysRegsUseOrder.empty() || >+ PhysRegsUseOrder.back() == Reg) return; // Already most recently used >+ >+ for (unsigned i = PhysRegsUseOrder.size(); i != 0; --i) >+ if (areRegsEqual(Reg, PhysRegsUseOrder[i-1])) { >+ unsigned RegMatch = PhysRegsUseOrder[i-1]; // remove from middle >+ PhysRegsUseOrder.erase(PhysRegsUseOrder.begin()+i-1); >+ // Add it to the end of the list >+ PhysRegsUseOrder.push_back(RegMatch); >+ if (RegMatch == Reg) >+ return; // Found an exact match, exit early >+ } >+ } >+ >+ public: >+ virtual const char *getPassName() const { > > Doxygen comment. >+ return "BigBlock Register Allocator"; >+ } >+ >+ virtual void getAnalysisUsage(AnalysisUsage &AU) const { > > Doxygen comment. >+ AU.addRequired(); >+ AU.addRequiredID(PHIEliminationID); >+ AU.addRequiredID(TwoAddressInstructionPassID); >+ MachineFunctionPass::getAnalysisUsage(AU); >+ } >+ >+ private: >+ /// runOnMachineFunction - Register allocate the whole function > > This won't get picked up by doxygen. Either it needs to be 2 lines long or you need to use @brief >+ bool runOnMachineFunction(MachineFunction &Fn); >+ >+ /// AllocateBasicBlock - Register allocate the specified basic block. > > Same. >+ void AllocateBasicBlock(MachineBasicBlock &MBB); >+ >+ /// FillVRegReadTable - Fill out the table of vreg read times given a BB > > Same. >+ void FillVRegReadTable(MachineBasicBlock &MBB); >+ >+ /// areRegsEqual - This method returns true if the specified registers are >+ /// related to each other. To do this, it checks to see if they are equal >+ /// or if the first register is in the alias set of the second register. >+ /// >+ bool areRegsEqual(unsigned R1, unsigned R2) const { >+ if (R1 == R2) return true; >+ for (const unsigned *AliasSet = RegInfo->getAliasSet(R2); >+ *AliasSet; ++AliasSet) { >+ if (*AliasSet == R1) return true; >+ } >+ return false; >+ } >+ >+ /// getStackSpaceFor - This returns the frame index of the specified virtual >+ /// register on the stack, allocating space if necessary. >+ int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC); >+ >+ /// removePhysReg - This method marks the specified physical register as no >+ /// longer being in use. >+ /// >+ void removePhysReg(unsigned PhysReg); >+ >+ /// spillVirtReg - This method spills the value specified by PhysReg into >+ /// the virtual register slot specified by VirtReg. It then updates the RA >+ /// data structures to indicate the fact that PhysReg is now available. >+ /// >+ void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, >+ unsigned VirtReg, unsigned PhysReg); >+ >+ /// spillPhysReg - This method spills the specified physical register into >+ /// the virtual register slot associated with it. If OnlyVirtRegs is set to >+ /// true, then the request is ignored if the physical register does not >+ /// contain a virtual register. >+ /// >+ void spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I, >+ unsigned PhysReg, bool OnlyVirtRegs = false); >+ >+ /// assignVirtToPhysReg - This method updates local state so that we know >+ /// that PhysReg is the proper container for VirtReg now. The physical >+ /// register must not be used for anything else when this is called. >+ /// >+ void assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg); >+ >+ /// liberatePhysReg - Make sure the specified physical register is available >+ /// for use. If there is currently a value in it, it is either moved out of >+ /// the way or spilled to memory. >+ /// >+ void liberatePhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I, >+ unsigned PhysReg); >+ >+ /// isPhysRegAvailable - Return true if the specified physical register is >+ /// free and available for use. This also includes checking to see if >+ /// aliased registers are all free... >+ /// >+ bool isPhysRegAvailable(unsigned PhysReg) const; >+ >+ /// getFreeReg - Look to see if there is a free register available in the >+ /// specified register class. If not, return 0. >+ /// >+ unsigned getFreeReg(const TargetRegisterClass *RC); >+ >+ /// chooseReg - Pick a physical register to hold the specified >+ /// virtual register by choosing the one which will be read furthest >+ /// in the future. >+ /// >+ unsigned chooseReg(MachineBasicBlock &MBB, MachineInstr *MI, >+ unsigned VirtReg); >+ >+ /// reloadVirtReg - This method transforms the specified specified virtual >+ /// register use to refer to a physical register. This method may do this >+ /// in one of several ways: if the register is available in a physical >+ /// register already, it uses that physical register. If the value is not >+ /// in a physical register, and if there are physical registers available, >+ /// it loads it into a register. If register pressure is high, and it is >+ /// possible, it tries to fold the load of the virtual register into the >+ /// instruction itself. It avoids doing this if register pressure is low to >+ /// improve the chance that subsequent instructions can use the reloaded >+ /// value. This method returns the modified instruction. >+ /// >+ MachineInstr *reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI, >+ unsigned OpNum); >+ >+ }; >+ char RABigBlock::ID = 0; >+ } >+ >+ /// getStackSpaceFor - This allocates space for the specified virtual register >+ /// to be held on the stack. >+ int RABigBlock::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) { >+ // Find the location Reg would belong... >+ std::map::iterator I =StackSlotForVirtReg.lower_bound(VirtReg); >+ >+ if (I != StackSlotForVirtReg.end() && I->first == VirtReg) >+ return I->second; // Already has space allocated? >+ >+ // Allocate a new stack object for this spill location... >+ int FrameIdx = MF->getFrameInfo()->CreateStackObject(RC->getSize(), >+ RC->getAlignment()); >+ >+ // Assign the slot... >+ StackSlotForVirtReg.insert(I, std::make_pair(VirtReg, FrameIdx)); >+ return FrameIdx; >+ } >+ >+ >+ /// removePhysReg - This method marks the specified physical register as no >+ /// longer being in use. >+ /// >+ void RABigBlock::removePhysReg(unsigned PhysReg) { >+ PhysRegsUsed[PhysReg] = -1; // PhyReg no longer used >+ >+ std::vector::iterator It = >+ std::find(PhysRegsUseOrder.begin(), PhysRegsUseOrder.end(), PhysReg); >+ if (It != PhysRegsUseOrder.end()) >+ PhysRegsUseOrder.erase(It); >+ } >+ >+ >+ /// spillVirtReg - This method spills the value specified by PhysReg into the >+ /// virtual register slot specified by VirtReg. It then updates the RA data >+ /// structures to indicate the fact that PhysReg is now available. >+ /// >+ void RABigBlock::spillVirtReg(MachineBasicBlock &MBB, >+ MachineBasicBlock::iterator I, >+ unsigned VirtReg, unsigned PhysReg) { >+ assert(VirtReg && "Spilling a physical register is illegal!" >+ " Must not have appropriate kill for the register or use exists beyond" >+ " the intended one."); >+ DOUT << " Spilling register " << RegInfo->getName(PhysReg) >+ << " containing %reg" << VirtReg; >+ if (!isVirtRegModified(VirtReg)) >+ DOUT << " which has not been modified, so no store necessary!"; >+ >+ // Otherwise, there is a virtual register corresponding to this physical >+ // register. We only need to spill it into its stack slot if it has been >+ // modified. >+ if (isVirtRegModified(VirtReg)) { >+ const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg); >+ int FrameIndex = getStackSpaceFor(VirtReg, RC); >+ DOUT << " to stack slot #" << FrameIndex; >+ RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIndex, RC); >+ ++NumStores; // Update statistics >+ } >+ >+ getVirt2PhysRegMapSlot(VirtReg) = 0; // VirtReg no longer available >+ >+ DOUT << "\n"; >+ removePhysReg(PhysReg); >+ } >+ >+ >+ /// spillPhysReg - This method spills the specified physical register into the >+ /// virtual register slot associated with it. If OnlyVirtRegs is set to true, >+ /// then the request is ignored if the physical register does not contain a >+ /// virtual register. >+ /// >+ void RABigBlock::spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I, >+ unsigned PhysReg, bool OnlyVirtRegs) { >+ if (PhysRegsUsed[PhysReg] != -1) { // Only spill it if it's used! >+ assert(PhysRegsUsed[PhysReg] != -2 && "Non allocable reg used!"); >+ if (PhysRegsUsed[PhysReg] || !OnlyVirtRegs) >+ spillVirtReg(MBB, I, PhysRegsUsed[PhysReg], PhysReg); >+ } else { >+ // If the selected register aliases any other registers, we must make >+ // sure that one of the aliases isn't alive. >+ for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg); >+ *AliasSet; ++AliasSet) >+ if (PhysRegsUsed[*AliasSet] != -1 && // Spill aliased register. >+ PhysRegsUsed[*AliasSet] != -2) // If allocatable. >+ if (PhysRegsUsed[*AliasSet] == 0) { >+ // This must have been a dead def due to something like this: >+ // %EAX := >+ // := op %AL >+ // No more use of %EAX, %AH, etc. >+ // %EAX isn't dead upon definition, but %AH is. However %AH isn't >+ // an operand of definition MI so it's not marked as such. >+ DOUT << " Register " << RegInfo->getName(*AliasSet) >+ << " [%reg" << *AliasSet >+ << "] is never used, removing it frame live list\n"; >+ removePhysReg(*AliasSet); >+ } else >+ spillVirtReg(MBB, I, PhysRegsUsed[*AliasSet], *AliasSet); >+ } >+ } >+ >+ >+ /// assignVirtToPhysReg - This method updates local state so that we know >+ /// that PhysReg is the proper container for VirtReg now. The physical >+ /// register must not be used for anything else when this is called. >+ /// >+ void RABigBlock::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) { >+ assert(PhysRegsUsed[PhysReg] == -1 && "Phys reg already assigned!"); >+ // Update information to note the fact that this register was just used, and >+ // it holds VirtReg. >+ PhysRegsUsed[PhysReg] = VirtReg; >+ getVirt2PhysRegMapSlot(VirtReg) = PhysReg; >+ PhysRegsUseOrder.push_back(PhysReg); // New use of PhysReg >+ } >+ >+ >+ /// isPhysRegAvailable - Return true if the specified physical register is free >+ /// and available for use. This also includes checking to see if aliased >+ /// registers are all free... >+ /// >+ bool RABigBlock::isPhysRegAvailable(unsigned PhysReg) const { >+ if (PhysRegsUsed[PhysReg] != -1) return false; >+ >+ // If the selected register aliases any other allocated registers, it is >+ // not free! >+ for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg); >+ *AliasSet; ++AliasSet) >+ if (PhysRegsUsed[*AliasSet] != -1) // Aliased register in use? >+ return false; // Can't use this reg then. >+ return true; >+ } >+ >+ >+ //////// FIX THIS: > > /// is sufficient. Also, please use "FIXME" or "TODO" as they are more standard for searches and IDE highlighting. >+ /// getFreeReg - Look to see if there is a free register available in the >+ /// specified register class. If not, return 0. >+ /// >+ unsigned RABigBlock::getFreeReg(const TargetRegisterClass *RC) { >+ // Get iterators defining the range of registers that are valid to allocate in >+ // this class, which also specifies the preferred allocation order. >+ TargetRegisterClass::iterator RI = RC->allocation_order_begin(*MF); >+ TargetRegisterClass::iterator RE = RC->allocation_order_end(*MF); >+ >+ for (; RI != RE; ++RI) >+ if (isPhysRegAvailable(*RI)) { // Is reg unused? >+ assert(*RI != 0 && "Cannot use register!"); >+ return *RI; // Found an unused register! >+ } >+ return 0; >+ } >+ >+ >+ /// liberatePhysReg - Make sure the specified physical register is available for >+ /// use. If there is currently a value in it, it is either moved out of the way >+ /// or spilled to memory. >+ /// >+ void RABigBlock::liberatePhysReg(MachineBasicBlock &MBB, >+ MachineBasicBlock::iterator &I, >+ unsigned PhysReg) { >+ spillPhysReg(MBB, I, PhysReg); >+ } >+ >+ /// chooseReg - Pick a physical register to hold the specified >+ /// virtual register by choosing the one whose value will be read >+ /// furthest in the future. >+ /// >+ unsigned RABigBlock::chooseReg(MachineBasicBlock &MBB, MachineInstr *I, >+ unsigned VirtReg) { >+ const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg); >+ // First check to see if we have a free register of the requested type... >+ unsigned PhysReg = getFreeReg(RC); >+ >+ // If we didn't find an unused register, find the one which will be >+ // read at the most distant point in time. >+ if (PhysReg == 0) { >+ unsigned delay=0, longest_delay=0; >+ SmallVector *ReadTimes; >+ >+ unsigned curTime = InsnTimes[I]; >+ >+ // for all physical regs in the RC, >+ for(TargetRegisterClass::iterator pReg = RC->begin(); >+ pReg != RC->end(); ++pReg) { >+ // how long until they're read? >+ if(PhysRegsUsed[*pReg]>0) { // ignore non-allocatable regs >+ ReadTimes = VRegReadTable[PhysRegsUsed[*pReg]]; >+ SmallVector::iterator pt = >+ std::lower_bound(ReadTimes->begin(), >+ ReadTimes->end(), >+ curTime); > > >+ delay = *pt - curTime; >+ >+ if(delay > longest_delay) { >+ longest_delay = delay; >+ PhysReg = *pReg; >+ } >+ } >+ } >+ >+ assert(PhysReg && "couldn't grab a register from the table?"); >+ // TODO: assert that RC->contains(PhysReg) / handle aliased registers >+ >+ // since we needed to look in the table we need to spill this register. >+ spillPhysReg(MBB, I, PhysReg); >+ } >+ >+ // assign the vreg to our chosen physical register >+ assignVirtToPhysReg(VirtReg, PhysReg); >+ return PhysReg; // and return it >+ } >+ >+ >+ /// reloadVirtReg - This method transforms an instruction with a virtual >+ /// register use to one that references a physical register. It does this as >+ /// follows: >+ /// >+ /// 1) If the register is already in a physical register, it uses it. >+ /// 2) Otherwise, if there is a free physical register, it uses that. >+ /// 3) Otherwise, it calls chooseReg() to get the physical register >+ /// holding the most distantly needed value, generating a spill in >+ /// the process. >+ /// >+ /// This method returns the modified instruction. >+ MachineInstr *RABigBlock::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI, >+ unsigned OpNum) { >+ unsigned VirtReg = MI->getOperand(OpNum).getReg(); >+ >+ // If the virtual register is already available in a physical register, >+ // just update the instruction and return. >+ if (unsigned PR = getVirt2PhysRegMapSlot(VirtReg)) { >+ MI->getOperand(OpNum).setReg(PR); >+ return MI; >+ } >+ >+ // Otherwise, if we have free physical registers available to hold the >+ // value, use them. >+ const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg); >+ unsigned PhysReg = getFreeReg(RC); >+ int FrameIndex = getStackSpaceFor(VirtReg, RC); >+ >+ if (PhysReg) { // we have a free register, so use it. >+ assignVirtToPhysReg(VirtReg, PhysReg); >+ } else { // no free registers available. >+ // try to fold the spill into the instruction >+ if(MachineInstr* FMI = RegInfo->foldMemoryOperand(MI, OpNum, FrameIndex)) { >+ ++NumFolded; >+ // Since we changed the address of MI, make sure to update live variables >+ // to know that the new instruction has the properties of the old one. >+ LV->instructionChanged(MI, FMI); >+ return MBB.insert(MBB.erase(MI), FMI); >+ } >+ >+ // determine which of the physical registers we'll kill off, since we >+ // couldn't fold. >+ PhysReg = chooseReg(MBB, MI, VirtReg); >+ } >+ >+ // this virtual register is now unmodified (since we just reloaded it) >+ markVirtRegModified(VirtReg, false); >+ >+ DOUT << " Reloading %reg" << VirtReg << " into " >+ << RegInfo->getName(PhysReg) << "\n"; >+ >+ // Add move instruction(s) >+ RegInfo->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC); >+ ++NumLoads; // Update statistics >+ >+ MF->setPhysRegUsed(PhysReg); >+ MI->getOperand(OpNum).setReg(PhysReg); // Assign the input register >+ return MI; >+ } >+ >+ /// Fill out the vreg read timetable. Since ReadTime increases >+ /// monotonically, the individual readtime sets will be sorted >+ /// in ascending order. >+ void RABigBlock::FillVRegReadTable(MachineBasicBlock &MBB) { >+ // loop over each instruction >+ MachineBasicBlock::iterator MII; >+ unsigned ReadTime; >+ >+ for(ReadTime=0, MII = MBB.begin(); MII != MBB.end(); ++ReadTime, ++MII) { >+ MachineInstr *MI = MII; >+ >+ InsnTimes[MI] = ReadTime; >+ >+ for (unsigned i = 0; i != MI->getNumOperands(); ++i) { >+ MachineOperand& MO = MI->getOperand(i); >+ // look for vreg reads.. >+ if (MO.isRegister() && !MO.isDef() && MO.getReg() && >+ MRegisterInfo::isVirtualRegister(MO.getReg())) { >+ // ..and add them to the read table. >+ if(!VRegReadTable[MO.getReg()]) >+ VRegReadTable[MO.getReg()] = new SmallVector; >+ >+ VRegReadTable[MO.getReg()]->push_back(ReadTime); >+ } >+ } >+ >+ } >+ >+ } >+ >+ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) { >+ // loop over each instruction >+ MachineBasicBlock::iterator MII = MBB.begin(); >+ const TargetInstrInfo &TII = *TM->getInstrInfo(); >+ >+ DEBUG(const BasicBlock *LBB = MBB.getBasicBlock(); >+ if (LBB) DOUT << "\nStarting RegAlloc of BB: " << LBB->getName()); >+ >+ // If this is the first basic block in the machine function, add live-in >+ // registers as active. >+ if (&MBB == &*MF->begin()) { >+ for (MachineFunction::livein_iterator I = MF->livein_begin(), >+ E = MF->livein_end(); I != E; ++I) { >+ unsigned Reg = I->first; >+ MF->setPhysRegUsed(Reg); >+ PhysRegsUsed[Reg] = 0; // It is free and reserved now >+ PhysRegsUseOrder.push_back(Reg); >+ for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg); >+ *AliasSet; ++AliasSet) { >+ if (PhysRegsUsed[*AliasSet] != -2) { >+ PhysRegsUseOrder.push_back(*AliasSet); >+ PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now >+ MF->setPhysRegUsed(*AliasSet); >+ } >+ } >+ } >+ } >+ >+ // Otherwise, sequentially allocate each instruction in the MBB. >+ while (MII != MBB.end()) { >+ MachineInstr *MI = MII++; >+ const TargetInstrDescriptor &TID = TII.get(MI->getOpcode()); >+ DEBUG(DOUT << "\nStarting RegAlloc of: " << *MI; >+ DOUT << " Regs have values: "; >+ for (unsigned i = 0; i != RegInfo->getNumRegs(); ++i) >+ if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2) >+ DOUT << "[" << RegInfo->getName(i) >+ << ",%reg" << PhysRegsUsed[i] << "] "; >+ DOUT << "\n"); >+ >+ // Loop over the implicit uses, making sure that they are at the head of the >+ // use order list, so they don't get reallocated. >+ if (TID.ImplicitUses) { >+ for (const unsigned *ImplicitUses = TID.ImplicitUses; >+ *ImplicitUses; ++ImplicitUses) >+ MarkPhysRegRecentlyUsed(*ImplicitUses); >+ } >+ >+ SmallVector Kills; >+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { >+ MachineOperand& MO = MI->getOperand(i); >+ if (MO.isRegister() && MO.isKill()) >+ Kills.push_back(MO.getReg()); >+ } >+ >+ // Get the used operands into registers. This has the potential to spill >+ // incoming values if we are out of registers. Note that we completely >+ // ignore physical register uses here. We assume that if an explicit >+ // physical register is referenced by the instruction, that it is guaranteed >+ // to be live-in, or the input is badly hosed. >+ // >+ for (unsigned i = 0; i != MI->getNumOperands(); ++i) { >+ MachineOperand& MO = MI->getOperand(i); >+ // here we are looking for only used operands (never def&use) >+ if (MO.isRegister() && !MO.isDef() && MO.getReg() && !MO.isImplicit() && >+ MRegisterInfo::isVirtualRegister(MO.getReg())) >+ MI = reloadVirtReg(MBB, MI, i); >+ } >+ >+ // If this instruction is the last user of this register, kill the >+ // value, freeing the register being used, so it doesn't need to be >+ // spilled to memory. >+ // >+ for (unsigned i = 0, e = Kills.size(); i != e; ++i) { >+ unsigned VirtReg = Kills[i]; >+ unsigned PhysReg = VirtReg; >+ if (MRegisterInfo::isVirtualRegister(VirtReg)) { >+ // If the virtual register was never materialized into a register, it >+ // might not be in the map, but it won't hurt to zero it out anyway. >+ unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg); >+ PhysReg = PhysRegSlot; >+ PhysRegSlot = 0; >+ } else if (PhysRegsUsed[PhysReg] == -2) { >+ // Unallocatable register dead, ignore. >+ continue; >+ } >+ >+ if (PhysReg) { >+ DOUT << " Last use of " << RegInfo->getName(PhysReg) >+ << "[%reg" << VirtReg <<"], removing it from live set\n"; >+ removePhysReg(PhysReg); >+ for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg); >+ *AliasSet; ++AliasSet) { >+ if (PhysRegsUsed[*AliasSet] != -2) { >+ DOUT << " Last use of " >+ << RegInfo->getName(*AliasSet) >+ << "[%reg" << VirtReg <<"], removing it from live set\n"; >+ removePhysReg(*AliasSet); >+ } >+ } >+ } >+ } >+ >+ // Loop over all of the operands of the instruction, spilling registers that >+ // are defined, and marking explicit destinations in the PhysRegsUsed map. >+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { >+ MachineOperand& MO = MI->getOperand(i); >+ if (MO.isRegister() && MO.isDef() && !MO.isImplicit() && MO.getReg() && >+ MRegisterInfo::isPhysicalRegister(MO.getReg())) { >+ unsigned Reg = MO.getReg(); >+ if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP. >+ >+ MF->setPhysRegUsed(Reg); >+ spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in reg >+ PhysRegsUsed[Reg] = 0; // It is free and reserved now >+ PhysRegsUseOrder.push_back(Reg); >+ for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg); >+ *AliasSet; ++AliasSet) { >+ if (PhysRegsUsed[*AliasSet] != -2) { >+ PhysRegsUseOrder.push_back(*AliasSet); >+ PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now >+ MF->setPhysRegUsed(*AliasSet); >+ } >+ } >+ } >+ } >+ >+ // Loop over the implicit defs, spilling them as well. >+ if (TID.ImplicitDefs) { >+ for (const unsigned *ImplicitDefs = TID.ImplicitDefs; >+ *ImplicitDefs; ++ImplicitDefs) { >+ unsigned Reg = *ImplicitDefs; >+ bool IsNonAllocatable = PhysRegsUsed[Reg] == -2; >+ if (!IsNonAllocatable) { >+ spillPhysReg(MBB, MI, Reg, true); >+ PhysRegsUseOrder.push_back(Reg); >+ PhysRegsUsed[Reg] = 0; // It is free and reserved now >+ } >+ MF->setPhysRegUsed(Reg); >+ >+ for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg); >+ *AliasSet; ++AliasSet) { >+ if (PhysRegsUsed[*AliasSet] != -2) { >+ if (!IsNonAllocatable) { >+ PhysRegsUseOrder.push_back(*AliasSet); >+ PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now >+ } >+ MF->setPhysRegUsed(*AliasSet); >+ } >+ } >+ } >+ } >+ >+ SmallVector DeadDefs; >+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { >+ MachineOperand& MO = MI->getOperand(i); >+ if (MO.isRegister() && MO.isDead()) >+ DeadDefs.push_back(MO.getReg()); >+ } >+ >+ // Okay, we have allocated all of the source operands and spilled any values >+ // that would be destroyed by defs of this instruction. Loop over the >+ // explicit defs and assign them to a register, spilling incoming values if >+ // we need to scavenge a register. >+ // >+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { >+ MachineOperand& MO = MI->getOperand(i); >+ if (MO.isRegister() && MO.isDef() && MO.getReg() && >+ MRegisterInfo::isVirtualRegister(MO.getReg())) { >+ unsigned DestVirtReg = MO.getReg(); >+ unsigned DestPhysReg; >+ >+ // If DestVirtReg already has a value, use it. >+ if (!(DestPhysReg = getVirt2PhysRegMapSlot(DestVirtReg))) >+ DestPhysReg = chooseReg(MBB, MI, DestVirtReg); >+ MF->setPhysRegUsed(DestPhysReg); >+ markVirtRegModified(DestVirtReg); >+ MI->getOperand(i).setReg(DestPhysReg); // Assign the output register >+ } >+ } >+ >+ // If this instruction defines any registers that are immediately dead, >+ // kill them now. >+ // >+ for (unsigned i = 0, e = DeadDefs.size(); i != e; ++i) { >+ unsigned VirtReg = DeadDefs[i]; >+ unsigned PhysReg = VirtReg; >+ if (MRegisterInfo::isVirtualRegister(VirtReg)) { >+ unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg); >+ PhysReg = PhysRegSlot; >+ assert(PhysReg != 0); >+ PhysRegSlot = 0; >+ } else if (PhysRegsUsed[PhysReg] == -2) { >+ // Unallocatable register dead, ignore. >+ continue; >+ } >+ >+ if (PhysReg) { >+ DOUT << " Register " << RegInfo->getName(PhysReg) >+ << " [%reg" << VirtReg >+ << "] is never used, removing it frame live list\n"; >+ removePhysReg(PhysReg); >+ for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg); >+ *AliasSet; ++AliasSet) { >+ if (PhysRegsUsed[*AliasSet] != -2) { >+ DOUT << " Register " << RegInfo->getName(*AliasSet) >+ << " [%reg" << *AliasSet >+ << "] is never used, removing it frame live list\n"; >+ removePhysReg(*AliasSet); >+ } >+ } >+ } >+ } >+ >+ // Finally, if this is a noop copy instruction, zap it. >+ unsigned SrcReg, DstReg; >+ if (TII.isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == DstReg) { >+ LV->removeVirtualRegistersKilled(MI); >+ LV->removeVirtualRegistersDead(MI); >+ MBB.erase(MI); >+ } >+ } >+ >+ MachineBasicBlock::iterator MI = MBB.getFirstTerminator(); >+ >+ // Spill all physical registers holding virtual registers now. >+ for (unsigned i = 0, e = RegInfo->getNumRegs(); i != e; ++i) >+ if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2) >+ if (unsigned VirtReg = PhysRegsUsed[i]) >+ spillVirtReg(MBB, MI, VirtReg, i); >+ else >+ removePhysReg(i); >+ >+ #if 0 >+ // This checking code is very expensive. >+ bool AllOk = true; >+ for (unsigned i = MRegisterInfo::FirstVirtualRegister, >+ e = MF->getSSARegMap()->getLastVirtReg(); i <= e; ++i) >+ if (unsigned PR = Virt2PhysRegMap[i]) { >+ cerr << "Register still mapped: " << i << " -> " << PR << "\n"; >+ AllOk = false; >+ } >+ assert(AllOk && "Virtual registers still in phys regs?"); >+ #endif > > Really need to keep this #if 0 section? >+ >+ // Clear any physical register which appear live at the end of the basic >+ // block, but which do not hold any virtual registers. e.g., the stack >+ // pointer. >+ PhysRegsUseOrder.clear(); >+ } >+ >+ /// runOnMachineFunction - Register allocate the whole function >+ /// >+ bool RABigBlock::runOnMachineFunction(MachineFunction &Fn) { >+ DOUT << "Machine Function " << "\n"; >+ MF = &Fn; >+ TM = &Fn.getTarget(); >+ RegInfo = TM->getRegisterInfo(); >+ LV = &getAnalysis(); >+ >+ PhysRegsUsed.assign(RegInfo->getNumRegs(), -1); >+ >+ // At various places we want to efficiently check to see whether a register >+ // is allocatable. To handle this, we mark all unallocatable registers as >+ // being pinned down, permanently. >+ { >+ BitVector Allocable = RegInfo->getAllocatableSet(Fn); >+ for (unsigned i = 0, e = Allocable.size(); i != e; ++i) >+ if (!Allocable[i]) >+ PhysRegsUsed[i] = -2; // Mark the reg unallocable. >+ } >+ >+ // initialize the virtual->physical register map to have a 'null' >+ // mapping for all virtual registers >+ Virt2PhysRegMap.grow(MF->getSSARegMap()->getLastVirtReg()); >+ >+ // Loop over all of the basic blocks, eliminating virtual register references >+ for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end(); >+ MBB != MBBe; ++MBB) { >+ // fill out the read timetable >+ FillVRegReadTable(*MBB); >+ // use it to allocate the BB >+ AllocateBasicBlock(*MBB); >+ // clear it >+ VRegReadTable.clear(); >+ } >+ >+ StackSlotForVirtReg.clear(); >+ PhysRegsUsed.clear(); >+ VirtRegModified.clear(); >+ Virt2PhysRegMap.clear(); >+ return true; >+ } >+ >+ FunctionPass *llvm::createBigBlockRegisterAllocator() { >+ return new RABigBlock(); >+ } >+ > > > >_______________________________________________ >llvm-commits mailing list >llvm-commits at cs.uiuc.edu >http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > > From djg at cray.com Fri Jun 22 09:59:42 2007 From: djg at cray.com (Dan Gohman) Date: Fri, 22 Jun 2007 09:59:42 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp Message-ID: <200706221459.l5MExgg1028677@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Alpha: AlphaISelDAGToDAG.cpp updated: 1.70 -> 1.71 --- Log message: Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from TargetLowering to SelectionDAG so that they have more convenient access to the current DAG, in preparation for the ValueType routines being changed from standalone functions to members of SelectionDAG for the pre-legalize vector type changes. --- Diffs of the changes: (+1 -1) AlphaISelDAGToDAG.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp diff -u llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.70 llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.71 --- llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.70 Tue Jun 19 09:13:56 2007 +++ llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp Fri Jun 22 09:59:07 2007 @@ -90,7 +90,7 @@ // see if the missing bits (0x1000) are already known zero if not, the zap // isn't okay to do, as it won't clear all the required bits. if (BitsToCheck && - !getTargetLowering().MaskedValueIsZero(LHS, BitsToCheck)) + !CurDAG->MaskedValueIsZero(LHS, BitsToCheck)) return 0; return Result; From djg at cray.com Fri Jun 22 09:59:45 2007 From: djg at cray.com (Dan Gohman) Date: Fri, 22 Jun 2007 09:59:45 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp TargetLowering.cpp Message-ID: <200706221459.l5MExji1028691@zion.cs.uiuc.edu> Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.314 -> 1.315 LegalizeDAG.cpp updated: 1.499 -> 1.500 SelectionDAG.cpp updated: 1.408 -> 1.409 SelectionDAGISel.cpp updated: 1.467 -> 1.468 TargetLowering.cpp updated: 1.121 -> 1.122 --- Log message: Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from TargetLowering to SelectionDAG so that they have more convenient access to the current DAG, in preparation for the ValueType routines being changed from standalone functions to members of SelectionDAG for the pre-legalize vector type changes. --- Diffs of the changes: (+582 -581) DAGCombiner.cpp | 46 ++-- LegalizeDAG.cpp | 6 SelectionDAG.cpp | 546 +++++++++++++++++++++++++++++++++++++++++++++++++ SelectionDAGISel.cpp | 4 TargetLowering.cpp | 561 --------------------------------------------------- 5 files changed, 582 insertions(+), 581 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.314 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.315 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.314 Thu Jun 21 02:39:16 2007 +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Jun 22 09:59:07 2007 @@ -896,9 +896,9 @@ uint64_t LHSZero, LHSOne; uint64_t RHSZero, RHSOne; uint64_t Mask = MVT::getIntVTBitMask(VT); - TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); + DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); if (LHSZero) { - TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); + DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); // If all possibly-set bits on the LHS are clear on the RHS, return an OR. // If all possibly-set bits on the RHS are clear on the LHS, return an OR. @@ -957,9 +957,9 @@ uint64_t LHSZero, LHSOne; uint64_t RHSZero, RHSOne; uint64_t Mask = MVT::getIntVTBitMask(VT); - TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); + DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); if (LHSZero) { - TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); + DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); // If all possibly-set bits on the LHS are clear on the RHS, return an OR. // If all possibly-set bits on the RHS are clear on the LHS, return an OR. @@ -1120,8 +1120,8 @@ // If we know the sign bits of both operands are zero, strength reduce to a // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); - if (TLI.MaskedValueIsZero(N1, SignBit) && - TLI.MaskedValueIsZero(N0, SignBit)) + if (DAG.MaskedValueIsZero(N1, SignBit) && + DAG.MaskedValueIsZero(N0, SignBit)) return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); // fold (sdiv X, pow2) -> simple ops after legalize if (N1C && N1C->getValue() && !TLI.isIntDivCheap() && @@ -1214,8 +1214,8 @@ // If we know the sign bits of both operands are zero, strength reduce to a // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); - if (TLI.MaskedValueIsZero(N1, SignBit) && - TLI.MaskedValueIsZero(N0, SignBit)) + if (DAG.MaskedValueIsZero(N1, SignBit) && + DAG.MaskedValueIsZero(N0, SignBit)) return DAG.getNode(ISD::UREM, VT, N0, N1); // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on @@ -1357,7 +1357,7 @@ if (N1C && N1C->isAllOnesValue()) return N0; // if (and x, c) is known to be zero, return 0 - if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) + if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) return DAG.getConstant(0, VT); // reassociate and SDOperand RAND = ReassociateOps(ISD::AND, N0, N1); @@ -1371,7 +1371,7 @@ // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType()); - if (TLI.MaskedValueIsZero(N0.getOperand(0), + if (DAG.MaskedValueIsZero(N0.getOperand(0), ~N1C->getValue() & InMask)) { SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), N0.getOperand(0)); @@ -1442,7 +1442,7 @@ MVT::ValueType EVT = LN0->getLoadedVT(); // If we zero all the possible extended bits, then we can turn this into // a zextload if we are running before legalize or the operation is legal. - if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && + if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), LN0->getBasePtr(), LN0->getSrcValue(), @@ -1461,7 +1461,7 @@ MVT::ValueType EVT = LN0->getLoadedVT(); // If we zero all the possible extended bits, then we can turn this into // a zextload if we are running before legalize or the operation is legal. - if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && + if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), LN0->getBasePtr(), LN0->getSrcValue(), @@ -1542,7 +1542,7 @@ return N1; // fold (or x, c) -> c iff (x & ~c) == 0 if (N1C && - TLI.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)))) + DAG.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)))) return N1; // reassociate or SDOperand ROR = ReassociateOps(ISD::OR, N0, N1); @@ -1611,8 +1611,8 @@ uint64_t LHSMask = cast(N0.getOperand(1))->getValue(); uint64_t RHSMask = cast(N1.getOperand(1))->getValue(); - if (TLI.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && - TLI.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { + if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && + DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0)); return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT)); } @@ -1914,7 +1914,7 @@ if (N1C && N1C->isNullValue()) return N0; // if (shl x, c) is known to be zero, return 0 - if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) + if (DAG.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) return DAG.getConstant(0, VT); if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) return SDOperand(N, 0); @@ -2005,7 +2005,7 @@ // If the sign bit is known to be zero, switch this to a SRL. - if (TLI.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT))) + if (DAG.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT))) return DAG.getNode(ISD::SRL, VT, N0, N1); return SDOperand(); } @@ -2031,7 +2031,7 @@ if (N1C && N1C->isNullValue()) return N0; // if (srl x, c) is known to be zero, return 0 - if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits))) + if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits))) return DAG.getConstant(0, VT); // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) @@ -2068,7 +2068,7 @@ if (N1C && N0.getOpcode() == ISD::CTLZ && N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) { uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT); - TLI.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); + DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); // If any of the input bits are KnownOne, then the input couldn't be all // zeros, thus the result of the srl will always be zero. @@ -2270,7 +2270,7 @@ unsigned OpBits = MVT::getSizeInBits(Op.getValueType()); unsigned MidBits = MVT::getSizeInBits(N0.getValueType()); unsigned DestBits = MVT::getSizeInBits(VT); - unsigned NumSignBits = TLI.ComputeNumSignBits(Op); + unsigned NumSignBits = DAG.ComputeNumSignBits(Op); if (OpBits == DestBits) { // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign @@ -2634,7 +2634,7 @@ return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); // If the input is already sign extended, just drop the extension. - if (TLI.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1) + if (DAG.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1) return N0; // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 @@ -2644,7 +2644,7 @@ } // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. - if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1))) + if (DAG.MaskedValueIsZero(N0, 1ULL << (EVTBits-1))) return DAG.getZeroExtendInReg(N0, EVT); // fold operands of sext_in_reg based on knowledge that the top bits are not @@ -2666,7 +2666,7 @@ if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) { // We can turn this into an SRA iff the input to the SRL is already sign // extended enough. - unsigned InSignBits = TLI.ComputeNumSignBits(N0.getOperand(0)); + unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits) return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1)); } Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.499 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.500 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.499 Thu Jun 21 09:48:26 2007 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Jun 22 09:59:07 2007 @@ -1449,7 +1449,7 @@ // The top bits of the promoted condition are not necessarily zero, ensure // that the value is properly zero extended. - if (!TLI.MaskedValueIsZero(Tmp2, + if (!DAG.MaskedValueIsZero(Tmp2, MVT::getIntVTBitMask(Tmp2.getValueType())^1)) Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); break; @@ -2041,7 +2041,7 @@ case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. // Make sure the condition is either zero or one. - if (!TLI.MaskedValueIsZero(Tmp1, + if (!DAG.MaskedValueIsZero(Tmp1, MVT::getIntVTBitMask(Tmp1.getValueType())^1)) Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); break; @@ -4209,7 +4209,7 @@ // Okay, the shift amount isn't constant. However, if we can tell that it is // >= 32 or < 32, we can still simplify it, without knowing the actual value. uint64_t Mask = NVTBits, KnownZero, KnownOne; - TLI.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne); + DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne); // If we know that the high bit of the shift amount is one, then we can do // this as a couple of simple shifts. Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.408 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.409 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.408 Tue Jun 19 09:13:56 2007 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Fri Jun 22 09:59:07 2007 @@ -936,6 +936,552 @@ return SDOperand(); } +/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use +/// this predicate to simplify operations downstream. Mask is known to be zero +/// for bits that V cannot have. +bool SelectionDAG::MaskedValueIsZero(SDOperand Op, uint64_t Mask, + unsigned Depth) const { + // The masks are not wide enough to represent this type! Should use APInt. + if (Op.getValueType() == MVT::i128) + return false; + + uint64_t KnownZero, KnownOne; + ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); + assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); + return (KnownZero & Mask) == Mask; +} + +/// ComputeMaskedBits - Determine which of the bits specified in Mask are +/// known to be either zero or one and return them in the KnownZero/KnownOne +/// bitsets. This code only analyzes bits in Mask, in order to short-circuit +/// processing. +void SelectionDAG::ComputeMaskedBits(SDOperand Op, uint64_t Mask, + uint64_t &KnownZero, uint64_t &KnownOne, + unsigned Depth) const { + KnownZero = KnownOne = 0; // Don't know anything. + if (Depth == 6 || Mask == 0) + return; // Limit search depth. + + // The masks are not wide enough to represent this type! Should use APInt. + if (Op.getValueType() == MVT::i128) + return; + + uint64_t KnownZero2, KnownOne2; + + switch (Op.getOpcode()) { + case ISD::Constant: + // We know all of the bits for a constant! + KnownOne = cast(Op)->getValue() & Mask; + KnownZero = ~KnownOne & Mask; + return; + case ISD::AND: + // If either the LHS or the RHS are Zero, the result is zero. + ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); + Mask &= ~KnownZero; + ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); + assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); + assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); + + // Output known-1 bits are only known if set in both the LHS & RHS. + KnownOne &= KnownOne2; + // Output known-0 are known to be clear if zero in either the LHS | RHS. + KnownZero |= KnownZero2; + return; + case ISD::OR: + ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); + Mask &= ~KnownOne; + ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); + assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); + assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); + + // Output known-0 bits are only known if clear in both the LHS & RHS. + KnownZero &= KnownZero2; + // Output known-1 are known to be set if set in either the LHS | RHS. + KnownOne |= KnownOne2; + return; + case ISD::XOR: { + ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); + ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); + assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); + assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); + + // Output known-0 bits are known if clear or set in both the LHS & RHS. + uint64_t KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); + // Output known-1 are known to be set if set in only one of the LHS, RHS. + KnownOne = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); + KnownZero = KnownZeroOut; + return; + } + case ISD::SELECT: + ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero, KnownOne, Depth+1); + ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero2, KnownOne2, Depth+1); + assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); + assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); + + // Only known if known in both the LHS and RHS. + KnownOne &= KnownOne2; + KnownZero &= KnownZero2; + return; + case ISD::SELECT_CC: + ComputeMaskedBits(Op.getOperand(3), Mask, KnownZero, KnownOne, Depth+1); + ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero2, KnownOne2, Depth+1); + assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); + assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); + + // Only known if known in both the LHS and RHS. + KnownOne &= KnownOne2; + KnownZero &= KnownZero2; + return; + case ISD::SETCC: + // If we know the result of a setcc has the top bits zero, use this info. + if (TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) + KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL); + return; + case ISD::SHL: + // (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0 + if (ConstantSDNode *SA = dyn_cast(Op.getOperand(1))) { + ComputeMaskedBits(Op.getOperand(0), Mask >> SA->getValue(), + KnownZero, KnownOne, Depth+1); + assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); + KnownZero <<= SA->getValue(); + KnownOne <<= SA->getValue(); + KnownZero |= (1ULL << SA->getValue())-1; // low bits known zero. + } + return; + case ISD::SRL: + // (ushr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0 + if (ConstantSDNode *SA = dyn_cast(Op.getOperand(1))) { + MVT::ValueType VT = Op.getValueType(); + unsigned ShAmt = SA->getValue(); + + uint64_t TypeMask = MVT::getIntVTBitMask(VT); + ComputeMaskedBits(Op.getOperand(0), (Mask << ShAmt) & TypeMask, + KnownZero, KnownOne, Depth+1); + assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); + KnownZero &= TypeMask; + KnownOne &= TypeMask; + KnownZero >>= ShAmt; + KnownOne >>= ShAmt; + + uint64_t HighBits = (1ULL << ShAmt)-1; + HighBits <<= MVT::getSizeInBits(VT)-ShAmt; + KnownZero |= HighBits; // High bits known zero. + } + return; + case ISD::SRA: + if (ConstantSDNode *SA = dyn_cast(Op.getOperand(1))) { + MVT::ValueType VT = Op.getValueType(); + unsigned ShAmt = SA->getValue(); + + // Compute the new bits that are at the top now. + uint64_t TypeMask = MVT::getIntVTBitMask(VT); + + uint64_t InDemandedMask = (Mask << ShAmt) & TypeMask; + // If any of the demanded bits are produced by the sign extension, we also + // demand the input sign bit. + uint64_t HighBits = (1ULL << ShAmt)-1; + HighBits <<= MVT::getSizeInBits(VT) - ShAmt; + if (HighBits & Mask) + InDemandedMask |= MVT::getIntVTSignBit(VT); + + ComputeMaskedBits(Op.getOperand(0), InDemandedMask, KnownZero, KnownOne, + Depth+1); + assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); + KnownZero &= TypeMask; + KnownOne &= TypeMask; + KnownZero >>= ShAmt; + KnownOne >>= ShAmt; + + // Handle the sign bits. + uint64_t SignBit = MVT::getIntVTSignBit(VT); + SignBit >>= ShAmt; // Adjust to where it is now in the mask. + + if (KnownZero & SignBit) { + KnownZero |= HighBits; // New bits are known zero. + } else if (KnownOne & SignBit) { + KnownOne |= HighBits; // New bits are known one. + } + } + return; + case ISD::SIGN_EXTEND_INREG: { + MVT::ValueType EVT = cast(Op.getOperand(1))->getVT(); + + // Sign extension. Compute the demanded bits in the result that are not + // present in the input. + uint64_t NewBits = ~MVT::getIntVTBitMask(EVT) & Mask; + + uint64_t InSignBit = MVT::getIntVTSignBit(EVT); + int64_t InputDemandedBits = Mask & MVT::getIntVTBitMask(EVT); + + // If the sign extended bits are demanded, we know that the sign + // bit is demanded. + if (NewBits) + InputDemandedBits |= InSignBit; + + ComputeMaskedBits(Op.getOperand(0), InputDemandedBits, + KnownZero, KnownOne, Depth+1); + assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); + + // If the sign bit of the input is known set or clear, then we know the + // top bits of the result. + if (KnownZero & InSignBit) { // Input sign bit known clear + KnownZero |= NewBits; + KnownOne &= ~NewBits; + } else if (KnownOne & InSignBit) { // Input sign bit known set + KnownOne |= NewBits; + KnownZero &= ~NewBits; + } else { // Input sign bit unknown + KnownZero &= ~NewBits; + KnownOne &= ~NewBits; + } + return; + } + case ISD::CTTZ: + case ISD::CTLZ: + case ISD::CTPOP: { + MVT::ValueType VT = Op.getValueType(); + unsigned LowBits = Log2_32(MVT::getSizeInBits(VT))+1; + KnownZero = ~((1ULL << LowBits)-1) & MVT::getIntVTBitMask(VT); + KnownOne = 0; + return; + } + case ISD::LOAD: { + if (ISD::isZEXTLoad(Op.Val)) { + LoadSDNode *LD = cast(Op); + MVT::ValueType VT = LD->getLoadedVT(); + KnownZero |= ~MVT::getIntVTBitMask(VT) & Mask; + } + return; + } + case ISD::ZERO_EXTEND: { + uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType()); + uint64_t NewBits = (~InMask) & Mask; + ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero, + KnownOne, Depth+1); + KnownZero |= NewBits & Mask; + KnownOne &= ~NewBits; + return; + } + case ISD::SIGN_EXTEND: { + MVT::ValueType InVT = Op.getOperand(0).getValueType(); + unsigned InBits = MVT::getSizeInBits(InVT); + uint64_t InMask = MVT::getIntVTBitMask(InVT); + uint64_t InSignBit = 1ULL << (InBits-1); + uint64_t NewBits = (~InMask) & Mask; + uint64_t InDemandedBits = Mask & InMask; + + // If any of the sign extended bits are demanded, we know that the sign + // bit is demanded. + if (NewBits & Mask) + InDemandedBits |= InSignBit; + + ComputeMaskedBits(Op.getOperand(0), InDemandedBits, KnownZero, + KnownOne, Depth+1); + // If the sign bit is known zero or one, the top bits match. + if (KnownZero & InSignBit) { + KnownZero |= NewBits; + KnownOne &= ~NewBits; + } else if (KnownOne & InSignBit) { + KnownOne |= NewBits; + KnownZero &= ~NewBits; + } else { // Otherwise, top bits aren't known. + KnownOne &= ~NewBits; + KnownZero &= ~NewBits; + } + return; + } + case ISD::ANY_EXTEND: { + MVT::ValueType VT = Op.getOperand(0).getValueType(); + ComputeMaskedBits(Op.getOperand(0), Mask & MVT::getIntVTBitMask(VT), + KnownZero, KnownOne, Depth+1); + return; + } + case ISD::TRUNCATE: { + ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); + assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); + uint64_t OutMask = MVT::getIntVTBitMask(Op.getValueType()); + KnownZero &= OutMask; + KnownOne &= OutMask; + break; + } + case ISD::AssertZext: { + MVT::ValueType VT = cast(Op.getOperand(1))->getVT(); + uint64_t InMask = MVT::getIntVTBitMask(VT); + ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero, + KnownOne, Depth+1); + KnownZero |= (~InMask) & Mask; + return; + } + case ISD::ADD: { + // If either the LHS or the RHS are Zero, the result is zero. + ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); + ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); + assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); + assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); + + // Output known-0 bits are known if clear or set in both the low clear bits + // common to both LHS & RHS. For example, 8+(X<<3) is known to have the + // low 3 bits clear. + uint64_t KnownZeroOut = std::min(CountTrailingZeros_64(~KnownZero), + CountTrailingZeros_64(~KnownZero2)); + + KnownZero = (1ULL << KnownZeroOut) - 1; + KnownOne = 0; + return; + } + case ISD::SUB: { + ConstantSDNode *CLHS = dyn_cast(Op.getOperand(0)); + if (!CLHS) return; + + // We know that the top bits of C-X are clear if X contains less bits + // than C (i.e. no wrap-around can happen). For example, 20-X is + // positive if we can prove that X is >= 0 and < 16. + MVT::ValueType VT = CLHS->getValueType(0); + if ((CLHS->getValue() & MVT::getIntVTSignBit(VT)) == 0) { // sign bit clear + unsigned NLZ = CountLeadingZeros_64(CLHS->getValue()+1); + uint64_t MaskV = (1ULL << (63-NLZ))-1; // NLZ can't be 64 with no sign bit + MaskV = ~MaskV & MVT::getIntVTBitMask(VT); + ComputeMaskedBits(Op.getOperand(1), MaskV, KnownZero, KnownOne, Depth+1); + + // If all of the MaskV bits are known to be zero, then we know the output + // top bits are zero, because we now know that the output is from [0-C]. + if ((KnownZero & MaskV) == MaskV) { + unsigned NLZ2 = CountLeadingZeros_64(CLHS->getValue()); + KnownZero = ~((1ULL << (64-NLZ2))-1) & Mask; // Top bits known zero. + KnownOne = 0; // No one bits known. + } else { + KnownZero = KnownOne = 0; // Otherwise, nothing known. + } + } + return; + } + default: + // Allow the target to implement this method for its nodes. + if (Op.getOpcode() >= ISD::BUILTIN_OP_END) { + case ISD::INTRINSIC_WO_CHAIN: + case ISD::INTRINSIC_W_CHAIN: + case ISD::INTRINSIC_VOID: + TLI.computeMaskedBitsForTargetNode(Op, Mask, KnownZero, KnownOne, *this); + } + return; + } +} + +/// ComputeNumSignBits - Return the number of times the sign bit of the +/// register is replicated into the other bits. We know that at least 1 bit +/// is always equal to the sign bit (itself), but other cases can give us +/// information. For example, immediately after an "SRA X, 2", we know that +/// the top 3 bits are all equal to each other, so we return 3. +unsigned SelectionDAG::ComputeNumSignBits(SDOperand Op, unsigned Depth) const{ + MVT::ValueType VT = Op.getValueType(); + assert(MVT::isInteger(VT) && "Invalid VT!"); + unsigned VTBits = MVT::getSizeInBits(VT); + unsigned Tmp, Tmp2; + + if (Depth == 6) + return 1; // Limit search depth. + + switch (Op.getOpcode()) { + default: break; + case ISD::AssertSext: + Tmp = MVT::getSizeInBits(cast(Op.getOperand(1))->getVT()); + return VTBits-Tmp+1; + case ISD::AssertZext: + Tmp = MVT::getSizeInBits(cast(Op.getOperand(1))->getVT()); + return VTBits-Tmp; + + case ISD::Constant: { + uint64_t Val = cast(Op)->getValue(); + // If negative, invert the bits, then look at it. + if (Val & MVT::getIntVTSignBit(VT)) + Val = ~Val; + + // Shift the bits so they are the leading bits in the int64_t. + Val <<= 64-VTBits; + + // Return # leading zeros. We use 'min' here in case Val was zero before + // shifting. We don't want to return '64' as for an i32 "0". + return std::min(VTBits, CountLeadingZeros_64(Val)); + } + + case ISD::SIGN_EXTEND: + Tmp = VTBits-MVT::getSizeInBits(Op.getOperand(0).getValueType()); + return ComputeNumSignBits(Op.getOperand(0), Depth+1) + Tmp; + + case ISD::SIGN_EXTEND_INREG: + // Max of the input and what this extends. + Tmp = MVT::getSizeInBits(cast(Op.getOperand(1))->getVT()); + Tmp = VTBits-Tmp+1; + + Tmp2 = ComputeNumSignBits(Op.getOperand(0), Depth+1); + return std::max(Tmp, Tmp2); + + case ISD::SRA: + Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); + // SRA X, C -> adds C sign bits. + if (ConstantSDNode *C = dyn_cast(Op.getOperand(1))) { + Tmp += C->getValue(); + if (Tmp > VTBits) Tmp = VTBits; + } + return Tmp; + case ISD::SHL: + if (ConstantSDNode *C = dyn_cast(Op.getOperand(1))) { + // shl destroys sign bits. + Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); + if (C->getValue() >= VTBits || // Bad shift. + C->getValue() >= Tmp) break; // Shifted all sign bits out. + return Tmp - C->getValue(); + } + break; + case ISD::AND: + case ISD::OR: + case ISD::XOR: // NOT is handled here. + // Logical binary ops preserve the number of sign bits. + Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); + if (Tmp == 1) return 1; // Early out. + Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); + return std::min(Tmp, Tmp2); + + case ISD::SELECT: + Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); + if (Tmp == 1) return 1; // Early out. + Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); + return std::min(Tmp, Tmp2); + + case ISD::SETCC: + // If setcc returns 0/-1, all bits are sign bits. + if (TLI.getSetCCResultContents() == + TargetLowering::ZeroOrNegativeOneSetCCResult) + return VTBits; + break; + case ISD::ROTL: + case ISD::ROTR: + if (ConstantSDNode *C = dyn_cast(Op.getOperand(1))) { + unsigned RotAmt = C->getValue() & (VTBits-1); + + // Handle rotate right by N like a rotate left by 32-N. + if (Op.getOpcode() == ISD::ROTR) + RotAmt = (VTBits-RotAmt) & (VTBits-1); + + // If we aren't rotating out all of the known-in sign bits, return the + // number that are left. This handles rotl(sext(x), 1) for example. + Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); + if (Tmp > RotAmt+1) return Tmp-RotAmt; + } + break; + case ISD::ADD: + // Add can have at most one carry bit. Thus we know that the output + // is, at worst, one more bit than the inputs. + Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); + if (Tmp == 1) return 1; // Early out. + + // Special case decrementing a value (ADD X, -1): + if (ConstantSDNode *CRHS = dyn_cast(Op.getOperand(0))) + if (CRHS->isAllOnesValue()) { + uint64_t KnownZero, KnownOne; + uint64_t Mask = MVT::getIntVTBitMask(VT); + ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); + + // If the input is known to be 0 or 1, the output is 0/-1, which is all + // sign bits set. + if ((KnownZero|1) == Mask) + return VTBits; + + // If we are subtracting one from a positive number, there is no carry + // out of the result. + if (KnownZero & MVT::getIntVTSignBit(VT)) + return Tmp; + } + + Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); + if (Tmp2 == 1) return 1; + return std::min(Tmp, Tmp2)-1; + break; + + case ISD::SUB: + Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); + if (Tmp2 == 1) return 1; + + // Handle NEG. + if (ConstantSDNode *CLHS = dyn_cast(Op.getOperand(0))) + if (CLHS->getValue() == 0) { + uint64_t KnownZero, KnownOne; + uint64_t Mask = MVT::getIntVTBitMask(VT); + ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); + // If the input is known to be 0 or 1, the output is 0/-1, which is all + // sign bits set. + if ((KnownZero|1) == Mask) + return VTBits; + + // If the input is known to be positive (the sign bit is known clear), + // the output of the NEG has the same number of sign bits as the input. + if (KnownZero & MVT::getIntVTSignBit(VT)) + return Tmp2; + + // Otherwise, we treat this like a SUB. + } + + // Sub can have at most one carry bit. Thus we know that the output + // is, at worst, one more bit than the inputs. + Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); + if (Tmp == 1) return 1; // Early out. + return std::min(Tmp, Tmp2)-1; + break; + case ISD::TRUNCATE: + // FIXME: it's tricky to do anything useful for this, but it is an important + // case for targets like X86. + break; + } + + // Handle LOADX separately here. EXTLOAD case will fallthrough. + if (Op.getOpcode() == ISD::LOAD) { + LoadSDNode *LD = cast(Op); + unsigned ExtType = LD->getExtensionType(); + switch (ExtType) { + default: break; + case ISD::SEXTLOAD: // '17' bits known + Tmp = MVT::getSizeInBits(LD->getLoadedVT()); + return VTBits-Tmp+1; + case ISD::ZEXTLOAD: // '16' bits known + Tmp = MVT::getSizeInBits(LD->getLoadedVT()); + return VTBits-Tmp; + } + } + + // Allow the target to implement this method for its nodes. + if (Op.getOpcode() >= ISD::BUILTIN_OP_END || + Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || + Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || + Op.getOpcode() == ISD::INTRINSIC_VOID) { + unsigned NumBits = TLI.ComputeNumSignBitsForTargetNode(Op, Depth); + if (NumBits > 1) return NumBits; + } + + // Finally, if we can prove that the top bits of the result are 0's or 1's, + // use this information. + uint64_t KnownZero, KnownOne; + uint64_t Mask = MVT::getIntVTBitMask(VT); + ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); + + uint64_t SignBit = MVT::getIntVTSignBit(VT); + if (KnownZero & SignBit) { // SignBit is 0 + Mask = KnownZero; + } else if (KnownOne & SignBit) { // SignBit is 1; + Mask = KnownOne; + } else { + // Nothing known. + return 1; + } + + // Okay, we know that the sign bit in Mask is set. Use CLZ to determine + // the number of identical bits in the top of the input value. + Mask ^= ~0ULL; + Mask <<= 64-VTBits; + // Return # leading zeros. We use 'min' here in case Val was zero before + // shifting. We don't want to return '64' as for an i32 "0". + return std::min(VTBits, CountLeadingZeros_64(Mask)); +} + /// getNode - Gets or creates the specified node. /// Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.467 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.468 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.467 Thu Jun 21 09:42:22 2007 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Fri Jun 22 09:59:07 2007 @@ -5026,7 +5026,7 @@ // Otherwise, the DAG Combiner may have proven that the value coming in is // either already zero or is not demanded. Check for known zero input bits. uint64_t NeededMask = DesiredMask & ~ActualMask; - if (getTargetLowering().MaskedValueIsZero(LHS, NeededMask)) + if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) return true; // TODO: check to see if missing bits are just not demanded. @@ -5057,7 +5057,7 @@ uint64_t NeededMask = DesiredMask & ~ActualMask; uint64_t KnownZero, KnownOne; - getTargetLowering().ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); + CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne); // If all the missing bits in the or are already known to be set, match! if ((NeededMask & KnownOne) == NeededMask) Index: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp diff -u llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.121 llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.122 --- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.121 Thu Jun 21 09:48:26 2007 +++ llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp Fri Jun 22 09:59:07 2007 @@ -375,7 +375,7 @@ if (Depth != 0) { // If not at the root, Just compute the KnownZero/KnownOne bits to // simplify things downstream. - ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); + TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); return false; } // If this is the root being simplified, allow it to have multiple uses, @@ -404,8 +404,8 @@ // the RHS. if (ConstantSDNode *RHSC = dyn_cast(Op.getOperand(1))) { uint64_t LHSZero, LHSOne; - ComputeMaskedBits(Op.getOperand(0), DemandedMask, - LHSZero, LHSOne, Depth+1); + TLO.DAG.ComputeMaskedBits(Op.getOperand(0), DemandedMask, + LHSZero, LHSOne, Depth+1); // If the LHS already has zeros where RHSC does, this and is dead. if ((LHSZero & DemandedMask) == (~RHSC->getValue() & DemandedMask)) return TLO.CombineTo(Op, Op.getOperand(0)); @@ -862,7 +862,7 @@ case ISD::INTRINSIC_W_CHAIN: case ISD::INTRINSIC_VOID: // Just use ComputeMaskedBits to compute output bits. - ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); + TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); break; } @@ -874,337 +874,6 @@ return false; } -/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use -/// this predicate to simplify operations downstream. Mask is known to be zero -/// for bits that V cannot have. -bool TargetLowering::MaskedValueIsZero(SDOperand Op, uint64_t Mask, - unsigned Depth) const { - // The masks are not wide enough to represent this type! Should use APInt. - if (Op.getValueType() == MVT::i128) - return false; - - uint64_t KnownZero, KnownOne; - ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); - assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); - return (KnownZero & Mask) == Mask; -} - -/// ComputeMaskedBits - Determine which of the bits specified in Mask are -/// known to be either zero or one and return them in the KnownZero/KnownOne -/// bitsets. This code only analyzes bits in Mask, in order to short-circuit -/// processing. -void TargetLowering::ComputeMaskedBits(SDOperand Op, uint64_t Mask, - uint64_t &KnownZero, uint64_t &KnownOne, - unsigned Depth) const { - KnownZero = KnownOne = 0; // Don't know anything. - if (Depth == 6 || Mask == 0) - return; // Limit search depth. - - // The masks are not wide enough to represent this type! Should use APInt. - if (Op.getValueType() == MVT::i128) - return; - - uint64_t KnownZero2, KnownOne2; - - switch (Op.getOpcode()) { - case ISD::Constant: - // We know all of the bits for a constant! - KnownOne = cast(Op)->getValue() & Mask; - KnownZero = ~KnownOne & Mask; - return; - case ISD::AND: - // If either the LHS or the RHS are Zero, the result is zero. - ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); - Mask &= ~KnownZero; - ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); - assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); - assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); - - // Output known-1 bits are only known if set in both the LHS & RHS. - KnownOne &= KnownOne2; - // Output known-0 are known to be clear if zero in either the LHS | RHS. - KnownZero |= KnownZero2; - return; - case ISD::OR: - ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); - Mask &= ~KnownOne; - ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); - assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); - assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); - - // Output known-0 bits are only known if clear in both the LHS & RHS. - KnownZero &= KnownZero2; - // Output known-1 are known to be set if set in either the LHS | RHS. - KnownOne |= KnownOne2; - return; - case ISD::XOR: { - ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); - ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); - assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); - assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); - - // Output known-0 bits are known if clear or set in both the LHS & RHS. - uint64_t KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); - // Output known-1 are known to be set if set in only one of the LHS, RHS. - KnownOne = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); - KnownZero = KnownZeroOut; - return; - } - case ISD::SELECT: - ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero, KnownOne, Depth+1); - ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero2, KnownOne2, Depth+1); - assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); - assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); - - // Only known if known in both the LHS and RHS. - KnownOne &= KnownOne2; - KnownZero &= KnownZero2; - return; - case ISD::SELECT_CC: - ComputeMaskedBits(Op.getOperand(3), Mask, KnownZero, KnownOne, Depth+1); - ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero2, KnownOne2, Depth+1); - assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); - assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); - - // Only known if known in both the LHS and RHS. - KnownOne &= KnownOne2; - KnownZero &= KnownZero2; - return; - case ISD::SETCC: - // If we know the result of a setcc has the top bits zero, use this info. - if (getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) - KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL); - return; - case ISD::SHL: - // (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0 - if (ConstantSDNode *SA = dyn_cast(Op.getOperand(1))) { - ComputeMaskedBits(Op.getOperand(0), Mask >> SA->getValue(), - KnownZero, KnownOne, Depth+1); - assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); - KnownZero <<= SA->getValue(); - KnownOne <<= SA->getValue(); - KnownZero |= (1ULL << SA->getValue())-1; // low bits known zero. - } - return; - case ISD::SRL: - // (ushr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0 - if (ConstantSDNode *SA = dyn_cast(Op.getOperand(1))) { - MVT::ValueType VT = Op.getValueType(); - unsigned ShAmt = SA->getValue(); - - uint64_t TypeMask = MVT::getIntVTBitMask(VT); - ComputeMaskedBits(Op.getOperand(0), (Mask << ShAmt) & TypeMask, - KnownZero, KnownOne, Depth+1); - assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); - KnownZero &= TypeMask; - KnownOne &= TypeMask; - KnownZero >>= ShAmt; - KnownOne >>= ShAmt; - - uint64_t HighBits = (1ULL << ShAmt)-1; - HighBits <<= MVT::getSizeInBits(VT)-ShAmt; - KnownZero |= HighBits; // High bits known zero. - } - return; - case ISD::SRA: - if (ConstantSDNode *SA = dyn_cast(Op.getOperand(1))) { - MVT::ValueType VT = Op.getValueType(); - unsigned ShAmt = SA->getValue(); - - // Compute the new bits that are at the top now. - uint64_t TypeMask = MVT::getIntVTBitMask(VT); - - uint64_t InDemandedMask = (Mask << ShAmt) & TypeMask; - // If any of the demanded bits are produced by the sign extension, we also - // demand the input sign bit. - uint64_t HighBits = (1ULL << ShAmt)-1; - HighBits <<= MVT::getSizeInBits(VT) - ShAmt; - if (HighBits & Mask) - InDemandedMask |= MVT::getIntVTSignBit(VT); - - ComputeMaskedBits(Op.getOperand(0), InDemandedMask, KnownZero, KnownOne, - Depth+1); - assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); - KnownZero &= TypeMask; - KnownOne &= TypeMask; - KnownZero >>= ShAmt; - KnownOne >>= ShAmt; - - // Handle the sign bits. - uint64_t SignBit = MVT::getIntVTSignBit(VT); - SignBit >>= ShAmt; // Adjust to where it is now in the mask. - - if (KnownZero & SignBit) { - KnownZero |= HighBits; // New bits are known zero. - } else if (KnownOne & SignBit) { - KnownOne |= HighBits; // New bits are known one. - } - } - return; - case ISD::SIGN_EXTEND_INREG: { - MVT::ValueType EVT = cast(Op.getOperand(1))->getVT(); - - // Sign extension. Compute the demanded bits in the result that are not - // present in the input. - uint64_t NewBits = ~MVT::getIntVTBitMask(EVT) & Mask; - - uint64_t InSignBit = MVT::getIntVTSignBit(EVT); - int64_t InputDemandedBits = Mask & MVT::getIntVTBitMask(EVT); - - // If the sign extended bits are demanded, we know that the sign - // bit is demanded. - if (NewBits) - InputDemandedBits |= InSignBit; - - ComputeMaskedBits(Op.getOperand(0), InputDemandedBits, - KnownZero, KnownOne, Depth+1); - assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); - - // If the sign bit of the input is known set or clear, then we know the - // top bits of the result. - if (KnownZero & InSignBit) { // Input sign bit known clear - KnownZero |= NewBits; - KnownOne &= ~NewBits; - } else if (KnownOne & InSignBit) { // Input sign bit known set - KnownOne |= NewBits; - KnownZero &= ~NewBits; - } else { // Input sign bit unknown - KnownZero &= ~NewBits; - KnownOne &= ~NewBits; - } - return; - } - case ISD::CTTZ: - case ISD::CTLZ: - case ISD::CTPOP: { - MVT::ValueType VT = Op.getValueType(); - unsigned LowBits = Log2_32(MVT::getSizeInBits(VT))+1; - KnownZero = ~((1ULL << LowBits)-1) & MVT::getIntVTBitMask(VT); - KnownOne = 0; - return; - } - case ISD::LOAD: { - if (ISD::isZEXTLoad(Op.Val)) { - LoadSDNode *LD = cast(Op); - MVT::ValueType VT = LD->getLoadedVT(); - KnownZero |= ~MVT::getIntVTBitMask(VT) & Mask; - } - return; - } - case ISD::ZERO_EXTEND: { - uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType()); - uint64_t NewBits = (~InMask) & Mask; - ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero, - KnownOne, Depth+1); - KnownZero |= NewBits & Mask; - KnownOne &= ~NewBits; - return; - } - case ISD::SIGN_EXTEND: { - MVT::ValueType InVT = Op.getOperand(0).getValueType(); - unsigned InBits = MVT::getSizeInBits(InVT); - uint64_t InMask = MVT::getIntVTBitMask(InVT); - uint64_t InSignBit = 1ULL << (InBits-1); - uint64_t NewBits = (~InMask) & Mask; - uint64_t InDemandedBits = Mask & InMask; - - // If any of the sign extended bits are demanded, we know that the sign - // bit is demanded. - if (NewBits & Mask) - InDemandedBits |= InSignBit; - - ComputeMaskedBits(Op.getOperand(0), InDemandedBits, KnownZero, - KnownOne, Depth+1); - // If the sign bit is known zero or one, the top bits match. - if (KnownZero & InSignBit) { - KnownZero |= NewBits; - KnownOne &= ~NewBits; - } else if (KnownOne & InSignBit) { - KnownOne |= NewBits; - KnownZero &= ~NewBits; - } else { // Otherwise, top bits aren't known. - KnownOne &= ~NewBits; - KnownZero &= ~NewBits; - } - return; - } - case ISD::ANY_EXTEND: { - MVT::ValueType VT = Op.getOperand(0).getValueType(); - ComputeMaskedBits(Op.getOperand(0), Mask & MVT::getIntVTBitMask(VT), - KnownZero, KnownOne, Depth+1); - return; - } - case ISD::TRUNCATE: { - ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); - assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); - uint64_t OutMask = MVT::getIntVTBitMask(Op.getValueType()); - KnownZero &= OutMask; - KnownOne &= OutMask; - break; - } - case ISD::AssertZext: { - MVT::ValueType VT = cast(Op.getOperand(1))->getVT(); - uint64_t InMask = MVT::getIntVTBitMask(VT); - ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero, - KnownOne, Depth+1); - KnownZero |= (~InMask) & Mask; - return; - } - case ISD::ADD: { - // If either the LHS or the RHS are Zero, the result is zero. - ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); - ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); - assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); - assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); - - // Output known-0 bits are known if clear or set in both the low clear bits - // common to both LHS & RHS. For example, 8+(X<<3) is known to have the - // low 3 bits clear. - uint64_t KnownZeroOut = std::min(CountTrailingZeros_64(~KnownZero), - CountTrailingZeros_64(~KnownZero2)); - - KnownZero = (1ULL << KnownZeroOut) - 1; - KnownOne = 0; - return; - } - case ISD::SUB: { - ConstantSDNode *CLHS = dyn_cast(Op.getOperand(0)); - if (!CLHS) return; - - // We know that the top bits of C-X are clear if X contains less bits - // than C (i.e. no wrap-around can happen). For example, 20-X is - // positive if we can prove that X is >= 0 and < 16. - MVT::ValueType VT = CLHS->getValueType(0); - if ((CLHS->getValue() & MVT::getIntVTSignBit(VT)) == 0) { // sign bit clear - unsigned NLZ = CountLeadingZeros_64(CLHS->getValue()+1); - uint64_t MaskV = (1ULL << (63-NLZ))-1; // NLZ can't be 64 with no sign bit - MaskV = ~MaskV & MVT::getIntVTBitMask(VT); - ComputeMaskedBits(Op.getOperand(1), MaskV, KnownZero, KnownOne, Depth+1); - - // If all of the MaskV bits are known to be zero, then we know the output - // top bits are zero, because we now know that the output is from [0-C]. - if ((KnownZero & MaskV) == MaskV) { - unsigned NLZ2 = CountLeadingZeros_64(CLHS->getValue()); - KnownZero = ~((1ULL << (64-NLZ2))-1) & Mask; // Top bits known zero. - KnownOne = 0; // No one bits known. - } else { - KnownZero = KnownOne = 0; // Otherwise, nothing known. - } - } - return; - } - default: - // Allow the target to implement this method for its nodes. - if (Op.getOpcode() >= ISD::BUILTIN_OP_END) { - case ISD::INTRINSIC_WO_CHAIN: - case ISD::INTRINSIC_W_CHAIN: - case ISD::INTRINSIC_VOID: - computeMaskedBitsForTargetNode(Op, Mask, KnownZero, KnownOne); - } - return; - } -} - /// computeMaskedBitsForTargetNode - Determine which of the bits specified /// in Mask are known to be either zero or one and return them in the /// KnownZero/KnownOne bitsets. @@ -1212,6 +881,7 @@ uint64_t Mask, uint64_t &KnownZero, uint64_t &KnownOne, + const SelectionDAG &DAG, unsigned Depth) const { assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || @@ -1223,222 +893,6 @@ KnownOne = 0; } -/// ComputeNumSignBits - Return the number of times the sign bit of the -/// register is replicated into the other bits. We know that at least 1 bit -/// is always equal to the sign bit (itself), but other cases can give us -/// information. For example, immediately after an "SRA X, 2", we know that -/// the top 3 bits are all equal to each other, so we return 3. -unsigned TargetLowering::ComputeNumSignBits(SDOperand Op, unsigned Depth) const{ - MVT::ValueType VT = Op.getValueType(); - assert(MVT::isInteger(VT) && "Invalid VT!"); - unsigned VTBits = MVT::getSizeInBits(VT); - unsigned Tmp, Tmp2; - - if (Depth == 6) - return 1; // Limit search depth. - - switch (Op.getOpcode()) { - default: break; - case ISD::AssertSext: - Tmp = MVT::getSizeInBits(cast(Op.getOperand(1))->getVT()); - return VTBits-Tmp+1; - case ISD::AssertZext: - Tmp = MVT::getSizeInBits(cast(Op.getOperand(1))->getVT()); - return VTBits-Tmp; - - case ISD::Constant: { - uint64_t Val = cast(Op)->getValue(); - // If negative, invert the bits, then look at it. - if (Val & MVT::getIntVTSignBit(VT)) - Val = ~Val; - - // Shift the bits so they are the leading bits in the int64_t. - Val <<= 64-VTBits; - - // Return # leading zeros. We use 'min' here in case Val was zero before - // shifting. We don't want to return '64' as for an i32 "0". - return std::min(VTBits, CountLeadingZeros_64(Val)); - } - - case ISD::SIGN_EXTEND: - Tmp = VTBits-MVT::getSizeInBits(Op.getOperand(0).getValueType()); - return ComputeNumSignBits(Op.getOperand(0), Depth+1) + Tmp; - - case ISD::SIGN_EXTEND_INREG: - // Max of the input and what this extends. - Tmp = MVT::getSizeInBits(cast(Op.getOperand(1))->getVT()); - Tmp = VTBits-Tmp+1; - - Tmp2 = ComputeNumSignBits(Op.getOperand(0), Depth+1); - return std::max(Tmp, Tmp2); - - case ISD::SRA: - Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); - // SRA X, C -> adds C sign bits. - if (ConstantSDNode *C = dyn_cast(Op.getOperand(1))) { - Tmp += C->getValue(); - if (Tmp > VTBits) Tmp = VTBits; - } - return Tmp; - case ISD::SHL: - if (ConstantSDNode *C = dyn_cast(Op.getOperand(1))) { - // shl destroys sign bits. - Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); - if (C->getValue() >= VTBits || // Bad shift. - C->getValue() >= Tmp) break; // Shifted all sign bits out. - return Tmp - C->getValue(); - } - break; - case ISD::AND: - case ISD::OR: - case ISD::XOR: // NOT is handled here. - // Logical binary ops preserve the number of sign bits. - Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); - if (Tmp == 1) return 1; // Early out. - Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); - return std::min(Tmp, Tmp2); - - case ISD::SELECT: - Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); - if (Tmp == 1) return 1; // Early out. - Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); - return std::min(Tmp, Tmp2); - - case ISD::SETCC: - // If setcc returns 0/-1, all bits are sign bits. - if (getSetCCResultContents() == ZeroOrNegativeOneSetCCResult) - return VTBits; - break; - case ISD::ROTL: - case ISD::ROTR: - if (ConstantSDNode *C = dyn_cast(Op.getOperand(1))) { - unsigned RotAmt = C->getValue() & (VTBits-1); - - // Handle rotate right by N like a rotate left by 32-N. - if (Op.getOpcode() == ISD::ROTR) - RotAmt = (VTBits-RotAmt) & (VTBits-1); - - // If we aren't rotating out all of the known-in sign bits, return the - // number that are left. This handles rotl(sext(x), 1) for example. - Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); - if (Tmp > RotAmt+1) return Tmp-RotAmt; - } - break; - case ISD::ADD: - // Add can have at most one carry bit. Thus we know that the output - // is, at worst, one more bit than the inputs. - Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); - if (Tmp == 1) return 1; // Early out. - - // Special case decrementing a value (ADD X, -1): - if (ConstantSDNode *CRHS = dyn_cast(Op.getOperand(0))) - if (CRHS->isAllOnesValue()) { - uint64_t KnownZero, KnownOne; - uint64_t Mask = MVT::getIntVTBitMask(VT); - ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); - - // If the input is known to be 0 or 1, the output is 0/-1, which is all - // sign bits set. - if ((KnownZero|1) == Mask) - return VTBits; - - // If we are subtracting one from a positive number, there is no carry - // out of the result. - if (KnownZero & MVT::getIntVTSignBit(VT)) - return Tmp; - } - - Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); - if (Tmp2 == 1) return 1; - return std::min(Tmp, Tmp2)-1; - break; - - case ISD::SUB: - Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); - if (Tmp2 == 1) return 1; - - // Handle NEG. - if (ConstantSDNode *CLHS = dyn_cast(Op.getOperand(0))) - if (CLHS->getValue() == 0) { - uint64_t KnownZero, KnownOne; - uint64_t Mask = MVT::getIntVTBitMask(VT); - ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); - // If the input is known to be 0 or 1, the output is 0/-1, which is all - // sign bits set. - if ((KnownZero|1) == Mask) - return VTBits; - - // If the input is known to be positive (the sign bit is known clear), - // the output of the NEG has the same number of sign bits as the input. - if (KnownZero & MVT::getIntVTSignBit(VT)) - return Tmp2; - - // Otherwise, we treat this like a SUB. - } - - // Sub can have at most one carry bit. Thus we know that the output - // is, at worst, one more bit than the inputs. - Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); - if (Tmp == 1) return 1; // Early out. - return std::min(Tmp, Tmp2)-1; - break; - case ISD::TRUNCATE: - // FIXME: it's tricky to do anything useful for this, but it is an important - // case for targets like X86. - break; - } - - // Handle LOADX separately here. EXTLOAD case will fallthrough. - if (Op.getOpcode() == ISD::LOAD) { - LoadSDNode *LD = cast(Op); - unsigned ExtType = LD->getExtensionType(); - switch (ExtType) { - default: break; - case ISD::SEXTLOAD: // '17' bits known - Tmp = MVT::getSizeInBits(LD->getLoadedVT()); - return VTBits-Tmp+1; - case ISD::ZEXTLOAD: // '16' bits known - Tmp = MVT::getSizeInBits(LD->getLoadedVT()); - return VTBits-Tmp; - } - } - - // Allow the target to implement this method for its nodes. - if (Op.getOpcode() >= ISD::BUILTIN_OP_END || - Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || - Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || - Op.getOpcode() == ISD::INTRINSIC_VOID) { - unsigned NumBits = ComputeNumSignBitsForTargetNode(Op, Depth); - if (NumBits > 1) return NumBits; - } - - // Finally, if we can prove that the top bits of the result are 0's or 1's, - // use this information. - uint64_t KnownZero, KnownOne; - uint64_t Mask = MVT::getIntVTBitMask(VT); - ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); - - uint64_t SignBit = MVT::getIntVTSignBit(VT); - if (KnownZero & SignBit) { // SignBit is 0 - Mask = KnownZero; - } else if (KnownOne & SignBit) { // SignBit is 1; - Mask = KnownOne; - } else { - // Nothing known. - return 1; - } - - // Okay, we know that the sign bit in Mask is set. Use CLZ to determine - // the number of identical bits in the top of the input value. - Mask ^= ~0ULL; - Mask <<= 64-VTBits; - // Return # leading zeros. We use 'min' here in case Val was zero before - // shifting. We don't want to return '64' as for an i32 "0". - return std::min(VTBits, CountLeadingZeros_64(Mask)); -} - - - /// ComputeNumSignBitsForTargetNode - This method can be implemented by /// targets that want to expose additional information about sign bits to the /// DAG Combiner. @@ -1597,7 +1051,8 @@ cast(N0.getOperand(1))->getValue() == 1) { // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We // can only do this if the top bits are known zero. - if (MaskedValueIsZero(N0, MVT::getIntVTBitMask(N0.getValueType())-1)){ + if (DAG.MaskedValueIsZero(N0, + MVT::getIntVTBitMask(N0.getValueType())-1)){ // Okay, get the un-inverted input value. SDOperand Val; if (N0.getOpcode() == ISD::XOR) @@ -1761,7 +1216,7 @@ if (N0.getOpcode() == ISD::XOR) // If we know that all of the inverted bits are zero, don't bother // performing the inversion. - if (MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue())) + if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue())) return DAG.getSetCC(VT, N0.getOperand(0), DAG.getConstant(LHSR->getValue()^RHSC->getValue(), N0.getValueType()), Cond); From djg at cray.com Fri Jun 22 09:59:50 2007 From: djg at cray.com (Dan Gohman) Date: Fri, 22 Jun 2007 09:59:50 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/Target/TargetLowering.h Message-ID: <200706221459.l5MExoCh028698@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/Target: TargetLowering.h updated: 1.128 -> 1.129 --- Log message: Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from TargetLowering to SelectionDAG so that they have more convenient access to the current DAG, in preparation for the ValueType routines being changed from standalone functions to members of SelectionDAG for the pre-legalize vector type changes. --- Diffs of the changes: (+1 -21) TargetLowering.h | 22 +--------------------- 1 files changed, 1 insertion(+), 21 deletions(-) Index: llvm/include/llvm/Target/TargetLowering.h diff -u llvm/include/llvm/Target/TargetLowering.h:1.128 llvm/include/llvm/Target/TargetLowering.h:1.129 --- llvm/include/llvm/Target/TargetLowering.h:1.128 Thu Jun 21 09:42:22 2007 +++ llvm/include/llvm/Target/TargetLowering.h Fri Jun 22 09:59:07 2007 @@ -494,20 +494,6 @@ bool ShrinkDemandedConstant(SDOperand Op, uint64_t Demanded); }; - /// MaskedValueIsZero - Return true if 'Op & Mask' is known to be zero. We - /// use this predicate to simplify operations downstream. Op and Mask are - /// known to be the same type. - bool MaskedValueIsZero(SDOperand Op, uint64_t Mask, unsigned Depth = 0) - const; - - /// ComputeMaskedBits - Determine which of the bits specified in Mask are - /// known to be either zero or one and return them in the KnownZero/KnownOne - /// bitsets. This code only analyzes bits in Mask, in order to short-circuit - /// processing. Targets can implement the computeMaskedBitsForTargetNode - /// method, to allow target nodes to be understood. - void ComputeMaskedBits(SDOperand Op, uint64_t Mask, uint64_t &KnownZero, - uint64_t &KnownOne, unsigned Depth = 0) const; - /// SimplifyDemandedBits - Look at Op. At this point, we know that only the /// DemandedMask bits of the result of Op are ever used downstream. If we can /// use this information to simplify Op, create a new simplified DAG node and @@ -527,15 +513,9 @@ uint64_t Mask, uint64_t &KnownZero, uint64_t &KnownOne, + const SelectionDAG &DAG, unsigned Depth = 0) const; - /// ComputeNumSignBits - Return the number of times the sign bit of the - /// register is replicated into the other bits. We know that at least 1 bit - /// is always equal to the sign bit (itself), but other cases can give us - /// information. For example, immediately after an "SRA X, 2", we know that - /// the top 3 bits are all equal to each other, so we return 3. - unsigned ComputeNumSignBits(SDOperand Op, unsigned Depth = 0) const; - /// ComputeNumSignBitsForTargetNode - This method can be implemented by /// targets that want to expose additional information about sign bits to the /// DAG Combiner. From djg at cray.com Fri Jun 22 09:59:52 2007 From: djg at cray.com (Dan Gohman) Date: Fri, 22 Jun 2007 09:59:52 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp Message-ID: <200706221459.l5MExqeg028710@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/Sparc: SparcISelDAGToDAG.cpp updated: 1.122 -> 1.123 --- Log message: Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from TargetLowering to SelectionDAG so that they have more convenient access to the current DAG, in preparation for the ValueType routines being changed from standalone functions to members of SelectionDAG for the pre-legalize vector type changes. --- Diffs of the changes: (+6 -2) SparcISelDAGToDAG.cpp | 8 ++++++-- 1 files changed, 6 insertions(+), 2 deletions(-) Index: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp diff -u llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.122 llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.123 --- llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.122 Wed Mar 7 10:25:09 2007 +++ llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp Fri Jun 22 09:59:07 2007 @@ -112,6 +112,7 @@ uint64_t Mask, uint64_t &KnownZero, uint64_t &KnownOne, + const SelectionDAG &DAG, unsigned Depth = 0) const; virtual std::vector @@ -261,6 +262,7 @@ uint64_t Mask, uint64_t &KnownZero, uint64_t &KnownOne, + const SelectionDAG &DAG, unsigned Depth) const { uint64_t KnownZero2, KnownOne2; KnownZero = KnownOne = 0; // Don't know anything. @@ -269,8 +271,10 @@ default: break; case SPISD::SELECT_ICC: case SPISD::SELECT_FCC: - ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); - ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); + DAG.ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, + Depth+1); + DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, + Depth+1); assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); From djg at cray.com Fri Jun 22 09:59:52 2007 From: djg at cray.com (Dan Gohman) Date: Fri, 22 Jun 2007 09:59:52 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp X86ISelLowering.cpp X86ISelLowering.h Message-ID: <200706221459.l5MExqJ5028719@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/X86: X86ISelDAGToDAG.cpp updated: 1.149 -> 1.150 X86ISelLowering.cpp updated: 1.413 -> 1.414 X86ISelLowering.h updated: 1.100 -> 1.101 --- Log message: Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from TargetLowering to SelectionDAG so that they have more convenient access to the current DAG, in preparation for the ValueType routines being changed from standalone functions to members of SelectionDAG for the pre-legalize vector type changes. --- Diffs of the changes: (+3 -1) X86ISelDAGToDAG.cpp | 2 +- X86ISelLowering.cpp | 1 + X86ISelLowering.h | 1 + 3 files changed, 3 insertions(+), 1 deletion(-) Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.149 llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.150 --- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.149 Wed Apr 11 17:29:46 2007 +++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Fri Jun 22 09:59:07 2007 @@ -744,7 +744,7 @@ // On x86-64, the resultant disp must fit in 32-bits. isInt32(AM.Disp + CN->getSignExtended()) && // Check to see if the LHS & C is zero. - TLI.MaskedValueIsZero(N.getOperand(0), CN->getValue())) { + CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getValue())) { AM.Disp += CN->getValue(); return false; } Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.413 llvm/lib/Target/X86/X86ISelLowering.cpp:1.414 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.413 Mon Jun 18 19:13:10 2007 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Fri Jun 22 09:59:07 2007 @@ -4506,6 +4506,7 @@ uint64_t Mask, uint64_t &KnownZero, uint64_t &KnownOne, + const SelectionDAG &DAG, unsigned Depth) const { unsigned Opc = Op.getOpcode(); assert((Opc >= ISD::BUILTIN_OP_END || Index: llvm/lib/Target/X86/X86ISelLowering.h diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.100 llvm/lib/Target/X86/X86ISelLowering.h:1.101 --- llvm/lib/Target/X86/X86ISelLowering.h:1.100 Tue Apr 24 16:16:55 2007 +++ llvm/lib/Target/X86/X86ISelLowering.h Fri Jun 22 09:59:07 2007 @@ -319,6 +319,7 @@ uint64_t Mask, uint64_t &KnownZero, uint64_t &KnownOne, + const SelectionDAG &DAG, unsigned Depth = 0) const; SDOperand getReturnAddressFrameIndex(SelectionDAG &DAG); From djg at cray.com Fri Jun 22 09:59:53 2007 From: djg at cray.com (Dan Gohman) Date: Fri, 22 Jun 2007 09:59:53 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp PPCISelLowering.cpp PPCISelLowering.h Message-ID: <200706221459.l5MExrIo028731@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/PowerPC: PPCISelDAGToDAG.cpp updated: 1.230 -> 1.231 PPCISelLowering.cpp updated: 1.274 -> 1.275 PPCISelLowering.h updated: 1.65 -> 1.66 --- Log message: Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from TargetLowering to SelectionDAG so that they have more convenient access to the current DAG, in preparation for the ValueType routines being changed from standalone functions to members of SelectionDAG for the pre-legalize vector type changes. --- Diffs of the changes: (+8 -6) PPCISelDAGToDAG.cpp | 4 ++-- PPCISelLowering.cpp | 9 +++++---- PPCISelLowering.h | 1 + 3 files changed, 8 insertions(+), 6 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.230 llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.231 --- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.230 Mon Apr 2 00:59:42 2007 +++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Fri Jun 22 09:59:07 2007 @@ -424,8 +424,8 @@ SDOperand Op1 = N->getOperand(1); uint64_t LKZ, LKO, RKZ, RKO; - TLI.ComputeMaskedBits(Op0, 0xFFFFFFFFULL, LKZ, LKO); - TLI.ComputeMaskedBits(Op1, 0xFFFFFFFFULL, RKZ, RKO); + CurDAG->ComputeMaskedBits(Op0, 0xFFFFFFFFULL, LKZ, LKO); + CurDAG->ComputeMaskedBits(Op1, 0xFFFFFFFFULL, RKZ, RKO); unsigned TargetMask = LKZ; unsigned InsertMask = RKZ; Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.274 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.275 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.274 Tue Jun 19 00:46:06 2007 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Fri Jun 22 09:59:07 2007 @@ -688,10 +688,10 @@ // disjoint. uint64_t LHSKnownZero, LHSKnownOne; uint64_t RHSKnownZero, RHSKnownOne; - ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne); + DAG.ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne); if (LHSKnownZero) { - ComputeMaskedBits(N.getOperand(1), ~0U, RHSKnownZero, RHSKnownOne); + DAG.ComputeMaskedBits(N.getOperand(1), ~0U, RHSKnownZero, RHSKnownOne); // If all of the bits are known zero on the LHS or RHS, the add won't // carry. if ((LHSKnownZero | RHSKnownZero) == ~0U) { @@ -742,7 +742,7 @@ // (for better address arithmetic) if the LHS and RHS of the OR are // provably disjoint. uint64_t LHSKnownZero, LHSKnownOne; - ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne); + DAG.ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne); if ((LHSKnownZero|~(unsigned)imm) == ~0U) { // If all of the bits are known zero on the LHS or RHS, the add won't // carry. @@ -850,7 +850,7 @@ // (for better address arithmetic) if the LHS and RHS of the OR are // provably disjoint. uint64_t LHSKnownZero, LHSKnownOne; - ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne); + DAG.ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne); if ((LHSKnownZero|~(unsigned)imm) == ~0U) { // If all of the bits are known zero on the LHS or RHS, the add won't // carry. @@ -3235,6 +3235,7 @@ uint64_t Mask, uint64_t &KnownZero, uint64_t &KnownOne, + const SelectionDAG &DAG, unsigned Depth) const { KnownZero = 0; KnownOne = 0; Index: llvm/lib/Target/PowerPC/PPCISelLowering.h diff -u llvm/lib/Target/PowerPC/PPCISelLowering.h:1.65 llvm/lib/Target/PowerPC/PPCISelLowering.h:1.66 --- llvm/lib/Target/PowerPC/PPCISelLowering.h:1.65 Tue Apr 3 08:59:52 2007 +++ llvm/lib/Target/PowerPC/PPCISelLowering.h Fri Jun 22 09:59:07 2007 @@ -230,6 +230,7 @@ uint64_t Mask, uint64_t &KnownZero, uint64_t &KnownOne, + const SelectionDAG &DAG, unsigned Depth = 0) const; virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI, From djg at cray.com Fri Jun 22 09:59:53 2007 From: djg at cray.com (Dan Gohman) Date: Fri, 22 Jun 2007 09:59:53 -0500 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAG.h Message-ID: <200706221459.l5MExrdC028724@zion.cs.uiuc.edu> Changes in directory llvm/include/llvm/CodeGen: SelectionDAG.h updated: 1.150 -> 1.151 --- Log message: Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from TargetLowering to SelectionDAG so that they have more convenient access to the current DAG, in preparation for the ValueType routines being changed from standalone functions to members of SelectionDAG for the pre-legalize vector type changes. --- Diffs of the changes: (+23 -0) SelectionDAG.h | 23 +++++++++++++++++++++++ 1 files changed, 23 insertions(+) Index: llvm/include/llvm/CodeGen/SelectionDAG.h diff -u llvm/include/llvm/CodeGen/SelectionDAG.h:1.150 llvm/include/llvm/CodeGen/SelectionDAG.h:1.151 --- llvm/include/llvm/CodeGen/SelectionDAG.h:1.150 Sun Apr 22 18:15:29 2007 +++ llvm/include/llvm/CodeGen/SelectionDAG.h Fri Jun 22 09:59:07 2007 @@ -465,6 +465,29 @@ SDOperand FoldSetCC(MVT::ValueType VT, SDOperand N1, SDOperand N2, ISD::CondCode Cond); + /// MaskedValueIsZero - Return true if 'Op & Mask' is known to be zero. We + /// use this predicate to simplify operations downstream. Op and Mask are + /// known to be the same type. + bool MaskedValueIsZero(SDOperand Op, uint64_t Mask, unsigned Depth = 0) + const; + + /// ComputeMaskedBits - Determine which of the bits specified in Mask are + /// known to be either zero or one and return them in the KnownZero/KnownOne + /// bitsets. This code only analyzes bits in Mask, in order to short-circuit + /// processing. Targets can implement the computeMaskedBitsForTargetNode + /// method in the TargetLowering class to allow target nodes to be understood. + void ComputeMaskedBits(SDOperand Op, uint64_t Mask, uint64_t &KnownZero, + uint64_t &KnownOne, unsigned Depth = 0) const; + + /// ComputeNumSignBits - Return the number of times the sign bit of the + /// register is replicated into the other bits. We know that at least 1 bit + /// is always equal to the sign bit (itself), but other cases can give us + /// information. For example, immediately after an "SRA X, 2", we know that + /// the top 3 bits are all equal to each other, so we return 3. Targets can + /// implement the ComputeNumSignBitsForTarget method in the TargetLowering + /// class to allow target nodes to be understood. + unsigned ComputeNumSignBits(SDOperand Op, unsigned Depth = 0) const; + private: void RemoveNodeFromCSEMaps(SDNode *N); SDNode *AddNonLeafNodeToCSEMaps(SDNode *N); From djg at cray.com Fri Jun 22 09:59:50 2007 From: djg at cray.com (Dan Gohman) Date: Fri, 22 Jun 2007 09:59:50 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp ARMISelLowering.h Message-ID: <200706221459.l5MExoLq028705@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/ARM: ARMISelLowering.cpp updated: 1.58 -> 1.59 ARMISelLowering.h updated: 1.17 -> 1.18 --- Log message: Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from TargetLowering to SelectionDAG so that they have more convenient access to the current DAG, in preparation for the ValueType routines being changed from standalone functions to members of SelectionDAG for the pre-legalize vector type changes. --- Diffs of the changes: (+9 -8) ARMISelLowering.cpp | 16 ++++++++-------- ARMISelLowering.h | 1 + 2 files changed, 9 insertions(+), 8 deletions(-) Index: llvm/lib/Target/ARM/ARMISelLowering.cpp diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.58 llvm/lib/Target/ARM/ARMISelLowering.cpp:1.59 --- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.58 Tue Jun 19 18:55:02 2007 +++ llvm/lib/Target/ARM/ARMISelLowering.cpp Fri Jun 22 09:59:07 2007 @@ -1254,9 +1254,8 @@ SDOperand RL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(1), DAG.getConstant(0, MVT::i32)); - const TargetLowering &TL = DAG.getTargetLoweringInfo(); - unsigned LHSSB = TL.ComputeNumSignBits(Op.getOperand(0)); - unsigned RHSSB = TL.ComputeNumSignBits(Op.getOperand(1)); + unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0)); + unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1)); SDOperand Lo, Hi; // Figure out how to lower this multiply. @@ -1265,8 +1264,8 @@ Lo = DAG.getNode(ISD::MUL, MVT::i32, LL, RL); Hi = DAG.getNode(ISD::MULHS, MVT::i32, LL, RL); } else if (LHSSB == 32 && RHSSB == 32 && - TL.MaskedValueIsZero(Op.getOperand(0), 0xFFFFFFFF00000000ULL) && - TL.MaskedValueIsZero(Op.getOperand(1), 0xFFFFFFFF00000000ULL)) { + DAG.MaskedValueIsZero(Op.getOperand(0), 0xFFFFFFFF00000000ULL) && + DAG.MaskedValueIsZero(Op.getOperand(1), 0xFFFFFFFF00000000ULL)) { // If the inputs are zero extended, use mulhu. Lo = DAG.getNode(ISD::MUL, MVT::i32, LL, RL); Hi = DAG.getNode(ISD::MULHU, MVT::i32, LL, RL); @@ -1757,6 +1756,7 @@ uint64_t Mask, uint64_t &KnownZero, uint64_t &KnownOne, + const SelectionDAG &DAG, unsigned Depth) const { KnownZero = 0; KnownOne = 0; @@ -1764,12 +1764,12 @@ default: break; case ARMISD::CMOV: { // Bits are known zero/one if known on the LHS and RHS. - ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); + DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); if (KnownZero == 0 && KnownOne == 0) return; uint64_t KnownZeroRHS, KnownOneRHS; - ComputeMaskedBits(Op.getOperand(1), Mask, - KnownZeroRHS, KnownOneRHS, Depth+1); + DAG.ComputeMaskedBits(Op.getOperand(1), Mask, + KnownZeroRHS, KnownOneRHS, Depth+1); KnownZero &= KnownZeroRHS; KnownOne &= KnownOneRHS; return; Index: llvm/lib/Target/ARM/ARMISelLowering.h diff -u llvm/lib/Target/ARM/ARMISelLowering.h:1.17 llvm/lib/Target/ARM/ARMISelLowering.h:1.18 --- llvm/lib/Target/ARM/ARMISelLowering.h:1.17 Tue Jun 19 16:05:09 2007 +++ llvm/lib/Target/ARM/ARMISelLowering.h Fri Jun 22 09:59:07 2007 @@ -108,6 +108,7 @@ uint64_t Mask, uint64_t &KnownZero, uint64_t &KnownOne, + const SelectionDAG &DAG, unsigned Depth) const; ConstraintType getConstraintType(const std::string &Constraint) const; std::pair From resistor at mac.com Fri Jun 22 12:00:16 2007 From: resistor at mac.com (Owen Anderson) Date: Fri, 22 Jun 2007 12:00:16 -0500 Subject: [llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.td Message-ID: <200706221700.l5MH0GhB000406@zion.cs.uiuc.edu> Changes in directory llvm/lib/Target/ARM: ARMInstrInfo.td updated: 1.113 -> 1.114 --- Log message: Fix the build. --- Diffs of the changes: (+1 -1) ARMInstrInfo.td | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/ARM/ARMInstrInfo.td diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.113 llvm/lib/Target/ARM/ARMInstrInfo.td:1.114 --- llvm/lib/Target/ARM/ARMInstrInfo.td:1.113 Tue Jun 19 16:05:09 2007 +++ llvm/lib/Target/ARM/ARMInstrInfo.td Fri Jun 22 11:59:54 2007 @@ -152,7 +152,7 @@ // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits. def sext_16_node : PatLeaf<(i32 GPR:$a), [{ - return TLI.ComputeNumSignBits(SDOperand(N,0)) >= 17; + return CurDAG->ComputeNumSignBits(SDOperand(N,0)) >= 17; }]>; From resistor at mac.com Fri Jun 22 12:05:03 2007 From: resistor at mac.com (Owen Anderson) Date: Fri, 22 Jun 2007 12:05:03 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/GVNPRE.cpp Message-ID: <200706221705.l5MH53v8000588@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: GVNPRE.cpp updated: 1.52 -> 1.53 --- Log message: Remove some code that I was using for collecting performance information that should not have been committed. --- Diffs of the changes: (+18 -18) GVNPRE.cpp | 36 ++++++++++++++++++------------------ 1 files changed, 18 insertions(+), 18 deletions(-) Index: llvm/lib/Transforms/Scalar/GVNPRE.cpp diff -u llvm/lib/Transforms/Scalar/GVNPRE.cpp:1.52 llvm/lib/Transforms/Scalar/GVNPRE.cpp:1.53 --- llvm/lib/Transforms/Scalar/GVNPRE.cpp:1.52 Thu Jun 21 22:14:03 2007 +++ llvm/lib/Transforms/Scalar/GVNPRE.cpp Fri Jun 22 12:04:40 2007 @@ -367,47 +367,47 @@ // Helper fuctions // FIXME: eliminate or document these better - void dump(const SmallPtrSet& s) const __attribute__((noinline)); - void clean(SmallPtrSet& set) __attribute__((noinline)); + void dump(const SmallPtrSet& s) const; + void clean(SmallPtrSet& set); Value* find_leader(SmallPtrSet& vals, - uint32_t v) __attribute__((noinline)); - Value* phi_translate(Value* V, BasicBlock* pred, BasicBlock* succ) __attribute__((noinline)); + uint32_t v); + Value* phi_translate(Value* V, BasicBlock* pred, BasicBlock* succ); void phi_translate_set(SmallPtrSet& anticIn, BasicBlock* pred, - BasicBlock* succ, SmallPtrSet& out) __attribute__((noinline)); + BasicBlock* succ, SmallPtrSet& out); void topo_sort(SmallPtrSet& set, - std::vector& vec) __attribute__((noinline)); + std::vector& vec); - void cleanup() __attribute__((noinline)); - bool elimination() __attribute__((noinline)); + void cleanup(); + bool elimination(); - void val_insert(SmallPtrSet& s, Value* v) __attribute__((noinline)); - void val_replace(SmallPtrSet& s, Value* v) __attribute__((noinline)); - bool dependsOnInvoke(Value* V) __attribute__((noinline)); + void val_insert(SmallPtrSet& s, Value* v); + void val_replace(SmallPtrSet& s, Value* v); + bool dependsOnInvoke(Value* V); void buildsets_availout(BasicBlock::iterator I, SmallPtrSet& currAvail, SmallPtrSet& currPhis, SmallPtrSet& currExps, SmallPtrSet& currTemps, BitVector& availNumbers, - BitVector& expNumbers) __attribute__((noinline)); + BitVector& expNumbers); bool buildsets_anticout(BasicBlock* BB, SmallPtrSet& anticOut, - std::set& visited) __attribute__((noinline)); + std::set& visited); unsigned buildsets_anticin(BasicBlock* BB, SmallPtrSet& anticOut, SmallPtrSet& currExps, SmallPtrSet& currTemps, - std::set& visited) __attribute__((noinline)); - unsigned buildsets(Function& F) __attribute__((noinline)); + std::set& visited); + unsigned buildsets(Function& F); void insertion_pre(Value* e, BasicBlock* BB, std::map& avail, - SmallPtrSet& new_set) __attribute__((noinline)); + SmallPtrSet& new_set); unsigned insertion_mergepoint(std::vector& workList, df_iterator& D, - SmallPtrSet& new_set) __attribute__((noinline)); - bool insertion(Function& F) __attribute__((noinline)); + SmallPtrSet& new_set); + bool insertion(Function& F); }; From clattner at apple.com Fri Jun 22 12:05:06 2007 From: clattner at apple.com (Chris Lattner) Date: Fri, 22 Jun 2007 10:05:06 -0700 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp TargetLowering.cpp In-Reply-To: <200706221459.l5MExji1028691@zion.cs.uiuc.edu> References: <200706221459.l5MExji1028691@zion.cs.uiuc.edu> Message-ID: <6567C84E-6B8F-4610-A9CF-4692F19F861B@apple.com> On Jun 22, 2007, at 7:59 AM, Dan Gohman wrote: > Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from > TargetLowering to SelectionDAG so that they have more convenient > access to the current DAG, in preparation for the ValueType routines > being changed from standalone functions to members of SelectionDAG for > the pre-legalize vector type changes. Ah, that's also a much more logical place for them anyway. They originally started out in DAGCombine, this is their third home :). Thanks Dan, -Chris From clattner at apple.com Fri Jun 22 12:09:58 2007 From: clattner at apple.com (Chris Lattner) Date: Fri, 22 Jun 2007 10:09:58 -0700 Subject: [llvm-commits] CVS: llvm/lib/Target/X86/X86InstrFPStack.td X86InstrInfo.cpp X86InstrInfo.h X86InstrInfo.td X86InstrMMX.td X86InstrSSE.td In-Reply-To: <20070621215621.GR5693@village.us.cray.com> References: <20070621215621.GR5693@village.us.cray.com> Message-ID: <74E967A1-557B-4774-AB85-1614C412DDCF@apple.com> >> How about this proposal (Obviously feel free to pick better names for >> these things): >> >> 1. Reintroduce the 'isremat-able' flag, set it to true for all the >> instructions that are *potentially* rematerializable. >> 2. Add a virtual target hook that can override the flag: >> "TII::isReallyRematerializable(Machineinstr*)". >> 3. Introduce a new non-virtual method: >> bool TII::isRematerializable(Machineinstr *MI) { >> return MI->flags->isrematable && isReallyRematerializable(MI); >> } > > I tried this, and got circular dependencies between libLLVMAnalysis.a, > libLLVMTarget.a, and libLLVMCodeGen.a. I think it's because the actual > code for 3. uses MachineInstr::getOpcode. It shouldn't need to, it can be an inline function that calls: MI->getInstrDescriptor()->isrematable() MachineInstrs have a direct pointer to their TargetInstrDescriptor record. They actually don't hold their opcode :) >> I'm sorry I didn't look at your patch when you asked for comments, >> but does this proposal sound sane? > > *shrug*. Adding isReMaterializable flags to all the load > instructions in > the X86 files isn't unambiguously prettier though. But I've already > strayed from my tangent here :-}. True, in the future we can add some smarts to tblgen... we already know what the loads are (from the patterns), so tblgen could do this automatically for every target. Unfortunately, the tblgen code that interprets the patterns is built into the DAGISelEmitter.cpp file. Someday we should refactor the code for interpreting the patterns out from the code that emits the isel. That way, other tblgen backends could use the patterns to autogenerate things (e.g. the "fold load into instruction" code). -Chris From resistor at mac.com Fri Jun 22 13:27:27 2007 From: resistor at mac.com (Owen Anderson) Date: Fri, 22 Jun 2007 13:27:27 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/GVNPRE.cpp Message-ID: <200706221827.l5MIRRkp002247@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: GVNPRE.cpp updated: 1.53 -> 1.54 --- Log message: Perform fewer set insertions while calculating ANTIC_IN. This reduces the amount of time to optimize 403.gcc from 21.9s to 18.2s. --- Diffs of the changes: (+31 -40) GVNPRE.cpp | 71 ++++++++++++++++++++++++++----------------------------------- 1 files changed, 31 insertions(+), 40 deletions(-) Index: llvm/lib/Transforms/Scalar/GVNPRE.cpp diff -u llvm/lib/Transforms/Scalar/GVNPRE.cpp:1.53 llvm/lib/Transforms/Scalar/GVNPRE.cpp:1.54 --- llvm/lib/Transforms/Scalar/GVNPRE.cpp:1.53 Fri Jun 22 12:04:40 2007 +++ llvm/lib/Transforms/Scalar/GVNPRE.cpp Fri Jun 22 13:27:04 2007 @@ -818,20 +818,20 @@ availNumbers.resize(VN.size()); if (isa(leftValue)) - if (!expNumbers.test(VN.lookup(leftValue)-1)) { + if (!expNumbers.test(VN.lookup(leftValue))) { currExps.insert(leftValue); - expNumbers.set(VN.lookup(leftValue)-1); + expNumbers.set(VN.lookup(leftValue)); } if (isa(rightValue)) - if (!expNumbers.test(VN.lookup(rightValue)-1)) { + if (!expNumbers.test(VN.lookup(rightValue))) { currExps.insert(rightValue); - expNumbers.set(VN.lookup(rightValue)-1); + expNumbers.set(VN.lookup(rightValue)); } - if (!expNumbers.test(VN.lookup(BO)-1)) { + if (!expNumbers.test(VN.lookup(BO))) { currExps.insert(BO); - expNumbers.set(num-1); + expNumbers.set(num); } // Handle cmp ops... @@ -846,19 +846,19 @@ availNumbers.resize(VN.size()); if (isa(leftValue)) - if (!expNumbers.test(VN.lookup(leftValue)-1)) { + if (!expNumbers.test(VN.lookup(leftValue))) { currExps.insert(leftValue); - expNumbers.set(VN.lookup(leftValue)-1); + expNumbers.set(VN.lookup(leftValue)); } if (isa(rightValue)) - if (!expNumbers.test(VN.lookup(rightValue)-1)) { + if (!expNumbers.test(VN.lookup(rightValue))) { currExps.insert(rightValue); - expNumbers.set(VN.lookup(rightValue)-1); + expNumbers.set(VN.lookup(rightValue)); } - if (!expNumbers.test(VN.lookup(C)-1)) { + if (!expNumbers.test(VN.lookup(C))) { currExps.insert(C); - expNumbers.set(num-1); + expNumbers.set(num); } // Handle unsupported ops @@ -871,9 +871,9 @@ } if (!I->isTerminator()) - if (!availNumbers.test(VN.lookup(I)-1)) { + if (!availNumbers.test(VN.lookup(I))) { currAvail.insert(I); - availNumbers.set(VN.lookup(I)-1); + availNumbers.set(VN.lookup(I)); } } @@ -921,45 +921,36 @@ SmallPtrSet& currTemps, std::set& visited) { SmallPtrSet& anticIn = anticipatedIn[BB]; - SmallPtrSet old (anticIn.begin(), anticIn.end()); + unsigned old = anticIn.size(); bool defer = buildsets_anticout(BB, anticOut, visited); if (defer) return 0; - - SmallPtrSet S; - for (SmallPtrSet::iterator I = anticOut.begin(), - E = anticOut.end(); I != E; ++I) - if (currTemps.count(*I) == 0) - S.insert(*I); anticIn.clear(); + BitVector numbers(VN.size()); + for (SmallPtrSet::iterator I = anticOut.begin(), + E = anticOut.end(); I != E; ++I) { + anticIn.insert(*I); + numbers.set(VN.lookup_or_add(*I)); + } for (SmallPtrSet::iterator I = currExps.begin(), - E = currExps.end(); I != E; ++I) - if (currTemps.count(*I) == 0) + E = currExps.end(); I != E; ++I) { + if (!numbers.test(VN.lookup_or_add(*I))) { anticIn.insert(*I); + numbers.set(VN.lookup(*I)); + } + } + + for (SmallPtrSet::iterator I = currTemps.begin(), + E = currTemps.end(); I != E; ++I) + anticIn.erase(*I); - BitVector numbers(VN.size()); - for (SmallPtrSet::iterator I = anticIn.begin(), - E = anticIn.end(); I != E; ++I) - numbers.set(VN.lookup(*I)-1); - for (SmallPtrSet::iterator I = S.begin(), E = S.end(); - I != E; ++I) { - // For non-opaque values, we should already have a value numbering. - // However, for opaques, such as constants within PHI nodes, it is - // possible that they have not yet received a number. Make sure they do - // so now. - if (!isa(*I) && !isa(*I)) - VN.lookup_or_add(*I); - if (!numbers.test(VN.lookup(*I)-1)) - anticIn.insert(*I); - } - clean(anticIn); anticOut.clear(); - if (old.size() != anticIn.size()) + if (old != anticIn.size()) return 2; else return 1; From dpatel at apple.com Fri Jun 22 15:28:03 2007 From: dpatel at apple.com (dpatel at apple.com) Date: Fri, 22 Jun 2007 13:28:03 -0700 (PDT) Subject: [llvm-commits] [128742] Fix warning. Message-ID: <20070622202803.3E833A3C1333@src> Revision: 128742 Author: dpatel Date: 2007-06-22 13:28:02 -0700 (Fri, 22 Jun 2007) Log Message: ----------- Fix warning. Modified Paths: -------------- apple-local/branches/llvm/gcc/c-lex.c Modified: apple-local/branches/llvm/gcc/c-lex.c =================================================================== --- apple-local/branches/llvm/gcc/c-lex.c 2007-06-22 17:28:14 UTC (rev 128741) +++ apple-local/branches/llvm/gcc/c-lex.c 2007-06-22 20:28:02 UTC (rev 128742) @@ -826,7 +826,7 @@ my_cpp_num_sign_extend (cpp_num num, size_t precision) { if (num.high) - printf("%lu\n", num.high); + printf("%lu\n", (long unsigned int) num.high); if (!num.unsignedp) { if (precision > PART_PRECISION) From resistor at mac.com Fri Jun 22 16:31:41 2007 From: resistor at mac.com (Owen Anderson) Date: Fri, 22 Jun 2007 16:31:41 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/GVNPRE.cpp Message-ID: <200706222131.l5MLVfHm006677@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: GVNPRE.cpp updated: 1.54 -> 1.55 --- Log message: Rework topo_sort so eliminate some behavior that scaled terribly. This reduces the time to optimize 403.gcc from 18.2s to 17.5s, and has an even larger effect on larger testcases. --- Diffs of the changes: (+40 -57) GVNPRE.cpp | 97 +++++++++++++++++++++++++------------------------------------ 1 files changed, 40 insertions(+), 57 deletions(-) Index: llvm/lib/Transforms/Scalar/GVNPRE.cpp diff -u llvm/lib/Transforms/Scalar/GVNPRE.cpp:1.54 llvm/lib/Transforms/Scalar/GVNPRE.cpp:1.55 --- llvm/lib/Transforms/Scalar/GVNPRE.cpp:1.54 Fri Jun 22 13:27:04 2007 +++ llvm/lib/Transforms/Scalar/GVNPRE.cpp Fri Jun 22 16:31:16 2007 @@ -650,71 +650,54 @@ /// topo_sort - Given a set of values, sort them by topological /// order into the provided vector. void GVNPRE::topo_sort(SmallPtrSet& set, std::vector& vec) { - SmallPtrSet toErase; + SmallPtrSet visited; + std::vector stack; for (SmallPtrSet::iterator I = set.begin(), E = set.end(); I != E; ++I) { - if (BinaryOperator* BO = dyn_cast(*I)) - for (SmallPtrSet::iterator SI = set.begin(); SI != E; ++SI) { - if (VN.lookup(BO->getOperand(0)) == VN.lookup(*SI) || - VN.lookup(BO->getOperand(1)) == VN.lookup(*SI)) { - toErase.insert(*SI); + if (visited.count(*I) == 0) + stack.push_back(*I); + + while (!stack.empty()) { + Value* e = stack.back(); + + if (BinaryOperator* BO = dyn_cast(e)) { + Value* l = find_leader(set, VN.lookup(BO->getOperand(0))); + Value* r = find_leader(set, VN.lookup(BO->getOperand(1))); + + if (l != 0 && isa(l) && + visited.count(l) == 0) + stack.push_back(l); + else if (r != 0 && isa(r) && + visited.count(r) == 0) + stack.push_back(r); + else { + vec.push_back(e); + visited.insert(e); + stack.pop_back(); } - } - else if (CmpInst* C = dyn_cast(*I)) - for (SmallPtrSet::iterator SI = set.begin(); SI != E; ++SI) { - if (VN.lookup(C->getOperand(0)) == VN.lookup(*SI) || - VN.lookup(C->getOperand(1)) == VN.lookup(*SI)) { - toErase.insert(*SI); + } else if (CmpInst* C = dyn_cast(e)) { + Value* l = find_leader(set, VN.lookup(C->getOperand(0))); + Value* r = find_leader(set, VN.lookup(C->getOperand(1))); + + if (l != 0 && isa(l) && + visited.count(l) == 0) + stack.push_back(l); + else if (r != 0 && isa(r) && + visited.count(r) == 0) + stack.push_back(r); + else { + vec.push_back(e); + visited.insert(e); + stack.pop_back(); } - } - } - - std::vector Q; - for (SmallPtrSet::iterator I = set.begin(), E = set.end(); - I != E; ++I) { - if (toErase.count(*I) == 0) - Q.push_back(*I); - } - - SmallPtrSet visited; - while (!Q.empty()) { - Value* e = Q.back(); - - if (BinaryOperator* BO = dyn_cast(e)) { - Value* l = find_leader(set, VN.lookup(BO->getOperand(0))); - Value* r = find_leader(set, VN.lookup(BO->getOperand(1))); - - if (l != 0 && isa(l) && - visited.count(l) == 0) - Q.push_back(l); - else if (r != 0 && isa(r) && - visited.count(r) == 0) - Q.push_back(r); - else { - vec.push_back(e); + } else { visited.insert(e); - Q.pop_back(); - } - } else if (CmpInst* C = dyn_cast(e)) { - Value* l = find_leader(set, VN.lookup(C->getOperand(0))); - Value* r = find_leader(set, VN.lookup(C->getOperand(1))); - - if (l != 0 && isa(l) && - visited.count(l) == 0) - Q.push_back(l); - else if (r != 0 && isa(r) && - visited.count(r) == 0) - Q.push_back(r); - else { vec.push_back(e); - visited.insert(e); - Q.pop_back(); + stack.pop_back(); } - } else { - visited.insert(e); - vec.push_back(e); - Q.pop_back(); } + + stack.clear(); } } From nicholas at mxc.ca Sat Jun 23 23:36:42 2007 From: nicholas at mxc.ca (Nick Lewycky) Date: Sat, 23 Jun 2007 23:36:42 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/PredicateSimplifier.cpp Message-ID: <200706240436.l5O4ag1N020264@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: PredicateSimplifier.cpp updated: 1.78 -> 1.79 --- Log message: Remove use of ETForest. Also cleaned up issues around unreachable basic blocks, and optimizing within one basic block. --- Diffs of the changes: (+326 -156) PredicateSimplifier.cpp | 482 ++++++++++++++++++++++++++++++++---------------- 1 files changed, 326 insertions(+), 156 deletions(-) Index: llvm/lib/Transforms/Scalar/PredicateSimplifier.cpp diff -u llvm/lib/Transforms/Scalar/PredicateSimplifier.cpp:1.78 llvm/lib/Transforms/Scalar/PredicateSimplifier.cpp:1.79 --- llvm/lib/Transforms/Scalar/PredicateSimplifier.cpp:1.78 Mon Jun 4 18:52:59 2007 +++ llvm/lib/Transforms/Scalar/PredicateSimplifier.cpp Sat Jun 23 23:36:20 2007 @@ -92,7 +92,6 @@ #include "llvm/ADT/Statistic.h" #include "llvm/ADT/STLExtras.h" #include "llvm/Analysis/Dominators.h" -#include "llvm/Analysis/ET-Forest.h" #include "llvm/Support/CFG.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/ConstantRange.h" @@ -103,6 +102,7 @@ #include #include #include +#include using namespace llvm; STATISTIC(NumVarsReplaced, "Number of argument substitutions"); @@ -112,6 +112,186 @@ STATISTIC(NumSnuggle , "Number of comparisons snuggled"); namespace { + class DomTreeDFS { + public: + class Node { + friend class DomTreeDFS; + public: + typedef std::vector::iterator iterator; + typedef std::vector::const_iterator const_iterator; + + unsigned getDFSNumIn() const { return DFSin; } + unsigned getDFSNumOut() const { return DFSout; } + + BasicBlock *getBlock() const { return BB; } + + iterator begin() { return Children.begin(); } + iterator end() { return Children.end(); } + + const_iterator begin() const { return Children.begin(); } + const_iterator end() const { return Children.end(); } + + bool dominates(const Node *N) const { + return DFSin <= N->DFSin && DFSout >= N->DFSout; + } + + bool DominatedBy(const Node *N) const { + return N->dominates(this); + } + + /// Sorts by the number of descendants. With this, you can iterate + /// through a sorted list and the first matching entry is the most + /// specific match for your basic block. The order provided is stable; + /// DomTreeDFS::Nodes with the same number of descendants are sorted by + /// DFS in number. + bool operator<(const Node &N) const { + unsigned spread = DFSout - DFSin; + unsigned N_spread = N.DFSout - N.DFSin; + if (spread == N_spread) return DFSin < N.DFSin; + else return DFSout - DFSin < N.DFSout - N.DFSin; + } + bool operator>(const Node &N) const { return N < *this; } + + private: + unsigned DFSin, DFSout; + BasicBlock *BB; + + std::vector Children; + }; + + // XXX: this may be slow. Instead of using "new" for each node, consider + // putting them in a vector to keep them contiguous. + explicit DomTreeDFS(DominatorTree *DT) { + std::stack > S; + + Entry = new Node; + Entry->BB = DT->getRootNode()->getBlock(); + S.push(std::make_pair(Entry, DT->getRootNode())); + + NodeMap[Entry->BB] = Entry; + + while (!S.empty()) { + std::pair &Pair = S.top(); + Node *N = Pair.first; + DomTreeNode *DTNode = Pair.second; + S.pop(); + + for (DomTreeNode::iterator I = DTNode->begin(), E = DTNode->end(); + I != E; ++I) { + Node *NewNode = new Node; + NewNode->BB = (*I)->getBlock(); + N->Children.push_back(NewNode); + S.push(std::make_pair(NewNode, *I)); + + NodeMap[NewNode->BB] = NewNode; + } + } + + renumber(); + +#ifndef NDEBUG + DEBUG(dump()); +#endif + } + +#ifndef NDEBUG + virtual +#endif + ~DomTreeDFS() { + std::stack S; + + S.push(Entry); + while (!S.empty()) { + Node *N = S.top(); S.pop(); + + for (Node::iterator I = N->begin(), E = N->end(); I != E; ++I) + S.push(*I); + + delete N; + } + } + + Node *getRootNode() const { return Entry; } + + Node *getNodeForBlock(BasicBlock *BB) const { + if (!NodeMap.count(BB)) return 0; + else return const_cast(this)->NodeMap[BB]; + } + + bool dominates(Instruction *I1, Instruction *I2) { + BasicBlock *BB1 = I1->getParent(), + *BB2 = I2->getParent(); + if (BB1 == BB2) { + if (isa(I1)) return false; + if (isa(I2)) return true; + if ( isa(I1) && !isa(I2)) return true; + if (!isa(I1) && isa(I2)) return false; + + for (BasicBlock::const_iterator I = BB2->begin(), E = BB2->end(); + I != E; ++I) { + if (&*I == I1) return true; + else if (&*I == I2) return false; + } + assert(!"Instructions not found in parent BasicBlock?"); + } else { + Node *Node1 = getNodeForBlock(BB1), + *Node2 = getNodeForBlock(BB2); + if (!Node1 || !Node2) return false; + return Node1->dominates(Node2); + } + } + private: + void renumber() { + std::stack > S; + unsigned n = 0; + + Entry->DFSin = ++n; + S.push(std::make_pair(Entry, Entry->begin())); + + while (!S.empty()) { + std::pair &Pair = S.top(); + Node *N = Pair.first; + Node::iterator &I = Pair.second; + + if (I == N->end()) { + N->DFSout = ++n; + S.pop(); + } else { + Node *Next = *I++; + Next->DFSin = ++n; + S.push(std::make_pair(Next, Next->begin())); + } + } + } + +#ifndef NDEBUG + virtual void dump() const { + dump(*cerr.stream()); + } + + void dump(std::ostream &os) const { + os << "Predicate simplifier DomTreeDFS: \n"; + dump(Entry, 0, os); + os << "\n\n"; + } + + void dump(Node *N, int depth, std::ostream &os) const { + ++depth; + for (int i = 0; i < depth; ++i) { os << " "; } + os << "[" << depth << "] "; + + os << N->getBlock()->getName() << " (" << N->getDFSNumIn() + << ", " << N->getDFSNumOut() << ")\n"; + + for (Node::iterator I = N->begin(), E = N->end(); I != E; ++I) + dump(*I, depth, os); + } +#endif + + Node *Entry; + std::map NodeMap; + }; + // SLT SGT ULT UGT EQ // 0 1 0 1 0 -- GT 10 // 0 1 0 1 1 -- GE 11 @@ -181,20 +361,6 @@ return Rev; } - /// This is a StrictWeakOrdering predicate that sorts ETNodes by how many - /// descendants they have. With this, you can iterate through a list sorted - /// by this operation and the first matching entry is the most specific - /// match for your basic block. The order provided is stable; ETNodes with - /// the same number of children are sorted by pointer address. - struct VISIBILITY_HIDDEN OrderByDominance { - bool operator()(const ETNode *LHS, const ETNode *RHS) const { - unsigned LHS_spread = LHS->getDFSNumOut() - LHS->getDFSNumIn(); - unsigned RHS_spread = RHS->getDFSNumOut() - RHS->getDFSNumIn(); - if (LHS_spread != RHS_spread) return LHS_spread < RHS_spread; - else return LHS < RHS; - } - }; - /// The InequalityGraph stores the relationships between values. /// Each Value in the graph is assigned to a Node. Nodes are pointer /// comparable for equality. The caller is expected to maintain the logical @@ -203,35 +369,37 @@ /// The InequalityGraph class may invalidate Node*s after any mutator call. /// @brief The InequalityGraph stores the relationships between values. class VISIBILITY_HIDDEN InequalityGraph { - ETNode *TreeRoot; + DomTreeDFS::Node *TreeRoot; InequalityGraph(); // DO NOT IMPLEMENT InequalityGraph(InequalityGraph &); // DO NOT IMPLEMENT public: - explicit InequalityGraph(ETNode *TreeRoot) : TreeRoot(TreeRoot) {} + explicit InequalityGraph(DomTreeDFS::Node *TreeRoot) : TreeRoot(TreeRoot){} class Node; /// An Edge is contained inside a Node making one end of the edge implicit /// and contains a pointer to the other end. The edge contains a lattice - /// value specifying the relationship and an ETNode specifying the root - /// in the dominator tree to which this edge applies. + /// value specifying the relationship and an DomTreeDFS::Node specifying + /// the root in the dominator tree to which this edge applies. class VISIBILITY_HIDDEN Edge { public: - Edge(unsigned T, LatticeVal V, ETNode *ST) + Edge(unsigned T, LatticeVal V, DomTreeDFS::Node *ST) : To(T), LV(V), Subtree(ST) {} unsigned To; LatticeVal LV; - ETNode *Subtree; + DomTreeDFS::Node *Subtree; bool operator<(const Edge &edge) const { if (To != edge.To) return To < edge.To; - else return OrderByDominance()(Subtree, edge.Subtree); + else return *Subtree < *edge.Subtree; } + bool operator<(unsigned to) const { return To < to; } + bool operator>(unsigned to) const { return To > to; } @@ -293,7 +461,7 @@ const_iterator begin() const { return Relations.begin(); } const_iterator end() const { return Relations.end(); } - iterator find(unsigned n, ETNode *Subtree) { + iterator find(unsigned n, DomTreeDFS::Node *Subtree) { iterator E = end(); for (iterator I = std::lower_bound(begin(), E, n); I != E && I->To == n; ++I) { @@ -303,7 +471,7 @@ return E; } - const_iterator find(unsigned n, ETNode *Subtree) const { + const_iterator find(unsigned n, DomTreeDFS::Node *Subtree) const { const_iterator E = end(); for (const_iterator I = std::lower_bound(begin(), E, n); I != E && I->To == n; ++I) { @@ -321,7 +489,7 @@ /// Updates the lattice value for a given node. Create a new entry if /// one doesn't exist, otherwise it merges the values. The new lattice /// value must not be inconsistent with any previously existing value. - void update(unsigned n, LatticeVal R, ETNode *Subtree) { + void update(unsigned n, LatticeVal R, DomTreeDFS::Node *Subtree) { assert(validPredicate(R) && "Invalid predicate."); iterator I = find(n, Subtree); if (I == end()) { @@ -360,9 +528,9 @@ struct VISIBILITY_HIDDEN NodeMapEdge { Value *V; unsigned index; - ETNode *Subtree; + DomTreeDFS::Node *Subtree; - NodeMapEdge(Value *V, unsigned index, ETNode *Subtree) + NodeMapEdge(Value *V, unsigned index, DomTreeDFS::Node *Subtree) : V(V), index(index), Subtree(Subtree) {} bool operator==(const NodeMapEdge &RHS) const { @@ -372,7 +540,7 @@ bool operator<(const NodeMapEdge &RHS) const { if (V != RHS.V) return V < RHS.V; - return OrderByDominance()(Subtree, RHS.Subtree); + else return *Subtree < *RHS.Subtree; } bool operator<(Value *RHS) const { @@ -397,7 +565,7 @@ /// Returns the node currently representing Value V, or zero if no such /// node exists. - unsigned getNode(Value *V, ETNode *Subtree) { + unsigned getNode(Value *V, DomTreeDFS::Node *Subtree) { NodeMapType::iterator E = NodeMap.end(); NodeMapEdge Edge(V, 0, Subtree); NodeMapType::iterator I = std::lower_bound(NodeMap.begin(), E, Edge); @@ -411,7 +579,7 @@ /// getOrInsertNode - always returns a valid node index, creating a node /// to match the Value if needed. - unsigned getOrInsertNode(Value *V, ETNode *Subtree) { + unsigned getOrInsertNode(Value *V, DomTreeDFS::Node *Subtree) { if (unsigned n = getNode(V, Subtree)) return n; else @@ -420,6 +588,9 @@ /// newNode - creates a new node for a given Value and returns the index. unsigned newNode(Value *V) { + assert(!isa(V) && "BBs may not be nodes."); + assert(V->getType() != Type::VoidTy && "Void node?"); + Nodes.push_back(Node(V)); NodeMapEdge MapEntry = NodeMapEdge(V, Nodes.size(), TreeRoot); @@ -432,7 +603,7 @@ /// If the Value is in the graph, return the canonical form. Otherwise, /// return the original Value. - Value *canonicalize(Value *V, ETNode *Subtree) { + Value *canonicalize(Value *V, DomTreeDFS::Node *Subtree) { if (isa(V)) return V; if (unsigned n = getNode(V, Subtree)) @@ -442,7 +613,8 @@ } /// isRelatedBy - true iff n1 op n2 - bool isRelatedBy(unsigned n1, unsigned n2, ETNode *Subtree, LatticeVal LV) { + bool isRelatedBy(unsigned n1, unsigned n2, DomTreeDFS::Node *Subtree, + LatticeVal LV) { if (n1 == n2) return LV & EQ_BIT; Node *N1 = node(n1); @@ -455,7 +627,7 @@ // The add* methods assume that your input is logically valid and may // assertion-fail or infinitely loop if you attempt a contradiction. - void addEquality(unsigned n, Value *V, ETNode *Subtree) { + void addEquality(unsigned n, Value *V, DomTreeDFS::Node *Subtree) { assert(canonicalize(node(n)->getValue(), Subtree) == node(n)->getValue() && "Node's 'canonical' choice isn't best within this subtree."); @@ -504,7 +676,7 @@ /// addInequality - Sets n1 op n2. /// It is also an error to call this on an inequality that is already true. - void addInequality(unsigned n1, unsigned n2, ETNode *Subtree, + void addInequality(unsigned n1, unsigned n2, DomTreeDFS::Node *Subtree, LatticeVal LV1) { assert(n1 != n2 && "A node can't be inequal to itself."); @@ -529,7 +701,7 @@ for (Node::iterator I = N1->begin(), E = N1->end(); I != E; ++I) { if (I->LV != NE && I->To != n2) { - ETNode *Local_Subtree = NULL; + DomTreeDFS::Node *Local_Subtree = NULL; if (Subtree->DominatedBy(I->Subtree)) Local_Subtree = Subtree; else if (I->Subtree->DominatedBy(Subtree)) @@ -565,7 +737,7 @@ for (Node::iterator I = N2->begin(), E = N2->end(); I != E; ++I) { if (I->LV != NE && I->To != n1) { - ETNode *Local_Subtree = NULL; + DomTreeDFS::Node *Local_Subtree = NULL; if (Subtree->DominatedBy(I->Subtree)) Local_Subtree = Subtree; else if (I->Subtree->DominatedBy(Subtree)) @@ -661,16 +833,16 @@ /// the scope of a rooted subtree in the dominator tree. class VISIBILITY_HIDDEN ScopedRange { public: - ScopedRange(Value *V, ConstantRange CR, ETNode *ST) + ScopedRange(Value *V, ConstantRange CR, DomTreeDFS::Node *ST) : V(V), CR(CR), Subtree(ST) {} Value *V; ConstantRange CR; - ETNode *Subtree; + DomTreeDFS::Node *Subtree; bool operator<(const ScopedRange &range) const { if (V != range.V) return V < range.V; - else return OrderByDominance()(Subtree, range.Subtree); + else return Subtree < range.Subtree; } bool operator<(const Value *value) const { @@ -697,7 +869,7 @@ iterator begin() { return Ranges.begin(); } iterator end() { return Ranges.end(); } - iterator find(Value *V, ETNode *Subtree) { + iterator find(Value *V, DomTreeDFS::Node *Subtree) { iterator E = end(); for (iterator I = std::lower_bound(begin(), E, V); I != E && I->V == V; ++I) { @@ -707,7 +879,7 @@ return E; } - void update(Value *V, ConstantRange CR, ETNode *Subtree) { + void update(Value *V, ConstantRange CR, DomTreeDFS::Node *Subtree) { assert(!CR.isEmptySet() && "Empty ConstantRange!"); if (CR.isFullSet()) return; @@ -827,7 +999,7 @@ } #ifndef NDEBUG - bool isCanonical(Value *V, ETNode *Subtree, VRPSolver *VRP); + bool isCanonical(Value *V, DomTreeDFS::Node *Subtree, VRPSolver *VRP); #endif public: @@ -838,7 +1010,8 @@ // constant it constructs the single element range, otherwise it performs // a lookup. The width W must be retrieved from typeToWidth and may not // be zero. - ConstantRange rangeFromValue(Value *V, ETNode *Subtree, uint32_t W) { + ConstantRange rangeFromValue(Value *V, DomTreeDFS::Node *Subtree, + uint32_t W) { if (ConstantInt *C = dyn_cast(V)) { return ConstantRange(C->getValue()); } else if (isa(V)) { @@ -863,7 +1036,8 @@ return 0; } - bool isRelatedBy(Value *V1, Value *V2, ETNode *Subtree, LatticeVal LV) { + bool isRelatedBy(Value *V1, Value *V2, DomTreeDFS::Node *Subtree, + LatticeVal LV) { uint32_t W = typeToWidth(V1->getType()); if (!W) return false; @@ -922,8 +1096,8 @@ VRPSolver *VRP); void markBlock(VRPSolver *VRP); - void mergeInto(Value **I, unsigned n, Value *New, ETNode *Subtree, - VRPSolver *VRP) { + void mergeInto(Value **I, unsigned n, Value *New, + DomTreeDFS::Node *Subtree, VRPSolver *VRP) { assert(isCanonical(New, Subtree, VRP) && "Best choice not canonical?"); uint32_t W = typeToWidth(New->getType()); @@ -943,8 +1117,8 @@ applyRange(New, Merged, Subtree, VRP); } - void applyRange(Value *V, const ConstantRange &CR, ETNode *Subtree, - VRPSolver *VRP) { + void applyRange(Value *V, const ConstantRange &CR, + DomTreeDFS::Node *Subtree, VRPSolver *VRP) { assert(isCanonical(V, Subtree, VRP) && "Value not canonical."); if (const APInt *I = CR.getSingleElement()) { @@ -970,7 +1144,8 @@ update(V, Merged, Subtree); } - void addNotEquals(Value *V1, Value *V2, ETNode *Subtree, VRPSolver *VRP) { + void addNotEquals(Value *V1, Value *V2, DomTreeDFS::Node *Subtree, + VRPSolver *VRP) { uint32_t W = typeToWidth(V1->getType()); if (!W) return; @@ -1024,8 +1199,8 @@ } } - void addInequality(Value *V1, Value *V2, ETNode *Subtree, LatticeVal LV, - VRPSolver *VRP) { + void addInequality(Value *V1, Value *V2, DomTreeDFS::Node *Subtree, + LatticeVal LV, VRPSolver *VRP) { assert(!isRelatedBy(V1, V2, Subtree, LV) && "Asked to do useless work."); assert(isCanonical(V1, Subtree, VRP) && "Value not canonical."); @@ -1123,7 +1298,7 @@ Value *LHS, *RHS; ICmpInst::Predicate Op; - BasicBlock *ContextBB; + BasicBlock *ContextBB; // XXX use a DomTreeDFS::Node instead Instruction *ContextInst; }; std::deque WorkList; @@ -1131,37 +1306,14 @@ InequalityGraph &IG; UnreachableBlocks &UB; ValueRanges &VR; - - ETForest *Forest; - ETNode *Top; + DomTreeDFS *DTDFS; + DomTreeDFS::Node *Top; BasicBlock *TopBB; Instruction *TopInst; bool &modified; typedef InequalityGraph::Node Node; - /// IdomI - Determines whether one Instruction dominates another. - bool IdomI(Instruction *I1, Instruction *I2) const { - BasicBlock *BB1 = I1->getParent(), - *BB2 = I2->getParent(); - if (BB1 == BB2) { - if (isa(I1)) return false; - if (isa(I2)) return true; - if (isa(I1) && !isa(I2)) return true; - if (!isa(I1) && isa(I2)) return false; - - for (BasicBlock::const_iterator I = BB1->begin(), E = BB1->end(); - I != E; ++I) { - if (&*I == I1) return true; - if (&*I == I2) return false; - } - assert(!"Instructions not found in parent BasicBlock?"); - } else { - return Forest->properlyDominates(BB1, BB2); - } - return false; - } - /// Returns true if V1 is a better canonical value than V2. bool compare(Value *V1, Value *V2) const { if (isa(V1)) @@ -1179,22 +1331,48 @@ if (!I1 || !I2) return V1->getNumUses() < V2->getNumUses(); - return IdomI(I1, I2); + return DTDFS->dominates(I1, I2); } // below - true if the Instruction is dominated by the current context // block or instruction bool below(Instruction *I) { - if (TopInst) - return IdomI(TopInst, I); - else { - ETNode *Node = Forest->getNodeForBlock(I->getParent()); - return Node->DominatedBy(Top); + BasicBlock *BB = I->getParent(); + if (TopInst && TopInst->getParent() == BB) { + if (isa(TopInst)) return false; + if (isa(I)) return true; + if ( isa(TopInst) && !isa(I)) return true; + if (!isa(TopInst) && isa(I)) return false; + + for (BasicBlock::const_iterator Iter = BB->begin(), E = BB->end(); + Iter != E; ++Iter) { + if (&*Iter == TopInst) return true; + else if (&*Iter == I) return false; + } + assert(!"Instructions not found in parent BasicBlock?"); + } else { + DomTreeDFS::Node *Node = DTDFS->getNodeForBlock(BB); + if (!Node) return false; + return Top->dominates(Node); } } + // aboveOrBelow - true if the Instruction either dominates or is dominated + // by the current context block or instruction + bool aboveOrBelow(Instruction *I) { + BasicBlock *BB = I->getParent(); + DomTreeDFS::Node *Node = DTDFS->getNodeForBlock(BB); + if (!Node) return false; + + return Top == Node || Top->dominates(Node) || Node->dominates(Top); + } + bool makeEqual(Value *V1, Value *V2) { DOUT << "makeEqual(" << *V1 << ", " << *V2 << ")\n"; + DOUT << "context is "; + if (TopInst) DOUT << "I: " << *TopInst << "\n"; + else DOUT << "BB: " << TopBB->getName() + << "(" << Top->getDFSNumIn() << ")\n"; assert(V1->getType() == V2->getType() && "Can't make two values with different types equal."); @@ -1396,8 +1574,7 @@ if (i) R = IG.node(Remove[i])->getValue(); // skip n2. if (Instruction *I2 = dyn_cast(R)) { - if (below(I2) || - Top->DominatedBy(Forest->getNodeForBlock(I2->getParent()))) + if (aboveOrBelow(I2)) defToOps(I2); } for (Value::use_iterator UI = V2->use_begin(), UE = V2->use_end(); @@ -1405,8 +1582,7 @@ Use &TheUse = UI.getUse(); ++UI; if (Instruction *I = dyn_cast(TheUse.getUser())) { - if (below(I) || - Top->DominatedBy(Forest->getNodeForBlock(I->getParent()))) + if (aboveOrBelow(I)) opsToDef(I); } } @@ -1422,8 +1598,7 @@ Value *V = TheUse.getUser(); if (!V->use_empty()) { if (Instruction *Inst = dyn_cast(V)) { - if (below(Inst) || - Top->DominatedBy(Forest->getNodeForBlock(Inst->getParent()))) + if (aboveOrBelow(Inst)) opsToDef(Inst); } } @@ -1465,27 +1640,32 @@ public: VRPSolver(InequalityGraph &IG, UnreachableBlocks &UB, ValueRanges &VR, - ETForest *Forest, bool &modified, BasicBlock *TopBB) + DomTreeDFS *DTDFS, bool &modified, BasicBlock *TopBB) : IG(IG), UB(UB), VR(VR), - Forest(Forest), - Top(Forest->getNodeForBlock(TopBB)), + DTDFS(DTDFS), + Top(DTDFS->getNodeForBlock(TopBB)), TopBB(TopBB), TopInst(NULL), - modified(modified) {} + modified(modified) + { + assert(Top && "VRPSolver created for unreachable basic block."); + } VRPSolver(InequalityGraph &IG, UnreachableBlocks &UB, ValueRanges &VR, - ETForest *Forest, bool &modified, Instruction *TopInst) + DomTreeDFS *DTDFS, bool &modified, Instruction *TopInst) : IG(IG), UB(UB), VR(VR), - Forest(Forest), + DTDFS(DTDFS), + Top(DTDFS->getNodeForBlock(TopInst->getParent())), + TopBB(TopInst->getParent()), TopInst(TopInst), modified(modified) { - TopBB = TopInst->getParent(); - Top = Forest->getNodeForBlock(TopBB); + assert(Top && "VRPSolver created for unreachable basic block."); + assert(Top->getBlock() == TopInst->getParent() && "Context mismatch."); } bool isRelatedBy(Value *V1, Value *V2, ICmpInst::Predicate Pred) const { @@ -1514,7 +1694,7 @@ Instruction *I = NULL) { DOUT << "adding " << *V1 << " " << Pred << " " << *V2; if (I) DOUT << " context: " << *I; - else DOUT << " default context"; + else DOUT << " default context (" << Top->getDFSNumIn() << ")"; DOUT << "\n"; assert(V1->getType() == V2->getType() && @@ -1856,7 +2036,7 @@ Operation &O = WorkList.front(); TopInst = O.ContextInst; TopBB = O.ContextBB; - Top = Forest->getNodeForBlock(TopBB); + Top = DTDFS->getNodeForBlock(TopBB); // XXX move this into Context O.LHS = IG.canonicalize(O.LHS, Top); O.RHS = IG.canonicalize(O.RHS, Top); @@ -1933,8 +2113,7 @@ } if (Instruction *I1 = dyn_cast(O.LHS)) { - if (below(I1) || - Top->DominatedBy(Forest->getNodeForBlock(I1->getParent()))) + if (aboveOrBelow(I1)) defToOps(I1); } if (isa(O.LHS) || isa(O.LHS)) { @@ -1943,15 +2122,13 @@ Use &TheUse = UI.getUse(); ++UI; if (Instruction *I = dyn_cast(TheUse.getUser())) { - if (below(I) || - Top->DominatedBy(Forest->getNodeForBlock(I->getParent()))) + if (aboveOrBelow(I)) opsToDef(I); } } } if (Instruction *I2 = dyn_cast(O.RHS)) { - if (below(I2) || - Top->DominatedBy(Forest->getNodeForBlock(I2->getParent()))) + if (aboveOrBelow(I2)) defToOps(I2); } if (isa(O.RHS) || isa(O.RHS)) { @@ -1960,9 +2137,7 @@ Use &TheUse = UI.getUse(); ++UI; if (Instruction *I = dyn_cast(TheUse.getUser())) { - if (below(I) || - Top->DominatedBy(Forest->getNodeForBlock(I->getParent()))) - + if (aboveOrBelow(I)) opsToDef(I); } } @@ -1984,7 +2159,8 @@ } #ifndef NDEBUG - bool ValueRanges::isCanonical(Value *V, ETNode *Subtree, VRPSolver *VRP) { + bool ValueRanges::isCanonical(Value *V, DomTreeDFS::Node *Subtree, + VRPSolver *VRP) { return V == VRP->IG.canonicalize(V, Subtree); } #endif @@ -1994,14 +2170,13 @@ /// can't be equal and will solve setcc instructions when possible. /// @brief Root of the predicate simplifier optimization. class VISIBILITY_HIDDEN PredicateSimplifier : public FunctionPass { - DominatorTree *DT; - ETForest *Forest; + DomTreeDFS *DTDFS; bool modified; InequalityGraph *IG; UnreachableBlocks UB; ValueRanges *VR; - std::vector WorkList; + std::vector WorkList; public: static char ID; // Pass identification, replacement for typeid @@ -2012,7 +2187,6 @@ virtual void getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequiredID(BreakCriticalEdgesID); AU.addRequired(); - AU.addRequired(); AU.addRequired(); AU.addPreserved(); } @@ -2027,14 +2201,14 @@ class VISIBILITY_HIDDEN Forwards : public InstVisitor { friend class InstVisitor; PredicateSimplifier *PS; - DomTreeNode *DTNode; + DomTreeDFS::Node *DTNode; public: InequalityGraph &IG; UnreachableBlocks &UB; ValueRanges &VR; - Forwards(PredicateSimplifier *PS, DomTreeNode *DTNode) + Forwards(PredicateSimplifier *PS, DomTreeDFS::Node *DTNode) : PS(PS), DTNode(DTNode), IG(*PS->IG), UB(PS->UB), VR(*PS->VR) {} void visitTerminatorInst(TerminatorInst &TI); @@ -2055,31 +2229,30 @@ // Used by terminator instructions to proceed from the current basic // block to the next. Verifies that "current" dominates "next", // then calls visitBasicBlock. - void proceedToSuccessors(DomTreeNode *Current) { - for (DomTreeNode::iterator I = Current->begin(), + void proceedToSuccessors(DomTreeDFS::Node *Current) { + for (DomTreeDFS::Node::iterator I = Current->begin(), E = Current->end(); I != E; ++I) { WorkList.push_back(*I); } } - void proceedToSuccessor(DomTreeNode *Next) { + void proceedToSuccessor(DomTreeDFS::Node *Next) { WorkList.push_back(Next); } // Visits each instruction in the basic block. - void visitBasicBlock(DomTreeNode *Node) { + void visitBasicBlock(DomTreeDFS::Node *Node) { BasicBlock *BB = Node->getBlock(); - ETNode *ET = Forest->getNodeForBlock(BB); DOUT << "Entering Basic Block: " << BB->getName() - << " (" << ET->getDFSNumIn() << ")\n"; + << " (" << Node->getDFSNumIn() << ")\n"; for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;) { - visitInstruction(I++, Node, ET); + visitInstruction(I++, Node); } } // Tries to simplify each Instruction and add new properties to // the PropertySet. - void visitInstruction(Instruction *I, DomTreeNode *DT, ETNode *ET) { + void visitInstruction(Instruction *I, DomTreeDFS::Node *DT) { DOUT << "Considering instruction " << *I << "\n"; DEBUG(IG->dump()); @@ -2094,7 +2267,7 @@ #ifndef NDEBUG // Try to replace the whole instruction. - Value *V = IG->canonicalize(I, ET); + Value *V = IG->canonicalize(I, DT); assert(V == I && "Late instruction canonicalization."); if (V != I) { modified = true; @@ -2109,7 +2282,7 @@ // Try to substitute operands. for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) { Value *Oper = I->getOperand(i); - Value *V = IG->canonicalize(Oper, ET); + Value *V = IG->canonicalize(Oper, DT); assert(V == Oper && "Late operand canonicalization."); if (V != Oper) { modified = true; @@ -2130,28 +2303,25 @@ }; bool PredicateSimplifier::runOnFunction(Function &F) { - DT = &getAnalysis(); - Forest = &getAnalysis(); - + DominatorTree *DT = &getAnalysis(); + DTDFS = new DomTreeDFS(DT); TargetData *TD = &getAnalysis(); - // XXX: should only act when numbers are out of date - Forest->updateDFSNumbers(); - DOUT << "Entering Function: " << F.getName() << "\n"; modified = false; - BasicBlock *RootBlock = &F.getEntryBlock(); - IG = new InequalityGraph(Forest->getNodeForBlock(RootBlock)); + DomTreeDFS::Node *Root = DTDFS->getRootNode(); + IG = new InequalityGraph(Root); VR = new ValueRanges(TD); - WorkList.push_back(DT->getRootNode()); + WorkList.push_back(Root); do { - DomTreeNode *DTNode = WorkList.back(); + DomTreeDFS::Node *DTNode = WorkList.back(); WorkList.pop_back(); if (!UB.isDead(DTNode->getBlock())) visitBasicBlock(DTNode); } while (!WorkList.empty()); + delete DTDFS; delete VR; delete IG; @@ -2179,21 +2349,21 @@ return; } - for (DomTreeNode::iterator I = DTNode->begin(), E = DTNode->end(); + for (DomTreeDFS::Node::iterator I = DTNode->begin(), E = DTNode->end(); I != E; ++I) { BasicBlock *Dest = (*I)->getBlock(); DOUT << "Branch thinking about %" << Dest->getName() - << "(" << PS->Forest->getNodeForBlock(Dest)->getDFSNumIn() << ")\n"; + << "(" << PS->DTDFS->getNodeForBlock(Dest)->getDFSNumIn() << ")\n"; if (Dest == TrueDest) { DOUT << "(" << DTNode->getBlock()->getName() << ") true set:\n"; - VRPSolver VRP(IG, UB, VR, PS->Forest, PS->modified, Dest); + VRPSolver VRP(IG, UB, VR, PS->DTDFS, PS->modified, Dest); VRP.add(ConstantInt::getTrue(), Condition, ICmpInst::ICMP_EQ); VRP.solve(); DEBUG(IG.dump()); } else if (Dest == FalseDest) { DOUT << "(" << DTNode->getBlock()->getName() << ") false set:\n"; - VRPSolver VRP(IG, UB, VR, PS->Forest, PS->modified, Dest); + VRPSolver VRP(IG, UB, VR, PS->DTDFS, PS->modified, Dest); VRP.add(ConstantInt::getFalse(), Condition, ICmpInst::ICMP_EQ); VRP.solve(); DEBUG(IG.dump()); @@ -2209,13 +2379,13 @@ // Set the EQProperty in each of the cases BBs, and the NEProperties // in the default BB. - for (DomTreeNode::iterator I = DTNode->begin(), E = DTNode->end(); + for (DomTreeDFS::Node::iterator I = DTNode->begin(), E = DTNode->end(); I != E; ++I) { BasicBlock *BB = (*I)->getBlock(); DOUT << "Switch thinking about BB %" << BB->getName() - << "(" << PS->Forest->getNodeForBlock(BB)->getDFSNumIn() << ")\n"; + << "(" << PS->DTDFS->getNodeForBlock(BB)->getDFSNumIn() << ")\n"; - VRPSolver VRP(IG, UB, VR, PS->Forest, PS->modified, BB); + VRPSolver VRP(IG, UB, VR, PS->DTDFS, PS->modified, BB); if (BB == SI.getDefaultDest()) { for (unsigned i = 1, e = SI.getNumCases(); i < e; ++i) if (SI.getSuccessor(i) != BB) @@ -2230,7 +2400,7 @@ } void PredicateSimplifier::Forwards::visitAllocaInst(AllocaInst &AI) { - VRPSolver VRP(IG, UB, VR, PS->Forest, PS->modified, &AI); + VRPSolver VRP(IG, UB, VR, PS->DTDFS, PS->modified, &AI); VRP.add(Constant::getNullValue(AI.getType()), &AI, ICmpInst::ICMP_NE); VRP.solve(); } @@ -2240,7 +2410,7 @@ // avoid "load uint* null" -> null NE null. if (isa(Ptr)) return; - VRPSolver VRP(IG, UB, VR, PS->Forest, PS->modified, &LI); + VRPSolver VRP(IG, UB, VR, PS->DTDFS, PS->modified, &LI); VRP.add(Constant::getNullValue(Ptr->getType()), Ptr, ICmpInst::ICMP_NE); VRP.solve(); } @@ -2249,13 +2419,13 @@ Value *Ptr = SI.getPointerOperand(); if (isa(Ptr)) return; - VRPSolver VRP(IG, UB, VR, PS->Forest, PS->modified, &SI); + VRPSolver VRP(IG, UB, VR, PS->DTDFS, PS->modified, &SI); VRP.add(Constant::getNullValue(Ptr->getType()), Ptr, ICmpInst::ICMP_NE); VRP.solve(); } void PredicateSimplifier::Forwards::visitSExtInst(SExtInst &SI) { - VRPSolver VRP(IG, UB, VR, PS->Forest, PS->modified, &SI); + VRPSolver VRP(IG, UB, VR, PS->DTDFS, PS->modified, &SI); uint32_t SrcBitWidth = cast(SI.getSrcTy())->getBitWidth(); uint32_t DstBitWidth = cast(SI.getDestTy())->getBitWidth(); APInt Min(APInt::getHighBitsSet(DstBitWidth, DstBitWidth-SrcBitWidth+1)); @@ -2266,7 +2436,7 @@ } void PredicateSimplifier::Forwards::visitZExtInst(ZExtInst &ZI) { - VRPSolver VRP(IG, UB, VR, PS->Forest, PS->modified, &ZI); + VRPSolver VRP(IG, UB, VR, PS->DTDFS, PS->modified, &ZI); uint32_t SrcBitWidth = cast(ZI.getSrcTy())->getBitWidth(); uint32_t DstBitWidth = cast(ZI.getDestTy())->getBitWidth(); APInt Max(APInt::getLowBitsSet(DstBitWidth, SrcBitWidth)); @@ -2284,7 +2454,7 @@ case Instruction::UDiv: case Instruction::SDiv: { Value *Divisor = BO.getOperand(1); - VRPSolver VRP(IG, UB, VR, PS->Forest, PS->modified, &BO); + VRPSolver VRP(IG, UB, VR, PS->DTDFS, PS->modified, &BO); VRP.add(Constant::getNullValue(Divisor->getType()), Divisor, ICmpInst::ICMP_NE); VRP.solve(); @@ -2295,34 +2465,34 @@ switch (ops) { default: break; case Instruction::Shl: { - VRPSolver VRP(IG, UB, VR, PS->Forest, PS->modified, &BO); + VRPSolver VRP(IG, UB, VR, PS->DTDFS, PS->modified, &BO); VRP.add(&BO, BO.getOperand(0), ICmpInst::ICMP_UGE); VRP.solve(); } break; case Instruction::AShr: { - VRPSolver VRP(IG, UB, VR, PS->Forest, PS->modified, &BO); + VRPSolver VRP(IG, UB, VR, PS->DTDFS, PS->modified, &BO); VRP.add(&BO, BO.getOperand(0), ICmpInst::ICMP_SLE); VRP.solve(); } break; case Instruction::LShr: case Instruction::UDiv: { - VRPSolver VRP(IG, UB, VR, PS->Forest, PS->modified, &BO); + VRPSolver VRP(IG, UB, VR, PS->DTDFS, PS->modified, &BO); VRP.add(&BO, BO.getOperand(0), ICmpInst::ICMP_ULE); VRP.solve(); } break; case Instruction::URem: { - VRPSolver VRP(IG, UB, VR, PS->Forest, PS->modified, &BO); + VRPSolver VRP(IG, UB, VR, PS->DTDFS, PS->modified, &BO); VRP.add(&BO, BO.getOperand(1), ICmpInst::ICMP_ULE); VRP.solve(); } break; case Instruction::And: { - VRPSolver VRP(IG, UB, VR, PS->Forest, PS->modified, &BO); + VRPSolver VRP(IG, UB, VR, PS->DTDFS, PS->modified, &BO); VRP.add(&BO, BO.getOperand(0), ICmpInst::ICMP_ULE); VRP.add(&BO, BO.getOperand(1), ICmpInst::ICMP_ULE); VRP.solve(); } break; case Instruction::Or: { - VRPSolver VRP(IG, UB, VR, PS->Forest, PS->modified, &BO); + VRPSolver VRP(IG, UB, VR, PS->DTDFS, PS->modified, &BO); VRP.add(&BO, BO.getOperand(0), ICmpInst::ICMP_UGE); VRP.add(&BO, BO.getOperand(1), ICmpInst::ICMP_UGE); VRP.solve(); @@ -2348,7 +2518,7 @@ case ICmpInst::ICMP_SGE: Pred = ICmpInst::ICMP_SGT; break; } if (Pred != IC.getPredicate()) { - VRPSolver VRP(IG, UB, VR, PS->Forest, PS->modified, &IC); + VRPSolver VRP(IG, UB, VR, PS->DTDFS, PS->modified, &IC); if (VRP.isRelatedBy(IC.getOperand(1), IC.getOperand(0), ICmpInst::ICMP_NE)) { ++NumSnuggle; @@ -2376,7 +2546,7 @@ } if (NextVal) { - VRPSolver VRP(IG, UB, VR, PS->Forest, PS->modified, &IC); + VRPSolver VRP(IG, UB, VR, PS->DTDFS, PS->modified, &IC); if (VRP.isRelatedBy(IC.getOperand(0), NextVal, ICmpInst::getInversePredicate(Pred))) { ICmpInst *NewIC = new ICmpInst(ICmpInst::ICMP_EQ, IC.getOperand(0), From nicholas at mxc.ca Sat Jun 23 23:40:38 2007 From: nicholas at mxc.ca (Nick Lewycky) Date: Sat, 23 Jun 2007 23:40:38 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/PredicateSimplifier.cpp Message-ID: <200706240440.l5O4ecQx020343@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: PredicateSimplifier.cpp updated: 1.79 -> 1.80 --- Log message: Remove tabs. --- Diffs of the changes: (+2 -2) PredicateSimplifier.cpp | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/Transforms/Scalar/PredicateSimplifier.cpp diff -u llvm/lib/Transforms/Scalar/PredicateSimplifier.cpp:1.79 llvm/lib/Transforms/Scalar/PredicateSimplifier.cpp:1.80 --- llvm/lib/Transforms/Scalar/PredicateSimplifier.cpp:1.79 Sat Jun 23 23:36:20 2007 +++ llvm/lib/Transforms/Scalar/PredicateSimplifier.cpp Sat Jun 23 23:40:16 2007 @@ -234,7 +234,7 @@ } assert(!"Instructions not found in parent BasicBlock?"); } else { - Node *Node1 = getNodeForBlock(BB1), + Node *Node1 = getNodeForBlock(BB1), *Node2 = getNodeForBlock(BB2); if (!Node1 || !Node2) return false; return Node1->dominates(Node2); @@ -1351,7 +1351,7 @@ } assert(!"Instructions not found in parent BasicBlock?"); } else { - DomTreeDFS::Node *Node = DTDFS->getNodeForBlock(BB); + DomTreeDFS::Node *Node = DTDFS->getNodeForBlock(BB); if (!Node) return false; return Top->dominates(Node); } From resistor at mac.com Sun Jun 24 03:18:30 2007 From: resistor at mac.com (Owen Anderson) Date: Sun, 24 Jun 2007 03:18:30 -0500 Subject: [llvm-commits] CVS: llvm/test/Transforms/GVNPRE/basic.ll Message-ID: <200706240818.l5O8IUlq000892@zion.cs.uiuc.edu> Changes in directory llvm/test/Transforms/GVNPRE: basic.ll updated: 1.2 -> 1.3 --- Log message: Rename variables to expose the fact that this test is failing. --- Diffs of the changes: (+16 -16) basic.ll | 32 ++++++++++++++++---------------- 1 files changed, 16 insertions(+), 16 deletions(-) Index: llvm/test/Transforms/GVNPRE/basic.ll diff -u llvm/test/Transforms/GVNPRE/basic.ll:1.2 llvm/test/Transforms/GVNPRE/basic.ll:1.3 --- llvm/test/Transforms/GVNPRE/basic.ll:1.2 Mon Jun 11 23:40:48 2007 +++ llvm/test/Transforms/GVNPRE/basic.ll Sun Jun 24 03:17:41 2007 @@ -1,38 +1,38 @@ -; RUN: llvm-as < %s | opt -gvnpre | llvm-dis | not grep {%t3 =} -; RUN: llvm-as < %s | opt -gvnpre | llvm-dis | not grep {%t9 =} +; RUN: llvm-as < %s | opt -gvnpre | llvm-dis | not grep {%z3 =} +; RUN: llvm-as < %s | opt -gvnpre | llvm-dis | not grep {%z9 =} define i32 @main() { block1: - %t1 = bitcast i32 0 to i32 ; [#uses=5] + %z1 = bitcast i32 0 to i32 ; [#uses=5] br label %block2 block2: ; preds = %block6, %block1 - %t2 = phi i32 [ %t1, %block1 ], [ %t3, %block6 ] ; [#uses=3] - %t3 = add i32 %t2, 1 ; [#uses=5] + %z2 = phi i32 [ %z1, %block1 ], [ %z3, %block6 ] ; [#uses=3] + %z3 = add i32 %z2, 1 ; [#uses=5] br i1 false, label %block3, label %block7 block3: ; preds = %block2 br i1 true, label %block4, label %block5 block4: ; preds = %block3 - %t4 = add i32 %t2, %t3 ; [#uses=1] - %t5 = bitcast i32 %t4 to i32 ; [#uses=1] - %t6 = add i32 %t1, %t5 ; [#uses=0] + %z4 = add i32 %z2, %z3 ; [#uses=1] + %z5 = bitcast i32 %z4 to i32 ; [#uses=1] + %z6 = add i32 %z1, %z5 ; [#uses=0] br label %block6 block5: ; preds = %block3 - %t7 = add i32 %t3, 1 ; [#uses=1] + %z7 = add i32 %z3, 1 ; [#uses=1] br label %block6 block6: ; preds = %block5, %block4 - %t8 = phi i32 [ %t1, %block4 ], [ %t7, %block5 ] ; [#uses=1] - %t9 = add i32 %t2, %t3 ; [#uses=2] - %t10 = add i32 %t9, %t8 ; [#uses=0] - %t11 = bitcast i32 12 to i32 ; [#uses=1] - %t12 = add i32 %t9, %t11 ; [#uses=1] - %t13 = add i32 %t12, %t3 ; [#uses=0] + %z8 = phi i32 [ %z1, %block4 ], [ %z7, %block5 ] ; [#uses=1] + %z9 = add i32 %z2, %z3 ; [#uses=2] + %z10 = add i32 %z9, %z8 ; [#uses=0] + %z11 = bitcast i32 12 to i32 ; [#uses=1] + %z12 = add i32 %z9, %z11 ; [#uses=1] + %z13 = add i32 %z12, %z3 ; [#uses=0] br label %block2 block7: ; preds = %block2 - ret i32 %t1 + ret i32 %z1 } From resistor at mac.com Sun Jun 24 03:42:46 2007 From: resistor at mac.com (Owen Anderson) Date: Sun, 24 Jun 2007 03:42:46 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/GVNPRE.cpp Message-ID: <200706240842.l5O8gkik001317@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: GVNPRE.cpp updated: 1.55 -> 1.56 --- Log message: Fix a silly mistake that was causing failures. --- Diffs of the changes: (+2 -2) GVNPRE.cpp | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/lib/Transforms/Scalar/GVNPRE.cpp diff -u llvm/lib/Transforms/Scalar/GVNPRE.cpp:1.55 llvm/lib/Transforms/Scalar/GVNPRE.cpp:1.56 --- llvm/lib/Transforms/Scalar/GVNPRE.cpp:1.55 Fri Jun 22 16:31:16 2007 +++ llvm/lib/Transforms/Scalar/GVNPRE.cpp Sun Jun 24 03:42:24 2007 @@ -1013,8 +1013,8 @@ - unsigned ret = buildsets_anticin(BB, anticOut, generatedTemporaries[BB], - generatedExpressions[BB], visited); + unsigned ret = buildsets_anticin(BB, anticOut,generatedExpressions[BB], + generatedTemporaries[BB], visited); if (ret == 0) { changed = true; From nicholas at mxc.ca Sun Jun 24 15:14:47 2007 From: nicholas at mxc.ca (Nick Lewycky) Date: Sun, 24 Jun 2007 15:14:47 -0500 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/PredicateSimplifier.cpp Message-ID: <200706242014.l5OKElKr030253@zion.cs.uiuc.edu> Changes in directory llvm/lib/Transforms/Scalar: PredicateSimplifier.cpp updated: 1.80 -> 1.81 --- Log message: Fix value ranges. --- Diffs of the changes: (+1 -1) PredicateSimplifier.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Transforms/Scalar/PredicateSimplifier.cpp diff -u llvm/lib/Transforms/Scalar/PredicateSimplifier.cpp:1.80 llvm/lib/Transforms/Scalar/PredicateSimplifier.cpp:1.81 --- llvm/lib/Transforms/Scalar/PredicateSimplifier.cpp:1.80 Sat Jun 23 23:40:16 2007 +++ llvm/lib/Transforms/Scalar/PredicateSimplifier.cpp Sun Jun 24 15:14:22 2007 @@ -842,7 +842,7 @@ bool operator<(const ScopedRange &range) const { if (V != range.V) return V < range.V; - else return Subtree < range.Subtree; + else return *Subtree < *range.Subtree; } bool operator<(const Value *value) const { From romixlev at yahoo.com Sun Jun 24 16:18:06 2007 From: romixlev at yahoo.com (Roman Levenstein) Date: Sun, 24 Jun 2007 23:18:06 +0200 (CEST) Subject: [llvm-commits] [LLVMdev] BigBlock register allocator Message-ID: <50075.99914.qm@web56302.mail.re3.yahoo.com> Hi Duraid, Here is a promised patch. It makes the VigBlock regalloc faster (almost as fast as Local), removes some unused code derived from the Local regalloc and also fixes one or two bugs. More precisely: 1) InsnTimes map was removed completely 2) For each vector of VReg read occurences In VRegReadTable current index is maintained. It allows for expecting only those occurences that are in the future and avoids looking at the old references. 3) PhysRegsUseOrder is not used any more 4) There was a bug in your code when an instruction was changed due to the memory operands folding. The new instruction had always an incorrect time (i.e. 0), because it was not found in the InsnTimes map. It lead to wrong results in chooseReg(). Fixed. Duraid, I send your the whole file, since there are quite some changes. Please review it and commit if you think it is OK. I'm looking forward to getting from you some examples of very big BBs for testing. -Roman > --- Roman Levenstein schrieb: > > > Hi Duraid, > > > > > Hi everyone, > > > > > > Quick summary: > > > > > > LLVM now has a new register allocator particularly suitable for > > > compiling (very) large, machine-generated functions. > > > > Congrats! Very good job! > > > > > Longer story: > > > > > > I've recently been using LLVM in an application that involves > > JITing > > > > > > fairly large functions that have no control flow - they're just > > flat > > > sequences of instructions, anywhere from 100 to 10000+ in size. > > (The > > > control flow is all in the host program, which works out which > > > monster function to call and when.) > > > > > The default (linearscan) register allocator wasn't doing a good > > job, > > as > > > it doesn't (yet) have live range splitting. It would quickly use > > all > > > available registers and then get stuck, using only a single > > register > > > (and the stack, a lot!) for hundreds or thousands of instructions > > at > > > a time, greatly slowing (+bloating) the code. > > > > True. I'm working on the version of the linear scan based on > Wimmer's > > thesis. It supports live range splitting. I'd like to compare it > with > > yours. Do you have any good examples of those fairly large > functions > > that are just flat sequences of instructions, anywhere from 100 to > > 10000+ in size??? It would be nice, if you could send me those test > > cases (as C or ll files). I could use it then as a basis for a > > comparision and report about results. > > > > > The good news is the new "BigBlock" allocator turns out to > > > produce even better code than the local allocator when blocks > are > > very > > > large. We're talking a +10~20% speed boost on average. (If your > > basic > > > > > blocks are small, or there's not much register pressure, you'll > > > actually get the same code out of both local and BigBlock.) > > > > Do you have numbers comparing it to the current version of the > LLVM's > > linear scan? The win of your allocator over the linear scan should > be > > even better, I guess. > > > > > > > While BigBlock isn't (and never will be) as fast as the local > > > allocator, it's not much slower, doesn't use much memory, and is > > > certainly faster than linearscan. So if you're compiling very > > large, > > > (probably) machine-generated blocks of straight-line code, give > the > > > > > Local and BigBlock allocators a try, especially if you're JITing > > > things and compile time is important. > > > > I looked at your code. And I see some things that could be > > significantlty sped up, e.g. > > - InsnTimes handling. I have the feeling, this map can be > eliminated > > completely. > > - use of the VRegReadTable. The vector of read occurences can be > > shortened every time, you processed the corresponding intruction. > > This > > makes it shorter and makes searches inside this vector faster, thus > > making chooseReg much faster. Probably also some other > optimizations > > can be applied to the chooseReg function. > > - PhysRegsUseOrder - you remove some elements from the middle of > > this > > vector in removePhysReg. This is not a very efficient operation on > > the > > vectors, since it need to copy the tail of the vector. I think > using > > a > > list data-structure could be much more efficient for this purpose > > > > I think these changes may significantely improve the performance of > > your BigBlock register allocator. I'll try to come up with some > more > > concrete proposals or even patches over the week-end or next week. > > > > -Roman __________________________________________________ Do You Yahoo!? Sie sind Spam leid? Yahoo! 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