From reid at x10sys.com Mon Jul 2 01:16:33 2007 From: reid at x10sys.com (Reid Spencer) Date: Mon, 02 Jul 2007 06:16:33 -0000 Subject: [llvm-commits] [llvm] r37836 - /llvm/trunk/utils/NewNightlyTest.pl Message-ID: <200707020616.l626GXOS000374@zion.cs.uiuc.edu> Author: reid Date: Mon Jul 2 01:16:32 2007 New Revision: 37836 URL: http://llvm.org/viewvc/llvm-project?rev=37836&view=rev Log: We want the Subversion checkout to succeed even if we don't specify the -verbose option! Doh! Modified: llvm/trunk/utils/NewNightlyTest.pl Modified: llvm/trunk/utils/NewNightlyTest.pl URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/NewNightlyTest.pl?rev=37836&r1=37835&r2=37836&view=diff ============================================================================== --- llvm/trunk/utils/NewNightlyTest.pl (original) +++ llvm/trunk/utils/NewNightlyTest.pl Mon Jul 2 01:16:32 2007 @@ -513,24 +513,24 @@ # ############################################################## if (!$NOCHECKOUT) { - if ( $VERBOSE ) { - print "CHECKOUT STAGE:\n"; - } + if ( $VERBOSE ) { print "CHECKOUT STAGE:\n"; } if ($USESVN) { my $SVNCMD = "$NICE svn co $SVNURL"; if ($VERBOSE) { print "( time -p $SVNCMD/llvm/trunk llvm; cd llvm/projects ; " . "$SVNCMD/test-suite/trunk llvm-test ) > $COLog 2>&1\n"; - system "( time -p $SVNCMD/llvm/trunk llvm; cd llvm/projects ; " . - "$SVNCMD/test-suite/trunk llvm-test ) > $COLog 2>&1\n"; } + system "( time -p $SVNCMD/llvm/trunk llvm; cd llvm/projects ; " . + "$SVNCMD/test-suite/trunk llvm-test ) > $COLog 2>&1\n"; } else { my $CVSOPT = ""; $CVSOPT = "-z3" # Use compression if going over ssh. if $CVSRootDir =~ /^:ext:/; my $CVSCMD = "$NICE cvs $CVSOPT -d $CVSRootDir co -P $CVSCOOPT"; - print "( time -p $CVSCMD llvm; cd llvm/projects ; " . - "$CVSCMD llvm-test ) > $COLog 2>&1\n"; + if ($VERBOSE) { + print "( time -p $CVSCMD llvm; cd llvm/projects ; " . + "$CVSCMD llvm-test ) > $COLog 2>&1\n"; + } system "( time -p $CVSCMD llvm; cd llvm/projects ; " . "$CVSCMD llvm-test ) > $COLog 2>&1\n"; } From reid at x10sys.com Mon Jul 2 01:19:57 2007 From: reid at x10sys.com (Reid Spencer) Date: Mon, 02 Jul 2007 06:19:57 -0000 Subject: [llvm-commits] [llvm] r37837 - /llvm/trunk/utils/NewNightlyTest.pl Message-ID: <200707020619.l626JvUv000490@zion.cs.uiuc.edu> Author: reid Date: Mon Jul 2 01:19:57 2007 New Revision: 37837 URL: http://llvm.org/viewvc/llvm-project?rev=37837&view=rev Log: Remove the last vestiges of -usesvn. Implement -usecvs just in case we need to go back to cvs for some reason. Modified: llvm/trunk/utils/NewNightlyTest.pl Modified: llvm/trunk/utils/NewNightlyTest.pl URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/NewNightlyTest.pl?rev=37837&r1=37836&r2=37837&view=diff ============================================================================== --- llvm/trunk/utils/NewNightlyTest.pl (original) +++ llvm/trunk/utils/NewNightlyTest.pl Mon Jul 2 01:19:57 2007 @@ -45,10 +45,8 @@ # -gccpath Path to gcc/g++ used to build LLVM # -cvstag Check out a specific CVS tag to build LLVM (useful for # testing release branches) -# -usesvn Check code out from a subversion repository. -# -svnurl Specify the SVN URL where LLVM can be found. Needs -usesvn -# to be useful. If -svnurl is not used but -usesvn is then -# the standard (UIUC) repository will be used. +# -usecvs Check code out from the (old) CVS Repository instead of from +# the standard Subversion repository. # -target Specify the target triplet # -cflags Next argument specifies that C compilation options that # override the default. @@ -170,7 +168,7 @@ else { $GCCPATH=""; } if (/^-cvstag/) { $CVSCOOPT .= " -r $ARGV[0]"; shift; next; } else { $CVSCOOPT="";} - if (/^-svnurl/) { $SVNURL = $ARGV[0]; shift; next; } + if (/^-usecvs/) { $USESVN = 0; } if (/^-target/) { $CONFIGUREARGS .= " --target=$ARGV[0]"; shift; next; } if (/^-cflags/) { $MAKEOPTS = "$MAKEOPTS C.Flags=\'$ARGV[0]\'"; From zhousheng00 at gmail.com Mon Jul 2 03:02:15 2007 From: zhousheng00 at gmail.com (Zhou Sheng) Date: Mon, 02 Jul 2007 08:02:15 -0000 Subject: [llvm-commits] [llvm] r37838 - /llvm/trunk/test/Transforms/IndVarsSimplify/iterationCount_zext_or_trunc.ll Message-ID: <200707020802.l6282F5Y012575@zion.cs.uiuc.edu> Author: sheng Date: Mon Jul 2 03:02:14 2007 New Revision: 37838 URL: http://llvm.org/viewvc/llvm-project?rev=37838&view=rev Log: Test case for recent patch for IndVarSimplify.cpp Added: llvm/trunk/test/Transforms/IndVarsSimplify/iterationCount_zext_or_trunc.ll Added: llvm/trunk/test/Transforms/IndVarsSimplify/iterationCount_zext_or_trunc.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarsSimplify/iterationCount_zext_or_trunc.ll?rev=37838&view=auto ============================================================================== --- llvm/trunk/test/Transforms/IndVarsSimplify/iterationCount_zext_or_trunc.ll (added) +++ llvm/trunk/test/Transforms/IndVarsSimplify/iterationCount_zext_or_trunc.ll Mon Jul 2 03:02:14 2007 @@ -0,0 +1,25 @@ +; RUN: llvm-as < %s | opt -indvars -disable-output + +; ModuleID = 'testcase.bc' +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64" +target triple = "i686-pc-linux-gnu" + +define i32 @testcase(i5 zext %k) { +entry: + br label %bb2 + +bb: ; preds = %bb2 + %tmp1 = add i32 %tmp2, %result ; [#uses=1] + %indvar_next1 = add i5 %k_0, 1 ; [#uses=1] + br label %bb2 + +bb2: ; preds = %bb, %entry + %k_0 = phi i5 [ 0, %entry ], [ %indvar_next1, %bb ] ; [#uses=2] + %result = phi i32 [ 0, %entry ], [ %tmp1, %bb ] ; [#uses=2] + %tmp2 = zext i5 %k_0 to i32 ; [#uses=1] + %exitcond = icmp eq i32 %tmp2, 16 ; [#uses=1] + br i1 %exitcond, label %bb3, label %bb + +bb3: ; preds = %bb2 + ret i32 %result +} From djg at cray.com Mon Jul 2 09:53:38 2007 From: djg at cray.com (Dan Gohman) Date: Mon, 02 Jul 2007 14:53:38 -0000 Subject: [llvm-commits] [llvm] r37839 - in /llvm/trunk: include/llvm/Analysis/LoopPass.h include/llvm/CallGraphSCCPass.h include/llvm/CodeGen/MachineFunctionPass.h lib/Analysis/BasicAliasAnalysis.cpp lib/Analysis/CFGPrinter.cpp Message-ID: <200707021453.l62ErcOj026620@zion.cs.uiuc.edu> Author: djg Date: Mon Jul 2 09:53:37 2007 New Revision: 37839 URL: http://llvm.org/viewvc/llvm-project?rev=37839&view=rev Log: Add explicit keywords. Modified: llvm/trunk/include/llvm/Analysis/LoopPass.h llvm/trunk/include/llvm/CallGraphSCCPass.h llvm/trunk/include/llvm/CodeGen/MachineFunctionPass.h llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp llvm/trunk/lib/Analysis/CFGPrinter.cpp Modified: llvm/trunk/include/llvm/Analysis/LoopPass.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/LoopPass.h?rev=37839&r1=37838&r2=37839&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/LoopPass.h (original) +++ llvm/trunk/include/llvm/Analysis/LoopPass.h Mon Jul 2 09:53:37 2007 @@ -29,9 +29,9 @@ class LoopPass : public Pass { public: - LoopPass(intptr_t pid) : Pass(pid) {} + explicit LoopPass(intptr_t pid) : Pass(pid) {} - // runOnLoop - THis method should be implemented by the subclass to perform + // runOnLoop - This method should be implemented by the subclass to perform // whatever action is necessary for the specfied Loop. virtual bool runOnLoop (Loop *L, LPPassManager &LPM) = 0; virtual bool runOnFunctionBody (Function &F, LPPassManager &LPM) { Modified: llvm/trunk/include/llvm/CallGraphSCCPass.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CallGraphSCCPass.h?rev=37839&r1=37838&r2=37839&view=diff ============================================================================== --- llvm/trunk/include/llvm/CallGraphSCCPass.h (original) +++ llvm/trunk/include/llvm/CallGraphSCCPass.h Mon Jul 2 09:53:37 2007 @@ -31,7 +31,7 @@ struct CallGraphSCCPass : public Pass { - CallGraphSCCPass(intptr_t pid) : Pass(pid) {} + explicit CallGraphSCCPass(intptr_t pid) : Pass(pid) {} /// doInitialization - This method is called before the SCC's of the program /// has been processed, allowing the pass to do initialization as necessary. Modified: llvm/trunk/include/llvm/CodeGen/MachineFunctionPass.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineFunctionPass.h?rev=37839&r1=37838&r2=37839&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineFunctionPass.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineFunctionPass.h Mon Jul 2 09:53:37 2007 @@ -26,7 +26,7 @@ struct MachineFunctionPass : public FunctionPass { - MachineFunctionPass(intptr_t ID) : FunctionPass(ID) {} + explicit MachineFunctionPass(intptr_t ID) : FunctionPass(ID) {} /// runOnMachineFunction - This method must be overloaded to perform the /// desired machine code transformation or analysis. Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp?rev=37839&r1=37838&r2=37839&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Mon Jul 2 09:53:37 2007 @@ -38,7 +38,7 @@ struct VISIBILITY_HIDDEN NoAA : public ImmutablePass, public AliasAnalysis { static char ID; // Class identification, replacement for typeinfo NoAA() : ImmutablePass((intptr_t)&ID) {} - NoAA(intptr_t PID) : ImmutablePass(PID) { } + explicit NoAA(intptr_t PID) : ImmutablePass(PID) { } virtual void getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequired(); Modified: llvm/trunk/lib/Analysis/CFGPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/CFGPrinter.cpp?rev=37839&r1=37838&r2=37839&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/CFGPrinter.cpp (original) +++ llvm/trunk/lib/Analysis/CFGPrinter.cpp Mon Jul 2 09:53:37 2007 @@ -135,7 +135,7 @@ struct VISIBILITY_HIDDEN CFGPrinter : public FunctionPass { static char ID; // Pass identification, replacement for typeid CFGPrinter() : FunctionPass((intptr_t)&ID) {} - CFGPrinter(intptr_t pid) : FunctionPass(pid) {} + explicit CFGPrinter(intptr_t pid) : FunctionPass(pid) {} virtual bool runOnFunction(Function &F) { std::string Filename = "cfg." + F.getName() + ".dot"; From djg at cray.com Mon Jul 2 10:06:26 2007 From: djg at cray.com (Dan Gohman) Date: Mon, 02 Jul 2007 15:06:26 -0000 Subject: [llvm-commits] [llvm] r37840 - in /llvm/trunk/include/llvm/CodeGen: InstrScheduling.h Passes.h Message-ID: <200707021506.l62F6Q3T026983@zion.cs.uiuc.edu> Author: djg Date: Mon Jul 2 10:06:26 2007 New Revision: 37840 URL: http://llvm.org/viewvc/llvm-project?rev=37840&view=rev Log: Remove declarations for code no longer in the tree, to avoid confusion. Removed: llvm/trunk/include/llvm/CodeGen/InstrScheduling.h Modified: llvm/trunk/include/llvm/CodeGen/Passes.h Removed: llvm/trunk/include/llvm/CodeGen/InstrScheduling.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/InstrScheduling.h?rev=37839&view=auto ============================================================================== --- llvm/trunk/include/llvm/CodeGen/InstrScheduling.h (original) +++ llvm/trunk/include/llvm/CodeGen/InstrScheduling.h (removed) @@ -1,37 +0,0 @@ -//===-- InstrScheduling.h - Interface To Instruction Scheduling -*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file was developed by the LLVM research group and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file defines a minimal, but complete, interface to instruction -// scheduling. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_CODEGEN_INSTR_SCHEDULING_H -#define LLVM_CODEGEN_INSTR_SCHEDULING_H - -namespace llvm { - -class FunctionPass; -class TargetMachine; - -//--------------------------------------------------------------------------- -// Function: createScheduleInstructionsWithSSAPass(..) -// -// Purpose: -// Entry point for instruction scheduling on SSA form. -// Schedules the machine instructions generated by instruction selection. -// Assumes that register allocation has not been done, i.e., operands -// are still in SSA form. -//--------------------------------------------------------------------------- - -FunctionPass *createInstructionSchedulingWithSSAPass(const TargetMachine &TM); - -} // End llvm namespace - -#endif Modified: llvm/trunk/include/llvm/CodeGen/Passes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/Passes.h?rev=37840&r1=37839&r2=37840&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/Passes.h (original) +++ llvm/trunk/include/llvm/CodeGen/Passes.h Mon Jul 2 10:06:26 2007 @@ -112,12 +112,6 @@ /// for the Sparc. FunctionPass *getRegisterAllocator(TargetMachine &T); - //createModuloSchedulingPass - Creates the Swing Modulo Scheduling Pass - FunctionPass *createModuloSchedulingPass(TargetMachine & targ); - - //createModuloSchedulingPass - Creates the Swing Modulo Scheduling Pass - FunctionPass *createModuloSchedulingSBPass(TargetMachine & targ); - } // End llvm namespace #endif From djg at cray.com Mon Jul 2 10:43:21 2007 From: djg at cray.com (Dan Gohman) Date: Mon, 02 Jul 2007 15:43:21 -0000 Subject: [llvm-commits] [llvm] r37841 - /llvm/trunk/test/CodeGen/X86/negative-sin.ll Message-ID: <200707021543.l62FhLZG028059@zion.cs.uiuc.edu> Author: djg Date: Mon Jul 2 10:43:20 2007 New Revision: 37841 URL: http://llvm.org/viewvc/llvm-project?rev=37841&view=rev Log: New test case. DAGCombiner should be able to fold -sin(-x) in -enable-unsafe-fp-math mode. Added: llvm/trunk/test/CodeGen/X86/negative-sin.ll Added: llvm/trunk/test/CodeGen/X86/negative-sin.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/negative-sin.ll?rev=37841&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/negative-sin.ll (added) +++ llvm/trunk/test/CodeGen/X86/negative-sin.ll Mon Jul 2 10:43:20 2007 @@ -0,0 +1,12 @@ +; RUN: llvm-as < %s | llc -enable-unsafe-fp-math -march=x86-64 | \ +; RUN: not egrep {addsd|subsd|xor} + +declare double @sin(double %f) + +define double @foo(double %e) +{ + %f = sub double 0.0, %e + %g = call double @sin(double %f) + %h = sub double 0.0, %g + ret double %h +} From djg at cray.com Mon Jul 2 10:48:56 2007 From: djg at cray.com (Dan Gohman) Date: Mon, 02 Jul 2007 15:48:56 -0000 Subject: [llvm-commits] [llvm] r37842 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <200707021548.l62Fmvlw028181@zion.cs.uiuc.edu> Author: djg Date: Mon Jul 2 10:48:56 2007 New Revision: 37842 URL: http://llvm.org/viewvc/llvm-project?rev=37842&view=rev Log: Teach GetNegatedExpression to negate 0-B to B in UnsafeFPMath mode, and visitFSUB to fold 0-B to -B in UnsafeFPMath mode. Also change visitFNEG to use isNegatibleForFree/GetNegatedExpression instead of doing a subset of the same thing manually. This fixes test/CodeGen/X86/negative-sin.ll. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=37842&r1=37841&r2=37842&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Jul 2 10:48:56 2007 @@ -429,6 +429,11 @@ case ISD::FSUB: // We can't turn -(A-B) into B-A when we honor signed zeros. assert(UnsafeFPMath); + + // -(0-B) -> B + if (ConstantFPSDNode *N0CFP = dyn_cast(Op.getOperand(0))) + if (N0CFP->getValue() == 0.0) + return Op.getOperand(1); // -(A-B) -> B-A return DAG.getNode(ISD::FSUB, Op.getValueType(), Op.getOperand(1), @@ -3025,6 +3030,12 @@ // fold (fsub c1, c2) -> c1-c2 if (N0CFP && N1CFP) return DAG.getNode(ISD::FSUB, VT, N0, N1); + // fold (0-B) -> -B + if (UnsafeFPMath && N0CFP && N0CFP->getValue() == 0.0) { + if (isNegatibleForFree(N1)) + return GetNegatedExpression(N1, DAG); + return DAG.getNode(ISD::FNEG, VT, N1); + } // fold (A-(-B)) -> A+B if (isNegatibleForFree(N1)) return DAG.getNode(ISD::FADD, VT, N0, GetNegatedExpression(N1, DAG)); @@ -3297,18 +3308,10 @@ SDOperand DAGCombiner::visitFNEG(SDNode *N) { SDOperand N0 = N->getOperand(0); - ConstantFPSDNode *N0CFP = dyn_cast(N0); - MVT::ValueType VT = N->getValueType(0); - // fold (fneg c1) -> -c1 - if (N0CFP) - return DAG.getNode(ISD::FNEG, VT, N0); - // fold (fneg (sub x, y)) -> (sub y, x) - if (N0.getOpcode() == ISD::SUB) - return DAG.getNode(ISD::SUB, VT, N0.getOperand(1), N0.getOperand(0)); - // fold (fneg (fneg x)) -> x - if (N0.getOpcode() == ISD::FNEG) - return N0.getOperand(0); + if (isNegatibleForFree(N0)) + return GetNegatedExpression(N0, DAG); + return SDOperand(); } From djg at cray.com Mon Jul 2 11:18:06 2007 From: djg at cray.com (Dan Gohman) Date: Mon, 02 Jul 2007 16:18:06 -0000 Subject: [llvm-commits] [llvm] r37843 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Message-ID: <200707021618.l62GI6GA029325@zion.cs.uiuc.edu> Author: djg Date: Mon Jul 2 11:18:06 2007 New Revision: 37843 URL: http://llvm.org/viewvc/llvm-project?rev=37843&view=rev Log: Replace ExpandScalarFormalArgs and ExpandScalarCallArgs with the newly refactored getCopyFromParts and getCopyToParts, which are more general. This effectively adds support for lowering illegal by-val vector call arguments. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=37843&r1=37842&r2=37843&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon Jul 2 11:18:06 2007 @@ -2861,7 +2861,7 @@ if (!MVT::isVector(ValueVT) || NumParts == 1) { // If the value was expanded, copy from the parts. if (NumParts > 1) { - for (unsigned i = 0; i < NumParts; ++i) + for (unsigned i = 0; i != NumParts; ++i) Parts[i] = DAG.getNode(ISD::EXTRACT_ELEMENT, PartVT, Val, DAG.getConstant(i, MVT::i32)); return; @@ -2950,7 +2950,7 @@ // Copy the legal parts from the registers. unsigned NumParts = Regs.size(); SmallVector Parts(NumParts); - for (unsigned i = 0; i < NumParts; ++i) { + for (unsigned i = 0; i != NumParts; ++i) { SDOperand Part = Flag ? DAG.getCopyFromReg(Chain, Regs[i], RegVT, *Flag) : DAG.getCopyFromReg(Chain, Regs[i], RegVT); @@ -2981,7 +2981,7 @@ getCopyToParts(DAG, Val, &Parts[0], NumParts, RegVT); // Copy the parts into the registers. - for (unsigned i = 0; i < NumParts; ++i) { + for (unsigned i = 0; i != NumParts; ++i) { SDOperand Part = Flag ? DAG.getCopyToReg(Chain, R[i], Parts[i], *Flag) : DAG.getCopyToReg(Chain, R[i], Parts[i]); @@ -3746,32 +3746,6 @@ DAG.getSrcValue(I.getOperand(2)))); } -/// ExpandScalarFormalArgs - Recursively expand the formal_argument node, either -/// bit_convert it or join a pair of them with a BUILD_PAIR when appropriate. -static SDOperand ExpandScalarFormalArgs(MVT::ValueType VT, SDNode *Arg, - unsigned &i, SelectionDAG &DAG, - TargetLowering &TLI) { - if (TLI.getTypeAction(VT) != TargetLowering::Expand) - return SDOperand(Arg, i++); - - MVT::ValueType EVT = TLI.getTypeToTransformTo(VT); - unsigned NumVals = MVT::getSizeInBits(VT) / MVT::getSizeInBits(EVT); - if (NumVals == 1) { - return DAG.getNode(ISD::BIT_CONVERT, VT, - ExpandScalarFormalArgs(EVT, Arg, i, DAG, TLI)); - } else if (NumVals == 2) { - SDOperand Lo = ExpandScalarFormalArgs(EVT, Arg, i, DAG, TLI); - SDOperand Hi = ExpandScalarFormalArgs(EVT, Arg, i, DAG, TLI); - if (!TLI.isLittleEndian()) - std::swap(Lo, Hi); - return DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); - } else { - // Value scalarized into many values. Unimp for now. - assert(0 && "Cannot expand i64 -> i16 yet!"); - } - return SDOperand(); -} - /// TargetLowering::LowerArguments - This is the default LowerArguments /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be @@ -3842,8 +3816,8 @@ SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, DAG.getNodeValueTypes(RetVals), RetVals.size(), &Ops[0], Ops.size()).Val; - - DAG.setRoot(SDOperand(Result, Result->getNumValues()-1)); + unsigned NumArgRegs = Result->getNumValues() - 1; + DAG.setRoot(SDOperand(Result, NumArgRegs)); // Set up the return result vector. Ops.clear(); @@ -3875,79 +3849,22 @@ Ops.push_back(Op); break; } - case Expand: - if (!MVT::isVector(VT)) { - // If this is a large integer or a floating point node that needs to be - // expanded, it needs to be reassembled from small integers. Figure out - // what the source elt type is and how many small integers it is. - Ops.push_back(ExpandScalarFormalArgs(VT, Result, i, DAG, *this)); - } else { - // Otherwise, this is a vector type. We only support legal vectors - // right now. - const VectorType *PTy = cast(I->getType()); - unsigned NumElems = PTy->getNumElements(); - const Type *EltTy = PTy->getElementType(); - - // Figure out if there is a Packed type corresponding to this Vector - // type. If so, convert to the vector type. - MVT::ValueType TVT = - MVT::getVectorType(getValueType(EltTy), NumElems); - if (TVT != MVT::Other && isTypeLegal(TVT)) { - SDOperand N = SDOperand(Result, i++); - // Handle copies from vectors to registers. - N = DAG.getNode(ISD::BIT_CONVERT, TVT, N); - Ops.push_back(N); - } else { - assert(0 && "Don't support illegal by-val vector arguments yet!"); - abort(); - } - } + case Expand: { + MVT::ValueType PartVT = getRegisterType(VT); + unsigned NumParts = getNumRegisters(VT); + SmallVector Parts(NumParts); + for (unsigned j = 0; j != NumParts; ++j) + Parts[j] = SDOperand(Result, i++); + Ops.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT)); break; } + } } + assert(i == NumArgRegs && "Argument register count mismatch!"); return Ops; } -/// ExpandScalarCallArgs - Recursively expand call argument node by -/// bit_converting it or extract a pair of elements from the larger node. -static void ExpandScalarCallArgs(MVT::ValueType VT, SDOperand Arg, - unsigned Flags, - SmallVector &Ops, - SelectionDAG &DAG, - TargetLowering &TLI, - bool isFirst = true) { - - if (TLI.getTypeAction(VT) != TargetLowering::Expand) { - // if it isn't first piece, alignment must be 1 - if (!isFirst) - Flags = (Flags & (~ISD::ParamFlags::OrigAlignment)) | - (1 << ISD::ParamFlags::OrigAlignmentOffs); - Ops.push_back(Arg); - Ops.push_back(DAG.getConstant(Flags, MVT::i32)); - return; - } - - MVT::ValueType EVT = TLI.getTypeToTransformTo(VT); - unsigned NumVals = MVT::getSizeInBits(VT) / MVT::getSizeInBits(EVT); - if (NumVals == 1) { - Arg = DAG.getNode(ISD::BIT_CONVERT, EVT, Arg); - ExpandScalarCallArgs(EVT, Arg, Flags, Ops, DAG, TLI, isFirst); - } else if (NumVals == 2) { - SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, EVT, Arg, - DAG.getConstant(0, TLI.getPointerTy())); - SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, EVT, Arg, - DAG.getConstant(1, TLI.getPointerTy())); - if (!TLI.isLittleEndian()) - std::swap(Lo, Hi); - ExpandScalarCallArgs(EVT, Lo, Flags, Ops, DAG, TLI, isFirst); - ExpandScalarCallArgs(EVT, Hi, Flags, Ops, DAG, TLI, false); - } else { - // Value scalarized into many values. Unimp for now. - assert(0 && "Cannot expand i64 -> i16 yet!"); - } -} - /// TargetLowering::LowerCallTo - This is the default LowerCallTo /// implementation, which just inserts an ISD::CALL node, which is later custom /// lowered by the target to something concrete. FIXME: When all targets are @@ -4014,35 +3931,24 @@ Ops.push_back(Op); Ops.push_back(DAG.getConstant(Flags, MVT::i32)); break; - case Expand: - if (!MVT::isVector(VT)) { - // If this is a large integer, it needs to be broken down into small - // integers. Figure out what the source elt type is and how many small - // integers it is. - ExpandScalarCallArgs(VT, Op, Flags, Ops, DAG, *this); - } else { - // Otherwise, this is a vector type. We only support legal vectors - // right now. - const VectorType *PTy = cast(Args[i].Ty); - unsigned NumElems = PTy->getNumElements(); - const Type *EltTy = PTy->getElementType(); - - // Figure out if there is a Packed type corresponding to this Vector - // type. If so, convert to the vector type. - MVT::ValueType TVT = - MVT::getVectorType(getValueType(EltTy), NumElems); - if (TVT != MVT::Other && isTypeLegal(TVT)) { - // Insert a BIT_CONVERT of the original type to the vector type. - Op = DAG.getNode(ISD::BIT_CONVERT, TVT, Op); - Ops.push_back(Op); - Ops.push_back(DAG.getConstant(Flags, MVT::i32)); - } else { - assert(0 && "Don't support illegal by-val vector call args yet!"); - abort(); - } + case Expand: { + MVT::ValueType PartVT = getRegisterType(VT); + unsigned NumParts = getNumRegisters(VT); + SmallVector Parts(NumParts); + getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT); + for (unsigned i = 0; i != NumParts; ++i) { + // if it isn't first piece, alignment must be 1 + unsigned MyFlags = Flags; + if (i != 0) + MyFlags = (MyFlags & (~ISD::ParamFlags::OrigAlignment)) | + (1 << ISD::ParamFlags::OrigAlignmentOffs); + + Ops.push_back(Parts[i]); + Ops.push_back(DAG.getConstant(MyFlags, MVT::i32)); } break; } + } } // Figure out the result value types. @@ -4360,7 +4266,7 @@ // Copy the value by legal parts into sequential virtual registers. getCopyToParts(DAG, Op, &Regs[0], NumRegs, RegisterVT); - for (unsigned i = 0; i < NumRegs; ++i) + for (unsigned i = 0; i != NumRegs; ++i) Chains[i] = DAG.getCopyToReg(getRoot(), Reg + i, Regs[i]); return DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs); } From djg at cray.com Mon Jul 2 11:21:53 2007 From: djg at cray.com (Dan Gohman) Date: Mon, 02 Jul 2007 16:21:53 -0000 Subject: [llvm-commits] [llvm] r37844 - /llvm/trunk/lib/Target/X86/X86CallingConv.td Message-ID: <200707021621.l62GLsPM029629@zion.cs.uiuc.edu> Author: djg Date: Mon Jul 2 11:21:53 2007 New Revision: 37844 URL: http://llvm.org/viewvc/llvm-project?rev=37844&view=rev Log: Vector results may be returned in XMM0 and XMM1, not just XMM0. With the recent lowering changes, this allows types like <4 x double> to be returned, using two vector registers. Modified: llvm/trunk/lib/Target/X86/X86CallingConv.td Modified: llvm/trunk/lib/Target/X86/X86CallingConv.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CallingConv.td?rev=37844&r1=37843&r2=37844&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86CallingConv.td (original) +++ llvm/trunk/lib/Target/X86/X86CallingConv.td Mon Jul 2 11:21:53 2007 @@ -28,9 +28,10 @@ CCIfType<[i32], CCAssignToReg<[EAX, EDX]>>, CCIfType<[i64], CCAssignToReg<[RAX, RDX]>>, - // Vector types are always returned in XMM0. If the target doesn't have XMM0, - // it won't have vector types. - CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToReg<[XMM0]>>, + // Vector types are returned in XMM0 and XMM1, when they fit. If the target + // doesn't have XMM registers, it won't have vector types. + CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], + CCAssignToReg<[XMM0,XMM1]>>, // MMX vector types are always returned in MM0. If the target doesn't have // MM0, it doesn't support these vector types. From djg at cray.com Mon Jul 2 11:23:47 2007 From: djg at cray.com (Dan Gohman) Date: Mon, 02 Jul 2007 16:23:47 -0000 Subject: [llvm-commits] [llvm] r37845 - /llvm/trunk/test/CodeGen/X86/illegal-vector-args-return.ll Message-ID: <200707021623.l62GNlaG029742@zion.cs.uiuc.edu> Author: djg Date: Mon Jul 2 11:23:47 2007 New Revision: 37845 URL: http://llvm.org/viewvc/llvm-project?rev=37845&view=rev Log: Add a basic test-case for passing and returning <4 x double> and <8 x float> values on X86. Added: llvm/trunk/test/CodeGen/X86/illegal-vector-args-return.ll Added: llvm/trunk/test/CodeGen/X86/illegal-vector-args-return.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/illegal-vector-args-return.ll?rev=37845&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/illegal-vector-args-return.ll (added) +++ llvm/trunk/test/CodeGen/X86/illegal-vector-args-return.ll Mon Jul 2 11:23:47 2007 @@ -0,0 +1,14 @@ +; RUN: llvm-as < %s | llc -mattr=+sse2 | grep {mulpd %xmm3, %xmm1} +; RUN: llvm-as < %s | llc -mattr=+sse2 | grep {mulpd %xmm2, %xmm0} +; RUN: llvm-as < %s | llc -mattr=+sse2 | grep {addps %xmm3, %xmm1} +; RUN: llvm-as < %s | llc -mattr=+sse2 | grep {addps %xmm2, %xmm0} + +define <4 x double> @foo(<4 x double> %x, <4 x double> %z) { + %y = mul <4 x double> %x, %z + ret <4 x double> %y +} + +define <8 x float> @bar(<8 x float> %x, <8 x float> %z) { + %y = add <8 x float> %x, %z + ret <8 x float> %y +} From tonic at nondot.org Mon Jul 2 13:10:53 2007 From: tonic at nondot.org (Tanya Lattner) Date: Mon, 02 Jul 2007 18:10:53 -0000 Subject: [llvm-commits] [llvm] r37846 - /llvm/trunk/CREDITS.TXT Message-ID: <200707021810.l62IArba001515@zion.cs.uiuc.edu> Author: tbrethou Date: Mon Jul 2 13:10:52 2007 New Revision: 37846 URL: http://llvm.org/viewvc/llvm-project?rev=37846&view=rev Log: Testing commit. Modified: llvm/trunk/CREDITS.TXT Modified: llvm/trunk/CREDITS.TXT URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/CREDITS.TXT?rev=37846&r1=37845&r2=37846&view=diff ============================================================================== --- llvm/trunk/CREDITS.TXT (original) +++ llvm/trunk/CREDITS.TXT Mon Jul 2 13:10:52 2007 @@ -146,7 +146,7 @@ W: http://nondot.org/~sabre/ D: Primary architect of LLVM -N: Tanya Lattner (formerly Tanya Brethour) +N: Tanya Lattner (Tanya Brethour) E: tonic at nondot.org W: http://nondot.org/~tonic/ D: The initial llvm-ar tool, converted regression testsuite to dejagnu From clattner at apple.com Mon Jul 2 13:50:22 2007 From: clattner at apple.com (Chris Lattner) Date: Mon, 2 Jul 2007 11:50:22 -0700 Subject: [llvm-commits] CVS: llvm/include/llvm/CodeGen/CallingConvLower.h SelectionDAG.h SelectionDAGNodes.h ValueTypes.h In-Reply-To: <20070629194748.GS5693@village.us.cray.com> References: <20070629194748.GS5693@village.us.cray.com> Message-ID: <98A64F8D-BF44-4A48-A173-CB52BCFF7538@apple.com> On Jun 29, 2007, at 12:47 PM, Dan Gohman wrote: >>> >>> I notice that several places use !MVT::isExtendedValueType(VT). >>> Please add MVT::isSimpleValueType() > > After making a different change to TargetLowering.h following the > review feedback, > there are fewer of these. Fewer uses of isExtendedVT are negated > than not now. > I'd prefer to avoid having two different names to do essentially > the same thing. Ok, nice work on 8 x float btw! -Chris From clattner at apple.com Mon Jul 2 13:53:51 2007 From: clattner at apple.com (Chris Lattner) Date: Mon, 2 Jul 2007 11:53:51 -0700 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp TargetLowering.cpp In-Reply-To: <20070629193833.GR5693@village.us.cray.com> References: <20070629193833.GR5693@village.us.cray.com> Message-ID: <0C341E52-0053-4CA9-9175-221B86599970@apple.com> On Jun 29, 2007, at 12:38 PM, Dan Gohman wrote: >>> Just as there isn't a special ADD node kind for vectors -- just >>> an ADD >>> kind with nodes that can have a vector ValueType, ConstantFP can >>> also >>> be "vectorized". A ConstantFP with a vector ValueType is a vector >>> constant, >>> equivalent to what is currently represented as a splat BUILD_VECTOR, >>> except that it's easier to work with :). >> >> I'm not opposed to doing this, but I don't think we should overload >> ConstantFP() and getConstantFP() for this. Could you make a new >> VectorConstantFP or something? > > We overload ISD::FADD and quite a lot of others. Why not > ISD::ConstantFP too? Fair enough, after pondering on it, I agree with you. The proposed semantics are that a ConstantFP (and also a normal Constant?) produce the splatted immediate value? If so, this sounds fine. This should also reduce codegen memory usage for many common cases, a very nice bonus :) Please add a dag combine xform from build_vector [c,c,c,c] -> constantfp and friends. Thanks Dan, -Chris From dalej at apple.com Mon Jul 2 19:53:03 2007 From: dalej at apple.com (Dale Johannesen) Date: Tue, 03 Jul 2007 00:53:03 -0000 Subject: [llvm-commits] [llvm] r37847 - in /llvm/trunk/lib: CodeGen/SelectionDAG/ Target/X86/ Message-ID: <200707030053.l630r4O3013545@zion.cs.uiuc.edu> Author: johannes Date: Mon Jul 2 19:53:03 2007 New Revision: 37847 URL: http://llvm.org/viewvc/llvm-project?rev=37847&view=rev Log: Fix for PR 1505 (and 1489). Rewrite X87 register model to include f32 variants. Some factoring improvments forthcoming. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86InstrFPStack.td llvm/trunk/lib/Target/X86/X86InstrInfo.cpp llvm/trunk/lib/Target/X86/X86InstrSSE.td llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp llvm/trunk/lib/Target/X86/X86RegisterInfo.td Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=37847&r1=37846&r2=37847&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Jul 2 19:53:03 2007 @@ -3016,11 +3016,33 @@ } break; + case ISD::FP_ROUND: + if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) == + TargetLowering::Expand) { + // The only way we can lower this is to turn it into a TRUNCSTORE, + // EXTLOAD pair, targetting a temporary location (a stack slot). + + // NOTE: there is a choice here between constantly creating new stack + // slots and always reusing the same one. We currently always create + // new ones, as reuse may inhibit scheduling. + MVT::ValueType VT = Op.getValueType(); // 32 + const Type *Ty = MVT::getTypeForValueType(VT); + uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty); + unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); + MachineFunction &MF = DAG.getMachineFunction(); + int SSFI = + MF.getFrameInfo()->CreateStackObject(TySize, Align); + SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); + Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0), + StackSlot, NULL, 0, VT); + Result = DAG.getLoad(VT, Result, StackSlot, NULL, 0, VT); + break; + } + // FALL THROUGH case ISD::ANY_EXTEND: case ISD::ZERO_EXTEND: case ISD::SIGN_EXTEND: case ISD::FP_EXTEND: - case ISD::FP_ROUND: switch (getTypeAction(Node->getOperand(0).getValueType())) { case Expand: assert(0 && "Shouldn't need to expand other operators here!"); case Legal: Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=37847&r1=37846&r2=37847&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon Jul 2 19:53:03 2007 @@ -3918,15 +3918,7 @@ Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op); } else { assert(MVT::isFloatingPoint(VT) && "Not int or FP?"); - // A true promotion would change the size of the argument. - // Instead, pretend this is an int. If FP objects are not - // passed the same as ints, the original type should be Legal - // and we should not get here. - Op = DAG.getNode(ISD::BIT_CONVERT, - VT==MVT::f32 ? MVT::i32 : - (VT==MVT::f64 ? MVT::i64 : - MVT::Other), - Op); + Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op); } Ops.push_back(Op); Ops.push_back(DAG.getConstant(Flags, MVT::i32)); Modified: llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp?rev=37847&r1=37846&r2=37847&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp Mon Jul 2 19:53:03 2007 @@ -324,61 +324,101 @@ // concrete X86 instruction which uses the register stack. // static const TableEntry OpcodeTable[] = { - { X86::FpABS , X86::FABS }, + { X86::FpABS32 , X86::FABS }, + { X86::FpABS64 , X86::FABS }, { X86::FpADD32m , X86::FADD32m }, { X86::FpADD64m , X86::FADD64m }, - { X86::FpCHS , X86::FCHS }, - { X86::FpCMOVB , X86::FCMOVB }, - { X86::FpCMOVBE , X86::FCMOVBE }, - { X86::FpCMOVE , X86::FCMOVE }, - { X86::FpCMOVNB , X86::FCMOVNB }, - { X86::FpCMOVNBE , X86::FCMOVNBE }, - { X86::FpCMOVNE , X86::FCMOVNE }, - { X86::FpCMOVNP , X86::FCMOVNP }, - { X86::FpCMOVP , X86::FCMOVP }, - { X86::FpCOS , X86::FCOS }, + { X86::FpCHS32 , X86::FCHS }, + { X86::FpCHS64 , X86::FCHS }, + { X86::FpCMOVB32 , X86::FCMOVB }, + { X86::FpCMOVB64 , X86::FCMOVB }, + { X86::FpCMOVBE32 , X86::FCMOVBE }, + { X86::FpCMOVBE64 , X86::FCMOVBE }, + { X86::FpCMOVE32 , X86::FCMOVE }, + { X86::FpCMOVE64 , X86::FCMOVE }, + { X86::FpCMOVNB32 , X86::FCMOVNB }, + { X86::FpCMOVNB64 , X86::FCMOVNB }, + { X86::FpCMOVNBE32 , X86::FCMOVNBE }, + { X86::FpCMOVNBE64 , X86::FCMOVNBE }, + { X86::FpCMOVNE32 , X86::FCMOVNE }, + { X86::FpCMOVNE64 , X86::FCMOVNE }, + { X86::FpCMOVNP32 , X86::FCMOVNP }, + { X86::FpCMOVNP64 , X86::FCMOVNP }, + { X86::FpCMOVP32 , X86::FCMOVP }, + { X86::FpCMOVP64 , X86::FCMOVP }, + { X86::FpCOS32 , X86::FCOS }, + { X86::FpCOS64 , X86::FCOS }, { X86::FpDIV32m , X86::FDIV32m }, { X86::FpDIV64m , X86::FDIV64m }, { X86::FpDIVR32m , X86::FDIVR32m }, { X86::FpDIVR64m , X86::FDIVR64m }, - { X86::FpIADD16m , X86::FIADD16m }, - { X86::FpIADD32m , X86::FIADD32m }, - { X86::FpIDIV16m , X86::FIDIV16m }, - { X86::FpIDIV32m , X86::FIDIV32m }, - { X86::FpIDIVR16m, X86::FIDIVR16m}, - { X86::FpIDIVR32m, X86::FIDIVR32m}, - { X86::FpILD16m , X86::FILD16m }, - { X86::FpILD32m , X86::FILD32m }, - { X86::FpILD64m , X86::FILD64m }, - { X86::FpIMUL16m , X86::FIMUL16m }, - { X86::FpIMUL32m , X86::FIMUL32m }, - { X86::FpIST16m , X86::FIST16m }, - { X86::FpIST32m , X86::FIST32m }, - { X86::FpIST64m , X86::FISTP64m }, - { X86::FpISTT16m , X86::FISTTP16m}, - { X86::FpISTT32m , X86::FISTTP32m}, - { X86::FpISTT64m , X86::FISTTP64m}, - { X86::FpISUB16m , X86::FISUB16m }, - { X86::FpISUB32m , X86::FISUB32m }, - { X86::FpISUBR16m, X86::FISUBR16m}, - { X86::FpISUBR32m, X86::FISUBR32m}, - { X86::FpLD0 , X86::FLD0 }, - { X86::FpLD1 , X86::FLD1 }, + { X86::FpIADD16m32 , X86::FIADD16m }, + { X86::FpIADD16m64 , X86::FIADD16m }, + { X86::FpIADD32m32 , X86::FIADD32m }, + { X86::FpIADD32m64 , X86::FIADD32m }, + { X86::FpIDIV16m32 , X86::FIDIV16m }, + { X86::FpIDIV16m64 , X86::FIDIV16m }, + { X86::FpIDIV32m32 , X86::FIDIV32m }, + { X86::FpIDIV32m64 , X86::FIDIV32m }, + { X86::FpIDIVR16m32, X86::FIDIVR16m}, + { X86::FpIDIVR16m64, X86::FIDIVR16m}, + { X86::FpIDIVR32m32, X86::FIDIVR32m}, + { X86::FpIDIVR32m64, X86::FIDIVR32m}, + { X86::FpILD16m32 , X86::FILD16m }, + { X86::FpILD16m64 , X86::FILD16m }, + { X86::FpILD32m32 , X86::FILD32m }, + { X86::FpILD32m64 , X86::FILD32m }, + { X86::FpILD64m32 , X86::FILD64m }, + { X86::FpILD64m64 , X86::FILD64m }, + { X86::FpIMUL16m32 , X86::FIMUL16m }, + { X86::FpIMUL16m64 , X86::FIMUL16m }, + { X86::FpIMUL32m32 , X86::FIMUL32m }, + { X86::FpIMUL32m64 , X86::FIMUL32m }, + { X86::FpIST16m32 , X86::FIST16m }, + { X86::FpIST16m64 , X86::FIST16m }, + { X86::FpIST32m32 , X86::FIST32m }, + { X86::FpIST32m64 , X86::FIST32m }, + { X86::FpIST64m32 , X86::FISTP64m }, + { X86::FpIST64m64 , X86::FISTP64m }, + { X86::FpISTT16m32 , X86::FISTTP16m}, + { X86::FpISTT16m64 , X86::FISTTP16m}, + { X86::FpISTT32m32 , X86::FISTTP32m}, + { X86::FpISTT32m64 , X86::FISTTP32m}, + { X86::FpISTT64m32 , X86::FISTTP64m}, + { X86::FpISTT64m64 , X86::FISTTP64m}, + { X86::FpISUB16m32 , X86::FISUB16m }, + { X86::FpISUB16m64 , X86::FISUB16m }, + { X86::FpISUB32m32 , X86::FISUB32m }, + { X86::FpISUB32m64 , X86::FISUB32m }, + { X86::FpISUBR16m32, X86::FISUBR16m}, + { X86::FpISUBR16m64, X86::FISUBR16m}, + { X86::FpISUBR32m32, X86::FISUBR32m}, + { X86::FpISUBR32m64, X86::FISUBR32m}, + { X86::FpLD032 , X86::FLD0 }, + { X86::FpLD064 , X86::FLD0 }, + { X86::FpLD132 , X86::FLD1 }, + { X86::FpLD164 , X86::FLD1 }, { X86::FpLD32m , X86::FLD32m }, { X86::FpLD64m , X86::FLD64m }, { X86::FpMUL32m , X86::FMUL32m }, { X86::FpMUL64m , X86::FMUL64m }, - { X86::FpSIN , X86::FSIN }, - { X86::FpSQRT , X86::FSQRT }, + { X86::FpSIN32 , X86::FSIN }, + { X86::FpSIN64 , X86::FSIN }, + { X86::FpSQRT32 , X86::FSQRT }, + { X86::FpSQRT64 , X86::FSQRT }, { X86::FpST32m , X86::FST32m }, { X86::FpST64m , X86::FST64m }, + { X86::FpST64m32 , X86::FST32m }, { X86::FpSUB32m , X86::FSUB32m }, { X86::FpSUB64m , X86::FSUB64m }, { X86::FpSUBR32m , X86::FSUBR32m }, { X86::FpSUBR64m , X86::FSUBR64m }, - { X86::FpTST , X86::FTST }, - { X86::FpUCOMIr , X86::FUCOMIr }, - { X86::FpUCOMr , X86::FUCOMr }, + { X86::FpTST32 , X86::FTST }, + { X86::FpTST64 , X86::FTST }, + { X86::FpUCOMIr32 , X86::FUCOMIr }, + { X86::FpUCOMIr64 , X86::FUCOMIr }, + { X86::FpUCOMr32 , X86::FUCOMr }, + { X86::FpUCOMr64 , X86::FUCOMr }, }; static unsigned getConcreteOpcode(unsigned Opcode) { @@ -510,10 +550,14 @@ // Ditto FISTTP16m, FISTTP32m, FISTTP64m. // if (!KillsSrc && - (MI->getOpcode() == X86::FpIST64m || - MI->getOpcode() == X86::FpISTT16m || - MI->getOpcode() == X86::FpISTT32m || - MI->getOpcode() == X86::FpISTT64m)) { + (MI->getOpcode() == X86::FpIST64m32 || + MI->getOpcode() == X86::FpISTT16m32 || + MI->getOpcode() == X86::FpISTT32m32 || + MI->getOpcode() == X86::FpISTT64m32 || + MI->getOpcode() == X86::FpIST64m64 || + MI->getOpcode() == X86::FpISTT16m64 || + MI->getOpcode() == X86::FpISTT32m64 || + MI->getOpcode() == X86::FpISTT64m64)) { duplicateToTop(Reg, 7 /*temp register*/, I); } else { moveToTop(Reg, I); // Move to the top of the stack... @@ -578,34 +622,50 @@ // ForwardST0Table - Map: A = B op C into: ST(0) = ST(0) op ST(i) static const TableEntry ForwardST0Table[] = { - { X86::FpADD , X86::FADDST0r }, - { X86::FpDIV , X86::FDIVST0r }, - { X86::FpMUL , X86::FMULST0r }, - { X86::FpSUB , X86::FSUBST0r }, + { X86::FpADD32 , X86::FADDST0r }, + { X86::FpADD64 , X86::FADDST0r }, + { X86::FpDIV32 , X86::FDIVST0r }, + { X86::FpDIV64 , X86::FDIVST0r }, + { X86::FpMUL32 , X86::FMULST0r }, + { X86::FpMUL64 , X86::FMULST0r }, + { X86::FpSUB32 , X86::FSUBST0r }, + { X86::FpSUB64 , X86::FSUBST0r }, }; // ReverseST0Table - Map: A = B op C into: ST(0) = ST(i) op ST(0) static const TableEntry ReverseST0Table[] = { - { X86::FpADD , X86::FADDST0r }, // commutative - { X86::FpDIV , X86::FDIVRST0r }, - { X86::FpMUL , X86::FMULST0r }, // commutative - { X86::FpSUB , X86::FSUBRST0r }, + { X86::FpADD32 , X86::FADDST0r }, // commutative + { X86::FpADD64 , X86::FADDST0r }, // commutative + { X86::FpDIV32 , X86::FDIVRST0r }, + { X86::FpDIV64 , X86::FDIVRST0r }, + { X86::FpMUL32 , X86::FMULST0r }, // commutative + { X86::FpMUL64 , X86::FMULST0r }, // commutative + { X86::FpSUB32 , X86::FSUBRST0r }, + { X86::FpSUB64 , X86::FSUBRST0r }, }; // ForwardSTiTable - Map: A = B op C into: ST(i) = ST(0) op ST(i) static const TableEntry ForwardSTiTable[] = { - { X86::FpADD , X86::FADDrST0 }, // commutative - { X86::FpDIV , X86::FDIVRrST0 }, - { X86::FpMUL , X86::FMULrST0 }, // commutative - { X86::FpSUB , X86::FSUBRrST0 }, + { X86::FpADD32 , X86::FADDrST0 }, // commutative + { X86::FpADD64 , X86::FADDrST0 }, // commutative + { X86::FpDIV32 , X86::FDIVRrST0 }, + { X86::FpDIV64 , X86::FDIVRrST0 }, + { X86::FpMUL32 , X86::FMULrST0 }, // commutative + { X86::FpMUL64 , X86::FMULrST0 }, // commutative + { X86::FpSUB32 , X86::FSUBRrST0 }, + { X86::FpSUB64 , X86::FSUBRrST0 }, }; // ReverseSTiTable - Map: A = B op C into: ST(i) = ST(i) op ST(0) static const TableEntry ReverseSTiTable[] = { - { X86::FpADD , X86::FADDrST0 }, - { X86::FpDIV , X86::FDIVrST0 }, - { X86::FpMUL , X86::FMULrST0 }, - { X86::FpSUB , X86::FSUBrST0 }, + { X86::FpADD32 , X86::FADDrST0 }, + { X86::FpADD64 , X86::FADDrST0 }, + { X86::FpDIV32 , X86::FDIVrST0 }, + { X86::FpDIV64 , X86::FDIVrST0 }, + { X86::FpMUL32 , X86::FMULrST0 }, + { X86::FpMUL64 , X86::FMULrST0 }, + { X86::FpSUB32 , X86::FSUBrST0 }, + { X86::FpSUB64 , X86::FSUBrST0 }, }; @@ -777,15 +837,20 @@ MachineInstr *MI = I; switch (MI->getOpcode()) { default: assert(0 && "Unknown SpecialFP instruction!"); - case X86::FpGETRESULT: // Appears immediately after a call returning FP type! + case X86::FpGETRESULT32: // Appears immediately after a call returning FP type! + case X86::FpGETRESULT64: // Appears immediately after a call returning FP type! assert(StackTop == 0 && "Stack should be empty after a call!"); pushReg(getFPReg(MI->getOperand(0))); break; - case X86::FpSETRESULT: + case X86::FpSETRESULT32: + case X86::FpSETRESULT64: assert(StackTop == 1 && "Stack should have one element on it to return!"); --StackTop; // "Forget" we have something on the top of stack! break; - case X86::FpMOV: { + case X86::FpMOV3232: + case X86::FpMOV3264: + case X86::FpMOV6432: + case X86::FpMOV6464: { unsigned SrcReg = getFPReg(MI->getOperand(1)); unsigned DestReg = getFPReg(MI->getOperand(0)); Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=37847&r1=37846&r2=37847&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Mon Jul 2 19:53:03 2007 @@ -492,11 +492,13 @@ for (MachineBasicBlock::iterator I = MBBI->begin(), E = MBBI->end(); !ContainsFPCode && I != E; ++I) { if (I->getNumOperands() != 0 && I->getOperand(0).isRegister()) { + const TargetRegisterClass *clas; for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op) { if (I->getOperand(op).isRegister() && I->getOperand(op).isDef() && MRegisterInfo::isVirtualRegister(I->getOperand(op).getReg()) && - RegMap->getRegClass(I->getOperand(0).getReg()) == - X86::RFPRegisterClass) { + ((clas = RegMap->getRegClass(I->getOperand(0).getReg())) == + X86::RFP32RegisterClass || + clas == X86::RFP64RegisterClass)) { ContainsFPCode = true; break; } Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=37847&r1=37846&r2=37847&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Jul 2 19:53:03 2007 @@ -289,11 +289,14 @@ addLegalFPImmediate(+0.0); // xorps / xorpd } else { // Set up the FP register classes. - addRegisterClass(MVT::f64, X86::RFPRegisterClass); + addRegisterClass(MVT::f64, X86::RFP64RegisterClass); + addRegisterClass(MVT::f32, X86::RFP32RegisterClass); setOperationAction(ISD::UNDEF, MVT::f64, Expand); + setOperationAction(ISD::UNDEF, MVT::f32, Expand); setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); + setOperationAction(ISD::FP_ROUND, MVT::f32, Expand); if (!UnsafeFPMath) { setOperationAction(ISD::FSIN , MVT::f64 , Expand); @@ -301,6 +304,7 @@ } setOperationAction(ISD::ConstantFP, MVT::f64, Expand); + setOperationAction(ISD::ConstantFP, MVT::f32, Expand); addLegalFPImmediate(+0.0); // FLD0 addLegalFPImmediate(+1.0); // FLD1 addLegalFPImmediate(-0.0); // FLD0/FCHS @@ -553,7 +557,7 @@ MemLoc = DAG.getFrameIndex(SSFI, getPointerTy()); Chain = DAG.getStore(Op.getOperand(0), Value, MemLoc, NULL, 0); } - SDVTList Tys = DAG.getVTList(MVT::f64, MVT::Other); + SDVTList Tys = DAG.getVTList(RVLocs[0].getValVT(), MVT::Other); SDOperand Ops[] = {Chain, MemLoc, DAG.getValueType(RVLocs[0].getValVT())}; Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3); Chain = Value.getValue(1); @@ -604,7 +608,7 @@ // before the fp stackifier runs. // Copy ST0 into an RFP register with FP_GET_RESULT. - SDVTList Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag); + SDVTList Tys = DAG.getVTList(RVLocs[0].getValVT(), MVT::Other, MVT::Flag); SDOperand GROps[] = { Chain, InFlag }; SDOperand RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, GROps, 2); Chain = RetVal.getValue(1); @@ -626,11 +630,6 @@ RetVal = DAG.getLoad(RVLocs[0].getValVT(), Chain, StackSlot, NULL, 0); Chain = RetVal.getValue(1); } - - if (RVLocs[0].getValVT() == MVT::f32 && !X86ScalarSSE) - // FIXME: we would really like to remember that this FP_ROUND - // operation is okay to eliminate if we allow excess FP precision. - RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal); ResultVals.push_back(RetVal); } @@ -3252,7 +3251,7 @@ if (X86ScalarSSE) Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag); else - Tys = DAG.getVTList(MVT::f64, MVT::Other); + Tys = DAG.getVTList(Op.getValueType(), MVT::Other); SmallVector Ops; Ops.push_back(Chain); Ops.push_back(StackSlot); @@ -3307,7 +3306,7 @@ if (X86ScalarSSE) { assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!"); Chain = DAG.getStore(Chain, Value, StackSlot, NULL, 0); - SDVTList Tys = DAG.getVTList(MVT::f64, MVT::Other); + SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); SDOperand Ops[] = { Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType()) }; @@ -4437,9 +4436,12 @@ return BB; } - case X86::FP_TO_INT16_IN_MEM: - case X86::FP_TO_INT32_IN_MEM: - case X86::FP_TO_INT64_IN_MEM: { + case X86::FP32_TO_INT16_IN_MEM: + case X86::FP32_TO_INT32_IN_MEM: + case X86::FP32_TO_INT64_IN_MEM: + case X86::FP64_TO_INT16_IN_MEM: + case X86::FP64_TO_INT32_IN_MEM: + case X86::FP64_TO_INT64_IN_MEM: { // Change the floating point control register to use "round towards zero" // mode when truncating to an integer value. MachineFunction *F = BB->getParent(); @@ -4466,9 +4468,12 @@ unsigned Opc; switch (MI->getOpcode()) { default: assert(0 && "illegal opcode!"); - case X86::FP_TO_INT16_IN_MEM: Opc = X86::FpIST16m; break; - case X86::FP_TO_INT32_IN_MEM: Opc = X86::FpIST32m; break; - case X86::FP_TO_INT64_IN_MEM: Opc = X86::FpIST64m; break; + case X86::FP32_TO_INT16_IN_MEM: Opc = X86::FpIST16m32; break; + case X86::FP32_TO_INT32_IN_MEM: Opc = X86::FpIST32m32; break; + case X86::FP32_TO_INT64_IN_MEM: Opc = X86::FpIST64m32; break; + case X86::FP64_TO_INT16_IN_MEM: Opc = X86::FpIST16m64; break; + case X86::FP64_TO_INT32_IN_MEM: Opc = X86::FpIST32m64; break; + case X86::FP64_TO_INT64_IN_MEM: Opc = X86::FpIST64m64; break; } X86AddressMode AM; Modified: llvm/trunk/lib/Target/X86/X86InstrFPStack.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFPStack.td?rev=37847&r1=37846&r2=37847&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrFPStack.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrFPStack.td Mon Jul 2 19:53:03 2007 @@ -17,13 +17,13 @@ // FPStack specific DAG Nodes. //===----------------------------------------------------------------------===// -def SDTX86FpGet : SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>; +def SDTX86FpGet : SDTypeProfile<1, 0, [SDTCisFP<0>]>; def SDTX86FpSet : SDTypeProfile<0, 1, [SDTCisFP<0>]>; -def SDTX86Fld : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, +def SDTX86Fld : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>]>; def SDTX86Fst : SDTypeProfile<0, 3, [SDTCisFP<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>]>; -def SDTX86Fild : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisPtrTy<1>, +def SDTX86Fild : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>]>; def SDTX86FpToIMem: SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>; @@ -50,19 +50,19 @@ // FPStack pattern fragments //===----------------------------------------------------------------------===// -def fp64imm0 : PatLeaf<(f64 fpimm), [{ +def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>; -def fp64immneg0 : PatLeaf<(f64 fpimm), [{ +def fpimmneg0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(-0.0); }]>; -def fp64imm1 : PatLeaf<(f64 fpimm), [{ +def fpimm1 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+1.0); }]>; -def fp64immneg1 : PatLeaf<(f64 fpimm), [{ +def fpimmneg1 : PatLeaf<(fpimm), [{ return N->isExactlyValue(-1.0); }]>; @@ -70,18 +70,30 @@ // Some 'special' instructions let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler. - def FP_TO_INT16_IN_MEM : I<0, Pseudo, - (ops i16mem:$dst, RFP:$src), - "#FP_TO_INT16_IN_MEM PSEUDO!", - [(X86fp_to_i16mem RFP:$src, addr:$dst)]>; - def FP_TO_INT32_IN_MEM : I<0, Pseudo, - (ops i32mem:$dst, RFP:$src), - "#FP_TO_INT32_IN_MEM PSEUDO!", - [(X86fp_to_i32mem RFP:$src, addr:$dst)]>; - def FP_TO_INT64_IN_MEM : I<0, Pseudo, - (ops i64mem:$dst, RFP:$src), - "#FP_TO_INT64_IN_MEM PSEUDO!", - [(X86fp_to_i64mem RFP:$src, addr:$dst)]>; + def FP32_TO_INT16_IN_MEM : I<0, Pseudo, + (ops i16mem:$dst, RFP32:$src), + "#FP32_TO_INT16_IN_MEM PSEUDO!", + [(X86fp_to_i16mem RFP32:$src, addr:$dst)]>; + def FP32_TO_INT32_IN_MEM : I<0, Pseudo, + (ops i32mem:$dst, RFP32:$src), + "#FP32_TO_INT32_IN_MEM PSEUDO!", + [(X86fp_to_i32mem RFP32:$src, addr:$dst)]>; + def FP32_TO_INT64_IN_MEM : I<0, Pseudo, + (ops i64mem:$dst, RFP32:$src), + "#FP32_TO_INT64_IN_MEM PSEUDO!", + [(X86fp_to_i64mem RFP32:$src, addr:$dst)]>; + def FP64_TO_INT16_IN_MEM : I<0, Pseudo, + (ops i16mem:$dst, RFP64:$src), + "#FP64_TO_INT16_IN_MEM PSEUDO!", + [(X86fp_to_i16mem RFP64:$src, addr:$dst)]>; + def FP64_TO_INT32_IN_MEM : I<0, Pseudo, + (ops i32mem:$dst, RFP64:$src), + "#FP64_TO_INT32_IN_MEM PSEUDO!", + [(X86fp_to_i32mem RFP64:$src, addr:$dst)]>; + def FP64_TO_INT64_IN_MEM : I<0, Pseudo, + (ops i64mem:$dst, RFP64:$src), + "#FP64_TO_INT64_IN_MEM PSEUDO!", + [(X86fp_to_i64mem RFP64:$src, addr:$dst)]>; } let isTerminator = 1 in @@ -111,30 +123,47 @@ } // Random Pseudo Instructions. -def FpGETRESULT : FpI_<(ops RFP:$dst), SpecialFP, - [(set RFP:$dst, X86fpget)]>; // FPR = ST(0) +def FpGETRESULT32 : FpI_<(ops RFP32:$dst), SpecialFP, + [(set RFP32:$dst, X86fpget)]>; // FPR = ST(0) -let noResults = 1 in - def FpSETRESULT : FpI_<(ops RFP:$src), SpecialFP, - [(X86fpset RFP:$src)]>, Imp<[], [ST0]>; // ST(0) = FPR +def FpGETRESULT64 : FpI_<(ops RFP64:$dst), SpecialFP, + [(set RFP64:$dst, X86fpget)]>; // FPR = ST(0) +let noResults = 1 in { + def FpSETRESULT32 : FpI_<(ops RFP32:$src), SpecialFP, + [(X86fpset RFP32:$src)]>, Imp<[], [ST0]>; // ST(0) = FPR + + def FpSETRESULT64 : FpI_<(ops RFP64:$src), SpecialFP, + [(X86fpset RFP64:$src)]>, Imp<[], [ST0]>; // ST(0) = FPR +} // FpI - Floating Point Psuedo Instruction template. Predicated on FPStack. class FpI pattern> : FpI_, Requires<[FPStack]>; - -def FpMOV : FpI<(ops RFP:$dst, RFP:$src), SpecialFP, []>; // f1 = fmov f2 +// Register copies. Just copies, the 64->32 version does not truncate. +def FpMOV3232 : FpI<(ops RFP32:$dst, RFP32:$src), SpecialFP, []>; // f1 = fmov f2 +def FpMOV3264 : FpI<(ops RFP64:$dst, RFP32:$src), SpecialFP, []>; // f1 = fmov f2 +def FpMOV6432 : FpI<(ops RFP32:$dst, RFP64:$src), SpecialFP, []>; // f1 = fmov f2 +def FpMOV6464 : FpI<(ops RFP64:$dst, RFP64:$src), SpecialFP, []>; // f1 = fmov f2 // Arithmetic // Add, Sub, Mul, Div. -def FpADD : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), TwoArgFP, - [(set RFP:$dst, (fadd RFP:$src1, RFP:$src2))]>; -def FpSUB : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), TwoArgFP, - [(set RFP:$dst, (fsub RFP:$src1, RFP:$src2))]>; -def FpMUL : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), TwoArgFP, - [(set RFP:$dst, (fmul RFP:$src1, RFP:$src2))]>; -def FpDIV : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), TwoArgFP, - [(set RFP:$dst, (fdiv RFP:$src1, RFP:$src2))]>; +def FpADD32 : FpI<(ops RFP32:$dst, RFP32:$src1, RFP32:$src2), TwoArgFP, + [(set RFP32:$dst, (fadd RFP32:$src1, RFP32:$src2))]>; +def FpSUB32 : FpI<(ops RFP32:$dst, RFP32:$src1, RFP32:$src2), TwoArgFP, + [(set RFP32:$dst, (fsub RFP32:$src1, RFP32:$src2))]>; +def FpMUL32 : FpI<(ops RFP32:$dst, RFP32:$src1, RFP32:$src2), TwoArgFP, + [(set RFP32:$dst, (fmul RFP32:$src1, RFP32:$src2))]>; +def FpDIV32 : FpI<(ops RFP32:$dst, RFP32:$src1, RFP32:$src2), TwoArgFP, + [(set RFP32:$dst, (fdiv RFP32:$src1, RFP32:$src2))]>; +def FpADD64 : FpI<(ops RFP64:$dst, RFP64:$src1, RFP64:$src2), TwoArgFP, + [(set RFP64:$dst, (fadd RFP64:$src1, RFP64:$src2))]>; +def FpSUB64 : FpI<(ops RFP64:$dst, RFP64:$src1, RFP64:$src2), TwoArgFP, + [(set RFP64:$dst, (fsub RFP64:$src1, RFP64:$src2))]>; +def FpMUL64 : FpI<(ops RFP64:$dst, RFP64:$src1, RFP64:$src2), TwoArgFP, + [(set RFP64:$dst, (fmul RFP64:$src1, RFP64:$src2))]>; +def FpDIV64 : FpI<(ops RFP64:$dst, RFP64:$src1, RFP64:$src2), TwoArgFP, + [(set RFP64:$dst, (fdiv RFP64:$src1, RFP64:$src2))]>; class FPST0rInst o, string asm> : FPI, D8; @@ -144,47 +173,41 @@ : FPI, DE; // Binary Ops with a memory source. -def FpADD32m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW, - [(set RFP:$dst, (fadd RFP:$src1, - (extloadf64f32 addr:$src2)))]>; +def FpADD32m : FpI<(ops RFP32:$dst, RFP32:$src1, f32mem:$src2), OneArgFPRW, + [(set RFP32:$dst, (fadd RFP32:$src1, (loadf32 addr:$src2)))]>; // ST(0) = ST(0) + [mem32] -def FpADD64m : FpI<(ops RFP:$dst, RFP:$src1, f64mem:$src2), OneArgFPRW, - [(set RFP:$dst, (fadd RFP:$src1, (loadf64 addr:$src2)))]>; +def FpADD64m : FpI<(ops RFP64:$dst, RFP64:$src1, f64mem:$src2), OneArgFPRW, + [(set RFP64:$dst, (fadd RFP64:$src1, (loadf64 addr:$src2)))]>; // ST(0) = ST(0) + [mem64] -def FpMUL32m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW, - [(set RFP:$dst, (fmul RFP:$src1, - (extloadf64f32 addr:$src2)))]>; +def FpMUL32m : FpI<(ops RFP32:$dst, RFP32:$src1, f32mem:$src2), OneArgFPRW, + [(set RFP32:$dst, (fmul RFP32:$src1, (loadf32 addr:$src2)))]>; // ST(0) = ST(0) * [mem32] -def FpMUL64m : FpI<(ops RFP:$dst, RFP:$src1, f64mem:$src2), OneArgFPRW, - [(set RFP:$dst, (fmul RFP:$src1, (loadf64 addr:$src2)))]>; +def FpMUL64m : FpI<(ops RFP64:$dst, RFP64:$src1, f64mem:$src2), OneArgFPRW, + [(set RFP64:$dst, (fmul RFP64:$src1, (loadf64 addr:$src2)))]>; // ST(0) = ST(0) * [mem64] -def FpSUB32m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW, - [(set RFP:$dst, (fsub RFP:$src1, - (extloadf64f32 addr:$src2)))]>; +def FpSUB32m : FpI<(ops RFP32:$dst, RFP32:$src1, f32mem:$src2), OneArgFPRW, + [(set RFP32:$dst, (fsub RFP32:$src1, (loadf32 addr:$src2)))]>; // ST(0) = ST(0) - [mem32] -def FpSUB64m : FpI<(ops RFP:$dst, RFP:$src1, f64mem:$src2), OneArgFPRW, - [(set RFP:$dst, (fsub RFP:$src1, (loadf64 addr:$src2)))]>; +def FpSUB64m : FpI<(ops RFP64:$dst, RFP64:$src1, f64mem:$src2), OneArgFPRW, + [(set RFP64:$dst, (fsub RFP64:$src1, (loadf64 addr:$src2)))]>; // ST(0) = ST(0) - [mem64] -def FpSUBR32m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW, - [(set RFP:$dst, (fsub (extloadf64f32 addr:$src2), - RFP:$src1))]>; +def FpSUBR32m : FpI<(ops RFP32:$dst, RFP32:$src1, f32mem:$src2), OneArgFPRW, + [(set RFP32:$dst, (fsub (loadf32 addr:$src2), RFP32:$src1))]>; // ST(0) = [mem32] - ST(0) -def FpSUBR64m : FpI<(ops RFP:$dst, RFP:$src1, f64mem:$src2), OneArgFPRW, - [(set RFP:$dst, (fsub (loadf64 addr:$src2), RFP:$src1))]>; +def FpSUBR64m : FpI<(ops RFP64:$dst, RFP64:$src1, f64mem:$src2), OneArgFPRW, + [(set RFP64:$dst, (fsub (loadf64 addr:$src2), RFP64:$src1))]>; // ST(0) = [mem64] - ST(0) -def FpDIV32m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW, - [(set RFP:$dst, (fdiv RFP:$src1, - (extloadf64f32 addr:$src2)))]>; +def FpDIV32m : FpI<(ops RFP32:$dst, RFP32:$src1, f32mem:$src2), OneArgFPRW, + [(set RFP32:$dst, (fdiv RFP32:$src1, (loadf32 addr:$src2)))]>; // ST(0) = ST(0) / [mem32] -def FpDIV64m : FpI<(ops RFP:$dst, RFP:$src1, f64mem:$src2), OneArgFPRW, - [(set RFP:$dst, (fdiv RFP:$src1, (loadf64 addr:$src2)))]>; +def FpDIV64m : FpI<(ops RFP64:$dst, RFP64:$src1, f64mem:$src2), OneArgFPRW, + [(set RFP64:$dst, (fdiv RFP64:$src1, (loadf64 addr:$src2)))]>; // ST(0) = ST(0) / [mem64] -def FpDIVR32m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW, - [(set RFP:$dst, (fdiv (extloadf64f32 addr:$src2), - RFP:$src1))]>; +def FpDIVR32m : FpI<(ops RFP32:$dst, RFP32:$src1, f32mem:$src2), OneArgFPRW, + [(set RFP32:$dst, (fdiv (loadf32 addr:$src2), RFP32:$src1))]>; // ST(0) = [mem32] / ST(0) -def FpDIVR64m : FpI<(ops RFP:$dst, RFP:$src1, f64mem:$src2), OneArgFPRW, - [(set RFP:$dst, (fdiv (loadf64 addr:$src2), RFP:$src1))]>; +def FpDIVR64m : FpI<(ops RFP64:$dst, RFP64:$src1, f64mem:$src2), OneArgFPRW, + [(set RFP64:$dst, (fdiv (loadf64 addr:$src2), RFP64:$src1))]>; // ST(0) = [mem64] / ST(0) @@ -201,53 +224,102 @@ def FDIVR32m : FPI<0xD8, MRM7m, (ops f32mem:$src), "fdivr{s} $src">; def FDIVR64m : FPI<0xDC, MRM7m, (ops f64mem:$src), "fdivr{l} $src">; -def FpIADD16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW, - [(set RFP:$dst, (fadd RFP:$src1, +def FpIADD16m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i16mem:$src2), OneArgFPRW, + [(set RFP32:$dst, (fadd RFP32:$src1, + (X86fild addr:$src2, i16)))]>; + // ST(0) = ST(0) + [mem16int] +def FpIADD32m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i32mem:$src2), OneArgFPRW, + [(set RFP32:$dst, (fadd RFP32:$src1, + (X86fild addr:$src2, i32)))]>; + // ST(0) = ST(0) + [mem32int] +def FpIMUL16m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i16mem:$src2), OneArgFPRW, + [(set RFP32:$dst, (fmul RFP32:$src1, + (X86fild addr:$src2, i16)))]>; + // ST(0) = ST(0) * [mem16int] +def FpIMUL32m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i32mem:$src2), OneArgFPRW, + [(set RFP32:$dst, (fmul RFP32:$src1, + (X86fild addr:$src2, i32)))]>; + // ST(0) = ST(0) * [mem32int] +def FpISUB16m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i16mem:$src2), OneArgFPRW, + [(set RFP32:$dst, (fsub RFP32:$src1, + (X86fild addr:$src2, i16)))]>; + // ST(0) = ST(0) - [mem16int] +def FpISUB32m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i32mem:$src2), OneArgFPRW, + [(set RFP32:$dst, (fsub RFP32:$src1, + (X86fild addr:$src2, i32)))]>; + // ST(0) = ST(0) - [mem32int] +def FpISUBR16m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i16mem:$src2), OneArgFPRW, + [(set RFP32:$dst, (fsub (X86fild addr:$src2, i16), + RFP32:$src1))]>; + // ST(0) = [mem16int] - ST(0) +def FpISUBR32m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i32mem:$src2), OneArgFPRW, + [(set RFP32:$dst, (fsub (X86fild addr:$src2, i32), + RFP32:$src1))]>; + // ST(0) = [mem32int] - ST(0) +def FpIDIV16m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i16mem:$src2), OneArgFPRW, + [(set RFP32:$dst, (fdiv RFP32:$src1, + (X86fild addr:$src2, i16)))]>; + // ST(0) = ST(0) / [mem16int] +def FpIDIV32m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i32mem:$src2), OneArgFPRW, + [(set RFP32:$dst, (fdiv RFP32:$src1, + (X86fild addr:$src2, i32)))]>; + // ST(0) = ST(0) / [mem32int] +def FpIDIVR16m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i16mem:$src2), OneArgFPRW, + [(set RFP32:$dst, (fdiv (X86fild addr:$src2, i16), + RFP32:$src1))]>; + // ST(0) = [mem16int] / ST(0) +def FpIDIVR32m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i32mem:$src2), OneArgFPRW, + [(set RFP32:$dst, (fdiv (X86fild addr:$src2, i32), + RFP32:$src1))]>; + // ST(0) = [mem32int] / ST(0) + +def FpIADD16m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i16mem:$src2), OneArgFPRW, + [(set RFP64:$dst, (fadd RFP64:$src1, (X86fild addr:$src2, i16)))]>; // ST(0) = ST(0) + [mem16int] -def FpIADD32m : FpI<(ops RFP:$dst, RFP:$src1, i32mem:$src2), OneArgFPRW, - [(set RFP:$dst, (fadd RFP:$src1, +def FpIADD32m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i32mem:$src2), OneArgFPRW, + [(set RFP64:$dst, (fadd RFP64:$src1, (X86fild addr:$src2, i32)))]>; // ST(0) = ST(0) + [mem32int] -def FpIMUL16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW, - [(set RFP:$dst, (fmul RFP:$src1, +def FpIMUL16m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i16mem:$src2), OneArgFPRW, + [(set RFP64:$dst, (fmul RFP64:$src1, (X86fild addr:$src2, i16)))]>; // ST(0) = ST(0) * [mem16int] -def FpIMUL32m : FpI<(ops RFP:$dst, RFP:$src1, i32mem:$src2), OneArgFPRW, - [(set RFP:$dst, (fmul RFP:$src1, +def FpIMUL32m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i32mem:$src2), OneArgFPRW, + [(set RFP64:$dst, (fmul RFP64:$src1, (X86fild addr:$src2, i32)))]>; // ST(0) = ST(0) * [mem32int] -def FpISUB16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW, - [(set RFP:$dst, (fsub RFP:$src1, +def FpISUB16m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i16mem:$src2), OneArgFPRW, + [(set RFP64:$dst, (fsub RFP64:$src1, (X86fild addr:$src2, i16)))]>; // ST(0) = ST(0) - [mem16int] -def FpISUB32m : FpI<(ops RFP:$dst, RFP:$src1, i32mem:$src2), OneArgFPRW, - [(set RFP:$dst, (fsub RFP:$src1, +def FpISUB32m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i32mem:$src2), OneArgFPRW, + [(set RFP64:$dst, (fsub RFP64:$src1, (X86fild addr:$src2, i32)))]>; // ST(0) = ST(0) - [mem32int] -def FpISUBR16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW, - [(set RFP:$dst, (fsub (X86fild addr:$src2, i16), - RFP:$src1))]>; +def FpISUBR16m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i16mem:$src2), OneArgFPRW, + [(set RFP64:$dst, (fsub (X86fild addr:$src2, i16), + RFP64:$src1))]>; // ST(0) = [mem16int] - ST(0) -def FpISUBR32m : FpI<(ops RFP:$dst, RFP:$src1, i32mem:$src2), OneArgFPRW, - [(set RFP:$dst, (fsub (X86fild addr:$src2, i32), - RFP:$src1))]>; +def FpISUBR32m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i32mem:$src2), OneArgFPRW, + [(set RFP64:$dst, (fsub (X86fild addr:$src2, i32), + RFP64:$src1))]>; // ST(0) = [mem32int] - ST(0) -def FpIDIV16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW, - [(set RFP:$dst, (fdiv RFP:$src1, +def FpIDIV16m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i16mem:$src2), OneArgFPRW, + [(set RFP64:$dst, (fdiv RFP64:$src1, (X86fild addr:$src2, i16)))]>; // ST(0) = ST(0) / [mem16int] -def FpIDIV32m : FpI<(ops RFP:$dst, RFP:$src1, i32mem:$src2), OneArgFPRW, - [(set RFP:$dst, (fdiv RFP:$src1, +def FpIDIV32m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i32mem:$src2), OneArgFPRW, + [(set RFP64:$dst, (fdiv RFP64:$src1, (X86fild addr:$src2, i32)))]>; // ST(0) = ST(0) / [mem32int] -def FpIDIVR16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW, - [(set RFP:$dst, (fdiv (X86fild addr:$src2, i16), - RFP:$src1))]>; +def FpIDIVR16m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i16mem:$src2), OneArgFPRW, + [(set RFP64:$dst, (fdiv (X86fild addr:$src2, i16), + RFP64:$src1))]>; // ST(0) = [mem16int] / ST(0) -def FpIDIVR32m : FpI<(ops RFP:$dst, RFP:$src1, i32mem:$src2), OneArgFPRW, - [(set RFP:$dst, (fdiv (X86fild addr:$src2, i32), - RFP:$src1))]>; +def FpIDIVR32m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i32mem:$src2), OneArgFPRW, + [(set RFP64:$dst, (fdiv (X86fild addr:$src2, i32), + RFP64:$src1))]>; // ST(0) = [mem32int] / ST(0) def FIADD16m : FPI<0xDE, MRM0m, (ops i16mem:$src), "fiadd{s} $src">; @@ -285,19 +357,31 @@ def FDIVRrST0 : FPrST0Inst <0xF0, "fdiv{|r} {%st(0), $op|$op, %ST(0)}">; def FDIVRPrST0 : FPrST0PInst<0xF0, "fdiv{|r}p $op">; - // Unary operations. -def FpCHS : FpI<(ops RFP:$dst, RFP:$src), OneArgFPRW, - [(set RFP:$dst, (fneg RFP:$src))]>; -def FpABS : FpI<(ops RFP:$dst, RFP:$src), OneArgFPRW, - [(set RFP:$dst, (fabs RFP:$src))]>; -def FpSQRT : FpI<(ops RFP:$dst, RFP:$src), OneArgFPRW, - [(set RFP:$dst, (fsqrt RFP:$src))]>; -def FpSIN : FpI<(ops RFP:$dst, RFP:$src), OneArgFPRW, - [(set RFP:$dst, (fsin RFP:$src))]>; -def FpCOS : FpI<(ops RFP:$dst, RFP:$src), OneArgFPRW, - [(set RFP:$dst, (fcos RFP:$src))]>; -def FpTST : FpI<(ops RFP:$src), OneArgFP, +def FpCHS32 : FpI<(ops RFP32:$dst, RFP32:$src), OneArgFPRW, + [(set RFP32:$dst, (fneg RFP32:$src))]>; +def FpABS32 : FpI<(ops RFP32:$dst, RFP32:$src), OneArgFPRW, + [(set RFP32:$dst, (fabs RFP32:$src))]>; +def FpSQRT32 : FpI<(ops RFP32:$dst, RFP32:$src), OneArgFPRW, + [(set RFP32:$dst, (fsqrt RFP32:$src))]>; +def FpSIN32 : FpI<(ops RFP32:$dst, RFP32:$src), OneArgFPRW, + [(set RFP32:$dst, (fsin RFP32:$src))]>; +def FpCOS32 : FpI<(ops RFP32:$dst, RFP32:$src), OneArgFPRW, + [(set RFP32:$dst, (fcos RFP32:$src))]>; +def FpTST32 : FpI<(ops RFP32:$src), OneArgFP, + []>; + +def FpCHS64 : FpI<(ops RFP64:$dst, RFP64:$src), OneArgFPRW, + [(set RFP64:$dst, (fneg RFP64:$src))]>; +def FpABS64 : FpI<(ops RFP64:$dst, RFP64:$src), OneArgFPRW, + [(set RFP64:$dst, (fabs RFP64:$src))]>; +def FpSQRT64 : FpI<(ops RFP64:$dst, RFP64:$src), OneArgFPRW, + [(set RFP64:$dst, (fsqrt RFP64:$src))]>; +def FpSIN64 : FpI<(ops RFP64:$dst, RFP64:$src), OneArgFPRW, + [(set RFP64:$dst, (fsin RFP64:$src))]>; +def FpCOS64 : FpI<(ops RFP64:$dst, RFP64:$src), OneArgFPRW, + [(set RFP64:$dst, (fcos RFP64:$src))]>; +def FpTST64 : FpI<(ops RFP64:$src), OneArgFP, []>; def FCHS : FPI<0xE0, RawFrm, (ops), "fchs">, D9; @@ -310,29 +394,54 @@ // Floating point cmovs. let isTwoAddress = 1 in { - def FpCMOVB : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP, - [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2, + def FpCMOVB32 : FpI<(ops RFP32:$dst, RFP32:$src1, RFP32:$src2), CondMovFP, + [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, X86_COND_B))]>; - def FpCMOVBE : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP, - [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2, + def FpCMOVBE32 : FpI<(ops RFP32:$dst, RFP32:$src1, RFP32:$src2), CondMovFP, + [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, X86_COND_BE))]>; - def FpCMOVE : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP, - [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2, + def FpCMOVE32 : FpI<(ops RFP32:$dst, RFP32:$src1, RFP32:$src2), CondMovFP, + [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, X86_COND_E))]>; - def FpCMOVP : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP, - [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2, + def FpCMOVP32 : FpI<(ops RFP32:$dst, RFP32:$src1, RFP32:$src2), CondMovFP, + [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, X86_COND_P))]>; - def FpCMOVNB : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP, - [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2, + def FpCMOVNB32 : FpI<(ops RFP32:$dst, RFP32:$src1, RFP32:$src2), CondMovFP, + [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, X86_COND_AE))]>; - def FpCMOVNBE: FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP, - [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2, + def FpCMOVNBE32: FpI<(ops RFP32:$dst, RFP32:$src1, RFP32:$src2), CondMovFP, + [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, X86_COND_A))]>; - def FpCMOVNE : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP, - [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2, + def FpCMOVNE32 : FpI<(ops RFP32:$dst, RFP32:$src1, RFP32:$src2), CondMovFP, + [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, X86_COND_NE))]>; - def FpCMOVNP : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP, - [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2, + def FpCMOVNP32 : FpI<(ops RFP32:$dst, RFP32:$src1, RFP32:$src2), CondMovFP, + [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, + X86_COND_NP))]>; + + def FpCMOVB64 : FpI<(ops RFP64:$dst, RFP64:$src1, RFP64:$src2), CondMovFP, + [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, + X86_COND_B))]>; + def FpCMOVBE64 : FpI<(ops RFP64:$dst, RFP64:$src1, RFP64:$src2), CondMovFP, + [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, + X86_COND_BE))]>; + def FpCMOVE64 : FpI<(ops RFP64:$dst, RFP64:$src1, RFP64:$src2), CondMovFP, + [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, + X86_COND_E))]>; + def FpCMOVP64 : FpI<(ops RFP64:$dst, RFP64:$src1, RFP64:$src2), CondMovFP, + [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, + X86_COND_P))]>; + def FpCMOVNB64 : FpI<(ops RFP64:$dst, RFP64:$src1, RFP64:$src2), CondMovFP, + [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, + X86_COND_AE))]>; + def FpCMOVNBE64: FpI<(ops RFP64:$dst, RFP64:$src1, RFP64:$src2), CondMovFP, + [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, + X86_COND_A))]>; + def FpCMOVNE64 : FpI<(ops RFP64:$dst, RFP64:$src1, RFP64:$src2), CondMovFP, + [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, + X86_COND_NE))]>; + def FpCMOVNP64 : FpI<(ops RFP64:$dst, RFP64:$src1, RFP64:$src2), CondMovFP, + [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, X86_COND_NP))]>; } @@ -354,27 +463,39 @@ "fcmovnu {$op, %st(0)|%ST(0), $op}">, DB; // Floating point loads & stores. -def FpLD32m : FpI<(ops RFP:$dst, f32mem:$src), ZeroArgFP, - [(set RFP:$dst, (extloadf64f32 addr:$src))]>; -def FpLD64m : FpI<(ops RFP:$dst, f64mem:$src), ZeroArgFP, - [(set RFP:$dst, (loadf64 addr:$src))]>; -def FpILD16m : FpI<(ops RFP:$dst, i16mem:$src), ZeroArgFP, - [(set RFP:$dst, (X86fild addr:$src, i16))]>; -def FpILD32m : FpI<(ops RFP:$dst, i32mem:$src), ZeroArgFP, - [(set RFP:$dst, (X86fild addr:$src, i32))]>; -def FpILD64m : FpI<(ops RFP:$dst, i64mem:$src), ZeroArgFP, - [(set RFP:$dst, (X86fild addr:$src, i64))]>; - -def FpST32m : FpI<(ops f32mem:$op, RFP:$src), OneArgFP, - [(truncstoref32 RFP:$src, addr:$op)]>; -def FpST64m : FpI<(ops f64mem:$op, RFP:$src), OneArgFP, - [(store RFP:$src, addr:$op)]>; - -def FpSTP32m : FpI<(ops f32mem:$op, RFP:$src), OneArgFP, []>; -def FpSTP64m : FpI<(ops f64mem:$op, RFP:$src), OneArgFP, []>; -def FpIST16m : FpI<(ops i16mem:$op, RFP:$src), OneArgFP, []>; -def FpIST32m : FpI<(ops i32mem:$op, RFP:$src), OneArgFP, []>; -def FpIST64m : FpI<(ops i64mem:$op, RFP:$src), OneArgFP, []>; +def FpLD32m : FpI<(ops RFP32:$dst, f32mem:$src), ZeroArgFP, + [(set RFP32:$dst, (loadf32 addr:$src))]>; +def FpLD64m : FpI<(ops RFP64:$dst, f64mem:$src), ZeroArgFP, + [(set RFP64:$dst, (loadf64 addr:$src))]>; +def FpILD16m32 : FpI<(ops RFP32:$dst, i16mem:$src), ZeroArgFP, + [(set RFP32:$dst, (X86fild addr:$src, i16))]>; +def FpILD32m32 : FpI<(ops RFP32:$dst, i32mem:$src), ZeroArgFP, + [(set RFP32:$dst, (X86fild addr:$src, i32))]>; +def FpILD64m32 : FpI<(ops RFP32:$dst, i64mem:$src), ZeroArgFP, + [(set RFP32:$dst, (X86fild addr:$src, i64))]>; +def FpILD16m64 : FpI<(ops RFP64:$dst, i16mem:$src), ZeroArgFP, + [(set RFP64:$dst, (X86fild addr:$src, i16))]>; +def FpILD32m64 : FpI<(ops RFP64:$dst, i32mem:$src), ZeroArgFP, + [(set RFP64:$dst, (X86fild addr:$src, i32))]>; +def FpILD64m64 : FpI<(ops RFP64:$dst, i64mem:$src), ZeroArgFP, + [(set RFP64:$dst, (X86fild addr:$src, i64))]>; + +def FpST32m : FpI<(ops f32mem:$op, RFP32:$src), OneArgFP, + [(store RFP32:$src, addr:$op)]>; +def FpST64m32 : FpI<(ops f32mem:$op, RFP64:$src), OneArgFP, + [(truncstoref32 RFP64:$src, addr:$op)]>; +def FpST64m : FpI<(ops f64mem:$op, RFP64:$src), OneArgFP, + [(store RFP64:$src, addr:$op)]>; + +def FpSTP32m : FpI<(ops f32mem:$op, RFP32:$src), OneArgFP, []>; +def FpSTP64m32 : FpI<(ops f32mem:$op, RFP64:$src), OneArgFP, []>; +def FpSTP64m : FpI<(ops f64mem:$op, RFP64:$src), OneArgFP, []>; +def FpIST16m32 : FpI<(ops i16mem:$op, RFP32:$src), OneArgFP, []>; +def FpIST32m32 : FpI<(ops i32mem:$op, RFP32:$src), OneArgFP, []>; +def FpIST64m32 : FpI<(ops i64mem:$op, RFP32:$src), OneArgFP, []>; +def FpIST16m64 : FpI<(ops i16mem:$op, RFP64:$src), OneArgFP, []>; +def FpIST32m64 : FpI<(ops i32mem:$op, RFP64:$src), OneArgFP, []>; +def FpIST64m64 : FpI<(ops i64mem:$op, RFP64:$src), OneArgFP, []>; def FLD32m : FPI<0xD9, MRM0m, (ops f32mem:$src), "fld{s} $src">; def FLD64m : FPI<0xDD, MRM0m, (ops f64mem:$src), "fld{l} $src">; @@ -392,14 +513,23 @@ def FISTP64m : FPI<0xDF, MRM7m, (ops i64mem:$dst), "fistp{ll} $dst">; // FISTTP requires SSE3 even though it's a FPStack op. -def FpISTT16m : FpI_<(ops i16mem:$op, RFP:$src), OneArgFP, - [(X86fp_to_i16mem RFP:$src, addr:$op)]>, +def FpISTT16m32 : FpI_<(ops i16mem:$op, RFP32:$src), OneArgFP, + [(X86fp_to_i16mem RFP32:$src, addr:$op)]>, + Requires<[HasSSE3]>; +def FpISTT32m32 : FpI_<(ops i32mem:$op, RFP32:$src), OneArgFP, + [(X86fp_to_i32mem RFP32:$src, addr:$op)]>, Requires<[HasSSE3]>; -def FpISTT32m : FpI_<(ops i32mem:$op, RFP:$src), OneArgFP, - [(X86fp_to_i32mem RFP:$src, addr:$op)]>, +def FpISTT64m32 : FpI_<(ops i64mem:$op, RFP32:$src), OneArgFP, + [(X86fp_to_i64mem RFP32:$src, addr:$op)]>, Requires<[HasSSE3]>; -def FpISTT64m : FpI_<(ops i64mem:$op, RFP:$src), OneArgFP, - [(X86fp_to_i64mem RFP:$src, addr:$op)]>, +def FpISTT16m64 : FpI_<(ops i16mem:$op, RFP64:$src), OneArgFP, + [(X86fp_to_i16mem RFP64:$src, addr:$op)]>, + Requires<[HasSSE3]>; +def FpISTT32m64 : FpI_<(ops i32mem:$op, RFP64:$src), OneArgFP, + [(X86fp_to_i32mem RFP64:$src, addr:$op)]>, + Requires<[HasSSE3]>; +def FpISTT64m64 : FpI_<(ops i64mem:$op, RFP64:$src), OneArgFP, + [(X86fp_to_i64mem RFP64:$src, addr:$op)]>, Requires<[HasSSE3]>; def FISTTP16m : FPI<0xDF, MRM1m, (ops i16mem:$dst), "fisttp{s} $dst">; @@ -414,10 +544,14 @@ // Floating point constant loads. let isReMaterializable = 1 in { -def FpLD0 : FpI<(ops RFP:$dst), ZeroArgFP, - [(set RFP:$dst, fp64imm0)]>; -def FpLD1 : FpI<(ops RFP:$dst), ZeroArgFP, - [(set RFP:$dst, fp64imm1)]>; +def FpLD032 : FpI<(ops RFP32:$dst), ZeroArgFP, + [(set RFP32:$dst, fpimm0)]>; +def FpLD132 : FpI<(ops RFP32:$dst), ZeroArgFP, + [(set RFP32:$dst, fpimm1)]>; +def FpLD064 : FpI<(ops RFP64:$dst), ZeroArgFP, + [(set RFP64:$dst, fpimm0)]>; +def FpLD164 : FpI<(ops RFP64:$dst), ZeroArgFP, + [(set RFP64:$dst, fpimm1)]>; } def FLD0 : FPI<0xEE, RawFrm, (ops), "fldz">, D9; @@ -425,10 +559,14 @@ // Floating point compares. -def FpUCOMr : FpI<(ops RFP:$lhs, RFP:$rhs), CompareFP, +def FpUCOMr32 : FpI<(ops RFP32:$lhs, RFP32:$rhs), CompareFP, + []>; // FPSW = cmp ST(0) with ST(i) +def FpUCOMIr32 : FpI<(ops RFP32:$lhs, RFP32:$rhs), CompareFP, + [(X86cmp RFP32:$lhs, RFP32:$rhs)]>; // CC = cmp ST(0) with ST(i) +def FpUCOMr64 : FpI<(ops RFP64:$lhs, RFP64:$rhs), CompareFP, []>; // FPSW = cmp ST(0) with ST(i) -def FpUCOMIr : FpI<(ops RFP:$lhs, RFP:$rhs), CompareFP, - [(X86cmp RFP:$lhs, RFP:$rhs)]>; // CC = cmp ST(0) with ST(i) +def FpUCOMIr64 : FpI<(ops RFP64:$lhs, RFP64:$rhs), CompareFP, + [(X86cmp RFP64:$lhs, RFP64:$rhs)]>; // CC = cmp ST(0) with ST(i) def FUCOMr : FPI<0xE0, AddRegFrm, // FPSW = cmp ST(0) with ST(i) (ops RST:$reg), @@ -447,7 +585,6 @@ (ops RST:$reg), "fucomip {$reg, %st(0)|%ST(0), $reg}">, DF, Imp<[ST0],[]>; - // Floating point flag ops. def FNSTSW8r : I<0xE0, RawFrm, // AX = fp flags (ops), "fnstsw", []>, DF, Imp<[],[AX]>; @@ -466,12 +603,18 @@ def : Pat<(X86fld addr:$src, f64), (FpLD64m addr:$src)>; // Required for CALL which return f32 / f64 values. -def : Pat<(X86fst RFP:$src, addr:$op, f32), (FpST32m addr:$op, RFP:$src)>; -def : Pat<(X86fst RFP:$src, addr:$op, f64), (FpST64m addr:$op, RFP:$src)>; +def : Pat<(X86fst RFP32:$src, addr:$op, f32), (FpST32m addr:$op, RFP32:$src)>; +def : Pat<(X86fst RFP64:$src, addr:$op, f32), (FpST64m32 addr:$op, RFP64:$src)>; +def : Pat<(X86fst RFP64:$src, addr:$op, f64), (FpST64m addr:$op, RFP64:$src)>; // Floating point constant -0.0 and -1.0 -def : Pat<(f64 fp64immneg0), (FpCHS (FpLD0))>, Requires<[FPStack]>; -def : Pat<(f64 fp64immneg1), (FpCHS (FpLD1))>, Requires<[FPStack]>; +def : Pat<(f32 fpimmneg0), (FpCHS32 (FpLD032))>, Requires<[FPStack]>; +def : Pat<(f32 fpimmneg1), (FpCHS32 (FpLD132))>, Requires<[FPStack]>; +def : Pat<(f64 fpimmneg0), (FpCHS64 (FpLD064))>, Requires<[FPStack]>; +def : Pat<(f64 fpimmneg1), (FpCHS64 (FpLD164))>, Requires<[FPStack]>; // Used to conv. i64 to f64 since there isn't a SSE version. -def : Pat<(X86fildflag addr:$src, i64), (FpILD64m addr:$src)>; +def : Pat<(X86fildflag addr:$src, i64), (FpILD64m64 addr:$src)>; + +def : Pat<(extloadf32 addr:$src), (FpMOV3264 (FpLD32m addr:$src))>, Requires<[FPStack]>; +def : Pat<(fextend RFP32:$src), (FpMOV3264 RFP32:$src)>, Requires<[FPStack]>; Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=37847&r1=37846&r2=37847&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Mon Jul 2 19:53:03 2007 @@ -33,7 +33,8 @@ if (oc == X86::MOV8rr || oc == X86::MOV16rr || oc == X86::MOV32rr || oc == X86::MOV64rr || oc == X86::MOV16to16_ || oc == X86::MOV32to32_ || - oc == X86::FpMOV || oc == X86::MOVSSrr || oc == X86::MOVSDrr || + oc == X86::FpMOV3232 || oc == X86::MOVSSrr || oc == X86::MOVSDrr || + oc == X86::FpMOV3264 || oc == X86::FpMOV6432 || oc == X86::FpMOV6464 || oc == X86::FsMOVAPSrr || oc == X86::FsMOVAPDrr || oc == X86::MOVAPSrr || oc == X86::MOVAPDrr || oc == X86::MOVSS2PSrr || oc == X86::MOVSD2PDrr || Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=37847&r1=37846&r2=37847&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Mon Jul 2 19:53:03 2007 @@ -964,7 +964,7 @@ // Alias instructions that map fld0 to pxor for sse. def FsFLD0SD : I<0xEF, MRMInitReg, (ops FR64:$dst), - "pxor $dst, $dst", [(set FR64:$dst, fp64imm0)]>, + "pxor $dst, $dst", [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>, TB, OpSize; // Alias instruction to do FR64 reg-to-reg copy using movapd. Upper bits are Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=37847&r1=37846&r2=37847&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Mon Jul 2 19:53:03 2007 @@ -82,8 +82,10 @@ Opc = X86::MOV32_mr; } else if (RC == &X86::GR16_RegClass) { Opc = X86::MOV16_mr; - } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) { + } else if (RC == &X86::RFP64RegClass || RC == &X86::RSTRegClass) { Opc = X86::FpST64m; + } else if (RC == &X86::RFP32RegClass) { + Opc = X86::FpST32m; } else if (RC == &X86::FR32RegClass) { Opc = X86::MOVSSmr; } else if (RC == &X86::FR64RegClass) { @@ -117,8 +119,10 @@ Opc = X86::MOV32_rm; } else if (RC == &X86::GR16_RegClass) { Opc = X86::MOV16_rm; - } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) { + } else if (RC == &X86::RFP64RegClass || RC == &X86::RSTRegClass) { Opc = X86::FpLD64m; + } else if (RC == &X86::RFP32RegClass) { + Opc = X86::FpLD32m; } else if (RC == &X86::FR32RegClass) { Opc = X86::MOVSSrm; } else if (RC == &X86::FR64RegClass) { @@ -151,8 +155,10 @@ Opc = X86::MOV32_rr; } else if (RC == &X86::GR16_RegClass) { Opc = X86::MOV16_rr; - } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) { - Opc = X86::FpMOV; + } else if (RC == &X86::RFP32RegClass) { + Opc = X86::FpMOV3232; + } else if (RC == &X86::RFP64RegClass || RC == &X86::RSTRegClass) { + Opc = X86::FpMOV6464; } else if (RC == &X86::FR32RegClass) { Opc = X86::FsMOVAPSrr; } else if (RC == &X86::FR64RegClass) { Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.td?rev=37847&r1=37846&r2=37847&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86RegisterInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.td Mon Jul 2 19:53:03 2007 @@ -425,7 +425,8 @@ // faster on common hardware. In reality, this should be controlled by a // command line option or something. -def RFP : RegisterClass<"X86", [f64], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>; +def RFP32 : RegisterClass<"X86", [f32], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>; +def RFP64 : RegisterClass<"X86", [f64], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>; // Floating point stack registers (these are not allocatable by the // register allocator - the floating point stackifier is responsible From dalej at apple.com Mon Jul 2 19:58:37 2007 From: dalej at apple.com (Dale Johannesen) Date: Tue, 03 Jul 2007 00:58:37 -0000 Subject: [llvm-commits] [llvm] r37848 - in /llvm/trunk/test/CodeGen/X86: pr1489.ll pr1505.ll pr1505b.ll Message-ID: <200707030058.l630wbpe013743@zion.cs.uiuc.edu> Author: johannes Date: Mon Jul 2 19:58:37 2007 New Revision: 37848 URL: http://llvm.org/viewvc/llvm-project?rev=37848&view=rev Log: New testcases for rev 37847 (PR's 1489 and 1505). Added: llvm/trunk/test/CodeGen/X86/pr1489.ll llvm/trunk/test/CodeGen/X86/pr1505.ll llvm/trunk/test/CodeGen/X86/pr1505b.ll Added: llvm/trunk/test/CodeGen/X86/pr1489.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr1489.ll?rev=37848&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/pr1489.ll (added) +++ llvm/trunk/test/CodeGen/X86/pr1489.ll Mon Jul 2 19:58:37 2007 @@ -0,0 +1,55 @@ +; RUN: llvm-as < %s | llc -disable-fp-elim -fast -mcpu=i486 | grep 1082126238 | wc -l | grep 3 +; RUN: llvm-as < %s | llc -disable-fp-elim -fast -mcpu=i486 | grep 3058016715 | wc -l | grep 1 +;; magic constants are 3.999f and half of 3.999 +; ModuleID = '1489.c' +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64" +target triple = "i686-apple-darwin8" + at .str = internal constant [13 x i8] c"%d %d %d %d\0A\00" ; <[13 x i8]*> [#uses=1] + +define i32 @quux() { +entry: + %tmp1 = tail call i32 @lrintf( float 0x400FFDF3C0000000 ) ; [#uses=1] + %tmp2 = icmp slt i32 %tmp1, 1 ; [#uses=1] + %tmp23 = zext i1 %tmp2 to i32 ; [#uses=1] + ret i32 %tmp23 +} + +declare i32 @lrintf(float) + +define i32 @foo() { +entry: + %tmp1 = tail call i32 @lrint( double 3.999000e+00 ) ; [#uses=1] + %tmp2 = icmp slt i32 %tmp1, 1 ; [#uses=1] + %tmp23 = zext i1 %tmp2 to i32 ; [#uses=1] + ret i32 %tmp23 +} + +declare i32 @lrint(double) + +define i32 @bar() { +entry: + %tmp1 = tail call i32 @lrintf( float 0x400FFDF3C0000000 ) ; [#uses=1] + %tmp2 = icmp slt i32 %tmp1, 1 ; [#uses=1] + %tmp23 = zext i1 %tmp2 to i32 ; [#uses=1] + ret i32 %tmp23 +} + +define i32 @baz() { +entry: + %tmp1 = tail call i32 @lrintf( float 0x400FFDF3C0000000 ) ; [#uses=1] + %tmp2 = icmp slt i32 %tmp1, 1 ; [#uses=1] + %tmp23 = zext i1 %tmp2 to i32 ; [#uses=1] + ret i32 %tmp23 +} + +define i32 @main() { +entry: + %tmp = tail call i32 @baz( ) ; [#uses=1] + %tmp1 = tail call i32 @bar( ) ; [#uses=1] + %tmp2 = tail call i32 @foo( ) ; [#uses=1] + %tmp3 = tail call i32 @quux( ) ; [#uses=1] + %tmp5 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([13 x i8]* @.str, i32 0, i32 0), i32 %tmp3, i32 %tmp2, i32 %tmp1, i32 %tmp ) ; [#uses=0] + ret i32 undef +} + +declare i32 @printf(i8*, ...) Added: llvm/trunk/test/CodeGen/X86/pr1505.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr1505.ll?rev=37848&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/pr1505.ll (added) +++ llvm/trunk/test/CodeGen/X86/pr1505.ll Mon Jul 2 19:58:37 2007 @@ -0,0 +1,12 @@ +; RUN: llvm-as < %s | llc -mcpu=i486 | not grep fldl + +; ModuleID = '' +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64" +target triple = "i686-apple-darwin8" + at G = weak global float 0.000000e+00 ; [#uses=1] + +define void @t1(float %F) { +entry: + store float %F, float* @G + ret void +} Added: llvm/trunk/test/CodeGen/X86/pr1505b.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr1505b.ll?rev=37848&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/pr1505b.ll (added) +++ llvm/trunk/test/CodeGen/X86/pr1505b.ll Mon Jul 2 19:58:37 2007 @@ -0,0 +1,73 @@ +; RUN: llvm-as < %s | llc -mcpu=i486 | grep fstpl | wc -l | grep 4 +; RUN: llvm-as < %s | llc -mcpu=i486 | grep fstps | wc -l | grep 3 + +; ModuleID = '' +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64" +target triple = "i686-apple-darwin8" + %"struct.std::basic_ios >" = type { %"struct.std::ios_base", %"struct.std::basic_ostream >"*, i8, i8, %"struct.std::basic_streambuf >"*, %"struct.std::ctype"*, %"struct.std::num_get > >"*, %"struct.std::num_get > >"* } + %"struct.std::basic_ostream >" = type { i32 (...)**, %"struct.std::basic_ios >" } + %"struct.std::basic_streambuf >" = type { i32 (...)**, i8*, i8*, i8*, i8*, i8*, i8*, %"struct.std::locale" } + %"struct.std::ctype" = type { %"struct.std::locale::facet", i32*, i8, i32*, i32*, i32*, i8, [256 x i8], [256 x i8], i8 } + %"struct.std::ctype_base" = type <{ i8 }> + %"struct.std::ios_base" = type { i32 (...)**, i32, i32, i32, i32, i32, %"struct.std::ios_base::_Callback_list"*, %"struct.std::ios_base::_Words", [8 x %"struct.std::ios_base::_Words"], i32, %"struct.std::ios_base::_Words"*, %"struct.std::locale" } + %"struct.std::ios_base::_Callback_list" = type { %"struct.std::ios_base::_Callback_list"*, void (i32, %"struct.std::ios_base"*, i32)*, i32, i32 } + %"struct.std::ios_base::_Words" = type { i8*, i32 } + %"struct.std::locale" = type { %"struct.std::locale::_Impl"* } + %"struct.std::locale::_Impl" = type { i32, %"struct.std::locale::facet"**, i32, %"struct.std::locale::facet"**, i8** } + %"struct.std::locale::facet" = type { i32 (...)**, i32 } + %"struct.std::num_get > >" = type { %"struct.std::locale::facet" } + at a = global float 0x3FD3333340000000 ; [#uses=1] + at b = global double 6.000000e-01, align 8 ; [#uses=1] + at _ZSt8__ioinit = internal global %"struct.std::ctype_base" zeroinitializer ; <%"struct.std::ctype_base"*> [#uses=2] + at __dso_handle = external global i8* ; [#uses=1] + at _ZSt4cout = external global %"struct.std::basic_ostream >" ; <%"struct.std::basic_ostream >"*> [#uses=2] + at .str = internal constant [12 x i8] c"tan float: \00" ; <[12 x i8]*> [#uses=1] + at .str1 = internal constant [13 x i8] c"tan double: \00" ; <[13 x i8]*> [#uses=1] + at llvm.global_ctors = appending global [1 x { i32, void ()* }] [ { i32, void ()* } { i32 65535, void ()* @_GLOBAL__I_a } ] ; <[1 x { i32, void ()* }]*> [#uses=0] + +define internal void @_GLOBAL__I_a() section "__TEXT,__StaticInit,regular,pure_instructions" { +entry: + tail call void @_ZNSt8ios_base4InitC1Ev( %"struct.std::ctype_base"* @_ZSt8__ioinit ) + %tmp10.i = tail call i32 @__cxa_atexit( void (i8*)* @__tcf_0, i8* null, i8* bitcast (i8** @__dso_handle to i8*) ) ; [#uses=0] + ret void +} + +define internal void @__tcf_0(i8* %unnamed_arg) { +entry: + tail call void @_ZNSt8ios_base4InitD1Ev( %"struct.std::ctype_base"* @_ZSt8__ioinit ) + ret void +} + +declare void @_ZNSt8ios_base4InitD1Ev(%"struct.std::ctype_base"*) + +declare void @_ZNSt8ios_base4InitC1Ev(%"struct.std::ctype_base"*) + +declare i32 @__cxa_atexit(void (i8*)*, i8*, i8*) + +define i32 @main() { +entry: + %tmp6 = volatile load float* @a ; [#uses=1] + %tmp9 = tail call float @tanf( float %tmp6 ) ; [#uses=1] + %tmp12 = volatile load double* @b ; [#uses=1] + %tmp13 = tail call double @tan( double %tmp12 ) ; [#uses=1] + %tmp1314 = fptrunc double %tmp13 to float ; [#uses=1] + %tmp16 = tail call %"struct.std::basic_ostream >"* @_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc( %"struct.std::basic_ostream >"* @_ZSt4cout, i8* getelementptr ([12 x i8]* @.str, i32 0, i32 0) ) ; <%"struct.std::basic_ostream >"*> [#uses=1] + %tmp1920 = fpext float %tmp9 to double ; [#uses=1] + %tmp22 = tail call %"struct.std::basic_ostream >"* @_ZNSolsEd( %"struct.std::basic_ostream >"* %tmp16, double %tmp1920 ) ; <%"struct.std::basic_ostream >"*> [#uses=1] + %tmp30 = tail call %"struct.std::basic_ostream >"* @_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_( %"struct.std::basic_ostream >"* %tmp22 ) ; <%"struct.std::basic_ostream >"*> [#uses=0] + %tmp34 = tail call %"struct.std::basic_ostream >"* @_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc( %"struct.std::basic_ostream >"* @_ZSt4cout, i8* getelementptr ([13 x i8]* @.str1, i32 0, i32 0) ) ; <%"struct.std::basic_ostream >"*> [#uses=1] + %tmp3940 = fpext float %tmp1314 to double ; [#uses=1] + %tmp42 = tail call %"struct.std::basic_ostream >"* @_ZNSolsEd( %"struct.std::basic_ostream >"* %tmp34, double %tmp3940 ) ; <%"struct.std::basic_ostream >"*> [#uses=1] + %tmp51 = tail call %"struct.std::basic_ostream >"* @_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_( %"struct.std::basic_ostream >"* %tmp42 ) ; <%"struct.std::basic_ostream >"*> [#uses=0] + ret i32 0 +} + +declare float @tanf(float) + +declare double @tan(double) + +declare %"struct.std::basic_ostream >"* @_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc(%"struct.std::basic_ostream >"*, i8*) + +declare %"struct.std::basic_ostream >"* @_ZNSolsEd(%"struct.std::basic_ostream >"*, double) + +declare %"struct.std::basic_ostream >"* @_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_(%"struct.std::basic_ostream >"*) From resistor at mac.com Mon Jul 2 21:28:17 2007 From: resistor at mac.com (Owen Anderson) Date: Tue, 03 Jul 2007 02:28:17 -0000 Subject: [llvm-commits] [llvm] r37849 - /llvm/trunk/CREDITS.TXT Message-ID: <200707030228.l632SH1d016019@zion.cs.uiuc.edu> Author: resistor Date: Mon Jul 2 21:28:17 2007 New Revision: 37849 URL: http://llvm.org/viewvc/llvm-project?rev=37849&view=rev Log: Test commit. Modified: llvm/trunk/CREDITS.TXT Modified: llvm/trunk/CREDITS.TXT URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/CREDITS.TXT?rev=37849&r1=37848&r2=37849&view=diff ============================================================================== --- llvm/trunk/CREDITS.TXT (original) +++ llvm/trunk/CREDITS.TXT Mon Jul 2 21:28:17 2007 @@ -15,7 +15,8 @@ N: Owen Anderson E: resistor at mac.com -D: LCSSA pass and related LoopUnswitch work, TargetData refactoring, random improvements +D: LCSSA pass and related LoopUnswitch work +D: GVNPRE pass, TargetData refactoring, random improvements N: Henrik Bach D: MingW Win32 API portability layer From greened at obbligato.org Mon Jul 2 22:04:37 2007 From: greened at obbligato.org (David A. Greene) Date: Mon, 2 Jul 2007 22:04:37 -0500 Subject: [llvm-commits] [llvm] r37845 - /llvm/trunk/test/CodeGen/X86/illegal-vector-args-return.ll In-Reply-To: <200707021623.l62GNlaG029742@zion.cs.uiuc.edu> References: <200707021623.l62GNlaG029742@zion.cs.uiuc.edu> Message-ID: <200707022204.38345.greened@obbligato.org> On Monday 02 July 2007 11:23, Dan Gohman wrote: > URL: http://llvm.org/viewvc/llvm-project?rev=37845&view=rev > Log: > Add a basic test-case for passing and returning <4 x double> and > <8 x float> values on X86. Hey Dan, what's the goal of all of this? -Dave From greened at obbligato.org Mon Jul 2 23:28:16 2007 From: greened at obbligato.org (David A. Greene) Date: Mon, 2 Jul 2007 23:28:16 -0500 Subject: [llvm-commits] [llvm] r37845 - /llvm/trunk/test/CodeGen/X86/illegal-vector-args-return.ll In-Reply-To: <200707022204.38345.greened@obbligato.org> References: <200707021623.l62GNlaG029742@zion.cs.uiuc.edu> <200707022204.38345.greened@obbligato.org> Message-ID: <200707022328.16395.greened@obbligato.org> On Monday 02 July 2007 22:04, David A. Greene wrote: > On Monday 02 July 2007 11:23, Dan Gohman wrote: > > URL: http://llvm.org/viewvc/llvm-project?rev=37845&view=rev > > Log: > > Add a basic test-case for passing and returning <4 x double> and > > <8 x float> values on X86. > > Hey Dan, what's the goal of all of this? Sorry folks. Apparently I don't know how to use an e-mail client. That was just supposed to go to Dan. -Dave From clattner at apple.com Mon Jul 2 23:33:17 2007 From: clattner at apple.com (Chris Lattner) Date: Mon, 2 Jul 2007 21:33:17 -0700 Subject: [llvm-commits] [llvm] r37845 - /llvm/trunk/test/CodeGen/X86/illegal-vector-args-return.ll In-Reply-To: <200707022328.16395.greened@obbligato.org> References: <200707021623.l62GNlaG029742@zion.cs.uiuc.edu> <200707022204.38345.greened@obbligato.org> <200707022328.16395.greened@obbligato.org> Message-ID: On Jul 2, 2007, at 9:28 PM, David A. Greene wrote: > On Monday 02 July 2007 22:04, David A. Greene wrote: >> On Monday 02 July 2007 11:23, Dan Gohman wrote: >>> URL: http://llvm.org/viewvc/llvm-project?rev=37845&view=rev >>> Log: >>> Add a basic test-case for passing and returning <4 x double> and >>> <8 x float> values on X86. >> >> Hey Dan, what's the goal of all of this? > > Sorry folks. Apparently I don't know how to use an e-mail client. > That > was just supposed to go to Dan. No worries, the list is configured to reply to the list. This is to prevent people on email discussions from getting many copies IIRC. -Chris From sabre at nondot.org Mon Jul 2 23:41:50 2007 From: sabre at nondot.org (Chris Lattner) Date: Tue, 03 Jul 2007 04:41:50 -0000 Subject: [llvm-commits] [llvm] r37850 - /llvm/trunk/docs/AliasAnalysis.html Message-ID: <200707030441.l634foUc019355@zion.cs.uiuc.edu> Author: lattner Date: Mon Jul 2 23:41:50 2007 New Revision: 37850 URL: http://llvm.org/viewvc/llvm-project?rev=37850&view=rev Log: note where to get steens-aa and ds-aa Modified: llvm/trunk/docs/AliasAnalysis.html Modified: llvm/trunk/docs/AliasAnalysis.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/AliasAnalysis.html?rev=37850&r1=37849&r2=37850&view=diff ============================================================================== --- llvm/trunk/docs/AliasAnalysis.html (original) +++ llvm/trunk/docs/AliasAnalysis.html Mon Jul 2 23:41:50 2007 @@ -755,6 +755,9 @@ Structure Analysis framework. This gives it substantially more precision than the standard algorithm while maintaining excellent analysis scalability.

+

Note that -steens-aa is available in the optional "poolalloc" +module, it is not part of the LLVM core.

+ @@ -775,6 +778,9 @@ only major facility not implemented so far is support for must-alias information.

+

Note that -ds-aa is available in the optional "poolalloc" +module, it is not part of the LLVM core.

+ From djg at cray.com Tue Jul 3 09:03:58 2007 From: djg at cray.com (Dan Gohman) Date: Tue, 03 Jul 2007 14:03:58 -0000 Subject: [llvm-commits] [llvm] r37851 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <200707031403.l63E3woZ011704@zion.cs.uiuc.edu> Author: djg Date: Tue Jul 3 09:03:57 2007 New Revision: 37851 URL: http://llvm.org/viewvc/llvm-project?rev=37851&view=rev Log: Fix several over-aggressive folds for undef nodes in dagcombine, to follow the rules for undef used in instcombine. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=37851&r1=37850&r2=37851&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Jul 3 09:03:57 2007 @@ -854,6 +854,9 @@ SDOperand FoldedVOp = SimplifyVBinOp(N); if (FoldedVOp.Val) return FoldedVOp; + // fold (add x, undef) -> undef + if (N1.getOpcode() == ISD::UNDEF) + return N1; // fold (add c1, c2) -> c1+c2 if (N0C && N1C) return DAG.getNode(ISD::ADD, VT, N0, N1); @@ -925,10 +928,6 @@ if (Result.Val) return Result; } - // If either operand is undef, the result is undef - if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) - return DAG.getNode(ISD::UNDEF, VT); - return SDOperand(); } @@ -1029,7 +1028,7 @@ SDOperand Result = combineSelectAndUse(N, N1, N0, DAG); if (Result.Val) return Result; } - // If either operand is undef, the result is undef + // If either operand of a sub is undef, the result is undef if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) return DAG.getNode(ISD::UNDEF, VT); @@ -1047,6 +1046,9 @@ SDOperand FoldedVOp = SimplifyVBinOp(N); if (FoldedVOp.Val) return FoldedVOp; + // fold (mul x, undef) -> 0 + if (N1.getOpcode() == ISD::UNDEF) + return DAG.getConstant(0, VT); // fold (mul c1, c2) -> c1*c2 if (N0C && N1C) return DAG.getNode(ISD::MUL, VT, N0, N1); @@ -1112,10 +1114,6 @@ if (RMUL.Val != 0) return RMUL; - // If either operand is undef, the result is undef - if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) - return DAG.getNode(ISD::UNDEF, VT); - return SDOperand(); } @@ -1185,9 +1183,12 @@ if (Op.Val) return Op; } - // If either operand is undef, the result is undef - if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) - return DAG.getNode(ISD::UNDEF, VT); + // undef / X -> 0 + if (N0.getOpcode() == ISD::UNDEF) + return DAG.getConstant(0, VT); + // X / undef -> undef + if (N1.getOpcode() == ISD::UNDEF) + return N1; return SDOperand(); } @@ -1230,9 +1231,12 @@ if (Op.Val) return Op; } - // If either operand is undef, the result is undef - if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) - return DAG.getNode(ISD::UNDEF, VT); + // undef / X -> 0 + if (N0.getOpcode() == ISD::UNDEF) + return DAG.getConstant(0, VT); + // X / undef -> undef + if (N1.getOpcode() == ISD::UNDEF) + return N1; return SDOperand(); } @@ -1265,9 +1269,12 @@ return Sub; } - // If either operand is undef, the result is undef - if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) - return DAG.getNode(ISD::UNDEF, VT); + // undef % X -> 0 + if (N0.getOpcode() == ISD::UNDEF) + return DAG.getConstant(0, VT); + // X % undef -> undef + if (N1.getOpcode() == ISD::UNDEF) + return N1; return SDOperand(); } @@ -1307,9 +1314,12 @@ return Sub; } - // If either operand is undef, the result is undef - if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) - return DAG.getNode(ISD::UNDEF, VT); + // undef % X -> 0 + if (N0.getOpcode() == ISD::UNDEF) + return DAG.getConstant(0, VT); + // X % undef -> undef + if (N1.getOpcode() == ISD::UNDEF) + return N1; return SDOperand(); } @@ -1328,9 +1338,9 @@ return DAG.getNode(ISD::SRA, N0.getValueType(), N0, DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1, TLI.getShiftAmountTy())); - // If either operand is undef, the result is undef - if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) - return DAG.getNode(ISD::UNDEF, VT); + // fold (mulhs x, undef) -> 0 + if (N1.getOpcode() == ISD::UNDEF) + return DAG.getConstant(0, VT); return SDOperand(); } @@ -1347,9 +1357,9 @@ // fold (mulhu x, 1) -> 0 if (N1C && N1C->getValue() == 1) return DAG.getConstant(0, N0.getValueType()); - // If either operand is undef, the result is undef - if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) - return DAG.getNode(ISD::UNDEF, VT); + // fold (mulhu x, undef) -> 0 + if (N1.getOpcode() == ISD::UNDEF) + return DAG.getConstant(0, VT); return SDOperand(); } @@ -1390,10 +1400,6 @@ return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); } - // If either operand is undef, the result is undef - if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) - return DAG.getNode(ISD::UNDEF, VT); - return SDOperand(); } @@ -1409,6 +1415,9 @@ SDOperand FoldedVOp = SimplifyVBinOp(N); if (FoldedVOp.Val) return FoldedVOp; + // fold (and x, undef) -> 0 + if (N1.getOpcode() == ISD::UNDEF) + return DAG.getConstant(0, VT); // fold (and c1, c2) -> c1&c2 if (N0C && N1C) return DAG.getNode(ISD::AND, VT, N0, N1); @@ -1594,6 +1603,9 @@ SDOperand FoldedVOp = SimplifyVBinOp(N); if (FoldedVOp.Val) return FoldedVOp; + // fold (or x, undef) -> -1 + if (N1.getOpcode() == ISD::UNDEF) + return DAG.getConstant(-1, VT); // fold (or c1, c2) -> c1|c2 if (N0C && N1C) return DAG.getNode(ISD::OR, VT, N0, N1); @@ -1877,6 +1889,9 @@ SDOperand FoldedVOp = SimplifyVBinOp(N); if (FoldedVOp.Val) return FoldedVOp; + // fold (xor x, undef) -> undef + if (N1.getOpcode() == ISD::UNDEF) + return N1; // fold (xor c1, c2) -> c1^c2 if (N0C && N1C) return DAG.getNode(ISD::XOR, VT, N0, N1); @@ -3009,10 +3024,6 @@ return DAG.getNode(ISD::FADD, VT, N0.getOperand(0), DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1)); - // If either operand is undef, the result is undef - if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) - return DAG.getNode(ISD::UNDEF, VT); - return SDOperand(); } @@ -3040,10 +3051,6 @@ if (isNegatibleForFree(N1)) return DAG.getNode(ISD::FADD, VT, N0, GetNegatedExpression(N1, DAG)); - // If either operand is undef, the result is undef - if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) - return DAG.getNode(ISD::UNDEF, VT); - return SDOperand(); } @@ -3088,10 +3095,6 @@ return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0), DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1)); - // If either operand is undef, the result is undef - if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) - return DAG.getNode(ISD::UNDEF, VT); - return SDOperand(); } @@ -3122,10 +3125,6 @@ } } - // If either operand is undef, the result is undef - if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) - return DAG.getNode(ISD::UNDEF, VT); - return SDOperand(); } @@ -3140,10 +3139,6 @@ if (N0CFP && N1CFP) return DAG.getNode(ISD::FREM, VT, N0, N1); - // If either operand is undef, the result is undef - if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) - return DAG.getNode(ISD::UNDEF, VT); - return SDOperand(); } From baldrick at free.fr Tue Jul 3 09:43:14 2007 From: baldrick at free.fr (Duncan Sands) Date: Tue, 3 Jul 2007 16:43:14 +0200 Subject: [llvm-commits] [llvm] r37851 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp In-Reply-To: <200707031403.l63E3woZ011704@zion.cs.uiuc.edu> References: <200707031403.l63E3woZ011704@zion.cs.uiuc.edu> Message-ID: <200707031643.14426.baldrick@free.fr> Hi Dan, > + // fold (add x, undef) -> undef > + if (N1.getOpcode() == ISD::UNDEF) > + return N1; what if N0 is undef and not N1? > - // If either operand is undef, the result is undef > - if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) > - return DAG.getNode(ISD::UNDEF, VT); > - Did you move this earlier to make it more efficient, or for another reason? > - // If either operand is undef, the result is undef > + // If either operand of a sub is undef, the result is undef > if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) > return DAG.getNode(ISD::UNDEF, VT); If it was more efficient doing this earlier for add, presumably the same is true for subtraction. > + // fold (mul x, undef) -> 0 > + if (N1.getOpcode() == ISD::UNDEF) > + return DAG.getConstant(0, VT); Yes, this seems better :) Again, is the undef guaranteed to be in N1 and not N0? > + // undef / X -> 0 > + if (N0.getOpcode() == ISD::UNDEF) > + return DAG.getConstant(0, VT); Indeed. > + // X / undef -> undef > + if (N1.getOpcode() == ISD::UNDEF) > + return N1; Here you use that X / 0 is undefined in the usual sense, and can take on any value. Is it undefined? Also, wouldn't it be better to do this before the N0 one, in case you have undef/undef ? Same comments for udiv, srem and urem. > @@ -1390,10 +1400,6 @@ > return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); > } > > - // If either operand is undef, the result is undef > - if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) > - return DAG.getNode(ISD::UNDEF, VT); > - > return SDOperand(); > } (SimplifyBinOpWithSameOpcodeHands) In this case both N0 and N1 must be undef (since by definition they have the same opcode here), so returning undef seems ok here. That said, the original "if" was kind of silly since if one opcode is undef then so is the other. > + // fold (or x, undef) -> -1 > + if (N1.getOpcode() == ISD::UNDEF) > + return DAG.getConstant(-1, VT); Is this the right way to get an all-bits-one value? > @@ -3040,10 +3051,6 @@ > if (isNegatibleForFree(N1)) > return DAG.getNode(ISD::FADD, VT, N0, GetNegatedExpression(N1, DAG)); > > - // If either operand is undef, the result is undef > - if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) > - return DAG.getNode(ISD::UNDEF, VT); > - > return SDOperand(); > } Why the difference between fadd and fsub? If you are worried about NaNs etc, at worst you can always, I suppose, turn x fsub undef into x. Likewise for the other floating point ops. Ciao, Duncan. From clattner at apple.com Tue Jul 3 11:23:19 2007 From: clattner at apple.com (Chris Lattner) Date: Tue, 3 Jul 2007 09:23:19 -0700 Subject: [llvm-commits] [llvm] r37851 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp In-Reply-To: <200707031643.14426.baldrick@free.fr> References: <200707031403.l63E3woZ011704@zion.cs.uiuc.edu> <200707031643.14426.baldrick@free.fr> Message-ID: <27DA872F-8A61-4916-9C7D-B151D16440A3@apple.com> On Jul 3, 2007, at 7:43 AM, Duncan Sands wrote: > Hi Dan, >> + // fold (add x, undef) -> undef >> + if (N1.getOpcode() == ISD::UNDEF) >> + return N1; > > what if N0 is undef and not N1? Presumably, undef is being canonicalized to the RHS somewhere. I don't know if this is actually true in the dag combiner though, it should be checked. >> + // fold (mul x, undef) -> 0 >> + if (N1.getOpcode() == ISD::UNDEF) >> + return DAG.getConstant(0, VT); > > Yes, this seems better :) Again, is the undef guaranteed to be > in N1 and not N0? Does this work for vectors? Does DAG.getConstant(0, MVT::v4i32) work? This xform should probably be disabled after legalize for vectors. >> + // fold (or x, undef) -> -1 >> + if (N1.getOpcode() == ISD::UNDEF) >> + return DAG.getConstant(-1, VT); > > Is this the right way to get an all-bits-one value? Yes, but this has the same problem with vectors. :) -Chris From greened at obbligato.org Tue Jul 3 11:43:08 2007 From: greened at obbligato.org (David A. Greene) Date: Tue, 3 Jul 2007 11:43:08 -0500 Subject: [llvm-commits] [llvm] r37851 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp In-Reply-To: <27DA872F-8A61-4916-9C7D-B151D16440A3@apple.com> References: <200707031403.l63E3woZ011704@zion.cs.uiuc.edu> <200707031643.14426.baldrick@free.fr> <27DA872F-8A61-4916-9C7D-B151D16440A3@apple.com> Message-ID: <200707031143.08661.greened@obbligato.org> On Tuesday 03 July 2007 11:23, Chris Lattner wrote: > >> + // fold (or x, undef) -> -1 > >> + if (N1.getOpcode() == ISD::UNDEF) > >> + return DAG.getConstant(-1, VT); > > > > Is this the right way to get an all-bits-one value? > > Yes, but this has the same problem with vectors. :) I don't understand the comment about vectors, but I would have expected "all ones" to be spelled "~0ull." Of course, the suffix used might depend on the host architecture, which makes things tricky. But not every host may be two's-complement, either. :) -Dave From asl at math.spbu.ru Tue Jul 3 12:01:59 2007 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Tue, 03 Jul 2007 17:01:59 -0000 Subject: [llvm-commits] [llvm] r37852 - in /llvm/trunk: autoconf/configure.ac configure Message-ID: <200707031701.l63H1xKa016388@zion.cs.uiuc.edu> Author: asl Date: Tue Jul 3 12:01:58 2007 New Revision: 37852 URL: http://llvm.org/viewvc/llvm-project?rev=37852&view=rev Log: Rename llvm-test => test-suite. By Dave Greene. Modified: llvm/trunk/autoconf/configure.ac llvm/trunk/configure Modified: llvm/trunk/autoconf/configure.ac URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/configure.ac?rev=37852&r1=37851&r2=37852&view=diff ============================================================================== --- llvm/trunk/autoconf/configure.ac (original) +++ llvm/trunk/autoconf/configure.ac Tue Jul 3 12:01:58 2007 @@ -70,7 +70,7 @@ sample) AC_CONFIG_SUBDIRS([projects/sample]) ;; privbracket) AC_CONFIG_SUBDIRS([projects/privbracket]) ;; llvm-stacker) AC_CONFIG_SUBDIRS([projects/llvm-stacker]) ;; - llvm-test) AC_CONFIG_SUBDIRS([projects/llvm-test]) ;; + test-suite) AC_CONFIG_SUBDIRS([projects/test-suite]) ;; llvm-reopt) AC_CONFIG_SUBDIRS([projects/llvm-reopt]);; llvm-gcc) AC_CONFIG_SUBDIRS([projects/llvm-gcc]) ;; llvm-java) AC_CONFIG_SUBDIRS([projects/llvm-java]) ;; Modified: llvm/trunk/configure URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/configure?rev=37852&r1=37851&r2=37852&view=diff ============================================================================== --- llvm/trunk/configure (original) +++ llvm/trunk/configure Tue Jul 3 12:01:58 2007 @@ -944,7 +944,7 @@ ac_subdirs_all='projects/sample projects/privbracket projects/llvm-stacker -projects/llvm-test +projects/test-suite projects/llvm-reopt projects/llvm-gcc projects/llvm-java @@ -2074,7 +2074,7 @@ ;; llvm-stacker) subdirs="$subdirs projects/llvm-stacker" ;; - llvm-test) subdirs="$subdirs projects/llvm-test" + test-suite) subdirs="$subdirs projects/test-suite" ;; llvm-reopt) subdirs="$subdirs projects/llvm-reopt" ;; From dalej at apple.com Tue Jul 3 12:07:33 2007 From: dalej at apple.com (Dale Johannesen) Date: Tue, 03 Jul 2007 17:07:33 -0000 Subject: [llvm-commits] [llvm] r37853 - in /llvm/trunk/lib/Target/X86: X86FloatingPoint.cpp X86InstrFPStack.td Message-ID: <200707031707.l63H7XRT016593@zion.cs.uiuc.edu> Author: johannes Date: Tue Jul 3 12:07:33 2007 New Revision: 37853 URL: http://llvm.org/viewvc/llvm-project?rev=37853&view=rev Log: Some spacing fixes. Cosmetic. Modified: llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp llvm/trunk/lib/Target/X86/X86InstrFPStack.td Modified: llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp?rev=37853&r1=37852&r2=37853&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp Tue Jul 3 12:07:33 2007 @@ -326,8 +326,8 @@ static const TableEntry OpcodeTable[] = { { X86::FpABS32 , X86::FABS }, { X86::FpABS64 , X86::FABS }, - { X86::FpADD32m , X86::FADD32m }, - { X86::FpADD64m , X86::FADD64m }, + { X86::FpADD32m , X86::FADD32m }, + { X86::FpADD64m , X86::FADD64m }, { X86::FpCHS32 , X86::FCHS }, { X86::FpCHS64 , X86::FCHS }, { X86::FpCMOVB32 , X86::FCMOVB }, @@ -348,10 +348,10 @@ { X86::FpCMOVP64 , X86::FCMOVP }, { X86::FpCOS32 , X86::FCOS }, { X86::FpCOS64 , X86::FCOS }, - { X86::FpDIV32m , X86::FDIV32m }, - { X86::FpDIV64m , X86::FDIV64m }, - { X86::FpDIVR32m , X86::FDIVR32m }, - { X86::FpDIVR64m , X86::FDIVR64m }, + { X86::FpDIV32m , X86::FDIV32m }, + { X86::FpDIV64m , X86::FDIV64m }, + { X86::FpDIVR32m , X86::FDIVR32m }, + { X86::FpDIVR64m , X86::FDIVR64m }, { X86::FpIADD16m32 , X86::FIADD16m }, { X86::FpIADD16m64 , X86::FIADD16m }, { X86::FpIADD32m32 , X86::FIADD32m }, @@ -398,21 +398,21 @@ { X86::FpLD064 , X86::FLD0 }, { X86::FpLD132 , X86::FLD1 }, { X86::FpLD164 , X86::FLD1 }, - { X86::FpLD32m , X86::FLD32m }, - { X86::FpLD64m , X86::FLD64m }, - { X86::FpMUL32m , X86::FMUL32m }, - { X86::FpMUL64m , X86::FMUL64m }, + { X86::FpLD32m , X86::FLD32m }, + { X86::FpLD64m , X86::FLD64m }, + { X86::FpMUL32m , X86::FMUL32m }, + { X86::FpMUL64m , X86::FMUL64m }, { X86::FpSIN32 , X86::FSIN }, { X86::FpSIN64 , X86::FSIN }, { X86::FpSQRT32 , X86::FSQRT }, { X86::FpSQRT64 , X86::FSQRT }, - { X86::FpST32m , X86::FST32m }, - { X86::FpST64m , X86::FST64m }, + { X86::FpST32m , X86::FST32m }, + { X86::FpST64m , X86::FST64m }, { X86::FpST64m32 , X86::FST32m }, - { X86::FpSUB32m , X86::FSUB32m }, - { X86::FpSUB64m , X86::FSUB64m }, - { X86::FpSUBR32m , X86::FSUBR32m }, - { X86::FpSUBR64m , X86::FSUBR64m }, + { X86::FpSUB32m , X86::FSUB32m }, + { X86::FpSUB64m , X86::FSUB64m }, + { X86::FpSUBR32m , X86::FSUBR32m }, + { X86::FpSUBR64m , X86::FSUBR64m }, { X86::FpTST32 , X86::FTST }, { X86::FpTST64 , X86::FTST }, { X86::FpUCOMIr32 , X86::FUCOMIr }, Modified: llvm/trunk/lib/Target/X86/X86InstrFPStack.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFPStack.td?rev=37853&r1=37852&r2=37853&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrFPStack.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrFPStack.td Tue Jul 3 12:07:33 2007 @@ -17,27 +17,27 @@ // FPStack specific DAG Nodes. //===----------------------------------------------------------------------===// -def SDTX86FpGet : SDTypeProfile<1, 0, [SDTCisFP<0>]>; -def SDTX86FpSet : SDTypeProfile<0, 1, [SDTCisFP<0>]>; -def SDTX86Fld : SDTypeProfile<1, 2, [SDTCisFP<0>, - SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>]>; -def SDTX86Fst : SDTypeProfile<0, 3, [SDTCisFP<0>, - SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>]>; -def SDTX86Fild : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisPtrTy<1>, - SDTCisVT<2, OtherVT>]>; -def SDTX86FpToIMem: SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>; +def SDTX86FpGet : SDTypeProfile<1, 0, [SDTCisFP<0>]>; +def SDTX86FpSet : SDTypeProfile<0, 1, [SDTCisFP<0>]>; +def SDTX86Fld : SDTypeProfile<1, 2, [SDTCisFP<0>, + SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>]>; +def SDTX86Fst : SDTypeProfile<0, 3, [SDTCisFP<0>, + SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>]>; +def SDTX86Fild : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisPtrTy<1>, + SDTCisVT<2, OtherVT>]>; +def SDTX86FpToIMem : SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>; -def X86fpget : SDNode<"X86ISD::FP_GET_RESULT", SDTX86FpGet, +def X86fpget : SDNode<"X86ISD::FP_GET_RESULT", SDTX86FpGet, [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>; -def X86fpset : SDNode<"X86ISD::FP_SET_RESULT", SDTX86FpSet, +def X86fpset : SDNode<"X86ISD::FP_SET_RESULT", SDTX86FpSet, [SDNPHasChain, SDNPOutFlag]>; -def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld, +def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld, [SDNPHasChain]>; -def X86fst : SDNode<"X86ISD::FST", SDTX86Fst, +def X86fst : SDNode<"X86ISD::FST", SDTX86Fst, [SDNPHasChain, SDNPInFlag]>; -def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild, +def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild, [SDNPHasChain]>; -def X86fildflag: SDNode<"X86ISD::FILD_FLAG",SDTX86Fild, +def X86fildflag : SDNode<"X86ISD::FILD_FLAG",SDTX86Fild, [SDNPHasChain, SDNPOutFlag]>; def X86fp_to_i16mem : SDNode<"X86ISD::FP_TO_INT16_IN_MEM", SDTX86FpToIMem, [SDNPHasChain]>; @@ -71,29 +71,29 @@ // Some 'special' instructions let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler. def FP32_TO_INT16_IN_MEM : I<0, Pseudo, - (ops i16mem:$dst, RFP32:$src), - "#FP32_TO_INT16_IN_MEM PSEUDO!", - [(X86fp_to_i16mem RFP32:$src, addr:$dst)]>; + (ops i16mem:$dst, RFP32:$src), + "#FP32_TO_INT16_IN_MEM PSEUDO!", + [(X86fp_to_i16mem RFP32:$src, addr:$dst)]>; def FP32_TO_INT32_IN_MEM : I<0, Pseudo, - (ops i32mem:$dst, RFP32:$src), - "#FP32_TO_INT32_IN_MEM PSEUDO!", - [(X86fp_to_i32mem RFP32:$src, addr:$dst)]>; + (ops i32mem:$dst, RFP32:$src), + "#FP32_TO_INT32_IN_MEM PSEUDO!", + [(X86fp_to_i32mem RFP32:$src, addr:$dst)]>; def FP32_TO_INT64_IN_MEM : I<0, Pseudo, - (ops i64mem:$dst, RFP32:$src), - "#FP32_TO_INT64_IN_MEM PSEUDO!", - [(X86fp_to_i64mem RFP32:$src, addr:$dst)]>; + (ops i64mem:$dst, RFP32:$src), + "#FP32_TO_INT64_IN_MEM PSEUDO!", + [(X86fp_to_i64mem RFP32:$src, addr:$dst)]>; def FP64_TO_INT16_IN_MEM : I<0, Pseudo, - (ops i16mem:$dst, RFP64:$src), - "#FP64_TO_INT16_IN_MEM PSEUDO!", - [(X86fp_to_i16mem RFP64:$src, addr:$dst)]>; + (ops i16mem:$dst, RFP64:$src), + "#FP64_TO_INT16_IN_MEM PSEUDO!", + [(X86fp_to_i16mem RFP64:$src, addr:$dst)]>; def FP64_TO_INT32_IN_MEM : I<0, Pseudo, - (ops i32mem:$dst, RFP64:$src), - "#FP64_TO_INT32_IN_MEM PSEUDO!", - [(X86fp_to_i32mem RFP64:$src, addr:$dst)]>; + (ops i32mem:$dst, RFP64:$src), + "#FP64_TO_INT32_IN_MEM PSEUDO!", + [(X86fp_to_i32mem RFP64:$src, addr:$dst)]>; def FP64_TO_INT64_IN_MEM : I<0, Pseudo, - (ops i64mem:$dst, RFP64:$src), - "#FP64_TO_INT64_IN_MEM PSEUDO!", - [(X86fp_to_i64mem RFP64:$src, addr:$dst)]>; + (ops i64mem:$dst, RFP64:$src), + "#FP64_TO_INT64_IN_MEM PSEUDO!", + [(X86fp_to_i64mem RFP64:$src, addr:$dst)]>; } let isTerminator = 1 in @@ -124,10 +124,10 @@ // Random Pseudo Instructions. def FpGETRESULT32 : FpI_<(ops RFP32:$dst), SpecialFP, - [(set RFP32:$dst, X86fpget)]>; // FPR = ST(0) + [(set RFP32:$dst, X86fpget)]>; // FPR = ST(0) def FpGETRESULT64 : FpI_<(ops RFP64:$dst), SpecialFP, - [(set RFP64:$dst, X86fpget)]>; // FPR = ST(0) + [(set RFP64:$dst, X86fpget)]>; // FPR = ST(0) let noResults = 1 in { def FpSETRESULT32 : FpI_<(ops RFP32:$src), SpecialFP, @@ -174,40 +174,40 @@ // Binary Ops with a memory source. def FpADD32m : FpI<(ops RFP32:$dst, RFP32:$src1, f32mem:$src2), OneArgFPRW, - [(set RFP32:$dst, (fadd RFP32:$src1, (loadf32 addr:$src2)))]>; + [(set RFP32:$dst, (fadd RFP32:$src1, (loadf32 addr:$src2)))]>; // ST(0) = ST(0) + [mem32] def FpADD64m : FpI<(ops RFP64:$dst, RFP64:$src1, f64mem:$src2), OneArgFPRW, - [(set RFP64:$dst, (fadd RFP64:$src1, (loadf64 addr:$src2)))]>; + [(set RFP64:$dst, (fadd RFP64:$src1, (loadf64 addr:$src2)))]>; // ST(0) = ST(0) + [mem64] def FpMUL32m : FpI<(ops RFP32:$dst, RFP32:$src1, f32mem:$src2), OneArgFPRW, - [(set RFP32:$dst, (fmul RFP32:$src1, (loadf32 addr:$src2)))]>; + [(set RFP32:$dst, (fmul RFP32:$src1, (loadf32 addr:$src2)))]>; // ST(0) = ST(0) * [mem32] def FpMUL64m : FpI<(ops RFP64:$dst, RFP64:$src1, f64mem:$src2), OneArgFPRW, - [(set RFP64:$dst, (fmul RFP64:$src1, (loadf64 addr:$src2)))]>; + [(set RFP64:$dst, (fmul RFP64:$src1, (loadf64 addr:$src2)))]>; // ST(0) = ST(0) * [mem64] def FpSUB32m : FpI<(ops RFP32:$dst, RFP32:$src1, f32mem:$src2), OneArgFPRW, - [(set RFP32:$dst, (fsub RFP32:$src1, (loadf32 addr:$src2)))]>; + [(set RFP32:$dst, (fsub RFP32:$src1, (loadf32 addr:$src2)))]>; // ST(0) = ST(0) - [mem32] def FpSUB64m : FpI<(ops RFP64:$dst, RFP64:$src1, f64mem:$src2), OneArgFPRW, - [(set RFP64:$dst, (fsub RFP64:$src1, (loadf64 addr:$src2)))]>; + [(set RFP64:$dst, (fsub RFP64:$src1, (loadf64 addr:$src2)))]>; // ST(0) = ST(0) - [mem64] def FpSUBR32m : FpI<(ops RFP32:$dst, RFP32:$src1, f32mem:$src2), OneArgFPRW, - [(set RFP32:$dst, (fsub (loadf32 addr:$src2), RFP32:$src1))]>; + [(set RFP32:$dst, (fsub (loadf32 addr:$src2), RFP32:$src1))]>; // ST(0) = [mem32] - ST(0) def FpSUBR64m : FpI<(ops RFP64:$dst, RFP64:$src1, f64mem:$src2), OneArgFPRW, - [(set RFP64:$dst, (fsub (loadf64 addr:$src2), RFP64:$src1))]>; + [(set RFP64:$dst, (fsub (loadf64 addr:$src2), RFP64:$src1))]>; // ST(0) = [mem64] - ST(0) def FpDIV32m : FpI<(ops RFP32:$dst, RFP32:$src1, f32mem:$src2), OneArgFPRW, - [(set RFP32:$dst, (fdiv RFP32:$src1, (loadf32 addr:$src2)))]>; + [(set RFP32:$dst, (fdiv RFP32:$src1, (loadf32 addr:$src2)))]>; // ST(0) = ST(0) / [mem32] def FpDIV64m : FpI<(ops RFP64:$dst, RFP64:$src1, f64mem:$src2), OneArgFPRW, - [(set RFP64:$dst, (fdiv RFP64:$src1, (loadf64 addr:$src2)))]>; + [(set RFP64:$dst, (fdiv RFP64:$src1, (loadf64 addr:$src2)))]>; // ST(0) = ST(0) / [mem64] def FpDIVR32m : FpI<(ops RFP32:$dst, RFP32:$src1, f32mem:$src2), OneArgFPRW, - [(set RFP32:$dst, (fdiv (loadf32 addr:$src2), RFP32:$src1))]>; + [(set RFP32:$dst, (fdiv (loadf32 addr:$src2), RFP32:$src1))]>; // ST(0) = [mem32] / ST(0) def FpDIVR64m : FpI<(ops RFP64:$dst, RFP64:$src1, f64mem:$src2), OneArgFPRW, - [(set RFP64:$dst, (fdiv (loadf64 addr:$src2), RFP64:$src1))]>; + [(set RFP64:$dst, (fdiv (loadf64 addr:$src2), RFP64:$src1))]>; // ST(0) = [mem64] / ST(0) @@ -226,101 +226,101 @@ def FpIADD16m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i16mem:$src2), OneArgFPRW, [(set RFP32:$dst, (fadd RFP32:$src1, - (X86fild addr:$src2, i16)))]>; - // ST(0) = ST(0) + [mem16int] + (X86fild addr:$src2, i16)))]>; + // ST(0) = ST(0) + [mem16int] def FpIADD32m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i32mem:$src2), OneArgFPRW, [(set RFP32:$dst, (fadd RFP32:$src1, - (X86fild addr:$src2, i32)))]>; - // ST(0) = ST(0) + [mem32int] + (X86fild addr:$src2, i32)))]>; + // ST(0) = ST(0) + [mem32int] def FpIMUL16m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i16mem:$src2), OneArgFPRW, [(set RFP32:$dst, (fmul RFP32:$src1, - (X86fild addr:$src2, i16)))]>; - // ST(0) = ST(0) * [mem16int] + (X86fild addr:$src2, i16)))]>; + // ST(0) = ST(0) * [mem16int] def FpIMUL32m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i32mem:$src2), OneArgFPRW, [(set RFP32:$dst, (fmul RFP32:$src1, - (X86fild addr:$src2, i32)))]>; - // ST(0) = ST(0) * [mem32int] + (X86fild addr:$src2, i32)))]>; + // ST(0) = ST(0) * [mem32int] def FpISUB16m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i16mem:$src2), OneArgFPRW, [(set RFP32:$dst, (fsub RFP32:$src1, - (X86fild addr:$src2, i16)))]>; - // ST(0) = ST(0) - [mem16int] + (X86fild addr:$src2, i16)))]>; + // ST(0) = ST(0) - [mem16int] def FpISUB32m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i32mem:$src2), OneArgFPRW, [(set RFP32:$dst, (fsub RFP32:$src1, - (X86fild addr:$src2, i32)))]>; - // ST(0) = ST(0) - [mem32int] -def FpISUBR16m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i16mem:$src2), OneArgFPRW, - [(set RFP32:$dst, (fsub (X86fild addr:$src2, i16), - RFP32:$src1))]>; - // ST(0) = [mem16int] - ST(0) -def FpISUBR32m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i32mem:$src2), OneArgFPRW, - [(set RFP32:$dst, (fsub (X86fild addr:$src2, i32), - RFP32:$src1))]>; - // ST(0) = [mem32int] - ST(0) + (X86fild addr:$src2, i32)))]>; + // ST(0) = ST(0) - [mem32int] +def FpISUBR16m32: FpI<(ops RFP32:$dst, RFP32:$src1, i16mem:$src2), OneArgFPRW, + [(set RFP32:$dst, (fsub (X86fild addr:$src2, i16), + RFP32:$src1))]>; + // ST(0) = [mem16int] - ST(0) +def FpISUBR32m32: FpI<(ops RFP32:$dst, RFP32:$src1, i32mem:$src2), OneArgFPRW, + [(set RFP32:$dst, (fsub (X86fild addr:$src2, i32), + RFP32:$src1))]>; + // ST(0) = [mem32int] - ST(0) def FpIDIV16m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i16mem:$src2), OneArgFPRW, [(set RFP32:$dst, (fdiv RFP32:$src1, - (X86fild addr:$src2, i16)))]>; - // ST(0) = ST(0) / [mem16int] + (X86fild addr:$src2, i16)))]>; + // ST(0) = ST(0) / [mem16int] def FpIDIV32m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i32mem:$src2), OneArgFPRW, [(set RFP32:$dst, (fdiv RFP32:$src1, - (X86fild addr:$src2, i32)))]>; - // ST(0) = ST(0) / [mem32int] -def FpIDIVR16m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i16mem:$src2), OneArgFPRW, - [(set RFP32:$dst, (fdiv (X86fild addr:$src2, i16), - RFP32:$src1))]>; - // ST(0) = [mem16int] / ST(0) -def FpIDIVR32m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i32mem:$src2), OneArgFPRW, - [(set RFP32:$dst, (fdiv (X86fild addr:$src2, i32), - RFP32:$src1))]>; - // ST(0) = [mem32int] / ST(0) + (X86fild addr:$src2, i32)))]>; + // ST(0) = ST(0) / [mem32int] +def FpIDIVR16m32: FpI<(ops RFP32:$dst, RFP32:$src1, i16mem:$src2), OneArgFPRW, + [(set RFP32:$dst, (fdiv (X86fild addr:$src2, i16), + RFP32:$src1))]>; + // ST(0) = [mem16int] / ST(0) +def FpIDIVR32m32: FpI<(ops RFP32:$dst, RFP32:$src1, i32mem:$src2), OneArgFPRW, + [(set RFP32:$dst, (fdiv (X86fild addr:$src2, i32), + RFP32:$src1))]>; + // ST(0) = [mem32int] / ST(0) def FpIADD16m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i16mem:$src2), OneArgFPRW, [(set RFP64:$dst, (fadd RFP64:$src1, - (X86fild addr:$src2, i16)))]>; - // ST(0) = ST(0) + [mem16int] + (X86fild addr:$src2, i16)))]>; + // ST(0) = ST(0) + [mem16int] def FpIADD32m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i32mem:$src2), OneArgFPRW, [(set RFP64:$dst, (fadd RFP64:$src1, - (X86fild addr:$src2, i32)))]>; - // ST(0) = ST(0) + [mem32int] + (X86fild addr:$src2, i32)))]>; + // ST(0) = ST(0) + [mem32int] def FpIMUL16m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i16mem:$src2), OneArgFPRW, [(set RFP64:$dst, (fmul RFP64:$src1, - (X86fild addr:$src2, i16)))]>; - // ST(0) = ST(0) * [mem16int] + (X86fild addr:$src2, i16)))]>; + // ST(0) = ST(0) * [mem16int] def FpIMUL32m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i32mem:$src2), OneArgFPRW, [(set RFP64:$dst, (fmul RFP64:$src1, - (X86fild addr:$src2, i32)))]>; - // ST(0) = ST(0) * [mem32int] + (X86fild addr:$src2, i32)))]>; + // ST(0) = ST(0) * [mem32int] def FpISUB16m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i16mem:$src2), OneArgFPRW, [(set RFP64:$dst, (fsub RFP64:$src1, - (X86fild addr:$src2, i16)))]>; - // ST(0) = ST(0) - [mem16int] + (X86fild addr:$src2, i16)))]>; + // ST(0) = ST(0) - [mem16int] def FpISUB32m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i32mem:$src2), OneArgFPRW, [(set RFP64:$dst, (fsub RFP64:$src1, - (X86fild addr:$src2, i32)))]>; - // ST(0) = ST(0) - [mem32int] -def FpISUBR16m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i16mem:$src2), OneArgFPRW, + (X86fild addr:$src2, i32)))]>; + // ST(0) = ST(0) - [mem32int] +def FpISUBR16m64: FpI<(ops RFP64:$dst, RFP64:$src1, i16mem:$src2), OneArgFPRW, [(set RFP64:$dst, (fsub (X86fild addr:$src2, i16), - RFP64:$src1))]>; - // ST(0) = [mem16int] - ST(0) -def FpISUBR32m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i32mem:$src2), OneArgFPRW, - [(set RFP64:$dst, (fsub (X86fild addr:$src2, i32), - RFP64:$src1))]>; - // ST(0) = [mem32int] - ST(0) + RFP64:$src1))]>; + // ST(0) = [mem16int] - ST(0) +def FpISUBR32m64: FpI<(ops RFP64:$dst, RFP64:$src1, i32mem:$src2), OneArgFPRW, + [(set RFP64:$dst, (fsub (X86fild addr:$src2, i32), + RFP64:$src1))]>; + // ST(0) = [mem32int] - ST(0) def FpIDIV16m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i16mem:$src2), OneArgFPRW, [(set RFP64:$dst, (fdiv RFP64:$src1, - (X86fild addr:$src2, i16)))]>; - // ST(0) = ST(0) / [mem16int] + (X86fild addr:$src2, i16)))]>; + // ST(0) = ST(0) / [mem16int] def FpIDIV32m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i32mem:$src2), OneArgFPRW, [(set RFP64:$dst, (fdiv RFP64:$src1, - (X86fild addr:$src2, i32)))]>; - // ST(0) = ST(0) / [mem32int] -def FpIDIVR16m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i16mem:$src2), OneArgFPRW, - [(set RFP64:$dst, (fdiv (X86fild addr:$src2, i16), - RFP64:$src1))]>; - // ST(0) = [mem16int] / ST(0) -def FpIDIVR32m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i32mem:$src2), OneArgFPRW, - [(set RFP64:$dst, (fdiv (X86fild addr:$src2, i32), - RFP64:$src1))]>; - // ST(0) = [mem32int] / ST(0) + (X86fild addr:$src2, i32)))]>; + // ST(0) = ST(0) / [mem32int] +def FpIDIVR16m64: FpI<(ops RFP64:$dst, RFP64:$src1, i16mem:$src2), OneArgFPRW, + [(set RFP64:$dst, (fdiv (X86fild addr:$src2, i16), + RFP64:$src1))]>; + // ST(0) = [mem16int] / ST(0) +def FpIDIVR32m64: FpI<(ops RFP64:$dst, RFP64:$src1, i32mem:$src2), OneArgFPRW, + [(set RFP64:$dst, (fdiv (X86fild addr:$src2, i32), + RFP64:$src1))]>; + // ST(0) = [mem32int] / ST(0) def FIADD16m : FPI<0xDE, MRM0m, (ops i16mem:$src), "fiadd{s} $src">; def FIADD32m : FPI<0xDA, MRM0m, (ops i32mem:$src), "fiadd{l} $src">; @@ -396,53 +396,53 @@ let isTwoAddress = 1 in { def FpCMOVB32 : FpI<(ops RFP32:$dst, RFP32:$src1, RFP32:$src2), CondMovFP, [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, - X86_COND_B))]>; + X86_COND_B))]>; def FpCMOVBE32 : FpI<(ops RFP32:$dst, RFP32:$src1, RFP32:$src2), CondMovFP, [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, - X86_COND_BE))]>; + X86_COND_BE))]>; def FpCMOVE32 : FpI<(ops RFP32:$dst, RFP32:$src1, RFP32:$src2), CondMovFP, [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, - X86_COND_E))]>; + X86_COND_E))]>; def FpCMOVP32 : FpI<(ops RFP32:$dst, RFP32:$src1, RFP32:$src2), CondMovFP, [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, - X86_COND_P))]>; + X86_COND_P))]>; def FpCMOVNB32 : FpI<(ops RFP32:$dst, RFP32:$src1, RFP32:$src2), CondMovFP, [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, - X86_COND_AE))]>; + X86_COND_AE))]>; def FpCMOVNBE32: FpI<(ops RFP32:$dst, RFP32:$src1, RFP32:$src2), CondMovFP, [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, - X86_COND_A))]>; + X86_COND_A))]>; def FpCMOVNE32 : FpI<(ops RFP32:$dst, RFP32:$src1, RFP32:$src2), CondMovFP, [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, - X86_COND_NE))]>; + X86_COND_NE))]>; def FpCMOVNP32 : FpI<(ops RFP32:$dst, RFP32:$src1, RFP32:$src2), CondMovFP, [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, - X86_COND_NP))]>; + X86_COND_NP))]>; def FpCMOVB64 : FpI<(ops RFP64:$dst, RFP64:$src1, RFP64:$src2), CondMovFP, [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, - X86_COND_B))]>; + X86_COND_B))]>; def FpCMOVBE64 : FpI<(ops RFP64:$dst, RFP64:$src1, RFP64:$src2), CondMovFP, [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, - X86_COND_BE))]>; + X86_COND_BE))]>; def FpCMOVE64 : FpI<(ops RFP64:$dst, RFP64:$src1, RFP64:$src2), CondMovFP, [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, - X86_COND_E))]>; + X86_COND_E))]>; def FpCMOVP64 : FpI<(ops RFP64:$dst, RFP64:$src1, RFP64:$src2), CondMovFP, [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, - X86_COND_P))]>; + X86_COND_P))]>; def FpCMOVNB64 : FpI<(ops RFP64:$dst, RFP64:$src1, RFP64:$src2), CondMovFP, [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, - X86_COND_AE))]>; + X86_COND_AE))]>; def FpCMOVNBE64: FpI<(ops RFP64:$dst, RFP64:$src1, RFP64:$src2), CondMovFP, [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, - X86_COND_A))]>; + X86_COND_A))]>; def FpCMOVNE64 : FpI<(ops RFP64:$dst, RFP64:$src1, RFP64:$src2), CondMovFP, [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, - X86_COND_NE))]>; + X86_COND_NE))]>; def FpCMOVNP64 : FpI<(ops RFP64:$dst, RFP64:$src1, RFP64:$src2), CondMovFP, [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, - X86_COND_NP))]>; + X86_COND_NP))]>; } def FCMOVB : FPI<0xC0, AddRegFrm, (ops RST:$op), @@ -455,7 +455,7 @@ "fcmovu {$op, %st(0)|%ST(0), $op}">, DA; def FCMOVNB : FPI<0xC0, AddRegFrm, (ops RST:$op), "fcmovnb {$op, %st(0)|%ST(0), $op}">, DB; -def FCMOVNBE : FPI<0xD0, AddRegFrm, (ops RST:$op), +def FCMOVNBE: FPI<0xD0, AddRegFrm, (ops RST:$op), "fcmovnbe {$op, %st(0)|%ST(0), $op}">, DB; def FCMOVNE : FPI<0xC8, AddRegFrm, (ops RST:$op), "fcmovne {$op, %st(0)|%ST(0), $op}">, DB; @@ -463,29 +463,29 @@ "fcmovnu {$op, %st(0)|%ST(0), $op}">, DB; // Floating point loads & stores. -def FpLD32m : FpI<(ops RFP32:$dst, f32mem:$src), ZeroArgFP, - [(set RFP32:$dst, (loadf32 addr:$src))]>; -def FpLD64m : FpI<(ops RFP64:$dst, f64mem:$src), ZeroArgFP, - [(set RFP64:$dst, (loadf64 addr:$src))]>; -def FpILD16m32 : FpI<(ops RFP32:$dst, i16mem:$src), ZeroArgFP, - [(set RFP32:$dst, (X86fild addr:$src, i16))]>; -def FpILD32m32 : FpI<(ops RFP32:$dst, i32mem:$src), ZeroArgFP, - [(set RFP32:$dst, (X86fild addr:$src, i32))]>; -def FpILD64m32 : FpI<(ops RFP32:$dst, i64mem:$src), ZeroArgFP, - [(set RFP32:$dst, (X86fild addr:$src, i64))]>; -def FpILD16m64 : FpI<(ops RFP64:$dst, i16mem:$src), ZeroArgFP, - [(set RFP64:$dst, (X86fild addr:$src, i16))]>; -def FpILD32m64 : FpI<(ops RFP64:$dst, i32mem:$src), ZeroArgFP, - [(set RFP64:$dst, (X86fild addr:$src, i32))]>; -def FpILD64m64 : FpI<(ops RFP64:$dst, i64mem:$src), ZeroArgFP, - [(set RFP64:$dst, (X86fild addr:$src, i64))]>; +def FpLD32m : FpI<(ops RFP32:$dst, f32mem:$src), ZeroArgFP, + [(set RFP32:$dst, (loadf32 addr:$src))]>; +def FpLD64m : FpI<(ops RFP64:$dst, f64mem:$src), ZeroArgFP, + [(set RFP64:$dst, (loadf64 addr:$src))]>; +def FpILD16m32: FpI<(ops RFP32:$dst, i16mem:$src), ZeroArgFP, + [(set RFP32:$dst, (X86fild addr:$src, i16))]>; +def FpILD32m32: FpI<(ops RFP32:$dst, i32mem:$src), ZeroArgFP, + [(set RFP32:$dst, (X86fild addr:$src, i32))]>; +def FpILD64m32: FpI<(ops RFP32:$dst, i64mem:$src), ZeroArgFP, + [(set RFP32:$dst, (X86fild addr:$src, i64))]>; +def FpILD16m64: FpI<(ops RFP64:$dst, i16mem:$src), ZeroArgFP, + [(set RFP64:$dst, (X86fild addr:$src, i16))]>; +def FpILD32m64: FpI<(ops RFP64:$dst, i32mem:$src), ZeroArgFP, + [(set RFP64:$dst, (X86fild addr:$src, i32))]>; +def FpILD64m64: FpI<(ops RFP64:$dst, i64mem:$src), ZeroArgFP, + [(set RFP64:$dst, (X86fild addr:$src, i64))]>; def FpST32m : FpI<(ops f32mem:$op, RFP32:$src), OneArgFP, - [(store RFP32:$src, addr:$op)]>; + [(store RFP32:$src, addr:$op)]>; def FpST64m32 : FpI<(ops f32mem:$op, RFP64:$src), OneArgFP, - [(truncstoref32 RFP64:$src, addr:$op)]>; + [(truncstoref32 RFP64:$src, addr:$op)]>; def FpST64m : FpI<(ops f64mem:$op, RFP64:$src), OneArgFP, - [(store RFP64:$src, addr:$op)]>; + [(store RFP64:$src, addr:$op)]>; def FpSTP32m : FpI<(ops f32mem:$op, RFP32:$src), OneArgFP, []>; def FpSTP64m32 : FpI<(ops f32mem:$op, RFP64:$src), OneArgFP, []>; @@ -513,24 +513,24 @@ def FISTP64m : FPI<0xDF, MRM7m, (ops i64mem:$dst), "fistp{ll} $dst">; // FISTTP requires SSE3 even though it's a FPStack op. -def FpISTT16m32 : FpI_<(ops i16mem:$op, RFP32:$src), OneArgFP, - [(X86fp_to_i16mem RFP32:$src, addr:$op)]>, - Requires<[HasSSE3]>; +def FpISTT16m32 : FpI_<(ops i16mem:$op, RFP32:$src), OneArgFP, + [(X86fp_to_i16mem RFP32:$src, addr:$op)]>, + Requires<[HasSSE3]>; def FpISTT32m32 : FpI_<(ops i32mem:$op, RFP32:$src), OneArgFP, - [(X86fp_to_i32mem RFP32:$src, addr:$op)]>, - Requires<[HasSSE3]>; -def FpISTT64m32 : FpI_<(ops i64mem:$op, RFP32:$src), OneArgFP, - [(X86fp_to_i64mem RFP32:$src, addr:$op)]>, - Requires<[HasSSE3]>; -def FpISTT16m64 : FpI_<(ops i16mem:$op, RFP64:$src), OneArgFP, - [(X86fp_to_i16mem RFP64:$src, addr:$op)]>, - Requires<[HasSSE3]>; -def FpISTT32m64 : FpI_<(ops i32mem:$op, RFP64:$src), OneArgFP, - [(X86fp_to_i32mem RFP64:$src, addr:$op)]>, - Requires<[HasSSE3]>; -def FpISTT64m64 : FpI_<(ops i64mem:$op, RFP64:$src), OneArgFP, - [(X86fp_to_i64mem RFP64:$src, addr:$op)]>, - Requires<[HasSSE3]>; + [(X86fp_to_i32mem RFP32:$src, addr:$op)]>, + Requires<[HasSSE3]>; +def FpISTT64m32 : FpI_<(ops i64mem:$op, RFP32:$src), OneArgFP, + [(X86fp_to_i64mem RFP32:$src, addr:$op)]>, + Requires<[HasSSE3]>; +def FpISTT16m64 : FpI_<(ops i16mem:$op, RFP64:$src), OneArgFP, + [(X86fp_to_i16mem RFP64:$src, addr:$op)]>, + Requires<[HasSSE3]>; +def FpISTT32m64 : FpI_<(ops i32mem:$op, RFP64:$src), OneArgFP, + [(X86fp_to_i32mem RFP64:$src, addr:$op)]>, + Requires<[HasSSE3]>; +def FpISTT64m64 : FpI_<(ops i64mem:$op, RFP64:$src), OneArgFP, + [(X86fp_to_i64mem RFP64:$src, addr:$op)]>, + Requires<[HasSSE3]>; def FISTTP16m : FPI<0xDF, MRM1m, (ops i16mem:$dst), "fisttp{s} $dst">; def FISTTP32m : FPI<0xDB, MRM1m, (ops i32mem:$dst), "fisttp{l} $dst">; @@ -559,31 +559,31 @@ // Floating point compares. -def FpUCOMr32 : FpI<(ops RFP32:$lhs, RFP32:$rhs), CompareFP, - []>; // FPSW = cmp ST(0) with ST(i) -def FpUCOMIr32 : FpI<(ops RFP32:$lhs, RFP32:$rhs), CompareFP, - [(X86cmp RFP32:$lhs, RFP32:$rhs)]>; // CC = cmp ST(0) with ST(i) -def FpUCOMr64 : FpI<(ops RFP64:$lhs, RFP64:$rhs), CompareFP, - []>; // FPSW = cmp ST(0) with ST(i) -def FpUCOMIr64 : FpI<(ops RFP64:$lhs, RFP64:$rhs), CompareFP, - [(X86cmp RFP64:$lhs, RFP64:$rhs)]>; // CC = cmp ST(0) with ST(i) +def FpUCOMr32 : FpI<(ops RFP32:$lhs, RFP32:$rhs), CompareFP, + []>; // FPSW = cmp ST(0) with ST(i) +def FpUCOMIr32: FpI<(ops RFP32:$lhs, RFP32:$rhs), CompareFP, + [(X86cmp RFP32:$lhs, RFP32:$rhs)]>; // CC = cmp ST(0) with ST(i) +def FpUCOMr64 : FpI<(ops RFP64:$lhs, RFP64:$rhs), CompareFP, + []>; // FPSW = cmp ST(0) with ST(i) +def FpUCOMIr64: FpI<(ops RFP64:$lhs, RFP64:$rhs), CompareFP, + [(X86cmp RFP64:$lhs, RFP64:$rhs)]>; // CC = cmp ST(0) with ST(i) def FUCOMr : FPI<0xE0, AddRegFrm, // FPSW = cmp ST(0) with ST(i) (ops RST:$reg), "fucom $reg">, DD, Imp<[ST0],[]>; def FUCOMPr : FPI<0xE8, AddRegFrm, // FPSW = cmp ST(0) with ST(i), pop - (ops RST:$reg), - "fucomp $reg">, DD, Imp<[ST0],[]>; + (ops RST:$reg), + "fucomp $reg">, DD, Imp<[ST0],[]>; def FUCOMPPr : FPI<0xE9, RawFrm, // cmp ST(0) with ST(1), pop, pop - (ops), - "fucompp">, DA, Imp<[ST0],[]>; + (ops), + "fucompp">, DA, Imp<[ST0],[]>; -def FUCOMIr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i) - (ops RST:$reg), - "fucomi {$reg, %st(0)|%ST(0), $reg}">, DB, Imp<[ST0],[]>; -def FUCOMIPr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop - (ops RST:$reg), - "fucomip {$reg, %st(0)|%ST(0), $reg}">, DF, Imp<[ST0],[]>; +def FUCOMIr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i) + (ops RST:$reg), + "fucomi {$reg, %st(0)|%ST(0), $reg}">, DB, Imp<[ST0],[]>; +def FUCOMIPr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop + (ops RST:$reg), + "fucomip {$reg, %st(0)|%ST(0), $reg}">, DF, Imp<[ST0],[]>; // Floating point flag ops. def FNSTSW8r : I<0xE0, RawFrm, // AX = fp flags From asl at math.spbu.ru Tue Jul 3 12:16:46 2007 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Tue, 03 Jul 2007 17:16:46 -0000 Subject: [llvm-commits] [llvm] r37854 - in /llvm/trunk: autoconf/configure.ac configure Message-ID: <200707031716.l63HGlAf016819@zion.cs.uiuc.edu> Author: asl Date: Tue Jul 3 12:16:46 2007 New Revision: 37854 URL: http://llvm.org/viewvc/llvm-project?rev=37854&view=rev Log: Revert last change until issue reported by Owen, won't be fixed. Modified: llvm/trunk/autoconf/configure.ac llvm/trunk/configure Modified: llvm/trunk/autoconf/configure.ac URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/configure.ac?rev=37854&r1=37853&r2=37854&view=diff ============================================================================== --- llvm/trunk/autoconf/configure.ac (original) +++ llvm/trunk/autoconf/configure.ac Tue Jul 3 12:16:46 2007 @@ -70,7 +70,7 @@ sample) AC_CONFIG_SUBDIRS([projects/sample]) ;; privbracket) AC_CONFIG_SUBDIRS([projects/privbracket]) ;; llvm-stacker) AC_CONFIG_SUBDIRS([projects/llvm-stacker]) ;; - test-suite) AC_CONFIG_SUBDIRS([projects/test-suite]) ;; + llvm-test) AC_CONFIG_SUBDIRS([projects/llvm-test]) ;; llvm-reopt) AC_CONFIG_SUBDIRS([projects/llvm-reopt]);; llvm-gcc) AC_CONFIG_SUBDIRS([projects/llvm-gcc]) ;; llvm-java) AC_CONFIG_SUBDIRS([projects/llvm-java]) ;; Modified: llvm/trunk/configure URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/configure?rev=37854&r1=37853&r2=37854&view=diff ============================================================================== --- llvm/trunk/configure (original) +++ llvm/trunk/configure Tue Jul 3 12:16:46 2007 @@ -944,7 +944,7 @@ ac_subdirs_all='projects/sample projects/privbracket projects/llvm-stacker -projects/test-suite +projects/llvm-test projects/llvm-reopt projects/llvm-gcc projects/llvm-java @@ -2074,7 +2074,7 @@ ;; llvm-stacker) subdirs="$subdirs projects/llvm-stacker" ;; - test-suite) subdirs="$subdirs projects/test-suite" + llvm-test) subdirs="$subdirs projects/llvm-test" ;; llvm-reopt) subdirs="$subdirs projects/llvm-reopt" ;; From lattner at apple.com Tue Jul 3 12:27:30 2007 From: lattner at apple.com (Tanya Lattner) Date: Tue, 3 Jul 2007 10:27:30 -0700 Subject: [llvm-commits] [llvm] r37852 - in /llvm/trunk: autoconf/configure.ac configure In-Reply-To: <200707031701.l63H1xKa016388@zion.cs.uiuc.edu> References: <200707031701.l63H1xKa016388@zion.cs.uiuc.edu> Message-ID: <681F705E-1249-4935-8587-B77393837D92@apple.com> This will most likely break the nightly tester. -Tanya On Jul 3, 2007, at 10:01 AM, Anton Korobeynikov wrote: > Author: asl > Date: Tue Jul 3 12:01:58 2007 > New Revision: 37852 > > URL: http://llvm.org/viewvc/llvm-project?rev=37852&view=rev > Log: > Rename llvm-test => test-suite. By Dave Greene. > > Modified: > llvm/trunk/autoconf/configure.ac > llvm/trunk/configure > > Modified: llvm/trunk/autoconf/configure.ac > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/ > configure.ac?rev=37852&r1=37851&r2=37852&view=diff > ====================================================================== > ======== > > --- llvm/trunk/autoconf/configure.ac (original) > +++ llvm/trunk/autoconf/configure.ac Tue Jul 3 12:01:58 2007 > @@ -70,7 +70,7 @@ > sample) AC_CONFIG_SUBDIRS([projects/sample]) ;; > privbracket) AC_CONFIG_SUBDIRS([projects/privbracket]) ;; > llvm-stacker) AC_CONFIG_SUBDIRS([projects/llvm-stacker]) ;; > - llvm-test) AC_CONFIG_SUBDIRS([projects/llvm-test]) ;; > + test-suite) AC_CONFIG_SUBDIRS([projects/test-suite]) ;; > llvm-reopt) AC_CONFIG_SUBDIRS([projects/llvm-reopt]);; > llvm-gcc) AC_CONFIG_SUBDIRS([projects/llvm-gcc]) ;; > llvm-java) AC_CONFIG_SUBDIRS([projects/llvm-java]) ;; > > Modified: llvm/trunk/configure > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/configure? > rev=37852&r1=37851&r2=37852&view=diff > ====================================================================== > ======== > > --- llvm/trunk/configure (original) > +++ llvm/trunk/configure Tue Jul 3 12:01:58 2007 > @@ -944,7 +944,7 @@ > ac_subdirs_all='projects/sample > projects/privbracket > projects/llvm-stacker > -projects/llvm-test > +projects/test-suite > projects/llvm-reopt > projects/llvm-gcc > projects/llvm-java > @@ -2074,7 +2074,7 @@ > ;; > llvm-stacker) subdirs="$subdirs projects/llvm-stacker" > ;; > - llvm-test) subdirs="$subdirs projects/llvm-test" > + test-suite) subdirs="$subdirs projects/test-suite" > ;; > llvm-reopt) subdirs="$subdirs projects/llvm-reopt" > ;; > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From raulherbster at gmail.com Tue Jul 3 12:35:54 2007 From: raulherbster at gmail.com (Raul Fernandes Herbster) Date: Tue, 3 Jul 2007 14:35:54 -0300 Subject: [llvm-commits] Patch: ARM JIT support Message-ID: <6fbb4ff20707031035v79af3e4bh3900dfa39e972ba0@mail.gmail.com> I received very important comments from Evan and fixed some problems. Thanks for any suggestion. []'s -- Raul Fernandes Herbster Embedded and Pervasive Computing Laboratory - embedded.dee.ufcg.edu.br Electrical Engineering Department - DEE - www.ee.ufcg.edu.br Electrical Engineering and Informatics Center - CEEI Federal University of Campina Grande - UFCG - www.ufcg.edu.br Caixa Postal 10105 58109-970 Campina Grande - PB - Brasil -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20070703/878d42ea/attachment.html -------------- next part -------------- A non-text attachment was scrubbed... Name: patch Type: application/octet-stream Size: 5519 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20070703/878d42ea/attachment.obj -------------- next part -------------- A non-text attachment was scrubbed... Name: arm_jit.tar.gz Type: application/x-gzip Size: 3490 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20070703/878d42ea/attachment.gz From tonic at nondot.org Tue Jul 3 13:11:20 2007 From: tonic at nondot.org (Tanya Lattner) Date: Tue, 03 Jul 2007 18:11:20 -0000 Subject: [llvm-commits] [llvm] r37855 - /llvm/trunk/docs/Makefile Message-ID: <200707031811.l63IBKcp018386@zion.cs.uiuc.edu> Author: tbrethou Date: Tue Jul 3 13:11:20 2007 New Revision: 37855 URL: http://llvm.org/viewvc/llvm-project?rev=37855&view=rev Log: We really should not have this version number in SO many makefiles. This should also probably change to svn instead of cvs, but leaving it for now. Modified: llvm/trunk/docs/Makefile Modified: llvm/trunk/docs/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/Makefile?rev=37855&r1=37854&r2=37855&view=diff ============================================================================== --- llvm/trunk/docs/Makefile (original) +++ llvm/trunk/docs/Makefile Tue Jul 3 13:11:20 2007 @@ -14,7 +14,7 @@ PROJ_OBJ_DIR = . DOXYGEN = doxygen # Extract version number from the AC_INT line in configure.ac -# AC_INIT([[llvm]],[[2.0cvs]],[llvmbugs at cs.uiuc.edu]) +# AC_INIT([[llvm]],[[2.1cvs]],[llvmbugs at cs.uiuc.edu]) PACKAGE_VERSION = $(shell grep AC_INIT ../autoconf/configure.ac | sed -e 's/[^,]*,[[][[]//' -e 's/]],.*//') $(warning VERSION=$(VERSION)) From isanbard at gmail.com Tue Jul 3 13:12:19 2007 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 3 Jul 2007 11:12:19 -0700 Subject: [llvm-commits] Commit Message Problems Message-ID: <16e5fdf90707031112t4edaefd7t12186ed12c4bb600@mail.gmail.com> On 7/3/07, Dan Gohman wrote: > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=37851&r1=37850&r2=37851&view=diff > ============================================================================== > Could there be an extra newline between the URL and the ==== border? My mail client makes it part of the URL. (Yes, I know it shouldn't do that, but still...) Thanks! -bw From asl at math.spbu.ru Tue Jul 3 13:20:40 2007 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Tue, 03 Jul 2007 22:20:40 +0400 Subject: [llvm-commits] Commit Message Problems In-Reply-To: <16e5fdf90707031112t4edaefd7t12186ed12c4bb600.SS587SS@mail.gmail.com> References: <16e5fdf90707031112t4edaefd7t12186ed12c4bb600.SS587SS@mail.gmail.com> Message-ID: <1183486840.6891.93.camel@asl.dorms.spbu.ru> Hello, Bill > On 7/3/07, Dan Gohman wrote: > > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=37851&r1=37850&r2=37851&view=diff > > ============================================================================== > > > Could there be an extra newline between the URL and the ==== border? > My mail client makes it part of the URL. (Yes, I know it shouldn't do > that, but still...) We know about this issue. Even more, I've prepared patch for it. It should be just installed on Zion. -- With best regards, Anton Korobeynikov. Faculty of Mathematics & Mechanics, Saint Petersburg State University. From isanbard at gmail.com Tue Jul 3 13:24:28 2007 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 3 Jul 2007 11:24:28 -0700 Subject: [llvm-commits] Commit Message Problems In-Reply-To: <1183486840.6891.93.camel@asl.dorms.spbu.ru> References: <16e5fdf90707031112t4edaefd7t12186ed12c4bb600.SS587SS@mail.gmail.com> <1183486840.6891.93.camel@asl.dorms.spbu.ru> Message-ID: <16e5fdf90707031124p39ff036bj6baef9dbcd13ee26@mail.gmail.com> On 7/3/07, Anton Korobeynikov wrote: > Hello, Bill > > > On 7/3/07, Dan Gohman wrote: > > > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=37851&r1=37850&r2=37851&view=diff > > > ============================================================================== > > > > > Could there be an extra newline between the URL and the ==== border? > > My mail client makes it part of the URL. (Yes, I know it shouldn't do > > that, but still...) > We know about this issue. Even more, I've prepared patch for it. It > should be just installed on Zion. > Coolness! Thanks :-) -bw From clattner at apple.com Tue Jul 3 13:32:37 2007 From: clattner at apple.com (Chris Lattner) Date: Tue, 3 Jul 2007 11:32:37 -0700 Subject: [llvm-commits] Commit Message Problems In-Reply-To: <1183486840.6891.93.camel@asl.dorms.spbu.ru> References: <16e5fdf90707031112t4edaefd7t12186ed12c4bb600.SS587SS@mail.gmail.com> <1183486840.6891.93.camel@asl.dorms.spbu.ru> Message-ID: On Jul 3, 2007, at 11:20 AM, Anton Korobeynikov wrote: > Hello, Bill > >> On 7/3/07, Dan Gohman wrote: >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ >>> SelectionDAG/DAGCombiner.cpp?rev=37851&r1=37850&r2=37851&view=diff >>> ==================================================================== >>> ========== >>> >> Could there be an extra newline between the URL and the ==== border? >> My mail client makes it part of the URL. (Yes, I know it shouldn't do >> that, but still...) > We know about this issue. Even more, I've prepared patch for it. It > should be just installed on Zion. I installed it on zion, it still doesn't work. Perhaps I did it wrong? -Chris From resistor at mac.com Tue Jul 3 13:37:09 2007 From: resistor at mac.com (Owen Anderson) Date: Tue, 03 Jul 2007 18:37:09 -0000 Subject: [llvm-commits] [llvm] r37856 - in /llvm/trunk: lib/Transforms/Scalar/GVNPRE.cpp test/Transforms/GVNPRE/cast.ll Message-ID: <200707031837.l63Ib9A3019244@zion.cs.uiuc.edu> Author: resistor Date: Tue Jul 3 13:37:08 2007 New Revision: 37856 URL: http://llvm.org/viewvc/llvm-project?rev=37856&view=rev Log: Add support for performing GVNPRE on cast instructions, and add a testcase for this. Added: llvm/trunk/test/Transforms/GVNPRE/cast.ll Modified: llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp Modified: llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp?rev=37856&r1=37855&r2=37856&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp Tue Jul 3 13:37:08 2007 @@ -629,8 +629,41 @@ if (V == 0) return 0; + // Unary Operations + if (isa(V)) { + User* U = cast(V); + + Value* newOp1 = 0; + if (isa(U->getOperand(0))) + newOp1 = phi_translate(U->getOperand(0), pred, succ); + else + newOp1 = U->getOperand(0); + + if (newOp1 == 0) + return 0; + + if (newOp1 != U->getOperand(0)) { + Instruction* newVal = 0; + if (CastInst* C = dyn_cast(U)) + newVal = CastInst::create(C->getOpcode(), + newOp1, C->getType(), + C->getName()+".expr"); + + uint32_t v = VN.lookup_or_add(newVal); + + Value* leader = find_leader(availableOut[pred], v); + if (leader == 0) { + createdExpressions.push_back(newVal); + return newVal; + } else { + VN.erase(newVal); + delete newVal; + return leader; + } + } + // Binary Operations - if (isa(V) || isa(V) || + } if (isa(V) || isa(V) || isa(V)) { User* U = cast(V); @@ -783,8 +816,22 @@ for (unsigned i = 0; i < worklist.size(); ++i) { Value* v = worklist[i]; + // Handle unary ops + if (isa(v)) { + User* U = cast(v); + + bool lhsValid = !isa(U->getOperand(0)); + lhsValid |= presentInSet.test(VN.lookup(U->getOperand(0))); + if (lhsValid) + lhsValid = !dependsOnInvoke(U->getOperand(0)); + + if (!lhsValid) { + set.erase(U); + presentInSet.flip(VN.lookup(U)); + } + // Handle binary ops - if (isa(v) || isa(v) || + } else if (isa(v) || isa(v) || isa(v)) { User* U = cast(v); @@ -843,9 +890,23 @@ while (!stack.empty()) { Value* e = stack.back(); - + + // Handle unary ops + if (isa(e)) { + User* U = cast(e); + Value* l = find_leader(set, VN.lookup(U->getOperand(0))); + + if (l != 0 && isa(l) && + visited.count(l) == 0) + stack.push_back(l); + else { + vec.push_back(e); + visited.insert(e); + stack.pop_back(); + } + // Handle binary ops - if (isa(e) || isa(e) || + } else if (isa(e) || isa(e) || isa(e)) { User* U = cast(e); Value* l = find_leader(set, VN.lookup(U->getOperand(0))); @@ -935,7 +996,8 @@ if (isa(BI) || isa(BI) || isa(BI) || isa(BI) || - isa(BI) || isa(BI)) { + isa(BI) || isa(BI) || + isa(BI)) { Value *leader = find_leader(availableOut[BB], VN.lookup(BI)); if (leader != 0) @@ -990,7 +1052,27 @@ availNumbers.resize(VN.size()); currPhis.insert(p); + + // Handle unary ops + } else if (isa(I)) { + User* U = cast(I); + Value* leftValue = U->getOperand(0); + + unsigned num = VN.lookup_or_add(U); + expNumbers.resize(VN.size()); + availNumbers.resize(VN.size()); + + if (isa(leftValue)) + if (!expNumbers.test(VN.lookup(leftValue))) { + currExps.insert(leftValue); + expNumbers.set(VN.lookup(leftValue)); + } + if (!expNumbers.test(VN.lookup(U))) { + currExps.insert(U); + expNumbers.set(num); + } + // Handle binary ops } else if (isa(I) || isa(I) || isa(I)) { @@ -1266,21 +1348,31 @@ isa(U->getOperand(0)) || isa(U->getOperand(0)) || isa(U->getOperand(0)) || - isa(U->getOperand(0))) + isa(U->getOperand(0)) || + isa(U->getOperand(0))) s1 = find_leader(availableOut[*PI], VN.lookup(U->getOperand(0))); else s1 = U->getOperand(0); Value* s2 = 0; - if (isa(U->getOperand(1)) || - isa(U->getOperand(1)) || - isa(U->getOperand(1)) || - isa(U->getOperand(1)) || - isa(U->getOperand(1)) || - isa(U->getOperand(1))) - s2 = find_leader(availableOut[*PI], VN.lookup(U->getOperand(1))); - else - s2 = U->getOperand(1); + + if (isa(U) || + isa(U) || + isa(U) || + isa(U) || + isa(U) || + isa(U)) + if (isa(U->getOperand(1)) || + isa(U->getOperand(1)) || + isa(U->getOperand(1)) || + isa(U->getOperand(1)) || + isa(U->getOperand(1)) || + isa(U->getOperand(1)) || + isa(U->getOperand(1))) { + s2 = find_leader(availableOut[*PI], VN.lookup(U->getOperand(1))); + } else { + s2 = U->getOperand(1); + } // Ternary Operators Value* s3 = 0; @@ -1292,10 +1384,12 @@ isa(U->getOperand(2)) || isa(U->getOperand(2)) || isa(U->getOperand(2)) || - isa(U->getOperand(2))) + isa(U->getOperand(2)) || + isa(U->getOperand(2))) { s3 = find_leader(availableOut[*PI], VN.lookup(U->getOperand(2))); - else + } else { s3 = U->getOperand(2); + } Value* newVal = 0; if (BinaryOperator* BO = dyn_cast(U)) @@ -1319,6 +1413,10 @@ newVal = new SelectInst(S->getCondition(), S->getTrueValue(), S->getFalseValue(), S->getName()+".gvnpre", (*PI)->getTerminator()); + else if (CastInst* C = dyn_cast(U)) + newVal = CastInst::create(C->getOpcode(), s1, C->getType(), + C->getName()+".gvnpre", + (*PI)->getTerminator()); VN.add(newVal, VN.lookup(U)); @@ -1365,7 +1463,7 @@ if (isa(e) || isa(e) || isa(e) || isa(e) || - isa(e) || isa(e)) { + isa(e) || isa(e) || isa(e)) { if (find_leader(availableOut[D->getIDom()->getBlock()], VN.lookup(e)) != 0) continue; Added: llvm/trunk/test/Transforms/GVNPRE/cast.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/GVNPRE/cast.ll?rev=37856&view=auto ============================================================================== --- llvm/trunk/test/Transforms/GVNPRE/cast.ll (added) +++ llvm/trunk/test/Transforms/GVNPRE/cast.ll Tue Jul 3 13:37:08 2007 @@ -0,0 +1,17 @@ +; RUN: llvm-as < %s | opt -gvnpre | llvm-dis | grep b.gvnpre + +define i32 @extract() { +entry: ; preds = %cond_false, %entry + br i1 true, label %cond_true, label %cond_false + +cond_true: + br label %end + +cond_false: + %a = sext i16 0 to i32 + br label %end + +end: + %b = sext i16 0 to i32 + ret i32 %b +} From resistor at mac.com Tue Jul 3 14:01:42 2007 From: resistor at mac.com (Owen Anderson) Date: Tue, 03 Jul 2007 19:01:42 -0000 Subject: [llvm-commits] [llvm] r37857 - /llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp Message-ID: <200707031901.l63J1gTf019961@zion.cs.uiuc.edu> Author: resistor Date: Tue Jul 3 14:01:42 2007 New Revision: 37857 URL: http://llvm.org/viewvc/llvm-project?rev=37857&view=rev Log: Make the unary operator case a bit faster, since casts are the only kind of unary operation. Modified: llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp Modified: llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp?rev=37857&r1=37856&r2=37857&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp Tue Jul 3 14:01:42 2007 @@ -630,9 +630,7 @@ return 0; // Unary Operations - if (isa(V)) { - User* U = cast(V); - + if (CastInst* U = dyn_cast(V)) { Value* newOp1 = 0; if (isa(U->getOperand(0))) newOp1 = phi_translate(U->getOperand(0), pred, succ); @@ -817,9 +815,7 @@ Value* v = worklist[i]; // Handle unary ops - if (isa(v)) { - User* U = cast(v); - + if (CastInst* U = dyn_cast(v)) { bool lhsValid = !isa(U->getOperand(0)); lhsValid |= presentInSet.test(VN.lookup(U->getOperand(0))); if (lhsValid) @@ -892,8 +888,7 @@ Value* e = stack.back(); // Handle unary ops - if (isa(e)) { - User* U = cast(e); + if (CastInst* U = dyn_cast(e)) { Value* l = find_leader(set, VN.lookup(U->getOperand(0))); if (l != 0 && isa(l) && @@ -1054,8 +1049,7 @@ currPhis.insert(p); // Handle unary ops - } else if (isa(I)) { - User* U = cast(I); + } else if (CastInst* U = dyn_cast(I)) { Value* leftValue = U->getOperand(0); unsigned num = VN.lookup_or_add(U); From greened at obbligato.org Tue Jul 3 15:11:10 2007 From: greened at obbligato.org (David A. Greene) Date: Tue, 3 Jul 2007 15:11:10 -0500 Subject: [llvm-commits] [llvm] r37854 - in /llvm/trunk: autoconf/configure.ac configure In-Reply-To: <200707031716.l63HGlAf016819@zion.cs.uiuc.edu> References: <200707031716.l63HGlAf016819@zion.cs.uiuc.edu> Message-ID: <200707031511.10946.greened@obbligato.org> On Tuesday 03 July 2007 12:16, Anton Korobeynikov wrote: > Author: asl > Date: Tue Jul 3 12:16:46 2007 > New Revision: 37854 > > URL: http://llvm.org/viewvc/llvm-project?rev=37854&view=rev > Log: > Revert last change until issue reported by Owen, won't be fixed. > - test-suite) AC_CONFIG_SUBDIRS([projects/test-suite]) ;; > + llvm-test) AC_CONFIG_SUBDIRS([projects/llvm-test]) ;; I believe the right thing to do here is fix the web page. -Dave From clattner at apple.com Tue Jul 3 15:31:24 2007 From: clattner at apple.com (Chris Lattner) Date: Tue, 3 Jul 2007 13:31:24 -0700 Subject: [llvm-commits] [llvm] r37854 - in /llvm/trunk: autoconf/configure.ac configure In-Reply-To: <200707031511.10946.greened@obbligato.org> References: <200707031716.l63HGlAf016819@zion.cs.uiuc.edu> <200707031511.10946.greened@obbligato.org> Message-ID: On Jul 3, 2007, at 1:11 PM, David A. Greene wrote: > On Tuesday 03 July 2007 12:16, Anton Korobeynikov wrote: >> Author: asl >> Date: Tue Jul 3 12:16:46 2007 >> New Revision: 37854 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=37854&view=rev >> Log: >> Revert last change until issue reported by Owen, won't be fixed. > >> - test-suite) AC_CONFIG_SUBDIRS([projects/test-suite]) ;; >> + llvm-test) AC_CONFIG_SUBDIRS([projects/llvm-test]) ;; > > I believe the right thing to do here is fix the web page. alternatively, just add both to the configure script. -Chris From djg at cray.com Tue Jul 3 16:13:20 2007 From: djg at cray.com (Dan Gohman) Date: Tue, 3 Jul 2007 16:13:20 -0500 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp TargetLowering.cpp Message-ID: <20070703211320.GF5693@village.us.cray.com> >> We overload ISD::FADD and quite a lot of others. Why not >> ISD::ConstantFP too? > > Fair enough, after pondering on it, I agree with you. The proposed > semantics are that a ConstantFP (and also a normal Constant?) produce > the splatted immediate value? Constant sounds good too. And UNDEF, for that matter. And yes, that's the semantics I mean. > If so, this sounds fine. This should also reduce codegen memory > usage for many common cases, a very nice bonus :) :) > Please add a dag combine xform from build_vector [c,c,c,c] -> > constantfp and friends. I sketched out some of the code for this. One question that's come up so far is whether if the vector has some undef elements but all the non-undef elements are equal it should still be folded. My initial preference is to still fold it, since that lets things like isBuildVectorAllZeros become trivial to unnecessary, but it is a pessimization in some obscure cases. Dan -- Dan Gohman, Cray Inc. From djg at cray.com Tue Jul 3 16:29:50 2007 From: djg at cray.com (Dan Gohman) Date: Tue, 3 Jul 2007 16:29:50 -0500 Subject: [llvm-commits] [llvm] r37851 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp In-Reply-To: <200707031643.14426.baldrick@free.fr> References: <200707031403.l63E3woZ011704@zion.cs.uiuc.edu> <200707031643.14426.baldrick@free.fr> Message-ID: <20070703212950.GG5693@village.us.cray.com> On Tue, Jul 03, 2007 at 04:43:14PM +0200, Duncan Sands wrote: > Hi Dan, > > > + // fold (add x, undef) -> undef > > + if (N1.getOpcode() == ISD::UNDEF) > > + return N1; > > what if N0 is undef and not N1? I had thought they'd be canonicalized, but I missed that the dagcombiner sometimes has non-canonicalized nodes. I'll fix these. > > - // If either operand is undef, the result is undef > > - if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) > > - return DAG.getNode(ISD::UNDEF, VT); > > - > > Did you move this earlier to make it more efficient, or for another > reason? I was looking at the instcombine code, where undefs tend to be handled toward the beginning. I wasn't trying to micro-optimize dagcombine :). > > - // If either operand is undef, the result is undef > > + // If either operand of a sub is undef, the result is undef > > if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) > > return DAG.getNode(ISD::UNDEF, VT); > > If it was more efficient doing this earlier for add, presumably the > same is true for subtraction. I guess I can make this more consistent with instcombine too. > > + // fold (mul x, undef) -> 0 > > + if (N1.getOpcode() == ISD::UNDEF) > > + return DAG.getConstant(0, VT); > > Yes, this seems better :) Again, is the undef guaranteed to be > in N1 and not N0? Same as add, above. > > + // X / undef -> undef > > + if (N1.getOpcode() == ISD::UNDEF) > > + return N1; > > Here you use that X / 0 is undefined in the usual sense, > and can take on any value. Is it undefined? Also, wouldn't > it be better to do this before the N0 one, in case you have > undef/undef ? > > Same comments for udiv, srem and urem. The primary aim of this mod was to get dagcombine to stop being over-aggressive. I agree that there does seem to be more room for optimization, in both instcombine and dagcombine. > > @@ -1390,10 +1400,6 @@ > > return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); > > } > > > > - // If either operand is undef, the result is undef > > - if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) > > - return DAG.getNode(ISD::UNDEF, VT); > > - > > return SDOperand(); > > } > > (SimplifyBinOpWithSameOpcodeHands) > > In this case both N0 and N1 must be undef (since by definition they > have the same opcode here), so returning undef seems ok here. That > said, the original "if" was kind of silly since if one opcode is undef > then so is the other. This logic was removed in favor of having specific logic in visitAND, visitOR, and visitXOR. The new code has the same problem as visitADD, discussed above, so I'll fix that, but then it'll cover the UNDEF op UNDEF cases as well. > > + // fold (or x, undef) -> -1 > > + if (N1.getOpcode() == ISD::UNDEF) > > + return DAG.getConstant(-1, VT); > > Is this the right way to get an all-bits-one value? I guess DAG.getConstant(~0ULL, VT) is the way its written elsewhere. And I have to fix it for vectors. I'll work on it. > > @@ -3040,10 +3051,6 @@ > > if (isNegatibleForFree(N1)) > > return DAG.getNode(ISD::FADD, VT, N0, GetNegatedExpression(N1, DAG)); > > > > - // If either operand is undef, the result is undef > > - if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) > > - return DAG.getNode(ISD::UNDEF, VT); > > - > > return SDOperand(); > > } > > Why the difference between fadd and fsub? If you are worried about NaNs > etc, at worst you can always, I suppose, turn x fsub undef into x. > Likewise for the other floating point ops. Did you mean the difference between integer add and fadd? I just decided that folding floating-point undef isn't very valuable to me, and the easiest way to fix the code was to revert the change. Looking at it a little more, I think the instcombine folds are actually wrong here. For example, it does X + undef -> undef, but that's wrong if X is a NaN. Dan -- Dan Gohman, Cray Inc. From resistor at mac.com Tue Jul 3 16:36:47 2007 From: resistor at mac.com (Owen Anderson) Date: Tue, 03 Jul 2007 21:36:47 -0000 Subject: [llvm-commits] [llvm] r37858 - in /llvm/trunk/examples: BFtoLLVM/ Makefile Message-ID: <200707032136.l63LalTV024067@zion.cs.uiuc.edu> Author: resistor Date: Tue Jul 3 16:36:47 2007 New Revision: 37858 URL: http://llvm.org/viewvc/llvm-project?rev=37858&view=rev Log: Remove BFtoLLVM. It was old, and a poor example because it didn't use best practices for making a LLVM frontend in C++. Maybe someday it will be rewritten.. Removed: llvm/trunk/examples/BFtoLLVM/ Modified: llvm/trunk/examples/Makefile Modified: llvm/trunk/examples/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/Makefile?rev=37858&r1=37857&r2=37858&view=diff ============================================================================== --- llvm/trunk/examples/Makefile (original) +++ llvm/trunk/examples/Makefile Tue Jul 3 16:36:47 2007 @@ -10,7 +10,7 @@ include $(LEVEL)/Makefile.config -PARALLEL_DIRS:= Fibonacci HowToUseJIT ModuleMaker BFtoLLVM +PARALLEL_DIRS:= Fibonacci HowToUseJIT ModuleMaker ifeq ($(HAVE_PTHREAD),1) PARALLEL_DIRS += ParallelJIT From clattner at apple.com Tue Jul 3 16:42:01 2007 From: clattner at apple.com (Chris Lattner) Date: Tue, 3 Jul 2007 14:42:01 -0700 Subject: [llvm-commits] [llvm] r37851 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp In-Reply-To: <20070703212950.GG5693@village.us.cray.com> References: <200707031403.l63E3woZ011704@zion.cs.uiuc.edu> <200707031643.14426.baldrick@free.fr> <20070703212950.GG5693@village.us.cray.com> Message-ID: <13196C7C-515E-4B33-BF85-68D843EBD0BA@apple.com> >>> + // fold (or x, undef) -> -1 >>> + if (N1.getOpcode() == ISD::UNDEF) >>> + return DAG.getConstant(-1, VT); >> >> Is this the right way to get an all-bits-one value? > > I guess DAG.getConstant(~0ULL, VT) is the way its written > elsewhere. And I > have to fix it for vectors. I'll work on it. Either way works. "-1" is a signed integer that sign extends to uint64_t. ~0ULL is more explicit though. > Looking at it a little more, I think the instcombine folds are > actually > wrong here. For example, it does X + undef -> undef, but that's > wrong if > X is a NaN. Ah, good point. -Chris From asl at math.spbu.ru Tue Jul 3 16:57:50 2007 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Tue, 03 Jul 2007 21:57:50 -0000 Subject: [llvm-commits] [llvm] r37859 - /llvm/trunk/utils/NLT.schema Message-ID: <200707032157.l63Lvo9m024974@zion.cs.uiuc.edu> Author: asl Date: Tue Jul 3 16:57:50 2007 New Revision: 37859 URL: http://llvm.org/viewvc/llvm-project?rev=37859&view=rev Log: Test modified svn mailer Modified: llvm/trunk/utils/NLT.schema Modified: llvm/trunk/utils/NLT.schema URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/NLT.schema?rev=37859&r1=37858&r2=37859&view=diff ============================================================================== --- llvm/trunk/utils/NLT.schema (original) +++ llvm/trunk/utils/NLT.schema Tue Jul 3 16:57:50 2007 @@ -5,3 +5,4 @@ `VALUE` double NOT NULL default '0', KEY `name_index` (`NAME`) ) ENGINE=MyISAM DEFAULT CHARSET=latin1 + From clattner at apple.com Tue Jul 3 17:07:26 2007 From: clattner at apple.com (Chris Lattner) Date: Tue, 3 Jul 2007 15:07:26 -0700 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp TargetLowering.cpp In-Reply-To: <20070703211320.GF5693@village.us.cray.com> References: <20070703211320.GF5693@village.us.cray.com> Message-ID: <6E7636D5-88D1-45E1-9017-86553FBF974B@apple.com> On Jul 3, 2007, at 2:13 PM, Dan Gohman wrote: >>> We overload ISD::FADD and quite a lot of others. Why not >>> ISD::ConstantFP too? >> >> Fair enough, after pondering on it, I agree with you. The proposed >> semantics are that a ConstantFP (and also a normal Constant?) produce >> the splatted immediate value? > > Constant sounds good too. And UNDEF, for that matter. And yes, > that's the > semantics I mean. Ok, makes sense. I think we already use UNDEF for vectors. >> Please add a dag combine xform from build_vector [c,c,c,c] -> >> constantfp and friends. > > I sketched out some of the code for this. One question that's come > up so far is > whether if the vector has some undef elements but all the non-undef > elements > are equal it should still be folded. My initial preference is to > still fold it, > since that lets things like isBuildVectorAllZeros become trivial to > unnecessary, > but it is a pessimization in some obscure cases. I'm not sure about it. One specific issue is with shuffle masks, which we want to retain the undef element values for. I don't think there is a good way to retain shuffle masks but not other build vectors, so we probably need to keep the individual undef elements in it. isBuildVectorAllZeros and friends are another issue. To me there are actually two issues that should be resolved at some point: 1. vector constant and shuffle mask matching code is crazily complex, particularly in the x86 backend. For vector constants, this is only slightly annoying. For vector shuffle masks, the selected shuffles are currently whatever is best for yonah, and it's not really possible to prefer different shuffles on different subtargets. We really want to add a layer of abstraction in the shuffle/constant matching code, which would make the undef handling stuff happen implicitly. Making a more declarative description of the various masks would make it much easier to maintain, understand, and debug. 2. the x86 backend specifically has a problem with the way it selects vector constants (I think this is in the readme). In particular, if you have a 4 x f32 and a 4 x i32 zero vector, you'll get two different pxor instructions, because they are of different type. There are two different ways to solve this problem: The easy answer is to do what the ppc backend does. It always selects zero (and -1) vectors to 4 x i32 IIRC, and then does a bitcast to the desired type if needed. This ensures that the constant vectors always get CSEd. The tricky part of this is to ensure that the 0/-1 vectors still get folded if you have operations (like ~) that require one of these as an operand. This ugliness is why we have "vnot" and "vnot_conv" and have to duplicate patterns. The better fix is to change the way the select phase produces code. In particular, the reason these two zero vectors don't get CSE'd after selection is because they have two different value types, and the autocse stuff doesn't "know" that the two VTs end up in the same register class. To solve this, it seems like we can add a new MVT type, where a certain range of MVTs (128-255?) correspond to register class ID's. At selection time, instead of giving the new nodes their old MVT's, they would get new MVT's that correspond to the regclass of the result (ok, we'd keep MVT::Other, MVT::Flag and maybe some others). This makes the scheduler slightly simpler (because it doesn't need to map MVT -> regclass) anymore, and opens up future possibilities. In particular, it lets us fix a long-standing class of issues where we can't have fp stack and SSE registers around at the same time, both with MVT::f32 or f64 type. The current scheduler can only map f32 to one register class (thus, it can't keep the distinction) but with this change the select pass can pick any regclass it wants. Anyway, this is a bit of a crazy tangent, but I think undef's in buildvector should probably stay :) -Chris From resistor at mac.com Tue Jul 3 17:50:57 2007 From: resistor at mac.com (Owen Anderson) Date: Tue, 03 Jul 2007 22:50:57 -0000 Subject: [llvm-commits] [llvm] r37860 - /llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp Message-ID: <200707032250.l63MovSU026731@zion.cs.uiuc.edu> Author: resistor Date: Tue Jul 3 17:50:56 2007 New Revision: 37860 URL: http://llvm.org/viewvc/llvm-project?rev=37860&view=rev Log: Add functionality to value number GEP instructions. This also provides the infrastructure that will be used for function calls. NOTE: This does not yet do any transformation of GEPs or function calls. Modified: llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp Modified: llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp?rev=37860&r1=37859&r2=37860&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp Tue Jul 3 17:50:56 2007 @@ -62,13 +62,14 @@ FCMPULT, FCMPULE, FCMPUNE, EXTRACT, INSERT, SHUFFLE, SELECT, TRUNC, ZEXT, SEXT, FPTOUI, FPTOSI, UITOFP, SITOFP, FPTRUNC, FPEXT, - PTRTOINT, INTTOPTR, BITCAST}; + PTRTOINT, INTTOPTR, BITCAST, GEP}; ExpressionOpcode opcode; const Type* type; uint32_t firstVN; uint32_t secondVN; uint32_t thirdVN; + std::vector varargs; bool operator< (const Expression& other) const { if (opcode < other.opcode) @@ -91,8 +92,20 @@ return true; else if (thirdVN > other.thirdVN) return false; - else + else { + if (varargs.size() < other.varargs.size()) + return true; + else if (varargs.size() > other.varargs.size()) + return false; + + for (size_t i = 0; i < varargs.size(); ++i) + if (varargs[i] < other.varargs[i]) + return true; + else if (varargs[i] > other.varargs[i]) + return false; + return false; + } } }; @@ -112,6 +125,7 @@ Expression create_expression(InsertElementInst* V); Expression create_expression(SelectInst* V); Expression create_expression(CastInst* C); + Expression create_expression(GetElementPtrInst* G); public: ValueTable() { nextValueNumber = 1; } uint32_t lookup_or_add(Value* V); @@ -354,6 +368,22 @@ return e; } +ValueTable::Expression ValueTable::create_expression(GetElementPtrInst* G) { + Expression e; + + e.firstVN = lookup_or_add(G->getPointerOperand()); + e.secondVN = 0; + e.thirdVN = 0; + e.type = G->getType(); + e.opcode = Expression::SELECT; + + for (GetElementPtrInst::op_iterator I = G->idx_begin(), E = G->idx_end(); + I != E; ++I) + e.varargs.push_back(lookup_or_add(*I)); + + return e; +} + //===----------------------------------------------------------------------===// // ValueTable External Functions //===----------------------------------------------------------------------===// From isanbard at gmail.com Tue Jul 3 18:04:11 2007 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 03 Jul 2007 23:04:11 -0000 Subject: [llvm-commits] [llvm] r37861 - /llvm/trunk/Makefile.config.in Message-ID: <200707032304.l63N4BWo027173@zion.cs.uiuc.edu> Author: void Date: Tue Jul 3 18:04:11 2007 New Revision: 37861 URL: http://llvm.org/viewvc/llvm-project?rev=37861&view=rev Log: Change the place where man pages are installed to ${prefix}/share/man1. This puts them in a more standardized place. Modified: llvm/trunk/Makefile.config.in Modified: llvm/trunk/Makefile.config.in URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.config.in?rev=37861&r1=37860&r2=37861&view=diff ============================================================================== --- llvm/trunk/Makefile.config.in (original) +++ llvm/trunk/Makefile.config.in Tue Jul 3 18:04:11 2007 @@ -83,7 +83,7 @@ PROJ_etcdir := $(DESTDIR)$(PROJ_prefix)/etc/llvm PROJ_includedir := $(DESTDIR)$(PROJ_prefix)/include PROJ_infodir := $(DESTDIR)$(PROJ_prefix)/info -PROJ_mandir := $(DESTDIR)$(PROJ_prefix)/man +PROJ_mandir := $(DESTDIR)$(PROJ_prefix)/share/man # Determine if we're on a unix type operating system LLVM_ON_UNIX:=@LLVM_ON_UNIX@ From bwendlin at apple.com Tue Jul 3 18:06:28 2007 From: bwendlin at apple.com (bwendlin at apple.com) Date: Tue, 3 Jul 2007 16:06:28 -0700 (PDT) Subject: [llvm-commits] [129120] Change the place the man pages are installed to be /usr/local/ share/man instead Message-ID: <20070703230628.23A84C3CC9B9@src> Revision: 129120 Author: bwendlin Date: 2007-07-03 16:06:28 -0700 (Tue, 03 Jul 2007) Log Message: ----------- Change the place the man pages are installed to be /usr/local/share/man instead of /usr/local/llvm-gcc-install/share/man. Modified Paths: -------------- apple-local/branches/llvm/build_gcc Modified: apple-local/branches/llvm/build_gcc =================================================================== --- apple-local/branches/llvm/build_gcc 2007-07-03 22:52:55 UTC (rev 129119) +++ apple-local/branches/llvm/build_gcc 2007-07-03 23:06:28 UTC (rev 129120) @@ -162,7 +162,7 @@ CONFIGFLAGS="--disable-checking --enable-werror \ --prefix=$DEST_ROOT \ - --mandir=$DEST_ROOT/share/man \ + --mandir=$DEST_DIR$LLVM_INSTALL_PREFIX/share/man \ --enable-languages=c,objc,c++,obj-c++ \ --program-transform-name=/^[cg][^.-]*$/s/$/-$MAJ_VERS/ \ $LIBSTDCXX_CONFIG_OPTION \ From clattner at apple.com Tue Jul 3 18:41:50 2007 From: clattner at apple.com (Chris Lattner) Date: Tue, 3 Jul 2007 16:41:50 -0700 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/IndVarSimplify.cpp In-Reply-To: <46831649.6010708@gmail.com> References: <46831649.6010708@gmail.com> Message-ID: <6526931C-F1A8-4E8C-8B70-221D47F82C00@apple.com> On Jun 27, 2007, at 7:00 PM, Sheng Zhou wrote: > Chris, > > Attached is the testcase, which will get: > > opt: /developer/home2/zsth/llvm-gcc-dev/HEAD/llvm/llvm/lib/VMCore/ > Constants.cpp:1559: static llvm::Constant* > llvm::ConstantExpr::getZExt(llvm::Constant*, const llvm::Type*): > Assertion `C->getType()->getPrimitiveSizeInBits() < Ty- > >getPrimitiveSizeInBits()&& "SrcTy must be smaller than DestTy for > ZExt!"' failed. > > The condition "IterationCount->getType() != LargestType" doesn't > mean the IterationCount->getType's bitwidth < LargestType's > so, sometimes, (like in this testcase), it need a trunc not ext. > This patch is to fix it. Ah, I see. Thank you for checking in the testcase. The reason this looked fishy to me is that the code attempts to insert the IV as the largest type, but that it could then need a zero extend. Doesn't this mean the zero extend case (which I know you didn't put in there :) is really dead? If so, please remove it and switch back to a simple: if (IterationCount->getType() != LargestType) IterationCount = SCEVTruncateExpr::get(IterationCount, LargestType); Thanks! If this doesn't make any sense, please feel free to ask for clarification :) -Chris > Sheng > > > > DOUT << "INDVARS: New CanIV: " << *IndVar; >> >> if (!isa(IterationCount)) { >> - if (IterationCount->getType() != LargestType) >> + if (IterationCount->getType()->getPrimitiveSizeInBits() < >> + LargestType->getPrimitiveSizeInBits()) >> IterationCount = SCEVZeroExtendExpr::get(IterationCount, >> LargestType); >> + else if (IterationCount->getType() != LargestType) >> + IterationCount = SCEVTruncateExpr::get(IterationCount, >> LargestType); >> if (Instruction *DI = LinearFunctionTestReplace(L, >> IterationCount,Rewriter)) >> DeadInsts.insert(DI); >> } > > > > ; ModuleID = 'testcase.bc' > target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32- > i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64" > target triple = "i686-pc-linux-gnu" > > define i32 @testcase(i5 zext %k) { > entry: > br label %bb2 > > bb: ; preds = %bb2 > %tmp1 = add i32 %tmp2, %result ; [#uses=1] > %indvar_next1 = add i5 %k_0, 1 ; [#uses=1] > br label %bb2 > > bb2: ; preds = %bb, %entry > %k_0 = phi i5 [ 0, %entry ], [ %indvar_next1, %bb ] ; [#uses=2] > %result = phi i32 [ 0, %entry ], [ %tmp1, %bb ] ; [#uses=2] > %tmp2 = zext i5 %k_0 to i32 ; [#uses=1] > %exitcond = icmp eq i32 %tmp2, 16 ; [#uses=1] > br i1 %exitcond, label %bb3, label %bb > > bb3: ; preds = %bb2 > ret i32 %result > } From clattner at apple.com Tue Jul 3 18:47:12 2007 From: clattner at apple.com (Chris Lattner) Date: Tue, 3 Jul 2007 16:47:12 -0700 Subject: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp In-Reply-To: <200706291010.23781.baldrick@free.fr> References: <20070627205029.GW5693@village.us.cray.com> <200706291010.23781.baldrick@free.fr> Message-ID: <646AEB4C-8291-4450-9CE3-CAF5D82CCFB0@apple.com> On Jun 29, 2007, at 1:10 AM, Duncan Sands wrote: > Hi, > >>>>> It seems like folding undef/X to undef isn't safe either though, > > here is my understanding of how to fold undef. I hope it clarifies > this confusing area. Of course, I could be confused myself but I > hope not :) > > (1) When is it OK to fold "y=foo(undef)" to "y=undef"? I claim that > it is OK if and only if foo is surjective, i.e. if for each possible > value for y there exists a value for x such that y=foo(x). > "Surjective" > is sometimes called "onto". > > Before I explain why I think this, an example: > y=(undef == z) > The possible values of y are 0 and 1 because the result of == is > an i1. Surjectivity means: can I get (undef==z) to produce each of > 0 and 1 by plugging in different values for undef? Obviously I can, > so in this case I can fold to "y=undef". Yep, I agree. > (2) What to do when foo is not surjective? Choose some value for > undef > and fold to "y=foo(value_chosen)". In general foo will involve some > other variables, so the trick is to find a constant value for y > that is > always obtainable no matter what those other variables are (while > it is > logically correct to replace y with a function of those other > variables, > which is what foo(0) will give in general for example, it is more > efficient > to use a constant value if possible). > > Example: folding "y=undef udiv x". This could be folded to 0 or to 1, > since 0 is what you get by substituting undef=0, and 1 is what you get > by substituting undef=x. (If x=0 then in both cases you get 0/0 which > is, I hear, undefined so you can choose it to be 0 or 1 as you like). > Of course you could also fold it to "1 div x" or "intmax div x" or > "(x*x) div x" if you really felt like it, but 0 and 1 are the only > constants that can always be obtained regardless of the value of x, > so they are the most efficient choices. Yes. Duncan, this whole write-up is very helpful. Can you find some place to put this so that we can find it again in the future? How about the programmer's manual? -Chris From resistor at mac.com Tue Jul 3 18:51:19 2007 From: resistor at mac.com (Owen Anderson) Date: Tue, 03 Jul 2007 23:51:19 -0000 Subject: [llvm-commits] [llvm] r37862 - in /llvm/trunk: lib/Transforms/Scalar/GVNPRE.cpp test/Transforms/GVNPRE/gep.ll Message-ID: <200707032351.l63NpJ9X028156@zion.cs.uiuc.edu> Author: resistor Date: Tue Jul 3 18:51:19 2007 New Revision: 37862 URL: http://llvm.org/viewvc/llvm-project?rev=37862&view=rev Log: Add support for performing GVNPRE on GEP instructions. Added: llvm/trunk/test/Transforms/GVNPRE/gep.ll Modified: llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp Modified: llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp?rev=37862&r1=37861&r2=37862&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp Tue Jul 3 18:51:19 2007 @@ -487,6 +487,19 @@ return nextValueNumber++; } + } else if (GetElementPtrInst* U = dyn_cast(V)) { + Expression e = create_expression(U); + + std::map::iterator EI = expressionNumbering.find(e); + if (EI != expressionNumbering.end()) { + valueNumbering.insert(std::make_pair(V, EI->second)); + return EI->second; + } else { + expressionNumbering.insert(std::make_pair(e, nextValueNumber)); + valueNumbering.insert(std::make_pair(V, nextValueNumber)); + + return nextValueNumber++; + } } else { valueNumbering.insert(std::make_pair(V, nextValueNumber)); return nextValueNumber++; @@ -798,6 +811,48 @@ } } + // Varargs operators + } else if (GetElementPtrInst* U = dyn_cast(V)) { + Value* newOp1 = 0; + if (isa(U->getPointerOperand())) + newOp1 = phi_translate(U->getPointerOperand(), pred, succ); + else + newOp1 = U->getPointerOperand(); + + if (newOp1 == 0) + return 0; + + bool changed_idx = false; + std::vector newIdx; + for (GetElementPtrInst::op_iterator I = U->idx_begin(), E = U->idx_end(); + I != E; ++I) + if (isa(*I)) { + Value* newVal = phi_translate(*I, pred, succ); + newIdx.push_back(newVal); + if (newVal != *I) + changed_idx = true; + } else { + newIdx.push_back(*I); + } + + if (newOp1 != U->getPointerOperand() || changed_idx) { + Instruction* newVal = new GetElementPtrInst(U->getPointerOperand(), + &newIdx[0], newIdx.size(), + U->getName()+".expr"); + + uint32_t v = VN.lookup_or_add(newVal); + + Value* leader = find_leader(availableOut[pred], v); + if (leader == 0) { + createdExpressions.push_back(newVal); + return newVal; + } else { + VN.erase(newVal); + delete newVal; + return leader; + } + } + // PHI Nodes } else if (PHINode* P = dyn_cast(V)) { if (P->getParent() == succ) @@ -900,6 +955,26 @@ set.erase(U); presentInSet.flip(VN.lookup(U)); } + + // Handle varargs ops + } else if (GetElementPtrInst* U = dyn_cast(v)) { + bool ptrValid = !isa(U->getPointerOperand()); + ptrValid |= presentInSet.test(VN.lookup(U->getPointerOperand())); + if (ptrValid) + ptrValid = !dependsOnInvoke(U->getPointerOperand()); + + bool varValid = true; + for (GetElementPtrInst::op_iterator I = U->idx_begin(), E = U->idx_end(); + I != E; ++I) + if (varValid) { + varValid &= !isa(*I) || presentInSet.test(VN.lookup(*I)); + varValid &= !dependsOnInvoke(*I); + } + + if (!ptrValid || !varValid) { + set.erase(U); + presentInSet.flip(VN.lookup(U)); + } } } } @@ -972,6 +1047,31 @@ stack.pop_back(); } + // Handle vararg ops + } else if (GetElementPtrInst* U = dyn_cast(e)) { + Value* p = find_leader(set, VN.lookup(U->getPointerOperand())); + + if (p != 0 && isa(p) && + visited.count(p) == 0) + stack.push_back(p); + else { + bool push_va = false; + for (GetElementPtrInst::op_iterator I = U->idx_begin(), + E = U->idx_end(); I != E; ++I) { + Value * v = find_leader(set, VN.lookup(*I)); + if (v != 0 && isa(v) && visited.count(v) == 0) { + stack.push_back(v); + push_va = true; + } + } + + if (!push_va) { + vec.push_back(e); + visited.insert(e); + stack.pop_back(); + } + } + // Handle opaque ops } else { visited.insert(e); @@ -1022,7 +1122,7 @@ if (isa(BI) || isa(BI) || isa(BI) || isa(BI) || isa(BI) || isa(BI) || - isa(BI)) { + isa(BI) || isa(BI)) { Value *leader = find_leader(availableOut[BB], VN.lookup(BI)); if (leader != 0) @@ -1160,6 +1260,34 @@ expNumbers.set(num); } + // Handle vararg ops + } else if (GetElementPtrInst* U = dyn_cast(I)) { + Value* ptrValue = U->getPointerOperand(); + + VN.lookup_or_add(U); + + unsigned num = VN.lookup_or_add(U); + expNumbers.resize(VN.size()); + availNumbers.resize(VN.size()); + + if (isa(ptrValue)) + if (!expNumbers.test(VN.lookup(ptrValue))) { + currExps.insert(ptrValue); + expNumbers.set(VN.lookup(ptrValue)); + } + + for (GetElementPtrInst::op_iterator OI = U->idx_begin(), OE = U->idx_end(); + OI != OE; ++OI) + if (isa(*OI) && !expNumbers.test(VN.lookup(*OI))) { + currExps.insert(*OI); + expNumbers.set(VN.lookup(*OI)); + } + + if (!expNumbers.test(VN.lookup(U))) { + currExps.insert(U); + expNumbers.set(num); + } + // Handle opaque ops } else if (!I->isTerminator()){ VN.lookup_or_add(I); @@ -1373,7 +1501,8 @@ isa(U->getOperand(0)) || isa(U->getOperand(0)) || isa(U->getOperand(0)) || - isa(U->getOperand(0))) + isa(U->getOperand(0)) || + isa(U->getOperand(0))) s1 = find_leader(availableOut[*PI], VN.lookup(U->getOperand(0))); else s1 = U->getOperand(0); @@ -1392,7 +1521,8 @@ isa(U->getOperand(1)) || isa(U->getOperand(1)) || isa(U->getOperand(1)) || - isa(U->getOperand(1))) { + isa(U->getOperand(1)) || + isa(U->getOperand(1))) { s2 = find_leader(availableOut[*PI], VN.lookup(U->getOperand(1))); } else { s2 = U->getOperand(1); @@ -1409,12 +1539,34 @@ isa(U->getOperand(2)) || isa(U->getOperand(2)) || isa(U->getOperand(2)) || - isa(U->getOperand(2))) { + isa(U->getOperand(2)) || + isa(U->getOperand(2))) { s3 = find_leader(availableOut[*PI], VN.lookup(U->getOperand(2))); } else { s3 = U->getOperand(2); } + // Vararg operators + std::vector sVarargs; + if (GetElementPtrInst* G = dyn_cast(U)) { + for (GetElementPtrInst::op_iterator OI = G->idx_begin(), + OE = G->idx_end(); OI != OE; ++OI) { + if (isa(*OI) || + isa(*OI) || + isa(*OI) || + isa(*OI) || + isa(*OI) || + isa(*OI) || + isa(*OI) || + isa(*OI)) { + sVarargs.push_back(find_leader(availableOut[*PI], + VN.lookup(*OI))); + } else { + sVarargs.push_back(*OI); + } + } + } + Value* newVal = 0; if (BinaryOperator* BO = dyn_cast(U)) newVal = BinaryOperator::create(BO->getOpcode(), s1, s2, @@ -1441,6 +1593,10 @@ newVal = CastInst::create(C->getOpcode(), s1, C->getType(), C->getName()+".gvnpre", (*PI)->getTerminator()); + else if (GetElementPtrInst* G = dyn_cast(U)) + newVal = new GetElementPtrInst(s1, &sVarargs[0], sVarargs.size(), + G->getName()+".gvnpre", + (*PI)->getTerminator()); VN.add(newVal, VN.lookup(U)); @@ -1487,7 +1643,8 @@ if (isa(e) || isa(e) || isa(e) || isa(e) || - isa(e) || isa(e) || isa(e)) { + isa(e) || isa(e) || isa(e) || + isa(e)) { if (find_leader(availableOut[D->getIDom()->getBlock()], VN.lookup(e)) != 0) continue; Added: llvm/trunk/test/Transforms/GVNPRE/gep.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/GVNPRE/gep.ll?rev=37862&view=auto ============================================================================== --- llvm/trunk/test/Transforms/GVNPRE/gep.ll (added) +++ llvm/trunk/test/Transforms/GVNPRE/gep.ll Tue Jul 3 18:51:19 2007 @@ -0,0 +1,17 @@ +; RUN: llvm-as < %s | opt -gvnpre | llvm-dis | grep b.gvnpre + +define i32 @extract({ i32 }* %P) { +entry: ; preds = %cond_false, %entry + br i1 true, label %cond_true, label %cond_false + +cond_true: + br label %end + +cond_false: + %a = getelementptr { i32 }* %P, i32 0, i32 0 + br label %end + +end: + %b = getelementptr { i32 }* %P, i32 0, i32 0 + ret i32 0 +} From isanbard at gmail.com Tue Jul 3 19:19:54 2007 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 04 Jul 2007 00:19:54 -0000 Subject: [llvm-commits] [llvm] r37863 - in /llvm/trunk: lib/Target/X86/X86InstrMMX.td test/CodeGen/X86/2007-06-15-IntToMMX.ll test/CodeGen/X86/2007-07-03-GR64ToVR64.ll Message-ID: <200707040019.l640Jsuc028788@zion.cs.uiuc.edu> Author: void Date: Tue Jul 3 19:19:54 2007 New Revision: 37863 URL: http://llvm.org/viewvc/llvm-project?rev=37863&view=rev Log: Allow a GR64 to be moved into an MMX register via the "movd" instruction. Still need to have JIT generate this code. Added: llvm/trunk/test/CodeGen/X86/2007-07-03-GR64ToVR64.ll Modified: llvm/trunk/lib/Target/X86/X86InstrMMX.td llvm/trunk/test/CodeGen/X86/2007-06-15-IntToMMX.ll Modified: llvm/trunk/lib/Target/X86/X86InstrMMX.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrMMX.td?rev=37863&r1=37862&r2=37863&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrMMX.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrMMX.td Tue Jul 3 19:19:54 2007 @@ -183,6 +183,9 @@ def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (ops i32mem:$dst, VR64:$src), "movd {$src, $dst|$dst, $src}", []>; +def MMX_MOVD64to64rr : MMXI<0x6E, MRMSrcReg, (ops VR64:$dst, GR64:$src), + "movd {$src, $dst|$dst, $src}", []>; + def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (ops VR64:$dst, VR64:$src), "movq {$src, $dst|$dst, $src}", []>; def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (ops VR64:$dst, i64mem:$src), @@ -552,6 +555,16 @@ def : Pat<(v1i64 (bitconvert (v4i16 VR64:$src))), (v1i64 VR64:$src)>; def : Pat<(v1i64 (bitconvert (v8i8 VR64:$src))), (v1i64 VR64:$src)>; +// 64-bit bit convert. +def : Pat<(v1i64 (bitconvert (i64 GR64:$src))), + (MMX_MOVD64to64rr GR64:$src)>; +def : Pat<(v2i32 (bitconvert (i64 GR64:$src))), + (MMX_MOVD64to64rr GR64:$src)>; +def : Pat<(v4i16 (bitconvert (i64 GR64:$src))), + (MMX_MOVD64to64rr GR64:$src)>; +def : Pat<(v8i8 (bitconvert (i64 GR64:$src))), + (MMX_MOVD64to64rr GR64:$src)>; + def MMX_X86s2vec : SDNode<"X86ISD::S2VEC", SDTypeProfile<1, 1, []>, []>; // Move scalar to XMM zero-extended Modified: llvm/trunk/test/CodeGen/X86/2007-06-15-IntToMMX.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2007-06-15-IntToMMX.ll?rev=37863&r1=37862&r2=37863&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2007-06-15-IntToMMX.ll (original) +++ llvm/trunk/test/CodeGen/X86/2007-06-15-IntToMMX.ll Tue Jul 3 19:19:54 2007 @@ -1,5 +1,4 @@ ; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+mmx | grep paddusw -; XFAIL: * @R = external global <1 x i64> ; <<1 x i64>*> [#uses=1] define void @foo(<1 x i64> %A, <1 x i64> %B) { Added: llvm/trunk/test/CodeGen/X86/2007-07-03-GR64ToVR64.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2007-07-03-GR64ToVR64.ll?rev=37863&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2007-07-03-GR64ToVR64.ll (added) +++ llvm/trunk/test/CodeGen/X86/2007-07-03-GR64ToVR64.ll Tue Jul 3 19:19:54 2007 @@ -0,0 +1,20 @@ +; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+mmx | grep {movd %rsi, %mm0} && +; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+mmx | grep {movd %rdi, %mm1} && +; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+mmx | grep {paddusw %mm0, %mm1} + + at R = external global <1 x i64> ; <<1 x i64>*> [#uses=1] + +define void @foo(<1 x i64> %A, <1 x i64> %B) { +entry: + %tmp4 = bitcast <1 x i64> %B to <4 x i16> ; <<4 x i16>> [#uses=1] + %tmp6 = bitcast <1 x i64> %A to <4 x i16> ; <<4 x i16>> [#uses=1] + %tmp7 = tail call <4 x i16> @llvm.x86.mmx.paddus.w( <4 x i16> %tmp6, <4 x i16> %tmp4 ) ; <<4 x i16>> [#uses=1] + %tmp8 = bitcast <4 x i16> %tmp7 to <1 x i64> ; <<1 x i64>> [#uses=1] + store <1 x i64> %tmp8, <1 x i64>* @R + tail call void @llvm.x86.mmx.emms( ) + ret void +} + +declare <4 x i16> @llvm.x86.mmx.paddus.w(<4 x i16>, <4 x i16>) + +declare void @llvm.x86.mmx.emms() From dpatel at apple.com Tue Jul 3 20:05:22 2007 From: dpatel at apple.com (Devang Patel) Date: Wed, 04 Jul 2007 01:05:22 -0000 Subject: [llvm-commits] [llvm] r37864 - /llvm/trunk/include/llvm/Analysis/Dominators.h Message-ID: <200707040105.l6415NgY029998@zion.cs.uiuc.edu> Author: dpatel Date: Tue Jul 3 20:05:22 2007 New Revision: 37864 URL: http://llvm.org/viewvc/llvm-project?rev=37864&view=rev Log: Fix typo in assertion check. Modified: llvm/trunk/include/llvm/Analysis/Dominators.h Modified: llvm/trunk/include/llvm/Analysis/Dominators.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/Dominators.h?rev=37864&r1=37863&r2=37864&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/Dominators.h (original) +++ llvm/trunk/include/llvm/Analysis/Dominators.h Tue Jul 3 20:05:22 2007 @@ -155,7 +155,7 @@ DomTreeNode *N = getNode(BB); assert (N && "Missing dominator tree node"); DomTreeNode *I = N->getIDom(); - assert (N && "Missing immediate dominator"); + assert (I && "Missing immediate dominator"); return I->getBlock(); } From dpatel at apple.com Tue Jul 3 20:11:19 2007 From: dpatel at apple.com (Devang Patel) Date: Wed, 04 Jul 2007 01:11:19 -0000 Subject: [llvm-commits] [llvm] r37865 - /llvm/trunk/include/llvm/Analysis/Dominators.h Message-ID: <200707040111.l641BJcc030189@zion.cs.uiuc.edu> Author: dpatel Date: Tue Jul 3 20:11:19 2007 New Revision: 37865 URL: http://llvm.org/viewvc/llvm-project?rev=37865&view=rev Log: Remove unused method - getIDomBlock(). Modified: llvm/trunk/include/llvm/Analysis/Dominators.h Modified: llvm/trunk/include/llvm/Analysis/Dominators.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/Dominators.h?rev=37865&r1=37864&r2=37865&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/Dominators.h (original) +++ llvm/trunk/include/llvm/Analysis/Dominators.h Tue Jul 3 20:11:19 2007 @@ -149,16 +149,6 @@ return getNode(BB); } - /// getIDomBlock - return basic block BB's immediate dominator basic block. - /// - BasicBlock *getIDomBlock(BasicBlock *BB) { - DomTreeNode *N = getNode(BB); - assert (N && "Missing dominator tree node"); - DomTreeNode *I = N->getIDom(); - assert (I && "Missing immediate dominator"); - return I->getBlock(); - } - /// getRootNode - This returns the entry node for the CFG of the function. If /// this tree represents the post-dominance relations for a function, however, /// this root may be a node with the block == NULL. This is the case when From isanbard at gmail.com Tue Jul 3 20:29:22 2007 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 04 Jul 2007 01:29:22 -0000 Subject: [llvm-commits] [llvm] r37866 - /llvm/trunk/lib/Target/X86/X86InstrMMX.td Message-ID: <200707040129.l641TMwl030772@zion.cs.uiuc.edu> Author: void Date: Tue Jul 3 20:29:22 2007 New Revision: 37866 URL: http://llvm.org/viewvc/llvm-project?rev=37866&view=rev Log: Support generation of GR64 to MMX code in the JIT. Modified: llvm/trunk/lib/Target/X86/X86InstrMMX.td Modified: llvm/trunk/lib/Target/X86/X86InstrMMX.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrMMX.td?rev=37866&r1=37865&r2=37866&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrMMX.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrMMX.td Tue Jul 3 20:29:22 2007 @@ -25,6 +25,8 @@ // MMXIS - MMX instructions with XS prefix. class MMXI o, Format F, dag ops, string asm, list pattern> : I, TB, Requires<[HasMMX]>; +class MMXRI o, Format F, dag ops, string asm, list pattern> + : I, TB, REX_W, Requires<[HasMMX]>; class MMX2I o, Format F, dag ops, string asm, list pattern> : I, TB, OpSize, Requires<[HasMMX]>; class MMXIi8 o, Format F, dag ops, string asm, list pattern> @@ -183,8 +185,8 @@ def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (ops i32mem:$dst, VR64:$src), "movd {$src, $dst|$dst, $src}", []>; -def MMX_MOVD64to64rr : MMXI<0x6E, MRMSrcReg, (ops VR64:$dst, GR64:$src), - "movd {$src, $dst|$dst, $src}", []>; +def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (ops VR64:$dst, GR64:$src), + "movd {$src, $dst|$dst, $src}", []>; def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (ops VR64:$dst, VR64:$src), "movq {$src, $dst|$dst, $src}", []>; From reid at x10sys.com Tue Jul 3 20:35:32 2007 From: reid at x10sys.com (Reid Spencer) Date: Wed, 04 Jul 2007 01:35:32 -0000 Subject: [llvm-commits] [llvm] r37867 - /llvm/trunk/utils/llvmdo Message-ID: <200707040135.l641ZWJt030928@zion.cs.uiuc.edu> Author: reid Date: Tue Jul 3 20:35:32 2007 New Revision: 37867 URL: http://llvm.org/viewvc/llvm-project?rev=37867&view=rev Log: Ignore the .svn directories so countloc.sh and llvmgrep won't traverse them. Modified: llvm/trunk/utils/llvmdo Modified: llvm/trunk/utils/llvmdo URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/llvmdo?rev=37867&r1=37866&r2=37867&view=diff ============================================================================== --- llvm/trunk/utils/llvmdo (original) +++ llvm/trunk/utils/llvmdo Tue Jul 3 20:35:32 2007 @@ -78,6 +78,8 @@ paths_to_ignore="\ -path */CVS -o \ -path */CVS/* -o \ + -path */.svn/ -o \ + -path */.svn/* -o \ -path docs/doxygen/* -o \ -path docs/CommandGuide/html/* -o \ -path docs/CommandGuide/man/* -o \ From evan.cheng at apple.com Tue Jul 3 20:35:58 2007 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 3 Jul 2007 18:35:58 -0700 Subject: [llvm-commits] [llvm] r37843 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp In-Reply-To: <200707021618.l62GI6GA029325@zion.cs.uiuc.edu> References: <200707021618.l62GI6GA029325@zion.cs.uiuc.edu> Message-ID: Hi Dan, This patch is breaking llvm-gcc bootstrapping on PPC. I am not sure what exactly wrong is it. But the old code has a check for endianness while your new code doesn't. Can you check again if you are taking endianness into consideration? Thanks, Evan On Jul 2, 2007, at 9:18 AM, Dan Gohman wrote: > Author: djg > Date: Mon Jul 2 11:18:06 2007 > New Revision: 37843 > > URL: http://llvm.org/viewvc/llvm-project?rev=37843&view=rev > Log: > Replace ExpandScalarFormalArgs and ExpandScalarCallArgs with the newly > refactored getCopyFromParts and getCopyToParts, which are more > general. > This effectively adds support for lowering illegal by-val vector call > arguments. > > Modified: > llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ > SelectionDAG/SelectionDAGISel.cpp? > rev=37843&r1=37842&r2=37843&view=diff > ====================================================================== > ======== > --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp > (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon > Jul 2 11:18:06 2007 > @@ -2861,7 +2861,7 @@ > if (!MVT::isVector(ValueVT) || NumParts == 1) { > // If the value was expanded, copy from the parts. > if (NumParts > 1) { > - for (unsigned i = 0; i < NumParts; ++i) > + for (unsigned i = 0; i != NumParts; ++i) > Parts[i] = DAG.getNode(ISD::EXTRACT_ELEMENT, PartVT, Val, > DAG.getConstant(i, MVT::i32)); > return; > @@ -2950,7 +2950,7 @@ > // Copy the legal parts from the registers. > unsigned NumParts = Regs.size(); > SmallVector Parts(NumParts); > - for (unsigned i = 0; i < NumParts; ++i) { > + for (unsigned i = 0; i != NumParts; ++i) { > SDOperand Part = Flag ? > DAG.getCopyFromReg(Chain, Regs[i], RegVT, > *Flag) : > DAG.getCopyFromReg(Chain, Regs[i], RegVT); > @@ -2981,7 +2981,7 @@ > getCopyToParts(DAG, Val, &Parts[0], NumParts, RegVT); > > // Copy the parts into the registers. > - for (unsigned i = 0; i < NumParts; ++i) { > + for (unsigned i = 0; i != NumParts; ++i) { > SDOperand Part = Flag ? > DAG.getCopyToReg(Chain, R[i], Parts[i], *Flag) : > DAG.getCopyToReg(Chain, R[i], Parts[i]); > @@ -3746,32 +3746,6 @@ > DAG.getSrcValue(I.getOperand(2)))); > } > > -/// ExpandScalarFormalArgs - Recursively expand the > formal_argument node, either > -/// bit_convert it or join a pair of them with a BUILD_PAIR when > appropriate. > -static SDOperand ExpandScalarFormalArgs(MVT::ValueType VT, SDNode > *Arg, > - unsigned &i, SelectionDAG > &DAG, > - TargetLowering &TLI) { > - if (TLI.getTypeAction(VT) != TargetLowering::Expand) > - return SDOperand(Arg, i++); > - > - MVT::ValueType EVT = TLI.getTypeToTransformTo(VT); > - unsigned NumVals = MVT::getSizeInBits(VT) / MVT::getSizeInBits > (EVT); > - if (NumVals == 1) { > - return DAG.getNode(ISD::BIT_CONVERT, VT, > - ExpandScalarFormalArgs(EVT, Arg, i, DAG, > TLI)); > - } else if (NumVals == 2) { > - SDOperand Lo = ExpandScalarFormalArgs(EVT, Arg, i, DAG, TLI); > - SDOperand Hi = ExpandScalarFormalArgs(EVT, Arg, i, DAG, TLI); > - if (!TLI.isLittleEndian()) > - std::swap(Lo, Hi); > - return DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); > - } else { > - // Value scalarized into many values. Unimp for now. > - assert(0 && "Cannot expand i64 -> i16 yet!"); > - } > - return SDOperand(); > -} > - > /// TargetLowering::LowerArguments - This is the default > LowerArguments > /// implementation, which just inserts a FORMAL_ARGUMENTS node. > FIXME: When all > /// targets are migrated to using FORMAL_ARGUMENTS, this hook > should be > @@ -3842,8 +3816,8 @@ > SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, > DAG.getNodeValueTypes(RetVals), > RetVals.size(), > &Ops[0], Ops.size()).Val; > - > - DAG.setRoot(SDOperand(Result, Result->getNumValues()-1)); > + unsigned NumArgRegs = Result->getNumValues() - 1; > + DAG.setRoot(SDOperand(Result, NumArgRegs)); > > // Set up the return result vector. > Ops.clear(); > @@ -3875,79 +3849,22 @@ > Ops.push_back(Op); > break; > } > - case Expand: > - if (!MVT::isVector(VT)) { > - // If this is a large integer or a floating point node > that needs to be > - // expanded, it needs to be reassembled from small > integers. Figure out > - // what the source elt type is and how many small integers > it is. > - Ops.push_back(ExpandScalarFormalArgs(VT, Result, i, DAG, > *this)); > - } else { > - // Otherwise, this is a vector type. We only support > legal vectors > - // right now. > - const VectorType *PTy = cast(I->getType()); > - unsigned NumElems = PTy->getNumElements(); > - const Type *EltTy = PTy->getElementType(); > - > - // Figure out if there is a Packed type corresponding to > this Vector > - // type. If so, convert to the vector type. > - MVT::ValueType TVT = > - MVT::getVectorType(getValueType(EltTy), NumElems); > - if (TVT != MVT::Other && isTypeLegal(TVT)) { > - SDOperand N = SDOperand(Result, i++); > - // Handle copies from vectors to registers. > - N = DAG.getNode(ISD::BIT_CONVERT, TVT, N); > - Ops.push_back(N); > - } else { > - assert(0 && "Don't support illegal by-val vector > arguments yet!"); > - abort(); > - } > - } > + case Expand: { > + MVT::ValueType PartVT = getRegisterType(VT); > + unsigned NumParts = getNumRegisters(VT); > + SmallVector Parts(NumParts); > + for (unsigned j = 0; j != NumParts; ++j) > + Parts[j] = SDOperand(Result, i++); > + Ops.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, > PartVT, VT)); > break; > } > + } > } > + assert(i == NumArgRegs && "Argument register count mismatch!"); > return Ops; > } > > > -/// ExpandScalarCallArgs - Recursively expand call argument node by > -/// bit_converting it or extract a pair of elements from the > larger node. > -static void ExpandScalarCallArgs(MVT::ValueType VT, SDOperand Arg, > - unsigned Flags, > - SmallVector &Ops, > - SelectionDAG &DAG, > - TargetLowering &TLI, > - bool isFirst = true) { > - > - if (TLI.getTypeAction(VT) != TargetLowering::Expand) { > - // if it isn't first piece, alignment must be 1 > - if (!isFirst) > - Flags = (Flags & (~ISD::ParamFlags::OrigAlignment)) | > - (1 << ISD::ParamFlags::OrigAlignmentOffs); > - Ops.push_back(Arg); > - Ops.push_back(DAG.getConstant(Flags, MVT::i32)); > - return; > - } > - > - MVT::ValueType EVT = TLI.getTypeToTransformTo(VT); > - unsigned NumVals = MVT::getSizeInBits(VT) / MVT::getSizeInBits > (EVT); > - if (NumVals == 1) { > - Arg = DAG.getNode(ISD::BIT_CONVERT, EVT, Arg); > - ExpandScalarCallArgs(EVT, Arg, Flags, Ops, DAG, TLI, isFirst); > - } else if (NumVals == 2) { > - SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, EVT, Arg, > - DAG.getConstant(0, TLI.getPointerTy > ())); > - SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, EVT, Arg, > - DAG.getConstant(1, TLI.getPointerTy > ())); > - if (!TLI.isLittleEndian()) > - std::swap(Lo, Hi); > - ExpandScalarCallArgs(EVT, Lo, Flags, Ops, DAG, TLI, isFirst); > - ExpandScalarCallArgs(EVT, Hi, Flags, Ops, DAG, TLI, false); > - } else { > - // Value scalarized into many values. Unimp for now. > - assert(0 && "Cannot expand i64 -> i16 yet!"); > - } > -} > - > /// TargetLowering::LowerCallTo - This is the default LowerCallTo > /// implementation, which just inserts an ISD::CALL node, which is > later custom > /// lowered by the target to something concrete. FIXME: When all > targets are > @@ -4014,35 +3931,24 @@ > Ops.push_back(Op); > Ops.push_back(DAG.getConstant(Flags, MVT::i32)); > break; > - case Expand: > - if (!MVT::isVector(VT)) { > - // If this is a large integer, it needs to be broken down > into small > - // integers. Figure out what the source elt type is and > how many small > - // integers it is. > - ExpandScalarCallArgs(VT, Op, Flags, Ops, DAG, *this); > - } else { > - // Otherwise, this is a vector type. We only support > legal vectors > - // right now. > - const VectorType *PTy = cast(Args[i].Ty); > - unsigned NumElems = PTy->getNumElements(); > - const Type *EltTy = PTy->getElementType(); > - > - // Figure out if there is a Packed type corresponding to > this Vector > - // type. If so, convert to the vector type. > - MVT::ValueType TVT = > - MVT::getVectorType(getValueType(EltTy), NumElems); > - if (TVT != MVT::Other && isTypeLegal(TVT)) { > - // Insert a BIT_CONVERT of the original type to the > vector type. > - Op = DAG.getNode(ISD::BIT_CONVERT, TVT, Op); > - Ops.push_back(Op); > - Ops.push_back(DAG.getConstant(Flags, MVT::i32)); > - } else { > - assert(0 && "Don't support illegal by-val vector call > args yet!"); > - abort(); > - } > + case Expand: { > + MVT::ValueType PartVT = getRegisterType(VT); > + unsigned NumParts = getNumRegisters(VT); > + SmallVector Parts(NumParts); > + getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT); > + for (unsigned i = 0; i != NumParts; ++i) { > + // if it isn't first piece, alignment must be 1 > + unsigned MyFlags = Flags; > + if (i != 0) > + MyFlags = (MyFlags & (~ISD::ParamFlags::OrigAlignment)) | > + (1 << ISD::ParamFlags::OrigAlignmentOffs); > + > + Ops.push_back(Parts[i]); > + Ops.push_back(DAG.getConstant(MyFlags, MVT::i32)); > } > break; > } > + } > } > > // Figure out the result value types. > @@ -4360,7 +4266,7 @@ > > // Copy the value by legal parts into sequential virtual registers. > getCopyToParts(DAG, Op, &Regs[0], NumRegs, RegisterVT); > - for (unsigned i = 0; i < NumRegs; ++i) > + for (unsigned i = 0; i != NumRegs; ++i) > Chains[i] = DAG.getCopyToReg(getRoot(), Reg + i, Regs[i]); > return DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], > NumRegs); > } > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From resistor at mac.com Tue Jul 3 23:51:16 2007 From: resistor at mac.com (Owen Anderson) Date: Wed, 04 Jul 2007 04:51:16 -0000 Subject: [llvm-commits] [llvm] r37868 - in /llvm/trunk: lib/Transforms/Scalar/GVNPRE.cpp test/Transforms/GVNPRE/2007-07-03-PhiTranslateGEP.ll Message-ID: <200707040451.l644pGat003148@zion.cs.uiuc.edu> Author: resistor Date: Tue Jul 3 23:51:16 2007 New Revision: 37868 URL: http://llvm.org/viewvc/llvm-project?rev=37868&view=rev Log: Fix an error in phi translation of GEPs that was causing failures. Added: llvm/trunk/test/Transforms/GVNPRE/2007-07-03-PhiTranslateGEP.ll Modified: llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp Modified: llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp?rev=37868&r1=37867&r2=37868&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp Tue Jul 3 23:51:16 2007 @@ -836,7 +836,7 @@ } if (newOp1 != U->getPointerOperand() || changed_idx) { - Instruction* newVal = new GetElementPtrInst(U->getPointerOperand(), + Instruction* newVal = new GetElementPtrInst(newOp1, &newIdx[0], newIdx.size(), U->getName()+".expr"); Added: llvm/trunk/test/Transforms/GVNPRE/2007-07-03-PhiTranslateGEP.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/GVNPRE/2007-07-03-PhiTranslateGEP.ll?rev=37868&view=auto ============================================================================== --- llvm/trunk/test/Transforms/GVNPRE/2007-07-03-PhiTranslateGEP.ll (added) +++ llvm/trunk/test/Transforms/GVNPRE/2007-07-03-PhiTranslateGEP.ll Tue Jul 3 23:51:16 2007 @@ -0,0 +1,14 @@ +; RUN: llvm-as < %s | opt -gvnpre | llvm-dis + +define i64 @foo({ i32, i32 }** %__v) { +entry: + br label %bb + +bb: ; preds = %bb, %entry + %__x.066.0 = phi { i32, i32 }* [ null, %entry ], [ null, %bb ] + %tmp2.i.i63 = getelementptr { i32, i32 }* %__x.066.0, i32 0, i32 1 + br i1 false, label %bb, label %cond_true + +cond_true: ; preds = %bb + ret i64 0 +} From zhousheng00 at gmail.com Wed Jul 4 00:34:06 2007 From: zhousheng00 at gmail.com (Zhou Sheng) Date: Wed, 4 Jul 2007 13:34:06 +0800 Subject: [llvm-commits] CVS: llvm/lib/Transforms/Scalar/IndVarSimplify.cpp In-Reply-To: <6526931C-F1A8-4E8C-8B70-221D47F82C00@apple.com> References: <46831649.6010708@gmail.com> <6526931C-F1A8-4E8C-8B70-221D47F82C00@apple.com> Message-ID: <8abe0dc60707032234i2cd26765o6f8fea29020f1970@mail.gmail.com> Hi Chris, > > The condition "IterationCount->getType() != LargestType" doesn't > > mean the IterationCount->getType's bitwidth < LargestType's > > so, sometimes, (like in this testcase), it need a trunc not ext. > > This patch is to fix it. > > Ah, I see. Thank you for checking in the testcase. The reason this > looked fishy to me is that the code attempts to insert the IV as the > largest type, but that it could then need a zero extend. Doesn't > this mean the zero extend case (which I know you didn't put in > there :) is really dead? If so, please remove it and switch back to > a simple: > > if (IterationCount->getType() != LargestType) > IterationCount = SCEVTruncateExpr::get(IterationCount, > LargestType); No, it's incorrect. That will fail llvm/test/Transforms/IndVarSimplify/exit_value_tests.llx ( which got an assertion) i think we should keep the extend code. Sheng. Thanks! If this doesn't make any sense, please feel free to ask for > clarification :) > > -Chris > > > Sheng > > > > > > > > DOUT << "INDVARS: New CanIV: " << *IndVar; > >> > >> if (!isa(IterationCount)) { > >> - if (IterationCount->getType() != LargestType) > >> + if (IterationCount->getType()->getPrimitiveSizeInBits() < > >> + LargestType->getPrimitiveSizeInBits()) > >> IterationCount = SCEVZeroExtendExpr::get(IterationCount, > >> LargestType); > >> + else if (IterationCount->getType() != LargestType) > >> + IterationCount = SCEVTruncateExpr::get(IterationCount, > >> LargestType); > >> if (Instruction *DI = LinearFunctionTestReplace(L, > >> IterationCount,Rewriter)) > >> DeadInsts.insert(DI); > >> } > > > > > > > > ; ModuleID = 'testcase.bc' > > target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32- > > i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64" > > target triple = "i686-pc-linux-gnu" > > > > define i32 @testcase(i5 zext %k) { > > entry: > > br label %bb2 > > > > bb: ; preds = %bb2 > > %tmp1 = add i32 %tmp2, %result ; [#uses=1] > > %indvar_next1 = add i5 %k_0, 1 ; [#uses=1] > > br label %bb2 > > > > bb2: ; preds = %bb, %entry > > %k_0 = phi i5 [ 0, %entry ], [ %indvar_next1, %bb ] ; > [#uses=2] > > %result = phi i32 [ 0, %entry ], [ %tmp1, %bb ] ; > [#uses=2] > > %tmp2 = zext i5 %k_0 to i32 ; [#uses=1] > > %exitcond = icmp eq i32 %tmp2, 16 ; [#uses=1] > > br i1 %exitcond, label %bb3, label %bb > > > > bb3: ; preds = %bb2 > > ret i32 %result > > } > > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20070704/9ca48814/attachment.html From clattner at apple.com Wed Jul 4 00:54:25 2007 From: clattner at apple.com (Chris Lattner) Date: Tue, 3 Jul 2007 22:54:25 -0700 Subject: [llvm-commits] [llvm] r37843 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp In-Reply-To: References: <200707021618.l62GI6GA029325@zion.cs.uiuc.edu> Message-ID: <3FD23FCD-D28C-41DB-BB50-258013EDC6E0@apple.com> On Jul 3, 2007, at 6:35 PM, Evan Cheng wrote: > Hi Dan, > > This patch is breaking llvm-gcc bootstrapping on PPC. > > I am not sure what exactly wrong is it. But the old code has a check > for endianness while your new code doesn't. Can you check again if > you are taking endianness into consideration? One thing to check: if returning (or passing) an i64 value, make sure the right halves are returned in r3 vs r4. Thanks! -Chris From rspencer at reidspencer.com Wed Jul 4 01:38:45 2007 From: rspencer at reidspencer.com (Reid Spencer) Date: Tue, 03 Jul 2007 23:38:45 -0700 Subject: [llvm-commits] [llvm] r37855 - /llvm/trunk/docs/Makefile In-Reply-To: <200707031811.l63IBKcp018386@zion.cs.uiuc.edu> References: <200707031811.l63IBKcp018386@zion.cs.uiuc.edu> Message-ID: <1183531125.3143.276.camel@bashful.x10sys.com> On Tue, 2007-07-03 at 18:11 +0000, Tanya Lattner wrote: > Author: tbrethou > Date: Tue Jul 3 13:11:20 2007 > New Revision: 37855 > > URL: http://llvm.org/viewvc/llvm-project?rev=37855&view=rev > Log: > We really should not have this version number in SO many makefiles. This should also probably change to svn instead of cvs, but leaving it for now. Its not in "SO" many makefiles. The line you changed is a comment (to remind us of the syntax of the line being grepped). The next line (PACKAGE_VERSION) is extracting the version number from the AC_INIT line in the configure.ac file, specifically so the version number can be in just one place. Do you know of other places where the version number is located? Reid. > > Modified: > llvm/trunk/docs/Makefile > > Modified: llvm/trunk/docs/Makefile > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/Makefile?rev=37855&r1=37854&r2=37855&view=diff > ============================================================================== > > --- llvm/trunk/docs/Makefile (original) > +++ llvm/trunk/docs/Makefile Tue Jul 3 13:11:20 2007 > @@ -14,7 +14,7 @@ > PROJ_OBJ_DIR = . > DOXYGEN = doxygen > # Extract version number from the AC_INT line in configure.ac > -# AC_INIT([[llvm]],[[2.0cvs]],[llvmbugs at cs.uiuc.edu]) > +# AC_INIT([[llvm]],[[2.1cvs]],[llvmbugs at cs.uiuc.edu]) > PACKAGE_VERSION = $(shell grep AC_INIT ../autoconf/configure.ac | sed -e 's/[^,]*,[[][[]//' -e 's/]],.*//') > $(warning VERSION=$(VERSION)) > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From rspencer at reidspencer.com Wed Jul 4 01:47:56 2007 From: rspencer at reidspencer.com (Reid Spencer) Date: Tue, 03 Jul 2007 23:47:56 -0700 Subject: [llvm-commits] [llvm] r37852 - in /llvm/trunk: autoconf/configure.ac configure In-Reply-To: <681F705E-1249-4935-8587-B77393837D92@apple.com> References: <200707031701.l63H1xKa016388@zion.cs.uiuc.edu> <681F705E-1249-4935-8587-B77393837D92@apple.com> Message-ID: <1183531676.3143.278.camel@bashful.x10sys.com> On Tue, 2007-07-03 at 10:27 -0700, Tanya Lattner wrote: > This will most likely break the nightly tester. Yeah, it will. The nightly tester checks out "test-suite" *as* llvm-test specifically so this configure stuff wouldn't break .. a temporary measure till we get llvm-top all figured out. Reid. > > -Tanya > > On Jul 3, 2007, at 10:01 AM, Anton Korobeynikov wrote: > > > Author: asl > > Date: Tue Jul 3 12:01:58 2007 > > New Revision: 37852 > > > > URL: http://llvm.org/viewvc/llvm-project?rev=37852&view=rev > > Log: > > Rename llvm-test => test-suite. By Dave Greene. > > > > Modified: > > llvm/trunk/autoconf/configure.ac > > llvm/trunk/configure > > > > Modified: llvm/trunk/autoconf/configure.ac > > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/ > > configure.ac?rev=37852&r1=37851&r2=37852&view=diff > > ====================================================================== > > ======== > > > > --- llvm/trunk/autoconf/configure.ac (original) > > +++ llvm/trunk/autoconf/configure.ac Tue Jul 3 12:01:58 2007 > > @@ -70,7 +70,7 @@ > > sample) AC_CONFIG_SUBDIRS([projects/sample]) ;; > > privbracket) AC_CONFIG_SUBDIRS([projects/privbracket]) ;; > > llvm-stacker) AC_CONFIG_SUBDIRS([projects/llvm-stacker]) ;; > > - llvm-test) AC_CONFIG_SUBDIRS([projects/llvm-test]) ;; > > + test-suite) AC_CONFIG_SUBDIRS([projects/test-suite]) ;; > > llvm-reopt) AC_CONFIG_SUBDIRS([projects/llvm-reopt]);; > > llvm-gcc) AC_CONFIG_SUBDIRS([projects/llvm-gcc]) ;; > > llvm-java) AC_CONFIG_SUBDIRS([projects/llvm-java]) ;; > > > > Modified: llvm/trunk/configure > > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/configure? > > rev=37852&r1=37851&r2=37852&view=diff > > ====================================================================== > > ======== > > > > --- llvm/trunk/configure (original) > > +++ llvm/trunk/configure Tue Jul 3 12:01:58 2007 > > @@ -944,7 +944,7 @@ > > ac_subdirs_all='projects/sample > > projects/privbracket > > projects/llvm-stacker > > -projects/llvm-test > > +projects/test-suite > > projects/llvm-reopt > > projects/llvm-gcc > > projects/llvm-java > > @@ -2074,7 +2074,7 @@ > > ;; > > llvm-stacker) subdirs="$subdirs projects/llvm-stacker" > > ;; > > - llvm-test) subdirs="$subdirs projects/llvm-test" > > + test-suite) subdirs="$subdirs projects/test-suite" > > ;; > > llvm-reopt) subdirs="$subdirs projects/llvm-reopt" > > ;; > > > > > > _______________________________________________ > > llvm-commits mailing list > > llvm-commits at cs.uiuc.edu > > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From baldrick at free.fr Wed Jul 4 03:13:02 2007 From: baldrick at free.fr (Duncan Sands) Date: Wed, 4 Jul 2007 10:13:02 +0200 Subject: [llvm-commits] [llvm] r37851 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp In-Reply-To: <20070703212950.GG5693@village.us.cray.com> References: <200707031403.l63E3woZ011704@zion.cs.uiuc.edu> <200707031643.14426.baldrick@free.fr> <20070703212950.GG5693@village.us.cray.com> Message-ID: <200707041013.02760.baldrick@free.fr> > Looking at it a little more, I think the instcombine folds are actually > wrong here. For example, it does X + undef -> undef, but that's wrong if > X is a NaN. Right, that's why I suggested X + undef -> X. Ciao, Duncan. From reid at x10sys.com Wed Jul 4 06:17:02 2007 From: reid at x10sys.com (Reid Spencer) Date: Wed, 4 Jul 2007 06:17:02 -0500 Subject: [llvm-commits] CVS: llvm-www/SVNLayout.html Message-ID: <200707041117.l64BH2lM024209@zion.cs.uiuc.edu> Changes in directory llvm-www: SVNLayout.html added (r1.1) --- Log message: Add a document to discuss Subversion design issues and policy. --- Diffs of the changes: (+219 -0) SVNLayout.html | 219 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 219 insertions(+) Index: llvm-www/SVNLayout.html diff -c /dev/null llvm-www/SVNLayout.html:1.1 *** /dev/null Wed Jul 4 06:16:50 2007 --- llvm-www/SVNLayout.html Wed Jul 4 06:16:40 2007 *************** *** 0 **** --- 1,219 ---- + + +
Subversion Layout and Policy
+
+

This document contains notes about the planned layout of the Subversion + repository and policies surrounding its use.

+
    +
  1. Introduction
    2. +
  2. URL +
  3. Top Level +
  4. The llvm-top Module +
  5. Rename 'llvm' as 'core' +
  6. The website Module +
  7. Best Practices +
+
+ + +
Introduction
+
+

There has been some confusion recently about how the Subversion repository + should be laid out. This document provides some proposals for the layout + including some reasoning for the decisions made. It is intended to be used as + a working draft until we have consensus and then as the specification for the + actual layout work to be done.

+

Much of the content here was culled from an IRC conversation between Chris, + Reid, Tanya and Gordon on July 2nd 2007

+

The sub-sections below each describe one layout construct.

+
+ + +
URL
+
+

Right now, access to subversion is provided through URLs of this form:

+
    +
  • http://llvm.org/svn/llvm-project/...
    • +
  • https://user at llvm.org/svn/llvm-project/...
    • +
+

The former is for anonymous access, the later for authenticated read-write + access.

+

Given that the URL already contains "llvm.org", the llvm-project directory + is redundant and should be dropped.

+

It is proposed that all URLS should be shortened to these prefixes:

+
    +
  • http://llvm.org/svn/...
    • +
  • https://user at llvm.org/svn/...
    • +
+

Advantages:

+
    +
  • Shorter paths are always welcome.
    • +
  • We don't intend for the project to have multiple repositories.
    • +
  • No confusion about "llvm-project".
    • +
+

Disadvantages:

+
    +
  • We won't be able to utilize multiple subversion repositories (some would + claim this to be an advantage).
    • +
+
+ + +
The Top Level
+
+

After much discussion, it was decided that the root of the repository + should contain only directories with one directory for each module + (sub-project). Under each of those directories are the usual trunk, + branches, and tags directories. + 

+     http://llvm.org/svn/llvm/
+        trunk/
+           lib/
+           include/
+           tools/
+           ...
+        tags/
+           RELEASE_10
+           ...
+           RELEASE_20
+ 
+     http://llvm.org/svn/llvm-gcc/
+        trunk/
+           gcc/
+           libcpp/
+           libiberty/
+           ...
+        tags/
+        branches/
+ 
+     ...
+
+

In other words, we are using the recommended and customary layout for the + repository as described in the Subversion project's + Best Practices. + +

There was some discussion about putting (only) the trunk, + branches, and tags directories at the top level with + sub-directories under each of those for the various modules. This was rejected + because of the following factors:

+
    +
  • It is not the conventional or customary arrangement for modules in a + repository.
    • +
  • It goes against the standard layout recommended by the Subversion + Best Practices.
    • +
  • It prevents a whole module from being dumped in a consistent state + because there is no top level directory that contains the trunk, the + branches and the tags all together. Having everything in one directory is a + requirement for having this history correctly mapped when you dump that + directory. This would make it difficult to move a module to a new + repository, for example.
    • +
  • The perceived benefits of this layout be handled by the + llvm-top module. The original motivation + for this layout was: +
      +
    • Allows a more natural checkout URL by putting the "trunk" above the + module name so that it isn't necessary to specify a local directory name + for the thing checked out. For example, you could just:
      +         svn co http://llvm.org/svn/trunk/llvm
+
      instead of:
      +         svn co http://llvm.org/svn/llvm/trunk llvm
+
      However, this isn't a huge inconvenience and it only needs to be + done once for the llvm-top module. From there the + makefile can fetch, configure and build what is needed.
      • +
    • Allows master release tags and branches to be created more easily. The + idea was that the modules of the project are quite interdependent and we + would want some kind of "version lock" on them. Turns out that since + everything is in the same repository and commits are atomic, that we can + simply use a revision number. If more specialized releases are needed, we + can handle them in llvm-top.
      • +
    +
+
+ + +
llvm-top
+
+

We have decided that there should be a module, named llvm-top that + contains some "top level" stuff. This is the module that you should check out + at the top level of your working directory. It should also be the only module + you need to check out manually because the Makefile in llvm-top will assist + you with checking out, configuring, and building the other modules. This + module may also have some top level documentation (project policies, etc.) but + nothing specific about individual modules.

+

For example, we expect the typical developer scenario to go something like + this:

+     svn co http://llvm.org/svn/llvm-top/trunk llvm-top
+     make get-llvm          # fetches the llvm module from subversion
+     make get-test-suite    # fetches the llvm test suite module from subversion
+     make get-llvm-gcc      # fetches the llvm-gcc module from subversion
+     make tested-C-compiler # configures and builds both llvm and llvm-gcc 
+                            # and runs the test suite against llvm-gcc c compiler
+
+

Note here that the user could have just done "make tested-C-compiler" which + would know that it depended on llvm, llvm-gcc, and + test-suite, checked them out automatically, and then proceeded with + the configure and build.

+

I have created an initial version of llvm-top in the repository already. + Please try it out and let me know what you think.

+
+ + +
Rename llvm as core
+
+

We would like to, at some point, rename the llvm module as + core (or something similar). The reasons for this are:

+
    +
  • The notion of checking out "llvm" from "llvm" is a bit confusing, + especially for folks new to the project.
    • +
  • The name no longer reflects the reality. We will likely be moving things + out of llvm and into llvm-top so that it really will + become just the core compiler code.
    • +
  • We thought you all would enjoy some serious confusion.
    • +
+
+ + +
The 'website' module
+
+

Because the project has become a federation of related projects, we are + redesigning the web site. The new website will, strangely enough, be located + in a module named website. This will be the site that is presented + for the http://llvm.org/ URL. This will describe the project as a + whole and then provide places where each module (sub-project) can insert its + own content.

+

Chris Lattner is working on a prototype for this and a proposal for the + site.

+
+ + +
Best Practices
+
+

We intend that developers follow the + Best Practices + defined by the Subversion project. Most of the items on that page have been + official or unofficial practice within the LLVM development community for + several years. Please make sure you read these best practices and then this + list of notes and exceptions:

+
    +
  1. Use a sane repository layout. The best practice recommends that + there be a "project root" with /trunk, /branches, and + /tags. We will follow that advice so that all top level directories + are for the modules (sub-projects) with t-t-b as a layer under each of them. + However, we have a slight twist. We want to have a module that gets checked + out first as the top level on the client side as + discussed above.
    2. +
  2. The "issue tracker" discussed means our Bugzilla system.
    3. +
  3. We will use the Branch-When-Needed system of branching.
    4. +
+
+ + +
+
+ Valid CSS! + Valid HTML 4.01! +
Last modified: $Date: 2007/07/04 11:16:40 $ +
+ From baldrick at free.fr Wed Jul 4 06:36:11 2007 From: baldrick at free.fr (Duncan Sands) Date: Wed, 4 Jul 2007 13:36:11 +0200 Subject: [llvm-commits] Handle nested try-catch statements Message-ID: <200707041336.12890.baldrick@free.fr> These patches, to LLVM and llvm-gcc, add support for nested try-catch statements. Previously, only the inner most catch or filter was being taken into account. Thanks to inlining it is possible for a function to contain any number of filters and catches nested within each other (without inlining filters only occur outermost). To support this I've junked the eh.filter intrinsic and extended the eh.selector intrinsic so it can simultaneously contain catches and filters. To indicate a filter, the number of typeinfos in the filter is given as an argument, followed by the typeinfos themselves. For example, %s = eh.selector(exception,personality,t1,2,t2,t3,t4); has a catch (typeinfo t1) followed by a filter of length 2 (typeinfos t2 and t3) followed by another catch (typeinfo t4). This is not very beautiful but it is simple, effective and unambiguous. An alternative would have been to keep eh.filter and output multiple filter/selector intrinsics like this: %s1 = eh.selector(exception,personality,t4); %s2 = eh.filter(exception,personality,t2,t3); %s3 = eh.selector(exception,personality,t1); (yes, in reverse order). Then %s1 and %s2 would never be used, and %s3 would be tested against the various typeinfos, even if they were never mentioned in the %s3 selector itself (eg t4). It also requires extra mucking around with the live-in markings for the exception and selector registers produced during codegen. I decided it was better to enhance eh.selector and get rid of eh.filter. Note that this means that eh.selector now corresponds directly to the action sequence in the dwarf eh table. The testcase shows the difference before and after (I've simplified the output a bit): Before: %eh_select = call @llvm.eh.filter(%eh_ptr, @__gxx_personality_v0, null) ; "empty" filter [the "null" should not be here - also fixed in this patch] After: %eh_select = call @llvm.eh.selector(%eh_ptr, @__gxx_personality_v0, i32 0, ; empty filter @_ZTI3One, ; catch i32 1, @_ZTI3Two, ; filter of length 1 @_ZTI5Three, @_ZTI4Four, ; two catches i32 2, @_ZTI4Five, @_ZTI3Six, ; filter of length 2 null) ; catch-all Ciao, Duncan. -------------- next part -------------- A non-text attachment was scrubbed... Name: llvm_part.diff Type: text/x-diff Size: 14442 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20070704/55365299/attachment.bin -------------- next part -------------- A non-text attachment was scrubbed... Name: gcc_part.diff Type: text/x-diff Size: 8422 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20070704/55365299/attachment-0001.bin -------------- next part -------------- A non-text attachment was scrubbed... Name: 2007-07-04-NestedCatches.cpp Type: text/x-c++src Size: 533 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20070704/55365299/attachment-0002.bin From clattner at apple.com Wed Jul 4 11:53:43 2007 From: clattner at apple.com (Chris Lattner) Date: Wed, 4 Jul 2007 09:53:43 -0700 Subject: [llvm-commits] [llvm] r37851 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp In-Reply-To: <200707041013.02760.baldrick@free.fr> References: <200707031403.l63E3woZ011704@zion.cs.uiuc.edu> <200707031643.14426.baldrick@free.fr> <20070703212950.GG5693@village.us.cray.com> <200707041013.02760.baldrick@free.fr> Message-ID: <24BE4655-4907-4C97-A13C-6A4FA7E37E32@apple.com> On Jul 4, 2007, at 1:13 AM, Duncan Sands wrote: >> Looking at it a little more, I think the instcombine folds are >> actually >> wrong here. For example, it does X + undef -> undef, but that's >> wrong if >> X is a NaN. > > Right, that's why I suggested X + undef -> X. Generally it's better to fold to a constant (e.g. a NAN) instead of retaining a use of X. Folding to a NAN makes the computation of X dead, and theoretically the nan will be folded through lots of other operations (which probably isn't true right now, but could be implemented). -Chris From resistor at mac.com Wed Jul 4 13:26:19 2007 From: resistor at mac.com (Owen Anderson) Date: Wed, 04 Jul 2007 18:26:19 -0000 Subject: [llvm-commits] [llvm] r37871 - in /llvm/trunk: lib/Transforms/Scalar/GVNPRE.cpp test/Transforms/GVNPRE/2007-07-04-CleanSelect.ll Message-ID: <200707041826.l64IQJ4V003117@zion.cs.uiuc.edu> Author: resistor Date: Wed Jul 4 13:26:18 2007 New Revision: 37871 URL: http://llvm.org/viewvc/llvm-project?rev=37871&view=rev Log: Fix a typo that was killing GVNPRE of select instructions. Added: llvm/trunk/test/Transforms/GVNPRE/2007-07-04-CleanSelect.ll Modified: llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp Modified: llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp?rev=37871&r1=37870&r2=37871&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp Wed Jul 4 13:26:18 2007 @@ -1040,7 +1040,7 @@ stack.push_back(r); else if (m != 0 && isa(m) && visited.count(m) == 0) - stack.push_back(r); + stack.push_back(m); else { vec.push_back(e); visited.insert(e); Added: llvm/trunk/test/Transforms/GVNPRE/2007-07-04-CleanSelect.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/GVNPRE/2007-07-04-CleanSelect.ll?rev=37871&view=auto ============================================================================== --- llvm/trunk/test/Transforms/GVNPRE/2007-07-04-CleanSelect.ll (added) +++ llvm/trunk/test/Transforms/GVNPRE/2007-07-04-CleanSelect.ll Wed Jul 4 13:26:18 2007 @@ -0,0 +1,9 @@ +; RUN: llvm-as < %s | opt -gvnpre | llvm-dis + +define i32* @_ZN6Solver9propagateEv(i32* %this) { +entry: + %tmp15.i48 = load i8* null ; [#uses=2] + %tmp64.i.i51 = sub i8 0, %tmp15.i48 ; [#uses=1] + %tmp231.i52 = select i1 false, i8 %tmp15.i48, i8 %tmp64.i.i51 ; [#uses=0] + ret i32* null +} From sabre at nondot.org Wed Jul 4 13:42:47 2007 From: sabre at nondot.org (Chris Lattner) Date: Wed, 04 Jul 2007 18:42:47 -0000 Subject: [llvm-commits] [llvm] r37872 - /llvm/trunk/docs/GettingStarted.html Message-ID: <200707041842.l64Igl3O003570@zion.cs.uiuc.edu> Author: lattner Date: Wed Jul 4 13:42:47 2007 New Revision: 37872 URL: http://llvm.org/viewvc/llvm-project?rev=37872&view=rev Log: Make the GSG actually work. Modified: llvm/trunk/docs/GettingStarted.html Modified: llvm/trunk/docs/GettingStarted.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/GettingStarted.html?rev=37872&r1=37871&r2=37872&view=diff ============================================================================== --- llvm/trunk/docs/GettingStarted.html (original) +++ llvm/trunk/docs/GettingStarted.html Wed Jul 4 13:42:47 2007 @@ -724,7 +724,7 @@ you get it from the Subversion repository:

   cd llvm/projects
-  svn co http://llvm.org/svn/llvm-project/test-suite/trunk test-suite
+  svn co http://llvm.org/svn/llvm-project/test-suite/trunk llvm-test

By placing it in the llvm/projects, it will be automatically configured by the LLVM configure script as well as automatically updated when From reid at x10sys.com Wed Jul 4 14:28:00 2007 From: reid at x10sys.com (Reid Spencer) Date: Wed, 4 Jul 2007 14:28:00 -0500 Subject: [llvm-commits] CVS: llvm-www/SVNLayout.html Message-ID: <200707041928.l64JS0ct004762@zion.cs.uiuc.edu> Changes in directory llvm-www: SVNLayout.html updated: 1.1 -> 1.2 --- Log message: Fix some validation errors. --- Diffs of the changes: (+5 -5) SVNLayout.html | 10 +++++----- 1 files changed, 5 insertions(+), 5 deletions(-) Index: llvm-www/SVNLayout.html diff -u llvm-www/SVNLayout.html:1.1 llvm-www/SVNLayout.html:1.2 --- llvm-www/SVNLayout.html:1.1 Wed Jul 4 06:16:40 2007 +++ llvm-www/SVNLayout.html Wed Jul 4 14:27:21 2007 @@ -90,7 +90,7 @@

In other words, we are using the recommended and customary layout for the repository as described in the Subversion project's - Best Practices. + Best Practices.

There was some discussion about putting (only) the trunk, branches, and tags directories at the top level with @@ -118,8 +118,8 @@ instead of:

         svn co http://llvm.org/svn/llvm/trunk llvm
However, this isn't a huge inconvenience and it only needs to be - done once for the llvm-top module. From there the - makefile can fetch, configure and build what is needed. + done once for the llvm-top module. From there + the makefile can fetch, configure and build what is needed.
  • Allows master release tags and branches to be created more easily. The idea was that the modules of the project are quite interdependent and we would want some kind of "version lock" on them. Turns out that since @@ -189,7 +189,7 @@
    Best Practices

    We intend that developers follow the - Best Practices + Best Practices defined by the Subversion project. Most of the items on that page have been official or unofficial practice within the LLVM development community for several years. Please make sure you read these best practices and then this @@ -214,6 +214,6 @@ src="http://jigsaw.w3.org/css-validator/images/vcss" alt="Valid CSS!"> Valid HTML 4.01! -
    Last modified: $Date: 2007/07/04 11:16:40 $ +
    Last modified: $Date: 2007/07/04 19:27:21 $ From reid at x10sys.com Wed Jul 4 14:30:28 2007 From: reid at x10sys.com (Reid Spencer) Date: Wed, 4 Jul 2007 14:30:28 -0500 Subject: [llvm-commits] CVS: llvm-www/SVNLayout.html Message-ID: <200707041930.l64JUSMC004877@zion.cs.uiuc.edu> Changes in directory llvm-www: SVNLayout.html updated: 1.2 -> 1.3 --- Log message: Make the example actually work. --- Diffs of the changes: (+2 -1) SVNLayout.html | 3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index: llvm-www/SVNLayout.html diff -u llvm-www/SVNLayout.html:1.2 llvm-www/SVNLayout.html:1.3 --- llvm-www/SVNLayout.html:1.2 Wed Jul 4 14:27:21 2007 +++ llvm-www/SVNLayout.html Wed Jul 4 14:30:09 2007 @@ -143,6 +143,7 @@

    For example, we expect the typical developer scenario to go something like this:

         svn co http://llvm.org/svn/llvm-top/trunk llvm-top
+    cd llvm-top            # enter the llvm-top module you just checked out
     make get-llvm          # fetches the llvm module from subversion
     make get-test-suite    # fetches the llvm test suite module from subversion
     make get-llvm-gcc      # fetches the llvm-gcc module from subversion
@@ -214,6 +215,6 @@
   src="http://jigsaw.w3.org/css-validator/images/vcss" alt="Valid CSS!">
   Valid HTML 4.01!
-
    Last modified: $Date: 2007/07/04 19:27:21 $
+
    Last modified: $Date: 2007/07/04 19:30:09 $
 
 





From reid at x10sys.com  Wed Jul  4 14:50:29 2007
From: reid at x10sys.com (Reid Spencer)
Date: Wed, 4 Jul 2007 14:50:29 -0500
Subject: [llvm-commits] CVS: llvm-www/SVNLayout.html
Message-ID: <200707041950.l64JoT4H005363@zion.cs.uiuc.edu>



Changes in directory llvm-www:

SVNLayout.html updated: 1.3 -> 1.4
---
Log message:

We won't move stuff to llvm-top from llvm, but perhaps from llvm to other
modules.


---
Diffs of the changes:  (+2 -2)

 SVNLayout.html |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm-www/SVNLayout.html
diff -u llvm-www/SVNLayout.html:1.3 llvm-www/SVNLayout.html:1.4
--- llvm-www/SVNLayout.html:1.3	Wed Jul  4 14:30:09 2007
+++ llvm-www/SVNLayout.html	Wed Jul  4 14:50:11 2007
@@ -167,7 +167,7 @@
     
  • The notion of checking out "llvm" from "llvm" is a bit confusing,
     especially for folks new to the project.
    • 
     
  • The name no longer reflects the reality. We will likely be moving things
-    out of llvm and into llvm-top so that it really will
+    out of llvm and into other modules so that it really will
     become just the core compiler code.
    • 
     
  • We thought you all would enjoy some serious confusion.
    • 
   
@@ -215,6 +215,6 @@
   src="http://jigsaw.w3.org/css-validator/images/vcss" alt="Valid CSS!">
   Valid HTML 4.01!
-
    Last modified: $Date: 2007/07/04 19:30:09 $
+
    Last modified: $Date: 2007/07/04 19:50:11 $
 
 





From baldrick at free.fr  Wed Jul  4 15:09:16 2007
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 04 Jul 2007 20:09:16 -0000
Subject: [llvm-commits] [test-suite] r37873 - in
 /test-suite/trunk/SingleSource/UnitTests/Vector/SSE: sse.expandfft.c
 sse.isamax.c sse.stepfft.c
Message-ID: <200707042009.l64K9G9s005919@zion.cs.uiuc.edu>

Author: baldrick
Date: Wed Jul  4 15:09:16 2007
New Revision: 37873

URL: http://llvm.org/viewvc/llvm-project?rev=37873&view=rev
Log:
In isamax, clearly align==1 should have been align==3.
Add bres to the indices calculated using SSE to correct
for the earlier offsetting  of xp.  Align xbig and indx.
For expandfft and stepfft make sure wu and wr are aligned
on a 16 byte boundary.  Without these alignment fixes, the
programs crash when built with gcc 4.1, 4.2 and 4.3.

Modified:
    test-suite/trunk/SingleSource/UnitTests/Vector/SSE/sse.expandfft.c
    test-suite/trunk/SingleSource/UnitTests/Vector/SSE/sse.isamax.c
    test-suite/trunk/SingleSource/UnitTests/Vector/SSE/sse.stepfft.c

Modified: test-suite/trunk/SingleSource/UnitTests/Vector/SSE/sse.expandfft.c
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/Vector/SSE/sse.expandfft.c?rev=37873&r1=37872&r2=37873&view=diff

==============================================================================
--- test-suite/trunk/SingleSource/UnitTests/Vector/SSE/sse.expandfft.c (original)
+++ test-suite/trunk/SingleSource/UnitTests/Vector/SSE/sse.expandfft.c Wed Jul  4 15:09:16 2007
@@ -94,7 +94,8 @@
    int jb, jc, jw, k, k2, lj, m, j, mj, mj2, pass, tgle;
    float (*a)[2],(*b)[2],(*c)[2],(*d)[2];
    float (*aa)[2],(*bb)[2],(*cb)[2],(*dd)[2];
-   float rp,up,wr[4],wu[4];
+   float rp,up,wra[7],wua[7];
+   float *wr = wra, *wu = wua;
    __m128 V0,V1,V2,V3,V4,V5,V6,V7;
    __m128 V8,V9,V10,V11,V12,V13,V14,V15;
 
@@ -107,6 +108,8 @@
    mj   = 1;
    mj2  = 2;
    lj   = n/2;
+   wr += (4 - ((unsigned int) wr >> 2)) & 0x03; // align wr
+   wu += (4 - ((unsigned int) wu >> 2)) & 0x03; // align wu
 // first pass thru data: x -> y
    a = (void *)&x[0][0];
    b = (void *)&x[n/2][0];

Modified: test-suite/trunk/SingleSource/UnitTests/Vector/SSE/sse.isamax.c
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/Vector/SSE/sse.isamax.c?rev=37873&r1=37872&r2=37873&view=diff

==============================================================================
--- test-suite/trunk/SingleSource/UnitTests/Vector/SSE/sse.isamax.c (original)
+++ test-suite/trunk/SingleSource/UnitTests/Vector/SSE/sse.isamax.c Wed Jul  4 15:09:16 2007
@@ -30,7 +30,8 @@
   float bbig,ebig,bres,*xp;
   int eres,i,ibbig,iebig,align,nsegs,mb,nn;
   __m128 offset4,V0,V1,V2,V3,V6,V7;
-  float xbig[8],indx[8];
+  float xbiga[11],indxa[11];
+  float *xbig = xbiga, *indx = indxa;
 // n < NS done in scalar mode
   if(n < NS){
      iebig = 0;
@@ -63,7 +64,7 @@
      if(fabsf(x[1]) > bbig){
         bbig  = fabsf(x[1]); ibbig = 1;
      }
-  } else if(align == 1){    // bres = 1 case
+  } else if(align == 3){    // bres = 1 case
      bbig = fabsf(x[0]); ibbig = 0;
      bres = 1.0; nn = n - 1;
   } else {                  // bres = 0 case
@@ -99,6 +100,8 @@
      V7 = _mm_max_ps(V7,V3);
   }
 // Now finish up: segment maxima are in V0, indices in V7
+  xbig += (4 - ((unsigned int) xbig >> 2)) & 0x03; // align xbig
+  indx += (4 - ((unsigned int) indx >> 2)) & 0x03; // align indx
   _mm_store_ps(xbig,V0);
   _mm_store_ps(indx,V7);
   if(eres>0){
@@ -112,7 +115,7 @@
   for(i=0;i<4+eres;i++){
      if(xbig[i] > ebig){
         ebig = xbig[i];
-        iebig = (int) indx[i];
+        iebig = (int) (indx[i]+bres);
      }
   }
   return(iebig);

Modified: test-suite/trunk/SingleSource/UnitTests/Vector/SSE/sse.stepfft.c
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/Vector/SSE/sse.stepfft.c?rev=37873&r1=37872&r2=37873&view=diff

==============================================================================
--- test-suite/trunk/SingleSource/UnitTests/Vector/SSE/sse.stepfft.c (original)
+++ test-suite/trunk/SingleSource/UnitTests/Vector/SSE/sse.stepfft.c Wed Jul  4 15:09:16 2007
@@ -156,12 +156,16 @@
 float a[][2],b[][2],c[][2],d[][2],w[][2],sign;
 {
    int j,k,jc,jw,l,lj,mj2,mseg;
-   float rp,up,wr[4],wu[4];
+   float rp,up,wra[7],wua[7];
    __m128 xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7;
+   float *wr = wra, *wu = wua;
 
    mj2 = 2*mj;
    lj  = n/mj2;
 
+   wr += (4 - ((unsigned int) wr >> 2)) & 0x03; // align wr
+   wu += (4 - ((unsigned int) wu >> 2)) & 0x03; // align wu
+
    for(j=0; j



Changes in directory llvm-www:

Users.html updated: 1.20 -> 1.21
---
Log message:

add faust


---
Diffs of the changes:  (+6 -1)

 Users.html |    7 ++++++-
 1 files changed, 6 insertions(+), 1 deletion(-)


Index: llvm-www/Users.html
diff -u llvm-www/Users.html:1.20 llvm-www/Users.html:1.21
--- llvm-www/Users.html:1.20	Wed Jun  6 15:16:55 2007
+++ llvm-www/Users.html	Wed Jul  4 15:10:08 2007
@@ -238,6 +238,11 @@
     PyPy Project
     Python interpreter written in Python.  Targets LLVM and C.
   
+  
+  
+    Faust Signal Processing Language
+    Signal processing language, uses the LLVM JIT for runtime codegen.
+
    @@ -252,6 +257,6 @@ src="http://www.w3.org/Icons/valid-html401" alt="Valid HTML 4.01!">
    LLVM Development List
    - Last modified: $Date: 2007/06/06 20:16:55 $ + Last modified: $Date: 2007/07/04 20:10:08 $ From baldrick at free.fr Wed Jul 4 15:48:48 2007 From: baldrick at free.fr (Duncan Sands) Date: Wed, 04 Jul 2007 20:48:48 -0000 Subject: [llvm-commits] [llvm] r37874 - /llvm/trunk/test/C++Frontend/2007-07-04-NestedCatches.cpp Message-ID: <200707042048.l64Kmmp2006909@zion.cs.uiuc.edu> Author: baldrick Date: Wed Jul 4 15:48:48 2007 New Revision: 37874 URL: http://llvm.org/viewvc/llvm-project?rev=37874&view=rev Log: Nested try-catch-filter testcase. Added: llvm/trunk/test/C++Frontend/2007-07-04-NestedCatches.cpp Added: llvm/trunk/test/C++Frontend/2007-07-04-NestedCatches.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/C%2B%2BFrontend/2007-07-04-NestedCatches.cpp?rev=37874&view=auto ============================================================================== --- llvm/trunk/test/C++Frontend/2007-07-04-NestedCatches.cpp (added) +++ llvm/trunk/test/C++Frontend/2007-07-04-NestedCatches.cpp Wed Jul 4 15:48:48 2007 @@ -0,0 +1,32 @@ +// RUN: %llvmgxx %s -S -emit-llvm -O2 -o - | \ +// RUN: ignore grep {eh\.selector.*One.*Two.*Three.*Four.*Five.*Six.*null} | \ +// RUN: wc -l | grep {\[02\]} + +extern void X(void); + +struct One {}; +struct Two {}; +struct Three {}; +struct Four {}; +struct Five {}; +struct Six {}; + +static void A(void) throw () +{ + X(); +} + +static void B(void) throw (Two) +{ + try { A(); } catch (One) {} +} + +static void C(void) throw (Six, Five) +{ + try { B(); } catch (Three) {} catch (Four) {} +} + +int main () +{ + try { C(); } catch (...) {} +} From clattner at apple.com Wed Jul 4 15:50:11 2007 From: clattner at apple.com (clattner at apple.com) Date: Wed, 4 Jul 2007 13:50:11 -0700 (PDT) Subject: [llvm-commits] [129185] Handle nested try-catch statements: From Duncan Message-ID: <20070704205011.D81A0C685905@src> Revision: 129185 Author: clattner Date: 2007-07-04 13:50:11 -0700 (Wed, 04 Jul 2007) Log Message: ----------- Handle nested try-catch statements: From Duncan These patches, to LLVM and llvm-gcc, add support for nested try-catch statements. Previously, only the inner most catch or filter was being taken into account. Thanks to inlining it is possible for a function to contain any number of filters and catches nested within each other (without inlining filters only occur outermost). To support this I've junked the eh.filter intrinsic and extended the eh.selector intrinsic so it can simultaneously contain catches and filters. To indicate a filter, the number of typeinfos in the filter is given as an argument, followed by the typeinfos themselves. For example, %s = eh.selector(exception,personality,t1,2,t2,t3,t4); has a catch (typeinfo t1) followed by a filter of length 2 (typeinfos t2 and t3) followed by another catch (typeinfo t4). This is not very beautiful but it is simple, effective and unambiguous. An alternative would have been to keep eh.filter and output multiple filter/selector intrinsics like this: %s1 = eh.selector(exception,personality,t4); %s2 = eh.filter(exception,personality,t2,t3); %s3 = eh.selector(exception,personality,t1); (yes, in reverse order). Then %s1 and %s2 would never be used, and %s3 would be tested against the various typeinfos, even if they were never mentioned in the %s3 selector itself (eg t4). It also requires extra mucking around with the live-in markings for the exception and selector registers produced during codegen. I decided it was better to enhance eh.selector and get rid of eh.filter. Note that this means that eh.selector now corresponds directly to the action sequence in the dwarf eh table. The testcase shows the difference before and after (I've simplified the output a bit): Before: %eh_select = call @llvm.eh.filter(%eh_ptr, @__gxx_personality_v0, null) ; "empty" filter [the "null" should not be here - also fixed in this patch] After: %eh_select = call @llvm.eh.selector(%eh_ptr, @__gxx_personality_v0, i32 0, ; empty filter @_ZTI3One, ; catch i32 1, @_ZTI3Two, ; filter of length 1 @_ZTI5Three, @_ZTI4Four, ; two catches i32 2, @_ZTI4Five, @_ZTI3Six, ; filter of length 2 null) ; catch-all Modified Paths: -------------- apple-local/branches/llvm/gcc/llvm-convert.cpp apple-local/branches/llvm/gcc/llvm-internal.h Modified: apple-local/branches/llvm/gcc/llvm-convert.cpp =================================================================== --- apple-local/branches/llvm/gcc/llvm-convert.cpp 2007-07-04 11:25:32 UTC (rev 129184) +++ apple-local/branches/llvm/gcc/llvm-convert.cpp 2007-07-04 20:50:11 UTC (rev 129185) @@ -350,7 +350,6 @@ ExceptionSelectorValue = 0; FuncEHException = 0; FuncEHSelector = 0; - FuncEHFilter = 0; FuncEHGetTypeID = 0; FuncCPPPersonality = 0; FuncUnwindResume = 0; @@ -1965,16 +1964,18 @@ /// GatherTypeInfo - Walk through the expression gathering all the /// typeinfos that are used. void TreeToLLVM::GatherTypeInfo(tree exp, - std::vector &TypeInfos) { + std::vector &TypeInfos) { if (TREE_CODE(exp) == CATCH_EXPR || TREE_CODE(exp) == EH_FILTER_EXPR) { tree Types = TREE_CODE(exp) == CATCH_EXPR ? CATCH_TYPES(exp) : EH_FILTER_TYPES(exp); if (!Types) { - // Catch all. - TypeInfos.push_back( - Constant::getNullValue(PointerType::get(Type::Int8Ty)) - ); + // Catch all or empty filter. + if (TREE_CODE(exp) == CATCH_EXPR) + // Catch all. + TypeInfos.push_back( + Constant::getNullValue(PointerType::get(Type::Int8Ty)) + ); } else if (TREE_CODE(Types) != TREE_LIST) { // Construct typeinfo object. Each call will produce a new expression // even if duplicate. @@ -1982,7 +1983,7 @@ // Produce value. Duplicate typeinfo get folded here. Value *TypeInfo = Emit(TypeInfoNopExpr, 0); // Capture typeinfo. - TypeInfos.push_back(TypeInfo); + TypeInfos.push_back(cast(TypeInfo)); } else { for (; Types; Types = TREE_CHAIN (Types)) { // Construct typeinfo object. Each call will produce a new expression @@ -1991,7 +1992,7 @@ // Produce value. Duplicate typeinfo get folded here. Value *TypeInfo = Emit(TypeInfoNopExpr, 0); // Capture typeinfo. - TypeInfos.push_back(TypeInfo); + TypeInfos.push_back(cast(TypeInfo)); } } } else if (TREE_CODE(exp) == STATEMENT_LIST) { @@ -2007,47 +2008,53 @@ /// AddLandingPad - Insert code to fetch and save the exception and exception /// selector. void TreeToLLVM::AddLandingPad() { - tree TryCatch = 0; - for (std::vector::reverse_iterator I = CurrentEHScopes.rbegin(), - E = CurrentEHScopes.rend(); - I != E; ++I) { - if (TREE_CODE(I->TryExpr) == TRY_CATCH_EXPR) { - TryCatch = I->TryExpr; - break; - } - } - CreateExceptionValues(); // Fetch and store the exception. Value *Ex = Builder.CreateCall(FuncEHException, "eh_ptr"); Builder.CreateStore(Ex, ExceptionValue); - if (!TryCatch) return; - - // Gather the typeinfo. - std::vector TypeInfos; - tree Catches = TREE_OPERAND(TryCatch, 1); - GatherTypeInfo(Catches, TypeInfos); - - // Choose type of landing pad type. - Function *F = FuncEHSelector; - - if (TREE_CODE(Catches) == STATEMENT_LIST && - !tsi_end_p(tsi_start(Catches)) && - TREE_CODE(tsi_stmt(tsi_start(Catches))) == EH_FILTER_EXPR) { - F = FuncEHFilter; + // Fetch and store the exception selector. + std::vector Args; + + for (std::vector::reverse_iterator I = CurrentEHScopes.rbegin(), + E = CurrentEHScopes.rend(); I != E; ++I) { + if (TREE_CODE(I->TryExpr) == TRY_CATCH_EXPR) { + if (I->InfosType == Unknown) { + // Gather the type info and determine the catch type. + tree Catches = TREE_OPERAND(I->TryExpr, 1); + GatherTypeInfo(Catches, I->TypeInfos); + I->InfosType = (TREE_CODE(Catches) == STATEMENT_LIST && + !tsi_end_p(tsi_start(Catches)) && + TREE_CODE(tsi_stmt(tsi_start(Catches))) == + EH_FILTER_EXPR) ? FilterExpr : CatchList; + } + + if (I->InfosType == CatchList && !I->TypeInfos.size()) + continue; + + // Lazily add the exception and the personality function. + if (!Args.size()) { + Args.push_back(Builder.CreateLoad(ExceptionValue, "eh_ptr")); + Args.push_back(CastToType(Instruction::BitCast, FuncCPPPersonality, + PointerType::get(Type::Int8Ty))); + } + + if (I->InfosType == FilterExpr) + // Filter - note the size. + Args.push_back(ConstantInt::get(Type::Int32Ty, I->TypeInfos.size())); + + Args.reserve(Args.size() + I->TypeInfos.size()); + for (unsigned j = 0, N = I->TypeInfos.size(); j < N; ++j) + Args.push_back(I->TypeInfos[j]); + } } - - // Fetch and store exception handler. - std::vector Args; - Args.push_back(Builder.CreateLoad(ExceptionValue, "eh_ptr")); - Args.push_back(CastToType(Instruction::BitCast, FuncCPPPersonality, - PointerType::get(Type::Int8Ty))); - for (unsigned i = 0, N = TypeInfos.size(); i < N; ++i) - Args.push_back(TypeInfos[i]); - Value *Select = Builder.CreateCall(F, &Args[0], Args.size(), "eh_select"); - Builder.CreateStore(Select, ExceptionSelectorValue); + + if (Args.size()) { + Value *Select = Builder.CreateCall(FuncEHSelector, &Args[0], Args.size(), + "eh_select"); + Builder.CreateStore(Select, ExceptionSelectorValue); + } } @@ -2067,8 +2074,6 @@ Intrinsic::eh_exception); FuncEHSelector = Intrinsic::getDeclaration(TheModule, Intrinsic::eh_selector); - FuncEHFilter = Intrinsic::getDeclaration(TheModule, - Intrinsic::eh_filter); FuncEHGetTypeID = Intrinsic::getDeclaration(TheModule, Intrinsic::eh_typeid_for); Modified: apple-local/branches/llvm/gcc/llvm-internal.h =================================================================== --- apple-local/branches/llvm/gcc/llvm-internal.h 2007-07-04 11:25:32 UTC (rev 129184) +++ apple-local/branches/llvm/gcc/llvm-internal.h 2007-07-04 20:50:11 UTC (rev 129185) @@ -258,25 +258,38 @@ BranchFixup(BranchInst *srcBranch, bool IsExceptionEdge) : SrcBranch(srcBranch), isExceptionEdge(IsExceptionEdge) {} }; - + + enum CatchTypes { Unknown = 0, CatchList, FilterExpr }; + /// EHScope - One of these scopes is maintained for each TRY_CATCH_EXPR and /// TRY_FINALLY_EXPR blocks that we are currently in. struct EHScope { /// TryExpr - This is the actual TRY_CATCH_EXPR or TRY_FINALLY_EXPR. tree_node *TryExpr; - + /// UnwindBlock - A basic block in this scope that branches to the unwind /// destination. This is lazily created by the first invoke in this scope. BasicBlock *UnwindBlock; - + // The basic blocks that are directly in this region. std::vector Blocks; - + /// BranchFixups - This is a list of fixups we need to process in this scope /// or in a parent scope. std::vector BranchFixups; - - EHScope(tree_node *expr) : TryExpr(expr), UnwindBlock(0) {} + + /// InfosType - The nature of the type infos TryExpr contains: a list of + /// CATCH_EXPR (-> CatchList) or an EH_FILTER_EXPR (-> FilterExpr). Equal + /// to Unknown if type info information has not yet been gathered. + CatchTypes InfosType; + + /// TypeInfos - The type infos corresponding to the catches or filter in + /// TryExpr. If InfosType is Unknown then this information has not yet + /// been gathered. + std::vector TypeInfos; + + EHScope(tree_node *expr) : + TryExpr(expr), UnwindBlock(0), InfosType(Unknown) {} }; /// CurrentEHScopes - The current stack of exception scopes we are @@ -305,10 +318,6 @@ /// Function *FuncEHSelector; - /// FuncEHFilter - Function used to handle the exception filtering. - /// - Function *FuncEHFilter; - /// FuncEHGetTypeID - Function used to return type id for give typeinfo. /// Function *FuncEHGetTypeID; @@ -457,7 +466,7 @@ private: /// GatherTypeInfo - Walk through the expression gathering all the /// typeinfos that are used. - void GatherTypeInfo(tree_node *exp, std::vector &TypeInfos); + void GatherTypeInfo(tree_node *exp, std::vector &TypeInfos); /// AddLandingPad - Insert code to fetch and save the exception and exception /// selector. From baldrick at free.fr Wed Jul 4 15:52:51 2007 From: baldrick at free.fr (Duncan Sands) Date: Wed, 04 Jul 2007 20:52:51 -0000 Subject: [llvm-commits] [llvm] r37875 - in /llvm/trunk: docs/ExceptionHandling.html include/llvm/Intrinsics.td lib/CodeGen/IntrinsicLowering.cpp lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Message-ID: <200707042052.l64Kqpqu007057@zion.cs.uiuc.edu> Author: baldrick Date: Wed Jul 4 15:52:51 2007 New Revision: 37875 URL: http://llvm.org/viewvc/llvm-project?rev=37875&view=rev Log: Extend eh.selector to support both catches and filters. Drop the eh.filter intrinsic. Modified: llvm/trunk/docs/ExceptionHandling.html llvm/trunk/include/llvm/Intrinsics.td llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Modified: llvm/trunk/docs/ExceptionHandling.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ExceptionHandling.html?rev=37875&r1=37874&r2=37875&view=diff ============================================================================== --- llvm/trunk/docs/ExceptionHandling.html (original) +++ llvm/trunk/docs/ExceptionHandling.html Wed Jul 4 15:52:51 2007 @@ -29,7 +29,6 @@
    1. llvm.eh.exception
    2. llvm.eh.selector
      3. -
    3. llvm.eh.filter
    4. llvm.eh.typeid.for
  • Asm Table Formats @@ -212,13 +211,18 @@

    llvm.eh.selector takes a minimum of three arguments. The first argument is the reference to the exception structure. The second argument is a reference to the personality function to be -used for this try catch sequence. The remaining arguments are references to the -type infos for each of the catch statements in the order they should be tested. +used for this try catch sequence. Each of the remaining arguments is either a +reference to the type info for a catch statement, or a non-negative integer +followed by that many type info references, representing a +filter. +The exception is tested against the arguments sequentially from first to last. The catch all (...) is represented with a null i8*. The result -of the llvm.eh.selector is the index of -the type info in the corresponding exception table. The LLVM C++ front end -generates code to save this value in an alloca location for further use in the -landing pad and catch code.

    +of the llvm.eh.selector is a positive +number if the exception matched a type info, a negative number if it matched a +filter, and zero if it didn't match anything. If a type info matched then the +returned value is the index of the type info in the exception table. +The LLVM C++ front end generates code to save this value in an alloca location +for further use in the landing pad and catch code.

    Once the landing pad has the type info selector, the code branches to the code for the first catch. The catch then checks the value of the type info @@ -268,12 +272,12 @@

    C++ allows the specification of which exception types that can be thrown from a function. To represent this a top level landing pad may exist to filter out invalid types. To express this in LLVM code the landing pad will call llvm.eh.filter instead of llvm.eh.selector. The arguments are the -same, but what gets created in the exception table is different. llvm.eh.filter will return a negative value -if it doesn't find a match. If no match is found then a call to -__cxa_call_unexpected should be made, otherwise +number of different type infos the function may throw, followed by the type +infos themselves. +llvm.eh.selector will return a negative +value if the exception does not match any of the type infos. If no match is +found then a call to __cxa_call_unexpected should be made, otherwise _Unwind_Resume. Each of these functions require a reference to the exception structure.

    @@ -326,32 +330,16 @@

    llvm.eh.selector takes a minimum of three arguments. The first argument is the reference to the exception structure. The second argument is a reference to the personality function to be -used for this try catch sequence. The remaining arguments are references to the -type infos for each of the catch statements in the order they should be tested. -The catch all (...) is represented with a null i8*.

    - - - - -
    - llvm.eh.filter -
    - -
    -
    -  i32 %llvm.eh.filter(i8*, i8*, i8*, ...)
-
    - -

    This intrinsic indicates that the exception selector is available at this -point in the code. The backend will replace this intrinsic with code to fetch -the second argument of a call. The effect is that the intrinsic result is the -exception selector.

    - -

    llvm.eh.filter takes a minimum of -three arguments. The first argument is the reference to the exception -structure. The second argument is a reference to the personality function to be -used for this function. The remaining arguments are references to the type infos -for each type that can be thrown by the current function.

    +used for this try catch sequence. Each of the remaining arguments is either a +reference to the type info for a catch statement, or a non-negative integer +followed by that many type info references, representing a +filter. +The exception is tested against the arguments sequentially from first to last. +The catch all (...) is represented with a null i8*. The result +of the llvm.eh.selector is a positive +number if the exception matched a type info, a negative number if it matched a +filter, and zero if it didn't match anything. If a type info matched then the +returned value is the index of the type info in the exception table.

    @@ -427,15 +415,6 @@
      -

    1. Need to create landing pads for code in between explicit landing pads. -The landing pads will have a zero action and a NULL landing pad address and are -used to inform the runtime that the exception should be rethrown.

      2. - -

    2. Actions for a given function should be folded to save space.

      3. - -

    3. Filters for inlined functions need to be handled more extensively. -Currently it's hardwired for one filter per function.

      4. -

    4. Testing/Testing/Testing.

    Modified: llvm/trunk/include/llvm/Intrinsics.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Intrinsics.td?rev=37875&r1=37874&r2=37875&view=diff ============================================================================== --- llvm/trunk/include/llvm/Intrinsics.td (original) +++ llvm/trunk/include/llvm/Intrinsics.td Wed Jul 4 15:52:51 2007 @@ -231,8 +231,6 @@ def int_eh_exception : Intrinsic<[llvm_ptr_ty]>; def int_eh_selector : Intrinsic<[llvm_i32_ty, llvm_ptr_ty, llvm_ptr_ty, llvm_vararg_ty]>; -def int_eh_filter : Intrinsic<[llvm_i32_ty, llvm_ptr_ty, llvm_ptr_ty, - llvm_vararg_ty]>; def int_eh_typeid_for : Intrinsic<[llvm_i32_ty, llvm_ptr_ty]>; //===---------------- Generic Variable Attribute Intrinsics----------------===// Modified: llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp?rev=37875&r1=37874&r2=37875&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp (original) +++ llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp Wed Jul 4 15:52:51 2007 @@ -708,7 +708,6 @@ case Intrinsic::dbg_declare: case Intrinsic::eh_exception: case Intrinsic::eh_selector: - case Intrinsic::eh_filter: break; // Simply strip out debugging and eh intrinsics case Intrinsic::var_annotation: Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=37875&r1=37874&r2=37875&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Jul 4 15:52:51 2007 @@ -205,12 +205,11 @@ }; } -/// isFilterOrSelector - Return true if this instruction is a call to the -/// eh.filter or the eh.selector intrinsic. -static bool isFilterOrSelector(Instruction *I) { +/// isSelector - Return true if this instruction is a call to the +/// eh.selector intrinsic. +static bool isSelector(Instruction *I) { if (IntrinsicInst *II = dyn_cast(I)) - return II->getIntrinsicID() == Intrinsic::eh_selector - || II->getIntrinsicID() == Intrinsic::eh_filter; + return II->getIntrinsicID() == Intrinsic::eh_selector; return false; } @@ -2293,12 +2292,12 @@ } } -/// ExtractGlobalVariable - If C is a global variable, or a bitcast of one +/// ExtractGlobalVariable - If V is a global variable, or a bitcast of one /// (possibly constant folded), return it. Otherwise return NULL. -static GlobalVariable *ExtractGlobalVariable (Constant *C) { - if (GlobalVariable *GV = dyn_cast(C)) +static GlobalVariable *ExtractGlobalVariable (Value *V) { + if (GlobalVariable *GV = dyn_cast(V)) return GV; - else if (ConstantExpr *CE = dyn_cast(C)) { + else if (ConstantExpr *CE = dyn_cast(V)) { if (CE->getOpcode() == Instruction::BitCast) return dyn_cast(CE->getOperand(0)); else if (CE->getOpcode() == Instruction::GetElementPtr) { @@ -2311,8 +2310,16 @@ return NULL; } +/// ExtractTypeInfo - Extracts the type info from a value. +static GlobalVariable *ExtractTypeInfo (Value *V) { + GlobalVariable *GV = ExtractGlobalVariable(V); + assert (GV || isa(V) && + "TypeInfo must be a global variable or NULL"); + return GV; +} + /// addCatchInfo - Extract the personality and type infos from an eh.selector -/// or eh.filter call, and add them to the specified machine basic block. +/// call, and add them to the specified machine basic block. static void addCatchInfo(CallInst &I, MachineModuleInfo *MMI, MachineBasicBlock *MBB) { // Inform the MachineModuleInfo of the personality for this landing pad. @@ -2325,17 +2332,38 @@ // Gather all the type infos for this landing pad and pass them along to // MachineModuleInfo. std::vector TyInfo; - for (unsigned i = 3, N = I.getNumOperands(); i < N; ++i) { - Constant *C = cast(I.getOperand(i)); - GlobalVariable *GV = ExtractGlobalVariable(C); - assert (GV || isa(C) && - "TypeInfo must be a global variable or NULL"); - TyInfo.push_back(GV); + unsigned N = I.getNumOperands(); + + for (unsigned i = N - 1; i > 2; --i) { + if (ConstantInt *CI = dyn_cast(I.getOperand(i))) { + unsigned FilterLength = CI->getZExtValue(); + unsigned FirstCatch = i + FilterLength + 1; + assert (FirstCatch <= N && "Invalid filter length"); + + if (FirstCatch < N) { + TyInfo.reserve(N - FirstCatch); + for (unsigned j = FirstCatch; j < N; ++j) + TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); + MMI->addCatchTypeInfo(MBB, TyInfo); + TyInfo.clear(); + } + + TyInfo.reserve(FilterLength); + for (unsigned j = i + 1; j < FirstCatch; ++j) + TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); + MMI->addFilterTypeInfo(MBB, TyInfo); + TyInfo.clear(); + + N = i; + } } - if (I.getCalledFunction()->getIntrinsicID() == Intrinsic::eh_filter) - MMI->addFilterTypeInfo(MBB, TyInfo); - else + + if (N > 3) { + TyInfo.reserve(N - 3); + for (unsigned j = 3; j < N; ++j) + TyInfo.push_back(ExtractTypeInfo(I.getOperand(j))); MMI->addCatchTypeInfo(MBB, TyInfo); + } } /// propagateEHRegister - The specified EH register is required in a successor @@ -2483,8 +2511,7 @@ return 0; } - case Intrinsic::eh_selector: - case Intrinsic::eh_filter:{ + case Intrinsic::eh_selector:{ MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); if (ExceptionHandling && MMI) { @@ -2518,10 +2545,7 @@ if (MMI) { // Find the type id for the given typeinfo. - Constant *C = cast(I.getOperand(1)); - GlobalVariable *GV = ExtractGlobalVariable(C); - assert (GV || isa(C) && - "TypeInfo must be a global variable or NULL"); + GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1)); unsigned TypeID = MMI->getTypeIDFor(GV); setValue(&I, DAG.getConstant(TypeID, MVT::i32)); @@ -4297,7 +4321,7 @@ assert(!FLI.MBBMap[SrcBB]->isLandingPad() && "Copying catch info out of a landing pad!"); for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I) - if (isFilterOrSelector(I)) { + if (isSelector(I)) { // Apply the catch info to DestBB. addCatchInfo(cast(*I), MMI, FLI.MBBMap[DestBB]); #ifndef NDEBUG @@ -4341,19 +4365,19 @@ // function and list of typeids logically belong to the invoke (or, if you // like, the basic block containing the invoke), and need to be associated // with it in the dwarf exception handling tables. Currently however the - // information is provided by intrinsics (eh.filter and eh.selector) that - // can be moved to unexpected places by the optimizers: if the unwind edge - // is critical, then breaking it can result in the intrinsics being in the - // successor of the landing pad, not the landing pad itself. This results - // in exceptions not being caught because no typeids are associated with - // the invoke. This may not be the only way things can go wrong, but it - // is the only way we try to work around for the moment. + // information is provided by an intrinsic (eh.selector) that can be moved + // to unexpected places by the optimizers: if the unwind edge is critical, + // then breaking it can result in the intrinsics being in the successor of + // the landing pad, not the landing pad itself. This results in exceptions + // not being caught because no typeids are associated with the invoke. + // This may not be the only way things can go wrong, but it is the only way + // we try to work around for the moment. BranchInst *Br = dyn_cast(LLVMBB->getTerminator()); if (Br && Br->isUnconditional()) { // Critical edge? BasicBlock::iterator I, E; for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I) - if (isFilterOrSelector(I)) + if (isSelector(I)) break; if (I == E) From dalej at apple.com Wed Jul 4 16:07:47 2007 From: dalej at apple.com (Dale Johannesen) Date: Wed, 04 Jul 2007 21:07:47 -0000 Subject: [llvm-commits] [llvm] r37876 - in /llvm/trunk/lib/Target/X86: X86FloatingPoint.cpp X86ISelLowering.cpp X86InstrFPStack.td X86InstrInfo.cpp X86RegisterInfo.cpp Message-ID: <200707042107.l64L7lQt007571@zion.cs.uiuc.edu> Author: johannes Date: Wed Jul 4 16:07:47 2007 New Revision: 37876 URL: http://llvm.org/viewvc/llvm-project?rev=37876&view=rev Log: Refactor X87 instructions. As a side effect, all their names are changed. Modified: llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86InstrFPStack.td llvm/trunk/lib/Target/X86/X86InstrInfo.cpp llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Modified: llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp?rev=37876&r1=37875&r2=37876&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp Wed Jul 4 16:07:47 2007 @@ -121,7 +121,7 @@ std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]); // Emit an fxch to update the runtime processors version of the state - BuildMI(*MBB, I, TII->get(X86::FXCH)).addReg(STReg); + BuildMI(*MBB, I, TII->get(X86::XCH_F)).addReg(STReg); NumFXCH++; } } @@ -130,7 +130,7 @@ unsigned STReg = getSTReg(RegNo); pushReg(AsReg); // New register on top of stack - BuildMI(*MBB, I, TII->get(X86::FLDrr)).addReg(STReg); + BuildMI(*MBB, I, TII->get(X86::LD_Frr)).addReg(STReg); } // popStackAfter - Pop the current value off of the top of the FP stack @@ -324,101 +324,101 @@ // concrete X86 instruction which uses the register stack. // static const TableEntry OpcodeTable[] = { - { X86::FpABS32 , X86::FABS }, - { X86::FpABS64 , X86::FABS }, - { X86::FpADD32m , X86::FADD32m }, - { X86::FpADD64m , X86::FADD64m }, - { X86::FpCHS32 , X86::FCHS }, - { X86::FpCHS64 , X86::FCHS }, - { X86::FpCMOVB32 , X86::FCMOVB }, - { X86::FpCMOVB64 , X86::FCMOVB }, - { X86::FpCMOVBE32 , X86::FCMOVBE }, - { X86::FpCMOVBE64 , X86::FCMOVBE }, - { X86::FpCMOVE32 , X86::FCMOVE }, - { X86::FpCMOVE64 , X86::FCMOVE }, - { X86::FpCMOVNB32 , X86::FCMOVNB }, - { X86::FpCMOVNB64 , X86::FCMOVNB }, - { X86::FpCMOVNBE32 , X86::FCMOVNBE }, - { X86::FpCMOVNBE64 , X86::FCMOVNBE }, - { X86::FpCMOVNE32 , X86::FCMOVNE }, - { X86::FpCMOVNE64 , X86::FCMOVNE }, - { X86::FpCMOVNP32 , X86::FCMOVNP }, - { X86::FpCMOVNP64 , X86::FCMOVNP }, - { X86::FpCMOVP32 , X86::FCMOVP }, - { X86::FpCMOVP64 , X86::FCMOVP }, - { X86::FpCOS32 , X86::FCOS }, - { X86::FpCOS64 , X86::FCOS }, - { X86::FpDIV32m , X86::FDIV32m }, - { X86::FpDIV64m , X86::FDIV64m }, - { X86::FpDIVR32m , X86::FDIVR32m }, - { X86::FpDIVR64m , X86::FDIVR64m }, - { X86::FpIADD16m32 , X86::FIADD16m }, - { X86::FpIADD16m64 , X86::FIADD16m }, - { X86::FpIADD32m32 , X86::FIADD32m }, - { X86::FpIADD32m64 , X86::FIADD32m }, - { X86::FpIDIV16m32 , X86::FIDIV16m }, - { X86::FpIDIV16m64 , X86::FIDIV16m }, - { X86::FpIDIV32m32 , X86::FIDIV32m }, - { X86::FpIDIV32m64 , X86::FIDIV32m }, - { X86::FpIDIVR16m32, X86::FIDIVR16m}, - { X86::FpIDIVR16m64, X86::FIDIVR16m}, - { X86::FpIDIVR32m32, X86::FIDIVR32m}, - { X86::FpIDIVR32m64, X86::FIDIVR32m}, - { X86::FpILD16m32 , X86::FILD16m }, - { X86::FpILD16m64 , X86::FILD16m }, - { X86::FpILD32m32 , X86::FILD32m }, - { X86::FpILD32m64 , X86::FILD32m }, - { X86::FpILD64m32 , X86::FILD64m }, - { X86::FpILD64m64 , X86::FILD64m }, - { X86::FpIMUL16m32 , X86::FIMUL16m }, - { X86::FpIMUL16m64 , X86::FIMUL16m }, - { X86::FpIMUL32m32 , X86::FIMUL32m }, - { X86::FpIMUL32m64 , X86::FIMUL32m }, - { X86::FpIST16m32 , X86::FIST16m }, - { X86::FpIST16m64 , X86::FIST16m }, - { X86::FpIST32m32 , X86::FIST32m }, - { X86::FpIST32m64 , X86::FIST32m }, - { X86::FpIST64m32 , X86::FISTP64m }, - { X86::FpIST64m64 , X86::FISTP64m }, - { X86::FpISTT16m32 , X86::FISTTP16m}, - { X86::FpISTT16m64 , X86::FISTTP16m}, - { X86::FpISTT32m32 , X86::FISTTP32m}, - { X86::FpISTT32m64 , X86::FISTTP32m}, - { X86::FpISTT64m32 , X86::FISTTP64m}, - { X86::FpISTT64m64 , X86::FISTTP64m}, - { X86::FpISUB16m32 , X86::FISUB16m }, - { X86::FpISUB16m64 , X86::FISUB16m }, - { X86::FpISUB32m32 , X86::FISUB32m }, - { X86::FpISUB32m64 , X86::FISUB32m }, - { X86::FpISUBR16m32, X86::FISUBR16m}, - { X86::FpISUBR16m64, X86::FISUBR16m}, - { X86::FpISUBR32m32, X86::FISUBR32m}, - { X86::FpISUBR32m64, X86::FISUBR32m}, - { X86::FpLD032 , X86::FLD0 }, - { X86::FpLD064 , X86::FLD0 }, - { X86::FpLD132 , X86::FLD1 }, - { X86::FpLD164 , X86::FLD1 }, - { X86::FpLD32m , X86::FLD32m }, - { X86::FpLD64m , X86::FLD64m }, - { X86::FpMUL32m , X86::FMUL32m }, - { X86::FpMUL64m , X86::FMUL64m }, - { X86::FpSIN32 , X86::FSIN }, - { X86::FpSIN64 , X86::FSIN }, - { X86::FpSQRT32 , X86::FSQRT }, - { X86::FpSQRT64 , X86::FSQRT }, - { X86::FpST32m , X86::FST32m }, - { X86::FpST64m , X86::FST64m }, - { X86::FpST64m32 , X86::FST32m }, - { X86::FpSUB32m , X86::FSUB32m }, - { X86::FpSUB64m , X86::FSUB64m }, - { X86::FpSUBR32m , X86::FSUBR32m }, - { X86::FpSUBR64m , X86::FSUBR64m }, - { X86::FpTST32 , X86::FTST }, - { X86::FpTST64 , X86::FTST }, - { X86::FpUCOMIr32 , X86::FUCOMIr }, - { X86::FpUCOMIr64 , X86::FUCOMIr }, - { X86::FpUCOMr32 , X86::FUCOMr }, - { X86::FpUCOMr64 , X86::FUCOMr }, + { X86::ABS_Fp32 , X86::ABS_F }, + { X86::ABS_Fp64 , X86::ABS_F }, + { X86::ADD_Fp32m , X86::ADD_F32m }, + { X86::ADD_Fp64m , X86::ADD_F64m }, + { X86::ADD_FpI16m32 , X86::ADD_FI16m }, + { X86::ADD_FpI16m64 , X86::ADD_FI16m }, + { X86::ADD_FpI32m32 , X86::ADD_FI32m }, + { X86::ADD_FpI32m64 , X86::ADD_FI32m }, + { X86::CHS_Fp32 , X86::CHS_F }, + { X86::CHS_Fp64 , X86::CHS_F }, + { X86::CMOVBE_Fp32 , X86::CMOVBE_F }, + { X86::CMOVBE_Fp64 , X86::CMOVBE_F }, + { X86::CMOVB_Fp32 , X86::CMOVB_F }, + { X86::CMOVB_Fp64 , X86::CMOVB_F }, + { X86::CMOVE_Fp32 , X86::CMOVE_F }, + { X86::CMOVE_Fp64 , X86::CMOVE_F }, + { X86::CMOVNBE_Fp32 , X86::CMOVNBE_F }, + { X86::CMOVNBE_Fp64 , X86::CMOVNBE_F }, + { X86::CMOVNB_Fp32 , X86::CMOVNB_F }, + { X86::CMOVNB_Fp64 , X86::CMOVNB_F }, + { X86::CMOVNE_Fp32 , X86::CMOVNE_F }, + { X86::CMOVNE_Fp64 , X86::CMOVNE_F }, + { X86::CMOVNP_Fp32 , X86::CMOVNP_F }, + { X86::CMOVNP_Fp64 , X86::CMOVNP_F }, + { X86::CMOVP_Fp32 , X86::CMOVP_F }, + { X86::CMOVP_Fp64 , X86::CMOVP_F }, + { X86::COS_Fp32 , X86::COS_F }, + { X86::COS_Fp64 , X86::COS_F }, + { X86::DIVR_Fp32m , X86::DIVR_F32m }, + { X86::DIVR_Fp64m , X86::DIVR_F64m }, + { X86::DIVR_FpI16m32, X86::DIVR_FI16m}, + { X86::DIVR_FpI16m64, X86::DIVR_FI16m}, + { X86::DIVR_FpI32m32, X86::DIVR_FI32m}, + { X86::DIVR_FpI32m64, X86::DIVR_FI32m}, + { X86::DIV_Fp32m , X86::DIV_F32m }, + { X86::DIV_Fp64m , X86::DIV_F64m }, + { X86::DIV_FpI16m32 , X86::DIV_FI16m }, + { X86::DIV_FpI16m64 , X86::DIV_FI16m }, + { X86::DIV_FpI32m32 , X86::DIV_FI32m }, + { X86::DIV_FpI32m64 , X86::DIV_FI32m }, + { X86::ILD_Fp16m32 , X86::ILD_F16m }, + { X86::ILD_Fp16m64 , X86::ILD_F16m }, + { X86::ILD_Fp32m32 , X86::ILD_F32m }, + { X86::ILD_Fp32m64 , X86::ILD_F32m }, + { X86::ILD_Fp64m32 , X86::ILD_F64m }, + { X86::ILD_Fp64m64 , X86::ILD_F64m }, + { X86::ISTT_Fp16m32 , X86::ISTT_FP16m}, + { X86::ISTT_Fp16m64 , X86::ISTT_FP16m}, + { X86::ISTT_Fp32m32 , X86::ISTT_FP32m}, + { X86::ISTT_Fp32m64 , X86::ISTT_FP32m}, + { X86::ISTT_Fp64m32 , X86::ISTT_FP64m}, + { X86::ISTT_Fp64m64 , X86::ISTT_FP64m}, + { X86::IST_Fp16m32 , X86::IST_F16m }, + { X86::IST_Fp16m64 , X86::IST_F16m }, + { X86::IST_Fp32m32 , X86::IST_F32m }, + { X86::IST_Fp32m64 , X86::IST_F32m }, + { X86::IST_Fp64m32 , X86::IST_FP64m }, + { X86::IST_Fp64m64 , X86::IST_FP64m }, + { X86::LD_Fp032 , X86::LD_F0 }, + { X86::LD_Fp064 , X86::LD_F0 }, + { X86::LD_Fp132 , X86::LD_F1 }, + { X86::LD_Fp164 , X86::LD_F1 }, + { X86::LD_Fp32m , X86::LD_F32m }, + { X86::LD_Fp64m , X86::LD_F64m }, + { X86::MUL_Fp32m , X86::MUL_F32m }, + { X86::MUL_Fp64m , X86::MUL_F64m }, + { X86::MUL_FpI16m32 , X86::MUL_FI16m }, + { X86::MUL_FpI16m64 , X86::MUL_FI16m }, + { X86::MUL_FpI32m32 , X86::MUL_FI32m }, + { X86::MUL_FpI32m64 , X86::MUL_FI32m }, + { X86::SIN_Fp32 , X86::SIN_F }, + { X86::SIN_Fp64 , X86::SIN_F }, + { X86::SQRT_Fp32 , X86::SQRT_F }, + { X86::SQRT_Fp64 , X86::SQRT_F }, + { X86::ST_Fp32m , X86::ST_F32m }, + { X86::ST_Fp64m , X86::ST_F64m }, + { X86::ST_Fp64m32 , X86::ST_F32m }, + { X86::SUBR_Fp32m , X86::SUBR_F32m }, + { X86::SUBR_Fp64m , X86::SUBR_F64m }, + { X86::SUBR_FpI16m32, X86::SUBR_FI16m}, + { X86::SUBR_FpI16m64, X86::SUBR_FI16m}, + { X86::SUBR_FpI32m32, X86::SUBR_FI32m}, + { X86::SUBR_FpI32m64, X86::SUBR_FI32m}, + { X86::SUB_Fp32m , X86::SUB_F32m }, + { X86::SUB_Fp64m , X86::SUB_F64m }, + { X86::SUB_FpI16m32 , X86::SUB_FI16m }, + { X86::SUB_FpI16m64 , X86::SUB_FI16m }, + { X86::SUB_FpI32m32 , X86::SUB_FI32m }, + { X86::SUB_FpI32m64 , X86::SUB_FI32m }, + { X86::TST_Fp32 , X86::TST_F }, + { X86::TST_Fp64 , X86::TST_F }, + { X86::UCOM_FpIr32 , X86::UCOM_FIr }, + { X86::UCOM_FpIr64 , X86::UCOM_FIr }, + { X86::UCOM_Fpr32 , X86::UCOM_Fr }, + { X86::UCOM_Fpr64 , X86::UCOM_Fr }, }; static unsigned getConcreteOpcode(unsigned Opcode) { @@ -436,27 +436,27 @@ // element is an instruction, the second is the version which pops. // static const TableEntry PopTable[] = { - { X86::FADDrST0 , X86::FADDPrST0 }, + { X86::ADD_FrST0 , X86::ADD_FPrST0 }, - { X86::FDIVRrST0, X86::FDIVRPrST0 }, - { X86::FDIVrST0 , X86::FDIVPrST0 }, + { X86::DIVR_FrST0, X86::DIVR_FPrST0 }, + { X86::DIV_FrST0 , X86::DIV_FPrST0 }, - { X86::FIST16m , X86::FISTP16m }, - { X86::FIST32m , X86::FISTP32m }, + { X86::IST_F16m , X86::IST_FP16m }, + { X86::IST_F32m , X86::IST_FP32m }, - { X86::FMULrST0 , X86::FMULPrST0 }, + { X86::MUL_FrST0 , X86::MUL_FPrST0 }, - { X86::FST32m , X86::FSTP32m }, - { X86::FST64m , X86::FSTP64m }, - { X86::FSTrr , X86::FSTPrr }, + { X86::ST_F32m , X86::ST_FP32m }, + { X86::ST_F64m , X86::ST_FP64m }, + { X86::ST_Frr , X86::ST_FPrr }, - { X86::FSUBRrST0, X86::FSUBRPrST0 }, - { X86::FSUBrST0 , X86::FSUBPrST0 }, + { X86::SUBR_FrST0, X86::SUBR_FPrST0 }, + { X86::SUB_FrST0 , X86::SUB_FPrST0 }, - { X86::FUCOMIr , X86::FUCOMIPr }, + { X86::UCOM_FIr , X86::UCOM_FIPr }, - { X86::FUCOMPr , X86::FUCOMPPr }, - { X86::FUCOMr , X86::FUCOMPr }, + { X86::UCOM_FPr , X86::UCOM_FPPr }, + { X86::UCOM_Fr , X86::UCOM_FPr }, }; /// popStackAfter - Pop the current value off of the top of the FP stack after @@ -474,10 +474,10 @@ int Opcode = Lookup(PopTable, ARRAY_SIZE(PopTable), I->getOpcode()); if (Opcode != -1) { I->setInstrDescriptor(TII->get(Opcode)); - if (Opcode == X86::FUCOMPPr) + if (Opcode == X86::UCOM_FPPr) I->RemoveOperand(0); } else { // Insert an explicit pop - I = BuildMI(*MBB, ++I, TII->get(X86::FSTPrr)).addReg(X86::ST0); + I = BuildMI(*MBB, ++I, TII->get(X86::ST_FPrr)).addReg(X86::ST0); } } @@ -501,7 +501,7 @@ RegMap[TopReg] = OldSlot; RegMap[FPRegNo] = ~0; Stack[--StackTop] = ~0; - I = BuildMI(*MBB, ++I, TII->get(X86::FSTPrr)).addReg(STReg); + I = BuildMI(*MBB, ++I, TII->get(X86::ST_FPrr)).addReg(STReg); } @@ -550,14 +550,14 @@ // Ditto FISTTP16m, FISTTP32m, FISTTP64m. // if (!KillsSrc && - (MI->getOpcode() == X86::FpIST64m32 || - MI->getOpcode() == X86::FpISTT16m32 || - MI->getOpcode() == X86::FpISTT32m32 || - MI->getOpcode() == X86::FpISTT64m32 || - MI->getOpcode() == X86::FpIST64m64 || - MI->getOpcode() == X86::FpISTT16m64 || - MI->getOpcode() == X86::FpISTT32m64 || - MI->getOpcode() == X86::FpISTT64m64)) { + (MI->getOpcode() == X86::IST_Fp64m32 || + MI->getOpcode() == X86::ISTT_Fp16m32 || + MI->getOpcode() == X86::ISTT_Fp32m32 || + MI->getOpcode() == X86::ISTT_Fp64m32 || + MI->getOpcode() == X86::IST_Fp64m64 || + MI->getOpcode() == X86::ISTT_Fp16m64 || + MI->getOpcode() == X86::ISTT_Fp32m64 || + MI->getOpcode() == X86::ISTT_Fp64m64)) { duplicateToTop(Reg, 7 /*temp register*/, I); } else { moveToTop(Reg, I); // Move to the top of the stack... @@ -567,10 +567,10 @@ MI->RemoveOperand(NumOps-1); // Remove explicit ST(0) operand MI->setInstrDescriptor(TII->get(getConcreteOpcode(MI->getOpcode()))); - if (MI->getOpcode() == X86::FISTP64m || - MI->getOpcode() == X86::FISTTP16m || - MI->getOpcode() == X86::FISTTP32m || - MI->getOpcode() == X86::FISTTP64m) { + if (MI->getOpcode() == X86::IST_FP64m || + MI->getOpcode() == X86::ISTT_FP16m || + MI->getOpcode() == X86::ISTT_FP32m || + MI->getOpcode() == X86::ISTT_FP64m) { assert(StackTop > 0 && "Stack empty??"); --StackTop; } else if (KillsSrc) { // Last use of operand? @@ -622,50 +622,50 @@ // ForwardST0Table - Map: A = B op C into: ST(0) = ST(0) op ST(i) static const TableEntry ForwardST0Table[] = { - { X86::FpADD32 , X86::FADDST0r }, - { X86::FpADD64 , X86::FADDST0r }, - { X86::FpDIV32 , X86::FDIVST0r }, - { X86::FpDIV64 , X86::FDIVST0r }, - { X86::FpMUL32 , X86::FMULST0r }, - { X86::FpMUL64 , X86::FMULST0r }, - { X86::FpSUB32 , X86::FSUBST0r }, - { X86::FpSUB64 , X86::FSUBST0r }, + { X86::ADD_Fp32 , X86::ADD_FST0r }, + { X86::ADD_Fp64 , X86::ADD_FST0r }, + { X86::DIV_Fp32 , X86::DIV_FST0r }, + { X86::DIV_Fp64 , X86::DIV_FST0r }, + { X86::MUL_Fp32 , X86::MUL_FST0r }, + { X86::MUL_Fp64 , X86::MUL_FST0r }, + { X86::SUB_Fp32 , X86::SUB_FST0r }, + { X86::SUB_Fp64 , X86::SUB_FST0r }, }; // ReverseST0Table - Map: A = B op C into: ST(0) = ST(i) op ST(0) static const TableEntry ReverseST0Table[] = { - { X86::FpADD32 , X86::FADDST0r }, // commutative - { X86::FpADD64 , X86::FADDST0r }, // commutative - { X86::FpDIV32 , X86::FDIVRST0r }, - { X86::FpDIV64 , X86::FDIVRST0r }, - { X86::FpMUL32 , X86::FMULST0r }, // commutative - { X86::FpMUL64 , X86::FMULST0r }, // commutative - { X86::FpSUB32 , X86::FSUBRST0r }, - { X86::FpSUB64 , X86::FSUBRST0r }, + { X86::ADD_Fp32 , X86::ADD_FST0r }, // commutative + { X86::ADD_Fp64 , X86::ADD_FST0r }, // commutative + { X86::DIV_Fp32 , X86::DIVR_FST0r }, + { X86::DIV_Fp64 , X86::DIVR_FST0r }, + { X86::MUL_Fp32 , X86::MUL_FST0r }, // commutative + { X86::MUL_Fp64 , X86::MUL_FST0r }, // commutative + { X86::SUB_Fp32 , X86::SUBR_FST0r }, + { X86::SUB_Fp64 , X86::SUBR_FST0r }, }; // ForwardSTiTable - Map: A = B op C into: ST(i) = ST(0) op ST(i) static const TableEntry ForwardSTiTable[] = { - { X86::FpADD32 , X86::FADDrST0 }, // commutative - { X86::FpADD64 , X86::FADDrST0 }, // commutative - { X86::FpDIV32 , X86::FDIVRrST0 }, - { X86::FpDIV64 , X86::FDIVRrST0 }, - { X86::FpMUL32 , X86::FMULrST0 }, // commutative - { X86::FpMUL64 , X86::FMULrST0 }, // commutative - { X86::FpSUB32 , X86::FSUBRrST0 }, - { X86::FpSUB64 , X86::FSUBRrST0 }, + { X86::ADD_Fp32 , X86::ADD_FrST0 }, // commutative + { X86::ADD_Fp64 , X86::ADD_FrST0 }, // commutative + { X86::DIV_Fp32 , X86::DIVR_FrST0 }, + { X86::DIV_Fp64 , X86::DIVR_FrST0 }, + { X86::MUL_Fp32 , X86::MUL_FrST0 }, // commutative + { X86::MUL_Fp64 , X86::MUL_FrST0 }, // commutative + { X86::SUB_Fp32 , X86::SUBR_FrST0 }, + { X86::SUB_Fp64 , X86::SUBR_FrST0 }, }; // ReverseSTiTable - Map: A = B op C into: ST(i) = ST(i) op ST(0) static const TableEntry ReverseSTiTable[] = { - { X86::FpADD32 , X86::FADDrST0 }, - { X86::FpADD64 , X86::FADDrST0 }, - { X86::FpDIV32 , X86::FDIVrST0 }, - { X86::FpDIV64 , X86::FDIVrST0 }, - { X86::FpMUL32 , X86::FMULrST0 }, - { X86::FpMUL64 , X86::FMULrST0 }, - { X86::FpSUB32 , X86::FSUBrST0 }, - { X86::FpSUB64 , X86::FSUBrST0 }, + { X86::ADD_Fp32 , X86::ADD_FrST0 }, + { X86::ADD_Fp64 , X86::ADD_FrST0 }, + { X86::DIV_Fp32 , X86::DIV_FrST0 }, + { X86::DIV_Fp64 , X86::DIV_FrST0 }, + { X86::MUL_Fp32 , X86::MUL_FrST0 }, + { X86::MUL_Fp64 , X86::MUL_FrST0 }, + { X86::SUB_Fp32 , X86::SUB_FrST0 }, + { X86::SUB_Fp64 , X86::SUB_FrST0 }, }; @@ -847,10 +847,10 @@ assert(StackTop == 1 && "Stack should have one element on it to return!"); --StackTop; // "Forget" we have something on the top of stack! break; - case X86::FpMOV3232: - case X86::FpMOV3264: - case X86::FpMOV6432: - case X86::FpMOV6464: { + case X86::MOV_Fp3232: + case X86::MOV_Fp3264: + case X86::MOV_Fp6432: + case X86::MOV_Fp6464: { unsigned SrcReg = getFPReg(MI->getOperand(1)); unsigned DestReg = getFPReg(MI->getOperand(0)); Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=37876&r1=37875&r2=37876&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Jul 4 16:07:47 2007 @@ -4468,12 +4468,12 @@ unsigned Opc; switch (MI->getOpcode()) { default: assert(0 && "illegal opcode!"); - case X86::FP32_TO_INT16_IN_MEM: Opc = X86::FpIST16m32; break; - case X86::FP32_TO_INT32_IN_MEM: Opc = X86::FpIST32m32; break; - case X86::FP32_TO_INT64_IN_MEM: Opc = X86::FpIST64m32; break; - case X86::FP64_TO_INT16_IN_MEM: Opc = X86::FpIST16m64; break; - case X86::FP64_TO_INT32_IN_MEM: Opc = X86::FpIST32m64; break; - case X86::FP64_TO_INT64_IN_MEM: Opc = X86::FpIST64m64; break; + case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break; + case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break; + case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break; + case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break; + case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break; + case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break; } X86AddressMode AM; Modified: llvm/trunk/lib/Target/X86/X86InstrFPStack.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFPStack.td?rev=37876&r1=37875&r2=37876&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrFPStack.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrFPStack.td Wed Jul 4 16:07:47 2007 @@ -66,8 +66,6 @@ return N->isExactlyValue(-1.0); }]>; -def extloadf64f32 : PatFrag<(ops node:$ptr), (f64 (extloadf32 node:$ptr))>; - // Some 'special' instructions let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler. def FP32_TO_INT16_IN_MEM : I<0, Pseudo, @@ -100,13 +98,20 @@ let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in def FP_REG_KILL : I<0, Pseudo, (ops), "#FP_REG_KILL", []>; -// All FP Stack operations are represented with two instructions here. The -// first instruction, generated by the instruction selector, uses "RFP" -// registers: a traditional register file to reference floating point values. -// These instructions are all psuedo instructions and use the "Fp" prefix. +// All FP Stack operations are represented with three instructions here. The +// first two instructions, generated by the instruction selector, uses "RFP32" +// or "RFP64" registers: traditional register files to reference 32-bit or +// 64-bit floating point values. These sizes apply to the values, not the +// registers, which are always 64 bits; RFP32 and RFP64 can be copied to +// each other without losing information. These instructions are all psuedo +// instructions and use the "_Fp" suffix. +// In some cases there are additional variants with a mixture of 32-bit and +// 64-bit registers. // The second instruction is defined with FPI, which is the actual instruction -// emitted by the assembler. The FP stackifier pass converts one to the other -// after register allocation occurs. +// emitted by the assembler. These use "RST" registers, although frequently +// the actual register(s) used are implicit. These are always 64-bits. +// The FP stackifier pass converts one to the other after register allocation +// occurs. // // Note that the FpI instruction should have instruction selection info (e.g. // a pattern) and the FPI instruction should have emission info (e.g. opcode @@ -141,29 +146,57 @@ FpI_, Requires<[FPStack]>; // Register copies. Just copies, the 64->32 version does not truncate. -def FpMOV3232 : FpI<(ops RFP32:$dst, RFP32:$src), SpecialFP, []>; // f1 = fmov f2 -def FpMOV3264 : FpI<(ops RFP64:$dst, RFP32:$src), SpecialFP, []>; // f1 = fmov f2 -def FpMOV6432 : FpI<(ops RFP32:$dst, RFP64:$src), SpecialFP, []>; // f1 = fmov f2 -def FpMOV6464 : FpI<(ops RFP64:$dst, RFP64:$src), SpecialFP, []>; // f1 = fmov f2 - -// Arithmetic -// Add, Sub, Mul, Div. -def FpADD32 : FpI<(ops RFP32:$dst, RFP32:$src1, RFP32:$src2), TwoArgFP, - [(set RFP32:$dst, (fadd RFP32:$src1, RFP32:$src2))]>; -def FpSUB32 : FpI<(ops RFP32:$dst, RFP32:$src1, RFP32:$src2), TwoArgFP, - [(set RFP32:$dst, (fsub RFP32:$src1, RFP32:$src2))]>; -def FpMUL32 : FpI<(ops RFP32:$dst, RFP32:$src1, RFP32:$src2), TwoArgFP, - [(set RFP32:$dst, (fmul RFP32:$src1, RFP32:$src2))]>; -def FpDIV32 : FpI<(ops RFP32:$dst, RFP32:$src1, RFP32:$src2), TwoArgFP, - [(set RFP32:$dst, (fdiv RFP32:$src1, RFP32:$src2))]>; -def FpADD64 : FpI<(ops RFP64:$dst, RFP64:$src1, RFP64:$src2), TwoArgFP, - [(set RFP64:$dst, (fadd RFP64:$src1, RFP64:$src2))]>; -def FpSUB64 : FpI<(ops RFP64:$dst, RFP64:$src1, RFP64:$src2), TwoArgFP, - [(set RFP64:$dst, (fsub RFP64:$src1, RFP64:$src2))]>; -def FpMUL64 : FpI<(ops RFP64:$dst, RFP64:$src1, RFP64:$src2), TwoArgFP, - [(set RFP64:$dst, (fmul RFP64:$src1, RFP64:$src2))]>; -def FpDIV64 : FpI<(ops RFP64:$dst, RFP64:$src1, RFP64:$src2), TwoArgFP, - [(set RFP64:$dst, (fdiv RFP64:$src1, RFP64:$src2))]>; +def MOV_Fp3232 : FpI<(ops RFP32:$dst, RFP32:$src), SpecialFP, []>; // f1 = fmov f2 +def MOV_Fp3264 : FpI<(ops RFP64:$dst, RFP32:$src), SpecialFP, []>; // f1 = fmov f2 +def MOV_Fp6432 : FpI<(ops RFP32:$dst, RFP64:$src), SpecialFP, []>; // f1 = fmov f2 +def MOV_Fp6464 : FpI<(ops RFP64:$dst, RFP64:$src), SpecialFP, []>; // f1 = fmov f2 + +// Factoring for arithmetic. +multiclass FPBinary_rr { +// Register op register -> register +// These are separated out because they have no reversed form. +def _Fp32 : FpI<(ops RFP32:$dst, RFP32:$src1, RFP32:$src2), TwoArgFP, + [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>; +def _Fp64 : FpI<(ops RFP64:$dst, RFP64:$src1, RFP64:$src2), TwoArgFP, + [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>; +} +// The FopST0 series are not included here because of the irregularities +// in where the 'r' goes in assembly output. +multiclass FPBinary { +// ST(0) = ST(0) + [mem] +def _Fp32m : FpI<(ops RFP32:$dst, RFP32:$src1, f32mem:$src2), OneArgFPRW, + [(set RFP32:$dst, (OpNode RFP32:$src1, (loadf32 addr:$src2)))]>; +def _Fp64m : FpI<(ops RFP64:$dst, RFP64:$src1, f64mem:$src2), OneArgFPRW, + [(set RFP64:$dst, (OpNode RFP64:$src1, (loadf64 addr:$src2)))]>; +def _F32m : FPI<0xD8, fp, (ops f32mem:$src), !strconcat("f", !strconcat(asmstring, "{s} $src"))>; +def _F64m : FPI<0xDC, fp, (ops f64mem:$src), !strconcat("f", !strconcat(asmstring, "{l} $src"))>; +// ST(0) = ST(0) + [memint] +def _FpI16m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i16mem:$src2), OneArgFPRW, + [(set RFP32:$dst, (OpNode RFP32:$src1, + (X86fild addr:$src2, i16)))]>; +def _FpI32m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i32mem:$src2), OneArgFPRW, + [(set RFP32:$dst, (OpNode RFP32:$src1, + (X86fild addr:$src2, i32)))]>; +def _FpI16m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i16mem:$src2), OneArgFPRW, + [(set RFP64:$dst, (OpNode RFP64:$src1, + (X86fild addr:$src2, i16)))]>; +def _FpI32m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i32mem:$src2), OneArgFPRW, + [(set RFP64:$dst, (OpNode RFP64:$src1, + (X86fild addr:$src2, i32)))]>; +def _FI16m : FPI<0xDE, fp, (ops i16mem:$src), !strconcat("fi", !strconcat(asmstring, "{s} $src"))>; +def _FI32m : FPI<0xDA, fp, (ops i32mem:$src), !strconcat("fi", !strconcat(asmstring, "{l} $src"))>; +} + +defm ADD : FPBinary_rr; +defm SUB : FPBinary_rr; +defm MUL : FPBinary_rr; +defm DIV : FPBinary_rr; +defm ADD : FPBinary; +defm SUB : FPBinary; +defm SUBR: FPBinary; +defm MUL : FPBinary; +defm DIV : FPBinary; +defm DIVR: FPBinary; class FPST0rInst o, string asm> : FPI, D8; @@ -172,416 +205,207 @@ class FPrST0PInst o, string asm> : FPI, DE; -// Binary Ops with a memory source. -def FpADD32m : FpI<(ops RFP32:$dst, RFP32:$src1, f32mem:$src2), OneArgFPRW, - [(set RFP32:$dst, (fadd RFP32:$src1, (loadf32 addr:$src2)))]>; - // ST(0) = ST(0) + [mem32] -def FpADD64m : FpI<(ops RFP64:$dst, RFP64:$src1, f64mem:$src2), OneArgFPRW, - [(set RFP64:$dst, (fadd RFP64:$src1, (loadf64 addr:$src2)))]>; - // ST(0) = ST(0) + [mem64] -def FpMUL32m : FpI<(ops RFP32:$dst, RFP32:$src1, f32mem:$src2), OneArgFPRW, - [(set RFP32:$dst, (fmul RFP32:$src1, (loadf32 addr:$src2)))]>; - // ST(0) = ST(0) * [mem32] -def FpMUL64m : FpI<(ops RFP64:$dst, RFP64:$src1, f64mem:$src2), OneArgFPRW, - [(set RFP64:$dst, (fmul RFP64:$src1, (loadf64 addr:$src2)))]>; - // ST(0) = ST(0) * [mem64] -def FpSUB32m : FpI<(ops RFP32:$dst, RFP32:$src1, f32mem:$src2), OneArgFPRW, - [(set RFP32:$dst, (fsub RFP32:$src1, (loadf32 addr:$src2)))]>; - // ST(0) = ST(0) - [mem32] -def FpSUB64m : FpI<(ops RFP64:$dst, RFP64:$src1, f64mem:$src2), OneArgFPRW, - [(set RFP64:$dst, (fsub RFP64:$src1, (loadf64 addr:$src2)))]>; - // ST(0) = ST(0) - [mem64] -def FpSUBR32m : FpI<(ops RFP32:$dst, RFP32:$src1, f32mem:$src2), OneArgFPRW, - [(set RFP32:$dst, (fsub (loadf32 addr:$src2), RFP32:$src1))]>; - // ST(0) = [mem32] - ST(0) -def FpSUBR64m : FpI<(ops RFP64:$dst, RFP64:$src1, f64mem:$src2), OneArgFPRW, - [(set RFP64:$dst, (fsub (loadf64 addr:$src2), RFP64:$src1))]>; - // ST(0) = [mem64] - ST(0) -def FpDIV32m : FpI<(ops RFP32:$dst, RFP32:$src1, f32mem:$src2), OneArgFPRW, - [(set RFP32:$dst, (fdiv RFP32:$src1, (loadf32 addr:$src2)))]>; - // ST(0) = ST(0) / [mem32] -def FpDIV64m : FpI<(ops RFP64:$dst, RFP64:$src1, f64mem:$src2), OneArgFPRW, - [(set RFP64:$dst, (fdiv RFP64:$src1, (loadf64 addr:$src2)))]>; - // ST(0) = ST(0) / [mem64] -def FpDIVR32m : FpI<(ops RFP32:$dst, RFP32:$src1, f32mem:$src2), OneArgFPRW, - [(set RFP32:$dst, (fdiv (loadf32 addr:$src2), RFP32:$src1))]>; - // ST(0) = [mem32] / ST(0) -def FpDIVR64m : FpI<(ops RFP64:$dst, RFP64:$src1, f64mem:$src2), OneArgFPRW, - [(set RFP64:$dst, (fdiv (loadf64 addr:$src2), RFP64:$src1))]>; - // ST(0) = [mem64] / ST(0) - - -def FADD32m : FPI<0xD8, MRM0m, (ops f32mem:$src), "fadd{s} $src">; -def FADD64m : FPI<0xDC, MRM0m, (ops f64mem:$src), "fadd{l} $src">; -def FMUL32m : FPI<0xD8, MRM1m, (ops f32mem:$src), "fmul{s} $src">; -def FMUL64m : FPI<0xDC, MRM1m, (ops f64mem:$src), "fmul{l} $src">; -def FSUB32m : FPI<0xD8, MRM4m, (ops f32mem:$src), "fsub{s} $src">; -def FSUB64m : FPI<0xDC, MRM4m, (ops f64mem:$src), "fsub{l} $src">; -def FSUBR32m : FPI<0xD8, MRM5m, (ops f32mem:$src), "fsubr{s} $src">; -def FSUBR64m : FPI<0xDC, MRM5m, (ops f64mem:$src), "fsubr{l} $src">; -def FDIV32m : FPI<0xD8, MRM6m, (ops f32mem:$src), "fdiv{s} $src">; -def FDIV64m : FPI<0xDC, MRM6m, (ops f64mem:$src), "fdiv{l} $src">; -def FDIVR32m : FPI<0xD8, MRM7m, (ops f32mem:$src), "fdivr{s} $src">; -def FDIVR64m : FPI<0xDC, MRM7m, (ops f64mem:$src), "fdivr{l} $src">; - -def FpIADD16m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i16mem:$src2), OneArgFPRW, - [(set RFP32:$dst, (fadd RFP32:$src1, - (X86fild addr:$src2, i16)))]>; - // ST(0) = ST(0) + [mem16int] -def FpIADD32m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i32mem:$src2), OneArgFPRW, - [(set RFP32:$dst, (fadd RFP32:$src1, - (X86fild addr:$src2, i32)))]>; - // ST(0) = ST(0) + [mem32int] -def FpIMUL16m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i16mem:$src2), OneArgFPRW, - [(set RFP32:$dst, (fmul RFP32:$src1, - (X86fild addr:$src2, i16)))]>; - // ST(0) = ST(0) * [mem16int] -def FpIMUL32m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i32mem:$src2), OneArgFPRW, - [(set RFP32:$dst, (fmul RFP32:$src1, - (X86fild addr:$src2, i32)))]>; - // ST(0) = ST(0) * [mem32int] -def FpISUB16m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i16mem:$src2), OneArgFPRW, - [(set RFP32:$dst, (fsub RFP32:$src1, - (X86fild addr:$src2, i16)))]>; - // ST(0) = ST(0) - [mem16int] -def FpISUB32m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i32mem:$src2), OneArgFPRW, - [(set RFP32:$dst, (fsub RFP32:$src1, - (X86fild addr:$src2, i32)))]>; - // ST(0) = ST(0) - [mem32int] -def FpISUBR16m32: FpI<(ops RFP32:$dst, RFP32:$src1, i16mem:$src2), OneArgFPRW, - [(set RFP32:$dst, (fsub (X86fild addr:$src2, i16), - RFP32:$src1))]>; - // ST(0) = [mem16int] - ST(0) -def FpISUBR32m32: FpI<(ops RFP32:$dst, RFP32:$src1, i32mem:$src2), OneArgFPRW, - [(set RFP32:$dst, (fsub (X86fild addr:$src2, i32), - RFP32:$src1))]>; - // ST(0) = [mem32int] - ST(0) -def FpIDIV16m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i16mem:$src2), OneArgFPRW, - [(set RFP32:$dst, (fdiv RFP32:$src1, - (X86fild addr:$src2, i16)))]>; - // ST(0) = ST(0) / [mem16int] -def FpIDIV32m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i32mem:$src2), OneArgFPRW, - [(set RFP32:$dst, (fdiv RFP32:$src1, - (X86fild addr:$src2, i32)))]>; - // ST(0) = ST(0) / [mem32int] -def FpIDIVR16m32: FpI<(ops RFP32:$dst, RFP32:$src1, i16mem:$src2), OneArgFPRW, - [(set RFP32:$dst, (fdiv (X86fild addr:$src2, i16), - RFP32:$src1))]>; - // ST(0) = [mem16int] / ST(0) -def FpIDIVR32m32: FpI<(ops RFP32:$dst, RFP32:$src1, i32mem:$src2), OneArgFPRW, - [(set RFP32:$dst, (fdiv (X86fild addr:$src2, i32), - RFP32:$src1))]>; - // ST(0) = [mem32int] / ST(0) - -def FpIADD16m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i16mem:$src2), OneArgFPRW, - [(set RFP64:$dst, (fadd RFP64:$src1, - (X86fild addr:$src2, i16)))]>; - // ST(0) = ST(0) + [mem16int] -def FpIADD32m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i32mem:$src2), OneArgFPRW, - [(set RFP64:$dst, (fadd RFP64:$src1, - (X86fild addr:$src2, i32)))]>; - // ST(0) = ST(0) + [mem32int] -def FpIMUL16m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i16mem:$src2), OneArgFPRW, - [(set RFP64:$dst, (fmul RFP64:$src1, - (X86fild addr:$src2, i16)))]>; - // ST(0) = ST(0) * [mem16int] -def FpIMUL32m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i32mem:$src2), OneArgFPRW, - [(set RFP64:$dst, (fmul RFP64:$src1, - (X86fild addr:$src2, i32)))]>; - // ST(0) = ST(0) * [mem32int] -def FpISUB16m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i16mem:$src2), OneArgFPRW, - [(set RFP64:$dst, (fsub RFP64:$src1, - (X86fild addr:$src2, i16)))]>; - // ST(0) = ST(0) - [mem16int] -def FpISUB32m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i32mem:$src2), OneArgFPRW, - [(set RFP64:$dst, (fsub RFP64:$src1, - (X86fild addr:$src2, i32)))]>; - // ST(0) = ST(0) - [mem32int] -def FpISUBR16m64: FpI<(ops RFP64:$dst, RFP64:$src1, i16mem:$src2), OneArgFPRW, - [(set RFP64:$dst, (fsub (X86fild addr:$src2, i16), - RFP64:$src1))]>; - // ST(0) = [mem16int] - ST(0) -def FpISUBR32m64: FpI<(ops RFP64:$dst, RFP64:$src1, i32mem:$src2), OneArgFPRW, - [(set RFP64:$dst, (fsub (X86fild addr:$src2, i32), - RFP64:$src1))]>; - // ST(0) = [mem32int] - ST(0) -def FpIDIV16m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i16mem:$src2), OneArgFPRW, - [(set RFP64:$dst, (fdiv RFP64:$src1, - (X86fild addr:$src2, i16)))]>; - // ST(0) = ST(0) / [mem16int] -def FpIDIV32m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i32mem:$src2), OneArgFPRW, - [(set RFP64:$dst, (fdiv RFP64:$src1, - (X86fild addr:$src2, i32)))]>; - // ST(0) = ST(0) / [mem32int] -def FpIDIVR16m64: FpI<(ops RFP64:$dst, RFP64:$src1, i16mem:$src2), OneArgFPRW, - [(set RFP64:$dst, (fdiv (X86fild addr:$src2, i16), - RFP64:$src1))]>; - // ST(0) = [mem16int] / ST(0) -def FpIDIVR32m64: FpI<(ops RFP64:$dst, RFP64:$src1, i32mem:$src2), OneArgFPRW, - [(set RFP64:$dst, (fdiv (X86fild addr:$src2, i32), - RFP64:$src1))]>; - // ST(0) = [mem32int] / ST(0) - -def FIADD16m : FPI<0xDE, MRM0m, (ops i16mem:$src), "fiadd{s} $src">; -def FIADD32m : FPI<0xDA, MRM0m, (ops i32mem:$src), "fiadd{l} $src">; -def FIMUL16m : FPI<0xDE, MRM1m, (ops i16mem:$src), "fimul{s} $src">; -def FIMUL32m : FPI<0xDA, MRM1m, (ops i32mem:$src), "fimul{l} $src">; -def FISUB16m : FPI<0xDE, MRM4m, (ops i16mem:$src), "fisub{s} $src">; -def FISUB32m : FPI<0xDA, MRM4m, (ops i32mem:$src), "fisub{l} $src">; -def FISUBR16m : FPI<0xDE, MRM5m, (ops i16mem:$src), "fisubr{s} $src">; -def FISUBR32m : FPI<0xDA, MRM5m, (ops i32mem:$src), "fisubr{l} $src">; -def FIDIV16m : FPI<0xDE, MRM6m, (ops i16mem:$src), "fidiv{s} $src">; -def FIDIV32m : FPI<0xDA, MRM6m, (ops i32mem:$src), "fidiv{l} $src">; -def FIDIVR16m : FPI<0xDE, MRM7m, (ops i16mem:$src), "fidivr{s} $src">; -def FIDIVR32m : FPI<0xDA, MRM7m, (ops i32mem:$src), "fidivr{l} $src">; - // NOTE: GAS and apparently all other AT&T style assemblers have a broken notion // of some of the 'reverse' forms of the fsub and fdiv instructions. As such, // we have to put some 'r's in and take them out of weird places. -def FADDST0r : FPST0rInst <0xC0, "fadd $op">; -def FADDrST0 : FPrST0Inst <0xC0, "fadd {%st(0), $op|$op, %ST(0)}">; -def FADDPrST0 : FPrST0PInst<0xC0, "faddp $op">; -def FSUBRST0r : FPST0rInst <0xE8, "fsubr $op">; -def FSUBrST0 : FPrST0Inst <0xE8, "fsub{r} {%st(0), $op|$op, %ST(0)}">; -def FSUBPrST0 : FPrST0PInst<0xE8, "fsub{r}p $op">; -def FSUBST0r : FPST0rInst <0xE0, "fsub $op">; -def FSUBRrST0 : FPrST0Inst <0xE0, "fsub{|r} {%st(0), $op|$op, %ST(0)}">; -def FSUBRPrST0 : FPrST0PInst<0xE0, "fsub{|r}p $op">; -def FMULST0r : FPST0rInst <0xC8, "fmul $op">; -def FMULrST0 : FPrST0Inst <0xC8, "fmul {%st(0), $op|$op, %ST(0)}">; -def FMULPrST0 : FPrST0PInst<0xC8, "fmulp $op">; -def FDIVRST0r : FPST0rInst <0xF8, "fdivr $op">; -def FDIVrST0 : FPrST0Inst <0xF8, "fdiv{r} {%st(0), $op|$op, %ST(0)}">; -def FDIVPrST0 : FPrST0PInst<0xF8, "fdiv{r}p $op">; -def FDIVST0r : FPST0rInst <0xF0, "fdiv $op">; -def FDIVRrST0 : FPrST0Inst <0xF0, "fdiv{|r} {%st(0), $op|$op, %ST(0)}">; -def FDIVRPrST0 : FPrST0PInst<0xF0, "fdiv{|r}p $op">; +def ADD_FST0r : FPST0rInst <0xC0, "fadd $op">; +def ADD_FrST0 : FPrST0Inst <0xC0, "fadd {%st(0), $op|$op, %ST(0)}">; +def ADD_FPrST0 : FPrST0PInst<0xC0, "faddp $op">; +def SUBR_FST0r : FPST0rInst <0xE8, "fsubr $op">; +def SUB_FrST0 : FPrST0Inst <0xE8, "fsub{r} {%st(0), $op|$op, %ST(0)}">; +def SUB_FPrST0 : FPrST0PInst<0xE8, "fsub{r}p $op">; +def SUB_FST0r : FPST0rInst <0xE0, "fsub $op">; +def SUBR_FrST0 : FPrST0Inst <0xE0, "fsub{|r} {%st(0), $op|$op, %ST(0)}">; +def SUBR_FPrST0 : FPrST0PInst<0xE0, "fsub{|r}p $op">; +def MUL_FST0r : FPST0rInst <0xC8, "fmul $op">; +def MUL_FrST0 : FPrST0Inst <0xC8, "fmul {%st(0), $op|$op, %ST(0)}">; +def MUL_FPrST0 : FPrST0PInst<0xC8, "fmulp $op">; +def DIVR_FST0r : FPST0rInst <0xF8, "fdivr $op">; +def DIV_FrST0 : FPrST0Inst <0xF8, "fdiv{r} {%st(0), $op|$op, %ST(0)}">; +def DIV_FPrST0 : FPrST0PInst<0xF8, "fdiv{r}p $op">; +def DIV_FST0r : FPST0rInst <0xF0, "fdiv $op">; +def DIVR_FrST0 : FPrST0Inst <0xF0, "fdiv{|r} {%st(0), $op|$op, %ST(0)}">; +def DIVR_FPrST0 : FPrST0PInst<0xF0, "fdiv{|r}p $op">; // Unary operations. -def FpCHS32 : FpI<(ops RFP32:$dst, RFP32:$src), OneArgFPRW, - [(set RFP32:$dst, (fneg RFP32:$src))]>; -def FpABS32 : FpI<(ops RFP32:$dst, RFP32:$src), OneArgFPRW, - [(set RFP32:$dst, (fabs RFP32:$src))]>; -def FpSQRT32 : FpI<(ops RFP32:$dst, RFP32:$src), OneArgFPRW, - [(set RFP32:$dst, (fsqrt RFP32:$src))]>; -def FpSIN32 : FpI<(ops RFP32:$dst, RFP32:$src), OneArgFPRW, - [(set RFP32:$dst, (fsin RFP32:$src))]>; -def FpCOS32 : FpI<(ops RFP32:$dst, RFP32:$src), OneArgFPRW, - [(set RFP32:$dst, (fcos RFP32:$src))]>; -def FpTST32 : FpI<(ops RFP32:$src), OneArgFP, - []>; - -def FpCHS64 : FpI<(ops RFP64:$dst, RFP64:$src), OneArgFPRW, - [(set RFP64:$dst, (fneg RFP64:$src))]>; -def FpABS64 : FpI<(ops RFP64:$dst, RFP64:$src), OneArgFPRW, - [(set RFP64:$dst, (fabs RFP64:$src))]>; -def FpSQRT64 : FpI<(ops RFP64:$dst, RFP64:$src), OneArgFPRW, - [(set RFP64:$dst, (fsqrt RFP64:$src))]>; -def FpSIN64 : FpI<(ops RFP64:$dst, RFP64:$src), OneArgFPRW, - [(set RFP64:$dst, (fsin RFP64:$src))]>; -def FpCOS64 : FpI<(ops RFP64:$dst, RFP64:$src), OneArgFPRW, - [(set RFP64:$dst, (fcos RFP64:$src))]>; -def FpTST64 : FpI<(ops RFP64:$src), OneArgFP, - []>; +multiclass FPUnary opcode, string asmstring> { +def _Fp32 : FpI<(ops RFP32:$dst, RFP32:$src), OneArgFPRW, + [(set RFP32:$dst, (OpNode RFP32:$src))]>; +def _Fp64 : FpI<(ops RFP64:$dst, RFP64:$src), OneArgFPRW, + [(set RFP64:$dst, (OpNode RFP64:$src))]>; +def _F : FPI, D9; +} -def FCHS : FPI<0xE0, RawFrm, (ops), "fchs">, D9; -def FABS : FPI<0xE1, RawFrm, (ops), "fabs">, D9; -def FSQRT : FPI<0xFA, RawFrm, (ops), "fsqrt">, D9; -def FSIN : FPI<0xFE, RawFrm, (ops), "fsin">, D9; -def FCOS : FPI<0xFF, RawFrm, (ops), "fcos">, D9; -def FTST : FPI<0xE4, RawFrm, (ops), "ftst">, D9; +defm CHS : FPUnary; +defm ABS : FPUnary; +defm SQRT: FPUnary; +defm SIN : FPUnary; +defm COS : FPUnary; +def TST_Fp32 : FpI<(ops RFP32:$src), OneArgFP, + []>; +def TST_Fp64 : FpI<(ops RFP64:$src), OneArgFP, + []>; +def TST_F : FPI<0xE4, RawFrm, (ops), "ftst">, D9; // Floating point cmovs. -let isTwoAddress = 1 in { - def FpCMOVB32 : FpI<(ops RFP32:$dst, RFP32:$src1, RFP32:$src2), CondMovFP, - [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, - X86_COND_B))]>; - def FpCMOVBE32 : FpI<(ops RFP32:$dst, RFP32:$src1, RFP32:$src2), CondMovFP, - [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, - X86_COND_BE))]>; - def FpCMOVE32 : FpI<(ops RFP32:$dst, RFP32:$src1, RFP32:$src2), CondMovFP, - [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, - X86_COND_E))]>; - def FpCMOVP32 : FpI<(ops RFP32:$dst, RFP32:$src1, RFP32:$src2), CondMovFP, - [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, - X86_COND_P))]>; - def FpCMOVNB32 : FpI<(ops RFP32:$dst, RFP32:$src1, RFP32:$src2), CondMovFP, - [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, - X86_COND_AE))]>; - def FpCMOVNBE32: FpI<(ops RFP32:$dst, RFP32:$src1, RFP32:$src2), CondMovFP, +multiclass FPCMov { + def _Fp32 : FpI<(ops RFP32:$dst, RFP32:$src1, RFP32:$src2), CondMovFP, [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, - X86_COND_A))]>; - def FpCMOVNE32 : FpI<(ops RFP32:$dst, RFP32:$src1, RFP32:$src2), CondMovFP, - [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, - X86_COND_NE))]>; - def FpCMOVNP32 : FpI<(ops RFP32:$dst, RFP32:$src1, RFP32:$src2), CondMovFP, - [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, - X86_COND_NP))]>; - - def FpCMOVB64 : FpI<(ops RFP64:$dst, RFP64:$src1, RFP64:$src2), CondMovFP, - [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, - X86_COND_B))]>; - def FpCMOVBE64 : FpI<(ops RFP64:$dst, RFP64:$src1, RFP64:$src2), CondMovFP, - [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, - X86_COND_BE))]>; - def FpCMOVE64 : FpI<(ops RFP64:$dst, RFP64:$src1, RFP64:$src2), CondMovFP, - [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, - X86_COND_E))]>; - def FpCMOVP64 : FpI<(ops RFP64:$dst, RFP64:$src1, RFP64:$src2), CondMovFP, + cc))]>; + def _Fp64 : FpI<(ops RFP64:$dst, RFP64:$src1, RFP64:$src2), CondMovFP, [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, - X86_COND_P))]>; - def FpCMOVNB64 : FpI<(ops RFP64:$dst, RFP64:$src1, RFP64:$src2), CondMovFP, - [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, - X86_COND_AE))]>; - def FpCMOVNBE64: FpI<(ops RFP64:$dst, RFP64:$src1, RFP64:$src2), CondMovFP, - [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, - X86_COND_A))]>; - def FpCMOVNE64 : FpI<(ops RFP64:$dst, RFP64:$src1, RFP64:$src2), CondMovFP, - [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, - X86_COND_NE))]>; - def FpCMOVNP64 : FpI<(ops RFP64:$dst, RFP64:$src1, RFP64:$src2), CondMovFP, - [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, - X86_COND_NP))]>; + cc))]>; +} +let isTwoAddress = 1 in { +defm CMOVB : FPCMov; +defm CMOVBE : FPCMov; +defm CMOVE : FPCMov; +defm CMOVP : FPCMov; +defm CMOVNB : FPCMov; +defm CMOVNBE: FPCMov; +defm CMOVNE : FPCMov; +defm CMOVNP : FPCMov; } -def FCMOVB : FPI<0xC0, AddRegFrm, (ops RST:$op), +// These are not factored because there's no clean way to pass DA/DB. +def CMOVB_F : FPI<0xC0, AddRegFrm, (ops RST:$op), "fcmovb {$op, %st(0)|%ST(0), $op}">, DA; -def FCMOVBE : FPI<0xD0, AddRegFrm, (ops RST:$op), +def CMOVBE_F : FPI<0xD0, AddRegFrm, (ops RST:$op), "fcmovbe {$op, %st(0)|%ST(0), $op}">, DA; -def FCMOVE : FPI<0xC8, AddRegFrm, (ops RST:$op), +def CMOVE_F : FPI<0xC8, AddRegFrm, (ops RST:$op), "fcmove {$op, %st(0)|%ST(0), $op}">, DA; -def FCMOVP : FPI<0xD8, AddRegFrm, (ops RST:$op), +def CMOVP_F : FPI<0xD8, AddRegFrm, (ops RST:$op), "fcmovu {$op, %st(0)|%ST(0), $op}">, DA; -def FCMOVNB : FPI<0xC0, AddRegFrm, (ops RST:$op), +def CMOVNB_F : FPI<0xC0, AddRegFrm, (ops RST:$op), "fcmovnb {$op, %st(0)|%ST(0), $op}">, DB; -def FCMOVNBE: FPI<0xD0, AddRegFrm, (ops RST:$op), +def CMOVNBE_F: FPI<0xD0, AddRegFrm, (ops RST:$op), "fcmovnbe {$op, %st(0)|%ST(0), $op}">, DB; -def FCMOVNE : FPI<0xC8, AddRegFrm, (ops RST:$op), +def CMOVNE_F : FPI<0xC8, AddRegFrm, (ops RST:$op), "fcmovne {$op, %st(0)|%ST(0), $op}">, DB; -def FCMOVNP : FPI<0xD8, AddRegFrm, (ops RST:$op), +def CMOVNP_F : FPI<0xD8, AddRegFrm, (ops RST:$op), "fcmovnu {$op, %st(0)|%ST(0), $op}">, DB; // Floating point loads & stores. -def FpLD32m : FpI<(ops RFP32:$dst, f32mem:$src), ZeroArgFP, +def LD_Fp32m : FpI<(ops RFP32:$dst, f32mem:$src), ZeroArgFP, [(set RFP32:$dst, (loadf32 addr:$src))]>; -def FpLD64m : FpI<(ops RFP64:$dst, f64mem:$src), ZeroArgFP, +def LD_Fp64m : FpI<(ops RFP64:$dst, f64mem:$src), ZeroArgFP, [(set RFP64:$dst, (loadf64 addr:$src))]>; -def FpILD16m32: FpI<(ops RFP32:$dst, i16mem:$src), ZeroArgFP, +def ILD_Fp16m32: FpI<(ops RFP32:$dst, i16mem:$src), ZeroArgFP, [(set RFP32:$dst, (X86fild addr:$src, i16))]>; -def FpILD32m32: FpI<(ops RFP32:$dst, i32mem:$src), ZeroArgFP, +def ILD_Fp32m32: FpI<(ops RFP32:$dst, i32mem:$src), ZeroArgFP, [(set RFP32:$dst, (X86fild addr:$src, i32))]>; -def FpILD64m32: FpI<(ops RFP32:$dst, i64mem:$src), ZeroArgFP, +def ILD_Fp64m32: FpI<(ops RFP32:$dst, i64mem:$src), ZeroArgFP, [(set RFP32:$dst, (X86fild addr:$src, i64))]>; -def FpILD16m64: FpI<(ops RFP64:$dst, i16mem:$src), ZeroArgFP, +def ILD_Fp16m64: FpI<(ops RFP64:$dst, i16mem:$src), ZeroArgFP, [(set RFP64:$dst, (X86fild addr:$src, i16))]>; -def FpILD32m64: FpI<(ops RFP64:$dst, i32mem:$src), ZeroArgFP, +def ILD_Fp32m64: FpI<(ops RFP64:$dst, i32mem:$src), ZeroArgFP, [(set RFP64:$dst, (X86fild addr:$src, i32))]>; -def FpILD64m64: FpI<(ops RFP64:$dst, i64mem:$src), ZeroArgFP, +def ILD_Fp64m64: FpI<(ops RFP64:$dst, i64mem:$src), ZeroArgFP, [(set RFP64:$dst, (X86fild addr:$src, i64))]>; -def FpST32m : FpI<(ops f32mem:$op, RFP32:$src), OneArgFP, +def ST_Fp32m : FpI<(ops f32mem:$op, RFP32:$src), OneArgFP, [(store RFP32:$src, addr:$op)]>; -def FpST64m32 : FpI<(ops f32mem:$op, RFP64:$src), OneArgFP, +def ST_Fp64m32 : FpI<(ops f32mem:$op, RFP64:$src), OneArgFP, [(truncstoref32 RFP64:$src, addr:$op)]>; -def FpST64m : FpI<(ops f64mem:$op, RFP64:$src), OneArgFP, +def ST_Fp64m : FpI<(ops f64mem:$op, RFP64:$src), OneArgFP, [(store RFP64:$src, addr:$op)]>; -def FpSTP32m : FpI<(ops f32mem:$op, RFP32:$src), OneArgFP, []>; -def FpSTP64m32 : FpI<(ops f32mem:$op, RFP64:$src), OneArgFP, []>; -def FpSTP64m : FpI<(ops f64mem:$op, RFP64:$src), OneArgFP, []>; -def FpIST16m32 : FpI<(ops i16mem:$op, RFP32:$src), OneArgFP, []>; -def FpIST32m32 : FpI<(ops i32mem:$op, RFP32:$src), OneArgFP, []>; -def FpIST64m32 : FpI<(ops i64mem:$op, RFP32:$src), OneArgFP, []>; -def FpIST16m64 : FpI<(ops i16mem:$op, RFP64:$src), OneArgFP, []>; -def FpIST32m64 : FpI<(ops i32mem:$op, RFP64:$src), OneArgFP, []>; -def FpIST64m64 : FpI<(ops i64mem:$op, RFP64:$src), OneArgFP, []>; - -def FLD32m : FPI<0xD9, MRM0m, (ops f32mem:$src), "fld{s} $src">; -def FLD64m : FPI<0xDD, MRM0m, (ops f64mem:$src), "fld{l} $src">; -def FILD16m : FPI<0xDF, MRM0m, (ops i16mem:$src), "fild{s} $src">; -def FILD32m : FPI<0xDB, MRM0m, (ops i32mem:$src), "fild{l} $src">; -def FILD64m : FPI<0xDF, MRM5m, (ops i64mem:$src), "fild{ll} $src">; -def FST32m : FPI<0xD9, MRM2m, (ops f32mem:$dst), "fst{s} $dst">; -def FST64m : FPI<0xDD, MRM2m, (ops f64mem:$dst), "fst{l} $dst">; -def FSTP32m : FPI<0xD9, MRM3m, (ops f32mem:$dst), "fstp{s} $dst">; -def FSTP64m : FPI<0xDD, MRM3m, (ops f64mem:$dst), "fstp{l} $dst">; -def FIST16m : FPI<0xDF, MRM2m, (ops i16mem:$dst), "fist{s} $dst">; -def FIST32m : FPI<0xDB, MRM2m, (ops i32mem:$dst), "fist{l} $dst">; -def FISTP16m : FPI<0xDF, MRM3m, (ops i16mem:$dst), "fistp{s} $dst">; -def FISTP32m : FPI<0xDB, MRM3m, (ops i32mem:$dst), "fistp{l} $dst">; -def FISTP64m : FPI<0xDF, MRM7m, (ops i64mem:$dst), "fistp{ll} $dst">; +def ST_FpP32m : FpI<(ops f32mem:$op, RFP32:$src), OneArgFP, []>; +def ST_FpP64m32 : FpI<(ops f32mem:$op, RFP64:$src), OneArgFP, []>; +def ST_FpP64m : FpI<(ops f64mem:$op, RFP64:$src), OneArgFP, []>; +def IST_Fp16m32 : FpI<(ops i16mem:$op, RFP32:$src), OneArgFP, []>; +def IST_Fp32m32 : FpI<(ops i32mem:$op, RFP32:$src), OneArgFP, []>; +def IST_Fp64m32 : FpI<(ops i64mem:$op, RFP32:$src), OneArgFP, []>; +def IST_Fp16m64 : FpI<(ops i16mem:$op, RFP64:$src), OneArgFP, []>; +def IST_Fp32m64 : FpI<(ops i32mem:$op, RFP64:$src), OneArgFP, []>; +def IST_Fp64m64 : FpI<(ops i64mem:$op, RFP64:$src), OneArgFP, []>; + +def LD_F32m : FPI<0xD9, MRM0m, (ops f32mem:$src), "fld{s} $src">; +def LD_F64m : FPI<0xDD, MRM0m, (ops f64mem:$src), "fld{l} $src">; +def ILD_F16m : FPI<0xDF, MRM0m, (ops i16mem:$src), "fild{s} $src">; +def ILD_F32m : FPI<0xDB, MRM0m, (ops i32mem:$src), "fild{l} $src">; +def ILD_F64m : FPI<0xDF, MRM5m, (ops i64mem:$src), "fild{ll} $src">; +def ST_F32m : FPI<0xD9, MRM2m, (ops f32mem:$dst), "fst{s} $dst">; +def ST_F64m : FPI<0xDD, MRM2m, (ops f64mem:$dst), "fst{l} $dst">; +def ST_FP32m : FPI<0xD9, MRM3m, (ops f32mem:$dst), "fstp{s} $dst">; +def ST_FP64m : FPI<0xDD, MRM3m, (ops f64mem:$dst), "fstp{l} $dst">; +def IST_F16m : FPI<0xDF, MRM2m, (ops i16mem:$dst), "fist{s} $dst">; +def IST_F32m : FPI<0xDB, MRM2m, (ops i32mem:$dst), "fist{l} $dst">; +def IST_FP16m : FPI<0xDF, MRM3m, (ops i16mem:$dst), "fistp{s} $dst">; +def IST_FP32m : FPI<0xDB, MRM3m, (ops i32mem:$dst), "fistp{l} $dst">; +def IST_FP64m : FPI<0xDF, MRM7m, (ops i64mem:$dst), "fistp{ll} $dst">; // FISTTP requires SSE3 even though it's a FPStack op. -def FpISTT16m32 : FpI_<(ops i16mem:$op, RFP32:$src), OneArgFP, +def ISTT_Fp16m32 : FpI_<(ops i16mem:$op, RFP32:$src), OneArgFP, [(X86fp_to_i16mem RFP32:$src, addr:$op)]>, Requires<[HasSSE3]>; -def FpISTT32m32 : FpI_<(ops i32mem:$op, RFP32:$src), OneArgFP, +def ISTT_Fp32m32 : FpI_<(ops i32mem:$op, RFP32:$src), OneArgFP, [(X86fp_to_i32mem RFP32:$src, addr:$op)]>, Requires<[HasSSE3]>; -def FpISTT64m32 : FpI_<(ops i64mem:$op, RFP32:$src), OneArgFP, +def ISTT_Fp64m32 : FpI_<(ops i64mem:$op, RFP32:$src), OneArgFP, [(X86fp_to_i64mem RFP32:$src, addr:$op)]>, Requires<[HasSSE3]>; -def FpISTT16m64 : FpI_<(ops i16mem:$op, RFP64:$src), OneArgFP, +def ISTT_Fp16m64 : FpI_<(ops i16mem:$op, RFP64:$src), OneArgFP, [(X86fp_to_i16mem RFP64:$src, addr:$op)]>, Requires<[HasSSE3]>; -def FpISTT32m64 : FpI_<(ops i32mem:$op, RFP64:$src), OneArgFP, +def ISTT_Fp32m64 : FpI_<(ops i32mem:$op, RFP64:$src), OneArgFP, [(X86fp_to_i32mem RFP64:$src, addr:$op)]>, Requires<[HasSSE3]>; -def FpISTT64m64 : FpI_<(ops i64mem:$op, RFP64:$src), OneArgFP, +def ISTT_Fp64m64 : FpI_<(ops i64mem:$op, RFP64:$src), OneArgFP, [(X86fp_to_i64mem RFP64:$src, addr:$op)]>, Requires<[HasSSE3]>; -def FISTTP16m : FPI<0xDF, MRM1m, (ops i16mem:$dst), "fisttp{s} $dst">; -def FISTTP32m : FPI<0xDB, MRM1m, (ops i32mem:$dst), "fisttp{l} $dst">; -def FISTTP64m : FPI<0xDD, MRM1m, (ops i64mem:$dst), "fisttp{ll} $dst">; +def ISTT_FP16m : FPI<0xDF, MRM1m, (ops i16mem:$dst), "fisttp{s} $dst">; +def ISTT_FP32m : FPI<0xDB, MRM1m, (ops i32mem:$dst), "fisttp{l} $dst">; +def ISTT_FP64m : FPI<0xDD, MRM1m, (ops i64mem:$dst), "fisttp{ll} $dst">; // FP Stack manipulation instructions. -def FLDrr : FPI<0xC0, AddRegFrm, (ops RST:$op), "fld $op">, D9; -def FSTrr : FPI<0xD0, AddRegFrm, (ops RST:$op), "fst $op">, DD; -def FSTPrr : FPI<0xD8, AddRegFrm, (ops RST:$op), "fstp $op">, DD; -def FXCH : FPI<0xC8, AddRegFrm, (ops RST:$op), "fxch $op">, D9; +def LD_Frr : FPI<0xC0, AddRegFrm, (ops RST:$op), "fld $op">, D9; +def ST_Frr : FPI<0xD0, AddRegFrm, (ops RST:$op), "fst $op">, DD; +def ST_FPrr : FPI<0xD8, AddRegFrm, (ops RST:$op), "fstp $op">, DD; +def XCH_F : FPI<0xC8, AddRegFrm, (ops RST:$op), "fxch $op">, D9; // Floating point constant loads. let isReMaterializable = 1 in { -def FpLD032 : FpI<(ops RFP32:$dst), ZeroArgFP, +def LD_Fp032 : FpI<(ops RFP32:$dst), ZeroArgFP, [(set RFP32:$dst, fpimm0)]>; -def FpLD132 : FpI<(ops RFP32:$dst), ZeroArgFP, +def LD_Fp132 : FpI<(ops RFP32:$dst), ZeroArgFP, [(set RFP32:$dst, fpimm1)]>; -def FpLD064 : FpI<(ops RFP64:$dst), ZeroArgFP, +def LD_Fp064 : FpI<(ops RFP64:$dst), ZeroArgFP, [(set RFP64:$dst, fpimm0)]>; -def FpLD164 : FpI<(ops RFP64:$dst), ZeroArgFP, +def LD_Fp164 : FpI<(ops RFP64:$dst), ZeroArgFP, [(set RFP64:$dst, fpimm1)]>; } -def FLD0 : FPI<0xEE, RawFrm, (ops), "fldz">, D9; -def FLD1 : FPI<0xE8, RawFrm, (ops), "fld1">, D9; +def LD_F0 : FPI<0xEE, RawFrm, (ops), "fldz">, D9; +def LD_F1 : FPI<0xE8, RawFrm, (ops), "fld1">, D9; // Floating point compares. -def FpUCOMr32 : FpI<(ops RFP32:$lhs, RFP32:$rhs), CompareFP, +def UCOM_Fpr32 : FpI<(ops RFP32:$lhs, RFP32:$rhs), CompareFP, []>; // FPSW = cmp ST(0) with ST(i) -def FpUCOMIr32: FpI<(ops RFP32:$lhs, RFP32:$rhs), CompareFP, +def UCOM_FpIr32: FpI<(ops RFP32:$lhs, RFP32:$rhs), CompareFP, [(X86cmp RFP32:$lhs, RFP32:$rhs)]>; // CC = cmp ST(0) with ST(i) -def FpUCOMr64 : FpI<(ops RFP64:$lhs, RFP64:$rhs), CompareFP, +def UCOM_Fpr64 : FpI<(ops RFP64:$lhs, RFP64:$rhs), CompareFP, []>; // FPSW = cmp ST(0) with ST(i) -def FpUCOMIr64: FpI<(ops RFP64:$lhs, RFP64:$rhs), CompareFP, +def UCOM_FpIr64: FpI<(ops RFP64:$lhs, RFP64:$rhs), CompareFP, [(X86cmp RFP64:$lhs, RFP64:$rhs)]>; // CC = cmp ST(0) with ST(i) -def FUCOMr : FPI<0xE0, AddRegFrm, // FPSW = cmp ST(0) with ST(i) +def UCOM_Fr : FPI<0xE0, AddRegFrm, // FPSW = cmp ST(0) with ST(i) (ops RST:$reg), "fucom $reg">, DD, Imp<[ST0],[]>; -def FUCOMPr : FPI<0xE8, AddRegFrm, // FPSW = cmp ST(0) with ST(i), pop +def UCOM_FPr : FPI<0xE8, AddRegFrm, // FPSW = cmp ST(0) with ST(i), pop (ops RST:$reg), "fucomp $reg">, DD, Imp<[ST0],[]>; -def FUCOMPPr : FPI<0xE9, RawFrm, // cmp ST(0) with ST(1), pop, pop +def UCOM_FPPr : FPI<0xE9, RawFrm, // cmp ST(0) with ST(1), pop, pop (ops), "fucompp">, DA, Imp<[ST0],[]>; -def FUCOMIr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i) +def UCOM_FIr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i) (ops RST:$reg), "fucomi {$reg, %st(0)|%ST(0), $reg}">, DB, Imp<[ST0],[]>; -def FUCOMIPr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop +def UCOM_FIPr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop (ops RST:$reg), "fucomip {$reg, %st(0)|%ST(0), $reg}">, DF, Imp<[ST0],[]>; @@ -599,22 +423,22 @@ //===----------------------------------------------------------------------===// // Required for RET of f32 / f64 values. -def : Pat<(X86fld addr:$src, f32), (FpLD32m addr:$src)>; -def : Pat<(X86fld addr:$src, f64), (FpLD64m addr:$src)>; +def : Pat<(X86fld addr:$src, f32), (LD_Fp32m addr:$src)>; +def : Pat<(X86fld addr:$src, f64), (LD_Fp64m addr:$src)>; // Required for CALL which return f32 / f64 values. -def : Pat<(X86fst RFP32:$src, addr:$op, f32), (FpST32m addr:$op, RFP32:$src)>; -def : Pat<(X86fst RFP64:$src, addr:$op, f32), (FpST64m32 addr:$op, RFP64:$src)>; -def : Pat<(X86fst RFP64:$src, addr:$op, f64), (FpST64m addr:$op, RFP64:$src)>; +def : Pat<(X86fst RFP32:$src, addr:$op, f32), (ST_Fp32m addr:$op, RFP32:$src)>; +def : Pat<(X86fst RFP64:$src, addr:$op, f32), (ST_Fp64m32 addr:$op, RFP64:$src)>; +def : Pat<(X86fst RFP64:$src, addr:$op, f64), (ST_Fp64m addr:$op, RFP64:$src)>; // Floating point constant -0.0 and -1.0 -def : Pat<(f32 fpimmneg0), (FpCHS32 (FpLD032))>, Requires<[FPStack]>; -def : Pat<(f32 fpimmneg1), (FpCHS32 (FpLD132))>, Requires<[FPStack]>; -def : Pat<(f64 fpimmneg0), (FpCHS64 (FpLD064))>, Requires<[FPStack]>; -def : Pat<(f64 fpimmneg1), (FpCHS64 (FpLD164))>, Requires<[FPStack]>; +def : Pat<(f32 fpimmneg0), (CHS_Fp32 (LD_Fp032))>, Requires<[FPStack]>; +def : Pat<(f32 fpimmneg1), (CHS_Fp32 (LD_Fp132))>, Requires<[FPStack]>; +def : Pat<(f64 fpimmneg0), (CHS_Fp64 (LD_Fp064))>, Requires<[FPStack]>; +def : Pat<(f64 fpimmneg1), (CHS_Fp64 (LD_Fp164))>, Requires<[FPStack]>; // Used to conv. i64 to f64 since there isn't a SSE version. -def : Pat<(X86fildflag addr:$src, i64), (FpILD64m64 addr:$src)>; +def : Pat<(X86fildflag addr:$src, i64), (ILD_Fp64m64 addr:$src)>; -def : Pat<(extloadf32 addr:$src), (FpMOV3264 (FpLD32m addr:$src))>, Requires<[FPStack]>; -def : Pat<(fextend RFP32:$src), (FpMOV3264 RFP32:$src)>, Requires<[FPStack]>; +def : Pat<(extloadf32 addr:$src), (MOV_Fp3264 (LD_Fp32m addr:$src))>, Requires<[FPStack]>; +def : Pat<(fextend RFP32:$src), (MOV_Fp3264 RFP32:$src)>, Requires<[FPStack]>; Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=37876&r1=37875&r2=37876&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Wed Jul 4 16:07:47 2007 @@ -33,8 +33,8 @@ if (oc == X86::MOV8rr || oc == X86::MOV16rr || oc == X86::MOV32rr || oc == X86::MOV64rr || oc == X86::MOV16to16_ || oc == X86::MOV32to32_ || - oc == X86::FpMOV3232 || oc == X86::MOVSSrr || oc == X86::MOVSDrr || - oc == X86::FpMOV3264 || oc == X86::FpMOV6432 || oc == X86::FpMOV6464 || + oc == X86::MOV_Fp3232 || oc == X86::MOVSSrr || oc == X86::MOVSDrr || + oc == X86::MOV_Fp3264 || oc == X86::MOV_Fp6432 || oc == X86::MOV_Fp6464 || oc == X86::FsMOVAPSrr || oc == X86::FsMOVAPDrr || oc == X86::MOVAPSrr || oc == X86::MOVAPDrr || oc == X86::MOVSS2PSrr || oc == X86::MOVSD2PDrr || @@ -61,7 +61,7 @@ case X86::MOV32rm: case X86::MOV32_rm: case X86::MOV64rm: - case X86::FpLD64m: + case X86::LD_Fp64m: case X86::MOVSSrm: case X86::MOVSDrm: case X86::MOVAPSrm: @@ -91,7 +91,7 @@ case X86::MOV32mr: case X86::MOV32_mr: case X86::MOV64mr: - case X86::FpSTP64m: + case X86::ST_FpP64m: case X86::MOVSSmr: case X86::MOVSDmr: case X86::MOVAPSmr: @@ -122,7 +122,7 @@ case X86::MOV32rm: case X86::MOV32_rm: case X86::MOV64rm: - case X86::FpLD64m: + case X86::LD_Fp64m: case X86::MOVSSrm: case X86::MOVSDrm: case X86::MOVAPSrm: Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=37876&r1=37875&r2=37876&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Wed Jul 4 16:07:47 2007 @@ -83,9 +83,9 @@ } else if (RC == &X86::GR16_RegClass) { Opc = X86::MOV16_mr; } else if (RC == &X86::RFP64RegClass || RC == &X86::RSTRegClass) { - Opc = X86::FpST64m; + Opc = X86::ST_Fp64m; } else if (RC == &X86::RFP32RegClass) { - Opc = X86::FpST32m; + Opc = X86::ST_Fp32m; } else if (RC == &X86::FR32RegClass) { Opc = X86::MOVSSmr; } else if (RC == &X86::FR64RegClass) { @@ -120,9 +120,9 @@ } else if (RC == &X86::GR16_RegClass) { Opc = X86::MOV16_rm; } else if (RC == &X86::RFP64RegClass || RC == &X86::RSTRegClass) { - Opc = X86::FpLD64m; + Opc = X86::LD_Fp64m; } else if (RC == &X86::RFP32RegClass) { - Opc = X86::FpLD32m; + Opc = X86::LD_Fp32m; } else if (RC == &X86::FR32RegClass) { Opc = X86::MOVSSrm; } else if (RC == &X86::FR64RegClass) { @@ -156,9 +156,9 @@ } else if (RC == &X86::GR16_RegClass) { Opc = X86::MOV16_rr; } else if (RC == &X86::RFP32RegClass) { - Opc = X86::FpMOV3232; + Opc = X86::MOV_Fp3232; } else if (RC == &X86::RFP64RegClass || RC == &X86::RSTRegClass) { - Opc = X86::FpMOV6464; + Opc = X86::MOV_Fp6464; } else if (RC == &X86::FR32RegClass) { Opc = X86::FsMOVAPSrr; } else if (RC == &X86::FR64RegClass) { From ggreif at gmail.com Wed Jul 4 16:55:50 2007 From: ggreif at gmail.com (Gabor Greif) Date: Wed, 04 Jul 2007 21:55:50 -0000 Subject: [llvm-commits] [llvm] r37877 - in /llvm/trunk/tools: bugpoint/ llvm-bcanalyzer/ Message-ID: <200707042155.l64Ltpam008699@zion.cs.uiuc.edu> Author: ggreif Date: Wed Jul 4 16:55:50 2007 New Revision: 37877 URL: http://llvm.org/viewvc/llvm-project?rev=37877&view=rev Log: Pretty straightforward replacement of "bytecode" by "bitcode" performed on tools/ first, in order not to cause lethal damage Modified: llvm/trunk/tools/bugpoint/BugDriver.cpp llvm/trunk/tools/bugpoint/BugDriver.h llvm/trunk/tools/bugpoint/CrashDebugger.cpp llvm/trunk/tools/bugpoint/ExecutionDriver.cpp llvm/trunk/tools/bugpoint/ExtractFunction.cpp llvm/trunk/tools/bugpoint/Miscompilation.cpp llvm/trunk/tools/bugpoint/OptimizerDriver.cpp llvm/trunk/tools/bugpoint/ToolRunner.cpp llvm/trunk/tools/bugpoint/ToolRunner.h llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp Modified: llvm/trunk/tools/bugpoint/BugDriver.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/bugpoint/BugDriver.cpp?rev=37877&r1=37876&r2=37877&view=diff ============================================================================== --- llvm/trunk/tools/bugpoint/BugDriver.cpp (original) +++ llvm/trunk/tools/bugpoint/BugDriver.cpp Wed Jul 4 16:55:50 2007 @@ -69,7 +69,7 @@ run_find_bugs(find_bugs), Timeout(timeout), MemoryLimit(memlimit) {} -/// ParseInputFile - Given a bytecode or assembly input filename, parse and +/// ParseInputFile - Given a bitcode or assembly input filename, parse and /// return it, or return null if not possible. /// Module *llvm::ParseInputFile(const std::string &Filename) { @@ -88,8 +88,8 @@ } // This method takes the specified list of LLVM input files, attempts to load -// them, either as assembly or bytecode, then link them together. It returns -// true on failure (if, for example, an input bytecode file could not be +// them, either as assembly or bitcode, then link them together. It returns +// true on failure (if, for example, an input bitcode file could not be // parsed), and false on success. // bool BugDriver::addSources(const std::vector &Filenames) { @@ -153,7 +153,7 @@ // determine what the problem is. Does the optimization series crash the // compiler, or does it produce illegal code? We make the top-level // decision by trying to run all of the passes on the the input program, - // which should generate a bytecode file. If it does generate a bytecode + // which should generate a bitcode file. If it does generate a bitcode // file, then we know the compiler didn't crash, so try to diagnose a // miscompilation. if (!PassesToRun.empty()) { @@ -162,7 +162,7 @@ return debugOptimizerCrash(); } - // Set up the execution environment, selecting a method to run LLVM bytecode. + // Set up the execution environment, selecting a method to run LLVM bitcode. if (initializeExecutionEnvironment()) return true; // Test to see if we have a code generator crash. Modified: llvm/trunk/tools/bugpoint/BugDriver.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/bugpoint/BugDriver.h?rev=37877&r1=37876&r2=37877&view=diff ============================================================================== --- llvm/trunk/tools/bugpoint/BugDriver.h (original) +++ llvm/trunk/tools/bugpoint/BugDriver.h Wed Jul 4 16:55:50 2007 @@ -107,9 +107,9 @@ const std::string &ReferenceOutput); /// compileSharedObject - This method creates a SharedObject from a given - /// BytecodeFile for debugging a code generator. + /// BitcodeFile for debugging a code generator. /// - std::string compileSharedObject(const std::string &BytecodeFile); + std::string compileSharedObject(const std::string &BitcodeFile); /// debugCodeGenerator - This method narrows down a module to a function or /// set of functions, using the CBE as a ``safe'' code generator for other @@ -167,7 +167,7 @@ /// generator (e.g., llc crashes), this will throw an exception. /// std::string executeProgram(std::string RequestedOutputFilename = "", - std::string Bytecode = "", + std::string Bitcode = "", const std::string &SharedObjects = "", AbstractInterpreter *AI = 0, bool *ProgramExitedNonzero = 0); @@ -191,14 +191,14 @@ /// is different, true is returned. If there is a problem with the code /// generator (e.g., llc crashes), this will throw an exception. /// - bool diffProgram(const std::string &BytecodeFile = "", + bool diffProgram(const std::string &BitcodeFile = "", const std::string &SharedObj = "", - bool RemoveBytecode = false); + bool RemoveBitcode = false); - /// EmitProgressBytecode - This function is used to output the current Program + /// EmitProgressBitcode - This function is used to output the current Program /// to a file named "bugpoint-ID.bc". /// - void EmitProgressBytecode(const std::string &ID, bool NoFlyer = false); + void EmitProgressBitcode(const std::string &ID, bool NoFlyer = false); /// deleteInstructionFromProgram - This method clones the current Program and /// deletes the specified instruction from the cloned module. It then runs a @@ -236,10 +236,10 @@ Module *runPassesOn(Module *M, const std::vector &Passes, bool AutoDebugCrashes = false); - /// runPasses - Run the specified passes on Program, outputting a bytecode + /// runPasses - Run the specified passes on Program, outputting a bitcode /// file and writting the filename into OutputFile if successful. If the /// optimizations fail for some reason (optimizer crashes), return true, - /// otherwise return false. If DeleteOutput is set to true, the bytecode is + /// otherwise return false. If DeleteOutput is set to true, the bitcode is /// deleted on success, and the filename string is undefined. This prints to /// cout a single line message indicating whether compilation was successful /// or failed, unless Quiet is set. @@ -258,7 +258,7 @@ bool runManyPasses(const std::vector &AllPasses); /// writeProgramToFile - This writes the current "Program" to the named - /// bytecode file. If an error occurs, true is returned. + /// bitcode file. If an error occurs, true is returned. /// bool writeProgramToFile(const std::string &Filename, Module *M = 0) const; @@ -282,7 +282,7 @@ bool initializeExecutionEnvironment(); }; -/// ParseInputFile - Given a bytecode or assembly input filename, parse and +/// ParseInputFile - Given a bitcode or assembly input filename, parse and /// return it, or return null if not possible. /// Module *ParseInputFile(const std::string &InputFilename); Modified: llvm/trunk/tools/bugpoint/CrashDebugger.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/bugpoint/CrashDebugger.cpp?rev=37877&r1=37876&r2=37877&view=diff ============================================================================== --- llvm/trunk/tools/bugpoint/CrashDebugger.cpp (original) +++ llvm/trunk/tools/bugpoint/CrashDebugger.cpp Wed Jul 4 16:55:50 2007 @@ -70,7 +70,7 @@ BD.Program = ParseInputFile(PrefixOutput.toString()); if (BD.Program == 0) { - std::cerr << BD.getToolName() << ": Error reading bytecode file '" + std::cerr << BD.getToolName() << ": Error reading bitcode file '" << PrefixOutput << "'!\n"; exit(1); } @@ -396,7 +396,7 @@ ReduceCrashingGlobalVariables(BD, TestFn).reduceList(GVs); if (GVs.size() < OldSize) - BD.EmitProgressBytecode("reduced-global-variables"); + BD.EmitProgressBitcode("reduced-global-variables"); } } } @@ -417,7 +417,7 @@ ReduceCrashingFunctions(BD, TestFn).reduceList(Functions); if (Functions.size() < OldSize) - BD.EmitProgressBytecode("reduced-function"); + BD.EmitProgressBitcode("reduced-function"); } // Attempt to delete entire basic blocks at a time to speed up @@ -508,7 +508,7 @@ } } - BD.EmitProgressBytecode("reduced-simplified"); + BD.EmitProgressBitcode("reduced-simplified"); return false; } @@ -532,7 +532,7 @@ << (PassesToRun.size() == 1 ? ": " : "es: ") << getPassesString(PassesToRun) << '\n'; - EmitProgressBytecode(ID); + EmitProgressBitcode(ID); return DebugACrash(*this, TestForOptimizerCrash); } Modified: llvm/trunk/tools/bugpoint/ExecutionDriver.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/bugpoint/ExecutionDriver.cpp?rev=37877&r1=37876&r2=37877&view=diff ============================================================================== --- llvm/trunk/tools/bugpoint/ExecutionDriver.cpp (original) +++ llvm/trunk/tools/bugpoint/ExecutionDriver.cpp Wed Jul 4 16:55:50 2007 @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // // This file contains code used to execute the program utilizing one of the -// various ways of running LLVM bytecode. +// various ways of running LLVM bitcode. // //===----------------------------------------------------------------------===// @@ -181,25 +181,25 @@ /// generation crash testing. /// void BugDriver::compileProgram(Module *M) { - // Emit the program to a bytecode file... - sys::Path BytecodeFile ("bugpoint-test-program.bc"); + // Emit the program to a bitcode file... + sys::Path BitcodeFile ("bugpoint-test-program.bc"); std::string ErrMsg; - if (BytecodeFile.makeUnique(true,&ErrMsg)) { + if (BitcodeFile.makeUnique(true,&ErrMsg)) { std::cerr << ToolName << ": Error making unique filename: " << ErrMsg << "\n"; exit(1); } - if (writeProgramToFile(BytecodeFile.toString(), M)) { - std::cerr << ToolName << ": Error emitting bytecode to file '" - << BytecodeFile << "'!\n"; + if (writeProgramToFile(BitcodeFile.toString(), M)) { + std::cerr << ToolName << ": Error emitting bitcode to file '" + << BitcodeFile << "'!\n"; exit(1); } - // Remove the temporary bytecode file when we are done. - FileRemover BytecodeFileRemover(BytecodeFile); + // Remove the temporary bitcode file when we are done. + FileRemover BitcodeFileRemover(BitcodeFile); // Actually compile the program! - Interpreter->compileProgram(BytecodeFile.toString()); + Interpreter->compileProgram(BitcodeFile.toString()); } @@ -208,35 +208,35 @@ /// filename may be optionally specified. /// std::string BugDriver::executeProgram(std::string OutputFile, - std::string BytecodeFile, + std::string BitcodeFile, const std::string &SharedObj, AbstractInterpreter *AI, bool *ProgramExitedNonzero) { if (AI == 0) AI = Interpreter; assert(AI && "Interpreter should have been created already!"); - bool CreatedBytecode = false; + bool CreatedBitcode = false; std::string ErrMsg; - if (BytecodeFile.empty()) { - // Emit the program to a bytecode file... + if (BitcodeFile.empty()) { + // Emit the program to a bitcode file... sys::Path uniqueFilename("bugpoint-test-program.bc"); if (uniqueFilename.makeUnique(true, &ErrMsg)) { std::cerr << ToolName << ": Error making unique filename: " << ErrMsg << "!\n"; exit(1); } - BytecodeFile = uniqueFilename.toString(); + BitcodeFile = uniqueFilename.toString(); - if (writeProgramToFile(BytecodeFile, Program)) { - std::cerr << ToolName << ": Error emitting bytecode to file '" - << BytecodeFile << "'!\n"; + if (writeProgramToFile(BitcodeFile, Program)) { + std::cerr << ToolName << ": Error emitting bitcode to file '" + << BitcodeFile << "'!\n"; exit(1); } - CreatedBytecode = true; + CreatedBitcode = true; } - // Remove the temporary bytecode file when we are done. - sys::Path BytecodePath (BytecodeFile); - FileRemover BytecodeFileRemover(BytecodePath, CreatedBytecode); + // Remove the temporary bitcode file when we are done. + sys::Path BitcodePath (BitcodeFile); + FileRemover BitcodeFileRemover(BitcodePath, CreatedBitcode); if (OutputFile.empty()) OutputFile = "bugpoint-execution-output"; @@ -261,11 +261,11 @@ int RetVal = 0; if (InterpreterSel == RunLLC || InterpreterSel == RunCBE || InterpreterSel == CBE_bug || InterpreterSel == LLC_Safe) - RetVal = AI->ExecuteProgram(BytecodeFile, InputArgv, InputFile, + RetVal = AI->ExecuteProgram(BitcodeFile, InputArgv, InputFile, OutputFile, AdditionalLinkerArgs, SharedObjs, Timeout, MemoryLimit); else - RetVal = AI->ExecuteProgram(BytecodeFile, InputArgv, InputFile, + RetVal = AI->ExecuteProgram(BitcodeFile, InputArgv, InputFile, OutputFile, std::vector(), SharedObjs, Timeout, MemoryLimit); @@ -311,12 +311,12 @@ return outFN; } -std::string BugDriver::compileSharedObject(const std::string &BytecodeFile) { +std::string BugDriver::compileSharedObject(const std::string &BitcodeFile) { assert(Interpreter && "Interpreter should have been created already!"); sys::Path OutputFile; // Using CBE - GCC::FileType FT = cbe->OutputCode(BytecodeFile, OutputFile); + GCC::FileType FT = cbe->OutputCode(BitcodeFile, OutputFile); std::string SharedObjectFile; if (gcc->MakeSharedObject(OutputFile.toString(), FT, @@ -360,20 +360,20 @@ /// is different, true is returned. If there is a problem with the code /// generator (e.g., llc crashes), this will throw an exception. /// -bool BugDriver::diffProgram(const std::string &BytecodeFile, +bool BugDriver::diffProgram(const std::string &BitcodeFile, const std::string &SharedObject, - bool RemoveBytecode) { + bool RemoveBitcode) { bool ProgramExitedNonzero; // Execute the program, generating an output file... - sys::Path Output(executeProgram("", BytecodeFile, SharedObject, 0, + sys::Path Output(executeProgram("", BitcodeFile, SharedObject, 0, &ProgramExitedNonzero)); // If we're checking the program exit code, assume anything nonzero is bad. if (CheckProgramExitCode && ProgramExitedNonzero) { Output.eraseFromDisk(); - if (RemoveBytecode) - sys::Path(BytecodeFile).eraseFromDisk(); + if (RemoveBitcode) + sys::Path(BitcodeFile).eraseFromDisk(); return true; } @@ -392,9 +392,9 @@ // Remove the generated output. Output.eraseFromDisk(); - // Remove the bytecode file if we are supposed to. - if (RemoveBytecode) - sys::Path(BytecodeFile).eraseFromDisk(); + // Remove the bitcode file if we are supposed to. + if (RemoveBitcode) + sys::Path(BitcodeFile).eraseFromDisk(); return FilesDifferent; } Modified: llvm/trunk/tools/bugpoint/ExtractFunction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/bugpoint/ExtractFunction.cpp?rev=37877&r1=37876&r2=37877&view=diff ============================================================================== --- llvm/trunk/tools/bugpoint/ExtractFunction.cpp (original) +++ llvm/trunk/tools/bugpoint/ExtractFunction.cpp Wed Jul 4 16:55:50 2007 @@ -139,7 +139,7 @@ if (NewM == 0) { Module *Old = swapProgramIn(M); std::cout << "*** Loop extraction failed: "; - EmitProgressBytecode("loopextraction", true); + EmitProgressBitcode("loopextraction", true); std::cout << "*** Sorry. :( Please report a bug!\n"; swapProgramIn(Old); return 0; @@ -361,7 +361,7 @@ if (Ret == 0) { std::cout << "*** Basic Block extraction failed, please report a bug!\n"; M = swapProgramIn(M); - EmitProgressBytecode("basicblockextractfail", true); + EmitProgressBitcode("basicblockextractfail", true); swapProgramIn(M); } return Ret; Modified: llvm/trunk/tools/bugpoint/Miscompilation.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/bugpoint/Miscompilation.cpp?rev=37877&r1=37876&r2=37877&view=diff ============================================================================== --- llvm/trunk/tools/bugpoint/Miscompilation.cpp (original) +++ llvm/trunk/tools/bugpoint/Miscompilation.cpp Wed Jul 4 16:55:50 2007 @@ -59,17 +59,17 @@ std::cout << "Checking to see if '" << getPassesString(Suffix) << "' compile correctly: "; - std::string BytecodeResult; - if (BD.runPasses(Suffix, BytecodeResult, false/*delete*/, true/*quiet*/)) { + std::string BitcodeResult; + if (BD.runPasses(Suffix, BitcodeResult, false/*delete*/, true/*quiet*/)) { std::cerr << " Error running this sequence of passes" << " on the input program!\n"; BD.setPassesToRun(Suffix); - BD.EmitProgressBytecode("pass-error", false); + BD.EmitProgressBitcode("pass-error", false); exit(BD.debugOptimizerCrash()); } // Check to see if the finished program matches the reference output... - if (BD.diffProgram(BytecodeResult, "", true /*delete bytecode*/)) { + if (BD.diffProgram(BitcodeResult, "", true /*delete bitcode*/)) { std::cout << " nope.\n"; if (Suffix.empty()) { std::cerr << BD.getToolName() << ": I'm confused: the test fails when " @@ -90,21 +90,21 @@ // If it is not broken with the kept passes, it's possible that the prefix // passes must be run before the kept passes to break it. If the program // WORKS after the prefix passes, but then fails if running the prefix AND - // kept passes, we can update our bytecode file to include the result of the + // kept passes, we can update our bitcode file to include the result of the // prefix passes, then discard the prefix passes. // - if (BD.runPasses(Prefix, BytecodeResult, false/*delete*/, true/*quiet*/)) { + if (BD.runPasses(Prefix, BitcodeResult, false/*delete*/, true/*quiet*/)) { std::cerr << " Error running this sequence of passes" << " on the input program!\n"; BD.setPassesToRun(Prefix); - BD.EmitProgressBytecode("pass-error", false); + BD.EmitProgressBitcode("pass-error", false); exit(BD.debugOptimizerCrash()); } // If the prefix maintains the predicate by itself, only keep the prefix! - if (BD.diffProgram(BytecodeResult)) { + if (BD.diffProgram(BitcodeResult)) { std::cout << " nope.\n"; - sys::Path(BytecodeResult).eraseFromDisk(); + sys::Path(BitcodeResult).eraseFromDisk(); return KeepPrefix; } std::cout << " yup.\n"; // No miscompilation! @@ -112,13 +112,13 @@ // Ok, so now we know that the prefix passes work, try running the suffix // passes on the result of the prefix passes. // - Module *PrefixOutput = ParseInputFile(BytecodeResult); + Module *PrefixOutput = ParseInputFile(BitcodeResult); if (PrefixOutput == 0) { - std::cerr << BD.getToolName() << ": Error reading bytecode file '" - << BytecodeResult << "'!\n"; + std::cerr << BD.getToolName() << ": Error reading bitcode file '" + << BitcodeResult << "'!\n"; exit(1); } - sys::Path(BytecodeResult).eraseFromDisk(); // No longer need the file on disk + sys::Path(BitcodeResult).eraseFromDisk(); // No longer need the file on disk // Don't check if there are no passes in the suffix. if (Suffix.empty()) @@ -129,16 +129,16 @@ << getPassesString(Prefix) << "' passes: "; Module *OriginalInput = BD.swapProgramIn(PrefixOutput); - if (BD.runPasses(Suffix, BytecodeResult, false/*delete*/, true/*quiet*/)) { + if (BD.runPasses(Suffix, BitcodeResult, false/*delete*/, true/*quiet*/)) { std::cerr << " Error running this sequence of passes" << " on the input program!\n"; BD.setPassesToRun(Suffix); - BD.EmitProgressBytecode("pass-error", false); + BD.EmitProgressBitcode("pass-error", false); exit(BD.debugOptimizerCrash()); } // Run the result... - if (BD.diffProgram(BytecodeResult, "", true/*delete bytecode*/)) { + if (BD.diffProgram(BitcodeResult, "", true/*delete bitcode*/)) { std::cout << " nope.\n"; delete OriginalInput; // We pruned down the original input... return KeepSuffix; @@ -601,25 +601,25 @@ std::cout << "\n*** Found miscompiling pass" << (getPassesToRun().size() == 1 ? "" : "es") << ": " << getPassesString(getPassesToRun()) << '\n'; - EmitProgressBytecode("passinput"); + EmitProgressBitcode("passinput"); std::vector MiscompiledFunctions = DebugAMiscompilation(*this, TestOptimizer); - // Output a bunch of bytecode files for the user... - std::cout << "Outputting reduced bytecode files which expose the problem:\n"; + // Output a bunch of bitcode files for the user... + std::cout << "Outputting reduced bitcode files which expose the problem:\n"; Module *ToNotOptimize = CloneModule(getProgram()); Module *ToOptimize = SplitFunctionsOutOfModule(ToNotOptimize, MiscompiledFunctions); std::cout << " Non-optimized portion: "; ToNotOptimize = swapProgramIn(ToNotOptimize); - EmitProgressBytecode("tonotoptimize", true); + EmitProgressBitcode("tonotoptimize", true); setNewProgram(ToNotOptimize); // Delete hacked module. std::cout << " Portion that is input to optimizer: "; ToOptimize = swapProgramIn(ToOptimize); - EmitProgressBytecode("tooptimize"); + EmitProgressBitcode("tooptimize"); setNewProgram(ToOptimize); // Delete hacked module. return false; @@ -795,7 +795,7 @@ exit(1); } if (BD.writeProgramToFile(TestModuleBC.toString(), Test)) { - std::cerr << "Error writing bytecode to `" << TestModuleBC << "'\nExiting."; + std::cerr << "Error writing bitcode to `" << TestModuleBC << "'\nExiting."; exit(1); } delete Test; @@ -809,7 +809,7 @@ } if (BD.writeProgramToFile(SafeModuleBC.toString(), Safe)) { - std::cerr << "Error writing bytecode to `" << SafeModuleBC << "'\nExiting."; + std::cerr << "Error writing bitcode to `" << SafeModuleBC << "'\nExiting."; exit(1); } std::string SharedObject = BD.compileSharedObject(SafeModuleBC.toString()); @@ -865,7 +865,7 @@ } if (writeProgramToFile(TestModuleBC.toString(), ToCodeGen)) { - std::cerr << "Error writing bytecode to `" << TestModuleBC << "'\nExiting."; + std::cerr << "Error writing bitcode to `" << TestModuleBC << "'\nExiting."; exit(1); } delete ToCodeGen; @@ -879,7 +879,7 @@ } if (writeProgramToFile(SafeModuleBC.toString(), ToNotCodeGen)) { - std::cerr << "Error writing bytecode to `" << SafeModuleBC << "'\nExiting."; + std::cerr << "Error writing bitcode to `" << SafeModuleBC << "'\nExiting."; exit(1); } std::string SharedObject = compileSharedObject(SafeModuleBC.toString()); Modified: llvm/trunk/tools/bugpoint/OptimizerDriver.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/bugpoint/OptimizerDriver.cpp?rev=37877&r1=37876&r2=37877&view=diff ============================================================================== --- llvm/trunk/tools/bugpoint/OptimizerDriver.cpp (original) +++ llvm/trunk/tools/bugpoint/OptimizerDriver.cpp Wed Jul 4 16:55:50 2007 @@ -47,7 +47,7 @@ cl::desc("Run optimizations through valgrind")); } -/// writeProgramToFile - This writes the current "Program" to the named bytecode +/// writeProgramToFile - This writes the current "Program" to the named bitcode /// file. If an error occurs, true is returned. /// bool BugDriver::writeProgramToFile(const std::string &Filename, @@ -62,11 +62,11 @@ } -/// EmitProgressBytecode - This function is used to output the current Program +/// EmitProgressBitcode - This function is used to output the current Program /// to a file named "bugpoint-ID.bc". /// -void BugDriver::EmitProgressBytecode(const std::string &ID, bool NoFlyer) { - // Output the input to the current pass to a bytecode file, emit a message +void BugDriver::EmitProgressBitcode(const std::string &ID, bool NoFlyer) { + // Output the input to the current pass to a bitcode file, emit a message // telling the user how to reproduce it: opt -foo blah.bc // std::string Filename = "bugpoint-" + ID + ".bc"; @@ -75,7 +75,7 @@ return; } - cout << "Emitted bytecode to '" << Filename << "'\n"; + cout << "Emitted bitcode to '" << Filename << "'\n"; if (NoFlyer || PassesToRun.empty()) return; cout << "\n*** You can reproduce the problem with: "; cout << "opt " << Filename << " "; @@ -88,7 +88,7 @@ std::ios::binary; std::ofstream OutFile(ChildOutput.c_str(), io_mode); if (!OutFile.good()) { - cerr << "Error opening bytecode file: " << ChildOutput << "\n"; + cerr << "Error opening bitcode file: " << ChildOutput << "\n"; return 1; } @@ -105,7 +105,7 @@ // Check that the module is well formed on completion of optimization PM.add(createVerifierPass()); - // Write bytecode out to disk as the last step... + // Write bitcode out to disk as the last step... PM.add(CreateBitcodeWriterPass(OutFile)); // Run all queued passes. @@ -114,10 +114,10 @@ return 0; } -/// runPasses - Run the specified passes on Program, outputting a bytecode file +/// runPasses - Run the specified passes on Program, outputting a bitcode file /// and writing the filename into OutputFile if successful. If the /// optimizations fail for some reason (optimizer crashes), return true, -/// otherwise return false. If DeleteOutput is set to true, the bytecode is +/// otherwise return false. If DeleteOutput is set to true, the bitcode is /// deleted on success, and the filename string is undefined. This prints to /// cout a single line message indicating whether compilation was successful or /// failed. @@ -147,7 +147,7 @@ std::ios::binary; std::ofstream InFile(inputFilename.c_str(), io_mode); if (!InFile.good()) { - cerr << "Error opening bytecode file: " << inputFilename << "\n"; + cerr << "Error opening bitcode file: " << inputFilename << "\n"; return(1); } WriteBitcodeToFile(Program, InFile); @@ -192,7 +192,7 @@ int result = sys::Program::ExecuteAndWait(prog, args, 0, 0, Timeout, MemoryLimit, &ErrMsg); - // If we are supposed to delete the bytecode file or if the passes crashed, + // If we are supposed to delete the bitcode file or if the passes crashed, // remove it now. This may fail if the file was never created, but that's ok. if (DeleteOutput || result != 0) sys::Path(OutputFilename).eraseFromDisk(); @@ -227,13 +227,13 @@ const std::vector &Passes, bool AutoDebugCrashes) { Module *OldProgram = swapProgramIn(M); - std::string BytecodeResult; - if (runPasses(Passes, BytecodeResult, false/*delete*/, true/*quiet*/)) { + std::string BitcodeResult; + if (runPasses(Passes, BitcodeResult, false/*delete*/, true/*quiet*/)) { if (AutoDebugCrashes) { cerr << " Error running this sequence of passes" << " on the input program!\n"; delete OldProgram; - EmitProgressBytecode("pass-error", false); + EmitProgressBitcode("pass-error", false); exit(debugOptimizerCrash()); } swapProgramIn(OldProgram); @@ -243,12 +243,12 @@ // Restore the current program. swapProgramIn(OldProgram); - Module *Ret = ParseInputFile(BytecodeResult); + Module *Ret = ParseInputFile(BitcodeResult); if (Ret == 0) { - cerr << getToolName() << ": Error reading bytecode file '" - << BytecodeResult << "'!\n"; + cerr << getToolName() << ": Error reading bitcode file '" + << BitcodeResult << "'!\n"; exit(1); } - sys::Path(BytecodeResult).eraseFromDisk(); // No longer need the file on disk + sys::Path(BitcodeResult).eraseFromDisk(); // No longer need the file on disk return Ret; } Modified: llvm/trunk/tools/bugpoint/ToolRunner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/bugpoint/ToolRunner.cpp?rev=37877&r1=37876&r2=37877&view=diff ============================================================================== --- llvm/trunk/tools/bugpoint/ToolRunner.cpp (original) +++ llvm/trunk/tools/bugpoint/ToolRunner.cpp Wed Jul 4 16:55:50 2007 @@ -108,7 +108,7 @@ if (Args) { ToolArgs = *Args; } } - virtual int ExecuteProgram(const std::string &Bytecode, + virtual int ExecuteProgram(const std::string &Bitcode, const std::vector &Args, const std::string &InputFile, const std::string &OutputFile, @@ -120,7 +120,7 @@ }; } -int LLI::ExecuteProgram(const std::string &Bytecode, +int LLI::ExecuteProgram(const std::string &Bitcode, const std::vector &Args, const std::string &InputFile, const std::string &OutputFile, @@ -143,7 +143,7 @@ for (unsigned i = 0, e = ToolArgs.size(); i != e; ++i) LLIArgs.push_back(ToolArgs[i].c_str()); - LLIArgs.push_back(Bytecode.c_str()); + LLIArgs.push_back(Bitcode.c_str()); // Add optional parameters to the running program from Argv for (unsigned i=0, e = Args.size(); i != e; ++i) LLIArgs.push_back(Args[i].c_str()); @@ -177,9 +177,9 @@ //===----------------------------------------------------------------------===// // LLC Implementation of AbstractIntepreter interface // -GCC::FileType LLC::OutputCode(const std::string &Bytecode, +GCC::FileType LLC::OutputCode(const std::string &Bitcode, sys::Path &OutputAsmFile) { - sys::Path uniqueFile(Bytecode+".llc.s"); + sys::Path uniqueFile(Bitcode+".llc.s"); std::string ErrMsg; if (uniqueFile.makeUnique(true, &ErrMsg)) { std::cerr << "Error making unique filename: " << ErrMsg << "\n"; @@ -196,7 +196,7 @@ LLCArgs.push_back ("-o"); LLCArgs.push_back (OutputAsmFile.c_str()); // Output to the Asm file LLCArgs.push_back ("-f"); // Overwrite as necessary... - LLCArgs.push_back (Bytecode.c_str()); // This is the input bytecode + LLCArgs.push_back (Bitcode.c_str()); // This is the input bitcode LLCArgs.push_back (0); std::cout << "" << std::flush; @@ -212,13 +212,13 @@ return GCC::AsmFile; } -void LLC::compileProgram(const std::string &Bytecode) { +void LLC::compileProgram(const std::string &Bitcode) { sys::Path OutputAsmFile; - OutputCode(Bytecode, OutputAsmFile); + OutputCode(Bitcode, OutputAsmFile); OutputAsmFile.eraseFromDisk(); } -int LLC::ExecuteProgram(const std::string &Bytecode, +int LLC::ExecuteProgram(const std::string &Bitcode, const std::vector &Args, const std::string &InputFile, const std::string &OutputFile, @@ -228,7 +228,7 @@ unsigned MemoryLimit) { sys::Path OutputAsmFile; - OutputCode(Bytecode, OutputAsmFile); + OutputCode(Bitcode, OutputAsmFile); FileRemover OutFileRemover(OutputAsmFile); std::vector GCCArgs(ArgsForGCC); @@ -274,7 +274,7 @@ if (Args) { ToolArgs = *Args; } } - virtual int ExecuteProgram(const std::string &Bytecode, + virtual int ExecuteProgram(const std::string &Bitcode, const std::vector &Args, const std::string &InputFile, const std::string &OutputFile, @@ -287,7 +287,7 @@ }; } -int JIT::ExecuteProgram(const std::string &Bytecode, +int JIT::ExecuteProgram(const std::string &Bitcode, const std::vector &Args, const std::string &InputFile, const std::string &OutputFile, @@ -310,7 +310,7 @@ JITArgs.push_back("-load"); JITArgs.push_back(SharedLibs[i].c_str()); } - JITArgs.push_back(Bytecode.c_str()); + JITArgs.push_back(Bitcode.c_str()); // Add optional parameters to the running program from Argv for (unsigned i=0, e = Args.size(); i != e; ++i) JITArgs.push_back(Args[i].c_str()); @@ -342,9 +342,9 @@ return 0; } -GCC::FileType CBE::OutputCode(const std::string &Bytecode, +GCC::FileType CBE::OutputCode(const std::string &Bitcode, sys::Path &OutputCFile) { - sys::Path uniqueFile(Bytecode+".cbe.c"); + sys::Path uniqueFile(Bitcode+".cbe.c"); std::string ErrMsg; if (uniqueFile.makeUnique(true, &ErrMsg)) { std::cerr << "Error making unique filename: " << ErrMsg << "\n"; @@ -362,7 +362,7 @@ LLCArgs.push_back (OutputCFile.c_str()); // Output to the C file LLCArgs.push_back ("-march=c"); // Output C language LLCArgs.push_back ("-f"); // Overwrite as necessary... - LLCArgs.push_back (Bytecode.c_str()); // This is the input bytecode + LLCArgs.push_back (Bitcode.c_str()); // This is the input bitcode LLCArgs.push_back (0); std::cout << "" << std::flush; @@ -377,13 +377,13 @@ return GCC::CFile; } -void CBE::compileProgram(const std::string &Bytecode) { +void CBE::compileProgram(const std::string &Bitcode) { sys::Path OutputCFile; - OutputCode(Bytecode, OutputCFile); + OutputCode(Bitcode, OutputCFile); OutputCFile.eraseFromDisk(); } -int CBE::ExecuteProgram(const std::string &Bytecode, +int CBE::ExecuteProgram(const std::string &Bitcode, const std::vector &Args, const std::string &InputFile, const std::string &OutputFile, @@ -392,7 +392,7 @@ unsigned Timeout, unsigned MemoryLimit) { sys::Path OutputCFile; - OutputCode(Bytecode, OutputCFile); + OutputCode(Bitcode, OutputCFile); FileRemover CFileRemove(OutputCFile); Modified: llvm/trunk/tools/bugpoint/ToolRunner.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/bugpoint/ToolRunner.h?rev=37877&r1=37876&r2=37877&view=diff ============================================================================== --- llvm/trunk/tools/bugpoint/ToolRunner.h (original) +++ llvm/trunk/tools/bugpoint/ToolRunner.h Wed Jul 4 16:55:50 2007 @@ -80,7 +80,7 @@ //===---------------------------------------------------------------------===// /// AbstractInterpreter Class - Subclasses of this class are used to execute -/// LLVM bytecode in a variety of ways. This abstract interface hides this +/// LLVM bitcode in a variety of ways. This abstract interface hides this /// complexity behind a simple interface. /// class AbstractInterpreter { @@ -101,25 +101,25 @@ virtual ~AbstractInterpreter() {} - /// compileProgram - Compile the specified program from bytecode to executable + /// compileProgram - Compile the specified program from bitcode to executable /// code. This does not produce any output, it is only used when debugging /// the code generator. If the code generator fails, an exception should be /// thrown, otherwise, this function will just return. - virtual void compileProgram(const std::string &Bytecode) {} + virtual void compileProgram(const std::string &Bitcode) {} - /// OutputCode - Compile the specified program from bytecode to code + /// OutputCode - Compile the specified program from bitcode to code /// understood by the GCC driver (either C or asm). If the code generator /// fails, an exception should be thrown, otherwise, this function returns the /// type of code emitted. - virtual GCC::FileType OutputCode(const std::string &Bytecode, + virtual GCC::FileType OutputCode(const std::string &Bitcode, sys::Path &OutFile) { throw std::string("OutputCode not supported by this AbstractInterpreter!"); } - /// ExecuteProgram - Run the specified bytecode file, emitting output to the + /// ExecuteProgram - Run the specified bitcode file, emitting output to the /// specified filename. This returns the exit code of the program. /// - virtual int ExecuteProgram(const std::string &Bytecode, + virtual int ExecuteProgram(const std::string &Bitcode, const std::vector &Args, const std::string &InputFile, const std::string &OutputFile, @@ -146,13 +146,13 @@ } ~CBE() { delete gcc; } - /// compileProgram - Compile the specified program from bytecode to executable + /// compileProgram - Compile the specified program from bitcode to executable /// code. This does not produce any output, it is only used when debugging /// the code generator. If the code generator fails, an exception should be /// thrown, otherwise, this function will just return. - virtual void compileProgram(const std::string &Bytecode); + virtual void compileProgram(const std::string &Bitcode); - virtual int ExecuteProgram(const std::string &Bytecode, + virtual int ExecuteProgram(const std::string &Bitcode, const std::vector &Args, const std::string &InputFile, const std::string &OutputFile, @@ -163,11 +163,11 @@ unsigned Timeout = 0, unsigned MemoryLimit = 0); - /// OutputCode - Compile the specified program from bytecode to code + /// OutputCode - Compile the specified program from bitcode to code /// understood by the GCC driver (either C or asm). If the code generator /// fails, an exception should be thrown, otherwise, this function returns the /// type of code emitted. - virtual GCC::FileType OutputCode(const std::string &Bytecode, + virtual GCC::FileType OutputCode(const std::string &Bitcode, sys::Path &OutFile); }; @@ -187,13 +187,13 @@ } ~LLC() { delete gcc; } - /// compileProgram - Compile the specified program from bytecode to executable + /// compileProgram - Compile the specified program from bitcode to executable /// code. This does not produce any output, it is only used when debugging /// the code generator. If the code generator fails, an exception should be /// thrown, otherwise, this function will just return. - virtual void compileProgram(const std::string &Bytecode); + virtual void compileProgram(const std::string &Bitcode); - virtual int ExecuteProgram(const std::string &Bytecode, + virtual int ExecuteProgram(const std::string &Bitcode, const std::vector &Args, const std::string &InputFile, const std::string &OutputFile, @@ -204,7 +204,7 @@ unsigned Timeout = 0, unsigned MemoryLimit = 0); - virtual GCC::FileType OutputCode(const std::string &Bytecode, + virtual GCC::FileType OutputCode(const std::string &Bitcode, sys::Path &OutFile); }; Modified: llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp?rev=37877&r1=37876&r2=37877&view=diff ============================================================================== --- llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp (original) +++ llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp Wed Jul 4 16:55:50 2007 @@ -1,4 +1,4 @@ -//===-- llvm-bcanalyzer.cpp - Byte Code Analyzer --------------------------===// +//===-- llvm-bcanalyzer.cpp - Bitcode Analyzer --------------------------===// // // The LLVM Compiler Infrastructure // @@ -8,22 +8,22 @@ //===----------------------------------------------------------------------===// // // This tool may be invoked in the following manner: -// llvm-bcanalyzer [options] - Read LLVM bytecode from stdin -// llvm-bcanalyzer [options] x.bc - Read LLVM bytecode from the x.bc file +// llvm-bcanalyzer [options] - Read LLVM bitcode from stdin +// llvm-bcanalyzer [options] x.bc - Read LLVM bitcode from the x.bc file // // Options: // --help - Output information about command line switches -// --dump - Dump low-level bytecode structure in readable format +// --dump - Dump low-level bitcode structure in readable format // -// This tool provides analytical information about a bytecode file. It is -// intended as an aid to developers of bytecode reading and writing software. It -// produces on std::out a summary of the bytecode file that shows various +// This tool provides analytical information about a bitcode file. It is +// intended as an aid to developers of bitcode reading and writing software. It +// produces on std::out a summary of the bitcode file that shows various // statistics about the contents of the file. By default this information is -// detailed and contains information about individual bytecode blocks and the +// detailed and contains information about individual bitcode blocks and the // functions in the module. -// The tool is also able to print a bytecode file in a straight forward text +// The tool is also able to print a bitcode file in a straight forward text // format that shows the containment and relationships of the information in -// the bytecode file (-dump option). +// the bitcode file (-dump option). // //===----------------------------------------------------------------------===// @@ -41,12 +41,12 @@ using namespace llvm; static cl::opt - InputFilename(cl::Positional, cl::desc(""), cl::init("-")); + InputFilename(cl::Positional, cl::desc(""), cl::init("-")); static cl::opt OutputFilename("-o", cl::init("-"), cl::desc("")); -static cl::opt Dump("dump", cl::desc("Dump low level bytecode trace")); +static cl::opt Dump("dump", cl::desc("Dump low level bitcode trace")); //===----------------------------------------------------------------------===// // Bitcode specific analysis. From resistor at mac.com Wed Jul 4 17:33:23 2007 From: resistor at mac.com (Owen Anderson) Date: Wed, 04 Jul 2007 22:33:23 -0000 Subject: [llvm-commits] [llvm] r37878 - in /llvm/trunk: lib/Transforms/Scalar/GVNPRE.cpp test/Transforms/GVNPRE/2007-07-04-SelectInst.ll Message-ID: <200707042233.l64MXNLM009706@zion.cs.uiuc.edu> Author: resistor Date: Wed Jul 4 17:33:23 2007 New Revision: 37878 URL: http://llvm.org/viewvc/llvm-project?rev=37878&view=rev Log: Fix another bug, this time in PREing select instructions. Added: llvm/trunk/test/Transforms/GVNPRE/2007-07-04-SelectInst.ll Modified: llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp Modified: llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp?rev=37878&r1=37877&r2=37878&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp Wed Jul 4 17:33:23 2007 @@ -1586,8 +1586,7 @@ newVal = new ExtractElementInst(s1, s2, S->getName()+".gvnpre", (*PI)->getTerminator()); else if (SelectInst* S = dyn_cast(U)) - newVal = new SelectInst(S->getCondition(), S->getTrueValue(), - S->getFalseValue(), S->getName()+".gvnpre", + newVal = new SelectInst(s1, s2, s3, S->getName()+".gvnpre", (*PI)->getTerminator()); else if (CastInst* C = dyn_cast(U)) newVal = CastInst::create(C->getOpcode(), s1, C->getType(), Added: llvm/trunk/test/Transforms/GVNPRE/2007-07-04-SelectInst.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/GVNPRE/2007-07-04-SelectInst.ll?rev=37878&view=auto ============================================================================== --- llvm/trunk/test/Transforms/GVNPRE/2007-07-04-SelectInst.ll (added) +++ llvm/trunk/test/Transforms/GVNPRE/2007-07-04-SelectInst.ll Wed Jul 4 17:33:23 2007 @@ -0,0 +1,18 @@ +; RUN: llvm-as < %s | opt -gvnpre | llvm-dis + +define void @set_depth_values(i32 %level) { +cond_true90: ; preds = %cond_next84 + br i1 false, label %cond_true105, label %cond_true151 + +cond_true105: ; preds = %cond_true90 + %tmp132 = add i32 %level, -3 ; [#uses=2] + %tmp133 = icmp sgt i32 %tmp132, 0 ; [#uses=1] + %max134 = select i1 %tmp133, i32 %tmp132, i32 1 ; [#uses=0] + br label %cond_true151 + +cond_true151: ; preds = %cond_true140, %cond_true105 + %tmp153 = add i32 %level, -3 ; [#uses=2] + %tmp154 = icmp sgt i32 %tmp153, 0 ; [#uses=1] + %max155 = select i1 %tmp154, i32 %tmp153, i32 1 ; [#uses=0] + ret void +} From baldrick at free.fr Wed Jul 4 17:57:40 2007 From: baldrick at free.fr (Duncan Sands) Date: Thu, 5 Jul 2007 00:57:40 +0200 Subject: [llvm-commits] llvm-gcc: exception handling tweaks Message-ID: <200707050057.41701.baldrick@free.fr> (1) Fix some comments. (2) Correct off-by-one in test for branching within the same scope (currently it never triggers, but comes out in the wash later). (3) Have all branches to the same destination share cleanup code, not just exception unwinding branches. Currently each non-unwind branch (like falling through at the end of a try scope) gets its own copy of cleanups. Change inspired by the thought that the optimizers find it easy to duplicate blocks, but hard to merge them. (4) Add a missing bitcast in a rare case. Ciao, Duncan. -------------- next part -------------- A non-text attachment was scrubbed... Name: eh_tweaks.diff Type: text/x-diff Size: 3778 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20070705/01727f15/attachment.bin From reid at x10sys.com Wed Jul 4 22:03:07 2007 From: reid at x10sys.com (Reid Spencer) Date: Thu, 05 Jul 2007 03:03:07 -0000 Subject: [llvm-commits] [llvm-top] r37880 - /llvm-top/trunk/Makefile Message-ID: <200707050303.l65337uB016117@zion.cs.uiuc.edu> Author: reid Date: Wed Jul 4 22:03:07 2007 New Revision: 37880 URL: http://llvm.org/viewvc/llvm-project?rev=37880&view=rev Log: Deduce the SVNROOT from the 'svn info .' command. This retains the user's SVNROOT from the original checkout of llvm-top, including protocol and user name so it is propagated down to the sub-directory. Modified: llvm-top/trunk/Makefile Modified: llvm-top/trunk/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm-top/trunk/Makefile?rev=37880&r1=37879&r2=37880&view=diff ============================================================================== --- llvm-top/trunk/Makefile (original) +++ llvm-top/trunk/Makefile Wed Jul 4 22:03:07 2007 @@ -13,8 +13,8 @@ # development environment, including checking out other software, configuration, # etc. # -SVN = svn -SVNROOT = http://llvm.org/svn/llvm-project +SVN = $(shell which svn) +SVNROOT = $(shell $(SVN) info . | grep 'Repository Root:' | sed -e 's/^Repository Root: //') .PHONY: get-llvm get-hlvm get-stacker get-test-suite get-llvm-gcc From nicholas at mxc.ca Wed Jul 4 22:15:01 2007 From: nicholas at mxc.ca (Nick Lewycky) Date: Thu, 05 Jul 2007 03:15:01 -0000 Subject: [llvm-commits] [llvm] r37881 - /llvm/trunk/lib/Transforms/Scalar/PredicateSimplifier.cpp Message-ID: <200707050315.l653F18m016387@zion.cs.uiuc.edu> Author: nicholas Date: Wed Jul 4 22:15:00 2007 New Revision: 37881 URL: http://llvm.org/viewvc/llvm-project?rev=37881&view=rev Log: Break "variable canonicalization" out of InequalityGraph and into its own class "ValueNumbering". Modified: llvm/trunk/lib/Transforms/Scalar/PredicateSimplifier.cpp Modified: llvm/trunk/lib/Transforms/Scalar/PredicateSimplifier.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/PredicateSimplifier.cpp?rev=37881&r1=37880&r2=37881&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/PredicateSimplifier.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/PredicateSimplifier.cpp Wed Jul 4 22:15:00 2007 @@ -148,7 +148,7 @@ unsigned spread = DFSout - DFSin; unsigned N_spread = N.DFSout - N.DFSin; if (spread == N_spread) return DFSin < N.DFSin; - else return DFSout - DFSin < N.DFSout - N.DFSin; + return spread < N_spread; } bool operator>(const Node &N) const { return N < *this; } @@ -215,7 +215,7 @@ Node *getNodeForBlock(BasicBlock *BB) const { if (!NodeMap.count(BB)) return 0; - else return const_cast(this)->NodeMap[BB]; + return const_cast(this)->NodeMap[BB]; } bool dominates(Instruction *I1, Instruction *I2) { @@ -236,8 +236,7 @@ } else { Node *Node1 = getNodeForBlock(BB1), *Node2 = getNodeForBlock(BB2); - if (!Node1 || !Node2) return false; - return Node1->dominates(Node2); + return Node1 && Node2 && Node1->dominates(Node2); } } private: @@ -361,6 +360,163 @@ return Rev; } + /// ValueNumbering stores the scope-specific value numbers for a given Value. + class VISIBILITY_HIDDEN ValueNumbering { + class VISIBILITY_HIDDEN VNPair { + public: + Value *V; + unsigned index; + DomTreeDFS::Node *Subtree; + + VNPair(Value *V, unsigned index, DomTreeDFS::Node *Subtree) + : V(V), index(index), Subtree(Subtree) {} + + bool operator==(const VNPair &RHS) const { + return V == RHS.V && Subtree == RHS.Subtree; + } + + bool operator<(const VNPair &RHS) const { + if (V != RHS.V) return V < RHS.V; + return *Subtree < *RHS.Subtree; + } + + bool operator<(Value *RHS) const { + return V < RHS; + } + }; + + typedef std::vector VNMapType; + VNMapType VNMap; + + std::vector Values; + + DomTreeDFS *DTDFS; + + public: + /// compare - returns true if V1 is a better canonical value than V2. + bool compare(Value *V1, Value *V2) const { + if (isa(V1)) + return !isa(V2); + else if (isa(V2)) + return false; + else if (isa(V1)) + return !isa(V2); + else if (isa(V2)) + return false; + + Instruction *I1 = dyn_cast(V1); + Instruction *I2 = dyn_cast(V2); + + if (!I1 || !I2) + return V1->getNumUses() < V2->getNumUses(); + + return DTDFS->dominates(I1, I2); + } + + ValueNumbering(DomTreeDFS *DTDFS) : DTDFS(DTDFS) {} + + /// valueNumber - finds the value number for V under the Subtree. If + /// there is no value number, returns zero. + unsigned valueNumber(Value *V, DomTreeDFS::Node *Subtree) { + VNMapType::iterator E = VNMap.end(); + VNPair pair(V, 0, Subtree); + VNMapType::iterator I = std::lower_bound(VNMap.begin(), E, pair); + while (I != E && I->V == V) { + if (I->Subtree->dominates(Subtree)) + return I->index; + ++I; + } + return 0; + } + + /// newVN - creates a new value number. Value V must not already have a + /// value number assigned. + unsigned newVN(Value *V) { + Values.push_back(V); + + VNPair pair = VNPair(V, Values.size(), DTDFS->getRootNode()); + assert(!std::binary_search(VNMap.begin(), VNMap.end(), pair) && + "Attempt to create a duplicate value number."); + VNMap.insert(std::lower_bound(VNMap.begin(), VNMap.end(), pair), pair); + + return Values.size(); + } + + /// value - returns the Value associated with a value number. + Value *value(unsigned index) const { + assert(index != 0 && "Zero index is reserved for not found."); + assert(index <= Values.size() && "Index out of range."); + return Values[index-1]; + } + + /// canonicalize - return a Value that is equal to V under Subtree. + Value *canonicalize(Value *V, DomTreeDFS::Node *Subtree) { + if (isa(V)) return V; + + if (unsigned n = valueNumber(V, Subtree)) + return value(n); + else + return V; + } + + /// addEquality - adds that value V belongs to the set of equivalent + /// values defined by value number n under Subtree. + void addEquality(unsigned n, Value *V, DomTreeDFS::Node *Subtree) { + assert(canonicalize(value(n), Subtree) == value(n) && + "Node's 'canonical' choice isn't best within this subtree."); + + // Suppose that we are given "%x -> node #1 (%y)". The problem is that + // we may already have "%z -> node #2 (%x)" somewhere above us in the + // graph. We need to find those edges and add "%z -> node #1 (%y)" + // to keep the lookups canonical. + + std::vector ToRepoint(1, V); + + if (unsigned Conflict = valueNumber(V, Subtree)) { + for (VNMapType::iterator I = VNMap.begin(), E = VNMap.end(); + I != E; ++I) { + if (I->index == Conflict && I->Subtree->dominates(Subtree)) + ToRepoint.push_back(I->V); + } + } + + for (std::vector::iterator VI = ToRepoint.begin(), + VE = ToRepoint.end(); VI != VE; ++VI) { + Value *V = *VI; + + VNPair pair(V, n, Subtree); + VNMapType::iterator B = VNMap.begin(), E = VNMap.end(); + VNMapType::iterator I = std::lower_bound(B, E, pair); + if (I != E && I->V == V && I->Subtree == Subtree) + I->index = n; // Update best choice + else + VNMap.insert(I, pair); // New Value + + // XXX: we currently don't have to worry about updating values with + // more specific Subtrees, but we will need to for PHI node support. + +#ifndef NDEBUG + Value *V_n = value(n); + if (isa(V) && isa(V_n)) { + assert(V == V_n && "Constant equals different constant?"); + } +#endif + } + } + + /// remove - removes all references to value V. + void remove(Value *V) { + VNMapType::iterator B = VNMap.begin(); + VNPair pair(V, 0, DTDFS->getRootNode()); + VNMapType::iterator J = std::upper_bound(B, VNMap.end(), pair); + VNMapType::iterator I = J; + + while (I != B && I->V == V) --I; + + VNMap.erase(I, J); + } + }; + /// The InequalityGraph stores the relationships between values. /// Each Value in the graph is assigned to a Node. Nodes are pointer /// comparable for equality. The caller is expected to maintain the logical @@ -369,12 +525,14 @@ /// The InequalityGraph class may invalidate Node*s after any mutator call. /// @brief The InequalityGraph stores the relationships between values. class VISIBILITY_HIDDEN InequalityGraph { + ValueNumbering &VN; DomTreeDFS::Node *TreeRoot; InequalityGraph(); // DO NOT IMPLEMENT InequalityGraph(InequalityGraph &); // DO NOT IMPLEMENT public: - explicit InequalityGraph(DomTreeDFS::Node *TreeRoot) : TreeRoot(TreeRoot){} + InequalityGraph(ValueNumbering &VN, DomTreeDFS::Node *TreeRoot) + : VN(VN), TreeRoot(TreeRoot) {} class Node; @@ -393,7 +551,7 @@ bool operator<(const Edge &edge) const { if (To != edge.To) return To < edge.To; - else return *Subtree < *edge.Subtree; + return *Subtree < *edge.Subtree; } bool operator<(unsigned to) const { @@ -419,8 +577,6 @@ typedef SmallVector RelationsType; RelationsType Relations; - Value *Canonical; - // TODO: can this idea improve performance? //friend class std::vector; //Node(Node &N) { RelationsType.swap(N.RelationsType); } @@ -429,33 +585,29 @@ typedef RelationsType::iterator iterator; typedef RelationsType::const_iterator const_iterator; - Node(Value *V) : Canonical(V) {} - - private: #ifndef NDEBUG - public: virtual ~Node() {} virtual void dump() const { dump(*cerr.stream()); } private: - void dump(std::ostream &os) const { - os << *getValue() << ":\n"; + void dump(std::ostream &os) const { + static const std::string names[32] = + { "000000", "000001", "000002", "000003", "000004", "000005", + "000006", "000007", "000008", "000009", " >", " >=", + " s>u<", "s>=u<=", " s>", " s>=", "000016", "000017", + " s", "s<=u>=", " <", " <=", " s<", " s<=", + "000024", "000025", " u>", " u>=", " u<", " u<=", + " !=", "000031" }; for (Node::const_iterator NI = begin(), NE = end(); NI != NE; ++NI) { - static const std::string names[32] = - { "000000", "000001", "000002", "000003", "000004", "000005", - "000006", "000007", "000008", "000009", " >", " >=", - " s>u<", "s>=u<=", " s>", " s>=", "000016", "000017", - " s", "s<=u>=", " <", " <=", " s<", " s<=", - "000024", "000025", " u>", " u>=", " u<", " u<=", - " !=", "000031" }; - os << " " << names[NI->LV] << " " << NI->To - << " (" << NI->Subtree->getDFSNumIn() << ")\n"; + os << names[NI->LV] << " " << NI->To + << " (" << NI->Subtree->getDFSNumIn() << ")"; + if (NI != NE) os << ", "; } } + public: #endif - public: iterator begin() { return Relations.begin(); } iterator end() { return Relations.end(); } const_iterator begin() const { return Relations.begin(); } @@ -481,11 +633,6 @@ return E; } - Value *getValue() const - { - return Canonical; - } - /// Updates the lattice value for a given node. Create a new entry if /// one doesn't exist, otherwise it merges the values. The new lattice /// value must not be inconsistent with any previously existing value. @@ -525,31 +672,6 @@ }; private: - struct VISIBILITY_HIDDEN NodeMapEdge { - Value *V; - unsigned index; - DomTreeDFS::Node *Subtree; - - NodeMapEdge(Value *V, unsigned index, DomTreeDFS::Node *Subtree) - : V(V), index(index), Subtree(Subtree) {} - - bool operator==(const NodeMapEdge &RHS) const { - return V == RHS.V && - Subtree == RHS.Subtree; - } - - bool operator<(const NodeMapEdge &RHS) const { - if (V != RHS.V) return V < RHS.V; - else return *Subtree < *RHS.Subtree; - } - - bool operator<(Value *RHS) const { - return V < RHS; - } - }; - - typedef std::vector NodeMapType; - NodeMapType NodeMap; std::vector Nodes; @@ -563,53 +685,15 @@ return &Nodes[index-1]; } - /// Returns the node currently representing Value V, or zero if no such - /// node exists. - unsigned getNode(Value *V, DomTreeDFS::Node *Subtree) { - NodeMapType::iterator E = NodeMap.end(); - NodeMapEdge Edge(V, 0, Subtree); - NodeMapType::iterator I = std::lower_bound(NodeMap.begin(), E, Edge); - while (I != E && I->V == V) { - if (Subtree->DominatedBy(I->Subtree)) - return I->index; - ++I; - } - return 0; - } - - /// getOrInsertNode - always returns a valid node index, creating a node - /// to match the Value if needed. - unsigned getOrInsertNode(Value *V, DomTreeDFS::Node *Subtree) { - if (unsigned n = getNode(V, Subtree)) - return n; - else - return newNode(V); - } - /// newNode - creates a new node for a given Value and returns the index. unsigned newNode(Value *V) { - assert(!isa(V) && "BBs may not be nodes."); + assert((isa(V) || isa(V) || isa(V)) && + "Bad Value for node."); assert(V->getType() != Type::VoidTy && "Void node?"); - Nodes.push_back(Node(V)); - - NodeMapEdge MapEntry = NodeMapEdge(V, Nodes.size(), TreeRoot); - assert(!std::binary_search(NodeMap.begin(), NodeMap.end(), MapEntry) && - "Attempt to create a duplicate Node."); - NodeMap.insert(std::lower_bound(NodeMap.begin(), NodeMap.end(), - MapEntry), MapEntry); - return MapEntry.index; - } - - /// If the Value is in the graph, return the canonical form. Otherwise, - /// return the original Value. - Value *canonicalize(Value *V, DomTreeDFS::Node *Subtree) { - if (isa(V)) return V; - - if (unsigned n = getNode(V, Subtree)) - return node(n)->getValue(); - else - return V; + unsigned n = VN.newVN(V); + if (Nodes.size() < n) Nodes.resize(n); + return n; } /// isRelatedBy - true iff n1 op n2 @@ -627,53 +711,6 @@ // The add* methods assume that your input is logically valid and may // assertion-fail or infinitely loop if you attempt a contradiction. - void addEquality(unsigned n, Value *V, DomTreeDFS::Node *Subtree) { - assert(canonicalize(node(n)->getValue(), Subtree) == node(n)->getValue() - && "Node's 'canonical' choice isn't best within this subtree."); - - // Suppose that we are given "%x -> node #1 (%y)". The problem is that - // we may already have "%z -> node #2 (%x)" somewhere above us in the - // graph. We need to find those edges and add "%z -> node #1 (%y)" - // to keep the lookups canonical. - - std::vector ToRepoint; - ToRepoint.push_back(V); - - if (unsigned Conflict = getNode(V, Subtree)) { - for (NodeMapType::iterator I = NodeMap.begin(), E = NodeMap.end(); - I != E; ++I) { - if (I->index == Conflict && Subtree->DominatedBy(I->Subtree)) - ToRepoint.push_back(I->V); - } - } - - for (std::vector::iterator VI = ToRepoint.begin(), - VE = ToRepoint.end(); VI != VE; ++VI) { - Value *V = *VI; - - // XXX: review this code. This may be doing too many insertions. - NodeMapEdge Edge(V, n, Subtree); - NodeMapType::iterator E = NodeMap.end(); - NodeMapType::iterator I = std::lower_bound(NodeMap.begin(), E, Edge); - if (I == E || I->V != V || I->Subtree != Subtree) { - // New Value - NodeMap.insert(I, Edge); - } else if (I != E && I->V == V && I->Subtree == Subtree) { - // Update best choice - I->index = n; - } - -#ifndef NDEBUG - Node *N = node(n); - if (isa(V)) { - if (isa(N->getValue())) { - assert(V == N->getValue() && "Constant equals different constant?"); - } - } -#endif - } - } - /// addInequality - Sets n1 op n2. /// It is also an error to call this on an inequality that is already true. void addInequality(unsigned n1, unsigned n2, DomTreeDFS::Node *Subtree, @@ -776,28 +813,18 @@ N2->update(n1, reversePredicate(LV1), Subtree); } - /// remove - Removes a Value from the graph. If the value is the canonical - /// choice for a Node, destroys the Node from the graph deleting all edges - /// to and from it. This method does not renumber the nodes. - void remove(Value *V) { - for (unsigned i = 0; i < NodeMap.size();) { - NodeMapType::iterator I = NodeMap.begin()+i; - if (I->V == V) { - Node *N = node(I->index); - if (node(I->index)->getValue() == V) { - for (Node::iterator NI = N->begin(), NE = N->end(); NI != NE; ++NI){ - Node::iterator Iter = node(NI->To)->find(I->index, TreeRoot); - do { - node(NI->To)->Relations.erase(Iter); - Iter = node(NI->To)->find(I->index, TreeRoot); - } while (Iter != node(NI->To)->end()); - } - N->Canonical = NULL; - } - N->Relations.clear(); - NodeMap.erase(I); - } else ++i; + /// remove - removes a node from the graph by removing all references to + /// and from it. + void remove(unsigned n) { + Node *N = node(n); + for (Node::iterator NI = N->begin(), NE = N->end(); NI != NE; ++NI) { + Node::iterator Iter = node(NI->To)->find(n, TreeRoot); + do { + node(NI->To)->Relations.erase(Iter); + Iter = node(NI->To)->find(n, TreeRoot); + } while (Iter != node(NI->To)->end()); } + N->Relations.clear(); } #ifndef NDEBUG @@ -807,19 +834,12 @@ } void dump(std::ostream &os) { - std::set VisitedNodes; - for (NodeMapType::const_iterator I = NodeMap.begin(), E = NodeMap.end(); - I != E; ++I) { - Node *N = node(I->index); - os << *I->V << " == " << I->index - << "(" << I->Subtree->getDFSNumIn() << ")\n"; - if (VisitedNodes.insert(N).second) { - os << I->index << ". "; - if (!N->getValue()) os << "(deleted node)\n"; - else N->dump(os); + for (unsigned i = 1; i <= Nodes.size(); ++i) { + os << i << " = {"; + node(i)->dump(os); + os << "}\n"; } } - } #endif }; @@ -842,7 +862,7 @@ bool operator<(const ScopedRange &range) const { if (V != range.V) return V < range.V; - else return *Subtree < *range.Subtree; + return *Subtree < *range.Subtree; } bool operator<(const Value *value) const { @@ -1303,6 +1323,7 @@ }; std::deque WorkList; + ValueNumbering &VN; InequalityGraph &IG; UnreachableBlocks &UB; ValueRanges &VR; @@ -1314,26 +1335,6 @@ typedef InequalityGraph::Node Node; - /// Returns true if V1 is a better canonical value than V2. - bool compare(Value *V1, Value *V2) const { - if (isa(V1)) - return !isa(V2); - else if (isa(V2)) - return false; - else if (isa(V1)) - return !isa(V2); - else if (isa(V2)) - return false; - - Instruction *I1 = dyn_cast(V1); - Instruction *I2 = dyn_cast(V2); - - if (!I1 || !I2) - return V1->getNumUses() < V2->getNumUses(); - - return DTDFS->dominates(I1, I2); - } - // below - true if the Instruction is dominated by the current context // block or instruction bool below(Instruction *I) { @@ -1382,17 +1383,17 @@ if (isa(V1) && isa(V2)) return false; - unsigned n1 = IG.getNode(V1, Top), n2 = IG.getNode(V2, Top); + unsigned n1 = VN.valueNumber(V1, Top), n2 = VN.valueNumber(V2, Top); if (n1 && n2) { if (n1 == n2) return true; if (IG.isRelatedBy(n1, n2, Top, NE)) return false; } - if (n1) assert(V1 == IG.node(n1)->getValue() && "Value isn't canonical."); - if (n2) assert(V2 == IG.node(n2)->getValue() && "Value isn't canonical."); + if (n1) assert(V1 == VN.value(n1) && "Value isn't canonical."); + if (n2) assert(V2 == VN.value(n2) && "Value isn't canonical."); - assert(!compare(V2, V1) && "Please order parameters to makeEqual."); + assert(!VN.compare(V2, V1) && "Please order parameters to makeEqual."); assert(!isa(V2) && "Tried to remove a constant."); @@ -1436,8 +1437,8 @@ for (SetVector::iterator I = Remove.begin()+1 /* skip n2 */, E = Remove.end(); I != E; ++I) { unsigned n = *I; - Value *V = IG.node(n)->getValue(); - if (compare(V, V1)) { + Value *V = VN.value(n); + if (VN.compare(V, V1)) { V1 = V; n1 = n; DontRemove = I; @@ -1459,7 +1460,7 @@ bool mergeIGNode = false; unsigned i = 0; for (Value *R = V2; i == 0 || i < Remove.size(); ++i) { - if (i) R = IG.node(Remove[i])->getValue(); // skip n2. + if (i) R = VN.value(Remove[i]); // skip n2. // Try to replace the whole instruction. If we can, we're done. Instruction *I2 = dyn_cast(R); @@ -1524,7 +1525,7 @@ for (SetVector::iterator I = Remove.begin(), E = Remove.end(); I != E; ++I) { - Value *V = IG.node(*I)->getValue(); + Value *V = VN.value(*I); if (!V->use_empty()) RemoveVals.push_back(V); } @@ -1559,11 +1560,11 @@ // Point V2 (and all items in Remove) to N1. if (!n2) - IG.addEquality(n1, V2, Top); + VN.addEquality(n1, V2, Top); else { for (SetVector::iterator I = Remove.begin(), E = Remove.end(); I != E; ++I) { - IG.addEquality(n1, IG.node(*I)->getValue(), Top); + VN.addEquality(n1, VN.value(*I), Top); } } @@ -1571,7 +1572,7 @@ // Even when Remove is empty, we still want to process V2. i = 0; for (Value *R = V2; i == 0 || i < Remove.size(); ++i) { - if (i) R = IG.node(Remove[i])->getValue(); // skip n2. + if (i) R = VN.value(Remove[i]); // skip n2. if (Instruction *I2 = dyn_cast(R)) { if (aboveOrBelow(I2)) @@ -1639,9 +1640,11 @@ } public: - VRPSolver(InequalityGraph &IG, UnreachableBlocks &UB, ValueRanges &VR, - DomTreeDFS *DTDFS, bool &modified, BasicBlock *TopBB) - : IG(IG), + VRPSolver(ValueNumbering &VN, InequalityGraph &IG, UnreachableBlocks &UB, + ValueRanges &VR, DomTreeDFS *DTDFS, bool &modified, + BasicBlock *TopBB) + : VN(VN), + IG(IG), UB(UB), VR(VR), DTDFS(DTDFS), @@ -1653,9 +1656,11 @@ assert(Top && "VRPSolver created for unreachable basic block."); } - VRPSolver(InequalityGraph &IG, UnreachableBlocks &UB, ValueRanges &VR, - DomTreeDFS *DTDFS, bool &modified, Instruction *TopInst) - : IG(IG), + VRPSolver(ValueNumbering &VN, InequalityGraph &IG, UnreachableBlocks &UB, + ValueRanges &VR, DomTreeDFS *DTDFS, bool &modified, + Instruction *TopInst) + : VN(VN), + IG(IG), UB(UB), VR(VR), DTDFS(DTDFS), @@ -1674,8 +1679,8 @@ return ConstantExpr::getCompare(Pred, C1, C2) == ConstantInt::getTrue(); - if (unsigned n1 = IG.getNode(V1, Top)) - if (unsigned n2 = IG.getNode(V2, Top)) { + if (unsigned n1 = VN.valueNumber(V1, Top)) + if (unsigned n2 = VN.valueNumber(V2, Top)) { if (n1 == n2) return Pred == ICmpInst::ICMP_EQ || Pred == ICmpInst::ICMP_ULE || Pred == ICmpInst::ICMP_UGE || @@ -1710,14 +1715,14 @@ /// new about, find any new relationships between its operands. void defToOps(Instruction *I) { Instruction *NewContext = below(I) ? I : TopInst; - Value *Canonical = IG.canonicalize(I, Top); + Value *Canonical = VN.canonicalize(I, Top); if (BinaryOperator *BO = dyn_cast(I)) { const Type *Ty = BO->getType(); assert(!Ty->isFPOrFPVector() && "Float in work queue!"); - Value *Op0 = IG.canonicalize(BO->getOperand(0), Top); - Value *Op1 = IG.canonicalize(BO->getOperand(1), Top); + Value *Op0 = VN.canonicalize(BO->getOperand(0), Top); + Value *Op1 = VN.canonicalize(BO->getOperand(1), Top); // TODO: "and i32 -1, %x" EQ %y then %x EQ %y. @@ -1786,11 +1791,11 @@ Value *True = SI->getTrueValue(); Value *False = SI->getFalseValue(); if (isRelatedBy(True, False, ICmpInst::ICMP_NE)) { - if (Canonical == IG.canonicalize(True, Top) || + if (Canonical == VN.canonicalize(True, Top) || isRelatedBy(Canonical, False, ICmpInst::ICMP_NE)) add(SI->getCondition(), ConstantInt::getTrue(), ICmpInst::ICMP_EQ, NewContext); - else if (Canonical == IG.canonicalize(False, Top) || + else if (Canonical == VN.canonicalize(False, Top) || isRelatedBy(Canonical, True, ICmpInst::ICMP_NE)) add(SI->getCondition(), ConstantInt::getFalse(), ICmpInst::ICMP_EQ, NewContext); @@ -1798,7 +1803,7 @@ } else if (GetElementPtrInst *GEPI = dyn_cast(I)) { for (GetElementPtrInst::op_iterator OI = GEPI->idx_begin(), OE = GEPI->idx_end(); OI != OE; ++OI) { - ConstantInt *Op = dyn_cast(IG.canonicalize(*OI, Top)); + ConstantInt *Op = dyn_cast(VN.canonicalize(*OI, Top)); if (!Op || !Op->isZero()) return; } // TODO: The GEPI indices are all zero. Copy from definition to operand, @@ -1812,7 +1817,7 @@ } else if (CastInst *CI = dyn_cast(I)) { const Type *SrcTy = CI->getSrcTy(); - Value *TheCI = IG.canonicalize(CI, Top); + Value *TheCI = VN.canonicalize(CI, Top); uint32_t W = VR.typeToWidth(SrcTy); if (!W) return; ConstantRange CR = VR.rangeFromValue(TheCI, Top, W); @@ -1823,11 +1828,11 @@ default: break; case Instruction::ZExt: case Instruction::SExt: - VR.applyRange(IG.canonicalize(CI->getOperand(0), Top), + VR.applyRange(VN.canonicalize(CI->getOperand(0), Top), CR.truncate(W), Top, this); break; case Instruction::BitCast: - VR.applyRange(IG.canonicalize(CI->getOperand(0), Top), + VR.applyRange(VN.canonicalize(CI->getOperand(0), Top), CR, Top, this); break; } @@ -1841,8 +1846,8 @@ Instruction *NewContext = below(I) ? I : TopInst; if (BinaryOperator *BO = dyn_cast(I)) { - Value *Op0 = IG.canonicalize(BO->getOperand(0), Top); - Value *Op1 = IG.canonicalize(BO->getOperand(1), Top); + Value *Op0 = VN.canonicalize(BO->getOperand(0), Top); + Value *Op1 = VN.canonicalize(BO->getOperand(1), Top); if (ConstantInt *CI0 = dyn_cast(Op0)) if (ConstantInt *CI1 = dyn_cast(Op1)) { @@ -1912,7 +1917,7 @@ // "%x = udiv i32 %y, %z" and %x EQ %y then %z EQ 1 Value *Known = Op0, *Unknown = Op1, - *TheBO = IG.canonicalize(BO, Top); + *TheBO = VN.canonicalize(BO, Top); if (Known != TheBO) std::swap(Known, Unknown); if (Known == TheBO) { switch (Opcode) { @@ -1947,8 +1952,8 @@ // "%a = icmp ult i32 %b, %c" and %b u>= %c then %a EQ false // etc. - Value *Op0 = IG.canonicalize(IC->getOperand(0), Top); - Value *Op1 = IG.canonicalize(IC->getOperand(1), Top); + Value *Op0 = VN.canonicalize(IC->getOperand(0), Top); + Value *Op1 = VN.canonicalize(IC->getOperand(1), Top); ICmpInst::Predicate Pred = IC->getPredicate(); if (isRelatedBy(Op0, Op1, Pred)) { @@ -1965,20 +1970,20 @@ // %x EQ false then %a EQ %c // %b EQ %c then %a EQ %b - Value *Canonical = IG.canonicalize(SI->getCondition(), Top); + Value *Canonical = VN.canonicalize(SI->getCondition(), Top); if (Canonical == ConstantInt::getTrue()) { add(SI, SI->getTrueValue(), ICmpInst::ICMP_EQ, NewContext); } else if (Canonical == ConstantInt::getFalse()) { add(SI, SI->getFalseValue(), ICmpInst::ICMP_EQ, NewContext); - } else if (IG.canonicalize(SI->getTrueValue(), Top) == - IG.canonicalize(SI->getFalseValue(), Top)) { + } else if (VN.canonicalize(SI->getTrueValue(), Top) == + VN.canonicalize(SI->getFalseValue(), Top)) { add(SI, SI->getTrueValue(), ICmpInst::ICMP_EQ, NewContext); } } else if (CastInst *CI = dyn_cast(I)) { const Type *DestTy = CI->getDestTy(); if (DestTy->isFPOrFPVector()) return; - Value *Op = IG.canonicalize(CI->getOperand(0), Top); + Value *Op = VN.canonicalize(CI->getOperand(0), Top); Instruction::CastOps Opcode = CI->getOpcode(); if (Constant *C = dyn_cast(Op)) { @@ -1987,7 +1992,7 @@ } uint32_t W = VR.typeToWidth(DestTy); - Value *TheCI = IG.canonicalize(CI, Top); + Value *TheCI = VN.canonicalize(CI, Top); ConstantRange CR = VR.rangeFromValue(Op, Top, W); if (!CR.isFullSet()) { @@ -2013,7 +2018,7 @@ } else if (GetElementPtrInst *GEPI = dyn_cast(I)) { for (GetElementPtrInst::op_iterator OI = GEPI->idx_begin(), OE = GEPI->idx_end(); OI != OE; ++OI) { - ConstantInt *Op = dyn_cast(IG.canonicalize(*OI, Top)); + ConstantInt *Op = dyn_cast(VN.canonicalize(*OI, Top)); if (!Op || !Op->isZero()) return; } // TODO: The GEPI indices are all zero. Copy from operand to definition, @@ -2038,11 +2043,11 @@ TopBB = O.ContextBB; Top = DTDFS->getNodeForBlock(TopBB); // XXX move this into Context - O.LHS = IG.canonicalize(O.LHS, Top); - O.RHS = IG.canonicalize(O.RHS, Top); + O.LHS = VN.canonicalize(O.LHS, Top); + O.RHS = VN.canonicalize(O.RHS, Top); - assert(O.LHS == IG.canonicalize(O.LHS, Top) && "Canonicalize isn't."); - assert(O.RHS == IG.canonicalize(O.RHS, Top) && "Canonicalize isn't."); + assert(O.LHS == VN.canonicalize(O.LHS, Top) && "Canonicalize isn't."); + assert(O.RHS == VN.canonicalize(O.RHS, Top) && "Canonicalize isn't."); DOUT << "solving " << *O.LHS << " " << O.Op << " " << *O.RHS; if (O.ContextInst) DOUT << " context inst: " << *O.ContextInst; @@ -2064,7 +2069,7 @@ } } - if (compare(O.LHS, O.RHS)) { + if (VN.compare(O.LHS, O.RHS)) { std::swap(O.LHS, O.RHS); O.Op = ICmpInst::getSwappedPredicate(O.Op); } @@ -2086,8 +2091,8 @@ continue; } - unsigned n1 = IG.getNode(O.LHS, Top); - unsigned n2 = IG.getNode(O.RHS, Top); + unsigned n1 = VN.valueNumber(O.LHS, Top); + unsigned n2 = VN.valueNumber(O.RHS, Top); if (n1 && n1 == n2) { if (O.Op != ICmpInst::ICMP_UGE && O.Op != ICmpInst::ICMP_ULE && @@ -2161,7 +2166,7 @@ #ifndef NDEBUG bool ValueRanges::isCanonical(Value *V, DomTreeDFS::Node *Subtree, VRPSolver *VRP) { - return V == VRP->IG.canonicalize(V, Subtree); + return V == VRP->VN.canonicalize(V, Subtree); } #endif @@ -2172,6 +2177,7 @@ class VISIBILITY_HIDDEN PredicateSimplifier : public FunctionPass { DomTreeDFS *DTDFS; bool modified; + ValueNumbering *VN; InequalityGraph *IG; UnreachableBlocks UB; ValueRanges *VR; @@ -2204,12 +2210,14 @@ DomTreeDFS::Node *DTNode; public: + ValueNumbering &VN; InequalityGraph &IG; UnreachableBlocks &UB; ValueRanges &VR; Forwards(PredicateSimplifier *PS, DomTreeDFS::Node *DTNode) - : PS(PS), DTNode(DTNode), IG(*PS->IG), UB(PS->UB), VR(*PS->VR) {} + : PS(PS), DTNode(DTNode), VN(*PS->VN), IG(*PS->IG), UB(PS->UB), + VR(*PS->VR) {} void visitTerminatorInst(TerminatorInst &TI); void visitBranchInst(BranchInst &BI); @@ -2260,20 +2268,24 @@ if (isInstructionTriviallyDead(I)) { ++NumSimple; modified = true; - IG->remove(I); + if (unsigned n = VN->valueNumber(I, DTDFS->getRootNode())) + if (VN->value(n) == I) IG->remove(n); + VN->remove(I); I->eraseFromParent(); return; } #ifndef NDEBUG // Try to replace the whole instruction. - Value *V = IG->canonicalize(I, DT); + Value *V = VN->canonicalize(I, DT); assert(V == I && "Late instruction canonicalization."); if (V != I) { modified = true; ++NumInstruction; DOUT << "Removing " << *I << ", replacing with " << *V << "\n"; - IG->remove(I); + if (unsigned n = VN->valueNumber(I, DTDFS->getRootNode())) + if (VN->value(n) == I) IG->remove(n); + VN->remove(I); I->replaceAllUsesWith(V); I->eraseFromParent(); return; @@ -2282,7 +2294,7 @@ // Try to substitute operands. for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) { Value *Oper = I->getOperand(i); - Value *V = IG->canonicalize(Oper, DT); + Value *V = VN->canonicalize(Oper, DT); assert(V == Oper && "Late operand canonicalization."); if (V != Oper) { modified = true; @@ -2311,7 +2323,8 @@ modified = false; DomTreeDFS::Node *Root = DTDFS->getRootNode(); - IG = new InequalityGraph(Root); + VN = new ValueNumbering(DTDFS); + IG = new InequalityGraph(*VN, Root); VR = new ValueRanges(TD); WorkList.push_back(Root); @@ -2357,13 +2370,13 @@ if (Dest == TrueDest) { DOUT << "(" << DTNode->getBlock()->getName() << ") true set:\n"; - VRPSolver VRP(IG, UB, VR, PS->DTDFS, PS->modified, Dest); + VRPSolver VRP(VN, IG, UB, VR, PS->DTDFS, PS->modified, Dest); VRP.add(ConstantInt::getTrue(), Condition, ICmpInst::ICMP_EQ); VRP.solve(); DEBUG(IG.dump()); } else if (Dest == FalseDest) { DOUT << "(" << DTNode->getBlock()->getName() << ") false set:\n"; - VRPSolver VRP(IG, UB, VR, PS->DTDFS, PS->modified, Dest); + VRPSolver VRP(VN, IG, UB, VR, PS->DTDFS, PS->modified, Dest); VRP.add(ConstantInt::getFalse(), Condition, ICmpInst::ICMP_EQ); VRP.solve(); DEBUG(IG.dump()); @@ -2385,7 +2398,7 @@ DOUT << "Switch thinking about BB %" << BB->getName() << "(" << PS->DTDFS->getNodeForBlock(BB)->getDFSNumIn() << ")\n"; - VRPSolver VRP(IG, UB, VR, PS->DTDFS, PS->modified, BB); + VRPSolver VRP(VN, IG, UB, VR, PS->DTDFS, PS->modified, BB); if (BB == SI.getDefaultDest()) { for (unsigned i = 1, e = SI.getNumCases(); i < e; ++i) if (SI.getSuccessor(i) != BB) @@ -2400,7 +2413,7 @@ } void PredicateSimplifier::Forwards::visitAllocaInst(AllocaInst &AI) { - VRPSolver VRP(IG, UB, VR, PS->DTDFS, PS->modified, &AI); + VRPSolver VRP(VN, IG, UB, VR, PS->DTDFS, PS->modified, &AI); VRP.add(Constant::getNullValue(AI.getType()), &AI, ICmpInst::ICMP_NE); VRP.solve(); } @@ -2410,7 +2423,7 @@ // avoid "load uint* null" -> null NE null. if (isa(Ptr)) return; - VRPSolver VRP(IG, UB, VR, PS->DTDFS, PS->modified, &LI); + VRPSolver VRP(VN, IG, UB, VR, PS->DTDFS, PS->modified, &LI); VRP.add(Constant::getNullValue(Ptr->getType()), Ptr, ICmpInst::ICMP_NE); VRP.solve(); } @@ -2419,13 +2432,13 @@ Value *Ptr = SI.getPointerOperand(); if (isa(Ptr)) return; - VRPSolver VRP(IG, UB, VR, PS->DTDFS, PS->modified, &SI); + VRPSolver VRP(VN, IG, UB, VR, PS->DTDFS, PS->modified, &SI); VRP.add(Constant::getNullValue(Ptr->getType()), Ptr, ICmpInst::ICMP_NE); VRP.solve(); } void PredicateSimplifier::Forwards::visitSExtInst(SExtInst &SI) { - VRPSolver VRP(IG, UB, VR, PS->DTDFS, PS->modified, &SI); + VRPSolver VRP(VN, IG, UB, VR, PS->DTDFS, PS->modified, &SI); uint32_t SrcBitWidth = cast(SI.getSrcTy())->getBitWidth(); uint32_t DstBitWidth = cast(SI.getDestTy())->getBitWidth(); APInt Min(APInt::getHighBitsSet(DstBitWidth, DstBitWidth-SrcBitWidth+1)); @@ -2436,7 +2449,7 @@ } void PredicateSimplifier::Forwards::visitZExtInst(ZExtInst &ZI) { - VRPSolver VRP(IG, UB, VR, PS->DTDFS, PS->modified, &ZI); + VRPSolver VRP(VN, IG, UB, VR, PS->DTDFS, PS->modified, &ZI); uint32_t SrcBitWidth = cast(ZI.getSrcTy())->getBitWidth(); uint32_t DstBitWidth = cast(ZI.getDestTy())->getBitWidth(); APInt Max(APInt::getLowBitsSet(DstBitWidth, SrcBitWidth)); @@ -2454,7 +2467,7 @@ case Instruction::UDiv: case Instruction::SDiv: { Value *Divisor = BO.getOperand(1); - VRPSolver VRP(IG, UB, VR, PS->DTDFS, PS->modified, &BO); + VRPSolver VRP(VN, IG, UB, VR, PS->DTDFS, PS->modified, &BO); VRP.add(Constant::getNullValue(Divisor->getType()), Divisor, ICmpInst::ICMP_NE); VRP.solve(); @@ -2465,34 +2478,34 @@ switch (ops) { default: break; case Instruction::Shl: { - VRPSolver VRP(IG, UB, VR, PS->DTDFS, PS->modified, &BO); + VRPSolver VRP(VN, IG, UB, VR, PS->DTDFS, PS->modified, &BO); VRP.add(&BO, BO.getOperand(0), ICmpInst::ICMP_UGE); VRP.solve(); } break; case Instruction::AShr: { - VRPSolver VRP(IG, UB, VR, PS->DTDFS, PS->modified, &BO); + VRPSolver VRP(VN, IG, UB, VR, PS->DTDFS, PS->modified, &BO); VRP.add(&BO, BO.getOperand(0), ICmpInst::ICMP_SLE); VRP.solve(); } break; case Instruction::LShr: case Instruction::UDiv: { - VRPSolver VRP(IG, UB, VR, PS->DTDFS, PS->modified, &BO); + VRPSolver VRP(VN, IG, UB, VR, PS->DTDFS, PS->modified, &BO); VRP.add(&BO, BO.getOperand(0), ICmpInst::ICMP_ULE); VRP.solve(); } break; case Instruction::URem: { - VRPSolver VRP(IG, UB, VR, PS->DTDFS, PS->modified, &BO); + VRPSolver VRP(VN, IG, UB, VR, PS->DTDFS, PS->modified, &BO); VRP.add(&BO, BO.getOperand(1), ICmpInst::ICMP_ULE); VRP.solve(); } break; case Instruction::And: { - VRPSolver VRP(IG, UB, VR, PS->DTDFS, PS->modified, &BO); + VRPSolver VRP(VN, IG, UB, VR, PS->DTDFS, PS->modified, &BO); VRP.add(&BO, BO.getOperand(0), ICmpInst::ICMP_ULE); VRP.add(&BO, BO.getOperand(1), ICmpInst::ICMP_ULE); VRP.solve(); } break; case Instruction::Or: { - VRPSolver VRP(IG, UB, VR, PS->DTDFS, PS->modified, &BO); + VRPSolver VRP(VN, IG, UB, VR, PS->DTDFS, PS->modified, &BO); VRP.add(&BO, BO.getOperand(0), ICmpInst::ICMP_UGE); VRP.add(&BO, BO.getOperand(1), ICmpInst::ICMP_UGE); VRP.solve(); @@ -2518,7 +2531,7 @@ case ICmpInst::ICMP_SGE: Pred = ICmpInst::ICMP_SGT; break; } if (Pred != IC.getPredicate()) { - VRPSolver VRP(IG, UB, VR, PS->DTDFS, PS->modified, &IC); + VRPSolver VRP(VN, IG, UB, VR, PS->DTDFS, PS->modified, &IC); if (VRP.isRelatedBy(IC.getOperand(1), IC.getOperand(0), ICmpInst::ICMP_NE)) { ++NumSnuggle; @@ -2546,14 +2559,19 @@ } if (NextVal) { - VRPSolver VRP(IG, UB, VR, PS->DTDFS, PS->modified, &IC); + VRPSolver VRP(VN, IG, UB, VR, PS->DTDFS, PS->modified, &IC); if (VRP.isRelatedBy(IC.getOperand(0), NextVal, ICmpInst::getInversePredicate(Pred))) { ICmpInst *NewIC = new ICmpInst(ICmpInst::ICMP_EQ, IC.getOperand(0), NextVal, "", &IC); NewIC->takeName(&IC); IC.replaceAllUsesWith(NewIC); - IG.remove(&IC); // XXX: prove this isn't necessary + + // XXX: prove this isn't necessary + if (unsigned n = VN.valueNumber(&IC, PS->DTDFS->getRootNode())) + if (VN.value(n) == &IC) IG.remove(n); + VN.remove(&IC); + IC.eraseFromParent(); ++NumSnuggle; PS->modified = true; From sabre at nondot.org Thu Jul 5 00:20:26 2007 From: sabre at nondot.org (Chris Lattner) Date: Thu, 05 Jul 2007 05:20:26 -0000 Subject: [llvm-commits] [llvm-top] r37882 - in /llvm-top/trunk: Makefile README.txt Message-ID: <200707050520.l655KQPA019927@zion.cs.uiuc.edu> Author: lattner Date: Thu Jul 5 00:20:25 2007 New Revision: 37882 URL: http://llvm.org/viewvc/llvm-project?rev=37882&view=rev Log: switch to a generic checkout target, so we don't need for the makefile to know all the modules. Modified: llvm-top/trunk/Makefile llvm-top/trunk/README.txt Modified: llvm-top/trunk/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm-top/trunk/Makefile?rev=37882&r1=37881&r2=37882&view=diff ============================================================================== --- llvm-top/trunk/Makefile (original) +++ llvm-top/trunk/Makefile Thu Jul 5 00:20:25 2007 @@ -13,33 +13,22 @@ # development environment, including checking out other software, configuration, # etc. # -SVN = $(shell which svn) -SVNROOT = $(shell $(SVN) info . | grep 'Repository Root:' | sed -e 's/^Repository Root: //') +SVN = svn +SVNROOT := $(shell $(SVN) info . | grep 'Repository Root:' | \ + sed -e 's/^Repository Root: //') + +.PHONY: checkout + +checkout: + $(SVN) co $(SVNROOT)/$(MODULE)/trunk $(MODULE) + + -.PHONY: get-llvm get-hlvm get-stacker get-test-suite get-llvm-gcc get-llvm: llvm llvm: @$(SVN) co $(SVNROOT)/llvm/trunk llvm -get-test-suite: test-suite -test-suite: - @$(SVN) co $(SVNROOT)/test-suite/trunk test-suite - -get-stacker: stacker -stacker: - @$(SVN) co $(SVNROOT)/stacker/trunk stacker - -get-hlvm: hlvm -hlvm: - @echo hlvm: Not implemented yet. - #@$(SVN) co $(SVNROOT)/hlvm/trunk hlvm - -get-llvm-gcc: llvm-gcc -llvm-gcc: - @echo llvm-gcc: Not implemented yet. - #@$(SVN) co $(SVNROOT)/llvm-gcc/trunk llvm-gcc - build-llvm: llvm @root=`pwd` ; cd llvm ; \ ./configure --prefix="$$root/install" \ Modified: llvm-top/trunk/README.txt URL: http://llvm.org/viewvc/llvm-project/llvm-top/trunk/README.txt?rev=37882&r1=37881&r2=37882&view=diff ============================================================================== --- llvm-top/trunk/README.txt (original) +++ llvm-top/trunk/README.txt Thu Jul 5 00:20:25 2007 @@ -13,11 +13,11 @@ Once you've done that, you can then use the following "make" targets to check out the various modules of the project: -get-llvm: Checks out the llvm (core) module -get-test-suite: Checks out the llvm test suite -get-stacker: Checks out the stacker front end -get-hlvm: Checks out the High Level Virtual Machine -get-llvm-gcc: Checks out the GCC based C/C++/Obj-C compiler +make checkout MODULE=llvm - Checks out the llvm (core) module +make checkout MODULE=llvm-gcc - Checks out the GCC based C/C++/Obj-C compiler +make checkout MODULE=test-suite - Checks out the llvm test suite +make checkout MODULE=stacker - Checks out the stacker front end +make checkout MODULE=hlvm - Checks out the High Level Virtual Machine Some Other Useful URLS ====================== From sabre at nondot.org Thu Jul 5 00:38:55 2007 From: sabre at nondot.org (Chris Lattner) Date: Thu, 05 Jul 2007 05:38:55 -0000 Subject: [llvm-commits] [stacker] r37883 - /stacker/trunk/ModuleInfo.txt Message-ID: <200707050538.l655ctFQ020303@zion.cs.uiuc.edu> Author: lattner Date: Thu Jul 5 00:38:55 2007 New Revision: 37883 URL: http://llvm.org/viewvc/llvm-project?rev=37883&view=rev Log: stacker depends on llvm Added: stacker/trunk/ModuleInfo.txt Added: stacker/trunk/ModuleInfo.txt URL: http://llvm.org/viewvc/llvm-project/stacker/trunk/ModuleInfo.txt?rev=37883&view=auto ============================================================================== --- stacker/trunk/ModuleInfo.txt (added) +++ stacker/trunk/ModuleInfo.txt Thu Jul 5 00:38:55 2007 @@ -0,0 +1,6 @@ +# This file defines the relationship of this module to other modules and +# tells llvm-top how to drive it. + +# Declare that stacker depends on llvm. +DepModule: llvm + From sabre at nondot.org Thu Jul 5 00:39:48 2007 From: sabre at nondot.org (Chris Lattner) Date: Thu, 05 Jul 2007 05:39:48 -0000 Subject: [llvm-commits] [poolalloc] r37884 - /poolalloc/trunk/ModuleInfo.txt Message-ID: <200707050539.l655dnLF020327@zion.cs.uiuc.edu> Author: lattner Date: Thu Jul 5 00:39:48 2007 New Revision: 37884 URL: http://llvm.org/viewvc/llvm-project?rev=37884&view=rev Log: poolalloc depends on llvm. Added: poolalloc/trunk/ModuleInfo.txt Added: poolalloc/trunk/ModuleInfo.txt URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/ModuleInfo.txt?rev=37884&view=auto ============================================================================== --- poolalloc/trunk/ModuleInfo.txt (added) +++ poolalloc/trunk/ModuleInfo.txt Thu Jul 5 00:39:48 2007 @@ -0,0 +1,6 @@ +# This file defines the relationship of this module to other modules and +# tells llvm-top how to drive it. + +# Declare that this module depends on llvm. +DepModule: llvm + From sabre at nondot.org Thu Jul 5 00:46:02 2007 From: sabre at nondot.org (Chris Lattner) Date: Thu, 05 Jul 2007 05:46:02 -0000 Subject: [llvm-commits] [llvm-top] r37885 - in /llvm-top/trunk: Makefile README.txt Message-ID: <200707050546.l655k2wK020472@zion.cs.uiuc.edu> Author: lattner Date: Thu Jul 5 00:46:02 2007 New Revision: 37885 URL: http://llvm.org/viewvc/llvm-project?rev=37885&view=rev Log: Make checkout automatically check out dependent projects. For example, 'make checkout MODULE=stacker' now checks out stacker and llvm. Modified: llvm-top/trunk/Makefile llvm-top/trunk/README.txt Modified: llvm-top/trunk/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm-top/trunk/Makefile?rev=37885&r1=37884&r2=37885&view=diff ============================================================================== --- llvm-top/trunk/Makefile (original) +++ llvm-top/trunk/Makefile Thu Jul 5 00:46:02 2007 @@ -14,14 +14,36 @@ # etc. # SVN = svn -SVNROOT := $(shell $(SVN) info . | grep 'Repository Root:' | \ +SVNROOT = $(shell $(SVN) info . | grep 'Repository Root:' | \ sed -e 's/^Repository Root: //') + +# Rule to get the modules that $(MODULE) depends on. +MODULEINFO = $(MODULE)/ModuleInfo.txt +DEPMODULES = grep -i DepModule: $(MODULEINFO) | \ + sed 's/DepModule: //g' + + .PHONY: checkout +ifndef MODULE +checkout: + @echo ERROR: you must specify a MODULE value to 'make checkout'. + @echo ERROR: for example, use: 'make checkout MODULE=llvm'. + +else + +# Check out a module and all its dependencies. checkout: $(SVN) co $(SVNROOT)/$(MODULE)/trunk $(MODULE) + @if test -f $(MODULEINFO); then \ + for mod in `$(DEPMODULES)`; do \ + echo "NOTE: $(MODULE) module depends on $$mod, checking it out."; \ + $(MAKE) checkout MODULE=$$mod; \ + done; \ + fi +endif Modified: llvm-top/trunk/README.txt URL: http://llvm.org/viewvc/llvm-project/llvm-top/trunk/README.txt?rev=37885&r1=37884&r2=37885&view=diff ============================================================================== --- llvm-top/trunk/README.txt (original) +++ llvm-top/trunk/README.txt Thu Jul 5 00:46:02 2007 @@ -10,14 +10,27 @@ svn co http://llvm.org/svn/llvm-project/llvm-top/trunk llvm-top -Once you've done that, you can then use the following "make" targets to check -out the various modules of the project: +Once you've done that, you can then check out a module (and all its +dependencies) with the 'make checkout MODULE=modulename' command. For example: + + make checkout MODULE=llvm-gcc-4.0 + +Checks out llvm-gcc (the llvm C/C++/ObjC compiler built with the GCC 4.0 +front-end) and all the things it depends on. Other modules available +are: + + test-suite - The llvm test suite + stacker - The stacker front end (a 'Forth-like' language) + hlvm - High Level Virtual Machine + +You can check out any number of modules. + + +Once you check out the modules, use the "make" command to automatically +configure and build the projects you checked out. + +... -make checkout MODULE=llvm - Checks out the llvm (core) module -make checkout MODULE=llvm-gcc - Checks out the GCC based C/C++/Obj-C compiler -make checkout MODULE=test-suite - Checks out the llvm test suite -make checkout MODULE=stacker - Checks out the stacker front end -make checkout MODULE=hlvm - Checks out the High Level Virtual Machine Some Other Useful URLS ====================== From sabre at nondot.org Thu Jul 5 01:01:40 2007 From: sabre at nondot.org (Chris Lattner) Date: Thu, 05 Jul 2007 06:01:40 -0000 Subject: [llvm-commits] [website] r37886 - in /website: ./ branches/ tags/ trunk/ Message-ID: <200707050601.l6561eei020848@zion.cs.uiuc.edu> Author: lattner Date: Thu Jul 5 01:01:39 2007 New Revision: 37886 URL: http://llvm.org/viewvc/llvm-project?rev=37886&view=rev Log: New website module Added: website/ website/branches/ website/tags/ website/trunk/ From sabre at nondot.org Thu Jul 5 01:04:46 2007 From: sabre at nondot.org (Chris Lattner) Date: Thu, 05 Jul 2007 06:04:46 -0000 Subject: [llvm-commits] [website] r37887 - in /website/trunk: ./ docs/ docs/CVS/ docs/img/ docs/img/CVS/ img/ subproj/ subproj/llvm/ subproj/test-suite/ Message-ID: <200707050604.l6564n15021037@zion.cs.uiuc.edu> Author: lattner Date: Thu Jul 5 01:04:45 2007 New Revision: 37887 URL: http://llvm.org/viewvc/llvm-project?rev=37887&view=rev Log: initial prototype for a new web page. [This commit notification would consist of 21 parts, which exceeds the limit of 10 ones, so it was shortened to the summary.] From sabre at nondot.org Thu Jul 5 01:47:21 2007 From: sabre at nondot.org (Chris Lattner) Date: Thu, 05 Jul 2007 06:47:21 -0000 Subject: [llvm-commits] [website] r37888 - /website/trunk/docs/CVS/ Message-ID: <200707050647.l656lL0O022158@zion.cs.uiuc.edu> Author: lattner Date: Thu Jul 5 01:47:21 2007 New Revision: 37888 URL: http://llvm.org/viewvc/llvm-project?rev=37888&view=rev Log: remove cvs dir Removed: website/trunk/docs/CVS/ From sabre at nondot.org Thu Jul 5 01:58:00 2007 From: sabre at nondot.org (Chris Lattner) Date: Thu, 05 Jul 2007 06:58:00 -0000 Subject: [llvm-commits] [website] r37889 - /website/trunk/docs/img/CVS/ Message-ID: <200707050658.l656w0bo022377@zion.cs.uiuc.edu> Author: lattner Date: Thu Jul 5 01:58:00 2007 New Revision: 37889 URL: http://llvm.org/viewvc/llvm-project?rev=37889&view=rev Log: remove CVS dir Removed: website/trunk/docs/img/CVS/ From clattner at apple.com Thu Jul 5 01:58:53 2007 From: clattner at apple.com (Chris Lattner) Date: Wed, 4 Jul 2007 23:58:53 -0700 Subject: [llvm-commits] [website] r37887 - in /website/trunk: ./ docs/ docs/CVS/ docs/img/ docs/img/CVS/ img/ subproj/ subproj/llvm/ subproj/test-suite/ In-Reply-To: <200707050604.l6564n15021037@zion.cs.uiuc.edu> References: <200707050604.l6564n15021037@zion.cs.uiuc.edu> Message-ID: <12A16A8B-6526-4245-B4A4-6637C2175932@apple.com> On Jul 4, 2007, at 11:04 PM, Chris Lattner wrote: > Author: lattner > Date: Thu Jul 5 01:04:45 2007 > New Revision: 37887 > > URL: http://llvm.org/viewvc/llvm-project?rev=37887&view=rev > Log: > initial prototype for a new web page. > > > > [This commit notification would consist of 21 parts, > which exceeds the limit of 10 ones, so it was shortened to the > summary.] Wow, this sucks. Instead of telling me everything, it told me nothing. Why shorten at all? If we need to shorten, we should at least list the files that changed. Also, the URL: links are always incorrect for multi-file commits. -Chris From evan.cheng at apple.com Thu Jul 5 02:05:39 2007 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 05 Jul 2007 07:05:39 -0000 Subject: [llvm-commits] [llvm] r37890 - /llvm/trunk/lib/CodeGen/RegisterScavenging.cpp Message-ID: <200707050705.l6575d8l022539@zion.cs.uiuc.edu> Author: evancheng Date: Thu Jul 5 02:05:38 2007 New Revision: 37890 URL: http://llvm.org/viewvc/llvm-project?rev=37890&view=rev Log: Better assertion messages. Modified: llvm/trunk/lib/CodeGen/RegisterScavenging.cpp Modified: llvm/trunk/lib/CodeGen/RegisterScavenging.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterScavenging.cpp?rev=37890&r1=37889&r2=37890&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegisterScavenging.cpp (original) +++ llvm/trunk/lib/CodeGen/RegisterScavenging.cpp Thu Jul 5 02:05:38 2007 @@ -110,7 +110,7 @@ if (!isUsed(Reg)) { // Register has been scavenged. Restore it! if (Reg != ScavengedReg) - assert(false); + assert(false && "Using an undefined register!"); else restoreScavengedReg(); } @@ -135,10 +135,11 @@ } // Skip two-address destination operand. if (TID->findTiedToSrcOperand(i) != -1) { - assert(isUsed(Reg)); + assert(isUsed(Reg) && "Using an undefined register!"); continue; } - assert(isUnused(Reg) || isReserved(Reg)); + assert((isUnused(Reg) || isReserved(Reg)) && + "Re-defining a live register!"); setUsed(Reg); } } From evan.cheng at apple.com Thu Jul 5 02:06:47 2007 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 05 Jul 2007 07:06:47 -0000 Subject: [llvm-commits] [llvm] r37891 - /llvm/trunk/lib/Target/TargetInstrInfo.cpp Message-ID: <200707050706.l6576llZ022574@zion.cs.uiuc.edu> Author: evancheng Date: Thu Jul 5 02:06:46 2007 New Revision: 37891 URL: http://llvm.org/viewvc/llvm-project?rev=37891&view=rev Log: Do not check isPredicated() on non-predicable instructions. Modified: llvm/trunk/lib/Target/TargetInstrInfo.cpp Modified: llvm/trunk/lib/Target/TargetInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetInstrInfo.cpp?rev=37891&r1=37890&r2=37891&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/TargetInstrInfo.cpp Thu Jul 5 02:06:46 2007 @@ -87,7 +87,10 @@ bool TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const { const TargetInstrDescriptor *TID = MI->getInstrDescriptor(); - if (TID->Flags & M_TERMINATOR_FLAG) + if (TID->Flags & M_TERMINATOR_FLAG) { + if ((TID->Flags & M_PREDICABLE) == 0) + return true; return !isPredicated(MI); +} return false; } From evan.cheng at apple.com Thu Jul 5 02:09:10 2007 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 05 Jul 2007 07:09:10 -0000 Subject: [llvm-commits] [llvm] r37892 - /llvm/trunk/lib/Target/Target.td Message-ID: <200707050709.l6579AjD023288@zion.cs.uiuc.edu> Author: evancheng Date: Thu Jul 5 02:09:09 2007 New Revision: 37892 URL: http://llvm.org/viewvc/llvm-project?rev=37892&view=rev Log: - Added zero_reg def to stand for register 0. - Added two variants of PredicateOperand: ImmutablePredicateOperand, whose predicate does not change after isel; PredicateDefOperand, which represent a predicate defintion operand. Modified: llvm/trunk/lib/Target/Target.td Modified: llvm/trunk/lib/Target/Target.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Target.td?rev=37892&r1=37891&r2=37892&view=diff ============================================================================== --- llvm/trunk/lib/Target/Target.td (original) +++ llvm/trunk/lib/Target/Target.td Thu Jul 5 02:09:09 2007 @@ -256,16 +256,33 @@ def i32imm : Operand; def i64imm : Operand; +/// zero_reg definition - Special node to stand for the zero register. +/// +def zero_reg; /// PredicateOperand - This can be used to define a predicate operand for an /// instruction. OpTypes specifies the MIOperandInfo for the operand, and /// AlwaysVal specifies the value of this predicate when set to "always -/// execute". -class PredicateOperand : Operand { +/// execute". If isOutput is true, then this is output operand. If isImmutable +/// is true, then the operand should not change after instruction selection. +class PredicateOperand + : Operand { let MIOperandInfo = OpTypes; + bit isOutput = 0; + bit isImmutable = 0; dag ExecuteAlways = AlwaysVal; } +class ImmutablePredicateOperand + : PredicateOperand { + let isImmutable = 1; +} + +class PredicateDefOperand + : PredicateOperand { + let isOutput = 1; +} + // InstrInfo - This class should only be instantiated once to provide parameters // which are global to the the target machine. From evan.cheng at apple.com Thu Jul 5 02:09:50 2007 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 05 Jul 2007 07:09:50 -0000 Subject: [llvm-commits] [llvm] r37893 - /llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Message-ID: <200707050709.l6579pNY023463@zion.cs.uiuc.edu> Author: evancheng Date: Thu Jul 5 02:09:50 2007 New Revision: 37893 URL: http://llvm.org/viewvc/llvm-project?rev=37893&view=rev Log: PPC conditional branch predicate does not change after isel. Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=37893&r1=37892&r2=37893&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original) +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Thu Jul 5 02:09:50 2007 @@ -272,7 +272,8 @@ // PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg // that doesn't matter. -def pred : PredicateOperand { +def pred : ImmutablePredicateOperand { let PrintMethod = "printPredicateOperand"; } From evan.cheng at apple.com Thu Jul 5 02:11:04 2007 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 05 Jul 2007 07:11:04 -0000 Subject: [llvm-commits] [llvm] r37894 - /llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp Message-ID: <200707050711.l657B5fs023992@zion.cs.uiuc.edu> Author: evancheng Date: Thu Jul 5 02:11:03 2007 New Revision: 37894 URL: http://llvm.org/viewvc/llvm-project?rev=37894&view=rev Log: Added ARM::CPSR to represent ARM CPSR status register. Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp?rev=37894&r1=37893&r2=37894&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp Thu Jul 5 02:11:03 2007 @@ -144,14 +144,15 @@ .addFrameIndex(FI).addImm(0); else BuildMI(MBB, I, TII.get(ARM::STR)).addReg(SrcReg, false, false, true) - .addFrameIndex(FI).addReg(0).addImm(0).addImm((int64_t)ARMCC::AL); + .addFrameIndex(FI).addReg(0).addImm(0).addImm((int64_t)ARMCC::AL) + .addReg(0); } else if (RC == ARM::DPRRegisterClass) { BuildMI(MBB, I, TII.get(ARM::FSTD)).addReg(SrcReg, false, false, true) - .addFrameIndex(FI).addImm(0).addImm((int64_t)ARMCC::AL); + .addFrameIndex(FI).addImm(0).addImm((int64_t)ARMCC::AL).addReg(0); } else { assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); BuildMI(MBB, I, TII.get(ARM::FSTS)).addReg(SrcReg, false, false, true) - .addFrameIndex(FI).addImm(0).addImm((int64_t)ARMCC::AL); + .addFrameIndex(FI).addImm(0).addImm((int64_t)ARMCC::AL).addReg(0); } } @@ -167,14 +168,15 @@ .addFrameIndex(FI).addImm(0); else BuildMI(MBB, I, TII.get(ARM::LDR), DestReg) - .addFrameIndex(FI).addReg(0).addImm(0).addImm((int64_t)ARMCC::AL); + .addFrameIndex(FI).addReg(0).addImm(0).addImm((int64_t)ARMCC::AL) + .addReg(0); } else if (RC == ARM::DPRRegisterClass) { BuildMI(MBB, I, TII.get(ARM::FLDD), DestReg) - .addFrameIndex(FI).addImm(0).addImm((int64_t)ARMCC::AL); + .addFrameIndex(FI).addImm(0).addImm((int64_t)ARMCC::AL).addReg(0); } else { assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); BuildMI(MBB, I, TII.get(ARM::FLDS), DestReg) - .addFrameIndex(FI).addImm(0).addImm((int64_t)ARMCC::AL); + .addFrameIndex(FI).addImm(0).addImm((int64_t)ARMCC::AL).addReg(0); } } @@ -189,13 +191,13 @@ BuildMI(MBB, I, TII.get(ARM::tMOVr), DestReg).addReg(SrcReg); else BuildMI(MBB, I, TII.get(ARM::MOVr), DestReg).addReg(SrcReg) - .addImm((int64_t)ARMCC::AL); + .addImm((int64_t)ARMCC::AL).addReg(0); } else if (RC == ARM::SPRRegisterClass) BuildMI(MBB, I, TII.get(ARM::FCPYS), DestReg).addReg(SrcReg) - .addImm((int64_t)ARMCC::AL); + .addImm((int64_t)ARMCC::AL).addReg(0); else if (RC == ARM::DPRRegisterClass) BuildMI(MBB, I, TII.get(ARM::FCPYD), DestReg).addReg(SrcReg) - .addImm((int64_t)ARMCC::AL); + .addImm((int64_t)ARMCC::AL).addReg(0); else abort(); } @@ -204,7 +206,8 @@ /// specified immediate. static void emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, - unsigned DestReg, ARMCC::CondCodes Pred, int Val, + unsigned DestReg, int Val, + ARMCC::CondCodes Pred, unsigned PredReg, const TargetInstrInfo &TII, bool isThumb) { MachineFunction &MF = *MBB.getParent(); MachineConstantPool *ConstantPool = MF.getConstantPool(); @@ -214,7 +217,7 @@ BuildMI(MBB, MBBI, TII.get(ARM::tLDRcp), DestReg).addConstantPoolIndex(Idx); else BuildMI(MBB, MBBI, TII.get(ARM::LDRcp), DestReg).addConstantPoolIndex(Idx) - .addReg(0).addImm(0).addImm((unsigned)Pred); + .addReg(0).addImm(0).addImm((unsigned)Pred).addReg(PredReg); } void ARMRegisterInfo::reMaterialize(MachineBasicBlock &MBB, @@ -223,8 +226,9 @@ const MachineInstr *Orig) const { if (Orig->getOpcode() == ARM::MOVi2pieces) { emitLoadConstPool(MBB, I, DestReg, - (ARMCC::CondCodes)Orig->getOperand(2).getImmedValue(), Orig->getOperand(1).getImmedValue(), + (ARMCC::CondCodes)Orig->getOperand(2).getImmedValue(), + Orig->getOperand(3).getReg(), TII, false); return; } @@ -255,14 +259,15 @@ default: break; case ARM::MOVr: { unsigned Pred = MI->getOperand(2).getImmedValue(); + unsigned PredReg = MI->getOperand(3).getReg(); if (OpNum == 0) { // move -> store unsigned SrcReg = MI->getOperand(1).getReg(); NewMI = BuildMI(TII.get(ARM::STR)).addReg(SrcReg).addFrameIndex(FI) - .addReg(0).addImm(0).addImm(Pred); + .addReg(0).addImm(0).addImm(Pred).addReg(PredReg); } else { // move -> load unsigned DstReg = MI->getOperand(0).getReg(); NewMI = BuildMI(TII.get(ARM::LDR), DstReg).addFrameIndex(FI).addReg(0) - .addImm(0).addImm(Pred); + .addImm(0).addImm(Pred).addReg(PredReg); } break; } @@ -286,27 +291,29 @@ } case ARM::FCPYS: { unsigned Pred = MI->getOperand(2).getImmedValue(); + unsigned PredReg = MI->getOperand(3).getReg(); if (OpNum == 0) { // move -> store unsigned SrcReg = MI->getOperand(1).getReg(); NewMI = BuildMI(TII.get(ARM::FSTS)).addReg(SrcReg).addFrameIndex(FI) - .addImm(0).addImm(Pred); + .addImm(0).addImm(Pred).addReg(PredReg); } else { // move -> load unsigned DstReg = MI->getOperand(0).getReg(); NewMI = BuildMI(TII.get(ARM::FLDS), DstReg).addFrameIndex(FI) - .addImm(0).addImm(Pred); + .addImm(0).addImm(Pred).addReg(PredReg); } break; } case ARM::FCPYD: { unsigned Pred = MI->getOperand(2).getImmedValue(); + unsigned PredReg = MI->getOperand(3).getReg(); if (OpNum == 0) { // move -> store unsigned SrcReg = MI->getOperand(1).getReg(); NewMI = BuildMI(TII.get(ARM::FSTD)).addReg(SrcReg).addFrameIndex(FI) - .addImm(0).addImm(Pred); + .addImm(0).addImm(Pred).addReg(PredReg); } else { // move -> load unsigned DstReg = MI->getOperand(0).getReg(); NewMI = BuildMI(TII.get(ARM::FLDD), DstReg).addFrameIndex(FI) - .addImm(0).addImm(Pred); + .addImm(0).addImm(Pred).addReg(PredReg); } break; } @@ -426,9 +433,9 @@ static void emitARMRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, - unsigned DestReg, unsigned BaseReg, - ARMCC::CondCodes Pred, - int NumBytes, const TargetInstrInfo &TII) { + unsigned DestReg, unsigned BaseReg, int NumBytes, + ARMCC::CondCodes Pred, unsigned PredReg, + const TargetInstrInfo &TII) { bool isSub = NumBytes < 0; if (isSub) NumBytes = -NumBytes; @@ -447,7 +454,7 @@ // Build the new ADD / SUB. BuildMI(MBB, MBBI, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg) .addReg(BaseReg, false, false, true).addImm(SOImmVal) - .addImm((unsigned)Pred); + .addImm((unsigned)Pred).addReg(PredReg, false); BaseReg = DestReg; } } @@ -512,7 +519,7 @@ BuildMI(MBB, MBBI, TII.get(ARM::tNEG), LdReg) .addReg(LdReg, false, false, true); } else - emitLoadConstPool(MBB, MBBI, LdReg, ARMCC::AL, NumBytes, TII, true); + emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, ARMCC::AL, 0, TII, true); // Emit add / sub. int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr); @@ -632,12 +639,13 @@ static void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, - ARMCC::CondCodes Pred, int NumBytes, bool isThumb, - const TargetInstrInfo &TII) { + int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, + bool isThumb, const TargetInstrInfo &TII) { if (isThumb) emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII); else - emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, Pred, NumBytes, TII); + emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, + Pred, PredReg, TII); } void ARMRegisterInfo:: @@ -662,11 +670,12 @@ bool isThumb = AFI->isThumbFunction(); ARMCC::CondCodes Pred = isThumb ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(1).getImmedValue(); + unsigned PredReg = isThumb ? 0 : Old->getOperand(2).getReg(); if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { - emitSPUpdate(MBB, I, Pred, -Amount, isThumb, TII); + emitSPUpdate(MBB, I, -Amount, Pred, PredReg, isThumb, TII); } else { assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); - emitSPUpdate(MBB, I, Pred, Amount, isThumb, TII); + emitSPUpdate(MBB, I, Amount, Pred, PredReg, isThumb, TII); } } } @@ -944,7 +953,7 @@ if (FrameReg == ARM::SP) emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII); else { - emitLoadConstPool(MBB, II, TmpReg, ARMCC::AL, Offset, TII, true); + emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, TII, true); UseRR = true; } } else @@ -979,7 +988,7 @@ if (FrameReg == ARM::SP) emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII); else { - emitLoadConstPool(MBB, II, TmpReg, ARMCC::AL, Offset, TII, true); + emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, TII, true); UseRR = true; } } else @@ -1012,8 +1021,9 @@ int PIdx = MI.findFirstPredOperandIdx(); ARMCC::CondCodes Pred = (PIdx == -1) ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImmedValue(); - emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg, Pred, - isSub ? -Offset : Offset, TII); + unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); + emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg, + isSub ? -Offset : Offset, Pred, PredReg, TII); MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true); } } @@ -1315,11 +1325,11 @@ int FramePtrSpillFI = 0; if (VARegSaveSize) - emitSPUpdate(MBB, MBBI, ARMCC::AL, -VARegSaveSize, isThumb, TII); + emitSPUpdate(MBB, MBBI, -VARegSaveSize, ARMCC::AL, 0, isThumb, TII); if (!AFI->hasStackFrame()) { if (NumBytes != 0) - emitSPUpdate(MBB, MBBI, ARMCC::AL, -NumBytes, isThumb, TII); + emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, isThumb, TII); return; } @@ -1359,7 +1369,7 @@ if (!isThumb) { // Build the new SUBri to adjust SP for integer callee-save spill area 1. - emitSPUpdate(MBB, MBBI, ARMCC::AL, -GPRCS1Size, isThumb, TII); + emitSPUpdate(MBB, MBBI, -GPRCS1Size, ARMCC::AL, 0, isThumb, TII); movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 1, STI); } else if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) ++MBBI; @@ -1370,16 +1380,16 @@ MachineInstrBuilder MIB = BuildMI(MBB, MBBI, TII.get(isThumb ? ARM::tADDrSPi : ARM::ADDri),FramePtr) .addFrameIndex(FramePtrSpillFI).addImm(0); - if (!isThumb) MIB.addImm(ARMCC::AL); + if (!isThumb) MIB.addImm(ARMCC::AL).addReg(0); } if (!isThumb) { // Build the new SUBri to adjust SP for integer callee-save spill area 2. - emitSPUpdate(MBB, MBBI, ARMCC::AL, -GPRCS2Size, false, TII); + emitSPUpdate(MBB, MBBI, -GPRCS2Size, ARMCC::AL, 0, false, TII); // Build the new SUBri to adjust SP for FP callee-save spill area. movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 2, STI); - emitSPUpdate(MBB, MBBI, ARMCC::AL, -DPRCSSize, false, TII); + emitSPUpdate(MBB, MBBI, -DPRCSSize, ARMCC::AL, 0, false, TII); } // Determine starting offsets of spill areas. @@ -1396,7 +1406,7 @@ // Insert it after all the callee-save spills. if (!isThumb) movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 3, STI); - emitSPUpdate(MBB, MBBI, ARMCC::AL, -NumBytes, isThumb, TII); + emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, isThumb, TII); } if(STI.isTargetELF() && hasFP(MF)) { @@ -1439,7 +1449,7 @@ int NumBytes = (int)MFI->getStackSize(); if (!AFI->hasStackFrame()) { if (NumBytes != 0) - emitSPUpdate(MBB, MBBI, ARMCC::AL, NumBytes, isThumb, TII); + emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, isThumb, TII); } else { // Unwind MBBI to point to first LDR / FLDD. const unsigned *CSRegs = getCalleeSavedRegs(); @@ -1469,9 +1479,9 @@ &MBB.front() != MBBI && prior(MBBI)->getOpcode() == ARM::tPOP) { MachineBasicBlock::iterator PMBBI = prior(MBBI); - emitSPUpdate(MBB, PMBBI, ARMCC::AL, NumBytes, isThumb, TII); + emitSPUpdate(MBB, PMBBI, NumBytes, ARMCC::AL, 0, isThumb, TII); } else - emitSPUpdate(MBB, MBBI, ARMCC::AL, NumBytes, isThumb, TII); + emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, isThumb, TII); } } else { // Darwin ABI requires FP to point to the stack slot that contains the @@ -1486,27 +1496,27 @@ hasFP(MF)) if (NumBytes) BuildMI(MBB, MBBI, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr) - .addImm(NumBytes).addImm((unsigned)ARMCC::AL); + .addImm(NumBytes).addImm((unsigned)ARMCC::AL).addReg(0); else BuildMI(MBB, MBBI, TII.get(ARM::MOVr), ARM::SP).addReg(FramePtr) - .addImm((unsigned)ARMCC::AL); + .addImm((unsigned)ARMCC::AL).addReg(0); } else if (NumBytes) { - emitSPUpdate(MBB, MBBI, ARMCC::AL, NumBytes, false, TII); + emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, false, TII); } // Move SP to start of integer callee save spill area 2. movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 3, STI); - emitSPUpdate(MBB, MBBI, ARMCC::AL, AFI->getDPRCalleeSavedAreaSize(), + emitSPUpdate(MBB, MBBI, AFI->getDPRCalleeSavedAreaSize(), ARMCC::AL, 0, false, TII); // Move SP to start of integer callee save spill area 1. movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 2, STI); - emitSPUpdate(MBB, MBBI, ARMCC::AL, AFI->getGPRCalleeSavedArea2Size(), + emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea2Size(), ARMCC::AL, 0, false, TII); // Move SP to SP upon entry to the function. movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 1, STI); - emitSPUpdate(MBB, MBBI, ARMCC::AL, AFI->getGPRCalleeSavedArea1Size(), + emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea1Size(), ARMCC::AL, 0, false, TII); } } @@ -1517,7 +1527,7 @@ // FIXME: Verify this is still ok when R3 is no longer being reserved. BuildMI(MBB, MBBI, TII.get(ARM::tPOP)).addReg(ARM::R3); - emitSPUpdate(MBB, MBBI, ARMCC::AL, VARegSaveSize, isThumb, TII); + emitSPUpdate(MBB, MBBI, VARegSaveSize, ARMCC::AL, 0, isThumb, TII); if (isThumb) { BuildMI(MBB, MBBI, TII.get(ARM::tBX_RET_vararg)).addReg(ARM::R3); From evan.cheng at apple.com Thu Jul 5 02:13:33 2007 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 05 Jul 2007 07:13:33 -0000 Subject: [llvm-commits] [llvm] r37895 - in /llvm/trunk/lib/Target/ARM: ARMInstrInfo.td ARMInstrThumb.td ARMInstrVFP.td Message-ID: <200707050713.l657DXvI025199@zion.cs.uiuc.edu> Author: evancheng Date: Thu Jul 5 02:13:32 2007 New Revision: 37895 URL: http://llvm.org/viewvc/llvm-project?rev=37895&view=rev Log: Each ARM use predicate operand is now made up of two components. The new component is the CPSR register. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMInstrThumb.td llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=37895&r1=37894&r2=37895&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Jul 5 02:13:32 2007 @@ -279,13 +279,22 @@ let MIOperandInfo = (ops GPR, i32imm); } -// ARM branch / cmov condition code operand. -def ccop : Operand { +// ARM Predicate operand. Default to 14 = always (AL). Second part is CC +// register whose default is 0 (no register). +def pred : PredicateOperand { let PrintMethod = "printPredicateOperand"; } -// ARM Predicate operand. Default to 14 = always (AL). -def pred : PredicateOperand { +// Conditional code operand for conditional branches and conditional moves. +// No AlwaysVal value. +def ccop : ImmutablePredicateOperand { + let PrintMethod = "printPredicateOperand"; +} + +// Conditional code result for cmp, etc. +// +def cc_out : PredicateResultOperand { let PrintMethod = "printPredicateOperand"; } @@ -409,39 +418,54 @@ /// AI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a /// binop that produces a value. -multiclass AI1_bin_irs { +multiclass AI1_bin_irs { def ri : AI1<(ops GPR:$dst, GPR:$a, so_imm:$b), - opc, !strconcat(mod, " $dst, $a, $b"), + opc, " $dst, $a, $b", [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>; def rr : AI1<(ops GPR:$dst, GPR:$a, GPR:$b), - opc, !strconcat(mod, " $dst, $a, $b"), + opc, " $dst, $a, $b", [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>; def rs : AI1<(ops GPR:$dst, GPR:$a, so_reg:$b), - opc, !strconcat(mod, " $dst, $a, $b"), + opc, " $dst, $a, $b", [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>; } -/// AI1_bin0_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns. -/// Similar to AI1_bin_irs except the instruction does not produce a result. -multiclass AI1_bin0_irs { +/// AI1_bin_s_irs - Similar to AI1_bin_irs except it sets the 's' bit so the +/// instruction modifies the CSPR register. +multiclass AI1_bin_s_irs { + def ri : AI1<(ops GPR:$dst, GPR:$a, so_imm:$b), + opc, "s $dst, $a, $b", + [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>, Imp<[], [CPSR]>; + def rr : AI1<(ops GPR:$dst, GPR:$a, GPR:$b), + opc, "s $dst, $a, $b", + [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>, Imp<[], [CPSR]>; + def rs : AI1<(ops GPR:$dst, GPR:$a, so_reg:$b), + opc, "s $dst, $a, $b", + [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>, Imp<[], [CPSR]>; +} + +/// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test +/// patterns. Similar to AI1_bin_irs except the instruction does not produce +/// a explicit result, only implicitly set CPSR. +multiclass AI1_cmp_irs { def ri : AI1<(ops GPR:$a, so_imm:$b), opc, " $a, $b", - [(opnode GPR:$a, so_imm:$b)]>; + [(opnode GPR:$a, so_imm:$b)]>, Imp<[], [CPSR]>; def rr : AI1<(ops GPR:$a, GPR:$b), opc, " $a, $b", - [(opnode GPR:$a, GPR:$b)]>; + [(opnode GPR:$a, GPR:$b)]>, Imp<[], [CPSR]>; def rs : AI1<(ops GPR:$a, so_reg:$b), opc, " $a, $b", - [(opnode GPR:$a, so_reg:$b)]>; + [(opnode GPR:$a, so_reg:$b)]>, Imp<[], [CPSR]>; } /// AI1_bin_is - Defines a set of (op r, {so_imm|so_reg}) patterns for a binop. -multiclass AI1_bin_is { +multiclass AI1_bin_is { def ri : AI1<(ops GPR:$dst, GPR:$a, so_imm:$b), - opc, !strconcat(mod, " $dst, $a, $b"), + opc, " $dst, $a, $b", [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>; def rs : AI1<(ops GPR:$dst, GPR:$a, so_reg:$b), - opc, !strconcat(mod, " $dst, $a, $b"), + opc, " $dst, $a, $b", [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>; } @@ -518,6 +542,20 @@ class JTI2 pattern> : XI; +/// AXI1_bin_c_irs - Same as AI1_bin_irs but without the predicate operand and +/// setting carry bit. +multiclass AXI1_bin_c_irs { + def ri : AXI1<(ops GPR:$dst, GPR:$a, so_imm:$b), + !strconcat(opc, " $dst, $a, $b"), + [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>, Imp<[CPSR], []>; + def rr : AXI1<(ops GPR:$dst, GPR:$a, GPR:$b), + !strconcat(opc, " $dst, $a, $b"), + [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>, Imp<[CPSR], []>; + def rs : AXI1<(ops GPR:$dst, GPR:$a, so_reg:$b), + !strconcat(opc, " $dst, $a, $b"), + [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>, Imp<[CPSR], []>; +} + //===----------------------------------------------------------------------===// // Instructions //===----------------------------------------------------------------------===// @@ -619,7 +657,7 @@ let isCall = 1, noResults = 1, clobbersPred = 1, Defs = [R0, R1, R2, R3, R12, LR, - D0, D1, D2, D3, D4, D5, D6, D7] in { + D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in { def BL : AXI<(ops i32imm:$func, variable_ops), "bl ${func:call}", [(ARMcall tglobaladdr:$func)]>; @@ -662,8 +700,10 @@ } } + // FIXME: should be able to write a pattern for ARMBrcond, but can't use + // a two-value operand where a dag node expects two operands. :( def Bcc : AXI<(ops brtarget:$dst, ccop:$cc), "b$cc $dst", - [(ARMbrcond bb:$dst, imm:$cc)]>; + [/*(ARMbrcond bb:$dst, imm:$cc, CCR:$ccr)*/]>; } //===----------------------------------------------------------------------===// @@ -821,10 +861,10 @@ let clobbersPred = 1 in { def MOVsrl_flag : AI1<(ops GPR:$dst, GPR:$src), "mov", "s $dst, $src, lsr #1", - [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>; + [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, Imp<[], [CPSR]>; def MOVsra_flag : AI1<(ops GPR:$dst, GPR:$src), "mov", "s $dst, $src, asr #1", - [(set GPR:$dst, (ARMsra_flag GPR:$src))]>; + [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, Imp<[], [CPSR]>; } def MOVrx : AI1<(ops GPR:$dst, GPR:$src), "mov", " $dst, $src, rrx", @@ -873,22 +913,39 @@ // Arithmetic Instructions. // -defm ADD : AI1_bin_irs<"add", "" , BinOpFrag<(add node:$LHS, node:$RHS)>>; -defm ADC : AI1_bin_irs<"adc", "" , BinOpFrag<(adde node:$LHS, node:$RHS)>>; -defm SUB : AI1_bin_irs<"sub", "" , BinOpFrag<(sub node:$LHS, node:$RHS)>>; -defm SBC : AI1_bin_irs<"sbc", "" , BinOpFrag<(sube node:$LHS, node:$RHS)>>; +defm ADD : AI1_bin_irs<"add", BinOpFrag<(add node:$LHS, node:$RHS)>>; +defm SUB : AI1_bin_irs<"sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>; +// ADD and SUB with 's' bit set. let clobbersPred = 1 in { -defm ADDS : AI1_bin_irs<"add", "s", BinOpFrag<(addc node:$LHS, node:$RHS)>>; -defm SUBS : AI1_bin_irs<"sub", "s", BinOpFrag<(subc node:$LHS, node:$RHS)>>; +defm ADDS : AI1_bin_s_irs<"add", BinOpFrag<(addc node:$LHS, node:$RHS)>>; +defm SUBS : AI1_bin_s_irs<"sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>; } +// FIXME: Do not allow ADC / SBC to be predicated for now. +defm ADC : AXI1_bin_c_irs<"adc", BinOpFrag<(adde node:$LHS, node:$RHS)>>; +defm SBC : AXI1_bin_c_irs<"sbc", BinOpFrag<(sube node:$LHS, node:$RHS)>>; + // These don't define reg/reg forms, because they are handled above. -defm RSB : AI1_bin_is <"rsb", "" , BinOpFrag<(sub node:$RHS, node:$LHS)>>; -defm RSC : AI1_bin_is <"rsc", "" , BinOpFrag<(sube node:$RHS, node:$LHS)>>; +defm RSB : AI1_bin_is <"rsb", BinOpFrag<(sub node:$RHS, node:$LHS)>>; + +// RSB with 's' bit set. +let clobbersPred = 1 in { +def RSBSri : AI1<(ops GPR:$dst, GPR:$a, so_imm:$b), + "rsb", "s $dst, $a, $b", + [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]>, Imp<[], [CPSR]>; +def RSBSrs : AI1<(ops GPR:$dst, GPR:$a, so_reg:$b), + "rsb", "s $dst, $a, $b", + [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]>, Imp<[], [CPSR]>; +} -let clobbersPred = 1 in -defm RSBS : AI1_bin_is <"rsb", "s", BinOpFrag<(subc node:$RHS, node:$LHS)>>; +// FIXME: Do not allow RSC to be predicated for now. +def RSCri : AXI1<(ops GPR:$dst, GPR:$a, so_imm:$b), + "rsc $dst, $a, $b", + [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>, Imp<[CPSR], []>; +def RSCrs : AXI1<(ops GPR:$dst, GPR:$a, so_reg:$b), + "rsc $dst, $a, $b", + [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>, Imp<[CPSR], []>; // (sub X, imm) gets canonicalized to (add X, -imm). Match this form. def : ARMPat<(add GPR:$src, so_imm_neg:$imm), @@ -910,10 +967,10 @@ // Bitwise Instructions. // -defm AND : AI1_bin_irs<"and", "", BinOpFrag<(and node:$LHS, node:$RHS)>>; -defm ORR : AI1_bin_irs<"orr", "", BinOpFrag<(or node:$LHS, node:$RHS)>>; -defm EOR : AI1_bin_irs<"eor", "", BinOpFrag<(xor node:$LHS, node:$RHS)>>; -defm BIC : AI1_bin_irs<"bic", "", BinOpFrag<(and node:$LHS, (not node:$RHS))>>; +defm AND : AI1_bin_irs<"and", BinOpFrag<(and node:$LHS, node:$RHS)>>; +defm ORR : AI1_bin_irs<"orr", BinOpFrag<(or node:$LHS, node:$RHS)>>; +defm EOR : AI1_bin_irs<"eor", BinOpFrag<(xor node:$LHS, node:$RHS)>>; +defm BIC : AI1_bin_irs<"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>; def MVNr : AI<(ops GPR:$dst, GPR:$src), "mvn", " $dst, $src", [(set GPR:$dst, (not GPR:$src))]>; @@ -1114,15 +1171,15 @@ // let clobbersPred = 1 in { -defm CMP : AI1_bin0_irs<"cmp", BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>; -defm CMN : AI1_bin0_irs<"cmn", BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>; +defm CMP : AI1_cmp_irs<"cmp", BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>; +defm CMN : AI1_cmp_irs<"cmn", BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>; // Note that TST/TEQ don't set all the same flags that CMP does! -defm TST : AI1_bin0_irs<"tst", BinOpFrag<(ARMcmpNZ (and node:$LHS, node:$RHS), 0)>>; -defm TEQ : AI1_bin0_irs<"teq", BinOpFrag<(ARMcmpNZ (xor node:$LHS, node:$RHS), 0)>>; +defm TST : AI1_cmp_irs<"tst", BinOpFrag<(ARMcmpNZ (and node:$LHS, node:$RHS), 0)>>; +defm TEQ : AI1_cmp_irs<"teq", BinOpFrag<(ARMcmpNZ (xor node:$LHS, node:$RHS), 0)>>; -defm CMPnz : AI1_bin0_irs<"cmp", BinOpFrag<(ARMcmpNZ node:$LHS, node:$RHS)>>; -defm CMNnz : AI1_bin0_irs<"cmn", BinOpFrag<(ARMcmpNZ node:$LHS,(ineg node:$RHS))>>; +defm CMPnz : AI1_cmp_irs<"cmp", BinOpFrag<(ARMcmpNZ node:$LHS, node:$RHS)>>; +defm CMNnz : AI1_cmp_irs<"cmn", BinOpFrag<(ARMcmpNZ node:$LHS,(ineg node:$RHS))>>; } def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm), @@ -1133,20 +1190,22 @@ // Conditional moves +// FIXME: should be able to write a pattern for ARMcmov, but can't use +// a two-value operand where a dag node expects two operands. :( def MOVCCr : AXI<(ops GPR:$dst, GPR:$false, GPR:$true, ccop:$cc), - "mov$cc $dst, $true", - [(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc))]>, - RegConstraint<"$false = $dst">; + "mov$cc $dst, $true", + [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>, + RegConstraint<"$false = $dst">; def MOVCCs : AXI<(ops GPR:$dst, GPR:$false, so_reg:$true, ccop:$cc), - "mov$cc $dst, $true", - [(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true,imm:$cc))]>, - RegConstraint<"$false = $dst">; + "mov$cc $dst, $true", + [/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>, + RegConstraint<"$false = $dst">; def MOVCCi : AXI<(ops GPR:$dst, GPR:$false, so_imm:$true, ccop:$cc), - "mov$cc $dst, $true", - [(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true,imm:$cc))]>, - RegConstraint<"$false = $dst">; + "mov$cc $dst, $true", + [/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>, + RegConstraint<"$false = $dst">; // LEApcrel - Load a pc-relative address into a register without offending the Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=37895&r1=37894&r2=37895&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Thu Jul 5 02:13:32 2007 @@ -223,9 +223,11 @@ } } +// FIXME: should be able to write a pattern for ARMBrcond, but can't use +// a two-value operand where a dag node expects two operands. :( let isBranch = 1, isTerminator = 1, noResults = 1 in def tBcc : TI<(ops brtarget:$dst, ccop:$cc), "b$cc $dst", - [(ARMbrcond bb:$dst, imm:$cc)]>; + [/*(ARMbrcond bb:$dst, imm:$cc)*/]>; //===----------------------------------------------------------------------===// // Load Store Instructions. @@ -522,7 +524,7 @@ def tMOVCCr : PseudoInst<(ops GPR:$dst, GPR:$false, GPR:$true, ccop:$cc), "@ tMOVCCr $cc", - [(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc))]>; + [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc))*/]>; // tLEApcrel - Load a pc-relative address into a register without offending the // assembler. Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=37895&r1=37894&r2=37895&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Thu Jul 5 02:13:32 2007 @@ -216,12 +216,10 @@ [(set SPR:$dst, (fround DPR:$a))]>; def FCPYD : ADI<(ops DPR:$dst, DPR:$a), - "fcpyd", " $dst, $a", - [/*(set DPR:$dst, DPR:$a)*/]>; + "fcpyd", " $dst, $a", []>; def FCPYS : ASI<(ops SPR:$dst, SPR:$a), - "fcpys", " $dst, $a", - [/*(set SPR:$dst, SPR:$a)*/]>; + "fcpys", " $dst, $a", []>; def FNEGD : ADI<(ops DPR:$dst, DPR:$a), "fnegd", " $dst, $a", @@ -278,7 +276,7 @@ // FMSRR: GPR -> SPR let clobbersPred = 1 in -def FMSTAT : ASI<(ops), "fmstat", "", [(arm_fmstat)]>; +def FMSTAT : ASI<(ops), "fmstat", "", [(arm_fmstat)]>, Imp<[], [CPSR]>; // FMXR: GPR -> VFP Sstem reg @@ -369,21 +367,21 @@ // def FCPYDcc : AXDI<(ops DPR:$dst, DPR:$false, DPR:$true, ccop:$cc), - "fcpyd$cc $dst, $true", - [(set DPR:$dst, (ARMcmov DPR:$false, DPR:$true, imm:$cc))]>, - RegConstraint<"$false = $dst">; + "fcpyd$cc $dst, $true", + [/*(set DPR:$dst, (ARMcmov DPR:$false, DPR:$true, imm:$cc))*/]>, + RegConstraint<"$false = $dst">; def FCPYScc : AXSI<(ops SPR:$dst, SPR:$false, SPR:$true, ccop:$cc), - "fcpys$cc $dst, $true", - [(set SPR:$dst, (ARMcmov SPR:$false, SPR:$true, imm:$cc))]>, - RegConstraint<"$false = $dst">; + "fcpys$cc $dst, $true", + [/*(set SPR:$dst, (ARMcmov SPR:$false, SPR:$true, imm:$cc))*/]>, + RegConstraint<"$false = $dst">; def FNEGDcc : AXDI<(ops DPR:$dst, DPR:$false, DPR:$true, ccop:$cc), - "fnegd$cc $dst, $true", - [(set DPR:$dst, (ARMcneg DPR:$false, DPR:$true, imm:$cc))]>, - RegConstraint<"$false = $dst">; + "fnegd$cc $dst, $true", + [/*(set DPR:$dst, (ARMcneg DPR:$false, DPR:$true, imm:$cc))*/]>, + RegConstraint<"$false = $dst">; def FNEGScc : AXSI<(ops SPR:$dst, SPR:$false, SPR:$true, ccop:$cc), - "fnegs$cc $dst, $true", - [(set SPR:$dst, (ARMcneg SPR:$false, SPR:$true, imm:$cc))]>, - RegConstraint<"$false = $dst">; + "fnegs$cc $dst, $true", + [/*(set SPR:$dst, (ARMcneg SPR:$false, SPR:$true, imm:$cc))*/]>, + RegConstraint<"$false = $dst">; From evan.cheng at apple.com Thu Jul 5 02:15:28 2007 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 05 Jul 2007 07:15:28 -0000 Subject: [llvm-commits] [llvm] r37896 - /llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Message-ID: <200707050715.l657FSRx026033@zion.cs.uiuc.edu> Author: evancheng Date: Thu Jul 5 02:15:27 2007 New Revision: 37896 URL: http://llvm.org/viewvc/llvm-project?rev=37896&view=rev Log: Unfortunately we now require C++ code to isel Bcc, conditional moves, etc. Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=37896&r1=37895&r2=37896&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Thu Jul 5 02:15:27 2007 @@ -524,8 +524,8 @@ return true; } -/// getDefaultPred - Returns a ARMCC::AL immediate node. -static inline SDOperand getDefaultPred(SelectionDAG *CurDAG) { +/// getAL - Returns a ARMCC::AL immediate node. +static inline SDOperand getAL(SelectionDAG *CurDAG) { return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32); } @@ -564,10 +564,11 @@ CPIdx, CurDAG->getRegister(0, MVT::i32), CurDAG->getTargetConstant(0, MVT::i32), - getDefaultPred(CurDAG), + getAL(CurDAG), + CurDAG->getRegister(0, MVT::i32), CurDAG->getEntryNode() }; - ResNode=CurDAG->getTargetNode(ARM::LDRcp, MVT::i32, MVT::Other, Ops, 5); + ResNode=CurDAG->getTargetNode(ARM::LDRcp, MVT::i32, MVT::Other, Ops, 6); } ReplaceUses(Op, SDOperand(ResNode, 0)); return NULL; @@ -583,10 +584,11 @@ if (Subtarget->isThumb()) return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI, CurDAG->getTargetConstant(0, MVT::i32)); - else - return CurDAG->SelectNodeTo(N, ARM::ADDri, MVT::i32, TFI, - CurDAG->getTargetConstant(0, MVT::i32), - getDefaultPred(CurDAG)); + else { + SDOperand Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32), + getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) }; + return CurDAG->SelectNodeTo(N, ARM::ADDri, MVT::i32, Ops, 4); + } } case ISD::ADD: { // Select add sp, c to tADDhirr. @@ -617,9 +619,10 @@ unsigned ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, Log2_32(RHSV-1)); SDOperand Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32), CurDAG->getTargetConstant(ShImm, MVT::i32), - getDefaultPred(CurDAG) +