From resistor at mac.com Mon Dec 31 00:32:01 2007 From: resistor at mac.com (Owen Anderson) Date: Mon, 31 Dec 2007 06:32:01 -0000 Subject: [llvm-commits] [llvm] r45470 - in /llvm/trunk: include/llvm/Target/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/CellSPU/ lib/Target/IA64/ lib/Target/Mips/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/X86/ Message-ID: <200712310632.lBV6W2to002259@zion.cs.uiuc.edu> Author: resistor Date: Mon Dec 31 00:32:00 2007 New Revision: 45470 URL: http://llvm.org/viewvc/llvm-project?rev=45470&view=rev Log: Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of the Machine-level API cleanup instigated by Chris. Modified: llvm/trunk/include/llvm/Target/MRegisterInfo.h llvm/trunk/include/llvm/Target/TargetInstrInfo.h llvm/trunk/lib/CodeGen/LowerSubregs.cpp llvm/trunk/lib/CodeGen/PHIElimination.cpp llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp llvm/trunk/lib/CodeGen/VirtRegMap.cpp llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp llvm/trunk/lib/Target/ARM/ARMInstrInfo.h llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp llvm/trunk/lib/Target/IA64/IA64InstrInfo.cpp llvm/trunk/lib/Target/IA64/IA64InstrInfo.h llvm/trunk/lib/Target/IA64/IA64RegisterInfo.cpp llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp llvm/trunk/lib/Target/Mips/MipsInstrInfo.h llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp llvm/trunk/lib/Target/X86/X86InstrInfo.cpp llvm/trunk/lib/Target/X86/X86InstrInfo.h llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Modified: llvm/trunk/include/llvm/Target/MRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/MRegisterInfo.h?rev=45470&r1=45469&r2=45470&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/MRegisterInfo.h (original) +++ llvm/trunk/include/llvm/Target/MRegisterInfo.h Mon Dec 31 00:32:00 2007 @@ -510,12 +510,6 @@ const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const =0; - virtual void copyRegToReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *DestRC, - const TargetRegisterClass *SrcRC) const = 0; - /// getCrossCopyRegClass - Returns a legal register class to copy a register /// in the specified class to or from. Returns NULL if it is possible to copy /// between a two registers of the specified class. Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=45470&r1=45469&r2=45470&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Mon Dec 31 00:32:00 2007 @@ -458,6 +458,15 @@ return 0; } + /// copyRegToReg - Add a copy between a pair of registers + virtual void copyRegToReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const { + assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!"); + } + /// BlockHasNoFallThrough - Return true if the specified block does not /// fall-through into its successor block. This is primarily used when a /// branch is unanalyzable. It is useful for things like unconditional Modified: llvm/trunk/lib/CodeGen/LowerSubregs.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LowerSubregs.cpp?rev=45470&r1=45469&r2=45470&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LowerSubregs.cpp (original) +++ llvm/trunk/lib/CodeGen/LowerSubregs.cpp Mon Dec 31 00:32:00 2007 @@ -63,6 +63,7 @@ MachineBasicBlock *MBB = MI->getParent(); MachineFunction &MF = *MBB->getParent(); const MRegisterInfo &MRI = *MF.getTarget().getRegisterInfo(); + const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); assert(MI->getOperand(0).isRegister() && MI->getOperand(0).isDef() && MI->getOperand(1).isRegister() && MI->getOperand(1).isUse() && @@ -88,7 +89,7 @@ assert(TRC == getPhysicalRegisterRegClass(MRI, SrcReg) && "Extract subreg and Dst must be of same register class"); - MRI.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC, TRC); + TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC, TRC); MachineBasicBlock::iterator dMI = MI; DOUT << "subreg: " << *(--dMI); } @@ -103,6 +104,7 @@ MachineBasicBlock *MBB = MI->getParent(); MachineFunction &MF = *MBB->getParent(); const MRegisterInfo &MRI = *MF.getTarget().getRegisterInfo(); + const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); unsigned DstReg = 0; unsigned SrcReg = 0; unsigned InsReg = 0; @@ -157,7 +159,7 @@ } else { TRC1 = MF.getRegInfo().getRegClass(InsReg); } - MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1); + TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1); #ifndef NDEBUG MachineBasicBlock::iterator dMI = MI; @@ -184,7 +186,7 @@ assert(TRC0 == getPhysicalRegisterRegClass(MRI, SrcReg) && "Insert superreg and Dst must be of same register class"); - MRI.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC0, TRC0); + TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC0, TRC0); #ifndef NDEBUG MachineBasicBlock::iterator dMI = MI; @@ -206,7 +208,7 @@ } else { TRC1 = MF.getRegInfo().getRegClass(InsReg); } - MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1); + TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1); #ifndef NDEBUG MachineBasicBlock::iterator dMI = MI; Modified: llvm/trunk/lib/CodeGen/PHIElimination.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PHIElimination.cpp?rev=45470&r1=45469&r2=45470&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PHIElimination.cpp (original) +++ llvm/trunk/lib/CodeGen/PHIElimination.cpp Mon Dec 31 00:32:00 2007 @@ -134,8 +134,8 @@ // after any remaining phi nodes) which copies the new incoming register // into the phi node destination. // - const MRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); - RegInfo->copyRegToReg(MBB, AfterPHIsIt, DestReg, IncomingReg, RC, RC); + const TargetInstrInfo *TII = MF.getTarget().getInstrInfo(); + TII->copyRegToReg(MBB, AfterPHIsIt, DestReg, IncomingReg, RC, RC); // Update live variable information if there is any... LiveVariables *LV = getAnalysisToUpdate(); @@ -201,7 +201,7 @@ MachineBasicBlock::iterator I = opBlock.getFirstTerminator(); // Insert the copy. - RegInfo->copyRegToReg(opBlock, I, IncomingReg, SrcReg, RC, RC); + TII->copyRegToReg(opBlock, I, IncomingReg, SrcReg, RC, RC); // Now update live variable information if we have it. Otherwise we're done if (!LV) continue; Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp?rev=45470&r1=45469&r2=45470&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Mon Dec 31 00:32:00 2007 @@ -359,7 +359,7 @@ } else { // Create the reg, emit the copy. VRBase = RegInfo.createVirtualRegister(TRC); - MRI->copyRegToReg(*BB, BB->end(), VRBase, SrcReg, TRC, TRC); + TII->copyRegToReg(*BB, BB->end(), VRBase, SrcReg, TRC, TRC); } if (InstanceNo > 0) @@ -751,7 +751,7 @@ TRC = MRI->getPhysicalRegisterRegClass(Node->getOperand(2).getValueType(), InReg); - MRI->copyRegToReg(*BB, BB->end(), DestReg, InReg, TRC, TRC); + TII->copyRegToReg(*BB, BB->end(), DestReg, InReg, TRC, TRC); } break; } @@ -848,7 +848,7 @@ } } assert(I->Reg && "Unknown physical register!"); - MRI->copyRegToReg(*BB, BB->end(), Reg, VRI->second, + TII->copyRegToReg(*BB, BB->end(), Reg, VRI->second, SU->CopyDstRC, SU->CopySrcRC); } else { // Copy from physical register. @@ -856,7 +856,7 @@ unsigned VRBase = RegInfo.createVirtualRegister(SU->CopyDstRC); bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase)); assert(isNew && "Node emitted out of order - early"); - MRI->copyRegToReg(*BB, BB->end(), VRBase, I->Reg, + TII->copyRegToReg(*BB, BB->end(), VRBase, I->Reg, SU->CopyDstRC, SU->CopySrcRC); } break; @@ -874,7 +874,7 @@ E = RegInfo.livein_end(); LI != E; ++LI) if (LI->second) { const TargetRegisterClass *RC = RegInfo.getRegClass(LI->second); - MRI->copyRegToReg(*MF.begin(), MF.begin()->end(), LI->second, + TII->copyRegToReg(*MF.begin(), MF.begin()->end(), LI->second, LI->first, RC, RC); } } Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=45470&r1=45469&r2=45470&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp (original) +++ llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Mon Dec 31 00:32:00 2007 @@ -80,7 +80,6 @@ DOUT << "Machine Function\n"; const TargetMachine &TM = MF.getTarget(); const TargetInstrInfo &TII = *TM.getInstrInfo(); - const MRegisterInfo &MRI = *TM.getRegisterInfo(); LiveVariables &LV = getAnalysis(); bool MadeChange = false; @@ -193,7 +192,7 @@ InstructionRearranged: const TargetRegisterClass* rc = MF.getRegInfo().getRegClass(regA); - MRI.copyRegToReg(*mbbi, mi, regA, regB, rc, rc); + TII.copyRegToReg(*mbbi, mi, regA, regB, rc, rc); MachineBasicBlock::iterator prevMi = prior(mi); DOUT << "\t\tprepend:\t"; DEBUG(prevMi->print(*cerr.stream(), &TM)); Modified: llvm/trunk/lib/CodeGen/VirtRegMap.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/VirtRegMap.cpp?rev=45470&r1=45469&r2=45470&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/VirtRegMap.cpp (original) +++ llvm/trunk/lib/CodeGen/VirtRegMap.cpp Mon Dec 31 00:32:00 2007 @@ -928,7 +928,7 @@ DOUT << MBB.getBasicBlock()->getName() << ":\n"; MachineFunction &MF = *MBB.getParent(); - + // Spills - Keep track of which spilled values are available in physregs so // that we can choose to reuse the physregs instead of emitting reloads. AvailableSpills Spills(MRI, TII); @@ -1182,7 +1182,7 @@ const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg); RegInfo->setPhysRegUsed(DesignatedReg); ReusedOperands.markClobbered(DesignatedReg); - MRI->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC, RC); + TII->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC, RC); MachineInstr *CopyMI = prior(MII); UpdateKills(*CopyMI, RegKills, KillOps); @@ -1268,7 +1268,7 @@ DOUT << "Promoted Load To Copy: " << MI; if (DestReg != InReg) { const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg); - MRI->copyRegToReg(MBB, &MI, DestReg, InReg, RC, RC); + TII->copyRegToReg(MBB, &MI, DestReg, InReg, RC, RC); // Revisit the copy so we make sure to notice the effects of the // operation on the destreg (either needing to RA it if it's // virtual or needing to clobber any values if it's physical). Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp?rev=45470&r1=45469&r2=45470&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp Mon Dec 31 00:32:00 2007 @@ -27,6 +27,16 @@ static cl::opt EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden, cl::desc("Enable ARM 2-addr to 3-addr conv")); +static inline +const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) { + return MIB.addImm((int64_t)ARMCC::AL).addReg(0); +} + +static inline +const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) { + return MIB.addReg(0); +} + ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI) : TargetInstrInfo(ARMInsts, array_lengthof(ARMInsts)), RI(*this, STI) { @@ -432,6 +442,34 @@ return 2; } +void ARMInstrInfo::copyRegToReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator I, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const { + if (DestRC != SrcRC) { + cerr << "Not yet supported!"; + abort(); + } + + if (DestRC == ARM::GPRRegisterClass) { + MachineFunction &MF = *MBB.getParent(); + ARMFunctionInfo *AFI = MF.getInfo(); + if (AFI->isThumbFunction()) + BuildMI(MBB, I, get(ARM::tMOVr), DestReg).addReg(SrcReg); + else + AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, get(ARM::MOVr), DestReg) + .addReg(SrcReg))); + } else if (DestRC == ARM::SPRRegisterClass) + AddDefaultPred(BuildMI(MBB, I, get(ARM::FCPYS), DestReg) + .addReg(SrcReg)); + else if (DestRC == ARM::DPRRegisterClass) + AddDefaultPred(BuildMI(MBB, I, get(ARM::FCPYD), DestReg) + .addReg(SrcReg)); + else + abort(); +} + bool ARMInstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const { if (MBB.empty()) return false; Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.h?rev=45470&r1=45469&r2=45470&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.h Mon Dec 31 00:32:00 2007 @@ -160,6 +160,11 @@ virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const std::vector &Cond) const; + virtual void copyRegToReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator I, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const; virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const; virtual bool ReverseBranchCondition(std::vector &Cond) const; Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp?rev=45470&r1=45469&r2=45470&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp Mon Dec 31 00:32:00 2007 @@ -270,34 +270,6 @@ return; } -void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, - unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *DestRC, - const TargetRegisterClass *SrcRC) const { - if (DestRC != SrcRC) { - cerr << "Not yet supported!"; - abort(); - } - - if (DestRC == ARM::GPRRegisterClass) { - MachineFunction &MF = *MBB.getParent(); - ARMFunctionInfo *AFI = MF.getInfo(); - if (AFI->isThumbFunction()) - BuildMI(MBB, I, TII.get(ARM::tMOVr), DestReg).addReg(SrcReg); - else - AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, TII.get(ARM::MOVr), DestReg) - .addReg(SrcReg))); - } else if (DestRC == ARM::SPRRegisterClass) - AddDefaultPred(BuildMI(MBB, I, TII.get(ARM::FCPYS), DestReg) - .addReg(SrcReg)); - else if (DestRC == ARM::DPRRegisterClass) - AddDefaultPred(BuildMI(MBB, I, TII.get(ARM::FCPYD), DestReg) - .addReg(SrcReg)); - else - abort(); -} - /// emitLoadConstPool - Emits a load from constpool to materialize the /// specified immediate. static void emitLoadConstPool(MachineBasicBlock &MBB, Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp?rev=45470&r1=45469&r2=45470&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp Mon Dec 31 00:32:00 2007 @@ -132,6 +132,29 @@ return 2; } +void AlphaInstrInfo::copyRegToReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const { + //cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n"; + if (DestRC != SrcRC) { + cerr << "Not yet supported!"; + abort(); + } + + if (DestRC == Alpha::GPRCRegisterClass) { + BuildMI(MBB, MI, get(Alpha::BISr), DestReg).addReg(SrcReg).addReg(SrcReg); + } else if (DestRC == Alpha::F4RCRegisterClass) { + BuildMI(MBB, MI, get(Alpha::CPYSS), DestReg).addReg(SrcReg).addReg(SrcReg); + } else if (DestRC == Alpha::F8RCRegisterClass) { + BuildMI(MBB, MI, get(Alpha::CPYST), DestReg).addReg(SrcReg).addReg(SrcReg); + } else { + cerr << "Attempt to copy register that is not GPR or FPR"; + abort(); + } +} + static unsigned AlphaRevCondCode(unsigned Opcode) { switch (Opcode) { case Alpha::BEQ: return Alpha::BNE; Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h?rev=45470&r1=45469&r2=45470&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h (original) +++ llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h Mon Dec 31 00:32:00 2007 @@ -42,6 +42,11 @@ virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const std::vector &Cond) const; + virtual void copyRegToReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const; bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, std::vector &Cond) const; Modified: llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp?rev=45470&r1=45469&r2=45470&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp Mon Dec 31 00:32:00 2007 @@ -190,30 +190,6 @@ return 0; } - -void AlphaRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *DestRC, - const TargetRegisterClass *SrcRC) const { - //cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n"; - if (DestRC != SrcRC) { - cerr << "Not yet supported!"; - abort(); - } - - if (DestRC == Alpha::GPRCRegisterClass) { - BuildMI(MBB, MI, TII.get(Alpha::BISr), DestReg).addReg(SrcReg).addReg(SrcReg); - } else if (DestRC == Alpha::F4RCRegisterClass) { - BuildMI(MBB, MI, TII.get(Alpha::CPYSS), DestReg).addReg(SrcReg).addReg(SrcReg); - } else if (DestRC == Alpha::F8RCRegisterClass) { - BuildMI(MBB, MI, TII.get(Alpha::CPYST), DestReg).addReg(SrcReg).addReg(SrcReg); - } else { - cerr << "Attempt to copy register that is not GPR or FPR"; - abort(); - } -} - void AlphaRegisterInfo::reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp?rev=45470&r1=45469&r2=45470&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp Mon Dec 31 00:32:00 2007 @@ -180,3 +180,40 @@ } return 0; } + +void SPUInstrInfo::copyRegToReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const +{ + if (DestRC != SrcRC) { + cerr << "SPURegisterInfo::copyRegToReg(): DestRC != SrcRC not supported!\n"; + abort(); + } + + if (DestRC == SPU::R8CRegisterClass) { + BuildMI(MBB, MI, get(SPU::ORBIr8), DestReg).addReg(SrcReg).addImm(0); + } else if (DestRC == SPU::R16CRegisterClass) { + BuildMI(MBB, MI, get(SPU::ORHIr16), DestReg).addReg(SrcReg).addImm(0); + } else if (DestRC == SPU::R32CRegisterClass) { + BuildMI(MBB, MI, get(SPU::ORIr32), DestReg).addReg(SrcReg).addImm(0); + } else if (DestRC == SPU::R32FPRegisterClass) { + BuildMI(MBB, MI, get(SPU::ORf32), DestReg).addReg(SrcReg) + .addReg(SrcReg); + } else if (DestRC == SPU::R64CRegisterClass) { + BuildMI(MBB, MI, get(SPU::ORIr64), DestReg).addReg(SrcReg).addImm(0); + } else if (DestRC == SPU::R64FPRegisterClass) { + BuildMI(MBB, MI, get(SPU::ORf64), DestReg).addReg(SrcReg) + .addReg(SrcReg); + } else if (DestRC == SPU::GPRCRegisterClass) { + BuildMI(MBB, MI, get(SPU::ORgprc), DestReg).addReg(SrcReg) + .addReg(SrcReg); + } else if (DestRC == SPU::VECREGRegisterClass) { + BuildMI(MBB, MI, get(SPU::ORv4i32), DestReg).addReg(SrcReg) + .addReg(SrcReg); + } else { + std::cerr << "Attempt to copy unknown/unsupported register class!\n"; + abort(); + } +} Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h?rev=45470&r1=45469&r2=45470&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h (original) +++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h Mon Dec 31 00:32:00 2007 @@ -46,6 +46,12 @@ unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const; unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const; + + virtual void copyRegToReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const; }; } Modified: llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp?rev=45470&r1=45469&r2=45470&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp Mon Dec 31 00:32:00 2007 @@ -360,43 +360,6 @@ } } -void SPURegisterInfo::copyRegToReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *DestRC, - const TargetRegisterClass *SrcRC) const -{ - if (DestRC != SrcRC) { - cerr << "SPURegisterInfo::copyRegToReg(): DestRC != SrcRC not supported!\n"; - abort(); - } - - if (DestRC == SPU::R8CRegisterClass) { - BuildMI(MBB, MI, TII.get(SPU::ORBIr8), DestReg).addReg(SrcReg).addImm(0); - } else if (DestRC == SPU::R16CRegisterClass) { - BuildMI(MBB, MI, TII.get(SPU::ORHIr16), DestReg).addReg(SrcReg).addImm(0); - } else if (DestRC == SPU::R32CRegisterClass) { - BuildMI(MBB, MI, TII.get(SPU::ORIr32), DestReg).addReg(SrcReg).addImm(0); - } else if (DestRC == SPU::R32FPRegisterClass) { - BuildMI(MBB, MI, TII.get(SPU::ORf32), DestReg).addReg(SrcReg) - .addReg(SrcReg); - } else if (DestRC == SPU::R64CRegisterClass) { - BuildMI(MBB, MI, TII.get(SPU::ORIr64), DestReg).addReg(SrcReg).addImm(0); - } else if (DestRC == SPU::R64FPRegisterClass) { - BuildMI(MBB, MI, TII.get(SPU::ORf64), DestReg).addReg(SrcReg) - .addReg(SrcReg); - } else if (DestRC == SPU::GPRCRegisterClass) { - BuildMI(MBB, MI, TII.get(SPU::ORgprc), DestReg).addReg(SrcReg) - .addReg(SrcReg); - } else if (DestRC == SPU::VECREGRegisterClass) { - BuildMI(MBB, MI, TII.get(SPU::ORv4i32), DestReg).addReg(SrcReg) - .addReg(SrcReg); - } else { - std::cerr << "Attempt to copy unknown/unsupported register class!\n"; - abort(); - } -} - void SPURegisterInfo::reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, Modified: llvm/trunk/lib/Target/IA64/IA64InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64InstrInfo.cpp?rev=45470&r1=45469&r2=45470&view=diff ============================================================================== --- llvm/trunk/lib/Target/IA64/IA64InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/IA64/IA64InstrInfo.cpp Mon Dec 31 00:32:00 2007 @@ -56,3 +56,21 @@ BuildMI(&MBB, get(IA64::BRL_NOTCALL)).addMBB(TBB); return 1; } + +void IA64InstrInfo::copyRegToReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const { + if (DestRC != SrcRC) { + cerr << "Not yet supported!"; + abort(); + } + + if(DestRC == IA64::PRRegisterClass ) // if a bool, we use pseudocode + // (SrcReg) DestReg = cmp.eq.unc(r0, r0) + BuildMI(MBB, MI, get(IA64::PCMPEQUNC), DestReg) + .addReg(IA64::r0).addReg(IA64::r0).addReg(SrcReg); + else // otherwise, MOV works (for both gen. regs and FP regs) + BuildMI(MBB, MI, get(IA64::MOV), DestReg).addReg(SrcReg); +} Modified: llvm/trunk/lib/Target/IA64/IA64InstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64InstrInfo.h?rev=45470&r1=45469&r2=45470&view=diff ============================================================================== --- llvm/trunk/lib/Target/IA64/IA64InstrInfo.h (original) +++ llvm/trunk/lib/Target/IA64/IA64InstrInfo.h Mon Dec 31 00:32:00 2007 @@ -40,7 +40,11 @@ virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const std::vector &Cond) const; - + virtual void copyRegToReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const; }; } // End llvm namespace Modified: llvm/trunk/lib/Target/IA64/IA64RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64RegisterInfo.cpp?rev=45470&r1=45469&r2=45470&view=diff ============================================================================== --- llvm/trunk/lib/Target/IA64/IA64RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/IA64/IA64RegisterInfo.cpp Mon Dec 31 00:32:00 2007 @@ -144,24 +144,6 @@ return; } -void IA64RegisterInfo::copyRegToReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *DestRC, - const TargetRegisterClass *SrcRC) const { - if (DestRC != SrcRC) { - cerr << "Not yet supported!"; - abort(); - } - - if(DestRC == IA64::PRRegisterClass ) // if a bool, we use pseudocode - // (SrcReg) DestReg = cmp.eq.unc(r0, r0) - BuildMI(MBB, MI, TII.get(IA64::PCMPEQUNC), DestReg) - .addReg(IA64::r0).addReg(IA64::r0).addReg(SrcReg); - else // otherwise, MOV works (for both gen. regs and FP regs) - BuildMI(MBB, MI, TII.get(IA64::MOV), DestReg).addReg(SrcReg); -} - void IA64RegisterInfo::reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=45470&r1=45469&r2=45470&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Mon Dec 31 00:32:00 2007 @@ -289,6 +289,23 @@ return 2; } +void MipsInstrInfo:: +copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const { + if (DestRC != SrcRC) { + cerr << "Not yet supported!"; + abort(); + } + + if (DestRC == Mips::CPURegsRegisterClass) + BuildMI(MBB, I, get(Mips::ADDu), DestReg).addReg(Mips::ZERO) + .addReg(SrcReg); + else + assert (0 && "Can't copy this register"); +} + unsigned MipsInstrInfo:: RemoveBranch(MachineBasicBlock &MBB) const { Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.h?rev=45470&r1=45469&r2=45470&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.h (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.h Mon Dec 31 00:32:00 2007 @@ -83,6 +83,10 @@ virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const std::vector &Cond) const; + virtual void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const; virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const; virtual bool ReverseBranchCondition(std::vector &Cond) const; Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp?rev=45470&r1=45469&r2=45470&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Mon Dec 31 00:32:00 2007 @@ -148,24 +148,6 @@ return; } -void MipsRegisterInfo:: -copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, - unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *DestRC, - const TargetRegisterClass *SrcRC) const -{ - if (DestRC != SrcRC) { - cerr << "Not yet supported!"; - abort(); - } - - if (DestRC == Mips::CPURegsRegisterClass) - BuildMI(MBB, I, TII.get(Mips::ADDu), DestReg).addReg(Mips::ZERO) - .addReg(SrcReg); - else - assert (0 && "Can't copy this register"); -} - void MipsRegisterInfo::reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=45470&r1=45469&r2=45470&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Mon Dec 31 00:32:00 2007 @@ -277,6 +277,34 @@ return 2; } +void PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const { + if (DestRC != SrcRC) { + cerr << "Not yet supported!"; + abort(); + } + + if (DestRC == PPC::GPRCRegisterClass) { + BuildMI(MBB, MI, get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg); + } else if (DestRC == PPC::G8RCRegisterClass) { + BuildMI(MBB, MI, get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg); + } else if (DestRC == PPC::F4RCRegisterClass) { + BuildMI(MBB, MI, get(PPC::FMRS), DestReg).addReg(SrcReg); + } else if (DestRC == PPC::F8RCRegisterClass) { + BuildMI(MBB, MI, get(PPC::FMRD), DestReg).addReg(SrcReg); + } else if (DestRC == PPC::CRRCRegisterClass) { + BuildMI(MBB, MI, get(PPC::MCRF), DestReg).addReg(SrcReg); + } else if (DestRC == PPC::VRRCRegisterClass) { + BuildMI(MBB, MI, get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg); + } else { + cerr << "Attempt to copy register that is not GPR or FPR"; + abort(); + } +} + bool PPCInstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const { if (MBB.empty()) return false; Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h?rev=45470&r1=45469&r2=45470&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h (original) +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h Mon Dec 31 00:32:00 2007 @@ -103,6 +103,11 @@ virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const std::vector &Cond) const; + void copyRegToReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const; virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const; virtual bool ReverseBranchCondition(std::vector &Cond) const; }; Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=45470&r1=45469&r2=45470&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Mon Dec 31 00:32:00 2007 @@ -332,34 +332,6 @@ return; } -void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *DestRC, - const TargetRegisterClass *SrcRC) const { - if (DestRC != SrcRC) { - cerr << "Not yet supported!"; - abort(); - } - - if (DestRC == PPC::GPRCRegisterClass) { - BuildMI(MBB, MI, TII.get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg); - } else if (DestRC == PPC::G8RCRegisterClass) { - BuildMI(MBB, MI, TII.get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg); - } else if (DestRC == PPC::F4RCRegisterClass) { - BuildMI(MBB, MI, TII.get(PPC::FMRS), DestReg).addReg(SrcReg); - } else if (DestRC == PPC::F8RCRegisterClass) { - BuildMI(MBB, MI, TII.get(PPC::FMRD), DestReg).addReg(SrcReg); - } else if (DestRC == PPC::CRRCRegisterClass) { - BuildMI(MBB, MI, TII.get(PPC::MCRF), DestReg).addReg(SrcReg); - } else if (DestRC == PPC::VRRCRegisterClass) { - BuildMI(MBB, MI, TII.get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg); - } else { - cerr << "Attempt to copy register that is not GPR or FPR"; - abort(); - } -} - void PPCRegisterInfo::reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp?rev=45470&r1=45469&r2=45470&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp Mon Dec 31 00:32:00 2007 @@ -12,6 +12,7 @@ //===----------------------------------------------------------------------===// #include "SparcInstrInfo.h" +#include "SparcSubtarget.h" #include "Sparc.h" #include "llvm/ADT/STLExtras.h" #include "llvm/CodeGen/MachineInstrBuilder.h" @@ -20,7 +21,7 @@ SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST) : TargetInstrInfo(SparcInsts, array_lengthof(SparcInsts)), - RI(ST, *this) { + RI(ST, *this), Subtarget(ST) { } static bool isZeroImm(const MachineOperand &op) { @@ -107,3 +108,24 @@ BuildMI(&MBB, get(SP::BA)).addMBB(TBB); return 1; } + +void SparcInstrInfo::copyRegToReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator I, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const { + if (DestRC != SrcRC) { + cerr << "Not yet supported!"; + abort(); + } + + if (DestRC == SP::IntRegsRegisterClass) + BuildMI(MBB, I, get(SP::ORrr), DestReg).addReg(SP::G0).addReg(SrcReg); + else if (DestRC == SP::FPRegsRegisterClass) + BuildMI(MBB, I, get(SP::FMOVS), DestReg).addReg(SrcReg); + else if (DestRC == SP::DFPRegsRegisterClass) + BuildMI(MBB, I, get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD),DestReg) + .addReg(SrcReg); + else + assert (0 && "Can't copy this register"); +} Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h?rev=45470&r1=45469&r2=45470&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h (original) +++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h Mon Dec 31 00:32:00 2007 @@ -33,6 +33,7 @@ class SparcInstrInfo : public TargetInstrInfo { const SparcRegisterInfo RI; + const SparcSubtarget& Subtarget; public: SparcInstrInfo(SparcSubtarget &ST); @@ -66,6 +67,12 @@ virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const std::vector &Cond) const; + + virtual void copyRegToReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator I, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const; }; } Modified: llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp?rev=45470&r1=45469&r2=45470&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp Mon Dec 31 00:32:00 2007 @@ -122,27 +122,6 @@ return; } -void SparcRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, - unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *DestRC, - const TargetRegisterClass *SrcRC) const { - if (DestRC != SrcRC) { - cerr << "Not yet supported!"; - abort(); - } - - if (DestRC == SP::IntRegsRegisterClass) - BuildMI(MBB, I, TII.get(SP::ORrr), DestReg).addReg(SP::G0).addReg(SrcReg); - else if (DestRC == SP::FPRegsRegisterClass) - BuildMI(MBB, I, TII.get(SP::FMOVS), DestReg).addReg(SrcReg); - else if (DestRC == SP::DFPRegsRegisterClass) - BuildMI(MBB, I, TII.get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD),DestReg) - .addReg(SrcReg); - else - assert (0 && "Can't copy this register"); -} - void SparcRegisterInfo::reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=45470&r1=45469&r2=45470&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Mon Dec 31 00:32:00 2007 @@ -784,6 +784,74 @@ return 2; } +void X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const { + if (DestRC != SrcRC) { + // Moving EFLAGS to / from another register requires a push and a pop. + if (SrcRC == &X86::CCRRegClass) { + assert(SrcReg == X86::EFLAGS); + if (DestRC == &X86::GR64RegClass) { + BuildMI(MBB, MI, get(X86::PUSHFQ)); + BuildMI(MBB, MI, get(X86::POP64r), DestReg); + return; + } else if (DestRC == &X86::GR32RegClass) { + BuildMI(MBB, MI, get(X86::PUSHFD)); + BuildMI(MBB, MI, get(X86::POP32r), DestReg); + return; + } + } else if (DestRC == &X86::CCRRegClass) { + assert(DestReg == X86::EFLAGS); + if (SrcRC == &X86::GR64RegClass) { + BuildMI(MBB, MI, get(X86::PUSH64r)).addReg(SrcReg); + BuildMI(MBB, MI, get(X86::POPFQ)); + return; + } else if (SrcRC == &X86::GR32RegClass) { + BuildMI(MBB, MI, get(X86::PUSH32r)).addReg(SrcReg); + BuildMI(MBB, MI, get(X86::POPFD)); + return; + } + } + cerr << "Not yet supported!"; + abort(); + } + + unsigned Opc; + if (DestRC == &X86::GR64RegClass) { + Opc = X86::MOV64rr; + } else if (DestRC == &X86::GR32RegClass) { + Opc = X86::MOV32rr; + } else if (DestRC == &X86::GR16RegClass) { + Opc = X86::MOV16rr; + } else if (DestRC == &X86::GR8RegClass) { + Opc = X86::MOV8rr; + } else if (DestRC == &X86::GR32_RegClass) { + Opc = X86::MOV32_rr; + } else if (DestRC == &X86::GR16_RegClass) { + Opc = X86::MOV16_rr; + } else if (DestRC == &X86::RFP32RegClass) { + Opc = X86::MOV_Fp3232; + } else if (DestRC == &X86::RFP64RegClass || DestRC == &X86::RSTRegClass) { + Opc = X86::MOV_Fp6464; + } else if (DestRC == &X86::RFP80RegClass) { + Opc = X86::MOV_Fp8080; + } else if (DestRC == &X86::FR32RegClass) { + Opc = X86::FsMOVAPSrr; + } else if (DestRC == &X86::FR64RegClass) { + Opc = X86::FsMOVAPDrr; + } else if (DestRC == &X86::VR128RegClass) { + Opc = X86::MOVAPSrr; + } else if (DestRC == &X86::VR64RegClass) { + Opc = X86::MMX_MOVQ64rr; + } else { + assert(0 && "Unknown regclass"); + abort(); + } + BuildMI(MBB, MI, get(Opc), DestReg).addReg(SrcReg); +} + bool X86InstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const { if (MBB.empty()) return false; Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=45470&r1=45469&r2=45470&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.h (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.h Mon Dec 31 00:32:00 2007 @@ -279,6 +279,11 @@ virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const std::vector &Cond) const; + virtual void copyRegToReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const; virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const; virtual bool ReverseBranchCondition(std::vector &Cond) const; Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=45470&r1=45469&r2=45470&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Mon Dec 31 00:32:00 2007 @@ -916,74 +916,6 @@ NewMIs.push_back(MIB); } -void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *DestRC, - const TargetRegisterClass *SrcRC) const { - if (DestRC != SrcRC) { - // Moving EFLAGS to / from another register requires a push and a pop. - if (SrcRC == &X86::CCRRegClass) { - assert(SrcReg == X86::EFLAGS); - if (DestRC == &X86::GR64RegClass) { - BuildMI(MBB, MI, TII.get(X86::PUSHFQ)); - BuildMI(MBB, MI, TII.get(X86::POP64r), DestReg); - return; - } else if (DestRC == &X86::GR32RegClass) { - BuildMI(MBB, MI, TII.get(X86::PUSHFD)); - BuildMI(MBB, MI, TII.get(X86::POP32r), DestReg); - return; - } - } else if (DestRC == &X86::CCRRegClass) { - assert(DestReg == X86::EFLAGS); - if (SrcRC == &X86::GR64RegClass) { - BuildMI(MBB, MI, TII.get(X86::PUSH64r)).addReg(SrcReg); - BuildMI(MBB, MI, TII.get(X86::POPFQ)); - return; - } else if (SrcRC == &X86::GR32RegClass) { - BuildMI(MBB, MI, TII.get(X86::PUSH32r)).addReg(SrcReg); - BuildMI(MBB, MI, TII.get(X86::POPFD)); - return; - } - } - cerr << "Not yet supported!"; - abort(); - } - - unsigned Opc; - if (DestRC == &X86::GR64RegClass) { - Opc = X86::MOV64rr; - } else if (DestRC == &X86::GR32RegClass) { - Opc = X86::MOV32rr; - } else if (DestRC == &X86::GR16RegClass) { - Opc = X86::MOV16rr; - } else if (DestRC == &X86::GR8RegClass) { - Opc = X86::MOV8rr; - } else if (DestRC == &X86::GR32_RegClass) { - Opc = X86::MOV32_rr; - } else if (DestRC == &X86::GR16_RegClass) { - Opc = X86::MOV16_rr; - } else if (DestRC == &X86::RFP32RegClass) { - Opc = X86::MOV_Fp3232; - } else if (DestRC == &X86::RFP64RegClass || DestRC == &X86::RSTRegClass) { - Opc = X86::MOV_Fp6464; - } else if (DestRC == &X86::RFP80RegClass) { - Opc = X86::MOV_Fp8080; - } else if (DestRC == &X86::FR32RegClass) { - Opc = X86::FsMOVAPSrr; - } else if (DestRC == &X86::FR64RegClass) { - Opc = X86::FsMOVAPDrr; - } else if (DestRC == &X86::VR128RegClass) { - Opc = X86::MOVAPSrr; - } else if (DestRC == &X86::VR64RegClass) { - Opc = X86::MMX_MOVQ64rr; - } else { - assert(0 && "Unknown regclass"); - abort(); - } - BuildMI(MBB, MI, TII.get(Opc), DestReg).addReg(SrcReg); -} - const TargetRegisterClass * X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const { if (RC == &X86::CCRRegClass) From isanbard at gmail.com Mon Dec 31 04:48:52 2007 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 31 Dec 2007 02:48:52 -0800 Subject: [llvm-commits] [llvm] r45470 - in /llvm/trunk: include/llvm/Target/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/CellSPU/ lib/Target/IA64/ lib/Target/Mips/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/X86/ In-Reply-To: <200712310632.lBV6W2to002259@zion.cs.uiuc.edu> References: <200712310632.lBV6W2to002259@zion.cs.uiuc.edu> Message-ID: <6ABC78F0-97C3-42F8-9996-7E5C5C64AD8B@gmail.com> Hi Owen, > ====================================================================== > ======== > --- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original) > +++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Mon Dec 31 > 00:32:00 2007 > @@ -458,6 +458,15 @@ > return 0; > } > > + /// copyRegToReg - Add a copy between a pair of registers > + virtual void copyRegToReg(MachineBasicBlock &MBB, > + MachineBasicBlock::iterator MI, > + unsigned DestReg, unsigned SrcReg, > + const TargetRegisterClass *DestRC, > + const TargetRegisterClass *SrcRC) const { > + assert(0 && "Target didn't implement > TargetInstrInfo::copyRegToReg!"); > + } > + > /// BlockHasNoFallThrough - Return true if the specified block > does not > /// fall-through into its successor block. This is primarily > used when a > /// branch is unanalyzable. It is useful for things like > unconditional > Is there any reason not to make this a pure virtual function? Just wondering. :-) -bw From baldrick at free.fr Mon Dec 31 08:05:53 2007 From: baldrick at free.fr (Duncan Sands) Date: Mon, 31 Dec 2007 14:05:53 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r45471 - in /llvm-gcc-4.2/trunk/gcc: llvm-convert.cpp llvm-internal.h Message-ID: <200712311405.lBVE5rd3003993@zion.cs.uiuc.edu> Author: baldrick Date: Mon Dec 31 08:05:52 2007 New Revision: 45471 URL: http://llvm.org/viewvc/llvm-project?rev=45471&view=rev Log: Due to gcc inlining, it is possible for resx expressions (i.e. rethrows) to occur inside must-not-throw regions. This is illegal, and can be handled by either executing the code specified by lang_protect_cleanup_actions (since this code should already have been emitted into some basic block, this means locating that basic block and jumping to it), or by marking the call with the nounwind attribute. Because using the nounwind attribute seems to be both simpler and more robust, that is the solution implemented here. This fixes the last known eh problem on x86 linux with llvm-gcc-4.2. Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp llvm-gcc-4.2/trunk/gcc/llvm-internal.h Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=45471&r1=45470&r2=45471&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Mon Dec 31 08:05:52 2007 @@ -349,7 +349,7 @@ TreeToLLVM::TreeToLLVM(tree fndecl) : TD(getTargetData()) { FnDecl = fndecl; Fn = 0; - ReturnBB = UnwindBB = 0; + ReturnBB = UnwindBB = NoUnwindBB = 0; if (TheDebugInfo) { expanded_location Location = expand_location(DECL_SOURCE_LOCATION (fndecl)); @@ -755,6 +755,7 @@ EmitLandingPads(); EmitPostPads(); EmitUnwindBlock(); + EmitNoUnwindBlock(); // If this function takes the address of a label, emit the indirect goto // block. @@ -1863,7 +1864,7 @@ PointerType::getUnqual(Type::Int8Ty))); // Add selections for each handler. - foreach_reachable_handler (i, false, AddHandler, &Handlers); + foreach_reachable_handler(i, false, AddHandler, &Handlers); for (std::vector::iterator I = Handlers.begin(), E = Handlers.end(); I != E; ++I) { @@ -2023,7 +2024,7 @@ } // Emit a RESX_EXPR which skips handlers with no post landing pad. - foreach_reachable_handler (i, true, AddHandler, &Handlers); + foreach_reachable_handler(i, true, AddHandler, &Handlers); BasicBlock *TargetBB = NULL; @@ -2038,13 +2039,20 @@ break; } - if (!TargetBB) { + if (TargetBB) { + Builder.CreateBr(TargetBB); + } else if (can_throw_external_1(i, true)) { + // Unwinding continues in the caller. if (!UnwindBB) UnwindBB = new BasicBlock("Unwind"); - TargetBB = UnwindBB; + Builder.CreateBr(UnwindBB); + } else { + // Unwinding in a must_not_throw region - notify the runtime. + if (!NoUnwindBB) + NoUnwindBB = new BasicBlock("NoUnwind"); + Builder.CreateBr(NoUnwindBB); } - Builder.CreateBr(TargetBB); Handlers.clear(); } } @@ -2062,6 +2070,22 @@ } } +/// EmitNoUnwindBlock - Emit the lazily created EH illegal-unwind block. +void TreeToLLVM::EmitNoUnwindBlock() { + if (NoUnwindBB) { + CreateExceptionValues(); + EmitBlock(NoUnwindBB); + // Fetch and store exception handler. + Value *Arg = Builder.CreateLoad(ExceptionValue, "eh_ptr"); + assert(llvm_unwind_resume_libfunc && "no unwind resume function!"); + CallInst *Call = + Builder.CreateCall(DECL_LLVM(llvm_unwind_resume_libfunc), Arg); + // Illegal unwind - notify the runtime. + Call->setDoesNotThrow(); + Builder.CreateUnreachable(); + } +} + //===----------------------------------------------------------------------===// // ... Expressions ... //===----------------------------------------------------------------------===// @@ -3267,7 +3291,7 @@ unsigned RegionNo = TREE_INT_CST_LOW(TREE_OPERAND (exp, 0)); std::vector Handlers; - foreach_reachable_handler (RegionNo, true, AddHandler, &Handlers); + foreach_reachable_handler(RegionNo, true, AddHandler, &Handlers); if (!Handlers.empty()) { for (std::vector::iterator I = Handlers.begin(), @@ -3276,10 +3300,16 @@ getPostPad(get_eh_region_number(*I)); Builder.CreateBr(getPostPad(get_eh_region_number(*Handlers.begin()))); - } else { + } else if (can_throw_external_1(RegionNo, true)) { + // Unwinding continues in the caller. if (!UnwindBB) UnwindBB = new BasicBlock("Unwind"); Builder.CreateBr(UnwindBB); + } else { + // Unwinding in a must_not_throw region - notify the runtime. + if (!NoUnwindBB) + NoUnwindBB = new BasicBlock("NoUnwind"); + Builder.CreateBr(NoUnwindBB); } EmitBlock(new BasicBlock("")); Modified: llvm-gcc-4.2/trunk/gcc/llvm-internal.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-internal.h?rev=45471&r1=45470&r2=45471&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-internal.h (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-internal.h Mon Dec 31 08:05:52 2007 @@ -267,7 +267,8 @@ Function *Fn; BasicBlock *ReturnBB; BasicBlock *UnwindBB; - + BasicBlock *NoUnwindBB; + // State that changes as the function is emitted. /// Builder - Instruction creator, the location to insert into is always the @@ -421,6 +422,9 @@ /// EmitUnwindBlock - Emit the lazily created EH unwind block. void EmitUnwindBlock(); + /// EmitNoUnwindBlock - Emit the lazily created EH illegal-unwind block. + void EmitNoUnwindBlock(); + private: // Helpers for exception handling. /// CreateExceptionValues - Create values used internally by exception From duncan.sands at math.u-psud.fr Mon Dec 31 08:37:05 2007 From: duncan.sands at math.u-psud.fr (Duncan Sands) Date: Mon, 31 Dec 2007 15:37:05 +0100 Subject: [llvm-commits] [llvm-gcc-4.2] r45471 - in /llvm-gcc-4.2/trunk/gcc: llvm-convert.cpp llvm-internal.h In-Reply-To: <200712311405.lBVE5rd3003993@zion.cs.uiuc.edu> References: <200712311405.lBVE5rd3003993@zion.cs.uiuc.edu> Message-ID: <200712311537.06147.duncan.sands@math.u-psud.fr> > ... This fixes the last known eh > problem on x86 linux with llvm-gcc-4.2. I forgot to mention that the testcase is g++.dg/eh/filter2.C from the gcc testsuite. Ciao, Duncan. From resistor at mac.com Mon Dec 31 10:20:48 2007 From: resistor at mac.com (Owen Anderson) Date: Mon, 31 Dec 2007 11:20:48 -0500 Subject: [llvm-commits] [llvm] r45470 - in /llvm/trunk: include/llvm/Target/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/CellSPU/ lib/Target/IA64/ lib/Target/Mips/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/X86/ In-Reply-To: <6ABC78F0-97C3-42F8-9996-7E5C5C64AD8B@gmail.com> References: <200712310632.lBV6W2to002259@zion.cs.uiuc.edu> <6ABC78F0-97C3-42F8-9996-7E5C5C64AD8B@gmail.com> Message-ID: <8AD12BF2-1389-40B6-87C7-271C0232E071@mac.com> On Dec 31, 2007, at 5:48 AM, Bill Wendling wrote: > Is there any reason not to make this a pure virtual function? > > Just wondering. :-) Just matching the style of TargetInstrInfo functions, like InsertBranch. --Owen From baldrick at free.fr Mon Dec 31 12:35:51 2007 From: baldrick at free.fr (Duncan Sands) Date: Mon, 31 Dec 2007 18:35:51 -0000 Subject: [llvm-commits] [llvm] r45472 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp test/CodeGen/Generic/2007-12-31-UnusedSelector.ll Message-ID: <200712311835.lBVIZpt2016469@zion.cs.uiuc.edu> Author: baldrick Date: Mon Dec 31 12:35:50 2007 New Revision: 45472 URL: http://llvm.org/viewvc/llvm-project?rev=45472&view=rev Log: Fix PR1833 - eh.exception and eh.selector return two values, which means doing extra legalization work. It would be easier to get this kind of thing right if there was some documentation... Added: llvm/trunk/test/CodeGen/Generic/2007-12-31-UnusedSelector.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=45472&r1=45471&r2=45472&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Dec 31 12:35:50 2007 @@ -858,7 +858,7 @@ default: assert(0 && "This action is not supported yet!"); case TargetLowering::Expand: { unsigned Reg = TLI.getExceptionAddressRegister(); - Result = DAG.getCopyFromReg(Tmp1, Reg, VT).getValue(Op.ResNo); + Result = DAG.getCopyFromReg(Tmp1, Reg, VT); } break; case TargetLowering::Custom: @@ -868,12 +868,23 @@ case TargetLowering::Legal: { SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 }; Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), - Ops, 2).getValue(Op.ResNo); + Ops, 2); break; } } } - break; + if (Result.Val->getNumValues() == 1) break; + + assert(Result.Val->getNumValues() == 2 && + "Cannot return more than two values!"); + + // Since we produced two values, make sure to remember that we + // legalized both of them. + Tmp1 = LegalizeOp(Result); + Tmp2 = LegalizeOp(Result.getValue(1)); + AddLegalizedOperand(Op.getValue(0), Tmp1); + AddLegalizedOperand(Op.getValue(1), Tmp2); + return Op.ResNo ? Tmp2 : Tmp1; case ISD::EHSELECTION: { Tmp1 = LegalizeOp(Node->getOperand(0)); Tmp2 = LegalizeOp(Node->getOperand(1)); @@ -882,7 +893,7 @@ default: assert(0 && "This action is not supported yet!"); case TargetLowering::Expand: { unsigned Reg = TLI.getExceptionSelectorRegister(); - Result = DAG.getCopyFromReg(Tmp2, Reg, VT).getValue(Op.ResNo); + Result = DAG.getCopyFromReg(Tmp2, Reg, VT); } break; case TargetLowering::Custom: @@ -892,12 +903,23 @@ case TargetLowering::Legal: { SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 }; Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), - Ops, 2).getValue(Op.ResNo); + Ops, 2); break; } } } - break; + if (Result.Val->getNumValues() == 1) break; + + assert(Result.Val->getNumValues() == 2 && + "Cannot return more than two values!"); + + // Since we produced two values, make sure to remember that we + // legalized both of them. + Tmp1 = LegalizeOp(Result); + Tmp2 = LegalizeOp(Result.getValue(1)); + AddLegalizedOperand(Op.getValue(0), Tmp1); + AddLegalizedOperand(Op.getValue(1), Tmp2); + return Op.ResNo ? Tmp2 : Tmp1; case ISD::EH_RETURN: { MVT::ValueType VT = Node->getValueType(0); // The only "good" option for this node is to custom lower it. Added: llvm/trunk/test/CodeGen/Generic/2007-12-31-UnusedSelector.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2007-12-31-UnusedSelector.ll?rev=45472&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Generic/2007-12-31-UnusedSelector.ll (added) +++ llvm/trunk/test/CodeGen/Generic/2007-12-31-UnusedSelector.ll Mon Dec 31 12:35:50 2007 @@ -0,0 +1,36 @@ +; RUN: llvm-as < %s | llc -enable-eh +; PR1833 + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32" +target triple = "i686-pc-linux-gnu" + %struct.__class_type_info_pseudo = type { %struct.__type_info_pseudo } + %struct.__type_info_pseudo = type { i8*, i8* } + at _ZTI2e1 = external constant %struct.__class_type_info_pseudo ; <%struct.__class_type_info_pseudo*> [#uses=1] + +define void @_Z7ex_testv() { +entry: + invoke void @__cxa_throw( i8* null, i8* bitcast (%struct.__class_type_info_pseudo* @_ZTI2e1 to i8*), void (i8*)* null ) noreturn + to label %UnifiedUnreachableBlock unwind label %lpad + +bb14: ; preds = %lpad + unreachable + +lpad: ; preds = %entry + invoke void @__cxa_end_catch( ) + to label %bb14 unwind label %lpad17 + +lpad17: ; preds = %lpad + %eh_select20 = tail call i32 (i8*, i8*, ...)* @llvm.eh.selector.i32( i8* null, i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*), i8* null ) ; [#uses=0] + unreachable + +UnifiedUnreachableBlock: ; preds = %entry + unreachable +} + +declare void @__cxa_throw(i8*, i8*, void (i8*)*) noreturn + +declare i32 @llvm.eh.selector.i32(i8*, i8*, ...) + +declare void @__cxa_end_catch() + +declare i32 @__gxx_personality_v0(...) From clattner at apple.com Mon Dec 31 13:09:55 2007 From: clattner at apple.com (Chris Lattner) Date: Mon, 31 Dec 2007 11:09:55 -0800 Subject: [llvm-commits] [llvm] r45470 - in /llvm/trunk: include/llvm/Target/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/CellSPU/ lib/Target/IA64/ lib/Target/Mips/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/X86/ In-Reply-To: <200712310632.lBV6W2to002259@zion.cs.uiuc.edu> References: <200712310632.lBV6W2to002259@zion.cs.uiuc.edu> Message-ID: <5246DB33-9312-444B-96EF-8094D945EEFE@apple.com> On Dec 30, 2007, at 10:32 PM, Owen Anderson wrote: > URL: http://llvm.org/viewvc/llvm-project?rev=45470&view=rev > Log: > Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is > part of the > Machine-level API cleanup instigated by Chris. Very nice Owen, thanks! One minor additional request: how about renaming it to "InsertCopy" instead of "copyRegToReg"? -Chris From resistor at mac.com Mon Dec 31 13:24:36 2007 From: resistor at mac.com (Owen Anderson) Date: Mon, 31 Dec 2007 14:24:36 -0500 Subject: [llvm-commits] [llvm] r45470 - in /llvm/trunk: include/llvm/Target/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/CellSPU/ lib/Target/IA64/ lib/Target/Mips/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/X86/ In-Reply-To: <5246DB33-9312-444B-96EF-8094D945EEFE@apple.com> References: <200712310632.lBV6W2to002259@zion.cs.uiuc.edu> <5246DB33-9312-444B-96EF-8094D945EEFE@apple.com> Message-ID: <80922000-8039-4DB7-8486-BDD458E84E0F@mac.com> On Dec 31, 2007, at 2:09 PM, Chris Lattner wrote: > On Dec 30, 2007, at 10:32 PM, Owen Anderson wrote: >> URL: http://llvm.org/viewvc/llvm-project?rev=45470&view=rev >> Log: >> Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is >> part of the >> Machine-level API cleanup instigated by Chris. > > Very nice Owen, thanks! One minor additional request: how about > renaming it to "InsertCopy" instead of "copyRegToReg"? There's a whole suite of instruction-creation APIs that need to be migrated over. My plan is to migrate them all over, and then refactor them into a self-consistent API. --Owen From clattner at apple.com Mon Dec 31 13:48:49 2007 From: clattner at apple.com (Chris Lattner) Date: Mon, 31 Dec 2007 11:48:49 -0800 Subject: [llvm-commits] [llvm] r45470 - in /llvm/trunk: include/llvm/Target/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/CellSPU/ lib/Target/IA64/ lib/Target/Mips/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/X86/ In-Reply-To: <80922000-8039-4DB7-8486-BDD458E84E0F@mac.com> References: <200712310632.lBV6W2to002259@zion.cs.uiuc.edu> <5246DB33-9312-444B-96EF-8094D945EEFE@apple.com> <80922000-8039-4DB7-8486-BDD458E84E0F@mac.com> Message-ID: <19176B3B-5AB7-4EA7-B1F2-065FEFF91F68@apple.com> On Dec 31, 2007, at 11:24 AM, Owen Anderson wrote: > On Dec 31, 2007, at 2:09 PM, Chris Lattner wrote: > >> On Dec 30, 2007, at 10:32 PM, Owen Anderson wrote: >>> URL: http://llvm.org/viewvc/llvm-project?rev=45470&view=rev >>> Log: >>> Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is >>> part of the >>> Machine-level API cleanup instigated by Chris. >> >> Very nice Owen, thanks! One minor additional request: how about >> renaming it to "InsertCopy" instead of "copyRegToReg"? > > There's a whole suite of instruction-creation APIs that need to be > migrated over. My plan is to migrate them all over, and then refactor > them into a self-consistent API. Ok, good deal! Thanks again for working on this, -Chris From sabre at nondot.org Mon Dec 31 17:58:31 2007 From: sabre at nondot.org (Chris Lattner) Date: Mon, 31 Dec 2007 23:58:31 -0000 Subject: [llvm-commits] [llvm] r45473 - /llvm/trunk/Makefile.rules Message-ID: <200712312358.lBVNwVn8004509@zion.cs.uiuc.edu> Author: lattner Date: Mon Dec 31 17:58:31 2007 New Revision: 45473 URL: http://llvm.org/viewvc/llvm-project?rev=45473&view=rev Log: Factor out makefile dependency generation better. Don't include system headers in the .d files. Don't use $@ in the makefile rules, as there are two possible targets it could resolve to: use the one that we need explicitly. Modified: llvm/trunk/Makefile.rules Modified: llvm/trunk/Makefile.rules URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=45473&r1=45472&r2=45473&view=diff ============================================================================== --- llvm/trunk/Makefile.rules (original) +++ llvm/trunk/Makefile.rules Mon Dec 31 17:58:31 2007 @@ -1079,23 +1079,28 @@ # Create .lo files in the ObjDir directory from the .cpp and .c files... #--------------------------------------------------------- +DEPEND_OPTIONS = -MMD -MP -MF "$(ObjDir)/$*.d.tmp" \ + -MT "$(ObjDir)/$*.lo" -MT "$(ObjDir)/$*.o" -MT "$(ObjDir)/$*.d" + +# If the build succeeded, move the dependency file over. If it failed, put an +# empty file there. +DEPEND_MOVEFILE = then $(MV) -f "$(ObjDir)/$*.d.tmp" "$(ObjDir)/$*.d"; \ + else $(RM) "$(ObjDir)/$*.d.tmp"; exit 1; fi + $(ObjDir)/%.lo $(ObjDir)/%.o: %.cpp $(ObjDir)/.dir $(BUILT_SOURCES) $(Echo) "Compiling $*.cpp for $(BuildMode) build " $(PIC_FLAG) - $(Verb) if $(MAYBE_PIC_Compile.CXX) -MD -MT $@ -MP -MF $(ObjDir)/$*.LACXXd $< -o $@ ;\ - then $(MV) -f "$(ObjDir)/$*.LACXXd" "$(ObjDir)/$*.d"; \ - else $(RM) -f "$(ObjDir)/$*.LACXXd"; exit 1; fi + $(Verb) if $(MAYBE_PIC_Compile.CXX) $(DEPEND_OPTIONS) $< -o $(ObjDir)/$*.o ; \ + $(DEPEND_MOVEFILE) $(ObjDir)/%.lo $(ObjDir)/%.o: %.cc $(ObjDir)/.dir $(BUILT_SOURCES) $(Echo) "Compiling $*.cc for $(BuildMode) build" $(PIC_FLAG) - $(Verb) if $(MAYBE_PIC_Compile.CXX) -MD -MT $@ -MP -MF $(ObjDir)/$*.LACXXd $< -o $@ ;\ - then $(MV) -f "$(ObjDir)/$*.LACXXd" "$(ObjDir)/$*.d"; \ - else $(RM) -f "$(ObjDir)/$*.LACXXd"; exit 1; fi + $(Verb) if $(MAYBE_PIC_Compile.CXX) $(DEPEND_OPTIONS) $< -o $(ObjDir)/$*.o ; \ + $(DEPEND_MOVEFILE) $(ObjDir)/%.lo $(ObjDir)/%.o: %.c $(ObjDir)/.dir $(BUILT_SOURCES) $(Echo) "Compiling $*.c for $(BuildMode) build" $(PIC_FLAG) - $(Verb) if $(MAYBE_PIC_Compile.C) -MD -MT $@ -MP -MF $(ObjDir)/$*.LACd $< -o $@ ; \ - then $(MV) -f "$(ObjDir)/$*.LACd" "$(ObjDir)/$*.d"; \ - else $(RM) -f "$(ObjDir)/$*.LACd"; exit 1; fi + $(Verb) if $(MAYBE_PIC_Compile.C) $(DEPEND_OPTIONS) $< -o $(ObjDir)/$*.o ; \ + $(DEPEND_MOVEFILE) #--------------------------------------------------------- # Create .bc files in the ObjDir directory from .cpp .cc and .c files... From isanbard at gmail.com Mon Dec 31 18:22:09 2007 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 01 Jan 2008 00:22:09 -0000 Subject: [llvm-commits] [test-suite] r45474 - /test-suite/trunk/Makefile.programs Message-ID: <200801010022.m010M9d7005814@zion.cs.uiuc.edu> Author: void Date: Mon Dec 31 18:22:07 2007 New Revision: 45474 URL: http://llvm.org/viewvc/llvm-project?rev=45474&view=rev Log: Turn on Machine LICM for a beta test. Modified: test-suite/trunk/Makefile.programs Modified: test-suite/trunk/Makefile.programs URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/Makefile.programs?rev=45474&r1=45473&r2=45474&view=diff ============================================================================== --- test-suite/trunk/Makefile.programs (original) +++ test-suite/trunk/Makefile.programs Mon Dec 31 18:22:07 2007 @@ -222,7 +222,8 @@ LLCBETAOPTION := -sched=simple endif ifeq ($(ARCH),x86) -LLCBETAOPTION := -new-coalescer-heuristic=true +LLCBETAOPTION := -machine-licm +#-new-coalescer-heuristic=true #-tailcallopt #-regalloc=local -fast #-disable-rematerialization From sabre at nondot.org Mon Dec 31 19:03:06 2007 From: sabre at nondot.org (Chris Lattner) Date: Tue, 01 Jan 2008 01:03:06 -0000 Subject: [llvm-commits] [llvm] r45475 - in /llvm/trunk: include/llvm/Target/ lib/CodeGen/ lib/Target/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/CellSPU/ lib/Target/IA64/ lib/Target/Mips/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/X86/ Message-ID: <200801010103.m0113756008675@zion.cs.uiuc.edu> Author: lattner Date: Mon Dec 31 19:03:04 2007 New Revision: 45475 URL: http://llvm.org/viewvc/llvm-project?rev=45475&view=rev Log: Fix a problem where lib/Target/TargetInstrInfo.h would include and use a header file from libcodegen. This violates a layering order: codegen depends on target, not the other way around. The fix to this is to split TII into two classes, TII and TargetInstrInfoImpl, which defines stuff that depends on libcodegen. It is defined in libcodegen, where the base is not. Added: llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp llvm/trunk/lib/Target/ARM/ARMInstrInfo.h llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h llvm/trunk/lib/Target/IA64/IA64InstrInfo.cpp llvm/trunk/lib/Target/IA64/IA64InstrInfo.h llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp llvm/trunk/lib/Target/Mips/MipsInstrInfo.h llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h llvm/trunk/lib/Target/TargetInstrInfo.cpp llvm/trunk/lib/Target/X86/X86InstrInfo.cpp llvm/trunk/lib/Target/X86/X86InstrInfo.h Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=45475&r1=45474&r2=45475&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Mon Dec 31 19:03:04 2007 @@ -406,7 +406,7 @@ /// return a new machine instruction. If an instruction cannot commute, it /// can also return null. /// - virtual MachineInstr *commuteInstruction(MachineInstr *MI) const; + virtual MachineInstr *commuteInstruction(MachineInstr *MI) const = 0; /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning /// true if it cannot be understood (e.g. it's a switch dispatch or isn't @@ -504,7 +504,7 @@ /// instruction. It returns true if the operation was successful. virtual bool PredicateInstruction(MachineInstr *MI, - const std::vector &Pred) const; + const std::vector &Pred) const = 0; /// SubsumesPredicate - Returns true if the first specified predicate /// subsumes the second, e.g. GE subsumes GT. @@ -531,6 +531,21 @@ } }; +/// TargetInstrInfoImpl - This is the default implementation of +/// TargetInstrInfo, which just provides a couple of default implementations +/// for various methods. This separated out because it is implemented in +/// libcodegen, not in libtarget. +class TargetInstrInfoImpl : public TargetInstrInfo { +protected: + TargetInstrInfoImpl(const TargetInstrDescriptor *desc, unsigned NumOpcodes) + : TargetInstrInfo(desc, NumOpcodes) {} +public: + virtual MachineInstr *commuteInstruction(MachineInstr *MI) const; + virtual bool PredicateInstruction(MachineInstr *MI, + const std::vector &Pred) const; + +}; + } // End llvm namespace #endif Added: llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp?rev=45475&view=auto ============================================================================== --- llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp (added) +++ llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp Mon Dec 31 19:03:04 2007 @@ -0,0 +1,58 @@ +//===-- TargetInstrInfoImpl.cpp - Target Instruction Information ----------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file implements the TargetInstrInfoImpl class, it just provides default +// implementations of various methods. +// +//===----------------------------------------------------------------------===// + +#include "llvm/Target/TargetInstrInfo.h" +#include "llvm/CodeGen/MachineInstr.h" +using namespace llvm; + +// commuteInstruction - The default implementation of this method just exchanges +// operand 1 and 2. +MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI) const { + assert(MI->getOperand(1).isRegister() && MI->getOperand(2).isRegister() && + "This only knows how to commute register operands so far"); + unsigned Reg1 = MI->getOperand(1).getReg(); + unsigned Reg2 = MI->getOperand(2).getReg(); + bool Reg1IsKill = MI->getOperand(1).isKill(); + bool Reg2IsKill = MI->getOperand(2).isKill(); + MI->getOperand(2).setReg(Reg1); + MI->getOperand(1).setReg(Reg2); + MI->getOperand(2).setIsKill(Reg1IsKill); + MI->getOperand(1).setIsKill(Reg2IsKill); + return MI; +} + +bool TargetInstrInfoImpl::PredicateInstruction(MachineInstr *MI, + const std::vector &Pred) const { + bool MadeChange = false; + const TargetInstrDescriptor *TID = MI->getInstrDescriptor(); + if (TID->Flags & M_PREDICABLE) { + for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) { + if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) { + MachineOperand &MO = MI->getOperand(i); + if (MO.isReg()) { + MO.setReg(Pred[j].getReg()); + MadeChange = true; + } else if (MO.isImm()) { + MO.setImm(Pred[j].getImm()); + MadeChange = true; + } else if (MO.isMBB()) { + MO.setMBB(Pred[j].getMBB()); + MadeChange = true; + } + ++j; + } + } + } + return MadeChange; +} Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp?rev=45475&r1=45474&r2=45475&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp Mon Dec 31 19:03:04 2007 @@ -38,7 +38,7 @@ } ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI) - : TargetInstrInfo(ARMInsts, array_lengthof(ARMInsts)), + : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)), RI(*this, STI) { } Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.h?rev=45475&r1=45474&r2=45475&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.h Mon Dec 31 19:03:04 2007 @@ -125,7 +125,7 @@ }; } -class ARMInstrInfo : public TargetInstrInfo { +class ARMInstrInfo : public TargetInstrInfoImpl { const ARMRegisterInfo RI; public: ARMInstrInfo(const ARMSubtarget &STI); Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp?rev=45475&r1=45474&r2=45475&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp Mon Dec 31 19:03:04 2007 @@ -19,7 +19,7 @@ using namespace llvm; AlphaInstrInfo::AlphaInstrInfo() - : TargetInstrInfo(AlphaInsts, array_lengthof(AlphaInsts)), + : TargetInstrInfoImpl(AlphaInsts, array_lengthof(AlphaInsts)), RI(*this) { } Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h?rev=45475&r1=45474&r2=45475&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h (original) +++ llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h Mon Dec 31 19:03:04 2007 @@ -19,7 +19,7 @@ namespace llvm { -class AlphaInstrInfo : public TargetInstrInfo { +class AlphaInstrInfo : public TargetInstrInfoImpl { const AlphaRegisterInfo RI; public: AlphaInstrInfo(); Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp?rev=45475&r1=45474&r2=45475&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp Mon Dec 31 19:03:04 2007 @@ -21,7 +21,7 @@ using namespace llvm; SPUInstrInfo::SPUInstrInfo(SPUTargetMachine &tm) - : TargetInstrInfo(SPUInsts, sizeof(SPUInsts)/sizeof(SPUInsts[0])), + : TargetInstrInfoImpl(SPUInsts, sizeof(SPUInsts)/sizeof(SPUInsts[0])), TM(tm), RI(*TM.getSubtargetImpl(), *this) { Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h?rev=45475&r1=45474&r2=45475&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h (original) +++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h Mon Dec 31 19:03:04 2007 @@ -20,8 +20,7 @@ namespace llvm { //! Cell SPU instruction information class - class SPUInstrInfo : public TargetInstrInfo - { + class SPUInstrInfo : public TargetInstrInfoImpl { SPUTargetMachine &TM; const SPURegisterInfo RI; public: Modified: llvm/trunk/lib/Target/IA64/IA64InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64InstrInfo.cpp?rev=45475&r1=45474&r2=45475&view=diff ============================================================================== --- llvm/trunk/lib/Target/IA64/IA64InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/IA64/IA64InstrInfo.cpp Mon Dec 31 19:03:04 2007 @@ -19,7 +19,7 @@ using namespace llvm; IA64InstrInfo::IA64InstrInfo() - : TargetInstrInfo(IA64Insts, sizeof(IA64Insts)/sizeof(IA64Insts[0])), + : TargetInstrInfoImpl(IA64Insts, sizeof(IA64Insts)/sizeof(IA64Insts[0])), RI(*this) { } Modified: llvm/trunk/lib/Target/IA64/IA64InstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64InstrInfo.h?rev=45475&r1=45474&r2=45475&view=diff ============================================================================== --- llvm/trunk/lib/Target/IA64/IA64InstrInfo.h (original) +++ llvm/trunk/lib/Target/IA64/IA64InstrInfo.h Mon Dec 31 19:03:04 2007 @@ -19,7 +19,7 @@ namespace llvm { -class IA64InstrInfo : public TargetInstrInfo { +class IA64InstrInfo : public TargetInstrInfoImpl { const IA64RegisterInfo RI; public: IA64InstrInfo(); Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=45475&r1=45474&r2=45475&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Mon Dec 31 19:03:04 2007 @@ -21,7 +21,7 @@ // TODO: Add the subtarget support on this constructor MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm) - : TargetInstrInfo(MipsInsts, array_lengthof(MipsInsts)), + : TargetInstrInfoImpl(MipsInsts, array_lengthof(MipsInsts)), TM(tm), RI(*this) {} static bool isZeroImm(const MachineOperand &op) { Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.h?rev=45475&r1=45474&r2=45475&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.h (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.h Mon Dec 31 19:03:04 2007 @@ -42,8 +42,7 @@ } -class MipsInstrInfo : public TargetInstrInfo -{ +class MipsInstrInfo : public TargetInstrInfoImpl { MipsTargetMachine &TM; const MipsRegisterInfo RI; public: Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=45475&r1=45474&r2=45475&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Mon Dec 31 19:03:04 2007 @@ -20,7 +20,7 @@ using namespace llvm; PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm) - : TargetInstrInfo(PPCInsts, array_lengthof(PPCInsts)), TM(tm), + : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm), RI(*TM.getSubtargetImpl(), *this) {} /// getPointerRegClass - Return the register class to use to hold pointers. Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h?rev=45475&r1=45474&r2=45475&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h (original) +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h Mon Dec 31 19:03:04 2007 @@ -61,7 +61,7 @@ } -class PPCInstrInfo : public TargetInstrInfo { +class PPCInstrInfo : public TargetInstrInfoImpl { PPCTargetMachine &TM; const PPCRegisterInfo RI; public: Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp?rev=45475&r1=45474&r2=45475&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp Mon Dec 31 19:03:04 2007 @@ -20,7 +20,7 @@ using namespace llvm; SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST) - : TargetInstrInfo(SparcInsts, array_lengthof(SparcInsts)), + : TargetInstrInfoImpl(SparcInsts, array_lengthof(SparcInsts)), RI(ST, *this), Subtarget(ST) { } Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h?rev=45475&r1=45474&r2=45475&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h (original) +++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h Mon Dec 31 19:03:04 2007 @@ -31,7 +31,7 @@ }; } -class SparcInstrInfo : public TargetInstrInfo { +class SparcInstrInfo : public TargetInstrInfoImpl { const SparcRegisterInfo RI; const SparcSubtarget& Subtarget; public: Modified: llvm/trunk/lib/Target/TargetInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetInstrInfo.cpp?rev=45475&r1=45474&r2=45475&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/TargetInstrInfo.cpp Mon Dec 31 19:03:04 2007 @@ -12,7 +12,6 @@ //===----------------------------------------------------------------------===// #include "llvm/Target/TargetInstrInfo.h" -#include "llvm/CodeGen/MachineInstr.h" #include "llvm/Constant.h" #include "llvm/DerivedTypes.h" using namespace llvm; @@ -38,47 +37,6 @@ TargetInstrInfo::~TargetInstrInfo() { } -// commuteInstruction - The default implementation of this method just exchanges -// operand 1 and 2. -MachineInstr *TargetInstrInfo::commuteInstruction(MachineInstr *MI) const { - assert(MI->getOperand(1).isRegister() && MI->getOperand(2).isRegister() && - "This only knows how to commute register operands so far"); - unsigned Reg1 = MI->getOperand(1).getReg(); - unsigned Reg2 = MI->getOperand(2).getReg(); - bool Reg1IsKill = MI->getOperand(1).isKill(); - bool Reg2IsKill = MI->getOperand(2).isKill(); - MI->getOperand(2).setReg(Reg1); - MI->getOperand(1).setReg(Reg2); - MI->getOperand(2).setIsKill(Reg1IsKill); - MI->getOperand(1).setIsKill(Reg2IsKill); - return MI; -} - -bool TargetInstrInfo::PredicateInstruction(MachineInstr *MI, - const std::vector &Pred) const { - bool MadeChange = false; - const TargetInstrDescriptor *TID = MI->getInstrDescriptor(); - if (TID->Flags & M_PREDICABLE) { - for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) { - if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) { - MachineOperand &MO = MI->getOperand(i); - if (MO.isReg()) { - MO.setReg(Pred[j].getReg()); - MadeChange = true; - } else if (MO.isImm()) { - MO.setImm(Pred[j].getImm()); - MadeChange = true; - } else if (MO.isMBB()) { - MO.setMBB(Pred[j].getMBB()); - MadeChange = true; - } - ++j; - } - } - } - return MadeChange; -} - bool TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const { const TargetInstrDescriptor *TID = MI->getInstrDescriptor(); if (TID->Flags & M_TERMINATOR_FLAG) { Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=45475&r1=45474&r2=45475&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Mon Dec 31 19:03:04 2007 @@ -25,7 +25,7 @@ using namespace llvm; X86InstrInfo::X86InstrInfo(X86TargetMachine &tm) - : TargetInstrInfo(X86Insts, array_lengthof(X86Insts)), + : TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts)), TM(tm), RI(tm, *this) { } Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=45475&r1=45474&r2=45475&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.h (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.h Mon Dec 31 19:03:04 2007 @@ -222,7 +222,7 @@ }; } -class X86InstrInfo : public TargetInstrInfo { +class X86InstrInfo : public TargetInstrInfoImpl { X86TargetMachine &TM; const X86RegisterInfo RI; mutable IndexedMap MachineInstrMap; From sabre at nondot.org Mon Dec 31 19:05:34 2007 From: sabre at nondot.org (Chris Lattner) Date: Tue, 01 Jan 2008 01:05:34 -0000 Subject: [llvm-commits] [llvm] r45476 - in /llvm/trunk/lib/Target: PowerPC/PPCInstrInfo.cpp X86/X86InstrInfo.cpp Message-ID: <200801010105.m0115Zcv008764@zion.cs.uiuc.edu> Author: lattner Date: Mon Dec 31 19:05:34 2007 New Revision: 45476 URL: http://llvm.org/viewvc/llvm-project?rev=45476&view=rev Log: Fix a bug in my previous patch: refer to the impl not the pure virtual version. It's unclear why gcc would ever compile this... Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=45476&r1=45475&r2=45476&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Mon Dec 31 19:05:34 2007 @@ -132,7 +132,7 @@ MachineInstr *PPCInstrInfo::commuteInstruction(MachineInstr *MI) const { // Normal instructions can be commuted the obvious way. if (MI->getOpcode() != PPC::RLWIMI) - return TargetInstrInfo::commuteInstruction(MI); + return TargetInstrInfoImpl::commuteInstruction(MI); // Cannot commute if it has a non-zero rotate count. if (MI->getOperand(3).getImm() != 0) Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=45476&r1=45475&r2=45476&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Mon Dec 31 19:05:34 2007 @@ -575,7 +575,7 @@ // Fallthrough intended. } default: - return TargetInstrInfo::commuteInstruction(MI); + return TargetInstrInfoImpl::commuteInstruction(MI); } } From sabre at nondot.org Mon Dec 31 19:12:32 2007 From: sabre at nondot.org (Chris Lattner) Date: Tue, 01 Jan 2008 01:12:32 -0000 Subject: [llvm-commits] [llvm] r45477 - in /llvm/trunk: include/llvm/CodeGen/MachineInstr.h include/llvm/CodeGen/MachineOperand.h include/llvm/CodeGen/MachineRegisterInfo.h lib/CodeGen/MachineBasicBlock.cpp lib/CodeGen/MachineInstr.cpp lib/CodeGen/MachineRegisterInfo.cpp Message-ID: <200801010112.m011CWwU009173@zion.cs.uiuc.edu> Author: lattner Date: Mon Dec 31 19:12:31 2007 New Revision: 45477 URL: http://llvm.org/viewvc/llvm-project?rev=45477&view=rev Log: Implement automatically updated def/use lists for all MachineInstr register operands. The lists are currently kept in MachineRegisterInfo, but it does not yet provide an iterator interface to them. Modified: llvm/trunk/include/llvm/CodeGen/MachineInstr.h llvm/trunk/include/llvm/CodeGen/MachineOperand.h llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp llvm/trunk/lib/CodeGen/MachineInstr.cpp llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp Modified: llvm/trunk/include/llvm/CodeGen/MachineInstr.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstr.h?rev=45477&r1=45476&r2=45477&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineInstr.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineInstr.h Mon Dec 31 19:12:31 2007 @@ -45,6 +45,7 @@ // Intrusive list support friend struct ilist_traits; + friend struct ilist_traits; void setParent(MachineBasicBlock *P) { Parent = P; } public: /// MachineInstr ctor - This constructor creates a dummy MachineInstr with @@ -154,27 +155,14 @@ void dump() const; //===--------------------------------------------------------------------===// - // Accessors to add operands when building up machine instructions. - // - void addOperand(const MachineOperand &Op) { - bool isImpReg = Op.isRegister() && Op.isImplicit(); - assert((isImpReg || !OperandsComplete()) && - "Trying to add an operand to a machine instr that is already done!"); - if (isImpReg || NumImplicitOps == 0) {// This is true most of the time. - Operands.push_back(Op); - Operands.back().ParentMI = this; - } else { - // Insert a real operand before any implicit ones. - unsigned OpNo = Operands.size()-NumImplicitOps; - Operands.insert(Operands.begin()+OpNo, Op); - Operands[OpNo].ParentMI = this; - } - } - - //===--------------------------------------------------------------------===// - // Accessors used to modify instructions in place. - // + // Accessors used to build up machine instructions. + /// addOperand - Add the specified operand to the instruction. If it is an + /// implicit operand, it is added to the end of the operand list. If it is + /// an explicit operand it is added at the end of the explicit operand list + /// (before the first implicit operand). + void addOperand(const MachineOperand &Op); + /// setInstrDescriptor - Replace the instruction descriptor (thus opcode) of /// the current instruction with a new one. /// @@ -183,14 +171,27 @@ /// RemoveOperand - Erase an operand from an instruction, leaving it with one /// fewer operand than it started with. /// - void RemoveOperand(unsigned i) { - Operands.erase(Operands.begin()+i); - } + void RemoveOperand(unsigned i); + private: + /// getRegInfo - If this instruction is embedded into a MachineFunction, + /// return the MachineRegisterInfo object for the current function, otherwise + /// return null. + MachineRegisterInfo *getRegInfo(); /// addImplicitDefUseOperands - Add all implicit def and use operands to /// this instruction. void addImplicitDefUseOperands(); + + /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in + /// this instruction from their respective use lists. This requires that the + /// operands already be on their use lists. + void RemoveRegOperandsFromUseLists(); + + /// AddRegOperandsToUseLists - Add all of the register operands in + /// this instruction from their respective use lists. This requires that the + /// operands not be on their use lists yet. + void AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo); }; //===----------------------------------------------------------------------===// Modified: llvm/trunk/include/llvm/CodeGen/MachineOperand.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineOperand.h?rev=45477&r1=45476&r2=45477&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineOperand.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineOperand.h Mon Dec 31 19:12:31 2007 @@ -25,6 +25,7 @@ class GlobalValue; class MachineInstr; class TargetMachine; +class MachineRegisterInfo; /// MachineOperand class - Representation of each machine instruction operand. /// @@ -76,8 +77,13 @@ /// Contents union - This contains the payload for the various operand types. union { MachineBasicBlock *MBB; // For MO_MachineBasicBlock. - unsigned RegNo; // For MO_Register. int64_t ImmVal; // For MO_Immediate. + + struct { // For MO_Register. + unsigned RegNo; + MachineOperand **Prev; // Access list for register. + MachineOperand *Next; + } Reg; /// OffsetedInfo - This struct contains the offset and an object identifier. /// this represent the object as with an optional offset from it. @@ -92,7 +98,6 @@ } Contents; MachineOperand(MachineOperandType K) : OpKind(K), ParentMI(0) {} - public: MachineOperand(const MachineOperand &M) { *this = M; @@ -138,7 +143,7 @@ /// getReg - Returns the register number. unsigned getReg() const { assert(isRegister() && "This is not a register operand!"); - return Contents.RegNo; + return Contents.Reg.RegNo; } unsigned getSubReg() const { @@ -175,11 +180,10 @@ // Mutators for Register Operands //===--------------------------------------------------------------------===// - void setReg(unsigned Reg) { - assert(isRegister() && "This is not a register operand!"); - Contents.RegNo = Reg; - } - + /// Change the register this operand corresponds to. + /// + void setReg(unsigned Reg); + void setSubReg(unsigned subReg) { assert(isRegister() && "Wrong MachineOperand accessor"); SubReg = (unsigned char)subReg; @@ -284,24 +288,13 @@ /// ChangeToImmediate - Replace this operand with a new immediate operand of /// the specified value. If an operand is known to be an immediate already, /// the setImm method should be used. - void ChangeToImmediate(int64_t ImmVal) { - OpKind = MO_Immediate; - Contents.ImmVal = ImmVal; - } - + void ChangeToImmediate(int64_t ImmVal); + /// ChangeToRegister - Replace this operand with a new register operand of /// the specified value. If an operand is known to be an register already, /// the setReg method should be used. void ChangeToRegister(unsigned Reg, bool isDef, bool isImp = false, - bool isKill = false, bool isDead = false) { - OpKind = MO_Register; - Contents.RegNo = Reg; - IsDef = isDef; - IsImp = isImp; - IsKill = isKill; - IsDead = isDead; - SubReg = 0; - } + bool isKill = false, bool isDead = false); //===--------------------------------------------------------------------===// // Construction methods. @@ -321,7 +314,9 @@ Op.IsImp = isImp; Op.IsKill = isKill; Op.IsDead = isDead; - Op.Contents.RegNo = Reg; + Op.Contents.Reg.RegNo = Reg; + Op.Contents.Reg.Prev = 0; + Op.Contents.Reg.Next = 0; Op.SubReg = SubReg; return Op; } @@ -371,6 +366,37 @@ } friend class MachineInstr; + friend class MachineRegisterInfo; +private: + //===--------------------------------------------------------------------===// + // Methods for handling register use/def lists. + //===--------------------------------------------------------------------===// + + /// isOnRegUseList - Return true if this operand is on a register use/def list + /// or false if not. This can only be called for register operands that are + /// part of a machine instruction. + bool isOnRegUseList() const { + assert(isReg() && "Can only add reg operand to use lists"); + return Contents.Reg.Prev != 0; + } + + /// AddRegOperandToRegInfo - Add this register operand to the specified + /// MachineRegisterInfo. If it is null, then the next/prev fields should be + /// explicitly nulled out. + void AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo); + + void RemoveRegOperandFromRegInfo() { + assert(isOnRegUseList() && "Can only add reg operand to use lists"); + // Unlink this from the doubly linked list of operands. + MachineOperand *NextOp = Contents.Reg.Next; + *Contents.Reg.Prev = NextOp; + if (NextOp) { + assert(NextOp->getReg() == getReg() && "Corrupt reg use/def chain!"); + NextOp->Contents.Reg.Prev = Contents.Reg.Prev; + } + Contents.Reg.Prev = 0; + Contents.Reg.Next = 0; + } }; inline std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO) { Modified: llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h?rev=45477&r1=45476&r2=45477&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h Mon Dec 31 19:12:31 2007 @@ -26,7 +26,14 @@ /// VRegInfo - Information we keep for each virtual register. The entries in /// this vector are actually converted to vreg numbers by adding the /// MRegisterInfo::FirstVirtualRegister delta to their index. - std::vector VRegInfo; + /// + /// Each element in this list contains the register class of the vreg and the + /// start of the use/def list for the register. + std::vector > VRegInfo; + + /// PhysRegUseDefLists - This is an array of the head of the use/def list for + /// physical registers. + MachineOperand **PhysRegUseDefLists; /// UsedPhysRegs - This is a bit vector that is computed and set by the /// register allocator, and must be kept up to date by passes that run after @@ -42,8 +49,21 @@ /// stored in the second element. std::vector > LiveIns; std::vector LiveOuts; + + MachineRegisterInfo(const MachineRegisterInfo&); // DO NOT IMPLEMENT + void operator=(const MachineRegisterInfo&); // DO NOT IMPLEMENT public: MachineRegisterInfo(const MRegisterInfo &MRI); + ~MachineRegisterInfo(); + + /// getRegUseDefListHead - Return the head pointer for the register use/def + /// list for the specified virtual or physical register. + MachineOperand *&getRegUseDefListHead(unsigned RegNo) { + if (RegNo < MRegisterInfo::FirstVirtualRegister) + return PhysRegUseDefLists[RegNo]; + RegNo -= MRegisterInfo::FirstVirtualRegister; + return VRegInfo[RegNo].second; + } //===--------------------------------------------------------------------===// @@ -54,15 +74,23 @@ const TargetRegisterClass *getRegClass(unsigned Reg) { Reg -= MRegisterInfo::FirstVirtualRegister; assert(Reg < VRegInfo.size() && "Invalid vreg!"); - return VRegInfo[Reg]; + return VRegInfo[Reg].first; } - + /// createVirtualRegister - Create and return a new virtual register in the /// function with the specified register class. /// unsigned createVirtualRegister(const TargetRegisterClass *RegClass) { assert(RegClass && "Cannot create register without RegClass!"); - VRegInfo.push_back(RegClass); + // Add a reg, but keep track of whether the vector reallocated or not. + void *ArrayBase = &VRegInfo[0]; + VRegInfo.push_back(std::make_pair(RegClass, (MachineOperand*)0)); + + if (&VRegInfo[0] == ArrayBase) + return getLastVirtReg(); + + // Otherwise, the vector reallocated, handle this now. + HandleVRegListReallocation(); return getLastVirtReg(); } @@ -111,6 +139,8 @@ liveout_iterator liveout_begin() const { return LiveOuts.begin(); } liveout_iterator liveout_end() const { return LiveOuts.end(); } bool liveout_empty() const { return LiveOuts.empty(); } +private: + void HandleVRegListReallocation(); }; } // End llvm namespace Modified: llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp?rev=45477&r1=45476&r2=45477&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp Mon Dec 31 19:12:31 2007 @@ -31,13 +31,23 @@ return OS; } -// MBBs start out as #-1. When a MBB is added to a MachineFunction, it -// gets the next available unique MBB number. If it is removed from a -// MachineFunction, it goes back to being #-1. +/// addNodeToList (MBB) - When an MBB is added to an MF, we need to update the +/// parent pointer of the MBB, the MBB numbering, and any instructions in the +/// MBB to be on the right operand list for registers. +/// +/// MBBs start out as #-1. When a MBB is added to a MachineFunction, it +/// gets the next available unique MBB number. If it is removed from a +/// MachineFunction, it goes back to being #-1. void ilist_traits::addNodeToList(MachineBasicBlock* N) { assert(N->getParent() == 0 && "machine instruction already in a basic block"); N->setParent(Parent); N->Number = Parent->addToMBBNumbering(N); + + // Make sure the instructions have their operands in the reginfo lists. + MachineRegisterInfo &RegInfo = Parent->getRegInfo(); + for (MachineBasicBlock::iterator I = N->begin(), E = N->end(); I != E; ++I) + I->AddRegOperandsToUseLists(RegInfo); + LeakDetector::removeGarbageObject(N); } @@ -46,6 +56,12 @@ N->getParent()->removeFromMBBNumbering(N->Number); N->Number = -1; N->setParent(0); + + // Make sure the instructions have their operands removed from the reginfo + // lists. + for (MachineBasicBlock::iterator I = N->begin(), E = N->end(); I != E; ++I) + I->RemoveRegOperandsFromUseLists(); + LeakDetector::addGarbageObject(N); } @@ -56,27 +72,62 @@ return dummy; } +/// addNodeToList (MI) - When we add an instruction to a basic block +/// list, we update its parent pointer and add its operands from reg use/def +/// lists if appropriate. void ilist_traits::addNodeToList(MachineInstr* N) { assert(N->getParent() == 0 && "machine instruction already in a basic block"); N->setParent(parent); LeakDetector::removeGarbageObject(N); + + // If the block is in a function, add the instruction's register operands to + // their corresponding use/def lists. + if (MachineFunction *MF = parent->getParent()) + N->AddRegOperandsToUseLists(MF->getRegInfo()); } +/// removeNodeFromList (MI) - When we remove an instruction from a basic block +/// list, we update its parent pointer and remove its operands from reg use/def +/// lists if appropriate. void ilist_traits::removeNodeFromList(MachineInstr* N) { assert(N->getParent() != 0 && "machine instruction not in a basic block"); + // If this block is in a function, remove from the use/def lists. + if (parent->getParent() != 0) + N->RemoveRegOperandsFromUseLists(); + N->setParent(0); LeakDetector::addGarbageObject(N); } +/// transferNodesFromList (MI) - When moving a range of instructions from one +/// MBB list to another, we need to update the parent pointers and the use/def +/// lists. void ilist_traits::transferNodesFromList( iplist >& fromList, ilist_iterator first, ilist_iterator last) { // Splice within the same MBB -> no change. if (parent == fromList.parent) return; + + // If splicing between two blocks within the same function, just update the + // parent pointers. + if (parent->getParent() == fromList.parent->getParent()) { + for (; first != last; ++first) + first->setParent(parent); + return; + } - for (; first != last; ++first) + // Otherwise, we have to update the parent and the use/def lists. The common + // case when this occurs is if we're splicing from a block in a MF to a block + // that is not in an MF. + bool HasOldMF = fromList.parent->getParent() != 0; + MachineFunction *NewMF = parent->getParent(); + + for (; first != last; ++first) { + if (HasOldMF) first->RemoveRegOperandsFromUseLists(); first->setParent(parent); + if (NewMF) first->AddRegOperandsToUseLists(NewMF->getRegInfo()); + } } MachineBasicBlock::iterator MachineBasicBlock::getFirstTerminator() { Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=45477&r1=45476&r2=45477&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Mon Dec 31 19:12:31 2007 @@ -14,6 +14,7 @@ #include "llvm/CodeGen/MachineInstr.h" #include "llvm/Value.h" #include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/MRegisterInfo.h" @@ -26,6 +27,96 @@ // MachineOperand Implementation //===----------------------------------------------------------------------===// +/// AddRegOperandToRegInfo - Add this register operand to the specified +/// MachineRegisterInfo. If it is null, then the next/prev fields should be +/// explicitly nulled out. +void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) { + assert(isReg() && "Can only add reg operand to use lists"); + + // If the reginfo pointer is null, just explicitly null out or next/prev + // pointers, to ensure they are not garbage. + if (RegInfo == 0) { + Contents.Reg.Prev = 0; + Contents.Reg.Next = 0; + return; + } + + // Otherwise, add this operand to the head of the registers use/def list. + MachineOperand *&Head = RegInfo->getRegUseDefListHead(getReg()); + + Contents.Reg.Next = Head; + if (Contents.Reg.Next) { + assert(getReg() == Contents.Reg.Next->getReg() && + "Different regs on the same list!"); + Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next; + } + + Contents.Reg.Prev = &Head; + Head = this; +} + +void MachineOperand::setReg(unsigned Reg) { + if (getReg() == Reg) return; // No change. + + // Otherwise, we have to change the register. If this operand is embedded + // into a machine function, we need to update the old and new register's + // use/def lists. + if (MachineInstr *MI = getParent()) + if (MachineBasicBlock *MBB = MI->getParent()) + if (MachineFunction *MF = MBB->getParent()) { + RemoveRegOperandFromRegInfo(); + Contents.Reg.RegNo = Reg; + AddRegOperandToRegInfo(&MF->getRegInfo()); + return; + } + + // Otherwise, just change the register, no problem. :) + Contents.Reg.RegNo = Reg; +} + +/// ChangeToImmediate - Replace this operand with a new immediate operand of +/// the specified value. If an operand is known to be an immediate already, +/// the setImm method should be used. +void MachineOperand::ChangeToImmediate(int64_t ImmVal) { + // If this operand is currently a register operand, and if this is in a + // function, deregister the operand from the register's use/def list. + if (isReg() && getParent() && getParent()->getParent() && + getParent()->getParent()->getParent()) + RemoveRegOperandFromRegInfo(); + + OpKind = MO_Immediate; + Contents.ImmVal = ImmVal; +} + +/// ChangeToRegister - Replace this operand with a new register operand of +/// the specified value. If an operand is known to be an register already, +/// the setReg method should be used. +void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp, + bool isKill, bool isDead) { + // If this operand is already a register operand, use setReg to update the + // register's use/def lists. + if (isReg()) { + setReg(Reg); + } else { + // Otherwise, change this to a register and set the reg#. + OpKind = MO_Register; + Contents.Reg.RegNo = Reg; + + // If this operand is embedded in a function, add the operand to the + // register's use/def list. + if (MachineInstr *MI = getParent()) + if (MachineBasicBlock *MBB = MI->getParent()) + if (MachineFunction *MF = MBB->getParent()) + AddRegOperandToRegInfo(&MF->getRegInfo()); + } + + IsDef = isDef; + IsImp = isImp; + IsKill = isKill; + IsDead = isDead; + SubReg = 0; +} + /// isIdenticalTo - Return true if this operand is identical to the specified /// operand. bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const { @@ -63,8 +154,7 @@ OS << "%reg" << getReg(); } else { // If the instruction is embedded into a basic block, we can find the - // target - // info for the instruction. + // target info for the instruction. if (TM == 0) if (const MachineInstr *MI = getParent()) if (const MachineBasicBlock *MBB = MI->getParent()) @@ -212,8 +302,11 @@ MachineInstr::~MachineInstr() { LeakDetector::removeGarbageObject(this); #ifndef NDEBUG - for (unsigned i = 0, e = Operands.size(); i != e; ++i) + for (unsigned i = 0, e = Operands.size(); i != e; ++i) { assert(Operands[i].ParentMI == this && "ParentMI mismatch!"); + assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) && + "Reg operand def/use list corrupted"); + } #endif } @@ -223,6 +316,159 @@ return TID->Opcode; } +/// getRegInfo - If this instruction is embedded into a MachineFunction, +/// return the MachineRegisterInfo object for the current function, otherwise +/// return null. +MachineRegisterInfo *MachineInstr::getRegInfo() { + if (MachineBasicBlock *MBB = getParent()) + if (MachineFunction *MF = MBB->getParent()) + return &MF->getRegInfo(); + return 0; +} + +/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in +/// this instruction from their respective use lists. This requires that the +/// operands already be on their use lists. +void MachineInstr::RemoveRegOperandsFromUseLists() { + for (unsigned i = 0, e = Operands.size(); i != e; ++i) { + if (Operands[i].isReg()) + Operands[i].RemoveRegOperandFromRegInfo(); + } +} + +/// AddRegOperandsToUseLists - Add all of the register operands in +/// this instruction from their respective use lists. This requires that the +/// operands not be on their use lists yet. +void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) { + for (unsigned i = 0, e = Operands.size(); i != e; ++i) { + if (Operands[i].isReg()) + Operands[i].AddRegOperandToRegInfo(&RegInfo); + } +} + + +/// addOperand - Add the specified operand to the instruction. If it is an +/// implicit operand, it is added to the end of the operand list. If it is +/// an explicit operand it is added at the end of the explicit operand list +/// (before the first implicit operand). +void MachineInstr::addOperand(const MachineOperand &Op) { + bool isImpReg = Op.isReg() && Op.isImplicit(); + assert((isImpReg || !OperandsComplete()) && + "Trying to add an operand to a machine instr that is already done!"); + + // If we are adding the operand to the end of the list, our job is simpler. + // This is true most of the time, so this is a reasonable optimization. + if (isImpReg || NumImplicitOps == 0) { + // We can only do this optimization if we know that the operand list won't + // reallocate. + if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) { + Operands.push_back(Op); + + // Set the parent of the operand. + Operands.back().ParentMI = this; + + // If the operand is a register, update the operand's use list. + if (Op.isReg()) + Operands.back().AddRegOperandToRegInfo(getRegInfo()); + return; + } + } + + // Otherwise, we have to insert a real operand before any implicit ones. + unsigned OpNo = Operands.size()-NumImplicitOps; + + MachineRegisterInfo *RegInfo = getRegInfo(); + + // If this instruction isn't embedded into a function, then we don't need to + // update any operand lists. + if (RegInfo == 0) { + // Simple insertion, no reginfo update needed for other register operands. + Operands.insert(Operands.begin()+OpNo, Op); + Operands[OpNo].ParentMI = this; + + // Do explicitly set the reginfo for this operand though, to ensure the + // next/prev fields are properly nulled out. + if (Operands[OpNo].isReg()) + Operands[OpNo].AddRegOperandToRegInfo(0); + + } else if (Operands.size()+1 <= Operands.capacity()) { + // Otherwise, we have to remove register operands from their register use + // list, add the operand, then add the register operands back to their use + // list. This also must handle the case when the operand list reallocates + // to somewhere else. + + // If insertion of this operand won't cause reallocation of the operand + // list, just remove the implicit operands, add the operand, then re-add all + // the rest of the operands. + for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { + assert(Operands[i].isReg() && "Should only be an implicit reg!"); + Operands[i].RemoveRegOperandFromRegInfo(); + } + + // Add the operand. If it is a register, add it to the reg list. + Operands.insert(Operands.begin()+OpNo, Op); + Operands[OpNo].ParentMI = this; + + if (Operands[OpNo].isReg()) + Operands[OpNo].AddRegOperandToRegInfo(RegInfo); + + // Re-add all the implicit ops. + for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) { + assert(Operands[i].isReg() && "Should only be an implicit reg!"); + Operands[i].AddRegOperandToRegInfo(RegInfo); + } + } else { + // Otherwise, we will be reallocating the operand list. Remove all reg + // operands from their list, then readd them after the operand list is + // reallocated. + RemoveRegOperandsFromUseLists(); + + Operands.insert(Operands.begin()+OpNo, Op); + Operands[OpNo].ParentMI = this; + + // Re-add all the operands. + AddRegOperandsToUseLists(*RegInfo); + } +} + +/// RemoveOperand - Erase an operand from an instruction, leaving it with one +/// fewer operand than it started with. +/// +void MachineInstr::RemoveOperand(unsigned OpNo) { + assert(OpNo < Operands.size() && "Invalid operand number"); + + // Special case removing the last one. + if (OpNo == Operands.size()-1) { + // If needed, remove from the reg def/use list. + if (Operands.back().isReg() && Operands.back().isOnRegUseList()) + Operands.back().RemoveRegOperandFromRegInfo(); + + Operands.pop_back(); + return; + } + + // Otherwise, we are removing an interior operand. If we have reginfo to + // update, remove all operands that will be shifted down from their reg lists, + // move everything down, then re-add them. + MachineRegisterInfo *RegInfo = getRegInfo(); + if (RegInfo) { + for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { + if (Operands[i].isReg()) + Operands[i].RemoveRegOperandFromRegInfo(); + } + } + + Operands.erase(Operands.begin()+OpNo); + + if (RegInfo) { + for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { + if (Operands[i].isReg()) + Operands[i].AddRegOperandToRegInfo(RegInfo); + } + } +} + + /// removeFromParent - This method unlinks 'this' from the containing basic /// block, and returns it, but does not delete it. MachineInstr *MachineInstr::removeFromParent() { Modified: llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp?rev=45477&r1=45476&r2=45477&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp Mon Dec 31 19:12:31 2007 @@ -1,4 +1,4 @@ -//===-- MachineRegisterInfo.cpp -------------------------------------------===// +//===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===// // // The LLVM Compiler Infrastructure // @@ -17,4 +17,30 @@ MachineRegisterInfo::MachineRegisterInfo(const MRegisterInfo &MRI) { VRegInfo.reserve(256); UsedPhysRegs.resize(MRI.getNumRegs()); + + // Create the physreg use/def lists. + PhysRegUseDefLists = new MachineOperand*[MRI.getNumRegs()]; + memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*MRI.getNumRegs()); +} + +MachineRegisterInfo::~MachineRegisterInfo() { +#ifndef NDEBUG + for (unsigned i = 0, e = VRegInfo.size(); i != e; ++i) + assert(VRegInfo[i].second == 0 && "Vreg use list non-empty still?"); +#endif + delete [] PhysRegUseDefLists; +} + +/// HandleVRegListReallocation - We just added a virtual register to the +/// VRegInfo info list and it reallocated. Update the use/def lists info +/// pointers. +void MachineRegisterInfo::HandleVRegListReallocation() { + // The back pointers for the vreg lists point into the previous vector. + // Update them to point to their correct slots. + for (unsigned i = 0, e = VRegInfo.size(); i != e; ++i) { + MachineOperand *List = VRegInfo[i].second; + if (!List) continue; + // Update the back-pointer to be accurate once more. + List->Contents.Reg.Prev = &VRegInfo[i].second; + } } From isanbard at gmail.com Mon Dec 31 19:34:37 2007 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 01 Jan 2008 01:34:37 -0000 Subject: [llvm-commits] [llvm] r45478 - /llvm/trunk/test/Transforms/LICM/scalar_promote.ll Message-ID: <200801010134.m011YbLC010131@zion.cs.uiuc.edu> Author: void Date: Mon Dec 31 19:34:36 2007 New Revision: 45478 URL: http://llvm.org/viewvc/llvm-project?rev=45478&view=rev Log: Update this testcase. The output needs to be disabled to pass. Modified: llvm/trunk/test/Transforms/LICM/scalar_promote.ll Modified: llvm/trunk/test/Transforms/LICM/scalar_promote.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LICM/scalar_promote.ll?rev=45478&r1=45477&r2=45478&view=diff ============================================================================== --- llvm/trunk/test/Transforms/LICM/scalar_promote.ll (original) +++ llvm/trunk/test/Transforms/LICM/scalar_promote.ll Mon Dec 31 19:34:36 2007 @@ -1,37 +1,35 @@ -; RUN: llvm-upgrade < %s | llvm-as | opt -licm -stats |& \ +; RUN: llvm-as < %s | opt -licm -disable-output -stats |& \ ; RUN: grep {memory locations promoted to register} + at X = global i32 7 ; [#uses=4] -%X = global int 7 - -void %testfunc(int %i) { +define void @testfunc(i32 %i) { +;