From natebegeman at mac.com Mon Feb 4 00:00:24 2008 From: natebegeman at mac.com (Nate Begeman) Date: Mon, 04 Feb 2008 06:00:24 -0000 Subject: [llvm-commits] [llvm] r46697 - /llvm/trunk/lib/Target/X86/X86InstrSSE.td Message-ID: <200802040600.m1460OOG024698@zion.cs.uiuc.edu> Author: sampo Date: Mon Feb 4 00:00:24 2008 New Revision: 46697 URL: http://llvm.org/viewvc/llvm-project?rev=46697&view=rev Log: The rest of the SSE4.1 intrinsic patterns that are obvious to me. Getting Evan's help with the rest. Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=46697&r1=46696&r2=46697&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Mon Feb 4 00:00:24 2008 @@ -3066,7 +3066,7 @@ Intrinsic V2F64Int> { // Intrinsic operation, reg. def SSr_Int : SS4AI, @@ -3074,7 +3074,7 @@ // Intrinsic operation, mem. def SSm_Int : SS4AI, @@ -3082,7 +3082,7 @@ // Vector intrinsic operation, reg def PSr_Int : SS4AI, @@ -3090,7 +3090,7 @@ // Vector intrinsic operation, mem def PSm_Int : SS4AI, @@ -3098,7 +3098,7 @@ // Intrinsic operation, reg. def SDr_Int : SS4AI, @@ -3106,7 +3106,7 @@ // Intrinsic operation, mem. def SDm_Int : SS4AI, @@ -3114,7 +3114,7 @@ // Vector intrinsic operation, reg def PDr_Int : SS4AI, @@ -3122,7 +3122,7 @@ // Vector intrinsic operation, mem def PDm_Int : SS4AI, @@ -3196,3 +3196,40 @@ int_x86_sse41_pmulld, 1>; defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq, 1>; + +/// SS41I_binop_rmi_int - SSE 4.1 binary operator with immediate +let isTwoAddress = 1 in { + multiclass SS41I_binop_rmi_int opc, string OpcodeStr, + Intrinsic IntId128, bit Commutable = 0> { + def rri128 : SS4AI, + OpSize { + let isCommutable = Commutable; + } + def rmi128 : SS4AI, + OpSize; + } +} + +defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", + int_x86_sse41_blendps, 0>; +defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", + int_x86_sse41_blendpd, 0>; +defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", + int_x86_sse41_pblendw, 0>; +defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", + int_x86_sse41_dpps, 1>; +defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", + int_x86_sse41_dppd, 1>; +defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", + int_x86_sse41_mpsadbw, 0>; From tonic at nondot.org Mon Feb 4 00:17:47 2008 From: tonic at nondot.org (Tanya Lattner) Date: Mon, 04 Feb 2008 06:17:47 -0000 Subject: [llvm-commits] [llvm] r46698 - in /llvm/branches/release_22/lib/Target/X86: X86RegisterInfo.cpp X86RegisterInfo.h X86RegisterInfo.td Message-ID: <200802040617.m146HlbR025216@zion.cs.uiuc.edu> Author: tbrethou Date: Mon Feb 4 00:17:46 2008 New Revision: 46698 URL: http://llvm.org/viewvc/llvm-project?rev=46698&view=rev Log: Merge from mainline. Provide correct DWARF register numbering for debug information emission on x86-32/Darwin. This should fix bunch of issues. Modified: llvm/branches/release_22/lib/Target/X86/X86RegisterInfo.cpp llvm/branches/release_22/lib/Target/X86/X86RegisterInfo.h llvm/branches/release_22/lib/Target/X86/X86RegisterInfo.td Modified: llvm/branches/release_22/lib/Target/X86/X86RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_22/lib/Target/X86/X86RegisterInfo.cpp?rev=46698&r1=46697&r2=46698&view=diff ============================================================================== --- llvm/branches/release_22/lib/Target/X86/X86RegisterInfo.cpp (original) +++ llvm/branches/release_22/lib/Target/X86/X86RegisterInfo.cpp Mon Feb 4 00:17:46 2008 @@ -64,12 +64,15 @@ unsigned Flavour = DWARFFlavour::X86_64; if (!Subtarget->is64Bit()) { if (Subtarget->isTargetDarwin()) { - Flavour = DWARFFlavour::X86_32_Darwin; + if (isEH) + Flavour = DWARFFlavour::X86_32_DarwinEH; + else + Flavour = DWARFFlavour::X86_32_Generic; } else if (Subtarget->isTargetCygMing()) { // Unsupported by now, just quick fallback - Flavour = DWARFFlavour::X86_32_ELF; + Flavour = DWARFFlavour::X86_32_Generic; } else { - Flavour = DWARFFlavour::X86_32_ELF; + Flavour = DWARFFlavour::X86_32_Generic; } } Modified: llvm/branches/release_22/lib/Target/X86/X86RegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_22/lib/Target/X86/X86RegisterInfo.h?rev=46698&r1=46697&r2=46698&view=diff ============================================================================== --- llvm/branches/release_22/lib/Target/X86/X86RegisterInfo.h (original) +++ llvm/branches/release_22/lib/Target/X86/X86RegisterInfo.h Mon Feb 4 00:17:46 2008 @@ -36,7 +36,7 @@ /// namespace DWARFFlavour { enum { - X86_64 = 0, X86_32_Darwin = 1, X86_32_ELF = 2 + X86_64 = 0, X86_32_DarwinEH = 1, X86_32_Generic = 2 }; } Modified: llvm/branches/release_22/lib/Target/X86/X86RegisterInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_22/lib/Target/X86/X86RegisterInfo.td?rev=46698&r1=46697&r2=46698&view=diff ============================================================================== --- llvm/branches/release_22/lib/Target/X86/X86RegisterInfo.td (original) +++ llvm/branches/release_22/lib/Target/X86/X86RegisterInfo.td Mon Feb 4 00:17:46 2008 @@ -25,11 +25,8 @@ // Dwarf numbering is different for 32-bit and 64-bit, and there are // variations by target as well. Currently the first entry is for X86-64, - // second - for X86-32/Darwin and third for X86-32/Linux - - // FIXME: Comments in gcc indicate that Darwin uses different numbering - // for debug info and exception handling info:( The numbering here is - // for exception handling. + // second - for EH on X86-32/Darwin and third is 'generic' one (X86-32/Linux + // and debug information on X86-32/Darwin) // 8-bit registers // Low registers From tonic at nondot.org Mon Feb 4 00:29:05 2008 From: tonic at nondot.org (Tanya Lattner) Date: Mon, 04 Feb 2008 06:29:05 -0000 Subject: [llvm-commits] [llvm] r46699 - /llvm/branches/release_22/lib/CodeGen/ShadowStackCollector.cpp Message-ID: <200802040629.m146T5ib025512@zion.cs.uiuc.edu> Author: tbrethou Date: Mon Feb 4 00:29:04 2008 New Revision: 46699 URL: http://llvm.org/viewvc/llvm-project?rev=46699&view=rev Log: Merge from mainline. Don't dump the function! Modified: llvm/branches/release_22/lib/CodeGen/ShadowStackCollector.cpp Modified: llvm/branches/release_22/lib/CodeGen/ShadowStackCollector.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_22/lib/CodeGen/ShadowStackCollector.cpp?rev=46699&r1=46698&r2=46699&view=diff ============================================================================== --- llvm/branches/release_22/lib/CodeGen/ShadowStackCollector.cpp (original) +++ llvm/branches/release_22/lib/CodeGen/ShadowStackCollector.cpp Mon Feb 4 00:29:04 2008 @@ -426,8 +426,6 @@ Roots[I].second->eraseFromParent(); } - F.dump(); - Roots.clear(); return true; } From tonic at nondot.org Mon Feb 4 00:46:24 2008 From: tonic at nondot.org (Tanya Lattner) Date: Mon, 04 Feb 2008 06:46:24 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r46700 - in /llvm-gcc-4.2/branches/release_22/gcc/config/arm: arm.c arm.h bpabi.h Message-ID: <200802040646.m146kOFk026292@zion.cs.uiuc.edu> Author: tbrethou Date: Mon Feb 4 00:46:23 2008 New Revision: 46700 URL: http://llvm.org/viewvc/llvm-project?rev=46700&view=rev Log: Merge from mainline. Fix the build for arm-linux-gnueabi. Modified: llvm-gcc-4.2/branches/release_22/gcc/config/arm/arm.c llvm-gcc-4.2/branches/release_22/gcc/config/arm/arm.h llvm-gcc-4.2/branches/release_22/gcc/config/arm/bpabi.h Modified: llvm-gcc-4.2/branches/release_22/gcc/config/arm/arm.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/branches/release_22/gcc/config/arm/arm.c?rev=46700&r1=46699&r2=46700&view=diff ============================================================================== --- llvm-gcc-4.2/branches/release_22/gcc/config/arm/arm.c (original) +++ llvm-gcc-4.2/branches/release_22/gcc/config/arm/arm.c Mon Feb 4 00:46:23 2008 @@ -15165,13 +15165,14 @@ const char *function_name; /* Darwin/mach-o: use a stub for dynamic references. */ - if (TARGET_MACHO - && (flag_pic || MACHO_DYNAMIC_NO_PIC_P) +#if TARGET_MACHO + if ((flag_pic || MACHO_DYNAMIC_NO_PIC_P) && ! machopic_data_defined_p (function_rtx)) function_name = machopic_indirection_name (function_rtx, true); - else - function_name = XSTR (function_rtx, 0); +#else + function_name = XSTR (function_rtx, 0); +#endif /* APPLE LOCAL ARM end 4745175 */ if (mi_delta < 0) Modified: llvm-gcc-4.2/branches/release_22/gcc/config/arm/arm.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/branches/release_22/gcc/config/arm/arm.h?rev=46700&r1=46699&r2=46700&view=diff ============================================================================== --- llvm-gcc-4.2/branches/release_22/gcc/config/arm/arm.h (original) +++ llvm-gcc-4.2/branches/release_22/gcc/config/arm/arm.h Mon Feb 4 00:46:23 2008 @@ -31,6 +31,9 @@ #ifndef TARGET_MACHO #define TARGET_MACHO 0 #endif +#ifndef MACHO_DYNAMIC_NO_PIC_P +#define MACHO_DYNAMIC_NO_PIC_P 0 +#endif /* APPLE LOCAL end ARM darwin target */ /* APPLE LOCAL ARM interworking */ @@ -1830,9 +1833,15 @@ #define SHORT_CALL_FLAG_CHAR '^' #define LONG_CALL_FLAG_CHAR '#' +#define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \ + (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR) + #define SYMBOL_SHORT_CALL_ATTR_P(SYMBOL) \ (SYMBOL_REF_FLAGS (SYMBOL) & SYMBOL_SHORT_CALL) +#define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \ + (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR) + #define SYMBOL_LONG_CALL_ATTR_P(SYMBOL) \ (SYMBOL_REF_FLAGS (SYMBOL) & SYMBOL_LONG_CALL) Modified: llvm-gcc-4.2/branches/release_22/gcc/config/arm/bpabi.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/branches/release_22/gcc/config/arm/bpabi.h?rev=46700&r1=46699&r2=46700&view=diff ============================================================================== --- llvm-gcc-4.2/branches/release_22/gcc/config/arm/bpabi.h (original) +++ llvm-gcc-4.2/branches/release_22/gcc/config/arm/bpabi.h Mon Feb 4 00:46:23 2008 @@ -35,7 +35,9 @@ /* EABI targets should enable interworking by default. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT MASK_INTERWORK +/* LLVM Local begin */ +#define TARGET_DEFAULT (0) +/* LLVM Local end */ /* The ARM BPABI functions return a boolean; they use no special calling convention. */ From tonic at nondot.org Mon Feb 4 00:47:14 2008 From: tonic at nondot.org (Tanya Lattner) Date: Mon, 04 Feb 2008 06:47:14 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r46701 - /llvm-gcc-4.2/branches/release_22/gcc/config/arm/arm.c Message-ID: <200802040647.m146lEtG026334@zion.cs.uiuc.edu> Author: tbrethou Date: Mon Feb 4 00:47:14 2008 New Revision: 46701 URL: http://llvm.org/viewvc/llvm-project?rev=46701&view=rev Log: Merge from mainline. Fix my previous patch. It changed the behavior on TARGET_MACHO. Modified: llvm-gcc-4.2/branches/release_22/gcc/config/arm/arm.c Modified: llvm-gcc-4.2/branches/release_22/gcc/config/arm/arm.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/branches/release_22/gcc/config/arm/arm.c?rev=46701&r1=46700&r2=46701&view=diff ============================================================================== --- llvm-gcc-4.2/branches/release_22/gcc/config/arm/arm.c (original) +++ llvm-gcc-4.2/branches/release_22/gcc/config/arm/arm.c Mon Feb 4 00:47:14 2008 @@ -15167,9 +15167,11 @@ /* Darwin/mach-o: use a stub for dynamic references. */ #if TARGET_MACHO if ((flag_pic || MACHO_DYNAMIC_NO_PIC_P) - && ! machopic_data_defined_p (function_rtx)) - function_name = - machopic_indirection_name (function_rtx, true); + && ! machopic_data_defined_p (function_rtx)) + function_name = + machopic_indirection_name (function_rtx, true); + else + function_name = XSTR (function_rtx, 0); #else function_name = XSTR (function_rtx, 0); #endif From tonic at nondot.org Mon Feb 4 00:48:51 2008 From: tonic at nondot.org (Tanya Lattner) Date: Mon, 04 Feb 2008 06:48:51 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r46702 - /llvm-gcc-4.2/branches/release_22/gcc/config/arm/arm.c Message-ID: <200802040648.m146mpNk026396@zion.cs.uiuc.edu> Author: tbrethou Date: Mon Feb 4 00:48:51 2008 New Revision: 46702 URL: http://llvm.org/viewvc/llvm-project?rev=46702&view=rev Log: Merge from mainline. Eliminate a compilation warning. Modified: llvm-gcc-4.2/branches/release_22/gcc/config/arm/arm.c Modified: llvm-gcc-4.2/branches/release_22/gcc/config/arm/arm.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/branches/release_22/gcc/config/arm/arm.c?rev=46702&r1=46701&r2=46702&view=diff ============================================================================== --- llvm-gcc-4.2/branches/release_22/gcc/config/arm/arm.c (original) +++ llvm-gcc-4.2/branches/release_22/gcc/config/arm/arm.c Mon Feb 4 00:48:51 2008 @@ -15233,11 +15233,14 @@ (inter-module thumbness is fixed up by the linker). */ rtx tem = gen_rtx_SYMBOL_REF (Pmode, function_name); - if (TARGET_MACHO - && ! machopic_data_defined_p (function_rtx)) +#if TARGET_MACHO + if (! machopic_data_defined_p (function_rtx)) tem = gen_rtx_PLUS (GET_MODE (tem), tem, GEN_INT (-8)); else tem = gen_rtx_PLUS (GET_MODE (tem), tem, GEN_INT (-7)); +#else + tem = gen_rtx_PLUS (GET_MODE (tem), tem, GEN_INT (-7)); +#endif /* APPLE LOCAL end ARM 4745175 */ tem = gen_rtx_MINUS (GET_MODE (tem), From tonic at nondot.org Mon Feb 4 01:03:17 2008 From: tonic at nondot.org (Tanya Lattner) Date: Mon, 04 Feb 2008 07:03:17 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r46703 - /llvm-gcc-4.2/branches/release_22/gcc/llvm-types.cpp Message-ID: <200802040703.m1473HWr026934@zion.cs.uiuc.edu> Author: tbrethou Date: Mon Feb 4 01:03:17 2008 New Revision: 46703 URL: http://llvm.org/viewvc/llvm-project?rev=46703&view=rev Log: Patch to not turn gcc's pure/const markings into readonly/readnone if a parameter has a byval attribute. Modified: llvm-gcc-4.2/branches/release_22/gcc/llvm-types.cpp Modified: llvm-gcc-4.2/branches/release_22/gcc/llvm-types.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/branches/release_22/gcc/llvm-types.cpp?rev=46703&r1=46702&r2=46703&view=diff ============================================================================== --- llvm-gcc-4.2/branches/release_22/gcc/llvm-types.cpp (original) +++ llvm-gcc-4.2/branches/release_22/gcc/llvm-types.cpp Mon Feb 4 01:03:17 2008 @@ -1123,18 +1123,17 @@ // accepts it). But llvm IR does not allow both, so // set only ReadNone. if (flags & ECF_CONST) - // Since they write the return value through a pointer, - // 'sret' functions cannot be 'readnone'. - if (!ABIConverter.isStructReturn()) - RAttributes |= ParamAttr::ReadNone; + RAttributes |= ParamAttr::ReadNone; // Check for 'readonly' function attribute. if (flags & ECF_PURE && !(flags & ECF_CONST)) - // Since they write the return value through a pointer, - // 'sret' functions cannot be 'readonly'. - if (!ABIConverter.isStructReturn()) - RAttributes |= ParamAttr::ReadOnly; + RAttributes |= ParamAttr::ReadOnly; + // Since they write the return value through a pointer, + // 'sret' functions cannot be 'readnone' or 'readonly'. + if (ABIConverter.isStructReturn()) + RAttributes &= ~(ParamAttr::ReadNone|ParamAttr::ReadOnly); + // Compute whether the result needs to be zext or sext'd. RAttributes |= HandleArgumentExtension(TREE_TYPE(type)); @@ -1162,6 +1161,9 @@ LLVM_TARGET_INIT_REGPARM(local_regparam, type); #endif // LLVM_TARGET_ENABLE_REGPARM + // Keep track of whether we see a byval argument. + bool HasByVal = false; + // Check if we have a corresponding decl to inspect. tree DeclArgs = (decl) ? DECL_ARGUMENTS(decl) : NULL; // Loop over all of the arguments, adding them as we go. @@ -1208,13 +1210,27 @@ local_regparam); #endif // LLVM_TARGET_ENABLE_REGPARM - if (Attributes != ParamAttr::None) + if (Attributes != ParamAttr::None) { + HasByVal |= Attributes & ParamAttr::ByVal; Attrs.push_back(ParamAttrsWithIndex::get(ArgTypes.size(), Attributes)); + } if (DeclArgs) DeclArgs = TREE_CHAIN(DeclArgs); } + // If there is a byval argument then it is not safe to mark the function + // 'readnone' or 'readonly': gcc permits a 'const' or 'pure' function to + // write to struct arguments passed by value, but in LLVM this becomes a + // write through the byval pointer argument, which LLVM does not allow for + // readonly/readnone functions. + if (HasByVal && Attrs[0].index == 0) { + uint16_t &RAttrs = Attrs[0].attrs; + RAttrs &= ~(ParamAttr::ReadNone | ParamAttr::ReadOnly); + if (RAttrs == ParamAttr::None) + Attrs.erase(Attrs.begin()); + } + // If the argument list ends with a void type node, it isn't vararg. isVarArg = (Args == 0); assert(RetTy && "Return type not specified!"); From tonic at nondot.org Mon Feb 4 01:16:42 2008 From: tonic at nondot.org (Tanya Lattner) Date: Mon, 04 Feb 2008 07:16:42 -0000 Subject: [llvm-commits] [llvm-gcc-4.0] r46704 - /llvm-gcc-4.0/branches/release_22/gcc/llvm-types.cpp Message-ID: <200802040716.m147GgvZ027616@zion.cs.uiuc.edu> Author: tbrethou Date: Mon Feb 4 01:16:40 2008 New Revision: 46704 URL: http://llvm.org/viewvc/llvm-project?rev=46704&view=rev Log: Patch to not turn gcc's pure/const markings into readonly/readnone if a parameter has a byval attribute. Modified: llvm-gcc-4.0/branches/release_22/gcc/llvm-types.cpp Modified: llvm-gcc-4.0/branches/release_22/gcc/llvm-types.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.0/branches/release_22/gcc/llvm-types.cpp?rev=46704&r1=46703&r2=46704&view=diff ============================================================================== --- llvm-gcc-4.0/branches/release_22/gcc/llvm-types.cpp (original) +++ llvm-gcc-4.0/branches/release_22/gcc/llvm-types.cpp Mon Feb 4 01:16:40 2008 @@ -1043,17 +1043,16 @@ // Check for 'readnone' function attribute. if (flags & ECF_CONST) - // Since they write the return value through a pointer, - // 'sret' functions cannot be 'readnone'. - if (!ABIConverter.isStructReturn()) - RAttributes |= ParamAttr::ReadNone; + RAttributes |= ParamAttr::ReadNone; // Check for 'readonly' function attribute. - if (flags & ECF_PURE) - // Since they write the return value through a pointer, - // 'sret' functions cannot be 'readonly'. - if (!ABIConverter.isStructReturn()) - RAttributes |= ParamAttr::ReadOnly; + if (flags & ECF_PURE && !(flags & ECF_CONST)) + RAttributes |= ParamAttr::ReadOnly; + + // Since they write the return value through a pointer, + // 'sret' functions cannot be 'readnone' or 'readonly'. + if (ABIConverter.isStructReturn()) + RAttributes &= ~(ParamAttr::ReadNone|ParamAttr::ReadOnly); // Compute whether the result needs to be zext or sext'd. RAttributes |= HandleArgumentExtension(TREE_TYPE(type)); @@ -1082,6 +1081,9 @@ LLVM_TARGET_INIT_REGPARM(local_regparam, type); #endif // LLVM_TARGET_ENABLE_REGPARM + // Keep track of whether we see a byval argument. + bool HasByVal = false; + // Check if we have a corresponding decl to inspect. tree DeclArgs = (decl) ? DECL_ARGUMENTS(decl) : NULL; // Loop over all of the arguments, adding them as we go. @@ -1128,13 +1130,27 @@ local_regparam); #endif // LLVM_TARGET_ENABLE_REGPARM - if (Attributes != ParamAttr::None) + if (Attributes != ParamAttr::None) { + HasByVal |= Attributes & ParamAttr::ByVal; Attrs.push_back(ParamAttrsWithIndex::get(ArgTypes.size(), Attributes)); + } if (DeclArgs) DeclArgs = TREE_CHAIN(DeclArgs); } + // If there is a byval argument then it is not safe to mark the function + // 'readnone' or 'readonly': gcc permits a 'const' or 'pure' function to + // write to struct arguments passed by value, but in LLVM this becomes a + // write through the byval pointer argument, which LLVM does not allow for + // readonly/readnone functions. + if (HasByVal && Attrs[0].index == 0) { + uint16_t &RAttrs = Attrs[0].attrs; + RAttrs &= ~(ParamAttr::ReadNone | ParamAttr::ReadOnly); + if (RAttrs == ParamAttr::None) + Attrs.erase(Attrs.begin()); + } + // If the argument list ends with a void type node, it isn't vararg. isVarArg = (Args == 0); assert(RetTy && "Return type not specified!"); From baldrick at free.fr Mon Feb 4 03:29:18 2008 From: baldrick at free.fr (Duncan Sands) Date: Mon, 04 Feb 2008 09:29:18 -0000 Subject: [llvm-commits] [llvm] r46705 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp Message-ID: <200802040929.m149TIBt008573@zion.cs.uiuc.edu> Author: baldrick Date: Mon Feb 4 03:29:17 2008 New Revision: 46705 URL: http://llvm.org/viewvc/llvm-project?rev=46705&view=rev Log: I don't see how NodeUpdated can be called with a ReadyToProcess node - add an assertion to check this. Add an assertion to NodeDeleted that checks that processed/ready nodes are indeed not deleted. It is because they are never deleted that none of the maps can have a deleted node as the source of a mapping. It does however seem to be possible in theory to have a deleted value as the target of a mapping, however this has not yet been spotted in the wild. Still mulling on what to do about this. [The theoretical situation is this: a node A is expanded/promoted/whatever to a newly created node B. Thus A->B is added to a map. When the subtree rooted at B is legalized it is conceivable that B is deleted due to RAUW on a node somewhere above it]. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp?rev=46705&r1=46704&r2=46705&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp Mon Feb 4 03:29:17 2008 @@ -220,22 +220,27 @@ namespace { /// NodeUpdateListener - This class is a DAGUpdateListener that listens for /// updates to nodes and recomputes their ready state. - class VISIBILITY_HIDDEN NodeUpdateListener : + class VISIBILITY_HIDDEN NodeUpdateListener : public SelectionDAG::DAGUpdateListener { DAGTypeLegalizer &DTL; public: NodeUpdateListener(DAGTypeLegalizer &dtl) : DTL(dtl) {} - + virtual void NodeDeleted(SDNode *N) { // Ignore deletes. + assert(N->getNodeId() != DAGTypeLegalizer::Processed && + N->getNodeId() != DAGTypeLegalizer::ReadyToProcess && + "RAUW deleted processed node!"); } - + virtual void NodeUpdated(SDNode *N) { // Node updates can mean pretty much anything. It is possible that an // operand was set to something already processed (f.e.) in which case // this node could become ready. Recompute its flags. - if (N->getNodeId() != DAGTypeLegalizer::ReadyToProcess) - DTL.ReanalyzeNodeFlags(N); + assert(N->getNodeId() != DAGTypeLegalizer::Processed && + N->getNodeId() != DAGTypeLegalizer::ReadyToProcess && + "RAUW updated processed node!"); + DTL.ReanalyzeNodeFlags(N); } }; } From baldrick at free.fr Mon Feb 4 03:40:27 2008 From: baldrick at free.fr (Duncan Sands) Date: Mon, 04 Feb 2008 09:40:27 -0000 Subject: [llvm-commits] [llvm] r46706 - /llvm/trunk/test/CodeGen/Generic/2008-01-30-LoadCrash.ll Message-ID: <200802040940.m149eSx4008857@zion.cs.uiuc.edu> Author: baldrick Date: Mon Feb 4 03:40:27 2008 New Revision: 46706 URL: http://llvm.org/viewvc/llvm-project?rev=46706&view=rev Log: Crashed the new type legalizer. Not likely to catch any bugs in the future since to get the crash you also need hacked in fake libcall support (which creates odd but legal trees), but since adding it doesn't hurt... Thanks to Chris for this ultimately reduced version. Added: llvm/trunk/test/CodeGen/Generic/2008-01-30-LoadCrash.ll Added: llvm/trunk/test/CodeGen/Generic/2008-01-30-LoadCrash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2008-01-30-LoadCrash.ll?rev=46706&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Generic/2008-01-30-LoadCrash.ll (added) +++ llvm/trunk/test/CodeGen/Generic/2008-01-30-LoadCrash.ll Mon Feb 4 03:40:27 2008 @@ -0,0 +1,21 @@ +; RUN: llvm-as < %s | llc + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32" +target triple = "i686-pc-linux-gnu" + at letters.3100 = external constant [63 x i8] ; <[63 x i8]*> [#uses=2] + +define i32 @mkstemps(i8* %pattern, i32 %suffix_len, i64 %tmp42.rle) nounwind { +bb20: + br label %bb41 + +bb41: ; preds = %bb20 + %tmp8182 = trunc i64 %tmp42.rle to i32 ; [#uses=1] + %tmp83 = getelementptr [63 x i8]* @letters.3100, i32 0, i32 %tmp8182 ; [#uses=1] + %tmp84 = load i8* %tmp83, align 1 ; [#uses=1] + store i8 %tmp84, i8* null, align 1 + %tmp90 = urem i64 %tmp42.rle, 62 ; [#uses=1] + %tmp9091 = trunc i64 %tmp90 to i32 ; [#uses=1] + %tmp92 = getelementptr [63 x i8]* @letters.3100, i32 0, i32 %tmp9091 ; [#uses=1] + store i8* %tmp92, i8** null, align 1 + ret i32 -1 +} From kremenek at apple.com Mon Feb 4 10:57:38 2008 From: kremenek at apple.com (Ted Kremenek) Date: Mon, 04 Feb 2008 16:57:38 -0000 Subject: [llvm-commits] [llvm] r46707 - /llvm/trunk/include/llvm/ADT/APSInt.h Message-ID: <200802041657.m14GvjA9025374@zion.cs.uiuc.edu> Author: kremenek Date: Mon Feb 4 10:57:26 2008 New Revision: 46707 URL: http://llvm.org/viewvc/llvm-project?rev=46707&view=rev Log: constified operator~(). Modified: llvm/trunk/include/llvm/ADT/APSInt.h Modified: llvm/trunk/include/llvm/ADT/APSInt.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/APSInt.h?rev=46707&r1=46706&r2=46707&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/APSInt.h (original) +++ llvm/trunk/include/llvm/ADT/APSInt.h Mon Feb 4 10:57:26 2008 @@ -223,7 +223,7 @@ assert(IsUnsigned == RHS.IsUnsigned && "Signedness mismatch!"); return APSInt(static_cast(*this) - RHS, IsUnsigned); } - APSInt operator~() { + APSInt operator~() const { return APSInt(~static_cast(*this), IsUnsigned); } From kremenek at apple.com Mon Feb 4 11:14:46 2008 From: kremenek at apple.com (Ted Kremenek) Date: Mon, 04 Feb 2008 17:14:46 -0000 Subject: [llvm-commits] [llvm] r46709 - /llvm/trunk/lib/Support/FoldingSet.cpp Message-ID: <200802041714.m14HErbS025926@zion.cs.uiuc.edu> Author: kremenek Date: Mon Feb 4 11:14:20 2008 New Revision: 46709 URL: http://llvm.org/viewvc/llvm-project?rev=46709&view=rev Log: Fixed 80 col. violation. Modified: llvm/trunk/lib/Support/FoldingSet.cpp Modified: llvm/trunk/lib/Support/FoldingSet.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/FoldingSet.cpp?rev=46709&r1=46708&r2=46709&view=diff ============================================================================== --- llvm/trunk/lib/Support/FoldingSet.cpp (original) +++ llvm/trunk/lib/Support/FoldingSet.cpp Mon Feb 4 11:14:20 2008 @@ -221,8 +221,10 @@ /// FindNodeOrInsertPos - Look up the node specified by ID. If it exists, /// return it. If not, return the insertion token that will make insertion /// faster. -FoldingSetImpl::Node *FoldingSetImpl::FindNodeOrInsertPos(const FoldingSetNodeID &ID, - void *&InsertPos) { +FoldingSetImpl::Node +*FoldingSetImpl::FindNodeOrInsertPos(const FoldingSetNodeID &ID, + void *&InsertPos) { + void **Bucket = GetBucketFor(ID, Buckets, NumBuckets); void *Probe = *Bucket; From baldrick at free.fr Mon Feb 4 11:21:43 2008 From: baldrick at free.fr (Duncan Sands) Date: Mon, 04 Feb 2008 17:21:43 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r46710 - in /llvm-gcc-4.2/trunk/gcc: llvm-convert.cpp llvm-internal.h Message-ID: <200802041721.m14HLmaG026157@zion.cs.uiuc.edu> Author: baldrick Date: Mon Feb 4 11:21:32 2008 New Revision: 46710 URL: http://llvm.org/viewvc/llvm-project?rev=46710&view=rev Log: Fix PR1942, hopefully correctly. This is the same as the previous fix except that a temporary buffer is not used if CALL_EXPR_RETURN_SLOT_OPT is true. This flag is sometimes used to indicate front-end semantic requirements and cannot be ignored. Also, unlike in the previous fixes, keep the mucking around with RESULT_DECL in EmitMODIFY_EXPR, only tweak it to match the logic in expand_assignment (expr.c). While there I introduced some symbolic names, tweaked some existing names and cleaned up trailing whitespace. Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp llvm-gcc-4.2/trunk/gcc/llvm-internal.h Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=46710&r1=46709&r2=46710&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Mon Feb 4 11:21:32 2008 @@ -2308,6 +2308,7 @@ CallingConv::ID &CallingConvention; LLVMBuilder &Builder; const MemRef *DestLoc; + MemRef BufLoc; std::vector LocStack; FunctionCallArgumentConversion(tree exp, SmallVector &ops, @@ -2339,7 +2340,19 @@ assert(LocStack.size() == 1 && "Imbalance!"); LocStack.clear(); } - + + // CopyOutResult - If the (aggregate) return result was redirected to a + // buffer, copy it to the final destination. + void CopyOutResult(tree result_type) { + if (BufLoc.Ptr && DestLoc) { + // A buffer was used for the aggregate return result. Copy it out now. + assert(ConvertType(result_type) == + cast(BufLoc.Ptr->getType())->getElementType() && + "Inconsistent result types!"); + TheTreeToLLVM->EmitAggregateCopy(*DestLoc, BufLoc, result_type); + } + } + /// HandleScalarResult - This callback is invoked if the function returns a /// simple scalar result value. void HandleScalarResult(const Type *RetTy) { @@ -2354,27 +2367,34 @@ void HandleAggregateResultAsScalar(const Type *ScalarTy) { // There is nothing to do here. } - + /// HandleAggregateShadowArgument - This callback is invoked if the function /// returns an aggregate value by using a "shadow" first parameter. If /// RetPtr is set to true, the pointer argument itself is returned from the /// function. void HandleAggregateShadowArgument(const PointerType *PtrArgTy, bool RetPtr) { - // We need to pass a buffer to return into. If the caller uses the - // result, DestLoc will be set. If it ignores it, it could be unset, - // in which case we need to create a dummy buffer. - // FIXME: The alignment and volatility of the buffer are being ignored! - Value *DestPtr; + // We need to pass memory to write the return value into. + // FIXME: alignment and volatility are being ignored! + assert(!DestLoc || PtrArgTy == DestLoc->Ptr->getType()); + if (DestLoc == 0) { - DestPtr = TheTreeToLLVM->CreateTemporary(PtrArgTy->getElementType()); + // The result is unused, but still needs to be stored somewhere. + Value *Buf = TheTreeToLLVM->CreateTemporary(PtrArgTy->getElementType()); + CallOperands.push_back(Buf); + } else if (CALL_EXPR_RETURN_SLOT_OPT(CallExpression)) { + // Letting the call write directly to the final destination is safe and + // may be required. Do not use a buffer. + CallOperands.push_back(DestLoc->Ptr); } else { - DestPtr = DestLoc->Ptr; - assert(PtrArgTy == DestPtr->getType()); + // Letting the call write directly to the final destination may not be + // safe (eg: if DestLoc aliases a parameter) and is not required - pass + // a buffer and copy it to DestLoc after the call. + BufLoc = TheTreeToLLVM->CreateTempLoc(PtrArgTy->getElementType()); + CallOperands.push_back(BufLoc.Ptr); } - CallOperands.push_back(DestPtr); } - + void HandleScalarArgument(const llvm::Type *LLVMTy, tree type) { assert(!LocStack.empty()); Value *Loc = LocStack.back(); @@ -2543,7 +2563,9 @@ cast(Call)->setParamAttrs(PAL); EmitBlock(NextBlock); } - + + Client.CopyOutResult(TREE_TYPE(exp)); + if (Call->getType() == Type::VoidTy) return 0; @@ -2626,50 +2648,48 @@ /// EmitMODIFY_EXPR - Note that MODIFY_EXPRs are rvalues only! /// Value *TreeToLLVM::EmitMODIFY_EXPR(tree exp, const MemRef *DestLoc) { + tree lhs = TREE_OPERAND (exp, 0); + tree rhs = TREE_OPERAND (exp, 1); + // If this is the definition of an SSA variable, set its DECL_LLVM to the // RHS. - bool Op0Signed = !TYPE_UNSIGNED(TREE_TYPE(TREE_OPERAND(exp, 0))); - bool Op1Signed = !TYPE_UNSIGNED(TREE_TYPE(TREE_OPERAND(exp, 1))); - if (isGCC_SSA_Temporary(TREE_OPERAND(exp, 0))) { + bool LHSSigned = !TYPE_UNSIGNED(TREE_TYPE(lhs)); + bool RHSSigned = !TYPE_UNSIGNED(TREE_TYPE(rhs)); + if (isGCC_SSA_Temporary(lhs)) { // If DECL_LLVM is already set, this is a multiply defined GCC temporary. - if (DECL_LLVM_SET_P(TREE_OPERAND(exp, 0))) { - HandleMultiplyDefinedGCCTemp(TREE_OPERAND(exp, 0)); + if (DECL_LLVM_SET_P(lhs)) { + HandleMultiplyDefinedGCCTemp(lhs); return EmitMODIFY_EXPR(exp, DestLoc); } - - Value *RHS = Emit(TREE_OPERAND(exp, 1), 0); - RHS = CastToAnyType(RHS, Op1Signed, - ConvertType(TREE_TYPE(TREE_OPERAND(exp, 0))), - Op0Signed); - SET_DECL_LLVM(TREE_OPERAND(exp, 0), RHS); + + Value *RHS = Emit(rhs, 0); + RHS = CastToAnyType(RHS, RHSSigned, ConvertType(TREE_TYPE(lhs)), LHSSigned); + SET_DECL_LLVM(lhs, RHS); return RHS; - } else if (TREE_CODE(TREE_OPERAND(exp, 0)) == VAR_DECL && - DECL_REGISTER(TREE_OPERAND(exp, 0)) && - TREE_STATIC(TREE_OPERAND(exp, 0))) { + } else if (TREE_CODE(lhs) == VAR_DECL && DECL_REGISTER(lhs) && + TREE_STATIC(lhs)) { // If this is a store to a register variable, EmitLV can't handle the dest // (there is no l-value of a register variable). Emit an inline asm node // that copies the value into the specified register. - Value *RHS = Emit(TREE_OPERAND(exp, 1), 0); - RHS = CastToAnyType(RHS, Op1Signed, - ConvertType(TREE_TYPE(TREE_OPERAND(exp, 0))), - Op0Signed); - EmitModifyOfRegisterVariable(TREE_OPERAND(exp, 0), RHS); + Value *RHS = Emit(rhs, 0); + RHS = CastToAnyType(RHS, RHSSigned, ConvertType(TREE_TYPE(lhs)), LHSSigned); + EmitModifyOfRegisterVariable(lhs, RHS); return RHS; } - - LValue LV = EmitLV(TREE_OPERAND(exp, 0)); - bool isVolatile = TREE_THIS_VOLATILE(TREE_OPERAND(exp, 0)); - unsigned Alignment = expr_align(TREE_OPERAND(exp, 0)) / 8; + + LValue LV = EmitLV(lhs); + bool isVolatile = TREE_THIS_VOLATILE(lhs); + unsigned Alignment = expr_align(lhs) / 8; if (!LV.isBitfield()) { - const Type *ValTy = ConvertType(TREE_TYPE(TREE_OPERAND(exp, 1))); + const Type *ValTy = ConvertType(TREE_TYPE(rhs)); if (ValTy->isFirstClassType()) { // Non-bitfield, scalar value. Just emit a store. - Value *RHS = Emit(TREE_OPERAND(exp, 1), 0); + Value *RHS = Emit(rhs, 0); // Convert RHS to the right type if we can, otherwise convert the pointer. const PointerType *PT = cast(LV.Ptr->getType()); if (PT->getElementType()->canLosslesslyBitCastTo(RHS->getType())) - RHS = CastToAnyType(RHS, Op1Signed, PT->getElementType(), Op0Signed); + RHS = CastToAnyType(RHS, RHSSigned, PT->getElementType(), LHSSigned); else LV.Ptr = BitCastToType(LV.Ptr, PointerType::getUnqual(RHS->getType())); StoreInst *SI = Builder.CreateStore(RHS, LV.Ptr, isVolatile); @@ -2680,27 +2700,27 @@ // Non-bitfield aggregate value. MemRef NewLoc(LV.Ptr, Alignment, isVolatile); - if (DestLoc) { - Emit(TREE_OPERAND(exp, 1), &NewLoc); - EmitAggregateCopy(*DestLoc, NewLoc, TREE_TYPE(exp)); - } else if (TREE_CODE(TREE_OPERAND(exp, 0)) != RESULT_DECL) { - Emit(TREE_OPERAND(exp, 1), &NewLoc); + // In case we are returning the contents of an object which overlaps + // the place the value is being stored, use a safe function when copying + // a value through a pointer into a structure value return block. + if (TREE_CODE (lhs) == RESULT_DECL && TREE_CODE (rhs) == INDIRECT_REF) { + MemRef Tmp = CreateTempLoc(ConvertType(TREE_TYPE(rhs))); + Emit(rhs, &Tmp); + EmitAggregateCopy(NewLoc, Tmp, TREE_TYPE(rhs)); } else { - // We do this for stores into RESULT_DECL because it is possible for that - // memory area to overlap with the object being stored into it; see - // gcc.c-torture/execute/20010124-1.c. - - MemRef Tmp = CreateTempLoc(ConvertType(TREE_TYPE(TREE_OPERAND(exp,1)))); - Emit(TREE_OPERAND(exp, 1), &Tmp); - EmitAggregateCopy(NewLoc, Tmp, TREE_TYPE(TREE_OPERAND(exp,1))); + Emit(rhs, &NewLoc); } + + if (DestLoc) + EmitAggregateCopy(*DestLoc, NewLoc, TREE_TYPE(exp)); + return 0; } - // Last case, this is a store to a bitfield, so we have to emit a + // Last case, this is a store to a bitfield, so we have to emit a // read/modify/write sequence. - Value *RHS = Emit(TREE_OPERAND(exp, 1), 0); + Value *RHS = Emit(rhs, 0); if (!LV.BitSize) return RHS; @@ -2716,7 +2736,7 @@ assert(ValSizeInBits >= LV.BitSize && "Bad bitfield lvalue!"); assert(2*ValSizeInBits > LV.BitSize+LV.BitStart && "Bad bitfield lvalue!"); - Value *BitSource = CastToAnyType(RHS, Op1Signed, ValTy, Op0Signed); + Value *BitSource = CastToAnyType(RHS, RHSSigned, ValTy, LHSSigned); for (unsigned I = 0; I < Strides; I++) { unsigned Index = BYTES_BIG_ENDIAN ? Strides - I - 1 : I; // LSB first Modified: llvm-gcc-4.2/trunk/gcc/llvm-internal.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-internal.h?rev=46710&r1=46709&r2=46710&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-internal.h (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-internal.h Mon Feb 4 11:21:32 2008 @@ -386,6 +386,13 @@ /// instruction's type is a pointer to the specified type. AllocaInst *CreateTemporary(const Type *Ty); + /// CreateTempLoc - Like CreateTemporary, but returns a MemRef. + MemRef CreateTempLoc(const Type *Ty); + + /// EmitAggregateCopy - Copy the elements from SrcLoc to DestLoc, using the + /// GCC type specified by GCCType to know which elements to copy. + void EmitAggregateCopy(MemRef DestLoc, MemRef SrcLoc, tree_node *GCCType); + private: // Helper functions. /// StartFunctionBody - Start the emission of 'fndecl', outputing all @@ -406,10 +413,6 @@ /// the previous block falls through into it, add an explicit branch. void EmitBlock(BasicBlock *BB); - /// EmitAggregateCopy - Copy the elements from SrcLoc to DestLoc, using the - /// GCC type specified by GCCType to know which elements to copy. - void EmitAggregateCopy(MemRef DestLoc, MemRef SrcLoc, tree_node *GCCType); - /// EmitAggregateZero - Zero the elements of DestLoc. /// void EmitAggregateZero(MemRef DestLoc, tree_node *GCCType); @@ -443,9 +446,6 @@ BasicBlock *getPostPad(unsigned RegionNo); private: - /// CreateTempLoc - Like CreateTemporary, but returns a MemRef. - MemRef CreateTempLoc(const Type *Ty); - void EmitAutomaticVariableDecl(tree_node *decl); /// isNoopCast - Return true if a cast from V to Ty does not change any bits. From clattner at apple.com Mon Feb 4 12:00:48 2008 From: clattner at apple.com (Chris Lattner) Date: Mon, 4 Feb 2008 10:00:48 -0800 Subject: [llvm-commits] [llvm] r46681 - in /llvm/trunk: include/llvm/IntrinsicsX86.td lib/Target/X86/X86.td lib/Target/X86/X86Instr64bit.td lib/Target/X86/X86InstrInfo.td lib/Target/X86/X86InstrSSE.td lib/Target/X86/X86Subtarget.cpp lib/Target/X86/X86Subtarget.h In-Reply-To: <200802030718.m137IsIO014453@zion.cs.uiuc.edu> References: <200802030718.m137IsIO014453@zion.cs.uiuc.edu> Message-ID: On Feb 2, 2008, at 11:18 PM, Nate Begeman wrote: > +// Vector insert > +let TargetPrefix = "x86" in { // All intrinsics start with > "llvm.x86.". > + def int_x86_sse41_pinsrb : > GCCBuiltin<"__builtin_ia32_vec_set_v16qi">, > + Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty, > llvm_i32_ty]>; > + def int_x86_sse41_pinsrd : > GCCBuiltin<"__builtin_ia32_vec_set_v4si">, > + Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_i32_ty, > llvm_i32_ty]>; > + def int_x86_sse41_pinsrq : > GCCBuiltin<"__builtin_ia32_vec_set_v2di">, > + Intrinsic<[llvm_v2i64_ty, llvm_v2i64_ty, llvm_i64_ty, > llvm_i32_ty]>; > + def int_x86_sse41_insertps : > GCCBuiltin<"__builtin_ia32_insertps128">, > + Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, > llvm_i32_ty]>; > +} Hey Nate, I think that some of these should be lowered in the front-end into the corresponding llvm instruction. For example, I think these should turn into insertelement instructions, and some of the other shuffles should turn into vector_shuffle instructions. This relies on the code generator to match the operations and turn them back into the "right thing" which ensures that the code generator aggressively matches the 'non intrinsic' forms of these operations when possible. -Chris From sabre at nondot.org Mon Feb 4 12:02:40 2008 From: sabre at nondot.org (Chris Lattner) Date: Mon, 04 Feb 2008 18:02:40 -0000 Subject: [llvm-commits] [llvm] r46711 - /llvm/trunk/test/CodeGen/Generic/2008-01-30-LoadCrash.ll Message-ID: <200802041802.m14I2fUd028493@zion.cs.uiuc.edu> Author: lattner Date: Mon Feb 4 12:02:37 2008 New Revision: 46711 URL: http://llvm.org/viewvc/llvm-project?rev=46711&view=rev Log: remove target triple to make this test more "generic" Modified: llvm/trunk/test/CodeGen/Generic/2008-01-30-LoadCrash.ll Modified: llvm/trunk/test/CodeGen/Generic/2008-01-30-LoadCrash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2008-01-30-LoadCrash.ll?rev=46711&r1=46710&r2=46711&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Generic/2008-01-30-LoadCrash.ll (original) +++ llvm/trunk/test/CodeGen/Generic/2008-01-30-LoadCrash.ll Mon Feb 4 12:02:37 2008 @@ -1,7 +1,5 @@ ; RUN: llvm-as < %s | llc -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32" -target triple = "i686-pc-linux-gnu" @letters.3100 = external constant [63 x i8] ; <[63 x i8]*> [#uses=2] define i32 @mkstemps(i8* %pattern, i32 %suffix_len, i64 %tmp42.rle) nounwind { From clattner at apple.com Mon Feb 4 12:04:24 2008 From: clattner at apple.com (Chris Lattner) Date: Mon, 4 Feb 2008 10:04:24 -0800 Subject: [llvm-commits] [llvm] r46705 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp In-Reply-To: <200802040929.m149TIBt008573@zion.cs.uiuc.edu> References: <200802040929.m149TIBt008573@zion.cs.uiuc.edu> Message-ID: <8DD5228B-EF6C-4F2F-8303-243A09E4C703@apple.com> On Feb 4, 2008, at 1:29 AM, Duncan Sands wrote: > Author: baldrick > Date: Mon Feb 4 03:29:17 2008 > New Revision: 46705 > > URL: http://llvm.org/viewvc/llvm-project?rev=46705&view=rev > Log: > I don't see how NodeUpdated can be called with a > ReadyToProcess node - add an assertion to check > this. Add an assertion to NodeDeleted that checks The assertion seems correct to me, thanks Duncan! -Chris From baldrick at free.fr Mon Feb 4 12:05:43 2008 From: baldrick at free.fr (Duncan Sands) Date: Mon, 04 Feb 2008 18:05:43 -0000 Subject: [llvm-commits] [llvm] r46712 - /llvm/trunk/test/CodeGen/Generic/2008-02-04-ExtractSubvector.ll Message-ID: <200802041805.m14I5hXa028649@zion.cs.uiuc.edu> Author: baldrick Date: Mon Feb 4 12:05:42 2008 New Revision: 46712 URL: http://llvm.org/viewvc/llvm-project?rev=46712&view=rev Log: Crashes LegalizeTypes with "Do not know how to split this operator's operand" (node: extract_subvector). Added: llvm/trunk/test/CodeGen/Generic/2008-02-04-ExtractSubvector.ll Added: llvm/trunk/test/CodeGen/Generic/2008-02-04-ExtractSubvector.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2008-02-04-ExtractSubvector.ll?rev=46712&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Generic/2008-02-04-ExtractSubvector.ll (added) +++ llvm/trunk/test/CodeGen/Generic/2008-02-04-ExtractSubvector.ll Mon Feb 4 12:05:42 2008 @@ -0,0 +1,14 @@ +; RUN: llvm-as < %s | llc + +define i32 @main() nounwind { +entry: + br label %bb15 + +bb15: ; preds = %bb15, %entry + %tmp21 = add <8 x double> zeroinitializer, zeroinitializer ; <<8 x double>> [#uses=1] + br i1 false, label %bb30, label %bb15 + +bb30: ; preds = %bb15 + store <8 x double> %tmp21, <8 x double>* null, align 64 + ret i32 0 +} From baldrick at free.fr Mon Feb 4 12:07:03 2008 From: baldrick at free.fr (Duncan Sands) Date: Mon, 04 Feb 2008 18:07:03 -0000 Subject: [llvm-commits] [llvm] r46713 - /llvm/trunk/test/CodeGen/Generic/2008-02-04-Ctlz.ll Message-ID: <200802041807.m14I73W0028700@zion.cs.uiuc.edu> Author: baldrick Date: Mon Feb 4 12:07:02 2008 New Revision: 46713 URL: http://llvm.org/viewvc/llvm-project?rev=46713&view=rev Log: Crashes LegalizeTypes with "Do not know how to expand the result of this operator!" (node: ctlz). Added: llvm/trunk/test/CodeGen/Generic/2008-02-04-Ctlz.ll Added: llvm/trunk/test/CodeGen/Generic/2008-02-04-Ctlz.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2008-02-04-Ctlz.ll?rev=46713&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Generic/2008-02-04-Ctlz.ll (added) +++ llvm/trunk/test/CodeGen/Generic/2008-02-04-Ctlz.ll Mon Feb 4 12:07:02 2008 @@ -0,0 +1,22 @@ +; RUN: llvm-as < %s | llc + + at .str3 = external constant [56 x i8] ; <[56 x i8]*> [#uses=1] + +define i32 @main() nounwind { +entry: + br label %bb30 + +bb30: ; preds = %bb30, %entry + %l.024 = phi i64 [ -10000, %entry ], [ 0, %bb30 ] ; [#uses=2] + %tmp37 = tail call i64 @llvm.ctlz.i64( i64 %l.024 ) ; [#uses=1] + trunc i64 %tmp37 to i32 ; :0 [#uses=1] + %tmp40 = tail call i32 (i8*, ...)* @printf( i8* noalias getelementptr ([56 x i8]* @.str3, i32 0, i32 0), i64 %l.024, i32 %0, i32 0, i32 0 ) nounwind ; [#uses=0] + br i1 false, label %bb30, label %bb9.i + +bb9.i: ; preds = %bb30 + ret i32 0 +} + +declare i32 @printf(i8* noalias , ...) nounwind + +declare i64 @llvm.ctlz.i64(i64) nounwind readnone From sabre at nondot.org Mon Feb 4 13:02:12 2008 From: sabre at nondot.org (Chris Lattner) Date: Mon, 04 Feb 2008 19:02:12 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r46714 - /llvm-gcc-4.2/trunk/README.LLVM Message-ID: <200802041902.m14J2Egs027941@zion.cs.uiuc.edu> Author: lattner Date: Mon Feb 4 13:01:58 2008 New Revision: 46714 URL: http://llvm.org/viewvc/llvm-project?rev=46714&view=rev Log: An additional symlink is required to find libstdc++. Modified: llvm-gcc-4.2/trunk/README.LLVM Modified: llvm-gcc-4.2/trunk/README.LLVM URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/README.LLVM?rev=46714&r1=46713&r2=46714&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/README.LLVM (original) +++ llvm-gcc-4.2/trunk/README.LLVM Mon Feb 4 13:01:58 2008 @@ -127,6 +127,7 @@ $ make $BUILDOPTIONS $ make install $ ln -sf /usr/lib/libstdc++.6.dylib `pwd`/../install/lib +$ ln -sf /usr/lib/libstdc++.6.dylib `pwd`/../install/lib/libstdc++.dylib That last step, "ln -sf ..." is required so that the linker (collect2) can find libstdc++ ('-lstdc++') and subsequently link C++ executables correctly. From dpatel at apple.com Mon Feb 4 14:58:06 2008 From: dpatel at apple.com (Devang Patel) Date: Mon, 04 Feb 2008 20:58:06 -0000 Subject: [llvm-commits] [llvm] r46715 - /llvm/trunk/lib/System/Unix/Program.inc Message-ID: <200802042058.m14Kw7xj016312@zion.cs.uiuc.edu> Author: dpatel Date: Mon Feb 4 14:57:54 2008 New Revision: 46715 URL: http://llvm.org/viewvc/llvm-project?rev=46715&view=rev Log: Set error message. Patch by Shantonu Sen. Modified: llvm/trunk/lib/System/Unix/Program.inc Modified: llvm/trunk/lib/System/Unix/Program.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Unix/Program.inc?rev=46715&r1=46714&r2=46715&view=diff ============================================================================== --- llvm/trunk/lib/System/Unix/Program.inc (original) +++ llvm/trunk/lib/System/Unix/Program.inc Mon Feb 4 14:57:54 2008 @@ -242,9 +242,11 @@ // Wait for child to die if (wait(&status) != child) MakeErrMsg(ErrMsg, "Child timed out but wouldn't die"); - + else + MakeErrMsg(ErrMsg, "Child timed out", 0); + return -1; // Timeout detected - } else { + } else if (errno != EINTR) { MakeErrMsg(ErrMsg, "Error waiting for child process"); return -1; } From kremenek at apple.com Mon Feb 4 15:11:34 2008 From: kremenek at apple.com (Ted Kremenek) Date: Mon, 04 Feb 2008 21:11:34 -0000 Subject: [llvm-commits] [llvm] r46716 - in /llvm/trunk: include/llvm/ADT/FoldingSet.h lib/Support/FoldingSet.cpp Message-ID: <200802042111.m14LBaHo016736@zion.cs.uiuc.edu> Author: kremenek Date: Mon Feb 4 15:11:17 2008 New Revision: 46716 URL: http://llvm.org/viewvc/llvm-project?rev=46716&view=rev Log: Added "bucket_iterators" to FoldingSet. Bucket iterators allow iteration over all the nodes in a particular bucket. Modified: llvm/trunk/include/llvm/ADT/FoldingSet.h llvm/trunk/lib/Support/FoldingSet.cpp Modified: llvm/trunk/include/llvm/ADT/FoldingSet.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/FoldingSet.h?rev=46716&r1=46715&r2=46716&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/FoldingSet.h (original) +++ llvm/trunk/include/llvm/ADT/FoldingSet.h Mon Feb 4 15:11:17 2008 @@ -224,6 +224,7 @@ // Convenience type to hide the implementation of the folding set. typedef FoldingSetImpl::Node FoldingSetNode; template class FoldingSetIterator; +template class FoldingSetBucketIterator; //===----------------------------------------------------------------------===// /// FoldingSetTrait - This trait class is used to define behavior of how @@ -265,6 +266,16 @@ const_iterator begin() const { return const_iterator(Buckets); } const_iterator end() const { return const_iterator(Buckets+NumBuckets); } + typedef FoldingSetBucketIterator bucket_iterator; + + bucket_iterator bucket_begin(unsigned hash) { + return bucket_iterator(Buckets + (hash & (NumBuckets-1))); + } + + bucket_iterator bucket_end(unsigned hash) { + return bucket_iterator(Buckets + (hash & (NumBuckets-1)), true); + } + /// GetOrInsertNode - If there is an existing simple Node exactly /// equal to the specified node, return it. Otherwise, insert 'N' and /// return it instead. @@ -322,6 +333,57 @@ }; //===----------------------------------------------------------------------===// +/// FoldingSetBucketIteratorImpl - This is the common bucket iterator support +/// shared by all folding sets, which knows how to walk a particular bucket +/// of a folding set hash table. + +class FoldingSetBucketIteratorImpl { +protected: + void *Ptr; + + FoldingSetBucketIteratorImpl(void **Bucket); + + FoldingSetBucketIteratorImpl(void **Bucket, bool) + : Ptr(reinterpret_cast(Bucket)) {} + + void advance() { + void *Probe = static_cast(Ptr)->getNextInBucket(); + uintptr_t x = reinterpret_cast(Probe) & ~0x1; + Ptr = reinterpret_cast(x); + } + +public: + bool operator==(const FoldingSetBucketIteratorImpl &RHS) const { + return Ptr == RHS.Ptr; + } + bool operator!=(const FoldingSetBucketIteratorImpl &RHS) const { + return Ptr != RHS.Ptr; + } +}; + + +template +class FoldingSetBucketIterator : public FoldingSetBucketIteratorImpl { +public: + FoldingSetBucketIterator(void **Bucket) : + FoldingSetBucketIteratorImpl(Bucket) {} + + FoldingSetBucketIterator(void **Bucket, bool) : + FoldingSetBucketIteratorImpl(Bucket, true) {} + + T& operator*() const { return *static_cast(Ptr); } + T* operator->() const { return static_cast(Ptr); } + + inline FoldingSetBucketIterator& operator++() { // Preincrement + advance(); + return *this; + } + FoldingSetBucketIterator operator++(int) { // Postincrement + FoldingSetBucketIterator tmp = *this; ++*this; return tmp; + } +}; + +//===----------------------------------------------------------------------===// /// FoldingSetNodeWrapper - This template class is used to "wrap" arbitrary /// types in an enclosing object so that they can be inserted into FoldingSets. template Modified: llvm/trunk/lib/Support/FoldingSet.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/FoldingSet.cpp?rev=46716&r1=46715&r2=46716&view=diff ============================================================================== --- llvm/trunk/lib/Support/FoldingSet.cpp (original) +++ llvm/trunk/lib/Support/FoldingSet.cpp Mon Feb 4 15:11:17 2008 @@ -148,7 +148,7 @@ return static_cast(NextInBucketPtr); } -/// GetBucketPtr - Provides a casting of a bucket pointer for isNode + /// testing. static void **GetBucketPtr(void *NextInBucketPtr) { intptr_t Ptr = reinterpret_cast(NextInBucketPtr); @@ -358,3 +358,9 @@ } } +//===----------------------------------------------------------------------===// +// FoldingSetBucketIteratorImpl Implementation + +FoldingSetBucketIteratorImpl::FoldingSetBucketIteratorImpl(void **Bucket) { + Ptr = (*Bucket == 0 || GetNextPtr(*Bucket) == 0) ? (void*) Bucket : *Bucket; +} From kremenek at apple.com Mon Feb 4 15:15:32 2008 From: kremenek at apple.com (Ted Kremenek) Date: Mon, 04 Feb 2008 21:15:32 -0000 Subject: [llvm-commits] [llvm] r46717 - /llvm/trunk/include/llvm/ADT/ImmutableSet.h Message-ID: <200802042115.m14LFXKR016855@zion.cs.uiuc.edu> Author: kremenek Date: Mon Feb 4 15:15:24 2008 New Revision: 46717 URL: http://llvm.org/viewvc/llvm-project?rev=46717&view=rev Log: Modified node creation of ImutAVLTree to do a hash lookup for an existing node in the FoldingSet of nodes held by the Factory object. If we we find a node with a matching hash, we do a full structural comparison. Nodes are also now inserted into the FoldingSet only when we mark them Immutable, as their children can change during intermediate-rebalancing. The 'Profile' method for ImutAVLTree is no longer used when looking up existing ImutAVLTrees with a given set of contents; instead the Profile method is used by other clients that wish to insert such a tree into a folding set. This means that we are not using FoldingSet in ImutAVLTreeFactory in the way it was intended, but instead are using it as an opaque hashtable. Modified: llvm/trunk/include/llvm/ADT/ImmutableSet.h Modified: llvm/trunk/include/llvm/ADT/ImmutableSet.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/ImmutableSet.h?rev=46717&r1=46716&r2=46717&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/ImmutableSet.h (original) +++ llvm/trunk/include/llvm/ADT/ImmutableSet.h Mon Feb 4 15:15:24 2008 @@ -25,8 +25,8 @@ //===----------------------------------------------------------------------===// template class ImutAVLFactory; - template class ImutAVLTreeInOrderIterator; +template class ImutAVLTreeGenericIterator; template class ImutAVLTree : public FoldingSetNode { @@ -38,6 +38,9 @@ typedef ImutAVLFactory Factory; friend class ImutAVLFactory; + friend class ImutAVLTreeGenericIterator; + friend class FoldingSet; + typedef ImutAVLTreeInOrderIterator iterator; //===----------------------------------------------------===// @@ -102,6 +105,24 @@ /// end - Returns an iterator for the tree that denotes the end of an /// inorder traversal. iterator end() const { return iterator(); } + + bool ElementEqual(value_type_ref V) const { + // Compare the keys. + if (!ImutInfo::isEqual(ImutInfo::KeyOfValue(getValue()), + ImutInfo::KeyOfValue(V))) + return false; + + // Also compare the data values. + if (!ImutInfo::isDataEqual(ImutInfo::DataOfValue(getValue()), + ImutInfo::DataOfValue(V))) + return false; + + return true; + } + + bool ElementEqual(const ImutAVLTree* RHS) const { + return ElementEqual(RHS->getValue()); + } /// isEqual - Compares two trees for structural equality and returns true /// if they are equal. This worst case performance of this operation is @@ -120,14 +141,7 @@ continue; } - // Compare the keys. - if (!ImutInfo::isEqual(ImutInfo::KeyOfValue(LItr->getValue()), - ImutInfo::KeyOfValue(RItr->getValue()))) - return false; - - // Also compare the data values. - if (!ImutInfo::isDataEqual(ImutInfo::DataOfValue(LItr->getValue()), - ImutInfo::DataOfValue(RItr->getValue()))) + if (!LItr->ElementEqual(*RItr)) return false; ++LItr; @@ -187,7 +201,15 @@ && "Current value is not less that value of right child."); return getHeight(); - } + } + + /// Profile - Profiling for ImutAVLTree. This is not used by the + // Factory object (which internally uses a FoldingSet), but can + // be used by external clients that wish to insert an ImutAVLTree + // object into a FoldingSet. + void Profile(llvm::FoldingSetNodeID& ID) const { + ID.AddPointer(this); + } //===----------------------------------------------------===// // Internal Values. @@ -200,70 +222,14 @@ value_type Value; unsigned Hash; - //===----------------------------------------------------===// - // Profiling or FoldingSet. - //===----------------------------------------------------===// - -private: - - static inline - unsigned ComputeHash(ImutAVLTree* L, ImutAVLTree* R, value_type_ref V) { - FoldingSetNodeID ID; - - if (L) ID.AddInteger(L->ComputeHash()); - ImutInfo::Profile(ID,V); - - // Compute the "intermediate" hash. Basically, we want the net profile to - // be: H(H(....H(H(H(item0),item1),item2)...),itemN), where - // H(item) is the hash of the data item and H(hash,item) is a hash - // of the last item hash and the the next item. - - unsigned X = ID.ComputeHash(); - - if (R) { - ID.clear(); - ID.AddInteger(X); - ID.AddInteger(R->ComputeHash()); - X = ID.ComputeHash(); - } - - return X; - } - - inline unsigned ComputeHash() { - if (Hash) return Hash; - - unsigned X = ComputeHash(getSafeLeft(), getRight(), getValue()); - if (!isMutable()) Hash = X; - - return X; - } - - /// Profile - Generates a FoldingSet profile for a tree node before it is - /// created. This is used by the ImutAVLFactory when creating - /// trees. - static inline - void Profile(FoldingSetNodeID& ID, ImutAVLTree* L, ImutAVLTree* R, - value_type_ref V) { - - ID.AddInteger(ComputeHash(L, R, V)); - } - -public: - - /// Profile - Generates a FoldingSet profile for an existing tree node. - void Profile(FoldingSetNodeID& ID) { - ID.AddInteger(ComputeHash()); - } - //===----------------------------------------------------===// // Internal methods (node manipulation; used by Factory). //===----------------------------------------------------===// - + private: enum { Mutable = 0x1 }; - + /// ImutAVLTree - Internal constructor that is only called by /// ImutAVLFactory. ImutAVLTree(ImutAVLTree* l, ImutAVLTree* r, value_type_ref v, unsigned height) @@ -330,6 +296,33 @@ assert (isMutable() && "Only a mutable tree can have its height changed."); Height = h; } + + + static inline + unsigned ComputeHash(ImutAVLTree* L, ImutAVLTree* R, value_type_ref V) { + unsigned hash = 0; + + if (L) hash += L->ComputeHash(); + + { // Compute hash of stored data. + FoldingSetNodeID ID; + ImutInfo::Profile(ID,V); + hash += ID.ComputeHash(); + } + + if (R) hash += R->ComputeHash(); + + return hash; + } + + inline unsigned ComputeHash() { + if (Hash) return Hash; + + unsigned X = ComputeHash(getSafeLeft(), getRight(), getValue()); + if (!isMutable()) Hash = X; + + return X; + } }; //===----------------------------------------------------------------------===// @@ -390,6 +383,20 @@ return ( hl > hr ? hl : hr ) + 1; } + + static bool CompareTreeWithSection(TreeTy* T, + typename TreeTy::iterator& TI, + typename TreeTy::iterator& TE) { + + typename TreeTy::iterator I = T->begin(), E = T->end(); + + for ( ; I!=E ; ++I, ++TI) + if (TI == TE || !I->ElementEqual(*TI)) + return false; + + return true; + } + //===--------------------------------------------------===// // "CreateNode" is used to generate new tree roots that link // to other trees. The functon may also simply move links @@ -401,21 +408,57 @@ //===--------------------------------------------------===// TreeTy* CreateNode(TreeTy* L, value_type_ref V, TreeTy* R) { - FoldingSetNodeID ID; - TreeTy::Profile(ID,L,R,V); - void* InsertPos; + // Search the FoldingSet bucket for a Tree with the same hash. + unsigned hash = TreeTy::ComputeHash(L, R, V); + typename CacheTy::bucket_iterator I = Cache.bucket_begin(hash); + typename CacheTy::bucket_iterator E = Cache.bucket_end(hash); - if (TreeTy* T = Cache.FindNodeOrInsertPos(ID,InsertPos)) + for (; I != E; ++I) { + TreeTy* T = &*I; + + if (T->ComputeHash() != hash) + continue; + + // We found a collision. Perform a comparison of Contents('T') + // with Contents('L')+'V'+Contents('R'). + + typename TreeTy::iterator TI = T->begin(), TE = T->end(); + + // First compare Contents('L') with the (initial) contents of T. + if (!CompareTreeWithSection(L, TI, TE)) + continue; + + // Now compare the new data element. + if (TI == TE || !TI->ElementEqual(V)) + continue; + + ++TI; + + // Now compare the remainder of 'T' with 'R'. + if (!CompareTreeWithSection(R, TI, TE)) + continue; + + if (TI != TE) // Contents('R') did not match suffix of 'T'. + continue; + + // Trees did match! Return 'T'. return T; + } - assert (InsertPos != NULL); - + // No tree with the contents: Contents('L')+'V'+Contents('R'). + // Create it. + // Allocate the new tree node and insert it into the cache. TreeTy* T = (TreeTy*) Allocator.Allocate(); new (T) TreeTy(L,R,V,IncrementHeight(L,R)); - Cache.InsertNode(T,InsertPos); - return T; + // We do not insert 'T' into the FoldingSet here. This is because + // this tree is still mutable and things may get rebalanced. + // Because our hash is associative and based on the contents of + // the set, this should hopefully not cause any strange bugs. + // 'T' is inserted by 'MarkImmutable'. + + return T; } TreeTy* CreateNode(TreeTy* L, TreeTy* OldTree, TreeTy* R) { @@ -546,6 +589,10 @@ T->MarkImmutable(); MarkImmutable(Left(T)); MarkImmutable(Right(T)); + + // Now that the node is immutable it can safely be inserted + // into the node cache. + Cache.InsertNode(T, (void*) &*Cache.bucket_end(T->ComputeHash())); } }; @@ -626,7 +673,7 @@ switch (getVisitState()) { case VisitedNone: - if (TreeTy* L = Current->getLeft()) + if (TreeTy* L = Current->getSafeLeft()) stack.push_back(reinterpret_cast(L)); else stack.back() |= VisitedLeft; From dpatel at apple.com Mon Feb 4 15:16:10 2008 From: dpatel at apple.com (Devang Patel) Date: Mon, 04 Feb 2008 21:16:10 -0000 Subject: [llvm-commits] [llvm] r46718 - /llvm/trunk/tools/lto/lto.cpp Message-ID: <200802042116.m14LGBXR016885@zion.cs.uiuc.edu> Author: dpatel Date: Mon Feb 4 15:16:10 2008 New Revision: 46718 URL: http://llvm.org/viewvc/llvm-project?rev=46718&view=rev Log: Do not set time out, lets assume assembler will do its job in reasonable amount of time. Modified: llvm/trunk/tools/lto/lto.cpp Modified: llvm/trunk/tools/lto/lto.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/lto.cpp?rev=46718&r1=46717&r2=46718&view=diff ============================================================================== --- llvm/trunk/tools/lto/lto.cpp (original) +++ llvm/trunk/tools/lto/lto.cpp Mon Feb 4 15:16:10 2008 @@ -516,7 +516,7 @@ args.push_back(tmpAsmFilePath.c_str()); args.push_back(0); - if (sys::Program::ExecuteAndWait(gcc, &args[0], 0, 0, 1, 0, &ErrMsg)) { + if (sys::Program::ExecuteAndWait(gcc, &args[0], 0, 0, 0, 0, &ErrMsg)) { cerr << "lto: " << ErrMsg << "\n"; return LTO_ASM_FAILURE; } From kremenek at apple.com Mon Feb 4 15:17:05 2008 From: kremenek at apple.com (Ted Kremenek) Date: Mon, 04 Feb 2008 21:17:05 -0000 Subject: [llvm-commits] [llvm] r46719 - /llvm/trunk/include/llvm/ADT/ImmutableMap.h Message-ID: <200802042117.m14LH64J016988@zion.cs.uiuc.edu> Author: kremenek Date: Mon Feb 4 15:17:02 2008 New Revision: 46719 URL: http://llvm.org/viewvc/llvm-project?rev=46719&view=rev Log: Modified 'Profile' method of ImmutableMap to use the 'Profile' method of the contained ImutAVLTree root. Modified: llvm/trunk/include/llvm/ADT/ImmutableMap.h Modified: llvm/trunk/include/llvm/ADT/ImmutableMap.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/ImmutableMap.h?rev=46719&r1=46718&r2=46719&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/ImmutableMap.h (original) +++ llvm/trunk/include/llvm/ADT/ImmutableMap.h Mon Feb 4 15:17:02 2008 @@ -205,8 +205,8 @@ inline unsigned getHeight() const { return Root ? Root->getHeight() : 0; } - static inline void Profile(FoldingSetNodeID& ID, const ImmutableMap& M) { - ID.AddPointer(M.Root); + static inline void Profile(FoldingSetNodeID& ID, const ImmutableMap& M) { + M.Root->Profile(ID); } inline void Profile(FoldingSetNodeID& ID) const { From natebegeman at mac.com Mon Feb 4 15:44:13 2008 From: natebegeman at mac.com (Nate Begeman) Date: Mon, 04 Feb 2008 21:44:13 -0000 Subject: [llvm-commits] [llvm] r46720 - /llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Message-ID: <200802042144.m14LiFMI017965@zion.cs.uiuc.edu> Author: sampo Date: Mon Feb 4 15:44:06 2008 New Revision: 46720 URL: http://llvm.org/viewvc/llvm-project?rev=46720&view=rev Log: Eliminate some redundant code. Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=46720&r1=46719&r2=46720&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Mon Feb 4 15:44:06 2008 @@ -203,7 +203,7 @@ setOperationAction(ISD::MEMMOVE , MVT::Other, Expand); // Use the default implementation. - setOperationAction(ISD::VASTART , MVT::Other, Expand); + setOperationAction(ISD::VASTART , MVT::Other, Custom); setOperationAction(ISD::VAARG , MVT::Other, Expand); setOperationAction(ISD::VACOPY , MVT::Other, Expand); setOperationAction(ISD::VAEND , MVT::Other, Expand); @@ -240,12 +240,6 @@ setOperationAction(ISD::BR_CC , MVT::f64, Custom); setOperationAction(ISD::BR_JT , MVT::Other, Custom); - setOperationAction(ISD::VASTART, MVT::Other, Custom); - setOperationAction(ISD::VACOPY, MVT::Other, Expand); - setOperationAction(ISD::VAEND, MVT::Other, Expand); - setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); - setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); - // FP Constants can't be immediates. setOperationAction(ISD::ConstantFP, MVT::f64, Expand); setOperationAction(ISD::ConstantFP, MVT::f32, Expand); From dpatel at apple.com Mon Feb 4 15:50:23 2008 From: dpatel at apple.com (Devang Patel) Date: Mon, 4 Feb 2008 13:50:23 -0800 Subject: [llvm-commits] [llvm-gcc-4.2] r46670 - in /llvm-gcc-4.2/trunk/gcc: llvm-backend.cpp llvm-convert.cpp In-Reply-To: <200802022023.m12KNSV7027714@zion.cs.uiuc.edu> References: <200802022023.m12KNSV7027714@zion.cs.uiuc.edu> Message-ID: <1AB86B5D-BCA8-43D5-8A03-BC96537D82DE@apple.com> Please update associated comments also. Thanks! - Devang On Feb 2, 2008, at 12:23 PM, Duncan Sands wrote: > Author: baldrick > Date: Sat Feb 2 14:23:27 2008 > New Revision: 46670 > > URL: http://llvm.org/viewvc/llvm-project?rev=46670&view=rev > Log: > Use alignment zero if the gcc alignment is less > than the ABI alignment, not just when it is equal > to it. > > Modified: > llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp > llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp > > Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=46670&r1=46669&r2=46670&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original) > +++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Sat Feb 2 14:23:27 2008 > @@ -969,7 +969,7 @@ > unsigned TargetAlign = > getTargetData().getABITypeAlignment(GV->getType()- > >getElementType()); > if (DECL_USER_ALIGN(decl) || > - TargetAlign != (unsigned)DECL_ALIGN_UNIT(decl)) > + TargetAlign < (unsigned)DECL_ALIGN_UNIT(decl)) > GV->setAlignment(DECL_ALIGN_UNIT(decl)); > } > > > Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=46670&r1=46669&r2=46670&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) > +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Sat Feb 2 14:23:27 2008 > @@ -1589,7 +1589,7 @@ > // 2) DECL_ALIGN is set by user. > if (DECL_ALIGN_UNIT(decl)) { > unsigned TargetAlign = getTargetData().getABITypeAlignment(Ty); > - if (DECL_USER_ALIGN(decl) || TargetAlign != > (unsigned)DECL_ALIGN_UNIT(decl)) > + if (DECL_USER_ALIGN(decl) || TargetAlign < > (unsigned)DECL_ALIGN_UNIT(decl)) > Alignment = DECL_ALIGN_UNIT(decl); > } > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits - Devang From natebegeman at mac.com Mon Feb 4 17:04:38 2008 From: natebegeman at mac.com (Nate Begeman) Date: Mon, 04 Feb 2008 23:04:38 -0000 Subject: [llvm-commits] [llvm] r46723 - /llvm/trunk/lib/Target/ARM/ARMISelLowering.h Message-ID: <200802042304.m14N4gtm020320@zion.cs.uiuc.edu> Author: sampo Date: Mon Feb 4 17:04:24 2008 New Revision: 46723 URL: http://llvm.org/viewvc/llvm-project?rev=46723&view=rev Log: This method should be virtual Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=46723&r1=46722&r2=46723&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Mon Feb 4 17:04:24 2008 @@ -78,7 +78,7 @@ virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); virtual SDNode *ExpandOperationResult(SDNode *N, SelectionDAG &DAG); - SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; + virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; virtual const char *getTargetNodeName(unsigned Opcode) const; From evan.cheng at apple.com Mon Feb 4 17:06:58 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 04 Feb 2008 23:06:58 -0000 Subject: [llvm-commits] [llvm] r46724 - in /llvm/trunk: lib/CodeGen/AsmPrinter.cpp lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/Alpha/AlphaISelDAGToDAG.cpp lib/Target/CellSPU/SPUISelDAGToDAG.cpp lib/Target/IA64/IA64ISelDAGToDAG.cpp lib/Target/Mips/MipsISelDAGToDAG.cpp lib/Target/PowerPC/PPCISelDAGToDAG.cpp lib/Target/Sparc/SparcISelDAGToDAG.cpp lib/Target/X86/X86ISelDAGToDAG.cpp utils/TableGen/DAGISelEmitter.cpp Message-ID: <200802042307.m14N71uV020412@zion.cs.uiuc.edu> Author: evancheng Date: Mon Feb 4 17:06:48 2008 New Revision: 46724 URL: http://llvm.org/viewvc/llvm-project?rev=46724&view=rev Log: Dwarf requires variable entries to be in the source order. Right now, since we are recording variable information at isel time this means parameters would appear in the reverse order. The short term fix is to issue recordVariable() at asm printing time instead. Modified: llvm/trunk/lib/CodeGen/AsmPrinter.cpp llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp llvm/trunk/lib/Target/IA64/IA64ISelDAGToDAG.cpp llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter.cpp?rev=46724&r1=46723&r2=46724&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter.cpp Mon Feb 4 17:06:48 2008 @@ -118,9 +118,8 @@ SwitchToDataSection(""); // Reset back to no section. - if (MachineModuleInfo *MMI = getAnalysisToUpdate()) { - MMI->AnalyzeModule(M); - } + MMI = getAnalysisToUpdate(); + if (MMI) MMI->AnalyzeModule(M); return false; } @@ -1291,8 +1290,12 @@ /// printDeclare - This method prints a local variable declaration used by /// debug tables. +/// FIXME: It doesn't really print anything rather it inserts a DebugVariable +/// entry into dwarf table. void AsmPrinter::printDeclare(const MachineInstr *MI) const { - // Do nothing. + int FI = MI->getOperand(0).getIndex(); + GlobalValue *GV = MI->getOperand(1).getGlobal(); + MMI->RecordVariable(GV, FI); } /// PrintAsmOperand - Print the specified operand of MI, an INLINEASM Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=46724&r1=46723&r2=46724&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Mon Feb 4 17:06:48 2008 @@ -23,7 +23,6 @@ #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" -#include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/SelectionDAGISel.h" #include "llvm/Target/TargetLowering.h" Modified: llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp?rev=46724&r1=46723&r2=46724&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp Mon Feb 4 17:06:48 2008 @@ -18,7 +18,6 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/SelectionDAGISel.h" Modified: llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp?rev=46724&r1=46723&r2=46724&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp Mon Feb 4 17:06:48 2008 @@ -20,7 +20,6 @@ #include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/SelectionDAGISel.h" #include "llvm/Target/TargetOptions.h" Modified: llvm/trunk/lib/Target/IA64/IA64ISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64ISelDAGToDAG.cpp?rev=46724&r1=46723&r2=46724&view=diff ============================================================================== --- llvm/trunk/lib/Target/IA64/IA64ISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/IA64/IA64ISelDAGToDAG.cpp Mon Feb 4 17:06:48 2008 @@ -18,7 +18,6 @@ #include "IA64ISelLowering.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/SelectionDAGISel.h" #include "llvm/Target/TargetOptions.h" Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=46724&r1=46723&r2=46724&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Mon Feb 4 17:06:48 2008 @@ -27,7 +27,6 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineInstrBuilder.h" -#include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/SelectionDAGISel.h" #include "llvm/Target/TargetMachine.h" Modified: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=46724&r1=46723&r2=46724&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Mon Feb 4 17:06:48 2008 @@ -20,7 +20,6 @@ #include "PPCHazardRecognizers.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/SelectionDAGISel.h" Modified: llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp?rev=46724&r1=46723&r2=46724&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp Mon Feb 4 17:06:48 2008 @@ -19,7 +19,6 @@ #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" -#include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/SelectionDAGISel.h" Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=46724&r1=46723&r2=46724&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Mon Feb 4 17:06:48 2008 @@ -29,7 +29,6 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineInstrBuilder.h" -#include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/SelectionDAGISel.h" #include "llvm/Target/TargetMachine.h" Modified: llvm/trunk/utils/TableGen/DAGISelEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelEmitter.cpp?rev=46724&r1=46723&r2=46724&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/DAGISelEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Mon Feb 4 17:06:48 2008 @@ -1780,7 +1780,6 @@ << "}\n\n"; OS << "SDNode *Select_DECLARE(const SDOperand &N) {\n" - << " MachineModuleInfo *MMI = CurDAG->getMachineModuleInfo();\n" << " SDOperand Chain = N.getOperand(0);\n" << " SDOperand N1 = N.getOperand(1);\n" << " SDOperand N2 = N.getOperand(2);\n" @@ -1791,8 +1790,6 @@ << " }\n" << " int FI = cast(N1)->getIndex();\n" << " GlobalValue *GV = cast(N2)->getGlobal();\n" - << " // FIXME. Handle variable declarations later since it lives on.\n" - << " MMI->RecordVariable(GV, FI);\n" << " SDOperand Tmp1 = " << "CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());\n" << " SDOperand Tmp2 = " From evan.cheng at apple.com Mon Feb 4 17:10:38 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 04 Feb 2008 23:10:38 -0000 Subject: [llvm-commits] [llvm] r46725 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAGNodes.h lib/CodeGen/SelectionDAG/SelectionDAG.cpp Message-ID: <200802042310.m14NAcIO020582@zion.cs.uiuc.edu> Author: evancheng Date: Mon Feb 4 17:10:38 2008 New Revision: 46725 URL: http://llvm.org/viewvc/llvm-project?rev=46725&view=rev Log: Typo. Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=46725&r1=46724&r2=46725&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Mon Feb 4 17:10:38 2008 @@ -598,7 +598,7 @@ bool isBuildVectorAllZeros(const SDNode *N); /// isDebugLabel - Return true if the specified node represents a debug - /// label (i.e. ISD::LABEL or TargetInstrInfo::LANEL node and third operand + /// label (i.e. ISD::LABEL or TargetInstrInfo::LABEL node and third operand /// is 0). bool isDebugLabel(const SDNode *N); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=46725&r1=46724&r2=46725&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Mon Feb 4 17:10:38 2008 @@ -176,7 +176,7 @@ } /// isDebugLabel - Return true if the specified node represents a debug -/// label (i.e. ISD::LABEL or TargetInstrInfo::LANEL node and third operand +/// label (i.e. ISD::LABEL or TargetInstrInfo::LABEL node and third operand /// is 0). bool ISD::isDebugLabel(const SDNode *N) { SDOperand Zero; From dpatel at apple.com Mon Feb 4 17:24:44 2008 From: dpatel at apple.com (Devang Patel) Date: Mon, 04 Feb 2008 23:24:44 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r46726 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Message-ID: <200802042324.m14NOiBg021071@zion.cs.uiuc.edu> Author: dpatel Date: Mon Feb 4 17:24:43 2008 New Revision: 46726 URL: http://llvm.org/viewvc/llvm-project?rev=46726&view=rev Log: Use appropriate alignment while handling packed struct member. Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=46726&r1=46725&r2=46726&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Mon Feb 4 17:24:43 2008 @@ -2148,6 +2148,13 @@ bool isVolatile = TREE_THIS_VOLATILE(exp); const Type *Ty = ConvertType(TREE_TYPE(exp)); unsigned Alignment = expr_align(exp) / 8; + if (TREE_CODE(exp) == COMPONENT_REF) + if (const StructType *STy = + dyn_cast(ConvertType(TREE_TYPE(TREE_OPERAND(exp, 0))))) + if (STy->isPacked()) + // Packed struct members use 1 byte alignment + Alignment = 1; + if (!LV.isBitfield()) { if (!DestLoc) { @@ -2680,6 +2687,12 @@ LValue LV = EmitLV(lhs); bool isVolatile = TREE_THIS_VOLATILE(lhs); unsigned Alignment = expr_align(lhs) / 8; + if (TREE_CODE(lhs) == COMPONENT_REF) + if (const StructType *STy = + dyn_cast(ConvertType(TREE_TYPE(TREE_OPERAND(lhs, 0))))) + if (STy->isPacked()) + // Packed struct members use 1 byte alignment + Alignment = 1; if (!LV.isBitfield()) { const Type *ValTy = ConvertType(TREE_TYPE(rhs)); From dalej at apple.com Mon Feb 4 17:27:29 2008 From: dalej at apple.com (Dale Johannesen) Date: Mon, 04 Feb 2008 23:27:29 -0000 Subject: [llvm-commits] [llvm] r46727 - /llvm/trunk/include/llvm/IntrinsicsX86.td Message-ID: <200802042327.m14NRT7G021211@zion.cs.uiuc.edu> Author: johannes Date: Mon Feb 4 17:27:29 2008 New Revision: 46727 URL: http://llvm.org/viewvc/llvm-project?rev=46727&view=rev Log: Do not unconditionally redefine vec_ext_v16qi and vec_ext_v4si builtins. This is a hack; they should be defined here, then resolved in the X86 BE. However there is enough other stuff missing in the X86 BE for SSE41 that this will do for now. Modified: llvm/trunk/include/llvm/IntrinsicsX86.td Modified: llvm/trunk/include/llvm/IntrinsicsX86.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsX86.td?rev=46727&r1=46726&r2=46727&view=diff ============================================================================== --- llvm/trunk/include/llvm/IntrinsicsX86.td (original) +++ llvm/trunk/include/llvm/IntrinsicsX86.td Mon Feb 4 17:27:29 2008 @@ -764,9 +764,9 @@ // Vector extract let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". - def int_x86_sse41_pextrb : GCCBuiltin<"__builtin_ia32_vec_ext_v16qi">, + def int_x86_sse41_pextrb : Intrinsic<[llvm_i32_ty, llvm_v16i8_ty, llvm_i32_ty]>; - def int_x86_sse41_pextrd : GCCBuiltin<"__builtin_ia32_vec_ext_v4si">, + def int_x86_sse41_pextrd : Intrinsic<[llvm_i32_ty, llvm_v4i32_ty, llvm_i32_ty]>; def int_x86_sse41_pextrq : GCCBuiltin<"__builtin_ia32_vec_ext_v2di">, Intrinsic<[llvm_i64_ty, llvm_v2i64_ty, llvm_i32_ty]>; From baldrick at free.fr Mon Feb 4 18:06:31 2008 From: baldrick at free.fr (Duncan Sands) Date: Tue, 05 Feb 2008 00:06:31 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r46728 - in /llvm-gcc-4.2/trunk/gcc: llvm-backend.cpp llvm-convert.cpp Message-ID: <200802050006.m1506VKv022472@zion.cs.uiuc.edu> Author: baldrick Date: Mon Feb 4 18:06:31 2008 New Revision: 46728 URL: http://llvm.org/viewvc/llvm-project?rev=46728&view=rev Log: Update comments. Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=46728&r1=46727&r2=46728&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Mon Feb 4 18:06:31 2008 @@ -963,7 +963,7 @@ } // Set the alignment for the global if one of the following condition is met - // 1) DECL_ALIGN_UNIT does not match alignment as per ABI specification + // 1) DECL_ALIGN_UNIT is better than the alignment as per ABI specification // 2) DECL_ALIGN is set by user. if (DECL_ALIGN_UNIT(decl)) { unsigned TargetAlign = Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=46728&r1=46727&r2=46728&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Mon Feb 4 18:06:31 2008 @@ -1583,7 +1583,7 @@ unsigned Alignment = 0; // Alignment in bytes. // Set the alignment for the local if one of the following condition is met - // 1) DECL_ALIGN_UNIT does not match alignment as per ABI specification + // 1) DECL_ALIGN_UNIT is better than the alignment as per ABI specification // 2) DECL_ALIGN is set by user. if (DECL_ALIGN_UNIT(decl)) { unsigned TargetAlign = getTargetData().getABITypeAlignment(Ty); From baldrick at free.fr Mon Feb 4 18:06:49 2008 From: baldrick at free.fr (Duncan Sands) Date: Tue, 5 Feb 2008 01:06:49 +0100 Subject: [llvm-commits] [llvm-gcc-4.2] r46670 - in /llvm-gcc-4.2/trunk/gcc: llvm-backend.cpp llvm-convert.cpp In-Reply-To: <1AB86B5D-BCA8-43D5-8A03-BC96537D82DE@apple.com> References: <200802022023.m12KNSV7027714@zion.cs.uiuc.edu> <1AB86B5D-BCA8-43D5-8A03-BC96537D82DE@apple.com> Message-ID: <200802050106.50268.baldrick@free.fr> On Monday 4 February 2008 22:50:23 Devang Patel wrote: > Please update associated comments also. Sorry about that - done now. Ciao, Duncan. From evan.cheng at apple.com Mon Feb 4 18:25:13 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 05 Feb 2008 00:25:13 -0000 Subject: [llvm-commits] [llvm] r46729 - /llvm/trunk/include/llvm/CodeGen/AsmPrinter.h Message-ID: <200802050025.m150PD4n022977@zion.cs.uiuc.edu> Author: evancheng Date: Mon Feb 4 18:25:13 2008 New Revision: 46729 URL: http://llvm.org/viewvc/llvm-project?rev=46729&view=rev Log: Unbreak teh build. Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/AsmPrinter.h?rev=46729&r1=46728&r2=46729&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/AsmPrinter.h (original) +++ llvm/trunk/include/llvm/CodeGen/AsmPrinter.h Mon Feb 4 18:25:13 2008 @@ -27,6 +27,7 @@ class GlobalAlias; class MachineConstantPoolEntry; class MachineConstantPoolValue; + class MachineModuleInfo; class Mangler; class TargetAsmInfo; class Type; @@ -43,6 +44,11 @@ /// unsigned FunctionNumber; + /// MachineModuleInfo - This is needed because printDeclare() has to insert + /// DebugVariable entries into the dwarf table. This is a short term hack + /// that ought be fixed soon. + MachineModuleInfo *MMI; + protected: // Necessary for external weak linkage support std::set ExtWeakSymbols; From evan.cheng at apple.com Mon Feb 4 18:25:31 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 05 Feb 2008 00:25:31 -0000 Subject: [llvm-commits] [llvm] r46730 - /llvm/trunk/test/C++Frontend/2006-11-06-StackTrace.cpp Message-ID: <200802050025.m150PVXZ022997@zion.cs.uiuc.edu> Author: evancheng Date: Mon Feb 4 18:25:31 2008 New Revision: 46730 URL: http://llvm.org/viewvc/llvm-project?rev=46730&view=rev Log: This should also work on x86 now. Modified: llvm/trunk/test/C++Frontend/2006-11-06-StackTrace.cpp Modified: llvm/trunk/test/C++Frontend/2006-11-06-StackTrace.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/C%2B%2BFrontend/2006-11-06-StackTrace.cpp?rev=46730&r1=46729&r2=46730&view=diff ============================================================================== --- llvm/trunk/test/C++Frontend/2006-11-06-StackTrace.cpp (original) +++ llvm/trunk/test/C++Frontend/2006-11-06-StackTrace.cpp Mon Feb 4 18:25:31 2008 @@ -9,8 +9,8 @@ // RUN: gdb -q -batch -n -x %t.in %t.exe | \ // RUN: grep {#7 0x.* in main.*(argc=\[12\],.*argv=.*)} -// Only works on ppc. Should generalize? -// XFAIL: i[1-9]86|alpha|ia64|arm|x86_64|amd64 +// Only works on ppc and x86. Should generalize? +// XFAIL: alpha|ia64|arm|x86_64|amd64 #include From dalej at apple.com Mon Feb 4 19:12:10 2008 From: dalej at apple.com (Dale Johannesen) Date: Tue, 05 Feb 2008 01:12:10 -0000 Subject: [llvm-commits] [llvm] r46733 - /llvm/trunk/include/llvm/IntrinsicsX86.td Message-ID: <200802050112.m151CBfH015222@zion.cs.uiuc.edu> Author: johannes Date: Mon Feb 4 19:12:10 2008 New Revision: 46733 URL: http://llvm.org/viewvc/llvm-project?rev=46733&view=rev Log: Missed one. Modified: llvm/trunk/include/llvm/IntrinsicsX86.td Modified: llvm/trunk/include/llvm/IntrinsicsX86.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsX86.td?rev=46733&r1=46732&r2=46733&view=diff ============================================================================== --- llvm/trunk/include/llvm/IntrinsicsX86.td (original) +++ llvm/trunk/include/llvm/IntrinsicsX86.td Mon Feb 4 19:12:10 2008 @@ -764,11 +764,11 @@ // Vector extract let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". - def int_x86_sse41_pextrb : + def int_x86_sse41_pextrb : Intrinsic<[llvm_i32_ty, llvm_v16i8_ty, llvm_i32_ty]>; - def int_x86_sse41_pextrd : + def int_x86_sse41_pextrd : Intrinsic<[llvm_i32_ty, llvm_v4i32_ty, llvm_i32_ty]>; - def int_x86_sse41_pextrq : GCCBuiltin<"__builtin_ia32_vec_ext_v2di">, + def int_x86_sse41_pextrq : Intrinsic<[llvm_i64_ty, llvm_v2i64_ty, llvm_i32_ty]>; def int_x86_sse41_extractps : GCCBuiltin<"__builtin_ia32_extractps128">, Intrinsic<[llvm_i32_ty, llvm_v4f32_ty, llvm_i32_ty]>; From resistor at mac.com Mon Feb 4 22:34:04 2008 From: resistor at mac.com (Owen Anderson) Date: Tue, 05 Feb 2008 04:34:04 -0000 Subject: [llvm-commits] [llvm] r46738 - /llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Message-ID: <200802050434.m154Y4xN005797@zion.cs.uiuc.edu> Author: resistor Date: Mon Feb 4 22:34:03 2008 New Revision: 46738 URL: http://llvm.org/viewvc/llvm-project?rev=46738&view=rev Log: Fix an obscure read-after-free bug that Duncan found. Modified: llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Modified: llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp?rev=46738&r1=46737&r2=46738&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Mon Feb 4 22:34:03 2008 @@ -463,15 +463,17 @@ reverseDep[depGraphLocal[rem].first].erase(rem); if (depGraphEntry->second.first != NonLocal && + depGraphEntry->second.first != None && depGraphEntry->second.second) { // If we have dep info for rem, set them to it BasicBlock::iterator RI = depGraphEntry->second.first; RI++; newDep = RI; - } else if (depGraphEntry->second.first == NonLocal && + } else if ( (depGraphEntry->second.first == NonLocal || + depGraphEntry->second.first == None ) && depGraphEntry->second.second ) { // If we have a confirmed non-local flag, use it - newDep = NonLocal; + newDep = depGraphEntry->second.first; } else { // Otherwise, use the immediate successor of rem // NOTE: This is because, when getDependence is called, it will first @@ -480,14 +482,22 @@ RI++; newDep = RI; } - - SmallPtrSet& set = reverseDep[rem]; - for (SmallPtrSet::iterator I = set.begin(), E = set.end(); - I != E; ++I) { - // Insert the new dependencies - // Mark it as unconfirmed as long as it is not the non-local flag - depGraphLocal[*I] = std::make_pair(newDep, !newDep); - } + } else { + // Otherwise, use the immediate successor of rem + // NOTE: This is because, when getDependence is called, it will first + // check the immediate predecessor of what is in the cache. + BasicBlock::iterator RI = rem; + RI++; + newDep = RI; + } + + SmallPtrSet& set = reverseDep[rem]; + for (SmallPtrSet::iterator I = set.begin(), E = set.end(); + I != E; ++I) { + // Insert the new dependencies + // Mark it as unconfirmed as long as it is not the non-local flag + depGraphLocal[*I] = std::make_pair(newDep, (newDep == NonLocal || + newDep == None)); } depGraphLocal.erase(rem); From sabre at nondot.org Mon Feb 4 22:45:35 2008 From: sabre at nondot.org (Chris Lattner) Date: Tue, 05 Feb 2008 04:45:35 -0000 Subject: [llvm-commits] [llvm] r46739 - in /llvm/trunk: lib/Transforms/Scalar/InstructionCombining.cpp test/Transforms/InstCombine/2008-02-04-GEPIdxBug.ll Message-ID: <200802050445.m154jaYY006291@zion.cs.uiuc.edu> Author: lattner Date: Mon Feb 4 22:45:32 2008 New Revision: 46739 URL: http://llvm.org/viewvc/llvm-project?rev=46739&view=rev Log: Fix a bug compiling PR1978 (perhaps not the only one though) which was incorrectly simplifying "x == (gep x, 1, i)" into false, even though i could be negative. As it turns out, all the code to handle this already existed, we just need to disable the incorrect optimization case and let the general case handle it. Added: llvm/trunk/test/Transforms/InstCombine/2008-02-04-GEPIdxBug.ll Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp?rev=46739&r1=46738&r2=46739&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Mon Feb 4 22:45:32 2008 @@ -4629,60 +4629,11 @@ Value *PtrBase = GEPLHS->getOperand(0); if (PtrBase == RHS) { - // As an optimization, we don't actually have to compute the actual value of - // OFFSET if this is a icmp_eq or icmp_ne comparison, just return whether - // each index is zero or not. - if (Cond == ICmpInst::ICMP_EQ || Cond == ICmpInst::ICMP_NE) { - Instruction *InVal = 0; - gep_type_iterator GTI = gep_type_begin(GEPLHS); - for (unsigned i = 1, e = GEPLHS->getNumOperands(); i != e; ++i, ++GTI) { - bool EmitIt = true; - if (Constant *C = dyn_cast(GEPLHS->getOperand(i))) { - if (isa(C)) // undef index -> undef. - return ReplaceInstUsesWith(I, UndefValue::get(I.getType())); - if (C->isNullValue()) - EmitIt = false; - else if (TD->getABITypeSize(GTI.getIndexedType()) == 0) { - EmitIt = false; // This is indexing into a zero sized array? - } else if (isa(C)) - return ReplaceInstUsesWith(I, // No comparison is needed here. - ConstantInt::get(Type::Int1Ty, - Cond == ICmpInst::ICMP_NE)); - } - - if (EmitIt) { - Instruction *Comp = - new ICmpInst(Cond, GEPLHS->getOperand(i), - Constant::getNullValue(GEPLHS->getOperand(i)->getType())); - if (InVal == 0) - InVal = Comp; - else { - InVal = InsertNewInstBefore(InVal, I); - InsertNewInstBefore(Comp, I); - if (Cond == ICmpInst::ICMP_NE) // True if any are unequal - InVal = BinaryOperator::createOr(InVal, Comp); - else // True if all are equal - InVal = BinaryOperator::createAnd(InVal, Comp); - } - } - } - - if (InVal) - return InVal; - else - // No comparison is needed here, all indexes = 0 - ReplaceInstUsesWith(I, ConstantInt::get(Type::Int1Ty, - Cond == ICmpInst::ICMP_EQ)); - } - - // Only lower this if the icmp is the only user of the GEP or if we expect - // the result to fold to a constant! - if (isa(GEPLHS) || GEPLHS->hasOneUse()) { - // ((gep Ptr, OFFSET) cmp Ptr) ---> (OFFSET cmp 0). - Value *Offset = EmitGEPOffset(GEPLHS, I, *this); - return new ICmpInst(ICmpInst::getSignedPredicate(Cond), Offset, - Constant::getNullValue(Offset->getType())); - } + // ((gep Ptr, OFFSET) cmp Ptr) ---> (OFFSET cmp 0). + // This transformation is valid because we know pointers can't overflow. + Value *Offset = EmitGEPOffset(GEPLHS, I, *this); + return new ICmpInst(ICmpInst::getSignedPredicate(Cond), Offset, + Constant::getNullValue(Offset->getType())); } else if (User *GEPRHS = dyn_castGetElementPtr(RHS)) { // If the base pointers are different, but the indices are the same, just // compare the base pointer. Added: llvm/trunk/test/Transforms/InstCombine/2008-02-04-GEPIdxBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/2008-02-04-GEPIdxBug.ll?rev=46739&view=auto ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/2008-02-04-GEPIdxBug.ll (added) +++ llvm/trunk/test/Transforms/InstCombine/2008-02-04-GEPIdxBug.ll Mon Feb 4 22:45:32 2008 @@ -0,0 +1,33 @@ +; RUN: llvm-as < %s | opt -instcombine | llvm-dis | grep {icmp eq i32 %indvar, 0} +; PR1978 +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" +target triple = "i686-apple-darwin8" + %struct.x = type <{ i8 }> + at .str = internal constant [6 x i8] c"Main!\00" ; <[6 x i8]*> [#uses=1] + at .str1 = internal constant [12 x i8] c"destroy %p\0A\00" ; <[12 x i8]*> [#uses=1] + +define i32 @main() nounwind { +entry: + %orientations = alloca [1 x [1 x %struct.x]] ; <[1 x [1 x %struct.x]]*> [#uses=2] + %tmp3 = call i32 @puts( i8* getelementptr ([6 x i8]* @.str, i32 0, i32 0) ) nounwind ; [#uses=0] + %tmp45 = getelementptr [1 x [1 x %struct.x]]* %orientations, i32 1, i32 0, i32 0 ; <%struct.x*> [#uses=1] + %orientations62 = getelementptr [1 x [1 x %struct.x]]* %orientations, i32 0, i32 0, i32 0 ; <%struct.x*> [#uses=1] + br label %bb10 + +bb10: ; preds = %bb10, %entry + %indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb10 ] ; [#uses=2] + %tmp.0.reg2mem.0.rec = mul i32 %indvar, -1 ; [#uses=1] + %tmp12.rec = add i32 %tmp.0.reg2mem.0.rec, -1 ; [#uses=1] + %tmp12 = getelementptr %struct.x* %tmp45, i32 %tmp12.rec ; <%struct.x*> [#uses=2] + %tmp16 = call i32 (i8*, ...)* @printf( i8* getelementptr ([12 x i8]* @.str1, i32 0, i32 0), %struct.x* %tmp12 ) nounwind ; [#uses=0] + %tmp84 = icmp eq %struct.x* %tmp12, %orientations62 ; [#uses=1] + %indvar.next = add i32 %indvar, 1 ; [#uses=1] + br i1 %tmp84, label %bb17, label %bb10 + +bb17: ; preds = %bb10 + ret i32 0 +} + +declare i32 @puts(i8*) + +declare i32 @printf(i8*, ...) From clattner at apple.com Mon Feb 4 23:07:08 2008 From: clattner at apple.com (Chris Lattner) Date: Mon, 4 Feb 2008 21:07:08 -0800 Subject: [llvm-commits] [llvm] r46727 - /llvm/trunk/include/llvm/IntrinsicsX86.td In-Reply-To: <200802042327.m14NRT7G021211@zion.cs.uiuc.edu> References: <200802042327.m14NRT7G021211@zion.cs.uiuc.edu> Message-ID: <9642BC09-56CD-4C7C-9294-0E5EA9D99F3E@apple.com> On Feb 4, 2008, at 3:27 PM, Dale Johannesen wrote: > Author: johannes > Date: Mon Feb 4 17:27:29 2008 > New Revision: 46727 > > URL: http://llvm.org/viewvc/llvm-project?rev=46727&view=rev > Log: > Do not unconditionally redefine vec_ext_v16qi and > vec_ext_v4si builtins. This is a hack; they should > be defined here, then resolved in the X86 BE. > However there is enough other stuff missing in the > X86 BE for SSE41 that this will do for now. I think these are in the category of builtins that should be expanded by the FE, and thus should be removed. Nate, thoughts? -Chris > > > Modified: > llvm/trunk/include/llvm/IntrinsicsX86.td > > Modified: llvm/trunk/include/llvm/IntrinsicsX86.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsX86.td?rev=46727&r1=46726&r2=46727&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/include/llvm/IntrinsicsX86.td (original) > +++ llvm/trunk/include/llvm/IntrinsicsX86.td Mon Feb 4 17:27:29 2008 > @@ -764,9 +764,9 @@ > > // Vector extract > let TargetPrefix = "x86" in { // All intrinsics start with > "llvm.x86.". > - def int_x86_sse41_pextrb : > GCCBuiltin<"__builtin_ia32_vec_ext_v16qi">, > + def int_x86_sse41_pextrb : > Intrinsic<[llvm_i32_ty, llvm_v16i8_ty, llvm_i32_ty]>; > - def int_x86_sse41_pextrd : > GCCBuiltin<"__builtin_ia32_vec_ext_v4si">, > + def int_x86_sse41_pextrd : > Intrinsic<[llvm_i32_ty, llvm_v4i32_ty, llvm_i32_ty]>; > def int_x86_sse41_pextrq : > GCCBuiltin<"__builtin_ia32_vec_ext_v2di">, > Intrinsic<[llvm_i64_ty, llvm_v2i64_ty, llvm_i32_ty]>; > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From sabre at nondot.org Tue Feb 5 00:18:42 2008 From: sabre at nondot.org (Chris Lattner) Date: Tue, 05 Feb 2008 06:18:42 -0000 Subject: [llvm-commits] [llvm] r46741 - in /llvm/trunk/docs/tutorial: LangImpl4.html LangImpl5.html LangImpl6.html LangImpl7.html Message-ID: <200802050618.m156IgGf009108@zion.cs.uiuc.edu> Author: lattner Date: Tue Feb 5 00:18:42 2008 New Revision: 46741 URL: http://llvm.org/viewvc/llvm-project?rev=46741&view=rev Log: dump the module *before* we delete it, not after. Modified: llvm/trunk/docs/tutorial/LangImpl4.html llvm/trunk/docs/tutorial/LangImpl5.html llvm/trunk/docs/tutorial/LangImpl6.html llvm/trunk/docs/tutorial/LangImpl7.html Modified: llvm/trunk/docs/tutorial/LangImpl4.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/tutorial/LangImpl4.html?rev=46741&r1=46740&r2=46741&view=diff ============================================================================== --- llvm/trunk/docs/tutorial/LangImpl4.html (original) +++ llvm/trunk/docs/tutorial/LangImpl4.html Tue Feb 5 00:18:42 2008 @@ -1109,11 +1109,11 @@ MainLoop(); TheFPM = 0; - } // Free module provider and pass manager. - + + // Print out all of the generated code. + TheModule->dump(); + } // Free module provider (and thus the module) and pass manager. - // Print out all of the generated code. - TheModule->dump(); return 0; } Modified: llvm/trunk/docs/tutorial/LangImpl5.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/tutorial/LangImpl5.html?rev=46741&r1=46740&r2=46741&view=diff ============================================================================== --- llvm/trunk/docs/tutorial/LangImpl5.html (original) +++ llvm/trunk/docs/tutorial/LangImpl5.html Tue Feb 5 00:18:42 2008 @@ -1735,11 +1735,11 @@ MainLoop(); TheFPM = 0; - } // Free module provider and pass manager. - + + // Print out all of the generated code. + TheModule->dump(); + } // Free module provider (and thus the module) and pass manager. - // Print out all of the generated code. - TheModule->dump(); return 0; } Modified: llvm/trunk/docs/tutorial/LangImpl6.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/tutorial/LangImpl6.html?rev=46741&r1=46740&r2=46741&view=diff ============================================================================== --- llvm/trunk/docs/tutorial/LangImpl6.html (original) +++ llvm/trunk/docs/tutorial/LangImpl6.html Tue Feb 5 00:18:42 2008 @@ -1774,11 +1774,11 @@ MainLoop(); TheFPM = 0; - } // Free module provider and pass manager. - - - // Print out all of the generated code. - TheModule->dump(); + + // Print out all of the generated code. + TheModule->dump(); + } // Free module provider (and thus the module) and pass manager. + return 0; } Modified: llvm/trunk/docs/tutorial/LangImpl7.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/tutorial/LangImpl7.html?rev=46741&r1=46740&r2=46741&view=diff ============================================================================== --- llvm/trunk/docs/tutorial/LangImpl7.html (original) +++ llvm/trunk/docs/tutorial/LangImpl7.html Tue Feb 5 00:18:42 2008 @@ -2129,11 +2129,12 @@ MainLoop(); TheFPM = 0; - } // Free module provider and pass manager. - - - // Print out all of the generated code. - TheModule->dump(); + + // Print out all of the generated code. + TheModule->dump(); + + } // Free module provider (and thus the module) and pass manager. + return 0; } From baldrick at free.fr Tue Feb 5 01:18:05 2008 From: baldrick at free.fr (Duncan Sands) Date: Tue, 5 Feb 2008 08:18:05 +0100 Subject: [llvm-commits] [llvm-gcc-4.2] r46726 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp In-Reply-To: <200802042324.m14NOiBg021071@zion.cs.uiuc.edu> References: <200802042324.m14NOiBg021071@zion.cs.uiuc.edu> Message-ID: <200802050818.06207.baldrick@free.fr> Hi Devang, > Use appropriate alignment while handling packed struct member. do you have a testcase for this? Thanks, Duncan. From natebegeman at mac.com Tue Feb 5 02:49:10 2008 From: natebegeman at mac.com (Nate Begeman) Date: Tue, 05 Feb 2008 08:49:10 -0000 Subject: [llvm-commits] [llvm] r46746 - /llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp Message-ID: <200802050849.m158nB2A021724@zion.cs.uiuc.edu> Author: sampo Date: Tue Feb 5 02:49:09 2008 New Revision: 46746 URL: http://llvm.org/viewvc/llvm-project?rev=46746&view=rev Log: Ident mnemonics appropriately Modified: llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp Modified: llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp?rev=46746&r1=46745&r2=46746&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp Tue Feb 5 02:49:09 2008 @@ -514,10 +514,10 @@ unsigned char MB = MI->getOperand(3).getImm(); unsigned char ME = MI->getOperand(4).getImm(); if (SH <= 31 && MB == 0 && ME == (31-SH)) { - O << "slwi "; FoundMnemonic = true; + O << "\tslwi "; FoundMnemonic = true; } if (SH <= 31 && MB == (32-SH) && ME == 31) { - O << "srwi "; FoundMnemonic = true; + O << "\tsrwi "; FoundMnemonic = true; SH = 32-SH; } if (FoundMnemonic) { @@ -529,7 +529,7 @@ } } else if (MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) { if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) { - O << "mr "; + O << "\tmr "; printOperand(MI, 0); O << ", "; printOperand(MI, 1); @@ -541,7 +541,7 @@ unsigned char ME = MI->getOperand(3).getImm(); // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH if (63-SH == ME) { - O << "sldi "; + O << "\tsldi "; printOperand(MI, 0); O << ", "; printOperand(MI, 1); From isanbard at gmail.com Tue Feb 5 03:46:25 2008 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 05 Feb 2008 09:46:25 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r46747 - in /llvm-gcc-4.2/trunk/gcc: config/darwin.c config/rs6000/rs6000.c varasm.c Message-ID: <200802050946.m159kPRM023332@zion.cs.uiuc.edu> Author: void Date: Tue Feb 5 03:46:24 2008 New Revision: 46747 URL: http://llvm.org/viewvc/llvm-project?rev=46747&view=rev Log: maybe_assemble_visibility issues a warning if the visibility isn't supported on a particular platform. A configuration might check for visibility. A warning in this case indicates that it's not supported. So this warning is actually important. Make it so! Modified: llvm-gcc-4.2/trunk/gcc/config/darwin.c llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.c llvm-gcc-4.2/trunk/gcc/varasm.c Modified: llvm-gcc-4.2/trunk/gcc/config/darwin.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/darwin.c?rev=46747&r1=46746&r2=46747&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/darwin.c (original) +++ llvm-gcc-4.2/trunk/gcc/config/darwin.c Tue Feb 5 03:46:24 2008 @@ -1988,6 +1988,19 @@ extern". There is no MACH-O equivalent of ELF's VISIBILITY_INTERNAL or VISIBILITY_PROTECTED. */ +/* LLVM LOCAL begin */ +#ifdef ENABLE_LLVM +void +darwin_assemble_visibility (tree decl ATTRIBUTE_UNUSED, int vis) +{ + /* Emit a warning if the visibility isn't supported with this + configuration. We don't want to output anything to the ASM file, of + course. */ + if (!(vis == VISIBILITY_DEFAULT || vis == VISIBILITY_HIDDEN)) + warning (OPT_Wattributes, "internal and protected visibility attributes " + "not supported in this configuration; ignored"); +} +#else void darwin_assemble_visibility (tree decl, int vis) { @@ -2004,6 +2017,8 @@ warning (OPT_Wattributes, "internal and protected visibility attributes " "not supported in this configuration; ignored"); } +#endif +/* LLVM LOCAL end */ /* Output a difference of two labels that will be an assembly time constant if the two labels are local. (.long lab1-lab2 will be Modified: llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.c?rev=46747&r1=46746&r2=46747&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.c (original) +++ llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.c Tue Feb 5 03:46:24 2008 @@ -944,10 +944,14 @@ #undef TARGET_ASM_INTEGER #define TARGET_ASM_INTEGER rs6000_assemble_integer +/* LLVM LOCAL - Use default assemble_visibility */ +#ifndef ENABLE_LLVM #ifdef HAVE_GAS_HIDDEN #undef TARGET_ASM_ASSEMBLE_VISIBILITY #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility #endif +/* LLVM LOCAL - Use default assemble_visibility */ +#endif #undef TARGET_HAVE_TLS #define TARGET_HAVE_TLS HAVE_AS_TLS Modified: llvm-gcc-4.2/trunk/gcc/varasm.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/varasm.c?rev=46747&r1=46746&r2=46747&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/varasm.c (original) +++ llvm-gcc-4.2/trunk/gcc/varasm.c Tue Feb 5 03:46:24 2008 @@ -1889,7 +1889,15 @@ fprintf(stderr, "LLVM must emit the data!"); abort(); } + emit_global_to_llvm(decl); + + /* The "make_assemble_visibility" method may issue a warning if the visibility + attribute isn't supported in a configuration. This is all done through a + call-back. We want to issue this same warning when needed. */ + if (TREE_PUBLIC (decl)) + maybe_assemble_visibility (decl); + return; #endif /* LLVM LOCAL end */ @@ -5307,7 +5315,8 @@ name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)); type = visibility_types[vis]; -#ifdef HAVE_GAS_HIDDEN + +#if !defined(ENABLE_LLVM) && defined(HAVE_GAS_HIDDEN) fprintf (asm_out_file, "\t.%s\t", type); assemble_name (asm_out_file, name); fprintf (asm_out_file, "\n"); From isanbard at gmail.com Tue Feb 5 03:52:54 2008 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 05 Feb 2008 09:52:54 -0000 Subject: [llvm-commits] [llvm] r46748 - /llvm/tags/Apple/llvmCore-2015/ Message-ID: <200802050952.m159qsrc023513@zion.cs.uiuc.edu> Author: void Date: Tue Feb 5 03:52:54 2008 New Revision: 46748 URL: http://llvm.org/viewvc/llvm-project?rev=46748&view=rev Log: Creating llvmCore-2015 branch Added: llvm/tags/Apple/llvmCore-2015/ - copied from r46747, llvm/trunk/ From isanbard at gmail.com Tue Feb 5 03:53:01 2008 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 05 Feb 2008 09:53:01 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r46749 - /llvm-gcc-4.2/tags/Apple/llvmgcc42-2015/ Message-ID: <200802050953.m159r1Nt023534@zion.cs.uiuc.edu> Author: void Date: Tue Feb 5 03:53:01 2008 New Revision: 46749 URL: http://llvm.org/viewvc/llvm-project?rev=46749&view=rev Log: Creating llvmgcc42-2015 branch Added: llvm-gcc-4.2/tags/Apple/llvmgcc42-2015/ - copied from r46748, llvm-gcc-4.2/trunk/ From kremenek at apple.com Tue Feb 5 11:30:43 2008 From: kremenek at apple.com (Ted Kremenek) Date: Tue, 05 Feb 2008 17:30:43 -0000 Subject: [llvm-commits] [llvm] r46753 - in /llvm/trunk/include/llvm/ADT: ImmutableMap.h ImmutableSet.h Message-ID: <200802051730.m15HUhgH004956@zion.cs.uiuc.edu> Author: kremenek Date: Tue Feb 5 11:30:43 2008 New Revision: 46753 URL: http://llvm.org/viewvc/llvm-project?rev=46753&view=rev Log: Changed profiling method for ImmutableMap to once again just use its unique ImutAVLTree* for profiling. Modified ImutAVLTree: (1) changed ComputeHash() to ComputeDigest() and (2) changed Profile() to use the computed digest and (3) modified insertion of IMutAVLTree into the FoldingSet owned by the ImutAVLTreeFactory object to use profiling instead of computing a direct hash. This fixes a bug where our abuse of the FoldingSet would not work when the FoldingSet was resized. Modified: llvm/trunk/include/llvm/ADT/ImmutableMap.h llvm/trunk/include/llvm/ADT/ImmutableSet.h Modified: llvm/trunk/include/llvm/ADT/ImmutableMap.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/ImmutableMap.h?rev=46753&r1=46752&r2=46753&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/ImmutableMap.h (original) +++ llvm/trunk/include/llvm/ADT/ImmutableMap.h Tue Feb 5 11:30:43 2008 @@ -206,7 +206,7 @@ inline unsigned getHeight() const { return Root ? Root->getHeight() : 0; } static inline void Profile(FoldingSetNodeID& ID, const ImmutableMap& M) { - M.Root->Profile(ID); + ID.AddPointer(M.Root); } inline void Profile(FoldingSetNodeID& ID) const { Modified: llvm/trunk/include/llvm/ADT/ImmutableSet.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/ImmutableSet.h?rev=46753&r1=46752&r2=46753&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/ImmutableSet.h (original) +++ llvm/trunk/include/llvm/ADT/ImmutableSet.h Tue Feb 5 11:30:43 2008 @@ -203,13 +203,10 @@ return getHeight(); } - /// Profile - Profiling for ImutAVLTree. This is not used by the - // Factory object (which internally uses a FoldingSet), but can - // be used by external clients that wish to insert an ImutAVLTree - // object into a FoldingSet. - void Profile(llvm::FoldingSetNodeID& ID) const { - ID.AddPointer(this); - } + /// Profile - Profiling for ImutAVLTree. + void Profile(llvm::FoldingSetNodeID& ID) { + ID.AddInteger(ComputeDigest()); + } //===----------------------------------------------------===// // Internal Values. @@ -220,7 +217,7 @@ ImutAVLTree* Right; unsigned Height; value_type Value; - unsigned Hash; + unsigned Digest; //===----------------------------------------------------===// // Internal methods (node manipulation; used by Factory). @@ -234,7 +231,7 @@ /// ImutAVLFactory. ImutAVLTree(ImutAVLTree* l, ImutAVLTree* r, value_type_ref v, unsigned height) : Left(reinterpret_cast(l) | Mutable), - Right(r), Height(height), Value(v), Hash(0) {} + Right(r), Height(height), Value(v), Digest(0) {} /// isMutable - Returns true if the left and right subtree references @@ -299,27 +296,27 @@ static inline - unsigned ComputeHash(ImutAVLTree* L, ImutAVLTree* R, value_type_ref V) { - unsigned hash = 0; + unsigned ComputeDigest(ImutAVLTree* L, ImutAVLTree* R, value_type_ref V) { + unsigned digest = 0; - if (L) hash += L->ComputeHash(); + if (L) digest += L->ComputeDigest(); - { // Compute hash of stored data. + { // Compute digest of stored data. FoldingSetNodeID ID; ImutInfo::Profile(ID,V); - hash += ID.ComputeHash(); + digest += ID.ComputeHash(); } - if (R) hash += R->ComputeHash(); + if (R) digest += R->ComputeDigest(); - return hash; + return digest; } - inline unsigned ComputeHash() { - if (Hash) return Hash; + inline unsigned ComputeDigest() { + if (Digest) return Digest; - unsigned X = ComputeHash(getSafeLeft(), getRight(), getValue()); - if (!isMutable()) Hash = X; + unsigned X = ComputeDigest(getSafeLeft(), getRight(), getValue()); + if (!isMutable()) Digest = X; return X; } @@ -408,15 +405,19 @@ //===--------------------------------------------------===// TreeTy* CreateNode(TreeTy* L, value_type_ref V, TreeTy* R) { - // Search the FoldingSet bucket for a Tree with the same hash. - unsigned hash = TreeTy::ComputeHash(L, R, V); + // Search the FoldingSet bucket for a Tree with the same digest. + FoldingSetNodeID ID; + unsigned digest = TreeTy::ComputeDigest(L, R, V); + ID.AddInteger(digest); + unsigned hash = ID.ComputeHash(); + typename CacheTy::bucket_iterator I = Cache.bucket_begin(hash); typename CacheTy::bucket_iterator E = Cache.bucket_end(hash); for (; I != E; ++I) { TreeTy* T = &*I; - if (T->ComputeHash() != hash) + if (T->ComputeDigest() != digest) continue; // We found a collision. Perform a comparison of Contents('T') @@ -454,7 +455,7 @@ // We do not insert 'T' into the FoldingSet here. This is because // this tree is still mutable and things may get rebalanced. - // Because our hash is associative and based on the contents of + // Because our digest is associative and based on the contents of // the set, this should hopefully not cause any strange bugs. // 'T' is inserted by 'MarkImmutable'. @@ -592,7 +593,9 @@ // Now that the node is immutable it can safely be inserted // into the node cache. - Cache.InsertNode(T, (void*) &*Cache.bucket_end(T->ComputeHash())); + llvm::FoldingSetNodeID ID; + ID.AddInteger(T->ComputeDigest()); + Cache.InsertNode(T, (void*) &*Cache.bucket_end(ID.ComputeHash())); } }; From dalej at apple.com Tue Feb 5 11:43:00 2008 From: dalej at apple.com (Dale Johannesen) Date: Tue, 5 Feb 2008 09:43:00 -0800 Subject: [llvm-commits] [llvm] r46727 - /llvm/trunk/include/llvm/IntrinsicsX86.td In-Reply-To: <9642BC09-56CD-4C7C-9294-0E5EA9D99F3E@apple.com> References: <200802042327.m14NRT7G021211@zion.cs.uiuc.edu> <9642BC09-56CD-4C7C-9294-0E5EA9D99F3E@apple.com> Message-ID: <80FF2637-CEA7-46E1-8078-8C7EDAED9CD1@apple.com> On Feb 4, 2008, at 9:07 PM, Chris Lattner wrote: > > On Feb 4, 2008, at 3:27 PM, Dale Johannesen wrote: > >> Author: johannes >> Date: Mon Feb 4 17:27:29 2008 >> New Revision: 46727 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=46727&view=rev >> Log: >> Do not unconditionally redefine vec_ext_v16qi and >> vec_ext_v4si builtins. This is a hack; they should >> be defined here, then resolved in the X86 BE. >> However there is enough other stuff missing in the >> X86 BE for SSE41 that this will do for now. > > I think these are in the category of builtins that should be expanded > by the FE, and thus should be removed. Nate, thoughts? > > -Chris That means you have to know whether you've got SSE4.1 in the FE. This is not an insuperable obstacle, but I think it's better to leave target dependencies in the BE when possible. >> Modified: >> llvm/trunk/include/llvm/IntrinsicsX86.td >> >> Modified: llvm/trunk/include/llvm/IntrinsicsX86.td >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsX86.td?rev=46727&r1=46726&r2=46727&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/include/llvm/IntrinsicsX86.td (original) >> +++ llvm/trunk/include/llvm/IntrinsicsX86.td Mon Feb 4 17:27:29 2008 >> @@ -764,9 +764,9 @@ >> >> // Vector extract >> let TargetPrefix = "x86" in { // All intrinsics start with >> "llvm.x86.". >> - def int_x86_sse41_pextrb : >> GCCBuiltin<"__builtin_ia32_vec_ext_v16qi">, >> + def int_x86_sse41_pextrb : >> Intrinsic<[llvm_i32_ty, llvm_v16i8_ty, llvm_i32_ty]>; >> - def int_x86_sse41_pextrd : >> GCCBuiltin<"__builtin_ia32_vec_ext_v4si">, >> + def int_x86_sse41_pextrd : >> Intrinsic<[llvm_i32_ty, llvm_v4i32_ty, llvm_i32_ty]>; >> def int_x86_sse41_pextrq : >> GCCBuiltin<"__builtin_ia32_vec_ext_v2di">, >> Intrinsic<[llvm_i64_ty, llvm_v2i64_ty, llvm_i32_ty]>; >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From asl at math.spbu.ru Tue Feb 5 12:38:29 2008 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Tue, 05 Feb 2008 21:38:29 +0300 Subject: [llvm-commits] [llvm] r46730 - /llvm/trunk/test/C++Frontend/2006-11-06-StackTrace.cpp In-Reply-To: <200802050025.m150PVXZ022997@zion.cs.uiuc.edu> References: <200802050025.m150PVXZ022997@zion.cs.uiuc.edu> Message-ID: <1202236709.17220.19.camel@asl.dorms.spbu.ru> Evan, > This should also work on x86 now. But this this worked on PPC before then? -- With best regards, Anton Korobeynikov. Faculty of Mathematics & Mechanics, Saint Petersburg State University. From kremenek at apple.com Tue Feb 5 12:50:25 2008 From: kremenek at apple.com (Ted Kremenek) Date: Tue, 05 Feb 2008 18:50:25 -0000 Subject: [llvm-commits] [llvm] r46757 - /llvm/trunk/include/llvm/ADT/ImmutableSet.h Message-ID: <200802051850.m15IoPvF008002@zion.cs.uiuc.edu> Author: kremenek Date: Tue Feb 5 12:50:25 2008 New Revision: 46757 URL: http://llvm.org/viewvc/llvm-project?rev=46757&view=rev Log: Added FoldingSet profiling support to ImmutableSet. Modified: llvm/trunk/include/llvm/ADT/ImmutableSet.h Modified: llvm/trunk/include/llvm/ADT/ImmutableSet.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/ImmutableSet.h?rev=46757&r1=46756&r2=46757&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/ImmutableSet.h (original) +++ llvm/trunk/include/llvm/ADT/ImmutableSet.h Tue Feb 5 12:50:25 2008 @@ -1012,11 +1012,24 @@ iterator end() const { return iterator(); } //===--------------------------------------------------===// + // Utility methods. + //===--------------------------------------------------===// + + inline unsigned getHeight() const { return Root ? Root->getHeight() : 0; } + + static inline void Profile(FoldingSetNodeID& ID, const ImmutableSet& S) { + ID.AddPointer(S.Root); + } + + inline void Profile(FoldingSetNodeID& ID) const { + return Profile(ID,*this); + } + + //===--------------------------------------------------===// // For testing. //===--------------------------------------------------===// void verify() const { if (Root) Root->verify(); } - unsigned getHeight() const { return Root ? Root->getHeight() : 0; } }; } // end namespace llvm From evan.cheng at apple.com Tue Feb 5 13:37:23 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 5 Feb 2008 11:37:23 -0800 Subject: [llvm-commits] [llvm] r46727 - /llvm/trunk/include/llvm/IntrinsicsX86.td In-Reply-To: <80FF2637-CEA7-46E1-8078-8C7EDAED9CD1@apple.com> References: <200802042327.m14NRT7G021211@zion.cs.uiuc.edu> <9642BC09-56CD-4C7C-9294-0E5EA9D99F3E@apple.com> <80FF2637-CEA7-46E1-8078-8C7EDAED9CD1@apple.com> Message-ID: <95A45B70-64AB-4283-815A-14CB22ECAA17@apple.com> On Feb 5, 2008, at 9:43 AM, Dale Johannesen wrote: > > On Feb 4, 2008, at 9:07 PM, Chris Lattner wrote: > >> >> On Feb 4, 2008, at 3:27 PM, Dale Johannesen wrote: >> >>> Author: johannes >>> Date: Mon Feb 4 17:27:29 2008 >>> New Revision: 46727 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=46727&view=rev >>> Log: >>> Do not unconditionally redefine vec_ext_v16qi and >>> vec_ext_v4si builtins. This is a hack; they should >>> be defined here, then resolved in the X86 BE. >>> However there is enough other stuff missing in the >>> X86 BE for SSE41 that this will do for now. >> >> I think these are in the category of builtins that should be expanded >> by the FE, and thus should be removed. Nate, thoughts? >> >> -Chris > > That means you have to know whether you've got SSE4.1 in the FE. > This is not an insuperable obstacle, but I think it's better to leave > target > dependencies in the BE when possible. Even with SSE4.1, it's a good idea to lower them to extract element instructions. X86ISelLoweringhas all the information necessary to determine what instructions to they should be selected to. Evan > > >>> Modified: >>> llvm/trunk/include/llvm/IntrinsicsX86.td >>> >>> Modified: llvm/trunk/include/llvm/IntrinsicsX86.td >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsX86.td?rev=46727&r1=46726&r2=46727&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ==================================================================== >>> --- llvm/trunk/include/llvm/IntrinsicsX86.td (original) >>> +++ llvm/trunk/include/llvm/IntrinsicsX86.td Mon Feb 4 17:27:29 >>> 2008 >>> @@ -764,9 +764,9 @@ >>> >>> // Vector extract >>> let TargetPrefix = "x86" in { // All intrinsics start with >>> "llvm.x86.". >>> - def int_x86_sse41_pextrb : >>> GCCBuiltin<"__builtin_ia32_vec_ext_v16qi">, >>> + def int_x86_sse41_pextrb : >>> Intrinsic<[llvm_i32_ty, llvm_v16i8_ty, llvm_i32_ty]>; >>> - def int_x86_sse41_pextrd : >>> GCCBuiltin<"__builtin_ia32_vec_ext_v4si">, >>> + def int_x86_sse41_pextrd : >>> Intrinsic<[llvm_i32_ty, llvm_v4i32_ty, llvm_i32_ty]>; >>> def int_x86_sse41_pextrq : >>> GCCBuiltin<"__builtin_ia32_vec_ext_v2di">, >>> Intrinsic<[llvm_i64_ty, llvm_v2i64_ty, llvm_i32_ty]>; >>> >>> >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From evan.cheng at apple.com Tue Feb 5 13:37:47 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 5 Feb 2008 11:37:47 -0800 Subject: [llvm-commits] [llvm] r46730 - /llvm/trunk/test/C++Frontend/2006-11-06-StackTrace.cpp In-Reply-To: <1202236709.17220.19.camel@asl.dorms.spbu.ru> References: <200802050025.m150PVXZ022997@zion.cs.uiuc.edu> <1202236709.17220.19.camel@asl.dorms.spbu.ru> Message-ID: <8B7F6F6E-8E1C-4C19-945D-17E91BF2F0FB@apple.com> Yes it did. Evan On Feb 5, 2008, at 10:38 AM, Anton Korobeynikov wrote: > Evan, > >> This should also work on x86 now. > But this this worked on PPC before then? > > -- > With best regards, Anton Korobeynikov. > > Faculty of Mathematics & Mechanics, Saint Petersburg State University. > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From clattner at apple.com Tue Feb 5 13:39:43 2008 From: clattner at apple.com (Chris Lattner) Date: Tue, 5 Feb 2008 11:39:43 -0800 Subject: [llvm-commits] [llvm] r46727 - /llvm/trunk/include/llvm/IntrinsicsX86.td In-Reply-To: <95A45B70-64AB-4283-815A-14CB22ECAA17@apple.com> References: <200802042327.m14NRT7G021211@zion.cs.uiuc.edu> <9642BC09-56CD-4C7C-9294-0E5EA9D99F3E@apple.com> <80FF2637-CEA7-46E1-8078-8C7EDAED9CD1@apple.com> <95A45B70-64AB-4283-815A-14CB22ECAA17@apple.com> Message-ID: <15D95739-61E8-4952-B170-06A6FB1A3716@apple.com> On Feb 5, 2008, at 11:37 AM, Evan Cheng wrote: >> That means you have to know whether you've got SSE4.1 in the FE. >> This is not an insuperable obstacle, but I think it's better to leave >> target >> dependencies in the BE when possible. > > Even with SSE4.1, it's a good idea to lower them to extract element > instructions. X86ISelLoweringhas all the information necessary to > determine what instructions to they should be selected to. Do you mean 'even without SSE4.1'? -Chris From evan.cheng at apple.com Tue Feb 5 13:41:07 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 5 Feb 2008 11:41:07 -0800 Subject: [llvm-commits] [llvm] r46727 - /llvm/trunk/include/llvm/IntrinsicsX86.td In-Reply-To: <15D95739-61E8-4952-B170-06A6FB1A3716@apple.com> References: <200802042327.m14NRT7G021211@zion.cs.uiuc.edu> <9642BC09-56CD-4C7C-9294-0E5EA9D99F3E@apple.com> <80FF2637-CEA7-46E1-8078-8C7EDAED9CD1@apple.com> <95A45B70-64AB-4283-815A-14CB22ECAA17@apple.com> <15D95739-61E8-4952-B170-06A6FB1A3716@apple.com> Message-ID: <72BEB2A5-7674-43F4-9101-86C018AC62A7@apple.com> With or without... On Feb 5, 2008, at 11:39 AM, Chris Lattner wrote: > > On Feb 5, 2008, at 11:37 AM, Evan Cheng wrote: > >>> That means you have to know whether you've got SSE4.1 in the FE. >>> This is not an insuperable obstacle, but I think it's better to >>> leave >>> target >>> dependencies in the BE when possible. >> >> Even with SSE4.1, it's a good idea to lower them to extract element >> instructions. X86ISelLoweringhas all the information necessary to >> determine what instructions to they should be selected to. > > Do you mean 'even without SSE4.1'? > > -Chris > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From sabre at nondot.org Tue Feb 5 13:43:41 2008 From: sabre at nondot.org (Chris Lattner) Date: Tue, 05 Feb 2008 19:43:41 -0000 Subject: [llvm-commits] [llvm] r46760 - in /llvm/trunk: Makefile.rules autoconf/configure.ac Message-ID: <200802051943.m15Jhflj013152@zion.cs.uiuc.edu> Author: lattner Date: Tue Feb 5 13:43:40 2008 New Revision: 46760 URL: http://llvm.org/viewvc/llvm-project?rev=46760&view=rev Log: Make the check for GCC version more robust, fix shared library dependencies in makefile, and fix llvm_cv_no_link_all_option on darwin. Patch by Shantonu Sen, more info here: http://lists.cs.uiuc.edu/pipermail/llvmdev/2008-February/012410.html Modified: llvm/trunk/Makefile.rules llvm/trunk/autoconf/configure.ac Modified: llvm/trunk/Makefile.rules URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=46760&r1=46759&r2=46760&view=diff ============================================================================== --- llvm/trunk/Makefile.rules (original) +++ llvm/trunk/Makefile.rules Tue Feb 5 13:43:40 2008 @@ -805,7 +805,7 @@ else SharedLibKindMessage := "Shared Library" endif -$(LibName.LA): $(ObjectsLO) $(LibDir)/.dir +$(LibName.LA): $(ObjectsLO) $(ProjLibsPaths) $(LLVMLibsPaths) $(LibDir)/.dir $(Echo) Linking $(BuildMode) $(SharedLibKindMessage) \ $(LIBRARYNAME)$(SHLIBEXT) $(Verb) $(LTLink) -o $@ $(ObjectsLO) $(ProjLibsOptions) \ Modified: llvm/trunk/autoconf/configure.ac URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/configure.ac?rev=46760&r1=46759&r2=46760&view=diff ============================================================================== --- llvm/trunk/autoconf/configure.ac (original) +++ llvm/trunk/autoconf/configure.ac Tue Feb 5 13:43:40 2008 @@ -119,7 +119,7 @@ llvm_cv_platform_type="Unix" ;; *-*-darwin*) llvm_cv_link_all_option="-Wl,-all_load" - llvm_cv_link_all_option="-Wl,-noall_load" + llvm_cv_no_link_all_option="-Wl,-noall_load" llvm_cv_os_type="Darwin" llvm_cv_platform_type="Unix" ;; *-*-freebsd*) @@ -656,11 +656,10 @@ dnl Verify that GCC is version 3.0 or higher if test "$GCC" = "yes" then - gccmajor=`$CC --version | head -n 1 | sed 's/[[^0-9]]*\([[0-9.]]\).*/\1/'` - if test "$gccmajor" -lt "3" - then - AC_MSG_ERROR([gcc 3.x required, but you have a lower version]) - fi + AC_COMPILE_IFELSE([[#if !defined(__GNUC__) || __GNUC__ < 3 +#error Unsupported GCC version +#endif +]], [], [AC_MSG_ERROR([gcc 3.x required, but you have a lower version])]) fi dnl Check for GNU Make. We use its extensions, so don't build without it From sabre at nondot.org Tue Feb 5 13:43:53 2008 From: sabre at nondot.org (Chris Lattner) Date: Tue, 05 Feb 2008 19:43:53 -0000 Subject: [llvm-commits] [llvm] r46761 - /llvm/trunk/configure Message-ID: <200802051943.m15Jhs5S013171@zion.cs.uiuc.edu> Author: lattner Date: Tue Feb 5 13:43:53 2008 New Revision: 46761 URL: http://llvm.org/viewvc/llvm-project?rev=46761&view=rev Log: regenerate Modified: llvm/trunk/configure Modified: llvm/trunk/configure URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/configure?rev=46761&r1=46760&r2=46761&view=diff ============================================================================== --- llvm/trunk/configure (original) +++ llvm/trunk/configure Tue Feb 5 13:43:53 2008 @@ -2263,7 +2263,7 @@ llvm_cv_platform_type="Unix" ;; *-*-darwin*) llvm_cv_link_all_option="-Wl,-all_load" - llvm_cv_link_all_option="-Wl,-noall_load" + llvm_cv_no_link_all_option="-Wl,-noall_load" llvm_cv_os_type="Darwin" llvm_cv_platform_type="Unix" ;; *-*-freebsd*) @@ -26953,13 +26953,57 @@ if test "$GCC" = "yes" then - gccmajor=`$CC --version | head -n 1 | sed 's/[^0-9]*\([0-9.]\).*/\1/'` - if test "$gccmajor" -lt "3" - then - { { echo "$as_me:$LINENO: error: gcc 3.x required, but you have a lower version" >&5 + cat >conftest.$ac_ext <<_ACEOF +#if !defined(__GNUC__) || __GNUC__ < 3 +#error Unsupported GCC version +#endif + +_ACEOF +rm -f conftest.$ac_objext +if { (ac_try="$ac_compile" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 + (eval "$ac_compile") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && + { ac_try='test -z "$ac_c_werror_flag" || test ! -s conftest.err' + { (case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 + (eval "$ac_try") 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; } && + { ac_try='test -s conftest.$ac_objext' + { (case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 + (eval "$ac_try") 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; }; then + : +else + echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + { { echo "$as_me:$LINENO: error: gcc 3.x required, but you have a lower version" >&5 echo "$as_me: error: gcc 3.x required, but you have a lower version" >&2;} { (exit 1); exit 1; }; } - fi +fi + +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi if test -z "$llvm_cv_gnu_make_command" From evan.cheng at apple.com Tue Feb 5 14:04:18 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 05 Feb 2008 20:04:18 -0000 Subject: [llvm-commits] [llvm] r46763 - in /llvm/trunk: lib/CodeGen/LiveVariables.cpp test/CodeGen/PowerPC/2008-02-05-LiveIntervalsAssert.ll Message-ID: <200802052004.m15K4I28014352@zion.cs.uiuc.edu> Author: evancheng Date: Tue Feb 5 14:04:18 2008 New Revision: 46763 URL: http://llvm.org/viewvc/llvm-project?rev=46763&view=rev Log: If a vr is already marked alive in a bb, then it has PHI uses that are visited earlier, then it is not killed in the def block (i.e. not dead). Added: llvm/trunk/test/CodeGen/PowerPC/2008-02-05-LiveIntervalsAssert.ll Modified: llvm/trunk/lib/CodeGen/LiveVariables.cpp Modified: llvm/trunk/lib/CodeGen/LiveVariables.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveVariables.cpp?rev=46763&r1=46762&r2=46763&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveVariables.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveVariables.cpp Tue Feb 5 14:04:18 2008 @@ -436,8 +436,9 @@ if (MO.isRegister() && MO.isDef() && MO.getReg()) { if (MRegisterInfo::isVirtualRegister(MO.getReg())) { VarInfo &VRInfo = getVarInfo(MO.getReg()); - // Defaults to dead - VRInfo.Kills.push_back(MI); + if (VRInfo.AliveBlocks.none()) + // If vr is not alive in any block, then defaults to dead. + VRInfo.Kills.push_back(MI); } else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) && !ReservedRegisters[MO.getReg()]) { HandlePhysRegDef(MO.getReg(), MI); Added: llvm/trunk/test/CodeGen/PowerPC/2008-02-05-LiveIntervalsAssert.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/2008-02-05-LiveIntervalsAssert.ll?rev=46763&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/PowerPC/2008-02-05-LiveIntervalsAssert.ll (added) +++ llvm/trunk/test/CodeGen/PowerPC/2008-02-05-LiveIntervalsAssert.ll Tue Feb 5 14:04:18 2008 @@ -0,0 +1,67 @@ +; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin + + %struct.Handle = type { %struct.oopDesc** } + %struct.JNI_ArgumentPusher = type { %struct.SignatureIterator, %struct.JavaCallArguments* } + %struct.JNI_ArgumentPusherArray = type { %struct.JNI_ArgumentPusher, %struct.JvmtiEventEnabled* } + %struct.JavaCallArguments = type { [9 x i32], [9 x i32], i32*, i32*, i32, i32, i32 } + %struct.JvmtiEventEnabled = type { i64 } + %struct.KlassHandle = type { %struct.Handle } + %struct.SignatureIterator = type { i32 (...)**, %struct.KlassHandle, i32, i32, i32 } + %struct.instanceOopDesc = type { %struct.oopDesc } + %struct.oopDesc = type { %struct.instanceOopDesc*, %struct.instanceOopDesc* } + at .str = external constant [44 x i8] ; <[44 x i8]*> [#uses=1] + +define void @_ZN23JNI_ArgumentPusherArray7iterateEy(%struct.JNI_ArgumentPusherArray* %this, i64 %fingerprint) nounwind { +entry: + br label %bb113 + +bb22.preheader: ; preds = %bb113 + ret void + +bb32.preheader: ; preds = %bb113 + ret void + +bb42.preheader: ; preds = %bb113 + ret void + +bb52: ; preds = %bb113 + br label %bb113 + +bb62.preheader: ; preds = %bb113 + ret void + +bb72.preheader: ; preds = %bb113 + ret void + +bb82: ; preds = %bb113 + br label %bb113 + +bb93: ; preds = %bb113 + br label %bb113 + +bb103.preheader: ; preds = %bb113 + ret void + +bb113: ; preds = %bb113, %bb93, %bb82, %bb52, %entry + %fingerprint_addr.0.reg2mem.9 = phi i64 [ 0, %entry ], [ 0, %bb52 ], [ 0, %bb82 ], [ 0, %bb93 ], [ %tmp118, %bb113 ] ; [#uses=1] + tail call void @_Z28report_should_not_reach_herePKci( i8* getelementptr ([44 x i8]* @.str, i32 0, i32 0), i32 817 ) nounwind + %tmp118 = lshr i64 %fingerprint_addr.0.reg2mem.9, 4 ; [#uses=2] + %tmp21158 = and i64 %tmp118, 15 ; [#uses=1] + switch i64 %tmp21158, label %bb113 [ + i64 1, label %bb22.preheader + i64 2, label %bb52 + i64 3, label %bb32.preheader + i64 4, label %bb42.preheader + i64 5, label %bb62.preheader + i64 6, label %bb82 + i64 7, label %bb93 + i64 8, label %bb103.preheader + i64 9, label %bb72.preheader + i64 10, label %UnifiedReturnBlock + ] + +UnifiedReturnBlock: ; preds = %bb113 + ret void +} + +declare void @_Z28report_should_not_reach_herePKci(i8*, i32) From dalej at apple.com Tue Feb 5 14:46:33 2008 From: dalej at apple.com (Dale Johannesen) Date: Tue, 05 Feb 2008 20:46:33 -0000 Subject: [llvm-commits] [llvm] r46764 - in /llvm/trunk: include/llvm/CallingConv.h lib/Target/X86/X86CallingConv.td lib/Target/X86/X86ISelLowering.cpp Message-ID: <200802052046.m15KkXq0016743@zion.cs.uiuc.edu> Author: johannes Date: Tue Feb 5 14:46:33 2008 New Revision: 46764 URL: http://llvm.org/viewvc/llvm-project?rev=46764&view=rev Log: Implement sseregparm. Modified: llvm/trunk/include/llvm/CallingConv.h llvm/trunk/lib/Target/X86/X86CallingConv.td llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/include/llvm/CallingConv.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CallingConv.h?rev=46764&r1=46763&r2=46764&view=diff ============================================================================== --- llvm/trunk/include/llvm/CallingConv.h (original) +++ llvm/trunk/include/llvm/CallingConv.h Tue Feb 5 14:46:33 2008 @@ -57,7 +57,11 @@ /// X86_FastCall - 'fast' analog of X86_StdCall. Passes first two arguments /// in ECX:EDX registers, others - via stack. Callee is responsible for /// stack cleaning. - X86_FastCall = 65 + X86_FastCall = 65, + + /// X86_SSEreg - The standard convention except that float and double + /// values are returned in XMM0 if SSE support is available. + X86_SSECall = 66 }; } // End CallingConv namespace Modified: llvm/trunk/lib/Target/X86/X86CallingConv.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CallingConv.td?rev=46764&r1=46763&r2=46764&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86CallingConv.td (original) +++ llvm/trunk/lib/Target/X86/X86CallingConv.td Tue Feb 5 14:46:33 2008 @@ -61,6 +61,15 @@ CCDelegateTo ]>; +// X86-32 SSEregparm return-value convention. +def RetCC_X86_32_SSE : CallingConv<[ + // The X86-32 sseregparm calling convention returns FP values in XMM0 if the + // target has SSE2, otherwise it is the C calling convention. + CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0]>>>, + CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0]>>>, + CCDelegateTo +]>; + // X86-64 C return-value convention. def RetCC_X86_64_C : CallingConv<[ // The X86-64 calling convention always returns FP values in XMM0. @@ -69,12 +78,12 @@ CCDelegateTo ]>; - - // This is the root return-value convention for the X86-32 backend. def RetCC_X86_32 : CallingConv<[ // If FastCC, use RetCC_X86_32_Fast. CCIfCC<"CallingConv::Fast", CCDelegateTo>, + // If SSECC, use RetCC_X86_32_SSE. + CCIfCC<"CallingConv::X86_SSECall", CCDelegateTo>, // Otherwise, use RetCC_X86_32_C. CCDelegateTo ]>; @@ -179,6 +188,11 @@ // Handles byval parameters. CCIfByVal>, + // The first 3 float or double arguments, if marked 'inreg' and if the call + // is not a vararg call and if SSE2 is available, are passed in SSE registers. + CCIfNotVarArg>>>>, + // Integer/Float values get stored in stack slots that are 4 bytes in // size and 4-byte aligned. CCIfType<[i32, f32], CCAssignToStack<4, 4>>, Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=46764&r1=46763&r2=46764&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Feb 5 14:46:33 2008 @@ -1137,9 +1137,9 @@ RC = X86::GR32RegisterClass; else if (Is64Bit && RegVT == MVT::i64) RC = X86::GR64RegisterClass; - else if (Is64Bit && RegVT == MVT::f32) + else if (RegVT == MVT::f32) RC = X86::FR32RegisterClass; - else if (Is64Bit && RegVT == MVT::f64) + else if (RegVT == MVT::f64) RC = X86::FR64RegisterClass; else { assert(MVT::isVector(RegVT)); From dalej at apple.com Tue Feb 5 14:48:34 2008 From: dalej at apple.com (Dale Johannesen) Date: Tue, 05 Feb 2008 20:48:34 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r46765 - in /llvm-gcc-4.2/trunk/gcc: config/i386/llvm-i386-target.h llvm-types.cpp Message-ID: <200802052048.m15KmZSl016808@zion.cs.uiuc.edu> Author: johannes Date: Tue Feb 5 14:48:34 2008 New Revision: 46765 URL: http://llvm.org/viewvc/llvm-project?rev=46765&view=rev Log: Implement sseregparm in llvm. Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h llvm-gcc-4.2/trunk/gcc/llvm-types.cpp Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h?rev=46765&r1=46764&r2=46765&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h (original) +++ llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h Tue Feb 5 14:48:34 2008 @@ -28,8 +28,11 @@ CC = CallingConv::X86_StdCall; \ } else if (lookup_attribute("fastcall", type_attributes)) { \ CC = CallingConv::X86_FastCall; \ + } else if (!TARGET_64BIT && \ + lookup_attribute("sseregparm", type_attributes)){\ + CC = CallingConv::X86_SSECall; \ } \ - } \ + } /* LLVM specific stuff for converting gcc's `regparm` attribute to LLVM's `inreg` parameter attribute */ @@ -37,28 +40,46 @@ extern int ix86_regparm; -#define LLVM_TARGET_INIT_REGPARM(local_regparm, type) \ +#define LLVM_TARGET_INIT_REGPARM(local_regparm, local_fp_regparm, type) \ { \ tree attr; \ local_regparm = ix86_regparm; \ + local_fp_regparm = TARGET_SSEREGPARM ? 3 : 0; \ attr = lookup_attribute ("regparm", \ TYPE_ATTRIBUTES (type)); \ if (attr) { \ local_regparm = TREE_INT_CST_LOW (TREE_VALUE \ (TREE_VALUE (attr))); \ } \ + attr = lookup_attribute("sseregparm", \ + TYPE_ATTRIBUTES (type)); \ + if (attr) \ + local_fp_regparm = 3; \ } -#define LLVM_ADJUST_REGPARM_ATTRIBUTE(Attribute, Size, \ - local_regparm) \ +#define LLVM_ADJUST_REGPARM_ATTRIBUTE(Attribute, Type, Size, \ + local_regparm, \ + local_fp_regparm) \ { \ if (!TARGET_64BIT) { \ - int words = (Size + BITS_PER_WORD - 1) / BITS_PER_WORD; \ - local_regparm -= words; \ - if (local_regparm>=0) { \ - Attribute |= ParamAttr::InReg; \ - } else \ - local_regparm = 0; \ + if (TREE_CODE(Type) == REAL_TYPE && \ + (TYPE_PRECISION(Type)==32 || \ + TYPE_PRECISION(Type)==64)) { \ + local_fp_regparm -= 1; \ + if (local_fp_regparm >= 0) \ + Attribute |= ParamAttr::InReg; \ + else \ + local_fp_regparm = 0; \ + } else if (TREE_CODE(Type) == INTEGER_TYPE || \ + TREE_CODE(Type) == ENUMERAL_TYPE) { \ + int words = \ + (Size + BITS_PER_WORD - 1) / BITS_PER_WORD; \ + local_regparm -= words; \ + if (local_regparm>=0) \ + Attribute |= ParamAttr::InReg; \ + else \ + local_regparm = 0; \ + } \ } \ } Modified: llvm-gcc-4.2/trunk/gcc/llvm-types.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-types.cpp?rev=46765&r1=46764&r2=46765&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-types.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-types.cpp Tue Feb 5 14:48:34 2008 @@ -1161,8 +1161,9 @@ // If the target has regparam parameters, allow it to inspect the function // type. int local_regparam = 0; + int local_fp_regparam = 0; #ifdef LLVM_TARGET_ENABLE_REGPARM - LLVM_TARGET_INIT_REGPARM(local_regparam, type); + LLVM_TARGET_INIT_REGPARM(local_regparam, local_fp_regparam, type); #endif // LLVM_TARGET_ENABLE_REGPARM // Keep track of whether we see a byval argument. @@ -1208,10 +1209,11 @@ #ifdef LLVM_TARGET_ENABLE_REGPARM // Allow the target to mark this as inreg. - if (TREE_CODE(ArgTy) == INTEGER_TYPE || TREE_CODE(ArgTy) == POINTER_TYPE) - LLVM_ADJUST_REGPARM_ATTRIBUTE(Attributes, + if (TREE_CODE(ArgTy) == INTEGER_TYPE || TREE_CODE(ArgTy) == POINTER_TYPE || + TREE_CODE(ArgTy) == REAL_TYPE) + LLVM_ADJUST_REGPARM_ATTRIBUTE(Attributes, ArgTy, TREE_INT_CST_LOW(TYPE_SIZE(ArgTy)), - local_regparam); + local_regparam, local_fp_regparam); #endif // LLVM_TARGET_ENABLE_REGPARM if (Attributes != ParamAttr::None) { From sabre at nondot.org Tue Feb 5 15:26:24 2008 From: sabre at nondot.org (Chris Lattner) Date: Tue, 05 Feb 2008 21:26:24 -0000 Subject: [llvm-commits] [llvm] r46767 - /llvm/trunk/lib/Transforms/Utils/PromoteMemoryToRegister.cpp Message-ID: <200802052126.m15LQOrh017838@zion.cs.uiuc.edu> Author: lattner Date: Tue Feb 5 15:26:23 2008 New Revision: 46767 URL: http://llvm.org/viewvc/llvm-project?rev=46767&view=rev Log: Make RenamePass faster by making the 'is this a new phi node' check more intelligent. This speeds up mem2reg from 5.29s to 0.79s on a synthetic testcase with tons of predecessors and phi nodes. Modified: llvm/trunk/lib/Transforms/Utils/PromoteMemoryToRegister.cpp Modified: llvm/trunk/lib/Transforms/Utils/PromoteMemoryToRegister.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/PromoteMemoryToRegister.cpp?rev=46767&r1=46766&r2=46767&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/PromoteMemoryToRegister.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/PromoteMemoryToRegister.cpp Tue Feb 5 15:26:23 2008 @@ -849,7 +849,6 @@ return true; } - // RenamePass - Recursively traverse the CFG of the function, renaming loads and // stores to the allocas which we are promoting. IncomingVals indicates what // value each Alloca contains on exit from the predecessor block Pred. @@ -877,6 +876,14 @@ // If we have PHI nodes to update, compute the number of edges from Pred to // BB. if (!HasPredEntries) { + // We want to be able to distinguish between PHI nodes being inserted by + // this invocation of mem2reg from those phi nodes that already existed in + // the IR before mem2reg was run. We determine that APN is being inserted + // because it is missing incoming edges. All other PHI nodes being + // inserted by this pass of mem2reg will have the same number of incoming + // operands so far. Remember this count. + unsigned NewPHINumOperands = APN->getNumOperands(); + TerminatorInst *PredTerm = Pred->getTerminator(); unsigned NumEdges = 0; for (unsigned i = 0, e = PredTerm->getNumSuccessors(); i != e; ++i) { @@ -902,16 +909,9 @@ APN = dyn_cast(PNI); if (APN == 0) break; - // Verify it doesn't already have entries for Pred. If it does, it is - // not being inserted by this mem2reg invocation. - HasPredEntries = false; - for (unsigned i = 0, e = APN->getNumIncomingValues(); i != e; ++i) { - if (APN->getIncomingBlock(i) == Pred) { - HasPredEntries = true; - break; - } - } - } while (!HasPredEntries); + // Verify that it is missing entries. If not, it is not being inserted + // by this mem2reg invocation so we want to ignore it. + } while (APN->getNumOperands() == NewPHINumOperands); } } From asl at math.spbu.ru Tue Feb 5 15:56:53 2008 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Wed, 06 Feb 2008 00:56:53 +0300 Subject: [llvm-commits] [llvm-gcc-4.2] r46765 - in /llvm-gcc-4.2/trunk/gcc: config/i386/llvm-i386-target.h llvm-types.cpp In-Reply-To: <200802052048.m15KmZSl016808@zion.cs.uiuc.edu> References: <200802052048.m15KmZSl016808@zion.cs.uiuc.edu> Message-ID: <1202248613.17220.31.camel@asl.dorms.spbu.ru> Hi Dale, Looks like there is some desynchronization here now: > + } else if (TREE_CODE(Type) == INTEGER_TYPE || \ > + TREE_CODE(Type) == ENUMERAL_TYPE) { \ Shouldn't be POINTER_TYPE here also? > + if (TREE_CODE(ArgTy) == INTEGER_TYPE || TREE_CODE(ArgTy) == POINTER_TYPE || > + TREE_CODE(ArgTy) == REAL_TYPE) And ENUMERAL_TYPE here? -- With best regards, Anton Korobeynikov. Faculty of Mathematics & Mechanics, Saint Petersburg State University. From dalej at apple.com Tue Feb 5 16:16:30 2008 From: dalej at apple.com (Dale Johannesen) Date: Tue, 5 Feb 2008 14:16:30 -0800 Subject: [llvm-commits] [llvm-gcc-4.2] r46765 - in /llvm-gcc-4.2/trunk/gcc: config/i386/llvm-i386-target.h llvm-types.cpp In-Reply-To: <1202248613.17220.31.camel@asl.dorms.spbu.ru> References: <200802052048.m15KmZSl016808@zion.cs.uiuc.edu> <1202248613.17220.31.camel@asl.dorms.spbu.ru> Message-ID: On Feb 5, 2008, at 1:56 PM, Anton Korobeynikov wrote: > Hi Dale, > > Looks like there is some desynchronization here now: > >> + } else if (TREE_CODE(Type) == INTEGER_TYPE || \ >> + TREE_CODE(Type) == ENUMERAL_TYPE) { \ > Shouldn't be POINTER_TYPE here also? > >> + if (TREE_CODE(ArgTy) == INTEGER_TYPE || TREE_CODE(ArgTy) == >> POINTER_TYPE || >> + TREE_CODE(ArgTy) == REAL_TYPE) > And ENUMERAL_TYPE here? Oops, I meant POINTER throughout, as it was before. Will fix, thanks. From clattner at apple.com Tue Feb 5 16:19:12 2008 From: clattner at apple.com (Chris Lattner) Date: Tue, 5 Feb 2008 14:19:12 -0800 Subject: [llvm-commits] [llvm] r46727 - /llvm/trunk/include/llvm/IntrinsicsX86.td In-Reply-To: <72BEB2A5-7674-43F4-9101-86C018AC62A7@apple.com> References: <200802042327.m14NRT7G021211@zion.cs.uiuc.edu> <9642BC09-56CD-4C7C-9294-0E5EA9D99F3E@apple.com> <80FF2637-CEA7-46E1-8078-8C7EDAED9CD1@apple.com> <95A45B70-64AB-4283-815A-14CB22ECAA17@apple.com> <15D95739-61E8-4952-B170-06A6FB1A3716@apple.com> <72BEB2A5-7674-43F4-9101-86C018AC62A7@apple.com> Message-ID: <483704A9-E821-436F-9BDC-97BB1188F38C@apple.com> On Feb 5, 2008, at 11:41 AM, Evan Cheng wrote: > With or without... Right, I agree. The f.e. should do this unconditionally, -Chris > > > On Feb 5, 2008, at 11:39 AM, Chris Lattner wrote: > >> >> On Feb 5, 2008, at 11:37 AM, Evan Cheng wrote: >> >>>> That means you have to know whether you've got SSE4.1 in the FE. >>>> This is not an insuperable obstacle, but I think it's better to >>>> leave >>>> target >>>> dependencies in the BE when possible. >>> >>> Even with SSE4.1, it's a good idea to lower them to extract element >>> instructions. X86ISelLoweringhas all the information necessary to >>> determine what instructions to they should be selected to. >> >> Do you mean 'even without SSE4.1'? >> >> -Chris >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From dalej at apple.com Tue Feb 5 16:22:24 2008 From: dalej at apple.com (Dale Johannesen) Date: Tue, 05 Feb 2008 22:22:24 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r46773 - /llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h Message-ID: <200802052222.m15MMO5D019349@zion.cs.uiuc.edu> Author: johannes Date: Tue Feb 5 16:22:23 2008 New Revision: 46773 URL: http://llvm.org/viewvc/llvm-project?rev=46773&view=rev Log: Fix per review feedback. Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h?rev=46773&r1=46772&r2=46773&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h (original) +++ llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h Tue Feb 5 16:22:23 2008 @@ -71,7 +71,7 @@ else \ local_fp_regparm = 0; \ } else if (TREE_CODE(Type) == INTEGER_TYPE || \ - TREE_CODE(Type) == ENUMERAL_TYPE) { \ + TREE_CODE(Type) == POINTER_TYPE) { \ int words = \ (Size + BITS_PER_WORD - 1) / BITS_PER_WORD; \ local_regparm -= words; \ From dalej at apple.com Tue Feb 5 16:23:51 2008 From: dalej at apple.com (Dale Johannesen) Date: Tue, 5 Feb 2008 14:23:51 -0800 Subject: [llvm-commits] [llvm-gcc-4.2] r46765 - in /llvm-gcc-4.2/trunk/gcc: config/i386/llvm-i386-target.h llvm-types.cpp In-Reply-To: References: <200802052048.m15KmZSl016808@zion.cs.uiuc.edu> <1202248613.17220.31.camel@asl.dorms.spbu.ru> Message-ID: On Feb 5, 2008, at 2:16 PM, Dale Johannesen wrote: > > On Feb 5, 2008, at 1:56 PM, Anton Korobeynikov wrote: > >> Hi Dale, >> >> Looks like there is some desynchronization here now: >> >>> + } else if (TREE_CODE(Type) == INTEGER_TYPE || \ >>> + TREE_CODE(Type) == ENUMERAL_TYPE) { \ >> Shouldn't be POINTER_TYPE here also? >> >>> + if (TREE_CODE(ArgTy) == INTEGER_TYPE || TREE_CODE(ArgTy) == >>> POINTER_TYPE || >>> + TREE_CODE(ArgTy) == REAL_TYPE) >> And ENUMERAL_TYPE here? > > Oops, I meant POINTER throughout, as it was before. Will fix, thanks. Fixed. There is something wrong with the dependencies. I had to remove llvm-types.o to get it to recompile. From clattner at apple.com Tue Feb 5 16:25:12 2008 From: clattner at apple.com (Chris Lattner) Date: Tue, 5 Feb 2008 14:25:12 -0800 Subject: [llvm-commits] [llvm] r46764 - in /llvm/trunk: include/llvm/CallingConv.h lib/Target/X86/X86CallingConv.td lib/Target/X86/X86ISelLowering.cpp In-Reply-To: <200802052046.m15KkXq0016743@zion.cs.uiuc.edu> References: <200802052046.m15KkXq0016743@zion.cs.uiuc.edu> Message-ID: <0D34AD0E-E368-4E71-9E90-345AFC264D83@apple.com> On Feb 5, 2008, at 12:46 PM, Dale Johannesen wrote: > URL: http://llvm.org/viewvc/llvm-project?rev=46764&view=rev > Log: > Implement sseregparm. Very nice. One thought about X86_SSECall: if it is only used to return float/ double in an xmm reg, you could get the same effect by having the CFE lower ssecall functions to return <4x f32> and <2 x f64> instead of float/double. On the callee, you'd end up with an "ret insertelement undef, fpval" and on the caller side you'd get an extract element. I think the calling convention stuff that Evan has been working on is powerful enough to model though sort of stuff, but might need minor extensions. Do you think it would be reasonable do use this approach? Doing so would eliminate a "magic" calling convention, which would be nice :) -Chris From asl at math.spbu.ru Tue Feb 5 16:27:00 2008 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Wed, 06 Feb 2008 01:27:00 +0300 Subject: [llvm-commits] [llvm-gcc-4.2] r46773 - /llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h In-Reply-To: <200802052222.m15MMO5D019349@zion.cs.uiuc.edu> References: <200802052222.m15MMO5D019349@zion.cs.uiuc.edu> Message-ID: <1202250420.17220.38.camel@asl.dorms.spbu.ru> > URL: http://llvm.org/viewvc/llvm-project?rev=46773&view=rev > Log: > Fix per review feedback. Thanks! -- With best regards, Anton Korobeynikov. Faculty of Mathematics & Mechanics, Saint Petersburg State University. From gohman at apple.com Tue Feb 5 15:53:12 2008 From: gohman at apple.com (Dan Gohman) Date: Tue, 5 Feb 2008 13:53:12 -0800 Subject: [llvm-commits] [llvm] r46556 - in /llvm/trunk: include/llvm/CodeGen/PseudoSourceValue.h include/llvm/Value.h lib/CodeGen/PseudoSourceValue.cpp Message-ID: > Some comments on the patch: > > + > + // Save loads/stores matched by a pattern. > + if (!N->isLeaf() && N->getName().empty() && > + ((N->getOperator()->getName() == "ld") || > + (N->getOperator()->getName() == "st") || > + (N->getOperator()->getName() == "ist"))) { > + LSI.push_back(RootName); > + } > + > > I am not sure about this. Perhaps it should be similar to > what > InstrInfoEmitter.cpp is doing? The MayStore and MayLoad properties are per-instruction; the code above needs to know which specific SDNodes in the pattern will be represented with StoreSDNode or LoadSDNode. An alternative to checking for "st" and friends would be to check if the node's Opcode field is one of the strings "ISD::STORE" or "ISD::LOAD"; I guess that's a little more flexible. > + static const char *PSVNames[] = { > + "FPRel", > + "SPRel", > + "GPRel", > + "TPRel", > + "CPRel", > + "JTRel" > + }; > > I am taking exception to the names. FPRel looks too much like it has > something to do with FP register, GPRel looks like it is referring to > general purpose register. How about just spill it out? e.g. > StackObjRel, FixedStackObjRel, GOTRel, ThreadPtrRel, > ConstPoolRel, JumpTabRel? Sounds reasonable to me. I'll update this before committing. Dan From dalej at apple.com Tue Feb 5 16:31:13 2008 From: dalej at apple.com (Dale Johannesen) Date: Tue, 5 Feb 2008 14:31:13 -0800 Subject: [llvm-commits] [llvm] r46764 - in /llvm/trunk: include/llvm/CallingConv.h lib/Target/X86/X86CallingConv.td lib/Target/X86/X86ISelLowering.cpp In-Reply-To: <0D34AD0E-E368-4E71-9E90-345AFC264D83@apple.com> References: <200802052046.m15KkXq0016743@zion.cs.uiuc.edu> <0D34AD0E-E368-4E71-9E90-345AFC264D83@apple.com> Message-ID: <61A65A2A-8D56-4CAA-8A0A-095A85626BB5@apple.com> On Feb 5, 2008, at 2:25 PM, Chris Lattner wrote: > On Feb 5, 2008, at 12:46 PM, Dale Johannesen wrote: >> URL: http://llvm.org/viewvc/llvm-project?rev=46764&view=rev >> Log: >> Implement sseregparm. > > Very nice. > > One thought about X86_SSECall: if it is only used to return float/ > double in an xmm reg, you could get the same effect by having the CFE > lower ssecall functions to return <4x f32> and <2 x f64> instead of > float/double. On the callee, you'd end up with an "ret insertelement > undef, fpval" and on the caller side you'd get an extract element. > > I think the calling convention stuff that Evan has been working on is > powerful enough to model though sort of stuff, but might need minor > extensions. Do you think it would be reasonable do use this > approach? Doing so would eliminate a "magic" calling convention, > which would be nice :) It would, but coercing standard types to a different type strikes me as worse. The IR really ought to be able to handle standard types without obfuscation. What I really wanted was to put InReg on the return value. From clattner at apple.com Tue Feb 5 16:34:05 2008 From: clattner at apple.com (Chris Lattner) Date: Tue, 5 Feb 2008 14:34:05 -0800 Subject: [llvm-commits] [llvm] r46764 - in /llvm/trunk: include/llvm/CallingConv.h lib/Target/X86/X86CallingConv.td lib/Target/X86/X86ISelLowering.cpp In-Reply-To: <61A65A2A-8D56-4CAA-8A0A-095A85626BB5@apple.com> References: <200802052046.m15KkXq0016743@zion.cs.uiuc.edu> <0D34AD0E-E368-4E71-9E90-345AFC264D83@apple.com> <61A65A2A-8D56-4CAA-8A0A-095A85626BB5@apple.com> Message-ID: <9624F9F3-E870-4832-BAA0-4591C872DC0D@apple.com> On Feb 5, 2008, at 2:31 PM, Dale Johannesen wrote: >> I think the calling convention stuff that Evan has been working on is >> powerful enough to model though sort of stuff, but might need minor >> extensions. Do you think it would be reasonable do use this >> approach? Doing so would eliminate a "magic" calling convention, >> which would be nice :) > > It would, but coercing standard types to a different type strikes me > as worse. > The IR really ought to be able to handle standard types without > obfuscation. I don't think it would be a problem in this specific case, but I understand what you mean. > What I really wanted was to put InReg on the return value. Ah, that's a good idea. Why not do that? :) Generally, putting the attribute on argument "#0" means that the attribute applies to the function or the return value. Given that 'inreg' doesn't make any sense for a function, it would be fine to overload it for this, what do you think? -Chris From dalej at apple.com Tue Feb 5 16:36:28 2008 From: dalej at apple.com (Dale Johannesen) Date: Tue, 5 Feb 2008 14:36:28 -0800 Subject: [llvm-commits] [llvm] r46764 - in /llvm/trunk: include/llvm/CallingConv.h lib/Target/X86/X86CallingConv.td lib/Target/X86/X86ISelLowering.cpp In-Reply-To: <9624F9F3-E870-4832-BAA0-4591C872DC0D@apple.com> References: <200802052046.m15KkXq0016743@zion.cs.uiuc.edu> <0D34AD0E-E368-4E71-9E90-345AFC264D83@apple.com> <61A65A2A-8D56-4CAA-8A0A-095A85626BB5@apple.com> <9624F9F3-E870-4832-BAA0-4591C872DC0D@apple.com> Message-ID: On Feb 5, 2008, at 2:34 PM, Chris Lattner wrote: > On Feb 5, 2008, at 2:31 PM, Dale Johannesen wrote: >>> I think the calling convention stuff that Evan has been working on >>> is >>> powerful enough to model though sort of stuff, but might need minor >>> extensions. Do you think it would be reasonable do use this >>> approach? Doing so would eliminate a "magic" calling convention, >>> which would be nice :) >> >> It would, but coercing standard types to a different type strikes me >> as worse. >> The IR really ought to be able to handle standard types without >> obfuscation. > > I don't think it would be a problem in this specific case, but I > understand what you mean. > >> What I really wanted was to put InReg on the return value. > > Ah, that's a good idea. Why not do that? :) Generally, putting the > attribute on argument "#0" means that the attribute applies to the > function or the return value. Given that 'inreg' doesn't make any > sense for a function, it would be fine to overload it for this, what > do you think? Sound good if it's that simple. It looked more complicated, but I was probably missing something. I'll look again. From dalej at apple.com Tue Feb 5 16:40:30 2008 From: dalej at apple.com (Dale Johannesen) Date: Tue, 5 Feb 2008 14:40:30 -0800 Subject: [llvm-commits] [llvm] r46727 - /llvm/trunk/include/llvm/IntrinsicsX86.td In-Reply-To: <483704A9-E821-436F-9BDC-97BB1188F38C@apple.com> References: <200802042327.m14NRT7G021211@zion.cs.uiuc.edu> <9642BC09-56CD-4C7C-9294-0E5EA9D99F3E@apple.com> <80FF2637-CEA7-46E1-8078-8C7EDAED9CD1@apple.com> <95A45B70-64AB-4283-815A-14CB22ECAA17@apple.com> <15D95739-61E8-4952-B170-06A6FB1A3716@apple.com> <72BEB2A5-7674-43F4-9101-86C018AC62A7@apple.com> <483704A9-E821-436F-9BDC-97BB1188F38C@apple.com> Message-ID: <34696A8C-0C4F-4E4E-9E2B-7724804D54F2@apple.com> On Feb 5, 2008, at 2:19 PM, Chris Lattner wrote: > On Feb 5, 2008, at 11:41 AM, Evan Cheng wrote: >> With or without... > > Right, I agree. The f.e. should do this unconditionally, > > -Chris OK, maybe so. The trouble is people use those builtins that are linked to a particular instruction, and expect to get that instruction and nothing else. But I don't have much sympathy for those people:) >> On Feb 5, 2008, at 11:39 AM, Chris Lattner wrote: >>> On Feb 5, 2008, at 11:37 AM, Evan Cheng wrote: >>> >>>>> That means you have to know whether you've got SSE4.1 in the FE. >>>>> This is not an insuperable obstacle, but I think it's better to >>>>> leave >>>>> target >>>>> dependencies in the BE when possible. >>>> >>>> Even with SSE4.1, it's a good idea to lower them to extract element >>>> instructions. X86ISelLoweringhas all the information necessary to >>>> determine what instructions to they should be selected to. >>> >>> Do you mean 'even without SSE4.1'? >>> >>> -Chris >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From evan.cheng at apple.com Tue Feb 5 16:44:07 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 05 Feb 2008 22:44:07 -0000 Subject: [llvm-commits] [llvm] r46775 - /llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Message-ID: <200802052244.m15Mi7TI020034@zion.cs.uiuc.edu> Author: evancheng Date: Tue Feb 5 16:44:06 2008 New Revision: 46775 URL: http://llvm.org/viewvc/llvm-project?rev=46775&view=rev Log: Move to getCALLSEQ_END to ensure CALLSEQ_END node produces a flag. This is consistent with the definition in td file. Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=46775&r1=46774&r2=46775&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Tue Feb 5 16:44:06 2008 @@ -1227,6 +1227,13 @@ Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size()); InFlag = Chain.getValue(1); + Chain = DAG.getCALLSEQ_END(Chain, + DAG.getConstant(NumStackBytes, PtrVT), + DAG.getConstant(0, PtrVT), + InFlag); + if (Op.Val->getValueType(0) != MVT::Other) + InFlag = Chain.getValue(1); + SDOperand ResultVals[3]; unsigned NumResults = 0; NodeTys.clear(); @@ -1278,8 +1285,6 @@ break; } - Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, - DAG.getConstant(NumStackBytes, PtrVT)); NodeTys.push_back(MVT::Other); // If the function returns void, just return the chain. From evan.cheng at apple.com Tue Feb 5 16:50:29 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 05 Feb 2008 22:50:29 -0000 Subject: [llvm-commits] [llvm] r46776 - in /llvm/trunk: lib/CodeGen/SelectionDAG/SelectionDAG.cpp test/CodeGen/X86/2008-02-05-ISelCrash.ll utils/TableGen/DAGISelEmitter.cpp Message-ID: <200802052250.m15MoTAi020239@zion.cs.uiuc.edu> Author: evancheng Date: Tue Feb 5 16:50:29 2008 New Revision: 46776 URL: http://llvm.org/viewvc/llvm-project?rev=46776&view=rev Log: Fix PR1975: dag isel emitter produces patterns that isel wrong flag result. Added: llvm/trunk/test/CodeGen/X86/2008-02-05-ISelCrash.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=46776&r1=46775&r2=46776&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue Feb 5 16:50:29 2008 @@ -3183,10 +3183,6 @@ void SelectionDAG::ReplaceAllUsesWith(SDOperand FromN, SDOperand To, DAGUpdateListener *UpdateListener) { SDNode *From = FromN.Val; - // FIXME: This works around a dag isel emitter bug. - if (From->getNumValues() == 1 && FromN.ResNo != 0) - return; // FIXME: THIS IS BOGUS - assert(From->getNumValues() == 1 && FromN.ResNo == 0 && "Cannot replace with this method!"); assert(From != To.Val && "Cannot replace uses of with self"); Added: llvm/trunk/test/CodeGen/X86/2008-02-05-ISelCrash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-02-05-ISelCrash.ll?rev=46776&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2008-02-05-ISelCrash.ll (added) +++ llvm/trunk/test/CodeGen/X86/2008-02-05-ISelCrash.ll Tue Feb 5 16:50:29 2008 @@ -0,0 +1,12 @@ +; RUN: llvm-as < %s | llc -march=x86 +; PR1975 + + at nodes = external global i64 ; [#uses=2] + +define fastcc i32 @ab(i32 %alpha, i32 %beta) nounwind { +entry: + %tmp1 = load i64* @nodes, align 8 ; [#uses=1] + %tmp2 = add i64 %tmp1, 1 ; [#uses=1] + store i64 %tmp2, i64* @nodes, align 8 + ret i32 0 +} Modified: llvm/trunk/utils/TableGen/DAGISelEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelEmitter.cpp?rev=46776&r1=46775&r2=46776&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/DAGISelEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Tue Feb 5 16:50:29 2008 @@ -305,6 +305,8 @@ std::map VariableMap; // Node to operator mapping std::map OperatorMap; + // Name of the folded node which produces a flag. + std::pair FoldedFlag; // Names of all the folded nodes which produce chains. std::vector > FoldedChains; // Original input chain(s). @@ -587,8 +589,17 @@ emitCheck(RootName + ".getOpcode() == " + CInfo.getEnumName()); EmitMatchCode(Child, Parent, RootName, ChainSuffix, FoundChain); - if (NodeHasProperty(Child, SDNPHasChain, CGP)) + bool HasChain = false; + if (NodeHasProperty(Child, SDNPHasChain, CGP)) { + HasChain = true; FoldedChains.push_back(std::make_pair(RootName, CInfo.getNumResults())); + } + if (NodeHasProperty(Child, SDNPOutFlag, CGP)) { + assert(FoldedFlag.first == "" && FoldedFlag.second == 0 && + "Pattern folded multiple nodes which produce flags?"); + FoldedFlag = std::make_pair(RootName, + CInfo.getNumResults() + (unsigned)HasChain); + } } else { // If this child has a name associated with it, capture it in VarMap. If // we already saw this in the pattern, emit code to verify dagness. @@ -1105,9 +1116,15 @@ } if (NodeHasOutFlag) { - emitCode("ReplaceUses(SDOperand(N.Val, " + - utostr(NumPatResults + (unsigned)InputHasChain) - +"), InFlag);"); + if (FoldedFlag.first != "") { + emitCode("ReplaceUses(SDOperand(" + FoldedFlag.first + ".Val, " + + utostr(FoldedFlag.second) + "), InFlag);"); + } else { + assert(NodeHasProperty(Pattern, SDNPOutFlag, CGP)); + emitCode("ReplaceUses(SDOperand(N.Val, " + + utostr(NumPatResults + (unsigned)InputHasChain) + +"), InFlag);"); + } NeedReplace = true; } From isanbard at gmail.com Tue Feb 5 16:50:40 2008 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 5 Feb 2008 14:50:40 -0800 Subject: [llvm-commits] [llvm] r46727 - /llvm/trunk/include/llvm/IntrinsicsX86.td In-Reply-To: <34696A8C-0C4F-4E4E-9E2B-7724804D54F2@apple.com> References: <200802042327.m14NRT7G021211@zion.cs.uiuc.edu> <9642BC09-56CD-4C7C-9294-0E5EA9D99F3E@apple.com> <80FF2637-CEA7-46E1-8078-8C7EDAED9CD1@apple.com> <95A45B70-64AB-4283-815A-14CB22ECAA17@apple.com> <15D95739-61E8-4952-B170-06A6FB1A3716@apple.com> <72BEB2A5-7674-43F4-9101-86C018AC62A7@apple.com> <483704A9-E821-436F-9BDC-97BB1188F38C@apple.com> <34696A8C-0C4F-4E4E-9E2B-7724804D54F2@apple.com> Message-ID: <16e5fdf90802051450l17b20593rf8218bf21e901112@mail.gmail.com> On Feb 5, 2008 2:40 PM, Dale Johannesen wrote: > > On Feb 5, 2008, at 2:19 PM, Chris Lattner wrote: > > > On Feb 5, 2008, at 11:41 AM, Evan Cheng wrote: > >> With or without... > > > > Right, I agree. The f.e. should do this unconditionally, > > > > -Chris > > OK, maybe so. The trouble is people use those builtins that are > linked to a > particular instruction, and expect to get that instruction and nothing > else. > But I don't have much sympathy for those people:) > That's when we point them to the docs on inline ASM ;-) -bw From asl at math.spbu.ru Tue Feb 5 17:34:41 2008 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Tue, 05 Feb 2008 23:34:41 -0000 Subject: [llvm-commits] [llvm] r46781 - /llvm/trunk/include/llvm/ADT/StringMap.h Message-ID: <200802052334.m15NYfoM021622@zion.cs.uiuc.edu> Author: asl Date: Tue Feb 5 17:34:40 2008 New Revision: 46781 URL: http://llvm.org/viewvc/llvm-project?rev=46781&view=rev Log: Don't dereference an invalid pointer if string is empty. Modified: llvm/trunk/include/llvm/ADT/StringMap.h Modified: llvm/trunk/include/llvm/ADT/StringMap.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/StringMap.h?rev=46781&r1=46780&r2=46781&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/StringMap.h (original) +++ llvm/trunk/include/llvm/ADT/StringMap.h Tue Feb 5 17:34:40 2008 @@ -273,7 +273,7 @@ return find(Key, Key + strlen(Key)); } iterator find(const std::string &Key) { - const char* key_start = &Key[0]; + const char* key_start = (Key.empty() ? NULL : &Key[0]); return find(key_start, key_start + Key.size()); } @@ -286,7 +286,7 @@ return find(Key, Key + strlen(Key)); } const_iterator find(const std::string &Key) const { - const char* key_start = &Key[0]; + const char* key_start = (Key.empty() ? NULL : &Key[0]); return find(key_start, key_start + Key.size()); } @@ -295,7 +295,7 @@ return entry.getValue(); } ValueTy& operator[](const std::string &Key) { - const char* key_start = &Key[0]; + const char* key_start = (Key.empty() ? NULL : &Key[0]); value_type& entry = GetOrCreateValue(key_start, key_start + Key.size()); return entry.getValue(); } @@ -307,7 +307,7 @@ return count(Key, Key + strlen(Key)); } size_type count(const std::string &Key) const { - const char* key_start = &Key[0]; + const char* key_start = (Key.empty() ? NULL : &Key[0]); return count(key_start, key_start + Key.size()); } From tonic at nondot.org Tue Feb 5 18:54:55 2008 From: tonic at nondot.org (Tanya Lattner) Date: Wed, 06 Feb 2008 00:54:55 -0000 Subject: [llvm-commits] [llvm] r46790 - /llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Message-ID: <200802060054.m160stK3023791@zion.cs.uiuc.edu> Author: tbrethou Date: Tue Feb 5 18:54:55 2008 New Revision: 46790 URL: http://llvm.org/viewvc/llvm-project?rev=46790&view=rev Log: Throttle the non-local dependence analysis for basic blocks with more than 50 predecessors. Added command line option to play with this threshold. Modified: llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Modified: llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp?rev=46790&r1=46789&r2=46790&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Tue Feb 5 18:54:55 2008 @@ -20,6 +20,7 @@ #include "llvm/Function.h" #include "llvm/Analysis/AliasAnalysis.h" #include "llvm/Support/CFG.h" +#include "llvm/Support/CommandLine.h" #include "llvm/Target/TargetData.h" #include "llvm/ADT/Statistic.h" @@ -27,6 +28,15 @@ using namespace llvm; +namespace { + // Control the calculation of non-local dependencies by only examining the + // predecessors if the basic block has less than X amount (50 by default). + cl::opt + PredLimit("nonlocaldep-threshold", cl::Hidden, cl::init(50), + cl::desc("Control the calculation of non-local" + "dependencies (default = 50)")); +} + STATISTIC(NumCacheNonlocal, "Number of cached non-local responses"); STATISTIC(NumUncacheNonlocal, "Number of uncached non-local responses"); @@ -211,15 +221,18 @@ } // If we didn't find anything, recurse on the precessors of this block + // Only do this for blocks with a small number of predecessors. bool predOnStack = false; bool inserted = false; - for (pred_iterator PI = pred_begin(BB), PE = pred_end(BB); - PI != PE; ++PI) - if (!visited.count(*PI)) { - stack.push_back(*PI); - inserted = true; - } else - predOnStack = true; + if (std::distance(pred_begin(BB), pred_end(BB)) <= PredLimit) { + for (pred_iterator PI = pred_begin(BB), PE = pred_end(BB); + PI != PE; ++PI) + if (!visited.count(*PI)) { + stack.push_back(*PI); + inserted = true; + } else + predOnStack = true; + } // If we inserted a new predecessor, then we'll come back to this block if (inserted) From resistor at mac.com Tue Feb 5 21:28:55 2008 From: resistor at mac.com (Owen Anderson) Date: Tue, 5 Feb 2008 21:28:55 -0600 Subject: [llvm-commits] [llvm] r46790 - /llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp In-Reply-To: <200802060054.m160stK3023791@zion.cs.uiuc.edu> References: <200802060054.m160stK3023791@zion.cs.uiuc.edu> Message-ID: <6887BD71-4476-4914-81C2-90E2AD8765E7@mac.com> Wow, that must be one hell of a CFG you're dealing with. ;-) --Owen On Feb 5, 2008, at 6:54 PM, Tanya Lattner wrote: > Author: tbrethou > Date: Tue Feb 5 18:54:55 2008 > New Revision: 46790 > > URL: http://llvm.org/viewvc/llvm-project?rev=46790&view=rev > Log: > Throttle the non-local dependence analysis for basic blocks with > more than 50 predecessors. Added command line option to play with > this threshold. > > Modified: > llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp > > Modified: llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp?rev=46790&r1=46789&r2=46790&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp (original) > +++ llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Tue Feb 5 > 18:54:55 2008 > @@ -20,6 +20,7 @@ > #include "llvm/Function.h" > #include "llvm/Analysis/AliasAnalysis.h" > #include "llvm/Support/CFG.h" > +#include "llvm/Support/CommandLine.h" > #include "llvm/Target/TargetData.h" > #include "llvm/ADT/Statistic.h" > > @@ -27,6 +28,15 @@ > > using namespace llvm; > > +namespace { > + // Control the calculation of non-local dependencies by only > examining the > + // predecessors if the basic block has less than X amount (50 by > default). > + cl::opt > + PredLimit("nonlocaldep-threshold", cl::Hidden, cl::init(50), > + cl::desc("Control the calculation of non-local" > + "dependencies (default = 50)")); > +} > + > STATISTIC(NumCacheNonlocal, "Number of cached non-local responses"); > STATISTIC(NumUncacheNonlocal, "Number of uncached non-local > responses"); > > @@ -211,15 +221,18 @@ > } > > // If we didn't find anything, recurse on the precessors of this > block > + // Only do this for blocks with a small number of predecessors. > bool predOnStack = false; > bool inserted = false; > - for (pred_iterator PI = pred_begin(BB), PE = pred_end(BB); > - PI != PE; ++PI) > - if (!visited.count(*PI)) { > - stack.push_back(*PI); > - inserted = true; > - } else > - predOnStack = true; > + if (std::distance(pred_begin(BB), pred_end(BB)) <= PredLimit) { > + for (pred_iterator PI = pred_begin(BB), PE = pred_end(BB); > + PI != PE; ++PI) > + if (!visited.count(*PI)) { > + stack.push_back(*PI); > + inserted = true; > + } else > + predOnStack = true; > + } > > // If we inserted a new predecessor, then we'll come back to > this block > if (inserted) > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -------------- next part -------------- A non-text attachment was scrubbed... Name: smime.p7s Type: application/pkcs7-signature Size: 2555 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20080205/41d83392/attachment.bin From sabre at nondot.org Wed Feb 6 00:30:34 2008 From: sabre at nondot.org (Chris Lattner) Date: Wed, 06 Feb 2008 06:30:34 -0000 Subject: [llvm-commits] [llvm] r46810 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <200802060630.m166UYm3000469@zion.cs.uiuc.edu> Author: lattner Date: Wed Feb 6 00:30:34 2008 New Revision: 46810 URL: http://llvm.org/viewvc/llvm-project?rev=46810&view=rev Log: a starter shell for 2.2 release notes Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=46810&r1=46809&r2=46810&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Wed Feb 6 00:30:34 2008 @@ -4,11 +4,11 @@ - LLVM 2.1 Release Notes + LLVM 2.2 Release Notes -
LLVM 2.1 Release Notes
+
LLVM 2.2 Release Notes
  1. Introduction
    2. @@ -32,7 +32,7 @@

    This document contains the release notes for the LLVM compiler -infrastructure, release 2.1. Here we describe the status of LLVM, including +infrastructure, release 2.2. Here we describe the status of LLVM, including major improvements from the previous release and any known problems. All LLVM releases may be downloaded from the LLVM releases web site.

    @@ -58,31 +58,35 @@
    -

    This is the twelfth public release of the LLVM Compiler Infrastructure. -It includes many features and refinements from LLVM 2.0.

    +

    This is the thirteenth public release of the LLVM Compiler Infrastructure. +It includes many features and refinements from LLVM 2.1.

    -New Frontends +llvm-gcc 4.0, llvm-gcc 4.2, and clang
    -

    LLVM 2.1 brings two new beta C front-ends. First, a new version of llvm-gcc -based on GCC 4.2, innovatively called "llvm-gcc-4.2". This promises to bring -FORTRAN and Ada support to LLVM as well as features like atomic builtins and -OpenMP. None of these actually work yet, but don't let that stop you checking -it out!

    - -

    Second, LLVM now includes its own native C and Objective-C front-end (C++ is -in progress, but is not very far along) code named "clang". This front-end has a number of great -features, primarily aimed at source-level analysis and speeding up compile-time. -At this point though, the LLVM Code Generator component is still very early in -development, so it's mostly useful for people looking to build source-level -analysis tools or source-to-source translators.

    +

    LLVM 2.2 fully supports both the llvm-gcc 4.0 and llvm-gcc 4.2 front-ends (in +LLVM 2.1, llvm-gcc 4.2 was beta). Since LLVM 2.1, the llvm-gcc 4.2 front-end +has made leaps and bounds and is now at least as good as 4.0 in virtually every +area, and is better in several areas (for example, exception handling +correctness). We strongly recommend that you migrate from llvm-gcc 4.0 to +llvm-gcc 4.2 in this release cycle because LLVM 2.2 is the last release +that will support llvm-gcc 4.0: LLVM 2.3 will only support the llvm-gcc +4.2 front-end.

    + +

    The clang project is an effort +to build a set of new front-end technology for the LLVM optimizer and code +generator. Currently, its C and Objective-C support is maturing nicely, and it +has advanced source-to-source analysis and transformation capabilities. If you +are interested in building source-level tools for C and Objective-C (and +eventually C++), you should take a look. However, note that clang is not an +official part of the LLVM 2.2 release. If you are interested in this project, +please see the web site and check it out from SVN head.

    @@ -98,24 +102,7 @@
      -
    • Owen Anderson wrote the new MemoryDependenceAnalysis pass, which provides - a lazy, caching layer on top of AliasAnalysis. He then used it to rewrite - DeadStoreElimination which resulted in significantly better compile time in - common cases,
      • -
    • Owen implemented the new GVN pass, which is also based on - MemoryDependenceAnalysis. This pass replaces GCSE/LoadVN in the standard - set of passes, providing more aggressive optimization at a some-what - improved compile-time cost.
      • -
    • Owen implemented GVN-PRE, a partial redundancy elimination algorithm that - shares some details with the new GVN pass. It is still in need of compile - time tuning, and is not turned on by default.
      • -
    • Devang merged ETForest and DomTree into a single easier to use data - structure. This makes it more obvious which datastructure to choose - (because there is only one) and makes the compiler more memory and time - efficient (less stuff to keep up-to-date).
      • -
    • Nick Lewycky improved loop trip count analysis to handle many more common - cases.
      • +
    • .
    @@ -133,38 +120,7 @@
      -
    • Dale finished up the Tail Merging optimization in the code generator, and - enabled it by default. This produces smaller code that is also faster in - some cases.
      • - -
    • Christopher Lamb implemented support for virtual register sub-registers, - which can be used to better model many forms of subregisters. As an example - use, he modified the X86 backend to use this to model truncates and - extends more accurately (leading to better code).
      • - -
    • Dan Gohman changed the way we represent vectors before legalization, - significantly simplifying the SelectionDAG representation for these and - making the code generator faster for vector code.
      • - -
    • Evan contributed a new target independent if-converter. While it is - target independent, so far only the ARM backend uses it.
      • - -
    • Evan rewrote the way the register allocator handles rematerialization, - allowing it to be much more effective on two-address targets like X86, - and taught it to fold loads away when possible (also a big win on X86).
      • - -
    • Dan Gohman contributed support for better alignment and volatility handling - in the code generator, and significantly enhanced alignment analysis for SSE - load/store instructions. With his changes, an insufficiently-aligned SSE - load instruction turns into movups, for example.
      • - -
    • Duraid Madina contributed a new "bigblock" register allocator, and Roman - Levenstein contributed several big improvements. BigBlock is optimized for - code that uses very large basic blocks. It is slightly slower than the - "local" allocator, but produces much better code.
      • - -
    • David Greene refactored the register allocator to split coalescing out from - allocation, making coalescers pluggable.
      • +
    • .
    @@ -181,19 +137,7 @@

      -
    • Bruno Cardoso Lopes contributed initial MIPS support. It is sufficient to - run many small programs, but is still incomplete and is not yet - fully performant.
      • - -
    • Bill Wendling added SSSE3 support to the X86 backend.
      • - -
    • Nicholas Geoffray contributed improved linux/ppc ABI and JIT support.
      • - -
    • Dale Johannesen rewrote handling of 32-bit float values in the X86 backend - when using the floating point stack, fixing several nasty bugs.
      • - -
    • Dan contributed rematerialization support for the X86 backend, in addition - to several X86-specific micro optimizations.
      • +
    • .
    @@ -209,28 +153,7 @@

      -
    • Duncan and Anton made significant progress chasing down a number of problems - with C++ Zero-Cost exception handling in llvm-gcc 4.0 and 4.2. It is now at - the point where it "just works" on linux/X86-32 and has partial support on - other targets.
      • - -
    • Devang and Duncan fixed a huge number of bugs relating to bitfields, pragma - pack, and variable sized fields in structures.
      • - -
    • Tanya implemented support for __attribute__((noinline)) in - llvm-gcc, and added support for generic variable annotations which are - propagated into the LLVM IR, e.g. - "int X __attribute__((annotate("myproperty")));".
      • - -
    • Sheng Zhou and Christopher Lamb implemented alias analysis support for -"restrict" pointer arguments to functions.
      • - -
    • Duncan contributed support for trampolines (taking the address of a nested - function). Currently this is only supported on the X86-32 target.
      • - -
    • Lauro Ramos Venancio contributed support to encode alignment info in - load and store instructions, the foundation for other alignment-related - work.
      • +
    • .
    @@ -246,22 +169,7 @@

      -
    • Neil Booth contributed a new "APFloat" class, which ensures that floating - point representation and constant folding is not dependent on the host - architecture that builds the application. This support is the foundation - for "long double" support that will be wrapped up in LLVM 2.2.
      • - -
    • Based on the APFloat class, Dale redesigned the internals of the ConstantFP - class and has been working on extending the core and optimizer components to - support various target-specific 'long double's. We expect this work to be - completed in LLVM 2.2.
      • - -
    • LLVM now provides an LLVMBuilder class, which makes it significantly easier - to create LLVM IR instructions.
      • - -
    • Reid contributed support for intrinsics that take arbitrary integer typed - arguments. Dan Gohman and Chandler extended it to support arbitrary - floating point arguments and vectors.
      • +
    • .
    @@ -276,13 +184,7 @@

      -
    • Sterling Stein contributed a new BrainF frontend, located in llvm/examples. - This shows a some of the more modern APIs for building a front-end, and - demonstrates JIT compiler support.
      • - -
    • David Green contributed a new --enable-expensive-checks configure - option which enables STL checking, and fixed several bugs exposed by - it.
      • +
    • .
    @@ -300,7 +202,7 @@
    • Intel and AMD machines running Red Hat Linux, Fedora Core and FreeBSD (and probably other unix-like systems).
      • -
    • PowerPC and X86-based Mac OS X systems, running 10.2 and above in 32-bit and +
    • PowerPC and X86-based Mac OS X systems, running 10.3 and above in 32-bit and 64-bit modes.
    • Intel and AMD machines running on Win32 using MinGW libraries (native)
    • Intel and AMD machines running on Win32 with the Cygwin libraries (limited @@ -350,11 +252,10 @@
      • The -cee pass is known to be buggy, and may be removed in a future release.
        • -
      • The MSIL backend is experimental.
        • -
      • The IA64 code generator is experimental.
        • -
      • The Alpha backend is experimental.
        • -
      • "-filetype=asm" (the default) is the only supported value for the - -filetype llc option.
        • +
      • The MSIL, IA64, Alpha, and MIPS backends are experimental.
        • +
      • The LLC "-filetype=asm" (the default) is the only supported + value for this option.
        • +
      • The llvmc tool is not supported.
      @@ -384,8 +285,6 @@
      @@ -515,10 +414,6 @@
        -

      • "long double" is silently transformed by the front-end into "double". There -is no support for floating point data types of any size other than 32 and 64 -bits.

        • -

      • llvm-gcc does not support __builtin_apply yet. See Constructing Calls: Dispatching a call to another function.

        • @@ -623,29 +518,7 @@ itself, Qt, Mozilla, etc.

          -
        • Exception handling only works well on the linux/X86-32 target. -In some cases, illegally throwing an exception does not result -in a call to terminate.
          • - - +
        • Exception handling only works well on the X86 and PowerPC targets.
      From evan.cheng at apple.com Wed Feb 6 02:00:32 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 06 Feb 2008 08:00:32 -0000 Subject: [llvm-commits] [llvm] r46813 - /llvm/trunk/lib/CodeGen/RegAllocLocal.cpp Message-ID: <200802060800.m1680WmO002729@zion.cs.uiuc.edu> Author: evancheng Date: Wed Feb 6 02:00:32 2008 New Revision: 46813 URL: http://llvm.org/viewvc/llvm-project?rev=46813&view=rev Log: RegAllocaLocal still *requires* LiveVariables since it runs PHIElimination, followed by TwoAddress which requires LiveVariables. We cannot run LiveVariables on non-SSA code. Modified: llvm/trunk/lib/CodeGen/RegAllocLocal.cpp Modified: llvm/trunk/lib/CodeGen/RegAllocLocal.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocLocal.cpp?rev=46813&r1=46812&r2=46813&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocLocal.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocLocal.cpp Wed Feb 6 02:00:32 2008 @@ -14,11 +14,12 @@ #define DEBUG_TYPE "regalloc" #include "llvm/BasicBlock.h" -#include "llvm/CodeGen/Passes.h" +#include "llvm/CodeGen/LiveVariables.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/RegAllocRegistry.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" @@ -146,6 +147,7 @@ } virtual void getAnalysisUsage(AnalysisUsage &AU) const { + AU.addRequired(); AU.addRequiredID(PHIEliminationID); AU.addRequiredID(TwoAddressInstructionPassID); MachineFunctionPass::getAnalysisUsage(AU); From gabor at mac.com Wed Feb 6 07:33:06 2008 From: gabor at mac.com (Gabor Greif) Date: Wed, 06 Feb 2008 14:33:06 +0100 Subject: [llvm-commits] [llvm] r46810 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <47A9B712.8050301@mac.com> Here my 2 cent: +

      The clang project is an effort +to build a set of new front-end technology for the LLVM optimizer and code ^ technologies +generator. Currently, its C and Objective-C support is maturing nicely, and it +has advanced source-to-source analysis and transformation capabilities. If you +are interested in building source-level tools for C and Objective-C (and +eventually C++), you should take a look. However, note that clang is not an +official part of the LLVM 2.2 release. If you are interested in this project, +please see the web site and check it out from SVN head.

      Comment that it is developed in sync with llvm SVN head ? In the doc: "main focuses" --?--> "main foci" ? "using MinGW libraries (native)" --> "using MinGW libraries (native)." "The -cee pass is known to be buggy, and may be removed in a future release." Is it already gone in 2.2 or on SVN head? "The Linux PPC32/ABI support needs testing for the interpreter and static compilation, and lacks support for debug information." IIRC this has been fixed. "llvm-gcc4 does" llvm-gcc4.0 or llvm-gcc4.2 ? Cheers, Gabor From sabre at nondot.org Wed Feb 6 12:00:07 2008 From: sabre at nondot.org (Chris Lattner) Date: Wed, 06 Feb 2008 18:00:07 -0000 Subject: [llvm-commits] [llvm] r46816 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <200802061800.m16I07hk027721@zion.cs.uiuc.edu> Author: lattner Date: Wed Feb 6 12:00:06 2008 New Revision: 46816 URL: http://llvm.org/viewvc/llvm-project?rev=46816&view=rev Log: add a bunch of random notes and fix some issues noticed by Gabor. This is not ready for review or hacking, this is a work in progress :) Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=46816&r1=46815&r2=46816&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Wed Feb 6 12:00:06 2008 @@ -79,14 +79,38 @@ that will support llvm-gcc 4.0: LLVM 2.3 will only support the llvm-gcc 4.2 front-end.

      -

      The clang project is an effort -to build a set of new front-end technology for the LLVM optimizer and code -generator. Currently, its C and Objective-C support is maturing nicely, and it -has advanced source-to-source analysis and transformation capabilities. If you -are interested in building source-level tools for C and Objective-C (and -eventually C++), you should take a look. However, note that clang is not an -official part of the LLVM 2.2 release. If you are interested in this project, -please see the web site and check it out from SVN head.

      +

      The clang project is an effort to build +a set of new 'llvm native' front-end technologies for the LLVM optimizer +and code generator. Currently, its C and Objective-C support is maturing +nicely, and it has advanced source-to-source analysis and transformation +capabilities. If you are interested in building source-level tools for C and +Objective-C (and eventually C++), you should take a look. However, note that +clang is not an official part of the LLVM 2.2 release. If you are interested in +this project, please see the web site.

      + +
      + + +
      +Major New Features +
      + +
      + +

      Dale contributed full support for long double on x86/x86-64 (where it is 80 +bits) and on Darwin PPC/PPC64 (where it is 128 bits).

      + +

      Ada, gfortran

      + +

      +debug improvements -O0 +EH. + +Gordon: GC Revamp. docs/GarbageCollection.html + +Kaleidescope: docs/tutorial + +Gordon: C and Ocaml Bindings

      @@ -102,8 +126,12 @@
        -
      • .
        • +
      • Daniel Berlin and (?) rewrote Andersen's alias analysis (which is not +enabled by default) to be several orders of magnitude faster, implmented Offline +Variable Substitution.
        • + +Devang: LoopIndexSplit is enabled by default.
      @@ -115,13 +143,17 @@
      -

      One of the main focuses of this release was performance tuning and bug +

      foci of this release was performance tuning and bug fixing. In addition to these, several new major changes occurred:

        -
      • .
        • +
      • Owen contributed Machine Loop info, domintors, etc.
        • +
      • Dan added support for emitting debug information with .file and .loc on +targets that support it
        • + +
      • Evan physical register dependencies in the BURR scheduler
      @@ -137,7 +169,8 @@

        -
      • .
        • +
      • Evan X86 now models EFLAGS in instructions.
        • +
      • Evan: If conversion on by default for ARM.
      @@ -204,7 +237,7 @@ (and probably other unix-like systems).
    • PowerPC and X86-based Mac OS X systems, running 10.3 and above in 32-bit and 64-bit modes.
      • -
    • Intel and AMD machines running on Win32 using MinGW libraries (native)
      • +
    • Intel and AMD machines running on Win32 using MinGW libraries (native).
    • Intel and AMD machines running on Win32 with the Cygwin libraries (limited support is available for native builds with Visual C++).
    • Sun UltraSPARC workstations running Solaris 8.
      • @@ -250,8 +283,8 @@ components, please contact us on the LLVMdev list.

        -
      • The -cee pass is known to be buggy, and may be removed in a - future release.
        • +
      • The -cee pass is known to be buggy and will be removed in + LLVM 2.3.
      • The MSIL, IA64, Alpha, and MIPS backends are experimental.
      • The LLC "-filetype=asm" (the default) is the only supported value for this option.
        • @@ -400,8 +433,8 @@
        -

        llvm-gcc4 does not currently support Link-Time -Optimization on most platforms "out-of-the-box". Please inquire on the +

        llvm-gcc does not currently support Link-Time +Optimization on most platforms "out-of-the-box". Please inquire on the llvmdev mailing list if you are interested.

        From sabre at nondot.org Wed Feb 6 12:00:48 2008 From: sabre at nondot.org (Chris Lattner) Date: Wed, 06 Feb 2008 18:00:48 -0000 Subject: [llvm-commits] [llvm] r46817 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <200802061800.m16I0mHx027755@zion.cs.uiuc.edu> Author: lattner Date: Wed Feb 6 12:00:48 2008 New Revision: 46817 URL: http://llvm.org/viewvc/llvm-project?rev=46817&view=rev Log: make it clear :) Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=46817&r1=46816&r2=46817&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Wed Feb 6 12:00:48 2008 @@ -23,6 +23,9 @@

        Written by the LLVM Team

        +

        THIS IS A WORK IN PROGRESS FOR THE LLVM 2.2 +RELEASE +
        Introduction From clattner at apple.com Wed Feb 6 12:02:02 2008 From: clattner at apple.com (Chris Lattner) Date: Wed, 6 Feb 2008 10:02:02 -0800 Subject: [llvm-commits] [llvm] r46810 - /llvm/trunk/docs/ReleaseNotes.html In-Reply-To: <47A9B712.8050301@mac.com> References: <47A9B712.8050301@mac.com> Message-ID: <2417D7F3-9342-4F66-906D-DCFEFD7483CB@apple.com> On Feb 6, 2008, at 5:33 AM, Gabor Greif wrote: > Here my 2 cent: Thanks Gabor. I wasn't really ready for review, but I appreciate it :) > +

        The clang project is an > effort > +to build a set of new front-end technology for the LLVM optimizer > and code > ^ > technologies Fixed. > +generator. Currently, its C and Objective-C support is maturing > nicely, and it > +has advanced source-to-source analysis and transformation > capabilities. If you > +are interested in building source-level tools for C and Objective-C > (and > +eventually C++), you should take a look. However, note that clang > is not an > +official part of the LLVM 2.2 release. If you are interested in > this project, > +please see the web site and check it out from SVN head.

        > > Comment that it is developed in sync with llvm SVN head ? I just removed where the check it out. > In the doc: > "main focuses" --?--> "main foci" ? > "using MinGW libraries (native)" --> "using MinGW libraries (native)." Ok. > "The -cee pass is known to be buggy, and may be removed in a future > release." > Is it already gone in 2.2 or on SVN head? SVN Head, I clarified. > "The Linux PPC32/ABI support needs testing for the interpreter and > static compilation, and lacks support for debug information." > IIRC this has been fixed. I'm pretty sure there are still significant issues, with varargs for example. > "llvm-gcc4 does" > llvm-gcc4.0 or llvm-gcc4.2 ? Fixed. Neither! -Chris From echristo at apple.com Wed Feb 6 12:13:57 2008 From: echristo at apple.com (Eric Christopher) Date: Wed, 6 Feb 2008 10:13:57 -0800 Subject: [llvm-commits] [llvm] r46817 - /llvm/trunk/docs/ReleaseNotes.html In-Reply-To: <200802061800.m16I0mHx027755@zion.cs.uiuc.edu> References: <200802061800.m16I0mHx027755@zion.cs.uiuc.edu> Message-ID: <7B278341-4325-450B-8EFA-B8A401480642@apple.com> > > +

        THIS IS A WORK IN PROGRESS FOR THE LLVM 2.2 > +RELEASE > + You forgot the blink tag :) -eric From clattner at apple.com Wed Feb 6 12:17:44 2008 From: clattner at apple.com (Chris Lattner) Date: Wed, 6 Feb 2008 10:17:44 -0800 Subject: [llvm-commits] [llvm] r46817 - /llvm/trunk/docs/ReleaseNotes.html In-Reply-To: <7B278341-4325-450B-8EFA-B8A401480642@apple.com> References: <200802061800.m16I0mHx027755@zion.cs.uiuc.edu> <7B278341-4325-450B-8EFA-B8A401480642@apple.com> Message-ID: On Feb 6, 2008, at 10:13 AM, Eric Christopher wrote: >> >> +

        THIS IS A WORK IN PROGRESS FOR THE LLVM 2.2 >> +RELEASE >> + > > You forgot the blink tag :) How about a javascript animation using canvas!? :) -Chris From dalej at apple.com Wed Feb 6 12:18:14 2008 From: dalej at apple.com (Dale Johannesen) Date: Wed, 6 Feb 2008 10:18:14 -0800 Subject: [llvm-commits] [llvm] r46764 - in /llvm/trunk: include/llvm/CallingConv.h lib/Target/X86/X86CallingConv.td lib/Target/X86/X86ISelLowering.cpp In-Reply-To: References: <200802052046.m15KkXq0016743@zion.cs.uiuc.edu> <0D34AD0E-E368-4E71-9E90-345AFC264D83@apple.com> <61A65A2A-8D56-4CAA-8A0A-095A85626BB5@apple.com> <9624F9F3-E870-4832-BAA0-4591C872DC0D@apple.com> Message-ID: <4A426418-DFAF-4344-AA68-BF5121A88514@apple.com> On Feb 5, 2008, at 2:36 PM, Dale Johannesen wrote: > On Feb 5, 2008, at 2:34 PM, Chris Lattner wrote: >> On Feb 5, 2008, at 2:31 PM, Dale Johannesen wrote: >>>> I think the calling convention stuff that Evan has been working >>>> on is >>>> powerful enough to model though sort of stuff, but might need minor >>>> extensions. Do you think it would be reasonable do use this >>>> approach? Doing so would eliminate a "magic" calling convention, >>>> which would be nice :) >>> >>> It would, but coercing standard types to a different type strikes me >>> as worse. >>> The IR really ought to be able to handle standard types without >>> obfuscation. >> >> I don't think it would be a problem in this specific case, but I >> understand what you mean. >> >>> What I really wanted was to put InReg on the return value. >> >> Ah, that's a good idea. Why not do that? :) Generally, putting the >> attribute on argument "#0" means that the attribute applies to the >> function or the return value. Given that 'inreg' doesn't make any >> sense for a function, it would be fine to overload it for this, what >> do you think? > > Sound good if it's that simple. It looked more complicated, but I > was probably missing something. I'll look again. Attaching this to the Function node went smoothly enough, but I actually need it on the Return node, which it appears isn't supported in the current IR, but is in the the machine-level RET node. I could transfer the info from the Function node to the RET node at some point, or even reference the Function node from the code that handles RET I suppose, but it seems cleaner to change the IR; which would break binary compatibility. Considering that this works as is and is not all that important to begin with, I'm thinking it's best to wait until we can change the IR and do it right. Thoughts? From clattner at apple.com Wed Feb 6 12:25:12 2008 From: clattner at apple.com (Chris Lattner) Date: Wed, 6 Feb 2008 10:25:12 -0800 Subject: [llvm-commits] [llvm] r46764 - in /llvm/trunk: include/llvm/CallingConv.h lib/Target/X86/X86CallingConv.td lib/Target/X86/X86ISelLowering.cpp In-Reply-To: <4A426418-DFAF-4344-AA68-BF5121A88514@apple.com> References: <200802052046.m15KkXq0016743@zion.cs.uiuc.edu> <0D34AD0E-E368-4E71-9E90-345AFC264D83@apple.com> <61A65A2A-8D56-4CAA-8A0A-095A85626BB5@apple.com> <9624F9F3-E870-4832-BAA0-4591C872DC0D@apple.com> <4A426418-DFAF-4344-AA68-BF5121A88514@apple.com> Message-ID: >>> >>> Ah, that's a good idea. Why not do that? :) Generally, putting the >>> attribute on argument "#0" means that the attribute applies to the >>> function or the return value. Given that 'inreg' doesn't make any >>> sense for a function, it would be fine to overload it for this, what >>> do you think? >> >> Sound good if it's that simple. It looked more complicated, but I >> was probably missing something. I'll look again. > > Attaching this to the Function node went smoothly enough, but I > actually need it on the Return node, which it appears isn't > supported in the current IR, but is in the the machine-level RET > node. I could transfer the info from the Function node to the RET > node at some point, or even reference the Function node from the > code that handles RET I suppose, but it seems cleaner to change the > IR; which would break binary compatibility. Considering that this > works as is and is not all that important to begin with, I'm > thinking it's best to wait until we can change the IR and do it > right. Thoughts? From the current SelectionDAG you can get a pointer to the Function object, which should have the attribute. Lowering for an ISD::RET can thus getting it from following this chain, -Chris From sabre at nondot.org Wed Feb 6 12:32:06 2008 From: sabre at nondot.org (Chris Lattner) Date: Wed, 06 Feb 2008 18:32:06 -0000 Subject: [llvm-commits] [llvm] r46818 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <200802061832.m16IW6VH028654@zion.cs.uiuc.edu> Author: lattner Date: Wed Feb 6 12:32:06 2008 New Revision: 46818 URL: http://llvm.org/viewvc/llvm-project?rev=46818&view=rev Log: some more notes. Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=46818&r1=46817&r2=46818&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Wed Feb 6 12:32:06 2008 @@ -129,7 +129,7 @@
          -
        • Daniel Berlin and (?) rewrote Andersen's alias analysis (which is not +
        • Daniel Berlin and (Curtis?) rewrote Andersen's alias analysis (which is not enabled by default) to be several orders of magnitude faster, implmented Offline Variable Substitution.
          • @@ -151,12 +151,15 @@
            -
          • Owen contributed Machine Loop info, domintors, etc.
            • +
          • Owen contributed Machine Loop info, domintors, etc. Merged dom and + postdom.
          • Dan added support for emitting debug information with .file and .loc on targets that support it
          • Evan physical register dependencies in the BURR scheduler
            • + +
          • Evan EXTRACT_SUBREG coalescing support

        @@ -174,6 +177,8 @@
        • Evan X86 now models EFLAGS in instructions.
        • Evan: If conversion on by default for ARM.
          • +
        • Bruno: MIPS PIC support.
          • +
        • Arnold Schwaighofer: X86 tail call support.
        @@ -205,7 +210,8 @@

          -
        • .
          • +
        • Devang added LLVMFoldingBuilder.
          • +
        • Dan added support for vector sin, cos, and pow intrinsics.
        From dalej at apple.com Wed Feb 6 12:36:24 2008 From: dalej at apple.com (Dale Johannesen) Date: Wed, 6 Feb 2008 10:36:24 -0800 Subject: [llvm-commits] [llvm] r46764 - in /llvm/trunk: include/llvm/CallingConv.h lib/Target/X86/X86CallingConv.td lib/Target/X86/X86ISelLowering.cpp In-Reply-To: References: <200802052046.m15KkXq0016743@zion.cs.uiuc.edu> <0D34AD0E-E368-4E71-9E90-345AFC264D83@apple.com> <61A65A2A-8D56-4CAA-8A0A-095A85626BB5@apple.com> <9624F9F3-E870-4832-BAA0-4591C872DC0D@apple.com> <4A426418-DFAF-4344-AA68-BF5121A88514@apple.com> Message-ID: On Feb 6, 2008, at 10:25 AM, Chris Lattner wrote: >>>> >>>> Ah, that's a good idea. Why not do that? :) Generally, putting >>>> the >>>> attribute on argument "#0" means that the attribute applies to the >>>> function or the return value. Given that 'inreg' doesn't make any >>>> sense for a function, it would be fine to overload it for this, >>>> what >>>> do you think? >>> >>> Sound good if it's that simple. It looked more complicated, but I >>> was probably missing something. I'll look again. >> >> Attaching this to the Function node went smoothly enough, but I >> actually need it on the Return node, which it appears isn't >> supported in the current IR, but is in the the machine-level RET >> node. I could transfer the info from the Function node to the RET >> node at some point, or even reference the Function node from the >> code that handles RET I suppose, but it seems cleaner to change the >> IR; which would break binary compatibility. Considering that this >> works as is and is not all that important to begin with, I'm >> thinking it's best to wait until we can change the IR and do it >> right. Thoughts? > > From the current SelectionDAG you can get a pointer to the Function > object, which should have the attribute. Lowering for an ISD::RET > can thus getting it from following this chain, I know, I just don't think that's the right way to do it. From clattner at apple.com Wed Feb 6 12:48:51 2008 From: clattner at apple.com (Chris Lattner) Date: Wed, 6 Feb 2008 10:48:51 -0800 Subject: [llvm-commits] [llvm] r46764 - in /llvm/trunk: include/llvm/CallingConv.h lib/Target/X86/X86CallingConv.td lib/Target/X86/X86ISelLowering.cpp In-Reply-To: References: <200802052046.m15KkXq0016743@zion.cs.uiuc.edu> <0D34AD0E-E368-4E71-9E90-345AFC264D83@apple.com> <61A65A2A-8D56-4CAA-8A0A-095A85626BB5@apple.com> <9624F9F3-E870-4832-BAA0-4591C872DC0D@apple.com> <4A426418-DFAF-4344-AA68-BF5121A88514@apple.com> Message-ID: >>> Attaching this to the Function node went smoothly enough, but I >>> actually need it on the Return node, which it appears isn't >>> supported in the current IR, but is in the the machine-level RET >>> node. I could transfer the info from the Function node to the RET >>> node at some point, or even reference the Function node from the >>> code that handles RET I suppose, but it seems cleaner to change the >>> IR; which would break binary compatibility. Considering that this >>> works as is and is not all that important to begin with, I'm >>> thinking it's best to wait until we can change the IR and do it >>> right. Thoughts? >> >> From the current SelectionDAG you can get a pointer to the Function >> object, which should have the attribute. Lowering for an ISD::RET >> can thus getting it from following this chain, > > I know, I just don't think that's the right way to do it. Why not? -Chris From isanbard at gmail.com Wed Feb 6 13:05:56 2008 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 06 Feb 2008 19:05:56 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r46820 - /llvm-gcc-4.2/trunk/gcc/varasm.c Message-ID: <200802061905.m16J5uql029640@zion.cs.uiuc.edu> Author: void Date: Wed Feb 6 13:05:56 2008 New Revision: 46820 URL: http://llvm.org/viewvc/llvm-project?rev=46820&view=rev Log: I meant to retain the behavior when ENABLE_LLVM wasn't defined, but not output to the ASM file. My patch was wrong because it issued the warning unconditionally when ENABLE_LLVM was defined. This should enable the old behavior when ENABLE_LLVM is undefined and give us the warning when HAVE_GAS_HIDDEN isn't defined. Modified: llvm-gcc-4.2/trunk/gcc/varasm.c Modified: llvm-gcc-4.2/trunk/gcc/varasm.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/varasm.c?rev=46820&r1=46819&r2=46820&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/varasm.c (original) +++ llvm-gcc-4.2/trunk/gcc/varasm.c Wed Feb 6 13:05:56 2008 @@ -5316,10 +5316,13 @@ type = visibility_types[vis]; -#if !defined(ENABLE_LLVM) && defined(HAVE_GAS_HIDDEN) +#ifdef HAVE_GAS_HIDDEN +#ifndef ENABLE_LLVM fprintf (asm_out_file, "\t.%s\t", type); assemble_name (asm_out_file, name); fprintf (asm_out_file, "\n"); + /* LLVM LOCAL */ +#endif #else warning (OPT_Wattributes, "visibility attribute not supported " "in this configuration; ignored"); From dalej at apple.com Wed Feb 6 13:07:12 2008 From: dalej at apple.com (Dale Johannesen) Date: Wed, 6 Feb 2008 11:07:12 -0800 Subject: [llvm-commits] [llvm] r46764 - in /llvm/trunk: include/llvm/CallingConv.h lib/Target/X86/X86CallingConv.td lib/Target/X86/X86ISelLowering.cpp In-Reply-To: References: <200802052046.m15KkXq0016743@zion.cs.uiuc.edu> <0D34AD0E-E368-4E71-9E90-345AFC264D83@apple.com> <61A65A2A-8D56-4CAA-8A0A-095A85626BB5@apple.com> <9624F9F3-E870-4832-BAA0-4591C872DC0D@apple.com> <4A426418-DFAF-4344-AA68-BF5121A88514@apple.com> Message-ID: <0E37AD98-1897-4AC7-A202-9FFB8223B6C9@apple.com> On Feb 6, 2008, at 10:48 AM, Chris Lattner wrote: >>>> Attaching this to the Function node went smoothly enough, but I >>>> actually need it on the Return node, which it appears isn't >>>> supported in the current IR, but is in the the machine-level RET >>>> node. I could transfer the info from the Function node to the RET >>>> node at some point, or even reference the Function node from the >>>> code that handles RET I suppose, but it seems cleaner to change the >>>> IR; which would break binary compatibility. Considering that this >>>> works as is and is not all that important to begin with, I'm >>>> thinking it's best to wait until we can change the IR and do it >>>> right. Thoughts? >>> >>> From the current SelectionDAG you can get a pointer to the Function >>> object, which should have the attribute. Lowering for an ISD::RET >>> can thus getting it from following this chain, >> >> I know, I just don't think that's the right way to do it. > > Why not? Everywhere else we use ParamAttrs they're on the node where you need them. We could make the actual parameters get them from the callee prototype too, but we don't do that, we put the attributes right on the actual parameters. From clattner at apple.com Wed Feb 6 13:11:07 2008 From: clattner at apple.com (Chris Lattner) Date: Wed, 6 Feb 2008 11:11:07 -0800 Subject: [llvm-commits] [llvm] r46764 - in /llvm/trunk: include/llvm/CallingConv.h lib/Target/X86/X86CallingConv.td lib/Target/X86/X86ISelLowering.cpp In-Reply-To: <0E37AD98-1897-4AC7-A202-9FFB8223B6C9@apple.com> References: <200802052046.m15KkXq0016743@zion.cs.uiuc.edu> <0D34AD0E-E368-4E71-9E90-345AFC264D83@apple.com> <61A65A2A-8D56-4CAA-8A0A-095A85626BB5@apple.com> <9624F9F3-E870-4832-BAA0-4591C872DC0D@apple.com> <4A426418-DFAF-4344-AA68-BF5121A88514@apple.com> <0E37AD98-1897-4AC7-A202-9FFB8223B6C9@apple.com> Message-ID: >>>> From the current SelectionDAG you can get a pointer to the Function >>>> object, which should have the attribute. Lowering for an ISD::RET >>>> can thus getting it from following this chain, >>> >>> I know, I just don't think that's the right way to do it. >> >> Why not? > > Everywhere else we use ParamAttrs they're on the node where you need > them. We could make the actual parameters get them from the callee > prototype too, but we don't do that, we put the attributes right on > the actual parameters. Is that also true for sext/zext attributes on the result? Inreg seems like a very similar issue to them. -Chris From evan.cheng at apple.com Wed Feb 6 13:16:53 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 06 Feb 2008 19:16:53 -0000 Subject: [llvm-commits] [llvm] r46821 - in /llvm/trunk: lib/CodeGen/RegAllocLocal.cpp test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll Message-ID: <200802061916.m16JGrdD029950@zion.cs.uiuc.edu> Author: evancheng Date: Wed Feb 6 13:16:53 2008 New Revision: 46821 URL: http://llvm.org/viewvc/llvm-project?rev=46821&view=rev Log: Fix a number of local register allocator issues: PR1609. Added: llvm/trunk/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll Modified: llvm/trunk/lib/CodeGen/RegAllocLocal.cpp Modified: llvm/trunk/lib/CodeGen/RegAllocLocal.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocLocal.cpp?rev=46821&r1=46820&r2=46821&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocLocal.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocLocal.cpp Wed Feb 6 13:16:53 2008 @@ -29,6 +29,7 @@ #include "llvm/ADT/IndexedMap.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/Statistic.h" +#include "llvm/ADT/STLExtras.h" #include using namespace llvm; @@ -296,16 +297,24 @@ std::pair &LastUse = getVirtRegLastUse(VirtReg); if (LastUse.first) LastUse.first->getOperand(LastUse.second).setIsKill(); - } - - // Otherwise, there is a virtual register corresponding to this physical - // register. We only need to spill it into its stack slot if it has been - // modified. - if (isVirtRegModified(VirtReg)) { + } else { + // Otherwise, there is a virtual register corresponding to this physical + // register. We only need to spill it into its stack slot if it has been + // modified. const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg); int FrameIndex = getStackSpaceFor(VirtReg, RC); DOUT << " to stack slot #" << FrameIndex; TII->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIndex, RC); + + // If the instruction reads the register that's spilled, (e.g. this can + // happen if it is a move to a physical register), then the spill + // instruction is not a kill. + if (I != MBB.end() && I->findRegisterUseOperandIdx(PhysReg) != -1) { + MachineBasicBlock::iterator StoreMI = prior(I); + int Idx = StoreMI->findRegisterUseOperandIdx(PhysReg, true); + assert(Idx != -1 && "Unrecognized spill instruction!"); + StoreMI->getOperand(Idx).setIsKill(false); + } ++NumStores; // Update statistics } @@ -494,12 +503,6 @@ // If we can fold this spill into this instruction, do so now. SmallVector Ops; Ops.push_back(OpNum); - if (MachineInstr* FMI = TII->foldMemoryOperand(MI, Ops, FrameIndex)) { - ++NumFolded; - // Update kill/dead flags. - FMI->copyKillDeadInfo(MI); - return MBB.insert(MBB.erase(MI), FMI); - } // It looks like we can't fold this virtual register load into this // instruction. Force some poor hapless value out of the register file to @@ -775,9 +778,8 @@ // Finally, if this is a noop copy instruction, zap it. unsigned SrcReg, DstReg; - if (TII.isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == DstReg) { + if (TII.isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == DstReg) MBB.erase(MI); - } } MachineBasicBlock::iterator MI = MBB.getFirstTerminator(); Added: llvm/trunk/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll?rev=46821&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll (added) +++ llvm/trunk/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll Wed Feb 6 13:16:53 2008 @@ -0,0 +1,19 @@ +; RUN: llvm-as < %s | llc -mtriple=arm-linux-gnueabi -regalloc=local +; PR1609 + + %struct.encode_aux_nearestmatch = type { i32*, i32*, i32*, i32*, i32, i32 } + %struct.encode_aux_pigeonhole = type { float, float, i32, i32, i32*, i32, i32*, i32*, i32* } + %struct.encode_aux_threshmatch = type { float*, i32*, i32, i32 } + %struct.oggpack_buffer = type { i32, i32, i8*, i8*, i32 } + %struct.static_codebook = type { i32, i32, i32*, i32, i32, i32, i32, i32, i32*, %struct.encode_aux_nearestmatch*, %struct.encode_aux_threshmatch*, %struct.encode_aux_pigeonhole*, i32 } + +define i32 @vorbis_staticbook_pack(%struct.static_codebook* %c, %struct.oggpack_buffer* %opb) { +entry: + %opb_addr = alloca %struct.oggpack_buffer* ; <%struct.oggpack_buffer**> [#uses=1] + %tmp1 = load %struct.oggpack_buffer** %opb_addr, align 4 ; <%struct.oggpack_buffer*> [#uses=1] + call void @oggpack_write( %struct.oggpack_buffer* %tmp1, i32 5653314, i32 24 ) nounwind + call void @oggpack_write( %struct.oggpack_buffer* null, i32 0, i32 24 ) nounwind + unreachable +} + +declare void @oggpack_write(%struct.oggpack_buffer*, i32, i32) From lauro.venancio at gmail.com Wed Feb 6 13:53:21 2008 From: lauro.venancio at gmail.com (Lauro Ramos Venancio) Date: Wed, 6 Feb 2008 16:53:21 -0300 Subject: [llvm-commits] [llvm] r46821 - in /llvm/trunk: lib/CodeGen/RegAllocLocal.cpp test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll In-Reply-To: <200802061916.m16JGrdD029950@zion.cs.uiuc.edu> References: <200802061916.m16JGrdD029950@zion.cs.uiuc.edu> Message-ID: <9c10c9f0802061153h6787e8ddoddcd4b2d6b732b0c@mail.gmail.com> ============================================================================== > --- llvm/trunk/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll (added) > +++ llvm/trunk/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll Wed Feb 6 13:16:53 2008 > @@ -0,0 +1,19 @@ > +; RUN: llvm-as < %s | llc -mtriple=arm-linux-gnueabi -regalloc=local > +; PR1609 > + I think it should be PR1925. Lauro From isanbard at gmail.com Wed Feb 6 14:03:07 2008 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 06 Feb 2008 20:03:07 -0000 Subject: [llvm-commits] [llvm] r46822 - in /llvm/trunk: lib/Transforms/Scalar/GVN.cpp test/Transforms/GVN/memcpy.ll Message-ID: <200802062003.m16K37Q3031580@zion.cs.uiuc.edu> Author: void Date: Wed Feb 6 14:03:07 2008 New Revision: 46822 URL: http://llvm.org/viewvc/llvm-project?rev=46822&view=rev Log: Temporarily reverting: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20080128/057882.html This is causing a miscompilation on PPC G5 and just now seeing it on iMac x86-64. Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp llvm/trunk/test/Transforms/GVN/memcpy.ll Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVN.cpp?rev=46822&r1=46821&r2=46822&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/GVN.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/GVN.cpp Wed Feb 6 14:03:07 2008 @@ -19,7 +19,6 @@ #include "llvm/Constants.h" #include "llvm/DerivedTypes.h" #include "llvm/Function.h" -#include "llvm/IntrinsicInst.h" #include "llvm/Instructions.h" #include "llvm/Value.h" #include "llvm/ADT/BitVector.h" @@ -737,7 +736,6 @@ SmallVector& toErase); bool processNonLocalLoad(LoadInst* L, SmallVector& toErase); - bool processMemCpy(MemCpyInst* M, SmallVector& toErase); Value *GetValueForBlock(BasicBlock *BB, LoadInst* orig, DenseMap &Phis, bool top_level = false); @@ -1019,84 +1017,6 @@ return deletedLoad; } -/// processMemCpy - perform simplication of memcpy's. If we have memcpy A which -/// copies X to Y, and memcpy B which copies Y to Z, then we can rewrite B to be -/// a memcpy from X to Z (or potentially a memmove, depending on circumstances). -/// This allows later passes to remove the first memcpy altogether. -bool GVN::processMemCpy(MemCpyInst* M, - SmallVector& toErase) { - MemoryDependenceAnalysis& MD = getAnalysis(); - - // First, we have to check that the dependency is another memcpy - Instruction* dep = MD.getDependency(M); - if (dep == MemoryDependenceAnalysis::None || - dep == MemoryDependenceAnalysis::NonLocal || - !isa(dep)) - return false; - - // We can only transforms memcpy's where the dest of one is the source of the - // other - MemCpyInst* MDep = cast(dep); - if (M->getSource() != MDep->getDest()) - return false; - - // Second, the length of the memcpy's must be the same, or the preceeding one - // must be larger than the following one. - Value* DepLength = MDep->getLength(); - uint64_t CpySize = ~0UL; - uint64_t DepSize = ~0UL; - if (isa(DepLength)) { - if (isa(M->getLength())) { - if (cast(DepLength)->getLimitedValue() < - cast(M->getLength())->getLimitedValue()) { - return false; - } else { - CpySize = cast(M->getLength())->getLimitedValue(); - DepSize = cast(DepLength)->getLimitedValue(); - } - } else { - return false; - } - } else { - return false; - } - - // Finally, we have to make sure that the dest of the second does not - // alias the source of the first - AliasAnalysis& AA = getAnalysis(); - if (AA.alias(M->getRawDest(), CpySize, MDep->getRawSource(), DepSize) != - AliasAnalysis::NoAlias) { - // If they don't, we can still make the transformation by first turning M - // into a memmove rather than a memcpy. - bool is32bit = M->getIntrinsicID() == Intrinsic::memcpy_i32; - Function* MemMoveFun = Intrinsic::getDeclaration( - M->getParent()->getParent()->getParent(), - is32bit ? Intrinsic::memmove_i32 : - Intrinsic::memmove_i64); - - std::vector args; - args.push_back(M->getRawDest()); - args.push_back(MDep->getRawSource()); - args.push_back(M->getLength()); - args.push_back(M->getAlignment()); - - new CallInst(MemMoveFun, args.begin(), args.end(), "", M); - - MD.removeInstruction(M); - toErase.push_back(M); - - return true; - } - - // If all checks passed, then we can transform these memcpy's - M->setSource(MDep->getRawSource()); - - // Reset dependence information for the memcpy - MD.removeInstruction(M); - - return true; -} - /// processInstruction - When calculating availability, handle an instruction /// by inserting it into the appropriate sets bool GVN::processInstruction(Instruction* I, @@ -1105,8 +1025,6 @@ SmallVector& toErase) { if (LoadInst* L = dyn_cast(I)) { return processLoad(L, lastSeenLoad, toErase); - } else if (MemCpyInst* M = dyn_cast(I)) { - return processMemCpy(M, toErase); } unsigned num = VN.lookup_or_add(I); Modified: llvm/trunk/test/Transforms/GVN/memcpy.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/GVN/memcpy.ll?rev=46822&r1=46821&r2=46822&view=diff ============================================================================== --- llvm/trunk/test/Transforms/GVN/memcpy.ll (original) +++ llvm/trunk/test/Transforms/GVN/memcpy.ll Wed Feb 6 14:03:07 2008 @@ -1,4 +1,5 @@ ; RUN: llvm-as < %s | opt -gvn -dse | llvm-dis | grep memcpy | count 2 +; XFAIL: * target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target triple = "i686-apple-darwin9" From isanbard at gmail.com Wed Feb 6 15:34:01 2008 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 06 Feb 2008 21:34:01 -0000 Subject: [llvm-commits] [llvm] r46824 - /llvm/branches/Apple/Zim/ Message-ID: <200802062134.m16LY1fp001790@zion.cs.uiuc.edu> Author: void Date: Wed Feb 6 15:34:01 2008 New Revision: 46824 URL: http://llvm.org/viewvc/llvm-project?rev=46824&view=rev Log: Creating Zim branch based on llvmCore-2015 Added: llvm/branches/Apple/Zim/ - copied from r46823, llvm/tags/Apple/llvmCore-2015/ From evan.cheng at apple.com Wed Feb 6 16:07:17 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 06 Feb 2008 22:07:17 -0000 Subject: [llvm-commits] [llvm] r46825 - /llvm/trunk/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll Message-ID: <200802062207.m16M7IXL002708@zion.cs.uiuc.edu> Author: evancheng Date: Wed Feb 6 16:07:17 2008 New Revision: 46825 URL: http://llvm.org/viewvc/llvm-project?rev=46825&view=rev Log: It's PR1925, not PR1609. Modified: llvm/trunk/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll Modified: llvm/trunk/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll?rev=46825&r1=46824&r2=46825&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll Wed Feb 6 16:07:17 2008 @@ -1,5 +1,5 @@ ; RUN: llvm-as < %s | llc -mtriple=arm-linux-gnueabi -regalloc=local -; PR1609 +; PR1925 %struct.encode_aux_nearestmatch = type { i32*, i32*, i32*, i32*, i32, i32 } %struct.encode_aux_pigeonhole = type { float, float, i32, i32, i32*, i32, i32*, i32*, i32* } From isanbard at gmail.com Wed Feb 6 16:18:16 2008 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 06 Feb 2008 22:18:16 -0000 Subject: [llvm-commits] [llvm] r46826 - in /llvm/branches/Apple/Zim: lib/Transforms/Scalar/GVN.cpp test/Transforms/GVN/memcpy.ll Message-ID: <200802062218.m16MIG0d003067@zion.cs.uiuc.edu> Author: void Date: Wed Feb 6 16:18:16 2008 New Revision: 46826 URL: http://llvm.org/viewvc/llvm-project?rev=46826&view=rev Log: [From mainline] Temporarily reverting: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20080128/057882.html This is causing a miscompilation on PPC G5 and just now seeing it on iMac x86-64. Modified: llvm/branches/Apple/Zim/lib/Transforms/Scalar/GVN.cpp llvm/branches/Apple/Zim/test/Transforms/GVN/memcpy.ll Modified: llvm/branches/Apple/Zim/lib/Transforms/Scalar/GVN.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zim/lib/Transforms/Scalar/GVN.cpp?rev=46826&r1=46825&r2=46826&view=diff ============================================================================== --- llvm/branches/Apple/Zim/lib/Transforms/Scalar/GVN.cpp (original) +++ llvm/branches/Apple/Zim/lib/Transforms/Scalar/GVN.cpp Wed Feb 6 16:18:16 2008 @@ -19,7 +19,6 @@ #include "llvm/Constants.h" #include "llvm/DerivedTypes.h" #include "llvm/Function.h" -#include "llvm/IntrinsicInst.h" #include "llvm/Instructions.h" #include "llvm/Value.h" #include "llvm/ADT/BitVector.h" @@ -737,7 +736,6 @@ SmallVector& toErase); bool processNonLocalLoad(LoadInst* L, SmallVector& toErase); - bool processMemCpy(MemCpyInst* M, SmallVector& toErase); Value *GetValueForBlock(BasicBlock *BB, LoadInst* orig, DenseMap &Phis, bool top_level = false); @@ -1019,84 +1017,6 @@ return deletedLoad; } -/// processMemCpy - perform simplication of memcpy's. If we have memcpy A which -/// copies X to Y, and memcpy B which copies Y to Z, then we can rewrite B to be -/// a memcpy from X to Z (or potentially a memmove, depending on circumstances). -/// This allows later passes to remove the first memcpy altogether. -bool GVN::processMemCpy(MemCpyInst* M, - SmallVector& toErase) { - MemoryDependenceAnalysis& MD = getAnalysis(); - - // First, we have to check that the dependency is another memcpy - Instruction* dep = MD.getDependency(M); - if (dep == MemoryDependenceAnalysis::None || - dep == MemoryDependenceAnalysis::NonLocal || - !isa(dep)) - return false; - - // We can only transforms memcpy's where the dest of one is the source of the - // other - MemCpyInst* MDep = cast(dep); - if (M->getSource() != MDep->getDest()) - return false; - - // Second, the length of the memcpy's must be the same, or the preceeding one - // must be larger than the following one. - Value* DepLength = MDep->getLength(); - uint64_t CpySize = ~0UL; - uint64_t DepSize = ~0UL; - if (isa(DepLength)) { - if (isa(M->getLength())) { - if (cast(DepLength)->getLimitedValue() < - cast(M->getLength())->getLimitedValue()) { - return false; - } else { - CpySize = cast(M->getLength())->getLimitedValue(); - DepSize = cast(DepLength)->getLimitedValue(); - } - } else { - return false; - } - } else { - return false; - } - - // Finally, we have to make sure that the dest of the second does not - // alias the source of the first - AliasAnalysis& AA = getAnalysis(); - if (AA.alias(M->getRawDest(), CpySize, MDep->getRawSource(), DepSize) != - AliasAnalysis::NoAlias) { - // If they don't, we can still make the transformation by first turning M - // into a memmove rather than a memcpy. - bool is32bit = M->getIntrinsicID() == Intrinsic::memcpy_i32; - Function* MemMoveFun = Intrinsic::getDeclaration( - M->getParent()->getParent()->getParent(), - is32bit ? Intrinsic::memmove_i32 : - Intrinsic::memmove_i64); - - std::vector args; - args.push_back(M->getRawDest()); - args.push_back(MDep->getRawSource()); - args.push_back(M->getLength()); - args.push_back(M->getAlignment()); - - new CallInst(MemMoveFun, args.begin(), args.end(), "", M); - - MD.removeInstruction(M); - toErase.push_back(M); - - return true; - } - - // If all checks passed, then we can transform these memcpy's - M->setSource(MDep->getRawSource()); - - // Reset dependence information for the memcpy - MD.removeInstruction(M); - - return true; -} - /// processInstruction - When calculating availability, handle an instruction /// by inserting it into the appropriate sets bool GVN::processInstruction(Instruction* I, @@ -1105,8 +1025,6 @@ SmallVector& toErase) { if (LoadInst* L = dyn_cast(I)) { return processLoad(L, lastSeenLoad, toErase); - } else if (MemCpyInst* M = dyn_cast(I)) { - return processMemCpy(M, toErase); } unsigned num = VN.lookup_or_add(I); Modified: llvm/branches/Apple/Zim/test/Transforms/GVN/memcpy.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zim/test/Transforms/GVN/memcpy.ll?rev=46826&r1=46825&r2=46826&view=diff ============================================================================== --- llvm/branches/Apple/Zim/test/Transforms/GVN/memcpy.ll (original) +++ llvm/branches/Apple/Zim/test/Transforms/GVN/memcpy.ll Wed Feb 6 16:18:16 2008 @@ -1,4 +1,5 @@ ; RUN: llvm-as < %s | opt -gvn -dse | llvm-dis | grep memcpy | count 2 +; XFAIL: * target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target triple = "i686-apple-darwin9" From gohman at apple.com Wed Feb 6 16:27:42 2008 From: gohman at apple.com (Dan Gohman) Date: Wed, 06 Feb 2008 22:27:42 -0000 Subject: [llvm-commits] [llvm] r46827 - in /llvm/trunk: include/llvm/ include/llvm/CodeGen/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/IA64/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/X86/ utils/TableGen/ Message-ID: <200802062227.m16MRhjU003393@zion.cs.uiuc.edu> Author: djg Date: Wed Feb 6 16:27:42 2008 New Revision: 46827 URL: http://llvm.org/viewvc/llvm-project?rev=46827&view=rev Log: Re-apply the memory operand changes, with a fix for the static initializer problem, a minor tweak to the way the DAGISelEmitter finds load/store nodes, and a renaming of the new PseudoSourceValue objects. Modified: llvm/trunk/include/llvm/CodeGen/MachineInstr.h llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h llvm/trunk/include/llvm/CodeGen/MemOperand.h llvm/trunk/include/llvm/CodeGen/PseudoSourceValue.h llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h llvm/trunk/include/llvm/CodeGen/SelectionDAG.h llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h llvm/trunk/include/llvm/Value.h llvm/trunk/lib/CodeGen/MachineInstr.cpp llvm/trunk/lib/CodeGen/PseudoSourceValue.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Modified: llvm/trunk/include/llvm/CodeGen/MachineInstr.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstr.h?rev=46827&r1=46826&r2=46827&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineInstr.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineInstr.h Wed Feb 6 16:27:42 2008 @@ -17,6 +17,7 @@ #define LLVM_CODEGEN_MACHINEINSTR_H #include "llvm/CodeGen/MachineOperand.h" +#include "llvm/CodeGen/MemOperand.h" namespace llvm { @@ -35,6 +36,7 @@ // are determined at construction time). std::vector Operands; // the operands + std::vector MemOperands; // information on memory references MachineInstr *Prev, *Next; // Links for MBB's intrusive list. MachineBasicBlock *Parent; // Pointer to the owning basic block. @@ -94,6 +96,18 @@ /// unsigned getNumExplicitOperands() const; + /// Access to memory operands of the instruction + unsigned getNumMemOperands() const { return MemOperands.size(); } + + const MemOperand& getMemOperand(unsigned i) const { + assert(i < getNumMemOperands() && "getMemOperand() out of range!"); + return MemOperands[i]; + } + MemOperand& getMemOperand(unsigned i) { + assert(i < getNumMemOperands() && "getMemOperand() out of range!"); + return MemOperands[i]; + } + /// isIdenticalTo - Return true if this instruction is identical to (same /// opcode and same operands as) the specified instruction. bool isIdenticalTo(const MachineInstr *Other) const { @@ -196,6 +210,12 @@ /// void RemoveOperand(unsigned i); + /// addMemOperand - Add a MemOperand to the machine instruction, referencing + /// arbitrary storage. + void addMemOperand(const MemOperand &MO) { + MemOperands.push_back(MO); + } + private: /// getRegInfo - If this instruction is embedded into a MachineFunction, /// return the MachineRegisterInfo object for the current function, otherwise Modified: llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h?rev=46827&r1=46826&r2=46827&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h Wed Feb 6 16:27:42 2008 @@ -83,6 +83,12 @@ MI->addOperand(MachineOperand::CreateES(FnName, 0)); return *this; } + + /// addMemOperand - Add a memory operand to the machine instruction. + const MachineInstrBuilder &addMemOperand(const MemOperand &MO) const { + MI->addMemOperand(MO); + return *this; + } }; /// BuildMI - Builder interface. Specify how to create the initial instruction Modified: llvm/trunk/include/llvm/CodeGen/MemOperand.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MemOperand.h?rev=46827&r1=46826&r2=46827&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MemOperand.h (original) +++ llvm/trunk/include/llvm/CodeGen/MemOperand.h Wed Feb 6 16:27:42 2008 @@ -0,0 +1,82 @@ +//===-- llvm/CodeGen/MemOperand.h - MemOperand class ------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the declaration of the MemOperand class, which is a +// description of a memory reference. It is used to help track dependencies +// in the backend. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CODEGEN_MEMOPERAND_H +#define LLVM_CODEGEN_MEMOPERAND_H + +namespace llvm { + +class Value; + +//===----------------------------------------------------------------------===// +/// MemOperand - A description of a memory reference used in the backend. +/// Instead of holding a StoreInst or LoadInst, this class holds the address +/// Value of the reference along with a byte size and offset. This allows it +/// to describe lowered loads and stores. Also, the special PseudoSourceValue +/// objects can be used to represent loads and stores to memory locations +/// that aren't explicit in the regular LLVM IR. +/// +class MemOperand { + const Value *V; + unsigned int Flags; + int Offset; + int Size; + unsigned int Alignment; + +public: + /// Flags values. These may be or'd together. + enum MemOperandFlags { + /// The memory access reads data. + MOLoad = 1, + /// The memory access writes data. + MOStore = 2, + /// The memory access is volatile. + MOVolatile = 4 + }; + + /// MemOperand - Construct an MemOperand object with the specified + /// address Value, flags, offset, size, and alignment. + MemOperand(const Value *v, unsigned int f, int o, int s, unsigned int a) + : V(v), Flags(f), Offset(o), Size(s), Alignment(a) {} + + /// getValue - Return the base address of the memory access. + /// Special values are PseudoSourceValue::FPRel, PseudoSourceValue::SPRel, + /// and the other PseudoSourceValue members which indicate references to + /// frame/stack pointer relative references and other special references. + const Value *getValue() const { return V; } + + /// getFlags - Return the raw flags of the source value, \see MemOperandFlags. + unsigned int getFlags() const { return Flags; } + + /// getOffset - For normal values, this is a byte offset added to the base + /// address. For PseudoSourceValue::FPRel values, this is the FrameIndex + /// number. + int getOffset() const { return Offset; } + + /// getSize - Return the size in bytes of the memory reference. + int getSize() const { return Size; } + + /// getAlignment - Return the minimum known alignment in bytes of the + /// memory reference. + unsigned int getAlignment() const { return Alignment; } + + bool isLoad() const { return Flags & MOLoad; } + bool isStore() const { return Flags & MOStore; } + bool isVolatile() const { return Flags & MOVolatile; } +}; + +} // End llvm namespace + +#endif Modified: llvm/trunk/include/llvm/CodeGen/PseudoSourceValue.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/PseudoSourceValue.h?rev=46827&r1=46826&r2=46827&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/PseudoSourceValue.h (original) +++ llvm/trunk/include/llvm/CodeGen/PseudoSourceValue.h Wed Feb 6 16:27:42 2008 @@ -0,0 +1,58 @@ +//===-- llvm/CodeGen/PseudoSourceValue.h ------------------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the declaration of the PseudoSourceValue class. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CODEGEN_PSEUDOSOURCEVALUE_H +#define LLVM_CODEGEN_PSEUDOSOURCEVALUE_H + +#include "llvm/Value.h" + +namespace llvm { + /// PseudoSourceValue - Special value supplied for machine level alias + /// analysis. It indicates that the a memory access references the functions + /// stack frame (e.g., a spill slot), below the stack frame (e.g., argument + /// space), or constant pool. + class PseudoSourceValue : public Value { + public: + PseudoSourceValue(); + + virtual void print(std::ostream &OS) const; + + /// classof - Methods for support type inquiry through isa, cast, and + /// dyn_cast: + /// + static inline bool classof(const PseudoSourceValue *) { return true; } + static inline bool classof(const Value *V) { + return V->getValueID() == PseudoSourceValueVal; + } + + /// A pseudo source value referencing to the stack frame of a function, + /// e.g., a spill slot. + static const PseudoSourceValue &getFixedStack(); + + /// A source value referencing the area below the stack frame of a function, + /// e.g., the argument space. + static const PseudoSourceValue &getStack(); + + /// A source value referencing the global offset table (or something the + /// like). + static const PseudoSourceValue &getGOT(); + + /// A SV referencing the constant pool + static const PseudoSourceValue &getConstantPool(); + + /// A SV referencing the jump table + static const PseudoSourceValue &getJumpTable(); + }; +} // End llvm namespace + +#endif Modified: llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h?rev=46827&r1=46826&r2=46827&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h (original) +++ llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h Wed Feb 6 16:27:42 2008 @@ -279,6 +279,7 @@ if (isa(Node)) return true; if (isa(Node)) return true; if (isa(Node)) return true; + if (isa(Node)) return true; return false; } @@ -312,11 +313,15 @@ /// (which do not go into the machine instrs.) static unsigned CountResults(SDNode *Node); - /// CountOperands The inputs to target nodes have any actual inputs first, - /// followed by an optional chain operand, then flag operands. Compute the - /// number of actual operands that will go into the machine instr. + /// CountOperands - The inputs to target nodes have any actual inputs first, + /// followed by optional memory operands chain operand, then flag operands. + /// Compute the number of actual operands that will go into the machine + /// instr. static unsigned CountOperands(SDNode *Node); + /// CountMemOperands - Find the index of the last MemOperandSDNode + static unsigned CountMemOperands(SDNode *Node); + /// EmitNode - Generate machine code for an node and needed dependencies. /// VRBaseMap contains, for each already emitted node, the first virtual /// register number for the results of the node. @@ -357,6 +362,8 @@ void AddOperand(MachineInstr *MI, SDOperand Op, unsigned IIOpNum, const TargetInstrDesc *II, DenseMap &VRBaseMap); + + void AddMemOperand(MachineInstr *MI, const MemOperand &MO); }; /// createBURRListDAGScheduler - This creates a bottom up register usage Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=46827&r1=46826&r2=46827&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Wed Feb 6 16:27:42 2008 @@ -376,8 +376,12 @@ SDOperand getIndexedStore(SDOperand OrigStoe, SDOperand Base, SDOperand Offset, ISD::MemIndexedMode AM); - // getSrcValue - construct a node to track a Value* through the backend - SDOperand getSrcValue(const Value* I, int offset = 0); + // getSrcValue - Construct a node to track a Value* through the backend. + SDOperand getSrcValue(const Value *v); + + // getMemOperand - Construct a node to track a memory reference + // through the backend. + SDOperand getMemOperand(const MemOperand &MO); /// UpdateNodeOperands - *Mutate* the specified node in-place to have the /// specified operands. If the resultant node already exists in the DAG, Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=46827&r1=46826&r2=46827&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Wed Feb 6 16:27:42 2008 @@ -25,6 +25,7 @@ #include "llvm/ADT/iterator" #include "llvm/ADT/APFloat.h" #include "llvm/CodeGen/ValueTypes.h" +#include "llvm/CodeGen/MemOperand.h" #include "llvm/Support/DataTypes.h" #include @@ -542,11 +543,15 @@ // pointer, and a SRCVALUE. VAEND, VASTART, - // SRCVALUE - This corresponds to a Value*, and is used to associate memory - // locations with their value. This allows one use alias analysis - // information in the backend. + // SRCVALUE - This is a node type that holds a Value* that is used to + // make reference to a value in the LLVM IR. SRCVALUE, + // MEMOPERAND - This is a node that contains a MemOperand which records + // information about a memory reference. This is used to make AliasAnalysis + // queries from the backend. + MEMOPERAND, + // PCMARKER - This corresponds to the pcmarker intrinsic. PCMARKER, @@ -1391,17 +1396,16 @@ class SrcValueSDNode : public SDNode { const Value *V; - int offset; virtual void ANCHOR(); // Out-of-line virtual method to give class a home. protected: friend class SelectionDAG; - SrcValueSDNode(const Value* v, int o) - : SDNode(ISD::SRCVALUE, getSDVTList(MVT::Other)), V(v), offset(o) { - } + /// Create a SrcValue for a general value. + explicit SrcValueSDNode(const Value *v) + : SDNode(ISD::SRCVALUE, getSDVTList(MVT::Other)), V(v) {} public: + /// getValue - return the contained Value. const Value *getValue() const { return V; } - int getOffset() const { return offset; } static bool classof(const SrcValueSDNode *) { return true; } static bool classof(const SDNode *N) { @@ -1410,6 +1414,29 @@ }; +/// MemOperandSDNode - An SDNode that holds a MemOperand. This is +/// used to represent a reference to memory after ISD::LOAD +/// and ISD::STORE have been lowered. +/// +class MemOperandSDNode : public SDNode { + virtual void ANCHOR(); // Out-of-line virtual method to give class a home. +protected: + friend class SelectionDAG; + /// Create a MemOperand node + explicit MemOperandSDNode(MemOperand mo) + : SDNode(ISD::MEMOPERAND, getSDVTList(MVT::Other)), MO(mo) {} + +public: + /// MO - The contained MemOperand. + const MemOperand MO; + + static bool classof(const MemOperandSDNode *) { return true; } + static bool classof(const SDNode *N) { + return N->getOpcode() == ISD::MEMOPERAND; + } +}; + + class RegisterSDNode : public SDNode { unsigned Reg; virtual void ANCHOR(); // Out-of-line virtual method to give class a home. @@ -1559,6 +1586,10 @@ /// isUnindexed - Return true if this is NOT a pre/post inc/dec load/store. bool isUnindexed() const { return AddrMode == ISD::UNINDEXED; } + /// getMemOperand - Return a MemOperand object describing the memory + /// reference performed by this load or store. + MemOperand getMemOperand() const; + static bool classof(const LSBaseSDNode *N) { return true; } static bool classof(const SDNode *N) { return N->getOpcode() == ISD::LOAD || Modified: llvm/trunk/include/llvm/Value.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Value.h?rev=46827&r1=46826&r2=46827&view=diff ============================================================================== --- llvm/trunk/include/llvm/Value.h (original) +++ llvm/trunk/include/llvm/Value.h Wed Feb 6 16:27:42 2008 @@ -187,6 +187,7 @@ ConstantVectorVal, // This is an instance of ConstantVector ConstantPointerNullVal, // This is an instance of ConstantPointerNull InlineAsmVal, // This is an instance of InlineAsm + PseudoSourceValueVal, // This is an instance of PseudoSourceValue InstructionVal, // This is an instance of Instruction // Markers: Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=46827&r1=46826&r2=46827&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Wed Feb 6 16:27:42 2008 @@ -15,6 +15,8 @@ #include "llvm/Value.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/PseudoSourceValue.h" +#include "llvm/CodeGen/SelectionDAGNodes.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetInstrDesc.h" @@ -292,6 +294,7 @@ TID = &MI.getDesc(); NumImplicitOps = MI.NumImplicitOps; Operands.reserve(MI.getNumOperands()); + MemOperands = MI.MemOperands; // Add operands for (unsigned i = 0; i != MI.getNumOperands(); ++i) { @@ -627,6 +630,34 @@ getOperand(i).print(OS, TM); } + if (getNumMemOperands() > 0) { + OS << ", SV:"; + for (unsigned i = 0; i < getNumMemOperands(); i++) { + const MemOperand &MRO = getMemOperand(i); + const Value *V = MRO.getValue(); + + assert(V && "SV missing."); + assert((MRO.isLoad() || MRO.isStore()) && + "SV has to be a load, store or both."); + + if (MRO.isVolatile()) + OS << "Volatile "; + if (MRO.isLoad()) + OS << "LD "; + if (MRO.isStore()) + OS << "ST "; + + OS << MRO.getSize(); + + if (!V->getName().empty()) + OS << "[" << V->getName() << " + " << MRO.getOffset() << "]"; + else if (isa(V)) + OS << "[" << *V << " + " << MRO.getOffset() << "]"; + else + OS << "[" << V << " + " << MRO.getOffset() << "]"; + } + } + OS << "\n"; } Modified: llvm/trunk/lib/CodeGen/PseudoSourceValue.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PseudoSourceValue.cpp?rev=46827&r1=46826&r2=46827&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PseudoSourceValue.cpp (original) +++ llvm/trunk/lib/CodeGen/PseudoSourceValue.cpp Wed Feb 6 16:27:42 2008 @@ -0,0 +1,41 @@ +//===-- llvm/CodeGen/PseudoSourceValue.cpp ----------------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file implements the PseudoSourceValue class. +// +//===----------------------------------------------------------------------===// + +#include "llvm/CodeGen/PseudoSourceValue.h" +#include "llvm/DerivedTypes.h" +#include "llvm/Support/ManagedStatic.h" + +namespace llvm { + static ManagedStatic PSVs; + + const PseudoSourceValue &PseudoSourceValue::getFixedStack() { return (*PSVs)[0]; } + const PseudoSourceValue &PseudoSourceValue::getStack() { return (*PSVs)[1]; } + const PseudoSourceValue &PseudoSourceValue::getGOT() { return (*PSVs)[2]; } + const PseudoSourceValue &PseudoSourceValue::getConstantPool() { return (*PSVs)[3]; } + const PseudoSourceValue &PseudoSourceValue::getJumpTable() { return (*PSVs)[4]; } + + static const char *PSVNames[] = { + "FixedStack", + "Stack", + "GOT", + "ConstantPool", + "JumpTable" + }; + + PseudoSourceValue::PseudoSourceValue() : + Value(PointerType::getUnqual(Type::Int8Ty), PseudoSourceValueVal) {} + + void PseudoSourceValue::print(std::ostream &OS) const { + OS << PSVNames[this - *PSVs]; + } +} Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=46827&r1=46826&r2=46827&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Feb 6 16:27:42 2008 @@ -16,6 +16,7 @@ #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineJumpTableInfo.h" #include "llvm/CodeGen/MachineModuleInfo.h" +#include "llvm/CodeGen/PseudoSourceValue.h" #include "llvm/Target/TargetFrameInfo.h" #include "llvm/Target/TargetLowering.h" #include "llvm/Target/TargetData.h" @@ -509,9 +510,11 @@ SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); if (Extend) { return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), - CPIdx, NULL, 0, MVT::f32); + CPIdx, &PseudoSourceValue::getConstantPool(), + 0, MVT::f32); } else { - return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0); + return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, + &PseudoSourceValue::getConstantPool(), 0); } } @@ -796,6 +799,7 @@ case ISD::TargetExternalSymbol: case ISD::VALUETYPE: case ISD::SRCVALUE: + case ISD::MEMOPERAND: case ISD::STRING: case ISD::CONDCODE: // Primitives must all be legal. @@ -1316,8 +1320,15 @@ MVT::ValueType IdxVT = Tmp3.getValueType(); MVT::ValueType PtrVT = TLI.getPointerTy(); SDOperand StackPtr = DAG.CreateStackTemporary(VT); + + FrameIndexSDNode *StackPtrFI = dyn_cast(StackPtr.Val); + assert(StackPtrFI); + int SPFI = StackPtrFI->getIndex(); + // Store the vector. - SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, NULL, 0); + SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, + &PseudoSourceValue::getFixedStack(), + SPFI); // Truncate or zero extend offset to target pointer type. unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; @@ -1327,9 +1338,11 @@ Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr); // Store the scalar value. - Ch = DAG.getStore(Ch, Tmp2, StackPtr2, NULL, 0); + Ch = DAG.getStore(Ch, Tmp2, StackPtr2, + &PseudoSourceValue::getFixedStack(), SPFI); // Load the updated vector. - Result = DAG.getLoad(VT, Ch, StackPtr, NULL, 0); + Result = DAG.getLoad(VT, Ch, StackPtr, + &PseudoSourceValue::getFixedStack(), SPFI); break; } } @@ -1678,8 +1691,10 @@ SDOperand LD; switch (EntrySize) { default: assert(0 && "Size of jump table not supported yet."); break; - case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, NULL, 0); break; - case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, NULL, 0); break; + case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, + &PseudoSourceValue::getJumpTable(), 0); break; + case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, + &PseudoSourceValue::getJumpTable(), 0); break; } Addr = LD; @@ -3240,16 +3255,14 @@ } break; case TargetLowering::Expand: { - SrcValueSDNode *SV = cast(Node->getOperand(2)); - SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, - SV->getValue(), SV->getOffset()); + const Value *V = cast(Node->getOperand(2))->getValue(); + SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0); // Increment the pointer, VAList, to the next vaarg Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, DAG.getConstant(MVT::getSizeInBits(VT)/8, TLI.getPointerTy())); // Store the incremented VAList to the legalized pointer - Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(), - SV->getOffset()); + Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0); // Load the actual argument out of the pointer VAList Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0); Tmp1 = LegalizeOp(Result.getValue(1)); @@ -3285,12 +3298,10 @@ case TargetLowering::Expand: // This defaults to loading a pointer from the input and storing it to the // output, returning the chain. - SrcValueSDNode *SVD = cast(Node->getOperand(3)); - SrcValueSDNode *SVS = cast(Node->getOperand(4)); - Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD->getValue(), - SVD->getOffset()); - Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, SVS->getValue(), - SVS->getOffset()); + const Value *VD = cast(Node->getOperand(3))->getValue(); + const Value *VS = cast(Node->getOperand(4))->getValue(); + Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VD, 0); + Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VS, 0); break; } break; @@ -4285,16 +4296,14 @@ Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2)); Result = TLI.CustomPromoteOperation(Tmp3, DAG); } else { - SrcValueSDNode *SV = cast(Node->getOperand(2)); - SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, - SV->getValue(), SV->getOffset()); + const Value *V = cast(Node->getOperand(2))->getValue(); + SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0); // Increment the pointer, VAList, to the next vaarg Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, DAG.getConstant(MVT::getSizeInBits(VT)/8, TLI.getPointerTy())); // Store the incremented VAList to the legalized pointer - Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(), - SV->getOffset()); + Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0); // Load the actual argument out of the pointer VAList Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT); } @@ -4750,6 +4759,10 @@ // Create the stack frame object. SDOperand FIPtr = DAG.CreateStackTemporary(SlotVT); + FrameIndexSDNode *StackPtrFI = dyn_cast(FIPtr); + assert(StackPtrFI); + int SPFI = StackPtrFI->getIndex(); + unsigned SrcSize = MVT::getSizeInBits(SrcOp.getValueType()); unsigned SlotSize = MVT::getSizeInBits(SlotVT); unsigned DestSize = MVT::getSizeInBits(DestVT); @@ -4758,10 +4771,14 @@ // later than DestVT. SDOperand Store; if (SrcSize > SlotSize) - Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0,SlotVT); + Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr, + &PseudoSourceValue::getFixedStack(), + SPFI, SlotVT); else { assert(SrcSize == SlotSize && "Invalid store"); - Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0); + Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, + &PseudoSourceValue::getFixedStack(), + SPFI, SlotVT); } // Result is a load from the stack slot. @@ -4776,9 +4793,15 @@ // Create a vector sized/aligned stack slot, store the value to element #0, // then load the whole vector back out. SDOperand StackPtr = DAG.CreateStackTemporary(Node->getValueType(0)); + + FrameIndexSDNode *StackPtrFI = dyn_cast(StackPtr); + assert(StackPtrFI); + int SPFI = StackPtrFI->getIndex(); + SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr, - NULL, 0); - return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, NULL, 0); + &PseudoSourceValue::getFixedStack(), SPFI); + return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, + &PseudoSourceValue::getFixedStack(), SPFI); } @@ -4842,7 +4865,8 @@ } Constant *CP = ConstantVector::get(CV); SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); - return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0); + return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, + &PseudoSourceValue::getConstantPool(), 0); } if (SplatValue.Val) { // Splat of one value? @@ -5184,11 +5208,14 @@ CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); SDOperand FudgeInReg; if (DestTy == MVT::f32) - FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0); + FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, + &PseudoSourceValue::getConstantPool(), 0); else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32)) // FIXME: Avoid the extend by construction the right constantpool? FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(), - CPIdx, NULL, 0, MVT::f32); + CPIdx, + &PseudoSourceValue::getConstantPool(), 0, + MVT::f32); else assert(0 && "Unexpected conversion"); @@ -5330,11 +5357,14 @@ CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); SDOperand FudgeInReg; if (DestVT == MVT::f32) - FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0); + FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, + &PseudoSourceValue::getConstantPool(), 0); else { - FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT, - DAG.getEntryNode(), CPIdx, - NULL, 0, MVT::f32)); + FudgeInReg = + LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT, + DAG.getEntryNode(), CPIdx, + &PseudoSourceValue::getConstantPool(), 0, + MVT::f32)); } return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg); @@ -6743,10 +6773,16 @@ // Lower to a store/load so that it can be split. // FIXME: this could be improved probably. SDOperand Ptr = DAG.CreateStackTemporary(InOp.getValueType()); + FrameIndexSDNode *FI = dyn_cast(Ptr.Val); + assert(FI && "Expecting CreateStackTemporary to return a frame index.\n"); SDOperand St = DAG.getStore(DAG.getEntryNode(), - InOp, Ptr, NULL, 0); - InOp = DAG.getLoad(Op.getValueType(), St, Ptr, NULL, 0); + InOp, Ptr, + &PseudoSourceValue::getFixedStack(), + FI->getIndex()); + InOp = DAG.getLoad(Op.getValueType(), St, Ptr, + &PseudoSourceValue::getFixedStack(), + FI->getIndex()); } // Split the vector and convert each of the pieces now. SplitVectorOp(InOp, Lo, Hi); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp?rev=46827&r1=46826&r2=46827&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Wed Feb 6 16:27:42 2008 @@ -277,15 +277,27 @@ return N; } -/// CountOperands The inputs to target nodes have any actual inputs first, -/// followed by an optional chain operand, then flag operands. Compute the -/// number of actual operands that will go into the machine instr. +/// CountOperands - The inputs to target nodes have any actual inputs first, +/// followed by optional memory operands chain operand, then flag operands. +/// Compute the number of actual operands that will go into the machine istr. unsigned ScheduleDAG::CountOperands(SDNode *Node) { unsigned N = Node->getNumOperands(); while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag) --N; if (N && Node->getOperand(N - 1).getValueType() == MVT::Other) --N; // Ignore chain if it exists. + while (N && MemOperandSDNode::classof(Node->getOperand(N - 1).Val)) + --N; // Ignore MemOperand nodes + return N; +} + +/// CountMemOperands - Find the index of the last MemOperandSDNode operand +unsigned ScheduleDAG::CountMemOperands(SDNode *Node) { + unsigned N = Node->getNumOperands(); + while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag) + --N; + if (N && Node->getOperand(N - 1).getValueType() == MVT::Other) + --N; // Ignore chain if it exists. return N; } @@ -517,6 +529,10 @@ } +void ScheduleDAG::AddMemOperand(MachineInstr *MI, const MemOperand &MO) { + MI->addMemOperand(MO); +} + // Returns the Register Class of a subregister static const TargetRegisterClass *getSubRegisterRegClass( const TargetRegisterClass *TRC, @@ -675,6 +691,7 @@ unsigned NumResults = CountResults(Node); unsigned NodeOperands = CountOperands(Node); + unsigned NodeMemOperands = CountMemOperands(Node); unsigned NumMIOperands = NodeOperands + NumResults; bool HasPhysRegOuts = (NumResults > II.getNumDefs()) && II.getImplicitDefs() != 0; @@ -697,6 +714,10 @@ for (unsigned i = 0; i != NodeOperands; ++i) AddOperand(MI, Node->getOperand(i), i+II.getNumDefs(), &II, VRBaseMap); + // Emit all of the memory operands of this instruction + for (unsigned i = NodeOperands; i != NodeMemOperands; ++i) + AddMemOperand(MI, cast(Node->getOperand(i))->MO); + // Commute node if it has been determined to be profitable. if (CommuteSet.count(Node)) { MachineInstr *NewMI = TII->commuteInstruction(MI); @@ -737,6 +758,7 @@ case ISD::TokenFactor: case ISD::LABEL: case ISD::DECLARE: + case ISD::SRCVALUE: break; case ISD::CopyToReg: { unsigned InReg; Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=46827&r1=46826&r2=46827&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Feb 6 16:27:42 2008 @@ -21,6 +21,7 @@ #include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineModuleInfo.h" +#include "llvm/CodeGen/PseudoSourceValue.h" #include "llvm/Support/MathExtras.h" #include "llvm/Target/MRegisterInfo.h" #include "llvm/Target/TargetData.h" @@ -361,10 +362,16 @@ case ISD::Register: ID.AddInteger(cast(N)->getReg()); break; - case ISD::SRCVALUE: { - SrcValueSDNode *SV = cast(N); - ID.AddPointer(SV->getValue()); - ID.AddInteger(SV->getOffset()); + case ISD::SRCVALUE: + ID.AddPointer(cast(N)->getValue()); + break; + case ISD::MEMOPERAND: { + const MemOperand &MO = cast(N)->MO; + ID.AddPointer(MO.getValue()); + ID.AddInteger(MO.getFlags()); + ID.AddInteger(MO.getOffset()); + ID.AddInteger(MO.getSize()); + ID.AddInteger(MO.getAlignment()); break; } case ISD::FrameIndex: @@ -937,18 +944,42 @@ return SDOperand(N, 0); } -SDOperand SelectionDAG::getSrcValue(const Value *V, int Offset) { +SDOperand SelectionDAG::getSrcValue(const Value *V) { assert((!V || isa(V->getType())) && "SrcValue is not a pointer?"); FoldingSetNodeID ID; AddNodeIDNode(ID, ISD::SRCVALUE, getVTList(MVT::Other), 0, 0); ID.AddPointer(V); - ID.AddInteger(Offset); + void *IP = 0; if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) return SDOperand(E, 0); - SDNode *N = new SrcValueSDNode(V, Offset); + + SDNode *N = new SrcValueSDNode(V); + CSEMap.InsertNode(N, IP); + AllNodes.push_back(N); + return SDOperand(N, 0); +} + +SDOperand SelectionDAG::getMemOperand(const MemOperand &MO) { + const Value *v = MO.getValue(); + assert((!v || isa(v->getType())) && + "SrcValue is not a pointer?"); + + FoldingSetNodeID ID; + AddNodeIDNode(ID, ISD::MEMOPERAND, getVTList(MVT::Other), 0, 0); + ID.AddPointer(v); + ID.AddInteger(MO.getFlags()); + ID.AddInteger(MO.getOffset()); + ID.AddInteger(MO.getSize()); + ID.AddInteger(MO.getAlignment()); + + void *IP = 0; + if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) + return SDOperand(E, 0); + + SDNode *N = new MemOperandSDNode(MO); CSEMap.InsertNode(N, IP); AllNodes.push_back(N); return SDOperand(N, 0); @@ -3479,6 +3510,7 @@ void ConstantPoolSDNode::ANCHOR() {} void BasicBlockSDNode::ANCHOR() {} void SrcValueSDNode::ANCHOR() {} +void MemOperandSDNode::ANCHOR() {} void RegisterSDNode::ANCHOR() {} void ExternalSymbolSDNode::ANCHOR() {} void CondCodeSDNode::ANCHOR() {} @@ -3503,6 +3535,26 @@ TheGlobal = const_cast(GA); } +/// getMemOperand - Return a MemOperand object describing the memory +/// reference performed by this load or store. +MemOperand LSBaseSDNode::getMemOperand() const { + int Size = (MVT::getSizeInBits(getMemoryVT()) + 7) >> 3; + int Flags = + getOpcode() == ISD::LOAD ? MemOperand::MOLoad : MemOperand::MOStore; + if (IsVolatile) Flags |= MemOperand::MOVolatile; + + // Check if the load references a frame index, and does not have + // an SV attached. + const FrameIndexSDNode *FI = + dyn_cast(getBasePtr().Val); + if (!getSrcValue() && FI) + return MemOperand(&PseudoSourceValue::getFixedStack(), Flags, + FI->getIndex(), Size, Alignment); + else + return MemOperand(getSrcValue(), Flags, + getSrcValueOffset(), Size, Alignment); +} + /// Profile - Gather unique data for the node. /// void SDNode::Profile(FoldingSetNodeID &ID) { @@ -3695,6 +3747,7 @@ case ISD::PCMARKER: return "PCMarker"; case ISD::READCYCLECOUNTER: return "ReadCycleCounter"; case ISD::SRCVALUE: return "SrcValue"; + case ISD::MEMOPERAND: return "MemOperand"; case ISD::EntryToken: return "EntryToken"; case ISD::TokenFactor: return "TokenFactor"; case ISD::AssertSext: return "AssertSext"; @@ -4000,9 +4053,14 @@ cerr << "'" << ES->getSymbol() << "'"; } else if (const SrcValueSDNode *M = dyn_cast(this)) { if (M->getValue()) - cerr << "<" << M->getValue() << ":" << M->getOffset() << ">"; + cerr << "<" << M->getValue() << ">"; + else + cerr << ""; + } else if (const MemOperandSDNode *M = dyn_cast(this)) { + if (M->MO.getValue()) + cerr << "<" << M->MO.getValue() << ":" << M->MO.getOffset() << ">"; else - cerr << "getOffset() << ">"; + cerr << "MO.getOffset() << ">"; } else if (const VTSDNode *N = dyn_cast(this)) { cerr << ":" << MVT::getValueTypeString(N->getVT()); } else if (const LoadSDNode *LD = dyn_cast(this)) { Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp?rev=46827&r1=46826&r2=46827&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp Wed Feb 6 16:27:42 2008 @@ -142,9 +142,14 @@ Op += "'" + std::string(ES->getSymbol()) + "'"; } else if (const SrcValueSDNode *M = dyn_cast(Node)) { if (M->getValue()) - Op += "<" + M->getValue()->getName() + ":" + itostr(M->getOffset()) + ">"; + Op += "<" + M->getValue()->getName() + ">"; else - Op += "getOffset()) + ">"; + Op += ""; + } else if (const MemOperandSDNode *M = dyn_cast(Node)) { + if (M->MO.getValue()) + Op += "<" + M->MO.getValue()->getName() + ":" + itostr(M->MO.getOffset()) + ">"; + else + Op += "MO.getOffset()) + ">"; } else if (const VTSDNode *N = dyn_cast(Node)) { Op = Op + " VT=" + MVT::getValueTypeString(N->getVT()); } else if (const StringSDNode *N = dyn_cast(Node)) { Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=46827&r1=46826&r2=46827&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Feb 6 16:27:42 2008 @@ -905,9 +905,8 @@ // memory location argument. MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); - SrcValueSDNode *SV = cast(Op.getOperand(2)); - return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV->getValue(), - SV->getOffset()); + const Value *SV = cast(Op.getOperand(2))->getValue(); + return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0); } static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG, Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp?rev=46827&r1=46826&r2=46827&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp Wed Feb 6 16:27:42 2008 @@ -491,10 +491,9 @@ case ISD::VAARG: { SDOperand Chain = Op.getOperand(0); SDOperand VAListP = Op.getOperand(1); - SrcValueSDNode *VAListS = cast(Op.getOperand(2)); + const Value *VAListS = cast(Op.getOperand(2))->getValue(); - SDOperand Base = DAG.getLoad(MVT::i64, Chain, VAListP, VAListS->getValue(), - VAListS->getOffset()); + SDOperand Base = DAG.getLoad(MVT::i64, Chain, VAListP, VAListS, 0); SDOperand Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP, DAG.getConstant(8, MVT::i64)); SDOperand Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1), @@ -527,13 +526,11 @@ SDOperand Chain = Op.getOperand(0); SDOperand DestP = Op.getOperand(1); SDOperand SrcP = Op.getOperand(2); - SrcValueSDNode *DestS = cast(Op.getOperand(3)); - SrcValueSDNode *SrcS = cast(Op.getOperand(4)); + const Value *DestS = cast(Op.getOperand(3))->getValue(); + const Value *SrcS = cast(Op.getOperand(4))->getValue(); - SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP, - SrcS->getValue(), SrcS->getOffset()); - SDOperand Result = DAG.getStore(Val.getValue(1), Val, DestP, DestS->getValue(), - DestS->getOffset()); + SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP, SrcS, 0); + SDOperand Result = DAG.getStore(Val.getValue(1), Val, DestP, DestS, 0); SDOperand NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP, DAG.getConstant(8, MVT::i64)); Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP, NULL,0, MVT::i32); @@ -544,12 +541,11 @@ case ISD::VASTART: { SDOperand Chain = Op.getOperand(0); SDOperand VAListP = Op.getOperand(1); - SrcValueSDNode *VAListS = cast(Op.getOperand(2)); + const Value *VAListS = cast(Op.getOperand(2))->getValue(); // vastart stores the address of the VarArgsBase and VarArgsOffset SDOperand FR = DAG.getFrameIndex(VarArgsBase, MVT::i64); - SDOperand S1 = DAG.getStore(Chain, FR, VAListP, VAListS->getValue(), - VAListS->getOffset()); + SDOperand S1 = DAG.getStore(Chain, FR, VAListP, VAListS, 0); SDOperand SA2 = DAG.getNode(ISD::ADD, MVT::i64, VAListP, DAG.getConstant(8, MVT::i64)); return DAG.getTruncStore(S1, DAG.getConstant(VarArgsOffset, MVT::i64), Modified: llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp?rev=46827&r1=46826&r2=46827&view=diff ============================================================================== --- llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp Wed Feb 6 16:27:42 2008 @@ -581,16 +581,16 @@ } case ISD::VAARG: { MVT::ValueType VT = getPointerTy(); - SrcValueSDNode *SV = cast(Op.getOperand(2)); + const Value *SV = cast(Op.getOperand(2))->getValue(); SDOperand VAList = DAG.getLoad(VT, Op.getOperand(0), Op.getOperand(1), - SV->getValue(), SV->getOffset()); + SV, 0); // Increment the pointer, VAList, to the next vaarg SDOperand VAIncr = DAG.getNode(ISD::ADD, VT, VAList, DAG.getConstant(MVT::getSizeInBits(VT)/8, VT)); // Store the incremented VAList to the legalized pointer VAIncr = DAG.getStore(VAList.getValue(1), VAIncr, - Op.getOperand(1), SV->getValue(), SV->getOffset()); + Op.getOperand(1), SV, 0); // Load the actual argument out of the pointer VAList return DAG.getLoad(Op.getValueType(), VAIncr, VAList, NULL, 0); } @@ -598,9 +598,8 @@ // vastart just stores the address of the VarArgsFrameIndex slot into the // memory location argument. SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i64); - SrcValueSDNode *SV = cast(Op.getOperand(2)); - return DAG.getStore(Op.getOperand(0), FR, - Op.getOperand(1), SV->getValue(), SV->getOffset()); + const Value *SV = cast(Op.getOperand(2))->getValue(); + return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0); } // Frame & Return address. Currently unimplemented case ISD::RETURNADDR: break; Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=46827&r1=46826&r2=46827&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Wed Feb 6 16:27:42 2008 @@ -24,6 +24,7 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/PseudoSourceValue.h" #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/Constants.h" #include "llvm/Function.h" @@ -1175,9 +1176,8 @@ // memory location argument. MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); - SrcValueSDNode *SV = cast(Op.getOperand(2)); - return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV->getValue(), - SV->getOffset()); + const Value *SV = cast(Op.getOperand(2))->getValue(); + return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0); } // For ELF 32 ABI we follow the layout of the va_list struct. @@ -1211,37 +1211,41 @@ MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); - SDOperand StackOffset = DAG.getFrameIndex(VarArgsStackOffset, PtrVT); + SDOperand StackOffsetFI = DAG.getFrameIndex(VarArgsStackOffset, PtrVT); SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); - SDOperand ConstFrameOffset = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, - PtrVT); - SDOperand ConstStackOffset = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8 - 1, - PtrVT); - SDOperand ConstFPROffset = DAG.getConstant(1, PtrVT); + uint64_t FrameOffset = MVT::getSizeInBits(PtrVT)/8; + SDOperand ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT); + + uint64_t StackOffset = MVT::getSizeInBits(PtrVT)/8 - 1; + SDOperand ConstStackOffset = DAG.getConstant(StackOffset, PtrVT); + + uint64_t FPROffset = 1; + SDOperand ConstFPROffset = DAG.getConstant(FPROffset, PtrVT); - SrcValueSDNode *SV = cast(Op.getOperand(2)); + const Value *SV = cast(Op.getOperand(2))->getValue(); // Store first byte : number of int regs SDOperand firstStore = DAG.getStore(Op.getOperand(0), ArgGPR, - Op.getOperand(1), SV->getValue(), - SV->getOffset()); + Op.getOperand(1), SV, 0); + uint64_t nextOffset = FPROffset; SDOperand nextPtr = DAG.getNode(ISD::ADD, PtrVT, Op.getOperand(1), ConstFPROffset); // Store second byte : number of float regs - SDOperand secondStore = DAG.getStore(firstStore, ArgFPR, nextPtr, - SV->getValue(), SV->getOffset()); + SDOperand secondStore = + DAG.getStore(firstStore, ArgFPR, nextPtr, SV, nextOffset); + nextOffset += StackOffset; nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstStackOffset); // Store second word : arguments given on stack - SDOperand thirdStore = DAG.getStore(secondStore, StackOffset, nextPtr, - SV->getValue(), SV->getOffset()); + SDOperand thirdStore = + DAG.getStore(secondStore, StackOffsetFI, nextPtr, SV, nextOffset); + nextOffset += FrameOffset; nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstFrameOffset); // Store third word : arguments given in registers - return DAG.getStore(thirdStore, FR, nextPtr, SV->getValue(), - SV->getOffset()); + return DAG.getStore(thirdStore, FR, nextPtr, SV, nextOffset); } @@ -2199,9 +2203,11 @@ Op.getOperand(0)); // STD the extended value into the stack slot. + MemOperand MO(&PseudoSourceValue::getFixedStack(), + MemOperand::MOStore, FrameIdx, 8, 8); SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other, DAG.getEntryNode(), Ext64, FIdx, - DAG.getSrcValue(NULL)); + DAG.getMemOperand(MO)); // Load the value as a double. SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0); @@ -3300,11 +3306,11 @@ std::vector VTs; VTs.push_back(MVT::i32); VTs.push_back(MVT::Other); - SDOperand SV = DAG.getSrcValue(LD->getSrcValue(), LD->getSrcValueOffset()); + SDOperand MO = DAG.getMemOperand(LD->getMemOperand()); SDOperand Ops[] = { LD->getChain(), // Chain LD->getBasePtr(), // Ptr - SV, // SrcValue + MO, // MemOperand DAG.getValueType(N->getValueType(0)) // VT }; SDOperand BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4); Modified: llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp?rev=46827&r1=46826&r2=46827&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp Wed Feb 6 16:27:42 2008 @@ -805,25 +805,23 @@ SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32, DAG.getRegister(SP::I6, MVT::i32), DAG.getConstant(VarArgsFrameOffset, MVT::i32)); - SrcValueSDNode *SV = cast(Op.getOperand(2)); - return DAG.getStore(Op.getOperand(0), Offset, - Op.getOperand(1), SV->getValue(), SV->getOffset()); + const Value *SV = cast(Op.getOperand(2))->getValue(); + return DAG.getStore(Op.getOperand(0), Offset, Op.getOperand(1), SV, 0); } case ISD::VAARG: { SDNode *Node = Op.Val; MVT::ValueType VT = Node->getValueType(0); SDOperand InChain = Node->getOperand(0); SDOperand VAListPtr = Node->getOperand(1); - SrcValueSDNode *SV = cast(Node->getOperand(2)); - SDOperand VAList = DAG.getLoad(getPointerTy(), InChain, VAListPtr, - SV->getValue(), SV->getOffset()); + const Value *SV = cast(Node->getOperand(2))->getValue(); + SDOperand VAList = DAG.getLoad(getPointerTy(), InChain, VAListPtr, SV, 0); // Increment the pointer, VAList, to the next vaarg SDOperand NextPtr = DAG.getNode(ISD::ADD, getPointerTy(), VAList, DAG.getConstant(MVT::getSizeInBits(VT)/8, getPointerTy())); // Store the incremented VAList to the legalized pointer InChain = DAG.getStore(VAList.getValue(1), NextPtr, - VAListPtr, SV->getValue(), SV->getOffset()); + VAListPtr, SV, 0); // Load the actual argument out of the pointer VAList, unless this is an // f64 load. if (VT != MVT::f64) { Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=46827&r1=46826&r2=46827&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Feb 6 16:27:42 2008 @@ -32,6 +32,7 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/PseudoSourceValue.h" #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/Debug.h" @@ -1089,7 +1090,8 @@ SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy()); if (isByVal) return FIN; - return DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0); + return DAG.getLoad(VA.getValVT(), Root, FIN, + &PseudoSourceValue::getFixedStack(), FI); } SDOperand @@ -1217,7 +1219,10 @@ unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs], X86::GR64RegisterClass); SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i64); - SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); + SDOperand Store = + DAG.getStore(Val.getValue(1), Val, FIN, + &PseudoSourceValue::getFixedStack(), + RegSaveFrameIndex); MemOps.push_back(Store); FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(8)); @@ -1230,7 +1235,10 @@ unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs], X86::VR128RegisterClass); SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32); - SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); + SDOperand Store = + DAG.getStore(Val.getValue(1), Val, FIN, + &PseudoSourceValue::getFixedStack(), + RegSaveFrameIndex); MemOps.push_back(Store); FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(16)); @@ -1559,7 +1567,9 @@ Flags, DAG)); } else { // Store relative to framepointer. - MemOpChains2.push_back(DAG.getStore(Chain, Source, FIN, NULL, 0)); + MemOpChains2.push_back( + DAG.getStore(Chain, Source, FIN, + &PseudoSourceValue::getFixedStack(), FI)); } } } @@ -3788,7 +3798,8 @@ // the GV offset field. Platform check is inside GVRequiresExtraLoad() call // The same applies for external symbols during PIC codegen if (Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false)) - Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result, NULL, 0); + Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result, + &PseudoSourceValue::getGOT(), 0); return Result; } @@ -3846,7 +3857,8 @@ SDOperand Offset = DAG.getNode(X86ISD::Wrapper, PtrVT, TGA); if (GA->getGlobal()->isDeclaration()) // initial exec TLS model - Offset = DAG.getLoad(PtrVT, DAG.getEntryNode(), Offset, NULL, 0); + Offset = DAG.getLoad(PtrVT, DAG.getEntryNode(), Offset, + &PseudoSourceValue::getGOT(), 0); // The address of the thread local variable is the add of the thread // pointer with the offset of the variable. @@ -3978,7 +3990,9 @@ int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size); SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0), - StackSlot, NULL, 0); + StackSlot, + &PseudoSourceValue::getFixedStack(), + SSFI); // These are really Legal; caller falls through into that case. if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) @@ -4019,7 +4033,8 @@ Ops.push_back(DAG.getValueType(Op.getValueType())); Ops.push_back(InFlag); Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size()); - Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot, NULL, 0); + Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot, + &PseudoSourceValue::getFixedStack(), SSFI); } return Result; @@ -4057,7 +4072,8 @@ SDOperand Value = Op.getOperand(0); if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) { assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!"); - Chain = DAG.getStore(Chain, Value, StackSlot, NULL, 0); + Chain = DAG.getStore(Chain, Value, StackSlot, + &PseudoSourceValue::getFixedStack(), SSFI); SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); SDOperand Ops[] = { Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType()) @@ -4116,7 +4132,8 @@ } Constant *C = ConstantVector::get(CV); SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); - SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0, + SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, + &PseudoSourceValue::getConstantPool(), 0, false, 16); return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask); } @@ -4144,7 +4161,8 @@ } Constant *C = ConstantVector::get(CV); SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); - SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0, + SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, + &PseudoSourceValue::getConstantPool(), 0, false, 16); if (MVT::isVector(VT)) { return DAG.getNode(ISD::BIT_CONVERT, VT, @@ -4192,7 +4210,8 @@ } Constant *C = ConstantVector::get(CV); SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); - SDOperand Mask1 = DAG.getLoad(SrcVT, DAG.getEntryNode(), CPIdx, NULL, 0, + SDOperand Mask1 = DAG.getLoad(SrcVT, DAG.getEntryNode(), CPIdx, + &PseudoSourceValue::getConstantPool(), 0, false, 16); SDOperand SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1); @@ -4220,7 +4239,8 @@ } C = ConstantVector::get(CV); CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); - SDOperand Mask2 = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0, + SDOperand Mask2 = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, + &PseudoSourceValue::getConstantPool(), 0, false, 16); SDOperand Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2); @@ -4676,14 +4696,13 @@ } SDOperand X86TargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG) { - SrcValueSDNode *SV = cast(Op.getOperand(2)); + const Value *SV = cast(Op.getOperand(2))->getValue(); if (!Subtarget->is64Bit()) { // vastart just stores the address of the VarArgsFrameIndex slot into the // memory location argument. SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); - return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV->getValue(), - SV->getOffset()); + return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV, 0); } // __va_list_tag: @@ -4696,28 +4715,26 @@ // Store gp_offset SDOperand Store = DAG.getStore(Op.getOperand(0), DAG.getConstant(VarArgsGPOffset, MVT::i32), - FIN, SV->getValue(), SV->getOffset()); + FIN, SV, 0); MemOps.push_back(Store); // Store fp_offset FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4)); Store = DAG.getStore(Op.getOperand(0), DAG.getConstant(VarArgsFPOffset, MVT::i32), - FIN, SV->getValue(), SV->getOffset()); + FIN, SV, 0); MemOps.push_back(Store); // Store ptr to overflow_arg_area FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4)); SDOperand OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); - Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV->getValue(), - SV->getOffset()); + Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV, 0); MemOps.push_back(Store); // Store ptr to reg_save_area. FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(8)); SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy()); - Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV->getValue(), - SV->getOffset()); + Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV, 0); MemOps.push_back(Store); return DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOps[0], MemOps.size()); } @@ -4727,18 +4744,15 @@ SDOperand Chain = Op.getOperand(0); SDOperand DstPtr = Op.getOperand(1); SDOperand SrcPtr = Op.getOperand(2); - SrcValueSDNode *DstSV = cast(Op.getOperand(3)); - SrcValueSDNode *SrcSV = cast(Op.getOperand(4)); + const Value *DstSV = cast(Op.getOperand(3))->getValue(); + const Value *SrcSV = cast(Op.getOperand(4))->getValue(); - SrcPtr = DAG.getLoad(getPointerTy(), Chain, SrcPtr, - SrcSV->getValue(), SrcSV->getOffset()); + SrcPtr = DAG.getLoad(getPointerTy(), Chain, SrcPtr, SrcSV, 0); Chain = SrcPtr.getValue(1); for (unsigned i = 0; i < 3; ++i) { - SDOperand Val = DAG.getLoad(MVT::i64, Chain, SrcPtr, - SrcSV->getValue(), SrcSV->getOffset()); + SDOperand Val = DAG.getLoad(MVT::i64, Chain, SrcPtr, SrcSV, 0); Chain = Val.getValue(1); - Chain = DAG.getStore(Chain, Val, DstPtr, - DstSV->getValue(), DstSV->getOffset()); + Chain = DAG.getStore(Chain, Val, DstPtr, DstSV, 0); if (i == 2) break; SrcPtr = DAG.getNode(ISD::ADD, getPointerTy(), SrcPtr, @@ -4918,7 +4932,7 @@ SDOperand FPtr = Op.getOperand(2); // nested function SDOperand Nest = Op.getOperand(3); // 'nest' parameter value - SrcValueSDNode *TrmpSV = cast(Op.getOperand(4)); + const Value *TrmpAddr = cast(Op.getOperand(4))->getValue(); const X86InstrInfo *TII = ((X86TargetMachine&)getTargetMachine()).getInstrInfo(); @@ -4942,33 +4956,31 @@ unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 SDOperand Addr = Trmp; OutChains[0] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr, - TrmpSV->getValue(), TrmpSV->getOffset()); + TrmpAddr, 0); Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(2, MVT::i64)); - OutChains[1] = DAG.getStore(Root, FPtr, Addr, TrmpSV->getValue(), - TrmpSV->getOffset() + 2, false, 2); + OutChains[1] = DAG.getStore(Root, FPtr, Addr, TrmpAddr, 2, false, 2); // Load the 'nest' parameter value into R10. // R10 is specified in X86CallingConv.td OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(10, MVT::i64)); OutChains[2] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr, - TrmpSV->getValue(), TrmpSV->getOffset() + 10); + TrmpAddr, 10); Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(12, MVT::i64)); - OutChains[3] = DAG.getStore(Root, Nest, Addr, TrmpSV->getValue(), - TrmpSV->getOffset() + 12, false, 2); + OutChains[3] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 12, false, 2); // Jump to the nested function. OpCode = (JMP64r << 8) | REX_WB; // jmpq *... Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(20, MVT::i64)); OutChains[4] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr, - TrmpSV->getValue(), TrmpSV->getOffset() + 20); + TrmpAddr, 20); unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(22, MVT::i64)); OutChains[5] = DAG.getStore(Root, DAG.getConstant(ModRM, MVT::i8), Addr, - TrmpSV->getValue(), TrmpSV->getOffset() + 22); + TrmpAddr, 22); SDOperand Ops[] = { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 6) }; @@ -5026,20 +5038,18 @@ const unsigned char N86Reg = ((X86RegisterInfo*)RegInfo)->getX86RegNum(NestReg); OutChains[0] = DAG.getStore(Root, DAG.getConstant(MOV32ri|N86Reg, MVT::i8), - Trmp, TrmpSV->getValue(), TrmpSV->getOffset()); + Trmp, TrmpAddr, 0); Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(1, MVT::i32)); - OutChains[1] = DAG.getStore(Root, Nest, Addr, TrmpSV->getValue(), - TrmpSV->getOffset() + 1, false, 1); + OutChains[1] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 1, false, 1); const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP); Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(5, MVT::i32)); OutChains[2] = DAG.getStore(Root, DAG.getConstant(JMP, MVT::i8), Addr, - TrmpSV->getValue() + 5, TrmpSV->getOffset()); + TrmpAddr, 5, false, 1); Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(6, MVT::i32)); - OutChains[3] = DAG.getStore(Root, Disp, Addr, TrmpSV->getValue(), - TrmpSV->getOffset() + 6, false, 1); + OutChains[3] = DAG.getStore(Root, Disp, Addr, TrmpAddr, 6, false, 1); SDOperand Ops[] = { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 4) }; Modified: llvm/trunk/utils/TableGen/DAGISelEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelEmitter.cpp?rev=46827&r1=46826&r2=46827&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/DAGISelEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Wed Feb 6 16:27:42 2008 @@ -313,6 +313,12 @@ std::vector > OrigChains; std::set Duplicates; + /// LSI - Load/Store information. + /// Save loads/stores matched by a pattern, and generate a MemOperandSDNode + /// for each memory access. This facilitates the use of AliasAnalysis in + /// the backend. + std::vector LSI; + /// GeneratedCode - This is the buffer that we emit code to. The first int /// indicates whether this is an exit predicate (something that should be /// tested, and if true, the match fails) [when 1], or normal code to emit @@ -373,6 +379,16 @@ void EmitMatchCode(TreePatternNode *N, TreePatternNode *P, const std::string &RootName, const std::string &ChainSuffix, bool &FoundChain) { + + // Save loads/stores matched by a pattern. + if (!N->isLeaf() && N->getName().empty()) { + std::string EnumName = N->getOperator()->getValueAsString("Opcode"); + if (EnumName == "ISD::LOAD" || + EnumName == "ISD::STORE") { + LSI.push_back(RootName); + } + } + bool isRoot = (P == NULL); // Emit instruction predicates. Each predicate is just a string for now. if (isRoot) { @@ -944,6 +960,18 @@ } } + // Generate MemOperandSDNodes nodes for each memory accesses covered by this + // pattern. + if (isRoot) { + std::vector::const_iterator mi, mie; + for (mi = LSI.begin(), mie = LSI.end(); mi != mie; ++mi) { + emitCode("SDOperand LSI_" + *mi + " = " + "CurDAG->getMemOperand(cast(" + + *mi + ")->getMemOperand());"); + AllOps.push_back("LSI_" + *mi); + } + } + // Emit all the chain and CopyToReg stuff. bool ChainEmitted = NodeHasChain; if (NodeHasChain) From isanbard at gmail.com Wed Feb 6 16:33:59 2008 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 06 Feb 2008 22:33:59 -0000 Subject: [llvm-commits] [llvm] r46828 - /llvm/branches/Apple/Zim/lib/CodeGen/RegAllocLocal.cpp Message-ID: <200802062233.m16MXxdb003570@zion.cs.uiuc.edu> Author: void Date: Wed Feb 6 16:33:59 2008 New Revision: 46828 URL: http://llvm.org/viewvc/llvm-project?rev=46828&view=rev Log: [From mainline] http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20080204/057964.html RegAllocaLocal still *requires* LiveVariables since it runs PHIElimination, followed by TwoAddress which requires LiveVariables. We cannot run LiveVariables on non-SSA code. http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20080204/057979.html Fix a number of local register allocator issues: PR1609. Modified: llvm/branches/Apple/Zim/lib/CodeGen/RegAllocLocal.cpp Modified: llvm/branches/Apple/Zim/lib/CodeGen/RegAllocLocal.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zim/lib/CodeGen/RegAllocLocal.cpp?rev=46828&r1=46827&r2=46828&view=diff ============================================================================== --- llvm/branches/Apple/Zim/lib/CodeGen/RegAllocLocal.cpp (original) +++ llvm/branches/Apple/Zim/lib/CodeGen/RegAllocLocal.cpp Wed Feb 6 16:33:59 2008 @@ -14,11 +14,12 @@ #define DEBUG_TYPE "regalloc" #include "llvm/BasicBlock.h" -#include "llvm/CodeGen/Passes.h" +#include "llvm/CodeGen/LiveVariables.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/RegAllocRegistry.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" @@ -28,6 +29,7 @@ #include "llvm/ADT/IndexedMap.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/Statistic.h" +#include "llvm/ADT/STLExtras.h" #include using namespace llvm; @@ -146,6 +148,7 @@ } virtual void getAnalysisUsage(AnalysisUsage &AU) const { + AU.addRequired(); AU.addRequiredID(PHIEliminationID); AU.addRequiredID(TwoAddressInstructionPassID); MachineFunctionPass::getAnalysisUsage(AU); @@ -294,16 +297,24 @@ std::pair &LastUse = getVirtRegLastUse(VirtReg); if (LastUse.first) LastUse.first->getOperand(LastUse.second).setIsKill(); - } - - // Otherwise, there is a virtual register corresponding to this physical - // register. We only need to spill it into its stack slot if it has been - // modified. - if (isVirtRegModified(VirtReg)) { + } else { + // Otherwise, there is a virtual register corresponding to this physical + // register. We only need to spill it into its stack slot if it has been + // modified. const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg); int FrameIndex = getStackSpaceFor(VirtReg, RC); DOUT << " to stack slot #" << FrameIndex; TII->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIndex, RC); + + // If the instruction reads the register that's spilled, (e.g. this can + // happen if it is a move to a physical register), then the spill + // instruction is not a kill. + if (I != MBB.end() && I->findRegisterUseOperandIdx(PhysReg) != -1) { + MachineBasicBlock::iterator StoreMI = prior(I); + int Idx = StoreMI->findRegisterUseOperandIdx(PhysReg, true); + assert(Idx != -1 && "Unrecognized spill instruction!"); + StoreMI->getOperand(Idx).setIsKill(false); + } ++NumStores; // Update statistics } @@ -492,12 +503,6 @@ // If we can fold this spill into this instruction, do so now. SmallVector Ops; Ops.push_back(OpNum); - if (MachineInstr* FMI = TII->foldMemoryOperand(MI, Ops, FrameIndex)) { - ++NumFolded; - // Update kill/dead flags. - FMI->copyKillDeadInfo(MI); - return MBB.insert(MBB.erase(MI), FMI); - } // It looks like we can't fold this virtual register load into this // instruction. Force some poor hapless value out of the register file to @@ -773,9 +778,8 @@ // Finally, if this is a noop copy instruction, zap it. unsigned SrcReg, DstReg; - if (TII.isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == DstReg) { + if (TII.isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == DstReg) MBB.erase(MI); - } } MachineBasicBlock::iterator MI = MBB.getFirstTerminator(); From isanbard at gmail.com Wed Feb 6 16:35:09 2008 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 06 Feb 2008 22:35:09 -0000 Subject: [llvm-commits] [llvm] r46829 - /llvm/tags/Apple/llvmCore-2016/ Message-ID: <200802062235.m16MZ9GL003606@zion.cs.uiuc.edu> Author: void Date: Wed Feb 6 16:35:09 2008 New Revision: 46829 URL: http://llvm.org/viewvc/llvm-project?rev=46829&view=rev Log: Creating llvmCore-2016 tag from Zim branch Added: llvm/tags/Apple/llvmCore-2016/ - copied from r46828, llvm/branches/Apple/Zim/ From resistor at mac.com Wed Feb 6 17:08:59 2008 From: resistor at mac.com (Owen Anderson) Date: Wed, 6 Feb 2008 17:08:59 -0600 Subject: [llvm-commits] [llvm] r46828 - /llvm/branches/Apple/Zim/lib/CodeGen/RegAllocLocal.cpp In-Reply-To: <200802062233.m16MXxdb003570@zion.cs.uiuc.edu> References: <200802062233.m16MXxdb003570@zion.cs.uiuc.edu> Message-ID: I should clarify that, in a general sense, RegAllocLocal does not depend on LiveVariables, but declaring it as such seems to be necessary to obtain a working pass ordering. --Owen On Feb 6, 2008, at 4:33 PM, Bill Wendling wrote: > Author: void > Date: Wed Feb 6 16:33:59 2008 > New Revision: 46828 > > URL: http://llvm.org/viewvc/llvm-project?rev=46828&view=rev > Log: > [From mainline] > > http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20080204/057964.html > > RegAllocaLocal still *requires* LiveVariables since it runs > PHIElimination, > followed by TwoAddress which requires LiveVariables. We cannot run > LiveVariables on non-SSA code. > > http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20080204/057979.html > > Fix a number of local register allocator issues: PR1609. > > > Modified: > llvm/branches/Apple/Zim/lib/CodeGen/RegAllocLocal.cpp > > Modified: llvm/branches/Apple/Zim/lib/CodeGen/RegAllocLocal.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zim/lib/CodeGen/RegAllocLocal.cpp?rev=46828&r1=46827&r2=46828&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/branches/Apple/Zim/lib/CodeGen/RegAllocLocal.cpp (original) > +++ llvm/branches/Apple/Zim/lib/CodeGen/RegAllocLocal.cpp Wed Feb 6 > 16:33:59 2008 > @@ -14,11 +14,12 @@ > > #define DEBUG_TYPE "regalloc" > #include "llvm/BasicBlock.h" > -#include "llvm/CodeGen/Passes.h" > +#include "llvm/CodeGen/LiveVariables.h" > #include "llvm/CodeGen/MachineFunctionPass.h" > #include "llvm/CodeGen/MachineInstr.h" > #include "llvm/CodeGen/MachineFrameInfo.h" > #include "llvm/CodeGen/MachineRegisterInfo.h" > +#include "llvm/CodeGen/Passes.h" > #include "llvm/CodeGen/RegAllocRegistry.h" > #include "llvm/Target/TargetInstrInfo.h" > #include "llvm/Target/TargetMachine.h" > @@ -28,6 +29,7 @@ > #include "llvm/ADT/IndexedMap.h" > #include "llvm/ADT/SmallVector.h" > #include "llvm/ADT/Statistic.h" > +#include "llvm/ADT/STLExtras.h" > #include > using namespace llvm; > > @@ -146,6 +148,7 @@ > } > > virtual void getAnalysisUsage(AnalysisUsage &AU) const { > + AU.addRequired(); > AU.addRequiredID(PHIEliminationID); > AU.addRequiredID(TwoAddressInstructionPassID); > MachineFunctionPass::getAnalysisUsage(AU); > @@ -294,16 +297,24 @@ > std::pair &LastUse = > getVirtRegLastUse(VirtReg); > if (LastUse.first) > LastUse.first->getOperand(LastUse.second).setIsKill(); > - } > - > - // Otherwise, there is a virtual register corresponding to this > physical > - // register. We only need to spill it into its stack slot if it > has been > - // modified. > - if (isVirtRegModified(VirtReg)) { > + } else { > + // Otherwise, there is a virtual register corresponding to this > physical > + // register. We only need to spill it into its stack slot if > it has been > + // modified. > const TargetRegisterClass *RC = MF- > >getRegInfo().getRegClass(VirtReg); > int FrameIndex = getStackSpaceFor(VirtReg, RC); > DOUT << " to stack slot #" << FrameIndex; > TII->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIndex, RC); > + > + // If the instruction reads the register that's spilled, (e.g. > this can > + // happen if it is a move to a physical register), then the spill > + // instruction is not a kill. > + if (I != MBB.end() && I->findRegisterUseOperandIdx(PhysReg) != > -1) { > + MachineBasicBlock::iterator StoreMI = prior(I); > + int Idx = StoreMI->findRegisterUseOperandIdx(PhysReg, true); > + assert(Idx != -1 && "Unrecognized spill instruction!"); > + StoreMI->getOperand(Idx).setIsKill(false); > + } > ++NumStores; // Update statistics > } > > @@ -492,12 +503,6 @@ > // If we can fold this spill into this instruction, do so now. > SmallVector Ops; > Ops.push_back(OpNum); > - if (MachineInstr* FMI = TII->foldMemoryOperand(MI, Ops, > FrameIndex)) { > - ++NumFolded; > - // Update kill/dead flags. > - FMI->copyKillDeadInfo(MI); > - return MBB.insert(MBB.erase(MI), FMI); > - } > > // It looks like we can't fold this virtual register load into > this > // instruction. Force some poor hapless value out of the > register file to > @@ -773,9 +778,8 @@ > > // Finally, if this is a noop copy instruction, zap it. > unsigned SrcReg, DstReg; > - if (TII.isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == DstReg) { > + if (TII.isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == DstReg) > MBB.erase(MI); > - } > } > > MachineBasicBlock::iterator MI = MBB.getFirstTerminator(); > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -------------- next part -------------- A non-text attachment was scrubbed... Name: smime.p7s Type: application/pkcs7-signature Size: 2555 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20080206/03a0342e/attachment.bin From gohman at apple.com Wed Feb 6 17:09:16 2008 From: gohman at apple.com (Dan Gohman) Date: Wed, 06 Feb 2008 23:09:16 -0000 Subject: [llvm-commits] [llvm] r46833 - in /llvm/trunk: include/llvm/ADT/FoldingSet.h lib/Support/FoldingSet.cpp Message-ID: <200802062309.m16N9GRB004607@zion.cs.uiuc.edu> Author: djg Date: Wed Feb 6 17:09:15 2008 New Revision: 46833 URL: http://llvm.org/viewvc/llvm-project?rev=46833&view=rev Log: Add support to FoldingSet for hashing APInt objects. Modified: llvm/trunk/include/llvm/ADT/FoldingSet.h llvm/trunk/lib/Support/FoldingSet.cpp Modified: llvm/trunk/include/llvm/ADT/FoldingSet.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/FoldingSet.h?rev=46833&r1=46832&r2=46833&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/FoldingSet.h (original) +++ llvm/trunk/include/llvm/ADT/FoldingSet.h Wed Feb 6 17:09:15 2008 @@ -22,6 +22,7 @@ namespace llvm { class APFloat; + class APInt; /// This folding set used for two purposes: /// 1. Given information about a node we want to create, look up the unique @@ -206,6 +207,7 @@ void AddFloat(float F); void AddDouble(double D); void AddAPFloat(const APFloat& apf); + void AddAPInt(const APInt& api); void AddString(const std::string &String); /// clear - Clear the accumulated profile, allowing this FoldingSetNodeID Modified: llvm/trunk/lib/Support/FoldingSet.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/FoldingSet.cpp?rev=46833&r1=46832&r2=46833&view=diff ============================================================================== --- llvm/trunk/lib/Support/FoldingSet.cpp (original) +++ llvm/trunk/lib/Support/FoldingSet.cpp Wed Feb 6 17:09:15 2008 @@ -16,6 +16,7 @@ #include "llvm/ADT/FoldingSet.h" #include "llvm/ADT/APFloat.h" +#include "llvm/ADT/APInt.h" #include "llvm/Support/MathExtras.h" #include using namespace llvm; @@ -59,6 +60,9 @@ } void FoldingSetNodeID::AddAPFloat(const APFloat& apf) { APInt api = apf.convertToAPInt(); + AddAPInt(api); +} +void FoldingSetNodeID::AddAPInt(const APInt& api) { const uint64_t *p = api.getRawData(); for (unsigned i=0; i Author: johannes Date: Wed Feb 6 17:26:23 2008 New Revision: 46834 URL: http://llvm.org/viewvc/llvm-project?rev=46834&view=rev Log: Make TARGET_PIM_ALTIVEC actually reflect -mpim-altivec. This means vector constants using the PIM syntax will be splatted as they're supposed to be, rather than zero-filled. Modified: llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.c Modified: llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.c?rev=46834&r1=46833&r2=46834&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.c (original) +++ llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.c Wed Feb 6 17:26:23 2008 @@ -1486,8 +1486,11 @@ { flag_disable_opts_for_faltivec = 1; /* APPLE LOCAL radar 4161346 */ - target_flags |= (MASK_ALTIVEC | MASK_PIM_ALTIVEC); +/* LLVM LOCAL begin handle -mpim-altivec correctly */ + target_flags |= MASK_ALTIVEC; } + target_flags |= MASK_PIM_ALTIVEC; +/* LLVM LOCAL begin handle -mpim-altivec correctly */ } /* APPLE LOCAL end AltiVec */ From dpatel at apple.com Wed Feb 6 17:27:03 2008 From: dpatel at apple.com (Devang Patel) Date: Wed, 6 Feb 2008 15:27:03 -0800 Subject: [llvm-commits] [llvm] r46828 - /llvm/branches/Apple/Zim/lib/CodeGen/RegAllocLocal.cpp In-Reply-To: References: <200802062233.m16MXxdb003570@zion.cs.uiuc.edu> Message-ID: On Feb 6, 2008, at 3:08 PM, Owen Anderson wrote: > I should clarify that, in a general sense, RegAllocLocal does not > depend on LiveVariables, but declaring it as such seems to be > necessary to obtain a working pass ordering. hmmm, then LiveVariables pass should be inserted in the pass queue, before RegAllocLocal pass, using PassManager->addPass(). - Devang From gohman at apple.com Wed Feb 6 20:30:40 2008 From: gohman at apple.com (Dan Gohman) Date: Thu, 07 Feb 2008 02:30:40 -0000 Subject: [llvm-commits] [llvm] r46836 - /llvm/trunk/lib/VMCore/Constants.cpp Message-ID: <200802070230.m172UehQ010487@zion.cs.uiuc.edu> Author: djg Date: Wed Feb 6 20:30:40 2008 New Revision: 46836 URL: http://llvm.org/viewvc/llvm-project?rev=46836&view=rev Log: Fix a typo in a comment. Modified: llvm/trunk/lib/VMCore/Constants.cpp Modified: llvm/trunk/lib/VMCore/Constants.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Constants.cpp?rev=46836&r1=46835&r2=46836&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Constants.cpp (original) +++ llvm/trunk/lib/VMCore/Constants.cpp Wed Feb 6 20:30:40 2008 @@ -225,7 +225,7 @@ } // Get a ConstantInt from an APInt. Note that the value stored in the DenseMap -// as the key, is a DensMapAPIntKeyInfo::KeyTy which has provided the +// as the key, is a DenseMapAPIntKeyInfo::KeyTy which has provided the // operator== and operator!= to ensure that the DenseMap doesn't attempt to // compare APInt's of different widths, which would violate an APInt class // invariant which generates an assertion. From isanbard at gmail.com Wed Feb 6 23:45:14 2008 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 07 Feb 2008 05:45:14 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r46842 - in /llvm-gcc-4.2/trunk/gcc: config/darwin.c config/rs6000/rs6000.c varasm.c Message-ID: <200802070545.m175jFpf016054@zion.cs.uiuc.edu> Author: void Date: Wed Feb 6 23:45:10 2008 New Revision: 46842 URL: http://llvm.org/viewvc/llvm-project?rev=46842&view=rev Log: Clean up the patch about visibility. Only block out the parts LLVM doesn't want to do instead of creating new functions and making life miserable for everyone on the planet. Modified: llvm-gcc-4.2/trunk/gcc/config/darwin.c llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.c llvm-gcc-4.2/trunk/gcc/varasm.c Modified: llvm-gcc-4.2/trunk/gcc/config/darwin.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/darwin.c?rev=46842&r1=46841&r2=46842&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/darwin.c (original) +++ llvm-gcc-4.2/trunk/gcc/config/darwin.c Wed Feb 6 23:45:10 2008 @@ -1988,19 +1988,6 @@ extern". There is no MACH-O equivalent of ELF's VISIBILITY_INTERNAL or VISIBILITY_PROTECTED. */ -/* LLVM LOCAL begin */ -#ifdef ENABLE_LLVM -void -darwin_assemble_visibility (tree decl ATTRIBUTE_UNUSED, int vis) -{ - /* Emit a warning if the visibility isn't supported with this - configuration. We don't want to output anything to the ASM file, of - course. */ - if (!(vis == VISIBILITY_DEFAULT || vis == VISIBILITY_HIDDEN)) - warning (OPT_Wattributes, "internal and protected visibility attributes " - "not supported in this configuration; ignored"); -} -#else void darwin_assemble_visibility (tree decl, int vis) { @@ -2008,17 +1995,19 @@ ; else if (vis == VISIBILITY_HIDDEN) { +/* LLVM LOCAL */ +#ifndef ENABLE_LLVM fputs ("\t.private_extern ", asm_out_file); assemble_name (asm_out_file, (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)))); fputs ("\n", asm_out_file); +/* LLVM LOCAL */ +#endif } else warning (OPT_Wattributes, "internal and protected visibility attributes " "not supported in this configuration; ignored"); } -#endif -/* LLVM LOCAL end */ /* Output a difference of two labels that will be an assembly time constant if the two labels are local. (.long lab1-lab2 will be Modified: llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.c?rev=46842&r1=46841&r2=46842&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.c (original) +++ llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.c Wed Feb 6 23:45:10 2008 @@ -944,14 +944,10 @@ #undef TARGET_ASM_INTEGER #define TARGET_ASM_INTEGER rs6000_assemble_integer -/* LLVM LOCAL - Use default assemble_visibility */ -#ifndef ENABLE_LLVM #ifdef HAVE_GAS_HIDDEN #undef TARGET_ASM_ASSEMBLE_VISIBILITY #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility #endif -/* LLVM LOCAL - Use default assemble_visibility */ -#endif #undef TARGET_HAVE_TLS #define TARGET_HAVE_TLS HAVE_AS_TLS @@ -13108,6 +13104,8 @@ && DOT_SYMBOLS && TREE_CODE (decl) == FUNCTION_DECL) { +/* LLVM LOCAL */ +#ifndef ENABLE_LLVM static const char * const visibility_types[] = { NULL, "internal", "hidden", "protected" }; @@ -13120,6 +13118,8 @@ fprintf (asm_out_file, "\t.%s\t%s\n", type, name); fprintf (asm_out_file, "\t.%s\t.%s\n", type, name); +/* LLVM LOCAL */ +#endif } else default_assemble_visibility (decl, vis); Modified: llvm-gcc-4.2/trunk/gcc/varasm.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/varasm.c?rev=46842&r1=46841&r2=46842&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/varasm.c (original) +++ llvm-gcc-4.2/trunk/gcc/varasm.c Wed Feb 6 23:45:10 2008 @@ -5317,11 +5317,12 @@ #ifdef HAVE_GAS_HIDDEN +/* LLVM LOCAL */ #ifndef ENABLE_LLVM fprintf (asm_out_file, "\t.%s\t", type); assemble_name (asm_out_file, name); fprintf (asm_out_file, "\n"); - /* LLVM LOCAL */ +/* LLVM LOCAL */ #endif #else warning (OPT_Wattributes, "visibility attribute not supported " From nicholas at mxc.ca Thu Feb 7 00:36:27 2008 From: nicholas at mxc.ca (Nick Lewycky) Date: Thu, 07 Feb 2008 06:36:27 -0000 Subject: [llvm-commits] [llvm] r46848 - /llvm/trunk/lib/CodeGen/AsmPrinter.cpp Message-ID: <200802070636.m176aRAR017458@zion.cs.uiuc.edu> Author: nicholas Date: Thu Feb 7 00:36:26 2008 New Revision: 46848 URL: http://llvm.org/viewvc/llvm-project?rev=46848&view=rev Log: Don't make up new directives. (".set_foobar") Modified: llvm/trunk/lib/CodeGen/AsmPrinter.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter.cpp?rev=46848&r1=46847&r2=46848&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter.cpp Thu Feb 7 00:36:26 2008 @@ -157,7 +157,7 @@ else if (!I->hasInternalLinkage()) assert(0 && "Invalid alias linkage"); - O << TAI->getSetDirective() << Name << ", " << Target << "\n"; + O << TAI->getSetDirective() << ' ' << Name << ", " << Target << "\n"; // If the aliasee has external weak linkage it can be referenced only by // alias itself. In this case it can be not in ExtWeakSymbols list. Emit From evan.cheng at apple.com Thu Feb 7 02:29:53 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 07 Feb 2008 08:29:53 -0000 Subject: [llvm-commits] [llvm] r46849 - /llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Message-ID: <200802070829.m178Trmk020622@zion.cs.uiuc.edu> Author: evancheng Date: Thu Feb 7 02:29:53 2008 New Revision: 46849 URL: http://llvm.org/viewvc/llvm-project?rev=46849&view=rev Log: In some cases, e.g. ADD32ri, no transformation is made. Guide against it. Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=46849&r1=46848&r2=46849&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Thu Feb 7 02:29:53 2008 @@ -1011,6 +1011,8 @@ } } + if (!NewMI) return 0; + NewMI->copyKillDeadInfo(MI); LV.instructionChanged(MI, NewMI); // Update live variables MFI->insert(MBBI, NewMI); // Insert the new inst From evan.cheng at apple.com Thu Feb 7 02:32:31 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 7 Feb 2008 00:32:31 -0800 Subject: [llvm-commits] [llvm] r46827 - in /llvm/trunk: include/llvm/ include/llvm/CodeGen/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/IA64/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/X86/ utils/TableGen/ In-Reply-To: <200802062227.m16MRhjU003393@zion.cs.uiuc.edu> References: <200802062227.m16MRhjU003393@zion.cs.uiuc.edu> Message-ID: Hi Dan, This seems to be breaking -print-machineinstrs. Try test/CodeGen/X86/ pic_jumptable.ll: bb2: 0x1204da0, LLVM BB @0x1201c20, ID#1: Predecessors according to CFG: 0x12026c0 (#5) ADJCALLSTACKDOWN 4, %ESP, %EFLAGS, %ESP %reg1029 = MOV32rr %ESP MOV32mi %reg1029, 1, %reg0, 0, 1, SV:Assertion failed: (V && "SV missing."), function print, file MachineInstr.cpp, line 639. Thanks, Evan On Feb 6, 2008, at 2:27 PM, Dan Gohman wrote: > Author: djg > Date: Wed Feb 6 16:27:42 2008 > New Revision: 46827 > > URL: http://llvm.org/viewvc/llvm-project?rev=46827&view=rev > Log: > Re-apply the memory operand changes, with a fix for the static > initializer problem, a minor tweak to the way the > DAGISelEmitter finds load/store nodes, and a renaming of the > new PseudoSourceValue objects. > > Modified: > llvm/trunk/include/llvm/CodeGen/MachineInstr.h > llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h > llvm/trunk/include/llvm/CodeGen/MemOperand.h > llvm/trunk/include/llvm/CodeGen/PseudoSourceValue.h > llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h > llvm/trunk/include/llvm/CodeGen/SelectionDAG.h > llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h > llvm/trunk/include/llvm/Value.h > llvm/trunk/lib/CodeGen/MachineInstr.cpp > llvm/trunk/lib/CodeGen/PseudoSourceValue.cpp > llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp > llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp > llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp > llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp > llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp > llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp > llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp > llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp > llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp > llvm/trunk/lib/Target/X86/X86ISelLowering.cpp > llvm/trunk/utils/TableGen/DAGISelEmitter.cpp > > Modified: llvm/trunk/include/llvm/CodeGen/MachineInstr.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstr.h?rev=46827&r1=46826&r2=46827&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/include/llvm/CodeGen/MachineInstr.h (original) > +++ llvm/trunk/include/llvm/CodeGen/MachineInstr.h Wed Feb 6 > 16:27:42 2008 > @@ -17,6 +17,7 @@ > #define LLVM_CODEGEN_MACHINEINSTR_H > > #include "llvm/CodeGen/MachineOperand.h" > +#include "llvm/CodeGen/MemOperand.h" > > namespace llvm { > > @@ -35,6 +36,7 @@ > // are determined at > construction time). > > std::vector Operands; // the operands > + std::vector MemOperands; // information on memory > references > MachineInstr *Prev, *Next; // Links for MBB's intrusive > list. > MachineBasicBlock *Parent; // Pointer to the owning > basic block. > > @@ -94,6 +96,18 @@ > /// > unsigned getNumExplicitOperands() const; > > + /// Access to memory operands of the instruction > + unsigned getNumMemOperands() const { return MemOperands.size(); } > + > + const MemOperand& getMemOperand(unsigned i) const { > + assert(i < getNumMemOperands() && "getMemOperand() out of > range!"); > + return MemOperands[i]; > + } > + MemOperand& getMemOperand(unsigned i) { > + assert(i < getNumMemOperands() && "getMemOperand() out of > range!"); > + return MemOperands[i]; > + } > + > /// isIdenticalTo - Return true if this instruction is identical > to (same > /// opcode and same operands as) the specified instruction. > bool isIdenticalTo(const MachineInstr *Other) const { > @@ -196,6 +210,12 @@ > /// > void RemoveOperand(unsigned i); > > + /// addMemOperand - Add a MemOperand to the machine instruction, > referencing > + /// arbitrary storage. > + void addMemOperand(const MemOperand &MO) { > + MemOperands.push_back(MO); > + } > + > private: > /// getRegInfo - If this instruction is embedded into a > MachineFunction, > /// return the MachineRegisterInfo object for the current > function, otherwise > > Modified: llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h?rev=46827&r1=46826&r2=46827&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h (original) > +++ llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h Wed Feb 6 > 16:27:42 2008 > @@ -83,6 +83,12 @@ > MI->addOperand(MachineOperand::CreateES(FnName, 0)); > return *this; > } > + > + /// addMemOperand - Add a memory operand to the machine > instruction. > + const MachineInstrBuilder &addMemOperand(const MemOperand &MO) > const { > + MI->addMemOperand(MO); > + return *this; > + } > }; > > /// BuildMI - Builder interface. Specify how to create the initial > instruction > > Modified: llvm/trunk/include/llvm/CodeGen/MemOperand.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MemOperand.h?rev=46827&r1=46826&r2=46827&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/include/llvm/CodeGen/MemOperand.h (original) > +++ llvm/trunk/include/llvm/CodeGen/MemOperand.h Wed Feb 6 16:27:42 > 2008 > @@ -0,0 +1,82 @@ > +//===-- llvm/CodeGen/MemOperand.h - MemOperand class ------------*- > C++ -*-===// > +// > +// The LLVM Compiler Infrastructure > +// > +// This file is distributed under the University of Illinois Open > Source > +// License. See LICENSE.TXT for details. > +// > +// > = > = > = > ----------------------------------------------------------------------= > ==// > +// > +// This file contains the declaration of the MemOperand class, > which is a > +// description of a memory reference. It is used to help track > dependencies > +// in the backend. > +// > +// > = > = > = > ----------------------------------------------------------------------= > ==// > + > +#ifndef LLVM_CODEGEN_MEMOPERAND_H > +#define LLVM_CODEGEN_MEMOPERAND_H > + > +namespace llvm { > + > +class Value; > + > +// > = > = > = > ----------------------------------------------------------------------= > ==// > +/// MemOperand - A description of a memory reference used in the > backend. > +/// Instead of holding a StoreInst or LoadInst, this class holds > the address > +/// Value of the reference along with a byte size and offset. This > allows it > +/// to describe lowered loads and stores. Also, the special > PseudoSourceValue > +/// objects can be used to represent loads and stores to memory > locations > +/// that aren't explicit in the regular LLVM IR. > +/// > +class MemOperand { > + const Value *V; > + unsigned int Flags; > + int Offset; > + int Size; > + unsigned int Alignment; > + > +public: > + /// Flags values. These may be or'd together. > + enum MemOperandFlags { > + /// The memory access reads data. > + MOLoad = 1, > + /// The memory access writes data. > + MOStore = 2, > + /// The memory access is volatile. > + MOVolatile = 4 > + }; > + > + /// MemOperand - Construct an MemOperand object with the specified > + /// address Value, flags, offset, size, and alignment. > + MemOperand(const Value *v, unsigned int f, int o, int s, unsigned > int a) > + : V(v), Flags(f), Offset(o), Size(s), Alignment(a) {} > + > + /// getValue - Return the base address of the memory access. > + /// Special values are PseudoSourceValue::FPRel, > PseudoSourceValue::SPRel, > + /// and the other PseudoSourceValue members which indicate > references to > + /// frame/stack pointer relative references and other special > references. > + const Value *getValue() const { return V; } > + > + /// getFlags - Return the raw flags of the source value, \see > MemOperandFlags. > + unsigned int getFlags() const { return Flags; } > + > + /// getOffset - For normal values, this is a byte offset added to > the base > + /// address. For PseudoSourceValue::FPRel values, this is the > FrameIndex > + /// number. > + int getOffset() const { return Offset; } > + > + /// getSize - Return the size in bytes of the memory reference. > + int getSize() const { return Size; } > + > + /// getAlignment - Return the minimum known alignment in bytes of > the > + /// memory reference. > + unsigned int getAlignment() const { return Alignment; } > + > + bool isLoad() const { return Flags & MOLoad; } > + bool isStore() const { return Flags & MOStore; } > + bool isVolatile() const { return Flags & MOVolatile; } > +}; > + > +} // End llvm namespace > + > +#endif > > Modified: llvm/trunk/include/llvm/CodeGen/PseudoSourceValue.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/PseudoSourceValue.h?rev=46827&r1=46826&r2=46827&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/include/llvm/CodeGen/PseudoSourceValue.h (original) > +++ llvm/trunk/include/llvm/CodeGen/PseudoSourceValue.h Wed Feb 6 > 16:27:42 2008 > @@ -0,0 +1,58 @@ > +//===-- llvm/CodeGen/PseudoSourceValue.h ------------------------*- > C++ -*-===// > +// > +// The LLVM Compiler Infrastructure > +// > +// This file is distributed under the University of Illinois Open > Source > +// License. See LICENSE.TXT for details. > +// > +// > = > = > = > ----------------------------------------------------------------------= > ==// > +// > +// This file contains the declaration of the PseudoSourceValue class. > +// > +// > = > = > = > ----------------------------------------------------------------------= > ==// > + > +#ifndef LLVM_CODEGEN_PSEUDOSOURCEVALUE_H > +#define LLVM_CODEGEN_PSEUDOSOURCEVALUE_H > + > +#include "llvm/Value.h" > + > +namespace llvm { > + /// PseudoSourceValue - Special value supplied for machine level > alias > + /// analysis. It indicates that the a memory access references > the functions > + /// stack frame (e.g., a spill slot), below the stack frame > (e.g., argument > + /// space), or constant pool. > + class PseudoSourceValue : public Value { > + public: > + PseudoSourceValue(); > + > + virtual void print(std::ostream &OS) const; > + > + /// classof - Methods for support type inquiry through isa, > cast, and > + /// dyn_cast: > + /// > + static inline bool classof(const PseudoSourceValue *) { return > true; } > + static inline bool classof(const Value *V) { > + return V->getValueID() == PseudoSourceValueVal; > + } > + > + /// A pseudo source value referencing to the stack frame of a > function, > + /// e.g., a spill slot. > + static const PseudoSourceValue &getFixedStack(); > + > + /// A source value referencing the area below the stack frame > of a function, > + /// e.g., the argument space. > + static const PseudoSourceValue &getStack(); > + > + /// A source value referencing the global offset table (or > something the > + /// like). > + static const PseudoSourceValue &getGOT(); > + > + /// A SV referencing the constant pool > + static const PseudoSourceValue &getConstantPool(); > + > + /// A SV referencing the jump table > + static const PseudoSourceValue &getJumpTable(); > + }; > +} // End llvm namespace > + > +#endif > > Modified: llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h?rev=46827&r1=46826&r2=46827&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h (original) > +++ llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h Wed Feb 6 > 16:27:42 2008 > @@ -279,6 +279,7 @@ > if (isa(Node)) return true; > if (isa(Node)) return true; > if (isa(Node)) return true; > + if (isa(Node)) return true; > return false; > } > > @@ -312,11 +313,15 @@ > /// (which do not go into the machine instrs.) > static unsigned CountResults(SDNode *Node); > > - /// CountOperands The inputs to target nodes have any actual > inputs first, > - /// followed by an optional chain operand, then flag operands. > Compute the > - /// number of actual operands that will go into the machine > instr. > + /// CountOperands - The inputs to target nodes have any actual > inputs first, > + /// followed by optional memory operands chain operand, then > flag operands. > + /// Compute the number of actual operands that will go into > the machine > + /// instr. > static unsigned CountOperands(SDNode *Node); > > + /// CountMemOperands - Find the index of the last > MemOperandSDNode > + static unsigned CountMemOperands(SDNode *Node); > + > /// EmitNode - Generate machine code for an node and needed > dependencies. > /// VRBaseMap contains, for each already emitted node, the first > virtual > /// register number for the results of the node. > @@ -357,6 +362,8 @@ > void AddOperand(MachineInstr *MI, SDOperand Op, unsigned IIOpNum, > const TargetInstrDesc *II, > DenseMap &VRBaseMap); > + > + void AddMemOperand(MachineInstr *MI, const MemOperand &MO); > }; > > /// createBURRListDAGScheduler - This creates a bottom up register > usage > > Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=46827&r1=46826&r2=46827&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original) > +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Wed Feb 6 > 16:27:42 2008 > @@ -376,8 +376,12 @@ > SDOperand getIndexedStore(SDOperand OrigStoe, SDOperand Base, > SDOperand Offset, ISD::MemIndexedMode AM); > > - // getSrcValue - construct a node to track a Value* through the > backend > - SDOperand getSrcValue(const Value* I, int offset = 0); > + // getSrcValue - Construct a node to track a Value* through the > backend. > + SDOperand getSrcValue(const Value *v); > + > + // getMemOperand - Construct a node to track a memory reference > + // through the backend. > + SDOperand getMemOperand(const MemOperand &MO); > > /// UpdateNodeOperands - *Mutate* the specified node in-place to > have the > /// specified operands. If the resultant node already exists in > the DAG, > > Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=46827&r1=46826&r2=46827&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original) > +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Wed Feb 6 > 16:27:42 2008 > @@ -25,6 +25,7 @@ > #include "llvm/ADT/iterator" > #include "llvm/ADT/APFloat.h" > #include "llvm/CodeGen/ValueTypes.h" > +#include "llvm/CodeGen/MemOperand.h" > #include "llvm/Support/DataTypes.h" > #include > > @@ -542,11 +543,15 @@ > // pointer, and a SRCVALUE. > VAEND, VASTART, > > - // SRCVALUE - This corresponds to a Value*, and is used to > associate memory > - // locations with their value. This allows one use alias > analysis > - // information in the backend. > + // SRCVALUE - This is a node type that holds a Value* that is > used to > + // make reference to a value in the LLVM IR. > SRCVALUE, > > + // MEMOPERAND - This is a node that contains a MemOperand which > records > + // information about a memory reference. This is used to make > AliasAnalysis > + // queries from the backend. > + MEMOPERAND, > + > // PCMARKER - This corresponds to the pcmarker intrinsic. > PCMARKER, > > @@ -1391,17 +1396,16 @@ > > class SrcValueSDNode : public SDNode { > const Value *V; > - int offset; > virtual void ANCHOR(); // Out-of-line virtual method to give > class a home. > protected: > friend class SelectionDAG; > - SrcValueSDNode(const Value* v, int o) > - : SDNode(ISD::SRCVALUE, getSDVTList(MVT::Other)), V(v), > offset(o) { > - } > + /// Create a SrcValue for a general value. > + explicit SrcValueSDNode(const Value *v) > + : SDNode(ISD::SRCVALUE, getSDVTList(MVT::Other)), V(v) {} > > public: > + /// getValue - return the contained Value. > const Value *getValue() const { return V; } > - int getOffset() const { return offset; } > > static bool classof(const SrcValueSDNode *) { return true; } > static bool classof(const SDNode *N) { > @@ -1410,6 +1414,29 @@ > }; > > > +/// MemOperandSDNode - An SDNode that holds a MemOperand. This is > +/// used to represent a reference to memory after ISD::LOAD > +/// and ISD::STORE have been lowered. > +/// > +class MemOperandSDNode : public SDNode { > + virtual void ANCHOR(); // Out-of-line virtual method to give > class a home. > +protected: > + friend class SelectionDAG; > + /// Create a MemOperand node > + explicit MemOperandSDNode(MemOperand mo) > + : SDNode(ISD::MEMOPERAND, getSDVTList(MVT::Other)), MO(mo) {} > + > +public: > + /// MO - The contained MemOperand. > + const MemOperand MO; > + > + static bool classof(const MemOperandSDNode *) { return true; } > + static bool classof(const SDNode *N) { > + return N->getOpcode() == ISD::MEMOPERAND; > + } > +}; > + > + > class RegisterSDNode : public SDNode { > unsigned Reg; > virtual void ANCHOR(); // Out-of-line virtual method to give > class a home. > @@ -1559,6 +1586,10 @@ > /// isUnindexed - Return true if this is NOT a pre/post inc/dec > load/store. > bool isUnindexed() const { return AddrMode == ISD::UNINDEXED; } > > + /// getMemOperand - Return a MemOperand object describing the > memory > + /// reference performed by this load or store. > + MemOperand getMemOperand() const; > + > static bool classof(const LSBaseSDNode *N) { return true; } > static bool classof(const SDNode *N) { > return N->getOpcode() == ISD::LOAD || > > Modified: llvm/trunk/include/llvm/Value.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Value.h?rev=46827&r1=46826&r2=46827&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/include/llvm/Value.h (original) > +++ llvm/trunk/include/llvm/Value.h Wed Feb 6 16:27:42 2008 > @@ -187,6 +187,7 @@ > ConstantVectorVal, // This is an instance of ConstantVector > ConstantPointerNullVal, // This is an instance of > ConstantPointerNull > InlineAsmVal, // This is an instance of InlineAsm > + PseudoSourceValueVal, // This is an instance of > PseudoSourceValue > InstructionVal, // This is an instance of Instruction > > // Markers: > > Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=46827&r1=46826&r2=46827&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original) > +++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Wed Feb 6 16:27:42 2008 > @@ -15,6 +15,8 @@ > #include "llvm/Value.h" > #include "llvm/CodeGen/MachineFunction.h" > #include "llvm/CodeGen/MachineRegisterInfo.h" > +#include "llvm/CodeGen/PseudoSourceValue.h" > +#include "llvm/CodeGen/SelectionDAGNodes.h" > #include "llvm/Target/TargetMachine.h" > #include "llvm/Target/TargetInstrInfo.h" > #include "llvm/Target/TargetInstrDesc.h" > @@ -292,6 +294,7 @@ > TID = &MI.getDesc(); > NumImplicitOps = MI.NumImplicitOps; > Operands.reserve(MI.getNumOperands()); > + MemOperands = MI.MemOperands; > > // Add operands > for (unsigned i = 0; i != MI.getNumOperands(); ++i) { > @@ -627,6 +630,34 @@ > getOperand(i).print(OS, TM); > } > > + if (getNumMemOperands() > 0) { > + OS << ", SV:"; > + for (unsigned i = 0; i < getNumMemOperands(); i++) { > + const MemOperand &MRO = getMemOperand(i); > + const Value *V = MRO.getValue(); > + > + assert(V && "SV missing."); > + assert((MRO.isLoad() || MRO.isStore()) && > + "SV has to be a load, store or both."); > + > + if (MRO.isVolatile()) > + OS << "Volatile "; > + if (MRO.isLoad()) > + OS << "LD "; > + if (MRO.isStore()) > + OS << "ST "; > + > + OS << MRO.getSize(); > + > + if (!V->getName().empty()) > + OS << "[" << V->getName() << " + " << MRO.getOffset() << "]"; > + else if (isa(V)) > + OS << "[" << *V << " + " << MRO.getOffset() << "]"; > + else > + OS << "[" << V << " + " << MRO.getOffset() << "]"; > + } > + } > + > OS << "\n"; > } > > > Modified: llvm/trunk/lib/CodeGen/PseudoSourceValue.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PseudoSourceValue.cpp?rev=46827&r1=46826&r2=46827&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/CodeGen/PseudoSourceValue.cpp (original) > +++ llvm/trunk/lib/CodeGen/PseudoSourceValue.cpp Wed Feb 6 16:27:42 > 2008 > @@ -0,0 +1,41 @@ > +//===-- llvm/CodeGen/PseudoSourceValue.cpp ----------------------*- > C++ -*-===// > +// > +// The LLVM Compiler Infrastructure > +// > +// This file is distributed under the University of Illinois Open > Source > +// License. See LICENSE.TXT for details. > +// > +// > = > = > = > ----------------------------------------------------------------------= > ==// > +// > +// This file implements the PseudoSourceValue class. > +// > +// > = > = > = > ----------------------------------------------------------------------= > ==// > + > +#include "llvm/CodeGen/PseudoSourceValue.h" > +#include "llvm/DerivedTypes.h" > +#include "llvm/Support/ManagedStatic.h" > + > +namespace llvm { > + static ManagedStatic PSVs; > + > + const PseudoSourceValue &PseudoSourceValue::getFixedStack() > { return (*PSVs)[0]; } > + const PseudoSourceValue &PseudoSourceValue::getStack() { return > (*PSVs)[1]; } > + const PseudoSourceValue &PseudoSourceValue::getGOT() { return > (*PSVs)[2]; } > + const PseudoSourceValue &PseudoSourceValue::getConstantPool() > { return (*PSVs)[3]; } > + const PseudoSourceValue &PseudoSourceValue::getJumpTable() > { return (*PSVs)[4]; } > + > + static const char *PSVNames[] = { > + "FixedStack", > + "Stack", > + "GOT", > + "ConstantPool", > + "JumpTable" > + }; > + > + PseudoSourceValue::PseudoSourceValue() : > + Value(PointerType::getUnqual(Type::Int8Ty), > PseudoSourceValueVal) {} > + > + void PseudoSourceValue::print(std::ostream &OS) const { > + OS << PSVNames[this - *PSVs]; > + } > +} > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=46827&r1=46826&r2=46827&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Feb 6 > 16:27:42 2008 > @@ -16,6 +16,7 @@ > #include "llvm/CodeGen/MachineFrameInfo.h" > #include "llvm/CodeGen/MachineJumpTableInfo.h" > #include "llvm/CodeGen/MachineModuleInfo.h" > +#include "llvm/CodeGen/PseudoSourceValue.h" > #include "llvm/Target/TargetFrameInfo.h" > #include "llvm/Target/TargetLowering.h" > #include "llvm/Target/TargetData.h" > @@ -509,9 +510,11 @@ > SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); > if (Extend) { > return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), > - CPIdx, NULL, 0, MVT::f32); > + CPIdx, > &PseudoSourceValue::getConstantPool(), > + 0, MVT::f32); > } else { > - return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0); > + return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, > + &PseudoSourceValue::getConstantPool(), 0); > } > } > > @@ -796,6 +799,7 @@ > case ISD::TargetExternalSymbol: > case ISD::VALUETYPE: > case ISD::SRCVALUE: > + case ISD::MEMOPERAND: > case ISD::STRING: > case ISD::CONDCODE: > // Primitives must all be legal. > @@ -1316,8 +1320,15 @@ > MVT::ValueType IdxVT = Tmp3.getValueType(); > MVT::ValueType PtrVT = TLI.getPointerTy(); > SDOperand StackPtr = DAG.CreateStackTemporary(VT); > + > + FrameIndexSDNode *StackPtrFI = > dyn_cast(StackPtr.Val); > + assert(StackPtrFI); > + int SPFI = StackPtrFI->getIndex(); > + > // Store the vector. > - SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, > StackPtr, NULL, 0); > + SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, > + > &PseudoSourceValue::getFixedStack(), > + SPFI); > > // Truncate or zero extend offset to target pointer type. > unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : > ISD::ZERO_EXTEND; > @@ -1327,9 +1338,11 @@ > Tmp3 = DAG.getNode(ISD::MUL, IdxVT, > Tmp3,DAG.getConstant(EltSize, IdxVT)); > SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, > StackPtr); > // Store the scalar value. > - Ch = DAG.getStore(Ch, Tmp2, StackPtr2, NULL, 0); > + Ch = DAG.getStore(Ch, Tmp2, StackPtr2, > + &PseudoSourceValue::getFixedStack(), SPFI); > // Load the updated vector. > - Result = DAG.getLoad(VT, Ch, StackPtr, NULL, 0); > + Result = DAG.getLoad(VT, Ch, StackPtr, > + &PseudoSourceValue::getFixedStack(), > SPFI); > break; > } > } > @@ -1678,8 +1691,10 @@ > SDOperand LD; > switch (EntrySize) { > default: assert(0 && "Size of jump table not supported yet."); > break; > - case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, NULL, 0); > break; > - case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, NULL, 0); > break; > + case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, > + &PseudoSourceValue::getJumpTable(), > 0); break; > + case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, > + &PseudoSourceValue::getJumpTable(), > 0); break; > } > > Addr = LD; > @@ -3240,16 +3255,14 @@ > } > break; > case TargetLowering::Expand: { > - SrcValueSDNode *SV = cast(Node->getOperand(2)); > - SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, > - SV->getValue(), SV- > >getOffset()); > + const Value *V = cast(Node->getOperand(2))- > >getValue(); > + SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, > Tmp2, V, 0); > // Increment the pointer, VAList, to the next vaarg > Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, > DAG.getConstant(MVT::getSizeInBits(VT)/8, > TLI.getPointerTy())); > // Store the incremented VAList to the legalized pointer > - Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV- > >getValue(), > - SV->getOffset()); > + Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0); > // Load the actual argument out of the pointer VAList > Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0); > Tmp1 = LegalizeOp(Result.getValue(1)); > @@ -3285,12 +3298,10 @@ > case TargetLowering::Expand: > // This defaults to loading a pointer from the input and > storing it to the > // output, returning the chain. > - SrcValueSDNode *SVD = cast(Node- > >getOperand(3)); > - SrcValueSDNode *SVS = cast(Node- > >getOperand(4)); > - Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD- > >getValue(), > - SVD->getOffset()); > - Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, SVS- > >getValue(), > - SVS->getOffset()); > + const Value *VD = cast(Node->getOperand(3))- > >getValue(); > + const Value *VS = cast(Node->getOperand(4))- > >getValue(); > + Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VD, 0); > + Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VS, 0); > break; > } > break; > @@ -4285,16 +4296,14 @@ > Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2)); > Result = TLI.CustomPromoteOperation(Tmp3, DAG); > } else { > - SrcValueSDNode *SV = cast(Node->getOperand(2)); > - SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, > - SV->getValue(), SV- > >getOffset()); > + const Value *V = cast(Node->getOperand(2))- > >getValue(); > + SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, > Tmp2, V, 0); > // Increment the pointer, VAList, to the next vaarg > Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, > DAG.getConstant(MVT::getSizeInBits(VT)/8, > TLI.getPointerTy())); > // Store the incremented VAList to the legalized pointer > - Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV- > >getValue(), > - SV->getOffset()); > + Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0); > // Load the actual argument out of the pointer VAList > Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, > 0, VT); > } > @@ -4750,6 +4759,10 @@ > // Create the stack frame object. > SDOperand FIPtr = DAG.CreateStackTemporary(SlotVT); > > + FrameIndexSDNode *StackPtrFI = dyn_cast(FIPtr); > + assert(StackPtrFI); > + int SPFI = StackPtrFI->getIndex(); > + > unsigned SrcSize = MVT::getSizeInBits(SrcOp.getValueType()); > unsigned SlotSize = MVT::getSizeInBits(SlotVT); > unsigned DestSize = MVT::getSizeInBits(DestVT); > @@ -4758,10 +4771,14 @@ > // later than DestVT. > SDOperand Store; > if (SrcSize > SlotSize) > - Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr, > NULL, 0,SlotVT); > + Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr, > + &PseudoSourceValue::getFixedStack(), > + SPFI, SlotVT); > else { > assert(SrcSize == SlotSize && "Invalid store"); > - Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0); > + Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, > + &PseudoSourceValue::getFixedStack(), > + SPFI, SlotVT); > } > > // Result is a load from the stack slot. > @@ -4776,9 +4793,15 @@ > // Create a vector sized/aligned stack slot, store the value to > element #0, > // then load the whole vector back out. > SDOperand StackPtr = DAG.CreateStackTemporary(Node- > >getValueType(0)); > + > + FrameIndexSDNode *StackPtrFI = > dyn_cast(StackPtr); > + assert(StackPtrFI); > + int SPFI = StackPtrFI->getIndex(); > + > SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node- > >getOperand(0), StackPtr, > - NULL, 0); > - return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, NULL, 0); > + &PseudoSourceValue::getFixedStack(), > SPFI); > + return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, > + &PseudoSourceValue::getFixedStack(), SPFI); > } > > > @@ -4842,7 +4865,8 @@ > } > Constant *CP = ConstantVector::get(CV); > SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); > - return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0); > + return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, > + &PseudoSourceValue::getConstantPool(), 0); > } > > if (SplatValue.Val) { // Splat of one value? > @@ -5184,11 +5208,14 @@ > CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, > CstOffset); > SDOperand FudgeInReg; > if (DestTy == MVT::f32) > - FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, > NULL, 0); > + FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, > + > &PseudoSourceValue::getConstantPool(), 0); > else if (MVT::getSizeInBits(DestTy) > > MVT::getSizeInBits(MVT::f32)) > // FIXME: Avoid the extend by construction the right > constantpool? > FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, > DAG.getEntryNode(), > - CPIdx, NULL, 0, MVT::f32); > + CPIdx, > + > &PseudoSourceValue::getConstantPool(), 0, > + MVT::f32); > else > assert(0 && "Unexpected conversion"); > > @@ -5330,11 +5357,14 @@ > CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); > SDOperand FudgeInReg; > if (DestVT == MVT::f32) > - FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, > NULL, 0); > + FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, > + &PseudoSourceValue::getConstantPool(), > 0); > else { > - FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT, > - DAG.getEntryNode(), CPIdx, > - NULL, 0, MVT::f32)); > + FudgeInReg = > + LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT, > + DAG.getEntryNode(), CPIdx, > + > &PseudoSourceValue::getConstantPool(), 0, > + MVT::f32)); > } > > return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg); > @@ -6743,10 +6773,16 @@ > // Lower to a store/load so that it can be split. > // FIXME: this could be improved probably. > SDOperand Ptr = DAG.CreateStackTemporary(InOp.getValueType()); > + FrameIndexSDNode *FI = dyn_cast(Ptr.Val); > + assert(FI && "Expecting CreateStackTemporary to return a > frame index.\n"); > > SDOperand St = DAG.getStore(DAG.getEntryNode(), > - InOp, Ptr, NULL, 0); > - InOp = DAG.getLoad(Op.getValueType(), St, Ptr, NULL, 0); > + InOp, Ptr, > + > &PseudoSourceValue::getFixedStack(), > + FI->getIndex()); > + InOp = DAG.getLoad(Op.getValueType(), St, Ptr, > + &PseudoSourceValue::getFixedStack(), > + FI->getIndex()); > } > // Split the vector and convert each of the pieces now. > SplitVectorOp(InOp, Lo, Hi); > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp?rev=46827&r1=46826&r2=46827&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Wed Feb 6 > 16:27:42 2008 > @@ -277,15 +277,27 @@ > return N; > } > > -/// CountOperands The inputs to target nodes have any actual > inputs first, > -/// followed by an optional chain operand, then flag operands. > Compute the > -/// number of actual operands that will go into the machine instr. > +/// CountOperands - The inputs to target nodes have any actual > inputs first, > +/// followed by optional memory operands chain operand, then flag > operands. > +/// Compute the number of actual operands that will go into the > machine istr. > unsigned ScheduleDAG::CountOperands(SDNode *Node) { > unsigned N = Node->getNumOperands(); > while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag) > --N; > if (N && Node->getOperand(N - 1).getValueType() == MVT::Other) > --N; // Ignore chain if it exists. > + while (N && MemOperandSDNode::classof(Node->getOperand(N - 1).Val)) > + --N; // Ignore MemOperand nodes > + return N; > +} > + > +/// CountMemOperands - Find the index of the last MemOperandSDNode > operand > +unsigned ScheduleDAG::CountMemOperands(SDNode *Node) { > + unsigned N = Node->getNumOperands(); > + while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag) > + --N; > + if (N && Node->getOperand(N - 1).getValueType() == MVT::Other) > + --N; // Ignore chain if it exists. > return N; > } > > @@ -517,6 +529,10 @@ > > } > > +void ScheduleDAG::AddMemOperand(MachineInstr *MI, const MemOperand > &MO) { > + MI->addMemOperand(MO); > +} > + > // Returns the Register Class of a subregister > static const TargetRegisterClass *getSubRegisterRegClass( > const TargetRegisterClass *TRC, > @@ -675,6 +691,7 @@ > > unsigned NumResults = CountResults(Node); > unsigned NodeOperands = CountOperands(Node); > + unsigned NodeMemOperands = CountMemOperands(Node); > unsigned NumMIOperands = NodeOperands + NumResults; > bool HasPhysRegOuts = (NumResults > II.getNumDefs()) && > II.getImplicitDefs() != 0; > @@ -697,6 +714,10 @@ > for (unsigned i = 0; i != NodeOperands; ++i) > AddOperand(MI, Node->getOperand(i), i+II.getNumDefs(), &II, > VRBaseMap); > > + // Emit all of the memory operands of this instruction > + for (unsigned i = NodeOperands; i != NodeMemOperands; ++i) > + AddMemOperand(MI, cast(Node->getOperand(i))- > >MO); > + > // Commute node if it has been determined to be profitable. > if (CommuteSet.count(Node)) { > MachineInstr *NewMI = TII->commuteInstruction(MI); > @@ -737,6 +758,7 @@ > case ISD::TokenFactor: > case ISD::LABEL: > case ISD::DECLARE: > + case ISD::SRCVALUE: > break; > case ISD::CopyToReg: { > unsigned InReg; > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=46827&r1=46826&r2=46827&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Feb 6 > 16:27:42 2008 > @@ -21,6 +21,7 @@ > #include "llvm/CodeGen/MachineConstantPool.h" > #include "llvm/CodeGen/MachineFrameInfo.h" > #include "llvm/CodeGen/MachineModuleInfo.h" > +#include "llvm/CodeGen/PseudoSourceValue.h" > #include "llvm/Support/MathExtras.h" > #include "llvm/Target/MRegisterInfo.h" > #include "llvm/Target/TargetData.h" > @@ -361,10 +362,16 @@ > case ISD::Register: > ID.AddInteger(cast(N)->getReg()); > break; > - case ISD::SRCVALUE: { > - SrcValueSDNode *SV = cast(N); > - ID.AddPointer(SV->getValue()); > - ID.AddInteger(SV->getOffset()); > + case ISD::SRCVALUE: > + ID.AddPointer(cast(N)->getValue()); > + break; > + case ISD::MEMOPERAND: { > + const MemOperand &MO = cast(N)->MO; > + ID.AddPointer(MO.getValue()); > + ID.AddInteger(MO.getFlags()); > + ID.AddInteger(MO.getOffset()); > + ID.AddInteger(MO.getSize()); > + ID.AddInteger(MO.getAlignment()); > break; > } > case ISD::FrameIndex: > @@ -937,18 +944,42 @@ > return SDOperand(N, 0); > } > > -SDOperand SelectionDAG::getSrcValue(const Value *V, int Offset) { > +SDOperand SelectionDAG::getSrcValue(const Value *V) { > assert((!V || isa(V->getType())) && > "SrcValue is not a pointer?"); > > FoldingSetNodeID ID; > AddNodeIDNode(ID, ISD::SRCVALUE, getVTList(MVT::Other), 0, 0); > ID.AddPointer(V); > - ID.AddInteger(Offset); > + > void *IP = 0; > if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) > return SDOperand(E, 0); > - SDNode *N = new SrcValueSDNode(V, Offset); > + > + SDNode *N = new SrcValueSDNode(V); > + CSEMap.InsertNode(N, IP); > + AllNodes.push_back(N); > + return SDOperand(N, 0); > +} > + > +SDOperand SelectionDAG::getMemOperand(const MemOperand &MO) { > + const Value *v = MO.getValue(); > + assert((!v || isa(v->getType())) && > + "SrcValue is not a pointer?"); > + > + FoldingSetNodeID ID; > + AddNodeIDNode(ID, ISD::MEMOPERAND, getVTList(MVT::Other), 0, 0); > + ID.AddPointer(v); > + ID.AddInteger(MO.getFlags()); > + ID.AddInteger(MO.getOffset()); > + ID.AddInteger(MO.getSize()); > + ID.AddInteger(MO.getAlignment()); > + > + void *IP = 0; > + if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) > + return SDOperand(E, 0); > + > + SDNode *N = new MemOperandSDNode(MO); > CSEMap.InsertNode(N, IP); > AllNodes.push_back(N); > return SDOperand(N, 0); > @@ -3479,6 +3510,7 @@ > void ConstantPoolSDNode::ANCHOR() {} > void BasicBlockSDNode::ANCHOR() {} > void SrcValueSDNode::ANCHOR() {} > +void MemOperandSDNode::ANCHOR() {} > void RegisterSDNode::ANCHOR() {} > void ExternalSymbolSDNode::ANCHOR() {} > void CondCodeSDNode::ANCHOR() {} > @@ -3503,6 +3535,26 @@ > TheGlobal = const_cast(GA); > } > > +/// getMemOperand - Return a MemOperand object describing the memory > +/// reference performed by this load or store. > +MemOperand LSBaseSDNode::getMemOperand() const { > + int Size = (MVT::getSizeInBits(getMemoryVT()) + 7) >> 3; > + int Flags = > + getOpcode() == ISD::LOAD ? MemOperand::MOLoad : > MemOperand::MOStore; > + if (IsVolatile) Flags |= MemOperand::MOVolatile; > + > + // Check if the load references a frame index, and does not have > + // an SV attached. > + const FrameIndexSDNode *FI = > + dyn_cast(getBasePtr().Val); > + if (!getSrcValue() && FI) > + return MemOperand(&PseudoSourceValue::getFixedStack(), Flags, > + FI->getIndex(), Size, Alignment); > + else > + return MemOperand(getSrcValue(), Flags, > + getSrcValueOffset(), Size, Alignment); > +} > + > /// Profile - Gather unique data for the node. > /// > void SDNode::Profile(FoldingSetNodeID &ID) { > @@ -3695,6 +3747,7 @@ > case ISD::PCMARKER: return "PCMarker"; > case ISD::READCYCLECOUNTER: return "ReadCycleCounter"; > case ISD::SRCVALUE: return "SrcValue"; > + case ISD::MEMOPERAND: return "MemOperand"; > case ISD::EntryToken: return "EntryToken"; > case ISD::TokenFactor: return "TokenFactor"; > case ISD::AssertSext: return "AssertSext"; > @@ -4000,9 +4053,14 @@ > cerr << "'" << ES->getSymbol() << "'"; > } else if (const SrcValueSDNode *M = > dyn_cast(this)) { > if (M->getValue()) > - cerr << "<" << M->getValue() << ":" << M->getOffset() << ">"; > + cerr << "<" << M->getValue() << ">"; > + else > + cerr << ""; > + } else if (const MemOperandSDNode *M = > dyn_cast(this)) { > + if (M->MO.getValue()) > + cerr << "<" << M->MO.getValue() << ":" << M->MO.getOffset() > << ">"; > else > - cerr << "getOffset() << ">"; > + cerr << "MO.getOffset() << ">"; > } else if (const VTSDNode *N = dyn_cast(this)) { > cerr << ":" << MVT::getValueTypeString(N->getVT()); > } else if (const LoadSDNode *LD = dyn_cast(this)) { > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp?rev=46827&r1=46826&r2=46827&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp > (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp Wed > Feb 6 16:27:42 2008 > @@ -142,9 +142,14 @@ > Op += "'" + std::string(ES->getSymbol()) + "'"; > } else if (const SrcValueSDNode *M = > dyn_cast(Node)) { > if (M->getValue()) > - Op += "<" + M->getValue()->getName() + ":" + itostr(M- > >getOffset()) + ">"; > + Op += "<" + M->getValue()->getName() + ">"; > else > - Op += "getOffset()) + ">"; > + Op += ""; > + } else if (const MemOperandSDNode *M = > dyn_cast(Node)) { > + if (M->MO.getValue()) > + Op += "<" + M->MO.getValue()->getName() + ":" + itostr(M- > >MO.getOffset()) + ">"; > + else > + Op += "MO.getOffset()) + ">"; > } else if (const VTSDNode *N = dyn_cast(Node)) { > Op = Op + " VT=" + MVT::getValueTypeString(N->getVT()); > } else if (const StringSDNode *N = dyn_cast(Node)) { > > Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=46827&r1=46826&r2=46827&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Feb 6 > 16:27:42 2008 > @@ -905,9 +905,8 @@ > // memory location argument. > MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); > SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); > - SrcValueSDNode *SV = cast(Op.getOperand(2)); > - return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV- > >getValue(), > - SV->getOffset()); > + const Value *SV = cast(Op.getOperand(2))- > >getValue(); > + return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0); > } > > static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG, > > Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp?rev=46827&r1=46826&r2=46827&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp (original) > +++ llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp Wed Feb 6 > 16:27:42 2008 > @@ -491,10 +491,9 @@ > case ISD::VAARG: { > SDOperand Chain = Op.getOperand(0); > SDOperand VAListP = Op.getOperand(1); > - SrcValueSDNode *VAListS = cast(Op.getOperand(2)); > + const Value *VAListS = cast(Op.getOperand(2))- > >getValue(); > > - SDOperand Base = DAG.getLoad(MVT::i64, Chain, VAListP, VAListS- > >getValue(), > - VAListS->getOffset()); > + SDOperand Base = DAG.getLoad(MVT::i64, Chain, VAListP, VAListS, > 0); > SDOperand Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP, > DAG.getConstant(8, MVT::i64)); > SDOperand Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, > Base.getValue(1), > @@ -527,13 +526,11 @@ > SDOperand Chain = Op.getOperand(0); > SDOperand DestP = Op.getOperand(1); > SDOperand SrcP = Op.getOperand(2); > - SrcValueSDNode *DestS = cast(Op.getOperand(3)); > - SrcValueSDNode *SrcS = cast(Op.getOperand(4)); > + const Value *DestS = cast(Op.getOperand(3))- > >getValue(); > + const Value *SrcS = cast(Op.getOperand(4))- > >getValue(); > > - SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP, > - SrcS->getValue(), SrcS->getOffset()); > - SDOperand Result = DAG.getStore(Val.getValue(1), Val, DestP, > DestS->getValue(), > - DestS->getOffset()); > + SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP, SrcS, > 0); > + SDOperand Result = DAG.getStore(Val.getValue(1), Val, DestP, > DestS, 0); > SDOperand NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP, > DAG.getConstant(8, MVT::i64)); > Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP, NULL, > 0, MVT::i32); > @@ -544,12 +541,11 @@ > case ISD::VASTART: { > SDOperand Chain = Op.getOperand(0); > SDOperand VAListP = Op.getOperand(1); > - SrcValueSDNode *VAListS = cast(Op.getOperand(2)); > + const Value *VAListS = cast(Op.getOperand(2))- > >getValue(); > > // vastart stores the address of the VarArgsBase and VarArgsOffset > SDOperand FR = DAG.getFrameIndex(VarArgsBase, MVT::i64); > - SDOperand S1 = DAG.getStore(Chain, FR, VAListP, VAListS- > >getValue(), > - VAListS->getOffset()); > + SDOperand S1 = DAG.getStore(Chain, FR, VAListP, VAListS, 0); > SDOperand SA2 = DAG.getNode(ISD::ADD, MVT::i64, VAListP, > DAG.getConstant(8, MVT::i64)); > return DAG.getTruncStore(S1, DAG.getConstant(VarArgsOffset, > MVT::i64), > > Modified: llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp?rev=46827&r1=46826&r2=46827&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp (original) > +++ llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp Wed Feb 6 > 16:27:42 2008 > @@ -581,16 +581,16 @@ > } > case ISD::VAARG: { > MVT::ValueType VT = getPointerTy(); > - SrcValueSDNode *SV = cast(Op.getOperand(2)); > + const Value *SV = cast(Op.getOperand(2))- > >getValue(); > SDOperand VAList = DAG.getLoad(VT, Op.getOperand(0), > Op.getOperand(1), > - SV->getValue(), SV->getOffset()); > + SV, 0); > // Increment the pointer, VAList, to the next vaarg > SDOperand VAIncr = DAG.getNode(ISD::ADD, VT, VAList, > > DAG.getConstant(MVT::getSizeInBits(VT)/8, > VT)); > // Store the incremented VAList to the legalized pointer > VAIncr = DAG.getStore(VAList.getValue(1), VAIncr, > - Op.getOperand(1), SV->getValue(), SV- > >getOffset()); > + Op.getOperand(1), SV, 0); > // Load the actual argument out of the pointer VAList > return DAG.getLoad(Op.getValueType(), VAIncr, VAList, NULL, 0); > } > @@ -598,9 +598,8 @@ > // vastart just stores the address of the VarArgsFrameIndex slot > into the > // memory location argument. > SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i64); > - SrcValueSDNode *SV = cast(Op.getOperand(2)); > - return DAG.getStore(Op.getOperand(0), FR, > - Op.getOperand(1), SV->getValue(), SV- > >getOffset()); > + const Value *SV = cast(Op.getOperand(2))- > >getValue(); > + return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, > 0); > } > // Frame & Return address. Currently unimplemented > case ISD::RETURNADDR: break; > > Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=46827&r1=46826&r2=46827&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original) > +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Wed Feb 6 > 16:27:42 2008 > @@ -24,6 +24,7 @@ > #include "llvm/CodeGen/MachineFunction.h" > #include "llvm/CodeGen/MachineInstrBuilder.h" > #include "llvm/CodeGen/MachineRegisterInfo.h" > +#include "llvm/CodeGen/PseudoSourceValue.h" > #include "llvm/CodeGen/SelectionDAG.h" > #include "llvm/Constants.h" > #include "llvm/Function.h" > @@ -1175,9 +1176,8 @@ > // memory location argument. > MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); > SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); > - SrcValueSDNode *SV = cast(Op.getOperand(2)); > - return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV- > >getValue(), > - SV->getOffset()); > + const Value *SV = cast(Op.getOperand(2))- > >getValue(); > + return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, > 0); > } > > // For ELF 32 ABI we follow the layout of the va_list struct. > @@ -1211,37 +1211,41 @@ > > MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); > > - SDOperand StackOffset = DAG.getFrameIndex(VarArgsStackOffset, > PtrVT); > + SDOperand StackOffsetFI = DAG.getFrameIndex(VarArgsStackOffset, > PtrVT); > SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); > > - SDOperand ConstFrameOffset = > DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, > - PtrVT); > - SDOperand ConstStackOffset = > DAG.getConstant(MVT::getSizeInBits(PtrVT)/8 - 1, > - PtrVT); > - SDOperand ConstFPROffset = DAG.getConstant(1, PtrVT); > + uint64_t FrameOffset = MVT::getSizeInBits(PtrVT)/8; > + SDOperand ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT); > + > + uint64_t StackOffset = MVT::getSizeInBits(PtrVT)/8 - 1; > + SDOperand ConstStackOffset = DAG.getConstant(StackOffset, PtrVT); > + > + uint64_t FPROffset = 1; > + SDOperand ConstFPROffset = DAG.getConstant(FPROffset, PtrVT); > > - SrcValueSDNode *SV = cast(Op.getOperand(2)); > + const Value *SV = cast(Op.getOperand(2))- > >getValue(); > > // Store first byte : number of int regs > SDOperand firstStore = DAG.getStore(Op.getOperand(0), ArgGPR, > - Op.getOperand(1), SV- > >getValue(), > - SV->getOffset()); > + Op.getOperand(1), SV, 0); > + uint64_t nextOffset = FPROffset; > SDOperand nextPtr = DAG.getNode(ISD::ADD, PtrVT, Op.getOperand(1), > ConstFPROffset); > > // Store second byte : number of float regs > - SDOperand secondStore = DAG.getStore(firstStore, ArgFPR, nextPtr, > - SV->getValue(), SV- > >getOffset()); > + SDOperand secondStore = > + DAG.getStore(firstStore, ArgFPR, nextPtr, SV, nextOffset); > + nextOffset += StackOffset; > nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstStackOffset); > > // Store second word : arguments given on stack > - SDOperand thirdStore = DAG.getStore(secondStore, StackOffset, > nextPtr, > - SV->getValue(), SV- > >getOffset()); > + SDOperand thirdStore = > + DAG.getStore(secondStore, StackOffsetFI, nextPtr, SV, > nextOffset); > + nextOffset += FrameOffset; > nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstFrameOffset); > > // Store third word : arguments given in registers > - return DAG.getStore(thirdStore, FR, nextPtr, SV->getValue(), > - SV->getOffset()); > + return DAG.getStore(thirdStore, FR, nextPtr, SV, nextOffset); > > } > > @@ -2199,9 +2203,11 @@ > Op.getOperand(0)); > > // STD the extended value into the stack slot. > + MemOperand MO(&PseudoSourceValue::getFixedStack(), > + MemOperand::MOStore, FrameIdx, 8, 8); > SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other, > DAG.getEntryNode(), Ext64, FIdx, > - DAG.getSrcValue(NULL)); > + DAG.getMemOperand(MO)); > // Load the value as a double. > SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0); > > @@ -3300,11 +3306,11 @@ > std::vector VTs; > VTs.push_back(MVT::i32); > VTs.push_back(MVT::Other); > - SDOperand SV = DAG.getSrcValue(LD->getSrcValue(), LD- > >getSrcValueOffset()); > + SDOperand MO = DAG.getMemOperand(LD->getMemOperand()); > SDOperand Ops[] = { > LD->getChain(), // Chain > LD->getBasePtr(), // Ptr > - SV, // SrcValue > + MO, // MemOperand > DAG.getValueType(N->getValueType(0)) // VT > }; > SDOperand BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4); > > Modified: llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp?rev=46827&r1=46826&r2=46827&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp (original) > +++ llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp Wed Feb 6 > 16:27:42 2008 > @@ -805,25 +805,23 @@ > SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32, > DAG.getRegister(SP::I6, MVT::i32), > DAG.getConstant(VarArgsFrameOffset, > MVT::i32)); > - SrcValueSDNode *SV = cast(Op.getOperand(2)); > - return DAG.getStore(Op.getOperand(0), Offset, > - Op.getOperand(1), SV->getValue(), SV- > >getOffset()); > + const Value *SV = cast(Op.getOperand(2))- > >getValue(); > + return DAG.getStore(Op.getOperand(0), Offset, Op.getOperand(1), > SV, 0); > } > case ISD::VAARG: { > SDNode *Node = Op.Val; > MVT::ValueType VT = Node->getValueType(0); > SDOperand InChain = Node->getOperand(0); > SDOperand VAListPtr = Node->getOperand(1); > - SrcValueSDNode *SV = cast(Node->getOperand(2)); > - SDOperand VAList = DAG.getLoad(getPointerTy(), InChain, > VAListPtr, > - SV->getValue(), SV->getOffset()); > + const Value *SV = cast(Node->getOperand(2))- > >getValue(); > + SDOperand VAList = DAG.getLoad(getPointerTy(), InChain, > VAListPtr, SV, 0); > // Increment the pointer, VAList, to the next vaarg > SDOperand NextPtr = DAG.getNode(ISD::ADD, getPointerTy(), VAList, > > DAG.getConstant(MVT::getSizeInBits(VT)/8, > getPointerTy())); > // Store the incremented VAList to the legalized pointer > InChain = DAG.getStore(VAList.getValue(1), NextPtr, > - VAListPtr, SV->getValue(), SV- > >getOffset()); > + VAListPtr, SV, 0); > // Load the actual argument out of the pointer VAList, unless > this is an > // f64 load. > if (VT != MVT::f64) { > > Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=46827&r1=46826&r2=46827&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) > +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Feb 6 > 16:27:42 2008 > @@ -32,6 +32,7 @@ > #include "llvm/CodeGen/MachineInstrBuilder.h" > #include "llvm/CodeGen/MachineModuleInfo.h" > #include "llvm/CodeGen/MachineRegisterInfo.h" > +#include "llvm/CodeGen/PseudoSourceValue.h" > #include "llvm/CodeGen/SelectionDAG.h" > #include "llvm/Support/MathExtras.h" > #include "llvm/Support/Debug.h" > @@ -1089,7 +1090,8 @@ > SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy()); > if (isByVal) > return FIN; > - return DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0); > + return DAG.getLoad(VA.getValVT(), Root, FIN, > + &PseudoSourceValue::getFixedStack(), FI); > } > > SDOperand > @@ -1217,7 +1219,10 @@ > unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs], > X86::GR64RegisterClass); > SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i64); > - SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, > NULL, 0); > + SDOperand Store = > + DAG.getStore(Val.getValue(1), Val, FIN, > + &PseudoSourceValue::getFixedStack(), > + RegSaveFrameIndex); > MemOps.push_back(Store); > FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, > DAG.getIntPtrConstant(8)); > @@ -1230,7 +1235,10 @@ > unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs], > X86::VR128RegisterClass); > SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32); > - SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, > NULL, 0); > + SDOperand Store = > + DAG.getStore(Val.getValue(1), Val, FIN, > + &PseudoSourceValue::getFixedStack(), > + RegSaveFrameIndex); > MemOps.push_back(Store); > FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, > DAG.getIntPtrConstant(16)); > @@ -1559,7 +1567,9 @@ > Flags, > DAG)); > } else { > // Store relative to framepointer. > - MemOpChains2.push_back(DAG.getStore(Chain, Source, FIN, > NULL, 0)); > + MemOpChains2.push_back( > + DAG.getStore(Chain, Source, FIN, > + &PseudoSourceValue::getFixedStack(), FI)); > } > } > } > @@ -3788,7 +3798,8 @@ > // the GV offset field. Platform check is inside > GVRequiresExtraLoad() call > // The same applies for external symbols during PIC codegen > if (Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false)) > - Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), > Result, NULL, 0); > + Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result, > + &PseudoSourceValue::getGOT(), 0); > > return Result; > } > @@ -3846,7 +3857,8 @@ > SDOperand Offset = DAG.getNode(X86ISD::Wrapper, PtrVT, TGA); > > if (GA->getGlobal()->isDeclaration()) // initial exec TLS model > - Offset = DAG.getLoad(PtrVT, DAG.getEntryNode(), Offset, NULL, 0); > + Offset = DAG.getLoad(PtrVT, DAG.getEntryNode(), Offset, > + &PseudoSourceValue::getGOT(), 0); > > // The address of the thread local variable is the add of the thread > // pointer with the offset of the variable. > @@ -3978,7 +3990,9 @@ > int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size); > SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); > SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0), > - StackSlot, NULL, 0); > + StackSlot, > + &PseudoSourceValue::getFixedStack(), > + SSFI); > > // These are really Legal; caller falls through into that case. > if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) > @@ -4019,7 +4033,8 @@ > Ops.push_back(DAG.getValueType(Op.getValueType())); > Ops.push_back(InFlag); > Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size()); > - Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot, NULL, > 0); > + Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot, > + &PseudoSourceValue::getFixedStack(), SSFI); > } > > return Result; > @@ -4057,7 +4072,8 @@ > SDOperand Value = Op.getOperand(0); > if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) { > assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to > lower!"); > - Chain = DAG.getStore(Chain, Value, StackSlot, NULL, 0); > + Chain = DAG.getStore(Chain, Value, StackSlot, > + &PseudoSourceValue::getFixedStack(), SSFI); > SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), > MVT::Other); > SDOperand Ops[] = { > Chain, StackSlot, > DAG.getValueType(Op.getOperand(0).getValueType()) > @@ -4116,7 +4132,8 @@ > } > Constant *C = ConstantVector::get(CV); > SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); > - SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, > 0, > + SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, > + > &PseudoSourceValue::getConstantPool(), 0, > false, 16); > return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask); > } > @@ -4144,7 +4161,8 @@ > } > Constant *C = ConstantVector::get(CV); > SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); > - SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, > 0, > + SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, > + > &PseudoSourceValue::getConstantPool(), 0, > false, 16); > if (MVT::isVector(VT)) { > return DAG.getNode(ISD::BIT_CONVERT, VT, > @@ -4192,7 +4210,8 @@ > } > Constant *C = ConstantVector::get(CV); > SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); > - SDOperand Mask1 = DAG.getLoad(SrcVT, DAG.getEntryNode(), CPIdx, > NULL, 0, > + SDOperand Mask1 = DAG.getLoad(SrcVT, DAG.getEntryNode(), CPIdx, > + > &PseudoSourceValue::getConstantPool(), 0, > false, 16); > SDOperand SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1); > > @@ -4220,7 +4239,8 @@ > } > C = ConstantVector::get(CV); > CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); > - SDOperand Mask2 = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, > NULL, 0, > + SDOperand Mask2 = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, > + > &PseudoSourceValue::getConstantPool(), 0, > false, 16); > SDOperand Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2); > > @@ -4676,14 +4696,13 @@ > } > > SDOperand X86TargetLowering::LowerVASTART(SDOperand Op, SelectionDAG > &DAG) { > - SrcValueSDNode *SV = cast(Op.getOperand(2)); > + const Value *SV = cast(Op.getOperand(2))- > >getValue(); > > if (!Subtarget->is64Bit()) { > // vastart just stores the address of the VarArgsFrameIndex slot > into the > // memory location argument. > SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, > getPointerTy()); > - return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV- > >getValue(), > - SV->getOffset()); > + return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV, > 0); > } > > // __va_list_tag: > @@ -4696,28 +4715,26 @@ > // Store gp_offset > SDOperand Store = DAG.getStore(Op.getOperand(0), > DAG.getConstant(VarArgsGPOffset, > MVT::i32), > - FIN, SV->getValue(), SV- > >getOffset()); > + FIN, SV, 0); > MemOps.push_back(Store); > > // Store fp_offset > FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, > DAG.getIntPtrConstant(4)); > Store = DAG.getStore(Op.getOperand(0), > DAG.getConstant(VarArgsFPOffset, MVT::i32), > - FIN, SV->getValue(), SV->getOffset()); > + FIN, SV, 0); > MemOps.push_back(Store); > > // Store ptr to overflow_arg_area > FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, > DAG.getIntPtrConstant(4)); > SDOperand OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, > getPointerTy()); > - Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV->getValue(), > - SV->getOffset()); > + Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV, 0); > MemOps.push_back(Store); > > // Store ptr to reg_save_area. > FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, > DAG.getIntPtrConstant(8)); > SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, > getPointerTy()); > - Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV->getValue(), > - SV->getOffset()); > + Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV, 0); > MemOps.push_back(Store); > return DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOps[0], > MemOps.size()); > } > @@ -4727,18 +4744,15 @@ > SDOperand Chain = Op.getOperand(0); > SDOperand DstPtr = Op.getOperand(1); > SDOperand SrcPtr = Op.getOperand(2); > - SrcValueSDNode *DstSV = cast(Op.getOperand(3)); > - SrcValueSDNode *SrcSV = cast(Op.getOperand(4)); > + const Value *DstSV = cast(Op.getOperand(3))- > >getValue(); > + const Value *SrcSV = cast(Op.getOperand(4))- > >getValue(); > > - SrcPtr = DAG.getLoad(getPointerTy(), Chain, SrcPtr, > - SrcSV->getValue(), SrcSV->getOffset()); > + SrcPtr = DAG.getLoad(getPointerTy(), Chain, SrcPtr, SrcSV, 0); > Chain = SrcPtr.getValue(1); > for (unsigned i = 0; i < 3; ++i) { > - SDOperand Val = DAG.getLoad(MVT::i64, Chain, SrcPtr, > - SrcSV->getValue(), SrcSV- > >getOffset()); > + SDOperand Val = DAG.getLoad(MVT::i64, Chain, SrcPtr, SrcSV, 0); > Chain = Val.getValue(1); > - Chain = DAG.getStore(Chain, Val, DstPtr, > - DstSV->getValue(), DstSV->getOffset()); > + Chain = DAG.getStore(Chain, Val, DstPtr, DstSV, 0); > if (i == 2) > break; > SrcPtr = DAG.getNode(ISD::ADD, getPointerTy(), SrcPtr, > @@ -4918,7 +4932,7 @@ > SDOperand FPtr = Op.getOperand(2); // nested function > SDOperand Nest = Op.getOperand(3); // 'nest' parameter value > > - SrcValueSDNode *TrmpSV = cast(Op.getOperand(4)); > + const Value *TrmpAddr = cast(Op.getOperand(4))- > >getValue(); > > const X86InstrInfo *TII = > ((X86TargetMachine&)getTargetMachine()).getInstrInfo(); > @@ -4942,33 +4956,31 @@ > unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq > r11 > SDOperand Addr = Trmp; > OutChains[0] = DAG.getStore(Root, DAG.getConstant(OpCode, > MVT::i16), Addr, > - TrmpSV->getValue(), TrmpSV- > >getOffset()); > + TrmpAddr, 0); > > Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(2, > MVT::i64)); > - OutChains[1] = DAG.getStore(Root, FPtr, Addr, TrmpSV->getValue(), > - TrmpSV->getOffset() + 2, false, 2); > + OutChains[1] = DAG.getStore(Root, FPtr, Addr, TrmpAddr, 2, > false, 2); > > // Load the 'nest' parameter value into R10. > // R10 is specified in X86CallingConv.td > OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 > Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(10, > MVT::i64)); > OutChains[2] = DAG.getStore(Root, DAG.getConstant(OpCode, > MVT::i16), Addr, > - TrmpSV->getValue(), TrmpSV- > >getOffset() + 10); > + TrmpAddr, 10); > > Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(12, > MVT::i64)); > - OutChains[3] = DAG.getStore(Root, Nest, Addr, TrmpSV->getValue(), > - TrmpSV->getOffset() + 12, false, 2); > + OutChains[3] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 12, > false, 2); > > // Jump to the nested function. > OpCode = (JMP64r << 8) | REX_WB; // jmpq *... > Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(20, > MVT::i64)); > OutChains[4] = DAG.getStore(Root, DAG.getConstant(OpCode, > MVT::i16), Addr, > - TrmpSV->getValue(), TrmpSV- > >getOffset() + 20); > + TrmpAddr, 20); > > unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11 > Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(22, > MVT::i64)); > OutChains[5] = DAG.getStore(Root, DAG.getConstant(ModRM, > MVT::i8), Addr, > - TrmpSV->getValue(), TrmpSV- > >getOffset() + 22); > + TrmpAddr, 22); > > SDOperand Ops[] = > { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, > 6) }; > @@ -5026,20 +5038,18 @@ > const unsigned char N86Reg = > ((X86RegisterInfo*)RegInfo)->getX86RegNum(NestReg); > OutChains[0] = DAG.getStore(Root, DAG.getConstant(MOV32ri| > N86Reg, MVT::i8), > - Trmp, TrmpSV->getValue(), TrmpSV- > >getOffset()); > + Trmp, TrmpAddr, 0); > > Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(1, > MVT::i32)); > - OutChains[1] = DAG.getStore(Root, Nest, Addr, TrmpSV->getValue(), > - TrmpSV->getOffset() + 1, false, 1); > + OutChains[1] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 1, > false, 1); > > const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP); > Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(5, > MVT::i32)); > OutChains[2] = DAG.getStore(Root, DAG.getConstant(JMP, MVT::i8), > Addr, > - TrmpSV->getValue() + 5, TrmpSV- > >getOffset()); > + TrmpAddr, 5, false, 1); > > Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(6, > MVT::i32)); > - OutChains[3] = DAG.getStore(Root, Disp, Addr, TrmpSV->getValue(), > - TrmpSV->getOffset() + 6, false, 1); > + OutChains[3] = DAG.getStore(Root, Disp, Addr, TrmpAddr, 6, > false, 1); > > SDOperand Ops[] = > { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, > 4) }; > > Modified: llvm/trunk/utils/TableGen/DAGISelEmitter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelEmitter.cpp?rev=46827&r1=46826&r2=46827&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/utils/TableGen/DAGISelEmitter.cpp (original) > +++ llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Wed Feb 6 16:27:42 > 2008 > @@ -313,6 +313,12 @@ > std::vector > OrigChains; > std::set Duplicates; > > + /// LSI - Load/Store information. > + /// Save loads/stores matched by a pattern, and generate a > MemOperandSDNode > + /// for each memory access. This facilitates the use of > AliasAnalysis in > + /// the backend. > + std::vector LSI; > + > /// GeneratedCode - This is the buffer that we emit code to. The > first int > /// indicates whether this is an exit predicate (something that > should be > /// tested, and if true, the match fails) [when 1], or normal code > to emit > @@ -373,6 +379,16 @@ > void EmitMatchCode(TreePatternNode *N, TreePatternNode *P, > const std::string &RootName, const std::string > &ChainSuffix, > bool &FoundChain) { > + > + // Save loads/stores matched by a pattern. > + if (!N->isLeaf() && N->getName().empty()) { > + std::string EnumName = N->getOperator()- > >getValueAsString("Opcode"); > + if (EnumName == "ISD::LOAD" || > + EnumName == "ISD::STORE") { > + LSI.push_back(RootName); > + } > + } > + > bool isRoot = (P == NULL); > // Emit instruction predicates. Each predicate is just a string > for now. > if (isRoot) { > @@ -944,6 +960,18 @@ > } > } > > + // Generate MemOperandSDNodes nodes for each memory accesses > covered by this > + // pattern. > + if (isRoot) { > + std::vector::const_iterator mi, mie; > + for (mi = LSI.begin(), mie = LSI.end(); mi != mie; ++mi) { > + emitCode("SDOperand LSI_" + *mi + " = " > + "CurDAG->getMemOperand(cast(" + > + *mi + ")->getMemOperand());"); > + AllOps.push_back("LSI_" + *mi); > + } > + } > + > // Emit all the chain and CopyToReg stuff. > bool ChainEmitted = NodeHasChain; > if (NodeHasChain) > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From evan.cheng at apple.com Thu Feb 7 02:53:49 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 07 Feb 2008 08:53:49 -0000 Subject: [llvm-commits] [llvm] r46850 - in /llvm/trunk: lib/Target/X86/X86ISelDAGToDAG.cpp lib/Target/X86/X86Instr64bit.td lib/Target/X86/X86InstrInfo.td lib/Target/X86/X86Subtarget.cpp lib/Target/X86/X86Subtarget.h test/CodeGen/X86/pic_jumptable.ll test/CodeGen/X86/x86-64-gv-offset.ll Message-ID: <200802070853.m178rosx029306@zion.cs.uiuc.edu> Author: evancheng Date: Thu Feb 7 02:53:49 2008 New Revision: 46850 URL: http://llvm.org/viewvc/llvm-project?rev=46850&view=rev Log: Fix a x86-64 codegen deficiency. Allow gv + offset when using rip addressing mode. Before: _main: subq $8, %rsp leaq _X(%rip), %rax movsd 8(%rax), %xmm1 movss _X(%rip), %xmm0 call _t xorl %ecx, %ecx movl %ecx, %eax addq $8, %rsp ret Now: _main: subq $8, %rsp movsd _X+8(%rip), %xmm1 movss _X(%rip), %xmm0 call _t xorl %ecx, %ecx movl %ecx, %eax addq $8, %rsp ret Notice there is another idiotic codegen issue that needs to be fixed asap: xorl %ecx, %ecx movl %ecx, %eax Added: llvm/trunk/test/CodeGen/X86/x86-64-gv-offset.ll Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp llvm/trunk/lib/Target/X86/X86Instr64bit.td llvm/trunk/lib/Target/X86/X86InstrInfo.td llvm/trunk/lib/Target/X86/X86Subtarget.cpp llvm/trunk/lib/Target/X86/X86Subtarget.h llvm/trunk/test/CodeGen/X86/pic_jumptable.ll Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=46850&r1=46849&r2=46850&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Thu Feb 7 02:53:49 2008 @@ -63,7 +63,7 @@ int FrameIndex; } Base; - bool isRIPRel; // RIP relative? + bool isRIPRel; // RIP as base? unsigned Scale; SDOperand IndexReg; unsigned Disp; @@ -664,7 +664,9 @@ case X86ISD::Wrapper: { bool is64Bit = Subtarget->is64Bit(); // Under X86-64 non-small code model, GV (and friends) are 64-bits. - if (is64Bit && TM.getCodeModel() != CodeModel::Small) + // Also, base and index reg must be 0 in order to use rip as base. + if (is64Bit && (TM.getCodeModel() != CodeModel::Small || + AM.Base.Reg.Val || AM.IndexReg.Val)) break; if (AM.GV != 0 || AM.CP != 0 || AM.ES != 0 || AM.JT != -1) break; @@ -672,39 +674,27 @@ // been picked, we can't fit the result available in the register in the // addressing mode. Duplicate GlobalAddress or ConstantPool as displacement. if (!AlreadySelected || (AM.Base.Reg.Val && AM.IndexReg.Val)) { - bool isStatic = TM.getRelocationModel() == Reloc::Static; SDOperand N0 = N.getOperand(0); - // Mac OS X X86-64 lower 4G address is not available. - bool isAbs32 = !is64Bit || - (isStatic && Subtarget->hasLow4GUserSpaceAddress()); if (GlobalAddressSDNode *G = dyn_cast(N0)) { GlobalValue *GV = G->getGlobal(); - if (isAbs32 || isRoot) { - AM.GV = GV; - AM.Disp += G->getOffset(); - AM.isRIPRel = !isAbs32; - return false; - } + AM.GV = GV; + AM.Disp += G->getOffset(); + AM.isRIPRel = is64Bit; + return false; } else if (ConstantPoolSDNode *CP = dyn_cast(N0)) { - if (isAbs32 || isRoot) { - AM.CP = CP->getConstVal(); - AM.Align = CP->getAlignment(); - AM.Disp += CP->getOffset(); - AM.isRIPRel = !isAbs32; - return false; - } + AM.CP = CP->getConstVal(); + AM.Align = CP->getAlignment(); + AM.Disp += CP->getOffset(); + AM.isRIPRel = is64Bit; + return false; } else if (ExternalSymbolSDNode *S =dyn_cast(N0)) { - if (isAbs32 || isRoot) { - AM.ES = S->getSymbol(); - AM.isRIPRel = !isAbs32; - return false; - } + AM.ES = S->getSymbol(); + AM.isRIPRel = is64Bit; + return false; } else if (JumpTableSDNode *J = dyn_cast(N0)) { - if (isAbs32 || isRoot) { - AM.JT = J->getIndex(); - AM.isRIPRel = !isAbs32; - return false; - } + AM.JT = J->getIndex(); + AM.isRIPRel = is64Bit; + return false; } } break; @@ -719,7 +709,7 @@ break; case ISD::SHL: - if (AlreadySelected || AM.IndexReg.Val != 0 || AM.Scale != 1) + if (AlreadySelected || AM.IndexReg.Val != 0 || AM.Scale != 1 || AM.isRIPRel) break; if (ConstantSDNode *CN = dyn_cast(N.Val->getOperand(1))) { @@ -759,7 +749,8 @@ if (!AlreadySelected && AM.BaseType == X86ISelAddressMode::RegBase && AM.Base.Reg.Val == 0 && - AM.IndexReg.Val == 0) { + AM.IndexReg.Val == 0 && + !AM.isRIPRel) { if (ConstantSDNode *CN = dyn_cast(N.Val->getOperand(1))) if (CN->getValue() == 3 || CN->getValue() == 5 || CN->getValue() == 9) { AM.Scale = unsigned(CN->getValue())-1; @@ -834,6 +825,9 @@ // Scale must not be used already. if (AM.IndexReg.Val != 0 || AM.Scale != 1) break; + + // Not when RIP is used as the base. + if (AM.isRIPRel) break; ConstantSDNode *C2 = dyn_cast(N.getOperand(1)); ConstantSDNode *C1 = dyn_cast(Shift.getOperand(1)); @@ -874,7 +868,7 @@ // Is the base register already occupied? if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base.Reg.Val) { // If so, check to see if the scale index register is set. - if (AM.IndexReg.Val == 0) { + if (AM.IndexReg.Val == 0 && !AM.isRIPRel) { AM.IndexReg = N; AM.Scale = 1; return false; Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=46850&r1=46849&r2=46850&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original) +++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Thu Feb 7 02:53:49 2008 @@ -1125,16 +1125,16 @@ def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst), (MOV64mi32 addr:$dst, tconstpool:$src)>, - Requires<[SmallCode, HasLow4G, IsStatic]>; + Requires<[SmallCode, IsStatic]>; def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst), (MOV64mi32 addr:$dst, tjumptable:$src)>, - Requires<[SmallCode, HasLow4G, IsStatic]>; + Requires<[SmallCode, IsStatic]>; def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst), (MOV64mi32 addr:$dst, tglobaladdr:$src)>, - Requires<[SmallCode, HasLow4G, IsStatic]>; + Requires<[SmallCode, IsStatic]>; def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst), (MOV64mi32 addr:$dst, texternalsym:$src)>, - Requires<[SmallCode, HasLow4G, IsStatic]>; + Requires<[SmallCode, IsStatic]>; // Calls // Direct PC relative function call for small code model. 32-bit displacement Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=46850&r1=46849&r2=46850&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Thu Feb 7 02:53:49 2008 @@ -172,7 +172,6 @@ def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">; def In32BitMode : Predicate<"!Subtarget->is64Bit()">; def In64BitMode : Predicate<"Subtarget->is64Bit()">; -def HasLow4G : Predicate<"Subtarget->hasLow4GUserSpaceAddress()">; def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">; def NotSmallCode : Predicate<"TM.getCodeModel() != CodeModel::Small">; def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">; Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=46850&r1=46849&r2=46850&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original) +++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Thu Feb 7 02:53:49 2008 @@ -228,7 +228,6 @@ // FIXME: this is a known good value for Yonah. How about others? , MaxInlineSizeThreshold(128) , Is64Bit(is64Bit) - , HasLow4GUserAddress(true) , TargetType(isELF) { // Default to ELF unless otherwise specified. // Determine default and user specified characteristics @@ -300,9 +299,6 @@ ? X86Subtarget::Intel : X86Subtarget::ATT; } - if (TargetType == isDarwin && Is64Bit) - HasLow4GUserAddress = false; - if (TargetType == isDarwin || TargetType == isCygwin || TargetType == isMingw || Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=46850&r1=46849&r2=46850&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86Subtarget.h (original) +++ llvm/trunk/lib/Target/X86/X86Subtarget.h Thu Feb 7 02:53:49 2008 @@ -82,10 +82,6 @@ /// pointer size is 64 bit. bool Is64Bit; - /// HasLow4GUserAddress - True if the low 4G user-space address is available. - /// - bool HasLow4GUserAddress; - public: enum { isELF, isCygwin, isDarwin, isWindows, isMingw @@ -115,10 +111,6 @@ bool is64Bit() const { return Is64Bit; } - /// hasLow4GUserSpaceAddress - True if lower 4G user-space address is - /// available. - bool hasLow4GUserSpaceAddress() const { return HasLow4GUserAddress; } - PICStyle::Style getPICStyle() const { return PICStyle; } void setPICStyle(PICStyle::Style Style) { PICStyle = Style; } Modified: llvm/trunk/test/CodeGen/X86/pic_jumptable.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pic_jumptable.ll?rev=46850&r1=46849&r2=46850&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/pic_jumptable.ll (original) +++ llvm/trunk/test/CodeGen/X86/pic_jumptable.ll Thu Feb 7 02:53:49 2008 @@ -1,36 +1,35 @@ -; RUN: llvm-upgrade < %s | llvm-as | llc -relocation-model=pic -mtriple=i386-linux-gnu | not grep -F .text -; RUN: llvm-upgrade < %s | llvm-as | llc -relocation-model=pic -mtriple=i686-apple-darwin | not grep lea +; RUN: llvm-as < %s | llc -relocation-model=pic -mtriple=i386-linux-gnu | not grep -F .text +; RUN: llvm-as < %s | llc -relocation-model=pic -mtriple=i686-apple-darwin | not grep lea +; RUN: llvm-as < %s | llc -relocation-model=pic -mtriple=i686-apple-darwin | grep add | count 2 -implementation ; Functions: +declare void @_Z3bari(i32) -declare void %_Z3bari( int ) - -linkonce void %_Z3fooILi1EEvi(int %Y) { +define linkonce void @_Z3fooILi1EEvi(i32 %Y) { entry: - %Y_addr = alloca int ; [#uses=2] - "alloca point" = cast int 0 to int ; [#uses=0] - store int %Y, int* %Y_addr - %tmp = load int* %Y_addr ; [#uses=1] - switch int %tmp, label %bb10 [ - int 0, label %bb3 - int 1, label %bb - int 2, label %bb - int 3, label %bb - int 4, label %bb - int 5, label %bb - int 6, label %bb - int 7, label %bb - int 8, label %bb - int 9, label %bb - int 10, label %bb - int 12, label %bb1 - int 13, label %bb5 - int 14, label %bb6 - int 16, label %bb2 - int 17, label %bb4 - int 23, label %bb8 - int 27, label %bb7 - int 34, label %bb9 + %Y_addr = alloca i32 ; [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + store i32 %Y, i32* %Y_addr + %tmp = load i32* %Y_addr ; [#uses=1] + switch i32 %tmp, label %bb10 [ + i32 0, label %bb3 + i32 1, label %bb + i32 2, label %bb + i32 3, label %bb + i32 4, label %bb + i32 5, label %bb + i32 6, label %bb + i32 7, label %bb + i32 8, label %bb + i32 9, label %bb + i32 10, label %bb + i32 12, label %bb1 + i32 13, label %bb5 + i32 14, label %bb6 + i32 16, label %bb2 + i32 17, label %bb4 + i32 23, label %bb8 + i32 27, label %bb7 + i32 34, label %bb9 ] bb: ; preds = %entry, %entry, %entry, %entry, %entry, %entry, %entry, %entry, %entry, %entry @@ -40,7 +39,7 @@ br label %bb2 bb2: ; preds = %bb1, %entry - call void %_Z3bari( int 1 ) + call void @_Z3bari( i32 1 ) br label %bb11 bb3: ; preds = %entry @@ -53,7 +52,7 @@ br label %bb6 bb6: ; preds = %bb5, %entry - call void %_Z3bari( int 2 ) + call void @_Z3bari( i32 2 ) br label %bb11 bb7: ; preds = %entry @@ -63,7 +62,7 @@ br label %bb9 bb9: ; preds = %bb8, %entry - call void %_Z3bari( int 3 ) + call void @_Z3bari( i32 3 ) br label %bb11 bb10: ; preds = %entry Added: llvm/trunk/test/CodeGen/X86/x86-64-gv-offset.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/x86-64-gv-offset.ll?rev=46850&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/x86-64-gv-offset.ll (added) +++ llvm/trunk/test/CodeGen/X86/x86-64-gv-offset.ll Thu Feb 7 02:53:49 2008 @@ -0,0 +1,14 @@ +; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin | not grep lea + + %struct.x = type { float, double } + at X = global %struct.x { float 1.000000e+00, double 2.000000e+00 }, align 16 ; <%struct.x*> [#uses=2] + +define i32 @main() nounwind { +entry: + %tmp2 = load float* getelementptr (%struct.x* @X, i32 0, i32 0), align 16 ; [#uses=1] + %tmp4 = load double* getelementptr (%struct.x* @X, i32 0, i32 1), align 8 ; [#uses=1] + tail call void @t( float %tmp2, double %tmp4 ) nounwind + ret i32 0 +} + +declare void @t(float, double) From gohman at apple.com Thu Feb 7 10:18:00 2008 From: gohman at apple.com (Dan Gohman) Date: Thu, 07 Feb 2008 16:18:00 -0000 Subject: [llvm-commits] [llvm] r46853 - /llvm/trunk/lib/CodeGen/MachineInstr.cpp Message-ID: <200802071618.m17GI0fP010171@zion.cs.uiuc.edu> Author: djg Date: Thu Feb 7 10:18:00 2008 New Revision: 46853 URL: http://llvm.org/viewvc/llvm-project?rev=46853&view=rev Log: Don't abort if a MemOperand is missing a SourceValue; just print it as . And make some minor adjustments to the MemOperand dump format. Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=46853&r1=46852&r2=46853&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Thu Feb 7 10:18:00 2008 @@ -631,30 +631,34 @@ } if (getNumMemOperands() > 0) { - OS << ", SV:"; + OS << ", Mem:"; for (unsigned i = 0; i < getNumMemOperands(); i++) { const MemOperand &MRO = getMemOperand(i); const Value *V = MRO.getValue(); - assert(V && "SV missing."); assert((MRO.isLoad() || MRO.isStore()) && "SV has to be a load, store or both."); if (MRO.isVolatile()) OS << "Volatile "; + if (MRO.isLoad()) - OS << "LD "; + OS << "LD"; if (MRO.isStore()) - OS << "ST "; + OS << "ST"; - OS << MRO.getSize(); + OS << "(" << MRO.getSize() << ") ["; - if (!V->getName().empty()) - OS << "[" << V->getName() << " + " << MRO.getOffset() << "]"; + if (!V) + OS << ""; + else if (!V->getName().empty()) + OS << V->getName(); else if (isa(V)) - OS << "[" << *V << " + " << MRO.getOffset() << "]"; + OS << *V; else - OS << "[" << V << " + " << MRO.getOffset() << "]"; + OS << V; + + OS << " + " << MRO.getOffset() << "]"; } } From gohman at apple.com Thu Feb 7 10:28:05 2008 From: gohman at apple.com (Dan Gohman) Date: Thu, 07 Feb 2008 16:28:05 -0000 Subject: [llvm-commits] [llvm] r46854 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <200802071628.m17GS5Je010468@zion.cs.uiuc.edu> Author: djg Date: Thu Feb 7 10:28:05 2008 New Revision: 46854 URL: http://llvm.org/viewvc/llvm-project?rev=46854&view=rev Log: Add SourceValue information for outgoing argument stores on x86. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=46854&r1=46853&r2=46854&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Feb 7 10:28:05 2008 @@ -1290,14 +1290,16 @@ const CCValAssign &VA, SDOperand Chain, SDOperand Arg) { - SDOperand PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()); + unsigned LocMemOffset = VA.getLocMemOffset(); + SDOperand PtrOff = DAG.getIntPtrConstant(LocMemOffset); PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff); SDOperand FlagsOp = Op.getOperand(6+2*VA.getValNo()); unsigned Flags = cast(FlagsOp)->getValue(); if (Flags & ISD::ParamFlags::ByVal) { return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG); } - return DAG.getStore(Chain, Arg, PtrOff, NULL, 0); + return DAG.getStore(Chain, Arg, PtrOff, + &PseudoSourceValue::getStack(), LocMemOffset); } /// ClassifyX86_64SRetCallReturn - Classify how to implement a x86-64 From clattner at apple.com Thu Feb 7 11:41:07 2008 From: clattner at apple.com (Chris Lattner) Date: Thu, 7 Feb 2008 09:41:07 -0800 Subject: [llvm-commits] [llvm] r46854 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp In-Reply-To: <200802071628.m17GS5Je010468@zion.cs.uiuc.edu> References: <200802071628.m17GS5Je010468@zion.cs.uiuc.edu> Message-ID: <93F784F5-CD46-40B5-A904-FCAF7E2C90B7@apple.com> On Feb 7, 2008, at 8:28 AM, Dan Gohman wrote: > if (Flags & ISD::ParamFlags::ByVal) { > return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG); > } > - return DAG.getStore(Chain, Arg, PtrOff, NULL, 0); > + return DAG.getStore(Chain, Arg, PtrOff, > + &PseudoSourceValue::getStack(), LocMemOffset); > } Hey Dan, Why not have getStack() return a Value* instead of Value&? That would eliminate the '&'s and would be more consistent with other APIS, -Chris From clattner at apple.com Thu Feb 7 11:42:25 2008 From: clattner at apple.com (Chris Lattner) Date: Thu, 7 Feb 2008 09:42:25 -0800 Subject: [llvm-commits] Fwd: [llvm-testresults] zeppo-ia64 ia64 nightly tester results References: <200802071320.m17DKlU1005169@zion.cs.uiuc.edu> Message-ID: <203C0C17-C546-4B38-B4EC-E1176D0E0A61@apple.com> Begin forwarded message: > Subject: [llvm-testresults] zeppo-ia64 ia64 nightly tester results > > New Test Failures: > test/CodeGen/X86/fold-mul-lohi.ll [DEJAGNU] > test/CodeGen/X86/stride-nine-with-base-reg.ll [DEJAGNU] > test/CodeGen/X86/stride-reuse.ll [DEJAGNU] Anyone know why these are failing on an ia64 host? -Chris From baldrick at free.fr Thu Feb 7 11:35:30 2008 From: baldrick at free.fr (Duncan Sands) Date: Thu, 7 Feb 2008 18:35:30 +0100 Subject: [llvm-commits] [llvm-gcc-4.2] r46726 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp In-Reply-To: <200802042324.m14NOiBg021071@zion.cs.uiuc.edu> References: <200802042324.m14NOiBg021071@zion.cs.uiuc.edu> Message-ID: <200802071835.30827.baldrick@free.fr> Hi Devang, > Use appropriate alignment while handling packed struct member. the reason I asked for a testcase is that I thought all objects created by the IR we generate (whether locals, globals or on the heap) were supposed to be aligned at least as much as the gcc alignment. If so, the fact that we create a packed struct type (alignment 1) shouldn't make the gcc object alignment info in expr_align wrong, in fact it should be irrelevant. My fear is that your change might only be papering over the problem. > ? ?bool isVolatile = TREE_THIS_VOLATILE(exp); > ? ?const Type *Ty = ConvertType(TREE_TYPE(exp)); > ? ?unsigned Alignment = expr_align(exp) / 8; > + ?if (TREE_CODE(exp) == COMPONENT_REF) > + ? ?if (const StructType *STy = > + ? ? ? ?dyn_cast(ConvertType(TREE_TYPE(TREE_OPERAND(exp, > 0))))) + ? ? ?if (STy->isPacked()) > + ? ? ? ?// Packed struct members use 1 byte alignment > + ? ? ? ?Alignment = 1; > + ? ? > ? ? Best wishes, Duncan. From dpatel at apple.com Thu Feb 7 11:54:23 2008 From: dpatel at apple.com (Devang Patel) Date: Thu, 7 Feb 2008 09:54:23 -0800 Subject: [llvm-commits] [llvm-gcc-4.2] r46726 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp In-Reply-To: <200802071835.30827.baldrick@free.fr> References: <200802042324.m14NOiBg021071@zion.cs.uiuc.edu> <200802071835.30827.baldrick@free.fr> Message-ID: <501FF9A4-3632-4D09-B38B-E0CB6A06028C@apple.com> It is possible that I'm not solving the real problem here. struct { char a; char b; int c:8; int d:20; } S; When this struct is packed and S is aligned at 4 byte, what alignment should be specified on load instruction to load 'd' ? - Devang On Feb 7, 2008, at 9:35 AM, Duncan Sands wrote: > Hi Devang, > >> Use appropriate alignment while handling packed struct member. > > the reason I asked for a testcase is that I thought all objects > created by the IR we generate (whether locals, globals or on the > heap) were supposed to be aligned at least as much as the gcc > alignment. If so, the fact that we create a packed struct type > (alignment 1) shouldn't make the gcc object alignment info in > expr_align wrong, in fact it should be irrelevant. My fear is > that your change might only be papering over the problem. > >> bool isVolatile = TREE_THIS_VOLATILE(exp); >> const Type *Ty = ConvertType(TREE_TYPE(exp)); >> unsigned Alignment = expr_align(exp) / 8; >> + if (TREE_CODE(exp) == COMPONENT_REF) >> + if (const StructType *STy = >> + dyn_cast(ConvertType(TREE_TYPE(TREE_OPERAND(exp, >> 0))))) + if (STy->isPacked()) >> + // Packed struct members use 1 byte alignment >> + Alignment = 1; >> + >> > > Best wishes, > > Duncan. From dalej at apple.com Thu Feb 7 12:32:59 2008 From: dalej at apple.com (Dale Johannesen) Date: Thu, 7 Feb 2008 10:32:59 -0800 Subject: [llvm-commits] [llvm-gcc-4.2] r46726 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp In-Reply-To: <501FF9A4-3632-4D09-B38B-E0CB6A06028C@apple.com> References: <200802042324.m14NOiBg021071@zion.cs.uiuc.edu> <200802071835.30827.baldrick@free.fr> <501FF9A4-3632-4D09-B38B-E0CB6A06028C@apple.com> Message-ID: On Feb 7, 2008, at 9:54 AM, Devang Patel wrote: > It is possible that I'm not solving the real problem here. > > struct { > char a; > char b; > int c:8; > int d:20; > } S; > > When this struct is packed and S is aligned at 4 byte, what alignment > should be specified on load instruction to load 'd' ? The struct is only 6 bytes long in this case (try it with gcc), so representing d with a 32-bit load is probably not a good idea; there are machines where such misaligned loads are valid (e.g. x86) and a 32- bit load will read off the end of the structure. In general I prefer the IR to be target-independent where possible, but I don't see a good alternative to having the FE break up the load of d into 3 pieces here (or perhaps char + short). Having the IR include a load off the end of the object, that wasn't there in the source, and requiring the BE to figure this out seems very wrong. So to answer your question, there needs to be more than one load. However, if we modify the packed struct thus (it's now 7 bytes) > struct { > char a; > char b; > int c:8; > int d:32; > } S; referring to d with misaligned 32-bit loads and stores is sensible. That's valid code on x86, and representing it as byte operations and expecting the BE to stick them back together is a lot of trouble for no benefit. Of course, on many other targets, that load must be broken into pieces. That could be done in either end, but since we've got to break up 20-bit fields in the FE anyway, I guess we might as well do so for 32-bit fields when the target requires that. I could probably be convinced to do this one in the BE though. > Devang > On Feb 7, 2008, at 9:35 AM, Duncan Sands wrote: > >> Hi Devang, >> >>> Use appropriate alignment while handling packed struct member. >> >> the reason I asked for a testcase is that I thought all objects >> created by the IR we generate (whether locals, globals or on the >> heap) were supposed to be aligned at least as much as the gcc >> alignment. If so, the fact that we create a packed struct type >> (alignment 1) shouldn't make the gcc object alignment info in >> expr_align wrong, in fact it should be irrelevant. My fear is >> that your change might only be papering over the problem. >> >>> bool isVolatile = TREE_THIS_VOLATILE(exp); >>> const Type *Ty = ConvertType(TREE_TYPE(exp)); >>> unsigned Alignment = expr_align(exp) / 8; >>> + if (TREE_CODE(exp) == COMPONENT_REF) >>> + if (const StructType *STy = >>> + >>> dyn_cast(ConvertType(TREE_TYPE(TREE_OPERAND(exp, >>> 0))))) + if (STy->isPacked()) >>> + // Packed struct members use 1 byte alignment >>> + Alignment = 1; >>> + >>> >> >> Best wishes, >> >> Duncan. > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From gohman at apple.com Thu Feb 7 12:41:25 2008 From: gohman at apple.com (Dan Gohman) Date: Thu, 07 Feb 2008 18:41:25 -0000 Subject: [llvm-commits] [llvm] r46857 - in /llvm/trunk: include/llvm/CodeGen/PseudoSourceValue.h lib/CodeGen/PseudoSourceValue.cpp lib/CodeGen/SelectionDAG/LegalizeDAG.cpp lib/CodeGen/SelectionDAG/SelectionDAG.cpp lib/Target/PowerPC/PPCISelLowering.cpp lib/Target/X86/X86ISelLowering.cpp Message-ID: <200802071841.m17IfQNv014555@zion.cs.uiuc.edu> Author: djg Date: Thu Feb 7 12:41:25 2008 New Revision: 46857 URL: http://llvm.org/viewvc/llvm-project?rev=46857&view=rev Log: Follow Chris' suggestion; change the PseudoSourceValue accessors to return pointers instead of references, since this is always what is needed. Modified: llvm/trunk/include/llvm/CodeGen/PseudoSourceValue.h llvm/trunk/lib/CodeGen/PseudoSourceValue.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/include/llvm/CodeGen/PseudoSourceValue.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/PseudoSourceValue.h?rev=46857&r1=46856&r2=46857&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/PseudoSourceValue.h (original) +++ llvm/trunk/include/llvm/CodeGen/PseudoSourceValue.h Thu Feb 7 12:41:25 2008 @@ -37,21 +37,21 @@ /// A pseudo source value referencing to the stack frame of a function, /// e.g., a spill slot. - static const PseudoSourceValue &getFixedStack(); + static const PseudoSourceValue *getFixedStack(); /// A source value referencing the area below the stack frame of a function, /// e.g., the argument space. - static const PseudoSourceValue &getStack(); + static const PseudoSourceValue *getStack(); /// A source value referencing the global offset table (or something the /// like). - static const PseudoSourceValue &getGOT(); + static const PseudoSourceValue *getGOT(); /// A SV referencing the constant pool - static const PseudoSourceValue &getConstantPool(); + static const PseudoSourceValue *getConstantPool(); /// A SV referencing the jump table - static const PseudoSourceValue &getJumpTable(); + static const PseudoSourceValue *getJumpTable(); }; } // End llvm namespace Modified: llvm/trunk/lib/CodeGen/PseudoSourceValue.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PseudoSourceValue.cpp?rev=46857&r1=46856&r2=46857&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PseudoSourceValue.cpp (original) +++ llvm/trunk/lib/CodeGen/PseudoSourceValue.cpp Thu Feb 7 12:41:25 2008 @@ -18,11 +18,11 @@ namespace llvm { static ManagedStatic PSVs; - const PseudoSourceValue &PseudoSourceValue::getFixedStack() { return (*PSVs)[0]; } - const PseudoSourceValue &PseudoSourceValue::getStack() { return (*PSVs)[1]; } - const PseudoSourceValue &PseudoSourceValue::getGOT() { return (*PSVs)[2]; } - const PseudoSourceValue &PseudoSourceValue::getConstantPool() { return (*PSVs)[3]; } - const PseudoSourceValue &PseudoSourceValue::getJumpTable() { return (*PSVs)[4]; } + const PseudoSourceValue *PseudoSourceValue::getFixedStack() { return &(*PSVs)[0]; } + const PseudoSourceValue *PseudoSourceValue::getStack() { return &(*PSVs)[1]; } + const PseudoSourceValue *PseudoSourceValue::getGOT() { return &(*PSVs)[2]; } + const PseudoSourceValue *PseudoSourceValue::getConstantPool() { return &(*PSVs)[3]; } + const PseudoSourceValue *PseudoSourceValue::getJumpTable() { return &(*PSVs)[4]; } static const char *PSVNames[] = { "FixedStack", Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=46857&r1=46856&r2=46857&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Feb 7 12:41:25 2008 @@ -510,11 +510,11 @@ SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); if (Extend) { return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), - CPIdx, &PseudoSourceValue::getConstantPool(), + CPIdx, PseudoSourceValue::getConstantPool(), 0, MVT::f32); } else { return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, - &PseudoSourceValue::getConstantPool(), 0); + PseudoSourceValue::getConstantPool(), 0); } } @@ -1327,7 +1327,7 @@ // Store the vector. SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, - &PseudoSourceValue::getFixedStack(), + PseudoSourceValue::getFixedStack(), SPFI); // Truncate or zero extend offset to target pointer type. @@ -1339,10 +1339,10 @@ SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr); // Store the scalar value. Ch = DAG.getStore(Ch, Tmp2, StackPtr2, - &PseudoSourceValue::getFixedStack(), SPFI); + PseudoSourceValue::getFixedStack(), SPFI); // Load the updated vector. Result = DAG.getLoad(VT, Ch, StackPtr, - &PseudoSourceValue::getFixedStack(), SPFI); + PseudoSourceValue::getFixedStack(), SPFI); break; } } @@ -1692,9 +1692,9 @@ switch (EntrySize) { default: assert(0 && "Size of jump table not supported yet."); break; case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, - &PseudoSourceValue::getJumpTable(), 0); break; + PseudoSourceValue::getJumpTable(), 0); break; case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, - &PseudoSourceValue::getJumpTable(), 0); break; + PseudoSourceValue::getJumpTable(), 0); break; } Addr = LD; @@ -4772,12 +4772,12 @@ SDOperand Store; if (SrcSize > SlotSize) Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr, - &PseudoSourceValue::getFixedStack(), + PseudoSourceValue::getFixedStack(), SPFI, SlotVT); else { assert(SrcSize == SlotSize && "Invalid store"); Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, - &PseudoSourceValue::getFixedStack(), + PseudoSourceValue::getFixedStack(), SPFI, SlotVT); } @@ -4799,9 +4799,9 @@ int SPFI = StackPtrFI->getIndex(); SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr, - &PseudoSourceValue::getFixedStack(), SPFI); + PseudoSourceValue::getFixedStack(), SPFI); return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, - &PseudoSourceValue::getFixedStack(), SPFI); + PseudoSourceValue::getFixedStack(), SPFI); } @@ -4866,7 +4866,7 @@ Constant *CP = ConstantVector::get(CV); SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, - &PseudoSourceValue::getConstantPool(), 0); + PseudoSourceValue::getConstantPool(), 0); } if (SplatValue.Val) { // Splat of one value? @@ -5209,12 +5209,12 @@ SDOperand FudgeInReg; if (DestTy == MVT::f32) FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, - &PseudoSourceValue::getConstantPool(), 0); + PseudoSourceValue::getConstantPool(), 0); else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32)) // FIXME: Avoid the extend by construction the right constantpool? FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(), CPIdx, - &PseudoSourceValue::getConstantPool(), 0, + PseudoSourceValue::getConstantPool(), 0, MVT::f32); else assert(0 && "Unexpected conversion"); @@ -5358,12 +5358,12 @@ SDOperand FudgeInReg; if (DestVT == MVT::f32) FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, - &PseudoSourceValue::getConstantPool(), 0); + PseudoSourceValue::getConstantPool(), 0); else { FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT, DAG.getEntryNode(), CPIdx, - &PseudoSourceValue::getConstantPool(), 0, + PseudoSourceValue::getConstantPool(), 0, MVT::f32)); } @@ -6778,10 +6778,10 @@ SDOperand St = DAG.getStore(DAG.getEntryNode(), InOp, Ptr, - &PseudoSourceValue::getFixedStack(), + PseudoSourceValue::getFixedStack(), FI->getIndex()); InOp = DAG.getLoad(Op.getValueType(), St, Ptr, - &PseudoSourceValue::getFixedStack(), + PseudoSourceValue::getFixedStack(), FI->getIndex()); } // Split the vector and convert each of the pieces now. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=46857&r1=46856&r2=46857&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Feb 7 12:41:25 2008 @@ -3548,7 +3548,7 @@ const FrameIndexSDNode *FI = dyn_cast(getBasePtr().Val); if (!getSrcValue() && FI) - return MemOperand(&PseudoSourceValue::getFixedStack(), Flags, + return MemOperand(PseudoSourceValue::getFixedStack(), Flags, FI->getIndex(), Size, Alignment); else return MemOperand(getSrcValue(), Flags, Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=46857&r1=46856&r2=46857&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Thu Feb 7 12:41:25 2008 @@ -2203,7 +2203,7 @@ Op.getOperand(0)); // STD the extended value into the stack slot. - MemOperand MO(&PseudoSourceValue::getFixedStack(), + MemOperand MO(PseudoSourceValue::getFixedStack(), MemOperand::MOStore, FrameIdx, 8, 8); SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other, DAG.getEntryNode(), Ext64, FIdx, Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=46857&r1=46856&r2=46857&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Feb 7 12:41:25 2008 @@ -1091,7 +1091,7 @@ if (isByVal) return FIN; return DAG.getLoad(VA.getValVT(), Root, FIN, - &PseudoSourceValue::getFixedStack(), FI); + PseudoSourceValue::getFixedStack(), FI); } SDOperand @@ -1221,7 +1221,7 @@ SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i64); SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, - &PseudoSourceValue::getFixedStack(), + PseudoSourceValue::getFixedStack(), RegSaveFrameIndex); MemOps.push_back(Store); FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, @@ -1237,7 +1237,7 @@ SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32); SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, - &PseudoSourceValue::getFixedStack(), + PseudoSourceValue::getFixedStack(), RegSaveFrameIndex); MemOps.push_back(Store); FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, @@ -1299,7 +1299,7 @@ return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG); } return DAG.getStore(Chain, Arg, PtrOff, - &PseudoSourceValue::getStack(), LocMemOffset); + PseudoSourceValue::getStack(), LocMemOffset); } /// ClassifyX86_64SRetCallReturn - Classify how to implement a x86-64 @@ -1571,7 +1571,7 @@ // Store relative to framepointer. MemOpChains2.push_back( DAG.getStore(Chain, Source, FIN, - &PseudoSourceValue::getFixedStack(), FI)); + PseudoSourceValue::getFixedStack(), FI)); } } } @@ -3801,7 +3801,7 @@ // The same applies for external symbols during PIC codegen if (Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false)) Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result, - &PseudoSourceValue::getGOT(), 0); + PseudoSourceValue::getGOT(), 0); return Result; } @@ -3860,7 +3860,7 @@ if (GA->getGlobal()->isDeclaration()) // initial exec TLS model Offset = DAG.getLoad(PtrVT, DAG.getEntryNode(), Offset, - &PseudoSourceValue::getGOT(), 0); + PseudoSourceValue::getGOT(), 0); // The address of the thread local variable is the add of the thread // pointer with the offset of the variable. @@ -3993,7 +3993,7 @@ SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0), StackSlot, - &PseudoSourceValue::getFixedStack(), + PseudoSourceValue::getFixedStack(), SSFI); // These are really Legal; caller falls through into that case. @@ -4036,7 +4036,7 @@ Ops.push_back(InFlag); Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size()); Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot, - &PseudoSourceValue::getFixedStack(), SSFI); + PseudoSourceValue::getFixedStack(), SSFI); } return Result; @@ -4075,7 +4075,7 @@ if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) { assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!"); Chain = DAG.getStore(Chain, Value, StackSlot, - &PseudoSourceValue::getFixedStack(), SSFI); + PseudoSourceValue::getFixedStack(), SSFI); SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); SDOperand Ops[] = { Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType()) @@ -4135,7 +4135,7 @@ Constant *C = ConstantVector::get(CV); SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, - &PseudoSourceValue::getConstantPool(), 0, + PseudoSourceValue::getConstantPool(), 0, false, 16); return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask); } @@ -4164,7 +4164,7 @@ Constant *C = ConstantVector::get(CV); SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, - &PseudoSourceValue::getConstantPool(), 0, + PseudoSourceValue::getConstantPool(), 0, false, 16); if (MVT::isVector(VT)) { return DAG.getNode(ISD::BIT_CONVERT, VT, @@ -4213,7 +4213,7 @@ Constant *C = ConstantVector::get(CV); SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); SDOperand Mask1 = DAG.getLoad(SrcVT, DAG.getEntryNode(), CPIdx, - &PseudoSourceValue::getConstantPool(), 0, + PseudoSourceValue::getConstantPool(), 0, false, 16); SDOperand SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1); @@ -4242,7 +4242,7 @@ C = ConstantVector::get(CV); CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); SDOperand Mask2 = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, - &PseudoSourceValue::getConstantPool(), 0, + PseudoSourceValue::getConstantPool(), 0, false, 16); SDOperand Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2); From dpatel at apple.com Thu Feb 7 13:20:54 2008 From: dpatel at apple.com (Devang Patel) Date: Thu, 07 Feb 2008 19:20:54 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r46858 - in /llvm-gcc-4.2/trunk/gcc: config/darwin.h gcc.c Message-ID: <200802071920.m17JKtfZ015932@zion.cs.uiuc.edu> Author: dpatel Date: Thu Feb 7 13:20:51 2008 New Revision: 46858 URL: http://llvm.org/viewvc/llvm-project?rev=46858&view=rev Log: Do not supply --emit-llvm to darwin linker. Modified: llvm-gcc-4.2/trunk/gcc/config/darwin.h llvm-gcc-4.2/trunk/gcc/gcc.c Modified: llvm-gcc-4.2/trunk/gcc/config/darwin.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/darwin.h?rev=46858&r1=46857&r2=46858&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/darwin.h (original) +++ llvm-gcc-4.2/trunk/gcc/config/darwin.h Thu Feb 7 13:20:51 2008 @@ -134,6 +134,7 @@ { "-dylib_file", "-Zdylib_file" }, \ { "-dynamic", "-Zdynamic" }, \ { "-dynamiclib", "-Zdynamiclib" }, \ + { "-emit-llvm", "-Zemit-llvm" }, \ { "-exported_symbols_list", "-Zexported_symbols_list" }, \ { "-gfull", "-g -fno-eliminate-unused-debug-symbols" }, \ { "-gused", "-g -feliminate-unused-debug-symbols" }, \ Modified: llvm-gcc-4.2/trunk/gcc/gcc.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/gcc.c?rev=46858&r1=46857&r2=46858&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/gcc.c (original) +++ llvm-gcc-4.2/trunk/gcc/gcc.c Thu Feb 7 13:20:51 2008 @@ -825,12 +825,12 @@ /* LLVM LOCAL begin */ static const char *llvm_options = #ifdef ENABLE_LLVM -"%{O4|emit-llvm:%{S:-emit-llvm} \ +"%{O4|Zemit-llvm:%{S:-emit-llvm} \ %{!S:-emit-llvm-bc \ %{c: %W{o*} %{!o*:-o %b%w.o}} \ %{!c:-o %d%w%u%O}}}" #else - "%{emit-llvm:%e--emit-llvm is not supported in this configuration.}" + "%{Zemit-llvm:%e--emit-llvm is not supported in this configuration.}" #endif ; /* LLVM LOCAL end */ @@ -860,10 +860,10 @@ static const char *invoke_as = #ifdef AS_NEEDS_DASH_FOR_PIPED_INPUT /* LLVM LOCAL */ -"%{!O4:%{!emit-llvm:%{!S:-o %|.s |\n as %(asm_options) %|.s %A }}}"; +"%{!O4:%{!Zemit-llvm:%{!S:-o %|.s |\n as %(asm_options) %|.s %A }}}"; #else /* LLVM LOCAL */ -"%{!O4:%{!emit-llvm:%{!S:-o %|.s |\n as %(asm_options) %m.s %A }}}"; +"%{!O4:%{!Zemit-llvm:%{!S:-o %|.s |\n as %(asm_options) %m.s %A }}}"; #endif /* Some compilers have limits on line lengths, and the multilib_select From dpatel at apple.com Thu Feb 7 13:31:11 2008 From: dpatel at apple.com (Devang Patel) Date: Thu, 07 Feb 2008 19:31:11 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r46860 - /llvm-gcc-4.2/trunk/gcc/gcc.c Message-ID: <200802071931.m17JVBVm016313@zion.cs.uiuc.edu> Author: dpatel Date: Thu Feb 7 13:31:10 2008 New Revision: 46860 URL: http://llvm.org/viewvc/llvm-project?rev=46860&view=rev Log: Appropriate translate --emit-llvm for non-darwin target also. Modified: llvm-gcc-4.2/trunk/gcc/gcc.c Modified: llvm-gcc-4.2/trunk/gcc/gcc.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/gcc.c?rev=46860&r1=46859&r2=46860&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/gcc.c (original) +++ llvm-gcc-4.2/trunk/gcc/gcc.c Thu Feb 7 13:31:10 2008 @@ -1145,8 +1145,10 @@ {"--dependencies", "-M", 0}, {"--dump", "-d", "a"}, {"--dumpbase", "-dumpbase", "a"}, - /* LLVM LOCAL */ - {"--emit-llvm", "-emit-llvm", 0 }, + /* LLVM LOCAL begin */ + {"--emit-llvm", "-Zemit-llvm", 0 }, + {"-emit-llvm", "-Zemit-llvm", 0 }, + /* LLVM LOCAL end */ {"--encoding", "-fencoding=", "aj"}, {"--entry", "-e", 0}, {"--extra-warnings", "-W", 0}, From dpatel at apple.com Thu Feb 7 13:32:39 2008 From: dpatel at apple.com (Devang Patel) Date: Thu, 7 Feb 2008 11:32:39 -0800 Subject: [llvm-commits] [llvm-gcc-4.2] r46860 - /llvm-gcc-4.2/trunk/gcc/gcc.c In-Reply-To: <200802071931.m17JVBVm016313@zion.cs.uiuc.edu> References: <200802071931.m17JVBVm016313@zion.cs.uiuc.edu> Message-ID: Would it be possible for someone to verify that --emit-llvm works, after this patch, on non-darwin platforms ? Thanks, - Devang On Feb 7, 2008, at 11:31 AM, Devang Patel wrote: > Author: dpatel > Date: Thu Feb 7 13:31:10 2008 > New Revision: 46860 > > URL: http://llvm.org/viewvc/llvm-project?rev=46860&view=rev > Log: > Appropriate translate --emit-llvm for non-darwin target also. > > Modified: > llvm-gcc-4.2/trunk/gcc/gcc.c > > Modified: llvm-gcc-4.2/trunk/gcc/gcc.c > URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/gcc.c?rev=46860&r1=46859&r2=46860&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm-gcc-4.2/trunk/gcc/gcc.c (original) > +++ llvm-gcc-4.2/trunk/gcc/gcc.c Thu Feb 7 13:31:10 2008 > @@ -1145,8 +1145,10 @@ > {"--dependencies", "-M", 0}, > {"--dump", "-d", "a"}, > {"--dumpbase", "-dumpbase", "a"}, > - /* LLVM LOCAL */ > - {"--emit-llvm", "-emit-llvm", 0 }, > + /* LLVM LOCAL begin */ > + {"--emit-llvm", "-Zemit-llvm", 0 }, > + {"-emit-llvm", "-Zemit-llvm", 0 }, > + /* LLVM LOCAL end */ > {"--encoding", "-fencoding=", "aj"}, > {"--entry", "-e", 0}, > {"--extra-warnings", "-W", 0}, > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From evan.cheng at apple.com Thu Feb 7 13:46:56 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 07 Feb 2008 19:46:56 -0000 Subject: [llvm-commits] [llvm] r46861 - /llvm/trunk/lib/CodeGen/RegAllocLocal.cpp Message-ID: <200802071946.m17JkunG016863@zion.cs.uiuc.edu> Author: evancheng Date: Thu Feb 7 13:46:55 2008 New Revision: 46861 URL: http://llvm.org/viewvc/llvm-project?rev=46861&view=rev Log: Remove remnant of load folding in local register allocator. Patch by Holger Schurig. Modified: llvm/trunk/lib/CodeGen/RegAllocLocal.cpp Modified: llvm/trunk/lib/CodeGen/RegAllocLocal.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocLocal.cpp?rev=46861&r1=46860&r2=46861&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocLocal.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocLocal.cpp Thu Feb 7 13:46:55 2008 @@ -35,7 +35,6 @@ STATISTIC(NumStores, "Number of stores added"); STATISTIC(NumLoads , "Number of loads added"); -STATISTIC(NumFolded, "Number of loads/stores folded into instructions"); namespace { static RegisterRegAlloc @@ -500,12 +499,7 @@ if (PhysReg) { // Register is available, allocate it! assignVirtToPhysReg(VirtReg, PhysReg); } else { // No registers available. - // If we can fold this spill into this instruction, do so now. - SmallVector Ops; - Ops.push_back(OpNum); - - // It looks like we can't fold this virtual register load into this - // instruction. Force some poor hapless value out of the register file to + // Force some poor hapless value out of the register file to // make room for the new register, and reload it. PhysReg = getReg(MBB, MI, VirtReg); } From baldrick at free.fr Thu Feb 7 14:11:37 2008 From: baldrick at free.fr (Duncan Sands) Date: Thu, 7 Feb 2008 21:11:37 +0100 Subject: [llvm-commits] [llvm-gcc-4.2] r46726 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp In-Reply-To: <501FF9A4-3632-4D09-B38B-E0CB6A06028C@apple.com> References: <200802042324.m14NOiBg021071@zion.cs.uiuc.edu> <200802071835.30827.baldrick@free.fr> <501FF9A4-3632-4D09-B38B-E0CB6A06028C@apple.com> Message-ID: <200802072111.38003.baldrick@free.fr> Hi Devang, > It is possible that I'm not solving the real problem here. > > struct { > ????????char a; > ????????char b; > ????????int c:8; > ????????int d:20; > } S; > > When this struct is packed and S is aligned at 4 byte, what alignment ? > should be specified on load instruction to load 'd' ? since the alignment depends the address you choose to load it from, and several strategies are possible, relying on gcc's expr_align seems like a bad move. I think the LValue type should contain alignment info. That way the bitfield lvalue code, which knows exactly how it chose to address the bitfield, can set an appropriate alignment. This also concentrates all nastiness in one spot. [By the way, expr_align contains the following comment: /* LLVM local begin */ /* return correctly the alignment of packed structs */ case COMPONENT_REF: /* LLVM local end */ ] Best wishes, Duncan. From isanbard at gmail.com Thu Feb 7 16:31:11 2008 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 07 Feb 2008 22:31:11 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r46862 - /llvm-gcc-4.2/trunk/gcc/config/darwin.c Message-ID: <200802072231.m17MVCLJ021868@zion.cs.uiuc.edu> Author: void Date: Thu Feb 7 16:30:56 2008 New Revision: 46862 URL: http://llvm.org/viewvc/llvm-project?rev=46862&view=rev Log: Mark variable as "unused" if enable_llvm is defined. Modified: llvm-gcc-4.2/trunk/gcc/config/darwin.c Modified: llvm-gcc-4.2/trunk/gcc/config/darwin.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/darwin.c?rev=46862&r1=46861&r2=46862&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/darwin.c (original) +++ llvm-gcc-4.2/trunk/gcc/config/darwin.c Thu Feb 7 16:30:56 2008 @@ -1988,8 +1988,15 @@ extern". There is no MACH-O equivalent of ELF's VISIBILITY_INTERNAL or VISIBILITY_PROTECTED. */ +/* LLVM LOCAL begin */ +#ifdef ENABLE_LLVM +void +darwin_assemble_visibility (tree decl ATTRIBUTE_UNUSED, int vis) +#else void darwin_assemble_visibility (tree decl, int vis) +#endif +/* LLVM LOCAL end */ { if (vis == VISIBILITY_DEFAULT) ; From dpatel at apple.com Thu Feb 7 16:32:50 2008 From: dpatel at apple.com (Devang Patel) Date: Thu, 07 Feb 2008 22:32:50 -0000 Subject: [llvm-commits] [llvm] r46863 - /llvm/trunk/tools/lto/lto.cpp Message-ID: <200802072232.m17MWpdG021930@zion.cs.uiuc.edu> Author: dpatel Date: Thu Feb 7 16:32:50 2008 New Revision: 46863 URL: http://llvm.org/viewvc/llvm-project?rev=46863&view=rev Log: Begin setting features for target based on target triple string. Modified: llvm/trunk/tools/lto/lto.cpp Modified: llvm/trunk/tools/lto/lto.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/lto.cpp?rev=46863&r1=46862&r2=46863&view=diff ============================================================================== --- llvm/trunk/tools/lto/lto.cpp (original) +++ llvm/trunk/tools/lto/lto.cpp Thu Feb 7 16:32:50 2008 @@ -247,8 +247,19 @@ return; // Create target - std::string Features; - Target = March->CtorFn(*M, Features); + SubtargetFeatures Features; + std::string FeatureStr; + std::string TargetTriple = M->getTargetTriple(); + + if (strncmp(TargetTriple.c_str(), "powerpc-apple-", 14) == 0) + Features.AddFeature("altivec", true); + else if (strncmp(TargetTriple.c_str(), "powerpc64-apple-", 16) == 0) { + Features.AddFeature("64bit", true); + Features.AddFeature("altivec", true); + } + + FeatureStr = Features.getString(); + Target = March->CtorFn(*M, FeatureStr); } /// Optimize module M using various IPO passes. Use exportList to From echristo at apple.com Thu Feb 7 16:34:05 2008 From: echristo at apple.com (Eric Christopher) Date: Thu, 7 Feb 2008 14:34:05 -0800 Subject: [llvm-commits] [llvm-gcc-4.2] r46862 - /llvm-gcc-4.2/trunk/gcc/config/darwin.c In-Reply-To: <200802072231.m17MVCLJ021868@zion.cs.uiuc.edu> References: <200802072231.m17MVCLJ021868@zion.cs.uiuc.edu> Message-ID: <313290A0-C990-4897-A41D-9DD72691DDE8@apple.com> On Feb 7, 2008, at 2:31 PM, Bill Wendling wrote: > +/* LLVM LOCAL begin */ > +#ifdef ENABLE_LLVM > +void > +darwin_assemble_visibility (tree decl ATTRIBUTE_UNUSED, int vis) > +#else > void > darwin_assemble_visibility (tree decl, int vis) > +#endif FWIW you can just mark it if there are occasions where it's not used and gcc won't complain. i.e. /* LLVM LOCAL */ darwin_assemble_visibility (tree decl ATTRIBUTE_UNUSED, int vis) should be all you need. -eric From dpatel at apple.com Thu Feb 7 17:24:59 2008 From: dpatel at apple.com (Devang Patel) Date: Thu, 07 Feb 2008 23:24:59 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r46865 - in /llvm-gcc-4.2/trunk/gcc: llvm-backend.cpp llvm-linker-hack.cpp Message-ID: <200802072324.m17NOxFV023458@zion.cs.uiuc.edu> Author: dpatel Date: Thu Feb 7 17:24:58 2008 New Revision: 46865 URL: http://llvm.org/viewvc/llvm-project?rev=46865&view=rev Log: Add loop index split pass in optimization queue. Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp llvm-gcc-4.2/trunk/gcc/llvm-linker-hack.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=46865&r1=46864&r2=46865&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Thu Feb 7 17:24:58 2008 @@ -369,6 +369,7 @@ PM->add(createLoopRotatePass()); // Rotate Loop PM->add(createLICMPass()); // Hoist loop invariants PM->add(createLoopUnswitchPass(optimize_size ? true : false)); + PM->add(createLoopIndexSplitPass()); // Split loop index PM->add(createInstructionCombiningPass()); // Clean up after LICM/reassoc PM->add(createIndVarSimplifyPass()); // Canonicalize indvars if (flag_unroll_loops) Modified: llvm-gcc-4.2/trunk/gcc/llvm-linker-hack.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-linker-hack.cpp?rev=46865&r1=46864&r2=46865&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-linker-hack.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-linker-hack.cpp Thu Feb 7 17:24:58 2008 @@ -64,6 +64,7 @@ llvm::createLoopUnrollPass(); llvm::createReassociatePass(); llvm::createLoopUnswitchPass(); + llvm::createLoopIndexSplitPass(); llvm::createAggressiveDCEPass(); llvm::createConstantMergePass(); llvm::createIndVarSimplifyPass(); From evan.cheng at apple.com Thu Feb 7 18:12:59 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 08 Feb 2008 00:12:59 -0000 Subject: [llvm-commits] [llvm] r46866 - in /llvm/trunk: lib/Target/X86/X86InstrInfo.cpp test/CodeGen/X86/2008-02-06-LoadFoldingBug.ll Message-ID: <200802080013.m180D0bX024881@zion.cs.uiuc.edu> Author: evancheng Date: Thu Feb 7 18:12:56 2008 New Revision: 46866 URL: http://llvm.org/viewvc/llvm-project?rev=46866&view=rev Log: Added missing entries in X86 load / store folding tables. Added: llvm/trunk/test/CodeGen/X86/2008-02-06-LoadFoldingBug.ll Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=46866&r1=46865&r2=46866&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Thu Feb 7 18:12:56 2008 @@ -495,6 +495,14 @@ { X86::DIVPSrr, X86::DIVPSrm }, { X86::DIVSDrr, X86::DIVSDrm }, { X86::DIVSSrr, X86::DIVSSrm }, + { X86::FsANDNPDrr, X86::FsANDNPDrm }, + { X86::FsANDNPSrr, X86::FsANDNPSrm }, + { X86::FsANDPDrr, X86::FsANDPDrm }, + { X86::FsANDPSrr, X86::FsANDPSrm }, + { X86::FsORPDrr, X86::FsORPDrm }, + { X86::FsORPSrr, X86::FsORPSrm }, + { X86::FsXORPDrr, X86::FsXORPDrm }, + { X86::FsXORPSrr, X86::FsXORPSrm }, { X86::HADDPDrr, X86::HADDPDrm }, { X86::HADDPSrr, X86::HADDPSrm }, { X86::HSUBPDrr, X86::HSUBPDrm }, Added: llvm/trunk/test/CodeGen/X86/2008-02-06-LoadFoldingBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-02-06-LoadFoldingBug.ll?rev=46866&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2008-02-06-LoadFoldingBug.ll (added) +++ llvm/trunk/test/CodeGen/X86/2008-02-06-LoadFoldingBug.ll Thu Feb 7 18:12:56 2008 @@ -0,0 +1,20 @@ +; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep xor | grep CPI + +define void @casin({ double, double }* sret %agg.result, double %z.0, double %z.1) nounwind { +entry: + %memtmp = alloca { double, double }, align 8 ; <{ double, double }*> [#uses=3] + %tmp4 = sub double -0.000000e+00, %z.1 ; [#uses=1] + call void @casinh( { double, double }* sret %memtmp, double %tmp4, double %z.0 ) nounwind + %tmp19 = getelementptr { double, double }* %memtmp, i32 0, i32 0 ; [#uses=1] + %tmp20 = load double* %tmp19, align 8 ; [#uses=1] + %tmp22 = getelementptr { double, double }* %memtmp, i32 0, i32 1 ; [#uses=1] + %tmp23 = load double* %tmp22, align 8 ; [#uses=1] + %tmp32 = sub double -0.000000e+00, %tmp20 ; [#uses=1] + %tmp37 = getelementptr { double, double }* %agg.result, i32 0, i32 0 ; [#uses=1] + store double %tmp23, double* %tmp37, align 8 + %tmp40 = getelementptr { double, double }* %agg.result, i32 0, i32 1 ; [#uses=1] + store double %tmp32, double* %tmp40, align 8 + ret void +} + +declare void @casinh({ double, double }* sret , double, double) nounwind From isanbard at gmail.com Thu Feb 7 19:07:37 2008 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 08 Feb 2008 01:07:37 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r46870 - /llvm-gcc-4.2/trunk/gcc/config/darwin.c Message-ID: <200802080107.m1817bno026345@zion.cs.uiuc.edu> Author: void Date: Thu Feb 7 19:07:37 2008 New Revision: 46870 URL: http://llvm.org/viewvc/llvm-project?rev=46870&view=rev Log: No need to conditionalize the ATTRIBUTE_UNUSED as gcc won't complain about it if it is used. Modified: llvm-gcc-4.2/trunk/gcc/config/darwin.c Modified: llvm-gcc-4.2/trunk/gcc/config/darwin.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/darwin.c?rev=46870&r1=46869&r2=46870&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/darwin.c (original) +++ llvm-gcc-4.2/trunk/gcc/config/darwin.c Thu Feb 7 19:07:37 2008 @@ -1988,15 +1988,9 @@ extern". There is no MACH-O equivalent of ELF's VISIBILITY_INTERNAL or VISIBILITY_PROTECTED. */ -/* LLVM LOCAL begin */ -#ifdef ENABLE_LLVM void +/* LLVM LOCAL begin */ darwin_assemble_visibility (tree decl ATTRIBUTE_UNUSED, int vis) -#else -void -darwin_assemble_visibility (tree decl, int vis) -#endif -/* LLVM LOCAL end */ { if (vis == VISIBILITY_DEFAULT) ; From isanbard at gmail.com Thu Feb 7 19:07:54 2008 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 7 Feb 2008 17:07:54 -0800 Subject: [llvm-commits] [llvm-gcc-4.2] r46862 - /llvm-gcc-4.2/trunk/gcc/config/darwin.c In-Reply-To: <313290A0-C990-4897-A41D-9DD72691DDE8@apple.com> References: <200802072231.m17MVCLJ021868@zion.cs.uiuc.edu> <313290A0-C990-4897-A41D-9DD72691DDE8@apple.com> Message-ID: <16e5fdf90802071707k47a58c7y6a881c28a46ebe16@mail.gmail.com> On Feb 7, 2008 2:34 PM, Eric Christopher wrote: > > On Feb 7, 2008, at 2:31 PM, Bill Wendling wrote: > > > +/* LLVM LOCAL begin */ > > +#ifdef ENABLE_LLVM > > +void > > +darwin_assemble_visibility (tree decl ATTRIBUTE_UNUSED, int vis) > > +#else > > void > > darwin_assemble_visibility (tree decl, int vis) > > +#endif > > FWIW you can just mark it if there are occasions where it's not used > and gcc won't complain. > I was wondering about that. Done. Thanks! -bw From scottm at aero.org Thu Feb 7 19:11:33 2008 From: scottm at aero.org (Scott Michel) Date: Fri, 08 Feb 2008 01:11:33 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r46871 - /llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp Message-ID: <200802080111.m181BXAa026475@zion.cs.uiuc.edu> Author: pingbak Date: Thu Feb 7 19:11:33 2008 New Revision: 46871 URL: http://llvm.org/viewvc/llvm-project?rev=46871&view=rev Log: Move llvm_x86_should_pass_aggregate_in_memory so that it is declared before it is used. Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp?rev=46871&r1=46870&r2=46871&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp Thu Feb 7 19:11:33 2008 @@ -690,6 +690,48 @@ } /* Target hook for llvm-abi.h. It returns true if an aggregate of the + specified type should be passed in a number of registers of mixed types. + It also returns a vector of types that correspond to the registers used + for parameter passing. This is only called for x86-32. */ +bool +llvm_x86_32_should_pass_aggregate_in_mixed_regs(tree TreeType, const Type *Ty, + std::vector &Elts){ + // If this is a small fixed size type, investigate it. + HOST_WIDE_INT SrcSize = int_size_in_bytes(TreeType); + if (SrcSize <= 0 || SrcSize > 16) + return false; + + // X86-32 passes aggregates on the stack. If this is an extremely simple + // aggregate whose elements would be passed the same if passed as scalars, + // pass them that way in order to promote SROA on the caller and callee side. + // Note that we can't support passing all structs this way. For example, + // {i16, i16} should be passed in on 32-bit unit, which is not how "i16, i16" + // would be passed as stand-alone arguments. + const StructType *STy = dyn_cast(Ty); + if (!STy || STy->isPacked()) return false; + + for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { + const Type *EltTy = STy->getElementType(i); + // 32 and 64-bit integers are fine, as are float, double, and long double. + if (EltTy == Type::Int32Ty || + EltTy == Type::Int64Ty || + EltTy->isFloatingPoint() || + isa(EltTy)) { + Elts.push_back(EltTy); + continue; + } + + // TODO: Vectors are also ok to pass if they don't require extra alignment. + // TODO: We can also pass structs like {i8, i32}. + + Elts.clear(); + return false; + } + + return true; +} + +/* Target hook for llvm-abi.h. It returns true if an aggregate of the specified type should be passed in memory. */ bool llvm_x86_should_pass_aggregate_in_memory(tree TreeType, const Type *Ty) { enum machine_mode Mode = ix86_getNaturalModeForType(TreeType); @@ -800,46 +842,4 @@ } return true; } - -/* Target hook for llvm-abi.h. It returns true if an aggregate of the - specified type should be passed in a number of registers of mixed types. - It also returns a vector of types that correspond to the registers used - for parameter passing. This is only called for x86-32. */ -bool -llvm_x86_32_should_pass_aggregate_in_mixed_regs(tree TreeType, const Type *Ty, - std::vector &Elts){ - // If this is a small fixed size type, investigate it. - HOST_WIDE_INT SrcSize = int_size_in_bytes(TreeType); - if (SrcSize <= 0 || SrcSize > 16) - return false; - - // X86-32 passes aggregates on the stack. If this is an extremely simple - // aggregate whose elements would be passed the same if passed as scalars, - // pass them that way in order to promote SROA on the caller and callee side. - // Note that we can't support passing all structs this way. For example, - // {i16, i16} should be passed in on 32-bit unit, which is not how "i16, i16" - // would be passed as stand-alone arguments. - const StructType *STy = dyn_cast(Ty); - if (!STy || STy->isPacked()) return false; - - for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { - const Type *EltTy = STy->getElementType(i); - // 32 and 64-bit integers are fine, as are float, double, and long double. - if (EltTy == Type::Int32Ty || - EltTy == Type::Int64Ty || - EltTy->isFloatingPoint() || - isa(EltTy)) { - Elts.push_back(EltTy); - continue; - } - - // TODO: Vectors are also ok to pass if they don't require extra alignment. - // TODO: We can also pass structs like {i8, i32}. - - Elts.clear(); - return false; - } - - return true; -} /* LLVM LOCAL end (ENTIRE FILE!) */ From gohman at apple.com Thu Feb 7 21:26:46 2008 From: gohman at apple.com (Dan Gohman) Date: Fri, 08 Feb 2008 03:26:46 -0000 Subject: [llvm-commits] [llvm] r46876 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAGNodes.h lib/CodeGen/SelectionDAG/SelectionDAG.cpp Message-ID: <200802080326.m183QkGm030377@zion.cs.uiuc.edu> Author: djg Date: Thu Feb 7 21:26:46 2008 New Revision: 46876 URL: http://llvm.org/viewvc/llvm-project?rev=46876&view=rev Log: Avoid needlessly casting away const qualifiers. Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=46876&r1=46875&r2=46876&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Thu Feb 7 21:26:46 2008 @@ -1001,7 +1001,7 @@ /// getValueTypeList - Return a pointer to the specified value type. /// - static MVT::ValueType *getValueTypeList(MVT::ValueType VT); + static const MVT::ValueType *getValueTypeList(MVT::ValueType VT); static SDVTList getSDVTList(MVT::ValueType VT) { SDVTList Ret = { getValueTypeList(VT), 1 }; return Ret; Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=46876&r1=46875&r2=46876&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Feb 7 21:26:46 2008 @@ -3563,10 +3563,10 @@ /// getValueTypeList - Return a pointer to the specified value type. /// -MVT::ValueType *SDNode::getValueTypeList(MVT::ValueType VT) { +const MVT::ValueType *SDNode::getValueTypeList(MVT::ValueType VT) { if (MVT::isExtendedVT(VT)) { static std::set EVTs; - return (MVT::ValueType *)&(*EVTs.insert(VT).first); + return &(*EVTs.insert(VT).first); } else { static MVT::ValueType VTs[MVT::LAST_VALUETYPE]; VTs[VT] = VT; From gohman at apple.com Thu Feb 7 21:29:40 2008 From: gohman at apple.com (Dan Gohman) Date: Fri, 08 Feb 2008 03:29:40 -0000 Subject: [llvm-commits] [llvm] r46877 - in /llvm/trunk/lib/Target/X86: X86CodeEmitter.cpp X86ISelLowering.cpp X86RegisterInfo.cpp X86RegisterInfo.h Message-ID: <200802080329.m183Tfn5030472@zion.cs.uiuc.edu> Author: djg Date: Thu Feb 7 21:29:40 2008 New Revision: 46877 URL: http://llvm.org/viewvc/llvm-project?rev=46877&view=rev Log: Avoid needlessly casting away const qualifiers. Modified: llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp llvm/trunk/lib/Target/X86/X86RegisterInfo.h Modified: llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp?rev=46877&r1=46876&r2=46877&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp Thu Feb 7 21:29:40 2008 @@ -84,7 +84,7 @@ unsigned Op, unsigned RegOpcodeField, intptr_t PCAdj = 0); - unsigned getX86RegNum(unsigned RegNo); + unsigned getX86RegNum(unsigned RegNo) const; bool isX86_64ExtendedReg(const MachineOperand &MO); unsigned determineREX(const MachineInstr &MI); @@ -210,8 +210,8 @@ MCE.emitWordLE(0); // The relocated value will be added to the displacement } -unsigned Emitter::getX86RegNum(unsigned RegNo) { - return ((X86RegisterInfo&)II->getRegisterInfo()).getX86RegNum(RegNo); +unsigned Emitter::getX86RegNum(unsigned RegNo) const { + return ((const X86RegisterInfo&)II->getRegisterInfo()).getX86RegNum(RegNo); } inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode, Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=46877&r1=46876&r2=46877&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Feb 7 21:29:40 2008 @@ -4948,9 +4948,9 @@ const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri); const unsigned char N86R10 = - ((X86RegisterInfo*)RegInfo)->getX86RegNum(X86::R10); + ((const X86RegisterInfo*)RegInfo)->getX86RegNum(X86::R10); const unsigned char N86R11 = - ((X86RegisterInfo*)RegInfo)->getX86RegNum(X86::R11); + ((const X86RegisterInfo*)RegInfo)->getX86RegNum(X86::R11); const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix @@ -5038,7 +5038,7 @@ const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri); const unsigned char N86Reg = - ((X86RegisterInfo*)RegInfo)->getX86RegNum(NestReg); + ((const X86RegisterInfo*)RegInfo)->getX86RegNum(NestReg); OutChains[0] = DAG.getStore(Root, DAG.getConstant(MOV32ri|N86Reg, MVT::i8), Trmp, TrmpAddr, 0); Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=46877&r1=46876&r2=46877&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Thu Feb 7 21:29:40 2008 @@ -82,7 +82,7 @@ // getX86RegNum - This function maps LLVM register identifiers to their X86 // specific numbering, which is used in various places encoding instructions. // -unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) { +unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) const { switch(RegNo) { case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX; case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX; Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.h?rev=46877&r1=46876&r2=46877&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86RegisterInfo.h (original) +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.h Thu Feb 7 21:29:40 2008 @@ -71,7 +71,7 @@ /// getX86RegNum - Returns the native X86 register number for the given LLVM /// register identifier. - unsigned getX86RegNum(unsigned RegNo); + unsigned getX86RegNum(unsigned RegNo) const; unsigned getStackAlignment() const { return StackAlign; } From kremenek at apple.com Fri Feb 8 01:14:19 2008 From: kremenek at apple.com (Ted Kremenek) Date: Fri, 08 Feb 2008 07:14:19 -0000 Subject: [llvm-commits] [llvm] r46882 - /llvm/trunk/include/llvm/ADT/APSInt.h Message-ID: <200802080714.m187EJIi004546@zion.cs.uiuc.edu> Author: kremenek Date: Fri Feb 8 01:14:19 2008 New Revision: 46882 URL: http://llvm.org/viewvc/llvm-project?rev=46882&view=rev Log: Constified operator<< in APSInt. Modified: llvm/trunk/include/llvm/ADT/APSInt.h Modified: llvm/trunk/include/llvm/ADT/APSInt.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/APSInt.h?rev=46882&r1=46881&r2=46882&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/APSInt.h (original) +++ llvm/trunk/include/llvm/ADT/APSInt.h Fri Feb 8 01:14:19 2008 @@ -130,8 +130,8 @@ // The remaining operators just wrap the logic of APInt, but retain the // signedness information. - APSInt operator<<(unsigned Bits) { - return APSInt(static_cast(*this) << Bits, IsUnsigned); + APSInt operator<<(unsigned Bits) const { + return APSInt(static_cast(*this) << Bits, IsUnsigned); } APSInt& operator<<=(unsigned Amt) { *this = *this << Amt; From wmatyjewicz at fastmail.fm Fri Feb 8 03:27:05 2008 From: wmatyjewicz at fastmail.fm (Wojciech Matyjewicz) Date: Fri, 08 Feb 2008 10:27:05 +0100 Subject: [llvm-commits] [llvm-gcc-4.2] r46860 - /llvm-gcc-4.2/trunk/gcc/gcc.c In-Reply-To: References: <200802071931.m17JVBVm016313@zion.cs.uiuc.edu> Message-ID: <47AC2069.2040701@fastmail.fm> Devang Patel wrote: > Would it be possible for someone to verify that --emit-llvm works, > after this patch, on non-darwin platforms ? -emit-llvm option doesn't work on Linux platform now, while --emit-llvm does. Is it somehow related to this change? -Wojtek From dpatel at apple.com Fri Feb 8 12:58:16 2008 From: dpatel at apple.com (Devang Patel) Date: Fri, 08 Feb 2008 18:58:16 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r46886 - in /llvm-gcc-4.2/trunk/gcc: config/darwin.h gcc.c Message-ID: <200802081858.m18IwGw2000504@zion.cs.uiuc.edu> Author: dpatel Date: Fri Feb 8 12:58:15 2008 New Revision: 46886 URL: http://llvm.org/viewvc/llvm-project?rev=46886&view=rev Log: Fix -emit-llvm command line handling. Modified: llvm-gcc-4.2/trunk/gcc/config/darwin.h llvm-gcc-4.2/trunk/gcc/gcc.c Modified: llvm-gcc-4.2/trunk/gcc/config/darwin.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/darwin.h?rev=46886&r1=46885&r2=46886&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/darwin.h (original) +++ llvm-gcc-4.2/trunk/gcc/config/darwin.h Fri Feb 8 12:58:15 2008 @@ -134,7 +134,6 @@ { "-dylib_file", "-Zdylib_file" }, \ { "-dynamic", "-Zdynamic" }, \ { "-dynamiclib", "-Zdynamiclib" }, \ - { "-emit-llvm", "-Zemit-llvm" }, \ { "-exported_symbols_list", "-Zexported_symbols_list" }, \ { "-gfull", "-g -fno-eliminate-unused-debug-symbols" }, \ { "-gused", "-g -feliminate-unused-debug-symbols" }, \ Modified: llvm-gcc-4.2/trunk/gcc/gcc.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/gcc.c?rev=46886&r1=46885&r2=46886&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/gcc.c (original) +++ llvm-gcc-4.2/trunk/gcc/gcc.c Fri Feb 8 12:58:15 2008 @@ -1145,10 +1145,8 @@ {"--dependencies", "-M", 0}, {"--dump", "-d", "a"}, {"--dumpbase", "-dumpbase", "a"}, - /* LLVM LOCAL begin */ - {"--emit-llvm", "-Zemit-llvm", 0 }, - {"-emit-llvm", "-Zemit-llvm", 0 }, - /* LLVM LOCAL end */ + /* LLVM LOCAL */ + {"--emit-llvm", "-emit-llvm", 0 }, {"--encoding", "-fencoding=", "aj"}, {"--entry", "-e", 0}, {"--extra-warnings", "-W", 0}, @@ -1228,6 +1226,8 @@ const char *const replacements; } target_option_translations[] = { + /* LLVM LOCAL */ + {"-emit-llvm", "-Zemit-llvm"}, TARGET_OPTION_TRANSLATE_TABLE, { 0, 0 } }; From dpatel at apple.com Fri Feb 8 12:59:15 2008 From: dpatel at apple.com (Devang Patel) Date: Fri, 8 Feb 2008 10:59:15 -0800 Subject: [llvm-commits] [llvm-gcc-4.2] r46860 - /llvm-gcc-4.2/trunk/gcc/gcc.c In-Reply-To: <47AC2069.2040701@fastmail.fm> References: <200802071931.m17JVBVm016313@zion.cs.uiuc.edu> <47AC2069.2040701@fastmail.fm> Message-ID: <9756BA26-D0C7-42C2-A552-AC4D50A86FF0@apple.com> On Feb 8, 2008, at 1:27 AM, Wojciech Matyjewicz wrote: > Devang Patel wrote: >> Would it be possible for someone to verify that --emit-llvm works, >> after this patch, on non-darwin platforms ? > > -emit-llvm option doesn't work on Linux platform now, while --emit- > llvm > does. Is it somehow related to this change? Most likely. Please try again using following patch http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20080204/058023.html Thanks, - Devang From dalej at apple.com Fri Feb 8 13:48:20 2008 From: dalej at apple.com (Dale Johannesen) Date: Fri, 08 Feb 2008 19:48:20 -0000 Subject: [llvm-commits] [llvm] r46890 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <200802081948.m18JmKxh002307@zion.cs.uiuc.edu> Author: johannes Date: Fri Feb 8 13:48:20 2008 New Revision: 46890 URL: http://llvm.org/viewvc/llvm-project?rev=46890&view=rev Log: 64-bit (MMX) vectors do not need restrictive alignment. 128-bit vectors need it only when SSE is on. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=46890&r1=46889&r2=46890&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Feb 8 13:48:20 2008 @@ -704,9 +704,6 @@ if (const VectorType *VTy = dyn_cast(Ty)) { if (VTy->getBitWidth() == 128) MaxAlign = 16; - else if (VTy->getBitWidth() == 64) - if (MaxAlign < 8) - MaxAlign = 8; } else if (const ArrayType *ATy = dyn_cast(Ty)) { unsigned EltAlign = 0; getMaxByValAlign(ATy->getElementType(), EltAlign); @@ -727,13 +724,14 @@ /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate /// function arguments in the caller parameter area. For X86, aggregates -/// that contains are placed at 16-byte boundaries while the rest are at -/// 4-byte boundaries. +/// that contain SSE vectors are placed at 16-byte boundaries while the rest +/// are at 4-byte boundaries. unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const { if (Subtarget->is64Bit()) return getTargetData()->getABITypeAlignment(Ty); unsigned Align = 4; - getMaxByValAlign(Ty, Align); + if (Subtarget->hasSSE1()) + getMaxByValAlign(Ty, Align); return Align; } From evan.cheng at apple.com Fri Feb 8 15:20:40 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 08 Feb 2008 21:20:40 -0000 Subject: [llvm-commits] [llvm] r46893 - in /llvm/trunk: include/llvm/Target/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/CellSPU/ lib/Target/Mips/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/X86/ test/CodeGen/X86/ Message-ID: <200802082120.m18LKe4Y005011@zion.cs.uiuc.edu> Author: evancheng Date: Fri Feb 8 15:20:40 2008 New Revision: 46893 URL: http://llvm.org/viewvc/llvm-project?rev=46893&view=rev Log: It's not always safe to fold movsd into xorpd, etc. Check the alignment of the load address first to make sure it's 16 byte aligned. Added: llvm/trunk/test/CodeGen/X86/2008-02-08-LoadFoldingBug.ll Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp llvm/trunk/lib/Target/ARM/ARMInstrInfo.h llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp llvm/trunk/lib/Target/Mips/MipsInstrInfo.h llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h llvm/trunk/lib/Target/X86/X86InstrInfo.cpp llvm/trunk/lib/Target/X86/X86InstrInfo.h Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=46893&r1=46892&r2=46893&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Fri Feb 8 15:20:40 2008 @@ -262,7 +262,8 @@ /// operand folded, otherwise NULL is returned. The client is responsible for /// removing the old instruction and adding the new one in the instruction /// stream. - virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, + virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, + MachineInstr* MI, SmallVectorImpl &Ops, int FrameIndex) const { return 0; @@ -271,7 +272,8 @@ /// foldMemoryOperand - Same as the previous version except it allows folding /// of any load and store from / to any address, not just from a specific /// stack slot. - virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, + virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, + MachineInstr* MI, SmallVectorImpl &Ops, MachineInstr* LoadMI) const { return 0; Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp?rev=46893&r1=46892&r2=46893&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp Fri Feb 8 15:20:40 2008 @@ -640,9 +640,10 @@ return true; } -MachineInstr *ARMInstrInfo::foldMemoryOperand(MachineInstr *MI, - SmallVectorImpl &Ops, - int FI) const { +MachineInstr *ARMInstrInfo::foldMemoryOperand(MachineFunction &MF, + MachineInstr *MI, + SmallVectorImpl &Ops, + int FI) const { if (Ops.size() != 1) return NULL; unsigned OpNum = Ops[0]; @@ -721,7 +722,7 @@ } bool ARMInstrInfo::canFoldMemoryOperand(MachineInstr *MI, - SmallVectorImpl &Ops) const { + SmallVectorImpl &Ops) const { if (Ops.size() != 1) return false; unsigned OpNum = Ops[0]; Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.h?rev=46893&r1=46892&r2=46893&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.h Fri Feb 8 15:20:40 2008 @@ -191,11 +191,13 @@ MachineBasicBlock::iterator MI, const std::vector &CSI) const; - virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, + virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, + MachineInstr* MI, SmallVectorImpl &Ops, int FrameIndex) const; - virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, + virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, + MachineInstr* MI, SmallVectorImpl &Ops, MachineInstr* LoadMI) const { return 0; Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp?rev=46893&r1=46892&r2=46893&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp Fri Feb 8 15:20:40 2008 @@ -250,9 +250,10 @@ NewMIs.push_back(MIB); } -MachineInstr *AlphaInstrInfo::foldMemoryOperand(MachineInstr *MI, - SmallVectorImpl &Ops, - int FrameIndex) const { +MachineInstr *AlphaInstrInfo::foldMemoryOperand(MachineFunction &MF, + MachineInstr *MI, + SmallVectorImpl &Ops, + int FrameIndex) const { if (Ops.size() != 1) return NULL; // Make sure this is a reg-reg copy. Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h?rev=46893&r1=46892&r2=46893&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h (original) +++ llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h Fri Feb 8 15:20:40 2008 @@ -67,11 +67,13 @@ const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const; - virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, + virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, + MachineInstr* MI, SmallVectorImpl &Ops, int FrameIndex) const; - virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, + virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, + MachineInstr* MI, SmallVectorImpl &Ops, MachineInstr* LoadMI) const { return 0; Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp?rev=46893&r1=46892&r2=46893&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp Fri Feb 8 15:20:40 2008 @@ -391,9 +391,10 @@ /// foldMemoryOperand - SPU, like PPC, can only fold spills into /// copy instructions, turning them into load/store instructions. MachineInstr * -SPUInstrInfo::foldMemoryOperand(MachineInstr *MI, - SmallVectorImpl &Ops, - int FrameIndex) const +SPUInstrInfo::foldMemoryOperand(MachineFunction &MF, + MachineInstr *MI, + SmallVectorImpl &Ops, + int FrameIndex) const { #if SOMEDAY_SCOTT_LOOKS_AT_ME_AGAIN if (Ops.size() != 1) return NULL; Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h?rev=46893&r1=46892&r2=46893&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h (original) +++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h Fri Feb 8 15:20:40 2008 @@ -77,12 +77,14 @@ SmallVectorImpl &NewMIs) const; //! Fold spills into load/store instructions - virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, + virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, + MachineInstr* MI, SmallVectorImpl &Ops, int FrameIndex) const; //! Fold any load/store to an operand - virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, + virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, + MachineInstr* MI, SmallVectorImpl &Ops, MachineInstr* LoadMI) const { return 0; Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=46893&r1=46892&r2=46893&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Fri Feb 8 15:20:40 2008 @@ -370,7 +370,8 @@ } MachineInstr *MipsInstrInfo:: -foldMemoryOperand(MachineInstr* MI, +foldMemoryOperand(MachineFunction &MF, + MachineInstr* MI, SmallVectorImpl &Ops, int FI) const { if (Ops.size() != 1) return NULL; Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.h?rev=46893&r1=46892&r2=46893&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.h (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.h Fri Feb 8 15:20:40 2008 @@ -106,11 +106,13 @@ const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const; - virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, + virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, + MachineInstr* MI, SmallVectorImpl &Ops, int FrameIndex) const; - virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, + virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, + MachineInstr* MI, SmallVectorImpl &Ops, MachineInstr* LoadMI) const { return 0; Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=46893&r1=46892&r2=46893&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Fri Feb 8 15:20:40 2008 @@ -536,7 +536,8 @@ /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into /// copy instructions, turning them into load/store instructions. -MachineInstr *PPCInstrInfo::foldMemoryOperand(MachineInstr *MI, +MachineInstr *PPCInstrInfo::foldMemoryOperand(MachineFunction &MF, + MachineInstr *MI, SmallVectorImpl &Ops, int FrameIndex) const { if (Ops.size() != 1) return NULL; @@ -594,7 +595,7 @@ } bool PPCInstrInfo::canFoldMemoryOperand(MachineInstr *MI, - SmallVectorImpl &Ops) const { + SmallVectorImpl &Ops) const { if (Ops.size() != 1) return false; // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h?rev=46893&r1=46892&r2=46893&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h (original) +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h Fri Feb 8 15:20:40 2008 @@ -131,11 +131,13 @@ /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into /// copy instructions, turning them into load/store instructions. - virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, + virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, + MachineInstr* MI, SmallVectorImpl &Ops, int FrameIndex) const; - virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, + virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, + MachineInstr* MI, SmallVectorImpl &Ops, MachineInstr* LoadMI) const { return 0; Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp?rev=46893&r1=46892&r2=46893&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp Fri Feb 8 15:20:40 2008 @@ -222,9 +222,10 @@ return; } -MachineInstr *SparcInstrInfo::foldMemoryOperand(MachineInstr* MI, - SmallVectorImpl &Ops, - int FI) const { +MachineInstr *SparcInstrInfo::foldMemoryOperand(MachineFunction &MF, + MachineInstr* MI, + SmallVectorImpl &Ops, + int FI) const { if (Ops.size() != 1) return NULL; unsigned OpNum = Ops[0]; Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h?rev=46893&r1=46892&r2=46893&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h (original) +++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h Fri Feb 8 15:20:40 2008 @@ -94,11 +94,13 @@ const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const; - virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, + virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, + MachineInstr* MI, SmallVectorImpl &Ops, int FrameIndex) const; - virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, + virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, + MachineInstr* MI, SmallVectorImpl &Ops, MachineInstr* LoadMI) const { return 0; Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=46893&r1=46892&r2=46893&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Fri Feb 8 15:20:40 2008 @@ -1670,7 +1670,7 @@ MachineInstr* X86InstrInfo::foldMemoryOperand(MachineInstr *MI, unsigned i, - SmallVector &MOs) const { + SmallVector &MOs) const { const DenseMap *OpcodeTablePtr = NULL; bool isTwoAddrFold = false; unsigned NumOps = MI->getDesc().getNumOperands(); @@ -1730,12 +1730,33 @@ } -MachineInstr* X86InstrInfo::foldMemoryOperand(MachineInstr *MI, +MachineInstr* X86InstrInfo::foldMemoryOperand(MachineFunction &MF, + MachineInstr *MI, SmallVectorImpl &Ops, int FrameIndex) const { // Check switch flag if (NoFusing) return NULL; + const MachineFrameInfo *MFI = MF.getFrameInfo(); + unsigned Alignment = MFI->getObjectAlignment(FrameIndex); + // FIXME: Move alignment requirement into tables? + if (Alignment < 16) { + switch (MI->getOpcode()) { + default: break; + // Not always safe to fold movsd into these instructions since their load + // folding variants expects the address to be 16 byte aligned. + case X86::FsANDNPDrr: + case X86::FsANDNPSrr: + case X86::FsANDPDrr: + case X86::FsANDPSrr: + case X86::FsORPDrr: + case X86::FsORPSrr: + case X86::FsXORPDrr: + case X86::FsXORPSrr: + return NULL; + } + } + if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { unsigned NewOpc = 0; switch (MI->getOpcode()) { @@ -1756,12 +1777,39 @@ return foldMemoryOperand(MI, Ops[0], MOs); } -MachineInstr* X86InstrInfo::foldMemoryOperand(MachineInstr *MI, +MachineInstr* X86InstrInfo::foldMemoryOperand(MachineFunction &MF, + MachineInstr *MI, SmallVectorImpl &Ops, MachineInstr *LoadMI) const { // Check switch flag if (NoFusing) return NULL; + unsigned Alignment = 0; + for (unsigned i = 0, e = LoadMI->getNumMemOperands(); i != e; ++i) { + const MemOperand &MRO = LoadMI->getMemOperand(i); + unsigned Align = MRO.getAlignment(); + if (Align > Alignment) + Alignment = Align; + } + + // FIXME: Move alignment requirement into tables? + if (Alignment < 16) { + switch (MI->getOpcode()) { + default: break; + // Not always safe to fold movsd into these instructions since their load + // folding variants expects the address to be 16 byte aligned. + case X86::FsANDNPDrr: + case X86::FsANDNPSrr: + case X86::FsANDPDrr: + case X86::FsANDPSrr: + case X86::FsORPDrr: + case X86::FsORPSrr: + case X86::FsXORPDrr: + case X86::FsXORPSrr: + return NULL; + } + } + if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { unsigned NewOpc = 0; switch (MI->getOpcode()) { Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=46893&r1=46892&r2=46893&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.h (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.h Fri Feb 8 15:20:40 2008 @@ -324,14 +324,16 @@ /// folding and return true, otherwise it should return false. If it folds /// the instruction, it is likely that the MachineInstruction the iterator /// references has been changed. - virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, + virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, + MachineInstr* MI, SmallVectorImpl &Ops, int FrameIndex) const; /// foldMemoryOperand - Same as the previous version except it allows folding /// of any load and store from / to any address, not just from a specific /// stack slot. - virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, + virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, + MachineInstr* MI, SmallVectorImpl &Ops, MachineInstr* LoadMI) const; Added: llvm/trunk/test/CodeGen/X86/2008-02-08-LoadFoldingBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-02-08-LoadFoldingBug.ll?rev=46893&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2008-02-08-LoadFoldingBug.ll (added) +++ llvm/trunk/test/CodeGen/X86/2008-02-08-LoadFoldingBug.ll Fri Feb 8 15:20:40 2008 @@ -0,0 +1,99 @@ +; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep andpd | not grep esp + +declare double @llvm.sqrt.f64(double) nounwind readnone + +declare fastcc void @ApplyGivens(double**, double, double, i32, i32, i32, i32) nounwind + +declare double @fabs(double) + +define void @main_bb114_2E_outer_2E_i_bb3_2E_i27(double** %tmp12.sub.i.i, [51 x double*]* %tmp12.i.i.i, i32 %i.0.reg2mem.0.ph.i, i32 %tmp11688.i, i32 %tmp19.i, i32 %tmp24.i, [51 x double*]* %tmp12.i.i) { +newFuncRoot: + br label %bb3.i27 + +bb111.i77.bb121.i_crit_edge.exitStub: ; preds = %bb111.i77 + ret void + +bb3.i27: ; preds = %bb111.i77.bb3.i27_crit_edge, %newFuncRoot + %indvar94.i = phi i32 [ 0, %newFuncRoot ], [ %tmp113.i76, %bb111.i77.bb3.i27_crit_edge ] ; [#uses=6] + %tmp6.i20 = getelementptr [51 x double*]* %tmp12.i.i, i32 0, i32 %indvar94.i ; [#uses=1] + %tmp7.i21 = load double** %tmp6.i20, align 4 ; [#uses=2] + %tmp10.i = add i32 %indvar94.i, %i.0.reg2mem.0.ph.i ; [#uses=5] + %tmp11.i22 = getelementptr double* %tmp7.i21, i32 %tmp10.i ; [#uses=1] + %tmp12.i23 = load double* %tmp11.i22, align 8 ; [#uses=4] + %tmp20.i24 = add i32 %tmp19.i, %indvar94.i ; [#uses=3] + %tmp21.i = getelementptr double* %tmp7.i21, i32 %tmp20.i24 ; [#uses=1] + %tmp22.i25 = load double* %tmp21.i, align 8 ; [#uses=3] + %tmp1.i.i26 = fcmp oeq double %tmp12.i23, 0.000000e+00 ; [#uses=1] + br i1 %tmp1.i.i26, label %bb3.i27.Givens.exit.i49_crit_edge, label %bb5.i.i31 + +bb5.i.i31: ; preds = %bb3.i27 + %tmp7.i.i28 = call double @fabs( double %tmp12.i23 ) nounwind ; [#uses=1] + %tmp9.i.i29 = call double @fabs( double %tmp22.i25 ) nounwind ; [#uses=1] + %tmp10.i.i30 = fcmp ogt double %tmp7.i.i28, %tmp9.i.i29 ; [#uses=1] + br i1 %tmp10.i.i30, label %bb13.i.i37, label %bb30.i.i43 + +bb13.i.i37: ; preds = %bb5.i.i31 + %tmp15.i.i32 = sub double -0.000000e+00, %tmp22.i25 ; [#uses=1] + %tmp17.i.i33 = fdiv double %tmp15.i.i32, %tmp12.i23 ; [#uses=3] + %tmp20.i4.i = mul double %tmp17.i.i33, %tmp17.i.i33 ; [#uses=1] + %tmp21.i.i34 = add double %tmp20.i4.i, 1.000000e+00 ; [#uses=1] + %tmp22.i.i35 = call double @llvm.sqrt.f64( double %tmp21.i.i34 ) nounwind ; [#uses=1] + %tmp23.i5.i = fdiv double 1.000000e+00, %tmp22.i.i35 ; [#uses=2] + %tmp28.i.i36 = mul double %tmp23.i5.i, %tmp17.i.i33 ; [#uses=1] + br label %Givens.exit.i49 + +bb30.i.i43: ; preds = %bb5.i.i31 + %tmp32.i.i38 = sub double -0.000000e+00, %tmp12.i23 ; [#uses=1] + %tmp34.i.i39 = fdiv double %tmp32.i.i38, %tmp22.i25 ; [#uses=3] + %tmp37.i6.i = mul double %tmp34.i.i39, %tmp34.i.i39 ; [#uses=1] + %tmp38.i.i40 = add double %tmp37.i6.i, 1.000000e+00 ; [#uses=1] + %tmp39.i7.i = call double @llvm.sqrt.f64( double %tmp38.i.i40 ) nounwind ; [#uses=1] + %tmp40.i.i41 = fdiv double 1.000000e+00, %tmp39.i7.i ; [#uses=2] + %tmp45.i.i42 = mul double %tmp40.i.i41, %tmp34.i.i39 ; [#uses=1] + br label %Givens.exit.i49 + +Givens.exit.i49: ; preds = %bb3.i27.Givens.exit.i49_crit_edge, %bb30.i.i43, %bb13.i.i37 + %s.0.i44 = phi double [ %tmp45.i.i42, %bb30.i.i43 ], [ %tmp23.i5.i, %bb13.i.i37 ], [ 0.000000e+00, %bb3.i27.Givens.exit.i49_crit_edge ] ; [#uses=2] + %c.0.i45 = phi double [ %tmp40.i.i41, %bb30.i.i43 ], [ %tmp28.i.i36, %bb13.i.i37 ], [ 1.000000e+00, %bb3.i27.Givens.exit.i49_crit_edge ] ; [#uses=2] + %tmp26.i46 = add i32 %tmp24.i, %indvar94.i ; [#uses=2] + %tmp27.i47 = icmp slt i32 %tmp26.i46, 51 ; [#uses=1] + %min.i48 = select i1 %tmp27.i47, i32 %tmp26.i46, i32 50 ; [#uses=1] + call fastcc void @ApplyGivens( double** %tmp12.sub.i.i, double %s.0.i44, double %c.0.i45, i32 %tmp20.i24, i32 %tmp10.i, i32 %indvar94.i, i32 %min.i48 ) nounwind + br label %codeRepl + +codeRepl: ; preds = %Givens.exit.i49 + call void @main_bb114_2E_outer_2E_i_bb3_2E_i27_bb_2E_i48_2E_i( i32 %tmp10.i, i32 %tmp20.i24, double %s.0.i44, double %c.0.i45, [51 x double*]* %tmp12.i.i.i ) + br label %ApplyRGivens.exit49.i + +ApplyRGivens.exit49.i: ; preds = %codeRepl + %tmp10986.i = icmp sgt i32 %tmp11688.i, %tmp10.i ; [#uses=1] + br i1 %tmp10986.i, label %ApplyRGivens.exit49.i.bb52.i57_crit_edge, label %ApplyRGivens.exit49.i.bb111.i77_crit_edge + +codeRepl1: ; preds = %ApplyRGivens.exit49.i.bb52.i57_crit_edge + call void @main_bb114_2E_outer_2E_i_bb3_2E_i27_bb52_2E_i57( i32 %tmp10.i, double** %tmp12.sub.i.i, [51 x double*]* %tmp12.i.i.i, i32 %i.0.reg2mem.0.ph.i, i32 %tmp11688.i, i32 %tmp19.i, i32 %tmp24.i, [51 x double*]* %tmp12.i.i ) + br label %bb105.i.bb111.i77_crit_edge + +bb111.i77: ; preds = %bb105.i.bb111.i77_crit_edge, %ApplyRGivens.exit49.i.bb111.i77_crit_edge + %tmp113.i76 = add i32 %indvar94.i, 1 ; [#uses=2] + %tmp118.i = icmp sgt i32 %tmp11688.i, %tmp113.i76 ; [#uses=1] + br i1 %tmp118.i, label %bb111.i77.bb3.i27_crit_edge, label %bb111.i77.bb121.i_crit_edge.exitStub + +bb3.i27.Givens.exit.i49_crit_edge: ; preds = %bb3.i27 + br label %Givens.exit.i49 + +ApplyRGivens.exit49.i.bb52.i57_crit_edge: ; preds = %ApplyRGivens.exit49.i + br label %codeRepl1 + +ApplyRGivens.exit49.i.bb111.i77_crit_edge: ; preds = %ApplyRGivens.exit49.i + br label %bb111.i77 + +bb105.i.bb111.i77_crit_edge: ; preds = %codeRepl1 + br label %bb111.i77 + +bb111.i77.bb3.i27_crit_edge: ; preds = %bb111.i77 + br label %bb3.i27 +} + +declare void @main_bb114_2E_outer_2E_i_bb3_2E_i27_bb_2E_i48_2E_i(i32, i32, double, double, [51 x double*]*) + +declare void @main_bb114_2E_outer_2E_i_bb3_2E_i27_bb52_2E_i57(i32, double**, [51 x double*]*, i32, i32, i32, i32, [51 x double*]*) From gohman at apple.com Fri Feb 8 15:58:15 2008 From: gohman at apple.com (Dan Gohman) Date: Fri, 08 Feb 2008 21:58:15 -0000 Subject: [llvm-commits] [llvm] r46894 - /llvm/trunk/include/llvm/ADT/APInt.h Message-ID: <200802082158.m18LwFdG005989@zion.cs.uiuc.edu> Author: djg Date: Fri Feb 8 15:58:15 2008 New Revision: 46894 URL: http://llvm.org/viewvc/llvm-project?rev=46894&view=rev Log: Add an isSignedIntN, like isIntN but for signed integer values instead of unsigned. Modified: llvm/trunk/include/llvm/ADT/APInt.h Modified: llvm/trunk/include/llvm/ADT/APInt.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/APInt.h?rev=46894&r1=46893&r2=46894&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/APInt.h (original) +++ llvm/trunk/include/llvm/ADT/APInt.h Fri Feb 8 15:58:15 2008 @@ -280,7 +280,7 @@ isNegative() && countPopulation() == 1; } - /// @brief Check if this APInt has an N-bits integer value. + /// @brief Check if this APInt has an N-bits unsigned integer value. inline bool isIntN(uint32_t N) const { assert(N && "N == 0 ???"); if (isSingleWord()) { @@ -291,6 +291,12 @@ } } + /// @brief Check if this APInt has an N-bits signed integer value. + inline bool isSignedIntN(uint32_t N) const { + assert(N && "N == 0 ???"); + return getMinSignedBits() <= N; + } + /// @returns true if the argument APInt value is a power of two > 0. bool isPowerOf2() const; @@ -1221,11 +1227,16 @@ return A.ugt(B) ? A : B; } -/// @brief Check if the specified APInt has a N-bits integer value. +/// @brief Check if the specified APInt has a N-bits unsigned integer value. inline bool isIntN(uint32_t N, const APInt& APIVal) { return APIVal.isIntN(N); } +/// @brief Check if the specified APInt has a N-bits signed integer value. +inline bool isSignedIntN(uint32_t N, const APInt& APIVal) { + return APIVal.isSignedIntN(N); +} + /// @returns true if the argument APInt value is a sequence of ones /// starting at the least significant bit with the remainder zero. inline bool isMask(uint32_t numBits, const APInt& APIVal) { From andrewl at lenharth.org Fri Feb 8 15:58:35 2008 From: andrewl at lenharth.org (Andrew Lenharth) Date: Fri, 8 Feb 2008 15:58:35 -0600 Subject: [llvm-commits] [llvm] r46893 - in /llvm/trunk: include/llvm/Target/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/CellSPU/ lib/Target/Mips/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/X86/ test/CodeGen/X86/ In-Reply-To: <200802082120.m18LKe4Y005011@zion.cs.uiuc.edu> References: <200802082120.m18LKe4Y005011@zion.cs.uiuc.edu> Message-ID: <85dfcd7f0802081358i4a91b256ud463fbfc9256aebb@mail.gmail.com> This breaks the build. I think you forgot some files in /lib/Codegen. Andrew On 2/8/08, Evan Cheng wrote: > Author: evancheng > Date: Fri Feb 8 15:20:40 2008 > New Revision: 46893 > > URL: http://llvm.org/viewvc/llvm-project?rev=46893&view=rev > Log: > It's not always safe to fold movsd into xorpd, etc. Check the alignment of the load address first to make sure it's 16 byte aligned. > > Added: > llvm/trunk/test/CodeGen/X86/2008-02-08-LoadFoldingBug.ll > Modified: > llvm/trunk/include/llvm/Target/TargetInstrInfo.h > llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp > llvm/trunk/lib/Target/ARM/ARMInstrInfo.h > llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp > llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h > llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp > llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h > llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp > llvm/trunk/lib/Target/Mips/MipsInstrInfo.h > llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp > llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h > llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp > llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h > llvm/trunk/lib/Target/X86/X86InstrInfo.cpp > llvm/trunk/lib/Target/X86/X86InstrInfo.h > > Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=46893&r1=46892&r2=46893&view=diff > > ============================================================================== > --- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original) > +++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Fri Feb 8 15:20:40 2008 > @@ -262,7 +262,8 @@ > /// operand folded, otherwise NULL is returned. The client is responsible for > /// removing the old instruction and adding the new one in the instruction > /// stream. > - virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, > + virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, > + MachineInstr* MI, > SmallVectorImpl &Ops, > int FrameIndex) const { > return 0; > @@ -271,7 +272,8 @@ > /// foldMemoryOperand - Same as the previous version except it allows folding > /// of any load and store from / to any address, not just from a specific > /// stack slot. > - virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, > + virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, > + MachineInstr* MI, > SmallVectorImpl &Ops, > MachineInstr* LoadMI) const { > return 0; > > Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp?rev=46893&r1=46892&r2=46893&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp Fri Feb 8 15:20:40 2008 > @@ -640,9 +640,10 @@ > return true; > } > > -MachineInstr *ARMInstrInfo::foldMemoryOperand(MachineInstr *MI, > - SmallVectorImpl &Ops, > - int FI) const { > +MachineInstr *ARMInstrInfo::foldMemoryOperand(MachineFunction &MF, > + MachineInstr *MI, > + SmallVectorImpl &Ops, > + int FI) const { > if (Ops.size() != 1) return NULL; > > unsigned OpNum = Ops[0]; > @@ -721,7 +722,7 @@ > } > > bool ARMInstrInfo::canFoldMemoryOperand(MachineInstr *MI, > - SmallVectorImpl &Ops) const { > + SmallVectorImpl &Ops) const { > if (Ops.size() != 1) return false; > > unsigned OpNum = Ops[0]; > > Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.h?rev=46893&r1=46892&r2=46893&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.h (original) > +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.h Fri Feb 8 15:20:40 2008 > @@ -191,11 +191,13 @@ > MachineBasicBlock::iterator MI, > const std::vector &CSI) const; > > - virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, > + virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, > + MachineInstr* MI, > SmallVectorImpl &Ops, > int FrameIndex) const; > > - virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, > + virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, > + MachineInstr* MI, > SmallVectorImpl &Ops, > MachineInstr* LoadMI) const { > return 0; > > Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp?rev=46893&r1=46892&r2=46893&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp (original) > +++ llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp Fri Feb 8 15:20:40 2008 > @@ -250,9 +250,10 @@ > NewMIs.push_back(MIB); > } > > -MachineInstr *AlphaInstrInfo::foldMemoryOperand(MachineInstr *MI, > - SmallVectorImpl &Ops, > - int FrameIndex) const { > +MachineInstr *AlphaInstrInfo::foldMemoryOperand(MachineFunction &MF, > + MachineInstr *MI, > + SmallVectorImpl &Ops, > + int FrameIndex) const { > if (Ops.size() != 1) return NULL; > > // Make sure this is a reg-reg copy. > > Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h?rev=46893&r1=46892&r2=46893&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h (original) > +++ llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h Fri Feb 8 15:20:40 2008 > @@ -67,11 +67,13 @@ > const TargetRegisterClass *RC, > SmallVectorImpl &NewMIs) const; > > - virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, > + virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, > + MachineInstr* MI, > SmallVectorImpl &Ops, > int FrameIndex) const; > > - virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, > + virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, > + MachineInstr* MI, > SmallVectorImpl &Ops, > MachineInstr* LoadMI) const { > return 0; > > Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp?rev=46893&r1=46892&r2=46893&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp (original) > +++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp Fri Feb 8 15:20:40 2008 > @@ -391,9 +391,10 @@ > /// foldMemoryOperand - SPU, like PPC, can only fold spills into > /// copy instructions, turning them into load/store instructions. > MachineInstr * > -SPUInstrInfo::foldMemoryOperand(MachineInstr *MI, > - SmallVectorImpl &Ops, > - int FrameIndex) const > +SPUInstrInfo::foldMemoryOperand(MachineFunction &MF, > + MachineInstr *MI, > + SmallVectorImpl &Ops, > + int FrameIndex) const > { > #if SOMEDAY_SCOTT_LOOKS_AT_ME_AGAIN > if (Ops.size() != 1) return NULL; > > Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h?rev=46893&r1=46892&r2=46893&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h (original) > +++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h Fri Feb 8 15:20:40 2008 > @@ -77,12 +77,14 @@ > SmallVectorImpl &NewMIs) const; > > //! Fold spills into load/store instructions > - virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, > + virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, > + MachineInstr* MI, > SmallVectorImpl &Ops, > int FrameIndex) const; > > //! Fold any load/store to an operand > - virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, > + virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, > + MachineInstr* MI, > SmallVectorImpl &Ops, > MachineInstr* LoadMI) const { > return 0; > > Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=46893&r1=46892&r2=46893&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp (original) > +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Fri Feb 8 15:20:40 2008 > @@ -370,7 +370,8 @@ > } > > MachineInstr *MipsInstrInfo:: > -foldMemoryOperand(MachineInstr* MI, > +foldMemoryOperand(MachineFunction &MF, > + MachineInstr* MI, > SmallVectorImpl &Ops, int FI) const > { > if (Ops.size() != 1) return NULL; > > Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.h?rev=46893&r1=46892&r2=46893&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.h (original) > +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.h Fri Feb 8 15:20:40 2008 > @@ -106,11 +106,13 @@ > const TargetRegisterClass *RC, > SmallVectorImpl &NewMIs) const; > > - virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, > + virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, > + MachineInstr* MI, > SmallVectorImpl &Ops, > int FrameIndex) const; > > - virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, > + virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, > + MachineInstr* MI, > SmallVectorImpl &Ops, > MachineInstr* LoadMI) const { > return 0; > > Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=46893&r1=46892&r2=46893&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original) > +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Fri Feb 8 15:20:40 2008 > @@ -536,7 +536,8 @@ > > /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into > /// copy instructions, turning them into load/store instructions. > -MachineInstr *PPCInstrInfo::foldMemoryOperand(MachineInstr *MI, > +MachineInstr *PPCInstrInfo::foldMemoryOperand(MachineFunction &MF, > + MachineInstr *MI, > SmallVectorImpl &Ops, > int FrameIndex) const { > if (Ops.size() != 1) return NULL; > @@ -594,7 +595,7 @@ > } > > bool PPCInstrInfo::canFoldMemoryOperand(MachineInstr *MI, > - SmallVectorImpl &Ops) const { > + SmallVectorImpl &Ops) const { > if (Ops.size() != 1) return false; > > // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because > > Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h?rev=46893&r1=46892&r2=46893&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h (original) > +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h Fri Feb 8 15:20:40 2008 > @@ -131,11 +131,13 @@ > > /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into > /// copy instructions, turning them into load/store instructions. > - virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, > + virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, > + MachineInstr* MI, > SmallVectorImpl &Ops, > int FrameIndex) const; > > - virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, > + virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, > + MachineInstr* MI, > SmallVectorImpl &Ops, > MachineInstr* LoadMI) const { > return 0; > > Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp?rev=46893&r1=46892&r2=46893&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp (original) > +++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp Fri Feb 8 15:20:40 2008 > @@ -222,9 +222,10 @@ > return; > } > > -MachineInstr *SparcInstrInfo::foldMemoryOperand(MachineInstr* MI, > - SmallVectorImpl &Ops, > - int FI) const { > +MachineInstr *SparcInstrInfo::foldMemoryOperand(MachineFunction &MF, > + MachineInstr* MI, > + SmallVectorImpl &Ops, > + int FI) const { > if (Ops.size() != 1) return NULL; > > unsigned OpNum = Ops[0]; > > Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h?rev=46893&r1=46892&r2=46893&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h (original) > +++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h Fri Feb 8 15:20:40 2008 > @@ -94,11 +94,13 @@ > const TargetRegisterClass *RC, > SmallVectorImpl &NewMIs) const; > > - virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, > + virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, > + MachineInstr* MI, > SmallVectorImpl &Ops, > int FrameIndex) const; > > - virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, > + virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, > + MachineInstr* MI, > SmallVectorImpl &Ops, > MachineInstr* LoadMI) const { > return 0; > > Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=46893&r1=46892&r2=46893&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) > +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Fri Feb 8 15:20:40 2008 > @@ -1670,7 +1670,7 @@ > > MachineInstr* > X86InstrInfo::foldMemoryOperand(MachineInstr *MI, unsigned i, > - SmallVector &MOs) const { > + SmallVector &MOs) const { > const DenseMap *OpcodeTablePtr = NULL; > bool isTwoAddrFold = false; > unsigned NumOps = MI->getDesc().getNumOperands(); > @@ -1730,12 +1730,33 @@ > } > > > -MachineInstr* X86InstrInfo::foldMemoryOperand(MachineInstr *MI, > +MachineInstr* X86InstrInfo::foldMemoryOperand(MachineFunction &MF, > + MachineInstr *MI, > SmallVectorImpl &Ops, > int FrameIndex) const { > // Check switch flag > if (NoFusing) return NULL; > > + const MachineFrameInfo *MFI = MF.getFrameInfo(); > + unsigned Alignment = MFI->getObjectAlignment(FrameIndex); > + // FIXME: Move alignment requirement into tables? > + if (Alignment < 16) { > + switch (MI->getOpcode()) { > + default: break; > + // Not always safe to fold movsd into these instructions since their load > + // folding variants expects the address to be 16 byte aligned. > + case X86::FsANDNPDrr: > + case X86::FsANDNPSrr: > + case X86::FsANDPDrr: > + case X86::FsANDPSrr: > + case X86::FsORPDrr: > + case X86::FsORPSrr: > + case X86::FsXORPDrr: > + case X86::FsXORPSrr: > + return NULL; > + } > + } > + > if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { > unsigned NewOpc = 0; > switch (MI->getOpcode()) { > @@ -1756,12 +1777,39 @@ > return foldMemoryOperand(MI, Ops[0], MOs); > } > > -MachineInstr* X86InstrInfo::foldMemoryOperand(MachineInstr *MI, > +MachineInstr* X86InstrInfo::foldMemoryOperand(MachineFunction &MF, > + MachineInstr *MI, > SmallVectorImpl &Ops, > MachineInstr *LoadMI) const { > // Check switch flag > if (NoFusing) return NULL; > > + unsigned Alignment = 0; > + for (unsigned i = 0, e = LoadMI->getNumMemOperands(); i != e; ++i) { > + const MemOperand &MRO = LoadMI->getMemOperand(i); > + unsigned Align = MRO.getAlignment(); > + if (Align > Alignment) > + Alignment = Align; > + } > + > + // FIXME: Move alignment requirement into tables? > + if (Alignment < 16) { > + switch (MI->getOpcode()) { > + default: break; > + // Not always safe to fold movsd into these instructions since their load > + // folding variants expects the address to be 16 byte aligned. > + case X86::FsANDNPDrr: > + case X86::FsANDNPSrr: > + case X86::FsANDPDrr: > + case X86::FsANDPSrr: > + case X86::FsORPDrr: > + case X86::FsORPSrr: > + case X86::FsXORPDrr: > + case X86::FsXORPSrr: > + return NULL; > + } > + } > + > if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { > unsigned NewOpc = 0; > switch (MI->getOpcode()) { > > Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=46893&r1=46892&r2=46893&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/X86/X86InstrInfo.h (original) > +++ llvm/trunk/lib/Target/X86/X86InstrInfo.h Fri Feb 8 15:20:40 2008 > @@ -324,14 +324,16 @@ > /// folding and return true, otherwise it should return false. If it folds > /// the instruction, it is likely that the MachineInstruction the iterator > /// references has been changed. > - virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, > + virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, > + MachineInstr* MI, > SmallVectorImpl &Ops, > int FrameIndex) const; > > /// foldMemoryOperand - Same as the previous version except it allows folding > /// of any load and store from / to any address, not just from a specific > /// stack slot. > - virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, > + virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, > + MachineInstr* MI, > SmallVectorImpl &Ops, > MachineInstr* LoadMI) const; > > > Added: llvm/trunk/test/CodeGen/X86/2008-02-08-LoadFoldingBug.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-02-08-LoadFoldingBug.ll?rev=46893&view=auto > > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/2008-02-08-LoadFoldingBug.ll (added) > +++ llvm/trunk/test/CodeGen/X86/2008-02-08-LoadFoldingBug.ll Fri Feb 8 15:20:40 2008 > @@ -0,0 +1,99 @@ > +; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep andpd | not grep esp > + > +declare double @llvm.sqrt.f64(double) nounwind readnone > + > +declare fastcc void @ApplyGivens(double**, double, double, i32, i32, i32, i32) nounwind > + > +declare double @fabs(double) > + > +define void @main_bb114_2E_outer_2E_i_bb3_2E_i27(double** %tmp12.sub.i.i, [51 x double*]* %tmp12.i.i.i, i32 %i.0.reg2mem.0.ph.i, i32 %tmp11688.i, i32 %tmp19.i, i32 %tmp24.i, [51 x double*]* %tmp12.i.i) { > +newFuncRoot: > + br label %bb3.i27 > + > +bb111.i77.bb121.i_crit_edge.exitStub: ; preds = %bb111.i77 > + ret void > + > +bb3.i27: ; preds = %bb111.i77.bb3.i27_crit_edge, %newFuncRoot > + %indvar94.i = phi i32 [ 0, %newFuncRoot ], [ %tmp113.i76, %bb111.i77.bb3.i27_crit_edge ] ; [#uses=6] > + %tmp6.i20 = getelementptr [51 x double*]* %tmp12.i.i, i32 0, i32 %indvar94.i ; [#uses=1] > + %tmp7.i21 = load double** %tmp6.i20, align 4 ; [#uses=2] > + %tmp10.i = add i32 %indvar94.i, %i.0.reg2mem.0.ph.i ; [#uses=5] > + %tmp11.i22 = getelementptr double* %tmp7.i21, i32 %tmp10.i ; [#uses=1] > + %tmp12.i23 = load double* %tmp11.i22, align 8 ; [#uses=4] > + %tmp20.i24 = add i32 %tmp19.i, %indvar94.i ; [#uses=3] > + %tmp21.i = getelementptr double* %tmp7.i21, i32 %tmp20.i24 ; [#uses=1] > + %tmp22.i25 = load double* %tmp21.i, align 8 ; [#uses=3] > + %tmp1.i.i26 = fcmp oeq double %tmp12.i23, 0.000000e+00 ; [#uses=1] > + br i1 %tmp1.i.i26, label %bb3.i27.Givens.exit.i49_crit_edge, label %bb5.i.i31 > + > +bb5.i.i31: ; preds = %bb3.i27 > + %tmp7.i.i28 = call double @fabs( double %tmp12.i23 ) nounwind ; [#uses=1] > + %tmp9.i.i29 = call double @fabs( double %tmp22.i25 ) nounwind ; [#uses=1] > + %tmp10.i.i30 = fcmp ogt double %tmp7.i.i28, %tmp9.i.i29 ; [#uses=1] > + br i1 %tmp10.i.i30, label %bb13.i.i37, label %bb30.i.i43 > + > +bb13.i.i37: ; preds = %bb5.i.i31 > + %tmp15.i.i32 = sub double -0.000000e+00, %tmp22.i25 ; [#uses=1] > + %tmp17.i.i33 = fdiv double %tmp15.i.i32, %tmp12.i23 ; [#uses=3] > + %tmp20.i4.i = mul double %tmp17.i.i33, %tmp17.i.i33 ; [#uses=1] > + %tmp21.i.i34 = add double %tmp20.i4.i, 1.000000e+00 ; [#uses=1] > + %tmp22.i.i35 = call double @llvm.sqrt.f64( double %tmp21.i.i34 ) nounwind ; [#uses=1] > + %tmp23.i5.i = fdiv double 1.000000e+00, %tmp22.i.i35 ; [#uses=2] > + %tmp28.i.i36 = mul double %tmp23.i5.i, %tmp17.i.i33 ; [#uses=1] > + br label %Givens.exit.i49 > + > +bb30.i.i43: ; preds = %bb5.i.i31 > + %tmp32.i.i38 = sub double -0.000000e+00, %tmp12.i23 ; [#uses=1] > + %tmp34.i.i39 = fdiv double %tmp32.i.i38, %tmp22.i25 ; [#uses=3] > + %tmp37.i6.i = mul double %tmp34.i.i39, %tmp34.i.i39 ; [#uses=1] > + %tmp38.i.i40 = add double %tmp37.i6.i, 1.000000e+00 ; [#uses=1] > + %tmp39.i7.i = call double @llvm.sqrt.f64( double %tmp38.i.i40 ) nounwind ; [#uses=1] > + %tmp40.i.i41 = fdiv double 1.000000e+00, %tmp39.i7.i ; [#uses=2] > + %tmp45.i.i42 = mul double %tmp40.i.i41, %tmp34.i.i39 ; [#uses=1] > + br label %Givens.exit.i49 > + > +Givens.exit.i49: ; preds = %bb3.i27.Givens.exit.i49_crit_edge, %bb30.i.i43, %bb13.i.i37 > + %s.0.i44 = phi double [ %tmp45.i.i42, %bb30.i.i43 ], [ %tmp23.i5.i, %bb13.i.i37 ], [ 0.000000e+00, %bb3.i27.Givens.exit.i49_crit_edge ] ; [#uses=2] > + %c.0.i45 = phi double [ %tmp40.i.i41, %bb30.i.i43 ], [ %tmp28.i.i36, %bb13.i.i37 ], [ 1.000000e+00, %bb3.i27.Givens.exit.i49_crit_edge ] ; [#uses=2] > + %tmp26.i46 = add i32 %tmp24.i, %indvar94.i ; [#uses=2] > + %tmp27.i47 = icmp slt i32 %tmp26.i46, 51 ; [#uses=1] > + %min.i48 = select i1 %tmp27.i47, i32 %tmp26.i46, i32 50 ; [#uses=1] > + call fastcc void @ApplyGivens( double** %tmp12.sub.i.i, double %s.0.i44, double %c.0.i45, i32 %tmp20.i24, i32 %tmp10.i, i32 %indvar94.i, i32 %min.i48 ) nounwind > + br label %codeRepl > + > +codeRepl: ; preds = %Givens.exit.i49 > + call void @main_bb114_2E_outer_2E_i_bb3_2E_i27_bb_2E_i48_2E_i( i32 %tmp10.i, i32 %tmp20.i24, double %s.0.i44, double %c.0.i45, [51 x double*]* %tmp12.i.i.i ) > + br label %ApplyRGivens.exit49.i > + > +ApplyRGivens.exit49.i: ; preds = %codeRepl > + %tmp10986.i = icmp sgt i32 %tmp11688.i, %tmp10.i ; [#uses=1] > + br i1 %tmp10986.i, label %ApplyRGivens.exit49.i.bb52.i57_crit_edge, label %ApplyRGivens.exit49.i.bb111.i77_crit_edge > + > +codeRepl1: ; preds = %ApplyRGivens.exit49.i.bb52.i57_crit_edge > + call void @main_bb114_2E_outer_2E_i_bb3_2E_i27_bb52_2E_i57( i32 %tmp10.i, double** %tmp12.sub.i.i, [51 x double*]* %tmp12.i.i.i, i32 %i.0.reg2mem.0.ph.i, i32 %tmp11688.i, i32 %tmp19.i, i32 %tmp24.i, [51 x double*]* %tmp12.i.i ) > + br label %bb105.i.bb111.i77_crit_edge > + > +bb111.i77: ; preds = %bb105.i.bb111.i77_crit_edge, %ApplyRGivens.exit49.i.bb111.i77_crit_edge > + %tmp113.i76 = add i32 %indvar94.i, 1 ; [#uses=2] > + %tmp118.i = icmp sgt i32 %tmp11688.i, %tmp113.i76 ; [#uses=1] > + br i1 %tmp118.i, label %bb111.i77.bb3.i27_crit_edge, label %bb111.i77.bb121.i_crit_edge.exitStub > + > +bb3.i27.Givens.exit.i49_crit_edge: ; preds = %bb3.i27 > + br label %Givens.exit.i49 > + > +ApplyRGivens.exit49.i.bb52.i57_crit_edge: ; preds = %ApplyRGivens.exit49.i > + br label %codeRepl1 > + > +ApplyRGivens.exit49.i.bb111.i77_crit_edge: ; preds = %ApplyRGivens.exit49.i > + br label %bb111.i77 > + > +bb105.i.bb111.i77_crit_edge: ; preds = %codeRepl1 > + br label %bb111.i77 > + > +bb111.i77.bb3.i27_crit_edge: ; preds = %bb111.i77 > + br label %bb3.i27 > +} > + > +declare void @main_bb114_2E_outer_2E_i_bb3_2E_i27_bb_2E_i48_2E_i(i32, i32, double, double, [51 x double*]*) > + > +declare void @main_bb114_2E_outer_2E_i_bb3_2E_i27_bb52_2E_i57(i32, double**, [51 x double*]*, i32, i32, i32, i32, [51 x double*]*) > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From evan.cheng at apple.com Fri Feb 8 16:05:07 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 08 Feb 2008 22:05:07 -0000 Subject: [llvm-commits] [llvm] r46895 - /llvm/trunk/lib/CodeGen/MachineInstr.cpp Message-ID: <200802082205.m18M57tn006178@zion.cs.uiuc.edu> Author: evancheng Date: Fri Feb 8 16:05:07 2008 New Revision: 46895 URL: http://llvm.org/viewvc/llvm-project?rev=46895&view=rev Log: Also print alignment. Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=46895&r1=46894&r2=46895&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Fri Feb 8 16:05:07 2008 @@ -647,7 +647,7 @@ if (MRO.isStore()) OS << "ST"; - OS << "(" << MRO.getSize() << ") ["; + OS << "(" << MRO.getSize() << "," << MRO.getAlignment() << ") ["; if (!V) OS << ""; From evan.cheng at apple.com Fri Feb 8 16:05:27 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 08 Feb 2008 22:05:27 -0000 Subject: [llvm-commits] [llvm] r46896 - in /llvm/trunk/lib/CodeGen: LiveIntervalAnalysis.cpp RegAllocBigBlock.cpp VirtRegMap.cpp Message-ID: <200802082205.m18M5RSs006200@zion.cs.uiuc.edu> Author: evancheng Date: Fri Feb 8 16:05:27 2008 New Revision: 46896 URL: http://llvm.org/viewvc/llvm-project?rev=46896&view=rev Log: Forgot these files. Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp llvm/trunk/lib/CodeGen/RegAllocBigBlock.cpp llvm/trunk/lib/CodeGen/VirtRegMap.cpp Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=46896&r1=46895&r2=46896&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Fri Feb 8 16:05:27 2008 @@ -709,8 +709,8 @@ FoldOps.push_back(OpIdx); } - MachineInstr *fmi = isSS ? tii_->foldMemoryOperand(MI, FoldOps, Slot) - : tii_->foldMemoryOperand(MI, FoldOps, DefMI); + MachineInstr *fmi = isSS ? tii_->foldMemoryOperand(*mf_, MI, FoldOps, Slot) + : tii_->foldMemoryOperand(*mf_, MI, FoldOps, DefMI); if (fmi) { // Attempt to fold the memory reference into the instruction. If // we can do this, we don't need to insert spill code. Modified: llvm/trunk/lib/CodeGen/RegAllocBigBlock.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocBigBlock.cpp?rev=46896&r1=46895&r2=46896&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocBigBlock.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocBigBlock.cpp Fri Feb 8 16:05:27 2008 @@ -521,7 +521,7 @@ // try to fold the spill into the instruction SmallVector Ops; Ops.push_back(OpNum); - if(MachineInstr* FMI = TII->foldMemoryOperand(MI, Ops, FrameIndex)) { + if(MachineInstr* FMI = TII->foldMemoryOperand(*MF, MI, Ops, FrameIndex)) { ++NumFolded; FMI->copyKillDeadInfo(MI); return MBB.insert(MBB.erase(MI), FMI); Modified: llvm/trunk/lib/CodeGen/VirtRegMap.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/VirtRegMap.cpp?rev=46896&r1=46895&r2=46896&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/VirtRegMap.cpp (original) +++ llvm/trunk/lib/CodeGen/VirtRegMap.cpp Fri Feb 8 16:05:27 2008 @@ -839,7 +839,7 @@ assert(Idx != -1); SmallVector Ops; Ops.push_back(Idx); - MachineInstr *FoldedMI = TII->foldMemoryOperand(NewMI, Ops, SS); + MachineInstr *FoldedMI = TII->foldMemoryOperand(MF, NewMI, Ops, SS); if (FoldedMI) { if (!VRM.hasPhys(UnfoldVR)) VRM.assignVirt2Phys(UnfoldVR, UnfoldPR); From evan.cheng at apple.com Fri Feb 8 16:06:30 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 8 Feb 2008 14:06:30 -0800 Subject: [llvm-commits] [llvm] r46893 - in /llvm/trunk: include/llvm/Target/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/CellSPU/ lib/Target/Mips/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/X86/ test/CodeGen/X86/ In-Reply-To: <85dfcd7f0802081358i4a91b256ud463fbfc9256aebb@mail.gmail.com> References: <200802082120.m18LKe4Y005011@zion.cs.uiuc.edu> <85dfcd7f0802081358i4a91b256ud463fbfc9256aebb@mail.gmail.com> Message-ID: Sorry, committed. I seem to have some issues with my setup. Evan On Feb 8, 2008, at 1:58 PM, Andrew Lenharth wrote: > This breaks the build. I think you forgot some files in /lib/Codegen. > > Andrew > > On 2/8/08, Evan Cheng wrote: >> Author: evancheng >> Date: Fri Feb 8 15:20:40 2008 >> New Revision: 46893 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=46893&view=rev >> Log: >> It's not always safe to fold movsd into xorpd, etc. Check the >> alignment of the load address first to make sure it's 16 byte >> aligned. >> >> Added: >> llvm/trunk/test/CodeGen/X86/2008-02-08-LoadFoldingBug.ll >> Modified: >> llvm/trunk/include/llvm/Target/TargetInstrInfo.h >> llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp >> llvm/trunk/lib/Target/ARM/ARMInstrInfo.h >> llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp >> llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h >> llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp >> llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h >> llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp >> llvm/trunk/lib/Target/Mips/MipsInstrInfo.h >> llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp >> llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h >> llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp >> llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h >> llvm/trunk/lib/Target/X86/X86InstrInfo.cpp >> llvm/trunk/lib/Target/X86/X86InstrInfo.h >> >> Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=46893&r1=46892&r2=46893&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original) >> +++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Fri Feb 8 >> 15:20:40 2008 >> @@ -262,7 +262,8 @@ >> /// operand folded, otherwise NULL is returned. The client is >> responsible for >> /// removing the old instruction and adding the new one in the >> instruction >> /// stream. >> - virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, >> + virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, >> + MachineInstr* MI, >> SmallVectorImpl >> &Ops, >> int FrameIndex) const { >> return 0; >> @@ -271,7 +272,8 @@ >> /// foldMemoryOperand - Same as the previous version except it >> allows folding >> /// of any load and store from / to any address, not just from a >> specific >> /// stack slot. >> - virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, >> + virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, >> + MachineInstr* MI, >> SmallVectorImpl >> &Ops, >> MachineInstr* LoadMI) >> const { >> return 0; >> >> Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp?rev=46893&r1=46892&r2=46893&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp (original) >> +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp Fri Feb 8 15:20:40 >> 2008 >> @@ -640,9 +640,10 @@ >> return true; >> } >> >> -MachineInstr *ARMInstrInfo::foldMemoryOperand(MachineInstr *MI, >> - >> SmallVectorImpl &Ops, >> - int FI) const { >> +MachineInstr *ARMInstrInfo::foldMemoryOperand(MachineFunction &MF, >> + MachineInstr *MI, >> + >> SmallVectorImpl &Ops, >> + int FI) const { >> if (Ops.size() != 1) return NULL; >> >> unsigned OpNum = Ops[0]; >> @@ -721,7 +722,7 @@ >> } >> >> bool ARMInstrInfo::canFoldMemoryOperand(MachineInstr *MI, >> - SmallVectorImpl >> &Ops) const { >> + SmallVectorImpl >> &Ops) const { >> if (Ops.size() != 1) return false; >> >> unsigned OpNum = Ops[0]; >> >> Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.h?rev=46893&r1=46892&r2=46893&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.h (original) >> +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.h Fri Feb 8 15:20:40 2008 >> @@ -191,11 +191,13 @@ >> >> MachineBasicBlock::iterator MI, >> const std::vector >> &CSI) const; >> >> - virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, >> + virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, >> + MachineInstr* MI, >> SmallVectorImpl >> &Ops, >> int FrameIndex) const; >> >> - virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, >> + virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, >> + MachineInstr* MI, >> SmallVectorImpl >> &Ops, >> MachineInstr* LoadMI) >> const { >> return 0; >> >> Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp?rev=46893&r1=46892&r2=46893&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp (original) >> +++ llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp Fri Feb 8 >> 15:20:40 2008 >> @@ -250,9 +250,10 @@ >> NewMIs.push_back(MIB); >> } >> >> -MachineInstr *AlphaInstrInfo::foldMemoryOperand(MachineInstr *MI, >> - >> SmallVectorImpl &Ops, >> - int FrameIndex) >> const { >> +MachineInstr *AlphaInstrInfo::foldMemoryOperand(MachineFunction &MF, >> + MachineInstr *MI, >> + >> SmallVectorImpl &Ops, >> + int FrameIndex) >> const { >> if (Ops.size() != 1) return NULL; >> >> // Make sure this is a reg-reg copy. >> >> Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h?rev=46893&r1=46892&r2=46893&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h (original) >> +++ llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h Fri Feb 8 >> 15:20:40 2008 >> @@ -67,11 +67,13 @@ >> const TargetRegisterClass *RC, >> SmallVectorImpl >> &NewMIs) const; >> >> - virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, >> + virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, >> + MachineInstr* MI, >> SmallVectorImpl >> &Ops, >> int FrameIndex) const; >> >> - virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, >> + virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, >> + MachineInstr* MI, >> SmallVectorImpl >> &Ops, >> MachineInstr* LoadMI) >> const { >> return 0; >> >> Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp?rev=46893&r1=46892&r2=46893&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp (original) >> +++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp Fri Feb 8 >> 15:20:40 2008 >> @@ -391,9 +391,10 @@ >> /// foldMemoryOperand - SPU, like PPC, can only fold spills into >> /// copy instructions, turning them into load/store instructions. >> MachineInstr * >> -SPUInstrInfo::foldMemoryOperand(MachineInstr *MI, >> - SmallVectorImpl &Ops, >> - int FrameIndex) const >> +SPUInstrInfo::foldMemoryOperand(MachineFunction &MF, >> + MachineInstr *MI, >> + SmallVectorImpl &Ops, >> + int FrameIndex) const >> { >> #if SOMEDAY_SCOTT_LOOKS_AT_ME_AGAIN >> if (Ops.size() != 1) return NULL; >> >> Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h?rev=46893&r1=46892&r2=46893&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h (original) >> +++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h Fri Feb 8 >> 15:20:40 2008 >> @@ -77,12 +77,14 @@ >> SmallVectorImpl >> &NewMIs) const; >> >> //! Fold spills into load/store instructions >> - virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, >> + virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, >> + MachineInstr* MI, >> >> SmallVectorImpl &Ops, >> int FrameIndex) const; >> >> //! Fold any load/store to an operand >> - virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, >> + virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, >> + MachineInstr* MI, >> >> SmallVectorImpl &Ops, >> MachineInstr* LoadMI) >> const { >> return 0; >> >> Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=46893&r1=46892&r2=46893&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp (original) >> +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Fri Feb 8 >> 15:20:40 2008 >> @@ -370,7 +370,8 @@ >> } >> >> MachineInstr *MipsInstrInfo:: >> -foldMemoryOperand(MachineInstr* MI, >> +foldMemoryOperand(MachineFunction &MF, >> + MachineInstr* MI, >> SmallVectorImpl &Ops, int FI) const >> { >> if (Ops.size() != 1) return NULL; >> >> Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.h?rev=46893&r1=46892&r2=46893&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.h (original) >> +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.h Fri Feb 8 15:20:40 >> 2008 >> @@ -106,11 +106,13 @@ >> const TargetRegisterClass *RC, >> SmallVectorImpl >> &NewMIs) const; >> >> - virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, >> + virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, >> + MachineInstr* MI, >> SmallVectorImpl >> &Ops, >> int FrameIndex) const; >> >> - virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, >> + virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, >> + MachineInstr* MI, >> SmallVectorImpl >> &Ops, >> MachineInstr* LoadMI) >> const { >> return 0; >> >> Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=46893&r1=46892&r2=46893&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original) >> +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Fri Feb 8 >> 15:20:40 2008 >> @@ -536,7 +536,8 @@ >> >> /// foldMemoryOperand - PowerPC (like most RISC's) can only fold >> spills into >> /// copy instructions, turning them into load/store instructions. >> -MachineInstr *PPCInstrInfo::foldMemoryOperand(MachineInstr *MI, >> +MachineInstr *PPCInstrInfo::foldMemoryOperand(MachineFunction &MF, >> + MachineInstr *MI, >> >> SmallVectorImpl &Ops, >> int FrameIndex) const { >> if (Ops.size() != 1) return NULL; >> @@ -594,7 +595,7 @@ >> } >> >> bool PPCInstrInfo::canFoldMemoryOperand(MachineInstr *MI, >> - SmallVectorImpl >> &Ops) const { >> + SmallVectorImpl >> &Ops) const { >> if (Ops.size() != 1) return false; >> >> // Make sure this is a reg-reg copy. Note that we can't handle >> MCRF, because >> >> Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h?rev=46893&r1=46892&r2=46893&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h (original) >> +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h Fri Feb 8 >> 15:20:40 2008 >> @@ -131,11 +131,13 @@ >> >> /// foldMemoryOperand - PowerPC (like most RISC's) can only fold >> spills into >> /// copy instructions, turning them into load/store instructions. >> - virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, >> + virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, >> + MachineInstr* MI, >> SmallVectorImpl >> &Ops, >> int FrameIndex) const; >> >> - virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, >> + virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, >> + MachineInstr* MI, >> SmallVectorImpl >> &Ops, >> MachineInstr* LoadMI) >> const { >> return 0; >> >> Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp?rev=46893&r1=46892&r2=46893&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp (original) >> +++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp Fri Feb 8 >> 15:20:40 2008 >> @@ -222,9 +222,10 @@ >> return; >> } >> >> -MachineInstr *SparcInstrInfo::foldMemoryOperand(MachineInstr* MI, >> - >> SmallVectorImpl &Ops, >> - int FI) const { >> +MachineInstr *SparcInstrInfo::foldMemoryOperand(MachineFunction &MF, >> + MachineInstr* MI, >> + >> SmallVectorImpl &Ops, >> + int FI) const { >> if (Ops.size() != 1) return NULL; >> >> unsigned OpNum = Ops[0]; >> >> Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h?rev=46893&r1=46892&r2=46893&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h (original) >> +++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h Fri Feb 8 >> 15:20:40 2008 >> @@ -94,11 +94,13 @@ >> const TargetRegisterClass *RC, >> SmallVectorImpl >> &NewMIs) const; >> >> - virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, >> + virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, >> + MachineInstr* MI, >> SmallVectorImpl >> &Ops, >> int FrameIndex) const; >> >> - virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, >> + virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, >> + MachineInstr* MI, >> SmallVectorImpl >> &Ops, >> MachineInstr* LoadMI) >> const { >> return 0; >> >> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=46893&r1=46892&r2=46893&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) >> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Fri Feb 8 15:20:40 >> 2008 >> @@ -1670,7 +1670,7 @@ >> >> MachineInstr* >> X86InstrInfo::foldMemoryOperand(MachineInstr *MI, unsigned i, >> - SmallVector >> &MOs) const { >> + SmallVector >> &MOs) const { >> const DenseMap *OpcodeTablePtr = NULL; >> bool isTwoAddrFold = false; >> unsigned NumOps = MI->getDesc().getNumOperands(); >> @@ -1730,12 +1730,33 @@ >> } >> >> >> -MachineInstr* X86InstrInfo::foldMemoryOperand(MachineInstr *MI, >> +MachineInstr* X86InstrInfo::foldMemoryOperand(MachineFunction &MF, >> + MachineInstr *MI, >> >> SmallVectorImpl &Ops, >> int FrameIndex) const { >> // Check switch flag >> if (NoFusing) return NULL; >> >> + const MachineFrameInfo *MFI = MF.getFrameInfo(); >> + unsigned Alignment = MFI->getObjectAlignment(FrameIndex); >> + // FIXME: Move alignment requirement into tables? >> + if (Alignment < 16) { >> + switch (MI->getOpcode()) { >> + default: break; >> + // Not always safe to fold movsd into these instructions since >> their load >> + // folding variants expects the address to be 16 byte aligned. >> + case X86::FsANDNPDrr: >> + case X86::FsANDNPSrr: >> + case X86::FsANDPDrr: >> + case X86::FsANDPSrr: >> + case X86::FsORPDrr: >> + case X86::FsORPSrr: >> + case X86::FsXORPDrr: >> + case X86::FsXORPSrr: >> + return NULL; >> + } >> + } >> + >> if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { >> unsigned NewOpc = 0; >> switch (MI->getOpcode()) { >> @@ -1756,12 +1777,39 @@ >> return foldMemoryOperand(MI, Ops[0], MOs); >> } >> >> -MachineInstr* X86InstrInfo::foldMemoryOperand(MachineInstr *MI, >> +MachineInstr* X86InstrInfo::foldMemoryOperand(MachineFunction &MF, >> + MachineInstr *MI, >> >> SmallVectorImpl &Ops, >> MachineInstr *LoadMI) >> const { >> // Check switch flag >> if (NoFusing) return NULL; >> >> + unsigned Alignment = 0; >> + for (unsigned i = 0, e = LoadMI->getNumMemOperands(); i != e; + >> +i) { >> + const MemOperand &MRO = LoadMI->getMemOperand(i); >> + unsigned Align = MRO.getAlignment(); >> + if (Align > Alignment) >> + Alignment = Align; >> + } >> + >> + // FIXME: Move alignment requirement into tables? >> + if (Alignment < 16) { >> + switch (MI->getOpcode()) { >> + default: break; >> + // Not always safe to fold movsd into these instructions since >> their load >> + // folding variants expects the address to be 16 byte aligned. >> + case X86::FsANDNPDrr: >> + case X86::FsANDNPSrr: >> + case X86::FsANDPDrr: >> + case X86::FsANDPSrr: >> + case X86::FsORPDrr: >> + case X86::FsORPSrr: >> + case X86::FsXORPDrr: >> + case X86::FsXORPSrr: >> + return NULL; >> + } >> + } >> + >> if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { >> unsigned NewOpc = 0; >> switch (MI->getOpcode()) { >> >> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=46893&r1=46892&r2=46893&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/Target/X86/X86InstrInfo.h (original) >> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.h Fri Feb 8 15:20:40 2008 >> @@ -324,14 +324,16 @@ >> /// folding and return true, otherwise it should return false. >> If it folds >> /// the instruction, it is likely that the MachineInstruction the >> iterator >> /// references has been changed. >> - virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, >> + virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, >> + MachineInstr* MI, >> SmallVectorImpl >> &Ops, >> int FrameIndex) const; >> >> /// foldMemoryOperand - Same as the previous version except it >> allows folding >> /// of any load and store from / to any address, not just from a >> specific >> /// stack slot. >> - virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, >> + virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, >> + MachineInstr* MI, >> SmallVectorImpl &Ops, >> MachineInstr* LoadMI) const; >> >> >> Added: llvm/trunk/test/CodeGen/X86/2008-02-08-LoadFoldingBug.ll >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-02-08-LoadFoldingBug.ll?rev=46893&view=auto >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/test/CodeGen/X86/2008-02-08-LoadFoldingBug.ll (added) >> +++ llvm/trunk/test/CodeGen/X86/2008-02-08-LoadFoldingBug.ll Fri >> Feb 8 15:20:40 2008 >> @@ -0,0 +1,99 @@ >> +; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep andpd | >> not grep esp >> + >> +declare double @llvm.sqrt.f64(double) nounwind readnone >> + >> +declare fastcc void @ApplyGivens(double**, double, double, i32, >> i32, i32, i32) nounwind >> + >> +declare double @fabs(double) >> + >> +define void @main_bb114_2E_outer_2E_i_bb3_2E_i27(double** >> %tmp12.sub.i.i, [51 x double*]* %tmp12.i.i.i, i32 %i.0.reg2mem. >> 0.ph.i, i32 %tmp11688.i, i32 %tmp19.i, i32 %tmp24.i, [51 x >> double*]* %tmp12.i.i) { >> +newFuncRoot: >> + br label %bb3.i27 >> + >> +bb111.i77.bb121.i_crit_edge.exitStub: ; preds = %bb111.i77 >> + ret void >> + >> +bb3.i27: ; preds = %bb111.i77.bb3.i27_crit_edge, >> %newFuncRoot >> + %indvar94.i = phi i32 [ 0, %newFuncRoot ], [ %tmp113.i76, >> %bb111.i77.bb3.i27_crit_edge ] ; [#uses=6] >> + %tmp6.i20 = getelementptr [51 x double*]* %tmp12.i.i, i32 >> 0, i32 %indvar94.i ; [#uses=1] >> + %tmp7.i21 = load double** %tmp6.i20, align 4 ; >> [#uses=2] >> + %tmp10.i = add i32 %indvar94.i, %i.0.reg2mem. >> 0.ph.i ; [#uses=5] >> + %tmp11.i22 = getelementptr double* %tmp7.i21, i32 >> %tmp10.i ; [#uses=1] >> + %tmp12.i23 = load double* %tmp11.i22, align 8 ; >> [#uses=4] >> + %tmp20.i24 = add i32 %tmp19.i, %indvar94.i ; >> [#uses=3] >> + %tmp21.i = getelementptr double* %tmp7.i21, i32 >> %tmp20.i24 ; [#uses=1] >> + %tmp22.i25 = load double* %tmp21.i, align 8 ; >> [#uses=3] >> + %tmp1.i.i26 = fcmp oeq double %tmp12.i23, 0.000000e >> +00 ; [#uses=1] >> + br i1 %tmp1.i.i26, label >> %bb3.i27.Givens.exit.i49_crit_edge, label %bb5.i.i31 >> + >> +bb5.i.i31: ; preds = %bb3.i27 >> + %tmp7.i.i28 = call double @fabs( double %tmp12.i23 ) >> nounwind ; [#uses=1] >> + %tmp9.i.i29 = call double @fabs( double %tmp22.i25 ) >> nounwind ; [#uses=1] >> + %tmp10.i.i30 = fcmp ogt double %tmp7.i.i28, >> %tmp9.i.i29 ; [#uses=1] >> + br i1 %tmp10.i.i30, label %bb13.i.i37, label %bb30.i.i43 >> + >> +bb13.i.i37: ; preds = %bb5.i.i31 >> + %tmp15.i.i32 = sub double -0.000000e+00, >> %tmp22.i25 ; [#uses=1] >> + %tmp17.i.i33 = fdiv double %tmp15.i.i32, >> %tmp12.i23 ; [#uses=3] >> + %tmp20.i4.i = mul double %tmp17.i.i33, >> %tmp17.i.i33 ; [#uses=1] >> + %tmp21.i.i34 = add double %tmp20.i4.i, 1.000000e >> +00 ; [#uses=1] >> + %tmp22.i.i35 = call double @llvm.sqrt.f64( double >> %tmp21.i.i34 ) nounwind ; [#uses=1] >> + %tmp23.i5.i = fdiv double 1.000000e+00, >> %tmp22.i.i35 ; [#uses=2] >> + %tmp28.i.i36 = mul double %tmp23.i5.i, >> %tmp17.i.i33 ; [#uses=1] >> + br label %Givens.exit.i49 >> + >> +bb30.i.i43: ; preds = %bb5.i.i31 >> + %tmp32.i.i38 = sub double -0.000000e+00, >> %tmp12.i23 ; [#uses=1] >> + %tmp34.i.i39 = fdiv double %tmp32.i.i38, >> %tmp22.i25 ; [#uses=3] >> + %tmp37.i6.i = mul double %tmp34.i.i39, >> %tmp34.i.i39 ; [#uses=1] >> + %tmp38.i.i40 = add double %tmp37.i6.i, 1.000000e >> +00 ; [#uses=1] >> + %tmp39.i7.i = call double @llvm.sqrt.f64( double >> %tmp38.i.i40 ) nounwind ; [#uses=1] >> + %tmp40.i.i41 = fdiv double 1.000000e+00, >> %tmp39.i7.i ; [#uses=2] >> + %tmp45.i.i42 = mul double %tmp40.i.i41, >> %tmp34.i.i39 ; [#uses=1] >> + br label %Givens.exit.i49 >> + >> +Givens.exit.i49: ; preds = >> %bb3.i27.Givens.exit.i49_crit_edge, %bb30.i.i43, %bb13.i.i37 >> + %s.0.i44 = phi double [ %tmp45.i.i42, %bb30.i.i43 ], >> [ %tmp23.i5.i, %bb13.i.i37 ], [ 0.000000e+00, >> %bb3.i27.Givens.exit.i49_crit_edge ] ; [#uses=2] >> + %c.0.i45 = phi double [ %tmp40.i.i41, %bb30.i.i43 ], >> [ %tmp28.i.i36, %bb13.i.i37 ], [ 1.000000e+00, >> %bb3.i27.Givens.exit.i49_crit_edge ] ; >> [#uses=2] >> + %tmp26.i46 = add i32 %tmp24.i, %indvar94.i ; >> [#uses=2] >> + %tmp27.i47 = icmp slt i32 %tmp26.i46, 51 ; >> [#uses=1] >> + %min.i48 = select i1 %tmp27.i47, i32 %tmp26.i46, i32 >> 50 ; [#uses=1] >> + call fastcc void @ApplyGivens( double** %tmp12.sub.i.i, >> double %s.0.i44, double %c.0.i45, i32 %tmp20.i24, i32 %tmp10.i, i32 >> %indvar94.i, i32 %min.i48 ) nounwind >> + br label %codeRepl >> + >> +codeRepl: ; preds = %Givens.exit.i49 >> + call void >> @main_bb114_2E_outer_2E_i_bb3_2E_i27_bb_2E_i48_2E_i( i32 %tmp10.i, >> i32 %tmp20.i24, double %s.0.i44, double %c.0.i45, [51 x double*]* >> %tmp12.i.i.i ) >> + br label %ApplyRGivens.exit49.i >> + >> +ApplyRGivens.exit49.i: ; preds = %codeRepl >> + %tmp10986.i = icmp sgt i32 %tmp11688.i, >> %tmp10.i ; [#uses=1] >> + br i1 %tmp10986.i, label >> %ApplyRGivens.exit49.i.bb52.i57_crit_edge, label >> %ApplyRGivens.exit49.i.bb111.i77_crit_edge >> + >> +codeRepl1: ; preds = >> %ApplyRGivens.exit49.i.bb52.i57_crit_edge >> + call void >> @main_bb114_2E_outer_2E_i_bb3_2E_i27_bb52_2E_i57( i32 %tmp10.i, >> double** %tmp12.sub.i.i, [51 x double*]* %tmp12.i.i.i, i32 %i. >> 0.reg2mem.0.ph.i, i32 %tmp11688.i, i32 %tmp19.i, i32 %tmp24.i, [51 >> x double*]* %tmp12.i.i ) >> + br label %bb105.i.bb111.i77_crit_edge >> + >> +bb111.i77: ; preds = %bb105.i.bb111.i77_crit_edge, >> %ApplyRGivens.exit49.i.bb111.i77_crit_edge >> + %tmp113.i76 = add i32 %indvar94.i, 1 ; >> [#uses=2] >> + %tmp118.i = icmp sgt i32 %tmp11688.i, >> %tmp113.i76 ; [#uses=1] >> + br i1 %tmp118.i, label %bb111.i77.bb3.i27_crit_edge, label >> %bb111.i77.bb121.i_crit_edge.exitStub >> + >> +bb3.i27.Givens.exit.i49_crit_edge: ; preds = %bb3.i27 >> + br label %Givens.exit.i49 >> + >> +ApplyRGivens.exit49.i.bb52.i57_crit_edge: ; preds = >> %ApplyRGivens.exit49.i >> + br label %codeRepl1 >> + >> +ApplyRGivens.exit49.i.bb111.i77_crit_edge: ; preds = >> %ApplyRGivens.exit49.i >> + br label %bb111.i77 >> + >> +bb105.i.bb111.i77_crit_edge: ; preds = %codeRepl1 >> + br label %bb111.i77 >> + >> +bb111.i77.bb3.i27_crit_edge: ; preds = %bb111.i77 >> + br label %bb3.i27 >> +} >> + >> +declare void >> @main_bb114_2E_outer_2E_i_bb3_2E_i27_bb_2E_i48_2E_i(i32, i32, >> double, double, [51 x double*]*) >> + >> +declare void @main_bb114_2E_outer_2E_i_bb3_2E_i27_bb52_2E_i57(i32, >> double**, [51 x double*]*, i32, i32, i32, i32, [51 x double*]*) >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From dpatel at apple.com Fri Feb 8 16:49:13 2008 From: dpatel at apple.com (Devang Patel) Date: Fri, 08 Feb 2008 22:49:13 -0000 Subject: [llvm-commits] [llvm] r46898 - in /llvm/trunk: lib/Transforms/Scalar/LoopIndexSplit.cpp test/Transforms/LoopIndexSplit/2008-02-08-Crash.ll Message-ID: <200802082249.m18MnDsX007748@zion.cs.uiuc.edu> Author: dpatel Date: Fri Feb 8 16:49:13 2008 New Revision: 46898 URL: http://llvm.org/viewvc/llvm-project?rev=46898&view=rev Log: Fix PR 1995. Added: llvm/trunk/test/Transforms/LoopIndexSplit/2008-02-08-Crash.ll Modified: llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp Modified: llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp?rev=46898&r1=46897&r2=46898&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp Fri Feb 8 16:49:13 2008 @@ -1392,6 +1392,11 @@ if (!Succ0->getSinglePredecessor() || !Succ1->getSinglePredecessor()) return false; + // If Exiting block includes loop variant instructions then this + // loop may not be split safely. + if (!safeExitingBlock(SD, ExitCondition->getParent())) + return false; + // After loop is cloned there are two loops. // // First loop, referred as ALoop, executes first part of loop's iteration @@ -1616,8 +1621,8 @@ /// - ExitBB's single predecessor was Latch /// - Latch's second successor was Header /// Now -/// - ExitBB's single predecessor was Header -/// - Latch's one and only successor was Header +/// - ExitBB's single predecessor is Header +/// - Latch's one and only successor is Header /// /// Update ExitBB PHINodes' to reflect this change. void LoopIndexSplit::updatePHINodes(BasicBlock *ExitBB, BasicBlock *Latch, @@ -1632,27 +1637,18 @@ Value *V = PN->getIncomingValueForBlock(Latch); if (PHINode *PHV = dyn_cast(V)) { - // PHV is in Latch. PHV has two uses, one use is in ExitBB PHINode - // (i.e. PN :)). - // The second use is in Header and it is new incoming value for PN. - PHINode *U1 = NULL; - PHINode *U2 = NULL; + // PHV is in Latch. PHV has one use is in ExitBB PHINode. And one use + // in Header which is new incoming value for PN. Value *NewV = NULL; for (Value::use_iterator UI = PHV->use_begin(), E = PHV->use_end(); - UI != E; ++UI) { - if (!U1) - U1 = cast(*UI); - else if (!U2) - U2 = cast(*UI); - else - assert ( 0 && "Unexpected third use of this PHINode"); - } - assert (U1 && U2 && "Unable to find two uses"); - - if (U1->getParent() == Header) - NewV = U1; - else - NewV = U2; + UI != E; ++UI) + if (PHINode *U = dyn_cast(*UI)) + if (U->getParent() == Header) { + NewV = U; + break; + } + + assert (NewV && "Unable to find new incoming value for exit block PHI"); PN->addIncoming(NewV, Header); } else if (Instruction *PHI = dyn_cast(V)) { Added: llvm/trunk/test/Transforms/LoopIndexSplit/2008-02-08-Crash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopIndexSplit/2008-02-08-Crash.ll?rev=46898&view=auto ============================================================================== --- llvm/trunk/test/Transforms/LoopIndexSplit/2008-02-08-Crash.ll (added) +++ llvm/trunk/test/Transforms/LoopIndexSplit/2008-02-08-Crash.ll Fri Feb 8 16:49:13 2008 @@ -0,0 +1,48 @@ +; RUN: llvm-as < %s | opt -loop-index-split -disable-output +; PR 1995 + +define void @add_blkdev_randomness(i32 %major) nounwind { +entry: + br label %bb + +bb: ; preds = %bb39, %entry + %A.0.reg2mem.0 = phi i32 [ undef, %entry ], [ %TEMP.0, %bb39 ] ; [#uses=1] + %D.0.reg2mem.0 = phi i32 [ undef, %entry ], [ %C.0.reg2mem.0, %bb39 ] ; [#uses=3] + %C.0.reg2mem.0 = phi i32 [ undef, %entry ], [ %tmp34, %bb39 ] ; [#uses=4] + %TEMP.1.reg2mem.0 = phi i32 [ undef, %entry ], [ %TEMP.0, %bb39 ] ; [#uses=1] + %i.0.reg2mem.0 = phi i32 [ 0, %entry ], [ %tmp38, %bb39 ] ; [#uses=3] + %B.0.reg2mem.0 = phi i32 [ undef, %entry ], [ %A.0.reg2mem.0, %bb39 ] ; [#uses=5] + %tmp1 = icmp slt i32 %i.0.reg2mem.0, 40 ; [#uses=1] + br i1 %tmp1, label %bb3, label %bb12 + +bb3: ; preds = %bb + %tmp6 = xor i32 %C.0.reg2mem.0, %D.0.reg2mem.0 ; [#uses=1] + %tmp8 = and i32 %B.0.reg2mem.0, %tmp6 ; [#uses=1] + %tmp10 = xor i32 %tmp8, %D.0.reg2mem.0 ; [#uses=1] + %tmp11 = add i32 %tmp10, 1518500249 ; [#uses=1] + br label %bb39 + +bb12: ; preds = %bb + %tmp14 = icmp slt i32 %i.0.reg2mem.0, 60 ; [#uses=1] + br i1 %tmp14, label %bb17, label %bb39 + +bb17: ; preds = %bb12 + %tmp20 = and i32 %B.0.reg2mem.0, %C.0.reg2mem.0 ; [#uses=1] + %tmp23 = xor i32 %B.0.reg2mem.0, %C.0.reg2mem.0 ; [#uses=1] + %tmp25 = and i32 %tmp23, %D.0.reg2mem.0 ; [#uses=1] + %tmp26 = add i32 %tmp20, -1894007588 ; [#uses=1] + %tmp27 = add i32 %tmp26, %tmp25 ; [#uses=1] + br label %bb39 + +bb39: ; preds = %bb12, %bb3, %bb17 + %TEMP.0 = phi i32 [ %tmp27, %bb17 ], [ %tmp11, %bb3 ], [ %TEMP.1.reg2mem.0, %bb12 ] ; [#uses=2] + %tmp31 = lshr i32 %B.0.reg2mem.0, 2 ; [#uses=1] + %tmp33 = shl i32 %B.0.reg2mem.0, 30 ; [#uses=1] + %tmp34 = or i32 %tmp31, %tmp33 ; [#uses=1] + %tmp38 = add i32 %i.0.reg2mem.0, 1 ; [#uses=2] + %tmp41 = icmp slt i32 %tmp38, 80 ; [#uses=1] + br i1 %tmp41, label %bb, label %return + +return: ; preds = %bb39 + ret void +} \ No newline at end of file From gohman at apple.com Fri Feb 8 16:59:30 2008 From: gohman at apple.com (Dan Gohman) Date: Fri, 08 Feb 2008 22:59:30 -0000 Subject: [llvm-commits] [llvm] r46899 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAG.h include/llvm/CodeGen/SelectionDAGNodes.h lib/CodeGen/SelectionDAG/SelectionDAG.cpp Message-ID: <200802082259.m18MxVbt008033@zion.cs.uiuc.edu> Author: djg Date: Fri Feb 8 16:59:30 2008 New Revision: 46899 URL: http://llvm.org/viewvc/llvm-project?rev=46899&view=rev Log: Change ConstantSDNode to store an APInt instead of a uint64_t, and begin adding some methods to use it this way. Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=46899&r1=46898&r2=46899&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Fri Feb 8 16:59:30 2008 @@ -172,10 +172,14 @@ // SDOperand getString(const std::string &Val); SDOperand getConstant(uint64_t Val, MVT::ValueType VT, bool isTarget = false); + SDOperand getConstant(const APInt &Val, MVT::ValueType VT, bool isTarget = false); SDOperand getIntPtrConstant(uint64_t Val, bool isTarget = false); SDOperand getTargetConstant(uint64_t Val, MVT::ValueType VT) { return getConstant(Val, VT, true); } + SDOperand getTargetConstant(const APInt &Val, MVT::ValueType VT) { + return getConstant(Val, VT, true); + } SDOperand getConstantFP(double Val, MVT::ValueType VT, bool isTarget = false); SDOperand getConstantFP(const APFloat& Val, MVT::ValueType VT, bool isTarget = false); Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=46899&r1=46898&r2=46899&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Fri Feb 8 16:59:30 2008 @@ -24,6 +24,7 @@ #include "llvm/ADT/GraphTraits.h" #include "llvm/ADT/iterator" #include "llvm/ADT/APFloat.h" +#include "llvm/ADT/APInt.h" #include "llvm/CodeGen/ValueTypes.h" #include "llvm/CodeGen/MemOperand.h" #include "llvm/Support/DataTypes.h" @@ -1173,21 +1174,22 @@ }; class ConstantSDNode : public SDNode { - uint64_t Value; + APInt Value; virtual void ANCHOR(); // Out-of-line virtual method to give class a home. protected: friend class SelectionDAG; - ConstantSDNode(bool isTarget, uint64_t val, MVT::ValueType VT) + ConstantSDNode(bool isTarget, const APInt &val, MVT::ValueType VT) : SDNode(isTarget ? ISD::TargetConstant : ISD::Constant, getSDVTList(VT)), Value(val) { } public: - uint64_t getValue() const { return Value; } + const APInt &getAPIntValue() const { return Value; } + uint64_t getValue() const { return Value.getZExtValue(); } int64_t getSignExtended() const { unsigned Bits = MVT::getSizeInBits(getValueType(0)); - return ((int64_t)Value << (64-Bits)) >> (64-Bits); + return ((int64_t)Value.getZExtValue() << (64-Bits)) >> (64-Bits); } bool isNullValue() const { return Value == 0; } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=46899&r1=46898&r2=46899&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Fri Feb 8 16:59:30 2008 @@ -706,18 +706,25 @@ } SDOperand SelectionDAG::getConstant(uint64_t Val, MVT::ValueType VT, bool isT) { + MVT::ValueType EltVT = + MVT::isVector(VT) ? MVT::getVectorElementType(VT) : VT; + + return getConstant(APInt(MVT::getSizeInBits(EltVT), Val), VT, isT); +} + +SDOperand SelectionDAG::getConstant(const APInt &Val, MVT::ValueType VT, bool isT) { assert(MVT::isInteger(VT) && "Cannot create FP integer constant!"); MVT::ValueType EltVT = MVT::isVector(VT) ? MVT::getVectorElementType(VT) : VT; - // Mask out any bits that are not valid for this constant. - Val &= MVT::getIntVTBitMask(EltVT); + assert(Val.getBitWidth() == MVT::getSizeInBits(EltVT) && + "APInt size does not match type size!"); unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant; FoldingSetNodeID ID; AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0); - ID.AddInteger(Val); + ID.AddAPInt(Val); void *IP = 0; SDNode *N = NULL; if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) From sabre at nondot.org Fri Feb 8 19:06:02 2008 From: sabre at nondot.org (Chris Lattner) Date: Sat, 09 Feb 2008 01:06:02 -0000 Subject: [llvm-commits] [llvm] r46900 - /llvm/trunk/lib/VMCore/Verifier.cpp Message-ID: <200802090106.m19162Bg011622@zion.cs.uiuc.edu> Author: lattner Date: Fri Feb 8 19:06:01 2008 New Revision: 46900 URL: http://llvm.org/viewvc/llvm-project?rev=46900&view=rev Log: check that terminators only occur at the end of a block. This catches the common problem of putting two terminators in the same block. I can't write a testcase for this because the .ll parser rejects this before the verifier can, but this can occur when generating IR. Modified: llvm/trunk/lib/VMCore/Verifier.cpp Modified: llvm/trunk/lib/VMCore/Verifier.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Verifier.cpp?rev=46900&r1=46899&r2=46900&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Verifier.cpp (original) +++ llvm/trunk/lib/VMCore/Verifier.cpp Fri Feb 8 19:06:01 2008 @@ -1051,6 +1051,11 @@ !DT->dominates(&BB->getParent()->getEntryBlock(), BB), "Only PHI nodes may reference their own value!", &I); } + + // Verify that if this is a terminator that it is at the end of the block. + if (isa(I)) + Assert1(BB->getTerminator() == &I, "Terminator not at end of block!", &I); + // Check that void typed values don't have names Assert1(I.getType() != Type::VoidTy || !I.hasName(), From natebegeman at mac.com Fri Feb 8 19:37:05 2008 From: natebegeman at mac.com (Nate Begeman) Date: Sat, 09 Feb 2008 01:37:05 -0000 Subject: [llvm-commits] [llvm] r46901 - in /llvm/trunk: lib/Target/TargetSelectionDAG.td utils/TableGen/CodeGenDAGPatterns.cpp utils/TableGen/CodeGenDAGPatterns.h Message-ID: <200802090137.m191b5a6012404@zion.cs.uiuc.edu> Author: sampo Date: Fri Feb 8 19:37:05 2008 New Revision: 46901 URL: http://llvm.org/viewvc/llvm-project?rev=46901&view=rev Log: Tablegen support for insert & extract element matching Modified: llvm/trunk/lib/Target/TargetSelectionDAG.td llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h Modified: llvm/trunk/lib/Target/TargetSelectionDAG.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetSelectionDAG.td?rev=46901&r1=46900&r2=46901&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetSelectionDAG.td (original) +++ llvm/trunk/lib/Target/TargetSelectionDAG.td Fri Feb 8 19:37:05 2008 @@ -60,6 +60,13 @@ int OtherOpNum = OtherOp; } +/// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same +/// type as the element type of OtherOp, which is a vector type. +class SDTCisEltOfVec + : SDTypeConstraint { + int OtherOpNum = OtherOp; +} + //===----------------------------------------------------------------------===// // Selection DAG Type Profile definitions. // @@ -171,6 +178,12 @@ def SDTVecShuffle : SDTypeProfile<1, 3, [ SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisIntVectorOfSameSize<3, 0> ]>; +def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract + SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2> +]>; +def SDTVecInsert : SDTypeProfile<1, 2, [ // vector insert + SDTCisEltOfVec<1, 0>, SDTCisPtrTy<2> +]>; class SDCallSeqStart constraints> : SDTypeProfile<0, 1, constraints>; @@ -283,6 +296,9 @@ def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>; def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>; def bitconvert : SDNode<"ISD::BIT_CONVERT", SDTUnaryOp>; +def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>; +def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>; + def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>; def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>; Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp?rev=46901&r1=46900&r2=46901&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp (original) +++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp Fri Feb 8 19:37:05 2008 @@ -112,6 +112,10 @@ ConstraintType = SDTCisIntVectorOfSameSize; x.SDTCisIntVectorOfSameSize_Info.OtherOperandNum = R->getValueAsInt("OtherOpNum"); + } else if (R->isSubClassOf("SDTCisEltOfVec")) { + ConstraintType = SDTCisEltOfVec; + x.SDTCisEltOfVec_Info.OtherOperandNum = + R->getValueAsInt("OtherOpNum"); } else { cerr << "Unrecognized SDTypeConstraint '" << R->getName() << "'!\n"; exit(1); @@ -288,6 +292,19 @@ } return false; } + case SDTCisEltOfVec: { + TreePatternNode *OtherOperand = + getOperandNum(x.SDTCisIntVectorOfSameSize_Info.OtherOperandNum, + N, NumResults); + if (OtherOperand->hasTypeSet()) { + if (!MVT::isVector(OtherOperand->getTypeNum(0))) + TP.error(N->getOperator()->getName() + " VT operand must be a vector!"); + MVT::ValueType IVT = OtherOperand->getTypeNum(0); + IVT = MVT::getVectorElementType(IVT); + return NodeToApply->UpdateNodeType(IVT, TP); + } + return false; + } } return false; } Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h?rev=46901&r1=46900&r2=46901&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h (original) +++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h Fri Feb 8 19:37:05 2008 @@ -56,7 +56,8 @@ unsigned OperandNo; // The operand # this constraint applies to. enum { SDTCisVT, SDTCisPtrTy, SDTCisInt, SDTCisFP, SDTCisSameAs, - SDTCisVTSmallerThanOp, SDTCisOpSmallerThanOp, SDTCisIntVectorOfSameSize + SDTCisVTSmallerThanOp, SDTCisOpSmallerThanOp, SDTCisIntVectorOfSameSize, + SDTCisEltOfVec } ConstraintType; union { // The discriminated union. @@ -75,6 +76,9 @@ struct { unsigned OtherOperandNum; } SDTCisIntVectorOfSameSize_Info; + struct { + unsigned OtherOperandNum; + } SDTCisEltOfVec_Info; } x; /// ApplyTypeConstraint - Given a node in a pattern, apply this type From natebegeman at mac.com Fri Feb 8 19:38:08 2008 From: natebegeman at mac.com (Nate Begeman) Date: Sat, 09 Feb 2008 01:38:08 -0000 Subject: [llvm-commits] [llvm] r46902 - /llvm/trunk/lib/Target/X86/X86InstrSSE.td Message-ID: <200802090138.m191c8L0012440@zion.cs.uiuc.edu> Author: sampo Date: Fri Feb 8 19:38:08 2008 New Revision: 46902 URL: http://llvm.org/viewvc/llvm-project?rev=46902&view=rev Log: Skeleton of insert and extract matching, more to come Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=46902&r1=46901&r2=46902&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Fri Feb 8 19:38:08 2008 @@ -3192,11 +3192,45 @@ int_x86_sse41_pmaxud, 1>; defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", int_x86_sse41_pmaxuw, 1>; -defm PMULLD : SS41I_binop_rm_int<0x40, "pmulld", - int_x86_sse41_pmulld, 1>; defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq, 1>; + +/// SS41I_binop_rm_int - Simple SSE 4.1 binary operator +let isTwoAddress = 1 in { + multiclass SS41I_binop_patint opc, string OpcodeStr, SDNode OpNode, + Intrinsic IntId128, bit Commutable = 0> { + def rr : SS48I, OpSize { + let isCommutable = Commutable; + } + def rr_int : SS48I, + OpSize { + let isCommutable = Commutable; + } + def rm : SS48I, OpSize; + def rm_int : SS48I, + OpSize; + } +} +defm PMULLD : SS41I_binop_patint<0x40, "pmulld", mul, + int_x86_sse41_pmulld, 1>; + + /// SS41I_binop_rmi_int - SSE 4.1 binary operator with immediate let isTwoAddress = 1 in { multiclass SS41I_binop_rmi_int opc, string OpcodeStr, @@ -3233,3 +3267,29 @@ int_x86_sse41_dppd, 1>; defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw, 0>; + +/// SS41I_binop_ext32 - SSE 4.1 binary operator with immediate +multiclass SS41I_binop_ext32 opc, string OpcodeStr> { + def rri128 : SS4AI, + OpSize; +} + +defm PEXTRD : SS41I_binop_ext32<0x16, "pextrd">; + +/// SS41I_binop_extf32 - SSE 4.1 binary operator with immediate +multiclass SS41I_binop_extf32 opc, string OpcodeStr> { + def rri128 : SS4AI, + OpSize; +} + +defm EXTRACTPS : SS41I_binop_extf32<0x17, "extractps">; From kremenek at apple.com Fri Feb 8 20:07:33 2008 From: kremenek at apple.com (Ted Kremenek) Date: Fri, 8 Feb 2008 18:07:33 -0800 Subject: [llvm-commits] [llvm] r46833 - in /llvm/trunk: include/llvm/ADT/FoldingSet.h lib/Support/FoldingSet.cpp In-Reply-To: <200802062309.m16N9GRB004607@zion.cs.uiuc.edu> References: <200802062309.m16N9GRB004607@zion.cs.uiuc.edu> Message-ID: I'm wondering if we need to keep on adding specialized "Add" methods to FoldingSet. For example, APInt already has a "Profile" method for adding its profile to a FoldingSetNodeID, and APFloat could easily have a Profile method added to it. Now that FoldingSet uses FoldingSetTrait<> to profile its contained elements, perhaps we can just include a single "Add" member template to FoldingSetNodeID that uses the FoldingSetTrait<> to profile a generic item. When people want to include profiling support for a datatype, they need only specialize FoldingSetTrait<> (if the datatype doesn't already have a Profile method). This avoids bloat in the API for FoldingSetNodeID. If anyone else thinks this is a good idea, I'll go ahead and make the change. On Feb 6, 2008, at 3:09 PM, Dan Gohman wrote: > Author: djg > Date: Wed Feb 6 17:09:15 2008 > New Revision: 46833 > > URL: http://llvm.org/viewvc/llvm-project?rev=46833&view=rev > Log: > Add support to FoldingSet for hashing APInt objects. > > Modified: > llvm/trunk/include/llvm/ADT/FoldingSet.h > llvm/trunk/lib/Support/FoldingSet.cpp > > Modified: llvm/trunk/include/llvm/ADT/FoldingSet.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/FoldingSet.h?rev=46833&r1=46832&r2=46833&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/include/llvm/ADT/FoldingSet.h (original) > +++ llvm/trunk/include/llvm/ADT/FoldingSet.h Wed Feb 6 17:09:15 2008 > @@ -22,6 +22,7 @@ > > namespace llvm { > class APFloat; > + class APInt; > > /// This folding set used for two purposes: > /// 1. Given information about a node we want to create, look up > the unique > @@ -206,6 +207,7 @@ > void AddFloat(float F); > void AddDouble(double D); > void AddAPFloat(const APFloat& apf); > + void AddAPInt(const APInt& api); > void AddString(const std::string &String); > > /// clear - Clear the accumulated profile, allowing this > FoldingSetNodeID > > Modified: llvm/trunk/lib/Support/FoldingSet.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/FoldingSet.cpp?rev=46833&r1=46832&r2=46833&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Support/FoldingSet.cpp (original) > +++ llvm/trunk/lib/Support/FoldingSet.cpp Wed Feb 6 17:09:15 2008 > @@ -16,6 +16,7 @@ > > #include "llvm/ADT/FoldingSet.h" > #include "llvm/ADT/APFloat.h" > +#include "llvm/ADT/APInt.h" > #include "llvm/Support/MathExtras.h" > #include > using namespace llvm; > @@ -59,6 +60,9 @@ > } > void FoldingSetNodeID::AddAPFloat(const APFloat& apf) { > APInt api = apf.convertToAPInt(); > + AddAPInt(api); > +} > +void FoldingSetNodeID::AddAPInt(const APInt& api) { > const uint64_t *p = api.getRawData(); > for (unsigned i=0; i AddInteger(*p++); > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From clattner at apple.com Fri Feb 8 20:33:25 2008 From: clattner at apple.com (Chris Lattner) Date: Fri, 8 Feb 2008 18:33:25 -0800 Subject: [llvm-commits] [llvm] r46833 - in /llvm/trunk: include/llvm/ADT/FoldingSet.h lib/Support/FoldingSet.cpp In-Reply-To: References: <200802062309.m16N9GRB004607@zion.cs.uiuc.edu> Message-ID: <10CA1E32-3111-4721-85E3-93EB882F397E@apple.com> On Feb 8, 2008, at 6:07 PM, Ted Kremenek wrote: > I'm wondering if we need to keep on adding specialized "Add" methods > to FoldingSet. > > For example, APInt already has a "Profile" method for adding its > profile to a FoldingSetNodeID, and APFloat could easily have a Profile > method added to it. Now that FoldingSet uses FoldingSetTrait<> to > profile its contained elements, perhaps we can just include a single > "Add" member template to FoldingSetNodeID that uses the > FoldingSetTrait<> to profile a generic item. When people want to > include profiling support for a datatype, they need only specialize > FoldingSetTrait<> (if the datatype doesn't already have a Profile > method). This avoids bloat in the API for FoldingSetNodeID. If > anyone else thinks this is a good idea, I'll go ahead and make the > change. That sounds great to me. I'd rather have various classes know about foldingset than having foldingset know about all classes, -Chris From evan.cheng at apple.com Sat Feb 9 02:36:29 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Sat, 09 Feb 2008 08:36:29 -0000 Subject: [llvm-commits] [llvm] r46903 - /llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Message-ID: <200802090836.m198aT4Z027386@zion.cs.uiuc.edu> Author: evancheng Date: Sat Feb 9 02:36:28 2008 New Revision: 46903 URL: http://llvm.org/viewvc/llvm-project?rev=46903&view=rev Log: Remove unused hidden option. Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=46903&r1=46902&r2=46903&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original) +++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Sat Feb 9 02:36:28 2008 @@ -51,11 +51,6 @@ cl::desc("Use new coalescer heuristic"), cl::init(false)); - static cl::opt - ReMatSpillWeight("tweak-remat-spill-weight", - cl::desc("Tweak spill weight of re-materializable intervals"), - cl::init(true)); - RegisterPass X("simple-register-coalescing", "Simple Register Coalescing"); @@ -1496,7 +1491,7 @@ LI.weight = HUGE_VALF; else { bool isLoad = false; - if (ReMatSpillWeight && li_->isReMaterializable(LI, isLoad)) { + if (li_->isReMaterializable(LI, isLoad)) { // If all of the definitions of the interval are re-materializable, // it is a preferred candidate for spilling. If non of the defs are // loads, then it's potentially very cheap to re-materialize. From wmatyjewicz at fastmail.fm Sat Feb 9 05:30:21 2008 From: wmatyjewicz at fastmail.fm (Wojciech Matyjewicz) Date: Sat, 09 Feb 2008 12:30:21 +0100 Subject: [llvm-commits] [llvm-gcc-4.2] r46860 - /llvm-gcc-4.2/trunk/gcc/gcc.c In-Reply-To: <9756BA26-D0C7-42C2-A552-AC4D50A86FF0@apple.com> References: <200802071931.m17JVBVm016313@zion.cs.uiuc.edu> <47AC2069.2040701@fastmail.fm> <9756BA26-D0C7-42C2-A552-AC4D50A86FF0@apple.com> Message-ID: <47AD8ECD.5020901@fastmail.fm> Hi Devang, > Most likely. Please try again using following patch > http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20080204/058023.html After updating the tree, both -emit-llvm and --emit-llvm options don't work properly: llvm-gcc generates native assembly or object files whether they are given or not. This in on Linux/x86. // null.c is an empty file $ llvm-gcc -emit-llvm -S null.c -o - .ident "GCC: (GNU) 4.2.1 (Based on Apple Inc. build 5546) (LLVM build)" -Wojtek From baldrick at free.fr Fri Feb 8 12:03:13 2008 From: baldrick at free.fr (Duncan Sands) Date: Fri, 8 Feb 2008 19:03:13 +0100 Subject: [llvm-commits] [llvm-gcc-4.2] r46726 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp In-Reply-To: References: <200802042324.m14NOiBg021071@zion.cs.uiuc.edu> <501FF9A4-3632-4D09-B38B-E0CB6A06028C@apple.com> Message-ID: <200802081903.13331.baldrick@free.fr> Hi Dale, > > It is possible that I'm not solving the real problem here. > > > > struct { > > char a; > > char b; > > int c:8; > > int d:20; > > } S; > > > > When this struct is packed and S is aligned at 4 byte, what alignment > > should be specified on load instruction to load 'd' ? > > The struct is only 6 bytes long in this case (try it with gcc), so > representing d with a 32-bit load is probably not a good idea; there > are machines where such misaligned loads are valid (e.g. x86) and a 32- > bit load will read off the end of the structure. right, potentially causing a page fault or other badness. > In general I prefer the IR to be target-independent where possible, > but I don't see a good alternative to having the FE break up the load > of d into 3 pieces here (or perhaps char + short). Having the IR > include a load off the end of the object, that wasn't there in the > source, and requiring the BE to figure this out seems very wrong. So > to answer your question, there needs to be more than one load. I can't help feeling that a bitfield load or store should touch the minimum amount of bytes possible: only those that contain some part of the bitfield. In some situations touching other bytes could be fatal, for example if the type is overlaid on some memory mapped io region, or multiple threads are accessing different parts of the type simulteneously. In the above example you could try accessing d using 4 bytes starting from b, but this would give wrong results if some other thread was accessing b at the same time. I'm fairly sure that Ada has quite strict requirements about this, and I have the vague idea (I don't know where I got it from) that there is talk of requiring a minimum disturbance rule of some kind in C. > However, if we modify the packed struct thus (it's now 7 bytes) > > > struct { > > char a; > > char b; > > int c:8; > > int d:32; > > } S; > > > referring to d with misaligned 32-bit loads and stores is sensible. > That's valid code on x86, and representing it as byte operations and > expecting the BE to stick them back together is a lot of trouble for > no benefit. Of course, on many other targets, that load must be > broken into pieces. That could be done in either end, but since > we've got to break up 20-bit fields in the FE anyway, I guess we might > as well do so for 32-bit fields when the target requires that. I > could probably be convinced to do this one in the BE though. Doesn't the BE already do this? It has some code at least for turning unaligned loads into multiple aligned loads. Best wishes, Duncan. From wmatyjewicz at fastmail.fm Sat Feb 9 11:26:10 2008 From: wmatyjewicz at fastmail.fm (Wojciech Matyjewicz) Date: Sat, 09 Feb 2008 18:26:10 +0100 Subject: [llvm-commits] Fix for PR1798 (ScalarEvolution) In-Reply-To: <478D2769.8060503@fastmail.fm> References: <478D2769.8060503@fastmail.fm> Message-ID: <47ADE232.5070407@fastmail.fm> Hi, I've attached an updated version of the patch. It is ready for using support for APInts in the code generator, but currently it doesn't rely on this feature. I've added a hack that rounds up the computation bitwidth to power of 2 (only these bitwidths are allowed: 1, 2, ..., 64). Hack is visible and very easy to remove in future. Is it safe to commit it now? -Wojtek -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: PR1798-fix.patch Url: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20080209/3d511546/attachment.pl From wmatyjewicz at fastmail.fm Sat Feb 9 12:06:58 2008 From: wmatyjewicz at fastmail.fm (Wojciech Matyjewicz) Date: Sat, 09 Feb 2008 18:06:58 -0000 Subject: [llvm-commits] [llvm] r46907 - /llvm/trunk/include/llvm/Analysis/LoopInfo.h Message-ID: <200802091806.m19I6xoM017167@zion.cs.uiuc.edu> Author: wmat Date: Sat Feb 9 12:06:58 2008 New Revision: 46907 URL: http://llvm.org/viewvc/llvm-project?rev=46907&view=rev Log: Add a check if the initial value of the induction variable is 0 (the method comment says it should be). Modified: llvm/trunk/include/llvm/Analysis/LoopInfo.h Modified: llvm/trunk/include/llvm/Analysis/LoopInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/LoopInfo.h?rev=46907&r1=46906&r2=46907&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/LoopInfo.h (original) +++ llvm/trunk/include/llvm/Analysis/LoopInfo.h Sat Feb 9 12:06:58 2008 @@ -360,12 +360,16 @@ // Loop over all of the PHI nodes, looking for a canonical indvar. for (typename BlockT::iterator I = H->begin(); isa(I); ++I) { PHINode *PN = cast(I); - if (Instruction *Inc = - dyn_cast(PN->getIncomingValueForBlock(Backedge))) - if (Inc->getOpcode() == Instruction::Add && Inc->getOperand(0) == PN) - if (ConstantInt *CI = dyn_cast(Inc->getOperand(1))) - if (CI->equalsInt(1)) - return PN; + if (ConstantInt *CI = + dyn_cast(PN->getIncomingValueForBlock(Incoming))) + if (CI->isNullValue()) + if (Instruction *Inc = + dyn_cast(PN->getIncomingValueForBlock(Backedge))) + if (Inc->getOpcode() == Instruction::Add && + Inc->getOperand(0) == PN) + if (ConstantInt *CI = dyn_cast(Inc->getOperand(1))) + if (CI->equalsInt(1)) + return PN; } return 0; } From wmatyjewicz at fastmail.fm Sat Feb 9 12:30:13 2008 From: wmatyjewicz at fastmail.fm (Wojciech Matyjewicz) Date: Sat, 09 Feb 2008 18:30:13 -0000 Subject: [llvm-commits] [llvm] r46908 - /llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp Message-ID: <200802091830.m19IUDiV017847@zion.cs.uiuc.edu> Author: wmat Date: Sat Feb 9 12:30:13 2008 New Revision: 46908 URL: http://llvm.org/viewvc/llvm-project?rev=46908&view=rev Log: We should check that existing cast operation has the appropriate opcode before we reuse it. Modified: llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp Modified: llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp?rev=46908&r1=46907&r2=46908&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp (original) +++ llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp Sat Feb 9 12:30:13 2008 @@ -30,36 +30,38 @@ for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI) { if ((*UI)->getType() == Ty) - if (CastInst *CI = dyn_cast(cast(*UI))) { - // If the cast isn't the first instruction of the function, move it. - if (BasicBlock::iterator(CI) != - A->getParent()->getEntryBlock().begin()) { - CI->moveBefore(A->getParent()->getEntryBlock().begin()); + if (CastInst *CI = dyn_cast(cast(*UI))) + if (CI->getOpcode() == opcode) { + // If the cast isn't the first instruction of the function, move it. + if (BasicBlock::iterator(CI) != + A->getParent()->getEntryBlock().begin()) { + CI->moveBefore(A->getParent()->getEntryBlock().begin()); + } + return CI; } - return CI; - } } return CastInst::create(opcode, V, Ty, V->getName(), A->getParent()->getEntryBlock().begin()); } - + Instruction *I = cast(V); - + // Check to see if there is already a cast. If there is, use it. for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI) { if ((*UI)->getType() == Ty) - if (CastInst *CI = dyn_cast(cast(*UI))) { - BasicBlock::iterator It = I; ++It; - if (isa(I)) - It = cast(I)->getNormalDest()->begin(); - while (isa(It)) ++It; - if (It != BasicBlock::iterator(CI)) { - // Splice the cast immediately after the operand in question. - CI->moveBefore(It); + if (CastInst *CI = dyn_cast(cast(*UI))) + if (CI->getOpcode() == opcode) { + BasicBlock::iterator It = I; ++It; + if (isa(I)) + It = cast(I)->getNormalDest()->begin(); + while (isa(It)) ++It; + if (It != BasicBlock::iterator(CI)) { + // Splice the cast immediately after the operand in question. + CI->moveBefore(It); + } + return CI; } - return CI; - } } BasicBlock::iterator IP = I; ++IP; if (InvokeInst *II = dyn_cast(I)) From clattner at apple.com Sat Feb 9 12:38:32 2008 From: clattner at apple.com (Chris Lattner) Date: Sat, 9 Feb 2008 10:38:32 -0800 Subject: [llvm-commits] [llvm] r46907 - /llvm/trunk/include/llvm/Analysis/LoopInfo.h In-Reply-To: <200802091806.m19I6xoM017167@zion.cs.uiuc.edu> References: <200802091806.m19I6xoM017167@zion.cs.uiuc.edu> Message-ID: On Feb 9, 2008, at 10:06 AM, Wojciech Matyjewicz wrote: > Author: wmat > Date: Sat Feb 9 12:06:58 2008 > New Revision: 46907 > > URL: http://llvm.org/viewvc/llvm-project?rev=46907&view=rev > Log: > Add a check if the initial value of the induction variable is 0 (the > method comment says it should be). Nice. This method is pretty large, and it is specific to the LLVM IR loop info (not machine loop info etc). Would it be possible to make it an out of line method in LoopInfo that isn't in the template? -Chris > > Modified: > llvm/trunk/include/llvm/Analysis/LoopInfo.h > > Modified: llvm/trunk/include/llvm/Analysis/LoopInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/LoopInfo.h?rev=46907&r1=46906&r2=46907&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/include/llvm/Analysis/LoopInfo.h (original) > +++ llvm/trunk/include/llvm/Analysis/LoopInfo.h Sat Feb 9 12:06:58 > 2008 > @@ -360,12 +360,16 @@ > // Loop over all of the PHI nodes, looking for a canonical indvar. > for (typename BlockT::iterator I = H->begin(); isa(I); + > +I) { > PHINode *PN = cast(I); > - if (Instruction *Inc = > - dyn_cast(PN- > >getIncomingValueForBlock(Backedge))) > - if (Inc->getOpcode() == Instruction::Add && Inc- > >getOperand(0) == PN) > - if (ConstantInt *CI = dyn_cast(Inc- > >getOperand(1))) > - if (CI->equalsInt(1)) > - return PN; > + if (ConstantInt *CI = > + dyn_cast(PN- > >getIncomingValueForBlock(Incoming))) > + if (CI->isNullValue()) > + if (Instruction *Inc = > + dyn_cast(PN- > >getIncomingValueForBlock(Backedge))) > + if (Inc->getOpcode() == Instruction::Add && > + Inc->getOperand(0) == PN) > + if (ConstantInt *CI = dyn_cast(Inc- > >getOperand(1))) > + if (CI->equalsInt(1)) > + return PN; > } > return 0; > } > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From dalej at apple.com Sat Feb 9 13:04:26 2008 From: dalej at apple.com (Dale Johannesen) Date: Sat, 09 Feb 2008 19:04:26 -0000 Subject: [llvm-commits] [llvm] r46909 - /llvm/trunk/test/CodeGen/X86/byval7.ll Message-ID: <200802091904.m19J4QME018802@zion.cs.uiuc.edu> Author: johannes Date: Sat Feb 9 13:04:25 2008 New Revision: 46909 URL: http://llvm.org/viewvc/llvm-project?rev=46909&view=rev Log: Alignment of struct containing vectors depends on whether SSE is present, on Darwin anyway. Make it explicit. Modified: llvm/trunk/test/CodeGen/X86/byval7.ll Modified: llvm/trunk/test/CodeGen/X86/byval7.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/byval7.ll?rev=46909&r1=46908&r2=46909&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/byval7.ll (original) +++ llvm/trunk/test/CodeGen/X86/byval7.ll Sat Feb 9 13:04:25 2008 @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=x86 | grep add | grep 16 +; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah | grep add | grep 16 %struct.S = type { <2 x i64> } From dpatel at apple.com Sat Feb 9 14:20:50 2008 From: dpatel at apple.com (Devang Patel) Date: Sat, 9 Feb 2008 12:20:50 -0800 Subject: [llvm-commits] [llvm-gcc-4.2] r46860 - /llvm-gcc-4.2/trunk/gcc/gcc.c In-Reply-To: <47AD8ECD.5020901@fastmail.fm> References: <200802071931.m17JVBVm016313@zion.cs.uiuc.edu> <47AC2069.2040701@fastmail.fm> <9756BA26-D0C7-42C2-A552-AC4D50A86FF0@apple.com> <47AD8ECD.5020901@fastmail.fm> Message-ID: <037F900D-91CF-45B4-9407-2168834E97F0@apple.com> On Feb 9, 2008, at 3:30 AM, Wojciech Matyjewicz wrote: > Hi Devang, > >> Most likely. Please try again using following patch >> http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20080204/058023.html > > After updating the tree, both -emit-llvm and --emit-llvm options don't > work properly: llvm-gcc generates native assembly or object files > whether they are given or not. This in on Linux/x86. sigh.. Feel free to revert my patches. - Devang > > > // null.c is an empty file > $ llvm-gcc -emit-llvm -S null.c -o - > .ident "GCC: (GNU) 4.2.1 (Based on Apple Inc. build 5546) > (LLVM > build)" > > -Wojtek > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From dpatel at apple.com Sat Feb 9 14:31:33 2008 From: dpatel at apple.com (Devang Patel) Date: Sat, 9 Feb 2008 12:31:33 -0800 Subject: [llvm-commits] [llvm-gcc-4.2] r46726 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp In-Reply-To: <200802081903.13331.baldrick@free.fr> References: <200802042324.m14NOiBg021071@zion.cs.uiuc.edu> <501FF9A4-3632-4D09-B38B-E0CB6A06028C@apple.com> <200802081903.13331.baldrick@free.fr> Message-ID: <760C956E-1E4A-4E7B-9A51-8A96AE4CA3AA@apple.com> On Feb 8, 2008, at 10:03 AM, Duncan Sands wrote: > I can't help feeling that a bitfield load or store should touch the > minimum amount of bytes possible: only those that contain some part > of the bitfield. In some situations touching other bytes could be > fatal, for example if the type is overlaid on some memory mapped io > region, or multiple threads are accessing different parts of the > type simulteneously. I do not think this is required as part of current C ABI. This is responsibility of programmer who is using threading. > In the above example you could try accessing > d using 4 bytes starting from b, but this would give wrong results > if some other thread was accessing b at the same time. I'm fairly > sure that Ada has quite strict requirements about this, and I have > the vague idea (I don't know where I got it from) that there is talk > of requiring a minimum disturbance rule of some kind in C. However what about huge amount of existing C code and other tools that do not enforce this ? - Devang From wmatyjewicz at fastmail.fm Sat Feb 9 14:39:53 2008 From: wmatyjewicz at fastmail.fm (Wojciech Matyjewicz) Date: Sat, 09 Feb 2008 21:39:53 +0100 Subject: [llvm-commits] Fix for PR1798 (ScalarEvolution) In-Reply-To: <47ADE232.5070407@fastmail.fm> References: <478D2769.8060503@fastmail.fm> <47ADE232.5070407@fastmail.fm> Message-ID: <47AE0F99.4070209@fastmail.fm> Small correction: > (only these bitwidths are allowed: 1, 2, ..., 64). Should be: 32, 64. -Wojtek From baldrick at free.fr Sat Feb 9 15:24:19 2008 From: baldrick at free.fr (Duncan Sands) Date: Sat, 9 Feb 2008 22:24:19 +0100 Subject: [llvm-commits] [llvm-gcc-4.2] r46726 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp In-Reply-To: <760C956E-1E4A-4E7B-9A51-8A96AE4CA3AA@apple.com> References: <200802042324.m14NOiBg021071@zion.cs.uiuc.edu> <200802081903.13331.baldrick@free.fr> <760C956E-1E4A-4E7B-9A51-8A96AE4CA3AA@apple.com> Message-ID: <200802092224.20812.baldrick@free.fr> Hi Devang, > > I can't help feeling that a bitfield load or store should touch the > > minimum amount of bytes possible: only those that contain some part > > of the bitfield. ?In some situations touching other bytes could be > > fatal, for example if the type is overlaid on some memory mapped io > > region, or multiple threads are accessing different parts of the > > type simulteneously. > > I do not think this is required as part of current C ABI. This is ? > responsibility of programmer who is using threading. the current LLVM implementation means that anyone using threading needs to not do bitfield accesses, since the compiler generated code could cause trouble. Are you suggesting that users should roll their own bitfield code (I'm not saying that this is unreasonable)? > > In the above example you could try accessing > > d using 4 bytes starting from b, but this would give wrong results > > if some other thread was accessing b at the same time. I'm fairly > > sure that Ada has quite strict requirements about this, and I have > > the vague idea (I don't know where I got it from) that there is talk > > of requiring a minimum disturbance rule of some kind in C. > > However what about huge amount of existing C code and other tools that > do not enforce this ? I don't understand what you mean: I'm talking about making the compiler more strict in the code it generates for bitfield accesses. As such it cannot have any impact on correctness of existing C code (though it might make it run more slowly). As for Ada, the mainline front-end seems to claim that two record fields that do not share a common byte can be safely accessed by multiple threads without synchronization [*]. So it seems that the Ada f-e at least would like bitfield accesses to only touch the minimum number of bytes. By implication it means that gcc bitfield accesses have this property (I will do some experiments to check). Ciao, Duncan. [*] The language reference manual says (9.10 Shared Variables): "If two different objects, including nonoverlapping parts of the same object, are independently addressable, they can be manipulated concurrently by two different tasks without synchronization. Normally, any two nonoverlapping objects are independently addressable. However, if packing, record layout, or Component_Size is specified for a given composite object, then it is implementation defined whether or not two nonoverlapping parts of that composite object are independently addressable." Thus it is implementation defined whether two bitfield accesses are independently addressable (this falls under the record layout exception). However implementations are required to document how they define implementation defined things. The documentation for the gcc Ada front-end says: "27. Whether or not two non overlapping parts of a composite object are independently addressable, in the case where packing, record layout, or Component_Size is specified for the object. See 9.10(1). Separate components are independently addressable if they do not share overlapping storage units." A storage unit is Ada terminology for a byte. From ggreif at gmail.com Sat Feb 9 16:24:34 2008 From: ggreif at gmail.com (Gabor Greif) Date: Sat, 09 Feb 2008 22:24:34 -0000 Subject: [llvm-commits] [llvm] r46912 - /llvm/trunk/docs/LangRef.html Message-ID: <200802092224.m19MOZKa024552@zion.cs.uiuc.edu> Author: ggreif Date: Sat Feb 9 16:24:34 2008 New Revision: 46912 URL: http://llvm.org/viewvc/llvm-project?rev=46912&view=rev Log: explain that NumElements in alloca and malloc defaults to one Modified: llvm/trunk/docs/LangRef.html Modified: llvm/trunk/docs/LangRef.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=46912&r1=46911&r2=46912&view=diff ============================================================================== --- llvm/trunk/docs/LangRef.html (original) +++ llvm/trunk/docs/LangRef.html Sat Feb 9 16:24:34 2008 @@ -2760,10 +2760,10 @@ sizeof(<type>)*NumElements bytes of memory from the operating system and returns a pointer of the appropriate type to the program. If "NumElements" is specified, it is the -number of elements allocated. If an alignment is specified, the value result -of the allocation is guaranteed to be aligned to at least that boundary. If -not specified, or if zero, the target can choose to align the allocation on any -convenient boundary.

        +number of elements allocated, otherwise "NumElements" is defaulted to be one. +If an alignment is specified, the value result of the allocation is guaranteed to +be aligned to at least that boundary. If not specified, or if zero, the target can +choose to align the allocation on any convenient boundary.

        'type' must be a sized type.

        @@ -2846,11 +2846,11 @@

        The 'alloca' instruction allocates sizeof(<type>)*NumElements bytes of memory on the runtime stack, returning a pointer of the -appropriate type to the program. If "NumElements" is specified, it is the -number of elements allocated. If an alignment is specified, the value result -of the allocation is guaranteed to be aligned to at least that boundary. If -not specified, or if zero, the target can choose to align the allocation on any -convenient boundary.

        +appropriate type to the program. If "NumElements" is specified, it is the +number of elements allocated, otherwise "NumElements" is defaulted to be one. +If an alignment is specified, the value result of the allocation is guaranteed +to be aligned to at least that boundary. If not specified, or if zero, the target +can choose to align the allocation on any convenient boundary.

        'type' may be any sized type.

        From sabre at nondot.org Sat Feb 9 16:50:06 2008 From: sabre at nondot.org (Chris Lattner) Date: Sat, 09 Feb 2008 22:50:06 -0000 Subject: [llvm-commits] [llvm] r46913 - in /llvm/trunk: LICENSE.TXT docs/BOOST_LICENSE_1_0.txt Message-ID: <200802092250.m19Mo6hP025223@zion.cs.uiuc.edu> Author: lattner Date: Sat Feb 9 16:50:06 2008 New Revision: 46913 URL: http://llvm.org/viewvc/llvm-project?rev=46913&view=rev Log: scoped_ptr.h was removed. Removed: llvm/trunk/docs/BOOST_LICENSE_1_0.txt Modified: llvm/trunk/LICENSE.TXT Modified: llvm/trunk/LICENSE.TXT URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/LICENSE.TXT?rev=46913&r1=46912&r2=46913&view=diff ============================================================================== --- llvm/trunk/LICENSE.TXT (original) +++ llvm/trunk/LICENSE.TXT Sat Feb 9 16:50:06 2008 @@ -66,7 +66,6 @@ Autoconf llvm/autoconf llvm/projects/ModuleMaker/autoconf llvm/projects/sample/autoconf -Boost C++ Libraries llvm/include : docs/BOOST_LICENSE_1_0.txt CellSPU backend llvm/lib/Target/CellSPU/README.txt Removed: llvm/trunk/docs/BOOST_LICENSE_1_0.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/BOOST_LICENSE_1_0.txt?rev=46912&view=auto ============================================================================== --- llvm/trunk/docs/BOOST_LICENSE_1_0.txt (original) +++ llvm/trunk/docs/BOOST_LICENSE_1_0.txt (removed) @@ -1,23 +0,0 @@ -Boost Software License - Version 1.0 - August 17th, 2003 - -Permission is hereby granted, free of charge, to any person or organization -obtaining a copy of the software and accompanying documentation covered by -this license (the "Software") to use, reproduce, display, distribute, -execute, and transmit the Software, and to prepare derivative works of the -Software, and to permit third-parties to whom the Software is furnished to -do so, all subject to the following: - -The copyright notices in the Software and this entire statement, including -the above license grant, this restriction and the following disclaimer, -must be included in all copies of the Software, in whole or in part, and -all derivative works of the Software, unless such copies or derivative -works are solely in the form of machine-executable object code generated by -a source language processor. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT -SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE -FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, -ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER -DEALINGS IN THE SOFTWARE. From sabre at nondot.org Sat Feb 9 16:58:07 2008 From: sabre at nondot.org (Chris Lattner) Date: Sat, 09 Feb 2008 22:58:07 -0000 Subject: [llvm-commits] [llvm] r46914 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <200802092258.m19Mw7ZN025459@zion.cs.uiuc.edu> Author: lattner Date: Sat Feb 9 16:58:07 2008 New Revision: 46914 URL: http://llvm.org/viewvc/llvm-project?rev=46914&view=rev Log: add some more notes, still not ready for review :) Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=46914&r1=46913&r2=46914&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Sat Feb 9 16:58:07 2008 @@ -107,14 +107,14 @@

        debug improvements -O0 -EH. Gordon: GC Revamp. docs/GarbageCollection.html -Kaleidescope: docs/tutorial +Kaleidoscope: docs/tutorial Gordon: C and Ocaml Bindings +Christopher Lamb: Multiple address spaces. @@ -129,12 +129,18 @@

          -
        • Daniel Berlin and (Curtis?) rewrote Andersen's alias analysis (which is not -enabled by default) to be several orders of magnitude faster, implmented Offline -Variable Substitution.
          • - +
        • Daniel Berlin and Curtis Dunham rewrote Andersen's alias analysis (which is +not enabled by default) to be several orders of magnitude faster, implemented +Offline Variable Substitution.
          • Devang: LoopIndexSplit is enabled by default. + +Dan Gohman: LSR improvements for SSE intrinsics and + +Evan added simple exit value substitution to LSR. + +Anton added readnone/readonly attributes for modelling GCC pure/const +attributes.
        @@ -160,6 +166,14 @@
      • Evan physical register dependencies in the BURR scheduler
      • Evan EXTRACT_SUBREG coalescing support
        • +
      • Evan enhanced LSR to support induction variable reuse when the induction + variables have different widths.
        • + +
      • Rafael Espindola byval support, finished by Evan.
        • + +
      • mod/ref info for machineinstrs
        • + +
      • Evan: Live interval splitting on MBB boundaries.

      @@ -179,6 +193,8 @@
    • Evan: If conversion on by default for ARM.
    • Bruno: MIPS PIC support.
    • Arnold Schwaighofer: X86 tail call support.
      • +
    • Dale darwin/x86-64 and darwin/ppc eh
      • +
    • Evan: darwin/x86 debug info
    @@ -212,6 +228,12 @@
    • Devang added LLVMFoldingBuilder.
    • Dan added support for vector sin, cos, and pow intrinsics.
      • +
    • Ted added a framework for generic object serialization to bitcode files, + only used by clang right now for ASTs but could be used for other + stuff.
      • +
    • Duncan fixed TargetData to distinguish between the size/alignment of a type + in a register, in memory according to the platform ABI, and in memory when + we have a choice.
    @@ -226,7 +248,8 @@

      -
    • .
      • +
    • Gordon Henriksen updated docs/Passes.html
      • +
    • New lexer and parser for tblgen, new lexer for asmparser
    From natebegeman at mac.com Sat Feb 9 17:46:37 2008 From: natebegeman at mac.com (Nate Begeman) Date: Sat, 09 Feb 2008 23:46:37 -0000 Subject: [llvm-commits] [llvm] r46915 - /llvm/trunk/lib/Target/X86/X86InstrSSE.td Message-ID: <200802092346.m19Nkbbd026958@zion.cs.uiuc.edu> Author: sampo Date: Sat Feb 9 17:46:37 2008 New Revision: 46915 URL: http://llvm.org/viewvc/llvm-project?rev=46915&view=rev Log: memopv16i8 had wrong alignment requirement, would have broken pabsb pabs{b,w,d} are not two address fix extract-to-mem sse4 ops add sse4 vector sign extend nodes Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=46915&r1=46914&r2=46915&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Sat Feb 9 17:46:37 2008 @@ -130,9 +130,11 @@ def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>; def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>; def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>; +def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>; // SSSE3 uses MMX registers for some instructions. They aren't aligned on a // 16-byte boundary. +// FIXME: 8 byte alignment for mmx reads is not required def memop64 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{ if (LoadSDNode *LD = dyn_cast(N)) return LD->getExtensionType() == ISD::NON_EXTLOAD && @@ -142,7 +144,6 @@ }]>; def memopv8i8 : PatFrag<(ops node:$ptr), (v8i8 (memop64 node:$ptr))>; -def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop64 node:$ptr))>; def memopv4i16 : PatFrag<(ops node:$ptr), (v4i16 (memop64 node:$ptr))>; def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop64 node:$ptr))>; def memopv2i32 : PatFrag<(ops node:$ptr), (v2i32 (memop64 node:$ptr))>; @@ -2441,105 +2442,89 @@ : I, TA, Requires<[HasSSSE3]>; /// SS3I_unop_rm_int_8 - Simple SSSE3 unary operator whose type is v*i8. -let isTwoAddress = 1 in { - multiclass SS3I_unop_rm_int_8 opc, string OpcodeStr, - Intrinsic IntId64, Intrinsic IntId128, - bit Commutable = 0> { - def rr64 : SS38I { - let isCommutable = Commutable; - } - def rm64 : SS38I; +multiclass SS3I_unop_rm_int_8 opc, string OpcodeStr, + Intrinsic IntId64, Intrinsic IntId128> { + def rr64 : SS38I; + + def rm64 : SS38I; - def rr128 : SS38I, - OpSize { - let isCommutable = Commutable; - } - def rm128 : SS38I, OpSize; - } + def rr128 : SS38I, + OpSize; + + def rm128 : SS38I, OpSize; } /// SS3I_unop_rm_int_16 - Simple SSSE3 unary operator whose type is v*i16. -let isTwoAddress = 1 in { - multiclass SS3I_unop_rm_int_16 opc, string OpcodeStr, - Intrinsic IntId64, Intrinsic IntId128, - bit Commutable = 0> { - def rr64 : SS38I { - let isCommutable = Commutable; - } - def rm64 : SS38I; +multiclass SS3I_unop_rm_int_16 opc, string OpcodeStr, + Intrinsic IntId64, Intrinsic IntId128> { + def rr64 : SS38I; + + def rm64 : SS38I; - def rr128 : SS38I, - OpSize { - let isCommutable = Commutable; - } - def rm128 : SS38I, OpSize; - } + def rr128 : SS38I, + OpSize; + + def rm128 : SS38I, OpSize; } /// SS3I_unop_rm_int_32 - Simple SSSE3 unary operator whose type is v*i32. -let isTwoAddress = 1 in { - multiclass SS3I_unop_rm_int_32 opc, string OpcodeStr, - Intrinsic IntId64, Intrinsic IntId128, - bit Commutable = 0> { - def rr64 : SS38I { - let isCommutable = Commutable; - } - def rm64 : SS38I; +multiclass SS3I_unop_rm_int_32 opc, string OpcodeStr, + Intrinsic IntId64, Intrinsic IntId128> { + def rr64 : SS38I; + + def rm64 : SS38I; - def rr128 : SS38I, - OpSize { - let isCommutable = Commutable; - } - def rm128 : SS38I, OpSize; - } + def rr128 : SS38I, + OpSize; + + def rm128 : SS38I, OpSize; } -// FIXME: are these really two-address? defm PABSB : SS3I_unop_rm_int_8 <0x1C, "pabsb", int_x86_ssse3_pabs_b, int_x86_ssse3_pabs_b_128>; @@ -3156,19 +3141,19 @@ let isTwoAddress = 1 in { multiclass SS41I_binop_rm_int opc, string OpcodeStr, Intrinsic IntId128, bit Commutable = 0> { - def rr128 : SS48I, - OpSize { + def rr : SS48I, + OpSize { let isCommutable = Commutable; } - def rm128 : SS48I, OpSize; + def rm : SS48I, OpSize; } } @@ -3235,23 +3220,23 @@ let isTwoAddress = 1 in { multiclass SS41I_binop_rmi_int opc, string OpcodeStr, Intrinsic IntId128, bit Commutable = 0> { - def rri128 : SS4AI, - OpSize { + def rri : SS4AI, + OpSize { let isCommutable = Commutable; } - def rmi128 : SS4AI, - OpSize; + def rmi : SS4AI, + OpSize; } } @@ -3268,28 +3253,107 @@ defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw, 0>; + +multiclass SS41I_binop_rm_int8 opc, string OpcodeStr, Intrinsic IntId> { + def rr : SS48I, OpSize; + + def rm : SS48I, OpSize; +} + +defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>; +defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>; +defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>; +defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>; +defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>; +defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>; + +multiclass SS41I_binop_rm_int4 opc, string OpcodeStr, Intrinsic IntId> { + def rr : SS48I, OpSize; + + def rm : SS48I, OpSize; +} + +defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>; +defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>; +defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>; +defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>; + +multiclass SS41I_binop_rm_int2 opc, string OpcodeStr, Intrinsic IntId> { + def rr : SS48I, OpSize; + + def rm : SS48I, OpSize; +} + +defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>; +defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovsxbq", int_x86_sse41_pmovzxbq>; + + +/// SS41I_binop_ext8 - SSE 4.1 binary operator with immediate +multiclass SS41I_binop_ext8 opc, string OpcodeStr> { + def rr : SS4AI, OpSize; + def mr : SS4AI, OpSize; +} + +defm PEXTRB : SS41I_binop_ext8<0x14, "pextrb">; + /// SS41I_binop_ext32 - SSE 4.1 binary operator with immediate multiclass SS41I_binop_ext32 opc, string OpcodeStr> { - def rri128 : SS4AI, - OpSize; + def rr : SS4AI, OpSize; + def mr : SS4AI, OpSize; } defm PEXTRD : SS41I_binop_ext32<0x16, "pextrd">; /// SS41I_binop_extf32 - SSE 4.1 binary operator with immediate multiclass SS41I_binop_extf32 opc, string OpcodeStr> { - def rri128 : SS4AI, - OpSize; + def rr : SS4AI, OpSize; + def mr : SS4AI, OpSize; } defm EXTRACTPS : SS41I_binop_extf32<0x17, "extractps">; + From nicholas at mxc.ca Sat Feb 9 18:03:54 2008 From: nicholas at mxc.ca (Nick Lewycky) Date: Sun, 10 Feb 2008 00:03:54 -0000 Subject: [llvm-commits] [llvm] r46916 - /llvm/trunk/lib/Target/PowerPC/PPCTargetAsmInfo.cpp Message-ID: <200802100003.m1A03svv027444@zion.cs.uiuc.edu> Author: nicholas Date: Sat Feb 9 18:03:54 2008 New Revision: 46916 URL: http://llvm.org/viewvc/llvm-project?rev=46916&view=rev Log: Match GCC's behaviour for these sections. Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetAsmInfo.cpp Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetAsmInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetAsmInfo.cpp?rev=46916&r1=46915&r2=46916&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCTargetAsmInfo.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCTargetAsmInfo.cpp Sat Feb 9 18:03:54 2008 @@ -92,8 +92,8 @@ CommentString = "#"; GlobalPrefix = ""; PrivateGlobalPrefix = ""; - ConstantPoolSection = "\t.section .rodata.cst4\t"; - JumpTableDataSection = ".section .rodata.cst4"; + ConstantPoolSection = "\t.section .rodata\t"; + JumpTableDataSection = ".section .rodata"; CStringSection = "\t.section\t.rodata"; StaticCtorsSection = ".section\t.ctors,\"aw\", at progbits"; StaticDtorsSection = ".section\t.dtors,\"aw\", at progbits"; From sabre at nondot.org Sat Feb 9 19:01:35 2008 From: sabre at nondot.org (Chris Lattner) Date: Sun, 10 Feb 2008 01:01:35 -0000 Subject: [llvm-commits] [llvm] r46918 - /llvm/trunk/lib/CodeGen/README.txt Message-ID: <200802100101.m1A11ZO5028956@zion.cs.uiuc.edu> Author: lattner Date: Sat Feb 9 19:01:35 2008 New Revision: 46918 URL: http://llvm.org/viewvc/llvm-project?rev=46918&view=rev Log: add anote Modified: llvm/trunk/lib/CodeGen/README.txt Modified: llvm/trunk/lib/CodeGen/README.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/README.txt?rev=46918&r1=46917&r2=46918&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/README.txt (original) +++ llvm/trunk/lib/CodeGen/README.txt Sat Feb 9 19:01:35 2008 @@ -192,3 +192,10 @@ doing the wrong thing. //===---------------------------------------------------------------------===// + +It would be really nice to be able to write patterns in .td files for copies, +which would eliminate a bunch of explicit predicates on them (e.g. no side +effects). Once this is in place, it would be even better to have tblgen +synthesize the various copy insertion/inspection methods in TargetInstrInfo. + +//===---------------------------------------------------------------------===// From sabre at nondot.org Sun Feb 10 01:04:36 2008 From: sabre at nondot.org (Chris Lattner) Date: Sun, 10 Feb 2008 07:04:36 -0000 Subject: [llvm-commits] [llvm] r46920 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <200802100704.m1A74bb8006001@zion.cs.uiuc.edu> Author: lattner Date: Sun Feb 10 01:04:35 2008 New Revision: 46920 URL: http://llvm.org/viewvc/llvm-project?rev=46920&view=rev Log: random notes Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=46920&r1=46919&r2=46920&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Sun Feb 10 01:04:35 2008 @@ -68,6 +68,21 @@
    +Deprecated features in LLVM 2.2 +
    + +
    + +

    This is the last LLVM release to support llvm-gcc 4.0, llvm-upgrade, and +llvmc in its current form. llvm-gcc 4.0 has been replaced with llvm-gcc 4.2. +llvm-upgrade is useful for upgrading llvm 1.9 files to llvm 2.x syntax, but you +can always use an old release to do this. llvmc is currently mostly useless in +llvm 2.2, and will be redesigned or removed in llvm 2.3.

    + +
    + + +
    llvm-gcc 4.0, llvm-gcc 4.2, and clang
    @@ -100,6 +115,8 @@
    +

    Scott Michel contributed Cell backend

    +

    Dale contributed full support for long double on x86/x86-64 (where it is 80 bits) and on Darwin PPC/PPC64 (where it is 128 bits).

    @@ -131,7 +148,7 @@
  2. Daniel Berlin and Curtis Dunham rewrote Andersen's alias analysis (which is not enabled by default) to be several orders of magnitude faster, implemented -Offline Variable Substitution.
    3. +Offline Variable Substitution and Lazy Cycle Detection. Devang: LoopIndexSplit is enabled by default. @@ -139,8 +156,9 @@ Evan added simple exit value substitution to LSR. -Anton added readnone/readonly attributes for modelling GCC pure/const -attributes. +Anton added readnone/readonly attributes for modeling function side effects +and Duncan hooked up GCC's pure/const attributes to use them and enhanced alias +analysis to use them.
    @@ -169,11 +187,16 @@
  3. Evan enhanced LSR to support induction variable reuse when the induction variables have different widths.
    4. -
  4. Rafael Espindola byval support, finished by Evan.
    5. +
  5. Rafael Espindola byval support, finished by Evan for x86 (32/64).
    6. -
  6. mod/ref info for machineinstrs
    7. +
  7. mod/ref info for machineinstrs, inferred from .td files
  8. Evan: Live interval splitting on MBB boundaries.
    9. + +Efficient iteration over use/defs of registers like llvm ir. + +The MachineInstr, MachineOperand and TargetInstrDesc classes are simpler, more +consistent, and better documented. @@ -234,6 +257,9 @@
  9. Duncan fixed TargetData to distinguish between the size/alignment of a type in a register, in memory according to the platform ABI, and in memory when we have a choice.
    10. +
  10. Duncan moved parameter attributes off of function type and onto functions + and calls, which makes it much easier to add attributes to a function in a + transformation.
    11. @@ -250,6 +276,7 @@
    • Gordon Henriksen updated docs/Passes.html
    • New lexer and parser for tblgen, new lexer for asmparser
      • +
    • Dale GCC testsuite
    From sabre at nondot.org Sun Feb 10 01:46:44 2008 From: sabre at nondot.org (Chris Lattner) Date: Sun, 10 Feb 2008 07:46:44 -0000 Subject: [llvm-commits] [llvm] r46921 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <200802100746.m1A7kimH007169@zion.cs.uiuc.edu> Author: lattner Date: Sun Feb 10 01:46:44 2008 New Revision: 46921 URL: http://llvm.org/viewvc/llvm-project?rev=46921&view=rev Log: more prose, some organization improvements. Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=46921&r1=46920&r2=46921&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Sun Feb 10 01:46:44 2008 @@ -66,6 +66,13 @@ + +
    Deprecated features in LLVM 2.2 @@ -92,10 +99,10 @@ LLVM 2.1, llvm-gcc 4.2 was beta). Since LLVM 2.1, the llvm-gcc 4.2 front-end has made leaps and bounds and is now at least as good as 4.0 in virtually every area, and is better in several areas (for example, exception handling -correctness). We strongly recommend that you migrate from llvm-gcc 4.0 to -llvm-gcc 4.2 in this release cycle because LLVM 2.2 is the last release -that will support llvm-gcc 4.0: LLVM 2.3 will only support the llvm-gcc -4.2 front-end.

    +correctness, support for Ada and FORTRAN). We strongly recommend that you +migrate from llvm-gcc 4.0 to llvm-gcc 4.2 in this release cycle because +LLVM 2.2 is the last release that will support llvm-gcc 4.0: LLVM 2.3 +will only support the llvm-gcc 4.2 front-end.

    The clang project is an effort to build a set of new 'llvm native' front-end technologies for the LLVM optimizer @@ -104,7 +111,7 @@ capabilities. If you are interested in building source-level tools for C and Objective-C (and eventually C++), you should take a look. However, note that clang is not an official part of the LLVM 2.2 release. If you are interested in -this project, please see the web site.

    +this project, please see its web site.

    @@ -115,88 +122,113 @@
    -

    Scott Michel contributed Cell backend

    - -

    Dale contributed full support for long double on x86/x86-64 (where it is 80 -bits) and on Darwin PPC/PPC64 (where it is 128 bits).

    - -

    Ada, gfortran

    - -

    -debug improvements -O0 - -Gordon: GC Revamp. docs/GarbageCollection.html +

    LLVM 2.2 includes several major new capabilities:

    -Kaleidoscope: docs/tutorial +
      +
    • Scott Michel contributed an SPU backend, which generates code for the +vector coprocessors on the Cell processor. (Status?)
      • -Gordon: C and Ocaml Bindings +
    • llvm-gcc 4.2 has significantly improved support for the GCC Ada (GNAT) and +FORTRAN (gfortran) frontends. Duncan has the llvm-gcc 4.2 GNAT front-end +supporting almost all of the ACATS testsuite (except 2 tests?). The llvm-gcc +4.2 gfortran front-end supports a broad range of FORTRAN code, but does not support EQUIVALENCE yet.
      • + +
    • Dale contributed full support for long double on x86/x86-64 (where it is 80 +bits) and on Darwin PPC/PPC64 (where it is 128 bits). In previous LLVM +releases, llvm-gcc silently mapped long double to double.
      • + +
    • Gordon rewrote most of the Accurate Garbage +Collection code in the code generator, making the generated code more +efficient and adding support for the Ocaml garbage collector metadata +format.
      • + +
    • LLVM now includes a new set of detailed tutorials, which explain how to implement a +language with LLVM and shows how to use several important APIs.
      • -Christopher Lamb: Multiple address spaces.
    -Optimizer Improvements +Code Generator Improvements
    -

    Some of the most noticable feature improvements this release have been in the -optimizer, speeding it up and making it more aggressive. For example:

    +

    We put a significant amount of work into the code generator infrastructure, +which allows us to implement more aggressive algorithms and make it run +faster:

      -
    • Daniel Berlin and Curtis Dunham rewrote Andersen's alias analysis (which is -not enabled by default) to be several orders of magnitude faster, implemented -Offline Variable Substitution and Lazy Cycle Detection.
      • - -Devang: LoopIndexSplit is enabled by default. +
    • Owen refactored the existing LLVM dominator and loop information code to +allow it work on the machine code representation. He contributed support for +dominator and loop information on machine code and merged the code for forward +and backward dominator computation.
      • + +
    • Dan added support for emitting debug information with .file and .loc +directives on that support it, instead of emitting large tables in the .s +file.
      • + +
    • Evan extended the DAG scheduler to model physical register dependencies +explicitly and have the BURR scheduler pick a correct schedule based on the +dependencies. This reduces our use of the 'flag' operand hack.
      • + +
    • Evan added initial support for register coalescing of subregister +references.
      • + +
    • Rafael Espindola implemented initial support for a new 'byval' attribute, +which allows more efficient by-value argument passing in the LLVM IR. Evan +finished support for it and enabled it in the X86 (32- and 64-bit) and C +backends.
      • + +
    • The LLVM TargetInstrInfo class can now answer queries about the mod/ref and +side-effect behavior of MachineInstr's. This information is inferred +automatically by TableGen from .td files for all instructions with +patterns.
      • + +
    • Evan implemented simple live interval splitting on basic block boundaries. +This allows the register allocator to be more successful at keeping values in +registers in some parts of a value's live range, even if they need to be spilled +in some other block.
      • + +
    • The new MachineRegisterInfo.h class provides support for efficiently +iterating over all defs/uses of a register, and this information is +automatically kept up-to-date. This support is similar to the use_iterator in +the LLVM IR level.
      • -Dan Gohman: LSR improvements for SSE intrinsics and - -Evan added simple exit value substitution to LSR. - -Anton added readnone/readonly attributes for modeling function side effects -and Duncan hooked up GCC's pure/const attributes to use them and enhanced alias -analysis to use them. +
    • The MachineInstr, MachineOperand and TargetInstrDesc classes are simpler, +more consistent, and better documented.
    -Code Generator Improvements +Optimizer Improvements
    -

    foci of this release was performance tuning and bug - fixing. In addition to these, several new major changes occurred:

    +

    In addition to a huge array of bug fixes and minor performance tweaks, LLVM +2.2 supports a few major enhancements:

      -
    • Owen contributed Machine Loop info, domintors, etc. Merged dom and - postdom.
      • +
    • Daniel Berlin and Curtis Dunham rewrote Andersen's alias analysis to be +several orders of magnitude faster, implemented Offline Variable Substitution +and Lazy Cycle Detection. Note that Andersen's is not enabled in llvm-gcc by +default.
      • -
    • Dan added support for emitting debug information with .file and .loc on -targets that support it
      • +
    • Dan Gohman contributed several enhancements to Loop Strength Reduction (LSR) +to make it more aggressive with SSE intrinsics.
      • -
    • Evan physical register dependencies in the BURR scheduler
      • +
    • Evan added support for simple exit value substitution to LSR.
      • -
    • Evan EXTRACT_SUBREG coalescing support
    • Evan enhanced LSR to support induction variable reuse when the induction - variables have different widths.
      • - -
    • Rafael Espindola byval support, finished by Evan for x86 (32/64).
      • - -
    • mod/ref info for machineinstrs, inferred from .td files
      • - -
    • Evan: Live interval splitting on MBB boundaries.
      • - -Efficient iteration over use/defs of registers like llvm ir. +variables have different widths. -The MachineInstr, MachineOperand and TargetInstrDesc classes are simpler, more -consistent, and better documented.
    @@ -217,28 +249,11 @@
  11. Bruno: MIPS PIC support.
  12. Arnold Schwaighofer: X86 tail call support.
  13. Dale darwin/x86-64 and darwin/ppc eh
    14. -
  14. Evan: darwin/x86 debug info
    15. +
  15. Evan: darwin/x86 debug info, improvements at -O0?
    16. - - -
    -llvm-gcc Improvements -
    - -
    -

    New features include: -

    - -
      -
    • .
      • -
    - -
    - -
    LLVM Core Improvements @@ -260,6 +275,13 @@
  16. Duncan moved parameter attributes off of function type and onto functions and calls, which makes it much easier to add attributes to a function in a transformation.
    17. +
  17. Christopher Lamb: Multiple address spaces.
    18. +
  18. Gordon: C and Ocaml Bindings
    19. + +
  19. Anton added readnone/readonly attributes for modeling function side effects +and Duncan hooked up GCC's pure/const attributes to use them and enhanced alias +analysis to use them.
    20. +
    From isanbard at gmail.com Sun Feb 10 02:10:24 2008 From: isanbard at gmail.com (Bill Wendling) Date: Sun, 10 Feb 2008 08:10:24 -0000 Subject: [llvm-commits] [llvm] r46922 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <200802100810.m1A8AOS2007775@zion.cs.uiuc.edu> Author: void Date: Sun Feb 10 02:10:24 2008 New Revision: 46922 URL: http://llvm.org/viewvc/llvm-project?rev=46922&view=rev Log: Return "(c1 + c2)" instead of yet another ADD node (which made this a no-op). Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=46922&r1=46921&r2=46922&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sun Feb 10 02:10:24 2008 @@ -923,7 +923,7 @@ return N1; // fold (add c1, c2) -> c1+c2 if (N0C && N1C) - return DAG.getNode(ISD::ADD, VT, N0, N1); + return DAG.getConstant(N0C->getValue() + N1C->getValue(), VT); // canonicalize constant to RHS if (N0C && !N1C) return DAG.getNode(ISD::ADD, VT, N1, N0); From sabre at nondot.org Sun Feb 10 02:17:19 2008 From: sabre at nondot.org (Chris Lattner) Date: Sun, 10 Feb 2008 08:17:19 -0000 Subject: [llvm-commits] [llvm] r46923 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <200802100817.m1A8HJ50007971@zion.cs.uiuc.edu> Author: lattner Date: Sun Feb 10 02:17:19 2008 New Revision: 46923 URL: http://llvm.org/viewvc/llvm-project?rev=46923&view=rev Log: final set of major updates Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=46923&r1=46922&r2=46923&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Sun Feb 10 02:17:19 2008 @@ -138,10 +138,15 @@ bits) and on Darwin PPC/PPC64 (where it is 128 bits). In previous LLVM releases, llvm-gcc silently mapped long double to double. -
  20. Gordon rewrote most of the Accurate Garbage -Collection code in the code generator, making the generated code more -efficient and adding support for the Ocaml garbage collector metadata -format.
    21. +
  21. Gordon Henriksen rewrote most of the Accurate Garbage Collection code in the code generator, making the +generated code more efficient and adding support for the Ocaml garbage collector +metadata format.
    22. + +
  22. Christopher Lamb contributed support for multiple address spaces in LLVM +IR. This is useful for supporting targets that have 'near' vs 'far' pointers, +'RAM' vs 'ROM' pointers, or that have non-local memory that can be accessed with +special instructions.
  23. LLVM now includes a new set of detailed tutorials, which explain how to implement a @@ -151,6 +156,44 @@
    +LLVM Core Improvements +
    + +
    +

    New features include: +

    + +
      +
    • Gordon contributed support for C and Ocaml Bindings for the basic LLVM IR +construction routines as well as several other auxiliary APIs.
      • + +
    • Anton added readnone/readonly attributes for modeling function side effects. +Duncan hooked up GCC's pure/const attributes to use them and enhanced mod/ref +analysis to use them.
      • + +
    • Devang added LLVMFoldingBuilder, a version of LLVMBuilder that implicitly +simplifies the code as it is constructed.
      • + +
    • Ted Kremenek added a framework for generic object serialization to bitcode +files. This support is only used by clang right now for ASTs but is extensible +and could be used for serializing arbitrary other data into bitcode files.
      • + +
    • Duncan improved TargetData to distinguish between the size/alignment of a +type in a register, in memory according to the platform ABI, and in memory when +we have a choice.
      • + +
    • Duncan moved parameter attributes off of FunctionType and onto functions +and calls. This makes it much easier to add attributes to a function in a +transformation pass.
      • + +
    • Dan Gohman added support for vector sin, cos, and pow intrinsics.
      • + +
    + +
    + + +
    Code Generator Improvements
    @@ -211,15 +254,15 @@
    -

    In addition to a huge array of bug fixes and minor performance tweaks, LLVM -2.2 supports a few major enhancements:

    +

    In addition to a huge array of bug fixes and minor performance tweaks, the +LLVM 2.2 optimizers support a few major enhancements:

    • Daniel Berlin and Curtis Dunham rewrote Andersen's alias analysis to be -several orders of magnitude faster, implemented Offline Variable Substitution -and Lazy Cycle Detection. Note that Andersen's is not enabled in llvm-gcc by -default.
      • +several orders of magnitude faster, and implemented Offline Variable +Substitution and Lazy Cycle Detection. Note that Andersen's is not enabled in +llvm-gcc by default, but can be accessed through 'opt'.
    • Dan Gohman contributed several enhancements to Loop Strength Reduction (LSR) to make it more aggressive with SSE intrinsics.
      • @@ -240,48 +283,23 @@
    -

    New features include: +

    New target-specific features include:

      -
    • Evan X86 now models EFLAGS in instructions.
      • -
    • Evan: If conversion on by default for ARM.
      • -
    • Bruno: MIPS PIC support.
      • -
    • Arnold Schwaighofer: X86 tail call support.
      • -
    • Dale darwin/x86-64 and darwin/ppc eh
      • -
    • Evan: darwin/x86 debug info, improvements at -O0?
      • -
    - -
    - - -
    -LLVM Core Improvements -
    - -
    -

    New features include: -

    - -
      -
    • Devang added LLVMFoldingBuilder.
      • -
    • Dan added support for vector sin, cos, and pow intrinsics.
      • -
    • Ted added a framework for generic object serialization to bitcode files, - only used by clang right now for ASTs but could be used for other - stuff.
      • -
    • Duncan fixed TargetData to distinguish between the size/alignment of a type - in a register, in memory according to the platform ABI, and in memory when - we have a choice.
      • -
    • Duncan moved parameter attributes off of function type and onto functions - and calls, which makes it much easier to add attributes to a function in a - transformation.
      • -
    • Christopher Lamb: Multiple address spaces.
      • -
    • Gordon: C and Ocaml Bindings
      • - -
    • Anton added readnone/readonly attributes for modeling function side effects -and Duncan hooked up GCC's pure/const attributes to use them and enhanced alias -analysis to use them.
      • - +
    • Evan contributed support to the X86 backend to model the mod/ref behavior +of the EFLAGS register explicitly in all instructions. This gives more freedom +to the scheduler, and is a more explicit way to model the instructions.
      • +
    • Dale contributed support for exception handling on Darwin/x86-64 and +Darwin/ppc.
      • +
    • Evan turned on if-conversion by default for ARM, allowing LLVM to take +advantage of its predication features.
      • +
    • Bruno added PIC support to the MIPS backend, fixed many bugs and improved +support for architecture variants.
      • +
    • Arnold Schwaighofer added support for X86 tail calls (limitations? +details?).
      • +
    • Evan contributed several enhancements to Darwin/x86 debug information, +and improvements at -O0 (details?).
    @@ -296,9 +314,18 @@

      -
    • Gordon Henriksen updated docs/Passes.html
      • -
    • New lexer and parser for tblgen, new lexer for asmparser
      • -
    • Dale GCC testsuite
      • +
    • Gordon expanded and updated the LLVM Analysis and +Transformation Passes reference to include descriptions for each pass.
      • + +
    • We rewrote the lexer and parser used by TableGen to make them simpler +and cleaner. This gives tblgen support for 'caret diagnostics'. The .ll file +lexer was also rewritten to support caret diagnostics but doesn't use this +support yet.
      • + +
    • Dale has been grinding through the GCC testsuite, and marked many +LLVM-incompatible tests as not-to-be-run (for example, if they are grepping +through some GCC dump file that LLVM doesn't produce), he also found and fixed +many LLVM bugs exposed by the testsuite.
    @@ -387,6 +414,8 @@
  24. The X86 backend occasionally has alignment problems on operating systems that don't require 16-byte stack alignment (including most non-darwin OS's like linux).
    25. +
  25. The X86 backend generates inefficient floating point code when configured to + generate code for systems that don't have SSE2.
    26. @@ -418,7 +447,7 @@ results (PR1388).
  26. Compilation for ARM Linux OABI (old ABI) is supported, but not fully tested.
    27. -
  27. There is a bug in QEMU-ARM (<= 0.9.0) which causes it to incorrectly execute +
  28. There is a bug in QEMU-ARM (<= 0.9.0) which causes it to incorrectly execute programs compiled with LLVM. Please use more recent versions of QEMU.
    29. @@ -550,11 +579,11 @@ const, constructor, destructor, deprecated, fastcall, format, format_arg, non_null, noinline, - noreturn, pure, regparm + noreturn, nothrow, pure, regparm section, stdcall, unused, used, visibility, warn_unused_result, weak
    - Ignored: nothrow, malloc, + Ignored: malloc, no_instrument_function
From sabre at nondot.org Sun Feb 10 02:18:42 2008 From: sabre at nondot.org (Chris Lattner) Date: Sun, 10 Feb 2008 08:18:42 -0000 Subject: [llvm-commits] [llvm] r46924 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <200802100818.m1A8Iglw008079@zion.cs.uiuc.edu> Author: lattner Date: Sun Feb 10 02:18:42 2008 New Revision: 46924 URL: http://llvm.org/viewvc/llvm-project?rev=46924&view=rev Log: validation fixes Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=46924&r1=46923&r2=46924&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Sun Feb 10 02:18:42 2008 @@ -152,6 +152,8 @@ href="tutorial/index.html">tutorials, which explain how to implement a language with LLVM and shows how to use several important APIs. + + @@ -697,7 +699,7 @@ Valid CSS! Valid HTML 4.01! + src="http://www.w3.org/Icons/valid-html401" alt="Valid HTML 4.01!"> LLVM Compiler Infrastructure
Last modified: $Date$ From sabre at nondot.org Sun Feb 10 02:19:35 2008 From: sabre at nondot.org (Chris Lattner) Date: Sun, 10 Feb 2008 08:19:35 -0000 Subject: [llvm-commits] [llvm] r46925 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <200802100819.m1A8JZMB008111@zion.cs.uiuc.edu> Author: lattner Date: Sun Feb 10 02:19:35 2008 New Revision: 46925 URL: http://llvm.org/viewvc/llvm-project?rev=46925&view=rev Log: remove the in progress marker. Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=46925&r1=46924&r2=46925&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Sun Feb 10 02:19:35 2008 @@ -23,8 +23,6 @@

Written by the LLVM Team

-

THIS IS A WORK IN PROGRESS FOR THE LLVM 2.2 -RELEASE
From baldrick at free.fr Sun Feb 10 04:09:11 2008 From: baldrick at free.fr (Duncan Sands) Date: Sun, 10 Feb 2008 10:09:11 -0000 Subject: [llvm-commits] [llvm] r46926 - in /llvm/trunk/lib/CodeGen/SelectionDAG: LegalizeTypes.h LegalizeTypesExpand.cpp SelectionDAG.cpp Message-ID: <200802101009.m1AA9F1d019251@zion.cs.uiuc.edu> Author: baldrick Date: Sun Feb 10 04:08:52 2008 New Revision: 46926 URL: http://llvm.org/viewvc/llvm-project?rev=46926&view=rev Log: Add truncate and AssertZext result expansion. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=46926&r1=46925&r2=46926&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Sun Feb 10 04:08:52 2008 @@ -209,6 +209,8 @@ void ExpandResult_ANY_EXTEND (SDNode *N, SDOperand &Lo, SDOperand &Hi); void ExpandResult_ZERO_EXTEND(SDNode *N, SDOperand &Lo, SDOperand &Hi); void ExpandResult_SIGN_EXTEND(SDNode *N, SDOperand &Lo, SDOperand &Hi); + void ExpandResult_AssertZext (SDNode *N, SDOperand &Lo, SDOperand &Hi); + void ExpandResult_TRUNCATE (SDNode *N, SDOperand &Lo, SDOperand &Hi); void ExpandResult_BIT_CONVERT(SDNode *N, SDOperand &Lo, SDOperand &Hi); void ExpandResult_SIGN_EXTEND_INREG(SDNode *N, SDOperand &Lo, SDOperand &Hi); void ExpandResult_LOAD (LoadSDNode *N, SDOperand &Lo, SDOperand &Hi); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp?rev=46926&r1=46925&r2=46926&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp Sun Feb 10 04:08:52 2008 @@ -60,6 +60,8 @@ case ISD::ANY_EXTEND: ExpandResult_ANY_EXTEND(N, Lo, Hi); break; case ISD::ZERO_EXTEND: ExpandResult_ZERO_EXTEND(N, Lo, Hi); break; case ISD::SIGN_EXTEND: ExpandResult_SIGN_EXTEND(N, Lo, Hi); break; + case ISD::AssertZext: ExpandResult_AssertZext(N, Lo, Hi); break; + case ISD::TRUNCATE: ExpandResult_TRUNCATE(N, Lo, Hi); break; case ISD::BIT_CONVERT: ExpandResult_BIT_CONVERT(N, Lo, Hi); break; case ISD::SIGN_EXTEND_INREG: ExpandResult_SIGN_EXTEND_INREG(N, Lo, Hi); break; case ISD::LOAD: ExpandResult_LOAD(cast(N), Lo, Hi); break; @@ -202,6 +204,34 @@ } } +void DAGTypeLegalizer::ExpandResult_AssertZext(SDNode *N, + SDOperand &Lo, SDOperand &Hi) { + GetExpandedOp(N->getOperand(0), Lo, Hi); + MVT::ValueType NVT = Lo.getValueType(); + MVT::ValueType EVT = cast(N->getOperand(1))->getVT(); + unsigned NVTBits = MVT::getSizeInBits(NVT); + unsigned EVTBits = MVT::getSizeInBits(EVT); + + if (NVTBits < EVTBits) { + Hi = DAG.getNode(ISD::AssertZext, NVT, Hi, + DAG.getValueType(MVT::getIntegerType(EVTBits - NVTBits))); + } else { + Lo = DAG.getNode(ISD::AssertZext, NVT, Lo, DAG.getValueType(EVT)); + // The high part must be zero, make it explicit. + Hi = DAG.getConstant(0, NVT); + } +} + +void DAGTypeLegalizer::ExpandResult_TRUNCATE(SDNode *N, + SDOperand &Lo, SDOperand &Hi) { + MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + Lo = DAG.getNode(ISD::TRUNCATE, NVT, N->getOperand(0)); + Hi = DAG.getNode(ISD::SRL, N->getOperand(0).getValueType(), N->getOperand(0), + DAG.getConstant(MVT::getSizeInBits(NVT), + TLI.getShiftAmountTy())); + Hi = DAG.getNode(ISD::TRUNCATE, NVT, Hi); +} + void DAGTypeLegalizer::ExpandResult_BIT_CONVERT(SDNode *N, SDOperand &Lo, SDOperand &Hi) { // Lower the bit-convert to a store/load from the stack, then expand the load. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=46926&r1=46925&r2=46926&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Sun Feb 10 04:08:52 2008 @@ -2018,6 +2018,7 @@ "Cannot *_EXTEND_INREG FP types"); assert(MVT::getSizeInBits(EVT) <= MVT::getSizeInBits(VT) && "Not extending!"); + if (VT == EVT) return N1; // noop assertion. break; } case ISD::SIGN_EXTEND_INREG: { From wmatyjewicz at fastmail.fm Sun Feb 10 04:41:09 2008 From: wmatyjewicz at fastmail.fm (Wojciech Matyjewicz) Date: Sun, 10 Feb 2008 10:41:09 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r46927 - /llvm-gcc-4.2/trunk/gcc/gcc.c Message-ID: <200802101041.m1AAfAlM011963@zion.cs.uiuc.edu> Author: wmat Date: Sun Feb 10 04:41:01 2008 New Revision: 46927 URL: http://llvm.org/viewvc/llvm-project?rev=46927&view=rev Log: Revert commits: r46886, r46860, r46858. Restore proper working of -emit-llvm and --emit-llvm options on, at least, Linux/x86. Modified: llvm-gcc-4.2/trunk/gcc/gcc.c Modified: llvm-gcc-4.2/trunk/gcc/gcc.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/gcc.c?rev=46927&r1=46926&r2=46927&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/gcc.c (original) +++ llvm-gcc-4.2/trunk/gcc/gcc.c Sun Feb 10 04:41:01 2008 @@ -825,12 +825,12 @@ /* LLVM LOCAL begin */ static const char *llvm_options = #ifdef ENABLE_LLVM -"%{O4|Zemit-llvm:%{S:-emit-llvm} \ +"%{O4|emit-llvm:%{S:-emit-llvm} \ %{!S:-emit-llvm-bc \ %{c: %W{o*} %{!o*:-o %b%w.o}} \ %{!c:-o %d%w%u%O}}}" #else - "%{Zemit-llvm:%e--emit-llvm is not supported in this configuration.}" + "%{emit-llvm:%e--emit-llvm is not supported in this configuration.}" #endif ; /* LLVM LOCAL end */ @@ -860,10 +860,10 @@ static const char *invoke_as = #ifdef AS_NEEDS_DASH_FOR_PIPED_INPUT /* LLVM LOCAL */ -"%{!O4:%{!Zemit-llvm:%{!S:-o %|.s |\n as %(asm_options) %|.s %A }}}"; +"%{!O4:%{!emit-llvm:%{!S:-o %|.s |\n as %(asm_options) %|.s %A }}}"; #else /* LLVM LOCAL */ -"%{!O4:%{!Zemit-llvm:%{!S:-o %|.s |\n as %(asm_options) %m.s %A }}}"; +"%{!O4:%{!emit-llvm:%{!S:-o %|.s |\n as %(asm_options) %m.s %A }}}"; #endif /* Some compilers have limits on line lengths, and the multilib_select @@ -1226,8 +1226,6 @@ const char *const replacements; } target_option_translations[] = { - /* LLVM LOCAL */ - {"-emit-llvm", "-Zemit-llvm"}, TARGET_OPTION_TRANSLATE_TABLE, { 0, 0 } }; From baldrick at free.fr Sun Feb 10 07:40:58 2008 From: baldrick at free.fr (Duncan Sands) Date: Sun, 10 Feb 2008 13:40:58 -0000 Subject: [llvm-commits] [llvm] r46928 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <200802101340.m1ADew88016974@zion.cs.uiuc.edu> Author: baldrick Date: Sun Feb 10 07:40:55 2008 New Revision: 46928 URL: http://llvm.org/viewvc/llvm-project?rev=46928&view=rev Log: Add some Ada info and correct a few buglets. Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=46928&r1=46927&r2=46928&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Sun Feb 10 07:40:55 2008 @@ -97,7 +97,7 @@ LLVM 2.1, llvm-gcc 4.2 was beta). Since LLVM 2.1, the llvm-gcc 4.2 front-end has made leaps and bounds and is now at least as good as 4.0 in virtually every area, and is better in several areas (for example, exception handling -correctness, support for Ada and FORTRAN). We strongly recommend that you +correctness, support for Ada and Fortran). We strongly recommend that you migrate from llvm-gcc 4.0 to llvm-gcc 4.2 in this release cycle because LLVM 2.2 is the last release that will support llvm-gcc 4.0: LLVM 2.3 will only support the llvm-gcc 4.2 front-end.

@@ -126,11 +126,11 @@
  • Scott Michel contributed an SPU backend, which generates code for the vector coprocessors on the Cell processor. (Status?)
    • -
  • llvm-gcc 4.2 has significantly improved support for the GCC Ada (GNAT) and -FORTRAN (gfortran) frontends. Duncan has the llvm-gcc 4.2 GNAT front-end -supporting almost all of the ACATS testsuite (except 2 tests?). The llvm-gcc -4.2 gfortran front-end supports a broad range of FORTRAN code, but does not support EQUIVALENCE yet.
    • +
  • Anton and Duncan significantly improved llvm-gcc 4.2 support for the GCC Ada +(GNAT) and Fortran (gfortran) front-ends. These front-ends should still be considered +experimental however: see the list of known problems. +The release binaries do not contain either front-end: they need to be built from +source (the Ada front-end only builds on x86-32 linux).
  • Dale contributed full support for long double on x86/x86-64 (where it is 80 bits) and on Darwin PPC/PPC64 (where it is 128 bits). In previous LLVM @@ -168,7 +168,7 @@ construction routines as well as several other auxiliary APIs.
  • Anton added readnone/readonly attributes for modeling function side effects. -Duncan hooked up GCC's pure/const attributes to use them and enhanced mod/ref +Duncan hooked up GCC's pure/const attributes to them and enhanced mod/ref analysis to use them.
  • Devang added LLVMFoldingBuilder, a version of LLVMBuilder that implicitly @@ -182,7 +182,7 @@ type in a register, in memory according to the platform ABI, and in memory when we have a choice.
    • -
  • Duncan moved parameter attributes off of FunctionType and onto functions +
  • Reid moved parameter attributes off of FunctionType and onto functions and calls. This makes it much easier to add attributes to a function in a transformation pass.
    • @@ -211,7 +211,7 @@ and backward dominator computation.
  • Dan added support for emitting debug information with .file and .loc -directives on that support it, instead of emitting large tables in the .s +directives on platforms that support it, instead of emitting large tables in the .s file.
  • Evan extended the DAG scheduler to model physical register dependencies @@ -300,6 +300,7 @@ details?).
  • Evan contributed several enhancements to Darwin/x86 debug information, and improvements at -O0 (details?).
    • +
  • Duncan added x86-64 support for trampolines (pointers to nested functions).
    • @@ -528,6 +529,7 @@
  • The C backend violates the ABI of common C++ programs, preventing intermixing between C++ compiled by the CBE and C++ code compiled with LLC or native compilers.
    • +
  • The C backend does not support all exception handling constructs.
    • @@ -538,6 +540,52 @@ Known problems with the C front-end + +
    + Known problems with the Ada front-end +
    + +
    +The llvm-gcc 4.2 Ada compiler works fairly well, however this is not a mature +technology and problems should be expected. +
      +
    • The Ada front-end currently only builds on x86-32. This is mainly due +to lack of trampoline support (pointers to nested functions) on other platforms, +however it also fails to build on x86-64 +which does support trampolines.
      • +
    • The Ada front-end fails to bootstrap. +Workaround: configure with --disable-bootstrap.
      • +
    • The c380004 and c393010 ACATS tests +fail (c380004 also fails with gcc-4.2 mainline).
      • +
    • Many gcc specific Ada tests continue to crash the compiler.
      • +
    • The -E binder option (exception backtraces) +does not work and will result in programs +crashing if an exception is raised. Workaround: do not use -E.
      • +
    • Only discrete types are allowed to start +or finish at a non-byte offset in a record. Workaround: do not pack records +or use representation clauses that result in a field of a non-discrete type +starting or finishing in the middle of a byte.
      • +
    • The lli interpreter considers 'main' +as generated by the Ada binder to be invalid. +Workaround: hand edit the file to use pointers for argv and envp rather than +integers.
      • +
    • The -fstack-check option is ignored.
      • +
    +
    + + +
    + Known problems with the Fortran front-end +
    + +
    + + +
    +
    Bugs
    @@ -567,7 +615,7 @@ As in Algol and Pascal, lexical scoping of functions. Nested functions are supported, but llvm-gcc does not support - taking the address of a nested function (except on the X86-32 target) + taking the address of a nested function (except on X86 targets) or non-local gotos.
  • Function Attributes: @@ -661,7 +709,8 @@ itself, Qt, Mozilla, etc.

      -
    • Exception handling only works well on the X86 and PowerPC targets.
      • +
    • Exception handling only works well on the X86 and PowerPC targets. +It works well for x86-64 darwin but not x86-64 linux.
    From sabre at nondot.org Sun Feb 10 11:52:06 2008 From: sabre at nondot.org (Chris Lattner) Date: Sun, 10 Feb 2008 17:52:06 -0000 Subject: [llvm-commits] [llvm] r46929 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <200802101752.m1AHq67p024451@zion.cs.uiuc.edu> Author: lattner Date: Sun Feb 10 11:52:05 2008 New Revision: 46929 URL: http://llvm.org/viewvc/llvm-project?rev=46929&view=rev Log: close an li tag Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=46929&r1=46928&r2=46929&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Sun Feb 10 11:52:05 2008 @@ -130,7 +130,7 @@ (GNAT) and Fortran (gfortran) front-ends. These front-ends should still be considered experimental however: see the list of known problems. The release binaries do not contain either front-end: they need to be built from -source (the Ada front-end only builds on x86-32 linux). +source (the Ada front-end only builds on x86-32 linux).
  • Dale contributed full support for long double on x86/x86-64 (where it is 80 bits) and on Darwin PPC/PPC64 (where it is 128 bits). In previous LLVM From sabre at nondot.org Sun Feb 10 12:11:49 2008 From: sabre at nondot.org (Chris Lattner) Date: Sun, 10 Feb 2008 12:11:49 -0600 Subject: [llvm-commits] CVS: llvm-www/www-index.html Message-ID: <200802101811.m1AIBnBA025053@zion.cs.uiuc.edu> Changes in directory llvm-www: www-index.html updated: 1.151 -> 1.152 --- Log message: link to all the tutorials. --- Diffs of the changes: (+2 -2) www-index.html | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm-www/www-index.html diff -u llvm-www/www-index.html:1.151 llvm-www/www-index.html:1.152 --- llvm-www/www-index.html:1.151 Thu Jan 24 02:12:47 2008 +++ llvm-www/www-index.html Sun Feb 10 12:10:42 2008 @@ -79,8 +79,8 @@
    Want to learn more?
    -

    If you'd like to learn more about LLVM, take a look at LLVM Tutorial and the extensive +

    If you'd like to learn more about LLVM, take a look at the LLVM Tutorials and the extensive documentation for LLVM. In particular, all of the tools distributed with LLVM are described in the LLVM Command Guide. If you're interested in what From gohman at apple.com Sun Feb 10 12:45:24 2008 From: gohman at apple.com (Dan Gohman) Date: Sun, 10 Feb 2008 18:45:24 -0000 Subject: [llvm-commits] [llvm] r46930 - in /llvm/trunk: Xcode/LLVM.xcodeproj/ docs/ include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/CellSPU/ lib/Target/IA64/ lib/Target/Mips/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/X86/ test/TableGen/ utils/TableGen/ win32/Target/ Message-ID: <200802101845.m1AIjSxP026087@zion.cs.uiuc.edu> Author: djg Date: Sun Feb 10 12:45:23 2008 New Revision: 46930 URL: http://llvm.org/viewvc/llvm-project?rev=46930&view=rev Log: Rename MRegisterInfo to TargetRegisterInfo. Added: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h - copied, changed from r46597, llvm/trunk/include/llvm/Target/MRegisterInfo.h llvm/trunk/lib/Target/TargetRegisterInfo.cpp - copied, changed from r46597, llvm/trunk/lib/Target/MRegisterInfo.cpp Removed: llvm/trunk/include/llvm/Target/MRegisterInfo.h llvm/trunk/lib/Target/MRegisterInfo.cpp Modified: llvm/trunk/Xcode/LLVM.xcodeproj/project.pbxproj llvm/trunk/docs/CodeGenerator.html llvm/trunk/docs/WritingAnLLVMBackend.html llvm/trunk/include/llvm/CodeGen/CallingConvLower.h llvm/trunk/include/llvm/CodeGen/LiveInterval.h llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h llvm/trunk/include/llvm/CodeGen/LiveVariables.h llvm/trunk/include/llvm/CodeGen/MachineFrameInfo.h llvm/trunk/include/llvm/CodeGen/MachineInstr.h llvm/trunk/include/llvm/CodeGen/MachineLocation.h llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h llvm/trunk/include/llvm/CodeGen/RegisterCoalescer.h llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h llvm/trunk/include/llvm/Target/TargetMachine.h llvm/trunk/lib/CodeGen/BranchFolding.cpp llvm/trunk/lib/CodeGen/DwarfWriter.cpp llvm/trunk/lib/CodeGen/LiveInterval.cpp llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp llvm/trunk/lib/CodeGen/LiveVariables.cpp llvm/trunk/lib/CodeGen/LowerSubregs.cpp llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp llvm/trunk/lib/CodeGen/MachineFunction.cpp llvm/trunk/lib/CodeGen/MachineInstr.cpp llvm/trunk/lib/CodeGen/MachineLICM.cpp llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp llvm/trunk/lib/CodeGen/MachineSink.cpp llvm/trunk/lib/CodeGen/PHIElimination.cpp llvm/trunk/lib/CodeGen/PhysRegTracker.h llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp llvm/trunk/lib/CodeGen/RegAllocBigBlock.cpp llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp llvm/trunk/lib/CodeGen/RegAllocLocal.cpp llvm/trunk/lib/CodeGen/RegAllocSimple.cpp llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp llvm/trunk/lib/CodeGen/RegisterScavenging.cpp llvm/trunk/lib/CodeGen/SelectionDAG/CallingConvLower.cpp llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp llvm/trunk/lib/CodeGen/VirtRegMap.cpp llvm/trunk/lib/CodeGen/VirtRegMap.h llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp llvm/trunk/lib/Target/ARM/ARMInstrInfo.h llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp llvm/trunk/lib/Target/ARM/ARMMachineFunctionInfo.h llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp llvm/trunk/lib/Target/ARM/ARMRegisterInfo.h llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td llvm/trunk/lib/Target/ARM/ARMTargetMachine.h llvm/trunk/lib/Target/Alpha/AlphaAsmPrinter.cpp llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.h llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h llvm/trunk/lib/Target/CellSPU/SPUAsmPrinter.cpp llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h llvm/trunk/lib/Target/IA64/IA64AsmPrinter.cpp llvm/trunk/lib/Target/IA64/IA64InstrInfo.h llvm/trunk/lib/Target/IA64/IA64RegisterInfo.cpp llvm/trunk/lib/Target/IA64/IA64RegisterInfo.h llvm/trunk/lib/Target/IA64/IA64TargetMachine.h llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp llvm/trunk/lib/Target/Mips/MipsInstrInfo.h llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h llvm/trunk/lib/Target/Mips/MipsTargetMachine.h llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h llvm/trunk/lib/Target/Sparc/SparcAsmPrinter.cpp llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h llvm/trunk/lib/Target/X86/X86ATTAsmPrinter.cpp llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.h llvm/trunk/lib/Target/X86/X86InstrInfo.h llvm/trunk/lib/Target/X86/X86IntelAsmPrinter.cpp llvm/trunk/lib/Target/X86/X86IntelAsmPrinter.h llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp llvm/trunk/lib/Target/X86/X86RegisterInfo.h llvm/trunk/lib/Target/X86/X86RegisterInfo.td llvm/trunk/lib/Target/X86/X86TargetMachine.h llvm/trunk/test/TableGen/TargetInstrInfo.td llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp llvm/trunk/win32/Target/Target.vcproj Modified: llvm/trunk/Xcode/LLVM.xcodeproj/project.pbxproj URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Xcode/LLVM.xcodeproj/project.pbxproj?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/Xcode/LLVM.xcodeproj/project.pbxproj (original) +++ llvm/trunk/Xcode/LLVM.xcodeproj/project.pbxproj Sun Feb 10 12:45:23 2008 @@ -689,7 +689,7 @@ DE66EF0B08ABEE5E00323D32 /* IA64TargetMachine.cpp */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.cpp.cpp; path = IA64TargetMachine.cpp; sourceTree = ""; }; DE66EF0C08ABEE5E00323D32 /* IA64TargetMachine.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = IA64TargetMachine.h; sourceTree = ""; }; DE66EF0E08ABEE5E00323D32 /* README */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path = README; sourceTree = ""; }; - DE66EF1008ABEE5E00323D32 /* MRegisterInfo.cpp */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.cpp.cpp; path = MRegisterInfo.cpp; sourceTree = ""; }; + DE66EF1008ABEE5E00323D32 /* TargetRegisterInfo.cpp */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.cpp.cpp; path = TargetRegisterInfo.cpp; sourceTree = ""; }; DE66F08A08ABEE6000323D32 /* Target.td */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = text; path = Target.td; sourceTree = ""; }; DE66F08B08ABEE6000323D32 /* TargetData.cpp */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.cpp.cpp; path = TargetData.cpp; sourceTree = ""; }; DE66F08C08ABEE6000323D32 /* TargetFrameInfo.cpp */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.cpp.cpp; path = TargetFrameInfo.cpp; sourceTree = ""; }; @@ -915,7 +915,7 @@ DE66F29C08ABF03200323D32 /* Program.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = Program.h; sourceTree = ""; }; DE66F29D08ABF03200323D32 /* Signals.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = Signals.h; sourceTree = ""; }; DE66F29E08ABF03200323D32 /* TimeValue.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = TimeValue.h; sourceTree = ""; }; - DE66F2A008ABF03200323D32 /* MRegisterInfo.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = MRegisterInfo.h; sourceTree = ""; }; + DE66F2A008ABF03200323D32 /* TargetRegisterInfo.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = TargetRegisterInfo.h; sourceTree = ""; }; DE66F2A108ABF03200323D32 /* TargetData.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = TargetData.h; sourceTree = ""; }; DE66F2A208ABF03200323D32 /* TargetFrameInfo.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = TargetFrameInfo.h; sourceTree = ""; }; DE66F2A308ABF03200323D32 /* TargetInstrInfo.h */ = {isa = PBXFileReference; fileEncoding = 30; lastKnownFileType = sourcecode.c.h; path = TargetInstrInfo.h; sourceTree = ""; }; @@ -1765,7 +1765,7 @@ DE66EF1108ABEE5E00323D32 /* PowerPC */, DE66EF7008ABEE5F00323D32 /* Sparc */, DE66F09308ABEE6000323D32 /* X86 */, - DE66EF1008ABEE5E00323D32 /* MRegisterInfo.cpp */, + DE66EF1008ABEE5E00323D32 /* TargetRegisterInfo.cpp */, CF9BCD1508C75070001E7011 /* SubtargetFeature.cpp */, DE66F08A08ABEE6000323D32 /* Target.td */, CF47BD860AAF487E00A8B13E /* TargetAsmInfo.cpp */, @@ -2445,7 +2445,7 @@ DE66F29F08ABF03200323D32 /* Target */ = { isa = PBXGroup; children = ( - DE66F2A008ABF03200323D32 /* MRegisterInfo.h */, + DE66F2A008ABF03200323D32 /* TargetRegisterInfo.h */, CF9BCD0808C74DE0001E7011 /* SubtargetFeature.h */, CF47BD380AAF40BC00A8B13E /* TargetAsmInfo.h */, DE66F2A108ABF03200323D32 /* TargetData.h */, Modified: llvm/trunk/docs/CodeGenerator.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CodeGenerator.html?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/docs/CodeGenerator.html (original) +++ llvm/trunk/docs/CodeGenerator.html Sun Feb 10 12:45:23 2008 @@ -26,7 +26,7 @@

  • The TargetMachine class
  • The TargetData class
  • The TargetLowering class
    • -
  • The MRegisterInfo class
    • +
  • The TargetRegisterInfo class
  • The TargetInstrInfo class
  • The TargetFrameInfo class
  • The TargetSubtarget class
    • @@ -388,14 +388,13 @@
    - The MRegisterInfo class + The TargetRegisterInfo class
    -

    The MRegisterInfo class (which will eventually be renamed to -TargetRegisterInfo) is used to describe the register file of the -target and any interactions between the registers.

    +

    The TargetRegisterInfo class is used to describe the register +file of the target and any interactions between the registers.

    Registers in the code generator are represented in the code generator by unsigned integers. Physical registers (those that actually exist in the target @@ -408,8 +407,8 @@ (used to indicate whether one register overlaps with another).

    -

    In addition to the per-register description, the MRegisterInfo class -exposes a set of processor specific register classes (instances of the +

    In addition to the per-register description, the TargetRegisterInfo +class exposes a set of processor specific register classes (instances of the TargetRegisterClass class). Each register class contains sets of registers that have the same properties (for example, they are all 32-bit integer registers). Each SSA virtual register created by the instruction @@ -1292,7 +1291,7 @@ marked as aliased in LLVM. Given a particular architecture, you can check which registers are aliased by inspecting its RegisterInfo.td file. Moreover, the method -MRegisterInfo::getAliasSet(p_reg) returns an array containing +TargetRegisterInfo::getAliasSet(p_reg) returns an array containing all the physical registers aliased to the register p_reg.

    Physical registers, in LLVM, are grouped in Register Classes. @@ -1310,7 +1309,7 @@ bool RegMapping_Fer::compatible_class(MachineFunction &mf, unsigned v_reg, unsigned p_reg) { - assert(MRegisterInfo::isPhysicalRegister(p_reg) && + assert(TargetRegisterInfo::isPhysicalRegister(p_reg) && "Target register must be physical"); const TargetRegisterClass *trc = mf.getRegInfo().getRegClass(v_reg); return trc->contains(p_reg); @@ -1335,9 +1334,9 @@ number. The smallest virtual register is normally assigned the number 1024. This may change, so, in order to know which is the first virtual register, you should access -MRegisterInfo::FirstVirtualRegister. Any register whose +TargetRegisterInfo::FirstVirtualRegister. Any register whose number is greater than or equal to -MRegisterInfo::FirstVirtualRegister is considered a virtual +TargetRegisterInfo::FirstVirtualRegister is considered a virtual register. Whereas physical registers are statically defined in a TargetRegisterInfo.td file and cannot be created by the application developer, that is not the case with virtual registers. @@ -1394,7 +1393,7 @@

    There are two ways to map virtual registers to physical registers (or to memory slots). The first way, that we will call direct mapping, -is based on the use of methods of the classes MRegisterInfo, +is based on the use of methods of the classes TargetRegisterInfo, and MachineOperand. The second way, that we will call indirect mapping, relies on the VirtRegMap class in order to insert loads and stores sending and getting values to and from @@ -1408,8 +1407,8 @@ memory. To assign a physical register to a virtual register present in a given operand, use MachineOperand::setReg(p_reg). To insert a store instruction, use -MRegisterInfo::storeRegToStackSlot(...), and to insert a load -instruction, use MRegisterInfo::loadRegFromStackSlot.

    +TargetRegisterInfo::storeRegToStackSlot(...), and to insert a load +instruction, use TargetRegisterInfo::loadRegFromStackSlot.

    The indirect mapping shields the application developer from the complexities of inserting load and store instructions. In order to map @@ -1529,7 +1528,7 @@

    Instructions can be folded with the -MRegisterInfo::foldMemoryOperand(...) method. Care must be +TargetRegisterInfo::foldMemoryOperand(...) method. Care must be taken when folding instructions; a folded instruction can be quite different from the original instruction. See LiveIntervals::addIntervalsForSpills in Modified: llvm/trunk/docs/WritingAnLLVMBackend.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/WritingAnLLVMBackend.html?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/docs/WritingAnLLVMBackend.html (original) +++ llvm/trunk/docs/WritingAnLLVMBackend.html Sun Feb 10 12:45:23 2008 @@ -74,7 +74,7 @@

  • Create a TableGen description of the register set and register classes
  • Implement a subclass of MRegisterInfo
    • + href="CodeGenerator.html#targetregisterinfo">TargetRegisterInfo
  • Describe the instruction set.
      Modified: llvm/trunk/include/llvm/CodeGen/CallingConvLower.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/CallingConvLower.h?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/CallingConvLower.h (original) +++ llvm/trunk/include/llvm/CodeGen/CallingConvLower.h Sun Feb 10 12:45:23 2008 @@ -19,7 +19,7 @@ #include "llvm/CodeGen/ValueTypes.h" namespace llvm { - class MRegisterInfo; + class TargetRegisterInfo; class TargetMachine; class CCState; class SDNode; @@ -107,7 +107,7 @@ unsigned CallingConv; bool IsVarArg; const TargetMachine &TM; - const MRegisterInfo &MRI; + const TargetRegisterInfo &TRI; SmallVector &Locs; unsigned StackOffset; Modified: llvm/trunk/include/llvm/CodeGen/LiveInterval.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveInterval.h?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/LiveInterval.h (original) +++ llvm/trunk/include/llvm/CodeGen/LiveInterval.h Sun Feb 10 12:45:23 2008 @@ -30,7 +30,7 @@ namespace llvm { class MachineInstr; - class MRegisterInfo; + class TargetRegisterInfo; struct LiveInterval; /// VNInfo - If the value number definition is undefined (e.g. phi @@ -346,9 +346,9 @@ return beginNumber() < other.beginNumber(); } - void print(std::ostream &OS, const MRegisterInfo *MRI = 0) const; - void print(std::ostream *OS, const MRegisterInfo *MRI = 0) const { - if (OS) print(*OS, MRI); + void print(std::ostream &OS, const TargetRegisterInfo *TRI = 0) const; + void print(std::ostream *OS, const TargetRegisterInfo *TRI = 0) const { + if (OS) print(*OS, TRI); } void dump() const; Modified: llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h (original) +++ llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h Sun Feb 10 12:45:23 2008 @@ -33,7 +33,7 @@ class LiveVariables; class MachineLoopInfo; - class MRegisterInfo; + class TargetRegisterInfo; class MachineRegisterInfo; class TargetInstrInfo; class TargetRegisterClass; @@ -43,7 +43,7 @@ class LiveIntervals : public MachineFunctionPass { MachineFunction* mf_; const TargetMachine* tm_; - const MRegisterInfo* mri_; + const TargetRegisterInfo* tri_; const TargetInstrInfo* tii_; LiveVariables* lv_; Modified: llvm/trunk/include/llvm/CodeGen/LiveVariables.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveVariables.h?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/LiveVariables.h (original) +++ llvm/trunk/include/llvm/CodeGen/LiveVariables.h Sun Feb 10 12:45:23 2008 @@ -37,7 +37,7 @@ namespace llvm { -class MRegisterInfo; +class TargetRegisterInfo; class LiveVariables : public MachineFunctionPass { public: @@ -130,7 +130,7 @@ private: // Intermediate data structures MachineFunction *MF; - const MRegisterInfo *RegInfo; + const TargetRegisterInfo *RegInfo; // PhysRegInfo - Keep track of which instruction was the last def/use of a // physical register. This is a purely local property, because all physical Modified: llvm/trunk/include/llvm/CodeGen/MachineFrameInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineFrameInfo.h?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineFrameInfo.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineFrameInfo.h Sun Feb 10 12:45:23 2008 @@ -159,8 +159,8 @@ /// MMI - This field is set (via setMachineModuleInfo) by a module info /// consumer (ex. DwarfWriter) to indicate that frame layout information /// should be acquired. Typically, it's the responsibility of the target's - /// MRegisterInfo prologue/epilogue emitting code to inform MachineModuleInfo - /// of frame layouts. + /// TargetRegisterInfo prologue/epilogue emitting code to inform + /// MachineModuleInfo of frame layouts. MachineModuleInfo *MMI; /// TargetFrameInfo - Target information about frame layout. @@ -328,8 +328,8 @@ CSInfo = CSI; } - /// getMachineModuleInfo - Used by a prologue/epilogue emitter (MRegisterInfo) - /// to provide frame layout information. + /// getMachineModuleInfo - Used by a prologue/epilogue + /// emitter (TargetRegisterInfo) to provide frame layout information. MachineModuleInfo *getMachineModuleInfo() const { return MMI; } /// setMachineModuleInfo - Used by a meta info consumer (DwarfWriter) to Modified: llvm/trunk/include/llvm/CodeGen/MachineInstr.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstr.h?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineInstr.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineInstr.h Sun Feb 10 12:45:23 2008 @@ -22,7 +22,7 @@ namespace llvm { class TargetInstrDesc; -class MRegisterInfo; +class TargetRegisterInfo; template struct ilist_traits; template struct ilist; @@ -167,19 +167,20 @@ /// operand that uses it and mark it as IsKill. If AddIfNotFound is true, /// add a implicit operand if it's not found. Returns true if the operand /// exists / is added. - bool addRegisterKilled(unsigned IncomingReg, const MRegisterInfo *RegInfo, + bool addRegisterKilled(unsigned IncomingReg, + const TargetRegisterInfo *RegInfo, bool AddIfNotFound = false); /// addRegisterDead - We have determined MI defined a register without a use. /// Look for the operand that defines it and mark it as IsDead. If /// AddIfNotFound is true, add a implicit operand if it's not found. Returns /// true if the operand exists / is added. - bool addRegisterDead(unsigned IncomingReg, const MRegisterInfo *RegInfo, + bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound = false); /// copyKillDeadInfo - copies killed/dead information from one instr to another void copyKillDeadInfo(MachineInstr *OldMI, - const MRegisterInfo *RegInfo); + const TargetRegisterInfo *RegInfo); // // Debugging support Modified: llvm/trunk/include/llvm/CodeGen/MachineLocation.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineLocation.h?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineLocation.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineLocation.h Sun Feb 10 12:45:23 2008 @@ -32,7 +32,7 @@ public: enum { // The target register number for an abstract frame pointer. The value is - // an arbitrary value greater than MRegisterInfo::FirstVirtualRegister. + // an arbitrary value greater than TargetRegisterInfo::FirstVirtualRegister. VirtualFP = ~0U }; MachineLocation() Modified: llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h Sun Feb 10 12:45:23 2008 @@ -14,7 +14,7 @@ #ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H #define LLVM_CODEGEN_MACHINEREGISTERINFO_H -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/ADT/BitVector.h" #include "llvm/ADT/iterator" #include @@ -26,7 +26,7 @@ class MachineRegisterInfo { /// VRegInfo - Information we keep for each virtual register. The entries in /// this vector are actually converted to vreg numbers by adding the - /// MRegisterInfo::FirstVirtualRegister delta to their index. + /// TargetRegisterInfo::FirstVirtualRegister delta to their index. /// /// Each element in this list contains the register class of the vreg and the /// start of the use/def list for the register. @@ -54,7 +54,7 @@ MachineRegisterInfo(const MachineRegisterInfo&); // DO NOT IMPLEMENT void operator=(const MachineRegisterInfo&); // DO NOT IMPLEMENT public: - explicit MachineRegisterInfo(const MRegisterInfo &MRI); + explicit MachineRegisterInfo(const TargetRegisterInfo &TRI); ~MachineRegisterInfo(); //===--------------------------------------------------------------------===// @@ -98,16 +98,16 @@ /// getRegUseDefListHead - Return the head pointer for the register use/def /// list for the specified virtual or physical register. MachineOperand *&getRegUseDefListHead(unsigned RegNo) { - if (RegNo < MRegisterInfo::FirstVirtualRegister) + if (RegNo < TargetRegisterInfo::FirstVirtualRegister) return PhysRegUseDefLists[RegNo]; - RegNo -= MRegisterInfo::FirstVirtualRegister; + RegNo -= TargetRegisterInfo::FirstVirtualRegister; return VRegInfo[RegNo].second; } MachineOperand *getRegUseDefListHead(unsigned RegNo) const { - if (RegNo < MRegisterInfo::FirstVirtualRegister) + if (RegNo < TargetRegisterInfo::FirstVirtualRegister) return PhysRegUseDefLists[RegNo]; - RegNo -= MRegisterInfo::FirstVirtualRegister; + RegNo -= TargetRegisterInfo::FirstVirtualRegister; return VRegInfo[RegNo].second; } @@ -117,7 +117,7 @@ /// getRegClass - Return the register class of the specified virtual register. const TargetRegisterClass *getRegClass(unsigned Reg) { - Reg -= MRegisterInfo::FirstVirtualRegister; + Reg -= TargetRegisterInfo::FirstVirtualRegister; assert(Reg < VRegInfo.size() && "Invalid vreg!"); return VRegInfo[Reg].first; } @@ -142,7 +142,7 @@ /// getLastVirtReg - Return the highest currently assigned virtual register. /// unsigned getLastVirtReg() const { - return VRegInfo.size()+MRegisterInfo::FirstVirtualRegister-1; + return VRegInfo.size()+TargetRegisterInfo::FirstVirtualRegister-1; } /// getVRegDef - Return the machine instr that defines the specified virtual Modified: llvm/trunk/include/llvm/CodeGen/RegisterCoalescer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/RegisterCoalescer.h?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/RegisterCoalescer.h (original) +++ llvm/trunk/include/llvm/CodeGen/RegisterCoalescer.h Sun Feb 10 12:45:23 2008 @@ -16,7 +16,7 @@ #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/LiveIntervalAnalysis.h" #include "llvm/CodeGen/LiveVariables.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Support/Debug.h" #ifndef LLVM_CODEGEN_REGISTER_COALESCER_H @@ -29,7 +29,7 @@ class AnalysisUsage; class LiveIntervals; class MachineInstr; - class MRegisterInfo; + class TargetRegisterInfo; /// An abstract interface for register coalescers. Coalescers must /// implement this interface to be part of the coalescer analysis Modified: llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h (original) +++ llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h Sun Feb 10 12:45:23 2008 @@ -22,7 +22,7 @@ namespace llvm { -class MRegisterInfo; +class TargetRegisterInfo; class TargetInstrInfo; class TargetRegisterClass; @@ -127,7 +127,7 @@ } private: - const MRegisterInfo *RegInfo; + const TargetRegisterInfo *RegInfo; const TargetInstrInfo *TII; /// CalleeSavedrRegs - A bitvector of callee saved registers for the target. Modified: llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h (original) +++ llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h Sun Feb 10 12:45:23 2008 @@ -28,7 +28,7 @@ class MachineModuleInfo; class MachineRegisterInfo; class MachineInstr; - class MRegisterInfo; + class TargetRegisterInfo; class SelectionDAG; class SelectionDAGISel; class TargetInstrInfo; @@ -243,7 +243,7 @@ MachineBasicBlock *BB; // Current basic block const TargetMachine &TM; // Target processor const TargetInstrInfo *TII; // Target instruction information - const MRegisterInfo *MRI; // Target processor register info + const TargetRegisterInfo *TRI; // Target processor register info MachineFunction *MF; // Machine function MachineRegisterInfo &RegInfo; // Virtual/real register map MachineConstantPool *ConstPool; // Target constant pool Removed: llvm/trunk/include/llvm/Target/MRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/MRegisterInfo.h?rev=46929&view=auto ============================================================================== --- llvm/trunk/include/llvm/Target/MRegisterInfo.h (original) +++ llvm/trunk/include/llvm/Target/MRegisterInfo.h (removed) @@ -1,612 +0,0 @@ -//===- Target/MRegisterInfo.h - Target Register Information -----*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file describes an abstract interface used to get information about a -// target machines register file. This information is used for a variety of -// purposed, especially register allocation. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_TARGET_MREGISTERINFO_H -#define LLVM_TARGET_MREGISTERINFO_H - -#include "llvm/ADT/SmallVector.h" -#include "llvm/CodeGen/MachineBasicBlock.h" -#include "llvm/CodeGen/ValueTypes.h" -#include -#include - -namespace llvm { - -class BitVector; -class MachineFunction; -class MachineInstr; -class MachineMove; -class RegScavenger; -class SDNode; -class SelectionDAG; -class TargetRegisterClass; -class Type; - -/// TargetRegisterDesc - This record contains all of the information known about -/// a particular register. The AliasSet field (if not null) contains a pointer -/// to a Zero terminated array of registers that this register aliases. This is -/// needed for architectures like X86 which have AL alias AX alias EAX. -/// Registers that this does not apply to simply should set this to null. -/// The SubRegs field is a zero terminated array of registers that are -/// sub-registers of the specific register, e.g. AL, AH are sub-registers of AX. -/// The ImmsubRegs field is a subset of SubRegs. It includes only the immediate -/// sub-registers. e.g. EAX has only one immediate sub-register of AX, not AH, -/// AL which are immediate sub-registers of AX. The SuperRegs field is a zero -/// terminated array of registers that are super-registers of the specific -/// register, e.g. RAX, EAX, are super-registers of AX. -/// -struct TargetRegisterDesc { - const char *Name; // Assembly language name for the register - const unsigned *AliasSet; // Register Alias Set, described above - const unsigned *SubRegs; // Sub-register set, described above - const unsigned *ImmSubRegs; // Immediate sub-register set, described above - const unsigned *SuperRegs; // Super-register set, described above -}; - -class TargetRegisterClass { -public: - typedef const unsigned* iterator; - typedef const unsigned* const_iterator; - - typedef const MVT::ValueType* vt_iterator; - typedef const TargetRegisterClass* const * sc_iterator; -private: - unsigned ID; - bool isSubClass; - const vt_iterator VTs; - const sc_iterator SubClasses; - const sc_iterator SuperClasses; - const sc_iterator SubRegClasses; - const sc_iterator SuperRegClasses; - const unsigned RegSize, Alignment; // Size & Alignment of register in bytes - const int CopyCost; - const iterator RegsBegin, RegsEnd; -public: - TargetRegisterClass(unsigned id, - const MVT::ValueType *vts, - const TargetRegisterClass * const *subcs, - const TargetRegisterClass * const *supcs, - const TargetRegisterClass * const *subregcs, - const TargetRegisterClass * const *superregcs, - unsigned RS, unsigned Al, int CC, - iterator RB, iterator RE) - : ID(id), VTs(vts), SubClasses(subcs), SuperClasses(supcs), - SubRegClasses(subregcs), SuperRegClasses(superregcs), - RegSize(RS), Alignment(Al), CopyCost(CC), RegsBegin(RB), RegsEnd(RE) {} - virtual ~TargetRegisterClass() {} // Allow subclasses - - /// getID() - Return the register class ID number. - /// - unsigned getID() const { return ID; } - - /// begin/end - Return all of the registers in this class. - /// - iterator begin() const { return RegsBegin; } - iterator end() const { return RegsEnd; } - - /// getNumRegs - Return the number of registers in this class. - /// - unsigned getNumRegs() const { return RegsEnd-RegsBegin; } - - /// getRegister - Return the specified register in the class. - /// - unsigned getRegister(unsigned i) const { - assert(i < getNumRegs() && "Register number out of range!"); - return RegsBegin[i]; - } - - /// contains - Return true if the specified register is included in this - /// register class. - bool contains(unsigned Reg) const { - for (iterator I = begin(), E = end(); I != E; ++I) - if (*I == Reg) return true; - return false; - } - - /// hasType - return true if this TargetRegisterClass has the ValueType vt. - /// - bool hasType(MVT::ValueType vt) const { - for(int i = 0; VTs[i] != MVT::Other; ++i) - if (VTs[i] == vt) - return true; - return false; - } - - /// vt_begin / vt_end - Loop over all of the value types that can be - /// represented by values in this register class. - vt_iterator vt_begin() const { - return VTs; - } - - vt_iterator vt_end() const { - vt_iterator I = VTs; - while (*I != MVT::Other) ++I; - return I; - } - - /// hasSubClass - return true if the specified TargetRegisterClass is a - /// sub-register class of this TargetRegisterClass. - bool hasSubClass(const TargetRegisterClass *cs) const { - for (int i = 0; SubClasses[i] != NULL; ++i) - if (SubClasses[i] == cs) - return true; - return false; - } - - /// subclasses_begin / subclasses_end - Loop over all of the sub-classes of - /// this register class. - sc_iterator subclasses_begin() const { - return SubClasses; - } - - sc_iterator subclasses_end() const { - sc_iterator I = SubClasses; - while (*I != NULL) ++I; - return I; - } - - /// hasSuperClass - return true if the specified TargetRegisterClass is a - /// super-register class of this TargetRegisterClass. - bool hasSuperClass(const TargetRegisterClass *cs) const { - for (int i = 0; SuperClasses[i] != NULL; ++i) - if (SuperClasses[i] == cs) - return true; - return false; - } - - /// superclasses_begin / superclasses_end - Loop over all of the super-classes - /// of this register class. - sc_iterator superclasses_begin() const { - return SuperClasses; - } - - sc_iterator superclasses_end() const { - sc_iterator I = SuperClasses; - while (*I != NULL) ++I; - return I; - } - - /// hasSubRegClass - return true if the specified TargetRegisterClass is a - /// class of a sub-register class for this TargetRegisterClass. - bool hasSubRegClass(const TargetRegisterClass *cs) const { - for (int i = 0; SubRegClasses[i] != NULL; ++i) - if (SubRegClasses[i] == cs) - return true; - return false; - } - - /// hasClassForSubReg - return true if the specified TargetRegisterClass is a - /// class of a sub-register class for this TargetRegisterClass. - bool hasClassForSubReg(unsigned SubReg) const { - --SubReg; - for (unsigned i = 0; SubRegClasses[i] != NULL; ++i) - if (i == SubReg) - return true; - return false; - } - - /// getClassForSubReg - return theTargetRegisterClass for the sub-register - /// at idx for this TargetRegisterClass. - sc_iterator getClassForSubReg(unsigned SubReg) const { - --SubReg; - for (unsigned i = 0; SubRegClasses[i] != NULL; ++i) - if (i == SubReg) - return &SubRegClasses[i]; - assert(0 && "Invalid subregister index for register class"); - return NULL; - } - - /// subregclasses_begin / subregclasses_end - Loop over all of - /// the subregister classes of this register class. - sc_iterator subregclasses_begin() const { - return SubRegClasses; - } - - sc_iterator subregclasses_end() const { - sc_iterator I = SubRegClasses; - while (*I != NULL) ++I; - return I; - } - - /// superregclasses_begin / superregclasses_end - Loop over all of - /// the superregister classes of this register class. - sc_iterator superregclasses_begin() const { - return SuperRegClasses; - } - - sc_iterator superregclasses_end() const { - sc_iterator I = SuperRegClasses; - while (*I != NULL) ++I; - return I; - } - - /// allocation_order_begin/end - These methods define a range of registers - /// which specify the registers in this class that are valid to register - /// allocate, and the preferred order to allocate them in. For example, - /// callee saved registers should be at the end of the list, because it is - /// cheaper to allocate caller saved registers. - /// - /// These methods take a MachineFunction argument, which can be used to tune - /// the allocatable registers based on the characteristics of the function. - /// One simple example is that the frame pointer register can be used if - /// frame-pointer-elimination is performed. - /// - /// By default, these methods return all registers in the class. - /// - virtual iterator allocation_order_begin(const MachineFunction &MF) const { - return begin(); - } - virtual iterator allocation_order_end(const MachineFunction &MF) const { - return end(); - } - - - - /// getSize - Return the size of the register in bytes, which is also the size - /// of a stack slot allocated to hold a spilled copy of this register. - unsigned getSize() const { return RegSize; } - - /// getAlignment - Return the minimum required alignment for a register of - /// this class. - unsigned getAlignment() const { return Alignment; } - - /// getCopyCost - Return the cost of copying a value between two registers in - /// this class. - int getCopyCost() const { return CopyCost; } -}; - - -/// MRegisterInfo base class - We assume that the target defines a static array -/// of TargetRegisterDesc objects that represent all of the machine registers -/// that the target has. As such, we simply have to track a pointer to this -/// array so that we can turn register number into a register descriptor. -/// -class MRegisterInfo { -public: - typedef const TargetRegisterClass * const * regclass_iterator; -private: - const TargetRegisterDesc *Desc; // Pointer to the descriptor array - unsigned NumRegs; // Number of entries in the array - - regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses - - int CallFrameSetupOpcode, CallFrameDestroyOpcode; -protected: - MRegisterInfo(const TargetRegisterDesc *D, unsigned NR, - regclass_iterator RegClassBegin, regclass_iterator RegClassEnd, - int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1); - virtual ~MRegisterInfo(); -public: - - enum { // Define some target independent constants - /// NoRegister - This physical register is not a real target register. It - /// is useful as a sentinal. - NoRegister = 0, - - /// FirstVirtualRegister - This is the first register number that is - /// considered to be a 'virtual' register, which is part of the SSA - /// namespace. This must be the same for all targets, which means that each - /// target is limited to 1024 registers. - FirstVirtualRegister = 1024 - }; - - /// isPhysicalRegister - Return true if the specified register number is in - /// the physical register namespace. - static bool isPhysicalRegister(unsigned Reg) { - assert(Reg && "this is not a register!"); - return Reg < FirstVirtualRegister; - } - - /// isVirtualRegister - Return true if the specified register number is in - /// the virtual register namespace. - static bool isVirtualRegister(unsigned Reg) { - assert(Reg && "this is not a register!"); - return Reg >= FirstVirtualRegister; - } - - /// getPhysicalRegisterRegClass - Returns the Register Class of a physical - /// register of the given type. - const TargetRegisterClass *getPhysicalRegisterRegClass(MVT::ValueType VT, - unsigned Reg) const; - - /// getAllocatableSet - Returns a bitset indexed by register number - /// indicating if a register is allocatable or not. If a register class is - /// specified, returns the subset for the class. - BitVector getAllocatableSet(MachineFunction &MF, - const TargetRegisterClass *RC = NULL) const; - - const TargetRegisterDesc &operator[](unsigned RegNo) const { - assert(RegNo < NumRegs && - "Attempting to access record for invalid register number!"); - return Desc[RegNo]; - } - - /// Provide a get method, equivalent to [], but more useful if we have a - /// pointer to this object. - /// - const TargetRegisterDesc &get(unsigned RegNo) const { - return operator[](RegNo); - } - - /// getAliasSet - Return the set of registers aliased by the specified - /// register, or a null list of there are none. The list returned is zero - /// terminated. - /// - const unsigned *getAliasSet(unsigned RegNo) const { - return get(RegNo).AliasSet; - } - - /// getSubRegisters - Return the set of registers that are sub-registers of - /// the specified register, or a null list of there are none. The list - /// returned is zero terminated. - /// - const unsigned *getSubRegisters(unsigned RegNo) const { - return get(RegNo).SubRegs; - } - - /// getImmediateSubRegisters - Return the set of registers that are immediate - /// sub-registers of the specified register, or a null list of there are none. - /// The list returned is zero terminated. - /// - const unsigned *getImmediateSubRegisters(unsigned RegNo) const { - return get(RegNo).ImmSubRegs; - } - - /// getSuperRegisters - Return the set of registers that are super-registers - /// of the specified register, or a null list of there are none. The list - /// returned is zero terminated. - /// - const unsigned *getSuperRegisters(unsigned RegNo) const { - return get(RegNo).SuperRegs; - } - - /// getName - Return the symbolic target specific name for the specified - /// physical register. - const char *getName(unsigned RegNo) const { - return get(RegNo).Name; - } - - /// getNumRegs - Return the number of registers this target has (useful for - /// sizing arrays holding per register information) - unsigned getNumRegs() const { - return NumRegs; - } - - /// areAliases - Returns true if the two registers alias each other, false - /// otherwise - bool areAliases(unsigned regA, unsigned regB) const { - for (const unsigned *Alias = getAliasSet(regA); *Alias; ++Alias) - if (*Alias == regB) return true; - return false; - } - - /// regsOverlap - Returns true if the two registers are equal or alias each - /// other. The registers may be virtual register. - bool regsOverlap(unsigned regA, unsigned regB) const { - if (regA == regB) - return true; - - if (isVirtualRegister(regA) || isVirtualRegister(regB)) - return false; - return areAliases(regA, regB); - } - - /// isSubRegister - Returns true if regB is a sub-register of regA. - /// - bool isSubRegister(unsigned regA, unsigned regB) const { - for (const unsigned *SR = getSubRegisters(regA); *SR; ++SR) - if (*SR == regB) return true; - return false; - } - - /// isSuperRegister - Returns true if regB is a super-register of regA. - /// - bool isSuperRegister(unsigned regA, unsigned regB) const { - for (const unsigned *SR = getSuperRegisters(regA); *SR; ++SR) - if (*SR == regB) return true; - return false; - } - - /// getCalleeSavedRegs - Return a null-terminated list of all of the - /// callee saved registers on this target. The register should be in the - /// order of desired callee-save stack frame offset. The first register is - /// closed to the incoming stack pointer if stack grows down, and vice versa. - virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0) - const = 0; - - /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred - /// register classes to spill each callee saved register with. The order and - /// length of this list match the getCalleeSaveRegs() list. - virtual const TargetRegisterClass* const *getCalleeSavedRegClasses( - const MachineFunction *MF) const =0; - - /// getReservedRegs - Returns a bitset indexed by physical register number - /// indicating if a register is a special register that has particular uses - /// and should be considered unavailable at all times, e.g. SP, RA. This is - /// used by register scavenger to determine what registers are free. - virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0; - - /// getSubReg - Returns the physical register number of sub-register "Index" - /// for physical register RegNo. - virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0; - - //===--------------------------------------------------------------------===// - // Register Class Information - // - - /// Register class iterators - /// - regclass_iterator regclass_begin() const { return RegClassBegin; } - regclass_iterator regclass_end() const { return RegClassEnd; } - - unsigned getNumRegClasses() const { - return regclass_end()-regclass_begin(); - } - - /// getRegClass - Returns the register class associated with the enumeration - /// value. See class TargetOperandInfo. - const TargetRegisterClass *getRegClass(unsigned i) const { - assert(i <= getNumRegClasses() && "Register Class ID out of range"); - return i ? RegClassBegin[i - 1] : NULL; - } - - //===--------------------------------------------------------------------===// - // Interfaces used by the register allocator and stack frame - // manipulation passes to move data around between registers, - // immediates and memory. FIXME: Move these to TargetInstrInfo.h. - // - - /// getCrossCopyRegClass - Returns a legal register class to copy a register - /// in the specified class to or from. Returns NULL if it is possible to copy - /// between a two registers of the specified class. - virtual const TargetRegisterClass * - getCrossCopyRegClass(const TargetRegisterClass *RC) const { - return NULL; - } - - /// reMaterialize - Re-issue the specified 'original' instruction at the - /// specific location targeting a new destination register. - virtual void reMaterialize(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - unsigned DestReg, - const MachineInstr *Orig) const = 0; - - /// targetHandlesStackFrameRounding - Returns true if the target is - /// responsible for rounding up the stack frame (probably at emitPrologue - /// time). - virtual bool targetHandlesStackFrameRounding() const { - return false; - } - - /// requiresRegisterScavenging - returns true if the target requires (and can - /// make use of) the register scavenger. - virtual bool requiresRegisterScavenging(const MachineFunction &MF) const { - return false; - } - - /// hasFP - Return true if the specified function should have a dedicated - /// frame pointer register. For most targets this is true only if the function - /// has variable sized allocas or if frame pointer elimination is disabled. - virtual bool hasFP(const MachineFunction &MF) const = 0; - - // hasReservedCallFrame - Under normal circumstances, when a frame pointer is - // not required, we reserve argument space for call sites in the function - // immediately on entry to the current function. This eliminates the need for - // add/sub sp brackets around call sites. Returns true if the call frame is - // included as part of the stack frame. - virtual bool hasReservedCallFrame(MachineFunction &MF) const { - return !hasFP(MF); - } - - /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the - /// frame setup/destroy instructions if they exist (-1 otherwise). Some - /// targets use pseudo instructions in order to abstract away the difference - /// between operating with a frame pointer and operating without, through the - /// use of these two instructions. - /// - int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; } - int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; } - - - /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog - /// code insertion to eliminate call frame setup and destroy pseudo - /// instructions (but only if the Target is using them). It is responsible - /// for eliminating these instructions, replacing them with concrete - /// instructions. This method need only be implemented if using call frame - /// setup/destroy pseudo instructions. - /// - virtual void - eliminateCallFramePseudoInstr(MachineFunction &MF, - MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI) const { - assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 && - "eliminateCallFramePseudoInstr must be implemented if using" - " call frame setup/destroy pseudo instructions!"); - assert(0 && "Call Frame Pseudo Instructions do not exist on this target!"); - } - - /// processFunctionBeforeCalleeSavedScan - This method is called immediately - /// before PrologEpilogInserter scans the physical registers used to determine - /// what callee saved registers should be spilled. This method is optional. - virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF, - RegScavenger *RS = NULL) const { - - } - - /// processFunctionBeforeFrameFinalized - This method is called immediately - /// before the specified functions frame layout (MF.getFrameInfo()) is - /// finalized. Once the frame is finalized, MO_FrameIndex operands are - /// replaced with direct constants. This method is optional. - /// - virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const { - } - - /// eliminateFrameIndex - This method must be overriden to eliminate abstract - /// frame indices from instructions which may use them. The instruction - /// referenced by the iterator contains an MO_FrameIndex operand which must be - /// eliminated by this method. This method may modify or replace the - /// specified instruction, as long as it keeps the iterator pointing the the - /// finished product. SPAdj is the SP adjustment due to call frame setup - /// instruction. The return value is the number of instructions added to - /// (negative if removed from) the basic block. - /// - virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, - int SPAdj, RegScavenger *RS=NULL) const = 0; - - /// emitProlog/emitEpilog - These methods insert prolog and epilog code into - /// the function. The return value is the number of instructions - /// added to (negative if removed from) the basic block (entry for prologue). - /// - virtual void emitPrologue(MachineFunction &MF) const = 0; - virtual void emitEpilogue(MachineFunction &MF, - MachineBasicBlock &MBB) const = 0; - - //===--------------------------------------------------------------------===// - /// Debug information queries. - - /// getDwarfRegNum - Map a target register to an equivalent dwarf register - /// number. Returns -1 if there is no equivalent value. The second - /// parameter allows targets to use different numberings for EH info and - /// deubgging info. - virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0; - - /// getFrameRegister - This method should return the register used as a base - /// for values allocated in the current stack frame. - virtual unsigned getFrameRegister(MachineFunction &MF) const = 0; - - /// getFrameIndexOffset - Returns the displacement from the frame register to - /// the stack frame of the specified index. - virtual int getFrameIndexOffset(MachineFunction &MF, int FI) const; - - /// getRARegister - This method should return the register where the return - /// address can be found. - virtual unsigned getRARegister() const = 0; - - /// getInitialFrameState - Returns a list of machine moves that are assumed - /// on entry to all functions. Note that LabelID is ignored (assumed to be - /// the beginning of the function.) - virtual void getInitialFrameState(std::vector &Moves) const; -}; - -// This is useful when building IndexedMaps keyed on virtual registers -struct VirtReg2IndexFunctor : std::unary_function { - unsigned operator()(unsigned Reg) const { - return Reg - MRegisterInfo::FirstVirtualRegister; - } -}; - -} // End llvm namespace - -#endif Modified: llvm/trunk/include/llvm/Target/TargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetMachine.h?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetMachine.h (original) +++ llvm/trunk/include/llvm/Target/TargetMachine.h Sun Feb 10 12:45:23 2008 @@ -28,7 +28,7 @@ class TargetLowering; class TargetFrameInfo; class MachineCodeEmitter; -class MRegisterInfo; +class TargetRegisterInfo; class Module; class FunctionPassManager; class PassManager; @@ -140,7 +140,7 @@ /// not, return null. This is kept separate from RegInfo until RegInfo has /// details of graph coloring register allocation removed from it. /// - virtual const MRegisterInfo *getRegisterInfo() const { return 0; } + virtual const TargetRegisterInfo *getRegisterInfo() const { return 0; } /// getJITInfo - If this target supports a JIT, return information for it, /// otherwise return null. Copied: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (from r46597, llvm/trunk/include/llvm/Target/MRegisterInfo.h) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?p2=llvm/trunk/include/llvm/Target/TargetRegisterInfo.h&p1=llvm/trunk/include/llvm/Target/MRegisterInfo.h&r1=46597&r2=46930&rev=46930&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/MRegisterInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Sun Feb 10 12:45:23 2008 @@ -1,4 +1,4 @@ -//===- Target/MRegisterInfo.h - Target Register Information -----*- C++ -*-===// +//=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -13,8 +13,8 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_TARGET_MREGISTERINFO_H -#define LLVM_TARGET_MREGISTERINFO_H +#ifndef LLVM_TARGET_TARGETREGISTERINFO_H +#define LLVM_TARGET_TARGETREGISTERINFO_H #include "llvm/ADT/SmallVector.h" #include "llvm/CodeGen/MachineBasicBlock.h" @@ -268,12 +268,13 @@ }; -/// MRegisterInfo base class - We assume that the target defines a static array -/// of TargetRegisterDesc objects that represent all of the machine registers -/// that the target has. As such, we simply have to track a pointer to this -/// array so that we can turn register number into a register descriptor. +/// TargetRegisterInfo base class - We assume that the target defines a static +/// array of TargetRegisterDesc objects that represent all of the machine +/// registers that the target has. As such, we simply have to track a pointer +/// to this array so that we can turn register number into a register +/// descriptor. /// -class MRegisterInfo { +class TargetRegisterInfo { public: typedef const TargetRegisterClass * const * regclass_iterator; private: @@ -284,10 +285,12 @@ int CallFrameSetupOpcode, CallFrameDestroyOpcode; protected: - MRegisterInfo(const TargetRegisterDesc *D, unsigned NR, - regclass_iterator RegClassBegin, regclass_iterator RegClassEnd, - int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1); - virtual ~MRegisterInfo(); + TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR, + regclass_iterator RegClassBegin, + regclass_iterator RegClassEnd, + int CallFrameSetupOpcode = -1, + int CallFrameDestroyOpcode = -1); + virtual ~TargetRegisterInfo(); public: enum { // Define some target independent constants @@ -588,7 +591,7 @@ /// getFrameIndexOffset - Returns the displacement from the frame register to /// the stack frame of the specified index. - virtual int getFrameIndexOffset(MachineFunction &MF, unsigned FI) const; + virtual int getFrameIndexOffset(MachineFunction &MF, int FI) const; /// getRARegister - This method should return the register where the return /// address can be found. @@ -603,7 +606,7 @@ // This is useful when building IndexedMaps keyed on virtual registers struct VirtReg2IndexFunctor : std::unary_function { unsigned operator()(unsigned Reg) const { - return Reg - MRegisterInfo::FirstVirtualRegister; + return Reg - TargetRegisterInfo::FirstVirtualRegister; } }; Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/BranchFolding.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/BranchFolding.cpp (original) +++ llvm/trunk/lib/CodeGen/BranchFolding.cpp Sun Feb 10 12:45:23 2008 @@ -24,7 +24,7 @@ #include "llvm/CodeGen/RegisterScavenging.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" #include "llvm/ADT/Statistic.h" @@ -72,7 +72,7 @@ MachineBasicBlock::iterator BBI1); std::vector > MergePotentials; - const MRegisterInfo *RegInfo; + const TargetRegisterInfo *RegInfo; RegScavenger *RS; // Branch optzn. bool OptimizeBranches(MachineFunction &MF); Modified: llvm/trunk/lib/CodeGen/DwarfWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DwarfWriter.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/DwarfWriter.cpp (original) +++ llvm/trunk/lib/CodeGen/DwarfWriter.cpp Sun Feb 10 12:45:23 2008 @@ -30,7 +30,7 @@ #include "llvm/Support/Mangler.h" #include "llvm/System/Path.h" #include "llvm/Target/TargetAsmInfo.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetFrameInfo.h" #include "llvm/Target/TargetInstrInfo.h" @@ -782,7 +782,7 @@ const TargetData *TD; /// RI - Register Information. - const MRegisterInfo *RI; + const TargetRegisterInfo *RI; /// M - Current module. /// Modified: llvm/trunk/lib/CodeGen/LiveInterval.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveInterval.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveInterval.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveInterval.cpp Sun Feb 10 12:45:23 2008 @@ -22,7 +22,7 @@ #include "llvm/ADT/SmallSet.h" #include "llvm/ADT/STLExtras.h" #include "llvm/Support/Streams.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include #include using namespace llvm; @@ -589,9 +589,10 @@ cerr << *this << "\n"; } -void LiveInterval::print(std::ostream &OS, const MRegisterInfo *MRI) const { - if (MRI && MRegisterInfo::isPhysicalRegister(reg)) - OS << MRI->getName(reg); +void LiveInterval::print(std::ostream &OS, + const TargetRegisterInfo *TRI) const { + if (TRI && TargetRegisterInfo::isPhysicalRegister(reg)) + OS << TRI->getName(reg); else OS << "%reg" << reg; Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Sun Feb 10 12:45:23 2008 @@ -25,7 +25,7 @@ #include "llvm/CodeGen/MachineLoopInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/Passes.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Support/CommandLine.h" @@ -100,10 +100,10 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) { mf_ = &fn; tm_ = &fn.getTarget(); - mri_ = tm_->getRegisterInfo(); + tri_ = tm_->getRegisterInfo(); tii_ = tm_->getInstrInfo(); lv_ = &getAnalysis(); - allocatableRegs_ = mri_->getAllocatableSet(fn); + allocatableRegs_ = tri_->getAllocatableSet(fn); // Number MachineInstrs and MachineBasicBlocks. // Initialize MBB indexes to a sentinal. @@ -134,7 +134,7 @@ DOUT << "********** INTERVALS **********\n"; for (iterator I = begin(), E = end(); I != E; ++I) { - I->second.print(DOUT, mri_); + I->second.print(DOUT, tri_); DOUT << "\n"; } @@ -147,7 +147,7 @@ void LiveIntervals::print(std::ostream &O, const Module* ) const { O << "********** INTERVALS **********\n"; for (const_iterator I = begin(), E = end(); I != E; ++I) { - I->second.print(DOUT, mri_); + I->second.print(DOUT, tri_); DOUT << "\n"; } @@ -188,12 +188,12 @@ unsigned PhysReg = mop.getReg(); if (PhysReg == 0 || PhysReg == li.reg) continue; - if (MRegisterInfo::isVirtualRegister(PhysReg)) { + if (TargetRegisterInfo::isVirtualRegister(PhysReg)) { if (!vrm.hasPhys(PhysReg)) continue; PhysReg = vrm.getPhys(PhysReg); } - if (PhysReg && mri_->regsOverlap(PhysReg, reg)) + if (PhysReg && tri_->regsOverlap(PhysReg, reg)) return true; } } @@ -203,8 +203,8 @@ } void LiveIntervals::printRegName(unsigned reg) const { - if (MRegisterInfo::isPhysicalRegister(reg)) - cerr << mri_->getName(reg); + if (TargetRegisterInfo::isPhysicalRegister(reg)) + cerr << tri_->getName(reg); else cerr << "%reg" << reg; } @@ -347,7 +347,7 @@ interval.addRange(LiveRange(RedefIndex, RedefIndex+1, OldValNo)); DOUT << " RESULT: "; - interval.print(DOUT, mri_); + interval.print(DOUT, tri_); } else { // Otherwise, this must be because of phi elimination. If this is the @@ -363,11 +363,11 @@ unsigned Start = getMBBStartIdx(Killer->getParent()); unsigned End = getUseIndex(getInstructionIndex(Killer))+1; DOUT << " Removing [" << Start << "," << End << "] from: "; - interval.print(DOUT, mri_); DOUT << "\n"; + interval.print(DOUT, tri_); DOUT << "\n"; interval.removeRange(Start, End); interval.addKill(VNI, Start); VNI->hasPHIKill = true; - DOUT << " RESULT: "; interval.print(DOUT, mri_); + DOUT << " RESULT: "; interval.print(DOUT, tri_); // Replace the interval with one of a NEW value number. Note that this // value number isn't actually defined by an instruction, weird huh? :) @@ -375,7 +375,7 @@ DOUT << " replace range with " << LR; interval.addRange(LR); interval.addKill(LR.valno, End); - DOUT << " RESULT: "; interval.print(DOUT, mri_); + DOUT << " RESULT: "; interval.print(DOUT, tri_); } // In the case of PHI elimination, each variable definition is only @@ -470,7 +470,7 @@ MachineBasicBlock::iterator MI, unsigned MIIdx, unsigned reg) { - if (MRegisterInfo::isVirtualRegister(reg)) + if (TargetRegisterInfo::isVirtualRegister(reg)) handleVirtualRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg)); else if (allocatableRegs_[reg]) { unsigned SrcReg, DstReg; @@ -480,7 +480,7 @@ SrcReg = 0; handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg), SrcReg); // Def of a register also defines its sub-registers. - for (const unsigned* AS = mri_->getSubRegisters(reg); *AS; ++AS) + for (const unsigned* AS = tri_->getSubRegisters(reg); *AS; ++AS) // Avoid processing some defs more than once. if (!MI->findRegisterDefOperand(*AS)) handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(*AS), 0); @@ -557,7 +557,7 @@ LE = MBB->livein_end(); LI != LE; ++LI) { handleLiveInRegister(MBB, MIIndex, getOrCreateInterval(*LI)); // Multiple live-ins can alias the same register. - for (const unsigned* AS = mri_->getSubRegisters(*LI); *AS; ++AS) + for (const unsigned* AS = tri_->getSubRegisters(*LI); *AS; ++AS) if (!hasInterval(*AS)) handleLiveInRegister(MBB, MIIndex, getOrCreateInterval(*AS), true); @@ -597,7 +597,7 @@ LiveInterval LiveIntervals::createInterval(unsigned reg) { - float Weight = MRegisterInfo::isPhysicalRegister(reg) ? + float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ? HUGE_VALF : 0.0F; return LiveInterval(reg, Weight); } @@ -717,7 +717,7 @@ if (lv_) lv_->instructionChanged(MI, fmi); else - fmi->copyKillDeadInfo(MI, mri_); + fmi->copyKillDeadInfo(MI, tri_); MachineBasicBlock &MBB = *MI->getParent(); if (isSS && !mf_->getFrameInfo()->isImmutableObjectIndex(Slot)) vrm.virtFolded(Reg, MI, fmi, (VirtRegMap::ModRef)MRInfo); @@ -789,7 +789,7 @@ continue; unsigned Reg = mop.getReg(); unsigned RegI = Reg; - if (Reg == 0 || MRegisterInfo::isPhysicalRegister(Reg)) + if (Reg == 0 || TargetRegisterInfo::isPhysicalRegister(Reg)) continue; if (Reg != li.reg) continue; @@ -840,7 +840,7 @@ if (!MOj.isRegister()) continue; unsigned RegJ = MOj.getReg(); - if (RegJ == 0 || MRegisterInfo::isPhysicalRegister(RegJ)) + if (RegJ == 0 || TargetRegisterInfo::isPhysicalRegister(RegJ)) continue; if (RegJ == RegI) { Ops.push_back(j); @@ -939,7 +939,7 @@ } DOUT << "\t\t\t\tAdded new interval: "; - nI.print(DOUT, mri_); + nI.print(DOUT, tri_); DOUT << '\n'; } return CanFold; @@ -1181,7 +1181,7 @@ "attempt to spill already spilled interval!"); DOUT << "\t\t\t\tadding intervals for spills for interval: "; - li.print(DOUT, mri_); + li.print(DOUT, tri_); DOUT << '\n'; // Each bit specify whether it a spill is required in the MBB. Modified: llvm/trunk/lib/CodeGen/LiveVariables.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveVariables.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveVariables.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveVariables.cpp Sun Feb 10 12:45:23 2008 @@ -29,7 +29,7 @@ #include "llvm/CodeGen/LiveVariables.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/ADT/DepthFirstIterator.h" @@ -60,9 +60,9 @@ } LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) { - assert(MRegisterInfo::isVirtualRegister(RegIdx) && + assert(TargetRegisterInfo::isVirtualRegister(RegIdx) && "getVarInfo: not a virtual register!"); - RegIdx -= MRegisterInfo::FirstVirtualRegister; + RegIdx -= TargetRegisterInfo::FirstVirtualRegister; if (RegIdx >= VirtRegInfo.size()) { if (RegIdx >= 2*VirtRegInfo.size()) VirtRegInfo.resize(RegIdx*2); @@ -80,8 +80,8 @@ MachineOperand &MO = MI->getOperand(i); if (MO.isRegister() && MO.isKill()) { if ((MO.getReg() == Reg) || - (MRegisterInfo::isPhysicalRegister(MO.getReg()) && - MRegisterInfo::isPhysicalRegister(Reg) && + (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && + TargetRegisterInfo::isPhysicalRegister(Reg) && RegInfo->isSubRegister(MO.getReg(), Reg))) return true; } @@ -94,8 +94,8 @@ MachineOperand &MO = MI->getOperand(i); if (MO.isRegister() && MO.isDead()) { if ((MO.getReg() == Reg) || - (MRegisterInfo::isPhysicalRegister(MO.getReg()) && - MRegisterInfo::isPhysicalRegister(Reg) && + (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && + TargetRegisterInfo::isPhysicalRegister(Reg) && RegInfo->isSubRegister(MO.getReg(), Reg))) return true; } @@ -399,7 +399,7 @@ // Mark live-in registers as live-in. for (MachineBasicBlock::const_livein_iterator II = MBB->livein_begin(), EE = MBB->livein_end(); II != EE; ++II) { - assert(MRegisterInfo::isPhysicalRegister(*II) && + assert(TargetRegisterInfo::isPhysicalRegister(*II) && "Cannot have a live-in virtual register!"); HandlePhysRegDef(*II, 0); } @@ -421,9 +421,9 @@ for (unsigned i = 0; i != NumOperandsToProcess; ++i) { MachineOperand &MO = MI->getOperand(i); if (MO.isRegister() && MO.isUse() && MO.getReg()) { - if (MRegisterInfo::isVirtualRegister(MO.getReg())){ + if (TargetRegisterInfo::isVirtualRegister(MO.getReg())){ HandleVirtRegUse(MO.getReg(), MBB, MI); - } else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) && + } else if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && !ReservedRegisters[MO.getReg()]) { HandlePhysRegUse(MO.getReg(), MI); } @@ -434,12 +434,12 @@ for (unsigned i = 0; i != NumOperandsToProcess; ++i) { MachineOperand &MO = MI->getOperand(i); if (MO.isRegister() && MO.isDef() && MO.getReg()) { - if (MRegisterInfo::isVirtualRegister(MO.getReg())) { + if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) { VarInfo &VRInfo = getVarInfo(MO.getReg()); if (VRInfo.AliveBlocks.none()) // If vr is not alive in any block, then defaults to dead. VRInfo.Kills.push_back(MI); - } else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) && + } else if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && !ReservedRegisters[MO.getReg()]) { HandlePhysRegDef(MO.getReg(), MI); } @@ -469,7 +469,7 @@ for (MachineRegisterInfo::liveout_iterator I = MF->getRegInfo().liveout_begin(), E = MF->getRegInfo().liveout_end(); I != E; ++I) { - assert(MRegisterInfo::isPhysicalRegister(*I) && + assert(TargetRegisterInfo::isPhysicalRegister(*I) && "Cannot have a live-in virtual register!"); HandlePhysRegUse(*I, Ret); // Add live-out registers as implicit uses. @@ -498,13 +498,13 @@ for (unsigned i = 0, e1 = VirtRegInfo.size(); i != e1; ++i) for (unsigned j = 0, e2 = VirtRegInfo[i].Kills.size(); j != e2; ++j) { if (VirtRegInfo[i].Kills[j] == MRI.getVRegDef(i + - MRegisterInfo::FirstVirtualRegister)) + TargetRegisterInfo::FirstVirtualRegister)) VirtRegInfo[i].Kills[j]->addRegisterDead(i + - MRegisterInfo::FirstVirtualRegister, + TargetRegisterInfo::FirstVirtualRegister, RegInfo); else VirtRegInfo[i].Kills[j]->addRegisterKilled(i + - MRegisterInfo::FirstVirtualRegister, + TargetRegisterInfo::FirstVirtualRegister, RegInfo); } @@ -536,7 +536,7 @@ for (unsigned i = 0, e = OldMI->getNumOperands(); i != e; ++i) { MachineOperand &MO = OldMI->getOperand(i); if (MO.isRegister() && MO.getReg() && - MRegisterInfo::isVirtualRegister(MO.getReg())) { + TargetRegisterInfo::isVirtualRegister(MO.getReg())) { unsigned Reg = MO.getReg(); VarInfo &VI = getVarInfo(Reg); if (MO.isDef()) { @@ -564,7 +564,7 @@ if (MO.isRegister() && MO.isKill()) { MO.setIsKill(false); unsigned Reg = MO.getReg(); - if (MRegisterInfo::isVirtualRegister(Reg)) { + if (TargetRegisterInfo::isVirtualRegister(Reg)) { bool removed = getVarInfo(Reg).removeKill(MI); assert(removed && "kill not in register's VarInfo?"); } @@ -580,7 +580,7 @@ if (MO.isRegister() && MO.isDead()) { MO.setIsDead(false); unsigned Reg = MO.getReg(); - if (MRegisterInfo::isVirtualRegister(Reg)) { + if (TargetRegisterInfo::isVirtualRegister(Reg)) { bool removed = getVarInfo(Reg).removeKill(MI); assert(removed && "kill not in register's VarInfo?"); } Modified: llvm/trunk/lib/CodeGen/LowerSubregs.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LowerSubregs.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LowerSubregs.cpp (original) +++ llvm/trunk/lib/CodeGen/LowerSubregs.cpp Sun Feb 10 12:45:23 2008 @@ -13,7 +13,7 @@ #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Support/Debug.h" @@ -46,13 +46,13 @@ // Returns the Register Class of a physical register. static const TargetRegisterClass *getPhysicalRegisterRegClass( - const MRegisterInfo &MRI, + const TargetRegisterInfo &TRI, unsigned reg) { - assert(MRegisterInfo::isPhysicalRegister(reg) && + assert(TargetRegisterInfo::isPhysicalRegister(reg) && "reg must be a physical register"); // Pick the register class of the right type that contains this physreg. - for (MRegisterInfo::regclass_iterator I = MRI.regclass_begin(), - E = MRI.regclass_end(); I != E; ++I) + for (TargetRegisterInfo::regclass_iterator I = TRI.regclass_begin(), + E = TRI.regclass_end(); I != E; ++I) if ((*I)->contains(reg)) return *I; assert(false && "Couldn't find the register class"); @@ -62,7 +62,7 @@ bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) { MachineBasicBlock *MBB = MI->getParent(); MachineFunction &MF = *MBB->getParent(); - const MRegisterInfo &MRI = *MF.getTarget().getRegisterInfo(); + const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo(); const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); assert(MI->getOperand(0).isRegister() && MI->getOperand(0).isDef() && @@ -72,21 +72,21 @@ unsigned SuperReg = MI->getOperand(1).getReg(); unsigned SubIdx = MI->getOperand(2).getImm(); - assert(MRegisterInfo::isPhysicalRegister(SuperReg) && + assert(TargetRegisterInfo::isPhysicalRegister(SuperReg) && "Extract supperg source must be a physical register"); - unsigned SrcReg = MRI.getSubReg(SuperReg, SubIdx); + unsigned SrcReg = TRI.getSubReg(SuperReg, SubIdx); unsigned DstReg = MI->getOperand(0).getReg(); DOUT << "subreg: CONVERTING: " << *MI; if (SrcReg != DstReg) { const TargetRegisterClass *TRC = 0; - if (MRegisterInfo::isPhysicalRegister(DstReg)) { - TRC = getPhysicalRegisterRegClass(MRI, DstReg); + if (TargetRegisterInfo::isPhysicalRegister(DstReg)) { + TRC = getPhysicalRegisterRegClass(TRI, DstReg); } else { TRC = MF.getRegInfo().getRegClass(DstReg); } - assert(TRC == getPhysicalRegisterRegClass(MRI, SrcReg) && + assert(TRC == getPhysicalRegisterRegClass(TRI, SrcReg) && "Extract subreg and Dst must be of same register class"); TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC, TRC); @@ -103,7 +103,7 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) { MachineBasicBlock *MBB = MI->getParent(); MachineFunction &MF = *MBB->getParent(); - const MRegisterInfo &MRI = *MF.getTarget().getRegisterInfo(); + const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo(); const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); unsigned DstReg = 0; unsigned SrcReg = 0; @@ -133,13 +133,13 @@ assert(0 && "Malformed extract_subreg"); assert(SubIdx != 0 && "Invalid index for extract_subreg"); - unsigned DstSubReg = MRI.getSubReg(DstReg, SubIdx); + unsigned DstSubReg = TRI.getSubReg(DstReg, SubIdx); - assert(MRegisterInfo::isPhysicalRegister(SrcReg) && + assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) && "Insert superreg source must be in a physical register"); - assert(MRegisterInfo::isPhysicalRegister(DstReg) && + assert(TargetRegisterInfo::isPhysicalRegister(DstReg) && "Insert destination must be in a physical register"); - assert(MRegisterInfo::isPhysicalRegister(InsReg) && + assert(TargetRegisterInfo::isPhysicalRegister(InsReg) && "Inserted value must be in a physical register"); DOUT << "subreg: CONVERTING: " << *MI; @@ -148,14 +148,14 @@ // of the destination, we copy the subreg into the source // However, this is only safe if the insert instruction is the kill // of the source register - bool revCopyOrder = MRI.isSubRegister(DstReg, InsReg); + bool revCopyOrder = TRI.isSubRegister(DstReg, InsReg); if (revCopyOrder && InsReg != DstSubReg) { if (MI->getOperand(1).isKill()) { - DstSubReg = MRI.getSubReg(SrcReg, SubIdx); + DstSubReg = TRI.getSubReg(SrcReg, SubIdx); // Insert sub-register copy const TargetRegisterClass *TRC1 = 0; - if (MRegisterInfo::isPhysicalRegister(InsReg)) { - TRC1 = getPhysicalRegisterRegClass(MRI, InsReg); + if (TargetRegisterInfo::isPhysicalRegister(InsReg)) { + TRC1 = getPhysicalRegisterRegClass(TRI, InsReg); } else { TRC1 = MF.getRegInfo().getRegClass(InsReg); } @@ -178,12 +178,12 @@ if (SrcReg != DstReg) { // Insert super-register copy const TargetRegisterClass *TRC0 = 0; - if (MRegisterInfo::isPhysicalRegister(DstReg)) { - TRC0 = getPhysicalRegisterRegClass(MRI, DstReg); + if (TargetRegisterInfo::isPhysicalRegister(DstReg)) { + TRC0 = getPhysicalRegisterRegClass(TRI, DstReg); } else { TRC0 = MF.getRegInfo().getRegClass(DstReg); } - assert(TRC0 == getPhysicalRegisterRegClass(MRI, SrcReg) && + assert(TRC0 == getPhysicalRegisterRegClass(TRI, SrcReg) && "Insert superreg and Dst must be of same register class"); TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC0, TRC0); @@ -203,8 +203,8 @@ if (!revCopyOrder && InsReg != DstSubReg) { // Insert sub-register copy const TargetRegisterClass *TRC1 = 0; - if (MRegisterInfo::isPhysicalRegister(InsReg)) { - TRC1 = getPhysicalRegisterRegClass(MRI, InsReg); + if (TargetRegisterInfo::isPhysicalRegister(InsReg)) { + TRC1 = getPhysicalRegisterRegClass(TRI, InsReg); } else { TRC1 = MF.getRegInfo().getRegClass(InsReg); } Modified: llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp Sun Feb 10 12:45:23 2008 @@ -14,7 +14,7 @@ #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/BasicBlock.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetInstrDesc.h" #include "llvm/Target/TargetMachine.h" @@ -143,10 +143,10 @@ } static inline void OutputReg(std::ostream &os, unsigned RegNo, - const MRegisterInfo *MRI = 0) { - if (!RegNo || MRegisterInfo::isPhysicalRegister(RegNo)) { - if (MRI) - os << " %" << MRI->get(RegNo).Name; + const TargetRegisterInfo *TRI = 0) { + if (!RegNo || TargetRegisterInfo::isPhysicalRegister(RegNo)) { + if (TRI) + os << " %" << TRI->get(RegNo).Name; else os << " %mreg(" << RegNo << ")"; } else @@ -169,11 +169,11 @@ if (isLandingPad()) OS << ", EH LANDING PAD"; OS << ":\n"; - const MRegisterInfo *MRI = MF->getTarget().getRegisterInfo(); + const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo(); if (!livein_empty()) { OS << "Live Ins:"; for (const_livein_iterator I = livein_begin(),E = livein_end(); I != E; ++I) - OutputReg(OS, *I, MRI); + OutputReg(OS, *I, TRI); OS << "\n"; } // Print the preds of this block according to the CFG. Modified: llvm/trunk/lib/CodeGen/MachineFunction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineFunction.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineFunction.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineFunction.cpp Sun Feb 10 12:45:23 2008 @@ -207,14 +207,14 @@ // Print Constant Pool getConstantPool()->print(OS); - const MRegisterInfo *MRI = getTarget().getRegisterInfo(); + const TargetRegisterInfo *TRI = getTarget().getRegisterInfo(); if (!RegInfo->livein_empty()) { OS << "Live Ins:"; for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(), E = RegInfo->livein_end(); I != E; ++I) { - if (MRI) - OS << " " << MRI->getName(I->first); + if (TRI) + OS << " " << TRI->getName(I->first); else OS << " Reg #" << I->first; @@ -227,8 +227,8 @@ OS << "Live Outs:"; for (MachineRegisterInfo::liveout_iterator I = RegInfo->liveout_begin(), E = RegInfo->liveout_end(); I != E; ++I) - if (MRI) - OS << " " << MRI->getName(*I); + if (TRI) + OS << " " << TRI->getName(*I); else OS << " Reg #" << *I; OS << "\n"; Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Sun Feb 10 12:45:23 2008 @@ -20,7 +20,7 @@ #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetInstrDesc.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Support/LeakDetector.h" #include "llvm/Support/Streams.h" #include @@ -159,7 +159,7 @@ void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const { switch (getType()) { case MachineOperand::MO_Register: - if (getReg() == 0 || MRegisterInfo::isVirtualRegister(getReg())) { + if (getReg() == 0 || TargetRegisterInfo::isVirtualRegister(getReg())) { OS << "%reg" << getReg(); } else { // If the instruction is embedded into a basic block, we can find the @@ -666,7 +666,7 @@ } bool MachineInstr::addRegisterKilled(unsigned IncomingReg, - const MRegisterInfo *RegInfo, + const TargetRegisterInfo *RegInfo, bool AddIfNotFound) { bool Found = false; for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { @@ -679,8 +679,8 @@ MO.setIsKill(); Found = true; break; - } else if (MRegisterInfo::isPhysicalRegister(Reg) && - MRegisterInfo::isPhysicalRegister(IncomingReg) && + } else if (TargetRegisterInfo::isPhysicalRegister(Reg) && + TargetRegisterInfo::isPhysicalRegister(IncomingReg) && RegInfo->isSuperRegister(IncomingReg, Reg) && MO.isKill()) // A super-register kill already exists. @@ -699,7 +699,7 @@ } bool MachineInstr::addRegisterDead(unsigned IncomingReg, - const MRegisterInfo *RegInfo, + const TargetRegisterInfo *RegInfo, bool AddIfNotFound) { bool Found = false; for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { @@ -712,8 +712,8 @@ MO.setIsDead(); Found = true; break; - } else if (MRegisterInfo::isPhysicalRegister(Reg) && - MRegisterInfo::isPhysicalRegister(IncomingReg) && + } else if (TargetRegisterInfo::isPhysicalRegister(Reg) && + TargetRegisterInfo::isPhysicalRegister(IncomingReg) && RegInfo->isSuperRegister(IncomingReg, Reg) && MO.isDead()) // There exists a super-register that's marked dead. @@ -734,13 +734,13 @@ /// copyKillDeadInfo - copies killed/dead information from one instr to another void MachineInstr::copyKillDeadInfo(MachineInstr *OldMI, - const MRegisterInfo *RegInfo) { + const TargetRegisterInfo *RegInfo) { // If the instruction defines any virtual registers, update the VarInfo, // kill and dead information for the instruction. for (unsigned i = 0, e = OldMI->getNumOperands(); i != e; ++i) { MachineOperand &MO = OldMI->getOperand(i); if (MO.isRegister() && MO.getReg() && - MRegisterInfo::isVirtualRegister(MO.getReg())) { + TargetRegisterInfo::isVirtualRegister(MO.getReg())) { unsigned Reg = MO.getReg(); if (MO.isDef()) { if (MO.isDead()) { Modified: llvm/trunk/lib/CodeGen/MachineLICM.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineLICM.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineLICM.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineLICM.cpp Sun Feb 10 12:45:23 2008 @@ -17,7 +17,7 @@ #include "llvm/CodeGen/MachineDominators.h" #include "llvm/CodeGen/MachineLoopInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/ADT/SmallVector.h" @@ -248,19 +248,19 @@ if (I.getDesc().getImplicitUses()) { DOUT << " * Instruction has implicit uses:\n"; - const MRegisterInfo *MRI = TM->getRegisterInfo(); + const TargetRegisterInfo *TRI = TM->getRegisterInfo(); for (const unsigned *ImpUses = I.getDesc().getImplicitUses(); *ImpUses; ++ImpUses) - DOUT << " -> " << MRI->getName(*ImpUses) << "\n"; + DOUT << " -> " << TRI->getName(*ImpUses) << "\n"; } if (I.getDesc().getImplicitDefs()) { DOUT << " * Instruction has implicit defines:\n"; - const MRegisterInfo *MRI = TM->getRegisterInfo(); + const TargetRegisterInfo *TRI = TM->getRegisterInfo(); for (const unsigned *ImpDefs = I.getDesc().getImplicitDefs(); *ImpDefs; ++ImpDefs) - DOUT << " -> " << MRI->getName(*ImpDefs) << "\n"; + DOUT << " -> " << TRI->getName(*ImpDefs) << "\n"; } //if (TII->hasUnmodelledSideEffects(&I)) @@ -277,7 +277,7 @@ unsigned Reg = MO.getReg(); // Don't hoist instructions that access physical registers. - if (!MRegisterInfo::isVirtualRegister(Reg)) + if (!TargetRegisterInfo::isVirtualRegister(Reg)) return false; assert(RegInfo->getVRegDef(Reg)&&"Machine instr not mapped for this vreg?"); Modified: llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp Sun Feb 10 12:45:23 2008 @@ -14,13 +14,13 @@ #include "llvm/CodeGen/MachineRegisterInfo.h" using namespace llvm; -MachineRegisterInfo::MachineRegisterInfo(const MRegisterInfo &MRI) { +MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) { VRegInfo.reserve(256); - UsedPhysRegs.resize(MRI.getNumRegs()); + UsedPhysRegs.resize(TRI.getNumRegs()); // Create the physreg use/def lists. - PhysRegUseDefLists = new MachineOperand*[MRI.getNumRegs()]; - memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*MRI.getNumRegs()); + PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()]; + memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs()); } MachineRegisterInfo::~MachineRegisterInfo() { @@ -64,7 +64,7 @@ /// register or null if none is found. This assumes that the code is in SSA /// form, so there should only be one definition. MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const { - assert(Reg-MRegisterInfo::FirstVirtualRegister < VRegInfo.size() && + assert(Reg-TargetRegisterInfo::FirstVirtualRegister < VRegInfo.size() && "Invalid vreg!"); for (reg_iterator I = reg_begin(Reg), E = reg_end(); I != E; ++I) { // Since we are in SSA form, we can stop at the first definition. Modified: llvm/trunk/lib/CodeGen/MachineSink.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineSink.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineSink.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineSink.cpp Sun Feb 10 12:45:23 2008 @@ -15,7 +15,7 @@ #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/MachineDominators.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/ADT/SmallVector.h" @@ -61,7 +61,8 @@ /// occur in blocks dominated by the specified block. bool MachineSinking::AllUsesDominatedByBlock(unsigned Reg, MachineBasicBlock *MBB) const { - assert(MRegisterInfo::isVirtualRegister(Reg) && "Only makes sense for vregs"); + assert(TargetRegisterInfo::isVirtualRegister(Reg) && + "Only makes sense for vregs"); for (MachineRegisterInfo::reg_iterator I = RegInfo->reg_begin(Reg), E = RegInfo->reg_end(); I != E; ++I) { if (I.getOperand().isDef()) continue; // ignore def. @@ -179,7 +180,7 @@ unsigned Reg = MO.getReg(); if (Reg == 0) continue; - if (MRegisterInfo::isPhysicalRegister(Reg)) { + if (TargetRegisterInfo::isPhysicalRegister(Reg)) { // If this is a physical register use, we can't move it. If it is a def, // we can move it, but only if the def is dead. if (MO.isUse() || !MO.isDead()) Modified: llvm/trunk/lib/CodeGen/PHIElimination.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PHIElimination.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PHIElimination.cpp (original) +++ llvm/trunk/lib/CodeGen/PHIElimination.cpp Sun Feb 10 12:45:23 2008 @@ -181,7 +181,7 @@ std::set MBBsInsertedInto; for (int i = MPhi->getNumOperands() - 1; i >= 2; i-=2) { unsigned SrcReg = MPhi->getOperand(i-1).getReg(); - assert(MRegisterInfo::isVirtualRegister(SrcReg) && + assert(TargetRegisterInfo::isVirtualRegister(SrcReg) && "Machine PHI Operands must all be virtual registers!"); // Get the MachineBasicBlock equivalent of the BasicBlock that is the Modified: llvm/trunk/lib/CodeGen/PhysRegTracker.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PhysRegTracker.h?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PhysRegTracker.h (original) +++ llvm/trunk/lib/CodeGen/PhysRegTracker.h Sun Feb 10 12:45:23 2008 @@ -17,52 +17,52 @@ #ifndef LLVM_CODEGEN_PHYSREGTRACKER_H #define LLVM_CODEGEN_PHYSREGTRACKER_H -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" namespace llvm { class PhysRegTracker { - const MRegisterInfo* mri_; + const TargetRegisterInfo* tri_; std::vector regUse_; public: - explicit PhysRegTracker(const MRegisterInfo& mri) - : mri_(&mri), - regUse_(mri_->getNumRegs(), 0) { + explicit PhysRegTracker(const TargetRegisterInfo& tri) + : tri_(&tri), + regUse_(tri_->getNumRegs(), 0) { } PhysRegTracker(const PhysRegTracker& rhs) - : mri_(rhs.mri_), + : tri_(rhs.tri_), regUse_(rhs.regUse_) { } const PhysRegTracker& operator=(const PhysRegTracker& rhs) { - mri_ = rhs.mri_; + tri_ = rhs.tri_; regUse_ = rhs.regUse_; return *this; } void addRegUse(unsigned physReg) { - assert(MRegisterInfo::isPhysicalRegister(physReg) && + assert(TargetRegisterInfo::isPhysicalRegister(physReg) && "should be physical register!"); ++regUse_[physReg]; - for (const unsigned* as = mri_->getAliasSet(physReg); *as; ++as) + for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as) ++regUse_[*as]; } void delRegUse(unsigned physReg) { - assert(MRegisterInfo::isPhysicalRegister(physReg) && + assert(TargetRegisterInfo::isPhysicalRegister(physReg) && "should be physical register!"); assert(regUse_[physReg] != 0); --regUse_[physReg]; - for (const unsigned* as = mri_->getAliasSet(physReg); *as; ++as) { + for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as) { assert(regUse_[*as] != 0); --regUse_[*as]; } } bool isRegAvail(unsigned physReg) const { - assert(MRegisterInfo::isPhysicalRegister(physReg) && + assert(TargetRegisterInfo::isPhysicalRegister(physReg) && "should be physical register!"); return regUse_[physReg] == 0; } Modified: llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp (original) +++ llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp Sun Feb 10 12:45:23 2008 @@ -24,7 +24,7 @@ #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/RegisterScavenging.h" #include "llvm/Target/TargetMachine.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetFrameInfo.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Support/Compiler.h" @@ -45,8 +45,8 @@ /// frame indexes with appropriate references. /// bool runOnMachineFunction(MachineFunction &Fn) { - const MRegisterInfo *MRI = Fn.getTarget().getRegisterInfo(); - RS = MRI->requiresRegisterScavenging(Fn) ? new RegScavenger() : NULL; + const TargetRegisterInfo *TRI = Fn.getTarget().getRegisterInfo(); + RS = TRI->requiresRegisterScavenging(Fn) ? new RegScavenger() : NULL; // Get MachineModuleInfo so that we can track the construction of the // frame. @@ -55,7 +55,7 @@ // Allow the target machine to make some adjustments to the function // e.g. UsedPhysRegs before calculateCalleeSavedRegisters. - MRI->processFunctionBeforeCalleeSavedScan(Fn, RS); + TRI->processFunctionBeforeCalleeSavedScan(Fn, RS); // Scan the function for modified callee saved registers and insert spill // code for any callee saved registers that are modified. Also calculate @@ -118,7 +118,7 @@ /// instructions. /// void PEI::calculateCalleeSavedRegisters(MachineFunction &Fn) { - const MRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo(); + const TargetRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo(); const TargetFrameInfo *TFI = Fn.getTarget().getFrameInfo(); // Get the callee saved register list... @@ -377,7 +377,7 @@ // Make sure the special register scavenging spill slot is closest to the // frame pointer if a frame pointer is required. - const MRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo(); + const TargetRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo(); if (RS && RegInfo->hasFP(Fn)) { int SFI = RS->getScavengingFrameIndex(); if (SFI >= 0) { @@ -500,12 +500,12 @@ const TargetMachine &TM = Fn.getTarget(); assert(TM.getRegisterInfo() && "TM::getRegisterInfo() must be implemented!"); - const MRegisterInfo &MRI = *TM.getRegisterInfo(); + const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); const TargetFrameInfo *TFI = TM.getFrameInfo(); bool StackGrowsDown = TFI->getStackGrowthDirection() == TargetFrameInfo::StackGrowsDown; - int FrameSetupOpcode = MRI.getCallFrameSetupOpcode(); - int FrameDestroyOpcode = MRI.getCallFrameDestroyOpcode(); + int FrameSetupOpcode = TRI.getCallFrameSetupOpcode(); + int FrameDestroyOpcode = TRI.getCallFrameDestroyOpcode(); for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { int SPAdj = 0; // SP offset due to call frame setup / destroy. @@ -522,7 +522,7 @@ Size = -Size; SPAdj += Size; MachineBasicBlock::iterator PrevI = prior(I); - MRI.eliminateCallFramePseudoInstr(Fn, *BB, I); + TRI.eliminateCallFramePseudoInstr(Fn, *BB, I); // Visit the instructions created by eliminateCallFramePseudoInstr(). I = next(PrevI); MI = NULL; @@ -535,7 +535,7 @@ if (MI->getOperand(i).isFrameIndex()) { // If this instruction has a FrameIndex operand, we need to use that // target machine register info object to eliminate it. - MRI.eliminateFrameIndex(MI, SPAdj, RS); + TRI.eliminateFrameIndex(MI, SPAdj, RS); // Revisit the instruction in full. Some instructions (e.g. inline // asm instructions) can have multiple frame indices. Modified: llvm/trunk/lib/CodeGen/RegAllocBigBlock.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocBigBlock.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocBigBlock.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocBigBlock.cpp Sun Feb 10 12:45:23 2008 @@ -95,7 +95,7 @@ /// RegInfo - For dealing with machine register info (aliases, folds /// etc) - const MRegisterInfo *RegInfo; + const TargetRegisterInfo *RegInfo; typedef SmallVector VRegTimes; @@ -152,8 +152,8 @@ /// markVirtRegModified - Lets us flip bits in the VirtRegModified bitset /// void markVirtRegModified(unsigned Reg, bool Val = true) { - assert(MRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!"); - Reg -= MRegisterInfo::FirstVirtualRegister; + assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!"); + Reg -= TargetRegisterInfo::FirstVirtualRegister; if (VirtRegModified.size() <= Reg) VirtRegModified.resize(Reg+1); VirtRegModified[Reg] = Val; @@ -162,10 +162,10 @@ /// isVirtRegModified - Lets us query the VirtRegModified bitset /// bool isVirtRegModified(unsigned Reg) const { - assert(MRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!"); - assert(Reg - MRegisterInfo::FirstVirtualRegister < VirtRegModified.size() + assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!"); + assert(Reg - TargetRegisterInfo::FirstVirtualRegister < VirtRegModified.size() && "Illegal virtual register!"); - return VirtRegModified[Reg - MRegisterInfo::FirstVirtualRegister]; + return VirtRegModified[Reg - TargetRegisterInfo::FirstVirtualRegister]; } public: @@ -562,7 +562,7 @@ MachineOperand& MO = MI->getOperand(i); // look for vreg reads.. if (MO.isRegister() && !MO.isDef() && MO.getReg() && - MRegisterInfo::isVirtualRegister(MO.getReg())) { + TargetRegisterInfo::isVirtualRegister(MO.getReg())) { // ..and add them to the read table. VRegTimes* &Times = VRegReadTable[MO.getReg()]; if(!VRegReadTable[MO.getReg()]) { @@ -675,7 +675,7 @@ MachineOperand& MO = MI->getOperand(i); // here we are looking for only used operands (never def&use) if (MO.isRegister() && !MO.isDef() && MO.getReg() && !MO.isImplicit() && - MRegisterInfo::isVirtualRegister(MO.getReg())) + TargetRegisterInfo::isVirtualRegister(MO.getReg())) MI = reloadVirtReg(MBB, MI, i); } @@ -686,7 +686,7 @@ for (unsigned i = 0, e = Kills.size(); i != e; ++i) { unsigned VirtReg = Kills[i]; unsigned PhysReg = VirtReg; - if (MRegisterInfo::isVirtualRegister(VirtReg)) { + if (TargetRegisterInfo::isVirtualRegister(VirtReg)) { // If the virtual register was never materialized into a register, it // might not be in the map, but it won't hurt to zero it out anyway. unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg); @@ -721,7 +721,7 @@ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand& MO = MI->getOperand(i); if (MO.isRegister() && MO.isDef() && !MO.isImplicit() && MO.getReg() && - MRegisterInfo::isPhysicalRegister(MO.getReg())) { + TargetRegisterInfo::isPhysicalRegister(MO.getReg())) { unsigned Reg = MO.getReg(); if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP. // These are extra physical register defs when a sub-register @@ -777,7 +777,7 @@ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand& MO = MI->getOperand(i); if (MO.isRegister() && MO.isDef() && MO.getReg() && - MRegisterInfo::isVirtualRegister(MO.getReg())) { + TargetRegisterInfo::isVirtualRegister(MO.getReg())) { unsigned DestVirtReg = MO.getReg(); unsigned DestPhysReg; @@ -796,7 +796,7 @@ for (unsigned i = 0, e = DeadDefs.size(); i != e; ++i) { unsigned VirtReg = DeadDefs[i]; unsigned PhysReg = VirtReg; - if (MRegisterInfo::isVirtualRegister(VirtReg)) { + if (TargetRegisterInfo::isVirtualRegister(VirtReg)) { unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg); PhysReg = PhysRegSlot; assert(PhysReg != 0); @@ -865,7 +865,7 @@ Virt2PhysRegMap.grow(MF->getRegInfo().getLastVirtReg()); StackSlotForVirtReg.grow(MF->getRegInfo().getLastVirtReg()); VirtRegModified.resize(MF->getRegInfo().getLastVirtReg() - - MRegisterInfo::FirstVirtualRegister + 1, 0); + TargetRegisterInfo::FirstVirtualRegister + 1, 0); // Loop over all of the basic blocks, eliminating virtual register references for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end(); Modified: llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Sun Feb 10 12:45:23 2008 @@ -23,7 +23,7 @@ #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/RegAllocRegistry.h" #include "llvm/CodeGen/RegisterCoalescer.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/ADT/EquivalenceClasses.h" @@ -62,7 +62,7 @@ MachineFunction* mf_; const TargetMachine* tm_; - const MRegisterInfo* mri_; + const TargetRegisterInfo* tri_; const TargetInstrInfo* tii_; MachineRegisterInfo *reginfo_; BitVector allocatableRegs_; @@ -161,10 +161,10 @@ for (; i != e; ++i) { DOUT << "\t" << *i->first << " -> "; unsigned reg = i->first->reg; - if (MRegisterInfo::isVirtualRegister(reg)) { + if (TargetRegisterInfo::isVirtualRegister(reg)) { reg = vrm_->getPhys(reg); } - DOUT << mri_->getName(reg) << '\n'; + DOUT << tri_->getName(reg) << '\n'; } } }; @@ -172,17 +172,17 @@ } void RALinScan::ComputeRelatedRegClasses() { - const MRegisterInfo &MRI = *mri_; + const TargetRegisterInfo &TRI = *tri_; // First pass, add all reg classes to the union, and determine at least one // reg class that each register is in. bool HasAliases = false; - for (MRegisterInfo::regclass_iterator RCI = MRI.regclass_begin(), - E = MRI.regclass_end(); RCI != E; ++RCI) { + for (TargetRegisterInfo::regclass_iterator RCI = TRI.regclass_begin(), + E = TRI.regclass_end(); RCI != E; ++RCI) { RelatedRegClasses.insert(*RCI); for (TargetRegisterClass::iterator I = (*RCI)->begin(), E = (*RCI)->end(); I != E; ++I) { - HasAliases = HasAliases || *MRI.getAliasSet(*I) != 0; + HasAliases = HasAliases || *TRI.getAliasSet(*I) != 0; const TargetRegisterClass *&PRC = OneClassForEachPhysReg[*I]; if (PRC) { @@ -202,7 +202,7 @@ for (std::map::iterator I = OneClassForEachPhysReg.begin(), E = OneClassForEachPhysReg.end(); I != E; ++I) - for (const unsigned *AS = MRI.getAliasSet(I->first); *AS; ++AS) + for (const unsigned *AS = TRI.getAliasSet(I->first); *AS; ++AS) RelatedRegClasses.unionSets(I->second, OneClassForEachPhysReg[*AS]); } @@ -224,7 +224,7 @@ unsigned SrcReg, DstReg; if (!CopyMI || !tii_->isMoveInstr(*CopyMI, SrcReg, DstReg)) return Reg; - if (MRegisterInfo::isVirtualRegister(SrcReg)) + if (TargetRegisterInfo::isVirtualRegister(SrcReg)) if (!vrm_->isAssignedReg(SrcReg)) return Reg; else @@ -238,7 +238,7 @@ // Try to coalesce. if (!li_->conflictsWithPhysRegDef(cur, *vrm_, SrcReg)) { - DOUT << "Coalescing: " << cur << " -> " << mri_->getName(SrcReg) << '\n'; + DOUT << "Coalescing: " << cur << " -> " << tri_->getName(SrcReg) << '\n'; vrm_->clearVirt(cur.reg); vrm_->assignVirt2Phys(cur.reg, SrcReg); ++NumCoalesce; @@ -251,10 +251,10 @@ bool RALinScan::runOnMachineFunction(MachineFunction &fn) { mf_ = &fn; tm_ = &fn.getTarget(); - mri_ = tm_->getRegisterInfo(); + tri_ = tm_->getRegisterInfo(); tii_ = tm_->getInstrInfo(); reginfo_ = &mf_->getRegInfo(); - allocatableRegs_ = mri_->getAllocatableSet(fn); + allocatableRegs_ = tri_->getAllocatableSet(fn); li_ = &getAnalysis(); loopInfo = &getAnalysis(); @@ -267,7 +267,7 @@ if (RelatedRegClasses.empty()) ComputeRelatedRegClasses(); - if (!prt_.get()) prt_.reset(new PhysRegTracker(*mri_)); + if (!prt_.get()) prt_.reset(new PhysRegTracker(*tri_)); vrm_.reset(new VirtRegMap(*mf_)); if (!spiller_.get()) spiller_.reset(createSpiller()); @@ -297,7 +297,7 @@ "interval sets should be empty on initialization"); for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) { - if (MRegisterInfo::isPhysicalRegister(i->second.reg)) { + if (TargetRegisterInfo::isPhysicalRegister(i->second.reg)) { reginfo_->setPhysRegUsed(i->second.reg); fixed_.push_back(std::make_pair(&i->second, i->second.begin())); } else @@ -323,7 +323,7 @@ processActiveIntervals(cur->beginNumber()); processInactiveIntervals(cur->beginNumber()); - assert(MRegisterInfo::isVirtualRegister(cur->reg) && + assert(TargetRegisterInfo::isVirtualRegister(cur->reg) && "Can only allocate virtual registers!"); // Allocating a virtual register. try to find a free @@ -340,7 +340,7 @@ IntervalPtr &IP = active_.back(); unsigned reg = IP.first->reg; DOUT << "\tinterval " << *IP.first << " expired\n"; - assert(MRegisterInfo::isVirtualRegister(reg) && + assert(TargetRegisterInfo::isVirtualRegister(reg) && "Can only allocate virtual registers!"); reg = vrm_->getPhys(reg); prt_->delRegUse(reg); @@ -359,7 +359,7 @@ for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) { LiveInterval &cur = i->second; unsigned Reg = 0; - bool isPhys = MRegisterInfo::isPhysicalRegister(cur.reg); + bool isPhys = TargetRegisterInfo::isPhysicalRegister(cur.reg); if (isPhys) Reg = i->second.reg; else if (vrm_->isAssignedReg(cur.reg)) @@ -399,7 +399,7 @@ if (IntervalPos == Interval->end()) { // Remove expired intervals. DOUT << "\t\tinterval " << *Interval << " expired\n"; - assert(MRegisterInfo::isVirtualRegister(reg) && + assert(TargetRegisterInfo::isVirtualRegister(reg) && "Can only allocate virtual registers!"); reg = vrm_->getPhys(reg); prt_->delRegUse(reg); @@ -412,7 +412,7 @@ } else if (IntervalPos->start > CurPoint) { // Move inactive intervals to inactive list. DOUT << "\t\tinterval " << *Interval << " inactive\n"; - assert(MRegisterInfo::isVirtualRegister(reg) && + assert(TargetRegisterInfo::isVirtualRegister(reg) && "Can only allocate virtual registers!"); reg = vrm_->getPhys(reg); prt_->delRegUse(reg); @@ -453,7 +453,7 @@ } else if (IntervalPos->start <= CurPoint) { // move re-activated intervals in active list DOUT << "\t\tinterval " << *Interval << " active\n"; - assert(MRegisterInfo::isVirtualRegister(reg) && + assert(TargetRegisterInfo::isVirtualRegister(reg) && "Can only allocate virtual registers!"); reg = vrm_->getPhys(reg); prt_->addRegUse(reg); @@ -475,9 +475,9 @@ /// register and its weight. static void updateSpillWeights(std::vector &Weights, unsigned reg, float weight, - const MRegisterInfo *MRI) { + const TargetRegisterInfo *TRI) { Weights[reg] += weight; - for (const unsigned* as = MRI->getAliasSet(reg); *as; ++as) + for (const unsigned* as = TRI->getAliasSet(reg); *as; ++as) Weights[*as] += weight; } @@ -525,7 +525,7 @@ unsigned SrcReg, DstReg; if (tii_->isMoveInstr(*CopyMI, SrcReg, DstReg)) { unsigned Reg = 0; - if (MRegisterInfo::isPhysicalRegister(SrcReg)) + if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) Reg = SrcReg; else if (vrm_->isAssignedReg(SrcReg)) Reg = vrm_->getPhys(SrcReg); @@ -540,7 +540,7 @@ for (IntervalPtrs::const_iterator i = inactive_.begin(), e = inactive_.end(); i != e; ++i) { unsigned Reg = i->first->reg; - assert(MRegisterInfo::isVirtualRegister(Reg) && + assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Can only allocate virtual registers!"); const TargetRegisterClass *RegRC = reginfo_->getRegClass(Reg); // If this is not in a related reg class to the register we're allocating, @@ -564,7 +564,7 @@ // conflict with it. Check to see if we conflict with it or any of its // aliases. SmallSet RegAliases; - for (const unsigned *AS = mri_->getAliasSet(physReg); *AS; ++AS) + for (const unsigned *AS = tri_->getAliasSet(physReg); *AS; ++AS) RegAliases.insert(*AS); bool ConflictsWithFixed = false; @@ -626,7 +626,7 @@ // the free physical register and add this interval to the active // list. if (physReg) { - DOUT << mri_->getName(physReg) << '\n'; + DOUT << tri_->getName(physReg) << '\n'; vrm_->assignVirt2Phys(cur->reg, physReg); prt_->addRegUse(physReg); active_.push_back(std::make_pair(cur, cur->begin())); @@ -636,19 +636,19 @@ DOUT << "no free registers\n"; // Compile the spill weights into an array that is better for scanning. - std::vector SpillWeights(mri_->getNumRegs(), 0.0); + std::vector SpillWeights(tri_->getNumRegs(), 0.0); for (std::vector >::iterator I = SpillWeightsToAdd.begin(), E = SpillWeightsToAdd.end(); I != E; ++I) - updateSpillWeights(SpillWeights, I->first, I->second, mri_); + updateSpillWeights(SpillWeights, I->first, I->second, tri_); // for each interval in active, update spill weights. for (IntervalPtrs::const_iterator i = active_.begin(), e = active_.end(); i != e; ++i) { unsigned reg = i->first->reg; - assert(MRegisterInfo::isVirtualRegister(reg) && + assert(TargetRegisterInfo::isVirtualRegister(reg) && "Can only allocate virtual registers!"); reg = vrm_->getPhys(reg); - updateSpillWeights(SpillWeights, reg, i->first->weight, mri_); + updateSpillWeights(SpillWeights, reg, i->first->weight, tri_); } DOUT << "\tassigning stack slot at interval "<< *cur << ":\n"; @@ -674,7 +674,7 @@ unsigned reg = *i; // No need to worry about if the alias register size < regsize of RC. // We are going to spill all registers that alias it anyway. - for (const unsigned* as = mri_->getAliasSet(reg); *as; ++as) { + for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as) { if (minWeight > SpillWeights[*as]) { minWeight = SpillWeights[*as]; minReg = *as; @@ -688,7 +688,7 @@ } DOUT << "\t\tregister with min weight: " - << mri_->getName(minReg) << " (" << minWeight << ")\n"; + << tri_->getName(minReg) << " (" << minWeight << ")\n"; // if the current has the minimum weight, we need to spill it and // add any added intervals back to unhandled, and restart @@ -719,13 +719,13 @@ // minimum weight, rollback to the interval with the earliest // start point and let the linear scan algorithm run again std::vector added; - assert(MRegisterInfo::isPhysicalRegister(minReg) && + assert(TargetRegisterInfo::isPhysicalRegister(minReg) && "did not choose a register to spill?"); - BitVector toSpill(mri_->getNumRegs()); + BitVector toSpill(tri_->getNumRegs()); // We are going to spill minReg and all its aliases. toSpill[minReg] = true; - for (const unsigned* as = mri_->getAliasSet(minReg); *as; ++as) + for (const unsigned* as = tri_->getAliasSet(minReg); *as; ++as) toSpill[*as] = true; // the earliest start of a spilled interval indicates up to where @@ -742,7 +742,7 @@ // mark our rollback point. for (IntervalPtrs::iterator i = active_.begin(); i != active_.end(); ++i) { unsigned reg = i->first->reg; - if (//MRegisterInfo::isVirtualRegister(reg) && + if (//TargetRegisterInfo::isVirtualRegister(reg) && toSpill[vrm_->getPhys(reg)] && cur->overlapsFrom(*i->first, i->second)) { DOUT << "\t\t\tspilling(a): " << *i->first << '\n'; @@ -755,7 +755,7 @@ } for (IntervalPtrs::iterator i = inactive_.begin(); i != inactive_.end(); ++i){ unsigned reg = i->first->reg; - if (//MRegisterInfo::isVirtualRegister(reg) && + if (//TargetRegisterInfo::isVirtualRegister(reg) && toSpill[vrm_->getPhys(reg)] && cur->overlapsFrom(*i->first, i->second-1)) { DOUT << "\t\t\tspilling(i): " << *i->first << '\n'; @@ -785,19 +785,19 @@ IntervalPtrs::iterator it; if ((it = FindIntervalInVector(active_, i)) != active_.end()) { active_.erase(it); - assert(!MRegisterInfo::isPhysicalRegister(i->reg)); + assert(!TargetRegisterInfo::isPhysicalRegister(i->reg)); if (!spilled.count(i->reg)) unhandled_.push(i); prt_->delRegUse(vrm_->getPhys(i->reg)); vrm_->clearVirt(i->reg); } else if ((it = FindIntervalInVector(inactive_, i)) != inactive_.end()) { inactive_.erase(it); - assert(!MRegisterInfo::isPhysicalRegister(i->reg)); + assert(!TargetRegisterInfo::isPhysicalRegister(i->reg)); if (!spilled.count(i->reg)) unhandled_.push(i); vrm_->clearVirt(i->reg); } else { - assert(MRegisterInfo::isVirtualRegister(i->reg) && + assert(TargetRegisterInfo::isVirtualRegister(i->reg) && "Can only allocate virtual registers!"); vrm_->clearVirt(i->reg); unhandled_.push(i); @@ -824,7 +824,7 @@ HI->expiredAt(cur->beginNumber())) { DOUT << "\t\t\tundo changes for: " << *HI << '\n'; active_.push_back(std::make_pair(HI, HI->begin())); - assert(!MRegisterInfo::isPhysicalRegister(HI->reg)); + assert(!TargetRegisterInfo::isPhysicalRegister(HI->reg)); prt_->addRegUse(vrm_->getPhys(HI->reg)); } } @@ -837,7 +837,7 @@ /// getFreePhysReg - return a free physical register for this virtual register /// interval if we have one, otherwise return 0. unsigned RALinScan::getFreePhysReg(LiveInterval *cur) { - std::vector inactiveCounts(mri_->getNumRegs(), 0); + std::vector inactiveCounts(tri_->getNumRegs(), 0); unsigned MaxInactiveCount = 0; const TargetRegisterClass *RC = reginfo_->getRegClass(cur->reg); @@ -846,7 +846,7 @@ for (IntervalPtrs::iterator i = inactive_.begin(), e = inactive_.end(); i != e; ++i) { unsigned reg = i->first->reg; - assert(MRegisterInfo::isVirtualRegister(reg) && + assert(TargetRegisterInfo::isVirtualRegister(reg) && "Can only allocate virtual registers!"); // If this is not in a related reg class to the register we're allocating, @@ -867,11 +867,11 @@ if (cur->preference) if (prt_->isRegAvail(cur->preference)) { DOUT << "\t\tassigned the preferred register: " - << mri_->getName(cur->preference) << "\n"; + << tri_->getName(cur->preference) << "\n"; return cur->preference; } else DOUT << "\t\tunable to assign the preferred register: " - << mri_->getName(cur->preference) << "\n"; + << tri_->getName(cur->preference) << "\n"; // Scan for the first available register. TargetRegisterClass::iterator I = RC->allocation_order_begin(*mf_); Modified: llvm/trunk/lib/CodeGen/RegAllocLocal.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocLocal.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocLocal.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocLocal.cpp Sun Feb 10 12:45:23 2008 @@ -49,7 +49,7 @@ private: const TargetMachine *TM; MachineFunction *MF; - const MRegisterInfo *MRI; + const TargetRegisterInfo *TRI; const TargetInstrInfo *TII; // StackSlotForVirtReg - Maps virtual regs to the frame index where these @@ -91,7 +91,7 @@ Virt2LastUseMap; std::pair& getVirtRegLastUse(unsigned Reg) { - assert(MRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!"); + assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!"); return Virt2LastUseMap[Reg]; } @@ -103,8 +103,8 @@ BitVector VirtRegModified; void markVirtRegModified(unsigned Reg, bool Val = true) { - assert(MRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!"); - Reg -= MRegisterInfo::FirstVirtualRegister; + assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!"); + Reg -= TargetRegisterInfo::FirstVirtualRegister; if (Val) VirtRegModified.set(Reg); else @@ -112,10 +112,10 @@ } bool isVirtRegModified(unsigned Reg) const { - assert(MRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!"); - assert(Reg - MRegisterInfo::FirstVirtualRegister < VirtRegModified.size() + assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!"); + assert(Reg - TargetRegisterInfo::FirstVirtualRegister < VirtRegModified.size() && "Illegal virtual register!"); - return VirtRegModified[Reg - MRegisterInfo::FirstVirtualRegister]; + return VirtRegModified[Reg - TargetRegisterInfo::FirstVirtualRegister]; } void AddToPhysRegsUseOrder(unsigned Reg) { @@ -167,7 +167,7 @@ /// bool areRegsEqual(unsigned R1, unsigned R2) const { if (R1 == R2) return true; - for (const unsigned *AliasSet = MRI->getAliasSet(R2); + for (const unsigned *AliasSet = TRI->getAliasSet(R2); *AliasSet; ++AliasSet) { if (*AliasSet == R1) return true; } @@ -286,7 +286,7 @@ assert(VirtReg && "Spilling a physical register is illegal!" " Must not have appropriate kill for the register or use exists beyond" " the intended one."); - DOUT << " Spilling register " << MRI->getName(PhysReg) + DOUT << " Spilling register " << TRI->getName(PhysReg) << " containing %reg" << VirtReg; const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo(); @@ -338,7 +338,7 @@ } else { // If the selected register aliases any other registers, we must make // sure that one of the aliases isn't alive. - for (const unsigned *AliasSet = MRI->getAliasSet(PhysReg); + for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg); *AliasSet; ++AliasSet) if (PhysRegsUsed[*AliasSet] != -1 && // Spill aliased register. PhysRegsUsed[*AliasSet] != -2) // If allocatable. @@ -371,7 +371,7 @@ // If the selected register aliases any other allocated registers, it is // not free! - for (const unsigned *AliasSet = MRI->getAliasSet(PhysReg); + for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg); *AliasSet; ++AliasSet) if (PhysRegsUsed[*AliasSet] != -1) // Aliased register in use? return false; // Can't use this reg then. @@ -434,7 +434,7 @@ } else { // If one of the registers aliased to the current register is // compatible, use it. - for (const unsigned *AliasIt = MRI->getAliasSet(R); + for (const unsigned *AliasIt = TRI->getAliasSet(R); *AliasIt; ++AliasIt) { if (RC->contains(*AliasIt) && // If this is pinned down for some reason, don't use it. For @@ -507,7 +507,7 @@ markVirtRegModified(VirtReg, false); // Note that this reg was just reloaded DOUT << " Reloading %reg" << VirtReg << " into " - << MRI->getName(PhysReg) << "\n"; + << TRI->getName(PhysReg) << "\n"; // Add move instruction(s) const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo(); @@ -561,7 +561,7 @@ MF->getRegInfo().setPhysRegUsed(Reg); PhysRegsUsed[Reg] = 0; // It is free and reserved now AddToPhysRegsUseOrder(Reg); - for (const unsigned *AliasSet = MRI->getSubRegisters(Reg); + for (const unsigned *AliasSet = TRI->getSubRegisters(Reg); *AliasSet; ++AliasSet) { if (PhysRegsUsed[*AliasSet] != -2) { AddToPhysRegsUseOrder(*AliasSet); @@ -578,9 +578,9 @@ const TargetInstrDesc &TID = MI->getDesc(); DEBUG(DOUT << "\nStarting RegAlloc of: " << *MI; DOUT << " Regs have values: "; - for (unsigned i = 0; i != MRI->getNumRegs(); ++i) + for (unsigned i = 0; i != TRI->getNumRegs(); ++i) if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2) - DOUT << "[" << MRI->getName(i) + DOUT << "[" << TRI->getName(i) << ",%reg" << PhysRegsUsed[i] << "] "; DOUT << "\n"); @@ -616,7 +616,7 @@ MachineOperand& MO = MI->getOperand(i); // here we are looking for only used operands (never def&use) if (MO.isRegister() && !MO.isDef() && MO.getReg() && !MO.isImplicit() && - MRegisterInfo::isVirtualRegister(MO.getReg())) + TargetRegisterInfo::isVirtualRegister(MO.getReg())) MI = reloadVirtReg(MBB, MI, i); } @@ -627,7 +627,7 @@ for (unsigned i = 0, e = Kills.size(); i != e; ++i) { unsigned VirtReg = Kills[i]; unsigned PhysReg = VirtReg; - if (MRegisterInfo::isVirtualRegister(VirtReg)) { + if (TargetRegisterInfo::isVirtualRegister(VirtReg)) { // If the virtual register was never materialized into a register, it // might not be in the map, but it won't hurt to zero it out anyway. unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg); @@ -642,14 +642,14 @@ } if (PhysReg) { - DOUT << " Last use of " << MRI->getName(PhysReg) + DOUT << " Last use of " << TRI->getName(PhysReg) << "[%reg" << VirtReg <<"], removing it from live set\n"; removePhysReg(PhysReg); - for (const unsigned *AliasSet = MRI->getSubRegisters(PhysReg); + for (const unsigned *AliasSet = TRI->getSubRegisters(PhysReg); *AliasSet; ++AliasSet) { if (PhysRegsUsed[*AliasSet] != -2) { DOUT << " Last use of " - << MRI->getName(*AliasSet) + << TRI->getName(*AliasSet) << "[%reg" << VirtReg <<"], removing it from live set\n"; removePhysReg(*AliasSet); } @@ -662,7 +662,7 @@ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand& MO = MI->getOperand(i); if (MO.isRegister() && MO.isDef() && !MO.isImplicit() && MO.getReg() && - MRegisterInfo::isPhysicalRegister(MO.getReg())) { + TargetRegisterInfo::isPhysicalRegister(MO.getReg())) { unsigned Reg = MO.getReg(); if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP. // These are extra physical register defs when a sub-register @@ -675,7 +675,7 @@ PhysRegsUsed[Reg] = 0; // It is free and reserved now AddToPhysRegsUseOrder(Reg); - for (const unsigned *AliasSet = MRI->getSubRegisters(Reg); + for (const unsigned *AliasSet = TRI->getSubRegisters(Reg); *AliasSet; ++AliasSet) { if (PhysRegsUsed[*AliasSet] != -2) { MF->getRegInfo().setPhysRegUsed(*AliasSet); @@ -697,7 +697,7 @@ PhysRegsUsed[Reg] = 0; // It is free and reserved now } MF->getRegInfo().setPhysRegUsed(Reg); - for (const unsigned *AliasSet = MRI->getSubRegisters(Reg); + for (const unsigned *AliasSet = TRI->getSubRegisters(Reg); *AliasSet; ++AliasSet) { if (PhysRegsUsed[*AliasSet] != -2) { AddToPhysRegsUseOrder(*AliasSet); @@ -723,7 +723,7 @@ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand& MO = MI->getOperand(i); if (MO.isRegister() && MO.isDef() && MO.getReg() && - MRegisterInfo::isVirtualRegister(MO.getReg())) { + TargetRegisterInfo::isVirtualRegister(MO.getReg())) { unsigned DestVirtReg = MO.getReg(); unsigned DestPhysReg; @@ -743,7 +743,7 @@ for (unsigned i = 0, e = DeadDefs.size(); i != e; ++i) { unsigned VirtReg = DeadDefs[i]; unsigned PhysReg = VirtReg; - if (MRegisterInfo::isVirtualRegister(VirtReg)) { + if (TargetRegisterInfo::isVirtualRegister(VirtReg)) { unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg); PhysReg = PhysRegSlot; assert(PhysReg != 0); @@ -754,14 +754,14 @@ } if (PhysReg) { - DOUT << " Register " << MRI->getName(PhysReg) + DOUT << " Register " << TRI->getName(PhysReg) << " [%reg" << VirtReg << "] is never used, removing it frame live list\n"; removePhysReg(PhysReg); - for (const unsigned *AliasSet = MRI->getAliasSet(PhysReg); + for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg); *AliasSet; ++AliasSet) { if (PhysRegsUsed[*AliasSet] != -2) { - DOUT << " Register " << MRI->getName(*AliasSet) + DOUT << " Register " << TRI->getName(*AliasSet) << " [%reg" << *AliasSet << "] is never used, removing it frame live list\n"; removePhysReg(*AliasSet); @@ -779,7 +779,7 @@ MachineBasicBlock::iterator MI = MBB.getFirstTerminator(); // Spill all physical registers holding virtual registers now. - for (unsigned i = 0, e = MRI->getNumRegs(); i != e; ++i) + for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2) if (unsigned VirtReg = PhysRegsUsed[i]) spillVirtReg(MBB, MI, VirtReg, i); @@ -789,7 +789,7 @@ #if 0 // This checking code is very expensive. bool AllOk = true; - for (unsigned i = MRegisterInfo::FirstVirtualRegister, + for (unsigned i = TargetRegisterInfo::FirstVirtualRegister, e = MF->getRegInfo().getLastVirtReg(); i <= e; ++i) if (unsigned PR = Virt2PhysRegMap[i]) { cerr << "Register still mapped: " << i << " -> " << PR << "\n"; @@ -811,16 +811,16 @@ DOUT << "Machine Function " << "\n"; MF = &Fn; TM = &Fn.getTarget(); - MRI = TM->getRegisterInfo(); + TRI = TM->getRegisterInfo(); TII = TM->getInstrInfo(); - PhysRegsUsed.assign(MRI->getNumRegs(), -1); + PhysRegsUsed.assign(TRI->getNumRegs(), -1); // At various places we want to efficiently check to see whether a register // is allocatable. To handle this, we mark all unallocatable registers as // being pinned down, permanently. { - BitVector Allocable = MRI->getAllocatableSet(Fn); + BitVector Allocable = TRI->getAllocatableSet(Fn); for (unsigned i = 0, e = Allocable.size(); i != e; ++i) if (!Allocable[i]) PhysRegsUsed[i] = -2; // Mark the reg unallocable. @@ -831,7 +831,7 @@ unsigned LastVirtReg = MF->getRegInfo().getLastVirtReg(); Virt2PhysRegMap.grow(LastVirtReg); Virt2LastUseMap.grow(LastVirtReg); - VirtRegModified.resize(LastVirtReg+1-MRegisterInfo::FirstVirtualRegister); + VirtRegModified.resize(LastVirtReg+1-TargetRegisterInfo::FirstVirtualRegister); // Loop over all of the basic blocks, eliminating virtual register references for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end(); Modified: llvm/trunk/lib/CodeGen/RegAllocSimple.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocSimple.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocSimple.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocSimple.cpp Sun Feb 10 12:45:23 2008 @@ -44,7 +44,7 @@ private: MachineFunction *MF; const TargetMachine *TM; - const MRegisterInfo *MRI; + const TargetRegisterInfo *TRI; // StackSlotForVirtReg - Maps SSA Regs => frame index on the stack where // these values are spilled @@ -169,7 +169,7 @@ // Made to combat the incorrect allocation of r2 = add r1, r1 std::map Virt2PhysRegMap; - RegsUsed.resize(MRI->getNumRegs()); + RegsUsed.resize(TRI->getNumRegs()); // This is a preliminary pass that will invalidate any registers that are // used by the instruction (including implicit uses). @@ -192,7 +192,7 @@ MachineOperand &op = MI->getOperand(i); if (op.isRegister() && op.getReg() && - MRegisterInfo::isVirtualRegister(op.getReg())) { + TargetRegisterInfo::isVirtualRegister(op.getReg())) { unsigned virtualReg = (unsigned) op.getReg(); DOUT << "op: " << op << "\n"; DOUT << "\t inst[" << i << "]: "; @@ -239,7 +239,7 @@ DOUT << "Machine Function\n"; MF = &Fn; TM = &MF->getTarget(); - MRI = TM->getRegisterInfo(); + TRI = TM->getRegisterInfo(); // Loop over all of the basic blocks, eliminating virtual register references for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end(); Modified: llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp (original) +++ llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp Sun Feb 10 12:45:23 2008 @@ -16,7 +16,7 @@ #include "llvm/CodeGen/RegisterCoalescer.h" #include "llvm/CodeGen/LiveIntervalAnalysis.h" #include "llvm/CodeGen/MachineInstr.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Pass.h" using namespace llvm; Modified: llvm/trunk/lib/CodeGen/RegisterScavenging.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterScavenging.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegisterScavenging.cpp (original) +++ llvm/trunk/lib/CodeGen/RegisterScavenging.cpp Sun Feb 10 12:45:23 2008 @@ -19,7 +19,7 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineInstr.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/ADT/STLExtras.h" Modified: llvm/trunk/lib/CodeGen/SelectionDAG/CallingConvLower.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/CallingConvLower.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/CallingConvLower.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/CallingConvLower.cpp Sun Feb 10 12:45:23 2008 @@ -14,7 +14,7 @@ #include "llvm/CodeGen/CallingConvLower.h" #include "llvm/CodeGen/SelectionDAGNodes.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetMachine.h" using namespace llvm; @@ -22,11 +22,11 @@ CCState::CCState(unsigned CC, bool isVarArg, const TargetMachine &tm, SmallVector &locs) : CallingConv(CC), IsVarArg(isVarArg), TM(tm), - MRI(*TM.getRegisterInfo()), Locs(locs) { + TRI(*TM.getRegisterInfo()), Locs(locs) { // No stack is used. StackOffset = 0; - UsedRegs.resize(MRI.getNumRegs()); + UsedRegs.resize(TRI.getNumRegs()); } // HandleByVal - Allocate a stack slot large enough to pass an argument by @@ -53,7 +53,7 @@ void CCState::MarkAllocated(unsigned Reg) { UsedRegs[Reg/32] |= 1 << (Reg&31); - if (const unsigned *RegAliases = MRI.getAliasSet(Reg)) + if (const unsigned *RegAliases = TRI.getAliasSet(Reg)) for (; (Reg = *RegAliases); ++RegAliases) UsedRegs[Reg/32] |= 1 << (Reg&31); } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Sun Feb 10 12:45:23 2008 @@ -32,7 +32,7 @@ : DAG(dag), BB(bb), TM(tm), RegInfo(BB->getParent()->getRegInfo()) { TII = TM.getInstrInfo(); MF = &DAG.getMachineFunction(); - MRI = TM.getRegisterInfo(); + TRI = TM.getRegisterInfo(); ConstPool = BB->getParent()->getConstantPool(); } @@ -40,14 +40,14 @@ /// a specified operand is a physical register dependency. If so, returns the /// register and the cost of copying the register. static void CheckForPhysRegDependency(SDNode *Def, SDNode *Use, unsigned Op, - const MRegisterInfo *MRI, + const TargetRegisterInfo *TRI, const TargetInstrInfo *TII, unsigned &PhysReg, int &Cost) { if (Op != 2 || Use->getOpcode() != ISD::CopyToReg) return; unsigned Reg = cast(Use->getOperand(1))->getReg(); - if (MRegisterInfo::isVirtualRegister(Reg)) + if (TargetRegisterInfo::isVirtualRegister(Reg)) return; unsigned ResNo = Use->getOperand(2).ResNo; @@ -57,7 +57,7 @@ II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) { PhysReg = Reg; const TargetRegisterClass *RC = - MRI->getPhysicalRegisterRegClass(Def->getValueType(ResNo), Reg); + TRI->getPhysicalRegisterRegClass(Def->getValueType(ResNo), Reg); Cost = RC->getCopyCost(); } } @@ -185,7 +185,7 @@ unsigned PhysReg = 0; int Cost = 1; // Determine if this is a physical register dependency. - CheckForPhysRegDependency(OpN, N, i, MRI, TII, PhysReg, Cost); + CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost); SU->addPred(OpSU, isChain, false, PhysReg, Cost); } } @@ -302,7 +302,7 @@ } static const TargetRegisterClass *getInstrOperandRegClass( - const MRegisterInfo *MRI, + const TargetRegisterInfo *TRI, const TargetInstrInfo *TII, const TargetInstrDesc &II, unsigned Op) { @@ -312,14 +312,14 @@ } if (II.OpInfo[Op].isLookupPtrRegClass()) return TII->getPointerRegClass(); - return MRI->getRegClass(II.OpInfo[Op].RegClass); + return TRI->getRegClass(II.OpInfo[Op].RegClass); } void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo, unsigned InstanceNo, unsigned SrcReg, DenseMap &VRBaseMap) { unsigned VRBase = 0; - if (MRegisterInfo::isVirtualRegister(SrcReg)) { + if (TargetRegisterInfo::isVirtualRegister(SrcReg)) { // Just use the input register directly! if (InstanceNo > 0) VRBaseMap.erase(SDOperand(Node, ResNo)); @@ -339,7 +339,7 @@ Use->getOperand(2).Val == Node && Use->getOperand(2).ResNo == ResNo) { unsigned DestReg = cast(Use->getOperand(1))->getReg(); - if (MRegisterInfo::isVirtualRegister(DestReg)) { + if (TargetRegisterInfo::isVirtualRegister(DestReg)) { VRBase = DestReg; Match = false; } else if (DestReg != SrcReg) @@ -364,7 +364,7 @@ if (VRBase) TRC = RegInfo.getRegClass(VRBase); else - TRC = MRI->getPhysicalRegisterRegClass(Node->getValueType(ResNo), SrcReg); + TRC = TRI->getPhysicalRegisterRegClass(Node->getValueType(ResNo), SrcReg); // If all uses are reading from the src physical register and copying the // register is either impossible or very expensive, then don't create a copy. @@ -398,7 +398,7 @@ Use->getOperand(2).Val == Node && Use->getOperand(2).ResNo == i) { unsigned Reg = cast(Use->getOperand(1))->getReg(); - if (MRegisterInfo::isVirtualRegister(Reg)) { + if (TargetRegisterInfo::isVirtualRegister(Reg)) { VRBase = Reg; MI->addOperand(MachineOperand::CreateReg(Reg, true)); break; @@ -409,7 +409,7 @@ // Create the result registers for this node and add the result regs to // the machine instruction. if (VRBase == 0) { - const TargetRegisterClass *RC = getInstrOperandRegClass(MRI, TII, II, i); + const TargetRegisterClass *RC = getInstrOperandRegClass(TRI, TII, II, i); assert(RC && "Isn't a register operand!"); VRBase = RegInfo.createVirtualRegister(RC); MI->addOperand(MachineOperand::CreateReg(VRBase, true)); @@ -453,10 +453,10 @@ MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef)); // Verify that it is right. - assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); + assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); if (II) { const TargetRegisterClass *RC = - getInstrOperandRegClass(MRI, TII, *II, IIOpNum); + getInstrOperandRegClass(TRI, TII, *II, IIOpNum); assert(RC && "Don't have operand info for this instruction!"); const TargetRegisterClass *VRC = RegInfo.getRegClass(VReg); if (VRC != RC) { @@ -517,10 +517,10 @@ MI->addOperand(MachineOperand::CreateReg(VReg, false)); // Verify that it is right. - assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); + assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); if (II) { const TargetRegisterClass *RC = - getInstrOperandRegClass(MRI, TII, *II, IIOpNum); + getInstrOperandRegClass(TRI, TII, *II, IIOpNum); assert(RC && "Don't have operand info for this instruction!"); assert(RegInfo.getRegClass(VReg) == RC && "Register class of operand and regclass of use don't agree!"); @@ -538,7 +538,8 @@ const TargetRegisterClass *TRC, unsigned SubIdx) { // Pick the register class of the subregister - MRegisterInfo::regclass_iterator I = TRC->subregclasses_begin() + SubIdx-1; + TargetRegisterInfo::regclass_iterator I = + TRC->subregclasses_begin() + SubIdx-1; assert(I < TRC->subregclasses_end() && "Invalid subregister index for register class"); return *I; @@ -549,7 +550,7 @@ unsigned SubIdx, MVT::ValueType VT) { // Pick the register class of the superegister for this type - for (MRegisterInfo::regclass_iterator I = TRC->superregclasses_begin(), + for (TargetRegisterInfo::regclass_iterator I = TRC->superregclasses_begin(), E = TRC->superregclasses_end(); I != E; ++I) if ((*I)->hasType(VT) && getSubRegisterRegClass(*I, SubIdx) == TRC) return *I; @@ -572,7 +573,7 @@ if (Use->getOpcode() == ISD::CopyToReg && Use->getOperand(2).Val == Node) { unsigned DestReg = cast(Use->getOperand(1))->getReg(); - if (MRegisterInfo::isVirtualRegister(DestReg)) { + if (TargetRegisterInfo::isVirtualRegister(DestReg)) { VRBase = DestReg; break; } @@ -638,7 +639,7 @@ if (Use->getOpcode() == ISD::CopyToReg && Use->getOperand(2).Val == Node) { unsigned DestReg = cast(Use->getOperand(1))->getReg(); - if (MRegisterInfo::isVirtualRegister(DestReg)) { + if (TargetRegisterInfo::isVirtualRegister(DestReg)) { VRBase = DestReg; break; } @@ -770,11 +771,11 @@ if (InReg != DestReg) {// Coalesced away the copy? const TargetRegisterClass *TRC = 0; // Get the target register class - if (MRegisterInfo::isVirtualRegister(InReg)) + if (TargetRegisterInfo::isVirtualRegister(InReg)) TRC = RegInfo.getRegClass(InReg); else TRC = - MRI->getPhysicalRegisterRegClass(Node->getOperand(2).getValueType(), + TRI->getPhysicalRegisterRegClass(Node->getOperand(2).getValueType(), InReg); TII->copyRegToReg(*BB, BB->end(), DestReg, InReg, TRC, TRC); } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Sun Feb 10 12:45:23 2008 @@ -22,7 +22,7 @@ #include "llvm/CodeGen/ScheduleDAG.h" #include "llvm/CodeGen/SchedulerRegistry.h" #include "llvm/CodeGen/SelectionDAGISel.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetInstrInfo.h" Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Sun Feb 10 12:45:23 2008 @@ -18,7 +18,7 @@ #define DEBUG_TYPE "pre-RA-sched" #include "llvm/CodeGen/ScheduleDAG.h" #include "llvm/CodeGen/SchedulerRegistry.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetInstrInfo.h" @@ -106,8 +106,8 @@ void ScheduleDAGRRList::Schedule() { DOUT << "********** List Scheduling **********\n"; - LiveRegDefs.resize(MRI->getNumRegs(), NULL); - LiveRegCycles.resize(MRI->getNumRegs(), 0); + LiveRegDefs.resize(TRI->getNumRegs(), NULL); + LiveRegCycles.resize(TRI->getNumRegs(), 0); // Build scheduling units. BuildSchedUnits(); @@ -651,7 +651,7 @@ if (RegAdded.insert(Reg)) LRegs.push_back(Reg); } - for (const unsigned *Alias = MRI->getAliasSet(Reg); + for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != I->Dep) { if (RegAdded.insert(*Alias)) @@ -672,7 +672,7 @@ if (RegAdded.insert(*Reg)) LRegs.push_back(*Reg); } - for (const unsigned *Alias = MRI->getAliasSet(*Reg); + for (const unsigned *Alias = TRI->getAliasSet(*Reg); *Alias; ++Alias) if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != SU) { if (RegAdded.insert(*Alias)) @@ -768,8 +768,8 @@ // Issue expensive cross register class copies. MVT::ValueType VT = getPhysicalRegisterVT(LRDef->Node, Reg, TII); const TargetRegisterClass *RC = - MRI->getPhysicalRegisterRegClass(VT, Reg); - const TargetRegisterClass *DestRC = MRI->getCrossCopyRegClass(RC); + TRI->getPhysicalRegisterRegClass(VT, Reg); + const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC); if (!DestRC) { assert(false && "Don't know how to copy this physical register!"); abort(); @@ -1063,11 +1063,11 @@ std::vector SethiUllmanNumbers; const TargetInstrInfo *TII; - const MRegisterInfo *MRI; + const TargetRegisterInfo *TRI; public: explicit BURegReductionPriorityQueue(const TargetInstrInfo *tii, - const MRegisterInfo *mri) - : TII(tii), MRI(mri) {} + const TargetRegisterInfo *tri) + : TII(tii), TRI(tri) {} void initNodes(DenseMap > &sumap, std::vector &sunits) { @@ -1320,7 +1320,7 @@ /// physical register def. static bool canClobberPhysRegDefs(SUnit *SuccSU, SUnit *SU, const TargetInstrInfo *TII, - const MRegisterInfo *MRI) { + const TargetRegisterInfo *TRI) { SDNode *N = SuccSU->Node; unsigned NumDefs = TII->get(N->getTargetOpcode()).getNumDefs(); const unsigned *ImpDefs = TII->get(N->getTargetOpcode()).getImplicitDefs(); @@ -1337,7 +1337,7 @@ unsigned Reg = ImpDefs[i - NumDefs]; for (;*SUImpDefs; ++SUImpDefs) { unsigned SUReg = *SUImpDefs; - if (MRI->regsOverlap(Reg, SUReg)) + if (TRI->regsOverlap(Reg, SUReg)) return true; } } @@ -1388,7 +1388,7 @@ // Don't constrain nodes with physical register defs if the // predecessor can clobber them. if (SuccSU->hasPhysRegDefs) { - if (canClobberPhysRegDefs(SuccSU, SU, TII, MRI)) + if (canClobberPhysRegDefs(SuccSU, SU, TII, TRI)) continue; } // Don't constraint extract_subreg / insert_subreg these may be @@ -1580,9 +1580,9 @@ SelectionDAG *DAG, MachineBasicBlock *BB) { const TargetInstrInfo *TII = DAG->getTarget().getInstrInfo(); - const MRegisterInfo *MRI = DAG->getTarget().getRegisterInfo(); + const TargetRegisterInfo *TRI = DAG->getTarget().getRegisterInfo(); return new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), true, - new BURegReductionPriorityQueue(TII, MRI)); + new BURegReductionPriorityQueue(TII, TRI)); } llvm::ScheduleDAG* llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Sun Feb 10 12:45:23 2008 @@ -23,7 +23,7 @@ #include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/PseudoSourceValue.h" #include "llvm/Support/MathExtras.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetLowering.h" #include "llvm/Target/TargetInstrInfo.h" @@ -4051,7 +4051,8 @@ cerr << LBB->getName() << " "; cerr << (const void*)BBDN->getBasicBlock() << ">"; } else if (const RegisterSDNode *R = dyn_cast(this)) { - if (G && R->getReg() && MRegisterInfo::isPhysicalRegister(R->getReg())) { + if (G && R->getReg() && + TargetRegisterInfo::isPhysicalRegister(R->getReg())) { cerr << " " <getTarget().getRegisterInfo()->getName(R->getReg()); } else { cerr << " #" << R->getReg(); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sun Feb 10 12:45:23 2008 @@ -35,7 +35,7 @@ #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/SchedulerRegistry.h" #include "llvm/CodeGen/SelectionDAG.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetFrameInfo.h" #include "llvm/Target/TargetInstrInfo.h" @@ -3148,11 +3148,12 @@ /// register class for the register. Otherwise, return null. static const TargetRegisterClass * isAllocatableRegister(unsigned Reg, MachineFunction &MF, - const TargetLowering &TLI, const MRegisterInfo *MRI) { + const TargetLowering &TLI, + const TargetRegisterInfo *TRI) { MVT::ValueType FoundVT = MVT::Other; const TargetRegisterClass *FoundRC = 0; - for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(), - E = MRI->regclass_end(); RCI != E; ++RCI) { + for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(), + E = TRI->regclass_end(); RCI != E; ++RCI) { MVT::ValueType ThisVT = MVT::Other; const TargetRegisterClass *RC = *RCI; @@ -3416,7 +3417,7 @@ OpInfo.ConstraintVT); } - const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo(); + const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); unsigned NumAllocated = 0; for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) { unsigned Reg = RegClassRegs[i]; @@ -3431,7 +3432,7 @@ // Check to see if this register is allocatable (i.e. don't give out the // stack pointer). if (RC == 0) { - RC = isAllocatableRegister(Reg, MF, TLI, MRI); + RC = isAllocatableRegister(Reg, MF, TLI, TRI); if (!RC) { // Couldn't allocate this register. // Reset NumAllocated to make sure we return consecutive registers. NumAllocated = 0; Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp Sun Feb 10 12:45:23 2008 @@ -18,7 +18,7 @@ #include "llvm/CodeGen/ScheduleDAG.h" #include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Support/GraphWriter.h" #include "llvm/ADT/StringExtras.h" @@ -132,7 +132,7 @@ //Op += " " + (const void*)BBDN->getBasicBlock(); } else if (const RegisterSDNode *R = dyn_cast(Node)) { if (G && R->getReg() != 0 && - MRegisterInfo::isPhysicalRegister(R->getReg())) { + TargetRegisterInfo::isPhysicalRegister(R->getReg())) { Op = Op + " " + G->getTarget().getRegisterInfo()->getName(R->getReg()); } else { Op += " #" + utostr(R->getReg()); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Sun Feb 10 12:45:23 2008 @@ -15,7 +15,7 @@ #include "llvm/Target/TargetSubtarget.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetMachine.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/DerivedTypes.h" #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/ADT/StringExtras.h" @@ -1614,8 +1614,8 @@ std::string RegName(Constraint.begin()+1, Constraint.end()-1); // Figure out which register class contains this reg. - const MRegisterInfo *RI = TM.getRegisterInfo(); - for (MRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), + const TargetRegisterInfo *RI = TM.getRegisterInfo(); + for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), E = RI->regclass_end(); RCI != E; ++RCI) { const TargetRegisterClass *RC = *RCI; Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original) +++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Sun Feb 10 12:45:23 2008 @@ -137,17 +137,17 @@ // If a live interval is a physical register, conservatively check if any // of its sub-registers is overlapping the live interval of the virtual // register. If so, do not coalesce. - if (MRegisterInfo::isPhysicalRegister(IntB.reg) && - *mri_->getSubRegisters(IntB.reg)) { - for (const unsigned* SR = mri_->getSubRegisters(IntB.reg); *SR; ++SR) + if (TargetRegisterInfo::isPhysicalRegister(IntB.reg) && + *tri_->getSubRegisters(IntB.reg)) { + for (const unsigned* SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) if (li_->hasInterval(*SR) && IntA.overlaps(li_->getInterval(*SR))) { DOUT << "Interfere with sub-register "; - DEBUG(li_->getInterval(*SR).print(DOUT, mri_)); + DEBUG(li_->getInterval(*SR).print(DOUT, tri_)); return false; } } - DOUT << "\nExtending: "; IntB.print(DOUT, mri_); + DOUT << "\nExtending: "; IntB.print(DOUT, tri_); unsigned FillerStart = ValLR->end, FillerEnd = BLR->start; // We are about to delete CopyMI, so need to remove it as the 'instruction @@ -163,9 +163,9 @@ // If the IntB live range is assigned to a physical register, and if that // physreg has aliases, - if (MRegisterInfo::isPhysicalRegister(IntB.reg)) { + if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) { // Update the liveintervals of sub-registers. - for (const unsigned *AS = mri_->getSubRegisters(IntB.reg); *AS; ++AS) { + for (const unsigned *AS = tri_->getSubRegisters(IntB.reg); *AS; ++AS) { LiveInterval &AliasLI = li_->getInterval(*AS); AliasLI.addRange(LiveRange(FillerStart, FillerEnd, AliasLI.getNextValue(FillerStart, 0, li_->getVNInfoAllocator()))); @@ -175,7 +175,7 @@ // Okay, merge "B1" into the same value number as "B0". if (BValNo != ValLR->valno) IntB.MergeValueNumberInto(BValNo, ValLR->valno); - DOUT << " result = "; IntB.print(DOUT, mri_); + DOUT << " result = "; IntB.print(DOUT, tri_); DOUT << "\n"; // If the source instruction was killing the source register before the @@ -249,8 +249,8 @@ return false; // Not coalescable. } - bool SrcIsPhys = MRegisterInfo::isPhysicalRegister(repSrcReg); - bool DstIsPhys = MRegisterInfo::isPhysicalRegister(repDstReg); + bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(repSrcReg); + bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(repDstReg); // If they are both physical registers, we cannot join them. if (SrcIsPhys && DstIsPhys) { @@ -275,15 +275,15 @@ if (SrcIsPhys) // r1024 = EXTRACT_SUBREG EAX, 0 then r1024 is really going to be // coalesced with AX. - repSrcReg = mri_->getSubReg(repSrcReg, SubIdx); + repSrcReg = tri_->getSubReg(repSrcReg, SubIdx); else if (DstIsPhys) { // If this is a extract_subreg where dst is a physical register, e.g. // cl = EXTRACT_SUBREG reg1024, 1 // then create and update the actual physical register allocated to RHS. const TargetRegisterClass *RC=mf_->getRegInfo().getRegClass(repSrcReg); - for (const unsigned *SRs = mri_->getSuperRegisters(repDstReg); + for (const unsigned *SRs = tri_->getSuperRegisters(repDstReg); unsigned SR = *SRs; ++SRs) { - if (repDstReg == mri_->getSubReg(SR, SubIdx) && + if (repDstReg == tri_->getSubReg(SR, SubIdx) && RC->contains(SR)) { RealDstReg = SR; break; @@ -298,13 +298,13 @@ if (li_->hasInterval(RealDstReg) && RHS.overlaps(li_->getInterval(RealDstReg))) { DOUT << "Interfere with register "; - DEBUG(li_->getInterval(RealDstReg).print(DOUT, mri_)); + DEBUG(li_->getInterval(RealDstReg).print(DOUT, tri_)); return false; // Not coalescable } - for (const unsigned* SR = mri_->getSubRegisters(RealDstReg); *SR; ++SR) + for (const unsigned* SR = tri_->getSubRegisters(RealDstReg); *SR; ++SR) if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) { DOUT << "Interfere with sub-register "; - DEBUG(li_->getInterval(*SR).print(DOUT, mri_)); + DEBUG(li_->getInterval(*SR).print(DOUT, tri_)); return false; // Not coalescable } } else { @@ -340,8 +340,8 @@ assert(SrcInt.reg == repSrcReg && DstInt.reg == repDstReg && "Register mapping is horribly broken!"); - DOUT << "\t\tInspecting "; SrcInt.print(DOUT, mri_); - DOUT << " and "; DstInt.print(DOUT, mri_); + DOUT << "\t\tInspecting "; SrcInt.print(DOUT, tri_); + DOUT << " and "; DstInt.print(DOUT, tri_); DOUT << ": "; // Check if it is necessary to propagate "isDead" property before intervals @@ -421,7 +421,7 @@ if (isDead) { // Result of the copy is dead. Propagate this property. if (SrcStart == 0) { - assert(MRegisterInfo::isPhysicalRegister(repSrcReg) && + assert(TargetRegisterInfo::isPhysicalRegister(repSrcReg) && "Live-in must be a physical register!"); // Live-in to the function but dead. Remove it from entry live-in set. // JoinIntervals may end up swapping the two intervals. @@ -462,13 +462,13 @@ std::swap(repSrcReg, repDstReg); std::swap(ResSrcInt, ResDstInt); } - assert(MRegisterInfo::isVirtualRegister(repSrcReg) && + assert(TargetRegisterInfo::isVirtualRegister(repSrcReg) && "LiveInterval::join didn't work right!"); // If we're about to merge live ranges into a physical register live range, // we have to update any aliased register's live ranges to indicate that they // have clobbered values for this range. - if (MRegisterInfo::isPhysicalRegister(repDstReg)) { + if (TargetRegisterInfo::isPhysicalRegister(repDstReg)) { // Unset unnecessary kills. if (!ResDstInt->containsOneValue()) { for (LiveInterval::Ranges::const_iterator I = ResSrcInt->begin(), @@ -500,7 +500,7 @@ } // Update the liveintervals of sub-registers. - for (const unsigned *AS = mri_->getSubRegisters(repDstReg); *AS; ++AS) + for (const unsigned *AS = tri_->getSubRegisters(repDstReg); *AS; ++AS) li_->getOrCreateInterval(*AS).MergeInClobberRanges(*ResSrcInt, li_->getVNInfoAllocator()); } else { @@ -511,9 +511,9 @@ } // Remember these liveintervals have been joined. - JoinedLIs.set(repSrcReg - MRegisterInfo::FirstVirtualRegister); - if (MRegisterInfo::isVirtualRegister(repDstReg)) - JoinedLIs.set(repDstReg - MRegisterInfo::FirstVirtualRegister); + JoinedLIs.set(repSrcReg - TargetRegisterInfo::FirstVirtualRegister); + if (TargetRegisterInfo::isVirtualRegister(repDstReg)) + JoinedLIs.set(repDstReg - TargetRegisterInfo::FirstVirtualRegister); if (isExtSubReg && !SrcIsPhys && !DstIsPhys) { if (!Swapped) { @@ -544,7 +544,7 @@ } } - DOUT << "\n\t\tJoined. Result = "; ResDstInt->print(DOUT, mri_); + DOUT << "\n\t\tJoined. Result = "; ResDstInt->print(DOUT, tri_); DOUT << "\n"; // repSrcReg is guarateed to be the register whose live interval that is @@ -763,20 +763,20 @@ // If a live interval is a physical register, conservatively check if any // of its sub-registers is overlapping the live interval of the virtual // register. If so, do not coalesce. - if (MRegisterInfo::isPhysicalRegister(LHS.reg) && - *mri_->getSubRegisters(LHS.reg)) { - for (const unsigned* SR = mri_->getSubRegisters(LHS.reg); *SR; ++SR) + if (TargetRegisterInfo::isPhysicalRegister(LHS.reg) && + *tri_->getSubRegisters(LHS.reg)) { + for (const unsigned* SR = tri_->getSubRegisters(LHS.reg); *SR; ++SR) if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) { DOUT << "Interfere with sub-register "; - DEBUG(li_->getInterval(*SR).print(DOUT, mri_)); + DEBUG(li_->getInterval(*SR).print(DOUT, tri_)); return false; } - } else if (MRegisterInfo::isPhysicalRegister(RHS.reg) && - *mri_->getSubRegisters(RHS.reg)) { - for (const unsigned* SR = mri_->getSubRegisters(RHS.reg); *SR; ++SR) + } else if (TargetRegisterInfo::isPhysicalRegister(RHS.reg) && + *tri_->getSubRegisters(RHS.reg)) { + for (const unsigned* SR = tri_->getSubRegisters(RHS.reg); *SR; ++SR) if (li_->hasInterval(*SR) && LHS.overlaps(li_->getInterval(*SR))) { DOUT << "Interfere with sub-register "; - DEBUG(li_->getInterval(*SR).print(DOUT, mri_)); + DEBUG(li_->getInterval(*SR).print(DOUT, tri_)); return false; } } @@ -797,7 +797,7 @@ // If RHS is not defined as a copy from the LHS, we can use simpler and // faster checks to see if the live ranges are coalescable. This joiner // can't swap the LHS/RHS intervals though. - if (!MRegisterInfo::isPhysicalRegister(RHS.reg)) { + if (!TargetRegisterInfo::isPhysicalRegister(RHS.reg)) { return SimpleJoin(LHS, RHS); } else { RHSValNoInfo = RHSValNoInfo0; @@ -988,8 +988,8 @@ // If we get here, we know that we can coalesce the live ranges. Ask the // intervals to coalesce themselves now. if ((RHS.ranges.size() > LHS.ranges.size() && - MRegisterInfo::isVirtualRegister(LHS.reg)) || - MRegisterInfo::isPhysicalRegister(RHS.reg)) { + TargetRegisterInfo::isVirtualRegister(LHS.reg)) || + TargetRegisterInfo::isPhysicalRegister(RHS.reg)) { RHS.join(LHS, &RHSValNoAssignments[0], &LHSValNoAssignments[0], NewVNInfo); Swapped = true; } else { @@ -1030,11 +1030,11 @@ return false; else if (left.isBackEdge == right.isBackEdge) { // Join virtuals to physical registers first. - bool LDstIsPhys = MRegisterInfo::isPhysicalRegister(left.DstReg); - bool LSrcIsPhys = MRegisterInfo::isPhysicalRegister(left.SrcReg); + bool LDstIsPhys = TargetRegisterInfo::isPhysicalRegister(left.DstReg); + bool LSrcIsPhys = TargetRegisterInfo::isPhysicalRegister(left.SrcReg); bool LIsPhys = LDstIsPhys || LSrcIsPhys; - bool RDstIsPhys = MRegisterInfo::isPhysicalRegister(right.DstReg); - bool RSrcIsPhys = MRegisterInfo::isPhysicalRegister(right.SrcReg); + bool RDstIsPhys = TargetRegisterInfo::isPhysicalRegister(right.DstReg); + bool RSrcIsPhys = TargetRegisterInfo::isPhysicalRegister(right.SrcReg); bool RIsPhys = RDstIsPhys || RSrcIsPhys; if (LIsPhys && !RIsPhys) return false; @@ -1082,8 +1082,8 @@ unsigned repSrcReg = rep(SrcReg); unsigned repDstReg = rep(DstReg); - bool SrcIsPhys = MRegisterInfo::isPhysicalRegister(repSrcReg); - bool DstIsPhys = MRegisterInfo::isPhysicalRegister(repDstReg); + bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(repSrcReg); + bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(repDstReg); if (NewHeuristic) { JoinQueue->push(CopyRec(Inst, SrcReg, DstReg, LoopDepth, isBackEdgeCopy(Inst, DstReg))); @@ -1198,7 +1198,7 @@ // unnecessary kills. int RegNum = JoinedLIs.find_first(); while (RegNum != -1) { - unsigned Reg = RegNum + MRegisterInfo::FirstVirtualRegister; + unsigned Reg = RegNum + TargetRegisterInfo::FirstVirtualRegister; unsigned repReg = rep(Reg); LiveInterval &LI = li_->getInterval(repReg); LiveVariables::VarInfo& svi = lv_->getVarInfo(Reg); @@ -1233,15 +1233,15 @@ unsigned RegB) const { // Get the register classes for the first reg. - if (MRegisterInfo::isPhysicalRegister(RegA)) { - assert(MRegisterInfo::isVirtualRegister(RegB) && + if (TargetRegisterInfo::isPhysicalRegister(RegA)) { + assert(TargetRegisterInfo::isVirtualRegister(RegB) && "Shouldn't consider two physregs!"); return !mf_->getRegInfo().getRegClass(RegB)->contains(RegA); } // Compare against the regclass for the second reg. const TargetRegisterClass *RegClass = mf_->getRegInfo().getRegClass(RegA); - if (MRegisterInfo::isVirtualRegister(RegB)) + if (TargetRegisterInfo::isVirtualRegister(RegB)) return RegClass != mf_->getRegInfo().getRegClass(RegB); else return !RegClass->contains(RegB); @@ -1268,7 +1268,7 @@ for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) { MachineOperand &MO = MI->getOperand(i); if (MO.isRegister() && MO.isUse() && MO.getReg() && - mri_->regsOverlap(rep(MO.getReg()), Reg)) { + tri_->regsOverlap(rep(MO.getReg()), Reg)) { MOU = &MO; return MI; } @@ -1288,7 +1288,7 @@ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand &MO = MI->getOperand(i); if (MO.isRegister() && MO.isDef() && - mri_->regsOverlap(rep(MO.getReg()), Reg)) + tri_->regsOverlap(rep(MO.getReg()), Reg)) return &MO; } return NULL; @@ -1301,7 +1301,7 @@ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand &MO = MI->getOperand(i); if (MO.isRegister() && MO.isKill() && MO.getReg() && - mri_->regsOverlap(rep(MO.getReg()), Reg)) + tri_->regsOverlap(rep(MO.getReg()), Reg)) MO.setIsKill(false); } } @@ -1325,7 +1325,7 @@ for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) { MachineOperand &MO = MI->getOperand(i); if (MO.isRegister() && MO.isKill() && MO.getReg() && - mri_->regsOverlap(rep(MO.getReg()), Reg)) { + tri_->regsOverlap(rep(MO.getReg()), Reg)) { MO.setIsKill(false); } } @@ -1340,15 +1340,15 @@ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand &MO = MI->getOperand(i); if (MO.isRegister() && MO.isDef() && - mri_->regsOverlap(rep(MO.getReg()), Reg)) + tri_->regsOverlap(rep(MO.getReg()), Reg)) return true; } return false; } void SimpleRegisterCoalescing::printRegName(unsigned reg) const { - if (MRegisterInfo::isPhysicalRegister(reg)) - cerr << mri_->getName(reg); + if (TargetRegisterInfo::isPhysicalRegister(reg)) + cerr << tri_->getName(reg); else cerr << "%reg" << reg; } @@ -1374,7 +1374,7 @@ bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) { mf_ = &fn; tm_ = &fn.getTarget(); - mri_ = tm_->getRegisterInfo(); + tri_ = tm_->getRegisterInfo(); tii_ = tm_->getInstrInfo(); li_ = &getAnalysis(); lv_ = &getAnalysis(); @@ -1384,11 +1384,11 @@ << "********** Function: " << ((Value*)mf_->getFunction())->getName() << '\n'; - allocatableRegs_ = mri_->getAllocatableSet(fn); - for (MRegisterInfo::regclass_iterator I = mri_->regclass_begin(), - E = mri_->regclass_end(); I != E; ++I) + allocatableRegs_ = tri_->getAllocatableSet(fn); + for (TargetRegisterInfo::regclass_iterator I = tri_->regclass_begin(), + E = tri_->regclass_end(); I != E; ++I) allocatableRCRegs_.insert(std::make_pair(*I, - mri_->getAllocatableSet(fn, *I))); + tri_->getAllocatableSet(fn, *I))); MachineRegisterInfo &RegInfo = mf_->getRegInfo(); r2rMap_.grow(RegInfo.getLastVirtReg()); @@ -1400,7 +1400,7 @@ joinIntervals(); DOUT << "********** INTERVALS POST JOINING **********\n"; for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I){ - I->second.print(DOUT, mri_); + I->second.print(DOUT, tri_); DOUT << "\n"; } @@ -1454,13 +1454,13 @@ for (unsigned i = 0, e = mii->getNumOperands(); i != e; ++i) { const MachineOperand &mop = mii->getOperand(i); if (mop.isRegister() && mop.getReg() && - MRegisterInfo::isVirtualRegister(mop.getReg())) { + TargetRegisterInfo::isVirtualRegister(mop.getReg())) { // replace register with representative register unsigned OrigReg = mop.getReg(); unsigned reg = rep(OrigReg); unsigned SubIdx = RegSubIdxMap[OrigReg]; - if (SubIdx && MRegisterInfo::isPhysicalRegister(reg)) - mii->getOperand(i).setReg(mri_->getSubReg(reg, SubIdx)); + if (SubIdx && TargetRegisterInfo::isPhysicalRegister(reg)) + mii->getOperand(i).setReg(tri_->getSubReg(reg, SubIdx)); else { mii->getOperand(i).setReg(reg); mii->getOperand(i).setSubReg(SubIdx); @@ -1483,7 +1483,7 @@ for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I) { LiveInterval &LI = I->second; - if (MRegisterInfo::isVirtualRegister(LI.reg)) { + if (TargetRegisterInfo::isVirtualRegister(LI.reg)) { // If the live interval length is essentially zero, i.e. in every live // range the use follows def immediately, it doesn't make sense to spill // it and hope it will be easier to allocate for this li. Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h (original) +++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h Sun Feb 10 12:45:23 2008 @@ -25,7 +25,7 @@ namespace llvm { class SimpleRegisterCoalescing; class LiveVariables; - class MRegisterInfo; + class TargetRegisterInfo; class TargetInstrInfo; class VirtRegMap; class MachineLoopInfo; @@ -81,7 +81,7 @@ public RegisterCoalescer { MachineFunction* mf_; const TargetMachine* tm_; - const MRegisterInfo* mri_; + const TargetRegisterInfo* tri_; const TargetInstrInfo* tii_; LiveIntervals *li_; LiveVariables *lv_; Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp (original) +++ llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Sun Feb 10 12:45:23 2008 @@ -34,7 +34,7 @@ #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Support/Debug.h" @@ -121,8 +121,8 @@ unsigned regA = mi->getOperand(ti).getReg(); unsigned regB = mi->getOperand(si).getReg(); - assert(MRegisterInfo::isVirtualRegister(regA) && - MRegisterInfo::isVirtualRegister(regB) && + assert(TargetRegisterInfo::isVirtualRegister(regA) && + TargetRegisterInfo::isVirtualRegister(regB) && "cannot update physical register live information"); #ifndef NDEBUG Modified: llvm/trunk/lib/CodeGen/VirtRegMap.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/VirtRegMap.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/VirtRegMap.cpp (original) +++ llvm/trunk/lib/CodeGen/VirtRegMap.cpp Sun Feb 10 12:45:23 2008 @@ -79,7 +79,7 @@ } int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) { - assert(MRegisterInfo::isVirtualRegister(virtReg)); + assert(TargetRegisterInfo::isVirtualRegister(virtReg)); assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && "attempt to assign stack slot to already spilled register"); const TargetRegisterClass* RC = MF.getRegInfo().getRegClass(virtReg); @@ -91,7 +91,7 @@ } void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int frameIndex) { - assert(MRegisterInfo::isVirtualRegister(virtReg)); + assert(TargetRegisterInfo::isVirtualRegister(virtReg)); assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && "attempt to assign stack slot to already spilled register"); assert((frameIndex >= 0 || @@ -101,7 +101,7 @@ } int VirtRegMap::assignVirtReMatId(unsigned virtReg) { - assert(MRegisterInfo::isVirtualRegister(virtReg)); + assert(TargetRegisterInfo::isVirtualRegister(virtReg)); assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT && "attempt to assign re-mat id to already spilled register"); Virt2ReMatIdMap[virtReg] = ReMatId; @@ -109,7 +109,7 @@ } void VirtRegMap::assignVirtReMatId(unsigned virtReg, int id) { - assert(MRegisterInfo::isVirtualRegister(virtReg)); + assert(TargetRegisterInfo::isVirtualRegister(virtReg)); assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT && "attempt to assign re-mat id to already spilled register"); Virt2ReMatIdMap[virtReg] = id; @@ -135,17 +135,17 @@ } void VirtRegMap::print(std::ostream &OS) const { - const MRegisterInfo* MRI = MF.getTarget().getRegisterInfo(); + const TargetRegisterInfo* TRI = MF.getTarget().getRegisterInfo(); OS << "********** REGISTER MAP **********\n"; - for (unsigned i = MRegisterInfo::FirstVirtualRegister, + for (unsigned i = TargetRegisterInfo::FirstVirtualRegister, e = MF.getRegInfo().getLastVirtReg(); i <= e; ++i) { if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG) - OS << "[reg" << i << " -> " << MRI->getName(Virt2PhysMap[i]) << "]\n"; + OS << "[reg" << i << " -> " << TRI->getName(Virt2PhysMap[i]) << "]\n"; } - for (unsigned i = MRegisterInfo::FirstVirtualRegister, + for (unsigned i = TargetRegisterInfo::FirstVirtualRegister, e = MF.getRegInfo().getLastVirtReg(); i <= e; ++i) if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT) OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n"; @@ -192,7 +192,7 @@ for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { MachineOperand &MO = MI.getOperand(i); if (MO.isRegister() && MO.getReg()) - if (MRegisterInfo::isVirtualRegister(MO.getReg())) { + if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) { unsigned VirtReg = MO.getReg(); unsigned PhysReg = VRM.getPhys(VirtReg); if (!VRM.isAssignedReg(VirtReg)) { @@ -242,12 +242,12 @@ /// register pressure in other blocks). class VISIBILITY_HIDDEN LocalSpiller : public Spiller { MachineRegisterInfo *RegInfo; - const MRegisterInfo *MRI; + const TargetRegisterInfo *TRI; const TargetInstrInfo *TII; public: bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) { RegInfo = &MF.getRegInfo(); - MRI = MF.getTarget().getRegisterInfo(); + TRI = MF.getTarget().getRegisterInfo(); TII = MF.getTarget().getInstrInfo(); DOUT << "\n**** Local spiller rewriting function '" << MF.getFunction()->getName() << "':\n"; @@ -298,7 +298,7 @@ /// this bit and addAvailable sets it if. namespace { class VISIBILITY_HIDDEN AvailableSpills { - const MRegisterInfo *MRI; + const TargetRegisterInfo *TRI; const TargetInstrInfo *TII; // SpillSlotsOrReMatsAvailable - This map keeps track of all of the spilled @@ -316,11 +316,11 @@ void ClobberPhysRegOnly(unsigned PhysReg); public: - AvailableSpills(const MRegisterInfo *mri, const TargetInstrInfo *tii) - : MRI(mri), TII(tii) { + AvailableSpills(const TargetRegisterInfo *tri, const TargetInstrInfo *tii) + : TRI(tri), TII(tii) { } - const MRegisterInfo *getRegInfo() const { return MRI; } + const TargetRegisterInfo *getRegInfo() const { return TRI; } /// getSpillSlotOrReMatPhysReg - If the specified stack slot or remat is /// available in a physical register, return that PhysReg, otherwise @@ -350,7 +350,7 @@ DOUT << "Remembering RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1; else DOUT << "Remembering SS#" << SlotOrReMat; - DOUT << " in physreg " << MRI->getName(Reg) << "\n"; + DOUT << " in physreg " << TRI->getName(Reg) << "\n"; } /// canClobberPhysReg - Return true if the spiller is allowed to change the @@ -391,7 +391,7 @@ assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg && "Bidirectional map mismatch!"); SpillSlotsOrReMatsAvailable[SlotOrReMat] &= ~1; - DOUT << "PhysReg " << MRI->getName(PhysReg) + DOUT << "PhysReg " << TRI->getName(PhysReg) << " copied, it is available for use but can no longer be modified\n"; } } @@ -400,7 +400,7 @@ /// stackslot register and its aliases. The register and its aliases may /// still available but is no longer allowed to be modifed. void AvailableSpills::disallowClobberPhysReg(unsigned PhysReg) { - for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS) + for (const unsigned *AS = TRI->getAliasSet(PhysReg); *AS; ++AS) disallowClobberPhysRegOnly(*AS); disallowClobberPhysRegOnly(PhysReg); } @@ -416,7 +416,7 @@ assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg && "Bidirectional map mismatch!"); SpillSlotsOrReMatsAvailable.erase(SlotOrReMat); - DOUT << "PhysReg " << MRI->getName(PhysReg) + DOUT << "PhysReg " << TRI->getName(PhysReg) << " clobbered, invalidating "; if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT) DOUT << "RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1 << "\n"; @@ -429,7 +429,7 @@ /// value. We use this to invalidate any info about stuff we thing lives in /// it and any of its aliases. void AvailableSpills::ClobberPhysReg(unsigned PhysReg) { - for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS) + for (const unsigned *AS = TRI->getAliasSet(PhysReg); *AS; ++AS) ClobberPhysRegOnly(*AS); ClobberPhysRegOnly(PhysReg); } @@ -606,8 +606,8 @@ std::vector Reuses; BitVector PhysRegsClobbered; public: - ReuseInfo(MachineInstr &mi, const MRegisterInfo *mri) : MI(mi) { - PhysRegsClobbered.resize(mri->getNumRegs()); + ReuseInfo(MachineInstr &mi, const TargetRegisterInfo *tri) : MI(mi) { + PhysRegsClobbered.resize(tri->getNumRegs()); } bool hasReuses() const { @@ -670,8 +670,8 @@ // value aliases the new register. If so, codegen the previous reload // and use this one. unsigned PRRU = Op.PhysRegReused; - const MRegisterInfo *MRI = Spills.getRegInfo(); - if (MRI->areAliases(PRRU, PhysReg)) { + const TargetRegisterInfo *TRI = Spills.getRegInfo(); + if (TRI->areAliases(PRRU, PhysReg)) { // Okay, we found out that an alias of a reused register // was used. This isn't good because it means we have // to undo a previous reuse. @@ -693,7 +693,7 @@ Rejected, RegKills, KillOps, VRM); if (NewOp.StackSlotOrReMat > VirtRegMap::MAX_STACK_SLOT) { - MRI->reMaterialize(*MBB, MI, NewPhysReg, + TRI->reMaterialize(*MBB, MI, NewPhysReg, VRM.getReMaterializedMI(NewOp.VirtReg)); ++NumReMats; } else { @@ -806,23 +806,23 @@ if (!MO.isRegister() || MO.getReg() == 0 || !MO.isUse()) continue; unsigned VirtReg = MO.getReg(); - if (MRegisterInfo::isPhysicalRegister(VirtReg) || MO.getSubReg()) + if (TargetRegisterInfo::isPhysicalRegister(VirtReg) || MO.getSubReg()) continue; if (VRM.isAssignedReg(VirtReg)) { unsigned PhysReg = VRM.getPhys(VirtReg); - if (PhysReg && MRI->regsOverlap(PhysReg, UnfoldPR)) + if (PhysReg && TRI->regsOverlap(PhysReg, UnfoldPR)) return false; } else if (VRM.isReMaterialized(VirtReg)) continue; int SS = VRM.getStackSlot(VirtReg); unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS); if (PhysReg) { - if (MRI->regsOverlap(PhysReg, UnfoldPR)) + if (TRI->regsOverlap(PhysReg, UnfoldPR)) return false; continue; } PhysReg = VRM.getPhys(VirtReg); - if (!MRI->regsOverlap(PhysReg, UnfoldPR)) + if (!TRI->regsOverlap(PhysReg, UnfoldPR)) continue; // Ok, we'll need to reload the value into a register which makes @@ -858,11 +858,11 @@ /// findSuperReg - Find the SubReg's super-register of given register class /// where its SubIdx sub-register is SubReg. static unsigned findSuperReg(const TargetRegisterClass *RC, unsigned SubReg, - unsigned SubIdx, const MRegisterInfo *MRI) { + unsigned SubIdx, const TargetRegisterInfo *TRI) { for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I != E; ++I) { unsigned Reg = *I; - if (MRI->getSubReg(Reg, SubIdx) == SubReg) + if (TRI->getSubReg(Reg, SubIdx) == SubReg) return Reg; } return 0; @@ -935,7 +935,7 @@ // Spills - Keep track of which spilled values are available in physregs so // that we can choose to reuse the physregs instead of emitting reloads. - AvailableSpills Spills(MRI, TII); + AvailableSpills Spills(TRI, TII); // MaybeDeadStores - When we need to write a value back into a stack slot, // keep track of the inserted store. If the stack slot value is never read @@ -950,9 +950,9 @@ SmallSet ReMatDefs; // Keep track of kill information. - BitVector RegKills(MRI->getNumRegs()); + BitVector RegKills(TRI->getNumRegs()); std::vector KillOps; - KillOps.resize(MRI->getNumRegs(), NULL); + KillOps.resize(TRI->getNumRegs(), NULL); for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end(); MII != E; ) { @@ -978,7 +978,7 @@ unsigned Phys = VRM.getPhys(VirtReg); RegInfo->setPhysRegUsed(Phys); if (VRM.isReMaterialized(VirtReg)) { - MRI->reMaterialize(MBB, &MI, Phys, + TRI->reMaterialize(MBB, &MI, Phys, VRM.getReMaterializedMI(VirtReg)); ++NumReMats; } else { @@ -1016,7 +1016,7 @@ /// ReusedOperands - Keep track of operand reuse in case we need to undo /// reuse. - ReuseInfo ReusedOperands(MI, MRI); + ReuseInfo ReusedOperands(MI, TRI); // Process all of the spilled uses and all non spilled reg references. for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { MachineOperand &MO = MI.getOperand(i); @@ -1024,14 +1024,14 @@ continue; // Ignore non-register operands. unsigned VirtReg = MO.getReg(); - if (MRegisterInfo::isPhysicalRegister(VirtReg)) { + if (TargetRegisterInfo::isPhysicalRegister(VirtReg)) { // Ignore physregs for spilling, but remember that it is used by this // function. RegInfo->setPhysRegUsed(VirtReg); continue; } - assert(MRegisterInfo::isVirtualRegister(VirtReg) && + assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && "Not a virtual or a physical register?"); unsigned SubIdx = MO.getSubReg(); @@ -1041,7 +1041,7 @@ RegInfo->setPhysRegUsed(Phys); if (MO.isDef()) ReusedOperands.markClobbered(Phys); - unsigned RReg = SubIdx ? MRI->getSubReg(Phys, SubIdx) : Phys; + unsigned RReg = SubIdx ? TRI->getSubReg(Phys, SubIdx) : Phys; MI.getOperand(i).setReg(RReg); continue; } @@ -1100,10 +1100,10 @@ else DOUT << "Reusing SS#" << ReuseSlot; DOUT << " from physreg " - << MRI->getName(PhysReg) << " for vreg" + << TRI->getName(PhysReg) << " for vreg" << VirtReg <<" instead of reloading into physreg " - << MRI->getName(VRM.getPhys(VirtReg)) << "\n"; - unsigned RReg = SubIdx ? MRI->getSubReg(PhysReg, SubIdx) : PhysReg; + << TRI->getName(VRM.getPhys(VirtReg)) << "\n"; + unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg; MI.getOperand(i).setReg(RReg); // The only technical detail we have is that we don't know that @@ -1173,10 +1173,10 @@ DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1; else DOUT << "Reusing SS#" << ReuseSlot; - DOUT << " from physreg " << MRI->getName(PhysReg) << " for vreg" + DOUT << " from physreg " << TRI->getName(PhysReg) << " for vreg" << VirtReg << " instead of reloading into same physreg.\n"; - unsigned RReg = SubIdx ? MRI->getSubReg(PhysReg, SubIdx) : PhysReg; + unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg; MI.getOperand(i).setReg(RReg); ReusedOperands.markClobbered(RReg); ++NumReused; @@ -1196,7 +1196,7 @@ Spills.addAvailable(ReuseSlot, &MI, DesignatedReg); unsigned RReg = - SubIdx ? MRI->getSubReg(DesignatedReg, SubIdx) : DesignatedReg; + SubIdx ? TRI->getSubReg(DesignatedReg, SubIdx) : DesignatedReg; MI.getOperand(i).setReg(RReg); DOUT << '\t' << *prior(MII); ++NumReused; @@ -1218,7 +1218,7 @@ RegInfo->setPhysRegUsed(PhysReg); ReusedOperands.markClobbered(PhysReg); if (DoReMat) { - MRI->reMaterialize(MBB, &MI, PhysReg, VRM.getReMaterializedMI(VirtReg)); + TRI->reMaterialize(MBB, &MI, PhysReg, VRM.getReMaterializedMI(VirtReg)); ++NumReMats; } else { const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg); @@ -1236,7 +1236,7 @@ // unless it's a two-address operand. if (TID.getOperandConstraint(i, TOI::TIED_TO) == -1) MI.getOperand(i).setIsKill(); - unsigned RReg = SubIdx ? MRI->getSubReg(PhysReg, SubIdx) : PhysReg; + unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg; MI.getOperand(i).setReg(RReg); UpdateKills(*prior(MII), RegKills, KillOps); DOUT << '\t' << *prior(MII); @@ -1367,7 +1367,7 @@ int StackSlot; if (!(MR & VirtRegMap::isRef)) { if (unsigned SrcReg = TII->isStoreToStackSlot(&MI, StackSlot)) { - assert(MRegisterInfo::isPhysicalRegister(SrcReg) && + assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) && "Src hasn't been allocated yet?"); // Okay, this is certainly a store of SrcReg to [StackSlot]. Mark // this as a potentially dead store in case there is a subsequent @@ -1390,7 +1390,7 @@ continue; unsigned VirtReg = MO.getReg(); - if (!MRegisterInfo::isVirtualRegister(VirtReg)) { + if (!TargetRegisterInfo::isVirtualRegister(VirtReg)) { // Check to see if this is a noop copy. If so, eliminate the // instruction before considering the dest reg to be changed. unsigned Src, Dst; @@ -1440,8 +1440,8 @@ if (TiedOp != -1) { PhysReg = MI.getOperand(TiedOp).getReg(); if (SubIdx) { - unsigned SuperReg = findSuperReg(RC, PhysReg, SubIdx, MRI); - assert(SuperReg && MRI->getSubReg(SuperReg, SubIdx) == PhysReg && + unsigned SuperReg = findSuperReg(RC, PhysReg, SubIdx, TRI); + assert(SuperReg && TRI->getSubReg(SuperReg, SubIdx) == PhysReg && "Can't find corresponding super-register!"); PhysReg = SuperReg; } @@ -1456,7 +1456,7 @@ } RegInfo->setPhysRegUsed(PhysReg); - unsigned RReg = SubIdx ? MRI->getSubReg(PhysReg, SubIdx) : PhysReg; + unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg; ReusedOperands.markClobbered(RReg); MI.getOperand(i).setReg(RReg); Modified: llvm/trunk/lib/CodeGen/VirtRegMap.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/VirtRegMap.h?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/VirtRegMap.h (original) +++ llvm/trunk/lib/CodeGen/VirtRegMap.h Sun Feb 10 12:45:23 2008 @@ -17,7 +17,7 @@ #ifndef LLVM_CODEGEN_VIRTREGMAP_H #define LLVM_CODEGEN_VIRTREGMAP_H -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/IndexedMap.h" #include "llvm/Support/Streams.h" @@ -115,15 +115,15 @@ /// @brief returns the physical register mapped to the specified /// virtual register unsigned getPhys(unsigned virtReg) const { - assert(MRegisterInfo::isVirtualRegister(virtReg)); + assert(TargetRegisterInfo::isVirtualRegister(virtReg)); return Virt2PhysMap[virtReg]; } /// @brief creates a mapping for the specified virtual register to /// the specified physical register void assignVirt2Phys(unsigned virtReg, unsigned physReg) { - assert(MRegisterInfo::isVirtualRegister(virtReg) && - MRegisterInfo::isPhysicalRegister(physReg)); + assert(TargetRegisterInfo::isVirtualRegister(virtReg) && + TargetRegisterInfo::isPhysicalRegister(physReg)); assert(Virt2PhysMap[virtReg] == NO_PHYS_REG && "attempt to assign physical register to already mapped " "virtual register"); @@ -133,7 +133,7 @@ /// @brief clears the specified virtual register's, physical /// register mapping void clearVirt(unsigned virtReg) { - assert(MRegisterInfo::isVirtualRegister(virtReg)); + assert(TargetRegisterInfo::isVirtualRegister(virtReg)); assert(Virt2PhysMap[virtReg] != NO_PHYS_REG && "attempt to clear a not assigned virtual register"); Virt2PhysMap[virtReg] = NO_PHYS_REG; @@ -169,14 +169,14 @@ /// @brief returns the stack slot mapped to the specified virtual /// register int getStackSlot(unsigned virtReg) const { - assert(MRegisterInfo::isVirtualRegister(virtReg)); + assert(TargetRegisterInfo::isVirtualRegister(virtReg)); return Virt2StackSlotMap[virtReg]; } /// @brief returns the rematerialization id mapped to the specified virtual /// register int getReMatId(unsigned virtReg) const { - assert(MRegisterInfo::isVirtualRegister(virtReg)); + assert(TargetRegisterInfo::isVirtualRegister(virtReg)); return Virt2ReMatIdMap[virtReg]; } Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Sun Feb 10 12:45:23 2008 @@ -272,7 +272,7 @@ const MachineOperand &MO = MI->getOperand(opNum); switch (MO.getType()) { case MachineOperand::MO_Register: - if (MRegisterInfo::isPhysicalRegister(MO.getReg())) + if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) O << TM.getRegisterInfo()->get(MO.getReg()).Name; else assert(0 && "not implemented"); @@ -392,7 +392,7 @@ const MachineOperand &MO2 = MI->getOperand(Op+1); const MachineOperand &MO3 = MI->getOperand(Op+2); - assert(MRegisterInfo::isPhysicalRegister(MO1.getReg())); + assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg())); O << TM.getRegisterInfo()->get(MO1.getReg()).Name; // Print the shift opc. @@ -401,7 +401,7 @@ << " "; if (MO2.getReg()) { - assert(MRegisterInfo::isPhysicalRegister(MO2.getReg())); + assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg())); O << TM.getRegisterInfo()->get(MO2.getReg()).Name; assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0); } else { @@ -468,7 +468,7 @@ const MachineOperand &MO2 = MI->getOperand(Op+1); const MachineOperand &MO3 = MI->getOperand(Op+2); - assert(MRegisterInfo::isPhysicalRegister(MO1.getReg())); + assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg())); O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).Name; if (MO2.getReg()) { @@ -532,7 +532,7 @@ return; } - assert(MRegisterInfo::isPhysicalRegister(MO1.getReg())); + assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg())); if (Modifier && strcmp(Modifier, "submode") == 0) { ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MO2.getImm()); @@ -569,7 +569,7 @@ } const MachineOperand &MO1 = MI->getOperand(Op); - assert(MRegisterInfo::isPhysicalRegister(MO1.getReg())); + assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg())); O << "[pc, +" << TM.getRegisterInfo()->get(MO1.getReg()).Name << "]"; } Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Sun Feb 10 12:45:23 2008 @@ -134,7 +134,7 @@ intptr_t rv = 0; const MachineOperand &MO = MI.getOperand(OpIndex); if (MO.isRegister()) { - assert(MRegisterInfo::isPhysicalRegister(MO.getReg())); + assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg())); rv = ARMRegisterInfo::getRegisterNumbering(MO.getReg()); } else if (MO.isImmediate()) { rv = MO.getImm(); @@ -478,7 +478,7 @@ if(ARM_AM::getSORegShOp(MO2.getImm()) != ARM_AM::rrx) if(IsShiftByRegister) { // set the value of bit[11:8] (register Rs). - assert(MRegisterInfo::isPhysicalRegister(MO1.getReg())); + assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg())); op = ARMRegisterInfo::getRegisterNumbering(MO1.getReg()); assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0); Value |= op << ARMII::RegRsShift; @@ -540,7 +540,7 @@ // set bit I(25), because this is not in immediate enconding. Value |= 1 << ARMII::I_BitShift; - assert(MRegisterInfo::isPhysicalRegister(MO2.getReg())); + assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg())); // set bit[3:0] to the corresponding Rm register Value |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg()); @@ -640,7 +640,8 @@ for (unsigned i = OpIndex + 4, e = MI.getNumOperands(); i != e; ++i) { const MachineOperand &MOR = MI.getOperand(i); unsigned RegNumber = ARMRegisterInfo::getRegisterNumbering(MOR.getReg()); - assert(MRegisterInfo::isPhysicalRegister(MOR.getReg()) && RegNumber < 16); + assert(TargetRegisterInfo::isPhysicalRegister(MOR.getReg()) && + RegNumber < 16); Value |= 0x1 << RegNumber; } Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp Sun Feb 10 12:45:23 2008 @@ -282,7 +282,7 @@ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand &MO = MI->getOperand(i); if (MO.isRegister() && MO.getReg() && - MRegisterInfo::isVirtualRegister(MO.getReg())) { + TargetRegisterInfo::isVirtualRegister(MO.getReg())) { unsigned Reg = MO.getReg(); LiveVariables::VarInfo &VI = LV.getVarInfo(Reg); if (MO.isDef()) { Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.h?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.h Sun Feb 10 12:45:23 2008 @@ -134,7 +134,7 @@ /// such, whenever a client has an instance of instruction info, it should /// always be able to get register info as well (through this method). /// - virtual const MRegisterInfo &getRegisterInfo() const { return RI; } + virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; } /// getPointerRegClass - Return the register class to use to hold pointers. /// This is used for addressing modes. Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Sun Feb 10 12:45:23 2008 @@ -26,7 +26,7 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/RegisterScavenging.h" #include "llvm/Support/Compiler.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" using namespace llvm; @@ -42,7 +42,7 @@ ARMLoadStoreOpt() : MachineFunctionPass((intptr_t)&ID) {} const TargetInstrInfo *TII; - const MRegisterInfo *MRI; + const TargetRegisterInfo *TRI; ARMFunctionInfo *AFI; RegScavenger *RS; @@ -755,7 +755,7 @@ const TargetMachine &TM = Fn.getTarget(); AFI = Fn.getInfo(); TII = TM.getInstrInfo(); - MRI = TM.getRegisterInfo(); + TRI = TM.getRegisterInfo(); RS = new RegScavenger(); bool Modified = false; Modified: llvm/trunk/lib/Target/ARM/ARMMachineFunctionInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMachineFunctionInfo.h?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMachineFunctionInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMMachineFunctionInfo.h Sun Feb 10 12:45:23 2008 @@ -16,7 +16,7 @@ #include "ARMSubtarget.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/ADT/BitVector.h" Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp Sun Feb 10 12:45:23 2008 @@ -7,7 +7,7 @@ // //===----------------------------------------------------------------------===// // -// This file contains the ARM implementation of the MRegisterInfo class. +// This file contains the ARM implementation of the TargetRegisterInfo class. // //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.h?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.h Sun Feb 10 12:45:23 2008 @@ -7,14 +7,14 @@ // //===----------------------------------------------------------------------===// // -// This file contains the ARM implementation of the MRegisterInfo class. +// This file contains the ARM implementation of the TargetRegisterInfo class. // //===----------------------------------------------------------------------===// #ifndef ARMREGISTERINFO_H #define ARMREGISTERINFO_H -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "ARMGenRegisterInfo.h.inc" namespace llvm { Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td Sun Feb 10 12:45:23 2008 @@ -157,7 +157,7 @@ GPRClass::iterator GPRClass::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const MRegisterInfo *RI = TM.getRegisterInfo(); + const TargetRegisterInfo *RI = TM.getRegisterInfo(); const ARMSubtarget &Subtarget = TM.getSubtarget(); GPRClass::iterator I; if (Subtarget.isThumb()) Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.h?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.h (original) +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.h Sun Feb 10 12:45:23 2008 @@ -41,7 +41,7 @@ virtual const ARMInstrInfo *getInstrInfo() const { return &InstrInfo; } virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; } virtual TargetJITInfo *getJITInfo() { return &JITInfo; } - virtual const MRegisterInfo *getRegisterInfo() const { + virtual const TargetRegisterInfo *getRegisterInfo() const { return &InstrInfo.getRegisterInfo(); } virtual const TargetData *getTargetData() const { return &DataLayout; } Modified: llvm/trunk/lib/Target/Alpha/AlphaAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaAsmPrinter.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaAsmPrinter.cpp Sun Feb 10 12:45:23 2008 @@ -75,7 +75,8 @@ { const MachineOperand &MO = MI->getOperand(opNum); if (MO.getType() == MachineOperand::MO_Register) { - assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??"); + assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && + "Not physreg??"); O << TM.getRegisterInfo()->get(MO.getReg()).Name; } else if (MO.isImmediate()) { O << MO.getImm(); @@ -87,7 +88,7 @@ void AlphaAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) { - const MRegisterInfo &RI = *TM.getRegisterInfo(); + const TargetRegisterInfo &RI = *TM.getRegisterInfo(); switch (MO.getType()) { case MachineOperand::MO_Register: Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp Sun Feb 10 12:45:23 2008 @@ -261,7 +261,7 @@ VarArgsOffset = (Op.Val->getNumValues()-1) * 8; std::vector LS; for (int i = 0; i < 6; ++i) { - if (MRegisterInfo::isPhysicalRegister(args_int[i])) + if (TargetRegisterInfo::isPhysicalRegister(args_int[i])) args_int[i] = AddLiveIn(MF, args_int[i], &Alpha::GPRCRegClass); SDOperand argt = DAG.getCopyFromReg(Root, args_int[i], MVT::i64); int FI = MFI->CreateFixedObject(8, -8 * (6 - i)); @@ -269,7 +269,7 @@ SDOperand SDFI = DAG.getFrameIndex(FI, MVT::i64); LS.push_back(DAG.getStore(Root, argt, SDFI, NULL, 0)); - if (MRegisterInfo::isPhysicalRegister(args_float[i])) + if (TargetRegisterInfo::isPhysicalRegister(args_float[i])) args_float[i] = AddLiveIn(MF, args_float[i], &Alpha::F8RCRegClass); argt = DAG.getCopyFromReg(Root, args_float[i], MVT::f64); FI = MFI->CreateFixedObject(8, - 8 * (12 - i)); Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h (original) +++ llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h Sun Feb 10 12:45:23 2008 @@ -28,7 +28,7 @@ /// such, whenever a client has an instance of instruction info, it should /// always be able to get register info as well (through this method). /// - virtual const MRegisterInfo &getRegisterInfo() const { return RI; } + virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; } /// Return true if the instruction is a register to register move and /// leave the source and dest operands in the passed parameters. Modified: llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp Sun Feb 10 12:45:23 2008 @@ -7,7 +7,7 @@ // //===----------------------------------------------------------------------===// // -// This file contains the Alpha implementation of the MRegisterInfo class. +// This file contains the Alpha implementation of the TargetRegisterInfo class. // //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.h?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.h (original) +++ llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.h Sun Feb 10 12:45:23 2008 @@ -7,14 +7,14 @@ // //===----------------------------------------------------------------------===// // -// This file contains the Alpha implementation of the MRegisterInfo class. +// This file contains the Alpha implementation of the TargetRegisterInfo class. // //===----------------------------------------------------------------------===// #ifndef ALPHAREGISTERINFO_H #define ALPHAREGISTERINFO_H -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "AlphaGenRegisterInfo.h.inc" namespace llvm { Modified: llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h (original) +++ llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h Sun Feb 10 12:45:23 2008 @@ -43,7 +43,7 @@ virtual const AlphaInstrInfo *getInstrInfo() const { return &InstrInfo; } virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; } virtual const TargetSubtarget *getSubtargetImpl() const{ return &Subtarget; } - virtual const MRegisterInfo *getRegisterInfo() const { + virtual const TargetRegisterInfo *getRegisterInfo() const { return &InstrInfo.getRegisterInfo(); } virtual TargetLowering* getTargetLowering() const { Modified: llvm/trunk/lib/Target/CellSPU/SPUAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUAsmPrinter.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUAsmPrinter.cpp Sun Feb 10 12:45:23 2008 @@ -31,7 +31,7 @@ #include "llvm/Support/Debug.h" #include "llvm/Support/Compiler.h" #include "llvm/Target/TargetAsmInfo.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetOptions.h" #include "llvm/ADT/Statistic.h" @@ -73,14 +73,15 @@ /// void printRegister(const MachineOperand &MO, bool R0AsZero) { unsigned RegNo = MO.getReg(); - assert(MRegisterInfo::isPhysicalRegister(RegNo) && "Not physreg??"); + assert(TargetRegisterInfo::isPhysicalRegister(RegNo) && + "Not physreg??"); O << TM.getRegisterInfo()->get(RegNo).Name; } void printOperand(const MachineInstr *MI, unsigned OpNo) { const MachineOperand &MO = MI->getOperand(OpNo); if (MO.isRegister()) { - assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??"); + assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??"); O << TM.getRegisterInfo()->get(MO.getReg()).Name; } else if (MO.isImmediate()) { O << MO.getImm(); Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h (original) +++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h Sun Feb 10 12:45:23 2008 @@ -30,7 +30,7 @@ /// such, whenever a client has an instance of instruction info, it should /// always be able to get register info as well (through this method). /// - virtual const MRegisterInfo &getRegisterInfo() const { return RI; } + virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; } /// getPointerRegClass - Return the register class to use to hold pointers. /// This is used for addressing modes. Modified: llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp Sun Feb 10 12:45:23 2008 @@ -7,7 +7,7 @@ // //===----------------------------------------------------------------------===// // -// This file contains the Cell implementation of the MRegisterInfo class. +// This file contains the Cell implementation of the TargetRegisterInfo class. // //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h (original) +++ llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h Sun Feb 10 12:45:23 2008 @@ -7,7 +7,8 @@ // //===----------------------------------------------------------------------===// // -// This file contains the Cell SPU implementation of the MRegisterInfo class. +// This file contains the Cell SPU implementation of the TargetRegisterInfo +// class. // //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h (original) +++ llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h Sun Feb 10 12:45:23 2008 @@ -70,7 +70,7 @@ return const_cast(&TLInfo); } - virtual const MRegisterInfo *getRegisterInfo() const { + virtual const TargetRegisterInfo *getRegisterInfo() const { return &InstrInfo.getRegisterInfo(); } Modified: llvm/trunk/lib/Target/IA64/IA64AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64AsmPrinter.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/IA64/IA64AsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/IA64/IA64AsmPrinter.cpp Sun Feb 10 12:45:23 2008 @@ -53,7 +53,8 @@ void printOperand(const MachineInstr *MI, unsigned OpNo){ const MachineOperand &MO = MI->getOperand(OpNo); if (MO.getType() == MachineOperand::MO_Register) { - assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physref??"); + assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && + "Not physref??"); //XXX Bug Workaround: See note in Printer::doInitialization about %. O << TM.getRegisterInfo()->get(MO.getReg()).Name; } else { @@ -164,7 +165,7 @@ void IA64AsmPrinter::printOp(const MachineOperand &MO, bool isBRCALLinsn /* = false */) { - const MRegisterInfo &RI = *TM.getRegisterInfo(); + const TargetRegisterInfo &RI = *TM.getRegisterInfo(); switch (MO.getType()) { case MachineOperand::MO_Register: O << RI.get(MO.getReg()).Name; Modified: llvm/trunk/lib/Target/IA64/IA64InstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64InstrInfo.h?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/IA64/IA64InstrInfo.h (original) +++ llvm/trunk/lib/Target/IA64/IA64InstrInfo.h Sun Feb 10 12:45:23 2008 @@ -28,7 +28,7 @@ /// such, whenever a client has an instance of instruction info, it should /// always be able to get register info as well (through this method). /// - virtual const MRegisterInfo &getRegisterInfo() const { return RI; } + virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; } // // Return true if the instruction is a register to register move and Modified: llvm/trunk/lib/Target/IA64/IA64RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64RegisterInfo.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/IA64/IA64RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/IA64/IA64RegisterInfo.cpp Sun Feb 10 12:45:23 2008 @@ -7,8 +7,9 @@ // //===----------------------------------------------------------------------===// // -// This file contains the IA64 implementation of the MRegisterInfo class. This -// file is responsible for the frame pointer elimination optimization on IA64. +// This file contains the IA64 implementation of the TargetRegisterInfo class. +// This file is responsible for the frame pointer elimination optimization +// on IA64. // //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/IA64/IA64RegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64RegisterInfo.h?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/IA64/IA64RegisterInfo.h (original) +++ llvm/trunk/lib/Target/IA64/IA64RegisterInfo.h Sun Feb 10 12:45:23 2008 @@ -7,14 +7,14 @@ // //===----------------------------------------------------------------------===// // -// This file contains the IA64 implementation of the MRegisterInfo class. +// This file contains the IA64 implementation of the TargetRegisterInfo class. // //===----------------------------------------------------------------------===// #ifndef IA64REGISTERINFO_H #define IA64REGISTERINFO_H -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "IA64GenRegisterInfo.h.inc" namespace llvm { class llvm::Type; } Modified: llvm/trunk/lib/Target/IA64/IA64TargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64TargetMachine.h?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/IA64/IA64TargetMachine.h (original) +++ llvm/trunk/lib/Target/IA64/IA64TargetMachine.h Sun Feb 10 12:45:23 2008 @@ -40,7 +40,7 @@ virtual IA64TargetLowering *getTargetLowering() const { return const_cast(&TLInfo); } - virtual const MRegisterInfo *getRegisterInfo() const { + virtual const TargetRegisterInfo *getRegisterInfo() const { return &InstrInfo.getRegisterInfo(); } virtual const TargetData *getTargetData() const { return &DataLayout; } Removed: llvm/trunk/lib/Target/MRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MRegisterInfo.cpp?rev=46929&view=auto ============================================================================== --- llvm/trunk/lib/Target/MRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/MRegisterInfo.cpp (removed) @@ -1,90 +0,0 @@ -//===- MRegisterInfo.cpp - Target Register Information Implementation -----===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file implements the MRegisterInfo interface. -// -//===----------------------------------------------------------------------===// - -#include "llvm/Target/TargetMachine.h" -#include "llvm/Target/MRegisterInfo.h" -#include "llvm/Target/TargetFrameInfo.h" -#include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/MachineFrameInfo.h" -#include "llvm/ADT/BitVector.h" - -using namespace llvm; - -MRegisterInfo::MRegisterInfo(const TargetRegisterDesc *D, unsigned NR, - regclass_iterator RCB, regclass_iterator RCE, - int CFSO, int CFDO) - : Desc(D), NumRegs(NR), RegClassBegin(RCB), RegClassEnd(RCE) { - assert(NumRegs < FirstVirtualRegister && - "Target has too many physical registers!"); - - CallFrameSetupOpcode = CFSO; - CallFrameDestroyOpcode = CFDO; -} - -MRegisterInfo::~MRegisterInfo() {} - -/// getPhysicalRegisterRegClass - Returns the Register Class of a physical -/// register. -const TargetRegisterClass * -MRegisterInfo::getPhysicalRegisterRegClass(MVT::ValueType VT, - unsigned reg) const { - assert(isPhysicalRegister(reg) && "reg must be a physical register"); - // Pick the register class of the right type that contains this physreg. - for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I) - if ((*I)->hasType(VT) && (*I)->contains(reg)) - return *I; - assert(false && "Couldn't find the register class"); - return 0; -} - - -/// getAllocatableSetForRC - Toggle the bits that represent allocatable -/// registers for the specific register class. -static void getAllocatableSetForRC(MachineFunction &MF, - const TargetRegisterClass *RC, BitVector &R){ - for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), - E = RC->allocation_order_end(MF); I != E; ++I) - R.set(*I); -} - -BitVector MRegisterInfo::getAllocatableSet(MachineFunction &MF, - const TargetRegisterClass *RC) const { - BitVector Allocatable(NumRegs); - if (RC) { - getAllocatableSetForRC(MF, RC, Allocatable); - return Allocatable; - } - - for (MRegisterInfo::regclass_iterator I = regclass_begin(), - E = regclass_end(); I != E; ++I) - getAllocatableSetForRC(MF, *I, Allocatable); - return Allocatable; -} - -/// getFrameIndexOffset - Returns the displacement from the frame register to -/// the stack frame of the specified index. This is the default implementation -/// which is likely incorrect for the target. -int MRegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const { - const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo(); - MachineFrameInfo *MFI = MF.getFrameInfo(); - return MFI->getObjectOffset(FI) + MFI->getStackSize() - - TFI.getOffsetOfLocalArea() + MFI->getOffsetAdjustment(); -} - -/// getInitialFrameState - Returns a list of machine moves that are assumed -/// on entry to a function. -void -MRegisterInfo::getInitialFrameState(std::vector &Moves) const { - // Default is to do nothing. -} - Modified: llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp Sun Feb 10 12:45:23 2008 @@ -162,7 +162,7 @@ void MipsAsmPrinter:: emitFrameDirective(MachineFunction &MF) { - const MRegisterInfo &RI = *TM.getRegisterInfo(); + const TargetRegisterInfo &RI = *TM.getRegisterInfo(); unsigned stackReg = RI.getFrameRegister(MF); unsigned returnReg = RI.getRARegister(); @@ -195,7 +195,7 @@ unsigned int MipsAsmPrinter:: getSavedRegsBitmask(bool isFloat, MachineFunction &MF) { - const MRegisterInfo &RI = *TM.getRegisterInfo(); + const TargetRegisterInfo &RI = *TM.getRegisterInfo(); // Float Point Registers, TODO if (isFloat) @@ -323,7 +323,7 @@ printOperand(const MachineInstr *MI, int opNum) { const MachineOperand &MO = MI->getOperand(opNum); - const MRegisterInfo &RI = *TM.getRegisterInfo(); + const TargetRegisterInfo &RI = *TM.getRegisterInfo(); bool closeP = false; bool isPIC = (TM.getRelocationModel() == Reloc::PIC_); bool isCodeLarge = (TM.getCodeModel() == CodeModel::Large); @@ -364,7 +364,7 @@ switch (MO.getType()) { case MachineOperand::MO_Register: - if (MRegisterInfo::isPhysicalRegister(MO.getReg())) + if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) O << "$" << LowercaseString (RI.get(MO.getReg()).Name); else O << "$" << MO.getReg(); Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.h?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.h (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.h Sun Feb 10 12:45:23 2008 @@ -52,7 +52,7 @@ /// such, whenever a client has an instance of instruction info, it should /// always be able to get register info as well (through this method). /// - virtual const MRegisterInfo &getRegisterInfo() const { return RI; } + virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; } /// Return true if the instruction is a register to register move and /// leave the source and dest operands in the passed parameters. Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Sun Feb 10 12:45:23 2008 @@ -7,7 +7,7 @@ // //===----------------------------------------------------------------------===// // -// This file contains the MIPS implementation of the MRegisterInfo class. +// This file contains the MIPS implementation of the TargetRegisterInfo class. // //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h (original) +++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h Sun Feb 10 12:45:23 2008 @@ -7,14 +7,14 @@ // //===----------------------------------------------------------------------===// // -// This file contains the Mips implementation of the MRegisterInfo class. +// This file contains the Mips implementation of the TargetRegisterInfo class. // //===----------------------------------------------------------------------===// #ifndef MIPSREGISTERINFO_H #define MIPSREGISTERINFO_H -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "MipsGenRegisterInfo.h.inc" namespace llvm { Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.h?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsTargetMachine.h (original) +++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.h Sun Feb 10 12:45:23 2008 @@ -44,7 +44,7 @@ virtual const TargetData *getTargetData() const { return &DataLayout;} - virtual const MRegisterInfo *getRegisterInfo() const { + virtual const TargetRegisterInfo *getRegisterInfo() const { return &InstrInfo.getRegisterInfo(); } Modified: llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp Sun Feb 10 12:45:23 2008 @@ -37,7 +37,7 @@ #include "llvm/Support/Debug.h" #include "llvm/Support/Compiler.h" #include "llvm/Target/TargetAsmInfo.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetOptions.h" #include "llvm/ADT/Statistic.h" @@ -105,7 +105,7 @@ /// void printRegister(const MachineOperand &MO, bool R0AsZero) { unsigned RegNo = MO.getReg(); - assert(MRegisterInfo::isPhysicalRegister(RegNo) && "Not physreg??"); + assert(TargetRegisterInfo::isPhysicalRegister(RegNo) && "Not physreg??"); // If we should use 0 for R0. if (R0AsZero && RegNo == PPC::R0) { Modified: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Sun Feb 10 12:45:23 2008 @@ -225,7 +225,7 @@ // by the scheduler. Detect them now. MachineFunction &Fn = MachineFunction::get(&F); bool HasVectorVReg = false; - for (unsigned i = MRegisterInfo::FirstVirtualRegister, + for (unsigned i = TargetRegisterInfo::FirstVirtualRegister, e = RegInfo->getLastVirtReg()+1; i != e; ++i) if (RegInfo->getRegClass(i) == &PPC::VRRCRegClass) { HasVectorVReg = true; Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h (original) +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h Sun Feb 10 12:45:23 2008 @@ -71,7 +71,7 @@ /// such, whenever a client has an instance of instruction info, it should /// always be able to get register info as well (through this method). /// - virtual const MRegisterInfo &getRegisterInfo() const { return RI; } + virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; } /// getPointerRegClass - Return the register class to use to hold pointers. /// This is used for addressing modes. Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Sun Feb 10 12:45:23 2008 @@ -7,7 +7,8 @@ // //===----------------------------------------------------------------------===// // -// This file contains the PowerPC implementation of the MRegisterInfo class. +// This file contains the PowerPC implementation of the TargetRegisterInfo +// class. // //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h (original) +++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h Sun Feb 10 12:45:23 2008 @@ -7,7 +7,8 @@ // //===----------------------------------------------------------------------===// // -// This file contains the PowerPC implementation of the MRegisterInfo class. +// This file contains the PowerPC implementation of the TargetRegisterInfo +// class. // //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h (original) +++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h Sun Feb 10 12:45:23 2008 @@ -51,7 +51,7 @@ virtual PPCTargetLowering *getTargetLowering() const { return const_cast(&TLInfo); } - virtual const MRegisterInfo *getRegisterInfo() const { + virtual const TargetRegisterInfo *getRegisterInfo() const { return &InstrInfo.getRegisterInfo(); } Modified: llvm/trunk/lib/Target/Sparc/SparcAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcAsmPrinter.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcAsmPrinter.cpp Sun Feb 10 12:45:23 2008 @@ -132,7 +132,7 @@ void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum) { const MachineOperand &MO = MI->getOperand (opNum); - const MRegisterInfo &RI = *TM.getRegisterInfo(); + const TargetRegisterInfo &RI = *TM.getRegisterInfo(); bool CloseParen = false; if (MI->getOpcode() == SP::SETHIi && !MO.isRegister() && !MO.isImmediate()) { O << "%hi("; @@ -144,7 +144,7 @@ } switch (MO.getType()) { case MachineOperand::MO_Register: - if (MRegisterInfo::isPhysicalRegister(MO.getReg())) + if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) O << "%" << LowercaseString (RI.get(MO.getReg()).Name); else O << "%reg" << MO.getReg(); Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h (original) +++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h Sun Feb 10 12:45:23 2008 @@ -41,7 +41,7 @@ /// such, whenever a client has an instance of instruction info, it should /// always be able to get register info as well (through this method). /// - virtual const MRegisterInfo &getRegisterInfo() const { return RI; } + virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; } /// Return true if the instruction is a register to register move and /// leave the source and dest operands in the passed parameters. Modified: llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp Sun Feb 10 12:45:23 2008 @@ -7,7 +7,7 @@ // //===----------------------------------------------------------------------===// // -// This file contains the SPARC implementation of the MRegisterInfo class. +// This file contains the SPARC implementation of the TargetRegisterInfo class. // //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h (original) +++ llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h Sun Feb 10 12:45:23 2008 @@ -7,14 +7,14 @@ // //===----------------------------------------------------------------------===// // -// This file contains the Sparc implementation of the MRegisterInfo class. +// This file contains the Sparc implementation of the TargetRegisterInfo class. // //===----------------------------------------------------------------------===// #ifndef SPARCREGISTERINFO_H #define SPARCREGISTERINFO_H -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "SparcGenRegisterInfo.h.inc" namespace llvm { Modified: llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h (original) +++ llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h Sun Feb 10 12:45:23 2008 @@ -39,7 +39,7 @@ virtual const SparcInstrInfo *getInstrInfo() const { return &InstrInfo; } virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; } virtual const TargetSubtarget *getSubtargetImpl() const{ return &Subtarget; } - virtual const MRegisterInfo *getRegisterInfo() const { + virtual const TargetRegisterInfo *getRegisterInfo() const { return &InstrInfo.getRegisterInfo(); } virtual const TargetData *getTargetData() const { return &DataLayout; } Copied: llvm/trunk/lib/Target/TargetRegisterInfo.cpp (from r46597, llvm/trunk/lib/Target/MRegisterInfo.cpp) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetRegisterInfo.cpp?p2=llvm/trunk/lib/Target/TargetRegisterInfo.cpp&p1=llvm/trunk/lib/Target/MRegisterInfo.cpp&r1=46597&r2=46930&rev=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/MRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/TargetRegisterInfo.cpp Sun Feb 10 12:45:23 2008 @@ -1,4 +1,4 @@ -//===- MRegisterInfo.cpp - Target Register Information Implementation -----===// +//===- TargetRegisterInfo.cpp - Target Register Information Implementation ===// // // The LLVM Compiler Infrastructure // @@ -7,12 +7,12 @@ // //===----------------------------------------------------------------------===// // -// This file implements the MRegisterInfo interface. +// This file implements the TargetRegisterInfo interface. // //===----------------------------------------------------------------------===// #include "llvm/Target/TargetMachine.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFrameInfo.h" @@ -20,7 +20,7 @@ using namespace llvm; -MRegisterInfo::MRegisterInfo(const TargetRegisterDesc *D, unsigned NR, +TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR, regclass_iterator RCB, regclass_iterator RCE, int CFSO, int CFDO) : Desc(D), NumRegs(NR), RegClassBegin(RCB), RegClassEnd(RCE) { @@ -31,12 +31,12 @@ CallFrameDestroyOpcode = CFDO; } -MRegisterInfo::~MRegisterInfo() {} +TargetRegisterInfo::~TargetRegisterInfo() {} /// getPhysicalRegisterRegClass - Returns the Register Class of a physical /// register. const TargetRegisterClass * -MRegisterInfo::getPhysicalRegisterRegClass(MVT::ValueType VT, +TargetRegisterInfo::getPhysicalRegisterRegClass(MVT::ValueType VT, unsigned reg) const { assert(isPhysicalRegister(reg) && "reg must be a physical register"); // Pick the register class of the right type that contains this physreg. @@ -57,15 +57,15 @@ R.set(*I); } -BitVector MRegisterInfo::getAllocatableSet(MachineFunction &MF, - const TargetRegisterClass *RC) const { +BitVector TargetRegisterInfo::getAllocatableSet(MachineFunction &MF, + const TargetRegisterClass *RC) const { BitVector Allocatable(NumRegs); if (RC) { getAllocatableSetForRC(MF, RC, Allocatable); return Allocatable; } - for (MRegisterInfo::regclass_iterator I = regclass_begin(), + for (TargetRegisterInfo::regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I) getAllocatableSetForRC(MF, *I, Allocatable); return Allocatable; @@ -74,7 +74,7 @@ /// getFrameIndexOffset - Returns the displacement from the frame register to /// the stack frame of the specified index. This is the default implementation /// which is likely incorrect for the target. -int MRegisterInfo::getFrameIndexOffset(MachineFunction &MF, unsigned FI) const { +int TargetRegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const { const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo(); MachineFrameInfo *MFI = MF.getFrameInfo(); return MFI->getObjectOffset(FI) + MFI->getStackSize() - @@ -84,7 +84,7 @@ /// getInitialFrameState - Returns a list of machine moves that are assumed /// on entry to a function. void -MRegisterInfo::getInitialFrameState(std::vector &Moves) const { +TargetRegisterInfo::getInitialFrameState(std::vector &Moves) const { // Default is to do nothing. } Modified: llvm/trunk/lib/Target/X86/X86ATTAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ATTAsmPrinter.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ATTAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ATTAsmPrinter.cpp Sun Feb 10 12:45:23 2008 @@ -216,10 +216,10 @@ void X86ATTAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo, const char *Modifier, bool NotRIPRel) { const MachineOperand &MO = MI->getOperand(OpNo); - const MRegisterInfo &RI = *TM.getRegisterInfo(); + const TargetRegisterInfo &RI = *TM.getRegisterInfo(); switch (MO.getType()) { case MachineOperand::MO_Register: { - assert(MRegisterInfo::isPhysicalRegister(MO.getReg()) && + assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && "Virtual registers should not make it this far!"); O << '%'; unsigned Reg = MO.getReg(); @@ -553,7 +553,7 @@ bool X86ATTAsmPrinter::printAsmMRegister(const MachineOperand &MO, const char Mode) { - const MRegisterInfo &RI = *TM.getRegisterInfo(); + const TargetRegisterInfo &RI = *TM.getRegisterInfo(); unsigned Reg = MO.getReg(); switch (Mode) { default: return true; // Unknown mode. Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Sun Feb 10 12:45:23 2008 @@ -569,7 +569,7 @@ const TargetRegisterClass *clas; for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op) { if (I->getOperand(op).isRegister() && I->getOperand(op).isDef() && - MRegisterInfo::isVirtualRegister(I->getOperand(op).getReg()) && + TargetRegisterInfo::isVirtualRegister(I->getOperand(op).getReg()) && ((clas = RegInfo->getRegClass(I->getOperand(0).getReg())) == X86::RFP32RegisterClass || clas == X86::RFP64RegisterClass || Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sun Feb 10 12:45:23 2008 @@ -1051,7 +1051,7 @@ if (Op.getOpcode() == ISD::FORMAL_ARGUMENTS || (Op.getOpcode()== ISD::CopyFromReg && (OpReg = cast(Op.getOperand(1))) && - OpReg->getReg() >= MRegisterInfo::FirstVirtualRegister)) + OpReg->getReg() >= TargetRegisterInfo::FirstVirtualRegister)) return true; return false; } Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Sun Feb 10 12:45:23 2008 @@ -445,7 +445,7 @@ /// Subtarget - Keep a pointer to the X86Subtarget around so that we can /// make the right decision when generating code for different targets. const X86Subtarget *Subtarget; - const MRegisterInfo *RegInfo; + const TargetRegisterInfo *RegInfo; /// X86StackPtr - X86 physical register used as stack ptr. unsigned X86StackPtr; Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.h (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.h Sun Feb 10 12:45:23 2008 @@ -17,7 +17,7 @@ #include "llvm/Target/TargetInstrInfo.h" #include "X86RegisterInfo.h" #include "llvm/ADT/IndexedMap.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" namespace llvm { class X86RegisterInfo; @@ -245,7 +245,7 @@ /// such, whenever a client has an instance of instruction info, it should /// always be able to get register info as well (through this method). /// - virtual const MRegisterInfo &getRegisterInfo() const { return RI; } + virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; } // Return true if the instruction is a register to register move and // leave the source and dest operands in the passed parameters. Modified: llvm/trunk/lib/Target/X86/X86IntelAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86IntelAsmPrinter.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86IntelAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/X86/X86IntelAsmPrinter.cpp Sun Feb 10 12:45:23 2008 @@ -114,10 +114,10 @@ void X86IntelAsmPrinter::printOp(const MachineOperand &MO, const char *Modifier) { - const MRegisterInfo &RI = *TM.getRegisterInfo(); + const TargetRegisterInfo &RI = *TM.getRegisterInfo(); switch (MO.getType()) { case MachineOperand::MO_Register: { - if (MRegisterInfo::isPhysicalRegister(MO.getReg())) { + if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) { unsigned Reg = MO.getReg(); if (Modifier && strncmp(Modifier, "subreg", strlen("subreg")) == 0) { MVT::ValueType VT = (strcmp(Modifier,"subreg64") == 0) ? @@ -252,7 +252,7 @@ bool X86IntelAsmPrinter::printAsmMRegister(const MachineOperand &MO, const char Mode) { - const MRegisterInfo &RI = *TM.getRegisterInfo(); + const TargetRegisterInfo &RI = *TM.getRegisterInfo(); unsigned Reg = MO.getReg(); switch (Mode) { default: return true; // Unknown mode. Modified: llvm/trunk/lib/Target/X86/X86IntelAsmPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86IntelAsmPrinter.h?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86IntelAsmPrinter.h (original) +++ llvm/trunk/lib/Target/X86/X86IntelAsmPrinter.h Sun Feb 10 12:45:23 2008 @@ -16,7 +16,7 @@ #include "X86AsmPrinter.h" #include "llvm/CodeGen/ValueTypes.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" namespace llvm { @@ -41,7 +41,8 @@ const char *Modifier = 0) { const MachineOperand &MO = MI->getOperand(OpNo); if (MO.isRegister()) { - assert(MRegisterInfo::isPhysicalRegister(MO.getReg()) && "Not physreg??"); + assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && + "Not physreg??"); O << TM.getRegisterInfo()->get(MO.getReg()).Name; } else { printOp(MO, Modifier); Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Sun Feb 10 12:45:23 2008 @@ -7,8 +7,9 @@ // //===----------------------------------------------------------------------===// // -// This file contains the X86 implementation of the MRegisterInfo class. This -// file is responsible for the frame pointer elimination optimization on X86. +// This file contains the X86 implementation of the TargetRegisterInfo class. +// This file is responsible for the frame pointer elimination optimization +// on X86. // //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.h?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86RegisterInfo.h (original) +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.h Sun Feb 10 12:45:23 2008 @@ -7,7 +7,7 @@ // //===----------------------------------------------------------------------===// // -// This file contains the X86 implementation of the MRegisterInfo class. +// This file contains the X86 implementation of the TargetRegisterInfo class. // //===----------------------------------------------------------------------===// @@ -16,7 +16,7 @@ #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/SmallVector.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "X86GenRegisterInfo.h.inc" namespace llvm { Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.td?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86RegisterInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.td Sun Feb 10 12:45:23 2008 @@ -249,7 +249,7 @@ GR8Class::iterator GR8Class::allocation_order_begin(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const MRegisterInfo *RI = TM.getRegisterInfo(); + const TargetRegisterInfo *RI = TM.getRegisterInfo(); const X86Subtarget &Subtarget = TM.getSubtarget(); if (!Subtarget.is64Bit()) return X86_GR8_AO_32; @@ -262,7 +262,7 @@ GR8Class::iterator GR8Class::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const MRegisterInfo *RI = TM.getRegisterInfo(); + const TargetRegisterInfo *RI = TM.getRegisterInfo(); const X86Subtarget &Subtarget = TM.getSubtarget(); if (!Subtarget.is64Bit()) return X86_GR8_AO_32 + (sizeof(X86_GR8_AO_32) / sizeof(unsigned)); @@ -303,7 +303,7 @@ GR16Class::iterator GR16Class::allocation_order_begin(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const MRegisterInfo *RI = TM.getRegisterInfo(); + const TargetRegisterInfo *RI = TM.getRegisterInfo(); const X86Subtarget &Subtarget = TM.getSubtarget(); if (Subtarget.is64Bit()) { if (RI->hasFP(MF)) @@ -321,7 +321,7 @@ GR16Class::iterator GR16Class::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const MRegisterInfo *RI = TM.getRegisterInfo(); + const TargetRegisterInfo *RI = TM.getRegisterInfo(); const X86Subtarget &Subtarget = TM.getSubtarget(); if (Subtarget.is64Bit()) { if (RI->hasFP(MF)) @@ -367,7 +367,7 @@ GR32Class::iterator GR32Class::allocation_order_begin(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const MRegisterInfo *RI = TM.getRegisterInfo(); + const TargetRegisterInfo *RI = TM.getRegisterInfo(); const X86Subtarget &Subtarget = TM.getSubtarget(); if (Subtarget.is64Bit()) { if (RI->hasFP(MF)) @@ -385,7 +385,7 @@ GR32Class::iterator GR32Class::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const MRegisterInfo *RI = TM.getRegisterInfo(); + const TargetRegisterInfo *RI = TM.getRegisterInfo(); const X86Subtarget &Subtarget = TM.getSubtarget(); if (Subtarget.is64Bit()) { if (RI->hasFP(MF)) @@ -414,7 +414,7 @@ GR64Class::iterator GR64Class::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const MRegisterInfo *RI = TM.getRegisterInfo(); + const TargetRegisterInfo *RI = TM.getRegisterInfo(); if (RI->hasFP(MF)) // Does the function dedicate RBP to being a frame ptr? return end()-2; // If so, don't allocate RSP or RBP else Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.h?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86TargetMachine.h (original) +++ llvm/trunk/lib/Target/X86/X86TargetMachine.h Sun Feb 10 12:45:23 2008 @@ -49,7 +49,7 @@ virtual X86TargetLowering *getTargetLowering() const { return const_cast(&TLInfo); } - virtual const MRegisterInfo *getRegisterInfo() const { + virtual const TargetRegisterInfo *getRegisterInfo() const { return &InstrInfo.getRegisterInfo(); } virtual const TargetData *getTargetData() const { return &DataLayout; } Modified: llvm/trunk/test/TableGen/TargetInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/TableGen/TargetInstrInfo.td?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/test/TableGen/TargetInstrInfo.td (original) +++ llvm/trunk/test/TableGen/TargetInstrInfo.td Sun Feb 10 12:45:23 2008 @@ -83,7 +83,7 @@ // 6. Address expressions should become first-class entities. // Simple copy instruction. isMoveInstr could easily be inferred from this, -// as could MRegisterInfo::copyRegToReg. +// as could TargetRegisterInfo::copyRegToReg. def MOV8rr : Inst<(ops R8:$dst, R8:$src), "mov $dst, $src", 0x88, MRMDestReg, [(set R8:$dst, R8:$src)]>; Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Sun Feb 10 12:45:23 2008 @@ -52,12 +52,12 @@ const std::string &TargetName = Target.getName(); std::string ClassName = TargetName + "GenRegisterInfo"; - OS << "#include \"llvm/Target/MRegisterInfo.h\"\n"; + OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n"; OS << "#include \n\n"; OS << "namespace llvm {\n\n"; - OS << "struct " << ClassName << " : public MRegisterInfo {\n" + OS << "struct " << ClassName << " : public TargetRegisterInfo {\n" << " " << ClassName << "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n" << " virtual int getDwarfRegNumFull(unsigned RegNum, " @@ -588,7 +588,7 @@ // Emit the constructor of the class... OS << ClassName << "::" << ClassName << "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n" - << " : MRegisterInfo(RegisterDescriptors, " << Registers.size()+1 + << " : TargetRegisterInfo(RegisterDescriptors, " << Registers.size()+1 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n " << " CallFrameSetupOpcode, CallFrameDestroyOpcode) {}\n\n"; Modified: llvm/trunk/win32/Target/Target.vcproj URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/win32/Target/Target.vcproj?rev=46930&r1=46929&r2=46930&view=diff ============================================================================== --- llvm/trunk/win32/Target/Target.vcproj (original) +++ llvm/trunk/win32/Target/Target.vcproj Sun Feb 10 12:45:23 2008 @@ -305,7 +305,7 @@ UniqueIdentifier="{4FC737F1-C7A5-4376-A066-2A32D752A2FF}" > Author: sampo Date: Sun Feb 10 12:47:57 2008 New Revision: 46931 URL: http://llvm.org/viewvc/llvm-project?rev=46931&view=rev Log: xmm0 variable blends Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=46931&r1=46930&r2=46931&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Sun Feb 10 12:47:57 2008 @@ -3223,7 +3223,7 @@ def rri : SS4AI, OpSize { @@ -3232,7 +3232,7 @@ def rmi : SS4AI, @@ -3254,6 +3254,31 @@ int_x86_sse41_mpsadbw, 0>; +/// SS41I_binop_rmi_int - SSE 4.1 binary operator with immediate +let isTwoAddress = 1 in { + multiclass SS41I_ternary_int opc, string OpcodeStr, Intrinsic IntId> { + def rr0 : SS48I, + OpSize; + + def rm0 : SS48I, OpSize; + } +} + +defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>; +defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>; +defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>; + + multiclass SS41I_binop_rm_int8 opc, string OpcodeStr, Intrinsic IntId> { def rr : SS48I Author: lattner Date: Sun Feb 10 13:05:37 2008 New Revision: 46932 URL: http://llvm.org/viewvc/llvm-project?rev=46932&view=rev Log: Fix scalarrepl to not 'miscompile' undefined code, part #2. This fixes the store case, my previous patch just fixed the load case. rdar://5707076. Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=46932&r1=46931&r2=46932&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Sun Feb 10 13:05:37 2008 @@ -1150,7 +1150,7 @@ // then 'or' into place. Value *SV = SI->getOperand(0); const Type *AllocaType = NewAI->getType()->getElementType(); - if (SV->getType() == AllocaType) { + if (SV->getType() == AllocaType && Offset == 0) { // All is well. } else if (const VectorType *PTy = dyn_cast(AllocaType)) { Value *Old = new LoadInst(NewAI, NewAI->getName()+".in", SI); From clattner at apple.com Sun Feb 10 13:08:15 2008 From: clattner at apple.com (Chris Lattner) Date: Sun, 10 Feb 2008 11:08:15 -0800 Subject: [llvm-commits] [llvm] r46930 - in /llvm/trunk: Xcode/LLVM.xcodeproj/ docs/ include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/CellSPU/ lib/Target/IA64/ lib/Target/Mips/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/X86/ test/TableGen/ utils/TableGen/ win32/Target/ In-Reply-To: <200802101845.m1AIjSxP026087@zion.cs.uiuc.edu> References: <200802101845.m1AIjSxP026087@zion.cs.uiuc.edu> Message-ID: <33C65A8E-B6DE-475D-9F38-51714708F5C7@apple.com> On Feb 10, 2008, at 10:45 AM, Dan Gohman wrote: > Author: djg > Date: Sun Feb 10 12:45:23 2008 > New Revision: 46930 > > URL: http://llvm.org/viewvc/llvm-project?rev=46930&view=rev > Log: > Rename MRegisterInfo to TargetRegisterInfo. Whoa, excellent! We've needed this for a long time, -Chris From sabre at nondot.org Sun Feb 10 13:09:03 2008 From: sabre at nondot.org (Chris Lattner) Date: Sun, 10 Feb 2008 11:09:03 -0800 Subject: [llvm-commits] [llvm] r46108 - in /llvm/trunk: lib/Transforms/IPO/ArgumentPromotion.cpp test/Transforms/ArgumentPromotion/attrs.ll In-Reply-To: <200801171045.02711.duncan.sands@math.u-psud.fr> References: <200801170117.m0H1H3mE001661@zion.cs.uiuc.edu> <200801171045.02711.duncan.sands@math.u-psud.fr> Message-ID: <69290D90-47D6-4D31-AB6D-FE8A4864BA9E@nondot.org> On Jan 17, 2008, at 1:45 AM, Duncan Sands wrote: > Hi Chris, > >> Fix arg promotion to propagate the correct attrs on the calls to >> promoted functions. This is important for varargs calls in >> particular. Thanks to duncan for providing a great testcase. > > you forgot about attributes on the function return value. Hi Duncan, I've lost the context for this, do you remember what this was about? -Chris From sabre at nondot.org Sun Feb 10 13:11:04 2008 From: sabre at nondot.org (Chris Lattner) Date: Sun, 10 Feb 2008 19:11:04 -0000 Subject: [llvm-commits] [llvm] r46933 - in /llvm/trunk/docs/tutorial: JITTutorial1.html JITTutorial2.html LangImpl1.html LangImpl2.html LangImpl3.html LangImpl4.html LangImpl5.html LangImpl6.html LangImpl7.html Message-ID: <200802101911.m1AJB5wL026903@zion.cs.uiuc.edu> Author: lattner Date: Sun Feb 10 13:11:04 2008 New Revision: 46933 URL: http://llvm.org/viewvc/llvm-project?rev=46933&view=rev Log: Various updates from Sam Bishop: "I have been working my way through the JIT and Kaleidoscope tutorials in my (minuscule) spare time. Thanks again for writing them! I have attached a patch containing some minor changes, ranging from spelling and grammar fixes to adding a "Next: " hyperlink to the bottom of each page. Every page has been given the "next link" treatment, but otherwise I'm only half way through the Kaleidoscope tutorial. I will send a follow-on patch if time permits." Modified: llvm/trunk/docs/tutorial/JITTutorial1.html llvm/trunk/docs/tutorial/JITTutorial2.html llvm/trunk/docs/tutorial/LangImpl1.html llvm/trunk/docs/tutorial/LangImpl2.html llvm/trunk/docs/tutorial/LangImpl3.html llvm/trunk/docs/tutorial/LangImpl4.html llvm/trunk/docs/tutorial/LangImpl5.html llvm/trunk/docs/tutorial/LangImpl6.html llvm/trunk/docs/tutorial/LangImpl7.html Modified: llvm/trunk/docs/tutorial/JITTutorial1.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/tutorial/JITTutorial1.html?rev=46933&r1=46932&r2=46933&view=diff ============================================================================== --- llvm/trunk/docs/tutorial/JITTutorial1.html (original) +++ llvm/trunk/docs/tutorial/JITTutorial1.html Sun Feb 10 13:11:04 2008 @@ -25,7 +25,7 @@
      -

      For starters, lets consider a relatively straightforward function that takes three integer parameters and returns an arithmetic combination of them. This is nice and simple, especially since it involves no control flow:

      +

      For starters, let's consider a relatively straightforward function that takes three integer parameters and returns an arithmetic combination of them. This is nice and simple, especially since it involves no control flow:

      @@ -86,7 +86,7 @@
      -

      The first segment is pretty simple: it creates an LLVM ???module.??? In LLVM, a module represents a single unit of code that is to be processed together. A module contains things like global variables and function declarations and implementations. Here, we???ve declared a makeLLVMModule() function to do the real work of creating the module. Don???t worry, we???ll be looking at that one next!

      +

      The first segment is pretty simple: it creates an LLVM ???module.??? In LLVM, a module represents a single unit of code that is to be processed together. A module contains things like global variables, function declarations, and implementations. Here we???ve declared a makeLLVMModule() function to do the real work of creating the module. Don???t worry, we???ll be looking at that one next!

      The second segment runs the LLVM module verifier on our newly created module. While this probably isn???t really necessary for a simple module like this one, it???s always a good idea, especially if you???re generating LLVM IR based on some input. The verifier will print an error message if your LLVM module is malformed in any way.

      @@ -106,7 +106,7 @@ 
      -  Constant* c = mod->getOrInsertFunction("mul_add",
+  Constant* c = mod->getOrInsertFunction("mul_add",
   /*ret type*/                           IntegerType::get(32),
   /*args*/                               IntegerType::get(32),
                                          IntegerType::get(32),
@@ -114,31 +114,31 @@
   /*varargs terminated with null*/       NULL);
   
   Function* mul_add = cast<Function>(c);
-  mul_add->setCallingConv(CallingConv::C);
+  mul_add->setCallingConv(CallingConv::C);
      -

      We construct our Function by calling getOrInsertFunction() on our module, passing in the name, return type, and argument types of the function. In the case of our mul_add function, that means one 32-bit integer for the return value, and three 32-bit integers for the arguments.

      +

      We construct our Function by calling getOrInsertFunction() on our module, passing in the name, return type, and argument types of the function. In the case of our mul_add function, that means one 32-bit integer for the return value and three 32-bit integers for the arguments.

      -

      You'll notice that getOrInsertFunction doesn't actually return a Function*. This is because, if the function already existed, but with a different prototype, getOrInsertFunction will return a cast of the existing function to the desired prototype. Since we know that there's not already a mul_add function, we can safely just cast c to a Function*. +

      You'll notice that getOrInsertFunction() doesn't actually return a Function*. This is because getOrInsertFunction() will return a cast of the existing function if the function already existed with a different prototype. Since we know that there's not already a mul_add function, we can safely just cast c to a Function*.

      In addition, we set the calling convention for our new function to be the C calling convention. This isn???t strictly necessary, but it insures that our new function will interoperate properly with C code, which is a good thing.

      -  Function::arg_iterator args = mul_add->arg_begin();
+  Function::arg_iterator args = mul_add->arg_begin();
   Value* x = args++;
-  x->setName("x");
+  x->setName("x");
   Value* y = args++;
-  y->setName("y");
+  y->setName("y");
   Value* z = args++;
-  z->setName("z");
+  z->setName("z");
      -

      While we???re setting up our function, let???s also give names to the parameters. This also isn???t strictly necessary (LLVM will generate names for them if you don???t specify them), but it???ll make looking at our output somewhat more pleasant. To name the parameters, we iterator over the arguments of our function, and call setName() on them. We???ll also keep the pointer to x, y, and z around, since we???ll need them when we get around to creating instructions.

      +

      While we???re setting up our function, let???s also give names to the parameters. This also isn???t strictly necessary (LLVM will generate names for them if you don???t specify them), but it???ll make looking at our output somewhat more pleasant. To name the parameters, we iterate over the arguments of our function and call setName() on them. We???ll also keep the pointer to x, y, and z around, since we???ll need them when we get around to creating instructions.

      -

      Great! We have a function now. But what good is a function if it has no body? Before we start working on a body for our new function, we need to recall some details of the LLVM IR. The IR, being an abstract assembly language, represents control flow using jumps (we call them branches), both conditional and unconditional. The straight-line sequences of code between branches are called basic blocks, or just blocks. To create a body for our function, we fill it with blocks!

      +

      Great! We have a function now. But what good is a function if it has no body? Before we start working on a body for our new function, we need to recall some details of the LLVM IR. The IR, being an abstract assembly language, represents control flow using jumps (we call them branches), both conditional and unconditional. The straight-line sequences of code between branches are called basic blocks, or just blocks. To create a body for our function, we fill it with blocks:

      @@ -165,17 +165,18 @@
 
 
      The final step in creating our function is to create the instructions that make it up.  Our mul_add function is composed of just three instructions: a multiply, an add, and a return.  LLVMBuilder gives us a simple interface for constructing these instructions and appending them to the ???entry??? block.  Each of the calls to LLVMBuilder returns a Value* that represents the value yielded by the instruction.  You???ll also notice that, above, x, y, and z are also Value*???s, so it???s clear that instructions operate on Value*???s.
      
 
-
      And that???s it!  Now you can compile and run your code, and get a wonderful textual print out of the LLVM IR we saw at the beginning.  To compile, use the following commandline as a guide:
      
+
      And that???s it!  Now you can compile and run your code, and get a wonderful textual print out of the LLVM IR we saw at the beginning.  To compile, use the following command line as a guide:
      
 
 
      
 
      -# c++ -g tut2.cpp `llvm-config --cppflags --ldflags --libs core` -o tut2
-# ./tut2
+# c++ -g tut1.cpp `llvm-config --cppflags --ldflags --libs core` -o tut1
+# ./tut1
 
      
 
      
 
 
      The llvm-config utility is used to obtain the necessary GCC-compatible compiler flags for linking with LLVM.  For this example, we only need the 'core' library.  We'll use others once we start adding optimizers and the JIT engine.
      
 
+Next: A More Complicated Function
      Modified: llvm/trunk/docs/tutorial/JITTutorial2.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/tutorial/JITTutorial2.html?rev=46933&r1=46932&r2=46933&view=diff ============================================================================== --- llvm/trunk/docs/tutorial/JITTutorial2.html (original) +++ llvm/trunk/docs/tutorial/JITTutorial2.html Sun Feb 10 13:11:04 2008 @@ -32,7 +32,7 @@ unsigned gcd(unsigned x, unsigned y) { if(x == y) { return x; - } else if(x < y) { + } else if(x < y) { return gcd(x, y - x); } else { return gcd(x - y, y); @@ -45,7 +45,7 @@
      GCD CFG
      -

      The above is a graphical representation of a program in LLVM IR. It places each basic block on a node of a graph, and uses directed edges to indicate flow control. These blocks will be serialized when written to a text or bitcode file, but it is often useful conceptually to think of them as a graph. Again, if you are unsure about the code in the diagram, you should skim through the LLVM Language Reference Manual and convince yourself that it is, in fact, the GCD algorithm.

      +

      This is a graphical representation of a program in LLVM IR. It places each basic block on a node of a graph and uses directed edges to indicate flow control. These blocks will be serialized when written to a text or bitcode file, but it is often useful conceptually to think of them as a graph. Again, if you are unsure about the code in the diagram, you should skim through the LLVM Language Reference Manual and convince yourself that it is, in fact, the GCD algorithm.

      The first part of our code is practically the same as from the first tutorial. The same basic setup is required: creating a module, verifying it, and running the PrintModulePass on it. Even the first segment of makeLLVMModule() looks essentially the same, except that gcd takes one fewer parameter than mul_add.

      @@ -94,7 +94,7 @@

      Here, however, is where our code begins to diverge from the first tutorial. Because gcd has control flow, it is composed of multiple blocks interconnected by branching (br) instructions. For those familiar with assembly language, a block is similar to a labeled set of instructions. For those not familiar with assembly language, a block is basically a set of instructions that can be branched to and is executed linearly until the block is terminated by one of a small number of control flow instructions, such as br or ret.

      -

      Blocks corresponds to the nodes in the diagram we looked at in the beginning of this tutorial. From the diagram, we can see that this function contains five blocks, so we'll go ahead and create them. Note that, in this code sample, we're making use of LLVM's automatic name uniquing, since we're giving two blocks the same name.

      +

      Blocks correspond to the nodes in the diagram we looked at in the beginning of this tutorial. From the diagram, we can see that this function contains five blocks, so we'll go ahead and create them. Note that we're making use of LLVM's automatic name uniquing in this code sample, since we're giving two blocks the same name.

      @@ -106,7 +106,7 @@
      -

      Now, we're ready to begin generate code! We'll start with the entry block. This block corresponds to the top-level if-statement in the original C code, so we need to compare x == y To achieve this, we perform an explicity comparison using ICmpEQ. ICmpEQ stands for an integer comparison for equality and returns a 1-bit integer result. This 1-bit result is then used as the input to a conditional branch, with ret as the true and cond_false as the false case.

      +

      Now we're ready to begin generating code! We'll start with the entry block. This block corresponds to the top-level if-statement in the original C code, so we need to compare x and y. To achieve this, we perform an explicit comparison using ICmpEQ. ICmpEQ stands for an integer comparison for equality and returns a 1-bit integer result. This 1-bit result is then used as the input to a conditional branch, with ret as the true and cond_false as the false case.

      @@ -116,7 +116,7 @@
      -

      Our next block, ret, is pretty simple: it just returns the value of x. Recall that this block is only reached if x == y, so this is the correct behavior. Notice that, instead of creating a new LLVMBuilder for each block, we can use SetInsertPoint to retarget our existing one. This saves on construction and memory allocation costs.

      +

      Our next block, ret, is pretty simple: it just returns the value of x. Recall that this block is only reached if x == y, so this is the correct behavior. Notice that instead of creating a new LLVMBuilder for each block, we can use SetInsertPoint to retarget our existing one. This saves on construction and memory allocation costs.

      @@ -127,7 +127,7 @@
 
 
      cond_false is a more interesting block: we now know that x != y, so we must branch again to determine which of x and y is larger.  This is achieved using the ICmpULT instruction, which stands for integer comparison for unsigned less-than.  In LLVM, integer types do not carry sign; a 32-bit integer pseudo-register can interpreted as signed or unsigned without casting.  Whether a signed or unsigned interpretation is desired is specified in the instruction.  This is why several instructions in the LLVM IR, such as integer less-than, include a specifier for signed or unsigned.
      
 
-
      Also, note that we're again making use of LLVM's automatic name uniquing, this time at a register level.  We've deliberately chosen to name every instruction "tmp", to illustrate that LLVM will give them all unique names without getting confused.
      
+
      Also note that we're again making use of LLVM's automatic name uniquing, this time at a register level.  We've deliberately chosen to name every instruction "tmp" to illustrate that LLVM will give them all unique names without getting confused.
      
 
 
      
 
      
Modified: llvm/trunk/docs/tutorial/LangImpl1.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/tutorial/LangImpl1.html?rev=46933&r1=46932&r2=46933&view=diff

==============================================================================
--- llvm/trunk/docs/tutorial/LangImpl1.html (original)
+++ llvm/trunk/docs/tutorial/LangImpl1.html Sun Feb 10 13:11:04 2008
@@ -54,9 +54,10 @@
 modern and sane software engineering principles.  In practice, this means that
 we'll take a number of shortcuts to simplify the exposition.  For example, the
 code leaks memory, uses global variables all over the place, doesn't use nice
-design patterns like visitors, etc... but it is very simple.  If you dig in and
-use the code as a basis for future projects, fixing these deficiencies shouldn't
-be hard.
      
+design patterns like visitors, etc... but it
+is very simple.  If you dig in and use the code as a basis for future projects,
+fixing these deficiencies shouldn't be hard.
      
 
 
      I've tried to put this tutorial together in a way that makes chapters easy to
 skip over if you are already familiar with or are uninterested in the various
@@ -328,6 +329,7 @@
 so that you can use the lexer and parser together.
 
      
 
+Next: Implementing a Parser and AST
 
      
 
 

Modified: llvm/trunk/docs/tutorial/LangImpl2.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/tutorial/LangImpl2.html?rev=46933&r1=46932&r2=46933&view=diff

==============================================================================
--- llvm/trunk/docs/tutorial/LangImpl2.html (original)
+++ llvm/trunk/docs/tutorial/LangImpl2.html Sun Feb 10 13:11:04 2008
@@ -98,7 +98,7 @@
 
      Right now we only create the AST,  so there are no useful accessor methods on
 them.  It would be very easy to add a virtual method to pretty print the code,
 for example.  Here are the other expression AST node definitions that we'll use
-in the basic form of the Kaleidoscope language.
+in the basic form of the Kaleidoscope language:
 
      
 
 
      
@@ -130,7 +130,7 @@
      -

      This is all (intentially) rather straight-forward: variables capture the +

      This is all (intentionally) rather straight-forward: variables capture the variable name, binary operators capture their opcode (e.g. '+'), and calls capture a function name as well as a list of any argument expressions. One thing that is nice about our AST is that it captures the language features without @@ -201,7 +201,7 @@ 

       /// CurTok/getNextToken - Provide a simple token buffer.  CurTok is the current
-/// token the parser it looking at.  getNextToken reads another token from the
+/// token the parser is looking at.  getNextToken reads another token from the
 /// lexer and updates CurTok with its results.
 static int CurTok;
 static int getNextToken() {
@@ -263,11 +263,11 @@
 
 
      This routine is very simple: it expects to be called when the current token
 is a tok_number token.  It takes the current number value, creates 
-a NumberExprAST node, advances the lexer to the next token and finally
+a NumberExprAST node, advances the lexer to the next token, and finally
 returns.
      
 
 
      There are some interesting aspects to this.  The most important one is that
-this routine eats all of the tokens that correspond to the production, and
+this routine eats all of the tokens that correspond to the production and
 returns the lexer buffer with the next token (which is not part of the grammar
 production) ready to go.  This is a fairly standard way to go for recursive
 descent parsers.  For a better example, the parenthesis operator is defined like
@@ -293,7 +293,7 @@
 parser:
      
 
 
      
-1) it shows how we use the Error routines.  When called, this function expects
+1) It shows how we use the Error routines.  When called, this function expects
 that the current token is a '(' token, but after parsing the subexpression, it
 is possible that there is no ')' waiting.  For example, if the user types in
 "(4 x" instead of "(4)", the parser should emit an error.  Because errors can
@@ -305,8 +305,8 @@
 ParseParenExpr).  This is powerful because it allows us to handle 
 recursive grammars, and keeps each production very simple.  Note that
 parentheses do not cause construction of AST nodes themselves.  While we could
-do it this way, the most important role of parens are to guide the parser and
-provide grouping.  Once the parser constructs the AST, parens are not 
+do it this way, the most important role of parentheses are to guide the parser
+and provide grouping.  Once the parser constructs the AST, parentheses are not
 needed.
      
 
 
      The next simple production is for handling variable references and function
@@ -350,21 +350,21 @@
      -

      This routine follows the same style as the other routines (it expects to be +

      This routine follows the same style as the other routines. (It expects to be called if the current token is a tok_identifier token). It also has recursion and error handling. One interesting aspect of this is that it uses look-ahead to determine if the current identifier is a stand alone variable reference or if it is a function call expression. It handles this by -checking to see if the token after the identifier is a '(' token, and constructs +checking to see if the token after the identifier is a '(' token, constructing either a VariableExprAST or CallExprAST node as appropriate.

      -

      Now that we have all of our simple expression parsing logic in place, we can -define a helper function to wrap it together into one entry-point. We call this +

      Now that we have all of our simple expression-parsing logic in place, we can +define a helper function to wrap it together into one entry point. We call this class of expressions "primary" expressions, for reasons that will become more clear later in the tutorial. In order to parse an arbitrary primary expression, we need to determine what sort of -specific expression it is:

      +expression it is:

      @@ -383,13 +383,13 @@
      -

      Now that you see the definition of this function, it makes it more obvious -why we can assume the state of CurTok in the various functions. This uses -look-ahead to determine which sort of expression is being inspected, and parses -it with a function call.

      +

      Now that you see the definition of this function, it is more obvious why we +can assume the state of CurTok in the various functions. This uses look-ahead +to determine which sort of expression is being inspected, and then parses it +with a function call.

      -

      Now that basic expressions are handled, we need to handle binary expressions, -which are a bit more complex.

      +

      Now that basic expressions are handled, we need to handle binary expressions. +They are a bit more complex.

      @@ -447,12 +447,12 @@ or -1 if the token is not a binary operator. Having a map makes it easy to add new operators and makes it clear that the algorithm doesn't depend on the specific operators involved, but it would be easy enough to eliminate the map -and do the comparisons in the GetTokPrecedence function (or just use +and do the comparisons in the GetTokPrecedence function. (Or just use a fixed-size array).

      With the helper above defined, we can now start parsing binary expressions. The basic idea of operator precedence parsing is to break down an expression -with potentially ambiguous binary operators into pieces. Consider for example +with potentially ambiguous binary operators into pieces. Consider ,for example, the expression "a+b+(c+d)*e*f+g". Operator precedence parsing considers this as a stream of primary expressions separated by binary operators. As such, it will first parse the leading primary expression "a", then it will see the @@ -708,7 +708,7 @@ -

      Now that we have all the pieces, lets build a little driver that will let us +

      Now that we have all the pieces, let's build a little driver that will let us actually execute this code we've built!

      @@ -732,7 +732,7 @@ fprintf(stderr, "ready> "); switch (CurTok) { case tok_eof: return; - case ';': getNextToken(); break; // ignore top level semicolons. + case ';': getNextToken(); break; // ignore top-level semicolons. case tok_def: HandleDefinition(); break; case tok_extern: HandleExtern(); break; default: HandleTopLevelExpression(); break; @@ -742,13 +742,13 @@ -

      The most interesting part of this is that we ignore top-level semi colons. +

      The most interesting part of this is that we ignore top-level semicolons. Why is this, you ask? The basic reason is that if you type "4 + 5" at the command line, the parser doesn't know whether that is the end of what you will type or not. For example, on the next line you could type "def foo..." in which case 4+5 is the end of a top-level expression. Alternatively you could type "* 6", which would continue the expression. Having top-level semicolons allows you to -type "4+5;" and the parser will know you are done.

      +type "4+5;", and the parser will know you are done.

      @@ -760,8 +760,8 @@

      With just under 400 lines of commented code (240 lines of non-comment, non-blank code), we fully defined our minimal language, including a lexer, -parser and AST builder. With this done, the executable will validate -Kaleidoscope code and tell us if it is gramatically invalid. For +parser, and AST builder. With this done, the executable will validate +Kaleidoscope code and tell us if it is grammatically invalid. For example, here is a sample interaction:

      @@ -798,8 +798,8 @@

      Here is the complete code listing for this and the previous chapter. Note that it is fully self-contained: you don't need LLVM or any external -libraries at all for this (other than the C and C++ standard libraries of -course). To build this, just compile with:

      +libraries at all for this. (Besides the C and C++ standard libraries, of +course.) To build this, just compile with:

      @@ -955,7 +955,7 @@
 //===----------------------------------------------------------------------===//
 
 /// CurTok/getNextToken - Provide a simple token buffer.  CurTok is the current
-/// token the parser it looking at.  getNextToken reads another token from the
+/// token the parser is looking at.  getNextToken reads another token from the
 /// lexer and updates CurTok with its results.
 static int CurTok;
 static int getNextToken() {
@@ -1167,7 +1167,7 @@
 }
 
 static void HandleTopLevelExpression() {
-  // Evaluate a top level expression into an anonymous function.
+  // Evaluate a top-level expression into an anonymous function.
   if (FunctionAST *F = ParseTopLevelExpr()) {
     fprintf(stderr, "Parsed a top-level expr\n");
   } else {
@@ -1182,7 +1182,7 @@
     fprintf(stderr, "ready> ");
     switch (CurTok) {
     case tok_eof:    return;
-    case ';':        getNextToken(); break;  // ignore top level semicolons.
+    case ';':        getNextToken(); break;  // ignore top-level semicolons.
     case tok_def:    HandleDefinition(); break;
     case tok_extern: HandleExtern(); break;
     default:         HandleTopLevelExpression(); break;
@@ -1211,6 +1211,7 @@
 }
      +Next: Implementing Code Generation to LLVM IR
      Modified: llvm/trunk/docs/tutorial/LangImpl3.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/tutorial/LangImpl3.html?rev=46933&r1=46932&r2=46933&view=diff ============================================================================== --- llvm/trunk/docs/tutorial/LangImpl3.html (original) +++ llvm/trunk/docs/tutorial/LangImpl3.html Sun Feb 10 13:11:04 2008 @@ -59,8 +59,8 @@

      -In order to generate LLVM IR, we want some simple setup to get started. First, -we define virtual codegen methods in each AST class:

      +In order to generate LLVM IR, we want some simple setup to get started. First +we define virtual code generation (codegen) methods in each AST class:

      @@ -95,9 +95,11 @@
 Assignment - the concepts are really quite natural once you grok them.
      
 
 
      Note that instead of adding virtual methods to the ExprAST class hierarchy,
-it could also make sense to use a visitor pattern or some other way to model
-this.  Again, this tutorial won't dwell on good software engineering practices:
-for our purposes, adding a virtual method is simplest.
      
+it could also make sense to use a visitor pattern or some
+other way to model this.  Again, this tutorial won't dwell on good software
+engineering practices: for our purposes, adding a virtual method is
+simplest.
      
 
 
      The
 second thing we want is an "Error" method like we used for the parser, which will
@@ -121,16 +123,15 @@
 
 
      The Builder object is a helper object that makes it easy to generate
 LLVM instructions.  Instances of the LLVMBuilder 
-class keep track of the current place to
-insert instructions and has methods to create new instructions.
      
+href="http://llvm.org/doxygen/LLVMBuilder_8h-source.html">LLVMBuilder 
+class keep track of the current place to insert instructions and has methods to
+create new instructions.
      
 
 
      The NamedValues map keeps track of which values are defined in the
-current scope and what their LLVM representation is (in other words, it is a 
-symbol table for the code).  In this form of
-Kaleidoscope, the only things that can be referenced are function parameters.
-As such, function parameters will be in this map when generating code for their
-function body.
      
+current scope and what their LLVM representation is.  (In other words, it is a
+symbol table for the code).  In this form of Kaleidoscope, the only things that
+can be referenced are function parameters.  As such, function parameters will
+be in this map when generating code for their function body.
      
 
 
      
 With these basics in place, we can start talking about how to generate code for
@@ -148,7 +149,7 @@
 
      
 
 
      Generating LLVM code for expression nodes is very straightforward: less
-than 45 lines of commented code for all four of our expression nodes.  First,
+than 45 lines of commented code for all four of our expression nodes.  First
 we'll do numeric literals:
      
 
 
      
@@ -218,11 +219,13 @@
 LLVMBuilder knows where to insert the newly created instruction, all you have to
 do is specify what instruction to create (e.g. with CreateAdd), which
 operands to use (L and R here) and optionally provide a name
-for the generated instruction.  One nice thing about LLVM is that the name is 
-just a hint: if there are multiple additions in a single function, the first
-will be named "addtmp" and the second will be "autorenamed" by adding a suffix,
-giving it a name like "addtmp42".  Local value names for instructions are purely
-optional, but it makes it much easier to read the IR dumps.
      
+for the generated instruction.
      
+
+
      One nice thing about LLVM is that the name is just a hint.  For instance, if
+the code above emits multiple "addtmp" variables, LLVM will automatically
+provide each one with an increasing, unique numeric suffix.  Local value names
+for instructions are purely optional, but it makes it much easier to read the
+IR dumps.
      
 
 
      LLVM instructions are constrained by
 strict rules: for example, the Left and Right operators of
@@ -1228,6 +1231,7 @@
 }
      +Next: Adding JIT and Optimizer Support
      Modified: llvm/trunk/docs/tutorial/LangImpl4.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/tutorial/LangImpl4.html?rev=46933&r1=46932&r2=46933&view=diff ============================================================================== --- llvm/trunk/docs/tutorial/LangImpl4.html (original) +++ llvm/trunk/docs/tutorial/LangImpl4.html Sun Feb 10 13:11:04 2008 @@ -1119,6 +1119,7 @@ +Next: Extending the language: control flow Modified: llvm/trunk/docs/tutorial/LangImpl5.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/tutorial/LangImpl5.html?rev=46933&r1=46932&r2=46933&view=diff ============================================================================== --- llvm/trunk/docs/tutorial/LangImpl5.html (original) +++ llvm/trunk/docs/tutorial/LangImpl5.html Sun Feb 10 13:11:04 2008 @@ -1745,6 +1745,7 @@ +Next: Extending the language: user-defined operators Modified: llvm/trunk/docs/tutorial/LangImpl6.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/tutorial/LangImpl6.html?rev=46933&r1=46932&r2=46933&view=diff ============================================================================== --- llvm/trunk/docs/tutorial/LangImpl6.html (original) +++ llvm/trunk/docs/tutorial/LangImpl6.html Sun Feb 10 13:11:04 2008 @@ -1784,6 +1784,7 @@ +Next: Extending the language: mutable variables / SSA construction Modified: llvm/trunk/docs/tutorial/LangImpl7.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/tutorial/LangImpl7.html?rev=46933&r1=46932&r2=46933&view=diff ============================================================================== --- llvm/trunk/docs/tutorial/LangImpl7.html (original) +++ llvm/trunk/docs/tutorial/LangImpl7.html Sun Feb 10 13:11:04 2008 @@ -2140,6 +2140,7 @@ +Next: Conclusion and other useful LLVM tidbits From clattner at apple.com Sun Feb 10 13:11:29 2008 From: clattner at apple.com (Chris Lattner) Date: Sun, 10 Feb 2008 11:11:29 -0800 Subject: [llvm-commits] patches for the JIT and Kaleidoscope tutorials In-Reply-To: <31973.137.201.242.130.1201726289.squirrel@webmail.nwind.net> References: <31973.137.201.242.130.1201726289.squirrel@webmail.nwind.net> Message-ID: <959B74C1-68B1-44C0-A4C3-A8AF7F3CAE09@apple.com> On Jan 30, 2008, at 12:51 PM, Sam Bishop wrote: > I have been working my way through the JIT and Kaleidoscope > tutorials in my > (minuscule) spare time. Thanks again for writing them! I have > attached a > patch containing some minor changes, ranging from spelling and > grammar fixes > to adding a "Next: " hyperlink to the bottom > of each > page. > > Every page has been given the "next link" treatment, but otherwise > I'm only > half way through the Kaleidoscope tutorial. I will send a follow-on > patch > if time permits. Applied, thanks Sam! http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20080204/058073.html -Chris From clattner at apple.com Sun Feb 10 13:56:28 2008 From: clattner at apple.com (Chris Lattner) Date: Sun, 10 Feb 2008 11:56:28 -0800 Subject: [llvm-commits] [llvm] r46827 - memoperands #1 In-Reply-To: <200802062227.m16MRhjU003393@zion.cs.uiuc.edu> References: <200802062227.m16MRhjU003393@zion.cs.uiuc.edu> Message-ID: <1A0C0294-3729-415D-8A8D-BD8DCABF8CFC@apple.com> On Feb 6, 2008, at 2:27 PM, Dan Gohman wrote: > URL: http://llvm.org/viewvc/llvm-project?rev=46827&view=rev > Log: > Create a new class, MemOperand, for describing memory references > in the backend. Introduce a new SDNode type, MemOperandSDNode, for > holding a MemOperand in the SelectionDAG IR, and add a MemOperand > list to MachineInstr, and code to manage them. Remove the offset > field from SrcValueSDNode; uses of SrcValueSDNode that were using > it are all all using MemOperandSDNode now. > > Also, begin updating some getLoad and getStore calls to use the > PseudoSourceValue objects. > > Most of this was written by Florian Brander, some > reorganization and updating to TOT by me. > > Re-apply the memory operand changes, with a fix for the static > initializer problem, a minor tweak to the way the > DAGISelEmitter finds load/store nodes, and a renaming of the > new PseudoSourceValue objects. This is very nice work guys. Some thoughts: class MemOperand { Should this be named MachineMemOperand, or something like that, for consistency? unsigned int Flags; int Offset; int Size; unsigned int Alignment; Is 32 bits sufficient for offset information? Are there any targets that can do reg+largeoffset? If you store Alignment in power-of-two form, you can make it be a short, and then pack flags+alignment into the same word. Instead of Size here, would it make sense to store an MVT? That would seem to capture strictly more information, thought I'm not sure if it's directly useful right now. Is the Value* always required to have llvm::PointerType if nonnull? If so, it would be useful to add a comment stating that. When we have more support for alternate address spaces in the backend, this could be a useful invariant to have. In MachineInstr, is there any semantics associated with the ordering of memoperands? Are there any current targets that have instructions with multiple memoperands? > Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=46585&r1=46584&r2=46585&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original) > +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Wed Jan 30 > 18:25:39 2008 > @@ -381,8 +381,12 @@ > SDOperand getIndexedStore(SDOperand OrigStoe, SDOperand Base, > SDOperand Offset, ISD::MemIndexedMode AM); > > + // getSrcValue - Construct a node to track a Value* through the > backend. > + SDOperand getSrcValue(const Value *v); > + > + // getMemOperand - Construct a node to track a memory reference > + // through the backend. > + SDOperand getMemOperand(const MemOperand &MO); What is the difference between a SrcValueSDNode and a MemOperandSDNode now? Is the former a special case of the later? > +/// MemOperandSDNode - An SDNode that holds a MemOperand. This is > +/// used to represent a reference to memory after ISD::LOAD > +/// and ISD::STORE have been lowered. > +/// > +class MemOperandSDNode : public SDNode { > + virtual void ANCHOR(); // Out-of-line virtual method to give > class a home. > +protected: > + friend class SelectionDAG; > + /// Create a MemOperand node > + explicit MemOperandSDNode(MemOperand mo) This should probably take 'mo' by const reference to avoid a copy. > @@ -1546,6 +1573,10 @@ > /// isUnindexed - Return true if this is NOT a pre/post inc/dec > load/store. > bool isUnindexed() const { return AddrMode == ISD::UNINDEXED; } > > + /// getMemOperand - Return a MemOperand object describing the > memory > + /// reference performed by this load or store. > + MemOperand getMemOperand() const; Would it make sense to merge all the fields in LSBaseSDNode into a MemOperand ivar? > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/CodeGen/PseudoSourceValue.cpp (original) > +++ llvm/trunk/lib/CodeGen/PseudoSourceValue.cpp Wed Feb 6 16:27:42 > 2008 > @@ -0,0 +1,41 @@ ... > +namespace llvm { > + static ManagedStatic PSVs; > + > + const PseudoSourceValue &PseudoSourceValue::getFixedStack() > { return (*PSVs)[0]; } > + const PseudoSourceValue &PseudoSourceValue::getStack() { return > (*PSVs)[1]; } > + const PseudoSourceValue &PseudoSourceValue::getGOT() { return > (*PSVs)[2]; } > + const PseudoSourceValue &PseudoSourceValue::getConstantPool() > { return (*PSVs)[3]; } > + const PseudoSourceValue &PseudoSourceValue::getJumpTable() > { return (*PSVs)[4]; } > + 80 col violations, but otherwise looks nice. > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=46827&r1=46826&r2=46827&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Feb 6 > 16:27:42 2008 > @@ -1316,8 +1320,15 @@ > MVT::ValueType IdxVT = Tmp3.getValueType(); > MVT::ValueType PtrVT = TLI.getPointerTy(); > SDOperand StackPtr = DAG.CreateStackTemporary(VT); > + > + FrameIndexSDNode *StackPtrFI = > dyn_cast(StackPtr.Val); > + assert(StackPtrFI); Instead of dyn_cast + assert, please just use cast<> > + int SPFI = StackPtrFI->getIndex(); > + > // Store the vector. > + SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, > + > &PseudoSourceValue::getFixedStack(), > + SPFI); This is a little bit strange to me: isn't this setting the "offset" of the srcvalue to the frameindex? If this is expected, then please document this really clearly in MemOperand and friends. This is somewhat surprising to me (but not unreasonable), and any clients of this information will be required to handle this specially. > @@ -3240,16 +3255,14 @@ > } > break; > case TargetLowering::Expand: { > - SrcValueSDNode *SV = cast(Node->getOperand(2)); > - SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, > - SV->getValue(), SV- > >getOffset()); > + const Value *V = cast(Node->getOperand(2))- > >getValue(); > + SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, > Tmp2, V, 0); I think this is setting the offset incorrectly. Isn't SV->getOffset() correct here instead of 0? > > // Increment the pointer, VAList, to the next vaarg > Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, > DAG.getConstant(MVT::getSizeInBits(VT)/8, > TLI.getPointerTy())); > // Store the incremented VAList to the legalized pointer > - Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV- > >getValue(), > - SV->getOffset()); > + Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0); Likewise, I think this should be "offset + MVT::getSizeInBits(VT)/8". > @@ -3285,12 +3298,10 @@ > case TargetLowering::Expand: > // This defaults to loading a pointer from the input and > storing it to the > // output, returning the chain. > - SrcValueSDNode *SVD = cast(Node- > >getOperand(3)); > - SrcValueSDNode *SVS = cast(Node- > >getOperand(4)); > - Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD- > >getValue(), > - SVD->getOffset()); > - Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, SVS- > >getValue(), > - SVS->getOffset()); > + const Value *VD = cast(Node->getOperand(3))- > >getValue(); > + const Value *VS = cast(Node->getOperand(4))- > >getValue(); > + Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VD, 0); > + Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VS, 0); This also seems to be dropping offset info, though maybe I'm missing something? > @@ -4285,16 +4296,14 @@ > Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2)); > Result = TLI.CustomPromoteOperation(Tmp3, DAG); > } else { > - SrcValueSDNode *SV = cast(Node->getOperand(2)); > - SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, > - SV->getValue(), SV- > >getOffset()); > + const Value *V = cast(Node->getOperand(2))- > >getValue(); > + SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, > Tmp2, V, 0); Here too. > // Increment the pointer, VAList, to the next vaarg > Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, > DAG.getConstant(MVT::getSizeInBits(VT)/8, > TLI.getPointerTy())); > // Store the incremented VAList to the legalized pointer > - Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV- > >getValue(), > - SV->getOffset()); > + Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0); Here too. I assume I'm missing something, so I'll stop commenting on these. > @@ -4750,6 +4759,10 @@ > // Create the stack frame object. > SDOperand FIPtr = DAG.CreateStackTemporary(SlotVT); > > + FrameIndexSDNode *StackPtrFI = dyn_cast(FIPtr); > + assert(StackPtrFI); should be cast<> > @@ -4776,9 +4793,15 @@ > // Create a vector sized/aligned stack slot, store the value to > element #0, > // then load the whole vector back out. > SDOperand StackPtr = DAG.CreateStackTemporary(Node- > >getValueType(0)); > + > + FrameIndexSDNode *StackPtrFI = > dyn_cast(StackPtr); > + assert(StackPtrFI); cast<> > @@ -6743,10 +6773,16 @@ > // Lower to a store/load so that it can be split. > // FIXME: this could be improved probably. > SDOperand Ptr = DAG.CreateStackTemporary(InOp.getValueType()); > + FrameIndexSDNode *FI = dyn_cast(Ptr.Val); > + assert(FI && "Expecting CreateStackTemporary to return a > frame index.\n"); cast<> I'll continue the review in a separate email, -Chris From baldrick at free.fr Sun Feb 10 13:56:41 2008 From: baldrick at free.fr (Duncan Sands) Date: Sun, 10 Feb 2008 20:56:41 +0100 Subject: [llvm-commits] [llvm] r46108 - in /llvm/trunk: lib/Transforms/IPO/ArgumentPromotion.cpp test/Transforms/ArgumentPromotion/attrs.ll In-Reply-To: <69290D90-47D6-4D31-AB6D-FE8A4864BA9E@nondot.org> References: <200801170117.m0H1H3mE001661@zion.cs.uiuc.edu> <200801171045.02711.duncan.sands@math.u-psud.fr> <69290D90-47D6-4D31-AB6D-FE8A4864BA9E@nondot.org> Message-ID: <200802102056.42255.baldrick@free.fr> > > you forgot about attributes on the function return value. > > I've lost the context for this, do you remember what this was about? I fixed it for you already :) D. From sabre at nondot.org Sun Feb 10 13:57:36 2008 From: sabre at nondot.org (Chris Lattner) Date: Sun, 10 Feb 2008 11:57:36 -0800 Subject: [llvm-commits] [llvm] r46108 - in /llvm/trunk: lib/Transforms/IPO/ArgumentPromotion.cpp test/Transforms/ArgumentPromotion/attrs.ll In-Reply-To: <200802102056.42255.baldrick@free.fr> References: <200801170117.m0H1H3mE001661@zion.cs.uiuc.edu> <200801171045.02711.duncan.sands@math.u-psud.fr> <69290D90-47D6-4D31-AB6D-FE8A4864BA9E@nondot.org> <200802102056.42255.baldrick@free.fr> Message-ID: <8553EF7E-7B62-45F8-9E8D-C3B50CC93BC2@nondot.org> On Feb 10, 2008, at 11:56 AM, Duncan Sands wrote: >>> you forgot about attributes on the function return value. >> >> I've lost the context for this, do you remember what this was about? > > I fixed it for you already :) Ahh, thanks :) :) -Chris From ggreif at gmail.com Sun Feb 10 14:08:16 2008 From: ggreif at gmail.com (Gabor Greif) Date: Sun, 10 Feb 2008 20:08:16 -0000 Subject: [llvm-commits] [llvm] r46934 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <200802102008.m1AK8GxP028330@zion.cs.uiuc.edu> Author: ggreif Date: Sun Feb 10 14:08:16 2008 New Revision: 46934 URL: http://llvm.org/viewvc/llvm-project?rev=46934&view=rev Log: corrected some spellings maybe c380004 can be hyperlinked too? Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=46934&r1=46933&r2=46934&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Sun Feb 10 14:08:16 2008 @@ -138,7 +138,7 @@
    • Gordon Henriksen rewrote most of the Accurate Garbage Collection code in the code generator, making the -generated code more efficient and adding support for the Ocaml garbage collector +generated code more efficient and adding support for the OCaml garbage collector metadata format.
    • Christopher Lamb contributed support for multiple address spaces in LLVM @@ -164,7 +164,7 @@

        -
      • Gordon contributed support for C and Ocaml Bindings for the basic LLVM IR +
      • Gordon contributed support for C and OCaml Bindings for the basic LLVM IR construction routines as well as several other auxiliary APIs.
      • Anton added readnone/readonly attributes for modeling function side effects. @@ -291,7 +291,7 @@ of the EFLAGS register explicitly in all instructions. This gives more freedom to the scheduler, and is a more explicit way to model the instructions.
      • Dale contributed support for exception handling on Darwin/x86-64 and -Darwin/ppc.
        • +Darwin/PPC.
      • Evan turned on if-conversion by default for ARM, allowing LLVM to take advantage of its predication features.
      • Bruno added PIC support to the MIPS backend, fixed many bugs and improved From baldrick at free.fr Sun Feb 10 14:21:25 2008 From: baldrick at free.fr (Duncan Sands) Date: Sun, 10 Feb 2008 21:21:25 +0100 Subject: [llvm-commits] [llvm] r46934 - /llvm/trunk/docs/ReleaseNotes.html In-Reply-To: <200802102008.m1AK8GxP028330@zion.cs.uiuc.edu> References: <200802102008.m1AK8GxP028330@zion.cs.uiuc.edu> Message-ID: <200802102121.25649.baldrick@free.fr> > maybe c380004 can be hyperlinked too? There's not really much point: this is not an llvm-gcc problem. I don't plan to open a PR for it, so there's nothing to link to. Ciao, Duncan. From clattner at apple.com Sun Feb 10 14:51:05 2008 From: clattner at apple.com (Chris Lattner) Date: Sun, 10 Feb 2008 12:51:05 -0800 Subject: [llvm-commits] [llvm] r46827 - MemOperands #2/2 In-Reply-To: <200802062227.m16MRhjU003393@zion.cs.uiuc.edu> References: <200802062227.m16MRhjU003393@zion.cs.uiuc.edu> Message-ID: <1C931F37-1DB1-486F-AD32-10C82BCB390A@apple.com> On Feb 6, 2008, at 2:27 PM, Dan Gohman wrote: > URL: http://llvm.org/viewvc/llvm-project?rev=46827&view=rev > Log: > Re-apply the memory operand changes, with a fix for the static > initializer problem, a minor tweak to the way the > DAGISelEmitter finds load/store nodes, and a renaming of the > new PseudoSourceValue objects. Continuing the review: > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Wed Feb 6 > 16:27:42 2008 > @@ -277,15 +277,27 @@ > return N; > } > > +/// CountOperands - The inputs to target nodes have any actual > inputs first, > +/// followed by optional memory operands chain operand, then flag > operands. Strictly speaking, a node can have at most one flag operand. This comment isn't your bug, but it would be nice to fix it :) > > +/// Compute the number of actual operands that will go into the > machine istr. istr -> instr or instruction? Also, double space before 'will'. > > unsigned ScheduleDAG::CountOperands(SDNode *Node) { > unsigned N = Node->getNumOperands(); > while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag) > --N; > if (N && Node->getOperand(N - 1).getValueType() == MVT::Other) > --N; // Ignore chain if it exists. > + while (N && MemOperandSDNode::classof(Node->getOperand(N - 1).Val)) Instead of calling classof, please use: N && isa(...) > > + --N; // Ignore MemOperand nodes > + return N; > +} > + > +/// CountMemOperands - Find the index of the last MemOperandSDNode > operand > +unsigned ScheduleDAG::CountMemOperands(SDNode *Node) { Please rename this method. The name implies that it returns the number of mem operands, not the index of the last one. > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Feb 6 > 16:27:42 2008 > @@ -3503,6 +3535,26 @@ > TheGlobal = const_cast(GA); > } > > +/// getMemOperand - Return a MemOperand object describing the memory > +/// reference performed by this load or store. > +MemOperand LSBaseSDNode::getMemOperand() const { > + int Size = (MVT::getSizeInBits(getMemoryVT()) + 7) >> 3; > + int Flags = > + getOpcode() == ISD::LOAD ? MemOperand::MOLoad : > MemOperand::MOStore; > + if (IsVolatile) Flags |= MemOperand::MOVolatile; > + > + // Check if the load references a frame index, and does not have > + // an SV attached. > + const FrameIndexSDNode *FI = > + dyn_cast(getBasePtr().Val); > + if (!getSrcValue() && FI) > + return MemOperand(&PseudoSourceValue::getFixedStack(), Flags, > + FI->getIndex(), Size, Alignment); > + else > + return MemOperand(getSrcValue(), Flags, > + getSrcValueOffset(), Size, Alignment); This logic seems correct, but would be more clear (at least to me) if written as: if (getSrcValue() || !FI) > + return MemOperand(getSrcValue(), Flags, > + getSrcValueOffset(), Size, Alignment); else > + if (!getSrcValue() && FI) > + return MemOperand(&PseudoSourceValue::getFixedStack(), Flags, > + FI->getIndex(), Size, Alignment); It would be even easier if LSBaseSDNode just contained a memoperand to return by const reference though :) > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original) > +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Wed Feb 6 > 16:27:42 2008 > @@ -2199,9 +2203,11 @@ > Op.getOperand(0)); > > // STD the extended value into the stack slot. > + MemOperand MO(&PseudoSourceValue::getFixedStack(), > + MemOperand::MOStore, FrameIdx, 8, 8); Ah, this is interesting. I had to go look at the header file to make sure this is correct: wouldn't it make sense for the offset/index to be passed after the Value*? I would expect to see something like: > + MemOperand MO(&PseudoSourceValue::getFixedStack(), FrameIdx, > + MemOperand::MOStore, 8, 8); instead of splitting the two. If MemOperand stored an MVT instead of a size, it would make it a bit more clear what was going on, because the magic constants would be reduced: > + MemOperand MO(&PseudoSourceValue::getFixedStack(), FrameIdx, > + MemOperand::MOStore, MVT::i64, 8); etc. > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/utils/TableGen/DAGISelEmitter.cpp (original) > +++ llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Wed Feb 6 16:27:42 > 2008 > @@ -313,6 +313,12 @@ > std::vector > OrigChains; > std::set Duplicates; > > + /// LSI - Load/Store information. > + /// Save loads/stores matched by a pattern, and generate a > MemOperandSDNode > + /// for each memory access. This facilitates the use of > AliasAnalysis in > + /// the backend. > + std::vector LSI; > + > /// GeneratedCode - This is the buffer that we emit code to. The > first int > /// indicates whether this is an exit predicate (something that > should be > /// tested, and if true, the match fails) [when 1], or normal code > to emit > @@ -373,6 +379,16 @@ > void EmitMatchCode(TreePatternNode *N, TreePatternNode *P, > const std::string &RootName, const std::string > &ChainSuffix, > bool &FoundChain) { > + > + // Save loads/stores matched by a pattern. > + if (!N->isLeaf() && N->getName().empty()) { > + std::string EnumName = N->getOperator()- > >getValueAsString("Opcode"); > + if (EnumName == "ISD::LOAD" || > + EnumName == "ISD::STORE") { > + LSI.push_back(RootName); > + } > + } > + > bool isRoot = (P == NULL); > // Emit instruction predicates. Each predicate is just a string > for now. > if (isRoot) { > @@ -944,6 +960,18 @@ > } > } > > + // Generate MemOperandSDNodes nodes for each memory accesses > covered by this > + // pattern. > + if (isRoot) { > + std::vector::const_iterator mi, mie; > + for (mi = LSI.begin(), mie = LSI.end(); mi != mie; ++mi) { > + emitCode("SDOperand LSI_" + *mi + " = " > + "CurDAG->getMemOperand(cast(" + > + *mi + ")->getMemOperand());"); > + AllOps.push_back("LSI_" + *mi); > + } > + } > + Evan, please review this tblgen change. -Chris From clattner at apple.com Sun Feb 10 15:05:50 2008 From: clattner at apple.com (Chris Lattner) Date: Sun, 10 Feb 2008 13:05:50 -0800 Subject: [llvm-commits] Fix for PR1798 (ScalarEvolution) In-Reply-To: <47ADE232.5070407@fastmail.fm> References: <478D2769.8060503@fastmail.fm> <47ADE232.5070407@fastmail.fm> Message-ID: On Feb 9, 2008, at 9:26 AM, Wojciech Matyjewicz wrote: > Hi, > > I've attached an updated version of the patch. It is ready for using > support for APInts in the code generator, but currently it doesn't > rely > on this feature. I've added a hack that rounds up the computation > bitwidth to power of 2 (only these bitwidths are allowed: 1, 2, ..., > 64). Hack is visible and very easy to remove in future. > > Is it safe to commit it now? The patch looks good to me. Nicholas, can you please review it also? If Nicholas likes it, please commit, -Chris From wmatyjewicz at fastmail.fm Sun Feb 10 16:31:42 2008 From: wmatyjewicz at fastmail.fm (Wojciech Matyjewicz) Date: Sun, 10 Feb 2008 23:31:42 +0100 Subject: [llvm-commits] Fix for PR1798 (ScalarEvolution) In-Reply-To: References: <478D2769.8060503@fastmail.fm> <47ADE232.5070407@fastmail.fm> Message-ID: <47AF7B4E.5030701@fastmail.fm> Chris Lattner wrote: > > The patch looks good to me. Nicholas, can you please review it also? > If Nicholas likes it, please commit, IIRC, Nicholas reviewed the previous version. Nick, the only difference is the hack to round the necessary bitwitdh up to 32 or 64 in the beginning of BinomialCoefficient() function. Wojtek From nicholas at mxc.ca Sun Feb 10 16:45:06 2008 From: nicholas at mxc.ca (Nick Lewycky) Date: Sun, 10 Feb 2008 14:45:06 -0800 Subject: [llvm-commits] Fix for PR1798 (ScalarEvolution) In-Reply-To: References: <478D2769.8060503@fastmail.fm> <47ADE232.5070407@fastmail.fm> Message-ID: <47AF7E72.6080609@mxc.ca> Chris Lattner wrote: > On Feb 9, 2008, at 9:26 AM, Wojciech Matyjewicz wrote: > >> Hi, >> >> I've attached an updated version of the patch. It is ready for using >> support for APInts in the code generator, but currently it doesn't >> rely >> on this feature. I've added a hack that rounds up the computation >> bitwidth to power of 2 (only these bitwidths are allowed: 1, 2, ..., >> 64). Hack is visible and very easy to remove in future. >> >> Is it safe to commit it now? > > The patch looks good to me. Nicholas, can you please review it also? > If Nicholas likes it, please commit, Just one question, + const IntegerType *ExTy = IntegerType::get(std::max(DividendBits, 32U)); why the max of DividendBits and 32? If for whatever reason we think we need only 16 bits for the computation, why expand it to 32? Nick From wmatyjewicz at fastmail.fm Sun Feb 10 17:18:31 2008 From: wmatyjewicz at fastmail.fm (Wojciech Matyjewicz) Date: Mon, 11 Feb 2008 00:18:31 +0100 Subject: [llvm-commits] Fix for PR1798 (ScalarEvolution) In-Reply-To: <47AF7E72.6080609@mxc.ca> References: <478D2769.8060503@fastmail.fm> <47ADE232.5070407@fastmail.fm> <47AF7E72.6080609@mxc.ca> Message-ID: <47AF8647.8090505@fastmail.fm> Nick Lewycky wrote: > > Just one question, > > + const IntegerType *ExTy = IntegerType::get(std::max(DividendBits, 32U)); > > why the max of DividendBits and 32? If for whatever reason we think we > need only 16 bits for the computation, why expand it to 32? We compute the divisor of the BC formula using 32-bit arithmetic. Hence, this is the lower bound for the bitwitdh of the division, and the dividend as well. After your question, I have realized that 32 bits for the divisor may be too much... Using "only" 16 bits would allow us to handle AddRecs up to length 8. If you agree 16 is a safe bitwidth, I'll change it. However, the maximum operation you ask about will still be necessary. The other way is to compute the dividend with the minimum bitwidth (say, 8), and then zero-extend it to 16 (32 withouth the above change) if necessary just before performing the division. But wouldn't it be an overkill? Wojtek From nicholas at mxc.ca Sun Feb 10 18:32:36 2008 From: nicholas at mxc.ca (Nick Lewycky) Date: Sun, 10 Feb 2008 16:32:36 -0800 Subject: [llvm-commits] Fix for PR1798 (ScalarEvolution) In-Reply-To: <47AF8647.8090505@fastmail.fm> References: <478D2769.8060503@fastmail.fm> <47ADE232.5070407@fastmail.fm> <47AF7E72.6080609@mxc.ca> <47AF8647.8090505@fastmail.fm> Message-ID: <47AF97A4.6090909@mxc.ca> Wojciech Matyjewicz wrote: > Nick Lewycky wrote: >> Just one question, >> >> + const IntegerType *ExTy = IntegerType::get(std::max(DividendBits, 32U)); >> >> why the max of DividendBits and 32? If for whatever reason we think we >> need only 16 bits for the computation, why expand it to 32? > > We compute the divisor of the BC formula using 32-bit arithmetic. Hence, > this is the lower bound for the bitwitdh of the division, and the > dividend as well. That makes sense. > After your question, I have realized that 32 bits for the divisor may be > too much... Using "only" 16 bits would allow us to handle AddRecs up to > length 8. If you agree 16 is a safe bitwidth, I'll change it. However, > the maximum operation you ask about will still be necessary. Optimally, we'd use APInt and get the right length up front, but there's no need for that to hold up this patch. Nick From evan.cheng at apple.com Sun Feb 10 21:12:38 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Sun, 10 Feb 2008 19:12:38 -0800 Subject: [llvm-commits] [llvm] r46916 - /llvm/trunk/lib/Target/PowerPC/PPCTargetAsmInfo.cpp In-Reply-To: <200802100003.m1A03svv027444@zion.cs.uiuc.edu> References: <200802100003.m1A03svv027444@zion.cs.uiuc.edu> Message-ID: Any idea what the differences mean? .rodata.cst4 makes it possible to be merged? Was there a reason to change it or than to match gcc? Thanks, Evan On Feb 9, 2008, at 4:03 PM, Nick Lewycky wrote: > Author: nicholas > Date: Sat Feb 9 18:03:54 2008 > New Revision: 46916 > > URL: http://llvm.org/viewvc/llvm-project?rev=46916&view=rev > Log: > Match GCC's behaviour for these sections. > > Modified: > llvm/trunk/lib/Target/PowerPC/PPCTargetAsmInfo.cpp > > Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetAsmInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetAsmInfo.cpp?rev=46916&r1=46915&r2=46916&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/PowerPC/PPCTargetAsmInfo.cpp (original) > +++ llvm/trunk/lib/Target/PowerPC/PPCTargetAsmInfo.cpp Sat Feb 9 > 18:03:54 2008 > @@ -92,8 +92,8 @@ > CommentString = "#"; > GlobalPrefix = ""; > PrivateGlobalPrefix = ""; > - ConstantPoolSection = "\t.section .rodata.cst4\t"; > - JumpTableDataSection = ".section .rodata.cst4"; > + ConstantPoolSection = "\t.section .rodata\t"; > + JumpTableDataSection = ".section .rodata"; > CStringSection = "\t.section\t.rodata"; > StaticCtorsSection = ".section\t.ctors,\"aw\", at progbits"; > StaticDtorsSection = ".section\t.dtors,\"aw\", at progbits"; > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From evan.cheng at apple.com Sun Feb 10 21:46:07 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Sun, 10 Feb 2008 19:46:07 -0800 Subject: [llvm-commits] [llvm] r46922 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp In-Reply-To: <200802100810.m1A8AOS2007775@zion.cs.uiuc.edu> References: <200802100810.m1A8AOS2007775@zion.cs.uiuc.edu> Message-ID: <241F94F0-D3FB-4D23-B552-6A5C9E66F868@apple.com> What is this fixing? I would expect SelectionDAG to constant evaluating it to a constant node? Evan On Feb 10, 2008, at 12:10 AM, Bill Wendling wrote: > Author: void > Date: Sun Feb 10 02:10:24 2008 > New Revision: 46922 > > URL: http://llvm.org/viewvc/llvm-project?rev=46922&view=rev > Log: > Return "(c1 + c2)" instead of yet another ADD node (which made this a > no-op). > > Modified: > llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=46922&r1=46921&r2=46922&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sun Feb 10 > 02:10:24 2008 > @@ -923,7 +923,7 @@ > return N1; > // fold (add c1, c2) -> c1+c2 > if (N0C && N1C) > - return DAG.getNode(ISD::ADD, VT, N0, N1); > + return DAG.getConstant(N0C->getValue() + N1C->getValue(), VT); > // canonicalize constant to RHS > if (N0C && !N1C) > return DAG.getNode(ISD::ADD, VT, N1, N0); > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From natebegeman at mac.com Sun Feb 10 22:16:10 2008 From: natebegeman at mac.com (Nate Begeman) Date: Mon, 11 Feb 2008 04:16:10 -0000 Subject: [llvm-commits] [llvm] r46948 - /llvm/trunk/lib/Target/PowerPC/README.txt Message-ID: <200802110416.m1B4GBpm009952@zion.cs.uiuc.edu> Author: sampo Date: Sun Feb 10 22:16:09 2008 New Revision: 46948 URL: http://llvm.org/viewvc/llvm-project?rev=46948&view=rev Log: additional missing feature Modified: llvm/trunk/lib/Target/PowerPC/README.txt Modified: llvm/trunk/lib/Target/PowerPC/README.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/README.txt?rev=46948&r1=46947&r2=46948&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/README.txt (original) +++ llvm/trunk/lib/Target/PowerPC/README.txt Sun Feb 10 22:16:09 2008 @@ -4,6 +4,7 @@ * gpr0 allocation * implement do-loop -> bdnz transform * Implement __builtin_trap (ISD::TRAP) as 'tw 31, 0, 0' aka 'trap'. +* lmw/stmw pass a la arm load store optimizer for prolog/epilog ===-------------------------------------------------------------------------=== From natebegeman at mac.com Sun Feb 10 22:19:36 2008 From: natebegeman at mac.com (Nate Begeman) Date: Mon, 11 Feb 2008 04:19:36 -0000 Subject: [llvm-commits] [llvm] r46949 - in /llvm/trunk/lib/Target: TargetSelectionDAG.td X86/README-SSE.txt X86/X86ISelLowering.cpp X86/X86ISelLowering.h X86/X86InstrSSE.td Message-ID: <200802110419.m1B4Jbj7010123@zion.cs.uiuc.edu> Author: sampo Date: Sun Feb 10 22:19:36 2008 New Revision: 46949 URL: http://llvm.org/viewvc/llvm-project?rev=46949&view=rev Log: Enable SSE4 codegen and pattern matching. Add some notes to the README. Modified: llvm/trunk/lib/Target/TargetSelectionDAG.td llvm/trunk/lib/Target/X86/README-SSE.txt llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.h llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/TargetSelectionDAG.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetSelectionDAG.td?rev=46949&r1=46948&r2=46949&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetSelectionDAG.td (original) +++ llvm/trunk/lib/Target/TargetSelectionDAG.td Sun Feb 10 22:19:36 2008 @@ -181,8 +181,8 @@ def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2> ]>; -def SDTVecInsert : SDTypeProfile<1, 2, [ // vector insert - SDTCisEltOfVec<1, 0>, SDTCisPtrTy<2> +def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert + SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3> ]>; class SDCallSeqStart constraints> : Modified: llvm/trunk/lib/Target/X86/README-SSE.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/README-SSE.txt?rev=46949&r1=46948&r2=46949&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/README-SSE.txt (original) +++ llvm/trunk/lib/Target/X86/README-SSE.txt Sun Feb 10 22:19:36 2008 @@ -761,3 +761,23 @@ instead of in target independent code. //===---------------------------------------------------------------------===// + +Non-SSE4 insert into 16 x i8 is atrociously bad. + +//===---------------------------------------------------------------------===// + +<2 x i64> extract is substantially worse than <2 x f64>, even if the destination +is memory. + +//===---------------------------------------------------------------------===// + +SSE4 extract-to-mem ops aren't being pattern matched because of the AssertZext +sitting between the truncate and the extract. + +//===---------------------------------------------------------------------===// + +INSERTPS can match any insert (extract, imm1), imm2 for 4 x float, and insert +any number of 0.0 simultaneously. Currently we only use it for simple +insertions. + +See comments in LowerINSERT_VECTOR_ELT_SSE4. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=46949&r1=46948&r2=46949&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sun Feb 10 22:19:36 2008 @@ -678,6 +678,33 @@ setOperationAction(ISD::SELECT, MVT::v2f64, Custom); setOperationAction(ISD::SELECT, MVT::v2i64, Custom); } + + if (Subtarget->hasSSE41()) { + // FIXME: Do we need to handle scalar-to-vector here? + setOperationAction(ISD::MUL, MVT::v4i32, Legal); + + // i8 and i16 vectors are custom , because the source register and source + // source memory operand types are not the same width. f32 vectors are + // custom since the immediate controlling the insert encodes additional + // information. + setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); + setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); + setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Legal); + setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); + + setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom); + setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom); + setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal); + setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Legal); + + if (Subtarget->is64Bit()) { + setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal); + setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Legal); + + setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal); + setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal); + } + } // We want to custom lower some of our intrinsics. setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); @@ -3655,10 +3682,34 @@ } SDOperand +X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDOperand Op, + SelectionDAG &DAG) { + MVT::ValueType VT = Op.getValueType(); + if (MVT::getSizeInBits(VT) == 8) { + SDOperand Extract = DAG.getNode(X86ISD::PEXTRB, MVT::i32, + Op.getOperand(0), Op.getOperand(1)); + SDOperand Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract, + DAG.getValueType(VT)); + return DAG.getNode(ISD::TRUNCATE, VT, Assert); + } else if (MVT::getSizeInBits(VT) == 16) { + SDOperand Extract = DAG.getNode(X86ISD::PEXTRW, MVT::i32, + Op.getOperand(0), Op.getOperand(1)); + SDOperand Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract, + DAG.getValueType(VT)); + return DAG.getNode(ISD::TRUNCATE, VT, Assert); + } + return SDOperand(); +} + + +SDOperand X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) { if (!isa(Op.getOperand(1))) return SDOperand(); + if (Subtarget->hasSSE41()) + return LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG); + MVT::ValueType VT = Op.getValueType(); // TODO: handle v16i8. if (MVT::getSizeInBits(VT) == 16) { @@ -3699,6 +3750,9 @@ return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec, DAG.getIntPtrConstant(0)); } else if (MVT::getSizeInBits(VT) == 64) { + // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b + // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught + // to match extract_elt for f64. unsigned Idx = cast(Op.getOperand(1))->getValue(); if (Idx == 0) return Op; @@ -3724,9 +3778,47 @@ } SDOperand +X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDOperand Op, SelectionDAG &DAG){ + MVT::ValueType VT = Op.getValueType(); + MVT::ValueType EVT = MVT::getVectorElementType(VT); + + SDOperand N0 = Op.getOperand(0); + SDOperand N1 = Op.getOperand(1); + SDOperand N2 = Op.getOperand(2); + + if ((MVT::getSizeInBits(EVT) == 8) || (MVT::getSizeInBits(EVT) == 16)) { + unsigned Opc = (MVT::getSizeInBits(EVT) == 8) ? X86ISD::PINSRB + : X86ISD::PINSRW; + // Transform it so it match pinsr{b,w} which expects a GR32 as its second + // argument. + if (N1.getValueType() != MVT::i32) + N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1); + if (N2.getValueType() != MVT::i32) + N2 = DAG.getIntPtrConstant(cast(N2)->getValue()); + return DAG.getNode(Opc, VT, N0, N1, N2); + } else if (EVT == MVT::f32) { + // Bits [7:6] of the constant are the source select. This will always be + // zero here. The DAG Combiner may combine an extract_elt index into these + // bits. For example (insert (extract, 3), 2) could be matched by putting + // the '3' into bits [7:6] of X86ISD::INSERTPS. + // Bits [5:4] of the constant are the destination select. This is the + // value of the incoming immediate. + // Bits [3:0] of the constant are the zero mask. The DAG Combiner may + // combine either bitwise AND or insert of float 0.0 to set these bits. + N2 = DAG.getIntPtrConstant(cast(N2)->getValue() << 4); + return DAG.getNode(X86ISD::INSERTPS, VT, N0, N1, N2); + } + return SDOperand(); +} + +SDOperand X86TargetLowering::LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) { MVT::ValueType VT = Op.getValueType(); MVT::ValueType EVT = MVT::getVectorElementType(VT); + + if (Subtarget->hasSSE41()) + return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG); + if (EVT == MVT::i8) return SDOperand(); @@ -5273,7 +5365,10 @@ case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; case X86ISD::Wrapper: return "X86ISD::Wrapper"; case X86ISD::S2VEC: return "X86ISD::S2VEC"; + case X86ISD::PEXTRB: return "X86ISD::PEXTRB"; case X86ISD::PEXTRW: return "X86ISD::PEXTRW"; + case X86ISD::INSERTPS: return "X86ISD::INSERTPS"; + case X86ISD::PINSRB: return "X86ISD::PINSRB"; case X86ISD::PINSRW: return "X86ISD::PINSRW"; case X86ISD::FMAX: return "X86ISD::FMAX"; case X86ISD::FMIN: return "X86ISD::FMIN"; Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=46949&r1=46948&r2=46949&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Sun Feb 10 22:19:36 2008 @@ -170,10 +170,22 @@ /// have to match the operand type. S2VEC, + /// PEXTRB - Extract an 8-bit value from a vector and zero extend it to + /// i32, corresponds to X86::PEXTRB. + PEXTRB, + /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to /// i32, corresponds to X86::PEXTRW. PEXTRW, + /// INSERTPS - Insert any element of a 4 x float vector into any element + /// of a destination 4 x floatvector. + INSERTPS, + + /// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector, + /// corresponds to X86::PINSRB. + PINSRB, + /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector, /// corresponds to X86::PINSRW. PINSRW, @@ -493,7 +505,9 @@ SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG); SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG); SDOperand LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG); + SDOperand LowerEXTRACT_VECTOR_ELT_SSE4(SDOperand Op, SelectionDAG &DAG); SDOperand LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG); + SDOperand LowerINSERT_VECTOR_ELT_SSE4(SDOperand Op, SelectionDAG &DAG); SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG); SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG); SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG); Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=46949&r1=46948&r2=46949&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Sun Feb 10 22:19:36 2008 @@ -35,8 +35,19 @@ def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>; def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>; def X86s2vec : SDNode<"X86ISD::S2VEC", SDTypeProfile<1, 1, []>, []>; -def X86pextrw : SDNode<"X86ISD::PEXTRW", SDTypeProfile<1, 2, []>, []>; -def X86pinsrw : SDNode<"X86ISD::PINSRW", SDTypeProfile<1, 3, []>, []>; +def X86pextrb : SDNode<"X86ISD::PEXTRB", + SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>; +def X86pextrw : SDNode<"X86ISD::PEXTRW", + SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>; +def X86pinsrb : SDNode<"X86ISD::PINSRB", + SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>, + SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>; +def X86pinsrw : SDNode<"X86ISD::PINSRW", + SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>, + SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>; +def X86insrtps : SDNode<"X86ISD::INSERTPS", + SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>, + SDTCisVT<2, f32>, SDTCisPtrTy<3>]>>; //===----------------------------------------------------------------------===// // SSE 'Special' Instructions @@ -2087,23 +2098,21 @@ (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2), "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}", [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1), - (iPTR imm:$src2)))]>; + imm:$src2))]>; let isTwoAddress = 1 in { def PINSRWrri : PDIi8<0xC4, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, GR32:$src2, i32i8imm:$src3), "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}", [(set VR128:$dst, - (v8i16 (X86pinsrw (v8i16 VR128:$src1), - GR32:$src2, (iPTR imm:$src3))))]>; + (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>; def PINSRWrmi : PDIi8<0xC4, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i16mem:$src2, i32i8imm:$src3), "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}", - [(set VR128:$dst, - (v8i16 (X86pinsrw (v8i16 VR128:$src1), - (i32 (anyext (loadi16 addr:$src2))), - (iPTR imm:$src3))))]>; + [(set VR128:$dst, + (X86pinsrw VR128:$src1, (extloadi16 addr:$src2), + imm:$src3))]>; } // Mask creation @@ -3255,7 +3264,7 @@ /// SS41I_binop_rmi_int - SSE 4.1 binary operator with immediate -let isTwoAddress = 1 in { +let Uses = [XMM0], isTwoAddress = 1 in { multiclass SS41I_ternary_int opc, string OpcodeStr, Intrinsic IntId> { def rr0 : SS48I; -/// SS41I_binop_ext8 - SSE 4.1 binary operator with immediate -multiclass SS41I_binop_ext8 opc, string OpcodeStr> { +/// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem +multiclass SS41I_extract8 opc, string OpcodeStr> { def rr : SS4AI, OpSize; + [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>, + OpSize; def mr : SS4AI, OpSize; + []>, OpSize; +// FIXME: +// There's an AssertZext in the way of writing the store pattern +// (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst) +} + +defm PEXTRB : SS41I_extract8<0x14, "pextrb">; + + +/// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination +multiclass SS41I_extract16 opc, string OpcodeStr> { + def mr : SS4AI, OpSize; +// FIXME: +// There's an AssertZext in the way of writing the store pattern +// (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst) } -defm PEXTRB : SS41I_binop_ext8<0x14, "pextrb">; +defm PEXTRW : SS41I_extract16<0x15, "pextrw">; + -/// SS41I_binop_ext32 - SSE 4.1 binary operator with immediate -multiclass SS41I_binop_ext32 opc, string OpcodeStr> { +/// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination +multiclass SS41I_extract32 opc, string OpcodeStr> { def rr : SS4AI, OpSize; } -defm PEXTRD : SS41I_binop_ext32<0x16, "pextrd">; +defm PEXTRD : SS41I_extract32<0x16, "pextrd">; -/// SS41I_binop_extf32 - SSE 4.1 binary operator with immediate -multiclass SS41I_binop_extf32 opc, string OpcodeStr> { + +/// SS41I_extractf32 - SSE 4.1 extract 32 bits to fp reg or memory destination +multiclass SS41I_extractf32 opc, string OpcodeStr> { def rr : SS4AI, OpSize; } -defm EXTRACTPS : SS41I_binop_extf32<0x17, "extractps">; +defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">; + +let isTwoAddress = 1 in { + multiclass SS41I_insert8 opc, string OpcodeStr> { + def rr : SS4AI, OpSize; + def rm : SS4AI, OpSize; + } +} + +defm PINSRB : SS41I_insert8<0x20, "pinsrb">; + +let isTwoAddress = 1 in { + multiclass SS41I_insert32 opc, string OpcodeStr> { + def rr : SS4AI, + OpSize; + def rm : SS4AI, OpSize; + } +} + +defm PINSRD : SS41I_insert32<0x22, "pinsrd">; + +let isTwoAddress = 1 in { + multiclass SS41I_insertf32 opc, string OpcodeStr> { + def rr : SS4AI, OpSize; + def rm : SS4AI, OpSize; + } +} +defm INSERTPS : SS41I_insertf32<0x31, "insertps">; From dpatel at apple.com Sun Feb 10 23:21:17 2008 From: dpatel at apple.com (Devang Patel) Date: Sun, 10 Feb 2008 21:21:17 -0800 Subject: [llvm-commits] [llvm-gcc-4.2] r46726 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp In-Reply-To: <200802092224.20812.baldrick@free.fr> References: <200802042324.m14NOiBg021071@zion.cs.uiuc.edu> <200802081903.13331.baldrick@free.fr> <760C956E-1E4A-4E7B-9A51-8A96AE4CA3AA@apple.com> <200802092224.20812.baldrick@free.fr> Message-ID: <6C2B9229-8B1C-4B6D-8107-A8C7A72BB547@apple.com> On Feb 9, 2008, at 1:24 PM, Duncan Sands wrote: > the current LLVM implementation means that anyone using threading > needs > to not do bitfield accesses, since the compiler generated code could > cause trouble. This is not handled by LLVM, this is handled by FE that is translating source code into LLVM IR. Unless all front-ends enforce this, we can not claim that LLVM guarantees bit-field thread safety (I do think, it is convenient if tools support bit-field thread safety). If you are suggesting to handle this some how inside LLVM itself then I mis- understood your comment. > Are you suggesting that users should roll their own > bitfield code (I'm not saying that this is unreasonable)? No. I'm merely stating current status quo. - Devang