From romix.llvm at googlemail.com Mon Mar 3 05:05:57 2008 From: romix.llvm at googlemail.com (Roman Levenstein) Date: Mon, 3 Mar 2008 12:05:57 +0100 Subject: [llvm-commits] Fwd: Patch for review: Speeding up ScheduleDAG computations In-Reply-To: References: <2913F98D-C5BD-44BD-A404-5E6DFFEDCFBC@apple.com> <200802291429.22322.dag@cray.com> Message-ID: Hi, 2008/3/1, Evan Cheng : > Let's try to solve one problem at a time. > > 1. Roman's depth / height patch calculation is obviously goodness. > Please commit that first. Please find attached the patch for depth/height calculation. All of the proposed improvements from the review by Evan and Dan are incorporated. Please have a look at it, and if it is OK, I'll submit. -Roman -------------- next part -------------- A non-text attachment was scrubbed... Name: ScheduleDAG.patch Type: text/x-diff Size: 4828 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20080303/d1646650/attachment.bin From romix.llvm at googlemail.com Mon Mar 3 05:06:46 2008 From: romix.llvm at googlemail.com (Roman Levenstein) Date: Mon, 3 Mar 2008 12:06:46 +0100 Subject: [llvm-commits] Fwd: Patch for review: Speeding up ScheduleDAG computations In-Reply-To: References: <2913F98D-C5BD-44BD-A404-5E6DFFEDCFBC@apple.com> <200802291429.22322.dag@cray.com> Message-ID: Hi, 2008/3/1, Evan Cheng : > Let's try to solve one problem at a time. > > 1. Roman's depth / height patch calculation is obviously goodness. > Please commit that first. Here is the patch for ScheduleDAGList.cpp: computing priorities using a linear algorithm. It uses the same idea as the height/depth computation, i.e. dynamic programming. I took into account all comments from Dan & Evan from last review. Additionally, I use now std::set instead of a priority queue. The results are exactly the same as with the current SVN version - I really compared it side-by-side during execution. Using std::set makes operations such as removal from the middle of the queue much faster and removes a bottleneck. Scheduling of very bigs BBs is now up to 3-4 times faster. Please, review this new version, if it is OK for submission. And there is one more patch to come, for the ScheduleDAGRRList.cpp, which would also use std::set instead of priority queues, introduce strict ordering and contain queue update changes as David suggested. -Roman -------------- next part -------------- A non-text attachment was scrubbed... Name: ScheduleDAGList.patch Type: text/x-diff Size: 5113 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20080303/66404d47/attachment.bin From dag at cray.com Mon Mar 3 10:52:59 2008 From: dag at cray.com (David Greene) Date: Mon, 3 Mar 2008 10:52:59 -0600 Subject: [llvm-commits] Patch for review: Speeding up ScheduleDAG computations In-Reply-To: References: Message-ID: <200803031053.00270.dag@cray.com> On Friday 29 February 2008 17:49, Evan Cheng wrote: > Let's try to solve one problem at a time. > > 1. Roman's depth / height patch calculation is obviously goodness. > Please commit that first. > 2. It's probably safe to eliminate the "special tie-breaker" from top > down sorting function. > 3. We will need to fix up the sorting functions so strict ordering is > preserved. We need to do so without breaking any of the existing test > case. "return left->NodeNum < right->NodeNum;" doesn't. :-( What does > "return false" mean? Is it favoring nodes that are inserted earlier? > 4. It might be wise to add some debugging code so we can tell where > things start diverge. > 5. It would be nice to be able to rebalance the heap. Roman and David > can fight it out when we get to that point. :-) Sounds good. I don't know what "fight it out" means, however. :) It's more than "nice" to rebalance the heap. It's necessary if we want to avoid traps when _GLIBCXX_DEBUG is enabled. And we want to do that because it finds lots of bugs. -Dave From romix.llvm at googlemail.com Mon Mar 3 11:18:51 2008 From: romix.llvm at googlemail.com (Roman Levenstein) Date: Mon, 3 Mar 2008 18:18:51 +0100 Subject: [llvm-commits] Patch for review: Speeding up ScheduleDAG computations In-Reply-To: <200803031053.00270.dag@cray.com> References: <200803031053.00270.dag@cray.com> Message-ID: Hi Dave, 2008/3/3, David Greene : > On Friday 29 February 2008 17:49, Evan Cheng wrote: > > Let's try to solve one problem at a time. > > > > 1. Roman's depth / height patch calculation is obviously goodness. > > Please commit that first. > > 2. It's probably safe to eliminate the "special tie-breaker" from top > > down sorting function. > > 3. We will need to fix up the sorting functions so strict ordering is > > preserved. We need to do so without breaking any of the existing test > > case. "return left->NodeNum < right->NodeNum;" doesn't. :-( What does > > "return false" mean? Is it favoring nodes that are inserted earlier? > > 4. It might be wise to add some debugging code so we can tell where > > things start diverge. > > 5. It would be nice to be able to rebalance the heap. Roman and David > > can fight it out when we get to that point. :-) > > > Sounds good. I don't know what "fight it out" means, however. :) Me either ;) > It's more than "nice" to rebalance the heap. It's necessary if we > want to avoid traps when _GLIBCXX_DEBUG is enabled. And we > want to do that because it finds lots of bugs. Totally agree. Here is a proposed patch for ScheduleDAGRRList.cpp. It contains the following changes: 1) Uses std::set instead of the priority queue. This makes removal of nodes very fast and removes a bottleneck 2) sorting functions use now strict ordering 3) According to your proposal, it takes node priority updates into account and updates the priority queue by removing and re-inserting the updated element. 4) SumOfUnscheduledPredsOfSuccs is slightly changed to avoid useless computations. This saves a LOT OF time on big basic blocks. Please review and test, if possible. I have problems with running the llvm-test test-suite. When I to run it (and keep in mind, I never did it before), I always get the following error messages on my X86/Ubuntu system: make[4]: *** No rule to make target `Output/sse.expandfft.linked.rbc', needed by `Output/sse.expandfft.linked.bc'. Stop. -Roman -------------- next part -------------- A non-text attachment was scrubbed... Name: ScheduleDAGRRList.patch Type: text/x-diff Size: 4571 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20080303/bae9ca5c/attachment.bin From tonic at nondot.org Mon Mar 3 11:32:40 2008 From: tonic at nondot.org (Tanya Lattner) Date: Mon, 03 Mar 2008 17:32:40 -0000 Subject: [llvm-commits] [llvm] r47845 - /llvm/trunk/tools/Makefile Message-ID: <200803031732.m23HWePC004163@zion.cs.uiuc.edu> Author: tbrethou Date: Mon Mar 3 11:32:40 2008 New Revision: 47845 URL: http://llvm.org/viewvc/llvm-project?rev=47845&view=rev Log: Renable lto2 build. Modified: llvm/trunk/tools/Makefile Modified: llvm/trunk/tools/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/Makefile?rev=47845&r1=47844&r2=47845&view=diff ============================================================================== --- llvm/trunk/tools/Makefile (original) +++ llvm/trunk/tools/Makefile Mon Mar 3 11:32:40 2008 @@ -26,7 +26,7 @@ # only build new lto project on Darwin for now ifeq ($(OS),Darwin) -#PARALLEL_DIRS += lto2 +PARALLEL_DIRS += lto2 endif include $(LEVEL)/Makefile.common From dag at cray.com Mon Mar 3 11:48:51 2008 From: dag at cray.com (David Greene) Date: Mon, 3 Mar 2008 11:48:51 -0600 Subject: [llvm-commits] Patch for review: Speeding up ScheduleDAG computations In-Reply-To: References: <200803031053.00270.dag@cray.com> Message-ID: <200803031148.51509.dag@cray.com> On Monday 03 March 2008 11:18, Roman Levenstein wrote: > Here is a proposed patch for ScheduleDAGRRList.cpp. It contains the > following changes: > 1) Uses std::set instead of the priority queue. This makes removal of > nodes very fast and removes a bottleneck > 2) sorting functions use now strict ordering > 3) According to your proposal, it takes node priority updates into > account and updates the priority queue by removing and re-inserting > the updated element. > 4) SumOfUnscheduledPredsOfSuccs is slightly changed to avoid useless > computations. This saves a LOT OF time on big basic blocks. > > Please review and test, if possible. I have problems with running the I'm building and running tests with it right now. The patch is goodness. It avoids the clumsy and esoteric container_reference_wrapper and that alone makes it superior to my solution. If it speeds everything up as well, it's a no brainer to apply it assuming it passes testing. -Dave From lattner at apple.com Mon Mar 3 11:53:14 2008 From: lattner at apple.com (Tanya Lattner) Date: Mon, 3 Mar 2008 09:53:14 -0800 Subject: [llvm-commits] Patch for review: Speeding up ScheduleDAG computations In-Reply-To: References: <200803031053.00270.dag@cray.com> Message-ID: > Totally agree. > > Here is a proposed patch for ScheduleDAGRRList.cpp. It contains the > following changes: > 1) Uses std::set instead of the priority queue. This makes removal of > nodes very fast and removes a bottleneck > 2) sorting functions use now strict ordering > 3) According to your proposal, it takes node priority updates into > account and updates the priority queue by removing and re-inserting > the updated element. > 4) SumOfUnscheduledPredsOfSuccs is slightly changed to avoid useless > computations. This saves a LOT OF time on big basic blocks. > > Please review and test, if possible. I have problems with running the > llvm-test test-suite. When I to run it (and keep in mind, I never did > it before), I always get the following error messages on my X86/Ubuntu > system: > make[4]: *** No rule to make target > `Output/sse.expandfft.linked.rbc', needed by > `Output/sse.expandfft.linked.bc'. Stop. > > Please keep in mind that all proposed patches should have been tested before submitting. This includes llvm-test and 'make check'. http://llvm.org/docs/DeveloperPolicy.html#quality This will make Evan's job easier ;) As for the error in llvm-test that you are seeing, can you use 'make VERBOSE=1 TEST=nightly report' and post more details on what make is running? It looks like an error in configuration. Did you reconfigure once you set llvm-gcc path? Thanks, Tanya -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20080303/c9452d9b/attachment.html From gohman at apple.com Mon Mar 3 11:58:42 2008 From: gohman at apple.com (Dan Gohman) Date: Mon, 3 Mar 2008 09:58:42 -0800 Subject: [llvm-commits] Fwd: Patch for review: Speeding up ScheduleDAG computations In-Reply-To: References: <2913F98D-C5BD-44BD-A404-5E6DFFEDCFBC@apple.com> <200802291429.22322.dag@cray.com> Message-ID: Hi Roman, Just one comment on this patch from me; in this change: > SUnit *pop() { > if (empty()) return NULL; > - SUnit *V = Queue.top(); > - Queue.pop(); > + SUnit *V = *Queue.rbegin(); > + Queue.erase(V); > return V; > } The erase call here uses the "key" form of erase, so it incurs a lookup. This can can be avoided by using the iterator form, something like this: set::iterator i = prior(Queue.end()); SUnit *V = *i; Queue.erase(i); Dan On Mar 3, 2008, at 3:06 AM, Roman Levenstein wrote: > Hi, > > > 2008/3/1, Evan Cheng : > >> Let's try to solve one problem at a time. >> >> 1. Roman's depth / height patch calculation is obviously goodness. >> Please commit that first. > > > Here is the patch for ScheduleDAGList.cpp: computing priorities using > a linear algorithm. It uses the same idea as the height/depth > computation, i.e. dynamic programming. I took into account all > comments from Dan & Evan from last review. > > Additionally, I use now std::set instead of a priority queue. The > results are exactly the same as with the current SVN version - I > really compared it side-by-side during execution. Using std::set makes > operations such as removal from the middle of the queue much faster > and removes a bottleneck. Scheduling of very bigs BBs is now up to 3-4 > times faster. > > Please, review this new version, if it is OK for submission. > > And there is one more patch to come, for the ScheduleDAGRRList.cpp, > which would also use std::set instead of priority queues, introduce > strict ordering and contain queue update changes as David suggested. > > -Roman > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From lauro.venancio at gmail.com Mon Mar 3 12:24:36 2008 From: lauro.venancio at gmail.com (Lauro Ramos Venancio) Date: Mon, 03 Mar 2008 18:24:36 -0000 Subject: [llvm-commits] [test-suite] r47846 - /test-suite/trunk/RunSafely.sh Message-ID: <200803031824.m23IOaac005910@zion.cs.uiuc.edu> Author: laurov Date: Mon Mar 3 12:24:36 2008 New Revision: 47846 URL: http://llvm.org/viewvc/llvm-project?rev=47846&view=rev Log: Fix remote tests on Linux. Modified: test-suite/trunk/RunSafely.sh Modified: test-suite/trunk/RunSafely.sh URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/RunSafely.sh?rev=47846&r1=47845&r2=47846&view=diff ============================================================================== --- test-suite/trunk/RunSafely.sh (original) +++ test-suite/trunk/RunSafely.sh Mon Mar 3 12:24:36 2008 @@ -99,7 +99,7 @@ # necessary I/O redirection. # PWD=`pwd` -COMMAND="$PROGRAM $*" +COMMAND="$PWD/$PROGRAM $*" if [ "$SYSTEM" = "Darwin" ]; then COMMAND="${DIR}TimedExec.sh $ULIMIT $PWD $COMMAND" fi From dpatel at apple.com Mon Mar 3 12:36:03 2008 From: dpatel at apple.com (Devang Patel) Date: Mon, 03 Mar 2008 18:36:03 -0000 Subject: [llvm-commits] [llvm] r47847 - /llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp Message-ID: <200803031836.m23Ia3c5006434@zion.cs.uiuc.edu> Author: dpatel Date: Mon Mar 3 12:36:03 2008 New Revision: 47847 URL: http://llvm.org/viewvc/llvm-project?rev=47847&view=rev Log: Preserve paramater attributes. Modified: llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp Modified: llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp?rev=47847&r1=47846&r2=47847&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp Mon Mar 3 12:36:03 2008 @@ -17,6 +17,7 @@ #include "llvm/Module.h" #include "llvm/CallGraphSCCPass.h" #include "llvm/Instructions.h" +#include "llvm/ParamAttrsList.h" #include "llvm/Analysis/CallGraph.h" #include "llvm/Support/CallSite.h" #include "llvm/Support/CFG.h" @@ -181,21 +182,34 @@ Function *SRETPromotion::cloneFunctionBody(Function *F, const StructType *STy) { - // FIXME : Do not drop param attributes on the floor. const FunctionType *FTy = F->getFunctionType(); std::vector Params; + // ParamAttrs - Keep track of the parameter attributes for the arguments. + ParamAttrsVector ParamAttrsVec; + const ParamAttrsList *PAL = F->getParamAttrs(); + + // Add any return attributes. + if (ParameterAttributes attrs = PAL ? PAL->getParamAttrs(0) : ParamAttr::None) + ParamAttrsVec.push_back(ParamAttrsWithIndex::get(0, attrs)); + // Skip first argument. Function::arg_iterator I = F->arg_begin(), E = F->arg_end(); ++I; + unsigned ParamIndex = 1; // 0th parameter attribute is reserved for return type. while (I != E) { Params.push_back(I->getType()); + if (ParameterAttributes attrs = PAL ? PAL->getParamAttrs(ParamIndex) : + ParamAttr::None) + ParamAttrsVec.push_back(ParamAttrsWithIndex::get(Params.size(), attrs)); ++I; + ++ParamIndex; } FunctionType *NFTy = FunctionType::get(STy, Params, FTy->isVarArg()); Function *NF = new Function(NFTy, F->getLinkage(), F->getName()); NF->setCallingConv(F->getCallingConv()); + NF->setParamAttrs(ParamAttrsList::get(ParamAttrsVec)); F->getParent()->getFunctionList().insert(F, NF); NF->getBasicBlockList().splice(NF->begin(), F->getBasicBlockList()); @@ -217,20 +231,32 @@ /// updateCallSites - Update all sites that call F to use NF. void SRETPromotion::updateCallSites(Function *F, Function *NF) { - // FIXME : Handle parameter attributes SmallVector Args; + // ParamAttrs - Keep track of the parameter attributes for the arguments. + ParamAttrsVector ParamAttrsVec; + for (Value::use_iterator FUI = F->use_begin(), FUE = F->use_end(); FUI != FUE;) { CallSite CS = CallSite::get(*FUI); ++FUI; Instruction *Call = CS.getInstruction(); + const ParamAttrsList *PAL = F->getParamAttrs(); + // Add any return attributes. + if (ParameterAttributes attrs = PAL ? PAL->getParamAttrs(0) : ParamAttr::None) + ParamAttrsVec.push_back(ParamAttrsWithIndex::get(0, attrs)); + // Copy arguments, however skip first one. CallSite::arg_iterator AI = CS.arg_begin(), AE = CS.arg_end(); Value *FirstCArg = *AI; ++AI; + unsigned ParamIndex = 1; // 0th parameter attribute is reserved for return type. while (AI != AE) { Args.push_back(*AI); + if (ParameterAttributes Attrs = PAL ? PAL->getParamAttrs(ParamIndex) : + ParamAttr::None) + ParamAttrsVec.push_back(ParamAttrsWithIndex::get(Args.size(), Attrs)); + ++ParamIndex; ++AI; } @@ -240,13 +266,16 @@ New = new InvokeInst(NF, II->getNormalDest(), II->getUnwindDest(), Args.begin(), Args.end(), "", Call); cast(New)->setCallingConv(CS.getCallingConv()); + cast(New)->setParamAttrs(ParamAttrsList::get(ParamAttrsVec)); } else { New = new CallInst(NF, Args.begin(), Args.end(), "", Call); cast(New)->setCallingConv(CS.getCallingConv()); + cast(New)->setParamAttrs(ParamAttrsList::get(ParamAttrsVec)); if (cast(Call)->isTailCall()) cast(New)->setTailCall(); } Args.clear(); + ParamAttrsVec.clear(); New->takeName(Call); // Update all users of sret parameter to extract value using getresult. From dpatel at apple.com Mon Mar 3 12:58:16 2008 From: dpatel at apple.com (Devang Patel) Date: Mon, 03 Mar 2008 18:58:16 -0000 Subject: [llvm-commits] [llvm] r47848 - in /llvm/trunk/lib/VMCore: Function.cpp Verifier.cpp Message-ID: <200803031858.m23IwGpW007057@zion.cs.uiuc.edu> Author: dpatel Date: Mon Mar 3 12:58:16 2008 New Revision: 47848 URL: http://llvm.org/viewvc/llvm-project?rev=47848&view=rev Log: If a function uses multive values in ret instruction then it is returning a struct value. Modified: llvm/trunk/lib/VMCore/Function.cpp llvm/trunk/lib/VMCore/Verifier.cpp Modified: llvm/trunk/lib/VMCore/Function.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Function.cpp?rev=47848&r1=47847&r2=47848&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Function.cpp (original) +++ llvm/trunk/lib/VMCore/Function.cpp Mon Mar 3 12:58:16 2008 @@ -170,7 +170,8 @@ /// @brief Determine if the function returns a structure. bool Function::isStructReturn() const { - return paramHasAttr(1, ParamAttr::StructRet); + return paramHasAttr(1, ParamAttr::StructRet) + || isa(getReturnType()); } //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/VMCore/Verifier.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Verifier.cpp?rev=47848&r1=47847&r2=47848&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Verifier.cpp (original) +++ llvm/trunk/lib/VMCore/Verifier.cpp Mon Mar 3 12:58:16 2008 @@ -455,9 +455,6 @@ isa(F.getReturnType()), "Functions cannot return aggregate values!", &F); - Assert1(!F.isStructReturn() || FT->getReturnType() == Type::VoidTy, - "Invalid struct-return function!", &F); - const ParamAttrsList *Attrs = F.getParamAttrs(); Assert1(!Attrs || From dpatel at apple.com Mon Mar 3 12:58:47 2008 From: dpatel at apple.com (Devang Patel) Date: Mon, 03 Mar 2008 18:58:47 -0000 Subject: [llvm-commits] [llvm] r47849 - in /llvm/trunk/lib/AsmParser: llvmAsmParser.cpp.cvs llvmAsmParser.h.cvs llvmAsmParser.y.cvs Message-ID: <200803031858.m23IwlsV007089@zion.cs.uiuc.edu> Author: dpatel Date: Mon Mar 3 12:58:47 2008 New Revision: 47849 URL: http://llvm.org/viewvc/llvm-project?rev=47849&view=rev Log: regenerate. Modified: llvm/trunk/lib/AsmParser/llvmAsmParser.cpp.cvs llvm/trunk/lib/AsmParser/llvmAsmParser.h.cvs llvm/trunk/lib/AsmParser/llvmAsmParser.y.cvs Modified: llvm/trunk/lib/AsmParser/llvmAsmParser.cpp.cvs URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/llvmAsmParser.cpp.cvs?rev=47849&r1=47848&r2=47849&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/llvmAsmParser.cpp.cvs (original) +++ llvm/trunk/lib/AsmParser/llvmAsmParser.cpp.cvs Mon Mar 3 12:58:47 2008 @@ -139,89 +139,90 @@ X86_STDCALLCC_TOK = 320, X86_FASTCALLCC_TOK = 321, DATALAYOUT = 322, - RET = 323, - BR = 324, - SWITCH = 325, - INVOKE = 326, - UNWIND = 327, - UNREACHABLE = 328, - ADD = 329, - SUB = 330, - MUL = 331, - UDIV = 332, - SDIV = 333, - FDIV = 334, - UREM = 335, - SREM = 336, - FREM = 337, - AND = 338, - OR = 339, - XOR = 340, - SHL = 341, - LSHR = 342, - ASHR = 343, - ICMP = 344, - FCMP = 345, - EQ = 346, - NE = 347, - SLT = 348, - SGT = 349, - SLE = 350, - SGE = 351, - ULT = 352, - UGT = 353, - ULE = 354, - UGE = 355, - OEQ = 356, - ONE = 357, - OLT = 358, - OGT = 359, - OLE = 360, - OGE = 361, - ORD = 362, - UNO = 363, - UEQ = 364, - UNE = 365, - MALLOC = 366, - ALLOCA = 367, - FREE = 368, - LOAD = 369, - STORE = 370, - GETELEMENTPTR = 371, - TRUNC = 372, - ZEXT = 373, - SEXT = 374, - FPTRUNC = 375, - FPEXT = 376, - BITCAST = 377, - UITOFP = 378, - SITOFP = 379, - FPTOUI = 380, - FPTOSI = 381, - INTTOPTR = 382, - PTRTOINT = 383, - PHI_TOK = 384, - SELECT = 385, - VAARG = 386, - EXTRACTELEMENT = 387, - INSERTELEMENT = 388, - SHUFFLEVECTOR = 389, - GETRESULT = 390, - SIGNEXT = 391, - ZEROEXT = 392, - NORETURN = 393, - INREG = 394, - SRET = 395, - NOUNWIND = 396, - NOALIAS = 397, - BYVAL = 398, - NEST = 399, - READNONE = 400, - READONLY = 401, - GC = 402, - DEFAULT = 403, - HIDDEN = 404, - PROTECTED = 405 + UNWIND_TO = 323, + RET = 324, + BR = 325, + SWITCH = 326, + INVOKE = 327, + UNWIND = 328, + UNREACHABLE = 329, + ADD = 330, + SUB = 331, + MUL = 332, + UDIV = 333, + SDIV = 334, + FDIV = 335, + UREM = 336, + SREM = 337, + FREM = 338, + AND = 339, + OR = 340, + XOR = 341, + SHL = 342, + LSHR = 343, + ASHR = 344, + ICMP = 345, + FCMP = 346, + EQ = 347, + NE = 348, + SLT = 349, + SGT = 350, + SLE = 351, + SGE = 352, + ULT = 353, + UGT = 354, + ULE = 355, + UGE = 356, + OEQ = 357, + ONE = 358, + OLT = 359, + OGT = 360, + OLE = 361, + OGE = 362, + ORD = 363, + UNO = 364, + UEQ = 365, + UNE = 366, + MALLOC = 367, + ALLOCA = 368, + FREE = 369, + LOAD = 370, + STORE = 371, + GETELEMENTPTR = 372, + TRUNC = 373, + ZEXT = 374, + SEXT = 375, + FPTRUNC = 376, + FPEXT = 377, + BITCAST = 378, + UITOFP = 379, + SITOFP = 380, + FPTOUI = 381, + FPTOSI = 382, + INTTOPTR = 383, + PTRTOINT = 384, + PHI_TOK = 385, + SELECT = 386, + VAARG = 387, + EXTRACTELEMENT = 388, + INSERTELEMENT = 389, + SHUFFLEVECTOR = 390, + GETRESULT = 391, + SIGNEXT = 392, + ZEROEXT = 393, + NORETURN = 394, + INREG = 395, + SRET = 396, + NOUNWIND = 397, + NOALIAS = 398, + BYVAL = 399, + NEST = 400, + READNONE = 401, + READONLY = 402, + GC = 403, + DEFAULT = 404, + HIDDEN = 405, + PROTECTED = 406 }; #endif /* Tokens. */ @@ -290,89 +291,90 @@ #define X86_STDCALLCC_TOK 320 #define X86_FASTCALLCC_TOK 321 #define DATALAYOUT 322 -#define RET 323 -#define BR 324 -#define SWITCH 325 -#define INVOKE 326 -#define UNWIND 327 -#define UNREACHABLE 328 -#define ADD 329 -#define SUB 330 -#define MUL 331 -#define UDIV 332 -#define SDIV 333 -#define FDIV 334 -#define UREM 335 -#define SREM 336 -#define FREM 337 -#define AND 338 -#define OR 339 -#define XOR 340 -#define SHL 341 -#define LSHR 342 -#define ASHR 343 -#define ICMP 344 -#define FCMP 345 -#define EQ 346 -#define NE 347 -#define SLT 348 -#define SGT 349 -#define SLE 350 -#define SGE 351 -#define ULT 352 -#define UGT 353 -#define ULE 354 -#define UGE 355 -#define OEQ 356 -#define ONE 357 -#define OLT 358 -#define OGT 359 -#define OLE 360 -#define OGE 361 -#define ORD 362 -#define UNO 363 -#define UEQ 364 -#define UNE 365 -#define MALLOC 366 -#define ALLOCA 367 -#define FREE 368 -#define LOAD 369 -#define STORE 370 -#define GETELEMENTPTR 371 -#define TRUNC 372 -#define ZEXT 373 -#define SEXT 374 -#define FPTRUNC 375 -#define FPEXT 376 -#define BITCAST 377 -#define UITOFP 378 -#define SITOFP 379 -#define FPTOUI 380 -#define FPTOSI 381 -#define INTTOPTR 382 -#define PTRTOINT 383 -#define PHI_TOK 384 -#define SELECT 385 -#define VAARG 386 -#define EXTRACTELEMENT 387 -#define INSERTELEMENT 388 -#define SHUFFLEVECTOR 389 -#define GETRESULT 390 -#define SIGNEXT 391 -#define ZEROEXT 392 -#define NORETURN 393 -#define INREG 394 -#define SRET 395 -#define NOUNWIND 396 -#define NOALIAS 397 -#define BYVAL 398 -#define NEST 399 -#define READNONE 400 -#define READONLY 401 -#define GC 402 -#define DEFAULT 403 -#define HIDDEN 404 -#define PROTECTED 405 +#define UNWIND_TO 323 +#define RET 324 +#define BR 325 +#define SWITCH 326 +#define INVOKE 327 +#define UNWIND 328 +#define UNREACHABLE 329 +#define ADD 330 +#define SUB 331 +#define MUL 332 +#define UDIV 333 +#define SDIV 334 +#define FDIV 335 +#define UREM 336 +#define SREM 337 +#define FREM 338 +#define AND 339 +#define OR 340 +#define XOR 341 +#define SHL 342 +#define LSHR 343 +#define ASHR 344 +#define ICMP 345 +#define FCMP 346 +#define EQ 347 +#define NE 348 +#define SLT 349 +#define SGT 350 +#define SLE 351 +#define SGE 352 +#define ULT 353 +#define UGT 354 +#define ULE 355 +#define UGE 356 +#define OEQ 357 +#define ONE 358 +#define OLT 359 +#define OGT 360 +#define OLE 361 +#define OGE 362 +#define ORD 363 +#define UNO 364 +#define UEQ 365 +#define UNE 366 +#define MALLOC 367 +#define ALLOCA 368 +#define FREE 369 +#define LOAD 370 +#define STORE 371 +#define GETELEMENTPTR 372 +#define TRUNC 373 +#define ZEXT 374 +#define SEXT 375 +#define FPTRUNC 376 +#define FPEXT 377 +#define BITCAST 378 +#define UITOFP 379 +#define SITOFP 380 +#define FPTOUI 381 +#define FPTOSI 382 +#define INTTOPTR 383 +#define PTRTOINT 384 +#define PHI_TOK 385 +#define SELECT 386 +#define VAARG 387 +#define EXTRACTELEMENT 388 +#define INSERTELEMENT 389 +#define SHUFFLEVECTOR 390 +#define GETRESULT 391 +#define SIGNEXT 392 +#define ZEROEXT 393 +#define NORETURN 394 +#define INREG 395 +#define SRET 396 +#define NOUNWIND 397 +#define NOALIAS 398 +#define BYVAL 399 +#define NEST 400 +#define READNONE 401 +#define READONLY 402 +#define GC 403 +#define DEFAULT 404 +#define HIDDEN 405 +#define PROTECTED 406 @@ -886,7 +888,7 @@ /// defineBBVal - This is a definition of a new basic block with the specified /// identifier which must be the same as CurFun.NextValNum, if its numeric. -static BasicBlock *defineBBVal(const ValID &ID) { +static BasicBlock *defineBBVal(const ValID &ID, BasicBlock *unwindDest) { assert(inFunctionScope() && "Can't get basic block at global scope!"); BasicBlock *BB = 0; @@ -916,21 +918,19 @@ assert(ID.Num == CurFun.NextValNum && "Invalid new block number"); InsertValue(BB); } - - ID.destroy(); - return BB; - } - - // We haven't seen this BB before and its first mention is a definition. - // Just create it and return it. - std::string Name (ID.Type == ValID::LocalName ? ID.getName() : ""); - BB = new BasicBlock(Name, CurFun.CurrentFunction); - if (ID.Type == ValID::LocalID) { - assert(ID.Num == CurFun.NextValNum && "Invalid new block number"); - InsertValue(BB); + } else { + // We haven't seen this BB before and its first mention is a definition. + // Just create it and return it. + std::string Name (ID.Type == ValID::LocalName ? ID.getName() : ""); + BB = new BasicBlock(Name, CurFun.CurrentFunction); + if (ID.Type == ValID::LocalID) { + assert(ID.Num == CurFun.NextValNum && "Invalid new block number"); + InsertValue(BB); + } } - ID.destroy(); // Free strdup'd memory + ID.destroy(); + BB->setUnwindDest(unwindDest); return BB; } @@ -1338,7 +1338,7 @@ #if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED typedef union YYSTYPE -#line 953 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 951 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { llvm::Module *ModuleVal; llvm::Function *FunctionVal; @@ -1614,20 +1614,20 @@ /* YYFINAL -- State number of the termination state. */ #define YYFINAL 43 /* YYLAST -- Last index in YYTABLE. */ -#define YYLAST 1978 +#define YYLAST 2038 /* YYNTOKENS -- Number of terminals. */ -#define YYNTOKENS 165 +#define YYNTOKENS 166 /* YYNNTS -- Number of nonterminals. */ #define YYNNTS 85 /* YYNRULES -- Number of rules. */ -#define YYNRULES 322 +#define YYNRULES 324 /* YYNRULES -- Number of states. */ -#define YYNSTATES 629 +#define YYNSTATES 633 /* YYTRANSLATE(YYLEX) -- Bison symbol number corresponding to YYLEX. */ #define YYUNDEFTOK 2 -#define YYMAXUTOK 405 +#define YYMAXUTOK 406 #define YYTRANSLATE(YYX) \ ((unsigned int) (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK) @@ -1639,15 +1639,15 @@ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, - 151, 152, 155, 2, 154, 2, 2, 2, 2, 2, + 152, 153, 156, 2, 155, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, - 160, 153, 161, 2, 2, 2, 2, 2, 2, 2, + 161, 154, 162, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, - 2, 157, 156, 159, 2, 2, 2, 2, 2, 164, + 2, 158, 157, 160, 2, 2, 2, 2, 2, 165, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, - 158, 2, 2, 162, 2, 163, 2, 2, 2, 2, + 159, 2, 2, 163, 2, 164, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, @@ -1675,7 +1675,7 @@ 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, - 145, 146, 147, 148, 149, 150 + 145, 146, 147, 148, 149, 150, 151 }; #if YYDEBUG @@ -1710,157 +1710,158 @@ 664, 675, 677, 679, 684, 686, 688, 691, 695, 696, 698, 700, 702, 704, 706, 708, 710, 712, 714, 718, 720, 726, 728, 730, 732, 734, 736, 738, 741, 743, - 747, 750, 753, 757, 760, 761, 763, 766, 769, 773, - 783, 793, 802, 817, 819, 821, 828, 834, 837, 844, - 852, 857, 862, 869, 876, 877, 878, 882, 885, 887, - 893, 899, 906, 913, 918, 925, 930, 935, 942, 949, - 952, 961, 963, 965, 966, 970, 977, 981, 988, 991, - 997, 1005, 1011 + 747, 750, 753, 757, 760, 761, 764, 766, 770, 773, + 776, 780, 790, 800, 809, 824, 826, 828, 835, 841, + 844, 851, 859, 864, 869, 876, 883, 884, 885, 889, + 892, 894, 900, 906, 913, 920, 925, 932, 937, 942, + 949, 956, 959, 968, 970, 972, 973, 977, 984, 988, + 995, 998, 1004, 1012, 1018 }; /* YYRHS -- A `-1'-separated list of the rules' RHS. */ static const yytype_int16 yyrhs[] = { - 211, 0, -1, 74, -1, 75, -1, 76, -1, 77, - -1, 78, -1, 79, -1, 80, -1, 81, -1, 82, - -1, 86, -1, 87, -1, 88, -1, 83, -1, 84, - -1, 85, -1, 117, -1, 118, -1, 119, -1, 120, - -1, 121, -1, 122, -1, 123, -1, 124, -1, 125, - -1, 126, -1, 127, -1, 128, -1, 91, -1, 92, - -1, 93, -1, 94, -1, 95, -1, 96, -1, 97, - -1, 98, -1, 99, -1, 100, -1, 101, -1, 102, - -1, 103, -1, 104, -1, 105, -1, 106, -1, 107, - -1, 108, -1, 109, -1, 110, -1, 97, -1, 98, - -1, 99, -1, 100, -1, 26, -1, 27, -1, 11, + 212, 0, -1, 75, -1, 76, -1, 77, -1, 78, + -1, 79, -1, 80, -1, 81, -1, 82, -1, 83, + -1, 87, -1, 88, -1, 89, -1, 84, -1, 85, + -1, 86, -1, 118, -1, 119, -1, 120, -1, 121, + -1, 122, -1, 123, -1, 124, -1, 125, -1, 126, + -1, 127, -1, 128, -1, 129, -1, 92, -1, 93, + -1, 94, -1, 95, -1, 96, -1, 97, -1, 98, + -1, 99, -1, 100, -1, 101, -1, 102, -1, 103, + -1, 104, -1, 105, -1, 106, -1, 107, -1, 108, + -1, 109, -1, 110, -1, 111, -1, 98, -1, 99, + -1, 100, -1, 101, -1, 26, -1, 27, -1, 11, -1, 12, -1, 13, -1, 16, -1, 15, -1, 14, - -1, 19, -1, 22, -1, 24, -1, 173, -1, -1, - 54, 151, 4, 152, -1, -1, 173, 153, -1, -1, - 20, -1, 23, -1, 179, -1, -1, 177, 153, -1, + -1, 19, -1, 22, -1, 24, -1, 174, -1, -1, + 54, 152, 4, 153, -1, -1, 174, 154, -1, -1, + 20, -1, 23, -1, 180, -1, -1, 178, 154, -1, 42, -1, 44, -1, 43, -1, 45, -1, 47, -1, - 46, -1, 48, -1, 50, -1, -1, 148, -1, 149, - -1, 150, -1, -1, 46, -1, 48, -1, -1, 42, + 46, -1, 48, -1, 50, -1, -1, 149, -1, 150, + -1, 151, -1, -1, 46, -1, 48, -1, -1, 42, -1, 43, -1, 44, -1, 47, -1, -1, 44, -1, 42, -1, -1, 62, -1, 63, -1, 64, -1, 65, - -1, 66, -1, 61, 4, -1, 137, -1, 118, -1, - 136, -1, 119, -1, 139, -1, 140, -1, 142, -1, - 143, -1, 144, -1, 53, 4, -1, -1, 188, 187, - -1, 138, -1, 141, -1, 137, -1, 136, -1, 145, - -1, 146, -1, -1, 190, 189, -1, -1, 147, 22, - -1, -1, 53, 4, -1, -1, 154, 53, 4, -1, - 34, 22, -1, -1, 194, -1, -1, 154, 197, 196, - -1, 194, -1, 53, 4, -1, 11, -1, 12, -1, + -1, 66, -1, 61, 4, -1, 138, -1, 119, -1, + 137, -1, 120, -1, 140, -1, 141, -1, 143, -1, + 144, -1, 145, -1, 53, 4, -1, -1, 189, 188, + -1, 139, -1, 142, -1, 138, -1, 137, -1, 146, + -1, 147, -1, -1, 191, 190, -1, -1, 148, 22, + -1, -1, 53, 4, -1, -1, 155, 53, 4, -1, + 34, 22, -1, -1, 195, -1, -1, 155, 198, 197, + -1, 195, -1, 53, 4, -1, 11, -1, 12, -1, 13, -1, 16, -1, 15, -1, 14, -1, 17, -1, - 49, -1, 198, -1, 199, 175, 155, -1, 233, -1, - 156, 4, -1, 199, 151, 203, 152, 190, -1, 10, - 151, 203, 152, 190, -1, 157, 4, 158, 199, 159, - -1, 160, 4, 158, 199, 161, -1, 162, 204, 163, - -1, 162, 163, -1, 160, 162, 204, 163, 161, -1, - 160, 162, 163, 161, -1, 199, 188, -1, 199, -1, - 10, -1, 200, -1, 202, 154, 200, -1, 202, -1, - 202, 154, 39, -1, 39, -1, -1, 199, -1, 204, - 154, 199, -1, 199, 157, 207, 159, -1, 199, 157, - 159, -1, 199, 164, 22, -1, 199, 160, 207, 161, - -1, 199, 162, 207, 163, -1, 199, 162, 163, -1, - 199, 160, 162, 207, 163, 161, -1, 199, 160, 162, - 163, 161, -1, 199, 40, -1, 199, 41, -1, 199, - 233, -1, 199, 206, -1, 199, 25, -1, 171, 3, - -1, 171, 5, -1, 171, 4, -1, 171, 6, -1, - 11, 26, -1, 11, 27, -1, 172, 9, -1, 168, - 151, 205, 38, 199, 152, -1, 116, 151, 205, 245, - 152, -1, 130, 151, 205, 154, 205, 154, 205, 152, - -1, 166, 151, 205, 154, 205, 152, -1, 167, 151, - 205, 154, 205, 152, -1, 89, 169, 151, 205, 154, - 205, 152, -1, 90, 170, 151, 205, 154, 205, 152, - -1, 132, 151, 205, 154, 205, 152, -1, 133, 151, - 205, 154, 205, 154, 205, 152, -1, 134, 151, 205, - 154, 205, 154, 205, 152, -1, 207, 154, 205, -1, - 205, -1, 32, -1, 33, -1, 37, -1, -1, 201, - 233, -1, 122, 151, 210, 38, 199, 152, -1, 212, - -1, -1, 213, -1, 212, 213, -1, -1, 31, 214, - 229, -1, -1, 30, 215, 230, -1, 59, 58, 219, - -1, 176, 18, 199, -1, 176, 18, 10, -1, -1, - 178, 182, 209, 208, 205, 175, 216, 196, -1, -1, - 178, 180, 182, 209, 208, 205, 175, 217, 196, -1, - -1, 178, 181, 182, 209, 208, 199, 175, 218, 196, - -1, 178, 182, 35, 185, 210, -1, 51, 220, -1, - 55, 153, 221, -1, 22, -1, 52, 153, 22, -1, - 67, 153, 22, -1, 157, 222, 159, -1, 222, 154, - 22, -1, 22, -1, -1, 223, 154, 199, 188, 174, - -1, 199, 188, 174, -1, 223, -1, 223, 154, 39, - -1, 39, -1, -1, 186, 201, 177, 151, 224, 152, - 190, 195, 192, 191, -1, 28, -1, 162, -1, 184, - 182, 225, 226, -1, 29, -1, 163, -1, 237, 228, - -1, 183, 182, 225, -1, -1, 60, -1, 3, -1, + 49, -1, 199, -1, 200, 176, 156, -1, 234, -1, + 157, 4, -1, 200, 152, 204, 153, 191, -1, 10, + 152, 204, 153, 191, -1, 158, 4, 159, 200, 160, + -1, 161, 4, 159, 200, 162, -1, 163, 205, 164, + -1, 163, 164, -1, 161, 163, 205, 164, 162, -1, + 161, 163, 164, 162, -1, 200, 189, -1, 200, -1, + 10, -1, 201, -1, 203, 155, 201, -1, 203, -1, + 203, 155, 39, -1, 39, -1, -1, 200, -1, 205, + 155, 200, -1, 200, 158, 208, 160, -1, 200, 158, + 160, -1, 200, 165, 22, -1, 200, 161, 208, 162, + -1, 200, 163, 208, 164, -1, 200, 163, 164, -1, + 200, 161, 163, 208, 164, 162, -1, 200, 161, 163, + 164, 162, -1, 200, 40, -1, 200, 41, -1, 200, + 234, -1, 200, 207, -1, 200, 25, -1, 172, 3, + -1, 172, 5, -1, 172, 4, -1, 172, 6, -1, + 11, 26, -1, 11, 27, -1, 173, 9, -1, 169, + 152, 206, 38, 200, 153, -1, 117, 152, 206, 246, + 153, -1, 131, 152, 206, 155, 206, 155, 206, 153, + -1, 167, 152, 206, 155, 206, 153, -1, 168, 152, + 206, 155, 206, 153, -1, 90, 170, 152, 206, 155, + 206, 153, -1, 91, 171, 152, 206, 155, 206, 153, + -1, 133, 152, 206, 155, 206, 153, -1, 134, 152, + 206, 155, 206, 155, 206, 153, -1, 135, 152, 206, + 155, 206, 155, 206, 153, -1, 208, 155, 206, -1, + 206, -1, 32, -1, 33, -1, 37, -1, -1, 202, + 234, -1, 123, 152, 211, 38, 200, 153, -1, 213, + -1, -1, 214, -1, 213, 214, -1, -1, 31, 215, + 230, -1, -1, 30, 216, 231, -1, 59, 58, 220, + -1, 177, 18, 200, -1, 177, 18, 10, -1, -1, + 179, 183, 210, 209, 206, 176, 217, 197, -1, -1, + 179, 181, 183, 210, 209, 206, 176, 218, 197, -1, + -1, 179, 182, 183, 210, 209, 200, 176, 219, 197, + -1, 179, 183, 35, 186, 211, -1, 51, 221, -1, + 55, 154, 222, -1, 22, -1, 52, 154, 22, -1, + 67, 154, 22, -1, 158, 223, 160, -1, 223, 155, + 22, -1, 22, -1, -1, 224, 155, 200, 189, 175, + -1, 200, 189, 175, -1, 224, -1, 224, 155, 39, + -1, 39, -1, -1, 187, 202, 178, 152, 225, 153, + 191, 196, 193, 192, -1, 28, -1, 163, -1, 185, + 183, 226, 227, -1, 29, -1, 164, -1, 238, 229, + -1, 184, 183, 226, -1, -1, 60, -1, 3, -1, 4, -1, 9, -1, 26, -1, 27, -1, 40, -1, - 41, -1, 25, -1, 160, 207, 161, -1, 206, -1, - 58, 231, 22, 154, 22, -1, 7, -1, 8, -1, - 173, -1, 177, -1, 233, -1, 232, -1, 199, 234, - -1, 235, -1, 236, 154, 235, -1, 237, 238, -1, - 227, 238, -1, 239, 176, 240, -1, 239, 242, -1, - -1, 21, -1, 68, 236, -1, 68, 10, -1, 69, - 17, 234, -1, 69, 11, 234, 154, 17, 234, 154, - 17, 234, -1, 70, 171, 234, 154, 17, 234, 157, - 241, 159, -1, 70, 171, 234, 154, 17, 234, 157, - 159, -1, 71, 186, 201, 234, 151, 244, 152, 190, - 38, 17, 234, 72, 17, 234, -1, 72, -1, 73, - -1, 241, 171, 232, 154, 17, 234, -1, 171, 232, - 154, 17, 234, -1, 176, 247, -1, 199, 157, 234, - 154, 234, 159, -1, 243, 154, 157, 234, 154, 234, - 159, -1, 199, 188, 234, 188, -1, 17, 188, 234, - 188, -1, 244, 154, 199, 188, 234, 188, -1, 244, - 154, 17, 188, 234, 188, -1, -1, -1, 245, 154, - 235, -1, 57, 56, -1, 56, -1, 166, 199, 234, - 154, 234, -1, 167, 199, 234, 154, 234, -1, 89, - 169, 199, 234, 154, 234, -1, 90, 170, 199, 234, - 154, 234, -1, 168, 235, 38, 199, -1, 130, 235, - 154, 235, 154, 235, -1, 131, 235, 154, 199, -1, - 132, 235, 154, 235, -1, 133, 235, 154, 235, 154, - 235, -1, 134, 235, 154, 235, 154, 235, -1, 129, - 243, -1, 246, 186, 201, 234, 151, 244, 152, 190, - -1, 249, -1, 36, -1, -1, 111, 199, 193, -1, - 111, 199, 154, 11, 234, 193, -1, 112, 199, 193, - -1, 112, 199, 154, 11, 234, 193, -1, 113, 235, - -1, 248, 114, 199, 234, 193, -1, 248, 115, 235, - 154, 199, 234, 193, -1, 135, 199, 233, 154, 4, - -1, 116, 199, 234, 245, -1 + 41, -1, 25, -1, 161, 208, 162, -1, 207, -1, + 58, 232, 22, 155, 22, -1, 7, -1, 8, -1, + 174, -1, 178, -1, 234, -1, 233, -1, 200, 235, + -1, 236, -1, 237, 155, 236, -1, 238, 239, -1, + 228, 239, -1, 240, 177, 241, -1, 240, 243, -1, + -1, 68, 235, -1, 21, -1, 21, 68, 235, -1, + 69, 237, -1, 69, 10, -1, 70, 17, 235, -1, + 70, 11, 235, 155, 17, 235, 155, 17, 235, -1, + 71, 172, 235, 155, 17, 235, 158, 242, 160, -1, + 71, 172, 235, 155, 17, 235, 158, 160, -1, 72, + 187, 202, 235, 152, 245, 153, 191, 38, 17, 235, + 73, 17, 235, -1, 73, -1, 74, -1, 242, 172, + 233, 155, 17, 235, -1, 172, 233, 155, 17, 235, + -1, 177, 248, -1, 200, 158, 235, 155, 235, 160, + -1, 244, 155, 158, 235, 155, 235, 160, -1, 200, + 189, 235, 189, -1, 17, 189, 235, 189, -1, 245, + 155, 200, 189, 235, 189, -1, 245, 155, 17, 189, + 235, 189, -1, -1, -1, 246, 155, 236, -1, 57, + 56, -1, 56, -1, 167, 200, 235, 155, 235, -1, + 168, 200, 235, 155, 235, -1, 90, 170, 200, 235, + 155, 235, -1, 91, 171, 200, 235, 155, 235, -1, + 169, 236, 38, 200, -1, 131, 236, 155, 236, 155, + 236, -1, 132, 236, 155, 200, -1, 133, 236, 155, + 236, -1, 134, 236, 155, 236, 155, 236, -1, 135, + 236, 155, 236, 155, 236, -1, 130, 244, -1, 247, + 187, 202, 235, 152, 245, 153, 191, -1, 250, -1, + 36, -1, -1, 112, 200, 194, -1, 112, 200, 155, + 11, 235, 194, -1, 113, 200, 194, -1, 113, 200, + 155, 11, 235, 194, -1, 114, 236, -1, 249, 115, + 200, 235, 194, -1, 249, 116, 236, 155, 200, 235, + 194, -1, 136, 200, 234, 155, 4, -1, 117, 200, + 235, 246, -1 }; /* YYRLINE[YYN] -- source line where rule number YYN was defined. */ static const yytype_uint16 yyrline[] = { - 0, 1115, 1115, 1115, 1115, 1115, 1115, 1115, 1115, 1115, - 1115, 1116, 1116, 1116, 1116, 1116, 1116, 1117, 1117, 1117, - 1117, 1117, 1117, 1118, 1118, 1118, 1118, 1118, 1118, 1121, - 1121, 1122, 1122, 1123, 1123, 1124, 1124, 1125, 1125, 1129, - 1129, 1130, 1130, 1131, 1131, 1132, 1132, 1133, 1133, 1134, - 1134, 1135, 1135, 1136, 1137, 1142, 1143, 1143, 1143, 1143, - 1143, 1145, 1145, 1145, 1146, 1146, 1148, 1149, 1153, 1157, - 1162, 1162, 1164, 1165, 1170, 1176, 1177, 1178, 1179, 1180, - 1184, 1185, 1186, 1190, 1191, 1192, 1193, 1197, 1198, 1199, - 1203, 1204, 1205, 1206, 1207, 1211, 1212, 1213, 1216, 1217, - 1218, 1219, 1220, 1221, 1222, 1229, 1230, 1231, 1232, 1233, - 1234, 1235, 1236, 1237, 1238, 1242, 1243, 1248, 1249, 1250, - 1251, 1252, 1253, 1256, 1257, 1262, 1263, 1270, 1271, 1277, - 1278, 1287, 1295, 1296, 1301, 1302, 1303, 1308, 1321, 1321, - 1321, 1321, 1321, 1321, 1321, 1324, 1328, 1332, 1339, 1344, - 1352, 1382, 1407, 1412, 1422, 1432, 1436, 1446, 1453, 1462, - 1469, 1474, 1479, 1486, 1487, 1494, 1501, 1509, 1515, 1527, - 1555, 1571, 1598, 1626, 1652, 1672, 1698, 1718, 1730, 1737, - 1803, 1813, 1823, 1829, 1839, 1845, 1855, 1860, 1865, 1878, - 1890, 1912, 1920, 1926, 1937, 1942, 1947, 1953, 1959, 1968, - 1972, 1980, 1980, 1983, 1983, 1986, 1998, 2019, 2024, 2032, - 2033, 2037, 2037, 2041, 2041, 2044, 2047, 2071, 2083, 2082, - 2094, 2093, 2103, 2102, 2113, 2153, 2156, 2162, 2172, 2176, - 2181, 2183, 2188, 2193, 2202, 2212, 2223, 2227, 2236, 2245, - 2250, 2384, 2384, 2386, 2395, 2395, 2397, 2402, 2414, 2418, - 2423, 2427, 2431, 2435, 2439, 2443, 2447, 2451, 2455, 2480, - 2484, 2494, 2498, 2502, 2507, 2514, 2514, 2520, 2529, 2534, - 2539, 2543, 2552, 2561, 2570, 2574, 2582, 2589, 2593, 2598, - 2608, 2627, 2636, 2727, 2731, 2738, 2749, 2762, 2772, 2783, - 2793, 2804, 2812, 2822, 2829, 2832, 2833, 2840, 2844, 2849, - 2865, 2882, 2896, 2910, 2922, 2930, 2937, 2943, 2949, 2955, - 2970, 3068, 3073, 3077, 3084, 3091, 3099, 3106, 3114, 3122, - 3136, 3153, 3161 + 0, 1113, 1113, 1113, 1113, 1113, 1113, 1113, 1113, 1113, + 1113, 1114, 1114, 1114, 1114, 1114, 1114, 1115, 1115, 1115, + 1115, 1115, 1115, 1116, 1116, 1116, 1116, 1116, 1116, 1119, + 1119, 1120, 1120, 1121, 1121, 1122, 1122, 1123, 1123, 1127, + 1127, 1128, 1128, 1129, 1129, 1130, 1130, 1131, 1131, 1132, + 1132, 1133, 1133, 1134, 1135, 1140, 1141, 1141, 1141, 1141, + 1141, 1143, 1143, 1143, 1144, 1144, 1146, 1147, 1151, 1155, + 1160, 1160, 1162, 1163, 1168, 1174, 1175, 1176, 1177, 1178, + 1182, 1183, 1184, 1188, 1189, 1190, 1191, 1195, 1196, 1197, + 1201, 1202, 1203, 1204, 1205, 1209, 1210, 1211, 1214, 1215, + 1216, 1217, 1218, 1219, 1220, 1227, 1228, 1229, 1230, 1231, + 1232, 1233, 1234, 1235, 1236, 1240, 1241, 1246, 1247, 1248, + 1249, 1250, 1251, 1254, 1255, 1260, 1261, 1268, 1269, 1275, + 1276, 1285, 1293, 1294, 1299, 1300, 1301, 1306, 1319, 1319, + 1319, 1319, 1319, 1319, 1319, 1322, 1326, 1330, 1337, 1342, + 1350, 1380, 1405, 1410, 1420, 1430, 1434, 1444, 1451, 1460, + 1467, 1472, 1477, 1484, 1485, 1492, 1499, 1507, 1513, 1525, + 1553, 1569, 1596, 1624, 1650, 1670, 1696, 1716, 1728, 1735, + 1801, 1811, 1821, 1827, 1837, 1843, 1853, 1858, 1863, 1876, + 1888, 1910, 1918, 1924, 1935, 1940, 1945, 1951, 1957, 1966, + 1970, 1978, 1978, 1981, 1981, 1984, 1996, 2017, 2022, 2030, + 2031, 2035, 2035, 2039, 2039, 2042, 2045, 2069, 2081, 2080, + 2092, 2091, 2101, 2100, 2111, 2151, 2154, 2160, 2170, 2174, + 2179, 2181, 2186, 2191, 2200, 2210, 2221, 2225, 2234, 2243, + 2248, 2382, 2382, 2384, 2393, 2393, 2395, 2400, 2412, 2416, + 2421, 2425, 2429, 2433, 2437, 2441, 2445, 2449, 2453, 2478, + 2482, 2492, 2496, 2500, 2505, 2512, 2512, 2518, 2527, 2532, + 2537, 2541, 2550, 2559, 2568, 2572, 2576, 2581, 2588, 2595, + 2599, 2604, 2614, 2633, 2642, 2733, 2737, 2744, 2755, 2768, + 2778, 2789, 2799, 2810, 2818, 2828, 2835, 2838, 2839, 2846, + 2850, 2855, 2871, 2888, 2902, 2916, 2928, 2936, 2943, 2949, + 2955, 2961, 2976, 3074, 3079, 3083, 3090, 3097, 3105, 3112, + 3120, 3128, 3142, 3159, 3167 }; #endif @@ -1881,26 +1882,27 @@ "EXTERNAL", "TARGET", "TRIPLE", "ALIGN", "ADDRSPACE", "DEPLIBS", "CALL", "TAIL", "ASM_TOK", "MODULE", "SIDEEFFECT", "CC_TOK", "CCC_TOK", "FASTCC_TOK", "COLDCC_TOK", "X86_STDCALLCC_TOK", "X86_FASTCALLCC_TOK", - "DATALAYOUT", "RET", "BR", "SWITCH", "INVOKE", "UNWIND", "UNREACHABLE", - "ADD", "SUB", "MUL", "UDIV", "SDIV", "FDIV", "UREM", "SREM", "FREM", - "AND", "OR", "XOR", "SHL", "LSHR", "ASHR", "ICMP", "FCMP", "EQ", "NE", - "SLT", "SGT", "SLE", "SGE", "ULT", "UGT", "ULE", "UGE", "OEQ", "ONE", - "OLT", "OGT", "OLE", "OGE", "ORD", "UNO", "UEQ", "UNE", "MALLOC", - "ALLOCA", "FREE", "LOAD", "STORE", "GETELEMENTPTR", "TRUNC", "ZEXT", - "SEXT", "FPTRUNC", "FPEXT", "BITCAST", "UITOFP", "SITOFP", "FPTOUI", - "FPTOSI", "INTTOPTR", "PTRTOINT", "PHI_TOK", "SELECT", "VAARG", - "EXTRACTELEMENT", "INSERTELEMENT", "SHUFFLEVECTOR", "GETRESULT", - "SIGNEXT", "ZEROEXT", "NORETURN", "INREG", "SRET", "NOUNWIND", "NOALIAS", - "BYVAL", "NEST", "READNONE", "READONLY", "GC", "DEFAULT", "HIDDEN", - "PROTECTED", "'('", "')'", "'='", "','", "'*'", "'\\\\'", "'['", "'x'", - "']'", "'<'", "'>'", "'{'", "'}'", "'c'", "$accept", "ArithmeticOps", - "LogicalOps", "CastOps", "IPredicates", "FPredicates", "IntType", - "FPType", "LocalName", "OptLocalName", "OptAddrSpace", "OptLocalAssign", - "GlobalName", "OptGlobalAssign", "GlobalAssign", "GVInternalLinkage", - "GVExternalLinkage", "GVVisibilityStyle", "FunctionDeclareLinkage", - "FunctionDefineLinkage", "AliasLinkage", "OptCallingConv", "ParamAttr", - "OptParamAttrs", "FuncAttr", "OptFuncAttrs", "OptGC", "OptAlign", - "OptCAlign", "SectionString", "OptSection", "GlobalVarAttributes", + "DATALAYOUT", "UNWIND_TO", "RET", "BR", "SWITCH", "INVOKE", "UNWIND", + "UNREACHABLE", "ADD", "SUB", "MUL", "UDIV", "SDIV", "FDIV", "UREM", + "SREM", "FREM", "AND", "OR", "XOR", "SHL", "LSHR", "ASHR", "ICMP", + "FCMP", "EQ", "NE", "SLT", "SGT", "SLE", "SGE", "ULT", "UGT", "ULE", + "UGE", "OEQ", "ONE", "OLT", "OGT", "OLE", "OGE", "ORD", "UNO", "UEQ", + "UNE", "MALLOC", "ALLOCA", "FREE", "LOAD", "STORE", "GETELEMENTPTR", + "TRUNC", "ZEXT", "SEXT", "FPTRUNC", "FPEXT", "BITCAST", "UITOFP", + "SITOFP", "FPTOUI", "FPTOSI", "INTTOPTR", "PTRTOINT", "PHI_TOK", + "SELECT", "VAARG", "EXTRACTELEMENT", "INSERTELEMENT", "SHUFFLEVECTOR", + "GETRESULT", "SIGNEXT", "ZEROEXT", "NORETURN", "INREG", "SRET", + "NOUNWIND", "NOALIAS", "BYVAL", "NEST", "READNONE", "READONLY", "GC", + "DEFAULT", "HIDDEN", "PROTECTED", "'('", "')'", "'='", "','", "'*'", + "'\\\\'", "'['", "'x'", "']'", "'<'", "'>'", "'{'", "'}'", "'c'", + "$accept", "ArithmeticOps", "LogicalOps", "CastOps", "IPredicates", + "FPredicates", "IntType", "FPType", "LocalName", "OptLocalName", + "OptAddrSpace", "OptLocalAssign", "GlobalName", "OptGlobalAssign", + "GlobalAssign", "GVInternalLinkage", "GVExternalLinkage", + "GVVisibilityStyle", "FunctionDeclareLinkage", "FunctionDefineLinkage", + "AliasLinkage", "OptCallingConv", "ParamAttr", "OptParamAttrs", + "FuncAttr", "OptFuncAttrs", "OptGC", "OptAlign", "OptCAlign", + "SectionString", "OptSection", "GlobalVarAttributes", "GlobalVarAttribute", "PrimType", "Types", "ArgType", "ResultTypes", "ArgTypeList", "ArgTypeListI", "TypeListI", "ConstVal", "ConstExpr", "ConstVector", "GlobalType", "ThreadLocal", "AliaseeRef", "Module", @@ -1935,47 +1937,47 @@ 375, 376, 377, 378, 379, 380, 381, 382, 383, 384, 385, 386, 387, 388, 389, 390, 391, 392, 393, 394, 395, 396, 397, 398, 399, 400, 401, 402, 403, 404, - 405, 40, 41, 61, 44, 42, 92, 91, 120, 93, - 60, 62, 123, 125, 99 + 405, 406, 40, 41, 61, 44, 42, 92, 91, 120, + 93, 60, 62, 123, 125, 99 }; # endif /* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */ static const yytype_uint8 yyr1[] = { - 0, 165, 166, 166, 166, 166, 166, 166, 166, 166, - 166, 167, 167, 167, 167, 167, 167, 168, 168, 168, - 168, 168, 168, 168, 168, 168, 168, 168, 168, 169, + 0, 166, 167, 167, 167, 167, 167, 167, 167, 167, + 167, 168, 168, 168, 168, 168, 168, 169, 169, 169, 169, 169, 169, 169, 169, 169, 169, 169, 169, 170, - 170, 170, 170, 170, 170, 170, 170, 170, 170, 170, - 170, 170, 170, 170, 170, 171, 172, 172, 172, 172, - 172, 173, 173, 173, 174, 174, 175, 175, 176, 176, - 177, 177, 178, 178, 179, 180, 180, 180, 180, 180, - 181, 181, 181, 182, 182, 182, 182, 183, 183, 183, - 184, 184, 184, 184, 184, 185, 185, 185, 186, 186, - 186, 186, 186, 186, 186, 187, 187, 187, 187, 187, - 187, 187, 187, 187, 187, 188, 188, 189, 189, 189, - 189, 189, 189, 190, 190, 191, 191, 192, 192, 193, - 193, 194, 195, 195, 196, 196, 197, 197, 198, 198, - 198, 198, 198, 198, 198, 199, 199, 199, 199, 199, - 199, 199, 199, 199, 199, 199, 199, 199, 200, 201, - 201, 202, 202, 203, 203, 203, 203, 204, 204, 205, - 205, 205, 205, 205, 205, 205, 205, 205, 205, 205, - 205, 205, 205, 205, 205, 205, 205, 205, 205, 206, + 170, 170, 170, 170, 170, 170, 170, 170, 170, 171, + 171, 171, 171, 171, 171, 171, 171, 171, 171, 171, + 171, 171, 171, 171, 171, 172, 173, 173, 173, 173, + 173, 174, 174, 174, 175, 175, 176, 176, 177, 177, + 178, 178, 179, 179, 180, 181, 181, 181, 181, 181, + 182, 182, 182, 183, 183, 183, 183, 184, 184, 184, + 185, 185, 185, 185, 185, 186, 186, 186, 187, 187, + 187, 187, 187, 187, 187, 188, 188, 188, 188, 188, + 188, 188, 188, 188, 188, 189, 189, 190, 190, 190, + 190, 190, 190, 191, 191, 192, 192, 193, 193, 194, + 194, 195, 196, 196, 197, 197, 198, 198, 199, 199, + 199, 199, 199, 199, 199, 200, 200, 200, 200, 200, + 200, 200, 200, 200, 200, 200, 200, 200, 201, 202, + 202, 203, 203, 204, 204, 204, 204, 205, 205, 206, + 206, 206, 206, 206, 206, 206, 206, 206, 206, 206, 206, 206, 206, 206, 206, 206, 206, 206, 206, 207, - 207, 208, 208, 209, 209, 210, 210, 211, 211, 212, - 212, 214, 213, 215, 213, 213, 213, 213, 216, 213, - 217, 213, 218, 213, 213, 213, 213, 219, 220, 220, - 221, 222, 222, 222, 223, 223, 224, 224, 224, 224, - 225, 226, 226, 227, 228, 228, 229, 230, 231, 231, - 232, 232, 232, 232, 232, 232, 232, 232, 232, 232, - 232, 233, 233, 233, 233, 234, 234, 235, 236, 236, - 237, 237, 238, 239, 239, 239, 240, 240, 240, 240, - 240, 240, 240, 240, 240, 241, 241, 242, 243, 243, - 244, 244, 244, 244, 244, 245, 245, 246, 246, 247, - 247, 247, 247, 247, 247, 247, 247, 247, 247, 247, - 247, 247, 248, 248, 249, 249, 249, 249, 249, 249, - 249, 249, 249 + 207, 207, 207, 207, 207, 207, 207, 207, 207, 208, + 208, 209, 209, 210, 210, 211, 211, 212, 212, 213, + 213, 215, 214, 216, 214, 214, 214, 214, 217, 214, + 218, 214, 219, 214, 214, 214, 214, 220, 221, 221, + 222, 223, 223, 223, 224, 224, 225, 225, 225, 225, + 226, 227, 227, 228, 229, 229, 230, 231, 232, 232, + 233, 233, 233, 233, 233, 233, 233, 233, 233, 233, + 233, 234, 234, 234, 234, 235, 235, 236, 237, 237, + 238, 238, 239, 240, 240, 240, 240, 240, 241, 241, + 241, 241, 241, 241, 241, 241, 241, 242, 242, 243, + 244, 244, 245, 245, 245, 245, 245, 246, 246, 247, + 247, 248, 248, 248, 248, 248, 248, 248, 248, 248, + 248, 248, 248, 248, 249, 249, 250, 250, 250, 250, + 250, 250, 250, 250, 250 }; /* YYR2[YYN] -- Number of symbols composing right hand side of rule YYN. */ @@ -2008,12 +2010,12 @@ 10, 1, 1, 4, 1, 1, 2, 3, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3, 1, 5, 1, 1, 1, 1, 1, 1, 2, 1, 3, - 2, 2, 3, 2, 0, 1, 2, 2, 3, 9, - 9, 8, 14, 1, 1, 6, 5, 2, 6, 7, - 4, 4, 6, 6, 0, 0, 3, 2, 1, 5, - 5, 6, 6, 4, 6, 4, 4, 6, 6, 2, - 8, 1, 1, 0, 3, 6, 3, 6, 2, 5, - 7, 5, 4 + 2, 2, 3, 2, 0, 2, 1, 3, 2, 2, + 3, 9, 9, 8, 14, 1, 1, 6, 5, 2, + 6, 7, 4, 4, 6, 6, 0, 0, 3, 2, + 1, 5, 5, 6, 6, 4, 6, 4, 4, 6, + 6, 2, 8, 1, 1, 0, 3, 6, 3, 6, + 2, 5, 7, 5, 4 }; /* YYDEFACT[STATE-NAME] -- Default rule to reduce with in state @@ -2030,158 +2032,160 @@ 226, 227, 215, 261, 262, 217, 138, 139, 140, 143, 142, 141, 144, 145, 0, 0, 0, 0, 263, 264, 146, 216, 148, 204, 204, 95, 203, 0, 98, 98, - 275, 271, 69, 244, 245, 246, 270, 228, 229, 232, - 0, 166, 149, 0, 0, 0, 0, 155, 167, 0, - 0, 166, 0, 0, 0, 97, 96, 0, 201, 202, - 0, 0, 99, 100, 101, 102, 103, 0, 247, 0, - 313, 273, 0, 230, 165, 115, 161, 163, 0, 0, - 0, 0, 0, 0, 154, 0, 0, 147, 0, 0, - 160, 0, 159, 0, 224, 138, 139, 140, 143, 142, - 141, 0, 0, 67, 67, 104, 0, 241, 242, 243, - 312, 298, 0, 0, 0, 0, 98, 283, 284, 2, - 3, 4, 5, 6, 7, 8, 9, 10, 14, 15, - 16, 11, 12, 13, 0, 0, 0, 0, 0, 0, - 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, - 27, 28, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 272, 98, 287, 0, 311, 231, 158, 0, - 123, 67, 67, 157, 0, 168, 0, 123, 67, 67, - 0, 205, 186, 187, 182, 184, 183, 185, 188, 181, - 177, 178, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 180, 179, 218, 0, - 297, 277, 67, 268, 276, 0, 0, 55, 0, 0, - 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, - 0, 53, 54, 49, 50, 51, 52, 39, 40, 41, - 42, 43, 44, 45, 46, 47, 48, 0, 129, 129, - 318, 67, 67, 309, 0, 0, 0, 0, 0, 67, - 67, 67, 0, 0, 0, 0, 0, 106, 108, 107, - 105, 109, 110, 111, 112, 113, 116, 164, 162, 151, - 152, 153, 156, 66, 150, 220, 222, 0, 0, 0, - 0, 0, 0, 0, 0, 170, 200, 0, 0, 0, - 174, 0, 171, 0, 0, 0, 134, 239, 250, 251, - 252, 257, 253, 254, 255, 256, 248, 0, 259, 266, - 265, 267, 0, 0, 278, 0, 0, 67, 67, 0, - 314, 0, 316, 295, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 67, 0, 114, 120, - 119, 117, 118, 121, 122, 124, 134, 134, 0, 0, - 0, 295, 0, 0, 0, 0, 0, 169, 155, 167, - 0, 172, 173, 0, 0, 0, 0, 219, 238, 115, - 236, 0, 249, 0, 0, 269, 0, 0, 0, 0, - 0, 0, 0, 0, 322, 0, 0, 0, 305, 306, - 0, 0, 0, 0, 0, 303, 0, 129, 0, 221, - 223, 67, 0, 0, 0, 0, 0, 0, 0, 199, - 176, 0, 0, 0, 0, 0, 0, 136, 134, 65, - 0, 123, 0, 258, 0, 0, 294, 0, 0, 129, - 130, 129, 0, 0, 0, 0, 0, 0, 321, 299, - 300, 294, 0, 319, 67, 206, 0, 0, 190, 0, - 0, 0, 0, 175, 0, 0, 67, 131, 137, 135, - 64, 235, 237, 115, 132, 0, 0, 0, 115, 115, - 0, 301, 302, 315, 317, 296, 0, 0, 304, 307, - 308, 0, 129, 0, 0, 0, 196, 0, 0, 192, - 193, 189, 65, 133, 127, 260, 0, 0, 0, 0, - 123, 0, 288, 0, 123, 320, 194, 195, 0, 0, - 0, 234, 0, 125, 0, 281, 0, 0, 106, 108, - 115, 115, 0, 115, 115, 289, 310, 191, 197, 198, - 128, 0, 240, 279, 0, 280, 0, 291, 290, 0, - 0, 0, 126, 0, 0, 0, 115, 115, 0, 0, - 0, 293, 292, 286, 0, 0, 285, 0, 282 + 276, 0, 271, 69, 244, 245, 246, 270, 228, 229, + 232, 0, 166, 149, 0, 0, 0, 0, 155, 167, + 0, 0, 166, 0, 0, 0, 97, 96, 0, 201, + 202, 0, 0, 99, 100, 101, 102, 103, 0, 247, + 0, 0, 250, 251, 252, 257, 253, 254, 255, 256, + 248, 2, 3, 4, 5, 6, 7, 8, 9, 10, + 14, 15, 16, 11, 12, 13, 0, 0, 0, 17, + 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, + 28, 0, 0, 0, 0, 0, 0, 0, 0, 259, + 266, 265, 275, 315, 273, 0, 230, 165, 115, 161, + 163, 0, 0, 0, 0, 0, 0, 154, 0, 0, + 147, 0, 0, 160, 0, 159, 0, 224, 138, 139, + 140, 143, 142, 141, 0, 0, 67, 67, 104, 0, + 241, 242, 243, 277, 249, 0, 29, 30, 31, 32, + 33, 34, 35, 36, 37, 38, 0, 53, 54, 49, + 50, 51, 52, 39, 40, 41, 42, 43, 44, 45, + 46, 47, 48, 0, 0, 0, 0, 0, 0, 200, + 0, 0, 0, 0, 314, 300, 0, 0, 0, 0, + 98, 285, 286, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 272, + 98, 289, 0, 313, 231, 158, 0, 123, 67, 67, + 157, 0, 168, 0, 123, 67, 67, 0, 205, 186, + 187, 182, 184, 183, 185, 188, 181, 177, 178, 0, + 0, 0, 0, 180, 179, 218, 0, 0, 0, 0, + 297, 0, 0, 0, 0, 0, 258, 0, 0, 0, + 299, 279, 67, 268, 278, 0, 0, 55, 0, 0, + 0, 0, 129, 129, 320, 67, 67, 311, 0, 0, + 0, 0, 0, 67, 67, 67, 0, 0, 0, 0, + 0, 106, 108, 107, 105, 109, 110, 111, 112, 113, + 116, 164, 162, 151, 152, 153, 156, 66, 150, 220, + 222, 0, 170, 0, 0, 0, 174, 0, 171, 134, + 239, 0, 0, 0, 0, 0, 0, 0, 0, 199, + 0, 0, 0, 267, 0, 0, 280, 0, 0, 67, + 67, 0, 316, 0, 318, 297, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 67, 0, + 114, 120, 119, 117, 118, 121, 122, 124, 134, 134, + 0, 169, 155, 167, 0, 172, 173, 0, 219, 238, + 115, 236, 0, 260, 0, 0, 190, 0, 0, 0, + 0, 0, 0, 0, 67, 269, 0, 0, 0, 0, + 0, 0, 0, 0, 324, 0, 0, 0, 307, 308, + 0, 0, 0, 0, 0, 305, 0, 129, 0, 221, + 223, 67, 176, 0, 0, 0, 136, 134, 65, 0, + 123, 0, 0, 298, 0, 196, 0, 0, 192, 193, + 189, 0, 0, 296, 0, 0, 129, 130, 129, 0, + 0, 0, 0, 0, 323, 301, 302, 296, 0, 321, + 67, 206, 175, 131, 137, 135, 64, 235, 237, 115, + 132, 194, 195, 0, 0, 0, 0, 0, 115, 115, + 0, 303, 304, 317, 319, 0, 0, 306, 309, 310, + 0, 129, 65, 133, 127, 191, 197, 198, 0, 0, + 0, 0, 123, 0, 290, 0, 123, 322, 234, 0, + 125, 0, 283, 0, 0, 106, 108, 115, 115, 0, + 115, 115, 291, 312, 128, 0, 240, 281, 0, 282, + 0, 293, 292, 0, 0, 0, 126, 0, 0, 0, + 115, 115, 0, 0, 0, 295, 294, 288, 0, 0, + 287, 0, 284 }; /* YYDEFGOTO[NTERM-NUM]. */ static const yytype_int16 yydefgoto[] = { - -1, 263, 264, 265, 290, 307, 161, 162, 78, 531, - 112, 12, 79, 14, 15, 40, 41, 42, 47, 53, - 117, 127, 336, 228, 415, 339, 602, 583, 390, 487, - 564, 437, 488, 80, 163, 136, 153, 137, 138, 109, - 356, 378, 357, 120, 87, 154, 16, 17, 18, 20, - 19, 366, 416, 417, 62, 23, 60, 100, 440, 441, - 128, 169, 54, 95, 55, 48, 443, 379, 82, 381, - 273, 274, 56, 91, 92, 222, 587, 131, 313, 540, - 454, 223, 224, 225, 226 + -1, 176, 177, 178, 236, 253, 214, 215, 78, 547, + 113, 12, 79, 14, 15, 40, 41, 42, 47, 53, + 118, 128, 380, 295, 447, 383, 606, 590, 422, 506, + 574, 458, 507, 80, 216, 189, 206, 190, 191, 110, + 259, 179, 260, 121, 87, 207, 16, 17, 18, 20, + 19, 399, 448, 449, 62, 23, 60, 101, 461, 462, + 129, 222, 54, 96, 55, 48, 225, 180, 82, 182, + 343, 344, 56, 92, 93, 289, 594, 184, 357, 560, + 404, 290, 291, 292, 293 }; /* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing STATE-NUM. */ -#define YYPACT_NINF -572 +#define YYPACT_NINF -565 static const yytype_int16 yypact[] = { - 284, -572, -572, -572, -572, -572, -572, -572, -13, -121, - 36, -94, 101, -55, 19, -572, 135, 883, -572, 165, - 162, 13, 27, -572, 4, 199, -572, 1464, -572, -572, - -572, -572, -572, -572, -572, -572, -572, -572, -572, -572, - 106, 106, 203, -572, -572, -572, -572, 106, -572, -572, - -572, -572, -572, 106, 210, -572, -10, 215, 219, 224, - -572, -572, -572, -572, -572, 99, -572, -572, -572, -572, - -572, -572, -572, -572, 265, 271, 2, 126, -572, -572, - -572, 1, -572, 259, 259, 205, -572, 9, 382, 382, - -572, -572, 78, -572, -572, -572, -572, -572, -572, -572, - -32, 1059, -572, 147, 151, 506, 99, -572, 1, -114, - 166, 1059, 158, 9, 9, -572, -572, 1014, -572, -572, - 1504, 315, -572, -572, -572, -572, -572, 1562, -572, -2, - 1843, -572, 294, -572, -572, 1, -572, 172, 168, 1620, - 1620, 170, -68, 1620, -572, 329, 185, -572, 1504, 1620, - 99, 187, 1, 339, -572, 77, 333, 335, 336, 340, - 341, 262, 342, 1115, 298, -572, 139, -572, -572, -572, - -572, -572, 292, 1660, 59, 343, 382, -572, -572, -572, - -572, -572, -572, -572, -572, -572, -572, -572, -572, -572, - -572, -572, -572, -572, 312, 787, 1620, 1620, 1620, 1620, - -572, -572, -572, -572, -572, -572, -572, -572, -572, -572, - -572, -572, 1620, 1620, 1620, 1620, 1620, 1620, 1620, 1620, - 1620, 1620, -572, 382, -572, -42, -572, -572, 434, 1345, - -572, -31, -30, -572, 194, 1, 208, -572, 298, 3, - 1014, -572, -572, -572, -572, -572, -572, -572, -572, -572, - -572, -572, 312, 787, 213, 214, 218, 225, 228, 1385, - 1678, 609, 346, 230, 231, 238, -572, -572, -572, 242, - -572, 99, 702, -572, 241, 841, 841, -572, 841, 1562, - -572, -572, -572, -572, -572, -572, -572, -572, -572, -572, - 1620, -572, -572, -572, -572, -572, -572, -572, -572, -572, - -572, -572, -572, -572, -572, -572, -572, 1620, 97, 125, - -572, 702, -25, 244, 245, 261, 263, 266, 269, 14, - 702, 702, 358, 1562, 1620, 1620, 409, -572, -572, -572, - -572, -572, -572, -572, -572, -572, -572, -572, -572, -93, - -572, -572, -572, -572, -93, -572, 158, 378, 275, 277, - 1504, 1504, 1504, 1504, 1504, -572, -572, 80, 788, -83, - -572, -64, -572, 1504, 1504, 1504, 276, 1406, -572, -572, - -572, -572, -572, -572, -572, -572, 369, 1504, -572, -572, - -572, -572, 1620, 281, -572, 282, 841, 702, 702, 5, - -572, 7, -572, -572, 841, 274, 1620, 1620, 1620, 1620, - 1620, 283, 285, 287, 1620, 841, 702, 295, -572, -572, - -572, -572, -572, -572, -572, -572, 276, 276, 1620, 1504, - 1504, -572, 296, 299, 300, 301, 1504, -572, 306, 969, - -58, -572, -572, 302, 303, 421, -3, -572, -572, 1, - 307, 308, -572, 440, 22, -572, 451, 452, 321, 319, - 320, 841, 471, 841, 323, 324, 841, 328, 1, -572, - 330, 332, 479, 841, 841, 1, 337, 344, 1620, -572, - -572, -45, 347, 349, 133, 1504, 1504, 1504, 1504, -572, - -572, 334, 1504, 1504, 1620, 468, 487, -572, 276, 1746, - 1446, -572, 350, -572, 841, 841, 1718, 841, 841, 344, - -572, 344, 1620, 841, 351, 1620, 1620, 1620, -572, -572, - -572, 1718, 441, -572, 702, -572, 1504, 1504, -572, 352, - 348, 353, 357, -572, 360, 363, 64, -572, -572, -572, - -572, -572, -572, 1, 81, 474, 370, 374, 123, 1, - 138, -572, -572, -572, -572, -572, 368, 841, -572, -572, - -572, 171, 344, 380, 381, 1504, -572, 1504, 1504, -572, - -572, -572, 1746, -572, 483, -572, 520, -4, 560, 560, - -572, 1736, -572, 379, -572, -572, -572, -572, 394, 395, - 398, -572, 550, 410, 841, -572, 1255, -1, 405, 407, - -572, -572, 87, 123, 1, -572, -93, -572, -572, -572, - -572, 537, -572, -572, 411, -572, 1255, 434, 434, 544, - 560, 560, -572, 549, 418, 841, -572, -572, 841, 558, - 509, 434, 434, -572, 841, 571, -572, 841, -572 + 641, -565, -565, -565, -565, -565, -565, -565, -29, -130, + -24, -105, 35, -59, 335, -565, 103, 1109, -565, 53, + 231, -28, 10, -565, 31, 139, -565, 1574, -565, -565, + -565, -565, -565, -565, -565, -565, -565, -565, -565, -565, + 95, 95, 164, -565, -565, -565, -565, 95, -565, -565, + -565, -565, -565, 95, -12, -565, 7, 151, 155, 181, + -565, -565, -565, -565, -565, -68, -565, -565, -565, -565, + -565, -565, -565, -565, 205, 225, 9, 108, -565, -565, + -565, 50, -565, 149, 149, 242, -565, 182, 414, 414, + 166, 965, -565, 198, -565, -565, -565, -565, -565, -565, + -565, -110, 1185, -565, 89, 118, 590, -68, -565, 50, + -81, 69, 1185, 82, 182, 182, -565, -565, 1139, -565, + -565, 1592, 281, -565, -565, -565, -565, -565, 1632, -565, + -21, 965, -565, -565, -565, -565, -565, -565, -565, -565, + 228, -565, -565, -565, -565, -565, -565, -565, -565, -565, + -565, -565, -565, -565, -565, -565, 395, 547, 143, -565, + -565, -565, -565, -565, -565, -565, -565, -565, -565, -565, + -565, 154, 159, 163, 169, 1592, 177, 184, 188, -565, + -565, -565, -565, 1902, -565, 311, -565, -565, 50, -565, + 189, 192, 1691, 1691, 196, -74, 1691, -565, 346, 203, + -565, 1592, 1691, -68, 199, 50, 411, -565, 343, 350, + 354, 355, 356, 357, 314, 358, 1241, 319, -565, 12, + -565, -565, -565, -565, -565, 353, -565, -565, -565, -565, + -565, -565, -565, -565, -565, -565, 224, -565, -565, -565, + -565, -565, -565, -565, -565, -565, -565, -565, -565, -565, + -565, -565, -565, 232, 1592, 1592, 1592, 1592, 1592, -565, + -50, 1592, 1592, 1592, -565, -565, 336, 1749, 62, 382, + 414, -565, -565, 395, 547, 1691, 1691, 1691, 1691, 1691, + 1691, 1691, 1691, 1691, 1691, 1691, 1691, 1691, 1691, -565, + 414, -565, 148, -565, -565, 393, 1473, -565, -43, -15, + -565, 233, 50, 243, -565, 319, -39, 1139, -565, -565, + -565, -565, -565, -565, -565, -565, -565, -565, -565, 47, + 1789, 769, 375, -565, -565, -565, 248, 246, 1592, 1592, + -565, 253, 254, 257, 261, 1592, -565, 266, 267, 369, + -565, -68, 825, -565, 268, 965, 965, -565, 965, 1632, + 1691, 1691, 23, 28, -565, 825, -44, 270, 271, 274, + 277, 282, 283, 174, 825, 825, 398, 1632, 1691, 1691, + 435, -565, -565, -565, -565, -565, -565, -565, -565, -565, + -565, -565, -565, 323, -565, -565, -565, -565, 323, -565, + 82, 402, -565, 40, 874, 57, -565, -70, -565, 287, + 1513, 421, 290, 294, 141, 1592, 1592, 1592, 1592, -565, + 1592, 1592, 1691, -565, 1691, 296, -565, 297, 965, 825, + 825, 15, -565, 19, -565, -565, 965, 295, 1691, 1691, + 1691, 1691, 1691, 299, 309, 313, 1691, 965, 825, 316, + -565, -565, -565, -565, -565, -565, -565, -565, 287, 287, + 1691, -565, 320, 1094, -64, -565, -565, -1, -565, -565, + 50, 318, 328, -565, 1592, 1592, -565, 1691, 344, 345, + 347, 348, 351, 363, 84, -565, 484, 492, 365, 364, + 368, 965, 506, 965, 371, 372, 965, 374, 50, -565, + 377, 380, 514, 965, 965, 50, 389, 387, 1691, -565, + -565, 87, -565, 362, 521, 540, -565, 287, 194, 1534, + -565, 392, 394, -565, 1592, -565, 1592, 1592, -565, -565, + -565, 965, 965, 1807, 965, 965, 387, -565, 387, 965, + 391, 1691, 1691, 1691, -565, -565, -565, 1807, 497, -565, + 825, -565, -565, -565, -565, -565, -565, -565, -565, 50, + -3, -565, -565, 399, 401, 405, 396, 397, 79, 50, + 175, -565, -565, -565, -565, 400, 965, -565, -565, -565, + 202, 387, 194, -565, 508, -565, -565, -565, 542, 3, + 682, 682, -565, 1850, -565, 403, -565, -565, -565, 560, + 418, 965, -565, 1382, 5, 415, 416, -565, -565, 252, + 79, 50, -565, 323, -565, 548, -565, -565, 420, -565, + 1382, 393, 393, 552, 682, 682, -565, 554, 422, 965, + -565, -565, 965, 559, 505, 393, 393, -565, 965, 562, + -565, 965, -565 }; /* YYPGOTO[NTERM-NUM]. */ static const yytype_int16 yypgoto[] = { - -572, 459, 460, 461, 345, 354, -173, -572, 0, 30, - -150, 502, 8, -572, -572, -572, -572, 189, -572, -572, - -572, -149, -572, -409, -572, -234, -572, -572, -289, 61, - -572, -404, -572, -572, -26, 367, -122, -572, 488, 493, - -92, -159, -214, 84, 217, 362, -572, -572, 586, -572, - -572, -572, -572, -572, -572, -572, -572, -572, -572, -572, - 515, -572, -572, -572, -572, -572, -572, -571, -76, 46, - -105, -572, -572, 552, -572, -572, -572, -572, -572, 94, - 188, -572, -572, -572, -572 + -565, 404, 406, 407, 307, 308, -267, -565, 0, 14, + -195, 488, 4, -565, -565, -565, -565, 269, -565, -565, + -565, -243, -565, -452, -565, -299, -565, -565, -341, 34, + -565, -429, -565, -565, -26, 298, -125, -565, 479, 486, + -103, -210, -232, 153, 217, 286, -565, -565, 582, -565, + -565, -565, -565, -565, -565, -565, -565, -565, -565, -565, + 519, -565, -565, -565, -565, -565, -565, -564, -66, 102, + -240, -565, -565, 555, -565, -565, -565, -565, -565, 78, + 191, -565, -565, -565, -565 }; /* YYTABLE[YYPACT[STATE-NUM]]. What to do in state STATE-NUM. If @@ -2191,406 +2195,418 @@ #define YYTABLE_NINF -209 static const yytype_int16 yytable[] = { - 11, 81, 278, 344, 266, 166, 104, 277, 13, 110, - 277, 90, 469, 470, 268, 604, 451, 11, 453, 93, - 392, 63, 64, 110, 110, 13, 167, 279, 164, 110, - 489, 485, 24, 1, 2, 614, 3, 4, 5, 21, - 143, 118, 119, 409, 410, 411, 359, 361, 412, 144, - 486, 108, 413, 414, 22, 110, 238, 110, 452, 26, - 452, 29, 30, 31, 32, 33, 34, 35, 110, 36, - 275, 426, 324, 325, 323, 135, 276, 241, 431, 108, - -55, -55, -55, -55, 529, 135, 143, 267, 345, 346, - 426, 152, 11, 310, 25, 234, 426, 1, 28, 432, - 3, 152, 5, 242, 243, 481, 111, 515, 314, 315, - 316, 317, 318, 231, 232, 485, 322, 235, 110, 27, - 111, 111, 132, 239, 562, 609, 111, 133, 340, 568, - 569, 341, 394, 63, 64, 43, 106, 66, 67, 68, - 69, 70, 71, 72, 430, 1, 2, 272, 3, 4, - 5, 110, 111, 94, 111, 585, -67, 386, 605, 2, - 168, 59, 4, 444, 105, 111, 57, 37, 38, 39, - 308, 309, 272, 311, 269, 73, 426, -144, 513, 110, - 58, 607, 608, 493, 610, 611, 312, 272, 272, 272, - 272, 272, 319, 320, 321, 272, 380, 148, 149, 380, - 380, 405, 380, 135, 49, 50, 51, 621, 622, 52, - 543, 45, 544, 46, 152, 111, 561, 409, 410, 411, - 407, 61, 412, 409, 410, 411, 413, 414, 412, 83, - 84, 90, 413, 414, 426, 380, 88, 97, 85, 427, - 86, 98, 89, 401, 380, 380, 99, 115, 111, 116, - 101, 389, -67, 152, 37, 38, 39, 534, 421, 422, - 423, 424, 425, 575, 387, 244, 245, 246, 247, 102, - 266, 433, 434, 435, -144, 103, 111, 445, -144, 391, - -67, 388, 74, 75, -208, 518, 76, 502, 77, 107, - 570, 457, 571, 459, 460, 461, 86, 152, 406, 272, - 113, 114, -69, 1, 2, 139, 3, 4, 5, 140, - 380, 380, 380, 147, 6, 7, 227, 145, 380, 165, - 230, 383, 384, 574, 385, 571, 229, 472, 473, 380, - 380, 233, 429, 236, 479, 8, 592, 237, 240, 9, - 596, 439, -56, 10, -57, -60, 63, 64, 270, -59, - -58, 248, 110, 267, 277, 342, 272, 393, 1, 2, - 343, 3, 4, 5, 350, 351, 402, 403, 362, 352, - 272, 458, 272, 272, 272, 380, 353, 380, 465, 354, - 380, 363, 364, 519, 520, 521, 522, 380, 380, 365, - 524, 525, 471, 367, 586, 382, 404, 545, 395, 396, - 548, 549, 550, 280, 281, 282, 283, 284, 285, 286, - 287, 288, 289, 408, 606, 397, 418, 398, 380, 380, - 399, 380, 380, 400, 553, 554, 419, 380, 420, 442, - 436, 456, 448, 449, 450, 446, 447, 462, 380, 463, - 455, 464, 514, 121, 122, 123, 124, 125, 126, 468, - 475, 466, 467, 476, 477, 478, 482, 483, 526, 484, - 491, 490, 492, 578, 533, 579, 580, 480, 494, 495, - 539, 380, 496, 497, 498, 500, 272, 502, 503, 272, - 272, 272, 505, 508, 506, 539, 507, 326, 511, 530, - 527, 528, 380, 380, 452, 523, 565, 499, 512, 501, - 556, 516, 504, 517, 535, 547, 555, 557, 380, 509, - 510, 558, 559, 63, 64, 560, 106, 66, 67, 68, - 69, 70, 71, 72, 566, 1, 2, 572, 3, 4, - 5, 567, 576, 577, 380, 380, 582, 584, 595, 380, - 536, 537, 380, 541, 542, 594, 597, 598, 380, 546, - 599, 380, 327, 328, 600, 73, -18, 601, -19, 612, - 552, 615, 530, 368, 369, 613, 618, 63, 64, 370, - 329, 330, 619, 331, 332, 624, 333, 334, 335, 1, - 2, 625, 3, 4, 5, 371, 372, 373, 627, 219, - 220, 221, 581, 573, 130, 563, 338, 348, 142, 146, - 374, 375, 347, 44, 129, 551, 0, 349, 96, 474, - 0, 0, 0, 326, 590, 591, 63, 64, 376, 106, - 155, 156, 157, 158, 159, 160, 72, 0, 1, 2, - 603, 3, 4, 5, 179, 180, 181, 182, 183, 184, - 185, 186, 187, 188, 189, 190, 191, 192, 193, 252, - 253, 0, 0, 0, 0, 0, 616, 617, 73, 0, - 0, 620, 74, 75, 623, 0, 76, 0, 77, 141, - 626, 0, 0, 628, 0, 0, 254, 200, 588, 589, - 203, 204, 205, 206, 207, 208, 209, 210, 211, 0, - 255, 0, 256, 257, 258, 0, 329, 330, 0, 331, - 332, 0, 333, 334, 335, 368, 369, 0, 0, 63, - 64, 370, 0, 0, 0, 0, 0, 0, 0, 0, - 377, 1, 2, 0, 3, 4, 5, 371, 372, 373, + 11, 81, 348, 219, 13, 388, 323, 220, 508, 90, + 111, 111, 424, 105, 347, 111, 347, 11, 217, 499, + 500, 13, 325, 21, 24, 181, 481, 349, 90, 608, + 483, 504, 2, 504, 25, 4, 94, 354, 22, 111, + 358, 359, 360, 361, 362, 185, 618, 367, 366, 26, + 186, 109, 505, 27, 63, 64, 91, 107, 208, 209, + 210, 211, 212, 213, 72, 181, 1, 2, 482, 3, + 4, 5, 482, 345, 196, 91, 188, 111, 545, 346, + 109, 196, 111, 197, 102, 335, 188, 393, 395, 397, + 301, 335, 205, 11, 456, 28, 73, 572, 305, 45, + 503, 46, 205, 43, 111, 335, 580, 581, 112, 112, + 389, 390, 336, 112, 426, 63, 64, 384, 107, 66, + 67, 68, 69, 70, 71, 72, 57, 1, 2, 439, + 3, 4, 5, -144, 441, 442, 443, 112, 111, 444, + 308, 111, 221, 445, 446, 611, 612, 385, 614, 615, + 324, 330, 331, 332, 333, 334, 539, 73, 337, 338, + 339, 61, 454, 592, 58, 609, 298, 299, 625, 626, + 302, 95, 106, 98, 475, 112, 306, 99, 421, -67, + 112, 63, 64, 423, -67, 563, 86, 564, 487, 59, + 489, 490, 491, 1, 2, 335, 3, 4, 5, 85, + 451, 86, 112, 100, 74, 75, -67, 392, 76, 103, + 77, 550, 335, 1, 119, 120, 3, 1, 5, 455, + 3, 198, 5, 326, 418, 402, 403, 513, 111, 104, + 587, -144, 409, 223, 131, -144, 112, 520, 200, 112, + 541, 342, 437, 323, 37, 38, 39, 370, 192, 352, + 353, 342, 355, 356, 342, 342, 342, 342, 342, 363, + 364, 365, 342, 368, 369, 74, 75, 201, 202, 76, + 188, 77, 108, 49, 50, 51, 181, 193, 52, 181, + 181, 205, 181, 599, 116, 218, 117, 603, 224, 181, + 613, 567, 568, 569, 466, 254, 467, 433, 181, 181, + 114, 115, 468, 469, 470, 471, 255, 472, 473, 83, + 84, 256, 593, 371, 372, 257, 88, 311, 312, 313, + 314, 258, 89, 205, 419, 420, 112, 610, 582, 261, + 583, 373, 374, 294, 375, 376, 262, 377, 378, 379, + 263, 205, 438, 342, 296, 297, -55, -55, -55, -55, + 303, 307, 181, 181, 181, 586, 304, 583, 300, -56, + 181, 511, 512, -57, -60, -59, -58, 315, 453, 309, + 310, 181, 181, 111, 460, 327, 328, 29, 30, 31, + 32, 33, 34, 35, 329, 36, 474, 324, 342, 441, + 442, 443, 340, 347, 444, 386, 387, 398, 445, 446, + 400, 401, 342, 488, 342, 342, 342, 412, 405, 406, + 495, 553, 407, 554, 555, 181, 408, 181, 63, 64, + 181, 410, 411, 414, 501, 427, 428, 181, 181, 429, + 1, 2, 430, 3, 4, 5, 436, 431, 432, 440, + 450, 342, 457, 463, 413, 464, 370, 415, 416, 465, + 417, 476, 477, 486, 492, 181, 181, 425, 181, 181, + 441, 442, 443, 181, 493, 444, 434, 435, 494, 445, + 446, 498, 540, 509, 181, 122, 123, 124, 125, 126, + 127, 510, 502, 549, 37, 38, 39, 226, 227, 228, + 229, 230, 231, 232, 233, 234, 235, 559, 515, 514, + 181, 521, 516, 517, 518, 342, 342, 342, 546, 522, + 527, 559, 371, 372, 181, 181, 519, 523, 534, 524, + 478, 479, 480, 525, 542, 181, 467, 529, 485, 531, + 373, 374, 532, 375, 376, 533, 377, 378, 379, 496, + 497, 537, 538, 543, 544, 551, 566, 552, 181, 181, + 482, 578, 575, 181, 576, 579, 181, 601, 577, 591, + 584, 589, 181, 602, 604, 181, 605, -18, -19, 619, + 616, 622, 546, 237, 238, 617, 628, 623, 629, 631, + 350, 183, 351, 526, 573, 528, 588, 286, 530, 287, + 288, 199, 195, 391, 382, 535, 536, 63, 64, 44, + 107, 66, 67, 68, 69, 70, 71, 72, 130, 1, + 2, 97, 3, 4, 5, 570, 484, 0, 0, 0, + 0, 0, 0, 556, 557, 0, 561, 562, 0, 0, + 0, 565, 0, 0, 0, 0, 0, 0, 0, 73, + 0, -208, 571, 0, 0, 239, 240, 241, 242, 243, + 244, 245, 246, 247, 248, 249, 250, 251, 252, -69, + 1, 2, 0, 3, 4, 5, 0, 0, 585, 0, + 0, 6, 7, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 597, 598, 0, 132, 133, 0, 0, 63, + 64, 134, 8, 607, 0, 0, 9, 0, 0, 0, + 10, 1, 2, 0, 3, 4, 5, 135, 136, 137, + 0, 0, 0, 0, 0, 0, 620, 621, 0, 0, + 0, 624, 138, 139, 627, 0, 0, 0, 0, 0, + 630, 0, 0, 632, 0, 370, 0, 0, 0, 0, + 140, 0, 0, 0, 0, 0, 0, 74, 75, 0, + 0, 76, 0, 77, 194, 0, 0, 141, 142, 143, + 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, + 154, 155, 156, 157, 0, 0, 63, 64, 0, 107, + 208, 209, 210, 211, 212, 213, 72, 0, 1, 2, + 0, 3, 4, 5, 0, 0, 0, 0, 0, 158, + 159, 595, 596, 162, 163, 164, 165, 166, 167, 168, + 169, 170, 0, 171, 0, 172, 173, 174, 73, 373, + 374, 0, 375, 376, 0, 377, 378, 379, 132, 133, + 0, 0, 63, 64, 134, 0, 0, 0, 0, 0, + 0, 0, 0, 175, 1, 2, 0, 3, 4, 5, + 135, 136, 137, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 138, 139, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 111, + 0, 63, 64, 140, 107, 208, 209, 210, 211, 212, + 213, 72, 0, 1, 2, 0, 3, 4, 5, 0, + 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, + 151, 152, 153, 154, 155, 156, 157, 0, 0, 0, + 0, 0, 0, 73, 0, 0, 74, 75, 0, 0, + 76, 0, 77, 396, 0, 0, 0, 0, 0, 0, + 0, 0, 158, 159, 160, 161, 162, 163, 164, 165, + 166, 167, 168, 169, 170, 0, 171, 0, 172, 173, + 174, 0, 0, 0, 0, 0, 0, 0, 132, 133, + 0, 0, 63, 64, 134, 0, 0, 112, 0, 0, + 0, 0, 0, 0, 1, 2, 175, 3, 4, 5, + 135, 136, 137, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 138, 139, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 140, 0, 0, 0, 0, 0, 0, + 0, 74, 75, 0, 0, 76, 0, 77, 452, 0, + 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, + 151, 152, 153, 154, 155, 156, 157, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 374, 375, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 110, 0, 0, 0, - 376, 0, 0, 0, 0, 74, 75, 0, 0, 76, - 0, 77, 360, 0, 0, 0, 179, 180, 181, 182, - 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, - 193, 252, 253, 0, 0, 63, 64, 0, 106, 155, - 156, 157, 158, 159, 160, 72, 0, 1, 2, 0, - 3, 4, 5, 291, 292, 0, 0, 0, 254, 200, - 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, - 211, 0, 255, 0, 256, 257, 258, 73, 0, 0, - 0, 0, 0, 0, 368, 369, 0, 0, 63, 64, - 370, 0, 0, 111, 0, 0, 0, 0, 0, 0, - 1, 2, 377, 3, 4, 5, 371, 372, 373, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 374, 375, -207, 293, 294, 295, 296, 297, 298, - 299, 300, 301, 302, 303, 304, 305, 306, 0, 376, - 0, -69, 1, 2, 0, 3, 4, 5, 0, 0, - 0, 0, 0, 6, 7, 179, 180, 181, 182, 183, - 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, - 252, 253, 0, 0, 8, 0, 0, 0, 9, 0, - 0, 0, 10, 0, 74, 75, 0, 0, 76, 0, - 77, 428, 0, 0, 0, 0, 0, 254, 200, 201, - 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, - 0, 255, 0, 256, 257, 258, 63, 64, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, - 0, 3, 4, 5, 249, 0, 0, 0, 0, 0, - 0, 377, 0, 0, 0, 0, 0, 0, 0, 250, - 251, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 63, 64, 110, 150, 66, 67, 68, 69, 70, - 71, 72, 0, 1, 2, 0, 3, 4, 5, 0, - 0, 0, 0, 179, 180, 181, 182, 183, 184, 185, - 186, 187, 188, 189, 190, 191, 192, 193, 252, 253, - 0, 0, 0, 73, 0, 0, 63, 64, 0, 106, + 0, 0, 158, 159, 160, 161, 162, 163, 164, 165, + 166, 167, 168, 169, 170, 0, 171, 0, 172, 173, + 174, 63, 64, 0, 0, 0, 0, 0, 0, -207, + 0, 0, 0, 1, 2, 0, 3, 4, 5, 316, + 0, 0, 0, 0, 0, 0, 175, -69, 1, 2, + 0, 3, 4, 5, 317, 318, 0, 0, 0, 6, + 7, 0, 0, 0, 0, 0, 63, 64, 111, 203, 66, 67, 68, 69, 70, 71, 72, 0, 1, 2, - 0, 3, 4, 5, 0, 254, 200, 201, 202, 203, - 204, 205, 206, 207, 208, 209, 210, 211, 134, 255, - 0, 256, 257, 258, 0, 0, 0, 0, 73, 0, + 8, 3, 4, 5, 9, 0, 0, 0, 10, 141, + 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, + 152, 153, 154, 155, 156, 157, 0, 0, 73, 0, + 0, 0, 63, 64, 0, 107, 66, 67, 68, 69, + 70, 71, 72, 0, 1, 2, 0, 3, 4, 5, + 0, 158, 159, 160, 161, 162, 163, 164, 165, 166, + 167, 168, 169, 170, 187, 171, 0, 172, 173, 174, + 0, 0, 0, 0, 73, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 112, 0, 63, 64, + -67, 0, 319, 0, 0, 320, 0, 321, 0, 322, + 1, 2, 204, 3, 4, 5, 316, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 111, 0, 63, 64, -67, 0, 259, 0, 0, 260, - 0, 261, 0, 262, 1, 2, 151, 3, 4, 5, - 249, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 250, 251, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 110, - 74, 75, 0, 0, 76, 0, 77, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 179, - 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, - 190, 191, 192, 193, 252, 253, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 74, 75, 0, 0, 76, - 0, 77, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 254, 200, 201, 202, 203, 204, 205, 206, 207, - 208, 209, 210, 211, 0, 255, 0, 256, 257, 258, - 0, 0, 0, 0, 0, 0, 0, 0, 368, 369, - 0, 0, 0, 0, 370, 0, 111, 0, 0, 0, - 0, 0, 259, 0, 0, 260, 0, 261, 0, 262, - 371, 372, 373, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 374, 375, 0, 0, 0, + 0, 317, 318, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 111, 74, 75, 0, 0, + 76, 0, 77, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 141, 142, 143, 144, + 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, + 155, 156, 157, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 74, 75, 0, 0, 76, 0, 77, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 158, 159, + 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, + 170, 0, 171, 0, 172, 173, 174, 0, 0, 0, + 0, 0, 0, 0, 0, 132, 133, 0, 0, 0, + 0, 134, 0, 112, 0, 0, 0, 0, 0, 319, + 0, 0, 320, 0, 321, 0, 322, 135, 136, 137, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 376, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 179, - 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, - 190, 191, 192, 193, 252, 253, 0, 0, 0, 0, - 0, 0, 63, 64, 0, 106, 66, 67, 68, 69, - 70, 71, 72, 0, 1, 2, 0, 3, 4, 5, - 0, 254, 200, 201, 202, 203, 204, 205, 206, 207, - 208, 209, 210, 211, 337, 255, 0, 256, 257, 258, - 0, 0, 63, 64, 73, 106, 155, 156, 157, 158, - 159, 160, 72, 0, 1, 2, 0, 3, 4, 5, - 0, 0, 0, 63, 64, 377, 106, 66, 67, 68, - 69, 70, 71, 72, 0, 1, 2, 0, 3, 4, - 5, 0, 0, 0, 73, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 438, 0, 0, 0, 0, - 0, 0, 0, 63, 64, 73, 106, 66, 67, 68, - 69, 70, 71, 72, 0, 1, 2, 0, 3, 4, - 5, 63, 64, 0, 65, 66, 67, 68, 69, 70, - 71, 72, 0, 1, 2, 532, 3, 4, 5, 0, - 0, 0, 0, 0, 0, 73, 0, 0, 0, 0, - 0, 74, 75, 0, 0, 76, 0, 77, 0, 0, - 0, 63, 64, 73, 106, 155, 156, 157, 158, 159, - 160, 72, 0, 1, 2, 0, 3, 4, 5, 0, + 0, 0, 138, 139, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 74, 75, 0, 355, 76, 0, 77, 0, 0, + 140, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 141, 142, 143, + 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, + 154, 155, 156, 157, 0, 0, 0, 0, 0, 0, + 63, 64, 0, 107, 66, 67, 68, 69, 70, 71, + 72, 0, 1, 2, 0, 3, 4, 5, 0, 158, + 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, + 169, 170, 381, 171, 0, 172, 173, 174, 0, 0, + 63, 64, 73, 107, 66, 67, 68, 69, 70, 71, + 72, 0, 1, 2, 0, 3, 4, 5, 0, 0, + 0, 63, 64, 175, 107, 66, 67, 68, 69, 70, + 71, 72, 459, 1, 2, 0, 3, 4, 5, 0, + 0, 0, 73, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 548, 0, 0, 0, 0, 0, 0, + 0, 63, 64, 73, 65, 66, 67, 68, 69, 70, + 71, 72, 0, 1, 2, 0, 3, 4, 5, 63, + 64, 0, 107, 208, 209, 210, 211, 212, 213, 72, + 0, 1, 2, 0, 3, 4, 5, 0, 0, 0, 0, 0, 0, 73, 0, 0, 0, 0, 0, 0, - 0, 0, 74, 75, 0, 0, 76, 0, 77, 63, - 64, 0, 150, 66, 67, 68, 69, 70, 71, 72, + 74, 75, 0, 0, 76, 0, 77, 0, 0, 63, + 64, 73, 203, 66, 67, 68, 69, 70, 71, 72, 0, 1, 2, 0, 3, 4, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 74, 75, 0, 0, 76, 0, 77, 0, + 74, 75, 0, 0, 76, 0, 77, 0, 0, 0, 0, 73, 0, 0, 0, 0, 0, 0, 0, 0, - 74, 75, 0, 0, 76, 0, 77, 63, 64, 0, - 106, 66, 67, 68, 69, 70, 71, 72, 0, 1, - 2, 0, 3, 4, 5, 0, 0, 0, 0, 0, + 0, 74, 75, 0, 0, 76, 0, 77, 63, 64, + 0, 107, 66, 67, 68, 69, 70, 71, 72, 0, + 1, 2, 0, 3, 4, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 74, 75, 0, 0, 76, 0, 77, 63, 64, 73, - 271, 66, 67, 68, 69, 70, 71, 72, 0, 1, - 2, 0, 3, 4, 5, 63, 64, 0, 106, 155, - 156, 157, 158, 159, 160, 72, 0, 1, 2, 0, - 3, 4, 5, 0, 0, 0, 0, 0, 0, 73, + 0, 74, 75, 0, 0, 76, 0, 77, 0, 0, + 73, 0, 0, 0, 0, 0, 0, 0, 0, 74, + 75, 0, 0, 76, 0, 77, 63, 64, 0, 341, + 66, 67, 68, 69, 70, 71, 72, 0, 1, 2, + 0, 3, 4, 5, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 74, + 75, 0, 0, 76, 0, 77, 63, 64, 73, 107, + 208, 209, 210, 211, 212, 213, 72, 0, 1, 2, + 0, 3, 4, 5, 63, 64, 0, 107, 66, 67, + 68, 69, 70, 71, 558, 0, 1, 2, 0, 3, + 4, 5, 0, 0, 0, 0, 0, 0, 73, 0, 0, 0, 0, 0, 0, 0, 0, 0, 74, 75, - 0, 0, 76, 0, 77, 63, 64, 73, 106, 66, - 67, 68, 69, 70, 71, 538, 0, 1, 2, 0, - 3, 4, 5, 63, 64, 0, 106, 66, 67, 68, - 69, 70, 71, 593, 0, 1, 2, 0, 3, 4, - 5, 0, 0, 0, 0, 1, 0, 73, 3, 0, - 5, 0, 0, 0, 0, 0, 74, 75, 0, 0, - 76, 0, 77, 0, 0, 73, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 326, + 0, 0, 76, 0, 77, 0, 73, 63, 64, 0, + 107, 66, 67, 68, 69, 70, 71, 600, 0, 1, + 2, 0, 3, 4, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 73, 0, 0, 0, 0, 0, 0, 74, 75, 0, 0, 76, 0, 77, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 74, 75, 0, 0, 76, 0, - 358, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 327, 328, 0, 0, 0, 0, - 0, 0, 0, 0, 74, 75, 0, 0, 76, 170, - 77, 0, 329, 330, 0, 331, 332, 0, 333, 334, - 335, 0, 74, 75, 0, 0, 76, 0, 77, 171, - 172, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 173, 174, 175, 176, 177, 178, 179, 180, 181, - 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, - 192, 193, 194, 195, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 196, 197, 198, 0, 0, 199, - 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, - 210, 211, 212, 213, 214, 215, 216, 217, 218 + 0, 0, 0, 0, 0, 0, 0, 0, 264, 0, + 0, 0, 0, 0, 0, 0, 74, 75, 0, 0, + 76, 0, 394, 0, 0, 0, 0, 0, 265, 266, + 0, 0, 0, 0, 74, 75, 0, 0, 76, 0, + 77, 267, 268, 269, 270, 271, 272, 141, 142, 143, + 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, + 154, 155, 273, 274, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 74, 75, 0, + 0, 76, 0, 77, 275, 276, 277, 0, 0, 278, + 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, + 169, 170, 279, 280, 281, 282, 283, 284, 285 }; static const yytype_int16 yycheck[] = { - 0, 27, 175, 237, 163, 127, 4, 11, 0, 54, - 11, 21, 416, 417, 164, 586, 11, 17, 11, 29, - 309, 7, 8, 54, 54, 17, 28, 176, 120, 54, - 439, 34, 153, 19, 20, 606, 22, 23, 24, 52, - 154, 32, 33, 136, 137, 138, 260, 261, 141, 163, - 53, 77, 145, 146, 67, 54, 148, 54, 53, 153, - 53, 42, 43, 44, 45, 46, 47, 48, 54, 50, - 11, 154, 114, 115, 223, 101, 17, 153, 161, 105, - 3, 4, 5, 6, 488, 111, 154, 163, 238, 239, - 154, 117, 92, 198, 58, 163, 154, 19, 153, 163, - 22, 127, 24, 26, 27, 163, 151, 152, 213, 214, - 215, 216, 217, 139, 140, 34, 221, 143, 54, 18, - 151, 151, 154, 149, 533, 38, 151, 159, 159, 538, - 539, 161, 157, 7, 8, 0, 10, 11, 12, 13, - 14, 15, 16, 17, 358, 19, 20, 173, 22, 23, - 24, 54, 151, 163, 151, 159, 155, 279, 159, 20, - 162, 157, 23, 377, 162, 151, 153, 148, 149, 150, - 196, 197, 198, 199, 166, 49, 154, 54, 467, 54, - 153, 590, 591, 161, 593, 594, 212, 213, 214, 215, - 216, 217, 218, 219, 220, 221, 272, 113, 114, 275, - 276, 323, 278, 229, 42, 43, 44, 616, 617, 47, - 499, 46, 501, 48, 240, 151, 152, 136, 137, 138, - 325, 22, 141, 136, 137, 138, 145, 146, 141, 40, - 41, 21, 145, 146, 154, 311, 47, 22, 35, 159, - 37, 22, 53, 319, 320, 321, 22, 42, 151, 44, - 151, 154, 155, 279, 148, 149, 150, 491, 350, 351, - 352, 353, 354, 552, 290, 3, 4, 5, 6, 4, - 429, 363, 364, 365, 151, 4, 151, 382, 155, 154, - 155, 307, 156, 157, 0, 152, 160, 154, 162, 163, - 152, 396, 154, 398, 399, 400, 37, 323, 324, 325, - 83, 84, 18, 19, 20, 158, 22, 23, 24, 158, - 386, 387, 388, 155, 30, 31, 22, 151, 394, 4, - 152, 275, 276, 152, 278, 154, 154, 419, 420, 405, - 406, 161, 358, 4, 426, 51, 570, 152, 151, 55, - 574, 367, 9, 59, 9, 9, 7, 8, 56, 9, - 9, 9, 54, 429, 11, 161, 382, 311, 19, 20, - 152, 22, 23, 24, 151, 151, 320, 321, 22, 151, - 396, 397, 398, 399, 400, 451, 151, 453, 404, 151, - 456, 151, 151, 475, 476, 477, 478, 463, 464, 151, - 482, 483, 418, 151, 567, 154, 38, 502, 154, 154, - 505, 506, 507, 91, 92, 93, 94, 95, 96, 97, - 98, 99, 100, 4, 587, 154, 38, 154, 494, 495, - 154, 497, 498, 154, 516, 517, 151, 503, 151, 60, - 154, 157, 386, 387, 388, 154, 154, 154, 514, 154, - 394, 154, 468, 61, 62, 63, 64, 65, 66, 154, - 154, 405, 406, 154, 154, 154, 154, 154, 484, 38, - 152, 154, 22, 555, 490, 557, 558, 161, 17, 17, - 496, 547, 151, 154, 154, 4, 502, 154, 154, 505, - 506, 507, 154, 4, 154, 511, 154, 53, 151, 489, - 22, 4, 568, 569, 53, 161, 22, 451, 154, 453, - 152, 154, 456, 154, 154, 154, 154, 154, 584, 463, - 464, 154, 152, 7, 8, 152, 10, 11, 12, 13, - 14, 15, 16, 17, 154, 19, 20, 159, 22, 23, - 24, 157, 152, 152, 610, 611, 53, 17, 159, 615, - 494, 495, 618, 497, 498, 571, 152, 152, 624, 503, - 152, 627, 118, 119, 4, 49, 151, 147, 151, 22, - 514, 17, 562, 3, 4, 154, 17, 7, 8, 9, - 136, 137, 154, 139, 140, 17, 142, 143, 144, 19, - 20, 72, 22, 23, 24, 25, 26, 27, 17, 130, - 130, 130, 562, 547, 92, 534, 229, 252, 105, 111, - 40, 41, 240, 17, 89, 511, -1, 253, 56, 421, - -1, -1, -1, 53, 568, 569, 7, 8, 58, 10, - 11, 12, 13, 14, 15, 16, 17, -1, 19, 20, - 584, 22, 23, 24, 74, 75, 76, 77, 78, 79, - 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, - 90, -1, -1, -1, -1, -1, 610, 611, 49, -1, - -1, 615, 156, 157, 618, -1, 160, -1, 162, 163, - 624, -1, -1, 627, -1, -1, 116, 117, 118, 119, - 120, 121, 122, 123, 124, 125, 126, 127, 128, -1, - 130, -1, 132, 133, 134, -1, 136, 137, -1, 139, - 140, -1, 142, 143, 144, 3, 4, -1, -1, 7, - 8, 9, -1, -1, -1, -1, -1, -1, -1, -1, - 160, 19, 20, -1, 22, 23, 24, 25, 26, 27, - -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, 40, 41, -1, -1, -1, -1, -1, -1, - -1, -1, -1, -1, -1, -1, 54, -1, -1, -1, - 58, -1, -1, -1, -1, 156, 157, -1, -1, 160, - -1, 162, 163, -1, -1, -1, 74, 75, 76, 77, + 0, 27, 269, 128, 0, 304, 216, 28, 460, 21, + 54, 54, 353, 4, 11, 54, 11, 17, 121, 448, + 449, 17, 217, 52, 154, 91, 11, 270, 21, 593, + 11, 34, 20, 34, 58, 23, 29, 277, 67, 54, + 280, 281, 282, 283, 284, 155, 610, 290, 288, 154, + 160, 77, 53, 18, 7, 8, 68, 10, 11, 12, + 13, 14, 15, 16, 17, 131, 19, 20, 53, 22, + 23, 24, 53, 11, 155, 68, 102, 54, 507, 17, + 106, 155, 54, 164, 152, 155, 112, 319, 320, 321, + 164, 155, 118, 93, 164, 154, 49, 549, 201, 46, + 164, 48, 128, 0, 54, 155, 558, 559, 152, 152, + 305, 306, 162, 152, 158, 7, 8, 160, 10, 11, + 12, 13, 14, 15, 16, 17, 154, 19, 20, 369, + 22, 23, 24, 54, 137, 138, 139, 152, 54, 142, + 206, 54, 163, 146, 147, 597, 598, 162, 600, 601, + 216, 254, 255, 256, 257, 258, 497, 49, 261, 262, + 263, 22, 394, 160, 154, 160, 192, 193, 620, 621, + 196, 164, 163, 22, 414, 152, 202, 22, 155, 156, + 152, 7, 8, 155, 156, 526, 37, 528, 428, 158, + 430, 431, 432, 19, 20, 155, 22, 23, 24, 35, + 160, 37, 152, 22, 157, 158, 156, 160, 161, 4, + 163, 510, 155, 19, 32, 33, 22, 19, 24, 162, + 22, 152, 24, 219, 349, 328, 329, 467, 54, 4, + 571, 152, 335, 131, 68, 156, 152, 153, 156, 152, + 153, 267, 367, 453, 149, 150, 151, 53, 159, 275, + 276, 277, 278, 279, 280, 281, 282, 283, 284, 285, + 286, 287, 288, 115, 116, 157, 158, 114, 115, 161, + 296, 163, 164, 42, 43, 44, 342, 159, 47, 345, + 346, 307, 348, 582, 42, 4, 44, 586, 60, 355, + 38, 531, 532, 533, 153, 152, 155, 363, 364, 365, + 83, 84, 405, 406, 407, 408, 152, 410, 411, 40, + 41, 152, 579, 119, 120, 152, 47, 3, 4, 5, + 6, 152, 53, 349, 350, 351, 152, 594, 153, 152, + 155, 137, 138, 22, 140, 141, 152, 143, 144, 145, + 152, 367, 368, 369, 155, 153, 3, 4, 5, 6, + 4, 152, 418, 419, 420, 153, 153, 155, 162, 9, + 426, 464, 465, 9, 9, 9, 9, 9, 394, 26, + 27, 437, 438, 54, 400, 22, 152, 42, 43, 44, + 45, 46, 47, 48, 152, 50, 412, 453, 414, 137, + 138, 139, 56, 11, 142, 162, 153, 22, 146, 147, + 152, 155, 428, 429, 430, 431, 432, 38, 155, 155, + 436, 514, 155, 516, 517, 481, 155, 483, 7, 8, + 486, 155, 155, 155, 450, 155, 155, 493, 494, 155, + 19, 20, 155, 22, 23, 24, 38, 155, 155, 4, + 38, 467, 155, 22, 342, 155, 53, 345, 346, 155, + 348, 155, 155, 158, 155, 521, 522, 355, 524, 525, + 137, 138, 139, 529, 155, 142, 364, 365, 155, 146, + 147, 155, 498, 155, 540, 61, 62, 63, 64, 65, + 66, 153, 162, 509, 149, 150, 151, 92, 93, 94, + 95, 96, 97, 98, 99, 100, 101, 523, 153, 155, + 566, 17, 155, 155, 153, 531, 532, 533, 508, 17, + 4, 537, 119, 120, 580, 581, 153, 152, 4, 155, + 418, 419, 420, 155, 162, 591, 155, 155, 426, 155, + 137, 138, 155, 140, 141, 155, 143, 144, 145, 437, + 438, 152, 155, 22, 4, 153, 155, 153, 614, 615, + 53, 155, 153, 619, 153, 158, 622, 583, 153, 17, + 160, 53, 628, 160, 4, 631, 148, 152, 152, 17, + 22, 17, 572, 26, 27, 155, 17, 155, 73, 17, + 273, 93, 274, 481, 550, 483, 572, 183, 486, 183, + 183, 112, 106, 307, 296, 493, 494, 7, 8, 17, + 10, 11, 12, 13, 14, 15, 16, 17, 89, 19, + 20, 56, 22, 23, 24, 537, 425, -1, -1, -1, + -1, -1, -1, 521, 522, -1, 524, 525, -1, -1, + -1, 529, -1, -1, -1, -1, -1, -1, -1, 49, + -1, 0, 540, -1, -1, 98, 99, 100, 101, 102, + 103, 104, 105, 106, 107, 108, 109, 110, 111, 18, + 19, 20, -1, 22, 23, 24, -1, -1, 566, -1, + -1, 30, 31, -1, -1, -1, -1, -1, -1, -1, + -1, -1, 580, 581, -1, 3, 4, -1, -1, 7, + 8, 9, 51, 591, -1, -1, 55, -1, -1, -1, + 59, 19, 20, -1, 22, 23, 24, 25, 26, 27, + -1, -1, -1, -1, -1, -1, 614, 615, -1, -1, + -1, 619, 40, 41, 622, -1, -1, -1, -1, -1, + 628, -1, -1, 631, -1, 53, -1, -1, -1, -1, + 58, -1, -1, -1, -1, -1, -1, 157, 158, -1, + -1, 161, -1, 163, 164, -1, -1, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, - 88, 89, 90, -1, -1, 7, 8, -1, 10, 11, - 12, 13, 14, 15, 16, 17, -1, 19, 20, -1, - 22, 23, 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-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, -1, -1, 111, 112, 113, -1, -1, 116, - 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, - 127, 128, 129, 130, 131, 132, 133, 134, 135 + -1, -1, -1, -1, -1, -1, -1, -1, 36, -1, + -1, -1, -1, -1, -1, -1, 157, 158, -1, -1, + 161, -1, 163, -1, -1, -1, -1, -1, 56, 57, + -1, -1, -1, -1, 157, 158, -1, -1, 161, -1, + 163, 69, 70, 71, 72, 73, 74, 75, 76, 77, + 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, + 88, 89, 90, 91, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, 157, 158, -1, + -1, 161, -1, 163, 112, 113, 114, -1, -1, 117, + 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, + 128, 129, 130, 131, 132, 133, 134, 135, 136 }; /* YYSTOS[STATE-NUM] -- The (internal number of the) accessing @@ -2598,68 +2614,69 @@ static const yytype_uint8 yystos[] = { 0, 19, 20, 22, 23, 24, 30, 31, 51, 55, - 59, 173, 176, 177, 178, 179, 211, 212, 213, 215, - 214, 52, 67, 220, 153, 58, 153, 18, 153, 42, - 43, 44, 45, 46, 47, 48, 50, 148, 149, 150, - 180, 181, 182, 0, 213, 46, 48, 183, 230, 42, - 43, 44, 47, 184, 227, 229, 237, 153, 153, 157, - 221, 22, 219, 7, 8, 10, 11, 12, 13, 14, - 15, 16, 17, 49, 156, 157, 160, 162, 173, 177, - 198, 199, 233, 182, 182, 35, 37, 209, 182, 182, - 21, 238, 239, 29, 163, 228, 238, 22, 22, 22, - 222, 151, 4, 4, 4, 162, 10, 163, 199, 204, - 54, 151, 175, 209, 209, 42, 44, 185, 32, 33, - 208, 61, 62, 63, 64, 65, 66, 186, 225, 225, - 176, 242, 154, 159, 39, 199, 200, 202, 203, 158, - 158, 163, 204, 154, 163, 151, 203, 155, 208, 208, - 10, 122, 199, 201, 210, 11, 12, 13, 14, 15, - 16, 171, 172, 199, 205, 4, 201, 28, 162, 226, - 36, 56, 57, 68, 69, 70, 71, 72, 73, 74, - 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, - 85, 86, 87, 88, 89, 90, 111, 112, 113, 116, - 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, - 127, 128, 129, 130, 131, 132, 133, 134, 135, 166, - 167, 168, 240, 246, 247, 248, 249, 22, 188, 154, - 152, 199, 199, 161, 163, 199, 4, 152, 205, 199, - 151, 233, 26, 27, 3, 4, 5, 6, 9, 25, - 40, 41, 89, 90, 116, 130, 132, 133, 134, 157, - 160, 162, 164, 166, 167, 168, 206, 233, 175, 177, - 56, 10, 199, 235, 236, 11, 17, 11, 171, 186, - 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, - 169, 26, 27, 97, 98, 99, 100, 101, 102, 103, - 104, 105, 106, 107, 108, 109, 110, 170, 199, 199, - 235, 199, 199, 243, 235, 235, 235, 235, 235, 199, - 199, 199, 235, 186, 114, 115, 53, 118, 119, 136, - 137, 139, 140, 142, 143, 144, 187, 39, 200, 190, - 159, 161, 161, 152, 190, 175, 175, 210, 169, 170, - 151, 151, 151, 151, 151, 159, 205, 207, 162, 207, - 163, 207, 22, 151, 151, 151, 216, 151, 3, 4, - 9, 25, 26, 27, 40, 41, 58, 160, 206, 232, - 233, 234, 154, 234, 234, 234, 201, 199, 199, 154, - 193, 154, 193, 234, 157, 154, 154, 154, 154, 154, - 154, 233, 234, 234, 38, 201, 199, 235, 4, 136, - 137, 138, 141, 145, 146, 189, 217, 218, 38, 151, - 151, 205, 205, 205, 205, 205, 154, 159, 163, 199, - 207, 161, 163, 205, 205, 205, 154, 196, 39, 199, - 223, 224, 60, 231, 207, 235, 154, 154, 234, 234, - 234, 11, 53, 11, 245, 234, 157, 235, 199, 235, - 235, 235, 154, 154, 154, 199, 234, 234, 154, 196, - 196, 199, 205, 205, 245, 154, 154, 154, 154, 205, - 161, 163, 154, 154, 38, 34, 53, 194, 197, 188, - 154, 152, 22, 161, 17, 17, 151, 154, 154, 234, - 4, 234, 154, 154, 234, 154, 154, 154, 4, 234, - 234, 151, 154, 193, 199, 152, 154, 154, 152, 205, - 205, 205, 205, 161, 205, 205, 199, 22, 4, 196, - 173, 174, 39, 199, 190, 154, 234, 234, 17, 199, - 244, 234, 234, 193, 193, 235, 234, 154, 235, 235, - 235, 244, 234, 205, 205, 154, 152, 154, 154, 152, - 152, 152, 188, 194, 195, 22, 154, 157, 188, 188, - 152, 154, 159, 234, 152, 193, 152, 152, 205, 205, - 205, 174, 53, 192, 17, 159, 171, 241, 118, 119, - 234, 234, 190, 17, 199, 159, 190, 152, 152, 152, - 4, 147, 191, 234, 232, 159, 171, 188, 188, 38, - 188, 188, 22, 154, 232, 17, 234, 234, 17, 154, - 234, 188, 188, 234, 17, 72, 234, 17, 234 + 59, 174, 177, 178, 179, 180, 212, 213, 214, 216, + 215, 52, 67, 221, 154, 58, 154, 18, 154, 42, + 43, 44, 45, 46, 47, 48, 50, 149, 150, 151, + 181, 182, 183, 0, 214, 46, 48, 184, 231, 42, + 43, 44, 47, 185, 228, 230, 238, 154, 154, 158, + 222, 22, 220, 7, 8, 10, 11, 12, 13, 14, + 15, 16, 17, 49, 157, 158, 161, 163, 174, 178, + 199, 200, 234, 183, 183, 35, 37, 210, 183, 183, + 21, 68, 239, 240, 29, 164, 229, 239, 22, 22, + 22, 223, 152, 4, 4, 4, 163, 10, 164, 200, + 205, 54, 152, 176, 210, 210, 42, 44, 186, 32, + 33, 209, 61, 62, 63, 64, 65, 66, 187, 226, + 226, 68, 3, 4, 9, 25, 26, 27, 40, 41, + 58, 75, 76, 77, 78, 79, 80, 81, 82, 83, + 84, 85, 86, 87, 88, 89, 90, 91, 117, 118, + 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, + 129, 131, 133, 134, 135, 161, 167, 168, 169, 207, + 233, 234, 235, 177, 243, 155, 160, 39, 200, 201, + 203, 204, 159, 159, 164, 205, 155, 164, 152, 204, + 156, 209, 209, 10, 123, 200, 202, 211, 11, 12, + 13, 14, 15, 16, 172, 173, 200, 206, 4, 202, + 28, 163, 227, 235, 60, 232, 92, 93, 94, 95, + 96, 97, 98, 99, 100, 101, 170, 26, 27, 98, + 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, + 109, 110, 111, 171, 152, 152, 152, 152, 152, 206, + 208, 152, 152, 152, 36, 56, 57, 69, 70, 71, + 72, 73, 74, 90, 91, 112, 113, 114, 117, 130, + 131, 132, 133, 134, 135, 136, 167, 168, 169, 241, + 247, 248, 249, 250, 22, 189, 155, 153, 200, 200, + 162, 164, 200, 4, 153, 206, 200, 152, 234, 26, + 27, 3, 4, 5, 6, 9, 25, 40, 41, 158, + 161, 163, 165, 207, 234, 176, 178, 22, 152, 152, + 206, 206, 206, 206, 206, 155, 162, 206, 206, 206, + 56, 10, 200, 236, 237, 11, 17, 11, 172, 187, + 170, 171, 200, 200, 236, 200, 200, 244, 236, 236, + 236, 236, 236, 200, 200, 200, 236, 187, 115, 116, + 53, 119, 120, 137, 138, 140, 141, 143, 144, 145, + 188, 39, 201, 191, 160, 162, 162, 153, 191, 176, + 176, 211, 160, 208, 163, 208, 164, 208, 22, 217, + 152, 155, 206, 206, 246, 155, 155, 155, 155, 206, + 155, 155, 38, 235, 155, 235, 235, 235, 202, 200, + 200, 155, 194, 155, 194, 235, 158, 155, 155, 155, + 155, 155, 155, 234, 235, 235, 38, 202, 200, 236, + 4, 137, 138, 139, 142, 146, 147, 190, 218, 219, + 38, 160, 164, 200, 208, 162, 164, 155, 197, 39, + 200, 224, 225, 22, 155, 155, 153, 155, 206, 206, + 206, 206, 206, 206, 200, 236, 155, 155, 235, 235, + 235, 11, 53, 11, 246, 235, 158, 236, 200, 236, + 236, 236, 155, 155, 155, 200, 235, 235, 155, 197, + 197, 200, 162, 164, 34, 53, 195, 198, 189, 155, + 153, 206, 206, 236, 155, 153, 155, 155, 153, 153, + 153, 17, 17, 152, 155, 155, 235, 4, 235, 155, + 235, 155, 155, 155, 4, 235, 235, 152, 155, 194, + 200, 153, 162, 22, 4, 197, 174, 175, 39, 200, + 191, 153, 153, 206, 206, 206, 235, 235, 17, 200, + 245, 235, 235, 194, 194, 235, 155, 236, 236, 236, + 245, 235, 189, 195, 196, 153, 153, 153, 155, 158, + 189, 189, 153, 155, 160, 235, 153, 194, 175, 53, + 193, 17, 160, 172, 242, 119, 120, 235, 235, 191, + 17, 200, 160, 191, 4, 148, 192, 235, 233, 160, + 172, 189, 189, 38, 189, 189, 22, 155, 233, 17, + 235, 235, 17, 155, 235, 189, 189, 235, 17, 73, + 235, 17, 235 }; #define yyerrok (yyerrstatus = 0) @@ -3474,152 +3491,152 @@ switch (yyn) { case 29: -#line 1121 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1119 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.IPredicate) = ICmpInst::ICMP_EQ; ;} break; case 30: -#line 1121 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1119 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.IPredicate) = ICmpInst::ICMP_NE; ;} break; case 31: -#line 1122 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1120 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.IPredicate) = ICmpInst::ICMP_SLT; ;} break; case 32: -#line 1122 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1120 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.IPredicate) = ICmpInst::ICMP_SGT; ;} break; case 33: -#line 1123 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1121 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.IPredicate) = ICmpInst::ICMP_SLE; ;} break; case 34: -#line 1123 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1121 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.IPredicate) = ICmpInst::ICMP_SGE; ;} break; case 35: -#line 1124 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1122 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.IPredicate) = ICmpInst::ICMP_ULT; ;} break; case 36: -#line 1124 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1122 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.IPredicate) = ICmpInst::ICMP_UGT; ;} break; case 37: -#line 1125 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1123 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.IPredicate) = ICmpInst::ICMP_ULE; ;} break; case 38: -#line 1125 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1123 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.IPredicate) = ICmpInst::ICMP_UGE; ;} break; case 39: -#line 1129 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1127 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.FPredicate) = FCmpInst::FCMP_OEQ; ;} break; case 40: -#line 1129 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1127 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.FPredicate) = FCmpInst::FCMP_ONE; ;} break; case 41: -#line 1130 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1128 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.FPredicate) = FCmpInst::FCMP_OLT; ;} break; case 42: -#line 1130 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1128 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.FPredicate) = FCmpInst::FCMP_OGT; ;} break; case 43: -#line 1131 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1129 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.FPredicate) = FCmpInst::FCMP_OLE; ;} break; case 44: -#line 1131 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1129 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.FPredicate) = FCmpInst::FCMP_OGE; ;} break; case 45: -#line 1132 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1130 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.FPredicate) = FCmpInst::FCMP_ORD; ;} break; case 46: -#line 1132 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1130 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.FPredicate) = FCmpInst::FCMP_UNO; ;} break; case 47: -#line 1133 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1131 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.FPredicate) = FCmpInst::FCMP_UEQ; ;} break; case 48: -#line 1133 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1131 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.FPredicate) = FCmpInst::FCMP_UNE; ;} break; case 49: -#line 1134 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1132 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.FPredicate) = FCmpInst::FCMP_ULT; ;} break; case 50: -#line 1134 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1132 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.FPredicate) = FCmpInst::FCMP_UGT; ;} break; case 51: -#line 1135 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1133 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.FPredicate) = FCmpInst::FCMP_ULE; ;} break; case 52: -#line 1135 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1133 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.FPredicate) = FCmpInst::FCMP_UGE; ;} break; case 53: -#line 1136 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1134 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.FPredicate) = FCmpInst::FCMP_TRUE; ;} break; case 54: -#line 1137 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1135 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.FPredicate) = FCmpInst::FCMP_FALSE; ;} break; case 65: -#line 1146 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1144 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.StrVal) = 0; ;} break; case 66: -#line 1148 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1146 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.UIntVal)=(yyvsp[(3) - (4)].UInt64Val); ;} break; case 67: -#line 1149 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1147 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.UIntVal)=0; ;} break; case 68: -#line 1153 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1151 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.StrVal) = (yyvsp[(1) - (2)].StrVal); CHECK_FOR_ERROR @@ -3627,7 +3644,7 @@ break; case 69: -#line 1157 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1155 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.StrVal) = 0; CHECK_FOR_ERROR @@ -3635,7 +3652,7 @@ break; case 73: -#line 1165 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1163 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.StrVal) = 0; CHECK_FOR_ERROR @@ -3643,7 +3660,7 @@ break; case 74: -#line 1170 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1168 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.StrVal) = (yyvsp[(1) - (2)].StrVal); CHECK_FOR_ERROR @@ -3651,152 +3668,152 @@ break; case 75: -#line 1176 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1174 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.Linkage) = GlobalValue::InternalLinkage; ;} break; case 76: -#line 1177 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1175 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.Linkage) = GlobalValue::WeakLinkage; ;} break; case 77: -#line 1178 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1176 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.Linkage) = GlobalValue::LinkOnceLinkage; ;} break; case 78: -#line 1179 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1177 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.Linkage) = GlobalValue::AppendingLinkage; ;} break; case 79: -#line 1180 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1178 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.Linkage) = GlobalValue::DLLExportLinkage; ;} break; case 80: -#line 1184 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1182 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.Linkage) = GlobalValue::DLLImportLinkage; ;} break; case 81: -#line 1185 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1183 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.Linkage) = GlobalValue::ExternalWeakLinkage; ;} break; case 82: -#line 1186 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1184 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.Linkage) = GlobalValue::ExternalLinkage; ;} break; case 83: -#line 1190 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1188 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.Visibility) = GlobalValue::DefaultVisibility; ;} break; case 84: -#line 1191 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1189 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.Visibility) = GlobalValue::DefaultVisibility; ;} break; case 85: -#line 1192 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1190 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.Visibility) = GlobalValue::HiddenVisibility; ;} break; case 86: -#line 1193 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1191 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.Visibility) = GlobalValue::ProtectedVisibility; ;} break; case 87: -#line 1197 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1195 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.Linkage) = GlobalValue::ExternalLinkage; ;} break; case 88: -#line 1198 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1196 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.Linkage) = GlobalValue::DLLImportLinkage; ;} break; case 89: -#line 1199 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1197 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.Linkage) = GlobalValue::ExternalWeakLinkage; ;} break; case 90: -#line 1203 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1201 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.Linkage) = GlobalValue::ExternalLinkage; ;} break; case 91: -#line 1204 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1202 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.Linkage) = GlobalValue::InternalLinkage; ;} break; case 92: -#line 1205 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1203 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.Linkage) = GlobalValue::LinkOnceLinkage; ;} break; case 93: -#line 1206 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1204 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.Linkage) = GlobalValue::WeakLinkage; ;} break; case 94: -#line 1207 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1205 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.Linkage) = GlobalValue::DLLExportLinkage; ;} break; case 95: -#line 1211 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1209 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.Linkage) = GlobalValue::ExternalLinkage; ;} break; case 96: -#line 1212 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1210 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.Linkage) = GlobalValue::WeakLinkage; ;} break; case 97: -#line 1213 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1211 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.Linkage) = GlobalValue::InternalLinkage; ;} break; case 98: -#line 1216 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1214 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.UIntVal) = CallingConv::C; ;} break; case 99: -#line 1217 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1215 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.UIntVal) = CallingConv::C; ;} break; case 100: -#line 1218 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1216 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.UIntVal) = CallingConv::Fast; ;} break; case 101: -#line 1219 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1217 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.UIntVal) = CallingConv::Cold; ;} break; case 102: -#line 1220 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1218 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.UIntVal) = CallingConv::X86_StdCall; ;} break; case 103: -#line 1221 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1219 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.UIntVal) = CallingConv::X86_FastCall; ;} break; case 104: -#line 1222 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1220 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { if ((unsigned)(yyvsp[(2) - (2)].UInt64Val) != (yyvsp[(2) - (2)].UInt64Val)) GEN_ERROR("Calling conv too large"); @@ -3806,129 +3823,129 @@ break; case 105: -#line 1229 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1227 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.ParamAttrs) = ParamAttr::ZExt; ;} break; case 106: -#line 1230 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1228 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.ParamAttrs) = ParamAttr::ZExt; ;} break; case 107: -#line 1231 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1229 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.ParamAttrs) = ParamAttr::SExt; ;} break; case 108: -#line 1232 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1230 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.ParamAttrs) = ParamAttr::SExt; ;} break; case 109: -#line 1233 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1231 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.ParamAttrs) = ParamAttr::InReg; ;} break; case 110: -#line 1234 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1232 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.ParamAttrs) = ParamAttr::StructRet; ;} break; case 111: -#line 1235 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1233 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.ParamAttrs) = ParamAttr::NoAlias; ;} break; case 112: -#line 1236 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1234 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.ParamAttrs) = ParamAttr::ByVal; ;} break; case 113: -#line 1237 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1235 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.ParamAttrs) = ParamAttr::Nest; ;} break; case 114: -#line 1238 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1236 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.ParamAttrs) = ParamAttr::constructAlignmentFromInt((yyvsp[(2) - (2)].UInt64Val)); ;} break; case 115: -#line 1242 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1240 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.ParamAttrs) = ParamAttr::None; ;} break; case 116: -#line 1243 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1241 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.ParamAttrs) = (yyvsp[(1) - (2)].ParamAttrs) | (yyvsp[(2) - (2)].ParamAttrs); ;} break; case 117: -#line 1248 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1246 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.ParamAttrs) = ParamAttr::NoReturn; ;} break; case 118: -#line 1249 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1247 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.ParamAttrs) = ParamAttr::NoUnwind; ;} break; case 119: -#line 1250 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1248 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.ParamAttrs) = ParamAttr::ZExt; ;} break; case 120: -#line 1251 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1249 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.ParamAttrs) = ParamAttr::SExt; ;} break; case 121: -#line 1252 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1250 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.ParamAttrs) = ParamAttr::ReadNone; ;} break; case 122: -#line 1253 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1251 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.ParamAttrs) = ParamAttr::ReadOnly; ;} break; case 123: -#line 1256 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1254 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.ParamAttrs) = ParamAttr::None; ;} break; case 124: -#line 1257 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1255 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.ParamAttrs) = (yyvsp[(1) - (2)].ParamAttrs) | (yyvsp[(2) - (2)].ParamAttrs); ;} break; case 125: -#line 1262 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1260 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.StrVal) = 0; ;} break; case 126: -#line 1263 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1261 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.StrVal) = (yyvsp[(2) - (2)].StrVal); ;} break; case 127: -#line 1270 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1268 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.UIntVal) = 0; ;} break; case 128: -#line 1271 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1269 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.UIntVal) = (yyvsp[(2) - (2)].UInt64Val); if ((yyval.UIntVal) != 0 && !isPowerOf2_32((yyval.UIntVal))) @@ -3938,12 +3955,12 @@ break; case 129: -#line 1277 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1275 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.UIntVal) = 0; ;} break; case 130: -#line 1278 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1276 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.UIntVal) = (yyvsp[(3) - (3)].UInt64Val); if ((yyval.UIntVal) != 0 && !isPowerOf2_32((yyval.UIntVal))) @@ -3953,7 +3970,7 @@ break; case 131: -#line 1287 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1285 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { for (unsigned i = 0, e = (yyvsp[(2) - (2)].StrVal)->length(); i != e; ++i) if ((*(yyvsp[(2) - (2)].StrVal))[i] == '"' || (*(yyvsp[(2) - (2)].StrVal))[i] == '\\') @@ -3964,27 +3981,27 @@ break; case 132: -#line 1295 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1293 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.StrVal) = 0; ;} break; case 133: -#line 1296 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1294 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.StrVal) = (yyvsp[(1) - (1)].StrVal); ;} break; case 134: -#line 1301 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1299 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" {;} break; case 135: -#line 1302 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1300 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" {;} break; case 136: -#line 1303 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1301 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { CurGV->setSection(*(yyvsp[(1) - (1)].StrVal)); delete (yyvsp[(1) - (1)].StrVal); @@ -3993,7 +4010,7 @@ break; case 137: -#line 1308 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1306 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { if ((yyvsp[(2) - (2)].UInt64Val) != 0 && !isPowerOf2_32((yyvsp[(2) - (2)].UInt64Val))) GEN_ERROR("Alignment must be a power of two"); @@ -4003,7 +4020,7 @@ break; case 145: -#line 1324 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1322 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.TypeVal) = new PATypeHolder(OpaqueType::get()); CHECK_FOR_ERROR @@ -4011,7 +4028,7 @@ break; case 146: -#line 1328 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1326 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.TypeVal) = new PATypeHolder((yyvsp[(1) - (1)].PrimType)); CHECK_FOR_ERROR @@ -4019,7 +4036,7 @@ break; case 147: -#line 1332 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1330 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { // Pointer type? if (*(yyvsp[(1) - (3)].TypeVal) == Type::LabelTy) GEN_ERROR("Cannot form a pointer to a basic block"); @@ -4030,7 +4047,7 @@ break; case 148: -#line 1339 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1337 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { // Named types are also simple types... const Type* tmp = getTypeVal((yyvsp[(1) - (1)].ValIDVal)); CHECK_FOR_ERROR @@ -4039,7 +4056,7 @@ break; case 149: -#line 1344 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1342 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { // Type UpReference if ((yyvsp[(2) - (2)].UInt64Val) > (uint64_t)~0U) GEN_ERROR("Value out of range"); OpaqueType *OT = OpaqueType::get(); // Use temporary placeholder @@ -4051,7 +4068,7 @@ break; case 150: -#line 1352 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1350 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { // Allow but ignore attributes on function types; this permits auto-upgrade. // FIXME: remove in LLVM 3.0. @@ -4085,7 +4102,7 @@ break; case 151: -#line 1382 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1380 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { // Allow but ignore attributes on function types; this permits auto-upgrade. // FIXME: remove in LLVM 3.0. @@ -4113,7 +4130,7 @@ break; case 152: -#line 1407 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1405 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { // Sized array type? (yyval.TypeVal) = new PATypeHolder(HandleUpRefs(ArrayType::get(*(yyvsp[(4) - (5)].TypeVal), (unsigned)(yyvsp[(2) - (5)].UInt64Val)))); delete (yyvsp[(4) - (5)].TypeVal); @@ -4122,7 +4139,7 @@ break; case 153: -#line 1412 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1410 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { // Vector type? const llvm::Type* ElemTy = (yyvsp[(4) - (5)].TypeVal)->get(); if ((unsigned)(yyvsp[(2) - (5)].UInt64Val) != (yyvsp[(2) - (5)].UInt64Val)) @@ -4136,7 +4153,7 @@ break; case 154: -#line 1422 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1420 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { // Structure type? std::vector Elements; for (std::list::iterator I = (yyvsp[(2) - (3)].TypeList)->begin(), @@ -4150,7 +4167,7 @@ break; case 155: -#line 1432 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1430 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { // Empty structure type? (yyval.TypeVal) = new PATypeHolder(StructType::get(std::vector())); CHECK_FOR_ERROR @@ -4158,7 +4175,7 @@ break; case 156: -#line 1436 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1434 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { std::vector Elements; for (std::list::iterator I = (yyvsp[(3) - (5)].TypeList)->begin(), @@ -4172,7 +4189,7 @@ break; case 157: -#line 1446 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1444 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { // Empty structure type? (yyval.TypeVal) = new PATypeHolder(StructType::get(std::vector(), true)); CHECK_FOR_ERROR @@ -4180,7 +4197,7 @@ break; case 158: -#line 1453 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1451 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { // Allow but ignore attributes on function types; this permits auto-upgrade. // FIXME: remove in LLVM 3.0. @@ -4190,7 +4207,7 @@ break; case 159: -#line 1462 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1460 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(1) - (1)].TypeVal))->getDescription()); @@ -4201,14 +4218,14 @@ break; case 160: -#line 1469 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1467 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.TypeVal) = new PATypeHolder(Type::VoidTy); ;} break; case 161: -#line 1474 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1472 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.TypeWithAttrsList) = new TypeWithAttrsList(); (yyval.TypeWithAttrsList)->push_back((yyvsp[(1) - (1)].TypeWithAttrs)); @@ -4217,7 +4234,7 @@ break; case 162: -#line 1479 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1477 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { ((yyval.TypeWithAttrsList)=(yyvsp[(1) - (3)].TypeWithAttrsList))->push_back((yyvsp[(3) - (3)].TypeWithAttrs)); CHECK_FOR_ERROR @@ -4225,7 +4242,7 @@ break; case 164: -#line 1487 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1485 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.TypeWithAttrsList)=(yyvsp[(1) - (3)].TypeWithAttrsList); TypeWithAttrs TWA; TWA.Attrs = ParamAttr::None; @@ -4236,7 +4253,7 @@ break; case 165: -#line 1494 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1492 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.TypeWithAttrsList) = new TypeWithAttrsList; TypeWithAttrs TWA; TWA.Attrs = ParamAttr::None; @@ -4247,7 +4264,7 @@ break; case 166: -#line 1501 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1499 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.TypeWithAttrsList) = new TypeWithAttrsList(); CHECK_FOR_ERROR @@ -4255,7 +4272,7 @@ break; case 167: -#line 1509 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1507 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.TypeList) = new std::list(); (yyval.TypeList)->push_back(*(yyvsp[(1) - (1)].TypeVal)); @@ -4265,7 +4282,7 @@ break; case 168: -#line 1515 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1513 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { ((yyval.TypeList)=(yyvsp[(1) - (3)].TypeList))->push_back(*(yyvsp[(3) - (3)].TypeVal)); delete (yyvsp[(3) - (3)].TypeVal); @@ -4274,7 +4291,7 @@ break; case 169: -#line 1527 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1525 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { // Nonempty unsized arr if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(1) - (4)].TypeVal))->getDescription()); @@ -4306,7 +4323,7 @@ break; case 170: -#line 1555 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1553 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(1) - (3)].TypeVal))->getDescription()); @@ -4326,7 +4343,7 @@ break; case 171: -#line 1571 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1569 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(1) - (3)].TypeVal))->getDescription()); @@ -4357,7 +4374,7 @@ break; case 172: -#line 1598 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1596 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { // Nonempty unsized arr if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(1) - (4)].TypeVal))->getDescription()); @@ -4389,7 +4406,7 @@ break; case 173: -#line 1626 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1624 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { const StructType *STy = dyn_cast((yyvsp[(1) - (4)].TypeVal)->get()); if (STy == 0) @@ -4419,7 +4436,7 @@ break; case 174: -#line 1652 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1650 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(1) - (3)].TypeVal))->getDescription()); @@ -4443,7 +4460,7 @@ break; case 175: -#line 1672 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1670 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { const StructType *STy = dyn_cast((yyvsp[(1) - (6)].TypeVal)->get()); if (STy == 0) @@ -4473,7 +4490,7 @@ break; case 176: -#line 1698 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1696 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(1) - (5)].TypeVal))->getDescription()); @@ -4497,7 +4514,7 @@ break; case 177: -#line 1718 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1716 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(1) - (2)].TypeVal))->getDescription()); @@ -4513,7 +4530,7 @@ break; case 178: -#line 1730 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1728 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(1) - (2)].TypeVal))->getDescription()); @@ -4524,7 +4541,7 @@ break; case 179: -#line 1737 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1735 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(1) - (2)].TypeVal))->getDescription()); @@ -4594,7 +4611,7 @@ break; case 180: -#line 1803 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1801 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(1) - (2)].TypeVal))->getDescription()); @@ -4608,7 +4625,7 @@ break; case 181: -#line 1813 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1811 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(1) - (2)].TypeVal))->getDescription()); @@ -4622,7 +4639,7 @@ break; case 182: -#line 1823 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1821 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { // integral constants if (!ConstantInt::isValueValidForType((yyvsp[(1) - (2)].PrimType), (yyvsp[(2) - (2)].SInt64Val))) GEN_ERROR("Constant value doesn't fit in type"); @@ -4632,7 +4649,7 @@ break; case 183: -#line 1829 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1827 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { // arbitrary precision integer constants uint32_t BitWidth = cast((yyvsp[(1) - (2)].PrimType))->getBitWidth(); if ((yyvsp[(2) - (2)].APIntVal)->getBitWidth() > BitWidth) { @@ -4646,7 +4663,7 @@ break; case 184: -#line 1839 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1837 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { // integral constants if (!ConstantInt::isValueValidForType((yyvsp[(1) - (2)].PrimType), (yyvsp[(2) - (2)].UInt64Val))) GEN_ERROR("Constant value doesn't fit in type"); @@ -4656,7 +4673,7 @@ break; case 185: -#line 1845 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1843 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { // arbitrary precision integer constants uint32_t BitWidth = cast((yyvsp[(1) - (2)].PrimType))->getBitWidth(); if ((yyvsp[(2) - (2)].APIntVal)->getBitWidth() > BitWidth) { @@ -4670,7 +4687,7 @@ break; case 186: -#line 1855 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1853 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { // Boolean constants assert(cast((yyvsp[(1) - (2)].PrimType))->getBitWidth() == 1 && "Not Bool?"); (yyval.ConstVal) = ConstantInt::getTrue(); @@ -4679,7 +4696,7 @@ break; case 187: -#line 1860 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1858 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { // Boolean constants assert(cast((yyvsp[(1) - (2)].PrimType))->getBitWidth() == 1 && "Not Bool?"); (yyval.ConstVal) = ConstantInt::getFalse(); @@ -4688,7 +4705,7 @@ break; case 188: -#line 1865 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1863 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { // Floating point constants if (!ConstantFP::isValueValidForType((yyvsp[(1) - (2)].PrimType), *(yyvsp[(2) - (2)].FPVal))) GEN_ERROR("Floating point constant invalid for type"); @@ -4703,7 +4720,7 @@ break; case 189: -#line 1878 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1876 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(5) - (6)].TypeVal))->getDescription()); @@ -4719,7 +4736,7 @@ break; case 190: -#line 1890 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1888 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { if (!isa((yyvsp[(3) - (5)].ConstVal)->getType())) GEN_ERROR("GetElementPtr requires a pointer operand"); @@ -4745,7 +4762,7 @@ break; case 191: -#line 1912 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1910 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { if ((yyvsp[(3) - (8)].ConstVal)->getType() != Type::Int1Ty) GEN_ERROR("Select condition must be of boolean type"); @@ -4757,7 +4774,7 @@ break; case 192: -#line 1920 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1918 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { if ((yyvsp[(3) - (6)].ConstVal)->getType() != (yyvsp[(5) - (6)].ConstVal)->getType()) GEN_ERROR("Binary operator types must match"); @@ -4767,7 +4784,7 @@ break; case 193: -#line 1926 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1924 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { if ((yyvsp[(3) - (6)].ConstVal)->getType() != (yyvsp[(5) - (6)].ConstVal)->getType()) GEN_ERROR("Logical operator types must match"); @@ -4782,7 +4799,7 @@ break; case 194: -#line 1937 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1935 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { if ((yyvsp[(4) - (7)].ConstVal)->getType() != (yyvsp[(6) - (7)].ConstVal)->getType()) GEN_ERROR("icmp operand types must match"); @@ -4791,7 +4808,7 @@ break; case 195: -#line 1942 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1940 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { if ((yyvsp[(4) - (7)].ConstVal)->getType() != (yyvsp[(6) - (7)].ConstVal)->getType()) GEN_ERROR("fcmp operand types must match"); @@ -4800,7 +4817,7 @@ break; case 196: -#line 1947 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1945 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { if (!ExtractElementInst::isValidOperands((yyvsp[(3) - (6)].ConstVal), (yyvsp[(5) - (6)].ConstVal))) GEN_ERROR("Invalid extractelement operands"); @@ -4810,7 +4827,7 @@ break; case 197: -#line 1953 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1951 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { if (!InsertElementInst::isValidOperands((yyvsp[(3) - (8)].ConstVal), (yyvsp[(5) - (8)].ConstVal), (yyvsp[(7) - (8)].ConstVal))) GEN_ERROR("Invalid insertelement operands"); @@ -4820,7 +4837,7 @@ break; case 198: -#line 1959 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1957 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { if (!ShuffleVectorInst::isValidOperands((yyvsp[(3) - (8)].ConstVal), (yyvsp[(5) - (8)].ConstVal), (yyvsp[(7) - (8)].ConstVal))) GEN_ERROR("Invalid shufflevector operands"); @@ -4830,7 +4847,7 @@ break; case 199: -#line 1968 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1966 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { ((yyval.ConstVector) = (yyvsp[(1) - (3)].ConstVector))->push_back((yyvsp[(3) - (3)].ConstVal)); CHECK_FOR_ERROR @@ -4838,7 +4855,7 @@ break; case 200: -#line 1972 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1970 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.ConstVector) = new std::vector(); (yyval.ConstVector)->push_back((yyvsp[(1) - (1)].ConstVal)); @@ -4847,27 +4864,27 @@ break; case 201: -#line 1980 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1978 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.BoolVal) = false; ;} break; case 202: -#line 1980 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1978 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.BoolVal) = true; ;} break; case 203: -#line 1983 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1981 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.BoolVal) = true; ;} break; case 204: -#line 1983 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1981 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.BoolVal) = false; ;} break; case 205: -#line 1986 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1984 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { const Type* VTy = (yyvsp[(1) - (2)].TypeVal)->get(); Value *V = getVal(VTy, (yyvsp[(2) - (2)].ValIDVal)); @@ -4883,7 +4900,7 @@ break; case 206: -#line 1998 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 1996 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { Constant *Val = (yyvsp[(3) - (6)].ConstVal); const Type *DestTy = (yyvsp[(5) - (6)].TypeVal)->get(); @@ -4899,7 +4916,7 @@ break; case 207: -#line 2019 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2017 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.ModuleVal) = ParserResult = CurModule.CurrentModule; CurModule.ModuleDone(); @@ -4908,7 +4925,7 @@ break; case 208: -#line 2024 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2022 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.ModuleVal) = ParserResult = CurModule.CurrentModule; CurModule.ModuleDone(); @@ -4917,12 +4934,12 @@ break; case 211: -#line 2037 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2035 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { CurFun.isDeclare = false; ;} break; case 212: -#line 2037 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2035 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { CurFun.FunctionDone(); CHECK_FOR_ERROR @@ -4930,26 +4947,26 @@ break; case 213: -#line 2041 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2039 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { CurFun.isDeclare = true; ;} break; case 214: -#line 2041 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2039 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { CHECK_FOR_ERROR ;} break; case 215: -#line 2044 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2042 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { CHECK_FOR_ERROR ;} break; case 216: -#line 2047 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2045 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(3) - (3)].TypeVal))->getDescription()); @@ -4977,7 +4994,7 @@ break; case 217: -#line 2071 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2069 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { ResolveTypeTo((yyvsp[(1) - (3)].StrVal), (yyvsp[(3) - (3)].PrimType)); @@ -4992,7 +5009,7 @@ break; case 218: -#line 2083 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2081 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { /* "Externally Visible" Linkage */ if ((yyvsp[(5) - (6)].ConstVal) == 0) @@ -5004,14 +5021,14 @@ break; case 219: -#line 2090 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2088 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { CurGV = 0; ;} break; case 220: -#line 2094 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2092 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { if ((yyvsp[(6) - (7)].ConstVal) == 0) GEN_ERROR("Global value initializer is not a constant"); @@ -5021,14 +5038,14 @@ break; case 221: -#line 2099 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2097 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { CurGV = 0; ;} break; case 222: -#line 2103 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2101 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(6) - (7)].TypeVal))->getDescription()); @@ -5039,7 +5056,7 @@ break; case 223: -#line 2109 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2107 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { CurGV = 0; CHECK_FOR_ERROR @@ -5047,7 +5064,7 @@ break; case 224: -#line 2113 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2111 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { std::string Name; if ((yyvsp[(1) - (5)].StrVal)) { @@ -5091,21 +5108,21 @@ break; case 225: -#line 2153 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2151 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { CHECK_FOR_ERROR ;} break; case 226: -#line 2156 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2154 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { CHECK_FOR_ERROR ;} break; case 227: -#line 2162 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2160 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { const std::string &AsmSoFar = CurModule.CurrentModule->getModuleInlineAsm(); if (AsmSoFar.empty()) @@ -5118,7 +5135,7 @@ break; case 228: -#line 2172 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2170 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { CurModule.CurrentModule->setTargetTriple(*(yyvsp[(3) - (3)].StrVal)); delete (yyvsp[(3) - (3)].StrVal); @@ -5126,7 +5143,7 @@ break; case 229: -#line 2176 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2174 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { CurModule.CurrentModule->setDataLayout(*(yyvsp[(3) - (3)].StrVal)); delete (yyvsp[(3) - (3)].StrVal); @@ -5134,7 +5151,7 @@ break; case 231: -#line 2183 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2181 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { CurModule.CurrentModule->addLibrary(*(yyvsp[(3) - (3)].StrVal)); delete (yyvsp[(3) - (3)].StrVal); @@ -5143,7 +5160,7 @@ break; case 232: -#line 2188 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2186 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { CurModule.CurrentModule->addLibrary(*(yyvsp[(1) - (1)].StrVal)); delete (yyvsp[(1) - (1)].StrVal); @@ -5152,14 +5169,14 @@ break; case 233: -#line 2193 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2191 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { CHECK_FOR_ERROR ;} break; case 234: -#line 2202 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2200 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(3) - (5)].TypeVal))->getDescription()); @@ -5173,7 +5190,7 @@ break; case 235: -#line 2212 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2210 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(1) - (3)].TypeVal))->getDescription()); @@ -5187,7 +5204,7 @@ break; case 236: -#line 2223 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2221 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.ArgList) = (yyvsp[(1) - (1)].ArgList); CHECK_FOR_ERROR @@ -5195,7 +5212,7 @@ break; case 237: -#line 2227 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2225 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.ArgList) = (yyvsp[(1) - (3)].ArgList); struct ArgListEntry E; @@ -5208,7 +5225,7 @@ break; case 238: -#line 2236 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2234 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.ArgList) = new ArgListType; struct ArgListEntry E; @@ -5221,7 +5238,7 @@ break; case 239: -#line 2245 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2243 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.ArgList) = 0; CHECK_FOR_ERROR @@ -5229,7 +5246,7 @@ break; case 240: -#line 2251 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2249 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { std::string FunctionName(*(yyvsp[(3) - (10)].StrVal)); delete (yyvsp[(3) - (10)].StrVal); // Free strdup'd memory! @@ -5365,7 +5382,7 @@ break; case 243: -#line 2386 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2384 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.FunctionVal) = CurFun.CurrentFunction; @@ -5377,7 +5394,7 @@ break; case 246: -#line 2397 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2395 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.FunctionVal) = (yyvsp[(1) - (2)].FunctionVal); CHECK_FOR_ERROR @@ -5385,7 +5402,7 @@ break; case 247: -#line 2402 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2400 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { CurFun.CurrentFunction->setLinkage((yyvsp[(1) - (3)].Linkage)); CurFun.CurrentFunction->setVisibility((yyvsp[(2) - (3)].Visibility)); @@ -5396,7 +5413,7 @@ break; case 248: -#line 2414 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2412 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.BoolVal) = false; CHECK_FOR_ERROR @@ -5404,7 +5421,7 @@ break; case 249: -#line 2418 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2416 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.BoolVal) = true; CHECK_FOR_ERROR @@ -5412,7 +5429,7 @@ break; case 250: -#line 2423 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2421 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { // A reference to a direct constant (yyval.ValIDVal) = ValID::create((yyvsp[(1) - (1)].SInt64Val)); CHECK_FOR_ERROR @@ -5420,7 +5437,7 @@ break; case 251: -#line 2427 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2425 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.ValIDVal) = ValID::create((yyvsp[(1) - (1)].UInt64Val)); CHECK_FOR_ERROR @@ -5428,7 +5445,7 @@ break; case 252: -#line 2431 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2429 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { // Perhaps it's an FP constant? (yyval.ValIDVal) = ValID::create((yyvsp[(1) - (1)].FPVal)); CHECK_FOR_ERROR @@ -5436,7 +5453,7 @@ break; case 253: -#line 2435 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2433 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.ValIDVal) = ValID::create(ConstantInt::getTrue()); CHECK_FOR_ERROR @@ -5444,7 +5461,7 @@ break; case 254: -#line 2439 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2437 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.ValIDVal) = ValID::create(ConstantInt::getFalse()); CHECK_FOR_ERROR @@ -5452,7 +5469,7 @@ break; case 255: -#line 2443 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2441 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.ValIDVal) = ValID::createNull(); CHECK_FOR_ERROR @@ -5460,7 +5477,7 @@ break; case 256: -#line 2447 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2445 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.ValIDVal) = ValID::createUndef(); CHECK_FOR_ERROR @@ -5468,7 +5485,7 @@ break; case 257: -#line 2451 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2449 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { // A vector zero constant. (yyval.ValIDVal) = ValID::createZeroInit(); CHECK_FOR_ERROR @@ -5476,7 +5493,7 @@ break; case 258: -#line 2455 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2453 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { // Nonempty unsized packed vector const Type *ETy = (*(yyvsp[(2) - (3)].ConstVector))[0]->getType(); int NumElements = (yyvsp[(2) - (3)].ConstVector)->size(); @@ -5505,7 +5522,7 @@ break; case 259: -#line 2480 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2478 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.ValIDVal) = ValID::create((yyvsp[(1) - (1)].ConstVal)); CHECK_FOR_ERROR @@ -5513,7 +5530,7 @@ break; case 260: -#line 2484 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2482 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.ValIDVal) = ValID::createInlineAsm(*(yyvsp[(3) - (5)].StrVal), *(yyvsp[(5) - (5)].StrVal), (yyvsp[(2) - (5)].BoolVal)); delete (yyvsp[(3) - (5)].StrVal); @@ -5523,7 +5540,7 @@ break; case 261: -#line 2494 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2492 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { // Is it an integer reference...? (yyval.ValIDVal) = ValID::createLocalID((yyvsp[(1) - (1)].UIntVal)); CHECK_FOR_ERROR @@ -5531,7 +5548,7 @@ break; case 262: -#line 2498 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2496 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.ValIDVal) = ValID::createGlobalID((yyvsp[(1) - (1)].UIntVal)); CHECK_FOR_ERROR @@ -5539,7 +5556,7 @@ break; case 263: -#line 2502 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2500 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { // Is it a named reference...? (yyval.ValIDVal) = ValID::createLocalName(*(yyvsp[(1) - (1)].StrVal)); delete (yyvsp[(1) - (1)].StrVal); @@ -5548,7 +5565,7 @@ break; case 264: -#line 2507 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2505 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { // Is it a named reference...? (yyval.ValIDVal) = ValID::createGlobalName(*(yyvsp[(1) - (1)].StrVal)); delete (yyvsp[(1) - (1)].StrVal); @@ -5557,7 +5574,7 @@ break; case 267: -#line 2520 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2518 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(1) - (2)].TypeVal))->getDescription()); @@ -5568,7 +5585,7 @@ break; case 268: -#line 2529 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2527 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.ValueList) = new std::vector(); (yyval.ValueList)->push_back((yyvsp[(1) - (1)].ValueVal)); @@ -5577,7 +5594,7 @@ break; case 269: -#line 2534 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2532 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { ((yyval.ValueList)=(yyvsp[(1) - (3)].ValueList))->push_back((yyvsp[(3) - (3)].ValueVal)); CHECK_FOR_ERROR @@ -5585,7 +5602,7 @@ break; case 270: -#line 2539 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2537 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.FunctionVal) = (yyvsp[(1) - (2)].FunctionVal); CHECK_FOR_ERROR @@ -5593,7 +5610,7 @@ break; case 271: -#line 2543 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2541 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { // Do not allow functions with 0 basic blocks (yyval.FunctionVal) = (yyvsp[(1) - (2)].FunctionVal); CHECK_FOR_ERROR @@ -5601,7 +5618,7 @@ break; case 272: -#line 2552 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2550 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { setValueName((yyvsp[(3) - (3)].TermInstVal), (yyvsp[(2) - (3)].StrVal)); CHECK_FOR_ERROR @@ -5613,7 +5630,7 @@ break; case 273: -#line 2561 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2559 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { if (CastInst *CI1 = dyn_cast((yyvsp[(2) - (2)].InstVal))) if (CastInst *CI2 = dyn_cast(CI1->getOperand(0))) @@ -5626,25 +5643,41 @@ break; case 274: -#line 2570 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2568 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { // Empty space between instruction lists - (yyval.BasicBlockVal) = defineBBVal(ValID::createLocalID(CurFun.NextValNum)); + (yyval.BasicBlockVal) = defineBBVal(ValID::createLocalID(CurFun.NextValNum), 0); CHECK_FOR_ERROR ;} break; case 275: -#line 2574 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 2572 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" + { // Only the unwind to block + (yyval.BasicBlockVal) = defineBBVal(ValID::createLocalID(CurFun.NextValNum), getBBVal((yyvsp[(2) - (2)].ValIDVal))); + CHECK_FOR_ERROR + ;} + break; + + case 276: +#line 2576 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { // Labelled (named) basic block - (yyval.BasicBlockVal) = defineBBVal(ValID::createLocalName(*(yyvsp[(1) - (1)].StrVal))); + (yyval.BasicBlockVal) = defineBBVal(ValID::createLocalName(*(yyvsp[(1) - (1)].StrVal)), 0); delete (yyvsp[(1) - (1)].StrVal); CHECK_FOR_ERROR + ;} + break; + case 277: +#line 2581 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" + { + (yyval.BasicBlockVal) = defineBBVal(ValID::createLocalName(*(yyvsp[(1) - (3)].StrVal)), getBBVal((yyvsp[(3) - (3)].ValIDVal))); + delete (yyvsp[(1) - (3)].StrVal); + CHECK_FOR_ERROR ;} break; - case 276: -#line 2582 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" + case 278: +#line 2588 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { // Return with a result... ValueList &VL = *(yyvsp[(2) - (2)].ValueList); assert(!VL.empty() && "Invalid ret operands!"); @@ -5654,16 +5687,16 @@ ;} break; - case 277: -#line 2589 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" + case 279: +#line 2595 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { // Return with no result... (yyval.TermInstVal) = new ReturnInst(); CHECK_FOR_ERROR ;} break; - case 278: -#line 2593 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" + case 280: +#line 2599 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { // Unconditional Branch... BasicBlock* tmpBB = getBBVal((yyvsp[(3) - (3)].ValIDVal)); CHECK_FOR_ERROR @@ -5671,8 +5704,8 @@ ;} break; - case 279: -#line 2598 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" + case 281: +#line 2604 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { assert(cast((yyvsp[(2) - (9)].PrimType))->getBitWidth() == 1 && "Not Bool?"); BasicBlock* tmpBBA = getBBVal((yyvsp[(6) - (9)].ValIDVal)); @@ -5685,8 +5718,8 @@ ;} break; - case 280: -#line 2608 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" + case 282: +#line 2614 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { Value* tmpVal = getVal((yyvsp[(2) - (9)].PrimType), (yyvsp[(3) - (9)].ValIDVal)); CHECK_FOR_ERROR @@ -5708,8 +5741,8 @@ ;} break; - case 281: -#line 2627 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" + case 283: +#line 2633 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { Value* tmpVal = getVal((yyvsp[(2) - (8)].PrimType), (yyvsp[(3) - (8)].ValIDVal)); CHECK_FOR_ERROR @@ -5721,8 +5754,8 @@ ;} break; - case 282: -#line 2637 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" + case 284: +#line 2643 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { // Handle the short syntax @@ -5815,24 +5848,24 @@ ;} break; - case 283: -#line 2727 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" + case 285: +#line 2733 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.TermInstVal) = new UnwindInst(); CHECK_FOR_ERROR ;} break; - case 284: -#line 2731 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" + case 286: +#line 2737 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.TermInstVal) = new UnreachableInst(); CHECK_FOR_ERROR ;} break; - case 285: -#line 2738 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" + case 287: +#line 2744 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.JumpTable) = (yyvsp[(1) - (6)].JumpTable); Constant *V = cast(getExistingVal((yyvsp[(2) - (6)].PrimType), (yyvsp[(3) - (6)].ValIDVal))); @@ -5846,8 +5879,8 @@ ;} break; - case 286: -#line 2749 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" + case 288: +#line 2755 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.JumpTable) = new std::vector >(); Constant *V = cast(getExistingVal((yyvsp[(1) - (5)].PrimType), (yyvsp[(2) - (5)].ValIDVal))); @@ -5862,8 +5895,8 @@ ;} break; - case 287: -#line 2762 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" + case 289: +#line 2768 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { // Is this definition named?? if so, assign the name... setValueName((yyvsp[(2) - (2)].InstVal), (yyvsp[(1) - (2)].StrVal)); @@ -5874,8 +5907,8 @@ ;} break; - case 288: -#line 2772 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" + case 290: +#line 2778 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { // Used for PHI nodes if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(1) - (6)].TypeVal))->getDescription()); @@ -5889,8 +5922,8 @@ ;} break; - case 289: -#line 2783 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" + case 291: +#line 2789 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.PHIList) = (yyvsp[(1) - (7)].PHIList); Value* tmpVal = getVal((yyvsp[(1) - (7)].PHIList)->front().first->getType(), (yyvsp[(4) - (7)].ValIDVal)); @@ -5901,8 +5934,8 @@ ;} break; - case 290: -#line 2793 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" + case 292: +#line 2799 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { // FIXME: Remove trailing OptParamAttrs in LLVM 3.0, it was a mistake in 2.0 if (!UpRefs.empty()) @@ -5916,8 +5949,8 @@ ;} break; - case 291: -#line 2804 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" + case 293: +#line 2810 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { // FIXME: Remove trailing OptParamAttrs in LLVM 3.0, it was a mistake in 2.0 // Labels are only valid in ASMs @@ -5928,8 +5961,8 @@ ;} break; - case 292: -#line 2812 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" + case 294: +#line 2818 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { // FIXME: Remove trailing OptParamAttrs in LLVM 3.0, it was a mistake in 2.0 if (!UpRefs.empty()) @@ -5942,8 +5975,8 @@ ;} break; - case 293: -#line 2822 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" + case 295: +#line 2828 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { // FIXME: Remove trailing OptParamAttrs in LLVM 3.0, it was a mistake in 2.0 (yyval.ParamList) = (yyvsp[(1) - (6)].ParamList); @@ -5953,18 +5986,18 @@ ;} break; - case 294: -#line 2829 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" + case 296: +#line 2835 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.ParamList) = new ParamList(); ;} break; - case 295: -#line 2832 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" + case 297: +#line 2838 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.ValueList) = new std::vector(); ;} break; - case 296: -#line 2833 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" + case 298: +#line 2839 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.ValueList) = (yyvsp[(1) - (3)].ValueList); (yyval.ValueList)->push_back((yyvsp[(3) - (3)].ValueVal)); @@ -5972,24 +6005,24 @@ ;} break; - case 297: -#line 2840 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" + case 299: +#line 2846 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.BoolVal) = true; CHECK_FOR_ERROR ;} break; - case 298: -#line 2844 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" + case 300: +#line 2850 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.BoolVal) = false; CHECK_FOR_ERROR ;} break; - case 299: -#line 2849 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" + case 301: +#line 2855 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(2) - (5)].TypeVal))->getDescription()); @@ -6008,8 +6041,8 @@ ;} break; - case 300: -#line 2865 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" + case 302: +#line 2871 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(2) - (5)].TypeVal))->getDescription()); @@ -6029,8 +6062,8 @@ ;} break; - case 301: -#line 2882 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" + case 303: +#line 2888 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(3) - (6)].TypeVal))->getDescription()); @@ -6047,8 +6080,8 @@ ;} break; - case 302: -#line 2896 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" + case 304: +#line 2902 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(3) - (6)].TypeVal))->getDescription()); @@ -6065,8 +6098,8 @@ ;} break; - case 303: -#line 2910 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" + case 305: +#line 2916 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(4) - (4)].TypeVal))->getDescription()); @@ -6081,8 +6114,8 @@ ;} break; - case 304: -#line 2922 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" + case 306: +#line 2928 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { if ((yyvsp[(2) - (6)].ValueVal)->getType() != Type::Int1Ty) GEN_ERROR("select condition must be boolean"); @@ -6093,8 +6126,8 @@ ;} break; - case 305: -#line 2930 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" + case 307: +#line 2936 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(4) - (4)].TypeVal))->getDescription()); @@ -6104,8 +6137,8 @@ ;} break; - case 306: -#line 2937 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" + case 308: +#line 2943 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { if (!ExtractElementInst::isValidOperands((yyvsp[(2) - (4)].ValueVal), (yyvsp[(4) - (4)].ValueVal))) GEN_ERROR("Invalid extractelement operands"); @@ -6114,8 +6147,8 @@ ;} break; - case 307: -#line 2943 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" + case 309: +#line 2949 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { if (!InsertElementInst::isValidOperands((yyvsp[(2) - (6)].ValueVal), (yyvsp[(4) - (6)].ValueVal), (yyvsp[(6) - (6)].ValueVal))) GEN_ERROR("Invalid insertelement operands"); @@ -6124,8 +6157,8 @@ ;} break; - case 308: -#line 2949 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" + case 310: +#line 2955 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { if (!ShuffleVectorInst::isValidOperands((yyvsp[(2) - (6)].ValueVal), (yyvsp[(4) - (6)].ValueVal), (yyvsp[(6) - (6)].ValueVal))) GEN_ERROR("Invalid shufflevector operands"); @@ -6134,8 +6167,8 @@ ;} break; - case 309: -#line 2955 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" + case 311: +#line 2961 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { const Type *Ty = (yyvsp[(2) - (2)].PHIList)->front().first->getType(); if (!Ty->isFirstClassType()) @@ -6153,8 +6186,8 @@ ;} break; - case 310: -#line 2971 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" + case 312: +#line 2977 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { // Handle the short syntax @@ -6254,32 +6287,32 @@ ;} break; - case 311: -#line 3068 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" + case 313: +#line 3074 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.InstVal) = (yyvsp[(1) - (1)].InstVal); CHECK_FOR_ERROR ;} break; - case 312: -#line 3073 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" + case 314: +#line 3079 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.BoolVal) = true; CHECK_FOR_ERROR ;} break; - case 313: -#line 3077 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" + case 315: +#line 3083 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { (yyval.BoolVal) = false; CHECK_FOR_ERROR ;} break; - case 314: -#line 3084 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" + case 316: +#line 3090 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(2) - (3)].TypeVal))->getDescription()); @@ -6289,8 +6322,8 @@ ;} break; - case 315: -#line 3091 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" + case 317: +#line 3097 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(2) - (6)].TypeVal))->getDescription()); @@ -6301,8 +6334,8 @@ ;} break; - case 316: -#line 3099 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" + case 318: +#line 3105 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(2) - (3)].TypeVal))->getDescription()); @@ -6312,8 +6345,8 @@ ;} break; - case 317: -#line 3106 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" + case 319: +#line 3112 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(2) - (6)].TypeVal))->getDescription()); @@ -6324,8 +6357,8 @@ ;} break; - case 318: -#line 3114 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" + case 320: +#line 3120 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { if (!isa((yyvsp[(2) - (2)].ValueVal)->getType())) GEN_ERROR("Trying to free nonpointer type " + @@ -6335,8 +6368,8 @@ ;} break; - case 319: -#line 3122 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" + case 321: +#line 3128 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(3) - (5)].TypeVal))->getDescription()); @@ -6353,8 +6386,8 @@ ;} break; - case 320: -#line 3136 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" + case 322: +#line 3142 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(5) - (7)].TypeVal))->getDescription()); @@ -6374,8 +6407,8 @@ ;} break; - case 321: -#line 3153 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" + case 323: +#line 3159 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { Value *TmpVal = getVal((yyvsp[(2) - (5)].TypeVal)->get(), (yyvsp[(3) - (5)].ValIDVal)); if (!GetResultInst::isValidOperands(TmpVal, (yyvsp[(5) - (5)].UInt64Val))) @@ -6386,8 +6419,8 @@ ;} break; - case 322: -#line 3161 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" + case 324: +#line 3167 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { if (!UpRefs.empty()) GEN_ERROR("Invalid upreference in type: " + (*(yyvsp[(2) - (4)].TypeVal))->getDescription()); @@ -6407,7 +6440,7 @@ /* Line 1267 of yacc.c. */ -#line 6411 "llvmAsmParser.tab.c" +#line 6444 "llvmAsmParser.tab.c" default: break; } YY_SYMBOL_PRINT ("-> $$ =", yyr1[yyn], &yyval, &yyloc); @@ -6621,7 +6654,7 @@ } -#line 3178 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 3184 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" // common code from the two 'RunVMAsmParser' functions Modified: llvm/trunk/lib/AsmParser/llvmAsmParser.h.cvs URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/llvmAsmParser.h.cvs?rev=47849&r1=47848&r2=47849&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/llvmAsmParser.h.cvs (original) +++ llvm/trunk/lib/AsmParser/llvmAsmParser.h.cvs Mon Mar 3 12:58:47 2008 @@ -104,89 +104,90 @@ X86_STDCALLCC_TOK = 320, X86_FASTCALLCC_TOK = 321, DATALAYOUT = 322, - RET = 323, - BR = 324, - SWITCH = 325, - INVOKE = 326, - UNWIND = 327, - UNREACHABLE = 328, - ADD = 329, - SUB = 330, - MUL = 331, - UDIV = 332, - SDIV = 333, - FDIV = 334, - UREM = 335, - SREM = 336, - FREM = 337, - AND = 338, - OR = 339, - XOR = 340, - SHL = 341, - LSHR = 342, - ASHR = 343, - ICMP = 344, - FCMP = 345, - EQ = 346, - NE = 347, - SLT = 348, - SGT = 349, - SLE = 350, - SGE = 351, - ULT = 352, - UGT = 353, - ULE = 354, - UGE = 355, - OEQ = 356, - ONE = 357, - OLT = 358, - OGT = 359, - OLE = 360, - OGE = 361, - ORD = 362, - UNO = 363, - UEQ = 364, - UNE = 365, - MALLOC = 366, - ALLOCA = 367, - FREE = 368, - LOAD = 369, - STORE = 370, - GETELEMENTPTR = 371, - TRUNC = 372, - ZEXT = 373, - SEXT = 374, - FPTRUNC = 375, - FPEXT = 376, - BITCAST = 377, - UITOFP = 378, - SITOFP = 379, - FPTOUI = 380, - FPTOSI = 381, - INTTOPTR = 382, - PTRTOINT = 383, - PHI_TOK = 384, - SELECT = 385, - VAARG = 386, - EXTRACTELEMENT = 387, - INSERTELEMENT = 388, - SHUFFLEVECTOR = 389, - GETRESULT = 390, - SIGNEXT = 391, - ZEROEXT = 392, - NORETURN = 393, - INREG = 394, - SRET = 395, - NOUNWIND = 396, - NOALIAS = 397, - BYVAL = 398, - NEST = 399, - READNONE = 400, - READONLY = 401, - GC = 402, - DEFAULT = 403, - HIDDEN = 404, - PROTECTED = 405 + UNWIND_TO = 323, + RET = 324, + BR = 325, + SWITCH = 326, + INVOKE = 327, + UNWIND = 328, + UNREACHABLE = 329, + ADD = 330, + SUB = 331, + MUL = 332, + UDIV = 333, + SDIV = 334, + FDIV = 335, + UREM = 336, + SREM = 337, + FREM = 338, + AND = 339, + OR = 340, + XOR = 341, + SHL = 342, + LSHR = 343, + ASHR = 344, + ICMP = 345, + FCMP = 346, + EQ = 347, + NE = 348, + SLT = 349, + SGT = 350, + SLE = 351, + SGE = 352, + ULT = 353, + UGT = 354, + ULE = 355, + UGE = 356, + OEQ = 357, + ONE = 358, + OLT = 359, + OGT = 360, + OLE = 361, + OGE = 362, + ORD = 363, + UNO = 364, + UEQ = 365, + UNE = 366, + MALLOC = 367, + ALLOCA = 368, + FREE = 369, + LOAD = 370, + STORE = 371, + GETELEMENTPTR = 372, + TRUNC = 373, + ZEXT = 374, + SEXT = 375, + FPTRUNC = 376, + FPEXT = 377, + BITCAST = 378, + UITOFP = 379, + SITOFP = 380, + FPTOUI = 381, + FPTOSI = 382, + INTTOPTR = 383, + PTRTOINT = 384, + PHI_TOK = 385, + SELECT = 386, + VAARG = 387, + EXTRACTELEMENT = 388, + INSERTELEMENT = 389, + SHUFFLEVECTOR = 390, + GETRESULT = 391, + SIGNEXT = 392, + ZEROEXT = 393, + NORETURN = 394, + INREG = 395, + SRET = 396, + NOUNWIND = 397, + NOALIAS = 398, + BYVAL = 399, + NEST = 400, + READNONE = 401, + READONLY = 402, + GC = 403, + DEFAULT = 404, + HIDDEN = 405, + PROTECTED = 406 }; #endif /* Tokens. */ @@ -255,96 +256,97 @@ #define X86_STDCALLCC_TOK 320 #define X86_FASTCALLCC_TOK 321 #define DATALAYOUT 322 -#define RET 323 -#define BR 324 -#define SWITCH 325 -#define INVOKE 326 -#define UNWIND 327 -#define UNREACHABLE 328 -#define ADD 329 -#define SUB 330 -#define MUL 331 -#define UDIV 332 -#define SDIV 333 -#define FDIV 334 -#define UREM 335 -#define SREM 336 -#define FREM 337 -#define AND 338 -#define OR 339 -#define XOR 340 -#define SHL 341 -#define LSHR 342 -#define ASHR 343 -#define ICMP 344 -#define FCMP 345 -#define EQ 346 -#define NE 347 -#define SLT 348 -#define SGT 349 -#define SLE 350 -#define SGE 351 -#define ULT 352 -#define UGT 353 -#define ULE 354 -#define UGE 355 -#define OEQ 356 -#define ONE 357 -#define OLT 358 -#define OGT 359 -#define OLE 360 -#define OGE 361 -#define ORD 362 -#define UNO 363 -#define UEQ 364 -#define UNE 365 -#define MALLOC 366 -#define ALLOCA 367 -#define FREE 368 -#define LOAD 369 -#define STORE 370 -#define GETELEMENTPTR 371 -#define TRUNC 372 -#define ZEXT 373 -#define SEXT 374 -#define FPTRUNC 375 -#define FPEXT 376 -#define BITCAST 377 -#define UITOFP 378 -#define SITOFP 379 -#define FPTOUI 380 -#define FPTOSI 381 -#define INTTOPTR 382 -#define PTRTOINT 383 -#define PHI_TOK 384 -#define SELECT 385 -#define VAARG 386 -#define EXTRACTELEMENT 387 -#define INSERTELEMENT 388 -#define SHUFFLEVECTOR 389 -#define GETRESULT 390 -#define SIGNEXT 391 -#define ZEROEXT 392 -#define NORETURN 393 -#define INREG 394 -#define SRET 395 -#define NOUNWIND 396 -#define NOALIAS 397 -#define BYVAL 398 -#define NEST 399 -#define READNONE 400 -#define READONLY 401 -#define GC 402 -#define DEFAULT 403 -#define HIDDEN 404 -#define PROTECTED 405 +#define UNWIND_TO 323 +#define RET 324 +#define BR 325 +#define SWITCH 326 +#define INVOKE 327 +#define UNWIND 328 +#define UNREACHABLE 329 +#define ADD 330 +#define SUB 331 +#define MUL 332 +#define UDIV 333 +#define SDIV 334 +#define FDIV 335 +#define UREM 336 +#define SREM 337 +#define FREM 338 +#define AND 339 +#define OR 340 +#define XOR 341 +#define SHL 342 +#define LSHR 343 +#define ASHR 344 +#define ICMP 345 +#define FCMP 346 +#define EQ 347 +#define NE 348 +#define SLT 349 +#define SGT 350 +#define SLE 351 +#define SGE 352 +#define ULT 353 +#define UGT 354 +#define ULE 355 +#define UGE 356 +#define OEQ 357 +#define ONE 358 +#define OLT 359 +#define OGT 360 +#define OLE 361 +#define OGE 362 +#define ORD 363 +#define UNO 364 +#define UEQ 365 +#define UNE 366 +#define MALLOC 367 +#define ALLOCA 368 +#define FREE 369 +#define LOAD 370 +#define STORE 371 +#define GETELEMENTPTR 372 +#define TRUNC 373 +#define ZEXT 374 +#define SEXT 375 +#define FPTRUNC 376 +#define FPEXT 377 +#define BITCAST 378 +#define UITOFP 379 +#define SITOFP 380 +#define FPTOUI 381 +#define FPTOSI 382 +#define INTTOPTR 383 +#define PTRTOINT 384 +#define PHI_TOK 385 +#define SELECT 386 +#define VAARG 387 +#define EXTRACTELEMENT 388 +#define INSERTELEMENT 389 +#define SHUFFLEVECTOR 390 +#define GETRESULT 391 +#define SIGNEXT 392 +#define ZEROEXT 393 +#define NORETURN 394 +#define INREG 395 +#define SRET 396 +#define NOUNWIND 397 +#define NOALIAS 398 +#define BYVAL 399 +#define NEST 400 +#define READNONE 401 +#define READONLY 402 +#define GC 403 +#define DEFAULT 404 +#define HIDDEN 405 +#define PROTECTED 406 #if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED typedef union YYSTYPE -#line 953 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" +#line 951 "/Volumes/Nanpura/mrv/llvm/lib/AsmParser/llvmAsmParser.y" { llvm::Module *ModuleVal; llvm::Function *FunctionVal; @@ -392,7 +394,7 @@ llvm::FCmpInst::Predicate FPredicate; } /* Line 1529 of yacc.c. */ -#line 396 "llvmAsmParser.tab.h" +#line 398 "llvmAsmParser.tab.h" YYSTYPE; # define yystype YYSTYPE /* obsolescent; will be withdrawn */ # define YYSTYPE_IS_DECLARED 1 Modified: llvm/trunk/lib/AsmParser/llvmAsmParser.y.cvs URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/llvmAsmParser.y.cvs?rev=47849&r1=47848&r2=47849&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/llvmAsmParser.y.cvs (original) +++ llvm/trunk/lib/AsmParser/llvmAsmParser.y.cvs Mon Mar 3 12:58:47 2008 @@ -518,7 +518,7 @@ /// defineBBVal - This is a definition of a new basic block with the specified /// identifier which must be the same as CurFun.NextValNum, if its numeric. -static BasicBlock *defineBBVal(const ValID &ID) { +static BasicBlock *defineBBVal(const ValID &ID, BasicBlock *unwindDest) { assert(inFunctionScope() && "Can't get basic block at global scope!"); BasicBlock *BB = 0; @@ -548,21 +548,19 @@ assert(ID.Num == CurFun.NextValNum && "Invalid new block number"); InsertValue(BB); } - - ID.destroy(); - return BB; - } - - // We haven't seen this BB before and its first mention is a definition. - // Just create it and return it. - std::string Name (ID.Type == ValID::LocalName ? ID.getName() : ""); - BB = new BasicBlock(Name, CurFun.CurrentFunction); - if (ID.Type == ValID::LocalID) { - assert(ID.Num == CurFun.NextValNum && "Invalid new block number"); - InsertValue(BB); + } else { + // We haven't seen this BB before and its first mention is a definition. + // Just create it and return it. + std::string Name (ID.Type == ValID::LocalName ? ID.getName() : ""); + BB = new BasicBlock(Name, CurFun.CurrentFunction); + if (ID.Type == ValID::LocalID) { + assert(ID.Num == CurFun.NextValNum && "Invalid new block number"); + InsertValue(BB); + } } - ID.destroy(); // Free strdup'd memory + ID.destroy(); + BB->setUnwindDest(unwindDest); return BB; } @@ -1066,7 +1064,7 @@ %token OPAQUE EXTERNAL TARGET TRIPLE ALIGN ADDRSPACE %token DEPLIBS CALL TAIL ASM_TOK MODULE SIDEEFFECT %token CC_TOK CCC_TOK FASTCC_TOK COLDCC_TOK X86_STDCALLCC_TOK X86_FASTCALLCC_TOK -%token DATALAYOUT +%token DATALAYOUT UNWIND_TO %type OptCallingConv %type OptParamAttrs ParamAttr %type OptFuncAttrs FuncAttr @@ -2568,14 +2566,22 @@ CHECK_FOR_ERROR } | /* empty */ { // Empty space between instruction lists - $$ = defineBBVal(ValID::createLocalID(CurFun.NextValNum)); + $$ = defineBBVal(ValID::createLocalID(CurFun.NextValNum), 0); + CHECK_FOR_ERROR + } + | UNWIND_TO ValueRef { // Only the unwind to block + $$ = defineBBVal(ValID::createLocalID(CurFun.NextValNum), getBBVal($2)); CHECK_FOR_ERROR } | LABELSTR { // Labelled (named) basic block - $$ = defineBBVal(ValID::createLocalName(*$1)); + $$ = defineBBVal(ValID::createLocalName(*$1), 0); + delete $1; + CHECK_FOR_ERROR + } + | LABELSTR UNWIND_TO ValueRef { + $$ = defineBBVal(ValID::createLocalName(*$1), getBBVal($3)); delete $1; CHECK_FOR_ERROR - }; BBTerminatorInst : From clattner at apple.com Mon Mar 3 13:39:03 2008 From: clattner at apple.com (Chris Lattner) Date: Mon, 3 Mar 2008 11:39:03 -0800 Subject: [llvm-commits] [llvm] r47848 - in /llvm/trunk/lib/VMCore: Function.cpp Verifier.cpp In-Reply-To: <200803031858.m23IwGpW007057@zion.cs.uiuc.edu> References: <200803031858.m23IwGpW007057@zion.cs.uiuc.edu> Message-ID: On Mar 3, 2008, at 10:58 AM, Devang Patel wrote: > Author: dpatel > Date: Mon Mar 3 12:58:16 2008 > New Revision: 47848 > > URL: http://llvm.org/viewvc/llvm-project?rev=47848&view=rev > Log: > If a function uses multive values in ret instruction then it > is returning a struct value. Why do you want to do this? I think it would make sense to rename isStructReturn to hasStructRetAttribute() or something, but I don't think it makes sense to return true if the function returns multiple results. What does this fix? -Chris > > > Modified: > llvm/trunk/lib/VMCore/Function.cpp > llvm/trunk/lib/VMCore/Verifier.cpp > > Modified: llvm/trunk/lib/VMCore/Function.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Function.cpp?rev=47848&r1=47847&r2=47848&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/VMCore/Function.cpp (original) > +++ llvm/trunk/lib/VMCore/Function.cpp Mon Mar 3 12:58:16 2008 > @@ -170,7 +170,8 @@ > > /// @brief Determine if the function returns a structure. > bool Function::isStructReturn() const { > - return paramHasAttr(1, ParamAttr::StructRet); > + return paramHasAttr(1, ParamAttr::StructRet) > + || isa(getReturnType()); > } > > // > = > = > = > ----------------------------------------------------------------------= > ==// > > Modified: llvm/trunk/lib/VMCore/Verifier.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Verifier.cpp?rev=47848&r1=47847&r2=47848&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/VMCore/Verifier.cpp (original) > +++ llvm/trunk/lib/VMCore/Verifier.cpp Mon Mar 3 12:58:16 2008 > @@ -455,9 +455,6 @@ > isa(F.getReturnType()), > "Functions cannot return aggregate values!", &F); > > - Assert1(!F.isStructReturn() || FT->getReturnType() == Type::VoidTy, > - "Invalid struct-return function!", &F); > - > const ParamAttrsList *Attrs = F.getParamAttrs(); > > Assert1(!Attrs || > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From alenhar2 at cs.uiuc.edu Mon Mar 3 13:39:27 2008 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Mon, 03 Mar 2008 19:39:27 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r47853 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Message-ID: <200803031939.m23JdRZT008833@zion.cs.uiuc.edu> Author: alenhar2 Date: Mon Mar 3 13:39:27 2008 New Revision: 47853 URL: http://llvm.org/viewvc/llvm-project?rev=47853&view=rev Log: add some other atomic builtins that don't require loops Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=47853&r1=47852&r2=47853&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Mon Mar 3 13:39:27 2008 @@ -4300,7 +4300,12 @@ case BUILT_IN_VAL_COMPARE_AND_SWAP_2: case BUILT_IN_VAL_COMPARE_AND_SWAP_4: case BUILT_IN_VAL_COMPARE_AND_SWAP_8: - case BUILT_IN_VAL_COMPARE_AND_SWAP_16: { + case BUILT_IN_VAL_COMPARE_AND_SWAP_16: + case BUILT_IN_BOOL_COMPARE_AND_SWAP_1: + case BUILT_IN_BOOL_COMPARE_AND_SWAP_2: + case BUILT_IN_BOOL_COMPARE_AND_SWAP_4: + case BUILT_IN_BOOL_COMPARE_AND_SWAP_8: + case BUILT_IN_BOOL_COMPARE_AND_SWAP_16: { const Type *Ty = ConvertType(TREE_TYPE(exp)); tree arglist = TREE_OPERAND(exp, 1); Value* C[3] = { @@ -4318,6 +4323,12 @@ Intrinsic::atomic_lcs, &Ty, 1), C, C + 3); + if (((DECL_FUNCTION_CODE(fndecl)) == BUILT_IN_BOOL_COMPARE_AND_SWAP_1) || + ((DECL_FUNCTION_CODE(fndecl)) == BUILT_IN_BOOL_COMPARE_AND_SWAP_2) || + ((DECL_FUNCTION_CODE(fndecl)) == BUILT_IN_BOOL_COMPARE_AND_SWAP_4) || + ((DECL_FUNCTION_CODE(fndecl)) == BUILT_IN_BOOL_COMPARE_AND_SWAP_8) || + ((DECL_FUNCTION_CODE(fndecl)) == BUILT_IN_BOOL_COMPARE_AND_SWAP_16)) + Result = Builder.CreateICmpEQ(Result, C[1]); return true; } @@ -4325,13 +4336,24 @@ case BUILT_IN_FETCH_AND_ADD_2: case BUILT_IN_FETCH_AND_ADD_4: case BUILT_IN_FETCH_AND_ADD_8: - case BUILT_IN_FETCH_AND_ADD_16: { + case BUILT_IN_FETCH_AND_ADD_16: + case BUILT_IN_FETCH_AND_SUB_1: + case BUILT_IN_FETCH_AND_SUB_2: + case BUILT_IN_FETCH_AND_SUB_4: + case BUILT_IN_FETCH_AND_SUB_8: + case BUILT_IN_FETCH_AND_SUB_16: { const Type *Ty = ConvertType(TREE_TYPE(exp)); tree arglist = TREE_OPERAND(exp, 1); Value* C[2] = { Emit(TREE_VALUE(arglist), 0), Emit(TREE_VALUE(TREE_CHAIN(arglist)), 0) }; + if (((DECL_FUNCTION_CODE(fndecl)) == BUILT_IN_FETCH_AND_SUB_1) || + ((DECL_FUNCTION_CODE(fndecl)) == BUILT_IN_FETCH_AND_SUB_2) || + ((DECL_FUNCTION_CODE(fndecl)) == BUILT_IN_FETCH_AND_SUB_4) || + ((DECL_FUNCTION_CODE(fndecl)) == BUILT_IN_FETCH_AND_SUB_8) || + ((DECL_FUNCTION_CODE(fndecl)) == BUILT_IN_FETCH_AND_SUB_16)) + C[1] = Builder.CreateNeg(C[1]); if (C[1]->getType() != Ty) C[1] = Builder.CreateIntCast(C[1], Ty, "cast"); Result = From gohman at apple.com Mon Mar 3 13:41:48 2008 From: gohman at apple.com (Dan Gohman) Date: Mon, 3 Mar 2008 11:41:48 -0800 Subject: [llvm-commits] Fwd: Patch for review: Speeding up ScheduleDAG computations In-Reply-To: References: <2913F98D-C5BD-44BD-A404-5E6DFFEDCFBC@apple.com> <200802291429.22322.dag@cray.com> Message-ID: <48BE0336-D732-4228-96E7-D15B0736B6F3@apple.com> On Mar 3, 2008, at 3:05 AM, Roman Levenstein wrote: > > Please find attached the patch for depth/height calculation. > All of the proposed improvements from the review by Evan and Dan are > incorporated. > > Please have a look at it, and if it is OK, I'll submit. This patch looks good to me; please commit it. I've run a variety of tests here and the output with and without these patches is identical. Thanks for working on this! Dan From criswell at uiuc.edu Mon Mar 3 14:41:07 2008 From: criswell at uiuc.edu (John Criswell) Date: Mon, 03 Mar 2008 20:41:07 -0000 Subject: [llvm-commits] [poolalloc] r47854 - /poolalloc/trunk/include/poolalloc/PoolAllocate.h Message-ID: <200803032041.m23Kf7Zm011138@zion.cs.uiuc.edu> Author: criswell Date: Mon Mar 3 14:41:07 2008 New Revision: 47854 URL: http://llvm.org/viewvc/llvm-project?rev=47854&view=rev Log: Added support for strdup(). Modified: poolalloc/trunk/include/poolalloc/PoolAllocate.h Modified: poolalloc/trunk/include/poolalloc/PoolAllocate.h URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/poolalloc/PoolAllocate.h?rev=47854&r1=47853&r2=47854&view=diff ============================================================================== --- poolalloc/trunk/include/poolalloc/PoolAllocate.h (original) +++ poolalloc/trunk/include/poolalloc/PoolAllocate.h Mon Mar 3 14:41:07 2008 @@ -132,6 +132,7 @@ #endif Constant *PoolInit, *PoolDestroy, *PoolAlloc, *PoolRealloc, *PoolMemAlign; Constant *PoolFree; + Constant *PoolStrdup; #if defined(SAFECODE) || defined(BOUNDS_CHECK) Constant *PoolRegister; #endif From dpatel at apple.com Mon Mar 3 14:42:21 2008 From: dpatel at apple.com (Devang Patel) Date: Mon, 3 Mar 2008 12:42:21 -0800 Subject: [llvm-commits] [llvm] r47848 - in /llvm/trunk/lib/VMCore: Function.cpp Verifier.cpp In-Reply-To: References: <200803031858.m23IwGpW007057@zion.cs.uiuc.edu> Message-ID: <4A6DCB4E-9D0D-40B9-8996-7A04E1CA7815@apple.com> On Mar 3, 2008, at 11:39 AM, Chris Lattner wrote: > > On Mar 3, 2008, at 10:58 AM, Devang Patel wrote: > >> Author: dpatel >> Date: Mon Mar 3 12:58:16 2008 >> New Revision: 47848 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=47848&view=rev >> Log: >> If a function uses multive values in ret instruction then it >> is returning a struct value. > > Why do you want to do this? I think it would make sense to rename > isStructReturn to hasStructRetAttribute() or something, but I don't > think it makes sense to return true if the function returns multiple > results. What does this fix? I did this to preserve the semantics - does function return structure, irrespective how return value is handled ?. If we want to keep this predicate to check sret attr only then I'll rename this as hasStructRetAttribute(). - Devang From criswell at uiuc.edu Mon Mar 3 14:50:33 2008 From: criswell at uiuc.edu (John Criswell) Date: Mon, 03 Mar 2008 20:50:33 -0000 Subject: [llvm-commits] [poolalloc] r47855 - in /poolalloc/trunk/lib/PoolAllocate: PoolAllocate.cpp PoolOptimize.cpp TransformFunctionBody.cpp Message-ID: <200803032050.m23KoXla011502@zion.cs.uiuc.edu> Author: criswell Date: Mon Mar 3 14:50:33 2008 New Revision: 47855 URL: http://llvm.org/viewvc/llvm-project?rev=47855&view=rev Log: Added support for strdup() (which is not automatically inlined on Mac OS X). Fixed the arguments used for poolregister(). Removed unneeded header file from PoolAllocate.cpp. Improved some formatting. Updated bounds checking code to compile correctly. Modified: poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp poolalloc/trunk/lib/PoolAllocate/PoolOptimize.cpp poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp Modified: poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp?rev=47855&r1=47854&r2=47855&view=diff ============================================================================== --- poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp (original) +++ poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp Mon Mar 3 14:50:33 2008 @@ -25,7 +25,6 @@ #include "llvm/Module.h" #include "llvm/Constants.h" #include "llvm/ParamAttrsList.h" -#include "llvm/ParameterAttributes.h" #include "llvm/Support/CFG.h" #include "llvm/Target/TargetData.h" #include "llvm/Transforms/Utils/BasicBlockUtils.h" @@ -215,18 +214,19 @@ Type::Int32Ty, Type::Int32Ty, NULL); + // The poolstrdup function. + PoolStrdup = CurModule->getOrInsertFunction("poolstrdup", + VoidPtrTy, PoolDescPtrTy, + VoidPtrTy, NULL); + // The poolmemalign function. // Get the poolfree function. PoolFree = CurModule->getOrInsertFunction("poolfree", Type::VoidTy, PoolDescPtrTy, VoidPtrTy, NULL); -#ifdef SAFECODE +#if defined(SAFECODE) || defined(BOUNDS_CHECK) //Get the poolregister function PoolRegister = CurModule->getOrInsertFunction("poolregister", Type::VoidTy, - PoolDescPtrTy, Type::Int32Ty, VoidPtrTy, NULL); + PoolDescPtrTy, VoidPtrTy, Type::Int32Ty, NULL); #endif -#ifdef BOUNDS_CHECK - PoolRegister = CurModule->getOrInsertFunction("poolregister", Type::VoidTy, - PoolDescPtrTy, VoidPtrTy, Type::Int32Ty, NULL); -#endif } static void getCallsOf(Constant *C, std::vector &Calls) { @@ -672,11 +672,11 @@ for (DSGraph::node_iterator I = G.node_begin(), E = G.node_end(); I != E;++I){ // We only need to make a pool if there is a heap object in it... DSNode *N = I; - if ( #ifdef BOUNDS_CHECK - (N->isArray() || + if ((N->isArray()) || (N->isHeapNode())) +#else + if (N->isHeapNode()) #endif - (N->isHeapNode())) if (GlobalsGraphNodeMapping.count(N)) { // If it is a global pool, set up the pool descriptor appropriately. DSNode *GGN = GlobalsGraphNodeMapping[N].getNode(); Modified: poolalloc/trunk/lib/PoolAllocate/PoolOptimize.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/PoolOptimize.cpp?rev=47855&r1=47854&r2=47855&view=diff ============================================================================== --- poolalloc/trunk/lib/PoolAllocate/PoolOptimize.cpp (original) +++ poolalloc/trunk/lib/PoolAllocate/PoolOptimize.cpp Mon Mar 3 14:50:33 2008 @@ -51,7 +51,11 @@ bool PoolOptimize::runOnModule(Module &M) { const Type *VoidPtrTy = PointerType::getUnqual(Type::Int8Ty); +#ifdef SAFECODE + const Type *PoolDescPtrTy = PointerType::getUnqual(ArrayType::get(VoidPtrTy, 50)); +#else const Type *PoolDescPtrTy = PointerType::getUnqual(ArrayType::get(VoidPtrTy, 16)); +#endif // Get poolinit function. Modified: poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp?rev=47855&r1=47854&r2=47855&view=diff ============================================================================== --- poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp (original) +++ poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp Mon Mar 3 14:50:33 2008 @@ -68,6 +68,7 @@ void visitCallocCall(CallSite CS); void visitReallocCall(CallSite CS); void visitMemAlignCall(CallSite CS); + void visitStrdupCall(CallSite CS); void visitFreeInst(FreeInst &FI); void visitCallSite(CallSite CS); void visitCallInst(CallInst &CI) { visitCallSite(&CI); } @@ -261,10 +262,16 @@ MI.getOperand(0), "sizetmp", &MI); // TransformAllocationInstr(&MI, AllocSize); + BasicBlock::iterator InsertPt(MI); + ++InsertPt; Instruction *Casted = CastInst::createPointerCast(&MI, PointerType::getUnqual(Type::Int8Ty), - MI.getName()+".casted", MI.getNext()); + MI.getName()+".casted", InsertPt); + std::vector args; + args.push_back (PH); + args.push_back (Casted); + args.push_back (AllocSize); Instruction *V = new CallInst(PAInfo.PoolRegister, - make_vector(PH, Casted, AllocSize, 0), "", Casted->getNext()); + args.begin(), args.end(), "", InsertPt); AddPoolUse(*V, PH, PoolUses); } #endif @@ -464,6 +471,57 @@ I->eraseFromParent(); } +/// visitStrdupCall - Handle strdup(). +/// +void FuncTransform::visitStrdupCall(CallSite CS) { + assert(CS.arg_end()-CS.arg_begin() == 1 && "strdup takes one argument!"); + Instruction *I = CS.getInstruction(); + DSNode *Node = getDSNodeHFor(I).getNode(); + assert (Node && "strdup has NULL DSNode!\n"); + Value *PH = getPoolHandle(I); +#if 0 + assert (PH && "PH for strdup is null!\n"); +#else + if (!PH) { + std::cerr << "strdup: NoPH" << std::endl; + return; + } +#endif + Value *OldPtr = CS.getArgument(0); + + static Type *VoidPtrTy = PointerType::getUnqual(Type::Int8Ty); + if (OldPtr->getType() != VoidPtrTy) + OldPtr = CastInst::createPointerCast(OldPtr, VoidPtrTy, OldPtr->getName(), I); + + std::string Name = I->getName(); I->setName(""); + Value* Opts[3] = {PH, OldPtr, 0}; + Instruction *V = new CallInst(PAInfo.PoolStrdup, Opts, Opts + 2, Name, I); + Instruction *Casted = V; + if (V->getType() != I->getType()) + Casted = CastInst::createPointerCast(V, I->getType(), V->getName(), I); + + // Update def-use info + I->replaceAllUsesWith(Casted); + + // If we are modifying the original function, update the DSGraph. + if (!FI.Clone) { + // V and Casted now point to whatever the original allocation did. + G.getScalarMap().replaceScalar(I, V); + if (V != Casted) + G.getScalarMap()[Casted] = G.getScalarMap()[V]; + } else { // Otherwise, update the NewToOldValueMap + UpdateNewToOldValueMap(I, V, V != Casted ? Casted : 0); + } + + // If this was an invoke, fix up the CFG. + if (InvokeInst *II = dyn_cast(I)) { + new BranchInst(II->getNormalDest(), I); + II->getUnwindDest()->removePredecessor(II->getParent(), true); + } + + // Remove old allocation instruction. + I->eraseFromParent(); +} void FuncTransform::visitCallSite(CallSite CS) { @@ -496,7 +554,10 @@ visitMemAlignCall(CS); return; } else if (CF->getName() == "strdup") { - assert(0 && "strdup should have been linked into the program!"); +#if 1 + visitStrdupCall(CS); +#endif + return; } else if (CF->getName() == "valloc") { std::cerr << "VALLOC USED BUT NOT HANDLED!\n"; abort(); From clattner at apple.com Mon Mar 3 14:51:03 2008 From: clattner at apple.com (Chris Lattner) Date: Mon, 3 Mar 2008 12:51:03 -0800 Subject: [llvm-commits] [llvm] r47848 - in /llvm/trunk/lib/VMCore: Function.cpp Verifier.cpp In-Reply-To: <4A6DCB4E-9D0D-40B9-8996-7A04E1CA7815@apple.com> References: <200803031858.m23IwGpW007057@zion.cs.uiuc.edu> <4A6DCB4E-9D0D-40B9-8996-7A04E1CA7815@apple.com> Message-ID: <7048DA52-B355-4158-A7AB-6069AB011D2A@apple.com> >> Why do you want to do this? I think it would make sense to rename >> isStructReturn to hasStructRetAttribute() or something, but I don't >> think it makes sense to return true if the function returns multiple >> results. What does this fix? > > I did this to preserve the semantics - does function return structure, > irrespective how return value is handled ?. If we want to keep this > predicate to check sret attr only then I'll rename this as > hasStructRetAttribute(). Previous clients of this were safe to assume that the function's first argument was a pointer where the result is returned through. I don't think you want to make this change. -Chris From evan.cheng at apple.com Mon Mar 3 15:26:46 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 3 Mar 2008 13:26:46 -0800 Subject: [llvm-commits] Fwd: Patch for review: Speeding up ScheduleDAG computations In-Reply-To: References: <2913F98D-C5BD-44BD-A404-5E6DFFEDCFBC@apple.com> <200802291429.22322.dag@cray.com> Message-ID: Thanks. Using std::set<> makes me queasy. :-) Too bad it doesn't seem possible to use SmallPtrSet (elements are not in sorted order). Evan On Mar 3, 2008, at 9:58 AM, Dan Gohman wrote: > Hi Roman, > > Just one comment on this patch from me; in this change: > >> SUnit *pop() { >> if (empty()) return NULL; >> - SUnit *V = Queue.top(); >> - Queue.pop(); >> + SUnit *V = *Queue.rbegin(); >> + Queue.erase(V); >> return V; >> } > > The erase call here uses the "key" form of erase, so it incurs a > lookup. This can can be avoided by using the iterator form, > something like this: > > set::iterator i = prior(Queue.end()); > SUnit *V = *i; > Queue.erase(i); > > Dan > > On Mar 3, 2008, at 3:06 AM, Roman Levenstein wrote: > >> Hi, >> >> >> 2008/3/1, Evan Cheng : >> >>> Let's try to solve one problem at a time. >>> >>> 1. Roman's depth / height patch calculation is obviously goodness. >>> Please commit that first. >> >> >> Here is the patch for ScheduleDAGList.cpp: computing priorities using >> a linear algorithm. It uses the same idea as the height/depth >> computation, i.e. dynamic programming. I took into account all >> comments from Dan & Evan from last review. >> >> Additionally, I use now std::set instead of a priority queue. The >> results are exactly the same as with the current SVN version - I >> really compared it side-by-side during execution. Using std::set >> makes >> operations such as removal from the middle of the queue much faster >> and removes a bottleneck. Scheduling of very bigs BBs is now up to >> 3-4 >> times faster. >> >> Please, review this new version, if it is OK for submission. >> >> And there is one more patch to come, for the ScheduleDAGRRList.cpp, >> which would also use std::set instead of priority queues, introduce >> strict ordering and contain queue update changes as David suggested. >> >> -Roman >> < >> ScheduleDAGList.patch>_______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From clattner at apple.com Mon Mar 3 15:31:58 2008 From: clattner at apple.com (Chris Lattner) Date: Mon, 3 Mar 2008 13:31:58 -0800 Subject: [llvm-commits] Fwd: Patch for review: Speeding up ScheduleDAG computations In-Reply-To: References: <2913F98D-C5BD-44BD-A404-5E6DFFEDCFBC@apple.com> <200802291429.22322.dag@cray.com> Message-ID: <522BCA72-6445-4857-BE7B-019B841AA9DB@apple.com> On Mar 3, 2008, at 1:26 PM, Evan Cheng wrote: > Thanks. > > Using std::set<> makes me queasy. :-) Too bad it doesn't seem possible > to use SmallPtrSet (elements are not in sorted order). I'm sad to say that std::set is probably the best thing we have right now that provides priority queue + removal from the middle support. Does anyone know of a better data structure to implement these operations? Even if you don't volunteer to implement it, we can add it to the open projects page. -Chris From dpatel at apple.com Mon Mar 3 15:46:28 2008 From: dpatel at apple.com (Devang Patel) Date: Mon, 03 Mar 2008 21:46:28 -0000 Subject: [llvm-commits] [llvm] r47857 - in /llvm/trunk: include/llvm/Function.h include/llvm/Instructions.h lib/Target/CBackend/CBackend.cpp lib/Target/X86/X86AsmPrinter.cpp lib/Transforms/IPO/DeadArgumentElimination.cpp lib/Transforms/IPO/StructRetPromotion.cpp lib/VMCore/Function.cpp lib/VMCore/Instructions.cpp lib/VMCore/Verifier.cpp Message-ID: <200803032146.m23LkSFJ013597@zion.cs.uiuc.edu> Author: dpatel Date: Mon Mar 3 15:46:28 2008 New Revision: 47857 URL: http://llvm.org/viewvc/llvm-project?rev=47857&view=rev Log: s/isReturnStruct()/hasStructRetAttr()/g Modified: llvm/trunk/include/llvm/Function.h llvm/trunk/include/llvm/Instructions.h llvm/trunk/lib/Target/CBackend/CBackend.cpp llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp llvm/trunk/lib/Transforms/IPO/DeadArgumentElimination.cpp llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp llvm/trunk/lib/VMCore/Function.cpp llvm/trunk/lib/VMCore/Instructions.cpp llvm/trunk/lib/VMCore/Verifier.cpp Modified: llvm/trunk/include/llvm/Function.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Function.h?rev=47857&r1=47856&r2=47857&view=diff ============================================================================== --- llvm/trunk/include/llvm/Function.h (original) +++ llvm/trunk/include/llvm/Function.h Mon Mar 3 15:46:28 2008 @@ -181,8 +181,9 @@ /// @brief Determine if the function does not access or only reads memory. bool onlyReadsMemory() const; - /// @brief Determine if the function returns a structure. - bool isStructReturn() const; + /// @brief Determine if the function returns a structure through first + /// pointer argument. + bool hasStructRetAttr() const; /// deleteBody - This method deletes the body of the function, and converts /// the linkage to external. Modified: llvm/trunk/include/llvm/Instructions.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructions.h?rev=47857&r1=47856&r2=47857&view=diff ============================================================================== --- llvm/trunk/include/llvm/Instructions.h (original) +++ llvm/trunk/include/llvm/Instructions.h Mon Mar 3 15:46:28 2008 @@ -957,8 +957,9 @@ bool doesNotThrow() const; void setDoesNotThrow(bool doesNotThrow = true); - /// @brief Determine if the call returns a structure. - bool isStructReturn() const; + /// @brief Determine if the call returns a structure through first + /// pointer argument. + bool hasStructRetAttr() const; /// @brief Determine if any call argument is an aggregate passed by value. bool hasByValArgument() const; @@ -1769,8 +1770,9 @@ bool doesNotThrow() const; void setDoesNotThrow(bool doesNotThrow = true); - /// @brief Determine if the call returns a structure. - bool isStructReturn() const; + /// @brief Determine if the call returns a structure through first + /// pointer argument. + bool hasStructRetAttr() const; /// getCalledFunction - Return the function called, or null if this is an /// indirect function invocation. Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CBackend.cpp?rev=47857&r1=47856&r2=47857&view=diff ============================================================================== --- llvm/trunk/lib/Target/CBackend/CBackend.cpp (original) +++ llvm/trunk/lib/Target/CBackend/CBackend.cpp Mon Mar 3 15:46:28 2008 @@ -1904,7 +1904,7 @@ void CWriter::printFunctionSignature(const Function *F, bool Prototype) { /// isStructReturn - Should this function actually return a struct by-value? - bool isStructReturn = F->isStructReturn(); + bool isStructReturn = F->hasStructRetAttr(); if (F->hasInternalLinkage()) Out << "static "; if (F->hasDLLImportLinkage()) Out << "__declspec(dllimport) "; @@ -2024,7 +2024,7 @@ void CWriter::printFunction(Function &F) { /// isStructReturn - Should this function actually return a struct by-value? - bool isStructReturn = F.isStructReturn(); + bool isStructReturn = F.hasStructRetAttr(); printFunctionSignature(&F, false); Out << " {\n"; @@ -2148,7 +2148,7 @@ // void CWriter::visitReturnInst(ReturnInst &I) { // If this is a struct return function, return the temporary struct. - bool isStructReturn = I.getParent()->getParent()->isStructReturn(); + bool isStructReturn = I.getParent()->getParent()->hasStructRetAttr(); if (isStructReturn) { Out << " return StructReturn;\n"; @@ -2584,7 +2584,7 @@ // parameter instead of passing it to the call. const ParamAttrsList *PAL = I.getParamAttrs(); bool hasByVal = I.hasByValArgument(); - bool isStructRet = I.isStructReturn(); + bool isStructRet = I.hasStructRetAttr(); if (isStructRet) { writeOperandDeref(I.getOperand(1)); Out << " = "; Modified: llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp?rev=47857&r1=47856&r2=47857&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp Mon Mar 3 15:46:28 2008 @@ -102,13 +102,13 @@ case StdCall: // "Pure" variadic functions do not receive @0 suffix. if (!FT->isVarArg() || (FT->getNumParams() == 0) || - (FT->getNumParams() == 1 && F->isStructReturn())) + (FT->getNumParams() == 1 && F->hasStructRetAttr())) Name += '@' + utostr_32(Info->getBytesToPopOnReturn()); break; case FastCall: // "Pure" variadic functions do not receive @0 suffix. if (!FT->isVarArg() || (FT->getNumParams() == 0) || - (FT->getNumParams() == 1 && F->isStructReturn())) + (FT->getNumParams() == 1 && F->hasStructRetAttr())) Name += '@' + utostr_32(Info->getBytesToPopOnReturn()); if (Name[0] == '_') { Modified: llvm/trunk/lib/Transforms/IPO/DeadArgumentElimination.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/DeadArgumentElimination.cpp?rev=47857&r1=47856&r2=47857&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/DeadArgumentElimination.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/DeadArgumentElimination.cpp Mon Mar 3 15:46:28 2008 @@ -255,7 +255,7 @@ const Function *F = A.getParent(); // If this is the return value of a struct function, it's not really dead. - if (F->isStructReturn() && &*(F->arg_begin()) == &A) + if (F->hasStructRetAttr() && &*(F->arg_begin()) == &A) return Live; if (A.use_empty()) // First check, directly dead? Modified: llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp?rev=47857&r1=47856&r2=47857&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp Mon Mar 3 15:46:28 2008 @@ -75,7 +75,7 @@ return false; // Make sure that function returns struct. - if (F->arg_size() == 0 || !F->isStructReturn() || F->doesNotReturn()) + if (F->arg_size() == 0 || !F->hasStructRetAttr() || F->doesNotReturn()) return false; assert (F->getReturnType() == Type::VoidTy && "Invalid function return type"); Modified: llvm/trunk/lib/VMCore/Function.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Function.cpp?rev=47857&r1=47856&r2=47857&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Function.cpp (original) +++ llvm/trunk/lib/VMCore/Function.cpp Mon Mar 3 15:46:28 2008 @@ -168,10 +168,10 @@ return doesNotAccessMemory() || paramHasAttr(0, ParamAttr::ReadOnly); } -/// @brief Determine if the function returns a structure. -bool Function::isStructReturn() const { - return paramHasAttr(1, ParamAttr::StructRet) - || isa(getReturnType()); +/// @brief Determine if the function returns a structure through first +/// pointer argument. +bool Function::hasStructRetAttr() const { + return paramHasAttr(1, ParamAttr::StructRet); } //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/VMCore/Instructions.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instructions.cpp?rev=47857&r1=47856&r2=47857&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Instructions.cpp (original) +++ llvm/trunk/lib/VMCore/Instructions.cpp Mon Mar 3 15:46:28 2008 @@ -419,8 +419,9 @@ return paramHasAttr(0, ParamAttr::NoUnwind); } -/// @brief Determine if the call returns a structure. -bool CallInst::isStructReturn() const { +/// @brief Determine if the call returns a structure through first +/// pointer argument. +bool CallInst::hasStructRetAttr() const { // Be friendly and also check the callee. return paramHasAttr(1, ParamAttr::StructRet); } @@ -560,8 +561,9 @@ setParamAttrs(PAL); } -/// @brief Determine if the call returns a structure. -bool InvokeInst::isStructReturn() const { +/// @brief Determine if the invoke returns a structure through first +/// pointer argument. +bool InvokeInst::hasStructRetAttr() const { // Be friendly and also check the callee. return paramHasAttr(1, ParamAttr::StructRet); } Modified: llvm/trunk/lib/VMCore/Verifier.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Verifier.cpp?rev=47857&r1=47856&r2=47857&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Verifier.cpp (original) +++ llvm/trunk/lib/VMCore/Verifier.cpp Mon Mar 3 15:46:28 2008 @@ -455,6 +455,9 @@ isa(F.getReturnType()), "Functions cannot return aggregate values!", &F); + Assert1(!F.hasStructRetAttr() || F.getReturnType() == Type::VoidTy, + "Invalid struct return type!", &F); + const ParamAttrsList *Attrs = F.getParamAttrs(); Assert1(!Attrs || From sabre at nondot.org Mon Mar 3 15:59:00 2008 From: sabre at nondot.org (Chris Lattner) Date: Mon, 03 Mar 2008 21:59:00 -0000 Subject: [llvm-commits] [llvm] r47858 - /llvm/trunk/test/CFrontend/2008-03-03-CtorAttrType.c Message-ID: <200803032159.m23Lx0Es014156@zion.cs.uiuc.edu> Author: lattner Date: Mon Mar 3 15:59:00 2008 New Revision: 47858 URL: http://llvm.org/viewvc/llvm-project?rev=47858&view=rev Log: new testcase Added: llvm/trunk/test/CFrontend/2008-03-03-CtorAttrType.c Added: llvm/trunk/test/CFrontend/2008-03-03-CtorAttrType.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CFrontend/2008-03-03-CtorAttrType.c?rev=47858&view=auto ============================================================================== --- llvm/trunk/test/CFrontend/2008-03-03-CtorAttrType.c (added) +++ llvm/trunk/test/CFrontend/2008-03-03-CtorAttrType.c Mon Mar 3 15:59:00 2008 @@ -0,0 +1,6 @@ +// RUN: %llvmgcc %s -S -emit-llvm -o - | grep llvm.global_ctors +int __attribute__((constructor)) foo(void) { + return 0; +} +void __attribute__((constructor)) bar(void) {} + From sabre at nondot.org Mon Mar 3 15:59:25 2008 From: sabre at nondot.org (Chris Lattner) Date: Mon, 03 Mar 2008 21:59:25 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r47859 - /llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Message-ID: <200803032159.m23LxPRx014179@zion.cs.uiuc.edu> Author: lattner Date: Mon Mar 3 15:59:25 2008 New Revision: 47859 URL: http://llvm.org/viewvc/llvm-project?rev=47859&view=rev Log: Fix test/CFrontend/2008-03-03-CtorAttrType.c by forcing all ctor functions to have the same type. Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=47859&r1=47858&r2=47859&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Mon Mar 3 15:59:25 2008 @@ -476,9 +476,17 @@ std::vector InitList; std::vector StructInit; StructInit.resize(2); + + const Type *FPTy = FunctionType::get(Type::VoidTy, std::vector(), + false); + FPTy = PointerType::getUnqual(FPTy); + for (unsigned i = 0, e = Tors.size(); i != e; ++i) { StructInit[0] = ConstantInt::get(Type::Int32Ty, Tors[i].second); - StructInit[1] = Tors[i].first; + + // __attribute__(constructor) can be on a function with any type. Make sure + // the pointer is void()*. + StructInit[1] = ConstantExpr::getBitCast(Tors[i].first, FPTy); InitList.push_back(ConstantStruct::get(StructInit, false)); } Constant *Array = From isanbard at gmail.com Mon Mar 3 16:11:16 2008 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 03 Mar 2008 22:11:16 -0000 Subject: [llvm-commits] [llvm] r47860 - /llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp Message-ID: <200803032211.m23MBGqd014690@zion.cs.uiuc.edu> Author: void Date: Mon Mar 3 16:11:16 2008 New Revision: 47860 URL: http://llvm.org/viewvc/llvm-project?rev=47860&view=rev Log: Multiple instructions can be inserted when eliminating frame indexes. We need the register scavenger to process all of those new instructions instead of just the last one inserted. Modified: llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp Modified: llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp?rev=47860&r1=47859&r2=47860&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp (original) +++ llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp Mon Mar 3 16:11:16 2008 @@ -530,27 +530,44 @@ // Visit the instructions created by eliminateCallFramePseudoInstr(). I = next(PrevI); MI = NULL; - } else if (I->getOpcode() == TargetInstrInfo::DECLARE) + } else if (I->getOpcode() == TargetInstrInfo::DECLARE) { // Ignore it. - I++; - else { - I++; + ++I; + } else { + bool DoIncr = true; + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) if (MI->getOperand(i).isFrameIndex()) { + // Some instructions (e.g. inline asm instructions) can have + // multiple frame indices and/or cause eliminateFrameIndex to insert + // more than one instruction. We need the register scavenger to go + // through all of these instructions so that it can update its + // register information. We keep the iterator at the point before + // insertion so that we can revisit them in full. + bool AtBeginning = (I == BB->begin()); + if (!AtBeginning) --I; + // If this instruction has a FrameIndex operand, we need to use that // target machine register info object to eliminate it. TRI.eliminateFrameIndex(MI, SPAdj, RS); - // Revisit the instruction in full. Some instructions (e.g. inline - // asm instructions) can have multiple frame indices. - --I; + // Reset the iterator if we were at the beginning of the BB. + if (AtBeginning) { + I = BB->begin(); + DoIncr = false; + } + MI = 0; break; } + + if (DoIncr) ++I; } + // Update register states. if (RS && MI) RS->forward(MI); } + assert(SPAdj == 0 && "Unbalanced call frame setup / destroy pairs?"); } } From isanbard at gmail.com Mon Mar 3 16:12:26 2008 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 03 Mar 2008 22:12:26 -0000 Subject: [llvm-commits] [llvm] r47861 - /llvm/trunk/lib/CodeGen/RegisterScavenging.cpp Message-ID: <200803032212.m23MCQRq014745@zion.cs.uiuc.edu> Author: void Date: Mon Mar 3 16:12:25 2008 New Revision: 47861 URL: http://llvm.org/viewvc/llvm-project?rev=47861&view=rev Log: Make the register scavenger update the bookkeeping values for sub/super registers. Modified: llvm/trunk/lib/CodeGen/RegisterScavenging.cpp Modified: llvm/trunk/lib/CodeGen/RegisterScavenging.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterScavenging.cpp?rev=47861&r1=47860&r2=47861&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegisterScavenging.cpp (original) +++ llvm/trunk/lib/CodeGen/RegisterScavenging.cpp Mon Mar 3 16:12:25 2008 @@ -25,6 +25,24 @@ #include "llvm/ADT/STLExtras.h" using namespace llvm; +/// setUsed - Set the register and its sub-registers as being used. +void RegScavenger::setUsed(unsigned Reg) { + RegsAvailable.reset(Reg); + + for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg); + unsigned SubReg = *SubRegs; ++SubRegs) + RegsAvailable.reset(SubReg); +} + +/// setUnused - Set the register and its sub-registers as being unused. +void RegScavenger::setUnused(unsigned Reg) { + RegsAvailable.set(Reg); + + for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg); + unsigned SubReg = *SubRegs; ++SubRegs) + RegsAvailable.set(SubReg); +} + void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) { const MachineFunction &MF = *mbb->getParent(); const TargetMachine &TM = MF.getTarget(); @@ -105,9 +123,10 @@ const MachineOperand &MO = MI->getOperand(i); if (!MO.isRegister() || !MO.isUse()) continue; + unsigned Reg = MO.getReg(); - if (Reg == 0) - continue; + if (Reg == 0) continue; + if (!isUsed(Reg)) { // Register has been scavenged. Restore it! if (Reg != ScavengedReg) @@ -115,9 +134,16 @@ else restoreScavengedReg(); } - if (MO.isKill() && !isReserved(Reg)) + + if (MO.isKill() && !isReserved(Reg)) { ChangedRegs.set(Reg); + + for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg); + unsigned SubReg = *SubRegs; ++SubRegs) + ChangedRegs.set(SubReg); + } } + // Change states of all registers after all the uses are processed to guard // against multiple uses. setUnused(ChangedRegs); @@ -125,19 +151,24 @@ // Process defs. for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI->getOperand(i); + if (!MO.isRegister() || !MO.isDef()) continue; + unsigned Reg = MO.getReg(); + // If it's dead upon def, then it is now free. if (MO.isDead()) { setUnused(Reg); continue; } + // Skip two-address destination operand. if (TID.findTiedToSrcOperand(i) != -1) { assert(isUsed(Reg) && "Using an undefined register!"); continue; } + assert((isUnused(Reg) || isReserved(Reg)) && "Re-defining a live register!"); setUsed(Reg); @@ -177,6 +208,11 @@ continue; assert(isUnused(Reg) || isReserved(Reg)); ChangedRegs.set(Reg); + + // Set the sub-registers as "used". + for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg); + unsigned SubReg = *SubRegs; ++SubRegs) + ChangedRegs.set(SubReg); } setUsed(ChangedRegs); } From isanbard at gmail.com Mon Mar 3 16:14:33 2008 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 03 Mar 2008 22:14:33 -0000 Subject: [llvm-commits] [llvm] r47862 - /llvm/trunk/lib/CodeGen/MachineInstr.cpp Message-ID: <200803032214.m23MEXkF014824@zion.cs.uiuc.edu> Author: void Date: Mon Mar 3 16:14:33 2008 New Revision: 47862 URL: http://llvm.org/viewvc/llvm-project?rev=47862&view=rev Log: Go through the machine instruction's operands to make sure that we're not marking both a super- and sub-register as "killed". This removes implicit uses that are marked as "killed". Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=47862&r1=47861&r2=47862&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Mon Mar 3 16:14:33 2008 @@ -678,34 +678,74 @@ bool MachineInstr::addRegisterKilled(unsigned IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound) { - bool Found = false; - for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { + // Go through the machine instruction's operands to eliminate any potentially + // illegal conditions. I.e., a super- and sub-register both marked "kill". + Restart: + for (unsigned i = 0, e = getNumOperands(); i < e; ++i) { MachineOperand &MO = getOperand(i); + if (MO.isRegister() && MO.isUse()) { unsigned Reg = MO.getReg(); - if (!Reg) + + if (!Reg || IncomingReg == Reg || + !TargetRegisterInfo::isPhysicalRegister(Reg) || + !TargetRegisterInfo::isPhysicalRegister(IncomingReg)) continue; + + if (RegInfo->isSubRegister(IncomingReg, Reg)) { + if (MO.isKill()) { + if (MO.isImplicit()) { + // Remove this implicit use that marks the sub-register "kill". Let + // the super-register take care of this information. + RemoveOperand(i); + goto Restart; // Instruction was modified, redo checking. + } else { + // The super-register is going to take care of this kill + // information. + MO.setIsKill(false); + } + } + } else if (RegInfo->isSuperRegister(IncomingReg, Reg) && MO.isKill()) { + // The kill information is already handled by a super-register. Don't + // add this sub-register as a kill. + return true; + } + } + } + + // If the register already exists, then make sure it or its super-register is + // marked "kill". + for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { + MachineOperand &MO = getOperand(i); + + if (MO.isRegister() && MO.isUse()) { + unsigned Reg = MO.getReg(); + if (!Reg) continue; + if (Reg == IncomingReg) { MO.setIsKill(); - Found = true; - break; + return true; } else if (TargetRegisterInfo::isPhysicalRegister(Reg) && TargetRegisterInfo::isPhysicalRegister(IncomingReg) && RegInfo->isSuperRegister(IncomingReg, Reg) && - MO.isKill()) + MO.isKill()) { // A super-register kill already exists. - Found = true; + return true; + } } } - // If not found, this means an alias of one of the operand is killed. Add a + // If not found, this means an alias of one of the operands is killed. Add a // new implicit operand if required. - if (!Found && AddIfNotFound) { - addOperand(MachineOperand::CreateReg(IncomingReg, false/*IsDef*/, - true/*IsImp*/,true/*IsKill*/)); + if (AddIfNotFound) { + addOperand(MachineOperand::CreateReg(IncomingReg, + false /*IsDef*/, + true /*IsImp*/, + true /*IsKill*/)); return true; } - return Found; + + return false; } bool MachineInstr::addRegisterDead(unsigned IncomingReg, From isanbard at gmail.com Mon Mar 3 16:19:16 2008 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 03 Mar 2008 22:19:16 -0000 Subject: [llvm-commits] [llvm] r47863 - in /llvm/trunk: include/llvm/CodeGen/RegisterScavenging.h lib/Target/PowerPC/PPCInstrInfo.cpp lib/Target/PowerPC/PPCInstrInfo.td lib/Target/PowerPC/PPCMachineFunctionInfo.h lib/Target/PowerPC/PPCRegisterInfo.cpp lib/Target/PowerPC/PPCRegisterInfo.h test/CodeGen/PowerPC/Frames-alloca.ll Message-ID: <200803032219.m23MJG6l015020@zion.cs.uiuc.edu> Author: void Date: Mon Mar 3 16:19:16 2008 New Revision: 47863 URL: http://llvm.org/viewvc/llvm-project?rev=47863&view=rev Log: This is the initial check-in for adding register scavenging to PPC. (Currently, PPC-64 doesn't work.) This also lowers the spilling of the CR registers so that it uses a register other than the default R0 register (the scavenger scrounges for one). A significant part of this patch fixes how kill information is handled. Modified: llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td llvm/trunk/lib/Target/PowerPC/PPCMachineFunctionInfo.h llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h llvm/trunk/test/CodeGen/PowerPC/Frames-alloca.ll Modified: llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h?rev=47863&r1=47862&r2=47863&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h (original) +++ llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h Mon Mar 3 16:19:16 2008 @@ -96,9 +96,9 @@ /// setUsed / setUnused - Mark the state of one or a number of registers. /// - void setUsed(unsigned Reg) { RegsAvailable.reset(Reg); } + void setUsed(unsigned Reg); void setUsed(BitVector Regs) { RegsAvailable &= ~Regs; } - void setUnused(unsigned Reg) { RegsAvailable.set(Reg); } + void setUnused(unsigned Reg); void setUnused(BitVector Regs) { RegsAvailable |= Regs; } /// FindUnusedReg - Find a unused register of the specified register class Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=47863&r1=47862&r2=47863&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Mon Mar 3 16:19:16 2008 @@ -13,6 +13,7 @@ #include "PPCInstrInfo.h" #include "PPCInstrBuilder.h" +#include "PPCMachineFunctionInfo.h" #include "PPCPredicates.h" #include "PPCGenInstrInfo.inc" #include "PPCTargetMachine.h" @@ -316,10 +317,11 @@ } } -static void StoreRegToStackSlot(const TargetInstrInfo &TII, +static bool StoreRegToStackSlot(const TargetInstrInfo &TII, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, - SmallVectorImpl &NewMIs) { + SmallVectorImpl &NewMIs, + bool isPPC64/*FIXME (64-bit): Remove.*/) { if (RC == PPC::GPRCRegisterClass) { if (SrcReg != PPC::LR) { NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW)) @@ -351,22 +353,30 @@ NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STFS)) .addReg(SrcReg, false, false, isKill), FrameIdx)); } else if (RC == PPC::CRRCRegisterClass) { - // FIXME: We use R0 here, because it isn't available for RA. - // We need to store the CR in the low 4-bits of the saved value. First, - // issue a MFCR to save all of the CRBits. - NewMIs.push_back(BuildMI(TII.get(PPC::MFCR), PPC::R0)); + if (!isPPC64) { // FIXME (64-bit): Enable + NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::SPILL_CR)) + .addReg(SrcReg, false, false, isKill), + FrameIdx)); + return true; + } else { + // FIXME: We use R0 here, because it isn't available for RA. We need to + // store the CR in the low 4-bits of the saved value. First, issue a MFCR + // to save all of the CRBits. + NewMIs.push_back(BuildMI(TII.get(PPC::MFCR), PPC::R0)); - // If the saved register wasn't CR0, shift the bits left so that they are in - // CR0's slot. - if (SrcReg != PPC::CR0) { - unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4; - // rlwinm r0, r0, ShiftBits, 0, 31. - NewMIs.push_back(BuildMI(TII.get(PPC::RLWINM), PPC::R0) - .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31)); - } + // If the saved register wasn't CR0, shift the bits left so that they are + // in CR0's slot. + if (SrcReg != PPC::CR0) { + unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4; + // rlwinm r0, r0, ShiftBits, 0, 31. + NewMIs.push_back(BuildMI(TII.get(PPC::RLWINM), PPC::R0) + .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31)); + } - NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW)) - .addReg(PPC::R0, false, false, isKill), FrameIdx)); + NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW)) + .addReg(PPC::R0, false, false, isKill), + FrameIdx)); + } } else if (RC == PPC::VRRCRegisterClass) { // We don't have indexed addressing for vector loads. Emit: // R0 = ADDI FI# @@ -381,26 +391,39 @@ assert(0 && "Unknown regclass!"); abort(); } + + return false; } void PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - unsigned SrcReg, bool isKill, int FrameIdx, - const TargetRegisterClass *RC) const { + MachineBasicBlock::iterator MI, + unsigned SrcReg, bool isKill, int FrameIdx, + const TargetRegisterClass *RC) const { SmallVector NewMIs; - StoreRegToStackSlot(*this, SrcReg, isKill, FrameIdx, RC, NewMIs); + + if (StoreRegToStackSlot(*this, SrcReg, isKill, FrameIdx, RC, NewMIs, + TM.getSubtargetImpl()->isPPC64()/*FIXME (64-bit): Remove.*/)) { + PPCFunctionInfo *FuncInfo = MBB.getParent()->getInfo(); + FuncInfo->setSpillsCR(); + } + for (unsigned i = 0, e = NewMIs.size(); i != e; ++i) MBB.insert(MI, NewMIs[i]); } void PPCInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, - bool isKill, - SmallVectorImpl &Addr, - const TargetRegisterClass *RC, - SmallVectorImpl &NewMIs) const { + bool isKill, + SmallVectorImpl &Addr, + const TargetRegisterClass *RC, + SmallVectorImpl &NewMIs) const{ if (Addr[0].isFrameIndex()) { - StoreRegToStackSlot(*this, SrcReg, isKill, Addr[0].getIndex(), RC, NewMIs); + if (StoreRegToStackSlot(*this, SrcReg, isKill, Addr[0].getIndex(), RC, NewMIs, + TM.getSubtargetImpl()->isPPC64()/*FIXME (64-bit): Remove.*/)) { + PPCFunctionInfo *FuncInfo = MF.getInfo(); + FuncInfo->setSpillsCR(); + } + return; } @@ -495,9 +518,9 @@ void PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - unsigned DestReg, int FrameIdx, - const TargetRegisterClass *RC) const { + MachineBasicBlock::iterator MI, + unsigned DestReg, int FrameIdx, + const TargetRegisterClass *RC) const { SmallVector NewMIs; LoadRegFromStackSlot(*this, DestReg, FrameIdx, RC, NewMIs); for (unsigned i = 0, e = NewMIs.size(); i != e; ++i) @@ -505,9 +528,9 @@ } void PPCInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, - SmallVectorImpl &Addr, - const TargetRegisterClass *RC, - SmallVectorImpl &NewMIs) const{ + SmallVectorImpl &Addr, + const TargetRegisterClass *RC, + SmallVectorImpl &NewMIs)const{ if (Addr[0].isFrameIndex()) { LoadRegFromStackSlot(*this, DestReg, Addr[0].getIndex(), RC, NewMIs); return; Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=47863&r1=47862&r2=47863&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original) +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Mon Mar 3 16:19:16 2008 @@ -371,6 +371,11 @@ []>; } +// SPILL_CR - Indicate that we're dumping the CR register, so we'll need to +// scavenge a register for it. +def SPILL_CR : Pseudo<(outs), (ins GPRC:$cond, memri:$F), + "${:comment} SPILL_CR $cond $F", []>; + let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { let isReturn = 1 in def BLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$p), @@ -380,8 +385,6 @@ def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>; } - - let Defs = [LR] in def MovePCtoLR : Pseudo<(outs), (ins piclabel:$label), "bl $label", []>, PPC970_Unit_BRU; Modified: llvm/trunk/lib/Target/PowerPC/PPCMachineFunctionInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCMachineFunctionInfo.h?rev=47863&r1=47862&r2=47863&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCMachineFunctionInfo.h (original) +++ llvm/trunk/lib/Target/PowerPC/PPCMachineFunctionInfo.h Mon Mar 3 16:19:16 2008 @@ -35,6 +35,9 @@ /// only valid after the initial scan of the function by PEI. bool UsesLR; + /// SpillsCR - Indicates whether CR is spilled in the current function. + bool SpillsCR; + /// LRStoreRequired - The bool indicates whether there is some explicit use of /// the LR/LR8 stack slot that is not obvious from scanning the code. This /// requires that the code generator produce a store of LR to the stack on @@ -42,7 +45,10 @@ bool LRStoreRequired; public: PPCFunctionInfo(MachineFunction &MF) - : FramePointerSaveIndex(0), ReturnAddrSaveIndex(0), LRStoreRequired(false){} + : FramePointerSaveIndex(0), + ReturnAddrSaveIndex(0), + SpillsCR(false), + LRStoreRequired(false) {} int getFramePointerSaveIndex() const { return FramePointerSaveIndex; } void setFramePointerSaveIndex(int Idx) { FramePointerSaveIndex = Idx; } @@ -57,9 +63,11 @@ void setUsesLR(bool U) { UsesLR = U; } bool usesLR() const { return UsesLR; } + void setSpillsCR() { SpillsCR = true; } + bool isCRSpilled() const { return SpillsCR; } + void setLRStoreRequired() { LRStoreRequired = true; } bool isLRStoreRequired() const { return LRStoreRequired; } - }; } // end of namespace llvm Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=47863&r1=47862&r2=47863&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Mon Mar 3 16:19:16 2008 @@ -28,6 +28,7 @@ #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineLocation.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/RegisterScavenging.h" #include "llvm/CodeGen/SelectionDAGNodes.h" #include "llvm/Target/TargetFrameInfo.h" #include "llvm/Target/TargetInstrInfo.h" @@ -41,6 +42,12 @@ #include using namespace llvm; +// FIXME (64-bit): Should be inlined. +bool +PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const { + return !Subtarget.isPPC64(); +} + /// getRegisterNumbering - Given the enum value for some register, e.g. /// PPC::F14, return the number that it corresponds to (e.g. 14). unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) { @@ -280,23 +287,40 @@ return NoFramePointerElim || MFI->hasVarSizedObjects(); } +static bool spillsCR(const MachineFunction &MF) { + const PPCFunctionInfo *FuncInfo = MF.getInfo(); + return FuncInfo->isCRSpilled(); +} + BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { BitVector Reserved(getNumRegs()); Reserved.set(PPC::R0); Reserved.set(PPC::R1); Reserved.set(PPC::LR); + Reserved.set(PPC::LR8); + // In Linux, r2 is reserved for the OS. if (!Subtarget.isDarwin()) Reserved.set(PPC::R2); - // On PPC64, r13 is the thread pointer. Never allocate this register. - // Note that this is overconservative, as it also prevents allocation of - // R31 when the FP is not needed. + + // On PPC64, r13 is the thread pointer. Never allocate this register. Note + // that this is over conservative, as it also prevents allocation of R31 when + // the FP is not needed. if (Subtarget.isPPC64()) { Reserved.set(PPC::R13); Reserved.set(PPC::R31); + + Reserved.set(PPC::R0); // FIXME (64-bit): Remove + + Reserved.set(PPC::X0); + Reserved.set(PPC::X1); + Reserved.set(PPC::X13); + Reserved.set(PPC::X31); } + if (needsFP(MF)) Reserved.set(PPC::R31); + return Reserved; } @@ -333,14 +357,29 @@ MBB.erase(I); } -/// LowerDynamicAlloc - Generate the code for allocating an object in the +/// findScratchRegister - Find a 'free' PPC register. Try for a call-clobbered +/// register first and then a spilled callee-saved register if that fails. +static +unsigned findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS, + const TargetRegisterClass *RC, int SPAdj) { + assert(RS && "Register scavenging must be on"); + unsigned Reg = RS->FindUnusedReg(RC, true); + // FIXME: move ARM callee-saved reg scan to target independent code, then + // search for already spilled CS register here. + if (Reg == 0) + Reg = RS->scavengeRegister(RC, II, SPAdj); + return Reg; +} + +/// lowerDynamicAlloc - Generate the code for allocating an object in the /// current frame. The sequence of code with be in the general form /// /// addi R0, SP, #frameSize ; get the address of the previous frame /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size /// addi Rnew, SP, #maxCalFrameSize ; get the top of the allocation /// -void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const { +void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II, + int SPAdj, RegScavenger *RS) const { // Get the instruction. MachineInstr &MI = *II; // Get the instruction's basic block. @@ -369,44 +408,128 @@ // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. // Constructing the constant and adding would take 3 instructions. // Fortunately, a frame greater than 32K is rare. + const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; + const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; + const TargetRegisterClass *RC = LP64 ? G8RC : GPRC; + + // FIXME (64-bit): Use "findScratchRegister" + unsigned Reg; + if (!LP64) + Reg = findScratchRegister(II, RS, RC, SPAdj); + else + Reg = PPC::R0; + if (MaxAlign < TargetAlign && isInt16(FrameSize)) { - BuildMI(MBB, II, TII.get(PPC::ADDI), PPC::R0) + BuildMI(MBB, II, TII.get(PPC::ADDI), Reg) .addReg(PPC::R31) .addImm(FrameSize); } else if (LP64) { - BuildMI(MBB, II, TII.get(PPC::LD), PPC::X0) + Reg = PPC::X0; // FIXME (64-bit): Remove. + BuildMI(MBB, II, TII.get(PPC::LD), Reg) .addImm(0) .addReg(PPC::X1); } else { - BuildMI(MBB, II, TII.get(PPC::LWZ), PPC::R0) + BuildMI(MBB, II, TII.get(PPC::LWZ), Reg) .addImm(0) .addReg(PPC::R1); } - // Grow the stack and update the stack pointer link, then - // determine the address of new allocated space. + // Grow the stack and update the stack pointer link, then determine the + // address of new allocated space. if (LP64) { +#if 0 // FIXME (64-bit): Enable BuildMI(MBB, II, TII.get(PPC::STDUX)) - .addReg(PPC::X0) + .addReg(Reg, false, false, true) .addReg(PPC::X1) .addReg(MI.getOperand(1).getReg()); - BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) +#else + BuildMI(MBB, II, TII.get(PPC::STDUX)) + .addReg(PPC::X0, false, false, true) .addReg(PPC::X1) - .addImm(maxCallFrameSize); + .addReg(MI.getOperand(1).getReg()); +#endif + + if (!MI.getOperand(1).isKill()) + BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) + .addReg(PPC::X1) + .addImm(maxCallFrameSize); + else + // Implicitly kill the register. + BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) + .addReg(PPC::X1) + .addImm(maxCallFrameSize) + .addReg(MI.getOperand(1).getReg(), false, true, true); } else { BuildMI(MBB, II, TII.get(PPC::STWUX)) - .addReg(PPC::R0) + .addReg(Reg, false, false, true) .addReg(PPC::R1) .addReg(MI.getOperand(1).getReg()); - BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) - .addReg(PPC::R1) - .addImm(maxCallFrameSize); + + if (!MI.getOperand(1).isKill()) + BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) + .addReg(PPC::R1) + .addImm(maxCallFrameSize); + else + // Implicitly kill the register. + BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) + .addReg(PPC::R1) + .addImm(maxCallFrameSize) + .addReg(MI.getOperand(1).getReg(), false, true, true); } // Discard the DYNALLOC instruction. MBB.erase(II); } +/// lowerCRSpilling - Generate the code for spilling a CR register. Instead of +/// reserving a whole register (R0), we scrounge for one here. This generates +/// code like this: +/// +/// mfcr rA ; Move the conditional register into GPR rA. +/// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot. +/// stw rA, FI ; Store rA to the frame. +/// +void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, + unsigned FrameIndex, int SPAdj, + RegScavenger *RS) const { + // Get the instruction. + MachineInstr &MI = *II; // ; SPILL_CR , , + // Get the instruction's basic block. + MachineBasicBlock &MBB = *MI.getParent(); + + const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; + const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; + const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC; + unsigned Reg = findScratchRegister(II, RS, RC, SPAdj); + + // We need to store the CR in the low 4-bits of the saved value. First, issue + // an MFCR to save all of the CRBits. + if (!MI.getOperand(0).isKill()) + BuildMI(MBB, II, TII.get(PPC::MFCR), Reg); + else + // Implicitly kill the CR register. + BuildMI(MBB, II, TII.get(PPC::MFCR), Reg) + .addReg(MI.getOperand(0).getReg(), false, true, true); + + // If the saved register wasn't CR0, shift the bits left so that they are in + // CR0's slot. + unsigned SrcReg = MI.getOperand(0).getReg(); + if (SrcReg != PPC::CR0) + // rlwinm rA, rA, ShiftBits, 0, 31. + BuildMI(MBB, II, TII.get(PPC::RLWINM), Reg) + .addReg(Reg, false, false, true) + .addImm(PPCRegisterInfo::getRegisterNumbering(SrcReg) * 4) + .addImm(0) + .addImm(31); + + addFrameReference(BuildMI(MBB, II, TII.get(PPC::STW)) + .addReg(Reg, false, false, MI.getOperand(1).getImm()), + FrameIndex); + + // Discard the pseudo instruction. + MBB.erase(II); +} + void PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, RegScavenger *RS) const { assert(SPAdj == 0 && "Unexpected"); @@ -431,10 +554,10 @@ unsigned OffsetOperandNo = (FIOperandNo == 2) ? 1 : 2; if (MI.getOpcode() == TargetInstrInfo::INLINEASM) OffsetOperandNo = FIOperandNo-1; - + // Get the frame index. int FrameIndex = MI.getOperand(FIOperandNo).getIndex(); - + // Get the frame pointer save index. Users of this index are primarily // DYNALLOC instructions. PPCFunctionInfo *FI = MF.getInfo(); @@ -445,7 +568,14 @@ // Special case for dynamic alloca. if (FPSI && FrameIndex == FPSI && (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { - lowerDynamicAlloc(II); + lowerDynamicAlloc(II, SPAdj, RS); + return; + } + + // Special case for pseudo-op SPILL_CR. + if (!Subtarget.isPPC64()) // FIXME (64-bit): Remove. + if (OpC == PPC::SPILL_CR) { + lowerCRSpilling(II, FrameIndex, SPAdj, RS); return; } @@ -490,15 +620,31 @@ MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); return; } - - // Insert a set of r0 with the full offset value before the ld, st, or add - BuildMI(MBB, II, TII.get(PPC::LIS), PPC::R0).addImm(Offset >> 16); - BuildMI(MBB, II, TII.get(PPC::ORI), PPC::R0).addReg(PPC::R0).addImm(Offset); - - // Convert into indexed form of the instruction - // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 - // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 + + // The offset doesn't fit into a single register, scavenge one to build the + // offset in. + // FIXME: figure out what SPAdj is doing here. + + // FIXME (64-bit): Use "findScratchRegister". + unsigned SReg; + if (!Subtarget.isPPC64()) + SReg = findScratchRegister(II, RS, &PPC::GPRCRegClass, SPAdj); + else + SReg = PPC::R0; + + // Insert a set of rA with the full offset value before the ld, st, or add + BuildMI(MBB, II, TII.get(PPC::LIS), SReg) + .addImm(Offset >> 16); + BuildMI(MBB, II, TII.get(PPC::ORI), SReg) + .addReg(SReg, false, false, true) + .addImm(Offset); + + // Convert into indexed form of the instruction: + // + // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 + // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 unsigned OperandBase; + if (OpC != TargetInstrInfo::INLINEASM) { assert(ImmToIdxMap.count(OpC) && "No indexed form of load or store available!"); @@ -511,7 +657,7 @@ unsigned StackReg = MI.getOperand(FIOperandNo).getReg(); MI.getOperand(OperandBase).ChangeToRegister(StackReg, false); - MI.getOperand(OperandBase+1).ChangeToRegister(PPC::R0, false); + MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false); } /// VRRegNo - Map from a numbered VR register to its enum value. @@ -598,24 +744,47 @@ UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. } - unsigned SrcReg = MI->getOperand(1).getReg(); - unsigned DstReg = MI->getOperand(0).getReg(); // If no registers are used, turn this into a copy. if (UsedRegMask == 0) { // Remove all VRSAVE code. RemoveVRSaveCode(MI); return; - } else if ((UsedRegMask & 0xFFFF) == UsedRegMask) { - BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg) - .addReg(SrcReg).addImm(UsedRegMask); + } + + unsigned SrcReg = MI->getOperand(1).getReg(); + unsigned DstReg = MI->getOperand(0).getReg(); + + if ((UsedRegMask & 0xFFFF) == UsedRegMask) { + if (DstReg != SrcReg) + BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg) + .addReg(SrcReg) + .addImm(UsedRegMask); + else + BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg) + .addReg(SrcReg, false, false, true) + .addImm(UsedRegMask); } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { - BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) - .addReg(SrcReg).addImm(UsedRegMask >> 16); + if (DstReg != SrcReg) + BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) + .addReg(SrcReg) + .addImm(UsedRegMask >> 16); + else + BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) + .addReg(SrcReg, false, false, true) + .addImm(UsedRegMask >> 16); } else { - BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) - .addReg(SrcReg).addImm(UsedRegMask >> 16); + if (DstReg != SrcReg) + BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) + .addReg(SrcReg) + .addImm(UsedRegMask >> 16); + else + BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) + .addReg(SrcReg, false, false, true) + .addImm(UsedRegMask >> 16); + BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg) - .addReg(DstReg).addImm(UsedRegMask & 0xFFFF); + .addReg(DstReg, false, false, true) + .addImm(UsedRegMask & 0xFFFF); } // Remove the old UPDATE_VRSAVE instruction. @@ -675,9 +844,9 @@ MFI->setStackSize(FrameSize); } -void PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, - RegScavenger *RS) - const { +void +PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, + RegScavenger *RS) const { // Save and clear the LR state. PPCFunctionInfo *FI = MF.getInfo(); unsigned LR = getRARegister(); @@ -689,7 +858,7 @@ bool IsPPC64 = Subtarget.isPPC64(); bool IsELF32_ABI = Subtarget.isELF32_ABI(); bool IsMachoABI = Subtarget.isMachoABI(); - const MachineFrameInfo *MFI = MF.getFrameInfo(); + MachineFrameInfo *MFI = MF.getFrameInfo(); // If the frame pointer save index hasn't been defined yet. if (!FPSI && (NoFramePointerElim || MFI->hasVarSizedObjects()) && @@ -703,9 +872,25 @@ FI->setFramePointerSaveIndex(FPSI); } + // Reserve a slot closest to SP or frame pointer if we have a dynalloc or + // a large stack, which will require scavenging a register to materialize a + // large offset. + // FIXME: this doesn't actually check stack size, so is a bit pessimistic + // FIXME: doesn't detect whether or not we need to spill vXX, which requires + // r0 for now. + + if (!IsPPC64) // FIXME (64-bit): Enable. + if (needsFP(MF) || spillsCR(MF)) { + const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; + const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; + const TargetRegisterClass *RC = IsPPC64 ? G8RC : GPRC; + RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), + RC->getAlignment())); + } } -void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const { +void +PPCRegisterInfo::emitPrologue(MachineFunction &MF) const { MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB MachineBasicBlock::iterator MBBI = MBB.begin(); MachineFrameInfo *MFI = MF.getFrameInfo(); @@ -713,7 +898,7 @@ // Prepare for frame info. unsigned FrameLabelId = 0; - + // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, // process it. for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { @@ -725,7 +910,7 @@ // Move MBBI back to the beginning of the function. MBBI = MBB.begin(); - + // Work out frame sizes. determineFrameLayout(MF); unsigned FrameSize = MFI->getStackSize(); @@ -743,29 +928,37 @@ int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI); int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI); - + if (IsPPC64) { if (UsesLR) BuildMI(MBB, MBBI, TII.get(PPC::MFLR8), PPC::X0); if (HasFP) BuildMI(MBB, MBBI, TII.get(PPC::STD)) - .addReg(PPC::X31).addImm(FPOffset/4).addReg(PPC::X1); + .addReg(PPC::X31) + .addImm(FPOffset/4) + .addReg(PPC::X1); if (UsesLR) BuildMI(MBB, MBBI, TII.get(PPC::STD)) - .addReg(PPC::X0).addImm(LROffset/4).addReg(PPC::X1); + .addReg(PPC::X0) + .addImm(LROffset / 4) + .addReg(PPC::X1); } else { if (UsesLR) BuildMI(MBB, MBBI, TII.get(PPC::MFLR), PPC::R0); if (HasFP) BuildMI(MBB, MBBI, TII.get(PPC::STW)) - .addReg(PPC::R31).addImm(FPOffset).addReg(PPC::R1); + .addReg(PPC::R31) + .addImm(FPOffset) + .addReg(PPC::R1); if (UsesLR) BuildMI(MBB, MBBI, TII.get(PPC::STW)) - .addReg(PPC::R0).addImm(LROffset).addReg(PPC::R1); + .addReg(PPC::R0) + .addImm(LROffset) + .addReg(PPC::R1); } // Skip if a leaf routine. @@ -788,40 +981,65 @@ if (MaxAlign > TargetAlign) { assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!"); assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!"); + BuildMI(MBB, MBBI, TII.get(PPC::RLWINM), PPC::R0) - .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31); - BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC) ,PPC::R0).addReg(PPC::R0) + .addReg(PPC::R1) + .addImm(0) + .addImm(32 - Log2_32(MaxAlign)) + .addImm(31); + BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC) ,PPC::R0) + .addReg(PPC::R0, false, false, true) .addImm(NegFrameSize); BuildMI(MBB, MBBI, TII.get(PPC::STWUX)) - .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0); + .addReg(PPC::R1) + .addReg(PPC::R1) + .addReg(PPC::R0); } else if (isInt16(NegFrameSize)) { - BuildMI(MBB, MBBI, TII.get(PPC::STWU), - PPC::R1).addReg(PPC::R1).addImm(NegFrameSize).addReg(PPC::R1); + BuildMI(MBB, MBBI, TII.get(PPC::STWU), PPC::R1) + .addReg(PPC::R1) + .addImm(NegFrameSize) + .addReg(PPC::R1); } else { - BuildMI(MBB, MBBI, TII.get(PPC::LIS), PPC::R0).addImm(NegFrameSize >> 16); - BuildMI(MBB, MBBI, TII.get(PPC::ORI), PPC::R0).addReg(PPC::R0) + BuildMI(MBB, MBBI, TII.get(PPC::LIS), PPC::R0) + .addImm(NegFrameSize >> 16); + BuildMI(MBB, MBBI, TII.get(PPC::ORI), PPC::R0) + .addReg(PPC::R0, false, false, true) .addImm(NegFrameSize & 0xFFFF); - BuildMI(MBB, MBBI, TII.get(PPC::STWUX)).addReg(PPC::R1).addReg(PPC::R1) + BuildMI(MBB, MBBI, TII.get(PPC::STWUX)) + .addReg(PPC::R1) + .addReg(PPC::R1) .addReg(PPC::R0); } } else { // PPC64. if (MaxAlign > TargetAlign) { assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!"); assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!"); + BuildMI(MBB, MBBI, TII.get(PPC::RLDICL), PPC::X0) - .addReg(PPC::X1).addImm(0).addImm(64-Log2_32(MaxAlign)); - BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC8), PPC::X0).addReg(PPC::X0) + .addReg(PPC::X1) + .addImm(0) + .addImm(64 - Log2_32(MaxAlign)); + BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC8), PPC::X0) + .addReg(PPC::X0) .addImm(NegFrameSize); BuildMI(MBB, MBBI, TII.get(PPC::STDUX)) - .addReg(PPC::X1).addReg(PPC::X1).addReg(PPC::X0); + .addReg(PPC::X1) + .addReg(PPC::X1) + .addReg(PPC::X0); } else if (isInt16(NegFrameSize)) { BuildMI(MBB, MBBI, TII.get(PPC::STDU), PPC::X1) - .addReg(PPC::X1).addImm(NegFrameSize/4).addReg(PPC::X1); + .addReg(PPC::X1) + .addImm(NegFrameSize / 4) + .addReg(PPC::X1); } else { - BuildMI(MBB, MBBI, TII.get(PPC::LIS8), PPC::X0).addImm(NegFrameSize >>16); - BuildMI(MBB, MBBI, TII.get(PPC::ORI8), PPC::X0).addReg(PPC::X0) + BuildMI(MBB, MBBI, TII.get(PPC::LIS8), PPC::X0) + .addImm(NegFrameSize >> 16); + BuildMI(MBB, MBBI, TII.get(PPC::ORI8), PPC::X0) + .addReg(PPC::X0, false, false, true) .addImm(NegFrameSize & 0xFFFF); - BuildMI(MBB, MBBI, TII.get(PPC::STDUX)).addReg(PPC::X1).addReg(PPC::X1) + BuildMI(MBB, MBBI, TII.get(PPC::STDUX)) + .addReg(PPC::X1) + .addReg(PPC::X1) .addReg(PPC::X0); } } @@ -873,10 +1091,12 @@ // If there is a frame pointer, copy R1 into R31 if (HasFP) { if (!IsPPC64) { - BuildMI(MBB, MBBI, TII.get(PPC::OR), PPC::R31).addReg(PPC::R1) + BuildMI(MBB, MBBI, TII.get(PPC::OR), PPC::R31) + .addReg(PPC::R1) .addReg(PPC::R1); } else { - BuildMI(MBB, MBBI, TII.get(PPC::OR8), PPC::X31).addReg(PPC::X1) + BuildMI(MBB, MBBI, TII.get(PPC::OR8), PPC::X31) + .addReg(PPC::X1) .addReg(PPC::X1); } } Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h?rev=47863&r1=47862&r2=47863&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h (original) +++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h Mon Mar 3 16:19:16 2008 @@ -51,13 +51,20 @@ /// time). bool targetHandlesStackFrameRounding() const { return true; } + /// requiresRegisterScavenging - We require a register scavenger. + /// FIXME (64-bit): Should be inlined. + bool requiresRegisterScavenging(const MachineFunction &MF) const; + bool hasFP(const MachineFunction &MF) const; void eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const; - void lowerDynamicAlloc(MachineBasicBlock::iterator II) const; + void lowerDynamicAlloc(MachineBasicBlock::iterator II, + int SPAdj, RegScavenger *RS) const; + void lowerCRSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex, + int SPAdj, RegScavenger *RS) const; void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, RegScavenger *RS = NULL) const; Modified: llvm/trunk/test/CodeGen/PowerPC/Frames-alloca.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/Frames-alloca.ll?rev=47863&r1=47862&r2=47863&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/PowerPC/Frames-alloca.ll (original) +++ llvm/trunk/test/CodeGen/PowerPC/Frames-alloca.ll Mon Mar 3 16:19:16 2008 @@ -1,7 +1,7 @@ ; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | \ ; RUN: grep {stw r31, 20(r1)} ; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | \ -; RUN: grep {stwu r1, -64(r1)} +; RUN: grep {stwu r1, -80(r1)} ; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | \ ; RUN: grep {lwz r1, 0(r1)} ; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | \ @@ -9,7 +9,7 @@ ; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | \ ; RUN: grep {stw r31, 20(r1)} ; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | \ -; RUN: grep {stwu r1, -64(r1)} +; RUN: grep {stwu r1, -80(r1)} ; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | \ ; RUN: grep {lwz r1, 0(r1)} ; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | \ From gohman at apple.com Mon Mar 3 16:20:46 2008 From: gohman at apple.com (Dan Gohman) Date: Mon, 03 Mar 2008 22:20:46 -0000 Subject: [llvm-commits] [llvm] r47864 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <200803032220.m23MKkZm015081@zion.cs.uiuc.edu> Author: djg Date: Mon Mar 3 16:20:46 2008 New Revision: 47864 URL: http://llvm.org/viewvc/llvm-project?rev=47864&view=rev Log: More APInt-ification. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=47864&r1=47863&r2=47864&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Mar 3 16:20:46 2008 @@ -5760,9 +5760,10 @@ Hi = DAG.getNode(ISD::UNDEF, NVT); break; case ISD::Constant: { - uint64_t Cst = cast(Node)->getValue(); - Lo = DAG.getConstant(Cst, NVT); - Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT); + unsigned NVTBits = MVT::getSizeInBits(NVT); + const APInt &Cst = cast(Node)->getAPIntValue(); + Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT); + Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT); break; } case ISD::ConstantFP: { From gohman at apple.com Mon Mar 3 16:22:10 2008 From: gohman at apple.com (Dan Gohman) Date: Mon, 03 Mar 2008 22:22:10 -0000 Subject: [llvm-commits] [llvm] r47865 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <200803032222.m23MMAdA015134@zion.cs.uiuc.edu> Author: djg Date: Mon Mar 3 16:22:09 2008 New Revision: 47865 URL: http://llvm.org/viewvc/llvm-project?rev=47865&view=rev Log: Add support for lowering i64 SRA_PARTS and friends on x86-64. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=47865&r1=47864&r2=47865&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Mar 3 16:22:09 2008 @@ -276,6 +276,11 @@ setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); + if (Subtarget->is64Bit()) { + setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom); + setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom); + setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom); + } // X86 wants to expand memset / memcpy itself. setOperationAction(ISD::MEMSET , MVT::Other, Custom); setOperationAction(ISD::MEMCPY , MVT::Other, Custom); @@ -4087,64 +4092,65 @@ /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and /// take a 2 x i32 value to shift plus a shift amount. SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) { - assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 && - "Not an i64 shift!"); + assert(Op.getNumOperands() == 3 && "Not a double-shift!"); + MVT::ValueType VT = Op.getValueType(); + unsigned VTBits = MVT::getSizeInBits(VT); bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; SDOperand ShOpLo = Op.getOperand(0); SDOperand ShOpHi = Op.getOperand(1); SDOperand ShAmt = Op.getOperand(2); SDOperand Tmp1 = isSRA ? - DAG.getNode(ISD::SRA, MVT::i32, ShOpHi, DAG.getConstant(31, MVT::i8)) : - DAG.getConstant(0, MVT::i32); + DAG.getNode(ISD::SRA, VT, ShOpHi, DAG.getConstant(VTBits - 1, MVT::i8)) : + DAG.getConstant(0, VT); SDOperand Tmp2, Tmp3; if (Op.getOpcode() == ISD::SHL_PARTS) { - Tmp2 = DAG.getNode(X86ISD::SHLD, MVT::i32, ShOpHi, ShOpLo, ShAmt); - Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, ShOpLo, ShAmt); + Tmp2 = DAG.getNode(X86ISD::SHLD, VT, ShOpHi, ShOpLo, ShAmt); + Tmp3 = DAG.getNode(ISD::SHL, VT, ShOpLo, ShAmt); } else { - Tmp2 = DAG.getNode(X86ISD::SHRD, MVT::i32, ShOpLo, ShOpHi, ShAmt); - Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, MVT::i32, ShOpHi, ShAmt); + Tmp2 = DAG.getNode(X86ISD::SHRD, VT, ShOpLo, ShOpHi, ShAmt); + Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, VT, ShOpHi, ShAmt); } const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag); SDOperand AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt, - DAG.getConstant(32, MVT::i8)); - SDOperand Cond = DAG.getNode(X86ISD::CMP, MVT::i32, + DAG.getConstant(VTBits, MVT::i8)); + SDOperand Cond = DAG.getNode(X86ISD::CMP, VT, AndNode, DAG.getConstant(0, MVT::i8)); SDOperand Hi, Lo; SDOperand CC = DAG.getConstant(X86::COND_NE, MVT::i8); - VTs = DAG.getNodeValueTypes(MVT::i32, MVT::Flag); + VTs = DAG.getNodeValueTypes(VT, MVT::Flag); SmallVector Ops; if (Op.getOpcode() == ISD::SHL_PARTS) { Ops.push_back(Tmp2); Ops.push_back(Tmp3); Ops.push_back(CC); Ops.push_back(Cond); - Hi = DAG.getNode(X86ISD::CMOV, MVT::i32, &Ops[0], Ops.size()); + Hi = DAG.getNode(X86ISD::CMOV, VT, &Ops[0], Ops.size()); Ops.clear(); Ops.push_back(Tmp3); Ops.push_back(Tmp1); Ops.push_back(CC); Ops.push_back(Cond); - Lo = DAG.getNode(X86ISD::CMOV, MVT::i32, &Ops[0], Ops.size()); + Lo = DAG.getNode(X86ISD::CMOV, VT, &Ops[0], Ops.size()); } else { Ops.push_back(Tmp2); Ops.push_back(Tmp3); Ops.push_back(CC); Ops.push_back(Cond); - Lo = DAG.getNode(X86ISD::CMOV, MVT::i32, &Ops[0], Ops.size()); + Lo = DAG.getNode(X86ISD::CMOV, VT, &Ops[0], Ops.size()); Ops.clear(); Ops.push_back(Tmp3); Ops.push_back(Tmp1); Ops.push_back(CC); Ops.push_back(Cond); - Hi = DAG.getNode(X86ISD::CMOV, MVT::i32, &Ops[0], Ops.size()); + Hi = DAG.getNode(X86ISD::CMOV, VT, &Ops[0], Ops.size()); } - VTs = DAG.getNodeValueTypes(MVT::i32, MVT::i32); + VTs = DAG.getNodeValueTypes(VT, VT); Ops.clear(); Ops.push_back(Lo); Ops.push_back(Hi); From gohman at apple.com Mon Mar 3 16:22:56 2008 From: gohman at apple.com (Dan Gohman) Date: Mon, 03 Mar 2008 22:22:56 -0000 Subject: [llvm-commits] [llvm] r47866 - /llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Message-ID: <200803032222.m23MMv2F015165@zion.cs.uiuc.edu> Author: djg Date: Mon Mar 3 16:22:56 2008 New Revision: 47866 URL: http://llvm.org/viewvc/llvm-project?rev=47866&view=rev Log: More APInt-ification. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=47866&r1=47865&r2=47866&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Mon Mar 3 16:22:56 2008 @@ -1070,7 +1070,7 @@ } if (ConstantSDNode *N1C = dyn_cast(N1.Val)) { - uint64_t C1 = N1C->getValue(); + const APInt &C1 = N1C->getAPIntValue(); if (isa(N0.Val)) { return DAG.FoldSetCC(VT, N0, N1, Cond); } else { @@ -1104,8 +1104,8 @@ // If the comparison constant has bits in the upper part, the // zero-extended value could never match. - if (C1 & (~0ULL << InSize)) { - unsigned VSize = MVT::getSizeInBits(N0.getValueType()); + if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(), + C1.getBitWidth() - InSize))) { switch (Cond) { case ISD::SETUGT: case ISD::SETUGE: @@ -1116,11 +1116,11 @@ case ISD::SETGT: case ISD::SETGE: // True if the sign bit of C1 is set. - return DAG.getConstant((C1 & (1ULL << (VSize-1))) != 0, VT); + return DAG.getConstant(C1.isNegative(), VT); case ISD::SETLT: case ISD::SETLE: // True if the sign bit of C1 isn't set. - return DAG.getConstant((C1 & (1ULL << (VSize-1))) == 0, VT); + return DAG.getConstant(C1.isNonNegative(), VT); default: break; } @@ -1135,7 +1135,8 @@ case ISD::SETULT: case ISD::SETULE: return DAG.getSetCC(VT, N0.getOperand(0), - DAG.getConstant(C1, N0.getOperand(0).getValueType()), + DAG.getConstant(APInt(C1).trunc(InSize), + N0.getOperand(0).getValueType()), Cond); default: break; // todo, be more careful with signed comparisons @@ -1150,8 +1151,8 @@ // If the extended part has any inconsistent bits, it cannot ever // compare equal. In other words, they have to be all ones or all // zeros. - uint64_t ExtBits = - (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1)); + APInt ExtBits = + APInt::getHighBitsSet(ExtDstTyBits, ExtDstTyBits - ExtSrcTyBits); if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) return DAG.getConstant(Cond == ISD::SETNE, VT); @@ -1168,10 +1169,12 @@ DCI.AddToWorklist(ZextOp.Val); // Otherwise, make this a use of a zext. return DAG.getSetCC(VT, ZextOp, - DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)), + DAG.getConstant(C1 & APInt::getLowBitsSet( + ExtDstTyBits, + ExtSrcTyBits), ExtDstTy), Cond); - } else if ((N1C->getValue() == 0 || N1C->getValue() == 1) && + } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) && (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC @@ -1233,15 +1236,15 @@ // Canonicalize GE/LE comparisons to use GT/LT comparisons. if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true - --C1; // X >= C0 --> X > (C0-1) - return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), + // X >= C0 --> X > (C0-1) + return DAG.getSetCC(VT, N0, DAG.getConstant(C1-1, N1.getValueType()), (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); } if (Cond == ISD::SETLE || Cond == ISD::SETULE) { if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true - ++C1; // X <= C0 --> X < (C0+1) - return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), + // X <= C0 --> X < (C0+1) + return DAG.getSetCC(VT, N0, DAG.getConstant(C1+1, N1.getValueType()), (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); } @@ -1296,9 +1299,9 @@ } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) { // (X & 8) == 8 --> (X & 8) >> 3 // Perform the xform if C1 is a single bit. - if (isPowerOf2_64(C1)) { + if (C1.isPowerOf2()) { return DAG.getNode(ISD::SRL, VT, N0, - DAG.getConstant(Log2_64(C1), getShiftAmountTy())); + DAG.getConstant(C1.logBase2(), getShiftAmountTy())); } } } From gohman at apple.com Mon Mar 3 16:24:38 2008 From: gohman at apple.com (Dan Gohman) Date: Mon, 3 Mar 2008 14:24:38 -0800 Subject: [llvm-commits] Fwd: Patch for review: Speeding up ScheduleDAG computations In-Reply-To: <522BCA72-6445-4857-BE7B-019B841AA9DB@apple.com> References: <2913F98D-C5BD-44BD-A404-5E6DFFEDCFBC@apple.com> <200802291429.22322.dag@cray.com> <522BCA72-6445-4857-BE7B-019B841AA9DB@apple.com> Message-ID: On Mar 3, 2008, at 1:31 PM, Chris Lattner wrote: > On Mar 3, 2008, at 1:26 PM, Evan Cheng wrote: >> Thanks. >> >> Using std::set<> makes me queasy. :-) Too bad it doesn't seem >> possible >> to use SmallPtrSet (elements are not in sorted order). > > I'm sad to say that std::set is probably the best thing we have right > now that provides priority queue + removal from the middle support. > > Does anyone know of a better data structure to implement these > operations? Even if you don't volunteer to implement it, we can add > it to the open projects page. There's make_heap/push_heap/etc. in that let a plain std::vector (or a SmallVector I guess) be used as a heap. Dan From isanbard at gmail.com Mon Mar 3 16:32:03 2008 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 3 Mar 2008 14:32:03 -0800 Subject: [llvm-commits] [llvm] r47862 - /llvm/trunk/lib/CodeGen/MachineInstr.cpp In-Reply-To: <200803032214.m23MEXkF014824@zion.cs.uiuc.edu> References: <200803032214.m23MEXkF014824@zion.cs.uiuc.edu> Message-ID: <16e5fdf90803031432w66efb899j52b32154b0d78ea1@mail.gmail.com> On Mon, Mar 3, 2008 at 2:14 PM, Bill Wendling wrote: > Author: void > Date: Mon Mar 3 16:14:33 2008 > New Revision: 47862 > > URL: http://llvm.org/viewvc/llvm-project?rev=47862&view=rev > Log: > Go through the machine instruction's operands to make sure that we're not > marking both a super- and sub-register as "killed". This removes implicit uses > that are marked as "killed". > That is, they are implicit, marked "killed", and are sub-registers of a super-register that's already marked as killed. -bw From gohman at apple.com Mon Mar 3 16:37:52 2008 From: gohman at apple.com (Dan Gohman) Date: Mon, 03 Mar 2008 22:37:52 -0000 Subject: [llvm-commits] [llvm] r47867 - /llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Message-ID: <200803032237.m23MbqT5015621@zion.cs.uiuc.edu> Author: djg Date: Mon Mar 3 16:37:52 2008 New Revision: 47867 URL: http://llvm.org/viewvc/llvm-project?rev=47867&view=rev Log: Yet more APInt-ification. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=47867&r1=47866&r2=47867&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Mon Mar 3 16:37:52 2008 @@ -1161,7 +1161,7 @@ if (Op0Ty == ExtSrcTy) { ZextOp = N0.getOperand(0); } else { - int64_t Imm = ~0ULL >> (64-ExtSrcTyBits); + APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0), DAG.getConstant(Imm, Op0Ty)); } @@ -1220,17 +1220,14 @@ } } - uint64_t MinVal, MaxVal; + APInt MinVal, MaxVal; unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0)); if (ISD::isSignedIntSetCC(Cond)) { - MinVal = 1ULL << (OperandBitSize-1); - if (OperandBitSize != 1) // Avoid X >> 64, which is undefined. - MaxVal = ~0ULL >> (65-OperandBitSize); - else - MaxVal = 0; + MinVal = APInt::getSignedMinValue(OperandBitSize); + MaxVal = APInt::getSignedMaxValue(OperandBitSize); } else { - MinVal = 0; - MaxVal = ~0ULL >> (64-OperandBitSize); + MinVal = APInt::getMinValue(OperandBitSize); + MaxVal = APInt::getMaxValue(OperandBitSize); } // Canonicalize GE/LE comparisons to use GT/LT comparisons. From evan.cheng at apple.com Mon Mar 3 16:56:10 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 3 Mar 2008 14:56:10 -0800 Subject: [llvm-commits] [llvm] r47860 - /llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp In-Reply-To: <200803032211.m23MBGqd014690@zion.cs.uiuc.edu> References: <200803032211.m23MBGqd014690@zion.cs.uiuc.edu> Message-ID: On Mar 3, 2008, at 2:11 PM, Bill Wendling wrote: > Author: void > Date: Mon Mar 3 16:11:16 2008 > New Revision: 47860 > > URL: http://llvm.org/viewvc/llvm-project?rev=47860&view=rev > Log: > Multiple instructions can be inserted when eliminating frame > indexes. We need > the register scavenger to process all of those new instructions > instead of just > the last one inserted. > > > Modified: > llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp > > Modified: llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp?rev=47860&r1=47859&r2=47860&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp (original) > +++ llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp Mon Mar 3 > 16:11:16 2008 > @@ -530,27 +530,44 @@ > // Visit the instructions created by > eliminateCallFramePseudoInstr(). > I = next(PrevI); > MI = NULL; > - } else if (I->getOpcode() == TargetInstrInfo::DECLARE) > + } else if (I->getOpcode() == TargetInstrInfo::DECLARE) { > // Ignore it. > - I++; > - else { > - I++; > + ++I; This can be cleaned up. How about? if (I->getOpcode() == TargetInstrInfo::DECLARE) { // Ignore it. ++I; continue; } if (I->getOpcode() == FrameSetupOpcode || I->getOpcode() == FrameDestroyOpcode) { // Remember how much SP has been adjusted to create the call frame. int Size = I->getOperand(0).getImm(); if ((!StackGrowsDown && I->getOpcode() == FrameSetupOpcode) || (StackGrowsDown && I->getOpcode() == FrameDestroyOpcode)) Size = -Size; SPAdj += Size; MachineBasicBlock::iterator PrevI = prior(I); TRI.eliminateCallFramePseudoInstr(Fn, *BB, I); // Visit the instructions created by eliminateCallFramePseudoInstr(). I = next(PrevI); continue; } Then the next chunk doesn't have to be in else {}. Evan > > + } else { > + bool DoIncr = true; > + > for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) > if (MI->getOperand(i).isFrameIndex()) { > + // Some instructions (e.g. inline asm instructions) can > have > + // multiple frame indices and/or cause > eliminateFrameIndex to insert > + // more than one instruction. We need the register > scavenger to go > + // through all of these instructions so that it can > update its > + // register information. We keep the iterator at the > point before > + // insertion so that we can revisit them in full. > + bool AtBeginning = (I == BB->begin()); > + if (!AtBeginning) --I; > + > // If this instruction has a FrameIndex operand, we need > to use that > // target machine register info object to eliminate it. > TRI.eliminateFrameIndex(MI, SPAdj, RS); > > - // Revisit the instruction in full. Some instructions > (e.g. inline > - // asm instructions) can have multiple frame indices. > - --I; > + // Reset the iterator if we were at the beginning of > the BB. > + if (AtBeginning) { > + I = BB->begin(); > + DoIncr = false; > + } > + > MI = 0; > break; > } > + > + if (DoIncr) ++I; > } > + > // Update register states. > if (RS && MI) RS->forward(MI); > } > + > assert(SPAdj == 0 && "Unbalanced call frame setup / destroy > pairs?"); > } > } > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From evan.cheng at apple.com Mon Mar 3 17:05:18 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 3 Mar 2008 15:05:18 -0800 Subject: [llvm-commits] [llvm] r47863 - in /llvm/trunk: include/llvm/CodeGen/RegisterScavenging.h lib/Target/PowerPC/PPCInstrInfo.cpp lib/Target/PowerPC/PPCInstrInfo.td lib/Target/PowerPC/PPCMachineFunctionInfo.h lib/Target/PowerPC/PPCRegisterInfo.cpp lib/Target/PowerPC/PPCRegisterInfo.h test/CodeGen/PowerPC/Frames-alloca.ll In-Reply-To: <200803032219.m23MJG6l015020@zion.cs.uiuc.edu> References: <200803032219.m23MJG6l015020@zion.cs.uiuc.edu> Message-ID: Thanks. Some comments below. Evan On Mar 3, 2008, at 2:19 PM, Bill Wendling wrote: > Author: void > Date: Mon Mar 3 16:19:16 2008 > New Revision: 47863 > > URL: http://llvm.org/viewvc/llvm-project?rev=47863&view=rev > Log: > This is the initial check-in for adding register scavenging to PPC. > (Currently, > PPC-64 doesn't work.) This also lowers the spilling of the CR > registers so that > it uses a register other than the default R0 register (the scavenger > scrounges > for one). A significant part of this patch fixes how kill > information is > handled. > > > Modified: > llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h > llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp > llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td > llvm/trunk/lib/Target/PowerPC/PPCMachineFunctionInfo.h > llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp > llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h > llvm/trunk/test/CodeGen/PowerPC/Frames-alloca.ll > > Modified: llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h?rev=47863&r1=47862&r2=47863&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h (original) > +++ llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h Mon Mar 3 > 16:19:16 2008 > @@ -96,9 +96,9 @@ > > /// setUsed / setUnused - Mark the state of one or a number of > registers. > /// > - void setUsed(unsigned Reg) { RegsAvailable.reset(Reg); } > + void setUsed(unsigned Reg); > void setUsed(BitVector Regs) { RegsAvailable &= ~Regs; } > - void setUnused(unsigned Reg) { RegsAvailable.set(Reg); } > + void setUnused(unsigned Reg); > void setUnused(BitVector Regs) { RegsAvailable |= Regs; } > > /// FindUnusedReg - Find a unused register of the specified > register class > > Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=47863&r1=47862&r2=47863&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original) > +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Mon Mar 3 > 16:19:16 2008 > @@ -13,6 +13,7 @@ > > #include "PPCInstrInfo.h" > #include "PPCInstrBuilder.h" > +#include "PPCMachineFunctionInfo.h" > #include "PPCPredicates.h" > #include "PPCGenInstrInfo.inc" > #include "PPCTargetMachine.h" > @@ -316,10 +317,11 @@ > } > } > > -static void StoreRegToStackSlot(const TargetInstrInfo &TII, > +static bool StoreRegToStackSlot(const TargetInstrInfo &TII, > unsigned SrcReg, bool isKill, int > FrameIdx, > const TargetRegisterClass *RC, > - SmallVectorImpl > &NewMIs) { > + SmallVectorImpl > &NewMIs, > + bool isPPC64/*FIXME (64-bit): > Remove.*/) { > if (RC == PPC::GPRCRegisterClass) { > if (SrcReg != PPC::LR) { > NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW)) > @@ -351,22 +353,30 @@ > NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STFS)) > .addReg(SrcReg, false, false, > isKill), FrameIdx)); > } else if (RC == PPC::CRRCRegisterClass) { > - // FIXME: We use R0 here, because it isn't available for RA. > - // We need to store the CR in the low 4-bits of the saved > value. First, > - // issue a MFCR to save all of the CRBits. > - NewMIs.push_back(BuildMI(TII.get(PPC::MFCR), PPC::R0)); > + if (!isPPC64) { // FIXME (64-bit): Enable > + > NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::SPILL_CR)) > + .addReg(SrcReg, false, > false, isKill), > + FrameIdx)); > + return true; > + } else { > + // FIXME: We use R0 here, because it isn't available for RA. > We need to > + // store the CR in the low 4-bits of the saved value. First, > issue a MFCR > + // to save all of the CRBits. > + NewMIs.push_back(BuildMI(TII.get(PPC::MFCR), PPC::R0)); Is this right? I thought the whole point of using RS is so we don't have to reserved R0? > > > - // If the saved register wasn't CR0, shift the bits left so > that they are in > - // CR0's slot. > - if (SrcReg != PPC::CR0) { > - unsigned ShiftBits = > PPCRegisterInfo::getRegisterNumbering(SrcReg)*4; > - // rlwinm r0, r0, ShiftBits, 0, 31. > - NewMIs.push_back(BuildMI(TII.get(PPC::RLWINM), PPC::R0) > - .addReg > (PPC::R0).addImm(ShiftBits).addImm(0).addImm(31)); > - } > + // If the saved register wasn't CR0, shift the bits left so > that they are > + // in CR0's slot. > + if (SrcReg != PPC::CR0) { > + unsigned ShiftBits = > PPCRegisterInfo::getRegisterNumbering(SrcReg)*4; > + // rlwinm r0, r0, ShiftBits, 0, 31. > + NewMIs.push_back(BuildMI(TII.get(PPC::RLWINM), PPC::R0) > + > .addReg > (PPC::R0).addImm(ShiftBits).addImm(0).addImm(31)); > + } > > - NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW)) > - .addReg(PPC::R0, false, false, > isKill), FrameIdx)); > + NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW)) > + .addReg(PPC::R0, false, > false, isKill), > + FrameIdx)); > + } > } else if (RC == PPC::VRRCRegisterClass) { > // We don't have indexed addressing for vector loads. Emit: > // R0 = ADDI FI# > @@ -381,26 +391,39 @@ > assert(0 && "Unknown regclass!"); > abort(); > } > + > + return false; > } > > void > PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, > - MachineBasicBlock::iterator MI, > - unsigned SrcReg, bool isKill, > int FrameIdx, > - const TargetRegisterClass *RC) > const { > + MachineBasicBlock::iterator MI, > + unsigned SrcReg, bool isKill, int > FrameIdx, > + const TargetRegisterClass *RC) > const { > SmallVector NewMIs; > - StoreRegToStackSlot(*this, SrcReg, isKill, FrameIdx, RC, NewMIs); > + > + if (StoreRegToStackSlot(*this, SrcReg, isKill, FrameIdx, RC, > NewMIs, > + TM.getSubtargetImpl()->isPPC64()/*FIXME (64-bit): > Remove.*/)) { > + PPCFunctionInfo *FuncInfo = MBB.getParent()- > >getInfo(); > + FuncInfo->setSpillsCR(); > + } > + > for (unsigned i = 0, e = NewMIs.size(); i != e; ++i) > MBB.insert(MI, NewMIs[i]); > } > > void PPCInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned > SrcReg, > - bool isKill, > - > SmallVectorImpl &Addr, > - const TargetRegisterClass *RC, > - SmallVectorImpl > &NewMIs) const { > + bool isKill, > + SmallVectorImpl > &Addr, > + const TargetRegisterClass *RC, > + SmallVectorImpl > &NewMIs) const{ > if (Addr[0].isFrameIndex()) { > - StoreRegToStackSlot(*this, SrcReg, isKill, Addr[0].getIndex(), > RC, NewMIs); > + if (StoreRegToStackSlot(*this, SrcReg, isKill, > Addr[0].getIndex(), RC, NewMIs, > + TM.getSubtargetImpl()->isPPC64()/*FIXME (64-bit): > Remove.*/)) { > + PPCFunctionInfo *FuncInfo = MF.getInfo(); > + FuncInfo->setSpillsCR(); > + } > + > return; > } > > @@ -495,9 +518,9 @@ > > void > PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, > - MachineBasicBlock::iterator MI, > - unsigned DestReg, int FrameIdx, > - const TargetRegisterClass > *RC) const { > + MachineBasicBlock::iterator MI, > + unsigned DestReg, int FrameIdx, > + const TargetRegisterClass *RC) > const { > SmallVector NewMIs; > LoadRegFromStackSlot(*this, DestReg, FrameIdx, RC, NewMIs); > for (unsigned i = 0, e = NewMIs.size(); i != e; ++i) > @@ -505,9 +528,9 @@ > } > > void PPCInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned > DestReg, > - > SmallVectorImpl &Addr, > - const TargetRegisterClass *RC, > - SmallVectorImpl > &NewMIs) const{ > + SmallVectorImpl > &Addr, > + const TargetRegisterClass *RC, > + SmallVectorImpl > &NewMIs)const{ > if (Addr[0].isFrameIndex()) { > LoadRegFromStackSlot(*this, DestReg, Addr[0].getIndex(), RC, > NewMIs); > return; > > Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=47863&r1=47862&r2=47863&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original) > +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Mon Mar 3 > 16:19:16 2008 > @@ -371,6 +371,11 @@ > []>; > } > > +// SPILL_CR - Indicate that we're dumping the CR register, so we'll > need to > +// scavenge a register for it. > +def SPILL_CR : Pseudo<(outs), (ins GPRC:$cond, memri:$F), > + "${:comment} SPILL_CR $cond $F", []>; > + > let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { > let isReturn = 1 in > def BLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$p), > @@ -380,8 +385,6 @@ > def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), > "bctr", BrB, []>; > } > > - > - > let Defs = [LR] in > def MovePCtoLR : Pseudo<(outs), (ins piclabel:$label), "bl > $label", []>, > PPC970_Unit_BRU; > > Modified: llvm/trunk/lib/Target/PowerPC/PPCMachineFunctionInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCMachineFunctionInfo.h?rev=47863&r1=47862&r2=47863&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/PowerPC/PPCMachineFunctionInfo.h (original) > +++ llvm/trunk/lib/Target/PowerPC/PPCMachineFunctionInfo.h Mon Mar > 3 16:19:16 2008 > @@ -35,6 +35,9 @@ > /// only valid after the initial scan of the function by PEI. > bool UsesLR; > > + /// SpillsCR - Indicates whether CR is spilled in the current > function. > + bool SpillsCR; > + > /// LRStoreRequired - The bool indicates whether there is some > explicit use of > /// the LR/LR8 stack slot that is not obvious from scanning the > code. This > /// requires that the code generator produce a store of LR to the > stack on > @@ -42,7 +45,10 @@ > bool LRStoreRequired; > public: > PPCFunctionInfo(MachineFunction &MF) > - : FramePointerSaveIndex(0), ReturnAddrSaveIndex(0), > LRStoreRequired(false){} > + : FramePointerSaveIndex(0), > + ReturnAddrSaveIndex(0), > + SpillsCR(false), > + LRStoreRequired(false) {} > > int getFramePointerSaveIndex() const { return > FramePointerSaveIndex; } > void setFramePointerSaveIndex(int Idx) { FramePointerSaveIndex = > Idx; } > @@ -57,9 +63,11 @@ > void setUsesLR(bool U) { UsesLR = U; } > bool usesLR() const { return UsesLR; } > > + void setSpillsCR() { SpillsCR = true; } > + bool isCRSpilled() const { return SpillsCR; } > + > void setLRStoreRequired() { LRStoreRequired = true; } > bool isLRStoreRequired() const { return LRStoreRequired; } > - > }; > > } // end of namespace llvm > > Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=47863&r1=47862&r2=47863&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original) > +++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Mon Mar 3 > 16:19:16 2008 > @@ -28,6 +28,7 @@ > #include "llvm/CodeGen/MachineFrameInfo.h" > #include "llvm/CodeGen/MachineLocation.h" > #include "llvm/CodeGen/MachineRegisterInfo.h" > +#include "llvm/CodeGen/RegisterScavenging.h" > #include "llvm/CodeGen/SelectionDAGNodes.h" > #include "llvm/Target/TargetFrameInfo.h" > #include "llvm/Target/TargetInstrInfo.h" > @@ -41,6 +42,12 @@ > #include > using namespace llvm; > > +// FIXME (64-bit): Should be inlined. > +bool > +PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction > &) const { > + return !Subtarget.isPPC64(); > +} > + > /// getRegisterNumbering - Given the enum value for some register, > e.g. > /// PPC::F14, return the number that it corresponds to (e.g. 14). > unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) { > @@ -280,23 +287,40 @@ > return NoFramePointerElim || MFI->hasVarSizedObjects(); > } > > +static bool spillsCR(const MachineFunction &MF) { > + const PPCFunctionInfo *FuncInfo = MF.getInfo(); > + return FuncInfo->isCRSpilled(); > +} > + > BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction > &MF) const { > BitVector Reserved(getNumRegs()); > Reserved.set(PPC::R0); > Reserved.set(PPC::R1); > Reserved.set(PPC::LR); > + Reserved.set(PPC::LR8); > + > // In Linux, r2 is reserved for the OS. > if (!Subtarget.isDarwin()) > Reserved.set(PPC::R2); > - // On PPC64, r13 is the thread pointer. Never allocate this > register. > - // Note that this is overconservative, as it also prevents > allocation of > - // R31 when the FP is not needed. > + > + // On PPC64, r13 is the thread pointer. Never allocate this > register. Note > + // that this is over conservative, as it also prevents allocation > of R31 when > + // the FP is not needed. > if (Subtarget.isPPC64()) { > Reserved.set(PPC::R13); > Reserved.set(PPC::R31); > + > + Reserved.set(PPC::R0); // FIXME (64-bit): Remove > + > + Reserved.set(PPC::X0); > + Reserved.set(PPC::X1); > + Reserved.set(PPC::X13); > + Reserved.set(PPC::X31); > } > + > if (needsFP(MF)) > Reserved.set(PPC::R31); > + > return Reserved; > } > > @@ -333,14 +357,29 @@ > MBB.erase(I); > } > > -/// LowerDynamicAlloc - Generate the code for allocating an object > in the > +/// findScratchRegister - Find a 'free' PPC register. Try for a > call-clobbered > +/// register first and then a spilled callee-saved register if that > fails. > +static > +unsigned findScratchRegister(MachineBasicBlock::iterator II, > RegScavenger *RS, > + const TargetRegisterClass *RC, int > SPAdj) { > + assert(RS && "Register scavenging must be on"); > + unsigned Reg = RS->FindUnusedReg(RC, true); > + // FIXME: move ARM callee-saved reg scan to target independent > code, then > + // search for already spilled CS register here. > > + if (Reg == 0) > + Reg = RS->scavengeRegister(RC, II, SPAdj); > + return Reg; > +} > + > +/// lowerDynamicAlloc - Generate the code for allocating an object > in the > /// current frame. The sequence of code with be in the general form > /// > /// addi R0, SP, #frameSize ; get the address of the previous > frame > /// stwxu R0, SP, Rnegsize ; add and update the SP with the > negated size > /// addi Rnew, SP, #maxCalFrameSize ; get the top of the > allocation > /// > -void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator > II) const { > +void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator > II, > + int SPAdj, RegScavenger > *RS) const { > // Get the instruction. > MachineInstr &MI = *II; > // Get the instruction's basic block. > @@ -369,44 +408,128 @@ > // Because R0 is our only safe tmp register and addi/addis treat > R0 as zero. > // Constructing the constant and adding would take 3 instructions. > // Fortunately, a frame greater than 32K is rare. > + const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; > + const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; > + const TargetRegisterClass *RC = LP64 ? G8RC : GPRC; > + > + // FIXME (64-bit): Use "findScratchRegister" > + unsigned Reg; > + if (!LP64) > + Reg = findScratchRegister(II, RS, RC, SPAdj); > + else > + Reg = PPC::R0; Style police: unsigned Reg = ILP64 ? PPC:R0 : findScratchRegister()... Perhaps an assertion if findScratchRegister fails to scavenge a register? > > + > if (MaxAlign < TargetAlign && isInt16(FrameSize)) { > - BuildMI(MBB, II, TII.get(PPC::ADDI), PPC::R0) > + BuildMI(MBB, II, TII.get(PPC::ADDI), Reg) > .addReg(PPC::R31) > .addImm(FrameSize); > } else if (LP64) { > - BuildMI(MBB, II, TII.get(PPC::LD), PPC::X0) > + Reg = PPC::X0; // FIXME (64-bit): Remove. > + BuildMI(MBB, II, TII.get(PPC::LD), Reg) > .addImm(0) > .addReg(PPC::X1); > } else { > - BuildMI(MBB, II, TII.get(PPC::LWZ), PPC::R0) > + BuildMI(MBB, II, TII.get(PPC::LWZ), Reg) > .addImm(0) > .addReg(PPC::R1); > } > > - // Grow the stack and update the stack pointer link, then > - // determine the address of new allocated space. > + // Grow the stack and update the stack pointer link, then > determine the > + // address of new allocated space. > if (LP64) { > +#if 0 // FIXME (64-bit): Enable > BuildMI(MBB, II, TII.get(PPC::STDUX)) > - .addReg(PPC::X0) > + .addReg(Reg, false, false, true) > .addReg(PPC::X1) > .addReg(MI.getOperand(1).getReg()); > - BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) > +#else > + BuildMI(MBB, II, TII.get(PPC::STDUX)) > + .addReg(PPC::X0, false, false, true) > .addReg(PPC::X1) > - .addImm(maxCallFrameSize); > + .addReg(MI.getOperand(1).getReg()); > +#endif > + > + if (!MI.getOperand(1).isKill()) > + BuildMI(MBB, II, TII.get(PPC::ADDI8), > MI.getOperand(0).getReg()) > + .addReg(PPC::X1) > + .addImm(maxCallFrameSize); > + else > + // Implicitly kill the register. > + BuildMI(MBB, II, TII.get(PPC::ADDI8), > MI.getOperand(0).getReg()) > + .addReg(PPC::X1) > + .addImm(maxCallFrameSize) > + .addReg(MI.getOperand(1).getReg(), false, true, true); > } else { > BuildMI(MBB, II, TII.get(PPC::STWUX)) > - .addReg(PPC::R0) > + .addReg(Reg, false, false, true) > .addReg(PPC::R1) > .addReg(MI.getOperand(1).getReg()); > - BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) > - .addReg(PPC::R1) > - .addImm(maxCallFrameSize); > + > + if (!MI.getOperand(1).isKill()) > + BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) > + .addReg(PPC::R1) > + .addImm(maxCallFrameSize); > + else > + // Implicitly kill the register. > + BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) > + .addReg(PPC::R1) > + .addImm(maxCallFrameSize) > + .addReg(MI.getOperand(1).getReg(), false, true, true); > } > > // Discard the DYNALLOC instruction. > MBB.erase(II); > } > > +/// lowerCRSpilling - Generate the code for spilling a CR register. > Instead of > +/// reserving a whole register (R0), we scrounge for one here. This > generates > +/// code like this: > +/// > +/// mfcr rA ; Move the conditional register into > GPR rA. > +/// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in > CR0's slot. > +/// stw rA, FI ; Store rA to the frame. > +/// > +void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, > + unsigned FrameIndex, int SPAdj, > + RegScavenger *RS) const { > + // Get the instruction. > + MachineInstr &MI = *II; // ; SPILL_CR , , > > + // Get the instruction's basic block. > + MachineBasicBlock &MBB = *MI.getParent(); > + > + const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; > + const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; > + const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC; > + unsigned Reg = findScratchRegister(II, RS, RC, SPAdj); > + > + // We need to store the CR in the low 4-bits of the saved value. > First, issue > + // an MFCR to save all of the CRBits. > + if (!MI.getOperand(0).isKill()) > + BuildMI(MBB, II, TII.get(PPC::MFCR), Reg); > + else > + // Implicitly kill the CR register. > + BuildMI(MBB, II, TII.get(PPC::MFCR), Reg) > + .addReg(MI.getOperand(0).getReg(), false, true, true); > + > + // If the saved register wasn't CR0, shift the bits left so that > they are in > + // CR0's slot. > + unsigned SrcReg = MI.getOperand(0).getReg(); > + if (SrcReg != PPC::CR0) > + // rlwinm rA, rA, ShiftBits, 0, 31. > + BuildMI(MBB, II, TII.get(PPC::RLWINM), Reg) > + .addReg(Reg, false, false, true) > + .addImm(PPCRegisterInfo::getRegisterNumbering(SrcReg) * 4) > + .addImm(0) > + .addImm(31); > + > + addFrameReference(BuildMI(MBB, II, TII.get(PPC::STW)) > + .addReg(Reg, false, false, > MI.getOperand(1).getImm()), > + FrameIndex); > + > + // Discard the pseudo instruction. > + MBB.erase(II); > +} > + > void > PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, > int SPAdj, RegScavenger > *RS) const { > assert(SPAdj == 0 && "Unexpected"); > @@ -431,10 +554,10 @@ > unsigned OffsetOperandNo = (FIOperandNo == 2) ? 1 : 2; > if (MI.getOpcode() == TargetInstrInfo::INLINEASM) > OffsetOperandNo = FIOperandNo-1; > - > + > // Get the frame index. > int FrameIndex = MI.getOperand(FIOperandNo).getIndex(); > - > + > // Get the frame pointer save index. Users of this index are > primarily > // DYNALLOC instructions. > PPCFunctionInfo *FI = MF.getInfo(); > @@ -445,7 +568,14 @@ > // Special case for dynamic alloca. > if (FPSI && FrameIndex == FPSI && > (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { > - lowerDynamicAlloc(II); > + lowerDynamicAlloc(II, SPAdj, RS); > + return; > + } > + > + // Special case for pseudo-op SPILL_CR. > + if (!Subtarget.isPPC64()) // FIXME (64-bit): Remove. > + if (OpC == PPC::SPILL_CR) { > + lowerCRSpilling(II, FrameIndex, SPAdj, RS); > return; > } > > @@ -490,15 +620,31 @@ > MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); > return; > } > - > - // Insert a set of r0 with the full offset value before the ld, > st, or add > - BuildMI(MBB, II, TII.get(PPC::LIS), PPC::R0).addImm(Offset >> 16); > - BuildMI(MBB, II, TII.get(PPC::ORI), > PPC::R0).addReg(PPC::R0).addImm(Offset); > - > - // Convert into indexed form of the instruction > - // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 > - // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 > + > + // The offset doesn't fit into a single register, scavenge one to > build the > + // offset in. > + // FIXME: figure out what SPAdj is doing here. > + > + // FIXME (64-bit): Use "findScratchRegister". > + unsigned SReg; > + if (!Subtarget.isPPC64()) > + SReg = findScratchRegister(II, RS, &PPC::GPRCRegClass, SPAdj); > + else > + SReg = PPC::R0; > + > + // Insert a set of rA with the full offset value before the ld, > st, or add > + BuildMI(MBB, II, TII.get(PPC::LIS), SReg) > + .addImm(Offset >> 16); > + BuildMI(MBB, II, TII.get(PPC::ORI), SReg) > + .addReg(SReg, false, false, true) > + .addImm(Offset); > + > + // Convert into indexed form of the instruction: > + // > + // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 > + // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 > unsigned OperandBase; > + > if (OpC != TargetInstrInfo::INLINEASM) { > assert(ImmToIdxMap.count(OpC) && > "No indexed form of load or store available!"); > @@ -511,7 +657,7 @@ > > unsigned StackReg = MI.getOperand(FIOperandNo).getReg(); > MI.getOperand(OperandBase).ChangeToRegister(StackReg, false); > - MI.getOperand(OperandBase+1).ChangeToRegister(PPC::R0, false); > + MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false); > } > > /// VRRegNo - Map from a numbered VR register to its enum value. > @@ -598,24 +744,47 @@ > UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be > marked. > } > > - unsigned SrcReg = MI->getOperand(1).getReg(); > - unsigned DstReg = MI->getOperand(0).getReg(); > // If no registers are used, turn this into a copy. > if (UsedRegMask == 0) { > // Remove all VRSAVE code. > RemoveVRSaveCode(MI); > return; > - } else if ((UsedRegMask & 0xFFFF) == UsedRegMask) { > - BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg) > - .addReg(SrcReg).addImm(UsedRegMask); > + } > + > + unsigned SrcReg = MI->getOperand(1).getReg(); > + unsigned DstReg = MI->getOperand(0).getReg(); > + > + if ((UsedRegMask & 0xFFFF) == UsedRegMask) { > + if (DstReg != SrcReg) > + BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg) > + .addReg(SrcReg) > + .addImm(UsedRegMask); > + else > + BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg) > + .addReg(SrcReg, false, false, true) > + .addImm(UsedRegMask); > } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { > - BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) > - .addReg(SrcReg).addImm(UsedRegMask >> 16); > + if (DstReg != SrcReg) > + BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) > + .addReg(SrcReg) > + .addImm(UsedRegMask >> 16); > + else > + BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) > + .addReg(SrcReg, false, false, true) > + .addImm(UsedRegMask >> 16); > } else { > - BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) > - .addReg(SrcReg).addImm(UsedRegMask >> 16); > + if (DstReg != SrcReg) > + BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) > + .addReg(SrcReg) > + .addImm(UsedRegMask >> 16); > + else > + BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) > + .addReg(SrcReg, false, false, true) > + .addImm(UsedRegMask >> 16); > + > BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg) > - .addReg(DstReg).addImm(UsedRegMask & 0xFFFF); > + .addReg(DstReg, false, false, true) > + .addImm(UsedRegMask & 0xFFFF); > } > > // Remove the old UPDATE_VRSAVE instruction. > @@ -675,9 +844,9 @@ > MFI->setStackSize(FrameSize); > } > > -void > PPCRegisterInfo > ::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, > - > RegScavenger *RS) > - const { > +void > + > PPCRegisterInfo > ::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, > + RegScavenger > *RS) const { > // Save and clear the LR state. > PPCFunctionInfo *FI = MF.getInfo(); > unsigned LR = getRARegister(); > @@ -689,7 +858,7 @@ > bool IsPPC64 = Subtarget.isPPC64(); > bool IsELF32_ABI = Subtarget.isELF32_ABI(); > bool IsMachoABI = Subtarget.isMachoABI(); > - const MachineFrameInfo *MFI = MF.getFrameInfo(); > + MachineFrameInfo *MFI = MF.getFrameInfo(); > > // If the frame pointer save index hasn't been defined yet. > if (!FPSI && (NoFramePointerElim || MFI->hasVarSizedObjects()) && > @@ -703,9 +872,25 @@ > FI->setFramePointerSaveIndex(FPSI); > } > > + // Reserve a slot closest to SP or frame pointer if we have a > dynalloc or > + // a large stack, which will require scavenging a register to > materialize a > + // large offset. > + // FIXME: this doesn't actually check stack size, so is a bit > pessimistic > + // FIXME: doesn't detect whether or not we need to spill vXX, > which requires > + // r0 for now. > + > + if (!IsPPC64) // FIXME (64-bit): Enable. > + if (needsFP(MF) || spillsCR(MF)) { > + const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; > + const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; > + const TargetRegisterClass *RC = IsPPC64 ? G8RC : GPRC; > + RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), > + RC- > >getAlignment())); > + } > } > > -void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const { > +void > +PPCRegisterInfo::emitPrologue(MachineFunction &MF) const { > MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB > MachineBasicBlock::iterator MBBI = MBB.begin(); > MachineFrameInfo *MFI = MF.getFrameInfo(); > @@ -713,7 +898,7 @@ > > // Prepare for frame info. > unsigned FrameLabelId = 0; > - > + > // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If > we find it, > // process it. > for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { > @@ -725,7 +910,7 @@ > > // Move MBBI back to the beginning of the function. > MBBI = MBB.begin(); > - > + > // Work out frame sizes. > determineFrameLayout(MF); > unsigned FrameSize = MFI->getStackSize(); > @@ -743,29 +928,37 @@ > > int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, > IsMachoABI); > int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, > IsMachoABI); > - > + > if (IsPPC64) { > if (UsesLR) > BuildMI(MBB, MBBI, TII.get(PPC::MFLR8), PPC::X0); > > if (HasFP) > BuildMI(MBB, MBBI, TII.get(PPC::STD)) > - .addReg(PPC::X31).addImm(FPOffset/4).addReg(PPC::X1); > + .addReg(PPC::X31) > + .addImm(FPOffset/4) > + .addReg(PPC::X1); > > if (UsesLR) > BuildMI(MBB, MBBI, TII.get(PPC::STD)) > - .addReg(PPC::X0).addImm(LROffset/4).addReg(PPC::X1); > + .addReg(PPC::X0) > + .addImm(LROffset / 4) > + .addReg(PPC::X1); > } else { > if (UsesLR) > BuildMI(MBB, MBBI, TII.get(PPC::MFLR), PPC::R0); > > if (HasFP) > BuildMI(MBB, MBBI, TII.get(PPC::STW)) > - .addReg(PPC::R31).addImm(FPOffset).addReg(PPC::R1); > + .addReg(PPC::R31) > + .addImm(FPOffset) > + .addReg(PPC::R1); > > if (UsesLR) > BuildMI(MBB, MBBI, TII.get(PPC::STW)) > - .addReg(PPC::R0).addImm(LROffset).addReg(PPC::R1); > + .addReg(PPC::R0) > + .addImm(LROffset) > + .addReg(PPC::R1); > } > > // Skip if a leaf routine. > @@ -788,40 +981,65 @@ > if (MaxAlign > TargetAlign) { > assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid > alignment!"); > assert(isInt16(NegFrameSize) && "Unhandled stack size and > alignment!"); > + > BuildMI(MBB, MBBI, TII.get(PPC::RLWINM), PPC::R0) > - .addReg(PPC::R1).addImm(0).addImm(32- > Log2_32(MaxAlign)).addImm(31); > - BuildMI(MBB, MBBI, > TII.get(PPC::SUBFIC) ,PPC::R0).addReg(PPC::R0) > + .addReg(PPC::R1) > + .addImm(0) > + .addImm(32 - Log2_32(MaxAlign)) > + .addImm(31); > + BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC) ,PPC::R0) > + .addReg(PPC::R0, false, false, true) > .addImm(NegFrameSize); > BuildMI(MBB, MBBI, TII.get(PPC::STWUX)) > - .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0); > + .addReg(PPC::R1) > + .addReg(PPC::R1) > + .addReg(PPC::R0); > } else if (isInt16(NegFrameSize)) { > - BuildMI(MBB, MBBI, TII.get(PPC::STWU), > - > PPC::R1).addReg(PPC::R1).addImm(NegFrameSize).addReg(PPC::R1); > + BuildMI(MBB, MBBI, TII.get(PPC::STWU), PPC::R1) > + .addReg(PPC::R1) > + .addImm(NegFrameSize) > + .addReg(PPC::R1); > } else { > - BuildMI(MBB, MBBI, TII.get(PPC::LIS), > PPC::R0).addImm(NegFrameSize >> 16); > - BuildMI(MBB, MBBI, TII.get(PPC::ORI), PPC::R0).addReg(PPC::R0) > + BuildMI(MBB, MBBI, TII.get(PPC::LIS), PPC::R0) > + .addImm(NegFrameSize >> 16); > + BuildMI(MBB, MBBI, TII.get(PPC::ORI), PPC::R0) > + .addReg(PPC::R0, false, false, true) > .addImm(NegFrameSize & 0xFFFF); > - BuildMI(MBB, MBBI, > TII.get(PPC::STWUX)).addReg(PPC::R1).addReg(PPC::R1) > + BuildMI(MBB, MBBI, TII.get(PPC::STWUX)) > + .addReg(PPC::R1) > + .addReg(PPC::R1) > .addReg(PPC::R0); > } > } else { // PPC64. > if (MaxAlign > TargetAlign) { > assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid > alignment!"); > assert(isInt16(NegFrameSize) && "Unhandled stack size and > alignment!"); > + > BuildMI(MBB, MBBI, TII.get(PPC::RLDICL), PPC::X0) > - .addReg(PPC::X1).addImm(0).addImm(64-Log2_32(MaxAlign)); > - BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC8), > PPC::X0).addReg(PPC::X0) > + .addReg(PPC::X1) > + .addImm(0) > + .addImm(64 - Log2_32(MaxAlign)); > + BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC8), PPC::X0) > + .addReg(PPC::X0) > .addImm(NegFrameSize); > BuildMI(MBB, MBBI, TII.get(PPC::STDUX)) > - .addReg(PPC::X1).addReg(PPC::X1).addReg(PPC::X0); > + .addReg(PPC::X1) > + .addReg(PPC::X1) > + .addReg(PPC::X0); > } else if (isInt16(NegFrameSize)) { > BuildMI(MBB, MBBI, TII.get(PPC::STDU), PPC::X1) > - .addReg(PPC::X1).addImm(NegFrameSize/4).addReg(PPC::X1); > + .addReg(PPC::X1) > + .addImm(NegFrameSize / 4) > + .addReg(PPC::X1); > } else { > - BuildMI(MBB, MBBI, TII.get(PPC::LIS8), > PPC::X0).addImm(NegFrameSize >>16); > - BuildMI(MBB, MBBI, TII.get(PPC::ORI8), PPC::X0).addReg(PPC::X0) > + BuildMI(MBB, MBBI, TII.get(PPC::LIS8), PPC::X0) > + .addImm(NegFrameSize >> 16); > + BuildMI(MBB, MBBI, TII.get(PPC::ORI8), PPC::X0) > + .addReg(PPC::X0, false, false, true) > .addImm(NegFrameSize & 0xFFFF); > - BuildMI(MBB, MBBI, > TII.get(PPC::STDUX)).addReg(PPC::X1).addReg(PPC::X1) > + BuildMI(MBB, MBBI, TII.get(PPC::STDUX)) > + .addReg(PPC::X1) > + .addReg(PPC::X1) > .addReg(PPC::X0); > } > } > @@ -873,10 +1091,12 @@ > // If there is a frame pointer, copy R1 into R31 > if (HasFP) { > if (!IsPPC64) { > - BuildMI(MBB, MBBI, TII.get(PPC::OR), PPC::R31).addReg(PPC::R1) > + BuildMI(MBB, MBBI, TII.get(PPC::OR), PPC::R31) > + .addReg(PPC::R1) > .addReg(PPC::R1); > } else { > - BuildMI(MBB, MBBI, TII.get(PPC::OR8), PPC::X31).addReg(PPC::X1) > + BuildMI(MBB, MBBI, TII.get(PPC::OR8), PPC::X31) > + .addReg(PPC::X1) > .addReg(PPC::X1); > } > } > > Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h?rev=47863&r1=47862&r2=47863&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h (original) > +++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h Mon Mar 3 > 16:19:16 2008 > @@ -51,13 +51,20 @@ > /// time). > bool targetHandlesStackFrameRounding() const { return true; } > > + /// requiresRegisterScavenging - We require a register scavenger. > + /// FIXME (64-bit): Should be inlined. > + bool requiresRegisterScavenging(const MachineFunction &MF) const; > + > bool hasFP(const MachineFunction &MF) const; > > void eliminateCallFramePseudoInstr(MachineFunction &MF, > MachineBasicBlock &MBB, > MachineBasicBlock::iterator I) > const; > > - void lowerDynamicAlloc(MachineBasicBlock::iterator II) const; > + void lowerDynamicAlloc(MachineBasicBlock::iterator II, > + int SPAdj, RegScavenger *RS) const; > + void lowerCRSpilling(MachineBasicBlock::iterator II, unsigned > FrameIndex, > + int SPAdj, RegScavenger *RS) const; > void eliminateFrameIndex(MachineBasicBlock::iterator II, > int SPAdj, RegScavenger *RS = NULL) const; > > > Modified: llvm/trunk/test/CodeGen/PowerPC/Frames-alloca.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/Frames-alloca.ll?rev=47863&r1=47862&r2=47863&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/test/CodeGen/PowerPC/Frames-alloca.ll (original) > +++ llvm/trunk/test/CodeGen/PowerPC/Frames-alloca.ll Mon Mar 3 > 16:19:16 2008 > @@ -1,7 +1,7 @@ > ; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple- > darwin8 | \ > ; RUN: grep {stw r31, 20(r1)} > ; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple- > darwin8 | \ > -; RUN: grep {stwu r1, -64(r1)} > +; RUN: grep {stwu r1, -80(r1)} > ; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple- > darwin8 | \ > ; RUN: grep {lwz r1, 0(r1)} > ; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple- > darwin8 | \ > @@ -9,7 +9,7 @@ > ; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple- > darwin8 -disable-fp-elim | \ > ; RUN: grep {stw r31, 20(r1)} > ; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple- > darwin8 -disable-fp-elim | \ > -; RUN: grep {stwu r1, -64(r1)} > +; RUN: grep {stwu r1, -80(r1)} > ; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple- > darwin8 -disable-fp-elim | \ > ; RUN: grep {lwz r1, 0(r1)} > ; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple- > darwin8 -disable-fp-elim | \ > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From evan.cheng at apple.com Mon Mar 3 17:14:56 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 3 Mar 2008 15:14:56 -0800 Subject: [llvm-commits] [llvm] r47862 - /llvm/trunk/lib/CodeGen/MachineInstr.cpp In-Reply-To: <200803032214.m23MEXkF014824@zion.cs.uiuc.edu> References: <200803032214.m23MEXkF014824@zion.cs.uiuc.edu> Message-ID: On Mar 3, 2008, at 2:14 PM, Bill Wendling wrote: > Author: void > Date: Mon Mar 3 16:14:33 2008 > New Revision: 47862 > > URL: http://llvm.org/viewvc/llvm-project?rev=47862&view=rev > Log: > Go through the machine instruction's operands to make sure that > we're not > marking both a super- and sub-register as "killed". This removes > implicit uses > that are marked as "killed". > > > Modified: > llvm/trunk/lib/CodeGen/MachineInstr.cpp > > Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=47862&r1=47861&r2=47862&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original) > +++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Mon Mar 3 16:14:33 2008 > @@ -678,34 +678,74 @@ > bool MachineInstr::addRegisterKilled(unsigned IncomingReg, > const TargetRegisterInfo > *RegInfo, > bool AddIfNotFound) { > - bool Found = false; > - for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { > + // Go through the machine instruction's operands to eliminate any > potentially > + // illegal conditions. I.e., a super- and sub-register both > marked "kill". > + Restart: > + for (unsigned i = 0, e = getNumOperands(); i < e; ++i) { > MachineOperand &MO = getOperand(i); > + > if (MO.isRegister() && MO.isUse()) { > unsigned Reg = MO.getReg(); > - if (!Reg) > + > + if (!Reg || IncomingReg == Reg || > + !TargetRegisterInfo::isPhysicalRegister(Reg) || > + !TargetRegisterInfo::isPhysicalRegister(IncomingReg)) > continue; > + > + if (RegInfo->isSubRegister(IncomingReg, Reg)) { > + if (MO.isKill()) { > + if (MO.isImplicit()) { > > + // Remove this implicit use that marks the sub-register > "kill". Let > + // the super-register take care of this information. > + RemoveOperand(i); > + goto Restart; // Instruction was modified, redo > checking. Seems like this may increase compile time unnecessarily? Do you have to restart from first operand? Can you simply recompute 'e' and make sure i isn't incremented? > > + } else { > + // The super-register is going to take care of this kill > + // information. > + MO.setIsKill(false); > + } > + } > + } else if (RegInfo->isSuperRegister(IncomingReg, Reg) && > MO.isKill()) { > + // The kill information is already handled by a super- > register. Don't > + // add this sub-register as a kill. > + return true; > + } Check this first so we can take advantage of the early exit to avoid nesting. > > + } > + } > + > + // If the register already exists, then make sure it or its super- > register is > + // marked "kill". > + for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { > + MachineOperand &MO = getOperand(i); > + > + if (MO.isRegister() && MO.isUse()) { > + unsigned Reg = MO.getReg(); > + if (!Reg) continue; > + > if (Reg == IncomingReg) { > MO.setIsKill(); > - Found = true; > - break; > + return true; > > } else if (TargetRegisterInfo::isPhysicalRegister(Reg) && No need for else here. Evan > > TargetRegisterInfo::isPhysicalRegister(IncomingReg) > && > RegInfo->isSuperRegister(IncomingReg, Reg) && > - MO.isKill()) > + MO.isKill()) { > // A super-register kill already exists. > - Found = true; > + return true; > + } > } > } > > - // If not found, this means an alias of one of the operand is > killed. Add a > + // If not found, this means an alias of one of the operands is > killed. Add a > // new implicit operand if required. > - if (!Found && AddIfNotFound) { > - addOperand(MachineOperand::CreateReg(IncomingReg, false/*IsDef*/, > - true/*IsImp*/,true/ > *IsKill*/)); > + if (AddIfNotFound) { > + addOperand(MachineOperand::CreateReg(IncomingReg, > + false /*IsDef*/, > + true /*IsImp*/, > + true /*IsKill*/)); > return true; > } > - return Found; > + > + return false; > } > > bool MachineInstr::addRegisterDead(unsigned IncomingReg, > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From isanbard at gmail.com Mon Mar 3 17:19:03 2008 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 3 Mar 2008 15:19:03 -0800 Subject: [llvm-commits] [llvm] r47863 - in /llvm/trunk: include/llvm/CodeGen/RegisterScavenging.h lib/Target/PowerPC/PPCInstrInfo.cpp lib/Target/PowerPC/PPCInstrInfo.td lib/Target/PowerPC/PPCMachineFunctionInfo.h lib/Target/PowerPC/PPCRegisterInfo.cpp lib Message-ID: <16e5fdf90803031519j47e6e99x80a67b59b733f40@mail.gmail.com> On Mon, Mar 3, 2008 at 3:05 PM, Evan Cheng wrote: > Thanks. Some comments below. > > > @@ -351,22 +353,30 @@ > > NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STFS)) > > .addReg(SrcReg, false, false, > > isKill), FrameIdx)); > > } else if (RC == PPC::CRRCRegisterClass) { > > - // FIXME: We use R0 here, because it isn't available for RA. > > - // We need to store the CR in the low 4-bits of the saved > > value. First, > > - // issue a MFCR to save all of the CRBits. > > - NewMIs.push_back(BuildMI(TII.get(PPC::MFCR), PPC::R0)); > > + if (!isPPC64) { // FIXME (64-bit): Enable > > + > > NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::SPILL_CR)) > > + .addReg(SrcReg, false, > > false, isKill), > > + FrameIdx)); > > + return true; > > + } else { > > + // FIXME: We use R0 here, because it isn't available for RA. > > We need to > > + // store the CR in the low 4-bits of the saved value. First, > > issue a MFCR > > + // to save all of the CRBits. > > + NewMIs.push_back(BuildMI(TII.get(PPC::MFCR), PPC::R0)); > > Is this right? I thought the whole point of using RS is so we don't > have to reserved R0? > This is part of a "FIXME". PPC64 can't handle the register scavenger just yet. When it does, then this will be removed. > > + // FIXME (64-bit): Use "findScratchRegister" > > + unsigned Reg; > > + if (!LP64) > > + Reg = findScratchRegister(II, RS, RC, SPAdj); > > + else > > + Reg = PPC::R0; > > Style police: unsigned Reg = ILP64 ? PPC:R0 : findScratchRegister()... > > Perhaps an assertion if findScratchRegister fails to scavenge a > register? > Sure. :-) -bw From isanbard at gmail.com Mon Mar 3 17:22:41 2008 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 3 Mar 2008 15:22:41 -0800 Subject: [llvm-commits] [llvm] r47862 - /llvm/trunk/lib/CodeGen/MachineInstr.cpp In-Reply-To: References: <200803032214.m23MEXkF014824@zion.cs.uiuc.edu> Message-ID: <16e5fdf90803031522y7cd2c7c9nec7361de750844cf@mail.gmail.com> On Mon, Mar 3, 2008 at 3:14 PM, Evan Cheng wrote: > > --- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original) > > +++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Mon Mar 3 16:14:33 2008 > > @@ -678,34 +678,74 @@ > > bool MachineInstr::addRegisterKilled(unsigned IncomingReg, > > const TargetRegisterInfo > > *RegInfo, > > bool AddIfNotFound) { > > - bool Found = false; > > - for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { > > + // Go through the machine instruction's operands to eliminate any > > potentially > > + // illegal conditions. I.e., a super- and sub-register both > > marked "kill". > > + Restart: > > + for (unsigned i = 0, e = getNumOperands(); i < e; ++i) { > > MachineOperand &MO = getOperand(i); > > + > > if (MO.isRegister() && MO.isUse()) { > > unsigned Reg = MO.getReg(); > > - if (!Reg) > > + > > + if (!Reg || IncomingReg == Reg || > > + !TargetRegisterInfo::isPhysicalRegister(Reg) || > > + !TargetRegisterInfo::isPhysicalRegister(IncomingReg)) > > continue; > > + > > + if (RegInfo->isSubRegister(IncomingReg, Reg)) { > > + if (MO.isKill()) { > > + if (MO.isImplicit()) { > > > > + // Remove this implicit use that marks the sub-register > > "kill". Let > > + // the super-register take care of this information. > > + RemoveOperand(i); > > + goto Restart; // Instruction was modified, redo > > checking. > > Seems like this may increase compile time unnecessarily? Do you have > to restart from first operand? Can you simply recompute 'e' and make > sure i isn't incremented? > Okay. (I'm the only one who likes gotos ;-) > > + } else { > > + // The super-register is going to take care of this kill > > + // information. > > + MO.setIsKill(false); > > + } > > + } > > + } else if (RegInfo->isSuperRegister(IncomingReg, Reg) && > > MO.isKill()) { > > + // The kill information is already handled by a super- > > register. Don't > > + // add this sub-register as a kill. > > + return true; > > + } > > Check this first so we can take advantage of the early exit to avoid > nesting. > Okay. > > > > > + } > > + } > > + > > + // If the register already exists, then make sure it or its super- > > register is > > + // marked "kill". > > + for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { > > + MachineOperand &MO = getOperand(i); > > + > > + if (MO.isRegister() && MO.isUse()) { > > + unsigned Reg = MO.getReg(); > > + if (!Reg) continue; > > + > > if (Reg == IncomingReg) { > > MO.setIsKill(); > > - Found = true; > > - break; > > + return true; > > > > } else if (TargetRegisterInfo::isPhysicalRegister(Reg) && > > No need for else here. > Okay. -bw From dalej at apple.com Mon Mar 3 17:29:28 2008 From: dalej at apple.com (Dale Johannesen) Date: Mon, 3 Mar 2008 15:29:28 -0800 Subject: [llvm-commits] [llvm] r47862 - /llvm/trunk/lib/CodeGen/MachineInstr.cpp In-Reply-To: <16e5fdf90803031522y7cd2c7c9nec7361de750844cf@mail.gmail.com> References: <200803032214.m23MEXkF014824@zion.cs.uiuc.edu> <16e5fdf90803031522y7cd2c7c9nec7361de750844cf@mail.gmail.com> Message-ID: <72E52E44-C937-44C0-B9B6-5DA66057D71C@apple.com> On Mar 3, 2008, at 3:22 PM, Bill Wendling wrote: > On Mon, Mar 3, 2008 at 3:14 PM, Evan Cheng > wrote: >>> --- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original) >>> +++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Mon Mar 3 16:14:33 2008 >>> > Okay. (I'm the only one who likes gotos ;-) I don't mind them in rare cases, but I always get overruled:) From gohman at apple.com Mon Mar 3 17:35:36 2008 From: gohman at apple.com (Dan Gohman) Date: Mon, 03 Mar 2008 23:35:36 -0000 Subject: [llvm-commits] [llvm] r47868 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Message-ID: <200803032335.m23NZaZO017529@zion.cs.uiuc.edu> Author: djg Date: Mon Mar 3 17:35:36 2008 New Revision: 47868 URL: http://llvm.org/viewvc/llvm-project?rev=47868&view=rev Log: More APInt-ification. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=47868&r1=47867&r2=47868&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Mon Mar 3 17:35:36 2008 @@ -1518,17 +1518,13 @@ return VTBits-Tmp; case ISD::Constant: { - uint64_t Val = cast(Op)->getValue(); - // If negative, invert the bits, then look at it. - if (Val & MVT::getIntVTSignBit(VT)) - Val = ~Val; - - // Shift the bits so they are the leading bits in the int64_t. - Val <<= 64-VTBits; - - // Return # leading zeros. We use 'min' here in case Val was zero before - // shifting. We don't want to return '64' as for an i32 "0". - return std::min(VTBits, CountLeadingZeros_64(Val)); + const APInt &Val = cast(Op)->getAPIntValue(); + // If negative, return # leading ones. + if (Val.isNegative()) + return Val.countLeadingOnes(); + + // Return # leading zeros. + return Val.countLeadingZeros(); } case ISD::SIGN_EXTEND: From evan.cheng at apple.com Mon Mar 3 17:47:04 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 3 Mar 2008 15:47:04 -0800 Subject: [llvm-commits] [llvm] r47862 - /llvm/trunk/lib/CodeGen/MachineInstr.cpp In-Reply-To: <72E52E44-C937-44C0-B9B6-5DA66057D71C@apple.com> References: <200803032214.m23MEXkF014824@zion.cs.uiuc.edu> <16e5fdf90803031522y7cd2c7c9nec7361de750844cf@mail.gmail.com> <72E52E44-C937-44C0-B9B6-5DA66057D71C@apple.com> Message-ID: <3D7E8268-D07B-4EAC-A8CD-BF2C4FEF1CA0@apple.com> Haven't you heard goto's are evil? :-) I think goto's can be used tastefully. However, it's definitely not the right situation to use it in this case. Evan On Mar 3, 2008, at 3:29 PM, Dale Johannesen wrote: > > On Mar 3, 2008, at 3:22 PM, Bill Wendling wrote: > >> On Mon, Mar 3, 2008 at 3:14 PM, Evan Cheng >> wrote: >>>> --- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original) >>>> +++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Mon Mar 3 16:14:33 >>>> 2008 >>>> >> Okay. (I'm the only one who likes gotos ;-) > > I don't mind them in rare cases, but I always get overruled:) > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From gohman at apple.com Mon Mar 3 17:51:39 2008 From: gohman at apple.com (Dan Gohman) Date: Mon, 03 Mar 2008 23:51:39 -0000 Subject: [llvm-commits] [llvm] r47869 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <200803032351.m23Npd58017963@zion.cs.uiuc.edu> Author: djg Date: Mon Mar 3 17:51:38 2008 New Revision: 47869 URL: http://llvm.org/viewvc/llvm-project?rev=47869&view=rev Log: Misc. APInt-ification in the DAGCombiner. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=47869&r1=47868&r2=47869&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Mar 3 17:51:38 2008 @@ -1984,15 +1984,15 @@ // If there is an AND of either shifted operand, apply it to the result. if (LHSMask.Val || RHSMask.Val) { - uint64_t Mask = MVT::getIntVTBitMask(VT); + APInt Mask = APInt::getAllOnesValue(OpSizeInBits); if (LHSMask.Val) { - uint64_t RHSBits = (1ULL << LShVal)-1; - Mask &= cast(LHSMask)->getValue() | RHSBits; + APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); + Mask &= cast(LHSMask)->getAPIntValue() | RHSBits; } if (RHSMask.Val) { - uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1); - Mask &= cast(RHSMask)->getValue() | LHSBits; + APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); + Mask &= cast(RHSMask)->getAPIntValue() | LHSBits; } Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT)); @@ -2248,8 +2248,8 @@ // the constant which would cause it to be modified for this // operation. if (N->getOpcode() == ISD::SRA) { - uint64_t BinOpRHSSign = BinOpCst->getValue() >> (MVT::getSizeInBits(VT)-1); - if ((bool)BinOpRHSSign != HighBitSet) + bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); + if (BinOpRHSSignSet != HighBitSet) return SDOperand(); } @@ -2872,7 +2872,8 @@ } else if (X.getValueType() > VT) { X = DAG.getNode(ISD::TRUNCATE, VT, X); } - uint64_t Mask = cast(N0.getOperand(1))->getValue(); + APInt Mask = cast(N0.getOperand(1))->getAPIntValue(); + Mask.zext(MVT::getSizeInBits(VT)); return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); } @@ -2988,7 +2989,8 @@ } else if (X.getValueType() > VT) { X = DAG.getNode(ISD::TRUNCATE, VT, X); } - uint64_t Mask = cast(N0.getOperand(1))->getValue(); + APInt Mask = cast(N0.getOperand(1))->getAPIntValue(); + Mask.zext(MVT::getSizeInBits(VT)); return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); } @@ -3350,7 +3352,7 @@ SDOperand NewConv = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); AddToWorkList(NewConv.Val); - uint64_t SignBit = MVT::getIntVTSignBit(VT); + APInt SignBit = APInt::getSignBit(MVT::getSizeInBits(VT)); if (N0.getOpcode() == ISD::FNEG) return DAG.getNode(ISD::XOR, VT, NewConv, DAG.getConstant(SignBit, VT)); assert(N0.getOpcode() == ISD::FABS); @@ -3383,7 +3385,7 @@ AddToWorkList(X.Val); } - uint64_t SignBit = MVT::getIntVTSignBit(VT); + APInt SignBit = APInt::getSignBit(MVT::getSizeInBits(VT)); X = DAG.getNode(ISD::AND, VT, X, DAG.getConstant(SignBit, VT)); AddToWorkList(X.Val); @@ -3457,7 +3459,7 @@ for (unsigned i = 0, e = BV->getNumOperands(); i != e; i += NumInputsPerOutput) { bool isLE = TLI.isLittleEndian(); - uint64_t NewBits = 0; + APInt NewBits = APInt(DstBitSize, 0); bool EltIsUndef = true; for (unsigned j = 0; j != NumInputsPerOutput; ++j) { // Shift the previously computed bits over. @@ -3466,7 +3468,8 @@ if (Op.getOpcode() == ISD::UNDEF) continue; EltIsUndef = false; - NewBits |= cast(Op)->getValue(); + NewBits |= + APInt(cast(Op)->getAPIntValue()).zext(DstBitSize); } if (EltIsUndef) @@ -3492,14 +3495,14 @@ Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); continue; } - uint64_t OpVal = cast(BV->getOperand(i))->getValue(); + APInt OpVal = cast(BV->getOperand(i))->getAPIntValue(); for (unsigned j = 0; j != NumOutputsPerInput; ++j) { - unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1); + APInt ThisVal = APInt(OpVal).trunc(DstBitSize); Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); - if (isS2V && i == 0 && j == 0 && ThisVal == OpVal) + if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal) // Simply turn this into a SCALAR_TO_VECTOR of the new type. return DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Ops[0]); - OpVal >>= DstBitSize; + OpVal = OpVal.lshr(DstBitSize); } // For big endian targets, swap the order of the pieces of each element. From isanbard at gmail.com Mon Mar 3 17:51:48 2008 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 3 Mar 2008 15:51:48 -0800 Subject: [llvm-commits] [llvm] r47862 - /llvm/trunk/lib/CodeGen/MachineInstr.cpp In-Reply-To: <3D7E8268-D07B-4EAC-A8CD-BF2C4FEF1CA0@apple.com> References: <200803032214.m23MEXkF014824@zion.cs.uiuc.edu> <16e5fdf90803031522y7cd2c7c9nec7361de750844cf@mail.gmail.com> <72E52E44-C937-44C0-B9B6-5DA66057D71C@apple.com> <3D7E8268-D07B-4EAC-A8CD-BF2C4FEF1CA0@apple.com> Message-ID: <16e5fdf90803031551u70c97d29v174a4fde1286869c@mail.gmail.com> On Mon, Mar 3, 2008 at 3:47 PM, Evan Cheng wrote: > Haven't you heard goto's are evil? :-) > > I think goto's can be used tastefully. However, it's definitely not > the right situation to use it in this case. > Fair enough. I was 90% sure that that was going to be picked on when I submitted it. I did it that way because how the machine operands are stored in the machine instruction is non-intuitive and I didn't want to make a mistake of having an invalid iterator. :-) -bw From isanbard at gmail.com Mon Mar 3 17:57:28 2008 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 03 Mar 2008 23:57:28 -0000 Subject: [llvm-commits] [llvm] r47870 - in /llvm/trunk/lib/CodeGen: MachineInstr.cpp PrologEpilogInserter.cpp Message-ID: <200803032357.m23NvSju018174@zion.cs.uiuc.edu> Author: void Date: Mon Mar 3 17:57:28 2008 New Revision: 47870 URL: http://llvm.org/viewvc/llvm-project?rev=47870&view=rev Log: Miscellaneous clean-ups based on Evan's feedback: - Cleaned up how the prologue-epilogue inserter loops over the instructions. - Instead of restarting the processing of an instruction if we remove an implicit kill, just update the end iterator and make sure that the iterator isn't incremented. Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=47870&r1=47869&r2=47870&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Mon Mar 3 17:57:28 2008 @@ -680,37 +680,40 @@ bool AddIfNotFound) { // Go through the machine instruction's operands to eliminate any potentially // illegal conditions. I.e., a super- and sub-register both marked "kill". - Restart: - for (unsigned i = 0, e = getNumOperands(); i < e; ++i) { + for (unsigned i = 0, e = getNumOperands(); i < e;) { MachineOperand &MO = getOperand(i); - if (MO.isRegister() && MO.isUse()) { unsigned Reg = MO.getReg(); if (!Reg || IncomingReg == Reg || !TargetRegisterInfo::isPhysicalRegister(Reg) || - !TargetRegisterInfo::isPhysicalRegister(IncomingReg)) + !TargetRegisterInfo::isPhysicalRegister(IncomingReg)) { + ++i; continue; + } - if (RegInfo->isSubRegister(IncomingReg, Reg)) { - if (MO.isKill()) { - if (MO.isImplicit()) { - // Remove this implicit use that marks the sub-register "kill". Let - // the super-register take care of this information. - RemoveOperand(i); - goto Restart; // Instruction was modified, redo checking. - } else { - // The super-register is going to take care of this kill - // information. - MO.setIsKill(false); - } - } - } else if (RegInfo->isSuperRegister(IncomingReg, Reg) && MO.isKill()) { + if (RegInfo->isSuperRegister(IncomingReg, Reg) && MO.isKill()) // The kill information is already handled by a super-register. Don't // add this sub-register as a kill. return true; + + if (RegInfo->isSubRegister(IncomingReg, Reg) && MO.isKill()) { + if (MO.isImplicit()) { + // Remove this implicit use that marks the sub-register + // "kill". Let the super-register take care of this + // information. + RemoveOperand(i); + e = getNumOperands(); + continue; + } else { + // The super-register is going to take care of this kill + // information. + MO.setIsKill(false); + } } } + + ++i; } // If the register already exists, then make sure it or its super-register is @@ -725,13 +728,14 @@ if (Reg == IncomingReg) { MO.setIsKill(); return true; - } else if (TargetRegisterInfo::isPhysicalRegister(Reg) && - TargetRegisterInfo::isPhysicalRegister(IncomingReg) && - RegInfo->isSuperRegister(IncomingReg, Reg) && - MO.isKill()) { + } + + if (TargetRegisterInfo::isPhysicalRegister(Reg) && + TargetRegisterInfo::isPhysicalRegister(IncomingReg) && + RegInfo->isSuperRegister(IncomingReg, Reg) && + MO.isKill()) // A super-register kill already exists. return true; - } } } Modified: llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp?rev=47870&r1=47869&r2=47870&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp (original) +++ llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp Mon Mar 3 17:57:28 2008 @@ -517,53 +517,63 @@ for (MachineBasicBlock::iterator I = BB->begin(); I != BB->end(); ) { MachineInstr *MI = I; - if (I->getOpcode() == FrameSetupOpcode || - I->getOpcode() == FrameDestroyOpcode) { - // Remember how much SP has been adjustment to create the call frame. - int Size = I->getOperand(0).getImm(); - if ((!StackGrowsDown && I->getOpcode() == FrameSetupOpcode) || - (StackGrowsDown && I->getOpcode() == FrameDestroyOpcode)) - Size = -Size; - SPAdj += Size; - MachineBasicBlock::iterator PrevI = prior(I); - TRI.eliminateCallFramePseudoInstr(Fn, *BB, I); - // Visit the instructions created by eliminateCallFramePseudoInstr(). - I = next(PrevI); - MI = NULL; - } else if (I->getOpcode() == TargetInstrInfo::DECLARE) { + if (I->getOpcode() == TargetInstrInfo::DECLARE) { // Ignore it. ++I; - } else { - bool DoIncr = true; - - for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) - if (MI->getOperand(i).isFrameIndex()) { - // Some instructions (e.g. inline asm instructions) can have - // multiple frame indices and/or cause eliminateFrameIndex to insert - // more than one instruction. We need the register scavenger to go - // through all of these instructions so that it can update its - // register information. We keep the iterator at the point before - // insertion so that we can revisit them in full. - bool AtBeginning = (I == BB->begin()); - if (!AtBeginning) --I; - - // If this instruction has a FrameIndex operand, we need to use that - // target machine register info object to eliminate it. - TRI.eliminateFrameIndex(MI, SPAdj, RS); - - // Reset the iterator if we were at the beginning of the BB. - if (AtBeginning) { - I = BB->begin(); - DoIncr = false; - } - - MI = 0; - break; - } + continue; + } - if (DoIncr) ++I; + if (I->getOpcode() == FrameSetupOpcode || + I->getOpcode() == FrameDestroyOpcode) { + // Remember how much SP has been adjusted to create the call + // frame. + int Size = I->getOperand(0).getImm(); + + if ((!StackGrowsDown && I->getOpcode() == FrameSetupOpcode) || + (StackGrowsDown && I->getOpcode() == FrameDestroyOpcode)) + Size = -Size; + + SPAdj += Size; + + MachineBasicBlock::iterator PrevI = prior(I); + TRI.eliminateCallFramePseudoInstr(Fn, *BB, I); + + // Visit the instructions created by eliminateCallFramePseudoInstr(). + I = next(PrevI); + continue; } + bool DoIncr = true; + + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) + if (MI->getOperand(i).isFrameIndex()) { + // Some instructions (e.g. inline asm instructions) can have + // multiple frame indices and/or cause eliminateFrameIndex + // to insert more than one instruction. We need the register + // scavenger to go through all of these instructions so that + // it can update its register information. We keep the + // iterator at the point before insertion so that we can + // revisit them in full. + bool AtBeginning = (I == BB->begin()); + if (!AtBeginning) --I; + + // If this instruction has a FrameIndex operand, we need to + // use that target machine register info object to eliminate + // it. + TRI.eliminateFrameIndex(MI, SPAdj, RS); + + // Reset the iterator if we were at the beginning of the BB. + if (AtBeginning) { + I = BB->begin(); + DoIncr = false; + } + + MI = 0; + break; + } + + if (DoIncr) ++I; + // Update register states. if (RS && MI) RS->forward(MI); } From evan.cheng at apple.com Mon Mar 3 18:07:48 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 3 Mar 2008 16:07:48 -0800 Subject: [llvm-commits] [llvm] r47862 - /llvm/trunk/lib/CodeGen/MachineInstr.cpp In-Reply-To: <16e5fdf90803031551u70c97d29v174a4fde1286869c@mail.gmail.com> References: <200803032214.m23MEXkF014824@zion.cs.uiuc.edu> <16e5fdf90803031522y7cd2c7c9nec7361de750844cf@mail.gmail.com> <72E52E44-C937-44C0-B9B6-5DA66057D71C@apple.com> <3D7E8268-D07B-4EAC-A8CD-BF2C4FEF1CA0@apple.com> <16e5fdf90803031551u70c97d29v174a4fde1286869c@mail.gmail.com> Message-ID: <4A631404-9AD7-4325-9E66-5C8998C04602@apple.com> Except it's not using an iterator... Evan On Mar 3, 2008, at 3:51 PM, Bill Wendling wrote: > On Mon, Mar 3, 2008 at 3:47 PM, Evan Cheng > wrote: >> Haven't you heard goto's are evil? :-) >> >> I think goto's can be used tastefully. However, it's definitely not >> the right situation to use it in this case. >> > Fair enough. I was 90% sure that that was going to be picked on when I > submitted it. I did it that way because how the machine operands are > stored in the machine instruction is non-intuitive and I didn't want > to make a mistake of having an invalid iterator. :-) > > -bw > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From evan.cheng at apple.com Mon Mar 3 18:39:46 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 3 Mar 2008 16:39:46 -0800 Subject: [llvm-commits] [llvm] r47870 - in /llvm/trunk/lib/CodeGen: MachineInstr.cpp PrologEpilogInserter.cpp In-Reply-To: <200803032357.m23NvSju018174@zion.cs.uiuc.edu> References: <200803032357.m23NvSju018174@zion.cs.uiuc.edu> Message-ID: <4942617B-8D8C-406E-AD5A-13D3B46EE8A4@apple.com> On Mar 3, 2008, at 3:57 PM, Bill Wendling wrote: > > + > + if (RegInfo->isSubRegister(IncomingReg, Reg) && MO.isKill()) { > + if (MO.isImplicit()) { > + // Remove this implicit use that marks the sub-register > + // "kill". Let the super-register take care of this > + // information. > + RemoveOperand(i); > + e = getNumOperands(); --e is sufficient. Evan > > + continue; > + } else { > + // The super-register is going to take care of this kill > + // information. > + MO.setIsKill(false); > + } > } > } > + > + ++i; > } > > // If the register already exists, then make sure it or its super- > register is > @@ -725,13 +728,14 @@ > if (Reg == IncomingReg) { > MO.setIsKill(); > return true; > - } else if (TargetRegisterInfo::isPhysicalRegister(Reg) && > - > TargetRegisterInfo::isPhysicalRegister(IncomingReg) && > - RegInfo->isSuperRegister(IncomingReg, Reg) && > - MO.isKill()) { > + } > + > + if (TargetRegisterInfo::isPhysicalRegister(Reg) && > + TargetRegisterInfo::isPhysicalRegister(IncomingReg) && > + RegInfo->isSuperRegister(IncomingReg, Reg) && > + MO.isKill()) > // A super-register kill already exists. > return true; > - } > } > } > > > Modified: llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp?rev=47870&r1=47869&r2=47870&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp (original) > +++ llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp Mon Mar 3 > 17:57:28 2008 > @@ -517,53 +517,63 @@ > for (MachineBasicBlock::iterator I = BB->begin(); I != BB- > >end(); ) { > MachineInstr *MI = I; > > - if (I->getOpcode() == FrameSetupOpcode || > - I->getOpcode() == FrameDestroyOpcode) { > - // Remember how much SP has been adjustment to create the > call frame. > - int Size = I->getOperand(0).getImm(); > - if ((!StackGrowsDown && I->getOpcode() == FrameSetupOpcode) > || > - (StackGrowsDown && I->getOpcode() == FrameDestroyOpcode)) > - Size = -Size; > - SPAdj += Size; > - MachineBasicBlock::iterator PrevI = prior(I); > - TRI.eliminateCallFramePseudoInstr(Fn, *BB, I); > - // Visit the instructions created by > eliminateCallFramePseudoInstr(). > - I = next(PrevI); > - MI = NULL; > - } else if (I->getOpcode() == TargetInstrInfo::DECLARE) { > + if (I->getOpcode() == TargetInstrInfo::DECLARE) { > // Ignore it. > ++I; > - } else { > - bool DoIncr = true; > - > - for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) > - if (MI->getOperand(i).isFrameIndex()) { > - // Some instructions (e.g. inline asm instructions) can > have > - // multiple frame indices and/or cause > eliminateFrameIndex to insert > - // more than one instruction. We need the register > scavenger to go > - // through all of these instructions so that it can > update its > - // register information. We keep the iterator at the > point before > - // insertion so that we can revisit them in full. > - bool AtBeginning = (I == BB->begin()); > - if (!AtBeginning) --I; > - > - // If this instruction has a FrameIndex operand, we > need to use that > - // target machine register info object to eliminate it. > - TRI.eliminateFrameIndex(MI, SPAdj, RS); > - > - // Reset the iterator if we were at the beginning of > the BB. > - if (AtBeginning) { > - I = BB->begin(); > - DoIncr = false; > - } > - > - MI = 0; > - break; > - } > + continue; > + } > > - if (DoIncr) ++I; > + if (I->getOpcode() == FrameSetupOpcode || > + I->getOpcode() == FrameDestroyOpcode) { > + // Remember how much SP has been adjusted to create the call > + // frame. > + int Size = I->getOperand(0).getImm(); > + > + if ((!StackGrowsDown && I->getOpcode() == FrameSetupOpcode) || > + (StackGrowsDown && I->getOpcode() == FrameDestroyOpcode)) > + Size = -Size; > + > + SPAdj += Size; > + > + MachineBasicBlock::iterator PrevI = prior(I); > + TRI.eliminateCallFramePseudoInstr(Fn, *BB, I); > + > + // Visit the instructions created by > eliminateCallFramePseudoInstr(). > + I = next(PrevI); > + continue; > } > > + bool DoIncr = true; > + > + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) > + if (MI->getOperand(i).isFrameIndex()) { > + // Some instructions (e.g. inline asm instructions) can have > + // multiple frame indices and/or cause eliminateFrameIndex > + // to insert more than one instruction. We need the register > + // scavenger to go through all of these instructions so that > + // it can update its register information. We keep the > + // iterator at the point before insertion so that we can > + // revisit them in full. > + bool AtBeginning = (I == BB->begin()); > + if (!AtBeginning) --I; > + > + // If this instruction has a FrameIndex operand, we need to > + // use that target machine register info object to eliminate > + // it. > + TRI.eliminateFrameIndex(MI, SPAdj, RS); > + > + // Reset the iterator if we were at the beginning of the BB. > + if (AtBeginning) { > + I = BB->begin(); > + DoIncr = false; > + } > + > + MI = 0; > + break; > + } > + > + if (DoIncr) ++I; > + > // Update register states. > if (RS && MI) RS->forward(MI); > } > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From evan.cheng at apple.com Mon Mar 3 18:40:35 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 04 Mar 2008 00:40:35 -0000 Subject: [llvm-commits] [llvm] r47871 - in /llvm/trunk/lib/Target/X86: X86ISelDAGToDAG.cpp X86InstrInfo.td Message-ID: <200803040040.m240eais019889@zion.cs.uiuc.edu> Author: evancheng Date: Mon Mar 3 18:40:35 2008 New Revision: 47871 URL: http://llvm.org/viewvc/llvm-project?rev=47871&view=rev Log: Remove -always-fold-and-in-test. Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp llvm/trunk/lib/Target/X86/X86InstrInfo.td Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=47871&r1=47870&r2=47871&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Mon Mar 3 18:40:35 2008 @@ -44,13 +44,6 @@ STATISTIC(NumFPKill , "Number of FP_REG_KILL instructions added"); STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor"); -namespace { - static cl::opt - AlwaysFoldAndInTest("always-fold-and-in-test", - cl::desc("Always fold and operation in test"), - cl::init(false), cl::Hidden); -} - //===----------------------------------------------------------------------===// // Pattern Matcher Implementation //===----------------------------------------------------------------------===// @@ -433,7 +426,7 @@ RModW = true; std::swap(N10, N11); } - RModW = RModW && N10.Val->isOperand(Chain.Val) && N10.hasOneUse() && + RModW = RModW && N10.Val->isOperandOf(Chain.Val) && N10.hasOneUse() && (N10.getOperand(1) == N2) && (N10.Val->getValueType(0) == N1.getValueType()); if (RModW) @@ -452,7 +445,7 @@ case X86ISD::SHRD: { SDOperand N10 = N1.getOperand(0); if (ISD::isNON_EXTLoad(N10.Val)) - RModW = N10.Val->isOperand(Chain.Val) && N10.hasOneUse() && + RModW = N10.Val->isOperandOf(Chain.Val) && N10.hasOneUse() && (N10.getOperand(1) == N2) && (N10.Val->getValueType(0) == N1.getValueType()); if (RModW) Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=47871&r1=47870&r2=47871&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Mon Mar 3 18:40:35 2008 @@ -255,7 +255,7 @@ // An 'and' node with a single use. def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ - return AlwaysFoldAndInTest || N->hasOneUse(); + return N->hasOneUse(); }]>; //===----------------------------------------------------------------------===// From evan.cheng at apple.com Mon Mar 3 18:41:45 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 04 Mar 2008 00:41:45 -0000 Subject: [llvm-commits] [llvm] r47872 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAGNodes.h lib/CodeGen/SelectionDAG/DAGCombiner.cpp lib/CodeGen/SelectionDAG/ScheduleDAG.cpp lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp lib/CodeGen/SelectionDAG/SelectionDAG.cpp Message-ID: <200803040041.m240fjGC019946@zion.cs.uiuc.edu> Author: evancheng Date: Mon Mar 3 18:41:45 2008 New Revision: 47872 URL: http://llvm.org/viewvc/llvm-project?rev=47872&view=rev Log: Rename isOperand() to isOperandOf() (and other similar methods). It always confuses me. Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=47872&r1=47871&r2=47872&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Mon Mar 3 18:41:45 2008 @@ -825,8 +825,8 @@ return SDOperand(Val, R); } - // isOperand - Return true if this node is an operand of N. - bool isOperand(SDNode *N) const; + // isOperandOf - Return true if this node is an operand of N. + bool isOperandOf(SDNode *N) const; /// getValueType - Return the ValueType of the referenced return value. /// @@ -969,19 +969,19 @@ /// value. This method ignores uses of other values defined by this operation. bool hasAnyUseOfValue(unsigned Value) const; - /// isOnlyUse - Return true if this node is the only use of N. + /// isOnlyUseOf - Return true if this node is the only use of N. /// - bool isOnlyUse(SDNode *N) const; + bool isOnlyUseOf(SDNode *N) const; - /// isOperand - Return true if this node is an operand of N. + /// isOperandOf - Return true if this node is an operand of N. /// - bool isOperand(SDNode *N) const; + bool isOperandOf(SDNode *N) const; - /// isPredecessor - Return true if this node is a predecessor of N. This node - /// is either an operand of N or it can be reached by recursively traversing - /// up the operands. + /// isPredecessorOf - Return true if this node is a predecessor of N. This + /// node is either an operand of N or it can be reached by recursively + /// traversing up the operands. /// NOTE: this is an expensive method. Use it carefully. - bool isPredecessor(SDNode *N) const; + bool isPredecessorOf(SDNode *N) const; /// getNumOperands - Return the number of values used by this operation. /// Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=47872&r1=47871&r2=47872&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Mar 3 18:41:45 2008 @@ -4030,7 +4030,7 @@ // Check #2. if (!isLoad) { SDOperand Val = cast(N)->getValue(); - if (Val == BasePtr || BasePtr.Val->isPredecessor(Val.Val)) + if (Val == BasePtr || BasePtr.Val->isPredecessorOf(Val.Val)) return false; } @@ -4041,7 +4041,7 @@ SDNode *Use = *I; if (Use == N) continue; - if (Use->isPredecessor(N)) + if (Use->isPredecessorOf(N)) return false; if (!((Use->getOpcode() == ISD::LOAD && @@ -4179,7 +4179,7 @@ continue; // Check for #2 - if (!Op->isPredecessor(N) && !N->isPredecessor(Op)) { + if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { SDOperand Result = isLoad ? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM) : DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); @@ -5008,8 +5008,8 @@ if (TheSelect->getOpcode() == ISD::SELECT) { // Check that the condition doesn't reach either load. If so, folding // this will induce a cycle into the DAG. - if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) && - !RLD->isPredecessor(TheSelect->getOperand(0).Val)) { + if (!LLD->isPredecessorOf(TheSelect->getOperand(0).Val) && + !RLD->isPredecessorOf(TheSelect->getOperand(0).Val)) { Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(), TheSelect->getOperand(0), LLD->getBasePtr(), RLD->getBasePtr()); @@ -5017,10 +5017,10 @@ } else { // Check that the condition doesn't reach either load. If so, folding // this will induce a cycle into the DAG. - if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) && - !RLD->isPredecessor(TheSelect->getOperand(0).Val) && - !LLD->isPredecessor(TheSelect->getOperand(1).Val) && - !RLD->isPredecessor(TheSelect->getOperand(1).Val)) { + if (!LLD->isPredecessorOf(TheSelect->getOperand(0).Val) && + !RLD->isPredecessorOf(TheSelect->getOperand(0).Val) && + !LLD->isPredecessorOf(TheSelect->getOperand(1).Val) && + !RLD->isPredecessorOf(TheSelect->getOperand(1).Val)) { Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(), TheSelect->getOperand(0), TheSelect->getOperand(1), Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp?rev=47872&r1=47871&r2=47872&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Mon Mar 3 18:41:45 2008 @@ -128,7 +128,7 @@ bool HasFlagUse = false; for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E; ++UI) - if (FlagVal.isOperand(*UI)) { + if (FlagVal.isOperandOf(*UI)) { HasFlagUse = true; NodeSUnit->FlaggedNodes.push_back(N); SUnitMap[N].push_back(NodeSUnit); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=47872&r1=47871&r2=47872&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Mon Mar 3 18:41:45 2008 @@ -472,7 +472,7 @@ I != E; ++I) { if (I->isCtrl) ChainPred = I->Dep; - else if (I->Dep->Node && I->Dep->Node->isOperand(LoadNode)) + else if (I->Dep->Node && I->Dep->Node->isOperandOf(LoadNode)) LoadPreds.push_back(SDep(I->Dep, I->Reg, I->Cost, false, false)); else NodePreds.push_back(SDep(I->Dep, I->Reg, I->Cost, false, false)); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=47872&r1=47871&r2=47872&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Mon Mar 3 18:41:45 2008 @@ -3674,9 +3674,9 @@ } -/// isOnlyUse - Return true if this node is the only use of N. +/// isOnlyUseOf - Return true if this node is the only use of N. /// -bool SDNode::isOnlyUse(SDNode *N) const { +bool SDNode::isOnlyUseOf(SDNode *N) const { bool Seen = false; for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { SDNode *User = *I; @@ -3691,14 +3691,14 @@ /// isOperand - Return true if this node is an operand of N. /// -bool SDOperand::isOperand(SDNode *N) const { +bool SDOperand::isOperandOf(SDNode *N) const { for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) if (*this == N->getOperand(i)) return true; return false; } -bool SDNode::isOperand(SDNode *N) const { +bool SDNode::isOperandOf(SDNode *N) const { for (unsigned i = 0, e = N->NumOperands; i != e; ++i) if (this == N->OperandList[i].Val) return true; @@ -3751,11 +3751,11 @@ } } -/// isPredecessor - Return true if this node is a predecessor of N. This node +/// isPredecessorOf - Return true if this node is a predecessor of N. This node /// is either an operand of N or it can be reached by recursively traversing /// up the operands. /// NOTE: this is an expensive method. Use it carefully. -bool SDNode::isPredecessor(SDNode *N) const { +bool SDNode::isPredecessorOf(SDNode *N) const { SmallPtrSet Visited; bool found = false; findPredecessor(N, this, found, Visited); From isanbard at gmail.com Mon Mar 3 18:47:20 2008 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 3 Mar 2008 16:47:20 -0800 Subject: [llvm-commits] [llvm] r47862 - /llvm/trunk/lib/CodeGen/MachineInstr.cpp In-Reply-To: <4A631404-9AD7-4325-9E66-5C8998C04602@apple.com> References: <200803032214.m23MEXkF014824@zion.cs.uiuc.edu> <16e5fdf90803031522y7cd2c7c9nec7361de750844cf@mail.gmail.com> <72E52E44-C937-44C0-B9B6-5DA66057D71C@apple.com> <3D7E8268-D07B-4EAC-A8CD-BF2C4FEF1CA0@apple.com> <16e5fdf90803031551u70c97d29v174a4fde1286869c@mail.gmail.com> <4A631404-9AD7-4325-9E66-5C8998C04602@apple.com> Message-ID: <16e5fdf90803031647t7d890eeal4626c00f23902123@mail.gmail.com> I meant it in the general case. From what I could gather, the operands are kept in at least two different lists. Anyway, no biggie. -bw On Mon, Mar 3, 2008 at 4:07 PM, Evan Cheng wrote: > Except it's not using an iterator... > > Evan > > > > On Mar 3, 2008, at 3:51 PM, Bill Wendling wrote: > > > On Mon, Mar 3, 2008 at 3:47 PM, Evan Cheng > > wrote: > >> Haven't you heard goto's are evil? :-) > >> > >> I think goto's can be used tastefully. However, it's definitely not > >> the right situation to use it in this case. > >> > > Fair enough. I was 90% sure that that was going to be picked on when I > > submitted it. I did it that way because how the machine operands are > > stored in the machine instruction is non-intuitive and I didn't want > > to make a mistake of having an invalid iterator. :-) > > > > -bw > > > > _______________________________________________ > > llvm-commits mailing list > > llvm-commits at cs.uiuc.edu > > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From evan.cheng at apple.com Mon Mar 3 18:47:45 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 04 Mar 2008 00:47:45 -0000 Subject: [llvm-commits] [llvm] r47874 - /llvm/trunk/test/CodeGen/X86/coalescer-commute4.ll Message-ID: <200803040047.m240ljlT020156@zion.cs.uiuc.edu> Author: evancheng Date: Mon Mar 3 18:47:45 2008 New Revision: 47874 URL: http://llvm.org/viewvc/llvm-project?rev=47874&view=rev Log: Add PR1501 test case. Added: llvm/trunk/test/CodeGen/X86/coalescer-commute4.ll Added: llvm/trunk/test/CodeGen/X86/coalescer-commute4.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/coalescer-commute4.ll?rev=47874&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/coalescer-commute4.ll (added) +++ llvm/trunk/test/CodeGen/X86/coalescer-commute4.ll Mon Mar 3 18:47:45 2008 @@ -0,0 +1,30 @@ +d; RUN: llvm-as < %s | llc -mtriple=i686-apple-darwin -mattr=+sse2 | not grep movaps +; PR1501 + +efine float @foo(i32* %x, float* %y, i32 %c) nounwind { +entry: + %tmp2132 = icmp eq i32 %c, 0 ; [#uses=2] + br i1 %tmp2132, label %bb23, label %bb.preheader + +bb.preheader: ; preds = %entry + %umax = select i1 %tmp2132, i32 1, i32 %c ; [#uses=1] + br label %bb + +bb: ; preds = %bb, %bb.preheader + %i.0.reg2mem.0 = phi i32 [ 0, %bb.preheader ], [ %indvar.next, %bb ] ; [#uses=3] + %res.0.reg2mem.0 = phi float [ 0.000000e+00, %bb.preheader ], [ %tmp14, %bb ] ; [#uses=1] + %tmp3 = getelementptr i32* %x, i32 %i.0.reg2mem.0 ; [#uses=1] + %tmp4 = load i32* %tmp3, align 4 ; [#uses=1] + %tmp45 = sitofp i32 %tmp4 to float ; [#uses=1] + %tmp8 = getelementptr float* %y, i32 %i.0.reg2mem.0 ; [#uses=1] + %tmp9 = load float* %tmp8, align 4 ; [#uses=1] + %tmp11 = mul float %tmp9, %tmp45 ; [#uses=1] + %tmp14 = add float %tmp11, %res.0.reg2mem.0 ; [#uses=2] + %indvar.next = add i32 %i.0.reg2mem.0, 1 ; [#uses=2] + %exitcond = icmp eq i32 %indvar.next, %umax ; [#uses=1] + br i1 %exitcond, label %bb23, label %bb + +bb23: ; preds = %bb, %entry + %res.0.reg2mem.1 = phi float [ 0.000000e+00, %entry ], [ %tmp14, %bb ] ; [#uses=1] + ret float %res.0.reg2mem.1 +} From isanbard at gmail.com Mon Mar 3 18:48:16 2008 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 04 Mar 2008 00:48:16 -0000 Subject: [llvm-commits] [llvm] r47875 - /llvm/trunk/lib/CodeGen/MachineInstr.cpp Message-ID: <200803040048.m240mG5E020178@zion.cs.uiuc.edu> Author: void Date: Mon Mar 3 18:48:15 2008 New Revision: 47875 URL: http://llvm.org/viewvc/llvm-project?rev=47875&view=rev Log: Did I say 'e = getNumOperands()'? I meant --e, of course. Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=47875&r1=47874&r2=47875&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Mon Mar 3 18:48:15 2008 @@ -703,7 +703,7 @@ // "kill". Let the super-register take care of this // information. RemoveOperand(i); - e = getNumOperands(); + --e; continue; } else { // The super-register is going to take care of this kill From evan.cheng at apple.com Mon Mar 3 21:14:39 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 3 Mar 2008 19:14:39 -0800 Subject: [llvm-commits] [llvm] r47798 - in /llvm/trunk/lib: CodeGen/SelectionDAG/LegalizeDAG.cpp Target/X86/X86ISelLowering.cpp Target/X86/X86ISelLowering.h Target/X86/X86InstrInfo.td In-Reply-To: <200803012152.m21LqZx4015849@zion.cs.uiuc.edu> References: <200803012152.m21LqZx4015849@zion.cs.uiuc.edu> Message-ID: <5DE3990E-5E66-4039-AD32-FAA37D1059AD@apple.com> What about i64 ISD::ATOMIC_LCS? Also, there are quite a few 80-col violations in X86InstrInfo.td. Evan On Mar 1, 2008, at 1:52 PM, Andrew Lenharth wrote: > Author: alenhar2 > Date: Sat Mar 1 15:52:34 2008 > New Revision: 47798 > > URL: http://llvm.org/viewvc/llvm-project?rev=47798&view=rev > Log: > all but CAS working on x86 > > Modified: > llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp > llvm/trunk/lib/Target/X86/X86ISelLowering.cpp > llvm/trunk/lib/Target/X86/X86ISelLowering.h > llvm/trunk/lib/Target/X86/X86InstrInfo.td > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=47798&r1=47797&r2=47798&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sat Mar 1 > 15:52:34 2008 > @@ -1165,23 +1165,24 @@ > assert(((Node->getNumOperands() == 4 && Node->getOpcode() == > ISD::ATOMIC_LCS) || > (Node->getNumOperands() == 3 && Node->getOpcode() == > ISD::ATOMIC_LAS) || > (Node->getNumOperands() == 3 && Node->getOpcode() == > ISD::ATOMIC_SWAP)) && > - "Invalid MemBarrier node!"); > + "Invalid Atomic node!"); > int num = Node->getOpcode() == ISD::ATOMIC_LCS ? 4 : 3; > - MVT::ValueType VT = Node->getValueType(0); > - switch (TLI.getOperationAction(ISD::ATOMIC_LCS, VT)) { > + SDOperand Ops[4]; > + for (int x = 0; x < num; ++x) > + Ops[x] = LegalizeOp(Node->getOperand(x)); > + Result = DAG.UpdateNodeOperands(Result, &Ops[0], num); > + > + switch (TLI.getOperationAction(Node->getOpcode(), Node- > >getValueType(0))) { > default: assert(0 && "This action is not supported yet!"); > - case TargetLowering::Legal: { > - SDOperand Ops[4]; > - for (int x = 0; x < num; ++x) > - Ops[x] = LegalizeOp(Node->getOperand(x)); > - Result = DAG.UpdateNodeOperands(Result, &Ops[0], num); > - AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); > - AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); > - return Result.getValue(Op.ResNo); > + case TargetLowering::Custom: > + Result = TLI.LowerOperation(Result, DAG); > + break; > + case TargetLowering::Legal: > break; > } > - } > - break; > + AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); > + AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); > + return Result.getValue(Op.ResNo); > } > > case ISD::Constant: { > > Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=47798&r1=47797&r2=47798&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) > +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sat Mar 1 > 15:52:34 2008 > @@ -283,6 +283,9 @@ > if (!Subtarget->hasSSE2()) > setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand); > > + setOperationAction(ISD::ATOMIC_LCS , MVT::i8, Custom); > + setOperationAction(ISD::ATOMIC_LCS , MVT::i16, Custom); > + setOperationAction(ISD::ATOMIC_LCS , MVT::i32, Custom); > > // Use the default ISD::LOCATION, ISD::DECLARE expansion. > setOperationAction(ISD::LOCATION, MVT::Other, Expand); > @@ -5345,11 +5348,35 @@ > return Op; > } > > +SDOperand X86TargetLowering::LowerCAS(SDOperand Op, SelectionDAG > &DAG) { > + MVT::ValueType T = cast(Op.Val)->getVT(); > + unsigned Reg; > + unsigned size; > + switch(T) { > + case MVT::i8: Reg = X86::AL; size = 1; break; > + case MVT::i16: Reg = X86::AX; size = 2; break; > + case MVT::i32: Reg = X86::EAX; size = 4; break; > + }; > + SDOperand cpIn = DAG.getCopyToReg(Op.getOperand(0), Reg, > + Op.getOperand(2), SDOperand()); > + SDOperand Ops[] = { cpIn.getValue(0), > + Op.getOperand(1), > + Op.getOperand(3), > + DAG.getTargetConstant(size, MVT::i8), > + cpIn.getValue(1) }; > + SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); > + SDOperand Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, Tys, Ops, 5); > + SDOperand cpOut = > + DAG.getCopyFromReg(Result.getValue(0), Reg, T, > Result.getValue(1)); > + return cpOut; > +} > + > /// LowerOperation - Provide custom lowering hooks for some > operations. > /// > SDOperand X86TargetLowering::LowerOperation(SDOperand Op, > SelectionDAG &DAG) { > switch (Op.getOpcode()) { > default: assert(0 && "Should not custom lower this!"); > + case ISD::ATOMIC_LCS: return LowerCAS(Op,DAG); > case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); > case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); > case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, > DAG); > @@ -5454,6 +5481,7 @@ > case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN"; > case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN"; > case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m"; > + case X86ISD::LCMPXCHG_DAG: return "x86ISD::LCMPXCHG_DAG"; > } > } > > > Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=47798&r1=47797&r2=47798&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original) > +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Sat Mar 1 15:52:34 > 2008 > @@ -208,6 +208,9 @@ > // operand #3 optional in flag > TC_RETURN, > > + // compare and swap > + LCMPXCHG_DAG, > + > // Store FP control world into i16 memory > FNSTCW16m > }; > @@ -540,6 +543,7 @@ > SDOperand LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG); > SDOperand LowerCTLZ(SDOperand Op, SelectionDAG &DAG); > SDOperand LowerCTTZ(SDOperand Op, SelectionDAG &DAG); > + SDOperand LowerCAS(SDOperand Op, SelectionDAG &DAG); > SDNode *ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG); > SDNode *ExpandREADCYCLECOUNTER(SDNode *N, SelectionDAG &DAG); > }; > > Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=47798&r1=47797&r2=47798&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) > +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Sat Mar 1 15:52:34 2008 > @@ -35,6 +35,9 @@ > [SDTCisVT<0, i8>, > SDTCisVT<1, i8>, SDTCisVT<2, > i32>]>; > > +def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>, > + SDTCisVT<2, i8>]>; > + > def SDTX86Ret : SDTypeProfile<0, 1, [SDTCisVT<0, i16>]>; > > def SDT_X86CallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; > @@ -69,6 +72,10 @@ > [SDNPHasChain]>; > def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>; > > +def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas, > + [SDNPHasChain, SDNPInFlag, SDNPOutFlag, > SDNPMayStore, > + SDNPMayLoad]>; > + > def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret, > [SDNPHasChain, SDNPOptInFlag]>; > > @@ -2539,28 +2546,29 @@ > // Atomic support > // > > -//FIXME: Please check the format > - > -let Defs = [EAX], Uses = [EAX] in { > -def CMPXCHG32 : I<0xB1, Pseudo, (outs), (ins GR32:$ptr, GR32:$swap), > - "cmpxchgl $swap,($ptr)", []>, TB; > -def LCMPXCHG32 : I<0xB1, Pseudo, (outs), (ins GR32:$ptr, GR32:$swap), > - "lock cmpxchgl $swap,($ptr)", []>, TB, LOCK; > +//FIXME: Please check the format Pseudo is certainly wrong, but the > opcode and > +// prefixes should be correct > +let Defs = [EAX, EFLAGS], Uses = [EAX] in { > +def CMPXCHG32 : I<0xB1, Pseudo, (outs), (ins i32mem:$ptr, > GR32:$swap), > + "cmpxchgl $swap,$ptr", []>, TB; > +def LCMPXCHG32 : I<0xB1, Pseudo, (outs), (ins i32mem:$ptr, > GR32:$swap), > + "lock cmpxchgl $swap,$ptr", [(X86cas addr:$ptr, > GR32:$swap, 4)]>, TB, LOCK; > } > -let Defs = [AX], Uses = [AX] in { > -def CMPXCHG16 : I<0xB1, Pseudo, (outs), (ins GR32:$ptr, GR16:$swap), > + > +let Defs = [AX, EFLAGS], Uses = [AX] in { > +def CMPXCHG16 : I<0xB1, Pseudo, (outs), (ins i16mem:$ptr, > GR16:$swap), > "cmpxchgw $swap,($ptr)", []>, TB, OpSize; > -def LCMPXCHG16 : I<0xB1, Pseudo, (outs), (ins GR32:$ptr, GR16:$swap), > - "cmpxchgw $swap,($ptr)", []>, TB, OpSize, LOCK; > +def LCMPXCHG16 : I<0xB1, Pseudo, (outs), (ins i16mem:$ptr, > GR16:$swap), > + "lock cmpxchgw $swap,$ptr", [(X86cas addr:$ptr, > GR16:$swap, 2)]>, TB, OpSize, LOCK; > } > -let Defs = [AL], Uses = [AL] in { > -def CMPXCHG8 : I<0xB0, Pseudo, (outs), (ins GR32:$ptr, GR8:$swap), > +let Defs = [AL, EFLAGS], Uses = [AL] in { > +def CMPXCHG8 : I<0xB0, Pseudo, (outs), (ins i8mem:$ptr, GR8:$swap), > "cmpxchgb $swap,($ptr)", []>, TB; > -def LCMPXCHG8 : I<0xB0, Pseudo, (outs), (ins GR32:$ptr, GR8:$swap), > - "cmpxchgb $swap,($ptr)", []>, TB, LOCK; > +def LCMPXCHG8 : I<0xB0, Pseudo, (outs), (ins i8mem:$ptr, GR8:$swap), > + "lock cmpxchgb $swap,$ptr", [(X86cas addr:$ptr, > GR8:$swap, 1)]>, TB, LOCK; > } > > -let Constraints = "$val = $dst" in { > +let Constraints = "$val = $dst", Defs = [EFLAGS] in { > def LXADD32 : I<0xC1, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, > GR32:$val), > "lock xadd $val, $ptr", > [(set GR32:$dst, (atomic_las_32 addr:$ptr, > GR32:$val))]>, > @@ -2598,23 +2606,6 @@ > "lock xchg $val, $ptr", []>; > } > > -//FIXME: these are a hack until the patterns using the LCMPXCHG > written > -let Defs = [EAX], Uses = [EAX] in > -def PLCMPXCHG32 : I<0, Pseudo, (outs GR32:$dst), > - (ins i32mem:$ptr, GR32:$cmp, GR32:$swap), > - "movl $cmp, %eax \n lock \n cmpxchgl $swap,$ptr > \n movl %eax, $dst", > - [(set GR32:$dst, (atomic_lcs_32 addr:$ptr, > GR32:$cmp, GR32:$swap))]>; > -let Defs = [AX] in > -def PLCMPXCHG16 : I<0, Pseudo, (outs GR16:$dst), > - (ins i16mem:$ptr, GR16:$cmp, GR16:$swap), > - "movw $cmp, %ax \n lock \n cmpxchgw $swap,$ptr \n > movw %ax, $dst", > - [(set GR16:$dst, (atomic_lcs_16 addr:$ptr, > GR16:$cmp, GR16:$swap))]>; > -let Defs = [AL] in > -def PLCMPXCHG8 : I<0, Pseudo, (outs GR8:$dst), > - (ins i8mem:$ptr, GR8:$cmp, GR8:$swap), > - "movb $cmp, %al \n lock cmpxchgb $swap,$ptr \n > movb %al, $dst", > - [(set GR8:$dst, (atomic_lcs_8 addr:$ptr, > GR8:$cmp, GR8:$swap))]>; > - > // > = > = > = > ----------------------------------------------------------------------= > ==// > // Non-Instruction Patterns > // > = > = > = > ----------------------------------------------------------------------= > ==// > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From evan.cheng at apple.com Mon Mar 3 21:19:19 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 04 Mar 2008 03:19:19 -0000 Subject: [llvm-commits] [llvm] r47877 - /llvm/trunk/include/llvm/Intrinsics.td Message-ID: <200803040319.m243JJ7O025171@zion.cs.uiuc.edu> Author: evancheng Date: Mon Mar 3 21:19:19 2008 New Revision: 47877 URL: http://llvm.org/viewvc/llvm-project?rev=47877&view=rev Log: Fix 80 column violations. Modified: llvm/trunk/include/llvm/Intrinsics.td Modified: llvm/trunk/include/llvm/Intrinsics.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Intrinsics.td?rev=47877&r1=47876&r2=47877&view=diff ============================================================================== --- llvm/trunk/include/llvm/Intrinsics.td (original) +++ llvm/trunk/include/llvm/Intrinsics.td Mon Mar 3 21:19:19 2008 @@ -265,18 +265,23 @@ //===------------------------- Atomic Intrinsics --------------------------===// // def int_memory_barrier : Intrinsic<[llvm_void_ty, llvm_i1_ty, llvm_i1_ty, - llvm_i1_ty, llvm_i1_ty, llvm_i1_ty], []>; + llvm_i1_ty, llvm_i1_ty, llvm_i1_ty], []>; -def int_atomic_lcs : Intrinsic<[llvm_anyint_ty, LLVMPointerType>, +def int_atomic_lcs : Intrinsic<[llvm_anyint_ty, + LLVMPointerType>, LLVMMatchType<0>, LLVMMatchType<0>], - [IntrWriteArgMem]>, GCCBuiltin<"__sync_val_compare_and_swap">; -def int_atomic_las : Intrinsic<[llvm_anyint_ty, LLVMPointerType>, + [IntrWriteArgMem]>, + GCCBuiltin<"__sync_val_compare_and_swap">; +def int_atomic_las : Intrinsic<[llvm_anyint_ty, + LLVMPointerType>, LLVMMatchType<0>], - [IntrWriteArgMem]>, GCCBuiltin<"__sync_fetch_and_add">; -def int_atomic_swap : Intrinsic<[llvm_anyint_ty, LLVMPointerType>, + [IntrWriteArgMem]>, + GCCBuiltin<"__sync_fetch_and_add">; +def int_atomic_swap : Intrinsic<[llvm_anyint_ty, + LLVMPointerType>, LLVMMatchType<0>], - [IntrWriteArgMem]>, GCCBuiltin<"__sync_lock_test_and_set">; - + [IntrWriteArgMem]>, + GCCBuiltin<"__sync_lock_test_and_set">; //===-------------------------- Other Intrinsics --------------------------===// // From evan.cheng at apple.com Mon Mar 3 21:20:06 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 04 Mar 2008 03:20:06 -0000 Subject: [llvm-commits] [llvm] r47878 - /llvm/trunk/lib/Target/X86/X86InstrInfo.td Message-ID: <200803040320.m243K6XD025214@zion.cs.uiuc.edu> Author: evancheng Date: Mon Mar 3 21:20:06 2008 New Revision: 47878 URL: http://llvm.org/viewvc/llvm-project?rev=47878&view=rev Log: 80 column violations. Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=47878&r1=47877&r2=47878&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Mon Mar 3 21:20:06 2008 @@ -2553,20 +2553,23 @@ def CMPXCHG32 : I<0xB1, Pseudo, (outs), (ins i32mem:$ptr, GR32:$swap), "cmpxchgl $swap,$ptr", []>, TB; def LCMPXCHG32 : I<0xB1, Pseudo, (outs), (ins i32mem:$ptr, GR32:$swap), - "lock cmpxchgl $swap,$ptr", [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK; + "lock cmpxchgl $swap,$ptr", + [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK; } let Defs = [AX, EFLAGS], Uses = [AX] in { def CMPXCHG16 : I<0xB1, Pseudo, (outs), (ins i16mem:$ptr, GR16:$swap), "cmpxchgw $swap,($ptr)", []>, TB, OpSize; def LCMPXCHG16 : I<0xB1, Pseudo, (outs), (ins i16mem:$ptr, GR16:$swap), - "lock cmpxchgw $swap,$ptr", [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK; + "lock cmpxchgw $swap,$ptr", + [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK; } let Defs = [AL, EFLAGS], Uses = [AL] in { def CMPXCHG8 : I<0xB0, Pseudo, (outs), (ins i8mem:$ptr, GR8:$swap), "cmpxchgb $swap,($ptr)", []>, TB; def LCMPXCHG8 : I<0xB0, Pseudo, (outs), (ins i8mem:$ptr, GR8:$swap), - "lock cmpxchgb $swap,$ptr", [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK; + "lock cmpxchgb $swap,$ptr", + [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK; } let Constraints = "$val = $dst", Defs = [EFLAGS] in { From evan.cheng at apple.com Mon Mar 3 21:24:24 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 3 Mar 2008 19:24:24 -0800 Subject: [llvm-commits] [llvm-gcc-4.2] r47801 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp In-Reply-To: <200803012336.m21NaM6B018640@zion.cs.uiuc.edu> References: <200803012336.m21NaM6B018640@zion.cs.uiuc.edu> Message-ID: <8EDB1B64-6A30-433B-A606-D108BD0C9B7E@apple.com> This breaks x86-64. libgomp/critical compiles to: define void @GOMP_critical_name_start(i8** %pptr) nounwind { entry: ... tail call i64 @llvm.atomic.lcs.i64( i8** %pptr, i64 0, i64 %tmp1314 ) ; :0 [#uses=1] ... ret void } Evan On Mar 1, 2008, at 3:36 PM, Andrew Lenharth wrote: > Author: alenhar2 > Date: Sat Mar 1 17:36:21 2008 > New Revision: 47801 > > URL: http://llvm.org/viewvc/llvm-project?rev=47801&view=rev > Log: > turn on some atomics for a couple platforms > > Modified: > llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp > > Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=47801&r1=47800&r2=47801&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) > +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Sat Mar 1 17:36:21 2008 > @@ -4294,7 +4294,7 @@ > C, C + 5); > return true; > } > -#if 0 //FIXME: these break the build for backends that haven't > implemented them > +#if defined(TARGET_386) || defined(TARGET_ALPHA) > //gcc uses many names for the sync intrinsics > case BUILT_IN_VAL_COMPARE_AND_SWAP_1: > case BUILT_IN_VAL_COMPARE_AND_SWAP_2: > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From evan.cheng at apple.com Mon Mar 3 21:25:16 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 04 Mar 2008 03:25:16 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r47879 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Message-ID: <200803040325.m243PGJ2025366@zion.cs.uiuc.edu> Author: evancheng Date: Mon Mar 3 21:25:15 2008 New Revision: 47879 URL: http://llvm.org/viewvc/llvm-project?rev=47879&view=rev Log: Unbreak x86-64 build. Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=47879&r1=47878&r2=47879&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Mon Mar 3 21:25:15 2008 @@ -4294,7 +4294,7 @@ C, C + 5); return true; } -#if defined(TARGET_386) || defined(TARGET_ALPHA) +#if defined(TARGET_ALPHA) //gcc uses many names for the sync intrinsics case BUILT_IN_VAL_COMPARE_AND_SWAP_1: case BUILT_IN_VAL_COMPARE_AND_SWAP_2: From evan.cheng at apple.com Tue Mar 4 01:59:15 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 04 Mar 2008 07:59:15 -0000 Subject: [llvm-commits] [llvm] r47881 - /llvm/trunk/test/CodeGen/X86/coalescer-commute4.ll Message-ID: <200803040759.m247xFII000711@zion.cs.uiuc.edu> Author: evancheng Date: Tue Mar 4 01:59:13 2008 New Revision: 47881 URL: http://llvm.org/viewvc/llvm-project?rev=47881&view=rev Log: Fix broken test. Modified: llvm/trunk/test/CodeGen/X86/coalescer-commute4.ll Modified: llvm/trunk/test/CodeGen/X86/coalescer-commute4.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/coalescer-commute4.ll?rev=47881&r1=47880&r2=47881&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/coalescer-commute4.ll (original) +++ llvm/trunk/test/CodeGen/X86/coalescer-commute4.ll Tue Mar 4 01:59:13 2008 @@ -1,4 +1,4 @@ -d; RUN: llvm-as < %s | llc -mtriple=i686-apple-darwin -mattr=+sse2 | not grep movaps +; RUN: llvm-as < %s | llc -mtriple=i686-apple-darwin -mattr=+sse2 | not grep movaps ; PR1501 efine float @foo(i32* %x, float* %y, i32 %c) nounwind { From evan.cheng at apple.com Tue Mar 4 02:01:56 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 04 Mar 2008 08:01:56 -0000 Subject: [llvm-commits] [llvm] r47882 - /llvm/trunk/test/CodeGen/X86/coalescer-commute4.ll Message-ID: <200803040801.m2481u3w000813@zion.cs.uiuc.edu> Author: evancheng Date: Tue Mar 4 02:01:56 2008 New Revision: 47882 URL: http://llvm.org/viewvc/llvm-project?rev=47882&view=rev Log: Really fix the test. Modified: llvm/trunk/test/CodeGen/X86/coalescer-commute4.ll Modified: llvm/trunk/test/CodeGen/X86/coalescer-commute4.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/coalescer-commute4.ll?rev=47882&r1=47881&r2=47882&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/coalescer-commute4.ll (original) +++ llvm/trunk/test/CodeGen/X86/coalescer-commute4.ll Tue Mar 4 02:01:56 2008 @@ -1,7 +1,7 @@ ; RUN: llvm-as < %s | llc -mtriple=i686-apple-darwin -mattr=+sse2 | not grep movaps ; PR1501 -efine float @foo(i32* %x, float* %y, i32 %c) nounwind { +define float @foo(i32* %x, float* %y, i32 %c) nounwind { entry: %tmp2132 = icmp eq i32 %c, 0 ; [#uses=2] br i1 %tmp2132, label %bb23, label %bb.preheader From evan.cheng at apple.com Tue Mar 4 02:05:30 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 04 Mar 2008 08:05:30 -0000 Subject: [llvm-commits] [llvm] r47883 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <200803040805.m2485Uhk000936@zion.cs.uiuc.edu> Author: evancheng Date: Tue Mar 4 02:05:30 2008 New Revision: 47883 URL: http://llvm.org/viewvc/llvm-project?rev=47883&view=rev Log: Refactor ExpandConstantFP so it can optimize load from constpool of types larger than f64 into extload from smaller types. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=47883&r1=47882&r2=47883&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Mar 4 02:05:30 2008 @@ -488,34 +488,37 @@ // the constant pool as a float, even if it's is statically typed as a // double. MVT::ValueType VT = CFP->getValueType(0); - bool isDouble = VT == MVT::f64; ConstantFP *LLVMC = ConstantFP::get(MVT::getTypeForValueType(VT), CFP->getValueAPF()); if (!UseCP) { if (VT!=MVT::f64 && VT!=MVT::f32) assert(0 && "Invalid type expansion"); return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt().getZExtValue(), - isDouble ? MVT::i64 : MVT::i32); + (VT == MVT::f64) ? MVT::i64 : MVT::i32); } - if (isDouble && CFP->isValueValidForType(MVT::f32, CFP->getValueAPF()) && - // Only do this if the target has a native EXTLOAD instruction from f32. - // Do not try to be clever about long doubles (so far) - TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) { - LLVMC = cast(ConstantExpr::getFPTrunc(LLVMC,Type::FloatTy)); - VT = MVT::f32; - Extend = true; + MVT::ValueType OrigVT = VT; + MVT::ValueType SVT = VT; + while (SVT != MVT::f32) { + SVT = (unsigned)SVT - 1; + if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) && + // Only do this if the target has a native EXTLOAD instruction from + // smaller type. + TLI.isLoadXLegal(ISD::EXTLOAD, SVT)) { + const Type *SType = MVT::getTypeForValueType(SVT); + LLVMC = cast(ConstantExpr::getFPTrunc(LLVMC, SType)); + VT = SVT; + Extend = true; + } } SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); - if (Extend) { - return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), + if (Extend) + return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, DAG.getEntryNode(), CPIdx, PseudoSourceValue::getConstantPool(), - 0, MVT::f32); - } else { - return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, - PseudoSourceValue::getConstantPool(), 0); - } + 0, VT); + return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx, + PseudoSourceValue::getConstantPool(), 0); } From romix.llvm at googlemail.com Tue Mar 4 05:19:45 2008 From: romix.llvm at googlemail.com (Roman Levenstein) Date: Tue, 04 Mar 2008 11:19:45 -0000 Subject: [llvm-commits] [llvm] r47884 - /llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Message-ID: <200803041119.m24BJj4H018854@zion.cs.uiuc.edu> Author: romix Date: Tue Mar 4 05:19:43 2008 New Revision: 47884 URL: http://llvm.org/viewvc/llvm-project?rev=47884&view=rev Log: Some improvements related to the computation of heights, depths of SUnits. The basic idea is that all these algorithms are computing the longest paths from the root node or to the exit node. Therefore the existing implementation that uses and iterative and potentially exponential algorithm was changed to a well-known graph algorithm based on dynamic programming. It has a linear run-time. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp?rev=47884&r1=47883&r2=47884&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Tue Mar 4 05:19:43 2008 @@ -232,39 +232,111 @@ } } +/// CalculateDepths - compute depths using algorithms for the longest +/// paths in the DAG void ScheduleDAG::CalculateDepths() { - std::vector > WorkList; - for (unsigned i = 0, e = SUnits.size(); i != e; ++i) - if (SUnits[i].Preds.empty()) - WorkList.push_back(std::make_pair(&SUnits[i], 0U)); + unsigned DAGSize = SUnits.size(); + std::vector InDegree(DAGSize); + std::vector WorkList; + WorkList.reserve(DAGSize); + + // Initialize the data structures + for (unsigned i = 0, e = DAGSize; i != e; ++i) { + SUnit *SU = &SUnits[i]; + int NodeNum = SU->NodeNum; + unsigned Degree = SU->Preds.size(); + InDegree[NodeNum] = Degree; + SU->Depth = 0; + + // Is it a node without dependencies? + if (Degree == 0) { + assert(SU->Preds.empty() && "SUnit should have no predecessors"); + // Collect leaf nodes + WorkList.push_back(SU); + } + } + // Process nodes in the topological order while (!WorkList.empty()) { - SUnit *SU = WorkList.back().first; - unsigned Depth = WorkList.back().second; + SUnit *SU = WorkList.back(); WorkList.pop_back(); - if (SU->Depth == 0 || Depth > SU->Depth) { - SU->Depth = Depth; - for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); - I != E; ++I) - WorkList.push_back(std::make_pair(I->Dep, Depth+1)); + unsigned &SUDepth = SU->Depth; + + // Use dynamic programming: + // When current node is being processed, all of its dependencies + // are already processed. + // So, just iterate over all predecessors and take the longest path + for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); + I != E; ++I) { + unsigned PredDepth = I->Dep->Depth; + if (PredDepth+1 > SUDepth) { + SUDepth = PredDepth + 1; + } + } + + // Update InDegrees of all nodes depending on current SUnit + for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); + I != E; ++I) { + SUnit *SU = I->Dep; + if (!--InDegree[SU->NodeNum]) + // If all dependencies of the node are processed already, + // then the longest path for the node can be computed now + WorkList.push_back(SU); } } } +/// CalculateHeights - compute heights using algorithms for the longest +/// paths in the DAG void ScheduleDAG::CalculateHeights() { - std::vector > WorkList; - SUnit *Root = SUnitMap[DAG.getRoot().Val].front(); - WorkList.push_back(std::make_pair(Root, 0U)); + unsigned DAGSize = SUnits.size(); + std::vector InDegree(DAGSize); + std::vector WorkList; + WorkList.reserve(DAGSize); + + // Initialize the data structures + for (unsigned i = 0, e = DAGSize; i != e; ++i) { + SUnit *SU = &SUnits[i]; + int NodeNum = SU->NodeNum; + unsigned Degree = SU->Succs.size(); + InDegree[NodeNum] = Degree; + SU->Height = 0; + + // Is it a node without dependencies? + if (Degree == 0) { + assert(SU->Succs.empty() && "Something wrong"); + assert(WorkList.empty() && "Should be empty"); + // Collect leaf nodes + WorkList.push_back(SU); + } + } + // Process nodes in the topological order while (!WorkList.empty()) { - SUnit *SU = WorkList.back().first; - unsigned Height = WorkList.back().second; + SUnit *SU = WorkList.back(); WorkList.pop_back(); - if (SU->Height == 0 || Height > SU->Height) { - SU->Height = Height; - for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); - I != E; ++I) - WorkList.push_back(std::make_pair(I->Dep, Height+1)); + unsigned &SUHeight = SU->Height; + + // Use dynamic programming: + // When current node is being processed, all of its dependencies + // are already processed. + // So, just iterate over all successors and take the longest path + for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); + I != E; ++I) { + unsigned SuccHeight = I->Dep->Height; + if (SuccHeight+1 > SUHeight) { + SUHeight = SuccHeight + 1; + } + } + + // Update InDegrees of all nodes depending on current SUnit + for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); + I != E; ++I) { + SUnit *SU = I->Dep; + if (!--InDegree[SU->NodeNum]) + // If all dependencies of the node are processed already, + // then the longest path for the node can be computed now + WorkList.push_back(SU); } } } From romix.llvm at googlemail.com Tue Mar 4 05:44:49 2008 From: romix.llvm at googlemail.com (Roman Levenstein) Date: Tue, 4 Mar 2008 12:44:49 +0100 Subject: [llvm-commits] Fwd: Patch for review: Speeding up ScheduleDAG computations In-Reply-To: References: <522BCA72-6445-4857-BE7B-019B841AA9DB@apple.com> Message-ID: Hi, 2008/3/3, Dan Gohman : > > On Mar 3, 2008, at 1:31 PM, Chris Lattner wrote: > > > On Mar 3, 2008, at 1:26 PM, Evan Cheng wrote: > >> Thanks. > >> > >> Using std::set<> makes me queasy. :-) Too bad it doesn't seem > >> possible to use SmallPtrSet (elements are not in sorted order). > > > > I'm sad to say that std::set is probably the best thing we have right > > now that provides priority queue + removal from the middle support. > > > > There's make_heap/push_heap/etc. in that let a > plain std::vector (or a SmallVector I guess) be used as a heap. Yes, this is possible but produces much more overhead than std::set on my tests. BTW, this approach is used in DAGISel.inc files generated by tablegen. I tried to changed it to std::set as well and ,again, it works much (25%-30%) faster on BBs with few hundreds or thousends instructions. I'd like to understand better why Evan and Chris are some much against std::set? From some mails I got the impression that std::set implementation is very inefficient on Darwin or PowerPC? Is it correct? Or do you dislike that fact that std::set uses dynamic memory allocation extensively? > > Does anyone know of a better data structure to implement these > > operations? Even if you don't volunteer to implement it, we can add > > it to the open projects page. In principle, we need something like a balanced tree. And since we want to be able to remove from the middle, I'd say that it should not be mapped to something linear like std::vector, as it is done by make_heap, since it involves quite some overhead and a lot of copying around. Finding/creating a tree implementation is not such a big deal. But again, why it would be better than std::set, that anyway seems to be implemented internally as a read-black tree? To conclude: Guys, I'm still waiting for a review and approval of the two pending patches for ScheduleDAGList and ScheduleDAGRRList. Both of them use std::set approach among other things. - Roman From romix.llvm at googlemail.com Tue Mar 4 05:56:44 2008 From: romix.llvm at googlemail.com (Roman Levenstein) Date: Tue, 4 Mar 2008 12:56:44 +0100 Subject: [llvm-commits] Patch for review: Speeding up ScheduleDAG computations In-Reply-To: References: <200803031053.00270.dag@cray.com> Message-ID: Hi, 2008/3/3, Tanya Lattner : > Please review and test, if possible. I have problems with running the > llvm-test test-suite. When I to run it (and keep in mind, I never did > it before), I always get the following error messages on my X86/Ubuntu > system: > make[4]: *** No rule to make target > `Output/sse.expandfft.linked.rbc', needed > by > `Output/sse.expandfft.linked.bc'. > Stop. > > Please keep in mind that all proposed patches should have been tested before > submitting. This includes llvm-test and 'make check'. > http://llvm.org/docs/DeveloperPolicy.html#quality Sure! > This will make Evan's job easier ;) > > As for the error in llvm-test that you are seeing, can you use 'make > VERBOSE=1 TEST=nightly report' and post more details on what make is > running? It looks like an error in configuration. Did you reconfigure once > you set llvm-gcc path? Thanks for the advice, Tanya. OK. Here is what I did: First I reconfigured: ../../../llvm/projects/llvm-test/configure --with-llvmgccdir=/opt/llvm-gcc Than I execute 'make VERBOSE=1 TEST=nightly report' and get the following: make[1]: Entering directory `/opt/llvm.build/projects/llvm-test' if [ ! -f SingleSource/Makefile ]; \ then \ /opt/llvm/autoconf/mkinstalldirs SingleSource; \ cp /opt/llvm/projects/llvm-test/SingleSource/Makefile SingleSource/Makefile; \ fi; \ make -C SingleSource test -w make[2]: Entering directory `/opt/llvm.build/projects/llvm-test/SingleSource' if [ ! -f UnitTests/Makefile ]; \ then \ /opt/llvm/autoconf/mkinstalldirs UnitTests; \ cp /opt/llvm/projects/llvm-test/SingleSource/UnitTests/Makefile UnitTests/Makefile; \ fi; \ make -C UnitTests test -w make[3]: Entering directory `/opt/llvm.build/projects/llvm-test/SingleSource/UnitTests' for dir in Vector SignlessTypes Threads; do \ if [ ! -f $dir/Makefile ]; \ then \ /opt/llvm/autoconf/mkinstalldirs $dir; \ cp /opt/llvm/projects/llvm-test/SingleSource/UnitTests/$dir/Makefile $dir/Makefile; \ fi; \ (make -C $dir test -w) || exit 1; \ done make[4]: Entering directory `/opt/llvm.build/projects/llvm-test/SingleSource/UnitTests/Vector' for dir in SSE; do \ if [ ! -f $dir/Makefile ]; \ then \ /opt/llvm/autoconf/mkinstalldirs $dir; \ cp /opt/llvm/projects/llvm-test/SingleSource/UnitTests/Vector/$dir/Makefile $dir/Makefile; \ fi; \ (make -C $dir test -w) || exit 1; \ done make[5]: Entering directory `/opt/llvm.build/projects/llvm-test/SingleSource/UnitTests/Vector/SSE' make[5]: *** No rule to make target `Output/sse.expandfft.linked.rbc', needed by `Output/sse.expandfft.linked.bc'. Stop. make[5]: Leaving directory `/opt/llvm.build/projects/llvm-test/SingleSource/UnitTests/Vector/SSE' make[4]: *** [test] Error 1 make[4]: Leaving directory `/opt/llvm.build/projects/llvm-test/SingleSource/UnitTests/Vector' make[3]: *** [test] Error 1 make[3]: Leaving directory `/opt/llvm.build/projects/llvm-test/SingleSource/UnitTests' make[2]: *** [UnitTests/.maketest] Error 2 make[2]: Leaving directory `/opt/llvm.build/projects/llvm-test/SingleSource' make[1]: *** [SingleSource/.maketest] Error 2 make[1]: Leaving directory `/opt/llvm.build/projects/llvm-test' Any ideas about what I'm doing wrong? Thanks, Roman From zhousheng00 at gmail.com Tue Mar 4 07:44:11 2008 From: zhousheng00 at gmail.com (Zhou Sheng) Date: Tue, 4 Mar 2008 21:44:11 +0800 Subject: [llvm-commits] [test-suite] r47846 - /test-suite/trunk/RunSafely.sh Message-ID: <8abe0dc60803040544o77e1b354p3caa09daa7909ea8@mail.gmail.com> Hi, > @@ -99,7 +99,7 @@ > # necessary I/O redirection. > # > PWD=`pwd` > -COMMAND="$PROGRAM $*" > +COMMAND="$PWD/$PROGRAM $*" This is incorrect when PROGRAM=/xxx/bin/lli > if [ "$SYSTEM" = "Darwin" ]; then > COMMAND="${DIR}TimedExec.sh $ULIMIT $PWD $COMMAND" > fi -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20080304/3f9e084c/attachment.html From lauro.venancio at gmail.com Tue Mar 4 08:38:02 2008 From: lauro.venancio at gmail.com (Lauro Ramos Venancio) Date: Tue, 04 Mar 2008 14:38:02 -0000 Subject: [llvm-commits] [test-suite] r47885 - /test-suite/trunk/RunSafely.sh Message-ID: <200803041438.m24Ec2Nn024648@zion.cs.uiuc.edu> Author: laurov Date: Tue Mar 4 08:38:01 2008 New Revision: 47885 URL: http://llvm.org/viewvc/llvm-project?rev=47885&view=rev Log: Fix JIT tests. Modified: test-suite/trunk/RunSafely.sh Modified: test-suite/trunk/RunSafely.sh URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/RunSafely.sh?rev=47885&r1=47884&r2=47885&view=diff ============================================================================== --- test-suite/trunk/RunSafely.sh (original) +++ test-suite/trunk/RunSafely.sh Tue Mar 4 08:38:01 2008 @@ -99,17 +99,11 @@ # necessary I/O redirection. # PWD=`pwd` -COMMAND="$PWD/$PROGRAM $*" +COMMAND="$PROGRAM $*" if [ "$SYSTEM" = "Darwin" ]; then COMMAND="${DIR}TimedExec.sh $ULIMIT $PWD $COMMAND" fi -rm -f "$PWD/${PROGRAM}.command" -rm -f "$PWD/${PROGRAM}.remote" -rm -f "$PWD/${PROGRAM}.remote.time" -echo "$ULIMITCMD (time -p ($COMMAND > $PWD/$OUTFILE.remote 2>&1 < $INFILE;); echo exit $?) > $PWD/$OUTFILE.remote.time 2>&1" > "$PWD/${PROGRAM}.command" -chmod +x "$PWD/${PROGRAM}.command" - if [ "x$RHOST" = x ] ; then ( sh -c "$ULIMITCMD"; time -p sh -c "$COMMAND >$OUTFILE 2>&1 < $INFILE" ; echo exit $? ) 2>&1 \ | awk -- '\ @@ -119,6 +113,12 @@ !/^user/ && !/^sys/ { print; } END { printf("program %f\n", cpu); }' > $OUTFILE.time else + rm -f "$PWD/${PROGRAM}.command" + rm -f "$PWD/${PROGRAM}.remote" + rm -f "$PWD/${PROGRAM}.remote.time" + echo "$ULIMITCMD cd $PWD; (time -p ($COMMAND > $OUTFILE.remote 2>&1 < $INFILE;); echo exit $?) > $OUTFILE.remote.time 2>&1" > "$PWD/${PROGRAM}.command" + chmod +x "$PWD/${PROGRAM}.command" + ( rsh -l $RUSER $RHOST "ls $PWD/${PROGRAM}.command" ) > /dev/null 2>&1 ( rsh -l $RUSER $RHOST "$PWD/${PROGRAM}.command" ) cat $OUTFILE.remote.time | awk -- '\ From gordonhenriksen at mac.com Tue Mar 4 08:52:05 2008 From: gordonhenriksen at mac.com (Gordon Henriksen) Date: Tue, 04 Mar 2008 14:52:05 -0000 Subject: [llvm-commits] [llvm] r47886 - /llvm/trunk/bindings/ocaml/Makefile.ocaml Message-ID: <200803041452.m24Eq5Ou025079@zion.cs.uiuc.edu> Author: gordon Date: Tue Mar 4 08:52:05 2008 New Revision: 47886 URL: http://llvm.org/viewvc/llvm-project?rev=47886&view=rev Log: Fix a typo noticed by Erick Tryzelaar, Modified: llvm/trunk/bindings/ocaml/Makefile.ocaml Modified: llvm/trunk/bindings/ocaml/Makefile.ocaml URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/bindings/ocaml/Makefile.ocaml?rev=47886&r1=47885&r2=47886&view=diff ============================================================================== --- llvm/trunk/bindings/ocaml/Makefile.ocaml (original) +++ llvm/trunk/bindings/ocaml/Makefile.ocaml Tue Mar 4 08:52:05 2008 @@ -98,7 +98,7 @@ $(ObjDir)/$(LIBRARYNAME).ocamldep: $(OcamlSources) $(OcamlHeaders) \ $(OcamlDir)/.dir $(ObjDir)/.dir - $(Verb) $(OCAMLDEP) $(OCAMLCFLAGS) $(OcamlSources) $(OcamlHeader) > $@ + $(Verb) $(OCAMLDEP) $(OCAMLCFLAGS) $(OcamlSources) $(OcamlHeaders) > $@ $(ObjectsCMI): $(UsedOcamlInterfaces:%=$(OcamlDir)/%.cmi) From alenhar2 at cs.uiuc.edu Tue Mar 4 09:23:05 2008 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Tue, 04 Mar 2008 15:23:05 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r47887 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Message-ID: <200803041523.m24FN5K1026265@zion.cs.uiuc.edu> Author: alenhar2 Date: Tue Mar 4 09:23:05 2008 New Revision: 47887 URL: http://llvm.org/viewvc/llvm-project?rev=47887&view=rev Log: Use type of first arg rather than return type for picking intrinsic. fixes PR2119 Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=47887&r1=47886&r2=47887&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Tue Mar 4 09:23:05 2008 @@ -4306,13 +4306,13 @@ case BUILT_IN_BOOL_COMPARE_AND_SWAP_4: case BUILT_IN_BOOL_COMPARE_AND_SWAP_8: case BUILT_IN_BOOL_COMPARE_AND_SWAP_16: { - const Type *Ty = ConvertType(TREE_TYPE(exp)); tree arglist = TREE_OPERAND(exp, 1); Value* C[3] = { Emit(TREE_VALUE(arglist), 0), Emit(TREE_VALUE(TREE_CHAIN(arglist)), 0), Emit(TREE_VALUE(TREE_CHAIN(TREE_CHAIN(arglist))), 0) }; + const Type *Ty = cast(C[0]->getType())->getElementType(); if (C[1]->getType() != Ty) C[1] = Builder.CreateIntCast(C[1], Ty, "cast"); if (C[2]->getType() != Ty) From evan.cheng at apple.com Tue Mar 4 11:30:49 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 4 Mar 2008 09:30:49 -0800 Subject: [llvm-commits] Fwd: Patch for review: Speeding up ScheduleDAG computations In-Reply-To: References: <522BCA72-6445-4857-BE7B-019B841AA9DB@apple.com> Message-ID: <2DFEE2ED-2D57-4310-8F6C-1B08F18D4363@apple.com> On Mar 4, 2008, at 3:44 AM, Roman Levenstein wrote: > Hi, > > 2008/3/3, Dan Gohman : >> >> On Mar 3, 2008, at 1:31 PM, Chris Lattner wrote: >> >>> On Mar 3, 2008, at 1:26 PM, Evan Cheng wrote: >>>> Thanks. >>>> >>>> Using std::set<> makes me queasy. :-) Too bad it doesn't seem >>>> possible to use SmallPtrSet (elements are not in sorted order). >>> >>> I'm sad to say that std::set is probably the best thing we have >>> right >>> now that provides priority queue + removal from the middle support. >>> >> >> There's make_heap/push_heap/etc. in that let a >> plain std::vector (or a SmallVector I guess) be used as a heap. > > Yes, this is possible but produces much more overhead than std::set on > my tests. BTW, this approach is used in DAGISel.inc files generated by > tablegen. I tried to changed it to std::set as well and ,again, it > works much (25%-30%) faster on BBs with few hundreds or thousends > instructions. If you give me a patch, I'll test it on my end. Thanks. > > > I'd like to understand better why Evan and Chris are some much against > std::set? From some mails I got the impression that std::set > implementation is very inefficient on Darwin or PowerPC? Is it > correct? Or do you dislike that fact that std::set uses dynamic memory > allocation extensively? Right, it's very malloc intensive. That's the main issue. > > >>> Does anyone know of a better data structure to implement these >>> operations? Even if you don't volunteer to implement it, we can add >>> it to the open projects page. > > In principle, we need something like a balanced tree. And since we > want to be able to remove from the middle, I'd say that it should not > be mapped to something linear like std::vector, as it is done by > make_heap, since it involves quite some overhead and a lot of copying > around. Finding/creating a tree implementation is not such a big deal. > But again, why it would be better than std::set, that anyway seems to > be implemented internally as a read-black tree? Hard to say without testing. It might work better for small / medium sized programs if it were designed to avoid malloc for smallish queues. > > > To conclude: Guys, I'm still waiting for a review and approval of the > two pending patches for ScheduleDAGList and ScheduleDAGRRList. Both of > them use std::set approach among other things. I thought those were approved? We understanding std::set is probably the best choice of ADT for now. Thanks! Evan > > > - Roman > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From dpatel at apple.com Tue Mar 4 11:44:38 2008 From: dpatel at apple.com (Devang Patel) Date: Tue, 04 Mar 2008 17:44:38 -0000 Subject: [llvm-commits] [llvm] r47888 - /llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp Message-ID: <200803041744.m24Hic6T030716@zion.cs.uiuc.edu> Author: dpatel Date: Tue Mar 4 11:44:37 2008 New Revision: 47888 URL: http://llvm.org/viewvc/llvm-project?rev=47888&view=rev Log: Collect statistics. Modified: llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp Modified: llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp?rev=47888&r1=47887&r2=47888&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp Tue Mar 4 11:44:37 2008 @@ -24,9 +24,12 @@ #include "llvm/Support/Debug.h" #include "llvm/ADT/Statistic.h" #include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/Statistic.h" #include "llvm/Support/Compiler.h" using namespace llvm; +STATISTIC(NumRejectedSRETUses , "Number of sret rejected due to unexpected uses"); +STATISTIC(NumSRET , "Number of sret promoted"); namespace { /// SRETPromotion - This pass removes sret parameter and updates /// function to use multiple return value. @@ -87,15 +90,18 @@ assert (STy && "Invalid sret parameter element type"); // Check if it is ok to perform this promotion. - if (isSafeToUpdateAllCallers(F) == false) + if (isSafeToUpdateAllCallers(F) == false) { + NumRejectedSRETUses++; return false; + } // [1] Replace use of sret parameter - AllocaInst *TheAlloca = new AllocaInst (STy, NULL, "mrv", F->getEntryBlock().begin()); + AllocaInst *TheAlloca = new AllocaInst (STy, NULL, "mrv", + F->getEntryBlock().begin()); Value *NFirstArg = F->arg_begin(); NFirstArg->replaceAllUsesWith(TheAlloca); - // Find and replace ret instructions + // [2] Find and replace ret instructions SmallVector RetVals; for (Function::iterator FI = F->begin(), FE = F->end(); FI != FE; ++FI) for(BasicBlock::iterator BI = FI->begin(), BE = FI->end(); BI != BE; ) { @@ -119,10 +125,10 @@ } } - // Create the new function body and insert it into the module. + // [3] Create the new function body and insert it into the module. Function *NF = cloneFunctionBody(F, STy); - // Update all call sites to use new function + // [4] Update all call sites to use new function updateCallSites(F, NF); F->eraseFromParent(); From dpatel at apple.com Tue Mar 4 11:46:26 2008 From: dpatel at apple.com (Devang Patel) Date: Tue, 04 Mar 2008 17:46:26 -0000 Subject: [llvm-commits] [llvm] r47889 - /llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp Message-ID: <200803041746.m24HkQsT030782@zion.cs.uiuc.edu> Author: dpatel Date: Tue Mar 4 11:46:26 2008 New Revision: 47889 URL: http://llvm.org/viewvc/llvm-project?rev=47889&view=rev Log: Process externally visible functions also. Later on code generator will do the right thing. Modified: llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp Modified: llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp?rev=47889&r1=47888&r2=47889&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp Tue Mar 4 11:46:26 2008 @@ -73,8 +73,7 @@ bool SRETPromotion::PromoteReturn(CallGraphNode *CGN) { Function *F = CGN->getFunction(); - // Make sure that it is local to this module. - if (!F || !F->hasInternalLinkage()) + if (!F) return false; // Make sure that function returns struct. From dpatel at apple.com Tue Mar 4 11:47:06 2008 From: dpatel at apple.com (Devang Patel) Date: Tue, 04 Mar 2008 17:47:06 -0000 Subject: [llvm-commits] [llvm] r47890 - /llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp Message-ID: <200803041747.m24Hl6jE030812@zion.cs.uiuc.edu> Author: dpatel Date: Tue Mar 4 11:47:06 2008 New Revision: 47890 URL: http://llvm.org/viewvc/llvm-project?rev=47890&view=rev Log: Skip declarations. Modified: llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp Modified: llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp?rev=47890&r1=47889&r2=47890&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp Tue Mar 4 11:47:06 2008 @@ -73,7 +73,7 @@ bool SRETPromotion::PromoteReturn(CallGraphNode *CGN) { Function *F = CGN->getFunction(); - if (!F) + if (!F || F->isDeclaration()) return false; // Make sure that function returns struct. From dpatel at apple.com Tue Mar 4 11:48:12 2008 From: dpatel at apple.com (Devang Patel) Date: Tue, 04 Mar 2008 17:48:12 -0000 Subject: [llvm-commits] [llvm] r47892 - /llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp Message-ID: <200803041748.m24HmCWw030867@zion.cs.uiuc.edu> Author: dpatel Date: Tue Mar 4 11:48:11 2008 New Revision: 47892 URL: http://llvm.org/viewvc/llvm-project?rev=47892&view=rev Log: Increment counter that keeps track of total number of sret promoted. Modified: llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp Modified: llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp?rev=47892&r1=47891&r2=47892&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp Tue Mar 4 11:48:11 2008 @@ -94,6 +94,7 @@ return false; } + NumSRET++; // [1] Replace use of sret parameter AllocaInst *TheAlloca = new AllocaInst (STy, NULL, "mrv", F->getEntryBlock().begin()); From dalej at apple.com Tue Mar 4 12:12:07 2008 From: dalej at apple.com (Dale Johannesen) Date: Tue, 4 Mar 2008 10:12:07 -0800 Subject: [llvm-commits] [llvm] r47883 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp In-Reply-To: <200803040805.m2485Uhk000936@zion.cs.uiuc.edu> References: <200803040805.m2485Uhk000936@zion.cs.uiuc.edu> Message-ID: <3C49DA82-8B85-47C0-B4D4-3216ADFF4E9C@apple.com> Btw, this optimization is sometimes a loser on speed, we should have a way to disable it. I ran into this in gcc a while back: http://gcc.gnu.org/ml/gcc/2005-07/msg00289.html On Mar 4, 2008, at 12:05 AM, Evan Cheng wrote: > Author: evancheng > Date: Tue Mar 4 02:05:30 2008 > New Revision: 47883 > > URL: http://llvm.org/viewvc/llvm-project?rev=47883&view=rev > Log: > Refactor ExpandConstantFP so it can optimize load from constpool of > types larger than f64 into extload from smaller types. From romix.llvm at googlemail.com Tue Mar 4 12:37:34 2008 From: romix.llvm at googlemail.com (Roman Levenstein) Date: Tue, 4 Mar 2008 21:37:34 +0300 Subject: [llvm-commits] Fwd: Patch for review: Speeding up ScheduleDAG computations In-Reply-To: <2DFEE2ED-2D57-4310-8F6C-1B08F18D4363@apple.com> References: <522BCA72-6445-4857-BE7B-019B841AA9DB@apple.com> <2DFEE2ED-2D57-4310-8F6C-1B08F18D4363@apple.com> Message-ID: Hi Evan, 2008/3/4, Evan Cheng : > > On Mar 4, 2008, at 3:44 AM, Roman Levenstein wrote: > > > Hi, > > > > 2008/3/3, Dan Gohman : > >> > >> On Mar 3, 2008, at 1:31 PM, Chris Lattner wrote: > >> > >>> On Mar 3, 2008, at 1:26 PM, Evan Cheng wrote: > >>>> Thanks. > >>>> > >>>> Using std::set<> makes me queasy. :-) Too bad it doesn't seem > >>>> possible to use SmallPtrSet (elements are not in sorted order). > >>> > >>> I'm sad to say that std::set is probably the best thing we have > >>> right > >>> now that provides priority queue + removal from the middle support. > >>> > >> > >> There's make_heap/push_heap/etc. in that let a > >> plain std::vector (or a SmallVector I guess) be used as a heap. > > > > Yes, this is possible but produces much more overhead than std::set on > > my tests. BTW, this approach is used in DAGISel.inc files generated by > > tablegen. I tried to changed it to std::set as well and ,again, it > > works much (25%-30%) faster on BBs with few hundreds or thousends > > instructions. > > > If you give me a patch, I'll test it on my end. Thanks. Fine. I'll provide this patch tomorrow. It is not a patch for the tablegen yet, it is just a small change of the code selector generated by the tablegen for the X86 target. > > I'd like to understand better why Evan and Chris are some much against > > std::set? From some mails I got the impression that std::set > > implementation is very inefficient on Darwin or PowerPC? Is it > > correct? Or do you dislike that fact that std::set uses dynamic memory > > allocation extensively? > > > Right, it's very malloc intensive. That's the main issue. I think we may have a reasonable solution here. Remember that STL allows us to provide our own allocators as a template parameter for all collection classes including std::set. So, in principle we can use a cutom pool allocator or something like that to make std::set less memory intensive. BTW, here you can find a nice description about writing your own stl compatible allocator: http://www.codeguru.com/Cpp/Cpp/cpp_mfc/stl/article.php/c4079 > > > > > >>> Does anyone know of a better data structure to implement these > >>> operations? Even if you don't volunteer to implement it, we can add > >>> it to the open projects page. > > > > In principle, we need something like a balanced tree. And since we > > want to be able to remove from the middle, I'd say that it should not > > be mapped to something linear like std::vector, as it is done by > > make_heap, since it involves quite some overhead and a lot of copying > > around. Finding/creating a tree implementation is not such a big deal. > > But again, why it would be better than std::set, that anyway seems to > > be implemented internally as a read-black tree? > > > Hard to say without testing. It might work better for small / medium > sized programs if it were designed to avoid malloc for smallish queues. See above. Custom allocator may solve our problems. > > To conclude: Guys, I'm still waiting for a review and approval of the > > two pending patches for ScheduleDAGList and ScheduleDAGRRList. Both of > > them use std::set approach among other things. > > > I thought those were approved? We understanding std::set is probably > the best choice of ADT for now. Thanks! OK. I'll commit them tomorrow. But are you sure about the second one for the ScheduleDAGRRList? I mean this: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20080303/059078.html It also intorduces strict ordering for sorting functions and some other changes besides std::set. Would be nice to get a confirmation from others that it does not break any existing test-cases and compiled programms still produce correct results. - Roman From evan.cheng at apple.com Tue Mar 4 12:43:15 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 4 Mar 2008 10:43:15 -0800 Subject: [llvm-commits] [llvm] r47883 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp In-Reply-To: <3C49DA82-8B85-47C0-B4D4-3216ADFF4E9C@apple.com> References: <200803040805.m2485Uhk000936@zion.cs.uiuc.edu> <3C49DA82-8B85-47C0-B4D4-3216ADFF4E9C@apple.com> Message-ID: <13971D77-DA1A-4D2C-BB10-705ACF2F3D08@apple.com> Yep, that's the plan. See rdar://5755966 Evan On Mar 4, 2008, at 10:12 AM, Dale Johannesen wrote: > Btw, this optimization is sometimes a loser on speed, we should have a > way to disable it. > I ran into this in gcc a while back: > http://gcc.gnu.org/ml/gcc/2005-07/msg00289.html > > On Mar 4, 2008, at 12:05 AM, Evan Cheng wrote: > >> Author: evancheng >> Date: Tue Mar 4 02:05:30 2008 >> New Revision: 47883 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=47883&view=rev >> Log: >> Refactor ExpandConstantFP so it can optimize load from constpool of >> types larger than f64 into extload from smaller types. > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From evan.cheng at apple.com Tue Mar 4 12:44:45 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 4 Mar 2008 10:44:45 -0800 Subject: [llvm-commits] Patch for review: Speeding up ScheduleDAG computations In-Reply-To: References: <200803031053.00270.dag@cray.com> Message-ID: Are you sure llvm-gcc is in your path? Check Makefile.config make sure LLVMGCC etc. are pointing to the right executables. If not, make sure llvm-gcc is in the path and reconfigure the tree. Evan On Mar 4, 2008, at 3:56 AM, Roman Levenstein wrote: > Hi, > > 2008/3/3, Tanya Lattner : >> Please review and test, if possible. I have problems with running the >> llvm-test test-suite. When I to run it (and keep in mind, I never did >> it before), I always get the following error messages on my X86/ >> Ubuntu >> system: >> make[4]: *** No rule to make target >> `Output/sse.expandfft.linked.rbc', needed >> by >> `Output/sse.expandfft.linked.bc'. >> Stop. >> >> Please keep in mind that all proposed patches should have been >> tested before >> submitting. This includes llvm-test and 'make check'. >> http://llvm.org/docs/DeveloperPolicy.html#quality > > Sure! > >> This will make Evan's job easier ;) >> >> As for the error in llvm-test that you are seeing, can you use 'make >> VERBOSE=1 TEST=nightly report' and post more details on what make is >> running? It looks like an error in configuration. Did you >> reconfigure once >> you set llvm-gcc path? > > Thanks for the advice, Tanya. > > OK. Here is what I did: > > First I reconfigured: > ../../../llvm/projects/llvm-test/configure --with-llvmgccdir=/opt/ > llvm-gcc > > Than I execute 'make VERBOSE=1 TEST=nightly report' and get the > following: > > make[1]: Entering directory `/opt/llvm.build/projects/llvm-test' > if [ ! -f SingleSource/Makefile ]; \ > then \ > /opt/llvm/autoconf/mkinstalldirs SingleSource; \ > cp /opt/llvm/projects/llvm-test/SingleSource/Makefile > SingleSource/Makefile; \ > fi; \ > make -C SingleSource test -w > make[2]: Entering directory `/opt/llvm.build/projects/llvm-test/ > SingleSource' > if [ ! -f UnitTests/Makefile ]; \ > then \ > /opt/llvm/autoconf/mkinstalldirs UnitTests; \ > cp > /opt/llvm/projects/llvm-test/SingleSource/UnitTests/Makefile > UnitTests/Makefile; \ > fi; \ > make -C UnitTests test -w > make[3]: Entering directory > `/opt/llvm.build/projects/llvm-test/SingleSource/UnitTests' > for dir in Vector SignlessTypes Threads; do \ > if [ ! -f $dir/Makefile ]; \ > then \ > /opt/llvm/autoconf/mkinstalldirs $dir; \ > cp > /opt/llvm/projects/llvm-test/SingleSource/UnitTests/$dir/Makefile > $dir/Makefile; \ > fi; \ > (make -C $dir test -w) || exit 1; \ > done > make[4]: Entering directory > `/opt/llvm.build/projects/llvm-test/SingleSource/UnitTests/Vector' > for dir in SSE; do \ > if [ ! -f $dir/Makefile ]; \ > then \ > /opt/llvm/autoconf/mkinstalldirs $dir; \ > cp > /opt/llvm/projects/llvm-test/SingleSource/UnitTests/Vector/$dir/ > Makefile > $dir/Makefile; \ > fi; \ > (make -C $dir test -w) || exit 1; \ > done > make[5]: Entering directory > `/opt/llvm.build/projects/llvm-test/SingleSource/UnitTests/Vector/SSE' > make[5]: *** No rule to make target `Output/sse.expandfft.linked.rbc', > needed by `Output/sse.expandfft.linked.bc'. Stop. > make[5]: Leaving directory > `/opt/llvm.build/projects/llvm-test/SingleSource/UnitTests/Vector/SSE' > make[4]: *** [test] Error 1 > make[4]: Leaving directory > `/opt/llvm.build/projects/llvm-test/SingleSource/UnitTests/Vector' > make[3]: *** [test] Error 1 > make[3]: Leaving directory > `/opt/llvm.build/projects/llvm-test/SingleSource/UnitTests' > make[2]: *** [UnitTests/.maketest] Error 2 > make[2]: Leaving directory `/opt/llvm.build/projects/llvm-test/ > SingleSource' > make[1]: *** [SingleSource/.maketest] Error 2 > make[1]: Leaving directory `/opt/llvm.build/projects/llvm-test' > > Any ideas about what I'm doing wrong? > > Thanks, > Roman > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From clattner at apple.com Tue Mar 4 12:44:45 2008 From: clattner at apple.com (Chris Lattner) Date: Tue, 4 Mar 2008 10:44:45 -0800 Subject: [llvm-commits] [llvm] r47883 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp In-Reply-To: <13971D77-DA1A-4D2C-BB10-705ACF2F3D08@apple.com> References: <200803040805.m2485Uhk000936@zion.cs.uiuc.edu> <3C49DA82-8B85-47C0-B4D4-3216ADFF4E9C@apple.com> <13971D77-DA1A-4D2C-BB10-705ACF2F3D08@apple.com> Message-ID: <01F71675-0350-4C20-904A-49A43D80C801@apple.com> On Mar 4, 2008, at 10:43 AM, Evan Cheng wrote: > Yep, that's the plan. See rdar://5755966 aka PR1264. -Chris > > > Evan > On Mar 4, 2008, at 10:12 AM, Dale Johannesen wrote: > >> Btw, this optimization is sometimes a loser on speed, we should >> have a >> way to disable it. >> I ran into this in gcc a while back: >> http://gcc.gnu.org/ml/gcc/2005-07/msg00289.html >> >> On Mar 4, 2008, at 12:05 AM, Evan Cheng wrote: >> >>> Author: evancheng >>> Date: Tue Mar 4 02:05:30 2008 >>> New Revision: 47883 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=47883&view=rev >>> Log: >>> Refactor ExpandConstantFP so it can optimize load from constpool of >>> types larger than f64 into extload from smaller types. >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From dpatel at apple.com Tue Mar 4 12:57:06 2008 From: dpatel at apple.com (Devang Patel) Date: Tue, 04 Mar 2008 18:57:06 -0000 Subject: [llvm-commits] [llvm] r47895 - in /llvm/trunk: include/llvm/DerivedTypes.h lib/VMCore/Type.cpp Message-ID: <200803041857.m24Iv6Ck000553@zion.cs.uiuc.edu> Author: dpatel Date: Tue Mar 4 12:57:05 2008 New Revision: 47895 URL: http://llvm.org/viewvc/llvm-project?rev=47895&view=rev Log: Add FunctionType ctor variant that takes SmallVector params. Modified: llvm/trunk/include/llvm/DerivedTypes.h llvm/trunk/lib/VMCore/Type.cpp Modified: llvm/trunk/include/llvm/DerivedTypes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/DerivedTypes.h?rev=47895&r1=47894&r2=47895&view=diff ============================================================================== --- llvm/trunk/include/llvm/DerivedTypes.h (original) +++ llvm/trunk/include/llvm/DerivedTypes.h Tue Mar 4 12:57:05 2008 @@ -19,6 +19,7 @@ #define LLVM_DERIVED_TYPES_H #include "llvm/Type.h" +#include "llvm/ADT/SmallVector.h" namespace llvm { @@ -144,6 +145,8 @@ const FunctionType &operator=(const FunctionType &); // Do not implement FunctionType(const Type *Result, const std::vector &Params, bool IsVarArgs); + FunctionType(const Type *Result, const SmallVectorImpl &Params, + bool IsVarArgs); public: /// FunctionType::get - This static method is the primary way of constructing @@ -155,6 +158,12 @@ bool isVarArg ///< Whether this is a variable argument length function ); + static FunctionType *get( + const Type *Result, ///< The result type + const SmallVectorImpl &Params, ///< The types of the parameters + bool isVarArg ///< Whether this is a variable argument length function + ); + inline bool isVarArg() const { return isVarArgs; } inline const Type *getReturnType() const { return ContainedTys[0]; } Modified: llvm/trunk/lib/VMCore/Type.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Type.cpp?rev=47895&r1=47894&r2=47895&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Type.cpp (original) +++ llvm/trunk/lib/VMCore/Type.cpp Tue Mar 4 12:57:05 2008 @@ -460,6 +460,30 @@ setAbstract(isAbstract); } +FunctionType::FunctionType(const Type *Result, + const SmallVectorImpl &Params, + bool IsVarArgs) + : DerivedType(FunctionTyID), isVarArgs(IsVarArgs) { + ContainedTys = reinterpret_cast(this+1); + NumContainedTys = Params.size() + 1; // + 1 for result type + assert((Result->isFirstClassType() || Result == Type::VoidTy || + Result->getTypeID() == Type::StructTyID || + isa(Result)) && + "LLVM functions cannot return aggregates"); + bool isAbstract = Result->isAbstract(); + new (&ContainedTys[0]) PATypeHandle(Result, this); + + for (unsigned i = 0; i != Params.size(); ++i) { + assert((Params[i]->isFirstClassType() || isa(Params[i])) && + "Function arguments must be value types!"); + new (&ContainedTys[i+1]) PATypeHandle(Params[i],this); + isAbstract |= Params[i]->isAbstract(); + } + + // Calculate whether or not this type is abstract + setAbstract(isAbstract); +} + StructType::StructType(const std::vector &Types, bool isPacked) : CompositeType(StructTyID) { ContainedTys = reinterpret_cast(this + 1); @@ -1055,6 +1079,12 @@ ArgTypes.push_back(args[i]); } + FunctionValType(const Type *ret, const SmallVectorImpl &args, + bool isVA) : RetTy(ret), isVarArg(isVA) { + for (unsigned i = 0; i < args.size(); ++i) + ArgTypes.push_back(args[i]); + } + static FunctionValType get(const FunctionType *FT); static unsigned hashTypeStructure(const FunctionType *FT) { @@ -1108,6 +1138,27 @@ return FT; } +// FunctionType::get - The factory function for the FunctionType class... +FunctionType *FunctionType::get(const Type *ReturnType, + const SmallVectorImpl &Params, + bool isVarArg) { + FunctionValType VT(ReturnType, Params, isVarArg); + FunctionType *FT = FunctionTypes->get(VT); + if (FT) { + return FT; + } + + FT = (FunctionType*) new char[sizeof(FunctionType) + + sizeof(PATypeHandle)*(Params.size()+1)]; + new (FT) FunctionType(ReturnType, Params, isVarArg); + FunctionTypes->add(VT, FT); + +#ifdef DEBUG_MERGE_TYPES + DOUT << "Derived new type: " << FT << "\n"; +#endif + return FT; +} + //===----------------------------------------------------------------------===// // Array Type Factory... // From evan.cheng at apple.com Tue Mar 4 13:11:37 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 4 Mar 2008 11:11:37 -0800 Subject: [llvm-commits] Fwd: Patch for review: Speeding up ScheduleDAG computations In-Reply-To: References: <522BCA72-6445-4857-BE7B-019B841AA9DB@apple.com> <2DFEE2ED-2D57-4310-8F6C-1B08F18D4363@apple.com> Message-ID: <3F12013F-046B-4DF7-AFEE-6784E19CEE7D@apple.com> On Mar 4, 2008, at 10:37 AM, Roman Levenstein wrote: > Hi Evan, > > 2008/3/4, Evan Cheng : >> >> On Mar 4, 2008, at 3:44 AM, Roman Levenstein wrote: >> >>> Hi, >>> >>> 2008/3/3, Dan Gohman : >>>> >>>> On Mar 3, 2008, at 1:31 PM, Chris Lattner wrote: >>>> >>>>> On Mar 3, 2008, at 1:26 PM, Evan Cheng wrote: >>>>>> Thanks. >>>>>> >>>>>> Using std::set<> makes me queasy. :-) Too bad it doesn't seem >>>>>> possible to use SmallPtrSet (elements are not in sorted order). >>>>> >>>>> I'm sad to say that std::set is probably the best thing we have >>>>> right >>>>> now that provides priority queue + removal from the middle >>>>> support. >>>>> >>>> >>>> There's make_heap/push_heap/etc. in that let a >>>> plain std::vector (or a SmallVector I guess) be used as a heap. >>> >>> Yes, this is possible but produces much more overhead than >>> std::set on >>> my tests. BTW, this approach is used in DAGISel.inc files >>> generated by >>> tablegen. I tried to changed it to std::set as well and ,again, it >>> works much (25%-30%) faster on BBs with few hundreds or thousends >>> instructions. >> >> >> If you give me a patch, I'll test it on my end. Thanks. > > Fine. I'll provide this patch tomorrow. It is not a patch for the > tablegen yet, it is just a small change of the code selector generated > by the tablegen for the X86 target. Ok, thanks. > > >>> I'd like to understand better why Evan and Chris are some much >>> against >>> std::set? From some mails I got the impression that std::set >>> implementation is very inefficient on Darwin or PowerPC? Is it >>> correct? Or do you dislike that fact that std::set uses dynamic >>> memory >>> allocation extensively? >> >> >> Right, it's very malloc intensive. That's the main issue. > > I think we may have a reasonable solution here. Remember that STL > allows us to provide our own allocators as a template parameter for > all collection classes including std::set. So, in principle we can use > a cutom pool allocator or something like that to make std::set less > memory intensive. > > BTW, here you can find a nice description about writing your own stl > compatible allocator: > http://www.codeguru.com/Cpp/Cpp/cpp_mfc/stl/article.php/c4079 Ok. > > >>> >>> >>>>> Does anyone know of a better data structure to implement these >>>>> operations? Even if you don't volunteer to implement it, we can >>>>> add >>>>> it to the open projects page. >>> >>> In principle, we need something like a balanced tree. And since we >>> want to be able to remove from the middle, I'd say that it should >>> not >>> be mapped to something linear like std::vector, as it is done by >>> make_heap, since it involves quite some overhead and a lot of >>> copying >>> around. Finding/creating a tree implementation is not such a big >>> deal. >>> But again, why it would be better than std::set, that anyway seems >>> to >>> be implemented internally as a read-black tree? >> >> >> Hard to say without testing. It might work better for small / medium >> sized programs if it were designed to avoid malloc for smallish >> queues. > > See above. Custom allocator may solve our problems. > >>> To conclude: Guys, I'm still waiting for a review and approval of >>> the >>> two pending patches for ScheduleDAGList and ScheduleDAGRRList. >>> Both of >>> them use std::set approach among other things. >> >> >> I thought those were approved? We understanding std::set is probably >> the best choice of ADT for now. Thanks! > > OK. I'll commit them tomorrow. > > But are you sure about the second one for the ScheduleDAGRRList? > I mean this: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20080303/059078.html > > It also intorduces strict ordering for sorting functions and some > other changes besides std::set. Would be nice to get a confirmation > from others that it does not break any existing test-cases and > compiled programms still produce correct results. I'll take a look. Evan > > > - Roman > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From dpatel at apple.com Tue Mar 4 13:12:58 2008 From: dpatel at apple.com (Devang Patel) Date: Tue, 04 Mar 2008 19:12:58 -0000 Subject: [llvm-commits] [llvm] r47896 - /llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp Message-ID: <200803041912.m24JCwEK001100@zion.cs.uiuc.edu> Author: dpatel Date: Tue Mar 4 13:12:58 2008 New Revision: 47896 URL: http://llvm.org/viewvc/llvm-project?rev=47896&view=rev Log: Skip sret attribute while preparing attribute list for new function and new call sites. Modified: llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp Modified: llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp?rev=47896&r1=47895&r2=47896&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp Tue Mar 4 13:12:58 2008 @@ -205,9 +205,14 @@ unsigned ParamIndex = 1; // 0th parameter attribute is reserved for return type. while (I != E) { Params.push_back(I->getType()); - if (ParameterAttributes attrs = PAL ? PAL->getParamAttrs(ParamIndex) : - ParamAttr::None) - ParamAttrsVec.push_back(ParamAttrsWithIndex::get(Params.size(), attrs)); + ParameterAttributes Attrs; + if (PAL) { + Attrs = PAL->getParamAttrs(ParamIndex); + if (ParamIndex == 1) // Skip sret attribute + Attrs = Attrs ^ ParamAttr::StructRet; + } + if (Attrs != ParamAttr::None) + ParamAttrsVec.push_back(ParamAttrsWithIndex::get(ParamIndex, Attrs)); ++I; ++ParamIndex; } @@ -240,7 +245,7 @@ SmallVector Args; // ParamAttrs - Keep track of the parameter attributes for the arguments. - ParamAttrsVector ParamAttrsVec; + ParamAttrsVector ArgAttrsVec; for (Value::use_iterator FUI = F->use_begin(), FUE = F->use_end(); FUI != FUE;) { CallSite CS = CallSite::get(*FUI); @@ -250,7 +255,7 @@ const ParamAttrsList *PAL = F->getParamAttrs(); // Add any return attributes. if (ParameterAttributes attrs = PAL ? PAL->getParamAttrs(0) : ParamAttr::None) - ParamAttrsVec.push_back(ParamAttrsWithIndex::get(0, attrs)); + ArgAttrsVec.push_back(ParamAttrsWithIndex::get(0, attrs)); // Copy arguments, however skip first one. CallSite::arg_iterator AI = CS.arg_begin(), AE = CS.arg_end(); @@ -259,9 +264,14 @@ unsigned ParamIndex = 1; // 0th parameter attribute is reserved for return type. while (AI != AE) { Args.push_back(*AI); - if (ParameterAttributes Attrs = PAL ? PAL->getParamAttrs(ParamIndex) : - ParamAttr::None) - ParamAttrsVec.push_back(ParamAttrsWithIndex::get(Args.size(), Attrs)); + ParameterAttributes Attrs; + if (PAL) { + Attrs = PAL->getParamAttrs(ParamIndex); + if (ParamIndex == 1) // Skip sret attribute + Attrs = Attrs ^ ParamAttr::StructRet; + } + if (Attrs != ParamAttr::None) + ArgAttrsVec.push_back(ParamAttrsWithIndex::get(Args.size(), Attrs)); ++ParamIndex; ++AI; } @@ -272,16 +282,16 @@ New = new InvokeInst(NF, II->getNormalDest(), II->getUnwindDest(), Args.begin(), Args.end(), "", Call); cast(New)->setCallingConv(CS.getCallingConv()); - cast(New)->setParamAttrs(ParamAttrsList::get(ParamAttrsVec)); + cast(New)->setParamAttrs(ParamAttrsList::get(ArgAttrsVec)); } else { New = new CallInst(NF, Args.begin(), Args.end(), "", Call); cast(New)->setCallingConv(CS.getCallingConv()); - cast(New)->setParamAttrs(ParamAttrsList::get(ParamAttrsVec)); + cast(New)->setParamAttrs(ParamAttrsList::get(ArgAttrsVec)); if (cast(Call)->isTailCall()) cast(New)->setTailCall(); } Args.clear(); - ParamAttrsVec.clear(); + ArgAttrsVec.clear(); New->takeName(Call); // Update all users of sret parameter to extract value using getresult. From dpatel at apple.com Tue Mar 4 13:22:54 2008 From: dpatel at apple.com (Devang Patel) Date: Tue, 04 Mar 2008 19:22:54 -0000 Subject: [llvm-commits] [llvm] r47897 - /llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp Message-ID: <200803041922.m24JMstA001381@zion.cs.uiuc.edu> Author: dpatel Date: Tue Mar 4 13:22:54 2008 New Revision: 47897 URL: http://llvm.org/viewvc/llvm-project?rev=47897&view=rev Log: Use appropriate index to get the result value. Modified: llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp Modified: llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp?rev=47897&r1=47896&r2=47897&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp Tue Mar 4 13:22:54 2008 @@ -302,7 +302,9 @@ if (C2 && (C2 == Call)) continue; else if (GetElementPtrInst *UGEP = dyn_cast(U2)) { - Value *GR = new GetResultInst(New, 5, "xxx", UGEP); + ConstantInt *Idx = dyn_cast(UGEP->getOperand(2)); + assert (Idx && "Unexpected getelementptr index!"); + Value *GR = new GetResultInst(New, Idx->getZExtValue(), "gr", UGEP); for (Value::use_iterator GI = UGEP->use_begin(), GE = UGEP->use_end(); GI != GE; ++GI) { if (LoadInst *L = dyn_cast(*GI)) { From clattner at apple.com Tue Mar 4 13:30:21 2008 From: clattner at apple.com (Chris Lattner) Date: Tue, 4 Mar 2008 11:30:21 -0800 Subject: [llvm-commits] [llvm] r47895 - in /llvm/trunk: include/llvm/DerivedTypes.h lib/VMCore/Type.cpp In-Reply-To: <200803041857.m24Iv6Ck000553@zion.cs.uiuc.edu> References: <200803041857.m24Iv6Ck000553@zion.cs.uiuc.edu> Message-ID: On Mar 4, 2008, at 10:57 AM, Devang Patel wrote: > Author: dpatel > Date: Tue Mar 4 12:57:05 2008 > New Revision: 47895 > > URL: http://llvm.org/viewvc/llvm-project?rev=47895&view=rev > Log: > Add FunctionType ctor variant that takes SmallVector params. > > > #include "llvm/Type.h" > +#include "llvm/ADT/SmallVector.h" Instead of making this specific to smallvector, how about passing in pointer to pointer + count instead? That eliminates the #include and allows it to work with arrays on the stack and scalars. -Chris From clattner at apple.com Tue Mar 4 13:34:43 2008 From: clattner at apple.com (Chris Lattner) Date: Tue, 4 Mar 2008 11:34:43 -0800 Subject: [llvm-commits] Fwd: Patch for review: Speeding up ScheduleDAG computations In-Reply-To: References: <522BCA72-6445-4857-BE7B-019B841AA9DB@apple.com> <2DFEE2ED-2D57-4310-8F6C-1B08F18D4363@apple.com> Message-ID: <42F118AB-1A01-41F8-9DD8-7A3D16F47683@apple.com> >>> I'd like to understand better why Evan and Chris are some much >>> against >>> std::set? From some mails I got the impression that std::set >>> implementation is very inefficient on Darwin or PowerPC? Is it >>> correct? Or do you dislike that fact that std::set uses dynamic >>> memory >>> allocation extensively? >> >> >> Right, it's very malloc intensive. That's the main issue. There is a reasonable discussion of these issues here: http://llvm.org/docs/ProgrammersManual.html#datastructure > I think we may have a reasonable solution here. Remember that STL > allows us to provide our own allocators as a template parameter for > all collection classes including std::set. So, in principle we can use > a cutom pool allocator or something like that to make std::set less > memory intensive. This isn't really a good solution. Node based data structures are inherently less cache and memory efficient than dense ones (e.g. map vs densemap) regardless of the allocator you use. Making malloc faster improves the situation, but it doesn't solve the underlying problem. If you have per-datastructure heaps, you suffer significant fragmentation problems. -Chris From dpatel at apple.com Tue Mar 4 13:41:41 2008 From: dpatel at apple.com (Devang Patel) Date: Tue, 4 Mar 2008 11:41:41 -0800 Subject: [llvm-commits] [llvm] r47895 - in /llvm/trunk: include/llvm/DerivedTypes.h lib/VMCore/Type.cpp In-Reply-To: References: <200803041857.m24Iv6Ck000553@zion.cs.uiuc.edu> Message-ID: On Mar 4, 2008, at 11:30 AM, Chris Lattner wrote: > > On Mar 4, 2008, at 10:57 AM, Devang Patel wrote: > >> Author: dpatel >> Date: Tue Mar 4 12:57:05 2008 >> New Revision: 47895 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=47895&view=rev >> Log: >> Add FunctionType ctor variant that takes SmallVector params. >> >> >> #include "llvm/Type.h" >> +#include "llvm/ADT/SmallVector.h" > > Instead of making this specific to smallvector, how about passing in > pointer to pointer + count instead? That eliminates the #include and > allows it to work with arrays on the stack and scalars. I will do that conversion also. I did not do it immediately because it required many mechanical changes. - Devang From evan.cheng at apple.com Tue Mar 4 13:54:34 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 4 Mar 2008 11:54:34 -0800 Subject: [llvm-commits] Patch for review: Speeding up ScheduleDAG computations In-Reply-To: References: <200803031053.00270.dag@cray.com> Message-ID: <5B2F037F-C22F-4CDC-AE6E-1D711A11D975@apple.com> Some comments. + + if (!IsRemoved) + // fix the ordering here + AvailableQueue->updateNode(PredSU); Please start comment with a capital letter. :-) - virtual void updateNode(const SUnit *SU) {} + virtual void updateNode(const SUnit *SU) { + remove((SUnit *)SU); + push((SUnit *)SU); + } Rather than casting away the constness. It's probably ok to change the prototype instead. - Queue.push(U); + Queue.insert(U); <=== tab here } void push_all(const std::vector &Nodes) { - for (unsigned i = 0, e = Nodes.size(); i != e; ++i) - Queue.push(Nodes[i]); + for (unsigned i = 0, e = Nodes.size(); i != e; ++i) { + Queue.insert(Nodes[i]); <=== tab here + } No tabs please. - // FIXME: No strict ordering. - return false; + return (left->NodeNum < right->NodeNum); I think this is ok for now. But perhaps we can add a field to SUnit to track the relative temporal order of when nodes are inserted in the queue. This should then be changed to prefer nodes that were entered earlier rather than NodeNum which can be arbitrary. What do you think? This can be a later patch. Thanks, Evan On Mar 3, 2008, at 9:18 AM, Roman Levenstein wrote: > Hi Dave, > > 2008/3/3, David Greene : >> On Friday 29 February 2008 17:49, Evan Cheng wrote: >>> Let's try to solve one problem at a time. >>> >>> 1. Roman's depth / height patch calculation is obviously goodness. >>> Please commit that first. >>> 2. It's probably safe to eliminate the "special tie-breaker" from >>> top >>> down sorting function. >>> 3. We will need to fix up the sorting functions so strict ordering >>> is >>> preserved. We need to do so without breaking any of the existing >>> test >>> case. "return left->NodeNum < right->NodeNum;" doesn't. :-( What >>> does >>> "return false" mean? Is it favoring nodes that are inserted earlier? >>> 4. It might be wise to add some debugging code so we can tell where >>> things start diverge. >>> 5. It would be nice to be able to rebalance the heap. Roman and >>> David >>> can fight it out when we get to that point. :-) >> >> >> Sounds good. I don't know what "fight it out" means, however. :) > Me either ;) > >> It's more than "nice" to rebalance the heap. It's necessary if we >> want to avoid traps when _GLIBCXX_DEBUG is enabled. And we >> want to do that because it finds lots of bugs. > Totally agree. > > Here is a proposed patch for ScheduleDAGRRList.cpp. It contains the > following changes: > 1) Uses std::set instead of the priority queue. This makes removal of > nodes very fast and removes a bottleneck > 2) sorting functions use now strict ordering > 3) According to your proposal, it takes node priority updates into > account and updates the priority queue by removing and re-inserting > the updated element. > 4) SumOfUnscheduledPredsOfSuccs is slightly changed to avoid useless > computations. This saves a LOT OF time on big basic blocks. > > Please review and test, if possible. I have problems with running the > llvm-test test-suite. When I to run it (and keep in mind, I never did > it before), I always get the following error messages on my X86/Ubuntu > system: > make[4]: *** No rule to make target > `Output/sse.expandfft.linked.rbc', needed by > `Output/sse.expandfft.linked.bc'. Stop. > > > -Roman > < > ScheduleDAGRRList > .patch>_______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From asl at math.spbu.ru Tue Mar 4 14:15:35 2008 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Tue, 04 Mar 2008 20:15:35 -0000 Subject: [llvm-commits] [llvm] r47899 - /llvm/trunk/lib/Archive/Archive.cpp Message-ID: <200803042015.m24KFZVg003325@zion.cs.uiuc.edu> Author: asl Date: Tue Mar 4 14:15:35 2008 New Revision: 47899 URL: http://llvm.org/viewvc/llvm-project?rev=47899&view=rev Log: Add alias with non-external aliasee to the list of exported symbols of the library. Modified: llvm/trunk/lib/Archive/Archive.cpp Modified: llvm/trunk/lib/Archive/Archive.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Archive/Archive.cpp?rev=47899&r1=47898&r2=47899&view=diff ============================================================================== --- llvm/trunk/lib/Archive/Archive.cpp (original) +++ llvm/trunk/lib/Archive/Archive.cpp Tue Mar 4 14:15:35 2008 @@ -198,11 +198,20 @@ if (!GI->getName().empty()) symbols.push_back(GI->getName()); - // Loop over functions. + // Loop over functions for (Module::iterator FI = M->begin(), FE = M->end(); FI != FE; ++FI) if (!FI->isDeclaration() && !FI->hasInternalLinkage()) if (!FI->getName().empty()) symbols.push_back(FI->getName()); + + // Loop over aliases + for (Module::alias_iterator AI = M->alias_begin(), AE = M->alias_end(); + AI != AE; ++AI) { + const GlobalValue *Aliased = AI->getAliasedGlobal(); + if (!Aliased->isDeclaration()) + if (AI->hasName()) + symbols.push_back(AI->getName()); + } } // Get just the externally visible defined symbols from the bitcode From asl at math.spbu.ru Tue Mar 4 14:16:11 2008 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Tue, 04 Mar 2008 20:16:11 -0000 Subject: [llvm-commits] [llvm] r47900 - /llvm/trunk/lib/Linker/LinkArchives.cpp Message-ID: <200803042016.m24KGBU8003352@zion.cs.uiuc.edu> Author: asl Date: Tue Mar 4 14:16:11 2008 New Revision: 47900 URL: http://llvm.org/viewvc/llvm-project?rev=47900&view=rev Log: Properly populate lists of defined/undefined symbols in presence of aliases Modified: llvm/trunk/lib/Linker/LinkArchives.cpp Modified: llvm/trunk/lib/Linker/LinkArchives.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Linker/LinkArchives.cpp?rev=47900&r1=47899&r2=47900&view=diff ============================================================================== --- llvm/trunk/lib/Linker/LinkArchives.cpp (original) +++ llvm/trunk/lib/Linker/LinkArchives.cpp Tue Mar 4 14:16:11 2008 @@ -56,6 +56,7 @@ DefinedSymbols.insert(I->getName()); } } + for (Module::global_iterator I = M->global_begin(), E = M->global_end(); I != E; ++I) if (I->hasName()) { @@ -68,6 +69,16 @@ } } + for (Module::alias_iterator I = M->alias_begin(), E = M->alias_end(); + I != E; ++I) + if (I->hasName()) { + const GlobalValue *Aliased = I->getAliasedGlobal(); + if (Aliased->isDeclaration()) + UndefinedSymbols.insert(I->getName()); + else + DefinedSymbols.insert(I->getName()); + } + // Prune out any defined symbols from the undefined symbols set... for (std::set::iterator I = UndefinedSymbols.begin(); I != UndefinedSymbols.end(); ) @@ -88,7 +99,6 @@ /// FALSE - No errors. bool Linker::LinkInArchive(const sys::Path &Filename, bool &is_native) { - // Make sure this is an archive file we're dealing with if (!Filename.isArchive()) return error("File '" + Filename.toString() + "' is not an archive."); From andrewl at lenharth.org Tue Mar 4 14:19:04 2008 From: andrewl at lenharth.org (Andrew Lenharth) Date: Tue, 4 Mar 2008 14:19:04 -0600 Subject: [llvm-commits] [llvm-gcc-4.2] r47801 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp In-Reply-To: <8EDB1B64-6A30-433B-A606-D108BD0C9B7E@apple.com> References: <200803012336.m21NaM6B018640@zion.cs.uiuc.edu> <8EDB1B64-6A30-433B-A606-D108BD0C9B7E@apple.com> Message-ID: <85dfcd7f0803041219r2bba36f7he19487951f9d830d@mail.gmail.com> right, 64 bit atomics aren't implemented on x86 yet. On 3/3/08, Evan Cheng wrote: > This breaks x86-64. libgomp/critical compiles to: > > define void @GOMP_critical_name_start(i8** %pptr) nounwind { > entry: > ... > tail call i64 @llvm.atomic.lcs.i64( i8** %pptr, i64 0, i64 > %tmp1314 ) ; :0 [#uses=1] > ... > ret void > } > > > Evan > > > > On Mar 1, 2008, at 3:36 PM, Andrew Lenharth wrote: > > > Author: alenhar2 > > Date: Sat Mar 1 17:36:21 2008 > > New Revision: 47801 > > > > URL: http://llvm.org/viewvc/llvm-project?rev=47801&view=rev > > Log: > > turn on some atomics for a couple platforms > > > > Modified: > > llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp > > > > Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp > > URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=47801&r1=47800&r2=47801&view=diff > > > > = > > = > > = > > = > > = > > = > > = > > = > > ====================================================================== > > --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) > > +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Sat Mar 1 17:36:21 2008 > > @@ -4294,7 +4294,7 @@ > > C, C + 5); > > return true; > > } > > -#if 0 //FIXME: these break the build for backends that haven't > > implemented them > > +#if defined(TARGET_386) || defined(TARGET_ALPHA) > > //gcc uses many names for the sync intrinsics > > case BUILT_IN_VAL_COMPARE_AND_SWAP_1: > > case BUILT_IN_VAL_COMPARE_AND_SWAP_2: > > > > > > _______________________________________________ > > llvm-commits mailing list > > llvm-commits at cs.uiuc.edu > > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From alenhar2 at cs.uiuc.edu Tue Mar 4 15:13:34 2008 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Tue, 04 Mar 2008 21:13:34 -0000 Subject: [llvm-commits] [llvm] r47903 - in /llvm/trunk/lib/Target/X86: X86ISelLowering.cpp X86Instr64bit.td Message-ID: <200803042113.m24LDY50005171@zion.cs.uiuc.edu> Author: alenhar2 Date: Tue Mar 4 15:13:33 2008 New Revision: 47903 URL: http://llvm.org/viewvc/llvm-project?rev=47903&view=rev Log: x86-64 atomics Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86Instr64bit.td Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=47903&r1=47902&r2=47903&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Mar 4 15:13:33 2008 @@ -291,6 +291,7 @@ setOperationAction(ISD::ATOMIC_LCS , MVT::i8, Custom); setOperationAction(ISD::ATOMIC_LCS , MVT::i16, Custom); setOperationAction(ISD::ATOMIC_LCS , MVT::i32, Custom); + setOperationAction(ISD::ATOMIC_LCS , MVT::i64, Custom); // Use the default ISD::LOCATION, ISD::DECLARE expansion. setOperationAction(ISD::LOCATION, MVT::Other, Expand); @@ -5356,12 +5357,13 @@ SDOperand X86TargetLowering::LowerCAS(SDOperand Op, SelectionDAG &DAG) { MVT::ValueType T = cast(Op.Val)->getVT(); - unsigned Reg; - unsigned size; + unsigned Reg = 0; + unsigned size = 0; switch(T) { case MVT::i8: Reg = X86::AL; size = 1; break; case MVT::i16: Reg = X86::AX; size = 2; break; case MVT::i32: Reg = X86::EAX; size = 4; break; + case MVT::i64: Reg = X86::RAX; size = 8; break; }; SDOperand cpIn = DAG.getCopyToReg(Op.getOperand(0), Reg, Op.getOperand(3), SDOperand()); Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=47903&r1=47902&r2=47903&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original) +++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Tue Mar 4 15:13:33 2008 @@ -1122,6 +1122,37 @@ "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}", [(set GR64:$dst, i64immZExt32:$src)]>; + +//===----------------------------------------------------------------------===// +// Atomic Instructions +//===----------------------------------------------------------------------===// + +//FIXME: Please check the format Pseudo is certainly wrong, but the opcode and +// prefixes should be correct + +let Defs = [RAX, EFLAGS], Uses = [RAX] in { +def CMPXCHG64 : RI<0xB1, Pseudo, (outs), (ins i64mem:$ptr, GR64:$swap), + "cmpxchgq $swap,$ptr", []>, TB; +def LCMPXCHG64 : RI<0xB1, Pseudo, (outs), (ins i64mem:$ptr, GR64:$swap), + "lock cmpxchgq $swap,$ptr", + [(X86cas addr:$ptr, GR64:$swap, 8)]>, TB, LOCK; +} + +let Constraints = "$val = $dst", Defs = [EFLAGS] in { +def LXADD64 : RI<0xC1, Pseudo, (outs GR64:$dst), (ins i64mem:$ptr, GR64:$val), + "lock xadd $val, $ptr", + [(set GR64:$dst, (atomic_las_64 addr:$ptr, GR64:$val))]>, + TB, LOCK; +def XADD64 : RI<0xC1, Pseudo, (outs GR64:$dst), (ins i64mem:$ptr, GR64:$val), + "xadd $val, $ptr", []>, TB; +def LXCHG64 : RI<0x87, Pseudo, (outs GR64:$dst), (ins i64mem:$ptr, GR64:$val), + "lock xchg $val, $ptr", + [(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>, LOCK; +def XCHG64 : RI<0x87, Pseudo, (outs GR64:$dst), (ins i64mem:$ptr, GR64:$val), + "xchg $val, $ptr", []>; +} + + //===----------------------------------------------------------------------===// // Non-Instruction Patterns //===----------------------------------------------------------------------===// From andrewl at lenharth.org Tue Mar 4 15:15:00 2008 From: andrewl at lenharth.org (Andrew Lenharth) Date: Tue, 4 Mar 2008 15:15:00 -0600 Subject: [llvm-commits] [llvm-gcc-4.2] r47801 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp In-Reply-To: <85dfcd7f0803041219r2bba36f7he19487951f9d830d@mail.gmail.com> References: <200803012336.m21NaM6B018640@zion.cs.uiuc.edu> <8EDB1B64-6A30-433B-A606-D108BD0C9B7E@apple.com> <85dfcd7f0803041219r2bba36f7he19487951f9d830d@mail.gmail.com> Message-ID: <85dfcd7f0803041315h63c9e79cvb90552e9733911ef@mail.gmail.com> fixed On 3/4/08, Andrew Lenharth wrote: > right, 64 bit atomics aren't implemented on x86 yet. > > > On 3/3/08, Evan Cheng wrote: > > This breaks x86-64. libgomp/critical compiles to: > > > > define void @GOMP_critical_name_start(i8** %pptr) nounwind { > > entry: > > ... > > tail call i64 @llvm.atomic.lcs.i64( i8** %pptr, i64 0, i64 > > %tmp1314 ) ; :0 [#uses=1] > > ... > > ret void > > } > > > > > > Evan > > > > > > > > On Mar 1, 2008, at 3:36 PM, Andrew Lenharth wrote: > > > > > Author: alenhar2 > > > Date: Sat Mar 1 17:36:21 2008 > > > New Revision: 47801 > > > > > > URL: http://llvm.org/viewvc/llvm-project?rev=47801&view=rev > > > Log: > > > turn on some atomics for a couple platforms > > > > > > Modified: > > > llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp > > > > > > Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp > > > URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=47801&r1=47800&r2=47801&view=diff > > > > > > = > > > = > > > = > > > = > > > = > > > = > > > = > > > = > > > ====================================================================== > > > --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) > > > +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Sat Mar 1 17:36:21 2008 > > > @@ -4294,7 +4294,7 @@ > > > C, C + 5); > > > return true; > > > } > > > -#if 0 //FIXME: these break the build for backends that haven't > > > implemented them > > > +#if defined(TARGET_386) || defined(TARGET_ALPHA) > > > //gcc uses many names for the sync intrinsics > > > case BUILT_IN_VAL_COMPARE_AND_SWAP_1: > > > case BUILT_IN_VAL_COMPARE_AND_SWAP_2: > > > > > > > > > _______________________________________________ > > > llvm-commits mailing list > > > llvm-commits at cs.uiuc.edu > > > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > > > _______________________________________________ > > llvm-commits mailing list > > llvm-commits at cs.uiuc.edu > > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > > From dpatel at apple.com Tue Mar 4 15:15:16 2008 From: dpatel at apple.com (Devang Patel) Date: Tue, 04 Mar 2008 21:15:16 -0000 Subject: [llvm-commits] [llvm] r47904 - in /llvm/trunk: lib/Transforms/Utils/InlineFunction.cpp test/Transforms/Inline/2008-03-04-StructRet.ll Message-ID: <200803042115.m24LFGx6005243@zion.cs.uiuc.edu> Author: dpatel Date: Tue Mar 4 15:15:15 2008 New Revision: 47904 URL: http://llvm.org/viewvc/llvm-project?rev=47904&view=rev Log: Handle multiple return values. Added: llvm/trunk/test/Transforms/Inline/2008-03-04-StructRet.ll Modified: llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp Modified: llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp?rev=47904&r1=47903&r2=47904&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp Tue Mar 4 15:15:15 2008 @@ -442,9 +442,21 @@ // If the return instruction returned a value, replace uses of the call with // uses of the returned value. - if (!TheCall->use_empty()) - TheCall->replaceAllUsesWith(Returns[0]->getReturnValue()); - + if (!TheCall->use_empty()) { + ReturnInst *R = Returns[0]; + if (R->getNumOperands() > 1) { + // Multiple return values. + for (Value::use_iterator RUI = TheCall->use_begin(), + RUE = TheCall->use_end(); RUI != RUE; ) { + GetResultInst *GR = dyn_cast(RUI++); + assert (GR && "Invalid Call instruction use!"); + Value *RV = R->getOperand(GR->getIndex()); + GR->replaceAllUsesWith(RV); + GR->eraseFromParent(); + } + } else + TheCall->replaceAllUsesWith(R->getReturnValue()); + } // Since we are now done with the Call/Invoke, we can delete it. TheCall->getParent()->getInstList().erase(TheCall); Added: llvm/trunk/test/Transforms/Inline/2008-03-04-StructRet.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/Inline/2008-03-04-StructRet.ll?rev=47904&view=auto ============================================================================== --- llvm/trunk/test/Transforms/Inline/2008-03-04-StructRet.ll (added) +++ llvm/trunk/test/Transforms/Inline/2008-03-04-StructRet.ll Tue Mar 4 15:15:15 2008 @@ -0,0 +1,26 @@ +; RUN: llvm-as < %s | opt -inline -sretpromotion -disable-output + %struct.Benchmark = type { i32 (...)** } + %struct.Complex = type { double, double } + %struct.ComplexBenchmark = type { %struct.Benchmark } + +define void @_Zml7ComplexS_(%struct.Complex* sret %agg.result, double %a.0, double %a.1, double %b.0, double %b.1) nounwind { +entry: + ret void +} + +define void @_ZNK16ComplexBenchmark9oop_styleEv(%struct.ComplexBenchmark* %this) nounwind { +entry: + %tmp = alloca %struct.Complex ; <%struct.Complex*> [#uses=2] + br label %bb31 + +bb: ; preds = %bb31 + call void @_Zml7ComplexS_( %struct.Complex* sret %tmp, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00 ) nounwind + %tmp21 = getelementptr %struct.Complex* %tmp, i32 0, i32 1 ; [#uses=0] + br label %bb31 + +bb31: ; preds = %bb, %entry + br i1 false, label %bb, label %return + +return: ; preds = %bb31 + ret void +} From clattner at apple.com Tue Mar 4 15:17:09 2008 From: clattner at apple.com (Chris Lattner) Date: Tue, 4 Mar 2008 13:17:09 -0800 Subject: [llvm-commits] [llvm] r47895 - in /llvm/trunk: include/llvm/DerivedTypes.h lib/VMCore/Type.cpp In-Reply-To: References: <200803041857.m24Iv6Ck000553@zion.cs.uiuc.edu> Message-ID: >>> URL: http://llvm.org/viewvc/llvm-project?rev=47895&view=rev >>> Log: >>> Add FunctionType ctor variant that takes SmallVector params. >>> >>> >>> #include "llvm/Type.h" >>> +#include "llvm/ADT/SmallVector.h" >> >> Instead of making this specific to smallvector, how about passing in >> pointer to pointer + count instead? That eliminates the #include and >> allows it to work with arrays on the stack and scalars. > > I will do that conversion also. I did not do it immediately because it > required many mechanical changes. Just start using it where you would use the smallvector one, other existing clients don't need to change. I'd really like to avoid DerivedTypes.h #including SmallVector. -Chris From alenhar2 at cs.uiuc.edu Tue Mar 4 15:18:39 2008 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Tue, 04 Mar 2008 21:18:39 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r47905 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Message-ID: <200803042118.m24LIdd4005387@zion.cs.uiuc.edu> Author: alenhar2 Date: Tue Mar 4 15:18:39 2008 New Revision: 47905 URL: http://llvm.org/viewvc/llvm-project?rev=47905&view=rev Log: x86-64 supports these now, this builds fine now on linux/x86-64 Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=47905&r1=47904&r2=47905&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Tue Mar 4 15:18:39 2008 @@ -4294,7 +4294,7 @@ C, C + 5); return true; } -#if defined(TARGET_ALPHA) +#if defined(TARGET_ALPHA) || defined(TARGET_386) //gcc uses many names for the sync intrinsics case BUILT_IN_VAL_COMPARE_AND_SWAP_1: case BUILT_IN_VAL_COMPARE_AND_SWAP_2: From clattner at apple.com Tue Mar 4 15:19:35 2008 From: clattner at apple.com (Chris Lattner) Date: Tue, 4 Mar 2008 13:19:35 -0800 Subject: [llvm-commits] [llvm] r47863 - in /llvm/trunk: include/llvm/CodeGen/RegisterScavenging.h lib/Target/PowerPC/PPCInstrInfo.cpp lib/Target/PowerPC/PPCInstrInfo.td lib/Target/PowerPC/PPCMachineFunctionInfo.h lib/Target/PowerPC/PPCRegisterInfo.cpp lib/Target/PowerPC/PPCRegisterInfo.h test/CodeGen/PowerPC/Frames-alloca.ll In-Reply-To: <200803032219.m23MJG6l015020@zion.cs.uiuc.edu> References: <200803032219.m23MJG6l015020@zion.cs.uiuc.edu> Message-ID: <2B2080EE-B63F-470C-9535-41097675B197@apple.com> On Mar 3, 2008, at 2:19 PM, Bill Wendling wrote: > Author: void > Date: Mon Mar 3 16:19:16 2008 > New Revision: 47863 > > URL: http://llvm.org/viewvc/llvm-project?rev=47863&view=rev > Log: > This is the initial check-in for adding register scavenging to PPC. > (Currently, > PPC-64 doesn't work.) This also lowers the spilling of the CR > registers so that > it uses a register other than the default R0 register (the scavenger > scrounges > for one). A significant part of this patch fixes how kill > information is > handled. To clarify, this is just not enabled for PPC64 - so it doesn't cause a regression, right? -Chris From clattner at apple.com Tue Mar 4 15:22:37 2008 From: clattner at apple.com (Chris Lattner) Date: Tue, 4 Mar 2008 13:22:37 -0800 Subject: [llvm-commits] [llvm] r47862 - /llvm/trunk/lib/CodeGen/MachineInstr.cpp In-Reply-To: <3D7E8268-D07B-4EAC-A8CD-BF2C4FEF1CA0@apple.com> References: <200803032214.m23MEXkF014824@zion.cs.uiuc.edu> <16e5fdf90803031522y7cd2c7c9nec7361de750844cf@mail.gmail.com> <72E52E44-C937-44C0-B9B6-5DA66057D71C@apple.com> <3D7E8268-D07B-4EAC-A8CD-BF2C4FEF1CA0@apple.com> Message-ID: <5012AB20-340A-46E2-8CB4-AFDB5E2B1190@apple.com> On Mar 3, 2008, at 3:47 PM, Evan Cheng wrote: > Haven't you heard goto's are evil? :-) > > I think goto's can be used tastefully. However, it's definitely not > the right situation to use it in this case. I agree, there are some cases when they aren't heinous, but those places are good indicators when something bigger is wrong. Often the body of the loop needs to be factored out into a helper function or something. -Chris From clattner at apple.com Tue Mar 4 15:31:08 2008 From: clattner at apple.com (Chris Lattner) Date: Tue, 4 Mar 2008 13:31:08 -0800 Subject: [llvm-commits] [llvm] r47904 - in /llvm/trunk: lib/Transforms/Utils/InlineFunction.cpp test/Transforms/Inline/2008-03-04-StructRet.ll In-Reply-To: <200803042115.m24LFGx6005243@zion.cs.uiuc.edu> References: <200803042115.m24LFGx6005243@zion.cs.uiuc.edu> Message-ID: On Mar 4, 2008, at 1:15 PM, Devang Patel wrote: > URL: http://llvm.org/viewvc/llvm-project?rev=47904&view=rev > Log: > Handle multiple return values. Nice. > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp (original) > +++ llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp Tue Mar 4 > 15:15:15 2008 > @@ -442,9 +442,21 @@ > > // If the return instruction returned a value, replace uses of > the call with > // uses of the returned value. > - if (!TheCall->use_empty()) > - TheCall->replaceAllUsesWith(Returns[0]->getReturnValue()); > - > + if (!TheCall->use_empty()) { > + ReturnInst *R = Returns[0]; > + if (R->getNumOperands() > 1) { > + // Multiple return values. > + for (Value::use_iterator RUI = TheCall->use_begin(), > + RUE = TheCall->use_end(); RUI != RUE; ) { > + GetResultInst *GR = dyn_cast(RUI++); > > + assert (GR && "Invalid Call instruction use!"); Just use cast<> here instead of dyn_cast. cast<> doesn't have a cost when assertions are disabled, dyn_cast does, this also allows you to remove the assert. Also, it isn't a big deal, but it is more idiomatic and simpler to write the loop as: while (!TheCall->use_empty()) { GetResultInst *GR = cast(TheCall->use_back()); ... } > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/test/Transforms/Inline/2008-03-04-StructRet.ll (added) > +++ llvm/trunk/test/Transforms/Inline/2008-03-04-StructRet.ll Tue > Mar 4 15:15:15 2008 > @@ -0,0 +1,26 @@ > +; RUN: llvm-as < %s | opt -inline -sretpromotion -disable-output This test should not run sretpromotion, just use a .ll file from after sretpromotion is run. -Chris > > + %struct.Benchmark = type { i32 (...)** } > + %struct.Complex = type { double, double } > + %struct.ComplexBenchmark = type { %struct.Benchmark } > + > +define void @_Zml7ComplexS_(%struct.Complex* sret %agg.result, > double %a.0, double %a.1, double %b.0, double %b.1) nounwind { > +entry: > + ret void > +} > + > +define void > @_ZNK16ComplexBenchmark9oop_styleEv(%struct.ComplexBenchmark* %this) > nounwind { > +entry: > + %tmp = alloca %struct.Complex ; <%struct.Complex*> [#uses=2] > + br label %bb31 > + > +bb: ; preds = %bb31 > + call void @_Zml7ComplexS_( %struct.Complex* sret %tmp, double > 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double > 0.000000e+00 ) nounwind > + %tmp21 = getelementptr %struct.Complex* %tmp, i32 0, i32 1 ; > [#uses=0] > + br label %bb31 > + > +bb31: ; preds = %bb, %entry > + br i1 false, label %bb, label %return > + > +return: ; preds = %bb31 > + ret void > +} > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From dpatel at apple.com Tue Mar 4 15:32:09 2008 From: dpatel at apple.com (Devang Patel) Date: Tue, 04 Mar 2008 21:32:09 -0000 Subject: [llvm-commits] [llvm] r47906 - /llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp Message-ID: <200803042132.m24LW94w005772@zion.cs.uiuc.edu> Author: dpatel Date: Tue Mar 4 15:32:09 2008 New Revision: 47906 URL: http://llvm.org/viewvc/llvm-project?rev=47906&view=rev Log: Filter nested structs Modified: llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp Modified: llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp?rev=47906&r1=47905&r2=47906&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp Tue Mar 4 15:32:09 2008 @@ -48,6 +48,7 @@ bool isSafeToUpdateAllCallers(Function *F); Function *cloneFunctionBody(Function *F, const StructType *STy); void updateCallSites(Function *F, Function *NF); + bool nestedStructType(const StructType *STy); }; char SRETPromotion::ID = 0; @@ -88,6 +89,9 @@ dyn_cast(FArgType->getElementType()); assert (STy && "Invalid sret parameter element type"); + if (nestedStructType(STy)) + return false; + // Check if it is ok to perform this promotion. if (isSafeToUpdateAllCallers(F) == false) { NumRejectedSRETUses++; @@ -319,3 +323,15 @@ Call->eraseFromParent(); } } + +/// nestedStructType - Return true if STy includes any +/// other aggregate types +bool SRETPromotion::nestedStructType(const StructType *STy) { + unsigned Num = STy->getNumElements(); + for (unsigned i = 0; i < Num; i++) { + const Type *Ty = STy->getElementType(i); + if (!Ty->isFirstClassType() && Ty != Type::VoidTy) + return true; + } + return false; +} From dpatel at apple.com Tue Mar 4 15:45:28 2008 From: dpatel at apple.com (Devang Patel) Date: Tue, 04 Mar 2008 21:45:28 -0000 Subject: [llvm-commits] [llvm] r47907 - in /llvm/trunk: lib/Transforms/Utils/InlineFunction.cpp test/Transforms/Inline/2008-03-04-StructRet.ll Message-ID: <200803042145.m24LjSdX006288@zion.cs.uiuc.edu> Author: dpatel Date: Tue Mar 4 15:45:28 2008 New Revision: 47907 URL: http://llvm.org/viewvc/llvm-project?rev=47907&view=rev Log: Use cast instead of dyn_cast. Update test to use multiple return value directly, instead of relying on -sretpromotion. Modified: llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp llvm/trunk/test/Transforms/Inline/2008-03-04-StructRet.ll Modified: llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp?rev=47907&r1=47906&r2=47907&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp Tue Mar 4 15:45:28 2008 @@ -448,8 +448,7 @@ // Multiple return values. for (Value::use_iterator RUI = TheCall->use_begin(), RUE = TheCall->use_end(); RUI != RUE; ) { - GetResultInst *GR = dyn_cast(RUI++); - assert (GR && "Invalid Call instruction use!"); + GetResultInst *GR = cast(RUI++); Value *RV = R->getOperand(GR->getIndex()); GR->replaceAllUsesWith(RV); GR->eraseFromParent(); Modified: llvm/trunk/test/Transforms/Inline/2008-03-04-StructRet.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/Inline/2008-03-04-StructRet.ll?rev=47907&r1=47906&r2=47907&view=diff ============================================================================== --- llvm/trunk/test/Transforms/Inline/2008-03-04-StructRet.ll (original) +++ llvm/trunk/test/Transforms/Inline/2008-03-04-StructRet.ll Tue Mar 4 15:45:28 2008 @@ -1,26 +1,28 @@ -; RUN: llvm-as < %s | opt -inline -sretpromotion -disable-output +; RUN: llvm-as < %s | opt -inline -disable-output %struct.Benchmark = type { i32 (...)** } %struct.Complex = type { double, double } %struct.ComplexBenchmark = type { %struct.Benchmark } -define void @_Zml7ComplexS_(%struct.Complex* sret %agg.result, double %a.0, double %a.1, double %b.0, double %b.1) nounwind { +define %struct.Complex @_Zml7ComplexS_1(double %a.0, double %a.1, double %b.0, double %b.1) nounwind { entry: - ret void + %mrv = alloca %struct.Complex ; <%struct.Complex*> [#uses=2] + %mrv.gep = getelementptr %struct.Complex* %mrv, i32 0, i32 0 ; [#uses=1] + %mrv.ld = load double* %mrv.gep ; [#uses=1] + %mrv.gep1 = getelementptr %struct.Complex* %mrv, i32 0, i32 1 ; [#uses=1] + %mrv.ld2 = load double* %mrv.gep1 ; [#uses=1] + ret double %mrv.ld, double %mrv.ld2 } define void @_ZNK16ComplexBenchmark9oop_styleEv(%struct.ComplexBenchmark* %this) nounwind { entry: - %tmp = alloca %struct.Complex ; <%struct.Complex*> [#uses=2] + %tmp = alloca %struct.Complex ; <%struct.Complex*> [#uses=0] br label %bb31 - bb: ; preds = %bb31 - call void @_Zml7ComplexS_( %struct.Complex* sret %tmp, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00 ) nounwind - %tmp21 = getelementptr %struct.Complex* %tmp, i32 0, i32 1 ; [#uses=0] + call %struct.Complex @_Zml7ComplexS_1( double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00 ) nounwind ; <%struct.Complex>:0 [#uses=1] + %gr = getresult %struct.Complex %0, 1 ; [#uses=0] br label %bb31 - bb31: ; preds = %bb, %entry br i1 false, label %bb, label %return - return: ; preds = %bb31 ret void } From dpatel at apple.com Tue Mar 4 15:46:01 2008 From: dpatel at apple.com (Devang Patel) Date: Tue, 4 Mar 2008 13:46:01 -0800 Subject: [llvm-commits] [llvm] r47904 - in /llvm/trunk: lib/Transforms/Utils/InlineFunction.cpp test/Transforms/Inline/2008-03-04-StructRet.ll In-Reply-To: References: <200803042115.m24LFGx6005243@zion.cs.uiuc.edu> Message-ID: <49A88053-2044-4F73-AFCF-220D41E9F57D@apple.com> On Mar 4, 2008, at 1:31 PM, Chris Lattner wrote: > > Just use cast<> here instead of dyn_cast. cast<> doesn't have a cost > when assertions are disabled, dyn_cast does, this also allows you to > remove the assert. > > Also, it isn't a big deal, but it is more idiomatic and simpler to > write the loop as: > > while (!TheCall->use_empty()) { > GetResultInst *GR = cast(TheCall->use_back()); > ... > } ok >> >> = >> ===================================================================== >> --- llvm/trunk/test/Transforms/Inline/2008-03-04-StructRet.ll (added) >> +++ llvm/trunk/test/Transforms/Inline/2008-03-04-StructRet.ll Tue >> Mar 4 15:15:15 2008 >> @@ -0,0 +1,26 @@ >> +; RUN: llvm-as < %s | opt -inline -sretpromotion -disable-output > > This test should not run sretpromotion, just use a .ll file from after > sretpromotion is run. Done. - Devang From isanbard at gmail.com Tue Mar 4 15:54:03 2008 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 4 Mar 2008 13:54:03 -0800 Subject: [llvm-commits] [llvm] r47863 - in /llvm/trunk: include/llvm/CodeGen/RegisterScavenging.h lib/Target/PowerPC/PPCInstrInfo.cpp lib/Target/PowerPC/PPCInstrInfo.td lib/Target/PowerPC/PPCMachineFunctionInfo.h lib/Target/PowerPC/PPCRegisterInfo.cpp lib Message-ID: <16e5fdf90803041354g24548589y8fbc2a9402bb2ccf@mail.gmail.com> On Tue, Mar 4, 2008 at 1:19 PM, Chris Lattner wrote: > > On Mar 3, 2008, at 2:19 PM, Bill Wendling wrote: > > Author: void > > Date: Mon Mar 3 16:19:16 2008 > > New Revision: 47863 > > > > URL: http://llvm.org/viewvc/llvm-project?rev=47863&view=rev > > Log: > > This is the initial check-in for adding register scavenging to PPC. > > (Currently, > > PPC-64 doesn't work.) This also lowers the spilling of the CR > > registers so that > > it uses a register other than the default R0 register (the scavenger > > scrounges > > for one). A significant part of this patch fixes how kill > > information is > > handled. > > To clarify, this is just not enabled for PPC64 - so it doesn't cause a > regression, right? > This shouldn't regress PPC64, yes. -bw From dpatel at apple.com Tue Mar 4 15:54:56 2008 From: dpatel at apple.com (Devang Patel) Date: Tue, 04 Mar 2008 21:54:56 -0000 Subject: [llvm-commits] [llvm] r47908 - in /llvm/trunk: include/llvm/DerivedTypes.h lib/VMCore/Type.cpp Message-ID: <200803042154.m24Lsuq1006614@zion.cs.uiuc.edu> Author: dpatel Date: Tue Mar 4 15:54:56 2008 New Revision: 47908 URL: http://llvm.org/viewvc/llvm-project?rev=47908&view=rev Log: Revert SmallVector ctor variants. Modified: llvm/trunk/include/llvm/DerivedTypes.h llvm/trunk/lib/VMCore/Type.cpp Modified: llvm/trunk/include/llvm/DerivedTypes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/DerivedTypes.h?rev=47908&r1=47907&r2=47908&view=diff ============================================================================== --- llvm/trunk/include/llvm/DerivedTypes.h (original) +++ llvm/trunk/include/llvm/DerivedTypes.h Tue Mar 4 15:54:56 2008 @@ -19,7 +19,6 @@ #define LLVM_DERIVED_TYPES_H #include "llvm/Type.h" -#include "llvm/ADT/SmallVector.h" namespace llvm { @@ -145,8 +144,6 @@ const FunctionType &operator=(const FunctionType &); // Do not implement FunctionType(const Type *Result, const std::vector &Params, bool IsVarArgs); - FunctionType(const Type *Result, const SmallVectorImpl &Params, - bool IsVarArgs); public: /// FunctionType::get - This static method is the primary way of constructing @@ -158,12 +155,6 @@ bool isVarArg ///< Whether this is a variable argument length function ); - static FunctionType *get( - const Type *Result, ///< The result type - const SmallVectorImpl &Params, ///< The types of the parameters - bool isVarArg ///< Whether this is a variable argument length function - ); - inline bool isVarArg() const { return isVarArgs; } inline const Type *getReturnType() const { return ContainedTys[0]; } Modified: llvm/trunk/lib/VMCore/Type.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Type.cpp?rev=47908&r1=47907&r2=47908&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Type.cpp (original) +++ llvm/trunk/lib/VMCore/Type.cpp Tue Mar 4 15:54:56 2008 @@ -460,30 +460,6 @@ setAbstract(isAbstract); } -FunctionType::FunctionType(const Type *Result, - const SmallVectorImpl &Params, - bool IsVarArgs) - : DerivedType(FunctionTyID), isVarArgs(IsVarArgs) { - ContainedTys = reinterpret_cast(this+1); - NumContainedTys = Params.size() + 1; // + 1 for result type - assert((Result->isFirstClassType() || Result == Type::VoidTy || - Result->getTypeID() == Type::StructTyID || - isa(Result)) && - "LLVM functions cannot return aggregates"); - bool isAbstract = Result->isAbstract(); - new (&ContainedTys[0]) PATypeHandle(Result, this); - - for (unsigned i = 0; i != Params.size(); ++i) { - assert((Params[i]->isFirstClassType() || isa(Params[i])) && - "Function arguments must be value types!"); - new (&ContainedTys[i+1]) PATypeHandle(Params[i],this); - isAbstract |= Params[i]->isAbstract(); - } - - // Calculate whether or not this type is abstract - setAbstract(isAbstract); -} - StructType::StructType(const std::vector &Types, bool isPacked) : CompositeType(StructTyID) { ContainedTys = reinterpret_cast(this + 1); @@ -1079,12 +1055,6 @@ ArgTypes.push_back(args[i]); } - FunctionValType(const Type *ret, const SmallVectorImpl &args, - bool isVA) : RetTy(ret), isVarArg(isVA) { - for (unsigned i = 0; i < args.size(); ++i) - ArgTypes.push_back(args[i]); - } - static FunctionValType get(const FunctionType *FT); static unsigned hashTypeStructure(const FunctionType *FT) { @@ -1138,27 +1108,6 @@ return FT; } -// FunctionType::get - The factory function for the FunctionType class... -FunctionType *FunctionType::get(const Type *ReturnType, - const SmallVectorImpl &Params, - bool isVarArg) { - FunctionValType VT(ReturnType, Params, isVarArg); - FunctionType *FT = FunctionTypes->get(VT); - if (FT) { - return FT; - } - - FT = (FunctionType*) new char[sizeof(FunctionType) + - sizeof(PATypeHandle)*(Params.size()+1)]; - new (FT) FunctionType(ReturnType, Params, isVarArg); - FunctionTypes->add(VT, FT); - -#ifdef DEBUG_MERGE_TYPES - DOUT << "Derived new type: " << FT << "\n"; -#endif - return FT; -} - //===----------------------------------------------------------------------===// // Array Type Factory... // From dpatel at apple.com Tue Mar 4 15:55:53 2008 From: dpatel at apple.com (Devang Patel) Date: Tue, 4 Mar 2008 13:55:53 -0800 Subject: [llvm-commits] [llvm] r47895 - in /llvm/trunk: include/llvm/DerivedTypes.h lib/VMCore/Type.cpp In-Reply-To: References: <200803041857.m24Iv6Ck000553@zion.cs.uiuc.edu> Message-ID: <0534867B-89DC-447E-98BA-189B21D6CFAC@apple.com> On Mar 4, 2008, at 1:17 PM, Chris Lattner wrote: >>>> URL: http://llvm.org/viewvc/llvm-project?rev=47895&view=rev >>>> Log: >>>> Add FunctionType ctor variant that takes SmallVector params. >>>> >>>> >>>> #include "llvm/Type.h" >>>> +#include "llvm/ADT/SmallVector.h" >>> >>> Instead of making this specific to smallvector, how about passing in >>> pointer to pointer + count instead? That eliminates the #include >>> and >>> allows it to work with arrays on the stack and scalars. >> >> I will do that conversion also. I did not do it immediately because >> it >> required many mechanical changes. > > Just start using it where you would use the smallvector one, other > existing clients don't need to change. I'd really like to avoid > DerivedTypes.h #including SmallVector. My simplification run into something else, so I am not using SmallVector version right now. I just reverted this patch for now :) - Devang From dpatel at apple.com Tue Mar 4 15:59:49 2008 From: dpatel at apple.com (Devang Patel) Date: Tue, 04 Mar 2008 21:59:49 -0000 Subject: [llvm-commits] [llvm] r47909 - /llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp Message-ID: <200803042159.m24Lxn2X006800@zion.cs.uiuc.edu> Author: dpatel Date: Tue Mar 4 15:59:49 2008 New Revision: 47909 URL: http://llvm.org/viewvc/llvm-project?rev=47909&view=rev Log: Use while loop. Modified: llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp Modified: llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp?rev=47909&r1=47908&r2=47909&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp Tue Mar 4 15:59:49 2008 @@ -446,9 +446,8 @@ ReturnInst *R = Returns[0]; if (R->getNumOperands() > 1) { // Multiple return values. - for (Value::use_iterator RUI = TheCall->use_begin(), - RUE = TheCall->use_end(); RUI != RUE; ) { - GetResultInst *GR = cast(RUI++); + while (!TheCall->use_empty()) { + GetResultInst *GR = cast(TheCall->use_back()); Value *RV = R->getOperand(GR->getIndex()); GR->replaceAllUsesWith(RV); GR->eraseFromParent(); From dpatel at apple.com Tue Mar 4 16:05:14 2008 From: dpatel at apple.com (Devang Patel) Date: Tue, 04 Mar 2008 22:05:14 -0000 Subject: [llvm-commits] [llvm] r47911 - /llvm/trunk/lib/VMCore/AsmWriter.cpp Message-ID: <200803042205.m24M5EgE007013@zion.cs.uiuc.edu> Author: dpatel Date: Tue Mar 4 16:05:14 2008 New Revision: 47911 URL: http://llvm.org/viewvc/llvm-project?rev=47911&view=rev Log: Print types for all ret operands. Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AsmWriter.cpp?rev=47911&r1=47910&r2=47911&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/AsmWriter.cpp (original) +++ llvm/trunk/lib/VMCore/AsmWriter.cpp Tue Mar 4 16:05:14 2008 @@ -1417,7 +1417,8 @@ const Type *TheType = Operand->getType(); // Select, Store and ShuffleVector always print all types. - if (isa(I) || isa(I) || isa(I)) { + if (isa(I) || isa(I) || isa(I) + || isa(I)) { PrintAllTypes = true; } else { for (unsigned i = 1, E = I.getNumOperands(); i != E; ++i) { From andrewl at lenharth.org Tue Mar 4 16:23:16 2008 From: andrewl at lenharth.org (Andrew Lenharth) Date: Tue, 4 Mar 2008 16:23:16 -0600 Subject: [llvm-commits] [llvm-gcc-4.2] r47905 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp In-Reply-To: <200803042118.m24LIdd4005387@zion.cs.uiuc.edu> References: <200803042118.m24LIdd4005387@zion.cs.uiuc.edu> Message-ID: <85dfcd7f0803041423o521976ep8f15a9304b3570f9@mail.gmail.com> x86-32 doesn't support 64 bit CAS, working on it. On 3/4/08, Andrew Lenharth wrote: > Author: alenhar2 > Date: Tue Mar 4 15:18:39 2008 > New Revision: 47905 > > URL: http://llvm.org/viewvc/llvm-project?rev=47905&view=rev > Log: > x86-64 supports these now, this builds fine now on linux/x86-64 > > Modified: > llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp > > Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=47905&r1=47904&r2=47905&view=diff > > ============================================================================== > --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) > +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Tue Mar 4 15:18:39 2008 > @@ -4294,7 +4294,7 @@ > C, C + 5); > return true; > } > -#if defined(TARGET_ALPHA) > +#if defined(TARGET_ALPHA) || defined(TARGET_386) > //gcc uses many names for the sync intrinsics > case BUILT_IN_VAL_COMPARE_AND_SWAP_1: > case BUILT_IN_VAL_COMPARE_AND_SWAP_2: > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From gohman at apple.com Tue Mar 4 16:39:55 2008 From: gohman at apple.com (Dan Gohman) Date: Tue, 4 Mar 2008 14:39:55 -0800 Subject: [llvm-commits] Fwd: Patch for review: Speeding up ScheduleDAG computations In-Reply-To: References: <522BCA72-6445-4857-BE7B-019B841AA9DB@apple.com> <2DFEE2ED-2D57-4310-8F6C-1B08F18D4363@apple.com> Message-ID: <388F3E9D-F770-402B-8744-6D1501642885@apple.com> On Mar 4, 2008, at 10:37 AM, Roman Levenstein wrote: >> >> I thought those were approved? We understanding std::set is probably >> the best choice of ADT for now. Thanks! > > OK. I'll commit them tomorrow. Great! Note that I did have one comment on the ScheduleDAGList.cpp patch. > > But are you sure about the second one for the ScheduleDAGRRList? > I mean this: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20080303/059078.html I just took a look at this one. Here are my comments. > + // This may break the ordering in the priority queue. > PredSU->CycleBound = std::max(PredSU->CycleBound, > I->Dep->Cycle + PredSU->Latency); This seems dangerous. After this is done, updateNode is called, which attempts to remove the node from the set, but if the node has changed in a way that's significant to the comparison function, that remove may not work properly. It looks like the only way to be safe is to remove the node from the queue before making any modifications. > + for (unsigned i = 0, e = Nodes.size(); i != e; ++i) { > + Queue.insert(Nodes[i]); > + } This could be simplified with Queue.insert(Nodes.begin(), Nodes.end()); > + SUnit *V = *Queue.rbegin(); > + Queue.erase(--Queue.end(),Queue.end()); This could be simplified with Queue.erase(prior(Queue.end()); or even iterator i = prior(Queue.rbegin()); SUnit *V = *i; Queue.erase(i); `prior' is defined in llvm/ADT/STLExtras.h. > - unsigned LBonus = (SumOfUnscheduledPredsOfSuccs(left) == 1) ? 2 : 0; > - unsigned RBonus = (SumOfUnscheduledPredsOfSuccs(right) == 1) ? 2 : 0; > + unsigned LBonus = (SumOfUnscheduledPredsOfSuccs(left,1) == 1) ? 2 : 0; > + unsigned RBonus = (SumOfUnscheduledPredsOfSuccs(right,1) == 1) ? 2 : 0; It's not clear to me what this change is doing. Well, the original code isn't quite clear to me either :-}. Is this a heuristic change? Dan From isanbard at gmail.com Tue Mar 4 17:13:51 2008 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 04 Mar 2008 23:13:51 -0000 Subject: [llvm-commits] [llvm] r47915 - in /llvm/trunk/lib/Target/PowerPC: PPCInstrInfo.cpp PPCRegisterInfo.cpp Message-ID: <200803042313.m24NDqcq009236@zion.cs.uiuc.edu> Author: void Date: Tue Mar 4 17:13:51 2008 New Revision: 47915 URL: http://llvm.org/viewvc/llvm-project?rev=47915&view=rev Log: Use a command-line option to turn register scavenging on/off for PPC. Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=47915&r1=47914&r2=47915&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Tue Mar 4 17:13:51 2008 @@ -19,8 +19,11 @@ #include "PPCTargetMachine.h" #include "llvm/ADT/STLExtras.h" #include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/Support/CommandLine.h" using namespace llvm; +extern cl::opt EnablePPCRS; // FIXME (64-bit): See PPCRegisterInfo.cpp. + PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm) : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm), RI(*TM.getSubtargetImpl(), *this) {} @@ -320,8 +323,7 @@ static bool StoreRegToStackSlot(const TargetInstrInfo &TII, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, - SmallVectorImpl &NewMIs, - bool isPPC64/*FIXME (64-bit): Remove.*/) { + SmallVectorImpl &NewMIs) { if (RC == PPC::GPRCRegisterClass) { if (SrcReg != PPC::LR) { NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW)) @@ -353,7 +355,7 @@ NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STFS)) .addReg(SrcReg, false, false, isKill), FrameIdx)); } else if (RC == PPC::CRRCRegisterClass) { - if (!isPPC64) { // FIXME (64-bit): Enable + if (EnablePPCRS) { // FIXME (64-bit): Enable NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::SPILL_CR)) .addReg(SrcReg, false, false, isKill), FrameIdx)); @@ -402,8 +404,7 @@ const TargetRegisterClass *RC) const { SmallVector NewMIs; - if (StoreRegToStackSlot(*this, SrcReg, isKill, FrameIdx, RC, NewMIs, - TM.getSubtargetImpl()->isPPC64()/*FIXME (64-bit): Remove.*/)) { + if (StoreRegToStackSlot(*this, SrcReg, isKill, FrameIdx, RC, NewMIs)) { PPCFunctionInfo *FuncInfo = MBB.getParent()->getInfo(); FuncInfo->setSpillsCR(); } @@ -418,8 +419,8 @@ const TargetRegisterClass *RC, SmallVectorImpl &NewMIs) const{ if (Addr[0].isFrameIndex()) { - if (StoreRegToStackSlot(*this, SrcReg, isKill, Addr[0].getIndex(), RC, NewMIs, - TM.getSubtargetImpl()->isPPC64()/*FIXME (64-bit): Remove.*/)) { + if (StoreRegToStackSlot(*this, SrcReg, isKill, Addr[0].getIndex(), + RC, NewMIs)) { PPCFunctionInfo *FuncInfo = MF.getInfo(); FuncInfo->setSpillsCR(); } Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=47915&r1=47914&r2=47915&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Tue Mar 4 17:13:51 2008 @@ -42,10 +42,16 @@ #include using namespace llvm; +// FIXME (64-bit): Eventually enable by default. +cl::opt EnablePPCRS("enable-ppc-regscavenger", + cl::init(false), + cl::desc("enable PPC register scavenger"), + cl::Hidden); + // FIXME (64-bit): Should be inlined. bool PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const { - return !Subtarget.isPPC64(); + return EnablePPCRS; } /// getRegisterNumbering - Given the enum value for some register, e.g. @@ -310,7 +316,8 @@ Reserved.set(PPC::R13); Reserved.set(PPC::R31); - Reserved.set(PPC::R0); // FIXME (64-bit): Remove + if (!EnablePPCRS) + Reserved.set(PPC::R0); // FIXME (64-bit): Remove Reserved.set(PPC::X0); Reserved.set(PPC::X1); @@ -414,7 +421,7 @@ // FIXME (64-bit): Use "findScratchRegister" unsigned Reg; - if (!LP64) + if (EnablePPCRS) Reg = findScratchRegister(II, RS, RC, SPAdj); else Reg = PPC::R0; @@ -424,10 +431,15 @@ .addReg(PPC::R31) .addImm(FrameSize); } else if (LP64) { - Reg = PPC::X0; // FIXME (64-bit): Remove. - BuildMI(MBB, II, TII.get(PPC::LD), Reg) - .addImm(0) - .addReg(PPC::X1); + if (!EnablePPCRS) + if (EnablePPCRS) // FIXME (64-bit): Use "true" version. + BuildMI(MBB, II, TII.get(PPC::LD), Reg) + .addImm(0) + .addReg(PPC::X1); + else + BuildMI(MBB, II, TII.get(PPC::LD), PPC::X0) + .addImm(0) + .addReg(PPC::X1); } else { BuildMI(MBB, II, TII.get(PPC::LWZ), Reg) .addImm(0) @@ -437,17 +449,16 @@ // Grow the stack and update the stack pointer link, then determine the // address of new allocated space. if (LP64) { -#if 0 // FIXME (64-bit): Enable - BuildMI(MBB, II, TII.get(PPC::STDUX)) - .addReg(Reg, false, false, true) - .addReg(PPC::X1) - .addReg(MI.getOperand(1).getReg()); -#else - BuildMI(MBB, II, TII.get(PPC::STDUX)) - .addReg(PPC::X0, false, false, true) - .addReg(PPC::X1) - .addReg(MI.getOperand(1).getReg()); -#endif + if (EnablePPCRS) // FIXME (64-bit): Use "true" version. + BuildMI(MBB, II, TII.get(PPC::STDUX)) + .addReg(Reg, false, false, true) + .addReg(PPC::X1) + .addReg(MI.getOperand(1).getReg()); + else + BuildMI(MBB, II, TII.get(PPC::STDUX)) + .addReg(PPC::X0, false, false, true) + .addReg(PPC::X1) + .addReg(MI.getOperand(1).getReg()); if (!MI.getOperand(1).isKill()) BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) @@ -573,11 +584,11 @@ } // Special case for pseudo-op SPILL_CR. - if (!Subtarget.isPPC64()) // FIXME (64-bit): Remove. - if (OpC == PPC::SPILL_CR) { - lowerCRSpilling(II, FrameIndex, SPAdj, RS); - return; - } + if (EnablePPCRS) // FIXME (64-bit): Enable by default + if (OpC == PPC::SPILL_CR) { + lowerCRSpilling(II, FrameIndex, SPAdj, RS); + return; + } // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). MI.getOperand(FIOperandNo).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1, @@ -627,7 +638,7 @@ // FIXME (64-bit): Use "findScratchRegister". unsigned SReg; - if (!Subtarget.isPPC64()) + if (EnablePPCRS) SReg = findScratchRegister(II, RS, &PPC::GPRCRegClass, SPAdj); else SReg = PPC::R0; @@ -879,14 +890,14 @@ // FIXME: doesn't detect whether or not we need to spill vXX, which requires // r0 for now. - if (!IsPPC64) // FIXME (64-bit): Enable. - if (needsFP(MF) || spillsCR(MF)) { - const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; - const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; - const TargetRegisterClass *RC = IsPPC64 ? G8RC : GPRC; - RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), - RC->getAlignment())); - } + if (EnablePPCRS) // FIXME (64-bit): Enable. + if (needsFP(MF) || spillsCR(MF)) { + const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; + const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; + const TargetRegisterClass *RC = IsPPC64 ? G8RC : GPRC; + RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), + RC->getAlignment())); + } } void From isanbard at gmail.com Tue Mar 4 17:16:26 2008 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 04 Mar 2008 23:16:26 -0000 Subject: [llvm-commits] [llvm] r47916 - /llvm/trunk/test/CodeGen/PowerPC/Frames-alloca.ll Message-ID: <200803042316.m24NGQbD009314@zion.cs.uiuc.edu> Author: void Date: Tue Mar 4 17:16:26 2008 New Revision: 47916 URL: http://llvm.org/viewvc/llvm-project?rev=47916&view=rev Log: Use -enable-ppc-regscavenger flag for these checks Modified: llvm/trunk/test/CodeGen/PowerPC/Frames-alloca.ll Modified: llvm/trunk/test/CodeGen/PowerPC/Frames-alloca.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/Frames-alloca.ll?rev=47916&r1=47915&r2=47916&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/PowerPC/Frames-alloca.ll (original) +++ llvm/trunk/test/CodeGen/PowerPC/Frames-alloca.ll Tue Mar 4 17:16:26 2008 @@ -1,6 +1,6 @@ ; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | \ ; RUN: grep {stw r31, 20(r1)} -; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | \ +; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -enable-ppc-regscavenger | \ ; RUN: grep {stwu r1, -80(r1)} ; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | \ ; RUN: grep {lwz r1, 0(r1)} @@ -8,7 +8,7 @@ ; RUN: grep {lwz r31, 20(r1)} ; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | \ ; RUN: grep {stw r31, 20(r1)} -; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | \ +; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim -enable-ppc-regscavenger | \ ; RUN: grep {stwu r1, -80(r1)} ; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | \ ; RUN: grep {lwz r1, 0(r1)} From dalej at apple.com Tue Mar 4 17:17:14 2008 From: dalej at apple.com (Dale Johannesen) Date: Tue, 04 Mar 2008 23:17:14 -0000 Subject: [llvm-commits] [llvm] r47917 - in /llvm/trunk/lib/Target/PowerPC: PPCISelLowering.cpp PPCISelLowering.h Message-ID: <200803042317.m24NHEwO009351@zion.cs.uiuc.edu> Author: johannes Date: Tue Mar 4 17:17:14 2008 New Revision: 47917 URL: http://llvm.org/viewvc/llvm-project?rev=47917&view=rev Log: Move PPC lowering functions into PPCTargetLowering class (cosmetic). First piece of byval implementation; this doesn't work yet. No functional change. Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=47917&r1=47916&r2=47917&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Tue Mar 4 17:17:14 2008 @@ -1026,7 +1026,8 @@ // LowerOperation implementation //===----------------------------------------------------------------------===// -static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) { +SDOperand PPCTargetLowering::LowerConstantPool(SDOperand Op, + SelectionDAG &DAG) { MVT::ValueType PtrVT = Op.getValueType(); ConstantPoolSDNode *CP = cast(Op); Constant *C = CP->getConstVal(); @@ -1057,7 +1058,7 @@ return Lo; } -static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) { +SDOperand PPCTargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) { MVT::ValueType PtrVT = Op.getValueType(); JumpTableSDNode *JT = cast(Op); SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); @@ -1087,11 +1088,13 @@ return Lo; } -static SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) { +SDOperand PPCTargetLowering::LowerGlobalTLSAddress(SDOperand Op, + SelectionDAG &DAG) { assert(0 && "TLS not implemented for PPC."); } -static SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) { +SDOperand PPCTargetLowering::LowerGlobalAddress(SDOperand Op, + SelectionDAG &DAG) { MVT::ValueType PtrVT = Op.getValueType(); GlobalAddressSDNode *GSDN = cast(Op); GlobalValue *GV = GSDN->getGlobal(); @@ -1131,7 +1134,7 @@ return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, NULL, 0); } -static SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG) { +SDOperand PPCTargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG) { ISD::CondCode CC = cast(Op.getOperand(2))->get(); // If we're comparing for equality to zero, expose the fact that this is @@ -1173,7 +1176,7 @@ return SDOperand(); } -static SDOperand LowerVAARG(SDOperand Op, SelectionDAG &DAG, +SDOperand PPCTargetLowering::LowerVAARG(SDOperand Op, SelectionDAG &DAG, int VarArgsFrameIndex, int VarArgsStackOffset, unsigned VarArgsNumGPR, @@ -1183,7 +1186,7 @@ assert(0 && "VAARG in ELF32 ABI not implemented yet!"); } -static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG, +SDOperand PPCTargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG, int VarArgsFrameIndex, int VarArgsStackOffset, unsigned VarArgsNumGPR, @@ -1289,7 +1292,8 @@ return FPR; } -static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, +SDOperand PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, + SelectionDAG &DAG, int &VarArgsFrameIndex, int &VarArgsStackOffset, unsigned &VarArgsNumGPR, @@ -1566,9 +1570,25 @@ DAG.getTargetLoweringInfo().getPointerTy()).Val; } +/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified +/// by "Src" to address "Dst" of size "Size". Alignment information is +/// specified by the specific parameter attribute. The copy will be passed as +/// a byval function parameter. +/// Sometimes what we are copying is the end of a larger object, the part that +/// does not fit in registers. +static SDOperand +CreateCopyOfByValArgument(SDOperand Src, SDOperand Dst, SDOperand Chain, + unsigned Flags, SelectionDAG &DAG, unsigned Size) { + unsigned Align = 1 << + ((Flags & ISD::ParamFlags::ByValAlign) >> ISD::ParamFlags::ByValAlignOffs); + SDOperand AlignNode = DAG.getConstant(Align, MVT::i32); + SDOperand SizeNode = DAG.getConstant(Size, MVT::i32); + SDOperand AlwaysInline = DAG.getConstant(1, MVT::i32); + return DAG.getMemcpy(Chain, Dst, Src, SizeNode, AlignNode, AlwaysInline); +} -static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG, - const PPCSubtarget &Subtarget) { +SDOperand PPCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG, + const PPCSubtarget &Subtarget) { SDOperand Chain = Op.getOperand(0); bool isVarArg = cast(Op.getOperand(2))->getValue() != 0; SDOperand Callee = Op.getOperand(4); @@ -1592,7 +1612,11 @@ // Add up all the space actually used. for (unsigned i = 0; i != NumOps; ++i) { + unsigned Flags = cast(Op.getOperand(5+2*i+1))->getValue(); unsigned ArgSize =MVT::getSizeInBits(Op.getOperand(5+2*i).getValueType())/8; + if (Flags & ISD::ParamFlags::ByVal) + ArgSize = (Flags & ISD::ParamFlags::ByValSize) >> + ISD::ParamFlags::ByValSizeOffs; ArgSize = std::max(ArgSize, PtrByteSize); NumBytes += ArgSize; } @@ -1678,7 +1702,30 @@ Arg = DAG.getNode(ExtOp, MVT::i64, Arg); } - + + // FIXME Elf untested, what are alignment rules? + if (Flags & ISD::ParamFlags::ByVal) { + unsigned Size = (Flags & ISD::ParamFlags::ByValSize) >> + ISD::ParamFlags::ByValSizeOffs; + if (isELF32_ABI && Expand) GPR_idx += (GPR_idx % 2); + for (unsigned j=0; j RVLocs; unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); @@ -1954,7 +2002,7 @@ return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain); } -static SDOperand LowerSTACKRESTORE(SDOperand Op, SelectionDAG &DAG, +SDOperand PPCTargetLowering::LowerSTACKRESTORE(SDOperand Op, SelectionDAG &DAG, const PPCSubtarget &Subtarget) { // When we pop the dynamic allocation we need to restore the SP link. @@ -1980,7 +2028,8 @@ return DAG.getStore(Chain, LoadLinkSP, StackPtr, NULL, 0); } -static SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG, +SDOperand PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDOperand Op, + SelectionDAG &DAG, const PPCSubtarget &Subtarget) { MachineFunction &MF = DAG.getMachineFunction(); bool IsPPC64 = Subtarget.isPPC64(); @@ -2022,7 +2071,7 @@ /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when /// possible. -static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) { +SDOperand PPCTargetLowering::LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) { // Not FP? Not a fsel. if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) || !MVT::isFloatingPoint(Op.getOperand(2).getValueType())) @@ -2102,7 +2151,7 @@ } // FIXME: Split this code up when LegalizeDAGTypes lands. -static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) { +SDOperand PPCTargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) { assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType())); SDOperand Src = Op.getOperand(0); if (Src.getValueType() == MVT::f32) @@ -2133,7 +2182,8 @@ return DAG.getLoad(Op.getValueType(), Chain, FIPtr, NULL, 0); } -static SDOperand LowerFP_ROUND_INREG(SDOperand Op, SelectionDAG &DAG) { +SDOperand PPCTargetLowering::LowerFP_ROUND_INREG(SDOperand Op, + SelectionDAG &DAG) { assert(Op.getValueType() == MVT::ppcf128); SDNode *Node = Op.Val; assert(Node->getOperand(0).getValueType() == MVT::ppcf128); @@ -2191,7 +2241,7 @@ return DAG.getNode(ISD::BUILD_PAIR, Lo.getValueType(), FPreg, FPreg); } -static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { +SDOperand PPCTargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { if (Op.getOperand(0).getValueType() == MVT::i64) { SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0)); SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits); @@ -2230,7 +2280,7 @@ return FP; } -static SDOperand LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG) { +SDOperand PPCTargetLowering::LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG) { /* The rounding mode is in bits 30:31 of FPSR, and has the following settings: @@ -2291,7 +2341,7 @@ ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal); } -static SDOperand LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG) { +SDOperand PPCTargetLowering::LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG) { assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 && Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!"); @@ -2316,7 +2366,7 @@ OutOps, 2); } -static SDOperand LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) { +SDOperand PPCTargetLowering::LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) { assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 && Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRL!"); @@ -2341,7 +2391,7 @@ OutOps, 2); } -static SDOperand LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG) { +SDOperand PPCTargetLowering::LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG) { assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 && Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!"); @@ -2533,7 +2583,8 @@ // selects to a single instruction, return Op. Otherwise, if we can codegen // this case more efficiently than a constant pool load, lower it to the // sequence of ops that should be used. -static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) { +SDOperand PPCTargetLowering::LowerBUILD_VECTOR(SDOperand Op, + SelectionDAG &DAG) { // If this is a vector of constants or undefs, get the bits. A bit in // UndefBits is set if the corresponding element of the vector is an // ISD::UNDEF value. For undefs, the corresponding VectorBits values are @@ -2775,7 +2826,8 @@ /// is a shuffle we can handle in a single instruction, return it. Otherwise, /// return the code it can be lowered into. Worst case, it can always be /// lowered into a vperm. -static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) { +SDOperand PPCTargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, + SelectionDAG &DAG) { SDOperand V1 = Op.getOperand(0); SDOperand V2 = Op.getOperand(1); SDOperand PermMask = Op.getOperand(2); @@ -2939,7 +2991,8 @@ /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom /// lower, do it, otherwise return null. -static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) { +SDOperand PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op, + SelectionDAG &DAG) { // If this is a lowered altivec predicate compare, CompareOpc is set to the // opcode number of the comparison. int CompareOpc; @@ -3005,7 +3058,8 @@ return Flags; } -static SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) { +SDOperand PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDOperand Op, + SelectionDAG &DAG) { // Create a stack slot that is 16-byte aligned. MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); int FrameIdx = FrameInfo->CreateStackObject(16, 16); @@ -3019,7 +3073,7 @@ return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0); } -static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) { +SDOperand PPCTargetLowering::LowerMUL(SDOperand Op, SelectionDAG &DAG) { if (Op.getValueType() == MVT::v4i32) { SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h?rev=47917&r1=47916&r2=47917&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h Tue Mar 4 17:17:14 2008 @@ -295,6 +295,44 @@ SDOperand LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG); SDOperand LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG); + SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG); + SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG); + SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG); + SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG); + SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG); + SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG, + int VarArgsFrameIndex, int VarArgsStackOffset, + unsigned VarArgsNumGPR, unsigned VarArgsNumFPR, + const PPCSubtarget &Subtarget); + SDOperand LowerVAARG(SDOperand Op, SelectionDAG &DAG, int VarArgsFrameIndex, + int VarArgsStackOffset, unsigned VarArgsNumGPR, + unsigned VarArgsNumFPR, const PPCSubtarget &Subtarget); + SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, + int &VarArgsFrameIndex, + int &VarArgsStackOffset, + unsigned &VarArgsNumGPR, + unsigned &VarArgsNumFPR, + const PPCSubtarget &Subtarget); + SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG, + const PPCSubtarget &Subtarget); + SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG, TargetMachine &TM); + SDOperand LowerSTACKRESTORE(SDOperand Op, SelectionDAG &DAG, + const PPCSubtarget &Subtarget); + SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG, + const PPCSubtarget &Subtarget); + SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG); + SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG); + SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG); + SDOperand LowerFP_ROUND_INREG(SDOperand Op, SelectionDAG &DAG); + SDOperand LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG); + SDOperand LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG); + SDOperand LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG); + SDOperand LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG); + SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG); + SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG); + SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG); + SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG); + SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG); }; } From isanbard at gmail.com Tue Mar 4 17:27:33 2008 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 04 Mar 2008 23:27:33 -0000 Subject: [llvm-commits] [llvm] r47918 - /llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Message-ID: <200803042327.m24NRX8U009675@zion.cs.uiuc.edu> Author: void Date: Tue Mar 4 17:27:33 2008 New Revision: 47918 URL: http://llvm.org/viewvc/llvm-project?rev=47918&view=rev Log: Removed spurious EnablePPCRS check. Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=47918&r1=47917&r2=47918&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Tue Mar 4 17:27:33 2008 @@ -431,7 +431,6 @@ .addReg(PPC::R31) .addImm(FrameSize); } else if (LP64) { - if (!EnablePPCRS) if (EnablePPCRS) // FIXME (64-bit): Use "true" version. BuildMI(MBB, II, TII.get(PPC::LD), Reg) .addImm(0) @@ -513,15 +512,15 @@ const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC; unsigned Reg = findScratchRegister(II, RS, RC, SPAdj); - // We need to store the CR in the low 4-bits of the saved value. First, issue - // an MFCR to save all of the CRBits. + // We need to store the CR in the low 4-bits of the saved value. First, issue + // an MFCR to save all of the CRBits. Add an implicit kill of the CR. if (!MI.getOperand(0).isKill()) BuildMI(MBB, II, TII.get(PPC::MFCR), Reg); else // Implicitly kill the CR register. BuildMI(MBB, II, TII.get(PPC::MFCR), Reg) .addReg(MI.getOperand(0).getReg(), false, true, true); - + // If the saved register wasn't CR0, shift the bits left so that they are in // CR0's slot. unsigned SrcReg = MI.getOperand(0).getReg(); From dpatel at apple.com Tue Mar 4 18:27:05 2008 From: dpatel at apple.com (Devang Patel) Date: Wed, 05 Mar 2008 00:27:05 -0000 Subject: [llvm-commits] [llvm] r47922 - /llvm/trunk/lib/VMCore/Verifier.cpp Message-ID: <200803050027.m250R5R1011689@zion.cs.uiuc.edu> Author: dpatel Date: Tue Mar 4 18:27:05 2008 New Revision: 47922 URL: http://llvm.org/viewvc/llvm-project?rev=47922&view=rev Log: Check struct return type first. Modified: llvm/trunk/lib/VMCore/Verifier.cpp Modified: llvm/trunk/lib/VMCore/Verifier.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Verifier.cpp?rev=47922&r1=47921&r2=47922&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Verifier.cpp (original) +++ llvm/trunk/lib/VMCore/Verifier.cpp Tue Mar 4 18:27:05 2008 @@ -581,18 +581,19 @@ Assert2(F->getReturnType() == Type::VoidTy, "Found return instr that returns void in Function of non-void " "return type!", &RI, F->getReturnType()); - else if (N == 1) - Assert2(F->getReturnType() == RI.getOperand(0)->getType(), - "Function return type does not match operand " - "type of return inst!", &RI, F->getReturnType()); else if (const StructType *STy = dyn_cast(F->getReturnType())) { for (unsigned i = 0; i < N; i++) Assert2(STy->getElementType(i) == RI.getOperand(i)->getType(), "Function return type does not match operand " "type of return inst!", &RI, F->getReturnType()); - } else + } + else if (N == 1) + Assert2(F->getReturnType() == RI.getOperand(0)->getType(), + "Function return type does not match operand " + "type of return inst!", &RI, F->getReturnType()); + else Assert1(0, "Invalid return type!", &RI); - + // Check to make sure that the return value has necessary properties for // terminators... visitTerminatorInst(RI); From dpatel at apple.com Tue Mar 4 18:36:59 2008 From: dpatel at apple.com (Devang Patel) Date: Wed, 05 Mar 2008 00:36:59 -0000 Subject: [llvm-commits] [llvm] r47924 - /llvm/trunk/lib/Transforms/Utils/UnifyFunctionExitNodes.cpp Message-ID: <200803050036.m250axON012027@zion.cs.uiuc.edu> Author: dpatel Date: Tue Mar 4 18:36:59 2008 New Revision: 47924 URL: http://llvm.org/viewvc/llvm-project?rev=47924&view=rev Log: Skip functions that return multiple values. Modified: llvm/trunk/lib/Transforms/Utils/UnifyFunctionExitNodes.cpp Modified: llvm/trunk/lib/Transforms/Utils/UnifyFunctionExitNodes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/UnifyFunctionExitNodes.cpp?rev=47924&r1=47923&r2=47924&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/UnifyFunctionExitNodes.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/UnifyFunctionExitNodes.cpp Tue Mar 4 18:36:59 2008 @@ -50,6 +50,11 @@ // Loop over all of the blocks in a function, tracking all of the blocks that // return. // + + // PHINode can not handle aggregates returned by multiple value ret + // instructions. TODO: Handle each return value independently. + if (isa(F.getReturnType())) + return false; std::vector ReturningBlocks; std::vector UnwindingBlocks; std::vector UnreachableBlocks; From gohman at apple.com Tue Mar 4 18:41:34 2008 From: gohman at apple.com (Dan Gohman) Date: Tue, 4 Mar 2008 16:41:34 -0800 Subject: [llvm-commits] Patch for review: Speeding up ScheduleDAG computations In-Reply-To: References: <200803031053.00270.dag@cray.com> Message-ID: <6050EB9C-5859-496E-A193-727D23CAF638@apple.com> On Mar 4, 2008, at 3:56 AM, Roman Levenstein wrote: > > make[5]: Entering directory > `/opt/llvm.build/projects/llvm-test/SingleSource/UnitTests/Vector/SSE' > make[5]: *** No rule to make target `Output/sse.expandfft.linked.rbc', > needed by `Output/sse.expandfft.linked.bc'. Stop. When I've seen this error, the problem has been that my base llvm build configure was run without an llvm-gcc in PATH. llvm-test apparently relies on the base llvm build to locate llvm-gcc for it. Dan From clattner at apple.com Tue Mar 4 18:43:01 2008 From: clattner at apple.com (Chris Lattner) Date: Tue, 4 Mar 2008 16:43:01 -0800 Subject: [llvm-commits] [llvm] r47924 - /llvm/trunk/lib/Transforms/Utils/UnifyFunctionExitNodes.cpp In-Reply-To: <200803050036.m250axON012027@zion.cs.uiuc.edu> References: <200803050036.m250axON012027@zion.cs.uiuc.edu> Message-ID: <048A68DE-20C1-4D02-806B-AB797E56F889@apple.com> On Mar 4, 2008, at 4:36 PM, Devang Patel wrote: > URL: http://llvm.org/viewvc/llvm-project?rev=47924&view=rev > Log: > Skip functions that return multiple values. Why not fix this to insert multiple phi nodes? Clients of this pass only expect one return after it runs: you're breaking its invariant. -Chris > > > Modified: > llvm/trunk/lib/Transforms/Utils/UnifyFunctionExitNodes.cpp > > Modified: llvm/trunk/lib/Transforms/Utils/UnifyFunctionExitNodes.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/UnifyFunctionExitNodes.cpp?rev=47924&r1=47923&r2=47924&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Transforms/Utils/UnifyFunctionExitNodes.cpp > (original) > +++ llvm/trunk/lib/Transforms/Utils/UnifyFunctionExitNodes.cpp Tue > Mar 4 18:36:59 2008 > @@ -50,6 +50,11 @@ > // Loop over all of the blocks in a function, tracking all of the > blocks that > // return. > // > + > + // PHINode can not handle aggregates returned by multiple value ret > + // instructions. TODO: Handle each return value independently. > + if (isa(F.getReturnType())) > + return false; > std::vector ReturningBlocks; > std::vector UnwindingBlocks; > std::vector UnreachableBlocks; > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From evan.cheng at apple.com Tue Mar 4 18:59:57 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 05 Mar 2008 00:59:57 -0000 Subject: [llvm-commits] [llvm] r47927 - in /llvm/trunk: include/llvm/CodeGen/ lib/CodeGen/ lib/Target/ARM/ lib/Target/X86/ Message-ID: <200803050059.m250xwGF013035@zion.cs.uiuc.edu> Author: evancheng Date: Tue Mar 4 18:59:57 2008 New Revision: 47927 URL: http://llvm.org/viewvc/llvm-project?rev=47927&view=rev Log: Refactor code. Remove duplicated functions that basically do the same thing as findRegisterUseOperandIdx, findRegisterDefOperandIndx. Fix some naming inconsistencies. Modified: llvm/trunk/include/llvm/CodeGen/LiveVariables.h llvm/trunk/include/llvm/CodeGen/MachineInstr.h llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp llvm/trunk/lib/CodeGen/LiveVariables.cpp llvm/trunk/lib/CodeGen/MachineInstr.cpp llvm/trunk/lib/CodeGen/PHIElimination.cpp llvm/trunk/lib/CodeGen/RegAllocLocal.cpp llvm/trunk/lib/CodeGen/RegisterScavenging.cpp llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp llvm/trunk/lib/CodeGen/VirtRegMap.cpp llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp Modified: llvm/trunk/include/llvm/CodeGen/LiveVariables.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveVariables.h?rev=47927&r1=47926&r2=47927&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/LiveVariables.h (original) +++ llvm/trunk/include/llvm/CodeGen/LiveVariables.h Tue Mar 4 18:59:57 2008 @@ -130,7 +130,7 @@ private: // Intermediate data structures MachineFunction *MF; - const TargetRegisterInfo *RegInfo; + const TargetRegisterInfo *TRI; // PhysRegInfo - Keep track of which instruction was the last def/use of a // physical register. This is a purely local property, because all physical @@ -175,18 +175,10 @@ virtual bool runOnMachineFunction(MachineFunction &MF); - /// KillsRegister - Return true if the specified instruction kills the - /// specified register. - bool KillsRegister(MachineInstr *MI, unsigned Reg) const; - /// RegisterDefIsDead - Return true if the specified instruction defines the /// specified register, but that definition is dead. bool RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const; - /// ModifiesRegister - Return true if the specified instruction modifies the - /// specified register. - bool ModifiesRegister(MachineInstr *MI, unsigned Reg) const; - //===--------------------------------------------------------------------===// // API to update live variable information @@ -202,7 +194,7 @@ /// not found. void addVirtualRegisterKilled(unsigned IncomingReg, MachineInstr *MI, bool AddIfNotFound = false) { - if (MI->addRegisterKilled(IncomingReg, RegInfo, AddIfNotFound)) + if (MI->addRegisterKilled(IncomingReg, TRI, AddIfNotFound)) getVarInfo(IncomingReg).Kills.push_back(MI); } @@ -239,7 +231,7 @@ /// AddIfNotFound is true, add a implicit operand if it's not found. void addVirtualRegisterDead(unsigned IncomingReg, MachineInstr *MI, bool AddIfNotFound = false) { - if (MI->addRegisterDead(IncomingReg, RegInfo, AddIfNotFound)) + if (MI->addRegisterDead(IncomingReg, TRI, AddIfNotFound)) getVarInfo(IncomingReg).Kills.push_back(MI); } Modified: llvm/trunk/include/llvm/CodeGen/MachineInstr.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstr.h?rev=47927&r1=47926&r2=47927&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineInstr.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineInstr.h Tue Mar 4 18:59:57 2008 @@ -138,14 +138,65 @@ /// bool isDebugLabel() const; + /// readsRegister - Return true if the MachineInstr reads the specified + /// register. If TargetRegisterInfo is passed, then it also checks if there + /// is a read of a super-register. + bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const { + return findRegisterUseOperandIdx(Reg, false, TRI) != -1; + } + + /// killsRegister - Return true if the MachineInstr kills the specified + /// register. If TargetRegisterInfo is passed, then it also checks if there is + /// a kill of a super-register. + bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const { + return findRegisterUseOperandIdx(Reg, true, TRI) != -1; + } + + /// modifiesRegister - Return true if the MachineInstr modifies the + /// specified register. If TargetRegisterInfo is passed, then it also checks + /// if there is a def of a super-register. + bool modifiesRegister(unsigned Reg, + const TargetRegisterInfo *TRI = NULL) const { + return findRegisterDefOperandIdx(Reg, false, TRI) != -1; + } + + /// registerDefIsDead - Returns true if the register is dead in this machine + /// instruction. If TargetRegisterInfo is passed, then it also checks + /// if there is a dead def of a super-register. + bool registerDefIsDead(unsigned Reg, + const TargetRegisterInfo *TRI = NULL) const { + return findRegisterDefOperandIdx(Reg, true, TRI) != -1; + } + /// findRegisterUseOperandIdx() - Returns the operand index that is a use of /// the specific register or -1 if it is not found. It further tightening /// the search criteria to a use that kills the register if isKill is true. - int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false) const; + int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false, + const TargetRegisterInfo *TRI = NULL) const; + + /// findRegisterUseOperand - Wrapper for findRegisterUseOperandIdx, it returns + /// a pointer to the MachineOperand rather than an index. + MachineOperand *findRegisterUseOperand(unsigned Reg,bool isKill = false, + const TargetRegisterInfo *TRI = NULL) { + int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI); + return (Idx == -1) ? NULL : &getOperand(Idx); + } - /// findRegisterDefOperand() - Returns the MachineOperand that is a def of - /// the specific register or NULL if it is not found. - MachineOperand *findRegisterDefOperand(unsigned Reg); + /// findRegisterDefOperandIdx() - Returns the operand index that is a def of + /// the specific register or -1 if it is not found. It further tightening + /// the search criteria to a def that is dead the register if isDead is true. + /// If TargetRegisterInfo is passed, then it also checks if there is a def of + /// a super-register. + int findRegisterDefOperandIdx(unsigned Reg, bool isDead = false, + const TargetRegisterInfo *TRI = NULL) const; + + /// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it returns + /// a pointer to the MachineOperand rather than an index. + MachineOperand *findRegisterDefOperand(unsigned Reg,bool isDead = false, + const TargetRegisterInfo *TRI = NULL) { + int Idx = findRegisterDefOperandIdx(Reg, isDead, TRI); + return (Idx == -1) ? NULL : &getOperand(Idx); + } /// findFirstPredOperandIdx() - Find the index of the first operand in the /// operand list that is used to represent the predicate. It returns -1 if Modified: llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h?rev=47927&r1=47926&r2=47927&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h (original) +++ llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h Tue Mar 4 18:59:57 2008 @@ -127,7 +127,7 @@ } private: - const TargetRegisterInfo *RegInfo; + const TargetRegisterInfo *TRI; const TargetInstrInfo *TII; /// CalleeSavedrRegs - A bitvector of callee saved registers for the target. Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=47927&r1=47926&r2=47927&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Tue Mar 4 18:59:57 2008 @@ -324,7 +324,7 @@ // If this redefinition is dead, we need to add a dummy unit live // range covering the def slot. - if (lv_->RegisterDefIsDead(mi, interval.reg)) + if (mi->registerDefIsDead(interval.reg, tri_)) interval.addRange(LiveRange(RedefIndex, RedefIndex+1, OldValNo)); DOUT << " RESULT: "; @@ -399,7 +399,7 @@ // If it is not used after definition, it is considered dead at // the instruction defining it. Hence its interval is: // [defSlot(def), defSlot(def)+1) - if (lv_->RegisterDefIsDead(mi, interval.reg)) { + if (mi->registerDefIsDead(interval.reg, tri_)) { DOUT << " dead"; end = getDefIndex(start) + 1; goto exit; @@ -410,11 +410,11 @@ // [defSlot(def), useSlot(kill)+1) while (++mi != MBB->end()) { baseIndex += InstrSlots::NUM; - if (lv_->KillsRegister(mi, interval.reg)) { + if (mi->killsRegister(interval.reg, tri_)) { DOUT << " killed"; end = getUseIndex(baseIndex) + 1; goto exit; - } else if (lv_->ModifiesRegister(mi, interval.reg)) { + } else if (mi->modifiesRegister(interval.reg, tri_)) { // Another instruction redefines the register before it is ever read. // Then the register is essentially dead at the instruction that defines // it. Hence its interval is: @@ -459,8 +459,9 @@ handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg), CopyMI); // Def of a register also defines its sub-registers. for (const unsigned* AS = tri_->getSubRegisters(reg); *AS; ++AS) - // Avoid processing some defs more than once. - if (!MI->findRegisterDefOperand(*AS)) + // If MI also modifies the sub-register explicitly, avoid processing it + // more than once. Do not pass in TRI here so it checks for exact match. + if (!MI->modifiesRegister(*AS)) handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(*AS), 0); } } @@ -477,11 +478,11 @@ unsigned start = baseIndex; unsigned end = start; while (mi != MBB->end()) { - if (lv_->KillsRegister(mi, interval.reg)) { + if (mi->killsRegister(interval.reg, tri_)) { DOUT << " killed"; end = getUseIndex(baseIndex) + 1; goto exit; - } else if (lv_->ModifiesRegister(mi, interval.reg)) { + } else if (mi->modifiesRegister(interval.reg, tri_)) { // Another instruction redefines the register before it is ever read. // Then the register is essentially dead at the instruction that defines // it. Hence its interval is: @@ -842,9 +843,9 @@ if (!vrm.isReMaterialized(Reg)) continue; MachineInstr *ReMatMI = vrm.getReMaterializedMI(Reg); - int OpIdx = ReMatMI->findRegisterUseOperandIdx(li.reg); - if (OpIdx != -1) - ReMatMI->getOperand(OpIdx).setReg(NewVReg); + MachineOperand *UseMO = ReMatMI->findRegisterUseOperand(li.reg); + if (UseMO) + UseMO->setReg(NewVReg); } } @@ -1605,7 +1606,7 @@ LiveRange *LR = &LI->ranges[LI->ranges.size()-1]; unsigned LastUseIdx = getBaseIndex(LR->end); MachineInstr *LastUse = getInstructionFromIndex(LastUseIdx); - int UseIdx = LastUse->findRegisterUseOperandIdx(LI->reg); + int UseIdx = LastUse->findRegisterUseOperandIdx(LI->reg, false); assert(UseIdx != -1); if (LastUse->getOperand(UseIdx).isImplicit() || LastUse->getDesc().getOperandConstraint(UseIdx,TOI::TIED_TO) == -1){ Modified: llvm/trunk/lib/CodeGen/LiveVariables.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveVariables.cpp?rev=47927&r1=47926&r2=47927&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveVariables.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveVariables.cpp Tue Mar 4 18:59:57 2008 @@ -76,51 +76,6 @@ return VI; } -/// KillsRegister - Returns true if the machine instruction kills the specified -/// register. -bool LiveVariables::KillsRegister(MachineInstr *MI, unsigned Reg) const { - for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { - const MachineOperand &MO = MI->getOperand(i); - if (MO.isRegister() && MO.isKill()) { - unsigned MOReg = MO.getReg(); - if (MOReg == Reg || - (TargetRegisterInfo::isPhysicalRegister(MOReg) && - TargetRegisterInfo::isPhysicalRegister(Reg) && - RegInfo->isSubRegister(MOReg, Reg))) - return true; - } - } - return false; -} - -/// RegisterDefIsDead - Returns true if the register is dead in this machine -/// instruction. -bool LiveVariables::RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const { - for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { - const MachineOperand &MO = MI->getOperand(i); - if (MO.isRegister() && MO.isDead()) { - unsigned MOReg = MO.getReg(); - if ((MOReg == Reg) || - (TargetRegisterInfo::isPhysicalRegister(MOReg) && - TargetRegisterInfo::isPhysicalRegister(Reg) && - RegInfo->isSubRegister(MOReg, Reg))) - return true; - } - } - return false; -} - -/// ModifiesRegister - Returns true if the machine instruction modifies the -/// register. -bool LiveVariables::ModifiesRegister(MachineInstr *MI, unsigned Reg) const { - for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { - const MachineOperand &MO = MI->getOperand(i); - if (MO.isRegister() && MO.isDef() && MO.getReg() == Reg) - return true; - } - return false; -} - void LiveVariables::MarkVirtRegAliveInBlock(VarInfo& VRInfo, MachineBasicBlock *DefBlock, MachineBasicBlock *MBB, @@ -232,7 +187,7 @@ !PhysRegUsed[Reg]) { MachineInstr *Def = PhysRegInfo[Reg]; - if (!Def->findRegisterDefOperand(Reg)) + if (!Def->modifiesRegister(Reg)) Def->addOperand(MachineOperand::CreateReg(Reg, true /*IsDef*/, true /*IsImp*/)); @@ -244,14 +199,14 @@ PhysRegUsed[Reg] = true; // Now reset the use information for the sub-registers. - for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg); + for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); unsigned SubReg = *SubRegs; ++SubRegs) { PhysRegPartUse[SubReg] = NULL; PhysRegInfo[SubReg] = MI; PhysRegUsed[SubReg] = true; } - for (const unsigned *SuperRegs = RegInfo->getSuperRegisters(Reg); + for (const unsigned *SuperRegs = TRI->getSuperRegisters(Reg); unsigned SuperReg = *SuperRegs; ++SuperRegs) { // Remember the partial use of this super-register if it was previously // defined. @@ -261,7 +216,7 @@ // No need to go up more levels. A def of a register also sets its sub- // registers. So if PhysRegInfo[SuperReg] is NULL, it means SuperReg's // super-registers are not previously defined. - for (const unsigned *SSRegs = RegInfo->getSuperRegisters(SuperReg); + for (const unsigned *SSRegs = TRI->getSuperRegisters(SuperReg); unsigned SSReg = *SSRegs; ++SSRegs) if (PhysRegInfo[SSReg] != NULL) { HasPrevDef = true; @@ -281,11 +236,11 @@ void LiveVariables::addRegisterKills(unsigned Reg, MachineInstr *MI, SmallSet &SubKills) { if (SubKills.count(Reg) == 0) { - MI->addRegisterKilled(Reg, RegInfo, true); + MI->addRegisterKilled(Reg, TRI, true); return; } - for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg); + for (const unsigned *SubRegs = TRI->getImmediateSubRegisters(Reg); unsigned SubReg = *SubRegs; ++SubRegs) addRegisterKills(SubReg, MI, SubKills); } @@ -300,7 +255,7 @@ /// SubKills is filled with the set of sub-registers that are killed elsewhere. bool LiveVariables::HandlePhysRegKill(unsigned Reg, const MachineInstr *RefMI, SmallSet &SubKills) { - const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg); + const unsigned *SubRegs = TRI->getImmediateSubRegisters(Reg); for (; unsigned SubReg = *SubRegs; ++SubRegs) { const MachineInstr *LastRef = PhysRegInfo[SubReg]; @@ -330,12 +285,12 @@ if (HandlePhysRegKill(Reg, RefMI, SubKills)) { // This machine instruction kills this register. - RefMI->addRegisterKilled(Reg, RegInfo, true); + RefMI->addRegisterKilled(Reg, TRI, true); return true; } // Some sub-registers are killed by another machine instruction. - for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg); + for (const unsigned *SubRegs = TRI->getImmediateSubRegisters(Reg); unsigned SubReg = *SubRegs; ++SubRegs) addRegisterKills(SubReg, RefMI, SubKills); @@ -348,38 +303,38 @@ if (PhysRegUsed[Reg]) { if (!HandlePhysRegKill(Reg, LastRef)) { if (PhysRegPartUse[Reg]) - PhysRegPartUse[Reg]->addRegisterKilled(Reg, RegInfo, true); + PhysRegPartUse[Reg]->addRegisterKilled(Reg, TRI, true); } } else if (PhysRegPartUse[Reg]) { // Add implicit use / kill to last partial use. - PhysRegPartUse[Reg]->addRegisterKilled(Reg, RegInfo, true); + PhysRegPartUse[Reg]->addRegisterKilled(Reg, TRI, true); } else if (LastRef != MI) { // Defined, but not used. However, watch out for cases where a super-reg // is also defined on the same MI. - LastRef->addRegisterDead(Reg, RegInfo); + LastRef->addRegisterDead(Reg, TRI); } } - for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg); + for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); unsigned SubReg = *SubRegs; ++SubRegs) { if (MachineInstr *LastRef = PhysRegInfo[SubReg]) { if (PhysRegUsed[SubReg]) { if (!HandlePhysRegKill(SubReg, LastRef)) { if (PhysRegPartUse[SubReg]) - PhysRegPartUse[SubReg]->addRegisterKilled(SubReg, RegInfo, true); + PhysRegPartUse[SubReg]->addRegisterKilled(SubReg, TRI, true); } } else if (PhysRegPartUse[SubReg]) { // Add implicit use / kill to last use of a sub-register. - PhysRegPartUse[SubReg]->addRegisterKilled(SubReg, RegInfo, true); + PhysRegPartUse[SubReg]->addRegisterKilled(SubReg, TRI, true); } else if (LastRef != MI) { // This must be a def of the subreg on the same MI. - LastRef->addRegisterDead(SubReg, RegInfo); + LastRef->addRegisterDead(SubReg, TRI); } } } if (MI) { - for (const unsigned *SuperRegs = RegInfo->getSuperRegisters(Reg); + for (const unsigned *SuperRegs = TRI->getSuperRegisters(Reg); unsigned SuperReg = *SuperRegs; ++SuperRegs) { if (PhysRegInfo[SuperReg] && PhysRegInfo[SuperReg] != MI) { // The larger register is previously defined. Now a smaller part is @@ -404,7 +359,7 @@ PhysRegPartDef[Reg].clear(); PhysRegPartUse[Reg] = NULL; - for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg); + for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); unsigned SubReg = *SubRegs; ++SubRegs) { PhysRegInfo[SubReg] = MI; PhysRegUsed[SubReg] = false; @@ -416,13 +371,12 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &mf) { MF = &mf; - RegInfo = MF->getTarget().getRegisterInfo(); + TRI = MF->getTarget().getRegisterInfo(); MachineRegisterInfo& MRI = mf.getRegInfo(); - assert(RegInfo && "Target doesn't have register information?"); - ReservedRegisters = RegInfo->getReservedRegs(mf); + ReservedRegisters = TRI->getReservedRegs(mf); - unsigned NumRegs = RegInfo->getNumRegs(); + unsigned NumRegs = TRI->getNumRegs(); PhysRegInfo = new MachineInstr*[NumRegs]; PhysRegUsed = new bool[NumRegs]; PhysRegPartUse = new MachineInstr*[NumRegs]; @@ -533,7 +487,7 @@ HandlePhysRegUse(*I, Ret); // Add live-out registers as implicit uses. - if (Ret->findRegisterUseOperandIdx(*I) == -1) + if (!Ret->readsRegister(*I)) Ret->addOperand(MachineOperand::CreateReg(*I, false, true)); } } @@ -562,12 +516,12 @@ VirtRegInfo[i] .Kills[j]->addRegisterDead(i + TargetRegisterInfo::FirstVirtualRegister, - RegInfo); + TRI); else VirtRegInfo[i] .Kills[j]->addRegisterKilled(i + TargetRegisterInfo::FirstVirtualRegister, - RegInfo); + TRI); // Check to make sure there are no unreachable blocks in the MC CFG for the // function. If so, it is due to a bug in the instruction selector or some Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=47927&r1=47926&r2=47927&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Tue Mar 4 18:59:57 2008 @@ -532,25 +532,45 @@ /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of /// the specific register or -1 if it is not found. It further tightening /// the search criteria to a use that kills the register if isKill is true. -int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill) const { +int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill, + const TargetRegisterInfo *TRI) const { for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { const MachineOperand &MO = getOperand(i); - if (MO.isRegister() && MO.isUse() && MO.getReg() == Reg) + if (!MO.isRegister() || !MO.isUse()) + continue; + unsigned MOReg = MO.getReg(); + if (!MOReg) + continue; + if (MOReg == Reg || + (TRI && + TargetRegisterInfo::isPhysicalRegister(MOReg) && + TargetRegisterInfo::isPhysicalRegister(Reg) && + TRI->isSubRegister(MOReg, Reg))) if (!isKill || MO.isKill()) return i; } return -1; } -/// findRegisterDefOperand() - Returns the MachineOperand that is a def of -/// the specific register or NULL if it is not found. -MachineOperand *MachineInstr::findRegisterDefOperand(unsigned Reg) { +/// findRegisterDefOperandIdx() - Returns the operand index that is a def of +/// the specific register or -1 if it is not found. It further tightening + /// the search criteria to a def that is dead the register if isDead is true. +int MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, + const TargetRegisterInfo *TRI) const { for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { - MachineOperand &MO = getOperand(i); - if (MO.isRegister() && MO.isDef() && MO.getReg() == Reg) - return &MO; + const MachineOperand &MO = getOperand(i); + if (!MO.isRegister() || !MO.isDef()) + continue; + unsigned MOReg = MO.getReg(); + if (MOReg == Reg || + (TRI && + TargetRegisterInfo::isPhysicalRegister(MOReg) && + TargetRegisterInfo::isPhysicalRegister(Reg) && + TRI->isSubRegister(MOReg, Reg))) + if (!isDead || MO.isDead()) + return i; } - return NULL; + return -1; } /// findFirstPredOperandIdx() - Find the index of the first operand in the Modified: llvm/trunk/lib/CodeGen/PHIElimination.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PHIElimination.cpp?rev=47927&r1=47926&r2=47927&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PHIElimination.cpp (original) +++ llvm/trunk/lib/CodeGen/PHIElimination.cpp Tue Mar 4 18:59:57 2008 @@ -161,7 +161,7 @@ LV->removeVirtualRegistersKilled(MPhi); // If the result is dead, update LV. - if (LV->RegisterDefIsDead(MPhi, DestReg)) { + if (MPhi->registerDefIsDead(DestReg)) { LV->addVirtualRegisterDead(DestReg, PHICopy); LV->removeVirtualRegistersDead(MPhi); } Modified: llvm/trunk/lib/CodeGen/RegAllocLocal.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocLocal.cpp?rev=47927&r1=47926&r2=47927&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocLocal.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocLocal.cpp Tue Mar 4 18:59:57 2008 @@ -306,8 +306,7 @@ // If the instruction reads the register that's spilled, (e.g. this can // happen if it is a move to a physical register), then the spill // instruction is not a kill. - bool isKill = !(I != MBB.end() && - I->findRegisterUseOperandIdx(PhysReg) != -1); + bool isKill = !(I != MBB.end() && I->readsRegister(PhysReg)); TII->storeRegToStackSlot(MBB, I, PhysReg, isKill, FrameIndex, RC); ++NumStores; // Update statistics } Modified: llvm/trunk/lib/CodeGen/RegisterScavenging.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterScavenging.cpp?rev=47927&r1=47926&r2=47927&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegisterScavenging.cpp (original) +++ llvm/trunk/lib/CodeGen/RegisterScavenging.cpp Tue Mar 4 18:59:57 2008 @@ -29,7 +29,7 @@ void RegScavenger::setUsed(unsigned Reg) { RegsAvailable.reset(Reg); - for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg); + for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); unsigned SubReg = *SubRegs; ++SubRegs) RegsAvailable.reset(SubReg); } @@ -38,7 +38,7 @@ void RegScavenger::setUnused(unsigned Reg) { RegsAvailable.set(Reg); - for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg); + for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); unsigned SubReg = *SubRegs; ++SubRegs) RegsAvailable.set(SubReg); } @@ -47,21 +47,21 @@ const MachineFunction &MF = *mbb->getParent(); const TargetMachine &TM = MF.getTarget(); TII = TM.getInstrInfo(); - RegInfo = TM.getRegisterInfo(); + TRI = TM.getRegisterInfo(); - assert((NumPhysRegs == 0 || NumPhysRegs == RegInfo->getNumRegs()) && + assert((NumPhysRegs == 0 || NumPhysRegs == TRI->getNumRegs()) && "Target changed?"); if (!MBB) { - NumPhysRegs = RegInfo->getNumRegs(); + NumPhysRegs = TRI->getNumRegs(); RegsAvailable.resize(NumPhysRegs); // Create reserved registers bitvector. - ReservedRegs = RegInfo->getReservedRegs(MF); + ReservedRegs = TRI->getReservedRegs(MF); // Create callee-saved registers bitvector. CalleeSavedRegs.resize(NumPhysRegs); - const unsigned *CSRegs = RegInfo->getCalleeSavedRegs(); + const unsigned *CSRegs = TRI->getCalleeSavedRegs(); if (CSRegs != NULL) for (unsigned i = 0; CSRegs[i]; ++i) CalleeSavedRegs.set(CSRegs[i]); @@ -93,7 +93,7 @@ TII->loadRegFromStackSlot(*MBB, MBBI, ScavengedReg, ScavengingFrameIndex, ScavengedRC); MachineBasicBlock::iterator II = prior(MBBI); - RegInfo->eliminateFrameIndex(II, 0, this); + TRI->eliminateFrameIndex(II, 0, this); setUsed(ScavengedReg); ScavengedReg = 0; ScavengedRC = NULL; @@ -138,7 +138,7 @@ if (MO.isKill() && !isReserved(Reg)) { ChangedRegs.set(Reg); - for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg); + for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); unsigned SubReg = *SubRegs; ++SubRegs) ChangedRegs.set(SubReg); } @@ -210,7 +210,7 @@ ChangedRegs.set(Reg); // Set the sub-registers as "used". - for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg); + for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); unsigned SubReg = *SubRegs; ++SubRegs) ChangedRegs.set(SubReg); } @@ -267,12 +267,13 @@ /// calcDistanceToUse - Calculate the distance to the first use of the /// specified register. static unsigned calcDistanceToUse(MachineBasicBlock *MBB, - MachineBasicBlock::iterator I, unsigned Reg) { + MachineBasicBlock::iterator I, unsigned Reg, + const TargetRegisterInfo *TRI) { unsigned Dist = 0; I = next(I); while (I != MBB->end()) { Dist++; - if (I->findRegisterUseOperandIdx(Reg) != -1) + if (I->readsRegister(Reg, TRI)) return Dist; I = next(I); } @@ -302,7 +303,7 @@ unsigned MaxDist = 0; int Reg = Candidates.find_first(); while (Reg != -1) { - unsigned Dist = calcDistanceToUse(MBB, I, Reg); + unsigned Dist = calcDistanceToUse(MBB, I, Reg, TRI); if (Dist >= MaxDist) { MaxDist = Dist; SReg = Reg; @@ -315,12 +316,12 @@ TII->loadRegFromStackSlot(*MBB, I, ScavengedReg, ScavengingFrameIndex, ScavengedRC); MachineBasicBlock::iterator II = prior(I); - RegInfo->eliminateFrameIndex(II, SPAdj, this); + TRI->eliminateFrameIndex(II, SPAdj, this); } TII->storeRegToStackSlot(*MBB, I, SReg, true, ScavengingFrameIndex, RC); MachineBasicBlock::iterator II = prior(I); - RegInfo->eliminateFrameIndex(II, SPAdj, this); + TRI->eliminateFrameIndex(II, SPAdj, this); ScavengedReg = SReg; ScavengedRC = RC; Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=47927&r1=47926&r2=47927&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original) +++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Tue Mar 4 18:59:57 2008 @@ -307,7 +307,7 @@ MBB->insert(DefMI, NewMI); MBB->erase(DefMI); } - unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg); + unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false); NewMI->getOperand(OpIdx).setIsKill(); // Update uses of IntA of the specific Val# with IntB. @@ -588,7 +588,7 @@ // Check if it is necessary to propagate "isDead" property before intervals // are joined. - MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg); + MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg, false); bool isDead = mopd->isDead(); bool isShorten = false; unsigned SrcStart = 0, RemoveStart = 0; @@ -617,12 +617,9 @@ RemoveEnd = SrcEnd; } else { MachineInstr *SrcMI = li_->getInstructionFromIndex(SrcStart); - if (SrcMI) { - MachineOperand *mops = findDefOperand(SrcMI, SrcReg); - if (mops) - // A dead def should have a single cycle interval. - ++RemoveStart; - } + if (SrcMI && SrcMI->modifiesRegister(SrcReg, tri_)) + // A dead def should have a single cycle interval. + ++RemoveStart; } } } @@ -672,9 +669,9 @@ } else { MachineInstr *SrcMI = li_->getInstructionFromIndex(SrcStart); if (SrcMI) { - MachineOperand *mops = findDefOperand(SrcMI, SrcReg); - if (mops) - mops->setIsDead(); + int DeadIdx = SrcMI->findRegisterDefOperandIdx(SrcReg, false, tri_); + if (DeadIdx != -1) + SrcMI->getOperand(DeadIdx).setIsDead(); } } } @@ -1461,20 +1458,6 @@ } -/// findDefOperand - Returns the MachineOperand that is a def of the specific -/// register. It returns NULL if the def is not found. -/// FIXME: Move to MachineInstr. -MachineOperand *SimpleRegisterCoalescing::findDefOperand(MachineInstr *MI, - unsigned Reg) const { - for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { - MachineOperand &MO = MI->getOperand(i); - if (MO.isRegister() && MO.isDef() && - tri_->regsOverlap(MO.getReg(), Reg)) - return &MO; - } - return NULL; -} - /// RemoveUnnecessaryKills - Remove kill markers that are no longer accurate /// due to live range lengthening as the result of coalescing. void SimpleRegisterCoalescing::printRegName(unsigned reg) const { @@ -1548,7 +1531,7 @@ if (tii_->isMoveInstr(*mii, srcReg, dstReg) && srcReg == dstReg) { // remove from def list LiveInterval &RegInt = li_->getOrCreateInterval(srcReg); - MachineOperand *MO = mii->findRegisterDefOperand(dstReg); + MachineOperand *MO = mii->findRegisterDefOperand(dstReg, false); // If def of this move instruction is dead, remove its live range from // the dstination register's live interval. if (MO->isDead()) { Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h?rev=47927&r1=47926&r2=47927&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h (original) +++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h Tue Mar 4 18:59:57 2008 @@ -206,10 +206,6 @@ MachineOperand *lastRegisterUse(unsigned Start, unsigned End, unsigned Reg, unsigned &LastUseIdx) const; - /// findDefOperand - Returns the MachineOperand that is a def of the specific - /// register. It returns NULL if the def is not found. - MachineOperand *findDefOperand(MachineInstr *MI, unsigned Reg) const; - void printRegName(unsigned reg) const; }; Modified: llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp?rev=47927&r1=47926&r2=47927&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp (original) +++ llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp Tue Mar 4 18:59:57 2008 @@ -351,10 +351,10 @@ break; } // Store KillInsts if they match up with the definition - } else if (LV.KillsRegister(curr, a)) { + } else if (curr->killsRegister(a)) { if (def == MRI->getVRegDef(a)) { kill = curr; - } else if (LV.KillsRegister(curr, b)) { + } else if (curr->killsRegister(b)) { if (def == MRI->getVRegDef(b)) { kill = curr; } @@ -373,7 +373,7 @@ break; } // Save KillInsts of First - } else if (LV.KillsRegister(curr, a)) { + } else if (curr->killsRegister(a)) { kill = curr; } // Symmetric with the above @@ -386,7 +386,7 @@ interference = false; break; } - } else if (LV.KillsRegister(curr, b)) { + } else if (curr->killsRegister(b)) { kill = curr; } } Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=47927&r1=47926&r2=47927&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp (original) +++ llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Tue Mar 4 18:59:57 2008 @@ -139,7 +139,7 @@ // rearrange the code to make it so. Making it the killing user will // allow us to coalesce A and B together, eliminating the copy we are // about to insert. - if (!LV.KillsRegister(mi, regB)) { + if (!mi->killsRegister(regB)) { // If this instruction is commutative, check to see if C dies. If // so, swap the B and C operands. This makes the live ranges of A // and C joinable. @@ -148,7 +148,7 @@ assert(mi->getOperand(3-si).isRegister() && "Not a proper commutative instruction!"); unsigned regC = mi->getOperand(3-si).getReg(); - if (LV.KillsRegister(mi, regC)) { + if (mi->killsRegister(regC)) { DOUT << "2addr: COMMUTING : " << *mi; MachineInstr *NewMI = TII.commuteInstruction(mi); if (NewMI == 0) { Modified: llvm/trunk/lib/CodeGen/VirtRegMap.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/VirtRegMap.cpp?rev=47927&r1=47926&r2=47927&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/VirtRegMap.cpp (original) +++ llvm/trunk/lib/CodeGen/VirtRegMap.cpp Tue Mar 4 18:59:57 2008 @@ -862,8 +862,7 @@ MachineInstr* DeadStore = MaybeDeadStores[FoldedSS]; if (DeadStore && (MR & VirtRegMap::isModRef)) { unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(FoldedSS); - if (!PhysReg || - DeadStore->findRegisterUseOperandIdx(PhysReg, true) == -1) + if (!PhysReg || !DeadStore->readsRegister(PhysReg)) continue; UnfoldPR = PhysReg; UnfoldedOpc = TII->getOpcodeAfterMemoryUnfold(MI.getOpcode(), @@ -908,7 +907,7 @@ assert(NewMIs.size() == 1); MachineInstr *NewMI = NewMIs.back(); NewMIs.clear(); - int Idx = NewMI->findRegisterUseOperandIdx(VirtReg); + int Idx = NewMI->findRegisterUseOperandIdx(VirtReg, false); assert(Idx != -1); SmallVector Ops; Ops.push_back(Idx); @@ -1410,7 +1409,7 @@ // the physreg. if (PhysReg && !TII->isStoreToStackSlot(&MI, SS) && // Not profitable! - DeadStore->findRegisterUseOperandIdx(PhysReg, true) != -1 && + DeadStore->killsRegister(PhysReg) && TII->unfoldMemoryOperand(MF, &MI, PhysReg, false, true, NewMIs)) { MBB.insert(MII, NewMIs[0]); NewStore = NewMIs[1]; Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp?rev=47927&r1=47926&r2=47927&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp Tue Mar 4 18:59:57 2008 @@ -294,8 +294,7 @@ for (unsigned j = 0; j < 2; ++j) { // Look at the two new MI's in reverse order. MachineInstr *NewMI = NewMIs[j]; - int NIdx = NewMI->findRegisterUseOperandIdx(Reg); - if (NIdx == -1) + if (!NewMI->readsRegister(Reg)) continue; LV.addVirtualRegisterKilled(Reg, NewMI); if (VI.removeKill(MI)) Modified: llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp?rev=47927&r1=47926&r2=47927&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp Tue Mar 4 18:59:57 2008 @@ -154,18 +154,6 @@ FunctionPass *llvm::createX86FloatingPointStackifierPass() { return new FPS(); } -/// KillsRegister - Return true if the specified instruction kills (is the last -/// use of) the specified register. Note that this routine does not check for -/// kills of subregisters. -static bool KillsRegister(MachineInstr *MI, unsigned Reg) { - for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { - MachineOperand &MO = MI->getOperand(i); - if (MO.isRegister() && MO.isKill() && MO.getReg() == Reg) - return true; - } - return false; -} - /// getFPReg - Return the X86::FPx register number for the specified operand. /// For example, this returns 3 for X86::FP3. static unsigned getFPReg(const MachineOperand &MO) { @@ -610,7 +598,7 @@ // Is this the last use of the source register? unsigned Reg = getFPReg(MI->getOperand(NumOps-1)); - bool KillsSrc = KillsRegister(MI, X86::FP0+Reg); + bool KillsSrc = MI->killsRegister(X86::FP0+Reg); // FISTP64m is strange because there isn't a non-popping versions. // If we have one _and_ we don't want to pop the operand, duplicate the value @@ -669,7 +657,7 @@ // Is this the last use of the source register? unsigned Reg = getFPReg(MI->getOperand(1)); - bool KillsSrc = KillsRegister(MI, X86::FP0+Reg); + bool KillsSrc = MI->killsRegister(X86::FP0+Reg); if (KillsSrc) { // If this is the last use of the source register, just make sure it's on @@ -778,8 +766,8 @@ unsigned Dest = getFPReg(MI->getOperand(0)); unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2)); unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1)); - bool KillsOp0 = KillsRegister(MI, X86::FP0+Op0); - bool KillsOp1 = KillsRegister(MI, X86::FP0+Op1); + bool KillsOp0 = MI->killsRegister(X86::FP0+Op0); + bool KillsOp1 = MI->killsRegister(X86::FP0+Op1); unsigned TOS = getStackEntry(0); @@ -875,8 +863,8 @@ assert(NumOperands == 2 && "Illegal FUCOM* instruction!"); unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2)); unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1)); - bool KillsOp0 = KillsRegister(MI, X86::FP0+Op0); - bool KillsOp1 = KillsRegister(MI, X86::FP0+Op1); + bool KillsOp0 = MI->killsRegister(X86::FP0+Op0); + bool KillsOp1 = MI->killsRegister(X86::FP0+Op1); // Make sure the first operand is on the top of stack, the other one can be // anywhere. @@ -901,7 +889,7 @@ unsigned Op0 = getFPReg(MI->getOperand(0)); unsigned Op1 = getFPReg(MI->getOperand(2)); - bool KillsOp1 = KillsRegister(MI, X86::FP0+Op1); + bool KillsOp1 = MI->killsRegister(X86::FP0+Op1); // The first operand *must* be on the top of the stack. moveToTop(Op0, I); @@ -958,7 +946,7 @@ unsigned SrcReg = getFPReg(MI->getOperand(1)); unsigned DestReg = getFPReg(MI->getOperand(0)); - if (KillsRegister(MI, X86::FP0+SrcReg)) { + if (MI->killsRegister(X86::FP0+SrcReg)) { // If the input operand is killed, we can just change the owner of the // incoming stack slot into the result. unsigned Slot = getSlot(SrcReg); From gohman at apple.com Tue Mar 4 19:08:18 2008 From: gohman at apple.com (Dan Gohman) Date: Wed, 05 Mar 2008 01:08:18 -0000 Subject: [llvm-commits] [llvm] r47928 - in /llvm/trunk: include/llvm/CodeGen/RuntimeLibcalls.h lib/CodeGen/SelectionDAG/LegalizeDAG.cpp lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp lib/CodeGen/SelectionDAG/TargetLowering.cpp Message-ID: <200803050108.m2518IDg013299@zion.cs.uiuc.edu> Author: djg Date: Tue Mar 4 19:08:17 2008 New Revision: 47928 URL: http://llvm.org/viewvc/llvm-project?rev=47928&view=rev Log: Codegen support for i128 SINT_TO_FP. Modified: llvm/trunk/include/llvm/CodeGen/RuntimeLibcalls.h llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Modified: llvm/trunk/include/llvm/CodeGen/RuntimeLibcalls.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/RuntimeLibcalls.h?rev=47928&r1=47927&r2=47928&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/RuntimeLibcalls.h (original) +++ llvm/trunk/include/llvm/CodeGen/RuntimeLibcalls.h Tue Mar 4 19:08:17 2008 @@ -110,6 +110,10 @@ SINTTOFP_I64_F64, SINTTOFP_I64_F80, SINTTOFP_I64_PPCF128, + SINTTOFP_I128_F32, + SINTTOFP_I128_F64, + SINTTOFP_I128_F80, + SINTTOFP_I128_PPCF128, UINTTOFP_I32_F32, UINTTOFP_I32_F64, UINTTOFP_I64_F32, Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=47928&r1=47927&r2=47928&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Mar 4 19:08:17 2008 @@ -5275,12 +5275,12 @@ /// SDOperand SelectionDAGLegalize:: ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { - assert(getTypeAction(Source.getValueType()) == Expand && + MVT::ValueType SourceVT = Source.getValueType(); + assert(getTypeAction(SourceVT) == Expand && "This is not an expansion!"); - assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!"); if (!isSigned) { - assert(Source.getValueType() == MVT::i64 && + assert(SourceVT == MVT::i64 && "This only works for 64-bit -> FP"); // The 64-bit value loaded will be incorrectly if the 'sign bit' of the // incoming integer is set. To handle this, we dynamically test to see if @@ -5291,7 +5291,7 @@ // If this is unsigned, and not supported, first perform the conversion to // signed, then adjust the result if the sign bit is set. SDOperand SignedConv = ExpandIntToFP(true, DestTy, - DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi)); + DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi)); SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi, DAG.getConstant(0, Hi.getValueType()), @@ -5301,7 +5301,8 @@ SignSet, Four, Zero); uint64_t FF = 0x5f800000ULL; if (TLI.isLittleEndian()) FF <<= 32; - static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); + static Constant *FudgeFactor = + ConstantInt::get(IntegerType::get(Source.getValueSizeInBits()), FF); SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); @@ -5323,8 +5324,8 @@ // Destination type needs to be expanded as well. The FADD now we are // constructing will be expanded into a libcall. if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) { - assert(SCVT == MVT::i32 && DestTy == MVT::f64); - SignedConv = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, + assert(MVT::getSizeInBits(SCVT) * 2 == MVT::getSizeInBits(DestTy)); + SignedConv = DAG.getNode(ISD::BUILD_PAIR, DestTy, SignedConv, SignedConv.getValue(1)); } SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv); @@ -5333,7 +5334,7 @@ } // Check to see if the target has a custom way to lower this. If so, use it. - switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) { + switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) { default: assert(0 && "This action not implemented for this operation!"); case TargetLowering::Legal: case TargetLowering::Expand: @@ -5351,14 +5352,29 @@ // the source in case it is shared (this pass of legalize must traverse it). SDOperand SrcLo, SrcHi; ExpandOp(Source, SrcLo, SrcHi); - Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi); + Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, SrcLo, SrcHi); RTLIB::Libcall LC; - if (DestTy == MVT::f32) - LC = RTLIB::SINTTOFP_I64_F32; - else { - assert(DestTy == MVT::f64 && "Unknown fp value type!"); - LC = RTLIB::SINTTOFP_I64_F64; + if (SourceVT == MVT::i64) { + if (DestTy == MVT::f32) + LC = RTLIB::SINTTOFP_I64_F32; + else { + assert(DestTy == MVT::f64 && "Unknown fp value type!"); + LC = RTLIB::SINTTOFP_I64_F64; + } + } else if (SourceVT == MVT::i128) { + if (DestTy == MVT::f32) + LC = RTLIB::SINTTOFP_I128_F32; + else if (DestTy == MVT::f64) + LC = RTLIB::SINTTOFP_I128_F64; + else if (DestTy == MVT::f80) + LC = RTLIB::SINTTOFP_I128_F80; + else { + assert(DestTy == MVT::ppcf128 && "Unknown fp value type!"); + LC = RTLIB::SINTTOFP_I128_PPCF128; + } + } else { + assert(0 && "Unknown int value type"); } assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!"); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp?rev=47928&r1=47927&r2=47928&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp Tue Mar 4 19:08:17 2008 @@ -967,10 +967,10 @@ SDOperand DAGTypeLegalizer::ExpandOperand_SINT_TO_FP(SDOperand Source, MVT::ValueType DestTy) { // We know the destination is legal, but that the input needs to be expanded. - assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!"); + MVT::ValueType SourceVT = Source.getValueType(); // Check to see if the target has a custom way to lower this. If so, use it. - switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) { + switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) { default: assert(0 && "This action not implemented for this operation!"); case TargetLowering::Legal: case TargetLowering::Expand: @@ -983,11 +983,26 @@ } RTLIB::Libcall LC; - if (DestTy == MVT::f32) - LC = RTLIB::SINTTOFP_I64_F32; - else { - assert(DestTy == MVT::f64 && "Unknown fp value type!"); - LC = RTLIB::SINTTOFP_I64_F64; + if (SourceVT == MVT::i64) { + if (DestTy == MVT::f32) + LC = RTLIB::SINTTOFP_I64_F32; + else { + assert(DestTy == MVT::f64 && "Unknown fp value type!"); + LC = RTLIB::SINTTOFP_I64_F64; + } + } else if (SourceVT == MVT::i128) { + if (DestTy == MVT::f32) + LC = RTLIB::SINTTOFP_I128_F32; + else if (DestTy == MVT::f64) + LC = RTLIB::SINTTOFP_I128_F64; + else if (DestTy == MVT::f80) + LC = RTLIB::SINTTOFP_I128_F80; + else { + assert(DestTy == MVT::ppcf128 && "Unknown fp value type!"); + LC = RTLIB::SINTTOFP_I128_PPCF128; + } + } else { + assert(0 && "Unknown int value type!"); } assert(0 && "FIXME: no libcalls yet!"); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=47928&r1=47927&r2=47928&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Tue Mar 4 19:08:17 2008 @@ -107,6 +107,10 @@ Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; + Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; + Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; + Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; + Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; From alenhar2 at cs.uiuc.edu Tue Mar 4 19:15:49 2008 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Wed, 05 Mar 2008 01:15:49 -0000 Subject: [llvm-commits] [llvm] r47929 - in /llvm/trunk/lib: CodeGen/SelectionDAG/LegalizeDAG.cpp Target/X86/X86ISelLowering.cpp Target/X86/X86ISelLowering.h Target/X86/X86InstrInfo.td Message-ID: <200803050115.m251FnMs013504@zion.cs.uiuc.edu> Author: alenhar2 Date: Tue Mar 4 19:15:49 2008 New Revision: 47929 URL: http://llvm.org/viewvc/llvm-project?rev=47929&view=rev Log: 64bit CAS on 32bit x86. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.h llvm/trunk/lib/Target/X86/X86InstrInfo.td Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=47929&r1=47928&r2=47929&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Mar 4 19:15:49 2008 @@ -6095,6 +6095,17 @@ break; } + case ISD::ATOMIC_LCS: { + SDOperand Tmp = TLI.LowerOperation(Op, DAG); + assert(Tmp.Val && "Node must be custom expanded!"); + ExpandOp(Tmp.getValue(0), Lo, Hi); + AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain. + LegalizeOp(Tmp.getValue(1))); + break; + } + + + // These operators cannot be expanded directly, emit them as calls to // library functions. case ISD::FP_TO_SINT: { Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=47929&r1=47928&r2=47929&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Mar 4 19:15:49 2008 @@ -5355,7 +5355,7 @@ return Op; } -SDOperand X86TargetLowering::LowerCAS(SDOperand Op, SelectionDAG &DAG) { +SDOperand X86TargetLowering::LowerLCS(SDOperand Op, SelectionDAG &DAG) { MVT::ValueType T = cast(Op.Val)->getVT(); unsigned Reg = 0; unsigned size = 0; @@ -5363,15 +5363,20 @@ case MVT::i8: Reg = X86::AL; size = 1; break; case MVT::i16: Reg = X86::AX; size = 2; break; case MVT::i32: Reg = X86::EAX; size = 4; break; - case MVT::i64: Reg = X86::RAX; size = 8; break; + case MVT::i64: + if (Subtarget->is64Bit()) { + Reg = X86::RAX; size = 8; + } else //Should go away when LowerType stuff lands + return SDOperand(ExpandATOMIC_LCS(Op.Val, DAG), 0); + break; }; SDOperand cpIn = DAG.getCopyToReg(Op.getOperand(0), Reg, Op.getOperand(3), SDOperand()); SDOperand Ops[] = { cpIn.getValue(0), - Op.getOperand(1), - Op.getOperand(2), - DAG.getTargetConstant(size, MVT::i8), - cpIn.getValue(1) }; + Op.getOperand(1), + Op.getOperand(2), + DAG.getTargetConstant(size, MVT::i8), + cpIn.getValue(1) }; SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); SDOperand Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, Tys, Ops, 5); SDOperand cpOut = @@ -5379,12 +5384,48 @@ return cpOut; } +SDNode* X86TargetLowering::ExpandATOMIC_LCS(SDNode* Op, SelectionDAG &DAG) { + MVT::ValueType T = cast(Op)->getVT(); + assert (T == MVT::i64 && "Only know how to expand i64 CAS"); + SDOperand cpInL, cpInH; + cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(3), + DAG.getConstant(0, MVT::i32)); + cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(3), + DAG.getConstant(1, MVT::i32)); + cpInL = DAG.getCopyToReg(Op->getOperand(0), X86::EAX, + cpInL, SDOperand()); + cpInH = DAG.getCopyToReg(cpInL.getValue(0), X86::EDX, + cpInH, cpInL.getValue(1)); + SDOperand swapInL, swapInH; + swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(2), + DAG.getConstant(0, MVT::i32)); + swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(2), + DAG.getConstant(1, MVT::i32)); + swapInL = DAG.getCopyToReg(cpInH.getValue(0), X86::EBX, + swapInL, cpInH.getValue(1)); + swapInH = DAG.getCopyToReg(swapInL.getValue(0), X86::ECX, + swapInH, swapInL.getValue(1)); + SDOperand Ops[] = { swapInH.getValue(0), + Op->getOperand(1), + swapInH.getValue(1)}; + SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); + SDOperand Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, Tys, Ops, 3); + SDOperand cpOutL = DAG.getCopyFromReg(Result.getValue(0), X86::EAX, MVT::i32, + Result.getValue(1)); + SDOperand cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), X86::EDX, MVT::i32, + cpOutL.getValue(2)); + SDOperand OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; + SDOperand ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OpsF, 2); + Tys = DAG.getVTList(MVT::i64, MVT::Other); + return DAG.getNode(ISD::MERGE_VALUES, Tys, ResultVal, cpOutH.getValue(1)).Val; +} + /// LowerOperation - Provide custom lowering hooks for some operations. /// SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { switch (Op.getOpcode()) { default: assert(0 && "Should not custom lower this!"); - case ISD::ATOMIC_LCS: return LowerCAS(Op,DAG); + case ISD::ATOMIC_LCS: return LowerLCS(Op,DAG); case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); @@ -5437,6 +5478,7 @@ default: assert(0 && "Should not custom lower this!"); case ISD::FP_TO_SINT: return ExpandFP_TO_SINT(N, DAG); case ISD::READCYCLECOUNTER: return ExpandREADCYCLECOUNTER(N, DAG); + case ISD::ATOMIC_LCS: return ExpandATOMIC_LCS(N, DAG); } } @@ -5490,6 +5532,7 @@ case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN"; case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m"; case X86ISD::LCMPXCHG_DAG: return "x86ISD::LCMPXCHG_DAG"; + case X86ISD::LCMPXCHG8_DAG: return "x86ISD::LCMPXCHG8_DAG"; } } Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=47929&r1=47928&r2=47929&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Tue Mar 4 19:15:49 2008 @@ -210,6 +210,7 @@ // compare and swap LCMPXCHG_DAG, + LCMPXCHG8_DAG, // Store FP control world into i16 memory FNSTCW16m @@ -543,9 +544,10 @@ SDOperand LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG); SDOperand LowerCTLZ(SDOperand Op, SelectionDAG &DAG); SDOperand LowerCTTZ(SDOperand Op, SelectionDAG &DAG); - SDOperand LowerCAS(SDOperand Op, SelectionDAG &DAG); + SDOperand LowerLCS(SDOperand Op, SelectionDAG &DAG); SDNode *ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG); SDNode *ExpandREADCYCLECOUNTER(SDNode *N, SelectionDAG &DAG); + SDNode *ExpandATOMIC_LCS(SDNode *N, SelectionDAG &DAG); }; } Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=47929&r1=47928&r2=47929&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Tue Mar 4 19:15:49 2008 @@ -37,6 +37,7 @@ def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>, SDTCisVT<2, i8>]>; +def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; def SDTX86Ret : SDTypeProfile<0, 1, [SDTCisVT<0, i16>]>; @@ -75,6 +76,9 @@ def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas, [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore, SDNPMayLoad]>; +def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8, + [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore, + SDNPMayLoad]>; def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret, [SDNPHasChain, SDNPOptInFlag]>; @@ -2556,6 +2560,13 @@ "lock cmpxchgl $swap,$ptr", [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK; } +let Defs = [EAX, EBX, ECX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in { +def CMPXCHG8B : I<0xC7, Pseudo, (outs), (ins i32mem:$ptr), + "cmpxchg8b $ptr", []>, TB; +def LCMPXCHG8B : I<0xC7, Pseudo, (outs), (ins i32mem:$ptr), + "lock cmpxchg8b $ptr", + [(X86cas8 addr:$ptr)]>, TB, LOCK; +} let Defs = [AX, EFLAGS], Uses = [AX] in { def CMPXCHG16 : I<0xB1, Pseudo, (outs), (ins i16mem:$ptr, GR16:$swap), From evan.cheng at apple.com Tue Mar 4 19:30:59 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 05 Mar 2008 01:30:59 -0000 Subject: [llvm-commits] [llvm] r47931 - in /llvm/trunk: include/llvm/Target/TargetLowering.h lib/CodeGen/SelectionDAG/LegalizeDAG.cpp lib/Target/X86/X86ISelLowering.h test/CodeGen/X86/shrink-fp-const1.ll Message-ID: <200803050130.m251Uxsj013921@zion.cs.uiuc.edu> Author: evancheng Date: Tue Mar 4 19:30:59 2008 New Revision: 47931 URL: http://llvm.org/viewvc/llvm-project?rev=47931&view=rev Log: Add a target lowering hook to control whether it's worthwhile to compress fp constant. For x86, if sse2 is available, it's not a good idea since cvtss2sd is slower than a movsd load and it prevents load folding. On x87, it's important to shrink fp constant since fldt is very expensive. Added: llvm/trunk/test/CodeGen/X86/shrink-fp-const1.ll Modified: llvm/trunk/include/llvm/Target/TargetLowering.h llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.h Modified: llvm/trunk/include/llvm/Target/TargetLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=47931&r1=47930&r2=47931&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetLowering.h (original) +++ llvm/trunk/include/llvm/Target/TargetLowering.h Tue Mar 4 19:30:59 2008 @@ -467,6 +467,11 @@ assert(0 && "Unsupported extended type!"); } + /// ShouldShrinkFPConstant - If true, then instruction selection should + /// seek to shrink the FP constant of the specified type to a smaller type + /// in order to save space and / or reduce runtime. + virtual bool ShouldShrinkFPConstant(MVT::ValueType VT) const { return true; } + /// hasTargetDAGCombine - If true, the target has custom DAG combine /// transformations that it can perform for the specified node. bool hasTargetDAGCombine(ISD::NodeType NT) const { Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=47931&r1=47930&r2=47931&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Mar 4 19:30:59 2008 @@ -504,7 +504,8 @@ if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) && // Only do this if the target has a native EXTLOAD instruction from // smaller type. - TLI.isLoadXLegal(ISD::EXTLOAD, SVT)) { + TLI.isLoadXLegal(ISD::EXTLOAD, SVT) && + TLI.ShouldShrinkFPConstant(VT)) { const Type *SType = MVT::getTypeForValueType(SVT); LLVMC = cast(ConstantExpr::getFPTrunc(LLVMC, SType)); VT = SVT; Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=47931&r1=47930&r2=47931&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Tue Mar 4 19:30:59 2008 @@ -434,6 +434,16 @@ virtual bool isVectorClearMaskLegal(std::vector &BVOps, MVT::ValueType EVT, SelectionDAG &DAG) const; + + /// ShouldShrinkFPConstant - If true, then instruction selection should + /// seek to shrink the FP constant of the specified type to a smaller type + /// in order to save space and / or reduce runtime. + virtual bool ShouldShrinkFPConstant(MVT::ValueType VT) const { + // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more + // expensive than a straight movsd. On the other hand, it's important to + // shrink long double fp constant since fldt is very slow. + return !X86ScalarSSEf64 || VT == MVT::f80; + } /// IsEligibleForTailCallOptimization - Check whether the call is eligible /// for tail call optimization. Target which want to do tail call Added: llvm/trunk/test/CodeGen/X86/shrink-fp-const1.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/shrink-fp-const1.ll?rev=47931&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/shrink-fp-const1.ll (added) +++ llvm/trunk/test/CodeGen/X86/shrink-fp-const1.ll Tue Mar 4 19:30:59 2008 @@ -0,0 +1,7 @@ +; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+sse2 | not grep cvtss2sd +; PR1264 + +define double @foo(double %x) { + %y = mul double %x, 5.000000e-01 + ret double %y +} From gohman at apple.com Tue Mar 4 20:07:31 2008 From: gohman at apple.com (Dan Gohman) Date: Wed, 05 Mar 2008 02:07:31 -0000 Subject: [llvm-commits] [llvm] r47932 - in /llvm/trunk/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp LegalizeTypesExpand.cpp Message-ID: <200803050207.m2527W29014857@zion.cs.uiuc.edu> Author: djg Date: Tue Mar 4 20:07:31 2008 New Revision: 47932 URL: http://llvm.org/viewvc/llvm-project?rev=47932&view=rev Log: Codegen support for i128 UINT_TO_FP. This just fixes a bug in r47928 (Int64Ty is the correct type for the constant pool entry here) and removes the asserts, now that the code is capable of handling i128. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=47932&r1=47931&r2=47932&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Mar 4 20:07:31 2008 @@ -5281,9 +5281,7 @@ "This is not an expansion!"); if (!isSigned) { - assert(SourceVT == MVT::i64 && - "This only works for 64-bit -> FP"); - // The 64-bit value loaded will be incorrectly if the 'sign bit' of the + // The integer value loaded will be incorrectly if the 'sign bit' of the // incoming integer is set. To handle this, we dynamically test to see if // it is set, and, if so, add a fudge factor. SDOperand Lo, Hi; @@ -5302,8 +5300,7 @@ SignSet, Four, Zero); uint64_t FF = 0x5f800000ULL; if (TLI.isLittleEndian()) FF <<= 32; - static Constant *FudgeFactor = - ConstantInt::get(IntegerType::get(Source.getValueSizeInBits()), FF); + static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp?rev=47932&r1=47931&r2=47932&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp Tue Mar 4 20:07:31 2008 @@ -1020,7 +1020,6 @@ // We know the destination is legal, but that the input needs to be expanded. assert(getTypeAction(Source.getValueType()) == Expand && "This is not an expansion!"); - assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!"); // If this is unsigned, and not supported, first perform the conversion to // signed, then adjust the result if the sign bit is set. From evan.cheng at apple.com Tue Mar 4 20:08:04 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 05 Mar 2008 02:08:04 -0000 Subject: [llvm-commits] [llvm] r47933 - /llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp Message-ID: <200803050208.m252841t014884@zion.cs.uiuc.edu> Author: evancheng Date: Tue Mar 4 20:08:03 2008 New Revision: 47933 URL: http://llvm.org/viewvc/llvm-project?rev=47933&view=rev Log: Rather than asserting. Dump out the MI that we are not able to encode and abort. Modified: llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp Modified: llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp?rev=47933&r1=47932&r2=47933&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp Tue Mar 4 20:08:03 2008 @@ -807,5 +807,10 @@ break; } - assert((Desc->isVariadic() || CurOp == NumOps) && "Unknown encoding!"); + if (!Desc->isVariadic() && CurOp != NumOps) { + cerr << "Cannot encode: "; + MI.dump(); + cerr << '\n'; + abort(); + } } From evan.cheng at apple.com Tue Mar 4 20:34:36 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 05 Mar 2008 02:34:36 -0000 Subject: [llvm-commits] [llvm] r47934 - /llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp Message-ID: <200803050234.m252YapO015622@zion.cs.uiuc.edu> Author: evancheng Date: Tue Mar 4 20:34:36 2008 New Revision: 47934 URL: http://llvm.org/viewvc/llvm-project?rev=47934&view=rev Log: Ignore debugging related instructions if they get this far. Modified: llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp Modified: llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp?rev=47934&r1=47933&r2=47934&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp Tue Mar 4 20:34:36 2008 @@ -610,11 +610,15 @@ switch (Opcode) { default: assert(0 && "psuedo instructions should be removed before code emission"); + break; case TargetInstrInfo::INLINEASM: assert(0 && "JIT does not support inline asm!\n"); + break; case TargetInstrInfo::LABEL: MCE.emitLabel(MI.getOperand(0).getImm()); break; + case TargetInstrInfo::DECLARE: + case X86::DWARF_LOC: case X86::IMPLICIT_DEF_GR8: case X86::IMPLICIT_DEF_GR16: case X86::IMPLICIT_DEF_GR32: From resistor at mac.com Tue Mar 4 23:41:20 2008 From: resistor at mac.com (Owen Anderson) Date: Tue, 4 Mar 2008 23:41:20 -0600 Subject: [llvm-commits] [llvm-gcc-4.2] r47879 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp In-Reply-To: <200803040325.m243PGJ2025366@zion.cs.uiuc.edu> References: <200803040325.m243PGJ2025366@zion.cs.uiuc.edu> Message-ID: <8E59AE15-AB26-460F-9132-11476ADEDEED@mac.com> Evan, I'm seeing a failure in bootstrap when compiling libgomp after this patch. I'm reverting for now. --Owen On Mar 3, 2008, at 9:25 PM, Evan Cheng wrote: > Author: evancheng > Date: Mon Mar 3 21:25:15 2008 > New Revision: 47879 > > URL: http://llvm.org/viewvc/llvm-project?rev=47879&view=rev > Log: > Unbreak x86-64 build. > > Modified: > llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp > > Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=47879&r1=47878&r2=47879&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) > +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Mon Mar 3 21:25:15 2008 > @@ -4294,7 +4294,7 @@ > C, C + 5); > return true; > } > -#if defined(TARGET_386) || defined(TARGET_ALPHA) > +#if defined(TARGET_ALPHA) > //gcc uses many names for the sync intrinsics > case BUILT_IN_VAL_COMPARE_AND_SWAP_1: > case BUILT_IN_VAL_COMPARE_AND_SWAP_2: > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From resistor at mac.com Wed Mar 5 00:08:26 2008 From: resistor at mac.com (Owen Anderson) Date: Wed, 05 Mar 2008 06:08:26 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r47936 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Message-ID: <200803050608.m2568Q7m022471@zion.cs.uiuc.edu> Author: resistor Date: Wed Mar 5 00:08:26 2008 New Revision: 47936 URL: http://llvm.org/viewvc/llvm-project?rev=47936&view=rev Log: Revert the last patch to this file. It was breaking the build on Darwin. Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=47936&r1=47935&r2=47936&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Wed Mar 5 00:08:26 2008 @@ -4294,7 +4294,7 @@ C, C + 5); return true; } -#if defined(TARGET_ALPHA) || defined(TARGET_386) +#if defined(TARGET_ALPHA) //gcc uses many names for the sync intrinsics case BUILT_IN_VAL_COMPARE_AND_SWAP_1: case BUILT_IN_VAL_COMPARE_AND_SWAP_2: From resistor at mac.com Wed Mar 5 00:08:50 2008 From: resistor at mac.com (Owen Anderson) Date: Wed, 5 Mar 2008 00:08:50 -0600 Subject: [llvm-commits] [llvm-gcc-4.2] r47879 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp In-Reply-To: <8E59AE15-AB26-460F-9132-11476ADEDEED@mac.com> References: <200803040325.m243PGJ2025366@zion.cs.uiuc.edu> <8E59AE15-AB26-460F-9132-11476ADEDEED@mac.com> Message-ID: <0B2441E0-4406-4C8F-909B-FBB5D7E2B989@mac.com> Oops, looks like I spoke too soon. It was Andrew's patch that caused the real breakage. --Owen On Mar 4, 2008, at 11:41 PM, Owen Anderson wrote: > Evan, > > I'm seeing a failure in bootstrap when compiling libgomp after this > patch. I'm reverting for now. > > --Owen > > On Mar 3, 2008, at 9:25 PM, Evan Cheng wrote: > >> Author: evancheng >> Date: Mon Mar 3 21:25:15 2008 >> New Revision: 47879 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=47879&view=rev >> Log: >> Unbreak x86-64 build. >> >> Modified: >> llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp >> >> Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=47879&r1=47878&r2=47879&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) >> +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Mon Mar 3 21:25:15 2008 >> @@ -4294,7 +4294,7 @@ >> C, C + 5); >> return true; >> } >> -#if defined(TARGET_386) || defined(TARGET_ALPHA) >> +#if defined(TARGET_ALPHA) >> //gcc uses many names for the sync intrinsics >> case BUILT_IN_VAL_COMPARE_AND_SWAP_1: >> case BUILT_IN_VAL_COMPARE_AND_SWAP_2: >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From resistor at mac.com Wed Mar 5 00:09:28 2008 From: resistor at mac.com (Owen Anderson) Date: Wed, 5 Mar 2008 00:09:28 -0600 Subject: [llvm-commits] [llvm-gcc-4.2] r47905 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp In-Reply-To: <200803042118.m24LIdd4005387@zion.cs.uiuc.edu> References: <200803042118.m24LIdd4005387@zion.cs.uiuc.edu> Message-ID: This was causing bootstrap failure on Darwin/X86, so I just reverted it. --Owen On Mar 4, 2008, at 3:18 PM, Andrew Lenharth wrote: > Author: alenhar2 > Date: Tue Mar 4 15:18:39 2008 > New Revision: 47905 > > URL: http://llvm.org/viewvc/llvm-project?rev=47905&view=rev > Log: > x86-64 supports these now, this builds fine now on linux/x86-64 > > Modified: > llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp > > Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=47905&r1=47904&r2=47905&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) > +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Tue Mar 4 15:18:39 2008 > @@ -4294,7 +4294,7 @@ > C, C + 5); > return true; > } > -#if defined(TARGET_ALPHA) > +#if defined(TARGET_ALPHA) || defined(TARGET_386) > //gcc uses many names for the sync intrinsics > case BUILT_IN_VAL_COMPARE_AND_SWAP_1: > case BUILT_IN_VAL_COMPARE_AND_SWAP_2: > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From sabre at nondot.org Wed Mar 5 00:11:21 2008 From: sabre at nondot.org (Chris Lattner) Date: Wed, 5 Mar 2008 00:11:21 -0600 Subject: [llvm-commits] CVS: llvm-www/ProjectsWithLLVM/index.html Message-ID: <200803050611.m256BLwp022598@zion.cs.uiuc.edu> Changes in directory llvm-www/ProjectsWithLLVM: index.html updated: 1.42 -> 1.43 --- Log message: linkify AIF --- Diffs of the changes: (+2 -1) index.html | 3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index: llvm-www/ProjectsWithLLVM/index.html diff -u llvm-www/ProjectsWithLLVM/index.html:1.42 llvm-www/ProjectsWithLLVM/index.html:1.43 --- llvm-www/ProjectsWithLLVM/index.html:1.42 Fri Feb 29 17:32:13 2008 +++ llvm-www/ProjectsWithLLVM/index.html Wed Mar 5 00:10:34 2008 @@ -158,7 +158,8 @@

Efficient use of the computational resources available for image processing is -a goal of the Adobe Image Foundation project. Our language, "Hydra", is used +a goal of the Adobe +Image Foundation project. Our language, "Hydra", is used to describe single- and multi-stage image processing kernels, which are then compiled and run on a target machine within a larger application. Similarly to how its namesake had many heads, our Hydra can be run on the GPU or From sabre at nondot.org Wed Mar 5 00:46:59 2008 From: sabre at nondot.org (Chris Lattner) Date: Wed, 05 Mar 2008 06:46:59 -0000 Subject: [llvm-commits] [llvm] r47937 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <200803050646.m256kx85023666@zion.cs.uiuc.edu> Author: lattner Date: Wed Mar 5 00:46:58 2008 New Revision: 47937 URL: http://llvm.org/viewvc/llvm-project?rev=47937&view=rev Log: Improve comment, pass in the original VT so that we can shrink a long double constant all the way to float, not stopping at double. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=47937&r1=47936&r2=47937&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Mar 5 00:46:58 2008 @@ -486,7 +486,9 @@ // If a FP immediate is precise when represented as a float and if the // target can do an extending load from float to double, we put it into // the constant pool as a float, even if it's is statically typed as a - // double. + // double. This shrinks FP constants and canonicalizes them for targets where + // an FP extending load is the same cost as a normal load (such as on the x87 + // fp stack or PPC FP unit). MVT::ValueType VT = CFP->getValueType(0); ConstantFP *LLVMC = ConstantFP::get(MVT::getTypeForValueType(VT), CFP->getValueAPF()); @@ -505,7 +507,7 @@ // Only do this if the target has a native EXTLOAD instruction from // smaller type. TLI.isLoadXLegal(ISD::EXTLOAD, SVT) && - TLI.ShouldShrinkFPConstant(VT)) { + TLI.ShouldShrinkFPConstant(OrigVT)) { const Type *SType = MVT::getTypeForValueType(SVT); LLVMC = cast(ConstantExpr::getFPTrunc(LLVMC, SType)); VT = SVT; From sabre at nondot.org Wed Mar 5 00:48:14 2008 From: sabre at nondot.org (Chris Lattner) Date: Wed, 05 Mar 2008 06:48:14 -0000 Subject: [llvm-commits] [llvm] r47938 - in /llvm/trunk: lib/CodeGen/SelectionDAG/SelectionDAG.cpp test/CodeGen/X86/shrink-fp-const2.ll Message-ID: <200803050648.m256mEhj023710@zion.cs.uiuc.edu> Author: lattner Date: Wed Mar 5 00:48:13 2008 New Revision: 47938 URL: http://llvm.org/viewvc/llvm-project?rev=47938&view=rev Log: Generalize FP constant shrinking optimization to apply to any vt except ppc long double. This allows us to shrink constant pool entries for x86 long double constants, which in turn allows us to use flds/fldl instead of fldt. Added: llvm/trunk/test/CodeGen/X86/shrink-fp-const2.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=47938&r1=47937&r2=47938&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Mar 5 00:48:13 2008 @@ -44,6 +44,17 @@ return Res; } +static const fltSemantics *MVTToAPFloatSemantics(MVT::ValueType VT) { + switch (VT) { + default: assert(0 && "Unknown FP format"); + case MVT::f32: return &APFloat::IEEEsingle; + case MVT::f64: return &APFloat::IEEEdouble; + case MVT::f80: return &APFloat::x87DoubleExtended; + case MVT::f128: return &APFloat::IEEEquad; + case MVT::ppcf128: return &APFloat::PPCDoubleDouble; + } +} + SelectionDAG::DAGUpdateListener::~DAGUpdateListener() {} //===----------------------------------------------------------------------===// @@ -60,28 +71,20 @@ bool ConstantFPSDNode::isValueValidForType(MVT::ValueType VT, const APFloat& Val) { + assert(MVT::isFloatingPoint(VT) && "Can only convert between FP types"); + + // Anything can be extended to ppc long double. + if (VT == MVT::ppcf128) + return true; + + // PPC long double cannot be shrunk to anything though. + if (&Val.getSemantics() == &APFloat::PPCDoubleDouble) + return false; + // convert modifies in place, so make a copy. APFloat Val2 = APFloat(Val); - switch (VT) { - default: - return false; // These can't be represented as floating point! - - // FIXME rounding mode needs to be more flexible - case MVT::f32: - return &Val2.getSemantics() == &APFloat::IEEEsingle || - Val2.convert(APFloat::IEEEsingle, APFloat::rmNearestTiesToEven) == - APFloat::opOK; - case MVT::f64: - return &Val2.getSemantics() == &APFloat::IEEEsingle || - &Val2.getSemantics() == &APFloat::IEEEdouble || - Val2.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven) == - APFloat::opOK; - // TODO: Figure out how to test if we can use a shorter type instead! - case MVT::f80: - case MVT::f128: - case MVT::ppcf128: - return true; - } + return Val2.convert(*MVTToAPFloatSemantics(VT), + APFloat::rmNearestTiesToEven) == APFloat::opOK; } //===----------------------------------------------------------------------===// @@ -1786,12 +1789,8 @@ case ISD::FP_EXTEND: // This can return overflow, underflow, or inexact; we don't care. // FIXME need to be more flexible about rounding mode. - (void) V.convert(VT==MVT::f32 ? APFloat::IEEEsingle : - VT==MVT::f64 ? APFloat::IEEEdouble : - VT==MVT::f80 ? APFloat::x87DoubleExtended : - VT==MVT::f128 ? APFloat::IEEEquad : - APFloat::Bogus, - APFloat::rmNearestTiesToEven); + (void)V.convert(*MVTToAPFloatSemantics(VT), + APFloat::rmNearestTiesToEven); return getConstantFP(V, VT); case ISD::FP_TO_SINT: case ISD::FP_TO_UINT: { Added: llvm/trunk/test/CodeGen/X86/shrink-fp-const2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/shrink-fp-const2.ll?rev=47938&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/shrink-fp-const2.ll (added) +++ llvm/trunk/test/CodeGen/X86/shrink-fp-const2.ll Wed Mar 5 00:48:13 2008 @@ -0,0 +1,7 @@ +; RUN: llvm-as < %s | llc -march=x86 | grep flds +; This should be a flds, not fldt. +define x86_fp80 @test2() nounwind { +entry: + ret x86_fp80 0xK3FFFC000000000000000 +} + From romix.llvm at googlemail.com Wed Mar 5 01:08:39 2008 From: romix.llvm at googlemail.com (Roman Levenstein) Date: Wed, 5 Mar 2008 10:08:39 +0300 Subject: [llvm-commits] Fwd: Patch for review: Speeding up ScheduleDAG computations In-Reply-To: <388F3E9D-F770-402B-8744-6D1501642885@apple.com> References: <522BCA72-6445-4857-BE7B-019B841AA9DB@apple.com> <2DFEE2ED-2D57-4310-8F6C-1B08F18D4363@apple.com> <388F3E9D-F770-402B-8744-6D1501642885@apple.com> Message-ID: Hi Dan, 2008/3/5, Dan Gohman : > > On Mar 4, 2008, at 10:37 AM, Roman Levenstein wrote: > >> > > >> I thought those were approved? We understanding std::set is probably > >> the best choice of ADT for now. Thanks! > > > > OK. I'll commit them tomorrow. > > > Great! Note that I did have one comment on the ScheduleDAGList.cpp > patch. Sure, proposed changes from your comment will be in the patch. > > But are you sure about the second one for the ScheduleDAGRRList? > > I mean this: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20080303/059078.html > > > > I just took a look at this one. Here are my comments. > > > + // This may break the ordering in the priority queue. > > PredSU->CycleBound = std::max(PredSU->CycleBound, > > I->Dep->Cycle + PredSU->Latency); > > This seems dangerous. After this is done, updateNode is called, > which attempts to remove the node from the set, but if the node has > changed > in a way that's significant to the comparison function, that remove > may not > work properly. It looks like the only way to be safe is to remove the > node > from the queue before making any modifications. Good catch. I'll see how to fix this. > > + for (unsigned i = 0, e = Nodes.size(); i != e; ++i) { > > + Queue.insert(Nodes[i]); > > > + } > > This could be simplified with > > Queue.insert(Nodes.begin(), Nodes.end()); > > > + SUnit *V = *Queue.rbegin(); > > + Queue.erase(--Queue.end(),Queue.end()); > > This could be simplified with > > Queue.erase(prior(Queue.end()); > > or even > > iterator i = prior(Queue.rbegin()); > > SUnit *V = *i; > Queue.erase(i); > > > `prior' is defined in llvm/ADT/STLExtras.h. Thanks! This makes the code cleaner. > > - unsigned LBonus = (SumOfUnscheduledPredsOfSuccs(left) == 1) ? > > 2 : 0; > > - unsigned RBonus = (SumOfUnscheduledPredsOfSuccs(right) == 1) ? > 2 : 0; > > > + unsigned LBonus = (SumOfUnscheduledPredsOfSuccs(left,1) == 1) ? > 2 : 0; > > + unsigned RBonus = (SumOfUnscheduledPredsOfSuccs(right,1) == 1) ? > 2 : 0; > > It's not clear to me what this change is doing. Well, the original > code isn't > quite clear to me either :-}. Is this a heuristic change? No, it does not change the semantic. I don't know what the original code wanted to do. I just made it more efficient ;-) SumOfUnscheduledPredsOfSuccs is called from the comparison operator used by the priority queue, which is called rather often when any operations on the queue are performed. SumOfUnscheduledPredsOfSuccs tries every time to compute the number of ALL unscheduled predecessors of successors for a given node. And there can be hundreds/thousends of them for big BBs (On some of my testcases this function was taking up to 40-50% of the compilation time!). But then it compares this number to 1, as you can see above. So I modified SumOfUnscheduledPredsOfSuccs to compute only the number of predecessors until it reaches certain limit/treshold, since it is enough for our goals. After this change, SumOfUnscheduledPredsOfSuccs virtually does not consume any time at all, profiler does not even show it, and the overall compilation time is faster. -Roman From sabre at nondot.org Wed Mar 5 01:22:40 2008 From: sabre at nondot.org (Chris Lattner) Date: Wed, 05 Mar 2008 07:22:40 -0000 Subject: [llvm-commits] [llvm] r47939 - /llvm/trunk/lib/Target/X86/README-SSE.txt Message-ID: <200803050722.m257Mem8024675@zion.cs.uiuc.edu> Author: lattner Date: Wed Mar 5 01:22:39 2008 New Revision: 47939 URL: http://llvm.org/viewvc/llvm-project?rev=47939&view=rev Log: add a note Modified: llvm/trunk/lib/Target/X86/README-SSE.txt Modified: llvm/trunk/lib/Target/X86/README-SSE.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/README-SSE.txt?rev=47939&r1=47938&r2=47939&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/README-SSE.txt (original) +++ llvm/trunk/lib/Target/X86/README-SSE.txt Wed Mar 5 01:22:39 2008 @@ -748,3 +748,33 @@ right, but we shouldn't have to custom lower anything. This is probably related to <2 x i64> ops being so bad. +//===---------------------------------------------------------------------===// + +'select' on vectors and scalars could be a whole lot better. We currently +lower them to conditional branches. On x86-64 for example, we compile this: + +double test(double a, double b, double c, double d) { return a Author: evancheng Date: Wed Mar 5 02:11:27 2008 New Revision: 47940 URL: http://llvm.org/viewvc/llvm-project?rev=47940&view=rev Log: PSLLWri etc. are two-address instructions. Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=47940&r1=47939&r2=47940&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Mar 5 02:11:27 2008 @@ -1765,7 +1765,7 @@ [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>, XS, Requires<[HasSSE2]>; -let isTwoAddress = 1 in { +let Constraints = "$src1 = $dst" in { multiclass PDI_binop_rm_int opc, string OpcodeStr, Intrinsic IntId, bit Commutable = 0> { @@ -1866,6 +1866,7 @@ defm PSRAD : PDI_binop_rm_int<0xE2, "psrad", int_x86_sse2_psra_d>; // Some immediate variants need to match a bit_convert. +let Constraints = "$src1 = $dst" in { def PSLLWri : PDIi8<0x71, MRM6r, (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2), "psllw\t{$src2, $dst|$dst, $src2}", @@ -1908,6 +1909,7 @@ "psrad\t{$src2, $dst|$dst, $src2}", [(set VR128:$dst, (int_x86_sse2_psra_d VR128:$src1, (scalar_to_vector (i32 imm:$src2))))]>; +} // PSRAQ doesn't exist in SSE[1-3]. From evan.cheng at apple.com Wed Mar 5 02:19:17 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 05 Mar 2008 08:19:17 -0000 Subject: [llvm-commits] [llvm] r47941 - /llvm/trunk/lib/Target/X86/X86InstrSSE.td Message-ID: <200803050819.m258JHBi026228@zion.cs.uiuc.edu> Author: evancheng Date: Wed Mar 5 02:19:16 2008 New Revision: 47941 URL: http://llvm.org/viewvc/llvm-project?rev=47941&view=rev Log: isTwoAddress = 1 -> Constraints. Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=47941&r1=47940&r2=47941&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Mar 5 02:19:16 2008 @@ -360,7 +360,7 @@ "cvttps2pi\t{$src, $dst|$dst, $src}", [(set VR64:$dst, (int_x86_sse_cvttps2pi (load addr:$src)))]>; -let isTwoAddress = 1 in { +let Constraints = "$src1 = $dst" in { def Int_CVTPI2PSrr : PSI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR64:$src2), "cvtpi2ps\t{$src2, $dst|$dst, $src2}", @@ -383,7 +383,7 @@ [(set GR32:$dst, (int_x86_sse_cvttss2si(load addr:$src)))]>; -let isTwoAddress = 1 in { +let Constraints = "$src1 = $dst" in { def Int_CVTSI2SSrr : SSI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, GR32:$src2), "cvtsi2ss\t{$src2, $dst|$dst, $src2}", @@ -397,7 +397,7 @@ } // Comparison instructions -let isTwoAddress = 1 in { +let Constraints = "$src1 = $dst" in { let neverHasSideEffects = 1 in def CMPSSrr : SSIi8<0xC2, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src, SSECC:$cc), @@ -419,7 +419,7 @@ } // Defs = [EFLAGS] // Aliases to match intrinsics which expect XMM operand(s). -let isTwoAddress = 1 in { +let Constraints = "$src1 = $dst" in { def Int_CMPSSrr : SSIi8<0xC2, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc), "cmp${cc}ss\t{$src, $dst|$dst, $src}", @@ -479,7 +479,7 @@ [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>; // Alias bitwise logical operations using SSE logical ops on packed FP values. -let isTwoAddress = 1 in { +let Constraints = "$src1 = $dst" in { let isCommutable = 1 in { def FsANDPSrr : PSI<0x54, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2), "andps\t{$src2, $dst|$dst, $src2}", @@ -526,7 +526,7 @@ /// These three forms can each be reg+reg or reg+mem, so there are a total of /// six "instructions". /// -let isTwoAddress = 1 in { +let Constraints = "$src1 = $dst" in { multiclass basic_sse1_fp_binop_rm opc, string OpcodeStr, SDNode OpNode, Intrinsic F32Int, bit Commutable = 0> { @@ -584,7 +584,7 @@ /// /// This provides a total of eight "instructions". /// -let isTwoAddress = 1 in { +let Constraints = "$src1 = $dst" in { multiclass sse1_fp_binop_rm opc, string OpcodeStr, SDNode OpNode, Intrinsic F32Int, @@ -683,7 +683,7 @@ "movups\t{$src, $dst|$dst, $src}", [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>; -let isTwoAddress = 1 in { +let Constraints = "$src1 = $dst" in { let AddedComplexity = 20 in { def MOVLPSrm : PSI<0x12, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2), @@ -700,7 +700,7 @@ (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))), MOVHP_shuffle_mask)))]>; } // AddedComplexity -} // isTwoAddress +} // Constraints = "$src1 = $dst" def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src), "movlps\t{$src, $dst|$dst, $src}", @@ -717,7 +717,7 @@ UNPCKH_shuffle_mask)), (iPTR 0))), addr:$dst)]>; -let isTwoAddress = 1 in { +let Constraints = "$src1 = $dst" in { let AddedComplexity = 15 in { def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), "movlhps\t{$src2, $dst|$dst, $src2}", @@ -731,7 +731,7 @@ (v4f32 (vector_shuffle VR128:$src1, VR128:$src2, MOVHLPS_shuffle_mask)))]>; } // AddedComplexity -} // isTwoAddress +} // Constraints = "$src1 = $dst" @@ -815,7 +815,7 @@ int_x86_sse_rcp_ss, int_x86_sse_rcp_ps>; // Logical -let isTwoAddress = 1 in { +let Constraints = "$src1 = $dst" in { let isCommutable = 1 in { def ANDPSrr : PSI<0x54, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), @@ -865,7 +865,7 @@ (memopv2i64 addr:$src2))))]>; } -let isTwoAddress = 1 in { +let Constraints = "$src1 = $dst" in { def CMPPSrri : PSIi8<0xC2, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc), "cmp${cc}ps\t{$src, $dst|$dst, $src}", @@ -879,7 +879,7 @@ } // Shuffle and unpack instructions -let isTwoAddress = 1 in { +let Constraints = "$src1 = $dst" in { let isConvertibleToThreeAddress = 1 in // Convert to pshufd def SHUFPSrri : PSIi8<0xC6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, @@ -929,7 +929,7 @@ VR128:$src1, (memopv4f32 addr:$src2), UNPCKL_shuffle_mask)))]>; } // AddedComplexity -} // isTwoAddress +} // Constraints = "$src1 = $dst" // Mask creation def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src), @@ -993,7 +993,7 @@ // Move to lower bits of a VR128, leaving upper bits alone. // Three operand (but two address) aliases. -let isTwoAddress = 1 in { +let Constraints = "$src1 = $dst" in { let neverHasSideEffects = 1 in def MOVLSS2PSrr : SSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, FR32:$src2), @@ -1107,7 +1107,7 @@ (load addr:$src)))]>; // Comparison instructions -let isTwoAddress = 1, neverHasSideEffects = 1 in { +let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in { def CMPSDrr : SDIi8<0xC2, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src, SSECC:$cc), "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>; @@ -1128,7 +1128,7 @@ } // Aliases to match intrinsics which expect XMM operand(s). -let isTwoAddress = 1 in { +let Constraints = "$src1 = $dst" in { def Int_CMPSDrr : SDIi8<0xC2, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc), "cmp${cc}sd\t{$src, $dst|$dst, $src}", @@ -1184,7 +1184,7 @@ [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>; // Alias bitwise logical operations using SSE logical ops on packed FP values. -let isTwoAddress = 1 in { +let Constraints = "$src1 = $dst" in { let isCommutable = 1 in { def FsANDPDrr : PDI<0x54, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2), "andpd\t{$src2, $dst|$dst, $src2}", @@ -1231,7 +1231,7 @@ /// These three forms can each be reg+reg or reg+mem, so there are a total of /// six "instructions". /// -let isTwoAddress = 1 in { +let Constraints = "$src1 = $dst" in { multiclass basic_sse2_fp_binop_rm opc, string OpcodeStr, SDNode OpNode, Intrinsic F64Int, bit Commutable = 0> { @@ -1289,7 +1289,7 @@ /// /// This provides a total of eight "instructions". /// -let isTwoAddress = 1 in { +let Constraints = "$src1 = $dst" in { multiclass sse2_fp_binop_rm opc, string OpcodeStr, SDNode OpNode, Intrinsic F64Int, @@ -1387,7 +1387,7 @@ "movupd\t{$src, $dst|$dst, $src}", [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>; -let isTwoAddress = 1 in { +let Constraints = "$src1 = $dst" in { let AddedComplexity = 20 in { def MOVLPDrm : PDI<0x12, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2), @@ -1404,7 +1404,7 @@ (scalar_to_vector (loadf64 addr:$src2)), MOVHP_shuffle_mask)))]>; } // AddedComplexity -} // isTwoAddress +} // Constraints = "$src1 = $dst" def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src), "movlpd\t{$src, $dst|$dst, $src}", @@ -1500,7 +1500,7 @@ // Match intrinsics which expect XMM operand(s). // Aliases for intrinsics -let isTwoAddress = 1 in { +let Constraints = "$src1 = $dst" in { def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, GR32:$src2), "cvtsi2sd\t{$src2, $dst|$dst, $src2}", @@ -1610,7 +1610,7 @@ // There is no f64 version of the reciprocal approximation instructions. // Logical -let isTwoAddress = 1 in { +let Constraints = "$src1 = $dst" in { let isCommutable = 1 in { def ANDPDrr : PDI<0x54, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), @@ -1664,7 +1664,7 @@ (memopv2i64 addr:$src2)))]>; } -let isTwoAddress = 1 in { +let Constraints = "$src1 = $dst" in { def CMPPDrri : PDIi8<0xC2, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc), "cmp${cc}pd\t{$src, $dst|$dst, $src}", @@ -1678,7 +1678,7 @@ } // Shuffle and unpack instructions -let isTwoAddress = 1 in { +let Constraints = "$src1 = $dst" in { def SHUFPDrri : PDIi8<0xC6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i8imm:$src3), "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}", @@ -1725,7 +1725,7 @@ VR128:$src1, (memopv2f64 addr:$src2), UNPCKL_shuffle_mask)))]>; } // AddedComplexity -} // isTwoAddress +} // Constraints = "$src1 = $dst" //===----------------------------------------------------------------------===// @@ -1811,7 +1811,7 @@ [(set VR128:$dst, (OpNode VR128:$src1,(memopv2i64 addr:$src2)))]>; } -} // isTwoAddress +} // Constraints = "$src1 = $dst" // 128-bit Integer Arithmetic @@ -1914,7 +1914,7 @@ // PSRAQ doesn't exist in SSE[1-3]. // 128-bit logical shifts. -let isTwoAddress = 1, neverHasSideEffects = 1 in { +let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in { def PSLLDQri : PDIi8<0x73, MRM7r, (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2), "pslldq\t{$src2, $dst|$dst, $src2}", []>; @@ -1938,7 +1938,7 @@ defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or , 1>; defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>; -let isTwoAddress = 1 in { +let Constraints = "$src1 = $dst" in { def PANDNrr : PDI<0xDF, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), "pandn\t{$src2, $dst|$dst, $src2}", @@ -2015,7 +2015,7 @@ XD, Requires<[HasSSE2]>; -let isTwoAddress = 1 in { +let Constraints = "$src1 = $dst" in { def PUNPCKLBWrr : PDI<0x60, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), "punpcklbw\t{$src2, $dst|$dst, $src2}", @@ -2129,7 +2129,7 @@ "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}", [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1), imm:$src2))]>; -let isTwoAddress = 1 in { +let Constraints = "$src1 = $dst" in { def PINSRWrri : PDIi8<0xC4, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, GR32:$src2, i32i8imm:$src3), @@ -2263,7 +2263,7 @@ // Move to lower bits of a VR128, leaving upper bits alone. // Three operand (but two address) aliases. -let isTwoAddress = 1 in { +let Constraints = "$src1 = $dst" in { let neverHasSideEffects = 1 in def MOVLSD2PDrr : SDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, FR64:$src2), @@ -2386,7 +2386,7 @@ SSE_splat_lo_mask)))]>; // Arithmetic -let isTwoAddress = 1 in { +let Constraints = "$src1 = $dst" in { def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), "addsubps\t{$src2, $dst|$dst, $src2}", @@ -2431,7 +2431,7 @@ !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (load addr:$src2))))]>; -let isTwoAddress = 1 in { +let Constraints = "$src1 = $dst" in { def HADDPSrr : S3D_Intrr<0x7C, "haddps", int_x86_sse3_hadd_ps>; def HADDPSrm : S3D_Intrm<0x7C, "haddps", int_x86_sse3_hadd_ps>; def HADDPDrr : S3_Intrr <0x7C, "haddpd", int_x86_sse3_hadd_pd>; @@ -2567,7 +2567,7 @@ int_x86_ssse3_pabs_d_128>; /// SS3I_binop_rm_int_8 - Simple SSSE3 binary operator whose type is v*i8. -let isTwoAddress = 1 in { +let Constraints = "$src1 = $dst" in { multiclass SS3I_binop_rm_int_8 opc, string OpcodeStr, Intrinsic IntId64, Intrinsic IntId128, bit Commutable = 0> { @@ -2601,7 +2601,7 @@ } /// SS3I_binop_rm_int_16 - Simple SSSE3 binary operator whose type is v*i16. -let isTwoAddress = 1 in { +let Constraints = "$src1 = $dst" in { multiclass SS3I_binop_rm_int_16 opc, string OpcodeStr, Intrinsic IntId64, Intrinsic IntId128, bit Commutable = 0> { @@ -2635,7 +2635,7 @@ } /// SS3I_binop_rm_int_32 - Simple SSSE3 binary operator whose type is v*i32. -let isTwoAddress = 1 in { +let Constraints = "$src1 = $dst" in { multiclass SS3I_binop_rm_int_32 opc, string OpcodeStr, Intrinsic IntId64, Intrinsic IntId128, bit Commutable = 0> { @@ -2705,7 +2705,7 @@ int_x86_ssse3_psign_d, int_x86_ssse3_psign_d_128>; -let isTwoAddress = 1 in { +let Constraints = "$src1 = $dst" in { def PALIGNR64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2, i16imm:$src3), "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}", @@ -3149,7 +3149,7 @@ int_x86_sse41_phminposuw>; /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator -let isTwoAddress = 1 in { +let Constraints = "$src1 = $dst" in { multiclass SS41I_binop_rm_int opc, string OpcodeStr, Intrinsic IntId128, bit Commutable = 0> { def rr : SS48I opc, string OpcodeStr, SDNode OpNode, Intrinsic IntId128, bit Commutable = 0> { def rr : SS48I opc, string OpcodeStr, Intrinsic IntId128, bit Commutable = 0> { def rri : SS4AI opc, string OpcodeStr, Intrinsic IntId> { def rr0 : SS48I; -let isTwoAddress = 1 in { +let Constraints = "$src1 = $dst" in { multiclass SS41I_insert8 opc, string OpcodeStr> { def rr : SS4AI; -let isTwoAddress = 1 in { +let Constraints = "$src1 = $dst" in { multiclass SS41I_insert32 opc, string OpcodeStr> { def rr : SS4AI; -let isTwoAddress = 1 in { +let Constraints = "$src1 = $dst" in { multiclass SS41I_insertf32 opc, string OpcodeStr> { def rr : SS4AI Author: evancheng Date: Wed Mar 5 02:26:18 2008 New Revision: 47942 URL: http://llvm.org/viewvc/llvm-project?rev=47942&view=rev Log: Add a test for _mm_slli_epi16 and _mm_srli_epi16. Added: test-suite/trunk/SingleSource/UnitTests/Vector/SSE/sse.shift.c Added: test-suite/trunk/SingleSource/UnitTests/Vector/SSE/sse.shift.c URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/Vector/SSE/sse.shift.c?rev=47942&view=auto ============================================================================== --- test-suite/trunk/SingleSource/UnitTests/Vector/SSE/sse.shift.c (added) +++ test-suite/trunk/SingleSource/UnitTests/Vector/SSE/sse.shift.c Wed Mar 5 02:26:18 2008 @@ -0,0 +1,21 @@ +#include +#include + +typedef union { + __m128i V; + int A[4]; +} IV; + +static void printIV(IV *F) { + printf("%08x %08x %08x %08x\n", F->A[0], F->A[1], F->A[2], F->A[3]); +} + +int main() { + __m128i allones, zeroones, onezeros; + allones = _mm_cmpeq_epi32(allones, allones); + zeroones = _mm_srli_epi16(allones, 8); + printIV((IV*)&zeroones); + onezeros = _mm_slli_epi16(allones, 8); + printIV((IV*)&onezeros); + return 0; +} From evan.cheng at apple.com Wed Mar 5 02:41:28 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 5 Mar 2008 00:41:28 -0800 Subject: [llvm-commits] [llvm-gcc-4.2] r47879 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp In-Reply-To: <0B2441E0-4406-4C8F-909B-FBB5D7E2B989@mac.com> References: <200803040325.m243PGJ2025366@zion.cs.uiuc.edu> <8E59AE15-AB26-460F-9132-11476ADEDEED@mac.com> <0B2441E0-4406-4C8F-909B-FBB5D7E2B989@mac.com> Message-ID: <09AEE1B0-838F-4445-9D08-E81F9468B7FB@apple.com> Yeah, I know you want to blame me for *everything*. :-) Try again next time. Evan On Mar 4, 2008, at 10:08 PM, Owen Anderson wrote: > Oops, looks like I spoke too soon. It was Andrew's patch that caused > the real breakage. > > --Owen > > On Mar 4, 2008, at 11:41 PM, Owen Anderson wrote: > >> Evan, >> >> I'm seeing a failure in bootstrap when compiling libgomp after this >> patch. I'm reverting for now. >> >> --Owen >> >> On Mar 3, 2008, at 9:25 PM, Evan Cheng wrote: >> >>> Author: evancheng >>> Date: Mon Mar 3 21:25:15 2008 >>> New Revision: 47879 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=47879&view=rev >>> Log: >>> Unbreak x86-64 build. >>> >>> Modified: >>> llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp >>> >>> Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp >>> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=47879&r1=47878&r2=47879&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ==================================================================== >>> --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) >>> +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Mon Mar 3 21:25:15 2008 >>> @@ -4294,7 +4294,7 @@ >>> C, C + 5); >>> return true; >>> } >>> -#if defined(TARGET_386) || defined(TARGET_ALPHA) >>> +#if defined(TARGET_ALPHA) >>> //gcc uses many names for the sync intrinsics >>> case BUILT_IN_VAL_COMPARE_AND_SWAP_1: >>> case BUILT_IN_VAL_COMPARE_AND_SWAP_2: >>> >>> >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From isanbard at gmail.com Wed Mar 5 03:28:03 2008 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 05 Mar 2008 09:28:03 -0000 Subject: [llvm-commits] [llvm] r47943 - in /llvm/trunk: autoconf/configure.ac configure Message-ID: <200803050928.m259S4qe003634@zion.cs.uiuc.edu> Author: void Date: Wed Mar 5 03:28:02 2008 New Revision: 47943 URL: http://llvm.org/viewvc/llvm-project?rev=47943&view=rev Log: Use AC_PATH_PROG correctly: http://www.gnu.org/software/autoconf/manual/autoconf.html#Generic-Programs Modified: llvm/trunk/autoconf/configure.ac llvm/trunk/configure Modified: llvm/trunk/autoconf/configure.ac URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/configure.ac?rev=47943&r1=47942&r2=47943&view=diff ============================================================================== --- llvm/trunk/autoconf/configure.ac (original) +++ llvm/trunk/autoconf/configure.ac Wed Mar 5 03:28:02 2008 @@ -580,18 +580,18 @@ dnl are not found then they are set to "true" which always succeeds but does dnl nothing. This just lets the build output show that we could have done dnl something if the tool was available. -AC_PATH_PROG(BZIP2,[bzip2],[echo "Skipped: bzip2 not found"]) -AC_PATH_PROG(DOXYGEN,[doxygen],[echo "Skipped: doxygen not found"]) -AC_PATH_PROG(GROFF,[groff],[echo "Skipped: groff not found"]) -AC_PATH_PROG(GZIP,[gzip],[echo "Skipped: gzip not found"]) -AC_PATH_PROG(POD2HTML,[pod2html],[echo "Skipped: pod2html not found"]) -AC_PATH_PROG(POD2MAN,[pod2man],[echo "Skipped: pod2man not found"]) -AC_PATH_PROG(RUNTEST,[runtest],[echo "Skipped: runtest not found"]) +AC_PATH_PROG(BZIP2, [bzip2]) +AC_PATH_PROG(DOXYGEN, [doxygen]) +AC_PATH_PROG(GROFF, [groff]) +AC_PATH_PROG(GZIP, [gzip]) +AC_PATH_PROG(POD2HTML, [pod2html]) +AC_PATH_PROG(POD2MAN, [pod2man]) +AC_PATH_PROG(RUNTEST, [runtest]) DJ_AC_PATH_TCLSH -AC_PATH_PROG(ZIP,[zip],[echo "Skipped: zip not found"]) -AC_PATH_PROG(OCAMLC,[ocamlc],[echo "Skipped: ocamlc not found"]) -AC_PATH_PROG(OCAMLOPT,[ocamlopt],[echo "Skipped: ocamlopt not found"]) -AC_PATH_PROG(OCAMLDEP,[ocamldep],[echo "Skipped: ocamldep not found"]) +AC_PATH_PROG(ZIP, [zip]) +AC_PATH_PROG(OCAMLC, [ocamlc]) +AC_PATH_PROG(OCAMLOPT, [ocamlopt]) +AC_PATH_PROG(OCAMLDEP, [ocamldep]) dnl Determine if the linker supports the -R option. AC_LINK_USE_R Modified: llvm/trunk/configure URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/configure?rev=47943&r1=47942&r2=47943&view=diff ============================================================================== --- llvm/trunk/configure (original) +++ llvm/trunk/configure Wed Mar 5 03:28:02 2008 @@ -7604,7 +7604,6 @@ done IFS=$as_save_IFS - test -z "$ac_cv_path_BZIP2" && ac_cv_path_BZIP2="echo "Skipped: bzip2 not found"" ;; esac fi @@ -7645,7 +7644,6 @@ done IFS=$as_save_IFS - test -z "$ac_cv_path_DOXYGEN" && ac_cv_path_DOXYGEN="echo "Skipped: doxygen not found"" ;; esac fi @@ -7686,7 +7684,6 @@ done IFS=$as_save_IFS - test -z "$ac_cv_path_GROFF" && ac_cv_path_GROFF="echo "Skipped: groff not found"" ;; esac fi @@ -7727,7 +7724,6 @@ done IFS=$as_save_IFS - test -z "$ac_cv_path_GZIP" && ac_cv_path_GZIP="echo "Skipped: gzip not found"" ;; esac fi @@ -7768,7 +7764,6 @@ done IFS=$as_save_IFS - test -z "$ac_cv_path_POD2HTML" && ac_cv_path_POD2HTML="echo "Skipped: pod2html not found"" ;; esac fi @@ -7809,7 +7804,6 @@ done IFS=$as_save_IFS - test -z "$ac_cv_path_POD2MAN" && ac_cv_path_POD2MAN="echo "Skipped: pod2man not found"" ;; esac fi @@ -7850,7 +7844,6 @@ done IFS=$as_save_IFS - test -z "$ac_cv_path_RUNTEST" && ac_cv_path_RUNTEST="echo "Skipped: runtest not found"" ;; esac fi @@ -7981,7 +7974,6 @@ done IFS=$as_save_IFS - test -z "$ac_cv_path_ZIP" && ac_cv_path_ZIP="echo "Skipped: zip not found"" ;; esac fi @@ -8022,7 +8014,6 @@ done IFS=$as_save_IFS - test -z "$ac_cv_path_OCAMLC" && ac_cv_path_OCAMLC="echo "Skipped: ocamlc not found"" ;; esac fi @@ -8063,7 +8054,6 @@ done IFS=$as_save_IFS - test -z "$ac_cv_path_OCAMLOPT" && ac_cv_path_OCAMLOPT="echo "Skipped: ocamlopt not found"" ;; esac fi @@ -8104,7 +8094,6 @@ done IFS=$as_save_IFS - test -z "$ac_cv_path_OCAMLDEP" && ac_cv_path_OCAMLDEP="echo "Skipped: ocamldep not found"" ;; esac fi @@ -10580,7 +10569,7 @@ lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext < conftest.$ac_ext + echo '#line 12716 "configure"' > conftest.$ac_ext if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 (eval $ac_compile) 2>&5 ac_status=$? @@ -14442,11 +14431,11 @@ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:14445: $lt_compile\"" >&5) + (eval echo "\"\$as_me:14434: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:14449: \$? = $ac_status" >&5 + echo "$as_me:14438: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings other than the usual output. @@ -14710,11 +14699,11 @@ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:14713: $lt_compile\"" >&5) + (eval echo "\"\$as_me:14702: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:14717: \$? = $ac_status" >&5 + echo "$as_me:14706: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings other than the usual output. @@ -14814,11 +14803,11 @@ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:14817: $lt_compile\"" >&5) + (eval echo "\"\$as_me:14806: $lt_compile\"" >&5) (eval "$lt_compile" 2>out/conftest.err) ac_status=$? cat out/conftest.err >&5 - echo "$as_me:14821: \$? = $ac_status" >&5 + echo "$as_me:14810: \$? = $ac_status" >&5 if (exit $ac_status) && test -s out/conftest2.$ac_objext then # The compiler can only warn and ignore the option if not recognized @@ -17266,7 +17255,7 @@ lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext < conftest.$ac_ext <&5) + (eval echo "\"\$as_me:19726: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:19741: \$? = $ac_status" >&5 + echo "$as_me:19730: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings other than the usual output. @@ -19838,11 +19827,11 @@ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:19841: $lt_compile\"" >&5) + (eval echo "\"\$as_me:19830: $lt_compile\"" >&5) (eval "$lt_compile" 2>out/conftest.err) ac_status=$? cat out/conftest.err >&5 - echo "$as_me:19845: \$? = $ac_status" >&5 + echo "$as_me:19834: \$? = $ac_status" >&5 if (exit $ac_status) && test -s out/conftest2.$ac_objext then # The compiler can only warn and ignore the option if not recognized @@ -21408,11 +21397,11 @@ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:21411: $lt_compile\"" >&5) + (eval echo "\"\$as_me:21400: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:21415: \$? = $ac_status" >&5 + echo "$as_me:21404: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings other than the usual output. @@ -21512,11 +21501,11 @@ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:21515: $lt_compile\"" >&5) + (eval echo "\"\$as_me:21504: $lt_compile\"" >&5) (eval "$lt_compile" 2>out/conftest.err) ac_status=$? cat out/conftest.err >&5 - echo "$as_me:21519: \$? = $ac_status" >&5 + echo "$as_me:21508: \$? = $ac_status" >&5 if (exit $ac_status) && test -s out/conftest2.$ac_objext then # The compiler can only warn and ignore the option if not recognized @@ -23747,11 +23736,11 @@ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:23750: $lt_compile\"" >&5) + (eval echo "\"\$as_me:23739: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:23754: \$? = $ac_status" >&5 + echo "$as_me:23743: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings other than the usual output. @@ -24015,11 +24004,11 @@ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:24018: $lt_compile\"" >&5) + (eval echo "\"\$as_me:24007: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 - echo "$as_me:24022: \$? = $ac_status" >&5 + echo "$as_me:24011: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings other than the usual output. @@ -24119,11 +24108,11 @@ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` - (eval echo "\"\$as_me:24122: $lt_compile\"" >&5) + (eval echo "\"\$as_me:24111: $lt_compile\"" >&5) (eval "$lt_compile" 2>out/conftest.err) ac_status=$? cat out/conftest.err >&5 - echo "$as_me:24126: \$? = $ac_status" >&5 + echo "$as_me:24115: \$? = $ac_status" >&5 if (exit $ac_status) && test -s out/conftest2.$ac_objext then # The compiler can only warn and ignore the option if not recognized From andrewl at lenharth.org Wed Mar 5 09:09:30 2008 From: andrewl at lenharth.org (Andrew Lenharth) Date: Wed, 5 Mar 2008 09:09:30 -0600 Subject: [llvm-commits] [llvm-gcc-4.2] r47905 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp In-Reply-To: References: <200803042118.m24LIdd4005387@zion.cs.uiuc.edu> Message-ID: <85dfcd7f0803050709i70959a5bu5f395d27abed6670@mail.gmail.com> It would be nice if someone on darwin/x86 would check why it is failing. I have no problems on 23 or 64 bit x86 linux. Andrew On 3/5/08, Owen Anderson wrote: > This was causing bootstrap failure on Darwin/X86, so I just reverted it. > > > --Owen > > > On Mar 4, 2008, at 3:18 PM, Andrew Lenharth wrote: > > > Author: alenhar2 > > Date: Tue Mar 4 15:18:39 2008 > > New Revision: 47905 > > > > URL: http://llvm.org/viewvc/llvm-project?rev=47905&view=rev > > Log: > > x86-64 supports these now, this builds fine now on linux/x86-64 > > > > Modified: > > llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp > > > > Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp > > URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=47905&r1=47904&r2=47905&view=diff > > > > = > > = > > = > > = > > = > > = > > = > > = > > ====================================================================== > > --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) > > +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Tue Mar 4 15:18:39 2008 > > @@ -4294,7 +4294,7 @@ > > C, C + 5); > > return true; > > } > > -#if defined(TARGET_ALPHA) > > +#if defined(TARGET_ALPHA) || defined(TARGET_386) > > //gcc uses many names for the sync intrinsics > > case BUILT_IN_VAL_COMPARE_AND_SWAP_1: > > case BUILT_IN_VAL_COMPARE_AND_SWAP_2: > > > > > > _______________________________________________ > > llvm-commits mailing list > > llvm-commits at cs.uiuc.edu > > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From asl at math.spbu.ru Wed Mar 5 09:11:01 2008 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Wed, 05 Mar 2008 15:11:01 -0000 Subject: [llvm-commits] [llvm] r47944 - /llvm/trunk/lib/Linker/LinkModules.cpp Message-ID: <200803051511.m25FB1wT014017@zion.cs.uiuc.edu> Author: asl Date: Wed Mar 5 09:11:00 2008 New Revision: 47944 URL: http://llvm.org/viewvc/llvm-project?rev=47944&view=rev Log: Clarify the state-of-the-art Modified: llvm/trunk/lib/Linker/LinkModules.cpp Modified: llvm/trunk/lib/Linker/LinkModules.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Linker/LinkModules.cpp?rev=47944&r1=47943&r2=47944&view=diff ============================================================================== --- llvm/trunk/lib/Linker/LinkModules.cpp (original) +++ llvm/trunk/lib/Linker/LinkModules.cpp Wed Mar 5 09:11:00 2008 @@ -568,22 +568,25 @@ // LinkAlias - Loop through the alias in the src module and link them into the // dest module. static bool LinkAlias(Module *Dest, const Module *Src, std::string *Err) { + // FIXME: Desptie of the name, this function currently does not 'link' stuff, + // but only copies aliases from one Module to another. + // Loop over all alias in the src module for (Module::const_alias_iterator I = Src->alias_begin(), E = Src->alias_end(); I != E; ++I) { const GlobalAlias *GA = I; - GlobalValue *NewAliased = NULL; - const GlobalValue *Aliased = GA->getAliasedGlobal(); - if (isa(*Aliased)) - NewAliased = Dest->getGlobalVariable(Aliased->getName()); - else if (isa(*Aliased)) - NewAliased = Dest->getFunction(Aliased->getName()); - // FIXME: we should handle the bitcast alias. - assert(NewAliased && "Can't find the aliased GV."); + GlobalValue *NewAliasee = NULL; + const GlobalValue *Aliasee = GA->getAliasedGlobal(); + if (isa(Aliasee)) + NewAliasee = Dest->getGlobalVariable(Aliasee->getName()); + else if (isa(Aliasee)) + NewAliasee = Dest->getFunction(Aliasee->getName()); + // FIXME: we should handle the bitcasted aliasee. + assert(NewAliasee && "Can't find the aliased GV."); GlobalAlias *NewGA = new GlobalAlias(GA->getType(), GA->getLinkage(), - GA->getName(), NewAliased, Dest); + GA->getName(), NewAliasee, Dest); CopyGVAttributes(NewGA, GA); } return false; From asl at math.spbu.ru Wed Mar 5 09:27:21 2008 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Wed, 05 Mar 2008 15:27:21 -0000 Subject: [llvm-commits] [llvm] r47945 - /llvm/trunk/lib/Linker/LinkModules.cpp Message-ID: <200803051527.m25FRLEZ014524@zion.cs.uiuc.edu> Author: asl Date: Wed Mar 5 09:27:21 2008 New Revision: 47945 URL: http://llvm.org/viewvc/llvm-project?rev=47945&view=rev Log: Remember the source->dest mapping when copying aliases. This fixes PR2054 Modified: llvm/trunk/lib/Linker/LinkModules.cpp Modified: llvm/trunk/lib/Linker/LinkModules.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Linker/LinkModules.cpp?rev=47945&r1=47944&r2=47945&view=diff ============================================================================== --- llvm/trunk/lib/Linker/LinkModules.cpp (original) +++ llvm/trunk/lib/Linker/LinkModules.cpp Wed Mar 5 09:27:21 2008 @@ -567,7 +567,9 @@ // LinkAlias - Loop through the alias in the src module and link them into the // dest module. -static bool LinkAlias(Module *Dest, const Module *Src, std::string *Err) { +static bool LinkAlias(Module *Dest, const Module *Src, + std::map &ValueMap, + std::string *Err) { // FIXME: Desptie of the name, this function currently does not 'link' stuff, // but only copies aliases from one Module to another. @@ -588,6 +590,8 @@ GlobalAlias *NewGA = new GlobalAlias(GA->getType(), GA->getLinkage(), GA->getName(), NewAliasee, Dest); CopyGVAttributes(NewGA, GA); + + ValueMap.insert(std::make_pair(GA, NewGA)); } return false; } @@ -1033,6 +1037,11 @@ if (LinkFunctionProtos(Dest, Src, ValueMap, ErrorMsg)) return true; + // If there were any alias, link them now. We really need to do this now, + // because all of the aliases that may be referenced need to be available in + // ValueMap + if (LinkAlias(Dest, Src, ValueMap, ErrorMsg)) return true; + // Update the initializers in the Dest module now that all globals that may // be referenced are in Dest. if (LinkGlobalInits(Dest, Src, ValueMap, ErrorMsg)) return true; @@ -1045,9 +1054,6 @@ // If there were any appending global variables, link them together now. if (LinkAppendingVars(Dest, AppendingVars, ErrorMsg)) return true; - // If there were any alias, link them now. - if (LinkAlias(Dest, Src, ErrorMsg)) return true; - // If the source library's module id is in the dependent library list of the // destination library, remove it since that module is now linked in. sys::Path modId; From asl at math.spbu.ru Wed Mar 5 09:43:58 2008 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Wed, 05 Mar 2008 15:43:58 -0000 Subject: [llvm-commits] [llvm] r47946 - in /llvm/trunk/test/Linker: 2008-03-05-AliasReference.ll 2008-03-05-AliasReference2.ll Message-ID: <200803051543.m25Fhw83015264@zion.cs.uiuc.edu> Author: asl Date: Wed Mar 5 09:43:58 2008 New Revision: 47946 URL: http://llvm.org/viewvc/llvm-project?rev=47946&view=rev Log: Testcase for PR2054 Added: llvm/trunk/test/Linker/2008-03-05-AliasReference.ll llvm/trunk/test/Linker/2008-03-05-AliasReference2.ll Added: llvm/trunk/test/Linker/2008-03-05-AliasReference.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Linker/2008-03-05-AliasReference.ll?rev=47946&view=auto ============================================================================== --- llvm/trunk/test/Linker/2008-03-05-AliasReference.ll (added) +++ llvm/trunk/test/Linker/2008-03-05-AliasReference.ll Wed Mar 5 09:43:58 2008 @@ -0,0 +1,17 @@ +; PR2054 +; RUN: llvm-as %s -o %t1.bc -f +; RUN: llvm-as %p/2008-03-05-AliasReference2.ll -o %t2.bc -f +; RUN: llvm-link %t2.bc %t1.bc -f -o %t3.bc + +; ModuleID = 'bug.o' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" +target triple = "x86_64-unknown-linux-gnu" + at foo = weak global i32 0 ; [#uses=1] + + at bar = alias weak i32* @foo ; [#uses=1] + +define i32 @baz() nounwind { +entry: + %tmp1 = load i32* @bar, align 4 ; [#uses=1] + ret i32 %tmp1 +} Added: llvm/trunk/test/Linker/2008-03-05-AliasReference2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Linker/2008-03-05-AliasReference2.ll?rev=47946&view=auto ============================================================================== --- llvm/trunk/test/Linker/2008-03-05-AliasReference2.ll (added) +++ llvm/trunk/test/Linker/2008-03-05-AliasReference2.ll Wed Mar 5 09:43:58 2008 @@ -0,0 +1,11 @@ +; This file is used by 2008-03-05-AliasReference.ll +; RUN: true + +; ModuleID = 'bug.o' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" +target triple = "x86_64-unknown-linux-gnu" + +define i32 @baz1() nounwind { +entry: + ret i32 0 +} From asl at math.spbu.ru Wed Mar 5 09:44:25 2008 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Wed, 05 Mar 2008 15:44:25 -0000 Subject: [llvm-commits] [llvm] r47947 - /llvm/trunk/test/Linker/2006-01-19-ConstantPacked.ll Message-ID: <200803051544.m25FiP4B015302@zion.cs.uiuc.edu> Author: asl Date: Wed Mar 5 09:44:25 2008 New Revision: 47947 URL: http://llvm.org/viewvc/llvm-project?rev=47947&view=rev Log: Fix test not to emit junk into source directory Modified: llvm/trunk/test/Linker/2006-01-19-ConstantPacked.ll Modified: llvm/trunk/test/Linker/2006-01-19-ConstantPacked.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Linker/2006-01-19-ConstantPacked.ll?rev=47947&r1=47946&r2=47947&view=diff ============================================================================== --- llvm/trunk/test/Linker/2006-01-19-ConstantPacked.ll (original) +++ llvm/trunk/test/Linker/2006-01-19-ConstantPacked.ll Wed Mar 5 09:44:25 2008 @@ -1,5 +1,5 @@ -; RUN: llvm-upgrade < %s | llvm-as -f -o %s.bc -; RUN: llvm-link -f -o %s.linked %s.bc +; RUN: llvm-upgrade < %s | llvm-as -f -o %t1.bc +; RUN: llvm-link -f -o %t2.bc %t1.bc target endian = big target pointersize = 32 From romix.llvm at googlemail.com Wed Mar 5 10:48:51 2008 From: romix.llvm at googlemail.com (Roman Levenstein) Date: Wed, 5 Mar 2008 17:48:51 +0100 Subject: [llvm-commits] Speeding up instruction selection Message-ID: Hi Evan, 2008/3/4, Evan Cheng : > >> There's make_heap/push_heap/etc. in that let a > >> plain std::vector (or a SmallVector I guess) be used as a heap. > > > > Yes, this is possible but produces much more overhead than std::set on > > my tests. BTW, this approach is used in DAGISel.inc files generated by > > tablegen. I tried to changed it to std::set as well and ,again, it > > works much (25%-30%) faster on BBs with few hundreds or thousends > > instructions. > > If you give me a patch, I'll test it on my end. Thanks. Here is a patch for the DAGISel.inc. It is generated as a diff against the X86GenDAGISel.inc generated by tablegen. It is a bit ugly, but gives you the idea and enables testing. As a test, I used the big4.bc, which is one huge MBB. You can find it here: http://llvm.org/bugs/attachment.cgi?id=1275&action=edit I would be very interested if you could review it, test and provide some feedback. One thing I do not quite understand about the instruction selector is: 1) Can there be more than one SDNode with the same NodeId in the ISelQueue? I have the impression that it is possible, but I'm not sure. 2) Can _the same_ SDNode ocure more than once in the ISelQueue? These two questions are relevant, if std::set is to be used. Sets use the NodeId as a key of a given SDNode and std::set ensures the uniqueness of the the elements in the ISelQueue. If (1) is true, then probably std::multiset should be used instead of std::set. I tried with both set implementations and performance was roughly the same between them. I have also one more question regarding the ISelQueue: What exactly does it represent and how is it built? My understanding is that we start with the root element and then all of its dependencies are pushed into the queue as instruction selection proceeds. Then their dependencies and so on. But is it somehow related/similar to scheduler's dependencies? Would it be possible to do some sort of the topological sorting on the DAG first and then do the selection? For the above mentioned big4.bc use-case, the ISelQueue sometimes has up-to 2000 SDNodes in the queue, which makes make_heap() very inefficient. Is it normal that the queue becomes so long? Could it be that some dependencies are just selected already and could be safely removed? I cannot really explain and realize it at the moment yet, but it seems to me that a more efficient data structure than a priority queue could be used during instruction selection. -Roman -------------- next part -------------- A non-text attachment was scrubbed... Name: X86GenDAGISel.inc.patch Type: text/x-diff Size: 5614 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20080305/07ddc900/attachment.bin From sabre at nondot.org Wed Mar 5 11:11:51 2008 From: sabre at nondot.org (Chris Lattner) Date: Wed, 05 Mar 2008 17:11:51 -0000 Subject: [llvm-commits] [llvm] r47948 - /llvm/trunk/lib/Target/X86/README-SSE.txt Message-ID: <200803051711.m25HBpi2017911@zion.cs.uiuc.edu> Author: lattner Date: Wed Mar 5 11:11:51 2008 New Revision: 47948 URL: http://llvm.org/viewvc/llvm-project?rev=47948&view=rev Log: evan implemented this. Modified: llvm/trunk/lib/Target/X86/README-SSE.txt Modified: llvm/trunk/lib/Target/X86/README-SSE.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/README-SSE.txt?rev=47948&r1=47947&r2=47948&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/README-SSE.txt (original) +++ llvm/trunk/lib/Target/X86/README-SSE.txt Wed Mar 5 11:11:51 2008 @@ -586,32 +586,6 @@ //===---------------------------------------------------------------------===// -"converting 64-bit constant pool entry to 32-bit not necessarily beneficial" -http://llvm.org/PR1264 - -For this test case: - -define double @foo(double %x) { - %y = mul double %x, 5.000000e-01 - ret double %y -} - -llc -march=x86-64 currently produces a 32-bit constant pool entry and this code: - - cvtss2sd .LCPI1_0(%rip), %xmm1 - mulsd %xmm1, %xmm0 - -instead of just using a 64-bit constant pool entry with this: - - mulsd .LCPI1_0(%rip), %xmm0 - -This is due to the code in ExpandConstantFP in LegalizeDAG.cpp. It notices that -x86-64 indeed has an instruction to load a 32-bit float from memory and convert -it into a 64-bit float in a register, however it doesn't notice that this isn't -beneficial because it prevents the load from being folded into the multiply. - -//===---------------------------------------------------------------------===// - These functions: #include From romix.llvm at googlemail.com Wed Mar 5 11:16:22 2008 From: romix.llvm at googlemail.com (Roman Levenstein) Date: Wed, 5 Mar 2008 18:16:22 +0100 Subject: [llvm-commits] Patch for review: Speeding up ScheduleDAG computations In-Reply-To: <6050EB9C-5859-496E-A193-727D23CAF638@apple.com> References: <200803031053.00270.dag@cray.com> <6050EB9C-5859-496E-A193-727D23CAF638@apple.com> Message-ID: 2008/3/5, Dan Gohman : > On Mar 4, 2008, at 3:56 AM, Roman Levenstein wrote: > > > > > make[5]: Entering directory > > `/opt/llvm.build/projects/llvm-test/SingleSource/UnitTests/Vector/SSE' > > make[5]: *** No rule to make target `Output/sse.expandfft.linked.rbc', > > needed by `Output/sse.expandfft.linked.bc'. Stop. > > > When I've seen this error, the problem has been that my base llvm > build configure was run without an llvm-gcc in PATH. llvm-test > apparently relies on the base llvm build to locate llvm-gcc for it. Thanks! Now I checked again and it seems to work. So, I have other questions about testing (I guess some of them are asked quite often ;-): 1) I do run llvm/test tests. At the end I get some figures about the number of PASSED and UNEXPECTEDLY FAILED tests. This is fine. But is it guaranteed that UNEXPECTEDLY FAILED are introduced by my code or is it possible that due to some recent changes to the repository some of those tests just fail? If it is due to the changes in the repository, how do I know what are the figures without my changes, so that I can compare and see new failures introduced by my code? Are those numbers published anywhere, may be in the nightly tests results??? Or should I basically have to source trees: one for repository version and one for my local modifications and then run tests under both trees? 2) If I run the llvm-test tests, how do I produce reports? How do I know that something failed? 3) How can I run only a selected subset of the tests from llvm-test? In particular, I only change LLC mostly. Do I have to run the llvm-test every time, or can I reduce it to something smaller? Basically, I have my ScheduleDAG patches ready, All of the proposals from the review by you and Evan are implemented. But I don't know how to test them properly using llvm tests and how can I understand if something is broken by them.... I attach both patches for now, so that someone else can test them as well, while I'm trying to figure out how to do it on my machine. -Roman -------------- next part -------------- A non-text attachment was scrubbed... Name: ScheduleDAGRRList.patch Type: text/x-diff Size: 5443 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20080305/45eaecb7/attachment.bin -------------- next part -------------- A non-text attachment was scrubbed... Name: ScheduleDAGList.patch Type: text/x-diff Size: 5507 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20080305/45eaecb7/attachment-0001.bin From evan.cheng at apple.com Wed Mar 5 11:30:37 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 5 Mar 2008 09:30:37 -0800 Subject: [llvm-commits] Patch for review: Speeding up ScheduleDAG computations In-Reply-To: References: <200803031053.00270.dag@cray.com> <6050EB9C-5859-496E-A193-727D23CAF638@apple.com> Message-ID: On Mar 5, 2008, at 9:16 AM, Roman Levenstein wrote: > 2008/3/5, Dan Gohman : >> On Mar 4, 2008, at 3:56 AM, Roman Levenstein wrote: >>> >> >>> make[5]: Entering directory >>> `/opt/llvm.build/projects/llvm-test/SingleSource/UnitTests/Vector/ >>> SSE' >>> make[5]: *** No rule to make target `Output/ >>> sse.expandfft.linked.rbc', >>> needed by `Output/sse.expandfft.linked.bc'. Stop. >> >> >> When I've seen this error, the problem has been that my base llvm >> build configure was run without an llvm-gcc in PATH. llvm-test >> apparently relies on the base llvm build to locate llvm-gcc for it. > > Thanks! Now I checked again and it seems to work. > > So, I have other questions about testing (I guess some of them are > asked quite often ;-): > > 1) I do run llvm/test tests. At the end I get some figures about the > number of PASSED and UNEXPECTEDLY FAILED tests. This is fine. But is > it guaranteed that UNEXPECTEDLY FAILED are introduced by my code or is > it possible that due to some recent changes to the repository some of > those tests just fail? If it is due to the changes in the repository, > how do I know what are the figures without my changes, so that I can > compare and see new failures introduced by my code? Are those numbers > published anywhere, may be in the nightly tests results??? Or should I > basically have to source trees: one for repository version and one for > my local modifications and then run tests under both trees? There are lots of nightly testers and they include dejagnu tests. I maintain all the Grawp* and OldGrawp* testers. These are x86 Mac OS X testers. There are also x86 linux testers. http://www.llvm.org/nightlytest/ > > > 2) If I run the llvm-test tests, how do I produce reports? How do I > know that something failed? make TEST=nightly report It will produce a report at the end that's self-explanatory. > > > 3) How can I run only a selected subset of the tests from llvm-test? > In particular, I only change LLC mostly. Do I have to run the > llvm-test every time, or can I reduce it to something smaller? Ideally you run everything everytime. But you should run at least SingleSource and MultiSource. > > > Basically, I have my ScheduleDAG patches ready, All of the proposals > from the review by you and Evan are implemented. But I don't know how > to test them properly using llvm tests and how can I understand if > something is broken by them.... > > I attach both patches for now, so that someone else can test them as > well, while I'm trying to figure out how to do it on my machine. Ok. Thanks. Evan > > > -Roman > < > ScheduleDAGRRList > .patch > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From clattner at apple.com Wed Mar 5 11:36:54 2008 From: clattner at apple.com (Chris Lattner) Date: Wed, 5 Mar 2008 09:36:54 -0800 Subject: [llvm-commits] [test-suite] r47942 - /test-suite/trunk/SingleSource/UnitTests/Vector/SSE/sse.shift.c In-Reply-To: <200803050826.m258QIo0026660@zion.cs.uiuc.edu> References: <200803050826.m258QIo0026660@zion.cs.uiuc.edu> Message-ID: <6D122EE9-AA60-42C6-BF5C-2000D24F9A21@apple.com> On Mar 5, 2008, at 12:26 AM, Evan Cheng wrote: > Author: evancheng > > +int main() { > + __m128i allones, zeroones, onezeros; > + allones = _mm_cmpeq_epi32(allones, allones); FYI, the two operands to _mm_cmpeq_epi32 are not guaranteed to have the same value. Please initialize allones. -Chris > > + zeroones = _mm_srli_epi16(allones, 8); > + printIV((IV*)&zeroones); > + onezeros = _mm_slli_epi16(allones, 8); > + printIV((IV*)&onezeros); > + return 0; > +} > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From evan.cheng at apple.com Wed Mar 5 11:42:07 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 05 Mar 2008 17:42:07 -0000 Subject: [llvm-commits] [test-suite] r47949 - /test-suite/trunk/SingleSource/UnitTests/Vector/SSE/sse.shift.c Message-ID: <200803051742.m25Hg7LK018868@zion.cs.uiuc.edu> Author: evancheng Date: Wed Mar 5 11:42:06 2008 New Revision: 47949 URL: http://llvm.org/viewvc/llvm-project?rev=47949&view=rev Log: Initialize a variable. Modified: test-suite/trunk/SingleSource/UnitTests/Vector/SSE/sse.shift.c Modified: test-suite/trunk/SingleSource/UnitTests/Vector/SSE/sse.shift.c URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/Vector/SSE/sse.shift.c?rev=47949&r1=47948&r2=47949&view=diff ============================================================================== --- test-suite/trunk/SingleSource/UnitTests/Vector/SSE/sse.shift.c (original) +++ test-suite/trunk/SingleSource/UnitTests/Vector/SSE/sse.shift.c Wed Mar 5 11:42:06 2008 @@ -11,7 +11,8 @@ } int main() { - __m128i allones, zeroones, onezeros; + __m128i allones = _mm_set1_epi32(0); + __m128i zeroones, onezeros; allones = _mm_cmpeq_epi32(allones, allones); zeroones = _mm_srli_epi16(allones, 8); printIV((IV*)&zeroones); From scottm at aero.org Wed Mar 5 11:49:05 2008 From: scottm at aero.org (Scott Michel) Date: Wed, 05 Mar 2008 17:49:05 -0000 Subject: [llvm-commits] [llvm] r47950 - in /llvm/trunk/utils/TableGen: CodeGenDAGPatterns.cpp CodeGenDAGPatterns.h Message-ID: <200803051749.m25Hn5tq019065@zion.cs.uiuc.edu> Author: pingbak Date: Wed Mar 5 11:49:05 2008 New Revision: 47950 URL: http://llvm.org/viewvc/llvm-project?rev=47950&view=rev Log: This patch fixes a problem encountered by the CellSPU backend where variants were being pruned in patterns where a variable was used more than once, e.g.: (or (and R32C:$rA, R32C:$rC), (and R32C:$rB, (not R32C:$rC))) In this example, $rC is used more than once and is actually significant to instruction selection pattern matching when commuted variants are produced. This patch scans the pattern's clauses and collects the variables, creating a set of variables that are used more than once. TreePatternNode::isIsomorphicTo() also understands that multiply-used variables are significant. Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp?rev=47950&r1=47949&r2=47950&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp (original) +++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp Wed Mar 5 11:49:05 2008 @@ -81,6 +81,53 @@ } // end namespace MVT. } // end namespace llvm. + +/// Dependent variable map for CodeGenDAGPattern variant generation +typedef std::map DepVarMap; + +/// Const iterator shorthand for DepVarMap +typedef DepVarMap::const_iterator DepVarMap_citer; + +namespace { +void FindDepVarsOf(TreePatternNode *N, DepVarMap &DepMap) { + if (N->isLeaf()) { + if (dynamic_cast(N->getLeafValue()) != NULL) { + DepMap[N->getName()]++; + } + } else { + for (size_t i = 0, e = N->getNumChildren(); i != e; ++i) + FindDepVarsOf(N->getChild(i), DepMap); + } +} + +//! Find dependent variables within child patterns +/*! + */ +void FindDepVars(TreePatternNode *N, MultipleUseVarSet &DepVars) { + DepVarMap depcounts; + FindDepVarsOf(N, depcounts); + for (DepVarMap_citer i = depcounts.begin(); i != depcounts.end(); ++i) { + if (i->second > 1) { // std::pair + DepVars.insert(i->first); + } + } +} + +//! Dump the dependent variable set: +void DumpDepVars(MultipleUseVarSet &DepVars) { + if (DepVars.empty()) { + DOUT << ""; + } else { + DOUT << "[ "; + for (MultipleUseVarSet::const_iterator i = DepVars.begin(), e = DepVars.end(); + i != e; ++i) { + DOUT << (*i) << " "; + } + DOUT << "]"; + } +} +} + //===----------------------------------------------------------------------===// // SDTypeConstraint implementation // @@ -497,11 +544,15 @@ print(*cerr.stream()); } -/// isIsomorphicTo - Return true if this node is recursively isomorphic to -/// the specified node. For this comparison, all of the state of the node -/// is considered, except for the assigned name. Nodes with differing names -/// that are otherwise identical are considered isomorphic. -bool TreePatternNode::isIsomorphicTo(const TreePatternNode *N) const { +/// isIsomorphicTo - Return true if this node is recursively +/// isomorphic to the specified node. For this comparison, the node's +/// entire state is considered. The assigned name is ignored, since +/// nodes with differing names are considered isomorphic. However, if +/// the assigned name is present in the dependent variable set, then +/// the assigned name is considered significant and the node is +/// isomorphic if the names match. +bool TreePatternNode::isIsomorphicTo(const TreePatternNode *N, + const MultipleUseVarSet &DepVars) const { if (N == this) return true; if (N->isLeaf() != isLeaf() || getExtTypes() != N->getExtTypes() || getPredicateFn() != N->getPredicateFn() || @@ -509,16 +560,20 @@ return false; if (isLeaf()) { - if (DefInit *DI = dynamic_cast(getLeafValue())) - if (DefInit *NDI = dynamic_cast(N->getLeafValue())) - return DI->getDef() == NDI->getDef(); + if (DefInit *DI = dynamic_cast(getLeafValue())) { + if (DefInit *NDI = dynamic_cast(N->getLeafValue())) { + return ((DI->getDef() == NDI->getDef()) + && (DepVars.find(getName()) == DepVars.end() + || getName() == N->getName())); + } + } return getLeafValue() == N->getLeafValue(); } if (N->getOperator() != getOperator() || N->getNumChildren() != getNumChildren()) return false; for (unsigned i = 0, e = getNumChildren(); i != e; ++i) - if (!getChild(i)->isIsomorphicTo(N->getChild(i))) + if (!getChild(i)->isIsomorphicTo(N->getChild(i), DepVars)) return false; return true; } @@ -1840,7 +1895,8 @@ static void CombineChildVariants(TreePatternNode *Orig, const std::vector > &ChildVariants, std::vector &OutVariants, - CodeGenDAGPatterns &CDP) { + CodeGenDAGPatterns &CDP, + const MultipleUseVarSet &DepVars) { // Make sure that each operand has at least one variant to choose from. for (unsigned i = 0, e = ChildVariants.size(); i != e; ++i) if (ChildVariants[i].empty()) @@ -1849,8 +1905,17 @@ // The end result is an all-pairs construction of the resultant pattern. std::vector Idxs; Idxs.resize(ChildVariants.size()); - bool NotDone = true; - while (NotDone) { + bool NotDone; + do { +#ifndef NDEBUG + if (DebugFlag && !Idxs.empty()) { + cerr << Orig->getOperator()->getName() << ": Idxs = [ "; + for (unsigned i = 0; i < Idxs.size(); ++i) { + cerr << Idxs[i] << " "; + } + cerr << "]\n"; + } +#endif // Create the variant and add it to the output list. std::vector NewChildren; for (unsigned i = 0, e = ChildVariants.size(); i != e; ++i) @@ -1863,7 +1928,7 @@ R->setTransformFn(Orig->getTransformFn()); R->setTypes(Orig->getExtTypes()); - // If this pattern cannot every match, do not include it as a variant. + // If this pattern cannot match, do not include it as a variant. std::string ErrString; if (!R->canPatternMatch(ErrString, CDP)) { delete R; @@ -1875,7 +1940,7 @@ // (and GPRC:$a, GPRC:$b) -> (and GPRC:$b, GPRC:$a) // which are the same pattern. Ignore the dups. for (unsigned i = 0, e = OutVariants.size(); i != e; ++i) - if (R->isIsomorphicTo(OutVariants[i])) { + if (R->isIsomorphicTo(OutVariants[i], DepVars)) { AlreadyExists = true; break; } @@ -1886,17 +1951,18 @@ OutVariants.push_back(R); } - // Increment indices to the next permutation. - NotDone = false; - // Look for something we can increment without causing a wrap-around. - for (unsigned IdxsIdx = 0; IdxsIdx != Idxs.size(); ++IdxsIdx) { - if (++Idxs[IdxsIdx] < ChildVariants[IdxsIdx].size()) { - NotDone = true; // Found something to increment. + // Increment indices to the next permutation by incrementing the + // indicies from last index backward, e.g., generate the sequence + // [0, 0], [0, 1], [1, 0], [1, 1]. + int IdxsIdx; + for (IdxsIdx = Idxs.size() - 1; IdxsIdx >= 0; --IdxsIdx) { + if (++Idxs[IdxsIdx] == ChildVariants[IdxsIdx].size()) + Idxs[IdxsIdx] = 0; + else break; - } - Idxs[IdxsIdx] = 0; } - } + NotDone = (IdxsIdx >= 0); + } while (NotDone); } /// CombineChildVariants - A helper function for binary operators. @@ -1905,11 +1971,12 @@ const std::vector &LHS, const std::vector &RHS, std::vector &OutVariants, - CodeGenDAGPatterns &CDP) { + CodeGenDAGPatterns &CDP, + const MultipleUseVarSet &DepVars) { std::vector > ChildVariants; ChildVariants.push_back(LHS); ChildVariants.push_back(RHS); - CombineChildVariants(Orig, ChildVariants, OutVariants, CDP); + CombineChildVariants(Orig, ChildVariants, OutVariants, CDP, DepVars); } @@ -1941,7 +2008,8 @@ /// static void GenerateVariantsOf(TreePatternNode *N, std::vector &OutVariants, - CodeGenDAGPatterns &CDP) { + CodeGenDAGPatterns &CDP, + const MultipleUseVarSet &DepVars) { // We cannot permute leaves. if (N->isLeaf()) { OutVariants.push_back(N); @@ -1962,9 +2030,9 @@ if (MaximalChildren.size() == 3) { // Find the variants of all of our maximal children. std::vector AVariants, BVariants, CVariants; - GenerateVariantsOf(MaximalChildren[0], AVariants, CDP); - GenerateVariantsOf(MaximalChildren[1], BVariants, CDP); - GenerateVariantsOf(MaximalChildren[2], CVariants, CDP); + GenerateVariantsOf(MaximalChildren[0], AVariants, CDP, DepVars); + GenerateVariantsOf(MaximalChildren[1], BVariants, CDP, DepVars); + GenerateVariantsOf(MaximalChildren[2], CVariants, CDP, DepVars); // There are only two ways we can permute the tree: // (A op B) op C and A op (B op C) @@ -1977,28 +2045,28 @@ std::vector CAVariants; std::vector BCVariants; std::vector CBVariants; - CombineChildVariants(N, AVariants, BVariants, ABVariants, CDP); - CombineChildVariants(N, BVariants, AVariants, BAVariants, CDP); - CombineChildVariants(N, AVariants, CVariants, ACVariants, CDP); - CombineChildVariants(N, CVariants, AVariants, CAVariants, CDP); - CombineChildVariants(N, BVariants, CVariants, BCVariants, CDP); - CombineChildVariants(N, CVariants, BVariants, CBVariants, CDP); + CombineChildVariants(N, AVariants, BVariants, ABVariants, CDP, DepVars); + CombineChildVariants(N, BVariants, AVariants, BAVariants, CDP, DepVars); + CombineChildVariants(N, AVariants, CVariants, ACVariants, CDP, DepVars); + CombineChildVariants(N, CVariants, AVariants, CAVariants, CDP, DepVars); + CombineChildVariants(N, BVariants, CVariants, BCVariants, CDP, DepVars); + CombineChildVariants(N, CVariants, BVariants, CBVariants, CDP, DepVars); // Combine those into the result: (x op x) op x - CombineChildVariants(N, ABVariants, CVariants, OutVariants, CDP); - CombineChildVariants(N, BAVariants, CVariants, OutVariants, CDP); - CombineChildVariants(N, ACVariants, BVariants, OutVariants, CDP); - CombineChildVariants(N, CAVariants, BVariants, OutVariants, CDP); - CombineChildVariants(N, BCVariants, AVariants, OutVariants, CDP); - CombineChildVariants(N, CBVariants, AVariants, OutVariants, CDP); + CombineChildVariants(N, ABVariants, CVariants, OutVariants, CDP, DepVars); + CombineChildVariants(N, BAVariants, CVariants, OutVariants, CDP, DepVars); + CombineChildVariants(N, ACVariants, BVariants, OutVariants, CDP, DepVars); + CombineChildVariants(N, CAVariants, BVariants, OutVariants, CDP, DepVars); + CombineChildVariants(N, BCVariants, AVariants, OutVariants, CDP, DepVars); + CombineChildVariants(N, CBVariants, AVariants, OutVariants, CDP, DepVars); // Combine those into the result: x op (x op x) - CombineChildVariants(N, CVariants, ABVariants, OutVariants, CDP); - CombineChildVariants(N, CVariants, BAVariants, OutVariants, CDP); - CombineChildVariants(N, BVariants, ACVariants, OutVariants, CDP); - CombineChildVariants(N, BVariants, CAVariants, OutVariants, CDP); - CombineChildVariants(N, AVariants, BCVariants, OutVariants, CDP); - CombineChildVariants(N, AVariants, CBVariants, OutVariants, CDP); + CombineChildVariants(N, CVariants, ABVariants, OutVariants, CDP, DepVars); + CombineChildVariants(N, CVariants, BAVariants, OutVariants, CDP, DepVars); + CombineChildVariants(N, BVariants, ACVariants, OutVariants, CDP, DepVars); + CombineChildVariants(N, BVariants, CAVariants, OutVariants, CDP, DepVars); + CombineChildVariants(N, AVariants, BCVariants, OutVariants, CDP, DepVars); + CombineChildVariants(N, AVariants, CBVariants, OutVariants, CDP, DepVars); return; } } @@ -2007,10 +2075,10 @@ std::vector > ChildVariants; ChildVariants.resize(N->getNumChildren()); for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i) - GenerateVariantsOf(N->getChild(i), ChildVariants[i], CDP); + GenerateVariantsOf(N->getChild(i), ChildVariants[i], CDP, DepVars); // Build all permutations based on how the children were formed. - CombineChildVariants(N, ChildVariants, OutVariants, CDP); + CombineChildVariants(N, ChildVariants, OutVariants, CDP, DepVars); // If this node is commutative, consider the commuted order. if (NodeInfo.hasProperty(SDNPCommutative)) { @@ -2030,7 +2098,7 @@ // Consider the commuted order. if (NC == 2) CombineChildVariants(N, ChildVariants[1], ChildVariants[0], - OutVariants, CDP); + OutVariants, CDP, DepVars); } } @@ -2050,8 +2118,13 @@ // already been added. // for (unsigned i = 0, e = PatternsToMatch.size(); i != e; ++i) { + MultipleUseVarSet DepVars; std::vector Variants; - GenerateVariantsOf(PatternsToMatch[i].getSrcPattern(), Variants, *this); + FindDepVars(PatternsToMatch[i].getSrcPattern(), DepVars); + DOUT << "Dependent/multiply used variables: "; + DEBUG(DumpDepVars(DepVars)); + DOUT << "\n"; + GenerateVariantsOf(PatternsToMatch[i].getSrcPattern(), Variants, *this, DepVars); assert(!Variants.empty() && "Must create at least original variant!"); Variants.erase(Variants.begin()); // Remove the original pattern. @@ -2074,7 +2147,7 @@ bool AlreadyExists = false; for (unsigned p = 0, e = PatternsToMatch.size(); p != e; ++p) { // Check to see if this variant already exists. - if (Variant->isIsomorphicTo(PatternsToMatch[p].getSrcPattern())) { + if (Variant->isIsomorphicTo(PatternsToMatch[p].getSrcPattern(), DepVars)) { DOUT << " *** ALREADY EXISTS, ignoring variant.\n"; AlreadyExists = true; break; Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h?rev=47950&r1=47949&r2=47950&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h (original) +++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h Wed Mar 5 11:49:05 2008 @@ -15,6 +15,8 @@ #ifndef CODEGEN_DAGPATTERNS_H #define CODEGEN_DAGPATTERNS_H +#include + #include "TableGenBackend.h" #include "CodeGenTarget.h" #include "CodeGenIntrinsics.h" @@ -48,6 +50,9 @@ bool isExtFloatingPointInVTs(const std::vector &EVTs); } +/// Set type used to track multiply used variables in patterns +typedef std::set MultipleUseVarSet; + /// SDTypeConstraint - This is a discriminated union of constraints, /// corresponding to the SDTypeConstraint tablegen class in Target.td. struct SDTypeConstraint { @@ -231,7 +236,8 @@ /// the specified node. For this comparison, all of the state of the node /// is considered, except for the assigned name. Nodes with differing names /// that are otherwise identical are considered isomorphic. - bool isIsomorphicTo(const TreePatternNode *N) const; + bool isIsomorphicTo(const TreePatternNode *N, + const MultipleUseVarSet &DepVars) const; /// SubstituteFormalArguments - Replace the formal arguments in this tree /// with actual values specified by ArgMap. From resistor at mac.com Wed Mar 5 12:18:37 2008 From: resistor at mac.com (Owen Anderson) Date: Wed, 5 Mar 2008 12:18:37 -0600 Subject: [llvm-commits] [llvm-gcc-4.2] r47905 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp In-Reply-To: <85dfcd7f0803050709i70959a5bu5f395d27abed6670@mail.gmail.com> References: <200803042118.m24LIdd4005387@zion.cs.uiuc.edu> <85dfcd7f0803050709i70959a5bu5f395d27abed6670@mail.gmail.com> Message-ID: <70BE3971-F2D6-4448-AED8-544D74FC94C2@mac.com> The exact error message was: Assertion failed: (C->getType()->isInteger() && Ty->isInteger() && "Invalid cast"), function createIntegerCast, file Instructions.cpp, line 1949. ../../../llvm-gcc-4.2/libgomp/critical.c: In function 'GOMP_critical_name_start': ../../../llvm-gcc-4.2/libgomp/critical.c:54: internal compiler error: Abort trap Please submit a full bug report, with preprocessed source if appropriate. --Owen On Mar 5, 2008, at 9:09 AM, Andrew Lenharth wrote: > It would be nice if someone on darwin/x86 would check why it is > failing. I have no problems on 23 or 64 bit x86 linux. > > Andrew > > On 3/5/08, Owen Anderson wrote: >> This was causing bootstrap failure on Darwin/X86, so I just >> reverted it. >> >> >> --Owen >> >> >> On Mar 4, 2008, at 3:18 PM, Andrew Lenharth wrote: >> >>> Author: alenhar2 >>> Date: Tue Mar 4 15:18:39 2008 >>> New Revision: 47905 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=47905&view=rev >>> Log: >>> x86-64 supports these now, this builds fine now on linux/x86-64 >>> >>> Modified: >>> llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp >>> >>> Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp >>> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=47905&r1=47904&r2=47905&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ==================================================================== >>> --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) >>> +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Tue Mar 4 15:18:39 2008 >>> @@ -4294,7 +4294,7 @@ >>> C, C + 5); >>> return true; >>> } >>> -#if defined(TARGET_ALPHA) >>> +#if defined(TARGET_ALPHA) || defined(TARGET_386) >>> //gcc uses many names for the sync intrinsics >>> case BUILT_IN_VAL_COMPARE_AND_SWAP_1: >>> case BUILT_IN_VAL_COMPARE_AND_SWAP_2: >>> >>> >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From andrewl at lenharth.org Wed Mar 5 12:26:08 2008 From: andrewl at lenharth.org (Andrew Lenharth) Date: Wed, 5 Mar 2008 12:26:08 -0600 Subject: [llvm-commits] [llvm-gcc-4.2] r47905 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp In-Reply-To: <70BE3971-F2D6-4448-AED8-544D74FC94C2@mac.com> References: <200803042118.m24LIdd4005387@zion.cs.uiuc.edu> <85dfcd7f0803050709i70959a5bu5f395d27abed6670@mail.gmail.com> <70BE3971-F2D6-4448-AED8-544D74FC94C2@mac.com> Message-ID: <85dfcd7f0803051026g173c4af5sb89fded6d131d82b@mail.gmail.com> Thanks, that's what I needed to know. I was hoping gcc would normalize the types, but apparently it doesn't. Andrew On 3/5/08, Owen Anderson wrote: > The exact error message was: > > Assertion failed: (C->getType()->isInteger() && Ty->isInteger() && > "Invalid cast"), function createIntegerCast, file Instructions.cpp, > line 1949. > ../../../llvm-gcc-4.2/libgomp/critical.c: In function > 'GOMP_critical_name_start': > ../../../llvm-gcc-4.2/libgomp/critical.c:54: internal compiler error: > Abort trap > Please submit a full bug report, > with preprocessed source if appropriate. > > > --Owen > > > On Mar 5, 2008, at 9:09 AM, Andrew Lenharth wrote: > > > It would be nice if someone on darwin/x86 would check why it is > > failing. I have no problems on 23 or 64 bit x86 linux. > > > > Andrew > > > > On 3/5/08, Owen Anderson wrote: > >> This was causing bootstrap failure on Darwin/X86, so I just > >> reverted it. > >> > >> > >> --Owen > >> > >> > >> On Mar 4, 2008, at 3:18 PM, Andrew Lenharth wrote: > >> > >>> Author: alenhar2 > >>> Date: Tue Mar 4 15:18:39 2008 > >>> New Revision: 47905 > >>> > >>> URL: http://llvm.org/viewvc/llvm-project?rev=47905&view=rev > >>> Log: > >>> x86-64 supports these now, this builds fine now on linux/x86-64 > >>> > >>> Modified: > >>> llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp > >>> > >>> Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp > >>> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=47905&r1=47904&r2=47905&view=diff > >>> > >>> = > >>> = > >>> = > >>> = > >>> = > >>> = > >>> = > >>> = > >>> = > >>> = > >>> ==================================================================== > >>> --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) > >>> +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Tue Mar 4 15:18:39 2008 > >>> @@ -4294,7 +4294,7 @@ > >>> C, C + 5); > >>> return true; > >>> } > >>> -#if defined(TARGET_ALPHA) > >>> +#if defined(TARGET_ALPHA) || defined(TARGET_386) > >>> //gcc uses many names for the sync intrinsics > >>> case BUILT_IN_VAL_COMPARE_AND_SWAP_1: > >>> case BUILT_IN_VAL_COMPARE_AND_SWAP_2: > >>> > >>> > >>> _______________________________________________ > >>> llvm-commits mailing list > >>> llvm-commits at cs.uiuc.edu > >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > >> > >> _______________________________________________ > >> llvm-commits mailing list > >> llvm-commits at cs.uiuc.edu > >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > >> > > _______________________________________________ > > llvm-commits mailing list > > llvm-commits at cs.uiuc.edu > > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From lauro.venancio at gmail.com Wed Mar 5 13:05:26 2008 From: lauro.venancio at gmail.com (Lauro Ramos Venancio) Date: Wed, 5 Mar 2008 16:05:26 -0300 Subject: [llvm-commits] [test-suite] r47756 - /test-suite/trunk/RunSafely.sh In-Reply-To: <200802291801.m1TI1E57025104@zion.cs.uiuc.edu> References: <200802291801.m1TI1E57025104@zion.cs.uiuc.edu> Message-ID: <9c10c9f0803051105r784ace72i5736f2da25b6e4b3@mail.gmail.com> > if [ "x$RHOST" = x ] ; then > - ( sh -c "$ULIMITCMD time -p $COMMAND >$OUTFILE 2>&1 < $INFILE; echo exit \$?" ) 2>&1 \ > + ( sh -c "$ULIMITCMD"; time -p sh -c "$COMMAND >$OUTFILE 2>&1 < $INFILE" ; echo exit $? ) 2>&1 \ Evan, I'm afraid you reverted the fix for PR1437. Lauro From dalej at apple.com Wed Mar 5 13:14:03 2008 From: dalej at apple.com (Dale Johannesen) Date: Wed, 05 Mar 2008 19:14:03 -0000 Subject: [llvm-commits] [llvm] r47957 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAGNodes.h lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <200803051914.m25JE38i021577@zion.cs.uiuc.edu> Author: johannes Date: Wed Mar 5 13:14:03 2008 New Revision: 47957 URL: http://llvm.org/viewvc/llvm-project?rev=47957&view=rev Log: Clarify that CALLSEQ_START..END may not be nested, and add some protection against creating such. Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=47957&r1=47956&r2=47957&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Wed Mar 5 13:14:03 2008 @@ -529,6 +529,7 @@ // a call sequence, and carry arbitrary information that target might want // to know. The first operand is a chain, the rest are specified by the // target and not touched by the DAG optimizers. + // CALLSEQ_START..CALLSEQ_END pairs may not be nested. CALLSEQ_START, // Beginning of a call sequence CALLSEQ_END, // End of a call sequence Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=47957&r1=47956&r2=47957&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Mar 5 13:14:03 2008 @@ -1266,6 +1266,13 @@ // The only option for this is to custom lower it. Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG); assert(Tmp3.Val && "Target didn't custom lower this node!"); + // A call within a calling sequence must be legalized to something + // other than the normal CALLSEQ_END. Violating this gets Legalize + // into an infinite loop. + assert ((!IsLegalizingCall || + Node->getOpcode() != ISD::CALL || + Tmp3.Val->getOpcode() != ISD::CALLSEQ_END) && + "Nested CALLSEQ_START..CALLSEQ_END not supported."); // The number of incoming and outgoing values should match; unless the final // outgoing value is a flag. From dberlin at dberlin.org Wed Mar 5 13:31:47 2008 From: dberlin at dberlin.org (Daniel Berlin) Date: Wed, 05 Mar 2008 19:31:47 -0000 Subject: [llvm-commits] [llvm] r47959 - /llvm/trunk/lib/Analysis/IPA/Andersens.cpp Message-ID: <200803051931.m25JVla3022062@zion.cs.uiuc.edu> Author: dannyb Date: Wed Mar 5 13:31:47 2008 New Revision: 47959 URL: http://llvm.org/viewvc/llvm-project?rev=47959&view=rev Log: Add Hybrid Cycle Detection to Andersen's analysis. Patch by Curtis Dunham. Modified: llvm/trunk/lib/Analysis/IPA/Andersens.cpp Modified: llvm/trunk/lib/Analysis/IPA/Andersens.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/IPA/Andersens.cpp?rev=47959&r1=47958&r2=47959&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/IPA/Andersens.cpp (original) +++ llvm/trunk/lib/Analysis/IPA/Andersens.cpp Wed Mar 5 13:31:47 2008 @@ -31,10 +31,12 @@ // address taking. // // The offline constraint graph optimization portion includes offline variable -// substitution algorithms intended to computer pointer and location +// substitution algorithms intended to compute pointer and location // equivalences. Pointer equivalences are those pointers that will have the // same points-to sets, and location equivalences are those variables that -// always appear together in points-to sets. +// always appear together in points-to sets. It also includes an offline +// cycle detection algorithm that allows cycles to be collapsed sooner +// during solving. // // The inclusion constraint solving phase iteratively propagates the inclusion // constraints until a fixed point is reached. This is an O(N^3) algorithm. @@ -48,7 +50,7 @@ // CallReturnPos. The arguments start at getNode(F) + CallArgPos. // // Future Improvements: -// Offline detection of online cycles. Use of BDD's. +// Use of BDD's. //===----------------------------------------------------------------------===// #define DEBUG_TYPE "anders-aa" @@ -418,6 +420,13 @@ // pointer equivalent but not location equivalent variables. -1 if we have // no representative node for this pointer equivalence class yet. std::vector PENLEClass2Node; + // Union/Find for HCD + std::vector HCDSCCRep; + // HCD's offline-detected cycles; "Statically DeTected" + // -1 if not part of such a cycle, otherwise a representative node. + std::vector SDT; + // Whether to use SDT (UniteNodes can use it during solving, but not before) + bool SDTActive; public: static char ID; @@ -546,6 +555,8 @@ void RewriteConstraints(); void HU(); void HVN(); + void HCD(); + void Search(unsigned Node); void UnitePointerEquivalences(); void SolveConstraints(); bool QueryNode(unsigned Node); @@ -1985,11 +1996,141 @@ } } +/// The technique used here is described in "The Ant and the +/// Grasshopper: Fast and Accurate Pointer Analysis for Millions of +/// Lines of Code. In Programming Language Design and Implementation +/// (PLDI), June 2007." It is known as the "HCD" (Hybrid Cycle +/// Detection) algorithm. It is called a hybrid because it performs an +/// offline analysis and uses its results during the solving (online) +/// phase. This is just the offline portion; the results of this +/// operation are stored in SDT and are later used in SolveContraints() +/// and UniteNodes(). +void Andersens::HCD() { + DOUT << "Starting HCD.\n"; + HCDSCCRep.resize(GraphNodes.size()); + + for (unsigned i = 0; i < GraphNodes.size(); ++i) { + GraphNodes[i].Edges = new SparseBitVector<>; + HCDSCCRep[i] = i; + } + + for (unsigned i = 0, e = Constraints.size(); i != e; ++i) { + Constraint &C = Constraints[i]; + assert (C.Src < GraphNodes.size() && C.Dest < GraphNodes.size()); + if (C.Type == Constraint::AddressOf) { + continue; + } else if (C.Type == Constraint::Load) { + if( C.Offset == 0 ) + GraphNodes[C.Dest].Edges->set(C.Src + FirstRefNode); + } else if (C.Type == Constraint::Store) { + if( C.Offset == 0 ) + GraphNodes[C.Dest + FirstRefNode].Edges->set(C.Src); + } else { + GraphNodes[C.Dest].Edges->set(C.Src); + } + } + + Node2DFS.insert(Node2DFS.begin(), GraphNodes.size(), 0); + Node2Deleted.insert(Node2Deleted.begin(), GraphNodes.size(), false); + Node2Visited.insert(Node2Visited.begin(), GraphNodes.size(), false); + SDT.insert(SDT.begin(), GraphNodes.size() / 2, -1); + + DFSNumber = 0; + for (unsigned i = 0; i < GraphNodes.size(); ++i) { + unsigned Node = HCDSCCRep[i]; + if (!Node2Deleted[Node]) + Search(Node); + } + + for (unsigned i = 0; i < GraphNodes.size(); ++i) + if (GraphNodes[i].Edges != NULL) { + delete GraphNodes[i].Edges; + GraphNodes[i].Edges = NULL; + } + + while( !SCCStack.empty() ) + SCCStack.pop(); + + Node2DFS.clear(); + Node2Visited.clear(); + Node2Deleted.clear(); + HCDSCCRep.clear(); + DOUT << "HCD complete.\n"; +} + +// Component of HCD: +// Use Nuutila's variant of Tarjan's algorithm to detect +// Strongly-Connected Components (SCCs). For non-trivial SCCs +// containing ref nodes, insert the appropriate information in SDT. +void Andersens::Search(unsigned Node) { + unsigned MyDFS = DFSNumber++; + + Node2Visited[Node] = true; + Node2DFS[Node] = MyDFS; + + for (SparseBitVector<>::iterator Iter = GraphNodes[Node].Edges->begin(), + End = GraphNodes[Node].Edges->end(); + Iter != End; + ++Iter) { + unsigned J = HCDSCCRep[*Iter]; + assert(GraphNodes[J].isRep() && "Debug check; must be representative"); + if (!Node2Deleted[J]) { + if (!Node2Visited[J]) + Search(J); + if (Node2DFS[Node] > Node2DFS[J]) + Node2DFS[Node] = Node2DFS[J]; + } + } + + if( MyDFS != Node2DFS[Node] ) { + SCCStack.push(Node); + return; + } + + // This node is the root of a SCC, so process it. + // + // If the SCC is "non-trivial" (not a singleton) and contains a reference + // node, we place this SCC into SDT. We unite the nodes in any case. + if (!SCCStack.empty() && Node2DFS[SCCStack.top()] >= MyDFS) { + SparseBitVector<> SCC; + + SCC.set(Node); + + bool Ref = (Node >= FirstRefNode); + + Node2Deleted[Node] = true; + + do { + unsigned P = SCCStack.top(); SCCStack.pop(); + Ref |= (P >= FirstRefNode); + SCC.set(P); + HCDSCCRep[P] = Node; + } while (!SCCStack.empty() && Node2DFS[SCCStack.top()] >= MyDFS); + + if (Ref) { + unsigned Rep = SCC.find_first(); + assert(Rep < FirstRefNode && "The SCC didn't have a non-Ref node!"); + + SparseBitVector<>::iterator i = SCC.begin(); + + // Skip over the non-ref nodes + while( *i < FirstRefNode ) + ++i; + + while( i != SCC.end() ) + SDT[ (*i++) - FirstRefNode ] = Rep; + } + } +} + + /// Optimize the constraints by performing offline variable substitution and /// other optimizations. void Andersens::OptimizeConstraints() { DOUT << "Beginning constraint optimization\n"; + SDTActive = false; + // Function related nodes need to stay in the same relative position and can't // be location equivalent. for (std::map::iterator Iter = MaxK.begin(); @@ -2051,12 +2192,25 @@ if (FindNode(i) == i) { Node *N = &GraphNodes[i]; delete N->PointsTo; + N->PointsTo = NULL; delete N->PredEdges; + N->PredEdges = NULL; delete N->ImplicitPredEdges; + N->ImplicitPredEdges = NULL; delete N->PointedToBy; + N->PointedToBy = NULL; } } + + // perform Hybrid Cycle Detection (HCD) + HCD(); + SDTActive = true; + + // No longer any need for the upper half of GraphNodes (for ref nodes). GraphNodes.erase(GraphNodes.begin() + FirstRefNode, GraphNodes.end()); + + // HCD complete. + DOUT << "Finished constraint optimization\n"; FirstRefNode = 0; FirstAdrNode = 0; @@ -2221,6 +2375,14 @@ } } std::queue TarjanWL; +#if !FULL_UNIVERSAL + // "Rep and special variables" - in order for HCD to maintain conservative + // results when !FULL_UNIVERSAL, we need to treat the special variables in + // the same way that the !FULL_UNIVERSAL tweak does throughout the rest of + // the analysis - it's ok to add edges from the special nodes, but never + // *to* the special nodes. + std::vector RSV; +#endif while( !CurrWL->empty() ) { DOUT << "Starting iteration #" << ++NumIters << "\n"; @@ -2259,6 +2421,39 @@ continue; *(CurrNode->OldPointsTo) |= CurrPointsTo; + + // Check the offline-computed equivalencies from HCD. + bool SCC = false; + unsigned Rep; + + if (SDT[CurrNodeIndex] >= 0) { + SCC = true; + Rep = FindNode(SDT[CurrNodeIndex]); + +#if !FULL_UNIVERSAL + RSV.clear(); +#endif + for (SparseBitVector<>::iterator bi = CurrPointsTo.begin(); + bi != CurrPointsTo.end(); ++bi) { + unsigned Node = FindNode(*bi); +#if !FULL_UNIVERSAL + if (Node < NumberSpecialNodes) { + RSV.push_back(Node); + continue; + } +#endif + Rep = UniteNodes(Rep,Node); + } +#if !FULL_UNIVERSAL + RSV.push_back(Rep); +#endif + + NextWL->insert(&GraphNodes[Rep]); + + if ( ! CurrNode->isRep() ) + continue; + } + Seen.clear(); /* Now process the constraints for this node. */ @@ -2301,39 +2496,74 @@ li++; continue; } - // TODO: hybrid cycle detection would go here, we should check + + // See if we can use Hybrid Cycle Detection (that is, check // if it was a statically detected offline equivalence that - // involves pointers , and if so, remove the redundant constraints. + // involves pointers; if so, remove the redundant constraints). + if( SCC && K == 0 ) { +#if FULL_UNIVERSAL + CurrMember = Rep; - const SparseBitVector<> &Solution = CurrPointsTo; + if (GraphNodes[*Src].Edges->test_and_set(*Dest)) + if (GraphNodes[*Dest].PointsTo |= *(GraphNodes[*Src].PointsTo)) + NextWL->insert(&GraphNodes[*Dest]); +#else + for (unsigned i=0; i < RSV.size(); ++i) { + CurrMember = RSV[i]; - for (SparseBitVector<>::iterator bi = Solution.begin(); - bi != Solution.end(); - ++bi) { - CurrMember = *bi; - - // Need to increment the member by K since that is where we are - // supposed to copy to/from. Note that in positive weight cycles, - // which occur in address taking of fields, K can go past - // MaxK[CurrMember] elements, even though that is all it could point - // to. - if (K > 0 && K > MaxK[CurrMember]) - continue; - else - CurrMember = FindNode(CurrMember + K); + if (*Dest < NumberSpecialNodes) + continue; + if (GraphNodes[*Src].Edges->test_and_set(*Dest)) + if (GraphNodes[*Dest].PointsTo |= *(GraphNodes[*Src].PointsTo)) + NextWL->insert(&GraphNodes[*Dest]); + } +#endif + // since all future elements of the points-to set will be + // equivalent to the current ones, the complex constraints + // become redundant. + // + std::list::iterator lk = li; li++; +#if !FULL_UNIVERSAL + // In this case, we can still erase the constraints when the + // elements of the points-to sets are referenced by *Dest, + // but not when they are referenced by *Src (i.e. for a Load + // constraint). This is because if another special variable is + // put into the points-to set later, we still need to add the + // new edge from that special variable. + if( lk->Type != Constraint::Load) +#endif + GraphNodes[CurrNodeIndex].Constraints.erase(lk); + } else { + const SparseBitVector<> &Solution = CurrPointsTo; + + for (SparseBitVector<>::iterator bi = Solution.begin(); + bi != Solution.end(); + ++bi) { + CurrMember = *bi; + + // Need to increment the member by K since that is where we are + // supposed to copy to/from. Note that in positive weight cycles, + // which occur in address taking of fields, K can go past + // MaxK[CurrMember] elements, even though that is all it could point + // to. + if (K > 0 && K > MaxK[CurrMember]) + continue; + else + CurrMember = FindNode(CurrMember + K); - // Add an edge to the graph, so we can just do regular bitmap ior next - // time. It may also let us notice a cycle. + // Add an edge to the graph, so we can just do regular + // bitmap ior next time. It may also let us notice a cycle. #if !FULL_UNIVERSAL - if (*Dest < NumberSpecialNodes) - continue; + if (*Dest < NumberSpecialNodes) + continue; #endif - if (GraphNodes[*Src].Edges->test_and_set(*Dest)) - if (GraphNodes[*Dest].PointsTo |= *(GraphNodes[*Src].PointsTo)) - NextWL->insert(&GraphNodes[*Dest]); + if (GraphNodes[*Src].Edges->test_and_set(*Dest)) + if (GraphNodes[*Dest].PointsTo |= *(GraphNodes[*Src].PointsTo)) + NextWL->insert(&GraphNodes[*Dest]); + } + li++; } - li++; } SparseBitVector<> NewEdges; SparseBitVector<> ToErase; @@ -2351,8 +2581,8 @@ // got an edge for the representative, delete the current edge. if (Rep == CurrNodeIndex || (Rep != DestVar && NewEdges.test(Rep))) { - ToErase.set(DestVar); - continue; + ToErase.set(DestVar); + continue; } std::pair edge(CurrNodeIndex,Rep); @@ -2395,6 +2625,8 @@ delete N->OldPointsTo; delete N->Edges; } + SDTActive = false; + SDT.clear(); } //===----------------------------------------------------------------------===// @@ -2461,7 +2693,15 @@ DEBUG(PrintNode(SecondNode)); DOUT << "\n"; - // TODO: Handle SDT + if (SDTActive) + if (SDT[Second] >= 0) + if (SDT[First] < 0) + SDT[First] = SDT[Second]; + else { + UniteNodes( FindNode(SDT[First]), FindNode(SDT[Second]) ); + First = FindNode(First); + } + return First; } From evan.cheng at apple.com Wed Mar 5 13:41:09 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 5 Mar 2008 11:41:09 -0800 Subject: [llvm-commits] Patch for review: Speeding up ScheduleDAG computations In-Reply-To: References: <200803031053.00270.dag@cray.com> <6050EB9C-5859-496E-A193-727D23CAF638@apple.com> Message-ID: <5E772510-8B4F-488A-A7B5-BBECBAE88451@apple.com> I'm seeing 2 dejagnu test failures on my machine. CodeGen/Generic/print-arith-fp.ll while running: llvm-as < /Users/echeng/LLVM/llvm/test/CodeGen/Generic/ print-arith-fp.ll | llc *** List scheduling failed! *** SU(54): 0x120edc0: i32,ch,flag = CopyFromReg 0x120e680, 0x120b6a0, 0x120e680:1 0x12073e0: ch,flag = CALLpcrel32 0x1209aa0, 0x120eaf0 0x120e680: ch,flag = ADJCALLSTACKUP 0x120f370, 0x120b100, 0x12073e0, 0x12073e0:1 has been released too many times! Assertion failed: (0), function ReleasePred, file ScheduleDAGRRList.cpp, line 213. CodeGen/X86/2007-07-03-GR64ToVR64.ll Are you seeing any issues? Evan On Mar 5, 2008, at 9:16 AM, Roman Levenstein wrote: > 2008/3/5, Dan Gohman : >> On Mar 4, 2008, at 3:56 AM, Roman Levenstein wrote: >>> >> >>> make[5]: Entering directory >>> `/opt/llvm.build/projects/llvm-test/SingleSource/UnitTests/Vector/ >>> SSE' >>> make[5]: *** No rule to make target `Output/ >>> sse.expandfft.linked.rbc', >>> needed by `Output/sse.expandfft.linked.bc'. Stop. >> >> >> When I've seen this error, the problem has been that my base llvm >> build configure was run without an llvm-gcc in PATH. llvm-test >> apparently relies on the base llvm build to locate llvm-gcc for it. > > Thanks! Now I checked again and it seems to work. > > So, I have other questions about testing (I guess some of them are > asked quite often ;-): > > 1) I do run llvm/test tests. At the end I get some figures about the > number of PASSED and UNEXPECTEDLY FAILED tests. This is fine. But is > it guaranteed that UNEXPECTEDLY FAILED are introduced by my code or is > it possible that due to some recent changes to the repository some of > those tests just fail? If it is due to the changes in the repository, > how do I know what are the figures without my changes, so that I can > compare and see new failures introduced by my code? Are those numbers > published anywhere, may be in the nightly tests results??? Or should I > basically have to source trees: one for repository version and one for > my local modifications and then run tests under both trees? > > 2) If I run the llvm-test tests, how do I produce reports? How do I > know that something failed? > > 3) How can I run only a selected subset of the tests from llvm-test? > In particular, I only change LLC mostly. Do I have to run the > llvm-test every time, or can I reduce it to something smaller? > > Basically, I have my ScheduleDAG patches ready, All of the proposals > from the review by you and Evan are implemented. But I don't know how > to test them properly using llvm tests and how can I understand if > something is broken by them.... > > I attach both patches for now, so that someone else can test them as > well, while I'm trying to figure out how to do it on my machine. > > -Roman > < > ScheduleDAGRRList > .patch > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From alenhar2 at cs.uiuc.edu Wed Mar 5 13:48:27 2008 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Wed, 05 Mar 2008 19:48:27 -0000 Subject: [llvm-commits] [llvm] r47960 - /llvm/trunk/test/CFrontend/2008-03-05-syncPtr.c Message-ID: <200803051948.m25JmRi6022476@zion.cs.uiuc.edu> Author: alenhar2 Date: Wed Mar 5 13:48:27 2008 New Revision: 47960 URL: http://llvm.org/viewvc/llvm-project?rev=47960&view=rev Log: sync ops on ptrs, was breaking libgomp Added: llvm/trunk/test/CFrontend/2008-03-05-syncPtr.c Added: llvm/trunk/test/CFrontend/2008-03-05-syncPtr.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CFrontend/2008-03-05-syncPtr.c?rev=47960&view=auto ============================================================================== --- llvm/trunk/test/CFrontend/2008-03-05-syncPtr.c (added) +++ llvm/trunk/test/CFrontend/2008-03-05-syncPtr.c Wed Mar 5 13:48:27 2008 @@ -0,0 +1,25 @@ +// RUN: %llvmgcc %s -S -emit-llvm -o /dev/null + +int* foo(int** a, int* b, int* c) { +return __sync_val_compare_and_swap (a, b, c); +} + +int foo2(int** a, int* b, int* c) { +return __sync_bool_compare_and_swap (a, b, c); +} + +int* foo3(int** a, int b) { + return __sync_fetch_and_add (a, b); +} + +int* foo4(int** a, int b) { + return __sync_fetch_and_sub (a, b); +} + +int* foo5(int** a, int* b) { + return __sync_lock_test_and_set (a, b); +} + +int* foo6(int** a, int*** b) { + return __sync_lock_test_and_set (a, b); +} From alenhar2 at cs.uiuc.edu Wed Mar 5 13:49:26 2008 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Wed, 05 Mar 2008 19:49:26 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r47961 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Message-ID: <200803051949.m25JnQZc022521@zion.cs.uiuc.edu> Author: alenhar2 Date: Wed Mar 5 13:49:26 2008 New Revision: 47961 URL: http://llvm.org/viewvc/llvm-project?rev=47961&view=rev Log: fix atomic ops on ptrs Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=47961&r1=47960&r2=47961&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Wed Mar 5 13:49:26 2008 @@ -4306,14 +4306,21 @@ case BUILT_IN_BOOL_COMPARE_AND_SWAP_4: case BUILT_IN_BOOL_COMPARE_AND_SWAP_8: case BUILT_IN_BOOL_COMPARE_AND_SWAP_16: { + const Type *ResultTy = ConvertType(TREE_TYPE(exp)); tree arglist = TREE_OPERAND(exp, 1); Value* C[3] = { Emit(TREE_VALUE(arglist), 0), Emit(TREE_VALUE(TREE_CHAIN(arglist)), 0), Emit(TREE_VALUE(TREE_CHAIN(TREE_CHAIN(arglist))), 0) }; - const Type *Ty = cast(C[0]->getType())->getElementType(); - if (C[1]->getType() != Ty) + const Type *OrigTy = cast(C[0]->getType())->getElementType(); + const Type* Ty = OrigTy; + if (isa(Ty)) + Ty = TD.getIntPtrType(); + + if (C[0]->getType() != PointerType::getUnqual(Ty)) + C[0] = Builder.CreateBitCast(C[0], PointerType::getUnqual(Ty)); + if (C[1]->getType() != Ty) C[1] = Builder.CreateIntCast(C[1], Ty, "cast"); if (C[2]->getType() != Ty) C[2] = Builder.CreateIntCast(C[2], Ty, "cast"); @@ -4329,7 +4336,8 @@ ((DECL_FUNCTION_CODE(fndecl)) == BUILT_IN_BOOL_COMPARE_AND_SWAP_8) || ((DECL_FUNCTION_CODE(fndecl)) == BUILT_IN_BOOL_COMPARE_AND_SWAP_16)) Result = Builder.CreateICmpEQ(Result, C[1]); - + else if (Ty != OrigTy) + Result = Builder.CreateIntToPtr(Result, OrigTy); return true; } case BUILT_IN_FETCH_AND_ADD_1: @@ -4342,7 +4350,7 @@ case BUILT_IN_FETCH_AND_SUB_4: case BUILT_IN_FETCH_AND_SUB_8: case BUILT_IN_FETCH_AND_SUB_16: { - const Type *Ty = ConvertType(TREE_TYPE(exp)); + const Type *ResultTy = ConvertType(TREE_TYPE(exp)); tree arglist = TREE_OPERAND(exp, 1); Value* C[2] = { Emit(TREE_VALUE(arglist), 0), @@ -4354,6 +4362,13 @@ ((DECL_FUNCTION_CODE(fndecl)) == BUILT_IN_FETCH_AND_SUB_8) || ((DECL_FUNCTION_CODE(fndecl)) == BUILT_IN_FETCH_AND_SUB_16)) C[1] = Builder.CreateNeg(C[1]); + + const Type *OrigTy = cast(C[0]->getType())->getElementType(); + const Type* Ty = OrigTy; + if (isa(Ty)) + Ty = TD.getIntPtrType(); + if (C[0]->getType() != PointerType::getUnqual(Ty)) + C[0] = Builder.CreateBitCast(C[0], PointerType::getUnqual(Ty)); if (C[1]->getType() != Ty) C[1] = Builder.CreateIntCast(C[1], Ty, "cast"); Result = @@ -4361,7 +4376,8 @@ Intrinsic::atomic_las, &Ty, 1), C, C + 2); - + if (Ty != OrigTy) + Result = Builder.CreateIntToPtr(Result, OrigTy); return true; } case BUILT_IN_LOCK_TEST_AND_SET_1: @@ -4369,12 +4385,19 @@ case BUILT_IN_LOCK_TEST_AND_SET_4: case BUILT_IN_LOCK_TEST_AND_SET_8: case BUILT_IN_LOCK_TEST_AND_SET_16: { - const Type *Ty = ConvertType(TREE_TYPE(exp)); + const Type *ResultTy = ConvertType(TREE_TYPE(exp)); tree arglist = TREE_OPERAND(exp, 1); Value* C[2] = { Emit(TREE_VALUE(arglist), 0), Emit(TREE_VALUE(TREE_CHAIN(arglist)), 0) }; + + const Type *OrigTy = cast(C[0]->getType())->getElementType(); + const Type* Ty = OrigTy; + if (isa(Ty)) + Ty = TD.getIntPtrType(); + if (C[0]->getType() != PointerType::getUnqual(Ty)) + C[0] = Builder.CreateBitCast(C[0], PointerType::getUnqual(Ty)); if (C[1]->getType() != Ty) C[1] = Builder.CreateIntCast(C[1], Ty, "cast"); Result = @@ -4383,6 +4406,8 @@ &Ty, 1), C, C + 2); + if (Ty != OrigTy) + Result = Builder.CreateIntToPtr(Result, OrigTy); return true; } #endif //FIXME: these break the build for backends that haven't implemented them From andrewl at lenharth.org Wed Mar 5 13:50:54 2008 From: andrewl at lenharth.org (Andrew Lenharth) Date: Wed, 5 Mar 2008 13:50:54 -0600 Subject: [llvm-commits] [llvm-gcc-4.2] r47905 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp In-Reply-To: <85dfcd7f0803051026g173c4af5sb89fded6d131d82b@mail.gmail.com> References: <200803042118.m24LIdd4005387@zion.cs.uiuc.edu> <85dfcd7f0803050709i70959a5bu5f395d27abed6670@mail.gmail.com> <70BE3971-F2D6-4448-AED8-544D74FC94C2@mac.com> <85dfcd7f0803051026g173c4af5sb89fded6d131d82b@mail.gmail.com> Message-ID: <85dfcd7f0803051150t2cc12b60h7c1c1827415af4e4@mail.gmail.com> > On 3/5/08, Owen Anderson wrote: > > The exact error message was: > > Would you try reenabling the sync builtins and try bootstrapping? It should be fixed now. Andrew From alenhar2 at cs.uiuc.edu Wed Mar 5 14:24:27 2008 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Wed, 05 Mar 2008 20:24:27 -0000 Subject: [llvm-commits] [llvm] r47962 - /llvm/trunk/test/CFrontend/2008-03-05-syncPtr.c Message-ID: <200803052024.m25KORx5023500@zion.cs.uiuc.edu> Author: alenhar2 Date: Wed Mar 5 14:24:26 2008 New Revision: 47962 URL: http://llvm.org/viewvc/llvm-project?rev=47962&view=rev Log: test for something more interesting than not crashing Modified: llvm/trunk/test/CFrontend/2008-03-05-syncPtr.c Modified: llvm/trunk/test/CFrontend/2008-03-05-syncPtr.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CFrontend/2008-03-05-syncPtr.c?rev=47962&r1=47961&r2=47962&view=diff ============================================================================== --- llvm/trunk/test/CFrontend/2008-03-05-syncPtr.c (original) +++ llvm/trunk/test/CFrontend/2008-03-05-syncPtr.c Wed Mar 5 14:24:26 2008 @@ -1,4 +1,4 @@ -// RUN: %llvmgcc %s -S -emit-llvm -o /dev/null +// RUN: %llvmgcc %s -S -emit-llvm -o - | grep llvm.atomic int* foo(int** a, int* b, int* c) { return __sync_val_compare_and_swap (a, b, c); From lauro.venancio at gmail.com Wed Mar 5 15:10:26 2008 From: lauro.venancio at gmail.com (Lauro Ramos Venancio) Date: Wed, 05 Mar 2008 21:10:26 -0000 Subject: [llvm-commits] [test-suite] r47963 - in /test-suite/trunk/SingleSource/Benchmarks/Misc: flops-1.c flops-2.c flops-3.c flops-4.c flops-5.c flops-6.c flops-7.c flops-8.c Message-ID: <200803052110.m25LAQRc024722@zion.cs.uiuc.edu> Author: laurov Date: Wed Mar 5 15:10:26 2008 New Revision: 47963 URL: http://llvm.org/viewvc/llvm-project?rev=47963&view=rev Log: Implement SMALL_PROBLEM_SIZE. Modified: test-suite/trunk/SingleSource/Benchmarks/Misc/flops-1.c test-suite/trunk/SingleSource/Benchmarks/Misc/flops-2.c test-suite/trunk/SingleSource/Benchmarks/Misc/flops-3.c test-suite/trunk/SingleSource/Benchmarks/Misc/flops-4.c test-suite/trunk/SingleSource/Benchmarks/Misc/flops-5.c test-suite/trunk/SingleSource/Benchmarks/Misc/flops-6.c test-suite/trunk/SingleSource/Benchmarks/Misc/flops-7.c test-suite/trunk/SingleSource/Benchmarks/Misc/flops-8.c Modified: test-suite/trunk/SingleSource/Benchmarks/Misc/flops-1.c URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/Benchmarks/Misc/flops-1.c?rev=47963&r1=47962&r2=47963&view=diff ============================================================================== --- test-suite/trunk/SingleSource/Benchmarks/Misc/flops-1.c (original) +++ test-suite/trunk/SingleSource/Benchmarks/Misc/flops-1.c Wed Mar 5 15:10:26 2008 @@ -228,7 +228,11 @@ /* in the timing. */ /* 50.0% +, 00.0% -, 42.9% *, and 07.1% / */ /*******************************************************/ +#ifdef SMALL_PROBLEM_SIZE + n = loops*200; +#else n = loops*10000; +#endif sa = 0.0; n = 2 * n; Modified: test-suite/trunk/SingleSource/Benchmarks/Misc/flops-2.c URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/Benchmarks/Misc/flops-2.c?rev=47963&r1=47962&r2=47963&view=diff ============================================================================== --- test-suite/trunk/SingleSource/Benchmarks/Misc/flops-2.c (original) +++ test-suite/trunk/SingleSource/Benchmarks/Misc/flops-2.c Wed Mar 5 15:10:26 2008 @@ -227,8 +227,11 @@ /* in the timing. */ /* 42.9% +, 28.6% -, 14.3% *, and 14.3% / */ /*******************************************************/ - +#ifdef SMALL_PROBLEM_SIZE + m = loops*400; +#else m = loops*10000; +#endif s = -five; /********************/ sa = -one; /* Loop 2. */ /********************/ Modified: test-suite/trunk/SingleSource/Benchmarks/Misc/flops-3.c URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/Benchmarks/Misc/flops-3.c?rev=47963&r1=47962&r2=47963&view=diff ============================================================================== --- test-suite/trunk/SingleSource/Benchmarks/Misc/flops-3.c (original) +++ test-suite/trunk/SingleSource/Benchmarks/Misc/flops-3.c Wed Mar 5 15:10:26 2008 @@ -220,8 +220,11 @@ /*************************/ /* Initialize the timer. */ /*************************/ - - m = loops*20000; +#ifdef SMALL_PROBLEM_SIZE + m = loops*400; +#else + m = loops*20000; +#endif /*******************************************************/ Modified: test-suite/trunk/SingleSource/Benchmarks/Misc/flops-4.c URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/Benchmarks/Misc/flops-4.c?rev=47963&r1=47962&r2=47963&view=diff ============================================================================== --- test-suite/trunk/SingleSource/Benchmarks/Misc/flops-4.c (original) +++ test-suite/trunk/SingleSource/Benchmarks/Misc/flops-4.c Wed Mar 5 15:10:26 2008 @@ -220,8 +220,11 @@ /*************************/ /* Initialize the timer. */ /*************************/ - - m = loops*10000; +#ifdef SMALL_PROBLEM_SIZE + m = loops*400; +#else + m = loops*10000; +#endif /************************************************************/ Modified: test-suite/trunk/SingleSource/Benchmarks/Misc/flops-5.c URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/Benchmarks/Misc/flops-5.c?rev=47963&r1=47962&r2=47963&view=diff ============================================================================== --- test-suite/trunk/SingleSource/Benchmarks/Misc/flops-5.c (original) +++ test-suite/trunk/SingleSource/Benchmarks/Misc/flops-5.c Wed Mar 5 15:10:26 2008 @@ -220,8 +220,11 @@ /*************************/ /* Initialize the timer. */ /*************************/ - - m = loops*10000; +#ifdef SMALL_PROBLEM_SIZE + m = loops*200; +#else + m = loops*10000; +#endif /************************************************************/ Modified: test-suite/trunk/SingleSource/Benchmarks/Misc/flops-6.c URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/Benchmarks/Misc/flops-6.c?rev=47963&r1=47962&r2=47963&view=diff ============================================================================== --- test-suite/trunk/SingleSource/Benchmarks/Misc/flops-6.c (original) +++ test-suite/trunk/SingleSource/Benchmarks/Misc/flops-6.c Wed Mar 5 15:10:26 2008 @@ -220,8 +220,11 @@ /*************************/ /* Initialize the timer. */ /*************************/ - - m = loops*10000; +#ifdef SMALL_PROBLEM_SIZE + m = loops*200; +#else + m = loops*10000; +#endif /************************************************************/ Modified: test-suite/trunk/SingleSource/Benchmarks/Misc/flops-7.c URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/Benchmarks/Misc/flops-7.c?rev=47963&r1=47962&r2=47963&view=diff ============================================================================== --- test-suite/trunk/SingleSource/Benchmarks/Misc/flops-7.c (original) +++ test-suite/trunk/SingleSource/Benchmarks/Misc/flops-7.c Wed Mar 5 15:10:26 2008 @@ -220,8 +220,11 @@ /*************************/ /* Initialize the timer. */ /*************************/ - - m = loops*10000; +#ifdef SMALL_PROBLEM_SIZE + m = loops*200; +#else + m = loops*10000; +#endif Modified: test-suite/trunk/SingleSource/Benchmarks/Misc/flops-8.c URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/Benchmarks/Misc/flops-8.c?rev=47963&r1=47962&r2=47963&view=diff ============================================================================== --- test-suite/trunk/SingleSource/Benchmarks/Misc/flops-8.c (original) +++ test-suite/trunk/SingleSource/Benchmarks/Misc/flops-8.c Wed Mar 5 15:10:26 2008 @@ -220,8 +220,11 @@ /*************************/ /* Initialize the timer. */ /*************************/ - - m = loops*10000; +#ifdef SMALL_PROBLEM_SIZE + m = loops*200; +#else + m = loops*10000; +#endif From dpatel at apple.com Wed Mar 5 15:50:29 2008 From: dpatel at apple.com (Devang Patel) Date: Wed, 05 Mar 2008 21:50:29 -0000 Subject: [llvm-commits] [llvm] r47965 - /llvm/trunk/lib/Transforms/Utils/UnifyFunctionExitNodes.cpp Message-ID: <200803052150.m25LoVNY025963@zion.cs.uiuc.edu> Author: dpatel Date: Wed Mar 5 15:50:24 2008 New Revision: 47965 URL: http://llvm.org/viewvc/llvm-project?rev=47965&view=rev Log: Handle 'ret' with multiple values. Modified: llvm/trunk/lib/Transforms/Utils/UnifyFunctionExitNodes.cpp Modified: llvm/trunk/lib/Transforms/Utils/UnifyFunctionExitNodes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/UnifyFunctionExitNodes.cpp?rev=47965&r1=47964&r2=47965&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/UnifyFunctionExitNodes.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/UnifyFunctionExitNodes.cpp Wed Mar 5 15:50:24 2008 @@ -20,6 +20,7 @@ #include "llvm/Function.h" #include "llvm/Instructions.h" #include "llvm/Type.h" +#include "llvm/ADT/SmallVector.h" using namespace llvm; char UnifyFunctionExitNodes::ID = 0; @@ -50,11 +51,6 @@ // Loop over all of the blocks in a function, tracking all of the blocks that // return. // - - // PHINode can not handle aggregates returned by multiple value ret - // instructions. TODO: Handle each return value independently. - if (isa(F.getReturnType())) - return false; std::vector ReturningBlocks; std::vector UnwindingBlocks; std::vector UnreachableBlocks; @@ -110,18 +106,30 @@ } // Otherwise, we need to insert a new basic block into the function, add a PHI - // node (if the function returns a value), and convert all of the return + // nodes (if the function returns values), and convert all of the return // instructions into unconditional branches. // BasicBlock *NewRetBlock = new BasicBlock("UnifiedReturnBlock", &F); - PHINode *PN = 0; - if (F.getReturnType() != Type::VoidTy) { + SmallVector Phis; + unsigned NumRetVals = ReturningBlocks[0]->getTerminator()->getNumOperands(); + if (NumRetVals == 0) + new ReturnInst(NULL, NewRetBlock); + else if (const StructType *STy = dyn_cast(F.getReturnType())) { + for (unsigned i = 0; i < NumRetVals; ++i) { + PHINode *PN = new PHINode(STy->getElementType(i), "UnifiedRetVal"); + NewRetBlock->getInstList().push_back(PN); + Phis.push_back(PN); + } + new ReturnInst(&Phis[0], NumRetVals); + } + else { // If the function doesn't return void... add a PHI node to the block... - PN = new PHINode(F.getReturnType(), "UnifiedRetVal"); + PHINode *PN = new PHINode(F.getReturnType(), "UnifiedRetVal"); NewRetBlock->getInstList().push_back(PN); + Phis.push_back(PN); + new ReturnInst(PN, NewRetBlock); } - new ReturnInst(PN, NewRetBlock); // Loop over all of the blocks, replacing the return instruction with an // unconditional branch. @@ -132,7 +140,11 @@ // Add an incoming element to the PHI node for every return instruction that // is merging into this new block... - if (PN) PN->addIncoming(BB->getTerminator()->getOperand(0), BB); + if (!Phis.empty()) { + for (unsigned i = 0; i < NumRetVals; ++i) + cast(Phis[i])->addIncoming(BB->getTerminator()->getOperand(i), + BB); + } BB->getInstList().pop_back(); // Remove the return insn new BranchInst(NewRetBlock, BB); From evan.cheng at apple.com Wed Mar 5 16:09:43 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 05 Mar 2008 22:09:43 -0000 Subject: [llvm-commits] [llvm] r47966 - in /llvm/trunk: lib/CodeGen/SimpleRegisterCoalescing.cpp lib/CodeGen/SimpleRegisterCoalescing.h test/CodeGen/PowerPC/2008-03-05-RegScavengerAssert.ll Message-ID: <200803052209.m25M9hhE026634@zion.cs.uiuc.edu> Author: evancheng Date: Wed Mar 5 16:09:42 2008 New Revision: 47966 URL: http://llvm.org/viewvc/llvm-project?rev=47966&view=rev Log: Fix a coalescer bug wrt how dead copy interval is shortened. Added: llvm/trunk/test/CodeGen/PowerPC/2008-03-05-RegScavengerAssert.ll Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=47966&r1=47965&r2=47966&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original) +++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Wed Mar 5 16:09:42 2008 @@ -451,6 +451,30 @@ } } +/// ShortenDeadCopyLiveRange - Shorten a live range as it's artificially +/// extended by a dead copy. Mark the last use (if any) of the val# as kill +/// as ends the live range there. If there isn't another use, then this +/// live range is dead. +void SimpleRegisterCoalescing::ShortenDeadCopyLiveRange(LiveInterval &li, + MachineInstr *CopyMI) { + unsigned CopyIdx = li_->getInstructionIndex(CopyMI); + LiveInterval::iterator MLR = + li.FindLiveRangeContaining(li_->getDefIndex(CopyIdx)); + unsigned RemoveStart = MLR->start; + unsigned RemoveEnd = MLR->end; + unsigned LastUseIdx; + MachineOperand *LastUse = lastRegisterUse(RemoveStart, CopyIdx, li.reg, + LastUseIdx); + if (LastUse) { + // Shorten the liveinterval to the end of last use. + LastUse->setIsKill(); + RemoveStart = li_->getDefIndex(LastUseIdx); + } + li.removeRange(RemoveStart, RemoveEnd, true); + if (li.empty()) + li_->removeInterval(li.reg); +} + /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg, /// which are the src/dst of the copy instruction CopyMI. This returns true /// if the copy was successfully coalesced away. If it is not currently @@ -599,23 +623,22 @@ SrcInt.FindLiveRangeContaining(li_->getUseIndex(CopyIdx)); RemoveStart = SrcStart = SrcLR->start; RemoveEnd = SrcEnd = SrcLR->end; - // The instruction which defines the src is only truly dead if there are - // no intermediate uses and there isn't a use beyond the copy. - // FIXME: find the last use, mark is kill and shorten the live range. if (SrcEnd > li_->getDefIndex(CopyIdx)) { + // If there are other uses of SrcReg beyond the copy, there is nothing to do. isDead = false; } else { unsigned LastUseIdx; MachineOperand *LastUse = lastRegisterUse(SrcStart, CopyIdx, SrcReg, LastUseIdx); if (LastUse) { - // Shorten the liveinterval to the end of last use. + // There are uses before the copy, just shorten the live range to the end + // of last use. LastUse->setIsKill(); isDead = false; isShorten = true; RemoveStart = li_->getDefIndex(LastUseIdx); - RemoveEnd = SrcEnd; } else { + // This live range is truly dead. Remove it. MachineInstr *SrcMI = li_->getInstructionFromIndex(SrcStart); if (SrcMI && SrcMI->modifiesRegister(SrcReg, tri_)) // A dead def should have a single cycle interval. @@ -1531,16 +1554,10 @@ if (tii_->isMoveInstr(*mii, srcReg, dstReg) && srcReg == dstReg) { // remove from def list LiveInterval &RegInt = li_->getOrCreateInterval(srcReg); - MachineOperand *MO = mii->findRegisterDefOperand(dstReg, false); // If def of this move instruction is dead, remove its live range from // the dstination register's live interval. - if (MO->isDead()) { - unsigned MoveIdx = li_->getDefIndex(li_->getInstructionIndex(mii)); - LiveInterval::iterator MLR = RegInt.FindLiveRangeContaining(MoveIdx); - RegInt.removeRange(MLR->start, MoveIdx+1, true); - if (RegInt.empty()) - li_->removeInterval(srcReg); - } + if (mii->registerDefIsDead(dstReg)) + ShortenDeadCopyLiveRange(RegInt, mii); li_->RemoveMachineInstrFromMaps(mii); mii = mbbi->erase(mii); ++numPeep; Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h?rev=47966&r1=47965&r2=47966&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h (original) +++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h Wed Mar 5 16:09:42 2008 @@ -201,6 +201,12 @@ /// subregister. void UpdateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx); + /// ShortenDeadCopyLiveRange - Shorten a live range as it's artificially + /// extended by a dead copy. Mark the last use (if any) of the val# as kill + /// as ends the live range there. If there isn't another use, then this + /// live range is dead. + void ShortenDeadCopyLiveRange(LiveInterval &li, MachineInstr *CopyMI); + /// lastRegisterUse - Returns the last use of the specific register between /// cycles Start and End or NULL if there are no uses. MachineOperand *lastRegisterUse(unsigned Start, unsigned End, unsigned Reg, Added: llvm/trunk/test/CodeGen/PowerPC/2008-03-05-RegScavengerAssert.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/2008-03-05-RegScavengerAssert.ll?rev=47966&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/PowerPC/2008-03-05-RegScavengerAssert.ll (added) +++ llvm/trunk/test/CodeGen/PowerPC/2008-03-05-RegScavengerAssert.ll Wed Mar 5 16:09:42 2008 @@ -0,0 +1,18 @@ +; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin -enable-ppc-regscavenger + +declare i8* @bar(i32) + +define void @foo(i8* %pp) nounwind { +entry: + %tmp2 = tail call i8* @bar( i32 14 ) nounwind ; [#uses=0] + %tmp28 = bitcast i8* %pp to void ()** ; [#uses=1] + %tmp38 = load void ()** %tmp28, align 4 ; [#uses=2] + br i1 false, label %bb34, label %bb25 +bb25: ; preds = %entry + %tmp30 = bitcast void ()* %tmp38 to void (i8*)* ; [#uses=1] + tail call void %tmp30( i8* null ) nounwind + ret void +bb34: ; preds = %entry + tail call void %tmp38( ) nounwind + ret void +} From asl at math.spbu.ru Wed Mar 5 16:22:47 2008 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Wed, 05 Mar 2008 22:22:47 -0000 Subject: [llvm-commits] [llvm] r47968 - /llvm/trunk/lib/Linker/LinkModules.cpp Message-ID: <200803052222.m25MMlxB027088@zion.cs.uiuc.edu> Author: asl Date: Wed Mar 5 16:22:46 2008 New Revision: 47968 URL: http://llvm.org/viewvc/llvm-project?rev=47968&view=rev Log: Try hard to link aliases. Checks can be too strict by now. Modified: llvm/trunk/lib/Linker/LinkModules.cpp Modified: llvm/trunk/lib/Linker/LinkModules.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Linker/LinkModules.cpp?rev=47968&r1=47967&r2=47968&view=diff ============================================================================== --- llvm/trunk/lib/Linker/LinkModules.cpp (original) +++ llvm/trunk/lib/Linker/LinkModules.cpp Wed Mar 5 16:22:46 2008 @@ -565,34 +565,115 @@ return false; } +static GlobalValue::LinkageTypes +CalculateAliasLinkage(const GlobalValue *SGV, const GlobalValue *DGV) { + if (SGV->hasExternalLinkage() || DGV->hasExternalLinkage()) + return GlobalValue::ExternalLinkage; + else if (SGV->hasWeakLinkage() || DGV->hasWeakLinkage()) + return GlobalValue::WeakLinkage; + else { + assert(SGV->hasInternalLinkage() && DGV->hasInternalLinkage() && + "Unexpected linkage type"); + return GlobalValue::InternalLinkage; + } +} + // LinkAlias - Loop through the alias in the src module and link them into the -// dest module. +// dest module. We're assuming, that all functions/global variables were already +// linked in. static bool LinkAlias(Module *Dest, const Module *Src, std::map &ValueMap, std::string *Err) { - // FIXME: Desptie of the name, this function currently does not 'link' stuff, - // but only copies aliases from one Module to another. - // Loop over all alias in the src module for (Module::const_alias_iterator I = Src->alias_begin(), E = Src->alias_end(); I != E; ++I) { - const GlobalAlias *GA = I; + const GlobalAlias *SGA = I; + const GlobalValue *SAliasee = SGA->getAliasedGlobal(); + GlobalAlias *NewGA = NULL; + + // Globals were already linked, thus we can just query ValueMap for variant + // of SAliasee in Dest + std::map::const_iterator I = ValueMap.find(SAliasee); + assert(I != ValueMap.end() && "Aliasee not linked"); + GlobalValue* DAliasee = cast(I->second); + + // Try to find something 'similar' to SGA in destination module. + if (GlobalAlias *DGA = Dest->getNamedAlias(SGA->getName())) { + // If types don't agree due to opaque types, try to resolve them. + if (RecursiveResolveTypes(SGA->getType(), DGA->getType(), + &Dest->getTypeSymbolTable(), "")) + return Error(Err, "Alias Collision on '" + + ToStr(SGA->getType(), Src) +"':%"+SGA->getName()+ + " - aliases have different types"); + + // Now types are known to be the same, check whether aliasees equal. As + // globals are already linked we just need query ValueMap to find the + // mapping. + if (DAliasee == DGA->getAliasedGlobal()) { + // This is just two copies of the same alias. Propagate linkage, if + // necessary. + DGA->setLinkage(CalculateAliasLinkage(SGA, DGA)); + + NewGA = DGA; + // Proceed to 'common' steps + } else + return Error(Err, "Alias Collision on '" + + ToStr(SGA->getType(), Src) +"':%"+SGA->getName()+ + " - aliases have different aliasees"); + } else if (GlobalVariable *DGV = Dest->getGlobalVariable(SGA->getName())) { + RecursiveResolveTypes(SGA->getType(), DGV->getType(), + &Dest->getTypeSymbolTable(), ""); + // The only allowed way is to link alias with external declaration. + if (DGV->isDeclaration()) { + NewGA = new GlobalAlias(SGA->getType(), SGA->getLinkage(), + SGA->getName(), DAliasee, Dest); + CopyGVAttributes(NewGA, SGA); + + // Any uses of DGV need to change to NewGA, with cast, if needed. + if (SGA->getType() != DGV->getType()) + DGV->replaceAllUsesWith(ConstantExpr::getBitCast(NewGA, + DGV->getType())); + else + DGV->replaceAllUsesWith(NewGA); + + // DGV will conflict with NewGA because they both had the same + // name. We must erase this now so ForceRenaming doesn't assert + // because DGV might not have internal linkage. + DGV->eraseFromParent(); + + // Proceed to 'common' steps + } else + return Error(Err, "Alias Collision on '" + + ToStr(SGA->getType(), Src) +"':%"+SGA->getName()+ + " - symbol multiple defined"); + } else if (Function *DF = Dest->getFunction(SGA->getName())) { + RecursiveResolveTypes(SGA->getType(), DF->getType(), + &Dest->getTypeSymbolTable(), ""); + assert(0 && "FIXME"); + } else { + // Nothing similar found, just copy alias into destination module. - GlobalValue *NewAliasee = NULL; - const GlobalValue *Aliasee = GA->getAliasedGlobal(); - if (isa(Aliasee)) - NewAliasee = Dest->getGlobalVariable(Aliasee->getName()); - else if (isa(Aliasee)) - NewAliasee = Dest->getFunction(Aliasee->getName()); - // FIXME: we should handle the bitcasted aliasee. - assert(NewAliasee && "Can't find the aliased GV."); - - GlobalAlias *NewGA = new GlobalAlias(GA->getType(), GA->getLinkage(), - GA->getName(), NewAliasee, Dest); - CopyGVAttributes(NewGA, GA); + NewGA = new GlobalAlias(SGA->getType(), SGA->getLinkage(), + SGA->getName(), DAliasee, Dest); + CopyGVAttributes(NewGA, SGA); - ValueMap.insert(std::make_pair(GA, NewGA)); + // Proceed to 'common' steps + } + + assert(NewGA && "No alias was created in destination module!"); + + // If the symbol table renamed the function, but it is an externally + // visible symbol, DGV must be an existing function with internal + // linkage. Rename it. + if (NewGA->getName() != SGA->getName() && + !NewGA->hasInternalLinkage()) + ForceRenaming(NewGA, SGA->getName()); + + // Remember this mapping so uses in the source module get remapped + // later by RemapOperand. + ValueMap.insert(std::make_pair(SGA, NewGA)); } + return false; } From snaroff at apple.com Wed Mar 5 16:30:39 2008 From: snaroff at apple.com (Steve Naroff) Date: Wed, 05 Mar 2008 22:30:39 -0000 Subject: [llvm-commits] [llvm] r47969 - /llvm/trunk/win32/Support/Support.vcproj Message-ID: <200803052230.m25MUdkx027491@zion.cs.uiuc.edu> Author: snaroff Date: Wed Mar 5 16:30:39 2008 New Revision: 47969 URL: http://llvm.org/viewvc/llvm-project?rev=47969&view=rev Log: Update vcproj file. Modified: llvm/trunk/win32/Support/Support.vcproj Modified: llvm/trunk/win32/Support/Support.vcproj URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/win32/Support/Support.vcproj?rev=47969&r1=47968&r2=47969&view=diff ============================================================================== --- llvm/trunk/win32/Support/Support.vcproj (original) +++ llvm/trunk/win32/Support/Support.vcproj Wed Mar 5 16:30:39 2008 @@ -4,6 +4,7 @@ Version="8.00" Name="support" ProjectGUID="{28AA9146-3482-4F41-9CC6-407B1D258508}" + RootNamespace="support" Keyword="Win32Proj" > @@ -321,6 +322,10 @@ > + + From scottm at aero.org Wed Mar 5 17:00:20 2008 From: scottm at aero.org (Scott Michel) Date: Wed, 05 Mar 2008 23:00:20 -0000 Subject: [llvm-commits] [llvm] r47972 - in /llvm/trunk/test/CodeGen/CellSPU: and_ops.ll call_indirect.ll ctpop.ll dp_farith.ll eqv.ll fcmp.ll fdiv.ll fneg-fabs.ll immed16.ll immed32.ll immed64.ll int2fp.ll intrinsics_branch.ll intrinsics_float.ll intrinsics_logical.ll mul_ops.ll or_ops.ll rotate_ops.ll select_bits.ll shift_ops.ll sp_farith.ll struct_1.ll vec_const.ll vecinsert.ll Message-ID: <200803052300.m25N0LbU028459@zion.cs.uiuc.edu> Author: pingbak Date: Wed Mar 5 17:00:19 2008 New Revision: 47972 URL: http://llvm.org/viewvc/llvm-project?rev=47972&view=rev Log: - Expand tabs to spaces. - select_bits.ll now fully functional now that PR1993 is closed. It was previously broken by refactoring in SPUInstrInfo.td and using multiclasses. - Same for eqv.ll Modified: llvm/trunk/test/CodeGen/CellSPU/and_ops.ll llvm/trunk/test/CodeGen/CellSPU/call_indirect.ll llvm/trunk/test/CodeGen/CellSPU/ctpop.ll llvm/trunk/test/CodeGen/CellSPU/dp_farith.ll llvm/trunk/test/CodeGen/CellSPU/eqv.ll llvm/trunk/test/CodeGen/CellSPU/fcmp.ll llvm/trunk/test/CodeGen/CellSPU/fdiv.ll llvm/trunk/test/CodeGen/CellSPU/fneg-fabs.ll llvm/trunk/test/CodeGen/CellSPU/immed16.ll llvm/trunk/test/CodeGen/CellSPU/immed32.ll llvm/trunk/test/CodeGen/CellSPU/immed64.ll llvm/trunk/test/CodeGen/CellSPU/int2fp.ll llvm/trunk/test/CodeGen/CellSPU/intrinsics_branch.ll llvm/trunk/test/CodeGen/CellSPU/intrinsics_float.ll llvm/trunk/test/CodeGen/CellSPU/intrinsics_logical.ll llvm/trunk/test/CodeGen/CellSPU/mul_ops.ll llvm/trunk/test/CodeGen/CellSPU/or_ops.ll llvm/trunk/test/CodeGen/CellSPU/rotate_ops.ll llvm/trunk/test/CodeGen/CellSPU/select_bits.ll llvm/trunk/test/CodeGen/CellSPU/shift_ops.ll llvm/trunk/test/CodeGen/CellSPU/sp_farith.ll llvm/trunk/test/CodeGen/CellSPU/struct_1.ll llvm/trunk/test/CodeGen/CellSPU/vec_const.ll llvm/trunk/test/CodeGen/CellSPU/vecinsert.ll Modified: llvm/trunk/test/CodeGen/CellSPU/and_ops.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/and_ops.ll?rev=47972&r1=47971&r2=47972&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/CellSPU/and_ops.ll (original) +++ llvm/trunk/test/CodeGen/CellSPU/and_ops.ll Wed Mar 5 17:00:19 2008 @@ -4,6 +4,7 @@ ; RUN: grep andi %t1.s | count 36 ; RUN: grep andhi %t1.s | count 30 ; RUN: grep andbi %t1.s | count 4 + target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128" target triple = "spu" @@ -39,33 +40,33 @@ } define i32 @and_i32_1(i32 %arg1, i32 %arg2) { - %A = and i32 %arg2, %arg1 - ret i32 %A + %A = and i32 %arg2, %arg1 + ret i32 %A } define i32 @and_i32_2(i32 %arg1, i32 %arg2) { - %A = and i32 %arg1, %arg2 - ret i32 %A + %A = and i32 %arg1, %arg2 + ret i32 %A } define i16 @and_i16_1(i16 %arg1, i16 %arg2) { - %A = and i16 %arg2, %arg1 - ret i16 %A + %A = and i16 %arg2, %arg1 + ret i16 %A } define i16 @and_i16_2(i16 %arg1, i16 %arg2) { - %A = and i16 %arg1, %arg2 - ret i16 %A + %A = and i16 %arg1, %arg2 + ret i16 %A } define i8 @and_i8_1(i8 %arg1, i8 %arg2) { - %A = and i8 %arg2, %arg1 - ret i8 %A + %A = and i8 %arg2, %arg1 + ret i8 %A } define i8 @and_i8_2(i8 %arg1, i8 %arg2) { - %A = and i8 %arg1, %arg2 - ret i8 %A + %A = and i8 %arg1, %arg2 + ret i8 %A } ; ANDC instruction generation: @@ -126,57 +127,57 @@ } define i32 @andc_i32_1(i32 %arg1, i32 %arg2) { - %A = xor i32 %arg2, -1 - %B = and i32 %A, %arg1 - ret i32 %B + %A = xor i32 %arg2, -1 + %B = and i32 %A, %arg1 + ret i32 %B } define i32 @andc_i32_2(i32 %arg1, i32 %arg2) { - %A = xor i32 %arg1, -1 - %B = and i32 %A, %arg2 - ret i32 %B + %A = xor i32 %arg1, -1 + %B = and i32 %A, %arg2 + ret i32 %B } define i32 @andc_i32_3(i32 %arg1, i32 %arg2) { - %A = xor i32 %arg2, -1 - %B = and i32 %arg1, %A - ret i32 %B + %A = xor i32 %arg2, -1 + %B = and i32 %arg1, %A + ret i32 %B } define i16 @andc_i16_1(i16 %arg1, i16 %arg2) { - %A = xor i16 %arg2, -1 - %B = and i16 %A, %arg1 - ret i16 %B + %A = xor i16 %arg2, -1 + %B = and i16 %A, %arg1 + ret i16 %B } define i16 @andc_i16_2(i16 %arg1, i16 %arg2) { - %A = xor i16 %arg1, -1 - %B = and i16 %A, %arg2 - ret i16 %B + %A = xor i16 %arg1, -1 + %B = and i16 %A, %arg2 + ret i16 %B } define i16 @andc_i16_3(i16 %arg1, i16 %arg2) { - %A = xor i16 %arg2, -1 - %B = and i16 %arg1, %A - ret i16 %B + %A = xor i16 %arg2, -1 + %B = and i16 %arg1, %A + ret i16 %B } define i8 @andc_i8_1(i8 %arg1, i8 %arg2) { - %A = xor i8 %arg2, -1 - %B = and i8 %A, %arg1 - ret i8 %B + %A = xor i8 %arg2, -1 + %B = and i8 %A, %arg1 + ret i8 %B } define i8 @andc_i8_2(i8 %arg1, i8 %arg2) { - %A = xor i8 %arg1, -1 - %B = and i8 %A, %arg2 - ret i8 %B + %A = xor i8 %arg1, -1 + %B = and i8 %A, %arg2 + ret i8 %B } define i8 @andc_i8_3(i8 %arg1, i8 %arg2) { - %A = xor i8 %arg2, -1 - %B = and i8 %arg1, %A - ret i8 %B + %A = xor i8 %arg2, -1 + %B = and i8 %arg1, %A + ret i8 %B } ; ANDI instruction generation (i32 data type): @@ -252,7 +253,7 @@ ; i8 data type (s/b ANDBI if 8-bit registers were supported): define <16 x i8> @and_v16i8(<16 x i8> %in) { - ; ANDBI generated for vector types + ; ANDBI generated for vector types %tmp2 = and <16 x i8> %in, < i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42 > @@ -260,19 +261,19 @@ } define i8 @and_u8(i8 zeroext %in) zeroext { - ; ANDBI generated: + ; ANDBI generated: %tmp37 = and i8 %in, 37 ret i8 %tmp37 } define i8 @and_sext8(i8 signext %in) signext { - ; ANDBI generated + ; ANDBI generated %tmp38 = and i8 %in, 37 ret i8 %tmp38 } define i8 @and_i8(i8 %in) { - ; ANDBI generated + ; ANDBI generated %tmp38 = and i8 %in, 205 ret i8 %tmp38 } Modified: llvm/trunk/test/CodeGen/CellSPU/call_indirect.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/call_indirect.ll?rev=47972&r1=47971&r2=47972&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/CellSPU/call_indirect.ll (original) +++ llvm/trunk/test/CodeGen/CellSPU/call_indirect.ll Wed Mar 5 17:00:19 2008 @@ -23,27 +23,27 @@ define void @dispatcher(i32 %i_arg, float %f_arg) { entry: - %tmp2 = load void (i32, float)** getelementptr ([6 x void (i32, float)*]* @dispatch_tab, i32 0, i32 0), align 16 - tail call void %tmp2( i32 %i_arg, float %f_arg ) - %tmp2.1 = load void (i32, float)** getelementptr ([6 x void (i32, float)*]* @dispatch_tab, i32 0, i32 1), align 4 - tail call void %tmp2.1( i32 %i_arg, float %f_arg ) - %tmp2.2 = load void (i32, float)** getelementptr ([6 x void (i32, float)*]* @dispatch_tab, i32 0, i32 2), align 4 - tail call void %tmp2.2( i32 %i_arg, float %f_arg ) - %tmp2.3 = load void (i32, float)** getelementptr ([6 x void (i32, float)*]* @dispatch_tab, i32 0, i32 3), align 4 - tail call void %tmp2.3( i32 %i_arg, float %f_arg ) - %tmp2.4 = load void (i32, float)** getelementptr ([6 x void (i32, float)*]* @dispatch_tab, i32 0, i32 4), align 4 - tail call void %tmp2.4( i32 %i_arg, float %f_arg ) - %tmp2.5 = load void (i32, float)** getelementptr ([6 x void (i32, float)*]* @dispatch_tab, i32 0, i32 5), align 4 - tail call void %tmp2.5( i32 %i_arg, float %f_arg ) - ret void + %tmp2 = load void (i32, float)** getelementptr ([6 x void (i32, float)*]* @dispatch_tab, i32 0, i32 0), align 16 + tail call void %tmp2( i32 %i_arg, float %f_arg ) + %tmp2.1 = load void (i32, float)** getelementptr ([6 x void (i32, float)*]* @dispatch_tab, i32 0, i32 1), align 4 + tail call void %tmp2.1( i32 %i_arg, float %f_arg ) + %tmp2.2 = load void (i32, float)** getelementptr ([6 x void (i32, float)*]* @dispatch_tab, i32 0, i32 2), align 4 + tail call void %tmp2.2( i32 %i_arg, float %f_arg ) + %tmp2.3 = load void (i32, float)** getelementptr ([6 x void (i32, float)*]* @dispatch_tab, i32 0, i32 3), align 4 + tail call void %tmp2.3( i32 %i_arg, float %f_arg ) + %tmp2.4 = load void (i32, float)** getelementptr ([6 x void (i32, float)*]* @dispatch_tab, i32 0, i32 4), align 4 + tail call void %tmp2.4( i32 %i_arg, float %f_arg ) + %tmp2.5 = load void (i32, float)** getelementptr ([6 x void (i32, float)*]* @dispatch_tab, i32 0, i32 5), align 4 + tail call void %tmp2.5( i32 %i_arg, float %f_arg ) + ret void } @ptr_list = internal global [1 x void ()*] [ void ()* inttoptr (i64 4294967295 to void ()*) ], align 4 @ptr.a = internal global void ()** getelementptr ([1 x void ()*]* @ptr_list, i32 0, i32 1), align 16 define void @double_indirect_call() { - %a = load void ()*** @ptr.a, align 16 - %b = load void ()** %a, align 4 - tail call void %b() - ret void + %a = load void ()*** @ptr.a, align 16 + %b = load void ()** %a, align 4 + tail call void %b() + ret void } Modified: llvm/trunk/test/CodeGen/CellSPU/ctpop.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/ctpop.ll?rev=47972&r1=47971&r2=47972&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/CellSPU/ctpop.ll (original) +++ llvm/trunk/test/CodeGen/CellSPU/ctpop.ll Wed Mar 5 17:00:19 2008 @@ -11,20 +11,20 @@ declare i32 @llvm.ctpop.i32(i32) define i32 @test_i8(i8 %X) { - call i32 @llvm.ctpop.i8(i8 %X) - %Y = bitcast i32 %1 to i32 - ret i32 %Y + call i32 @llvm.ctpop.i8(i8 %X) + %Y = bitcast i32 %1 to i32 + ret i32 %Y } define i32 @test_i16(i16 %X) { call i32 @llvm.ctpop.i16(i16 %X) - %Y = bitcast i32 %1 to i32 + %Y = bitcast i32 %1 to i32 ret i32 %Y } define i32 @test_i32(i32 %X) { call i32 @llvm.ctpop.i32(i32 %X) - %Y = bitcast i32 %1 to i32 + %Y = bitcast i32 %1 to i32 ret i32 %Y } Modified: llvm/trunk/test/CodeGen/CellSPU/dp_farith.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/dp_farith.ll?rev=47972&r1=47971&r2=47972&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/CellSPU/dp_farith.ll (original) +++ llvm/trunk/test/CodeGen/CellSPU/dp_farith.ll Wed Mar 5 17:00:19 2008 @@ -11,92 +11,92 @@ target triple = "spu" define double @fadd(double %arg1, double %arg2) { - %A = add double %arg1, %arg2 - ret double %A + %A = add double %arg1, %arg2 + ret double %A } define <2 x double> @fadd_vec(<2 x double> %arg1, <2 x double> %arg2) { - %A = add <2 x double> %arg1, %arg2 - ret <2 x double> %A + %A = add <2 x double> %arg1, %arg2 + ret <2 x double> %A } define double @fsub(double %arg1, double %arg2) { - %A = sub double %arg1, %arg2 - ret double %A + %A = sub double %arg1, %arg2 + ret double %A } define <2 x double> @fsub_vec(<2 x double> %arg1, <2 x double> %arg2) { - %A = sub <2 x double> %arg1, %arg2 - ret <2 x double> %A + %A = sub <2 x double> %arg1, %arg2 + ret <2 x double> %A } define double @fmul(double %arg1, double %arg2) { - %A = mul double %arg1, %arg2 - ret double %A + %A = mul double %arg1, %arg2 + ret double %A } define <2 x double> @fmul_vec(<2 x double> %arg1, <2 x double> %arg2) { - %A = mul <2 x double> %arg1, %arg2 - ret <2 x double> %A + %A = mul <2 x double> %arg1, %arg2 + ret <2 x double> %A } define double @fma(double %arg1, double %arg2, double %arg3) { - %A = mul double %arg1, %arg2 - %B = add double %A, %arg3 - ret double %B + %A = mul double %arg1, %arg2 + %B = add double %A, %arg3 + ret double %B } define <2 x double> @fma_vec(<2 x double> %arg1, <2 x double> %arg2, <2 x double> %arg3) { - %A = mul <2 x double> %arg1, %arg2 - %B = add <2 x double> %A, %arg3 - ret <2 x double> %B + %A = mul <2 x double> %arg1, %arg2 + %B = add <2 x double> %A, %arg3 + ret <2 x double> %B } define double @fms(double %arg1, double %arg2, double %arg3) { - %A = mul double %arg1, %arg2 - %B = sub double %A, %arg3 - ret double %B + %A = mul double %arg1, %arg2 + %B = sub double %A, %arg3 + ret double %B } define <2 x double> @fms_vec(<2 x double> %arg1, <2 x double> %arg2, <2 x double> %arg3) { - %A = mul <2 x double> %arg1, %arg2 - %B = sub <2 x double> %A, %arg3 - ret <2 x double> %B + %A = mul <2 x double> %arg1, %arg2 + %B = sub <2 x double> %A, %arg3 + ret <2 x double> %B } ; - (a * b - c) define double @d_fnms_1(double %arg1, double %arg2, double %arg3) { - %A = mul double %arg1, %arg2 - %B = sub double %A, %arg3 - %C = sub double -0.000000e+00, %B ; [#uses=1] - ret double %C + %A = mul double %arg1, %arg2 + %B = sub double %A, %arg3 + %C = sub double -0.000000e+00, %B ; [#uses=1] + ret double %C } ; Annother way of getting fnms ; - ( a * b ) + c => c - (a * b) define double @d_fnms_2(double %arg1, double %arg2, double %arg3) { - %A = mul double %arg1, %arg2 - %B = sub double %arg3, %A - ret double %B + %A = mul double %arg1, %arg2 + %B = sub double %arg3, %A + ret double %B } ; FNMS: - (a * b - c) => c - (a * b) define <2 x double> @d_fnms_vec_1(<2 x double> %arg1, <2 x double> %arg2, <2 x double> %arg3) { - %A = mul <2 x double> %arg1, %arg2 - %B = sub <2 x double> %arg3, %A ; - ret <2 x double> %B + %A = mul <2 x double> %arg1, %arg2 + %B = sub <2 x double> %arg3, %A ; + ret <2 x double> %B } ; Another way to get fnms using a constant vector ; - ( a * b - c) define <2 x double> @d_fnms_vec_2(<2 x double> %arg1, <2 x double> %arg2, <2 x double> %arg3) { - %A = mul <2 x double> %arg1, %arg2 ; <<2 x double>> [#uses=1] - %B = sub <2 x double> %A, %arg3 ; <<2 x double>> [#uses=1] - %C = sub <2 x double> < double -0.00000e+00, double -0.00000e+00 >, %B - ret <2 x double> %C + %A = mul <2 x double> %arg1, %arg2 ; <<2 x double>> [#uses=1] + %B = sub <2 x double> %A, %arg3 ; <<2 x double>> [#uses=1] + %C = sub <2 x double> < double -0.00000e+00, double -0.00000e+00 >, %B + ret <2 x double> %C } ;define double @fdiv_1(double %arg1, double %arg2) { -; %A = fdiv double %arg1, %arg2 ; [#uses=1] -; ret double %A +; %A = fdiv double %arg1, %arg2 ; [#uses=1] +; ret double %A ;} Modified: llvm/trunk/test/CodeGen/CellSPU/eqv.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/eqv.ll?rev=47972&r1=47971&r2=47972&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/CellSPU/eqv.ll (original) +++ llvm/trunk/test/CodeGen/CellSPU/eqv.ll Wed Mar 5 17:00:19 2008 @@ -14,139 +14,139 @@ target triple = "spu" define <4 x i32> @equiv_v4i32_1(<4 x i32> %arg1, <4 x i32> %arg2) { - %A = and <4 x i32> %arg1, %arg2 ; <<4 x i32>> [#uses=1] - %B = or <4 x i32> %arg1, %arg2 ; <<4 x i32>> [#uses=1] - %Bnot = xor <4 x i32> %B, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>> [#uses=1] - %C = or <4 x i32> %A, %Bnot ; <<4 x i32>> [#uses=1] - ret <4 x i32> %C + %A = and <4 x i32> %arg1, %arg2 + %B = or <4 x i32> %arg1, %arg2 + %Bnot = xor <4 x i32> %B, < i32 -1, i32 -1, i32 -1, i32 -1 > + %C = or <4 x i32> %A, %Bnot + ret <4 x i32> %C } define <4 x i32> @equiv_v4i32_2(<4 x i32> %arg1, <4 x i32> %arg2) { - %B = or <4 x i32> %arg1, %arg2 ; <<4 x i32>> [#uses=1] - %Bnot = xor <4 x i32> %B, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>> [#uses=1] - %A = and <4 x i32> %arg1, %arg2 ; <<4 x i32>> [#uses=1] - %C = or <4 x i32> %A, %Bnot ; <<4 x i32>> [#uses=1] - ret <4 x i32> %C + %B = or <4 x i32> %arg1, %arg2 ; <<4 x i32>> [#uses=1] + %Bnot = xor <4 x i32> %B, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>> [#uses=1] + %A = and <4 x i32> %arg1, %arg2 ; <<4 x i32>> [#uses=1] + %C = or <4 x i32> %A, %Bnot ; <<4 x i32>> [#uses=1] + ret <4 x i32> %C } define <4 x i32> @equiv_v4i32_3(<4 x i32> %arg1, <4 x i32> %arg2) { - %B = or <4 x i32> %arg1, %arg2 ; <<4 x i32>> [#uses=1] - %A = and <4 x i32> %arg1, %arg2 ; <<4 x i32>> [#uses=1] - %Bnot = xor <4 x i32> %B, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>> [#uses=1] - %C = or <4 x i32> %A, %Bnot ; <<4 x i32>> [#uses=1] - ret <4 x i32> %C + %B = or <4 x i32> %arg1, %arg2 ; <<4 x i32>> [#uses=1] + %A = and <4 x i32> %arg1, %arg2 ; <<4 x i32>> [#uses=1] + %Bnot = xor <4 x i32> %B, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>> [#uses=1] + %C = or <4 x i32> %A, %Bnot ; <<4 x i32>> [#uses=1] + ret <4 x i32> %C } define <4 x i32> @equiv_v4i32_4(<4 x i32> %arg1, <4 x i32> %arg2) { - %arg2not = xor <4 x i32> %arg2, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>> [#uses=1] - %C = xor <4 x i32> %arg1, %arg2not - ret <4 x i32> %C + %arg2not = xor <4 x i32> %arg2, < i32 -1, i32 -1, i32 -1, i32 -1 > + %C = xor <4 x i32> %arg1, %arg2not + ret <4 x i32> %C } define i32 @equiv_i32_1(i32 %arg1, i32 %arg2) { - %A = and i32 %arg1, %arg2 ; [#uses=1] - %B = or i32 %arg1, %arg2 ; [#uses=1] - %Bnot = xor i32 %B, -1 ; [#uses=1] - %C = or i32 %A, %Bnot ; [#uses=1] - ret i32 %C + %A = and i32 %arg1, %arg2 ; [#uses=1] + %B = or i32 %arg1, %arg2 ; [#uses=1] + %Bnot = xor i32 %B, -1 ; [#uses=1] + %C = or i32 %A, %Bnot ; [#uses=1] + ret i32 %C } define i32 @equiv_i32_2(i32 %arg1, i32 %arg2) { - %B = or i32 %arg1, %arg2 ; [#uses=1] - %Bnot = xor i32 %B, -1 ; [#uses=1] - %A = and i32 %arg1, %arg2 ; [#uses=1] - %C = or i32 %A, %Bnot ; [#uses=1] - ret i32 %C + %B = or i32 %arg1, %arg2 ; [#uses=1] + %Bnot = xor i32 %B, -1 ; [#uses=1] + %A = and i32 %arg1, %arg2 ; [#uses=1] + %C = or i32 %A, %Bnot ; [#uses=1] + ret i32 %C } define i32 @equiv_i32_3(i32 %arg1, i32 %arg2) { - %B = or i32 %arg1, %arg2 ; [#uses=1] - %A = and i32 %arg1, %arg2 ; [#uses=1] - %Bnot = xor i32 %B, -1 ; [#uses=1] - %C = or i32 %A, %Bnot ; [#uses=1] - ret i32 %C + %B = or i32 %arg1, %arg2 ; [#uses=1] + %A = and i32 %arg1, %arg2 ; [#uses=1] + %Bnot = xor i32 %B, -1 ; [#uses=1] + %C = or i32 %A, %Bnot ; [#uses=1] + ret i32 %C } define i32 @equiv_i32_4(i32 %arg1, i32 %arg2) { - %arg2not = xor i32 %arg2, -1 - %C = xor i32 %arg1, %arg2not - ret i32 %C + %arg2not = xor i32 %arg2, -1 + %C = xor i32 %arg1, %arg2not + ret i32 %C } define i32 @equiv_i32_5(i32 %arg1, i32 %arg2) { - %arg1not = xor i32 %arg1, -1 - %C = xor i32 %arg2, %arg1not - ret i32 %C + %arg1not = xor i32 %arg1, -1 + %C = xor i32 %arg2, %arg1not + ret i32 %C } define i16 @equiv_i16_1(i16 signext %arg1, i16 signext %arg2) signext { - %A = and i16 %arg1, %arg2 ; [#uses=1] - %B = or i16 %arg1, %arg2 ; [#uses=1] - %Bnot = xor i16 %B, -1 ; [#uses=1] - %C = or i16 %A, %Bnot ; [#uses=1] - ret i16 %C + %A = and i16 %arg1, %arg2 ; [#uses=1] + %B = or i16 %arg1, %arg2 ; [#uses=1] + %Bnot = xor i16 %B, -1 ; [#uses=1] + %C = or i16 %A, %Bnot ; [#uses=1] + ret i16 %C } define i16 @equiv_i16_2(i16 signext %arg1, i16 signext %arg2) signext { - %B = or i16 %arg1, %arg2 ; [#uses=1] - %Bnot = xor i16 %B, -1 ; [#uses=1] - %A = and i16 %arg1, %arg2 ; [#uses=1] - %C = or i16 %A, %Bnot ; [#uses=1] - ret i16 %C + %B = or i16 %arg1, %arg2 ; [#uses=1] + %Bnot = xor i16 %B, -1 ; [#uses=1] + %A = and i16 %arg1, %arg2 ; [#uses=1] + %C = or i16 %A, %Bnot ; [#uses=1] + ret i16 %C } define i16 @equiv_i16_3(i16 signext %arg1, i16 signext %arg2) signext { - %B = or i16 %arg1, %arg2 ; [#uses=1] - %A = and i16 %arg1, %arg2 ; [#uses=1] - %Bnot = xor i16 %B, -1 ; [#uses=1] - %C = or i16 %A, %Bnot ; [#uses=1] - ret i16 %C + %B = or i16 %arg1, %arg2 ; [#uses=1] + %A = and i16 %arg1, %arg2 ; [#uses=1] + %Bnot = xor i16 %B, -1 ; [#uses=1] + %C = or i16 %A, %Bnot ; [#uses=1] + ret i16 %C } define i8 @equiv_i8_1(i8 signext %arg1, i8 signext %arg2) signext { - %A = and i8 %arg1, %arg2 ; [#uses=1] - %B = or i8 %arg1, %arg2 ; [#uses=1] - %Bnot = xor i8 %B, -1 ; [#uses=1] - %C = or i8 %A, %Bnot ; [#uses=1] - ret i8 %C + %A = and i8 %arg1, %arg2 ; [#uses=1] + %B = or i8 %arg1, %arg2 ; [#uses=1] + %Bnot = xor i8 %B, -1 ; [#uses=1] + %C = or i8 %A, %Bnot ; [#uses=1] + ret i8 %C } define i8 @equiv_i8_2(i8 signext %arg1, i8 signext %arg2) signext { - %B = or i8 %arg1, %arg2 ; [#uses=1] - %Bnot = xor i8 %B, -1 ; [#uses=1] - %A = and i8 %arg1, %arg2 ; [#uses=1] - %C = or i8 %A, %Bnot ; [#uses=1] - ret i8 %C + %B = or i8 %arg1, %arg2 ; [#uses=1] + %Bnot = xor i8 %B, -1 ; [#uses=1] + %A = and i8 %arg1, %arg2 ; [#uses=1] + %C = or i8 %A, %Bnot ; [#uses=1] + ret i8 %C } define i8 @equiv_i8_3(i8 signext %arg1, i8 signext %arg2) signext { - %B = or i8 %arg1, %arg2 ; [#uses=1] - %A = and i8 %arg1, %arg2 ; [#uses=1] - %Bnot = xor i8 %B, -1 ; [#uses=1] - %C = or i8 %A, %Bnot ; [#uses=1] - ret i8 %C + %B = or i8 %arg1, %arg2 ; [#uses=1] + %A = and i8 %arg1, %arg2 ; [#uses=1] + %Bnot = xor i8 %B, -1 ; [#uses=1] + %C = or i8 %A, %Bnot ; [#uses=1] + ret i8 %C } define i8 @equiv_u8_1(i8 zeroext %arg1, i8 zeroext %arg2) zeroext { - %A = and i8 %arg1, %arg2 ; [#uses=1] - %B = or i8 %arg1, %arg2 ; [#uses=1] - %Bnot = xor i8 %B, -1 ; [#uses=1] - %C = or i8 %A, %Bnot ; [#uses=1] - ret i8 %C + %A = and i8 %arg1, %arg2 ; [#uses=1] + %B = or i8 %arg1, %arg2 ; [#uses=1] + %Bnot = xor i8 %B, -1 ; [#uses=1] + %C = or i8 %A, %Bnot ; [#uses=1] + ret i8 %C } define i8 @equiv_u8_2(i8 zeroext %arg1, i8 zeroext %arg2) zeroext { - %B = or i8 %arg1, %arg2 ; [#uses=1] - %Bnot = xor i8 %B, -1 ; [#uses=1] - %A = and i8 %arg1, %arg2 ; [#uses=1] - %C = or i8 %A, %Bnot ; [#uses=1] - ret i8 %C + %B = or i8 %arg1, %arg2 ; [#uses=1] + %Bnot = xor i8 %B, -1 ; [#uses=1] + %A = and i8 %arg1, %arg2 ; [#uses=1] + %C = or i8 %A, %Bnot ; [#uses=1] + ret i8 %C } define i8 @equiv_u8_3(i8 zeroext %arg1, i8 zeroext %arg2) zeroext { - %B = or i8 %arg1, %arg2 ; [#uses=1] - %A = and i8 %arg1, %arg2 ; [#uses=1] - %Bnot = xor i8 %B, -1 ; [#uses=1] - %C = or i8 %A, %Bnot ; [#uses=1] - ret i8 %C + %B = or i8 %arg1, %arg2 ; [#uses=1] + %A = and i8 %arg1, %arg2 ; [#uses=1] + %Bnot = xor i8 %B, -1 ; [#uses=1] + %C = or i8 %A, %Bnot ; [#uses=1] + ret i8 %C } Modified: llvm/trunk/test/CodeGen/CellSPU/fcmp.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/fcmp.ll?rev=47972&r1=47971&r2=47972&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/CellSPU/fcmp.ll (original) +++ llvm/trunk/test/CodeGen/CellSPU/fcmp.ll Wed Mar 5 17:00:19 2008 @@ -10,13 +10,13 @@ declare float @fabsf(float) define i1 @fcmp_eq(float %arg1, float %arg2) { - %A = fcmp oeq float %arg1, %arg2 ; [#uses=1] - ret i1 %A + %A = fcmp oeq float %arg1, %arg2 ; [#uses=1] + ret i1 %A } define i1 @fcmp_mag_eq(float %arg1, float %arg2) { - %A = call float @fabsf(float %arg1) ; [#uses=1] - %B = call float @fabsf(float %arg2) ; [#uses=1] - %C = fcmp oeq float %A, %B ; [#uses=1] - ret i1 %C + %A = call float @fabsf(float %arg1) ; [#uses=1] + %B = call float @fabsf(float %arg2) ; [#uses=1] + %C = fcmp oeq float %A, %B ; [#uses=1] + ret i1 %C } Modified: llvm/trunk/test/CodeGen/CellSPU/fdiv.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/fdiv.ll?rev=47972&r1=47971&r2=47972&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/CellSPU/fdiv.ll (original) +++ llvm/trunk/test/CodeGen/CellSPU/fdiv.ll Wed Mar 5 17:00:19 2008 @@ -10,11 +10,11 @@ target triple = "spu" define float @fdiv32(float %arg1, float %arg2) { - %A = fdiv float %arg1, %arg2 - ret float %A + %A = fdiv float %arg1, %arg2 + ret float %A } define <4 x float> @fdiv_v4f32(<4 x float> %arg1, <4 x float> %arg2) { - %A = fdiv <4 x float> %arg1, %arg2 - ret <4 x float> %A + %A = fdiv <4 x float> %arg1, %arg2 + ret <4 x float> %A } Modified: llvm/trunk/test/CodeGen/CellSPU/fneg-fabs.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/fneg-fabs.ll?rev=47972&r1=47971&r2=47972&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/CellSPU/fneg-fabs.ll (original) +++ llvm/trunk/test/CodeGen/CellSPU/fneg-fabs.ll Wed Mar 5 17:00:19 2008 @@ -8,24 +8,24 @@ target triple = "spu" define double @fneg_dp(double %X) { - %Y = sub double -0.000000e+00, %X - ret double %Y + %Y = sub double -0.000000e+00, %X + ret double %Y } define <2 x double> @fneg_dp_vec(<2 x double> %X) { - %Y = sub <2 x double> < double -0.0000e+00, double -0.0000e+00 >, %X - ret <2 x double> %Y + %Y = sub <2 x double> < double -0.0000e+00, double -0.0000e+00 >, %X + ret <2 x double> %Y } define float @fneg_sp(float %X) { - %Y = sub float -0.000000e+00, %X - ret float %Y + %Y = sub float -0.000000e+00, %X + ret float %Y } define <4 x float> @fneg_sp_vec(<4 x float> %X) { - %Y = sub <4 x float> , %X - ret <4 x float> %Y + ret <4 x float> %Y } declare double @fabs(double) @@ -33,11 +33,11 @@ declare float @fabsf(float) define double @fabs_dp(double %X) { - %Y = call double @fabs( double %X ) ; [#uses=1] - ret double %Y + %Y = call double @fabs( double %X ) ; [#uses=1] + ret double %Y } define float @fabs_sp(float %X) { - %Y = call float @fabsf( float %X ) ; [#uses=1] - ret float %Y + %Y = call float @fabsf( float %X ) ; [#uses=1] + ret float %Y } Modified: llvm/trunk/test/CodeGen/CellSPU/immed16.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/immed16.ll?rev=47972&r1=47971&r2=47972&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/CellSPU/immed16.ll (original) +++ llvm/trunk/test/CodeGen/CellSPU/immed16.ll Wed Mar 5 17:00:19 2008 @@ -5,31 +5,31 @@ define i16 @test_1() { %x = alloca i16, align 16 - store i16 419, i16* %x ;; ILH via pattern + store i16 419, i16* %x ;; ILH via pattern ret i16 0 } define i16 @test_2() { %x = alloca i16, align 16 - store i16 1023, i16* %x ;; ILH via pattern + store i16 1023, i16* %x ;; ILH via pattern ret i16 0 } define i16 @test_3() { %x = alloca i16, align 16 - store i16 -1023, i16* %x ;; ILH via pattern + store i16 -1023, i16* %x ;; ILH via pattern ret i16 0 } define i16 @test_4() { %x = alloca i16, align 16 - store i16 32767, i16* %x ;; ILH via pattern + store i16 32767, i16* %x ;; ILH via pattern ret i16 0 } define i16 @test_5() { %x = alloca i16, align 16 - store i16 -32768, i16* %x ;; ILH via pattern + store i16 -32768, i16* %x ;; ILH via pattern ret i16 0 } Modified: llvm/trunk/test/CodeGen/CellSPU/immed32.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/immed32.ll?rev=47972&r1=47971&r2=47972&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/CellSPU/immed32.ll (original) +++ llvm/trunk/test/CodeGen/CellSPU/immed32.ll Wed Mar 5 17:00:19 2008 @@ -16,57 +16,57 @@ target triple = "spu" define i32 @test_1() { - ret i32 4784128 ;; ILHU via pattern (0x49000) + ret i32 4784128 ;; ILHU via pattern (0x49000) } define i32 @test_2() { - ret i32 5308431 ;; ILHU/IOHL via pattern (0x5100f) + ret i32 5308431 ;; ILHU/IOHL via pattern (0x5100f) } define i32 @test_3() { - ret i32 511 ;; IL via pattern + ret i32 511 ;; IL via pattern } define i32 @test_4() { - ret i32 -512 ;; IL via pattern + ret i32 -512 ;; IL via pattern } ;; double float floatval ;; 0x4005bf0a80000000 0x402d|f854 2.718282 define float @float_const_1() { - ret float 0x4005BF0A80000000 ;; ILHU/IOHL + ret float 0x4005BF0A80000000 ;; ILHU/IOHL } ;; double float floatval ;; 0x3810000000000000 0x0080|0000 0.000000 define float @float_const_2() { - ret float 0x3810000000000000 ;; IL 128 + ret float 0x3810000000000000 ;; IL 128 } ;; double float floatval ;; 0x47efffffe0000000 0x7f7f|ffff NaN define float @float_const_3() { - ret float 0x47EFFFFFE0000000 ;; ILHU/IOHL via pattern + ret float 0x47EFFFFFE0000000 ;; ILHU/IOHL via pattern } ;; double float floatval ;; 0x400921fb60000000 0x4049|0fdb 3.141593 define float @float_const_4() { - ret float 0x400921FB60000000 ;; ILHU/IOHL via pattern + ret float 0x400921FB60000000 ;; ILHU/IOHL via pattern } ;; double float floatval ;; 0xbff6a09e60000000 0xbfb5|04f3 -1.414214 define float @float_const_5() { - ret float 0xBFF6A09E60000000 ;; ILHU/IOHL via pattern + ret float 0xBFF6A09E60000000 ;; ILHU/IOHL via pattern } ;; double float floatval ;; 0x3ff6a09e60000000 0x3fb5|04f3 1.414214 define float @float_const_6() { - ret float 0x3FF6A09E60000000 ;; ILHU/IOHL via pattern + ret float 0x3FF6A09E60000000 ;; ILHU/IOHL via pattern } define float @float_const_7() { - ret float 0.000000e+00 ;; IL 0 via pattern + ret float 0.000000e+00 ;; IL 0 via pattern } Modified: llvm/trunk/test/CodeGen/CellSPU/immed64.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/immed64.ll?rev=47972&r1=47971&r2=47972&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/CellSPU/immed64.ll (original) +++ llvm/trunk/test/CodeGen/CellSPU/immed64.ll Wed Mar 5 17:00:19 2008 @@ -1,5 +1,6 @@ ; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s ; RUN: grep lqa %t1.s | count 13 +; RUN: grep il %t1.s | count 21 ; RUN: grep shufb %t1.s | count 13 ; RUN: grep 65520 %t1.s | count 1 ; RUN: grep 43981 %t1.s | count 1 @@ -52,6 +53,10 @@ ret i64 0 ;; IL } +define i64 @i64_const_9() { + ret i64 -1 ;; IL +} + ; 0x4005bf0a8b145769 -> ; (ILHU 0x4005 [16389]/IOHL 0xbf0a [48906]) ; (ILHU 0x8b14 [35604]/IOHL 0x5769 [22377]) Modified: llvm/trunk/test/CodeGen/CellSPU/int2fp.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/int2fp.ll?rev=47972&r1=47971&r2=47972&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/CellSPU/int2fp.ll (original) +++ llvm/trunk/test/CodeGen/CellSPU/int2fp.ll Wed Mar 5 17:00:19 2008 @@ -11,31 +11,31 @@ target triple = "spu" define float @sitofp_i32(i32 %arg1) { - %A = sitofp i32 %arg1 to float ; [#uses=1] - ret float %A + %A = sitofp i32 %arg1 to float ; [#uses=1] + ret float %A } define float @uitofp_u32(i32 %arg1) { - %A = uitofp i32 %arg1 to float ; [#uses=1] - ret float %A + %A = uitofp i32 %arg1 to float ; [#uses=1] + ret float %A } define float @sitofp_i16(i16 %arg1) { - %A = sitofp i16 %arg1 to float ; [#uses=1] - ret float %A + %A = sitofp i16 %arg1 to float ; [#uses=1] + ret float %A } define float @uitofp_i16(i16 %arg1) { - %A = uitofp i16 %arg1 to float ; [#uses=1] - ret float %A + %A = uitofp i16 %arg1 to float ; [#uses=1] + ret float %A } define float @sitofp_i8(i8 %arg1) { - %A = sitofp i8 %arg1 to float ; [#uses=1] - ret float %A + %A = sitofp i8 %arg1 to float ; [#uses=1] + ret float %A } define float @uitofp_i8(i8 %arg1) { - %A = uitofp i8 %arg1 to float ; [#uses=1] - ret float %A + %A = uitofp i8 %arg1 to float ; [#uses=1] + ret float %A } Modified: llvm/trunk/test/CodeGen/CellSPU/intrinsics_branch.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/intrinsics_branch.ll?rev=47972&r1=47971&r2=47972&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/CellSPU/intrinsics_branch.ll (original) +++ llvm/trunk/test/CodeGen/CellSPU/intrinsics_branch.ll Wed Mar 5 17:00:19 2008 @@ -36,115 +36,115 @@ define <4 x i32> @test(<4 x i32> %A) { - call <4 x i32> @llvm.spu.si.shli(<4 x i32> %A, i8 3) - %Y = bitcast <4 x i32> %1 to <4 x i32> - ret <4 x i32> %Y + call <4 x i32> @llvm.spu.si.shli(<4 x i32> %A, i8 3) + %Y = bitcast <4 x i32> %1 to <4 x i32> + ret <4 x i32> %Y } define <4 x i32> @ceqtest(<4 x i32> %A, <4 x i32> %B) { - call <4 x i32> @llvm.spu.si.ceq(<4 x i32> %A, <4 x i32> %B) - %Y = bitcast <4 x i32> %1 to <4 x i32> - ret <4 x i32> %Y + call <4 x i32> @llvm.spu.si.ceq(<4 x i32> %A, <4 x i32> %B) + %Y = bitcast <4 x i32> %1 to <4 x i32> + ret <4 x i32> %Y } define <8 x i16> @ceqhtest(<8 x i16> %A, <8 x i16> %B) { - call <8 x i16> @llvm.spu.si.ceqh(<8 x i16> %A, <8 x i16> %B) - %Y = bitcast <8 x i16> %1 to <8 x i16> - ret <8 x i16> %Y + call <8 x i16> @llvm.spu.si.ceqh(<8 x i16> %A, <8 x i16> %B) + %Y = bitcast <8 x i16> %1 to <8 x i16> + ret <8 x i16> %Y } define <16 x i8> @ceqbtest(<16 x i8> %A, <16 x i8> %B) { - call <16 x i8> @llvm.spu.si.ceqb(<16 x i8> %A, <16 x i8> %B) - %Y = bitcast <16 x i8> %1 to <16 x i8> - ret <16 x i8> %Y + call <16 x i8> @llvm.spu.si.ceqb(<16 x i8> %A, <16 x i8> %B) + %Y = bitcast <16 x i8> %1 to <16 x i8> + ret <16 x i8> %Y } define <4 x i32> @ceqitest(<4 x i32> %A) { - call <4 x i32> @llvm.spu.si.ceqi(<4 x i32> %A, i16 65) - %Y = bitcast <4 x i32> %1 to <4 x i32> - ret <4 x i32> %Y + call <4 x i32> @llvm.spu.si.ceqi(<4 x i32> %A, i16 65) + %Y = bitcast <4 x i32> %1 to <4 x i32> + ret <4 x i32> %Y } define <8 x i16> @ceqhitest(<8 x i16> %A) { - call <8 x i16> @llvm.spu.si.ceqhi(<8 x i16> %A, i16 65) - %Y = bitcast <8 x i16> %1 to <8 x i16> - ret <8 x i16> %Y + call <8 x i16> @llvm.spu.si.ceqhi(<8 x i16> %A, i16 65) + %Y = bitcast <8 x i16> %1 to <8 x i16> + ret <8 x i16> %Y } define <16 x i8> @ceqbitest(<16 x i8> %A) { - call <16 x i8> @llvm.spu.si.ceqbi(<16 x i8> %A, i8 65) - %Y = bitcast <16 x i8> %1 to <16 x i8> - ret <16 x i8> %Y + call <16 x i8> @llvm.spu.si.ceqbi(<16 x i8> %A, i8 65) + %Y = bitcast <16 x i8> %1 to <16 x i8> + ret <16 x i8> %Y } define <4 x i32> @cgttest(<4 x i32> %A, <4 x i32> %B) { - call <4 x i32> @llvm.spu.si.cgt(<4 x i32> %A, <4 x i32> %B) - %Y = bitcast <4 x i32> %1 to <4 x i32> - ret <4 x i32> %Y + call <4 x i32> @llvm.spu.si.cgt(<4 x i32> %A, <4 x i32> %B) + %Y = bitcast <4 x i32> %1 to <4 x i32> + ret <4 x i32> %Y } define <8 x i16> @cgthtest(<8 x i16> %A, <8 x i16> %B) { - call <8 x i16> @llvm.spu.si.cgth(<8 x i16> %A, <8 x i16> %B) - %Y = bitcast <8 x i16> %1 to <8 x i16> - ret <8 x i16> %Y + call <8 x i16> @llvm.spu.si.cgth(<8 x i16> %A, <8 x i16> %B) + %Y = bitcast <8 x i16> %1 to <8 x i16> + ret <8 x i16> %Y } define <16 x i8> @cgtbtest(<16 x i8> %A, <16 x i8> %B) { - call <16 x i8> @llvm.spu.si.cgtb(<16 x i8> %A, <16 x i8> %B) - %Y = bitcast <16 x i8> %1 to <16 x i8> - ret <16 x i8> %Y + call <16 x i8> @llvm.spu.si.cgtb(<16 x i8> %A, <16 x i8> %B) + %Y = bitcast <16 x i8> %1 to <16 x i8> + ret <16 x i8> %Y } define <4 x i32> @cgtitest(<4 x i32> %A) { - call <4 x i32> @llvm.spu.si.cgti(<4 x i32> %A, i16 65) - %Y = bitcast <4 x i32> %1 to <4 x i32> - ret <4 x i32> %Y + call <4 x i32> @llvm.spu.si.cgti(<4 x i32> %A, i16 65) + %Y = bitcast <4 x i32> %1 to <4 x i32> + ret <4 x i32> %Y } define <8 x i16> @cgthitest(<8 x i16> %A) { - call <8 x i16> @llvm.spu.si.cgthi(<8 x i16> %A, i16 65) - %Y = bitcast <8 x i16> %1 to <8 x i16> - ret <8 x i16> %Y + call <8 x i16> @llvm.spu.si.cgthi(<8 x i16> %A, i16 65) + %Y = bitcast <8 x i16> %1 to <8 x i16> + ret <8 x i16> %Y } define <16 x i8> @cgtbitest(<16 x i8> %A) { - call <16 x i8> @llvm.spu.si.cgtbi(<16 x i8> %A, i8 65) - %Y = bitcast <16 x i8> %1 to <16 x i8> - ret <16 x i8> %Y + call <16 x i8> @llvm.spu.si.cgtbi(<16 x i8> %A, i8 65) + %Y = bitcast <16 x i8> %1 to <16 x i8> + ret <16 x i8> %Y } define <4 x i32> @clgttest(<4 x i32> %A, <4 x i32> %B) { - call <4 x i32> @llvm.spu.si.clgt(<4 x i32> %A, <4 x i32> %B) - %Y = bitcast <4 x i32> %1 to <4 x i32> - ret <4 x i32> %Y + call <4 x i32> @llvm.spu.si.clgt(<4 x i32> %A, <4 x i32> %B) + %Y = bitcast <4 x i32> %1 to <4 x i32> + ret <4 x i32> %Y } define <8 x i16> @clgthtest(<8 x i16> %A, <8 x i16> %B) { - call <8 x i16> @llvm.spu.si.clgth(<8 x i16> %A, <8 x i16> %B) - %Y = bitcast <8 x i16> %1 to <8 x i16> - ret <8 x i16> %Y + call <8 x i16> @llvm.spu.si.clgth(<8 x i16> %A, <8 x i16> %B) + %Y = bitcast <8 x i16> %1 to <8 x i16> + ret <8 x i16> %Y } define <16 x i8> @clgtbtest(<16 x i8> %A, <16 x i8> %B) { - call <16 x i8> @llvm.spu.si.clgtb(<16 x i8> %A, <16 x i8> %B) - %Y = bitcast <16 x i8> %1 to <16 x i8> - ret <16 x i8> %Y + call <16 x i8> @llvm.spu.si.clgtb(<16 x i8> %A, <16 x i8> %B) + %Y = bitcast <16 x i8> %1 to <16 x i8> + ret <16 x i8> %Y } define <4 x i32> @clgtitest(<4 x i32> %A) { - call <4 x i32> @llvm.spu.si.clgti(<4 x i32> %A, i16 65) - %Y = bitcast <4 x i32> %1 to <4 x i32> - ret <4 x i32> %Y + call <4 x i32> @llvm.spu.si.clgti(<4 x i32> %A, i16 65) + %Y = bitcast <4 x i32> %1 to <4 x i32> + ret <4 x i32> %Y } define <8 x i16> @clgthitest(<8 x i16> %A) { - call <8 x i16> @llvm.spu.si.clgthi(<8 x i16> %A, i16 65) - %Y = bitcast <8 x i16> %1 to <8 x i16> - ret <8 x i16> %Y + call <8 x i16> @llvm.spu.si.clgthi(<8 x i16> %A, i16 65) + %Y = bitcast <8 x i16> %1 to <8 x i16> + ret <8 x i16> %Y } define <16 x i8> @clgtbitest(<16 x i8> %A) { - call <16 x i8> @llvm.spu.si.clgtbi(<16 x i8> %A, i8 65) - %Y = bitcast <16 x i8> %1 to <16 x i8> - ret <16 x i8> %Y + call <16 x i8> @llvm.spu.si.clgtbi(<16 x i8> %A, i8 65) + %Y = bitcast <16 x i8> %1 to <16 x i8> + ret <16 x i8> %Y } Modified: llvm/trunk/test/CodeGen/CellSPU/intrinsics_float.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/intrinsics_float.ll?rev=47972&r1=47971&r2=47972&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/CellSPU/intrinsics_float.ll (original) +++ llvm/trunk/test/CodeGen/CellSPU/intrinsics_float.ll Wed Mar 5 17:00:19 2008 @@ -28,15 +28,15 @@ declare <4 x float> @llvm.spu.si.fms(<4 x float>, <4 x float>, <4 x float>) define <4 x i32> @test(<4 x i32> %A) { - call <4 x i32> @llvm.spu.si.shli(<4 x i32> %A, i8 3) - %Y = bitcast <4 x i32> %1 to <4 x i32> - ret <4 x i32> %Y + call <4 x i32> @llvm.spu.si.shli(<4 x i32> %A, i8 3) + %Y = bitcast <4 x i32> %1 to <4 x i32> + ret <4 x i32> %Y } define <4 x float> @fatest(<4 x float> %A, <4 x float> %B) { - call <4 x float> @llvm.spu.si.fa(<4 x float> %A, <4 x float> %B) - %Y = bitcast <4 x float> %1 to <4 x float> - ret <4 x float> %Y + call <4 x float> @llvm.spu.si.fa(<4 x float> %A, <4 x float> %B) + %Y = bitcast <4 x float> %1 to <4 x float> + ret <4 x float> %Y } define <4 x float> @fstest(<4 x float> %A, <4 x float> %B) { @@ -46,49 +46,49 @@ } define <4 x float> @fmtest(<4 x float> %A, <4 x float> %B) { - call <4 x float> @llvm.spu.si.fm(<4 x float> %A, <4 x float> %B) - %Y = bitcast <4 x float> %1 to <4 x float> - ret <4 x float> %Y + call <4 x float> @llvm.spu.si.fm(<4 x float> %A, <4 x float> %B) + %Y = bitcast <4 x float> %1 to <4 x float> + ret <4 x float> %Y } define <4 x float> @fceqtest(<4 x float> %A, <4 x float> %B) { - call <4 x float> @llvm.spu.si.fceq(<4 x float> %A, <4 x float> %B) - %Y = bitcast <4 x float> %1 to <4 x float> - ret <4 x float> %Y + call <4 x float> @llvm.spu.si.fceq(<4 x float> %A, <4 x float> %B) + %Y = bitcast <4 x float> %1 to <4 x float> + ret <4 x float> %Y } define <4 x float> @fcmeqtest(<4 x float> %A, <4 x float> %B) { - call <4 x float> @llvm.spu.si.fcmeq(<4 x float> %A, <4 x float> %B) - %Y = bitcast <4 x float> %1 to <4 x float> - ret <4 x float> %Y + call <4 x float> @llvm.spu.si.fcmeq(<4 x float> %A, <4 x float> %B) + %Y = bitcast <4 x float> %1 to <4 x float> + ret <4 x float> %Y } define <4 x float> @fcgttest(<4 x float> %A, <4 x float> %B) { - call <4 x float> @llvm.spu.si.fcgt(<4 x float> %A, <4 x float> %B) - %Y = bitcast <4 x float> %1 to <4 x float> - ret <4 x float> %Y + call <4 x float> @llvm.spu.si.fcgt(<4 x float> %A, <4 x float> %B) + %Y = bitcast <4 x float> %1 to <4 x float> + ret <4 x float> %Y } define <4 x float> @fcmgttest(<4 x float> %A, <4 x float> %B) { - call <4 x float> @llvm.spu.si.fcmgt(<4 x float> %A, <4 x float> %B) - %Y = bitcast <4 x float> %1 to <4 x float> - ret <4 x float> %Y + call <4 x float> @llvm.spu.si.fcmgt(<4 x float> %A, <4 x float> %B) + %Y = bitcast <4 x float> %1 to <4 x float> + ret <4 x float> %Y } define <4 x float> @fmatest(<4 x float> %A, <4 x float> %B, <4 x float> %C) { - call <4 x float> @llvm.spu.si.fma(<4 x float> %A, <4 x float> %B, <4 x float> %C) - %Y = bitcast <4 x float> %1 to <4 x float> - ret <4 x float> %Y + call <4 x float> @llvm.spu.si.fma(<4 x float> %A, <4 x float> %B, <4 x float> %C) + %Y = bitcast <4 x float> %1 to <4 x float> + ret <4 x float> %Y } define <4 x float> @fnmstest(<4 x float> %A, <4 x float> %B, <4 x float> %C) { - call <4 x float> @llvm.spu.si.fnms(<4 x float> %A, <4 x float> %B, <4 x float> %C) - %Y = bitcast <4 x float> %1 to <4 x float> - ret <4 x float> %Y + call <4 x float> @llvm.spu.si.fnms(<4 x float> %A, <4 x float> %B, <4 x float> %C) + %Y = bitcast <4 x float> %1 to <4 x float> + ret <4 x float> %Y } define <4 x float> @fmstest(<4 x float> %A, <4 x float> %B, <4 x float> %C) { - call <4 x float> @llvm.spu.si.fms(<4 x float> %A, <4 x float> %B, <4 x float> %C) - %Y = bitcast <4 x float> %1 to <4 x float> - ret <4 x float> %Y + call <4 x float> @llvm.spu.si.fms(<4 x float> %A, <4 x float> %B, <4 x float> %C) + %Y = bitcast <4 x float> %1 to <4 x float> + ret <4 x float> %Y } Modified: llvm/trunk/test/CodeGen/CellSPU/intrinsics_logical.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/intrinsics_logical.ll?rev=47972&r1=47971&r2=47972&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/CellSPU/intrinsics_logical.ll (original) +++ llvm/trunk/test/CodeGen/CellSPU/intrinsics_logical.ll Wed Mar 5 17:00:19 2008 @@ -25,9 +25,9 @@ declare <4 x i32> @llvm.spu.si.nor(<4 x i32>, <4 x i32>) define <4 x i32> @andtest(<4 x i32> %A, <4 x i32> %B) { - call <4 x i32> @llvm.spu.si.and(<4 x i32> %A, <4 x i32> %B) - %Y = bitcast <4 x i32> %1 to <4 x i32> - ret <4 x i32> %Y + call <4 x i32> @llvm.spu.si.and(<4 x i32> %A, <4 x i32> %B) + %Y = bitcast <4 x i32> %1 to <4 x i32> + ret <4 x i32> %Y } define <4 x i32> @andctest(<4 x i32> %A, <4 x i32> %B) { @@ -37,13 +37,13 @@ } define <4 x i32> @anditest(<4 x i32> %A) { - call <4 x i32> @llvm.spu.si.andi(<4 x i32> %A, i16 65) - %Y = bitcast <4 x i32> %1 to <4 x i32> - ret <4 x i32> %Y + call <4 x i32> @llvm.spu.si.andi(<4 x i32> %A, i16 65) + %Y = bitcast <4 x i32> %1 to <4 x i32> + ret <4 x i32> %Y } define <8 x i16> @andhitest(<8 x i16> %A) { - call <8 x i16> @llvm.spu.si.andhi(<8 x i16> %A, i16 65) - %Y = bitcast <8 x i16> %1 to <8 x i16> - ret <8 x i16> %Y + call <8 x i16> @llvm.spu.si.andhi(<8 x i16> %A, i16 65) + %Y = bitcast <8 x i16> %1 to <8 x i16> + ret <8 x i16> %Y } Modified: llvm/trunk/test/CodeGen/CellSPU/mul_ops.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/mul_ops.ll?rev=47972&r1=47971&r2=47972&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/CellSPU/mul_ops.ll (original) +++ llvm/trunk/test/CodeGen/CellSPU/mul_ops.ll Wed Mar 5 17:00:19 2008 @@ -54,36 +54,36 @@ define i32 @mul_i32_1(i32 %arg1, i32 %arg2) { entry: - %A = mul i32 %arg2, %arg1 - ret i32 %A + %A = mul i32 %arg2, %arg1 + ret i32 %A } define i32 @mul_i32_2(i32 %arg1, i32 %arg2) { entry: - %A = mul i32 %arg1, %arg2 - ret i32 %A + %A = mul i32 %arg1, %arg2 + ret i32 %A } define i16 @mul_i16_1(i16 %arg1, i16 %arg2) { entry: - %A = mul i16 %arg2, %arg1 - ret i16 %A + %A = mul i16 %arg2, %arg1 + ret i16 %A } define i16 @mul_i16_2(i16 %arg1, i16 %arg2) { entry: - %A = mul i16 %arg1, %arg2 - ret i16 %A + %A = mul i16 %arg1, %arg2 + ret i16 %A } define i8 @mul_i8_1(i8 %arg1, i8 %arg2) { entry: - %A = mul i8 %arg2, %arg1 - ret i8 %A + %A = mul i8 %arg2, %arg1 + ret i8 %A } define i8 @mul_i8_2(i8 %arg1, i8 %arg2) { entry: - %A = mul i8 %arg1, %arg2 - ret i8 %A + %A = mul i8 %arg1, %arg2 + ret i8 %A } Modified: llvm/trunk/test/CodeGen/CellSPU/or_ops.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/or_ops.ll?rev=47972&r1=47971&r2=47972&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/CellSPU/or_ops.ll (original) +++ llvm/trunk/test/CodeGen/CellSPU/or_ops.ll Wed Mar 5 17:00:19 2008 @@ -39,33 +39,33 @@ } define i32 @or_i32_1(i32 %arg1, i32 %arg2) { - %A = or i32 %arg2, %arg1 - ret i32 %A + %A = or i32 %arg2, %arg1 + ret i32 %A } define i32 @or_i32_2(i32 %arg1, i32 %arg2) { - %A = or i32 %arg1, %arg2 - ret i32 %A + %A = or i32 %arg1, %arg2 + ret i32 %A } define i16 @or_i16_1(i16 %arg1, i16 %arg2) { - %A = or i16 %arg2, %arg1 - ret i16 %A + %A = or i16 %arg2, %arg1 + ret i16 %A } define i16 @or_i16_2(i16 %arg1, i16 %arg2) { - %A = or i16 %arg1, %arg2 - ret i16 %A + %A = or i16 %arg1, %arg2 + ret i16 %A } define i8 @or_i8_1(i8 %arg1, i8 %arg2) { - %A = or i8 %arg2, %arg1 - ret i8 %A + %A = or i8 %arg2, %arg1 + ret i8 %A } define i8 @or_i8_2(i8 %arg1, i8 %arg2) { - %A = or i8 %arg1, %arg2 - ret i8 %A + %A = or i8 %arg1, %arg2 + ret i8 %A } ; ORC instruction generation: @@ -126,57 +126,57 @@ } define i32 @orc_i32_1(i32 %arg1, i32 %arg2) { - %A = xor i32 %arg2, -1 - %B = or i32 %A, %arg1 - ret i32 %B + %A = xor i32 %arg2, -1 + %B = or i32 %A, %arg1 + ret i32 %B } define i32 @orc_i32_2(i32 %arg1, i32 %arg2) { - %A = xor i32 %arg1, -1 - %B = or i32 %A, %arg2 - ret i32 %B + %A = xor i32 %arg1, -1 + %B = or i32 %A, %arg2 + ret i32 %B } define i32 @orc_i32_3(i32 %arg1, i32 %arg2) { - %A = xor i32 %arg2, -1 - %B = or i32 %arg1, %A - ret i32 %B + %A = xor i32 %arg2, -1 + %B = or i32 %arg1, %A + ret i32 %B } define i16 @orc_i16_1(i16 %arg1, i16 %arg2) { - %A = xor i16 %arg2, -1 - %B = or i16 %A, %arg1 - ret i16 %B + %A = xor i16 %arg2, -1 + %B = or i16 %A, %arg1 + ret i16 %B } define i16 @orc_i16_2(i16 %arg1, i16 %arg2) { - %A = xor i16 %arg1, -1 - %B = or i16 %A, %arg2 - ret i16 %B + %A = xor i16 %arg1, -1 + %B = or i16 %A, %arg2 + ret i16 %B } define i16 @orc_i16_3(i16 %arg1, i16 %arg2) { - %A = xor i16 %arg2, -1 - %B = or i16 %arg1, %A - ret i16 %B + %A = xor i16 %arg2, -1 + %B = or i16 %arg1, %A + ret i16 %B } define i8 @orc_i8_1(i8 %arg1, i8 %arg2) { - %A = xor i8 %arg2, -1 - %B = or i8 %A, %arg1 - ret i8 %B + %A = xor i8 %arg2, -1 + %B = or i8 %A, %arg1 + ret i8 %B } define i8 @orc_i8_2(i8 %arg1, i8 %arg2) { - %A = xor i8 %arg1, -1 - %B = or i8 %A, %arg2 - ret i8 %B + %A = xor i8 %arg1, -1 + %B = or i8 %A, %arg2 + ret i8 %B } define i8 @orc_i8_3(i8 %arg1, i8 %arg2) { - %A = xor i8 %arg2, -1 - %B = or i8 %arg1, %A - ret i8 %B + %A = xor i8 %arg2, -1 + %B = or i8 %arg1, %A + ret i8 %B } ; ORI instruction generation (i32 data type): Modified: llvm/trunk/test/CodeGen/CellSPU/rotate_ops.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/rotate_ops.ll?rev=47972&r1=47971&r2=47972&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/CellSPU/rotate_ops.ll (original) +++ llvm/trunk/test/CodeGen/CellSPU/rotate_ops.ll Wed Mar 5 17:00:19 2008 @@ -115,45 +115,45 @@ } define i16 @rotli16(i16 %A) { - %B = shl i16 %A, 5 ; [#uses=1] - %C = lshr i16 %A, 11 ; [#uses=1] - %D = or i16 %B, %C ; [#uses=1] - ret i16 %D + %B = shl i16 %A, 5 ; [#uses=1] + %C = lshr i16 %A, 11 ; [#uses=1] + %D = or i16 %B, %C ; [#uses=1] + ret i16 %D } define i16 @rotri16(i16 %A) { - %B = lshr i16 %A, 5 ; [#uses=1] - %C = shl i16 %A, 11 ; [#uses=1] - %D = or i16 %B, %C ; [#uses=1] - ret i16 %D + %B = lshr i16 %A, 5 ; [#uses=1] + %C = shl i16 %A, 11 ; [#uses=1] + %D = or i16 %B, %C ; [#uses=1] + ret i16 %D } define i8 @rotl8(i8 %A, i8 %Amt) { - %B = shl i8 %A, %Amt ; [#uses=1] - %Amt2 = sub i8 8, %Amt ; [#uses=1] - %C = lshr i8 %A, %Amt2 ; [#uses=1] - %D = or i8 %B, %C ; [#uses=1] - ret i8 %D + %B = shl i8 %A, %Amt ; [#uses=1] + %Amt2 = sub i8 8, %Amt ; [#uses=1] + %C = lshr i8 %A, %Amt2 ; [#uses=1] + %D = or i8 %B, %C ; [#uses=1] + ret i8 %D } define i8 @rotr8(i8 %A, i8 %Amt) { - %B = lshr i8 %A, %Amt ; [#uses=1] - %Amt2 = sub i8 8, %Amt ; [#uses=1] - %C = shl i8 %A, %Amt2 ; [#uses=1] - %D = or i8 %B, %C ; [#uses=1] - ret i8 %D + %B = lshr i8 %A, %Amt ; [#uses=1] + %Amt2 = sub i8 8, %Amt ; [#uses=1] + %C = shl i8 %A, %Amt2 ; [#uses=1] + %D = or i8 %B, %C ; [#uses=1] + ret i8 %D } define i8 @rotli8(i8 %A) { - %B = shl i8 %A, 5 ; [#uses=1] - %C = lshr i8 %A, 3 ; [#uses=1] - %D = or i8 %B, %C ; [#uses=1] - ret i8 %D + %B = shl i8 %A, 5 ; [#uses=1] + %C = lshr i8 %A, 3 ; [#uses=1] + %D = or i8 %B, %C ; [#uses=1] + ret i8 %D } define i8 @rotri8(i8 %A) { - %B = lshr i8 %A, 5 ; [#uses=1] - %C = shl i8 %A, 3 ; [#uses=1] - %D = or i8 %B, %C ; [#uses=1] - ret i8 %D + %B = lshr i8 %A, 5 ; [#uses=1] + %C = shl i8 %A, 3 ; [#uses=1] + %D = or i8 %B, %C ; [#uses=1] + ret i8 %D } Modified: llvm/trunk/test/CodeGen/CellSPU/select_bits.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/select_bits.ll?rev=47972&r1=47971&r2=47972&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/CellSPU/select_bits.ll (original) +++ llvm/trunk/test/CodeGen/CellSPU/select_bits.ll Wed Mar 5 17:00:19 2008 @@ -1,296 +1,569 @@ ; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s -; RUN: grep selb %t1.s | count 160 -; RUN: grep and %t1.s | count 2 -; RUN: grep xsbh %t1.s | count 1 -; RUN: grep xshw %t1.s | count 2 +; RUN: grep selb %t1.s | count 280 + target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128" target triple = "spu" -define <16 x i8> @selb_v16i8_1(<16 x i8> %arg1, <16 x i8> %arg2, <16 x i8> %arg3) { - %A = xor <16 x i8> %arg3, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, - i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, - i8 -1, i8 -1, i8 -1, i8 -1 > - %B = and <16 x i8> %A, %arg1 ; <<16 x i8>> [#uses=1] - %C = and <16 x i8> %arg2, %arg3 ; <<16 x i8>> [#uses=1] - %D = or <16 x i8> %B, %C ; <<16 x i8>> [#uses=1] - ret <16 x i8> %D -} - -define <16 x i8> @selb_v16i8_11(<16 x i8> %arg1, <16 x i8> %arg2, <16 x i8> %arg3) { - %A = xor <16 x i8> %arg3, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, - i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, - i8 -1, i8 -1, i8 -1, i8 -1 > - %B = and <16 x i8> %arg1, %A ; <<16 x i8>> [#uses=1] - %C = and <16 x i8> %arg3, %arg2 ; <<16 x i8>> [#uses=1] - %D = or <16 x i8> %B, %C ; <<16 x i8>> [#uses=1] - ret <16 x i8> %D -} - -define <16 x i8> @selb_v16i8_12(<16 x i8> %arg1, <16 x i8> %arg2, <16 x i8> %arg3) { - %A = xor <16 x i8> %arg3, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, - i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, - i8 -1, i8 -1, i8 -1, i8 -1 > - %B = and <16 x i8> %arg1, %A ; <<16 x i8>> [#uses=1] - %C = and <16 x i8> %arg2, %arg3 ; <<16 x i8>> [#uses=1] - %D = or <16 x i8> %B, %C ; <<16 x i8>> [#uses=1] - ret <16 x i8> %D -} - -define <16 x i8> @selb_v16i8_13(<16 x i8> %arg1, <16 x i8> %arg2, <16 x i8> %arg3) { - %A = xor <16 x i8> %arg3, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, - i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, - i8 -1, i8 -1, i8 -1, i8 -1 > - %B = and <16 x i8> %A, %arg1 ; <<16 x i8>> [#uses=1] - %C = and <16 x i8> %arg2, %arg3 ; <<16 x i8>> [#uses=1] - %D = or <16 x i8> %B, %C ; <<16 x i8>> [#uses=1] - ret <16 x i8> %D -} - -define <16 x i8> @selb_v16i8_2(<16 x i8> %arg1, <16 x i8> %arg2, <16 x i8> %arg3) { - %A = xor <16 x i8> %arg1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, - i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, - i8 -1, i8 -1, i8 -1, i8 -1 > - %B = and <16 x i8> %A, %arg2 ; <<16 x i8>> [#uses=1] - %C = and <16 x i8> %arg3, %arg1 ; <<16 x i8>> [#uses=1] - %D = or <16 x i8> %B, %C ; <<16 x i8>> [#uses=1] - ret <16 x i8> %D -} - -define <16 x i8> @selb_v16i8_21(<16 x i8> %arg1, <16 x i8> %arg2, <16 x i8> %arg3) { - %A = xor <16 x i8> %arg1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, - i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, - i8 -1, i8 -1, i8 -1, i8 -1 > - %B = and <16 x i8> %arg2, %A ; <<16 x i8>> [#uses=1] - %C = and <16 x i8> %arg3, %arg1 ; <<16 x i8>> [#uses=1] - %D = or <16 x i8> %B, %C ; <<16 x i8>> [#uses=1] - ret <16 x i8> %D -} - -define <16 x i8> @selb_v16i8_3(<16 x i8> %arg1, <16 x i8> %arg2, <16 x i8> %arg3) { - %A = xor <16 x i8> %arg2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, - i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, - i8 -1, i8 -1, i8 -1, i8 -1 > - %B = and <16 x i8> %A, %arg1 ; <<16 x i8>> [#uses=1] - %C = and <16 x i8> %arg3, %arg2 ; <<16 x i8>> [#uses=1] - %D = or <16 x i8> %B, %C ; <<16 x i8>> [#uses=1] - ret <16 x i8> %D -} - -define <16 x i8> @selb_v16i8_4(<16 x i8> %arg1, <16 x i8> %arg2, <16 x i8> %arg3) { - %C = and <16 x i8> %arg3, %arg2 ; <<16 x i8>> [#uses=1] - %A = xor <16 x i8> %arg2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, - i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, - i8 -1, i8 -1, i8 -1, i8 -1 > - %B = and <16 x i8> %A, %arg1 ; <<16 x i8>> [#uses=1] - %D = or <16 x i8> %B, %C ; <<16 x i8>> [#uses=1] - ret <16 x i8> %D -} - -define <16 x i8> @selb_v16i8_41(<16 x i8> %arg1, <16 x i8> %arg2, <16 x i8> %arg3) { - %C = and <16 x i8> %arg2, %arg3 ; <<16 x i8>> [#uses=1] - %A = xor <16 x i8> %arg2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, - i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, - i8 -1, i8 -1, i8 -1, i8 -1 > - %B = and <16 x i8> %arg1, %A ; <<16 x i8>> [#uses=1] - %D = or <16 x i8> %C, %B ; <<16 x i8>> [#uses=1] - ret <16 x i8> %D -} - -define <16 x i8> @selb_v16i8_42(<16 x i8> %arg1, <16 x i8> %arg2, <16 x i8> %arg3) { - %C = and <16 x i8> %arg2, %arg3 ; <<16 x i8>> [#uses=1] - %A = xor <16 x i8> %arg2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, - i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, - i8 -1, i8 -1, i8 -1, i8 -1 > - %B = and <16 x i8> %A, %arg1 ; <<16 x i8>> [#uses=1] - %D = or <16 x i8> %C, %B ; <<16 x i8>> [#uses=1] - ret <16 x i8> %D -} - -define <16 x i8> @selb_v16i8_5(<16 x i8> %arg1, <16 x i8> %arg2, <16 x i8> %arg3) { - %C = and <16 x i8> %arg2, %arg1 ; <<16 x i8>> [#uses=1] - %A = xor <16 x i8> %arg1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, - i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, - i8 -1, i8 -1, i8 -1, i8 -1 > - %B = and <16 x i8> %A, %arg3 ; <<16 x i8>> [#uses=1] - %D = or <16 x i8> %B, %C ; <<16 x i8>> [#uses=1] - ret <16 x i8> %D -} - -define <8 x i16> @selb_v8i16_1(<8 x i16> %arg1, <8 x i16> %arg2, <8 x i16> %arg3) { - %A = xor <8 x i16> %arg3, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, - i16 -1, i16 -1 > - %B = and <8 x i16> %A, %arg1 ; <<8 x i16>> [#uses=1] - %C = and <8 x i16> %arg2, %arg3 ; <<8 x i16>> [#uses=1] - %D = or <8 x i16> %B, %C ; <<8 x i16>> [#uses=1] - ret <8 x i16> %D -} - -define <8 x i16> @selb_v8i16_11(<8 x i16> %arg1, <8 x i16> %arg2, <8 x i16> %arg3) { - %A = xor <8 x i16> %arg3, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, - i16 -1, i16 -1 > - %B = and <8 x i16> %arg1, %A ; <<8 x i16>> [#uses=1] - %C = and <8 x i16> %arg3, %arg2 ; <<8 x i16>> [#uses=1] - %D = or <8 x i16> %B, %C ; <<8 x i16>> [#uses=1] - ret <8 x i16> %D -} - -define <8 x i16> @selb_v8i16_12(<8 x i16> %arg1, <8 x i16> %arg2, <8 x i16> %arg3) { - %A = xor <8 x i16> %arg3, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, - i16 -1, i16 -1 > - %B = and <8 x i16> %arg1, %A ; <<8 x i16>> [#uses=1] - %C = and <8 x i16> %arg2, %arg3 ; <<8 x i16>> [#uses=1] - %D = or <8 x i16> %B, %C ; <<8 x i16>> [#uses=1] - ret <8 x i16> %D -} - -define <8 x i16> @selb_v8i16_13(<8 x i16> %arg1, <8 x i16> %arg2, <8 x i16> %arg3) { - %A = xor <8 x i16> %arg3, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, - i16 -1, i16 -1 > - %B = and <8 x i16> %A, %arg1 ; <<8 x i16>> [#uses=1] - %C = and <8 x i16> %arg2, %arg3 ; <<8 x i16>> [#uses=1] - %D = or <8 x i16> %B, %C ; <<8 x i16>> [#uses=1] - ret <8 x i16> %D -} - -define <8 x i16> @selb_v8i16_2(<8 x i16> %arg1, <8 x i16> %arg2, <8 x i16> %arg3) { - %A = xor <8 x i16> %arg1, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, - i16 -1, i16 -1 > - %B = and <8 x i16> %A, %arg2 ; <<8 x i16>> [#uses=1] - %C = and <8 x i16> %arg3, %arg1 ; <<8 x i16>> [#uses=1] - %D = or <8 x i16> %B, %C ; <<8 x i16>> [#uses=1] - ret <8 x i16> %D -} - -define <8 x i16> @selb_v8i16_21(<8 x i16> %arg1, <8 x i16> %arg2, <8 x i16> %arg3) { - %A = xor <8 x i16> %arg1, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, - i16 -1, i16 -1 > - %B = and <8 x i16> %arg2, %A ; <<8 x i16>> [#uses=1] - %C = and <8 x i16> %arg3, %arg1 ; <<8 x i16>> [#uses=1] - %D = or <8 x i16> %B, %C ; <<8 x i16>> [#uses=1] - ret <8 x i16> %D -} - -define <8 x i16> @selb_v8i16_3(<8 x i16> %arg1, <8 x i16> %arg2, <8 x i16> %arg3) { - %A = xor <8 x i16> %arg2, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, - i16 -1, i16 -1 > - %B = and <8 x i16> %A, %arg1 ; <<8 x i16>> [#uses=1] - %C = and <8 x i16> %arg3, %arg2 ; <<8 x i16>> [#uses=1] - %D = or <8 x i16> %B, %C ; <<8 x i16>> [#uses=1] - ret <8 x i16> %D -} - -define <8 x i16> @selb_v8i16_4(<8 x i16> %arg1, <8 x i16> %arg2, <8 x i16> %arg3) { - %C = and <8 x i16> %arg3, %arg2 ; <<8 x i16>> [#uses=1] - %A = xor <8 x i16> %arg2, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, - i16 -1, i16 -1 > - %B = and <8 x i16> %A, %arg1 ; <<8 x i16>> [#uses=1] - %D = or <8 x i16> %B, %C ; <<8 x i16>> [#uses=1] - ret <8 x i16> %D -} - -define <8 x i16> @selb_v8i16_41(<8 x i16> %arg1, <8 x i16> %arg2, <8 x i16> %arg3) { - %C = and <8 x i16> %arg2, %arg3 ; <<8 x i16>> [#uses=1] - %A = xor <8 x i16> %arg2, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, - i16 -1, i16 -1 > - %B = and <8 x i16> %arg1, %A ; <<8 x i16>> [#uses=1] - %D = or <8 x i16> %C, %B ; <<8 x i16>> [#uses=1] - ret <8 x i16> %D -} - -define <8 x i16> @selb_v8i16_42(<8 x i16> %arg1, <8 x i16> %arg2, <8 x i16> %arg3) { - %C = and <8 x i16> %arg2, %arg3 ; <<8 x i16>> [#uses=1] - %A = xor <8 x i16> %arg2, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, - i16 -1, i16 -1 > - %B = and <8 x i16> %A, %arg1 ; <<8 x i16>> [#uses=1] - %D = or <8 x i16> %C, %B ; <<8 x i16>> [#uses=1] - ret <8 x i16> %D -} - -define <8 x i16> @selb_v8i16_5(<8 x i16> %arg1, <8 x i16> %arg2, <8 x i16> %arg3) { - %C = and <8 x i16> %arg2, %arg1 ; <<8 x i16>> [#uses=1] - %A = xor <8 x i16> %arg1, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, - i16 -1, i16 -1 > - %B = and <8 x i16> %A, %arg3 ; <<8 x i16>> [#uses=1] - %D = or <8 x i16> %B, %C ; <<8 x i16>> [#uses=1] - ret <8 x i16> %D -} - -define <4 x i32> @selb_v4i32_1(<4 x i32> %arg1, <4 x i32> %arg2, <4 x i32> %arg3) { - %tmpnot = xor <4 x i32> %arg3, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>> [#uses=1] - %tmp2 = and <4 x i32> %tmpnot, %arg1 ; <<4 x i32>> [#uses=1] - %tmp5 = and <4 x i32> %arg2, %arg3 ; <<4 x i32>> [#uses=1] - %tmp6 = or <4 x i32> %tmp2, %tmp5 ; <<4 x i32>> [#uses=1] - ret <4 x i32> %tmp6 -} - -define <4 x i32> @selb_v4i32_2(<4 x i32> %arg1, <4 x i32> %arg2, <4 x i32> %arg3) { - %tmpnot = xor <4 x i32> %arg3, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>> [#uses=1] - %tmp2 = and <4 x i32> %tmpnot, %arg1 ; <<4 x i32>> [#uses=1] - %tmp5 = and <4 x i32> %arg2, %arg3 ; <<4 x i32>> [#uses=1] - %tmp6 = or <4 x i32> %tmp2, %tmp5 ; <<4 x i32>> [#uses=1] - ret <4 x i32> %tmp6 -} - -define <4 x i32> @selb_v4i32_3(<4 x i32> %arg1, <4 x i32> %arg2, <4 x i32> %arg3) { - %tmpnot = xor <4 x i32> %arg3, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>> [#uses=1] - %tmp2 = and <4 x i32> %tmpnot, %arg1 ; <<4 x i32>> [#uses=1] - %tmp5 = and <4 x i32> %arg3, %arg2 ; <<4 x i32>> [#uses=1] - %tmp6 = or <4 x i32> %tmp2, %tmp5 ; <<4 x i32>> [#uses=1] - ret <4 x i32> %tmp6 -} - -define <4 x i32> @selb_v4i32_4(<4 x i32> %arg1, <4 x i32> %arg2, <4 x i32> %arg3) { - %tmp2 = and <4 x i32> %arg3, %arg2 ; <<4 x i32>> [#uses=1] - %tmp3not = xor <4 x i32> %arg3, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>> [#uses=1] - %tmp5 = and <4 x i32> %tmp3not, %arg1 ; <<4 x i32>> [#uses=1] - %tmp6 = or <4 x i32> %tmp2, %tmp5 ; <<4 x i32>> [#uses=1] - ret <4 x i32> %tmp6 -} - -define <4 x i32> @selb_v4i32_5(<4 x i32> %arg1, <4 x i32> %arg2, <4 x i32> %arg3) { - %tmp2 = and <4 x i32> %arg3, %arg2 ; <<4 x i32>> [#uses=1] - %tmp3not = xor <4 x i32> %arg3, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>> [#uses=1] - %tmp5 = and <4 x i32> %tmp3not, %arg1 ; <<4 x i32>> [#uses=1] - %tmp6 = or <4 x i32> %tmp2, %tmp5 ; <<4 x i32>> [#uses=1] - ret <4 x i32> %tmp6 -} - -define i32 @selb_i32(i32 %arg1, i32 %arg2, i32 %arg3) { - %tmp1not = xor i32 %arg3, -1 ; [#uses=1] - %tmp3 = and i32 %tmp1not, %arg1 ; [#uses=1] - %tmp6 = and i32 %arg3, %arg2 ; [#uses=1] - %tmp7 = or i32 %tmp3, %tmp6 ; [#uses=1] - ret i32 %tmp7 -} - -define i16 @selb_i16(i16 signext %arg1, i16 signext %arg2, i16 signext %arg3) signext { - %tmp3 = and i16 %arg3, %arg1 ; [#uses=1] - %tmp4not = xor i16 %arg3, -1 ; [#uses=1] - %tmp6 = and i16 %tmp4not, %arg2 ; [#uses=1] - %retval1011 = or i16 %tmp3, %tmp6 ; [#uses=1] - ret i16 %retval1011 -} - -define i16 @selb_i16u(i16 zeroext %arg1, i16 zeroext %arg2, i16 zeroext %arg3) zeroext { - %tmp3 = and i16 %arg3, %arg1 ; [#uses=1] - %tmp4not = xor i16 %arg3, -1 ; [#uses=1] - %tmp6 = and i16 %tmp4not, %arg2 ; [#uses=1] - %retval1011 = or i16 %tmp3, %tmp6 ; [#uses=1] - ret i16 %retval1011 -} - -define i8 @selb_i8u(i8 zeroext %arg1, i8 zeroext %arg2, i8 zeroext %arg3) zeroext { - %tmp3 = and i8 %arg3, %arg1 ; [#uses=1] - %tmp4not = xor i8 %arg3, -1 ; [#uses=1] - %tmp6 = and i8 %tmp4not, %arg2 ; [#uses=1] - %retval1011 = or i8 %tmp3, %tmp6 ; [#uses=1] - ret i8 %retval1011 -} - -define i8 @selb_i8(i8 signext %arg1, i8 signext %arg2, i8 signext %arg3) signext { - %tmp3 = and i8 %arg3, %arg1 ; [#uses=1] - %tmp4not = xor i8 %arg3, -1 ; [#uses=1] - %tmp6 = and i8 %tmp4not, %arg2 ; [#uses=1] - %retval1011 = or i8 %tmp3, %tmp6 ; [#uses=1] - ret i8 %retval1011 +;-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ +; v2i64 +;-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ + +; (or (and rC, rB), (and (not rC), rA)) +define <2 x i64> @selb_v2i64_01(<2 x i64> %rA, <2 x i64> %rB, <2 x i64> %rC) { + %C = and <2 x i64> %rC, %rB + %A = xor <2 x i64> %rC, < i64 -1, i64 -1 > + %B = and <2 x i64> %A, %rA + %D = or <2 x i64> %C, %B + ret <2 x i64> %D +} + +; (or (and rB, rC), (and (not rC), rA)) +define <2 x i64> @selb_v2i64_02(<2 x i64> %rA, <2 x i64> %rB, <2 x i64> %rC) { + %C = and <2 x i64> %rB, %rC + %A = xor <2 x i64> %rC, < i64 -1, i64 -1 > + %B = and <2 x i64> %A, %rA + %D = or <2 x i64> %C, %B + ret <2 x i64> %D +} + +; (or (and (not rC), rA), (and rB, rC)) +define <2 x i64> @selb_v2i64_03(<2 x i64> %rA, <2 x i64> %rB, <2 x i64> %rC) { + %A = xor <2 x i64> %rC, < i64 -1, i64 -1 > + %B = and <2 x i64> %A, %rA + %C = and <2 x i64> %rB, %rC + %D = or <2 x i64> %C, %B + ret <2 x i64> %D +} + +; (or (and (not rC), rA), (and rC, rB)) +define <2 x i64> @selb_v2i64_04(<2 x i64> %rA, <2 x i64> %rB, <2 x i64> %rC) { + %A = xor <2 x i64> %rC, < i64 -1, i64 -1 > + %B = and <2 x i64> %A, %rA + %C = and <2 x i64> %rC, %rB + %D = or <2 x i64> %C, %B + ret <2 x i64> %D +} + +; (or (and rC, rB), (and rA, (not rC))) +define <2 x i64> @selb_v2i64_05(<2 x i64> %rA, <2 x i64> %rB, <2 x i64> %rC) { + %C = and <2 x i64> %rC, %rB + %A = xor <2 x i64> %rC, < i64 -1, i64 -1 > + %B = and <2 x i64> %rA, %A + %D = or <2 x i64> %C, %B + ret <2 x i64> %D +} + +; (or (and rB, rC), (and rA, (not rC))) +define <2 x i64> @selb_v2i64_06(<2 x i64> %rA, <2 x i64> %rB, <2 x i64> %rC) { + %C = and <2 x i64> %rB, %rC + %A = xor <2 x i64> %rC, < i64 -1, i64 -1 > + %B = and <2 x i64> %rA, %A + %D = or <2 x i64> %C, %B + ret <2 x i64> %D +} + +; (or (and rA, (not rC)), (and rB, rC)) +define <2 x i64> @selb_v2i64_07(<2 x i64> %rA, <2 x i64> %rB, <2 x i64> %rC) { + %A = xor <2 x i64> %rC, < i64 -1, i64 -1 > + %B = and <2 x i64> %rA, %A + %C = and <2 x i64> %rB, %rC + %D = or <2 x i64> %C, %B + ret <2 x i64> %D +} + +; (or (and rA, (not rC)), (and rC, rB)) +define <2 x i64> @selb_v2i64_08(<2 x i64> %rA, <2 x i64> %rB, <2 x i64> %rC) { + %A = xor <2 x i64> %rC, < i64 -1, i64 -1 > + %B = and <2 x i64> %rA, %A + %C = and <2 x i64> %rC, %rB + %D = or <2 x i64> %C, %B + ret <2 x i64> %D +} + +;-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ +; v4i32 +;-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ + +; (or (and rC, rB), (and (not rC), rA)) +define <4 x i32> @selb_v4i32_01(<4 x i32> %rA, <4 x i32> %rB, <4 x i32> %rC) { + %C = and <4 x i32> %rC, %rB + %A = xor <4 x i32> %rC, < i32 -1, i32 -1, i32 -1, i32 -1 > + %B = and <4 x i32> %A, %rA + %D = or <4 x i32> %C, %B + ret <4 x i32> %D +} + +; (or (and rB, rC), (and (not rC), rA)) +define <4 x i32> @selb_v4i32_02(<4 x i32> %rA, <4 x i32> %rB, <4 x i32> %rC) { + %C = and <4 x i32> %rB, %rC + %A = xor <4 x i32> %rC, < i32 -1, i32 -1, i32 -1, i32 -1 > + %B = and <4 x i32> %A, %rA + %D = or <4 x i32> %C, %B + ret <4 x i32> %D +} + +; (or (and (not rC), rA), (and rB, rC)) +define <4 x i32> @selb_v4i32_03(<4 x i32> %rA, <4 x i32> %rB, <4 x i32> %rC) { + %A = xor <4 x i32> %rC, < i32 -1, i32 -1, i32 -1, i32 -1 > + %B = and <4 x i32> %A, %rA + %C = and <4 x i32> %rB, %rC + %D = or <4 x i32> %C, %B + ret <4 x i32> %D +} + +; (or (and (not rC), rA), (and rC, rB)) +define <4 x i32> @selb_v4i32_04(<4 x i32> %rA, <4 x i32> %rB, <4 x i32> %rC) { + %A = xor <4 x i32> %rC, < i32 -1, i32 -1, i32 -1, i32 -1> + %B = and <4 x i32> %A, %rA + %C = and <4 x i32> %rC, %rB + %D = or <4 x i32> %C, %B + ret <4 x i32> %D +} + +; (or (and rC, rB), (and rA, (not rC))) +define <4 x i32> @selb_v4i32_05(<4 x i32> %rA, <4 x i32> %rB, <4 x i32> %rC) { + %C = and <4 x i32> %rC, %rB + %A = xor <4 x i32> %rC, < i32 -1, i32 -1, i32 -1, i32 -1> + %B = and <4 x i32> %rA, %A + %D = or <4 x i32> %C, %B + ret <4 x i32> %D +} + +; (or (and rB, rC), (and rA, (not rC))) +define <4 x i32> @selb_v4i32_06(<4 x i32> %rA, <4 x i32> %rB, <4 x i32> %rC) { + %C = and <4 x i32> %rB, %rC + %A = xor <4 x i32> %rC, < i32 -1, i32 -1, i32 -1, i32 -1> + %B = and <4 x i32> %rA, %A + %D = or <4 x i32> %C, %B + ret <4 x i32> %D +} + +; (or (and rA, (not rC)), (and rB, rC)) +define <4 x i32> @selb_v4i32_07(<4 x i32> %rA, <4 x i32> %rB, <4 x i32> %rC) { + %A = xor <4 x i32> %rC, < i32 -1, i32 -1, i32 -1, i32 -1> + %B = and <4 x i32> %rA, %A + %C = and <4 x i32> %rB, %rC + %D = or <4 x i32> %C, %B + ret <4 x i32> %D +} + +; (or (and rA, (not rC)), (and rC, rB)) +define <4 x i32> @selb_v4i32_08(<4 x i32> %rA, <4 x i32> %rB, <4 x i32> %rC) { + %A = xor <4 x i32> %rC, < i32 -1, i32 -1, i32 -1, i32 -1> + %B = and <4 x i32> %rA, %A + %C = and <4 x i32> %rC, %rB + %D = or <4 x i32> %C, %B + ret <4 x i32> %D +} + +;-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ +; v8i16 +;-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ + +; (or (and rC, rB), (and (not rC), rA)) +define <8 x i16> @selb_v8i16_01(<8 x i16> %rA, <8 x i16> %rB, <8 x i16> %rC) { + %C = and <8 x i16> %rC, %rB + %A = xor <8 x i16> %rC, < i16 -1, i16 -1, i16 -1, i16 -1, + i16 -1, i16 -1, i16 -1, i16 -1 > + %B = and <8 x i16> %A, %rA + %D = or <8 x i16> %C, %B + ret <8 x i16> %D +} + +; (or (and rB, rC), (and (not rC), rA)) +define <8 x i16> @selb_v8i16_02(<8 x i16> %rA, <8 x i16> %rB, <8 x i16> %rC) { + %C = and <8 x i16> %rB, %rC + %A = xor <8 x i16> %rC, < i16 -1, i16 -1, i16 -1, i16 -1, + i16 -1, i16 -1, i16 -1, i16 -1 > + %B = and <8 x i16> %A, %rA + %D = or <8 x i16> %C, %B + ret <8 x i16> %D +} + +; (or (and (not rC), rA), (and rB, rC)) +define <8 x i16> @selb_v8i16_03(<8 x i16> %rA, <8 x i16> %rB, <8 x i16> %rC) { + %A = xor <8 x i16> %rC, < i16 -1, i16 -1, i16 -1, i16 -1, + i16 -1, i16 -1, i16 -1, i16 -1 > + %B = and <8 x i16> %A, %rA + %C = and <8 x i16> %rB, %rC + %D = or <8 x i16> %C, %B + ret <8 x i16> %D +} + +; (or (and (not rC), rA), (and rC, rB)) +define <8 x i16> @selb_v8i16_04(<8 x i16> %rA, <8 x i16> %rB, <8 x i16> %rC) { + %A = xor <8 x i16> %rC, < i16 -1, i16 -1, i16 -1, i16 -1, + i16 -1, i16 -1, i16 -1, i16 -1 > + %B = and <8 x i16> %A, %rA + %C = and <8 x i16> %rC, %rB + %D = or <8 x i16> %C, %B + ret <8 x i16> %D +} + +; (or (and rC, rB), (and rA, (not rC))) +define <8 x i16> @selb_v8i16_05(<8 x i16> %rA, <8 x i16> %rB, <8 x i16> %rC) { + %C = and <8 x i16> %rC, %rB + %A = xor <8 x i16> %rC, < i16 -1, i16 -1, i16 -1, i16 -1, + i16 -1, i16 -1, i16 -1, i16 -1 > + %B = and <8 x i16> %rA, %A + %D = or <8 x i16> %C, %B + ret <8 x i16> %D +} + +; (or (and rB, rC), (and rA, (not rC))) +define <8 x i16> @selb_v8i16_06(<8 x i16> %rA, <8 x i16> %rB, <8 x i16> %rC) { + %C = and <8 x i16> %rB, %rC + %A = xor <8 x i16> %rC, < i16 -1, i16 -1, i16 -1, i16 -1, + i16 -1, i16 -1, i16 -1, i16 -1 > + %B = and <8 x i16> %rA, %A + %D = or <8 x i16> %C, %B + ret <8 x i16> %D +} + +; (or (and rA, (not rC)), (and rB, rC)) +define <8 x i16> @selb_v8i16_07(<8 x i16> %rA, <8 x i16> %rB, <8 x i16> %rC) { + %A = xor <8 x i16> %rC, < i16 -1, i16 -1, i16 -1, i16 -1, + i16 -1, i16 -1, i16 -1, i16 -1 > + %B = and <8 x i16> %rA, %A + %C = and <8 x i16> %rB, %rC + %D = or <8 x i16> %C, %B + ret <8 x i16> %D +} + +; (or (and rA, (not rC)), (and rC, rB)) +define <8 x i16> @selb_v8i16_08(<8 x i16> %rA, <8 x i16> %rB, <8 x i16> %rC) { + %A = xor <8 x i16> %rC, < i16 -1, i16 -1, i16 -1, i16 -1, + i16 -1, i16 -1, i16 -1, i16 -1 > + %B = and <8 x i16> %rA, %A + %C = and <8 x i16> %rC, %rB + %D = or <8 x i16> %C, %B + ret <8 x i16> %D +} + +;-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ +; v16i8 +;-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ + +; (or (and rC, rB), (and (not rC), rA)) +define <16 x i8> @selb_v16i8_01(<16 x i8> %rA, <16 x i8> %rB, <16 x i8> %rC) { + %C = and <16 x i8> %rC, %rB + %A = xor <16 x i8> %rC, < i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1 > + %B = and <16 x i8> %A, %rA + %D = or <16 x i8> %C, %B + ret <16 x i8> %D +} + +; (or (and rB, rC), (and (not rC), rA)) +define <16 x i8> @selb_v16i8_02(<16 x i8> %rA, <16 x i8> %rB, <16 x i8> %rC) { + %C = and <16 x i8> %rB, %rC + %A = xor <16 x i8> %rC, < i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1 > + %B = and <16 x i8> %A, %rA + %D = or <16 x i8> %C, %B + ret <16 x i8> %D +} + +; (or (and (not rC), rA), (and rB, rC)) +define <16 x i8> @selb_v16i8_03(<16 x i8> %rA, <16 x i8> %rB, <16 x i8> %rC) { + %A = xor <16 x i8> %rC, < i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1 > + %B = and <16 x i8> %A, %rA + %C = and <16 x i8> %rB, %rC + %D = or <16 x i8> %C, %B + ret <16 x i8> %D +} + +; (or (and (not rC), rA), (and rC, rB)) +define <16 x i8> @selb_v16i8_04(<16 x i8> %rA, <16 x i8> %rB, <16 x i8> %rC) { + %A = xor <16 x i8> %rC, < i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1 > + %B = and <16 x i8> %A, %rA + %C = and <16 x i8> %rC, %rB + %D = or <16 x i8> %C, %B + ret <16 x i8> %D +} + +; (or (and rC, rB), (and rA, (not rC))) +define <16 x i8> @selb_v16i8_05(<16 x i8> %rA, <16 x i8> %rB, <16 x i8> %rC) { + %C = and <16 x i8> %rC, %rB + %A = xor <16 x i8> %rC, < i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1 > + %B = and <16 x i8> %rA, %A + %D = or <16 x i8> %C, %B + ret <16 x i8> %D +} + +; (or (and rB, rC), (and rA, (not rC))) +define <16 x i8> @selb_v16i8_06(<16 x i8> %rA, <16 x i8> %rB, <16 x i8> %rC) { + %C = and <16 x i8> %rB, %rC + %A = xor <16 x i8> %rC, < i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1 > + %B = and <16 x i8> %rA, %A + %D = or <16 x i8> %C, %B + ret <16 x i8> %D +} + +; (or (and rA, (not rC)), (and rB, rC)) +define <16 x i8> @selb_v16i8_07(<16 x i8> %rA, <16 x i8> %rB, <16 x i8> %rC) { + %A = xor <16 x i8> %rC, < i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1 > + %B = and <16 x i8> %rA, %A + %C = and <16 x i8> %rB, %rC + %D = or <16 x i8> %C, %B + ret <16 x i8> %D +} + +; (or (and rA, (not rC)), (and rC, rB)) +define <16 x i8> @selb_v16i8_08(<16 x i8> %rA, <16 x i8> %rB, <16 x i8> %rC) { + %A = xor <16 x i8> %rC, < i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1 > + %B = and <16 x i8> %rA, %A + %C = and <16 x i8> %rC, %rB + %D = or <16 x i8> %C, %B + ret <16 x i8> %D +} + +;-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ +; i32 +;-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ + +; (or (and rC, rB), (and (not rC), rA)) +define i32 @selb_i32_01(i32 %rA, i32 %rB, i32 %rC) { + %C = and i32 %rC, %rB + %A = xor i32 %rC, -1 + %B = and i32 %A, %rA + %D = or i32 %C, %B + ret i32 %D +} + +; (or (and rB, rC), (and (not rC), rA)) +define i32 @selb_i32_02(i32 %rA, i32 %rB, i32 %rC) { + %C = and i32 %rB, %rC + %A = xor i32 %rC, -1 + %B = and i32 %A, %rA + %D = or i32 %C, %B + ret i32 %D +} + +; (or (and (not rC), rA), (and rB, rC)) +define i32 @selb_i32_03(i32 %rA, i32 %rB, i32 %rC) { + %A = xor i32 %rC, -1 + %B = and i32 %A, %rA + %C = and i32 %rB, %rC + %D = or i32 %C, %B + ret i32 %D +} + +; (or (and (not rC), rA), (and rC, rB)) +define i32 @selb_i32_04(i32 %rA, i32 %rB, i32 %rC) { + %A = xor i32 %rC, -1 + %B = and i32 %A, %rA + %C = and i32 %rC, %rB + %D = or i32 %C, %B + ret i32 %D +} + +; (or (and rC, rB), (and rA, (not rC))) +define i32 @selb_i32_05(i32 %rA, i32 %rB, i32 %rC) { + %C = and i32 %rC, %rB + %A = xor i32 %rC, -1 + %B = and i32 %rA, %A + %D = or i32 %C, %B + ret i32 %D +} + +; (or (and rB, rC), (and rA, (not rC))) +define i32 @selb_i32_06(i32 %rA, i32 %rB, i32 %rC) { + %C = and i32 %rB, %rC + %A = xor i32 %rC, -1 + %B = and i32 %rA, %A + %D = or i32 %C, %B + ret i32 %D +} + +; (or (and rA, (not rC)), (and rB, rC)) +define i32 @selb_i32_07(i32 %rA, i32 %rB, i32 %rC) { + %A = xor i32 %rC, -1 + %B = and i32 %rA, %A + %C = and i32 %rB, %rC + %D = or i32 %C, %B + ret i32 %D +} + +; (or (and rA, (not rC)), (and rC, rB)) +define i32 @selb_i32_08(i32 %rA, i32 %rB, i32 %rC) { + %A = xor i32 %rC, -1 + %B = and i32 %rA, %A + %C = and i32 %rC, %rB + %D = or i32 %C, %B + ret i32 %D +} + +;-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ +; i16 +;-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ + +; (or (and rC, rB), (and (not rC), rA)) +define i16 @selb_i16_01(i16 %rA, i16 %rB, i16 %rC) { + %C = and i16 %rC, %rB + %A = xor i16 %rC, -1 + %B = and i16 %A, %rA + %D = or i16 %C, %B + ret i16 %D +} + +; (or (and rB, rC), (and (not rC), rA)) +define i16 @selb_i16_02(i16 %rA, i16 %rB, i16 %rC) { + %C = and i16 %rB, %rC + %A = xor i16 %rC, -1 + %B = and i16 %A, %rA + %D = or i16 %C, %B + ret i16 %D +} + +; (or (and (not rC), rA), (and rB, rC)) +define i16 @selb_i16_03(i16 %rA, i16 %rB, i16 %rC) { + %A = xor i16 %rC, -1 + %B = and i16 %A, %rA + %C = and i16 %rB, %rC + %D = or i16 %C, %B + ret i16 %D +} + +; (or (and (not rC), rA), (and rC, rB)) +define i16 @selb_i16_04(i16 %rA, i16 %rB, i16 %rC) { + %A = xor i16 %rC, -1 + %B = and i16 %A, %rA + %C = and i16 %rC, %rB + %D = or i16 %C, %B + ret i16 %D +} + +; (or (and rC, rB), (and rA, (not rC))) +define i16 @selb_i16_05(i16 %rA, i16 %rB, i16 %rC) { + %C = and i16 %rC, %rB + %A = xor i16 %rC, -1 + %B = and i16 %rA, %A + %D = or i16 %C, %B + ret i16 %D +} + +; (or (and rB, rC), (and rA, (not rC))) +define i16 @selb_i16_06(i16 %rA, i16 %rB, i16 %rC) { + %C = and i16 %rB, %rC + %A = xor i16 %rC, -1 + %B = and i16 %rA, %A + %D = or i16 %C, %B + ret i16 %D +} + +; (or (and rA, (not rC)), (and rB, rC)) +define i16 @selb_i16_07(i16 %rA, i16 %rB, i16 %rC) { + %A = xor i16 %rC, -1 + %B = and i16 %rA, %A + %C = and i16 %rB, %rC + %D = or i16 %C, %B + ret i16 %D +} + +; (or (and rA, (not rC)), (and rC, rB)) +define i16 @selb_i16_08(i16 %rA, i16 %rB, i16 %rC) { + %A = xor i16 %rC, -1 + %B = and i16 %rA, %A + %C = and i16 %rC, %rB + %D = or i16 %C, %B + ret i16 %D +} + +;-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ +; i8 +;-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ + +; (or (and rC, rB), (and (not rC), rA)) +define i8 @selb_i8_01(i8 %rA, i8 %rB, i8 %rC) { + %C = and i8 %rC, %rB + %A = xor i8 %rC, -1 + %B = and i8 %A, %rA + %D = or i8 %C, %B + ret i8 %D +} + +; (or (and rB, rC), (and (not rC), rA)) +define i8 @selb_i8_02(i8 %rA, i8 %rB, i8 %rC) { + %C = and i8 %rB, %rC + %A = xor i8 %rC, -1 + %B = and i8 %A, %rA + %D = or i8 %C, %B + ret i8 %D +} + +; (or (and (not rC), rA), (and rB, rC)) +define i8 @selb_i8_03(i8 %rA, i8 %rB, i8 %rC) { + %A = xor i8 %rC, -1 + %B = and i8 %A, %rA + %C = and i8 %rB, %rC + %D = or i8 %C, %B + ret i8 %D +} + +; (or (and (not rC), rA), (and rC, rB)) +define i8 @selb_i8_04(i8 %rA, i8 %rB, i8 %rC) { + %A = xor i8 %rC, -1 + %B = and i8 %A, %rA + %C = and i8 %rC, %rB + %D = or i8 %C, %B + ret i8 %D +} + +; (or (and rC, rB), (and rA, (not rC))) +define i8 @selb_i8_05(i8 %rA, i8 %rB, i8 %rC) { + %C = and i8 %rC, %rB + %A = xor i8 %rC, -1 + %B = and i8 %rA, %A + %D = or i8 %C, %B + ret i8 %D +} + +; (or (and rB, rC), (and rA, (not rC))) +define i8 @selb_i8_06(i8 %rA, i8 %rB, i8 %rC) { + %C = and i8 %rB, %rC + %A = xor i8 %rC, -1 + %B = and i8 %rA, %A + %D = or i8 %C, %B + ret i8 %D +} + +; (or (and rA, (not rC)), (and rB, rC)) +define i8 @selb_i8_07(i8 %rA, i8 %rB, i8 %rC) { + %A = xor i8 %rC, -1 + %B = and i8 %rA, %A + %C = and i8 %rB, %rC + %D = or i8 %C, %B + ret i8 %D +} + +; (or (and rA, (not rC)), (and rC, rB)) +define i8 @selb_i8_08(i8 %rA, i8 %rB, i8 %rC) { + %A = xor i8 %rC, -1 + %B = and i8 %rA, %A + %C = and i8 %rC, %rB + %D = or i8 %C, %B + ret i8 %D } Modified: llvm/trunk/test/CodeGen/CellSPU/shift_ops.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/shift_ops.ll?rev=47972&r1=47971&r2=47972&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/CellSPU/shift_ops.ll (original) +++ llvm/trunk/test/CodeGen/CellSPU/shift_ops.ll Wed Mar 5 17:00:19 2008 @@ -15,198 +15,198 @@ ; to a 32-bit type: define i16 @shlh_i16_1(i16 %arg1, i16 %arg2) { - %A = shl i16 %arg1, %arg2 - ret i16 %A + %A = shl i16 %arg1, %arg2 + ret i16 %A } define i16 @shlh_i16_2(i16 %arg1, i16 %arg2) { - %A = shl i16 %arg2, %arg1 - ret i16 %A + %A = shl i16 %arg2, %arg1 + ret i16 %A } define i16 @shlh_i16_3(i16 signext %arg1, i16 signext %arg2) signext { - %A = shl i16 %arg1, %arg2 - ret i16 %A + %A = shl i16 %arg1, %arg2 + ret i16 %A } define i16 @shlh_i16_4(i16 signext %arg1, i16 signext %arg2) signext { - %A = shl i16 %arg2, %arg1 - ret i16 %A + %A = shl i16 %arg2, %arg1 + ret i16 %A } define i16 @shlh_i16_5(i16 zeroext %arg1, i16 zeroext %arg2) zeroext { - %A = shl i16 %arg1, %arg2 - ret i16 %A + %A = shl i16 %arg1, %arg2 + ret i16 %A } define i16 @shlh_i16_6(i16 zeroext %arg1, i16 zeroext %arg2) zeroext { - %A = shl i16 %arg2, %arg1 - ret i16 %A + %A = shl i16 %arg2, %arg1 + ret i16 %A } ; Shift left i16 with immediate: define i16 @shlhi_i16_1(i16 %arg1) { - %A = shl i16 %arg1, 12 - ret i16 %A + %A = shl i16 %arg1, 12 + ret i16 %A } ; Should not generate anything other than the return, arg1 << 0 = arg1 define i16 @shlhi_i16_2(i16 %arg1) { - %A = shl i16 %arg1, 0 - ret i16 %A + %A = shl i16 %arg1, 0 + ret i16 %A } define i16 @shlhi_i16_3(i16 %arg1) { - %A = shl i16 16383, %arg1 - ret i16 %A + %A = shl i16 16383, %arg1 + ret i16 %A } ; Should generate 0, 0 << arg1 = 0 define i16 @shlhi_i16_4(i16 %arg1) { - %A = shl i16 0, %arg1 - ret i16 %A + %A = shl i16 0, %arg1 + ret i16 %A } define i16 @shlhi_i16_5(i16 signext %arg1) signext { - %A = shl i16 %arg1, 12 - ret i16 %A + %A = shl i16 %arg1, 12 + ret i16 %A } ; Should not generate anything other than the return, arg1 << 0 = arg1 define i16 @shlhi_i16_6(i16 signext %arg1) signext { - %A = shl i16 %arg1, 0 - ret i16 %A + %A = shl i16 %arg1, 0 + ret i16 %A } define i16 @shlhi_i16_7(i16 signext %arg1) signext { - %A = shl i16 16383, %arg1 - ret i16 %A + %A = shl i16 16383, %arg1 + ret i16 %A } ; Should generate 0, 0 << arg1 = 0 define i16 @shlhi_i16_8(i16 signext %arg1) signext { - %A = shl i16 0, %arg1 - ret i16 %A + %A = shl i16 0, %arg1 + ret i16 %A } define i16 @shlhi_i16_9(i16 zeroext %arg1) zeroext { - %A = shl i16 %arg1, 12 - ret i16 %A + %A = shl i16 %arg1, 12 + ret i16 %A } ; Should not generate anything other than the return, arg1 << 0 = arg1 define i16 @shlhi_i16_10(i16 zeroext %arg1) zeroext { - %A = shl i16 %arg1, 0 - ret i16 %A + %A = shl i16 %arg1, 0 + ret i16 %A } define i16 @shlhi_i16_11(i16 zeroext %arg1) zeroext { - %A = shl i16 16383, %arg1 - ret i16 %A + %A = shl i16 16383, %arg1 + ret i16 %A } ; Should generate 0, 0 << arg1 = 0 define i16 @shlhi_i16_12(i16 zeroext %arg1) zeroext { - %A = shl i16 0, %arg1 - ret i16 %A + %A = shl i16 0, %arg1 + ret i16 %A } ; Shift left i32 via register, note that the second operand to shl is promoted ; to a 32-bit type: define i32 @shl_i32_1(i32 %arg1, i32 %arg2) { - %A = shl i32 %arg1, %arg2 - ret i32 %A + %A = shl i32 %arg1, %arg2 + ret i32 %A } define i32 @shl_i32_2(i32 %arg1, i32 %arg2) { - %A = shl i32 %arg2, %arg1 - ret i32 %A + %A = shl i32 %arg2, %arg1 + ret i32 %A } define i32 @shl_i32_3(i32 signext %arg1, i32 signext %arg2) signext { - %A = shl i32 %arg1, %arg2 - ret i32 %A + %A = shl i32 %arg1, %arg2 + ret i32 %A } define i32 @shl_i32_4(i32 signext %arg1, i32 signext %arg2) signext { - %A = shl i32 %arg2, %arg1 - ret i32 %A + %A = shl i32 %arg2, %arg1 + ret i32 %A } define i32 @shl_i32_5(i32 zeroext %arg1, i32 zeroext %arg2) zeroext { - %A = shl i32 %arg1, %arg2 - ret i32 %A + %A = shl i32 %arg1, %arg2 + ret i32 %A } define i32 @shl_i32_6(i32 zeroext %arg1, i32 zeroext %arg2) zeroext { - %A = shl i32 %arg2, %arg1 - ret i32 %A + %A = shl i32 %arg2, %arg1 + ret i32 %A } ; Shift left i32 with immediate: define i32 @shli_i32_1(i32 %arg1) { - %A = shl i32 %arg1, 12 - ret i32 %A + %A = shl i32 %arg1, 12 + ret i32 %A } ; Should not generate anything other than the return, arg1 << 0 = arg1 define i32 @shli_i32_2(i32 %arg1) { - %A = shl i32 %arg1, 0 - ret i32 %A + %A = shl i32 %arg1, 0 + ret i32 %A } define i32 @shli_i32_3(i32 %arg1) { - %A = shl i32 16383, %arg1 - ret i32 %A + %A = shl i32 16383, %arg1 + ret i32 %A } ; Should generate 0, 0 << arg1 = 0 define i32 @shli_i32_4(i32 %arg1) { - %A = shl i32 0, %arg1 - ret i32 %A + %A = shl i32 0, %arg1 + ret i32 %A } define i32 @shli_i32_5(i32 signext %arg1) signext { - %A = shl i32 %arg1, 12 - ret i32 %A + %A = shl i32 %arg1, 12 + ret i32 %A } ; Should not generate anything other than the return, arg1 << 0 = arg1 define i32 @shli_i32_6(i32 signext %arg1) signext { - %A = shl i32 %arg1, 0 - ret i32 %A + %A = shl i32 %arg1, 0 + ret i32 %A } define i32 @shli_i32_7(i32 signext %arg1) signext { - %A = shl i32 16383, %arg1 - ret i32 %A + %A = shl i32 16383, %arg1 + ret i32 %A } ; Should generate 0, 0 << arg1 = 0 define i32 @shli_i32_8(i32 signext %arg1) signext { - %A = shl i32 0, %arg1 - ret i32 %A + %A = shl i32 0, %arg1 + ret i32 %A } define i32 @shli_i32_9(i32 zeroext %arg1) zeroext { - %A = shl i32 %arg1, 12 - ret i32 %A + %A = shl i32 %arg1, 12 + ret i32 %A } ; Should not generate anything other than the return, arg1 << 0 = arg1 define i32 @shli_i32_10(i32 zeroext %arg1) zeroext { - %A = shl i32 %arg1, 0 - ret i32 %A + %A = shl i32 %arg1, 0 + ret i32 %A } define i32 @shli_i32_11(i32 zeroext %arg1) zeroext { - %A = shl i32 16383, %arg1 - ret i32 %A + %A = shl i32 16383, %arg1 + ret i32 %A } ; Should generate 0, 0 << arg1 = 0 define i32 @shli_i32_12(i32 zeroext %arg1) zeroext { - %A = shl i32 0, %arg1 - ret i32 %A + %A = shl i32 0, %arg1 + ret i32 %A } Modified: llvm/trunk/test/CodeGen/CellSPU/sp_farith.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/sp_farith.ll?rev=47972&r1=47971&r2=47972&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/CellSPU/sp_farith.ll (original) +++ llvm/trunk/test/CodeGen/CellSPU/sp_farith.ll Wed Mar 5 17:00:19 2008 @@ -12,79 +12,79 @@ target triple = "spu" define float @fp_add(float %arg1, float %arg2) { - %A = add float %arg1, %arg2 ; [#uses=1] - ret float %A + %A = add float %arg1, %arg2 ; [#uses=1] + ret float %A } define <4 x float> @fp_add_vec(<4 x float> %arg1, <4 x float> %arg2) { - %A = add <4 x float> %arg1, %arg2 ; <<4 x float>> [#uses=1] - ret <4 x float> %A + %A = add <4 x float> %arg1, %arg2 ; <<4 x float>> [#uses=1] + ret <4 x float> %A } define float @fp_sub(float %arg1, float %arg2) { - %A = sub float %arg1, %arg2 ; [#uses=1] - ret float %A + %A = sub float %arg1, %arg2 ; [#uses=1] + ret float %A } define <4 x float> @fp_sub_vec(<4 x float> %arg1, <4 x float> %arg2) { - %A = sub <4 x float> %arg1, %arg2 ; <<4 x float>> [#uses=1] - ret <4 x float> %A + %A = sub <4 x float> %arg1, %arg2 ; <<4 x float>> [#uses=1] + ret <4 x float> %A } define float @fp_mul(float %arg1, float %arg2) { - %A = mul float %arg1, %arg2 ; [#uses=1] - ret float %A + %A = mul float %arg1, %arg2 ; [#uses=1] + ret float %A } define <4 x float> @fp_mul_vec(<4 x float> %arg1, <4 x float> %arg2) { - %A = mul <4 x float> %arg1, %arg2 ; <<4 x float>> [#uses=1] - ret <4 x float> %A + %A = mul <4 x float> %arg1, %arg2 ; <<4 x float>> [#uses=1] + ret <4 x float> %A } define float @fp_mul_add(float %arg1, float %arg2, float %arg3) { - %A = mul float %arg1, %arg2 ; [#uses=1] - %B = add float %A, %arg3 ; [#uses=1] - ret float %B + %A = mul float %arg1, %arg2 ; [#uses=1] + %B = add float %A, %arg3 ; [#uses=1] + ret float %B } define <4 x float> @fp_mul_add_vec(<4 x float> %arg1, <4 x float> %arg2, <4 x float> %arg3) { - %A = mul <4 x float> %arg1, %arg2 ; <<4 x float>> [#uses=1] - %B = add <4 x float> %A, %arg3 ; <<4 x float>> [#uses=1] - ret <4 x float> %B + %A = mul <4 x float> %arg1, %arg2 ; <<4 x float>> [#uses=1] + %B = add <4 x float> %A, %arg3 ; <<4 x float>> [#uses=1] + ret <4 x float> %B } define float @fp_mul_sub(float %arg1, float %arg2, float %arg3) { - %A = mul float %arg1, %arg2 ; [#uses=1] - %B = sub float %A, %arg3 ; [#uses=1] - ret float %B + %A = mul float %arg1, %arg2 ; [#uses=1] + %B = sub float %A, %arg3 ; [#uses=1] + ret float %B } define <4 x float> @fp_mul_sub_vec(<4 x float> %arg1, <4 x float> %arg2, <4 x float> %arg3) { - %A = mul <4 x float> %arg1, %arg2 ; <<4 x float>> [#uses=1] - %B = sub <4 x float> %A, %arg3 ; <<4 x float>> [#uses=1] - ret <4 x float> %B + %A = mul <4 x float> %arg1, %arg2 ; <<4 x float>> [#uses=1] + %B = sub <4 x float> %A, %arg3 ; <<4 x float>> [#uses=1] + ret <4 x float> %B } ; Test the straightforward way of getting fnms ; c - a * b define float @fp_neg_mul_sub_1(float %arg1, float %arg2, float %arg3) { - %A = mul float %arg1, %arg2 - %B = sub float %arg3, %A - ret float %B + %A = mul float %arg1, %arg2 + %B = sub float %arg3, %A + ret float %B } ; Test another way of getting fnms ; - ( a *b -c ) = c - a * b define float @fp_neg_mul_sub_2(float %arg1, float %arg2, float %arg3) { - %A = mul float %arg1, %arg2 - %B = sub float %A, %arg3 - %C = sub float -0.0, %B - ret float %C + %A = mul float %arg1, %arg2 + %B = sub float %A, %arg3 + %C = sub float -0.0, %B + ret float %C } define <4 x float> @fp_neg_mul_sub_vec(<4 x float> %arg1, <4 x float> %arg2, <4 x float> %arg3) { - %A = mul <4 x float> %arg1, %arg2 - %B = sub <4 x float> %A, %arg3 - %D = sub <4 x float> < float -0.0, float -0.0, float -0.0, float -0.0 >, %B - ret <4 x float> %D + %A = mul <4 x float> %arg1, %arg2 + %B = sub <4 x float> %A, %arg3 + %D = sub <4 x float> < float -0.0, float -0.0, float -0.0, float -0.0 >, %B + ret <4 x float> %D } Modified: llvm/trunk/test/CodeGen/CellSPU/struct_1.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/struct_1.ll?rev=47972&r1=47971&r2=47972&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/CellSPU/struct_1.ll (original) +++ llvm/trunk/test/CodeGen/CellSPU/struct_1.ll Wed Mar 5 17:00:19 2008 @@ -49,96 +49,96 @@ define i8 @get_hackstate_c1() zeroext nounwind { entry: - %tmp2 = load i8* getelementptr (%struct.hackstate* @state, i32 0, i32 0), align 16 - ret i8 %tmp2 + %tmp2 = load i8* getelementptr (%struct.hackstate* @state, i32 0, i32 0), align 16 + ret i8 %tmp2 } define i8 @get_hackstate_c2() zeroext nounwind { entry: - %tmp2 = load i8* getelementptr (%struct.hackstate* @state, i32 0, i32 1), align 16 - ret i8 %tmp2 + %tmp2 = load i8* getelementptr (%struct.hackstate* @state, i32 0, i32 1), align 16 + ret i8 %tmp2 } define i8 @get_hackstate_c3() zeroext nounwind { entry: - %tmp2 = load i8* getelementptr (%struct.hackstate* @state, i32 0, i32 2), align 16 - ret i8 %tmp2 + %tmp2 = load i8* getelementptr (%struct.hackstate* @state, i32 0, i32 2), align 16 + ret i8 %tmp2 } define i32 @get_hackstate_i1() nounwind { entry: - %tmp2 = load i32* getelementptr (%struct.hackstate* @state, i32 0, i32 3), align 16 - ret i32 %tmp2 + %tmp2 = load i32* getelementptr (%struct.hackstate* @state, i32 0, i32 3), align 16 + ret i32 %tmp2 } define i16 @get_hackstate_s1() signext nounwind { entry: - %tmp2 = load i16* getelementptr (%struct.hackstate* @state, i32 0, i32 4), align 16 - ret i16 %tmp2 + %tmp2 = load i16* getelementptr (%struct.hackstate* @state, i32 0, i32 4), align 16 + ret i16 %tmp2 } define i8 @get_hackstate_c6() zeroext nounwind { entry: - %tmp2 = load i8* getelementptr (%struct.hackstate* @state, i32 0, i32 8), align 16 - ret i8 %tmp2 + %tmp2 = load i8* getelementptr (%struct.hackstate* @state, i32 0, i32 8), align 16 + ret i8 %tmp2 } define i8 @get_hackstate_c7() zeroext nounwind { entry: - %tmp2 = load i8* getelementptr (%struct.hackstate* @state, i32 0, i32 9), align 16 - ret i8 %tmp2 + %tmp2 = load i8* getelementptr (%struct.hackstate* @state, i32 0, i32 9), align 16 + ret i8 %tmp2 } define i32 @get_hackstate_i3() nounwind { entry: - %tmp2 = load i32* getelementptr (%struct.hackstate* @state, i32 0, i32 10), align 16 - ret i32 %tmp2 + %tmp2 = load i32* getelementptr (%struct.hackstate* @state, i32 0, i32 10), align 16 + ret i32 %tmp2 } define i32 @get_hackstate_i6() nounwind { entry: - %tmp2 = load i32* getelementptr (%struct.hackstate* @state, i32 0, i32 13), align 16 - ret i32 %tmp2 + %tmp2 = load i32* getelementptr (%struct.hackstate* @state, i32 0, i32 13), align 16 + ret i32 %tmp2 } define void @set_hackstate_c1(i8 zeroext %c) nounwind { entry: - store i8 %c, i8* getelementptr (%struct.hackstate* @state, i32 0, i32 0), align 16 - ret void + store i8 %c, i8* getelementptr (%struct.hackstate* @state, i32 0, i32 0), align 16 + ret void } define void @set_hackstate_c2(i8 zeroext %c) nounwind { entry: - store i8 %c, i8* getelementptr (%struct.hackstate* @state, i32 0, i32 1), align 16 - ret void + store i8 %c, i8* getelementptr (%struct.hackstate* @state, i32 0, i32 1), align 16 + ret void } define void @set_hackstate_c3(i8 zeroext %c) nounwind { entry: - store i8 %c, i8* getelementptr (%struct.hackstate* @state, i32 0, i32 2), align 16 - ret void + store i8 %c, i8* getelementptr (%struct.hackstate* @state, i32 0, i32 2), align 16 + ret void } define void @set_hackstate_i1(i32 %i) nounwind { entry: - store i32 %i, i32* getelementptr (%struct.hackstate* @state, i32 0, i32 3), align 16 - ret void + store i32 %i, i32* getelementptr (%struct.hackstate* @state, i32 0, i32 3), align 16 + ret void } define void @set_hackstate_s1(i16 signext %s) nounwind { entry: - store i16 %s, i16* getelementptr (%struct.hackstate* @state, i32 0, i32 4), align 16 - ret void + store i16 %s, i16* getelementptr (%struct.hackstate* @state, i32 0, i32 4), align 16 + ret void } define void @set_hackstate_i3(i32 %i) nounwind { entry: - store i32 %i, i32* getelementptr (%struct.hackstate* @state, i32 0, i32 10), align 16 - ret void + store i32 %i, i32* getelementptr (%struct.hackstate* @state, i32 0, i32 10), align 16 + ret void } define void @set_hackstate_i6(i32 %i) nounwind { entry: - store i32 %i, i32* getelementptr (%struct.hackstate* @state, i32 0, i32 13), align 16 - ret void + store i32 %i, i32* getelementptr (%struct.hackstate* @state, i32 0, i32 13), align 16 + ret void } Modified: llvm/trunk/test/CodeGen/CellSPU/vec_const.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/vec_const.ll?rev=47972&r1=47971&r2=47972&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/CellSPU/vec_const.ll (original) +++ llvm/trunk/test/CodeGen/CellSPU/vec_const.ll Wed Mar 5 17:00:19 2008 @@ -26,30 +26,30 @@ ; IL , 2 define <4 x i32> @v4i32_constvec() { - ret <4 x i32> < i32 2, i32 2, i32 2, i32 2 > + ret <4 x i32> < i32 2, i32 2, i32 2, i32 2 > } ; Spill to constant pool define <4 x i32> @v4i32_constpool() { - ret <4 x i32> < i32 2, i32 1, i32 1, i32 2 > + ret <4 x i32> < i32 2, i32 1, i32 1, i32 2 > } ; Max negative range for IL define <4 x i32> @v4i32_constvec_2() { - ret <4 x i32> < i32 -32768, i32 -32768, i32 -32768, i32 -32768 > + ret <4 x i32> < i32 -32768, i32 -32768, i32 -32768, i32 -32768 > } ; ILHU , 73 (0x49) ; 4784128 = 0x490000 define <4 x i32> @v4i32_constvec_3() { - ret <4 x i32> < i32 4784128, i32 4784128, + ret <4 x i32> < i32 4784128, i32 4784128, i32 4784128, i32 4784128 > } ; ILHU , 61 (0x3d) ; IOHL , 15395 (0x3c23) define <4 x i32> @v4i32_constvec_4() { - ret <4 x i32> < i32 4013091, i32 4013091, + ret <4 x i32> < i32 4013091, i32 4013091, i32 4013091, i32 4013091 > } @@ -58,25 +58,25 @@ ; Tests for whether we expand the size of the bit pattern properly, because ; this could be interpreted as an i8 pattern (0x50) define <4 x i32> @v4i32_constvec_5() { - ret <4 x i32> < i32 1347440720, i32 1347440720, + ret <4 x i32> < i32 1347440720, i32 1347440720, i32 1347440720, i32 1347440720 > } ; ILH define <8 x i16> @v8i16_constvec_1() { - ret <8 x i16> < i16 32767, i16 32767, i16 32767, i16 32767, + ret <8 x i16> < i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767 > } ; ILH define <8 x i16> @v8i16_constvec_2() { - ret <8 x i16> < i16 511, i16 511, i16 511, i16 511, i16 511, + ret <8 x i16> < i16 511, i16 511, i16 511, i16 511, i16 511, i16 511, i16 511, i16 511 > } ; ILH define <8 x i16> @v8i16_constvec_3() { - ret <8 x i16> < i16 -512, i16 -512, i16 -512, i16 -512, i16 -512, + ret <8 x i16> < i16 -512, i16 -512, i16 -512, i16 -512, i16 -512, i16 -512, i16 -512, i16 -512 > } @@ -84,7 +84,7 @@ ; Tests whether we expand the size of the bit pattern properly, because ; this could be interpreted as an i8 pattern (0x60) define <8 x i16> @v8i16_constvec_4() { - ret <8 x i16> < i16 24672, i16 24672, i16 24672, i16 24672, i16 24672, + ret <8 x i16> < i16 24672, i16 24672, i16 24672, i16 24672, i16 24672, i16 24672, i16 24672, i16 24672 > } @@ -93,7 +93,7 @@ ; this is an i8 pattern but has to be expanded out to i16 to load it ; properly into the vector register. define <16 x i8> @v16i8_constvec_1() { - ret <16 x i8> < i8 96, i8 96, i8 96, i8 96, i8 96, i8 96, i8 96, i8 96, + ret <16 x i8> < i8 96, i8 96, i8 96, i8 96, i8 96, i8 96, i8 96, i8 96, i8 96, i8 96, i8 96, i8 96, i8 96, i8 96, i8 96, i8 96 > } @@ -101,16 +101,16 @@ entry: ret <4 x float> < float 0x4005BF0A80000000, float 0x4005BF0A80000000, - float 0x4005BF0A80000000, - float 0x4005BF0A80000000 > + float 0x4005BF0A80000000, + float 0x4005BF0A80000000 > } define <4 x float> @v4f32_constvec_2() { entry: ret <4 x float> < float 0.000000e+00, float 0.000000e+00, - float 0.000000e+00, - float 0.000000e+00 > + float 0.000000e+00, + float 0.000000e+00 > } @@ -118,8 +118,8 @@ entry: ret <4 x float> < float 0x4005BF0A80000000, float 0x3810000000000000, - float 0x47EFFFFFE0000000, - float 0x400921FB60000000 > + float 0x47EFFFFFE0000000, + float 0x400921FB60000000 > } ; 1311768467750121234 => 0x 12345678 abcdef12 @@ -129,13 +129,13 @@ ; LO32_lo: 61202 define <2 x i64> @i64_constvec_1() { entry: - ret <2 x i64> < i64 1311768467750121234, - i64 1311768467750121234 > + ret <2 x i64> < i64 1311768467750121234, + i64 1311768467750121234 > } define <2 x i64> @i64_constvec_2() { entry: - ret <2 x i64> < i64 1, i64 1311768467750121234 > + ret <2 x i64> < i64 1, i64 1311768467750121234 > } define <2 x double> @f64_constvec_1() { @@ -150,5 +150,5 @@ define <2 x double> @f64_constvec_2() { entry: ret <2 x double> < double 0x400921fb54442d18, - double 0x400921fb54442d18 > + double 0x400921fb54442d18 > } Modified: llvm/trunk/test/CodeGen/CellSPU/vecinsert.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/vecinsert.ll?rev=47972&r1=47971&r2=47972&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/CellSPU/vecinsert.ll (original) +++ llvm/trunk/test/CodeGen/CellSPU/vecinsert.ll Wed Mar 5 17:00:19 2008 @@ -19,35 +19,35 @@ ; 67 -> 0x43, as 8-bit vector constant load = 0x4343 (17219)0x4343 define <16 x i8> @test_v16i8(<16 x i8> %P, i8 %x) { entry: - %tmp1 = insertelement <16 x i8> %P, i8 %x, i32 10 - %tmp1.1 = insertelement <16 x i8> %tmp1, i8 67, i32 7 - %tmp1.2 = insertelement <16 x i8> %tmp1.1, i8 %x, i32 15 - ret <16 x i8> %tmp1.2 + %tmp1 = insertelement <16 x i8> %P, i8 %x, i32 10 + %tmp1.1 = insertelement <16 x i8> %tmp1, i8 67, i32 7 + %tmp1.2 = insertelement <16 x i8> %tmp1.1, i8 %x, i32 15 + ret <16 x i8> %tmp1.2 } ; 22598 -> 0x5846 define <8 x i16> @test_v8i16(<8 x i16> %P, i16 %x) { entry: - %tmp1 = insertelement <8 x i16> %P, i16 %x, i32 5 - %tmp1.1 = insertelement <8 x i16> %tmp1, i16 22598, i32 7 - %tmp1.2 = insertelement <8 x i16> %tmp1.1, i16 %x, i32 2 - ret <8 x i16> %tmp1.2 + %tmp1 = insertelement <8 x i16> %P, i16 %x, i32 5 + %tmp1.1 = insertelement <8 x i16> %tmp1, i16 22598, i32 7 + %tmp1.2 = insertelement <8 x i16> %tmp1.1, i16 %x, i32 2 + ret <8 x i16> %tmp1.2 } ; 1574023 -> 0x180487 (ILHU 24/IOHL 1159) define <4 x i32> @test_v4i32_1(<4 x i32> %P, i32 %x) { entry: - %tmp1 = insertelement <4 x i32> %P, i32 %x, i32 2 - %tmp1.1 = insertelement <4 x i32> %tmp1, i32 1574023, i32 1 - %tmp1.2 = insertelement <4 x i32> %tmp1.1, i32 %x, i32 3 - ret <4 x i32> %tmp1.2 + %tmp1 = insertelement <4 x i32> %P, i32 %x, i32 2 + %tmp1.1 = insertelement <4 x i32> %tmp1, i32 1574023, i32 1 + %tmp1.2 = insertelement <4 x i32> %tmp1.1, i32 %x, i32 3 + ret <4 x i32> %tmp1.2 } ; Should generate IL for the load define <4 x i32> @test_v4i32_2(<4 x i32> %P, i32 %x) { entry: - %tmp1 = insertelement <4 x i32> %P, i32 %x, i32 2 - %tmp1.1 = insertelement <4 x i32> %tmp1, i32 -39, i32 1 - %tmp1.2 = insertelement <4 x i32> %tmp1.1, i32 %x, i32 3 - ret <4 x i32> %tmp1.2 + %tmp1 = insertelement <4 x i32> %P, i32 %x, i32 2 + %tmp1.1 = insertelement <4 x i32> %tmp1, i32 -39, i32 1 + %tmp1.2 = insertelement <4 x i32> %tmp1.1, i32 %x, i32 3 + ret <4 x i32> %tmp1.2 } From scottm at aero.org Wed Mar 5 17:02:02 2008 From: scottm at aero.org (Scott Michel) Date: Wed, 05 Mar 2008 23:02:02 -0000 Subject: [llvm-commits] [llvm] r47973 - in /llvm/trunk/lib/Target/CellSPU: SPUISelLowering.cpp SPUInstrInfo.td SPUNodes.td SPUOperands.td Message-ID: <200803052302.m25N22tR028528@zion.cs.uiuc.edu> Author: pingbak Date: Wed Mar 5 17:02:02 2008 New Revision: 47973 URL: http://llvm.org/viewvc/llvm-project?rev=47973&view=rev Log: - Fix support for "special" i64 immediates that can be loaded using IL, ILA, et. al. v2i64 and i64 are now supported by the select bits (SELB) instruction. - Add missing comparison operations (testcase forthcoming) - More multiclass refactoring. Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td llvm/trunk/lib/Target/CellSPU/SPUNodes.td llvm/trunk/lib/Target/CellSPU/SPUOperands.td Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=47973&r1=47972&r2=47973&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Wed Mar 5 17:02:02 2008 @@ -243,15 +243,23 @@ setOperationAction(ISD::CTLZ , MVT::i32, Legal); - // SPU does not have select or setcc + // SPU has a version of select setOperationAction(ISD::SELECT, MVT::i1, Expand); setOperationAction(ISD::SELECT, MVT::i8, Expand); - setOperationAction(ISD::SELECT, MVT::i16, Expand); - setOperationAction(ISD::SELECT, MVT::i32, Expand); + setOperationAction(ISD::SELECT, MVT::i16, Legal); + setOperationAction(ISD::SELECT, MVT::i32, Legal); setOperationAction(ISD::SELECT, MVT::i64, Expand); setOperationAction(ISD::SELECT, MVT::f32, Expand); setOperationAction(ISD::SELECT, MVT::f64, Expand); + setOperationAction(ISD::SETCC, MVT::i1, Expand); + setOperationAction(ISD::SETCC, MVT::i8, Expand); + setOperationAction(ISD::SETCC, MVT::i16, Legal); + setOperationAction(ISD::SETCC, MVT::i32, Legal); + setOperationAction(ISD::SETCC, MVT::i64, Expand); + setOperationAction(ISD::SETCC, MVT::f32, Expand); + setOperationAction(ISD::SETCC, MVT::f64, Expand); + // Zero extension and sign extension for i64 have to be // custom legalized setOperationAction(ISD::ZERO_EXTEND, MVT::i64, Custom); @@ -838,7 +846,6 @@ SDOperand T = DAG.getConstant(CN->getValue(), MVT::i64); return DAG.getNode(SPUISD::EXTRACT_ELT0, VT, DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i64, T, T)); - } else { cerr << "LowerConstant: unhandled constant type " << MVT::getValueTypeString(VT) @@ -981,6 +988,7 @@ break; case MVT::v2f64: case MVT::v4f32: + case MVT::v2i64: case MVT::v4i32: case MVT::v8i16: case MVT::v16i8: @@ -1359,24 +1367,9 @@ SDOperand SPU::get_vec_i16imm(SDNode *N, SelectionDAG &DAG, MVT::ValueType ValueType) { if (ConstantSDNode *CN = getVecImm(N)) { - if (ValueType == MVT::i32) { - int Value = (int) CN->getValue(); - int SExtValue = ((Value & 0xffff) << 16) >> 16; - - if (Value == SExtValue) - return DAG.getConstant(Value, ValueType); - } else if (ValueType == MVT::i16) { - short Value = (short) CN->getValue(); - int SExtValue = ((int) Value << 16) >> 16; - - if (Value == (short) SExtValue) - return DAG.getConstant(Value, ValueType); - } else if (ValueType == MVT::i64) { - int64_t Value = CN->getValue(); - int64_t SExtValue = ((Value & 0xffff) << (64 - 16)) >> (64 - 16); - - if (Value == SExtValue) - return DAG.getConstant(Value, ValueType); + int64_t Value = CN->getSignExtended(); + if (Value >= -(1 << 15) && Value <= ((1 << 15) - 1)) { + return DAG.getConstant(Value, ValueType); } } @@ -1389,9 +1382,8 @@ SDOperand SPU::get_vec_i10imm(SDNode *N, SelectionDAG &DAG, MVT::ValueType ValueType) { if (ConstantSDNode *CN = getVecImm(N)) { - int Value = (int) CN->getValue(); - if ((ValueType == MVT::i32 && isS10Constant(Value)) - || (ValueType == MVT::i16 && isS10Constant((short) Value))) + int64_t Value = CN->getSignExtended(); + if (isS10Constant(Value)) return DAG.getConstant(Value, ValueType); } @@ -1634,7 +1626,14 @@ uint32_t upper = uint32_t(val >> 32); uint32_t lower = uint32_t(val); - if (val != 0) { + if (val == 0) { + SDOperand Zero = DAG.getTargetConstant(0, MVT::i64); + return DAG.getNode(ISD::BUILD_VECTOR, VT, Zero, Zero); + } else if (val == 0xffffffffffffffffULL) { + // For -1, this and has a chance of matching immAllOnesV. + SDOperand NegOne = DAG.getTargetConstant(-1, MVT::i64); + return DAG.getNode(ISD::BUILD_VECTOR, VT, NegOne, NegOne); + } else { SDOperand LO32; SDOperand HI32; SmallVector ShufBytes; @@ -1708,12 +1707,6 @@ return DAG.getNode(SPUISD::SHUFB, VT, HI32, LO32, DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, &ShufBytes[0], ShufBytes.size())); - } else { - // For zero, this can be lowered efficiently via v4i32 BUILD_VECTOR - SDOperand Zero = DAG.getConstant(0, MVT::i32); - return DAG.getNode(ISD::BIT_CONVERT, VT, - DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, - Zero, Zero, Zero, Zero)); } } } Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td?rev=47973&r1=47972&r2=47973&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td (original) +++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td Wed Mar 5 17:02:02 2008 @@ -196,15 +196,13 @@ : RI16Form<0b0010010, (outs), (ins VECREG:$rT, addr256k:$src), "stqa\t$rT, $src", LoadStore, - [(store (vectype VECREG:$rT), aform_addr:$src)]> -{ } + [(store (vectype VECREG:$rT), aform_addr:$src)]>; class StoreAForm : RI16Form<0b001001, (outs), (ins rclass:$rT, addr256k:$src), "stqa\t$rT, $src", LoadStore, - [(store rclass:$rT, aform_addr:$src)]> -{ } + [(store rclass:$rT, aform_addr:$src)]>; multiclass StoreAForms { @@ -326,87 +324,89 @@ [(set R8C:$rT, immSExt8:$val)]>; // IL does sign extension! -def ILr64: - RI16Form<0b100000010, (outs R64C:$rT), (ins s16imm_i64:$val), - "il\t$rT, $val", ImmLoad, - [(set R64C:$rT, immSExt16:$val)]>; - -def ILv2i64: - RI16Form<0b100000010, (outs VECREG:$rT), (ins s16imm_i64:$val), - "il\t$rT, $val", ImmLoad, - [(set VECREG:$rT, (v2i64 v2i64SExt16Imm:$val))]>; - -def ILv4i32: - RI16Form<0b100000010, (outs VECREG:$rT), (ins s16imm:$val), - "il\t$rT, $val", ImmLoad, - [(set VECREG:$rT, (v4i32 v4i32SExt16Imm:$val))]>; - -def ILr32: - RI16Form<0b100000010, (outs R32C:$rT), (ins s16imm_i32:$val), - "il\t$rT, $val", ImmLoad, - [(set R32C:$rT, immSExt16:$val)]>; - -def ILf32: - RI16Form<0b100000010, (outs R32FP:$rT), (ins s16imm_f32:$val), - "il\t$rT, $val", ImmLoad, - [(set R32FP:$rT, fpimmSExt16:$val)]>; - -def ILf64: - RI16Form<0b100000010, (outs R64FP:$rT), (ins s16imm_f64:$val), - "il\t$rT, $val", ImmLoad, - [(set R64FP:$rT, fpimmSExt16:$val)]>; - -def ILHUv4i32: - RI16Form<0b010000010, (outs VECREG:$rT), (ins u16imm:$val), - "ilhu\t$rT, $val", ImmLoad, - [(set VECREG:$rT, (v4i32 immILHUvec:$val))]>; - -def ILHUr32: - RI16Form<0b010000010, (outs R32C:$rT), (ins u16imm:$val), - "ilhu\t$rT, $val", ImmLoad, - [(set R32C:$rT, hi16:$val)]>; - -// ILHUf32: Used to custom lower float constant loads -def ILHUf32: - RI16Form<0b010000010, (outs R32FP:$rT), (ins f16imm:$val), - "ilhu\t$rT, $val", ImmLoad, - [(set R32FP:$rT, hi16_f32:$val)]>; - -// ILHUhi: Used for loading high portion of an address. Note the symbolHi -// printer used for the operand. -def ILHUhi: - RI16Form<0b010000010, (outs R32C:$rT), (ins symbolHi:$val), - "ilhu\t$rT, $val", ImmLoad, - [(set R32C:$rT, hi16:$val)]>; + +class ILInst pattern>: + RI16Form<0b100000010, OOL, IOL, "il\t$rT, $val", + ImmLoad, pattern>; + +class ILVecInst: + ILInst<(outs VECREG:$rT), (ins immtype:$val), + [(set (vectype VECREG:$rT), (vectype xform:$val))]>; + +class ILRegInst: + ILInst<(outs rclass:$rT), (ins immtype:$val), + [(set rclass:$rT, xform:$val)]>; + +multiclass ImmediateLoad +{ + def v2i64: ILVecInst; + def v4i32: ILVecInst; + + // TODO: Need v2f64, v4f32 + + def r64: ILRegInst; + def r32: ILRegInst; + def f32: ILRegInst; + def f64: ILRegInst; +} + +defm IL : ImmediateLoad; + +class ILHUInst pattern>: + RI16Form<0b010000010, OOL, IOL, "ilhu\t$rT, $val", + ImmLoad, pattern>; + +class ILHUVecInst: + ILHUInst<(outs VECREG:$rT), (ins immtype:$val), + [(set (vectype VECREG:$rT), (vectype xform:$val))]>; + +class ILHURegInst: + ILHUInst<(outs rclass:$rT), (ins immtype:$val), + [(set rclass:$rT, xform:$val)]>; + +multiclass ImmLoadHalfwordUpper +{ + def v2i64: ILHUVecInst; + def v4i32: ILHUVecInst; + + def r64: ILHURegInst; + def r32: ILHURegInst; + + // Loads the high portion of an address + def hi: ILHURegInst; + + // Used in custom lowering constant SFP loads: + def f32: ILHURegInst; +} + +defm ILHU : ImmLoadHalfwordUpper; // Immediate load address (can also be used to load 18-bit unsigned constants, // see the zext 16->32 pattern) + class ILAInst pattern>: RI18Form<0b1000010, OOL, IOL, "ila\t$rT, $val", LoadNOP, pattern>; +class ILAVecInst: + ILAInst<(outs VECREG:$rT), (ins immtype:$val), + [(set (vectype VECREG:$rT), (vectype xform:$val))]>; + +class ILARegInst: + ILAInst<(outs rclass:$rT), (ins immtype:$val), + [(set rclass:$rT, xform:$val)]>; + multiclass ImmLoadAddress { - def v2i64: ILAInst<(outs VECREG:$rT), (ins u18imm:$val), - [(set (v2i64 VECREG:$rT), v2i64Uns18Imm:$val)]>; - - def v4i32: ILAInst<(outs VECREG:$rT), (ins u18imm:$val), - [(set (v4i32 VECREG:$rT), v4i32Uns18Imm:$val)]>; - - def r64: ILAInst<(outs R64C:$rT), (ins u18imm_i64:$val), - [(set R64C:$rT, imm18:$val)]>; - - def r32: ILAInst<(outs R32C:$rT), (ins u18imm:$val), - [(set R32C:$rT, imm18:$val)]>; + def v2i64: ILAVecInst; + def v4i32: ILAVecInst; - def f32: ILAInst<(outs R32FP:$rT), (ins f18imm:$val), - [(set R32FP:$rT, fpimm18:$val)]>; + def r64: ILARegInst; + def r32: ILARegInst; + def f32: ILARegInst; + def f64: ILARegInst; - def f64: ILAInst<(outs R64FP:$rT), (ins f18imm_f64:$val), - [(set R64FP:$rT, fpimm18:$val)]>; - - def lo: ILAInst<(outs R32C:$rT), (ins symbolLo:$val), - [(set R32C:$rT, imm18:$val)]>; + def lo: ILARegInst; def lsa: ILAInst<(outs R32C:$rT), (ins symbolLSA:$val), [/* no pattern */]>; @@ -419,43 +419,41 @@ // Note that these are really two operand instructions, but they're encoded // as three operands with the first two arguments tied-to each other. -def IOHLvec: - RI16Form<0b100000110, (outs VECREG:$rT), (ins VECREG:$rS, u16imm:$val), - "iohl\t$rT, $val", ImmLoad, - [/* insert intrinsic here */]>, - RegConstraint<"$rS = $rT">, - NoEncode<"$rS">; - -def IOHLr32: - RI16Form<0b100000110, (outs R32C:$rT), (ins R32C:$rS, i32imm:$val), - "iohl\t$rT, $val", ImmLoad, - [/* insert intrinsic here */]>, - RegConstraint<"$rS = $rT">, - NoEncode<"$rS">; - -def IOHLf32: - RI16Form<0b100000110, (outs R32FP:$rT), (ins R32FP:$rS, f32imm:$val), - "iohl\t$rT, $val", ImmLoad, - [/* insert intrinsic here */]>, - RegConstraint<"$rS = $rT">, - NoEncode<"$rS">; - -def IOHLlo: - RI16Form<0b100000110, (outs R32C:$rT), (ins R32C:$rS, symbolLo:$val), - "iohl\t$rT, $val", ImmLoad, - [/* no pattern */]>, - RegConstraint<"$rS = $rT">, - NoEncode<"$rS">; +class IOHLInst pattern>: + RI16Form<0b100000110, OOL, IOL, "iohl\t$rT, $val", + ImmLoad, pattern>, + RegConstraint<"$rS = $rT">, + NoEncode<"$rS">; + +class IOHLVecInst: + IOHLInst<(outs VECREG:$rT), (ins VECREG:$rS, immtype:$val), + [/* no pattern */]>; + +class IOHLRegInst: + IOHLInst<(outs rclass:$rT), (ins rclass:$rS, immtype:$val), + [/* no pattern */]>; + +multiclass ImmOrHalfwordLower +{ + def v2i64: IOHLVecInst; + def v4i32: IOHLVecInst; + + def r32: IOHLRegInst; + def f32: IOHLRegInst; + + def lo: IOHLRegInst; +} + +defm IOHL: ImmOrHalfwordLower; // Form select mask for bytes using immediate, used in conjunction with the // SELB instruction: -class FSMBIVec - : RI16Form<0b101001100, (outs VECREG:$rT), (ins u16imm:$val), - "fsmbi\t$rT, $val", - SelectOp, - [(set (vectype VECREG:$rT), (SPUfsmbi immU16:$val))]> -{ } +class FSMBIVec: + RI16Form<0b101001100, (outs VECREG:$rT), (ins u16imm:$val), + "fsmbi\t$rT, $val", + SelectOp, + [(set (vectype VECREG:$rT), (SPUfsmbi (i32 immU16:$val)))]>; multiclass FormSelectMaskBytesImm { @@ -470,22 +468,22 @@ // fsmb: Form select mask for bytes. N.B. Input operand, $rA, is 16-bits def FSMB: RRForm_1<0b01101101100, (outs VECREG:$rT), (ins R16C:$rA), - "fsmb\t$rT, $rA", SelectOp, - []>; + "fsmb\t$rT, $rA", SelectOp, + [(set (v16i8 VECREG:$rT), (SPUfsmbi R16C:$rA))]>; // fsmh: Form select mask for halfwords. N.B., Input operand, $rA, is // only 8-bits wide (even though it's input as 16-bits here) def FSMH: RRForm_1<0b10101101100, (outs VECREG:$rT), (ins R16C:$rA), "fsmh\t$rT, $rA", SelectOp, - []>; + [(set (v8i16 VECREG:$rT), (SPUfsmbi R16C:$rA))]>; // fsm: Form select mask for words. Like the other fsm* instructions, // only the lower 4 bits of $rA are significant. def FSM: RRForm_1<0b00101101100, (outs VECREG:$rT), (ins R16C:$rA), "fsm\t$rT, $rA", SelectOp, - []>; + [(set (v4i32 VECREG:$rT), (SPUfsmbi R16C:$rA))]>; //===----------------------------------------------------------------------===// // Integer and Logical Operations: @@ -926,6 +924,10 @@ [(set (vectype VECREG:$rT), (and (vectype VECREG:$rA), (vectype VECREG:$rB)))]>; +class ANDRegInst: + ANDInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB), + [(set rclass:$rT, (and rclass:$rA, rclass:$rB))]>; + multiclass BitwiseAnd { def v16i8: ANDVecInst; @@ -933,17 +935,11 @@ def v4i32: ANDVecInst; def v2i64: ANDVecInst; - def r64: ANDInst<(outs R64C:$rT), (ins R64C:$rA, R64C:$rB), - [(set R64C:$rT, (and R64C:$rA, R64C:$rB))]>; - - def r32: ANDInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB), - [(set R32C:$rT, (and R32C:$rA, R32C:$rB))]>; - - def r16: ANDInst<(outs R16C:$rT), (ins R16C:$rA, R16C:$rB), - [(set R16C:$rT, (and R16C:$rA, R16C:$rB))]>; - - def r8: ANDInst<(outs R8C:$rT), (ins R8C:$rA, R8C:$rB), - [(set R8C:$rT, (and R8C:$rA, R8C:$rB))]>; + def r128: ANDRegInst; + def r64: ANDRegInst; + def r32: ANDRegInst; + def r16: ANDRegInst; + def r8: ANDRegInst; //===--------------------------------------------- // Special instructions to perform the fabs instruction @@ -1323,61 +1319,49 @@ []>; // XOR: -def XORv16i8: - RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "xor\t$rT, $rA, $rB", IntegerOp, - [(set (v16i8 VECREG:$rT), (xor (v16i8 VECREG:$rA), (v16i8 VECREG:$rB)))]>; -def XORv8i16: - RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "xor\t$rT, $rA, $rB", IntegerOp, - [(set (v8i16 VECREG:$rT), (xor (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)))]>; +class XORInst pattern> : + RRForm<0b10010010000, OOL, IOL, "xor\t$rT, $rA, $rB", + IntegerOp, pattern>; -def XORv4i32: - RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "xor\t$rT, $rA, $rB", IntegerOp, - [(set (v4i32 VECREG:$rT), (xor (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>; +class XORVecInst: + XORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + [(set (vectype VECREG:$rT), (xor (vectype VECREG:$rA), + (vectype VECREG:$rB)))]>; -def XORr32: - RRForm<0b10010010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB), - "xor\t$rT, $rA, $rB", IntegerOp, - [(set R32C:$rT, (xor R32C:$rA, R32C:$rB))]>; +class XORRegInst: + XORInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB), + [(set rclass:$rT, (xor rclass:$rA, rclass:$rB))]>; -//==---------------------------------------------------------- -// Special forms for floating point instructions. -// Bitwise ORs and ANDs don't make sense for normal floating -// point numbers. These operations (fneg and fabs), however, -// require bitwise logical ops to manipulate the sign bit. -def XORfneg32: - RRForm<0b10010010000, (outs R32FP:$rT), (ins R32FP:$rA, R32C:$rB), - "xor\t$rT, $rA, $rB", IntegerOp, - [/* Intentionally does not match a pattern, see fneg32 */]>; - -// KLUDGY! Better way to do this without a VECREG? bitconvert? -// VECREG is assumed to contain two identical 64-bit masks, so -// it doesn't matter which word we select for the xor -def XORfneg64: - RRForm<0b10010010000, (outs R64FP:$rT), (ins R64FP:$rA, VECREG:$rB), - "xor\t$rT, $rA, $rB", IntegerOp, - [/* Intentionally does not match a pattern, see fneg64 */]>; +multiclass BitwiseExclusiveOr +{ + def v16i8: XORVecInst; + def v8i16: XORVecInst; + def v4i32: XORVecInst; + def v2i64: XORVecInst; -// Could use XORv4i32, but will use this for clarity -def XORfnegvec: - RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "xor\t$rT, $rA, $rB", IntegerOp, - [/* Intentionally does not match a pattern, see fneg{32,64} */]>; + def r128: XORRegInst; + def r64: XORRegInst; + def r32: XORRegInst; + def r16: XORRegInst; + def r8: XORRegInst; -//==---------------------------------------------------------- + // Special forms for floating point instructions. + // fneg and fabs require bitwise logical ops to manipulate the sign bit. -def XORr16: - RRForm<0b10010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB), - "xor\t$rT, $rA, $rB", IntegerOp, - [(set R16C:$rT, (xor R16C:$rA, R16C:$rB))]>; + def fneg32: XORInst<(outs R32FP:$rT), (ins R32FP:$rA, R32C:$rB), + [/* no pattern */]>; -def XORr8: - RRForm<0b10010010000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB), - "xor\t$rT, $rA, $rB", IntegerOp, - [(set R8C:$rT, (xor R8C:$rA, R8C:$rB))]>; + def fneg64: XORInst<(outs R64FP:$rT), (ins R64FP:$rA, VECREG:$rB), + [/* no pattern */]>; + + def fnegvec: XORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + [/* no pattern, see fneg{32,64} */]>; +} + +defm XOR : BitwiseExclusiveOr; + +//==---------------------------------------------------------- class XORBIInst pattern>: RI10Form<0b01100000, OOL, IOL, "xorbi\t$rT, $rA, $val", @@ -1486,433 +1470,156 @@ "nor\t$rT, $rA, $rB", IntegerOp, [(set R8C:$rT, (not (or R8C:$rA, R8C:$rB)))]>; -// EQV: Equivalence (1 for each same bit, otherwise 0) -def EQVv16i8: - RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "eqv\t$rT, $rA, $rB", IntegerOp, - [(set (v16i8 VECREG:$rT), (or (and (v16i8 VECREG:$rA), - (v16i8 VECREG:$rB)), - (and (vnot (v16i8 VECREG:$rA)), - (vnot (v16i8 VECREG:$rB)))))]>; - -def : Pat<(xor (v16i8 VECREG:$rA), (vnot (v16i8 VECREG:$rB))), - (EQVv16i8 VECREG:$rA, VECREG:$rB)>; - -def : Pat<(xor (vnot (v16i8 VECREG:$rA)), (v16i8 VECREG:$rB)), - (EQVv16i8 VECREG:$rA, VECREG:$rB)>; - -def EQVv8i16: - RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "eqv\t$rT, $rA, $rB", IntegerOp, - [(set (v8i16 VECREG:$rT), (or (and (v8i16 VECREG:$rA), - (v8i16 VECREG:$rB)), - (and (vnot (v8i16 VECREG:$rA)), - (vnot (v8i16 VECREG:$rB)))))]>; - -def : Pat<(xor (v8i16 VECREG:$rA), (vnot (v8i16 VECREG:$rB))), - (EQVv8i16 VECREG:$rA, VECREG:$rB)>; - -def : Pat<(xor (vnot (v8i16 VECREG:$rA)), (v8i16 VECREG:$rB)), - (EQVv8i16 VECREG:$rA, VECREG:$rB)>; - -def EQVv4i32: - RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), - "eqv\t$rT, $rA, $rB", IntegerOp, - [(set (v4i32 VECREG:$rT), (or (and (v4i32 VECREG:$rA), - (v4i32 VECREG:$rB)), - (and (vnot (v4i32 VECREG:$rA)), - (vnot (v4i32 VECREG:$rB)))))]>; - -def : Pat<(xor (v4i32 VECREG:$rA), (vnot (v4i32 VECREG:$rB))), - (EQVv4i32 VECREG:$rA, VECREG:$rB)>; - -def : Pat<(xor (vnot (v4i32 VECREG:$rA)), (v4i32 VECREG:$rB)), - (EQVv4i32 VECREG:$rA, VECREG:$rB)>; - -def EQVr32: - RRForm<0b10010010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB), - "eqv\t$rT, $rA, $rB", IntegerOp, - [(set R32C:$rT, (or (and R32C:$rA, R32C:$rB), - (and (not R32C:$rA), (not R32C:$rB))))]>; - -def : Pat<(xor R32C:$rA, (not R32C:$rB)), - (EQVr32 R32C:$rA, R32C:$rB)>; - -def : Pat<(xor (not R32C:$rA), R32C:$rB), - (EQVr32 R32C:$rA, R32C:$rB)>; - -def EQVr16: - RRForm<0b10010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB), - "eqv\t$rT, $rA, $rB", IntegerOp, - [(set R16C:$rT, (or (and R16C:$rA, R16C:$rB), - (and (not R16C:$rA), (not R16C:$rB))))]>; - -def : Pat<(xor R16C:$rA, (not R16C:$rB)), - (EQVr16 R16C:$rA, R16C:$rB)>; - -def : Pat<(xor (not R16C:$rA), R16C:$rB), - (EQVr16 R16C:$rA, R16C:$rB)>; - -def EQVr8: - RRForm<0b10010010000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB), - "eqv\t$rT, $rA, $rB", IntegerOp, - [(set R8C:$rT, (or (and R8C:$rA, R8C:$rB), - (and (not R8C:$rA), (not R8C:$rB))))]>; - -def : Pat<(xor R8C:$rA, (not R8C:$rB)), - (EQVr8 R8C:$rA, R8C:$rB)>; - -def : Pat<(xor (not R8C:$rA), R8C:$rB), - (EQVr8 R8C:$rA, R8C:$rB)>; - -// gcc optimizes (p & q) | (~p & ~q) -> ~(p | q) | (p & q), so match that -// pattern also: -def : Pat<(or (vnot (or (v16i8 VECREG:$rA), (v16i8 VECREG:$rB))), - (and (v16i8 VECREG:$rA), (v16i8 VECREG:$rB))), - (EQVv16i8 VECREG:$rA, VECREG:$rB)>; - -def : Pat<(or (vnot (or (v8i16 VECREG:$rA), (v8i16 VECREG:$rB))), - (and (v8i16 VECREG:$rA), (v8i16 VECREG:$rB))), - (EQVv8i16 VECREG:$rA, VECREG:$rB)>; - -def : Pat<(or (vnot (or (v4i32 VECREG:$rA), (v4i32 VECREG:$rB))), - (and (v4i32 VECREG:$rA), (v4i32 VECREG:$rB))), - (EQVv4i32 VECREG:$rA, VECREG:$rB)>; - -def : Pat<(or (not (or R32C:$rA, R32C:$rB)), (and R32C:$rA, R32C:$rB)), - (EQVr32 R32C:$rA, R32C:$rB)>; - -def : Pat<(or (not (or R16C:$rA, R16C:$rB)), (and R16C:$rA, R16C:$rB)), - (EQVr16 R16C:$rA, R16C:$rB)>; - -def : Pat<(or (not (or R8C:$rA, R8C:$rB)), (and R8C:$rA, R8C:$rB)), - (EQVr8 R8C:$rA, R8C:$rB)>; - // Select bits: -def SELBv16i8: - RRRForm<0b1000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC), - "selb\t$rT, $rA, $rB, $rC", IntegerOp, - [(set (v16i8 VECREG:$rT), - (SPUselb (v16i8 VECREG:$rA), (v16i8 VECREG:$rB), - (v16i8 VECREG:$rC)))]>; - -def : Pat<(or (and (v16i8 VECREG:$rA), (v16i8 VECREG:$rC)), - (and (v16i8 VECREG:$rB), (vnot (v16i8 VECREG:$rC)))), - (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v16i8 VECREG:$rC), (v16i8 VECREG:$rA)), - (and (v16i8 VECREG:$rB), (vnot (v16i8 VECREG:$rC)))), - (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v16i8 VECREG:$rA), (v16i8 VECREG:$rC)), - (and (vnot (v16i8 VECREG:$rC)), (v16i8 VECREG:$rB))), - (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v16i8 VECREG:$rC), (v16i8 VECREG:$rA)), - (and (vnot (v16i8 VECREG:$rC)), (v16i8 VECREG:$rB))), - (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v16i8 VECREG:$rA), (vnot (v16i8 VECREG:$rC))), - (and (v16i8 VECREG:$rB), (v16i8 VECREG:$rC))), - (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v16i8 VECREG:$rA), (vnot (v16i8 VECREG:$rC))), - (and (v16i8 VECREG:$rC), (v16i8 VECREG:$rB))), - (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (vnot (v16i8 VECREG:$rC)), (v16i8 VECREG:$rA)), - (and (v16i8 VECREG:$rB), (v16i8 VECREG:$rC))), - (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (vnot (v16i8 VECREG:$rC)), (v16i8 VECREG:$rA)), - (and (v16i8 VECREG:$rC), (v16i8 VECREG:$rB))), - (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v16i8 VECREG:$rA), (v16i8 VECREG:$rC)), - (and (v16i8 VECREG:$rB), (vnot (v16i8 VECREG:$rC)))), - (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v16i8 VECREG:$rC), (v16i8 VECREG:$rA)), - (and (v16i8 VECREG:$rB), (vnot (v16i8 VECREG:$rC)))), - (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v16i8 VECREG:$rA), (v16i8 VECREG:$rC)), - (and (vnot (v16i8 VECREG:$rC)), (v16i8 VECREG:$rB))), - (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v16i8 VECREG:$rC), (v16i8 VECREG:$rA)), - (and (vnot (v16i8 VECREG:$rC)), (v16i8 VECREG:$rB))), - (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v16i8 VECREG:$rA), (vnot (v16i8 VECREG:$rC))), - (and (v16i8 VECREG:$rB), (v16i8 VECREG:$rC))), - (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v16i8 VECREG:$rA), (vnot (v16i8 VECREG:$rC))), - (and (v16i8 VECREG:$rC), (v16i8 VECREG:$rB))), - (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (vnot (v16i8 VECREG:$rC)), (v16i8 VECREG:$rA)), - (and (v16i8 VECREG:$rB), (v16i8 VECREG:$rC))), - (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (vnot (v16i8 VECREG:$rC)), (v16i8 VECREG:$rA)), - (and (v16i8 VECREG:$rC), (v16i8 VECREG:$rB))), - (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def SELBv8i16: - RRRForm<0b1000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC), - "selb\t$rT, $rA, $rB, $rC", IntegerOp, - [(set (v8i16 VECREG:$rT), - (SPUselb (v8i16 VECREG:$rA), (v8i16 VECREG:$rB), - (v8i16 VECREG:$rC)))]>; +class SELBInst pattern>: + RRRForm<0b1000, OOL, IOL, "selb\t$rT, $rA, $rB, $rC", + IntegerOp, pattern>; -def : Pat<(or (and (v8i16 VECREG:$rA), (v8i16 VECREG:$rC)), - (and (v8i16 VECREG:$rB), (vnot (v8i16 VECREG:$rC)))), - (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v8i16 VECREG:$rC), (v8i16 VECREG:$rA)), - (and (v8i16 VECREG:$rB), (vnot (v8i16 VECREG:$rC)))), - (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v8i16 VECREG:$rA), (v8i16 VECREG:$rC)), - (and (vnot (v8i16 VECREG:$rC)), (v8i16 VECREG:$rB))), - (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v8i16 VECREG:$rC), (v8i16 VECREG:$rA)), - (and (vnot (v8i16 VECREG:$rC)), (v8i16 VECREG:$rB))), - (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v8i16 VECREG:$rA), (vnot (v8i16 VECREG:$rC))), - (and (v8i16 VECREG:$rB), (v8i16 VECREG:$rC))), - (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v8i16 VECREG:$rA), (vnot (v8i16 VECREG:$rC))), - (and (v8i16 VECREG:$rC), (v8i16 VECREG:$rB))), - (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (vnot (v8i16 VECREG:$rC)), (v8i16 VECREG:$rA)), - (and (v8i16 VECREG:$rB), (v8i16 VECREG:$rC))), - (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (vnot (v8i16 VECREG:$rC)), (v8i16 VECREG:$rA)), - (and (v8i16 VECREG:$rC), (v8i16 VECREG:$rB))), - (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v8i16 VECREG:$rA), (v8i16 VECREG:$rC)), - (and (v8i16 VECREG:$rB), (vnot (v8i16 VECREG:$rC)))), - (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v8i16 VECREG:$rC), (v8i16 VECREG:$rA)), - (and (v8i16 VECREG:$rB), (vnot (v8i16 VECREG:$rC)))), - (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v8i16 VECREG:$rA), (v8i16 VECREG:$rC)), - (and (vnot (v8i16 VECREG:$rC)), (v8i16 VECREG:$rB))), - (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v8i16 VECREG:$rC), (v8i16 VECREG:$rA)), - (and (vnot (v8i16 VECREG:$rC)), (v8i16 VECREG:$rB))), - (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v8i16 VECREG:$rA), (vnot (v8i16 VECREG:$rC))), - (and (v8i16 VECREG:$rB), (v8i16 VECREG:$rC))), - (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v8i16 VECREG:$rA), (vnot (v8i16 VECREG:$rC))), - (and (v8i16 VECREG:$rC), (v8i16 VECREG:$rB))), - (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (vnot (v8i16 VECREG:$rC)), (v8i16 VECREG:$rA)), - (and (v8i16 VECREG:$rB), (v8i16 VECREG:$rC))), - (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (vnot (v8i16 VECREG:$rC)), (v8i16 VECREG:$rA)), - (and (v8i16 VECREG:$rC), (v8i16 VECREG:$rB))), - (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def SELBv4i32: - RRRForm<0b1000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC), - "selb\t$rT, $rA, $rB, $rC", IntegerOp, - [(set (v4i32 VECREG:$rT), - (SPUselb (v4i32 VECREG:$rA), (v4i32 VECREG:$rB), - (v4i32 VECREG:$rC)))]>; +class SELBVecInst: + SELBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC), + [(set (vectype VECREG:$rT), + (or (and (vectype VECREG:$rC), (vectype VECREG:$rB)), + (and (vnot (vectype VECREG:$rC)), + (vectype VECREG:$rA))))]>; + +class SELBRegInst: + SELBInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB, rclass:$rC), + [(set rclass:$rT, + (or (and rclass:$rA, rclass:$rC), + (and rclass:$rB, (not rclass:$rC))))]>; + +multiclass SelectBits +{ + def v16i8: SELBVecInst; + def v8i16: SELBVecInst; + def v4i32: SELBVecInst; + def v2i64: SELBVecInst; + + def r128: SELBRegInst; + def r64: SELBRegInst; + def r32: SELBRegInst; + def r16: SELBRegInst; + def r8: SELBRegInst; +} + +defm SELB : SelectBits; + +class SPUselbPat: + Pat<(SPUselb (vectype VECREG:$rA), (vectype VECREG:$rB), (vectype VECREG:$rC)), + (inst VECREG:$rA, VECREG:$rB, VECREG:$rC)>; + +def : SPUselbPat; +def : SPUselbPat; +def : SPUselbPat; +def : SPUselbPat; + +class SelectConditional: + Pat<(select rclass:$rCond, rclass:$rTrue, rclass:$rFalse), + (inst rclass:$rCond, rclass:$rFalse, rclass:$rTrue)>; + +def : SelectConditional; +def : SelectConditional; +def : SelectConditional; -def : Pat<(or (and (v4i32 VECREG:$rA), (v4i32 VECREG:$rC)), - (and (v4i32 VECREG:$rB), (vnot (v4i32 VECREG:$rC)))), - (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v4i32 VECREG:$rC), (v4i32 VECREG:$rA)), - (and (v4i32 VECREG:$rB), (vnot (v4i32 VECREG:$rC)))), - (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v4i32 VECREG:$rA), (v4i32 VECREG:$rC)), - (and (vnot (v4i32 VECREG:$rC)), (v4i32 VECREG:$rB))), - (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v4i32 VECREG:$rC), (v4i32 VECREG:$rA)), - (and (vnot (v4i32 VECREG:$rC)), (v4i32 VECREG:$rB))), - (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v4i32 VECREG:$rA), (vnot (v4i32 VECREG:$rC))), - (and (v4i32 VECREG:$rB), (v4i32 VECREG:$rC))), - (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v4i32 VECREG:$rA), (vnot (v4i32 VECREG:$rC))), - (and (v4i32 VECREG:$rC), (v4i32 VECREG:$rB))), - (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (vnot (v4i32 VECREG:$rC)), (v4i32 VECREG:$rA)), - (and (v4i32 VECREG:$rB), (v4i32 VECREG:$rC))), - (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (vnot (v4i32 VECREG:$rC)), (v4i32 VECREG:$rA)), - (and (v4i32 VECREG:$rC), (v4i32 VECREG:$rB))), - (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v4i32 VECREG:$rA), (v4i32 VECREG:$rC)), - (and (v4i32 VECREG:$rB), (vnot (v4i32 VECREG:$rC)))), - (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v4i32 VECREG:$rC), (v4i32 VECREG:$rA)), - (and (v4i32 VECREG:$rB), (vnot (v4i32 VECREG:$rC)))), - (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v4i32 VECREG:$rA), (v4i32 VECREG:$rC)), - (and (vnot (v4i32 VECREG:$rC)), (v4i32 VECREG:$rB))), - (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v4i32 VECREG:$rC), (v4i32 VECREG:$rA)), - (and (vnot (v4i32 VECREG:$rC)), (v4i32 VECREG:$rB))), - (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v4i32 VECREG:$rA), (vnot (v4i32 VECREG:$rC))), - (and (v4i32 VECREG:$rB), (v4i32 VECREG:$rC))), - (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (v4i32 VECREG:$rA), (vnot (v4i32 VECREG:$rC))), - (and (v4i32 VECREG:$rC), (v4i32 VECREG:$rB))), - (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (vnot (v4i32 VECREG:$rC)), (v4i32 VECREG:$rA)), - (and (v4i32 VECREG:$rB), (v4i32 VECREG:$rC))), - (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def : Pat<(or (and (vnot (v4i32 VECREG:$rC)), (v4i32 VECREG:$rA)), - (and (v4i32 VECREG:$rC), (v4i32 VECREG:$rB))), - (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>; - -def SELBr32: - RRRForm<0b1000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB, R32C:$rC), - "selb\t$rT, $rA, $rB, $rC", IntegerOp, - []>; +// EQV: Equivalence (1 for each same bit, otherwise 0) +// +// Note: There are a lot of ways to match this bit operator and these patterns +// attempt to be as exhaustive as possible. -// And the various patterns that can be matched... (all 8 of them :-) -def : Pat<(or (and R32C:$rA, R32C:$rC), - (and R32C:$rB, (not R32C:$rC))), - (SELBr32 R32C:$rA, R32C:$rB, R32C:$rC)>; - -def : Pat<(or (and R32C:$rC, R32C:$rA), - (and R32C:$rB, (not R32C:$rC))), - (SELBr32 R32C:$rA, R32C:$rB, R32C:$rC)>; - -def : Pat<(or (and R32C:$rA, R32C:$rC), - (and (not R32C:$rC), R32C:$rB)), - (SELBr32 R32C:$rA, R32C:$rB, R32C:$rC)>; - -def : Pat<(or (and R32C:$rC, R32C:$rA), - (and (not R32C:$rC), R32C:$rB)), - (SELBr32 R32C:$rA, R32C:$rB, R32C:$rC)>; - -def : Pat<(or (and R32C:$rA, (not R32C:$rC)), - (and R32C:$rB, R32C:$rC)), - (SELBr32 R32C:$rA, R32C:$rB, R32C:$rC)>; - -def : Pat<(or (and R32C:$rA, (not R32C:$rC)), - (and R32C:$rC, R32C:$rB)), - (SELBr32 R32C:$rA, R32C:$rB, R32C:$rC)>; - -def : Pat<(or (and (not R32C:$rC), R32C:$rA), - (and R32C:$rB, R32C:$rC)), - (SELBr32 R32C:$rA, R32C:$rB, R32C:$rC)>; - -def : Pat<(or (and (not R32C:$rC), R32C:$rA), - (and R32C:$rC, R32C:$rB)), - (SELBr32 R32C:$rA, R32C:$rB, R32C:$rC)>; - -def SELBr16: - RRRForm<0b1000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB, R16C:$rC), - "selb\t$rT, $rA, $rB, $rC", IntegerOp, - []>; +class EQVInst pattern>: + RRForm<0b10010010000, OOL, IOL, "eqv\t$rT, $rA, $rB", + IntegerOp, pattern>; -def : Pat<(or (and R16C:$rA, R16C:$rC), - (and R16C:$rB, (not R16C:$rC))), - (SELBr16 R16C:$rA, R16C:$rB, R16C:$rC)>; - -def : Pat<(or (and R16C:$rC, R16C:$rA), - (and R16C:$rB, (not R16C:$rC))), - (SELBr16 R16C:$rA, R16C:$rB, R16C:$rC)>; - -def : Pat<(or (and R16C:$rA, R16C:$rC), - (and (not R16C:$rC), R16C:$rB)), - (SELBr16 R16C:$rA, R16C:$rB, R16C:$rC)>; - -def : Pat<(or (and R16C:$rC, R16C:$rA), - (and (not R16C:$rC), R16C:$rB)), - (SELBr16 R16C:$rA, R16C:$rB, R16C:$rC)>; - -def : Pat<(or (and R16C:$rA, (not R16C:$rC)), - (and R16C:$rB, R16C:$rC)), - (SELBr16 R16C:$rA, R16C:$rB, R16C:$rC)>; - -def : Pat<(or (and R16C:$rA, (not R16C:$rC)), - (and R16C:$rC, R16C:$rB)), - (SELBr16 R16C:$rA, R16C:$rB, R16C:$rC)>; - -def : Pat<(or (and (not R16C:$rC), R16C:$rA), - (and R16C:$rB, R16C:$rC)), - (SELBr16 R16C:$rA, R16C:$rB, R16C:$rC)>; - -def : Pat<(or (and (not R16C:$rC), R16C:$rA), - (and R16C:$rC, R16C:$rB)), - (SELBr16 R16C:$rA, R16C:$rB, R16C:$rC)>; - -def SELBr8: - RRRForm<0b1000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB, R8C:$rC), - "selb\t$rT, $rA, $rB, $rC", IntegerOp, - []>; +class EQVVecInst: + EQVInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + [(set (vectype VECREG:$rT), + (or (and (vectype VECREG:$rA), (vectype VECREG:$rB)), + (and (vnot (vectype VECREG:$rA)), + (vnot (vectype VECREG:$rB)))))]>; + +class EQVRegInst: + EQVInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB), + [(set rclass:$rT, (or (and rclass:$rA, rclass:$rB), + (and (not rclass:$rA), (not rclass:$rB))))]>; + +class EQVVecPattern1: + EQVInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + [(set (vectype VECREG:$rT), + (xor (vectype VECREG:$rA), (vnot (vectype VECREG:$rB))))]>; + +class EQVRegPattern1: + EQVInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB), + [(set rclass:$rT, (xor rclass:$rA, (not rclass:$rB)))]>; + +class EQVVecPattern2: + EQVInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + [(set (vectype VECREG:$rT), + (or (and (vectype VECREG:$rA), (vectype VECREG:$rB)), + (vnot (or (vectype VECREG:$rA), (vectype VECREG:$rB)))))]>; + +class EQVRegPattern2: + EQVInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB), + [(set rclass:$rT, + (or (and rclass:$rA, rclass:$rB), + (not (or rclass:$rA, rclass:$rB))))]>; + +class EQVVecPattern3: + EQVInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), + [(set (vectype VECREG:$rT), + (not (xor (vectype VECREG:$rA), (vectype VECREG:$rB))))]>; + +class EQVRegPattern3: + EQVInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB), + [(set rclass:$rT, (not (xor rclass:$rA, rclass:$rB)))]>; + +multiclass BitEquivalence +{ + def v16i8: EQVVecInst; + def v8i16: EQVVecInst; + def v4i32: EQVVecInst; + def v2i64: EQVVecInst; + + def v16i8_1: EQVVecPattern1; + def v8i16_1: EQVVecPattern1; + def v4i32_1: EQVVecPattern1; + def v2i64_1: EQVVecPattern1; + + def v16i8_2: EQVVecPattern2; + def v8i16_2: EQVVecPattern2; + def v4i32_2: EQVVecPattern2; + def v2i64_2: EQVVecPattern2; + + def v16i8_3: EQVVecPattern3; + def v8i16_3: EQVVecPattern3; + def v4i32_3: EQVVecPattern3; + def v2i64_3: EQVVecPattern3; + + def r128: EQVRegInst; + def r64: EQVRegInst; + def r32: EQVRegInst; + def r16: EQVRegInst; + def r8: EQVRegInst; + + def r128_1: EQVRegPattern1; + def r64_1: EQVRegPattern1; + def r32_1: EQVRegPattern1; + def r16_1: EQVRegPattern1; + def r8_1: EQVRegPattern1; + + def r128_2: EQVRegPattern2; + def r64_2: EQVRegPattern2; + def r32_2: EQVRegPattern2; + def r16_2: EQVRegPattern2; + def r8_2: EQVRegPattern2; + + def r128_3: EQVRegPattern3; + def r64_3: EQVRegPattern3; + def r32_3: EQVRegPattern3; + def r16_3: EQVRegPattern3; + def r8_3: EQVRegPattern3; +} -def : Pat<(or (and R8C:$rA, R8C:$rC), - (and R8C:$rB, (not R8C:$rC))), - (SELBr8 R8C:$rA, R8C:$rB, R8C:$rC)>; - -def : Pat<(or (and R8C:$rC, R8C:$rA), - (and R8C:$rB, (not R8C:$rC))), - (SELBr8 R8C:$rA, R8C:$rB, R8C:$rC)>; - -def : Pat<(or (and R8C:$rA, R8C:$rC), - (and (not R8C:$rC), R8C:$rB)), - (SELBr8 R8C:$rA, R8C:$rB, R8C:$rC)>; - -def : Pat<(or (and R8C:$rC, R8C:$rA), - (and (not R8C:$rC), R8C:$rB)), - (SELBr8 R8C:$rA, R8C:$rB, R8C:$rC)>; - -def : Pat<(or (and R8C:$rA, (not R8C:$rC)), - (and R8C:$rB, R8C:$rC)), - (SELBr8 R8C:$rA, R8C:$rB, R8C:$rC)>; - -def : Pat<(or (and R8C:$rA, (not R8C:$rC)), - (and R8C:$rC, R8C:$rB)), - (SELBr8 R8C:$rA, R8C:$rB, R8C:$rC)>; - -def : Pat<(or (and (not R8C:$rC), R8C:$rA), - (and R8C:$rB, R8C:$rC)), - (SELBr8 R8C:$rA, R8C:$rB, R8C:$rC)>; - -def : Pat<(or (and (not R8C:$rC), R8C:$rA), - (and R8C:$rC, R8C:$rB)), - (SELBr8 R8C:$rA, R8C:$rB, R8C:$rC)>; +defm EQV: BitEquivalence; //===----------------------------------------------------------------------===// // Vector shuffle... @@ -3062,7 +2769,7 @@ } class CLGTBInst pattern> : - RRForm<0b00001011010, OOL, IOL, "cgtb\t$rT, $rA, $rB", + RRForm<0b00001011010, OOL, IOL, "clgtb\t$rT, $rA, $rB", ByteOp, pattern>; multiclass CmpLGtrByte @@ -3078,7 +2785,7 @@ } class CLGTBIInst pattern> : - RI10Form<0b01111010, OOL, IOL, "cgtbi\t$rT, $rA, $val", + RI10Form<0b01111010, OOL, IOL, "clgtbi\t$rT, $rA, $val", ByteOp, pattern>; multiclass CmpLGtrByteImm @@ -3093,7 +2800,7 @@ } class CLGTHInst pattern> : - RRForm<0b00010011010, OOL, IOL, "cgth\t$rT, $rA, $rB", + RRForm<0b00010011010, OOL, IOL, "clgth\t$rT, $rA, $rB", ByteOp, pattern>; multiclass CmpLGtrHalfword @@ -3107,7 +2814,7 @@ } class CLGTHIInst pattern> : - RI10Form<0b10111010, OOL, IOL, "cgthi\t$rT, $rA, $val", + RI10Form<0b10111010, OOL, IOL, "clgthi\t$rT, $rA, $val", ByteOp, pattern>; multiclass CmpLGtrHalfwordImm @@ -3121,7 +2828,7 @@ } class CLGTInst pattern> : - RRForm<0b00000011010, OOL, IOL, "cgt\t$rT, $rA, $rB", + RRForm<0b00000011010, OOL, IOL, "clgt\t$rT, $rA, $rB", ByteOp, pattern>; multiclass CmpLGtrWord @@ -3135,7 +2842,7 @@ } class CLGTIInst pattern> : - RI10Form<0b00111010, OOL, IOL, "cgti\t$rT, $rA, $val", + RI10Form<0b00111010, OOL, IOL, "clgti\t$rT, $rA, $val", ByteOp, pattern>; multiclass CmpLGtrWordImm @@ -3146,7 +2853,7 @@ (v4i32 v4i32SExt16Imm:$val)))]>; def r32: CLGTIInst<(outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val), - [(set R32C:$rT, (setugt R32C:$rA, i32ImmSExt10:$val))]>; + [(set R32C:$rT, (setugt R32C:$rA, i32ImmSExt10:$val))]>; } defm CEQB : CmpEqualByte; @@ -3193,25 +2900,28 @@ def CLTBr8: SETCCBinOpReg; def CLTBIr8: SETCCBinOpImm; def CLTEQr8: Pat<(setle R8C:$rA, R8C:$rB), - (XORBIr8 (CGTBIr8 R8C:$rA, R8C:$rB), 0xff)>; + (XORBIr8 (CGTBr8 R8C:$rA, R8C:$rB), 0xff)>; def CLTEQIr8: Pat<(setle R8C:$rA, immU8:$imm), (XORBIr8 (CGTBIr8 R8C:$rA, immU8:$imm), 0xff)>; -def CGTEQHr16: SETCCBinOpReg; +def CGTEQHr16: SETCCBinOpReg; def CGTEQHIr16: SETCCBinOpImm; +def CLTHr16: SETCCBinOpReg; +def CLTHIr16: SETCCBinOpImm; def CLTEQr16: Pat<(setle R16C:$rA, R16C:$rB), - (XORHIr16 (CGTHIr16 R16C:$rA, R16C:$rB), 0xffff)>; -def CLTEQIr16: Pat<(setle R16C:$rA, i16ImmUns10:$imm), + (XORHIr16 (CGTHr16 R16C:$rA, R16C:$rB), 0xffff)>; +def CLTEQIr16: Pat<(setle R16C:$rA, i16ImmSExt10:$imm), (XORHIr16 (CGTHIr16 R16C:$rA, i16ImmSExt10:$imm), 0xffff)>; - -def CGTEQHr32: SETCCBinOpReg; -def CGTEQHIr32: SETCCBinOpImm; +def CGTEQHIr32: SETCCBinOpImm; +def CLTr32: SETCCBinOpReg; +def CLTIr32: SETCCBinOpImm; def CLTEQr32: Pat<(setle R32C:$rA, R32C:$rB), - (XORIr32 (CGTIr32 R32C:$rA, R32C:$rB), 0xffffffff)>; -def CLTEQIr32: Pat<(setle R32C:$rA, i32ImmUns10:$imm), + (XORIr32 (CGTr32 R32C:$rA, R32C:$rB), 0xffffffff)>; +def CLTEQIr32: Pat<(setle R32C:$rA, i32ImmSExt10:$imm), (XORIr32 (CGTIr32 R32C:$rA, i32ImmSExt10:$imm), 0xffffffff)>; def CLGTEQBr8: SETCCBinOpReg; @@ -3219,26 +2929,30 @@ def CLLTBr8: SETCCBinOpReg; def CLLTBIr8: SETCCBinOpImm; def CLLTEQr8: Pat<(setule R8C:$rA, R8C:$rB), - (XORBIr8 (CLGTBIr8 R8C:$rA, R8C:$rB), 0xff)>; + (XORBIr8 (CLGTBr8 R8C:$rA, R8C:$rB), 0xff)>; def CLLTEQIr8: Pat<(setule R8C:$rA, immU8:$imm), (XORBIr8 (CLGTBIr8 R8C:$rA, immU8:$imm), 0xff)>; -def CLGTEQHr16: SETCCBinOpReg; +def CLGTEQHr16: SETCCBinOpReg; def CLGTEQHIr16: SETCCBinOpImm; + ORr16, CLGTHIr16, CEQHIr16>; +def CLLTHr16: SETCCBinOpReg; +def CLLTHIr16: SETCCBinOpImm; def CLLTEQr16: Pat<(setule R16C:$rA, R16C:$rB), - (XORHIr16 (CLGTHIr16 R16C:$rA, R16C:$rB), 0xffff)>; + (XORHIr16 (CLGTHr16 R16C:$rA, R16C:$rB), 0xffff)>; def CLLTEQIr16: Pat<(setule R16C:$rA, i16ImmUns10:$imm), - (XORHIr16 (CLGTHIr16 R16C:$rA, i16ImmSExt10:$imm), 0xffff)>; + (XORHIr16 (CLGTHIr16 R16C:$rA, i16ImmSExt10:$imm), 0xffff)>; -def CLGTEQHr32: SETCCBinOpReg; +def CLGTEQHr32: SETCCBinOpReg; def CLGTEQHIr32: SETCCBinOpImm; + ORr32, CLGTIr32, CEQIr32>; +def CLLTr32: SETCCBinOpReg; +def CLLTIr32: SETCCBinOpImm; def CLLTEQr32: Pat<(setule R32C:$rA, R32C:$rB), - (XORIr32 (CLGTIr32 R32C:$rA, R32C:$rB), 0xffffffff)>; -def CLLTEQIr32: Pat<(setule R32C:$rA, i32ImmUns10:$imm), - (XORIr32 (CLGTIr32 R32C:$rA, i32ImmSExt10:$imm), 0xffffffff)>; + (XORIr32 (CLGTr32 R32C:$rA, R32C:$rB), 0xffffffff)>; +def CLLTEQIr32: Pat<(setule R32C:$rA, i32ImmSExt10:$imm), + (XORIr32 (CLGTIr32 R32C:$rA, i32ImmSExt10:$imm), 0xffffffff)>; //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ @@ -3959,8 +3673,8 @@ // General constant 32-bit vectors def : Pat<(v4i32 v4i32Imm:$imm), - (IOHLvec (v4i32 (ILHUv4i32 (HI16_vec v4i32Imm:$imm))), - (LO16_vec v4i32Imm:$imm))>; + (IOHLv4i32 (v4i32 (ILHUv4i32 (HI16_vec v4i32Imm:$imm))), + (LO16_vec v4i32Imm:$imm))>; // 8-bit constants def : Pat<(i8 imm:$imm), Modified: llvm/trunk/lib/Target/CellSPU/SPUNodes.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUNodes.td?rev=47973&r1=47972&r2=47973&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUNodes.td (original) +++ llvm/trunk/lib/Target/CellSPU/SPUNodes.td Wed Mar 5 17:02:02 2008 @@ -59,7 +59,7 @@ // FSMBI type constraints: There are several variations for the various // vector types (this avoids having to bit_convert all over the place.) def SPUfsmbi_type: SDTypeProfile<1, 1, [ - SDTCisVT<1, i32>]>; + /* SDTCisVT<1, i32> */ SDTCisInt<1>]>; // SELB type constraints: def SPUselb_type: SDTypeProfile<1, 3, [ Modified: llvm/trunk/lib/Target/CellSPU/SPUOperands.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUOperands.td?rev=47973&r1=47972&r2=47973&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUOperands.td (original) +++ llvm/trunk/lib/Target/CellSPU/SPUOperands.td Wed Mar 5 17:02:02 2008 @@ -141,7 +141,7 @@ }]>; def lo16 : PatLeaf<(imm), [{ - // hi16 predicate - returns true if the immediate has all zeros in the + // lo16 predicate - returns true if the immediate has all zeros in the // low order bits and is a 32-bit constant: if (N->getValueType(0) == MVT::i32) { uint32_t val = N->getValue(); @@ -155,8 +155,11 @@ // hi16 predicate - returns true if the immediate has all zeros in the // low order bits and is a 32-bit constant: if (N->getValueType(0) == MVT::i32) { - uint32_t val = N->getValue(); + uint32_t val = uint32_t(N->getValue()); return ((val & 0xffff0000) == val); + } else if (N->getValueType(0) == MVT::i64) { + uint64_t val = N->getValue(); + return ((val & 0xffff0000ULL) == val); } return false; @@ -503,6 +506,10 @@ let PrintMethod = "printS16ImmOperand"; } +def u16imm_i64 : Operand { + let PrintMethod = "printU16ImmOperand"; +} + def u16imm : Operand { let PrintMethod = "printU16ImmOperand"; } From asl at math.spbu.ru Wed Mar 5 17:08:16 2008 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Wed, 05 Mar 2008 23:08:16 -0000 Subject: [llvm-commits] [llvm] r47974 - /llvm/trunk/lib/Linker/LinkModules.cpp Message-ID: <200803052308.m25N8H5G028692@zion.cs.uiuc.edu> Author: asl Date: Wed Mar 5 17:08:16 2008 New Revision: 47974 URL: http://llvm.org/viewvc/llvm-project?rev=47974&view=rev Log: Handle functions as targets during linking of aliases as well Modified: llvm/trunk/lib/Linker/LinkModules.cpp Modified: llvm/trunk/lib/Linker/LinkModules.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Linker/LinkModules.cpp?rev=47974&r1=47973&r2=47974&view=diff ============================================================================== --- llvm/trunk/lib/Linker/LinkModules.cpp (original) +++ llvm/trunk/lib/Linker/LinkModules.cpp Wed Mar 5 17:08:16 2008 @@ -623,6 +623,7 @@ } else if (GlobalVariable *DGV = Dest->getGlobalVariable(SGA->getName())) { RecursiveResolveTypes(SGA->getType(), DGV->getType(), &Dest->getTypeSymbolTable(), ""); + // The only allowed way is to link alias with external declaration. if (DGV->isDeclaration()) { NewGA = new GlobalAlias(SGA->getType(), SGA->getLinkage(), @@ -649,7 +650,30 @@ } else if (Function *DF = Dest->getFunction(SGA->getName())) { RecursiveResolveTypes(SGA->getType(), DF->getType(), &Dest->getTypeSymbolTable(), ""); - assert(0 && "FIXME"); + + // The only allowed way is to link alias with external declaration. + if (DF->isDeclaration()) { + NewGA = new GlobalAlias(SGA->getType(), SGA->getLinkage(), + SGA->getName(), DAliasee, Dest); + CopyGVAttributes(NewGA, SGA); + + // Any uses of DF need to change to NewGA, with cast, if needed. + if (SGA->getType() != DF->getType()) + DF->replaceAllUsesWith(ConstantExpr::getBitCast(NewGA, + DF->getType())); + else + DF->replaceAllUsesWith(NewGA); + + // DF will conflict with NewGA because they both had the same + // name. We must erase this now so ForceRenaming doesn't assert + // because DF might not have internal linkage. + DF->eraseFromParent(); + + // Proceed to 'common' steps + } else + return Error(Err, "Alias Collision on '" + + ToStr(SGA->getType(), Src) +"':%"+SGA->getName()+ + " - symbol multiple defined"); } else { // Nothing similar found, just copy alias into destination module. From asl at math.spbu.ru Wed Mar 5 17:08:47 2008 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Wed, 05 Mar 2008 23:08:47 -0000 Subject: [llvm-commits] [llvm] r47975 - /llvm/trunk/lib/Linker/LinkModules.cpp Message-ID: <200803052308.m25N8ltp028714@zion.cs.uiuc.edu> Author: asl Date: Wed Mar 5 17:08:47 2008 New Revision: 47975 URL: http://llvm.org/viewvc/llvm-project?rev=47975&view=rev Log: Resolve aliases to aliasees, where possible Modified: llvm/trunk/lib/Linker/LinkModules.cpp Modified: llvm/trunk/lib/Linker/LinkModules.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Linker/LinkModules.cpp?rev=47975&r1=47974&r2=47975&view=diff ============================================================================== --- llvm/trunk/lib/Linker/LinkModules.cpp (original) +++ llvm/trunk/lib/Linker/LinkModules.cpp Wed Mar 5 17:08:47 2008 @@ -1159,6 +1159,9 @@ // If there were any appending global variables, link them together now. if (LinkAppendingVars(Dest, AppendingVars, ErrorMsg)) return true; + // Resolve all uses of aliases with aliasees + if (ResolveAliases(Dest)) return true; + // If the source library's module id is in the dependent library list of the // destination library, remove it since that module is now linked in. sys::Path modId; From resistor at mac.com Wed Mar 5 17:19:37 2008 From: resistor at mac.com (Owen Anderson) Date: Wed, 05 Mar 2008 23:19:37 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r47976 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Message-ID: <200803052319.m25NJcFd029026@zion.cs.uiuc.edu> Author: resistor Date: Wed Mar 5 17:19:37 2008 New Revision: 47976 URL: http://llvm.org/viewvc/llvm-project?rev=47976&view=rev Log: Reapply r47905 now that Andrew got things fixed. Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=47976&r1=47975&r2=47976&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Wed Mar 5 17:19:37 2008 @@ -4294,7 +4294,7 @@ C, C + 5); return true; } -#if defined(TARGET_ALPHA) +#if defined(TARGET_ALPHA) || defined(TARGET_386) //gcc uses many names for the sync intrinsics case BUILT_IN_VAL_COMPARE_AND_SWAP_1: case BUILT_IN_VAL_COMPARE_AND_SWAP_2: From resistor at mac.com Wed Mar 5 17:19:53 2008 From: resistor at mac.com (Owen Anderson) Date: Wed, 5 Mar 2008 17:19:53 -0600 Subject: [llvm-commits] [llvm-gcc-4.2] r47905 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp In-Reply-To: <85dfcd7f0803051150t2cc12b60h7c1c1827415af4e4@mail.gmail.com> References: <200803042118.m24LIdd4005387@zion.cs.uiuc.edu> <85dfcd7f0803050709i70959a5bu5f395d27abed6670@mail.gmail.com> <70BE3971-F2D6-4448-AED8-544D74FC94C2@mac.com> <85dfcd7f0803051026g173c4af5sb89fded6d131d82b@mail.gmail.com> <85dfcd7f0803051150t2cc12b60h7c1c1827415af4e4@mail.gmail.com> Message-ID: Yup, it works now. Reapplying. --Owen On Mar 5, 2008, at 1:50 PM, Andrew Lenharth wrote: >> On 3/5/08, Owen Anderson wrote: >>> The exact error message was: >>> > > Would you try reenabling the sync builtins and try bootstrapping? It > should be fixed now. > > Andrew > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From asl at math.spbu.ru Wed Mar 5 17:21:40 2008 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Wed, 05 Mar 2008 23:21:40 -0000 Subject: [llvm-commits] [llvm] r47977 - /llvm/trunk/lib/Linker/LinkModules.cpp Message-ID: <200803052321.m25NLeim029107@zion.cs.uiuc.edu> Author: asl Date: Wed Mar 5 17:21:39 2008 New Revision: 47977 URL: http://llvm.org/viewvc/llvm-project?rev=47977&view=rev Log: Missed patch from my last commit Modified: llvm/trunk/lib/Linker/LinkModules.cpp Modified: llvm/trunk/lib/Linker/LinkModules.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Linker/LinkModules.cpp?rev=47977&r1=47976&r2=47977&view=diff ============================================================================== --- llvm/trunk/lib/Linker/LinkModules.cpp (original) +++ llvm/trunk/lib/Linker/LinkModules.cpp Wed Mar 5 17:21:39 2008 @@ -1046,6 +1046,16 @@ return false; } +static bool ResolveAliases(Module *Dest) { + for (Module::alias_iterator I = Dest->alias_begin(), E = Dest->alias_end(); + I != E; ++I) { + GlobalValue* GV = const_cast(I->getAliasedGlobal()); + if (!GV->isDeclaration()) + I->replaceAllUsesWith(GV); + } + + return false; +} // LinkModules - This function links two modules together, with the resulting // left module modified to be the composite of the two input modules. If an From dalej at apple.com Wed Mar 5 17:31:27 2008 From: dalej at apple.com (Dale Johannesen) Date: Wed, 05 Mar 2008 23:31:27 -0000 Subject: [llvm-commits] [llvm] r47978 - /llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Message-ID: <200803052331.m25NVRv2029409@zion.cs.uiuc.edu> Author: johannes Date: Wed Mar 5 17:31:27 2008 New Revision: 47978 URL: http://llvm.org/viewvc/llvm-project?rev=47978&view=rev Log: Next bit of PPC ByVal handling; call-site code seems correct now. Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=47978&r1=47977&r2=47978&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Wed Mar 5 17:31:27 2008 @@ -1583,7 +1583,7 @@ ((Flags & ISD::ParamFlags::ByValAlign) >> ISD::ParamFlags::ByValAlignOffs); SDOperand AlignNode = DAG.getConstant(Align, MVT::i32); SDOperand SizeNode = DAG.getConstant(Size, MVT::i32); - SDOperand AlwaysInline = DAG.getConstant(1, MVT::i32); + SDOperand AlwaysInline = DAG.getConstant(0, MVT::i32); return DAG.getMemcpy(Chain, Dst, Src, SizeNode, AlignNode, AlwaysInline); } @@ -1633,6 +1633,7 @@ // These operations are automatically eliminated by the prolog/epilog pass Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes, PtrVT)); + SDOperand CallSeqStart = Chain; // Set up a copy of the stack pointer for use loading and storing any // arguments that may not fit in the registers available for argument @@ -1713,13 +1714,20 @@ SDOperand AddArg = DAG.getNode(ISD::ADD, PtrVT, Arg, Const); if (GPR_idx != NumGPRs) { SDOperand Load = DAG.getLoad(PtrVT, Chain, AddArg, NULL, 0); + MemOpChains.push_back(Load.getValue(1)); RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); if (isMachoABI) ArgOffset += PtrByteSize; } else { SDOperand AddPtr = DAG.getNode(ISD::ADD, PtrVT, PtrOff, Const); - MemOpChains.push_back(CreateCopyOfByValArgument(AddArg, AddPtr, - Chain, Flags, DAG, Size - j)); + SDOperand MemcpyCall = CreateCopyOfByValArgument(AddArg, AddPtr, + CallSeqStart.Val->getOperand(0), + Flags, DAG, Size - j); + // This must go outside the CALLSEQ_START..END. + SDOperand NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, + CallSeqStart.Val->getOperand(1)); + DAG.ReplaceAllUsesWith(CallSeqStart.Val, NewCallSeqStart.Val); + CallSeqStart = NewCallSeqStart; ArgOffset += ((Size - j + 3)/4)*4; } } From dpatel at apple.com Wed Mar 5 17:39:23 2008 From: dpatel at apple.com (Devang Patel) Date: Wed, 05 Mar 2008 23:39:23 -0000 Subject: [llvm-commits] [llvm] r47980 - /llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp Message-ID: <200803052339.m25NdNsN029651@zion.cs.uiuc.edu> Author: dpatel Date: Wed Mar 5 17:39:23 2008 New Revision: 47980 URL: http://llvm.org/viewvc/llvm-project?rev=47980&view=rev Log: Skip, for now, callsites where use of sret argument is not dominated by callsite. Modified: llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp Modified: llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp?rev=47980&r1=47979&r2=47980&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp Wed Mar 5 17:39:23 2008 @@ -171,6 +171,10 @@ // If FirstArg user is a GEP whose all users are not LoadInst then // this function F is not suitable for sret promotion. else if (GetElementPtrInst *GEP = dyn_cast(ArgI)) { + // TODO : Use dom info and insert PHINodes to collect get results + // from multiple call sites for this GEP. + if (GEP->getParent() != Call->getParent()) + return false; for (Value::use_iterator GEPI = GEP->use_begin(), GEPE = GEP->use_end(); GEPI != GEPE; ++GEPI) if (!isa(GEPI)) From alenhar2 at cs.uiuc.edu Wed Mar 5 17:41:38 2008 From: alenhar2 at cs.uiuc.edu (Andrew Lenharth) Date: Wed, 05 Mar 2008 23:41:38 -0000 Subject: [llvm-commits] [llvm] r47981 - /llvm/trunk/lib/Target/CBackend/CBackend.cpp Message-ID: <200803052341.m25NfcIg029757@zion.cs.uiuc.edu> Author: alenhar2 Date: Wed Mar 5 17:41:37 2008 New Revision: 47981 URL: http://llvm.org/viewvc/llvm-project?rev=47981&view=rev Log: gcc likes things spelled correctly Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CBackend.cpp?rev=47981&r1=47980&r2=47981&view=diff ============================================================================== --- llvm/trunk/lib/Target/CBackend/CBackend.cpp (original) +++ llvm/trunk/lib/Target/CBackend/CBackend.cpp Wed Mar 5 17:41:37 2008 @@ -2684,7 +2684,7 @@ return false; } case Intrinsic::memory_barrier: - Out << "__sync_syncronize()"; + Out << "__sync_synchronize()"; return true; case Intrinsic::vastart: Out << "0; "; From dag at cray.com Wed Mar 5 18:11:29 2008 From: dag at cray.com (David Greene) Date: Wed, 5 Mar 2008 18:11:29 -0600 Subject: [llvm-commits] Fwd: Patch for review: Speeding up ScheduleDAG computations In-Reply-To: <2DFEE2ED-2D57-4310-8F6C-1B08F18D4363@apple.com> References: <2DFEE2ED-2D57-4310-8F6C-1B08F18D4363@apple.com> Message-ID: <200803051811.29524.dag@cray.com> On Tuesday 04 March 2008 11:30, Evan Cheng wrote: > > I'd like to understand better why Evan and Chris are some much against > > std::set? From some mails I got the impression that std::set > > implementation is very inefficient on Darwin or PowerPC? Is it > > correct? Or do you dislike that fact that std::set uses dynamic memory > > allocation extensively? > > Right, it's very malloc intensive. That's the main issue. So why not define an allocator for it? -Dave From dag at cray.com Wed Mar 5 18:19:18 2008 From: dag at cray.com (David Greene) Date: Wed, 5 Mar 2008 18:19:18 -0600 Subject: [llvm-commits] Patch for review: Speeding up ScheduleDAG computations In-Reply-To: References: <6050EB9C-5859-496E-A193-727D23CAF638@apple.com> Message-ID: <200803051819.18406.dag@cray.com> On Wednesday 05 March 2008 11:16, Roman Levenstein wrote: > 1) I do run llvm/test tests. At the end I get some figures about the > number of PASSED and UNEXPECTEDLY FAILED tests. This is fine. But is > it guaranteed that UNEXPECTEDLY FAILED are introduced by my code or is > it possible that due to some recent changes to the repository some of > those tests just fail? If it is due to the changes in the repository, > how do I know what are the figures without my changes, so that I can > compare and see new failures introduced by my code? Are those numbers > published anywhere, may be in the nightly tests results??? Or should I > basically have to source trees: one for repository version and one for > my local modifications and then run tests under both trees? I find that the repository breaks rather a a lot. So what I do is keep two working copies: one official one and one with my changes. I run tests on both and compare the results. Yep, it's a pain. :( -Dave From evan.cheng at apple.com Wed Mar 5 20:11:43 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 06 Mar 2008 02:11:43 -0000 Subject: [llvm-commits] [test-suite] r47983 - /test-suite/trunk/RunSafely.sh Message-ID: <200803060211.m262BhfP001665@zion.cs.uiuc.edu> Author: evancheng Date: Wed Mar 5 20:11:43 2008 New Revision: 47983 URL: http://llvm.org/viewvc/llvm-project?rev=47983&view=rev Log: Re-apply fix for PR1437 that I accidentially removed. Modified: test-suite/trunk/RunSafely.sh Modified: test-suite/trunk/RunSafely.sh URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/RunSafely.sh?rev=47983&r1=47982&r2=47983&view=diff ============================================================================== --- test-suite/trunk/RunSafely.sh (original) +++ test-suite/trunk/RunSafely.sh Wed Mar 5 20:11:43 2008 @@ -105,7 +105,7 @@ fi if [ "x$RHOST" = x ] ; then - ( sh -c "$ULIMITCMD"; time -p sh -c "$COMMAND >$OUTFILE 2>&1 < $INFILE" ; echo exit $? ) 2>&1 \ + ( sh -c "$ULIMITCMD"; time -p "$COMMAND >$OUTFILE 2>&1 < $INFILE" ; echo exit $? ) 2>&1 \ | awk -- '\ BEGIN { cpu = 0.0; } /^user/ { cpu += $2; print; } From dalej at apple.com Wed Mar 5 20:50:06 2008 From: dalej at apple.com (Dale Johannesen) Date: Thu, 06 Mar 2008 02:50:06 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r47984 - in /llvm-gcc-4.2/trunk/gcc: config/i386/llvm-i386-target.h llvm-abi.h llvm-convert.cpp llvm-types.cpp Message-ID: <200803060250.m262o6QI002666@zion.cs.uiuc.edu> Author: johannes Date: Wed Mar 5 20:50:05 2008 New Revision: 47984 URL: http://llvm.org/viewvc/llvm-project?rev=47984&view=rev Log: Believe it or not, MMX builtins use a different calling convention from non-builtins on Darwin x86-32. Fix builtins. Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h llvm-gcc-4.2/trunk/gcc/llvm-abi.h llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp llvm-gcc-4.2/trunk/gcc/llvm-types.cpp Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h?rev=47984&r1=47983&r2=47984&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h (original) +++ llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h Wed Mar 5 20:50:05 2008 @@ -100,8 +100,9 @@ /* The MMX vector v1i64 is returned in EAX and EDX on Darwin. Communicate this by returning i64 here. */ -#define LLVM_SHOULD_RETURN_VECTOR_AS_SCALAR(X) \ +#define LLVM_SHOULD_RETURN_VECTOR_AS_SCALAR(X,isBuiltin)\ ((TARGET_MACHO && \ + !isBuiltin && \ !TARGET_64BIT && \ TREE_CODE(X) == VECTOR_TYPE && \ TYPE_SIZE(X) && \ @@ -111,8 +112,9 @@ /* MMX vectors v2i32, v4i16, v8i8, v2f32 are returned using sret on Darwin 32-bit. */ -#define LLVM_SHOULD_RETURN_VECTOR_AS_SHADOW(X) \ +#define LLVM_SHOULD_RETURN_VECTOR_AS_SHADOW(X,isBuiltin)\ ((TARGET_MACHO && \ + !isBuiltin && \ !TARGET_64BIT && \ TREE_CODE(X) == VECTOR_TYPE && \ TYPE_SIZE(X) && \ Modified: llvm-gcc-4.2/trunk/gcc/llvm-abi.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-abi.h?rev=47984&r1=47983&r2=47984&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-abi.h (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-abi.h Wed Mar 5 20:50:05 2008 @@ -199,7 +199,7 @@ // should be returned using the convention for that scalar TYPE, 0 otherwise. // X may be evaluated more than once. #ifndef LLVM_SHOULD_RETURN_VECTOR_AS_SCALAR -#define LLVM_SHOULD_RETURN_VECTOR_AS_SCALAR(X) 0 +#define LLVM_SHOULD_RETURN_VECTOR_AS_SCALAR(X,Y) 0 #endif // LLVM_SHOULD_RETURN_VECTOR_AS_SHADOW - Return true if this vector type @@ -226,14 +226,16 @@ /// return type. It potentially breaks down the argument and invokes methods /// on the client that indicate how its pieces should be handled. This /// handles things like returning structures via hidden parameters. - void HandleReturnType(tree type) { + void HandleReturnType(tree type, bool isBuiltin) { const Type *Ty = ConvertType(type); if (Ty->getTypeID() == Type::VectorTyID) { - // Vector handling is weird on x86. - tree ScalarType = LLVM_SHOULD_RETURN_VECTOR_AS_SCALAR(type); + // Vector handling is weird on x86. In particular builtin and + // non-builtin function of the same return types can use different + // calling conventions. + tree ScalarType = LLVM_SHOULD_RETURN_VECTOR_AS_SCALAR(type, isBuiltin); if (ScalarType) C.HandleAggregateResultAsScalar(ConvertType(ScalarType)); - else if (LLVM_SHOULD_RETURN_VECTOR_AS_SHADOW(type)) + else if (LLVM_SHOULD_RETURN_VECTOR_AS_SHADOW(type, isBuiltin)) C.HandleAggregateShadowArgument(PointerType::getUnqual(Ty), false); else C.HandleScalarResult(Ty); Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=47984&r1=47983&r2=47984&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Wed Mar 5 20:50:05 2008 @@ -660,7 +660,8 @@ TheLLVMABI ABIConverter(Client); // Handle the DECL_RESULT. - ABIConverter.HandleReturnType(TREE_TYPE(TREE_TYPE(FnDecl))); + ABIConverter.HandleReturnType(TREE_TYPE(TREE_TYPE(FnDecl)), + DECL_BUILT_IN(FnDecl)); // Prepend the static chain (if any) to the list of arguments. tree Args = static_chain ? static_chain : DECL_ARGUMENTS(FnDecl); @@ -2493,7 +2494,9 @@ TheLLVMABI ABIConverter(Client); // Handle the result, including struct returns. - ABIConverter.HandleReturnType(TREE_TYPE(exp)); + tree fndecl = get_callee_fndecl(exp); + ABIConverter.HandleReturnType(TREE_TYPE(exp), + fndecl ? DECL_BUILT_IN(fndecl) : false); // Pass the static chain, if any, as the first parameter. if (TREE_OPERAND(exp, 2)) Modified: llvm-gcc-4.2/trunk/gcc/llvm-types.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-types.cpp?rev=47984&r1=47983&r2=47984&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-types.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-types.cpp Wed Mar 5 20:50:05 2008 @@ -1044,7 +1044,8 @@ FunctionTypeConversion Client(RetTy, ArgTys, CallingConv, true /*K&R*/); TheLLVMABI ABIConverter(Client); - ABIConverter.HandleReturnType(ReturnType); + // Builtins are always prototyped, so this isn't one. + ABIConverter.HandleReturnType(ReturnType, false); ParamAttrsVector Attrs; @@ -1098,7 +1099,8 @@ FunctionTypeConversion Client(RetTy, ArgTypes, CallingConv, false/*not K&R*/); TheLLVMABI ABIConverter(Client); - ABIConverter.HandleReturnType(TREE_TYPE(type)); + ABIConverter.HandleReturnType(TREE_TYPE(type), + decl ? DECL_BUILT_IN(decl) : false); // Allow the target to set the CC for things like fastcall etc. #ifdef TARGET_ADJUST_LLVM_CC From clattner at apple.com Wed Mar 5 21:52:04 2008 From: clattner at apple.com (Chris Lattner) Date: Wed, 5 Mar 2008 19:52:04 -0800 Subject: [llvm-commits] Fwd: Patch for review: Speeding up ScheduleDAG computations In-Reply-To: <200803051811.29524.dag@cray.com> References: <2DFEE2ED-2D57-4310-8F6C-1B08F18D4363@apple.com> <200803051811.29524.dag@cray.com> Message-ID: <0E45612C-5CFA-4DE0-A685-09D648FBF204@apple.com> On Mar 5, 2008, at 4:11 PM, David Greene wrote: > On Tuesday 04 March 2008 11:30, Evan Cheng wrote: > >>> I'd like to understand better why Evan and Chris are some much >>> against >>> std::set? From some mails I got the impression that std::set >>> implementation is very inefficient on Darwin or PowerPC? Is it >>> correct? Or do you dislike that fact that std::set uses dynamic >>> memory >>> allocation extensively? >> >> Right, it's very malloc intensive. That's the main issue. > > So why not define an allocator for it? See the previous response. -Chris From scottm at aero.org Wed Mar 5 22:02:54 2008 From: scottm at aero.org (Scott Michel) Date: Thu, 06 Mar 2008 04:02:54 -0000 Subject: [llvm-commits] [llvm] r47985 - in /llvm/trunk: lib/Target/CellSPU/SPUISelLowering.cpp test/CodeGen/CellSPU/immed64.ll Message-ID: <200803060402.m2642snO004605@zion.cs.uiuc.edu> Author: pingbak Date: Wed Mar 5 22:02:54 2008 New Revision: 47985 URL: http://llvm.org/viewvc/llvm-project?rev=47985&view=rev Log: Refine Cell's i64 constant generation code to cover more constants where the upper and lower 32-bits are the same (in addition to 0 and -1 previously.) Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp llvm/trunk/test/CodeGen/CellSPU/immed64.ll Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=47985&r1=47984&r2=47985&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Wed Mar 5 22:02:54 2008 @@ -1354,6 +1354,14 @@ MVT::ValueType ValueType) { if (ConstantSDNode *CN = getVecImm(N)) { uint64_t Value = CN->getValue(); + if (ValueType == MVT::i64) { + uint64_t UValue = CN->getValue(); + uint32_t upper = uint32_t(UValue >> 32); + uint32_t lower = uint32_t(UValue); + if (upper != lower) + return SDOperand(); + Value = Value >> 32; + } if (Value <= 0x3ffff) return DAG.getConstant(Value, ValueType); } @@ -1368,6 +1376,14 @@ MVT::ValueType ValueType) { if (ConstantSDNode *CN = getVecImm(N)) { int64_t Value = CN->getSignExtended(); + if (ValueType == MVT::i64) { + uint64_t UValue = CN->getValue(); + uint32_t upper = uint32_t(UValue >> 32); + uint32_t lower = uint32_t(UValue); + if (upper != lower) + return SDOperand(); + Value = Value >> 32; + } if (Value >= -(1 << 15) && Value <= ((1 << 15) - 1)) { return DAG.getConstant(Value, ValueType); } @@ -1383,6 +1399,14 @@ MVT::ValueType ValueType) { if (ConstantSDNode *CN = getVecImm(N)) { int64_t Value = CN->getSignExtended(); + if (ValueType == MVT::i64) { + uint64_t UValue = CN->getValue(); + uint32_t upper = uint32_t(UValue >> 32); + uint32_t lower = uint32_t(UValue); + if (upper != lower) + return SDOperand(); + Value = Value >> 32; + } if (isS10Constant(Value)) return DAG.getConstant(Value, ValueType); } @@ -1626,13 +1650,10 @@ uint32_t upper = uint32_t(val >> 32); uint32_t lower = uint32_t(val); - if (val == 0) { - SDOperand Zero = DAG.getTargetConstant(0, MVT::i64); - return DAG.getNode(ISD::BUILD_VECTOR, VT, Zero, Zero); - } else if (val == 0xffffffffffffffffULL) { - // For -1, this and has a chance of matching immAllOnesV. - SDOperand NegOne = DAG.getTargetConstant(-1, MVT::i64); - return DAG.getNode(ISD::BUILD_VECTOR, VT, NegOne, NegOne); + if (upper == lower) { + // Magic constant that can be matched by IL, ILA, et. al. + SDOperand Val = DAG.getTargetConstant(val, MVT::i64); + return DAG.getNode(ISD::BUILD_VECTOR, VT, Val, Val); } else { SDOperand LO32; SDOperand HI32; Modified: llvm/trunk/test/CodeGen/CellSPU/immed64.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/immed64.ll?rev=47985&r1=47984&r2=47985&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/CellSPU/immed64.ll (original) +++ llvm/trunk/test/CodeGen/CellSPU/immed64.ll Wed Mar 5 22:02:54 2008 @@ -1,6 +1,6 @@ ; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s ; RUN: grep lqa %t1.s | count 13 -; RUN: grep il %t1.s | count 21 +; RUN: grep il %t1.s | count 22 ; RUN: grep shufb %t1.s | count 13 ; RUN: grep 65520 %t1.s | count 1 ; RUN: grep 43981 %t1.s | count 1 @@ -57,6 +57,10 @@ ret i64 -1 ;; IL } +define i64 @i64_const_10() { + ret i64 281470681808895 ;; IL 65535 +} + ; 0x4005bf0a8b145769 -> ; (ILHU 0x4005 [16389]/IOHL 0xbf0a [48906]) ; (ILHU 0x8b14 [35604]/IOHL 0x5769 [22377]) From nicholas at mxc.ca Thu Mar 6 00:48:30 2008 From: nicholas at mxc.ca (Nick Lewycky) Date: Thu, 06 Mar 2008 06:48:30 -0000 Subject: [llvm-commits] [llvm] r47987 - in /llvm/trunk: lib/Transforms/Scalar/InstructionCombining.cpp test/Transforms/InstCombine/rem.ll Message-ID: <200803060648.m266mUMB009110@zion.cs.uiuc.edu> Author: nicholas Date: Thu Mar 6 00:48:30 2008 New Revision: 47987 URL: http://llvm.org/viewvc/llvm-project?rev=47987&view=rev Log: Don't try to simplify urem and srem using arithmetic rules that don't work under modulo (overflow). Fixes PR1933. Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp llvm/trunk/test/Transforms/InstCombine/rem.ll Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp?rev=47987&r1=47986&r2=47987&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Thu Mar 6 00:48:30 2008 @@ -834,6 +834,49 @@ return; } break; + case Instruction::SRem: + if (ConstantInt *Rem = dyn_cast