From sabre at nondot.org Mon Mar 17 00:41:48 2008 From: sabre at nondot.org (Chris Lattner) Date: Mon, 17 Mar 2008 05:41:48 -0000 Subject: [llvm-commits] [llvm] r48443 - in /llvm/trunk/lib/Target/Sparc: Makefile Sparc.td SparcCallingConv.td SparcISelLowering.cpp Message-ID: <200803170541.m2H5fmc2007408@zion.cs.uiuc.edu> Author: lattner Date: Mon Mar 17 00:41:48 2008 New Revision: 48443 URL: http://llvm.org/viewvc/llvm-project?rev=48443&view=rev Log: Start moving sparc to use SparcCallingConv.td, switching over return lowering first. This fixes a bug where the top and bottom of i64 values were returned in the wrong registers before. Added: llvm/trunk/lib/Target/Sparc/SparcCallingConv.td Modified: llvm/trunk/lib/Target/Sparc/Makefile llvm/trunk/lib/Target/Sparc/Sparc.td llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Modified: llvm/trunk/lib/Target/Sparc/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/Makefile?rev=48443&r1=48442&r2=48443&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/Makefile (original) +++ llvm/trunk/lib/Target/Sparc/Makefile Mon Mar 17 00:41:48 2008 @@ -14,7 +14,7 @@ BUILT_SOURCES = SparcGenRegisterInfo.h.inc SparcGenRegisterNames.inc \ SparcGenRegisterInfo.inc SparcGenInstrNames.inc \ SparcGenInstrInfo.inc SparcGenAsmWriter.inc \ - SparcGenDAGISel.inc SparcGenSubtarget.inc + SparcGenDAGISel.inc SparcGenSubtarget.inc SparcGenCallingConv.inc include $(LEVEL)/Makefile.common Modified: llvm/trunk/lib/Target/Sparc/Sparc.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/Sparc.td?rev=48443&r1=48442&r2=48443&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/Sparc.td (original) +++ llvm/trunk/lib/Target/Sparc/Sparc.td Mon Mar 17 00:41:48 2008 @@ -31,15 +31,11 @@ "Enable UltraSPARC Visual Instruction Set extensions">; //===----------------------------------------------------------------------===// -// Register File Description +// Register File, Calling Conv, Instruction Descriptions //===----------------------------------------------------------------------===// include "SparcRegisterInfo.td" - -//===----------------------------------------------------------------------===// -// Instruction Descriptions -//===----------------------------------------------------------------------===// - +include "SparcCallingConv.td" include "SparcInstrInfo.td" def SparcInstrInfo : InstrInfo { Added: llvm/trunk/lib/Target/Sparc/SparcCallingConv.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcCallingConv.td?rev=48443&view=auto ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcCallingConv.td (added) +++ llvm/trunk/lib/Target/Sparc/SparcCallingConv.td Mon Mar 17 00:41:48 2008 @@ -0,0 +1,23 @@ +//===- SparcCallingConv.td - Calling Conventions Sparc -----*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This describes the calling conventions for the Sparc architectures. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Return Value Calling Conventions +//===----------------------------------------------------------------------===// + +// Sparc 32-bit C return-value convention. +def RetCC_Sparc32 : CallingConv<[ + CCIfType<[i32], CCAssignToReg<[I0, I1]>>, + CCIfType<[f32], CCAssignToReg<[F0]>>, + CCIfType<[f64], CCAssignToReg<[D0]>> +]>; Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp?rev=48443&r1=48442&r2=48443&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Mon Mar 17 00:41:48 2008 @@ -14,8 +14,8 @@ #include "SparcISelLowering.h" #include "SparcTargetMachine.h" -#include "llvm/DerivedTypes.h" #include "llvm/Function.h" +#include "llvm/CodeGen/CallingConvLower.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" @@ -23,228 +23,52 @@ #include "llvm/CodeGen/SelectionDAG.h" using namespace llvm; + //===----------------------------------------------------------------------===// -// TargetLowering Implementation +// Calling Convention Implementation //===----------------------------------------------------------------------===// -/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC -/// condition. -static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) { - switch (CC) { - default: assert(0 && "Unknown integer condition code!"); - case ISD::SETEQ: return SPCC::ICC_E; - case ISD::SETNE: return SPCC::ICC_NE; - case ISD::SETLT: return SPCC::ICC_L; - case ISD::SETGT: return SPCC::ICC_G; - case ISD::SETLE: return SPCC::ICC_LE; - case ISD::SETGE: return SPCC::ICC_GE; - case ISD::SETULT: return SPCC::ICC_CS; - case ISD::SETULE: return SPCC::ICC_LEU; - case ISD::SETUGT: return SPCC::ICC_GU; - case ISD::SETUGE: return SPCC::ICC_CC; - } -} +#include "SparcGenCallingConv.inc" -/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC -/// FCC condition. -static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) { - switch (CC) { - default: assert(0 && "Unknown fp condition code!"); - case ISD::SETEQ: - case ISD::SETOEQ: return SPCC::FCC_E; - case ISD::SETNE: - case ISD::SETUNE: return SPCC::FCC_NE; - case ISD::SETLT: - case ISD::SETOLT: return SPCC::FCC_L; - case ISD::SETGT: - case ISD::SETOGT: return SPCC::FCC_G; - case ISD::SETLE: - case ISD::SETOLE: return SPCC::FCC_LE; - case ISD::SETGE: - case ISD::SETOGE: return SPCC::FCC_GE; - case ISD::SETULT: return SPCC::FCC_UL; - case ISD::SETULE: return SPCC::FCC_ULE; - case ISD::SETUGT: return SPCC::FCC_UG; - case ISD::SETUGE: return SPCC::FCC_UGE; - case ISD::SETUO: return SPCC::FCC_U; - case ISD::SETO: return SPCC::FCC_O; - case ISD::SETONE: return SPCC::FCC_LG; - case ISD::SETUEQ: return SPCC::FCC_UE; +static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) { + // CCValAssign - represent the assignment of the return value to locations. + SmallVector RVLocs; + unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); + bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); + + // CCState - Info about the registers and stack slot. + CCState CCInfo(CC, isVarArg, DAG.getTarget(), RVLocs); + + // Analize return values of ISD::RET + CCInfo.AnalyzeReturn(Op.Val, RetCC_Sparc32); + + // If this is the first return lowered for this function, add the regs to the + // liveout set for the function. + if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { + for (unsigned i = 0; i != RVLocs.size(); ++i) + if (RVLocs[i].isRegLoc()) + DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); } -} - - -SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) - : TargetLowering(TM) { - // Set up the register classes. - addRegisterClass(MVT::i32, SP::IntRegsRegisterClass); - addRegisterClass(MVT::f32, SP::FPRegsRegisterClass); - addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass); - - // Turn FP extload into load/fextend - setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand); - // Sparc doesn't have i1 sign extending load - setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote); - // Turn FP truncstore into trunc + store. - setTruncStoreAction(MVT::f64, MVT::f32, Expand); - - // Custom legalize GlobalAddress nodes into LO/HI parts. - setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); - setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); - setOperationAction(ISD::ConstantPool , MVT::i32, Custom); - - // Sparc doesn't have sext_inreg, replace them with shl/sra - setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); - setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); - setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); - - // Sparc has no REM or DIVREM operations. - setOperationAction(ISD::UREM, MVT::i32, Expand); - setOperationAction(ISD::SREM, MVT::i32, Expand); - setOperationAction(ISD::SDIVREM, MVT::i32, Expand); - setOperationAction(ISD::UDIVREM, MVT::i32, Expand); - - // Custom expand fp<->sint - setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); - setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); - - // Expand fp<->uint - setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); - setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); - - setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); - setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); - - // Sparc has no select or setcc: expand to SELECT_CC. - setOperationAction(ISD::SELECT, MVT::i32, Expand); - setOperationAction(ISD::SELECT, MVT::f32, Expand); - setOperationAction(ISD::SELECT, MVT::f64, Expand); - setOperationAction(ISD::SETCC, MVT::i32, Expand); - setOperationAction(ISD::SETCC, MVT::f32, Expand); - setOperationAction(ISD::SETCC, MVT::f64, Expand); - - // Sparc doesn't have BRCOND either, it has BR_CC. - setOperationAction(ISD::BRCOND, MVT::Other, Expand); - setOperationAction(ISD::BRIND, MVT::Other, Expand); - setOperationAction(ISD::BR_JT, MVT::Other, Expand); - setOperationAction(ISD::BR_CC, MVT::i32, Custom); - setOperationAction(ISD::BR_CC, MVT::f32, Custom); - setOperationAction(ISD::BR_CC, MVT::f64, Custom); - - setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); - setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); - setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); - - // SPARC has no intrinsics for these particular operations. - setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); - setOperationAction(ISD::MEMSET, MVT::Other, Expand); - setOperationAction(ISD::MEMCPY, MVT::Other, Expand); - setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); - - setOperationAction(ISD::FSIN , MVT::f64, Expand); - setOperationAction(ISD::FCOS , MVT::f64, Expand); - setOperationAction(ISD::FREM , MVT::f64, Expand); - setOperationAction(ISD::FSIN , MVT::f32, Expand); - setOperationAction(ISD::FCOS , MVT::f32, Expand); - setOperationAction(ISD::FREM , MVT::f32, Expand); - setOperationAction(ISD::CTPOP, MVT::i32, Expand); - setOperationAction(ISD::CTTZ , MVT::i32, Expand); - setOperationAction(ISD::CTLZ , MVT::i32, Expand); - setOperationAction(ISD::ROTL , MVT::i32, Expand); - setOperationAction(ISD::ROTR , MVT::i32, Expand); - setOperationAction(ISD::BSWAP, MVT::i32, Expand); - setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); - setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); - setOperationAction(ISD::FPOW , MVT::f64, Expand); - setOperationAction(ISD::FPOW , MVT::f32, Expand); - - setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); - setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); - setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); + SDOperand Chain = Op.getOperand(0); + SDOperand Flag; - // FIXME: Sparc provides these multiplies, but we don't have them yet. - setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); + // Copy the result values into the output registers. + for (unsigned i = 0; i != RVLocs.size(); ++i) { + CCValAssign &VA = RVLocs[i]; + assert(VA.isRegLoc() && "Can only return in registers!"); - // We don't have line number support yet. - setOperationAction(ISD::LOCATION, MVT::Other, Expand); - setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); - setOperationAction(ISD::LABEL, MVT::Other, Expand); - - // RET must be custom lowered, to meet ABI requirements - setOperationAction(ISD::RET , MVT::Other, Custom); - - // VASTART needs to be custom lowered to use the VarArgsFrameIndex. - setOperationAction(ISD::VASTART , MVT::Other, Custom); - // VAARG needs to be lowered to not do unaligned accesses for doubles. - setOperationAction(ISD::VAARG , MVT::Other, Custom); - - // Use the default implementation. - setOperationAction(ISD::VACOPY , MVT::Other, Expand); - setOperationAction(ISD::VAEND , MVT::Other, Expand); - setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); - setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); - setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); - - // No debug info support yet. - setOperationAction(ISD::LOCATION, MVT::Other, Expand); - setOperationAction(ISD::LABEL, MVT::Other, Expand); - setOperationAction(ISD::DECLARE, MVT::Other, Expand); + // ISD::RET => ret chain, (regnum1,val1), ... + // So i*2+1 index only the regnums. + Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag); - setStackPointerRegisterToSaveRestore(SP::O6); - - if (TM.getSubtarget().isV9()) - setOperationAction(ISD::CTPOP, MVT::i32, Legal); - - computeRegisterProperties(); -} - -const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const { - switch (Opcode) { - default: return 0; - case SPISD::CMPICC: return "SPISD::CMPICC"; - case SPISD::CMPFCC: return "SPISD::CMPFCC"; - case SPISD::BRICC: return "SPISD::BRICC"; - case SPISD::BRFCC: return "SPISD::BRFCC"; - case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC"; - case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC"; - case SPISD::Hi: return "SPISD::Hi"; - case SPISD::Lo: return "SPISD::Lo"; - case SPISD::FTOI: return "SPISD::FTOI"; - case SPISD::ITOF: return "SPISD::ITOF"; - case SPISD::CALL: return "SPISD::CALL"; - case SPISD::RET_FLAG: return "SPISD::RET_FLAG"; + // Guarantee that all emitted copies are stuck together with flags. + Flag = Chain.getValue(1); } -} - -/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to -/// be zero. Op is expected to be a target specific node. Used by DAG -/// combiner. -void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, - const APInt &Mask, - APInt &KnownZero, - APInt &KnownOne, - const SelectionDAG &DAG, - unsigned Depth) const { - APInt KnownZero2, KnownOne2; - KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything. - switch (Op.getOpcode()) { - default: break; - case SPISD::SELECT_ICC: - case SPISD::SELECT_FCC: - DAG.ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, - Depth+1); - DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, - Depth+1); - assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); - assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); - - // Only known if known in both the LHS and RHS. - KnownOne &= KnownOne2; - KnownZero &= KnownZero2; - break; - } + if (Flag.Val) + return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Chain, Flag); + return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Chain); } /// LowerArguments - V8 uses a very simple ABI, where all values are passed in @@ -387,7 +211,7 @@ } // Store remaining ArgRegs to the stack if this is a varargs function. - if (F.getFunctionType()->isVarArg()) { + if (F.isVarArg()) { // Remember the vararg offset for the va_start implementation. VarArgsFrameOffset = ArgOffset; @@ -408,28 +232,6 @@ DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, &OutChains[0], OutChains.size())); - // Finally, inform the code generator which regs we return values in. - switch (getValueType(F.getReturnType())) { - default: assert(0 && "Unknown type!"); - case MVT::isVoid: break; - case MVT::i1: - case MVT::i8: - case MVT::i16: - case MVT::i32: - MF.getRegInfo().addLiveOut(SP::I0); - break; - case MVT::i64: - MF.getRegInfo().addLiveOut(SP::I0); - MF.getRegInfo().addLiveOut(SP::I1); - break; - case MVT::f32: - MF.getRegInfo().addLiveOut(SP::F0); - break; - case MVT::f64: - MF.getRegInfo().addLiveOut(SP::D0); - break; - } - return ArgValues; } @@ -589,6 +391,7 @@ InFlag = Chain.getValue(1); MVT::ValueType RetTyVT = getValueType(RetTy); + SDOperand RetVal; if (RetTyVT != MVT::isVoid) { switch (RetTyVT) { @@ -642,6 +445,232 @@ return std::make_pair(RetVal, Chain); } + + +//===----------------------------------------------------------------------===// +// TargetLowering Implementation +//===----------------------------------------------------------------------===// + +/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC +/// condition. +static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) { + switch (CC) { + default: assert(0 && "Unknown integer condition code!"); + case ISD::SETEQ: return SPCC::ICC_E; + case ISD::SETNE: return SPCC::ICC_NE; + case ISD::SETLT: return SPCC::ICC_L; + case ISD::SETGT: return SPCC::ICC_G; + case ISD::SETLE: return SPCC::ICC_LE; + case ISD::SETGE: return SPCC::ICC_GE; + case ISD::SETULT: return SPCC::ICC_CS; + case ISD::SETULE: return SPCC::ICC_LEU; + case ISD::SETUGT: return SPCC::ICC_GU; + case ISD::SETUGE: return SPCC::ICC_CC; + } +} + +/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC +/// FCC condition. +static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) { + switch (CC) { + default: assert(0 && "Unknown fp condition code!"); + case ISD::SETEQ: + case ISD::SETOEQ: return SPCC::FCC_E; + case ISD::SETNE: + case ISD::SETUNE: return SPCC::FCC_NE; + case ISD::SETLT: + case ISD::SETOLT: return SPCC::FCC_L; + case ISD::SETGT: + case ISD::SETOGT: return SPCC::FCC_G; + case ISD::SETLE: + case ISD::SETOLE: return SPCC::FCC_LE; + case ISD::SETGE: + case ISD::SETOGE: return SPCC::FCC_GE; + case ISD::SETULT: return SPCC::FCC_UL; + case ISD::SETULE: return SPCC::FCC_ULE; + case ISD::SETUGT: return SPCC::FCC_UG; + case ISD::SETUGE: return SPCC::FCC_UGE; + case ISD::SETUO: return SPCC::FCC_U; + case ISD::SETO: return SPCC::FCC_O; + case ISD::SETONE: return SPCC::FCC_LG; + case ISD::SETUEQ: return SPCC::FCC_UE; + } +} + + +SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) + : TargetLowering(TM) { + + // Set up the register classes. + addRegisterClass(MVT::i32, SP::IntRegsRegisterClass); + addRegisterClass(MVT::f32, SP::FPRegsRegisterClass); + addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass); + + // Turn FP extload into load/fextend + setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand); + // Sparc doesn't have i1 sign extending load + setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote); + // Turn FP truncstore into trunc + store. + setTruncStoreAction(MVT::f64, MVT::f32, Expand); + + // Custom legalize GlobalAddress nodes into LO/HI parts. + setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); + setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); + setOperationAction(ISD::ConstantPool , MVT::i32, Custom); + + // Sparc doesn't have sext_inreg, replace them with shl/sra + setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); + setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); + setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); + + // Sparc has no REM or DIVREM operations. + setOperationAction(ISD::UREM, MVT::i32, Expand); + setOperationAction(ISD::SREM, MVT::i32, Expand); + setOperationAction(ISD::SDIVREM, MVT::i32, Expand); + setOperationAction(ISD::UDIVREM, MVT::i32, Expand); + + // Custom expand fp<->sint + setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); + setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); + + // Expand fp<->uint + setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); + setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); + + setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); + setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); + + // Sparc has no select or setcc: expand to SELECT_CC. + setOperationAction(ISD::SELECT, MVT::i32, Expand); + setOperationAction(ISD::SELECT, MVT::f32, Expand); + setOperationAction(ISD::SELECT, MVT::f64, Expand); + setOperationAction(ISD::SETCC, MVT::i32, Expand); + setOperationAction(ISD::SETCC, MVT::f32, Expand); + setOperationAction(ISD::SETCC, MVT::f64, Expand); + + // Sparc doesn't have BRCOND either, it has BR_CC. + setOperationAction(ISD::BRCOND, MVT::Other, Expand); + setOperationAction(ISD::BRIND, MVT::Other, Expand); + setOperationAction(ISD::BR_JT, MVT::Other, Expand); + setOperationAction(ISD::BR_CC, MVT::i32, Custom); + setOperationAction(ISD::BR_CC, MVT::f32, Custom); + setOperationAction(ISD::BR_CC, MVT::f64, Custom); + + setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); + setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); + setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); + + // SPARC has no intrinsics for these particular operations. + setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); + setOperationAction(ISD::MEMSET, MVT::Other, Expand); + setOperationAction(ISD::MEMCPY, MVT::Other, Expand); + setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); + + setOperationAction(ISD::FSIN , MVT::f64, Expand); + setOperationAction(ISD::FCOS , MVT::f64, Expand); + setOperationAction(ISD::FREM , MVT::f64, Expand); + setOperationAction(ISD::FSIN , MVT::f32, Expand); + setOperationAction(ISD::FCOS , MVT::f32, Expand); + setOperationAction(ISD::FREM , MVT::f32, Expand); + setOperationAction(ISD::CTPOP, MVT::i32, Expand); + setOperationAction(ISD::CTTZ , MVT::i32, Expand); + setOperationAction(ISD::CTLZ , MVT::i32, Expand); + setOperationAction(ISD::ROTL , MVT::i32, Expand); + setOperationAction(ISD::ROTR , MVT::i32, Expand); + setOperationAction(ISD::BSWAP, MVT::i32, Expand); + setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); + setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); + setOperationAction(ISD::FPOW , MVT::f64, Expand); + setOperationAction(ISD::FPOW , MVT::f32, Expand); + + setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); + setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); + setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); + + // FIXME: Sparc provides these multiplies, but we don't have them yet. + setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); + + // We don't have line number support yet. + setOperationAction(ISD::LOCATION, MVT::Other, Expand); + setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); + setOperationAction(ISD::LABEL, MVT::Other, Expand); + + // RET must be custom lowered, to meet ABI requirements + setOperationAction(ISD::RET , MVT::Other, Custom); + + // VASTART needs to be custom lowered to use the VarArgsFrameIndex. + setOperationAction(ISD::VASTART , MVT::Other, Custom); + // VAARG needs to be lowered to not do unaligned accesses for doubles. + setOperationAction(ISD::VAARG , MVT::Other, Custom); + + // Use the default implementation. + setOperationAction(ISD::VACOPY , MVT::Other, Expand); + setOperationAction(ISD::VAEND , MVT::Other, Expand); + setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); + setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); + setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); + + // No debug info support yet. + setOperationAction(ISD::LOCATION, MVT::Other, Expand); + setOperationAction(ISD::LABEL, MVT::Other, Expand); + setOperationAction(ISD::DECLARE, MVT::Other, Expand); + + setStackPointerRegisterToSaveRestore(SP::O6); + + if (TM.getSubtarget().isV9()) + setOperationAction(ISD::CTPOP, MVT::i32, Legal); + + computeRegisterProperties(); +} + +const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const { + switch (Opcode) { + default: return 0; + case SPISD::CMPICC: return "SPISD::CMPICC"; + case SPISD::CMPFCC: return "SPISD::CMPFCC"; + case SPISD::BRICC: return "SPISD::BRICC"; + case SPISD::BRFCC: return "SPISD::BRFCC"; + case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC"; + case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC"; + case SPISD::Hi: return "SPISD::Hi"; + case SPISD::Lo: return "SPISD::Lo"; + case SPISD::FTOI: return "SPISD::FTOI"; + case SPISD::ITOF: return "SPISD::ITOF"; + case SPISD::CALL: return "SPISD::CALL"; + case SPISD::RET_FLAG: return "SPISD::RET_FLAG"; + } +} + +/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to +/// be zero. Op is expected to be a target specific node. Used by DAG +/// combiner. +void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, + const APInt &Mask, + APInt &KnownZero, + APInt &KnownOne, + const SelectionDAG &DAG, + unsigned Depth) const { + APInt KnownZero2, KnownOne2; + KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything. + + switch (Op.getOpcode()) { + default: break; + case SPISD::SELECT_ICC: + case SPISD::SELECT_FCC: + DAG.ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, + Depth+1); + DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, + Depth+1); + assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); + assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); + + // Only known if known in both the LHS and RHS. + KnownOne &= KnownOne2; + KnownZero &= KnownZero2; + break; + } +} + // Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so // set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition. static void LookThroughSetCC(SDOperand &LHS, SDOperand &RHS, @@ -818,36 +847,6 @@ return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2); } -static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) { - SDOperand Copy; - - switch(Op.getNumOperands()) { - default: - assert(0 && "Do not know how to return this many arguments!"); - abort(); - case 1: - return SDOperand(); // ret void is legal - case 3: { - unsigned ArgReg; - switch(Op.getOperand(1).getValueType()) { - default: assert(0 && "Unknown type to return!"); - case MVT::i32: ArgReg = SP::I0; break; - case MVT::f32: ArgReg = SP::F0; break; - case MVT::f64: ArgReg = SP::D0; break; - } - Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1), - SDOperand()); - break; - } - case 5: - Copy = DAG.getCopyToReg(Op.getOperand(0), SP::I0, Op.getOperand(3), - SDOperand()); - Copy = DAG.getCopyToReg(Copy, SP::I1, Op.getOperand(1), Copy.getValue(1)); - break; - } - return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); -} - SDOperand SparcTargetLowering:: LowerOperation(SDOperand Op, SelectionDAG &DAG) { @@ -945,4 +944,4 @@ delete MI; // The pseudo instruction is gone now. return BB; } - + From sabre at nondot.org Mon Mar 17 01:01:07 2008 From: sabre at nondot.org (Chris Lattner) Date: Mon, 17 Mar 2008 06:01:07 -0000 Subject: [llvm-commits] [llvm] r48444 - in /llvm/trunk/lib/Target/Sparc: SparcISelLowering.cpp SparcISelLowering.h Message-ID: <200803170601.m2H617EG007863@zion.cs.uiuc.edu> Author: lattner Date: Mon Mar 17 01:01:07 2008 New Revision: 48444 URL: http://llvm.org/viewvc/llvm-project?rev=48444&view=rev Log: Switch sparc from using LowerCallTo to using LowerOperation(CALL) like other targets. Use autogenerated calling conv to lower result of calls. Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp llvm/trunk/lib/Target/Sparc/SparcISelLowering.h Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp?rev=48444&r1=48443&r2=48444&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Mon Mar 17 01:01:07 2008 @@ -33,7 +33,7 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) { // CCValAssign - represent the assignment of the return value to locations. SmallVector RVLocs; - unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); + unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); // CCState - Info about the registers and stack slot. @@ -235,15 +235,16 @@ return ArgValues; } -std::pair -SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, - bool RetSExt, bool RetZExt, bool isVarArg, - unsigned CC, bool isTailCall, SDOperand Callee, - ArgListTy &Args, SelectionDAG &DAG) { +static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) { + unsigned CallingConv = cast(Op.getOperand(1))->getValue(); + SDOperand Chain = Op.getOperand(0); + SDOperand Callee = Op.getOperand(4); + bool isVarArg = cast(Op.getOperand(2))->getValue() != 0; + // Count the size of the outgoing arguments. unsigned ArgsSize = 0; - for (unsigned i = 0, e = Args.size(); i != e; ++i) { - switch (getValueType(Args[i].Ty)) { + for (unsigned i = 5, e = Op.getNumOperands(); i != e; i += 2) { + switch (Op.getOperand(i).getValueType()) { default: assert(0 && "Unknown value type!"); case MVT::i1: case MVT::i8: @@ -266,14 +267,14 @@ // Keep stack frames 8-byte aligned. ArgsSize = (ArgsSize+7) & ~7; - Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(ArgsSize, getPointerTy())); + Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(ArgsSize, MVT::i32)); SDOperand StackPtr; std::vector Stores; std::vector RegValuesToPass; unsigned ArgOffset = 68; - for (unsigned i = 0, e = Args.size(); i != e; ++i) { - SDOperand Val = Args[i].Node; + for (unsigned i = 5, e = Op.getNumOperands(); i != e; i += 2) { + SDOperand Val = Op.getOperand(i); MVT::ValueType ObjectVT = Val.getValueType(); SDOperand ValToStore(0, 0); unsigned ObjSize; @@ -282,12 +283,13 @@ case MVT::i1: case MVT::i8: case MVT::i16: { + assert(0 && "unreach"); // Promote the integer to 32-bits. If the input type is signed, use a // sign extend, otherwise use a zero extend. ISD::NodeType ExtendKind = ISD::ANY_EXTEND; - if (Args[i].isSExt) + if (Op.getConstantOperandVal(i+1) & 1) ExtendKind = ISD::SIGN_EXTEND; - else if (Args[i].isZExt) + else ExtendKind = ISD::ZERO_EXTEND; Val = DAG.getNode(ExtendKind, MVT::i32, Val); // FALL THROUGH @@ -332,9 +334,9 @@ } // Split the value into top and bottom part. Top part goes in a reg. - SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val, + SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val, DAG.getConstant(1, MVT::i32)); - SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val, + SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val, DAG.getConstant(0, MVT::i32)); RegValuesToPass.push_back(Hi); @@ -352,7 +354,7 @@ if (!StackPtr.Val) { StackPtr = DAG.getRegister(SP::O6, MVT::i32); } - SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); + SDOperand PtrOff = DAG.getConstant(ArgOffset, MVT::i32); PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); Stores.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0)); } @@ -390,59 +392,37 @@ Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops, InFlag.Val ? 3 : 2); InFlag = Chain.getValue(1); - MVT::ValueType RetTyVT = getValueType(RetTy); + Chain = DAG.getCALLSEQ_END(Chain, + DAG.getConstant(ArgsSize, MVT::i32), + DAG.getConstant(0, MVT::i32), InFlag); + InFlag = Chain.getValue(1); - SDOperand RetVal; - if (RetTyVT != MVT::isVoid) { - switch (RetTyVT) { - default: assert(0 && "Unknown value type to return!"); - case MVT::i1: - case MVT::i8: - case MVT::i16: { - RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag); - Chain = RetVal.getValue(1); - - // Add a note to keep track of whether it is sign or zero extended. - ISD::NodeType AssertKind = ISD::DELETED_NODE; - if (RetSExt) - AssertKind = ISD::AssertSext; - else if (RetZExt) - AssertKind = ISD::AssertZext; - - if (AssertKind != ISD::DELETED_NODE) - RetVal = DAG.getNode(AssertKind, MVT::i32, RetVal, - DAG.getValueType(RetTyVT)); - - RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal); - break; - } - case MVT::i32: - RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag); - Chain = RetVal.getValue(1); - break; - case MVT::f32: - RetVal = DAG.getCopyFromReg(Chain, SP::F0, MVT::f32, InFlag); - Chain = RetVal.getValue(1); - break; - case MVT::f64: - RetVal = DAG.getCopyFromReg(Chain, SP::D0, MVT::f64, InFlag); - Chain = RetVal.getValue(1); - break; - case MVT::i64: - SDOperand Lo = DAG.getCopyFromReg(Chain, SP::O1, MVT::i32, InFlag); - SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), SP::O0, MVT::i32, - Lo.getValue(2)); - RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi); - Chain = Hi.getValue(1); - break; - } + // Assign locations to each value returned by this call. + SmallVector RVLocs; + CCState CCInfo(CallingConv, isVarArg, DAG.getTarget(), RVLocs); + + CCInfo.AnalyzeCallResult(Op.Val, RetCC_Sparc32); + SmallVector ResultVals; + + // Copy all of the result registers out of their specified physreg. + for (unsigned i = 0; i != RVLocs.size(); ++i) { + unsigned Reg = RVLocs[i].getLocReg(); + + // Remap I0->I7 -> O0->O7. + if (Reg >= SP::I0 && Reg <= SP::I7) + Reg = Reg-SP::I0+SP::O0; + + Chain = DAG.getCopyFromReg(Chain, Reg, + RVLocs[i].getValVT(), InFlag).getValue(1); + InFlag = Chain.getValue(2); + ResultVals.push_back(Chain.getValue(0)); } - Chain = DAG.getCALLSEQ_END(Chain, - DAG.getConstant(ArgsSize, getPointerTy()), - DAG.getConstant(0, getPointerTy()), - SDOperand()); - return std::make_pair(RetVal, Chain); + ResultVals.push_back(Chain); + + // Merge everything together with a MERGE_VALUES node. + return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(), + &ResultVals[0], ResultVals.size()); } @@ -866,6 +846,7 @@ case ISD::VASTART: return LowerVASTART(Op, DAG, *this); case ISD::VAARG: return LowerVAARG(Op, DAG); case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); + case ISD::CALL: return LowerCALL(Op, DAG); case ISD::RET: return LowerRET(Op, DAG); } } Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.h?rev=48444&r1=48443&r2=48444&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcISelLowering.h (original) +++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.h Mon Mar 17 01:01:07 2008 @@ -59,11 +59,6 @@ virtual std::vector LowerArguments(Function &F, SelectionDAG &DAG); - virtual std::pair - LowerCallTo(SDOperand Chain, const Type *RetTy, - bool RetSExt, bool RetZExt, bool isVarArg, - unsigned CC, bool isTailCall, SDOperand Callee, - ArgListTy &Args, SelectionDAG &DAG); virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB); From sabre at nondot.org Mon Mar 17 01:04:10 2008 From: sabre at nondot.org (Chris Lattner) Date: Mon, 17 Mar 2008 06:04:10 -0000 Subject: [llvm-commits] [llvm] r48445 - /llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Message-ID: <200803170604.m2H64AtS007949@zion.cs.uiuc.edu> Author: lattner Date: Mon Mar 17 01:04:10 2008 New Revision: 48445 URL: http://llvm.org/viewvc/llvm-project?rev=48445&view=rev Log: remove dead code Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp?rev=48445&r1=48444&r2=48445&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Mon Mar 17 01:04:10 2008 @@ -162,16 +162,6 @@ if (CurArgReg < ArgRegEnd) ++CurArgReg; if (CurArgReg < ArgRegEnd) ++CurArgReg; ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); - } else if (/* FIXME: Apparently this isn't safe?? */ - 0 && CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 && - ((CurArgReg-ArgRegs) & 1) == 0) { - // If this is a double argument and the whole thing lives on the stack, - // and the argument is aligned, load the double straight from the stack. - // We can't do a load in cases like void foo([6ints], int,double), - // because the double wouldn't be aligned! - int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset); - SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); - ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, NULL, 0)); } else { SDOperand HiVal; if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR @@ -280,20 +270,6 @@ unsigned ObjSize; switch (ObjectVT) { default: assert(0 && "Unhandled argument type!"); - case MVT::i1: - case MVT::i8: - case MVT::i16: { - assert(0 && "unreach"); - // Promote the integer to 32-bits. If the input type is signed, use a - // sign extend, otherwise use a zero extend. - ISD::NodeType ExtendKind = ISD::ANY_EXTEND; - if (Op.getConstantOperandVal(i+1) & 1) - ExtendKind = ISD::SIGN_EXTEND; - else - ExtendKind = ISD::ZERO_EXTEND; - Val = DAG.getNode(ExtendKind, MVT::i32, Val); - // FALL THROUGH - } case MVT::i32: ObjSize = 4; @@ -315,14 +291,6 @@ break; case MVT::f64: ObjSize = 8; - // If we can store this directly into the outgoing slot, do so. We can - // do this when all ArgRegs are used and if the outgoing slot is aligned. - // FIXME: McGill/misr fails with this. - if (0 && RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) { - ValToStore = Val; - break; - } - // Otherwise, convert this to a FP value in int regs. Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val); // FALL THROUGH From resistor at mac.com Mon Mar 17 01:08:26 2008 From: resistor at mac.com (Owen Anderson) Date: Mon, 17 Mar 2008 06:08:26 -0000 Subject: [llvm-commits] [llvm] r48446 - /llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp Message-ID: <200803170608.m2H68QrB008075@zion.cs.uiuc.edu> Author: resistor Date: Mon Mar 17 01:08:26 2008 New Revision: 48446 URL: http://llvm.org/viewvc/llvm-project?rev=48446&view=rev Log: A first attempt at updating live intervals, with code lifted from the coalescer. This doesn't really work, but gets us farther than before. Modified: llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp Modified: llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp?rev=48446&r1=48445&r2=48446&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp (original) +++ llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp Mon Mar 17 01:08:26 2008 @@ -25,6 +25,7 @@ #include "llvm/CodeGen/MachineDominators.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" +#include "llvm/CodeGen/MachineLoopInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" @@ -404,13 +405,16 @@ // before the current one. std::set ProcessedNames; + MachineBasicBlock::iterator FirstNonPHI = MBB->begin(); + while (FirstNonPHI->getOpcode() == TargetInstrInfo::PHI) FirstNonPHI++; + // Iterate over all the PHI nodes in this block MachineBasicBlock::iterator P = MBB->begin(); - while (P != MBB->end() && P->getOpcode() == TargetInstrInfo::PHI) { + while (P != FirstNonPHI && P->getOpcode() == TargetInstrInfo::PHI) { unsigned DestReg = P->getOperand(0).getReg(); LiveInterval& PI = LI.getOrCreateInterval(DestReg); - unsigned pIdx = LI.getInstructionIndex(P); + unsigned pIdx = LI.getInstructionIndex(FirstNonPHI); VNInfo* PVN = PI.getLiveRangeContaining(pIdx)->valno; PhiValueNumber.insert(std::make_pair(DestReg, PVN->id)); @@ -734,9 +738,177 @@ Stacks[*I].pop_back(); } +/// ComputeUltimateVN - Assuming we are going to join two live intervals, +/// compute what the resultant value numbers for each value in the input two +/// ranges will be. This is complicated by copies between the two which can +/// and will commonly cause multiple value numbers to be merged into one. +/// +/// VN is the value number that we're trying to resolve. InstDefiningValue +/// keeps track of the new InstDefiningValue assignment for the result +/// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of +/// whether a value in this or other is a copy from the opposite set. +/// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have +/// already been assigned. +/// +/// ThisFromOther[x] - If x is defined as a copy from the other interval, this +/// contains the value number the copy is from. +/// +static unsigned ComputeUltimateVN(VNInfo *VNI, + SmallVector &NewVNInfo, + DenseMap &ThisFromOther, + DenseMap &OtherFromThis, + SmallVector &ThisValNoAssignments, + SmallVector &OtherValNoAssignments) { + unsigned VN = VNI->id; + + // If the VN has already been computed, just return it. + if (ThisValNoAssignments[VN] >= 0) + return ThisValNoAssignments[VN]; +// assert(ThisValNoAssignments[VN] != -2 && "Cyclic case?"); + + // If this val is not a copy from the other val, then it must be a new value + // number in the destination. + DenseMap::iterator I = ThisFromOther.find(VNI); + if (I == ThisFromOther.end()) { + NewVNInfo.push_back(VNI); + return ThisValNoAssignments[VN] = NewVNInfo.size()-1; + } + VNInfo *OtherValNo = I->second; + + // Otherwise, this *is* a copy from the RHS. If the other side has already + // been computed, return it. + if (OtherValNoAssignments[OtherValNo->id] >= 0) + return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo->id]; + + // Mark this value number as currently being computed, then ask what the + // ultimate value # of the other value is. + ThisValNoAssignments[VN] = -2; + unsigned UltimateVN = + ComputeUltimateVN(OtherValNo, NewVNInfo, OtherFromThis, ThisFromOther, + OtherValNoAssignments, ThisValNoAssignments); + return ThisValNoAssignments[VN] = UltimateVN; +} + void StrongPHIElimination::mergeLiveIntervals(unsigned primary, - unsigned secondary, unsigned VN) { - // FIXME: Update LiveIntervals + unsigned secondary, unsigned secondaryVN) { + unsigned primaryVN = PhiValueNumber[primary]; + + LiveIntervals& LI = getAnalysis(); + LiveInterval& LHS = LI.getOrCreateInterval(primary); + LiveInterval& RHS = LI.getOrCreateInterval(secondary); + + // Compute the final value assignment, assuming that the live ranges can be + // coalesced. + SmallVector LHSValNoAssignments; + SmallVector RHSValNoAssignments; + DenseMap LHSValsDefinedFromRHS; + DenseMap RHSValsDefinedFromLHS; + SmallVector NewVNInfo; + + LHSValNoAssignments.resize(LHS.getNumValNums(), -1); + RHSValNoAssignments.resize(RHS.getNumValNums(), -1); + NewVNInfo.resize(LHS.getNumValNums(), NULL); + + // Loop over the value numbers of the LHS, seeing if any are defined from + // the RHS. + for (LiveInterval::vni_iterator I = LHS.vni_begin(), E = LHS.vni_end(); + I != E; ++E) { + VNInfo *VNI = *I; + if (VNI->def == ~1U || VNI->copy == 0) // Src not defined by a copy? + continue; + + // DstReg is known to be a register in the LHS interval. If the src is + // from the RHS interval, we can use its value #. + if (LI.getVNInfoSourceReg(VNI) != RHS.reg) + continue; + + // Figure out the value # from the RHS. + LHSValsDefinedFromRHS[VNI]=RHS.getLiveRangeContaining(VNI->def-1)->valno; + } + + // Loop over the value numbers of the RHS, seeing if any are defined from + // the LHS. + for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end(); + i != e; ++i) { + VNInfo *VNI = *i; + if (VNI->def == ~1U || VNI->copy == 0) // Src not defined by a copy? + continue; + + // DstReg is known to be a register in the RHS interval. If the src is + // from the LHS interval, we can use its value #. + if (LI.getVNInfoSourceReg(VNI) != LHS.reg) + continue; + + // Figure out the value # from the LHS. + RHSValsDefinedFromLHS[VNI]=LHS.getLiveRangeContaining(VNI->def-1)->valno; + } + + LHSValNoAssignments.resize(LHS.getNumValNums(), -1); + RHSValNoAssignments.resize(RHS.getNumValNums(), -1); + NewVNInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums()); + + for (LiveInterval::vni_iterator I = LHS.vni_begin(), E = LHS.vni_end(); + I != E; ++I) { + VNInfo *VNI = *I; + unsigned VN = VNI->id; + if (LHSValNoAssignments[VN] >= 0 || VNI->def == ~1U) + continue; + ComputeUltimateVN(VNI, NewVNInfo, + LHSValsDefinedFromRHS, RHSValsDefinedFromLHS, + LHSValNoAssignments, RHSValNoAssignments); + } + + for (LiveInterval::vni_iterator I = RHS.vni_begin(), E = RHS.vni_end(); + I != E; ++I) { + VNInfo *VNI = *I; + unsigned VN = VNI->id; + if (RHSValNoAssignments[VN] >= 0 || VNI->def == ~1U) + continue; + // If this value number isn't a copy from the LHS, it's a new number. + if (RHSValsDefinedFromLHS.find(VNI) == RHSValsDefinedFromLHS.end()) { + NewVNInfo.push_back(VNI); + RHSValNoAssignments[VN] = NewVNInfo.size()-1; + continue; + } + + ComputeUltimateVN(VNI, NewVNInfo, + RHSValsDefinedFromLHS, LHSValsDefinedFromRHS, + RHSValNoAssignments, LHSValNoAssignments); + } + + // Update kill info. Some live ranges are extended due to copy coalescing. + for (DenseMap::iterator I = LHSValsDefinedFromRHS.begin(), + E = LHSValsDefinedFromRHS.end(); I != E; ++I) { + VNInfo *VNI = I->first; + unsigned LHSValID = LHSValNoAssignments[VNI->id]; + LiveInterval::removeKill(NewVNInfo[LHSValID], VNI->def); + NewVNInfo[LHSValID]->hasPHIKill |= VNI->hasPHIKill; + RHS.addKills(NewVNInfo[LHSValID], VNI->kills); + } + + // Update kill info. Some live ranges are extended due to copy coalescing. + for (DenseMap::iterator I = RHSValsDefinedFromLHS.begin(), + E = RHSValsDefinedFromLHS.end(); I != E; ++I) { + VNInfo *VNI = I->first; + unsigned RHSValID = RHSValNoAssignments[VNI->id]; + LiveInterval::removeKill(NewVNInfo[RHSValID], VNI->def); + NewVNInfo[RHSValID]->hasPHIKill |= VNI->hasPHIKill; + LHS.addKills(NewVNInfo[RHSValID], VNI->kills); + } + + // Use the VNInfo we collected earlier to ensure that the phi copy is + // merged correctly. + RHSValNoAssignments[secondaryVN] = primaryVN; + + // If we get here, we know that we can coalesce the live ranges. Ask the + // intervals to coalesce themselves now. + if ((RHS.ranges.size() > LHS.ranges.size() && + TargetRegisterInfo::isVirtualRegister(LHS.reg)) || + TargetRegisterInfo::isPhysicalRegister(RHS.reg)) { + RHS.join(LHS, &RHSValNoAssignments[0], &LHSValNoAssignments[0], NewVNInfo); + } else { + LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo); + } } bool StrongPHIElimination::runOnMachineFunction(MachineFunction &Fn) { From evan.cheng at apple.com Mon Mar 17 01:44:33 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Sun, 16 Mar 2008 23:44:33 -0700 Subject: [llvm-commits] [llvm] r48412 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/LowerSubregs.cpp lib/CodeGen/SelectionDAG/ScheduleDAG.cpp lib/Target/Target.td lib/Target/TargetSelectionDAG.td lib/Target/X86/X86ISelDAGToDAG.cpp lib/Target/X86/X86Instr64bit.td lib/Target/X86/X86InstrInfo.cpp utils/TableGen/CodeEmitterGen.cpp utils/TableGen/CodeGenTarget.cpp utils/TableGen/InstrInfoEmitter.cpp In-Reply-To: <200803160312.m2G3C4sN029979@zion.cs.uiuc.edu> References: <200803160312.m2G3C4sN029979@zion.cs.uiuc.edu> Message-ID: <78BF4D4F-9B93-402B-B3BB-C561D37322CD@apple.com> Hi Chris, Thanks. This patch is a step in the right direction. However it will likely needs to be revised again soon. Sorry I wasn't being clearer earlier. The other Chris and I now feel that it isn't necessary to have a separate form of insert_subreg for inserting into an undef. The register allocator will treat IMPLICIT_DEF defined interval as a special zero length interval. This will allow these insert_subreg instructions to be coalesced away. Let's talk again when we are there in a day or so. Evan On Mar 15, 2008, at 8:12 PM, Christopher Lamb wrote: > Author: clamb > Date: Sat Mar 15 22:12:01 2008 > New Revision: 48412 > > URL: http://llvm.org/viewvc/llvm-project?rev=48412&view=rev > Log: > Make insert_subreg a two-address instruction, vastly simplifying > LowerSubregs pass. Add a new TII, subreg_to_reg, which is like > insert_subreg except that it takes an immediate implicit value to > insert into rather than a register. > > > Modified: > llvm/trunk/include/llvm/Target/TargetInstrInfo.h > llvm/trunk/lib/CodeGen/LowerSubregs.cpp > llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp > llvm/trunk/lib/Target/Target.td > llvm/trunk/lib/Target/TargetSelectionDAG.td > llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp > llvm/trunk/lib/Target/X86/X86Instr64bit.td > llvm/trunk/lib/Target/X86/X86InstrInfo.cpp > llvm/trunk/utils/TableGen/CodeEmitterGen.cpp > llvm/trunk/utils/TableGen/CodeGenTarget.cpp > llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp > > Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=48412&r1=48411&r2=48412&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original) > +++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Sat Mar 15 > 22:12:01 2008 > @@ -50,16 +50,8 @@ > DECLARE = 3, > EXTRACT_SUBREG = 4, > INSERT_SUBREG = 5, > - IMPLICIT_DEF = 6 > - }; > - > - // Target independent implict values for use with subreg insert. > All targets > - // that support insert_subreg support IMPL_VAL_UNDEF. Support for > the other > - // values is target dependent. > - enum ImplictVal { > - IMPL_VAL_UNDEF = 0, > - IMPL_VAL_ZERO = 1, > - LAST_IMPL_VAL = 3 > + IMPLICIT_DEF = 6, > + SUBREG_TO_REG = 7 > }; > > unsigned getNumOpcodes() const { return NumOpcodes; } > > Modified: llvm/trunk/lib/CodeGen/LowerSubregs.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LowerSubregs.cpp?rev=48412&r1=48411&r2=48412&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/CodeGen/LowerSubregs.cpp (original) > +++ llvm/trunk/lib/CodeGen/LowerSubregs.cpp Sat Mar 15 22:12:01 2008 > @@ -35,6 +35,7 @@ > > bool LowerExtract(MachineInstr *MI); > bool LowerInsert(MachineInstr *MI); > + bool LowerSubregToReg(MachineInstr *MI); > }; > > char LowerSubregsInstructionPass::ID = 0; > @@ -54,29 +55,28 @@ > MI->getOperand(1).isRegister() && MI- > >getOperand(1).isUse() && > MI->getOperand(2).isImmediate() && "Malformed > extract_subreg"); > > + unsigned DstReg = MI->getOperand(0).getReg(); > unsigned SuperReg = MI->getOperand(1).getReg(); > - unsigned SubIdx = MI->getOperand(2).getImm(); > + unsigned SubIdx = MI->getOperand(2).getImm(); > + unsigned SrcReg = TRI.getSubReg(SuperReg, SubIdx); > > assert(TargetRegisterInfo::isPhysicalRegister(SuperReg) && > "Extract supperg source must be a physical register"); > - unsigned SrcReg = TRI.getSubReg(SuperReg, SubIdx); > - unsigned DstReg = MI->getOperand(0).getReg(); > - > + assert(TargetRegisterInfo::isPhysicalRegister(DstReg) && > + "Insert destination must be in a physical register"); > + > DOUT << "subreg: CONVERTING: " << *MI; > > if (SrcReg != DstReg) { > - const TargetRegisterClass *TRC = 0; > - if (TargetRegisterInfo::isPhysicalRegister(DstReg)) { > - TRC = TRI.getPhysicalRegisterRegClass(DstReg); > - } else { > - TRC = MF.getRegInfo().getRegClass(DstReg); > - } > + const TargetRegisterClass *TRC = > TRI.getPhysicalRegisterRegClass(DstReg); > assert(TRC == TRI.getPhysicalRegisterRegClass(SrcReg) && > "Extract subreg and Dst must be of same register class"); > - > TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC, TRC); > + > +#ifndef NDEBUG > MachineBasicBlock::iterator dMI = MI; > DOUT << "subreg: " << *(--dMI); > +#endif > } > > DOUT << "\n"; > @@ -84,115 +84,80 @@ > return true; > } > > - > -bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) { > +bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr > *MI) { > MachineBasicBlock *MBB = MI->getParent(); > MachineFunction &MF = *MBB->getParent(); > const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo(); > const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); > assert((MI->getOperand(0).isRegister() && MI- > >getOperand(0).isDef()) && > - ((MI->getOperand(1).isRegister() && MI- > >getOperand(1).isUse()) || > - MI->getOperand(1).isImmediate()) && > + MI->getOperand(1).isImmediate() && > (MI->getOperand(2).isRegister() && MI- > >getOperand(2).isUse()) && > - MI->getOperand(3).isImmediate() && "Invalid > insert_subreg"); > + MI->getOperand(3).isImmediate() && "Invalid > subreg_to_reg"); > > - // Check if we're inserting into an implicit undef value. > - bool isImplicit = MI->getOperand(1).isImmediate(); > - unsigned DstReg = MI->getOperand(0).getReg(); > - unsigned SrcReg = isImplicit ? DstReg : MI->getOperand(1).getReg(); > - unsigned InsReg = MI->getOperand(2).getReg(); > - unsigned SubIdx = MI->getOperand(3).getImm(); > + unsigned DstReg = MI->getOperand(0).getReg(); > + unsigned InsReg = MI->getOperand(2).getReg(); > + unsigned SubIdx = MI->getOperand(3).getImm(); > > - assert(SubIdx != 0 && "Invalid index for extract_subreg"); > + assert(SubIdx != 0 && "Invalid index for insert_subreg"); > unsigned DstSubReg = TRI.getSubReg(DstReg, SubIdx); > - > - assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) && > - "Insert superreg source must be in a physical register"); > + > assert(TargetRegisterInfo::isPhysicalRegister(DstReg) && > "Insert destination must be in a physical register"); > assert(TargetRegisterInfo::isPhysicalRegister(InsReg) && > "Inserted value must be in a physical register"); > > DOUT << "subreg: CONVERTING: " << *MI; > - > - // Check whether the implict subreg copy has side affects or not. > Only copies > - // into an undef value have no side affects, that is they can be > eliminated > - // without changing the semantics of the program. > - bool copyHasSideAffects = isImplicit? > - MI->getOperand(1).getImm() != > TargetInstrInfo::IMPL_VAL_UNDEF > - : false; > - > - // If the inserted register is already allocated into a subregister > - // of the destination, we copy the subreg into the source > - // However, this is only safe if the insert instruction is the kill > - // of the source register > - bool revCopyOrder = TRI.isSubRegister(DstReg, InsReg); > - if (revCopyOrder && (InsReg != DstSubReg || copyHasSideAffects)) { > - if (isImplicit || MI->getOperand(1).isKill()) { > - DstSubReg = TRI.getSubReg(SrcReg, SubIdx); > - // Insert sub-register copy > - const TargetRegisterClass *TRC1 = 0; > - if (TargetRegisterInfo::isPhysicalRegister(InsReg)) { > - TRC1 = TRI.getPhysicalRegisterRegClass(InsReg); > - } else { > - TRC1 = MF.getRegInfo().getRegClass(InsReg); > - } > - TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1); > + > + // Insert sub-register copy > + const TargetRegisterClass *TRC0 = > TRI.getPhysicalRegisterRegClass(DstSubReg); > + const TargetRegisterClass *TRC1 = > TRI.getPhysicalRegisterRegClass(InsReg); > + TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1); > > #ifndef NDEBUG > - MachineBasicBlock::iterator dMI = MI; > - DOUT << "subreg: " << *(--dMI); > -#endif > - } else { > - assert(0 && "Don't know how to convert this insert"); > - } > - } > -#ifndef NDEBUG > - if (InsReg == DstSubReg && !copyHasSideAffects) { > - DOUT << "subreg: Eliminated subreg copy\n"; > - } > + MachineBasicBlock::iterator dMI = MI; > + DOUT << "subreg: " << *(--dMI); > #endif > > - if (SrcReg != DstReg) { > - // Insert super-register copy > - const TargetRegisterClass *TRC0 = 0; > - if (TargetRegisterInfo::isPhysicalRegister(DstReg)) { > - TRC0 = TRI.getPhysicalRegisterRegClass(DstReg); > - } else { > - TRC0 = MF.getRegInfo().getRegClass(DstReg); > - } > - assert(TRC0 == TRI.getPhysicalRegisterRegClass(SrcReg) && > - "Insert superreg and Dst must be of same register > class"); > + DOUT << "\n"; > + MBB->remove(MI); > + return true; > +} > > - TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC0, TRC0); > +bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) { > + MachineBasicBlock *MBB = MI->getParent(); > + MachineFunction &MF = *MBB->getParent(); > + const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo(); > + const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); > + assert((MI->getOperand(0).isRegister() && MI- > >getOperand(0).isDef()) && > + (MI->getOperand(1).isRegister() && MI- > >getOperand(1).isUse()) && > + (MI->getOperand(2).isRegister() && MI- > >getOperand(2).isUse()) && > + MI->getOperand(3).isImmediate() && "Invalid > insert_subreg"); > + > + unsigned DstReg = MI->getOperand(0).getReg(); > + unsigned SrcReg = MI->getOperand(1).getReg(); > + unsigned InsReg = MI->getOperand(2).getReg(); > + unsigned SubIdx = MI->getOperand(3).getImm(); > > -#ifndef NDEBUG > - MachineBasicBlock::iterator dMI = MI; > - DOUT << "subreg: " << *(--dMI); > -#endif > - } > + assert(DstReg == SrcReg && "insert_subreg not a two-address > instruction?"); > + assert(SubIdx != 0 && "Invalid index for insert_subreg"); > + unsigned DstSubReg = TRI.getSubReg(DstReg, SubIdx); > > -#ifndef NDEBUG > - if (SrcReg == DstReg) { > - DOUT << "subreg: Eliminated superreg copy\n"; > - } > -#endif > + assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) && > + "Insert superreg source must be in a physical register"); > + assert(TargetRegisterInfo::isPhysicalRegister(InsReg) && > + "Inserted value must be in a physical register"); > > - if (!revCopyOrder && (InsReg != DstSubReg || copyHasSideAffects)) { > - // Insert sub-register copy > - const TargetRegisterClass *TRC1 = 0; > - if (TargetRegisterInfo::isPhysicalRegister(InsReg)) { > - TRC1 = TRI.getPhysicalRegisterRegClass(InsReg); > - } else { > - TRC1 = MF.getRegInfo().getRegClass(InsReg); > - } > - TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1); > + DOUT << "subreg: CONVERTING: " << *MI; > + > + // Insert sub-register copy > + const TargetRegisterClass *TRC0 = > TRI.getPhysicalRegisterRegClass(DstSubReg); > + const TargetRegisterClass *TRC1 = > TRI.getPhysicalRegisterRegClass(InsReg); > + TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1); > > #ifndef NDEBUG > - MachineBasicBlock::iterator dMI = MI; > - DOUT << "subreg: " << *(--dMI); > + MachineBasicBlock::iterator dMI = MI; > + DOUT << "subreg: " << *(--dMI); > #endif > - } > > DOUT << "\n"; > MBB->remove(MI); > @@ -220,6 +185,8 @@ > MadeChange |= LowerExtract(MI); > } else if (MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG) { > MadeChange |= LowerInsert(MI); > + } else if (MI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG) { > + MadeChange |= LowerSubregToReg(MI); > } > } > } > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp?rev=48412&r1=48411&r2=48412&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Sat Mar 15 > 22:12:01 2008 > @@ -661,26 +661,24 @@ > DenseMap &VRBaseMap) { > unsigned VRBase = 0; > unsigned Opc = Node->getTargetOpcode(); > - if (Opc == TargetInstrInfo::EXTRACT_SUBREG) { > - // If the node is only used by a CopyToReg and the dest reg is > a vreg, use > - // the CopyToReg'd destination register instead of creating a > new vreg. > - for (SDNode::use_iterator UI = Node->use_begin(), E = Node- > >use_end(); > - UI != E; ++UI) { > - SDNode *Use = *UI; > - if (Use->getOpcode() == ISD::CopyToReg && > - Use->getOperand(2).Val == Node) { > - unsigned DestReg = cast(Use->getOperand(1))- > >getReg(); > - if (TargetRegisterInfo::isVirtualRegister(DestReg)) { > - VRBase = DestReg; > - break; > - } > + > + // If the node is only used by a CopyToReg and the dest reg is a > vreg, use > + // the CopyToReg'd destination register instead of creating a new > vreg. > + for (SDNode::use_iterator UI = Node->use_begin(), E = Node- > >use_end(); > + UI != E; ++UI) { > + SDNode *Use = *UI; > + if (Use->getOpcode() == ISD::CopyToReg && > + Use->getOperand(2).Val == Node) { > + unsigned DestReg = cast(Use->getOperand(1))- > >getReg(); > + if (TargetRegisterInfo::isVirtualRegister(DestReg)) { > + VRBase = DestReg; > + break; > } > } > - > + } > + > + if (Opc == TargetInstrInfo::EXTRACT_SUBREG) { > unsigned SubIdx = cast(Node->getOperand(1))- > >getValue(); > - > - // TODO: If the node is a use of a CopyFromReg from a physical > register > - // fold the extract into the copy now > > // Create the extract_subreg machine instruction. > MachineInstr *MI = > @@ -707,36 +705,14 @@ > AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap); > MI->addOperand(MachineOperand::CreateImm(SubIdx)); > > - } else if (Opc == TargetInstrInfo::INSERT_SUBREG) { > + } else if (Opc == TargetInstrInfo::INSERT_SUBREG || > + Opc == TargetInstrInfo::SUBREG_TO_REG) { > SDOperand N0 = Node->getOperand(0); > SDOperand N1 = Node->getOperand(1); > SDOperand N2 = Node->getOperand(2); > unsigned SubReg = getVR(N1, VRBaseMap); > unsigned SubIdx = cast(N2)->getValue(); > > - // TODO: Add tracking info to MachineRegisterInfo of which > vregs are subregs > - // to allow coalescing in the allocator > - > - // If the node is only used by a CopyToReg and the dest reg is > a vreg, use > - // the CopyToReg'd destination register instead of creating a > new vreg. > - // If the CopyToReg'd destination register is physical, then > fold the > - // insert into the copy > - for (SDNode::use_iterator UI = Node->use_begin(), E = Node- > >use_end(); > - UI != E; ++UI) { > - SDNode *Use = *UI; > - if (Use->getOpcode() == ISD::CopyToReg && > - Use->getOperand(2).Val == Node) { > - unsigned DestReg = cast(Use->getOperand(1))- > >getReg(); > - if (TargetRegisterInfo::isVirtualRegister(DestReg)) { > - VRBase = DestReg; > - break; > - } > - } > - } > - > - // Create the insert_subreg machine instruction. > - MachineInstr *MI = > - new MachineInstr(BB, TII->get(TargetInstrInfo::INSERT_SUBREG)); > > // Figure out the register class to create for the destreg. > const TargetRegisterClass *TRC = 0; > @@ -749,19 +725,23 @@ > VRBase = MRI.createVirtualRegister(TRC); // Create the reg > } > > + // Create the insert_subreg or subreg_to_reg machine instruction. > + MachineInstr *MI = > + new MachineInstr(BB, TII->get(Opc)); > MI->addOperand(MachineOperand::CreateReg(VRBase, true)); > > - // If N0 is a constant then it indicates the insert is being done > - // into a target specific constant value, not a register. > - if (const ConstantSDNode *SD = dyn_cast(N0)) > + // If creating a subreg_to_reg, then the first input operand > + // is an implicit value immediate, otherwise it's a register > + if (Opc == TargetInstrInfo::SUBREG_TO_REG) { > + const ConstantSDNode *SD = cast(N0); > MI->addOperand(MachineOperand::CreateImm(SD->getValue())); > - else > + } else > AddOperand(MI, N0, 0, 0, VRBaseMap); > // Add the subregster being inserted > AddOperand(MI, N1, 0, 0, VRBaseMap); > MI->addOperand(MachineOperand::CreateImm(SubIdx)); > } else > - assert(0 && "Node is not a subreg insert or extract"); > + assert(0 && "Node is not insert_subreg, extract_subreg, or > subreg_to_reg"); > > bool isNew = VRBaseMap.insert(std::make_pair(SDOperand(Node,0), > VRBase)); > assert(isNew && "Node emitted out of order - early"); > @@ -777,7 +757,8 @@ > > // Handle subreg insert/extract specially > if (Opc == TargetInstrInfo::EXTRACT_SUBREG || > - Opc == TargetInstrInfo::INSERT_SUBREG) { > + Opc == TargetInstrInfo::INSERT_SUBREG || > + Opc == TargetInstrInfo::SUBREG_TO_REG) { > EmitSubregNode(Node, VRBaseMap); > return; > } > > Modified: llvm/trunk/lib/Target/Target.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Target.td?rev=48412&r1=48411&r2=48412&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/Target.td (original) > +++ llvm/trunk/lib/Target/Target.td Sat Mar 15 22:12:01 2008 > @@ -366,6 +366,7 @@ > let AsmString = ""; > let Namespace = "TargetInstrInfo"; > let neverHasSideEffects = 1; > + let Constraints = "$supersrc = $dst"; > } > def IMPLICIT_DEF : Instruction { > let OutOperandList = (ops unknown:$dst); > @@ -374,6 +375,13 @@ > let Namespace = "TargetInstrInfo"; > let neverHasSideEffects = 1; > } > +def SUBREG_TO_REG : Instruction { > + let OutOperandList = (ops unknown:$dst); > + let InOperandList = (ops unknown:$implsrc, unknown:$subsrc, > i32imm:$subidx); > + let AsmString = ""; > + let Namespace = "TargetInstrInfo"; > + let neverHasSideEffects = 1; > +} > > // > = > = > = > ----------------------------------------------------------------------= > ==// > // AsmWriter - This class can be implemented by targets that need to > customize > > Modified: llvm/trunk/lib/Target/TargetSelectionDAG.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetSelectionDAG.td?rev=48412&r1=48411&r2=48412&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/TargetSelectionDAG.td (original) > +++ llvm/trunk/lib/Target/TargetSelectionDAG.td Sat Mar 15 22:12:01 > 2008 > @@ -918,11 +918,3 @@ > def SDT_dwarf_loc : SDTypeProfile<0, 3, > [SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>]>; > def dwarf_loc : SDNode<"ISD::DEBUG_LOC", SDT_dwarf_loc, > [SDNPHasChain]>; > - > -// > = > = > = > ----------------------------------------------------------------------= > ==// > -// Implict value insert subreg support. > -// > -// These should match the enum TargetInstrInfo::ImplictVal. > -def tii_impl_val_undef : PatLeaf<(i32 0)>; > -def tii_impl_val_zero : PatLeaf<(i32 1)>; > - > > Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=48412&r1=48411&r2=48412&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original) > +++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Sat Mar 15 > 22:12:01 2008 > @@ -1529,39 +1529,36 @@ > } > > case ISD::ANY_EXTEND: { > + // Check if the type extended to supports subregs. > + if (NVT == MVT::i8) > + break; > + > SDOperand N0 = Node->getOperand(0); > + // Get the subregsiter index for the type to extend. > + MVT::ValueType N0VT = N0.getValueType(); > + unsigned Idx = (N0VT == MVT::i32) ? X86::SUBREG_32BIT : > + (N0VT == MVT::i16) ? X86::SUBREG_16BIT : > + (Subtarget->is64Bit()) ? X86::SUBREG_8BIT : > 0; > + > + // If we don't have a subreg Idx, let generated ISel have a > try. > + if (Idx == 0) > + break; > + > + // If we have an index, generate an insert_subreg into undef. > AddToISelQueue(N0); > - if (NVT == MVT::i64 || NVT == MVT::i32 || NVT == MVT::i16) { > - SDOperand SRIdx; > - switch(N0.getValueType()) { > - case MVT::i32: > - SRIdx = CurDAG->getTargetConstant(X86::SUBREG_32BIT, > MVT::i32); > - break; > - case MVT::i16: > - SRIdx = CurDAG->getTargetConstant(X86::SUBREG_16BIT, > MVT::i32); > - break; > - case MVT::i8: > - if (Subtarget->is64Bit()) > - SRIdx = CurDAG->getTargetConstant(X86::SUBREG_8BIT, > MVT::i32); > - break; > - default: assert(0 && "Unknown any_extend!"); > - } > - if (SRIdx.Val) { > - SDOperand ImplVal = > - CurDAG- > >getTargetConstant(X86InstrInfo::IMPL_VAL_UNDEF, MVT::i32); > - SDNode *ResNode = CurDAG->getTargetNode(X86::INSERT_SUBREG, > - NVT, ImplVal, N0, > SRIdx); > + SDOperand Undef = > + SDOperand(CurDAG- > >getTargetNode(X86::IMPLICIT_DEF, NVT), 0); > + SDOperand SRIdx = CurDAG->getTargetConstant(Idx, MVT::i32); > + SDNode *ResNode = CurDAG->getTargetNode(X86::INSERT_SUBREG, > + NVT, Undef, N0, > SRIdx); > > #ifndef NDEBUG > - DOUT << std::string(Indent-2, ' ') << "=> "; > - DEBUG(ResNode->dump(CurDAG)); > - DOUT << "\n"; > - Indent -= 2; > + DOUT << std::string(Indent-2, ' ') << "=> "; > + DEBUG(ResNode->dump(CurDAG)); > + DOUT << "\n"; > + Indent -= 2; > #endif > - return ResNode; > - } // Otherwise let generated ISel handle it. > - } > - break; > + return ResNode; > } > > case ISD::SIGN_EXTEND_INREG: { > > Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=48412&r1=48411&r2=48412&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original) > +++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Sat Mar 15 22:12:01 > 2008 > @@ -1202,43 +1202,43 @@ > > > // Zero-extension > -def : Pat<(i64 (zext GR32:$src)), (INSERT_SUBREG tii_impl_val_zero, > - GR32:$src, > x86_subreg_32bit)>; > +def : Pat<(i64 (zext GR32:$src)), > + (SUBREG_TO_REG (i64 0), GR32:$src, x86_subreg_32bit)>; > > // zextload bool -> zextload byte > def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>; > > -def : Pat<(zextloadi64i32 addr:$src), (INSERT_SUBREG > tii_impl_val_zero, > - (MOV32rm addr:$src), > x86_subreg_32bit)>; > +def : Pat<(zextloadi64i32 addr:$src), > + (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), > x86_subreg_32bit)>; > > // extload > def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>; > def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>; > def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>; > -def : Pat<(extloadi64i32 addr:$src), (INSERT_SUBREG > tii_impl_val_undef, > - (MOV32rm addr:$src), > x86_subreg_32bit)>; > +def : Pat<(extloadi64i32 addr:$src), > + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (MOV32rm addr:$src), > + x86_subreg_32bit)>; > > // anyext -> zext > def : Pat<(i64 (anyext GR8 :$src)), (MOVZX64rr8 GR8 :$src)>; > def : Pat<(i64 (anyext GR16:$src)), (MOVZX64rr16 GR16:$src)>; > -def : Pat<(i64 (anyext GR32:$src)), (INSERT_SUBREG > tii_impl_val_undef, > - GR32:$src, > x86_subreg_32bit)>; > +def : Pat<(i64 (anyext GR32:$src)), > + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, > x86_subreg_32bit)>; > > def : Pat<(i64 (anyext (loadi8 addr:$src))), (MOVZX64rm8 addr: > $src)>; > def : Pat<(i64 (anyext (loadi16 addr:$src))), (MOVZX64rm16 addr: > $src)>; > -def : Pat<(i64 (anyext (loadi32 addr:$src))), (INSERT_SUBREG > tii_impl_val_undef, > - (MOV32rm addr:$src), > - x86_subreg_32bit)>; > +def : Pat<(i64 (anyext (loadi32 addr:$src))), > + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (MOV32rm addr:$src), > + > x86_subreg_32bit)>; > > // > = > = > = > ----------------------------------------------------------------------= > ==// > // Some peepholes > // > = > = > = > ----------------------------------------------------------------------= > ==// > > - > // r & (2^32-1) ==> mov32 + implicit zext > def : Pat<(and GR64:$src, i64immFFFFFFFF), > - (INSERT_SUBREG tii_impl_val_zero, > - (MOV32rr (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit)), > + (SUBREG_TO_REG (i64 0), > + (i32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit)), > x86_subreg_32bit)>; > > // (shl x, 1) ==> (add x, x) > > Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=48412&r1=48411&r2=48412&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) > +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Sat Mar 15 22:12:01 > 2008 > @@ -920,10 +920,11 @@ > > // Build and insert into an implicit UNDEF value. This is OK > because > // well be shifting and then extracting the lower 16-bits. > + MachineInstr *Undef = BuildMI(get(X86::IMPLICIT_DEF), > leaInReg); > + > MachineInstr *Ins = > BuildMI(get(X86::INSERT_SUBREG),leaInReg) > - .addImm(X86InstrInfo::IMPL_VAL_UNDEF) > - .addReg(Src).addImm(X86::SUBREG_16BIT); > + > .addReg > (leaInReg).addReg(Src).addImm(X86::SUBREG_16BIT); > > NewMI = BuildMI(get(Opc), leaOutReg) > .addReg(0).addImm(1 << ShAmt).addReg(leaInReg).addImm(0); > @@ -933,6 +934,7 @@ > .addReg(leaOutReg).addImm(X86::SUBREG_16BIT); > Ext->copyKillDeadInfo(MI); > > + MFI->insert(MBBI, Undef); > MFI->insert(MBBI, Ins); // Insert the insert_subreg > LV.instructionChanged(MI, NewMI); // Update live variables > LV.addVirtualRegisterKilled(leaInReg, NewMI); > > Modified: llvm/trunk/utils/TableGen/CodeEmitterGen.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeEmitterGen.cpp?rev=48412&r1=48411&r2=48412&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/utils/TableGen/CodeEmitterGen.cpp (original) > +++ llvm/trunk/utils/TableGen/CodeEmitterGen.cpp Sat Mar 15 22:12:01 > 2008 > @@ -30,7 +30,8 @@ > R->getName() == "DECLARE" || > R->getName() == "EXTRACT_SUBREG" || > R->getName() == "INSERT_SUBREG" || > - R->getName() == "IMPLICIT_DEF") continue; > + R->getName() == "IMPLICIT_DEF" || > + R->getName() == "SUBREG_TO_REG") continue; > > BitsInit *BI = R->getValueAsBitsInit("Inst"); > > @@ -105,7 +106,8 @@ > R->getName() == "DECLARE" || > R->getName() == "EXTRACT_SUBREG" || > R->getName() == "INSERT_SUBREG" || > - R->getName() == "IMPLICIT_DEF") { > + R->getName() == "IMPLICIT_DEF" || > + R->getName() == "SUBREG_TO_REG") { > o << " 0U"; > continue; > } > @@ -139,7 +141,8 @@ > InstName == "DECLARE"|| > InstName == "EXTRACT_SUBREG" || > InstName == "INSERT_SUBREG" || > - InstName == "IMPLICIT_DEF") continue; > + InstName == "IMPLICIT_DEF" || > + InstName == "SUBREG_TO_REG") continue; > > BitsInit *BI = R->getValueAsBitsInit("Inst"); > const std::vector &Vals = R->getValues(); > > Modified: llvm/trunk/utils/TableGen/CodeGenTarget.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.cpp?rev=48412&r1=48411&r2=48412&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/utils/TableGen/CodeGenTarget.cpp (original) > +++ llvm/trunk/utils/TableGen/CodeGenTarget.cpp Sat Mar 15 22:12:01 > 2008 > @@ -309,6 +309,11 @@ > throw "Could not find 'IMPLICIT_DEF' instruction!"; > const CodeGenInstruction *IMPLICIT_DEF = &I->second; > > + I = getInstructions().find("SUBREG_TO_REG"); > + if (I == Instructions.end()) > + throw "Could not find 'SUBREG_TO_REG' instruction!"; > + const CodeGenInstruction *SUBREG_TO_REG = &I->second; > + > // Print out the rest of the instructions now. > NumberedInstructions.push_back(PHI); > NumberedInstructions.push_back(INLINEASM); > @@ -317,6 +322,7 @@ > NumberedInstructions.push_back(EXTRACT_SUBREG); > NumberedInstructions.push_back(INSERT_SUBREG); > NumberedInstructions.push_back(IMPLICIT_DEF); > + NumberedInstructions.push_back(SUBREG_TO_REG); > for (inst_iterator II = inst_begin(), E = inst_end(); II != E; ++II) > if (&II->second != PHI && > &II->second != INLINEASM && > @@ -324,7 +330,8 @@ > &II->second != DECLARE && > &II->second != EXTRACT_SUBREG && > &II->second != INSERT_SUBREG && > - &II->second != IMPLICIT_DEF) > + &II->second != IMPLICIT_DEF && > + &II->second != SUBREG_TO_REG) > NumberedInstructions.push_back(&II->second); > } > > > Modified: llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp?rev=48412&r1=48411&r2=48412&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp (original) > +++ llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp Sat Mar 15 > 22:12:01 2008 > @@ -411,7 +411,8 @@ > R->getName() != "DECLARE" && > R->getName() != "EXTRACT_SUBREG" && > R->getName() != "INSERT_SUBREG" && > - R->getName() != "IMPLICIT_DEF") > + R->getName() != "IMPLICIT_DEF" && > + R->getName() != "SUBREG_TO_REG") > throw R->getName() + " doesn't have a field named '" + > Val->getValue() + "'!"; > return; > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From evan.cheng at apple.com Mon Mar 17 01:56:03 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Sun, 16 Mar 2008 23:56:03 -0700 Subject: [llvm-commits] Patch to IfCvt In-Reply-To: <3491F16B-60DC-4930-9DF2-651B3056189E@gmail.com> References: <3491F16B-60DC-4930-9DF2-651B3056189E@gmail.com> Message-ID: <7B1820C5-29EF-48FA-8B78-59540AED1543@apple.com> + // We only have to predicate the block if we could fall through to it + if (!TII->BlockHasNoFallThrough(*BBI1->BB)) + PredicateBlock(*BBI2, DI2, *Cond2); I don't think this is the right fix. Whether the sub-cfg is a candidate diamond shape to be if-converted should be determined earlier. Also, the test is whether the true block has a fallthrough, which doesn't seem to match the comment. Do you have a test case in mind? Please file a bug or send it to me. Thanks, Evan On Mar 15, 2008, at 9:20 PM, Christopher Lamb wrote: > Is this patch safe? It passes the .dg tests and seems reasonable to > me, but I don't have an ARM to actually run tests on. > -- > Christopher Lamb > > > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From evan.cheng at apple.com Mon Mar 17 01:56:52 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 17 Mar 2008 06:56:52 -0000 Subject: [llvm-commits] [llvm] r48447 - in /llvm/trunk/lib/Target: Alpha/AlphaCodeEmitter.cpp PowerPC/PPCCodeEmitter.cpp X86/X86CodeEmitter.cpp Message-ID: <200803170656.m2H6uqYv009325@zion.cs.uiuc.edu> Author: evancheng Date: Mon Mar 17 01:56:52 2008 New Revision: 48447 URL: http://llvm.org/viewvc/llvm-project?rev=48447&view=rev Log: Unbreak JIT. Ignore TargetInstrInfo::IMPLICIT_DEF. Modified: llvm/trunk/lib/Target/Alpha/AlphaCodeEmitter.cpp llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp Modified: llvm/trunk/lib/Target/Alpha/AlphaCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaCodeEmitter.cpp?rev=48447&r1=48446&r2=48447&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaCodeEmitter.cpp Mon Mar 17 01:56:52 2008 @@ -95,6 +95,7 @@ case Alpha::ALTENT: case Alpha::PCLABEL: case Alpha::MEMLABEL: + case TargetInstrInfo::IMPLICIT_DEF: break; //skip these } } Modified: llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp?rev=48447&r1=48446&r2=48447&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp Mon Mar 17 01:56:52 2008 @@ -112,6 +112,8 @@ case TargetInstrInfo::LABEL: MCE.emitLabel(MI.getOperand(0).getImm()); break; + case TargetInstrInfo::IMPLICIT_DEF: + break; // pseudo opcode, no side effects case PPC::MovePCtoLR: case PPC::MovePCtoLR8: assert(TM.getRelocationModel() == Reloc::PIC_); Modified: llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp?rev=48447&r1=48446&r2=48447&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp Mon Mar 17 01:56:52 2008 @@ -621,6 +621,7 @@ case TargetInstrInfo::LABEL: MCE.emitLabel(MI.getOperand(0).getImm()); break; + case TargetInstrInfo::IMPLICIT_DEF: case TargetInstrInfo::DECLARE: case X86::DWARF_LOC: case X86::FP_REG_KILL: From sabre at nondot.org Mon Mar 17 01:57:02 2008 From: sabre at nondot.org (Chris Lattner) Date: Mon, 17 Mar 2008 06:57:02 -0000 Subject: [llvm-commits] [llvm] r48448 - /llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Message-ID: <200803170657.m2H6v2Ls009342@zion.cs.uiuc.edu> Author: lattner Date: Mon Mar 17 01:57:02 2008 New Revision: 48448 URL: http://llvm.org/viewvc/llvm-project?rev=48448&view=rev Log: minor cleanups Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=48448&r1=48447&r2=48448&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Mon Mar 17 01:57:02 2008 @@ -227,11 +227,10 @@ SDOperand MipsTargetLowering:: LowerCALL(SDOperand Op, SelectionDAG &DAG) { - unsigned CallingConv= cast(Op.getOperand(1))->getValue(); + unsigned CallingConv = cast(Op.getOperand(1))->getValue(); // By now, only CallingConv::C implemented - switch (CallingConv) - { + switch (CallingConv) { default: assert(0 && "Unsupported calling convention"); case CallingConv::Fast: @@ -248,7 +247,6 @@ LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC) { MachineFunction &MF = DAG.getMachineFunction(); - unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF); SDOperand Chain = Op.getOperand(0); SDOperand Callee = Op.getOperand(4); @@ -275,8 +273,7 @@ SmallVector, 8> RegsToPass; SmallVector MemOpChains; - SDOperand StackPtr; - int LastStackLoc=0; + int LastStackLoc = 0; // Walk the register/memloc assignments, inserting copies/loads. for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { @@ -287,43 +284,40 @@ // Promote the value if needed. switch (VA.getLocInfo()) { - default: assert(0 && "Unknown loc info!"); - case CCValAssign::Full: break; - case CCValAssign::SExt: - Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg); - break; - case CCValAssign::ZExt: - Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg); - break; - case CCValAssign::AExt: - Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg); - break; + default: assert(0 && "Unknown loc info!"); + case CCValAssign::Full: break; + case CCValAssign::SExt: + Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg); + break; + case CCValAssign::ZExt: + Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg); + break; + case CCValAssign::AExt: + Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg); + break; } // Arguments that can be passed on register must be kept at // RegsToPass vector if (VA.isRegLoc()) { RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); - } else { - - assert(VA.isMemLoc()); - - if (StackPtr.Val == 0) - StackPtr = DAG.getRegister(StackReg, getPointerTy()); - - // Create the frame index object for this incoming parameter - // This guarantees that when allocating Local Area the firsts - // 16 bytes which are alwayes reserved won't be overwritten. - LastStackLoc = (16 + VA.getLocMemOffset()); - int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8, - LastStackLoc); - - SDOperand PtrOff = DAG.getFrameIndex(FI,getPointerTy()); - - // emit ISD::STORE whichs stores the - // parameter value to a stack Location - MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); + continue; } + + assert(VA.isMemLoc()); + + // Create the frame index object for this incoming parameter + // This guarantees that when allocating Local Area the firsts + // 16 bytes which are alwayes reserved won't be overwritten. + LastStackLoc = (16 + VA.getLocMemOffset()); + int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8, + LastStackLoc); + + SDOperand PtrOff = DAG.getFrameIndex(FI,getPointerTy()); + + // emit ISD::STORE whichs stores the + // parameter value to a stack Location + MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); } // Transform all store nodes into one single node because From sabre at nondot.org Mon Mar 17 01:58:38 2008 From: sabre at nondot.org (Chris Lattner) Date: Mon, 17 Mar 2008 06:58:38 -0000 Subject: [llvm-commits] [llvm] r48449 - in /llvm/trunk/lib/Target/Sparc: SparcCallingConv.td SparcISelLowering.cpp Message-ID: <200803170658.m2H6wcWm009393@zion.cs.uiuc.edu> Author: lattner Date: Mon Mar 17 01:58:37 2008 New Revision: 48449 URL: http://llvm.org/viewvc/llvm-project?rev=48449&view=rev Log: Check in some #ifdef'd out code switching call argument lowering over to SparcCallingConv.td. We can't make the switch yet because we can't say to pass f64 registers in 2 x i32 registers with the td file yet. Modified: llvm/trunk/lib/Target/Sparc/SparcCallingConv.td llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Modified: llvm/trunk/lib/Target/Sparc/SparcCallingConv.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcCallingConv.td?rev=48449&r1=48448&r2=48449&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcCallingConv.td (original) +++ llvm/trunk/lib/Target/Sparc/SparcCallingConv.td Mon Mar 17 01:58:37 2008 @@ -21,3 +21,12 @@ CCIfType<[f32], CCAssignToReg<[F0]>>, CCIfType<[f64], CCAssignToReg<[D0]>> ]>; + +// Sparc 32-bit C Calling convention. +def CC_Sparc32 : CallingConv<[ + // All arguments get passed in integer registers if there is space. + CCIfType<[i32, f32, f64], CCAssignToReg<[I0, I1, I2, I3, I4, I5]>>, + + // Alternatively, they are assigned to the stack in 4-byte aligned units. + CCAssignToStack<4, 4> +]>; Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp?rev=48449&r1=48448&r2=48449&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Mon Mar 17 01:58:37 2008 @@ -231,38 +231,96 @@ SDOperand Callee = Op.getOperand(4); bool isVarArg = cast(Op.getOperand(2))->getValue() != 0; +#if 0 + // Analyze operands of the call, assigning locations to each operand. + SmallVector ArgLocs; + CCState CCInfo(CallingConv, isVarArg, DAG.getTarget(), ArgLocs); + CCInfo.AnalyzeCallOperands(Op.Val, CC_Sparc32); + + // Get the size of the outgoing arguments stack space requirement. + unsigned ArgsSize = CCInfo.getNextStackOffset(); + // FIXME: We can't use this until f64 is known to take two GPRs. +#else + (void)CC_Sparc32; + // Count the size of the outgoing arguments. unsigned ArgsSize = 0; for (unsigned i = 5, e = Op.getNumOperands(); i != e; i += 2) { switch (Op.getOperand(i).getValueType()) { - default: assert(0 && "Unknown value type!"); - case MVT::i1: - case MVT::i8: - case MVT::i16: - case MVT::i32: - case MVT::f32: - ArgsSize += 4; - break; - case MVT::i64: - case MVT::f64: - ArgsSize += 8; - break; + default: assert(0 && "Unknown value type!"); + case MVT::i1: + case MVT::i8: + case MVT::i16: + case MVT::i32: + case MVT::f32: + ArgsSize += 4; + break; + case MVT::i64: + case MVT::f64: + ArgsSize += 8; + break; } } if (ArgsSize > 4*6) ArgsSize -= 4*6; // Space for first 6 arguments is prereserved. else ArgsSize = 0; - +#endif + // Keep stack frames 8-byte aligned. ArgsSize = (ArgsSize+7) & ~7; - Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(ArgsSize, MVT::i32)); + Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize)); + + SmallVector, 8> RegsToPass; + SmallVector MemOpChains; + +#if 0 + // Walk the register/memloc assignments, inserting copies/loads. + for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { + CCValAssign &VA = ArgLocs[i]; + + // Arguments start after the 5 first operands of ISD::CALL + SDOperand Arg = Op.getOperand(5+2*VA.getValNo()); + + // Promote the value if needed. + switch (VA.getLocInfo()) { + default: assert(0 && "Unknown loc info!"); + case CCValAssign::Full: break; + case CCValAssign::SExt: + Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg); + break; + case CCValAssign::ZExt: + Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg); + break; + case CCValAssign::AExt: + Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg); + break; + } + + // Arguments that can be passed on register must be kept at + // RegsToPass vector + if (VA.isRegLoc()) { + RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); + continue; + } + + assert(VA.isMemLoc()); + + // Create a store off the stack pointer for this argument. + SDOperand StackPtr = DAG.getRegister(SP::O6, MVT::i32); + // FIXME: VERIFY THAT 68 IS RIGHT. + SDOperand PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+68); + PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); + MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); + } - SDOperand StackPtr; - std::vector Stores; - std::vector RegValuesToPass; +#else + static const unsigned ArgRegs[] = { + SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 + }; unsigned ArgOffset = 68; + for (unsigned i = 5, e = Op.getNumOperands(); i != e; i += 2) { SDOperand Val = Op.getOperand(i); MVT::ValueType ObjectVT = Val.getValueType(); @@ -273,20 +331,20 @@ case MVT::i32: ObjSize = 4; - if (RegValuesToPass.size() >= 6) { + if (RegsToPass.size() >= 6) { ValToStore = Val; } else { - RegValuesToPass.push_back(Val); + RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Val)); } break; case MVT::f32: ObjSize = 4; - if (RegValuesToPass.size() >= 6) { + if (RegsToPass.size() >= 6) { ValToStore = Val; } else { // Convert this to a FP value in an int reg. Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val); - RegValuesToPass.push_back(Val); + RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Val)); } break; case MVT::f64: @@ -296,7 +354,7 @@ // FALL THROUGH case MVT::i64: ObjSize = 8; - if (RegValuesToPass.size() >= 6) { + if (RegsToPass.size() >= 6) { ValToStore = Val; // Whole thing is passed in memory. break; } @@ -306,42 +364,45 @@ DAG.getConstant(1, MVT::i32)); SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val, DAG.getConstant(0, MVT::i32)); - RegValuesToPass.push_back(Hi); + RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Hi)); - if (RegValuesToPass.size() >= 6) { + if (RegsToPass.size() >= 6) { ValToStore = Lo; ArgOffset += 4; ObjSize = 4; } else { - RegValuesToPass.push_back(Lo); + RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Lo)); } break; } if (ValToStore.Val) { - if (!StackPtr.Val) { - StackPtr = DAG.getRegister(SP::O6, MVT::i32); - } + SDOperand StackPtr = DAG.getRegister(SP::O6, MVT::i32); SDOperand PtrOff = DAG.getConstant(ArgOffset, MVT::i32); PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); - Stores.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0)); + MemOpChains.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0)); } ArgOffset += ObjSize; } +#endif // Emit all stores, make sure the occur before any copies into physregs. - if (!Stores.empty()) - Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0],Stores.size()); - - static const unsigned ArgRegs[] = { - SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5 - }; - - // Build a sequence of copy-to-reg nodes chained together with token chain - // and flag operands which copy the outgoing args into O[0-5]. + if (!MemOpChains.empty()) + Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, + &MemOpChains[0], MemOpChains.size()); + + // Build a sequence of copy-to-reg nodes chained together with token + // chain and flag operands which copy the outgoing args into registers. + // The InFlag in necessary since all emited instructions must be + // stuck together. SDOperand InFlag; - for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) { - Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag); + for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { + unsigned Reg = RegsToPass[i].first; + // Remap I0->I7 -> O0->O7. + if (Reg >= SP::I0 && Reg <= SP::I7) + Reg = Reg-SP::I0+SP::O0; + + Chain = DAG.getCopyToReg(Chain, Reg, RegsToPass[i].second, InFlag); InFlag = Chain.getValue(1); } @@ -367,9 +428,9 @@ // Assign locations to each value returned by this call. SmallVector RVLocs; - CCState CCInfo(CallingConv, isVarArg, DAG.getTarget(), RVLocs); + CCState RVInfo(CallingConv, isVarArg, DAG.getTarget(), RVLocs); - CCInfo.AnalyzeCallResult(Op.Val, RetCC_Sparc32); + RVInfo.AnalyzeCallResult(Op.Val, RetCC_Sparc32); SmallVector ResultVals; // Copy all of the result registers out of their specified physreg. From baldrick at free.fr Mon Mar 17 02:18:30 2008 From: baldrick at free.fr (Duncan Sands) Date: Mon, 17 Mar 2008 08:18:30 +0100 Subject: [llvm-commits] [llvm-gcc-4.2] r48440 - in /llvm-gcc-4.2/trunk/gcc: config/rs6000/llvm-rs6000.cpp config/rs6000/rs6000.h llvm-abi.h In-Reply-To: <200803170221.m2H2LjiZ001706@zion.cs.uiuc.edu> References: <200803170221.m2H2LjiZ001706@zion.cs.uiuc.edu> Message-ID: <200803170818.31288.baldrick@free.fr> Hi Dale, > - !aggregate_value_p(type, current_function_decl) && > - // FIXME: this is a hack around returning 'complex double' by-val > - // which returns in r3/r4/r5/r6 on PowerPC. > - TREE_INT_CST_LOW(TYPE_SIZE_UNIT(type)) <= 8) { > + !aggregate_value_p(type, current_function_decl)) { while you are there, how about removing this bogus use of current_function_decl? After all, when analyzing a call it is not the current function you want but the callee... Thanks, Duncan. From natebegeman at mac.com Mon Mar 17 02:26:14 2008 From: natebegeman at mac.com (Nate Begeman) Date: Mon, 17 Mar 2008 07:26:14 -0000 Subject: [llvm-commits] [llvm] r48450 - /llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp Message-ID: <200803170726.m2H7QEBW010181@zion.cs.uiuc.edu> Author: sampo Date: Mon Mar 17 02:26:14 2008 New Revision: 48450 URL: http://llvm.org/viewvc/llvm-project?rev=48450&view=rev Log: Add support for escaping {} in asm strings, based on patch from Nick Burns. Modified: llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp Modified: llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp?rev=48450&r1=48449&r2=48450&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp Mon Mar 17 02:26:14 2008 @@ -122,7 +122,7 @@ std::string::size_type LastEmitted = 0; while (LastEmitted != AsmString.size()) { std::string::size_type DollarPos = - AsmString.find_first_of("${|}", LastEmitted); + AsmString.find_first_of("${|}\\", LastEmitted); if (DollarPos == std::string::npos) DollarPos = AsmString.size(); // Emit a constant string fragment. @@ -132,6 +132,23 @@ AddLiteralString(std::string(AsmString.begin()+LastEmitted, AsmString.begin()+DollarPos)); LastEmitted = DollarPos; + } else if (AsmString[DollarPos] == '\\') { + if (DollarPos+1 != AsmString.size() && + (CurVariant == Variant || CurVariant == ~0U)) { + if (AsmString[DollarPos+1] == 'n') { + AddLiteralString("\\n"); + } else if (AsmString[DollarPos+1] == 't') { + AddLiteralString("\\t"); + } else if (std::string("${|}\\").find(AsmString[DollarPos+1]) + != std::string::npos) { + AddLiteralString(std::string(1, AsmString[DollarPos+1])); + } else { + throw "Non-supported escaped character found in instruction '" + + CGI.TheDef->getName() + "'!"; + } + LastEmitted = DollarPos+2; + continue; + } } else if (AsmString[DollarPos] == '{') { if (CurVariant != ~0U) throw "Nested variants found for instruction '" + From isanbard at gmail.com Mon Mar 17 02:49:24 2008 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 17 Mar 2008 07:49:24 -0000 Subject: [llvm-commits] [llvm] r48451 - /llvm/trunk/bindings/ocaml/transforms/Makefile Message-ID: <200803170749.m2H7nOGI018660@zion.cs.uiuc.edu> Author: void Date: Mon Mar 17 02:49:23 2008 New Revision: 48451 URL: http://llvm.org/viewvc/llvm-project?rev=48451&view=rev Log: Fix for "make install" of ocaml docs. Patch by Erick Tryzelaar! Modified: llvm/trunk/bindings/ocaml/transforms/Makefile Modified: llvm/trunk/bindings/ocaml/transforms/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/bindings/ocaml/transforms/Makefile?rev=48451&r1=48450&r2=48451&view=diff ============================================================================== --- llvm/trunk/bindings/ocaml/transforms/Makefile (original) +++ llvm/trunk/bindings/ocaml/transforms/Makefile Mon Mar 17 02:49:23 2008 @@ -10,4 +10,9 @@ LEVEL := ../../.. DIRS = scalar +ocamldoc: + $(Verb) for i in $(DIRS) ; do \ + $(MAKE) -C $$i ocamldoc; \ + done + include $(LEVEL)/Makefile.common From baldrick at free.fr Mon Mar 17 07:17:44 2008 From: baldrick at free.fr (Duncan Sands) Date: Mon, 17 Mar 2008 12:17:44 -0000 Subject: [llvm-commits] [llvm] r48452 - /llvm/trunk/docs/LangRef.html Message-ID: <200803171217.m2HCHi1k026557@zion.cs.uiuc.edu> Author: baldrick Date: Mon Mar 17 07:17:41 2008 New Revision: 48452 URL: http://llvm.org/viewvc/llvm-project?rev=48452&view=rev Log: Clarify the unwind attribute. Add assumption about sret made by the optimizers. Modified: llvm/trunk/docs/LangRef.html Modified: llvm/trunk/docs/LangRef.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=48452&r1=48451&r2=48452&view=diff ============================================================================== --- llvm/trunk/docs/LangRef.html (original) +++ llvm/trunk/docs/LangRef.html Mon Mar 17 07:17:41 2008 @@ -829,6 +829,7 @@
sret
This indicates that the pointer parameter specifies the address of a structure that is the return value of the function in the source program. + Loads and stores to the structure are assumed not to trap. May only be applied to the first parameter.
noalias
@@ -842,10 +843,11 @@ an unreachable instruction immediately followed the call.
nounwind
-
This function attribute indicates that the function type does not use - the unwind instruction and does not allow stack unwinding to propagate - through it.
- +
This function attribute indicates that no exceptions unwind out of the + function. Usually this is because the function makes no use of exceptions, + but it may also be that the function catches any exceptions thrown when + executing it.
+
nest
This indicates that the parameter can be excised using the trampoline intrinsics.
From dalej at apple.com Mon Mar 17 12:11:10 2008 From: dalej at apple.com (Dale Johannesen) Date: Mon, 17 Mar 2008 17:11:10 -0000 Subject: [llvm-commits] [llvm] r48459 - in /llvm/trunk/lib/Target/PowerPC: PPCCallingConv.td PPCISelLowering.cpp Message-ID: <200803171711.m2HHBATR002684@zion.cs.uiuc.edu> Author: johannes Date: Mon Mar 17 12:11:08 2008 New Revision: 48459 URL: http://llvm.org/viewvc/llvm-project?rev=48459&view=rev Log: Make Complex long long/double/long double work in ppc64 mode. Modified: llvm/trunk/lib/Target/PowerPC/PPCCallingConv.td llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Modified: llvm/trunk/lib/Target/PowerPC/PPCCallingConv.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCCallingConv.td?rev=48459&r1=48458&r2=48459&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCCallingConv.td (original) +++ llvm/trunk/lib/Target/PowerPC/PPCCallingConv.td Mon Mar 17 12:11:08 2008 @@ -23,7 +23,7 @@ // Return-value convention for PowerPC def RetCC_PPC : CallingConv<[ CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>, - CCIfType<[i64], CCAssignToReg<[X3, X4]>>, + CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6]>>, CCIfType<[f32], CCAssignToReg<[F1]>>, CCIfType<[f64], CCAssignToReg<[F1, F2]>>, Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=48459&r1=48458&r2=48459&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Mon Mar 17 12:11:08 2008 @@ -2259,7 +2259,24 @@ NodeTys.push_back(MVT::i32); break; case MVT::i64: - if (Op.Val->getValueType(1) == MVT::i64) { + if (Op.Val->getNumValues()>=4 && + Op.Val->getValueType(3) == MVT::i64) { + Chain = DAG.getCopyFromReg(Chain, PPC::X3, MVT::i64, InFlag).getValue(1); + ResultVals[0] = Chain.getValue(0); + Chain = DAG.getCopyFromReg(Chain, PPC::X4, MVT::i64, + Chain.getValue(2)).getValue(1); + ResultVals[1] = Chain.getValue(0); + Chain = DAG.getCopyFromReg(Chain, PPC::X5, MVT::i64, + Chain.getValue(2)).getValue(1); + ResultVals[2] = Chain.getValue(0); + Chain = DAG.getCopyFromReg(Chain, PPC::X6, MVT::i64, + Chain.getValue(2)).getValue(1); + ResultVals[3] = Chain.getValue(0); + NumResults = 4; + NodeTys.push_back(MVT::i64); + NodeTys.push_back(MVT::i64); + NodeTys.push_back(MVT::i64); + } else if (Op.Val->getValueType(1) == MVT::i64) { Chain = DAG.getCopyFromReg(Chain, PPC::X3, MVT::i64, InFlag).getValue(1); ResultVals[0] = Chain.getValue(0); Chain = DAG.getCopyFromReg(Chain, PPC::X4, MVT::i64, From lattner at apple.com Mon Mar 17 12:28:49 2008 From: lattner at apple.com (Tanya Lattner) Date: Mon, 17 Mar 2008 10:28:49 -0700 Subject: [llvm-commits] [llvm-gcc-4.2] r48395 - /llvm-gcc-4.2/trunk/configure.in In-Reply-To: <200803151630.m2FGUjmo010412@zion.cs.uiuc.edu> References: <200803151630.m2FGUjmo010412@zion.cs.uiuc.edu> Message-ID: Shouldn't the configure script be regenerated? -Tanya On Mar 15, 2008, at 9:30 AM, Nick Lewycky wrote: > Author: nicholas > Date: Sat Mar 15 11:30:43 2008 > New Revision: 48395 > > URL: http://llvm.org/viewvc/llvm-project?rev=48395&view=rev > Log: > Fix the makeinfo >= 4.4 test to treat 4.10 as greater than 4.4. > > Modified: > llvm-gcc-4.2/trunk/configure.in > > Modified: llvm-gcc-4.2/trunk/configure.in > URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/ > configure.in?rev=48395&r1=48394&r2=48395&view=diff > > ====================================================================== > ======== > --- llvm-gcc-4.2/trunk/configure.in (original) > +++ llvm-gcc-4.2/trunk/configure.in Sat Mar 15 11:30:43 2008 > @@ -2277,7 +2277,7 @@ > # For an installed makeinfo, we require it to be from texinfo > 4.4 or > # higher, else we use the "missing" dummy. > if ${MAKEINFO} --version \ > - | egrep 'texinfo[^0-9]*([1-3][0-9]|4\.[4-9]|[5-9])' >/dev/ > null 2>&1; then > + | egrep 'texinfo[^0-9]*([1-3][0-9]|4\.([4-9]|[1-9][0-9])| > [5-9])' >/dev/null 2>&1; then > : > else > MAKEINFO="$MISSING makeinfo" > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From dalej at apple.com Mon Mar 17 13:21:03 2008 From: dalej at apple.com (Dale Johannesen) Date: Mon, 17 Mar 2008 11:21:03 -0700 Subject: [llvm-commits] [llvm-gcc-4.2] r48440 - in /llvm-gcc-4.2/trunk/gcc: config/rs6000/llvm-rs6000.cpp config/rs6000/rs6000.h llvm-abi.h In-Reply-To: <200803170818.31288.baldrick@free.fr> References: <200803170221.m2H2LjiZ001706@zion.cs.uiuc.edu> <200803170818.31288.baldrick@free.fr> Message-ID: <3F664640-84EE-408A-95EF-46805A7E9614@apple.com> On Mar 17, 2008, at 12:18 AM, Duncan Sands wrote: > Hi Dale, > >> - !aggregate_value_p(type, current_function_decl) && >> - // FIXME: this is a hack around returning 'complex >> double' by-val >> - // which returns in r3/r4/r5/r6 on PowerPC. >> - TREE_INT_CST_LOW(TYPE_SIZE_UNIT(type)) <= 8) { >> + !aggregate_value_p(type, current_function_decl)) { > > while you are there, how about removing this bogus use of > current_function_decl? > After all, when analyzing a call it is not the current function you > want but the > callee... That's an interesting point. One of the 4 places this is called is from StartFunctionBody and current_function_decl is OK in that case. The other 3 do look wrong, but it's not obvious why this isn't causing errors if it is. I guess I'll change it and see what breaks.... From evan.cheng at apple.com Mon Mar 17 13:27:30 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 17 Mar 2008 11:27:30 -0700 Subject: [llvm-commits] [llvm] r48459 - in /llvm/trunk/lib/Target/PowerPC: PPCCallingConv.td PPCISelLowering.cpp In-Reply-To: <200803171711.m2HHBATR002684@zion.cs.uiuc.edu> References: <200803171711.m2HHBATR002684@zion.cs.uiuc.edu> Message-ID: On Mar 17, 2008, at 10:11 AM, Dale Johannesen wrote: > Author: johannes > Date: Mon Mar 17 12:11:08 2008 > New Revision: 48459 > > URL: http://llvm.org/viewvc/llvm-project?rev=48459&view=rev > Log: > Make Complex long long/double/long double work > in ppc64 mode. > > > Modified: > llvm/trunk/lib/Target/PowerPC/PPCCallingConv.td > llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp > > Modified: llvm/trunk/lib/Target/PowerPC/PPCCallingConv.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCCallingConv.td?rev=48459&r1=48458&r2=48459&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/PowerPC/PPCCallingConv.td (original) > +++ llvm/trunk/lib/Target/PowerPC/PPCCallingConv.td Mon Mar 17 > 12:11:08 2008 > @@ -23,7 +23,7 @@ > // Return-value convention for PowerPC > def RetCC_PPC : CallingConv<[ > CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>, > - CCIfType<[i64], CCAssignToReg<[X3, X4]>>, > + CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6]>>, > > CCIfType<[f32], CCAssignToReg<[F1]>>, > CCIfType<[f64], CCAssignToReg<[F1, F2]>>, > > Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=48459&r1=48458&r2=48459&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original) > +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Mon Mar 17 > 12:11:08 2008 > @@ -2259,7 +2259,24 @@ > NodeTys.push_back(MVT::i32); > break; > case MVT::i64: > - if (Op.Val->getValueType(1) == MVT::i64) { > + if (Op.Val->getNumValues()>=4 && > + Op.Val->getValueType(3) == MVT::i64) { The part of call can really use some refactoring. Look at the case of MVT::i32, it can be significantly simplified into something like: unsigned NumValues = Op.Val->getNumValues(); if (Op.Val->getValueType(NumValues-1) == MVT::i32) for (unsigned i = 0; i != NumValues; ++i) { Chain = DAG.getCopyFromReg(Chain, CallRegs[i], MVT::i32, InFlag).getValue(1); InFlag = Chain.getValue(2); ResultVals.push_back(Chain.getValue(0)); NodeTys.push_back(MVT::i32); } BTW, why is it we are using tablegen generated CC code to handle arguments, but not return types (same issue on x86)? I've forgotten the history behind the tablegen CC development. Evan > > + Chain = DAG.getCopyFromReg(Chain, PPC::X3, MVT::i64, > InFlag).getValue(1); > + ResultVals[0] = Chain.getValue(0); > + Chain = DAG.getCopyFromReg(Chain, PPC::X4, MVT::i64, > + Chain.getValue(2)).getValue(1); > + ResultVals[1] = Chain.getValue(0); > + Chain = DAG.getCopyFromReg(Chain, PPC::X5, MVT::i64, > + Chain.getValue(2)).getValue(1); > + ResultVals[2] = Chain.getValue(0); > + Chain = DAG.getCopyFromReg(Chain, PPC::X6, MVT::i64, > + Chain.getValue(2)).getValue(1); > + ResultVals[3] = Chain.getValue(0); > + NumResults = 4; > + NodeTys.push_back(MVT::i64); > + NodeTys.push_back(MVT::i64); > + NodeTys.push_back(MVT::i64); > + } else if (Op.Val->getValueType(1) == MVT::i64) { > Chain = DAG.getCopyFromReg(Chain, PPC::X3, MVT::i64, > InFlag).getValue(1); > ResultVals[0] = Chain.getValue(0); > Chain = DAG.getCopyFromReg(Chain, PPC::X4, MVT::i64, > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From evan.cheng at apple.com Mon Mar 17 13:33:13 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 17 Mar 2008 11:33:13 -0700 Subject: [llvm-commits] [llvm] r48356 - /llvm/trunk/lib/Target/X86/README.txt In-Reply-To: References: <200803140600.m2E60KQ1017055@zion.cs.uiuc.edu> <25C013AF-33B1-490B-9024-E4158E8DF905@apple.com> Message-ID: For the sake of argument: ARM: _test: mov r3, r0, lsr #16 sxtb r0, r3 bx lr _test2: mov r3, r0, lsl #8 mov r0, r3, asr #24 bx lr PPC32: _test: srwi r2, r3, 16 extsb r3, r2 blr _test2: slwi r2, r3, 8 srawi r3, r2, 24 blr Don't diss x86! :-) Evan On Mar 14, 2008, at 10:34 AM, Chris Lattner wrote: > On Mar 14, 2008, at 10:15 AM, Evan Cheng wrote: >> This seems like a target independent dag combiner xform? > > Turning the first into the second is target independent, and should > actually be done in instcombine. The problem is that the second one > generates worse code from the x86 backend than the first one. > > On PPC and ARM, they generate equally good code (on ARM they both > compile to identical instructions even) so consider this to be "X86 > generates inefficient code for: > > define i32 @test2(i32 %f12) { > %f11 = shl i32 %f12, 8 > %tmp7.25 = ashr i32 %f11, 24 > ret i32 %tmp7.25 > }" > > :) > > -Chris > > >> On Mar 13, 2008, at 11:00 PM, Chris Lattner wrote: >> >>> >>> >>> +These two functions perform identical operations: >>> + >>> +define i32 @test(i32 %f12) { >>> + %tmp7.25 = lshr i32 %f12, 16 >>> + %tmp7.26 = trunc i32 %tmp7.25 to i8 >>> + %tmp78.2 = sext i8 %tmp7.26 to i32 >>> + ret i32 %tmp78.2 >>> +} >>> + >>> +define i32 @test2(i32 %f12) { >>> + %f11 = shl i32 %f12, 8 >>> + %tmp7.25 = ashr i32 %f11, 24 >>> + ret i32 %tmp7.25 >>> +} >>> + >>> +but the first compiles into significantly better code on x86-32: >>> + >>> +_test: >>> + movsbl 6(%esp), %eax >>> + ret >>> +_test2: >>> + movl 4(%esp), %eax >>> + shll $8, %eax >>> + sarl $24, %eax >>> + ret >>> + >>> +and on x86-64: >>> + >>> +_test: >>> + shrl $16, %edi >>> + movsbl %dil, %eax >>> + ret >>> +_test2: >>> + shll $8, %edi >>> + movl %edi, %eax >>> + sarl $24, %eax >>> + ret >>> + >>> +I would like instcombine to canonicalize the first into the second >>> (since it is >>> +shorter and doesn't involve type width changes) but the x86 backend >>> needs to do >>> +the right thing with the later sequence first. >>> + >>> +// >>> = >>> = >>> = >>> --------------------------------------------------------------------- >>> ===// >>> >>> >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From dalej at apple.com Mon Mar 17 13:43:50 2008 From: dalej at apple.com (Dale Johannesen) Date: Mon, 17 Mar 2008 11:43:50 -0700 Subject: [llvm-commits] [llvm] r48459 - in /llvm/trunk/lib/Target/PowerPC: PPCCallingConv.td PPCISelLowering.cpp In-Reply-To: References: <200803171711.m2HHBATR002684@zion.cs.uiuc.edu> Message-ID: On Mar 17, 2008, at 11:27 AM, Evan Cheng wrote: > The part of call can really use some refactoring. Look at the case of > MVT::i32, it can be significantly simplified into something like: > unsigned NumValues = Op.Val->getNumValues(); > if (Op.Val->getValueType(NumValues-1) == MVT::i32) > for (unsigned i = 0; i != NumValues; ++i) { > Chain = DAG.getCopyFromReg(Chain, CallRegs[i], MVT::i32, > InFlag).getValue(1); > InFlag = Chain.getValue(2); > ResultVals.push_back(Chain.getValue(0)); > NodeTys.push_back(MVT::i32); > } I had it like that and decided I prefer this. Generally I'd rather list the cases that are supposed to work explicitly rather than have something more general and trust we won't get handed cases that aren't supposed to happen. Shorter is not always better. > BTW, why is it we are using tablegen generated CC code to handle > arguments, but not return types (same issue on x86)? I've forgotten > the history behind the tablegen CC development. That is the way I found it. According to Chris, the PPC BE preceded tablegen. Return values, at least for ppc32, can be handled easily by the existing tablegen stuff. Parameters would need some extensions, e.g. same value in both regs and memory, structs passed part in regs and part in memory. From evan.cheng at apple.com Mon Mar 17 13:44:12 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 17 Mar 2008 11:44:12 -0700 Subject: [llvm-commits] [llvm] r48356 - /llvm/trunk/lib/Target/X86/README.txt In-Reply-To: <181F3478-DE13-456D-9EC5-C28D6C89ABD8@apple.com> References: <200803140600.m2E60KQ1017055@zion.cs.uiuc.edu> <25C013AF-33B1-490B-9024-E4158E8DF905@apple.com> <8E8D2116-9D12-40C4-9B08-465671CEED17@gmail.com> <181F3478-DE13-456D-9EC5-C28D6C89ABD8@apple.com> Message-ID: <2BF0DC46-7FD0-4A28-B121-ECF6BCF492E4@apple.com> On Mar 16, 2008, at 7:24 PM, Chris Lattner wrote: > > On Mar 15, 2008, at 2:01 PM, Christopher Lamb wrote: > >> Here's a proposed solution. It seems to work OK for me. It'll be >> even better when the undef and insert_subreg coalescing support gets >> done. > > Thanks for tackling this! Could this be done as a target independent > dag combine by selecting to "sext_in_reg(shrl)" when sext_in_reg is > available (or before legalize)? This avoids the apparent size changes > of the register. On PPC, for example, this would codegen to: I am not sure about utilizing sext_in_reg, is that correct? However, this can definitely be target independent. There is a TLI.isTruncateFree() that you can check to ensure using truncate is profitable. + if (CN->getValue() == ValueSize - 8) { + TruncVT = MVT::i8; + } else if (CN->getValue() == ValueSize - 16) { + TruncVT = MVT::i16; + } else if (CN->getValue() == ValueSize - 32) { + TruncVT = MVT::i32; + } + + if (TruncVT != MVT::isVoid) { Please just use early exit: } else { return SDOperand(); } It's just a matter of style, but checking TruncVT is not MVT::isVoid seems weird to me. Thanks! Evan > > > _test: > srwi r2, r3, 16 > extsb r3, r2 > blr > > instead of: > > _test2: > slwi r2, r3, 8 > srawi r3, r2, 24 > blr > > On X86, this is a win because sextinreg (aka movsbl and friends) are > 3- > address, but sar is 2-address, giving: > > _test: > shrl $16, %edi > movsbl %dil, %eax > ret > > instead of: > > _test2: > shll $8, %edi > movl %edi, %eax > sarl $24, %eax > ret > > What do you think? > > -Chris > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From dalej at apple.com Mon Mar 17 14:43:04 2008 From: dalej at apple.com (Dale Johannesen) Date: Mon, 17 Mar 2008 19:43:04 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r48463 - /llvm-gcc-4.2/trunk/gcc/llvm-abi.h Message-ID: <200803171943.m2HJh5fs007179@zion.cs.uiuc.edu> Author: johannes Date: Mon Mar 17 14:43:04 2008 New Revision: 48463 URL: http://llvm.org/viewvc/llvm-project?rev=48463&view=rev Log: Allow for case where a field has no size although the containing struct does (not what you might expect). struct { int a; int x[]; } Fixes gcc.c-torture/compile/pr16566-2.c on ppc32. Modified: llvm-gcc-4.2/trunk/gcc/llvm-abi.h Modified: llvm-gcc-4.2/trunk/gcc/llvm-abi.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-abi.h?rev=48463&r1=48462&r2=48463&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-abi.h (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-abi.h Mon Mar 17 14:43:04 2008 @@ -111,7 +111,8 @@ for (tree Field = TYPE_FIELDS(type); Field; Field = TREE_CHAIN(Field)) if (TREE_CODE(Field) == FIELD_DECL) { if (ignoreZeroLength) { - if (TREE_CODE(DECL_SIZE(Field)) == INTEGER_CST && + if (DECL_SIZE(Field) && + TREE_CODE(DECL_SIZE(Field)) == INTEGER_CST && TREE_INT_CST_LOW(DECL_SIZE(Field)) == 0) continue; } From isanbard at gmail.com Mon Mar 17 15:57:54 2008 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 17 Mar 2008 20:57:54 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r48464 - /llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h Message-ID: <200803172057.m2HKvsvS009397@zion.cs.uiuc.edu> Author: void Date: Mon Mar 17 15:57:53 2008 New Revision: 48464 URL: http://llvm.org/viewvc/llvm-project?rev=48464&view=rev Log: Remove C++-style comment. Modified: llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h Modified: llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h?rev=48464&r1=48463&r2=48464&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h (original) +++ llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h Mon Mar 17 15:57:53 2008 @@ -3482,7 +3482,7 @@ extern bool llvm_rs6000_should_pass_aggregate_in_mixed_regs(tree, const Type*, std::vector&); -// FIXME this is needed for 64-bit +/* FIXME this is needed for 64-bit */ #define LLVM_SHOULD_PASS_AGGREGATE_IN_MIXED_REGS(T, TY, E) \ llvm_rs6000_should_pass_aggregate_in_mixed_regs((T), (TY), (E)) From dalej at apple.com Mon Mar 17 17:22:06 2008 From: dalej at apple.com (Dale Johannesen) Date: Mon, 17 Mar 2008 22:22:06 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r48471 - in /llvm-gcc-4.2/trunk/gcc/config/rs6000: llvm-rs6000.cpp rs6000.h Message-ID: <200803172222.m2HMM6PU012362@zion.cs.uiuc.edu> Author: johannes Date: Mon Mar 17 17:22:06 2008 New Revision: 48471 URL: http://llvm.org/viewvc/llvm-project?rev=48471&view=rev Log: ppc32 structs containing a single generic vector are passed using the sret mechanism. Modified: llvm-gcc-4.2/trunk/gcc/config/rs6000/llvm-rs6000.cpp llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h Modified: llvm-gcc-4.2/trunk/gcc/config/rs6000/llvm-rs6000.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/rs6000/llvm-rs6000.cpp?rev=48471&r1=48470&r2=48471&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/rs6000/llvm-rs6000.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/config/rs6000/llvm-rs6000.cpp Mon Mar 17 17:22:06 2008 @@ -405,7 +405,8 @@ // Note this does not apply to long double. // This is required for ABI correctness. tree tType = isSingleElementStructOrArray(TreeType, true, false); - if (tType && int_size_in_bytes(tType)==Bytes && TYPE_MODE(tType)!=TFmode) + if (tType && int_size_in_bytes(tType)==Bytes && TYPE_MODE(tType)!=TFmode && + (TREE_CODE(tType)!=VECTOR_TYPE || Bytes==16)) return false; return true; @@ -430,14 +431,15 @@ const StructType *STy = dyn_cast(Ty); if (!STy || STy->isPacked()) return false; - // A struct containing only a float, double or vector field, possibly with + // A struct containing only a float, double or Altivec field, possibly with // some zero-length fields as well, must be passed as the field type. - // Note this does not apply to long double. + // Note this does not apply to long double, nor generic vectors. // Other single-element structs may be passed this way as well, but // only if the type size matches the element's type size (structs that // violate this can be created with __aligned__). tree tType = isSingleElementStructOrArray(TreeType, true, false); - if (tType && int_size_in_bytes(tType)==SrcSize && TYPE_MODE(tType)!=TFmode) { + if (tType && int_size_in_bytes(tType)==SrcSize && TYPE_MODE(tType)!=TFmode && + (TREE_CODE(tType)!=VECTOR_TYPE || SrcSize==16)) { Elts.push_back(ConvertType(tType)); return true; } Modified: llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h?rev=48471&r1=48470&r2=48471&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h (original) +++ llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h Mon Mar 17 17:22:06 2008 @@ -3486,6 +3486,16 @@ #define LLVM_SHOULD_PASS_AGGREGATE_IN_MIXED_REGS(T, TY, E) \ llvm_rs6000_should_pass_aggregate_in_mixed_regs((T), (TY), (E)) +// Non-altivec vectors bigger than 4 bytes are returned by sret. +#define LLVM_SHOULD_RETURN_VECTOR_AS_SHADOW(X,isBuiltin)\ + ((!TARGET_64BIT && \ + TREE_CODE(X) == VECTOR_TYPE && \ + TYPE_SIZE(X) && \ + TREE_CODE(TYPE_SIZE(X))==INTEGER_CST && \ + TREE_INT_CST_LOW(TYPE_SIZE(X))>32 && \ + TREE_INT_CST_LOW(TYPE_SIZE(X))!=128) \ + ? true : false) + #endif /* LLVM_ABI_H */ /* LLVM LOCAL end */ From isanbard at gmail.com Mon Mar 17 17:29:01 2008 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 17 Mar 2008 15:29:01 -0700 Subject: [llvm-commits] [llvm-gcc-4.2] r48471 - in /llvm-gcc-4.2/trunk/gcc/config/rs6000: llvm-rs6000.cpp rs6000.h In-Reply-To: <200803172222.m2HMM6PU012362@zion.cs.uiuc.edu> References: <200803172222.m2HMM6PU012362@zion.cs.uiuc.edu> Message-ID: <16e5fdf90803171529y45a77e59u793a6421aab1507@mail.gmail.com> Hi Dale, ============================================================================== > --- llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h (original) > +++ llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h Mon Mar 17 17:22:06 2008 > @@ -3486,6 +3486,16 @@ > #define LLVM_SHOULD_PASS_AGGREGATE_IN_MIXED_REGS(T, TY, E) \ > llvm_rs6000_should_pass_aggregate_in_mixed_regs((T), (TY), (E)) > > +// Non-altivec vectors bigger than 4 bytes are returned by sret. Watch out for C++-style comments in GCC header files. They're #included into non-C++ files which cause warnings which turn into errors when we build the Apple Way(tm). -bw > +#define LLVM_SHOULD_RETURN_VECTOR_AS_SHADOW(X,isBuiltin)\ > + ((!TARGET_64BIT && \ > + TREE_CODE(X) == VECTOR_TYPE && \ > + TYPE_SIZE(X) && \ > + TREE_CODE(TYPE_SIZE(X))==INTEGER_CST && \ > + TREE_INT_CST_LOW(TYPE_SIZE(X))>32 && \ > + TREE_INT_CST_LOW(TYPE_SIZE(X))!=128) \ > + ? true : false) > + > #endif /* LLVM_ABI_H */ > > /* LLVM LOCAL end */ From dalej at apple.com Mon Mar 17 17:47:52 2008 From: dalej at apple.com (Dale Johannesen) Date: Mon, 17 Mar 2008 22:47:52 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r48472 - /llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h Message-ID: <200803172247.m2HMlq7r013218@zion.cs.uiuc.edu> Author: johannes Date: Mon Mar 17 17:47:52 2008 New Revision: 48472 URL: http://llvm.org/viewvc/llvm-project?rev=48472&view=rev Log: remove C++ style comment. Modified: llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h Modified: llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h?rev=48472&r1=48471&r2=48472&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h (original) +++ llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h Mon Mar 17 17:47:52 2008 @@ -3486,7 +3486,7 @@ #define LLVM_SHOULD_PASS_AGGREGATE_IN_MIXED_REGS(T, TY, E) \ llvm_rs6000_should_pass_aggregate_in_mixed_regs((T), (TY), (E)) -// Non-altivec vectors bigger than 4 bytes are returned by sret. +/* Non-altivec vectors bigger than 4 bytes are returned by sret. */ #define LLVM_SHOULD_RETURN_VECTOR_AS_SHADOW(X,isBuiltin)\ ((!TARGET_64BIT && \ TREE_CODE(X) == VECTOR_TYPE && \ From dalej at apple.com Mon Mar 17 17:49:38 2008 From: dalej at apple.com (Dale Johannesen) Date: Mon, 17 Mar 2008 15:49:38 -0700 Subject: [llvm-commits] [llvm-gcc-4.2] r48471 - in /llvm-gcc-4.2/trunk/gcc/config/rs6000: llvm-rs6000.cpp rs6000.h In-Reply-To: <16e5fdf90803171529y45a77e59u793a6421aab1507@mail.gmail.com> References: <200803172222.m2HMM6PU012362@zion.cs.uiuc.edu> <16e5fdf90803171529y45a77e59u793a6421aab1507@mail.gmail.com> Message-ID: On Mar 17, 2008, at 3:29 PM, Bill Wendling wrote: > Hi Dale, > > = > = > = > = > = > = > = > = > ====================================================================== >> --- llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h (original) >> +++ llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h Mon Mar 17 >> 17:22:06 2008 >> @@ -3486,6 +3486,16 @@ >> #define LLVM_SHOULD_PASS_AGGREGATE_IN_MIXED_REGS(T, TY, E) \ >> llvm_rs6000_should_pass_aggregate_in_mixed_regs((T), (TY), (E)) >> >> +// Non-altivec vectors bigger than 4 bytes are returned by sret. > > Watch out for C++-style comments in GCC header files. They're > #included into non-C++ files which cause warnings which turn into > errors when we build the Apple Way(tm). Sorry, I did know that. But it occurs to me to wonder why this is a problem. Both gcc and Apple supported C++ style comments in C as far back as the early 90s, and there is really no reason not to accept them. Do we build with -pedantic or something? From isanbard at gmail.com Mon Mar 17 17:55:49 2008 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 17 Mar 2008 15:55:49 -0700 Subject: [llvm-commits] [llvm-gcc-4.2] r48471 - in /llvm-gcc-4.2/trunk/gcc/config/rs6000: llvm-rs6000.cpp rs6000.h In-Reply-To: References: <200803172222.m2HMM6PU012362@zion.cs.uiuc.edu> <16e5fdf90803171529y45a77e59u793a6421aab1507@mail.gmail.com> Message-ID: <16e5fdf90803171555o39e58396t5003f645f6bc5560@mail.gmail.com> On Mon, Mar 17, 2008 at 3:49 PM, Dale Johannesen wrote: > > > Watch out for C++-style comments in GCC header files. They're > > #included into non-C++ files which cause warnings which turn into > > errors when we build the Apple Way(tm). > > Sorry, I did know that. But it occurs to me to wonder why this is a > problem. Both gcc and Apple supported C++ style comments in C as far > back as the early 90s, and there is really no reason not to accept > them. Do we build with -pedantic or something? > Yes, it uses -pedantic and -Werror (among others). It would probably take adding a -std=c99 (or whatever) flag, I'm assuming. Though I don't know what (if anything) that will do to our builds, re code quality and such. -bw From isanbard at gmail.com Mon Mar 17 17:56:11 2008 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 17 Mar 2008 15:56:11 -0700 Subject: [llvm-commits] [llvm-gcc-4.2] r48472 - /llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h In-Reply-To: <200803172247.m2HMlq7r013218@zion.cs.uiuc.edu> References: <200803172247.m2HMlq7r013218@zion.cs.uiuc.edu> Message-ID: <16e5fdf90803171556t126ab9bfg4cb0ffc9382eddba@mail.gmail.com> Thanks! :-) -bw On Mon, Mar 17, 2008 at 3:47 PM, Dale Johannesen wrote: > Author: johannes > Date: Mon Mar 17 17:47:52 2008 > New Revision: 48472 > > URL: http://llvm.org/viewvc/llvm-project?rev=48472&view=rev > Log: > remove C++ style comment. > > > Modified: > llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h > > Modified: llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h > URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h?rev=48472&r1=48471&r2=48472&view=diff > > ============================================================================== > --- llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h (original) > +++ llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h Mon Mar 17 17:47:52 2008 > @@ -3486,7 +3486,7 @@ > #define LLVM_SHOULD_PASS_AGGREGATE_IN_MIXED_REGS(T, TY, E) \ > llvm_rs6000_should_pass_aggregate_in_mixed_regs((T), (TY), (E)) > > -// Non-altivec vectors bigger than 4 bytes are returned by sret. > +/* Non-altivec vectors bigger than 4 bytes are returned by sret. */ > #define LLVM_SHOULD_RETURN_VECTOR_AS_SHADOW(X,isBuiltin)\ > ((!TARGET_64BIT && \ > TREE_CODE(X) == VECTOR_TYPE && \ > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From gohman at apple.com Mon Mar 17 18:06:43 2008 From: gohman at apple.com (Dan Gohman) Date: Mon, 17 Mar 2008 23:06:43 -0000 Subject: [llvm-commits] [test-suite] r48473 - /test-suite/trunk/LLVMSource/Makefile Message-ID: <200803172306.m2HN6hOU013749@zion.cs.uiuc.edu> Author: djg Date: Mon Mar 17 18:06:43 2008 New Revision: 48473 URL: http://llvm.org/viewvc/llvm-project?rev=48473&view=rev Log: Fix LLVMSource Makefile's LEVEL. Modified: test-suite/trunk/LLVMSource/Makefile Modified: test-suite/trunk/LLVMSource/Makefile URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/LLVMSource/Makefile?rev=48473&r1=48472&r2=48473&view=diff ============================================================================== --- test-suite/trunk/LLVMSource/Makefile (original) +++ test-suite/trunk/LLVMSource/Makefile Mon Mar 17 18:06:43 2008 @@ -3,7 +3,7 @@ # This directory contains regression tests for LLVM backends written in LLVM # assembly language. # -LEVEL = ../../.. +LEVEL = .. DISABLE_FOR_LLVM_PROGRAMS := 1 PROGRAM_REQUIRED_TO_EXIT_OK := 1 REQUIRES_EH_SUPPORT := 1 From dpatel at apple.com Mon Mar 17 18:41:21 2008 From: dpatel at apple.com (Devang Patel) Date: Mon, 17 Mar 2008 23:41:21 -0000 Subject: [llvm-commits] [llvm] r48474 - /llvm/trunk/lib/Transforms/Scalar/LoopUnroll.cpp Message-ID: <200803172341.m2HNfLGv014986@zion.cs.uiuc.edu> Author: dpatel Date: Mon Mar 17 18:41:20 2008 New Revision: 48474 URL: http://llvm.org/viewvc/llvm-project?rev=48474&view=rev Log: Update heuritics that estimates cost of call instructions. Modified: llvm/trunk/lib/Transforms/Scalar/LoopUnroll.cpp Modified: llvm/trunk/lib/Transforms/Scalar/LoopUnroll.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopUnroll.cpp?rev=48474&r1=48473&r2=48474&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopUnroll.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopUnroll.cpp Mon Mar 17 18:41:20 2008 @@ -100,6 +100,11 @@ // Ignore instructions only used by the loop terminator. } else if (isa(I)) { // Ignore debug instructions + } else if (isa(I)) { + if (isa(I)) + Size = Size + 3; + else + Size = Size + 10; } else { ++Size; } From dalej at apple.com Mon Mar 17 19:20:54 2008 From: dalej at apple.com (Dale Johannesen) Date: Tue, 18 Mar 2008 00:20:54 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r48475 - /llvm-gcc-4.2/trunk/gcc/llvm-abi.h Message-ID: <200803180020.m2I0Ksrq015998@zion.cs.uiuc.edu> Author: johannes Date: Mon Mar 17 19:20:53 2008 New Revision: 48475 URL: http://llvm.org/viewvc/llvm-project?rev=48475&view=rev Log: Revert passing of large _Complex objects as int on x86-64. The code generated for these is incompatible with gcc, i.e. wrong, but at least it doesn't crash. Modified: llvm-gcc-4.2/trunk/gcc/llvm-abi.h Modified: llvm-gcc-4.2/trunk/gcc/llvm-abi.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-abi.h?rev=48475&r1=48474&r2=48475&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-abi.h (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-abi.h Mon Mar 17 19:20:53 2008 @@ -244,7 +244,13 @@ // Return scalar values normally. C.HandleScalarResult(Ty); } else if (TYPE_SIZE(type) && TREE_CODE(TYPE_SIZE(type)) == INTEGER_CST && - !aggregate_value_p(type, current_function_decl)) { + !aggregate_value_p(type, current_function_decl) +#if defined(TARGET_386) && defined(TARGET_64BIT) + // FIXME without this, _Complex long double crashes. With it, we + // just produce incorrect code. + && TREE_INT_CST_LOW(TYPE_SIZE_UNIT(type))<=8 +#endif + ) { tree SingleElt = LLVM_SHOULD_RETURN_STRUCT_AS_SCALAR(type); if (SingleElt && TYPE_SIZE(SingleElt) && TREE_CODE(TYPE_SIZE(SingleElt)) == INTEGER_CST && From dpatel at apple.com Mon Mar 17 19:39:19 2008 From: dpatel at apple.com (Devang Patel) Date: Tue, 18 Mar 2008 00:39:19 -0000 Subject: [llvm-commits] [llvm] r48476 - in /llvm/trunk: include/llvm/ include/llvm/Analysis/ lib/Analysis/ lib/Analysis/IPA/ lib/VMCore/ Message-ID: <200803180039.m2I0dK0g016477@zion.cs.uiuc.edu> Author: dpatel Date: Mon Mar 17 19:39:19 2008 New Revision: 48476 URL: http://llvm.org/viewvc/llvm-project?rev=48476&view=rev Log: Identify Analysis pass. Do not run analysis pass again if analysis info is still available. This fixes PR1441. Modified: llvm/trunk/include/llvm/Analysis/Dominators.h llvm/trunk/include/llvm/Analysis/FindUsedTypes.h llvm/trunk/include/llvm/Analysis/IntervalPartition.h llvm/trunk/include/llvm/Analysis/LoopInfo.h llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h llvm/trunk/include/llvm/Analysis/PostDominators.h llvm/trunk/include/llvm/Analysis/ScalarEvolution.h llvm/trunk/include/llvm/Pass.h llvm/trunk/lib/Analysis/AliasAnalysisCounter.cpp llvm/trunk/lib/Analysis/AliasAnalysisEvaluator.cpp llvm/trunk/lib/Analysis/AliasDebugger.cpp llvm/trunk/lib/Analysis/AliasSetTracker.cpp llvm/trunk/lib/Analysis/CFGPrinter.cpp llvm/trunk/lib/Analysis/IPA/Andersens.cpp llvm/trunk/lib/Analysis/IPA/GlobalsModRef.cpp llvm/trunk/lib/Analysis/InstCount.cpp llvm/trunk/lib/Analysis/LoadValueNumbering.cpp llvm/trunk/lib/Analysis/ProfileInfoLoaderPass.cpp llvm/trunk/lib/VMCore/PassManager.cpp Modified: llvm/trunk/include/llvm/Analysis/Dominators.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/Dominators.h?rev=48476&r1=48475&r2=48476&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/Dominators.h (original) +++ llvm/trunk/include/llvm/Analysis/Dominators.h Mon Mar 17 19:39:19 2008 @@ -300,6 +300,9 @@ // FIXME: Should remove this virtual bool runOnFunction(Function &F) { return false; } + /// isAnalysis - Return true if this pass is implementing an analysis pass. + virtual bool isAnalysis() const { return true; } + virtual void releaseMemory() { reset(); } /// getNode - return the (Post)DominatorTree node for the specified basic @@ -691,6 +694,9 @@ return DT->getRootNode(); } + /// isAnalysis - Return true if this pass is implementing an analysis pass. + virtual bool isAnalysis() const { return true; } + virtual bool runOnFunction(Function &F); virtual void getAnalysisUsage(AnalysisUsage &AU) const { @@ -910,6 +916,9 @@ return Roots[0]; } + /// isAnalysis - Return true if this pass is implementing an analysis pass. + virtual bool isAnalysis() const { return true; } + virtual bool runOnFunction(Function &) { Frontiers.clear(); DominatorTree &DT = getAnalysis(); Modified: llvm/trunk/include/llvm/Analysis/FindUsedTypes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/FindUsedTypes.h?rev=48476&r1=48475&r2=48476&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/FindUsedTypes.h (original) +++ llvm/trunk/include/llvm/Analysis/FindUsedTypes.h Mon Mar 17 19:39:19 2008 @@ -50,6 +50,10 @@ void IncorporateValue(const Value *V); public: + + /// isAnalysis - Return true if this pass is implementing an analysis pass. + virtual bool isAnalysis() const { return true; } + /// run - This incorporates all types used by the specified module bool runOnModule(Module &M); Modified: llvm/trunk/include/llvm/Analysis/IntervalPartition.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/IntervalPartition.h?rev=48476&r1=48475&r2=48476&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/IntervalPartition.h (original) +++ llvm/trunk/include/llvm/Analysis/IntervalPartition.h Mon Mar 17 19:39:19 2008 @@ -49,6 +49,9 @@ IntervalPartition() : FunctionPass((intptr_t)&ID), RootInterval(0) {} + /// isAnalysis - Return true if this pass is implementing an analysis pass. + virtual bool isAnalysis() const { return true; } + // run - Calculate the interval partition for this function virtual bool runOnFunction(Function &F); Modified: llvm/trunk/include/llvm/Analysis/LoopInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/LoopInfo.h?rev=48476&r1=48475&r2=48476&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/LoopInfo.h (original) +++ llvm/trunk/include/llvm/Analysis/LoopInfo.h Mon Mar 17 19:39:19 2008 @@ -580,6 +580,9 @@ LoopInfoBase() { } ~LoopInfoBase() { releaseMemory(); } + /// isAnalysis - Return true if this pass is implementing an analysis pass. + virtual bool isAnalysis() const { return true; } + void releaseMemory() { for (typename std::vector* >::iterator I = TopLevelLoops.begin(), E = TopLevelLoops.end(); I != E; ++I) Modified: llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h?rev=48476&r1=48475&r2=48476&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h (original) +++ llvm/trunk/include/llvm/Analysis/MemoryDependenceAnalysis.h Mon Mar 17 19:39:19 2008 @@ -68,6 +68,9 @@ static char ID; // Class identification, replacement for typeinfo MemoryDependenceAnalysis() : FunctionPass((intptr_t)&ID) {} + /// isAnalysis - Return true if this pass is implementing an analysis pass. + virtual bool isAnalysis() const { return true; } + /// Pass Implementation stuff. This doesn't do any analysis. /// bool runOnFunction(Function &) {return false; } Modified: llvm/trunk/include/llvm/Analysis/PostDominators.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/PostDominators.h?rev=48476&r1=48475&r2=48476&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/PostDominators.h (original) +++ llvm/trunk/include/llvm/Analysis/PostDominators.h Mon Mar 17 19:39:19 2008 @@ -29,6 +29,9 @@ DT = new DominatorTreeBase(true); } + /// isAnalysis - Return true if this pass is implementing an analysis pass. + virtual bool isAnalysis() const { return true; } + virtual bool runOnFunction(Function &F); virtual void getAnalysisUsage(AnalysisUsage &AU) const { @@ -69,6 +72,9 @@ PostDominanceFrontier() : DominanceFrontierBase((intptr_t) &ID, true) {} + /// isAnalysis - Return true if this pass is implementing an analysis pass. + virtual bool isAnalysis() const { return true; } + virtual bool runOnFunction(Function &) { Frontiers.clear(); PostDominatorTree &DT = getAnalysis(); Modified: llvm/trunk/include/llvm/Analysis/ScalarEvolution.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/ScalarEvolution.h?rev=48476&r1=48475&r2=48476&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/ScalarEvolution.h (original) +++ llvm/trunk/include/llvm/Analysis/ScalarEvolution.h Mon Mar 17 19:39:19 2008 @@ -291,6 +291,9 @@ /// that no dangling references are left around. void deleteValueFromRecords(Value *V) const; + /// isAnalysis - Return true if this pass is implementing an analysis pass. + virtual bool isAnalysis() const { return true; } + virtual bool runOnFunction(Function &F); virtual void releaseMemory(); virtual void getAnalysisUsage(AnalysisUsage &AU) const; Modified: llvm/trunk/include/llvm/Pass.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Pass.h?rev=48476&r1=48475&r2=48476&view=diff ============================================================================== --- llvm/trunk/include/llvm/Pass.h (original) +++ llvm/trunk/include/llvm/Pass.h Mon Mar 17 19:39:19 2008 @@ -130,6 +130,11 @@ return Resolver; } + /// isAnalysis - Return true if this pass is implementing an analysis pass. + virtual bool isAnalysis() const { + return false; + } + /// getAnalysisUsage - This function should be overriden by passes that need /// analysis information to do their job. If a pass specifies that it uses a /// particular analysis result to this function, it can then use the Modified: llvm/trunk/lib/Analysis/AliasAnalysisCounter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/AliasAnalysisCounter.cpp?rev=48476&r1=48475&r2=48476&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/AliasAnalysisCounter.cpp (original) +++ llvm/trunk/lib/Analysis/AliasAnalysisCounter.cpp Mon Mar 17 19:39:19 2008 @@ -72,6 +72,9 @@ } } + /// isAnalysis - Return true if this pass is implementing an analysis pass. + virtual bool isAnalysis() const { return true; } + bool runOnModule(Module &M) { this->M = &M; InitializeAliasAnalysis(this); Modified: llvm/trunk/lib/Analysis/AliasAnalysisEvaluator.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/AliasAnalysisEvaluator.cpp?rev=48476&r1=48475&r2=48476&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/AliasAnalysisEvaluator.cpp (original) +++ llvm/trunk/lib/Analysis/AliasAnalysisEvaluator.cpp Mon Mar 17 19:39:19 2008 @@ -70,6 +70,9 @@ return false; } + /// isAnalysis - Return true if this pass is implementing an analysis pass. + virtual bool isAnalysis() const { return true; } + bool runOnFunction(Function &F); bool doFinalization(Module &M); }; Modified: llvm/trunk/lib/Analysis/AliasDebugger.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/AliasDebugger.cpp?rev=48476&r1=48475&r2=48476&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/AliasDebugger.cpp (original) +++ llvm/trunk/lib/Analysis/AliasDebugger.cpp Mon Mar 17 19:39:19 2008 @@ -43,6 +43,9 @@ static char ID; // Class identification, replacement for typeinfo AliasDebugger() : ModulePass((intptr_t)&ID) {} + /// isAnalysis - Return true if this pass is implementing an analysis pass. + virtual bool isAnalysis() const { return true; } + bool runOnModule(Module &M) { InitializeAliasAnalysis(this); // set up super class Modified: llvm/trunk/lib/Analysis/AliasSetTracker.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/AliasSetTracker.cpp?rev=48476&r1=48475&r2=48476&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/AliasSetTracker.cpp (original) +++ llvm/trunk/lib/Analysis/AliasSetTracker.cpp Mon Mar 17 19:39:19 2008 @@ -558,6 +558,9 @@ AU.addRequired(); } + /// isAnalysis - Return true if this pass is implementing an analysis pass. + virtual bool isAnalysis() const { return true; } + virtual bool runOnFunction(Function &F) { Tracker = new AliasSetTracker(getAnalysis()); Modified: llvm/trunk/lib/Analysis/CFGPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/CFGPrinter.cpp?rev=48476&r1=48475&r2=48476&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/CFGPrinter.cpp (original) +++ llvm/trunk/lib/Analysis/CFGPrinter.cpp Mon Mar 17 19:39:19 2008 @@ -94,6 +94,9 @@ static char ID; // Pass identifcation, replacement for typeid CFGViewer() : FunctionPass((intptr_t)&ID) {} + /// isAnalysis - Return true if this pass is implementing an analysis pass. + virtual bool isAnalysis() const { return true; } + virtual bool runOnFunction(Function &F) { F.viewCFG(); return false; @@ -114,6 +117,9 @@ static char ID; // Pass identifcation, replacement for typeid CFGOnlyViewer() : FunctionPass((intptr_t)&ID) {} + /// isAnalysis - Return true if this pass is implementing an analysis pass. + virtual bool isAnalysis() const { return true; } + virtual bool runOnFunction(Function &F) { CFGOnly = true; F.viewCFG(); @@ -137,6 +143,9 @@ CFGPrinter() : FunctionPass((intptr_t)&ID) {} explicit CFGPrinter(intptr_t pid) : FunctionPass(pid) {} + /// isAnalysis - Return true if this pass is implementing an analysis pass. + virtual bool isAnalysis() const { return true; } + virtual bool runOnFunction(Function &F) { std::string Filename = "cfg." + F.getName() + ".dot"; cerr << "Writing '" << Filename << "'..."; @@ -164,6 +173,10 @@ struct VISIBILITY_HIDDEN CFGOnlyPrinter : public CFGPrinter { static char ID; // Pass identification, replacement for typeid CFGOnlyPrinter() : CFGPrinter((intptr_t)&ID) {} + + /// isAnalysis - Return true if this pass is implementing an analysis pass. + virtual bool isAnalysis() const { return true; } + virtual bool runOnFunction(Function &F) { bool OldCFGOnly = CFGOnly; CFGOnly = true; Modified: llvm/trunk/lib/Analysis/IPA/Andersens.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/IPA/Andersens.cpp?rev=48476&r1=48475&r2=48476&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/IPA/Andersens.cpp (original) +++ llvm/trunk/lib/Analysis/IPA/Andersens.cpp Mon Mar 17 19:39:19 2008 @@ -432,6 +432,9 @@ static char ID; Andersens() : ModulePass((intptr_t)&ID) {} + /// isAnalysis - Return true if this pass is implementing an analysis pass. + virtual bool isAnalysis() const { return true; } + bool runOnModule(Module &M) { InitializeAliasAnalysis(this); IdentifyObjects(M); Modified: llvm/trunk/lib/Analysis/IPA/GlobalsModRef.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/IPA/GlobalsModRef.cpp?rev=48476&r1=48475&r2=48476&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/IPA/GlobalsModRef.cpp (original) +++ llvm/trunk/lib/Analysis/IPA/GlobalsModRef.cpp Mon Mar 17 19:39:19 2008 @@ -86,6 +86,9 @@ static char ID; GlobalsModRef() : ModulePass((intptr_t)&ID) {} + /// isAnalysis - Return true if this pass is implementing an analysis pass. + virtual bool isAnalysis() const { return true; } + bool runOnModule(Module &M) { InitializeAliasAnalysis(this); // set up super class AnalyzeGlobals(M); // find non-addr taken globals Modified: llvm/trunk/lib/Analysis/InstCount.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InstCount.cpp?rev=48476&r1=48475&r2=48476&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/InstCount.cpp (original) +++ llvm/trunk/lib/Analysis/InstCount.cpp Mon Mar 17 19:39:19 2008 @@ -51,6 +51,10 @@ abort(); } public: + + /// isAnalysis - Return true if this pass is implementing an analysis pass. + virtual bool isAnalysis() const { return true; } + static char ID; // Pass identification, replacement for typeid InstCount() : FunctionPass((intptr_t)&ID) {} Modified: llvm/trunk/lib/Analysis/LoadValueNumbering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/LoadValueNumbering.cpp?rev=48476&r1=48475&r2=48476&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/LoadValueNumbering.cpp (original) +++ llvm/trunk/lib/Analysis/LoadValueNumbering.cpp Mon Mar 17 19:39:19 2008 @@ -43,6 +43,9 @@ static char ID; // Class identification, replacement for typeinfo LoadVN() : FunctionPass((intptr_t)&ID) {} + /// isAnalysis - Return true if this pass is implementing an analysis pass. + virtual bool isAnalysis() const { return true; } + /// Pass Implementation stuff. This doesn't do any analysis. /// bool runOnFunction(Function &) { return false; } Modified: llvm/trunk/lib/Analysis/ProfileInfoLoaderPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ProfileInfoLoaderPass.cpp?rev=48476&r1=48475&r2=48476&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ProfileInfoLoaderPass.cpp (original) +++ llvm/trunk/lib/Analysis/ProfileInfoLoaderPass.cpp Mon Mar 17 19:39:19 2008 @@ -46,6 +46,9 @@ return "Profiling information loader"; } + /// isAnalysis - Return true if this pass is implementing an analysis pass. + virtual bool isAnalysis() const { return true; } + /// run - Load the profile information from the specified file. virtual bool runOnModule(Module &M); }; Modified: llvm/trunk/lib/VMCore/PassManager.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/PassManager.cpp?rev=48476&r1=48475&r2=48476&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/PassManager.cpp (original) +++ llvm/trunk/lib/VMCore/PassManager.cpp Mon Mar 17 19:39:19 2008 @@ -426,6 +426,12 @@ // Give pass a chance to prepare the stage. P->preparePassManager(activeStack); + // If P is an analysis pass and it is available then do not + // generate the analysis again. Stale analysis info should not be + // available at this point. + if (P->isAnalysis() && findAnalysisPass(P->getPassInfo())) + return; + AnalysisUsage AnUsage; P->getAnalysisUsage(AnUsage); const std::vector &RequiredSet = AnUsage.getRequiredSet(); From dalej at apple.com Mon Mar 17 20:52:17 2008 From: dalej at apple.com (Dale Johannesen) Date: Tue, 18 Mar 2008 01:52:17 -0000 Subject: [llvm-commits] [llvm] r48478 - /llvm/trunk/include/llvm/Analysis/LoopInfo.h Message-ID: <200803180152.m2I1qHdt018431@zion.cs.uiuc.edu> Author: johannes Date: Mon Mar 17 20:52:17 2008 New Revision: 48478 URL: http://llvm.org/viewvc/llvm-project?rev=48478&view=rev Log: Get rid of compilation warnings. Per Devang. Modified: llvm/trunk/include/llvm/Analysis/LoopInfo.h Modified: llvm/trunk/include/llvm/Analysis/LoopInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/LoopInfo.h?rev=48478&r1=48477&r2=48478&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/LoopInfo.h (original) +++ llvm/trunk/include/llvm/Analysis/LoopInfo.h Mon Mar 17 20:52:17 2008 @@ -580,9 +580,6 @@ LoopInfoBase() { } ~LoopInfoBase() { releaseMemory(); } - /// isAnalysis - Return true if this pass is implementing an analysis pass. - virtual bool isAnalysis() const { return true; } - void releaseMemory() { for (typename std::vector* >::iterator I = TopLevelLoops.begin(), E = TopLevelLoops.end(); I != E; ++I) @@ -922,6 +919,9 @@ return LI->isLoopHeader(BB); } + /// isAnalysis - Return true if this pass is implementing an analysis pass. + bool isAnalysis() const { return true; } + /// runOnFunction - Calculate the natural loop information. /// virtual bool runOnFunction(Function &F); From criswell at uiuc.edu Mon Mar 17 21:49:11 2008 From: criswell at uiuc.edu (John Criswell) Date: Tue, 18 Mar 2008 02:49:11 -0000 Subject: [llvm-commits] [poolalloc] r48480 - in /poolalloc/branches/SVA: include/dsa/DSNode.h lib/DSA/Local.cpp Message-ID: <200803180249.m2I2nBMY019968@zion.cs.uiuc.edu> Author: criswell Date: Mon Mar 17 21:49:11 2008 New Revision: 48480 URL: http://llvm.org/viewvc/llvm-project?rev=48480&view=rev Log: Add support for I/O allocations. Modified: poolalloc/branches/SVA/include/dsa/DSNode.h poolalloc/branches/SVA/lib/DSA/Local.cpp Modified: poolalloc/branches/SVA/include/dsa/DSNode.h URL: http://llvm.org/viewvc/llvm-project/poolalloc/branches/SVA/include/dsa/DSNode.h?rev=48480&r1=48479&r2=48480&view=diff ============================================================================== --- poolalloc/branches/SVA/include/dsa/DSNode.h (original) +++ poolalloc/branches/SVA/include/dsa/DSNode.h Mon Mar 17 21:49:11 2008 @@ -158,11 +158,12 @@ Array = 1 << 7, // This node is treated like an array External = 1 << 8, // This node comes from an external source + IONode = 1 << 9, // This node comes from an external source //#ifndef NDEBUG - DEAD = 1 << 9, // This node is dead and should not be pointed to + DEAD = 1 << 10, // This node is dead and should not be pointed to //#endif - Composition = AllocaNode | HeapNode | GlobalNode | UnknownNode + Composition = AllocaNode | HeapNode | GlobalNode | IONode | UnknownNode }; /// NodeType - A union of the above bits. "Shadow" nodes do not add any flags @@ -419,10 +420,12 @@ bool isComplete() const { return !isIncomplete(); } bool isDeadNode() const { return NodeType & DEAD; } bool isExternalNode() const { return NodeType & External; } + bool isIONode() const { return IONode & External; } DSNode *setAllocaNodeMarker() { NodeType |= AllocaNode; return this; } DSNode *setHeapNodeMarker() { NodeType |= HeapNode; return this; } DSNode *setGlobalNodeMarker() { NodeType |= GlobalNode; return this; } + DSNode *setIONodeMarker() { NodeType |= IONode; return this; } DSNode *setUnknownNodeMarker(); // { ++stat_unknown; NodeType |= UnknownNode; return this; } DSNode *setExternalMarker() { NodeType |= External; return this; } Modified: poolalloc/branches/SVA/lib/DSA/Local.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/branches/SVA/lib/DSA/Local.cpp?rev=48480&r1=48479&r2=48480&view=diff ============================================================================== --- poolalloc/branches/SVA/lib/DSA/Local.cpp (original) +++ poolalloc/branches/SVA/lib/DSA/Local.cpp Mon Mar 17 21:49:11 2008 @@ -79,6 +79,12 @@ cl::CommaSeparated, cl::Hidden); static cl::list +IOAllocList("dsa-ioalloc-list", + cl::value_desc("list"), + cl::desc("List of functions that allocate memory for I/O"), + cl::CommaSeparated, cl::Hidden); + +static cl::list FreeList("dsa-free-list", cl::value_desc("list"), cl::desc("List of functions that free memory from the heap"), @@ -1513,7 +1519,20 @@ RetNH.getNode()->getMP()->addCallSite(CS); return; } - + +#ifdef SVA_IO + if (IOAllocList.end() != std::find(IOAllocList.begin(), IOAllocList.end(), F->getName())) { + DSNodeHandle RetNH; + if (F->getName() == "pseudo_alloc") + RetNH = getValueDest(**CS.arg_begin()); + else + RetNH = getValueDest(*CS.getInstruction()); + RetNH.getNode()->setIONodeMarker()->setModifiedMarker(); + RetNH.getNode()->getMP()->addCallSite(CS); + return; + } +#endif + // Determine if the called function is one of the specified heap // free functions if (FreeList.end() != std::find(FreeList.begin(), FreeList.end(), @@ -1804,6 +1823,11 @@ AllocList.push_back("pseudo_alloc"); AllocList.push_back("malloc"); +#ifdef SVA_IO + IOAllocList.push_back("ioremap"); + IOAllocList.push_back("ioremap_nocache"); +#endif + #if 0 FreeList.push_back("kfree"); #endif From criswell at uiuc.edu Mon Mar 17 22:28:06 2008 From: criswell at uiuc.edu (John Criswell) Date: Tue, 18 Mar 2008 03:28:06 -0000 Subject: [llvm-commits] [poolalloc] r48481 - in /poolalloc/branches/SVA: autoconf/configure.ac configure include/poolalloc/Config/config.h.in Message-ID: <200803180328.m2I3S7n5021166@zion.cs.uiuc.edu> Author: criswell Date: Mon Mar 17 22:28:06 2008 New Revision: 48481 URL: http://llvm.org/viewvc/llvm-project?rev=48481&view=rev Log: Added the --enable-safeio configure option for safe I/O in SVA. Fixed a comment in configure.ac. Modified: poolalloc/branches/SVA/autoconf/configure.ac poolalloc/branches/SVA/configure poolalloc/branches/SVA/include/poolalloc/Config/config.h.in Modified: poolalloc/branches/SVA/autoconf/configure.ac URL: http://llvm.org/viewvc/llvm-project/poolalloc/branches/SVA/autoconf/configure.ac?rev=48481&r1=48480&r2=48481&view=diff ============================================================================== --- poolalloc/branches/SVA/autoconf/configure.ac (original) +++ poolalloc/branches/SVA/autoconf/configure.ac Mon Mar 17 22:28:06 2008 @@ -79,13 +79,20 @@ AC_DEFINE(BOUNDS_CHECK,[[1]]), ) -dnl --enable-llva-kernel: Compile DSA for pool inference +dnl --enable-kernel: Compile DSA for pool inference AC_ARG_ENABLE(kernel, AS_HELP_STRING(--enable-kernel, [Use SAFECode for use with Linux Kernel (default is NO)]), AC_DEFINE(LLVA_KERNEL,[[1]]), ) +dnl --enable-safeio: Compile DSA to support safe I/O in SVA +AC_ARG_ENABLE(safeio, + AS_HELP_STRING(--enable-safeio, + [Enable safe I/O for SVA (default is NO)]), + AC_DEFINE(SVA_IO,[[1]]), + ) + dnl ************************************************************************** dnl * Set the location of various third-party software packages dnl ************************************************************************** Modified: poolalloc/branches/SVA/configure URL: http://llvm.org/viewvc/llvm-project/poolalloc/branches/SVA/configure?rev=48481&r1=48480&r2=48481&view=diff ============================================================================== --- poolalloc/branches/SVA/configure (original) +++ poolalloc/branches/SVA/configure Mon Mar 17 22:28:06 2008 @@ -848,6 +848,7 @@ --enable-boundschecks Enable SAFECode bounds checking (default is NO) --enable-kernel Use SAFECode for use with Linux Kernel (default is NO) + --enable-safeio Enable safe I/O for SVA (default is NO) Optional Packages: --with-PACKAGE[=ARG] use PACKAGE [ARG=yes] @@ -3664,6 +3665,15 @@ fi; +# Check whether --enable-safeio or --disable-safeio was given. +if test "${enable_safeio+set}" = set; then + enableval="$enable_safeio" + cat >>confdefs.h <<\_ACEOF +#define SVA_IO 1 +_ACEOF + +fi; + # Check whether --with-safecodesrc or --without-safecodesrc was given. Modified: poolalloc/branches/SVA/include/poolalloc/Config/config.h.in URL: http://llvm.org/viewvc/llvm-project/poolalloc/branches/SVA/include/poolalloc/Config/config.h.in?rev=48481&r1=48480&r2=48481&view=diff ============================================================================== --- poolalloc/branches/SVA/include/poolalloc/Config/config.h.in (original) +++ poolalloc/branches/SVA/include/poolalloc/Config/config.h.in Mon Mar 17 22:28:06 2008 @@ -475,3 +475,6 @@ /* Define to 1 if compiling for pool inference */ #undef LLVA_KERNEL +/* Define to 1 if compiling with safe I/O for SVA */ +#undef SVA_IO + From tonic at nondot.org Mon Mar 17 22:45:46 2008 From: tonic at nondot.org (Tanya Lattner) Date: Tue, 18 Mar 2008 03:45:46 -0000 Subject: [llvm-commits] [llvm] r48483 - in /llvm/trunk/test/Transforms: InstCombine/ SimplifyCFG/ Message-ID: <200803180345.m2I3jkEl021832@zion.cs.uiuc.edu> Author: tbrethou Date: Mon Mar 17 22:45:45 2008 New Revision: 48483 URL: http://llvm.org/viewvc/llvm-project?rev=48483&view=rev Log: Upgrade tests to not use llvm-upgrade. Modified: llvm/trunk/test/Transforms/InstCombine/div.ll llvm/trunk/test/Transforms/InstCombine/memmove.ll llvm/trunk/test/Transforms/InstCombine/mul.ll llvm/trunk/test/Transforms/SimplifyCFG/BrUnwind.ll llvm/trunk/test/Transforms/SimplifyCFG/DeadSetCC.ll llvm/trunk/test/Transforms/SimplifyCFG/EqualPHIEdgeBlockMerge.ll llvm/trunk/test/Transforms/SimplifyCFG/HoistCode.ll llvm/trunk/test/Transforms/SimplifyCFG/InvokeEliminate.ll llvm/trunk/test/Transforms/SimplifyCFG/PhiBlockMerge.ll llvm/trunk/test/Transforms/SimplifyCFG/PhiEliminate.ll llvm/trunk/test/Transforms/SimplifyCFG/PhiEliminate2.ll llvm/trunk/test/Transforms/SimplifyCFG/PhiNoEliminate.ll llvm/trunk/test/Transforms/SimplifyCFG/UncondBranchToReturn.ll llvm/trunk/test/Transforms/SimplifyCFG/UnreachableEliminate.ll llvm/trunk/test/Transforms/SimplifyCFG/basictest.ll llvm/trunk/test/Transforms/SimplifyCFG/branch-cond-merge.ll llvm/trunk/test/Transforms/SimplifyCFG/branch-cond-prop.ll llvm/trunk/test/Transforms/SimplifyCFG/branch-fold-test.ll llvm/trunk/test/Transforms/SimplifyCFG/branch-fold.ll llvm/trunk/test/Transforms/SimplifyCFG/branch-phi-thread.ll llvm/trunk/test/Transforms/SimplifyCFG/hoist-common-code.ll llvm/trunk/test/Transforms/SimplifyCFG/return-merge.ll llvm/trunk/test/Transforms/SimplifyCFG/switch-simplify-crash.ll llvm/trunk/test/Transforms/SimplifyCFG/switch_create.ll llvm/trunk/test/Transforms/SimplifyCFG/switch_formation.ll llvm/trunk/test/Transforms/SimplifyCFG/switch_switch_fold.ll Modified: llvm/trunk/test/Transforms/InstCombine/div.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/div.ll?rev=48483&r1=48482&r2=48483&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/div.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/div.ll Mon Mar 17 22:45:45 2008 @@ -1,69 +1,74 @@ ; This test makes sure that div instructions are properly eliminated. ; -; RUN: llvm-upgrade < %s | llvm-as | opt -instcombine | llvm-dis | not grep div +; RUN: llvm-as < %s | opt -instcombine | llvm-dis | not grep div ; END. -implementation - -int %test1(int %A) { - %B = div int %A, 1 - ret int %B +define i32 @test1(i32 %A) { + %B = sdiv i32 %A, 1 ; [#uses=1] + ret i32 %B } -uint %test2(uint %A) { - %B = div uint %A, 8 ; => Shift - ret uint %B +define i32 @test2(i32 %A) { + ; => Shift + %B = udiv i32 %A, 8 ; [#uses=1] + ret i32 %B } -int %test3(int %A) { - %B = div int 0, %A ; => 0, don't need to keep traps - ret int %B +define i32 @test3(i32 %A) { + ; => 0, don't need to keep traps + %B = sdiv i32 0, %A ; [#uses=1] + ret i32 %B } -int %test4(int %A) { - %B = div int %A, -1 ; 0-A - ret int %B +define i32 @test4(i32 %A) { + ; 0-A + %B = sdiv i32 %A, -1 ; [#uses=1] + ret i32 %B } -uint %test5(uint %A) { - %B = div uint %A, 4294967280 - %C = div uint %B, 4294967292 - ret uint %C +define i32 @test5(i32 %A) { + %B = udiv i32 %A, -16 ; [#uses=1] + %C = udiv i32 %B, -4 ; [#uses=1] + ret i32 %C } -bool %test6(uint %A) { - %B = div uint %A, 123 - %C = seteq uint %B, 0 ; A < 123 - ret bool %C -} +define i1 @test6(i32 %A) { + %B = udiv i32 %A, 123 ; [#uses=1] + ; A < 123 + %C = icmp eq i32 %B, 0 ; [#uses=1] + ret i1 %C +} -bool %test7(uint %A) { - %B = div uint %A, 10 - %C = seteq uint %B, 2 ; A >= 20 && A < 30 - ret bool %C +define i1 @test7(i32 %A) { + %B = udiv i32 %A, 10 ; [#uses=1] + ; A >= 20 && A < 30 + %C = icmp eq i32 %B, 2 ; [#uses=1] + ret i1 %C } -bool %test8(ubyte %A) { - %B = div ubyte %A, 123 - %C = seteq ubyte %B, 2 ; A >= 246 - ret bool %C -} +define i1 @test8(i8 %A) { + %B = udiv i8 %A, 123 ; [#uses=1] + ; A >= 246 + %C = icmp eq i8 %B, 2 ; [#uses=1] + ret i1 %C +} -bool %test9(ubyte %A) { - %B = div ubyte %A, 123 - %C = setne ubyte %B, 2 ; A < 246 - ret bool %C -} +define i1 @test9(i8 %A) { + %B = udiv i8 %A, 123 ; [#uses=1] + ; A < 246 + %C = icmp ne i8 %B, 2 ; [#uses=1] + ret i1 %C +} -uint %test10(uint %X, bool %C) { - %V = select bool %C, uint 64, uint 8 - %R = udiv uint %X, %V - ret uint %R +define i32 @test10(i32 %X, i1 %C) { + %V = select i1 %C, i32 64, i32 8 ; [#uses=1] + %R = udiv i32 %X, %V ; [#uses=1] + ret i32 %R } -int %test11(int %X, bool %C) { - %A = select bool %C, int 1024, int 32 - %B = udiv int %X, %A - ret int %B +define i32 @test11(i32 %X, i1 %C) { + %A = select i1 %C, i32 1024, i32 32 ; [#uses=1] + %B = udiv i32 %X, %A ; [#uses=1] + ret i32 %B } Modified: llvm/trunk/test/Transforms/InstCombine/memmove.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/memmove.ll?rev=48483&r1=48482&r2=48483&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/memmove.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/memmove.ll Mon Mar 17 22:45:45 2008 @@ -1,23 +1,19 @@ ; This test makes sure that memmove instructions are properly eliminated. ; -; RUN: llvm-upgrade < %s | llvm-as | opt -instcombine | llvm-dis | \ +; RUN: llvm-as < %s | opt -instcombine | llvm-dis | \ ; RUN: not grep {call void @llvm.memmove} -%S = internal constant [33 x sbyte] c"panic: restorelist inconsistency\00" + at S = internal constant [33 x i8] c"panic: restorelist inconsistency\00" ; <[33 x i8]*> [#uses=1] -implementation +declare void @llvm.memmove.i32(i8*, i8*, i32, i32) -declare void %llvm.memmove.i32(sbyte*, sbyte*, uint, uint) - -void %test1(sbyte* %A, sbyte* %B, uint %N) { - ;; 0 bytes -> noop. - call void %llvm.memmove.i32(sbyte* %A, sbyte* %B, uint 0, uint 1) +define void @test1(i8* %A, i8* %B, i32 %N) { + call void @llvm.memmove.i32( i8* %A, i8* %B, i32 0, i32 1 ) ret void } -void %test2(sbyte *%A, uint %N) { - ;; dest can't alias source since we can't write to source! - call void %llvm.memmove.i32(sbyte* %A, sbyte* getelementptr ([33 x sbyte]* %S, int 0, int 0), - uint %N, uint 1) +define void @test2(i8* %A, i32 %N) { + ;; dest can't alias source since we can't write to source! + call void @llvm.memmove.i32( i8* %A, i8* getelementptr ([33 x i8]* @S, i32 0, i32 0), i32 %N, i32 1 ) ret void } Modified: llvm/trunk/test/Transforms/InstCombine/mul.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/mul.ll?rev=48483&r1=48482&r2=48483&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/mul.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/mul.ll Mon Mar 17 22:45:45 2008 @@ -1,74 +1,80 @@ ; This test makes sure that mul instructions are properly eliminated. ; -; RUN: llvm-upgrade < %s | llvm-as | opt -instcombine | llvm-dis | not grep mul +; RUN: llvm-as < %s | opt -instcombine | llvm-dis | not grep mul ; END. -implementation - -int %test1(int %A) { - %B = mul int %A, 1 - ret int %B +define i32 @test1(i32 %A) { + %B = mul i32 %A, 1 ; [#uses=1] + ret i32 %B } -int %test2(int %A) { - %B = mul int %A, 2 ; Should convert to an add instruction - ret int %B +define i32 @test2(i32 %A) { + ; Should convert to an add instruction + %B = mul i32 %A, 2 ; [#uses=1] + ret i32 %B } -int %test3(int %A) { - %B = mul int %A, 0 ; This should disappear entirely - ret int %B +define i32 @test3(i32 %A) { + ; This should disappear entirely + %B = mul i32 %A, 0 ; [#uses=1] + ret i32 %B } -double %test4(double %A) { - %B = mul double 1.0, %A ; This is safe for FP - ret double %B +define double @test4(double %A) { + ; This is safe for FP + %B = mul double 1.000000e+00, %A ; [#uses=1] + ret double %B } -int %test5(int %A) { - %B = mul int %A, 8 - ret int %B +define i32 @test5(i32 %A) { + %B = mul i32 %A, 8 ; [#uses=1] + ret i32 %B } -ubyte %test6(ubyte %A) { - %B = mul ubyte %A, 8 - %C = mul ubyte %B, 8 - ret ubyte %C +define i8 @test6(i8 %A) { + %B = mul i8 %A, 8 ; [#uses=1] + %C = mul i8 %B, 8 ; [#uses=1] + ret i8 %C } -int %test7(int %i) { - %tmp = mul int %i, -1 ; %tmp = sub 0, %i - ret int %tmp +define i32 @test7(i32 %i) { + %tmp = mul i32 %i, -1 ; [#uses=1] + ret i32 %tmp } -ulong %test8(ulong %i) { - %j = mul ulong %i, 18446744073709551615 ; tmp = sub 0, %i - ret ulong %j +define i64 @test8(i64 %i) { + ; tmp = sub 0, %i + %j = mul i64 %i, -1 ; [#uses=1] + ret i64 %j } -uint %test9(uint %i) { - %j = mul uint %i, 4294967295 ; %j = sub 0, %i - ret uint %j +define i32 @test9(i32 %i) { + ; %j = sub 0, %i + %j = mul i32 %i, -1 ; [#uses=1] + ret i32 %j } -uint %test10(int %a, uint %b) { - %c = setlt int %a, 0 - %d = cast bool %c to uint - %e = mul uint %d, %b ; e = b & (a >> 31) - ret uint %e +define i32 @test10(i32 %a, i32 %b) { + %c = icmp slt i32 %a, 0 ; [#uses=1] + %d = zext i1 %c to i32 ; [#uses=1] + ; e = b & (a >> 31) + %e = mul i32 %d, %b ; [#uses=1] + ret i32 %e } -uint %test11(int %a, uint %b) { - %c = setle int %a, -1 - %d = cast bool %c to uint - %e = mul uint %d, %b ; e = b & (a >> 31) - ret uint %e +define i32 @test11(i32 %a, i32 %b) { + %c = icmp sle i32 %a, -1 ; [#uses=1] + %d = zext i1 %c to i32 ; [#uses=1] + ; e = b & (a >> 31) + %e = mul i32 %d, %b ; [#uses=1] + ret i32 %e } -uint %test12(ubyte %a, uint %b) { - %c = setgt ubyte %a, 127 - %d = cast bool %c to uint - %e = mul uint %d, %b ; e = b & (a >> 31) - ret uint %e +define i32 @test12(i8 %a, i32 %b) { + %c = icmp ugt i8 %a, 127 ; [#uses=1] + %d = zext i1 %c to i32 ; [#uses=1] + ; e = b & (a >> 31) + %e = mul i32 %d, %b ; [#uses=1] + ret i32 %e } Modified: llvm/trunk/test/Transforms/SimplifyCFG/BrUnwind.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/BrUnwind.ll?rev=48483&r1=48482&r2=48483&view=diff ============================================================================== --- llvm/trunk/test/Transforms/SimplifyCFG/BrUnwind.ll (original) +++ llvm/trunk/test/Transforms/SimplifyCFG/BrUnwind.ll Mon Mar 17 22:45:45 2008 @@ -1,14 +1,15 @@ -; RUN: llvm-upgrade < %s | llvm-as | opt -simplifycfg | llvm-dis | \ +; RUN: llvm-as < %s | opt -simplifycfg | llvm-dis | \ ; RUN: not grep {br label} -void %test(bool %C) { - br bool %C, label %A, label %B -A: - call void %test(bool %C) - br label %X -B: - call void %test(bool %C) - br label %X -X: - unwind +define void @test(i1 %C) { + br i1 %C, label %A, label %B +A: ; preds = %0 + call void @test( i1 %C ) + br label %X +B: ; preds = %0 + call void @test( i1 %C ) + br label %X +X: ; preds = %B, %A + unwind } + Modified: llvm/trunk/test/Transforms/SimplifyCFG/DeadSetCC.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/DeadSetCC.ll?rev=48483&r1=48482&r2=48483&view=diff ============================================================================== --- llvm/trunk/test/Transforms/SimplifyCFG/DeadSetCC.ll (original) +++ llvm/trunk/test/Transforms/SimplifyCFG/DeadSetCC.ll Mon Mar 17 22:45:45 2008 @@ -1,27 +1,28 @@ -; RUN: llvm-upgrade < %s | llvm-as | opt -simplifycfg | llvm-dis | \ +; RUN: llvm-as < %s | opt -simplifycfg | llvm-dis | \ ; RUN: not grep {icmp eq} ; Check that simplifycfg deletes a dead 'seteq' instruction when it ; folds a conditional branch into a switch instruction. -declare void %foo() -declare void %bar() +declare void @foo() -void %testcfg(uint %V) { - %C = seteq uint %V, 18 - %D = seteq uint %V, 180 - %E = or bool %C, %D - br bool %E, label %L1, label %Sw -Sw: - switch uint %V, label %L1 [ - uint 15, label %L2 - uint 16, label %L2 +declare void @bar() + +define void @testcfg(i32 %V) { + %C = icmp eq i32 %V, 18 ; [#uses=1] + %D = icmp eq i32 %V, 180 ; [#uses=1] + %E = or i1 %C, %D ; [#uses=1] + br i1 %E, label %L1, label %Sw +Sw: ; preds = %0 + switch i32 %V, label %L1 [ + i32 15, label %L2 + i32 16, label %L2 ] -L1: - call void %foo() - ret void -L2: - call void %bar() - ret void +L1: ; preds = %Sw, %0 + call void @foo( ) + ret void +L2: ; preds = %Sw, %Sw + call void @bar( ) + ret void } Modified: llvm/trunk/test/Transforms/SimplifyCFG/EqualPHIEdgeBlockMerge.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/EqualPHIEdgeBlockMerge.ll?rev=48483&r1=48482&r2=48483&view=diff ============================================================================== --- llvm/trunk/test/Transforms/SimplifyCFG/EqualPHIEdgeBlockMerge.ll (original) +++ llvm/trunk/test/Transforms/SimplifyCFG/EqualPHIEdgeBlockMerge.ll Mon Mar 17 22:45:45 2008 @@ -1,18 +1,18 @@ ; Test merging of blocks with phi nodes. ; -; RUN: llvm-upgrade < %s | llvm-as | opt -simplifycfg | llvm-dis | not grep N: +; RUN: llvm-as < %s | opt -simplifycfg | llvm-dis | not grep N: ; -int %test(bool %a) { +define i32 @test(i1 %a) { Q: - br bool %a, label %N, label %M -N: - br label %M -M: - ; It's ok to merge N and M because the incoming values for W are the + br i1 %a, label %N, label %M +N: ; preds = %Q + br label %M +M: ; preds = %N, %Q + ; It's ok to merge N and M because the incoming values for W are the ; same for both cases... - %W = phi int [2, %N], [2, %Q] - %R = add int %W, 1 - ret int %R + %W = phi i32 [ 2, %N ], [ 2, %Q ] ; [#uses=1] + %R = add i32 %W, 1 ; [#uses=1] + ret i32 %R } Modified: llvm/trunk/test/Transforms/SimplifyCFG/HoistCode.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/HoistCode.ll?rev=48483&r1=48482&r2=48483&view=diff ============================================================================== --- llvm/trunk/test/Transforms/SimplifyCFG/HoistCode.ll (original) +++ llvm/trunk/test/Transforms/SimplifyCFG/HoistCode.ll Mon Mar 17 22:45:45 2008 @@ -1,11 +1,11 @@ -; RUN: llvm-upgrade < %s | llvm-as | opt -simplifycfg | llvm-dis | not grep br +; RUN: llvm-as < %s | opt -simplifycfg | llvm-dis | not grep br -void %foo(bool %C, int* %P) { - br bool %C, label %T, label %F -T: - store int 7, int* %P - ret void -F: - store int 7, int* %P - ret void +define void @foo(i1 %C, i32* %P) { + br i1 %C, label %T, label %F +T: ; preds = %0 + store i32 7, i32* %P + ret void +F: ; preds = %0 + store i32 7, i32* %P + ret void } Modified: llvm/trunk/test/Transforms/SimplifyCFG/InvokeEliminate.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/InvokeEliminate.ll?rev=48483&r1=48482&r2=48483&view=diff ============================================================================== --- llvm/trunk/test/Transforms/SimplifyCFG/InvokeEliminate.ll (original) +++ llvm/trunk/test/Transforms/SimplifyCFG/InvokeEliminate.ll Mon Mar 17 22:45:45 2008 @@ -3,16 +3,16 @@ ; If this test is successful, the function should be reduced to 'call; ret' -; RUN: llvm-upgrade < %s | llvm-as | opt -simplifycfg | llvm-dis | \ +; RUN: llvm-as < %s | opt -simplifycfg | llvm-dis | \ ; RUN: not egrep {\\(invoke\\)|\\(br\\)} -declare void %bar() +declare void @bar() -int %test() { - invoke void %bar() to label %Ok except label %Rethrow -Ok: - ret int 0 -Rethrow: - unwind +define i32 @test() { + invoke void @bar( ) + to label %Ok unwind label %Rethrow +Ok: ; preds = %0 + ret i32 0 +Rethrow: ; preds = %0 + unwind } - Modified: llvm/trunk/test/Transforms/SimplifyCFG/PhiBlockMerge.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/PhiBlockMerge.ll?rev=48483&r1=48482&r2=48483&view=diff ============================================================================== --- llvm/trunk/test/Transforms/SimplifyCFG/PhiBlockMerge.ll (original) +++ llvm/trunk/test/Transforms/SimplifyCFG/PhiBlockMerge.ll Mon Mar 17 22:45:45 2008 @@ -1,23 +1,22 @@ ; Test merging of blocks that only have PHI nodes in them ; -; RUN: llvm-upgrade < %s | llvm-as | opt -simplifycfg | llvm-dis | not grep N: +; RUN: llvm-as < %s | opt -simplifycfg | llvm-dis | not grep N: ; -int %test(bool %a, bool %b) { - br bool %a, label %M, label %O - -O: - br bool %b, label %N, label %Q -Q: - br label %N -N: - %Wp = phi int [0, %O], [1, %Q] - ; This block should be foldable into M - br label %M - -M: - %W = phi int [%Wp, %N], [2, %0] - %R = add int %W, 1 - ret int %R +define i32 @test(i1 %a, i1 %b) { +;