::operands(this),
InsertAtEnd) {
From gohman at apple.com Mon May 12 15:01:55 2008
From: gohman at apple.com (Dan Gohman)
Date: Mon, 12 May 2008 13:01:55 -0700
Subject: [llvm-commits] [llvm] r50985 - in /llvm/trunk: docs/
include/llvm/ include/llvm/Support/ lib/AsmParser/
lib/Bitcode/Reader/ lib/Bitcode/Writer/ lib/VMCore/
In-Reply-To: <200805121902.m4CJ22Nt020896@zion.cs.uiuc.edu>
References: <200805121902.m4CJ22Nt020896@zion.cs.uiuc.edu>
Message-ID: <7F43E616-CAAE-4571-A7F2-0A5AC5A8791F@apple.com>
On May 12, 2008, at 12:01 PM, Nate Begeman wrote:
> Author: sampo
> Date: Mon May 12 14:01:56 2008
> New Revision: 50985
>
> URL: http://llvm.org/viewvc/llvm-project?rev=50985&view=rev
> Log:
> Add two new instructions to the llvm IR, vicmp and vfcmp. see
> updated LangRef
> for details. CodeGen support coming in a follow up patch
Awesome!
> +Semantics:
> +The 'vicmp' instruction compares var1 and
> var2
> +according to the condition code given as cond. The
> comparison yields a
> +vector of integer
> result, of
> +identical type as the values being compared. The most significant
> bit in each
> +element is 1 if the element-wise comparison evaluates to true, and
> is 0
> +otherwise. All other bits of the result are undefined. The
> condition codes
> +are evaluated identically to the 'icmp'
> +instruction.
It would be neat to overload the existing fcmp and icmp instead of
introducing new instructions. But vicmp and vfcmp address a real
need today without requiring the codegen to perform a bunch of magic
on vectors of i1 to make this approach work well on current targets.
Fortunately, nothing here rules out extending fcmp and icmp in the
future :-).
Dan
From resistor at mac.com Mon May 12 15:05:25 2008
From: resistor at mac.com (Owen Anderson)
Date: Mon, 12 May 2008 15:05:25 -0500
Subject: [llvm-commits] [llvm] r50991 - in /llvm/trunk/lib:
CodeGen/SelectionDAG/TargetLowering.cpp
Target/X86/X86ISelLowering.cpp Target/X86/X86ISelLowering.h
In-Reply-To: <200805121956.m4CJuueV022748@zion.cs.uiuc.edu>
References: <200805121956.m4CJuueV022748@zion.cs.uiuc.edu>
Message-ID: <1D2E46A3-380C-402E-A5F5-C5E0BCAE01FC@mac.com>
This is breaking the build.
llvm[3]: Compiling TargetLowering.cpp for Release build
TargetLowering.cpp:1485: error: no ?bool
llvm::TargetLowering::isGAPlusOffset(llvm::SDNode*,
llvm::GlobalValue*&, int64_t&) const? member function declared in
class ?llvm::TargetLowering?
TargetLowering.cpp:1517: error: no ?bool
llvm::TargetLowering::isConsecutiveLoad(llvm::SDNode*, llvm::SDNode*,
unsigned int, int, llvm::MachineFrameInfo*) const? member function
declared in class ?llvm::TargetLowering?
--Owen
On May 12, 2008, at 2:56 PM, Evan Cheng wrote:
> Author: evancheng
> Date: Mon May 12 14:56:52 2008
> New Revision: 50991
>
> URL: http://llvm.org/viewvc/llvm-project?rev=50991&view=rev
> Log:
> Refactor isConsecutiveLoad from X86 to TargetLowering so DAG
> combiner can make use of it.
>
> Modified:
> llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
> llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> llvm/trunk/lib/Target/X86/X86ISelLowering.h
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=50991&r1=50990&r2=50991&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Mon May
> 12 14:56:52 2008
> @@ -19,6 +19,7 @@
> #include "llvm/Target/TargetRegisterInfo.h"
> #include "llvm/GlobalVariable.h"
> #include "llvm/DerivedTypes.h"
> +#include "llvm/CodeGen/MachineFrameInfo.h"
> #include "llvm/CodeGen/SelectionDAG.h"
> #include "llvm/ADT/StringExtras.h"
> #include "llvm/ADT/STLExtras.h"
> @@ -1478,6 +1479,73 @@
> return SDOperand();
> }
>
> +/// isGAPlusOffset - Returns true (and the GlobalValue and the
> offset) if the
> +/// node is a GlobalAddress + offset.
> +bool TargetLowering::isGAPlusOffset(SDNode *N, GlobalValue* &GA,
> + int64_t &Offset) const {
> + if (isa(N)) {
> + GA = cast(N)->getGlobal();
> + return true;
> + }
> +
> + if (N->getOpcode() == ISD::ADD) {
> + SDOperand N1 = N->getOperand(0);
> + SDOperand N2 = N->getOperand(1);
> + if (isGAPlusOffset(N1.Val, GA, Offset)) {
> + ConstantSDNode *V = dyn_cast(N2);
> + if (V) {
> + Offset += V->getSignExtended();
> + return true;
> + }
> + } else if (isGAPlusOffset(N2.Val, GA, Offset)) {
> + ConstantSDNode *V = dyn_cast(N1);
> + if (V) {
> + Offset += V->getSignExtended();
> + return true;
> + }
> + }
> + }
> + return false;
> +}
> +
> +
> +/// isConsecutiveLoad - Return true if LD (which must be a
> LoadSDNode) is
> +/// loading 'Bytes' bytes from a location that is 'Dist' units away
> from the
> +/// location that the 'Base' load is loading from.
> +bool TargetLowering::isConsecutiveLoad(SDNode *LD, SDNode *Base,
> + unsigned Bytes, int Dist,
> + MachineFrameInfo *MFI) const {
> + if (LD->getOperand(0).Val != Base->getOperand(0).Val)
> + return false;
> + MVT::ValueType VT = LD->getValueType(0);
> + if (MVT::getSizeInBits(VT) / 8 != Bytes)
> + return false;
> +
> + SDOperand Loc = LD->getOperand(1);
> + SDOperand BaseLoc = Base->getOperand(1);
> + if (Loc.getOpcode() == ISD::FrameIndex) {
> + if (BaseLoc.getOpcode() != ISD::FrameIndex)
> + return false;
> + int FI = cast(Loc)->getIndex();
> + int BFI = cast(BaseLoc)->getIndex();
> + int FS = MFI->getObjectSize(FI);
> + int BFS = MFI->getObjectSize(BFI);
> + if (FS != BFS || FS != (int)Bytes) return false;
> + return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) +
> Dist*Bytes);
> + }
> +
> + GlobalValue *GV1 = NULL;
> + GlobalValue *GV2 = NULL;
> + int64_t Offset1 = 0;
> + int64_t Offset2 = 0;
> + bool isGA1 = isGAPlusOffset(Loc.Val, GV1, Offset1);
> + bool isGA2 = isGAPlusOffset(BaseLoc.Val, GV2, Offset2);
> + if (isGA1 && isGA2 && GV1 == GV2)
> + return Offset1 == (Offset2 + Dist*Bytes);
> + return false;
> +}
> +
> +
> SDOperand TargetLowering::
> PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
> // Default implementation: no optimization.
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=50991&r1=50990&r2=50991&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon May 12
> 14:56:52 2008
> @@ -6194,71 +6194,23 @@
> }
>
> /// isGAPlusOffset - Returns true (and the GlobalValue and the
> offset) if the
> -/// node is a GlobalAddress + an offset.
> -static bool isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t
> &Offset) {
> - unsigned Opc = N->getOpcode();
> - if (Opc == X86ISD::Wrapper) {
> - if (dyn_cast(N->getOperand(0))) {
> +/// node is a GlobalAddress + offset.
> +bool X86TargetLowering::isGAPlusOffset(SDNode *N,
> + GlobalValue* &GA, int64_t
> &Offset) const{
> + if (N->getOpcode() == X86ISD::Wrapper) {
> + if (isa(N->getOperand(0))) {
> GA = cast(N->getOperand(0))->getGlobal();
> return true;
> }
> - } else if (Opc == ISD::ADD) {
> - SDOperand N1 = N->getOperand(0);
> - SDOperand N2 = N->getOperand(1);
> - if (isGAPlusOffset(N1.Val, GA, Offset)) {
> - ConstantSDNode *V = dyn_cast(N2);
> - if (V) {
> - Offset += V->getSignExtended();
> - return true;
> - }
> - } else if (isGAPlusOffset(N2.Val, GA, Offset)) {
> - ConstantSDNode *V = dyn_cast(N1);
> - if (V) {
> - Offset += V->getSignExtended();
> - return true;
> - }
> - }
> - }
> - return false;
> -}
> -
> -/// isConsecutiveLoad - Returns true if N is loading from an
> address of Base
> -/// + Dist * Size.
> -static bool isConsecutiveLoad(SDNode *N, SDNode *Base, int Dist,
> int Size,
> - MachineFrameInfo *MFI) {
> - if (N->getOperand(0).Val != Base->getOperand(0).Val)
> - return false;
> -
> - SDOperand Loc = N->getOperand(1);
> - SDOperand BaseLoc = Base->getOperand(1);
> - if (Loc.getOpcode() == ISD::FrameIndex) {
> - if (BaseLoc.getOpcode() != ISD::FrameIndex)
> - return false;
> - int FI = cast(Loc)->getIndex();
> - int BFI = cast(BaseLoc)->getIndex();
> - int FS = MFI->getObjectSize(FI);
> - int BFS = MFI->getObjectSize(BFI);
> - if (FS != BFS || FS != Size) return false;
> - return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) +
> Dist*Size);
> - } else {
> - GlobalValue *GV1 = NULL;
> - GlobalValue *GV2 = NULL;
> - int64_t Offset1 = 0;
> - int64_t Offset2 = 0;
> - bool isGA1 = isGAPlusOffset(Loc.Val, GV1, Offset1);
> - bool isGA2 = isGAPlusOffset(BaseLoc.Val, GV2, Offset2);
> - if (isGA1 && isGA2 && GV1 == GV2)
> - return Offset1 == (Offset2 + Dist*Size);
> }
> -
> - return false;
> + return TargetLowering::isGAPlusOffset(N, GA, Offset);
> }
>
> -static bool isBaseAlignmentOfN(unsigned N, SDNode *Base,
> MachineFrameInfo *MFI,
> - const X86Subtarget *Subtarget) {
> +static bool isBaseAlignmentOfN(unsigned N, SDNode *Base,
> + const TargetLowering &TLI) {
> GlobalValue *GV;
> int64_t Offset = 0;
> - if (isGAPlusOffset(Base, GV, Offset))
> + if (TLI.isGAPlusOffset(Base, GV, Offset))
> return (GV->getAlignment() >= N && (Offset % N) == 0);
> // DAG combine handles the stack object case.
> return false;
> @@ -6266,8 +6218,9 @@
>
> static bool EltsFromConsecutiveLoads(SDNode *N, SDOperand PermMask,
> unsigned NumElems,
> MVT::ValueType EVT,
> - MachineFrameInfo *MFI,
> - SelectionDAG &DAG, SDNode
> *&Base) {
> + SDNode *&Base,
> + SelectionDAG &DAG,
> MachineFrameInfo *MFI,
> + const TargetLowering &TLI) {
> Base = NULL;
> for (unsigned i = 0; i < NumElems; ++i) {
> SDOperand Idx = PermMask.getOperand(i);
> @@ -6291,7 +6244,8 @@
> if (Elt.getOpcode() == ISD::UNDEF)
> continue;
>
> - if (!isConsecutiveLoad(Elt.Val, Base, i,
> MVT::getSizeInBits(EVT)/8,MFI))
> + if (!TLI.isConsecutiveLoad(Elt.Val, Base,
> + MVT::getSizeInBits(EVT)/8, i, MFI))
> return false;
> }
> return true;
> @@ -6302,18 +6256,19 @@
> /// if the load addresses are consecutive, non-overlapping, and in
> the right
> /// order.
> static SDOperand PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
> - const X86Subtarget
> *Subtarget) {
> + const TargetLowering &TLI) {
> MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
> MVT::ValueType VT = N->getValueType(0);
> MVT::ValueType EVT = MVT::getVectorElementType(VT);
> SDOperand PermMask = N->getOperand(2);
> unsigned NumElems = PermMask.getNumOperands();
> SDNode *Base = NULL;
> - if (!EltsFromConsecutiveLoads(N, PermMask, NumElems, EVT, MFI,
> DAG, Base))
> + if (!EltsFromConsecutiveLoads(N, PermMask, NumElems, EVT, Base,
> + DAG, MFI, TLI))
> return SDOperand();
>
> LoadSDNode *LD = cast(Base);
> - if (isBaseAlignmentOfN(16, Base->getOperand(1).Val, MFI,
> Subtarget))
> + if (isBaseAlignmentOfN(16, Base->getOperand(1).Val, TLI))
> return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD-
> >getSrcValue(),
> LD->getSrcValueOffset(), LD->isVolatile());
> return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD-
> >getSrcValue(),
> @@ -6329,7 +6284,8 @@
> }
>
> static SDOperand PerformBuildVectorCombine(SDNode *N, SelectionDAG
> &DAG,
> - const X86Subtarget
> *Subtarget) {
> + const X86Subtarget
> *Subtarget,
> + const TargetLowering
> &TLI) {
> // Ignore single operand BUILD_VECTOR.
> if (N->getNumOperands() == 1)
> return SDOperand();
> @@ -6360,7 +6316,7 @@
> return SDOperand();
> SDNode *NextLD = getBuildPairElt(Pair, 1);
> if (!ISD::isNON_EXTLoad(NextLD) ||
> - !isConsecutiveLoad(NextLD, Base, 1, 4/*32 bits*/, MFI))
> + !TLI.isConsecutiveLoad(NextLD, Base, 4/*32 bits*/, 1, MFI))
> return SDOperand();
> }
> LoadSDNode *LD = cast(Base);
> @@ -6564,8 +6520,9 @@
> SelectionDAG &DAG = DCI.DAG;
> switch (N->getOpcode()) {
> default: break;
> - case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG,
> Subtarget);
> - case ISD::BUILD_VECTOR: return PerformBuildVectorCombine(N,
> DAG, Subtarget);
> + case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG,
> *this);
> + case ISD::BUILD_VECTOR:
> + return PerformBuildVectorCombine(N, DAG, Subtarget, *this);
> case ISD::SELECT: return PerformSELECTCombine(N, DAG,
> Subtarget);
> case ISD::STORE: return PerformSTORECombine(N, DAG,
> Subtarget);
> case X86ISD::FXOR:
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=50991&r1=50990&r2=50991&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Mon May 12 14:56:52
> 2008
> @@ -369,6 +369,9 @@
> APInt &KnownOne,
> const SelectionDAG
> &DAG,
> unsigned Depth = 0)
> const;
> +
> + virtual bool
> + isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset)
> const;
>
> SDOperand getReturnAddressFrameIndex(SelectionDAG &DAG);
>
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
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From evan.cheng at apple.com Mon May 12 15:08:12 2008
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 12 May 2008 20:08:12 -0000
Subject: [llvm-commits] [llvm] r50993 -
/llvm/trunk/include/llvm/Target/TargetLowering.h
Message-ID: <200805122008.m4CK8DVW001908@zion.cs.uiuc.edu>
Author: evancheng
Date: Mon May 12 15:08:05 2008
New Revision: 50993
URL: http://llvm.org/viewvc/llvm-project?rev=50993&view=rev
Log:
Forgot this.
Modified:
llvm/trunk/include/llvm/Target/TargetLowering.h
Modified: llvm/trunk/include/llvm/Target/TargetLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=50993&r1=50992&r2=50993&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetLowering.h (original)
+++ llvm/trunk/include/llvm/Target/TargetLowering.h Mon May 12 15:08:05 2008
@@ -32,18 +32,19 @@
#include
namespace llvm {
- class Value;
class Function;
- class TargetMachine;
- class TargetData;
- class TargetRegisterClass;
+ class MachineBasicBlock;
+ class MachineFrameInfo;
+ class MachineInstr;
class SDNode;
class SDOperand;
class SelectionDAG;
- class MachineBasicBlock;
- class MachineInstr;
- class VectorType;
+ class TargetData;
+ class TargetMachine;
+ class TargetRegisterClass;
class TargetSubtarget;
+ class Value;
+ class VectorType;
//===----------------------------------------------------------------------===//
/// TargetLowering - This class defines information used to lower LLVM code to
@@ -681,6 +682,17 @@
ISD::CondCode Cond, bool foldBooleans,
DAGCombinerInfo &DCI) const;
+ /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
+ /// node is a GlobalAddress + offset.
+ virtual bool
+ isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) const;
+
+ /// isConsecutiveLoad - Return true if LD (which must be a LoadSDNode) is
+ /// loading 'Bytes' bytes from a location that is 'Dist' units away from the
+ /// location that the 'Base' load is loading from.
+ bool isConsecutiveLoad(SDNode *LD, SDNode *Base, unsigned Bytes, int Dist,
+ MachineFrameInfo *MFI) const;
+
/// PerformDAGCombine - This method will be invoked for all target nodes and
/// for any target-independent nodes that the target has registered with
/// invoke it for.
From natebegeman at mac.com Mon May 12 15:11:05 2008
From: natebegeman at mac.com (Nate Begeman)
Date: Mon, 12 May 2008 20:11:05 -0000
Subject: [llvm-commits] [llvm] r50994 - in /llvm/trunk/lib:
Bitcode/Reader/BitcodeReader.cpp VMCore/Instructions.cpp
Message-ID: <200805122011.m4CKB50B002744@zion.cs.uiuc.edu>
Author: sampo
Date: Mon May 12 15:11:05 2008
New Revision: 50994
URL: http://llvm.org/viewvc/llvm-project?rev=50994&view=rev
Log:
Pointer comparisons should be handled by icmp, not vicmp :)
Modified:
llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp
llvm/trunk/lib/VMCore/Instructions.cpp
Modified: llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp?rev=50994&r1=50993&r2=50994&view=diff
==============================================================================
--- llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp (original)
+++ llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp Mon May 12 15:11:05 2008
@@ -1359,7 +1359,7 @@
OpNum+1 != Record.size())
return Error("Invalid CMP record");
- if (LHS->getType()->isInteger())
+ if (LHS->getType()->isInteger() || isa(LHS->getType()))
I = new ICmpInst((ICmpInst::Predicate)Record[OpNum], LHS, RHS);
else if (LHS->getType()->isFloatingPoint())
I = new FCmpInst((FCmpInst::Predicate)Record[OpNum], LHS, RHS);
Modified: llvm/trunk/lib/VMCore/Instructions.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instructions.cpp?rev=50994&r1=50993&r2=50994&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Instructions.cpp (original)
+++ llvm/trunk/lib/VMCore/Instructions.cpp Mon May 12 15:11:05 2008
@@ -2335,7 +2335,7 @@
CmpInst::CmpInst(const Type *ty, OtherOps op, unsigned short predicate,
Value *LHS, Value *RHS, const std::string &Name,
Instruction *InsertBefore)
- : Instruction(Type::Int1Ty, op,
+ : Instruction(ty, op,
OperandTraits::op_begin(this),
OperandTraits::operands(this),
InsertBefore) {
@@ -2348,7 +2348,7 @@
CmpInst::CmpInst(const Type *ty, OtherOps op, unsigned short predicate,
Value *LHS, Value *RHS, const std::string &Name,
BasicBlock *InsertAtEnd)
- : Instruction(Type::Int1Ty, op,
+ : Instruction(ty, op,
OperandTraits::op_begin(this),
OperandTraits::operands(this),
InsertAtEnd) {
From resistor at mac.com Mon May 12 15:15:57 2008
From: resistor at mac.com (Owen Anderson)
Date: Mon, 12 May 2008 20:15:57 -0000
Subject: [llvm-commits] [llvm] r50995 -
/llvm/trunk/lib/Transforms/Scalar/GVN.cpp
Message-ID: <200805122015.m4CKFvXi011285@zion.cs.uiuc.edu>
Author: resistor
Date: Mon May 12 15:15:55 2008
New Revision: 50995
URL: http://llvm.org/viewvc/llvm-project?rev=50995&view=rev
Log:
Go back to passing the analyses around as parameters.
Modified:
llvm/trunk/lib/Transforms/Scalar/GVN.cpp
Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVN.cpp?rev=50995&r1=50994&r2=50995&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/GVN.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/GVN.cpp Mon May 12 15:15:55 2008
@@ -42,10 +42,6 @@
// ValueTable Class
//===----------------------------------------------------------------------===//
-static DominatorTree* DT;
-static AliasAnalysis* AA;
-static MemoryDependenceAnalysis* MD;
-
/// This class holds the mapping between values and value numbers. It is used
/// as an efficient mechanism to determine the expression-wise equivalence of
/// two values.
@@ -133,6 +129,9 @@
private:
DenseMap valueNumbering;
DenseMap expressionNumbering;
+ AliasAnalysis* AA;
+ MemoryDependenceAnalysis* MD;
+ DominatorTree* DT;
uint32_t nextValueNumber;
@@ -156,6 +155,9 @@
void clear();
void erase(Value* v);
unsigned size();
+ void setAliasAnalysis(AliasAnalysis* A) { AA = A; }
+ void setMemDep(MemoryDependenceAnalysis* M) { MD = M; }
+ void setDomTree(DominatorTree* D) { DT = D; }
};
}
@@ -734,6 +736,7 @@
}
Value* GVN::CollapsePhi(PHINode* p) {
+ DominatorTree &DT = getAnalysis();
Value* constVal = p->hasConstantValue();
if (!constVal) return 0;
@@ -742,7 +745,7 @@
if (!inst)
return constVal;
- if (DT->dominates(inst, p))
+ if (DT.dominates(inst, p))
if (isSafeReplacement(p, inst))
return inst;
return 0;
@@ -793,7 +796,8 @@
PN->addIncoming(val, *PI);
}
- AA->copyValue(orig, PN);
+ AliasAnalysis& AA = getAnalysis();
+ AA.copyValue(orig, PN);
// Attempt to collapse PHI nodes that are trivially redundant
Value* v = CollapsePhi(PN);
@@ -802,8 +806,10 @@
phiMap[orig->getPointerOperand()].insert(PN);
return PN;
}
+
+ MemoryDependenceAnalysis& MD = getAnalysis();
- MD->removeInstruction(PN);
+ MD.removeInstruction(PN);
PN->replaceAllUsesWith(v);
for (DenseMap::iterator I = Phis.begin(),
@@ -821,9 +827,11 @@
/// non-local by performing PHI construction.
bool GVN::processNonLocalLoad(LoadInst* L,
SmallVectorImpl &toErase) {
+ MemoryDependenceAnalysis& MD = getAnalysis();
+
// Find the non-local dependencies of the load
DenseMap deps;
- MD->getNonLocalDependency(L, deps);
+ MD.getNonLocalDependency(L, deps);
DenseMap repl;
@@ -854,7 +862,7 @@
for (SmallPtrSet::iterator I = p.begin(), E = p.end();
I != E; ++I) {
if ((*I)->getParent() == L->getParent()) {
- MD->removeInstruction(L);
+ MD.removeInstruction(L);
L->replaceAllUsesWith(*I);
toErase.push_back(L);
NumGVNLoad++;
@@ -868,7 +876,7 @@
SmallPtrSet visited;
Value* v = GetValueForBlock(L->getParent(), L, repl, true);
- MD->removeInstruction(L);
+ MD.removeInstruction(L);
L->replaceAllUsesWith(v);
toErase.push_back(L);
NumGVNLoad++;
@@ -889,8 +897,9 @@
LoadInst*& last = lastLoad[pointer];
// ... to a pointer that has been loaded from before...
+ MemoryDependenceAnalysis& MD = getAnalysis();
bool removedNonLocal = false;
- Instruction* dep = MD->getDependency(L);
+ Instruction* dep = MD.getDependency(L);
if (dep == MemoryDependenceAnalysis::NonLocal &&
L->getParent() != &L->getParent()->getParent()->getEntryBlock()) {
removedNonLocal = processNonLocalLoad(L, toErase);
@@ -913,7 +922,7 @@
if (StoreInst* S = dyn_cast(dep)) {
if (S->getPointerOperand() == pointer) {
// Remove it!
- MD->removeInstruction(L);
+ MD.removeInstruction(L);
L->replaceAllUsesWith(S->getOperand(0));
toErase.push_back(L);
@@ -930,7 +939,7 @@
break;
} else if (dep == last) {
// Remove it!
- MD->removeInstruction(L);
+ MD.removeInstruction(L);
L->replaceAllUsesWith(last);
toErase.push_back(L);
@@ -939,7 +948,7 @@
break;
} else {
- dep = MD->getDependency(L, dep);
+ dep = MD.getDependency(L, dep);
}
}
@@ -961,7 +970,7 @@
// If this load depends directly on an allocation, there isn't
// anything stored there; therefore, we can optimize this load
// to undef.
- MD->removeInstruction(L);
+ MD.removeInstruction(L);
L->replaceAllUsesWith(UndefValue::get(L->getType()));
toErase.push_back(L);
@@ -1009,7 +1018,8 @@
Value* repl = find_leader(currAvail, num);
// Remove it!
- MD->removeInstruction(I);
+ MemoryDependenceAnalysis& MD = getAnalysis();
+ MD.removeInstruction(I);
VN.erase(I);
I->replaceAllUsesWith(repl);
@@ -1027,9 +1037,9 @@
// function.
//
bool GVN::runOnFunction(Function& F) {
- DT = &getAnalysis();
- AA = &getAnalysis();
- MD = &getAnalysis();
+ VN.setAliasAnalysis(&getAnalysis());
+ VN.setMemDep(&getAnalysis());
+ VN.setDomTree(&getAnalysis());
bool changed = false;
bool shouldContinue = true;
@@ -1052,13 +1062,15 @@
bool changed_function = false;
+ DominatorTree &DT = getAnalysis();
+
SmallVector toErase;
DenseMap lastSeenLoad;
DenseMap numChildrenVisited;
// Top-down walk of the dominator tree
- for (df_iterator DI = df_begin(DT->getRootNode()),
- E = df_end(DT->getRootNode()); DI != E; ++DI) {
+ for (df_iterator DI = df_begin(DT.getRootNode()),
+ E = df_end(DT.getRootNode()); DI != E; ++DI) {
// Get the set to update for this block
ValueNumberedSet& currAvail = availableOut[DI->getBlock()];
From natebegeman at mac.com Mon May 12 15:16:56 2008
From: natebegeman at mac.com (Nate Begeman)
Date: Mon, 12 May 2008 20:16:56 -0000
Subject: [llvm-commits] [llvm] r50996 -
/llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp
Message-ID: <200805122016.m4CKGusI011348@zion.cs.uiuc.edu>
Author: sampo
Date: Mon May 12 15:16:55 2008
New Revision: 50996
URL: http://llvm.org/viewvc/llvm-project?rev=50996&view=rev
Log:
Pointer comparisons should use icmp, not vicmp
Modified:
llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp
Modified: llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp?rev=50996&r1=50995&r2=50996&view=diff
==============================================================================
--- llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp (original)
+++ llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp Mon May 12 15:16:55 2008
@@ -818,7 +818,7 @@
if (OpTy->isFloatingPoint())
V = ConstantExpr::getFCmp(Record[3], Op0, Op1);
- else if (OpTy->isInteger())
+ else if (OpTy->isInteger() || isa(OpTy))
V = ConstantExpr::getICmp(Record[3], Op0, Op1);
else if (OpTy->isFPOrFPVector())
V = ConstantExpr::getVFCmp(Record[3], Op0, Op1);
From gohman at apple.com Mon May 12 15:22:46 2008
From: gohman at apple.com (Dan Gohman)
Date: Mon, 12 May 2008 20:22:46 -0000
Subject: [llvm-commits] [llvm] r50997 -
/llvm/trunk/lib/Target/X86/X86InstrInfo.td
Message-ID: <200805122022.m4CKMkDh012549@zion.cs.uiuc.edu>
Author: djg
Date: Mon May 12 15:22:45 2008
New Revision: 50997
URL: http://llvm.org/viewvc/llvm-project?rev=50997&view=rev
Log:
Fix a copy+paste bug; pseudo-instructions shouldn't have
encoding information.
Modified:
llvm/trunk/lib/Target/X86/X86InstrInfo.td
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=50997&r1=50996&r2=50997&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Mon May 12 15:22:45 2008
@@ -2601,58 +2601,51 @@
// Atomic exchange and and, or, xor
let Constraints = "$val = $dst", Defs = [EFLAGS],
usesCustomDAGSchedInserter = 1 in {
-def ATOMAND32 : I<0xC1, MRMSrcMem,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
+def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
"#ATOMAND32 PSUEDO!",
- [(set GR32:$dst, (atomic_load_and addr:$ptr, GR32:$val))]>,
- TB, LOCK;
+ [(set GR32:$dst, (atomic_load_and addr:$ptr, GR32:$val))]>;
}
let Constraints = "$val = $dst", Defs = [EFLAGS],
usesCustomDAGSchedInserter = 1 in {
-def ATOMOR32 : I<0xC1, MRMSrcMem, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
+def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
"#ATOMOR32 PSUEDO!",
- [(set GR32:$dst, (atomic_load_or addr:$ptr, GR32:$val))]>,
- TB, LOCK;
+ [(set GR32:$dst, (atomic_load_or addr:$ptr, GR32:$val))]>;
}
let Constraints = "$val = $dst", Defs = [EFLAGS],
usesCustomDAGSchedInserter = 1 in {
-def ATOMXOR32 : I<0xC1, MRMSrcMem,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
+def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
"#ATOMXOR32 PSUEDO!",
- [(set GR32:$dst, (atomic_load_xor addr:$ptr, GR32:$val))]>,
- TB, LOCK;
+ [(set GR32:$dst, (atomic_load_xor addr:$ptr, GR32:$val))]>;
}
let Constraints = "$val = $dst", Defs = [EFLAGS],
usesCustomDAGSchedInserter = 1 in {
-def ATOMMIN32: I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
+def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
"#ATOMMIN32 PSUEDO!",
- [(set GR32:$dst, (atomic_load_min addr:$ptr, GR32:$val))]>,
- TB, LOCK;
+ [(set GR32:$dst, (atomic_load_min addr:$ptr, GR32:$val))]>;
}
let Constraints = "$val = $dst", Defs = [EFLAGS],
usesCustomDAGSchedInserter = 1 in {
-def ATOMMAX32: I<0xC1, MRMSrcMem, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
+def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
"#ATOMMAX32 PSUEDO!",
- [(set GR32:$dst, (atomic_load_max addr:$ptr, GR32:$val))]>,
- TB, LOCK;
+ [(set GR32:$dst, (atomic_load_max addr:$ptr, GR32:$val))]>;
}
let Constraints = "$val = $dst", Defs = [EFLAGS],
usesCustomDAGSchedInserter = 1 in {
-def ATOMUMIN32: I<0xC1, MRMSrcMem,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
+def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
"#ATOMUMIN32 PSUEDO!",
- [(set GR32:$dst, (atomic_load_umin addr:$ptr, GR32:$val))]>,
- TB, LOCK;
+ [(set GR32:$dst, (atomic_load_umin addr:$ptr, GR32:$val))]>;
}
let Constraints = "$val = $dst", Defs = [EFLAGS],
usesCustomDAGSchedInserter = 1 in {
-def ATOMUMAX32: I<0xC1, MRMSrcMem,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
+def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
"#ATOMUMAX32 PSUEDO!",
- [(set GR32:$dst, (atomic_load_umax addr:$ptr, GR32:$val))]>,
- TB, LOCK;
+ [(set GR32:$dst, (atomic_load_umax addr:$ptr, GR32:$val))]>;
}
//===----------------------------------------------------------------------===//
From clattner at apple.com Mon May 12 15:24:40 2008
From: clattner at apple.com (Chris Lattner)
Date: Mon, 12 May 2008 13:24:40 -0700
Subject: [llvm-commits] [llvm] r50985 - in /llvm/trunk:
docs/ include/llvm/ include/llvm/Support/
lib/AsmParser/ lib/Bitcode/Reader/ lib/Bitcode/Writer/ lib/VMCore/
In-Reply-To: <7F43E616-CAAE-4571-A7F2-0A5AC5A8791F@apple.com>
References: <200805121902.m4CJ22Nt020896@zion.cs.uiuc.edu>
<7F43E616-CAAE-4571-A7F2-0A5AC5A8791F@apple.com>
Message-ID: <6FD9ACF7-6A37-473A-B7AE-4AB0C6F5B59B@apple.com>
On May 12, 2008, at 1:01 PM, Dan Gohman wrote:
>> +vector of integer
>> result, of
>> +identical type as the values being compared. The most significant
>> bit in each
>> +element is 1 if the element-wise comparison evaluates to true, and
>> is 0
>> +otherwise. All other bits of the result are undefined. The
>> condition codes
>> +are evaluated identically to the 'icmp'
>> +instruction.
>
> It would be neat to overload the existing fcmp and icmp instead of
> introducing new instructions. But vicmp and vfcmp address a real
> need today without requiring the codegen to perform a bunch of magic
> on vectors of i1 to make this approach work well on current targets.
>
> Fortunately, nothing here rules out extending fcmp and icmp in the
> future :-).
Nate and I chatted about this, and decided the change would be really
invasive. The issue is that the vcmp instructions actually return a
vector of integers, not a vector of i1. This is pretty dissimilar to
how icmp/fcmp works.
-Chris
From dalej at apple.com Mon May 12 15:33:57 2008
From: dalej at apple.com (Dale Johannesen)
Date: Mon, 12 May 2008 20:33:57 -0000
Subject: [llvm-commits] [llvm] r50999 -
/llvm/trunk/lib/CodeGen/BranchFolding.cpp
Message-ID: <200805122033.m4CKXvpU001380@zion.cs.uiuc.edu>
Author: johannes
Date: Mon May 12 15:33:57 2008
New Revision: 50999
URL: http://llvm.org/viewvc/llvm-project?rev=50999&view=rev
Log:
Further rework of tail merge algorithm. Not quite
semantically identical, but little difference in
either results or execution speed; but it's much
easier to read, at least IMO.
Modified:
llvm/trunk/lib/CodeGen/BranchFolding.cpp
Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/BranchFolding.cpp?rev=50999&r1=50998&r2=50999&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/BranchFolding.cpp (original)
+++ llvm/trunk/lib/CodeGen/BranchFolding.cpp Mon May 12 15:33:57 2008
@@ -74,10 +74,13 @@
unsigned ComputeSameTails(unsigned CurHash, unsigned minCommonTailLength);
void RemoveBlocksWithHash(unsigned CurHash, MachineBasicBlock* SuccBB,
MachineBasicBlock* PredBB);
+ unsigned CreateCommonTailOnlyBlock(MachineBasicBlock *&PredBB,
+ unsigned maxCommonTailLength);
typedef std::pair MergePotentialsElt;
typedef std::vector::iterator MPIterator;
std::vector MergePotentials;
+
typedef std::pair SameTailElt;
std::vector SameTails;
@@ -422,42 +425,6 @@
return Time;
}
-/// ShouldSplitFirstBlock - We need to either split MBB1 at MBB1I or MBB2 at
-/// MBB2I and then insert an unconditional branch in the other block. Determine
-/// which is the best to split
-static bool ShouldSplitFirstBlock(MachineBasicBlock *MBB1,
- MachineBasicBlock::iterator MBB1I,
- MachineBasicBlock *MBB2,
- MachineBasicBlock::iterator MBB2I,
- MachineBasicBlock *PredBB) {
- // If one block is the entry block, split the other one; we can't generate
- // a branch to the entry block, as its label is not emitted.
- MachineBasicBlock *Entry = MBB1->getParent()->begin();
- if (MBB1 == Entry)
- return false;
- if (MBB2 == Entry)
- return true;
-
- // If one block falls through into the common successor, choose that
- // one to split; it is one instruction less to do that.
- if (PredBB) {
- if (MBB1 == PredBB)
- return true;
- else if (MBB2 == PredBB)
- return false;
- }
- // TODO: if we had some notion of which block was hotter, we could split
- // the hot block, so it is the fall-through. Since we don't have profile info
- // make a decision based on which will hurt most to split.
- unsigned MBB1Time = EstimateRuntime(MBB1->begin(), MBB1I);
- unsigned MBB2Time = EstimateRuntime(MBB2->begin(), MBB2I);
-
- // If the MBB1 prefix takes "less time" to run than the MBB2 prefix, split the
- // MBB1 block so it falls through. This will penalize the MBB2 path, but will
- // have a lower overall impact on the program execution.
- return MBB1Time < MBB2Time;
-}
-
// CurMBB needs to add an unconditional branch to SuccMBB (we removed these
// branches temporarily for tail merging). In the case where CurMBB ends
// with a conditional branch to the next block, optimize by reversing the
@@ -565,6 +532,44 @@
}
}
+/// CreateCommonTailOnlyBlock - None of the blocks to be tail-merged consist
+/// only of the common tail. Create a block that does by splitting one.
+unsigned BranchFolder::CreateCommonTailOnlyBlock(MachineBasicBlock *&PredBB,
+ unsigned maxCommonTailLength) {
+ unsigned i, commonTailIndex;
+ unsigned TimeEstimate = ~0U;
+ for (i=0, commonTailIndex=0; isecond==PredBB) {
+ commonTailIndex = i;
+ break;
+ }
+ // Otherwise, make a (fairly bogus) choice based on estimate of
+ // how long it will take the various blocks to execute.
+ unsigned t = EstimateRuntime(SameTails[i].first->second->begin(),
+ SameTails[i].second);
+ if (t<=TimeEstimate) {
+ TimeEstimate = t;
+ commonTailIndex = i;
+ }
+ }
+
+ MachineBasicBlock::iterator BBI = SameTails[commonTailIndex].second;
+ MachineBasicBlock *MBB = SameTails[commonTailIndex].first->second;
+
+ DOUT << "\nSplitting " << MBB->getNumber() << ", size " <<
+ maxCommonTailLength;
+
+ MachineBasicBlock *newMBB = SplitMBBAt(*MBB, BBI);
+ SameTails[commonTailIndex].first->second = newMBB;
+ SameTails[commonTailIndex].second = newMBB->begin();
+ // If we split PredBB, newMBB is the new predecessor.
+ if (PredBB==MBB)
+ PredBB = newMBB;
+
+ return commonTailIndex;
+}
+
// See if any of the blocks in MergePotentials (which all have a common single
// successor, or all have no successor) can be tail-merged. If there is a
// successor, any blocks in MergePotentials that are not tail-merged and
@@ -575,10 +580,6 @@
bool BranchFolder::TryMergeBlocks(MachineBasicBlock *SuccBB,
MachineBasicBlock* PredBB) {
- // We cannot jump to the entry block, which affects various choices below.
- MachineBasicBlock *Entry = MergePotentials.begin()->second->
- getParent()->begin();
-
// It doesn't make sense to save a single instruction since tail merging
// will add a jump.
// FIXME: Ask the target to provide the threshold?
@@ -608,78 +609,43 @@
}
// If one of the blocks is the entire common tail (and not the entry
- // block, which we can't jump to), treat all blocks with this same
- // tail at once.
- unsigned int i;
- for (i=0; isecond->
+ getParent()->begin();
+ unsigned int commonTailIndex, i;
+ for (commonTailIndex=SameTails.size(), i=0; isecond;
- if (MBB->begin() == SameTails[i].second && MBB != Entry)
- break;
- }
- if (i!=SameTails.size()) {
- MachineBasicBlock *MBB = SameTails[i].first->second;
- // MBB is common tail. Adjust all other BB's to jump to this one.
- // Traversal must be forwards so erases work.
- DOUT << "\nUsing common tail " << MBB->getNumber() << " for ";
- for (unsigned int j=0; jsecond->getNumber() << ",";
- // Hack the end off BB j, making it jump to BB i instead.
- ReplaceTailWithBranchTo(SameTails[j].second, MBB);
- // This modifies BB j, so remove it from the worklist.
- MergePotentials.erase(SameTails[j].first);
+ if (MBB->begin() == SameTails[i].second && MBB != EntryBB) {
+ commonTailIndex = i;
+ if (MBB==PredBB)
+ break;
}
- DOUT << "\n";
- // We leave i in the worklist in case there are other blocks that
- // match it with a smaller number of instructions.
- MadeChange = true;
- continue;
}
- // Otherwise, merge the 2 blocks in SameTails that are latest in
- // MergePotentials; these are at indices 0 and 1 in SameTails.
- MachineBasicBlock::iterator BBI1 = (SameTails[0]).second;
- MachineBasicBlock::iterator BBI2 = (SameTails[1]).second;
- MachineBasicBlock *MBB1 = (SameTails[0]).first->second;
- MachineBasicBlock *MBB2 = (SameTails[1]).first->second;
-
- DOUT << "\nMerging " << MBB1->getNumber() << "," <<
- MBB2->getNumber() << ", size " << maxCommonTailLength;
-
- // Neither block is the entire common tail; split the tail of one block
- // to make it redundant with the other tail. We cannot jump to the
- // entry block, so if one block is the entry block, split the other one.
-
- // The second half of the split block will remain in SameTails, and will
- // consist entirely of common code. Thus in the case where there are
- // multiple blocks that would all need to be split, the next iteration of
- // the outer loop will handle all the rest of them.
-
- // Decide whether we want to split MBB1 or MBB2.
- if (ShouldSplitFirstBlock(MBB1, BBI1, MBB2, BBI2, PredBB)) {
- MBB1 = SplitMBBAt(*MBB1, BBI1);
- BBI1 = MBB1->begin();
- SameTails[0].first->second = MBB1;
- } else {
- MBB2 = SplitMBBAt(*MBB2, BBI2);
- BBI2 = MBB2->begin();
- SameTails[1].first->second = MBB2;
- }
-
- if (MBB2->begin() == BBI2 && MBB2 != Entry) {
- // Hack the end off MBB1, making it jump to MBB2 instead.
- ReplaceTailWithBranchTo(BBI1, MBB2);
- // This modifies MBB1, so remove it from the worklist.
- MergePotentials.erase(SameTails[0].first);
- } else {
- assert(MBB1->begin() == BBI1 && MBB1 != Entry &&
- "Didn't split block correctly?");
- // Hack the end off MBB2, making it jump to MBB1 instead.
- ReplaceTailWithBranchTo(BBI2, MBB1);
- // This modifies MBB2, so remove it from the worklist.
- MergePotentials.erase(SameTails[1].first);
+ if (commonTailIndex==SameTails.size()) {
+ // None of the blocks consist entirely of the common tail.
+ // Split a block so that one does.
+ commonTailIndex = CreateCommonTailOnlyBlock(PredBB, maxCommonTailLength);
}
+
+ MachineBasicBlock *MBB = SameTails[commonTailIndex].first->second;
+ // MBB is common tail. Adjust all other BB's to jump to this one.
+ // Traversal must be forwards so erases work.
+ DOUT << "\nUsing common tail " << MBB->getNumber() << " for ";
+ for (unsigned int i=0; isecond->getNumber() << ",";
+ // Hack the end off BB i, making it jump to BB commonTailIndex instead.
+ ReplaceTailWithBranchTo(SameTails[i].second, MBB);
+ // BB i is no longer a predecessor of SuccBB; remove it from the worklist.
+ MergePotentials.erase(SameTails[i].first);
+ }
+ DOUT << "\n";
+ // We leave commonTailIndex in the worklist in case there are other blocks
+ // that match it with a smaller number of instructions.
MadeChange = true;
}
return MadeChange;
@@ -782,12 +748,11 @@
if (MergePotentials.size() >= 2)
MadeChange |= TryMergeBlocks(I, PredBB);
// Reinsert an unconditional branch if needed.
- // The 1 below can be either an original single predecessor, or a result
- // of removing blocks in TryMergeBlocks.
+ // The 1 below can occur as a result of removing blocks in TryMergeBlocks.
PredBB = prior(I); // this may have been changed in TryMergeBlocks
if (MergePotentials.size()==1 &&
- (MergePotentials.begin())->second != PredBB)
- FixTail((MergePotentials.begin())->second, I, TII);
+ MergePotentials.begin()->second != PredBB)
+ FixTail(MergePotentials.begin()->second, I, TII);
}
}
return MadeChange;
@@ -827,7 +792,8 @@
///
bool BranchFolder::CanFallThrough(MachineBasicBlock *CurBB,
bool BranchUnAnalyzable,
- MachineBasicBlock *TBB, MachineBasicBlock *FBB,
+ MachineBasicBlock *TBB,
+ MachineBasicBlock *FBB,
const std::vector &Cond) {
MachineFunction::iterator Fallthrough = CurBB;
++Fallthrough;
From natebegeman at mac.com Mon May 12 15:33:53 2008
From: natebegeman at mac.com (Nate Begeman)
Date: Mon, 12 May 2008 20:33:53 -0000
Subject: [llvm-commits] [llvm] r50998 -
/llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp
Message-ID: <200805122033.m4CKXrPZ001366@zion.cs.uiuc.edu>
Author: sampo
Date: Mon May 12 15:33:52 2008
New Revision: 50998
URL: http://llvm.org/viewvc/llvm-project?rev=50998&view=rev
Log:
Simplify some checks
Modified:
llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp
Modified: llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp?rev=50998&r1=50997&r2=50998&view=diff
==============================================================================
--- llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp (original)
+++ llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp Mon May 12 15:33:52 2008
@@ -818,7 +818,7 @@
if (OpTy->isFloatingPoint())
V = ConstantExpr::getFCmp(Record[3], Op0, Op1);
- else if (OpTy->isInteger() || isa(OpTy))
+ else if (!isa(OpTy))
V = ConstantExpr::getICmp(Record[3], Op0, Op1);
else if (OpTy->isFPOrFPVector())
V = ConstantExpr::getVFCmp(Record[3], Op0, Op1);
@@ -1359,10 +1359,10 @@
OpNum+1 != Record.size())
return Error("Invalid CMP record");
- if (LHS->getType()->isInteger() || isa(LHS->getType()))
- I = new ICmpInst((ICmpInst::Predicate)Record[OpNum], LHS, RHS);
- else if (LHS->getType()->isFloatingPoint())
+ if (LHS->getType()->isFloatingPoint())
I = new FCmpInst((FCmpInst::Predicate)Record[OpNum], LHS, RHS);
+ else if (!isa(LHS->getType()))
+ I = new ICmpInst((ICmpInst::Predicate)Record[OpNum], LHS, RHS);
else if (LHS->getType()->isFPOrFPVector())
I = new VFCmpInst((FCmpInst::Predicate)Record[OpNum], LHS, RHS);
else
From natebegeman at mac.com Mon May 12 15:34:32 2008
From: natebegeman at mac.com (Nate Begeman)
Date: Mon, 12 May 2008 20:34:32 -0000
Subject: [llvm-commits] [llvm] r51000 - in /llvm/trunk/lib/Target/X86:
X86ISelLowering.cpp X86ISelLowering.h X86InstrSSE.td
Message-ID: <200805122034.m4CKYXhG001415@zion.cs.uiuc.edu>
Author: sampo
Date: Mon May 12 15:34:32 2008
New Revision: 51000
URL: http://llvm.org/viewvc/llvm-project?rev=51000&view=rev
Log:
Initial X86 codegen support for VSETCC.
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/lib/Target/X86/X86ISelLowering.h
llvm/trunk/lib/Target/X86/X86InstrSSE.td
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=51000&r1=50999&r2=51000&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon May 12 15:34:32 2008
@@ -530,6 +530,7 @@
setOperationAction(ISD::ROTL, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::ROTR, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::BSWAP, (MVT::ValueType)VT, Expand);
+ setOperationAction(ISD::VSETCC, (MVT::ValueType)VT, Expand);
}
if (Subtarget->hasMMX()) {
@@ -614,6 +615,7 @@
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
+ setOperationAction(ISD::VSETCC, MVT::v4f32, Legal);
}
if (Subtarget->hasSSE2()) {
@@ -639,6 +641,12 @@
setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
+ setOperationAction(ISD::VSETCC, MVT::v2f64, Legal);
+ setOperationAction(ISD::VSETCC, MVT::v16i8, Legal);
+ setOperationAction(ISD::VSETCC, MVT::v8i16, Legal);
+ setOperationAction(ISD::VSETCC, MVT::v4i32, Legal);
+ setOperationAction(ISD::VSETCC, MVT::v2i64, Legal);
+
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
@@ -686,6 +694,7 @@
setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
+
}
if (Subtarget->hasSSE41()) {
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=51000&r1=50999&r2=51000&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Mon May 12 15:34:32 2008
@@ -565,7 +565,6 @@
MachineBasicBlock *EmitAtomicMinMaxWithCustomInserter(MachineInstr *BInstr,
MachineBasicBlock *BB,
unsigned cmovOpc);
-
};
}
Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=51000&r1=50999&r2=51000&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Mon May 12 15:34:32 2008
@@ -161,6 +161,22 @@
return getI32Imm(N->getValue() >> 3);
}]>;
+def SSE_CC_imm : SDNodeXFormget()) {
+ default: Val = 0; assert(0 && "Unexpected CondCode"); break;
+ case ISD::SETOEQ: Val = 0; break;
+ case ISD::SETOLT: Val = 1; break;
+ case ISD::SETOLE: Val = 2; break;
+ case ISD::SETUO: Val = 3; break;
+ case ISD::SETONE: Val = 4; break;
+ case ISD::SETOGE: Val = 5; break;
+ case ISD::SETOGT: Val = 6; break;
+ case ISD::SETO: Val = 7; break;
+ }
+ return getI8Imm(Val);
+}]>;
+
// SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
// SHUFP* etc. imm.
def SHUFFLE_get_shuf_imm : SDNodeXForm;
+
//===----------------------------------------------------------------------===//
// SSE scalar FP Instructions
//===----------------------------------------------------------------------===//
@@ -855,16 +872,20 @@
let Constraints = "$src1 = $dst" in {
def CMPPSrri : PSIi8<0xC2, MRMSrcReg,
- (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
- "cmp${cc}ps\t{$src, $dst|$dst, $src}",
- [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
- VR128:$src, imm:$cc))]>;
+ (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
+ "cmp${cc}ps\t{$src, $dst|$dst, $src}",
+ [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
+ VR128:$src, imm:$cc))]>;
def CMPPSrmi : PSIi8<0xC2, MRMSrcMem,
- (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
- "cmp${cc}ps\t{$src, $dst|$dst, $src}",
- [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
- (load addr:$src), imm:$cc))]>;
-}
+ (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
+ "cmp${cc}ps\t{$src, $dst|$dst, $src}",
+ [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
+ (load addr:$src), imm:$cc))]>;
+}
+def : Pat<(v4i32 (vsetcc (v4f32 VR128:$src1), VR128:$src2, cond:$cc)),
+ (CMPPSrri VR128:$src1, VR128:$src2, (SSE_CC_imm cond:$cc))>;
+def : Pat<(v4i32 (vsetcc (v4f32 VR128:$src1), (memop addr:$src2), cond:$cc)),
+ (CMPPSrmi VR128:$src1, addr:$src2, (SSE_CC_imm cond:$cc))>;
// Shuffle and unpack instructions
let Constraints = "$src1 = $dst" in {
@@ -1675,13 +1696,17 @@
(outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
"cmp${cc}pd\t{$src, $dst|$dst, $src}",
[(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
- VR128:$src, imm:$cc))]>;
+ VR128:$src, imm:$cc))]>;
def CMPPDrmi : PDIi8<0xC2, MRMSrcMem,
(outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
"cmp${cc}pd\t{$src, $dst|$dst, $src}",
[(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
- (load addr:$src), imm:$cc))]>;
+ (load addr:$src), imm:$cc))]>;
}
+def : Pat<(v2i64 (vsetcc (v2f64 VR128:$src1), VR128:$src2, cond:$cc)),
+ (CMPPDrri VR128:$src1, VR128:$src2, (SSE_CC_imm cond:$cc))>;
+def : Pat<(v2i64 (vsetcc (v2f64 VR128:$src1), (memop addr:$src2), cond:$cc)),
+ (CMPPDrmi VR128:$src1, addr:$src2, (SSE_CC_imm cond:$cc))>;
// Shuffle and unpack instructions
let Constraints = "$src1 = $dst" in {
From isanbard at gmail.com Mon May 12 15:54:34 2008
From: isanbard at gmail.com (Bill Wendling)
Date: Mon, 12 May 2008 20:54:34 -0000
Subject: [llvm-commits] [llvm] r51001 - in /llvm/trunk:
include/llvm/Target/TargetInstrInfo.h lib/Target/X86/X86InstrInfo.cpp
lib/Target/X86/X86InstrInfo.h
Message-ID: <200805122054.m4CKsaL7015649@zion.cs.uiuc.edu>
Author: void
Date: Mon May 12 15:54:26 2008
New Revision: 51001
URL: http://llvm.org/viewvc/llvm-project?rev=51001&view=rev
Log:
Constify the machine instruction passed into the
"is{Trivially,Really}ReMaterializable" methods.
Modified:
llvm/trunk/include/llvm/Target/TargetInstrInfo.h
llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
llvm/trunk/lib/Target/X86/X86InstrInfo.h
Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=51001&r1=51000&r2=51001&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Mon May 12 15:54:26 2008
@@ -67,7 +67,7 @@
/// isTriviallyReMaterializable - Return true if the instruction is trivially
/// rematerializable, meaning it has no side effects and requires no operands
/// that aren't always available.
- bool isTriviallyReMaterializable(MachineInstr *MI) const {
+ bool isTriviallyReMaterializable(const MachineInstr *MI) const {
return MI->getDesc().isRematerializable() &&
isReallyTriviallyReMaterializable(MI);
}
@@ -81,7 +81,7 @@
/// return false if the instruction has any side effects other than
/// producing a value, or if it requres any address registers that are not
/// always available.
- virtual bool isReallyTriviallyReMaterializable(MachineInstr *MI) const {
+ virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI) const {
return true;
}
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=51001&r1=51000&r2=51001&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Mon May 12 15:54:26 2008
@@ -760,7 +760,8 @@
return TM.getSubtarget().GVRequiresExtraLoad(GV, TM, false);
}
-bool X86InstrInfo::isReallyTriviallyReMaterializable(MachineInstr *MI) const {
+bool
+X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI) const {
switch (MI->getOpcode()) {
default: break;
case X86::MOV8rm:
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=51001&r1=51000&r2=51001&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.h (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.h Mon May 12 15:54:26 2008
@@ -260,7 +260,7 @@
unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
- bool isReallyTriviallyReMaterializable(MachineInstr *MI) const;
+ bool isReallyTriviallyReMaterializable(const MachineInstr *MI) const;
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
unsigned DestReg, const MachineInstr *Orig) const;
From gohman at apple.com Mon May 12 16:31:11 2008
From: gohman at apple.com (Dan Gohman)
Date: Mon, 12 May 2008 14:31:11 -0700
Subject: [llvm-commits] PATCH for PIC16 target.
In-Reply-To:
References:
Message-ID:
On May 8, 2008, at 5:13 AM, Sanjiv.Gupta at microchip.com wrote:
> Please find attached files for Microchip's PIC16 backend.
> These files are to be placed under a new directory lib/Target/PIC16.
> Though the current PIC16 backend can handle few very elementary cases
> for code generation, these files enable basic llvm framework for PIC16
> target.
>
> The code builds on linux/mingw platforms without warnings/errors.
>
> I will send a separate patch for configure.
Ok, I've read through all the files. They look very straight-forward.
I have a
number of minor comments below, but these files look fine to check in
whenever you're ready.
Along the way I saw a reference to A5.1.3. Is this in a document
that's publically available? Can you put a link to it somewhere?
In PIC16RegisterInfo.cpp:
> // This file contains the PIC16 implementation of the MRegisterInfo
class.
The code is right, but the comment still says MRegisterInfo. It should
say TargetRegisterInfo.
In PIC16TargetMachine.h:
> #include "llvm/Target/TargetMachine.h"
> #include "llvm/Target/TargetData.h"
> #include "PIC16InstrInfo.h"
> #include "PIC16Subtarget.h"
> #include "PIC16ISelLowering.h"
> #include "llvm/Target/TargetFrameInfo.h"
Please sort the include-files by subdirectory.
> namespace llvm {
>
> /// PIC16TargetMachine
> ///
> class PIC16TargetMachine : public LLVMTargetMachine {
> PIC16Subtarget Subtarget;
> [...]
> };
> } // end namespace llvm
Watch out for spacing.
In PIC16AsmPrinter.cpp:
> if (MO1.isRegister())
> {
> if(strcmp(TM.getRegisterInfo()->get(MO1.getReg()).Name,
"SP")==0)
> {
LLVM style has the opening brace on the same line as the if.
In PIC16InstrInfo.h:
> PIC16InstrInfo(PIC16TargetMachine &TM);
This misses an explicit keyword.
In PIC16RegisterInfo.h:
> PIC16RegisterInfo(const TargetInstrInfo &tii);
This misses an explicit keyword.
In PIC16TargetAsmInfo.h:
> PIC16TargetAsmInfo(const PIC16TargetMachine &TM);
This misses an explicit keyword.
Dan
From isanbard at gmail.com Mon May 12 17:15:05 2008
From: isanbard at gmail.com (Bill Wendling)
Date: Mon, 12 May 2008 22:15:05 -0000
Subject: [llvm-commits] [llvm] r51004 -
/llvm/trunk/lib/CodeGen/PHIElimination.cpp
Message-ID: <200805122215.m4CMF5AA004933@zion.cs.uiuc.edu>
Author: void
Date: Mon May 12 17:15:05 2008
New Revision: 51004
URL: http://llvm.org/viewvc/llvm-project?rev=51004&view=rev
Log:
Constify isSourceDefinedByImplicitDef function. Otherwise, just formatting
changes that don't change functionality.
Modified:
llvm/trunk/lib/CodeGen/PHIElimination.cpp
Modified: llvm/trunk/lib/CodeGen/PHIElimination.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PHIElimination.cpp?rev=51004&r1=51003&r2=51004&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/PHIElimination.cpp (original)
+++ llvm/trunk/lib/CodeGen/PHIElimination.cpp Mon May 12 17:15:05 2008
@@ -127,11 +127,11 @@
return true;
}
-static bool isSourceDefinedByImplicitDef(MachineInstr *MPhi,
- MachineRegisterInfo *MRI) {
+static bool isSourceDefinedByImplicitDef(const MachineInstr *MPhi,
+ const MachineRegisterInfo *MRI) {
for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2) {
unsigned SrcReg = MPhi->getOperand(i).getReg();
- MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
+ const MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
if (!DefMI || DefMI->getOpcode() != TargetInstrInfo::IMPLICIT_DEF)
return false;
}
@@ -142,6 +142,7 @@
/// under the assuption that it needs to be lowered in a way that supports
/// atomic execution of PHIs. This lowering method is always correct all of the
/// time.
+///
void PNE::LowerAtomicPHINode(MachineBasicBlock &MBB,
MachineBasicBlock::iterator AfterPHIsIt) {
// Unlink the PHI node from the basic block, but don't delete the PHI yet.
@@ -155,10 +156,9 @@
const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
unsigned IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
- // Insert a register to register copy in the top of the current block (but
+ // Insert a register to register copy at the top of the current block (but
// after any remaining phi nodes) which copies the new incoming register
// into the phi node destination.
- //
const TargetInstrInfo *TII = MF.getTarget().getInstrInfo();
if (isSourceDefinedByImplicitDef(MPhi, MRI))
// If all sources of a PHI node are implicit_def, just emit an implicit_def
@@ -167,7 +167,7 @@
else
TII->copyRegToReg(MBB, AfterPHIsIt, DestReg, IncomingReg, RC, RC);
- // Update live variable information if there is any...
+ // Update live variable information if there is any.
LiveVariables *LV = getAnalysisToUpdate();
if (LV) {
MachineInstr *PHICopy = prior(AfterPHIsIt);
@@ -177,15 +177,13 @@
// Add information to LiveVariables to know that the incoming value is
// killed. Note that because the value is defined in several places (once
- // each for each incoming block), the "def" block and instruction fields
- // for the VarInfo is not filled in.
- //
+ // each for each incoming block), the "def" block and instruction fields for
+ // the VarInfo is not filled in.
LV->addVirtualRegisterKilled(IncomingReg, PHICopy);
- // Since we are going to be deleting the PHI node, if it is the last use
- // of any registers, or if the value itself is dead, we need to move this
+ // Since we are going to be deleting the PHI node, if it is the last use of
+ // any registers, or if the value itself is dead, we need to move this
// information over to the new copy we just inserted.
- //
LV->removeVirtualRegistersKilled(MPhi);
// If the result is dead, update LV.
@@ -197,41 +195,39 @@
LV->getVarInfo(IncomingReg).UsedBlocks[MBB.getNumber()] = true;
}
- // Adjust the VRegPHIUseCount map to account for the removal of this PHI
- // node.
+ // Adjust the VRegPHIUseCount map to account for the removal of this PHI node.
for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2)
--VRegPHIUseCount[BBVRegPair(MPhi->getOperand(i + 1).getMBB(),
MPhi->getOperand(i).getReg())];
- // Now loop over all of the incoming arguments, changing them to copy into
- // the IncomingReg register in the corresponding predecessor basic block.
- //
+ // Now loop over all of the incoming arguments, changing them to copy into the
+ // IncomingReg register in the corresponding predecessor basic block.
SmallPtrSet MBBsInsertedInto;
for (int i = NumSrcs - 1; i >= 0; --i) {
unsigned SrcReg = MPhi->getOperand(i*2+1).getReg();
assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
"Machine PHI Operands must all be virtual registers!");
- // If source is defined by an implicit def, there is no need to insert
- // a copy unless it's the only source.
+ // If source is defined by an implicit def, there is no need to insert a
+ // copy unless it's the only source.
MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
if (DefMI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
ImpDefs.insert(DefMI);
continue;
}
- // Get the MachineBasicBlock equivalent of the BasicBlock that is the
- // source path the PHI.
+ // Get the MachineBasicBlock equivalent of the BasicBlock that is the source
+ // path the PHI.
MachineBasicBlock &opBlock = *MPhi->getOperand(i*2+2).getMBB();
// Check to make sure we haven't already emitted the copy for this block.
- // This can happen because PHI nodes may have multiple entries for the
- // same basic block.
+ // This can happen because PHI nodes may have multiple entries for the same
+ // basic block.
if (!MBBsInsertedInto.insert(&opBlock))
continue; // If the copy has already been emitted, we're done.
- // Find a safe location to insert the copy, this may be the first
- // terminator in the block (or end()).
+ // Find a safe location to insert the copy, this may be the first terminator
+ // in the block (or end()).
MachineBasicBlock::iterator InsertPos = opBlock.getFirstTerminator();
// Insert the copy.
@@ -240,26 +236,24 @@
// Now update live variable information if we have it. Otherwise we're done
if (!LV) continue;
- // We want to be able to insert a kill of the register if this PHI
- // (aka, the copy we just inserted) is the last use of the source
- // value. Live variable analysis conservatively handles this by
- // saying that the value is live until the end of the block the PHI
- // entry lives in. If the value really is dead at the PHI copy, there
- // will be no successor blocks which have the value live-in.
- //
- // Check to see if the copy is the last use, and if so, update the
- // live variables information so that it knows the copy source
- // instruction kills the incoming value.
+ // We want to be able to insert a kill of the register if this PHI (aka, the
+ // copy we just inserted) is the last use of the source value. Live
+ // variable analysis conservatively handles this by saying that the value is
+ // live until the end of the block the PHI entry lives in. If the value
+ // really is dead at the PHI copy, there will be no successor blocks which
+ // have the value live-in.
//
+ // Check to see if the copy is the last use, and if so, update the live
+ // variables information so that it knows the copy source instruction kills
+ // the incoming value.
LiveVariables::VarInfo &InRegVI = LV->getVarInfo(SrcReg);
InRegVI.UsedBlocks[opBlock.getNumber()] = true;
- // Loop over all of the successors of the basic block, checking to see
- // if the value is either live in the block, or if it is killed in the
- // block. Also check to see if this register is in use by another PHI
- // node which has not yet been eliminated. If so, it will be killed
- // at an appropriate point later.
- //
+ // Loop over all of the successors of the basic block, checking to see if
+ // the value is either live in the block, or if it is killed in the block.
+ // Also check to see if this register is in use by another PHI node which
+ // has not yet been eliminated. If so, it will be killed at an appropriate
+ // point later.
// Is it used by any PHI instructions in this block?
bool ValueIsLive = VRegPHIUseCount[BBVRegPair(&opBlock, SrcReg)] != 0;
@@ -316,12 +310,11 @@
}
}
- // Okay, if we now know that the value is not live out of the block,
- // we can add a kill marker in this block saying that it kills the incoming
- // value!
+ // Okay, if we now know that the value is not live out of the block, we can
+ // add a kill marker in this block saying that it kills the incoming value!
if (!ValueIsLive) {
// In our final twist, we have to decide which instruction kills the
- // register. In most cases this is the copy, however, the first
+ // register. In most cases this is the copy, however, the first
// terminator instruction at the end of the block may also use the value.
// In this case, we should mark *it* as being the killing block, not the
// copy.
From dalej at apple.com Mon May 12 17:53:13 2008
From: dalej at apple.com (Dale Johannesen)
Date: Mon, 12 May 2008 22:53:13 -0000
Subject: [llvm-commits] [llvm] r51006 -
/llvm/trunk/lib/CodeGen/BranchFolding.cpp
Message-ID: <200805122253.m4CMrD8w014161@zion.cs.uiuc.edu>
Author: johannes
Date: Mon May 12 17:53:12 2008
New Revision: 51006
URL: http://llvm.org/viewvc/llvm-project?rev=51006&view=rev
Log:
Be more aggressive about tail-merging small blocks
if those blocks consist entirely of common instructions;
merging will not add an extra branch in this case.
Modified:
llvm/trunk/lib/CodeGen/BranchFolding.cpp
Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/BranchFolding.cpp?rev=51006&r1=51005&r2=51006&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/BranchFolding.cpp (original)
+++ llvm/trunk/lib/CodeGen/BranchFolding.cpp Mon May 12 17:53:12 2008
@@ -495,7 +495,18 @@
CurMPIter->second,
I->second,
TrialBBI1, TrialBBI2);
- if (CommonTailLen >= minCommonTailLength) {
+ // If we will have to split a block, there should be at least
+ // minCommonTailLength instructions in common; if not, at worst
+ // we will be replacing a fallthrough into the common tail with a
+ // branch, which at worst breaks even with falling through into
+ // the duplicated common tail, so 1 instruction in common is enough.
+ // We will always pick a block we do not have to split as the common
+ // tail if there is one.
+ // (Empty blocks will get forwarded and need not be considered.)
+ if (CommonTailLen >= minCommonTailLength ||
+ (CommonTailLen > 0 &&
+ (TrialBBI1==CurMPIter->second->begin() ||
+ TrialBBI2==I->second->begin()))) {
if (CommonTailLen > maxCommonTailLength) {
SameTails.clear();
maxCommonTailLength = CommonTailLen;
From dalej at apple.com Mon May 12 17:59:55 2008
From: dalej at apple.com (Dale Johannesen)
Date: Mon, 12 May 2008 22:59:55 -0000
Subject: [llvm-commits] [llvm] r51007 -
/llvm/trunk/test/CodeGen/X86/2008-05-12-tailmerge-5.ll
Message-ID: <200805122259.m4CMxtVE015970@zion.cs.uiuc.edu>
Author: johannes
Date: Mon May 12 17:59:44 2008
New Revision: 51007
URL: http://llvm.org/viewvc/llvm-project?rev=51007&view=rev
Log:
New test for tail merging
Added:
llvm/trunk/test/CodeGen/X86/2008-05-12-tailmerge-5.ll
Added: llvm/trunk/test/CodeGen/X86/2008-05-12-tailmerge-5.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-05-12-tailmerge-5.ll?rev=51007&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2008-05-12-tailmerge-5.ll (added)
+++ llvm/trunk/test/CodeGen/X86/2008-05-12-tailmerge-5.ll Mon May 12 17:59:44 2008
@@ -0,0 +1,145 @@
+; RUN: llvm-as < %s | llc | grep abort | count 1
+; Calls to abort should all be merged
+
+; ModuleID = '5898899.c'
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-apple-darwin8"
+ %struct.BoundaryAlignment = type { [3 x i8], i8, i16, i16, i8, [2 x i8] }
+
+define void @passing2(i64 %str.0, i64 %str.1, i16 signext %s, i32 %j, i8 signext %c, i16 signext %t, i16 signext %u, i8 signext %d) nounwind {
+entry:
+ %str_addr = alloca %struct.BoundaryAlignment ; <%struct.BoundaryAlignment*> [#uses=7]
+ %s_addr = alloca i16 ; [#uses=1]
+ %j_addr = alloca i32 ; [#uses=2]
+ %c_addr = alloca i8 ; [#uses=2]
+ %t_addr = alloca i16 ; [#uses=2]
+ %u_addr = alloca i16 ; [#uses=2]
+ %d_addr = alloca i8 ; [#uses=2]
+ %"alloca point" = bitcast i32 0 to i32 ; [#uses=0]
+ %tmp = bitcast %struct.BoundaryAlignment* %str_addr to { i64, i64 }* ; <{ i64, i64 }*> [#uses=1]
+ %tmp1 = getelementptr { i64, i64 }* %tmp, i32 0, i32 0 ; [#uses=1]
+ store i64 %str.0, i64* %tmp1
+ %tmp2 = bitcast %struct.BoundaryAlignment* %str_addr to { i64, i64 }* ; <{ i64, i64 }*> [#uses=1]
+ %tmp3 = getelementptr { i64, i64 }* %tmp2, i32 0, i32 1 ; [#uses=1]
+ %bc = bitcast i64* %tmp3 to i8* ; [#uses=2]
+ %byte = trunc i64 %str.1 to i8 ; [#uses=1]
+ store i8 %byte, i8* %bc
+ %shft = lshr i64 %str.1, 8 ; [#uses=2]
+ %Loc = getelementptr i8* %bc, i32 1 ; [#uses=2]
+ %byte4 = trunc i64 %shft to i8 ; [#uses=1]
+ store i8 %byte4, i8* %Loc
+ %shft5 = lshr i64 %shft, 8 ; [#uses=2]
+ %Loc6 = getelementptr i8* %Loc, i32 1 ; [#uses=2]
+ %byte7 = trunc i64 %shft5 to i8 ; [#uses=1]
+ store i8 %byte7, i8* %Loc6
+ %shft8 = lshr i64 %shft5, 8 ; [#uses=2]
+ %Loc9 = getelementptr i8* %Loc6, i32 1 ; [#uses=2]
+ %byte10 = trunc i64 %shft8 to i8 ; [#uses=1]
+ store i8 %byte10, i8* %Loc9
+ %shft11 = lshr i64 %shft8, 8 ; [#uses=0]
+ %Loc12 = getelementptr i8* %Loc9, i32 1 ; [#uses=0]
+ store i16 %s, i16* %s_addr
+ store i32 %j, i32* %j_addr
+ store i8 %c, i8* %c_addr
+ store i16 %t, i16* %t_addr
+ store i16 %u, i16* %u_addr
+ store i8 %d, i8* %d_addr
+ %tmp13 = getelementptr %struct.BoundaryAlignment* %str_addr, i32 0, i32 0 ; <[3 x i8]*> [#uses=1]
+ %tmp1314 = bitcast [3 x i8]* %tmp13 to i32* ; [#uses=1]
+ %tmp15 = load i32* %tmp1314, align 4 ; [#uses=1]
+ %tmp16 = shl i32 %tmp15, 14 ; [#uses=1]
+ %tmp17 = ashr i32 %tmp16, 23 ; [#uses=1]
+ %tmp1718 = trunc i32 %tmp17 to i16 ; [#uses=1]
+ %sextl = shl i16 %tmp1718, 7 ; [#uses=1]
+ %sextr = ashr i16 %sextl, 7 ; [#uses=2]
+ %sextl19 = shl i16 %sextr, 7 ; [#uses=1]
+ %sextr20 = ashr i16 %sextl19, 7 ; [#uses=0]
+ %sextl21 = shl i16 %sextr, 7 ; [#uses=1]
+ %sextr22 = ashr i16 %sextl21, 7 ; [#uses=1]
+ %sextr2223 = sext i16 %sextr22 to i32 ; [#uses=1]
+ %tmp24 = load i32* %j_addr, align 4 ; [#uses=1]
+ %tmp25 = icmp ne i32 %sextr2223, %tmp24 ; [#uses=1]
+ %tmp2526 = zext i1 %tmp25 to i8 ; [#uses=1]
+ %toBool = icmp ne i8 %tmp2526, 0 ; [#uses=1]
+ br i1 %toBool, label %bb, label %bb27
+
+bb: ; preds = %entry
+ call void (...)* @abort( ) noreturn nounwind
+ unreachable
+
+bb27: ; preds = %entry
+ %tmp28 = getelementptr %struct.BoundaryAlignment* %str_addr, i32 0, i32 1 ; [#uses=1]
+ %tmp29 = load i8* %tmp28, align 4 ; [#uses=1]
+ %tmp30 = load i8* %c_addr, align 1 ; [#uses=1]
+ %tmp31 = icmp ne i8 %tmp29, %tmp30 ; [#uses=1]
+ %tmp3132 = zext i1 %tmp31 to i8 ; [#uses=1]
+ %toBool33 = icmp ne i8 %tmp3132, 0 ; [#uses=1]
+ br i1 %toBool33, label %bb34, label %bb35
+
+bb34: ; preds = %bb27
+ call void (...)* @abort( ) noreturn nounwind
+ unreachable
+
+bb35: ; preds = %bb27
+ %tmp36 = getelementptr %struct.BoundaryAlignment* %str_addr, i32 0, i32 2 ; [#uses=1]
+ %tmp37 = load i16* %tmp36, align 4 ; [#uses=1]
+ %tmp38 = shl i16 %tmp37, 7 ; [#uses=1]
+ %tmp39 = ashr i16 %tmp38, 7 ; [#uses=1]
+ %sextl40 = shl i16 %tmp39, 7 ; [#uses=1]
+ %sextr41 = ashr i16 %sextl40, 7 ; [#uses=2]
+ %sextl42 = shl i16 %sextr41, 7 ; [#uses=1]
+ %sextr43 = ashr i16 %sextl42, 7 ; [#uses=0]
+ %sextl44 = shl i16 %sextr41, 7 ; [#uses=1]
+ %sextr45 = ashr i16 %sextl44, 7 ; [#uses=1]
+ %tmp46 = load i16* %t_addr, align 2 ; [#uses=1]
+ %tmp47 = icmp ne i16 %sextr45, %tmp46 ; [#uses=1]
+ %tmp4748 = zext i1 %tmp47 to i8 ; [#uses=1]
+ %toBool49 = icmp ne i8 %tmp4748, 0 ; [#uses=1]
+ br i1 %toBool49, label %bb50, label %bb51
+
+bb50: ; preds = %bb35
+ call void (...)* @abort( ) noreturn nounwind
+ unreachable
+
+bb51: ; preds = %bb35
+ %tmp52 = getelementptr %struct.BoundaryAlignment* %str_addr, i32 0, i32 3 ; [#uses=1]
+ %tmp53 = load i16* %tmp52, align 4 ; [#uses=1]
+ %tmp54 = shl i16 %tmp53, 7 ; [#uses=1]
+ %tmp55 = ashr i16 %tmp54, 7 ; [#uses=1]
+ %sextl56 = shl i16 %tmp55, 7 ; [#uses=1]
+ %sextr57 = ashr i16 %sextl56, 7 ; [#uses=2]
+ %sextl58 = shl i16 %sextr57, 7 ; [#uses=1]
+ %sextr59 = ashr i16 %sextl58, 7 ; [#uses=0]
+ %sextl60 = shl i16 %sextr57, 7 ; [#uses=1]
+ %sextr61 = ashr i16 %sextl60, 7 ; [#uses=1]
+ %tmp62 = load i16* %u_addr, align 2 ; [#uses=1]
+ %tmp63 = icmp ne i16 %sextr61, %tmp62 ; [#uses=1]
+ %tmp6364 = zext i1 %tmp63 to i8 ; [#uses=1]
+ %toBool65 = icmp ne i8 %tmp6364, 0 ; [#uses=1]
+ br i1 %toBool65, label %bb66, label %bb67
+
+bb66: ; preds = %bb51
+ call void (...)* @abort( ) noreturn nounwind
+ unreachable
+
+bb67: ; preds = %bb51
+ %tmp68 = getelementptr %struct.BoundaryAlignment* %str_addr, i32 0, i32 4 ; [#uses=1]
+ %tmp69 = load i8* %tmp68, align 4 ; [#uses=1]
+ %tmp70 = load i8* %d_addr, align 1 ; [#uses=1]
+ %tmp71 = icmp ne i8 %tmp69, %tmp70 ; [#uses=1]
+ %tmp7172 = zext i1 %tmp71 to i8 ; [#uses=1]
+ %toBool73 = icmp ne i8 %tmp7172, 0 ; [#uses=1]
+ br i1 %toBool73, label %bb74, label %bb75
+
+bb74: ; preds = %bb67
+ call void (...)* @abort( ) noreturn nounwind
+ unreachable
+
+bb75: ; preds = %bb67
+ br label %return
+
+return: ; preds = %bb75
+ ret void
+}
+
+declare void @abort(...) noreturn nounwind
From evan.cheng at apple.com Mon May 12 18:04:08 2008
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 12 May 2008 23:04:08 -0000
Subject: [llvm-commits] [llvm] r51008 - in /llvm/trunk:
include/llvm/Target/TargetLowering.h
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
lib/CodeGen/SelectionDAG/TargetLowering.cpp lib/Target/X86/README-SSE.txt
lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/combine-lds.ll
Message-ID: <200805122304.m4CN49MH018589@zion.cs.uiuc.edu>
Author: evancheng
Date: Mon May 12 18:04:07 2008
New Revision: 51008
URL: http://llvm.org/viewvc/llvm-project?rev=51008&view=rev
Log:
Xform bitconvert(build_pair(load a, load b)) to a single load if the load locations are at the right offset from each other.
Added:
llvm/trunk/test/CodeGen/X86/combine-lds.ll
Modified:
llvm/trunk/include/llvm/Target/TargetLowering.h
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/trunk/lib/Target/X86/README-SSE.txt
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Modified: llvm/trunk/include/llvm/Target/TargetLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=51008&r1=51007&r2=51008&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetLowering.h (original)
+++ llvm/trunk/include/llvm/Target/TargetLowering.h Mon May 12 18:04:07 2008
@@ -691,7 +691,7 @@
/// loading 'Bytes' bytes from a location that is 'Dist' units away from the
/// location that the 'Base' load is loading from.
bool isConsecutiveLoad(SDNode *LD, SDNode *Base, unsigned Bytes, int Dist,
- MachineFrameInfo *MFI) const;
+ const MachineFrameInfo *MFI) const;
/// PerformDAGCombine - This method will be invoked for all target nodes and
/// for any target-independent nodes that the target has registered with
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=51008&r1=51007&r2=51008&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon May 12 18:04:07 2008
@@ -177,6 +177,7 @@
SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
SDOperand visitTRUNCATE(SDNode *N);
SDOperand visitBIT_CONVERT(SDNode *N);
+ SDOperand visitBUILD_PAIR(SDNode *N);
SDOperand visitFADD(SDNode *N);
SDOperand visitFSUB(SDNode *N);
SDOperand visitFMUL(SDNode *N);
@@ -217,6 +218,7 @@
ISD::CondCode Cond, bool foldBooleans = true);
SDOperand SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
unsigned HiOp);
+ SDOperand CombineConsecutiveLoads(SDNode *N, MVT::ValueType VT);
SDOperand ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT::ValueType);
SDOperand BuildSDIV(SDNode *N);
SDOperand BuildUDIV(SDNode *N);
@@ -710,6 +712,7 @@
case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
case ISD::TRUNCATE: return visitTRUNCATE(N);
case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
+ case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
case ISD::FADD: return visitFADD(N);
case ISD::FSUB: return visitFSUB(N);
case ISD::FMUL: return visitFMUL(N);
@@ -3356,6 +3359,40 @@
return ReduceLoadWidth(N);
}
+static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
+ SDOperand Elt = N->getOperand(i);
+ if (Elt.getOpcode() != ISD::MERGE_VALUES)
+ return Elt.Val;
+ return Elt.getOperand(Elt.ResNo).Val;
+}
+
+/// CombineConsecutiveLoads - build_pair (load, load) -> load
+/// if load locations are consecutive.
+SDOperand DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT::ValueType VT) {
+ assert(N->getOpcode() == ISD::BUILD_PAIR);
+
+ SDNode *LD1 = getBuildPairElt(N, 0);
+ if (!ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse())
+ return SDOperand();
+ MVT::ValueType LD1VT = LD1->getValueType(0);
+ SDNode *LD2 = getBuildPairElt(N, 1);
+ const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
+ if (ISD::isNON_EXTLoad(LD2) &&
+ LD2->hasOneUse() &&
+ TLI.isConsecutiveLoad(LD2, LD1, MVT::getSizeInBits(LD1VT)/8, 1, MFI)) {
+ LoadSDNode *LD = cast