From edwintorok at gmail.com Mon Jun 2 02:23:42 2008 From: edwintorok at gmail.com (=?ISO-8859-1?Q?T=F6r=F6k_Edwin?=) Date: Mon, 02 Jun 2008 10:23:42 +0300 Subject: [llvm-commits] value range analysis based on scalar-evolutions In-Reply-To: <48436EF1.8020203@mxc.ca> References: <48436EF1.8020203@mxc.ca> Message-ID: <48439FFE.9040804@gmail.com> Nick Lewycky wrote: > I've implemented an analysis pass that uses SCEV to determine value > ranges of integer-typed registers. > > Currently it maintains a map of Value* to ConstantRange*, which is > rather inelegant. There is a SCEVHandle->getValueRange(), perhaps you could move the implementation there and then you wouldn't need the map? > I was thinking we could have one analysis which would do that and > others that would update the central analysis. There is also Transforms/Scalar/PredicateSimplifier that tracks value ranges. It would be nice to have all that value range info available to other passes as well. Best regards, --Edwin From rafael.espindola at gmail.com Mon Jun 2 02:52:44 2008 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Mon, 02 Jun 2008 07:52:44 -0000 Subject: [llvm-commits] [llvm] r51865 - /llvm/trunk/lib/Target/X86/X86Subtarget.cpp Message-ID: <200806020752.m527qiO6026315@zion.cs.uiuc.edu> Author: rafael Date: Mon Jun 2 02:52:43 2008 New Revision: 51865 URL: http://llvm.org/viewvc/llvm-project?rev=51865&view=rev Log: Don't use the GOT for symbols that are not externally visible. Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=51865&r1=51864&r2=51865&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original) +++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Mon Jun 2 02:52:43 2008 @@ -44,9 +44,12 @@ GV->hasCommonLinkage() || (GV->isDeclaration() && !GV->hasNotBeenReadFromBitcode()))); } else if (isTargetELF()) { - // Extra load is needed for all non-statics. - return (!isDirectCall && - (GV->isDeclaration() || !GV->hasInternalLinkage())); + // Extra load is needed for all externally visible. + if (isDirectCall) + return false; + if (GV->hasInternalLinkage() || GV->hasHiddenVisibility()) + return false; + return true; } else if (isTargetCygMing() || isTargetWindows()) { return (GV->hasDLLImportLinkage()); } From matthijs at stdin.nl Mon Jun 2 08:39:30 2008 From: matthijs at stdin.nl (Matthijs Kooijman) Date: Mon, 2 Jun 2008 15:39:30 +0200 Subject: [llvm-commits] [llvm] r51806 - in /llvm/trunk: docs/LangRef.html include/llvm/Constants.h include/llvm/DerivedTypes.h include/llvm/Instructions.h lib/AsmParser/llvmAsmParser.cpp.cvs lib/AsmParser/llvmAsmParser.h.cvs lib/AsmParser/llvmAsmParser.y lib/AsmParser/llvmAsmParser.y.cvs lib/Bitcode/Reader/BitcodeReader.cpp lib/Bitcode/Writer/BitcodeWriter.cpp lib/VMCore/Constants.cpp lib/VMCore/Instructions.cpp lib/VMCore/Type.cpp test/Assembler/insertextractvalue.ll In-Reply-To: <200805310058.m4V0wNwU011642@zion.cs.uiuc.edu> References: <200805310058.m4V0wNwU011642@zion.cs.uiuc.edu> Message-ID: <20080602133930.GG25337@katherina.student.utwente.nl> Hi Dan, there are still some constructors missing, find a patch for them attached. With that patch applied, I can succesfully create extractvalue and insertvalue instructions with a single index. I only tested the InsertBefore variants, but I guess the InsertAtEnd should work identically. I'm not really sure if that setName should be there, it's a bit weird that one of the init methods does set the name, but the others don't. Perhaps adding a Name argument to all init methods is better? Gr. Matthijs -------------- next part -------------- A non-text attachment was scrubbed... Name: insertextract.diff Type: text/x-diff Size: 2593 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20080602/dffcecb4/attachment.bin -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 189 bytes Desc: Digital signature Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20080602/dffcecb4/attachment-0001.bin From resistor at mac.com Mon Jun 2 09:58:42 2008 From: resistor at mac.com (Owen Anderson) Date: Mon, 02 Jun 2008 07:58:42 -0700 Subject: [llvm-commits] value range analysis based on scalar-evolutions In-Reply-To: <48439FFE.9040804@gmail.com> References: <48436EF1.8020203@mxc.ca> <48439FFE.9040804@gmail.com> Message-ID: <63D0BCDF-C482-4701-AF07-1D98B56DA86A@mac.com> On Jun 2, 2008, at 12:23 AM, T?r?k Edwin wrote: > Nick Lewycky wrote: > >> I was thinking we could have one analysis which would do that and >> others that would update the central analysis. > > There is also Transforms/Scalar/PredicateSimplifier that tracks value > ranges. > It would be nice to have all that value range info available to other > passes as well. He's the author of PredSimplify. ;-) --Owen -------------- next part -------------- A non-text attachment was scrubbed... Name: smime.p7s Type: application/pkcs7-signature Size: 4260 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20080602/5d2d9507/attachment.bin From baldrick at free.fr Mon Jun 2 10:56:49 2008 From: baldrick at free.fr (Duncan Sands) Date: Mon, 02 Jun 2008 15:56:49 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r51866 - /llvm-gcc-4.2/trunk/gcc/llvm-types.cpp Message-ID: <200806021556.m52FunYg008136@zion.cs.uiuc.edu> Author: baldrick Date: Mon Jun 2 10:56:49 2008 New Revision: 51866 URL: http://llvm.org/viewvc/llvm-project?rev=51866&view=rev Log: Fix 2003-10-09-UnionInitializerBug.c on x86-64. The problem was that in ConvertUNION if the new field was less aligned than a previous one but was also the biggest field seen so far then it was selected. But the most aligned field is supposed to always be selected. This caused a crash in ConvertStructFieldInitializerToType which relies on initializers not being more aligned than the LLVM type. In the long run I think ConvertStructFieldInitializerToType should be modified to not care about the alignment. Modified: llvm-gcc-4.2/trunk/gcc/llvm-types.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-types.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-types.cpp?rev=51866&r1=51865&r2=51866&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-types.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-types.cpp Mon Jun 2 10:56:49 2008 @@ -2179,7 +2179,7 @@ const TargetData &TD = getTargetData(); const Type *UnionTy = 0; tree GccUnionTy = 0; - unsigned MaxSize = 0, MaxAlign = 0; + unsigned MaxAlignSize = 0, MaxAlign = 0; for (tree Field = TYPE_FIELDS(type); Field; Field = TREE_CHAIN(Field)) { if (TREE_CODE(Field) != FIELD_DECL) continue; // assert(getFieldOffsetInBits(Field) == 0 && "Union with non-zero offset?"); @@ -2233,29 +2233,27 @@ const Type *TheTy = ConvertType(TheGccTy); unsigned Size = TD.getABITypeSize(TheTy); unsigned Align = TD.getABITypeAlignment(TheTy); - + adjustPaddingElement(GccUnionTy, TheGccTy); - // Select TheTy as union type if it meets one of the following criteria - // 1) UnionTy is 0 - // 2) TheTy alignment is more then UnionTy - // 3) TheTy size is greater than UnionTy size and TheTy alignment is - // equal to UnionTy - // 4) TheTy size is greater then UnionTy size and TheTy is packed - bool useTheTy = false; + // Select TheTy as union type if it is more aligned than any other. If more + // than one field achieves the maximum alignment then choose the biggest. + bool useTheTy; if (UnionTy == 0) useTheTy = true; + else if (Align < MaxAlign) + useTheTy = false; else if (Align > MaxAlign) useTheTy = true; - else if (MaxAlign == Align && Size > MaxSize) - useTheTy = true; - else if (Size > MaxSize) + else if (Size > MaxAlignSize) useTheTy = true; + else + useTheTy = false; if (useTheTy) { UnionTy = TheTy; GccUnionTy = TheGccTy; - MaxSize = MAX(MaxSize, Size); + MaxAlignSize = Size; MaxAlign = Align; } From snaroff at apple.com Mon Jun 2 11:37:37 2008 From: snaroff at apple.com (Steve Naroff) Date: Mon, 02 Jun 2008 16:37:37 -0000 Subject: [llvm-commits] [llvm] r51867 - /llvm/trunk/win32/Configure/Configure.vcproj Message-ID: <200806021637.m52Gbb63009558@zion.cs.uiuc.edu> Author: snaroff Date: Mon Jun 2 11:37:36 2008 New Revision: 51867 URL: http://llvm.org/viewvc/llvm-project?rev=51867&view=rev Log: update vc configure project for renaming of hash_map/hash_set/iterator to have a .h suffix. Modified: llvm/trunk/win32/Configure/Configure.vcproj Modified: llvm/trunk/win32/Configure/Configure.vcproj URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/win32/Configure/Configure.vcproj?rev=51867&r1=51866&r2=51867&view=diff ============================================================================== --- llvm/trunk/win32/Configure/Configure.vcproj (original) +++ llvm/trunk/win32/Configure/Configure.vcproj Mon Jun 2 11:37:36 2008 @@ -235,16 +235,16 @@ Author: tbrethou Date: Mon Jun 2 11:39:20 2008 New Revision: 51868 URL: http://llvm.org/viewvc/llvm-project?rev=51868&view=rev Log: Merge from mainline. Modified: llvm/branches/release_23/test/CodeGen/CBackend/2007-01-08-ParamAttr-ICmp.ll Modified: llvm/branches/release_23/test/CodeGen/CBackend/2007-01-08-ParamAttr-ICmp.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_23/test/CodeGen/CBackend/2007-01-08-ParamAttr-ICmp.ll?rev=51868&r1=51867&r2=51868&view=diff ============================================================================== --- llvm/branches/release_23/test/CodeGen/CBackend/2007-01-08-ParamAttr-ICmp.ll (original) +++ llvm/branches/release_23/test/CodeGen/CBackend/2007-01-08-ParamAttr-ICmp.ll Mon Jun 2 11:39:20 2008 @@ -1,6 +1,5 @@ ; For PR1099 -; RUN: llvm-as < %s | llc -march=c | \ -; RUN: grep {return ((((llvm_cbe_tmp2 == llvm_cbe_b_2e_0_2e_0_2e_val)) ? (1) : (0)))} +; RUN: llvm-as < %s | llc -march=c | grep {(llvm_cbe_tmp2 == llvm_cbe_b_2e_0_2e_0_2e_val)} target datalayout = "e-p:32:32" target triple = "i686-apple-darwin8" From tonic at nondot.org Mon Jun 2 11:40:49 2008 From: tonic at nondot.org (Tanya Lattner) Date: Mon, 02 Jun 2008 16:40:49 -0000 Subject: [llvm-commits] [llvm] r51869 - in /llvm/branches/release_23: lib/Target/CBackend/CBackend.cpp test/CodeGen/CBackend/2008-05-31-BoolOverflow.ll Message-ID: <200806021640.m52GenWF009695@zion.cs.uiuc.edu> Author: tbrethou Date: Mon Jun 2 11:40:49 2008 New Revision: 51869 URL: http://llvm.org/viewvc/llvm-project?rev=51869&view=rev Log: Merge from mainline. Added: llvm/branches/release_23/test/CodeGen/CBackend/2008-05-31-BoolOverflow.ll - copied unchanged from r51813, llvm/trunk/test/CodeGen/CBackend/2008-05-31-BoolOverflow.ll Modified: llvm/branches/release_23/lib/Target/CBackend/CBackend.cpp Modified: llvm/branches/release_23/lib/Target/CBackend/CBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_23/lib/Target/CBackend/CBackend.cpp?rev=51869&r1=51868&r2=51869&view=diff ============================================================================== --- llvm/branches/release_23/lib/Target/CBackend/CBackend.cpp (original) +++ llvm/branches/release_23/lib/Target/CBackend/CBackend.cpp Mon Jun 2 11:40:49 2008 @@ -155,6 +155,7 @@ void writeOperand(Value *Operand); void writeOperandRaw(Value *Operand); + void writeInstComputationInline(Instruction &I); void writeOperandInternal(Value *Operand); void writeOperandWithCast(Value* Operand, unsigned Opcode); void writeOperandWithCast(Value* Operand, const ICmpInst &I); @@ -1217,12 +1218,32 @@ return Name; } +/// writeInstComputationInline - Emit the computation for the specified +/// instruction inline, with no destination provided. +void CWriter::writeInstComputationInline(Instruction &I) { + // If this is a non-trivial bool computation, make sure to truncate down to + // a 1 bit value. This is important because we want "add i1 x, y" to return + // "0" when x and y are true, not "2" for example. + bool NeedBoolTrunc = false; + if (I.getType() == Type::Int1Ty && !isa(I) && !isa(I)) + NeedBoolTrunc = true; + + if (NeedBoolTrunc) + Out << "(("; + + visit(I); + + if (NeedBoolTrunc) + Out << ")&1)"; +} + + void CWriter::writeOperandInternal(Value *Operand) { if (Instruction *I = dyn_cast(Operand)) + // Should we inline this instruction to build a tree? if (isInlinableInst(*I) && !isDirectAlloca(I)) { - // Should we inline this instruction to build a tree? Out << '('; - visit(*I); + writeInstComputationInline(*I); Out << ')'; return; } @@ -2146,12 +2167,12 @@ outputLValue(II); else Out << " "; - visit(*II); + writeInstComputationInline(*II); Out << ";\n"; } } - // Don't emit prefix or suffix for the terminator... + // Don't emit prefix or suffix for the terminator. visit(*BB->getTerminator()); } @@ -2475,29 +2496,34 @@ void CWriter::visitCastInst(CastInst &I) { const Type *DstTy = I.getType(); const Type *SrcTy = I.getOperand(0)->getType(); - Out << '('; if (isFPIntBitCast(I)) { + Out << '('; // These int<->float and long<->double casts need to be handled specially Out << GetValueName(&I) << "__BITCAST_TEMPORARY." << getFloatBitCastField(I.getOperand(0)->getType()) << " = "; writeOperand(I.getOperand(0)); Out << ", " << GetValueName(&I) << "__BITCAST_TEMPORARY." << getFloatBitCastField(I.getType()); - } else { - printCast(I.getOpcode(), SrcTy, DstTy); - if (I.getOpcode() == Instruction::SExt && SrcTy == Type::Int1Ty) { - // Make sure we really get a sext from bool by subtracing the bool from 0 - Out << "0-"; - } - writeOperand(I.getOperand(0)); - if (DstTy == Type::Int1Ty && - (I.getOpcode() == Instruction::Trunc || - I.getOpcode() == Instruction::FPToUI || - I.getOpcode() == Instruction::FPToSI || - I.getOpcode() == Instruction::PtrToInt)) { - // Make sure we really get a trunc to bool by anding the operand with 1 - Out << "&1u"; - } + Out << ')'; + return; + } + + Out << '('; + printCast(I.getOpcode(), SrcTy, DstTy); + + // Make a sext from i1 work by subtracting the i1 from 0 (an int). + if (SrcTy == Type::Int1Ty && I.getOpcode() == Instruction::SExt) + Out << "0-"; + + writeOperand(I.getOperand(0)); + + if (DstTy == Type::Int1Ty && + (I.getOpcode() == Instruction::Trunc || + I.getOpcode() == Instruction::FPToUI || + I.getOpcode() == Instruction::FPToSI || + I.getOpcode() == Instruction::PtrToInt)) { + // Make sure we really get a trunc to bool by anding the operand with 1 + Out << "&1u"; } Out << ')'; } From tonic at nondot.org Mon Jun 2 11:54:16 2008 From: tonic at nondot.org (Tanya Lattner) Date: Mon, 02 Jun 2008 16:54:16 -0000 Subject: [llvm-commits] [test-suite] r51870 - /test-suite/branches/release_23/SingleSource/Benchmarks/CoyoteBench/fftbench.cpp Message-ID: <200806021654.m52GsGXB010267@zion.cs.uiuc.edu> Author: tbrethou Date: Mon Jun 2 11:54:15 2008 New Revision: 51870 URL: http://llvm.org/viewvc/llvm-project?rev=51870&view=rev Log: Merge from mainline. Modified: test-suite/branches/release_23/SingleSource/Benchmarks/CoyoteBench/fftbench.cpp Modified: test-suite/branches/release_23/SingleSource/Benchmarks/CoyoteBench/fftbench.cpp URL: http://llvm.org/viewvc/llvm-project/test-suite/branches/release_23/SingleSource/Benchmarks/CoyoteBench/fftbench.cpp?rev=51870&r1=51869&r2=51870&view=diff ============================================================================== --- test-suite/branches/release_23/SingleSource/Benchmarks/CoyoteBench/fftbench.cpp (original) +++ test-suite/branches/release_23/SingleSource/Benchmarks/CoyoteBench/fftbench.cpp Mon Jun 2 11:54:15 2008 @@ -46,7 +46,7 @@ #ifdef SMALL_PROBLEM_SIZE static const int TEST_SIZE = 50000; #else -static const int TEST_SIZE = 2097152; +static const int TEST_SIZE = 2097152/2; #endif #endif From kremenek at apple.com Mon Jun 2 12:15:46 2008 From: kremenek at apple.com (Ted Kremenek) Date: Mon, 02 Jun 2008 17:15:46 -0000 Subject: [llvm-commits] [llvm] r51873 - /llvm/tags/checker/checker-35/ Message-ID: <200806021715.m52HFkB5010907@zion.cs.uiuc.edu> Author: kremenek Date: Mon Jun 2 12:15:46 2008 New Revision: 51873 URL: http://llvm.org/viewvc/llvm-project?rev=51873&view=rev Log: Tagging checker-35. Added: llvm/tags/checker/checker-35/ - copied from r51872, llvm/trunk/ From wmatyjewicz at fastmail.fm Mon Jun 2 12:26:12 2008 From: wmatyjewicz at fastmail.fm (Wojciech Matyjewicz) Date: Mon, 02 Jun 2008 17:26:12 -0000 Subject: [llvm-commits] [llvm] r51875 - in /llvm/trunk: lib/Analysis/BasicAliasAnalysis.cpp test/Analysis/BasicAA/2008-06-02-GEPTailCrash.ll Message-ID: <200806021726.m52HQCpu011191@zion.cs.uiuc.edu> Author: wmat Date: Mon Jun 2 12:26:12 2008 New Revision: 51875 URL: http://llvm.org/viewvc/llvm-project?rev=51875&view=rev Log: Fixes PR2395. Looking for a constant in a GEP tail (when the first GEP is longer than the second one) should stop after finding one. Added break instruction guarantees it. It also changes difference between offsets to absolute value of this difference in the condition. Added: llvm/trunk/test/Analysis/BasicAA/2008-06-02-GEPTailCrash.ll Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp?rev=51875&r1=51874&r2=51875&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Mon Jun 2 12:26:12 2008 @@ -687,7 +687,7 @@ if (isa(GEP1Ops[i]) && !cast(GEP1Ops[i])->isZero()) { // Yup, there's a constant in the tail. Set all variables to - // constants in the GEP instruction to make it suiteable for + // constants in the GEP instruction to make it suitable for // TargetData::getIndexedOffset. for (i = 0; i != MaxOperands; ++i) if (!isa(GEP1Ops[i])) @@ -702,9 +702,15 @@ int64_t Offset2 = TD.getIndexedOffset(GEPPointerTy, GEP1Ops, MinOperands); + // Make sure we compare the absolute difference. + if (Offset1 > Offset2) + std::swap(Offset1, Offset2); + // If the tail provided a bit enough offset, return noalias! if ((uint64_t)(Offset2-Offset1) >= SizeMax) return NoAlias; + // Otherwise break - we don't look for another constant in the tail. + break; } } Added: llvm/trunk/test/Analysis/BasicAA/2008-06-02-GEPTailCrash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/BasicAA/2008-06-02-GEPTailCrash.ll?rev=51875&view=auto ============================================================================== --- llvm/trunk/test/Analysis/BasicAA/2008-06-02-GEPTailCrash.ll (added) +++ llvm/trunk/test/Analysis/BasicAA/2008-06-02-GEPTailCrash.ll Mon Jun 2 12:26:12 2008 @@ -0,0 +1,15 @@ +; RUN: llvm-as < %s | opt -gvn -disable-output +; PR2395 + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32" +target triple = "i686-pc-linux-gnu" + %struct.S291 = type <{ %union.anon, i32 }> + %union.anon = type { } + at a291 = external global [5 x %struct.S291] ; <[5 x %struct.S291]*> [#uses=2] + +define void @test291() nounwind { +entry: + store i32 1138410269, i32* getelementptr ([5 x %struct.S291]* @a291, i32 0, i32 2, i32 1) + %tmp54 = load i32* bitcast (%struct.S291* getelementptr ([5 x %struct.S291]* @a291, i32 0, i32 2) to i32*), align 4 ; [#uses=0] + unreachable +} From resistor at mac.com Mon Jun 2 12:36:36 2008 From: resistor at mac.com (Owen Anderson) Date: Mon, 02 Jun 2008 17:36:36 -0000 Subject: [llvm-commits] [llvm] r51876 - /llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Message-ID: <200806021736.m52Haaci011474@zion.cs.uiuc.edu> Author: resistor Date: Mon Jun 2 12:36:36 2008 New Revision: 51876 URL: http://llvm.org/viewvc/llvm-project?rev=51876&view=rev Log: Correctly handle removed instructions at the beginning of MBBs when renumbering. Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=51876&r1=51875&r2=51876&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Mon Jun 2 12:36:36 2008 @@ -128,13 +128,11 @@ i++; } while (!newInstr); - MachineInstr* preceding = i2miMap_[(mi2iMap_[newInstr] - - InstrSlots::NUM) / InstrSlots::NUM]; - if (preceding->getParent() == newInstr->getParent() && - preceding->modifiesRegister(I->second.reg)) - LI->start = mi2iMap_[newInstr] - InstrSlots::NUM + offset; - else + if (mi2iMap_[newInstr] == + MBB2IdxMap[newInstr->getParent()->getNumber()].first) LI->start = mi2iMap_[newInstr]; + else + LI->start = mi2iMap_[newInstr] - InstrSlots::NUM + offset; } // Remap the ending index in the same way that we remapped the start, @@ -172,13 +170,11 @@ i++; } while (!newInstr); - MachineInstr* preceding = i2miMap_[(mi2iMap_[newInstr] - - InstrSlots::NUM) / InstrSlots::NUM]; - if (preceding->getParent() == newInstr->getParent() && - preceding->modifiesRegister(I->second.reg)) - vni->def = mi2iMap_[newInstr] - InstrSlots::NUM + offset; - else + if (mi2iMap_[newInstr] == + MBB2IdxMap[newInstr->getParent()->getNumber()].first) vni->def = mi2iMap_[newInstr]; + else + vni->def = mi2iMap_[newInstr] - InstrSlots::NUM + offset; } // Remap the VNInfo kill indices, which works the same as From gohman at apple.com Mon Jun 2 12:40:39 2008 From: gohman at apple.com (Dan Gohman) Date: Mon, 02 Jun 2008 17:40:39 -0000 Subject: [llvm-commits] [llvm] r51877 - in /llvm/trunk: test/CodeGen/X86/variadic-node-pic.ll utils/TableGen/DAGISelEmitter.cpp Message-ID: <200806021740.m52Hedhq011599@zion.cs.uiuc.edu> Author: djg Date: Mon Jun 2 12:40:38 2008 New Revision: 51877 URL: http://llvm.org/viewvc/llvm-project?rev=51877&view=rev Log: Fix the position of MemOperands in nodes that use variadic_ops in DAGISelEmitter output. This bug was recently uncovered by the addition of patterns for CALL32m and CALL64m, which are nodes that now have both MemOperands and variadic_ops. This bug was especially visible with PIC in various configurations, because the new patterns are matching the indirect call code used in many PIC configurations. Added: llvm/trunk/test/CodeGen/X86/variadic-node-pic.ll Modified: llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Added: llvm/trunk/test/CodeGen/X86/variadic-node-pic.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/variadic-node-pic.ll?rev=51877&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/variadic-node-pic.ll (added) +++ llvm/trunk/test/CodeGen/X86/variadic-node-pic.ll Mon Jun 2 12:40:38 2008 @@ -0,0 +1,11 @@ +; RUN: llvm-as < %s | llc -relocation-model=pic -code-model=large + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" +target triple = "x86_64-apple-darwin8" + +declare void @xscanf(i64) nounwind + +define void @foo() nounwind { + call void (i64)* @xscanf( i64 0 ) nounwind + unreachable +} Modified: llvm/trunk/utils/TableGen/DAGISelEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelEmitter.cpp?rev=51877&r1=51876&r2=51877&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/DAGISelEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Mon Jun 2 12:40:38 2008 @@ -992,18 +992,6 @@ } } - // Generate MemOperandSDNodes nodes for each memory accesses covered by - // this pattern. - if (II.isSimpleLoad | II.mayLoad | II.mayStore) { - std::vector::const_iterator mi, mie; - for (mi = LSI.begin(), mie = LSI.end(); mi != mie; ++mi) { - emitCode("SDOperand LSI_" + *mi + " = " - "CurDAG->getMemOperand(cast(" + - *mi + ")->getMemOperand());"); - AllOps.push_back("LSI_" + *mi); - } - } - // Emit all the chain and CopyToReg stuff. bool ChainEmitted = NodeHasChain; if (NodeHasChain) @@ -1088,6 +1076,21 @@ emitCode("}"); } + // Generate MemOperandSDNodes nodes for each memory accesses covered by + // this pattern. + if (II.isSimpleLoad | II.mayLoad | II.mayStore) { + std::vector::const_iterator mi, mie; + for (mi = LSI.begin(), mie = LSI.end(); mi != mie; ++mi) { + emitCode("SDOperand LSI_" + *mi + " = " + "CurDAG->getMemOperand(cast(" + + *mi + ")->getMemOperand());"); + if (IsVariadic) + emitCode("Ops" + utostr(OpsNo) + ".push_back(LSI_" + *mi + ");"); + else + AllOps.push_back("LSI_" + *mi); + } + } + if (NodeHasChain) { if (IsVariadic) emitCode("Ops" + utostr(OpsNo) + ".push_back(" + ChainName + ");"); From gohman at apple.com Mon Jun 2 12:47:29 2008 From: gohman at apple.com (Dan Gohman) Date: Mon, 2 Jun 2008 10:47:29 -0700 Subject: [llvm-commits] [llvm] r51863 - in /llvm/trunk: include/llvm/Analysis/ValueTracking.h lib/Analysis/ValueTracking.cpp lib/Transforms/Scalar/InstructionCombining.cpp In-Reply-To: <200806020118.m521ILWG007059@zion.cs.uiuc.edu> References: <200806020118.m521ILWG007059@zion.cs.uiuc.edu> Message-ID: On Jun 1, 2008, at 6:18 PM, Chris Lattner wrote: > Author: lattner > Date: Sun Jun 1 20:18:21 2008 > New Revision: 51863 > > URL: http://llvm.org/viewvc/llvm-project?rev=51863&view=rev > Log: > move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits > out of instcombine into a new file in libanalysis. This also teaches > ComputeNumSignBits about the number of sign bits in a constantint. Hi Chris, ComputeNumSignBits has fallback code that uses ComputeMaskedBits to compute a result for any node that it doesn't have special logic for. That logic should have handled ConstantInt; was it failing to do so? Dan From gohman at apple.com Mon Jun 2 12:52:55 2008 From: gohman at apple.com (Dan Gohman) Date: Mon, 2 Jun 2008 10:52:55 -0700 Subject: [llvm-commits] [llvm] r51806 - in /llvm/trunk: docs/LangRef.html include/llvm/Constants.h include/llvm/DerivedTypes.h include/llvm/Instructions.h lib/AsmParser/llvmAsmParser.cpp.cvs lib/AsmParser/llvmAsmParser.h.cvs lib/AsmParser/llvmAsmParser.y lib/AsmParser/llvmAsmParser.y.cvs lib/Bitcode/Reader/BitcodeReader.cpp lib/Bitcode/Writer/BitcodeWriter.cpp lib/VMCore/Constants.cpp lib/VMCore/Instructions.cpp lib/VMCore/Type.cpp test/Assembler/insertextractvalue.ll In-Reply-To: <1F0682CE-29D4-483E-BE8D-324DEE70F17C@mac.com> References: <1F0682CE-29D4-483E-BE8D-324DEE70F17C@mac.com> Message-ID: <40C0FD9E-4F8A-49EB-83FB-82B72B1C2483@apple.com> On May 31, 2008, at 12:25 AM, Gabor Greif wrote: > Hi Dan, > > please find my comments inline: Hi Gabor, Thanks a lot for reviewing this! I neglected to mention that 51820 and 51821 fix the issues you found. Dan From sabre at nondot.org Mon Jun 2 13:39:07 2008 From: sabre at nondot.org (Chris Lattner) Date: Mon, 02 Jun 2008 18:39:07 -0000 Subject: [llvm-commits] [llvm] r51878 - /llvm/trunk/lib/Analysis/ValueTracking.cpp Message-ID: <200806021839.m52Id80o013239@zion.cs.uiuc.edu> Author: lattner Date: Mon Jun 2 13:39:07 2008 New Revision: 51878 URL: http://llvm.org/viewvc/llvm-project?rev=51878&view=rev Log: Remove unneeded code I added. Modified: llvm/trunk/lib/Analysis/ValueTracking.cpp Modified: llvm/trunk/lib/Analysis/ValueTracking.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ValueTracking.cpp?rev=51878&r1=51877&r2=51878&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ValueTracking.cpp (original) +++ llvm/trunk/lib/Analysis/ValueTracking.cpp Mon Jun 2 13:39:07 2008 @@ -565,12 +565,9 @@ unsigned Tmp, Tmp2; unsigned FirstAnswer = 1; - if (ConstantInt *CI = dyn_cast(V)) { - if (CI->getValue().isNegative()) - return CI->getValue().countLeadingOnes(); - return CI->getValue().countLeadingZeros(); - } - + // Note that ConstantInt is handled by the general ComputeMaskedBits case + // below. + if (Depth == 6) return 1; // Limit search depth. From clattner at apple.com Mon Jun 2 13:39:28 2008 From: clattner at apple.com (Chris Lattner) Date: Mon, 2 Jun 2008 11:39:28 -0700 Subject: [llvm-commits] [llvm] r51863 - in /llvm/trunk: include/llvm/Analysis/ValueTracking.h lib/Analysis/ValueTracking.cpp lib/Transforms/Scalar/InstructionCombining.cpp In-Reply-To: References: <200806020118.m521ILWG007059@zion.cs.uiuc.edu> Message-ID: <6B9303D7-5957-4115-92CA-1C3DE34869ED@apple.com> On Jun 2, 2008, at 10:47 AM, Dan Gohman wrote: > > On Jun 1, 2008, at 6:18 PM, Chris Lattner wrote: > >> Author: lattner >> Date: Sun Jun 1 20:18:21 2008 >> New Revision: 51863 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=51863&view=rev >> Log: >> move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits >> out of instcombine into a new file in libanalysis. This also teaches >> ComputeNumSignBits about the number of sign bits in a constantint. > > Hi Chris, > > ComputeNumSignBits has fallback code that uses ComputeMaskedBits > to compute a result for any node that it doesn't have special > logic for. That logic should have handled ConstantInt; was it > failing to do so? Very subtle, I missed that. Thanks, I added a comment and removed the code. -Chris From gohman at apple.com Mon Jun 2 14:47:10 2008 From: gohman at apple.com (Dan Gohman) Date: Mon, 02 Jun 2008 19:47:10 -0000 Subject: [llvm-commits] [llvm] r51879 - /llvm/trunk/utils/llvm.grm Message-ID: <200806021947.m52JlA1t015313@zion.cs.uiuc.edu> Author: djg Date: Mon Jun 2 14:47:09 2008 New Revision: 51879 URL: http://llvm.org/viewvc/llvm-project?rev=51879&view=rev Log: Update the polygen grammer for the new insertvalue and extractvalue syntax. Modified: llvm/trunk/utils/llvm.grm Modified: llvm/trunk/utils/llvm.grm URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/llvm.grm?rev=51879&r1=51878&r2=51879&view=diff ============================================================================== --- llvm/trunk/utils/llvm.grm (original) +++ llvm/trunk/utils/llvm.grm Mon Jun 2 14:47:09 2008 @@ -223,8 +223,8 @@ | extractelement "(" ^ ConstVal ^ "," ConstVal ^ ")" | insertelement "(" ^ ConstVal ^ "," ConstVal ^ "," ConstVal ^ ")" | shufflevector "(" ^ ConstVal ^ "," ConstVal ^ "," ConstVal ^ ")" - | extractvalue "(" ^ ConstVal IndexList ^ ")" - | insertvalue "(" ^ ConstVal ^ "," ConstVal IndexList ^ ")" ; + | extractvalue "(" ^ ConstVal ^ ConstantIndexList ^ ")" + | insertvalue "(" ^ ConstVal ^ "," ConstVal ^ ConstantIndexList ^ ")" ; ConstVector ::= ConstVector ^ "," ConstVal | ConstVal ; @@ -345,6 +345,8 @@ IndexList ::= _ | IndexList ^ "," ResolvedVal ; +ConstantIndexList ::= "," EUINT64VAL | ConstantIndexList ^ "," EUINT64VAL ; + OptTailCall ::= tail call | call ; InstVal ::= @@ -376,5 +378,5 @@ | OptVolatile store ResolvedVal ^ "," Types ValueRef OptCAlign | getresult Types ValueRef ^ "," EUINT64VAL | getelementptr Types ValueRef IndexList - | extractvalue Types ValueRef IndexList - | insertvalue Types ValueRef ^ "," Types ValueRef IndexList ; + | extractvalue Types ValueRef ^ ConstantIndexList + | insertvalue Types ValueRef ^ "," Types ValueRef ^ ConstantIndexList ; From gohman at apple.com Mon Jun 2 15:15:53 2008 From: gohman at apple.com (Dan Gohman) Date: Mon, 2 Jun 2008 13:15:53 -0700 Subject: [llvm-commits] [llvm] r51806 - in /llvm/trunk: docs/LangRef.html include/llvm/Constants.h include/llvm/DerivedTypes.h include/llvm/Instructions.h lib/AsmParser/llvmAsmParser.cpp.cvs lib/AsmParser/llvmAsmParser.h.cvs lib/AsmParser/llvmAsmParser.y lib/AsmParser/llvmAsmParser.y.cvs lib/Bitcode/Reader/BitcodeReader.cpp lib/Bitcode/Writer/BitcodeWriter.cpp lib/VMCore/Constants.cpp lib/VMCore/Instructions.cpp lib/VMCore/Type.cpp test/Assembler/insertextractvalue.ll In-Reply-To: <20080602133930.GG25337@katherina.student.utwente.nl> References: <200805310058.m4V0wNwU011642@zion.cs.uiuc.edu> <20080602133930.GG25337@katherina.student.utwente.nl> Message-ID: <04C413B9-0D61-4F4F-A605-786B2D735CF6@apple.com> Hi Matthijs, This looks good; please commit it. I agree the setName situation is a little inconsistent. This code is actually modeled after the getelementptr code which works the same way. Would you mind preparing a patch to fix this? Thanks, Dan On Jun 2, 2008, at 6:39 AM, Matthijs Kooijman wrote: > Hi Dan, > > there are still some constructors missing, find a patch for them > attached. > > With that patch applied, I can succesfully create extractvalue and > insertvalue > instructions with a single index. I only tested the InsertBefore > variants, but > I guess the InsertAtEnd should work identically. > > I'm not really sure if that setName should be there, it's a bit > weird that one > of the init methods does set the name, but the others don't. Perhaps > adding a > Name argument to all init methods is better? > > Gr. > > Matthijs > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From gohman at apple.com Mon Jun 2 16:30:50 2008 From: gohman at apple.com (Dan Gohman) Date: Mon, 02 Jun 2008 21:30:50 -0000 Subject: [llvm-commits] [llvm] r51881 - in /llvm/trunk: lib/Target/CBackend/CBackend.cpp test/CodeGen/CBackend/2007-01-15-NamedArrayType.ll Message-ID: <200806022130.m52LUoxf025539@zion.cs.uiuc.edu> Author: djg Date: Mon Jun 2 16:30:49 2008 New Revision: 51881 URL: http://llvm.org/viewvc/llvm-project?rev=51881&view=rev Log: Implement CBE support for first-class structs and array values, and insertvalue and extractvalue instructions. First-class array values are not trivial because C doesn't support them. The approach I took here is to wrap all arrays in structs. Feedback is welcome. The 2007-01-15-NamedArrayType.ll test needed to be modified because it has a "not grep" for a string that now exists, because array types now have associated struct types, and those struct types have names. Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp llvm/trunk/test/CodeGen/CBackend/2007-01-15-NamedArrayType.ll Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CBackend.cpp?rev=51881&r1=51880&r2=51881&view=diff ============================================================================== --- llvm/trunk/lib/Target/CBackend/CBackend.cpp (original) +++ llvm/trunk/lib/Target/CBackend/CBackend.cpp Mon Jun 2 16:30:49 2008 @@ -171,7 +171,7 @@ void printModule(Module *M); void printModuleTypes(const TypeSymbolTable &ST); - void printContainedStructs(const Type *Ty, std::set &); + void printContainedStructs(const Type *Ty, std::set &); void printFloatingPointConstants(Function &F); void printFunctionSignature(const Function *F, bool Prototype); @@ -210,7 +210,8 @@ // emit it inline where it would go. if (I.getType() == Type::VoidTy || !I.hasOneUse() || isa(I) || isa(I) || isa(I) || - isa(I) || isa(I) || isa(I)) + isa(I) || isa(I) || isa(I) || + isa(I)) // Don't inline a load across a store or other bad things! return false; @@ -286,6 +287,9 @@ void visitShuffleVectorInst(ShuffleVectorInst &SVI); void visitGetResultInst(GetResultInst &GRI); + void visitInsertValueInst(InsertValueInst &I); + void visitExtractValueInst(ExtractValueInst &I); + void visitInstruction(Instruction &I) { cerr << "C Writer does not know about " << I; abort(); @@ -325,9 +329,10 @@ TI != TE; ) { TypeSymbolTable::iterator I = TI++; - // If this isn't a struct type, remove it from our set of types to name. - // This simplifies emission later. - if (!isa(I->second) && !isa(I->second)) { + // If this isn't a struct or array type, remove it from our set of types + // to name. This simplifies emission later. + if (!isa(I->second) && !isa(I->second) && + !isa(I->second)) { TST.remove(I); } else { // If this is not used, remove it from the symbol table. @@ -346,8 +351,8 @@ unsigned RenameCounter = 0; for (std::set::const_iterator I = UT.begin(), E = UT.end(); I != E; ++I) - if (const StructType *ST = dyn_cast(*I)) { - while (M.addTypeName("unnamed"+utostr(RenameCounter), ST)) + if (isa(*I) || isa(*I)) { + while (M.addTypeName("unnamed"+utostr(RenameCounter), *I)) ++RenameCounter; Changed = true; } @@ -557,8 +562,12 @@ const ArrayType *ATy = cast(Ty); unsigned NumElements = ATy->getNumElements(); if (NumElements == 0) NumElements = 1; - return printType(Out, ATy->getElementType(), false, - NameSoFar + "[" + utostr(NumElements) + "]"); + // Arrays are wrapped in structs to allow them to have normal + // value semantics (avoiding the array "decay"). + Out << NameSoFar << " { "; + printType(Out, ATy->getElementType(), false, + "array[" + utostr(NumElements) + "]"); + return Out << "; }"; } case Type::OpaqueTyID: { @@ -1013,6 +1022,7 @@ } case Type::ArrayTyID: + Out << "{ "; // Arrays are wrapped in struct types. if (ConstantArray *CA = dyn_cast(CPV)) { printConstantArray(CA); } else { @@ -1030,6 +1040,7 @@ } Out << " }"; } + Out << " }"; // Arrays are wrapped in struct types. break; case Type::VectorTyID: @@ -1760,9 +1771,12 @@ // the compiler figure out the rest of the zeros. Out << " = " ; if (isa(I->getInitializer()->getType()) || - isa(I->getInitializer()->getType()) || isa(I->getInitializer()->getType())) { Out << "{ 0 }"; + } else if (isa(I->getInitializer()->getType())) { + // As with structs and vectors, but with an extra set of braces + // because arrays are wrapped in structs. + Out << "{ { 0 } }"; } else { // Just print it out normally. writeOperand(I->getInitializer()); @@ -1904,16 +1918,16 @@ Out << '\n'; // Keep track of which structures have been printed so far... - std::set StructPrinted; + std::set StructPrinted; // Loop over all structures then push them into the stack so they are // printed in the correct order. // Out << "/* Structure contents */\n"; for (I = TST.begin(); I != End; ++I) - if (const StructType *STy = dyn_cast(I->second)) + if (isa(I->second) || isa(I->second)) // Only print out used types! - printContainedStructs(STy, StructPrinted); + printContainedStructs(I->second, StructPrinted); } // Push the struct onto the stack and recursively push all structs @@ -1922,7 +1936,7 @@ // TODO: Make this work properly with vector types // void CWriter::printContainedStructs(const Type *Ty, - std::set &StructPrinted){ + std::set &StructPrinted) { // Don't walk through pointers. if (isa(Ty) || Ty->isPrimitiveType() || Ty->isInteger()) return; @@ -1931,12 +1945,12 @@ E = Ty->subtype_end(); I != E; ++I) printContainedStructs(*I, StructPrinted); - if (const StructType *STy = dyn_cast(Ty)) { + if (isa(Ty) || isa(Ty)) { // Check to see if we have already printed this struct. - if (StructPrinted.insert(STy).second) { + if (StructPrinted.insert(Ty).second) { // Print structure type out. - std::string Name = TypeNames[STy]; - printType(Out, STy, false, Name, true); + std::string Name = TypeNames[Ty]; + printType(Out, Ty, false, Name, true); Out << ";\n\n"; } } @@ -3097,6 +3111,10 @@ for (; I != E; ++I) { if (isa(*I)) { Out << ".field" << cast(I.getOperand())->getZExtValue(); + } else if (isa(*I)) { + Out << ".array["; + writeOperandWithCast(I.getOperand(), Instruction::GetElementPtr); + Out << ']'; } else if (!isa(*I)) { Out << '['; writeOperandWithCast(I.getOperand(), Instruction::GetElementPtr); @@ -3255,6 +3273,47 @@ Out << ")"; } +void CWriter::visitInsertValueInst(InsertValueInst &IVI) { + // Start by copying the entire aggregate value into the result variable. + writeOperand(IVI.getOperand(0)); + Out << ";\n "; + + // Then do the insert to update the field. + Out << GetValueName(&IVI); + for (const unsigned *b = IVI.idx_begin(), *i = b, *e = IVI.idx_end(); + i != e; ++i) { + const Type *IndexedTy = + ExtractValueInst::getIndexedType(IVI.getOperand(0)->getType(), b, i+1); + if (isa(IndexedTy)) + Out << ".array[" << *i << "]"; + else + Out << ".field" << *i; + } + Out << " = "; + writeOperand(IVI.getOperand(1)); +} + +void CWriter::visitExtractValueInst(ExtractValueInst &EVI) { + Out << "("; + if (isa(EVI.getOperand(0))) { + Out << "("; + printType(Out, EVI.getType()); + Out << ") 0/*UNDEF*/"; + } else { + Out << GetValueName(EVI.getOperand(0)); + for (const unsigned *b = EVI.idx_begin(), *i = b, *e = EVI.idx_end(); + i != e; ++i) { + const Type *IndexedTy = + ExtractValueInst::getIndexedType(EVI.getOperand(0)->getType(), b, i+1); + if (isa(IndexedTy)) + Out << ".array[" << *i << "]"; + else + Out << ".field" << *i; + } + } + Out << ")"; +} + //===----------------------------------------------------------------------===// // External Interface declaration //===----------------------------------------------------------------------===// Modified: llvm/trunk/test/CodeGen/CBackend/2007-01-15-NamedArrayType.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CBackend/2007-01-15-NamedArrayType.ll?rev=51881&r1=51880&r2=51881&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/CBackend/2007-01-15-NamedArrayType.ll (original) +++ llvm/trunk/test/CodeGen/CBackend/2007-01-15-NamedArrayType.ll Mon Jun 2 16:30:49 2008 @@ -1,5 +1,5 @@ ; PR918 -; RUN: llvm-as < %s | llc -march=c | not grep fixarray_array3 +; RUN: llvm-as < %s | llc -march=c | not grep {l_structtype_s l_fixarray_array3} %structtype_s = type { i32 } %fixarray_array3 = type [3 x %structtype_s] From scottm at aero.org Mon Jun 2 17:18:03 2008 From: scottm at aero.org (Scott Michel) Date: Mon, 02 Jun 2008 22:18:03 -0000 Subject: [llvm-commits] [llvm] r51884 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp lib/Target/CellSPU/SPUISelLowering.cpp lib/Target/CellSPU/SPUISelLowering.h lib/Target/CellSPU/SPUInstrInfo.td lib/Target/CellSPU/SPUNodes.td lib/Target/CellSPU/SPUOperands.td test/CodeGen/CellSPU/immed64.ll Message-ID: <200806022218.m52MI4Ud024127@zion.cs.uiuc.edu> Author: pingbak Date: Mon Jun 2 17:18:03 2008 New Revision: 51884 URL: http://llvm.org/viewvc/llvm-project?rev=51884&view=rev Log: Add necessary 64-bit support so that gcc frontend compiles (mostly). Current issue is operand promotion for setcc/select... but looks like the fundamental stuff is implemented for CellSPU. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td llvm/trunk/lib/Target/CellSPU/SPUNodes.td llvm/trunk/lib/Target/CellSPU/SPUOperands.td llvm/trunk/test/CodeGen/CellSPU/immed64.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=51884&r1=51883&r2=51884&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Jun 2 17:18:03 2008 @@ -4441,11 +4441,20 @@ AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); break; } - case ISD::SELECT: + case ISD::SELECT: { Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 + + unsigned VT2 = Tmp2.getValueType(); + assert(VT2 == Tmp3.getValueType() + && "PromoteOp: Operands 2 and 3 ValueTypes don't match"); + // Ensure tha NVT is the same as the operands' value types, because we + // cannot assume that TLI.getSetCCValueType() is constant. + if (NVT != VT2) + NVT = VT2; Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3); break; + } case ISD::SELECT_CC: Tmp2 = PromoteOp(Node->getOperand(2)); // True Tmp3 = PromoteOp(Node->getOperand(3)); // False Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=51884&r1=51883&r2=51884&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Mon Jun 2 17:18:03 2008 @@ -219,8 +219,10 @@ // Custom lower i32 multiplications setOperationAction(ISD::MUL, MVT::i32, Custom); - // Need to custom handle (some) common i8 math ops + // Need to custom handle (some) common i8, i64 math ops + setOperationAction(ISD::ADD, MVT::i64, Custom); setOperationAction(ISD::SUB, MVT::i8, Custom); + setOperationAction(ISD::SUB, MVT::i64, Custom); setOperationAction(ISD::MUL, MVT::i8, Custom); // SPU does not have BSWAP. It does have i32 support CTLZ. @@ -238,7 +240,7 @@ setOperationAction(ISD::CTLZ , MVT::i32, Legal); - // SPU has a version of select that implements (a&~c)|(b|c), just like + // SPU has a version of select that implements (a&~c)|(b&c), just like // select ought to work: setOperationAction(ISD::SELECT, MVT::i1, Promote); setOperationAction(ISD::SELECT, MVT::i8, Legal); @@ -427,8 +429,14 @@ node_names[(unsigned) SPUISD::ROTBYTES_LEFT] = "SPUISD::ROTBYTES_LEFT"; node_names[(unsigned) SPUISD::ROTBYTES_LEFT_CHAINED] = "SPUISD::ROTBYTES_LEFT_CHAINED"; - node_names[(unsigned) SPUISD::FSMBI] = "SPUISD::FSMBI"; + node_names[(unsigned) SPUISD::ROTBYTES_LEFT_BITS] = + "SPUISD::ROTBYTES_LEFT_BITS"; + node_names[(unsigned) SPUISD::SELECT_MASK] = "SPUISD::SELECT_MASK"; node_names[(unsigned) SPUISD::SELB] = "SPUISD::SELB"; + node_names[(unsigned) SPUISD::ADD_EXTENDED] = "SPUISD::ADD_EXTENDED"; + node_names[(unsigned) SPUISD::CARRY_GENERATE] = "SPUISD::CARRY_GENERATE"; + node_names[(unsigned) SPUISD::SUB_EXTENDED] = "SPUISD::SUB_EXTENDED"; + node_names[(unsigned) SPUISD::BORROW_GENERATE] = "SPUISD::BORROW_GENERATE"; node_names[(unsigned) SPUISD::FPInterp] = "SPUISD::FPInterp"; node_names[(unsigned) SPUISD::FPRecipEst] = "SPUISD::FPRecipEst"; node_names[(unsigned) SPUISD::SEXT32TO64] = "SPUISD::SEXT32TO64"; @@ -1706,33 +1714,33 @@ } for (int i = 0; i < 4; ++i) { + uint64_t val = 0; for (int j = 0; j < 4; ++j) { SDOperand V; bool process_upper, process_lower; - uint64_t val = 0; - + val <<= 8; process_upper = (upper_special && (i & 1) == 0); process_lower = (lower_special && (i & 1) == 1); if (process_upper || process_lower) { if ((process_upper && upper == 0) || (process_lower && lower == 0)) - val = 0x80; + val |= 0x80; else if ((process_upper && upper == 0xffffffff) || (process_lower && lower == 0xffffffff)) - val = 0xc0; + val |= 0xc0; else if ((process_upper && upper == 0x80000000) || (process_lower && lower == 0x80000000)) - val = (j == 0 ? 0xe0 : 0x80); + val |= (j == 0 ? 0xe0 : 0x80); } else - val = i * 4 + j + ((i & 1) * 16); - - ShufBytes.push_back(DAG.getConstant(val, MVT::i8)); + val |= i * 4 + j + ((i & 1) * 16); } + + ShufBytes.push_back(DAG.getConstant(val, MVT::i32)); } return DAG.getNode(SPUISD::SHUFB, VT, HI32, LO32, - DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, + DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, &ShufBytes[0], ShufBytes.size())); } } @@ -1904,7 +1912,7 @@ // b) multiply upper halves, rotate left by 16 bits (inserts 16 lower zeroes) // c) Use SELB to select upper and lower halves from the intermediate results // - // NOTE: We really want to move the FSMBI to earlier to actually get the + // NOTE: We really want to move the SELECT_MASK to earlier to actually get the // dual-issue. This code does manage to do this, even if it's a little on // the wacky side case MVT::v8i16: { @@ -1918,7 +1926,7 @@ SDOperand FSMBOp = DAG.getCopyToReg(Chain, FSMBIreg, - DAG.getNode(SPUISD::FSMBI, MVT::v8i16, + DAG.getNode(SPUISD::SELECT_MASK, MVT::v8i16, DAG.getConstant(0xcccc, MVT::i16))); SDOperand HHProd = @@ -1962,7 +1970,7 @@ DAG.getNode(SPUISD::VEC_SHL, MVT::v8i16, DAG.getNode(SPUISD::MPY, MVT::v8i16, rALH, rBLH), c8); - SDOperand FSMBmask = DAG.getNode(SPUISD::FSMBI, MVT::v8i16, + SDOperand FSMBmask = DAG.getNode(SPUISD::SELECT_MASK, MVT::v8i16, DAG.getConstant(0x2222, MVT::i16)); SDOperand LoProdParts = @@ -2293,6 +2301,64 @@ DAG.getConstant(4, MVT::i32)))); } + case ISD::ADD: { + // Turn operands into vectors to satisfy type checking (shufb works on + // vectors) + SDOperand Op0 = + DAG.getNode(SPUISD::PROMOTE_SCALAR, MVT::v2i64, Op.getOperand(0)); + SDOperand Op1 = + DAG.getNode(SPUISD::PROMOTE_SCALAR, MVT::v2i64, Op.getOperand(1)); + SmallVector ShufBytes; + + // Create the shuffle mask for "rotating" the borrow up one register slot + // once the borrow is generated. + ShufBytes.push_back(DAG.getConstant(0x04050607, MVT::i32)); + ShufBytes.push_back(DAG.getConstant(0x80808080, MVT::i32)); + ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, MVT::i32)); + ShufBytes.push_back(DAG.getConstant(0x80808080, MVT::i32)); + + SDOperand CarryGen = + DAG.getNode(SPUISD::CARRY_GENERATE, MVT::v2i64, Op0, Op1); + SDOperand ShiftedCarry = + DAG.getNode(SPUISD::SHUFB, MVT::v2i64, + CarryGen, CarryGen, + DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, + &ShufBytes[0], ShufBytes.size())); + + return DAG.getNode(SPUISD::EXTRACT_ELT0, MVT::i64, + DAG.getNode(SPUISD::ADD_EXTENDED, MVT::v2i64, + Op0, Op1, ShiftedCarry)); + } + + case ISD::SUB: { + // Turn operands into vectors to satisfy type checking (shufb works on + // vectors) + SDOperand Op0 = + DAG.getNode(SPUISD::PROMOTE_SCALAR, MVT::v2i64, Op.getOperand(0)); + SDOperand Op1 = + DAG.getNode(SPUISD::PROMOTE_SCALAR, MVT::v2i64, Op.getOperand(1)); + SmallVector ShufBytes; + + // Create the shuffle mask for "rotating" the borrow up one register slot + // once the borrow is generated. + ShufBytes.push_back(DAG.getConstant(0x04050607, MVT::i32)); + ShufBytes.push_back(DAG.getConstant(0xc0c0c0c0, MVT::i32)); + ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, MVT::i32)); + ShufBytes.push_back(DAG.getConstant(0xc0c0c0c0, MVT::i32)); + + SDOperand BorrowGen = + DAG.getNode(SPUISD::BORROW_GENERATE, MVT::v2i64, Op0, Op1); + SDOperand ShiftedBorrow = + DAG.getNode(SPUISD::SHUFB, MVT::v2i64, + BorrowGen, BorrowGen, + DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, + &ShufBytes[0], ShufBytes.size())); + + return DAG.getNode(SPUISD::EXTRACT_ELT0, MVT::i64, + DAG.getNode(SPUISD::SUB_EXTENDED, MVT::v2i64, + Op0, Op1, ShiftedBorrow)); + } + case ISD::SHL: { SDOperand ShiftAmt = Op.getOperand(1); unsigned ShiftAmtVT = unsigned(ShiftAmt.getValueType()); @@ -2301,7 +2367,7 @@ DAG.getNode(SPUISD::SELB, VecVT, Op0Vec, DAG.getConstant(0, VecVT), - DAG.getNode(SPUISD::FSMBI, VecVT, + DAG.getNode(SPUISD::SELECT_MASK, VecVT, DAG.getConstant(0xff00ULL, MVT::i16))); SDOperand ShiftAmtBytes = DAG.getNode(ISD::SRL, ShiftAmtVT, @@ -2337,6 +2403,43 @@ Op0, ShiftAmtBytes), ShiftAmtBits); } + + case ISD::SRA: { + // Promote Op0 to vector + SDOperand Op0 = + DAG.getNode(SPUISD::PROMOTE_SCALAR, MVT::v2i64, Op.getOperand(0)); + SDOperand ShiftAmt = Op.getOperand(1); + unsigned ShiftVT = ShiftAmt.getValueType(); + + // Negate variable shift amounts + if (!isa(ShiftAmt)) { + ShiftAmt = DAG.getNode(ISD::SUB, ShiftVT, + DAG.getConstant(0, ShiftVT), ShiftAmt); + } + + SDOperand UpperHalfSign = + DAG.getNode(SPUISD::EXTRACT_ELT0, MVT::i32, + DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, + DAG.getNode(SPUISD::VEC_SRA, MVT::v2i64, + Op0, DAG.getConstant(31, MVT::i32)))); + SDOperand UpperHalfSignMask = + DAG.getNode(SPUISD::SELECT_MASK, MVT::v2i64, UpperHalfSign); + SDOperand UpperLowerMask = + DAG.getNode(SPUISD::SELECT_MASK, MVT::v2i64, + DAG.getConstant(0xff00, MVT::i16)); + SDOperand UpperLowerSelect = + DAG.getNode(SPUISD::SELB, MVT::v2i64, + UpperHalfSignMask, Op0, UpperLowerMask); + SDOperand RotateLeftBytes = + DAG.getNode(SPUISD::ROTBYTES_LEFT_BITS, MVT::v2i64, + UpperLowerSelect, ShiftAmt); + SDOperand RotateLeftBits = + DAG.getNode(SPUISD::ROTBYTES_LEFT, MVT::v2i64, + RotateLeftBytes, ShiftAmt); + + return DAG.getNode(SPUISD::EXTRACT_ELT0, MVT::i64, + RotateLeftBits); + } } return SDOperand(); @@ -2567,17 +2670,19 @@ case ISD::ZERO_EXTEND: case ISD::SIGN_EXTEND: case ISD::ANY_EXTEND: + case ISD::ADD: case ISD::SUB: case ISD::ROTR: case ISD::ROTL: case ISD::SRL: case ISD::SHL: - case ISD::SRA: + case ISD::SRA: { if (VT == MVT::i8) return LowerI8Math(Op, DAG, Opc); else if (VT == MVT::i64) return LowerI64Math(Op, DAG, Opc); break; + } // Vector-related lowering. case ISD::BUILD_VECTOR: @@ -2641,9 +2746,7 @@ case ISD::ADD: { SDOperand Op1 = N->getOperand(1); - if ((Op1.getOpcode() == ISD::Constant - || Op1.getOpcode() == ISD::TargetConstant) - && Op0.getOpcode() == SPUISD::IndirectAddr) { + if (isa(Op1) && Op0.getOpcode() == SPUISD::IndirectAddr) { SDOperand Op01 = Op0.getOperand(1); if (Op01.getOpcode() == ISD::Constant || Op01.getOpcode() == ISD::TargetConstant) { @@ -2662,8 +2765,7 @@ return DAG.getNode(SPUISD::IndirectAddr, Op0.getValueType(), Op0.getOperand(0), combinedConst); } - } else if ((Op0.getOpcode() == ISD::Constant - || Op0.getOpcode() == ISD::TargetConstant) + } else if (isa(Op0) && Op1.getOpcode() == SPUISD::IndirectAddr) { SDOperand Op11 = Op1.getOperand(1); if (Op11.getOpcode() == ISD::Constant @@ -2899,11 +3001,11 @@ case SPUISD::ROTBYTES_RIGHT_S: case SPUISD::ROTBYTES_LEFT: case SPUISD::ROTBYTES_LEFT_CHAINED: - case FSMBI: - case SELB: - case FPInterp: - case FPRecipEst: - case SEXT32TO64: + case SPUISD::SELECT_MASK: + case SPUISD::SELB: + case SPUISD::FPInterp: + case SPUISD::FPRecipEst: + case SPUISD::SEXT32TO64: #endif } } Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h?rev=51884&r1=51883&r2=51884&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h (original) +++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h Mon Jun 2 17:18:03 2008 @@ -62,8 +62,13 @@ ROTBYTES_RIGHT_S, ///< Vector rotate right, by bytes, sign fill ROTBYTES_LEFT, ///< Rotate bytes (loads -> ROTQBYI) ROTBYTES_LEFT_CHAINED, ///< Rotate bytes (loads -> ROTQBYI), with chain - FSMBI, ///< Form Select Mask for Bytes, Immediate + ROTBYTES_LEFT_BITS, ///< Rotate bytes left by bit shift count + SELECT_MASK, ///< Select Mask (FSM, FSMB, FSMH, FSMBI) SELB, ///< Select bits -> (b & mask) | (a & ~mask) + ADD_EXTENDED, ///< Add extended, with carry + CARRY_GENERATE, ///< Carry generate for ADD_EXTENDED + SUB_EXTENDED, ///< Subtract extended, with borrow + BORROW_GENERATE, ///< Borrow generate for SUB_EXTENDED FPInterp, ///< Floating point interpolate FPRecipEst, ///< Floating point reciprocal estimate SEXT32TO64, ///< Sign-extended 32-bit const -> 64-bits Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td?rev=51884&r1=51883&r2=51884&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td (original) +++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td Mon Jun 2 17:18:03 2008 @@ -469,7 +469,7 @@ RI16Form<0b101001100, (outs VECREG:$rT), (ins u16imm:$val), "fsmbi\t$rT, $val", SelectOp, - [(set (vectype VECREG:$rT), (SPUfsmbi (i16 immU16:$val)))]>; + [(set (vectype VECREG:$rT), (SPUselmask (i16 immU16:$val)))]>; multiclass FormSelectMaskBytesImm { @@ -485,21 +485,37 @@ def FSMB: RRForm_1<0b01101101100, (outs VECREG:$rT), (ins R16C:$rA), "fsmb\t$rT, $rA", SelectOp, - [(set (v16i8 VECREG:$rT), (SPUfsmbi R16C:$rA))]>; + [(set (v16i8 VECREG:$rT), (SPUselmask R16C:$rA))]>; // fsmh: Form select mask for halfwords. N.B., Input operand, $rA, is // only 8-bits wide (even though it's input as 16-bits here) def FSMH: RRForm_1<0b10101101100, (outs VECREG:$rT), (ins R16C:$rA), "fsmh\t$rT, $rA", SelectOp, - [(set (v8i16 VECREG:$rT), (SPUfsmbi R16C:$rA))]>; + [(set (v8i16 VECREG:$rT), (SPUselmask R16C:$rA))]>; // fsm: Form select mask for words. Like the other fsm* instructions, // only the lower 4 bits of $rA are significant. -def FSM: - RRForm_1<0b00101101100, (outs VECREG:$rT), (ins R16C:$rA), - "fsm\t$rT, $rA", SelectOp, - [(set (v4i32 VECREG:$rT), (SPUfsmbi R16C:$rA))]>; +class FSMInst: + RRForm_1<0b00101101100, (outs VECREG:$rT), (ins rclass:$rA), + "fsm\t$rT, $rA", + SelectOp, + [(set (vectype VECREG:$rT), (SPUselmask rclass:$rA))]>; + +multiclass FormSelectMaskWord { + def r32 : FSMInst; + def r16 : FSMInst; +} + +defm FSM : FormSelectMaskWord; + +// Special case when used for i64 math operations +multiclass FormSelectMaskWord64 { + def r32 : FSMInst; + def r16 : FSMInst; +} + +defm FSM64 : FormSelectMaskWord64; //===----------------------------------------------------------------------===// // Integer and Logical Operations: @@ -545,7 +561,7 @@ def Ar8: RRForm<0b00000011000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB), "a\t$rT, $rA, $rB", IntegerOp, - [(set R8C:$rT, (add R8C:$rA, R8C:$rB))]>; + [/* no pattern */]>; def AIvec: RI10Form<0b00111000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val), @@ -600,42 +616,125 @@ [(set R32C:$rT, (sub i32ImmSExt10:$val, R32C:$rA))]>; // ADDX: only available in vector form, doesn't match a pattern. -def ADDXvec: - RRForm<0b00000010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, - VECREG:$rCarry), - "addx\t$rT, $rA, $rB", IntegerOp, - []>, +class ADDXInst pattern>: + RRForm<0b00000010110, OOL, IOL, + "addx\t$rT, $rA, $rB", + IntegerOp, pattern>; + +class ADDXVecInst: + ADDXInst<(outs VECREG:$rT), + (ins VECREG:$rA, VECREG:$rB, VECREG:$rCarry), + [(set (vectype VECREG:$rT), + (SPUaddx (vectype VECREG:$rA), (vectype VECREG:$rB), + (vectype VECREG:$rCarry)))]>, RegConstraint<"$rCarry = $rT">, NoEncode<"$rCarry">; -// CG: only available in vector form, doesn't match a pattern. -def CGvec: - RRForm<0b01000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, - VECREG:$rCarry), - "cg\t$rT, $rA, $rB", IntegerOp, - []>, +class ADDXRegInst: + ADDXInst<(outs rclass:$rT), + (ins rclass:$rA, rclass:$rB, rclass:$rCarry), + [(set rclass:$rT, + (SPUaddx rclass:$rA, rclass:$rB, rclass:$rCarry))]>, RegConstraint<"$rCarry = $rT">, NoEncode<"$rCarry">; -// SFX: only available in vector form, doesn't match a pattern -def SFXvec: - RRForm<0b10000010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, - VECREG:$rCarry), - "sfx\t$rT, $rA, $rB", IntegerOp, - []>, +multiclass AddExtended { + def v2i64 : ADDXVecInst; + def v4i32 : ADDXVecInst; + def r64 : ADDXRegInst; + def r32 : ADDXRegInst; +} + +defm ADDX : AddExtended; + +// CG: Generate carry for add +class CGInst pattern>: + RRForm<0b01000011000, OOL, IOL, + "cg\t$rT, $rA, $rB", + IntegerOp, pattern>; + +class CGVecInst: + CGInst<(outs VECREG:$rT), + (ins VECREG:$rA, VECREG:$rB), + [(set (vectype VECREG:$rT), + (SPUcarry_gen (vectype VECREG:$rA), (vectype VECREG:$rB)))]>; + +class CGRegInst: + CGInst<(outs rclass:$rT), + (ins rclass:$rA, rclass:$rB), + [(set rclass:$rT, + (SPUcarry_gen rclass:$rA, rclass:$rB))]>; + +multiclass CarryGenerate { + def v2i64 : CGVecInst; + def v4i32 : CGVecInst; + def r64 : CGRegInst; + def r32 : CGRegInst; +} + +defm CG : CarryGenerate; + +// SFX: Subract from, extended. This is used in conjunction with BG to subtract +// with carry (borrow, in this case) +class SFXInst pattern>: + RRForm<0b10000010110, OOL, IOL, + "sfx\t$rT, $rA, $rB", + IntegerOp, pattern>; + +class SFXVecInst: + SFXInst<(outs VECREG:$rT), + (ins VECREG:$rA, VECREG:$rB, VECREG:$rCarry), + [(set (vectype VECREG:$rT), + (SPUsubx (vectype VECREG:$rA), (vectype VECREG:$rB), + (vectype VECREG:$rCarry)))]>, RegConstraint<"$rCarry = $rT">, NoEncode<"$rCarry">; -// BG: only available in vector form, doesn't match a pattern. -def BGvec: - RRForm<0b01000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, - VECREG:$rCarry), - "bg\t$rT, $rA, $rB", IntegerOp, - []>, +class SFXRegInst: + SFXInst<(outs rclass:$rT), + (ins rclass:$rA, rclass:$rB, rclass:$rCarry), + [(set rclass:$rT, + (SPUsubx rclass:$rA, rclass:$rB, rclass:$rCarry))]>, RegConstraint<"$rCarry = $rT">, NoEncode<"$rCarry">; -// BGX: only available in vector form, doesn't match a pattern. +multiclass SubtractExtended { + def v2i64 : SFXVecInst; + def v4i32 : SFXVecInst; + def r64 : SFXRegInst; + def r32 : SFXRegInst; +} + +defm SFX : SubtractExtended; + +// BG: only available in vector form, doesn't match a pattern. +class BGInst pattern>: + RRForm<0b01000010000, OOL, IOL, + "bg\t$rT, $rA, $rB", + IntegerOp, pattern>; + +class BGVecInst: + BGInst<(outs VECREG:$rT), + (ins VECREG:$rA, VECREG:$rB), + [(set (vectype VECREG:$rT), + (SPUborrow_gen (vectype VECREG:$rA), (vectype VECREG:$rB)))]>; + +class BGRegInst: + BGInst<(outs rclass:$rT), + (ins rclass:$rA, rclass:$rB), + [(set rclass:$rT, + (SPUborrow_gen rclass:$rA, rclass:$rB))]>; + +multiclass BorrowGenerate { + def v4i32 : BGVecInst; + def v2i64 : BGVecInst; + def r64 : BGRegInst; + def r32 : BGRegInst; +} + +defm BG : BorrowGenerate; + +// BGX: Borrow generate, extended. def BGXvec: RRForm<0b11000010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rCarry), @@ -817,17 +916,17 @@ def CNTBv16i8: RRForm_1<0b00101101010, (outs VECREG:$rT), (ins VECREG:$rA), "cntb\t$rT, $rA", IntegerOp, - [(set (v16i8 VECREG:$rT), (SPUcntb_v16i8 (v16i8 VECREG:$rA)))]>; + [(set (v16i8 VECREG:$rT), (SPUcntb (v16i8 VECREG:$rA)))]>; def CNTBv8i16 : RRForm_1<0b00101101010, (outs VECREG:$rT), (ins VECREG:$rA), "cntb\t$rT, $rA", IntegerOp, - [(set (v8i16 VECREG:$rT), (SPUcntb_v8i16 (v8i16 VECREG:$rA)))]>; + [(set (v8i16 VECREG:$rT), (SPUcntb (v8i16 VECREG:$rA)))]>; def CNTBv4i32 : RRForm_1<0b00101101010, (outs VECREG:$rT), (ins VECREG:$rA), "cntb\t$rT, $rA", IntegerOp, - [(set (v4i32 VECREG:$rT), (SPUcntb_v4i32 (v4i32 VECREG:$rA)))]>; + [(set (v4i32 VECREG:$rT), (SPUcntb (v4i32 VECREG:$rA)))]>; // gbb: Gather all low order bits from each byte in $rA into a single 16-bit // quantity stored into $rT @@ -869,31 +968,38 @@ []>; // Sign extension operations: -def XSBHvec: - RRForm_1<0b01101101010, (outs VECREG:$rDst), (ins VECREG:$rSrc), - "xsbh\t$rDst, $rSrc", IntegerOp, - [(set (v8i16 VECREG:$rDst), (sext (v16i8 VECREG:$rSrc)))]>; - -// Ordinary form for XSBH -def XSBHr16: - RRForm_1<0b01101101010, (outs R16C:$rDst), (ins R16C:$rSrc), - "xsbh\t$rDst, $rSrc", IntegerOp, - [(set R16C:$rDst, (sext_inreg R16C:$rSrc, i8))]>; +class XSBHInst pattern>: + RRForm_1<0b01101101010, OOL, IOL, + "xsbh\t$rDst, $rSrc", + IntegerOp, pattern>; + +class XSBHVecInst: + XSBHInst<(outs VECREG:$rDst), (ins VECREG:$rSrc), + [(set (v8i16 VECREG:$rDst), (sext (vectype VECREG:$rSrc)))]>; + +class XSBHRegInst: + XSBHInst<(outs rclass:$rDst), (ins rclass:$rSrc), + [(set rclass:$rDst, (sext_inreg rclass:$rSrc, i8))]>; + +multiclass ExtendByteHalfword { + def v16i8: XSBHVecInst; + def r16: XSBHRegInst; + + // 32-bit form for XSBH: used to sign extend 8-bit quantities to 16-bit + // quantities to 32-bit quantities via a 32-bit register (see the sext 8->32 + // pattern below). Intentionally doesn't match a pattern because we want the + // sext 8->32 pattern to do the work for us, namely because we need the extra + // XSHWr32. + def r32: XSBHRegInst; +} + +defm XSBH : ExtendByteHalfword; +// Sign-extend, but take an 8-bit register to a 16-bit register (not done as +// sext_inreg) def XSBHr8: - RRForm_1<0b01101101010, (outs R16C:$rDst), (ins R8C:$rSrc), - "xsbh\t$rDst, $rSrc", IntegerOp, - [(set R16C:$rDst, (sext R8C:$rSrc))]>; - -// 32-bit form for XSBH: used to sign extend 8-bit quantities to 16-bit -// quantities to 32-bit quantities via a 32-bit register (see the sext 8->32 -// pattern below). Intentionally doesn't match a pattern because we want the -// sext 8->32 pattern to do the work for us, namely because we need the extra -// XSHWr32. -def XSBHr32: - RRForm_1<0b01101101010, (outs R32C:$rDst), (ins R32C:$rSrc), - "xsbh\t$rDst, $rSrc", IntegerOp, - [(set R32C:$rDst, (sext_inreg R32C:$rSrc, i8))]>; + XSBHInst<(outs R16C:$rDst), (ins R8C:$rSrc), + [(set R16C:$rDst, (sext R8C:$rSrc))]>; // Sign extend halfwords to words: def XSHWvec: @@ -1658,9 +1764,9 @@ // It's this pattern that's probably the most useful, since SPUISelLowering // methods create a v16i8 vector for $rC: -class SHUFBVecPat1: +class SHUFBVecPat1: Pat<(SPUshuffle (vectype VECREG:$rA), (vectype VECREG:$rB), - (v16i8 VECREG:$rC)), + (masktype VECREG:$rC)), (inst VECREG:$rA, VECREG:$rB, VECREG:$rC)>; multiclass ShuffleBytes @@ -1676,11 +1782,19 @@ defm SHUFB : ShuffleBytes; -def : SHUFBVecPat1; -def : SHUFBVecPat1; -def : SHUFBVecPat1; -def : SHUFBVecPat1; -def : SHUFBVecPat1; +// Shuffle mask is a v16i8 vector +def : SHUFBVecPat1; +def : SHUFBVecPat1; +def : SHUFBVecPat1; +def : SHUFBVecPat1; +def : SHUFBVecPat1; + +// Shuffle mask is a v4i32 vector: +def : SHUFBVecPat1; +def : SHUFBVecPat1; +def : SHUFBVecPat1; +def : SHUFBVecPat1; +def : SHUFBVecPat1; //===----------------------------------------------------------------------===// // Shift and rotate group: @@ -2079,10 +2193,24 @@ (ROTQBYIv2i64 VECREG:$rA, uimm7:$val)>; // See ROTQBY note above. -def ROTQBYBIvec: - RI7Form<0b00110011100, (outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val), - "rotqbybi\t$rT, $rA, $val", RotateShift, - [/* intrinsic */]>; +class ROTQBYBIInst pattern>: + RI7Form<0b00110011100, OOL, IOL, + "rotqbybi\t$rT, $rA, $shift", + RotateShift, pattern>; + +class ROTQBYBIVecInst: + ROTQBYBIInst<(outs VECREG:$rT), (ins VECREG:$rA, rclass:$shift), + [(set (vectype VECREG:$rT), + (SPUrotbytes_left_bits (vectype VECREG:$rA), rclass:$shift))]>; + +multiclass RotateQuadByBytesByBitshift { + def v16i8_r32: ROTQBYBIVecInst; + def v8i16_r32: ROTQBYBIVecInst; + def v4i32_r32: ROTQBYBIVecInst; + def v2i64_r32: ROTQBYBIVecInst; +} + +defm ROTQBYBI : RotateQuadByBytesByBitshift; //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ // See ROTQBY note above. @@ -2358,7 +2486,6 @@ defm ROTQMBYI : RotateQuadBytesImm; - //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ // Rotate right and mask by bit count //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ @@ -2545,25 +2672,28 @@ (ROTMAr32 R32C:$rA, (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>; -def ROTMAIv4i32: - RRForm<0b01011110000, (outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val), - "rotmai\t$rT, $rA, $val", RotateShift, - [(set (v4i32 VECREG:$rT), - (SPUvec_sra VECREG:$rA, (i32 uimm7:$val)))]>; - -def : Pat<(SPUvec_sra VECREG:$rA, (i16 uimm7:$val)), - (ROTMAIv4i32 VECREG:$rA, uimm7:$val)>; - -def ROTMAIr32: - RRForm<0b01011110000, (outs R32C:$rT), (ins R32C:$rA, rotNeg7imm:$val), - "rotmai\t$rT, $rA, $val", RotateShift, - [(set R32C:$rT, (sra R32C:$rA, (i32 uimm7:$val)))]>; - -def : Pat<(sra R32C:$rA, (i16 uimm7:$val)), - (ROTMAIr32 R32C:$rA, uimm7:$val)>; +class ROTMAIInst pattern>: + RRForm<0b01011110000, OOL, IOL, + "rotmai\t$rT, $rA, $val", + RotateShift, pattern>; + +class ROTMAIVecInst: + ROTMAIInst<(outs VECREG:$rT), (ins VECREG:$rA, intop:$val), + [(set (vectype VECREG:$rT), + (SPUvec_sra VECREG:$rA, (inttype uimm7:$val)))]>; + +class ROTMAIRegInst: + ROTMAIInst<(outs rclass:$rT), (ins rclass:$rA, intop:$val), + [(set rclass:$rT, (sra rclass:$rA, (inttype uimm7:$val)))]>; + +multiclass RotateMaskAlgebraicImm { + def v2i64_i32 : ROTMAIVecInst; + def v4i32_i32 : ROTMAIVecInst; + def r64_i32 : ROTMAIRegInst; + def r32_i32 : ROTMAIRegInst; +} -def : Pat<(sra R32C:$rA, (i8 uimm7:$val)), - (ROTMAIr32 R32C:$rA, uimm7:$val)>; +defm ROTMAI : RotateMaskAlgebraicImm; //===----------------------------------------------------------------------===// // Branch and conditionals: Modified: llvm/trunk/lib/Target/CellSPU/SPUNodes.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUNodes.td?rev=51884&r1=51883&r2=51884&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUNodes.td (original) +++ llvm/trunk/lib/Target/CellSPU/SPUNodes.td Mon Jun 2 17:18:03 2008 @@ -36,29 +36,25 @@ ]>; // Unary, binary v16i8 operator type constraints: -def SPUv16i8_unop: SDTypeProfile<1, 1, [ - SDTCisVT<0, v16i8>, SDTCisSameAs<0, 1>]>; - def SPUv16i8_binop: SDTypeProfile<1, 2, [ SDTCisVT<0, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>; // Binary v8i16 operator type constraints: -def SPUv8i16_unop: SDTypeProfile<1, 1, [ - SDTCisVT<0, v8i16>, SDTCisSameAs<0, 1>]>; - def SPUv8i16_binop: SDTypeProfile<1, 2, [ SDTCisVT<0, v8i16>, SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>; // Binary v4i32 operator type constraints: -def SPUv4i32_unop: SDTypeProfile<1, 1, [ - SDTCisVT<0, v4i32>, SDTCisSameAs<0, 1>]>; - def SPUv4i32_binop: SDTypeProfile<1, 2, [ SDTCisVT<0, v4i32>, SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>; -// FSMBI type constraints: There are several variations for the various +// Trinary operators, e.g., addx, carry generate +def SPUIntTrinaryOp : SDTypeProfile<1, 3, [ + SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisInt<0> +]>; + +// SELECT_MASK type constraints: There are several variations for the various // vector types (this avoids having to bit_convert all over the place.) -def SPUfsmbi_type: SDTypeProfile<1, 1, [ +def SPUselmask_type: SDTypeProfile<1, 1, [ SDTCisInt<1> ]>; @@ -74,10 +70,16 @@ // Synthetic/pseudo-instructions //===----------------------------------------------------------------------===// +/// Add extended, carry generate: +def SPUaddx : SDNode<"SPUISD::ADD_EXTENDED", SPUIntTrinaryOp, []>; +def SPUcarry_gen : SDNode<"SPUISD::CARRY_GENERATE", SDTIntBinOp, []>; + +// Subtract extended, borrow generate +def SPUsubx : SDNode<"SPUISD::SUB_EXTENDED", SPUIntTrinaryOp, []>; +def SPUborrow_gen : SDNode<"SPUISD::BORROW_GENERATE", SDTIntBinOp, []>; + // SPU CNTB: -def SPUcntb_v16i8: SDNode<"SPUISD::CNTB", SPUv16i8_unop, []>; -def SPUcntb_v8i16: SDNode<"SPUISD::CNTB", SPUv8i16_unop, []>; -def SPUcntb_v4i32: SDNode<"SPUISD::CNTB", SPUv4i32_unop, []>; +def SPUcntb : SDNode<"SPUISD::CNTB", SDTIntUnaryOp>; // SPU vector shuffle node, matched by the SPUISD::SHUFB enum (see // SPUISelLowering.h): @@ -122,14 +124,23 @@ def SPUrotbytes_right_sfill: SDNode<"SPUISD::ROTBYTES_RIGHT_S", SPUvecshift_type, []>; +// Vector rotate left, bits shifted out of the left are rotated in on the right def SPUrotbytes_left: SDNode<"SPUISD::ROTBYTES_LEFT", SPUvecshift_type, []>; +// Same as above, but the node also has a chain associated (used in loads and +// stores) def SPUrotbytes_left_chained : SDNode<"SPUISD::ROTBYTES_LEFT_CHAINED", SPUvecshift_type, [SDNPHasChain]>; +// Vector rotate left by bytes, but the count is given in bits and the SPU +// internally converts it to bytes (saves an instruction to mask off lower +// three bits) +def SPUrotbytes_left_bits : SDNode<"SPUISD::ROTBYTES_LEFT_BITS", + SPUvecshift_type>; + // SPU form select mask for bytes, immediate -def SPUfsmbi: SDNode<"SPUISD::FSMBI", SPUfsmbi_type, []>; +def SPUselmask: SDNode<"SPUISD::SELECT_MASK", SPUselmask_type, []>; // SPU select bits instruction def SPUselb: SDNode<"SPUISD::SELB", SPUselb_type, []>; Modified: llvm/trunk/lib/Target/CellSPU/SPUOperands.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUOperands.td?rev=51884&r1=51883&r2=51884&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUOperands.td (original) +++ llvm/trunk/lib/Target/CellSPU/SPUOperands.td Mon Jun 2 17:18:03 2008 @@ -559,6 +559,10 @@ let PrintMethod = "printROTNeg7Imm"; } +def rotNeg7imm_i8 : Operand { + let PrintMethod = "printROTNeg7Imm"; +} + def target : Operand { let PrintMethod = "printBranchOperand"; } Modified: llvm/trunk/test/CodeGen/CellSPU/immed64.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/immed64.ll?rev=51884&r1=51883&r2=51884&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/CellSPU/immed64.ll (original) +++ llvm/trunk/test/CodeGen/CellSPU/immed64.ll Mon Jun 2 17:18:03 2008 @@ -1,16 +1,16 @@ ; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s -; RUN: grep lqa %t1.s | count 13 -; RUN: grep il %t1.s | count 22 -; RUN: grep shufb %t1.s | count 13 -; RUN: grep 65520 %t1.s | count 1 -; RUN: grep 43981 %t1.s | count 1 -; RUN: grep 13702 %t1.s | count 1 -; RUN: grep 81 %t1.s | count 2 -; RUN: grep 28225 %t1.s | count 1 -; RUN: grep 30720 %t1.s | count 1 -; RUN: grep 192 %t1.s | count 32 -; RUN: grep 128 %t1.s | count 30 -; RUN: grep 224 %t1.s | count 2 +; RUN: grep lqa %t1.s | count 13 +; RUN: grep il %t1.s | count 22 +; RUN: grep shufb %t1.s | count 13 +; RUN: grep 65520 %t1.s | count 1 +; RUN: grep 43981 %t1.s | count 1 +; RUN: grep 13702 %t1.s | count 1 +; RUN: grep 28225 %t1.s | count 1 +; RUN: grep 30720 %t1.s | count 1 +; RUN: grep 3233857728 %t1.s | count 8 +; RUN: grep 2155905152 %t1.s | count 6 +; RUN: grep 66051 %t1.s | count 7 +; RUN: grep 471670303 %t1.s | count 11 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128" target triple = "spu" From scottm at aero.org Mon Jun 2 17:19:12 2008 From: scottm at aero.org (Scott Michel) Date: Mon, 02 Jun 2008 22:19:12 -0000 Subject: [llvm-commits] [llvm] r51885 - /llvm/trunk/lib/CodeGen/AsmPrinter.cpp Message-ID: <200806022219.m52MJCeZ024222@zion.cs.uiuc.edu> Author: pingbak Date: Mon Jun 2 17:19:12 2008 New Revision: 51885 URL: http://llvm.org/viewvc/llvm-project?rev=51885&view=rev Log: Minor cosmetic patch so that the hex equivalent of a decimal constant shows up in the assembly language output. Helps with debugging without a HP calculator having to be handy. Modified: llvm/trunk/lib/CodeGen/AsmPrinter.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter.cpp?rev=51885&r1=51884&r2=51885&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter.cpp Mon Jun 2 17:19:12 2008 @@ -742,7 +742,9 @@ if (CV->isNullValue() || isa(CV)) O << "0"; else if (const ConstantInt *CI = dyn_cast(CV)) { - O << CI->getZExtValue(); + O << CI->getZExtValue() << "\t\t\t" + << TAI->getCommentString() << " 0x" + << CI->getValue().toStringUnsigned(16); } else if (const GlobalValue *GV = dyn_cast(CV)) { // This is a constant address for a global variable or function. Use the // name of the variable or function as the address value, possibly From gohman at apple.com Mon Jun 2 17:27:05 2008 From: gohman at apple.com (Dan Gohman) Date: Mon, 02 Jun 2008 22:27:05 -0000 Subject: [llvm-commits] [llvm] r51886 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Message-ID: <200806022227.m52MR5aw025627@zion.cs.uiuc.edu> Author: djg Date: Mon Jun 2 17:27:05 2008 New Revision: 51886 URL: http://llvm.org/viewvc/llvm-project?rev=51886&view=rev Log: Fold adds and subtracts of zero immediately, instead of waiting for dagcombine to do this. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=51886&r1=51885&r2=51886&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Mon Jun 2 17:27:05 2008 @@ -2115,10 +2115,12 @@ break; case ISD::OR: case ISD::XOR: + case ISD::ADD: + case ISD::SUB: assert(MVT::isInteger(VT) && N1.getValueType() == N2.getValueType() && N1.getValueType() == VT && "Binary operator types must match!"); - // (X ^| 0) -> X. This commonly occurs when legalizing i64 values, so it's - // worth handling here. + // (X ^|+- 0) -> X. This commonly occurs when legalizing i64 values, so + // it's worth handling here. if (N2C && N2C->isNullValue()) return N1; break; @@ -2128,8 +2130,6 @@ case ISD::MULHS: assert(MVT::isInteger(VT) && "This operator does not apply to FP types!"); // fall through - case ISD::ADD: - case ISD::SUB: case ISD::MUL: case ISD::SDIV: case ISD::SREM: From dpatel at apple.com Mon Jun 2 17:52:57 2008 From: dpatel at apple.com (Devang Patel) Date: Mon, 02 Jun 2008 22:52:57 -0000 Subject: [llvm-commits] [llvm] r51887 - in /llvm/trunk: lib/Transforms/Scalar/LoopUnswitch.cpp test/Transforms/LoopUnswitch/2008-06-02-DomInfo.ll Message-ID: <200806022252.m52MqvZl003079@zion.cs.uiuc.edu> Author: dpatel Date: Mon Jun 2 17:52:56 2008 New Revision: 51887 URL: http://llvm.org/viewvc/llvm-project?rev=51887&view=rev Log: Update dom tree. Fix PR 2372. Added: llvm/trunk/test/Transforms/LoopUnswitch/2008-06-02-DomInfo.ll Modified: llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp Modified: llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp?rev=51887&r1=51886&r2=51887&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp Mon Jun 2 17:52:56 2008 @@ -569,7 +569,6 @@ // Insert the new branch. BranchInst::Create(TrueDest, FalseDest, BranchVal, InsertPt); - } @@ -607,6 +606,10 @@ // insert the new conditional branch. EmitPreheaderBranchOnCondition(Cond, Val, NewExit, NewPH, OrigPH->getTerminator()); + if (DT) { + DT->changeImmediateDominator(NewExit, OrigPH); + DT->changeImmediateDominator(NewPH, OrigPH); + } LPM->deleteSimpleAnalysisValue(OrigPH->getTerminator(), L); OrigPH->getTerminator()->eraseFromParent(); Added: llvm/trunk/test/Transforms/LoopUnswitch/2008-06-02-DomInfo.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopUnswitch/2008-06-02-DomInfo.ll?rev=51887&view=auto ============================================================================== --- llvm/trunk/test/Transforms/LoopUnswitch/2008-06-02-DomInfo.ll (added) +++ llvm/trunk/test/Transforms/LoopUnswitch/2008-06-02-DomInfo.ll Mon Jun 2 17:52:56 2008 @@ -0,0 +1,26 @@ +; RUN: llvm-as < %s | opt -loop-unswitch -instcombine -gvn -disable-output +; PR2372 +target triple = "i386-pc-linux-gnu" + +define i32 @func_3(i16 signext %p_5, i16 signext %p_6) nounwind { +entry: + %tmp3 = icmp eq i16 %p_5, 0 ; [#uses=1] + %tmp1314 = sext i16 %p_6 to i32 ; [#uses=1] + %tmp28 = icmp ugt i32 %tmp1314, 3 ; [#uses=1] + %bothcond = or i1 %tmp28, false ; [#uses=1] + br label %bb +bb: ; preds = %bb54, %entry + br i1 %tmp3, label %bb54, label %bb5 +bb5: ; preds = %bb + br i1 %bothcond, label %bb54, label %bb31 +bb31: ; preds = %bb5 + br label %bb54 +bb54: ; preds = %bb31, %bb5, %bb + br i1 false, label %bb64, label %bb +bb64: ; preds = %bb54 + %tmp6566 = sext i16 %p_6 to i32 ; [#uses=1] + %tmp68 = tail call i32 (...)* @func_18( i32 1, i32 %tmp6566, i32 1 ) nounwind ; [#uses=0] + ret i32 undef +} + +declare i32 @func_18(...) From gohman at apple.com Mon Jun 2 19:15:21 2008 From: gohman at apple.com (Dan Gohman) Date: Tue, 03 Jun 2008 00:15:21 -0000 Subject: [llvm-commits] [llvm] r51889 - in /llvm/trunk: lib/VMCore/ConstantFold.cpp lib/VMCore/ConstantFold.h lib/VMCore/Constants.cpp test/Assembler/insertextractvalue.ll Message-ID: <200806030015.m530FLlc003023@zion.cs.uiuc.edu> Author: djg Date: Mon Jun 2 19:15:20 2008 New Revision: 51889 URL: http://llvm.org/viewvc/llvm-project?rev=51889&view=rev Log: Constant folding for insertvalue and extractvalue. Modified: llvm/trunk/lib/VMCore/ConstantFold.cpp llvm/trunk/lib/VMCore/ConstantFold.h llvm/trunk/lib/VMCore/Constants.cpp llvm/trunk/test/Assembler/insertextractvalue.ll Modified: llvm/trunk/lib/VMCore/ConstantFold.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/ConstantFold.cpp?rev=51889&r1=51888&r2=51889&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/ConstantFold.cpp (original) +++ llvm/trunk/lib/VMCore/ConstantFold.cpp Mon Jun 2 19:15:20 2008 @@ -394,6 +394,7 @@ } return ConstantVector::get(Ops); } + return 0; } @@ -447,18 +448,112 @@ return ConstantVector::get(&Result[0], Result.size()); } -Constant *llvm::ConstantFoldExtractValue(const Constant *Agg, - Constant* const *Idxs, - unsigned NumIdx) { - // FIXME: implement some constant folds - return 0; +Constant *llvm::ConstantFoldExtractValueInstruction(const Constant *Agg, + const unsigned *Idxs, + unsigned NumIdx) { + // Base case: no indices, so return the entire value. + if (NumIdx == 0) + return const_cast(Agg); + + if (isa(Agg)) // ev(undef, x) -> undef + return UndefValue::get(ExtractValueInst::getIndexedType(Agg->getType(), + Idxs, + Idxs + NumIdx)); + + if (isa(Agg)) // ev(0, x) -> 0 + return + Constant::getNullValue(ExtractValueInst::getIndexedType(Agg->getType(), + Idxs, + Idxs + NumIdx)); + + // Otherwise recurse. + return ConstantFoldExtractValueInstruction(Agg->getOperand(*Idxs), + Idxs+1, NumIdx-1); } -Constant *llvm::ConstantFoldInsertValue(const Constant *Agg, - const Constant *Val, - Constant* const *Idxs, - unsigned NumIdx) { - // FIXME: implement some constant folds +Constant *llvm::ConstantFoldInsertValueInstruction(const Constant *Agg, + const Constant *Val, + const unsigned *Idxs, + unsigned NumIdx) { + // Base case: no indices, so replace the entire value. + if (NumIdx == 0) + return const_cast(Val); + + if (isa(Agg)) { + // Insertion of constant into aggregate undef + // Optimize away insertion of undef + if (isa(Val)) + return const_cast(Agg); + // Otherwise break the aggregate undef into multiple undefs and do + // the insertion + const CompositeType *AggTy = cast(Agg->getType()); + unsigned numOps; + if (const ArrayType *AR = dyn_cast(AggTy)) + numOps = AR->getNumElements(); + else + numOps = cast(AggTy)->getNumElements(); + std::vector Ops(numOps); + for (unsigned i = 0; i < numOps; ++i) { + const Type *MemberTy = AggTy->getTypeAtIndex(i); + const Constant *Op = + (*Idxs == i) ? + ConstantFoldInsertValueInstruction(UndefValue::get(MemberTy), + Val, Idxs+1, NumIdx-1) : + UndefValue::get(MemberTy); + Ops[i] = const_cast(Op); + } + if (isa(AggTy)) + return ConstantStruct::get(Ops); + else + return ConstantArray::get(cast(AggTy), Ops); + } + if (isa(Agg)) { + // Insertion of constant into aggregate zero + // Optimize away insertion of zero + if (Val->isNullValue()) + return const_cast(Agg); + // Otherwise break the aggregate zero into multiple zeros and do + // the insertion + const CompositeType *AggTy = cast(Agg->getType()); + unsigned numOps; + if (const ArrayType *AR = dyn_cast(AggTy)) + numOps = AR->getNumElements(); + else + numOps = cast(AggTy)->getNumElements(); + std::vector Ops(numOps); + for (unsigned i = 0; i < numOps; ++i) { + const Type *MemberTy = AggTy->getTypeAtIndex(i); + const Constant *Op = + (*Idxs == i) ? + ConstantFoldInsertValueInstruction(Constant::getNullValue(MemberTy), + Val, Idxs+1, NumIdx-1) : + Constant::getNullValue(MemberTy); + Ops[i] = const_cast(Op); + } + if (isa(AggTy)) + return ConstantStruct::get(Ops); + else + return ConstantArray::get(cast(AggTy), Ops); + } + if (isa(Agg) || isa(Agg)) { + // Insertion of constant into aggregate constant + std::vector Ops(Agg->getNumOperands()); + for (unsigned i = 0; i < Agg->getNumOperands(); ++i) { + const Constant *Op = + (*Idxs == i) ? + ConstantFoldInsertValueInstruction(Agg->getOperand(i), + Val, Idxs+1, NumIdx-1) : + Agg->getOperand(i); + Ops[i] = const_cast(Op); + } + Constant *C; + if (isa(Agg->getType())) + C = ConstantStruct::get(Ops); + else + C = ConstantArray::get(cast(Agg->getType()), Ops); + return C; + } + return 0; } Modified: llvm/trunk/lib/VMCore/ConstantFold.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/ConstantFold.h?rev=51889&r1=51888&r2=51889&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/ConstantFold.h (original) +++ llvm/trunk/lib/VMCore/ConstantFold.h Mon Jun 2 19:15:20 2008 @@ -41,10 +41,13 @@ Constant *ConstantFoldShuffleVectorInstruction(const Constant *V1, const Constant *V2, const Constant *Mask); - Constant *ConstantFoldExtractValue(const Constant *Agg, - Constant* const *Idxs, unsigned NumIdx); - Constant *ConstantFoldInsertValue(const Constant *Agg, const Constant *Val, - Constant* const *Idxs, unsigned NumIdx); + Constant *ConstantFoldExtractValueInstruction(const Constant *Agg, + const unsigned *Idxs, + unsigned NumIdx); + Constant *ConstantFoldInsertValueInstruction(const Constant *Agg, + const Constant *Val, + const unsigned* Idxs, + unsigned NumIdx); Constant *ConstantFoldBinaryInstruction(unsigned Opcode, const Constant *V1, const Constant *V2); Constant *ConstantFoldCompareInstruction(unsigned short predicate, Modified: llvm/trunk/lib/VMCore/Constants.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Constants.cpp?rev=51889&r1=51888&r2=51889&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Constants.cpp (original) +++ llvm/trunk/lib/VMCore/Constants.cpp Mon Jun 2 19:15:20 2008 @@ -2305,9 +2305,10 @@ "insertvalue indices invalid!"); assert(Agg->getType() == ReqTy && "insertvalue type invalid!"); - assert(Agg->getType()->isFirstClassType() && "Non-first-class type for constant InsertValue expression"); + if (Constant *FC = ConstantFoldInsertValueInstruction(Agg, Val, Idxs, NumIdx)) + return FC; // Fold a few common cases... // Look up the constant in the table first to ensure uniqueness std::vector ArgVec; ArgVec.push_back(Agg); @@ -2336,6 +2337,8 @@ "extractvalue indices invalid!"); assert(Agg->getType()->isFirstClassType() && "Non-first-class type for constant extractvalue expression"); + if (Constant *FC = ConstantFoldExtractValueInstruction(Agg, Idxs, NumIdx)) + return FC; // Fold a few common cases... // Look up the constant in the table first to ensure uniqueness std::vector ArgVec; ArgVec.push_back(Agg); Modified: llvm/trunk/test/Assembler/insertextractvalue.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Assembler/insertextractvalue.ll?rev=51889&r1=51888&r2=51889&view=diff ============================================================================== --- llvm/trunk/test/Assembler/insertextractvalue.ll (original) +++ llvm/trunk/test/Assembler/insertextractvalue.ll Mon Jun 2 19:15:20 2008 @@ -1,4 +1,6 @@ -; RUN: llvm-as < %s +; RUN: llvm-as < %s | llvm-dis > %t +; RUN: grep insertvalue %t | count 1 +; RUN: grep extractvalue %t | count 1 define float @foo({{i32},{float, double}}* %p) { %t = load {{i32},{float, double}}* %p @@ -11,3 +13,11 @@ store {{i32},{float, double}} insertvalue ({{i32},{float, double}}{{i32}{i32 4},{float, double}{float 4.0, double 5.0}}, double 20.0, 1, 1), {{i32},{float, double}}* %p ret float extractvalue ({{i32},{float, double}}{{i32}{i32 3},{float, double}{float 7.0, double 9.0}}, 1, 0) } +define float @car({{i32},{float, double}}* %p) { + store {{i32},{float, double}} insertvalue ({{i32},{float, double}} undef, double 20.0, 1, 1), {{i32},{float, double}}* %p + ret float extractvalue ({{i32},{float, double}} undef, 1, 0) +} +define float @dar({{i32},{float, double}}* %p) { + store {{i32},{float, double}} insertvalue ({{i32},{float, double}} zeroinitializer, double 20.0, 1, 1), {{i32},{float, double}}* %p + ret float extractvalue ({{i32},{float, double}} zeroinitializer, 1, 0) +} From evan.cheng at apple.com Mon Jun 2 19:35:41 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 2 Jun 2008 17:35:41 -0700 Subject: [llvm-commits] [llvm-gcc-4.2] r51723 - in /llvm-gcc-4.2/trunk/gcc: config/i386/llvm-i386-target.h config/i386/llvm-i386.cpp config/rs6000/llvm-rs6000.cpp llvm-abi.h In-Reply-To: <200805300123.m4U1NDZl019942@zion.cs.uiuc.edu> References: <200805300123.m4U1NDZl019942@zion.cs.uiuc.edu> Message-ID: <4B25ACA3-2667-47BE-8483-B937CEA1719F@apple.com> Hi Dale, Looks like this patch broke 447.dealII on x86-64. Try this: make ENABLE_OPTIMIZED=1 TEST=nightly TARGET_FLAGS="-m64 - DSPEC_CPU2000_LP64 -DSPEC_CPU_LP64" TARGET_LLCFLAGS="-relocation- model=pic -disable-fp-elim" EXTRA_LLI_OPTS="-relocation-model=pic - disable-fp-elim" clean Output/447.dealII.diff-llc Evan On May 29, 2008, at 6:23 PM, Dale Johannesen wrote: > Author: johannes > Date: Thu May 29 20:23:12 2008 > New Revision: 51723 > > URL: http://llvm.org/viewvc/llvm-project?rev=51723&view=rev > Log: > X86-64 ABI fix. Revert isSingleElementStructOrArray > change in favor of a more general version which handles > the case where there's more than one element correctly. > Fixes gcc.dg/compat/struct-layout-1.exp/t003 > and many more. > > > Modified: > llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h > llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp > llvm-gcc-4.2/trunk/gcc/config/rs6000/llvm-rs6000.cpp > llvm-gcc-4.2/trunk/gcc/llvm-abi.h > > Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h > URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h?rev=51723&r1=51722&r2=51723&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h (original) > +++ llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h Thu May 29 > 20:23:12 2008 > @@ -95,17 +95,18 @@ > considered as if they were the type of the data field. */ > #ifndef LLVM_SHOULD_RETURN_SELT_STRUCT_AS_SCALAR > #define LLVM_SHOULD_RETURN_SELT_STRUCT_AS_SCALAR(X) \ > - isSingleElementStructOrArray(X, true, false, false) > + isSingleElementStructOrArray(X, true, false) > #endif > > +extern bool llvm_x86_should_pass_aggregate_in_integer_regs(tree, > unsigned*); > + > /* LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS - Return true if this > aggregate > value should be passed in integer registers. This differs from > the usual > - handling in that x86-64 passes single-int-element unions as the > type of the > - field. */ > -#define > LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS(X) \ > - > (TARGET_64BIT ? \ > - !isSingleElementStructOrArray((X), true, true, > true) : \ > - !isSingleElementStructOrArray((X), false, true, false)) > + handling in that x86-64 passes 128-bit structs and unions which > only > + contain data in the first 64 bits, as 64-bit objects. (These > can be > + created by abusing __attribute__((aligned)). */ > +#define LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS(X, > Y) \ > + llvm_x86_should_pass_aggregate_in_integer_regs((X), (Y)) > > extern bool llvm_x86_should_pass_vector_in_integer_regs(tree); > > > Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp?rev=51723&r1=51722&r2=51723&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp (original) > +++ llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp Thu May 29 > 20:23:12 2008 > @@ -1288,4 +1288,38 @@ > return Loc; > } > > +/// llvm_x86_should_pass_aggregate_in_integer_regs - x86-32 is same > as the > +/// default. x86-64 detects the case where a type is 16 bytes long > but > +/// only 8 of them are passed, the rest being padding (*size is set > to 8 > +/// to identify this case). > +bool llvm_x86_should_pass_aggregate_in_integer_regs(tree type, > unsigned *size) > +{ > + *size = 0; > + if (TARGET_64BIT) { > + enum x86_64_reg_class Class[MAX_CLASSES]; > + enum machine_mode Mode = ix86_getNaturalModeForType(type); > + int NumClasses = ix86_ClassifyArgument(Mode, type, Class, 0); > + if (NumClasses == 1 && (Class[0] == X86_64_INTEGERSI_CLASS || > + Class[0] == X86_64_INTEGER_CLASS)) { > + /* 8 byte object, one int register */ > + return true; > + } > + if (NumClasses == 2 && (Class[0] == X86_64_INTEGERSI_CLASS || > + Class[0] == X86_64_INTEGER_CLASS)) { > + if (Class[1] == X86_64_INTEGERSI_CLASS || > + Class[1] == X86_64_INTEGER_CLASS) > + /* 16 byte object, 2 int registers */ > + return true; > + if (Class[1] == X86_64_NO_CLASS) { > + /* 16 byte object, only 1st register has information */ > + *size = 8; > + return true; > + } > + } > + return false; > + } > + else > + return !isSingleElementStructOrArray(type, false, true); > +} > + > /* LLVM LOCAL end (ENTIRE FILE!) */ > > Modified: llvm-gcc-4.2/trunk/gcc/config/rs6000/llvm-rs6000.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/rs6000/llvm-rs6000.cpp?rev=51723&r1=51722&r2=51723&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm-gcc-4.2/trunk/gcc/config/rs6000/llvm-rs6000.cpp (original) > +++ llvm-gcc-4.2/trunk/gcc/config/rs6000/llvm-rs6000.cpp Thu May 29 > 20:23:12 2008 > @@ -404,7 +404,7 @@ > // some zero-length fields as well, must be passed as the field > type. > // Note this does not apply to long double. > // This is required for ABI correctness. > - tree tType = isSingleElementStructOrArray(TreeType, true, false, > false); > + tree tType = isSingleElementStructOrArray(TreeType, true, false); > if (tType && int_size_in_bytes(tType)==Bytes && TYPE_MODE(tType)! > =TFmode && > (TREE_CODE(tType)!=VECTOR_TYPE || Bytes==16)) > return false; > @@ -437,7 +437,7 @@ > // Other single-element structs may be passed this way as well, but > // only if the type size matches the element's type size (structs > that > // violate this can be created with __aligned__). > - tree tType = isSingleElementStructOrArray(TreeType, true, false, > false); > + tree tType = isSingleElementStructOrArray(TreeType, true, false); > if (tType && int_size_in_bytes(tType)==SrcSize && TYPE_MODE(tType)! > =TFmode && > (TREE_CODE(tType)!=VECTOR_TYPE || SrcSize==16)) { > Elts.push_back(ConvertType(tType)); > > Modified: llvm-gcc-4.2/trunk/gcc/llvm-abi.h > URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-abi.h?rev=51723&r1=51722&r2=51723&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm-gcc-4.2/trunk/gcc/llvm-abi.h (original) > +++ llvm-gcc-4.2/trunk/gcc/llvm-abi.h Thu May 29 20:23:12 2008 > @@ -138,21 +138,17 @@ > /// rejectFatBitField, and the single element is a bitfield of a > type that's > /// bigger than the struct, return null anyway. > static tree isSingleElementStructOrArray(tree type, bool > ignoreZeroLength, > - bool rejectFatBitfield, > - bool acceptUnions) { > + bool rejectFatBitfield) { > // Scalars are good. > if (!isAggregateTreeType(type)) return type; > > tree FoundField = 0; > switch (TREE_CODE(type)) { > case QUAL_UNION_TYPE: > + case UNION_TYPE: // Single element unions don't count. > case COMPLEX_TYPE: // Complex values are like 2-element records. > default: > return 0; > - case UNION_TYPE: // Single element unions don't count. > - if (!acceptUnions) > - return 0; > - // fall through > case RECORD_TYPE: > // If this record has variable length, reject it. > if (TREE_CODE(TYPE_SIZE(type)) != INTEGER_CST) > @@ -178,15 +174,13 @@ > } > } > return FoundField ? isSingleElementStructOrArray(FoundField, > - > ignoreZeroLength, false, > - false) > + > ignoreZeroLength, false) > : 0; > case ARRAY_TYPE: > const ArrayType *Ty = dyn_cast(ConvertType(type)); > if (!Ty || Ty->getNumElements() != 1) > return 0; > - return isSingleElementStructOrArray(TREE_TYPE(type), false, > false, > - false); > + return isSingleElementStructOrArray(TREE_TYPE(type), false, > false); > } > } > > @@ -283,8 +277,8 @@ > // single element is a bitfield of a type bigger than the struct; > the code > // for field-by-field struct passing does not handle this one right. > #ifndef LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS > -#define LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS(X) \ > - !isSingleElementStructOrArray(X, false, true, false) > +#define LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS(X, Y) \ > + !isSingleElementStructOrArray((X), false, true) > #endif > > // LLVM_SHOULD_RETURN_SELT_STRUCT_AS_SCALAR - Return a TYPE tree if > this single > @@ -295,7 +289,7 @@ > // by abusing the __aligned__ attribute.) > #ifndef LLVM_SHOULD_RETURN_SELT_STRUCT_AS_SCALAR > #define LLVM_SHOULD_RETURN_SELT_STRUCT_AS_SCALAR(X) \ > - isSingleElementStructOrArray(X, false, false, false) > + isSingleElementStructOrArray(X, false, false) > #endif > > // LLVM_SHOULD_RETURN_VECTOR_AS_SCALAR - Return a TYPE tree if this > vector type > @@ -408,6 +402,7 @@ > /// their fields. > void HandleArgument(tree type, std::vector &ScalarElts, > ParameterAttributes *Attributes = NULL) { > + unsigned Size = 0; > const Type *Ty = ConvertType(type); > // Figure out if this field is zero bits wide, e.g. {} or [0 x > int]. Do > // not include variable sized fields here. > @@ -418,7 +413,7 @@ > ScalarElts.push_back(PtrTy); > } else if (Ty->getTypeID()==Type::VectorTyID) { > if (LLVM_SHOULD_PASS_VECTOR_IN_INTEGER_REGS(type)) { > - PassInIntegerRegisters(type, Ty, ScalarElts); > + PassInIntegerRegisters(type, Ty, ScalarElts, 0); > } else { > C.HandleScalarArgument(Ty, type); > ScalarElts.push_back(Ty); > @@ -444,8 +439,8 @@ > *Attributes |= > > ParamAttr::constructAlignmentFromInt(LLVM_BYVAL_ALIGNMENT(type)); > } > - } else if (LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS(type)) { > - PassInIntegerRegisters(type, Ty, ScalarElts); > + } else if (LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS(type, > &Size)) { > + PassInIntegerRegisters(type, Ty, ScalarElts, Size); > } else if (isZeroSizedStructOrUnion(type)) { > // Zero sized struct or union, just drop it! > ; > @@ -526,10 +521,15 @@ > > /// PassInIntegerRegisters - Given an aggregate value that should > be passed in > /// integer registers, convert it to a structure containing ints > and pass all > - /// of the struct elements in. > + /// of the struct elements in. If Size is set we pass only that > many bytes. > void PassInIntegerRegisters(tree type, const Type *Ty, > - std::vector &ScalarElts) { > - unsigned Size = TREE_INT_CST_LOW(TYPE_SIZE(type))/8; > + std::vector &ScalarElts, > + unsigned origSize) { > + unsigned Size; > + if (origSize) > + Size = origSize; > + else > + Size = TREE_INT_CST_LOW(TYPE_SIZE(type))/8; > > // FIXME: We should preserve all aggregate value alignment > information. > // Work around to preserve some aggregate value alignment > information: > @@ -568,7 +568,7 @@ > Elts.push_back(Type::Int8Ty); > Size -= 1; > } > - assert(Size == 0 && "Didn't cover value?"); > + assert((origSize || Size == 0) && "Didn't cover value?"); > const StructType *STy = StructType::get(Elts, false); > > unsigned i = 0; > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From dalej at apple.com Mon Jun 2 19:40:20 2008 From: dalej at apple.com (Dale Johannesen) Date: Mon, 2 Jun 2008 17:40:20 -0700 Subject: [llvm-commits] [llvm-gcc-4.2] r51723 - in /llvm-gcc-4.2/trunk/gcc: config/i386/llvm-i386-target.h config/i386/llvm-i386.cpp config/rs6000/llvm-rs6000.cpp llvm-abi.h In-Reply-To: <4B25ACA3-2667-47BE-8483-B937CEA1719F@apple.com> References: <200805300123.m4U1NDZl019942@zion.cs.uiuc.edu> <4B25ACA3-2667-47BE-8483-B937CEA1719F@apple.com> Message-ID: I'll look. On Jun 2, 2008, at 5:35 PM, Evan Cheng wrote: > Hi Dale, > > Looks like this patch broke 447.dealII on x86-64. Try this: > > make ENABLE_OPTIMIZED=1 TEST=nightly TARGET_FLAGS="-m64 - > DSPEC_CPU2000_LP64 -DSPEC_CPU_LP64" TARGET_LLCFLAGS="-relocation- > model=pic -disable-fp-elim" EXTRA_LLI_OPTS="-relocation-model=pic - > disable-fp-elim" clean Output/447.dealII.diff-llc > > Evan > > On May 29, 2008, at 6:23 PM, Dale Johannesen wrote: > >> Author: johannes >> Date: Thu May 29 20:23:12 2008 >> New Revision: 51723 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=51723&view=rev >> Log: >> X86-64 ABI fix. Revert isSingleElementStructOrArray >> change in favor of a more general version which handles >> the case where there's more than one element correctly. >> Fixes gcc.dg/compat/struct-layout-1.exp/t003 >> and many more. >> >> >> Modified: >> llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h >> llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp >> llvm-gcc-4.2/trunk/gcc/config/rs6000/llvm-rs6000.cpp >> llvm-gcc-4.2/trunk/gcc/llvm-abi.h >> >> Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h >> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h?rev=51723&r1=51722&r2=51723&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h (original) >> +++ llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h Thu May >> 29 20:23:12 2008 >> @@ -95,17 +95,18 @@ >> considered as if they were the type of the data field. */ >> #ifndef LLVM_SHOULD_RETURN_SELT_STRUCT_AS_SCALAR >> #define LLVM_SHOULD_RETURN_SELT_STRUCT_AS_SCALAR(X) \ >> - isSingleElementStructOrArray(X, true, false, false) >> + isSingleElementStructOrArray(X, true, false) >> #endif >> >> +extern bool llvm_x86_should_pass_aggregate_in_integer_regs(tree, >> unsigned*); >> + >> /* LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS - Return true if this >> aggregate >> value should be passed in integer registers. This differs from >> the usual >> - handling in that x86-64 passes single-int-element unions as the >> type of the >> - field. */ >> -#define >> LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS(X) \ >> - >> (TARGET_64BIT ? \ >> - !isSingleElementStructOrArray((X), true, true, >> true) : \ >> - !isSingleElementStructOrArray((X), false, true, false)) >> + handling in that x86-64 passes 128-bit structs and unions which >> only >> + contain data in the first 64 bits, as 64-bit objects. (These >> can be >> + created by abusing __attribute__((aligned)). */ >> +#define LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS(X, >> Y) \ >> + llvm_x86_should_pass_aggregate_in_integer_regs((X), (Y)) >> >> extern bool llvm_x86_should_pass_vector_in_integer_regs(tree); >> >> >> Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp?rev=51723&r1=51722&r2=51723&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp (original) >> +++ llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp Thu May 29 >> 20:23:12 2008 >> @@ -1288,4 +1288,38 @@ >> return Loc; >> } >> >> +/// llvm_x86_should_pass_aggregate_in_integer_regs - x86-32 is >> same as the >> +/// default. x86-64 detects the case where a type is 16 bytes >> long but >> +/// only 8 of them are passed, the rest being padding (*size is >> set to 8 >> +/// to identify this case). >> +bool llvm_x86_should_pass_aggregate_in_integer_regs(tree type, >> unsigned *size) >> +{ >> + *size = 0; >> + if (TARGET_64BIT) { >> + enum x86_64_reg_class Class[MAX_CLASSES]; >> + enum machine_mode Mode = ix86_getNaturalModeForType(type); >> + int NumClasses = ix86_ClassifyArgument(Mode, type, Class, 0); >> + if (NumClasses == 1 && (Class[0] == X86_64_INTEGERSI_CLASS || >> + Class[0] == X86_64_INTEGER_CLASS)) { >> + /* 8 byte object, one int register */ >> + return true; >> + } >> + if (NumClasses == 2 && (Class[0] == X86_64_INTEGERSI_CLASS || >> + Class[0] == X86_64_INTEGER_CLASS)) { >> + if (Class[1] == X86_64_INTEGERSI_CLASS || >> + Class[1] == X86_64_INTEGER_CLASS) >> + /* 16 byte object, 2 int registers */ >> + return true; >> + if (Class[1] == X86_64_NO_CLASS) { >> + /* 16 byte object, only 1st register has information */ >> + *size = 8; >> + return true; >> + } >> + } >> + return false; >> + } >> + else >> + return !isSingleElementStructOrArray(type, false, true); >> +} >> + >> /* LLVM LOCAL end (ENTIRE FILE!) */ >> >> Modified: llvm-gcc-4.2/trunk/gcc/config/rs6000/llvm-rs6000.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/rs6000/llvm-rs6000.cpp?rev=51723&r1=51722&r2=51723&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm-gcc-4.2/trunk/gcc/config/rs6000/llvm-rs6000.cpp (original) >> +++ llvm-gcc-4.2/trunk/gcc/config/rs6000/llvm-rs6000.cpp Thu May 29 >> 20:23:12 2008 >> @@ -404,7 +404,7 @@ >> // some zero-length fields as well, must be passed as the field >> type. >> // Note this does not apply to long double. >> // This is required for ABI correctness. >> - tree tType = isSingleElementStructOrArray(TreeType, true, false, >> false); >> + tree tType = isSingleElementStructOrArray(TreeType, true, false); >> if (tType && int_size_in_bytes(tType)==Bytes && TYPE_MODE(tType)! >> =TFmode && >> (TREE_CODE(tType)!=VECTOR_TYPE || Bytes==16)) >> return false; >> @@ -437,7 +437,7 @@ >> // Other single-element structs may be passed this way as well, but >> // only if the type size matches the element's type size (structs >> that >> // violate this can be created with __aligned__). >> - tree tType = isSingleElementStructOrArray(TreeType, true, false, >> false); >> + tree tType = isSingleElementStructOrArray(TreeType, true, false); >> if (tType && int_size_in_bytes(tType)==SrcSize && TYPE_MODE(tType)! >> =TFmode && >> (TREE_CODE(tType)!=VECTOR_TYPE || SrcSize==16)) { >> Elts.push_back(ConvertType(tType)); >> >> Modified: llvm-gcc-4.2/trunk/gcc/llvm-abi.h >> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-abi.h?rev=51723&r1=51722&r2=51723&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm-gcc-4.2/trunk/gcc/llvm-abi.h (original) >> +++ llvm-gcc-4.2/trunk/gcc/llvm-abi.h Thu May 29 20:23:12 2008 >> @@ -138,21 +138,17 @@ >> /// rejectFatBitField, and the single element is a bitfield of a >> type that's >> /// bigger than the struct, return null anyway. >> static tree isSingleElementStructOrArray(tree type, bool >> ignoreZeroLength, >> - bool rejectFatBitfield, >> - bool acceptUnions) { >> + bool rejectFatBitfield) { >> // Scalars are good. >> if (!isAggregateTreeType(type)) return type; >> >> tree FoundField = 0; >> switch (TREE_CODE(type)) { >> case QUAL_UNION_TYPE: >> + case UNION_TYPE: // Single element unions don't count. >> case COMPLEX_TYPE: // Complex values are like 2-element records. >> default: >> return 0; >> - case UNION_TYPE: // Single element unions don't count. >> - if (!acceptUnions) >> - return 0; >> - // fall through >> case RECORD_TYPE: >> // If this record has variable length, reject it. >> if (TREE_CODE(TYPE_SIZE(type)) != INTEGER_CST) >> @@ -178,15 +174,13 @@ >> } >> } >> return FoundField ? isSingleElementStructOrArray(FoundField, >> - >> ignoreZeroLength, false, >> - false) >> + >> ignoreZeroLength, false) >> : 0; >> case ARRAY_TYPE: >> const ArrayType *Ty = dyn_cast(ConvertType(type)); >> if (!Ty || Ty->getNumElements() != 1) >> return 0; >> - return isSingleElementStructOrArray(TREE_TYPE(type), false, >> false, >> - false); >> + return isSingleElementStructOrArray(TREE_TYPE(type), false, >> false); >> } >> } >> >> @@ -283,8 +277,8 @@ >> // single element is a bitfield of a type bigger than the struct; >> the code >> // for field-by-field struct passing does not handle this one right. >> #ifndef LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS >> -#define LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS(X) \ >> - !isSingleElementStructOrArray(X, false, true, false) >> +#define LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS(X, Y) \ >> + !isSingleElementStructOrArray((X), false, true) >> #endif >> >> // LLVM_SHOULD_RETURN_SELT_STRUCT_AS_SCALAR - Return a TYPE tree if >> this single >> @@ -295,7 +289,7 @@ >> // by abusing the __aligned__ attribute.) >> #ifndef LLVM_SHOULD_RETURN_SELT_STRUCT_AS_SCALAR >> #define LLVM_SHOULD_RETURN_SELT_STRUCT_AS_SCALAR(X) \ >> - isSingleElementStructOrArray(X, false, false, false) >> + isSingleElementStructOrArray(X, false, false) >> #endif >> >> // LLVM_SHOULD_RETURN_VECTOR_AS_SCALAR - Return a TYPE tree if this >> vector type >> @@ -408,6 +402,7 @@ >> /// their fields. >> void HandleArgument(tree type, std::vector &ScalarElts, >> ParameterAttributes *Attributes = NULL) { >> + unsigned Size = 0; >> const Type *Ty = ConvertType(type); >> // Figure out if this field is zero bits wide, e.g. {} or [0 x >> int]. Do >> // not include variable sized fields here. >> @@ -418,7 +413,7 @@ >> ScalarElts.push_back(PtrTy); >> } else if (Ty->getTypeID()==Type::VectorTyID) { >> if (LLVM_SHOULD_PASS_VECTOR_IN_INTEGER_REGS(type)) { >> - PassInIntegerRegisters(type, Ty, ScalarElts); >> + PassInIntegerRegisters(type, Ty, ScalarElts, 0); >> } else { >> C.HandleScalarArgument(Ty, type); >> ScalarElts.push_back(Ty); >> @@ -444,8 +439,8 @@ >> *Attributes |= >> >> ParamAttr::constructAlignmentFromInt(LLVM_BYVAL_ALIGNMENT(type)); >> } >> - } else if (LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS(type)) { >> - PassInIntegerRegisters(type, Ty, ScalarElts); >> + } else if (LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS(type, >> &Size)) { >> + PassInIntegerRegisters(type, Ty, ScalarElts, Size); >> } else if (isZeroSizedStructOrUnion(type)) { >> // Zero sized struct or union, just drop it! >> ; >> @@ -526,10 +521,15 @@ >> >> /// PassInIntegerRegisters - Given an aggregate value that should >> be passed in >> /// integer registers, convert it to a structure containing ints >> and pass all >> - /// of the struct elements in. >> + /// of the struct elements in. If Size is set we pass only that >> many bytes. >> void PassInIntegerRegisters(tree type, const Type *Ty, >> - std::vector >> &ScalarElts) { >> - unsigned Size = TREE_INT_CST_LOW(TYPE_SIZE(type))/8; >> + std::vector &ScalarElts, >> + unsigned origSize) { >> + unsigned Size; >> + if (origSize) >> + Size = origSize; >> + else >> + Size = TREE_INT_CST_LOW(TYPE_SIZE(type))/8; >> >> // FIXME: We should preserve all aggregate value alignment >> information. >> // Work around to preserve some aggregate value alignment >> information: >> @@ -568,7 +568,7 @@ >> Elts.push_back(Type::Int8Ty); >> Size -= 1; >> } >> - assert(Size == 0 && "Didn't cover value?"); >> + assert((origSize || Size == 0) && "Didn't cover value?"); >> const StructType *STy = StructType::get(Elts, false); >> >> unsigned i = 0; >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From evan.cheng at apple.com Mon Jun 2 19:49:40 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 2 Jun 2008 17:49:40 -0700 Subject: [llvm-commits] [llvm-gcc-4.2] r51723 - in /llvm-gcc-4.2/trunk/gcc: config/i386/llvm-i386-target.h config/i386/llvm-i386.cpp config/rs6000/llvm-rs6000.cpp llvm-abi.h In-Reply-To: References: <200805300123.m4U1NDZl019942@zion.cs.uiuc.edu> <4B25ACA3-2667-47BE-8483-B937CEA1719F@apple.com> Message-ID: <8EAC15B2-AC97-489B-A223-B2BA78AE6AC9@apple.com> Thanks! Evan On Jun 2, 2008, at 5:40 PM, Dale Johannesen wrote: > I'll look. > > On Jun 2, 2008, at 5:35 PM, Evan Cheng wrote: > >> Hi Dale, >> >> Looks like this patch broke 447.dealII on x86-64. Try this: >> >> make ENABLE_OPTIMIZED=1 TEST=nightly TARGET_FLAGS="-m64 - >> DSPEC_CPU2000_LP64 -DSPEC_CPU_LP64" TARGET_LLCFLAGS="-relocation- >> model=pic -disable-fp-elim" EXTRA_LLI_OPTS="-relocation-model=pic - >> disable-fp-elim" clean Output/447.dealII.diff-llc >> >> Evan >> >> On May 29, 2008, at 6:23 PM, Dale Johannesen wrote: >> >>> Author: johannes >>> Date: Thu May 29 20:23:12 2008 >>> New Revision: 51723 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=51723&view=rev >>> Log: >>> X86-64 ABI fix. Revert isSingleElementStructOrArray >>> change in favor of a more general version which handles >>> the case where there's more than one element correctly. >>> Fixes gcc.dg/compat/struct-layout-1.exp/t003 >>> and many more. >>> >>> >>> Modified: >>> llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h >>> llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp >>> llvm-gcc-4.2/trunk/gcc/config/rs6000/llvm-rs6000.cpp >>> llvm-gcc-4.2/trunk/gcc/llvm-abi.h >>> >>> Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h >>> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h?rev=51723&r1=51722&r2=51723&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ==================================================================== >>> --- llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h (original) >>> +++ llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h Thu May >>> 29 20:23:12 2008 >>> @@ -95,17 +95,18 @@ >>> considered as if they were the type of the data field. */ >>> #ifndef LLVM_SHOULD_RETURN_SELT_STRUCT_AS_SCALAR >>> #define LLVM_SHOULD_RETURN_SELT_STRUCT_AS_SCALAR(X) \ >>> - isSingleElementStructOrArray(X, true, false, false) >>> + isSingleElementStructOrArray(X, true, false) >>> #endif >>> >>> +extern bool llvm_x86_should_pass_aggregate_in_integer_regs(tree, >>> unsigned*); >>> + >>> /* LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS - Return true if >>> this aggregate >>> value should be passed in integer registers. This differs from >>> the usual >>> - handling in that x86-64 passes single-int-element unions as >>> the type of the >>> - field. */ >>> -#define >>> LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS(X) \ >>> - >>> (TARGET_64BIT ? \ >>> - !isSingleElementStructOrArray((X), true, true, >>> true) : \ >>> - !isSingleElementStructOrArray((X), false, true, false)) >>> + handling in that x86-64 passes 128-bit structs and unions >>> which only >>> + contain data in the first 64 bits, as 64-bit objects. (These >>> can be >>> + created by abusing __attribute__((aligned)). */ >>> +#define LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS(X, >>> Y) \ >>> + llvm_x86_should_pass_aggregate_in_integer_regs((X), (Y)) >>> >>> extern bool llvm_x86_should_pass_vector_in_integer_regs(tree); >>> >>> >>> Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp >>> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp?rev=51723&r1=51722&r2=51723&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ==================================================================== >>> --- llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp (original) >>> +++ llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp Thu May 29 >>> 20:23:12 2008 >>> @@ -1288,4 +1288,38 @@ >>> return Loc; >>> } >>> >>> +/// llvm_x86_should_pass_aggregate_in_integer_regs - x86-32 is >>> same as the >>> +/// default. x86-64 detects the case where a type is 16 bytes >>> long but >>> +/// only 8 of them are passed, the rest being padding (*size is >>> set to 8 >>> +/// to identify this case). >>> +bool llvm_x86_should_pass_aggregate_in_integer_regs(tree type, >>> unsigned *size) >>> +{ >>> + *size = 0; >>> + if (TARGET_64BIT) { >>> + enum x86_64_reg_class Class[MAX_CLASSES]; >>> + enum machine_mode Mode = ix86_getNaturalModeForType(type); >>> + int NumClasses = ix86_ClassifyArgument(Mode, type, Class, 0); >>> + if (NumClasses == 1 && (Class[0] == X86_64_INTEGERSI_CLASS || >>> + Class[0] == X86_64_INTEGER_CLASS)) { >>> + /* 8 byte object, one int register */ >>> + return true; >>> + } >>> + if (NumClasses == 2 && (Class[0] == X86_64_INTEGERSI_CLASS || >>> + Class[0] == X86_64_INTEGER_CLASS)) { >>> + if (Class[1] == X86_64_INTEGERSI_CLASS || >>> + Class[1] == X86_64_INTEGER_CLASS) >>> + /* 16 byte object, 2 int registers */ >>> + return true; >>> + if (Class[1] == X86_64_NO_CLASS) { >>> + /* 16 byte object, only 1st register has information */ >>> + *size = 8; >>> + return true; >>> + } >>> + } >>> + return false; >>> + } >>> + else >>> + return !isSingleElementStructOrArray(type, false, true); >>> +} >>> + >>> /* LLVM LOCAL end (ENTIRE FILE!) */ >>> >>> Modified: llvm-gcc-4.2/trunk/gcc/config/rs6000/llvm-rs6000.cpp >>> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/rs6000/llvm-rs6000.cpp?rev=51723&r1=51722&r2=51723&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ==================================================================== >>> --- llvm-gcc-4.2/trunk/gcc/config/rs6000/llvm-rs6000.cpp (original) >>> +++ llvm-gcc-4.2/trunk/gcc/config/rs6000/llvm-rs6000.cpp Thu May >>> 29 20:23:12 2008 >>> @@ -404,7 +404,7 @@ >>> // some zero-length fields as well, must be passed as the field >>> type. >>> // Note this does not apply to long double. >>> // This is required for ABI correctness. >>> - tree tType = isSingleElementStructOrArray(TreeType, true, >>> false, false); >>> + tree tType = isSingleElementStructOrArray(TreeType, true, false); >>> if (tType && int_size_in_bytes(tType)==Bytes && TYPE_MODE(tType)! >>> =TFmode && >>> (TREE_CODE(tType)!=VECTOR_TYPE || Bytes==16)) >>> return false; >>> @@ -437,7 +437,7 @@ >>> // Other single-element structs may be passed this way as well, but >>> // only if the type size matches the element's type size (structs >>> that >>> // violate this can be created with __aligned__). >>> - tree tType = isSingleElementStructOrArray(TreeType, true, >>> false, false); >>> + tree tType = isSingleElementStructOrArray(TreeType, true, false); >>> if (tType && int_size_in_bytes(tType)==SrcSize && TYPE_MODE(tType)! >>> =TFmode && >>> (TREE_CODE(tType)!=VECTOR_TYPE || SrcSize==16)) { >>> Elts.push_back(ConvertType(tType)); >>> >>> Modified: llvm-gcc-4.2/trunk/gcc/llvm-abi.h >>> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-abi.h?rev=51723&r1=51722&r2=51723&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ==================================================================== >>> --- llvm-gcc-4.2/trunk/gcc/llvm-abi.h (original) >>> +++ llvm-gcc-4.2/trunk/gcc/llvm-abi.h Thu May 29 20:23:12 2008 >>> @@ -138,21 +138,17 @@ >>> /// rejectFatBitField, and the single element is a bitfield of a >>> type that's >>> /// bigger than the struct, return null anyway. >>> static tree isSingleElementStructOrArray(tree type, bool >>> ignoreZeroLength, >>> - bool rejectFatBitfield, >>> - bool acceptUnions) { >>> + bool rejectFatBitfield) { >>> // Scalars are good. >>> if (!isAggregateTreeType(type)) return type; >>> >>> tree FoundField = 0; >>> switch (TREE_CODE(type)) { >>> case QUAL_UNION_TYPE: >>> + case UNION_TYPE: // Single element unions don't count. >>> case COMPLEX_TYPE: // Complex values are like 2-element records. >>> default: >>> return 0; >>> - case UNION_TYPE: // Single element unions don't count. >>> - if (!acceptUnions) >>> - return 0; >>> - // fall through >>> case RECORD_TYPE: >>> // If this record has variable length, reject it. >>> if (TREE_CODE(TYPE_SIZE(type)) != INTEGER_CST) >>> @@ -178,15 +174,13 @@ >>> } >>> } >>> return FoundField ? isSingleElementStructOrArray(FoundField, >>> - >>> ignoreZeroLength, false, >>> - false) >>> + >>> ignoreZeroLength, false) >>> : 0; >>> case ARRAY_TYPE: >>> const ArrayType *Ty = dyn_cast(ConvertType(type)); >>> if (!Ty || Ty->getNumElements() != 1) >>> return 0; >>> - return isSingleElementStructOrArray(TREE_TYPE(type), false, >>> false, >>> - false); >>> + return isSingleElementStructOrArray(TREE_TYPE(type), false, >>> false); >>> } >>> } >>> >>> @@ -283,8 +277,8 @@ >>> // single element is a bitfield of a type bigger than the struct; >>> the code >>> // for field-by-field struct passing does not handle this one right. >>> #ifndef LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS >>> -#define LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS(X) \ >>> - !isSingleElementStructOrArray(X, false, true, false) >>> +#define LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS(X, Y) \ >>> + !isSingleElementStructOrArray((X), false, true) >>> #endif >>> >>> // LLVM_SHOULD_RETURN_SELT_STRUCT_AS_SCALAR - Return a TYPE tree >>> if this single >>> @@ -295,7 +289,7 @@ >>> // by abusing the __aligned__ attribute.) >>> #ifndef LLVM_SHOULD_RETURN_SELT_STRUCT_AS_SCALAR >>> #define LLVM_SHOULD_RETURN_SELT_STRUCT_AS_SCALAR(X) \ >>> - isSingleElementStructOrArray(X, false, false, false) >>> + isSingleElementStructOrArray(X, false, false) >>> #endif >>> >>> // LLVM_SHOULD_RETURN_VECTOR_AS_SCALAR - Return a TYPE tree if >>> this vector type >>> @@ -408,6 +402,7 @@ >>> /// their fields. >>> void HandleArgument(tree type, std::vector &ScalarElts, >>> ParameterAttributes *Attributes = NULL) { >>> + unsigned Size = 0; >>> const Type *Ty = ConvertType(type); >>> // Figure out if this field is zero bits wide, e.g. {} or [0 x >>> int]. Do >>> // not include variable sized fields here. >>> @@ -418,7 +413,7 @@ >>> ScalarElts.push_back(PtrTy); >>> } else if (Ty->getTypeID()==Type::VectorTyID) { >>> if (LLVM_SHOULD_PASS_VECTOR_IN_INTEGER_REGS(type)) { >>> - PassInIntegerRegisters(type, Ty, ScalarElts); >>> + PassInIntegerRegisters(type, Ty, ScalarElts, 0); >>> } else { >>> C.HandleScalarArgument(Ty, type); >>> ScalarElts.push_back(Ty); >>> @@ -444,8 +439,8 @@ >>> *Attributes |= >>> >>> ParamAttr::constructAlignmentFromInt(LLVM_BYVAL_ALIGNMENT(type)); >>> } >>> - } else if (LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS(type)) { >>> - PassInIntegerRegisters(type, Ty, ScalarElts); >>> + } else if (LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS(type, >>> &Size)) { >>> + PassInIntegerRegisters(type, Ty, ScalarElts, Size); >>> } else if (isZeroSizedStructOrUnion(type)) { >>> // Zero sized struct or union, just drop it! >>> ; >>> @@ -526,10 +521,15 @@ >>> >>> /// PassInIntegerRegisters - Given an aggregate value that should >>> be passed in >>> /// integer registers, convert it to a structure containing ints >>> and pass all >>> - /// of the struct elements in. >>> + /// of the struct elements in. If Size is set we pass only >>> that many bytes. >>> void PassInIntegerRegisters(tree type, const Type *Ty, >>> - std::vector >>> &ScalarElts) { >>> - unsigned Size = TREE_INT_CST_LOW(TYPE_SIZE(type))/8; >>> + std::vector &ScalarElts, >>> + unsigned origSize) { >>> + unsigned Size; >>> + if (origSize) >>> + Size = origSize; >>> + else >>> + Size = TREE_INT_CST_LOW(TYPE_SIZE(type))/8; >>> >>> // FIXME: We should preserve all aggregate value alignment >>> information. >>> // Work around to preserve some aggregate value alignment >>> information: >>> @@ -568,7 +568,7 @@ >>> Elts.push_back(Type::Int8Ty); >>> Size -= 1; >>> } >>> - assert(Size == 0 && "Didn't cover value?"); >>> + assert((origSize || Size == 0) && "Didn't cover value?"); >>> const StructType *STy = StructType::get(Elts, false); >>> >>> unsigned i = 0; >>> >>> >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> > From gohman at apple.com Mon Jun 2 19:57:23 2008 From: gohman at apple.com (Dan Gohman) Date: Tue, 03 Jun 2008 00:57:23 -0000 Subject: [llvm-commits] [llvm] r51890 - /llvm/trunk/lib/Transforms/Utils/LCSSA.cpp Message-ID: <200806030057.m530vN9j012718@zion.cs.uiuc.edu> Author: djg Date: Mon Jun 2 19:57:21 2008 New Revision: 51890 URL: http://llvm.org/viewvc/llvm-project?rev=51890&view=rev Log: Fix whitespace in whitespace-significant pseudocode in a comment. Modified: llvm/trunk/lib/Transforms/Utils/LCSSA.cpp Modified: llvm/trunk/lib/Transforms/Utils/LCSSA.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/LCSSA.cpp?rev=51890&r1=51889&r2=51890&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/LCSSA.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/LCSSA.cpp Mon Jun 2 19:57:21 2008 @@ -17,8 +17,8 @@ // else else // X2 = ... X2 = ... // X3 = phi(X1, X2) X3 = phi(X1, X2) -// ... = X3 + 4 X4 = phi(X3) -// ... = X4 + 4 +// ... = X3 + 4 X4 = phi(X3) +// ... = X4 + 4 // // This is still valid LLVM; the extra phi nodes are purely redundant, and will // be trivially eliminated by InstCombine. The major benefit of this From dpatel at apple.com Mon Jun 2 20:02:16 2008 From: dpatel at apple.com (Devang Patel) Date: Tue, 03 Jun 2008 01:02:16 -0000 Subject: [llvm-commits] [llvm] r51891 - /llvm/trunk/lib/VMCore/PassManager.cpp Message-ID: <200806030102.m5312GuL013087@zion.cs.uiuc.edu> Author: dpatel Date: Mon Jun 2 20:02:16 2008 New Revision: 51891 URL: http://llvm.org/viewvc/llvm-project?rev=51891&view=rev Log: Add debugging aid. Modified: llvm/trunk/lib/VMCore/PassManager.cpp Modified: llvm/trunk/lib/VMCore/PassManager.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/PassManager.cpp?rev=51891&r1=51890&r2=51891&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/PassManager.cpp (original) +++ llvm/trunk/lib/VMCore/PassManager.cpp Mon Jun 2 20:02:16 2008 @@ -621,9 +621,15 @@ std::map::iterator Info = I++; if (!dynamic_cast(Info->second) && std::find(PreservedSet.begin(), PreservedSet.end(), Info->first) == - PreservedSet.end()) + PreservedSet.end()) { // Remove this analysis AvailableAnalysis.erase(Info); + if (PassDebugging >= Details) { + Pass *S = Info->second; + cerr << " -- " << P->getPassName() << " is not preserving "; + cerr << S->getPassName() << "\n"; + } + } } // Check inherited analysis also. If P is not preserving analysis From isanbard at gmail.com Mon Jun 2 20:13:02 2008 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 2 Jun 2008 18:13:02 -0700 Subject: [llvm-commits] [llvm] r51891 - /llvm/trunk/lib/VMCore/PassManager.cpp In-Reply-To: <200806030102.m5312GuL013087@zion.cs.uiuc.edu> References: <200806030102.m5312GuL013087@zion.cs.uiuc.edu> Message-ID: <16e5fdf90806021813l6fc839ecj34fb4c881d231738@mail.gmail.com> If you use "DOUT" instead of "cerr", then this checking part will be removed for a release build. -bw On Mon, Jun 2, 2008 at 6:02 PM, Devang Patel wrote: > Author: dpatel > Date: Mon Jun 2 20:02:16 2008 > New Revision: 51891 > > URL: http://llvm.org/viewvc/llvm-project?rev=51891&view=rev > Log: > Add debugging aid. > > Modified: > llvm/trunk/lib/VMCore/PassManager.cpp > > Modified: llvm/trunk/lib/VMCore/PassManager.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/PassManager.cpp?rev=51891&r1=51890&r2=51891&view=diff > > ============================================================================== > --- llvm/trunk/lib/VMCore/PassManager.cpp (original) > +++ llvm/trunk/lib/VMCore/PassManager.cpp Mon Jun 2 20:02:16 2008 > @@ -621,9 +621,15 @@ > std::map::iterator Info = I++; > if (!dynamic_cast(Info->second) > && std::find(PreservedSet.begin(), PreservedSet.end(), Info->first) == > - PreservedSet.end()) > + PreservedSet.end()) { > // Remove this analysis > AvailableAnalysis.erase(Info); > + if (PassDebugging >= Details) { > + Pass *S = Info->second; > + cerr << " -- " << P->getPassName() << " is not preserving "; > + cerr << S->getPassName() << "\n"; > + } > + } > } > > // Check inherited analysis also. If P is not preserving analysis > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From bruno.cardoso at gmail.com Mon Jun 2 20:19:39 2008 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Mon, 2 Jun 2008 22:19:39 -0300 Subject: [llvm-commits] [PATCH] mips and mipsel support in llvm-gcc 4.2 Message-ID: <275e64e40806021819ie62f9c5jdab6348c885eab7b@mail.gmail.com> Is it ok to commit this? -- Bruno Cardoso Lopes ( now @ Cocos Island ) http://www.brunocardoso.cc ++ The saddest aspect of life right now is that science gathers knowledge faster than society gathers wisdom + Isaac Asimov -------------- next part -------------- A non-text attachment was scrubbed... Name: mips.patch Type: application/octet-stream Size: 439 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20080602/283caeb1/attachment.obj From dpatel at apple.com Mon Jun 2 20:20:02 2008 From: dpatel at apple.com (Devang Patel) Date: Tue, 03 Jun 2008 01:20:02 -0000 Subject: [llvm-commits] [llvm] r51892 - /llvm/trunk/lib/VMCore/PassManager.cpp Message-ID: <200806030120.m531K2JU013559@zion.cs.uiuc.edu> Author: dpatel Date: Mon Jun 2 20:20:02 2008 New Revision: 51892 URL: http://llvm.org/viewvc/llvm-project?rev=51892&view=rev Log: "Unable to schedule required by " is more helpful then "Unable to handle Pass that requires lower level Analysis pass" Modified: llvm/trunk/lib/VMCore/PassManager.cpp Modified: llvm/trunk/lib/VMCore/PassManager.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/PassManager.cpp?rev=51892&r1=51891&r2=51892&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/PassManager.cpp (original) +++ llvm/trunk/lib/VMCore/PassManager.cpp Mon Jun 2 20:20:02 2008 @@ -930,7 +930,11 @@ // When Pass manager is not able to order required analysis info, Pass manager // checks whether any lower level manager will be able to provide this // analysis info on demand or not. - assert (0 && "Unable to handle Pass that requires lower level Analysis pass"); +#ifndef NDEBUG + cerr << "Unable to schedule " << RequiredPass->getPassName(); + cerr << " required by " << P->getPassName() << "\n"; +#endif + assert (0 && "Unable to schedule pass"); } // Destructor From gohman at apple.com Mon Jun 2 20:21:11 2008 From: gohman at apple.com (Dan Gohman) Date: Tue, 03 Jun 2008 01:21:11 -0000 Subject: [llvm-commits] [llvm] r51893 - /llvm/trunk/test/Assembler/insertextractvalue.ll Message-ID: <200806030121.m531LBQW013605@zion.cs.uiuc.edu> Author: djg Date: Mon Jun 2 20:21:11 2008 New Revision: 51893 URL: http://llvm.org/viewvc/llvm-project?rev=51893&view=rev Log: nounwindify. Modified: llvm/trunk/test/Assembler/insertextractvalue.ll Modified: llvm/trunk/test/Assembler/insertextractvalue.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Assembler/insertextractvalue.ll?rev=51893&r1=51892&r2=51893&view=diff ============================================================================== --- llvm/trunk/test/Assembler/insertextractvalue.ll (original) +++ llvm/trunk/test/Assembler/insertextractvalue.ll Mon Jun 2 20:21:11 2008 @@ -2,22 +2,22 @@ ; RUN: grep insertvalue %t | count 1 ; RUN: grep extractvalue %t | count 1 -define float @foo({{i32},{float, double}}* %p) { +define float @foo({{i32},{float, double}}* %p) nounwind { %t = load {{i32},{float, double}}* %p %s = extractvalue {{i32},{float, double}} %t, 1, 0 %r = insertvalue {{i32},{float, double}} %t, double 2.0, 1, 1 store {{i32},{float, double}} %r, {{i32},{float, double}}* %p ret float %s } -define float @bar({{i32},{float, double}}* %p) { +define float @bar({{i32},{float, double}}* %p) nounwind { store {{i32},{float, double}} insertvalue ({{i32},{float, double}}{{i32}{i32 4},{float, double}{float 4.0, double 5.0}}, double 20.0, 1, 1), {{i32},{float, double}}* %p ret float extractvalue ({{i32},{float, double}}{{i32}{i32 3},{float, double}{float 7.0, double 9.0}}, 1, 0) } -define float @car({{i32},{float, double}}* %p) { +define float @car({{i32},{float, double}}* %p) nounwind { store {{i32},{float, double}} insertvalue ({{i32},{float, double}} undef, double 20.0, 1, 1), {{i32},{float, double}}* %p ret float extractvalue ({{i32},{float, double}} undef, 1, 0) } -define float @dar({{i32},{float, double}}* %p) { +define float @dar({{i32},{float, double}}* %p) nounwind { store {{i32},{float, double}} insertvalue ({{i32},{float, double}} zeroinitializer, double 20.0, 1, 1), {{i32},{float, double}}* %p ret float extractvalue ({{i32},{float, double}} zeroinitializer, 1, 0) } From echristo at apple.com Mon Jun 2 20:21:16 2008 From: echristo at apple.com (Eric Christopher) Date: Mon, 2 Jun 2008 18:21:16 -0700 Subject: [llvm-commits] [PATCH] mips and mipsel support in llvm-gcc 4.2 In-Reply-To: <275e64e40806021819ie62f9c5jdab6348c885eab7b@mail.gmail.com> References: <275e64e40806021819ie62f9c5jdab6348c885eab7b@mail.gmail.com> Message-ID: <3F45BAD1-A42D-4156-83CB-93D6AD5C6FB2@apple.com> On Jun 2, 2008, at 6:19 PM, Bruno Cardoso Lopes wrote: > Is it ok to commit this? Should be just fine. -eric From dalej at apple.com Mon Jun 2 20:21:17 2008 From: dalej at apple.com (Dale Johannesen) Date: Mon, 2 Jun 2008 18:21:17 -0700 Subject: [llvm-commits] [llvm] r51885 - /llvm/trunk/lib/CodeGen/AsmPrinter.cpp In-Reply-To: <200806022219.m52MJCeZ024222@zion.cs.uiuc.edu> References: <200806022219.m52MJCeZ024222@zion.cs.uiuc.edu> Message-ID: <13962B00-98F4-4D0C-9CC8-93330280ABD6@apple.com> This makes the assembly produced for address+constant look like .long (symbol) + (constant #comment) Darwin's as actually accepts this, although it whines, but this isn't right. On Jun 2, 2008, at 3:19 PM, Scott Michel wrote: > Author: pingbak > Date: Mon Jun 2 17:19:12 2008 > New Revision: 51885 > > URL: http://llvm.org/viewvc/llvm-project?rev=51885&view=rev > Log: > Minor cosmetic patch so that the hex equivalent of a decimal > constant shows up in the assembly language output. Helps with > debugging without a HP calculator having to be handy. > > Modified: > llvm/trunk/lib/CodeGen/AsmPrinter.cpp > > Modified: llvm/trunk/lib/CodeGen/AsmPrinter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter.cpp?rev=51885&r1=51884&r2=51885&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/CodeGen/AsmPrinter.cpp (original) > +++ llvm/trunk/lib/CodeGen/AsmPrinter.cpp Mon Jun 2 17:19:12 2008 > @@ -742,7 +742,9 @@ > if (CV->isNullValue() || isa(CV)) > O << "0"; > else if (const ConstantInt *CI = dyn_cast(CV)) { > - O << CI->getZExtValue(); > + O << CI->getZExtValue() << "\t\t\t" > + << TAI->getCommentString() << " 0x" > + << CI->getValue().toStringUnsigned(16); > } else if (const GlobalValue *GV = dyn_cast(CV)) { > // This is a constant address for a global variable or function. > Use the > // name of the variable or function as the address value, possibly > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From bruno.cardoso at gmail.com Mon Jun 2 20:25:30 2008 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Mon, 2 Jun 2008 22:25:30 -0300 Subject: [llvm-commits] [PATCH] llvm-gcc 4.2 mips cross-compiler! Message-ID: <275e64e40806021825o643f300foe43b2d0629454658@mail.gmail.com> When cross-compiling for Mips some ifndef are needed to solve some undefined references into mips.c Is it ok to commit this too? -- Bruno Cardoso Lopes ( now @ Cocos Island ) http://www.brunocardoso.cc ++ The saddest aspect of life right now is that science gathers knowledge faster than society gathers wisdom + Isaac Asimov -------------- next part -------------- A non-text attachment was scrubbed... Name: mips.c.patch Type: application/octet-stream Size: 2046 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20080602/c881d609/attachment.obj From echristo at apple.com Mon Jun 2 20:29:30 2008 From: echristo at apple.com (Eric Christopher) Date: Mon, 2 Jun 2008 18:29:30 -0700 Subject: [llvm-commits] [PATCH] llvm-gcc 4.2 mips cross-compiler! In-Reply-To: <275e64e40806021825o643f300foe43b2d0629454658@mail.gmail.com> References: <275e64e40806021825o643f300foe43b2d0629454658@mail.gmail.com> Message-ID: On Jun 2, 2008, at 6:25 PM, Bruno Cardoso Lopes wrote: > This should work just fine, but you can also likely comment out the containing functions. For now, don't worry about it :) -eric From bruno.cardoso at gmail.com Mon Jun 2 20:33:26 2008 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 03 Jun 2008 01:33:26 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r51894 - in /llvm-gcc-4.2/trunk/gcc: Makefile.in config/mips/mips.c Message-ID: <200806030133.m531XR5Y013940@zion.cs.uiuc.edu> Author: bruno Date: Mon Jun 2 20:33:26 2008 New Revision: 51894 URL: http://llvm.org/viewvc/llvm-project?rev=51894&view=rev Log: Added mips and mipsel support and fixed undefined references in mips.c Modified: llvm-gcc-4.2/trunk/gcc/Makefile.in llvm-gcc-4.2/trunk/gcc/config/mips/mips.c Modified: llvm-gcc-4.2/trunk/gcc/Makefile.in URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/Makefile.in?rev=51894&r1=51893&r2=51894&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/Makefile.in (original) +++ llvm-gcc-4.2/trunk/gcc/Makefile.in Mon Jun 2 20:33:26 2008 @@ -1140,6 +1140,8 @@ ia64-*-*) echo ia64;; \ i[34567]86-*-*) echo x86;; \ x86_64-*-*) echo x86;; \ + mips-*-*) echo mips;; \ + mipsel-*-*) echo mipsel;; \ powerpc*-*-*) echo powerpc;; \ sparc-*-*) echo sparc;; \ sparcv9-*-*) echo sparc;; \ Modified: llvm-gcc-4.2/trunk/gcc/config/mips/mips.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/mips/mips.c?rev=51894&r1=51893&r2=51894&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/mips/mips.c (original) +++ llvm-gcc-4.2/trunk/gcc/config/mips/mips.c Mon Jun 2 20:33:26 2008 @@ -7219,7 +7219,9 @@ split_all_insns_noflow (); if (TARGET_MIPS16) mips16_lay_out_constants (); +#ifndef ENABLE_LLVM shorten_branches (insn); +#endif final_start_function (insn, file, 1); final (insn, file, 1); final_end_function (); @@ -9022,7 +9024,9 @@ /* Recalculate instruction lengths without taking nops into account. */ cfun->machine->ignore_hazard_length_p = true; +#ifndef ENABLE_LLVM shorten_branches (get_insns ()); +#endif cfun->machine->all_noreorder_p = true; @@ -9344,15 +9348,16 @@ delay slot if is not annulled. */ if (!INSN_ANNULLED_BRANCH_P (insn)) { +#ifndef ENABLE_LLVM final_scan_insn (XVECEXP (final_sequence, 0, 1), asm_out_file, optimize, 1, NULL); +#endif INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1; } else output_asm_insn ("nop", 0); fprintf (asm_out_file, "\n"); } - /* Output the unconditional branch to TAKEN. */ if (length <= 16) output_asm_insn ("j\t%0%/", &taken); @@ -9369,8 +9374,10 @@ Use INSN's delay slot if is annulled. */ if (INSN_ANNULLED_BRANCH_P (insn)) { +#ifndef ENABLE_LLVM final_scan_insn (XVECEXP (final_sequence, 0, 1), asm_out_file, optimize, 1, NULL); +#endif INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1; } else @@ -9808,12 +9815,14 @@ If INSN1 is the last instruction blocking X, it would better to choose (INSN1, X) over (INSN2, INSN1). */ +#ifndef ENABLE_LLVM for (dep = INSN_DEPEND (insn1); dep != 0; dep = XEXP (dep, 1)) if (REG_NOTE_KIND (dep) == REG_DEP_ANTI && INSN_PRIORITY (XEXP (dep, 0)) > INSN_PRIORITY (insn2) && recog_memoized (XEXP (dep, 0)) >= 0 && get_attr_vr4130_class (XEXP (dep, 0)) == VR4130_CLASS_ALU) return false; +#endif if (vr4130_last_insn != 0 && recog_memoized (insn1) >= 0 From dalej at apple.com Mon Jun 2 21:35:29 2008 From: dalej at apple.com (Dale Johannesen) Date: Mon, 2 Jun 2008 19:35:29 -0700 Subject: [llvm-commits] [llvm-gcc-4.2] r51723 - in /llvm-gcc-4.2/trunk/gcc: config/i386/llvm-i386-target.h config/i386/llvm-i386.cpp config/rs6000/llvm-rs6000.cpp llvm-abi.h In-Reply-To: <4B25ACA3-2667-47BE-8483-B937CEA1719F@apple.com> References: <200805300123.m4U1NDZl019942@zion.cs.uiuc.edu> <4B25ACA3-2667-47BE-8483-B937CEA1719F@apple.com> Message-ID: <983E84B7-0FC5-416B-A174-E1D5C0A50E87@apple.com> Not saying you're wrong, but why do you think it's this patch? On Jun 2, 2008, at 5:35 PM, Evan Cheng wrote: > Hi Dale, > > Looks like this patch broke 447.dealII on x86-64. Try this: > > make ENABLE_OPTIMIZED=1 TEST=nightly TARGET_FLAGS="-m64 - > DSPEC_CPU2000_LP64 -DSPEC_CPU_LP64" TARGET_LLCFLAGS="-relocation- > model=pic -disable-fp-elim" EXTRA_LLI_OPTS="-relocation-model=pic - > disable-fp-elim" clean Output/447.dealII.diff-llc > > Evan > > On May 29, 2008, at 6:23 PM, Dale Johannesen wrote: > >> Author: johannes >> Date: Thu May 29 20:23:12 2008 >> New Revision: 51723 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=51723&view=rev >> Log: >> X86-64 ABI fix. Revert isSingleElementStructOrArray >> change in favor of a more general version which handles >> the case where there's more than one element correctly. >> Fixes gcc.dg/compat/struct-layout-1.exp/t003 >> and many more. >> >> >> Modified: >> llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h >> llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp >> llvm-gcc-4.2/trunk/gcc/config/rs6000/llvm-rs6000.cpp >> llvm-gcc-4.2/trunk/gcc/llvm-abi.h >> >> Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h >> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h?rev=51723&r1=51722&r2=51723&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h (original) >> +++ llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h Thu May >> 29 20:23:12 2008 >> @@ -95,17 +95,18 @@ >> considered as if they were the type of the data field. */ >> #ifndef LLVM_SHOULD_RETURN_SELT_STRUCT_AS_SCALAR >> #define LLVM_SHOULD_RETURN_SELT_STRUCT_AS_SCALAR(X) \ >> - isSingleElementStructOrArray(X, true, false, false) >> + isSingleElementStructOrArray(X, true, false) >> #endif >> >> +extern bool llvm_x86_should_pass_aggregate_in_integer_regs(tree, >> unsigned*); >> + >> /* LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS - Return true if this >> aggregate >> value should be passed in integer registers. This differs from >> the usual >> - handling in that x86-64 passes single-int-element unions as the >> type of the >> - field. */ >> -#define >> LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS(X) \ >> - >> (TARGET_64BIT ? \ >> - !isSingleElementStructOrArray((X), true, true, >> true) : \ >> - !isSingleElementStructOrArray((X), false, true, false)) >> + handling in that x86-64 passes 128-bit structs and unions which >> only >> + contain data in the first 64 bits, as 64-bit objects. (These >> can be >> + created by abusing __attribute__((aligned)). */ >> +#define LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS(X, >> Y) \ >> + llvm_x86_should_pass_aggregate_in_integer_regs((X), (Y)) >> >> extern bool llvm_x86_should_pass_vector_in_integer_regs(tree); >> >> >> Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp?rev=51723&r1=51722&r2=51723&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp (original) >> +++ llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp Thu May 29 >> 20:23:12 2008 >> @@ -1288,4 +1288,38 @@ >> return Loc; >> } >> >> +/// llvm_x86_should_pass_aggregate_in_integer_regs - x86-32 is >> same as the >> +/// default. x86-64 detects the case where a type is 16 bytes >> long but >> +/// only 8 of them are passed, the rest being padding (*size is >> set to 8 >> +/// to identify this case). >> +bool llvm_x86_should_pass_aggregate_in_integer_regs(tree type, >> unsigned *size) >> +{ >> + *size = 0; >> + if (TARGET_64BIT) { >> + enum x86_64_reg_class Class[MAX_CLASSES]; >> + enum machine_mode Mode = ix86_getNaturalModeForType(type); >> + int NumClasses = ix86_ClassifyArgument(Mode, type, Class, 0); >> + if (NumClasses == 1 && (Class[0] == X86_64_INTEGERSI_CLASS || >> + Class[0] == X86_64_INTEGER_CLASS)) { >> + /* 8 byte object, one int register */ >> + return true; >> + } >> + if (NumClasses == 2 && (Class[0] == X86_64_INTEGERSI_CLASS || >> + Class[0] == X86_64_INTEGER_CLASS)) { >> + if (Class[1] == X86_64_INTEGERSI_CLASS || >> + Class[1] == X86_64_INTEGER_CLASS) >> + /* 16 byte object, 2 int registers */ >> + return true; >> + if (Class[1] == X86_64_NO_CLASS) { >> + /* 16 byte object, only 1st register has information */ >> + *size = 8; >> + return true; >> + } >> + } >> + return false; >> + } >> + else >> + return !isSingleElementStructOrArray(type, false, true); >> +} >> + >> /* LLVM LOCAL end (ENTIRE FILE!) */ >> >> Modified: llvm-gcc-4.2/trunk/gcc/config/rs6000/llvm-rs6000.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/rs6000/llvm-rs6000.cpp?rev=51723&r1=51722&r2=51723&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm-gcc-4.2/trunk/gcc/config/rs6000/llvm-rs6000.cpp (original) >> +++ llvm-gcc-4.2/trunk/gcc/config/rs6000/llvm-rs6000.cpp Thu May 29 >> 20:23:12 2008 >> @@ -404,7 +404,7 @@ >> // some zero-length fields as well, must be passed as the field >> type. >> // Note this does not apply to long double. >> // This is required for ABI correctness. >> - tree tType = isSingleElementStructOrArray(TreeType, true, false, >> false); >> + tree tType = isSingleElementStructOrArray(TreeType, true, false); >> if (tType && int_size_in_bytes(tType)==Bytes && TYPE_MODE(tType)! >> =TFmode && >> (TREE_CODE(tType)!=VECTOR_TYPE || Bytes==16)) >> return false; >> @@ -437,7 +437,7 @@ >> // Other single-element structs may be passed this way as well, but >> // only if the type size matches the element's type size (structs >> that >> // violate this can be created with __aligned__). >> - tree tType = isSingleElementStructOrArray(TreeType, true, false, >> false); >> + tree tType = isSingleElementStructOrArray(TreeType, true, false); >> if (tType && int_size_in_bytes(tType)==SrcSize && TYPE_MODE(tType)! >> =TFmode && >> (TREE_CODE(tType)!=VECTOR_TYPE || SrcSize==16)) { >> Elts.push_back(ConvertType(tType)); >> >> Modified: llvm-gcc-4.2/trunk/gcc/llvm-abi.h >> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-abi.h?rev=51723&r1=51722&r2=51723&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm-gcc-4.2/trunk/gcc/llvm-abi.h (original) >> +++ llvm-gcc-4.2/trunk/gcc/llvm-abi.h Thu May 29 20:23:12 2008 >> @@ -138,21 +138,17 @@ >> /// rejectFatBitField, and the single element is a bitfield of a >> type that's >> /// bigger than the struct, return null anyway. >> static tree isSingleElementStructOrArray(tree type, bool >> ignoreZeroLength, >> - bool rejectFatBitfield, >> - bool acceptUnions) { >> + bool rejectFatBitfield) { >> // Scalars are good. >> if (!isAggregateTreeType(type)) return type; >> >> tree FoundField = 0; >> switch (TREE_CODE(type)) { >> case QUAL_UNION_TYPE: >> + case UNION_TYPE: // Single element unions don't count. >> case COMPLEX_TYPE: // Complex values are like 2-element records. >> default: >> return 0; >> - case UNION_TYPE: // Single element unions don't count. >> - if (!acceptUnions) >> - return 0; >> - // fall through >> case RECORD_TYPE: >> // If this record has variable length, reject it. >> if (TREE_CODE(TYPE_SIZE(type)) != INTEGER_CST) >> @@ -178,15 +174,13 @@ >> } >> } >> return FoundField ? isSingleElementStructOrArray(FoundField, >> - >> ignoreZeroLength, false, >> - false) >> + >> ignoreZeroLength, false) >> : 0; >> case ARRAY_TYPE: >> const ArrayType *Ty = dyn_cast(ConvertType(type)); >> if (!Ty || Ty->getNumElements() != 1) >> return 0; >> - return isSingleElementStructOrArray(TREE_TYPE(type), false, >> false, >> - false); >> + return isSingleElementStructOrArray(TREE_TYPE(type), false, >> false); >> } >> } >> >> @@ -283,8 +277,8 @@ >> // single element is a bitfield of a type bigger than the struct; >> the code >> // for field-by-field struct passing does not handle this one right. >> #ifndef LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS >> -#define LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS(X) \ >> - !isSingleElementStructOrArray(X, false, true, false) >> +#define LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS(X, Y) \ >> + !isSingleElementStructOrArray((X), false, true) >> #endif >> >> // LLVM_SHOULD_RETURN_SELT_STRUCT_AS_SCALAR - Return a TYPE tree if >> this single >> @@ -295,7 +289,7 @@ >> // by abusing the __aligned__ attribute.) >> #ifndef LLVM_SHOULD_RETURN_SELT_STRUCT_AS_SCALAR >> #define LLVM_SHOULD_RETURN_SELT_STRUCT_AS_SCALAR(X) \ >> - isSingleElementStructOrArray(X, false, false, false) >> + isSingleElementStructOrArray(X, false, false) >> #endif >> >> // LLVM_SHOULD_RETURN_VECTOR_AS_SCALAR - Return a TYPE tree if this >> vector type >> @@ -408,6 +402,7 @@ >> /// their fields. >> void HandleArgument(tree type, std::vector &ScalarElts, >> ParameterAttributes *Attributes = NULL) { >> + unsigned Size = 0; >> const Type *Ty = ConvertType(type); >> // Figure out if this field is zero bits wide, e.g. {} or [0 x >> int]. Do >> // not include variable sized fields here. >> @@ -418,7 +413,7 @@ >> ScalarElts.push_back(PtrTy); >> } else if (Ty->getTypeID()==Type::VectorTyID) { >> if (LLVM_SHOULD_PASS_VECTOR_IN_INTEGER_REGS(type)) { >> - PassInIntegerRegisters(type, Ty, ScalarElts); >> + PassInIntegerRegisters(type, Ty, ScalarElts, 0); >> } else { >> C.HandleScalarArgument(Ty, type); >> ScalarElts.push_back(Ty); >> @@ -444,8 +439,8 @@ >> *Attributes |= >> >> ParamAttr::constructAlignmentFromInt(LLVM_BYVAL_ALIGNMENT(type)); >> } >> - } else if (LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS(type)) { >> - PassInIntegerRegisters(type, Ty, ScalarElts); >> + } else if (LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS(type, >> &Size)) { >> + PassInIntegerRegisters(type, Ty, ScalarElts, Size); >> } else if (isZeroSizedStructOrUnion(type)) { >> // Zero sized struct or union, just drop it! >> ; >> @@ -526,10 +521,15 @@ >> >> /// PassInIntegerRegisters - Given an aggregate value that should >> be passed in >> /// integer registers, convert it to a structure containing ints >> and pass all >> - /// of the struct elements in. >> + /// of the struct elements in. If Size is set we pass only that >> many bytes. >> void PassInIntegerRegisters(tree type, const Type *Ty, >> - std::vector >> &ScalarElts) { >> - unsigned Size = TREE_INT_CST_LOW(TYPE_SIZE(type))/8; >> + std::vector &ScalarElts, >> + unsigned origSize) { >> + unsigned Size; >> + if (origSize) >> + Size = origSize; >> + else >> + Size = TREE_INT_CST_LOW(TYPE_SIZE(type))/8; >> >> // FIXME: We should preserve all aggregate value alignment >> information. >> // Work around to preserve some aggregate value alignment >> information: >> @@ -568,7 +568,7 @@ >> Elts.push_back(Type::Int8Ty); >> Size -= 1; >> } >> - assert(Size == 0 && "Didn't cover value?"); >> + assert((origSize || Size == 0) && "Didn't cover value?"); >> const StructType *STy = StructType::get(Elts, false); >> >> unsigned i = 0; >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From nicholas at mxc.ca Mon Jun 2 21:58:19 2008 From: nicholas at mxc.ca (Nick Lewycky) Date: Mon, 02 Jun 2008 19:58:19 -0700 Subject: [llvm-commits] value range analysis based on scalar-evolutions In-Reply-To: <48439FFE.9040804@gmail.com> References: <48436EF1.8020203@mxc.ca> <48439FFE.9040804@gmail.com> Message-ID: <4844B34B.9010307@mxc.ca> T?r?k Edwin wrote: > Nick Lewycky wrote: >> I've implemented an analysis pass that uses SCEV to determine value >> ranges of integer-typed registers. >> >> Currently it maintains a map of Value* to ConstantRange*, which is >> rather inelegant. > > There is a SCEVHandle->getValueRange(), perhaps you could move the > implementation there and then you wouldn't need the map? I was planning to delete that. It's unfinished and unused. Alternately, I could move the LoopVR implementation stuff over there, and leave just a map as an analysis to be updated. (But who would fill that map? We don't want scalar-evolutions to waste its time when nobody's requested that data.) >> I was thinking we could have one analysis which would do that and >> others that would update the central analysis. > > There is also Transforms/Scalar/PredicateSimplifier that tracks value > ranges. > It would be nice to have all that value range info available to other > passes as well. Yup! I'm trying to break predsimplify down into its composite pieces to replace the behemoth that is the current predsimplify pass. Nick From clattner at apple.com Tue Jun 3 00:08:02 2008 From: clattner at apple.com (Chris Lattner) Date: Mon, 2 Jun 2008 22:08:02 -0700 Subject: [llvm-commits] [llvm] r51885 - /llvm/trunk/lib/CodeGen/AsmPrinter.cpp In-Reply-To: <13962B00-98F4-4D0C-9CC8-93330280ABD6@apple.com> References: <200806022219.m52MJCeZ024222@zion.cs.uiuc.edu> <13962B00-98F4-4D0C-9CC8-93330280ABD6@apple.com> Message-ID: <23F52D58-8791-487A-86AF-EABA2DEC3E11@apple.com> On Jun 2, 2008, at 6:21 PM, Dale Johannesen wrote: > This makes the assembly produced for address+constant look like > > .long (symbol) + (constant #comment) > > Darwin's as actually accepts this, although it whines, but this isn't > right. Please revert the patch until it is fixed. -Chris > > > On Jun 2, 2008, at 3:19 PM, Scott Michel wrote: > >> Author: pingbak >> Date: Mon Jun 2 17:19:12 2008 >> New Revision: 51885 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=51885&view=rev >> Log: >> Minor cosmetic patch so that the hex equivalent of a decimal >> constant shows up in the assembly language output. Helps with >> debugging without a HP calculator having to be handy. >> >> Modified: >> llvm/trunk/lib/CodeGen/AsmPrinter.cpp >> >> Modified: llvm/trunk/lib/CodeGen/AsmPrinter.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter.cpp?rev=51885&r1=51884&r2=51885&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> = >> ===================================================================== >> --- llvm/trunk/lib/CodeGen/AsmPrinter.cpp (original) >> +++ llvm/trunk/lib/CodeGen/AsmPrinter.cpp Mon Jun 2 17:19:12 2008 >> @@ -742,7 +742,9 @@ >> if (CV->isNullValue() || isa(CV)) >> O << "0"; >> else if (const ConstantInt *CI = dyn_cast(CV)) { >> - O << CI->getZExtValue(); >> + O << CI->getZExtValue() << "\t\t\t" >> + << TAI->getCommentString() << " 0x" >> + << CI->getValue().toStringUnsigned(16); >> } else if (const GlobalValue *GV = dyn_cast(CV)) { >> // This is a constant address for a global variable or function. >> Use the >> // name of the variable or function as the address value, possibly >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From bruno.cardoso at gmail.com Tue Jun 3 01:11:38 2008 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 3 Jun 2008 03:11:38 -0300 Subject: [llvm-commits] [PATCH] bad behavior in calculateFrameObjectOffsets Message-ID: <275e64e40806022311r3f05338fhbaf20747ab081a9@mail.gmail.com> Using unsigned in the loop below can lead to bad stack objects access, one example is when MinCSFrameIndex = 0, the variable i doesnt go negative and the loop starts to access fixed objects locations (since getObjectAlignment param is int) overwriting previous calculated stack locations. This is breaking callee saved register spill in Mips. lib/CodeGen/PrologEpilogInserter.cpp, line 365 for (unsigned i = MaxCSFrameIndex; i >= MinCSFrameIndex; --i) { unsigned Align = FFI->getObjectAlignment(i); -- Bruno Cardoso Lopes ( now @ Cocos Island ) http://www.brunocardoso.cc ++ The saddest aspect of life right now is that science gathers knowledge faster than society gathers wisdom + Isaac Asimov -------------- next part -------------- A non-text attachment was scrubbed... Name: PrologEpilogInserter.cpp.patch Type: application/octet-stream Size: 655 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20080603/3c1116da/attachment.obj From scottm at aero.org Tue Jun 3 01:18:20 2008 From: scottm at aero.org (Scott Michel) Date: Tue, 03 Jun 2008 06:18:20 -0000 Subject: [llvm-commits] [llvm] r51897 - /llvm/trunk/lib/CodeGen/AsmPrinter.cpp Message-ID: <200806030618.m536IKvD022419@zion.cs.uiuc.edu> Author: pingbak Date: Tue Jun 3 01:18:19 2008 New Revision: 51897 URL: http://llvm.org/viewvc/llvm-project?rev=51897&view=rev Log: Revert this patch Modified: llvm/trunk/lib/CodeGen/AsmPrinter.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter.cpp?rev=51897&r1=51896&r2=51897&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter.cpp Tue Jun 3 01:18:19 2008 @@ -742,9 +742,7 @@ if (CV->isNullValue() || isa(CV)) O << "0"; else if (const ConstantInt *CI = dyn_cast(CV)) { - O << CI->getZExtValue() << "\t\t\t" - << TAI->getCommentString() << " 0x" - << CI->getValue().toStringUnsigned(16); + O << CI->getZExtValue(); } else if (const GlobalValue *GV = dyn_cast(CV)) { // This is a constant address for a global variable or function. Use the // name of the variable or function as the address value, possibly From evan.cheng at apple.com Tue Jun 3 01:56:08 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 03 Jun 2008 06:56:08 -0000 Subject: [llvm-commits] [llvm] r51898 - /llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Message-ID: <200806030656.m536u8JR023508@zion.cs.uiuc.edu> Author: evancheng Date: Tue Jun 3 01:56:08 2008 New Revision: 51898 URL: http://llvm.org/viewvc/llvm-project?rev=51898&view=rev Log: Do not run loop-aligner at -fast (e.g. -O0). Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=51898&r1=51897&r2=51898&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original) +++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Tue Jun 3 01:56:08 2008 @@ -140,7 +140,7 @@ if (addPreEmitPass(PM, Fast) && PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); - if (AlignLoops && !OptimizeForSize) + if (AlignLoops && !Fast && !OptimizeForSize) PM.add(createLoopAlignerPass()); switch (FileType) { From evan.cheng at apple.com Tue Jun 3 01:58:34 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 2 Jun 2008 23:58:34 -0700 Subject: [llvm-commits] [llvm-gcc-4.2] r51723 - in /llvm-gcc-4.2/trunk/gcc: config/i386/llvm-i386-target.h config/i386/llvm-i386.cpp config/rs6000/llvm-rs6000.cpp llvm-abi.h In-Reply-To: <983E84B7-0FC5-416B-A174-E1D5C0A50E87@apple.com> References: <200805300123.m4U1NDZl019942@zion.cs.uiuc.edu> <4B25ACA3-2667-47BE-8483-B937CEA1719F@apple.com> <983E84B7-0FC5-416B-A174-E1D5C0A50E87@apple.com> Message-ID: <97A489F4-409F-47F6-9EC7-9CC3DCD7563B@apple.com> Purely trial and error. llvm-gcc before this patch works. :-) Evan On Jun 2, 2008, at 7:35 PM, Dale Johannesen wrote: > Not saying you're wrong, but why do you think it's this patch? > > On Jun 2, 2008, at 5:35 PM, Evan Cheng wrote: > >> Hi Dale, >> >> Looks like this patch broke 447.dealII on x86-64. Try this: >> >> make ENABLE_OPTIMIZED=1 TEST=nightly TARGET_FLAGS="-m64 - >> DSPEC_CPU2000_LP64 -DSPEC_CPU_LP64" TARGET_LLCFLAGS="-relocation- >> model=pic -disable-fp-elim" EXTRA_LLI_OPTS="-relocation-model=pic - >> disable-fp-elim" clean Output/447.dealII.diff-llc >> >> Evan >> >> On May 29, 2008, at 6:23 PM, Dale Johannesen wrote: >> >>> Author: johannes >>> Date: Thu May 29 20:23:12 2008 >>> New Revision: 51723 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=51723&view=rev >>> Log: >>> X86-64 ABI fix. Revert isSingleElementStructOrArray >>> change in favor of a more general version which handles >>> the case where there's more than one element correctly. >>> Fixes gcc.dg/compat/struct-layout-1.exp/t003 >>> and many more. >>> >>> >>> Modified: >>> llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h >>> llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp >>> llvm-gcc-4.2/trunk/gcc/config/rs6000/llvm-rs6000.cpp >>> llvm-gcc-4.2/trunk/gcc/llvm-abi.h >>> >>> Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h >>> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h?rev=51723&r1=51722&r2=51723&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ==================================================================== >>> --- llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h (original) >>> +++ llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h Thu May >>> 29 20:23:12 2008 >>> @@ -95,17 +95,18 @@ >>> considered as if they were the type of the data field. */ >>> #ifndef LLVM_SHOULD_RETURN_SELT_STRUCT_AS_SCALAR >>> #define LLVM_SHOULD_RETURN_SELT_STRUCT_AS_SCALAR(X) \ >>> - isSingleElementStructOrArray(X, true, false, false) >>> + isSingleElementStructOrArray(X, true, false) >>> #endif >>> >>> +extern bool llvm_x86_should_pass_aggregate_in_integer_regs(tree, >>> unsigned*); >>> + >>> /* LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS - Return true if >>> this aggregate >>> value should be passed in integer registers. This differs from >>> the usual >>> - handling in that x86-64 passes single-int-element unions as >>> the type of the >>> - field. */ >>> -#define >>> LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS(X) \ >>> - >>> (TARGET_64BIT ? \ >>> - !isSingleElementStructOrArray((X), true, true, >>> true) : \ >>> - !isSingleElementStructOrArray((X), false, true, false)) >>> + handling in that x86-64 passes 128-bit structs and unions >>> which only >>> + contain data in the first 64 bits, as 64-bit objects. (These >>> can be >>> + created by abusing __attribute__((aligned)). */ >>> +#define LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS(X, >>> Y) \ >>> + llvm_x86_should_pass_aggregate_in_integer_regs((X), (Y)) >>> >>> extern bool llvm_x86_should_pass_vector_in_integer_regs(tree); >>> >>> >>> Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp >>> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp?rev=51723&r1=51722&r2=51723&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ==================================================================== >>> --- llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp (original) >>> +++ llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp Thu May 29 >>> 20:23:12 2008 >>> @@ -1288,4 +1288,38 @@ >>> return Loc; >>> } >>> >>> +/// llvm_x86_should_pass_aggregate_in_integer_regs - x86-32 is >>> same as the >>> +/// default. x86-64 detects the case where a type is 16 bytes >>> long but >>> +/// only 8 of them are passed, the rest being padding (*size is >>> set to 8 >>> +/// to identify this case). >>> +bool llvm_x86_should_pass_aggregate_in_integer_regs(tree type, >>> unsigned *size) >>> +{ >>> + *size = 0; >>> + if (TARGET_64BIT) { >>> + enum x86_64_reg_class Class[MAX_CLASSES]; >>> + enum machine_mode Mode = ix86_getNaturalModeForType(type); >>> + int NumClasses = ix86_ClassifyArgument(Mode, type, Class, 0); >>> + if (NumClasses == 1 && (Class[0] == X86_64_INTEGERSI_CLASS || >>> + Class[0] == X86_64_INTEGER_CLASS)) { >>> + /* 8 byte object, one int register */ >>> + return true; >>> + } >>> + if (NumClasses == 2 && (Class[0] == X86_64_INTEGERSI_CLASS || >>> + Class[0] == X86_64_INTEGER_CLASS)) { >>> + if (Class[1] == X86_64_INTEGERSI_CLASS || >>> + Class[1] == X86_64_INTEGER_CLASS) >>> + /* 16 byte object, 2 int registers */ >>> + return true; >>> + if (Class[1] == X86_64_NO_CLASS) { >>> + /* 16 byte object, only 1st register has information */ >>> + *size = 8; >>> + return true; >>> + } >>> + } >>> + return false; >>> + } >>> + else >>> + return !isSingleElementStructOrArray(type, false, true); >>> +} >>> + >>> /* LLVM LOCAL end (ENTIRE FILE!) */ >>> >>> Modified: llvm-gcc-4.2/trunk/gcc/config/rs6000/llvm-rs6000.cpp >>> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/rs6000/llvm-rs6000.cpp?rev=51723&r1=51722&r2=51723&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ==================================================================== >>> --- llvm-gcc-4.2/trunk/gcc/config/rs6000/llvm-rs6000.cpp (original) >>> +++ llvm-gcc-4.2/trunk/gcc/config/rs6000/llvm-rs6000.cpp Thu May >>> 29 20:23:12 2008 >>> @@ -404,7 +404,7 @@ >>> // some zero-length fields as well, must be passed as the field >>> type. >>> // Note this does not apply to long double. >>> // This is required for ABI correctness. >>> - tree tType = isSingleElementStructOrArray(TreeType, true, >>> false, false); >>> + tree tType = isSingleElementStructOrArray(TreeType, true, false); >>> if (tType && int_size_in_bytes(tType)==Bytes && TYPE_MODE(tType)! >>> =TFmode && >>> (TREE_CODE(tType)!=VECTOR_TYPE || Bytes==16)) >>> return false; >>> @@ -437,7 +437,7 @@ >>> // Other single-element structs may be passed this way as well, but >>> // only if the type size matches the element's type size (structs >>> that >>> // violate this can be created with __aligned__). >>> - tree tType = isSingleElementStructOrArray(TreeType, true, >>> false, false); >>> + tree tType = isSingleElementStructOrArray(TreeType, true, false); >>> if (tType && int_size_in_bytes(tType)==SrcSize && TYPE_MODE(tType)! >>> =TFmode && >>> (TREE_CODE(tType)!=VECTOR_TYPE || SrcSize==16)) { >>> Elts.push_back(ConvertType(tType)); >>> >>> Modified: llvm-gcc-4.2/trunk/gcc/llvm-abi.h >>> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-abi.h?rev=51723&r1=51722&r2=51723&view=diff >>> >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> = >>> ==================================================================== >>> --- llvm-gcc-4.2/trunk/gcc/llvm-abi.h (original) >>> +++ llvm-gcc-4.2/trunk/gcc/llvm-abi.h Thu May 29 20:23:12 2008 >>> @@ -138,21 +138,17 @@ >>> /// rejectFatBitField, and the single element is a bitfield of a >>> type that's >>> /// bigger than the struct, return null anyway. >>> static tree isSingleElementStructOrArray(tree type, bool >>> ignoreZeroLength, >>> - bool rejectFatBitfield, >>> - bool acceptUnions) { >>> + bool rejectFatBitfield) { >>> // Scalars are good. >>> if (!isAggregateTreeType(type)) return type; >>> >>> tree FoundField = 0; >>> switch (TREE_CODE(type)) { >>> case QUAL_UNION_TYPE: >>> + case UNION_TYPE: // Single element unions don't count. >>> case COMPLEX_TYPE: // Complex values are like 2-element records. >>> default: >>> return 0; >>> - case UNION_TYPE: // Single element unions don't count. >>> - if (!acceptUnions) >>> - return 0; >>> - // fall through >>> case RECORD_TYPE: >>> // If this record has variable length, reject it. >>> if (TREE_CODE(TYPE_SIZE(type)) != INTEGER_CST) >>> @@ -178,15 +174,13 @@ >>> } >>> } >>> return FoundField ? isSingleElementStructOrArray(FoundField, >>> - >>> ignoreZeroLength, false, >>> - false) >>> + >>> ignoreZeroLength, false) >>> : 0; >>> case ARRAY_TYPE: >>> const ArrayType *Ty = dyn_cast(ConvertType(type)); >>> if (!Ty || Ty->getNumElements() != 1) >>> return 0; >>> - return isSingleElementStructOrArray(TREE_TYPE(type), false, >>> false, >>> - false); >>> + return isSingleElementStructOrArray(TREE_TYPE(type), false, >>> false); >>> } >>> } >>> >>> @@ -283,8 +277,8 @@ >>> // single element is a bitfield of a type bigger than the struct; >>> the code >>> // for field-by-field struct passing does not handle this one right. >>> #ifndef LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS >>> -#define LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS(X) \ >>> - !isSingleElementStructOrArray(X, false, true, false) >>> +#define LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS(X, Y) \ >>> + !isSingleElementStructOrArray((X), false, true) >>> #endif >>> >>> // LLVM_SHOULD_RETURN_SELT_STRUCT_AS_SCALAR - Return a TYPE tree >>> if this single >>> @@ -295,7 +289,7 @@ >>> // by abusing the __aligned__ attribute.) >>> #ifndef LLVM_SHOULD_RETURN_SELT_STRUCT_AS_SCALAR >>> #define LLVM_SHOULD_RETURN_SELT_STRUCT_AS_SCALAR(X) \ >>> - isSingleElementStructOrArray(X, false, false, false) >>> + isSingleElementStructOrArray(X, false, false) >>> #endif >>> >>> // LLVM_SHOULD_RETURN_VECTOR_AS_SCALAR - Return a TYPE tree if >>> this vector type >>> @@ -408,6 +402,7 @@ >>> /// their fields. >>> void HandleArgument(tree type, std::vector &ScalarElts, >>> ParameterAttributes *Attributes = NULL) { >>> + unsigned Size = 0; >>> const Type *Ty = ConvertType(type); >>> // Figure out if this field is zero bits wide, e.g. {} or [0 x >>> int]. Do >>> // not include variable sized fields here. >>> @@ -418,7 +413,7 @@ >>> ScalarElts.push_back(PtrTy); >>> } else if (Ty->getTypeID()==Type::VectorTyID) { >>> if (LLVM_SHOULD_PASS_VECTOR_IN_INTEGER_REGS(type)) { >>> - PassInIntegerRegisters(type, Ty, ScalarElts); >>> + PassInIntegerRegisters(type, Ty, ScalarElts, 0); >>> } else { >>> C.HandleScalarArgument(Ty, type); >>> ScalarElts.push_back(Ty); >>> @@ -444,8 +439,8 @@ >>> *Attributes |= >>> >>> ParamAttr::constructAlignmentFromInt(LLVM_BYVAL_ALIGNMENT(type)); >>> } >>> - } else if (LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS(type)) { >>> - PassInIntegerRegisters(type, Ty, ScalarElts); >>> + } else if (LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS(type, >>> &Size)) { >>> + PassInIntegerRegisters(type, Ty, ScalarElts, Size); >>> } else if (isZeroSizedStructOrUnion(type)) { >>> // Zero sized struct or union, just drop it! >>> ; >>> @@ -526,10 +521,15 @@ >>> >>> /// PassInIntegerRegisters - Given an aggregate value that should >>> be passed in >>> /// integer registers, convert it to a structure containing ints >>> and pass all >>> - /// of the struct elements in. >>> + /// of the struct elements in. If Size is set we pass only >>> that many bytes. >>> void PassInIntegerRegisters(tree type, const Type *Ty, >>> - std::vector >>> &ScalarElts) { >>> - unsigned Size = TREE_INT_CST_LOW(TYPE_SIZE(type))/8; >>> + std::vector &ScalarElts, >>> + unsigned origSize) { >>> + unsigned Size; >>> + if (origSize) >>> + Size = origSize; >>> + else >>> + Size = TREE_INT_CST_LOW(TYPE_SIZE(type))/8; >>> >>> // FIXME: We should preserve all aggregate value alignment >>> information. >>> // Work around to preserve some aggregate value alignment >>> information: >>> @@ -568,7 +568,7 @@ >>> Elts.push_back(Type::Int8Ty); >>> Size -= 1; >>> } >>> - assert(Size == 0 && "Didn't cover value?"); >>> + assert((origSize || Size == 0) && "Didn't cover value?"); >>> const StructType *STy = StructType::get(Elts, false); >>> >>> unsigned i = 0; >>> >>> >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> > From evan.cheng at apple.com Tue Jun 3 02:00:25 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 3 Jun 2008 00:00:25 -0700 Subject: [llvm-commits] [PATCH] bad behavior in calculateFrameObjectOffsets In-Reply-To: <275e64e40806022311r3f05338fhbaf20747ab081a9@mail.gmail.com> References: <275e64e40806022311r3f05338fhbaf20747ab081a9@mail.gmail.com> Message-ID: <3FE0314A-0385-402A-A695-247B38DE101A@apple.com> Oops. Please commit. Evan On Jun 2, 2008, at 11:11 PM, Bruno Cardoso Lopes wrote: > Using unsigned in the loop below can lead to bad stack objects access, > one example is when > MinCSFrameIndex = 0, the variable i doesnt go negative > and the loop starts to access fixed objects locations (since > getObjectAlignment > param is int) overwriting previous calculated stack locations. This is > breaking callee > saved register spill in Mips. > > lib/CodeGen/PrologEpilogInserter.cpp, line 365 > for (unsigned i = MaxCSFrameIndex; i >= MinCSFrameIndex; --i) { > unsigned Align = FFI->getObjectAlignment(i); > > -- > Bruno Cardoso Lopes ( now @ Cocos Island ) > http://www.brunocardoso.cc > > ++ The saddest aspect of life right now is that > science gathers knowledge faster than society > gathers wisdom + Isaac Asimov > < > PrologEpilogInserter > .cpp.patch>_______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From baldrick at free.fr Tue Jun 3 02:59:39 2008 From: baldrick at free.fr (Duncan Sands) Date: Tue, 3 Jun 2008 09:59:39 +0200 Subject: [llvm-commits] [llvm] r51884 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp lib/Target/CellSPU/SPUISelLowering.cpp lib/Target/CellSPU/SPUISelLowering.h lib/Target/CellSPU/SPUInstrInfo.td lib/Target/CellSPU/SPUNodes.td lib/Target/CellSPU/SPUOperands.td test/CodeGen/CellSPU/immed64.ll In-Reply-To: <200806022218.m52MI4Ud024127@zion.cs.uiuc.edu> References: <200806022218.m52MI4Ud024127@zion.cs.uiuc.edu> Message-ID: <200806030959.39385.baldrick@free.fr> Hi, > + assert(VT2 == Tmp3.getValueType() > + && "PromoteOp: Operands 2 and 3 ValueTypes don't match"); it is not usual for assertions to mention the function in which they occur. > + // Ensure tha NVT is the same as the operands' value types, because we Ensure tha -> Ensure that Ciao, Duncan. From bruno.cardoso at gmail.com Tue Jun 3 03:47:00 2008 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 03 Jun 2008 08:47:00 -0000 Subject: [llvm-commits] [llvm] r51899 - /llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp Message-ID: <200806030847.m538l0Gj002654@zion.cs.uiuc.edu> Author: bruno Date: Tue Jun 3 03:46:59 2008 New Revision: 51899 URL: http://llvm.org/viewvc/llvm-project?rev=51899&view=rev Log: Fixed bug in bad behavior in calculateFrameObjectOffsets, the solution commited is different from the previous patch to avoid int and unsigned comparison Modified: llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp Modified: llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp?rev=51899&r1=51898&r2=51899&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp (original) +++ llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp Tue Jun 3 03:46:59 2008 @@ -362,7 +362,8 @@ FFI->setObjectOffset(i, -Offset); // Set the computed offset } } else { - for (unsigned i = MaxCSFrameIndex; i >= MinCSFrameIndex; --i) { + int MaxCSFI = MaxCSFrameIndex, MinCSFI = MinCSFrameIndex; + for (int i = MaxCSFI; i >= MinCSFI ; --i) { unsigned Align = FFI->getObjectAlignment(i); // If the alignment of this object is greater than that of the stack, then // increase the stack alignment to match. From matthijs at stdin.nl Tue Jun 3 04:23:08 2008 From: matthijs at stdin.nl (Matthijs Kooijman) Date: Tue, 3 Jun 2008 11:23:08 +0200 Subject: [llvm-commits] [PATCH] Add support for loads and stores of first class aggregrates to ScalarReplaceAggregrates In-Reply-To: <20080530144352.GI13410@katherina.student.utwente.nl> References: <20080530144352.GI13410@katherina.student.utwente.nl> Message-ID: <20080603092308.GM25337@katherina.student.utwente.nl> Hi All, can I conclude from the lack of replies that this is okay to go in? I don't think there will be any direct benefit or influence, since first class scalars aren't really generated anywhere yet. Attached is an updated patch, that compiles again after Dan's changes to the insert/extractvalue instructions. Gr. Matthijs -------------- next part -------------- A non-text attachment was scrubbed... Name: scalarrepl.diff Type: text/x-diff Size: 3135 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20080603/cb9c9e5f/attachment.bin -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 189 bytes Desc: Digital signature Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20080603/cb9c9e5f/attachment-0001.bin From baldrick at free.fr Tue Jun 3 10:18:05 2008 From: baldrick at free.fr (Duncan Sands) Date: Tue, 03 Jun 2008 15:18:05 -0000 Subject: [llvm-commits] [test-suite] r51903 - /test-suite/trunk/SingleSource/UnitTests/Vector/SSE/Makefile Message-ID: <200806031518.m53FI5Ru015250@zion.cs.uiuc.edu> Author: baldrick Date: Tue Jun 3 10:18:05 2008 New Revision: 51903 URL: http://llvm.org/viewvc/llvm-project?rev=51903&view=rev Log: Add -lm, needed by the CBE. Modified: test-suite/trunk/SingleSource/UnitTests/Vector/SSE/Makefile Modified: test-suite/trunk/SingleSource/UnitTests/Vector/SSE/Makefile URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/Vector/SSE/Makefile?rev=51903&r1=51902&r2=51903&view=diff ============================================================================== --- test-suite/trunk/SingleSource/UnitTests/Vector/SSE/Makefile (original) +++ test-suite/trunk/SingleSource/UnitTests/Vector/SSE/Makefile Tue Jun 3 10:18:05 2008 @@ -3,6 +3,7 @@ DIRS = LEVEL = ../../../.. FP_TOLERANCE := 0.016 +LDFLAGS += -lm include $(LEVEL)/SingleSource/Makefile.singlesrc From scottm at aero.org Tue Jun 3 10:39:51 2008 From: scottm at aero.org (Scott Michel) Date: Tue, 03 Jun 2008 15:39:51 -0000 Subject: [llvm-commits] [llvm] r51904 - /llvm/trunk/lib/CodeGen/AsmPrinter.cpp Message-ID: <200806031539.m53FdpdY015874@zion.cs.uiuc.edu> Author: pingbak Date: Tue Jun 3 10:39:51 2008 New Revision: 51904 URL: http://llvm.org/viewvc/llvm-project?rev=51904&view=rev Log: Find a better place to output hex constants corresponding to integers. Modified: llvm/trunk/lib/CodeGen/AsmPrinter.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter.cpp?rev=51904&r1=51903&r2=51904&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter.cpp Tue Jun 3 10:39:51 2008 @@ -1074,6 +1074,11 @@ const Type *type = CV->getType(); printDataDirective(type); EmitConstantValueOnly(CV); + if (const ConstantInt *CI = dyn_cast(CV)) { + O << "\t\t\t" + << TAI->getCommentString() + << " 0x" << CI->getValue().toStringUnsigned(16); + } O << "\n"; } From asl at math.spbu.ru Tue Jun 3 11:03:12 2008 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Tue, 03 Jun 2008 16:03:12 -0000 Subject: [llvm-commits] [test-suite] r51905 - /test-suite/trunk/SingleSource/Benchmarks/CoyoteBench/fftbench.cpp Message-ID: <200806031603.m53G3CEj016861@zion.cs.uiuc.edu> Author: asl Date: Tue Jun 3 11:03:12 2008 New Revision: 51905 URL: http://llvm.org/viewvc/llvm-project?rev=51905&view=rev Log: Reduce testsize even more. This is needed at least on x86-32/linux Modified: test-suite/trunk/SingleSource/Benchmarks/CoyoteBench/fftbench.cpp Modified: test-suite/trunk/SingleSource/Benchmarks/CoyoteBench/fftbench.cpp URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/Benchmarks/CoyoteBench/fftbench.cpp?rev=51905&r1=51904&r2=51905&view=diff ============================================================================== --- test-suite/trunk/SingleSource/Benchmarks/CoyoteBench/fftbench.cpp (original) +++ test-suite/trunk/SingleSource/Benchmarks/CoyoteBench/fftbench.cpp Tue Jun 3 11:03:12 2008 @@ -46,7 +46,7 @@ #ifdef SMALL_PROBLEM_SIZE static const int TEST_SIZE = 50000; #else -static const int TEST_SIZE = 2097152/2; +static const int TEST_SIZE = 2097152/4; #endif #endif From tonic at nondot.org Tue Jun 3 11:08:20 2008 From: tonic at nondot.org (Tanya Lattner) Date: Tue, 03 Jun 2008 16:08:20 -0000 Subject: [llvm-commits] [test-suite] r51906 - /test-suite/branches/release_23/SingleSource/Benchmarks/CoyoteBench/fftbench.cpp Message-ID: <200806031608.m53G8Kgj017037@zion.cs.uiuc.edu> Author: tbrethou Date: Tue Jun 3 11:08:19 2008 New Revision: 51906 URL: http://llvm.org/viewvc/llvm-project?rev=51906&view=rev Log: Merge from mainline. Modified: test-suite/branches/release_23/SingleSource/Benchmarks/CoyoteBench/fftbench.cpp Modified: test-suite/branches/release_23/SingleSource/Benchmarks/CoyoteBench/fftbench.cpp URL: http://llvm.org/viewvc/llvm-project/test-suite/branches/release_23/SingleSource/Benchmarks/CoyoteBench/fftbench.cpp?rev=51906&r1=51905&r2=51906&view=diff ============================================================================== --- test-suite/branches/release_23/SingleSource/Benchmarks/CoyoteBench/fftbench.cpp (original) +++ test-suite/branches/release_23/SingleSource/Benchmarks/CoyoteBench/fftbench.cpp Tue Jun 3 11:08:19 2008 @@ -46,7 +46,7 @@ #ifdef SMALL_PROBLEM_SIZE static const int TEST_SIZE = 50000; #else -static const int TEST_SIZE = 2097152/2; +static const int TEST_SIZE = 2097152/4; #endif #endif From clattner at apple.com Tue Jun 3 11:29:03 2008 From: clattner at apple.com (Chris Lattner) Date: Tue, 3 Jun 2008 09:29:03 -0700 Subject: [llvm-commits] [llvm] r51904 - /llvm/trunk/lib/CodeGen/AsmPrinter.cpp In-Reply-To: <200806031539.m53FdpdY015874@zion.cs.uiuc.edu> References: <200806031539.m53FdpdY015874@zion.cs.uiuc.edu> Message-ID: <4965F0E1-15C5-45EC-B084-22A5FFA5A6D5@apple.com> > URL: http://llvm.org/viewvc/llvm-project?rev=51904&view=rev > Log: > Find a better place to output hex constants corresponding to integers. Hey Scott, how much does this affect -O0 compile times? Doing at least one extra malloc/free is very bad for each constant. -Chris > > > Modified: > llvm/trunk/lib/CodeGen/AsmPrinter.cpp > > Modified: llvm/trunk/lib/CodeGen/AsmPrinter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter.cpp?rev=51904&r1=51903&r2=51904&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/CodeGen/AsmPrinter.cpp (original) > +++ llvm/trunk/lib/CodeGen/AsmPrinter.cpp Tue Jun 3 10:39:51 2008 > @@ -1074,6 +1074,11 @@ > const Type *type = CV->getType(); > printDataDirective(type); > EmitConstantValueOnly(CV); > + if (const ConstantInt *CI = dyn_cast(CV)) { > + O << "\t\t\t" > + << TAI->getCommentString() > + << " 0x" << CI->getValue().toStringUnsigned(16); > + } > O << "\n"; > } > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From dalej at apple.com Tue Jun 3 12:57:17 2008 From: dalej at apple.com (Dale Johannesen) Date: Tue, 3 Jun 2008 10:57:17 -0700 Subject: [llvm-commits] [llvm-gcc-4.2] r51866 - /llvm-gcc-4.2/trunk/gcc/llvm-types.cpp In-Reply-To: <200806021556.m52FunYg008136@zion.cs.uiuc.edu> References: <200806021556.m52FunYg008136@zion.cs.uiuc.edu> Message-ID: This patch breaks FrontendC/2008-01-28-UnionSize.c and FrontendC/ 2007-09-28-PackedUnionMember.c on Darwin x86-32. FAIL: /Volumes/MacOS9/gcc/llvm/test/FrontendC/2007-09-28- PackedUnionMember.c Failed with exit(1) at line 1 while running: /usr/local/bin/llvm-gcc -emit-llvm /Volumes/MacOS9/gcc/ llvm/test/FrontendC/2007-09-28-PackedUnionMember.c -S -o - Assertion failed: ((!TYPE_SIZE(Tr) || !Ty->isSized() || ! isInt64(TYPE_SIZE(Tr), true) || getInt64(TYPE_SIZE(Tr), true) == getTargetData().getABITypeSizeInBits(Ty)) && "LLVM type size doesn't match GCC type size!"), function llvm_set_type, file ../../llvm- gcc-4.2/gcc/llvm-types.cpp, line 84. /Volumes/MacOS9/gcc/llvm/test/FrontendC/2007-09-28- PackedUnionMember.c: In function ?hndlr?: It's odd that the nightly testers aren't showing this. I suspect they aren't rebuilding llvm-gcc every night. On Jun 2, 2008, at 8:56 AM, Duncan Sands wrote: > Author: baldrick > Date: Mon Jun 2 10:56:49 2008 > New Revision: 51866 > > URL: http://llvm.org/viewvc/llvm-project?rev=51866&view=rev > Log: > Fix 2003-10-09-UnionInitializerBug.c on x86-64. > The problem was that in ConvertUNION if the > new field was less aligned than a previous one > but was also the biggest field seen so far then > it was selected. But the most aligned field is > supposed to always be selected. This caused a > crash in ConvertStructFieldInitializerToType > which relies on initializers not being more > aligned than the LLVM type. In the long run > I think ConvertStructFieldInitializerToType > should be modified to not care about the > alignment. > > Modified: > llvm-gcc-4.2/trunk/gcc/llvm-types.cpp > > Modified: llvm-gcc-4.2/trunk/gcc/llvm-types.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-types.cpp?rev=51866&r1=51865&r2=51866&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm-gcc-4.2/trunk/gcc/llvm-types.cpp (original) > +++ llvm-gcc-4.2/trunk/gcc/llvm-types.cpp Mon Jun 2 10:56:49 2008 > @@ -2179,7 +2179,7 @@ > const TargetData &TD = getTargetData(); > const Type *UnionTy = 0; > tree GccUnionTy = 0; > - unsigned MaxSize = 0, MaxAlign = 0; > + unsigned MaxAlignSize = 0, MaxAlign = 0; > for (tree Field = TYPE_FIELDS(type); Field; Field = > TREE_CHAIN(Field)) { > if (TREE_CODE(Field) != FIELD_DECL) continue; > // assert(getFieldOffsetInBits(Field) == 0 && "Union with non- > zero offset?"); > @@ -2233,29 +2233,27 @@ > const Type *TheTy = ConvertType(TheGccTy); > unsigned Size = TD.getABITypeSize(TheTy); > unsigned Align = TD.getABITypeAlignment(TheTy); > - > + > adjustPaddingElement(GccUnionTy, TheGccTy); > > - // Select TheTy as union type if it meets one of the following > criteria > - // 1) UnionTy is 0 > - // 2) TheTy alignment is more then UnionTy > - // 3) TheTy size is greater than UnionTy size and TheTy > alignment is > - // equal to UnionTy > - // 4) TheTy size is greater then UnionTy size and TheTy is packed > - bool useTheTy = false; > + // Select TheTy as union type if it is more aligned than any > other. If more > + // than one field achieves the maximum alignment then choose > the biggest. > + bool useTheTy; > if (UnionTy == 0) > useTheTy = true; > + else if (Align < MaxAlign) > + useTheTy = false; > else if (Align > MaxAlign) > useTheTy = true; > - else if (MaxAlign == Align && Size > MaxSize) > - useTheTy = true; > - else if (Size > MaxSize) > + else if (Size > MaxAlignSize) > useTheTy = true; > + else > + useTheTy = false; > > if (useTheTy) { > UnionTy = TheTy; > GccUnionTy = TheGccTy; > - MaxSize = MAX(MaxSize, Size); > + MaxAlignSize = Size; > MaxAlign = Align; > } > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From dalej at apple.com Tue Jun 3 13:09:06 2008 From: dalej at apple.com (Dale Johannesen) Date: Tue, 03 Jun 2008 18:09:06 -0000 Subject: [llvm-commits] [llvm] r51909 - in /llvm/trunk: include/llvm/Target/TargetAsmInfo.h lib/Target/ARM/ARMTargetAsmInfo.cpp lib/Target/PowerPC/PPCTargetAsmInfo.cpp lib/Target/TargetAsmInfo.cpp lib/Target/X86/X86TargetAsmInfo.cpp Message-ID: <200806031809.m53I97kY022205@zion.cs.uiuc.edu> Author: johannes Date: Tue Jun 3 13:09:06 2008 New Revision: 51909 URL: http://llvm.org/viewvc/llvm-project?rev=51909&view=rev Log: Add StringConstantPrefix to control what the assembler names of string constants look like. Modified: llvm/trunk/include/llvm/Target/TargetAsmInfo.h llvm/trunk/lib/Target/ARM/ARMTargetAsmInfo.cpp llvm/trunk/lib/Target/PowerPC/PPCTargetAsmInfo.cpp llvm/trunk/lib/Target/TargetAsmInfo.cpp llvm/trunk/lib/Target/X86/X86TargetAsmInfo.cpp Modified: llvm/trunk/include/llvm/Target/TargetAsmInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetAsmInfo.h?rev=51909&r1=51908&r2=51909&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetAsmInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetAsmInfo.h Tue Jun 3 13:09:06 2008 @@ -147,6 +147,10 @@ /// AssemblerDialect - Which dialect of an assembler variant to use. unsigned AssemblerDialect; // Defaults to 0 + /// StringConstantPrefix - Prefix to use when generating unnamed + /// constant strings. These names get run through the Mangler later. + const char *StringConstantPrefix; // Defaults to ".str" + //===--- Data Emission Directives -------------------------------------===// /// ZeroDirective - this should be set to the directive used to get some @@ -496,6 +500,9 @@ unsigned getAssemblerDialect() const { return AssemblerDialect; } + const char *getStringConstantPrefix() const { + return StringConstantPrefix; + } const char *getZeroDirective() const { return ZeroDirective; } Modified: llvm/trunk/lib/Target/ARM/ARMTargetAsmInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetAsmInfo.cpp?rev=51909&r1=51908&r2=51909&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMTargetAsmInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMTargetAsmInfo.cpp Tue Jun 3 13:09:06 2008 @@ -48,6 +48,7 @@ if (Subtarget->isTargetDarwin()) { GlobalPrefix = "_"; PrivateGlobalPrefix = "L"; + StringConstantPrefix = "\1LC"; BSSSection = 0; // no BSS section. ZeroFillDirective = "\t.zerofill\t"; // Uses .zerofill SetDirective = "\t.set\t"; Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetAsmInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetAsmInfo.cpp?rev=51909&r1=51908&r2=51909&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCTargetAsmInfo.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCTargetAsmInfo.cpp Tue Jun 3 13:09:06 2008 @@ -39,6 +39,7 @@ CommentString = ";"; GlobalPrefix = "_"; PrivateGlobalPrefix = "L"; + StringConstantPrefix = "\1LC"; ConstantPoolSection = "\t.const\t"; JumpTableDataSection = ".const"; CStringSection = "\t.cstring"; Modified: llvm/trunk/lib/Target/TargetAsmInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetAsmInfo.cpp?rev=51909&r1=51908&r2=51909&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetAsmInfo.cpp (original) +++ llvm/trunk/lib/Target/TargetAsmInfo.cpp Tue Jun 3 13:09:06 2008 @@ -45,6 +45,7 @@ InlineAsmStart("#APP"), InlineAsmEnd("#NO_APP"), AssemblerDialect(0), + StringConstantPrefix(".str"), ZeroDirective("\t.zero\t"), ZeroDirectiveSuffix(0), AsciiDirective("\t.ascii\t"), Modified: llvm/trunk/lib/Target/X86/X86TargetAsmInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetAsmInfo.cpp?rev=51909&r1=51908&r2=51909&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86TargetAsmInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86TargetAsmInfo.cpp Tue Jun 3 13:09:06 2008 @@ -66,6 +66,7 @@ ReadOnlySection = "\t.const\n"; LCOMMDirective = "\t.lcomm\t"; SwitchToSectionDirective = "\t.section "; + StringConstantPrefix = "\1LC"; COMMDirectiveTakesAlignment = false; HasDotTypeDotSizeDirective = false; if (TM.getRelocationModel() == Reloc::Static) { From dalej at apple.com Tue Jun 3 13:14:30 2008 From: dalej at apple.com (Dale Johannesen) Date: Tue, 03 Jun 2008 18:14:30 -0000 Subject: [llvm-commits] [llvm] r51910 - /llvm/trunk/lib/VMCore/AsmWriter.cpp Message-ID: <200806031814.m53IEUIA022419@zion.cs.uiuc.edu> Author: johannes Date: Tue Jun 3 13:14:29 2008 New Revision: 51910 URL: http://llvm.org/viewvc/llvm-project?rev=51910&view=rev Log: Prevent a crash in debug dumps. Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AsmWriter.cpp?rev=51910&r1=51909&r2=51910&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/AsmWriter.cpp (original) +++ llvm/trunk/lib/VMCore/AsmWriter.cpp Tue Jun 3 13:14:29 2008 @@ -979,7 +979,11 @@ } void AssemblyWriter::printAlias(const GlobalAlias *GA) { - Out << getLLVMName(GA->getName(), GlobalPrefix) << " = "; + // Don't crash when dumping partially built GA + if (!GA->hasName()) + Out << "<> = "; + else + Out << getLLVMName(GA->getName(), GlobalPrefix) << " = "; switch (GA->getVisibility()) { default: assert(0 && "Invalid visibility style!"); case GlobalValue::DefaultVisibility: break; From dalej at apple.com Tue Jun 3 13:15:04 2008 From: dalej at apple.com (Dale Johannesen) Date: Tue, 03 Jun 2008 18:15:04 -0000 Subject: [llvm-commits] [llvm] r51911 - /llvm/trunk/include/llvm/Target/TargetAsmInfo.h Message-ID: <200806031815.m53IF4Y5022450@zion.cs.uiuc.edu> Author: johannes Date: Tue Jun 3 13:15:03 2008 New Revision: 51911 URL: http://llvm.org/viewvc/llvm-project?rev=51911&view=rev Log: Expand documentation of StringConstantPrefix. Modified: llvm/trunk/include/llvm/Target/TargetAsmInfo.h Modified: llvm/trunk/include/llvm/Target/TargetAsmInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetAsmInfo.h?rev=51911&r1=51910&r2=51911&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetAsmInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetAsmInfo.h Tue Jun 3 13:15:03 2008 @@ -147,8 +147,10 @@ /// AssemblerDialect - Which dialect of an assembler variant to use. unsigned AssemblerDialect; // Defaults to 0 - /// StringConstantPrefix - Prefix to use when generating unnamed - /// constant strings. These names get run through the Mangler later. + /// StringConstantPrefix - Prefix for FEs to use when generating unnamed + /// constant strings. These names get run through the Mangler later; if + /// you want the Mangler not to add the GlobalPrefix as well, + /// use '\1' as the first character. const char *StringConstantPrefix; // Defaults to ".str" //===--- Data Emission Directives -------------------------------------===// From dalej at apple.com Tue Jun 3 13:16:19 2008 From: dalej at apple.com (Dale Johannesen) Date: Tue, 03 Jun 2008 18:16:19 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r51912 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Message-ID: <200806031816.m53IGKuF022489@zion.cs.uiuc.edu> Author: johannes Date: Tue Jun 3 13:16:19 2008 New Revision: 51912 URL: http://llvm.org/viewvc/llvm-project?rev=51912&view=rev Log: Use StringConstantPrefix to control the names of constant strings in the IR. Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=51912&r1=51911&r2=51912&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Tue Jun 3 13:16:19 2008 @@ -6604,9 +6604,12 @@ } // Create a new string global. + const TargetAsmInfo *TAI = TheTarget->getTargetAsmInfo(); GlobalVariable *GV = new GlobalVariable(Init->getType(), StringIsConstant, - GlobalVariable::InternalLinkage, - Init, ".str", TheModule); + GlobalVariable::InternalLinkage, Init, + TAI ? + TAI->getStringConstantPrefix() : + ".str", TheModule); if (SlotP) *SlotP = GV; return GV; } From dalej at apple.com Tue Jun 3 13:21:35 2008 From: dalej at apple.com (Dale Johannesen) Date: Tue, 03 Jun 2008 18:21:35 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r51914 - /llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp Message-ID: <200806031821.m53ILZMc022692@zion.cs.uiuc.edu> Author: johannes Date: Tue Jun 3 13:21:34 2008 New Revision: 51914 URL: http://llvm.org/viewvc/llvm-project?rev=51914&view=rev Log: Handle some cases of mixed register use on x86-64. Fixes a few more struct-layout-1 cases. Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp?rev=51914&r1=51913&r2=51914&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp Tue Jun 3 13:21:34 2008 @@ -743,14 +743,18 @@ case X86_64_SSE_CLASS: // If it's a SSE class argument, then one of the followings are possible: // 1. 1 x SSE, size is 8: 1 x Double. - // 2. 1 x SSE + 1 x SSEUP, size is 16: 1 x <4 x i32>, <4 x f32>, + // 2. 1 x SSE, size is 4: 1 x Float. + // 3. 1 x SSE + 1 x SSEUP, size is 16: 1 x <4 x i32>, <4 x f32>, // <2 x i64>, or <2 x f64>. - // 3. 1 x SSE + 1 x SSESF, size is 12: 1 x Double, 1 x Float. - // 4. 2 x SSE, size is 16: 2 x Double. + // 4. 1 x SSE + 1 x SSESF, size is 12: 1 x Double, 1 x Float. + // 5. 2 x SSE, size is 16: 2 x Double. if ((NumClasses-i) == 1) { if (Bytes == 8) { Elts.push_back(Type::DoubleTy); Bytes -= 8; + } else if (Bytes == 4) { + Elts.push_back (Type::FloatTy); + Bytes -= 4; } else assert(0 && "Not yet handled!"); } else if ((NumClasses-i) == 2) { @@ -799,6 +803,10 @@ } else if (Class[i+1] == X86_64_INTEGER_CLASS) { Elts.push_back(VectorType::get(Type::FloatTy, 2)); Elts.push_back(Type::Int64Ty); + } else if (Class[i+1] == X86_64_NO_CLASS) { + // padding bytes, don't pass + Elts.push_back(Type::DoubleTy); + Bytes -= 16; } else assert(0 && "Not yet handled!"); ++i; // Already handled the next one. @@ -1001,14 +1009,18 @@ case X86_64_SSE_CLASS: // If it's a SSE class argument, then one of the followings are possible: // 1. 1 x SSE, size is 8: 1 x Double. - // 2. 1 x SSE + 1 x SSEUP, size is 16: 1 x <4 x i32>, <4 x f32>, + // 2. 1 x SSE, size is 4: 1 x Float. + // 3. 1 x SSE + 1 x SSEUP, size is 16: 1 x <4 x i32>, <4 x f32>, // <2 x i64>, or <2 x f64>. - // 3. 1 x SSE + 1 x SSESF, size is 12: 1 x Double, 1 x Float. - // 4. 2 x SSE, size is 16: 2 x Double. + // 4. 1 x SSE + 1 x SSESF, size is 12: 1 x Double, 1 x Float. + // 5. 2 x SSE, size is 16: 2 x Double. if ((NumClasses-i) == 1) { if (Bytes == 8) { Elts.push_back(Type::DoubleTy); Bytes -= 8; + } else if (Bytes == 4) { + Elts.push_back(Type::FloatTy); + Bytes -= 4; } else assert(0 && "Not yet handled!"); } else if ((NumClasses-i) == 2) { From resistor at mac.com Tue Jun 3 13:29:48 2008 From: resistor at mac.com (Owen Anderson) Date: Tue, 03 Jun 2008 18:29:48 -0000 Subject: [llvm-commits] [llvm] r51915 - /llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp Message-ID: <200806031829.m53ITmJS022939@zion.cs.uiuc.edu> Author: resistor Date: Tue Jun 3 13:29:48 2008 New Revision: 51915 URL: http://llvm.org/viewvc/llvm-project?rev=51915&view=rev Log: LoopIndexSplit can sometimes result in cases where a block in its own domfrontier. Don't crash when we encounter one of these. Modified: llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp Modified: llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp?rev=51915&r1=51914&r2=51915&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp Tue Jun 3 13:29:48 2008 @@ -235,9 +235,12 @@ DominanceFrontier::iterator I = DF->find(DestBB); if (I != DF->end()) { DF->addBasicBlock(NewBB, I->second); - // However NewBB's frontier does not include DestBB. - DominanceFrontier::iterator NF = DF->find(NewBB); - DF->removeFromFrontier(NF, DestBB); + + if (I->second.count(DestBB)) { + // However NewBB's frontier does not include DestBB. + DominanceFrontier::iterator NF = DF->find(NewBB); + DF->removeFromFrontier(NF, DestBB); + } } else DF->addBasicBlock(NewBB, DominanceFrontier::DomSetType()); From resistor at mac.com Tue Jun 3 13:32:27 2008 From: resistor at mac.com (Owen Anderson) Date: Tue, 03 Jun 2008 18:32:27 -0000 Subject: [llvm-commits] [llvm] r51916 - /llvm/trunk/test/Transforms/LoopIndexSplit/2008-06-03-DomFrontier.ll Message-ID: <200806031832.m53IWR3A023014@zion.cs.uiuc.edu> Author: resistor Date: Tue Jun 3 13:32:27 2008 New Revision: 51916 URL: http://llvm.org/viewvc/llvm-project?rev=51916&view=rev Log: Testcase for LoopIndexSplit and DomFrontier. Added: llvm/trunk/test/Transforms/LoopIndexSplit/2008-06-03-DomFrontier.ll Added: llvm/trunk/test/Transforms/LoopIndexSplit/2008-06-03-DomFrontier.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopIndexSplit/2008-06-03-DomFrontier.ll?rev=51916&view=auto ============================================================================== --- llvm/trunk/test/Transforms/LoopIndexSplit/2008-06-03-DomFrontier.ll (added) +++ llvm/trunk/test/Transforms/LoopIndexSplit/2008-06-03-DomFrontier.ll Tue Jun 3 13:32:27 2008 @@ -0,0 +1,32 @@ +; RUN: llvm-as < %s | opt -loop-rotate -loop-unswitch -loop-index-split -instcombine -disable-output +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" +target triple = "i386-apple-darwin9" + %struct.__CFData = type opaque + %struct.__CFString = type opaque + +define %struct.__CFData* @WirelessCreatePSK(%struct.__CFString* %inPassphrase, %struct.__CFData* %inSSID) nounwind { +entry: + br label %bb52 + +bb52: ; preds = %bb142, %bb52, %entry + br i1 false, label %bb142, label %bb52 + +bb63: ; preds = %bb142, %bb131 + %t.0.reg2mem.0 = phi i32 [ %tmp133, %bb131 ], [ 0, %bb142 ] ; [#uses=2] + %tmp65 = icmp ult i32 %t.0.reg2mem.0, 16 ; [#uses=1] + br i1 %tmp65, label %bb68, label %bb89 + +bb68: ; preds = %bb63 + br label %bb131 + +bb89: ; preds = %bb63 + br label %bb131 + +bb131: ; preds = %bb89, %bb68 + %tmp133 = add i32 %t.0.reg2mem.0, 1 ; [#uses=2] + %tmp136 = icmp ult i32 %tmp133, 80 ; [#uses=1] + br i1 %tmp136, label %bb63, label %bb142 + +bb142: ; preds = %bb131, %bb52 + br i1 undef, label %bb63, label %bb52 +} From scottm at aero.org Tue Jun 3 14:13:20 2008 From: scottm at aero.org (Scott Michel) Date: Tue, 03 Jun 2008 19:13:20 -0000 Subject: [llvm-commits] [llvm] r51917 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <200806031913.m53JDKLZ024341@zion.cs.uiuc.edu> Author: pingbak Date: Tue Jun 3 14:13:20 2008 New Revision: 51917 URL: http://llvm.org/viewvc/llvm-project?rev=51917&view=rev Log: Fix spellnig error Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=51917&r1=51916&r2=51917&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Jun 3 14:13:20 2008 @@ -4447,12 +4447,11 @@ unsigned VT2 = Tmp2.getValueType(); assert(VT2 == Tmp3.getValueType() - && "PromoteOp: Operands 2 and 3 ValueTypes don't match"); - // Ensure tha NVT is the same as the operands' value types, because we - // cannot assume that TLI.getSetCCValueType() is constant. - if (NVT != VT2) - NVT = VT2; - Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3); + && "PromoteOp SELECT: Operands 2 and 3 ValueTypes don't match"); + // Ensure that the resulting node is at least the same size as the operands' + // value types, because we cannot assume that TLI.getSetCCValueType() is + // constant. + Result = DAG.getNode(ISD::SELECT, VT2, Node->getOperand(0), Tmp2, Tmp3); break; } case ISD::SELECT_CC: From dalej at apple.com Tue Jun 3 14:23:35 2008 From: dalej at apple.com (Dale Johannesen) Date: Tue, 3 Jun 2008 12:23:35 -0700 Subject: [llvm-commits] [llvm-gcc-4.2] r51723 - in /llvm-gcc-4.2/trunk/gcc: config/i386/llvm-i386-target.h config/i386/llvm-i386.cpp config/rs6000/llvm-rs6000.cpp llvm-abi.h In-Reply-To: <97A489F4-409F-47F6-9EC7-9CC3DCD7563B@apple.com> References: <200805300123.m4U1NDZl019942@zion.cs.uiuc.edu> <4B25ACA3-2667-47BE-8483-B937CEA1719F@apple.com> <983E84B7-0FC5-416B-A174-E1D5C0A50E87@apple.com> <97A489F4-409F-47F6-9EC7-9CC3DCD7563B@apple.com> Message-ID: On Jun 2, 2008, at 11:58 PM, Evan Cheng wrote: > Purely trial and error. llvm-gcc before this patch works. :-) > > Evan Revs 51722 and 51723 both work for me; it was broken after this. Do we have a way to tell what rev was in effect when the nightly tester first reported a failure? > On Jun 2, 2008, at 7:35 PM, Dale Johannesen wrote: > >> Not saying you're wrong, but why do you think it's this patch? >> >> On Jun 2, 2008, at 5:35 PM, Evan Cheng wrote: >> >>> Hi Dale, >>> >>> Looks like this patch broke 447.dealII on x86-64. Try this: >>> >>> make ENABLE_OPTIMIZED=1 TEST=nightly TARGET_FLAGS="-m64 - >>> DSPEC_CPU2000_LP64 -DSPEC_CPU_LP64" TARGET_LLCFLAGS="-relocation- >>> model=pic -disable-fp-elim" EXTRA_LLI_OPTS="-relocation-model=pic - >>> disable-fp-elim" clean Output/447.dealII.diff-llc >>> >>> Evan >>> >>> On May 29, 2008, at 6:23 PM, Dale Johannesen wrote: >>> >>>> Author: johannes >>>> Date: Thu May 29 20:23:12 2008 >>>> New Revision: 51723 >>>> >>>> URL: http://llvm.org/viewvc/llvm-project?rev=51723&view=rev >>>> Log: >>>> X86-64 ABI fix. Revert isSingleElementStructOrArray >>>> change in favor of a more general version which handles >>>> the case where there's more than one element correctly. >>>> Fixes gcc.dg/compat/struct-layout-1.exp/t003 >>>> and many more. >>>> >>>> >>>> Modified: >>>> llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h >>>> llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp >>>> llvm-gcc-4.2/trunk/gcc/config/rs6000/llvm-rs6000.cpp >>>> llvm-gcc-4.2/trunk/gcc/llvm-abi.h >>>> >>>> Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h >>>> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h?rev=51723&r1=51722&r2=51723&view=diff >>>> >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> =================================================================== >>>> --- llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h >>>> (original) >>>> +++ llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h Thu May >>>> 29 20:23:12 2008 >>>> @@ -95,17 +95,18 @@ >>>> considered as if they were the type of the data field. */ >>>> #ifndef LLVM_SHOULD_RETURN_SELT_STRUCT_AS_SCALAR >>>> #define LLVM_SHOULD_RETURN_SELT_STRUCT_AS_SCALAR(X) \ >>>> - isSingleElementStructOrArray(X, true, false, false) >>>> + isSingleElementStructOrArray(X, true, false) >>>> #endif >>>> >>>> +extern bool llvm_x86_should_pass_aggregate_in_integer_regs(tree, >>>> unsigned*); >>>> + >>>> /* LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS - Return true if >>>> this aggregate >>>> value should be passed in integer registers. This differs from >>>> the usual >>>> - handling in that x86-64 passes single-int-element unions as >>>> the type of the >>>> - field. */ >>>> -#define >>>> LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS(X) \ >>>> - >>>> (TARGET_64BIT >>>> ? \ >>>> - !isSingleElementStructOrArray((X), true, true, >>>> true) : \ >>>> - !isSingleElementStructOrArray((X), false, true, false)) >>>> + handling in that x86-64 passes 128-bit structs and unions >>>> which only >>>> + contain data in the first 64 bits, as 64-bit objects. (These >>>> can be >>>> + created by abusing __attribute__((aligned)). */ >>>> +#define LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS(X, >>>> Y) \ >>>> + llvm_x86_should_pass_aggregate_in_integer_regs((X), (Y)) >>>> >>>> extern bool llvm_x86_should_pass_vector_in_integer_regs(tree); >>>> >>>> >>>> Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp >>>> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp?rev=51723&r1=51722&r2=51723&view=diff >>>> >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> =================================================================== >>>> --- llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp (original) >>>> +++ llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp Thu May 29 >>>> 20:23:12 2008 >>>> @@ -1288,4 +1288,38 @@ >>>> return Loc; >>>> } >>>> >>>> +/// llvm_x86_should_pass_aggregate_in_integer_regs - x86-32 is >>>> same as the >>>> +/// default. x86-64 detects the case where a type is 16 bytes >>>> long but >>>> +/// only 8 of them are passed, the rest being padding (*size is >>>> set to 8 >>>> +/// to identify this case). >>>> +bool llvm_x86_should_pass_aggregate_in_integer_regs(tree type, >>>> unsigned *size) >>>> +{ >>>> + *size = 0; >>>> + if (TARGET_64BIT) { >>>> + enum x86_64_reg_class Class[MAX_CLASSES]; >>>> + enum machine_mode Mode = ix86_getNaturalModeForType(type); >>>> + int NumClasses = ix86_ClassifyArgument(Mode, type, Class, 0); >>>> + if (NumClasses == 1 && (Class[0] == X86_64_INTEGERSI_CLASS || >>>> + Class[0] == X86_64_INTEGER_CLASS)) { >>>> + /* 8 byte object, one int register */ >>>> + return true; >>>> + } >>>> + if (NumClasses == 2 && (Class[0] == X86_64_INTEGERSI_CLASS || >>>> + Class[0] == X86_64_INTEGER_CLASS)) { >>>> + if (Class[1] == X86_64_INTEGERSI_CLASS || >>>> + Class[1] == X86_64_INTEGER_CLASS) >>>> + /* 16 byte object, 2 int registers */ >>>> + return true; >>>> + if (Class[1] == X86_64_NO_CLASS) { >>>> + /* 16 byte object, only 1st register has information */ >>>> + *size = 8; >>>> + return true; >>>> + } >>>> + } >>>> + return false; >>>> + } >>>> + else >>>> + return !isSingleElementStructOrArray(type, false, true); >>>> +} >>>> + >>>> /* LLVM LOCAL end (ENTIRE FILE!) */ >>>> >>>> Modified: llvm-gcc-4.2/trunk/gcc/config/rs6000/llvm-rs6000.cpp >>>> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/rs6000/llvm-rs6000.cpp?rev=51723&r1=51722&r2=51723&view=diff >>>> >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> =================================================================== >>>> --- llvm-gcc-4.2/trunk/gcc/config/rs6000/llvm-rs6000.cpp (original) >>>> +++ llvm-gcc-4.2/trunk/gcc/config/rs6000/llvm-rs6000.cpp Thu May >>>> 29 20:23:12 2008 >>>> @@ -404,7 +404,7 @@ >>>> // some zero-length fields as well, must be passed as the field >>>> type. >>>> // Note this does not apply to long double. >>>> // This is required for ABI correctness. >>>> - tree tType = isSingleElementStructOrArray(TreeType, true, >>>> false, false); >>>> + tree tType = isSingleElementStructOrArray(TreeType, true, >>>> false); >>>> if (tType && int_size_in_bytes(tType)==Bytes && TYPE_MODE(tType)! >>>> =TFmode && >>>> (TREE_CODE(tType)!=VECTOR_TYPE || Bytes==16)) >>>> return false; >>>> @@ -437,7 +437,7 @@ >>>> // Other single-element structs may be passed this way as well, but >>>> // only if the type size matches the element's type size (structs >>>> that >>>> // violate this can be created with __aligned__). >>>> - tree tType = isSingleElementStructOrArray(TreeType, true, >>>> false, false); >>>> + tree tType = isSingleElementStructOrArray(TreeType, true, >>>> false); >>>> if (tType && int_size_in_bytes(tType)==SrcSize && >>>> TYPE_MODE(tType)!=TFmode && >>>> (TREE_CODE(tType)!=VECTOR_TYPE || SrcSize==16)) { >>>> Elts.push_back(ConvertType(tType)); >>>> >>>> Modified: llvm-gcc-4.2/trunk/gcc/llvm-abi.h >>>> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-abi.h?rev=51723&r1=51722&r2=51723&view=diff >>>> >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> = >>>> =================================================================== >>>> --- llvm-gcc-4.2/trunk/gcc/llvm-abi.h (original) >>>> +++ llvm-gcc-4.2/trunk/gcc/llvm-abi.h Thu May 29 20:23:12 2008 >>>> @@ -138,21 +138,17 @@ >>>> /// rejectFatBitField, and the single element is a bitfield of a >>>> type that's >>>> /// bigger than the struct, return null anyway. >>>> static tree isSingleElementStructOrArray(tree type, bool >>>> ignoreZeroLength, >>>> - bool rejectFatBitfield, >>>> - bool acceptUnions) { >>>> + bool rejectFatBitfield) { >>>> // Scalars are good. >>>> if (!isAggregateTreeType(type)) return type; >>>> >>>> tree FoundField = 0; >>>> switch (TREE_CODE(type)) { >>>> case QUAL_UNION_TYPE: >>>> + case UNION_TYPE: // Single element unions don't count. >>>> case COMPLEX_TYPE: // Complex values are like 2-element records. >>>> default: >>>> return 0; >>>> - case UNION_TYPE: // Single element unions don't count. >>>> - if (!acceptUnions) >>>> - return 0; >>>> - // fall through >>>> case RECORD_TYPE: >>>> // If this record has variable length, reject it. >>>> if (TREE_CODE(TYPE_SIZE(type)) != INTEGER_CST) >>>> @@ -178,15 +174,13 @@ >>>> } >>>> } >>>> return FoundField ? isSingleElementStructOrArray(FoundField, >>>> - >>>> ignoreZeroLength, false, >>>> - false) >>>> + >>>> ignoreZeroLength, false) >>>> : 0; >>>> case ARRAY_TYPE: >>>> const ArrayType *Ty = dyn_cast(ConvertType(type)); >>>> if (!Ty || Ty->getNumElements() != 1) >>>> return 0; >>>> - return isSingleElementStructOrArray(TREE_TYPE(type), false, >>>> false, >>>> - false); >>>> + return isSingleElementStructOrArray(TREE_TYPE(type), false, >>>> false); >>>> } >>>> } >>>> >>>> @@ -283,8 +277,8 @@ >>>> // single element is a bitfield of a type bigger than the struct; >>>> the code >>>> // for field-by-field struct passing does not handle this one >>>> right. >>>> #ifndef LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS >>>> -#define LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS(X) \ >>>> - !isSingleElementStructOrArray(X, false, true, false) >>>> +#define LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS(X, Y) \ >>>> + !isSingleElementStructOrArray((X), false, true) >>>> #endif >>>> >>>> // LLVM_SHOULD_RETURN_SELT_STRUCT_AS_SCALAR - Return a TYPE tree >>>> if this single >>>> @@ -295,7 +289,7 @@ >>>> // by abusing the __aligned__ attribute.) >>>> #ifndef LLVM_SHOULD_RETURN_SELT_STRUCT_AS_SCALAR >>>> #define LLVM_SHOULD_RETURN_SELT_STRUCT_AS_SCALAR(X) \ >>>> - isSingleElementStructOrArray(X, false, false, false) >>>> + isSingleElementStructOrArray(X, false, false) >>>> #endif >>>> >>>> // LLVM_SHOULD_RETURN_VECTOR_AS_SCALAR - Return a TYPE tree if >>>> this vector type >>>> @@ -408,6 +402,7 @@ >>>> /// their fields. >>>> void HandleArgument(tree type, std::vector >>>> &ScalarElts, >>>> ParameterAttributes *Attributes = NULL) { >>>> + unsigned Size = 0; >>>> const Type *Ty = ConvertType(type); >>>> // Figure out if this field is zero bits wide, e.g. {} or [0 x >>>> int]. Do >>>> // not include variable sized fields here. >>>> @@ -418,7 +413,7 @@ >>>> ScalarElts.push_back(PtrTy); >>>> } else if (Ty->getTypeID()==Type::VectorTyID) { >>>> if (LLVM_SHOULD_PASS_VECTOR_IN_INTEGER_REGS(type)) { >>>> - PassInIntegerRegisters(type, Ty, ScalarElts); >>>> + PassInIntegerRegisters(type, Ty, ScalarElts, 0); >>>> } else { >>>> C.HandleScalarArgument(Ty, type); >>>> ScalarElts.push_back(Ty); >>>> @@ -444,8 +439,8 @@ >>>> *Attributes |= >>>> >>>> ParamAttr::constructAlignmentFromInt(LLVM_BYVAL_ALIGNMENT(type)); >>>> } >>>> - } else if (LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS(type)) { >>>> - PassInIntegerRegisters(type, Ty, ScalarElts); >>>> + } else if (LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS(type, >>>> &Size)) { >>>> + PassInIntegerRegisters(type, Ty, ScalarElts, Size); >>>> } else if (isZeroSizedStructOrUnion(type)) { >>>> // Zero sized struct or union, just drop it! >>>> ; >>>> @@ -526,10 +521,15 @@ >>>> >>>> /// PassInIntegerRegisters - Given an aggregate value that should >>>> be passed in >>>> /// integer registers, convert it to a structure containing ints >>>> and pass all >>>> - /// of the struct elements in. >>>> + /// of the struct elements in. If Size is set we pass only >>>> that many bytes. >>>> void PassInIntegerRegisters(tree type, const Type *Ty, >>>> - std::vector >>>> &ScalarElts) { >>>> - unsigned Size = TREE_INT_CST_LOW(TYPE_SIZE(type))/8; >>>> + std::vector >>>> &ScalarElts, >>>> + unsigned origSize) { >>>> + unsigned Size; >>>> + if (origSize) >>>> + Size = origSize; >>>> + else >>>> + Size = TREE_INT_CST_LOW(TYPE_SIZE(type))/8; >>>> >>>> // FIXME: We should preserve all aggregate value alignment >>>> information. >>>> // Work around to preserve some aggregate value alignment >>>> information: >>>> @@ -568,7 +568,7 @@ >>>> Elts.push_back(Type::Int8Ty); >>>> Size -= 1; >>>> } >>>> - assert(Size == 0 && "Didn't cover value?"); >>>> + assert((origSize || Size == 0) && "Didn't cover value?"); >>>> const StructType *STy = StructType::get(Elts, false); >>>> >>>> unsigned i = 0; >>>> >>>> >>>> _______________________________________________ >>>> llvm-commits mailing list >>>> llvm-commits at cs.uiuc.edu >>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>> >> > From isanbard at gmail.com Tue Jun 3 14:52:45 2008 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 3 Jun 2008 12:52:45 -0700 Subject: [llvm-commits] [llvm-gcc-4.2] r51866 - /llvm-gcc-4.2/trunk/gcc/llvm-types.cpp In-Reply-To: References: <200806021556.m52FunYg008136@zion.cs.uiuc.edu> Message-ID: <16e5fdf90806031252p41168fffv17fefd3fb547b9d5@mail.gmail.com> Please go ahead and revert this patch until Duncan can fix it. Thanks! -bw On Tue, Jun 3, 2008 at 10:57 AM, Dale Johannesen wrote: > This patch breaks FrontendC/2008-01-28-UnionSize.c and FrontendC/ > 2007-09-28-PackedUnionMember.c on Darwin x86-32. > > FAIL: /Volumes/MacOS9/gcc/llvm/test/FrontendC/2007-09-28- > PackedUnionMember.c > Failed with exit(1) at line 1 > while running: /usr/local/bin/llvm-gcc -emit-llvm /Volumes/MacOS9/gcc/ > llvm/test/FrontendC/2007-09-28-PackedUnionMember.c -S -o - > Assertion failed: ((!TYPE_SIZE(Tr) || !Ty->isSized() || ! > isInt64(TYPE_SIZE(Tr), true) || getInt64(TYPE_SIZE(Tr), true) == > getTargetData().getABITypeSizeInBits(Ty)) && "LLVM type size doesn't > match GCC type size!"), function llvm_set_type, file ../../llvm- > gcc-4.2/gcc/llvm-types.cpp, line 84. > /Volumes/MacOS9/gcc/llvm/test/FrontendC/2007-09-28- > PackedUnionMember.c: In function 'hndlr': > > It's odd that the nightly testers aren't showing this. I suspect they > aren't rebuilding llvm-gcc every night. > > On Jun 2, 2008, at 8:56 AM, Duncan Sands wrote: > >> Author: baldrick >> Date: Mon Jun 2 10:56:49 2008 >> New Revision: 51866 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=51866&view=rev >> Log: >> Fix 2003-10-09-UnionInitializerBug.c on x86-64. >> The problem was that in ConvertUNION if the >> new field was less aligned than a previous one >> but was also the biggest field seen so far then >> it was selected. But the most aligned field is >> supposed to always be selected. This caused a >> crash in ConvertStructFieldInitializerToType >> which relies on initializers not being more >> aligned than the LLVM type. In the long run >> I think ConvertStructFieldInitializerToType >> should be modified to not care about the >> alignment. >> >> Modified: >> llvm-gcc-4.2/trunk/gcc/llvm-types.cpp >> >> Modified: llvm-gcc-4.2/trunk/gcc/llvm-types.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-types.cpp?rev=51866&r1=51865&r2=51866&view=diff >> >> = >> = >> = >> = >> = >> = >> = >> = >> ====================================================================== >> --- llvm-gcc-4.2/trunk/gcc/llvm-types.cpp (original) >> +++ llvm-gcc-4.2/trunk/gcc/llvm-types.cpp Mon Jun 2 10:56:49 2008 >> @@ -2179,7 +2179,7 @@ >> const TargetData &TD = getTargetData(); >> const Type *UnionTy = 0; >> tree GccUnionTy = 0; >> - unsigned MaxSize = 0, MaxAlign = 0; >> + unsigned MaxAlignSize = 0, MaxAlign = 0; >> for (tree Field = TYPE_FIELDS(type); Field; Field = >> TREE_CHAIN(Field)) { >> if (TREE_CODE(Field) != FIELD_DECL) continue; >> // assert(getFieldOffsetInBits(Field) == 0 && "Union with non- >> zero offset?"); >> @@ -2233,29 +2233,27 @@ >> const Type *TheTy = ConvertType(TheGccTy); >> unsigned Size = TD.getABITypeSize(TheTy); >> unsigned Align = TD.getABITypeAlignment(TheTy); >> - >> + >> adjustPaddingElement(GccUnionTy, TheGccTy); >> >> - // Select TheTy as union type if it meets one of the following >> criteria >> - // 1) UnionTy is 0 >> - // 2) TheTy alignment is more then UnionTy >> - // 3) TheTy size is greater than UnionTy size and TheTy >> alignment is >> - // equal to UnionTy >> - // 4) TheTy size is greater then UnionTy size and TheTy is packed >> - bool useTheTy = false; >> + // Select TheTy as union type if it is more aligned than any >> other. If more >> + // than one field achieves the maximum alignment then choose >> the biggest. >> + bool useTheTy; >> if (UnionTy == 0) >> useTheTy = true; >> + else if (Align < MaxAlign) >> + useTheTy = false; >> else if (Align > MaxAlign) >> useTheTy = true; >> - else if (MaxAlign == Align && Size > MaxSize) >> - useTheTy = true; >> - else if (Size > MaxSize) >> + else if (Size > MaxAlignSize) >> useTheTy = true; >> + else >> + useTheTy = false; >> >> if (useTheTy) { >> UnionTy = TheTy; >> GccUnionTy = TheGccTy; >> - MaxSize = MAX(MaxSize, Size); >> + MaxAlignSize = Size; >> MaxAlign = Align; >> } >> >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From dpatel at apple.com Tue Jun 3 15:15:57 2008 From: dpatel at apple.com (Devang Patel) Date: Tue, 3 Jun 2008 13:15:57 -0700 Subject: [llvm-commits] [llvm-gcc-4.2] r51723 - in /llvm-gcc-4.2/trunk/gcc: config/i386/llvm-i386-target.h config/i386/llvm-i386.cpp config/rs6000/llvm-rs6000.cpp llvm-abi.h In-Reply-To: References: <200805300123.m4U1NDZl019942@zion.cs.uiuc.edu> <4B25ACA3-2667-47BE-8483-B937CEA1719F@apple.com> <983E84B7-0FC5-416B-A174-E1D5C0A50E87@apple.com> <97A489F4-409F-47F6-9EC7-9CC3DCD7563B@apple.com> Message-ID: <3ACA7950-FD16-4CAC-9D0C-F403E63CC2E5@apple.com> On Jun 3, 2008, at 12:23 PM, Dale Johannesen wrote: > Do we have a way to tell what rev was in effect when the nightly > tester first reported a failure? Nope, http://llvm.org/bugs/show_bug.cgi?id=1587 Hopefully one of the GSoC project will address this. - Devang From dpatel at apple.com Tue Jun 3 15:46:04 2008 From: dpatel at apple.com (Devang Patel) Date: Tue, 3 Jun 2008 13:46:04 -0700 Subject: [llvm-commits] value range analysis based on scalar-evolutions In-Reply-To: <48436EF1.8020203@mxc.ca> References: <48436EF1.8020203@mxc.ca> Message-ID: <36D98FFC-7C90-448F-AA77-F84CE3F71013@apple.com> On Jun 1, 2008, at 8:54 PM, Nick Lewycky wrote: > I've implemented an analysis pass that uses SCEV to determine value > ranges of integer-typed registers. > > Currently it maintains a map of Value* to ConstantRange*, which is > rather inelegant. I was thinking we could have one analysis which > would do that and others that would update the central analysis. > > I also implemented an optz'n pass based on it, but it hardly > optimized anything and as such is not included in this patch. > > Please comment! +static RegisterPass X("loopvr", "Loop Value Ranges"); You want to register this as an analysis pass and cfe-only pass. +static SCEVHandle getTruncateOrZeroExtend(const SCEVHandle &V, const Type *Ty, + ScalarEvolution &SE) { Why not move this into ScalarEvolution.h ? + APInt Spread_X = X.getSetSize(), Spread_Y = Y.getSetSize(); + APInt NewLower = X.getLower() + Y.getLower(), + NewUpper = X.getUpper() + Y.getUpper() - 1; nit-pick. I'd prefer to write this as APInt NewLower = ..; APInt NewUpper = ..; +bool LoopVR::runOnFunction(Function &F) { Is there a reason to not make this a LoopPass ? + for (LoopInfo::iterator I = LI.begin(), E = LI.end(); I != E; ++I) { + Loop *L = *I; ... + Loop *LL = LI.getLoopFor(*BI); + if (LL->isLoopInvariant(II)) continue; Do you really want to check LL->isLoopInvariant(II) instead of L- >isLoopInvariant(II) here ? - Devang From baldrick at free.fr Tue Jun 3 15:51:49 2008 From: baldrick at free.fr (Duncan Sands) Date: Tue, 3 Jun 2008 22:51:49 +0200 Subject: [llvm-commits] [llvm-gcc-4.2] r51866 - /llvm-gcc-4.2/trunk/gcc/llvm-types.cpp In-Reply-To: References: <200806021556.m52FunYg008136@zion.cs.uiuc.edu> Message-ID: <200806032251.50415.baldrick@free.fr> Hi Dale, > This patch breaks FrontendC/2008-01-28-UnionSize.c and FrontendC/ > 2007-09-28-PackedUnionMember.c on Darwin x86-32. sorry about that, I don't understand why I didn't see it when testing because I sure see it now (x86-64)! The problem is that gcc says that this type union { struct opaque1 *f3; struct opaque2 *f4; struct { struct opaque3 *f5; unsigned short f6; } f7; }; is 16 byte aligned but has a size of 10 bytes. I thought gcc sizes were always a multiple of the alignment? Anyway, ConvertUNION chooses to represent this using "struct opaque1 *" (the reason being that f7 is packed, dunno why, so has alignment 1, which is less than the alignment of the pointers). It then observes that the size (8 bytes) is less than the gcc size (10 bytes) so tries to pad by adding 2 bytes, resulting in { opaque *, [2 x i8] } This actually has an ABI size of 16 bytes - it is 10 bytes wide but is 8 bytes aligned -> 16 bytes. This is not the same as the gcc type size. I'm rather taken aback that gcc is producing type sizes that are not a multiple of the alignment. I also don't understand why the alignment is 16. I guess most of these oddities are related to the "#pragma pack(push, 2)" on the first line of 2007-09-28-PackedUnionMember.c. What does that mean? And if things are packed, shouldn't the union be converted to a packed type or something? Ciao, Duncan. From dalej at apple.com Tue Jun 3 16:28:56 2008 From: dalej at apple.com (Dale Johannesen) Date: Tue, 3 Jun 2008 14:28:56 -0700 Subject: [llvm-commits] [llvm-gcc-4.2] r51866 - /llvm-gcc-4.2/trunk/gcc/llvm-types.cpp In-Reply-To: <200806032251.50415.baldrick@free.fr> References: <200806021556.m52FunYg008136@zion.cs.uiuc.edu> <200806032251.50415.baldrick@free.fr> Message-ID: <528981CF-4D08-4B73-8E8A-55544FCA9090@apple.com> On Jun 3, 2008, at 1:51 PM, Duncan Sands wrote: > Hi Dale, > >> This patch breaks FrontendC/2008-01-28-UnionSize.c and FrontendC/ >> 2007-09-28-PackedUnionMember.c on Darwin x86-32. > > sorry about that, I don't understand why I didn't see it when testing > because I sure see it now (x86-64)! The problem is that gcc says that > this type > > union { > struct opaque1 *f3; > struct opaque2 *f4; > struct { > struct opaque3 *f5; > unsigned short f6; > } f7; > }; > > is 16 byte aligned but has a size of 10 bytes. I thought gcc sizes > were always a multiple of the alignment? Anyway, ConvertUNION chooses > to represent this using "struct opaque1 *" (the reason being that f7 > is packed, dunno why, so has alignment 1, which is less than the > alignment > of the pointers). It then observes that the size (8 bytes) is less > than > the gcc size (10 bytes) so tries to pad by adding 2 bytes, resulting > in > { opaque *, [2 x i8] } > This actually has an ABI size of 16 bytes - it is 10 bytes wide but is > 8 bytes aligned -> 16 bytes. This is not the same as the gcc type > size. > > I'm rather taken aback that gcc is producing type sizes that are not a > multiple of the alignment. I also don't understand why the alignment > is 16. > > I guess most of these oddities are related to the "#pragma > pack(push, 2)" > on the first line of 2007-09-28-PackedUnionMember.c. What does that > mean? > And if things are packed, shouldn't the union be converted to a > packed type > or something? The pragma means all struct/unions encountered thereafter (until the next such pragma) have alignment 2 and max alignment of any field is 2. So struct { char c; int x; }; is size 6, alignment 2. So the size and alignment for that union are 10 and 2, and if you compile it with gcc that's what they are. I'm not sure how that's represented inside gcc, probably there's another field somewhere you need to look at. From dalej at apple.com Tue Jun 3 17:15:55 2008 From: dalej at apple.com (Dale Johannesen) Date: Tue, 3 Jun 2008 15:15:55 -0700 Subject: [llvm-commits] [llvm-gcc-4.2] r51723 - in /llvm-gcc-4.2/trunk/gcc: config/i386/llvm-i386-target.h config/i386/llvm-i386.cpp config/rs6000/llvm-rs6000.cpp llvm-abi.h In-Reply-To: References: <200805300123.m4U1NDZl019942@zion.cs.uiuc.edu> <4B25ACA3-2667-47BE-8483-B937CEA1719F@apple.com> <983E84B7-0FC5-416B-A174-E1D5C0A50E87@apple.com> <97A489F4-409F-47F6-9EC7-9CC3DCD7563B@apple.com> Message-ID: <7B9EDBC2-D0D8-4258-BD1F-7BF8F914ED6C@apple.com> On Jun 3, 2008, at 12:23 PM, Dale Johannesen wrote: > On Jun 2, 2008, at 11:58 PM, Evan Cheng wrote: > >> Purely trial and error. llvm-gcc before this patch works. :-) >> >> Evan > > Revs 51722 and 51723 both work for me; it was broken after this. It's 51799, so that is me. > Do we have a way to tell what rev was in effect when the nightly > tester first reported a failure? > >> On Jun 2, 2008, at 7:35 PM, Dale Johannesen wrote: >> >>> Not saying you're wrong, but why do you think it's this patch? >>> >>> On Jun 2, 2008, at 5:35 PM, Evan Cheng wrote: >>> >>>> Hi Dale, >>>> >>>> Looks like this patch broke 447.dealII on x86-64. Try this: >>>> >>>> make ENABLE_OPTIMIZED=1 TEST=nightly TARGET_FLAGS="-m64 - >>>> DSPEC_CPU2000_LP64 -DSPEC_CPU_LP64" TARGET_LLCFLAGS="-relocation- >>>> model=pic -disable-fp-elim" EXTRA_LLI_OPTS="-relocation-model=pic >>>> -disable-fp-elim" clean Output/447.dealII.diff-llc >>>> >>>> Evan >>>> >>>> On May 29, 2008, at 6:23 PM, Dale Johannesen wrote: >>>> >>>>> Author: johannes >>>>> Date: Thu May 29 20:23:12 2008 >>>>> New Revision: 51723 >>>>> >>>>> URL: http://llvm.org/viewvc/llvm-project?rev=51723&view=rev >>>>> Log: >>>>> X86-64 ABI fix. Revert isSingleElementStructOrArray >>>>> change in favor of a more general version which handles >>>>> the case where there's more than one element correctly. >>>>> Fixes gcc.dg/compat/struct-layout-1.exp/t003 >>>>> and many more. >>>>> >>>>> >>>>> Modified: >>>>> llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h >>>>> llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp >>>>> llvm-gcc-4.2/trunk/gcc/config/rs6000/llvm-rs6000.cpp >>>>> llvm-gcc-4.2/trunk/gcc/llvm-abi.h >>>>> >>>>> Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h >>>>> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h?rev=51723&r1=51722&r2=51723&view=diff >>>>> >>>>> = >>>>> = >>>>> = >>>>> = >>>>> = >>>>> = >>>>> = >>>>> = >>>>> = >>>>> = >>>>> = >>>>> = >>>>> ================================================================== >>>>> --- llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h >>>>> (original) >>>>> +++ llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h Thu >>>>> May 29 20:23:12 2008 >>>>> @@ -95,17 +95,18 @@ >>>>> considered as if they were the type of the data field. */ >>>>> #ifndef LLVM_SHOULD_RETURN_SELT_STRUCT_AS_SCALAR >>>>> #define LLVM_SHOULD_RETURN_SELT_STRUCT_AS_SCALAR(X) \ >>>>> - isSingleElementStructOrArray(X, true, false, false) >>>>> + isSingleElementStructOrArray(X, true, false) >>>>> #endif >>>>> >>>>> +extern bool >>>>> llvm_x86_should_pass_aggregate_in_integer_regs(tree, unsigned*); >>>>> + >>>>> /* LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS - Return true if >>>>> this aggregate >>>>> value should be passed in integer registers. This differs from >>>>> the usual >>>>> - handling in that x86-64 passes single-int-element unions as >>>>> the type of the >>>>> - field. */ >>>>> -#define >>>>> LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS(X) \ >>>>> - >>>>> (TARGET_64BIT >>>>> ? \ >>>>> - !isSingleElementStructOrArray((X), true, true, >>>>> true) : \ >>>>> - !isSingleElementStructOrArray((X), false, true, false)) >>>>> + handling in that x86-64 passes 128-bit structs and unions >>>>> which only >>>>> + contain data in the first 64 bits, as 64-bit objects. >>>>> (These can be >>>>> + created by abusing __attribute__((aligned)). */ >>>>> +#define LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS(X, >>>>> Y) \ >>>>> + llvm_x86_should_pass_aggregate_in_integer_regs((X), (Y)) >>>>> >>>>> extern bool llvm_x86_should_pass_vector_in_integer_regs(tree); >>>>> >>>>> >>>>> Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp >>>>> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp?rev=51723&r1=51722&r2=51723&view=diff >>>>> >>>>> = >>>>> = >>>>> = >>>>> = >>>>> = >>>>> = >>>>> = >>>>> = >>>>> = >>>>> = >>>>> = >>>>> = >>>>> ================================================================== >>>>> --- llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp (original) >>>>> +++ llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp Thu May 29 >>>>> 20:23:12 2008 >>>>> @@ -1288,4 +1288,38 @@ >>>>> return Loc; >>>>> } >>>>> >>>>> +/// llvm_x86_should_pass_aggregate_in_integer_regs - x86-32 is >>>>> same as the >>>>> +/// default. x86-64 detects the case where a type is 16 bytes >>>>> long but >>>>> +/// only 8 of them are passed, the rest being padding (*size is >>>>> set to 8 >>>>> +/// to identify this case). >>>>> +bool llvm_x86_should_pass_aggregate_in_integer_regs(tree type, >>>>> unsigned *size) >>>>> +{ >>>>> + *size = 0; >>>>> + if (TARGET_64BIT) { >>>>> + enum x86_64_reg_class Class[MAX_CLASSES]; >>>>> + enum machine_mode Mode = ix86_getNaturalModeForType(type); >>>>> + int NumClasses = ix86_ClassifyArgument(Mode, type, Class, 0); >>>>> + if (NumClasses == 1 && (Class[0] == X86_64_INTEGERSI_CLASS || >>>>> + Class[0] == X86_64_INTEGER_CLASS)) { >>>>> + /* 8 byte object, one int register */ >>>>> + return true; >>>>> + } >>>>> + if (NumClasses == 2 && (Class[0] == X86_64_INTEGERSI_CLASS || >>>>> + Class[0] == X86_64_INTEGER_CLASS)) { >>>>> + if (Class[1] == X86_64_INTEGERSI_CLASS || >>>>> + Class[1] == X86_64_INTEGER_CLASS) >>>>> + /* 16 byte object, 2 int registers */ >>>>> + return true; >>>>> + if (Class[1] == X86_64_NO_CLASS) { >>>>> + /* 16 byte object, only 1st register has information */ >>>>> + *size = 8; >>>>> + return true; >>>>> + } >>>>> + } >>>>> + return false; >>>>> + } >>>>> + else >>>>> + return !isSingleElementStructOrArray(type, false, true); >>>>> +} >>>>> + >>>>> /* LLVM LOCAL end (ENTIRE FILE!) */ >>>>> >>>>> Modified: llvm-gcc-4.2/trunk/gcc/config/rs6000/llvm-rs6000.cpp >>>>> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/rs6000/llvm-rs6000.cpp?rev=51723&r1=51722&r2=51723&view=diff >>>>> >>>>> = >>>>> = >>>>> = >>>>> = >>>>> = >>>>> = >>>>> = >>>>> = >>>>> = >>>>> = >>>>> = >>>>> = >>>>> ================================================================== >>>>> --- llvm-gcc-4.2/trunk/gcc/config/rs6000/llvm-rs6000.cpp >>>>> (original) >>>>> +++ llvm-gcc-4.2/trunk/gcc/config/rs6000/llvm-rs6000.cpp Thu May >>>>> 29 20:23:12 2008 >>>>> @@ -404,7 +404,7 @@ >>>>> // some zero-length fields as well, must be passed as the field >>>>> type. >>>>> // Note this does not apply to long double. >>>>> // This is required for ABI correctness. >>>>> - tree tType = isSingleElementStructOrArray(TreeType, true, >>>>> false, false); >>>>> + tree tType = isSingleElementStructOrArray(TreeType, true, >>>>> false); >>>>> if (tType && int_size_in_bytes(tType)==Bytes && TYPE_MODE(tType)! >>>>> =TFmode && >>>>> (TREE_CODE(tType)!=VECTOR_TYPE || Bytes==16)) >>>>> return false; >>>>> @@ -437,7 +437,7 @@ >>>>> // Other single-element structs may be passed this way as well, >>>>> but >>>>> // only if the type size matches the element's type size >>>>> (structs that >>>>> // violate this can be created with __aligned__). >>>>> - tree tType = isSingleElementStructOrArray(TreeType, true, >>>>> false, false); >>>>> + tree tType = isSingleElementStructOrArray(TreeType, true, >>>>> false); >>>>> if (tType && int_size_in_bytes(tType)==SrcSize && >>>>> TYPE_MODE(tType)!=TFmode && >>>>> (TREE_CODE(tType)!=VECTOR_TYPE || SrcSize==16)) { >>>>> Elts.push_back(ConvertType(tType)); >>>>> >>>>> Modified: llvm-gcc-4.2/trunk/gcc/llvm-abi.h >>>>> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-abi.h?rev=51723&r1=51722&r2=51723&view=diff >>>>> >>>>> = >>>>> = >>>>> = >>>>> = >>>>> = >>>>> = >>>>> = >>>>> = >>>>> = >>>>> = >>>>> = >>>>> = >>>>> ================================================================== >>>>> --- llvm-gcc-4.2/trunk/gcc/llvm-abi.h (original) >>>>> +++ llvm-gcc-4.2/trunk/gcc/llvm-abi.h Thu May 29 20:23:12 2008 >>>>> @@ -138,21 +138,17 @@ >>>>> /// rejectFatBitField, and the single element is a bitfield of a >>>>> type that's >>>>> /// bigger than the struct, return null anyway. >>>>> static tree isSingleElementStructOrArray(tree type, bool >>>>> ignoreZeroLength, >>>>> - bool rejectFatBitfield, >>>>> - bool acceptUnions) { >>>>> + bool >>>>> rejectFatBitfield) { >>>>> // Scalars are good. >>>>> if (!isAggregateTreeType(type)) return type; >>>>> >>>>> tree FoundField = 0; >>>>> switch (TREE_CODE(type)) { >>>>> case QUAL_UNION_TYPE: >>>>> + case UNION_TYPE: // Single element unions don't count. >>>>> case COMPLEX_TYPE: // Complex values are like 2-element records. >>>>> default: >>>>> return 0; >>>>> - case UNION_TYPE: // Single element unions don't count. >>>>> - if (!acceptUnions) >>>>> - return 0; >>>>> - // fall through >>>>> case RECORD_TYPE: >>>>> // If this record has variable length, reject it. >>>>> if (TREE_CODE(TYPE_SIZE(type)) != INTEGER_CST) >>>>> @@ -178,15 +174,13 @@ >>>>> } >>>>> } >>>>> return FoundField ? isSingleElementStructOrArray(FoundField, >>>>> - >>>>> ignoreZeroLength, false, >>>>> - false) >>>>> + >>>>> ignoreZeroLength, false) >>>>> : 0; >>>>> case ARRAY_TYPE: >>>>> const ArrayType *Ty = dyn_cast(ConvertType(type)); >>>>> if (!Ty || Ty->getNumElements() != 1) >>>>> return 0; >>>>> - return isSingleElementStructOrArray(TREE_TYPE(type), false, >>>>> false, >>>>> - false); >>>>> + return isSingleElementStructOrArray(TREE_TYPE(type), false, >>>>> false); >>>>> } >>>>> } >>>>> >>>>> @@ -283,8 +277,8 @@ >>>>> // single element is a bitfield of a type bigger than the >>>>> struct; the code >>>>> // for field-by-field struct passing does not handle this one >>>>> right. >>>>> #ifndef LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS >>>>> -#define LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS(X) \ >>>>> - !isSingleElementStructOrArray(X, false, true, false) >>>>> +#define LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS(X, Y) \ >>>>> + !isSingleElementStructOrArray((X), false, true) >>>>> #endif >>>>> >>>>> // LLVM_SHOULD_RETURN_SELT_STRUCT_AS_SCALAR - Return a TYPE tree >>>>> if this single >>>>> @@ -295,7 +289,7 @@ >>>>> // by abusing the __aligned__ attribute.) >>>>> #ifndef LLVM_SHOULD_RETURN_SELT_STRUCT_AS_SCALAR >>>>> #define LLVM_SHOULD_RETURN_SELT_STRUCT_AS_SCALAR(X) \ >>>>> - isSingleElementStructOrArray(X, false, false, false) >>>>> + isSingleElementStructOrArray(X, false, false) >>>>> #endif >>>>> >>>>> // LLVM_SHOULD_RETURN_VECTOR_AS_SCALAR - Return a TYPE tree if >>>>> this vector type >>>>> @@ -408,6 +402,7 @@ >>>>> /// their fields. >>>>> void HandleArgument(tree type, std::vector >>>>> &ScalarElts, >>>>> ParameterAttributes *Attributes = NULL) { >>>>> + unsigned Size = 0; >>>>> const Type *Ty = ConvertType(type); >>>>> // Figure out if this field is zero bits wide, e.g. {} or [0 x >>>>> int]. Do >>>>> // not include variable sized fields here. >>>>> @@ -418,7 +413,7 @@ >>>>> ScalarElts.push_back(PtrTy); >>>>> } else if (Ty->getTypeID()==Type::VectorTyID) { >>>>> if (LLVM_SHOULD_PASS_VECTOR_IN_INTEGER_REGS(type)) { >>>>> - PassInIntegerRegisters(type, Ty, ScalarElts); >>>>> + PassInIntegerRegisters(type, Ty, ScalarElts, 0); >>>>> } else { >>>>> C.HandleScalarArgument(Ty, type); >>>>> ScalarElts.push_back(Ty); >>>>> @@ -444,8 +439,8 @@ >>>>> *Attributes |= >>>>> >>>>> ParamAttr::constructAlignmentFromInt(LLVM_BYVAL_ALIGNMENT(type)); >>>>> } >>>>> - } else if >>>>> (LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS(type)) { >>>>> - PassInIntegerRegisters(type, Ty, ScalarElts); >>>>> + } else if (LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS(type, >>>>> &Size)) { >>>>> + PassInIntegerRegisters(type, Ty, ScalarElts, Size); >>>>> } else if (isZeroSizedStructOrUnion(type)) { >>>>> // Zero sized struct or union, just drop it! >>>>> ; >>>>> @@ -526,10 +521,15 @@ >>>>> >>>>> /// PassInIntegerRegisters - Given an aggregate value that >>>>> should be passed in >>>>> /// integer registers, convert it to a structure containing ints >>>>> and pass all >>>>> - /// of the struct elements in. >>>>> + /// of the struct elements in. If Size is set we pass only >>>>> that many bytes. >>>>> void PassInIntegerRegisters(tree type, const Type *Ty, >>>>> - std::vector >>>>> &ScalarElts) { >>>>> - unsigned Size = TREE_INT_CST_LOW(TYPE_SIZE(type))/8; >>>>> + std::vector >>>>> &ScalarElts, >>>>> + unsigned origSize) { >>>>> + unsigned Size; >>>>> + if (origSize) >>>>> + Size = origSize; >>>>> + else >>>>> + Size = TREE_INT_CST_LOW(TYPE_SIZE(type))/8; >>>>> >>>>> // FIXME: We should preserve all aggregate value alignment >>>>> information. >>>>> // Work around to preserve some aggregate value alignment >>>>> information: >>>>> @@ -568,7 +568,7 @@ >>>>> Elts.push_back(Type::Int8Ty); >>>>> Size -= 1; >>>>> } >>>>> - assert(Size == 0 && "Didn't cover value?"); >>>>> + assert((origSize || Size == 0) && "Didn't cover value?"); >>>>> const StructType *STy = StructType::get(Elts, false); >>>>> >>>>> unsigned i = 0; >>>>> >>>>> >>>>> _______________________________________________ >>>>> llvm-commits mailing list >>>>> llvm-commits at cs.uiuc.edu >>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>>> >>> >> > From evan.cheng at apple.com Tue Jun 3 19:14:35 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 3 Jun 2008 17:14:35 -0700 Subject: [llvm-commits] [llvm-gcc-4.2] r51723 - in /llvm-gcc-4.2/trunk/gcc: config/i386/llvm-i386-target.h config/i386/llvm-i386.cpp config/rs6000/llvm-rs6000.cpp llvm-abi.h In-Reply-To: <7B9EDBC2-D0D8-4258-BD1F-7BF8F914ED6C@apple.com> References: <200805300123.m4U1NDZl019942@zion.cs.uiuc.edu> <4B25ACA3-2667-47BE-8483-B937CEA1719F@apple.com> <983E84B7-0FC5-416B-A174-E1D5C0A50E87@apple.com> <97A489F4-409F-47F6-9EC7-9CC3DCD7563B@apple.com> <7B9EDBC2-D0D8-4258-BD1F-7BF8F914ED6C@apple.com> Message-ID: <2A9725F3-E438-4037-A713-B9C295889A69@apple.com> On Jun 3, 2008, at 3:15 PM, Dale Johannesen wrote: > On Jun 3, 2008, at 12:23 PM, Dale Johannesen wrote: >> On Jun 2, 2008, at 11:58 PM, Evan Cheng wrote: >> >>> Purely trial and error. llvm-gcc before this patch works. :-) >>> >>> Evan >> >> Revs 51722 and 51723 both work for me; it was broken after this. > > It's 51799, so that is me. Close enough. :-) Thanks for tracking it down. Evan > > >> Do we have a way to tell what rev was in effect when the nightly >> tester first reported a failure? >> >>> On Jun 2, 2008, at 7:35 PM, Dale Johannesen wrote: >>> >>>> Not saying you're wrong, but why do you think it's this patch? >>>> >>>> On Jun 2, 2008, at 5:35 PM, Evan Cheng wrote: >>>> >>>>> Hi Dale, >>>>> >>>>> Looks like this patch broke 447.dealII on x86-64. Try this: >>>>> >>>>> make ENABLE_OPTIMIZED=1 TEST=nightly TARGET_FLAGS="-m64 - >>>>> DSPEC_CPU2000_LP64 -DSPEC_CPU_LP64" TARGET_LLCFLAGS="-relocation- >>>>> model=pic -disable-fp-elim" EXTRA_LLI_OPTS="-relocation- >>>>> model=pic -disable-fp-elim" clean Output/447.dealII.diff-llc >>>>> >>>>> Evan >>>>> >>>>> On May 29, 2008, at 6:23 PM, Dale Johannesen wrote: >>>>> >>>>>> Author: johannes >>>>>> Date: Thu May 29 20:23:12 2008 >>>>>> New Revision: 51723 >>>>>> >>>>>> URL: http://llvm.org/viewvc/llvm-project?rev=51723&view=rev >>>>>> Log: >>>>>> X86-64 ABI fix. Revert isSingleElementStructOrArray >>>>>> change in favor of a more general version which handles >>>>>> the case where there's more than one element correctly. >>>>>> Fixes gcc.dg/compat/struct-layout-1.exp/t003 >>>>>> and many more. >>>>>> >>>>>> >>>>>> Modified: >>>>>> llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h >>>>>> llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp >>>>>> llvm-gcc-4.2/trunk/gcc/config/rs6000/llvm-rs6000.cpp >>>>>> llvm-gcc-4.2/trunk/gcc/llvm-abi.h >>>>>> >>>>>> Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h >>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h?rev=51723&r1=51722&r2=51723&view=diff >>>>>> >>>>>> = >>>>>> = >>>>>> = >>>>>> = >>>>>> = >>>>>> = >>>>>> = >>>>>> = >>>>>> = >>>>>> = >>>>>> = >>>>>> = >>>>>> = >>>>>> ================================================================= >>>>>> --- llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h >>>>>> (original) >>>>>> +++ llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h Thu >>>>>> May 29 20:23:12 2008 >>>>>> @@ -95,17 +95,18 @@ >>>>>> considered as if they were the type of the data field. */ >>>>>> #ifndef LLVM_SHOULD_RETURN_SELT_STRUCT_AS_SCALAR >>>>>> #define LLVM_SHOULD_RETURN_SELT_STRUCT_AS_SCALAR(X) \ >>>>>> - isSingleElementStructOrArray(X, true, false, false) >>>>>> + isSingleElementStructOrArray(X, true, false) >>>>>> #endif >>>>>> >>>>>> +extern bool >>>>>> llvm_x86_should_pass_aggregate_in_integer_regs(tree, unsigned*); >>>>>> + >>>>>> /* LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS - Return true if >>>>>> this aggregate >>>>>> value should be passed in integer registers. This differs from >>>>>> the usual >>>>>> - handling in that x86-64 passes single-int-element unions as >>>>>> the type of the >>>>>> - field. */ >>>>>> -#define >>>>>> LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS(X) \ >>>>>> - >>>>>> (TARGET_64BIT >>>>>> ? \ >>>>>> - !isSingleElementStructOrArray((X), true, true, >>>>>> true) : \ >>>>>> - !isSingleElementStructOrArray((X), false, true, false)) >>>>>> + handling in that x86-64 passes 128-bit structs and unions >>>>>> which only >>>>>> + contain data in the first 64 bits, as 64-bit objects. >>>>>> (These can be >>>>>> + created by abusing __attribute__((aligned)). */ >>>>>> +#define LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS(X, >>>>>> Y) \ >>>>>> + llvm_x86_should_pass_aggregate_in_integer_regs((X), (Y)) >>>>>> >>>>>> extern bool llvm_x86_should_pass_vector_in_integer_regs(tree); >>>>>> >>>>>> >>>>>> Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp >>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp?rev=51723&r1=51722&r2=51723&view=diff >>>>>> >>>>>> = >>>>>> = >>>>>> = >>>>>> = >>>>>> = >>>>>> = >>>>>> = >>>>>> = >>>>>> = >>>>>> = >>>>>> = >>>>>> = >>>>>> = >>>>>> ================================================================= >>>>>> --- llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp (original) >>>>>> +++ llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp Thu May 29 >>>>>> 20:23:12 2008 >>>>>> @@ -1288,4 +1288,38 @@ >>>>>> return Loc; >>>>>> } >>>>>> >>>>>> +/// llvm_x86_should_pass_aggregate_in_integer_regs - x86-32 is >>>>>> same as the >>>>>> +/// default. x86-64 detects the case where a type is 16 bytes >>>>>> long but >>>>>> +/// only 8 of them are passed, the rest being padding (*size >>>>>> is set to 8 >>>>>> +/// to identify this case). >>>>>> +bool llvm_x86_should_pass_aggregate_in_integer_regs(tree type, >>>>>> unsigned *size) >>>>>> +{ >>>>>> + *size = 0; >>>>>> + if (TARGET_64BIT) { >>>>>> + enum x86_64_reg_class Class[MAX_CLASSES]; >>>>>> + enum machine_mode Mode = ix86_getNaturalModeForType(type); >>>>>> + int NumClasses = ix86_ClassifyArgument(Mode, type, Class, >>>>>> 0); >>>>>> + if (NumClasses == 1 && (Class[0] == X86_64_INTEGERSI_CLASS >>>>>> || >>>>>> + Class[0] == X86_64_INTEGER_CLASS)) { >>>>>> + /* 8 byte object, one int register */ >>>>>> + return true; >>>>>> + } >>>>>> + if (NumClasses == 2 && (Class[0] == X86_64_INTEGERSI_CLASS >>>>>> || >>>>>> + Class[0] == X86_64_INTEGER_CLASS)) { >>>>>> + if (Class[1] == X86_64_INTEGERSI_CLASS || >>>>>> + Class[1] == X86_64_INTEGER_CLASS) >>>>>> + /* 16 byte object, 2 int registers */ >>>>>> + return true; >>>>>> + if (Class[1] == X86_64_NO_CLASS) { >>>>>> + /* 16 byte object, only 1st register has information */ >>>>>> + *size = 8; >>>>>> + return true; >>>>>> + } >>>>>> + } >>>>>> + return false; >>>>>> + } >>>>>> + else >>>>>> + return !isSingleElementStructOrArray(type, false, true); >>>>>> +} >>>>>> + >>>>>> /* LLVM LOCAL end (ENTIRE FILE!) */ >>>>>> >>>>>> Modified: llvm-gcc-4.2/trunk/gcc/config/rs6000/llvm-rs6000.cpp >>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/rs6000/llvm-rs6000.cpp?rev=51723&r1=51722&r2=51723&view=diff >>>>>> >>>>>> = >>>>>> = >>>>>> = >>>>>> = >>>>>> = >>>>>> = >>>>>> = >>>>>> = >>>>>> = >>>>>> = >>>>>> = >>>>>> = >>>>>> = >>>>>> ================================================================= >>>>>> --- llvm-gcc-4.2/trunk/gcc/config/rs6000/llvm-rs6000.cpp >>>>>> (original) >>>>>> +++ llvm-gcc-4.2/trunk/gcc/config/rs6000/llvm-rs6000.cpp Thu >>>>>> May 29 20:23:12 2008 >>>>>> @@ -404,7 +404,7 @@ >>>>>> // some zero-length fields as well, must be passed as the field >>>>>> type. >>>>>> // Note this does not apply to long double. >>>>>> // This is required for ABI correctness. >>>>>> - tree tType = isSingleElementStructOrArray(TreeType, true, >>>>>> false, false); >>>>>> + tree tType = isSingleElementStructOrArray(TreeType, true, >>>>>> false); >>>>>> if (tType && int_size_in_bytes(tType)==Bytes && >>>>>> TYPE_MODE(tType)!=TFmode && >>>>>> (TREE_CODE(tType)!=VECTOR_TYPE || Bytes==16)) >>>>>> return false; >>>>>> @@ -437,7 +437,7 @@ >>>>>> // Other single-element structs may be passed this way as well, >>>>>> but >>>>>> // only if the type size matches the element's type size >>>>>> (structs that >>>>>> // violate this can be created with __aligned__). >>>>>> - tree tType = isSingleElementStructOrArray(TreeType, true, >>>>>> false, false); >>>>>> + tree tType = isSingleElementStructOrArray(TreeType, true, >>>>>> false); >>>>>> if (tType && int_size_in_bytes(tType)==SrcSize && >>>>>> TYPE_MODE(tType)!=TFmode && >>>>>> (TREE_CODE(tType)!=VECTOR_TYPE || SrcSize==16)) { >>>>>> Elts.push_back(ConvertType(tType)); >>>>>> >>>>>> Modified: llvm-gcc-4.2/trunk/gcc/llvm-abi.h >>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-abi.h?rev=51723&r1=51722&r2=51723&view=diff >>>>>> >>>>>> = >>>>>> = >>>>>> = >>>>>> = >>>>>> = >>>>>> = >>>>>> = >>>>>> = >>>>>> = >>>>>> = >>>>>> = >>>>>> = >>>>>> = >>>>>> ================================================================= >>>>>> --- llvm-gcc-4.2/trunk/gcc/llvm-abi.h (original) >>>>>> +++ llvm-gcc-4.2/trunk/gcc/llvm-abi.h Thu May 29 20:23:12 2008 >>>>>> @@ -138,21 +138,17 @@ >>>>>> /// rejectFatBitField, and the single element is a bitfield of >>>>>> a type that's >>>>>> /// bigger than the struct, return null anyway. >>>>>> static tree isSingleElementStructOrArray(tree type, bool >>>>>> ignoreZeroLength, >>>>>> - bool rejectFatBitfield, >>>>>> - bool acceptUnions) { >>>>>> + bool >>>>>> rejectFatBitfield) { >>>>>> // Scalars are good. >>>>>> if (!isAggregateTreeType(type)) return type; >>>>>> >>>>>> tree FoundField = 0; >>>>>> switch (TREE_CODE(type)) { >>>>>> case QUAL_UNION_TYPE: >>>>>> + case UNION_TYPE: // Single element unions don't count. >>>>>> case COMPLEX_TYPE: // Complex values are like 2-element >>>>>> records. >>>>>> default: >>>>>> return 0; >>>>>> - case UNION_TYPE: // Single element unions don't count. >>>>>> - if (!acceptUnions) >>>>>> - return 0; >>>>>> - // fall through >>>>>> case RECORD_TYPE: >>>>>> // If this record has variable length, reject it. >>>>>> if (TREE_CODE(TYPE_SIZE(type)) != INTEGER_CST) >>>>>> @@ -178,15 +174,13 @@ >>>>>> } >>>>>> } >>>>>> return FoundField ? isSingleElementStructOrArray(FoundField, >>>>>> - >>>>>> ignoreZeroLength, false, >>>>>> - false) >>>>>> + >>>>>> ignoreZeroLength, false) >>>>>> : 0; >>>>>> case ARRAY_TYPE: >>>>>> const ArrayType *Ty = dyn_cast(ConvertType(type)); >>>>>> if (!Ty || Ty->getNumElements() != 1) >>>>>> return 0; >>>>>> - return isSingleElementStructOrArray(TREE_TYPE(type), >>>>>> false, false, >>>>>> - false); >>>>>> + return isSingleElementStructOrArray(TREE_TYPE(type), >>>>>> false, false); >>>>>> } >>>>>> } >>>>>> >>>>>> @@ -283,8 +277,8 @@ >>>>>> // single element is a bitfield of a type bigger than the >>>>>> struct; the code >>>>>> // for field-by-field struct passing does not handle this one >>>>>> right. >>>>>> #ifndef LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS >>>>>> -#define LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS(X) \ >>>>>> - !isSingleElementStructOrArray(X, false, true, false) >>>>>> +#define LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS(X, Y) \ >>>>>> + !isSingleElementStructOrArray((X), false, true) >>>>>> #endif >>>>>> >>>>>> // LLVM_SHOULD_RETURN_SELT_STRUCT_AS_SCALAR - Return a TYPE >>>>>> tree if this single >>>>>> @@ -295,7 +289,7 @@ >>>>>> // by abusing the __aligned__ attribute.) >>>>>> #ifndef LLVM_SHOULD_RETURN_SELT_STRUCT_AS_SCALAR >>>>>> #define LLVM_SHOULD_RETURN_SELT_STRUCT_AS_SCALAR(X) \ >>>>>> - isSingleElementStructOrArray(X, false, false, false) >>>>>> + isSingleElementStructOrArray(X, false, false) >>>>>> #endif >>>>>> >>>>>> // LLVM_SHOULD_RETURN_VECTOR_AS_SCALAR - Return a TYPE tree if >>>>>> this vector type >>>>>> @@ -408,6 +402,7 @@ >>>>>> /// their fields. >>>>>> void HandleArgument(tree type, std::vector >>>>>> &ScalarElts, >>>>>> ParameterAttributes *Attributes = NULL) { >>>>>> + unsigned Size = 0; >>>>>> const Type *Ty = ConvertType(type); >>>>>> // Figure out if this field is zero bits wide, e.g. {} or [0 x >>>>>> int]. Do >>>>>> // not include variable sized fields here. >>>>>> @@ -418,7 +413,7 @@ >>>>>> ScalarElts.push_back(PtrTy); >>>>>> } else if (Ty->getTypeID()==Type::VectorTyID) { >>>>>> if (LLVM_SHOULD_PASS_VECTOR_IN_INTEGER_REGS(type)) { >>>>>> - PassInIntegerRegisters(type, Ty, ScalarElts); >>>>>> + PassInIntegerRegisters(type, Ty, ScalarElts, 0); >>>>>> } else { >>>>>> C.HandleScalarArgument(Ty, type); >>>>>> ScalarElts.push_back(Ty); >>>>>> @@ -444,8 +439,8 @@ >>>>>> *Attributes |= >>>>>> >>>>>> ParamAttr::constructAlignmentFromInt(LLVM_BYVAL_ALIGNMENT(type)); >>>>>> } >>>>>> - } else if >>>>>> (LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS(type)) { >>>>>> - PassInIntegerRegisters(type, Ty, ScalarElts); >>>>>> + } else if >>>>>> (LLVM_SHOULD_PASS_AGGREGATE_IN_INTEGER_REGS(type, &Size)) { >>>>>> + PassInIntegerRegisters(type, Ty, ScalarElts, Size); >>>>>> } else if (isZeroSizedStructOrUnion(type)) { >>>>>> // Zero sized struct or union, just drop it! >>>>>> ; >>>>>> @@ -526,10 +521,15 @@ >>>>>> >>>>>> /// PassInIntegerRegisters - Given an aggregate value that >>>>>> should be passed in >>>>>> /// integer registers, convert it to a structure containing >>>>>> ints and pass all >>>>>> - /// of the struct elements in. >>>>>> + /// of the struct elements in. If Size is set we pass only >>>>>> that many bytes. >>>>>> void PassInIntegerRegisters(tree type, const Type *Ty, >>>>>> - std::vector >>>>>> &ScalarElts) { >>>>>> - unsigned Size = TREE_INT_CST_LOW(TYPE_SIZE(type))/8; >>>>>> + std::vector >>>>>> &ScalarElts, >>>>>> + unsigned origSize) { >>>>>> + unsigned Size; >>>>>> + if (origSize) >>>>>> + Size = origSize; >>>>>> + else >>>>>> + Size = TREE_INT_CST_LOW(TYPE_SIZE(type))/8; >>>>>> >>>>>> // FIXME: We should preserve all aggregate value alignment >>>>>> information. >>>>>> // Work around to preserve some aggregate value alignment >>>>>> information: >>>>>> @@ -568,7 +568,7 @@ >>>>>> Elts.push_back(Type::Int8Ty); >>>>>> Size -= 1; >>>>>> } >>>>>> - assert(Size == 0 && "Didn't cover value?"); >>>>>> + assert((origSize || Size == 0) && "Didn't cover value?"); >>>>>> const StructType *STy = StructType::get(Elts, false); >>>>>> >>>>>> unsigned i = 0; >>>>>> >>>>>> >>>>>> _______________________________________________ >>>>>> llvm-commits mailing list >>>>>> llvm-commits at cs.uiuc.edu >>>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>>>> >>>> >>> >> > From resistor at mac.com Tue Jun 3 19:38:57 2008 From: resistor at mac.com (Owen Anderson) Date: Wed, 04 Jun 2008 00:38:57 -0000 Subject: [llvm-commits] [llvm] r51922 - /llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp Message-ID: <200806040038.m540cv9N001468@zion.cs.uiuc.edu> Author: resistor Date: Tue Jun 3 19:38:56 2008 New Revision: 51922 URL: http://llvm.org/viewvc/llvm-project?rev=51922&view=rev Log: We need to subtract one from this index because live ranges are open at the end. Modified: llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp Modified: llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp?rev=51922&r1=51921&r2=51922&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp (original) +++ llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp Tue Jun 3 19:38:56 2008 @@ -467,7 +467,7 @@ } else { // Otherwise, add it to the renaming set LiveInterval& I = LI.getOrCreateInterval(SrcReg); - unsigned idx = LI.getMBBEndIdx(P->getOperand(i).getMBB()); + unsigned idx = LI.getMBBEndIdx(P->getOperand(i).getMBB()) - 1; VNInfo* VN = I.getLiveRangeContaining(idx)->valno; assert(VN && "No VNInfo for register?"); From echristo at apple.com Tue Jun 3 19:40:41 2008 From: echristo at apple.com (Eric Christopher) Date: Tue, 3 Jun 2008 17:40:41 -0700 Subject: [llvm-commits] [llvm] r51922 - /llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp In-Reply-To: <200806040038.m540cv9N001468@zion.cs.uiuc.edu> References: <200806040038.m540cv9N001468@zion.cs.uiuc.edu> Message-ID: <2B698B86-C507-4C43-85FA-A19AC568C86D@apple.com> > > We need to subtract one from this index because live ranges are open > at the end. > > - unsigned idx = LI.getMBBEndIdx(P->getOperand(i).getMBB()); > + unsigned idx = LI.getMBBEndIdx(P->getOperand(i).getMBB()) - > 1; > VNInfo* VN = I.getLiveRangeContaining(idx)->valno; This would make a great comment right here :) -eric From bruno.cardoso at gmail.com Tue Jun 3 20:45:25 2008 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Wed, 04 Jun 2008 01:45:25 -0000 Subject: [llvm-commits] [llvm] r51923 - in /llvm/trunk/lib/Target/Mips: MipsAsmPrinter.cpp MipsISelLowering.cpp MipsInstrInfo.td MipsRegisterInfo.cpp MipsSubtarget.cpp MipsSubtarget.h MipsTargetMachine.cpp MipsTargetMachine.h Message-ID: <200806040145.m541jQs8003499@zion.cs.uiuc.edu> Author: bruno Date: Tue Jun 3 20:45:25 2008 New Revision: 51923 URL: http://llvm.org/viewvc/llvm-project?rev=51923&view=rev Log: Some Mips minor fixes Added support for mips little endian arch => mipsel Modified: llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp llvm/trunk/lib/Target/Mips/MipsInstrInfo.td llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp llvm/trunk/lib/Target/Mips/MipsSubtarget.h llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp llvm/trunk/lib/Target/Mips/MipsTargetMachine.h Modified: llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp?rev=51923&r1=51922&r2=51923&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp Tue Jun 3 20:45:25 2008 @@ -547,5 +547,7 @@ } } + O << "\n"; + return AsmPrinter::doFinalization(M); } Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=51923&r1=51922&r2=51923&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Tue Jun 3 20:45:25 2008 @@ -365,6 +365,7 @@ Chain = DAG.getNode(MipsISD::JmpLink, NodeTys, &Ops[0], Ops.size()); InFlag = Chain.getValue(1); + // Create the CALLSEQ_END node. Chain = DAG.getCALLSEQ_END(Chain, DAG.getConstant(NumBytes, getPointerTy()), DAG.getConstant(0, getPointerTy()), @@ -400,8 +401,6 @@ InFlag = Chain.getValue(1); } - // Create the CALLSEQ_END node. - // Handle result values, copying them out of physregs into vregs that we // return. return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo); Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=51923&r1=51922&r2=51923&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Tue Jun 3 20:45:25 2008 @@ -135,7 +135,6 @@ [], IIAlu>; // Arithmetic 2 register operands -let isCommutable = 1 in class ArithI op, string instr_asm, SDNode OpNode, Operand Od, PatLeaf imm_type> : FI< op, Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp?rev=51923&r1=51922&r2=51923&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Tue Jun 3 20:45:25 2008 @@ -147,7 +147,7 @@ // // 0 ---------- // 4 Args to pass -// . saved $GP (used in PIC - not supported yet) +// . saved $GP (used in PIC) // . Local Area // . saved "Callee Saved" Registers // . saved FP @@ -369,7 +369,7 @@ // lw $ra, stack_loc($sp) if (MFI->hasCalls()) { BuildMI(MBB, MBBI, TII.get(Mips::LW)) - .addReg(Mips::RA).addImm(RAOffset).addReg(Mips::SP); + .addReg(Mips::RA).addImm(RAOffset).addReg(Mips::SP); } // adjust stack : insert addi sp, sp, (imm) Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp?rev=51923&r1=51922&r2=51923&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp Tue Jun 3 20:45:25 2008 @@ -17,8 +17,9 @@ using namespace llvm; MipsSubtarget::MipsSubtarget(const TargetMachine &TM, const Module &M, - const std::string &FS) : - IsMipsIII(false) + const std::string &FS, bool little) : + IsMipsIII(false), + IsLittle(little) { std::string CPU = "mips1"; Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.h?rev=51923&r1=51922&r2=51923&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsSubtarget.h (original) +++ llvm/trunk/lib/Target/Mips/MipsSubtarget.h Tue Jun 3 20:45:25 2008 @@ -27,14 +27,14 @@ protected: bool IsMipsIII; + bool IsLittle; InstrItineraryData InstrItins; public: /// This constructor initializes the data members to match that /// of the specified module. - /// MipsSubtarget(const TargetMachine &TM, const Module &M, - const std::string &FS); + const std::string &FS, bool little); /// ParseSubtargetFeatures - Parses features string setting specified /// subtarget options. Definition of function is auto generated by tblgen. @@ -43,6 +43,9 @@ /// isMipsIII - Return true if the selected CPU supports MipsIII ISA /// support. bool isMipsIII() const { return IsMipsIII; } + + /// isMipsIII - Return true if the target is little endian. + bool isLittle() const { return IsLittle; } }; } // End llvm namespace Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp?rev=51923&r1=51922&r2=51923&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp Tue Jun 3 20:45:25 2008 @@ -20,7 +20,8 @@ using namespace llvm; // Register the target. -static RegisterTarget X("mips", " Mips"); +static RegisterTarget X("mips", " Mips"); +static RegisterTarget Y("mipsel", " Mipsel"); const TargetAsmInfo *MipsTargetMachine:: createTargetAsmInfo() const @@ -35,11 +36,13 @@ // offset from the stack/frame pointer, so StackGrowsUp is used. // When using CodeModel::Large the behaviour // -// MipsTargetMachine:: -MipsTargetMachine(const Module &M, const std::string &FS): - Subtarget(*this, M, FS), DataLayout("E-p:32:32:32"), - InstrInfo(*this), FrameInfo(TargetFrameInfo::StackGrowsUp, 8, 0), +MipsTargetMachine(const Module &M, const std::string &FS, bool isLittle=false): + Subtarget(*this, M, FS, isLittle), + DataLayout(isLittle ? std::string("e-p:32:32:32") : + std::string("E-p:32:32:32")), + InstrInfo(*this), + FrameInfo(TargetFrameInfo::StackGrowsUp, 8, 0), TLInfo(*this) { if (getRelocationModel() != Reloc::Static) @@ -48,6 +51,10 @@ setCodeModel(CodeModel::Small); } +MipselTargetMachine:: +MipselTargetMachine(const Module &M, const std::string &FS) : + MipsTargetMachine(M, FS, true) {} + // return 0 and must specify -march to gen MIPS code. unsigned MipsTargetMachine:: getModuleMatchQuality(const Module &M) @@ -60,6 +67,18 @@ return 0; } +// return 0 and must specify -march to gen MIPSel code. +unsigned MipselTargetMachine:: +getModuleMatchQuality(const Module &M) +{ + // We strongly match "mipsel-*". + std::string TT = M.getTargetTriple(); + if (TT.size() >= 7 && std::string(TT.begin(), TT.begin()+7) == "mipsel-") + return 20; + + return 0; +} + // Install an instruction selector pass using // the ISelDag to gen Mips code. bool MipsTargetMachine:: Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.h?rev=51923&r1=51922&r2=51923&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsTargetMachine.h (original) +++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.h Tue Jun 3 20:45:25 2008 @@ -33,7 +33,7 @@ virtual const TargetAsmInfo *createTargetAsmInfo() const; public: - MipsTargetMachine(const Module &M, const std::string &FS); + MipsTargetMachine(const Module &M, const std::string &FS, bool isLittle); virtual const MipsInstrInfo *getInstrInfo() const { return &InstrInfo; } @@ -60,6 +60,16 @@ virtual bool addAssemblyEmitter(PassManagerBase &PM, bool Fast, std::ostream &Out); }; + +/// MipselTargetMachine - Mipsel target machine. +/// +class MipselTargetMachine : public MipsTargetMachine { +public: + MipselTargetMachine(const Module &M, const std::string &FS); + + static unsigned getModuleMatchQuality(const Module &M); +}; + } // End llvm namespace #endif From nicholas at mxc.ca Tue Jun 3 22:51:24 2008 From: nicholas at mxc.ca (Nick Lewycky) Date: Tue, 03 Jun 2008 20:51:24 -0700 Subject: [llvm-commits] value range analysis based on scalar-evolutions In-Reply-To: <36D98FFC-7C90-448F-AA77-F84CE3F71013@apple.com> References: <48436EF1.8020203@mxc.ca> <36D98FFC-7C90-448F-AA77-F84CE3F71013@apple.com> Message-ID: <4846113C.2060002@mxc.ca> Devang Patel wrote: > On Jun 1, 2008, at 8:54 PM, Nick Lewycky wrote: > >> I've implemented an analysis pass that uses SCEV to determine value >> ranges of integer-typed registers. >> >> Currently it maintains a map of Value* to ConstantRange*, which is >> rather inelegant. I was thinking we could have one analysis which >> would do that and others that would update the central analysis. >> >> I also implemented an optz'n pass based on it, but it hardly >> optimized anything and as such is not included in this patch. >> >> Please comment! > > > +static RegisterPass X("loopvr", "Loop Value Ranges"); > > You want to register this as an analysis pass and cfe-only pass. Fixed. Thanks. > +static SCEVHandle getTruncateOrZeroExtend(const SCEVHandle &V, const > Type *Ty, > + ScalarEvolution &SE) { > > Why not move this into ScalarEvolution.h ? Done. > + APInt Spread_X = X.getSetSize(), Spread_Y = Y.getSetSize(); > + APInt NewLower = X.getLower() + Y.getLower(), > + NewUpper = X.getUpper() + Y.getUpper() - 1; > > nit-pick. I'd prefer to write this as > > APInt NewLower = ..; > APInt NewUpper = ..; > Yep, good point. Done. > +bool LoopVR::runOnFunction(Function &F) { > > Is there a reason to not make this a LoopPass ? Because then it wouldn't store Value->ConstantRange mappings for the whole function. There's no reason the SCEV analysis stuff couldn't move into a LoopPass, but the mapping probably shouldn't be. > + for (LoopInfo::iterator I = LI.begin(), E = LI.end(); I != E; ++I) { > + Loop *L = *I; > > ... > > + Loop *LL = LI.getLoopFor(*BI); > + if (LL->isLoopInvariant(II)) continue; > > Do you really want to check LL->isLoopInvariant(II) instead of L- > >isLoopInvariant(II) here ? We aren't iterating across all loops with 'L', only the top-level ones. 'LL' is the inner-most loop containing this BB. It would probably be best if we looked at every loop that contains a given BB, but looking at only the outer-most loop could cause us to compute the wrong result. (Suppose in the outer loop, the result it known to go from 1 to 5, but in the inner loop we know it goes from 25 to 1, ending between 1 and 5 once the inner loop is done. We can't optimize instructions in the inner loop based on the 1..5 range!) Nick From sabre at nondot.org Tue Jun 3 23:46:14 2008 From: sabre at nondot.org (Chris Lattner) Date: Wed, 04 Jun 2008 04:46:14 -0000 Subject: [llvm-commits] [llvm] r51926 - in /llvm/trunk: lib/Analysis/ValueTracking.cpp utils/TableGen/LLVMCConfigurationEmitter.cpp Message-ID: <200806040446.m544kEhs008617@zion.cs.uiuc.edu> Author: lattner Date: Tue Jun 3 23:46:14 2008 New Revision: 51926 URL: http://llvm.org/viewvc/llvm-project?rev=51926&view=rev Log: Add #includes required by GCC 4.3, thanks for Zhongxing Xu for reporting this. Modified: llvm/trunk/lib/Analysis/ValueTracking.cpp llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp Modified: llvm/trunk/lib/Analysis/ValueTracking.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ValueTracking.cpp?rev=51926&r1=51925&r2=51926&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ValueTracking.cpp (original) +++ llvm/trunk/lib/Analysis/ValueTracking.cpp Tue Jun 3 23:46:14 2008 @@ -19,6 +19,7 @@ #include "llvm/Target/TargetData.h" #include "llvm/Support/GetElementPtrTypeIterator.h" #include "llvm/Support/MathExtras.h" +#include using namespace llvm; /// getOpcode - If this is an Instruction or a ConstantExpr, return the Modified: llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp?rev=51926&r1=51925&r2=51926&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/LLVMCConfigurationEmitter.cpp Tue Jun 3 23:46:14 2008 @@ -20,13 +20,12 @@ #include "llvm/ADT/StringMap.h" #include "llvm/ADT/StringSet.h" #include "llvm/Support/Streams.h" - #include #include #include #include #include - +#include using namespace llvm; namespace { From baldrick at free.fr Wed Jun 4 02:04:38 2008 From: baldrick at free.fr (Duncan Sands) Date: Wed, 04 Jun 2008 07:04:38 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r51927 - /llvm-gcc-4.2/trunk/gcc/llvm-types.cpp Message-ID: <200806040704.m5474cA1012835@zion.cs.uiuc.edu> Author: baldrick Date: Wed Jun 4 02:04:38 2008 New Revision: 51927 URL: http://llvm.org/viewvc/llvm-project?rev=51927&view=rev Log: If the gcc union type is less aligned than the LLVM struct, pack the struct. While there, remove some dead code that creates a filler for empty unions (this was already handled by the general case a few lines before) and remove trailing whitespace. This cures some testsuite failures caused by fixing the way the union element is chosen. Modified: llvm-gcc-4.2/trunk/gcc/llvm-types.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-types.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-types.cpp?rev=51927&r1=51926&r2=51927&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-types.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-types.cpp Wed Jun 4 02:04:38 2008 @@ -2264,40 +2264,36 @@ } std::vector UnionElts; - unsigned UnionSize = 0; + unsigned EltAlign = 0; + unsigned EltSize = 0; if (UnionTy) { // Not an empty union. - UnionSize = TD.getABITypeSize(UnionTy); + EltAlign = TD.getABITypeAlignment(UnionTy); + EltSize = TD.getABITypeSize(UnionTy); UnionElts.push_back(UnionTy); } - + // If the LLVM struct requires explicit tail padding to be the same size as // the GCC union, insert tail padding now. This handles cases where the union // has larger alignment than the largest member does, thus requires tail // padding. if (TYPE_SIZE(type) && TREE_CODE(TYPE_SIZE(type)) == INTEGER_CST) { unsigned GCCTypeSize = ((unsigned)TREE_INT_CST_LOW(TYPE_SIZE(type))+7)/8; - - if (UnionSize != GCCTypeSize) { - assert(UnionSize < GCCTypeSize && + + if (EltSize != GCCTypeSize) { + assert(EltSize < GCCTypeSize && "LLVM type size doesn't match GCC type size!"); const Type *PadTy = Type::Int8Ty; - if (GCCTypeSize-UnionSize != 1) - PadTy = ArrayType::get(PadTy, GCCTypeSize-UnionSize); + if (GCCTypeSize-EltSize != 1) + PadTy = ArrayType::get(PadTy, GCCTypeSize-EltSize); UnionElts.push_back(PadTy); } } - - // If this is an empty union, but there is tail padding, make a filler. - if (UnionTy == 0) { - unsigned Size = ((unsigned)TREE_INT_CST_LOW(TYPE_SIZE(type))+7)/8; - UnionTy = Type::Int8Ty; - if (Size != 1) UnionTy = ArrayType::get(UnionTy, Size); - } - - const Type *ResultTy = StructType::get(UnionElts, false); + + bool isPacked = EltAlign > TYPE_ALIGN_UNIT(type); + const Type *ResultTy = StructType::get(UnionElts, isPacked); const OpaqueType *OldTy = cast_or_null(GET_TYPE_LLVM(type)); TypeDB.setType(type, ResultTy); - + // If there was a forward declaration for this type that is now resolved, // refine anything that used it to the new type. if (OldTy) From baldrick at free.fr Wed Jun 4 02:16:12 2008 From: baldrick at free.fr (Duncan Sands) Date: Wed, 4 Jun 2008 09:16:12 +0200 Subject: [llvm-commits] [llvm-gcc-4.2] r51866 - /llvm-gcc-4.2/trunk/gcc/llvm-types.cpp In-Reply-To: References: <200806021556.m52FunYg008136@zion.cs.uiuc.edu> Message-ID: <200806040916.13008.baldrick@free.fr> On Tuesday 03 June 2008 19:57:17 Dale Johannesen wrote: > This patch breaks FrontendC/2008-01-28-UnionSize.c and FrontendC/ > 2007-09-28-PackedUnionMember.c on Darwin x86-32. These should be fixed now. Sorry for the breakage. Ciao, Duncan. From baldrick at free.fr Wed Jun 4 03:21:45 2008 From: baldrick at free.fr (Duncan Sands) Date: Wed, 04 Jun 2008 08:21:45 -0000 Subject: [llvm-commits] [llvm] r51928 - in /llvm/trunk: include/llvm/CodeGen/AsmPrinter.h lib/CodeGen/AsmPrinter.cpp lib/Target/TargetData.cpp lib/Transforms/Scalar/ScalarReplAggregates.cpp test/Other/2008-06-04-FieldSizeInPacked.ll Message-ID: <200806040821.m548LjJT023760@zion.cs.uiuc.edu> Author: baldrick Date: Wed Jun 4 03:21:45 2008 New Revision: 51928 URL: http://llvm.org/viewvc/llvm-project?rev=51928&view=rev Log: Change packed struct layout so that field sizes are the same as in unpacked structs, only field positions differ. This only matters for structs containing x86 long double or an apint; it may cause backwards compatibility problems if someone has bitcode containing a packed struct with a field of one of those types. The issue is that only 10 bytes are needed to hold an x86 long double: the store size is 10 bytes, but the ABI size is 12 or 16 bytes (linux/ darwin) which comes from rounding the store size up by the alignment. Because it seemed silly not to pack an x86 long double into 10 bytes in a packed struct, this is what was done. I now think this was a mistake. Reserving the ABI size for an x86 long double field even in a packed struct makes things more uniform: the ABI size is now always used when reserving space for a type. This means that developers are less likely to make mistakes. It also makes life easier for the CBE which otherwise could not represent all LLVM packed structs (PR2402). Front-end people might need to adjust the way they create LLVM structs - see following change to llvm-gcc. Added: llvm/trunk/test/Other/2008-06-04-FieldSizeInPacked.ll Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h llvm/trunk/lib/CodeGen/AsmPrinter.cpp llvm/trunk/lib/Target/TargetData.cpp llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/AsmPrinter.h?rev=51928&r1=51927&r2=51928&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/AsmPrinter.h (original) +++ llvm/trunk/include/llvm/CodeGen/AsmPrinter.h Wed Jun 4 03:21:45 2008 @@ -314,8 +314,7 @@ void EmitConstantValueOnly(const Constant *CV); /// EmitGlobalConstant - Print a general LLVM constant to the .s file. - /// If Packed is false, pad to the ABI size. - void EmitGlobalConstant(const Constant* CV, bool Packed = false); + void EmitGlobalConstant(const Constant* CV); virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV); Modified: llvm/trunk/lib/CodeGen/AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter.cpp?rev=51928&r1=51927&r2=51928&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter.cpp Wed Jun 4 03:21:45 2008 @@ -889,11 +889,9 @@ } /// EmitGlobalConstant - Print a general LLVM constant to the .s file. -/// If Packed is false, pad to the ABI size. -void AsmPrinter::EmitGlobalConstant(const Constant *CV, bool Packed) { +void AsmPrinter::EmitGlobalConstant(const Constant *CV) { const TargetData *TD = TM.getTargetData(); - unsigned Size = Packed ? - TD->getTypeStoreSize(CV->getType()) : TD->getABITypeSize(CV->getType()); + unsigned Size = TD->getABITypeSize(CV->getType()); if (CV->isNullValue() || isa(CV)) { EmitZeros(Size); @@ -903,7 +901,7 @@ EmitString(CVA); } else { // Not a string. Print the values in successive locations for (unsigned i = 0, e = CVA->getNumOperands(); i != e; ++i) - EmitGlobalConstant(CVA->getOperand(i), false); + EmitGlobalConstant(CVA->getOperand(i)); } return; } else if (const ConstantStruct *CVS = dyn_cast(CV)) { @@ -914,13 +912,13 @@ const Constant* field = CVS->getOperand(i); // Check if padding is needed and insert one or more 0s. - uint64_t fieldSize = TD->getTypeStoreSize(field->getType()); + uint64_t fieldSize = TD->getABITypeSize(field->getType()); uint64_t padSize = ((i == e-1 ? Size : cvsLayout->getElementOffset(i+1)) - cvsLayout->getElementOffset(i)) - fieldSize; sizeSoFar += fieldSize + padSize; - // Now print the actual field value without ABI size padding. - EmitGlobalConstant(field, true); + // Now print the actual field value. + EmitGlobalConstant(field); // Insert padding - this may include padding to increase the size of the // current field up to the ABI size (if the struct is not packed) as well @@ -1066,7 +1064,7 @@ const VectorType *PTy = CP->getType(); for (unsigned I = 0, E = PTy->getNumElements(); I < E; ++I) - EmitGlobalConstant(CP->getOperand(I), false); + EmitGlobalConstant(CP->getOperand(I)); return; } Modified: llvm/trunk/lib/Target/TargetData.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetData.cpp?rev=51928&r1=51927&r2=51928&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetData.cpp (original) +++ llvm/trunk/lib/Target/TargetData.cpp Wed Jun 4 03:21:45 2008 @@ -48,10 +48,7 @@ // Loop over each of the elements, placing them in memory... for (unsigned i = 0, e = NumElements; i != e; ++i) { const Type *Ty = ST->getElementType(i); - unsigned TyAlign = ST->isPacked() ? - 1 : TD.getABITypeAlignment(Ty); - uint64_t TySize = ST->isPacked() ? - TD.getTypeStoreSize(Ty) : TD.getABITypeSize(Ty); + unsigned TyAlign = ST->isPacked() ? 1 : TD.getABITypeAlignment(Ty); // Add padding if necessary to align the data element properly... StructSize = (StructSize + TyAlign - 1)/TyAlign * TyAlign; @@ -60,7 +57,7 @@ StructAlignment = std::max(TyAlign, StructAlignment); MemberOffsets[i] = StructSize; - StructSize += TySize; // Consume space for this data item + StructSize += TD.getABITypeSize(Ty); // Consume space for this data item } // Empty structures have alignment of 1 byte. Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=51928&r1=51927&r2=51928&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Wed Jun 4 03:21:45 2008 @@ -737,8 +737,7 @@ /// HasPadding - Return true if the specified type has any structure or /// alignment padding, false otherwise. -static bool HasPadding(const Type *Ty, const TargetData &TD, - bool inPacked = false) { +static bool HasPadding(const Type *Ty, const TargetData &TD) { if (const StructType *STy = dyn_cast(Ty)) { const StructLayout *SL = TD.getStructLayout(STy); unsigned PrevFieldBitOffset = 0; @@ -746,7 +745,7 @@ unsigned FieldBitOffset = SL->getElementOffsetInBits(i); // Padding in sub-elements? - if (HasPadding(STy->getElementType(i), TD, STy->isPacked())) + if (HasPadding(STy->getElementType(i), TD)) return true; // Check to see if there is any padding between this element and the @@ -770,12 +769,11 @@ } } else if (const ArrayType *ATy = dyn_cast(Ty)) { - return HasPadding(ATy->getElementType(), TD, false); + return HasPadding(ATy->getElementType(), TD); } else if (const VectorType *VTy = dyn_cast(Ty)) { - return HasPadding(VTy->getElementType(), TD, false); + return HasPadding(VTy->getElementType(), TD); } - return inPacked ? - false : TD.getTypeSizeInBits(Ty) != TD.getABITypeSizeInBits(Ty); + return TD.getTypeSizeInBits(Ty) != TD.getABITypeSizeInBits(Ty); } /// isSafeStructAllocaToScalarRepl - Check to see if the specified allocation of Added: llvm/trunk/test/Other/2008-06-04-FieldSizeInPacked.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Other/2008-06-04-FieldSizeInPacked.ll?rev=51928&view=auto ============================================================================== --- llvm/trunk/test/Other/2008-06-04-FieldSizeInPacked.ll (added) +++ llvm/trunk/test/Other/2008-06-04-FieldSizeInPacked.ll Wed Jun 4 03:21:45 2008 @@ -0,0 +1,14 @@ +; RUN: llvm-as < %s | opt -instcombine | llvm-dis | grep true + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" +target triple = "x86_64-unknown-linux-gnu" + %packed = type <{ x86_fp80, i8 }> + %unpacked = type { x86_fp80, i8 } + +define i1 @q() nounwind { +entry: + %char_p = getelementptr %packed* null, i32 0, i32 1 ; [#uses=1] + %char_u = getelementptr %unpacked* null, i32 0, i32 1 ; [#uses=1] + %res = icmp eq i8* %char_p, %char_u ; [#uses=1] + ret i1 %res +} From baldrick at free.fr Wed Jun 4 03:22:10 2008 From: baldrick at free.fr (Duncan Sands) Date: Wed, 04 Jun 2008 08:22:10 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r51929 - /llvm-gcc-4.2/trunk/gcc/llvm-types.cpp Message-ID: <200806040822.m548MAGK023800@zion.cs.uiuc.edu> Author: baldrick Date: Wed Jun 4 03:22:10 2008 New Revision: 51929 URL: http://llvm.org/viewvc/llvm-project?rev=51929&view=rev Log: The ABI size is now used for fields of packed structs like for unpacked structs. Modified: llvm-gcc-4.2/trunk/gcc/llvm-types.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-types.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-types.cpp?rev=51929&r1=51928&r2=51929&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-types.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-types.cpp Wed Jun 4 03:22:10 2008 @@ -1321,7 +1321,7 @@ /// getTypeSize - Return the size of the specified type in bytes. /// unsigned getTypeSize(const Type *Ty) const { - return Packed ? TD.getTypeStoreSize(Ty) : TD.getABITypeSize(Ty); + return TD.getABITypeSize(Ty); } /// getLLVMType - Return the LLVM type for the specified object. From evan.cheng at apple.com Wed Jun 4 04:13:39 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 04 Jun 2008 09:13:39 -0000 Subject: [llvm-commits] [llvm] r51930 - /llvm/trunk/lib/VMCore/PassManager.cpp Message-ID: <200806040913.m549DdBm026005@zion.cs.uiuc.edu> Author: evancheng Date: Wed Jun 4 04:13:31 2008 New Revision: 51930 URL: http://llvm.org/viewvc/llvm-project?rev=51930&view=rev Log: More pass manager debugging outputs. Modified: llvm/trunk/lib/VMCore/PassManager.cpp Modified: llvm/trunk/lib/VMCore/PassManager.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/PassManager.cpp?rev=51930&r1=51929&r2=51930&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/PassManager.cpp (original) +++ llvm/trunk/lib/VMCore/PassManager.cpp Wed Jun 4 04:13:31 2008 @@ -665,6 +665,11 @@ TPM->collectLastUses(DeadPasses, P); + if (PassDebugging >= Details) { + cerr << " -*- " << P->getPassName(); + cerr << " is the last users of following passes. Free them\n"; + } + for (SmallVector::iterator I = DeadPasses.begin(), E = DeadPasses.end(); I != E; ++I) { From evan.cheng at apple.com Wed Jun 4 04:15:51 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 04 Jun 2008 09:15:51 -0000 Subject: [llvm-commits] [llvm] r51931 - /llvm/trunk/lib/CodeGen/IfConversion.cpp Message-ID: <200806040915.m549FqWZ026145@zion.cs.uiuc.edu> Author: evancheng Date: Wed Jun 4 04:15:51 2008 New Revision: 51931 URL: http://llvm.org/viewvc/llvm-project?rev=51931&view=rev Log: Register if-converter pass for -debug-pass. Modified: llvm/trunk/lib/CodeGen/IfConversion.cpp Modified: llvm/trunk/lib/CodeGen/IfConversion.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/IfConversion.cpp?rev=51931&r1=51930&r2=51931&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/IfConversion.cpp (original) +++ llvm/trunk/lib/CodeGen/IfConversion.cpp Wed Jun 4 04:15:51 2008 @@ -149,7 +149,7 @@ IfConverter() : MachineFunctionPass((intptr_t)&ID) {} virtual bool runOnMachineFunction(MachineFunction &MF); - virtual const char *getPassName() const { return "If converter"; } + virtual const char *getPassName() const { return "If Converter"; } private: bool ReverseBranchCondition(BBInfo &BBI); @@ -215,6 +215,9 @@ char IfConverter::ID = 0; } +static RegisterPass +X("if-converter", "If Converter"); + FunctionPass *llvm::createIfConverterPass() { return new IfConverter(); } bool IfConverter::runOnMachineFunction(MachineFunction &MF) { From evan.cheng at apple.com Wed Jun 4 04:16:33 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 04 Jun 2008 09:16:33 -0000 Subject: [llvm-commits] [llvm] r51932 - in /llvm/trunk/lib/CodeGen: VirtRegMap.cpp VirtRegMap.h Message-ID: <200806040916.m549GXGr026178@zion.cs.uiuc.edu> Author: evancheng Date: Wed Jun 4 04:16:33 2008 New Revision: 51932 URL: http://llvm.org/viewvc/llvm-project?rev=51932&view=rev Log: Move #include to right place. Modified: llvm/trunk/lib/CodeGen/VirtRegMap.cpp llvm/trunk/lib/CodeGen/VirtRegMap.h Modified: llvm/trunk/lib/CodeGen/VirtRegMap.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/VirtRegMap.cpp?rev=51932&r1=51931&r2=51932&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/VirtRegMap.cpp (original) +++ llvm/trunk/lib/CodeGen/VirtRegMap.cpp Wed Jun 4 04:16:33 2008 @@ -29,6 +29,7 @@ #include "llvm/Support/Debug.h" #include "llvm/Support/Compiler.h" #include "llvm/ADT/BitVector.h" +#include "llvm/ADT/DenseMap.h" #include "llvm/ADT/Statistic.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SmallSet.h" Modified: llvm/trunk/lib/CodeGen/VirtRegMap.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/VirtRegMap.h?rev=51932&r1=51931&r2=51932&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/VirtRegMap.h (original) +++ llvm/trunk/lib/CodeGen/VirtRegMap.h Wed Jun 4 04:16:33 2008 @@ -19,7 +19,6 @@ #include "llvm/Target/TargetRegisterInfo.h" #include "llvm/ADT/BitVector.h" -#include "llvm/ADT/DenseMap.h" #include "llvm/ADT/IndexedMap.h" #include "llvm/ADT/SmallPtrSet.h" #include "llvm/Support/Streams.h" From evan.cheng at apple.com Wed Jun 4 04:17:17 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 04 Jun 2008 09:17:17 -0000 Subject: [llvm-commits] [llvm] r51933 - /llvm/trunk/lib/CodeGen/LowerSubregs.cpp Message-ID: <200806040917.m549HHQW026206@zion.cs.uiuc.edu> Author: evancheng Date: Wed Jun 4 04:17:16 2008 New Revision: 51933 URL: http://llvm.org/viewvc/llvm-project?rev=51933&view=rev Log: LowerSubregs should not clobber any analysis. Modified: llvm/trunk/lib/CodeGen/LowerSubregs.cpp Modified: llvm/trunk/lib/CodeGen/LowerSubregs.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LowerSubregs.cpp?rev=51933&r1=51932&r2=51933&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LowerSubregs.cpp (original) +++ llvm/trunk/lib/CodeGen/LowerSubregs.cpp Wed Jun 4 04:17:16 2008 @@ -30,6 +30,10 @@ return "Subregister lowering instruction pass"; } + void getAnalysisUsage(AnalysisUsage &AU) const { + AU.setPreservesAll(); + } + /// runOnMachineFunction - pass entry point bool runOnMachineFunction(MachineFunction&); From evan.cheng at apple.com Wed Jun 4 04:18:42 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 04 Jun 2008 09:18:42 -0000 Subject: [llvm-commits] [llvm] r51934 - in /llvm/trunk: include/llvm/CodeGen/LiveInterval.h include/llvm/CodeGen/LiveStackAnalysis.h include/llvm/CodeGen/MachineFrameInfo.h include/llvm/CodeGen/Passes.h lib/CodeGen/LLVMTargetMachine.cpp lib/CodeGen/LiveInterval.cpp lib/CodeGen/LiveIntervalAnalysis.cpp lib/CodeGen/LiveStackAnalysis.cpp lib/CodeGen/RegAllocLinearScan.cpp lib/CodeGen/StackSlotColoring.cpp Message-ID: <200806040918.m549Ig4X026263@zion.cs.uiuc.edu> Author: evancheng Date: Wed Jun 4 04:18:41 2008 New Revision: 51934 URL: http://llvm.org/viewvc/llvm-project?rev=51934&view=rev Log: Add a stack slot coloring pass. Not yet enabled. Added: llvm/trunk/include/llvm/CodeGen/LiveStackAnalysis.h llvm/trunk/lib/CodeGen/LiveStackAnalysis.cpp llvm/trunk/lib/CodeGen/StackSlotColoring.cpp Modified: llvm/trunk/include/llvm/CodeGen/LiveInterval.h llvm/trunk/include/llvm/CodeGen/MachineFrameInfo.h llvm/trunk/include/llvm/CodeGen/Passes.h llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp llvm/trunk/lib/CodeGen/LiveInterval.cpp llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Modified: llvm/trunk/include/llvm/CodeGen/LiveInterval.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveInterval.h?rev=51934&r1=51933&r2=51934&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/LiveInterval.h (original) +++ llvm/trunk/include/llvm/CodeGen/LiveInterval.h Wed Jun 4 04:18:41 2008 @@ -35,6 +35,7 @@ /// merge point), it contains ~0u,x. If the value number is not in use, it /// contains ~1u,x to indicate that the value # is not used. /// def - Instruction # of the definition. + /// - or reg # of the definition if it's a stack slot liveinterval. /// copy - Copy iff val# is defined by a copy; zero otherwise. /// hasPHIKill - One or more of the kills are PHI nodes. /// kills - Instruction # of the kills. @@ -100,15 +101,16 @@ typedef SmallVector Ranges; typedef SmallVector VNInfoList; - unsigned reg; // the register of this interval + bool isSS; // True if this represents a stack slot + unsigned reg; // the register or stack slot of this interval unsigned preference; // preferred register to allocate for this interval float weight; // weight of this interval Ranges ranges; // the ranges in which this register is live VNInfoList valnos; // value#'s public: - LiveInterval(unsigned Reg, float Weight) - : reg(Reg), preference(0), weight(Weight) { + LiveInterval(unsigned Reg, float Weight, bool IsSS = false) + : isSS(IsSS), reg(Reg), preference(0), weight(Weight) { } typedef Ranges::iterator iterator; @@ -139,6 +141,17 @@ return I; } + /// isStackSlot - Return true if this is a stack slot interval. + /// + bool isStackSlot() const { return isSS; } + + /// getStackSlotIndex - Return stack slot index if this is a stack slot + /// interval. + int getStackSlotIndex() const { + assert(isStackSlot() && "Interval is not a stack slot interval!"); + return reg; + } + bool containsOneValue() const { return valnos.size() == 1; } unsigned getNumValNums() const { return (unsigned)valnos.size(); } @@ -313,6 +326,11 @@ /// FindLiveRangeContaining - Return an iterator to the live range that /// contains the specified index, or end() if there is none. iterator FindLiveRangeContaining(unsigned Idx); + + /// findDefinedVNInfo - Find the VNInfo that's defined at the specified + /// index (register interval) or defined by the specified register (stack + /// inteval). + VNInfo *findDefinedVNInfo(unsigned DefIdxOrReg) const; /// overlaps - Return true if the intersection of the two live intervals is /// not empty. Added: llvm/trunk/include/llvm/CodeGen/LiveStackAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveStackAnalysis.h?rev=51934&view=auto ============================================================================== --- llvm/trunk/include/llvm/CodeGen/LiveStackAnalysis.h (added) +++ llvm/trunk/include/llvm/CodeGen/LiveStackAnalysis.h Wed Jun 4 04:18:41 2008 @@ -0,0 +1,71 @@ +//===-- LiveStackAnalysis.h - Live Stack Slot Analysis ----------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file implements the live stack slot analysis pass. It is analogous to +// live interval analysis except it's analyzing liveness of stack slots rather +// than registers. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CODEGEN_LIVESTACK_ANALYSIS_H +#define LLVM_CODEGEN_LIVESTACK_ANALYSIS_H + +#include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/LiveInterval.h" +#include "llvm/Support/Allocator.h" +#include + +namespace llvm { + + class LiveStacks : public MachineFunctionPass { + /// Special pool allocator for VNInfo's (LiveInterval val#). + /// + BumpPtrAllocator VNInfoAllocator; + + /// s2iMap - Stack slot indices to live interval mapping. + /// + typedef std::map SS2IntervalMap; + SS2IntervalMap s2iMap; + + public: + static char ID; // Pass identification, replacement for typeid + LiveStacks() : MachineFunctionPass((intptr_t)&ID) {} + + typedef SS2IntervalMap::iterator iterator; + typedef SS2IntervalMap::const_iterator const_iterator; + const_iterator begin() const { return s2iMap.begin(); } + const_iterator end() const { return s2iMap.end(); } + iterator begin() { return s2iMap.begin(); } + iterator end() { return s2iMap.end(); } + unsigned getNumIntervals() const { return (unsigned)s2iMap.size(); } + + LiveInterval &getOrCreateInterval(int Slot) { + SS2IntervalMap::iterator I = s2iMap.find(Slot); + if (I == s2iMap.end()) + I = s2iMap.insert(I,std::make_pair(Slot,LiveInterval(Slot,0.0F,true))); + return I->second; + } + + BumpPtrAllocator& getVNInfoAllocator() { return VNInfoAllocator; } + + virtual void getAnalysisUsage(AnalysisUsage &AU) const; + virtual void releaseMemory(); + + /// runOnMachineFunction - pass entry point + virtual bool runOnMachineFunction(MachineFunction&); + + /// print - Implement the dump method. + virtual void print(std::ostream &O, const Module* = 0) const; + void print(std::ostream *O, const Module* M = 0) const { + if (O) print(*O, M); + } + }; +} + +#endif /* LLVM_CODEGEN_LIVESTACK_ANALYSIS_H */ Modified: llvm/trunk/include/llvm/CodeGen/MachineFrameInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineFrameInfo.h?rev=51934&r1=51933&r2=51934&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineFrameInfo.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineFrameInfo.h Wed Jun 4 04:18:41 2008 @@ -195,6 +195,13 @@ /// int getObjectIndexEnd() const { return (int)Objects.size()-NumFixedObjects; } + /// getNumFixedObjects() - Return the number of fixed objects. + unsigned getNumFixedObjects() const { return NumFixedObjects; } + + /// getNumObjects() - Return the number of objects. + /// + unsigned getNumObjects() const { return Objects.size(); } + /// getObjectSize - Return the size of the specified object /// int64_t getObjectSize(int ObjectIdx) const { @@ -203,6 +210,13 @@ return Objects[ObjectIdx+NumFixedObjects].Size; } + // setObjectSize - Change the size of the specified stack object... + void setObjectSize(int ObjectIdx, int64_t Size) { + assert(unsigned(ObjectIdx+NumFixedObjects) < Objects.size() && + "Invalid Object Idx!"); + Objects[ObjectIdx+NumFixedObjects].Size = Size; + } + /// getObjectAlignment - Return the alignment of the specified stack object... unsigned getObjectAlignment(int ObjectIdx) const { assert(unsigned(ObjectIdx+NumFixedObjects) < Objects.size() && @@ -324,12 +338,8 @@ /// RemoveStackObject - Remove or mark dead a statically sized stack object. /// void RemoveStackObject(int ObjectIdx) { - if (ObjectIdx == (int)(Objects.size()-NumFixedObjects-1)) - // Last object, simply pop it off the list. - Objects.pop_back(); - else - // Mark it dead. - Objects[ObjectIdx+NumFixedObjects].Size = ~0ULL; + // Mark it dead. + Objects[ObjectIdx+NumFixedObjects].Size = ~0ULL; } /// CreateVariableSizedObject - Notify the MachineFrameInfo object that a Modified: llvm/trunk/include/llvm/CodeGen/Passes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/Passes.h?rev=51934&r1=51933&r2=51934&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/Passes.h (original) +++ llvm/trunk/include/llvm/CodeGen/Passes.h Wed Jun 4 04:18:41 2008 @@ -172,6 +172,9 @@ /// createMachineSinkingPass - This pass performs sinking on machine /// instructions. FunctionPass *createMachineSinkingPass(); + + /// createStackSlotColoringPass - This pass performs stack slot coloring. + FunctionPass *createStackSlotColoringPass(); } // End llvm namespace Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=51934&r1=51933&r2=51934&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original) +++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Wed Jun 4 04:18:41 2008 @@ -38,12 +38,13 @@ EnableSinking("enable-sinking", cl::init(false), cl::Hidden, cl::desc("Perform sinking on machine code")); static cl::opt -AlignLoops("align-loops", cl::init(true), cl::Hidden, - cl::desc("Align loop headers")); +EnableStackColoring("stack-coloring", + cl::init(true), cl::Hidden, + cl::desc("Perform stack slot coloring")); static cl::opt -PerformLICM("machine-licm", - cl::init(false), cl::Hidden, - cl::desc("Perform loop-invariant code motion on machine code")); +EnableLICM("machine-licm", + cl::init(false), cl::Hidden, + cl::desc("Perform loop-invariant code motion on machine code")); // When this works it will be on by default. static cl::opt @@ -88,7 +89,7 @@ if (PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); - if (PerformLICM) + if (EnableLICM) PM.add(createMachineLICMPass()); if (EnableSinking) @@ -101,21 +102,28 @@ // Perform register allocation to convert to a concrete x86 representation PM.add(createRegisterAllocator()); - if (PrintMachineCode) + // Perform stack slot coloring. + if (EnableStackColoring) + PM.add(createStackSlotColoringPass()); + + if (PrintMachineCode) // Print the register-allocated code PM.add(createMachineFunctionPrinterPass(cerr)); - - PM.add(createLowerSubregsPass()); - if (PrintMachineCode) // Print the subreg lowered code - PM.add(createMachineFunctionPrinterPass(cerr)); - // Run post-ra passes. if (addPostRegAlloc(PM, Fast) && PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); + PM.add(createLowerSubregsPass()); + + if (PrintMachineCode) // Print the subreg lowered code + PM.add(createMachineFunctionPrinterPass(cerr)); + // Insert prolog/epilog code. Eliminate abstract frame index references... PM.add(createPrologEpilogCodeInserter()); + if (PrintMachineCode) + PM.add(createMachineFunctionPrinterPass(cerr)); + // Second pass scheduler. if (!Fast && !DisablePostRAScheduler) PM.add(createPostRAScheduler()); @@ -140,7 +148,7 @@ if (addPreEmitPass(PM, Fast) && PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); - if (AlignLoops && !Fast && !OptimizeForSize) + if (!Fast && !OptimizeForSize) PM.add(createLoopAlignerPass()); switch (FileType) { @@ -218,7 +226,7 @@ if (PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); - if (PerformLICM) + if (EnableLICM) PM.add(createMachineLICMPass()); if (EnableSinking) @@ -228,25 +236,32 @@ if (addPreRegAlloc(PM, Fast) && PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); - // Perform register allocation to convert to a concrete x86 representation + // Perform register allocation. PM.add(createRegisterAllocator()); - + + // Perform stack slot coloring. + if (EnableStackColoring) + PM.add(createStackSlotColoringPass()); + if (PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); + // Run post-ra passes. + if (addPostRegAlloc(PM, Fast) && PrintMachineCode) + PM.add(createMachineFunctionPrinterPass(cerr)); + + if (PrintMachineCode) // Print the register-allocated code + PM.add(createMachineFunctionPrinterPass(cerr)); + PM.add(createLowerSubregsPass()); if (PrintMachineCode) // Print the subreg lowered code PM.add(createMachineFunctionPrinterPass(cerr)); - // Run post-ra passes. - if (addPostRegAlloc(PM, Fast) && PrintMachineCode) - PM.add(createMachineFunctionPrinterPass(cerr)); - // Insert prolog/epilog code. Eliminate abstract frame index references... PM.add(createPrologEpilogCodeInserter()); - if (PrintMachineCode) // Print the register-allocated code + if (PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); // Second pass scheduler. @@ -258,6 +273,7 @@ PM.add(createBranchFoldingPass(getEnableTailMergeDefault())); PM.add(createGCMachineCodeAnalysisPass()); + if (PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); Modified: llvm/trunk/lib/CodeGen/LiveInterval.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveInterval.cpp?rev=51934&r1=51933&r2=51934&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveInterval.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveInterval.cpp Wed Jun 4 04:18:41 2008 @@ -358,6 +358,20 @@ return end(); } +/// findDefinedVNInfo - Find the VNInfo that's defined at the specified index +/// (register interval) or defined by the specified register (stack inteval). +VNInfo *LiveInterval::findDefinedVNInfo(unsigned DefIdxOrReg) const { + VNInfo *VNI = NULL; + for (LiveInterval::const_vni_iterator i = vni_begin(), e = vni_end(); + i != e; ++i) + if ((*i)->def == DefIdxOrReg) { + VNI = *i; + break; + } + return VNI; +} + + /// join - Join two live intervals (this, and other) together. This applies /// mappings to the value numbers in the LHS/RHS intervals as specified. If /// the intervals are not joinable, this aborts. @@ -664,7 +678,9 @@ void LiveInterval::print(std::ostream &OS, const TargetRegisterInfo *TRI) const { - if (TRI && TargetRegisterInfo::isPhysicalRegister(reg)) + if (isSS) + OS << "SS#" << reg; + else if (TRI && TargetRegisterInfo::isPhysicalRegister(reg)) OS << TRI->getName(reg); else OS << "%reg" << reg; @@ -672,7 +688,7 @@ OS << ',' << weight; if (empty()) - OS << "EMPTY"; + OS << " EMPTY"; else { OS << " = "; for (LiveInterval::Ranges::const_iterator I = ranges.begin(), Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=51934&r1=51933&r2=51934&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Wed Jun 4 04:18:41 2008 @@ -65,6 +65,7 @@ } void LiveIntervals::releaseMemory() { + MBB2IdxMap.clear(); Idx2MBBMap.clear(); mi2iMap_.clear(); i2miMap_.clear(); @@ -229,8 +230,8 @@ void LiveIntervals::print(std::ostream &O, const Module* ) const { O << "********** INTERVALS **********\n"; for (const_iterator I = begin(), E = end(); I != E; ++I) { - I->second.print(DOUT, tri_); - DOUT << "\n"; + I->second.print(O, tri_); + O << "\n"; } O << "********** MACHINEINSTRS **********\n"; @@ -1160,17 +1161,6 @@ return false; } -static const VNInfo *findDefinedVNInfo(const LiveInterval &li, unsigned DefIdx) { - const VNInfo *VNI = NULL; - for (LiveInterval::const_vni_iterator i = li.vni_begin(), - e = li.vni_end(); i != e; ++i) - if ((*i)->def == DefIdx) { - VNI = *i; - break; - } - return VNI; -} - /// RewriteInfo - Keep track of machine instrs that will be rewritten /// during spilling. namespace { @@ -1318,7 +1308,7 @@ HasKill = anyKillInMBBAfterIdx(li, I->valno, MBB, getDefIndex(index)); else { // If this is a two-address code, then this index starts a new VNInfo. - const VNInfo *VNI = findDefinedVNInfo(li, getDefIndex(index)); + const VNInfo *VNI = li.findDefinedVNInfo(getDefIndex(index)); if (VNI) HasKill = anyKillInMBBAfterIdx(li, VNI, MBB, getDefIndex(index)); } Added: llvm/trunk/lib/CodeGen/LiveStackAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveStackAnalysis.cpp?rev=51934&view=auto ============================================================================== --- llvm/trunk/lib/CodeGen/LiveStackAnalysis.cpp (added) +++ llvm/trunk/lib/CodeGen/LiveStackAnalysis.cpp Wed Jun 4 04:18:41 2008 @@ -0,0 +1,50 @@ +//===-- LiveStackAnalysis.cpp - Live Stack Slot Analysis ------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file implements the live stack slot analysis pass. It is analogous to +// live interval analysis except it's analyzing liveness of stack slots rather +// than registers. +// +//===----------------------------------------------------------------------===// + +#define DEBUG_TYPE "livestacks" +#include "llvm/CodeGen/LiveStackAnalysis.h" +#include "llvm/CodeGen/Passes.h" +#include "llvm/Target/TargetRegisterInfo.h" +#include "llvm/Support/Debug.h" +#include "llvm/ADT/Statistic.h" +using namespace llvm; + +char LiveStacks::ID = 0; +static RegisterPass X("livestacks", "Live Stack Slot Analysis"); + +void LiveStacks::getAnalysisUsage(AnalysisUsage &AU) const { + AU.setPreservesAll(); +} + +void LiveStacks::releaseMemory() { + // Release VNInfo memroy regions after all VNInfo objects are dtor'd. + VNInfoAllocator.Reset(); + s2iMap.clear(); +} + +bool LiveStacks::runOnMachineFunction(MachineFunction &) { + // FIXME: No analysis is being done right now. We are relying on the + // register allocators to provide the information. + return false; +} + +/// print - Implement the dump method. +void LiveStacks::print(std::ostream &O, const Module* ) const { + O << "********** INTERVALS **********\n"; + for (const_iterator I = begin(), E = end(); I != E; ++I) { + I->second.print(O); + O << "\n"; + } +} Modified: llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp?rev=51934&r1=51933&r2=51934&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Wed Jun 4 04:18:41 2008 @@ -12,10 +12,11 @@ //===----------------------------------------------------------------------===// #define DEBUG_TYPE "regalloc" -#include "llvm/CodeGen/LiveIntervalAnalysis.h" #include "PhysRegTracker.h" #include "VirtRegMap.h" #include "llvm/Function.h" +#include "llvm/CodeGen/LiveIntervalAnalysis.h" +#include "llvm/CodeGen/LiveStackAnalysis.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineLoopInfo.h" @@ -67,6 +68,7 @@ MachineRegisterInfo *reginfo_; BitVector allocatableRegs_; LiveIntervals* li_; + LiveStacks* ls_; const MachineLoopInfo *loopInfo; /// handled_ - Intervals are added to the handled_ set in the order of their @@ -103,6 +105,8 @@ // Make sure PassManager knows which analyses to make available // to coalescing and which analyses coalescing invalidates. AU.addRequiredTransitive(); + AU.addRequired(); + AU.addPreserved(); AU.addRequired(); AU.addPreserved(); AU.addPreservedID(MachineDominatorsID); @@ -171,6 +175,9 @@ char RALinScan::ID = 0; } +static RegisterPass +X("linearscan-regalloc", "Linear Scan Register Allocator"); + void RALinScan::ComputeRelatedRegClasses() { const TargetRegisterInfo &TRI = *tri_; @@ -258,6 +265,7 @@ reginfo_ = &mf_->getRegInfo(); allocatableRegs_ = tri_->getAllocatableSet(fn); li_ = &getAnalysis(); + ls_ = &getAnalysis(); loopInfo = &getAnalysis(); // We don't run the coalescer here because we have no reason to @@ -504,6 +512,26 @@ } } +/// addStackInterval - Create a LiveInterval for stack if the specified live +/// interval has been spilled. +static void addStackInterval(LiveInterval *cur, LiveStacks *ls_, + LiveIntervals *li_, VirtRegMap &vrm_) { + int SS = vrm_.getStackSlot(cur->reg); + if (SS == VirtRegMap::NO_STACK_SLOT) + return; + LiveInterval &SI = ls_->getOrCreateInterval(SS); + VNInfo *VNI; + if (SI.getNumValNums()) + VNI = SI.getValNumInfo(0); + else + VNI = SI.getNextValue(~0U, 0, ls_->getVNInfoAllocator()); + + LiveInterval &RI = li_->getInterval(cur->reg); + // FIXME: This may be overly conservative. + SI.MergeRangesInAsValue(RI, VNI); + SI.weight += RI.weight; +} + /// assignRegOrStackSlotAtInterval - assign a register if one is available, or /// spill. void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) @@ -717,6 +745,7 @@ DOUT << "\t\t\tspilling(c): " << *cur << '\n'; std::vector added = li_->addIntervalsForSpills(*cur, loopInfo, *vrm_); + addStackInterval(cur, ls_, li_, *vrm_); if (added.empty()) return; // Early exit if all spills were folded. @@ -769,6 +798,7 @@ earliestStart = std::min(earliestStart, i->first->beginNumber()); std::vector newIs = li_->addIntervalsForSpills(*i->first, loopInfo, *vrm_); + addStackInterval(i->first, ls_, li_, *vrm_); std::copy(newIs.begin(), newIs.end(), std::back_inserter(added)); spilled.insert(reg); } @@ -782,6 +812,7 @@ earliestStart = std::min(earliestStart, i->first->beginNumber()); std::vector newIs = li_->addIntervalsForSpills(*i->first, loopInfo, *vrm_); + addStackInterval(i->first, ls_, li_, *vrm_); std::copy(newIs.begin(), newIs.end(), std::back_inserter(added)); spilled.insert(reg); } Added: llvm/trunk/lib/CodeGen/StackSlotColoring.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/StackSlotColoring.cpp?rev=51934&view=auto ============================================================================== --- llvm/trunk/lib/CodeGen/StackSlotColoring.cpp (added) +++ llvm/trunk/lib/CodeGen/StackSlotColoring.cpp Wed Jun 4 04:18:41 2008 @@ -0,0 +1,271 @@ +//===-- StackSlotColoring.cpp - Sinking for machine instructions ----------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file implements the stack slot coloring pass. +// +//===----------------------------------------------------------------------===// + +#define DEBUG_TYPE "stackcoloring" +#include "llvm/CodeGen/LiveStackAnalysis.h" +#include "llvm/CodeGen/MachineFrameInfo.h" +#include "llvm/CodeGen/Passes.h" +#include "llvm/Support/CommandLine.h" +#include "llvm/Support/Compiler.h" +#include "llvm/Support/Debug.h" +#include "llvm/ADT/BitVector.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/Statistic.h" +#include +using namespace llvm; + +static cl::opt +DisableSharing("no-stack-slot-sharing", + cl::init(false), cl::Hidden, + cl::desc("Surpress slot sharing during stack coloring")); + +static cl::opt +DeleteLimit("slot-delete-limit", cl::init(-1), cl::Hidden, + cl::desc("Stack coloring slot deletion limit")); + +STATISTIC(NumEliminated, "Number of stack slots eliminated due to coloring"); + +namespace { + class VISIBILITY_HIDDEN StackSlotColoring : public MachineFunctionPass { + LiveStacks* LS; + MachineFrameInfo *MFI; + + // SSIntervals - Spill slot intervals. + std::vector SSIntervals; + + // OrigAlignments - Alignments of stack objects before coloring. + SmallVector OrigAlignments; + + // OrigSizes - Sizess of stack objects before coloring. + SmallVector OrigSizes; + + // AllColors - If index is set, it's a spill slot, i.e. color. + // FIXME: This assumes PEI locate spill slot with smaller indices + // closest to stack pointer / frame pointer. Therefore, smaller + // index == better color. + BitVector AllColors; + + // NextColor - Next "color" that's not yet used. + int NextColor; + + // UsedColors - "Colors" that have been assigned. + BitVector UsedColors; + + // Assignments - Color to intervals mapping. + SmallVector,16> Assignments; + + public: + static char ID; // Pass identification + StackSlotColoring() : MachineFunctionPass((intptr_t)&ID), NextColor(-1) {} + + virtual void getAnalysisUsage(AnalysisUsage &AU) const { + AU.addRequired(); + MachineFunctionPass::getAnalysisUsage(AU); + } + + virtual bool runOnMachineFunction(MachineFunction &MF); + virtual const char* getPassName() const { + return "Stack Slot Coloring"; + } + + private: + bool InitializeSlots(); + bool OverlapWithAssignments(LiveInterval *li, int Color) const; + int ColorSlot(LiveInterval *li); + bool ColorSlots(MachineFunction &MF); + }; +} // end anonymous namespace + +char StackSlotColoring::ID = 0; + +static RegisterPass +X("stack-slot-coloring", "Stack Slot Coloring"); + +FunctionPass *llvm::createStackSlotColoringPass() { + return new StackSlotColoring(); +} + +namespace { + // IntervalSorter - Comparison predicate that sort live intervals by + // their weight. + struct IntervalSorter { + bool operator()(LiveInterval* LHS, LiveInterval* RHS) const { + return LHS->weight > RHS->weight; + } + }; +} + +/// InitializeSlots - Process all spill stack slot liveintervals and add them +/// to a sorted (by weight) list. +bool StackSlotColoring::InitializeSlots() { + if (LS->getNumIntervals() < 2) + return false; + + int LastFI = MFI->getObjectIndexEnd(); + OrigAlignments.resize(LastFI); + OrigSizes.resize(LastFI); + AllColors.resize(LastFI); + UsedColors.resize(LastFI); + Assignments.resize(LastFI); + + // Gather all spill slots into a list. + for (LiveStacks::iterator i = LS->begin(), e = LS->end(); i != e; ++i) { + LiveInterval &li = i->second; + int FI = li.getStackSlotIndex(); + if (MFI->isDeadObjectIndex(FI)) + continue; + SSIntervals.push_back(&li); + OrigAlignments[FI] = MFI->getObjectAlignment(FI); + OrigSizes[FI] = MFI->getObjectSize(FI); + AllColors.set(FI); + } + + // Sort them by weight. + std::stable_sort(SSIntervals.begin(), SSIntervals.end(), IntervalSorter()); + + // Get first "color". + NextColor = AllColors.find_first(); + return true; +} + +/// OverlapWithAssignments - Return true if LiveInterval overlaps with any +/// LiveIntervals that have already been assigned to the specified color. +bool +StackSlotColoring::OverlapWithAssignments(LiveInterval *li, int Color) const { + const SmallVector &OtherLIs = Assignments[Color]; + for (unsigned i = 0, e = OtherLIs.size(); i != e; ++i) { + LiveInterval *OtherLI = OtherLIs[i]; + if (OtherLI->overlaps(*li)) + return true; + } + return false; +} + +/// ColorSlot - Assign a "color" (stack slot) to the specified stack slot. +/// +int StackSlotColoring::ColorSlot(LiveInterval *li) { + int Color = -1; + bool Share = false; + if (!DisableSharing && + (DeleteLimit == -1 || (int)NumEliminated < DeleteLimit)) { + // Check if it's possible to reuse any of the used colors. + Color = UsedColors.find_first(); + while (Color != -1) { + if (!OverlapWithAssignments(li, Color)) { + Share = true; + ++NumEliminated; + break; + } + Color = UsedColors.find_next(Color); + } + } + + // Assign it to the first available color (assumed to be the best) if it's + // not possible to share a used color with other objects. + if (!Share) { + assert(NextColor != -1 && "No more spill slots?"); + Color = NextColor; + UsedColors.set(Color); + NextColor = AllColors.find_next(NextColor); + } + + // Record the assignment. + Assignments[Color].push_back(li); + int FI = li->getStackSlotIndex(); + DOUT << "Assigning fi #" << FI << " to fi #" << Color << "\n"; + + // Change size and alignment of the allocated slot. If there are multiple + // objects sharing the same slot, then make sure the size and alignment + // are large enough for all. + unsigned Align = OrigAlignments[FI]; + if (!Share || Align > MFI->getObjectAlignment(Color)) + MFI->setObjectAlignment(Color, Align); + int64_t Size = OrigSizes[FI]; + if (!Share || Size > MFI->getObjectSize(Color)) + MFI->setObjectSize(Color, Size); + return Color; +} + +/// Colorslots - Color all spill stack slots and rewrite all frameindex machine +/// operands in the function. +bool StackSlotColoring::ColorSlots(MachineFunction &MF) { + unsigned NumObjs = MFI->getObjectIndexEnd(); + std::vector SlotMapping(NumObjs, -1); + SlotMapping.resize(NumObjs, -1); + + bool Changed = false; + for (unsigned i = 0, e = SSIntervals.size(); i != e; ++i) { + LiveInterval *li = SSIntervals[i]; + int SS = li->getStackSlotIndex(); + int NewSS = ColorSlot(li); + SlotMapping[SS] = NewSS; + Changed |= (SS != NewSS); + } + + if (!Changed) + return false; + + // Rewrite all MO_FrameIndex operands. + // FIXME: Need the equivalent of MachineRegisterInfo for frameindex operands. + for (MachineFunction::iterator MBB = MF.begin(), E = MF.end(); + MBB != E; ++MBB) { + for (MachineBasicBlock::iterator MII = MBB->begin(), EE = MBB->end(); + MII != EE; ++MII) { + MachineInstr &MI = *MII; + for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { + MachineOperand &MO = MI.getOperand(i); + if (!MO.isFrameIndex()) + continue; + int FI = MO.getIndex(); + if (FI < 0) + continue; + FI = SlotMapping[FI]; + if (FI == -1) + continue; + MO.setIndex(FI); + } + } + } + + // Delete unused stack slots. + while (NextColor != -1) { + DOUT << "Removing unused stack object fi #" << NextColor << "\n"; + MFI->RemoveStackObject(NextColor); + NextColor = AllColors.find_next(NextColor); + } + + return true; +} + +bool StackSlotColoring::runOnMachineFunction(MachineFunction &MF) { + DOUT << "******** Stack Slot Coloring ********\n"; + + MFI = MF.getFrameInfo(); + LS = &getAnalysis(); + + bool Changed = false; + if (InitializeSlots()) + Changed = ColorSlots(MF); + + NextColor = -1; + SSIntervals.clear(); + OrigAlignments.clear(); + OrigSizes.clear(); + AllColors.clear(); + UsedColors.clear(); + for (unsigned i = 0, e = Assignments.size(); i != e; ++i) + Assignments[i].clear(); + Assignments.clear(); + + return Changed; +} From evan.cheng at apple.com Wed Jun 4 04:21:46 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 04 Jun 2008 09:21:46 -0000 Subject: [llvm-commits] [test-suite] r51935 - /test-suite/trunk/Makefile.programs Message-ID: <200806040921.m549LkFv026367@zion.cs.uiuc.edu> Author: evancheng Date: Wed Jun 4 04:21:46 2008 New Revision: 51935 URL: http://llvm.org/viewvc/llvm-project?rev=51935&view=rev Log: Try stack coloring as llcbeta for x86 and ARM. Modified: test-suite/trunk/Makefile.programs Modified: test-suite/trunk/Makefile.programs URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/Makefile.programs?rev=51935&r1=51934&r2=51935&view=diff ============================================================================== --- test-suite/trunk/Makefile.programs (original) +++ test-suite/trunk/Makefile.programs Wed Jun 4 04:21:46 2008 @@ -207,7 +207,6 @@ ifeq ($(ARCH),PowerPC) LLCBETAOPTION := -enable-sinking #-machine-licm -#-coalescer-commute-instrs #--enable-tail-merge #--enable-ppc-preinc #-regalloc=local -fast @@ -220,15 +219,13 @@ LLCBETAOPTION := -sched=simple endif ifeq ($(ARCH),x86) -LLCBETAOPTION := -schedule-livein-copies -#-align-loops=false +LLCBETAOPTION := -stack-coloring +#-schedule-livein-copies #-enable-sinking -#-coalescer-commute-instrs #-machine-licm #-new-coalescer-heuristic=true #-tailcallopt #-regalloc=local -fast -#-disable-rematerialization #-disable-fp-elim #-regalloc=bigblock -fast endif @@ -236,11 +233,10 @@ LLCBETAOPTION := -enable-sparc-v9-insts endif ifeq ($(ARCH),ARM) -LLCBETAOPTION := -schedule-livein-copies +LLCBETAOPTION := -stack-coloring +#-schedule-livein-copies #-enable-sinking -#-coalescer-commute-instrs #-new-coalescer-heuristic=true -#-disable-rematerialization #-march=thumb endif ifeq ($(ARCH),THUMB) From matthijs at stdin.nl Wed Jun 4 09:40:56 2008 From: matthijs at stdin.nl (Matthijs Kooijman) Date: Wed, 04 Jun 2008 14:40:56 -0000 Subject: [llvm-commits] [llvm] r51937 - in /llvm/trunk: include/llvm/Instructions.h lib/VMCore/Instructions.cpp Message-ID: <200806041440.m54EeuB2003772@zion.cs.uiuc.edu> Author: matthijs Date: Wed Jun 4 09:40:55 2008 New Revision: 51937 URL: http://llvm.org/viewvc/llvm-project?rev=51937&view=rev Log: Implement the two constructors in InsertValueInst and ExtractValueInst. Add a Name argment to two init methods in these classes as well to make things a bit more consistent. Modified: llvm/trunk/include/llvm/Instructions.h llvm/trunk/lib/VMCore/Instructions.cpp Modified: llvm/trunk/include/llvm/Instructions.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructions.h?rev=51937&r1=51936&r2=51937&view=diff ============================================================================== --- llvm/trunk/include/llvm/Instructions.h (original) +++ llvm/trunk/include/llvm/Instructions.h Wed Jun 4 09:40:55 2008 @@ -1458,8 +1458,8 @@ SmallVector Indices; ExtractValueInst(const ExtractValueInst &EVI); - void init(Value *Agg, const unsigned *Idx, unsigned NumIdx); - void init(Value *Agg, unsigned Idx); + void init(Value *Agg, const unsigned *Idx, unsigned NumIdx, const std::string &Name); + void init(Value *Agg, unsigned Idx, const std::string &Name); template void init(Value *Agg, InputIterator IdxBegin, InputIterator IdxEnd, @@ -1476,10 +1476,8 @@ assert(NumIdx > 0 && "ExtractValueInst must have at least one index"); // This requires that the iterator points to contiguous memory. - init(Agg, &*IdxBegin, NumIdx); // FIXME: for the general case - // we have to build an array here - - setName(Name); + init(Agg, &*IdxBegin, NumIdx, Name); // FIXME: for the general case + // we have to build an array here } /// getIndexedType - Returns the type of the element that would be extracted @@ -1667,8 +1665,8 @@ void *operator new(size_t, unsigned); // Do not implement InsertValueInst(const InsertValueInst &IVI); - void init(Value *Agg, Value *Val, const unsigned *Idx, unsigned NumIdx); - void init(Value *Agg, Value *Val, unsigned Idx); + void init(Value *Agg, Value *Val, const unsigned *Idx, unsigned NumIdx, const std::string &Name); + void init(Value *Agg, Value *Val, unsigned Idx, const std::string &Name); template void init(Value *Agg, Value *Val, @@ -1686,10 +1684,8 @@ assert(NumIdx > 0 && "InsertValueInst must have at least one index"); // This requires that the iterator points to contiguous memory. - init(Agg, Val, &*IdxBegin, NumIdx); // FIXME: for the general case - // we have to build an array here - - setName(Name); + init(Agg, Val, &*IdxBegin, NumIdx, Name); // FIXME: for the general case + // we have to build an array here } /// Constructors - Create a insertvalue instruction with a base aggregate Modified: llvm/trunk/lib/VMCore/Instructions.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instructions.cpp?rev=51937&r1=51936&r2=51937&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Instructions.cpp (original) +++ llvm/trunk/lib/VMCore/Instructions.cpp Wed Jun 4 09:40:55 2008 @@ -1350,21 +1350,24 @@ // InsertValueInst Class //===----------------------------------------------------------------------===// -void InsertValueInst::init(Value *Agg, Value *Val, - const unsigned *Idx, unsigned NumIdx) { +void InsertValueInst::init(Value *Agg, Value *Val, const unsigned *Idx, + unsigned NumIdx, const std::string &Name) { assert(NumOperands == 2 && "NumOperands not initialized?"); Op<0>() = Agg; Op<1>() = Val; Indices.insert(Indices.end(), Idx, Idx + NumIdx); + setName(Name); } -void InsertValueInst::init(Value *Agg, Value *Val, unsigned Idx) { +void InsertValueInst::init(Value *Agg, Value *Val, unsigned Idx, + const std::string &Name) { assert(NumOperands == 2 && "NumOperands not initialized?"); Op<0>() = Agg; Op<1>() = Val; Indices.push_back(Idx); + setName(Name); } InsertValueInst::InsertValueInst(const InsertValueInst &IVI) @@ -1373,22 +1376,46 @@ Indices(IVI.Indices) { } +InsertValueInst::InsertValueInst(Value *Agg, + Value *Val, + unsigned Idx, + const std::string &Name, + Instruction *InsertBefore) + : Instruction(Agg->getType(), InsertValue, + OperandTraits::op_begin(this), + 2, InsertBefore) { + init(Agg, Val, Idx, Name); +} + +InsertValueInst::InsertValueInst(Value *Agg, + Value *Val, + unsigned Idx, + const std::string &Name, + BasicBlock *InsertAtEnd) + : Instruction(Agg->getType(), InsertValue, + OperandTraits::op_begin(this), + 2, InsertAtEnd) { + init(Agg, Val, Idx, Name); +} + //===----------------------------------------------------------------------===// // ExtractValueInst Class //===----------------------------------------------------------------------===// -void ExtractValueInst::init(Value *Agg, const unsigned *Idx, unsigned NumIdx) { +void ExtractValueInst::init(Value *Agg, const unsigned *Idx, unsigned NumIdx, const std::string &Name) { assert(NumOperands == 1 && "NumOperands not initialized?"); Op<0>() = Agg; Indices.insert(Indices.end(), Idx, Idx + NumIdx); + setName(Name); } -void ExtractValueInst::init(Value *Agg, unsigned Idx) { +void ExtractValueInst::init(Value *Agg, unsigned Idx, const std::string &Name) { assert(NumOperands == 1 && "NumOperands not initialized?"); Op<0>() = Agg; Indices.push_back(Idx); + setName(Name); } ExtractValueInst::ExtractValueInst(const ExtractValueInst &EVI) @@ -1424,6 +1451,28 @@ return CurIdx == NumIdx ? Agg : 0; } +ExtractValueInst::ExtractValueInst(Value *Agg, + unsigned Idx, + const std::string &Name, + BasicBlock *InsertAtEnd) + : Instruction(checkType(getIndexedType(Agg->getType(), &Idx, 1)), + ExtractValue, + OperandTraits::op_begin(this), + 1, InsertAtEnd) { + init(Agg, Idx, Name); +} + +ExtractValueInst::ExtractValueInst(Value *Agg, + unsigned Idx, + const std::string &Name, + Instruction *InsertBefore) + : Instruction(checkType(getIndexedType(Agg->getType(), &Idx, 1)), + ExtractValue, + OperandTraits::op_begin(this), + 1, InsertBefore) { + init(Agg, Idx, Name); +} + //===----------------------------------------------------------------------===// // BinaryOperator Class //===----------------------------------------------------------------------===// From nicolas.geoffray at lip6.fr Wed Jun 4 10:24:57 2008 From: nicolas.geoffray at lip6.fr (Nicolas Geoffray) Date: Wed, 04 Jun 2008 15:24:57 -0000 Subject: [llvm-commits] [vmkit] r51940 - /vmkit/trunk/lib/JnJVM/VMCore/Jnjvm.h Message-ID: <200806041524.m54FOvBO005111@zion.cs.uiuc.edu> Author: geoffray Date: Wed Jun 4 10:24:56 2008 New Revision: 51940 URL: http://llvm.org/viewvc/llvm-project?rev=51940&view=rev Log: Attribut objects are not GC allocated. Modified: vmkit/trunk/lib/JnJVM/VMCore/Jnjvm.h Modified: vmkit/trunk/lib/JnJVM/VMCore/Jnjvm.h URL: http://llvm.org/viewvc/llvm-project/vmkit/trunk/lib/JnJVM/VMCore/Jnjvm.h?rev=51940&r1=51939&r2=51940&view=diff ============================================================================== --- vmkit/trunk/lib/JnJVM/VMCore/Jnjvm.h (original) +++ vmkit/trunk/lib/JnJVM/VMCore/Jnjvm.h Wed Jun 4 10:24:56 2008 @@ -192,8 +192,7 @@ void readParents(Class* cl, Reader& reader); void loadParents(Class* cl); - void readAttributs(Class* cl, Reader& reader, - std::vector > & attr); + void readAttributs(Class* cl, Reader& reader, std::vector & attr); void readFields(Class* cl, Reader& reader); void readMethods(Class* cl, Reader& reader); void readClass(Class* cl); From clattner at apple.com Wed Jun 4 10:27:26 2008 From: clattner at apple.com (Chris Lattner) Date: Wed, 4 Jun 2008 08:27:26 -0700 Subject: [llvm-commits] [llvm] r51933 - /llvm/trunk/lib/CodeGen/LowerSubregs.cpp In-Reply-To: <200806040917.m549HHQW026206@zion.cs.uiuc.edu> References: <200806040917.m549HHQW026206@zion.cs.uiuc.edu> Message-ID: <012C137B-A859-486F-985B-57BA4538C3F3@apple.com> On Jun 4, 2008, at 2:17 AM, Evan Cheng wrote: > Author: evancheng > Date: Wed Jun 4 04:17:16 2008 > New Revision: 51933 > > URL: http://llvm.org/viewvc/llvm-project?rev=51933&view=rev > Log: > LowerSubregs should not clobber any analysis. Hey Evan, Passes should only set this if they make no changes to the code at all. Please just preserve the specific passes that you know are safe for lower subregs. -Chris > > > Modified: > llvm/trunk/lib/CodeGen/LowerSubregs.cpp > > Modified: llvm/trunk/lib/CodeGen/LowerSubregs.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LowerSubregs.cpp?rev=51933&r1=51932&r2=51933&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/CodeGen/LowerSubregs.cpp (original) > +++ llvm/trunk/lib/CodeGen/LowerSubregs.cpp Wed Jun 4 04:17:16 2008 > @@ -30,6 +30,10 @@ > return "Subregister lowering instruction pass"; > } > > + void getAnalysisUsage(AnalysisUsage &AU) const { > + AU.setPreservesAll(); > + } > + > /// runOnMachineFunction - pass entry point > bool runOnMachineFunction(MachineFunction&); > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From matthijs at stdin.nl Wed Jun 4 10:46:35 2008 From: matthijs at stdin.nl (Matthijs Kooijman) Date: Wed, 04 Jun 2008 15:46:35 -0000 Subject: [llvm-commits] [llvm] r51942 - /llvm/trunk/docs/CodeGenerator.html Message-ID: <200806041546.m54FkZkp005727@zion.cs.uiuc.edu> Author: matthijs Date: Wed Jun 4 10:46:35 2008 New Revision: 51942 URL: http://llvm.org/viewvc/llvm-project?rev=51942&view=rev Log: Fix example to be valid LLVM assembly. Modified: llvm/trunk/docs/CodeGenerator.html Modified: llvm/trunk/docs/CodeGenerator.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CodeGenerator.html?rev=51942&r1=51941&r2=51942&view=diff ============================================================================== --- llvm/trunk/docs/CodeGenerator.html (original) +++ llvm/trunk/docs/CodeGenerator.html Wed Jun 4 10:46:35 2008 @@ -621,9 +621,9 @@ 
-int %test(int %X, int %Y) {
-  %Z = div int %X, %Y
-  ret int %Z
+define i32 @test(i32 %X, i32 %Y) {
+  %Z = udiv i32 %X, %Y
+  ret i32 %Z
 }
From matthijs at stdin.nl Wed Jun 4 11:14:12 2008 From: matthijs at stdin.nl (Matthijs Kooijman) Date: Wed, 04 Jun 2008 16:14:12 -0000 Subject: [llvm-commits] [llvm] r51945 - in /llvm/trunk: include/llvm/Instructions.h lib/VMCore/Instructions.cpp Message-ID: <200806041614.m54GECVN006685@zion.cs.uiuc.edu> Author: matthijs Date: Wed Jun 4 11:14:12 2008 New Revision: 51945 URL: http://llvm.org/viewvc/llvm-project?rev=51945&view=rev Log: Add a Name parameter to two of the init methods of GetElementPointer to make the name setting more consistent. Modified: llvm/trunk/include/llvm/Instructions.h llvm/trunk/lib/VMCore/Instructions.cpp Modified: llvm/trunk/include/llvm/Instructions.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructions.h?rev=51945&r1=51944&r2=51945&view=diff ============================================================================== --- llvm/trunk/include/llvm/Instructions.h (original) +++ llvm/trunk/include/llvm/Instructions.h Wed Jun 4 11:14:12 2008 @@ -379,8 +379,8 @@ /// class GetElementPtrInst : public Instruction { GetElementPtrInst(const GetElementPtrInst &GEPI); - void init(Value *Ptr, Value* const *Idx, unsigned NumIdx); - void init(Value *Ptr, Value *Idx); + void init(Value *Ptr, Value* const *Idx, unsigned NumIdx, const std::string &Name); + void init(Value *Ptr, Value *Idx, const std::string &Name); template void init(Value *Ptr, InputIterator IdxBegin, InputIterator IdxEnd, @@ -392,14 +392,12 @@ if (NumIdx > 0) { // This requires that the iterator points to contiguous memory. - init(Ptr, &*IdxBegin, NumIdx); // FIXME: for the general case + init(Ptr, &*IdxBegin, NumIdx, Name); // FIXME: for the general case // we have to build an array here } else { - init(Ptr, 0, NumIdx); + init(Ptr, 0, NumIdx, Name); } - - setName(Name); } /// getIndexedType - Returns the type of the element that would be loaded with Modified: llvm/trunk/lib/VMCore/Instructions.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instructions.cpp?rev=51945&r1=51944&r2=51945&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Instructions.cpp (original) +++ llvm/trunk/lib/VMCore/Instructions.cpp Wed Jun 4 11:14:12 2008 @@ -992,20 +992,24 @@ return cast(Val->getType())->getAddressSpace(); } -void GetElementPtrInst::init(Value *Ptr, Value* const *Idx, unsigned NumIdx) { +void GetElementPtrInst::init(Value *Ptr, Value* const *Idx, unsigned NumIdx, const std::string &Name) { assert(NumOperands == 1+NumIdx && "NumOperands not initialized?"); Use *OL = OperandList; OL[0] = Ptr; for (unsigned i = 0; i != NumIdx; ++i) OL[i+1] = Idx[i]; + + setName(Name); } -void GetElementPtrInst::init(Value *Ptr, Value *Idx) { +void GetElementPtrInst::init(Value *Ptr, Value *Idx, const std::string &Name) { assert(NumOperands == 2 && "NumOperands not initialized?"); Use *OL = OperandList; OL[0] = Ptr; OL[1] = Idx; + + setName(Name); } GetElementPtrInst::GetElementPtrInst(const GetElementPtrInst &GEPI) @@ -1026,8 +1030,7 @@ GetElementPtr, OperandTraits::op_end(this) - 2, 2, InBe) { - init(Ptr, Idx); - setName(Name); + init(Ptr, Idx, Name); } GetElementPtrInst::GetElementPtrInst(Value *Ptr, Value *Idx, @@ -1037,8 +1040,7 @@ GetElementPtr, OperandTraits::op_end(this) - 2, 2, IAE) { - init(Ptr, Idx); - setName(Name); + init(Ptr, Idx, Name); } // getIndexedType - Returns the type of the element that would be loaded with From matthijs at stdin.nl Wed Jun 4 11:31:12 2008 From: matthijs at stdin.nl (Matthijs Kooijman) Date: Wed, 04 Jun 2008 16:31:12 -0000 Subject: [llvm-commits] [llvm] r51946 - in /llvm/trunk: include/llvm/Support/CallSite.h lib/VMCore/Instructions.cpp Message-ID: <200806041631.m54GVCiV007208@zion.cs.uiuc.edu> Author: matthijs Date: Wed Jun 4 11:31:12 2008 New Revision: 51946 URL: http://llvm.org/viewvc/llvm-project?rev=51946&view=rev Log: Add CallSite::hasArgument to allow for seeing if a call passes a certain value as an argument quickly. Modified: llvm/trunk/include/llvm/Support/CallSite.h llvm/trunk/lib/VMCore/Instructions.cpp Modified: llvm/trunk/include/llvm/Support/CallSite.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/CallSite.h?rev=51946&r1=51945&r2=51946&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/CallSite.h (original) +++ llvm/trunk/include/llvm/Support/CallSite.h Wed Jun 4 11:31:12 2008 @@ -129,6 +129,10 @@ else I->setOperand(ArgNo+3, newVal); // Skip Function, BB, BB } + + /// hasArgument - Returns true if this CallSite passes the given Value* as an + /// argument to the called function. + bool hasArgument(Value *Arg); /// arg_iterator - The type of iterator to use when looping over actual /// arguments at this call site... Modified: llvm/trunk/lib/VMCore/Instructions.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instructions.cpp?rev=51946&r1=51945&r2=51946&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Instructions.cpp (original) +++ llvm/trunk/lib/VMCore/Instructions.cpp Wed Jun 4 11:31:12 2008 @@ -91,6 +91,13 @@ cast(I)->setDoesNotThrow(doesNotThrow); } +bool CallSite::hasArgument(Value *Arg) { + for (arg_iterator AI = this->arg_begin(), E = this->arg_end(); AI != E; ++AI) + if (AI->get() == Arg) + return true; + return false; +} + //===----------------------------------------------------------------------===// // TerminatorInst Class //===----------------------------------------------------------------------===// From matthijs at stdin.nl Wed Jun 4 11:57:50 2008 From: matthijs at stdin.nl (Matthijs Kooijman) Date: Wed, 04 Jun 2008 16:57:50 -0000 Subject: [llvm-commits] [llvm] r51947 - in /llvm/trunk/lib: Analysis/IPA/CallGraph.cpp Transforms/IPO/DeadArgumentElimination.cpp Message-ID: <200806041657.m54GvooK008226@zion.cs.uiuc.edu> Author: matthijs Date: Wed Jun 4 11:57:50 2008 New Revision: 51947 URL: http://llvm.org/viewvc/llvm-project?rev=51947&view=rev Log: Replace two manual loops with calls to CallSite::hasArguments (no functional changes). Modified: llvm/trunk/lib/Analysis/IPA/CallGraph.cpp llvm/trunk/lib/Transforms/IPO/DeadArgumentElimination.cpp Modified: llvm/trunk/lib/Analysis/IPA/CallGraph.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/IPA/CallGraph.cpp?rev=51947&r1=51946&r2=51947&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/IPA/CallGraph.cpp (original) +++ llvm/trunk/lib/Analysis/IPA/CallGraph.cpp Wed Jun 4 11:57:50 2008 @@ -26,9 +26,7 @@ /// takes the address of the function. static bool isOnlyADirectCall(Function *F, CallSite CS) { if (!CS.getInstruction()) return false; - for (CallSite::arg_iterator I = CS.arg_begin(), E = CS.arg_end(); I != E; ++I) - if (*I == F) return false; - return true; + return !CS.hasArgument(F); } namespace { Modified: llvm/trunk/lib/Transforms/IPO/DeadArgumentElimination.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/DeadArgumentElimination.cpp?rev=51947&r1=51946&r2=51947&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/DeadArgumentElimination.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/DeadArgumentElimination.cpp Wed Jun 4 11:57:50 2008 @@ -331,13 +331,11 @@ } // If the function is PASSED IN as an argument, its address has been taken - for (CallSite::arg_iterator AI = CS.arg_begin(), E = CS.arg_end(); - AI != E; ++AI) - if (AI->get() == &F) { - FunctionIntrinsicallyLive = true; - break; - } - if (FunctionIntrinsicallyLive) break; + + if (CS.hasArgument(&F)) { + FunctionIntrinsicallyLive = true; + break; + } } if (FunctionIntrinsicallyLive) { From clattner at apple.com Wed Jun 4 12:00:30 2008 From: clattner at apple.com (Chris Lattner) Date: Wed, 4 Jun 2008 10:00:30 -0700 Subject: [llvm-commits] [llvm] r51946 - in /llvm/trunk: include/llvm/Support/CallSite.h lib/VMCore/Instructions.cpp In-Reply-To: <200806041631.m54GVCiV007208@zion.cs.uiuc.edu> References: <200806041631.m54GVCiV007208@zion.cs.uiuc.edu> Message-ID: On Jun 4, 2008, at 9:31 AM, Matthijs Kooijman wrote: > URL: http://llvm.org/viewvc/llvm-project?rev=51946&view=rev > Log: > Add CallSite::hasArgument to allow for seeing if a call passes a > certain value as an argument quickly. Hey Matthijs, This is nice, but I think the method should be marked 'const' and take a const Value*. -Chris > > > Modified: > llvm/trunk/include/llvm/Support/CallSite.h > llvm/trunk/lib/VMCore/Instructions.cpp > > Modified: llvm/trunk/include/llvm/Support/CallSite.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/CallSite.h?rev=51946&r1=51945&r2=51946&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/include/llvm/Support/CallSite.h (original) > +++ llvm/trunk/include/llvm/Support/CallSite.h Wed Jun 4 11:31:12 > 2008 > @@ -129,6 +129,10 @@ > else > I->setOperand(ArgNo+3, newVal); // Skip Function, BB, BB > } > + > + /// hasArgument - Returns true if this CallSite passes the given > Value* as an > + /// argument to the called function. > + bool hasArgument(Value *Arg); > > /// arg_iterator - The type of iterator to use when looping over > actual > /// arguments at this call site... > > Modified: llvm/trunk/lib/VMCore/Instructions.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instructions.cpp?rev=51946&r1=51945&r2=51946&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/VMCore/Instructions.cpp (original) > +++ llvm/trunk/lib/VMCore/Instructions.cpp Wed Jun 4 11:31:12 2008 > @@ -91,6 +91,13 @@ > cast(I)->setDoesNotThrow(doesNotThrow); > } > > +bool CallSite::hasArgument(Value *Arg) { > + for (arg_iterator AI = this->arg_begin(), E = this->arg_end(); > AI != E; ++AI) > + if (AI->get() == Arg) > + return true; > + return false; > +} > + > // > = > = > = > ----------------------------------------------------------------------= > ==// > // TerminatorInst Class > // > = > = > = > ----------------------------------------------------------------------= > ==// > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From clattner at apple.com Wed Jun 4 12:02:16 2008 From: clattner at apple.com (Chris Lattner) Date: Wed, 4 Jun 2008 10:02:16 -0700 Subject: [llvm-commits] [llvm] r51947 - in /llvm/trunk/lib: Analysis/IPA/CallGraph.cpp Transforms/IPO/DeadArgumentElimination.cpp In-Reply-To: <200806041657.m54GvooK008226@zion.cs.uiuc.edu> References: <200806041657.m54GvooK008226@zion.cs.uiuc.edu> Message-ID: On Jun 4, 2008, at 9:57 AM, Matthijs Kooijman wrote: > URL: http://llvm.org/viewvc/llvm-project?rev=51947&view=rev > Log: > Replace two manual loops with calls to CallSite::hasArguments (no > functional changes). Ok. > +++ llvm/trunk/lib/Transforms/IPO/DeadArgumentElimination.cpp Wed > Jun 4 11:57:50 2008 > @@ -331,13 +331,11 @@ > } > > // If the function is PASSED IN as an argument, its address > has been taken > + if (CS.hasArgument(&F)) { > + FunctionIntrinsicallyLive = true; > + break; > + } > } Actually, this can be checked in O(1) time by just calling I.getOperandNo(). If the use_iterator is for the callee operand of the function, then it is ok. If not, you know it is passing in the address of the function. The DeadArgElim code was written before getOperandNo() existed on use_iterator. -Chris From evan.cheng at apple.com Wed Jun 4 12:21:44 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 04 Jun 2008 17:21:44 -0000 Subject: [llvm-commits] [llvm] r51949 - /llvm/trunk/lib/CodeGen/LowerSubregs.cpp Message-ID: <200806041721.m54HLiju009089@zion.cs.uiuc.edu> Author: evancheng Date: Wed Jun 4 12:21:44 2008 New Revision: 51949 URL: http://llvm.org/viewvc/llvm-project?rev=51949&view=rev Log: Revert this. Modified: llvm/trunk/lib/CodeGen/LowerSubregs.cpp Modified: llvm/trunk/lib/CodeGen/LowerSubregs.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LowerSubregs.cpp?rev=51949&r1=51948&r2=51949&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LowerSubregs.cpp (original) +++ llvm/trunk/lib/CodeGen/LowerSubregs.cpp Wed Jun 4 12:21:44 2008 @@ -30,10 +30,6 @@ return "Subregister lowering instruction pass"; } - void getAnalysisUsage(AnalysisUsage &AU) const { - AU.setPreservesAll(); - } - /// runOnMachineFunction - pass entry point bool runOnMachineFunction(MachineFunction&); From matthijs at stdin.nl Wed Jun 4 12:30:01 2008 From: matthijs at stdin.nl (Matthijs Kooijman) Date: Wed, 4 Jun 2008 19:30:01 +0200 Subject: [llvm-commits] [llvm] r51947 - in /llvm/trunk/lib: Analysis/IPA/CallGraph.cpp Transforms/IPO/DeadArgumentElimination.cpp In-Reply-To: References: <200806041657.m54GvooK008226@zion.cs.uiuc.edu> Message-ID: <20080604173001.GS25337@katherina.student.utwente.nl> Hi Chris, > Actually, this can be checked in O(1) time by just calling > I.getOperandNo(). If the use_iterator is for the callee operand of > the function, then it is ok. If not, you know it is passing in the > address of the function. The DeadArgElim code was written before > getOperandNo() existed on use_iterator. Sounds better, I'll change it to that way tomorrow. But, how about functions that have themselves as an argument? Or would that solve itself because then both operands (callee and argument) would be in the use list seperately? Must be the last one, so it sounds safe to change this. Gr. Matthijs -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 189 bytes Desc: Digital signature Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20080604/c9c13583/attachment.bin From clattner at apple.com Wed Jun 4 12:34:40 2008 From: clattner at apple.com (Chris Lattner) Date: Wed, 4 Jun 2008 10:34:40 -0700 Subject: [llvm-commits] [llvm] r51947 - in /llvm/trunk/lib: Analysis/IPA/CallGraph.cpp Transforms/IPO/DeadArgumentElimination.cpp In-Reply-To: <20080604173001.GS25337@katherina.student.utwente.nl> References: <200806041657.m54GvooK008226@zion.cs.uiuc.edu> <20080604173001.GS25337@katherina.student.utwente.nl> Message-ID: <8E2F3847-833F-4A1C-8B0B-1C5372914088@apple.com> On Jun 4, 2008, at 10:30 AM, Matthijs Kooijman wrote: > Hi Chris, > >> Actually, this can be checked in O(1) time by just calling >> I.getOperandNo(). If the use_iterator is for the callee operand of >> the function, then it is ok. If not, you know it is passing in the >> address of the function. The DeadArgElim code was written before >> getOperandNo() existed on use_iterator. > Sounds better, I'll change it to that way tomorrow. > > But, how about functions that have themselves as an argument? Or > would that > solve itself because then both operands (callee and argument) would > be in the > use list seperately? Must be the last one, so it sounds safe to > change this. Yep, exactly. BTW, are you seeing this build error? llvm[2]: Compiling Optimize.cpp for Debug build Undefined symbols: "llvm::GetElementPtrInst::init(llvm::Value*, llvm::Value* const*, unsigned int)", referenced from: void llvm::GetElementPtrInst::init(llvm::Value*, llvm::Value**, llvm::Value**, std::basic_string, std::allocator > const&, std::random_access_iterator_tag)in libLLVMScalarOpts.a(InstructionCombining.o) void llvm::GetElementPtrInst::init(llvm::Value*, llvm::Value**, llvm::Value**, std::basic_string, std::allocator > const&, std::random_access_iterator_tag)in libLLVMScalarOpts.a(InstructionCombining.o) void llvm::GetElementPtrInst::init(llvm::Value*, llvm::Value**, llvm::Value**, std::basic_string References: <200806041657.m54GvooK008226@zion.cs.uiuc.edu> <20080604173001.GS25337@katherina.student.utwente.nl> <8E2F3847-833F-4A1C-8B0B-1C5372914088@apple.com> Message-ID: <1FB9CB18-C897-4426-9E0E-DA5E48AECADE@apple.com> On Jun 4, 2008, at 10:34 AM, Chris Lattner wrote: > > llvm[2]: Compiling Optimize.cpp for Debug build > Undefined symbols: > "llvm::GetElementPtrInst::init(llvm::Value*, llvm::Value* const*, > unsigned int)", referenced from: > void llvm::GetElementPtrInst::init(llvm::Value*, Sorry for the noise, a clean rebuild fixed it. -chris From resistor at mac.com Wed Jun 4 12:55:59 2008 From: resistor at mac.com (Owen Anderson) Date: Wed, 04 Jun 2008 17:55:59 -0000 Subject: [llvm-commits] [llvm] r51950 - /llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp Message-ID: <200806041755.m54Htx0Y010472@zion.cs.uiuc.edu> Author: resistor Date: Wed Jun 4 12:55:58 2008 New Revision: 51950 URL: http://llvm.org/viewvc/llvm-project?rev=51950&view=rev Log: Correctly construct live intervals for the copies we inserted into the predecessors of a block containing a PHI. Modified: llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp Modified: llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp?rev=51950&r1=51949&r2=51950&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp (original) +++ llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp Wed Jun 4 12:55:58 2008 @@ -467,6 +467,8 @@ } else { // Otherwise, add it to the renaming set LiveInterval& I = LI.getOrCreateInterval(SrcReg); + // We need to subtract one from the index because live ranges are open + // at the end. unsigned idx = LI.getMBBEndIdx(P->getOperand(i).getMBB()) - 1; VNInfo* VN = I.getLiveRangeContaining(idx)->valno; @@ -632,7 +634,7 @@ /// of Static Single Assignment Form" by Briggs, et al. void StrongPHIElimination::ScheduleCopies(MachineBasicBlock* MBB, std::set& pushed) { - // FIXME: This function needs to update LiveVariables + // FIXME: This function needs to update LiveIntervals std::map& copy_set= Waiting[MBB]; std::map worklist; @@ -661,6 +663,8 @@ MachineRegisterInfo& MRI = MF->getRegInfo(); const TargetInstrInfo *TII = MF->getTarget().getInstrInfo(); + SmallVector, 4> InsertedPHIDests; + // Iterate over the worklist, inserting copies while (!worklist.empty() || !copy_set.empty()) { while (!worklist.empty()) { @@ -691,6 +695,11 @@ map[curr.first], RC, RC); map[curr.first] = curr.second; + // Push this copy onto InsertedPHICopies so we can + // update LiveIntervals with it. + MachineBasicBlock::iterator MI = MBB->getFirstTerminator(); + InsertedPHIDests.push_back(std::make_pair(curr.second, --MI)); + // If curr.first is a destination in copy_set... for (std::map::iterator I = copy_set.begin(), E = copy_set.end(); I != E; ) @@ -723,6 +732,34 @@ worklist.insert(curr); } } + + // Renumber the instructions so that we can perform the index computations + // needed to create new live intervals. + LI.computeNumbering(); + + // For copies that we inserted at the ends of predecessors, we construct + // live intervals. This is pretty easy, since we know that the destination + // register cannot have be in live at that point previously. We just have + // to make sure that, for registers that serve as inputs to more than one + // PHI, we don't create multiple overlapping live intervals. + std::set RegHandled; + for (SmallVector, 4>::iterator I = + InsertedPHIDests.begin(), E = InsertedPHIDests.end(); I != E; ++I) { + if (!RegHandled.count(I->first)) { + LiveInterval& Interval = LI.getOrCreateInterval(I->first); + VNInfo* VN = Interval.getNextValue( + LI.getInstructionIndex(I->second) + LiveIntervals::InstrSlots::DEF, + I->second, LI.getVNInfoAllocator()); + VN->hasPHIKill = true; + VN->kills.push_back(LI.getMBBEndIdx(I->second->getParent())); + LiveRange LR(LI.getInstructionIndex(I->second) + + LiveIntervals::InstrSlots::DEF, + LI.getMBBEndIdx(I->second->getParent()) + 1, VN); + Interval.addRange(LR); + + RegHandled.insert(I->first); + } + } } /// InsertCopies - insert copies into MBB and all of its successors From evan.cheng at apple.com Wed Jun 4 12:59:28 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 4 Jun 2008 10:59:28 -0700 Subject: [llvm-commits] [llvm] r51950 - /llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp In-Reply-To: <200806041755.m54Htx0Y010472@zion.cs.uiuc.edu> References: <200806041755.m54Htx0Y010472@zion.cs.uiuc.edu> Message-ID: <56E95044-3895-4B65-9C6B-B3AFFD977323@apple.com> Hi Owen, While you are doing this and cleaning up liveintervals. Can you add helper function to liveinterval for creating copy intervals etc.? Evan On Jun 4, 2008, at 10:55 AM, Owen Anderson wrote: > > + > + // Renumber the instructions so that we can perform the index > computations > + // needed to create new live intervals. > + LI.computeNumbering(); > + > + // For copies that we inserted at the ends of predecessors, we > construct > + // live intervals. This is pretty easy, since we know that the > destination > + // register cannot have be in live at that point previously. We > just have > + // to make sure that, for registers that serve as inputs to more > than one > + // PHI, we don't create multiple overlapping live intervals. > + std::set RegHandled; > + for (SmallVector, 4>::iterator > I = > + InsertedPHIDests.begin(), E = InsertedPHIDests.end(); I != > E; ++I) { > + if (!RegHandled.count(I->first)) { > + LiveInterval& Interval = LI.getOrCreateInterval(I->first); > + VNInfo* VN = Interval.getNextValue( > + LI.getInstructionIndex(I->second) + > LiveIntervals::InstrSlots::DEF, > + I->second, > LI.getVNInfoAllocator()); > + VN->hasPHIKill = true; > + VN->kills.push_back(LI.getMBBEndIdx(I->second->getParent())); > + LiveRange LR(LI.getInstructionIndex(I->second) + > + LiveIntervals::InstrSlots::DEF, > + LI.getMBBEndIdx(I->second->getParent()) + 1, VN); > + Interval.addRange(LR); > + > + RegHandled.insert(I->first); > + } > + } > } > > /// InsertCopies - insert copies into MBB and all of its successors > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From resistor at mac.com Wed Jun 4 13:02:29 2008 From: resistor at mac.com (Owen Anderson) Date: Wed, 04 Jun 2008 11:02:29 -0700 Subject: [llvm-commits] [llvm] r51950 - /llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp In-Reply-To: <56E95044-3895-4B65-9C6B-B3AFFD977323@apple.com> References: <200806041755.m54Htx0Y010472@zion.cs.uiuc.edu> <56E95044-3895-4B65-9C6B-B3AFFD977323@apple.com> Message-ID: <56F8AB65-32BA-4001-9DE3-518F00D59BD9@mac.com> I don't follow. What would this helper do? --Owen On Jun 4, 2008, at 10:59 AM, Evan Cheng wrote: > Hi Owen, > > While you are doing this and cleaning up liveintervals. Can you add > helper function to liveinterval for creating copy intervals etc.? > > Evan > > On Jun 4, 2008, at 10:55 AM, Owen Anderson wrote: > >> >> + >> + // Renumber the instructions so that we can perform the index >> computations >> + // needed to create new live intervals. >> + LI.computeNumbering(); >> + >> + // For copies that we inserted at the ends of predecessors, we >> construct >> + // live intervals. This is pretty easy, since we know that the >> destination >> + // register cannot have be in live at that point previously. We >> just have >> + // to make sure that, for registers that serve as inputs to more >> than one >> + // PHI, we don't create multiple overlapping live intervals. >> + std::set RegHandled; >> + for (SmallVector, 4>::iterator >> I = >> + InsertedPHIDests.begin(), E = InsertedPHIDests.end(); I != >> E; ++I) { >> + if (!RegHandled.count(I->first)) { >> + LiveInterval& Interval = LI.getOrCreateInterval(I->first); >> + VNInfo* VN = Interval.getNextValue( >> + LI.getInstructionIndex(I->second) + >> LiveIntervals::InstrSlots::DEF, >> + I->second, >> LI.getVNInfoAllocator()); >> + VN->hasPHIKill = true; >> + VN->kills.push_back(LI.getMBBEndIdx(I->second->getParent())); >> + LiveRange LR(LI.getInstructionIndex(I->second) + >> + LiveIntervals::InstrSlots::DEF, >> + LI.getMBBEndIdx(I->second->getParent()) + 1, VN); >> + Interval.addRange(LR); >> + >> + RegHandled.insert(I->first); >> + } >> + } >> } >> >> /// InsertCopies - insert copies into MBB and all of its successors >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From sabre at nondot.org Wed Jun 4 13:03:29 2008 From: sabre at nondot.org (Chris Lattner) Date: Wed, 04 Jun 2008 18:03:29 -0000 Subject: [llvm-commits] [llvm] r51952 - in /llvm/trunk: lib/Target/CBackend/CBackend.cpp test/CodeGen/CBackend/2008-06-04-IndirectMem.ll Message-ID: <200806041803.m54I3T50010821@zion.cs.uiuc.edu> Author: lattner Date: Wed Jun 4 13:03:28 2008 New Revision: 51952 URL: http://llvm.org/viewvc/llvm-project?rev=51952&view=rev Log: Rewrite a bunch of the CBE's inline asm code, giving it the ability to handle indirect input operands. This fixes PR2407. Added: llvm/trunk/test/CodeGen/CBackend/2008-06-04-IndirectMem.ll Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CBackend.cpp?rev=51952&r1=51951&r2=51952&view=diff ============================================================================== --- llvm/trunk/lib/Target/CBackend/CBackend.cpp (original) +++ llvm/trunk/lib/Target/CBackend/CBackend.cpp Wed Jun 4 13:03:28 2008 @@ -2956,10 +2956,6 @@ void CWriter::visitInlineAsm(CallInst &CI) { InlineAsm* as = cast(CI.getOperand(0)); std::vector Constraints = as->ParseConstraints(); - std::vector > Input; - std::vector > > Output; - std::string Clobber; - unsigned ValueCount = 0; std::vector > ResultVals; if (CI.getType() == Type::VoidTy) @@ -2971,61 +2967,103 @@ ResultVals.push_back(std::make_pair(&CI, -1)); } + // Fix up the asm string for gcc and emit it. + Out << "__asm__ volatile (\"" << gccifyAsm(as->getAsmString()) << "\"\n"; + Out << " :"; + + unsigned ValueCount = 0; + bool IsFirst = true; + + // Convert over all the output constraints. for (std::vector::iterator I = Constraints.begin(), - E = Constraints.end(); I != E; ++I) { + E = Constraints.end(); I != E; ++I) { + + if (I->Type != InlineAsm::isOutput) { + ++ValueCount; + continue; // Ignore non-output constraints. + } + assert(I->Codes.size() == 1 && "Too many asm constraint codes to handle"); std::string C = InterpretASMConstraint(*I); if (C.empty()) continue; - switch (I->Type) { - default: assert(0 && "Unknown asm constraint"); - case InlineAsm::isInput: { - assert(ValueCount >= ResultVals.size() && "Input can't refer to result"); - Value *V = CI.getOperand(ValueCount-ResultVals.size()+1); - Input.push_back(std::make_pair(C, V)); - break; - } - case InlineAsm::isOutput: { - std::pair V; - if (ValueCount < ResultVals.size()) - V = ResultVals[ValueCount]; - else - V = std::make_pair(CI.getOperand(ValueCount-ResultVals.size()+1), -1); - Output.push_back(std::make_pair("="+((I->isEarlyClobber ? "&" : "")+C), - V)); - break; - } - case InlineAsm::isClobber: - Clobber += ",\"" + C + "\""; - continue; // Not an actual argument. + if (!IsFirst) { + Out << ", "; + IsFirst = false; } - ++ValueCount; // Consumes an argument. + + // Unpack the dest. + Value *DestVal; + int DestValNo = -1; + + if (ValueCount < ResultVals.size()) { + DestVal = ResultVals[ValueCount].first; + DestValNo = ResultVals[ValueCount].second; + } else + DestVal = CI.getOperand(ValueCount-ResultVals.size()+1); + + if (I->isEarlyClobber) + C = "&"+C; + + Out << "\"=" << C << "\"(" << GetValueName(DestVal); + if (DestValNo != -1) + Out << ".field" << DestValNo; // Multiple retvals. + Out << ")"; + ++ValueCount; } - // Fix up the asm string for gcc. - std::string asmstr = gccifyAsm(as->getAsmString()); - Out << "__asm__ volatile (\"" << asmstr << "\"\n"; - Out << " :"; - for (unsigned i = 0, e = Output.size(); i != e; ++i) { - if (i) + // Convert over all the input constraints. + Out << "\n :"; + IsFirst = true; + ValueCount = 0; + for (std::vector::iterator I = Constraints.begin(), + E = Constraints.end(); I != E; ++I) { + if (I->Type != InlineAsm::isInput) { + ++ValueCount; + continue; // Ignore non-input constraints. + } + + assert(I->Codes.size() == 1 && "Too many asm constraint codes to handle"); + std::string C = InterpretASMConstraint(*I); + if (C.empty()) continue; + + if (!IsFirst) { Out << ", "; - Out << "\"" << Output[i].first << "\"(" - << GetValueName(Output[i].second.first); - if (Output[i].second.second != -1) - Out << ".field" << Output[i].second.second; // Multiple retvals. + IsFirst = false; + } + + assert(ValueCount >= ResultVals.size() && "Input can't refer to result"); + Value *SrcVal = CI.getOperand(ValueCount-ResultVals.size()+1); + + Out << "\"" << C << "\"("; + if (!I->isIndirect) + writeOperand(SrcVal); + else + writeOperandDeref(SrcVal); Out << ")"; } - Out << "\n :"; - for (unsigned i = 0, e = Input.size(); i != e; ++i) { - if (i) + + // Convert over the clobber constraints. + IsFirst = true; + ValueCount = 0; + for (std::vector::iterator I = Constraints.begin(), + E = Constraints.end(); I != E; ++I) { + if (I->Type != InlineAsm::isClobber) + continue; // Ignore non-input constraints. + + assert(I->Codes.size() == 1 && "Too many asm constraint codes to handle"); + std::string C = InterpretASMConstraint(*I); + if (C.empty()) continue; + + if (!IsFirst) { Out << ", "; - Out << "\"" << Input[i].first << "\"("; - writeOperand(Input[i].second); - Out << ")"; + IsFirst = false; + } + + Out << '\"' << C << '"'; } - if (Clobber.size()) - Out << "\n :" << Clobber.substr(1); + Out << ")"; } Added: llvm/trunk/test/CodeGen/CBackend/2008-06-04-IndirectMem.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CBackend/2008-06-04-IndirectMem.ll?rev=51952&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/CBackend/2008-06-04-IndirectMem.ll (added) +++ llvm/trunk/test/CodeGen/CBackend/2008-06-04-IndirectMem.ll Wed Jun 4 13:03:28 2008 @@ -0,0 +1,12 @@ +; RUN: llvm-as < %s | llc -march=c | grep {"m"(llvm_cbe_newcw))} +; PR2407 + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32" +target triple = "i386-pc-linux-gnu" + +define void @foo() { + %newcw = alloca i16 ; [#uses=2] + call void asm sideeffect "fldcw $0", "*m,~{dirflag},~{fpsr},~{flags}"( i16* +%newcw ) nounwind + ret void +} From matthijs at stdin.nl Wed Jun 4 13:06:00 2008 From: matthijs at stdin.nl (Matthijs Kooijman) Date: Wed, 4 Jun 2008 20:06:00 +0200 Subject: [llvm-commits] [llvm] r51946 - in /llvm/trunk: include/llvm/Support/CallSite.h lib/VMCore/Instructions.cpp In-Reply-To: References: <200806041631.m54GVCiV007208@zion.cs.uiuc.edu> Message-ID: <20080604180600.GT25337@katherina.student.utwente.nl> Hi Chris, > This is nice, but I think the method should be marked 'const' and take > a const Value*. I'm quite positive you're right. I'm still getting used to the entire C++ const stuff, I'll change in the morning. Thanks for the feedback! Gr. Matthijs -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 189 bytes Desc: Digital signature Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20080604/a29f87d7/attachment.bin From dalej at apple.com Wed Jun 4 13:07:51 2008 From: dalej at apple.com (Dale Johannesen) Date: Wed, 4 Jun 2008 11:07:51 -0700 Subject: [llvm-commits] [llvm] r51904 - /llvm/trunk/lib/CodeGen/AsmPrinter.cpp In-Reply-To: <200806031539.m53FdpdY015874@zion.cs.uiuc.edu> References: <200806031539.m53FdpdY015874@zion.cs.uiuc.edu> Message-ID: <49273962-E864-43D5-9422-E2D080DB4CB7@apple.com> Hi Scott, this broke a bunch of tests in the gcc testsuite that are looking for specific patterns in the .s file: Tests that now fail, but worked before: objc.dg/const-cfstring-4-64bit.m scan-assembler .quad \t___CFConstantStringClassReference\n\t.long\t1992\n\t.space( |\t)4\n \t.quad\t.*\n\t.quad\t19\n objc.dg/const-cfstring-4.m scan-assembler .long \t___CFConstantStringClassReference\n\t.long\t1992\n\t.long\t.*\n \t.long\t19\n objc.dg/const-str-10-64bit.m scan-assembler .quad \t__NSConstantStringClassReference\n\t.quad\t.*\n\t.long\t5\n \t.space( |\t)4\n objc.dg/const-str-10.m scan-assembler .long \t__NSConstantStringClassReference\n\t.long\t.*\n\t.long\t5\n objc.dg/const-str-11-64bit.m scan-assembler .quad\t__XStrClassReference \n\t.quad\t.*\n\t.long\t5\n\t.space( |\t)4\n objc.dg/const-str-11.m scan-assembler .long\t__XStrClassReference\n \t.long\t.*\n\t.long\t5\n objc.dg/const-str-9-64bit.m scan-assembler .quad \t__NSConstantStringClassReference\n\t.quad\t.*\n\t.long\t5\n \t.space( |\t)4\n objc.dg/const-str-9.m scan-assembler .long \t__NSConstantStringClassReference\n\t.long\t.*\n\t.long\t5\n objc.dg/next-runtime-1.m scan-assembler L_OBJC_MODULES:.*\n[ \t]*.long \t7\n objc.dg/objc2-protocol-ext-1.m scan-assembler .long\t72\n\t.(long\t0| space\t4) objc.dg/symtab-1-64bit.m scan-assembler L_OBJC_SYMBOLS.*:.*\n\t(.quad \t0|.space\t8)\n\t(.long\t0\n\t.space 4|.space\t8)\n\t.(short|word) \t2\n\t.((short|word)\t0|space\t2)\n\t.space( |\t)4\n\t.quad \tL_OBJC_CLASS_Derived.*\n\t.quad\tL_OBJC_CLASS_Base.*\n objc.dg/symtab-1.m scan-assembler L_OBJC_SYMBOLS.*:.*\n\t(.long \t0|.space\t4)\n\t(.long\t0|.space\t4)\n\t.(short|word)\t2\n\t.((short| word)\t0|space\t2)\n\t.long\tL_OBJC_CLASS_Derived.*\n\t.long \tL_OBJC_CLASS_Base.*\n Tests that now fail, but worked before: obj-c++.dg/const-cfstring-4-64bit.mm scan-assembler .quad \t___CFConstantStringClassReference\n\t.long\t1992\n\t.space( |\t)4\n \t.quad\t.*\n\t.quad\t19\n obj-c++.dg/const-cfstring-4.mm scan-assembler .long \t___CFConstantStringClassReference\n\t.long\t1992\n\t.long\t.*\n \t.long\t19\n obj-c++.dg/const-str-10.mm scan-assembler .long \t__NSConstantStringClassReference\n\t.long\t.*\n\t.long\t5\n obj-c++.dg/const-str-11.mm scan-assembler .long\t__XStrClassReference\n \t.long\t.*\n\t.long\t5\n obj-c++.dg/const-str-9.mm scan-assembler .long \t__NSConstantStringClassReference\n\t.long\t.*\n\t.long\t5\n obj-c++.dg/objc2-protocol-ext-1.mm scan-assembler .long\t72\n\t.(long \t0|space\t4) Would you mind dealing with these? Here's one example of how: Index: const-cfstring-4-64bit.m =================================================================== --- const-cfstring-4-64bit.m (revision 51948) +++ const-cfstring-4-64bit.m (working copy) @@ -9,4 +9,4 @@ /* { dg-final { scan-assembler ".section __DATA, __cfstring" } } */ /* LLVM LOCAL accept llvm syntax */ -/* { dg-final { scan-assembler ".quad \t___CFConstantStringClassReference\n\t.long\t1992\n\t.space( |\t)4\n \t.quad\t.*\n\t.quad\t19\n" } } */ +/* { dg-final { scan-assembler ".quad \t___CFConstantStringClassReference\n\t.long\t1992(\t\t\t## 0x7C8)?\n \t.space( |\t)4\n\t.quad\t.*\n\t.quad\t19\n" } } */ On Jun 3, 2008, at 8:39 AM, Scott Michel wrote: > Author: pingbak > Date: Tue Jun 3 10:39:51 2008 > New Revision: 51904 > > URL: http://llvm.org/viewvc/llvm-project?rev=51904&view=rev > Log: > Find a better place to output hex constants corresponding to integers. > > Modified: > llvm/trunk/lib/CodeGen/AsmPrinter.cpp > > Modified: llvm/trunk/lib/CodeGen/AsmPrinter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter.cpp?rev=51904&r1=51903&r2=51904&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/CodeGen/AsmPrinter.cpp (original) > +++ llvm/trunk/lib/CodeGen/AsmPrinter.cpp Tue Jun 3 10:39:51 2008 > @@ -1074,6 +1074,11 @@ > const Type *type = CV->getType(); > printDataDirective(type); > EmitConstantValueOnly(CV); > + if (const ConstantInt *CI = dyn_cast(CV)) { > + O << "\t\t\t" > + << TAI->getCommentString() > + << " 0x" << CI->getValue().toStringUnsigned(16); > + } > O << "\n"; > } From evan.cheng at apple.com Wed Jun 4 13:09:20 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 04 Jun 2008 18:09:20 -0000 Subject: [llvm-commits] [llvm] r51953 - /llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Message-ID: <200806041809.m54I9K8S011043@zion.cs.uiuc.edu> Author: evancheng Date: Wed Jun 4 13:09:20 2008 New Revision: 51953 URL: http://llvm.org/viewvc/llvm-project?rev=51953&view=rev Log: Oops. Should not be enabled by default. Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=51953&r1=51952&r2=51953&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original) +++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Wed Jun 4 13:09:20 2008 @@ -39,7 +39,7 @@ cl::desc("Perform sinking on machine code")); static cl::opt EnableStackColoring("stack-coloring", - cl::init(true), cl::Hidden, + cl::init(false), cl::Hidden, cl::desc("Perform stack slot coloring")); static cl::opt EnableLICM("machine-licm", From sabre at nondot.org Wed Jun 4 13:20:43 2008 From: sabre at nondot.org (Chris Lattner) Date: Wed, 04 Jun 2008 18:20:43 -0000 Subject: [llvm-commits] [llvm] r51954 - /llvm/trunk/docs/ProgrammersManual.html Message-ID: <200806041820.m54IKhP1011380@zion.cs.uiuc.edu> Author: lattner Date: Wed Jun 4 13:20:42 2008 New Revision: 51954 URL: http://llvm.org/viewvc/llvm-project?rev=51954&view=rev Log: Fix inst_iterator example. Modified: llvm/trunk/docs/ProgrammersManual.html Modified: llvm/trunk/docs/ProgrammersManual.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ProgrammersManual.html?rev=51954&r1=51953&r2=51954&view=diff ============================================================================== --- llvm/trunk/docs/ProgrammersManual.html (original) +++ llvm/trunk/docs/ProgrammersManual.html Wed Jun 4 13:20:42 2008 @@ -1484,8 +1484,8 @@ #include "llvm/Support/InstIterator.h" // F is a pointer to a Function instance -for (inst_iterator i = inst_begin(F), e = inst_end(F); i != e; ++i) - llvm::cerr << *i << "\n"; +for (inst_iterator I = inst_begin(F), E = inst_end(F); I != E; ++I) + llvm::cerr << *I << "\n"; @@ -1497,7 +1497,10 @@ 
 std::set<Instruction*> worklist;
-worklist.insert(inst_begin(F), inst_end(F));
+// or better yet, SmallPtrSet<Instruction*, 64> worklist;
+
+for (inst_iterator I = inst_begin(F), E = inst_end(F); I != E; ++I)
+   worklist.insert(&*I);
From gohman at apple.com Wed Jun 4 13:26:06 2008 From: gohman at apple.com (Dan Gohman) Date: Wed, 4 Jun 2008 11:26:06 -0700 Subject: [llvm-commits] [llvm] r51937 - in /llvm/trunk: include/llvm/Instructions.h lib/VMCore/Instructions.cpp In-Reply-To: <200806041440.m54EeuB2003772@zion.cs.uiuc.edu> References: <200806041440.m54EeuB2003772@zion.cs.uiuc.edu> Message-ID: <56BBE960-59A4-47C9-81CD-46F9C5DA1798@apple.com> Hi Matthijs, This patch looks good. Just one stylistic comment below. On Jun 4, 2008, at 7:40 AM, Matthijs Kooijman wrote: > > ExtractValueInst(const ExtractValueInst &EVI); > - void init(Value *Agg, const unsigned *Idx, unsigned NumIdx); > - void init(Value *Agg, unsigned Idx); > + void init(Value *Agg, const unsigned *Idx, unsigned NumIdx, const > std::string &Name); > InsertValueInst(const InsertValueInst &IVI); > - void init(Value *Agg, Value *Val, const unsigned *Idx, unsigned > NumIdx); > - void init(Value *Agg, Value *Val, unsigned Idx); > + void init(Value *Agg, Value *Val, const unsigned *Idx, unsigned > NumIdx, const std::string &Name); > > -void ExtractValueInst::init(Value *Agg, const unsigned *Idx, > unsigned NumIdx) { > +void ExtractValueInst::init(Value *Agg, const unsigned *Idx, > unsigned NumIdx, const std::string &Name) { Please adjust these lines to be within 80 columns. Thanks! Dan From resistor at mac.com Wed Jun 4 13:28:10 2008 From: resistor at mac.com (Owen Anderson) Date: Wed, 04 Jun 2008 18:28:10 -0000 Subject: [llvm-commits] [llvm] r51955 - /llvm/trunk/lib/Transforms/Scalar/GVN.cpp Message-ID: <200806041828.m54ISAbR011662@zion.cs.uiuc.edu> Author: resistor Date: Wed Jun 4 13:28:10 2008 New Revision: 51955 URL: http://llvm.org/viewvc/llvm-project?rev=51955&view=rev Log: Remove unneeded #include. Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVN.cpp?rev=51955&r1=51954&r2=51955&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/GVN.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/GVN.cpp Wed Jun 4 13:28:10 2008 @@ -32,7 +32,6 @@ #include "llvm/Support/CFG.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/Debug.h" -#include using namespace llvm; STATISTIC(NumGVNInstr, "Number of instructions deleted"); From gohman at apple.com Wed Jun 4 13:43:03 2008 From: gohman at apple.com (Dan Gohman) Date: Wed, 4 Jun 2008 11:43:03 -0700 Subject: [llvm-commits] value range analysis based on scalar-evolutions In-Reply-To: <4846113C.2060002@mxc.ca> References: <48436EF1.8020203@mxc.ca> <36D98FFC-7C90-448F-AA77-F84CE3F71013@apple.com> <4846113C.2060002@mxc.ca> Message-ID: <99070F00-41E5-466C-92CC-8A3D5B15FF06@apple.com> On Jun 3, 2008, at 8:51 PM, Nick Lewycky wrote: > Devang Patel wrote: >> >> Is there a reason to not make this a LoopPass ? > > Because then it wouldn't store Value->ConstantRange mappings for the > whole function. There's no reason the SCEV analysis stuff couldn't > move > into a LoopPass, but the mapping probably shouldn't be. SCEV isn't conceptually a LoopPass. It's true that our current in-tree SCEV users are all LoopPasses, but the underlying SCEV logic isn't fundamentally single-loop-oriented or even single-loop-nest-oriented. SCEV isn't really even a FunctionPass either, at a conceptual level. ModulePass is closer, except that that would be a significant inconvenience given the way we currently use it. ImmutablePass is also closer, except for the requirement of notification whenever an instruction is deleted, which ImmutablePass doesn't allow. I believe SCEV is something that doesn't fit well in the current Pass hierarchy. And Nick's value-range pass is in a similar situation. Also, I've been thinking about making what's now ValueTracking.cpp into a pass so that it can memoize results; such a pass would be yet another instance of this. I'd be interested in discussing ideas for this problem. But getting back to the patch itself, I see it has a runOnFunction that eagerly computes results for all instructions in all loops in a function. I'd like to suggest that it compute results on demand, similar to how SCEV works. Dan From dalej at apple.com Wed Jun 4 14:31:55 2008 From: dalej at apple.com (Dale Johannesen) Date: Wed, 04 Jun 2008 19:31:55 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r51959 - in /llvm-gcc-4.2/trunk/gcc: config/i386/llvm-i386.cpp llvm-abi.h Message-ID: <200806041931.m54JVtgE013677@zion.cs.uiuc.edu> Author: johannes Date: Wed Jun 4 14:31:55 2008 New Revision: 51959 URL: http://llvm.org/viewvc/llvm-project?rev=51959&view=rev Log: x86-64 ABI conformance; for objects of 4 or 12 bytes pass the 4-byte piece as 4 bytes not 8 bytes. Fixes all but 1 struct-layout-1 failure (does not, however, fix 477.dealII). Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp llvm-gcc-4.2/trunk/gcc/llvm-abi.h Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp?rev=51959&r1=51958&r2=51959&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp Wed Jun 4 14:31:55 2008 @@ -1315,20 +1315,28 @@ enum machine_mode Mode = ix86_getNaturalModeForType(type); int NumClasses = ix86_ClassifyArgument(Mode, type, Class, 0); *DontCheckAlignment= true; - if (NumClasses == 1 && (Class[0] == X86_64_INTEGERSI_CLASS || - Class[0] == X86_64_INTEGER_CLASS)) { + if (NumClasses == 1 && Class[0] == X86_64_INTEGER_CLASS) { /* 8 byte object, one int register */ *size = 8; return true; } + if (NumClasses == 1 && Class[0] == X86_64_INTEGERSI_CLASS) { + /* 4 byte object, one int register */ + *size = 4; + return true; + } if (NumClasses == 2 && (Class[0] == X86_64_INTEGERSI_CLASS || Class[0] == X86_64_INTEGER_CLASS)) { - if (Class[1] == X86_64_INTEGERSI_CLASS || - Class[1] == X86_64_INTEGER_CLASS) { + if (Class[1] == X86_64_INTEGER_CLASS) { /* 16 byte object, 2 int registers */ *size = 16; return true; } + if (Class[1] == X86_64_INTEGERSI_CLASS) { + /* 12 byte object, 2 int registers */ + *size = 12; + return true; + } if (Class[1] == X86_64_NO_CLASS) { /* 16 byte object, only 1st register has information */ *size = 8; Modified: llvm-gcc-4.2/trunk/gcc/llvm-abi.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-abi.h?rev=51959&r1=51958&r2=51959&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-abi.h (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-abi.h Wed Jun 4 14:31:55 2008 @@ -570,7 +570,7 @@ Elts.push_back(Type::Int8Ty); Size -= 1; } - assert((origSize || Size == 0) && "Didn't cover value?"); + assert(Size == 0 && "Didn't cover value?"); const StructType *STy = StructType::get(Elts, false); unsigned i = 0; From tonic at nondot.org Wed Jun 4 15:21:59 2008 From: tonic at nondot.org (Tanya Lattner) Date: Wed, 04 Jun 2008 20:21:59 -0000 Subject: [llvm-commits] [llvm] r51962 - in /llvm/branches/release_23: lib/Target/CBackend/CBackend.cpp test/CodeGen/CBackend/2008-06-04-IndirectMem.ll Message-ID: <200806042021.m54KLx8x015399@zion.cs.uiuc.edu> Author: tbrethou Date: Wed Jun 4 15:21:59 2008 New Revision: 51962 URL: http://llvm.org/viewvc/llvm-project?rev=51962&view=rev Log: Merge from mainline to fix PR2407. Added: llvm/branches/release_23/test/CodeGen/CBackend/2008-06-04-IndirectMem.ll - copied unchanged from r51952, llvm/trunk/test/CodeGen/CBackend/2008-06-04-IndirectMem.ll Modified: llvm/branches/release_23/lib/Target/CBackend/CBackend.cpp Modified: llvm/branches/release_23/lib/Target/CBackend/CBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_23/lib/Target/CBackend/CBackend.cpp?rev=51962&r1=51961&r2=51962&view=diff ============================================================================== --- llvm/branches/release_23/lib/Target/CBackend/CBackend.cpp (original) +++ llvm/branches/release_23/lib/Target/CBackend/CBackend.cpp Wed Jun 4 15:21:59 2008 @@ -2936,10 +2936,6 @@ void CWriter::visitInlineAsm(CallInst &CI) { InlineAsm* as = cast(CI.getOperand(0)); std::vector Constraints = as->ParseConstraints(); - std::vector > Input; - std::vector > > Output; - std::string Clobber; - unsigned ValueCount = 0; std::vector > ResultVals; if (CI.getType() == Type::VoidTy) @@ -2951,61 +2947,103 @@ ResultVals.push_back(std::make_pair(&CI, -1)); } + // Fix up the asm string for gcc and emit it. + Out << "__asm__ volatile (\"" << gccifyAsm(as->getAsmString()) << "\"\n"; + Out << " :"; + + unsigned ValueCount = 0; + bool IsFirst = true; + + // Convert over all the output constraints. for (std::vector::iterator I = Constraints.begin(), - E = Constraints.end(); I != E; ++I) { + E = Constraints.end(); I != E; ++I) { + + if (I->Type != InlineAsm::isOutput) { + ++ValueCount; + continue; // Ignore non-output constraints. + } + assert(I->Codes.size() == 1 && "Too many asm constraint codes to handle"); std::string C = InterpretASMConstraint(*I); if (C.empty()) continue; - switch (I->Type) { - default: assert(0 && "Unknown asm constraint"); - case InlineAsm::isInput: { - assert(ValueCount >= ResultVals.size() && "Input can't refer to result"); - Value *V = CI.getOperand(ValueCount-ResultVals.size()+1); - Input.push_back(std::make_pair(C, V)); - break; - } - case InlineAsm::isOutput: { - std::pair V; - if (ValueCount < ResultVals.size()) - V = ResultVals[ValueCount]; - else - V = std::make_pair(CI.getOperand(ValueCount-ResultVals.size()+1), -1); - Output.push_back(std::make_pair("="+((I->isEarlyClobber ? "&" : "")+C), - V)); - break; - } - case InlineAsm::isClobber: - Clobber += ",\"" + C + "\""; - continue; // Not an actual argument. + if (!IsFirst) { + Out << ", "; + IsFirst = false; } - ++ValueCount; // Consumes an argument. + + // Unpack the dest. + Value *DestVal; + int DestValNo = -1; + + if (ValueCount < ResultVals.size()) { + DestVal = ResultVals[ValueCount].first; + DestValNo = ResultVals[ValueCount].second; + } else + DestVal = CI.getOperand(ValueCount-ResultVals.size()+1); + + if (I->isEarlyClobber) + C = "&"+C; + + Out << "\"=" << C << "\"(" << GetValueName(DestVal); + if (DestValNo != -1) + Out << ".field" << DestValNo; // Multiple retvals. + Out << ")"; + ++ValueCount; } - // Fix up the asm string for gcc. - std::string asmstr = gccifyAsm(as->getAsmString()); - Out << "__asm__ volatile (\"" << asmstr << "\"\n"; - Out << " :"; - for (unsigned i = 0, e = Output.size(); i != e; ++i) { - if (i) + // Convert over all the input constraints. + Out << "\n :"; + IsFirst = true; + ValueCount = 0; + for (std::vector::iterator I = Constraints.begin(), + E = Constraints.end(); I != E; ++I) { + if (I->Type != InlineAsm::isInput) { + ++ValueCount; + continue; // Ignore non-input constraints. + } + + assert(I->Codes.size() == 1 && "Too many asm constraint codes to handle"); + std::string C = InterpretASMConstraint(*I); + if (C.empty()) continue; + + if (!IsFirst) { Out << ", "; - Out << "\"" << Output[i].first << "\"(" - << GetValueName(Output[i].second.first); - if (Output[i].second.second != -1) - Out << ".field" << Output[i].second.second; // Multiple retvals. + IsFirst = false; + } + + assert(ValueCount >= ResultVals.size() && "Input can't refer to result"); + Value *SrcVal = CI.getOperand(ValueCount-ResultVals.size()+1); + + Out << "\"" << C << "\"("; + if (!I->isIndirect) + writeOperand(SrcVal); + else + writeOperandDeref(SrcVal); Out << ")"; } - Out << "\n :"; - for (unsigned i = 0, e = Input.size(); i != e; ++i) { - if (i) + + // Convert over the clobber constraints. + IsFirst = true; + ValueCount = 0; + for (std::vector::iterator I = Constraints.begin(), + E = Constraints.end(); I != E; ++I) { + if (I->Type != InlineAsm::isClobber) + continue; // Ignore non-input constraints. + + assert(I->Codes.size() == 1 && "Too many asm constraint codes to handle"); + std::string C = InterpretASMConstraint(*I); + if (C.empty()) continue; + + if (!IsFirst) { Out << ", "; - Out << "\"" << Input[i].first << "\"("; - writeOperand(Input[i].second); - Out << ")"; + IsFirst = false; + } + + Out << '\"' << C << '"'; } - if (Clobber.size()) - Out << "\n :" << Clobber.substr(1); + Out << ")"; } From evan.cheng at apple.com Wed Jun 4 17:30:00 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 4 Jun 2008 15:30:00 -0700 Subject: [llvm-commits] [llvm] r51950 - /llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp In-Reply-To: <56F8AB65-32BA-4001-9DE3-518F00D59BD9@mac.com> References: <200806041755.m54Htx0Y010472@zion.cs.uiuc.edu> <56E95044-3895-4B65-9C6B-B3AFFD977323@apple.com> <56F8AB65-32BA-4001-9DE3-518F00D59BD9@mac.com> Message-ID: <461E68AA-30D6-4B4E-BFAB-063B94C37F74@apple.com> I'd like to see code like this being refactored out into a function. Evan >> + LiveInterval& Interval = LI.getOrCreateInterval(I->first); >> + VNInfo* VN = Interval.getNextValue( >> + LI.getInstructionIndex(I->second) + >> LiveIntervals::InstrSlots::DEF, >> + I->second, >> LI.getVNInfoAllocator()); >> + VN->hasPHIKill = true; >> + VN->kills.push_back(LI.getMBBEndIdx(I->second->getParent())); >> + LiveRange LR(LI.getInstructionIndex(I->second) + >> + LiveIntervals::InstrSlots::DEF, >> + LI.getMBBEndIdx(I->second->getParent()) + 1, VN); >> + Interval.addRange(LR); On Jun 4, 2008, at 11:02 AM, Owen Anderson wrote: > I don't follow. What would this helper do? > > --Owen > > On Jun 4, 2008, at 10:59 AM, Evan Cheng wrote: > >> Hi Owen, >> >> While you are doing this and cleaning up liveintervals. Can you add >> helper function to liveinterval for creating copy intervals etc.? >> >> Evan >> >> On Jun 4, 2008, at 10:55 AM, Owen Anderson wrote: >> >>> >>> + >>> + // Renumber the instructions so that we can perform the index >>> computations >>> + // needed to create new live intervals. >>> + LI.computeNumbering(); >>> + >>> + // For copies that we inserted at the ends of predecessors, we >>> construct >>> + // live intervals. This is pretty easy, since we know that the >>> destination >>> + // register cannot have be in live at that point previously. We >>> just have >>> + // to make sure that, for registers that serve as inputs to more >>> than one >>> + // PHI, we don't create multiple overlapping live intervals. >>> + std::set RegHandled; >>> + for (SmallVector, 4>::iterator >>> I = >>> + InsertedPHIDests.begin(), E = InsertedPHIDests.end(); I != >>> E; ++I) { >>> + if (!RegHandled.count(I->first)) { >>> + LiveInterval& Interval = LI.getOrCreateInterval(I->first); >>> + VNInfo* VN = Interval.getNextValue( >>> + LI.getInstructionIndex(I->second) + >>> LiveIntervals::InstrSlots::DEF, >>> + I->second, >>> LI.getVNInfoAllocator()); >>> + VN->hasPHIKill = true; >>> + VN->kills.push_back(LI.getMBBEndIdx(I->second->getParent())); >>> + LiveRange LR(LI.getInstructionIndex(I->second) + >>> + LiveIntervals::InstrSlots::DEF, >>> + LI.getMBBEndIdx(I->second->getParent()) + 1, >>> VN); >>> + Interval.addRange(LR); >>> + >>> + RegHandled.insert(I->first); >>> + } >>> + } >>> } >>> >>> /// InsertCopies - insert copies into MBB and all of its successors >>> >>> >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20080604/026bdd7b/attachment.html From resistor at mac.com Wed Jun 4 18:20:38 2008 From: resistor at mac.com (Owen Anderson) Date: Wed, 04 Jun 2008 16:20:38 -0700 Subject: [llvm-commits] [llvm] r51892 - /llvm/trunk/lib/VMCore/PassManager.cpp In-Reply-To: <200806030120.m531K2JU013559@zion.cs.uiuc.edu> References: <200806030120.m531K2JU013559@zion.cs.uiuc.edu> Message-ID: <0D0AB52E-5823-4D97-A004-753AE6DA0991@mac.com> THANK YOU! --Owen On Jun 2, 2008, at 6:20 PM, Devang Patel wrote: > Author: dpatel > Date: Mon Jun 2 20:20:02 2008 > New Revision: 51892 > > URL: http://llvm.org/viewvc/llvm-project?rev=51892&view=rev > Log: > "Unable to schedule required by " is more helpful then > "Unable to handle Pass that requires lower level Analysis pass" > > Modified: > llvm/trunk/lib/VMCore/PassManager.cpp > > Modified: llvm/trunk/lib/VMCore/PassManager.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/PassManager.cpp?rev=51892&r1=51891&r2=51892&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/VMCore/PassManager.cpp (original) > +++ llvm/trunk/lib/VMCore/PassManager.cpp Mon Jun 2 20:20:02 2008 > @@ -930,7 +930,11 @@ > // When Pass manager is not able to order required analysis info, > Pass manager > // checks whether any lower level manager will be able to provide > this > // analysis info on demand or not. > - assert (0 && "Unable to handle Pass that requires lower level > Analysis pass"); > +#ifndef NDEBUG > + cerr << "Unable to schedule " << RequiredPass->getPassName(); > + cerr << " required by " << P->getPassName() << "\n"; > +#endif > + assert (0 && "Unable to schedule pass"); > } > > // Destructor > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From evan.cheng at apple.com Wed Jun 4 18:37:54 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 04 Jun 2008 23:37:54 -0000 Subject: [llvm-commits] [llvm] r51970 - in /llvm/trunk: lib/CodeGen/SelectionDAG/SelectionDAG.cpp test/CodeGen/X86/2008-06-04-MemCpyLoweringBug.ll Message-ID: <200806042337.m54NbsJW020562@zion.cs.uiuc.edu> Author: evancheng Date: Wed Jun 4 18:37:54 2008 New Revision: 51970 URL: http://llvm.org/viewvc/llvm-project?rev=51970&view=rev Log: Fix a memcpy lowering bug. Even though the memcpy alignment is smaller than the desired alignment, the frame destination alignment may still be larger than the desired alignment. Don't change its alignment to something smaller. Added: llvm/trunk/test/CodeGen/X86/2008-06-04-MemCpyLoweringBug.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=51970&r1=51969&r2=51970&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Jun 4 18:37:54 2008 @@ -2633,8 +2633,9 @@ if (AllowUnalign) VT = MVT::iAny; } else { - // Give the stack frame object a larger alignment. - MFI->setObjectAlignment(FI, NewAlign); + // Give the stack frame object a larger alignment if needed. + if (MFI->getObjectAlignment(FI) < NewAlign) + MFI->setObjectAlignment(FI, NewAlign); Align = NewAlign; } } Added: llvm/trunk/test/CodeGen/X86/2008-06-04-MemCpyLoweringBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-06-04-MemCpyLoweringBug.ll?rev=51970&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2008-06-04-MemCpyLoweringBug.ll (added) +++ llvm/trunk/test/CodeGen/X86/2008-06-04-MemCpyLoweringBug.ll Wed Jun 4 18:37:54 2008 @@ -0,0 +1,19 @@ +; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -mattr=+sse2 -disable-fp-elim | grep subl | grep 24 + + %struct.argument_t = type { i8*, %struct.argument_t*, i32, %struct.ipc_type_t*, i32, void (...)*, void (...)*, void (...)*, void (...)*, void (...)*, i8*, i8*, i8*, i8*, i8*, i32, i32, i32, %struct.routine*, %struct.argument_t*, %struct.argument_t*, %struct.argument_t*, %struct.argument_t*, %struct.argument_t*, %struct.argument_t*, %struct.argument_t*, i32, i32, i32, i32, i32, i32 } + %struct.ipc_type_t = type { i8*, %struct.ipc_type_t*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8*, i8*, i32, i32, i32, i32, i32, i32, %struct.ipc_type_t*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8* } + %struct.routine = type opaque +@"\01LC" = external constant [11 x i8] ; <[11 x i8]*> [#uses=1] + +define i8* @InArgMsgField(%struct.argument_t* %arg, i8* %str) nounwind { +entry: + %who = alloca [20 x i8] ; <[20 x i8]*> [#uses=1] + %who1 = getelementptr [20 x i8]* %who, i32 0, i32 0 ; [#uses=2] + call void @llvm.memset.i32( i8* %who1, i8 0, i32 20, i32 1 ) + call void @llvm.memcpy.i32( i8* %who1, i8* getelementptr ([11 x i8]* @"\01LC", i32 0, i32 0), i32 11, i32 1 ) + unreachable +} + +declare void @llvm.memset.i32(i8*, i8, i32, i32) nounwind + +declare void @llvm.memcpy.i32(i8*, i8*, i32, i32) nounwind From dalej at apple.com Wed Jun 4 19:01:22 2008 From: dalej at apple.com (Dale Johannesen) Date: Thu, 05 Jun 2008 00:01:22 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r51971 - /llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp Message-ID: <200806050001.m5501MXh004719@zion.cs.uiuc.edu> Author: johannes Date: Wed Jun 4 19:01:22 2008 New Revision: 51971 URL: http://llvm.org/viewvc/llvm-project?rev=51971&view=rev Log: X86-64 ABI: pass structs shorter than 4 bytes as i16 or i8. Fixes 477.dealII. Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp?rev=51971&r1=51970&r2=51971&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp Wed Jun 4 19:01:22 2008 @@ -1316,29 +1316,27 @@ int NumClasses = ix86_ClassifyArgument(Mode, type, Class, 0); *DontCheckAlignment= true; if (NumClasses == 1 && Class[0] == X86_64_INTEGER_CLASS) { - /* 8 byte object, one int register */ + // one int register *size = 8; return true; } if (NumClasses == 1 && Class[0] == X86_64_INTEGERSI_CLASS) { - /* 4 byte object, one int register */ - *size = 4; + // one shorter-than-64-bits register + HOST_WIDE_INT Bytes = + (Mode == BLKmode) ? int_size_in_bytes(type) : (int) GET_MODE_SIZE(Mode); + *size = Bytes; return true; } if (NumClasses == 2 && (Class[0] == X86_64_INTEGERSI_CLASS || Class[0] == X86_64_INTEGER_CLASS)) { if (Class[1] == X86_64_INTEGER_CLASS) { - /* 16 byte object, 2 int registers */ + // 16 byte object, 2 int registers *size = 16; return true; } - if (Class[1] == X86_64_INTEGERSI_CLASS) { - /* 12 byte object, 2 int registers */ - *size = 12; - return true; - } + // IntegerSI can occur only as element 0. if (Class[1] == X86_64_NO_CLASS) { - /* 16 byte object, only 1st register has information */ + // 16 byte object, only 1st register has information *size = 8; return true; } From dalej at apple.com Wed Jun 4 20:24:43 2008 From: dalej at apple.com (Dale Johannesen) Date: Thu, 05 Jun 2008 01:24:43 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r51973 - /llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp Message-ID: <200806050124.m551OhJf016819@zion.cs.uiuc.edu> Author: johannes Date: Wed Jun 4 20:24:40 2008 New Revision: 51973 URL: http://llvm.org/viewvc/llvm-project?rev=51973&view=rev Log: Adjust preceding patch, it seems INTEGER_SI_CLASS can be returned for values too big to fit in an SI. Live and learn. Fixes regression introduced into struct-layout-1. Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp?rev=51973&r1=51972&r2=51973&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp Wed Jun 4 20:24:40 2008 @@ -1315,16 +1315,17 @@ enum machine_mode Mode = ix86_getNaturalModeForType(type); int NumClasses = ix86_ClassifyArgument(Mode, type, Class, 0); *DontCheckAlignment= true; - if (NumClasses == 1 && Class[0] == X86_64_INTEGER_CLASS) { + if (NumClasses == 1 && (Class[0] == X86_64_INTEGER_CLASS || + Class[0] == X86_64_INTEGERSI_CLASS)) { // one int register - *size = 8; - return true; - } - if (NumClasses == 1 && Class[0] == X86_64_INTEGERSI_CLASS) { - // one shorter-than-64-bits register HOST_WIDE_INT Bytes = (Mode == BLKmode) ? int_size_in_bytes(type) : (int) GET_MODE_SIZE(Mode); - *size = Bytes; + if (Bytes>4) + *size = 8; + else if (Bytes>2) + *size = 4; + else + *size = Bytes; return true; } if (NumClasses == 2 && (Class[0] == X86_64_INTEGERSI_CLASS || From isanbard at gmail.com Wed Jun 4 20:31:20 2008 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 05 Jun 2008 01:31:20 -0000 Subject: [llvm-commits] [llvm] r51974 - /llvm/tags/Apple/llvmCore-2047/ Message-ID: <200806050131.m551VKs2018934@zion.cs.uiuc.edu> Author: void Date: Wed Jun 4 20:31:20 2008 New Revision: 51974 URL: http://llvm.org/viewvc/llvm-project?rev=51974&view=rev Log: Creating llvmCore-2047 branch Added: llvm/tags/Apple/llvmCore-2047/ - copied from r51973, llvm/trunk/ From isanbard at gmail.com Wed Jun 4 20:31:27 2008 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 05 Jun 2008 01:31:27 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r51975 - /llvm-gcc-4.2/tags/Apple/llvmgcc42-2047/ Message-ID: <200806050131.m551VRaR019006@zion.cs.uiuc.edu> Author: void Date: Wed Jun 4 20:31:27 2008 New Revision: 51975 URL: http://llvm.org/viewvc/llvm-project?rev=51975&view=rev Log: Creating llvmgcc42-2047 branch Added: llvm-gcc-4.2/tags/Apple/llvmgcc42-2047/ - copied from r51974, llvm-gcc-4.2/trunk/ From sabre at nondot.org Thu Jun 5 01:25:56 2008 From: sabre at nondot.org (Chris Lattner) Date: Thu, 05 Jun 2008 06:25:56 -0000 Subject: [llvm-commits] [llvm] r51977 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <200806050625.m556Pubf032534@zion.cs.uiuc.edu> Author: lattner Date: Thu Jun 5 01:25:56 2008 New Revision: 51977 URL: http://llvm.org/viewvc/llvm-project?rev=51977&view=rev Log: Start adding 2.3 content. Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=51977&r1=51976&r2=51977&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Thu Jun 5 01:25:56 2008 @@ -23,9 +23,6 @@

Written by the LLVM Team

-

THIS IS A WORK IN PROGRESS FOR LLVM 2.3 (currently in -progress on SVN HEAD)

-
Introduction @@ -62,7 +59,7 @@

This is the fourteenth public release of the LLVM Compiler Infrastructure. -It includes many features and refinements from LLVM 2.2.

+It includes a large number of features and refinements from LLVM 2.2.

@@ -82,45 +79,55 @@

LLVM 2.2 was the last LLVM release to support llvm-gcc 4.0 and llvm-upgrade. llvm-gcc 4.0 has been replaced with llvm-gcc 4.2. llvm-upgrade was useful for -upgrading llvm 1.9 files to llvm 2.x syntax, but you can always use a previous -llvm release to do this.

+upgrading LLVM 1.9 files to LLVM 2.x syntax, but you can always use a previous +LLVM release to do this. One nice impact of this is that the LLVM regressionn +test suite no longer depends on llvm-upgrade, which makes it run faster.

-llvm-gcc 4.2 and clang +Major New Features
-

LLVM 2.3 fully supports llvm-gcc 4.2 front-end.

+

LLVM 2.3 includes several major new capabilities:

-

The clang project is an effort to build -a set of new 'llvm native' front-end technologies for the LLVM optimizer -and code generator. Currently, its C and Objective-C support is maturing -nicely, and it has advanced source-to-source analysis and transformation -capabilities. If you are interested in building source-level tools for C and -Objective-C (and eventually C++), you should take a look. However, note that -clang is not an official part of the LLVM 2.3 release. If you are interested in -this project, please see its web site.

+
    +
  • Multiple Return Value Support
    • +
+
-Major New Features +llvm-gcc 4.2 Improvements and Clang
-

LLVM 2.3 includes several major new capabilities:

+

LLVM 2.3 fully supports llvm-gcc 4.2 front-end.

-
    -
+

llvm-gcc 4.2 includes numerous fixes to better support the Objective-C +front-end. Objective-C now works very well on Mac OS/X.

+ +

llvm-gcc 4.2 includes many other fixes which improve conformance with the +relevant parts of the GCC testsuite.

+ +

The clang project is an effort to build +a set of new 'llvm native' front-end technologies for the LLVM optimizer +and code generator. Currently, its C and Objective-C support is maturing +nicely, and it has advanced source-to-source analysis and transformation +capabilities. If you are interested in building source-level tools for C and +Objective-C (and eventually C++), you should take a look. However, note that +clang is not an official part of the LLVM 2.3 release. If you are interested in +this project, please see its web site.

+
LLVM Core Improvements @@ -130,8 +137,12 @@

New features include:

-
    +Common linkage? + +Atomic operation support, Alpha, X86, PowerPC. "__sync_syncronize" + +
@@ -148,7 +159,8 @@ faster:

    -
  • MemOperand in the code generator.
    • +
  • MemOperand in the code generator: describe me!.
    • +
  • i128 support and APInt through most of codegen.
@@ -165,8 +177,9 @@
    -
  • Index set splitting on by default.
    • - +
  • Loop index set splitting on by default: describe me.
    • +
  • LLVM includes a new memcpy optimization pass which optimizes out dead +memcpy calls and unneeded copies of aggregates.
@@ -182,6 +195,25 @@

    +
  • llvm-gcc's X86-64 ABI conformance is far improved, particularly in the + area of passing and returning structures by value. llvm-gcc Compiled code + now interoperates very well on X86-64 systems with other compilers.
    • + +
  • The LLVM X86 backend now supports the support SSE 4.1 instruction set, and + the llvm-gcc 4.2 front-end supports the SSE 4.1 compiler builtins.
    • + +
  • The X86 backend now does a number of optimizations that aim to avoid + converting numbers back and forth from SSE registers to the X87 floating + point stack.
    • + +
  • The X86 backend now supports the "sseregparm" options in GCC, which allow + functions to be tagged as passing floating point values in SSE + registers.
    • + +
  • Trampolines (taking the address of a nested function) now work on + Linux/x86-64.
    • + +
From sabre at nondot.org Thu Jun 5 01:35:40 2008 From: sabre at nondot.org (Chris Lattner) Date: Thu, 05 Jun 2008 06:35:40 -0000 Subject: [llvm-commits] [llvm] r51978 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <200806050635.m556Zfbl000317@zion.cs.uiuc.edu> Author: lattner Date: Thu Jun 5 01:35:40 2008 New Revision: 51978 URL: http://llvm.org/viewvc/llvm-project?rev=51978&view=rev Log: various status updates. Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=51978&r1=51977&r2=51978&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Thu Jun 5 01:35:40 2008 @@ -312,9 +312,6 @@
  • The X86 backend does not yet support inline assembly that uses the X86 floating point stack.
    • -
  • The X86 backend occasionally has alignment - problems on operating systems that don't require 16-byte stack alignment - (including most non-darwin OS's like linux).
  • The X86 backend generates inefficient floating point code when configured to generate code for systems that don't have SSE2.
@@ -422,10 +419,8 @@
- - -
- Notes -
- -
-
    - -

  • llvm-gcc does not support __builtin_apply yet. - See Constructing Calls: Dispatching a call to another function.

    -
    • - -

  • llvm-gcc partially supports these GCC extensions:

    -
      -
    1. Nested Functions: - - As in Algol and Pascal, lexical scoping of functions. - Nested functions are supported, but llvm-gcc does not support - taking the address of a nested function (except on X86 targets) - or non-local gotos.
      2. - -
    2. Function Attributes: - - Declaring that functions have no side effects or that they can never - return.
      - - Supported: alias, always_inline, cdecl, - const, constructor, destructor, - deprecated, fastcall, format, - format_arg, non_null, noinline, - noreturn, nothrow, pure, regparm - section, stdcall, unused, used, - visibility, warn_unused_result, weak
      - - Ignored: malloc, - no_instrument_function
      3. -
    -
    • - -
+

The only major language feature of GCC not supported by llvm-gcc is + the __builtin_apply family of builtins. However, some extensions + are only supported on some targets. For example, trampolines are only + supported on some targets, which are used when you take the address of a + nested function.

-

If you run into GCC extensions which have not been included in any of these -lists, please let us know (also including whether or not they work).

+

If you run into GCC extensions which are not supported, please let us know. +

- Known problems with the C++ front-end + Known problems with the llvm-gcc C++ front-end
@@ -509,8 +467,9 @@ itself, Qt, Mozilla, etc.

    -
  • Exception handling only works well on the X86 and PowerPC targets. -It works well for x86-64 darwin but not x86-64 linux.
    • +
  • Exception handling works well on the X86 and PowerPC targets, including +x86-64 darwin. This works when linking to a libstdc++ compiled by GCC. It is +supported on x86-64 linux, but that is disabled by default in this release.
@@ -518,7 +477,7 @@
- Known problems with the Ada front-end + Known problems with the llvm-gcc Ada front-end
@@ -551,7 +510,7 @@
- Known problems with the Fortran front-end + Known problems with the llvm-gcc Fortran front-end
From tonic at nondot.org Thu Jun 5 01:44:40 2008 From: tonic at nondot.org (Tanya Lattner) Date: Thu, 5 Jun 2008 01:44:40 -0500 Subject: [llvm-commits] CVS: llvm-www/www-index.html Message-ID: <200806050644.m556ie4l000636@zion.cs.uiuc.edu> Changes in directory llvm-www: www-index.html updated: 1.157 -> 1.158 --- Log message: New release date of June 9th. --- Diffs of the changes: (+2 -9) www-index.html | 11 ++--------- 1 files changed, 2 insertions(+), 9 deletions(-) Index: llvm-www/www-index.html diff -u llvm-www/www-index.html:1.157 llvm-www/www-index.html:1.158 --- llvm-www/www-index.html:1.157 Sat May 24 00:15:21 2008 +++ llvm-www/www-index.html Thu Jun 5 01:43:59 2008 @@ -117,15 +117,8 @@
Upcoming Releases
-

LLVM 2.3 release schedule:

-
    -
  • May 9, 2008: Branch creation/Code Freeze (9PM PDT).
    • -
  • May 12, 2008: First round of pre-release testing begins.
    • -
  • May 21, 2008: Pre-release testing ends.
    • -
  • May 28, 2008: Second round of pre-release testing begins.
    • -
  • June 1, 2008: Pre-release testing ends.
    • -
  • June 4, 2008: 2.3 Released.
    • -
+

LLVM 2.3 is in final stages of the release process. +The new release date is June 9, 2008. Thanks for your patience!


From sabre at nondot.org Thu Jun 5 01:57:39 2008 From: sabre at nondot.org (Chris Lattner) Date: Thu, 05 Jun 2008 06:57:39 -0000 Subject: [llvm-commits] [llvm] r51979 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <200806050657.m556veXC001025@zion.cs.uiuc.edu> Author: lattner Date: Thu Jun 5 01:57:39 2008 New Revision: 51979 URL: http://llvm.org/viewvc/llvm-project?rev=51979&view=rev Log: add llvmc2 notes, stack realignment. Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=51979&r1=51978&r2=51979&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Thu Jun 5 01:57:39 2008 @@ -96,6 +96,31 @@
  • Multiple Return Value Support
    • + + +

  • LLVM 2.3 includes a complete reimplementation of the "llvmc" tool. It is +designed to overcome several problems of the original llvmc and to provide a +superset of the features as the 'gcc' driver.

    + +

    The main features of llvmc2 is:

    + +
      +
    • Extended handling of command line options and smart rules for +dispatching them to different tools.
      • +
    • Flexible (and extensible) rules for defining different tools.
      • +
    • The different intermediate steps performed by tools are represented +as edged in the abstract graph.
      • +The 'language' for driver behaviour definition is tablegen and thus +it's relatively easy to add new features. +
    • The definition of driver is transformed into set of C++ classes, thus +no runtime interpretation is needed.
      • +
    + +
    • + + + +
@@ -205,6 +230,9 @@
  • The X86 backend now does a number of optimizations that aim to avoid converting numbers back and forth from SSE registers to the X87 floating point stack.
    • + +
  • The X86 backend supports stack realignment, which is particularly useful for + vector code on OS's without 16-byte aligned stacks.
  • The X86 backend now supports the "sseregparm" options in GCC, which allow functions to be tagged as passing floating point values in SSE @@ -228,6 +256,7 @@

      +
    • LLVM now builds with GCC 4.3.
    • @@ -255,8 +284,7 @@
  • Itanium-based machines running Linux and HP-UX.
    • -

    The core LLVM infrastructure uses -GNU autoconf to adapt itself +

    The core LLVM infrastructure uses GNU autoconf to adapt itself to the machine and operating system on which it is built. However, minor porting may be required to get LLVM to work on new platforms. We welcome your portability patches and reports of successful builds or error messages.

    @@ -297,7 +325,6 @@
  • The MSIL, IA64, Alpha, SPU, and MIPS backends are experimental.
  • The LLC "-filetype=asm" (the default) is the only supported value for this option.
    • -
  • The llvmc tool is not supported.
    • From isanbard at gmail.com Thu Jun 5 02:24:08 2008 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 05 Jun 2008 07:24:08 -0000 Subject: [llvm-commits] [llvm] r51980 - /llvm/trunk/include/llvm/DerivedTypes.h Message-ID: <200806050724.m557O9pX001972@zion.cs.uiuc.edu> Author: void Date: Thu Jun 5 02:24:08 2008 New Revision: 51980 URL: http://llvm.org/viewvc/llvm-project?rev=51980&view=rev Log: Remove unused parameter. Some clients might use -Werror when compiling and cause drama. Modified: llvm/trunk/include/llvm/DerivedTypes.h Modified: llvm/trunk/include/llvm/DerivedTypes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/DerivedTypes.h?rev=51980&r1=51979&r2=51980&view=diff ============================================================================== --- llvm/trunk/include/llvm/DerivedTypes.h (original) +++ llvm/trunk/include/llvm/DerivedTypes.h Thu Jun 5 02:24:08 2008 @@ -292,7 +292,7 @@ inline const Type *getElementType() const { return ContainedTys[0]; } virtual bool indexValid(const Value *V) const; - virtual bool indexValid(unsigned Idx) const { + virtual bool indexValid(unsigned) const { return true; } @@ -302,7 +302,7 @@ virtual const Type *getTypeAtIndex(const Value *) const { return ContainedTys[0]; } - virtual const Type *getTypeAtIndex(unsigned Idx) const { + virtual const Type *getTypeAtIndex(unsigned) const { return ContainedTys[0]; } From matthijs at stdin.nl Thu Jun 5 02:26:15 2008 From: matthijs at stdin.nl (Matthijs Kooijman) Date: Thu, 05 Jun 2008 07:26:15 -0000 Subject: [llvm-commits] [llvm] r51981 - /llvm/trunk/include/llvm/Instructions.h Message-ID: <200806050726.m557QFjq002033@zion.cs.uiuc.edu> Author: matthijs Date: Thu Jun 5 02:26:15 2008 New Revision: 51981 URL: http://llvm.org/viewvc/llvm-project?rev=51981&view=rev Log: Fix 80 column violations. Modified: llvm/trunk/include/llvm/Instructions.h Modified: llvm/trunk/include/llvm/Instructions.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructions.h?rev=51981&r1=51980&r2=51981&view=diff ============================================================================== --- llvm/trunk/include/llvm/Instructions.h (original) +++ llvm/trunk/include/llvm/Instructions.h Thu Jun 5 02:26:15 2008 @@ -379,7 +379,8 @@ /// class GetElementPtrInst : public Instruction { GetElementPtrInst(const GetElementPtrInst &GEPI); - void init(Value *Ptr, Value* const *Idx, unsigned NumIdx, const std::string &Name); + void init(Value *Ptr, Value* const *Idx, unsigned NumIdx, + const std::string &Name); void init(Value *Ptr, Value *Idx, const std::string &Name); template @@ -1456,7 +1457,8 @@ SmallVector Indices; ExtractValueInst(const ExtractValueInst &EVI); - void init(Value *Agg, const unsigned *Idx, unsigned NumIdx, const std::string &Name); + void init(Value *Agg, const unsigned *Idx, unsigned NumIdx, + const std::string &Name); void init(Value *Agg, unsigned Idx, const std::string &Name); template @@ -1663,7 +1665,8 @@ void *operator new(size_t, unsigned); // Do not implement InsertValueInst(const InsertValueInst &IVI); - void init(Value *Agg, Value *Val, const unsigned *Idx, unsigned NumIdx, const std::string &Name); + void init(Value *Agg, Value *Val, const unsigned *Idx, unsigned NumIdx, + const std::string &Name); void init(Value *Agg, Value *Val, unsigned Idx, const std::string &Name); template @@ -1714,7 +1717,7 @@ } template - static InsertValueInst *Create(Value *Agg, Value *Val, InputIterator IdxBegin, + static InsertValueInst *Create(Value *Agg, Value *Val, InputIterator IdxBegin, InputIterator IdxEnd, const std::string &Name = "", Instruction *InsertBefore = 0) { From matthijs at stdin.nl Thu Jun 5 02:26:36 2008 From: matthijs at stdin.nl (Matthijs Kooijman) Date: Thu, 5 Jun 2008 09:26:36 +0200 Subject: [llvm-commits] [llvm] r51937 - in /llvm/trunk: include/llvm/Instructions.h lib/VMCore/Instructions.cpp In-Reply-To: <56BBE960-59A4-47C9-81CD-46F9C5DA1798@apple.com> References: <200806041440.m54EeuB2003772@zion.cs.uiuc.edu> <56BBE960-59A4-47C9-81CD-46F9C5DA1798@apple.com> Message-ID: <20080605072636.GV25337@katherina.student.utwente.nl> > Please adjust these lines to be within 80 columns. Fixed, thanks for the feedback! -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 189 bytes Desc: Digital signature Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20080605/47b0a4a1/attachment.bin From isanbard at gmail.com Thu Jun 5 02:35:27 2008 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 05 Jun 2008 07:35:27 -0000 Subject: [llvm-commits] [llvm] r51982 - /llvm/trunk/include/llvm/Instructions.h Message-ID: <200806050735.m557ZRAV005044@zion.cs.uiuc.edu> Author: void Date: Thu Jun 5 02:35:27 2008 New Revision: 51982 URL: http://llvm.org/viewvc/llvm-project?rev=51982&view=rev Log: Cast because I think I know what I'm doing. There are warnings about converting from 64-bit to 32-bit. Modified: llvm/trunk/include/llvm/Instructions.h Modified: llvm/trunk/include/llvm/Instructions.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructions.h?rev=51982&r1=51981&r2=51982&view=diff ============================================================================== --- llvm/trunk/include/llvm/Instructions.h (original) +++ llvm/trunk/include/llvm/Instructions.h Thu Jun 5 02:35:27 2008 @@ -1602,7 +1602,7 @@ } unsigned getNumIndices() const { // Note: always non-negative - return Indices.size(); + return (unsigned)Indices.size(); } bool hasIndices() const { @@ -1781,7 +1781,7 @@ } unsigned getNumIndices() const { // Note: always non-negative - return Indices.size(); + return (unsigned)Indices.size(); } bool hasIndices() const { From matthijs at stdin.nl Thu Jun 5 02:55:50 2008 From: matthijs at stdin.nl (Matthijs Kooijman) Date: Thu, 05 Jun 2008 07:55:50 -0000 Subject: [llvm-commits] [llvm] r51983 - in /llvm/trunk: docs/Passes.html lib/Analysis/ValueNumbering.cpp lib/Transforms/Scalar/GCSE.cpp lib/Transforms/Scalar/GVN.cpp lib/Transforms/Scalar/GVNPRE.cpp Message-ID: <200806050755.m557to4Z011556@zion.cs.uiuc.edu> Author: matthijs Date: Thu Jun 5 02:55:49 2008 New Revision: 51983 URL: http://llvm.org/viewvc/llvm-project?rev=51983&view=rev Log: Update comments and documentation to reflect that GCSE and ValueNumbering are deprecated by the GVN and GVNPRE passes. Modified: llvm/trunk/docs/Passes.html llvm/trunk/lib/Analysis/ValueNumbering.cpp llvm/trunk/lib/Transforms/Scalar/GCSE.cpp llvm/trunk/lib/Transforms/Scalar/GVN.cpp llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp Modified: llvm/trunk/docs/Passes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/Passes.html?rev=51983&r1=51982&r2=51983&view=diff ============================================================================== --- llvm/trunk/docs/Passes.html (original) +++ llvm/trunk/docs/Passes.html Thu Jun 5 02:55:49 2008 @@ -298,7 +298,7 @@
    - Basic Value Numbering (default GVN impl) + Basic Value Numbering (default Value Numbering impl)

    @@ -307,6 +307,12 @@ lexically identical expressions. This does not require any ahead of time analysis, so it is a very fast default implementation.

    +

    + The ValueNumbering analysis passes are mostly deprecated. They are only used + by the Global Common Subexpression Elimination pass, which + is deprecated by the Global Value Numbering pass (which + does its value numbering on its own). +

    @@ -859,9 +865,13 @@

    This pass is designed to be a very quick global transformation that eliminates global common subexpressions from a function. It does this by - using an existing value numbering implementation to identify the common + using an existing value numbering analysis pass to identify the common subexpressions, eliminating them when possible.

    +

    + This pass is deprecated by the Global Value Numbering pass + (which does a better job with its own value numbering). +

    @@ -899,6 +909,10 @@ This pass performs global value numbering to eliminate fully redundant instructions. It also performs simple dead load elimination.

    +

    + Note that this pass does the value numbering itself, it does not use the + ValueNumbering analysis passes. +

    @@ -916,6 +930,10 @@ live ranges, and should be used with caution on platforms that are very sensitive to register pressure.

    +

    + Note that this pass does the value numbering itself, it does not use the + ValueNumbering analysis passes. +

    Modified: llvm/trunk/lib/Analysis/ValueNumbering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ValueNumbering.cpp?rev=51983&r1=51982&r2=51983&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ValueNumbering.cpp (original) +++ llvm/trunk/lib/Analysis/ValueNumbering.cpp Thu Jun 5 02:55:49 2008 @@ -10,6 +10,10 @@ // This file implements the non-abstract Value Numbering methods as well as a // default implementation for the analysis group. // +// The ValueNumbering analysis pass is mostly deprecated. It is only used by the +// Global Common Subexpression Elimination pass, which is deprecated by the +// Global Value Numbering pass (which does its value numbering on its own). +// //===----------------------------------------------------------------------===// #include "llvm/Analysis/Passes.h" Modified: llvm/trunk/lib/Transforms/Scalar/GCSE.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GCSE.cpp?rev=51983&r1=51982&r2=51983&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/GCSE.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/GCSE.cpp Thu Jun 5 02:55:49 2008 @@ -9,9 +9,12 @@ // // This pass is designed to be a very quick global transformation that // eliminates global common subexpressions from a function. It does this by -// using an existing value numbering implementation to identify the common +// using an existing value numbering analysis pass to identify the common // subexpressions, eliminating them when possible. // +// This pass is deprecated by the Global Value Numbering pass (which does a +// better job with its own value numbering). +// //===----------------------------------------------------------------------===// #define DEBUG_TYPE "gcse" Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVN.cpp?rev=51983&r1=51982&r2=51983&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/GVN.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/GVN.cpp Thu Jun 5 02:55:49 2008 @@ -10,6 +10,9 @@ // This pass performs global value numbering to eliminate fully redundant // instructions. It also performs simple dead load elimination. // +// Note that this pass does the value numbering itself, it does not use the +// ValueNumbering analysis passes. +// //===----------------------------------------------------------------------===// #define DEBUG_TYPE "gvn" Modified: llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp?rev=51983&r1=51982&r2=51983&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/GVNPRE.cpp Thu Jun 5 02:55:49 2008 @@ -16,6 +16,9 @@ // live ranges, and should be used with caution on platforms that are very // sensitive to register pressure. // +// Note that this pass does the value numbering itself, it does not use the +// ValueNumbering analysis passes. +// //===----------------------------------------------------------------------===// #define DEBUG_TYPE "gvnpre" From isanbard at gmail.com Thu Jun 5 02:56:05 2008 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 05 Jun 2008 07:56:05 -0000 Subject: [llvm-commits] [llvm] r51984 - /llvm/tags/Apple/llvmCore-2047/ Message-ID: <200806050756.m557u5Ce011580@zion.cs.uiuc.edu> Author: void Date: Thu Jun 5 02:56:05 2008 New Revision: 51984 URL: http://llvm.org/viewvc/llvm-project?rev=51984&view=rev Log: Redoing tag. Removed: llvm/tags/Apple/llvmCore-2047/ From isanbard at gmail.com Thu Jun 5 02:56:49 2008 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 05 Jun 2008 07:56:49 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r51985 - /llvm-gcc-4.2/tags/Apple/llvmgcc42-2047/ Message-ID: <200806050756.m557un4D011611@zion.cs.uiuc.edu> Author: void Date: Thu Jun 5 02:56:49 2008 New Revision: 51985 URL: http://llvm.org/viewvc/llvm-project?rev=51985&view=rev Log: Redoing tag. Removed: llvm-gcc-4.2/tags/Apple/llvmgcc42-2047/ From isanbard at gmail.com Thu Jun 5 02:58:06 2008 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 05 Jun 2008 07:58:06 -0000 Subject: [llvm-commits] [llvm] r51986 - /llvm/tags/Apple/llvmCore-2047/ Message-ID: <200806050758.m557w6In011655@zion.cs.uiuc.edu> Author: void Date: Thu Jun 5 02:58:06 2008 New Revision: 51986 URL: http://llvm.org/viewvc/llvm-project?rev=51986&view=rev Log: Creating llvmCore-2047 branch Added: llvm/tags/Apple/llvmCore-2047/ - copied from r51985, llvm/trunk/ From isanbard at gmail.com Thu Jun 5 02:58:12 2008 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 05 Jun 2008 07:58:12 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r51987 - /llvm-gcc-4.2/tags/Apple/llvmgcc42-2047/ Message-ID: <200806050758.m557wCK8011668@zion.cs.uiuc.edu> Author: void Date: Thu Jun 5 02:58:12 2008 New Revision: 51987 URL: http://llvm.org/viewvc/llvm-project?rev=51987&view=rev Log: Creating llvmgcc42-2047 branch Added: llvm-gcc-4.2/tags/Apple/llvmgcc42-2047/ - copied from r51986, llvm-gcc-4.2/trunk/ From sabre at nondot.org Thu Jun 5 03:02:50 2008 From: sabre at nondot.org (Chris Lattner) Date: Thu, 05 Jun 2008 08:02:50 -0000 Subject: [llvm-commits] [llvm] r51988 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <200806050802.m5582oI7011831@zion.cs.uiuc.edu> Author: lattner Date: Thu Jun 5 03:02:49 2008 New Revision: 51988 URL: http://llvm.org/viewvc/llvm-project?rev=51988&view=rev Log: more updates and random notes, including changes up through Week-of-Mon-20080324. Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=51988&r1=51987&r2=51988&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Thu Jun 5 03:02:49 2008 @@ -23,6 +23,8 @@

    Written by the LLVM Team

    + +

    Introduction @@ -64,7 +66,6 @@
    -Removed features in LLVM 2.3 +Major Changes in LLVM 2.3
    @@ -83,6 +84,9 @@ LLVM release to do this. One nice impact of this is that the LLVM regressionn test suite no longer depends on llvm-upgrade, which makes it run faster.

    +

    LLVM 2.3 renames the LLVMBuilder and LLVMFoldingBuilder classes to + IRBuilder.

    +
    @@ -118,8 +122,11 @@ +
  • Reimplemented LTO interface in + C.
    • +
  • kaleidoscope tutorial in ocaml.
    • @@ -165,7 +172,7 @@ Common linkage? -Atomic operation support, Alpha, X86, PowerPC. "__sync_syncronize" +Atomic operation support, Alpha, X86, X86-64, PowerPC. "__sync_synchronize"
    @@ -186,6 +193,7 @@
    • MemOperand in the code generator: describe me!.
    • i128 support and APInt through most of codegen.
      • +
    • Several compile time speedups for code with large basic blocks.
    @@ -204,7 +212,9 @@
  • Loop index set splitting on by default: describe me.
  • LLVM includes a new memcpy optimization pass which optimizes out dead -memcpy calls and unneeded copies of aggregates.
    • +memcpy calls, unneeded copies of aggregates, and handles the return slot +optimization. The LLVM optimizer now notices long sequences of consequtive +stores and merges them into memcpy's where profitable. @@ -212,7 +222,7 @@
    -Target Specific Improvements +X86/X86-64 Specific Improvements
    @@ -241,6 +251,8 @@
  • Trampolines (taking the address of a nested function) now work on Linux/x86-64.
    • +
  • __builtin_prefetch is now compiled into the appropriate prefetch + instructions instead of being ignored.
    • @@ -248,6 +260,25 @@
    +Other Target Specific Improvements +
    + +
    +

    New target-specific features include: +

    + +
      +
    • The LLVM C backend now supports vectors code.
      • + + +
    + +
    + + + + +
    Other Improvements
    @@ -257,6 +288,7 @@
    • LLVM now builds with GCC 4.3.
      • +
    • llvm2cpp tool was moved into llc, use llc -march=cpp
    @@ -337,8 +369,9 @@
    From matthijs at stdin.nl Thu Jun 5 03:04:58 2008 From: matthijs at stdin.nl (Matthijs Kooijman) Date: Thu, 05 Jun 2008 08:04:58 -0000 Subject: [llvm-commits] [llvm] r51989 - in /llvm/trunk: include/llvm/Support/CallSite.h lib/VMCore/Instructions.cpp Message-ID: <200806050804.m5584wBo011898@zion.cs.uiuc.edu> Author: matthijs Date: Thu Jun 5 03:04:58 2008 New Revision: 51989 URL: http://llvm.org/viewvc/llvm-project?rev=51989&view=rev Log: * Make CallSite::hasArgument const and let it take a const parameter. Modified: llvm/trunk/include/llvm/Support/CallSite.h llvm/trunk/lib/VMCore/Instructions.cpp Modified: llvm/trunk/include/llvm/Support/CallSite.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/CallSite.h?rev=51989&r1=51988&r2=51989&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/CallSite.h (original) +++ llvm/trunk/include/llvm/Support/CallSite.h Thu Jun 5 03:04:58 2008 @@ -132,7 +132,7 @@ /// hasArgument - Returns true if this CallSite passes the given Value* as an /// argument to the called function. - bool hasArgument(Value *Arg); + bool hasArgument(const Value *Arg) const; /// arg_iterator - The type of iterator to use when looping over actual /// arguments at this call site... Modified: llvm/trunk/lib/VMCore/Instructions.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instructions.cpp?rev=51989&r1=51988&r2=51989&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Instructions.cpp (original) +++ llvm/trunk/lib/VMCore/Instructions.cpp Thu Jun 5 03:04:58 2008 @@ -91,7 +91,7 @@ cast(I)->setDoesNotThrow(doesNotThrow); } -bool CallSite::hasArgument(Value *Arg) { +bool CallSite::hasArgument(const Value *Arg) const { for (arg_iterator AI = this->arg_begin(), E = this->arg_end(); AI != E; ++AI) if (AI->get() == Arg) return true; From matthijs at stdin.nl Thu Jun 5 03:05:14 2008 From: matthijs at stdin.nl (Matthijs Kooijman) Date: Thu, 5 Jun 2008 10:05:14 +0200 Subject: [llvm-commits] [llvm] r51946 - in /llvm/trunk: include/llvm/Support/CallSite.h lib/VMCore/Instructions.cpp In-Reply-To: References: <200806041631.m54GVCiV007208@zion.cs.uiuc.edu> Message-ID: <20080605080514.GW25337@katherina.student.utwente.nl> > This is nice, but I think the method should be marked 'const' and take > a const Value*. Fixed. -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 189 bytes Desc: Digital signature Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20080605/27e4ad4f/attachment.bin From matthijs at stdin.nl Thu Jun 5 03:34:26 2008 From: matthijs at stdin.nl (Matthijs Kooijman) Date: Thu, 05 Jun 2008 08:34:26 -0000 Subject: [llvm-commits] [llvm] r51990 - /llvm/trunk/lib/Transforms/IPO/DeadArgumentElimination.cpp Message-ID: <200806050834.m558YQZp012762@zion.cs.uiuc.edu> Author: matthijs Date: Thu Jun 5 03:34:25 2008 New Revision: 51990 URL: http://llvm.org/viewvc/llvm-project?rev=51990&view=rev Log: Use use_iterator::getOperandNo instead of CallSite::hasArgument to check if a function is passed as an argument instead of called. Also do this check a bit earlier. Modified: llvm/trunk/lib/Transforms/IPO/DeadArgumentElimination.cpp Modified: llvm/trunk/lib/Transforms/IPO/DeadArgumentElimination.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/DeadArgumentElimination.cpp?rev=51990&r1=51989&r2=51990&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/DeadArgumentElimination.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/DeadArgumentElimination.cpp Thu Jun 5 03:34:25 2008 @@ -302,6 +302,12 @@ FunctionIntrinsicallyLive = true; else for (Value::use_iterator I = F.use_begin(), E = F.use_end(); I != E; ++I) { + // If the function is PASSED IN as an argument, its address has been taken + if (I.getOperandNo() != 0) { + FunctionIntrinsicallyLive = true; + break; + } + // If this use is anything other than a call site, the function is alive. CallSite CS = CallSite::get(*I); Instruction *TheCall = CS.getInstruction(); @@ -329,13 +335,6 @@ RetValLiveness = Live; break; } - - // If the function is PASSED IN as an argument, its address has been taken - - if (CS.hasArgument(&F)) { - FunctionIntrinsicallyLive = true; - break; - } } if (FunctionIntrinsicallyLive) { From matthijs at stdin.nl Thu Jun 5 03:48:33 2008 From: matthijs at stdin.nl (Matthijs Kooijman) Date: Thu, 05 Jun 2008 08:48:33 -0000 Subject: [llvm-commits] [llvm] r51991 - in /llvm/trunk: lib/Transforms/IPO/StructRetPromotion.cpp test/Transforms/SRETPromotion/2008-06-04-function-pointer-passing.ll Message-ID: <200806050848.m558mX0h013136@zion.cs.uiuc.edu> Author: matthijs Date: Thu Jun 5 03:48:32 2008 New Revision: 51991 URL: http://llvm.org/viewvc/llvm-project?rev=51991&view=rev Log: Let StructRetPromotion check if it's users are really calling it and not passing its pointer. Fixes test with added testcase. Added: llvm/trunk/test/Transforms/SRETPromotion/2008-06-04-function-pointer-passing.ll Modified: llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp Modified: llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp?rev=51991&r1=51990&r2=51991&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp Thu Jun 5 03:48:32 2008 @@ -158,6 +158,10 @@ for (Value::use_iterator FnUseI = F->use_begin(), FnUseE = F->use_end(); FnUseI != FnUseE; ++FnUseI) { + // The function is passed in as an argument to (possibly) another function, + // we can't change it! + if (FnUseI.getOperandNo() != 0) + return false; CallSite CS = CallSite::get(*FnUseI); Instruction *Call = CS.getInstruction(); Added: llvm/trunk/test/Transforms/SRETPromotion/2008-06-04-function-pointer-passing.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SRETPromotion/2008-06-04-function-pointer-passing.ll?rev=51991&view=auto ============================================================================== --- llvm/trunk/test/Transforms/SRETPromotion/2008-06-04-function-pointer-passing.ll (added) +++ llvm/trunk/test/Transforms/SRETPromotion/2008-06-04-function-pointer-passing.ll Thu Jun 5 03:48:32 2008 @@ -0,0 +1,24 @@ +; This test lures sretpromotion into promoting the sret argument of foo, even +; when the function is used as an argument to bar. It used to not check for +; this, assuming that all users of foo were direct calls, resulting in an +; assertion failure later on. + +; We're mainly testing for opt not to crash, but we'll check to see if the sret +; attribute is still there for good measure. +; RUN: llvm-as < %s | opt -sretpromotion | llvm-dis | grep sret + +%struct.S = type <{ i32, i32 }> + +define i32 @main() { +entry: + %tmp = alloca %struct.S ; <%struct.S*> [#uses=1] + call void @bar( %struct.S* sret %tmp, void (%struct.S*, ...)* @foo ) + ret i32 undef +} + +declare void @bar(%struct.S* sret , void (%struct.S*, ...)*) + +define internal void @foo(%struct.S* sret %agg.result, ...) { +entry: + ret void +} From matthijs at stdin.nl Thu Jun 5 03:55:27 2008 From: matthijs at stdin.nl (Matthijs Kooijman) Date: Thu, 5 Jun 2008 10:55:27 +0200 Subject: [llvm-commits] [llvm] r51947 - in /llvm/trunk/lib: Analysis/IPA/CallGraph.cpp Transforms/IPO/DeadArgumentElimination.cpp In-Reply-To: References: <200806041657.m54GvooK008226@zion.cs.uiuc.edu> Message-ID: <20080605085527.GX25337@katherina.student.utwente.nl> Hi Chris, > Actually, this can be checked in O(1) time by just calling > I.getOperandNo(). If the use_iterator is for the callee operand of > the function, then it is ok. If not, you know it is passing in the > address of the function. The DeadArgElim code was written before > getOperandNo() existed on use_iterator. I fixed this for the DeadArgumentElimination. I left it unchanged for the CallGraph code. It could be done there as well, but it requires some restructuring of code I'm not really into. Gr. Matthijs -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 189 bytes Desc: Digital signature Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20080605/c2129219/attachment.bin From matthijs at stdin.nl Thu Jun 5 03:57:21 2008 From: matthijs at stdin.nl (Matthijs Kooijman) Date: Thu, 05 Jun 2008 08:57:21 -0000 Subject: [llvm-commits] [llvm] r51992 - in /llvm/trunk: lib/Transforms/IPO/StructRetPromotion.cpp test/Transforms/SRETPromotion/2008-06-05-non-call-use.ll Message-ID: <200806050857.m558vLwb013413@zion.cs.uiuc.edu> Author: matthijs Date: Thu Jun 5 03:57:20 2008 New Revision: 51992 URL: http://llvm.org/viewvc/llvm-project?rev=51992&view=rev Log: Let StructRetPromotion check if all if its users are really calls or invokesn, not other instructions. This fixes a crash with the added testcase. Added: llvm/trunk/test/Transforms/SRETPromotion/2008-06-05-non-call-use.ll Modified: llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp Modified: llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp?rev=51992&r1=51991&r2=51992&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp Thu Jun 5 03:57:20 2008 @@ -165,6 +165,10 @@ CallSite CS = CallSite::get(*FnUseI); Instruction *Call = CS.getInstruction(); + // The function is used by something else than a call or invoke instruction, + // we can't change it! + if (!Call) + return false; CallSite::arg_iterator AI = CS.arg_begin(); Value *FirstArg = *AI; Added: llvm/trunk/test/Transforms/SRETPromotion/2008-06-05-non-call-use.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SRETPromotion/2008-06-05-non-call-use.ll?rev=51992&view=auto ============================================================================== --- llvm/trunk/test/Transforms/SRETPromotion/2008-06-05-non-call-use.ll (added) +++ llvm/trunk/test/Transforms/SRETPromotion/2008-06-05-non-call-use.ll Thu Jun 5 03:57:20 2008 @@ -0,0 +1,20 @@ +; This test shows an sret function that is used as an operand to a bitcast. +; StructRetPromotion used to assume that a function was only used by call or +; invoke instructions, making this code cause an assertion failure. + +; We're mainly testing for opt not to crash, but we'll check to see if the sret +; attribute is still there for good measure. +; RUN: llvm-as < %s | opt -sretpromotion | llvm-dis | grep sret + +%struct.S = type <{ i32, i32 }> + +define i32 @main() { +entry: + %bar = bitcast void (%struct.S*)* @foo to i32 ()* + ret i32 undef +} + +define internal void @foo(%struct.S* sret) { +entry: + ret void +} From nicolas.geoffray at lip6.fr Thu Jun 5 07:46:06 2008 From: nicolas.geoffray at lip6.fr (Nicolas Geoffray) Date: Thu, 05 Jun 2008 12:46:06 -0000 Subject: [llvm-commits] [vmkit] r51994 - in /vmkit/trunk: include/mvm/ include/mvm/Threads/ lib/JnJVM/Classpath/ lib/JnJVM/LLVMRuntime/ lib/JnJVM/VMCore/ lib/Mvm/ Message-ID: <200806051246.m55Ck9Iv021293@zion.cs.uiuc.edu> Author: geoffray Date: Thu Jun 5 07:45:58 2008 New Revision: 51994 URL: http://llvm.org/viewvc/llvm-project?rev=51994&view=rev Log: A thin lock implementation on JnJVM. A few things still need to be improved: 1) Make class info locks protected by thin locks. 2) Create "real" IDs for threads. 3) Create a compiler dependent file for builtins (e.g. compare and swap) Modified: vmkit/trunk/include/mvm/JIT.h vmkit/trunk/include/mvm/Threads/Thread.h vmkit/trunk/lib/JnJVM/Classpath/ClasspathVMObject.cpp vmkit/trunk/lib/JnJVM/Classpath/ClasspathVMThread.cpp vmkit/trunk/lib/JnJVM/LLVMRuntime/runtime-default.ll vmkit/trunk/lib/JnJVM/VMCore/JavaInitialise.cpp vmkit/trunk/lib/JnJVM/VMCore/JavaIsolate.cpp vmkit/trunk/lib/JnJVM/VMCore/JavaJIT.cpp vmkit/trunk/lib/JnJVM/VMCore/JavaJIT.h vmkit/trunk/lib/JnJVM/VMCore/JavaJITOpcodes.cpp vmkit/trunk/lib/JnJVM/VMCore/JavaObject.cpp vmkit/trunk/lib/JnJVM/VMCore/JavaObject.h vmkit/trunk/lib/JnJVM/VMCore/JavaRuntimeJIT.cpp vmkit/trunk/lib/JnJVM/VMCore/JavaThread.h vmkit/trunk/lib/JnJVM/VMCore/JnjvmModule.cpp vmkit/trunk/lib/JnJVM/VMCore/JnjvmModule.h vmkit/trunk/lib/JnJVM/VMCore/VirtualTables.cpp vmkit/trunk/lib/Mvm/JIT.cpp vmkit/trunk/lib/Mvm/Main.cpp Modified: vmkit/trunk/include/mvm/JIT.h URL: http://llvm.org/viewvc/llvm-project/vmkit/trunk/include/mvm/JIT.h?rev=51994&r1=51993&r2=51994&view=diff ============================================================================== --- vmkit/trunk/include/mvm/JIT.h (original) +++ vmkit/trunk/include/mvm/JIT.h Thu Jun 5 07:45:58 2008 @@ -93,6 +93,7 @@ extern llvm::Function* llvm_memcpy_i32; extern llvm::Function* llvm_memset_i32; +extern llvm::Function* llvm_atomic_lcs_i32; extern llvm::ExecutionEngine* executionEngine; Modified: vmkit/trunk/include/mvm/Threads/Thread.h URL: http://llvm.org/viewvc/llvm-project/vmkit/trunk/include/mvm/Threads/Thread.h?rev=51994&r1=51993&r2=51994&view=diff ============================================================================== --- vmkit/trunk/include/mvm/Threads/Thread.h (original) +++ vmkit/trunk/include/mvm/Threads/Thread.h Thu Jun 5 07:45:58 2008 @@ -10,6 +10,8 @@ #ifndef MVM_THREAD_H #define MVM_THREAD_H +#include "types.h" + #include "MvmGC.h" #include "mvm/Threads/Key.h" @@ -31,6 +33,7 @@ static mvm::Key* threadKey; Collector* GC; void* baseSP; + uint32 threadID; static Thread* get() { return (Thread*)Thread::threadKey->get(); } Modified: vmkit/trunk/lib/JnJVM/Classpath/ClasspathVMObject.cpp URL: http://llvm.org/viewvc/llvm-project/vmkit/trunk/lib/JnJVM/Classpath/ClasspathVMObject.cpp?rev=51994&r1=51993&r2=51994&view=diff ============================================================================== --- vmkit/trunk/lib/JnJVM/Classpath/ClasspathVMObject.cpp (original) +++ vmkit/trunk/lib/JnJVM/Classpath/ClasspathVMObject.cpp Thu Jun 5 07:45:58 2008 @@ -31,10 +31,11 @@ jobject _src) { JavaObject* src = (JavaObject*)_src; - uint64 size = src->objectSize() + 4; // + VT + uint64 size = src->objectSize() + sizeof(void*); // + VT JavaObject* res = (JavaObject*) JavaThread::get()->isolate->allocateObject(size, src->getVirtualTable()); memcpy(res, src, size); + res->lock = 0; return (jobject)res; } Modified: vmkit/trunk/lib/JnJVM/Classpath/ClasspathVMThread.cpp URL: http://llvm.org/viewvc/llvm-project/vmkit/trunk/lib/JnJVM/Classpath/ClasspathVMThread.cpp?rev=51994&r1=51993&r2=51994&view=diff ============================================================================== --- vmkit/trunk/lib/JnJVM/Classpath/ClasspathVMThread.cpp (original) +++ vmkit/trunk/lib/JnJVM/Classpath/ClasspathVMThread.cpp Thu Jun 5 07:45:58 2008 @@ -62,6 +62,8 @@ JavaIsolate* isolate = (JavaIsolate*)(intern->isolate); ThreadSystem* ts = isolate->threadSystem; bool isDaemon = ClasspathThread::daemon->getVirtualInt8Field(thread); + intern->threadID = (mvm::Thread::self() << 8) & 0x7FFFFF00; + if (!isDaemon) { ts->nonDaemonLock->lock(); Modified: vmkit/trunk/lib/JnJVM/LLVMRuntime/runtime-default.ll URL: http://llvm.org/viewvc/llvm-project/vmkit/trunk/lib/JnJVM/LLVMRuntime/runtime-default.ll?rev=51994&r1=51993&r2=51994&view=diff ============================================================================== --- vmkit/trunk/lib/JnJVM/LLVMRuntime/runtime-default.ll (original) +++ vmkit/trunk/lib/JnJVM/LLVMRuntime/runtime-default.ll Thu Jun 5 07:45:58 2008 @@ -15,7 +15,7 @@ %JavaClass = type { %VT, i32, %VT ,%JavaClass**, i32} ;;; The root of all Java Objects: a VT, a class and a lock. -%JavaObject = type { %VT, %JavaClass*, i8* } +%JavaObject = type { %VT, %JavaClass*, i32 } ;;; Types for Java arrays. A size of 0 means an undefined size. %JavaArray = type { %JavaObject, i32 } @@ -53,9 +53,12 @@ ;;; getVT - Get the VT of the object. declare %VT @getVT(%JavaObject*) readnone -;;; getClass - Get the class of an object +;;; getClass - Get the class of an object. declare %JavaClass* @getClass(%JavaObject*) readnone +;;; getLock - Get the lock of an object. +declare i32* @getLock(%JavaObject*) + ;;; getVTFromClass - Get the VT of a class from its runtime representation. declare %VT @getVTFromClass(%JavaClass*) readnone @@ -112,6 +115,10 @@ ;;; block or method. declare void @JavaObjectRelease(%JavaObject*) +;;; overflowThinLock - Change a thin lock to a fat lock when the thin lock +;;; overflows +declare void @overflowThinLock(%JavaObject*) + ;;; isAssignableFrom - Returns if the objet's class implements the given class. declare i1 @instanceOf(%JavaObject*, %JavaClass*) readnone @@ -128,6 +135,10 @@ ;;; class. declare %JavaObject* @getClassDelegatee(%JavaClass*) readnone +;;; getThreadID - Returns the thread ID of the current thread. Used for thin +;;; locks. +declare i32 @getThreadID() readnone + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Exception methods ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Modified: vmkit/trunk/lib/JnJVM/VMCore/JavaInitialise.cpp URL: http://llvm.org/viewvc/llvm-project/vmkit/trunk/lib/JnJVM/VMCore/JavaInitialise.cpp?rev=51994&r1=51993&r2=51994&view=diff ============================================================================== --- vmkit/trunk/lib/JnJVM/VMCore/JavaInitialise.cpp (original) +++ vmkit/trunk/lib/JnJVM/VMCore/JavaInitialise.cpp Thu Jun 5 07:45:58 2008 @@ -78,8 +78,7 @@ } static void initialiseStatics() { - JavaObject::globalLock = mvm::Lock::allocNormal(); - + Jnjvm* vm = JavaIsolate::bootstrapVM = JavaIsolate::allocateBootstrap(); // Array initialization @@ -192,7 +191,8 @@ extern "C" void ClasspathBoot(); void handler(int val, siginfo_t* info, void* addr) { - printf("Crash in JnJVM at %p\n", addr); + printf("[%d] Crash in JnJVM at %p\n", mvm::Thread::self(), addr); + JavaJIT::printBacktrace(); assert(0); } Modified: vmkit/trunk/lib/JnJVM/VMCore/JavaIsolate.cpp URL: http://llvm.org/viewvc/llvm-project/vmkit/trunk/lib/JnJVM/VMCore/JavaIsolate.cpp?rev=51994&r1=51993&r2=51994&view=diff ============================================================================== --- vmkit/trunk/lib/JnJVM/VMCore/JavaIsolate.cpp (original) +++ vmkit/trunk/lib/JnJVM/VMCore/JavaIsolate.cpp Thu Jun 5 07:45:58 2008 @@ -450,6 +450,8 @@ isolate->bootstrapThread = vm_new(isolate, JavaThread)(); isolate->bootstrapThread->initialise(0, isolate); void* baseSP = mvm::Thread::get()->baseSP; + isolate->bootstrapThread->threadID = (mvm::Thread::self() << 8) & 0x7FFFFF00; + #ifdef MULTIPLE_GC isolate->bootstrapThread->GC = isolate->GC; isolate->GC->inject_my_thread(baseSP); @@ -508,6 +510,7 @@ isolate->bootstrapThread = vm_new(isolate, JavaThread)(); isolate->bootstrapThread->initialise(0, isolate); void* baseSP = mvm::Thread::get()->baseSP; + isolate->bootstrapThread->threadID = (mvm::Thread::self() << 8) & 0x7FFFFF00; #ifdef MULTIPLE_GC isolate->bootstrapThread->GC = isolate->GC; #endif Modified: vmkit/trunk/lib/JnJVM/VMCore/JavaJIT.cpp URL: http://llvm.org/viewvc/llvm-project/vmkit/trunk/lib/JnJVM/VMCore/JavaJIT.cpp?rev=51994&r1=51993&r2=51994&view=diff ============================================================================== --- vmkit/trunk/lib/JnJVM/VMCore/JavaJIT.cpp (original) +++ vmkit/trunk/lib/JnJVM/VMCore/JavaJIT.cpp Thu Jun 5 07:45:58 2008 @@ -276,44 +276,186 @@ return llvmFunction; } +void JavaJIT::monitorEnter(Value* obj) { + std::vector gep; + gep.push_back(mvm::jit::constantZero); + gep.push_back(JnjvmModule::JavaObjectLockOffsetConstant); + Value* lockPtr = GetElementPtrInst::Create(obj, gep.begin(), gep.end(), "", + currentBlock); + Value* threadId = CallInst::Create(JnjvmModule::GetThreadIDFunction, "", + currentBlock); + std::vector atomicArgs; + atomicArgs.push_back(lockPtr); + atomicArgs.push_back(mvm::jit::constantZero); + atomicArgs.push_back(threadId); + + // Do the atomic compare and swap. + Value* atomic = CallInst::Create(mvm::jit::llvm_atomic_lcs_i32, + atomicArgs.begin(), atomicArgs.end(), "", + currentBlock); + + Value* cmp = new ICmpInst(ICmpInst::ICMP_EQ, atomic, mvm::jit::constantZero, + "", currentBlock); + + BasicBlock* OK = createBasicBlock("synchronize passed"); + BasicBlock* NotOK = createBasicBlock("synchronize did not pass"); + BasicBlock* FatLockBB = createBasicBlock("fat lock"); + BasicBlock* ThinLockBB = createBasicBlock("thin lock"); + + BranchInst::Create(OK, NotOK, cmp, currentBlock); + + currentBlock = NotOK; + + // The compare and swap did not pass, look if it's a thin lock + Value* thinMask = ConstantInt::get(Type::Int32Ty, 0x80000000); + Value* isThin = BinaryOperator::createAnd(atomic, thinMask, "", + currentBlock); + cmp = new ICmpInst(ICmpInst::ICMP_EQ, isThin, mvm::jit::constantZero, "", + currentBlock); + + BranchInst::Create(ThinLockBB, FatLockBB, cmp, currentBlock); + + // It's a thin lock. Look if we're the owner of this lock. + currentBlock = ThinLockBB; + Value* idMask = ConstantInt::get(Type::Int32Ty, 0x7FFFFF00); + Value* cptMask = ConstantInt::get(Type::Int32Ty, 0xFF); + Value* IdInLock = BinaryOperator::createAnd(atomic, idMask, "", currentBlock); + Value* owner = new ICmpInst(ICmpInst::ICMP_EQ, threadId, IdInLock, "", + currentBlock); + + BasicBlock* OwnerBB = createBasicBlock("owner thread"); + + BranchInst::Create(OwnerBB, FatLockBB, owner, currentBlock); + currentBlock = OwnerBB; + + // OK, we are the owner, now check if the counter will overflow. + Value* count = BinaryOperator::createAnd(atomic, cptMask, "", currentBlock); + cmp = new ICmpInst(ICmpInst::ICMP_ULT, count, cptMask, "", currentBlock); + + BasicBlock* IncCounterBB = createBasicBlock("Increment counter"); + BasicBlock* OverflowCounterBB = createBasicBlock("Overflow counter"); + + BranchInst::Create(IncCounterBB, OverflowCounterBB, cmp, currentBlock); + currentBlock = IncCounterBB; + + // The counter will not overflow, increment it. + Value* Add = BinaryOperator::createAdd(mvm::jit::constantOne, atomic, "", + currentBlock); + new StoreInst(Add, lockPtr, "", currentBlock); + BranchInst::Create(OK, currentBlock); + + currentBlock = OverflowCounterBB; + + // The counter will overflow, call this function to create a new lock, + // lock it 0x101 times, and pass. + CallInst::Create(JnjvmModule::OverflowThinLockFunction, obj, "", + currentBlock); + BranchInst::Create(OK, currentBlock); + + currentBlock = FatLockBB; + + // Either it's a fat lock or there is contention. + CallInst::Create(JnjvmModule::AquireObjectFunction, obj, "", currentBlock); + BranchInst::Create(OK, currentBlock); + currentBlock = OK; +} + +void JavaJIT::monitorExit(Value* obj) { + std::vector gep; + gep.push_back(mvm::jit::constantZero); + gep.push_back(JnjvmModule::JavaObjectLockOffsetConstant); + Value* lockPtr = GetElementPtrInst::Create(obj, gep.begin(), gep.end(), "", + currentBlock); + Value* lock = new LoadInst(lockPtr, "", currentBlock); + Value* threadId = CallInst::Create(JnjvmModule::GetThreadIDFunction, "", + currentBlock); + + Value* cmp = new ICmpInst(ICmpInst::ICMP_EQ, lock, threadId, "", + currentBlock); + + + BasicBlock* EndUnlock = createBasicBlock("end unlock"); + BasicBlock* LockedOnceBB = createBasicBlock("desynchronize thin lock"); + BasicBlock* NotLockedOnceBB = + createBasicBlock("simple desynchronize did not pass"); + BasicBlock* FatLockBB = createBasicBlock("fat lock"); + BasicBlock* ThinLockBB = createBasicBlock("thin lock"); + + BranchInst::Create(LockedOnceBB, NotLockedOnceBB, cmp, currentBlock); + + // Locked once, set zero + currentBlock = LockedOnceBB; + new StoreInst(mvm::jit::constantZero, lockPtr, currentBlock); + BranchInst::Create(EndUnlock, currentBlock); + + currentBlock = NotLockedOnceBB; + // Look if the lock is thin. + Value* thinMask = ConstantInt::get(Type::Int32Ty, 0x80000000); + Value* isThin = BinaryOperator::createAnd(lock, thinMask, "", + currentBlock); + cmp = new ICmpInst(ICmpInst::ICMP_EQ, isThin, mvm::jit::constantZero, "", + currentBlock); + + BranchInst::Create(ThinLockBB, FatLockBB, cmp, currentBlock); + + currentBlock = ThinLockBB; + + // Decrement the counter. + Value* Sub = BinaryOperator::createSub(lock, mvm::jit::constantOne, "", + currentBlock); + new StoreInst(Sub, lockPtr, currentBlock); + BranchInst::Create(EndUnlock, currentBlock); + + currentBlock = FatLockBB; + + // Either it's a fat lock or there is contention. + CallInst::Create(JnjvmModule::ReleaseObjectFunction, obj, "", currentBlock); + BranchInst::Create(EndUnlock, currentBlock); + currentBlock = EndUnlock; +} + void JavaJIT::beginSynchronize() { - std::vector argsSync; + Value* obj = 0; if (isVirtual(compilingMethod->access)) { - argsSync.push_back(llvmFunction->arg_begin()); + obj = llvmFunction->arg_begin(); } else { LLVMClassInfo* LCI = (LLVMClassInfo*)module->getClassInfo(compilingClass); - Value* arg = LCI->getStaticVar(this); - argsSync.push_back(arg); + obj = LCI->getStaticVar(this); } -#ifdef SERVICE_VM - if (ServiceDomain::isLockableDomain(compilingClass->isolate)) +#ifndef SERVICE_VM + monitorEnter(obj); +#else + if (ServiceDomain::isLockableDomain(compilingClass->isolate)) { llvm::CallInst::Create(JnjvmModule::AquireObjectInSharedDomainFunction, - argsSync.begin(), argsSync.end(), "", currentBlock); - else + obj, "", currentBlock); + } else { + llvm::CallInst::Create(JnjvmModule::AquireObjectFunction, + obj, "", currentBlock); + } #endif - llvm::CallInst::Create(JnjvmModule::AquireObjectFunction, argsSync.begin(), - argsSync.end(), "", currentBlock); } void JavaJIT::endSynchronize() { - std::vector argsSync; + Value* obj = 0; if (isVirtual(compilingMethod->access)) { - argsSync.push_back(llvmFunction->arg_begin()); + obj = llvmFunction->arg_begin(); } else { LLVMClassInfo* LCI = (LLVMClassInfo*)module->getClassInfo(compilingClass); - Value* arg = LCI->getStaticVar(this); - argsSync.push_back(arg); + obj = LCI->getStaticVar(this); } -#ifdef SERVICE_VM - if (ServiceDomain::isLockableDomain(compilingClass->isolate)) +#ifndef SERVICE_VM + monitorExit(obj); +#else + if (ServiceDomain::isLockableDomain(compilingClass->isolate)) { llvm::CallInst::Create(JnjvmModule::ReleaseObjectInSharedDomainFunction, argsSync.begin(), argsSync.end(), "", currentBlock); - else + } else { + llvm::CallInst::Create(JnjvmModule::ReleaseObjectFunction, argsSync.begin(), + argsSync.end(), "", currentBlock); + } #endif - llvm::CallInst::Create(JnjvmModule::ReleaseObjectFunction, argsSync.begin(), - argsSync.end(), "", currentBlock); } Modified: vmkit/trunk/lib/JnJVM/VMCore/JavaJIT.h URL: http://llvm.org/viewvc/llvm-project/vmkit/trunk/lib/JnJVM/VMCore/JavaJIT.h?rev=51994&r1=51993&r2=51994&view=diff ============================================================================== --- vmkit/trunk/lib/JnJVM/VMCore/JavaJIT.h (original) +++ vmkit/trunk/lib/JnJVM/VMCore/JavaJIT.h Thu Jun 5 07:45:58 2008 @@ -193,6 +193,8 @@ // synchronize void beginSynchronize(); void endSynchronize(); + void monitorEnter(llvm::Value* obj); + void monitorExit(llvm::Value* obj); // fields invoke void getStaticField(uint16 index); Modified: vmkit/trunk/lib/JnJVM/VMCore/JavaJITOpcodes.cpp URL: http://llvm.org/viewvc/llvm-project/vmkit/trunk/lib/JnJVM/VMCore/JavaJITOpcodes.cpp?rev=51994&r1=51993&r2=51994&view=diff ============================================================================== --- vmkit/trunk/lib/JnJVM/VMCore/JavaJITOpcodes.cpp (original) +++ vmkit/trunk/lib/JnJVM/VMCore/JavaJITOpcodes.cpp Thu Jun 5 07:45:58 2008 @@ -2029,11 +2029,15 @@ Value* obj = pop(); #ifdef SERVICE_VM if (ServiceDomain::isLockableDomain(compilingClass->isolate)) - invoke(JnjvmModule::AquireObjectInSharedDomainFunction, obj, "", - currentBlock); + invoke(JnjvmModule::AquireObjectInSharedDomainFunction, obj, "", + currentBlock); else + invoke(JnjvmModule::AquireObjectFunction, obj, "", + currentBlock); +#else + JITVerifyNull(obj); + monitorEnter(obj); #endif - invoke(JnjvmModule::AquireObjectFunction, obj, "", currentBlock); break; } @@ -2041,11 +2045,15 @@ Value* obj = pop(); #ifdef SERVICE_VM if (ServiceDomain::isLockableDomain(compilingClass->isolate)) - invoke(JnjvmModule::ReleaseObjectInSharedDomainFunction, obj, "", - currentBlock); + invoke(JnjvmModule::ReleaseObjectInSharedDomainFunction, obj, "", + currentBlock); else + invoke(JnjvmModule::ReleaseObjectFunction, obj, "", + currentBlock); +#else + JITVerifyNull(obj); + monitorExit(obj); #endif - invoke(JnjvmModule::ReleaseObjectFunction, obj, "", currentBlock); break; } Modified: vmkit/trunk/lib/JnJVM/VMCore/JavaObject.cpp URL: http://llvm.org/viewvc/llvm-project/vmkit/trunk/lib/JnJVM/VMCore/JavaObject.cpp?rev=51994&r1=51993&r2=51994&view=diff ============================================================================== --- vmkit/trunk/lib/JnJVM/VMCore/JavaObject.cpp (original) +++ vmkit/trunk/lib/JnJVM/VMCore/JavaObject.cpp Thu Jun 5 07:45:58 2008 @@ -22,8 +22,6 @@ using namespace jnjvm; -mvm::Lock* JavaObject::globalLock = 0; - void JavaCond::notify() { for (std::vector::iterator i = threads.begin(), e = threads.end(); i!= e;) { @@ -75,22 +73,95 @@ } LockObj* LockObj::allocate() { +#ifdef USE_GC_BOEHM + LockObj* res = new LockObj(); +#else LockObj* res = vm_new(JavaThread::get()->isolate, LockObj)(); +#endif res->lock = mvm::Lock::allocRecursive(); res->varcond = 0; return res; } -void LockObj::aquire() { - lock->lock(); +bool JavaObject::owner() { + uint32 id = mvm::Thread::get()->threadID; + if (id == lock) return true; + if ((lock & 0x7FFFFF00) == id) return true; + if (lock & 0x80000000) { + LockObj* obj = (LockObj*)(lock << 1); + return obj->owner(); + } + return false; +} + +void JavaObject::overflowThinlock() { + LockObj* obj = LockObj::allocate(); + mvm::LockRecursive::my_lock_all(obj->lock, 257); + lock = ((uint32)obj >> 1) | 0x80000000; +} + +void JavaObject::release() { + uint32 id = mvm::Thread::get()->threadID; + if (lock == id) { + lock = 0; + } else if (lock & 0x80000000) { + LockObj* obj = (LockObj*)(lock << 1); + obj->release(); + } else { + lock--; + } } -void LockObj::release() { - lock->unlock(); +void JavaObject::acquire() { + uint32 id = mvm::Thread::get()->threadID; + uint32 val = __sync_val_compare_and_swap((uint32*)&lock, 0, id); + if (val != 0) { + //fat! + if (!(val & 0x80000000)) { + if ((val & 0x7FFFFF00) == id) { + if ((val & 0xFF) != 0xFF) { + lock++; + } else { + overflowThinlock(); + } + } else { + LockObj* obj = LockObj::allocate(); + uint32 val = ((uint32)obj >> 1) | 0x80000000; +loop: + uint32 count = 0; + while (lock) { + if (lock & 0x80000000) { +#ifdef USE_GC_BOEHM + delete obj; +#endif + goto end; + } + else mvm::Thread::yield(&count); + } + + uint32 test = __sync_val_compare_and_swap((uint32*)&lock, 0, val); + if (test) goto loop; + obj->acquire(); + } + } else { +end: + LockObj* obj = (LockObj*)(lock << 1); + obj->acquire(); + } + } } -bool LockObj::owner() { - return mvm::Lock::selfOwner(lock); +LockObj* JavaObject::changeToFatlock() { + if (!(lock & 0x80000000)) { + LockObj* obj = LockObj::allocate(); + uint32 val = (((uint32) obj) >> 1) | 0x80000000; + uint32 count = lock & 0xFF; + mvm::LockRecursive::my_lock_all(obj->lock, count + 1); + lock = val; + return obj; + } else { + return (LockObj*)(lock << 1); + } } void JavaObject::print(mvm::PrintBuffer* buf) const { @@ -99,23 +170,10 @@ buf->write(">"); } -LockObj* LockObj::myLock(JavaObject* obj) { - verifyNull(obj); - if (obj->lockObj == 0) { - JavaObject::globalLock->lock(); - if (obj->lockObj == 0) { - obj->lockObj = LockObj::allocate(); - } - JavaObject::globalLock->unlock(); - } - return obj->lockObj; -} - void JavaObject::waitIntern(struct timeval* info, bool timed) { - LockObj * l = LockObj::myLock(this); - bool owner = l->owner(); - if (owner) { + if (owner()) { + LockObj * l = changeToFatlock(); JavaThread* thread = JavaThread::get(); mvm::Lock* mutexThread = thread->lock; mvm::Cond* varcondThread = thread->varcond; @@ -168,8 +226,8 @@ } void JavaObject::notify() { - LockObj* l = LockObj::myLock(this); - if (l->owner()) { + if (owner()) { + LockObj * l = changeToFatlock(); l->getCond()->notify(); } else { JavaThread::get()->isolate->illegalMonitorStateException(this); @@ -177,8 +235,8 @@ } void JavaObject::notifyAll() { - LockObj* l = LockObj::myLock(this); - if (l->owner()) { + if (owner()) { + LockObj * l = changeToFatlock(); l->getCond()->notifyAll(); } else { JavaThread::get()->isolate->illegalMonitorStateException(this); @@ -189,3 +247,9 @@ if (varcond) delete varcond; delete lock; } + +#ifdef USE_GC_BOEHM +void JavaObject::destroyer(size_t sz) { + if (lockObj()) delete lockObj(); +} +#endif Modified: vmkit/trunk/lib/JnJVM/VMCore/JavaObject.h URL: http://llvm.org/viewvc/llvm-project/vmkit/trunk/lib/JnJVM/VMCore/JavaObject.h?rev=51994&r1=51993&r2=51994&view=diff ============================================================================== --- vmkit/trunk/lib/JnJVM/VMCore/JavaObject.h (original) +++ vmkit/trunk/lib/JnJVM/VMCore/JavaObject.h Thu Jun 5 07:45:58 2008 @@ -59,9 +59,11 @@ /// LockObj - This class represents a Java monitor. /// class LockObj : public mvm::Object { -public: - static VirtualTable* VT; + friend class JavaObject; + +private: + /// lock - The internal lock of this object lock. /// @@ -80,16 +82,23 @@ /// static LockObj* myLock(JavaObject* obj); - /// aquire - Acquires the lock. + /// acquire - Acquires the lock. /// - void aquire(); + void acquire() { + lock->lock(); + } /// release - Releases the lock. /// - void release(); - - /// owner - Returns true if the curren thread is the owner of this lock. - bool owner(); + void release() { + lock->unlock(); + } + + /// owner - Returns if the current thread owns this lock. + /// + bool owner() { + return mvm::Lock::selfOwner(lock); + } /// getCond - Returns the conditation variable of this lock, allocating it /// if non-existant. @@ -98,7 +107,9 @@ if (!varcond) varcond = new JavaCond(); return varcond; } - + +public: + static VirtualTable* VT; virtual void print(mvm::PrintBuffer* buf) const; virtual void TRACER; virtual void destroyer(size_t sz); @@ -114,6 +125,7 @@ /// void waitIntern(struct timeval *info, bool timed); + public: static VirtualTable* VT; @@ -121,14 +133,10 @@ /// CommonClass* classOf; - /// lockObj - The monitor of this object. Most of the time null. - /// - LockObj* lockObj; - - /// globalLock - The global lock to allocate monitors. + /// lock - The monitor of this object. Most of the time null. /// - static mvm::Lock* globalLock; - + uint32 lock; + /// wait - Java wait. Makes the current thread waiting on a monitor. /// void wait(); @@ -152,7 +160,7 @@ /// void initialise(CommonClass* cl) { this->classOf = cl; - this->lockObj = 0; + this->lock = 0; } /// instanceOfString - Is this object's class of type the given name? @@ -169,6 +177,24 @@ else return this->classOf->isAssignableFrom(cl); } + /// acquire - Acquire the lock on this object. + void acquire(); + + /// release - Release the lock on this object + void release(); + + /// changeToFatlock - Change the lock of this object to a fat lock. The lock + /// may be in thin lock or in fat lock. + LockObj* changeToFatlock(); + + /// overflowThinlock -Change the lock of this object to a fat lock because + /// we have reached 0xFF locks. + void overflowThinlock(); + + /// owner - Returns true if the curren thread is the owner of this object's + /// lock. + bool owner(); + #ifdef SIGSEGV_THROW_NULL #define verifyNull(obj) {} #else @@ -178,7 +204,18 @@ virtual void print(mvm::PrintBuffer* buf) const; virtual void TRACER; - + +#ifdef USE_GC_BOEHM + virtual void destroyer(size_t sz); +#endif + + LockObj* lockObj() { + if (lock & 0x80000000) { + return (LockObj*)(lock << 1); + } else { + return 0; + } + } }; Modified: vmkit/trunk/lib/JnJVM/VMCore/JavaRuntimeJIT.cpp URL: http://llvm.org/viewvc/llvm-project/vmkit/trunk/lib/JnJVM/VMCore/JavaRuntimeJIT.cpp?rev=51994&r1=51993&r2=51994&view=diff ============================================================================== --- vmkit/trunk/lib/JnJVM/VMCore/JavaRuntimeJIT.cpp (original) +++ vmkit/trunk/lib/JnJVM/VMCore/JavaRuntimeJIT.cpp Thu Jun 5 07:45:58 2008 @@ -286,7 +286,7 @@ vm->serviceError(vm, "I'm locking an object I don't own"); } #endif - LockObj::myLock(obj)->aquire(); + obj->acquire(); } @@ -298,17 +298,18 @@ vm->serviceError(vm, "I'm unlocking an object I don't own"); } #endif - obj->lockObj->release(); + obj->release(); } #ifdef SERVICE_VM extern "C" void JavaObjectAquireInSharedDomain(JavaObject* obj) { - LockObj::myLock(obj)->aquire(); + verifyNull(obj); + obj->acquire(); } extern "C" void JavaObjectReleaseInSharedDomain(JavaObject* obj) { verifyNull(obj); - obj->lockObj->release(); + obj->release(); } #endif @@ -347,3 +348,11 @@ extern "C" void JavaThreadClearException() { return JavaThread::clearException(); } + +extern "C" uint32 getThreadID() { + return JavaThread::get()->threadID; +} + +extern "C" void overflowThinLock(JavaObject* obj) { + obj->overflowThinlock(); +} Modified: vmkit/trunk/lib/JnJVM/VMCore/JavaThread.h URL: http://llvm.org/viewvc/llvm-project/vmkit/trunk/lib/JnJVM/VMCore/JavaThread.h?rev=51994&r1=51993&r2=51994&view=diff ============================================================================== --- vmkit/trunk/lib/JnJVM/VMCore/JavaThread.h (original) +++ vmkit/trunk/lib/JnJVM/VMCore/JavaThread.h Thu Jun 5 07:45:58 2008 @@ -38,9 +38,8 @@ mvm::Cond* varcond; JavaObject* pendingException; void* internalPendingException; - unsigned int self; - unsigned int interruptFlag; - unsigned int state; + uint32 interruptFlag; + uint32 state; std::vector sjlj_buffers; static const unsigned int StateRunning; @@ -58,7 +57,6 @@ this->varcond = mvm::Cond::allocCond(); this->interruptFlag = 0; this->state = StateRunning; - this->self = mvm::Thread::self(); this->pendingException = 0; } Modified: vmkit/trunk/lib/JnJVM/VMCore/JnjvmModule.cpp URL: http://llvm.org/viewvc/llvm-project/vmkit/trunk/lib/JnJVM/VMCore/JnjvmModule.cpp?rev=51994&r1=51993&r2=51994&view=diff ============================================================================== --- vmkit/trunk/lib/JnJVM/VMCore/JnjvmModule.cpp (original) +++ vmkit/trunk/lib/JnJVM/VMCore/JnjvmModule.cpp Thu Jun 5 07:45:58 2008 @@ -111,7 +111,7 @@ llvm::Function* JnjvmModule::GetObjectSizeFromClassFunction = 0; #ifdef MULTIPLE_GC -llvm::Function* JnjvmModule::FetCollectorFunction = 0; +llvm::Function* JnjvmModule::GetCollectorFunction = 0; #endif #ifdef SERVICE_VM @@ -121,6 +121,10 @@ llvm::Function* JnjvmModule::ServiceCallStopFunction = 0; #endif +llvm::Function* JnjvmModule::GetThreadIDFunction = 0; +llvm::Function* JnjvmModule::GetLockFunction = 0; +llvm::Function* JnjvmModule::OverflowThinLockFunction = 0; + Value* LLVMCommonClassInfo::getVar(JavaJIT* jit) { @@ -967,6 +971,7 @@ GetClassInDisplayFunction = module->getFunction("getClassInDisplay"); AquireObjectFunction = module->getFunction("JavaObjectAquire"); ReleaseObjectFunction = module->getFunction("JavaObjectRelease"); + OverflowThinLockFunction = module->getFunction("overflowThinLock"); FieldLookupFunction = module->getFunction("fieldLookup"); @@ -1023,7 +1028,9 @@ #ifdef MULTIPLE_GC GetCollectorFunction = module->getFunction("getCollector"); #endif - + + GetThreadIDFunction = module->getFunction("getThreadID"); + GetLockFunction = module->getFunction("getLock"); UTF8NullConstant = Constant::getNullValue(JavaArrayUInt16Type); JavaClassNullConstant = Constant::getNullValue(JavaClassType); Modified: vmkit/trunk/lib/JnJVM/VMCore/JnjvmModule.h URL: http://llvm.org/viewvc/llvm-project/vmkit/trunk/lib/JnJVM/VMCore/JnjvmModule.h?rev=51994&r1=51993&r2=51994&view=diff ============================================================================== --- vmkit/trunk/lib/JnJVM/VMCore/JnjvmModule.h (original) +++ vmkit/trunk/lib/JnJVM/VMCore/JnjvmModule.h Thu Jun 5 07:45:58 2008 @@ -326,6 +326,11 @@ #endif static llvm::Function* GetVTFromClassFunction; static llvm::Function* GetObjectSizeFromClassFunction; + + static llvm::Function* GetLockFunction; + static llvm::Function* GetThreadIDFunction; + static llvm::Function* OverflowThinLockFunction; + static llvm::ConstantInt* OffsetObjectSizeInClassConstant; static llvm::ConstantInt* OffsetVTInClassConstant; static llvm::ConstantInt* OffsetDepthInClassConstant; Modified: vmkit/trunk/lib/JnJVM/VMCore/VirtualTables.cpp URL: http://llvm.org/viewvc/llvm-project/vmkit/trunk/lib/JnJVM/VMCore/VirtualTables.cpp?rev=51994&r1=51993&r2=51994&view=diff ============================================================================== --- vmkit/trunk/lib/JnJVM/VMCore/VirtualTables.cpp (original) +++ vmkit/trunk/lib/JnJVM/VMCore/VirtualTables.cpp Thu Jun 5 07:45:58 2008 @@ -57,7 +57,7 @@ void ArrayObject::TRACER { classOf->MARK_AND_TRACE; - if (lockObj) lockObj->MARK_AND_TRACE; + if (lockObj()) lockObj()->MARK_AND_TRACE; for (sint32 i = 0; i < size; i++) { if (elements[i]) elements[i]->MARK_AND_TRACE; } @@ -65,8 +65,8 @@ #define ARRAYTRACER(name) \ void name::TRACER { \ - if (lockObj) \ - lockObj->MARK_AND_TRACE; \ + if (lockObj()) \ + lockObj()->MARK_AND_TRACE; \ } @@ -112,7 +112,7 @@ void JavaObject::TRACER { classOf->MARK_AND_TRACE; - if (lockObj) lockObj->MARK_AND_TRACE; + if (lockObj()) lockObj()->MARK_AND_TRACE; } #ifdef MULTIPLE_GC @@ -121,7 +121,7 @@ extern "C" void JavaObjectTracer(JavaObject* obj) { #endif obj->classOf->MARK_AND_TRACE; - if (obj->lockObj) obj->lockObj->MARK_AND_TRACE; + if (obj->lockObj()) obj->lockObj()->MARK_AND_TRACE; } Modified: vmkit/trunk/lib/Mvm/JIT.cpp URL: http://llvm.org/viewvc/llvm-project/vmkit/trunk/lib/Mvm/JIT.cpp?rev=51994&r1=51993&r2=51994&view=diff ============================================================================== --- vmkit/trunk/lib/Mvm/JIT.cpp (original) +++ vmkit/trunk/lib/Mvm/JIT.cpp Thu Jun 5 07:45:58 2008 @@ -513,6 +513,23 @@ /*Linkage=*/GlobalValue::ExternalLinkage, /*Name=*/"llvm.memset.i32", module); // (external, no body) } + + /* Create atomic cas i32 */ + { + std::vectorFuncTy_4_args; + FuncTy_4_args.push_back(ptr32Type); + FuncTy_4_args.push_back(IntegerType::get(32)); + FuncTy_4_args.push_back(IntegerType::get(32)); + FunctionType* FuncTy_4 = FunctionType::get( + /*Result=*/Type::Int32Ty, + /*Params=*/FuncTy_4_args, + /*isVarArg=*/false); + llvm_atomic_lcs_i32 = Function::Create( + /*Type=*/FuncTy_4, + /*Linkage=*/GlobalValue::ExternalLinkage, + /*Name=*/"llvm.atomic.lcs.i32", module); // (external, no body) + } + // Constant declaration @@ -565,6 +582,8 @@ llvm::Function* mvm::jit::llvm_memcpy_i32; llvm::Function* mvm::jit::llvm_memset_i32; +llvm::Function* mvm::jit::llvm_atomic_lcs_i32; + llvm::Function* mvm::jit::exceptionEndCatch; llvm::Function* mvm::jit::exceptionBeginCatch; llvm::Function* mvm::jit::unwindResume; Modified: vmkit/trunk/lib/Mvm/Main.cpp URL: http://llvm.org/viewvc/llvm-project/vmkit/trunk/lib/Mvm/Main.cpp?rev=51994&r1=51993&r2=51994&view=diff ============================================================================== --- vmkit/trunk/lib/Mvm/Main.cpp (original) +++ vmkit/trunk/lib/Mvm/Main.cpp Thu Jun 5 07:45:58 2008 @@ -46,7 +46,7 @@ jit::initialise(); Object::initialise(); Thread::initialise(); - Collector::initialise(Object::markAndTraceRoots, &base); + Collector::initialise(0, &base); CommandLine cl; cl.start(); From gordonhenriksen at mac.com Thu Jun 5 07:48:47 2008 From: gordonhenriksen at mac.com (Gordon Henriksen) Date: Thu, 05 Jun 2008 12:48:47 -0000 Subject: [llvm-commits] [llvm] r51995 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <200806051248.m55CmmHf021441@zion.cs.uiuc.edu> Author: gordon Date: Thu Jun 5 07:48:32 2008 New Revision: 51995 URL: http://llvm.org/viewvc/llvm-project?rev=51995&view=rev Log: Adding release notes for bindings improvements. Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=51995&r1=51994&r2=51995&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Thu Jun 5 07:48:32 2008 @@ -215,6 +215,9 @@ memcpy calls, unneeded copies of aggregates, and handles the return slot optimization. The LLVM optimizer now notices long sequences of consequtive stores and merges them into memcpy's where profitable. +
  • The C and Ocaml bindings have received additional improvements. The +bindings now cover pass managers, several transformation passes, iteration +over the LLVM IR, target data, and parameter attribute lists.
    • From gordonhenriksen at mac.com Thu Jun 5 07:52:03 2008 From: gordonhenriksen at mac.com (Gordon Henriksen) Date: Thu, 05 Jun 2008 12:52:03 -0000 Subject: [llvm-commits] [llvm] r51996 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <200806051252.m55Cq5Kt021627@zion.cs.uiuc.edu> Author: gordon Date: Thu Jun 5 07:51:50 2008 New Revision: 51996 URL: http://llvm.org/viewvc/llvm-project?rev=51996&view=rev Log: Move this to the proper section. I misread Optimizer Improvements as Other Improvements for some reason. Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=51996&r1=51995&r2=51996&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Thu Jun 5 07:51:50 2008 @@ -175,6 +175,9 @@ Atomic operation support, Alpha, X86, X86-64, PowerPC. "__sync_synchronize"
      +
    • The C and Ocaml bindings have received additional improvements. The +bindings now cover pass managers, several transformation passes, iteration +over the LLVM IR, target data, and parameter attribute lists.
    @@ -215,9 +218,6 @@ memcpy calls, unneeded copies of aggregates, and handles the return slot optimization. The LLVM optimizer now notices long sequences of consequtive stores and merges them into memcpy's where profitable. -
  • The C and Ocaml bindings have received additional improvements. The -bindings now cover pass managers, several transformation passes, iteration -over the LLVM IR, target data, and parameter attribute lists.
    • From matthijs at stdin.nl Thu Jun 5 07:52:03 2008 From: matthijs at stdin.nl (Matthijs Kooijman) Date: Thu, 05 Jun 2008 12:52:03 -0000 Subject: [llvm-commits] [llvm] r51997 - in /llvm/trunk: lib/Transforms/Scalar/ScalarReplAggregates.cpp test/Transforms/ScalarRepl/2008-06-05-loadstore-agg.ll Message-ID: <200806051252.m55Cq5ID021629@zion.cs.uiuc.edu> Author: matthijs Date: Thu Jun 5 07:51:53 2008 New Revision: 51997 URL: http://llvm.org/viewvc/llvm-project?rev=51997&view=rev Log: Learn ScalarReplAggregrates how stores and loads of first class aggregrates work and how to replace them into individual values. Also, when trying to replace an aggregrate that is used by load or store with a single (large) integer, don't crash (but don't replace the aggregrate either). Also adds a testcase for both structs and arrays. Added: llvm/trunk/test/Transforms/ScalarRepl/2008-06-05-loadstore-agg.ll Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=51997&r1=51996&r2=51997&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Thu Jun 5 07:51:53 2008 @@ -302,6 +302,41 @@ continue; } + // Replace %res = load { i32, i32 }* %alloc + // by + // %load.0 = load i32* %alloc.0 + // %insert.0 insertvalue { i32, i32 } zeroinitializer, i32 %load.0, 0 + // %load.1 = load i32* %alloc.1 + // %insert = insertvalue { i32, i32 } %insert.0, i32 %load.1, 1 + // (Also works for arrays instead of structs) + if (LoadInst *LI = dyn_cast(User)) { + Value *Insert = UndefValue::get(LI->getType()); + for (unsigned i = 0, e = ElementAllocas.size(); i != e; ++i) { + Value *Load = new LoadInst(ElementAllocas[i], "load", LI); + Insert = InsertValueInst::Create(Insert, Load, i, "insert", LI); + } + LI->replaceAllUsesWith(Insert); + LI->eraseFromParent(); + continue; + } + + // Replace store { i32, i32 } %val, { i32, i32 }* %alloc + // by + // %val.0 = extractvalue { i32, i32 } %val, 0 + // store i32 %val.0, i32* %alloc.0 + // %val.1 = extractvalue { i32, i32 } %val, 1 + // store i32 %val.1, i32* %alloc.1 + // (Also works for arrays instead of structs) + if (StoreInst *SI = dyn_cast(User)) { + Value *Val = SI->getOperand(0); + for (unsigned i = 0, e = ElementAllocas.size(); i != e; ++i) { + Value *Extract = ExtractValueInst::Create(Val, i, Val->getName(), SI); + new StoreInst(Extract, ElementAllocas[i], SI); + } + SI->eraseFromParent(); + continue; + } + GetElementPtrInst *GEPI = cast(User); // We now know that the GEP is of the form: GEP , 0, unsigned Idx = @@ -440,6 +475,12 @@ if (BitCastInst *C = dyn_cast(User)) return isSafeUseOfBitCastedAllocation(C, AI, Info); + if (isa(User)) + return; // Loads (returning a first class aggregrate) are always rewritable + + if (isa(User) && User->getOperand(0) != AI) + return; // Store is ok if storing INTO the pointer, not storing the pointer + GetElementPtrInst *GEPI = dyn_cast(User); if (GEPI == 0) return MarkUnsafe(Info); @@ -961,12 +1002,22 @@ Instruction *User = cast(*UI); if (LoadInst *LI = dyn_cast(User)) { + // FIXME: Loads of a first class aggregrate value could be converted to a + // series of loads and insertvalues + if (!LI->getType()->isSingleValueType()) + return 0; + if (MergeInType(LI->getType(), UsedType, TD)) return 0; } else if (StoreInst *SI = dyn_cast(User)) { // Storing the pointer, not into the value? if (SI->getOperand(0) == V) return 0; + + // FIXME: Stores of a first class aggregrate value could be converted to a + // series of extractvalues and stores + if (!SI->getOperand(0)->getType()->isSingleValueType()) + return 0; // NOTE: We could handle storing of FP imms into integers here! Added: llvm/trunk/test/Transforms/ScalarRepl/2008-06-05-loadstore-agg.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ScalarRepl/2008-06-05-loadstore-agg.ll?rev=51997&view=auto ============================================================================== --- llvm/trunk/test/Transforms/ScalarRepl/2008-06-05-loadstore-agg.ll (added) +++ llvm/trunk/test/Transforms/ScalarRepl/2008-06-05-loadstore-agg.ll Thu Jun 5 07:51:53 2008 @@ -0,0 +1,32 @@ +; This test shows an alloca of a struct and an array that can be reduced to +; multiple variables easily. However, the alloca is used by a store +; instruction, which was not possible before aggregrates were first class +; values. This checks of scalarrepl splits up the struct and array properly. + +; RUN: llvm-as < %s | opt -scalarrepl | llvm-dis | not grep alloca + +define i32 @foo() { + %target = alloca { i32, i32 } ; <{ i32, i32 }*> [#uses=1] + ; Build a first class struct to store + %res1 = insertvalue { i32, i32 } undef, i32 1, 0 ; <{ i32, i32 }> [#uses=1] + %res2 = insertvalue { i32, i32 } %res1, i32 2, 1 ; <{ i32, i32 }> [#uses=1] + ; And store it + store { i32, i32 } %res2, { i32, i32 }* %target + ; Actually use %target, so it doesn't get removed alltogether + %ptr = getelementptr { i32, i32 }* %target, i32 0, i32 0 + %val = load i32* %ptr + ret i32 %val +} + +define i32 @bar() { + %target = alloca [ 2 x i32 ] ; <{ i32, i32 }*> [#uses=1] + ; Build a first class array to store + %res1 = insertvalue [ 2 x i32 ] undef, i32 1, 0 ; <{ i32, i32 }> [#uses=1] + %res2 = insertvalue [ 2 x i32 ] %res1, i32 2, 1 ; <{ i32, i32 }> [#uses=1] + ; And store it + store [ 2 x i32 ] %res2, [ 2 x i32 ]* %target + ; Actually use %target, so it doesn't get removed alltogether + %ptr = getelementptr [ 2 x i32 ]* %target, i32 0, i32 0 + %val = load i32* %ptr + ret i32 %val +} From nicholas at mxc.ca Thu Jun 5 07:53:25 2008 From: nicholas at mxc.ca (Nick Lewycky) Date: Thu, 05 Jun 2008 05:53:25 -0700 Subject: [llvm-commits] [llvm] r51988 - /llvm/trunk/docs/ReleaseNotes.html In-Reply-To: <200806050802.m5582oI7011831@zion.cs.uiuc.edu> References: <200806050802.m5582oI7011831@zion.cs.uiuc.edu> Message-ID: <4847E1C5.1060203@mxc.ca> Chris Lattner wrote: > @@ -204,7 +212,9 @@ > >
  • Loop index set splitting on by default: describe me.
    • >
  • LLVM includes a new memcpy optimization pass which optimizes out dead > -memcpy calls and unneeded copies of aggregates.
    • > +memcpy calls, unneeded copies of aggregates, and handles the return slot > +optimization. The LLVM optimizer now notices long sequences of consequtive 'consecutive' Nick > +stores and merges them into memcpy's where profitable. > > > From nicholas at mxc.ca Thu Jun 5 07:54:53 2008 From: nicholas at mxc.ca (Nick Lewycky) Date: Thu, 05 Jun 2008 12:54:53 -0000 Subject: [llvm-commits] [llvm] r51998 - /llvm/trunk/utils/NewNightlyTest.pl Message-ID: <200806051254.m55CstBS021766@zion.cs.uiuc.edu> Author: nicholas Date: Thu Jun 5 07:54:44 2008 New Revision: 51998 URL: http://llvm.org/viewvc/llvm-project?rev=51998&view=rev Log: Escape "$#". Modified: llvm/trunk/utils/NewNightlyTest.pl Modified: llvm/trunk/utils/NewNightlyTest.pl URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/NewNightlyTest.pl?rev=51998&r1=51997&r2=51998&view=diff ============================================================================== --- llvm/trunk/utils/NewNightlyTest.pl (original) +++ llvm/trunk/utils/NewNightlyTest.pl Thu Jun 5 07:54:44 2008 @@ -558,7 +558,7 @@ my $NumDirsInCVS = 0; if ($USESVN) { $NumFilesInCVS = `egrep '^A' $COLog | wc -l` + 0; - $NumDirsInCVS = `sed -e 's#/[^/]*$##' $COLog | sort | uniq | wc -l` + 0; + $NumDirsInCVS = `sed -e 's#/[^/]*\$##' $COLog | sort | uniq | wc -l` + 0; } else { $NumFilesInCVS = `egrep '^U' $COLog | wc -l` + 0; $NumDirsInCVS = `egrep '^cvs (checkout|server|update):' $COLog | wc -l` + 0; From zhousheng00 at gmail.com Thu Jun 5 08:27:40 2008 From: zhousheng00 at gmail.com (Zhou Sheng) Date: Thu, 05 Jun 2008 13:27:40 -0000 Subject: [llvm-commits] [llvm] r51999 - /llvm/trunk/lib/Support/APInt.cpp Message-ID: <200806051327.m55DReqJ022892@zion.cs.uiuc.edu> Author: sheng Date: Thu Jun 5 08:27:38 2008 New Revision: 51999 URL: http://llvm.org/viewvc/llvm-project?rev=51999&view=rev Log: As comments said, for negative value, the arithmetic over-shift-right should return -1. So here it should be signed-extended, when bitwidth larger than 64. test case: llvm/test/ExecutionEngine/2008-06-05-APInt-OverAShr.ll Modified: llvm/trunk/lib/Support/APInt.cpp Modified: llvm/trunk/lib/Support/APInt.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/APInt.cpp?rev=51999&r1=51998&r2=51999&view=diff ============================================================================== --- llvm/trunk/lib/Support/APInt.cpp (original) +++ llvm/trunk/lib/Support/APInt.cpp Thu Jun 5 08:27:38 2008 @@ -1113,7 +1113,7 @@ // issues in the algorithm below. if (shiftAmt == BitWidth) { if (isNegative()) - return APInt(BitWidth, -1ULL); + return APInt(BitWidth, -1ULL, true); else return APInt(BitWidth, 0); } From zhousheng00 at gmail.com Thu Jun 5 08:42:21 2008 From: zhousheng00 at gmail.com (Zhou Sheng) Date: Thu, 05 Jun 2008 13:42:21 -0000 Subject: [llvm-commits] [llvm] r52000 - /llvm/trunk/test/ExecutionEngine/2008-06-05-APInt-OverAShr.ll Message-ID: <200806051342.m55DgLeG023304@zion.cs.uiuc.edu> Author: sheng Date: Thu Jun 5 08:42:21 2008 New Revision: 52000 URL: http://llvm.org/viewvc/llvm-project?rev=52000&view=rev Log: Add a test case for APInt bug fix in r51999. Added: llvm/trunk/test/ExecutionEngine/2008-06-05-APInt-OverAShr.ll Added: llvm/trunk/test/ExecutionEngine/2008-06-05-APInt-OverAShr.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/ExecutionEngine/2008-06-05-APInt-OverAShr.ll?rev=52000&view=auto ============================================================================== --- llvm/trunk/test/ExecutionEngine/2008-06-05-APInt-OverAShr.ll (added) +++ llvm/trunk/test/ExecutionEngine/2008-06-05-APInt-OverAShr.ll Thu Jun 5 08:42:21 2008 @@ -0,0 +1,60 @@ +; RUN: llvm-as %s -f -o %t.bc +; RUN: lli -force-interpreter=true %t.bc | grep 1 + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32" +target triple = "i686-pc-linux-gnu" + at .str = internal constant [10 x i8] c"MSB = %d\0A\00" ; <[10 x i8]*> [#uses=1] + +define i65 @foo(i65 %x) { +entry: + %x_addr = alloca i65 ; [#uses=2] + %retval = alloca i65 ; [#uses=2] + %tmp = alloca i65 ; [#uses=2] + %"alloca point" = bitcast i65 0 to i65 ; [#uses=0] + store i65 %x, i65* %x_addr + %tmp1 = load i65* %x_addr, align 4 ; [#uses=1] + %tmp2 = ashr i65 %tmp1, 65 ; [#uses=1] + store i65 %tmp2, i65* %tmp, align 4 + %tmp3 = load i65* %tmp, align 4 ; [#uses=1] + store i65 %tmp3, i65* %retval, align 4 + br label %return + +return: ; preds = %entry + %retval4 = load i65* %retval ; [#uses=1] + ret i65 %retval4 +} + +define i32 @main() { +entry: + %retval = alloca i32 ; [#uses=1] + %iftmp.0 = alloca i32 ; [#uses=3] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + %tmp = call i65 @foo( i65 -9 ) ; [#uses=1] + %tmp1 = lshr i65 %tmp, 64 ; [#uses=1] + %tmp2 = xor i65 %tmp1, 1 ; [#uses=1] + %tmp3 = and i65 %tmp2, 1 ; [#uses=1] + %tmp34 = trunc i65 %tmp3 to i8 ; [#uses=1] + %toBool = icmp ne i8 %tmp34, 0 ; [#uses=1] + br i1 %toBool, label %cond_true, label %cond_false + +cond_true: ; preds = %entry + store i32 0, i32* %iftmp.0, align 4 + br label %cond_next + +cond_false: ; preds = %entry + store i32 1, i32* %iftmp.0, align 4 + br label %cond_next + +cond_next: ; preds = %cond_false, %cond_true + %tmp5 = getelementptr [10 x i8]* @.str, i32 0, i32 0 ; [#uses=1] + %tmp6 = load i32* %iftmp.0, align 4 ; [#uses=1] + %tmp7 = call i32 (i8*, ...)* @printf( i8* noalias %tmp5, i32 %tmp6 ) nounwind ; [#uses=0] + br label %return + +return: ; preds = %cond_next + store i32 0, i32* %retval, align 4 + %retval8 = load i32* %retval ; [#uses=1] + ret i32 %retval8 +} + +declare i32 @printf(i8* noalias , ...) nounwind From matthijs at stdin.nl Thu Jun 5 09:00:36 2008 From: matthijs at stdin.nl (Matthijs Kooijman) Date: Thu, 05 Jun 2008 14:00:36 -0000 Subject: [llvm-commits] [llvm] r52002 - in /llvm/trunk: lib/VMCore/Verifier.cpp test/Assembler/AggregrateReturn.ll Message-ID: <200806051400.m55E0aUM024060@zion.cs.uiuc.edu> Author: matthijs Date: Thu Jun 5 09:00:36 2008 New Revision: 52002 URL: http://llvm.org/viewvc/llvm-project?rev=52002&view=rev Log: Change the Verifier to support returning first class aggregrates. Add a testcase for functions returning first class aggregrates. Added: llvm/trunk/test/Assembler/AggregrateReturn.ll Modified: llvm/trunk/lib/VMCore/Verifier.cpp Modified: llvm/trunk/lib/VMCore/Verifier.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Verifier.cpp?rev=52002&r1=52001&r2=52002&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Verifier.cpp (original) +++ llvm/trunk/lib/VMCore/Verifier.cpp Thu Jun 5 09:00:36 2008 @@ -594,7 +594,10 @@ Assert2(N == 0, "Found return instr that returns void in Function of non-void " "return type!", &RI, F->getReturnType()); - else if (const StructType *STy = dyn_cast(F->getReturnType())) { + else if (N > 1) { + const StructType *STy = dyn_cast(F->getReturnType()); + Assert2(STy, "Return instr with multiple values, but return type is not " + "a struct", &RI, F->getReturnType()); Assert2(STy->getNumElements() == N, "Incorrect number of return values in ret instruction!", &RI, F->getReturnType()); Added: llvm/trunk/test/Assembler/AggregrateReturn.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Assembler/AggregrateReturn.ll?rev=52002&view=auto ============================================================================== --- llvm/trunk/test/Assembler/AggregrateReturn.ll (added) +++ llvm/trunk/test/Assembler/AggregrateReturn.ll Thu Jun 5 09:00:36 2008 @@ -0,0 +1,22 @@ +; RUN: llvm-as < %s | llvm-dis + +define { i32, i32 } @foo() { + %res = insertvalue { i32, i32 } undef, i32 0, 0 + %res2 = insertvalue { i32, i32 } %res, i32 1, 1 + ret { i32, i32 } %res2 +} + +define [ 2 x i32 ] @bar() { + %res = insertvalue [ 2 x i32 ] undef, i32 0, 0 + %res2 = insertvalue [ 2 x i32 ] %res, i32 1, 1 + ret [ 2 x i32 ] %res2 +} + +define i32 @main() { + %a = call { i32, i32 }()* @foo () + %b = call [ 2 x i32 ]()* @bar () + %a.0 = extractvalue { i32, i32 } %a, 0 + %b.1 = extractvalue [ 2 x i32 ] %b, 1 + %r = add i32 %a.0, %b.1 + ret i32 %r +} From zhousheng00 at gmail.com Thu Jun 5 09:23:44 2008 From: zhousheng00 at gmail.com (Zhou Sheng) Date: Thu, 05 Jun 2008 14:23:44 -0000 Subject: [llvm-commits] [llvm] r52003 - /llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Message-ID: <200806051423.m55ENjdT024882@zion.cs.uiuc.edu> Author: sheng Date: Thu Jun 5 09:23:44 2008 New Revision: 52003 URL: http://llvm.org/viewvc/llvm-project?rev=52003&view=rev Log: If BitWidth equals to ShtAmt, the RHSKnownZero[BitWidth-ShiftAmt-1] will crash the opt. Just fix this. Test case in llvm/test/Transforms/InstCombine/2008-06-05-ashr-crash.ll Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp?rev=52003&r1=52002&r2=52003&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Thu Jun 5 09:23:44 2008 @@ -1236,7 +1236,7 @@ // If the input sign bit is known to be zero, or if none of the top bits // are demanded, turn this into an unsigned shift right. - if (RHSKnownZero[BitWidth-ShiftAmt-1] || + if (BitWidth == ShiftAmt || RHSKnownZero[BitWidth-ShiftAmt-1] || (HighBits & ~DemandedMask) == HighBits) { // Perform the logical shift right. Value *NewVal = BinaryOperator::CreateLShr( From zhousheng00 at gmail.com Thu Jun 5 09:25:11 2008 From: zhousheng00 at gmail.com (Zhou Sheng) Date: Thu, 05 Jun 2008 14:25:11 -0000 Subject: [llvm-commits] [llvm] r52004 - /llvm/trunk/test/Transforms/InstCombine/2008-06-05-ashr-crash.ll Message-ID: <200806051425.m55EPBpU024930@zion.cs.uiuc.edu> Author: sheng Date: Thu Jun 5 09:25:11 2008 New Revision: 52004 URL: http://llvm.org/viewvc/llvm-project?rev=52004&view=rev Log: Add a test case for opt -instcombine bug fix in revision 52003. Added: llvm/trunk/test/Transforms/InstCombine/2008-06-05-ashr-crash.ll Added: llvm/trunk/test/Transforms/InstCombine/2008-06-05-ashr-crash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/2008-06-05-ashr-crash.ll?rev=52004&view=auto ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/2008-06-05-ashr-crash.ll (added) +++ llvm/trunk/test/Transforms/InstCombine/2008-06-05-ashr-crash.ll Thu Jun 5 09:25:11 2008 @@ -0,0 +1,7 @@ +; RUN: llvm-as < %s | opt -instcombine + +define i65 @foo(i65 %x) nounwind { +entry: + %tmp2 = ashr i65 %x, 65 ; [#uses=1] + ret i65 %tmp2 +} From gohman at apple.com Thu Jun 5 10:43:11 2008 From: gohman at apple.com (Dan Gohman) Date: Thu, 05 Jun 2008 15:43:11 -0000 Subject: [llvm-commits] [llvm] r52007 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <200806051543.m55FhBTE027382@zion.cs.uiuc.edu> Author: djg Date: Thu Jun 5 10:43:11 2008 New Revision: 52007 URL: http://llvm.org/viewvc/llvm-project?rev=52007&view=rev Log: Expand the bullet item about i128 support and APInt usage in codegen. Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=52007&r1=52006&r2=52007&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Thu Jun 5 10:43:11 2008 @@ -195,7 +195,12 @@
    • MemOperand in the code generator: describe me!.
      • -
    • i128 support and APInt through most of codegen.
      • +
    • Target-independent codegen infastructure now uses LLVM's APInt class for + handling integer values, which allow it to support integer types larger + than 64 bits. Note that support for such types is also dependent on + target-specific support. Use of APInt is also a step toward support for + non-power-of-2 integer sizes.
      • +
    • Support for 128-bit integers on X86-64.
    • Several compile time speedups for code with large basic blocks.
    From gohman at apple.com Thu Jun 5 10:46:36 2008 From: gohman at apple.com (Dan Gohman) Date: Thu, 05 Jun 2008 15:46:36 -0000 Subject: [llvm-commits] [llvm] r52008 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <200806051546.m55FkauH027486@zion.cs.uiuc.edu> Author: djg Date: Thu Jun 5 10:46:36 2008 New Revision: 52008 URL: http://llvm.org/viewvc/llvm-project?rev=52008&view=rev Log: Add a note mentioning --view-sunit-dags improvements. Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=52008&r1=52007&r2=52008&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Thu Jun 5 10:46:36 2008 @@ -202,6 +202,8 @@ non-power-of-2 integer sizes.
  • Support for 128-bit integers on X86-64.
  • Several compile time speedups for code with large basic blocks.
    • +
  • Several improvements which make llc's --view-sunit-dags + visualization of scheduling dependency graphs easier to understand.
    • From gohman at apple.com Thu Jun 5 10:49:30 2008 From: gohman at apple.com (Dan Gohman) Date: Thu, 05 Jun 2008 15:49:30 -0000 Subject: [llvm-commits] [llvm] r52009 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <200806051549.m55FnUUY027580@zion.cs.uiuc.edu> Author: djg Date: Thu Jun 5 10:49:29 2008 New Revision: 52009 URL: http://llvm.org/viewvc/llvm-project?rev=52009&view=rev Log: Add a note about improved alignment detection. Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=52009&r1=52008&r2=52009&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Thu Jun 5 10:49:29 2008 @@ -225,6 +225,8 @@ memcpy calls, unneeded copies of aggregates, and handles the return slot optimization. The LLVM optimizer now notices long sequences of consequtive stores and merges them into memcpy's where profitable. +
  • Alignment detection for vector memory references and for memcpy and +memset is now more aggressive.
    • From clattner at apple.com Thu Jun 5 11:40:15 2008 From: clattner at apple.com (Chris Lattner) Date: Thu, 5 Jun 2008 09:40:15 -0700 Subject: [llvm-commits] [llvm] r52003 - /llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp In-Reply-To: <200806051423.m55ENjdT024882@zion.cs.uiuc.edu> References: <200806051423.m55ENjdT024882@zion.cs.uiuc.edu> Message-ID: On Jun 5, 2008, at 7:23 AM, Zhou Sheng wrote: > Author: sheng > Date: Thu Jun 5 09:23:44 2008 > New Revision: 52003 > > URL: http://llvm.org/viewvc/llvm-project?rev=52003&view=rev > Log: > If BitWidth equals to ShtAmt, the RHSKnownZero[BitWidth-ShiftAmt-1] > will > crash the opt. Just fix this. Hi Sheng, What happens if ShiftAmt is larger? Shifting by the bitwidth or more is undefined... maybe this should be caught earlier? -Chris > > > Test case in llvm/test/Transforms/InstCombine/2008-06-05-ashr-crash.ll > > Modified: > llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp > > Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp?rev=52003&r1=52002&r2=52003&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp > (original) > +++ llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Thu > Jun 5 09:23:44 2008 > @@ -1236,7 +1236,7 @@ > > // If the input sign bit is known to be zero, or if none of > the top bits > // are demanded, turn this into an unsigned shift right. > - if (RHSKnownZero[BitWidth-ShiftAmt-1] || > + if (BitWidth == ShiftAmt || RHSKnownZero[BitWidth-ShiftAmt-1] > || > (HighBits & ~DemandedMask) == HighBits) { > // Perform the logical shift right. > Value *NewVal = BinaryOperator::CreateLShr( > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From criswell at uiuc.edu Thu Jun 5 11:57:29 2008 From: criswell at uiuc.edu (John Criswell) Date: Thu, 05 Jun 2008 16:57:29 -0000 Subject: [llvm-commits] [poolalloc] r52011 - in /poolalloc/trunk: include/dsa/DSGraph.h include/dsa/DSGraphTraits.h include/dsa/DSNode.h include/dsa/DSSupport.h include/dsa/DataStructure.h include/poolalloc/PoolAllocate.h lib/DSA/DataStructure.cpp lib/PoolAllocate/PASimple.cpp Message-ID: <200806051657.m55GvTbf029725@zion.cs.uiuc.edu> Author: criswell Date: Thu Jun 5 11:57:29 2008 New Revision: 52011 URL: http://llvm.org/viewvc/llvm-project?rev=52011&view=rev Log: Updated to new LLVM header file names. Changed the default size of the global pool to 32 bytes for the simple pool allocator. Modified: poolalloc/trunk/include/dsa/DSGraph.h poolalloc/trunk/include/dsa/DSGraphTraits.h poolalloc/trunk/include/dsa/DSNode.h poolalloc/trunk/include/dsa/DSSupport.h poolalloc/trunk/include/dsa/DataStructure.h poolalloc/trunk/include/poolalloc/PoolAllocate.h poolalloc/trunk/lib/DSA/DataStructure.cpp poolalloc/trunk/lib/PoolAllocate/PASimple.cpp Modified: poolalloc/trunk/include/dsa/DSGraph.h URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/dsa/DSGraph.h?rev=52011&r1=52010&r2=52011&view=diff ============================================================================== --- poolalloc/trunk/include/dsa/DSGraph.h (original) +++ poolalloc/trunk/include/dsa/DSGraph.h Thu Jun 5 11:57:29 2008 @@ -16,7 +16,7 @@ #define LLVM_ANALYSIS_DSGRAPH_H #include "dsa/DSNode.h" -#include "llvm/ADT/hash_map" +#include "llvm/ADT/hash_map.h" #include "llvm/ADT/EquivalenceClasses.h" #include Modified: poolalloc/trunk/include/dsa/DSGraphTraits.h URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/dsa/DSGraphTraits.h?rev=52011&r1=52010&r2=52011&view=diff ============================================================================== --- poolalloc/trunk/include/dsa/DSGraphTraits.h (original) +++ poolalloc/trunk/include/dsa/DSGraphTraits.h Thu Jun 5 11:57:29 2008 @@ -18,7 +18,7 @@ #include "dsa/DSGraph.h" #include "llvm/ADT/GraphTraits.h" -#include "llvm/ADT/iterator" +#include "llvm/ADT/iterator.h" #include "llvm/ADT/STLExtras.h" namespace llvm { Modified: poolalloc/trunk/include/dsa/DSNode.h URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/dsa/DSNode.h?rev=52011&r1=52010&r2=52011&view=diff ============================================================================== --- poolalloc/trunk/include/dsa/DSNode.h (original) +++ poolalloc/trunk/include/dsa/DSNode.h Thu Jun 5 11:57:29 2008 @@ -15,7 +15,8 @@ #define LLVM_ANALYSIS_DSNODE_H #include "dsa/DSSupport.h" -#include "llvm/ADT/hash_map" +#include "llvm/ADT/hash_map.h" +#include "llvm/Support/Streams.h" namespace llvm { Modified: poolalloc/trunk/include/dsa/DSSupport.h URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/dsa/DSSupport.h?rev=52011&r1=52010&r2=52011&view=diff ============================================================================== --- poolalloc/trunk/include/dsa/DSSupport.h (original) +++ poolalloc/trunk/include/dsa/DSSupport.h Thu Jun 5 11:57:29 2008 @@ -15,8 +15,8 @@ #define LLVM_ANALYSIS_DSSUPPORT_H #include -#include "llvm/ADT/hash_map" -#include "llvm/ADT/hash_set" +#include "llvm/ADT/hash_map.h" +#include "llvm/ADT/hash_set.h" #include "llvm/Support/CallSite.h" namespace llvm { Modified: poolalloc/trunk/include/dsa/DataStructure.h URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/dsa/DataStructure.h?rev=52011&r1=52010&r2=52011&view=diff ============================================================================== --- poolalloc/trunk/include/dsa/DataStructure.h (original) +++ poolalloc/trunk/include/dsa/DataStructure.h Thu Jun 5 11:57:29 2008 @@ -17,8 +17,8 @@ #include "llvm/Pass.h" #include "llvm/Target/TargetData.h" #include "llvm/Support/CallSite.h" -#include "llvm/ADT/hash_map" -#include "llvm/ADT/hash_set" +#include "llvm/ADT/hash_map.h" +#include "llvm/ADT/hash_set.h" #include "llvm/ADT/EquivalenceClasses.h" #include Modified: poolalloc/trunk/include/poolalloc/PoolAllocate.h URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/poolalloc/PoolAllocate.h?rev=52011&r1=52010&r2=52011&view=diff ============================================================================== --- poolalloc/trunk/include/poolalloc/PoolAllocate.h (original) +++ poolalloc/trunk/include/poolalloc/PoolAllocate.h Thu Jun 5 11:57:29 2008 @@ -22,7 +22,7 @@ #include "llvm/Support/CallSite.h" #include "llvm/ADT/EquivalenceClasses.h" #include "llvm/ADT/VectorExtras.h" -#include "llvm/ADT/hash_set" +#include "llvm/ADT/hash_set.h" #include "dsa/DataStructure.h" #include "poolalloc/Config/config.h" Modified: poolalloc/trunk/lib/DSA/DataStructure.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/DataStructure.cpp?rev=52011&r1=52010&r2=52011&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/DataStructure.cpp (original) +++ poolalloc/trunk/lib/DSA/DataStructure.cpp Thu Jun 5 11:57:29 2008 @@ -29,7 +29,7 @@ #include "llvm/ADT/SCCIterator.h" #include "llvm/ADT/Statistic.h" #include "llvm/Support/Timer.h" -#include "llvm/ADT/hash_map" +#include "llvm/ADT/hash_map.h" #include #include Modified: poolalloc/trunk/lib/PoolAllocate/PASimple.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/PASimple.cpp?rev=52011&r1=52010&r2=52011&view=diff ============================================================================== --- poolalloc/trunk/lib/PoolAllocate/PASimple.cpp (original) +++ poolalloc/trunk/lib/PoolAllocate/PASimple.cpp Thu Jun 5 11:57:29 2008 @@ -126,7 +126,7 @@ // // Create the global pool. // - TheGlobalPool = CreateGlobalPool(1, 1, MainFunc->getEntryBlock().begin(), M); + TheGlobalPool = CreateGlobalPool(32, 1, MainFunc->getEntryBlock().begin(), M); // // Now that all call targets are available, rewrite the function bodies of the From resistor at mac.com Thu Jun 5 12:15:43 2008 From: resistor at mac.com (Owen Anderson) Date: Thu, 05 Jun 2008 17:15:43 -0000 Subject: [llvm-commits] [llvm] r52012 - in /llvm/trunk: include/llvm/CodeGen/LiveIntervalAnalysis.h lib/CodeGen/LiveIntervalAnalysis.cpp Message-ID: <200806051715.m55HFhhb030297@zion.cs.uiuc.edu> Author: resistor Date: Thu Jun 5 12:15:43 2008 New Revision: 52012 URL: http://llvm.org/viewvc/llvm-project?rev=52012&view=rev Log: Add a helper for constructing new live ranges that ended from an instruction to the end of its MBB. Modified: llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Modified: llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h?rev=52012&r1=52011&r2=52012&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h (original) +++ llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h Thu Jun 5 12:15:43 2008 @@ -220,6 +220,11 @@ I = r2iMap_.insert(I, std::make_pair(reg, createInterval(reg))); return I->second; } + + /// addLiveRangeToEndOfBlock - Given a register and an instruction, + /// adds a live range from that instruction to the end of its MBB. + LiveRange addLiveRangeToEndOfBlock(unsigned reg, + MachineInstr* startInst); // Interval removal Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=52012&r1=52011&r2=52012&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Thu Jun 5 12:15:43 2008 @@ -1830,3 +1830,18 @@ } } } + +LiveRange LiveIntervals::addLiveRangeToEndOfBlock(unsigned reg, + MachineInstr* startInst) { + LiveInterval& Interval = getOrCreateInterval(reg); + VNInfo* VN = Interval.getNextValue( + getInstructionIndex(startInst) + InstrSlots::DEF, + startInst, getVNInfoAllocator()); + VN->hasPHIKill = true; + VN->kills.push_back(getMBBEndIdx(startInst->getParent())); + LiveRange LR(getInstructionIndex(startInst) + InstrSlots::DEF, + getMBBEndIdx(startInst->getParent()) + 1, VN); + Interval.addRange(LR); + + return LR; +} From gohman at apple.com Thu Jun 5 11:15:40 2008 From: gohman at apple.com (Dan Gohman) Date: Thu, 05 Jun 2008 16:15:40 -0000 Subject: [llvm-commits] [llvm] r52010 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <200806051615.m55GFeR4028371@zion.cs.uiuc.edu> Author: djg Date: Thu Jun 5 11:15:39 2008 New Revision: 52010 URL: http://llvm.org/viewvc/llvm-project?rev=52010&view=rev Log: Move i128 on x86-64 from the codegen section to the x86-specific section. Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=52010&r1=52009&r2=52010&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Thu Jun 5 11:15:39 2008 @@ -200,7 +200,6 @@ than 64 bits. Note that support for such types is also dependent on target-specific support. Use of APInt is also a step toward support for non-power-of-2 integer sizes. -
  • Support for 128-bit integers on X86-64.
  • Several compile time speedups for code with large basic blocks.
  • Several improvements which make llc's --view-sunit-dags visualization of scheduling dependency graphs easier to understand.
    • @@ -266,6 +265,8 @@
  • __builtin_prefetch is now compiled into the appropriate prefetch instructions instead of being ignored.
    • +
  • 128-bit integers are now supported on x86-64 targets.
    • + From resistor at mac.com Thu Jun 5 12:22:53 2008 From: resistor at mac.com (Owen Anderson) Date: Thu, 05 Jun 2008 17:22:53 -0000 Subject: [llvm-commits] [llvm] r52013 - /llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp Message-ID: <200806051722.m55HMrqr030871@zion.cs.uiuc.edu> Author: resistor Date: Thu Jun 5 12:22:53 2008 New Revision: 52013 URL: http://llvm.org/viewvc/llvm-project?rev=52013&view=rev Log: Use the newly created helper on LiveIntervals. Modified: llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp Modified: llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp?rev=52013&r1=52012&r2=52013&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp (original) +++ llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp Thu Jun 5 12:22:53 2008 @@ -52,8 +52,9 @@ // used as operands to another another PHI node std::set UsedByAnother; - // RenameSets are the sets of operands (and their VNInfo IDs) to a PHI - // (the defining instruction of the key) that can be renamed without copies. + // RenameSets are the is a map from a PHI-defined register + // to the input registers to be coalesced along with the index + // of the input registers. std::map > RenameSets; // PhiValueNumber holds the ID numbers of the VNs for each phi that we're @@ -466,15 +467,11 @@ UsedByAnother.insert(SrcReg); } else { // Otherwise, add it to the renaming set - LiveInterval& I = LI.getOrCreateInterval(SrcReg); // We need to subtract one from the index because live ranges are open // at the end. unsigned idx = LI.getMBBEndIdx(P->getOperand(i).getMBB()) - 1; - VNInfo* VN = I.getLiveRangeContaining(idx)->valno; - assert(VN && "No VNInfo for register?"); - - PHIUnion.insert(std::make_pair(SrcReg, VN->id)); + PHIUnion.insert(std::make_pair(SrcReg, idx)); UnionedBlocks.insert(MRI.getVRegDef(SrcReg)->getParent()); } } @@ -744,22 +741,9 @@ // PHI, we don't create multiple overlapping live intervals. std::set RegHandled; for (SmallVector, 4>::iterator I = - InsertedPHIDests.begin(), E = InsertedPHIDests.end(); I != E; ++I) { - if (!RegHandled.count(I->first)) { - LiveInterval& Interval = LI.getOrCreateInterval(I->first); - VNInfo* VN = Interval.getNextValue( - LI.getInstructionIndex(I->second) + LiveIntervals::InstrSlots::DEF, - I->second, LI.getVNInfoAllocator()); - VN->hasPHIKill = true; - VN->kills.push_back(LI.getMBBEndIdx(I->second->getParent())); - LiveRange LR(LI.getInstructionIndex(I->second) + - LiveIntervals::InstrSlots::DEF, - LI.getMBBEndIdx(I->second->getParent()) + 1, VN); - Interval.addRange(LR); - - RegHandled.insert(I->first); - } - } + InsertedPHIDests.begin(), E = InsertedPHIDests.end(); I != E; ++I) + if (!RegHandled.count(I->first)) + LI.addLiveRangeToEndOfBlock(I->first, I->second); } /// InsertCopies - insert copies into MBB and all of its successors @@ -794,111 +778,30 @@ Stacks[*I].pop_back(); } -/// ComputeUltimateVN - Assuming we are going to join two live intervals, -/// compute what the resultant value numbers for each value in the input two -/// ranges will be. This is complicated by copies between the two which can -/// and will commonly cause multiple value numbers to be merged into one. -/// -/// VN is the value number that we're trying to resolve. InstDefiningValue -/// keeps track of the new InstDefiningValue assignment for the result -/// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of -/// whether a value in this or other is a copy from the opposite set. -/// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have -/// already been assigned. -/// -/// ThisFromOther[x] - If x is defined as a copy from the other interval, this -/// contains the value number the copy is from. -/// -static unsigned ComputeUltimateVN(VNInfo *VNI, - SmallVector &NewVNInfo, - DenseMap &ThisFromOther, - DenseMap &OtherFromThis, - SmallVector &ThisValNoAssignments, - SmallVector &OtherValNoAssignments) { - unsigned VN = VNI->id; - - // If the VN has already been computed, just return it. - if (ThisValNoAssignments[VN] >= 0) - return ThisValNoAssignments[VN]; -// assert(ThisValNoAssignments[VN] != -2 && "Cyclic case?"); - - // If this val is not a copy from the other val, then it must be a new value - // number in the destination. - DenseMap::iterator I = ThisFromOther.find(VNI); - if (I == ThisFromOther.end()) { - NewVNInfo.push_back(VNI); - return ThisValNoAssignments[VN] = NewVNInfo.size()-1; - } - VNInfo *OtherValNo = I->second; - - // Otherwise, this *is* a copy from the RHS. If the other side has already - // been computed, return it. - if (OtherValNoAssignments[OtherValNo->id] >= 0) - return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo->id]; - - // Mark this value number as currently being computed, then ask what the - // ultimate value # of the other value is. - ThisValNoAssignments[VN] = -2; - unsigned UltimateVN = - ComputeUltimateVN(OtherValNo, NewVNInfo, OtherFromThis, ThisFromOther, - OtherValNoAssignments, ThisValNoAssignments); - return ThisValNoAssignments[VN] = UltimateVN; -} - void StrongPHIElimination::mergeLiveIntervals(unsigned primary, unsigned secondary, - unsigned secondaryVN) { + unsigned secondaryIdx) { LiveIntervals& LI = getAnalysis(); LiveInterval& LHS = LI.getOrCreateInterval(primary); LiveInterval& RHS = LI.getOrCreateInterval(secondary); - // Compute the final value assignment, assuming that the live ranges can be - // coalesced. - SmallVector LHSValNoAssignments; - SmallVector RHSValNoAssignments; - SmallVector NewVNInfo; - - LHSValNoAssignments.resize(LHS.getNumValNums(), -1); - RHSValNoAssignments.resize(RHS.getNumValNums(), -1); - NewVNInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums()); - - for (LiveInterval::vni_iterator I = LHS.vni_begin(), E = LHS.vni_end(); - I != E; ++I) { - VNInfo *VNI = *I; - unsigned VN = VNI->id; - if (LHSValNoAssignments[VN] >= 0 || VNI->def == ~1U) - continue; - - NewVNInfo.push_back(VNI); - LHSValNoAssignments[VN] = NewVNInfo.size()-1; - } - - for (LiveInterval::vni_iterator I = RHS.vni_begin(), E = RHS.vni_end(); - I != E; ++I) { - VNInfo *VNI = *I; - unsigned VN = VNI->id; - if (RHSValNoAssignments[VN] >= 0 || VNI->def == ~1U) - continue; - - NewVNInfo.push_back(VNI); - RHSValNoAssignments[VN] = NewVNInfo.size()-1; - } - - // If we get here, we know that we can coalesce the live ranges. Ask the - // intervals to coalesce themselves now. - - LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo); - LI.removeInterval(secondary); + LI.computeNumbering(); - // The valno that was previously the input to the PHI node - // now has a PHIKill. - LHS.getValNumInfo(RHSValNoAssignments[secondaryVN])->hasPHIKill = true; + const LiveRange* RangeMergingIn = RHS.getLiveRangeContaining(secondaryIdx); + VNInfo* NewVN = LHS.getNextValue(secondaryIdx, RangeMergingIn->valno->copy, + LI.getVNInfoAllocator()); + NewVN->hasPHIKill = true; + LiveRange NewRange(RangeMergingIn->start, RangeMergingIn->end, NewVN); + LHS.addRange(NewRange); + RHS.removeRange(RangeMergingIn->start, RangeMergingIn->end, true); } bool StrongPHIElimination::runOnMachineFunction(MachineFunction &Fn) { LiveIntervals& LI = getAnalysis(); + LI.dump(); + // Compute DFS numbers of each block computeDFS(Fn); @@ -909,7 +812,7 @@ processBlock(I); // Insert copies - // FIXME: This process should probably preserve LiveVariables + // FIXME: This process should probably preserve LiveIntervals SmallPtrSet visited; InsertCopies(Fn.begin(), visited); @@ -961,5 +864,7 @@ LI.computeNumbering(); + LI.dump(); + return true; } From isanbard at gmail.com Thu Jun 5 13:31:08 2008 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 5 Jun 2008 11:31:08 -0700 Subject: [llvm-commits] [llvm] r52007 - /llvm/trunk/docs/ReleaseNotes.html In-Reply-To: <200806051543.m55FhBTE027382@zion.cs.uiuc.edu> References: <200806051543.m55FhBTE027382@zion.cs.uiuc.edu> Message-ID: <16e5fdf90806051131i1592cb66sb4d4f0a615c70a32@mail.gmail.com> On Thu, Jun 5, 2008 at 8:43 AM, Dan Gohman wrote: > --- llvm/trunk/docs/ReleaseNotes.html (original) > +++ llvm/trunk/docs/ReleaseNotes.html Thu Jun 5 10:43:11 2008 > @@ -195,7 +195,12 @@ > >
      >
    • MemOperand in the code generator: describe me!.
      • > -
    • i128 support and APInt through most of codegen.
      • > +
    • Target-independent codegen infastructure now uses LLVM's APInt class for s/Target/The target/ s/uses/uses the/ s/infastructure/infrastructure/ s/for handling/to handle/ > + handling integer values, which allow it to support integer types larger s/allow/allows/ > + than 64 bits. Note that support for such types is also dependent on > + target-specific support. Use of APInt is also a step toward support for > + non-power-of-2 integer sizes.
      • > +
    • Support for 128-bit integers on X86-64.
      • >
    • Several compile time speedups for code with large basic blocks.
      • >
    > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From ggreif at gmail.com Thu Jun 5 13:39:01 2008 From: ggreif at gmail.com (Gabor Greif) Date: Thu, 05 Jun 2008 18:39:01 -0000 Subject: [llvm-commits] [llvm] r52015 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <200806051839.m55Id1Qi000617@zion.cs.uiuc.edu> Author: ggreif Date: Thu Jun 5 13:39:01 2008 New Revision: 52015 URL: http://llvm.org/viewvc/llvm-project?rev=52015&view=rev Log: fix typos, tweak stuff, make it to validate Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=52015&r1=52014&r2=52015&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Thu Jun 5 13:39:01 2008 @@ -81,7 +81,7 @@

    LLVM 2.2 was the last LLVM release to support llvm-gcc 4.0 and llvm-upgrade. llvm-gcc 4.0 has been replaced with llvm-gcc 4.2. llvm-upgrade was useful for upgrading LLVM 1.9 files to LLVM 2.x syntax, but you can always use a previous -LLVM release to do this. One nice impact of this is that the LLVM regressionn +LLVM release to do this. One nice impact of this is that the LLVM regression test suite no longer depends on llvm-upgrade, which makes it run faster.

    LLVM 2.3 renames the LLVMBuilder and LLVMFoldingBuilder classes to @@ -113,15 +113,15 @@ dispatching them to different tools.

  • Flexible (and extensible) rules for defining different tools.
  • The different intermediate steps performed by tools are represented -as edged in the abstract graph.
    • -The 'language' for driver behaviour definition is tablegen and thus +as edges in the abstract graph. +
  • The 'language' for driver behaviour definition is tablegen and thus it's relatively easy to add new features.
  • The definition of driver is transformed into set of C++ classes, thus no runtime interpretation is needed.
    • - +
  • Reimplemented LTO interface in C.
    • @@ -196,7 +196,7 @@
    • MemOperand in the code generator: describe me!.
    • Target-independent codegen infastructure now uses LLVM's APInt class for - handling integer values, which allow it to support integer types larger + handling integer values, which allows it to support integer types larger than 64 bits. Note that support for such types is also dependent on target-specific support. Use of APInt is also a step toward support for non-power-of-2 integer sizes.
      • @@ -220,12 +220,12 @@
      • Loop index set splitting on by default: describe me.
        • -
      • LLVM includes a new memcpy optimization pass which optimizes out dead -memcpy calls, unneeded copies of aggregates, and handles the return slot +
      • LLVM includes a new memcpy optimization pass which optimizes out dead +memcpy calls, unneeded copies of aggregates, and handles the return slot optimization. The LLVM optimizer now notices long sequences of consequtive -stores and merges them into memcpy's where profitable.
        • -
      • Alignment detection for vector memory references and for memcpy and -memset is now more aggressive.
        • +stores and merges them into memcpys where profitable. +
      • Alignment detection for vector memory references and for memcpy and +memset is now more aggressive.
      @@ -242,7 +242,7 @@
      • llvm-gcc's X86-64 ABI conformance is far improved, particularly in the - area of passing and returning structures by value. llvm-gcc Compiled code + area of passing and returning structures by value. llvm-gcc compiled code now interoperates very well on X86-64 systems with other compilers.
      • The LLVM X86 backend now supports the support SSE 4.1 instruction set, and @@ -281,7 +281,7 @@

          -
        • The LLVM C backend now supports vectors code.
          • +
        • The LLVM C backend now supports vector code.
        @@ -301,7 +301,7 @@
        • LLVM now builds with GCC 4.3.
          • -
        • llvm2cpp tool was moved into llc, use llc -march=cpp
          • +
        • llvm2cpp tool has been folded into llc, use llc -march=cpp
        @@ -317,16 +317,16 @@

        LLVM is known to work on the following platforms:

          -
        • Intel and AMD machines running Red Hat Linux, Fedora Core and FreeBSD +
        • Intel and AMD machines (IA32) running Red Hat Linux, Fedora Core and FreeBSD (and probably other unix-like systems).
        • PowerPC and X86-based Mac OS X systems, running 10.3 and above in 32-bit and 64-bit modes.
        • Intel and AMD machines running on Win32 using MinGW libraries (native).
        • Intel and AMD machines running on Win32 with the Cygwin libraries (limited support is available for native builds with Visual C++).
          • -
        • Sun UltraSPARC workstations running Solaris 8.
          • +
        • Sun UltraSPARC workstations running Solaris 10.
        • Alpha-based machines running Debian GNU/Linux.
          • -
        • Itanium-based machines running Linux and HP-UX.
          • +
        • Itanium-based (IA64) machines running Linux and HP-UX.

        The core LLVM infrastructure uses GNU autoconf to adapt itself @@ -573,11 +573,11 @@ or finish at a non-byte offset in a record. Workaround: do not pack records or use representation clauses that result in a field of a non-discrete type starting or finishing in the middle of a byte.

        • -
      • The lli interpreter considers 'main' +
      • The lli interpreter considers 'main' as generated by the Ada binder to be invalid. -Workaround: hand edit the file to use pointers for argv and envp rather than +Workaround: hand edit the file to use pointers for argv and envp rather than integers.
        • -
      • The -fstack-check option is ignored.
        • +
      • The -fstack-check option is ignored.
      @@ -590,7 +590,7 @@ From isanbard at gmail.com Thu Jun 5 13:39:13 2008 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 5 Jun 2008 11:39:13 -0700 Subject: [llvm-commits] [llvm] r52013 - /llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp In-Reply-To: <200806051722.m55HMrqr030871@zion.cs.uiuc.edu> References: <200806051722.m55HMrqr030871@zion.cs.uiuc.edu> Message-ID: <16e5fdf90806051139u72d737e6qabb95da6492522a0@mail.gmail.com> On Thu, Jun 5, 2008 at 10:22 AM, Owen Anderson wrote: > --- llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp (original) > +++ llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp Thu Jun 5 12:22:53 2008 ... > > bool StrongPHIElimination::runOnMachineFunction(MachineFunction &Fn) { > LiveIntervals& LI = getAnalysis(); > > + LI.dump(); > + Debugging code? > // Compute DFS numbers of each block > computeDFS(Fn); > > @@ -909,7 +812,7 @@ > processBlock(I); > > // Insert copies > - // FIXME: This process should probably preserve LiveVariables > + // FIXME: This process should probably preserve LiveIntervals > SmallPtrSet visited; > InsertCopies(Fn.begin(), visited); > > @@ -961,5 +864,7 @@ > > LI.computeNumbering(); > > + LI.dump(); > + Also here? -bw From resistor at mac.com Thu Jun 5 13:43:34 2008 From: resistor at mac.com (Owen Anderson) Date: Thu, 05 Jun 2008 18:43:34 -0000 Subject: [llvm-commits] [llvm] r52016 - /llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp Message-ID: <200806051843.m55IhYlM000752@zion.cs.uiuc.edu> Author: resistor Date: Thu Jun 5 13:43:34 2008 New Revision: 52016 URL: http://llvm.org/viewvc/llvm-project?rev=52016&view=rev Log: Remove debugging code. Modified: llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp Modified: llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp?rev=52016&r1=52015&r2=52016&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp (original) +++ llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp Thu Jun 5 13:43:34 2008 @@ -800,8 +800,6 @@ bool StrongPHIElimination::runOnMachineFunction(MachineFunction &Fn) { LiveIntervals& LI = getAnalysis(); - LI.dump(); - // Compute DFS numbers of each block computeDFS(Fn); @@ -864,7 +862,5 @@ LI.computeNumbering(); - LI.dump(); - return true; } From gohman at apple.com Thu Jun 5 13:45:33 2008 From: gohman at apple.com (Dan Gohman) Date: Thu, 05 Jun 2008 18:45:33 -0000 Subject: [llvm-commits] [llvm] r52017 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <200806051845.m55IjXUr000816@zion.cs.uiuc.edu> Author: djg Date: Thu Jun 5 13:45:33 2008 New Revision: 52017 URL: http://llvm.org/viewvc/llvm-project?rev=52017&view=rev Log: Wording fixes. Thanks Bill! Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=52017&r1=52016&r2=52017&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Thu Jun 5 13:45:33 2008 @@ -195,9 +195,9 @@
      • MemOperand in the code generator: describe me!.
        • -
      • Target-independent codegen infastructure now uses LLVM's APInt class for - handling integer values, which allows it to support integer types larger - than 64 bits. Note that support for such types is also dependent on +
      • The target-independent code generator infrastructure now uses LLVM's APInt + class to handle integer values, which allows it to support integer types + larger than 64 bits. Note that support for such types is also dependent on target-specific support. Use of APInt is also a step toward support for non-power-of-2 integer sizes.
      • Several compile time speedups for code with large basic blocks.
        • From gohman at apple.com Thu Jun 5 13:49:17 2008 From: gohman at apple.com (Dan Gohman) Date: Thu, 5 Jun 2008 11:49:17 -0700 Subject: [llvm-commits] [llvm] r52007 - /llvm/trunk/docs/ReleaseNotes.html In-Reply-To: <16e5fdf90806051131i1592cb66sb4d4f0a615c70a32@mail.gmail.com> References: <200806051543.m55FhBTE027382@zion.cs.uiuc.edu> <16e5fdf90806051131i1592cb66sb4d4f0a615c70a32@mail.gmail.com> Message-ID: <5F953FC8-12B3-466A-B352-9EAD95A75EAD@apple.com> On Jun 5, 2008, at 11:31 AM, Bill Wendling wrote: > On Thu, Jun 5, 2008 at 8:43 AM, Dan Gohman wrote: >> --- llvm/trunk/docs/ReleaseNotes.html (original) >> +++ llvm/trunk/docs/ReleaseNotes.html Thu Jun 5 10:43:11 2008 >> @@ -195,7 +195,12 @@ >> >>
          >>
        • MemOperand in the code generator: describe me!.
          • >> -
        • i128 support and APInt through most of codegen.
          • >> +
        • Target-independent codegen infastructure now uses LLVM's APInt >> class for > > s/Target/The target/ > > s/uses/uses the/ > > s/infastructure/infrastructure/ > > s/for handling/to handle/ I made thes changes, except for the s/users/users the/ one. The rest of the document just talks about "LLVM", not "the LLVM". > >> + handling integer values, which allow it to support integer >> types larger > > s/allow/allows/ Looks like Gabor beat me to fixing this one :-). Thanks! Dan From criswell at uiuc.edu Thu Jun 5 15:14:48 2008 From: criswell at uiuc.edu (John Criswell) Date: Thu, 05 Jun 2008 20:14:48 -0000 Subject: [llvm-commits] [poolalloc] r52018 - /poolalloc/trunk/lib/DSA/StdLibPass.cpp Message-ID: <200806052014.m55KEm91003822@zion.cs.uiuc.edu> Author: criswell Date: Thu Jun 5 15:14:48 2008 New Revision: 52018 URL: http://llvm.org/viewvc/llvm-project?rev=52018&view=rev Log: Do not create a DSGraph for realloc() if it does not return a pointer. Modified: poolalloc/trunk/lib/DSA/StdLibPass.cpp Modified: poolalloc/trunk/lib/DSA/StdLibPass.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/StdLibPass.cpp?rev=52018&r1=52017&r2=52018&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/StdLibPass.cpp (original) +++ poolalloc/trunk/lib/DSA/StdLibPass.cpp Thu Jun 5 15:14:48 2008 @@ -54,10 +54,12 @@ Graph.getReturnNodeFor(*I).getNode()->clearNodeFlags() ->setHeapMarker()->setModifiedMarker(); } else if (Name == "realloc") { - Graph.getReturnNodeFor(*I).getNode()->clearNodeFlags() - ->setHeapMarker()->setModifiedMarker(); - Graph.getNodeForValue(I->arg_begin()).getNode()->clearNodeFlags() - ->mergeWith(Graph.getReturnNodeFor(*I), 0); + if (isa(I->getReturnType())) { + Graph.getReturnNodeFor(*I).getNode()->clearNodeFlags() + ->setHeapMarker()->setModifiedMarker(); + Graph.getNodeForValue(I->arg_begin()).getNode()->clearNodeFlags() + ->mergeWith(Graph.getReturnNodeFor(*I), 0); + } } else if (Name == "strdup") { Graph.getReturnNodeFor(*I).getNode()->clearNodeFlags() ->setHeapMarker()->setModifiedMarker(); From nicolas.geoffray at lip6.fr Thu Jun 5 15:55:45 2008 From: nicolas.geoffray at lip6.fr (Nicolas Geoffray) Date: Thu, 05 Jun 2008 20:55:45 -0000 Subject: [llvm-commits] [vmkit] r52019 - /vmkit/trunk/lib/JnJVM/Classpath/Classpath.cpp Message-ID: <200806052055.m55Ktjt7005646@zion.cs.uiuc.edu> Author: geoffray Date: Thu Jun 5 15:55:44 2008 New Revision: 52019 URL: http://llvm.org/viewvc/llvm-project?rev=52019&view=rev Log: the class given to createObjectArray is the base class, not the array class. Modified: vmkit/trunk/lib/JnJVM/Classpath/Classpath.cpp Modified: vmkit/trunk/lib/JnJVM/Classpath/Classpath.cpp URL: http://llvm.org/viewvc/llvm-project/vmkit/trunk/lib/JnJVM/Classpath/Classpath.cpp?rev=52019&r1=52018&r2=52019&view=diff ============================================================================== --- vmkit/trunk/lib/JnJVM/Classpath/Classpath.cpp (original) +++ vmkit/trunk/lib/JnJVM/Classpath/Classpath.cpp Thu Jun 5 15:55:44 2008 @@ -165,8 +165,14 @@ jclass arrayType, jint arrayLength) { Jnjvm* vm = JavaThread::get()->isolate; - ClassArray* cl = (ClassArray*)NativeUtil::resolvedImplClass(arrayType, true); - return (jobject) ArrayObject::acons((sint32)arrayLength, cl, vm); + CommonClass* base = NativeUtil::resolvedImplClass(arrayType, true); + JavaObject* loader = base->classLoader; + const UTF8* name = base->name; + const UTF8* arrayName = AssessorDesc::constructArrayName(vm, 0, 1, name); + ClassArray* array = vm->constructArray(arrayName, loader); + ArrayObject* res = ArrayObject::acons(arrayLength, array, vm); + + return (jobject) res; } From nicolas.geoffray at lip6.fr Thu Jun 5 15:56:28 2008 From: nicolas.geoffray at lip6.fr (Nicolas Geoffray) Date: Thu, 05 Jun 2008 20:56:28 -0000 Subject: [llvm-commits] [vmkit] r52020 - /vmkit/trunk/lib/JnJVM/Classpath/ClasspathVMThrowable.cpp Message-ID: <200806052056.m55KuTlE005693@zion.cs.uiuc.edu> Author: geoffray Date: Thu Jun 5 15:56:28 2008 New Revision: 52020 URL: http://llvm.org/viewvc/llvm-project?rev=52020&view=rev Log: Jitted methods are not allocated by the GC anymore. Modified: vmkit/trunk/lib/JnJVM/Classpath/ClasspathVMThrowable.cpp Modified: vmkit/trunk/lib/JnJVM/Classpath/ClasspathVMThrowable.cpp URL: http://llvm.org/viewvc/llvm-project/vmkit/trunk/lib/JnJVM/Classpath/ClasspathVMThrowable.cpp?rev=52020&r1=52019&r2=52020&view=diff ============================================================================== --- vmkit/trunk/lib/JnJVM/Classpath/ClasspathVMThrowable.cpp (original) +++ vmkit/trunk/lib/JnJVM/Classpath/ClasspathVMThrowable.cpp Thu Jun 5 15:56:28 2008 @@ -74,12 +74,7 @@ ArrayObject* recGetStackTrace(int** stack, uint32 first, uint32 rec) { Jnjvm* vm = JavaThread::get()->isolate; if (stack[first] != 0) { -#ifdef MULTIPLE_GC - int *begIp = (int*)mvm::Thread::get()->GC->begOf(stack[first]); -#else - int *begIp = (int*)Collector::begOf(stack[first]); -#endif - JavaMethod* meth = JavaJIT::IPToJavaMethod(begIp); + JavaMethod* meth = JavaJIT::IPToJavaMethod(stack[first]); if (meth) { ArrayObject* res = recGetStackTrace(stack, first + 1, rec + 1); res->elements[rec] = consStackElement(meth, stack[first]); From isanbard at gmail.com Thu Jun 5 16:34:56 2008 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 5 Jun 2008 14:34:56 -0700 Subject: [llvm-commits] [llvm] r52007 - /llvm/trunk/docs/ReleaseNotes.html In-Reply-To: <5F953FC8-12B3-466A-B352-9EAD95A75EAD@apple.com> References: <200806051543.m55FhBTE027382@zion.cs.uiuc.edu> <16e5fdf90806051131i1592cb66sb4d4f0a615c70a32@mail.gmail.com> <5F953FC8-12B3-466A-B352-9EAD95A75EAD@apple.com> Message-ID: <16e5fdf90806051434n4bc192b9oeb056d137b31d6df@mail.gmail.com> On Thu, Jun 5, 2008 at 11:49 AM, Dan Gohman wrote: > > On Jun 5, 2008, at 11:31 AM, Bill Wendling wrote: > >> On Thu, Jun 5, 2008 at 8:43 AM, Dan Gohman wrote: >>> --- llvm/trunk/docs/ReleaseNotes.html (original) >>> +++ llvm/trunk/docs/ReleaseNotes.html Thu Jun 5 10:43:11 2008 >>> @@ -195,7 +195,12 @@ >>> >>>
            >>>
          • MemOperand in the code generator: describe me!.
            • >>> -
          • i128 support and APInt through most of codegen.
            • >>> +
          • Target-independent codegen infastructure now uses LLVM's APInt >>> class for >> >> s/uses/uses the/ >> > > I made thes changes, except for the s/users/users the/ one. The rest > of the document just talks about "LLVM", not "the LLVM". > That was a brain-fart on my part. :-) Thanks! -bw >> >>> + handling integer values, which allow it to support integer >>> types larger >> >> s/allow/allows/ > > Looks like Gabor beat me to fixing this one :-). > > Thanks! > > Dan > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From andrewl at lenharth.org Thu Jun 5 16:35:16 2008 From: andrewl at lenharth.org (Andrew Lenharth) Date: Thu, 5 Jun 2008 16:35:16 -0500 Subject: [llvm-commits] [llvm] r50663 - in /llvm/trunk: include/llvm/ include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/ lib/Target/X86/ test/CodeGen/X86/ In-Reply-To: <200805051906.m45J60NF001231@zion.cs.uiuc.edu> References: <200805051906.m45J60NF001231@zion.cs.uiuc.edu> Message-ID: <85dfcd7f0806051435l5e575140y5c5a41c037a0c19e@mail.gmail.com> The language reference needs to be updated with these intrinsics. Andrew On Mon, May 5, 2008 at 2:05 PM, Mon P Wang wrote: > Author: wangmp > Date: Mon May 5 14:05:59 2008 > New Revision: 50663 > > URL: http://llvm.org/viewvc/llvm-project?rev=50663&view=rev > Log: > Added addition atomic instrinsics and, or, xor, min, and max. > > Added: > llvm/trunk/test/CodeGen/X86/atomic_op.ll > Modified: > llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h > llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h > llvm/trunk/include/llvm/Intrinsics.td > llvm/trunk/include/llvm/Target/TargetLowering.h > llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp > llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp > llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp > llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp > llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp > llvm/trunk/lib/Target/TargetSelectionDAG.td > llvm/trunk/lib/Target/X86/X86ISelLowering.cpp > llvm/trunk/lib/Target/X86/X86ISelLowering.h > llvm/trunk/lib/Target/X86/X86InstrInfo.td > llvm/trunk/lib/Target/X86/X86Subtarget.cpp > > Modified: llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h?rev=50663&r1=50662&r2=50663&view=diff > > ============================================================================== > --- llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h (original) > +++ llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h Mon May 5 14:05:59 2008 > @@ -236,6 +236,11 @@ > /// > succ_iterator removeSuccessor(succ_iterator I); > > + /// transferSuccessors - Transfers all the successors from MBB to this > + /// machine basic block (i.e., copies all the successors fromMBB and > + /// remove all the successors fromBB). > + void transferSuccessors(MachineBasicBlock *fromMBB); > + > /// isSuccessor - Return true if the specified MBB is a successor of this > /// block. > bool isSuccessor(MachineBasicBlock *MBB) const; > > Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=50663&r1=50662&r2=50663&view=diff > > ============================================================================== > --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original) > +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Mon May 5 14:05:59 2008 > @@ -594,6 +594,24 @@ > // the return is always the original value in *ptr > ATOMIC_SWAP, > > + // Val, OUTCHAIN = ATOMIC_LSS(INCHAIN, ptr, amt) > + // this corresponds to the atomic.lss intrinsic. > + // *ptr - amt is stored to *ptr atomically. > + // the return is always the original value in *ptr > + ATOMIC_LSS, > + > + // Val, OUTCHAIN = ATOMIC_L[OpName]S(INCHAIN, ptr, amt) > + // this corresponds to the atomic.[OpName] intrinsic. > + // op(*ptr, amt) is stored to *ptr atomically. > + // the return is always the original value in *ptr > + ATOMIC_LOAD_AND, > + ATOMIC_LOAD_OR, > + ATOMIC_LOAD_XOR, > + ATOMIC_LOAD_MIN, > + ATOMIC_LOAD_MAX, > + ATOMIC_LOAD_UMIN, > + ATOMIC_LOAD_UMAX, > + > // BUILTIN_OP_END - This must be the last enum value in this list. > BUILTIN_OP_END > }; > > Modified: llvm/trunk/include/llvm/Intrinsics.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Intrinsics.td?rev=50663&r1=50662&r2=50663&view=diff > > ============================================================================== > --- llvm/trunk/include/llvm/Intrinsics.td (original) > +++ llvm/trunk/include/llvm/Intrinsics.td Mon May 5 14:05:59 2008 > @@ -267,22 +267,62 @@ > def int_memory_barrier : Intrinsic<[llvm_void_ty, llvm_i1_ty, llvm_i1_ty, > llvm_i1_ty, llvm_i1_ty, llvm_i1_ty], []>; > > -def int_atomic_lcs : Intrinsic<[llvm_anyint_ty, > - LLVMPointerType>, > - LLVMMatchType<0>, LLVMMatchType<0>], > +def int_atomic_lcs : Intrinsic<[llvm_anyint_ty, > + LLVMPointerType>, > + LLVMMatchType<0>, LLVMMatchType<0>], > + [IntrWriteArgMem]>, > + GCCBuiltin<"__sync_val_compare_and_swap">; > +def int_atomic_las : Intrinsic<[llvm_anyint_ty, > + LLVMPointerType>, > + LLVMMatchType<0>], > + [IntrWriteArgMem]>, > + GCCBuiltin<"__sync_fetch_and_add">; > +def int_atomic_swap : Intrinsic<[llvm_anyint_ty, > + LLVMPointerType>, > + LLVMMatchType<0>], > [IntrWriteArgMem]>, > - GCCBuiltin<"__sync_val_compare_and_swap">; > -def int_atomic_las : Intrinsic<[llvm_anyint_ty, > - LLVMPointerType>, > - LLVMMatchType<0>], > - [IntrWriteArgMem]>, > - GCCBuiltin<"__sync_fetch_and_add">; > -def int_atomic_swap : Intrinsic<[llvm_anyint_ty, > - LLVMPointerType>, > - LLVMMatchType<0>], > - [IntrWriteArgMem]>, > - GCCBuiltin<"__sync_lock_test_and_set">; > - > + GCCBuiltin<"__sync_lock_test_and_set">; > +def int_atomic_lss : Intrinsic<[llvm_anyint_ty, > + LLVMPointerType>, > + LLVMMatchType<0>], > + [IntrWriteArgMem]>, > + GCCBuiltin<"__sync_fetch_and_sub">; > +def int_atomic_load_and : Intrinsic<[llvm_anyint_ty, > + LLVMPointerType>, > + LLVMMatchType<0>], > + [IntrWriteArgMem]>, > + GCCBuiltin<"__sync_fetch_and_and">; > +def int_atomic_load_or : Intrinsic<[llvm_anyint_ty, > + LLVMPointerType>, > + LLVMMatchType<0>], > + [IntrWriteArgMem]>, > + GCCBuiltin<"__sync_fetch_and_or">; > +def int_atomic_load_xor : Intrinsic<[llvm_anyint_ty, > + LLVMPointerType>, > + LLVMMatchType<0>], > + [IntrWriteArgMem]>, > + GCCBuiltin<"__sync_fetch_and_xor">; > +def int_atomic_load_min : Intrinsic<[llvm_anyint_ty, > + LLVMPointerType>, > + LLVMMatchType<0>], > + [IntrWriteArgMem]>, > + GCCBuiltin<"__sync_fetch_and_min">; > +def int_atomic_load_max : Intrinsic<[llvm_anyint_ty, > + LLVMPointerType>, > + LLVMMatchType<0>], > + [IntrWriteArgMem]>, > + GCCBuiltin<"__sync_fetch_and_max">; > +def int_atomic_load_umin : Intrinsic<[llvm_anyint_ty, > + LLVMPointerType>, > + LLVMMatchType<0>], > + [IntrWriteArgMem]>, > + GCCBuiltin<"__sync_fetch_and_umin">; > +def int_atomic_load_umax : Intrinsic<[llvm_anyint_ty, > + LLVMPointerType>, > + LLVMMatchType<0>], > + [IntrWriteArgMem]>, > + GCCBuiltin<"__sync_fetch_and_umax">; > + > //===-------------------------- Other Intrinsics --------------------------===// > // > def int_flt_rounds : Intrinsic<[llvm_i32_ty]>, > > Modified: llvm/trunk/include/llvm/Target/TargetLowering.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=50663&r1=50662&r2=50663&view=diff > > ============================================================================== > --- llvm/trunk/include/llvm/Target/TargetLowering.h (original) > +++ llvm/trunk/include/llvm/Target/TargetLowering.h Mon May 5 14:05:59 2008 > @@ -1340,12 +1340,15 @@ > /// by the system, this holds the same type (e.g. i32 -> i32). > MVT::ValueType TransformToType[MVT::LAST_VALUETYPE]; > > + // Defines the capacity of the TargetLowering::OpActions table > + static const int OpActionsCapacity = 173; > + > /// OpActions - For each operation and each value type, keep a LegalizeAction > /// that indicates how instruction selection should deal with the operation. > /// Most operations are Legal (aka, supported natively by the target), but > /// operations that are not should be described. Note that operations on > /// non-legal value types are not described here. > - uint64_t OpActions[156]; > + uint64_t OpActions[OpActionsCapacity]; > > /// LoadXActions - For each load of load extension type and each value type, > /// keep a LegalizeAction that indicates how instruction selection should deal > @@ -1378,7 +1381,7 @@ > /// TargetDAGCombineArray - Targets can specify ISD nodes that they would > /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(), > /// which sets a bit in this array. > - unsigned char TargetDAGCombineArray[160/(sizeof(unsigned char)*8)]; > + unsigned char TargetDAGCombineArray[168/(sizeof(unsigned char)*8)]; > > /// PromoteToType - For operations that must be promoted to a specific type, > /// this holds the destination type. This map should be sparse, so don't hold > > Modified: llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp?rev=50663&r1=50662&r2=50663&view=diff > > ============================================================================== > --- llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp (original) > +++ llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp Mon May 5 14:05:59 2008 > @@ -252,6 +252,19 @@ > Predecessors.erase(I); > } > > +void MachineBasicBlock::transferSuccessors(MachineBasicBlock *fromMBB) > +{ > + if (this == fromMBB) > + return; > + > + for(MachineBasicBlock::succ_iterator iter = fromMBB->succ_begin(), > + end = fromMBB->succ_end(); iter != end; ++iter) { > + addSuccessor(*iter); > + } > + while(!fromMBB->succ_empty()) > + fromMBB->removeSuccessor(fromMBB->succ_begin()); > +} > + > bool MachineBasicBlock::isSuccessor(MachineBasicBlock *MBB) const { > std::vector::const_iterator I = > std::find(Successors.begin(), Successors.end(), MBB); > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=50663&r1=50662&r2=50663&view=diff > > ============================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon May 5 14:05:59 2008 > @@ -1235,32 +1235,58 @@ > break; > } > > - case ISD::ATOMIC_LCS: > + case ISD::ATOMIC_LCS: { > + unsigned int num_operands = 4; > + assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!"); > + SDOperand Ops[4]; > + for (unsigned int x = 0; x < num_operands; ++x) > + Ops[x] = LegalizeOp(Node->getOperand(x)); > + Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands); > + > + switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { > + default: assert(0 && "This action is not supported yet!"); > + case TargetLowering::Custom: > + Result = TLI.LowerOperation(Result, DAG); > + break; > + case TargetLowering::Legal: > + break; > + } > + AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); > + AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); > + return Result.getValue(Op.ResNo); > + } > case ISD::ATOMIC_LAS: > + case ISD::ATOMIC_LSS: > + case ISD::ATOMIC_LOAD_AND: > + case ISD::ATOMIC_LOAD_OR: > + case ISD::ATOMIC_LOAD_XOR: > + case ISD::ATOMIC_LOAD_MIN: > + case ISD::ATOMIC_LOAD_MAX: > + case ISD::ATOMIC_LOAD_UMIN: > + case ISD::ATOMIC_LOAD_UMAX: > case ISD::ATOMIC_SWAP: { > - assert(((Node->getNumOperands() == 4 && Node->getOpcode() == ISD::ATOMIC_LCS) || > - (Node->getNumOperands() == 3 && Node->getOpcode() == ISD::ATOMIC_LAS) || > - (Node->getNumOperands() == 3 && Node->getOpcode() == ISD::ATOMIC_SWAP)) && > - "Invalid Atomic node!"); > - int num = Node->getOpcode() == ISD::ATOMIC_LCS ? 4 : 3; > - SDOperand Ops[4]; > - for (int x = 0; x < num; ++x) > + unsigned int num_operands = 3; > + assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!"); > + SDOperand Ops[3]; > + for (unsigned int x = 0; x < num_operands; ++x) > Ops[x] = LegalizeOp(Node->getOperand(x)); > - Result = DAG.UpdateNodeOperands(Result, &Ops[0], num); > + Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands); > > switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { > default: assert(0 && "This action is not supported yet!"); > case TargetLowering::Custom: > Result = TLI.LowerOperation(Result, DAG); > break; > + case TargetLowering::Expand: > + Result = SDOperand(TLI.ExpandOperationResult(Op.Val, DAG),0); > + break; > case TargetLowering::Legal: > break; > } > AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); > AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); > return Result.getValue(Op.ResNo); > - } > - > + } > case ISD::Constant: { > ConstantSDNode *CN = cast(Node); > unsigned opAction = > @@ -4242,6 +4268,14 @@ > break; > } > case ISD::ATOMIC_LAS: > + case ISD::ATOMIC_LSS: > + case ISD::ATOMIC_LOAD_AND: > + case ISD::ATOMIC_LOAD_OR: > + case ISD::ATOMIC_LOAD_XOR: > + case ISD::ATOMIC_LOAD_MIN: > + case ISD::ATOMIC_LOAD_MAX: > + case ISD::ATOMIC_LOAD_UMIN: > + case ISD::ATOMIC_LOAD_UMAX: > case ISD::ATOMIC_SWAP: { > Tmp2 = PromoteOp(Node->getOperand(2)); > Result = DAG.getAtomic(Node->getOpcode(), Node->getOperand(0), > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=50663&r1=50662&r2=50663&view=diff > > ============================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Mon May 5 14:05:59 2008 > @@ -2855,7 +2855,11 @@ > SDOperand SelectionDAG::getAtomic(unsigned Opcode, SDOperand Chain, > SDOperand Ptr, SDOperand Val, > MVT::ValueType VT) { > - assert((Opcode == ISD::ATOMIC_LAS || Opcode == ISD::ATOMIC_SWAP) > + assert(( Opcode == ISD::ATOMIC_LAS || Opcode == ISD::ATOMIC_LSS > + || Opcode == ISD::ATOMIC_SWAP || Opcode == ISD::ATOMIC_LOAD_AND > + || Opcode == ISD::ATOMIC_LOAD_OR || Opcode == ISD::ATOMIC_LOAD_XOR > + || Opcode == ISD::ATOMIC_LOAD_MIN || Opcode == ISD::ATOMIC_LOAD_MAX > + || Opcode == ISD::ATOMIC_LOAD_UMIN || Opcode == ISD::ATOMIC_LOAD_UMAX) > && "Invalid Atomic Op"); > SDVTList VTs = getVTList(Val.getValueType(), MVT::Other); > FoldingSetNodeID ID; > @@ -4269,7 +4273,15 @@ > case ISD::MEMBARRIER: return "MemBarrier"; > case ISD::ATOMIC_LCS: return "AtomicLCS"; > case ISD::ATOMIC_LAS: return "AtomicLAS"; > - case ISD::ATOMIC_SWAP: return "AtomicSWAP"; > + case ISD::ATOMIC_LSS: return "AtomicLSS"; > + case ISD::ATOMIC_LOAD_AND: return "AtomicLoadAnd"; > + case ISD::ATOMIC_LOAD_OR: return "AtomicLoadOr"; > + case ISD::ATOMIC_LOAD_XOR: return "AtomicLoadXor"; > + case ISD::ATOMIC_LOAD_MIN: return "AtomicLoadMin"; > + case ISD::ATOMIC_LOAD_MAX: return "AtomicLoadMax"; > + case ISD::ATOMIC_LOAD_UMIN: return "AtomicLoadUMin"; > + case ISD::ATOMIC_LOAD_UMAX: return "AtomicLoadUMax"; > + case ISD::ATOMIC_SWAP: return "AtomicSWAP"; > case ISD::PCMARKER: return "PCMarker"; > case ISD::READCYCLECOUNTER: return "ReadCycleCounter"; > case ISD::SRCVALUE: return "SrcValue"; > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=50663&r1=50662&r2=50663&view=diff > > ============================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon May 5 14:05:59 2008 > @@ -732,6 +732,10 @@ > assert(0 && "UserOp2 should not exist at instruction selection time!"); > abort(); > } > + > +private: > + inline const char *implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op); > + > }; > } // end namespace llvm > > @@ -2769,6 +2773,22 @@ > } > } > > + > +/// Inlined utility function to implement binary input atomic intrinsics for > +// visitIntrinsicCall: I is a call instruction > +// Op is the associated NodeType for I > +const char * > +SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) { > + SDOperand Root = getRoot(); > + SDOperand O2 = getValue(I.getOperand(2)); > + SDOperand L = DAG.getAtomic(Op, Root, > + getValue(I.getOperand(1)), > + O2, O2.getValueType()); > + setValue(&I, L); > + DAG.setRoot(L.getValue(1)); > + return 0; > +} > + > /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If > /// we want to emit this as a call to a named external function, return the name > /// otherwise lower it and return null. > @@ -3205,27 +3225,26 @@ > DAG.setRoot(L.getValue(1)); > return 0; > } > - case Intrinsic::atomic_las: { > - SDOperand Root = getRoot(); > - SDOperand O2 = getValue(I.getOperand(2)); > - SDOperand L = DAG.getAtomic(ISD::ATOMIC_LAS, Root, > - getValue(I.getOperand(1)), > - O2, O2.getValueType()); > - setValue(&I, L); > - DAG.setRoot(L.getValue(1)); > - return 0; > - } > - case Intrinsic::atomic_swap: { > - SDOperand Root = getRoot(); > - SDOperand O2 = getValue(I.getOperand(2)); > - SDOperand L = DAG.getAtomic(ISD::ATOMIC_SWAP, Root, > - getValue(I.getOperand(1)), > - O2, O2.getValueType()); > - setValue(&I, L); > - DAG.setRoot(L.getValue(1)); > - return 0; > - } > - > + case Intrinsic::atomic_las: > + return implVisitBinaryAtomic(I, ISD::ATOMIC_LAS); > + case Intrinsic::atomic_lss: > + return implVisitBinaryAtomic(I, ISD::ATOMIC_LSS); > + case Intrinsic::atomic_load_and: > + return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND); > + case Intrinsic::atomic_load_or: > + return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR); > + case Intrinsic::atomic_load_xor: > + return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR); > + case Intrinsic::atomic_load_min: > + return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN); > + case Intrinsic::atomic_load_max: > + return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX); > + case Intrinsic::atomic_load_umin: > + return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN); > + case Intrinsic::atomic_load_umax: > + return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX); > + case Intrinsic::atomic_swap: > + return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP); > } > } > > @@ -4519,8 +4538,6 @@ > AU.setPreservesAll(); > } > > - > - > bool SelectionDAGISel::runOnFunction(Function &Fn) { > // Get alias analysis for load/store combining. > AA = &getAnalysis(); > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=50663&r1=50662&r2=50663&view=diff > > ============================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Mon May 5 14:05:59 2008 > @@ -165,7 +165,7 @@ > > TargetLowering::TargetLowering(TargetMachine &tm) > : TM(tm), TD(TM.getTargetData()) { > - assert(ISD::BUILTIN_OP_END <= 156 && > + assert(ISD::BUILTIN_OP_END <= OpActionsCapacity && > "Fixed size array in TargetLowering is not large enough!"); > // All operations default to being supported. > memset(OpActions, 0, sizeof(OpActions)); > > Modified: llvm/trunk/lib/Target/TargetSelectionDAG.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetSelectionDAG.td?rev=50663&r1=50662&r2=50663&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/TargetSelectionDAG.td (original) > +++ llvm/trunk/lib/Target/TargetSelectionDAG.td Mon May 5 14:05:59 2008 > @@ -358,6 +358,22 @@ > [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; > def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", STDAtomic2, > [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; > +def atomic_lss : SDNode<"ISD::ATOMIC_LSS" , STDAtomic2, > + [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; > +def atomic_load_and : SDNode<"ISD::ATOMIC_LOAD_AND" , STDAtomic2, > + [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; > +def atomic_load_or : SDNode<"ISD::ATOMIC_LOAD_OR" , STDAtomic2, > + [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; > +def atomic_load_xor : SDNode<"ISD::ATOMIC_LOAD_XOR" , STDAtomic2, > + [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; > +def atomic_load_min : SDNode<"ISD::ATOMIC_LOAD_MIN", STDAtomic2, > + [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; > +def atomic_load_max : SDNode<"ISD::ATOMIC_LOAD_MAX", STDAtomic2, > + [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; > +def atomic_load_umin : SDNode<"ISD::ATOMIC_LOAD_UMIN", STDAtomic2, > + [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; > +def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", STDAtomic2, > + [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; > > // Do not use ld, st directly. Use load, extload, sextload, zextload, store, > // and truncst (see below). > > Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=50663&r1=50662&r2=50663&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) > +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon May 5 14:05:59 2008 > @@ -292,10 +292,12 @@ > if (!Subtarget->hasSSE2()) > setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand); > > + // Expand certain atomics > setOperationAction(ISD::ATOMIC_LCS , MVT::i8, Custom); > setOperationAction(ISD::ATOMIC_LCS , MVT::i16, Custom); > setOperationAction(ISD::ATOMIC_LCS , MVT::i32, Custom); > setOperationAction(ISD::ATOMIC_LCS , MVT::i64, Custom); > + setOperationAction(ISD::ATOMIC_LSS , MVT::i32, Expand); > > // Use the default ISD::LOCATION, ISD::DECLARE expansion. > setOperationAction(ISD::LOCATION, MVT::Other, Expand); > @@ -5511,6 +5513,15 @@ > return DAG.getNode(ISD::MERGE_VALUES, Tys, ResultVal, cpOutH.getValue(1)).Val; > } > > +SDNode* X86TargetLowering::ExpandATOMIC_LSS(SDNode* Op, SelectionDAG &DAG) { > + MVT::ValueType T = cast(Op)->getVT(); > + assert (T == MVT::i32 && "Only know how to expand i32 LSS"); > + SDOperand negOp = DAG.getNode(ISD::SUB, T, > + DAG.getConstant(0, T), Op->getOperand(2)); > + return DAG.getAtomic(ISD::ATOMIC_LAS, Op->getOperand(0), > + Op->getOperand(1), negOp, T).Val; > +} > + > /// LowerOperation - Provide custom lowering hooks for some operations. > /// > SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { > @@ -5568,6 +5579,7 @@ > case ISD::FP_TO_SINT: return ExpandFP_TO_SINT(N, DAG); > case ISD::READCYCLECOUNTER: return ExpandREADCYCLECOUNTER(N, DAG); > case ISD::ATOMIC_LCS: return ExpandATOMIC_LCS(N, DAG); > + case ISD::ATOMIC_LSS: return ExpandATOMIC_LSS(N,DAG); > } > } > > @@ -5732,6 +5744,187 @@ > // X86 Scheduler Hooks > //===----------------------------------------------------------------------===// > > +// private utility function > +MachineBasicBlock * > +X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr, > + MachineBasicBlock *MBB, > + unsigned regOpc, > + unsigned immOpc) { > + // For the atomic bitwise operator, we generate > + // thisMBB: > + // newMBB: > + // ld EAX = [bitinstr.addr] > + // mov t1 = EAX > + // op t2 = t1, [bitinstr.val] > + // lcs dest = [bitinstr.addr], t2 [EAX is implicit] > + // bz newMBB > + // fallthrough -->nextMBB > + const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); > + const BasicBlock *LLVM_BB = MBB->getBasicBlock(); > + ilist::iterator MBBIter = MBB; > + ++MBBIter; > + > + /// First build the CFG > + MachineFunction *F = MBB->getParent(); > + MachineBasicBlock *thisMBB = MBB; > + MachineBasicBlock *newMBB = new MachineBasicBlock(LLVM_BB); > + MachineBasicBlock *nextMBB = new MachineBasicBlock(LLVM_BB); > + F->getBasicBlockList().insert(MBBIter, newMBB); > + F->getBasicBlockList().insert(MBBIter, nextMBB); > + > + // Move all successors to thisMBB to nextMBB > + nextMBB->transferSuccessors(thisMBB); > + > + // Update thisMBB to fall through to newMBB > + thisMBB->addSuccessor(newMBB); > + > + // newMBB jumps to itself and fall through to nextMBB > + newMBB->addSuccessor(nextMBB); > + newMBB->addSuccessor(newMBB); > + > + // Insert instructions into newMBB based on incoming instruction > + assert(bInstr->getNumOperands() < 8 && "unexpected number of operands"); > + MachineOperand& destOper = bInstr->getOperand(0); > + MachineOperand* argOpers[6]; > + int numArgs = bInstr->getNumOperands() - 1; > + for (int i=0; i < numArgs; ++i) > + argOpers[i] = &bInstr->getOperand(i+1); > + > + // x86 address has 4 operands: base, index, scale, and displacement > + int lastAddrIndx = 3; // [0,3] > + int valArgIndx = 4; > + > + MachineInstrBuilder MIB = BuildMI(newMBB, TII->get(X86::MOV32rm), X86::EAX); > + for (int i=0; i <= lastAddrIndx; ++i) > + (*MIB).addOperand(*argOpers[i]); > + > + unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); > + MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), t1); > + MIB.addReg(X86::EAX); > + > + unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); > + assert( (argOpers[valArgIndx]->isReg() || argOpers[valArgIndx]->isImm()) > + && "invalid operand"); > + if (argOpers[valArgIndx]->isReg()) > + MIB = BuildMI(newMBB, TII->get(regOpc), t2); > + else > + MIB = BuildMI(newMBB, TII->get(immOpc), t2); > + MIB.addReg(t1); > + (*MIB).addOperand(*argOpers[valArgIndx]); > + > + MIB = BuildMI(newMBB, TII->get(X86::LCMPXCHG32)); > + for (int i=0; i <= lastAddrIndx; ++i) > + (*MIB).addOperand(*argOpers[i]); > + MIB.addReg(t2); > + > + MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), destOper.getReg()); > + MIB.addReg(X86::EAX); > + > + // insert branch > + BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB); > + > + delete bInstr; // The pseudo instruction is gone now. > + return nextMBB; > +} > + > +// private utility function > +MachineBasicBlock * > +X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr, > + MachineBasicBlock *MBB, > + unsigned cmovOpc) { > + // For the atomic min/max operator, we generate > + // thisMBB: > + // newMBB: > + // ld EAX = [min/max.addr] > + // mov t1 = EAX > + // mov t2 = [min/max.val] > + // cmp t1, t2 > + // cmov[cond] t2 = t1 > + // lcs dest = [bitinstr.addr], t2 [EAX is implicit] > + // bz newMBB > + // fallthrough -->nextMBB > + // > + const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); > + const BasicBlock *LLVM_BB = MBB->getBasicBlock(); > + ilist::iterator MBBIter = MBB; > + ++MBBIter; > + > + /// First build the CFG > + MachineFunction *F = MBB->getParent(); > + MachineBasicBlock *thisMBB = MBB; > + MachineBasicBlock *newMBB = new MachineBasicBlock(LLVM_BB); > + MachineBasicBlock *nextMBB = new MachineBasicBlock(LLVM_BB); > + F->getBasicBlockList().insert(MBBIter, newMBB); > + F->getBasicBlockList().insert(MBBIter, nextMBB); > + > + // Move all successors to thisMBB to nextMBB > + nextMBB->transferSuccessors(thisMBB); > + > + // Update thisMBB to fall through to newMBB > + thisMBB->addSuccessor(newMBB); > + > + // newMBB jumps to newMBB and fall through to nextMBB > + newMBB->addSuccessor(nextMBB); > + newMBB->addSuccessor(newMBB); > + > + // Insert instructions into newMBB based on incoming instruction > + assert(mInstr->getNumOperands() < 8 && "unexpected number of operands"); > + MachineOperand& destOper = mInstr->getOperand(0); > + MachineOperand* argOpers[6]; > + int numArgs = mInstr->getNumOperands() - 1; > + for (int i=0; i < numArgs; ++i) > + argOpers[i] = &mInstr->getOperand(i+1); > + > + // x86 address has 4 operands: base, index, scale, and displacement > + int lastAddrIndx = 3; // [0,3] > + int valArgIndx = 4; > + > + MachineInstrBuilder MIB = BuildMI(newMBB, TII->get(X86::MOV32rm), X86::EAX); > + for (int i=0; i <= lastAddrIndx; ++i) > + (*MIB).addOperand(*argOpers[i]); > + > + unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); > + MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), t1); > + MIB.addReg(X86::EAX); > + > + // We only support register and immediate values > + assert( (argOpers[valArgIndx]->isReg() || argOpers[valArgIndx]->isImm()) > + && "invalid operand"); > + > + unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); > + if (argOpers[valArgIndx]->isReg()) > + MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), t2); > + else > + MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), t2); > + (*MIB).addOperand(*argOpers[valArgIndx]); > + > + MIB = BuildMI(newMBB, TII->get(X86::CMP32rr)); > + MIB.addReg(t1); > + MIB.addReg(t2); > + > + // Generate movc > + unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); > + MIB = BuildMI(newMBB, TII->get(cmovOpc),t3); > + MIB.addReg(t2); > + MIB.addReg(t1); > + > + // Cmp and exchange if none has modified the memory location > + MIB = BuildMI(newMBB, TII->get(X86::LCMPXCHG32)); > + for (int i=0; i <= lastAddrIndx; ++i) > + (*MIB).addOperand(*argOpers[i]); > + MIB.addReg(t3); > + > + MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), destOper.getReg()); > + MIB.addReg(X86::EAX); > + > + // insert branch > + BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB); > + > + delete mInstr; // The pseudo instruction is gone now. > + return nextMBB; > +} > + > + > MachineBasicBlock * > X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, > MachineBasicBlock *BB) { > @@ -5766,15 +5959,11 @@ > MachineFunction *F = BB->getParent(); > F->getBasicBlockList().insert(It, copy0MBB); > F->getBasicBlockList().insert(It, sinkMBB); > - // Update machine-CFG edges by first adding all successors of the current > + // Update machine-CFG edges by transferring all successors of the current > // block to the new block which will contain the Phi node for the select. > - for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), > - e = BB->succ_end(); i != e; ++i) > - sinkMBB->addSuccessor(*i); > - // Next, remove all successors of the current block, and add the true > - // and fallthrough blocks as its successors. > - while(!BB->succ_empty()) > - BB->removeSuccessor(BB->succ_begin()); > + sinkMBB->transferSuccessors(BB); > + > + // Add the true and fallthrough blocks as its successors. > BB->addSuccessor(copy0MBB); > BB->addSuccessor(sinkMBB); > > @@ -5874,6 +6063,23 @@ > delete MI; // The pseudo instruction is gone now. > return BB; > } > + case X86::ATOMAND32: > + return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, > + X86::AND32ri); > + case X86::ATOMOR32: > + return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr, > + X86::OR32ri); > + case X86::ATOMXOR32: > + return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr, > + X86::XOR32ri); > + case X86::ATOMMIN32: > + return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr); > + case X86::ATOMMAX32: > + return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr); > + case X86::ATOMUMIN32: > + return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr); > + case X86::ATOMUMAX32: > + return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr); > } > } > > > Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=50663&r1=50662&r2=50663&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original) > +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Mon May 5 14:05:59 2008 > @@ -346,6 +346,7 @@ > virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, > MachineBasicBlock *MBB); > > + > /// getTargetNodeName - This method returns the name of a target specific > /// DAG node. > virtual const char *getTargetNodeName(unsigned Opcode) const; > @@ -524,7 +525,8 @@ > SDNode *ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG); > SDNode *ExpandREADCYCLECOUNTER(SDNode *N, SelectionDAG &DAG); > SDNode *ExpandATOMIC_LCS(SDNode *N, SelectionDAG &DAG); > - > + SDNode *ExpandATOMIC_LSS(SDNode *N, SelectionDAG &DAG); > + > SDOperand EmitTargetCodeForMemset(SelectionDAG &DAG, > SDOperand Chain, > SDOperand Dst, SDOperand Src, > @@ -537,6 +539,23 @@ > bool AlwaysInline, > const Value *DstSV, uint64_t DstSVOff, > const Value *SrcSV, uint64_t SrcSVOff); > + > + /// Utility function to emit atomic bitwise operations (and, or, xor). > + // It takes the bitwise instruction to expand, the associated machine basic > + // block, and the associated X86 opcodes for reg/reg and reg/imm. > + MachineBasicBlock *EmitAtomicBitwiseWithCustomInserter( > + MachineInstr *BInstr, > + MachineBasicBlock *BB, > + unsigned regOpc, > + unsigned immOpc); > + > + /// Utility function to emit atomic min and max. It takes the min/max > + // instruction to expand, the associated basic block, and the associated > + // cmov opcode for moving the min or max value. > + MachineBasicBlock *EmitAtomicMinMaxWithCustomInserter(MachineInstr *BInstr, > + MachineBasicBlock *BB, > + unsigned cmovOpc); > + > }; > } > > > Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=50663&r1=50662&r2=50663&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) > +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Mon May 5 14:05:59 2008 > @@ -2598,6 +2598,63 @@ > TB, LOCK; > } > > +// Atomic exchange and and, or, xor > +let Constraints = "$val = $dst", Defs = [EFLAGS], > + usesCustomDAGSchedInserter = 1 in { > +def ATOMAND32 : I<0xC1, MRMSrcMem,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), > + "#ATOMAND32 PSUEDO!", > + [(set GR32:$dst, (atomic_load_and addr:$ptr, GR32:$val))]>, > + TB, LOCK; > +} > + > +let Constraints = "$val = $dst", Defs = [EFLAGS], > + usesCustomDAGSchedInserter = 1 in { > +def ATOMOR32 : I<0xC1, MRMSrcMem, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), > + "#ATOMOR32 PSUEDO!", > + [(set GR32:$dst, (atomic_load_or addr:$ptr, GR32:$val))]>, > + TB, LOCK; > +} > + > +let Constraints = "$val = $dst", Defs = [EFLAGS], > + usesCustomDAGSchedInserter = 1 in { > +def ATOMXOR32 : I<0xC1, MRMSrcMem,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), > + "#ATOMXOR32 PSUEDO!", > + [(set GR32:$dst, (atomic_load_xor addr:$ptr, GR32:$val))]>, > + TB, LOCK; > +} > + > +let Constraints = "$val = $dst", Defs = [EFLAGS], > + usesCustomDAGSchedInserter = 1 in { > +def ATOMMIN32: I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val), > + "#ATOMMIN32 PSUEDO!", > + [(set GR32:$dst, (atomic_load_min addr:$ptr, GR32:$val))]>, > + TB, LOCK; > +} > + > +let Constraints = "$val = $dst", Defs = [EFLAGS], > + usesCustomDAGSchedInserter = 1 in { > +def ATOMMAX32: I<0xC1, MRMSrcMem, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), > + "#ATOMMAX32 PSUEDO!", > + [(set GR32:$dst, (atomic_load_max addr:$ptr, GR32:$val))]>, > + TB, LOCK; > +} > + > +let Constraints = "$val = $dst", Defs = [EFLAGS], > + usesCustomDAGSchedInserter = 1 in { > +def ATOMUMIN32: I<0xC1, MRMSrcMem,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), > + "#ATOMUMIN32 PSUEDO!", > + [(set GR32:$dst, (atomic_load_umin addr:$ptr, GR32:$val))]>, > + TB, LOCK; > +} > + > +let Constraints = "$val = $dst", Defs = [EFLAGS], > + usesCustomDAGSchedInserter = 1 in { > +def ATOMUMAX32: I<0xC1, MRMSrcMem,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val), > + "#ATOMUMAX32 PSUEDO!", > + [(set GR32:$dst, (atomic_load_umax addr:$ptr, GR32:$val))]>, > + TB, LOCK; > +} > + > //===----------------------------------------------------------------------===// > // Non-Instruction Patterns > //===----------------------------------------------------------------------===// > > Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=50663&r1=50662&r2=50663&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original) > +++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Mon May 5 14:05:59 2008 > @@ -247,7 +247,7 @@ > , MaxInlineSizeThreshold(128) > , Is64Bit(is64Bit) > , TargetType(isELF) { // Default to ELF unless otherwise specified. > - > + > // Determine default and user specified characteristics > if (!FS.empty()) { > // If feature string is not empty, parse features string. > > Added: llvm/trunk/test/CodeGen/X86/atomic_op.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/atomic_op.ll?rev=50663&view=auto > > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/atomic_op.ll (added) > +++ llvm/trunk/test/CodeGen/X86/atomic_op.ll Mon May 5 14:05:59 2008 > @@ -0,0 +1,93 @@ > +; RUN: llvm-as < %s | llc -march=x86 -o %t1 -f > +; RUN: grep "lock xaddl" %t1 | count 4 > +; RUN: grep "lock cmpxchgl" %t1 | count 13 > +; RUN: grep "xchgl" %t1 | count 14 > +; RUN: grep "cmova" %t1 | count 2 > +; RUN: grep "cmovb" %t1 | count 2 > +; RUN: grep "cmovg" %t1 | count 2 > +; RUN: grep "cmovl" %t1 | count 2 > + > +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" > + > +define void @main(i32 %argc, i8** %argv) { > +entry: > + %argc.addr = alloca i32 ; [#uses=1] > + %argv.addr = alloca i8** ; [#uses=1] > + %val1 = alloca i32 ; [#uses=2] > + %val2 = alloca i32 ; [#uses=15] > + %andt = alloca i32 ; [#uses=2] > + %ort = alloca i32 ; [#uses=2] > + %xort = alloca i32 ; [#uses=2] > + %old = alloca i32 ; [#uses=18] > + %temp = alloca i32 ; [#uses=2] > + store i32 %argc, i32* %argc.addr > + store i8** %argv, i8*** %argv.addr > + store i32 0, i32* %val1 > + store i32 31, i32* %val2 > + store i32 3855, i32* %andt > + store i32 3855, i32* %ort > + store i32 3855, i32* %xort > + store i32 4, i32* %temp > + %tmp = load i32* %temp ; [#uses=1] > + call i32 @llvm.atomic.las.i32( i32* %val1, i32 %tmp ) ; :0 [#uses=1] > + store i32 %0, i32* %old > + call i32 @llvm.atomic.lss.i32( i32* %val2, i32 30 ) ; :1 [#uses=1] > + store i32 %1, i32* %old > + call i32 @llvm.atomic.las.i32( i32* %val2, i32 1 ) ; :2 [#uses=1] > + store i32 %2, i32* %old > + call i32 @llvm.atomic.lss.i32( i32* %val2, i32 1 ) ; :3 [#uses=1] > + store i32 %3, i32* %old > + call i32 @llvm.atomic.load.and.i32( i32* %andt, i32 4080 ) ; :4 [#uses=1] > + store i32 %4, i32* %old > + call i32 @llvm.atomic.load.or.i32( i32* %ort, i32 4080 ) ; :5 [#uses=1] > + store i32 %5, i32* %old > + call i32 @llvm.atomic.load.xor.i32( i32* %xort, i32 4080 ) ; :6 [#uses=1] > + store i32 %6, i32* %old > + call i32 @llvm.atomic.load.min.i32( i32* %val2, i32 16 ) ; :7 [#uses=1] > + store i32 %7, i32* %old > + %neg = sub i32 0, 1 ; [#uses=1] > + call i32 @llvm.atomic.load.min.i32( i32* %val2, i32 %neg ) ; :8 [#uses=1] > + store i32 %8, i32* %old > + call i32 @llvm.atomic.load.max.i32( i32* %val2, i32 1 ) ; :9 [#uses=1] > + store i32 %9, i32* %old > + call i32 @llvm.atomic.load.max.i32( i32* %val2, i32 0 ) ; :10 [#uses=1] > + store i32 %10, i32* %old > + call i32 @llvm.atomic.load.umax.i32( i32* %val2, i32 65535 ) ; :11 [#uses=1] > + store i32 %11, i32* %old > + call i32 @llvm.atomic.load.umax.i32( i32* %val2, i32 10 ) ; :12 [#uses=1] > + store i32 %12, i32* %old > + call i32 @llvm.atomic.load.umin.i32( i32* %val2, i32 1 ) ; :13 [#uses=1] > + store i32 %13, i32* %old > + call i32 @llvm.atomic.load.umin.i32( i32* %val2, i32 10 ) ; :14 [#uses=1] > + store i32 %14, i32* %old > + call i32 @llvm.atomic.swap.i32( i32* %val2, i32 1976 ) ; :15 [#uses=1] > + store i32 %15, i32* %old > + %neg1 = sub i32 0, 10 ; [#uses=1] > + call i32 @llvm.atomic.lcs.i32( i32* %val2, i32 %neg1, i32 1 ) ; :16 [#uses=1] > + store i32 %16, i32* %old > + call i32 @llvm.atomic.lcs.i32( i32* %val2, i32 1976, i32 1 ) ; :17 [#uses=1] > + store i32 %17, i32* %old > + ret void > +} > + > +declare i32 @llvm.atomic.las.i32(i32*, i32) nounwind > + > +declare i32 @llvm.atomic.lss.i32(i32*, i32) nounwind > + > +declare i32 @llvm.atomic.load.and.i32(i32*, i32) nounwind > + > +declare i32 @llvm.atomic.load.or.i32(i32*, i32) nounwind > + > +declare i32 @llvm.atomic.load.xor.i32(i32*, i32) nounwind > + > +declare i32 @llvm.atomic.load.min.i32(i32*, i32) nounwind > + > +declare i32 @llvm.atomic.load.max.i32(i32*, i32) nounwind > + > +declare i32 @llvm.atomic.load.umax.i32(i32*, i32) nounwind > + > +declare i32 @llvm.atomic.load.umin.i32(i32*, i32) nounwind > + > +declare i32 @llvm.atomic.swap.i32(i32*, i32) nounwind > + > +declare i32 @llvm.atomic.lcs.i32(i32*, i32, i32) nounwind > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From evan.cheng at apple.com Thu Jun 5 16:41:22 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 5 Jun 2008 14:41:22 -0700 Subject: [llvm-commits] [llvm] r52013 - /llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp In-Reply-To: <200806051722.m55HMrqr030871@zion.cs.uiuc.edu> References: <200806051722.m55HMrqr030871@zion.cs.uiuc.edu> Message-ID: <3EF7D1F1-EA85-4589-8285-FEA5F3E146D4@apple.com> Thanks Owen. Evan On Jun 5, 2008, at 10:22 AM, Owen Anderson wrote: > Author: resistor > Date: Thu Jun 5 12:22:53 2008 > New Revision: 52013 > > URL: http://llvm.org/viewvc/llvm-project?rev=52013&view=rev > Log: > Use the newly created helper on LiveIntervals. > > Modified: > llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp > > Modified: llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp?rev=52013&r1=52012&r2=52013&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp (original) > +++ llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp Thu Jun 5 > 12:22:53 2008 > @@ -52,8 +52,9 @@ > // used as operands to another another PHI node > std::set UsedByAnother; > > - // RenameSets are the sets of operands (and their VNInfo IDs) > to a PHI > - // (the defining instruction of the key) that can be renamed > without copies. > + // RenameSets are the is a map from a PHI-defined register > + // to the input registers to be coalesced along with the index > + // of the input registers. > std::map > RenameSets; > > // PhiValueNumber holds the ID numbers of the VNs for each phi > that we're > @@ -466,15 +467,11 @@ > UsedByAnother.insert(SrcReg); > } else { > // Otherwise, add it to the renaming set > - LiveInterval& I = LI.getOrCreateInterval(SrcReg); > // We need to subtract one from the index because live > ranges are open > // at the end. > unsigned idx = LI.getMBBEndIdx(P->getOperand(i).getMBB()) - 1; > - VNInfo* VN = I.getLiveRangeContaining(idx)->valno; > > - assert(VN && "No VNInfo for register?"); > - > - PHIUnion.insert(std::make_pair(SrcReg, VN->id)); > + PHIUnion.insert(std::make_pair(SrcReg, idx)); > UnionedBlocks.insert(MRI.getVRegDef(SrcReg)->getParent()); > } > } > @@ -744,22 +741,9 @@ > // PHI, we don't create multiple overlapping live intervals. > std::set RegHandled; > for (SmallVector, 4>::iterator > I = > - InsertedPHIDests.begin(), E = InsertedPHIDests.end(); I != > E; ++I) { > - if (!RegHandled.count(I->first)) { > - LiveInterval& Interval = LI.getOrCreateInterval(I->first); > - VNInfo* VN = Interval.getNextValue( > - LI.getInstructionIndex(I->second) + > LiveIntervals::InstrSlots::DEF, > - I->second, > LI.getVNInfoAllocator()); > - VN->hasPHIKill = true; > - VN->kills.push_back(LI.getMBBEndIdx(I->second->getParent())); > - LiveRange LR(LI.getInstructionIndex(I->second) + > - LiveIntervals::InstrSlots::DEF, > - LI.getMBBEndIdx(I->second->getParent()) + 1, VN); > - Interval.addRange(LR); > - > - RegHandled.insert(I->first); > - } > - } > + InsertedPHIDests.begin(), E = InsertedPHIDests.end(); I != > E; ++I) > + if (!RegHandled.count(I->first)) > + LI.addLiveRangeToEndOfBlock(I->first, I->second); > } > > /// InsertCopies - insert copies into MBB and all of its successors > @@ -794,111 +778,30 @@ > Stacks[*I].pop_back(); > } > > -/// ComputeUltimateVN - Assuming we are going to join two live > intervals, > -/// compute what the resultant value numbers for each value in the > input two > -/// ranges will be. This is complicated by copies between the two > which can > -/// and will commonly cause multiple value numbers to be merged > into one. > -/// > -/// VN is the value number that we're trying to resolve. > InstDefiningValue > -/// keeps track of the new InstDefiningValue assignment for the > result > -/// LiveInterval. ThisFromOther/OtherFromThis are sets that keep > track of > -/// whether a value in this or other is a copy from the opposite set. > -/// ThisValNoAssignments/OtherValNoAssignments keep track of value > #'s that have > -/// already been assigned. > -/// > -/// ThisFromOther[x] - If x is defined as a copy from the other > interval, this > -/// contains the value number the copy is from. > -/// > -static unsigned ComputeUltimateVN(VNInfo *VNI, > - SmallVector > &NewVNInfo, > - DenseMap > &ThisFromOther, > - DenseMap > &OtherFromThis, > - SmallVector > &ThisValNoAssignments, > - SmallVector > &OtherValNoAssignments) { > - unsigned VN = VNI->id; > - > - // If the VN has already been computed, just return it. > - if (ThisValNoAssignments[VN] >= 0) > - return ThisValNoAssignments[VN]; > -// assert(ThisValNoAssignments[VN] != -2 && "Cyclic case?"); > - > - // If this val is not a copy from the other val, then it must be > a new value > - // number in the destination. > - DenseMap::iterator I = ThisFromOther.find(VNI); > - if (I == ThisFromOther.end()) { > - NewVNInfo.push_back(VNI); > - return ThisValNoAssignments[VN] = NewVNInfo.size()-1; > - } > - VNInfo *OtherValNo = I->second; > - > - // Otherwise, this *is* a copy from the RHS. If the other side > has already > - // been computed, return it. > - if (OtherValNoAssignments[OtherValNo->id] >= 0) > - return ThisValNoAssignments[VN] = > OtherValNoAssignments[OtherValNo->id]; > - > - // Mark this value number as currently being computed, then ask > what the > - // ultimate value # of the other value is. > - ThisValNoAssignments[VN] = -2; > - unsigned UltimateVN = > - ComputeUltimateVN(OtherValNo, NewVNInfo, OtherFromThis, > ThisFromOther, > - OtherValNoAssignments, ThisValNoAssignments); > - return ThisValNoAssignments[VN] = UltimateVN; > -} > - > void StrongPHIElimination::mergeLiveIntervals(unsigned primary, > unsigned secondary, > - unsigned secondaryVN) { > + unsigned > secondaryIdx) { > > LiveIntervals& LI = getAnalysis(); > LiveInterval& LHS = LI.getOrCreateInterval(primary); > LiveInterval& RHS = LI.getOrCreateInterval(secondary); > > - // Compute the final value assignment, assuming that the live > ranges can be > - // coalesced. > - SmallVector LHSValNoAssignments; > - SmallVector RHSValNoAssignments; > - SmallVector NewVNInfo; > - > - LHSValNoAssignments.resize(LHS.getNumValNums(), -1); > - RHSValNoAssignments.resize(RHS.getNumValNums(), -1); > - NewVNInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums()); > - > - for (LiveInterval::vni_iterator I = LHS.vni_begin(), E = > LHS.vni_end(); > - I != E; ++I) { > - VNInfo *VNI = *I; > - unsigned VN = VNI->id; > - if (LHSValNoAssignments[VN] >= 0 || VNI->def == ~1U) > - continue; > - > - NewVNInfo.push_back(VNI); > - LHSValNoAssignments[VN] = NewVNInfo.size()-1; > - } > - > - for (LiveInterval::vni_iterator I = RHS.vni_begin(), E = > RHS.vni_end(); > - I != E; ++I) { > - VNInfo *VNI = *I; > - unsigned VN = VNI->id; > - if (RHSValNoAssignments[VN] >= 0 || VNI->def == ~1U) > - continue; > - > - NewVNInfo.push_back(VNI); > - RHSValNoAssignments[VN] = NewVNInfo.size()-1; > - } > - > - // If we get here, we know that we can coalesce the live ranges. > Ask the > - // intervals to coalesce themselves now. > - > - LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], > NewVNInfo); > - LI.removeInterval(secondary); > + LI.computeNumbering(); > > - // The valno that was previously the input to the PHI node > - // now has a PHIKill. > - LHS.getValNumInfo(RHSValNoAssignments[secondaryVN])->hasPHIKill = > true; > + const LiveRange* RangeMergingIn = > RHS.getLiveRangeContaining(secondaryIdx); > + VNInfo* NewVN = LHS.getNextValue(secondaryIdx, RangeMergingIn- > >valno->copy, > + LI.getVNInfoAllocator()); > + NewVN->hasPHIKill = true; > + LiveRange NewRange(RangeMergingIn->start, RangeMergingIn->end, > NewVN); > + LHS.addRange(NewRange); > + RHS.removeRange(RangeMergingIn->start, RangeMergingIn->end, true); > } > > bool StrongPHIElimination::runOnMachineFunction(MachineFunction &Fn) { > LiveIntervals& LI = getAnalysis(); > > + LI.dump(); > + > // Compute DFS numbers of each block > computeDFS(Fn); > > @@ -909,7 +812,7 @@ > processBlock(I); > > // Insert copies > - // FIXME: This process should probably preserve LiveVariables > + // FIXME: This process should probably preserve LiveIntervals > SmallPtrSet visited; > InsertCopies(Fn.begin(), visited); > > @@ -961,5 +864,7 @@ > > LI.computeNumbering(); > > + LI.dump(); > + > return true; > } > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From dpatel at apple.com Thu Jun 5 16:44:00 2008 From: dpatel at apple.com (Devang Patel) Date: Thu, 05 Jun 2008 21:44:00 -0000 Subject: [llvm-commits] [llvm] r52021 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <200806052144.m55Li0oC008322@zion.cs.uiuc.edu> Author: dpatel Date: Thu Jun 5 16:44:00 2008 New Revision: 52021 URL: http://llvm.org/viewvc/llvm-project?rev=52021&view=rev Log: Describe loop index split. Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=52021&r1=52020&r2=52021&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Thu Jun 5 16:44:00 2008 @@ -219,7 +219,21 @@
              -
            • Loop index set splitting on by default: describe me.
              • +
            • Loop index set splitting on by default.

              +This transformation hoists conditions from loop bodies and reduces loop's +iteration space to improve performance. For example,

              +

              +for (i = LB; i < UB; ++i)
+  if (i <= NV)
+    LOOP_BODY
+
              +is transformed into +
              +NUB = min(NV+1, UB)
+for (i = LB; i < NUB; ++i)
+  LOOP_BODY
+
              +
            • LLVM includes a new memcpy optimization pass which optimizes out dead memcpy calls, unneeded copies of aggregates, and handles the return slot optimization. The LLVM optimizer now notices long sequences of consequtive From scottm at aero.org Thu Jun 5 17:23:24 2008 From: scottm at aero.org (Scott Michel) Date: Thu, 05 Jun 2008 22:23:24 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r52022 - /llvm-gcc-4.2/trunk/gcc/ddg.c Message-ID: <200806052223.m55MNOr8010887@zion.cs.uiuc.edu> Author: pingbak Date: Thu Jun 5 17:23:24 2008 New Revision: 52022 URL: http://llvm.org/viewvc/llvm-project?rev=52022&view=rev Log: Fix typo Modified: llvm-gcc-4.2/trunk/gcc/ddg.c Modified: llvm-gcc-4.2/trunk/gcc/ddg.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/ddg.c?rev=52022&r1=52021&r2=52022&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/ddg.c (original) +++ llvm-gcc-4.2/trunk/gcc/ddg.c Thu Jun 5 17:23:24 2008 @@ -51,7 +51,7 @@ #undef INSN_SCHEDULING #endif -#ifdef ISNS_SCHEDULING +#ifdef INSN_SCHEDULING /* LLVM LOCAL end */ /* A flag indicating that a ddg edge belongs to an SCC or not. */ enum edge_flag {NOT_IN_SCC = 0, IN_SCC}; From evan.cheng at apple.com Thu Jun 5 17:59:21 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 05 Jun 2008 22:59:21 -0000 Subject: [llvm-commits] [llvm] r52026 - /llvm/trunk/lib/Target/X86/X86JITInfo.cpp Message-ID: <200806052259.m55MxLQY013189@zion.cs.uiuc.edu> Author: evancheng Date: Thu Jun 5 17:59:21 2008 New Revision: 52026 URL: http://llvm.org/viewvc/llvm-project?rev=52026&view=rev Log: Don't break strict aliasing. Modified: llvm/trunk/lib/Target/X86/X86JITInfo.cpp Modified: llvm/trunk/lib/Target/X86/X86JITInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86JITInfo.cpp?rev=52026&r1=52025&r2=52026&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86JITInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86JITInfo.cpp Thu Jun 5 17:59:21 2008 @@ -396,8 +396,8 @@ MachineCodeEmitter &MCE) { #if defined (X86_64_JIT) MCE.startFunctionStub(GV, 8, 8); - MCE.emitWordLE(((unsigned *)&ptr)[0]); - MCE.emitWordLE(((unsigned *)&ptr)[1]); + MCE.emitWordLE((unsigned)(intptr_t)ptr); + MCE.emitWordLE((unsigned)(((intptr_t)ptr) >> 32)); #else MCE.startFunctionStub(GV, 4, 4); MCE.emitWordLE((intptr_t)ptr); @@ -420,8 +420,8 @@ MCE.startFunctionStub(F, 13, 4); MCE.emitByte(0x49); // REX prefix MCE.emitByte(0xB8+2); // movabsq r10 - MCE.emitWordLE(((unsigned *)&Fn)[0]); - MCE.emitWordLE(((unsigned *)&Fn)[1]); + MCE.emitWordLE((unsigned)(intptr_t)Fn); + MCE.emitWordLE((unsigned)(((intptr_t)Fn) >> 32)); MCE.emitByte(0x41); // REX prefix MCE.emitByte(0xFF); // jmpq *r10 MCE.emitByte(2 | (4 << 3) | (3 << 6)); @@ -437,8 +437,8 @@ MCE.startFunctionStub(F, 14, 4); MCE.emitByte(0x49); // REX prefix MCE.emitByte(0xB8+2); // movabsq r10 - MCE.emitWordLE(((unsigned *)&Fn)[0]); - MCE.emitWordLE(((unsigned *)&Fn)[1]); + MCE.emitWordLE((unsigned)(intptr_t)Fn); + MCE.emitWordLE((unsigned)(((intptr_t)Fn) >> 32)); MCE.emitByte(0x41); // REX prefix MCE.emitByte(0xFF); // callq *r10 MCE.emitByte(2 | (2 << 3) | (3 << 6)); From evan.cheng at apple.com Thu Jun 5 18:00:08 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 05 Jun 2008 23:00:08 -0000 Subject: [llvm-commits] [llvm] r52027 - /llvm/trunk/Makefile.rules Message-ID: <200806052300.m55N08K0013243@zion.cs.uiuc.edu> Author: evancheng Date: Thu Jun 5 18:00:08 2008 New Revision: 52027 URL: http://llvm.org/viewvc/llvm-project?rev=52027&view=rev Log: Warn of potential violations of strict aliasing rules. Modified: llvm/trunk/Makefile.rules Modified: llvm/trunk/Makefile.rules URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=52027&r1=52026&r2=52027&view=diff ============================================================================== --- llvm/trunk/Makefile.rules (original) +++ llvm/trunk/Makefile.rules Thu Jun 5 18:00:08 2008 @@ -226,7 +226,7 @@ # Darwin requires -fstrict-aliasing to be explicitly enabled. ifeq ($(OS),Darwin) - EXTRA_OPTIONS += -fstrict-aliasing + EXTRA_OPTIONS += -fstrict-aliasing -Wstrict-aliasing endif CXX.Flags += $(OPTIMIZE_OPTION) $(OmitFramePointer) From sabre at nondot.org Thu Jun 5 18:38:34 2008 From: sabre at nondot.org (Chris Lattner) Date: Thu, 05 Jun 2008 23:38:34 -0000 Subject: [llvm-commits] [llvm] r52028 - /llvm/trunk/lib/Analysis/LibCallAliasAnalysis.cpp Message-ID: <200806052338.m55NcZWu015400@zion.cs.uiuc.edu> Author: lattner Date: Thu Jun 5 18:38:34 2008 New Revision: 52028 URL: http://llvm.org/viewvc/llvm-project?rev=52028&view=rev Log: Let libcall semantics decide whether it knows about functions with definitions or not. Modified: llvm/trunk/lib/Analysis/LibCallAliasAnalysis.cpp Modified: llvm/trunk/lib/Analysis/LibCallAliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/LibCallAliasAnalysis.cpp?rev=52028&r1=52027&r2=52028&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/LibCallAliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/LibCallAliasAnalysis.cpp Thu Jun 5 18:38:34 2008 @@ -155,8 +155,8 @@ // If this is a direct call to a function that LCI knows about, get the // information about the runtime function. - if (Function *F = CS.getCalledFunction()) { - if (LCI && F->isDeclaration()) { + if (LCI) { + if (Function *F = CS.getCalledFunction()) { if (const LibCallFunctionInfo *FI = LCI->getFunctionInfo(F)) { MRInfo = ModRefResult(MRInfo & AnalyzeLibCallDetails(FI, CS, P, Size)); if (MRInfo == NoModRef) return NoModRef; From sabre at nondot.org Thu Jun 5 18:45:18 2008 From: sabre at nondot.org (Chris Lattner) Date: Thu, 05 Jun 2008 23:45:18 -0000 Subject: [llvm-commits] [llvm] r52029 - in /llvm/trunk: include/llvm/Analysis/LibCallAliasAnalysis.h lib/Analysis/LibCallAliasAnalysis.cpp Message-ID: <200806052345.m55NjIUg015763@zion.cs.uiuc.edu> Author: lattner Date: Thu Jun 5 18:45:18 2008 New Revision: 52029 URL: http://llvm.org/viewvc/llvm-project?rev=52029&view=rev Log: Expose a public interface to this pass. Added: llvm/trunk/include/llvm/Analysis/LibCallAliasAnalysis.h Modified: llvm/trunk/lib/Analysis/LibCallAliasAnalysis.cpp Added: llvm/trunk/include/llvm/Analysis/LibCallAliasAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/LibCallAliasAnalysis.h?rev=52029&view=auto ============================================================================== --- llvm/trunk/include/llvm/Analysis/LibCallAliasAnalysis.h (added) +++ llvm/trunk/include/llvm/Analysis/LibCallAliasAnalysis.h Thu Jun 5 18:45:18 2008 @@ -0,0 +1,61 @@ +//===- LibCallAliasAnalysis.h - Implement AliasAnalysis for libcalls ------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the LibCallAliasAnalysis class. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_ANALYSIS_LIBCALL_AA_H +#define LLVM_ANALYSIS_LIBCALL_AA_H + +#include "llvm/Analysis/AliasAnalysis.h" +#include "llvm/Pass.h" + +namespace llvm { + class LibCallInfo; + class LibCallFunctionInfo; + + /// LibCallAliasAnalysis - Alias analysis driven from LibCallInfo. + struct LibCallAliasAnalysis : public FunctionPass, AliasAnalysis { + static char ID; // Class identification + + LibCallInfo *LCI; + + explicit LibCallAliasAnalysis(LibCallInfo *LC = 0) + : FunctionPass(&ID), LCI(LC) { + } + explicit LibCallAliasAnalysis(const void *ID, LibCallInfo *LC) + : FunctionPass(ID), LCI(LC) { + } + ~LibCallAliasAnalysis(); + + ModRefResult getModRefInfo(CallSite CS, Value *P, unsigned Size); + + ModRefResult getModRefInfo(CallSite CS1, CallSite CS2) { + // TODO: Could compare two direct calls against each other if we cared to. + return AliasAnalysis::getModRefInfo(CS1,CS2); + } + + virtual void getAnalysisUsage(AnalysisUsage &AU) const; + + virtual bool runOnFunction(Function &F) { + InitializeAliasAnalysis(this); // set up super class + return false; + } + + /// hasNoModRefInfoForCalls - We can provide mod/ref information against + /// non-escaping allocations. + virtual bool hasNoModRefInfoForCalls() const { return false; } + private: + ModRefResult AnalyzeLibCallDetails(const LibCallFunctionInfo *FI, + CallSite CS, Value *P, unsigned Size); + }; +} // End of llvm namespace + +#endif Modified: llvm/trunk/lib/Analysis/LibCallAliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/LibCallAliasAnalysis.cpp?rev=52029&r1=52028&r2=52029&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/LibCallAliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/LibCallAliasAnalysis.cpp Thu Jun 5 18:45:18 2008 @@ -11,52 +11,13 @@ // //===----------------------------------------------------------------------===// +#include "llvm/Analysis/LibCallAliasAnalysis.h" #include "llvm/Analysis/Passes.h" #include "llvm/Analysis/LibCallSemantics.h" #include "llvm/Function.h" #include "llvm/Pass.h" #include "llvm/Target/TargetData.h" using namespace llvm; - -namespace { - /// LibCallAliasAnalysis - Alias analysis driven from LibCallInfo. - struct LibCallAliasAnalysis : public FunctionPass, AliasAnalysis { - static char ID; // Class identification - - LibCallInfo *LCI; - - explicit LibCallAliasAnalysis(LibCallInfo *LC = 0) - : FunctionPass((intptr_t)&ID), LCI(LC) { - } - ~LibCallAliasAnalysis() { - delete LCI; - } - - ModRefResult getModRefInfo(CallSite CS, Value *P, unsigned Size); - ModRefResult getModRefInfo(CallSite CS1, CallSite CS2) { - // TODO: Could compare two direct calls against each other if we cared to. - return AliasAnalysis::getModRefInfo(CS1,CS2); - } - - virtual void getAnalysisUsage(AnalysisUsage &AU) const { - AliasAnalysis::getAnalysisUsage(AU); - AU.addRequired(); - AU.setPreservesAll(); // Does not transform code - } - - virtual bool runOnFunction(Function &F) { - InitializeAliasAnalysis(this); // set up super class - return false; - } - - /// hasNoModRefInfoForCalls - We can provide mod/ref information against - /// non-escaping allocations. - virtual bool hasNoModRefInfoForCalls() const { return false; } - private: - ModRefResult AnalyzeLibCallDetails(const LibCallFunctionInfo *FI, - CallSite CS, Value *P, unsigned Size); - }; -} // End of anonymous namespace // Register this pass... char LibCallAliasAnalysis::ID = 0; @@ -70,6 +31,17 @@ return new LibCallAliasAnalysis(LCI); } +LibCallAliasAnalysis::~LibCallAliasAnalysis() { + delete LCI; +} + +void LibCallAliasAnalysis::getAnalysisUsage(AnalysisUsage &AU) const { + AliasAnalysis::getAnalysisUsage(AU); + AU.addRequired(); + AU.setPreservesAll(); // Does not transform code +} + + /// AnalyzeLibCallDetails - Given a call to a function with the specified /// LibCallFunctionInfo, see if we can improve the mod/ref footprint of the call From gohman at apple.com Thu Jun 5 18:44:12 2008 From: gohman at apple.com (Dan Gohman) Date: Thu, 05 Jun 2008 16:44:12 -0700 Subject: [llvm-commits] [llvm] r52002 - in /llvm/trunk: lib/VMCore/Verifier.cpp test/Assembler/AggregrateReturn.ll In-Reply-To: <200806051400.m55E0aUM024060@zion.cs.uiuc.edu> References: <200806051400.m55E0aUM024060@zion.cs.uiuc.edu> Message-ID: <1212709452.20049.24.camel@dgohman1> Hi Matthijs, This conflicts with the existing multiple-return-value syntax, and along with it the llvm-gcc-4.2 build. I'm getting this error: Function return type does not match operand type of return inst! ret double %mrv { double }Broken module found, compilation aborted! while building _mulsc3.o. Here's a reduced testcase: ?define { i32 } @foo() { ret i32 0 } It's surprising that llvm-gcc is using { double } here instead of just plain double, and possibly a minor bug. I'm going to revert 52002 at least until the llvm-gcc issue is figured out. We'll probably also need to figure out an upgrade path for LLVM 2.3 multiple-return-value code. I haven't thought much about whether it's best to do a full transition all at once, or to support both aggregate returns and multiple-return-values at the same time for some time. Dan On Thu, 2008-06-05 at 14:00 +0000, Matthijs Kooijman wrote: > Author: matthijs > Date: Thu Jun 5 09:00:36 2008 > New Revision: 52002 > > URL: http://llvm.org/viewvc/llvm-project?rev=52002&view=rev > Log: > Change the Verifier to support returning first class aggregrates. > > Add a testcase for functions returning first class aggregrates. > > Added: > llvm/trunk/test/Assembler/AggregrateReturn.ll > Modified: > llvm/trunk/lib/VMCore/Verifier.cpp > > Modified: llvm/trunk/lib/VMCore/Verifier.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Verifier.cpp?rev=52002&r1=52001&r2=52002&view=diff > > ============================================================================== > --- llvm/trunk/lib/VMCore/Verifier.cpp (original) > +++ llvm/trunk/lib/VMCore/Verifier.cpp Thu Jun 5 09:00:36 2008 > @@ -594,7 +594,10 @@ > Assert2(N == 0, > "Found return instr that returns void in Function of non-void " > "return type!", &RI, F->getReturnType()); > - else if (const StructType *STy = dyn_cast(F->getReturnType())) { > + else if (N > 1) { > + const StructType *STy = dyn_cast(F->getReturnType()); > + Assert2(STy, "Return instr with multiple values, but return type is not " > + "a struct", &RI, F->getReturnType()); > Assert2(STy->getNumElements() == N, > "Incorrect number of return values in ret instruction!", > &RI, F->getReturnType()); > > Added: llvm/trunk/test/Assembler/AggregrateReturn.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Assembler/AggregrateReturn.ll?rev=52002&view=auto > > ============================================================================== > --- llvm/trunk/test/Assembler/AggregrateReturn.ll (added) > +++ llvm/trunk/test/Assembler/AggregrateReturn.ll Thu Jun 5 09:00:36 2008 > @@ -0,0 +1,22 @@ > +; RUN: llvm-as < %s | llvm-dis > + > +define { i32, i32 } @foo() { > + %res = insertvalue { i32, i32 } undef, i32 0, 0 > + %res2 = insertvalue { i32, i32 } %res, i32 1, 1 > + ret { i32, i32 } %res2 > +} > + > +define [ 2 x i32 ] @bar() { > + %res = insertvalue [ 2 x i32 ] undef, i32 0, 0 > + %res2 = insertvalue [ 2 x i32 ] %res, i32 1, 1 > + ret [ 2 x i32 ] %res2 > +} > + > +define i32 @main() { > + %a = call { i32, i32 }()* @foo () > + %b = call [ 2 x i32 ]()* @bar () > + %a.0 = extractvalue { i32, i32 } %a, 0 > + %b.1 = extractvalue [ 2 x i32 ] %b, 1 > + %r = add i32 %a.0, %b.1 > + ret i32 %r > +} > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From gohman at apple.com Thu Jun 5 18:57:06 2008 From: gohman at apple.com (Dan Gohman) Date: Thu, 05 Jun 2008 23:57:06 -0000 Subject: [llvm-commits] [llvm] r52030 - in /llvm/trunk: lib/VMCore/Verifier.cpp test/Assembler/AggregrateReturn.ll Message-ID: <200806052357.m55Nv6r8016391@zion.cs.uiuc.edu> Author: djg Date: Thu Jun 5 18:57:06 2008 New Revision: 52030 URL: http://llvm.org/viewvc/llvm-project?rev=52030&view=rev Log: Revert 52002. Removed: llvm/trunk/test/Assembler/AggregrateReturn.ll Modified: llvm/trunk/lib/VMCore/Verifier.cpp Modified: llvm/trunk/lib/VMCore/Verifier.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Verifier.cpp?rev=52030&r1=52029&r2=52030&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Verifier.cpp (original) +++ llvm/trunk/lib/VMCore/Verifier.cpp Thu Jun 5 18:57:06 2008 @@ -594,10 +594,7 @@ Assert2(N == 0, "Found return instr that returns void in Function of non-void " "return type!", &RI, F->getReturnType()); - else if (N > 1) { - const StructType *STy = dyn_cast(F->getReturnType()); - Assert2(STy, "Return instr with multiple values, but return type is not " - "a struct", &RI, F->getReturnType()); + else if (const StructType *STy = dyn_cast(F->getReturnType())) { Assert2(STy->getNumElements() == N, "Incorrect number of return values in ret instruction!", &RI, F->getReturnType()); Removed: llvm/trunk/test/Assembler/AggregrateReturn.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Assembler/AggregrateReturn.ll?rev=52029&view=auto ============================================================================== --- llvm/trunk/test/Assembler/AggregrateReturn.ll (original) +++ llvm/trunk/test/Assembler/AggregrateReturn.ll (removed) @@ -1,22 +0,0 @@ -; RUN: llvm-as < %s | llvm-dis - -define { i32, i32 } @foo() { - %res = insertvalue { i32, i32 } undef, i32 0, 0 - %res2 = insertvalue { i32, i32 } %res, i32 1, 1 - ret { i32, i32 } %res2 -} - -define [ 2 x i32 ] @bar() { - %res = insertvalue [ 2 x i32 ] undef, i32 0, 0 - %res2 = insertvalue [ 2 x i32 ] %res, i32 1, 1 - ret [ 2 x i32 ] %res2 -} - -define i32 @main() { - %a = call { i32, i32 }()* @foo () - %b = call [ 2 x i32 ]()* @bar () - %a.0 = extractvalue { i32, i32 } %a, 0 - %b.1 = extractvalue [ 2 x i32 ] %b, 1 - %r = add i32 %a.0, %b.1 - ret i32 %r -} From bruno.cardoso at gmail.com Thu Jun 5 19:58:27 2008 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Fri, 06 Jun 2008 00:58:27 -0000 Subject: [llvm-commits] [llvm] r52031 - in /llvm/trunk/lib/Target/Mips: MipsISelDAGToDAG.cpp MipsISelLowering.cpp MipsISelLowering.h MipsInstrFormats.td MipsInstrInfo.td Message-ID: <200806060058.m560wRgj019753@zion.cs.uiuc.edu> Author: bruno Date: Thu Jun 5 19:58:26 2008 New Revision: 52031 URL: http://llvm.org/viewvc/llvm-project?rev=52031&view=rev Log: Added custom SELECT_CC lowering Added special isel for ADDE,SUBE and new patterns to match SUBC,ADDC Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp llvm/trunk/lib/Target/Mips/MipsISelLowering.h llvm/trunk/lib/Target/Mips/MipsInstrFormats.td llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=52031&r1=52030&r2=52031&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Thu Jun 5 19:58:26 2008 @@ -226,6 +226,52 @@ default: break; + case ISD::ADDE: { + // ADDE is usally attached with a ADDC instruction, we must + // compare ADDC operands and set a register if we have a carry. + SDOperand InFlag = Node->getOperand(2); + unsigned Opc = InFlag.getOpcode(); + assert((Opc == ISD::ADDC || Opc == ISD::ADDE) && + "ADDE flag operand must come from a ADDC or ADDE"); + SDOperand Ops[] = { InFlag.getValue(0), InFlag.getOperand(1) }; + + SDOperand LHS = Node->getOperand(0); + SDOperand RHS = Node->getOperand(1); + AddToISelQueue(LHS); + AddToISelQueue(RHS); + + MVT::ValueType VT = LHS.getValueType(); + SDNode *Carry = CurDAG->getTargetNode(Mips::SLTu, VT, Ops, 2); + SDNode *AddCarry = CurDAG->getTargetNode(Mips::ADDu, VT, + SDOperand(Carry,0), RHS); + + return CurDAG->SelectNodeTo(N.Val, Mips::ADDu, VT, MVT::Flag, + LHS, SDOperand(AddCarry,0)); + } + + case ISD::SUBE: { + // SUBE is usally attached with a SUBC instruction, we must + // compare SUBC operands and set a register if we have a carry. + SDOperand InFlag = Node->getOperand(2); + unsigned Opc = InFlag.getOpcode(); + assert((Opc == ISD::SUBC || Opc == ISD::SUBE) && + "SUBE flag operand must come from a SUBC or SUBE"); + SDOperand Ops[] = { InFlag.getOperand(0), InFlag.getOperand(1) }; + + SDOperand LHS = Node->getOperand(0); + SDOperand RHS = Node->getOperand(1); + AddToISelQueue(LHS); + AddToISelQueue(RHS); + + MVT::ValueType VT = LHS.getValueType(); + SDNode *Carry = CurDAG->getTargetNode(Mips::SLTu, VT, Ops, 2); + SDNode *AddCarry = CurDAG->getTargetNode(Mips::ADDu, VT, + SDOperand(Carry,0), RHS); + + return CurDAG->SelectNodeTo(N.Val, Mips::SUBu, VT, MVT::Flag, + LHS, SDOperand(AddCarry,0)); + } + /// Special Mul operations case ISD::MULHS: case ISD::MULHU: { Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=52031&r1=52030&r2=52031&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Thu Jun 5 19:58:26 2008 @@ -39,11 +39,12 @@ { switch (Opcode) { - case MipsISD::JmpLink : return "MipsISD::JmpLink"; - case MipsISD::Hi : return "MipsISD::Hi"; - case MipsISD::Lo : return "MipsISD::Lo"; - case MipsISD::Ret : return "MipsISD::Ret"; - default : return NULL; + case MipsISD::JmpLink : return "MipsISD::JmpLink"; + case MipsISD::Hi : return "MipsISD::Hi"; + case MipsISD::Lo : return "MipsISD::Lo"; + case MipsISD::Ret : return "MipsISD::Ret"; + case MipsISD::SelectCC : return "MipsISD::SelectCC"; + default : return NULL; } } @@ -65,6 +66,7 @@ setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); setOperationAction(ISD::RET, MVT::Other, Custom); setOperationAction(ISD::JumpTable, MVT::i32, Custom); + setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); // Load extented operations for i1 types must be promoted setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote); @@ -75,7 +77,6 @@ setOperationAction(ISD::BR_JT, MVT::Other, Expand); setOperationAction(ISD::BR_CC, MVT::Other, Expand); setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); - setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); setOperationAction(ISD::SELECT, MVT::i32, Expand); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); @@ -124,10 +125,75 @@ case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); case ISD::JumpTable: return LowerJumpTable(Op, DAG); + case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); } return SDOperand(); } +MachineBasicBlock * +MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, + MachineBasicBlock *BB) +{ + const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); + switch (MI->getOpcode()) { + default: assert(false && "Unexpected instr type to insert"); + case Mips::Select_CC: { + // To "insert" a SELECT_CC instruction, we actually have to insert the + // diamond control-flow pattern. The incoming instruction knows the + // destination vreg to set, the condition code register to branch on, the + // true/false values to select between, and a branch opcode to use. + const BasicBlock *LLVM_BB = BB->getBasicBlock(); + ilist::iterator It = BB; + ++It; + + // thisMBB: + // ... + // TrueVal = ... + // setcc r1, r2, r3 + // bNE r1, r0, copy1MBB + // fallthrough --> copy0MBB + MachineBasicBlock *thisMBB = BB; + MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); + MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); + BuildMI(BB, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg()) + .addReg(Mips::ZERO).addMBB(sinkMBB); + MachineFunction *F = BB->getParent(); + F->getBasicBlockList().insert(It, copy0MBB); + F->getBasicBlockList().insert(It, sinkMBB); + // Update machine-CFG edges by first adding all successors of the current + // block to the new block which will contain the Phi node for the select. + for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), + e = BB->succ_end(); i != e; ++i) + sinkMBB->addSuccessor(*i); + // Next, remove all successors of the current block, and add the true + // and fallthrough blocks as its successors. + while(!BB->succ_empty()) + BB->removeSuccessor(BB->succ_begin()); + BB->addSuccessor(copy0MBB); + BB->addSuccessor(sinkMBB); + + // copy0MBB: + // %FalseValue = ... + // # fallthrough to sinkMBB + BB = copy0MBB; + + // Update machine-CFG edges + BB->addSuccessor(sinkMBB); + + // sinkMBB: + // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] + // ... + BB = sinkMBB; + BuildMI(BB, TII->get(Mips::PHI), MI->getOperand(0).getReg()) + .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) + .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB); + + delete MI; // The pseudo instruction is gone now. + return BB; + } + } +} + //===----------------------------------------------------------------------===// // Lower helper functions //===----------------------------------------------------------------------===// @@ -182,6 +248,23 @@ } SDOperand MipsTargetLowering:: +LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) +{ + SDOperand LHS = Op.getOperand(0); + SDOperand RHS = Op.getOperand(1); + SDOperand True = Op.getOperand(2); + SDOperand False = Op.getOperand(3); + SDOperand CC = Op.getOperand(4); + + const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::i32); + SDOperand Ops[] = { LHS, RHS, CC }; + SDOperand SetCCRes = DAG.getNode(ISD::SETCC, VTs, 1, Ops, 3); + + return DAG.getNode(MipsISD::SelectCC, True.getValueType(), + SetCCRes, True, False); +} + +SDOperand MipsTargetLowering:: LowerJumpTable(SDOperand Op, SelectionDAG &DAG) { SDOperand ResNode; Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.h?rev=52031&r1=52030&r2=52031&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.h (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.h Thu Jun 5 19:58:26 2008 @@ -37,6 +37,9 @@ // No relation with Mips Lo register Lo, + // Select CC Pseudo Instruction + SelectCC, + // Return Ret }; @@ -80,6 +83,10 @@ SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG); SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG); SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG); + SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG); + + virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, + MachineBasicBlock *MBB); // Inline asm support ConstraintType getConstraintType(const std::string &Constraint) const; Modified: llvm/trunk/lib/Target/Mips/MipsInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFormats.td?rev=52031&r1=52030&r2=52031&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrFormats.td (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrFormats.td Thu Jun 5 19:58:26 2008 @@ -43,7 +43,7 @@ } // Mips Pseudo Instructions Format -class PseudoInstMips pattern>: +class MipsPseudo pattern>: MipsInst; //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=52031&r1=52030&r2=52031&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Thu Jun 5 19:58:26 2008 @@ -43,6 +43,11 @@ def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd, [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; +// Select CC +def SDT_MipsSelectCC : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, + SDTCisSameAs<1, 2>, SDTCisInt<3>]>; +def MipsSelectCC : SDNode<"MipsISD::SelectCC", SDT_MipsSelectCC>; + //===----------------------------------------------------------------------===// // Mips Instruction Predicate Definitions. //===----------------------------------------------------------------------===// @@ -346,10 +351,10 @@ // As stack alignment is always done with addiu, we need a 16-bit immediate let Defs = [SP], Uses = [SP] in { -def ADJCALLSTACKDOWN : PseudoInstMips<(outs), (ins uimm16:$amt), +def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins uimm16:$amt), "!ADJCALLSTACKDOWN $amt", [(callseq_start imm:$amt)]>; -def ADJCALLSTACKUP : PseudoInstMips<(outs), (ins uimm16:$amt1, uimm16:$amt2), +def ADJCALLSTACKUP : MipsPseudo<(outs), (ins uimm16:$amt1, uimm16:$amt2), "!ADJCALLSTACKUP $amt1", [(callseq_end imm:$amt1, imm:$amt2)]>; } @@ -358,10 +363,22 @@ // directives. If the real instructions corresponding these directives // are used, we have the same behavior, but get also a bunch of warnings // from the assembler. -def CPLOAD: PseudoInstMips<(outs), (ins CPURegs:$reg), - ".set noreorder\n\t.cpload $reg\n\t.set reorder\n", []>; -def CPRESTORE: PseudoInstMips<(outs), (ins uimm16:$loc), - ".cprestore $loc\n", []>; +def CPLOAD : MipsPseudo<(outs), (ins CPURegs:$reg), + ".set noreorder\n\t.cpload $reg\n\t.set reorder\n", + []>; +def CPRESTORE : MipsPseudo<(outs), (ins uimm16:$loc), + ".cprestore $loc\n", []>; + +// The supported Mips ISAs dont have any instruction close to the SELECT_CC +// operation. The solution is to create a Mips pseudo SELECT_CC instruction +// (MipsSelectCC), use LowerSELECT_CC to generate this instruction and finally +// replace it for real supported nodes into EmitInstrWithCustomInserter +let usesCustomDAGSchedInserter = 1 in { + def Select_CC : MipsPseudo<(outs CPURegs:$dst), + (ins CPURegs:$CmpRes, CPURegs:$T, CPURegs:$F), "# MipsSelect_CC", + [(set CPURegs:$dst, (MipsSelectCC CPURegs:$CmpRes, + CPURegs:$T, CPURegs:$F))]>; +} //===----------------------------------------------------------------------===// // Instruction definition @@ -502,6 +519,14 @@ def : Pat<(i32 imm:$imm), (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>; +// Carry patterns +def : Pat<(subc CPURegs:$lhs, CPURegs:$rhs), + (SUBu CPURegs:$lhs, CPURegs:$rhs)>; +def : Pat<(addc CPURegs:$lhs, CPURegs:$rhs), + (ADDu CPURegs:$lhs, CPURegs:$rhs)>; +def : Pat<(addc CPURegs:$src, imm:$imm), + (ADDiu CPURegs:$src, imm:$imm)>; + // Call def : Pat<(MipsJmpLink (i32 tglobaladdr:$dst)), (JAL tglobaladdr:$dst)>; @@ -529,7 +554,7 @@ def : Pat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; def : Pat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>; -// some peepholes +// peepholes def : Pat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; /// From bruno.cardoso at gmail.com Fri Jun 6 01:37:32 2008 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Fri, 06 Jun 2008 06:37:32 -0000 Subject: [llvm-commits] [llvm] r52036 - in /llvm/trunk/lib/Target/Mips: MipsISelDAGToDAG.cpp MipsInstrInfo.td Message-ID: <200806060637.m566bX5e005564@zion.cs.uiuc.edu> Author: bruno Date: Fri Jun 6 01:37:31 2008 New Revision: 52036 URL: http://llvm.org/viewvc/llvm-project?rev=52036&view=rev Log: Added custom isel for MUL, SDIVREM, UDIVREM, SMUL_LOHI and UMUL_LOHI nodes MUL is not anymore directly matched because its a pseudoinstruction. LogicI class fixed to zero-extend immediates. Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=52036&r1=52035&r2=52036&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Fri Jun 6 01:37:31 2008 @@ -226,14 +226,24 @@ default: break; + case ISD::SUBE: case ISD::ADDE: { - // ADDE is usally attached with a ADDC instruction, we must - // compare ADDC operands and set a register if we have a carry. - SDOperand InFlag = Node->getOperand(2); - unsigned Opc = InFlag.getOpcode(); - assert((Opc == ISD::ADDC || Opc == ISD::ADDE) && - "ADDE flag operand must come from a ADDC or ADDE"); - SDOperand Ops[] = { InFlag.getValue(0), InFlag.getOperand(1) }; + SDOperand InFlag = Node->getOperand(2), CmpLHS; + unsigned Opc = InFlag.getOpcode(), MOp; + + assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) || + (Opc == ISD::SUBC || Opc == ISD::SUBE)) && + "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn"); + + if (Opcode == ISD::ADDE) { + CmpLHS = InFlag.getValue(0); + MOp = Mips::ADDu; + } else { + CmpLHS = InFlag.getOperand(0); + MOp = Mips::SUBu; + } + + SDOperand Ops[] = { CmpLHS, InFlag.getOperand(1) }; SDOperand LHS = Node->getOperand(0); SDOperand RHS = Node->getOperand(1); @@ -245,34 +255,45 @@ SDNode *AddCarry = CurDAG->getTargetNode(Mips::ADDu, VT, SDOperand(Carry,0), RHS); - return CurDAG->SelectNodeTo(N.Val, Mips::ADDu, VT, MVT::Flag, + return CurDAG->SelectNodeTo(N.Val, MOp, VT, MVT::Flag, LHS, SDOperand(AddCarry,0)); } - case ISD::SUBE: { - // SUBE is usally attached with a SUBC instruction, we must - // compare SUBC operands and set a register if we have a carry. - SDOperand InFlag = Node->getOperand(2); - unsigned Opc = InFlag.getOpcode(); - assert((Opc == ISD::SUBC || Opc == ISD::SUBE) && - "SUBE flag operand must come from a SUBC or SUBE"); - SDOperand Ops[] = { InFlag.getOperand(0), InFlag.getOperand(1) }; + /// Mul/Div with two results + case ISD::SDIVREM: + case ISD::UDIVREM: + case ISD::SMUL_LOHI: + case ISD::UMUL_LOHI: { + SDOperand Op1 = Node->getOperand(0); + SDOperand Op2 = Node->getOperand(1); + AddToISelQueue(Op1); + AddToISelQueue(Op2); + + unsigned Op; + if (Opcode == ISD::UMUL_LOHI || Opcode == ISD::SMUL_LOHI) + Op = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT); + else + Op = (Opcode == ISD::UDIVREM ? Mips::DIVu : Mips::DIV); + + SDNode *Node = CurDAG->getTargetNode(Op, MVT::Flag, Op1, Op2); + + SDOperand InFlag = SDOperand(Node, 0); + SDNode *Lo = CurDAG->getTargetNode(Mips::MFLO, MVT::i32, MVT::Flag, InFlag); - SDOperand LHS = Node->getOperand(0); - SDOperand RHS = Node->getOperand(1); - AddToISelQueue(LHS); - AddToISelQueue(RHS); + InFlag = SDOperand(Lo,1); + SDNode *Hi = CurDAG->getTargetNode(Mips::MFHI, MVT::i32, InFlag); - MVT::ValueType VT = LHS.getValueType(); - SDNode *Carry = CurDAG->getTargetNode(Mips::SLTu, VT, Ops, 2); - SDNode *AddCarry = CurDAG->getTargetNode(Mips::ADDu, VT, - SDOperand(Carry,0), RHS); + if (!N.getValue(0).use_empty()) + ReplaceUses(N.getValue(0), SDOperand(Lo,0)); - return CurDAG->SelectNodeTo(N.Val, Mips::SUBu, VT, MVT::Flag, - LHS, SDOperand(AddCarry,0)); + if (!N.getValue(1).use_empty()) + ReplaceUses(N.getValue(1), SDOperand(Hi,0)); + + return NULL; } - /// Special Mul operations + /// Special Muls + case ISD::MUL: case ISD::MULHS: case ISD::MULHU: { SDOperand MulOp1 = Node->getOperand(0); @@ -283,38 +304,36 @@ unsigned MulOp = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT); SDNode *MulNode = CurDAG->getTargetNode(MulOp, MVT::Flag, MulOp1, MulOp2); - SDOperand MFInFlag = SDOperand(MulNode, 0); - return CurDAG->getTargetNode(Mips::MFHI, MVT::i32, MFInFlag); + SDOperand InFlag = SDOperand(MulNode, 0); + + if (MulOp == ISD::MUL) + return CurDAG->getTargetNode(Mips::MFLO, MVT::i32, InFlag); + else + return CurDAG->getTargetNode(Mips::MFHI, MVT::i32, InFlag); } - /// Div operations + /// Div/Rem operations + case ISD::SREM: + case ISD::UREM: case ISD::SDIV: case ISD::UDIV: { - SDOperand DivOp1 = Node->getOperand(0); - SDOperand DivOp2 = Node->getOperand(1); - AddToISelQueue(DivOp1); - AddToISelQueue(DivOp2); - - unsigned DivOp = (Opcode == ISD::SDIV ? Mips::DIV : Mips::DIVu); - SDNode *DivNode = CurDAG->getTargetNode(DivOp, MVT::Flag, DivOp1, DivOp2); - - SDOperand MFInFlag = SDOperand(DivNode, 0); - return CurDAG->getTargetNode(Mips::MFLO, MVT::i32, MFInFlag); - } - - /// Rem operations - case ISD::SREM: - case ISD::UREM: { - SDOperand RemOp1 = Node->getOperand(0); - SDOperand RemOp2 = Node->getOperand(1); - AddToISelQueue(RemOp1); - AddToISelQueue(RemOp2); - - unsigned RemOp = (Opcode == ISD::SREM ? Mips::DIV : Mips::DIVu); - SDNode *RemNode = CurDAG->getTargetNode(RemOp, MVT::Flag, RemOp1, RemOp2); + SDOperand Op1 = Node->getOperand(0); + SDOperand Op2 = Node->getOperand(1); + AddToISelQueue(Op1); + AddToISelQueue(Op2); + + unsigned Op, MOp; + if (Opcode == ISD::SDIV || Opcode == ISD::UDIV) { + Op = (Opcode == ISD::SDIV ? Mips::DIV : Mips::DIVu); + MOp = Mips::MFLO; + } else { + Op = (Opcode == ISD::SREM ? Mips::DIV : Mips::DIVu); + MOp = Mips::MFHI; + } + SDNode *Node = CurDAG->getTargetNode(Op, MVT::Flag, Op1, Op2); - SDOperand MFInFlag = SDOperand(RemNode, 0); - return CurDAG->getTargetNode(Mips::MFHI, MVT::i32, MFInFlag); + SDOperand InFlag = SDOperand(Node, 0); + return CurDAG->getTargetNode(MOp, MVT::i32, InFlag); } // Get target GOT address. Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=52036&r1=52035&r2=52036&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Fri Jun 6 01:37:31 2008 @@ -172,7 +172,7 @@ (outs CPURegs:$dst), (ins CPURegs:$b, uimm16:$c), !strconcat(instr_asm, " $dst, $b, $c"), - [(set CPURegs:$dst, (OpNode CPURegs:$b, immSExt16:$c))], IIAlu>; + [(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt16:$c))], IIAlu>; class LogicNOR op, bits<6> func, string instr_asm>: FR< op, @@ -392,9 +392,10 @@ // ADDiu just accept 16-bit immediates but we handle this on Pat's. // immZExt32 is used here so it can match GlobalAddress immediates. +// MUL is a assembly macro in the current used ISAs. def ADDiu : ArithI<0x09, "addiu", add, uimm16, immZExt16>; def ADDi : ArithI<0x08, "addi", add, simm16, immSExt16>; -def MUL : ArithR<0x1c, 0x02, "mul", mul, IIImul>; +//def MUL : ArithR<0x1c, 0x02, "mul", mul, IIImul>; def ADDu : ArithR<0x00, 0x21, "addu", add, IIAlu>; def SUBu : ArithR<0x00, 0x23, "subu", sub, IIAlu>; def ADD : ArithOverflowR<0x00, 0x20, "add">; From asl at math.spbu.ru Fri Jun 6 02:20:08 2008 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Fri, 06 Jun 2008 07:20:08 -0000 Subject: [llvm-commits] [llvm] r52037 - /llvm/trunk/lib/System/Win32/DynamicLibrary.inc Message-ID: <200806060720.m567K81g007310@zion.cs.uiuc.edu> Author: asl Date: Fri Jun 6 02:20:07 2008 New Revision: 52037 URL: http://llvm.org/viewvc/llvm-project?rev=52037&view=rev Log: Provide hooks for libgcc symbols' address resolution inside lli on mingw32. Patch by Julien Lerouge! Modified: llvm/trunk/lib/System/Win32/DynamicLibrary.inc Modified: llvm/trunk/lib/System/Win32/DynamicLibrary.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Win32/DynamicLibrary.inc?rev=52037&r1=52036&r2=52037&view=diff ============================================================================== --- llvm/trunk/lib/System/Win32/DynamicLibrary.inc (original) +++ llvm/trunk/lib/System/Win32/DynamicLibrary.inc Fri Jun 6 02:20:07 2008 @@ -134,6 +134,21 @@ #if defined(__MINGW32__) EXPLICIT_SYMBOL_DEF(_alloca); EXPLICIT_SYMBOL_DEF(__main); + EXPLICIT_SYMBOL_DEF(__ashldi3); + EXPLICIT_SYMBOL_DEF(__ashrdi3); + EXPLICIT_SYMBOL_DEF(__cmpdi2); + EXPLICIT_SYMBOL_DEF(__divdi3); + EXPLICIT_SYMBOL_DEF(__eprintf); + EXPLICIT_SYMBOL_DEF(__fixdfdi); + EXPLICIT_SYMBOL_DEF(__fixsfdi); + EXPLICIT_SYMBOL_DEF(__fixunsdfdi); + EXPLICIT_SYMBOL_DEF(__fixunssfdi); + EXPLICIT_SYMBOL_DEF(__floatdidf); + EXPLICIT_SYMBOL_DEF(__floatdisf); + EXPLICIT_SYMBOL_DEF(__lshrdi3); + EXPLICIT_SYMBOL_DEF(__moddi3); + EXPLICIT_SYMBOL_DEF(__udivdi3); + EXPLICIT_SYMBOL_DEF(__umoddi3); #elif defined(_MSC_VER) EXPLICIT_SYMBOL_DEF(_alloca_probe); #endif @@ -157,6 +172,21 @@ { EXPLICIT_SYMBOL(_alloca); EXPLICIT_SYMBOL(__main); + EXPLICIT_SYMBOL(__ashldi3); + EXPLICIT_SYMBOL(__ashrdi3); + EXPLICIT_SYMBOL(__cmpdi2); + EXPLICIT_SYMBOL(__divdi3); + EXPLICIT_SYMBOL(__eprintf); + EXPLICIT_SYMBOL(__fixdfdi); + EXPLICIT_SYMBOL(__fixsfdi); + EXPLICIT_SYMBOL(__fixunsdfdi); + EXPLICIT_SYMBOL(__fixunssfdi); + EXPLICIT_SYMBOL(__floatdidf); + EXPLICIT_SYMBOL(__floatdisf); + EXPLICIT_SYMBOL(__lshrdi3); + EXPLICIT_SYMBOL(__moddi3); + EXPLICIT_SYMBOL(__udivdi3); + EXPLICIT_SYMBOL(__umoddi3); EXPLICIT_SYMBOL2(alloca, _alloca); #undef EXPLICIT_SYMBOL From asl at math.spbu.ru Fri Jun 6 02:24:01 2008 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Fri, 06 Jun 2008 07:24:01 -0000 Subject: [llvm-commits] [llvm] r52038 - /llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp Message-ID: <200806060724.m567O1cI007426@zion.cs.uiuc.edu> Author: asl Date: Fri Jun 6 02:24:01 2008 New Revision: 52038 URL: http://llvm.org/viewvc/llvm-project?rev=52038&view=rev Log: Turn stdout into binary mode during bitcode emission. This is necessary on windows targets, since stdout is in text mode there. Patch by Julien Lerouge! Modified: llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp Modified: llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp?rev=52038&r1=52037&r2=52038&view=diff ============================================================================== --- llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp (original) +++ llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp Fri Jun 6 02:24:01 2008 @@ -23,6 +23,7 @@ #include "llvm/TypeSymbolTable.h" #include "llvm/ValueSymbolTable.h" #include "llvm/Support/MathExtras.h" +#include "llvm/System/Program.h" using namespace llvm; /// These are manifest constants used by the bitcode writer. They do not need to @@ -1292,6 +1293,10 @@ // Emit the module. WriteModule(M, Stream); + // If writing to stdout, set binary mode. + if (llvm::cout == Out) + sys::Program::ChangeStdoutToBinary(); + // Write the generated bitstream to "Out". Out.write((char*)&Buffer.front(), Buffer.size()); From asl at math.spbu.ru Fri Jun 6 02:25:40 2008 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Fri, 06 Jun 2008 07:25:40 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r52039 - /llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Message-ID: <200806060725.m567PfNj007476@zion.cs.uiuc.edu> Author: asl Date: Fri Jun 6 02:25:40 2008 New Revision: 52039 URL: http://llvm.org/viewvc/llvm-project?rev=52039&view=rev Log: Turn stdout into binary mode during bitcode emission. This is necessary on windows targets, since stdout is in text mode there. Patch by Julien Lerouge! Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=52039&r1=52038&r2=52039&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Fri Jun 6 02:25:40 2008 @@ -51,6 +51,7 @@ #include "llvm/Support/Streams.h" #include "llvm/Support/ManagedStatic.h" #include "llvm/Support/MemoryBuffer.h" +#include "llvm/System/Program.h" #include #undef VISIBILITY_HIDDEN extern "C" { @@ -272,6 +273,10 @@ PerModulePasses = new PassManager(); PerModulePasses->add(new TargetData(*TheTarget->getTargetData())); + // If writing to stdout, set binary mode. + if (asm_out_file == stdout) + sys::Program::ChangeStdoutToBinary(); + // Emit an LLVM .bc file to the output. This is used when passed // -emit-llvm -c to the GCC driver. PerModulePasses->add(CreateBitcodeWriterPass(*AsmOutStream)); @@ -473,6 +478,10 @@ // wrong for llvm/.bc emission cases. flag_no_ident = 1; + // If writing to stdout, set binary mode. + if (asm_out_file == stdout) + sys::Program::ChangeStdoutToBinary(); + AttributeUsedGlobals.clear(); timevar_pop(TV_LLVM_INIT); } From evan.cheng at apple.com Fri Jun 6 02:54:39 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 06 Jun 2008 07:54:39 -0000 Subject: [llvm-commits] [llvm] r52040 - in /llvm/trunk: include/llvm/CodeGen/LiveIntervalAnalysis.h lib/CodeGen/LiveIntervalAnalysis.cpp lib/CodeGen/RegAllocLinearScan.cpp Message-ID: <200806060754.m567sdoR016706@zion.cs.uiuc.edu> Author: evancheng Date: Fri Jun 6 02:54:39 2008 New Revision: 52040 URL: http://llvm.org/viewvc/llvm-project?rev=52040&view=rev Log: Refine stack slot interval weight computation. Modified: llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Modified: llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h?rev=52040&r1=52039&r2=52040&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h (original) +++ llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h Fri Jun 6 02:54:39 2008 @@ -283,10 +283,12 @@ } /// addIntervalsForSpills - Create new intervals for spilled defs / uses of - /// the given interval. + /// the given interval. FIXME: It also returns the weight of the spill slot + /// (if any is created) by reference. This is temporary. std::vector addIntervalsForSpills(const LiveInterval& i, - const MachineLoopInfo *loopInfo, VirtRegMap& vrm); + const MachineLoopInfo *loopInfo, VirtRegMap& vrm, + float &SSWeight); /// spillPhysRegAroundRegDefsUses - Spill the specified physical register /// around all defs and uses of the specified interval. @@ -424,7 +426,7 @@ SmallVector &ReMatIds, const MachineLoopInfo *loopInfo, unsigned &NewVReg, unsigned ImpUse, bool &HasDef, bool &HasUse, std::map &MBBVRegsMap, - std::vector &NewLIs); + std::vector &NewLIs, float &SSWeight); void rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit, LiveInterval::Ranges::const_iterator &I, MachineInstr *OrigDefMI, MachineInstr *DefMI, unsigned Slot, int LdSlot, @@ -436,7 +438,7 @@ BitVector &RestoreMBBs, std::map > &RestoreIdxes, std::map &MBBVRegsMap, - std::vector &NewLIs); + std::vector &NewLIs, float &SSWeight); static LiveInterval createInterval(unsigned Reg); Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=52040&r1=52039&r2=52040&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Fri Jun 6 02:54:39 2008 @@ -972,7 +972,9 @@ const MachineLoopInfo *loopInfo, unsigned &NewVReg, unsigned ImpUse, bool &HasDef, bool &HasUse, std::map &MBBVRegsMap, - std::vector &NewLIs) { + std::vector &NewLIs, float &SSWeight) { + MachineBasicBlock *MBB = MI->getParent(); + unsigned loopDepth = loopInfo->getLoopDepth(MBB); bool CanFold = false; RestartInstruction: for (unsigned i = 0; i != MI->getNumOperands(); ++i) { @@ -1041,7 +1043,14 @@ } } - if (TryFold) { + // Update stack slot spill weight if we are splitting. + float Weight = getSpillWeight(HasDef, HasUse, loopDepth); + if (!TrySplit) + SSWeight += Weight; + + if (!TryFold) + CanFold = false; + else { // Do not fold load / store here if we are splitting. We'll find an // optimal point to insert a load / store later. if (!TrySplit) { @@ -1052,15 +1061,17 @@ HasUse = false; HasDef = false; CanFold = false; - if (isRemoved(MI)) + if (isRemoved(MI)) { + SSWeight -= Weight; break; + } goto RestartInstruction; } } else { + // We'll try to fold it later if it's profitable. CanFold = canFoldMemoryOperand(MI, Ops, DefIsReMat); } - } else - CanFold = false; + } // Create a new virtual register for the spill interval. bool CreatedNewVReg = false; @@ -1195,7 +1206,7 @@ BitVector &RestoreMBBs, std::map > &RestoreIdxes, std::map &MBBVRegsMap, - std::vector &NewLIs) { + std::vector &NewLIs, float &SSWeight) { bool AllCanFold = true; unsigned NewVReg = 0; unsigned start = getBaseIndex(I->start); @@ -1283,10 +1294,10 @@ bool HasDef = false; bool HasUse = false; bool CanFold = rewriteInstructionForSpills(li, I->valno, TrySplit, - index, end, MI, ReMatOrigDefMI, ReMatDefMI, - Slot, LdSlot, isLoad, isLoadSS, DefIsReMat, - CanDelete, vrm, rc, ReMatIds, loopInfo, NewVReg, - ImpUse, HasDef, HasUse, MBBVRegsMap, NewLIs); + index, end, MI, ReMatOrigDefMI, ReMatDefMI, + Slot, LdSlot, isLoad, isLoadSS, DefIsReMat, + CanDelete, vrm, rc, ReMatIds, loopInfo, NewVReg, + ImpUse, HasDef, HasUse, MBBVRegsMap, NewLIs, SSWeight); if (!HasDef && !HasUse) continue; @@ -1445,7 +1456,8 @@ std::vector LiveIntervals:: addIntervalsForSpills(const LiveInterval &li, - const MachineLoopInfo *loopInfo, VirtRegMap &vrm) { + const MachineLoopInfo *loopInfo, VirtRegMap &vrm, + float &SSWeight) { // Since this is called after the analysis is done we don't know if // LiveVariables is available lv_ = getAnalysisToUpdate(); @@ -1457,6 +1469,9 @@ li.print(DOUT, tri_); DOUT << '\n'; + // Spill slot weight. + SSWeight = 0.0f; + // Each bit specify whether it a spill is required in the MBB. BitVector SpillMBBs(mf_->getNumBlockIDs()); std::map > SpillIdxes; @@ -1511,17 +1526,18 @@ Slot, LdSlot, isLoad, isLoadSS, DefIsReMat, false, vrm, rc, ReMatIds, loopInfo, SpillMBBs, SpillIdxes, RestoreMBBs, RestoreIdxes, - MBBVRegsMap, NewLIs); + MBBVRegsMap, NewLIs, SSWeight); } else { rewriteInstructionsForSpills(li, false, I, NULL, 0, Slot, 0, false, false, false, false, vrm, rc, ReMatIds, loopInfo, SpillMBBs, SpillIdxes, RestoreMBBs, RestoreIdxes, - MBBVRegsMap, NewLIs); + MBBVRegsMap, NewLIs, SSWeight); } IsFirstRange = false; } + SSWeight = 0.0f; // Already accounted for when split. handleSpilledImpDefs(li, vrm, rc, NewLIs); return NewLIs; } @@ -1587,7 +1603,7 @@ Slot, LdSlot, isLoad, isLoadSS, DefIsReMat, CanDelete, vrm, rc, ReMatIds, loopInfo, SpillMBBs, SpillIdxes, RestoreMBBs, RestoreIdxes, - MBBVRegsMap, NewLIs); + MBBVRegsMap, NewLIs, SSWeight); } // Insert spills / restores if we are splitting. @@ -1601,6 +1617,8 @@ if (NeedStackSlot) { int Id = SpillMBBs.find_first(); while (Id != -1) { + MachineBasicBlock *MBB = mf_->getBlockNumbered(Id); + unsigned loopDepth = loopInfo->getLoopDepth(MBB); std::vector &spills = SpillIdxes[Id]; for (unsigned i = 0, e = spills.size(); i != e; ++i) { int index = spills[i].index; @@ -1657,6 +1675,10 @@ if (isKill) AddedKill.insert(&nI); } + + // Update spill slot weight. + if (!isReMat) + SSWeight += getSpillWeight(true, false, loopDepth); } Id = SpillMBBs.find_next(Id); } @@ -1664,6 +1686,9 @@ int Id = RestoreMBBs.find_first(); while (Id != -1) { + MachineBasicBlock *MBB = mf_->getBlockNumbered(Id); + unsigned loopDepth = loopInfo->getLoopDepth(MBB); + std::vector &restores = RestoreIdxes[Id]; for (unsigned i = 0, e = restores.size(); i != e; ++i) { int index = restores[i].index; @@ -1671,6 +1696,7 @@ continue; unsigned VReg = restores[i].vreg; LiveInterval &nI = getOrCreateInterval(VReg); + bool isReMat = vrm.isReMaterialized(VReg); MachineInstr *MI = getInstructionFromIndex(index); bool CanFold = false; Ops.clear(); @@ -1694,7 +1720,7 @@ // Fold the load into the use if possible. bool Folded = false; if (CanFold && !Ops.empty()) { - if (!vrm.isReMaterialized(VReg)) + if (!isReMat) Folded = tryFoldMemoryOperand(MI, vrm, NULL,index,Ops,true,Slot,VReg); else { MachineInstr *ReMatDefMI = vrm.getReMaterializedMI(VReg); @@ -1722,6 +1748,10 @@ nI.removeRange(getLoadIndex(index), getUseIndex(index)+1); else vrm.addRestorePoint(VReg, MI); + + // Update spill slot weight. + if (!isReMat) + SSWeight += getSpillWeight(false, true, loopDepth); } Id = RestoreMBBs.find_next(Id); } Modified: llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp?rev=52040&r1=52039&r2=52040&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Fri Jun 6 02:54:39 2008 @@ -515,11 +515,14 @@ /// addStackInterval - Create a LiveInterval for stack if the specified live /// interval has been spilled. static void addStackInterval(LiveInterval *cur, LiveStacks *ls_, - LiveIntervals *li_, VirtRegMap &vrm_) { + LiveIntervals *li_, float &Weight, + VirtRegMap &vrm_) { int SS = vrm_.getStackSlot(cur->reg); if (SS == VirtRegMap::NO_STACK_SLOT) return; LiveInterval &SI = ls_->getOrCreateInterval(SS); + SI.weight += Weight; + VNInfo *VNI; if (SI.getNumValNums()) VNI = SI.getValNumInfo(0); @@ -529,7 +532,6 @@ LiveInterval &RI = li_->getInterval(cur->reg); // FIXME: This may be overly conservative. SI.MergeRangesInAsValue(RI, VNI); - SI.weight += RI.weight; } /// assignRegOrStackSlotAtInterval - assign a register if one is available, or @@ -743,9 +745,10 @@ // linearscan. if (cur->weight != HUGE_VALF && cur->weight <= minWeight) { DOUT << "\t\t\tspilling(c): " << *cur << '\n'; + float SSWeight; std::vector added = - li_->addIntervalsForSpills(*cur, loopInfo, *vrm_); - addStackInterval(cur, ls_, li_, *vrm_); + li_->addIntervalsForSpills(*cur, loopInfo, *vrm_, SSWeight); + addStackInterval(cur, ls_, li_, SSWeight, *vrm_); if (added.empty()) return; // Early exit if all spills were folded. @@ -796,9 +799,10 @@ cur->overlapsFrom(*i->first, i->second)) { DOUT << "\t\t\tspilling(a): " << *i->first << '\n'; earliestStart = std::min(earliestStart, i->first->beginNumber()); + float SSWeight; std::vector newIs = - li_->addIntervalsForSpills(*i->first, loopInfo, *vrm_); - addStackInterval(i->first, ls_, li_, *vrm_); + li_->addIntervalsForSpills(*i->first, loopInfo, *vrm_, SSWeight); + addStackInterval(i->first, ls_, li_, SSWeight, *vrm_); std::copy(newIs.begin(), newIs.end(), std::back_inserter(added)); spilled.insert(reg); } @@ -810,9 +814,10 @@ cur->overlapsFrom(*i->first, i->second-1)) { DOUT << "\t\t\tspilling(i): " << *i->first << '\n'; earliestStart = std::min(earliestStart, i->first->beginNumber()); + float SSWeight; std::vector newIs = - li_->addIntervalsForSpills(*i->first, loopInfo, *vrm_); - addStackInterval(i->first, ls_, li_, *vrm_); + li_->addIntervalsForSpills(*i->first, loopInfo, *vrm_, SSWeight); + addStackInterval(i->first, ls_, li_, SSWeight, *vrm_); std::copy(newIs.begin(), newIs.end(), std::back_inserter(added)); spilled.insert(reg); } From zhousheng00 at gmail.com Fri Jun 6 03:32:06 2008 From: zhousheng00 at gmail.com (Zhou Sheng) Date: Fri, 06 Jun 2008 08:32:06 -0000 Subject: [llvm-commits] [llvm] r52041 - /llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Message-ID: <200806060832.m568W6Si017780@zion.cs.uiuc.edu> Author: sheng Date: Fri Jun 6 03:32:05 2008 New Revision: 52041 URL: http://llvm.org/viewvc/llvm-project?rev=52041&view=rev Log: As Chris suggested, handle the situation if ShAmt larger than BitWidth, otherwise, opt might crash. Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp?rev=52041&r1=52040&r2=52041&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Fri Jun 6 03:32:05 2008 @@ -1236,7 +1236,7 @@ // If the input sign bit is known to be zero, or if none of the top bits // are demanded, turn this into an unsigned shift right. - if (BitWidth == ShiftAmt || RHSKnownZero[BitWidth-ShiftAmt-1] || + if (BitWidth <= ShiftAmt || RHSKnownZero[BitWidth-ShiftAmt-1] || (HighBits & ~DemandedMask) == HighBits) { // Perform the logical shift right. Value *NewVal = BinaryOperator::CreateLShr( From isanbard at gmail.com Fri Jun 6 03:36:13 2008 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 06 Jun 2008 08:36:13 -0000 Subject: [llvm-commits] [llvm] r52042 - /llvm/tags/Apple/llvmCore-2048/ Message-ID: <200806060836.m568aDVB017893@zion.cs.uiuc.edu> Author: void Date: Fri Jun 6 03:36:13 2008 New Revision: 52042 URL: http://llvm.org/viewvc/llvm-project?rev=52042&view=rev Log: Creating llvmCore-2048 branch Added: llvm/tags/Apple/llvmCore-2048/ - copied from r52041, llvm/trunk/ From isanbard at gmail.com Fri Jun 6 03:36:19 2008 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 06 Jun 2008 08:36:19 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r52043 - /llvm-gcc-4.2/tags/Apple/llvmgcc42-2048/ Message-ID: <200806060836.m568aJ4B017904@zion.cs.uiuc.edu> Author: void Date: Fri Jun 6 03:36:19 2008 New Revision: 52043 URL: http://llvm.org/viewvc/llvm-project?rev=52043&view=rev Log: Creating llvmgcc42-2048 branch Added: llvm-gcc-4.2/tags/Apple/llvmgcc42-2048/ - copied from r52042, llvm-gcc-4.2/trunk/ From matthijs at stdin.nl Fri Jun 6 04:57:53 2008 From: matthijs at stdin.nl (Matthijs Kooijman) Date: Fri, 6 Jun 2008 11:57:53 +0200 Subject: [llvm-commits] [llvm] r52002 - in /llvm/trunk: lib/VMCore/Verifier.cpp test/Assembler/AggregrateReturn.ll In-Reply-To: <1212709452.20049.24.camel@dgohman1> References: <200806051400.m55E0aUM024060@zion.cs.uiuc.edu> <1212709452.20049.24.camel@dgohman1> Message-ID: <20080606095753.GG25337@katherina.student.utwente.nl> Hi Dan, > define { i32 } @foo() { > ret i32 0 > } I didn't think this was valid syntax, but apparently it is used. The language reference is a bit vague about the multiple return syntax and constraints currently. > It's surprising that llvm-gcc is using { double } here instead > of just plain double, and possibly a minor bug. I'm going to > revert 52002 at least until the llvm-gcc issue is figured out. I'm seeing if I can reproduce the issue, but I guess this only triggers on a bootstrap build (which I didn't do before). > We'll probably also need to figure out an upgrade path for > LLVM 2.3 multiple-return-value code. I haven't thought much > about whether it's best to do a full transition all at once, or > to support both aggregate returns and multiple-return-values > at the same time for some time. I guess supporting both would be ok for now, though that might require some awkward code in some of the passes. Depending on what gcc does exactly, I'll fix gcc and reapply my patch, or leave gcc and modify my patch to also allow for the above syntax. Perhaps the last approach is better anyway, since this syntax is implicitely valid currently (the validator accepts it, and the language reference doesn't really say if this is ok or not...). Gr. Matthijs -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 189 bytes Desc: Digital signature Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20080606/ad9f0f89/attachment.bin From baldrick at free.fr Fri Jun 6 07:08:03 2008 From: baldrick at free.fr (Duncan Sands) Date: Fri, 06 Jun 2008 12:08:03 -0000 Subject: [llvm-commits] [llvm] r52044 - in /llvm/trunk: docs/ include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/SelectionDAG/ lib/Target/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/CellSPU/ lib/Target/IA64/ lib/Target/Mips/ lib/Target/PIC16/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/X86/ lib/Transforms/Scalar/ lib/VMCore/ utils/TableGen/ Message-ID: <200806061208.m56C86HV024845@zion.cs.uiuc.edu> Author: baldrick Date: Fri Jun 6 07:08:01 2008 New Revision: 52044 URL: http://llvm.org/viewvc/llvm-project?rev=52044&view=rev Log: Wrap MVT::ValueType in a struct to get type safety and better control the abstraction. Rename the type to MVT. To update out-of-tree patches, the main thing to do is to rename MVT::ValueType to MVT, and rewrite expressions like MVT::getSizeInBits(VT) in the form VT.getSizeInBits(). Use VT.getSimpleVT() to extract a MVT::SimpleValueType for use in switch statements (you will get an assert failure if VT is an extended value type - these shouldn't exist after type legalization). This results in a small speedup of codegen and no new testsuite failures (x86-64 linux). Modified: llvm/trunk/docs/CodeGenerator.html llvm/trunk/include/llvm/CodeGen/CallingConvLower.h llvm/trunk/include/llvm/CodeGen/SelectionDAG.h llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h llvm/trunk/include/llvm/CodeGen/ValueTypes.h llvm/trunk/include/llvm/Target/TargetLowering.h llvm/trunk/include/llvm/Target/TargetRegisterInfo.h llvm/trunk/lib/CodeGen/SelectionDAG/CallingConvLower.cpp llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesFloatToInt.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesScalarize.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesSplit.cpp llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.h llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp llvm/trunk/lib/Target/Alpha/AlphaISelLowering.h llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h llvm/trunk/lib/Target/IA64/IA64ISelDAGToDAG.cpp llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp llvm/trunk/lib/Target/IA64/IA64ISelLowering.h llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp llvm/trunk/lib/Target/Mips/MipsISelLowering.h llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp llvm/trunk/lib/Target/TargetRegisterInfo.cpp llvm/trunk/lib/Target/TargetSelectionDAG.td llvm/trunk/lib/Target/X86/X86ATTAsmPrinter.cpp llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.h llvm/trunk/lib/Target/X86/X86InstrInfo.cpp llvm/trunk/lib/Target/X86/X86IntelAsmPrinter.cpp llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp llvm/trunk/lib/Target/X86/X86RegisterInfo.h llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp llvm/trunk/lib/VMCore/Function.cpp llvm/trunk/lib/VMCore/ValueTypes.cpp llvm/trunk/lib/VMCore/Verifier.cpp llvm/trunk/utils/TableGen/CallingConvEmitter.cpp llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h llvm/trunk/utils/TableGen/CodeGenIntrinsics.h llvm/trunk/utils/TableGen/CodeGenRegisters.h llvm/trunk/utils/TableGen/CodeGenTarget.cpp llvm/trunk/utils/TableGen/CodeGenTarget.h llvm/trunk/utils/TableGen/DAGISelEmitter.cpp llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Modified: llvm/trunk/docs/CodeGenerator.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CodeGenerator.html?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/docs/CodeGenerator.html (original) +++ llvm/trunk/docs/CodeGenerator.html Fri Jun 6 07:08:01 2008 @@ -790,7 +790,8 @@ edges are represented by instances of the SDOperand class, which is a <SDNode, unsigned> pair, indicating the node and result value being used, respectively. Each value produced by an SDNode has -an associated MVT::ValueType indicating what type the value is.

              +an associated MVT (Machine Value Type) indicating what the type of the +value is.

              SelectionDAGs contain two different kinds of values: those that represent data flow and those that represent control flow dependencies. Data values are Modified: llvm/trunk/include/llvm/CodeGen/CallingConvLower.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/CallingConvLower.h?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/CallingConvLower.h (original) +++ llvm/trunk/include/llvm/CodeGen/CallingConvLower.h Fri Jun 6 07:08:01 2008 @@ -49,14 +49,14 @@ LocInfo HTP : 7; /// ValVT - The type of the value being assigned. - MVT::ValueType ValVT; + MVT ValVT; /// LocVT - The type of the location being assigned to. - MVT::ValueType LocVT; + MVT LocVT; public: - static CCValAssign getReg(unsigned ValNo, MVT::ValueType ValVT, - unsigned RegNo, MVT::ValueType LocVT, + static CCValAssign getReg(unsigned ValNo, MVT ValVT, + unsigned RegNo, MVT LocVT, LocInfo HTP) { CCValAssign Ret; Ret.ValNo = ValNo; @@ -67,8 +67,8 @@ Ret.LocVT = LocVT; return Ret; } - static CCValAssign getMem(unsigned ValNo, MVT::ValueType ValVT, - unsigned Offset, MVT::ValueType LocVT, + static CCValAssign getMem(unsigned ValNo, MVT ValVT, + unsigned Offset, MVT LocVT, LocInfo HTP) { CCValAssign Ret; Ret.ValNo = ValNo; @@ -81,14 +81,14 @@ } unsigned getValNo() const { return ValNo; } - MVT::ValueType getValVT() const { return ValVT; } + MVT getValVT() const { return ValVT; } bool isRegLoc() const { return !isMem; } bool isMemLoc() const { return isMem; } unsigned getLocReg() const { assert(isRegLoc()); return Loc; } unsigned getLocMemOffset() const { assert(isMemLoc()); return Loc; } - MVT::ValueType getLocVT() const { return LocVT; } + MVT getLocVT() const { return LocVT; } LocInfo getLocInfo() const { return HTP; } }; @@ -96,8 +96,8 @@ /// CCAssignFn - This function assigns a location for Val, updating State to /// reflect the change. -typedef bool CCAssignFn(unsigned ValNo, MVT::ValueType ValVT, - MVT::ValueType LocVT, CCValAssign::LocInfo LocInfo, +typedef bool CCAssignFn(unsigned ValNo, MVT ValVT, + MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State); @@ -217,8 +217,8 @@ // HandleByVal - Allocate a stack slot large enough to pass an argument by // value. The size and alignment information of the argument is encoded in its // parameter attribute. - void HandleByVal(unsigned ValNo, MVT::ValueType ValVT, - MVT::ValueType LocVT, CCValAssign::LocInfo LocInfo, + void HandleByVal(unsigned ValNo, MVT ValVT, + MVT LocVT, CCValAssign::LocInfo LocInfo, int MinSize, int MinAlign, ISD::ArgFlagsTy ArgFlags); private: Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Fri Jun 6 07:08:01 2008 @@ -144,24 +144,22 @@ /// getVTList - Return an SDVTList that represents the list of values /// specified. - SDVTList getVTList(MVT::ValueType VT); - SDVTList getVTList(MVT::ValueType VT1, MVT::ValueType VT2); - SDVTList getVTList(MVT::ValueType VT1, MVT::ValueType VT2,MVT::ValueType VT3); - SDVTList getVTList(const MVT::ValueType *VTs, unsigned NumVTs); + SDVTList getVTList(MVT VT); + SDVTList getVTList(MVT VT1, MVT VT2); + SDVTList getVTList(MVT VT1, MVT VT2, MVT VT3); + SDVTList getVTList(const MVT *VTs, unsigned NumVTs); /// getNodeValueTypes - These are obsolete, use getVTList instead. - const MVT::ValueType *getNodeValueTypes(MVT::ValueType VT) { + const MVT *getNodeValueTypes(MVT VT) { return getVTList(VT).VTs; } - const MVT::ValueType *getNodeValueTypes(MVT::ValueType VT1, - MVT::ValueType VT2) { + const MVT *getNodeValueTypes(MVT VT1, MVT VT2) { return getVTList(VT1, VT2).VTs; } - const MVT::ValueType *getNodeValueTypes(MVT::ValueType VT1,MVT::ValueType VT2, - MVT::ValueType VT3) { + const MVT *getNodeValueTypes(MVT VT1, MVT VT2, MVT VT3) { return getVTList(VT1, VT2, VT3).VTs; } - const MVT::ValueType *getNodeValueTypes(std::vector &vtList) { + const MVT *getNodeValueTypes(std::vector &vtList) { return getVTList(&vtList[0], (unsigned)vtList.size()).VTs; } @@ -170,57 +168,56 @@ // Node creation methods. // SDOperand getString(const std::string &Val); - SDOperand getConstant(uint64_t Val, MVT::ValueType VT, bool isTarget = false); - SDOperand getConstant(const APInt &Val, MVT::ValueType VT, bool isTarget = false); + SDOperand getConstant(uint64_t Val, MVT VT, bool isTarget = false); + SDOperand getConstant(const APInt &Val, MVT VT, bool isTarget = false); SDOperand getIntPtrConstant(uint64_t Val, bool isTarget = false); - SDOperand getTargetConstant(uint64_t Val, MVT::ValueType VT) { + SDOperand getTargetConstant(uint64_t Val, MVT VT) { return getConstant(Val, VT, true); } - SDOperand getTargetConstant(const APInt &Val, MVT::ValueType VT) { + SDOperand getTargetConstant(const APInt &Val, MVT VT) { return getConstant(Val, VT, true); } - SDOperand getConstantFP(double Val, MVT::ValueType VT, bool isTarget = false); - SDOperand getConstantFP(const APFloat& Val, MVT::ValueType VT, - bool isTarget = false); - SDOperand getTargetConstantFP(double Val, MVT::ValueType VT) { + SDOperand getConstantFP(double Val, MVT VT, bool isTarget = false); + SDOperand getConstantFP(const APFloat& Val, MVT VT, bool isTarget = false); + SDOperand getTargetConstantFP(double Val, MVT VT) { return getConstantFP(Val, VT, true); } - SDOperand getTargetConstantFP(const APFloat& Val, MVT::ValueType VT) { + SDOperand getTargetConstantFP(const APFloat& Val, MVT VT) { return getConstantFP(Val, VT, true); } - SDOperand getGlobalAddress(const GlobalValue *GV, MVT::ValueType VT, + SDOperand getGlobalAddress(const GlobalValue *GV, MVT VT, int offset = 0, bool isTargetGA = false); - SDOperand getTargetGlobalAddress(const GlobalValue *GV, MVT::ValueType VT, + SDOperand getTargetGlobalAddress(const GlobalValue *GV, MVT VT, int offset = 0) { return getGlobalAddress(GV, VT, offset, true); } - SDOperand getFrameIndex(int FI, MVT::ValueType VT, bool isTarget = false); - SDOperand getTargetFrameIndex(int FI, MVT::ValueType VT) { + SDOperand getFrameIndex(int FI, MVT VT, bool isTarget = false); + SDOperand getTargetFrameIndex(int FI, MVT VT) { return getFrameIndex(FI, VT, true); } - SDOperand getJumpTable(int JTI, MVT::ValueType VT, bool isTarget = false); - SDOperand getTargetJumpTable(int JTI, MVT::ValueType VT) { + SDOperand getJumpTable(int JTI, MVT VT, bool isTarget = false); + SDOperand getTargetJumpTable(int JTI, MVT VT) { return getJumpTable(JTI, VT, true); } - SDOperand getConstantPool(Constant *C, MVT::ValueType VT, + SDOperand getConstantPool(Constant *C, MVT VT, unsigned Align = 0, int Offs = 0, bool isT=false); - SDOperand getTargetConstantPool(Constant *C, MVT::ValueType VT, + SDOperand getTargetConstantPool(Constant *C, MVT VT, unsigned Align = 0, int Offset = 0) { return getConstantPool(C, VT, Align, Offset, true); } - SDOperand getConstantPool(MachineConstantPoolValue *C, MVT::ValueType VT, + SDOperand getConstantPool(MachineConstantPoolValue *C, MVT VT, unsigned Align = 0, int Offs = 0, bool isT=false); SDOperand getTargetConstantPool(MachineConstantPoolValue *C, - MVT::ValueType VT, unsigned Align = 0, + MVT VT, unsigned Align = 0, int Offset = 0) { return getConstantPool(C, VT, Align, Offset, true); } SDOperand getBasicBlock(MachineBasicBlock *MBB); - SDOperand getExternalSymbol(const char *Sym, MVT::ValueType VT); - SDOperand getTargetExternalSymbol(const char *Sym, MVT::ValueType VT); + SDOperand getExternalSymbol(const char *Sym, MVT VT); + SDOperand getTargetExternalSymbol(const char *Sym, MVT VT); SDOperand getArgFlags(ISD::ArgFlagsTy Flags); - SDOperand getValueType(MVT::ValueType); - SDOperand getRegister(unsigned Reg, MVT::ValueType VT); + SDOperand getValueType(MVT); + SDOperand getRegister(unsigned Reg, MVT VT); SDOperand getCopyToReg(SDOperand Chain, unsigned Reg, SDOperand N) { return getNode(ISD::CopyToReg, MVT::Other, Chain, @@ -232,7 +229,7 @@ // null) and that there should be a flag result. SDOperand getCopyToReg(SDOperand Chain, unsigned Reg, SDOperand N, SDOperand Flag) { - const MVT::ValueType *VTs = getNodeValueTypes(MVT::Other, MVT::Flag); + const MVT *VTs = getNodeValueTypes(MVT::Other, MVT::Flag); SDOperand Ops[] = { Chain, getRegister(Reg, N.getValueType()), N, Flag }; return getNode(ISD::CopyToReg, VTs, 2, Ops, Flag.Val ? 4 : 3); } @@ -240,13 +237,13 @@ // Similar to last getCopyToReg() except parameter Reg is a SDOperand SDOperand getCopyToReg(SDOperand Chain, SDOperand Reg, SDOperand N, SDOperand Flag) { - const MVT::ValueType *VTs = getNodeValueTypes(MVT::Other, MVT::Flag); + const MVT *VTs = getNodeValueTypes(MVT::Other, MVT::Flag); SDOperand Ops[] = { Chain, Reg, N, Flag }; return getNode(ISD::CopyToReg, VTs, 2, Ops, Flag.Val ? 4 : 3); } - SDOperand getCopyFromReg(SDOperand Chain, unsigned Reg, MVT::ValueType VT) { - const MVT::ValueType *VTs = getNodeValueTypes(VT, MVT::Other); + SDOperand getCopyFromReg(SDOperand Chain, unsigned Reg, MVT VT) { + const MVT *VTs = getNodeValueTypes(VT, MVT::Other); SDOperand Ops[] = { Chain, getRegister(Reg, VT) }; return getNode(ISD::CopyFromReg, VTs, 2, Ops, 2); } @@ -254,9 +251,9 @@ // This version of the getCopyFromReg method takes an extra operand, which // indicates that there is potentially an incoming flag value (if Flag is not // null) and that there should be a flag result. - SDOperand getCopyFromReg(SDOperand Chain, unsigned Reg, MVT::ValueType VT, + SDOperand getCopyFromReg(SDOperand Chain, unsigned Reg, MVT VT, SDOperand Flag) { - const MVT::ValueType *VTs = getNodeValueTypes(VT, MVT::Other, MVT::Flag); + const MVT *VTs = getNodeValueTypes(VT, MVT::Other, MVT::Flag); SDOperand Ops[] = { Chain, getRegister(Reg, VT), Flag }; return getNode(ISD::CopyFromReg, VTs, 3, Ops, Flag.Val ? 3 : 2); } @@ -265,12 +262,12 @@ /// getZeroExtendInReg - Return the expression required to zero extend the Op /// value assuming it was the smaller SrcTy value. - SDOperand getZeroExtendInReg(SDOperand Op, MVT::ValueType SrcTy); + SDOperand getZeroExtendInReg(SDOperand Op, MVT SrcTy); /// getCALLSEQ_START - Return a new CALLSEQ_START node, which always must have /// a flag result (to ensure it's not CSE'd). SDOperand getCALLSEQ_START(SDOperand Chain, SDOperand Op) { - const MVT::ValueType *VTs = getNodeValueTypes(MVT::Other, MVT::Flag); + const MVT *VTs = getNodeValueTypes(MVT::Other, MVT::Flag); SDOperand Ops[] = { Chain, Op }; return getNode(ISD::CALLSEQ_START, VTs, 2, Ops, 2); } @@ -291,27 +288,24 @@ /// getNode - Gets or creates the specified node. /// - SDOperand getNode(unsigned Opcode, MVT::ValueType VT); - SDOperand getNode(unsigned Opcode, MVT::ValueType VT, SDOperand N); - SDOperand getNode(unsigned Opcode, MVT::ValueType VT, - SDOperand N1, SDOperand N2); - SDOperand getNode(unsigned Opcode, MVT::ValueType VT, + SDOperand getNode(unsigned Opcode, MVT VT); + SDOperand getNode(unsigned Opcode, MVT VT, SDOperand N); + SDOperand getNode(unsigned Opcode, MVT VT, SDOperand N1, SDOperand N2); + SDOperand getNode(unsigned Opcode, MVT VT, SDOperand N1, SDOperand N2, SDOperand N3); - SDOperand getNode(unsigned Opcode, MVT::ValueType VT, + SDOperand getNode(unsigned Opcode, MVT VT, SDOperand N1, SDOperand N2, SDOperand N3, SDOperand N4); - SDOperand getNode(unsigned Opcode, MVT::ValueType VT, + SDOperand getNode(unsigned Opcode, MVT VT, SDOperand N1, SDOperand N2, SDOperand N3, SDOperand N4, SDOperand N5); - SDOperand getNode(unsigned Opcode, MVT::ValueType VT, + SDOperand getNode(unsigned Opcode, MVT VT, SDOperandPtr Ops, unsigned NumOps); + SDOperand getNode(unsigned Opcode, std::vector &ResultTys, SDOperandPtr Ops, unsigned NumOps); - SDOperand getNode(unsigned Opcode, std::vector &ResultTys, - SDOperandPtr Ops, unsigned NumOps); - SDOperand getNode(unsigned Opcode, const MVT::ValueType *VTs, unsigned NumVTs, + SDOperand getNode(unsigned Opcode, const MVT *VTs, unsigned NumVTs, SDOperandPtr Ops, unsigned NumOps); SDOperand getNode(unsigned Opcode, SDVTList VTs); SDOperand getNode(unsigned Opcode, SDVTList VTs, SDOperand N); - SDOperand getNode(unsigned Opcode, SDVTList VTs, - SDOperand N1, SDOperand N2); + SDOperand getNode(unsigned Opcode, SDVTList VTs, SDOperand N1, SDOperand N2); SDOperand getNode(unsigned Opcode, SDVTList VTs, SDOperand N1, SDOperand N2, SDOperand N3); SDOperand getNode(unsigned Opcode, SDVTList VTs, @@ -340,7 +334,7 @@ /// getSetCC - Helper function to make it easier to build SetCC's if you just /// have an ISD::CondCode instead of an SDOperand. /// - SDOperand getSetCC(MVT::ValueType VT, SDOperand LHS, SDOperand RHS, + SDOperand getSetCC(MVT VT, SDOperand LHS, SDOperand RHS, ISD::CondCode Cond) { return getNode(ISD::SETCC, VT, LHS, RHS, getCondCode(Cond)); } @@ -348,7 +342,7 @@ /// getVSetCC - Helper function to make it easier to build VSetCC's nodes /// if you just have an ISD::CondCode instead of an SDOperand. /// - SDOperand getVSetCC(MVT::ValueType VT, SDOperand LHS, SDOperand RHS, + SDOperand getVSetCC(MVT VT, SDOperand LHS, SDOperand RHS, ISD::CondCode Cond) { return getNode(ISD::VSETCC, VT, LHS, RHS, getCondCode(Cond)); } @@ -364,35 +358,35 @@ /// getVAArg - VAArg produces a result and token chain, and takes a pointer /// and a source value as input. - SDOperand getVAArg(MVT::ValueType VT, SDOperand Chain, SDOperand Ptr, + SDOperand getVAArg(MVT VT, SDOperand Chain, SDOperand Ptr, SDOperand SV); /// getAtomic - Gets a node for an atomic op, produces result and chain, takes // 3 operands SDOperand getAtomic(unsigned Opcode, SDOperand Chain, SDOperand Ptr, - SDOperand Cmp, SDOperand Swp, MVT::ValueType VT); + SDOperand Cmp, SDOperand Swp, MVT VT); /// getAtomic - Gets a node for an atomic op, produces result and chain, takes // 2 operands SDOperand getAtomic(unsigned Opcode, SDOperand Chain, SDOperand Ptr, - SDOperand Val, MVT::ValueType VT); + SDOperand Val, MVT VT); /// getLoad - Loads are not normal binary operators: their result type is not /// determined by their operands, and they produce a value AND a token chain. /// - SDOperand getLoad(MVT::ValueType VT, SDOperand Chain, SDOperand Ptr, + SDOperand getLoad(MVT VT, SDOperand Chain, SDOperand Ptr, const Value *SV, int SVOffset, bool isVolatile=false, unsigned Alignment=0); - SDOperand getExtLoad(ISD::LoadExtType ExtType, MVT::ValueType VT, + SDOperand getExtLoad(ISD::LoadExtType ExtType, MVT VT, SDOperand Chain, SDOperand Ptr, const Value *SV, - int SVOffset, MVT::ValueType EVT, bool isVolatile=false, + int SVOffset, MVT EVT, bool isVolatile=false, unsigned Alignment=0); SDOperand getIndexedLoad(SDOperand OrigLoad, SDOperand Base, SDOperand Offset, ISD::MemIndexedMode AM); SDOperand getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, - MVT::ValueType VT, SDOperand Chain, + MVT VT, SDOperand Chain, SDOperand Ptr, SDOperand Offset, - const Value *SV, int SVOffset, MVT::ValueType EVT, + const Value *SV, int SVOffset, MVT EVT, bool isVolatile=false, unsigned Alignment=0); /// getStore - Helper function to build ISD::STORE nodes. @@ -401,7 +395,7 @@ const Value *SV, int SVOffset, bool isVolatile=false, unsigned Alignment=0); SDOperand getTruncStore(SDOperand Chain, SDOperand Val, SDOperand Ptr, - const Value *SV, int SVOffset, MVT::ValueType TVT, + const Value *SV, int SVOffset, MVT TVT, bool isVolatile=false, unsigned Alignment=0); SDOperand getIndexedStore(SDOperand OrigStoe, SDOperand Base, SDOperand Offset, ISD::MemIndexedMode AM); @@ -434,20 +428,18 @@ /// operands. Note that target opcodes are stored as /// ISD::BUILTIN_OP_END+TargetOpcode in the node opcode field. The 0th value /// of the resultant node is returned. - SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT::ValueType VT); - SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT::ValueType VT, - SDOperand Op1); - SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT::ValueType VT, + SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT); + SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT, SDOperand Op1); + SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT, SDOperand Op1, SDOperand Op2); - SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT::ValueType VT, + SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT, SDOperand Op1, SDOperand Op2, SDOperand Op3); - SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT::ValueType VT, + SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT, SDOperandPtr Ops, unsigned NumOps); - SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT::ValueType VT1, - MVT::ValueType VT2, SDOperand Op1, SDOperand Op2); - SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT::ValueType VT1, - MVT::ValueType VT2, SDOperand Op1, SDOperand Op2, - SDOperand Op3); + SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT1, + MVT VT2, SDOperand Op1, SDOperand Op2); + SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT1, + MVT VT2, SDOperand Op1, SDOperand Op2, SDOperand Op3); /// getTargetNode - These are used for target selectors to create a new node @@ -456,41 +448,30 @@ /// Note that getTargetNode returns the resultant node. If there is already a /// node of the specified opcode and operands, it returns that node instead of /// the current one. - SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT); - SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT, - SDOperand Op1); - SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT, - SDOperand Op1, SDOperand Op2); - SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT, + SDNode *getTargetNode(unsigned Opcode, MVT VT); + SDNode *getTargetNode(unsigned Opcode, MVT VT, SDOperand Op1); + SDNode *getTargetNode(unsigned Opcode, MVT VT, SDOperand Op1, SDOperand Op2); + SDNode *getTargetNode(unsigned Opcode, MVT VT, SDOperand Op1, SDOperand Op2, SDOperand Op3); - SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT, + SDNode *getTargetNode(unsigned Opcode, MVT VT, SDOperandPtr Ops, unsigned NumOps); - SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT1, - MVT::ValueType VT2); - SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT1, - MVT::ValueType VT2, SDOperand Op1); - SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT1, - MVT::ValueType VT2, SDOperand Op1, SDOperand Op2); - SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT1, - MVT::ValueType VT2, SDOperand Op1, SDOperand Op2, - SDOperand Op3); - SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT1, - MVT::ValueType VT2, + SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2); + SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, SDOperand Op1); + SDNode *getTargetNode(unsigned Opcode, MVT VT1, + MVT VT2, SDOperand Op1, SDOperand Op2); + SDNode *getTargetNode(unsigned Opcode, MVT VT1, + MVT VT2, SDOperand Op1, SDOperand Op2, SDOperand Op3); + SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, SDOperandPtr Ops, unsigned NumOps); - SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT1, - MVT::ValueType VT2, MVT::ValueType VT3, + SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, SDOperand Op1, SDOperand Op2); - SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT1, - MVT::ValueType VT2, MVT::ValueType VT3, + SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, SDOperand Op1, SDOperand Op2, SDOperand Op3); - SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT1, - MVT::ValueType VT2, MVT::ValueType VT3, + SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, SDOperandPtr Ops, unsigned NumOps); - SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT1, - MVT::ValueType VT2, MVT::ValueType VT3, - MVT::ValueType VT4, + SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, MVT VT4, SDOperandPtr Ops, unsigned NumOps); - SDNode *getTargetNode(unsigned Opcode, std::vector &ResultTys, + SDNode *getTargetNode(unsigned Opcode, std::vector &ResultTys, SDOperandPtr Ops, unsigned NumOps); /// getNodeIfExists - Get the specified node if it's already available, or @@ -570,10 +551,10 @@ /// CreateStackTemporary - Create a stack temporary, suitable for holding the /// specified value type. - SDOperand CreateStackTemporary(MVT::ValueType VT); + SDOperand CreateStackTemporary(MVT VT); /// FoldSetCC - Constant fold a setcc to true or false. - SDOperand FoldSetCC(MVT::ValueType VT, SDOperand N1, + SDOperand FoldSetCC(MVT VT, SDOperand N1, SDOperand N2, ISD::CondCode Cond); /// SignBitIsZero - Return true if the sign bit of Op is known to be zero. We @@ -623,13 +604,13 @@ void DeleteNodeNotInCSEMaps(SDNode *N); // List of non-single value types. - std::list > VTList; + std::list > VTList; // Maps to auto-CSE operations. std::vector CondCodeNodes; std::vector ValueTypeNodes; - std::map ExtendedValueTypeNodes; + std::map ExtendedValueTypeNodes; std::map ExternalSymbols; std::map TargetExternalSymbols; std::map StringNodes; Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h Fri Jun 6 07:08:01 2008 @@ -55,7 +55,7 @@ virtual bool runOnFunction(Function &Fn); - unsigned MakeReg(MVT::ValueType VT); + unsigned MakeReg(MVT VT); virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {} virtual void InstructionSelectBasicBlock(SelectionDAG &SD) = 0; Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Fri Jun 6 07:08:01 2008 @@ -48,7 +48,7 @@ /// SelectionDAG::getVTList(...). /// struct SDVTList { - const MVT::ValueType *VTs; + const MVT *VTs; unsigned short NumVTs; }; @@ -834,12 +834,12 @@ /// getValueType - Return the ValueType of the referenced return value. /// - inline MVT::ValueType getValueType() const; + inline MVT getValueType() const; - /// getValueSizeInBits - Returns MVT::getSizeInBits(getValueType()). + /// getValueSizeInBits - Returns the size of the value in bits. /// unsigned getValueSizeInBits() const { - return MVT::getSizeInBits(getValueType()); + return getValueType().getSizeInBits(); } // Forwarding methods - These forward to the corresponding methods in SDNode. @@ -1045,7 +1045,7 @@ /// ValueList - The types of the values this node defines. SDNode's may /// define multiple values simultaneously. - const MVT::ValueType *ValueList; + const MVT *ValueList; /// NumOperands/NumValues - The number of entries in the Operand/Value list. unsigned short NumOperands, NumValues; @@ -1216,7 +1216,7 @@ /// getValueType - Return the type of a specified result. /// - MVT::ValueType getValueType(unsigned ResNo) const { + MVT getValueType(unsigned ResNo) const { assert(ResNo < NumValues && "Illegal result number!"); return ValueList[ResNo]; } @@ -1224,10 +1224,10 @@ /// getValueSizeInBits - Returns MVT::getSizeInBits(getValueType(ResNo)). /// unsigned getValueSizeInBits(unsigned ResNo) const { - return MVT::getSizeInBits(getValueType(ResNo)); + return getValueType(ResNo).getSizeInBits(); } - typedef const MVT::ValueType* value_iterator; + typedef const MVT* value_iterator; value_iterator value_begin() const { return ValueList; } value_iterator value_end() const { return ValueList+NumValues; } @@ -1249,8 +1249,8 @@ /// getValueTypeList - Return a pointer to the specified value type. /// - static const MVT::ValueType *getValueTypeList(MVT::ValueType VT); - static SDVTList getSDVTList(MVT::ValueType VT) { + static const MVT *getValueTypeList(MVT VT); + static SDVTList getSDVTList(MVT VT) { SDVTList Ret = { getValueTypeList(VT), 1 }; return Ret; } @@ -1344,7 +1344,7 @@ inline unsigned SDOperand::getOpcode() const { return Val->getOpcode(); } -inline MVT::ValueType SDOperand::getValueType() const { +inline MVT SDOperand::getValueType() const { return Val->getValueType(ResNo); } inline unsigned SDOperand::getNumOperands() const { @@ -1439,10 +1439,10 @@ class AtomicSDNode : public SDNode { virtual void ANCHOR(); // Out-of-line virtual method to give class a home. SDUse Ops[4]; - MVT::ValueType OrigVT; + MVT OrigVT; public: AtomicSDNode(unsigned Opc, SDVTList VTL, SDOperand Chain, SDOperand Ptr, - SDOperand Cmp, SDOperand Swp, MVT::ValueType VT) + SDOperand Cmp, SDOperand Swp, MVT VT) : SDNode(Opc, VTL) { Ops[0] = Chain; Ops[1] = Ptr; @@ -1452,7 +1452,7 @@ OrigVT=VT; } AtomicSDNode(unsigned Opc, SDVTList VTL, SDOperand Chain, SDOperand Ptr, - SDOperand Val, MVT::ValueType VT) + SDOperand Val, MVT VT) : SDNode(Opc, VTL) { Ops[0] = Chain; Ops[1] = Ptr; @@ -1460,7 +1460,7 @@ InitOperands(Ops, 3); OrigVT=VT; } - MVT::ValueType getVT() const { return OrigVT; } + MVT getVT() const { return OrigVT; } bool isCompareAndSwap() const { return getOpcode() == ISD::ATOMIC_LCS; } }; @@ -1485,7 +1485,7 @@ virtual void ANCHOR(); // Out-of-line virtual method to give class a home. protected: friend class SelectionDAG; - ConstantSDNode(bool isTarget, const APInt &val, MVT::ValueType VT) + ConstantSDNode(bool isTarget, const APInt &val, MVT VT) : SDNode(isTarget ? ISD::TargetConstant : ISD::Constant, getSDVTList(VT)), Value(val) { } @@ -1495,13 +1495,13 @@ uint64_t getValue() const { return Value.getZExtValue(); } int64_t getSignExtended() const { - unsigned Bits = MVT::getSizeInBits(getValueType(0)); + unsigned Bits = getValueType(0).getSizeInBits(); return ((int64_t)Value.getZExtValue() << (64-Bits)) >> (64-Bits); } bool isNullValue() const { return Value == 0; } bool isAllOnesValue() const { - return Value == MVT::getIntVTBitMask(getValueType(0)); + return Value == getValueType(0).getIntegerVTBitMask(); } static bool classof(const ConstantSDNode *) { return true; } @@ -1516,7 +1516,7 @@ virtual void ANCHOR(); // Out-of-line virtual method to give class a home. protected: friend class SelectionDAG; - ConstantFPSDNode(bool isTarget, const APFloat& val, MVT::ValueType VT) + ConstantFPSDNode(bool isTarget, const APFloat& val, MVT VT) : SDNode(isTarget ? ISD::TargetConstantFP : ISD::ConstantFP, getSDVTList(VT)), Value(val) { } @@ -1542,7 +1542,7 @@ } bool isExactlyValue(const APFloat& V) const; - bool isValueValidForType(MVT::ValueType VT, const APFloat& Val); + bool isValueValidForType(MVT VT, const APFloat& Val); static bool classof(const ConstantFPSDNode *) { return true; } static bool classof(const SDNode *N) { @@ -1557,8 +1557,7 @@ virtual void ANCHOR(); // Out-of-line virtual method to give class a home. protected: friend class SelectionDAG; - GlobalAddressSDNode(bool isTarget, const GlobalValue *GA, MVT::ValueType VT, - int o = 0); + GlobalAddressSDNode(bool isTarget, const GlobalValue *GA, MVT VT, int o = 0); public: GlobalValue *getGlobal() const { return TheGlobal; } @@ -1578,7 +1577,7 @@ virtual void ANCHOR(); // Out-of-line virtual method to give class a home. protected: friend class SelectionDAG; - FrameIndexSDNode(int fi, MVT::ValueType VT, bool isTarg) + FrameIndexSDNode(int fi, MVT VT, bool isTarg) : SDNode(isTarg ? ISD::TargetFrameIndex : ISD::FrameIndex, getSDVTList(VT)), FI(fi) { } @@ -1598,7 +1597,7 @@ virtual void ANCHOR(); // Out-of-line virtual method to give class a home. protected: friend class SelectionDAG; - JumpTableSDNode(int jti, MVT::ValueType VT, bool isTarg) + JumpTableSDNode(int jti, MVT VT, bool isTarg) : SDNode(isTarg ? ISD::TargetJumpTable : ISD::JumpTable, getSDVTList(VT)), JTI(jti) { } @@ -1623,22 +1622,20 @@ virtual void ANCHOR(); // Out-of-line virtual method to give class a home. protected: friend class SelectionDAG; - ConstantPoolSDNode(bool isTarget, Constant *c, MVT::ValueType VT, - int o=0) + ConstantPoolSDNode(bool isTarget, Constant *c, MVT VT, int o=0) : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool, getSDVTList(VT)), Offset(o), Alignment(0) { assert((int)Offset >= 0 && "Offset is too large"); Val.ConstVal = c; } - ConstantPoolSDNode(bool isTarget, Constant *c, MVT::ValueType VT, int o, - unsigned Align) + ConstantPoolSDNode(bool isTarget, Constant *c, MVT VT, int o, unsigned Align) : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool, getSDVTList(VT)), Offset(o), Alignment(Align) { assert((int)Offset >= 0 && "Offset is too large"); Val.ConstVal = c; } ConstantPoolSDNode(bool isTarget, MachineConstantPoolValue *v, - MVT::ValueType VT, int o=0) + MVT VT, int o=0) : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool, getSDVTList(VT)), Offset(o), Alignment(0) { assert((int)Offset >= 0 && "Offset is too large"); @@ -1646,7 +1643,7 @@ Offset |= 1 << (sizeof(unsigned)*8-1); } ConstantPoolSDNode(bool isTarget, MachineConstantPoolValue *v, - MVT::ValueType VT, int o, unsigned Align) + MVT VT, int o, unsigned Align) : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool, getSDVTList(VT)), Offset(o), Alignment(Align) { assert((int)Offset >= 0 && "Offset is too large"); @@ -1760,7 +1757,7 @@ virtual void ANCHOR(); // Out-of-line virtual method to give class a home. protected: friend class SelectionDAG; - RegisterSDNode(unsigned reg, MVT::ValueType VT) + RegisterSDNode(unsigned reg, MVT VT) : SDNode(ISD::Register, getSDVTList(VT)), Reg(reg) { } public: @@ -1778,7 +1775,7 @@ virtual void ANCHOR(); // Out-of-line virtual method to give class a home. protected: friend class SelectionDAG; - ExternalSymbolSDNode(bool isTarget, const char *Sym, MVT::ValueType VT) + ExternalSymbolSDNode(bool isTarget, const char *Sym, MVT VT) : SDNode(isTarget ? ISD::TargetExternalSymbol : ISD::ExternalSymbol, getSDVTList(VT)), Symbol(Sym) { } @@ -1914,19 +1911,19 @@ } }; -/// VTSDNode - This class is used to represent MVT::ValueType's, which are used +/// VTSDNode - This class is used to represent MVT's, which are used /// to parameterize some operations. class VTSDNode : public SDNode { - MVT::ValueType ValueType; + MVT ValueType; virtual void ANCHOR(); // Out-of-line virtual method to give class a home. protected: friend class SelectionDAG; - explicit VTSDNode(MVT::ValueType VT) + explicit VTSDNode(MVT VT) : SDNode(ISD::VALUETYPE, getSDVTList(MVT::Other)), ValueType(VT) { } public: - MVT::ValueType getVT() const { return ValueType; } + MVT getVT() const { return ValueType; } static bool classof(const VTSDNode *) { return true; } static bool classof(const SDNode *N) { @@ -1942,7 +1939,7 @@ ISD::MemIndexedMode AddrMode; // MemoryVT - VT of in-memory value. - MVT::ValueType MemoryVT; + MVT MemoryVT; //! SrcValue - Memory location for alias analysis. const Value *SrcValue; @@ -1965,7 +1962,7 @@ SDUse Ops[4]; public: LSBaseSDNode(ISD::NodeType NodeTy, SDOperand *Operands, unsigned numOperands, - SDVTList VTs, ISD::MemIndexedMode AM, MVT::ValueType VT, + SDVTList VTs, ISD::MemIndexedMode AM, MVT VT, const Value *SV, int SVO, unsigned Align, bool Vol) : SDNode(NodeTy, VTs), AddrMode(AM), MemoryVT(VT), @@ -1989,7 +1986,7 @@ const Value *getSrcValue() const { return SrcValue; } int getSrcValueOffset() const { return SVOffset; } unsigned getAlignment() const { return Alignment; } - MVT::ValueType getMemoryVT() const { return MemoryVT; } + MVT getMemoryVT() const { return MemoryVT; } bool isVolatile() const { return IsVolatile; } ISD::MemIndexedMode getAddressingMode() const { return AddrMode; } @@ -2022,7 +2019,7 @@ protected: friend class SelectionDAG; LoadSDNode(SDOperand *ChainPtrOff, SDVTList VTs, - ISD::MemIndexedMode AM, ISD::LoadExtType ETy, MVT::ValueType LVT, + ISD::MemIndexedMode AM, ISD::LoadExtType ETy, MVT LVT, const Value *SV, int O=0, unsigned Align=0, bool Vol=false) : LSBaseSDNode(ISD::LOAD, ChainPtrOff, 3, VTs, AM, LVT, SV, O, Align, Vol), @@ -2049,7 +2046,7 @@ protected: friend class SelectionDAG; StoreSDNode(SDOperand *ChainValuePtrOff, SDVTList VTs, - ISD::MemIndexedMode AM, bool isTrunc, MVT::ValueType SVT, + ISD::MemIndexedMode AM, bool isTrunc, MVT SVT, const Value *SV, int O=0, unsigned Align=0, bool Vol=false) : LSBaseSDNode(ISD::STORE, ChainValuePtrOff, 4, VTs, AM, SVT, SV, O, Align, Vol), Modified: llvm/trunk/include/llvm/CodeGen/ValueTypes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ValueTypes.h?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/ValueTypes.h (original) +++ llvm/trunk/include/llvm/CodeGen/ValueTypes.h Fri Jun 6 07:08:01 2008 @@ -24,368 +24,389 @@ namespace llvm { class Type; -/// MVT namespace - This namespace defines the SimpleValueType enum, which -/// contains the various low-level value types, and the ValueType typedef. -/// -namespace MVT { // MVT = Machine Value Types - enum SimpleValueType { - // If you change this numbering, you must change the values in ValueTypes.td - // well! - Other = 0, // This is a non-standard value - i1 = 1, // This is a 1 bit integer value - i8 = 2, // This is an 8 bit integer value - i16 = 3, // This is a 16 bit integer value - i32 = 4, // This is a 32 bit integer value - i64 = 5, // This is a 64 bit integer value - i128 = 6, // This is a 128 bit integer value - - FIRST_INTEGER_VALUETYPE = i1, - LAST_INTEGER_VALUETYPE = i128, - - f32 = 7, // This is a 32 bit floating point value - f64 = 8, // This is a 64 bit floating point value - f80 = 9, // This is a 80 bit floating point value - f128 = 10, // This is a 128 bit floating point value - ppcf128 = 11, // This is a PPC 128-bit floating point value - Flag = 12, // This is a condition code or machine flag. - - isVoid = 13, // This has no value - - v8i8 = 14, // 8 x i8 - v4i16 = 15, // 4 x i16 - v2i32 = 16, // 2 x i32 - v1i64 = 17, // 1 x i64 - v16i8 = 18, // 16 x i8 - v8i16 = 19, // 8 x i16 - v3i32 = 20, // 3 x i32 - v4i32 = 21, // 4 x i32 - v2i64 = 22, // 2 x i64 - - v2f32 = 23, // 2 x f32 - v3f32 = 24, // 3 x f32 - v4f32 = 25, // 4 x f32 - v2f64 = 26, // 2 x f64 - - FIRST_VECTOR_VALUETYPE = v8i8, - LAST_VECTOR_VALUETYPE = v2f64, - - LAST_VALUETYPE = 27, // This always remains at the end of the list. - - // fAny - Any floating-point or vector floating-point value. This is used - // for intrinsics that have overloadings based on floating-point types. - // This is only for tblgen's consumption! - fAny = 253, - - // iAny - An integer or vector integer value of any bit width. This is - // used for intrinsics that have overloadings based on integer bit widths. - // This is only for tblgen's consumption! - iAny = 254, - - // iPTR - An int value the size of the pointer of the current - // target. This should only be used internal to tblgen! - iPTR = 255 - }; + struct MVT { // MVT = Machine Value Type + + enum SimpleValueType { + // If you change this numbering, you must change the values in + // ValueTypes.td well! + Other = 0, // This is a non-standard value + i1 = 1, // This is a 1 bit integer value + i8 = 2, // This is an 8 bit integer value + i16 = 3, // This is a 16 bit integer value + i32 = 4, // This is a 32 bit integer value + i64 = 5, // This is a 64 bit integer value + i128 = 6, // This is a 128 bit integer value + + FIRST_INTEGER_VALUETYPE = i1, + LAST_INTEGER_VALUETYPE = i128, + + f32 = 7, // This is a 32 bit floating point value + f64 = 8, // This is a 64 bit floating point value + f80 = 9, // This is a 80 bit floating point value + f128 = 10, // This is a 128 bit floating point value + ppcf128 = 11, // This is a PPC 128-bit floating point value + Flag = 12, // This is a condition code or machine flag. + + isVoid = 13, // This has no value + + v8i8 = 14, // 8 x i8 + v4i16 = 15, // 4 x i16 + v2i32 = 16, // 2 x i32 + v1i64 = 17, // 1 x i64 + v16i8 = 18, // 16 x i8 + v8i16 = 19, // 8 x i16 + v3i32 = 20, // 3 x i32 + v4i32 = 21, // 4 x i32 + v2i64 = 22, // 2 x i64 + + v2f32 = 23, // 2 x f32 + v3f32 = 24, // 3 x f32 + v4f32 = 25, // 4 x f32 + v2f64 = 26, // 2 x f64 + + FIRST_VECTOR_VALUETYPE = v8i8, + LAST_VECTOR_VALUETYPE = v2f64, + + LAST_VALUETYPE = 27, // This always remains at the end of the list. + + // fAny - Any floating-point or vector floating-point value. This is used + // for intrinsics that have overloadings based on floating-point types. + // This is only for tblgen's consumption! + fAny = 253, + + // iAny - An integer or vector integer value of any bit width. This is + // used for intrinsics that have overloadings based on integer bit widths. + // This is only for tblgen's consumption! + iAny = 254, + + // iPTR - An int value the size of the pointer of the current + // target. This should only be used internal to tblgen! + iPTR = 255 + }; + + /// MVT - This type holds low-level value types. Valid values include any of + /// the values in the SimpleValueType enum, or any value returned from one + /// of the MVT methods. Any value type equal to one of the SimpleValueType + /// enum values is a "simple" value type. All others are "extended". + /// + /// Note that simple doesn't necessary mean legal for the target machine. + /// All legal value types must be simple, but often there are some simple + /// value types that are not legal. + /// + /// @internal + /// Extended types are either vector types or arbitrary precision integers. + /// Arbitrary precision integers have iAny in the first SimpleTypeBits bits, + /// and the bit-width in the next PrecisionBits bits, offset by minus one. + /// Vector types are encoded by having the first SimpleTypeBits+PrecisionBits + /// bits encode the vector element type (which must be a scalar type, possibly + /// an arbitrary precision integer) and the remaining VectorBits upper bits + /// encode the vector length, offset by one. + /// + /// 31--------------16-----------8-------------0 + /// | Vector length | Precision | Simple type | + /// | | Vector element | + /// + + static const int SimpleTypeBits = 8; + static const int PrecisionBits = 8; + static const int VectorBits = 32 - SimpleTypeBits - PrecisionBits; + + static const uint32_t SimpleTypeMask = + (~uint32_t(0) << (32 - SimpleTypeBits)) >> (32 - SimpleTypeBits); + + static const uint32_t PrecisionMask = + ((~uint32_t(0) << VectorBits) >> (32 - PrecisionBits)) << SimpleTypeBits; + + static const uint32_t VectorMask = + (~uint32_t(0) >> (32 - VectorBits)) << (32 - VectorBits); + + static const uint32_t ElementMask = + (~uint32_t(0) << VectorBits) >> VectorBits; + + uint32_t V; + + MVT() {} + MVT(SimpleValueType S) { V = S; } + inline bool operator== (const MVT VT) const { return V == VT.V; } + inline bool operator!= (const MVT VT) const { return V != VT.V; } + + /// FIXME: The following comparison methods are bogus - they are only here + /// to ease the transition to a struct type. + inline bool operator< (const MVT VT) const { return V < VT.V; } + inline bool operator<= (const MVT VT) const { return V <= VT.V; } + inline bool operator> (const MVT VT) const { return V > VT.V; } + inline bool operator>= (const MVT VT) const { return V >= VT.V; } + + /// getIntegerVT - Returns the MVT that represents an integer with the given + /// number of bits. + static inline MVT getIntegerVT(unsigned BitWidth) { + switch (BitWidth) { + default: + break; + case 1: + return i1; + case 8: + return i8; + case 16: + return i16; + case 32: + return i32; + case 64: + return i64; + case 128: + return i128; + } + MVT VT; + VT.V = iAny | (((BitWidth - 1) << SimpleTypeBits) & PrecisionMask); + assert(VT.getSizeInBits() == BitWidth && "Bad bit width!"); + return VT; + } + + /// getVectorVT - Returns the MVT that represents a vector NumElements in + /// length, where each element is of type VT. + static inline MVT getVectorVT(MVT VT, unsigned NumElements) { + switch (VT.V) { + default: + break; + case i8: + if (NumElements == 8) return v8i8; + if (NumElements == 16) return v16i8; + break; + case i16: + if (NumElements == 4) return v4i16; + if (NumElements == 8) return v8i16; + break; + case i32: + if (NumElements == 2) return v2i32; + if (NumElements == 3) return v3i32; + if (NumElements == 4) return v4i32; + break; + case i64: + if (NumElements == 1) return v1i64; + if (NumElements == 2) return v2i64; + break; + case f32: + if (NumElements == 2) return v2f32; + if (NumElements == 3) return v3f32; + if (NumElements == 4) return v4f32; + break; + case f64: + if (NumElements == 2) return v2f64; + break; + } + // Set the length with the top bit forced to zero (needed by the verifier). + MVT Result; + Result.V = VT.V | (((NumElements + 1) << (33 - VectorBits)) >> 1); + assert(Result.getVectorElementType() == VT && + "Bad vector element type!"); + assert(Result.getVectorNumElements() == NumElements && + "Bad vector length!"); + return Result; + } + + /// getIntVectorWithNumElements - Return any integer vector type that has + /// the specified number of elements. + static inline MVT getIntVectorWithNumElements(unsigned NumElts) { + switch (NumElts) { + default: return getVectorVT(i8, NumElts); + case 1: return v1i64; + case 2: return v2i32; + case 3: return v3i32; + case 4: return v4i16; + case 8: return v8i8; + case 16: return v16i8; + } + } + + + /// isSimple - Test if the given MVT is simple (as opposed to being + /// extended). + inline bool isSimple() const { + return V <= SimpleTypeMask; + } + + /// isExtended - Test if the given MVT is extended (as opposed to + /// being simple). + inline bool isExtended() const { + return !isSimple(); + } + + /// isFloatingPoint - Return true if this is a FP, or a vector FP type. + inline bool isFloatingPoint() const { + uint32_t SVT = V & SimpleTypeMask; + return (SVT >= f32 && SVT <= ppcf128) || (SVT >= v2f32 && SVT <= v2f64); + } + + /// isInteger - Return true if this is an integer, or a vector integer type. + inline bool isInteger() const { + uint32_t SVT = V & SimpleTypeMask; + return (SVT >= FIRST_INTEGER_VALUETYPE && SVT <= LAST_INTEGER_VALUETYPE) || + (SVT >= v8i8 && SVT <= v2i64) || (SVT == iAny && (V & PrecisionMask)); + } + + /// isVector - Return true if this is a vector value type. + inline bool isVector() const { + return (V >= FIRST_VECTOR_VALUETYPE && V <= LAST_VECTOR_VALUETYPE) || + (V & VectorMask); + } + + /// is64BitVector - Return true if this is a 64-bit vector type. + inline bool is64BitVector() const { + return (V==v8i8 || V==v4i16 || V==v2i32 || V==v1i64 || V==v2f32 || + (isExtended() && isVector() && getSizeInBits()==64)); + } - /// MVT::ValueType - This type holds low-level value types. Valid values - /// include any of the values in the SimpleValueType enum, or any value - /// returned from a function in the MVT namespace that has a ValueType - /// return type. Any value type equal to one of the SimpleValueType enum - /// values is a "simple" value type. All other value types are "extended". - /// - /// Note that simple doesn't necessary mean legal for the target machine. - /// All legal value types must be simple, but often there are some simple - /// value types that are not legal. - /// - /// @internal - /// Extended types are either vector types or arbitrary precision integers. - /// Arbitrary precision integers have iAny in the first SimpleTypeBits bits, - /// and the bit-width in the next PrecisionBits bits, offset by minus one. - /// Vector types are encoded by having the first SimpleTypeBits+PrecisionBits - /// bits encode the vector element type (which must be a scalar type, possibly - /// an arbitrary precision integer) and the remaining VectorBits upper bits - /// encode the vector length, offset by one. - /// - /// 31--------------16-----------8-------------0 - /// | Vector length | Precision | Simple type | - /// | | Vector element | - /// - /// Note that the verifier currently requires the top bit to be zero. - - typedef uint32_t ValueType; - - static const int SimpleTypeBits = 8; - static const int PrecisionBits = 8; - static const int VectorBits = 32 - SimpleTypeBits - PrecisionBits; - - static const uint32_t SimpleTypeMask = - (~uint32_t(0) << (32 - SimpleTypeBits)) >> (32 - SimpleTypeBits); - - static const uint32_t PrecisionMask = - ((~uint32_t(0) << VectorBits) >> (32 - PrecisionBits)) << SimpleTypeBits; - - static const uint32_t VectorMask = - (~uint32_t(0) >> (32 - VectorBits)) << (32 - VectorBits); - - static const uint32_t ElementMask = - (~uint32_t(0) << VectorBits) >> VectorBits; - - /// MVT::isExtendedVT - Test if the given ValueType is extended - /// (as opposed to being simple). - static inline bool isExtendedVT(ValueType VT) { - return VT > SimpleTypeMask; - } - - /// MVT::isInteger - Return true if this is an integer, or a vector integer - /// type. - static inline bool isInteger(ValueType VT) { - ValueType SVT = VT & SimpleTypeMask; - return (SVT >= FIRST_INTEGER_VALUETYPE && SVT <= LAST_INTEGER_VALUETYPE) || - (SVT >= v8i8 && SVT <= v2i64) || (SVT == iAny && (VT & PrecisionMask)); - } - - /// MVT::isFloatingPoint - Return true if this is an FP, or a vector FP type. - static inline bool isFloatingPoint(ValueType VT) { - ValueType SVT = VT & SimpleTypeMask; - return (SVT >= f32 && SVT <= ppcf128) || (SVT >= v2f32 && SVT <= v2f64); - } - - /// MVT::isVector - Return true if this is a vector value type. - static inline bool isVector(ValueType VT) { - return (VT >= FIRST_VECTOR_VALUETYPE && VT <= LAST_VECTOR_VALUETYPE) || - (VT & VectorMask); - } - - /// MVT::getVectorElementType - Given a vector type, return the type of - /// each element. - static inline ValueType getVectorElementType(ValueType VT) { - assert(isVector(VT) && "Invalid vector type!"); - switch (VT) { - default: - assert(isExtendedVT(VT) && "Unknown simple vector type!"); - return VT & ElementMask; - case v8i8 : - case v16i8: return i8; - case v4i16: - case v8i16: return i16; - case v2i32: - case v3i32: - case v4i32: return i32; - case v1i64: - case v2i64: return i64; - case v2f32: - case v3f32: - case v4f32: return f32; - case v2f64: return f64; - } - } - - /// MVT::getVectorNumElements - Given a vector type, return the - /// number of elements it contains. - static inline unsigned getVectorNumElements(ValueType VT) { - assert(isVector(VT) && "Invalid vector type!"); - switch (VT) { - default: - assert(isExtendedVT(VT) && "Unknown simple vector type!"); - return ((VT & VectorMask) >> (32 - VectorBits)) - 1; - case v16i8: return 16; - case v8i8 : - case v8i16: return 8; - case v4i16: - case v4i32: - case v4f32: return 4; - case v3i32: - case v3f32: return 3; - case v2i32: - case v2i64: - case v2f32: - case v2f64: return 2; - case v1i64: return 1; - } - } - - /// MVT::getSizeInBits - Return the size of the specified value type - /// in bits. - /// - static inline unsigned getSizeInBits(ValueType VT) { - switch (VT) { - default: - assert(isExtendedVT(VT) && "ValueType has no known size!"); - if (isVector(VT)) - return getSizeInBits(getVectorElementType(VT)) * - getVectorNumElements(VT); - if (isInteger(VT)) - return ((VT & PrecisionMask) >> SimpleTypeBits) + 1; - assert(0 && "Unknown value type!"); - case MVT::i1 : return 1; - case MVT::i8 : return 8; - case MVT::i16 : return 16; - case MVT::f32 : - case MVT::i32 : return 32; - case MVT::f64 : - case MVT::i64 : - case MVT::v8i8: - case MVT::v4i16: - case MVT::v2i32: - case MVT::v1i64: - case MVT::v2f32: return 64; - case MVT::f80 : return 80; - case MVT::v3i32: - case MVT::v3f32: return 96; - case MVT::f128: - case MVT::ppcf128: - case MVT::i128: - case MVT::v16i8: - case MVT::v8i16: - case MVT::v4i32: - case MVT::v2i64: - case MVT::v4f32: - case MVT::v2f64: return 128; - } - } - - /// MVT::getStoreSizeInBits - Return the number of bits overwritten by a - /// store of the specified value type. - /// - static inline unsigned getStoreSizeInBits(ValueType VT) { - return (getSizeInBits(VT) + 7)/8*8; - } - - /// MVT::is64BitVector - Return true if this is a 64-bit vector type. - static inline bool is64BitVector(ValueType VT) { - return (VT==v8i8 || VT==v4i16 || VT==v2i32 || VT==v1i64 || VT==v2f32 || - (isExtendedVT(VT) && isVector(VT) && getSizeInBits(VT)==64)); - } - - /// MVT::is128BitVector - Return true if this is a 128-bit vector type. - static inline bool is128BitVector(ValueType VT) { - return (VT==v16i8 || VT==v8i16 || VT==v4i32 || VT==v2i64 || - VT==v4f32 || VT==v2f64 || - (isExtendedVT(VT) && isVector(VT) && getSizeInBits(VT)==128)); - } - - /// MVT::getIntegerType - Returns the ValueType that represents an integer - /// with the given number of bits. - /// - static inline ValueType getIntegerType(unsigned BitWidth) { - switch (BitWidth) { - default: - break; - case 1: - return MVT::i1; - case 8: - return MVT::i8; - case 16: - return MVT::i16; - case 32: - return MVT::i32; - case 64: - return MVT::i64; - case 128: - return MVT::i128; - } - ValueType Result = iAny | - (((BitWidth - 1) << SimpleTypeBits) & PrecisionMask); - assert(getSizeInBits(Result) == BitWidth && "Bad bit width!"); - return Result; - } - - /// MVT::RoundIntegerType - Rounds the bit-width of the given integer - /// ValueType up to the nearest power of two (and at least to eight), - /// and returns the integer ValueType with that number of bits. - /// - static inline ValueType RoundIntegerType(ValueType VT) { - assert(isInteger(VT) && !isVector(VT) && "Invalid integer type!"); - unsigned BitWidth = getSizeInBits(VT); - if (BitWidth <= 8) - return MVT::i8; - else - return getIntegerType(1 << Log2_32_Ceil(BitWidth)); - } - - /// MVT::getVectorType - Returns the ValueType that represents a vector - /// NumElements in length, where each element is of type VT. - /// - static inline ValueType getVectorType(ValueType VT, unsigned NumElements) { - switch (VT) { - default: - break; - case MVT::i8: - if (NumElements == 8) return MVT::v8i8; - if (NumElements == 16) return MVT::v16i8; - break; - case MVT::i16: - if (NumElements == 4) return MVT::v4i16; - if (NumElements == 8) return MVT::v8i16; - break; - case MVT::i32: - if (NumElements == 2) return MVT::v2i32; - if (NumElements == 3) return MVT::v3i32; - if (NumElements == 4) return MVT::v4i32; - break; - case MVT::i64: - if (NumElements == 1) return MVT::v1i64; - if (NumElements == 2) return MVT::v2i64; - break; - case MVT::f32: - if (NumElements == 2) return MVT::v2f32; - if (NumElements == 3) return MVT::v3f32; - if (NumElements == 4) return MVT::v4f32; - break; - case MVT::f64: - if (NumElements == 2) return MVT::v2f64; - break; - } - // Set the length with the top bit forced to zero (needed by the verifier). - ValueType Result = VT | (((NumElements + 1) << (33 - VectorBits)) >> 1); - assert(getVectorElementType(Result) == VT && - "Bad vector element type!"); - assert(getVectorNumElements(Result) == NumElements && - "Bad vector length!"); - return Result; - } - - /// MVT::getIntVectorWithNumElements - Return any integer vector type that has - /// the specified number of elements. - static inline ValueType getIntVectorWithNumElements(unsigned NumElts) { - switch (NumElts) { - default: return getVectorType(i8, NumElts); - case 1: return v1i64; - case 2: return v2i32; - case 3: return v3i32; - case 4: return v4i16; - case 8: return v8i8; - case 16: return v16i8; - } - } - - - /// MVT::getIntVTBitMask - Return an integer with 1's every place there are - /// bits in the specified integer value type. - static inline uint64_t getIntVTBitMask(ValueType VT) { - assert(isInteger(VT) && !isVector(VT) && "Only applies to int scalars!"); - return ~uint64_t(0UL) >> (64-getSizeInBits(VT)); - } - /// MVT::getIntVTSignBit - Return an integer with a 1 in the position of the - /// sign bit for the specified integer value type. - static inline uint64_t getIntVTSignBit(ValueType VT) { - assert(isInteger(VT) && !isVector(VT) && "Only applies to int scalars!"); - return uint64_t(1UL) << (getSizeInBits(VT)-1); - } - - /// MVT::getValueTypeString - This function returns value type as a string, - /// e.g. "i32". - std::string getValueTypeString(ValueType VT); - - /// MVT::getTypeForValueType - This method returns an LLVM type corresponding - /// to the specified ValueType. For integer types, this returns an unsigned - /// type. Note that this will abort for types that cannot be represented. - const Type *getTypeForValueType(ValueType VT); - - /// MVT::getValueType - Return the value type corresponding to the specified - /// type. This returns all pointers as MVT::iPTR. If HandleUnknown is true, - /// unknown types are returned as Other, otherwise they are invalid. - ValueType getValueType(const Type *Ty, bool HandleUnknown = false); -} + /// is128BitVector - Return true if this is a 128-bit vector type. + inline bool is128BitVector() const { + return (V==v16i8 || V==v8i16 || V==v4i32 || V==v2i64 || + V==v4f32 || V==v2f64 || + (isExtended() && isVector() && getSizeInBits()==128)); + } + + + /// getSimpleVT - Return the SimpleValueType held in the specified + /// simple MVT. + inline SimpleValueType getSimpleVT() const { + assert(isSimple() && "Expected a SimpleValueType!"); + return (SimpleValueType)V; + } + + /// getVectorElementType - Given a vector type, return the type of + /// each element. + inline MVT getVectorElementType() const { + assert(isVector() && "Invalid vector type!"); + switch (V) { + default: { + assert(isExtended() && "Unknown simple vector type!"); + MVT VT; + VT.V = V & ElementMask; + return VT; + } + case v8i8 : + case v16i8: return i8; + case v4i16: + case v8i16: return i16; + case v2i32: + case v3i32: + case v4i32: return i32; + case v1i64: + case v2i64: return i64; + case v2f32: + case v3f32: + case v4f32: return f32; + case v2f64: return f64; + } + } + + /// getVectorNumElements - Given a vector type, return the number of + /// elements it contains. + inline unsigned getVectorNumElements() const { + assert(isVector() && "Invalid vector type!"); + switch (V) { + default: + assert(isExtended() && "Unknown simple vector type!"); + return ((V & VectorMask) >> (32 - VectorBits)) - 1; + case v16i8: return 16; + case v8i8 : + case v8i16: return 8; + case v4i16: + case v4i32: + case v4f32: return 4; + case v3i32: + case v3f32: return 3; + case v2i32: + case v2i64: + case v2f32: + case v2f64: return 2; + case v1i64: return 1; + } + } + + /// getSizeInBits - Return the size of the specified value type in bits. + inline unsigned getSizeInBits() const { + switch (V) { + default: + assert(isExtended() && "MVT has no known size!"); + if (isVector()) + return getVectorElementType().getSizeInBits()*getVectorNumElements(); + if (isInteger()) + return ((V & PrecisionMask) >> SimpleTypeBits) + 1; + assert(false && "Unknown value type!"); + return 0; + case i1 : return 1; + case i8 : return 8; + case i16 : return 16; + case f32 : + case i32 : return 32; + case f64 : + case i64 : + case v8i8: + case v4i16: + case v2i32: + case v1i64: + case v2f32: return 64; + case f80 : return 80; + case v3i32: + case v3f32: return 96; + case f128: + case ppcf128: + case i128: + case v16i8: + case v8i16: + case v4i32: + case v2i64: + case v4f32: + case v2f64: return 128; + } + } + + /// getStoreSizeInBits - Return the number of bits overwritten by a store + /// of the specified value type. + inline unsigned getStoreSizeInBits() const { + return (getSizeInBits() + 7)/8*8; + } + + /// getRoundIntegerType - Rounds the bit-width of the given integer MVT up + /// to the nearest power of two (and at least to eight), and returns the + /// integer MVT with that number of bits. + inline MVT getRoundIntegerType() const { + assert(isInteger() && !isVector() && "Invalid integer type!"); + unsigned BitWidth = getSizeInBits(); + if (BitWidth <= 8) + return i8; + else + return getIntegerVT(1 << Log2_32_Ceil(BitWidth)); + } + + /// getIntegerVTBitMask - Return an integer with 1's every place there are + /// bits in the specified integer value type. FIXME: Should return an apint. + inline uint64_t getIntegerVTBitMask() const { + assert(isInteger() && !isVector() && "Only applies to int scalars!"); + return ~uint64_t(0UL) >> (64-getSizeInBits()); + } + + /// getIntegerVTSignBit - Return an integer with a 1 in the position of the + /// sign bit for the specified integer value type. FIXME: Should return an + /// apint. + inline uint64_t getIntegerVTSignBit() const { + assert(isInteger() && !isVector() && "Only applies to int scalars!"); + return uint64_t(1UL) << (getSizeInBits()-1); + } + + /// getMVTString - This function returns value type as a string, + /// e.g. "i32". + std::string getMVTString() const; + + /// getTypeForMVT - This method returns an LLVM type corresponding to the + /// specified MVT. For integer types, this returns an unsigned type. Note + /// that this will abort for types that cannot be represented. + const Type *getTypeForMVT() const; + + /// getMVT - Return the value type corresponding to the specified type. + /// This returns all pointers as iPTR. If HandleUnknown is true, unknown + /// types are returned as Other, otherwise they are invalid. + static MVT getMVT(const Type *Ty, bool HandleUnknown = false); + }; } // End llvm namespace Modified: llvm/trunk/include/llvm/Target/TargetLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetLowering.h (original) +++ llvm/trunk/include/llvm/Target/TargetLowering.h Fri Jun 6 07:08:01 2008 @@ -90,8 +90,8 @@ bool isBigEndian() const { return !IsLittleEndian; } bool isLittleEndian() const { return IsLittleEndian; } - MVT::ValueType getPointerTy() const { return PointerTy; } - MVT::ValueType getShiftAmountTy() const { return ShiftAmountTy; } + MVT getPointerTy() const { return PointerTy; } + MVT getShiftAmountTy() const { return ShiftAmountTy; } OutOfRangeShiftAmount getShiftAmountFlavor() const {return ShiftAmtHandling; } /// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC @@ -112,7 +112,7 @@ /// getSetCCResultType - Return the ValueType of the result of setcc /// operations. - virtual MVT::ValueType getSetCCResultType(const SDOperand &) const; + virtual MVT getSetCCResultType(const SDOperand &) const; /// getSetCCResultContents - For targets without boolean registers, this flag /// returns information about the contents of the high-bits in the setcc @@ -126,9 +126,9 @@ /// getRegClassFor - Return the register class that should be used for the /// specified value type. This may only be called on legal types. - TargetRegisterClass *getRegClassFor(MVT::ValueType VT) const { - assert(VT < array_lengthof(RegClassForVT)); - TargetRegisterClass *RC = RegClassForVT[VT]; + TargetRegisterClass *getRegClassFor(MVT VT) const { + assert((unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT)); + TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT()]; assert(RC && "This value type is not natively supported!"); return RC; } @@ -136,9 +136,10 @@ /// isTypeLegal - Return true if the target has native support for the /// specified value type. This means that it has a register that directly /// holds it without promotions or expansions. - bool isTypeLegal(MVT::ValueType VT) const { - assert(MVT::isExtendedVT(VT) || VT < array_lengthof(RegClassForVT)); - return !MVT::isExtendedVT(VT) && RegClassForVT[VT] != 0; + bool isTypeLegal(MVT VT) const { + assert(!VT.isSimple() || + (unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT)); + return VT.isSimple() && RegClassForVT[VT.getSimpleVT()] != 0; } class ValueTypeActionImpl { @@ -155,20 +156,23 @@ ValueTypeActions[1] = RHS.ValueTypeActions[1]; } - LegalizeAction getTypeAction(MVT::ValueType VT) const { - if (MVT::isExtendedVT(VT)) { - if (MVT::isVector(VT)) return Expand; - if (MVT::isInteger(VT)) + LegalizeAction getTypeAction(MVT VT) const { + if (VT.isExtended()) { + if (VT.isVector()) return Expand; + if (VT.isInteger()) // First promote to a power-of-two size, then expand if necessary. - return VT == MVT::RoundIntegerType(VT) ? Expand : Promote; + return VT == VT.getRoundIntegerType() ? Expand : Promote; assert(0 && "Unsupported extended type!"); + return Legal; } - assert(VT<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0])); - return (LegalizeAction)((ValueTypeActions[VT>>4] >> ((2*VT) & 31)) & 3); + unsigned I = VT.getSimpleVT(); + assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0])); + return (LegalizeAction)((ValueTypeActions[I>>4] >> ((2*I) & 31)) & 3); } - void setTypeAction(MVT::ValueType VT, LegalizeAction Action) { - assert(VT<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0])); - ValueTypeActions[VT>>4] |= Action << ((VT*2) & 31); + void setTypeAction(MVT VT, LegalizeAction Action) { + unsigned I = VT.getSimpleVT(); + assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0])); + ValueTypeActions[I>>4] |= Action << ((I*2) & 31); } }; @@ -180,7 +184,7 @@ /// it is already legal (return 'Legal') or we need to promote it to a larger /// type (return 'Promote'), or we need to expand it into multiple registers /// of smaller integer type (return 'Expand'). 'Custom' is not an option. - LegalizeAction getTypeAction(MVT::ValueType VT) const { + LegalizeAction getTypeAction(MVT VT) const { return ValueTypeActions.getTypeAction(VT); } @@ -190,37 +194,37 @@ /// than the largest integer register, this contains one step in the expansion /// to get to the smaller register. For illegal floating point types, this /// returns the integer type to transform to. - MVT::ValueType getTypeToTransformTo(MVT::ValueType VT) const { - if (!MVT::isExtendedVT(VT)) { - assert(VT < array_lengthof(TransformToType)); - MVT::ValueType NVT = TransformToType[VT]; + MVT getTypeToTransformTo(MVT VT) const { + if (VT.isSimple()) { + assert((unsigned)VT.getSimpleVT() < array_lengthof(TransformToType)); + MVT NVT = TransformToType[VT.getSimpleVT()]; assert(getTypeAction(NVT) != Promote && "Promote may not follow Expand or Promote"); return NVT; } - if (MVT::isVector(VT)) - return MVT::getVectorType(MVT::getVectorElementType(VT), - MVT::getVectorNumElements(VT) / 2); - if (MVT::isInteger(VT)) { - MVT::ValueType NVT = MVT::RoundIntegerType(VT); + if (VT.isVector()) + return MVT::getVectorVT(VT.getVectorElementType(), + VT.getVectorNumElements() / 2); + if (VT.isInteger()) { + MVT NVT = VT.getRoundIntegerType(); if (NVT == VT) // Size is a power of two - expand to half the size. - return MVT::getIntegerType(MVT::getSizeInBits(VT) / 2); + return MVT::getIntegerVT(VT.getSizeInBits() / 2); else // Promote to a power of two size, avoiding multi-step promotion. return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT; } assert(0 && "Unsupported extended type!"); - return MVT::ValueType(); // Not reached + return MVT(); // Not reached } /// getTypeToExpandTo - For types supported by the target, this is an /// identity function. For types that must be expanded (i.e. integer types /// that are larger than the largest integer register or illegal floating /// point types), this returns the largest legal type it will be expanded to. - MVT::ValueType getTypeToExpandTo(MVT::ValueType VT) const { - assert(!MVT::isVector(VT)); + MVT getTypeToExpandTo(MVT VT) const { + assert(!VT.isVector()); while (true) { switch (getTypeAction(VT)) { case Legal: @@ -245,10 +249,10 @@ /// register. It also returns the VT and quantity of the intermediate values /// before they are promoted/expanded. /// - unsigned getVectorTypeBreakdown(MVT::ValueType VT, - MVT::ValueType &IntermediateVT, + unsigned getVectorTypeBreakdown(MVT VT, + MVT &IntermediateVT, unsigned &NumIntermediates, - MVT::ValueType &RegisterVT) const; + MVT &RegisterVT) const; typedef std::vector::const_iterator legal_fpimm_iterator; legal_fpimm_iterator legal_fpimm_begin() const { @@ -262,7 +266,7 @@ /// support *some* VECTOR_SHUFFLE operations, those with specific masks. /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values /// are assumed to be legal. - virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const { + virtual bool isShuffleMaskLegal(SDOperand Mask, MVT VT) const { return true; } @@ -271,7 +275,7 @@ /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant /// pool entry. virtual bool isVectorClearMaskLegal(const std::vector &BVOps, - MVT::ValueType EVT, + MVT EVT, SelectionDAG &DAG) const { return false; } @@ -280,16 +284,17 @@ /// it is legal, needs to be promoted to a larger size, needs to be /// expanded to some other code sequence, or the target has a custom expander /// for it. - LegalizeAction getOperationAction(unsigned Op, MVT::ValueType VT) const { - if (MVT::isExtendedVT(VT)) return Expand; + LegalizeAction getOperationAction(unsigned Op, MVT VT) const { + if (VT.isExtended()) return Expand; assert(Op < array_lengthof(OpActions) && - VT < sizeof(OpActions[0])*4 && "Table isn't big enough!"); - return (LegalizeAction)((OpActions[Op] >> (2*VT)) & 3); + (unsigned)VT.getSimpleVT() < sizeof(OpActions[0])*4 && + "Table isn't big enough!"); + return (LegalizeAction)((OpActions[Op] >> (2*VT.getSimpleVT())) & 3); } /// isOperationLegal - Return true if the specified operation is legal on this /// target. - bool isOperationLegal(unsigned Op, MVT::ValueType VT) const { + bool isOperationLegal(unsigned Op, MVT VT) const { return getOperationAction(Op, VT) == Legal || getOperationAction(Op, VT) == Custom; } @@ -298,16 +303,17 @@ /// either it is legal, needs to be promoted to a larger size, needs to be /// expanded to some other code sequence, or the target has a custom expander /// for it. - LegalizeAction getLoadXAction(unsigned LType, MVT::ValueType VT) const { + LegalizeAction getLoadXAction(unsigned LType, MVT VT) const { assert(LType < array_lengthof(LoadXActions) && - VT < sizeof(LoadXActions[0])*4 && "Table isn't big enough!"); - return (LegalizeAction)((LoadXActions[LType] >> (2*VT)) & 3); + (unsigned)VT.getSimpleVT() < sizeof(LoadXActions[0])*4 && + "Table isn't big enough!"); + return (LegalizeAction)((LoadXActions[LType] >> (2*VT.getSimpleVT())) & 3); } /// isLoadXLegal - Return true if the specified load with extension is legal /// on this target. - bool isLoadXLegal(unsigned LType, MVT::ValueType VT) const { - return !MVT::isExtendedVT(VT) && + bool isLoadXLegal(unsigned LType, MVT VT) const { + return VT.isSimple() && (getLoadXAction(LType, VT) == Legal || getLoadXAction(LType, VT) == Custom); } @@ -316,17 +322,19 @@ /// treated: either it is legal, needs to be promoted to a larger size, needs /// to be expanded to some other code sequence, or the target has a custom /// expander for it. - LegalizeAction getTruncStoreAction(MVT::ValueType ValVT, - MVT::ValueType MemVT) const { - assert(ValVT < array_lengthof(TruncStoreActions) && - MemVT < sizeof(TruncStoreActions[0])*4 && "Table isn't big enough!"); - return (LegalizeAction)((TruncStoreActions[ValVT] >> (2*MemVT)) & 3); + LegalizeAction getTruncStoreAction(MVT ValVT, + MVT MemVT) const { + assert((unsigned)ValVT.getSimpleVT() < array_lengthof(TruncStoreActions) && + (unsigned)MemVT.getSimpleVT() < sizeof(TruncStoreActions[0])*4 && + "Table isn't big enough!"); + return (LegalizeAction)((TruncStoreActions[ValVT.getSimpleVT()] >> + (2*MemVT.getSimpleVT())) & 3); } /// isTruncStoreLegal - Return true if the specified store with truncation is /// legal on this target. - bool isTruncStoreLegal(MVT::ValueType ValVT, MVT::ValueType MemVT) const { - return !MVT::isExtendedVT(MemVT) && + bool isTruncStoreLegal(MVT ValVT, MVT MemVT) const { + return MemVT.isSimple() && (getTruncStoreAction(ValVT, MemVT) == Legal || getTruncStoreAction(ValVT, MemVT) == Custom); } @@ -336,16 +344,17 @@ /// expanded to some other code sequence, or the target has a custom expander /// for it. LegalizeAction - getIndexedLoadAction(unsigned IdxMode, MVT::ValueType VT) const { + getIndexedLoadAction(unsigned IdxMode, MVT VT) const { assert(IdxMode < array_lengthof(IndexedModeActions[0]) && - VT < sizeof(IndexedModeActions[0][0])*4 && + (unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[0][0])*4 && "Table isn't big enough!"); - return (LegalizeAction)((IndexedModeActions[0][IdxMode] >> (2*VT)) & 3); + return (LegalizeAction)((IndexedModeActions[0][IdxMode] >> + (2*VT.getSimpleVT())) & 3); } /// isIndexedLoadLegal - Return true if the specified indexed load is legal /// on this target. - bool isIndexedLoadLegal(unsigned IdxMode, MVT::ValueType VT) const { + bool isIndexedLoadLegal(unsigned IdxMode, MVT VT) const { return getIndexedLoadAction(IdxMode, VT) == Legal || getIndexedLoadAction(IdxMode, VT) == Custom; } @@ -355,16 +364,17 @@ /// expanded to some other code sequence, or the target has a custom expander /// for it. LegalizeAction - getIndexedStoreAction(unsigned IdxMode, MVT::ValueType VT) const { + getIndexedStoreAction(unsigned IdxMode, MVT VT) const { assert(IdxMode < array_lengthof(IndexedModeActions[1]) && - VT < sizeof(IndexedModeActions[1][0])*4 && + (unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[1][0])*4 && "Table isn't big enough!"); - return (LegalizeAction)((IndexedModeActions[1][IdxMode] >> (2*VT)) & 3); + return (LegalizeAction)((IndexedModeActions[1][IdxMode] >> + (2*VT.getSimpleVT())) & 3); } /// isIndexedStoreLegal - Return true if the specified indexed load is legal /// on this target. - bool isIndexedStoreLegal(unsigned IdxMode, MVT::ValueType VT) const { + bool isIndexedStoreLegal(unsigned IdxMode, MVT VT) const { return getIndexedStoreAction(IdxMode, VT) == Legal || getIndexedStoreAction(IdxMode, VT) == Custom; } @@ -374,50 +384,52 @@ /// expanded to some other code sequence, or the target has a custom expander /// for it. LegalizeAction - getConvertAction(MVT::ValueType FromVT, MVT::ValueType ToVT) const { - assert(FromVT < array_lengthof(ConvertActions) && - ToVT < sizeof(ConvertActions[0])*4 && "Table isn't big enough!"); - return (LegalizeAction)((ConvertActions[FromVT] >> (2*ToVT)) & 3); + getConvertAction(MVT FromVT, MVT ToVT) const { + assert((unsigned)FromVT.getSimpleVT() < array_lengthof(ConvertActions) && + (unsigned)ToVT.getSimpleVT() < sizeof(ConvertActions[0])*4 && + "Table isn't big enough!"); + return (LegalizeAction)((ConvertActions[FromVT.getSimpleVT()] >> + (2*ToVT.getSimpleVT())) & 3); } /// isConvertLegal - Return true if the specified conversion is legal /// on this target. - bool isConvertLegal(MVT::ValueType FromVT, MVT::ValueType ToVT) const { + bool isConvertLegal(MVT FromVT, MVT ToVT) const { return getConvertAction(FromVT, ToVT) == Legal || getConvertAction(FromVT, ToVT) == Custom; } /// getTypeToPromoteTo - If the action for this operation is to promote, this /// method returns the ValueType to promote to. - MVT::ValueType getTypeToPromoteTo(unsigned Op, MVT::ValueType VT) const { + MVT getTypeToPromoteTo(unsigned Op, MVT VT) const { assert(getOperationAction(Op, VT) == Promote && "This operation isn't promoted!"); // See if this has an explicit type specified. - std::map, - MVT::ValueType>::const_iterator PTTI = + std::map, + MVT>::const_iterator PTTI = PromoteToType.find(std::make_pair(Op, VT)); if (PTTI != PromoteToType.end()) return PTTI->second; - - assert((MVT::isInteger(VT) || MVT::isFloatingPoint(VT)) && + + assert((VT.isInteger() || VT.isFloatingPoint()) && "Cannot autopromote this type, add it with AddPromotedToType."); - MVT::ValueType NVT = VT; + MVT NVT = VT; do { - NVT = (MVT::ValueType)(NVT+1); - assert(MVT::isInteger(NVT) == MVT::isInteger(VT) && NVT != MVT::isVoid && + NVT = (MVT::SimpleValueType)(NVT.getSimpleVT()+1); + assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid && "Didn't find type to promote to!"); } while (!isTypeLegal(NVT) || getOperationAction(Op, NVT) == Promote); return NVT; } - /// getValueType - Return the MVT::ValueType corresponding to this LLVM type. + /// getValueType - Return the MVT corresponding to this LLVM type. /// This is fixed by the LLVM operations except for the pointer size. If /// AllowUnknown is true, this will return MVT::Other for types with no MVT /// counterpart (e.g. structs), otherwise it will assert. - MVT::ValueType getValueType(const Type *Ty, bool AllowUnknown = false) const { - MVT::ValueType VT = MVT::getValueType(Ty, AllowUnknown); + MVT getValueType(const Type *Ty, bool AllowUnknown = false) const { + MVT VT = MVT::getMVT(Ty, AllowUnknown); return VT == MVT::iPTR ? PointerTy : VT; } @@ -428,22 +440,22 @@ /// getRegisterType - Return the type of registers that this ValueType will /// eventually require. - MVT::ValueType getRegisterType(MVT::ValueType VT) const { - if (!MVT::isExtendedVT(VT)) { - assert(VT < array_lengthof(RegisterTypeForVT)); - return RegisterTypeForVT[VT]; + MVT getRegisterType(MVT VT) const { + if (VT.isSimple()) { + assert((unsigned)VT.getSimpleVT() < array_lengthof(RegisterTypeForVT)); + return RegisterTypeForVT[VT.getSimpleVT()]; } - if (MVT::isVector(VT)) { - MVT::ValueType VT1, RegisterVT; + if (VT.isVector()) { + MVT VT1, RegisterVT; unsigned NumIntermediates; (void)getVectorTypeBreakdown(VT, VT1, NumIntermediates, RegisterVT); return RegisterVT; } - if (MVT::isInteger(VT)) { + if (VT.isInteger()) { return getRegisterType(getTypeToTransformTo(VT)); } assert(0 && "Unsupported extended type!"); - return MVT::ValueType(); // Not reached + return MVT(); // Not reached } /// getNumRegisters - Return the number of registers that this ValueType will @@ -452,19 +464,19 @@ /// into pieces. For types like i140, which are first promoted then expanded, /// it is the number of registers needed to hold all the bits of the original /// type. For an i140 on a 32 bit machine this means 5 registers. - unsigned getNumRegisters(MVT::ValueType VT) const { - if (!MVT::isExtendedVT(VT)) { - assert(VT < array_lengthof(NumRegistersForVT)); - return NumRegistersForVT[VT]; + unsigned getNumRegisters(MVT VT) const { + if (VT.isSimple()) { + assert((unsigned)VT.getSimpleVT() < array_lengthof(NumRegistersForVT)); + return NumRegistersForVT[VT.getSimpleVT()]; } - if (MVT::isVector(VT)) { - MVT::ValueType VT1, VT2; + if (VT.isVector()) { + MVT VT1, VT2; unsigned NumIntermediates; return getVectorTypeBreakdown(VT, VT1, NumIntermediates, VT2); } - if (MVT::isInteger(VT)) { - unsigned BitWidth = MVT::getSizeInBits(VT); - unsigned RegWidth = MVT::getSizeInBits(getRegisterType(VT)); + if (VT.isInteger()) { + unsigned BitWidth = VT.getSizeInBits(); + unsigned RegWidth = getRegisterType(VT).getSizeInBits(); return (BitWidth + RegWidth - 1) / RegWidth; } assert(0 && "Unsupported extended type!"); @@ -474,7 +486,7 @@ /// ShouldShrinkFPConstant - If true, then instruction selection should /// seek to shrink the FP constant of the specified type to a smaller type /// in order to save space and / or reduce runtime. - virtual bool ShouldShrinkFPConstant(MVT::ValueType VT) const { return true; } + virtual bool ShouldShrinkFPConstant(MVT VT) const { return true; } /// hasTargetDAGCombine - If true, the target has custom DAG combine /// transformations that it can perform for the specified node. @@ -515,8 +527,8 @@ /// and store operations as a result of memset, memcpy, and memmove lowering. /// It returns MVT::iAny if SelectionDAG should be responsible for /// determining it. - virtual MVT::ValueType getOptimalMemOpType(uint64_t Size, unsigned Align, - bool isSrcConst, bool isSrcStr) const { + virtual MVT getOptimalMemOpType(uint64_t Size, unsigned Align, + bool isSrcConst, bool isSrcStr) const { return MVT::iAny; } @@ -687,7 +699,7 @@ /// SimplifySetCC - Try to simplify a setcc built with the specified operands /// and cc. If it is unable to simplify it, return a null SDOperand. - SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, + SDOperand SimplifySetCC(MVT VT, SDOperand N0, SDOperand N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI) const; @@ -729,7 +741,7 @@ /// setShiftAmountType - Describe the type that should be used for shift /// amounts. This type defaults to the pointer type. - void setShiftAmountType(MVT::ValueType VT) { ShiftAmountTy = VT; } + void setShiftAmountType(MVT VT) { ShiftAmountTy = VT; } /// setSetCCResultContents - Specify how the target extends the result of a /// setcc operation in a register. @@ -798,10 +810,10 @@ /// addRegisterClass - Add the specified register class as an available /// regclass for the specified value type. This indicates the selector can /// handle values of that class natively. - void addRegisterClass(MVT::ValueType VT, TargetRegisterClass *RC) { - assert(VT < array_lengthof(RegClassForVT)); + void addRegisterClass(MVT VT, TargetRegisterClass *RC) { + assert((unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT)); AvailableRegClasses.push_back(std::make_pair(VT, RC)); - RegClassForVT[VT] = RC; + RegClassForVT[VT.getSimpleVT()] = RC; } /// computeRegisterProperties - Once all of the register classes are added, @@ -810,77 +822,82 @@ /// setOperationAction - Indicate that the specified operation does not work /// with the specified type and indicate what to do about it. - void setOperationAction(unsigned Op, MVT::ValueType VT, + void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action) { - assert(VT < sizeof(OpActions[0])*4 && Op < array_lengthof(OpActions) && - "Table isn't big enough!"); - OpActions[Op] &= ~(uint64_t(3UL) << VT*2); - OpActions[Op] |= (uint64_t)Action << VT*2; + assert((unsigned)VT.getSimpleVT() < sizeof(OpActions[0])*4 && + Op < array_lengthof(OpActions) && "Table isn't big enough!"); + OpActions[Op] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2); + OpActions[Op] |= (uint64_t)Action << VT.getSimpleVT()*2; } /// setLoadXAction - Indicate that the specified load with extension does not /// work with the with specified type and indicate what to do about it. - void setLoadXAction(unsigned ExtType, MVT::ValueType VT, + void setLoadXAction(unsigned ExtType, MVT VT, LegalizeAction Action) { - assert(VT < sizeof(LoadXActions[0])*4 && + assert((unsigned)VT.getSimpleVT() < sizeof(LoadXActions[0])*4 && ExtType < array_lengthof(LoadXActions) && "Table isn't big enough!"); - LoadXActions[ExtType] &= ~(uint64_t(3UL) << VT*2); - LoadXActions[ExtType] |= (uint64_t)Action << VT*2; + LoadXActions[ExtType] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2); + LoadXActions[ExtType] |= (uint64_t)Action << VT.getSimpleVT()*2; } /// setTruncStoreAction - Indicate that the specified truncating store does /// not work with the with specified type and indicate what to do about it. - void setTruncStoreAction(MVT::ValueType ValVT, MVT::ValueType MemVT, + void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action) { - assert(ValVT < array_lengthof(TruncStoreActions) && - MemVT < sizeof(TruncStoreActions[0])*4 && "Table isn't big enough!"); - TruncStoreActions[ValVT] &= ~(uint64_t(3UL) << MemVT*2); - TruncStoreActions[ValVT] |= (uint64_t)Action << MemVT*2; + assert((unsigned)ValVT.getSimpleVT() < array_lengthof(TruncStoreActions) && + (unsigned)MemVT.getSimpleVT() < sizeof(TruncStoreActions[0])*4 && + "Table isn't big enough!"); + TruncStoreActions[ValVT.getSimpleVT()] &= ~(uint64_t(3UL) << + MemVT.getSimpleVT()*2); + TruncStoreActions[ValVT.getSimpleVT()] |= (uint64_t)Action << + MemVT.getSimpleVT()*2; } /// setIndexedLoadAction - Indicate that the specified indexed load does or /// does not work with the with specified type and indicate what to do abort /// it. NOTE: All indexed mode loads are initialized to Expand in /// TargetLowering.cpp - void setIndexedLoadAction(unsigned IdxMode, MVT::ValueType VT, + void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action) { - assert(VT < sizeof(IndexedModeActions[0])*4 && IdxMode < - array_lengthof(IndexedModeActions[0]) && + assert((unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[0])*4 && + IdxMode < array_lengthof(IndexedModeActions[0]) && "Table isn't big enough!"); - IndexedModeActions[0][IdxMode] &= ~(uint64_t(3UL) << VT*2); - IndexedModeActions[0][IdxMode] |= (uint64_t)Action << VT*2; + IndexedModeActions[0][IdxMode] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2); + IndexedModeActions[0][IdxMode] |= (uint64_t)Action << VT.getSimpleVT()*2; } /// setIndexedStoreAction - Indicate that the specified indexed store does or /// does not work with the with specified type and indicate what to do about /// it. NOTE: All indexed mode stores are initialized to Expand in /// TargetLowering.cpp - void setIndexedStoreAction(unsigned IdxMode, MVT::ValueType VT, + void setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action) { - assert(VT < sizeof(IndexedModeActions[1][0])*4 && + assert((unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[1][0])*4 && IdxMode < array_lengthof(IndexedModeActions[1]) && "Table isn't big enough!"); - IndexedModeActions[1][IdxMode] &= ~(uint64_t(3UL) << VT*2); - IndexedModeActions[1][IdxMode] |= (uint64_t)Action << VT*2; + IndexedModeActions[1][IdxMode] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2); + IndexedModeActions[1][IdxMode] |= (uint64_t)Action << VT.getSimpleVT()*2; } /// setConvertAction - Indicate that the specified conversion does or does /// not work with the with specified type and indicate what to do about it. - void setConvertAction(MVT::ValueType FromVT, MVT::ValueType ToVT, + void setConvertAction(MVT FromVT, MVT ToVT, LegalizeAction Action) { - assert(FromVT < array_lengthof(ConvertActions) && - ToVT < sizeof(ConvertActions[0])*4 && "Table isn't big enough!"); - ConvertActions[FromVT] &= ~(uint64_t(3UL) << ToVT*2); - ConvertActions[FromVT] |= (uint64_t)Action << ToVT*2; + assert((unsigned)FromVT.getSimpleVT() < array_lengthof(ConvertActions) && + (unsigned)ToVT.getSimpleVT() < sizeof(ConvertActions[0])*4 && + "Table isn't big enough!"); + ConvertActions[FromVT.getSimpleVT()] &= ~(uint64_t(3UL) << + ToVT.getSimpleVT()*2); + ConvertActions[FromVT.getSimpleVT()] |= (uint64_t)Action << + ToVT.getSimpleVT()*2; } /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the /// promotion code defaults to trying a larger integer/fp until it can find /// one that works. If that default is insufficient, this method can be used /// by the target to override the default. - void AddPromotedToType(unsigned Opc, MVT::ValueType OrigVT, - MVT::ValueType DestVT) { + void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { PromoteToType[std::make_pair(Opc, OrigVT)] = DestVT; } @@ -1121,7 +1138,7 @@ Value *CallOperandVal; /// ConstraintVT - The ValueType for the operand value. - MVT::ValueType ConstraintVT; + MVT ConstraintVT; AsmOperandInfo(const InlineAsm::ConstraintInfo &info) : InlineAsm::ConstraintInfo(info), @@ -1148,7 +1165,7 @@ /// This should only be used for C_RegisterClass constraints. virtual std::vector getRegClassForInlineAsmConstraint(const std::string &Constraint, - MVT::ValueType VT) const; + MVT VT) const; /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g. /// {edx}), return the register number and the register class for the @@ -1162,13 +1179,13 @@ /// this returns a register number of 0 and a null register class pointer.. virtual std::pair getRegForInlineAsmConstraint(const std::string &Constraint, - MVT::ValueType VT) const; + MVT VT) const; /// LowerXConstraint - try to replace an X constraint, which matches anything, /// with another that has more specific requirements based on the type of the /// corresponding operand. This returns null if there is no replacement to /// make. - virtual const char *LowerXConstraint(MVT::ValueType ConstraintVT) const; + virtual const char *LowerXConstraint(MVT ConstraintVT) const; /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops /// vector. If it is invalid, don't add anything to Ops. @@ -1220,7 +1237,7 @@ return false; } - virtual bool isTruncateFree(MVT::ValueType VT1, MVT::ValueType VT2) const { + virtual bool isTruncateFree(MVT VT1, MVT VT2) const { return false; } @@ -1271,7 +1288,7 @@ /// PointerTy - The type to use for pointers, usually i32 or i64. /// - MVT::ValueType PointerTy; + MVT PointerTy; /// UsesGlobalOffsetTable - True if this target uses a GOT for PIC codegen. /// @@ -1279,7 +1296,7 @@ /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever /// PointerTy is. - MVT::ValueType ShiftAmountTy; + MVT ShiftAmountTy; OutOfRangeShiftAmount ShiftAmtHandling; @@ -1352,14 +1369,14 @@ /// each ValueType the target supports natively. TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE]; unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE]; - MVT::ValueType RegisterTypeForVT[MVT::LAST_VALUETYPE]; + MVT RegisterTypeForVT[MVT::LAST_VALUETYPE]; /// TransformToType - For any value types we are promoting or expanding, this /// contains the value type that we are changing to. For Expanded types, this /// contains one step of the expand (e.g. i64 -> i32), even if there are /// multiple steps required (e.g. i64 -> i16). For types natively supported /// by the system, this holds the same type (e.g. i32 -> i32). - MVT::ValueType TransformToType[MVT::LAST_VALUETYPE]; + MVT TransformToType[MVT::LAST_VALUETYPE]; // Defines the capacity of the TargetLowering::OpActions table static const int OpActionsCapacity = 176; @@ -1396,8 +1413,7 @@ std::vector LegalFPImmediates; - std::vector > AvailableRegClasses; + std::vector > AvailableRegClasses; /// TargetDAGCombineArray - Targets can specify ISD nodes that they would /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(), @@ -1411,7 +1427,7 @@ /// /// Targets add entries to this map with AddPromotedToType(..), clients access /// this with getTypeToPromoteTo(..). - std::map, MVT::ValueType> PromoteToType; + std::map, MVT> PromoteToType; /// LibcallRoutineNames - Stores the name each libcall. /// Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Fri Jun 6 07:08:01 2008 @@ -61,7 +61,7 @@ typedef const unsigned* iterator; typedef const unsigned* const_iterator; - typedef const MVT::ValueType* vt_iterator; + typedef const MVT* vt_iterator; typedef const TargetRegisterClass* const * sc_iterator; private: unsigned ID; @@ -76,7 +76,7 @@ const iterator RegsBegin, RegsEnd; public: TargetRegisterClass(unsigned id, - const MVT::ValueType *vts, + const MVT *vts, const TargetRegisterClass * const *subcs, const TargetRegisterClass * const *supcs, const TargetRegisterClass * const *subregcs, @@ -118,7 +118,7 @@ /// hasType - return true if this TargetRegisterClass has the ValueType vt. /// - bool hasType(MVT::ValueType vt) const { + bool hasType(MVT vt) const { for(int i = 0; VTs[i] != MVT::Other; ++i) if (VTs[i] == vt) return true; @@ -324,7 +324,7 @@ /// register of the given type. If type is MVT::Other, then just return any /// register class the register belongs to. const TargetRegisterClass *getPhysicalRegisterRegClass(unsigned Reg, - MVT::ValueType VT = MVT::Other) const; + MVT VT = MVT::Other) const; /// getAllocatableSet - Returns a bitset indexed by register number /// indicating if a register is allocatable or not. If a register class is Modified: llvm/trunk/lib/CodeGen/SelectionDAG/CallingConvLower.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/CallingConvLower.cpp?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/CallingConvLower.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/CallingConvLower.cpp Fri Jun 6 07:08:01 2008 @@ -32,8 +32,8 @@ // HandleByVal - Allocate a stack slot large enough to pass an argument by // value. The size and alignment information of the argument is encoded in its // parameter attribute. -void CCState::HandleByVal(unsigned ValNo, MVT::ValueType ValVT, - MVT::ValueType LocVT, CCValAssign::LocInfo LocInfo, +void CCState::HandleByVal(unsigned ValNo, MVT ValVT, + MVT LocVT, CCValAssign::LocInfo LocInfo, int MinSize, int MinAlign, ISD::ArgFlagsTy ArgFlags) { unsigned Align = ArgFlags.getByValAlign(); @@ -62,12 +62,12 @@ unsigned NumArgs = TheArgs->getNumValues()-1; for (unsigned i = 0; i != NumArgs; ++i) { - MVT::ValueType ArgVT = TheArgs->getValueType(i); + MVT ArgVT = TheArgs->getValueType(i); ISD::ArgFlagsTy ArgFlags = cast(TheArgs->getOperand(3+i))->getArgFlags(); if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) { cerr << "Formal argument #" << i << " has unhandled type " - << MVT::getValueTypeString(ArgVT) << "\n"; + << ArgVT.getMVTString() << "\n"; abort(); } } @@ -78,12 +78,12 @@ void CCState::AnalyzeReturn(SDNode *TheRet, CCAssignFn Fn) { // Determine which register each value should be copied into. for (unsigned i = 0, e = TheRet->getNumOperands() / 2; i != e; ++i) { - MVT::ValueType VT = TheRet->getOperand(i*2+1).getValueType(); + MVT VT = TheRet->getOperand(i*2+1).getValueType(); ISD::ArgFlagsTy ArgFlags = cast(TheRet->getOperand(i*2+2))->getArgFlags(); if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)){ cerr << "Return operand #" << i << " has unhandled type " - << MVT::getValueTypeString(VT) << "\n"; + << VT.getMVTString() << "\n"; abort(); } } @@ -95,12 +95,12 @@ void CCState::AnalyzeCallOperands(SDNode *TheCall, CCAssignFn Fn) { unsigned NumOps = (TheCall->getNumOperands() - 5) / 2; for (unsigned i = 0; i != NumOps; ++i) { - MVT::ValueType ArgVT = TheCall->getOperand(5+2*i).getValueType(); + MVT ArgVT = TheCall->getOperand(5+2*i).getValueType(); ISD::ArgFlagsTy ArgFlags = cast(TheCall->getOperand(5+2*i+1))->getArgFlags(); if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) { cerr << "Call operand #" << i << " has unhandled type " - << MVT::getValueTypeString(ArgVT) << "\n"; + << ArgVT.getMVTString() << "\n"; abort(); } } @@ -110,10 +110,10 @@ /// incorporating info about the passed values into this state. void CCState::AnalyzeCallResult(SDNode *TheCall, CCAssignFn Fn) { for (unsigned i = 0, e = TheCall->getNumValues() - 1; i != e; ++i) { - MVT::ValueType VT = TheCall->getValueType(i); + MVT VT = TheCall->getValueType(i); if (Fn(i, VT, VT, CCValAssign::Full, ISD::ArgFlagsTy(), *this)) { cerr << "Call result #" << i << " has unhandled type " - << MVT::getValueTypeString(VT) << "\n"; + << VT.getMVTString() << "\n"; abort(); } } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Jun 6 07:08:01 2008 @@ -215,12 +215,12 @@ SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, SDOperand N3, ISD::CondCode CC, bool NotExtCompare = false); - SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, + SDOperand SimplifySetCC(MVT VT, SDOperand N0, SDOperand N1, ISD::CondCode Cond, bool foldBooleans = true); SDOperand SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, unsigned HiOp); - SDOperand CombineConsecutiveLoads(SDNode *N, MVT::ValueType VT); - SDOperand ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT::ValueType); + SDOperand CombineConsecutiveLoads(SDNode *N, MVT VT); + SDOperand ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT); SDOperand BuildSDIV(SDNode *N); SDOperand BuildUDIV(SDNode *N); SDNode *MatchRotate(SDOperand LHS, SDOperand RHS); @@ -482,7 +482,7 @@ } SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){ - MVT::ValueType VT = N0.getValueType(); + MVT VT = N0.getValueType(); // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) if (N0.getOpcode() == Opc && isa(N0.getOperand(1))) { @@ -887,7 +887,7 @@ static SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) { - MVT::ValueType VT = N0.getValueType(); + MVT VT = N0.getValueType(); SDOperand N00 = N0.getOperand(0); SDOperand N01 = N0.getOperand(1); ConstantSDNode *N01C = dyn_cast(N01); @@ -904,7 +904,7 @@ static SDOperand combineSelectAndUse(SDNode *N, SDOperand Slct, SDOperand OtherOp, SelectionDAG &DAG) { - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); unsigned Opc = N->getOpcode(); bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC; SDOperand LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1); @@ -930,8 +930,8 @@ cast(RHS)->isNullValue()) { std::swap(LHS, RHS); SDOperand Op0 = Slct.getOperand(0); - bool isInt = MVT::isInteger(isSlctCC ? Op0.getValueType() - : Op0.getOperand(0).getValueType()); + bool isInt = (isSlctCC ? Op0.getValueType() : + Op0.getOperand(0).getValueType()).isInteger(); CC = ISD::getSetCCInverse(CC, isInt); DoXform = true; InvCC = true; @@ -956,10 +956,10 @@ SDOperand N1 = N->getOperand(1); ConstantSDNode *N0C = dyn_cast(N0); ConstantSDNode *N1C = dyn_cast(N1); - MVT::ValueType VT = N0.getValueType(); + MVT VT = N0.getValueType(); // fold vector ops - if (MVT::isVector(VT)) { + if (VT.isVector()) { SDOperand FoldedVOp = SimplifyVBinOp(N); if (FoldedVOp.Val) return FoldedVOp; } @@ -1001,14 +1001,14 @@ if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) return N1.getOperand(0); - if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0))) + if (!VT.isVector() && SimplifyDemandedBits(SDOperand(N, 0))) return SDOperand(N, 0); // fold (a+b) -> (a|b) iff a and b share no bits. - if (MVT::isInteger(VT) && !MVT::isVector(VT)) { + if (VT.isInteger() && !VT.isVector()) { APInt LHSZero, LHSOne; APInt RHSZero, RHSOne; - APInt Mask = APInt::getAllOnesValue(MVT::getSizeInBits(VT)); + APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); if (LHSZero.getBoolValue()) { DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); @@ -1049,7 +1049,7 @@ SDOperand N1 = N->getOperand(1); ConstantSDNode *N0C = dyn_cast(N0); ConstantSDNode *N1C = dyn_cast(N1); - MVT::ValueType VT = N0.getValueType(); + MVT VT = N0.getValueType(); // If the flag result is dead, turn this into an ADD. if (N->hasNUsesOfValue(0, 1)) @@ -1069,7 +1069,7 @@ // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. APInt LHSZero, LHSOne; APInt RHSZero, RHSOne; - APInt Mask = APInt::getAllOnesValue(MVT::getSizeInBits(VT)); + APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); if (LHSZero.getBoolValue()) { DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); @@ -1091,7 +1091,7 @@ SDOperand CarryIn = N->getOperand(2); ConstantSDNode *N0C = dyn_cast(N0); ConstantSDNode *N1C = dyn_cast(N1); - //MVT::ValueType VT = N0.getValueType(); + //MVT VT = N0.getValueType(); // canonicalize constant to RHS if (N0C && !N1C) { @@ -1115,10 +1115,10 @@ SDOperand N1 = N->getOperand(1); ConstantSDNode *N0C = dyn_cast(N0.Val); ConstantSDNode *N1C = dyn_cast(N1.Val); - MVT::ValueType VT = N0.getValueType(); + MVT VT = N0.getValueType(); // fold vector ops - if (MVT::isVector(VT)) { + if (VT.isVector()) { SDOperand FoldedVOp = SimplifyVBinOp(N); if (FoldedVOp.Val) return FoldedVOp; } @@ -1158,10 +1158,10 @@ SDOperand N1 = N->getOperand(1); ConstantSDNode *N0C = dyn_cast(N0); ConstantSDNode *N1C = dyn_cast(N1); - MVT::ValueType VT = N0.getValueType(); + MVT VT = N0.getValueType(); // fold vector ops - if (MVT::isVector(VT)) { + if (VT.isVector()) { SDOperand FoldedVOp = SimplifyVBinOp(N); if (FoldedVOp.Val) return FoldedVOp; } @@ -1242,10 +1242,10 @@ SDOperand N1 = N->getOperand(1); ConstantSDNode *N0C = dyn_cast(N0.Val); ConstantSDNode *N1C = dyn_cast(N1.Val); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // fold vector ops - if (MVT::isVector(VT)) { + if (VT.isVector()) { SDOperand FoldedVOp = SimplifyVBinOp(N); if (FoldedVOp.Val) return FoldedVOp; } @@ -1261,7 +1261,7 @@ return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); // If we know the sign bits of both operands are zero, strength reduce to a // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 - if (!MVT::isVector(VT)) { + if (!VT.isVector()) { if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); } @@ -1278,12 +1278,12 @@ unsigned lg2 = Log2_64(abs2); // Splat the sign bit into the register SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0, - DAG.getConstant(MVT::getSizeInBits(VT)-1, + DAG.getConstant(VT.getSizeInBits()-1, TLI.getShiftAmountTy())); AddToWorkList(SGN.Val); // Add (N0 < 0) ? abs2 - 1 : 0; SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN, - DAG.getConstant(MVT::getSizeInBits(VT)-lg2, + DAG.getConstant(VT.getSizeInBits()-lg2, TLI.getShiftAmountTy())); SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); AddToWorkList(SRL.Val); @@ -1320,10 +1320,10 @@ SDOperand N1 = N->getOperand(1); ConstantSDNode *N0C = dyn_cast(N0.Val); ConstantSDNode *N1C = dyn_cast(N1.Val); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // fold vector ops - if (MVT::isVector(VT)) { + if (VT.isVector()) { SDOperand FoldedVOp = SimplifyVBinOp(N); if (FoldedVOp.Val) return FoldedVOp; } @@ -1340,7 +1340,7 @@ if (N1.getOpcode() == ISD::SHL) { if (ConstantSDNode *SHC = dyn_cast(N1.getOperand(0))) { if (SHC->getAPIntValue().isPowerOf2()) { - MVT::ValueType ADDVT = N1.getOperand(1).getValueType(); + MVT ADDVT = N1.getOperand(1).getValueType(); SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), DAG.getConstant(SHC->getAPIntValue() .logBase2(), @@ -1371,14 +1371,14 @@ SDOperand N1 = N->getOperand(1); ConstantSDNode *N0C = dyn_cast(N0); ConstantSDNode *N1C = dyn_cast(N1); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // fold (srem c1, c2) -> c1%c2 if (N0C && N1C && !N1C->isNullValue()) return DAG.getNode(ISD::SREM, VT, N0, N1); // If we know the sign bits of both operands are zero, strength reduce to a // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 - if (!MVT::isVector(VT)) { + if (!VT.isVector()) { if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) return DAG.getNode(ISD::UREM, VT, N0, N1); } @@ -1412,7 +1412,7 @@ SDOperand N1 = N->getOperand(1); ConstantSDNode *N0C = dyn_cast(N0); ConstantSDNode *N1C = dyn_cast(N1); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // fold (urem c1, c2) -> c1%c2 if (N0C && N1C && !N1C->isNullValue()) @@ -1427,7 +1427,7 @@ if (SHC->getAPIntValue().isPowerOf2()) { SDOperand Add = DAG.getNode(ISD::ADD, VT, N1, - DAG.getConstant(APInt::getAllOnesValue(MVT::getSizeInBits(VT)), + DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT)); AddToWorkList(Add.Val); return DAG.getNode(ISD::AND, VT, N0, Add); @@ -1462,7 +1462,7 @@ SDOperand N0 = N->getOperand(0); SDOperand N1 = N->getOperand(1); ConstantSDNode *N1C = dyn_cast(N1); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // fold (mulhs x, 0) -> 0 if (N1C && N1C->isNullValue()) @@ -1470,7 +1470,7 @@ // fold (mulhs x, 1) -> (sra x, size(x)-1) if (N1C && N1C->getAPIntValue() == 1) return DAG.getNode(ISD::SRA, N0.getValueType(), N0, - DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1, + DAG.getConstant(N0.getValueType().getSizeInBits()-1, TLI.getShiftAmountTy())); // fold (mulhs x, undef) -> 0 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) @@ -1483,7 +1483,7 @@ SDOperand N0 = N->getOperand(0); SDOperand N1 = N->getOperand(1); ConstantSDNode *N1C = dyn_cast(N1); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // fold (mulhu x, 0) -> 0 if (N1C && N1C->isNullValue()) @@ -1583,7 +1583,7 @@ /// two operands of the same opcode, try to simplify it. SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1); - MVT::ValueType VT = N0.getValueType(); + MVT VT = N0.getValueType(); assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); // For each of OP in AND/OR/XOR: @@ -1624,11 +1624,11 @@ SDOperand LL, LR, RL, RR, CC0, CC1; ConstantSDNode *N0C = dyn_cast(N0); ConstantSDNode *N1C = dyn_cast(N1); - MVT::ValueType VT = N1.getValueType(); - unsigned BitWidth = MVT::getSizeInBits(VT); + MVT VT = N1.getValueType(); + unsigned BitWidth = VT.getSizeInBits(); // fold vector ops - if (MVT::isVector(VT)) { + if (VT.isVector()) { SDOperand FoldedVOp = SimplifyVBinOp(N); if (FoldedVOp.Val) return FoldedVOp; } @@ -1683,7 +1683,7 @@ ISD::CondCode Op1 = cast(CC1)->get(); if (LR == RR && isa(LR) && Op0 == Op1 && - MVT::isInteger(LL.getValueType())) { + LL.getValueType().isInteger()) { // fold (X == 0) & (Y == 0) -> (X|Y == 0) if (cast(LR)->isNullValue() && Op1 == ISD::SETEQ) { SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); @@ -1709,7 +1709,7 @@ std::swap(RL, RR); } if (LL == RL && LR == RR) { - bool isInteger = MVT::isInteger(LL.getValueType()); + bool isInteger = LL.getValueType().isInteger(); ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); if (Result != ISD::SETCC_INVALID) return DAG.getSetCC(N0.getValueType(), LL, LR, Result); @@ -1724,18 +1724,18 @@ // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) // fold (and (sra)) -> (and (srl)) when possible. - if (!MVT::isVector(VT) && + if (!VT.isVector() && SimplifyDemandedBits(SDOperand(N, 0))) return SDOperand(N, 0); // fold (zext_inreg (extload x)) -> (zextload x) if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) { LoadSDNode *LN0 = cast(N0); - MVT::ValueType EVT = LN0->getMemoryVT(); + MVT EVT = LN0->getMemoryVT(); // If we zero all the possible extended bits, then we can turn this into // a zextload if we are running before legalize or the operation is legal. unsigned BitWidth = N1.getValueSizeInBits(); if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, - BitWidth - MVT::getSizeInBits(EVT))) && + BitWidth - EVT.getSizeInBits())) && (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), LN0->getBasePtr(), LN0->getSrcValue(), @@ -1751,12 +1751,12 @@ if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { LoadSDNode *LN0 = cast(N0); - MVT::ValueType EVT = LN0->getMemoryVT(); + MVT EVT = LN0->getMemoryVT(); // If we zero all the possible extended bits, then we can turn this into // a zextload if we are running before legalize or the operation is legal. unsigned BitWidth = N1.getValueSizeInBits(); if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, - BitWidth - MVT::getSizeInBits(EVT))) && + BitWidth - EVT.getSizeInBits())) && (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), LN0->getBasePtr(), LN0->getSrcValue(), @@ -1775,7 +1775,7 @@ LoadSDNode *LN0 = cast(N0); if (LN0->getExtensionType() != ISD::SEXTLOAD && LN0->isUnindexed() && N0.hasOneUse()) { - MVT::ValueType EVT, LoadedVT; + MVT EVT, LoadedVT; if (N1C->getAPIntValue() == 255) EVT = MVT::i8; else if (N1C->getAPIntValue() == 65535) @@ -1788,12 +1788,12 @@ LoadedVT = LN0->getMemoryVT(); if (EVT != MVT::Other && LoadedVT > EVT && (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { - MVT::ValueType PtrType = N0.getOperand(1).getValueType(); + MVT PtrType = N0.getOperand(1).getValueType(); // For big endian targets, we need to add an offset to the pointer to // load the correct bytes. For little endian systems, we merely need to // read fewer bytes from the same pointer. - unsigned LVTStoreBytes = MVT::getStoreSizeInBits(LoadedVT)/8; - unsigned EVTStoreBytes = MVT::getStoreSizeInBits(EVT)/8; + unsigned LVTStoreBytes = LoadedVT.getStoreSizeInBits()/8; + unsigned EVTStoreBytes = EVT.getStoreSizeInBits()/8; unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; unsigned Alignment = LN0->getAlignment(); SDOperand NewPtr = LN0->getBasePtr(); @@ -1823,10 +1823,10 @@ SDOperand LL, LR, RL, RR, CC0, CC1; ConstantSDNode *N0C = dyn_cast(N0); ConstantSDNode *N1C = dyn_cast(N1); - MVT::ValueType VT = N1.getValueType(); + MVT VT = N1.getValueType(); // fold vector ops - if (MVT::isVector(VT)) { + if (VT.isVector()) { SDOperand FoldedVOp = SimplifyVBinOp(N); if (FoldedVOp.Val) return FoldedVOp; } @@ -1868,7 +1868,7 @@ ISD::CondCode Op1 = cast(CC1)->get(); if (LR == RR && isa(LR) && Op0 == Op1 && - MVT::isInteger(LL.getValueType())) { + LL.getValueType().isInteger()) { // fold (X != 0) | (Y != 0) -> (X|Y != 0) // fold (X < 0) | (Y < 0) -> (X|Y < 0) if (cast(LR)->isNullValue() && @@ -1892,7 +1892,7 @@ std::swap(RL, RR); } if (LL == RL && LR == RR) { - bool isInteger = MVT::isInteger(LL.getValueType()); + bool isInteger = LL.getValueType().isInteger(); ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); if (Result != ISD::SETCC_INVALID) return DAG.getSetCC(N0.getValueType(), LL, LR, Result); @@ -1959,7 +1959,7 @@ // a rot[lr]. SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) { // Must be a legal type. Expanded an promoted things won't work with rotates. - MVT::ValueType VT = LHS.getValueType(); + MVT VT = LHS.getValueType(); if (!TLI.isTypeLegal(VT)) return 0; // The target must have at least one rotate flavor. @@ -1991,7 +1991,7 @@ std::swap(LHSMask , RHSMask ); } - unsigned OpSizeInBits = MVT::getSizeInBits(VT); + unsigned OpSizeInBits = VT.getSizeInBits(); SDOperand LHSShiftArg = LHSShift.getOperand(0); SDOperand LHSShiftAmt = LHSShift.getOperand(1); SDOperand RHSShiftAmt = RHSShift.getOperand(1); @@ -2115,10 +2115,10 @@ SDOperand LHS, RHS, CC; ConstantSDNode *N0C = dyn_cast(N0); ConstantSDNode *N1C = dyn_cast(N1); - MVT::ValueType VT = N0.getValueType(); + MVT VT = N0.getValueType(); // fold vector ops - if (MVT::isVector(VT)) { + if (VT.isVector()) { SDOperand FoldedVOp = SimplifyVBinOp(N); if (FoldedVOp.Val) return FoldedVOp; } @@ -2146,7 +2146,7 @@ return RXOR; // fold !(x cc y) -> (x !cc y) if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { - bool isInt = MVT::isInteger(LHS.getValueType()); + bool isInt = LHS.getValueType().isInteger(); ISD::CondCode NotCC = ISD::getSetCCInverse(cast(CC)->get(), isInt); if (N0.getOpcode() == ISD::SETCC) @@ -2205,12 +2205,12 @@ } // fold (xor x, x) -> 0 if (N0 == N1) { - if (!MVT::isVector(VT)) { + if (!VT.isVector()) { return DAG.getConstant(0, VT); } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { // Produce a vector of zeros. - SDOperand El = DAG.getConstant(0, MVT::getVectorElementType(VT)); - std::vector Ops(MVT::getVectorNumElements(VT), El); + SDOperand El = DAG.getConstant(0, VT.getVectorElementType()); + std::vector Ops(VT.getVectorNumElements(), El); return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); } } @@ -2222,7 +2222,7 @@ } // Simplify the expression using non-local knowledge. - if (!MVT::isVector(VT) && + if (!VT.isVector() && SimplifyDemandedBits(SDOperand(N, 0))) return SDOperand(N, 0); @@ -2274,7 +2274,7 @@ !isa(BinOpLHSVal->getOperand(1))) return SDOperand(); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // If this is a signed shift right, and the high bit is modified // by the logical operation, do not perform the transformation. @@ -2305,8 +2305,8 @@ SDOperand N1 = N->getOperand(1); ConstantSDNode *N0C = dyn_cast(N0); ConstantSDNode *N1C = dyn_cast(N1); - MVT::ValueType VT = N0.getValueType(); - unsigned OpSizeInBits = MVT::getSizeInBits(VT); + MVT VT = N0.getValueType(); + unsigned OpSizeInBits = VT.getSizeInBits(); // fold (shl c1, c2) -> c1<getOperand(1); ConstantSDNode *N0C = dyn_cast(N0); ConstantSDNode *N1C = dyn_cast(N1); - MVT::ValueType VT = N0.getValueType(); + MVT VT = N0.getValueType(); // fold (sra c1, c2) -> c1>>c2 if (N0C && N1C) @@ -2376,7 +2376,7 @@ if (N0C && N0C->isAllOnesValue()) return N0; // fold (sra x, c >= size(x)) -> undef - if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT)) + if (N1C && N1C->getValue() >= VT.getSizeInBits()) return DAG.getNode(ISD::UNDEF, VT); // fold (sra x, 0) -> x if (N1C && N1C->isNullValue()) @@ -2384,8 +2384,8 @@ // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports // sext_inreg. if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { - unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue(); - MVT::ValueType EVT; + unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getValue(); + MVT EVT; switch (LowBits) { default: EVT = MVT::Other; break; case 1: EVT = MVT::i1; break; @@ -2402,7 +2402,7 @@ if (N1C && N0.getOpcode() == ISD::SRA) { if (ConstantSDNode *C1 = dyn_cast(N0.getOperand(1))) { unsigned Sum = N1C->getValue() + C1->getValue(); - if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1; + if (Sum >= VT.getSizeInBits()) Sum = VT.getSizeInBits()-1; return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), DAG.getConstant(Sum, N1C->getValueType(0))); } @@ -2418,8 +2418,9 @@ const ConstantSDNode *N01C = dyn_cast(N0.getOperand(1)); if (N01C && N1C) { // Determine what the truncate's result bitsize and type would be. - unsigned VTValSize = MVT::getSizeInBits(VT); - MVT::ValueType TruncVT = MVT::getIntegerType(VTValSize - N1C->getValue()); + unsigned VTValSize = VT.getSizeInBits(); + MVT TruncVT = + MVT::getIntegerVT(VTValSize - N1C->getValue()); // Determine the residual right-shift amount. unsigned ShiftAmt = N1C->getValue() - N01C->getValue(); @@ -2458,8 +2459,8 @@ SDOperand N1 = N->getOperand(1); ConstantSDNode *N0C = dyn_cast(N0); ConstantSDNode *N1C = dyn_cast(N1); - MVT::ValueType VT = N0.getValueType(); - unsigned OpSizeInBits = MVT::getSizeInBits(VT); + MVT VT = N0.getValueType(); + unsigned OpSizeInBits = VT.getSizeInBits(); // fold (srl c1, c2) -> c1 >>u c2 if (N0C && N1C) @@ -2492,8 +2493,8 @@ // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { // Shifting in all undef bits? - MVT::ValueType SmallVT = N0.getOperand(0).getValueType(); - if (N1C->getValue() >= MVT::getSizeInBits(SmallVT)) + MVT SmallVT = N0.getOperand(0).getValueType(); + if (N1C->getValue() >= SmallVT.getSizeInBits()) return DAG.getNode(ISD::UNDEF, VT); SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1); @@ -2503,16 +2504,16 @@ // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign // bit, which is unmodified by sra. - if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) { + if (N1C && N1C->getValue()+1 == VT.getSizeInBits()) { if (N0.getOpcode() == ISD::SRA) return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1); } // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). if (N1C && N0.getOpcode() == ISD::CTLZ && - N1C->getAPIntValue() == Log2_32(MVT::getSizeInBits(VT))) { + N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { APInt KnownZero, KnownOne; - APInt Mask = APInt::getAllOnesValue(MVT::getSizeInBits(VT)); + APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); // If any of the input bits are KnownOne, then the input couldn't be all @@ -2551,7 +2552,7 @@ SDOperand DAGCombiner::visitCTLZ(SDNode *N) { SDOperand N0 = N->getOperand(0); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // fold (ctlz c1) -> c2 if (isa(N0)) @@ -2561,7 +2562,7 @@ SDOperand DAGCombiner::visitCTTZ(SDNode *N) { SDOperand N0 = N->getOperand(0); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // fold (cttz c1) -> c2 if (isa(N0)) @@ -2571,7 +2572,7 @@ SDOperand DAGCombiner::visitCTPOP(SDNode *N) { SDOperand N0 = N->getOperand(0); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // fold (ctpop c1) -> c2 if (isa(N0)) @@ -2586,8 +2587,8 @@ ConstantSDNode *N0C = dyn_cast(N0); ConstantSDNode *N1C = dyn_cast(N1); ConstantSDNode *N2C = dyn_cast(N2); - MVT::ValueType VT = N->getValueType(0); - MVT::ValueType VT0 = N0.getValueType(); + MVT VT = N->getValueType(0); + MVT VT0 = N0.getValueType(); // fold select C, X, X -> X if (N1 == N2) @@ -2599,16 +2600,16 @@ if (N0C && N0C->isNullValue()) return N2; // fold select C, 1, X -> C | X - if (MVT::i1 == VT && N1C && N1C->getAPIntValue() == 1) + if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) return DAG.getNode(ISD::OR, VT, N0, N2); // fold select C, 0, 1 -> ~C - if (MVT::isInteger(VT) && MVT::isInteger(VT0) && + if (VT.isInteger() && VT0.isInteger() && N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { SDOperand XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0)); if (VT == VT0) return XORNode; AddToWorkList(XORNode.Val); - if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(VT0)) + if (VT.getSizeInBits() > VT0.getSizeInBits()) return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode); return DAG.getNode(ISD::TRUNCATE, VT, XORNode); } @@ -2626,13 +2627,13 @@ } // fold select C, X, 0 -> C & X // FIXME: this should check for C type == X type, not i1? - if (MVT::i1 == VT && N2C && N2C->isNullValue()) + if (VT == MVT::i1 && N2C && N2C->isNullValue()) return DAG.getNode(ISD::AND, VT, N0, N1); // fold X ? X : Y --> X ? 1 : Y --> X | Y - if (MVT::i1 == VT && N0 == N1) + if (VT == MVT::i1 && N0 == N1) return DAG.getNode(ISD::OR, VT, N0, N2); // fold X ? Y : X --> X ? Y : 0 --> X & Y - if (MVT::i1 == VT && N0 == N2) + if (VT == MVT::i1 && N0 == N2) return DAG.getNode(ISD::AND, VT, N0, N1); // If we can fold this based on the true/false value, do so. @@ -2766,7 +2767,7 @@ SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { SDOperand N0 = N->getOperand(0); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // fold (sext c1) -> c1 if (isa(N0)) @@ -2790,9 +2791,9 @@ // See if the value being truncated is already sign extended. If so, just // eliminate the trunc/sext pair. SDOperand Op = N0.getOperand(0); - unsigned OpBits = MVT::getSizeInBits(Op.getValueType()); - unsigned MidBits = MVT::getSizeInBits(N0.getValueType()); - unsigned DestBits = MVT::getSizeInBits(VT); + unsigned OpBits = Op.getValueType().getSizeInBits(); + unsigned MidBits = N0.getValueType().getSizeInBits(); + unsigned DestBits = VT.getSizeInBits(); unsigned NumSignBits = DAG.ComputeNumSignBits(Op); if (OpBits == DestBits) { @@ -2866,7 +2867,7 @@ if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { LoadSDNode *LN0 = cast(N0); - MVT::ValueType EVT = LN0->getMemoryVT(); + MVT EVT = LN0->getMemoryVT(); if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) { SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), LN0->getBasePtr(), LN0->getSrcValue(), @@ -2899,7 +2900,7 @@ SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { SDOperand N0 = N->getOperand(0); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // fold (zext c1) -> c1 if (isa(N0)) @@ -2943,7 +2944,7 @@ X = DAG.getNode(ISD::TRUNCATE, VT, X); } APInt Mask = cast(N0.getOperand(1))->getAPIntValue(); - Mask.zext(MVT::getSizeInBits(VT)); + Mask.zext(VT.getSizeInBits()); return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); } @@ -2989,7 +2990,7 @@ if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { LoadSDNode *LN0 = cast(N0); - MVT::ValueType EVT = LN0->getMemoryVT(); + MVT EVT = LN0->getMemoryVT(); SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), LN0->getBasePtr(), LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, @@ -3015,7 +3016,7 @@ SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) { SDOperand N0 = N->getOperand(0); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // fold (aext c1) -> c1 if (isa(N0)) @@ -3060,7 +3061,7 @@ X = DAG.getNode(ISD::TRUNCATE, VT, X); } APInt Mask = cast(N0.getOperand(1))->getAPIntValue(); - Mask.zext(MVT::getSizeInBits(VT)); + Mask.zext(VT.getSizeInBits()); return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); } @@ -3087,7 +3088,7 @@ !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { LoadSDNode *LN0 = cast(N0); - MVT::ValueType EVT = LN0->getMemoryVT(); + MVT EVT = LN0->getMemoryVT(); SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT, LN0->getChain(), LN0->getBasePtr(), LN0->getSrcValue(), @@ -3154,8 +3155,8 @@ unsigned Opc = N->getOpcode(); ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; SDOperand N0 = N->getOperand(0); - MVT::ValueType VT = N->getValueType(0); - MVT::ValueType EVT = N->getValueType(0); + MVT VT = N->getValueType(0); + MVT EVT = N->getValueType(0); // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then // extended to VT. @@ -3166,7 +3167,7 @@ return SDOperand(); } - unsigned EVTBits = MVT::getSizeInBits(EVT); + unsigned EVTBits = EVT.getSizeInBits(); unsigned ShAmt = 0; bool CombineSRL = false; if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { @@ -3175,7 +3176,7 @@ // Is the shift amount a multiple of size of VT? if ((ShAmt & (EVTBits-1)) == 0) { N0 = N0.getOperand(0); - if (MVT::getSizeInBits(N0.getValueType()) <= EVTBits) + if (N0.getValueType().getSizeInBits() <= EVTBits) return SDOperand(); CombineSRL = true; } @@ -3188,15 +3189,15 @@ // that it is already zero extended. // FIXME: This should be reevaluated. VT != MVT::i1) { - assert(MVT::getSizeInBits(N0.getValueType()) > EVTBits && + assert(N0.getValueType().getSizeInBits() > EVTBits && "Cannot truncate to larger type!"); LoadSDNode *LN0 = cast(N0); - MVT::ValueType PtrType = N0.getOperand(1).getValueType(); + MVT PtrType = N0.getOperand(1).getValueType(); // For big endian targets, we need to adjust the offset to the pointer to // load the correct bytes. if (TLI.isBigEndian()) { - unsigned LVTStoreBits = MVT::getStoreSizeInBits(N0.getValueType()); - unsigned EVTStoreBits = MVT::getStoreSizeInBits(EVT); + unsigned LVTStoreBits = N0.getValueType().getStoreSizeInBits(); + unsigned EVTStoreBits = EVT.getStoreSizeInBits(); ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; } uint64_t PtrOff = ShAmt / 8; @@ -3235,17 +3236,17 @@ SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { SDOperand N0 = N->getOperand(0); SDOperand N1 = N->getOperand(1); - MVT::ValueType VT = N->getValueType(0); - MVT::ValueType EVT = cast(N1)->getVT(); - unsigned VTBits = MVT::getSizeInBits(VT); - unsigned EVTBits = MVT::getSizeInBits(EVT); + MVT VT = N->getValueType(0); + MVT EVT = cast(N1)->getVT(); + unsigned VTBits = VT.getSizeInBits(); + unsigned EVTBits = EVT.getSizeInBits(); // fold (sext_in_reg c1) -> c1 if (isa(N0) || N0.getOpcode() == ISD::UNDEF) return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); // If the input is already sign extended, just drop the extension. - if (DAG.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1) + if (DAG.ComputeNumSignBits(N0) >= VT.getSizeInBits()-EVTBits+1) return N0; // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 @@ -3274,11 +3275,11 @@ // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. if (N0.getOpcode() == ISD::SRL) { if (ConstantSDNode *ShAmt = dyn_cast(N0.getOperand(1))) - if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) { + if (ShAmt->getValue()+EVTBits <= VT.getSizeInBits()) { // We can turn this into an SRA iff the input to the SRL is already sign // extended enough. unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); - if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits) + if (VT.getSizeInBits()-(ShAmt->getValue()+EVTBits) < InSignBits) return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1)); } } @@ -3318,7 +3319,7 @@ SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { SDOperand N0 = N->getOperand(0); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // noop truncate if (N0.getValueType() == N->getValueType(0)) @@ -3349,7 +3350,7 @@ // -> trunc y SDOperand Shorter = GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), - MVT::getSizeInBits(VT))); + VT.getSizeInBits())); if (Shorter.Val) return DAG.getNode(ISD::TRUNCATE, VT, Shorter); @@ -3367,22 +3368,22 @@ /// CombineConsecutiveLoads - build_pair (load, load) -> load /// if load locations are consecutive. -SDOperand DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT::ValueType VT) { +SDOperand DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT VT) { assert(N->getOpcode() == ISD::BUILD_PAIR); SDNode *LD1 = getBuildPairElt(N, 0); if (!ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse()) return SDOperand(); - MVT::ValueType LD1VT = LD1->getValueType(0); + MVT LD1VT = LD1->getValueType(0); SDNode *LD2 = getBuildPairElt(N, 1); const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); if (ISD::isNON_EXTLoad(LD2) && LD2->hasOneUse() && - TLI.isConsecutiveLoad(LD2, LD1, MVT::getSizeInBits(LD1VT)/8, 1, MFI)) { + TLI.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1, MFI)) { LoadSDNode *LD = cast(LD1); unsigned Align = LD->getAlignment(); unsigned NewAlign = TLI.getTargetMachine().getTargetData()-> - getABITypeAlignment(MVT::getTypeForValueType(VT)); + getABITypeAlignment(VT.getTypeForMVT()); if ((!AfterLegalize || TLI.isTypeLegal(VT)) && TLI.isOperationLegal(ISD::LOAD, VT) && NewAlign <= Align) return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), @@ -3394,7 +3395,7 @@ SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) { SDOperand N0 = N->getOperand(0); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // If the input is a BUILD_VECTOR with all constant elements, fold this now. // Only do this before legalize, since afterward the target may be depending @@ -3402,7 +3403,7 @@ // First check to see if this is all constant. if (!AfterLegalize && N0.getOpcode() == ISD::BUILD_VECTOR && N0.Val->hasOneUse() && - MVT::isVector(VT)) { + VT.isVector()) { bool isSimple = true; for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) if (N0.getOperand(i).getOpcode() != ISD::UNDEF && @@ -3412,8 +3413,8 @@ break; } - MVT::ValueType DestEltVT = MVT::getVectorElementType(N->getValueType(0)); - assert(!MVT::isVector(DestEltVT) && + MVT DestEltVT = N->getValueType(0).getVectorElementType(); + assert(!DestEltVT.isVector() && "Element type of vector ValueType must not be vector!"); if (isSimple) { return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.Val, DestEltVT); @@ -3435,7 +3436,7 @@ TLI.isOperationLegal(ISD::LOAD, VT)) { LoadSDNode *LN0 = cast(N0); unsigned Align = TLI.getTargetMachine().getTargetData()-> - getABITypeAlignment(MVT::getTypeForValueType(VT)); + getABITypeAlignment(VT.getTypeForMVT()); unsigned OrigAlign = LN0->getAlignment(); if (Align <= OrigAlign) { SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(), @@ -3452,11 +3453,11 @@ // Fold bitconvert(fabs(x)) -> and(bitconvert(x), ~signbit) // This often reduces constant pool loads. if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && - N0.Val->hasOneUse() && MVT::isInteger(VT) && !MVT::isVector(VT)) { + N0.Val->hasOneUse() && VT.isInteger() && !VT.isVector()) { SDOperand NewConv = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); AddToWorkList(NewConv.Val); - APInt SignBit = APInt::getSignBit(MVT::getSizeInBits(VT)); + APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); if (N0.getOpcode() == ISD::FNEG) return DAG.getNode(ISD::XOR, VT, NewConv, DAG.getConstant(SignBit, VT)); assert(N0.getOpcode() == ISD::FABS); @@ -3468,14 +3469,15 @@ // to an fneg or fabs. if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse() && isa(N0.getOperand(0)) && - MVT::isInteger(VT) && !MVT::isVector(VT)) { - unsigned OrigXWidth = MVT::getSizeInBits(N0.getOperand(1).getValueType()); - SDOperand X = DAG.getNode(ISD::BIT_CONVERT, MVT::getIntegerType(OrigXWidth), + VT.isInteger() && !VT.isVector()) { + unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); + SDOperand X = DAG.getNode(ISD::BIT_CONVERT, + MVT::getIntegerVT(OrigXWidth), N0.getOperand(1)); AddToWorkList(X.Val); // If X has a different width than the result/lhs, sext it or truncate it. - unsigned VTWidth = MVT::getSizeInBits(VT); + unsigned VTWidth = VT.getSizeInBits(); if (OrigXWidth < VTWidth) { X = DAG.getNode(ISD::SIGN_EXTEND, VT, X); AddToWorkList(X.Val); @@ -3489,7 +3491,7 @@ AddToWorkList(X.Val); } - APInt SignBit = APInt::getSignBit(MVT::getSizeInBits(VT)); + APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); X = DAG.getNode(ISD::AND, VT, X, DAG.getConstant(SignBit, VT)); AddToWorkList(X.Val); @@ -3511,7 +3513,7 @@ } SDOperand DAGCombiner::visitBUILD_PAIR(SDNode *N) { - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); return CombineConsecutiveLoads(N, VT); } @@ -3519,14 +3521,14 @@ /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the /// destination element value type. SDOperand DAGCombiner:: -ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) { - MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType(); +ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) { + MVT SrcEltVT = BV->getOperand(0).getValueType(); // If this is already the right type, we're done. if (SrcEltVT == DstEltVT) return SDOperand(BV, 0); - unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT); - unsigned DstBitSize = MVT::getSizeInBits(DstEltVT); + unsigned SrcBitSize = SrcEltVT.getSizeInBits(); + unsigned DstBitSize = DstEltVT.getSizeInBits(); // If this is a conversion of N elements of one type to N elements of another // type, convert each element. This handles FP<->INT cases. @@ -3536,29 +3538,28 @@ Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i))); AddToWorkList(Ops.back().Val); } - MVT::ValueType VT = - MVT::getVectorType(DstEltVT, - MVT::getVectorNumElements(BV->getValueType(0))); + MVT VT = MVT::getVectorVT(DstEltVT, + BV->getValueType(0).getVectorNumElements()); return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); } // Otherwise, we're growing or shrinking the elements. To avoid having to // handle annoying details of growing/shrinking FP values, we convert them to // int first. - if (MVT::isFloatingPoint(SrcEltVT)) { + if (SrcEltVT.isFloatingPoint()) { // Convert the input float vector to a int vector where the elements are the // same sizes. assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); - MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64; + MVT IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64; BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).Val; SrcEltVT = IntVT; } // Now we know the input is an integer vector. If the output is a FP type, // convert to integer first, then to FP of the right size. - if (MVT::isFloatingPoint(DstEltVT)) { + if (DstEltVT.isFloatingPoint()) { assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); - MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64; + MVT TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64; SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).Val; // Next, convert to FP elements of the same size. @@ -3567,7 +3568,7 @@ // Okay, we know the src/dst types are both integers of differing types. // Handling growing first. - assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT)); + assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); if (SrcBitSize < DstBitSize) { unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; @@ -3594,7 +3595,7 @@ Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); } - MVT::ValueType VT = MVT::getVectorType(DstEltVT, Ops.size()); + MVT VT = MVT::getVectorVT(DstEltVT, Ops.size()); return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); } @@ -3602,8 +3603,7 @@ // turns into multiple outputs. bool isS2V = ISD::isScalarToVector(BV); unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; - MVT::ValueType VT = MVT::getVectorType(DstEltVT, - NumOutputsPerInput * BV->getNumOperands()); + MVT VT = MVT::getVectorVT(DstEltVT, NumOutputsPerInput*BV->getNumOperands()); SmallVector Ops; for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { @@ -3635,10 +3635,10 @@ SDOperand N1 = N->getOperand(1); ConstantFPSDNode *N0CFP = dyn_cast(N0); ConstantFPSDNode *N1CFP = dyn_cast(N1); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // fold vector ops - if (MVT::isVector(VT)) { + if (VT.isVector()) { SDOperand FoldedVOp = SimplifyVBinOp(N); if (FoldedVOp.Val) return FoldedVOp; } @@ -3672,10 +3672,10 @@ SDOperand N1 = N->getOperand(1); ConstantFPSDNode *N0CFP = dyn_cast(N0); ConstantFPSDNode *N1CFP = dyn_cast(N1); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // fold vector ops - if (MVT::isVector(VT)) { + if (VT.isVector()) { SDOperand FoldedVOp = SimplifyVBinOp(N); if (FoldedVOp.Val) return FoldedVOp; } @@ -3702,10 +3702,10 @@ SDOperand N1 = N->getOperand(1); ConstantFPSDNode *N0CFP = dyn_cast(N0); ConstantFPSDNode *N1CFP = dyn_cast(N1); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // fold vector ops - if (MVT::isVector(VT)) { + if (VT.isVector()) { SDOperand FoldedVOp = SimplifyVBinOp(N); if (FoldedVOp.Val) return FoldedVOp; } @@ -3749,10 +3749,10 @@ SDOperand N1 = N->getOperand(1); ConstantFPSDNode *N0CFP = dyn_cast(N0); ConstantFPSDNode *N1CFP = dyn_cast(N1); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // fold vector ops - if (MVT::isVector(VT)) { + if (VT.isVector()) { SDOperand FoldedVOp = SimplifyVBinOp(N); if (FoldedVOp.Val) return FoldedVOp; } @@ -3782,7 +3782,7 @@ SDOperand N1 = N->getOperand(1); ConstantFPSDNode *N0CFP = dyn_cast(N0); ConstantFPSDNode *N1CFP = dyn_cast(N1); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // fold (frem c1, c2) -> fmod(c1,c2) if (N0CFP && N1CFP && VT != MVT::ppcf128) @@ -3796,7 +3796,7 @@ SDOperand N1 = N->getOperand(1); ConstantFPSDNode *N0CFP = dyn_cast(N0); ConstantFPSDNode *N1CFP = dyn_cast(N1); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1); @@ -3839,7 +3839,7 @@ SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { SDOperand N0 = N->getOperand(0); ConstantSDNode *N0C = dyn_cast(N0); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // fold (sint_to_fp c1) -> c1fp if (N0C && N0.getValueType() != MVT::ppcf128) @@ -3850,7 +3850,7 @@ SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { SDOperand N0 = N->getOperand(0); ConstantSDNode *N0C = dyn_cast(N0); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // fold (uint_to_fp c1) -> c1fp if (N0C && N0.getValueType() != MVT::ppcf128) @@ -3861,7 +3861,7 @@ SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { SDOperand N0 = N->getOperand(0); ConstantFPSDNode *N0CFP = dyn_cast(N0); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // fold (fp_to_sint c1fp) -> c1 if (N0CFP) @@ -3872,7 +3872,7 @@ SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) { SDOperand N0 = N->getOperand(0); ConstantFPSDNode *N0CFP = dyn_cast(N0); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // fold (fp_to_uint c1fp) -> c1 if (N0CFP && VT != MVT::ppcf128) @@ -3884,7 +3884,7 @@ SDOperand N0 = N->getOperand(0); SDOperand N1 = N->getOperand(1); ConstantFPSDNode *N0CFP = dyn_cast(N0); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // fold (fp_round c1fp) -> c1fp if (N0CFP && N0.getValueType() != MVT::ppcf128) @@ -3915,8 +3915,8 @@ SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { SDOperand N0 = N->getOperand(0); - MVT::ValueType VT = N->getValueType(0); - MVT::ValueType EVT = cast(N->getOperand(1))->getVT(); + MVT VT = N->getValueType(0); + MVT EVT = cast(N->getOperand(1))->getVT(); ConstantFPSDNode *N0CFP = dyn_cast(N0); // fold (fp_round_inreg c1fp) -> c1fp @@ -3930,7 +3930,7 @@ SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { SDOperand N0 = N->getOperand(0); ConstantFPSDNode *N0CFP = dyn_cast(N0); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. if (N->hasOneUse() && @@ -3981,13 +3981,13 @@ // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading // constant pool values. if (N0.getOpcode() == ISD::BIT_CONVERT && N0.Val->hasOneUse() && - MVT::isInteger(N0.getOperand(0).getValueType()) && - !MVT::isVector(N0.getOperand(0).getValueType())) { + N0.getOperand(0).getValueType().isInteger() && + !N0.getOperand(0).getValueType().isVector()) { SDOperand Int = N0.getOperand(0); - MVT::ValueType IntVT = Int.getValueType(); - if (MVT::isInteger(IntVT) && !MVT::isVector(IntVT)) { + MVT IntVT = Int.getValueType(); + if (IntVT.isInteger() && !IntVT.isVector()) { Int = DAG.getNode(ISD::XOR, IntVT, Int, - DAG.getConstant(MVT::getIntVTSignBit(IntVT), IntVT)); + DAG.getConstant(IntVT.getIntegerVTSignBit(), IntVT)); AddToWorkList(Int.Val); return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int); } @@ -3999,7 +3999,7 @@ SDOperand DAGCombiner::visitFABS(SDNode *N) { SDOperand N0 = N->getOperand(0); ConstantFPSDNode *N0CFP = dyn_cast(N0); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // fold (fabs c1) -> fabs(c1) if (N0CFP && VT != MVT::ppcf128) @@ -4015,13 +4015,13 @@ // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading // constant pool values. if (N0.getOpcode() == ISD::BIT_CONVERT && N0.Val->hasOneUse() && - MVT::isInteger(N0.getOperand(0).getValueType()) && - !MVT::isVector(N0.getOperand(0).getValueType())) { + N0.getOperand(0).getValueType().isInteger() && + !N0.getOperand(0).getValueType().isVector()) { SDOperand Int = N0.getOperand(0); - MVT::ValueType IntVT = Int.getValueType(); - if (MVT::isInteger(IntVT) && !MVT::isVector(IntVT)) { + MVT IntVT = Int.getValueType(); + if (IntVT.isInteger() && !IntVT.isVector()) { Int = DAG.getNode(ISD::AND, IntVT, Int, - DAG.getConstant(~MVT::getIntVTSignBit(IntVT), IntVT)); + DAG.getConstant(~IntVT.getIntegerVTSignBit(), IntVT)); AddToWorkList(Int.Val); return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int); } @@ -4093,7 +4093,7 @@ bool isLoad = true; SDOperand Ptr; - MVT::ValueType VT; + MVT VT; if (LoadSDNode *LD = dyn_cast(N)) { if (LD->isIndexed()) return false; @@ -4214,7 +4214,7 @@ bool isLoad = true; SDOperand Ptr; - MVT::ValueType VT; + MVT VT; if (LoadSDNode *LD = dyn_cast(N)) { if (LD->isIndexed()) return false; @@ -4513,9 +4513,9 @@ if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && ST->isUnindexed()) { unsigned Align = ST->getAlignment(); - MVT::ValueType SVT = Value.getOperand(0).getValueType(); + MVT SVT = Value.getOperand(0).getValueType(); unsigned OrigAlign = TLI.getTargetMachine().getTargetData()-> - getABITypeAlignment(MVT::getTypeForValueType(SVT)); + getABITypeAlignment(SVT.getTypeForMVT()); if (Align <= OrigAlign && TLI.isOperationLegal(ISD::STORE, SVT)) return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), ST->getSrcValueOffset(), ST->isVolatile(), Align); @@ -4525,7 +4525,7 @@ if (ConstantFPSDNode *CFP = dyn_cast(Value)) { if (Value.getOpcode() != ISD::TargetConstantFP) { SDOperand Tmp; - switch (CFP->getValueType(0)) { + switch (CFP->getValueType(0).getSimpleVT()) { default: assert(0 && "Unknown FP type"); case MVT::f80: // We don't do this for these yet. case MVT::f128: @@ -4610,14 +4610,14 @@ // FIXME: is there such a thing as a truncating indexed store? if (ST->isTruncatingStore() && ST->isUnindexed() && - MVT::isInteger(Value.getValueType())) { + Value.getValueType().isInteger()) { // See if we can simplify the input to this truncstore with knowledge that // only the low bits are being used. For example: // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" SDOperand Shorter = GetDemandedBits(Value, APInt::getLowBitsSet(Value.getValueSizeInBits(), - MVT::getSizeInBits(ST->getMemoryVT()))); + ST->getMemoryVT().getSizeInBits())); AddToWorkList(Value.Val); if (Shorter.Val) return DAG.getTruncStore(Chain, Shorter, Ptr, ST->getSrcValue(), @@ -4629,7 +4629,7 @@ if (SimplifyDemandedBits(Value, APInt::getLowBitsSet( Value.getValueSizeInBits(), - MVT::getSizeInBits(ST->getMemoryVT())))) + ST->getMemoryVT().getSizeInBits()))) return SDOperand(N, 0); } @@ -4695,17 +4695,17 @@ if (isa(EltNo)) { unsigned Elt = cast(EltNo)->getValue(); bool NewLoad = false; - MVT::ValueType VT = InVec.getValueType(); - MVT::ValueType EVT = MVT::getVectorElementType(VT); - MVT::ValueType LVT = EVT; + MVT VT = InVec.getValueType(); + MVT EVT = VT.getVectorElementType(); + MVT LVT = EVT; if (InVec.getOpcode() == ISD::BIT_CONVERT) { - MVT::ValueType BCVT = InVec.getOperand(0).getValueType(); - if (!MVT::isVector(BCVT) - || (MVT::getSizeInBits(EVT) > - MVT::getSizeInBits(MVT::getVectorElementType(BCVT)))) + MVT BCVT = InVec.getOperand(0).getValueType(); + if (!BCVT.isVector() + || (EVT.getSizeInBits() > + BCVT.getVectorElementType().getSizeInBits())) return SDOperand(); InVec = InVec.getOperand(0); - EVT = MVT::getVectorElementType(BCVT); + EVT = BCVT.getVectorElementType(); NewLoad = true; } @@ -4739,7 +4739,7 @@ // Check the resultant load doesn't need a higher alignment than the // original load. unsigned NewAlign = TLI.getTargetMachine().getTargetData()-> - getABITypeAlignment(MVT::getTypeForValueType(LVT)); + getABITypeAlignment(LVT.getTypeForMVT()); if (!TLI.isOperationLegal(ISD::LOAD, LVT) || NewAlign > Align) return SDOperand(); Align = NewAlign; @@ -4747,10 +4747,10 @@ SDOperand NewPtr = LN0->getBasePtr(); if (Elt) { - unsigned PtrOff = MVT::getSizeInBits(LVT) * Elt / 8; - MVT::ValueType PtrType = NewPtr.getValueType(); + unsigned PtrOff = LVT.getSizeInBits() * Elt / 8; + MVT PtrType = NewPtr.getValueType(); if (TLI.isBigEndian()) - PtrOff = MVT::getSizeInBits(VT) / 8 - PtrOff; + PtrOff = VT.getSizeInBits() / 8 - PtrOff; NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, DAG.getConstant(PtrOff, PtrType)); } @@ -4764,9 +4764,9 @@ SDOperand DAGCombiner::visitBUILD_VECTOR(SDNode *N) { unsigned NumInScalars = N->getNumOperands(); - MVT::ValueType VT = N->getValueType(0); - unsigned NumElts = MVT::getVectorNumElements(VT); - MVT::ValueType EltType = MVT::getVectorElementType(VT); + MVT VT = N->getValueType(0); + unsigned NumElts = VT.getVectorNumElements(); + MVT EltType = VT.getVectorElementType(); // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from @@ -4830,7 +4830,7 @@ } // Add count and size info. - MVT::ValueType BuildVecVT = MVT::getVectorType(TLI.getPointerTy(), NumElts); + MVT BuildVecVT = MVT::getVectorVT(TLI.getPointerTy(), NumElts); // Return the new VECTOR_SHUFFLE node. SDOperand Ops[5]; @@ -4933,7 +4933,7 @@ // look though conversions that change things like v4f32 to v2f64. if (V->getOpcode() == ISD::BIT_CONVERT) { SDOperand ConvInput = V->getOperand(0); - if (MVT::getVectorNumElements(ConvInput.getValueType()) == NumElts) + if (ConvInput.getValueType().getVectorNumElements() == NumElts) V = ConvInput.Val; } @@ -5006,7 +5006,7 @@ std::vector IdxOps; unsigned NumOps = RHS.getNumOperands(); unsigned NumElts = NumOps; - MVT::ValueType EVT = MVT::getVectorElementType(RHS.getValueType()); + MVT EVT = RHS.getValueType().getVectorElementType(); for (unsigned i = 0; i != NumElts; ++i) { SDOperand Elt = RHS.getOperand(i); if (!isa(Elt)) @@ -5024,7 +5024,7 @@ return SDOperand(); // Return the new VECTOR_SHUFFLE node. - MVT::ValueType VT = MVT::getVectorType(EVT, NumElts); + MVT VT = MVT::getVectorVT(EVT, NumElts); std::vector Ops; LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS); Ops.push_back(LHS); @@ -5052,10 +5052,10 @@ // things. Simplifying them may result in a loss of legality. if (AfterLegalize) return SDOperand(); - MVT::ValueType VT = N->getValueType(0); - assert(MVT::isVector(VT) && "SimplifyVBinOp only works on vectors!"); + MVT VT = N->getValueType(0); + assert(VT.isVector() && "SimplifyVBinOp only works on vectors!"); - MVT::ValueType EltType = MVT::getVectorElementType(VT); + MVT EltType = VT.getVectorElementType(); SDOperand LHS = N->getOperand(0); SDOperand RHS = N->getOperand(1); SDOperand Shuffle = XformToShuffleWithZero(N); @@ -5095,7 +5095,7 @@ } if (Ops.size() == LHS.getNumOperands()) { - MVT::ValueType VT = LHS.getValueType(); + MVT VT = LHS.getValueType(); return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); } } @@ -5217,7 +5217,7 @@ SDOperand N2, SDOperand N3, ISD::CondCode CC, bool NotExtCompare) { - MVT::ValueType VT = N2.getValueType(); + MVT VT = N2.getValueType(); ConstantSDNode *N1C = dyn_cast(N1.Val); ConstantSDNode *N2C = dyn_cast(N2.Val); ConstantSDNode *N3C = dyn_cast(N3.Val); @@ -5255,18 +5255,18 @@ // Check to see if we can perform the "gzip trick", transforming // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && - MVT::isInteger(N0.getValueType()) && - MVT::isInteger(N2.getValueType()) && + N0.getValueType().isInteger() && + N2.getValueType().isInteger() && (N1C->isNullValue() || // (a < 0) ? b : 0 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 - MVT::ValueType XType = N0.getValueType(); - MVT::ValueType AType = N2.getValueType(); + MVT XType = N0.getValueType(); + MVT AType = N2.getValueType(); if (XType >= AType) { // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a // single-bit constant. if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { unsigned ShCtV = N2C->getAPIntValue().logBase2(); - ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; + ShCtV = XType.getSizeInBits()-ShCtV-1; SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); AddToWorkList(Shift.Val); @@ -5277,7 +5277,7 @@ return DAG.getNode(ISD::AND, AType, Shift, N2); } SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, - DAG.getConstant(MVT::getSizeInBits(XType)-1, + DAG.getConstant(XType.getSizeInBits()-1, TLI.getShiftAmountTy())); AddToWorkList(Shift.Val); if (XType > AType) { @@ -5327,7 +5327,7 @@ // FIXME: Turn all of these into setcc if setcc if setcc is legal // otherwise, go ahead with the folds. if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { - MVT::ValueType XType = N0.getValueType(); + MVT XType = N0.getValueType(); if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(N0))) { SDOperand Res = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC); if (Res.getValueType() != VT) @@ -5340,7 +5340,7 @@ TLI.isOperationLegal(ISD::CTLZ, XType)) { SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); return DAG.getNode(ISD::SRL, XType, Ctlz, - DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)), + DAG.getConstant(Log2_32(XType.getSizeInBits()), TLI.getShiftAmountTy())); } // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) @@ -5351,13 +5351,13 @@ DAG.getConstant(~0ULL, XType)); return DAG.getNode(ISD::SRL, XType, DAG.getNode(ISD::AND, XType, NegN0, NotN0), - DAG.getConstant(MVT::getSizeInBits(XType)-1, + DAG.getConstant(XType.getSizeInBits()-1, TLI.getShiftAmountTy())); } // setgt X, -1 -> xor (srl (X, size(X)-1), 1) if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0, - DAG.getConstant(MVT::getSizeInBits(XType)-1, + DAG.getConstant(XType.getSizeInBits()-1, TLI.getShiftAmountTy())); return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); } @@ -5367,10 +5367,10 @@ // Y = sra (X, size(X)-1); xor (add (X, Y), Y) if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && - N2.getOperand(0) == N1 && MVT::isInteger(N0.getValueType())) { - MVT::ValueType XType = N0.getValueType(); + N2.getOperand(0) == N1 && N0.getValueType().isInteger()) { + MVT XType = N0.getValueType(); SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, - DAG.getConstant(MVT::getSizeInBits(XType)-1, + DAG.getConstant(XType.getSizeInBits()-1, TLI.getShiftAmountTy())); SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); AddToWorkList(Shift.Val); @@ -5382,10 +5382,10 @@ if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { if (ConstantSDNode *SubC = dyn_cast(N3.getOperand(0))) { - MVT::ValueType XType = N0.getValueType(); - if (SubC->isNullValue() && MVT::isInteger(XType)) { + MVT XType = N0.getValueType(); + if (SubC->isNullValue() && XType.isInteger()) { SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, - DAG.getConstant(MVT::getSizeInBits(XType)-1, + DAG.getConstant(XType.getSizeInBits()-1, TLI.getShiftAmountTy())); SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); AddToWorkList(Shift.Val); @@ -5399,7 +5399,7 @@ } /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. -SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0, +SDOperand DAGCombiner::SimplifySetCC(MVT VT, SDOperand N0, SDOperand N1, ISD::CondCode Cond, bool foldBooleans) { TargetLowering::DAGCombinerInfo @@ -5502,13 +5502,13 @@ const Value *&SrcValue, int &SrcValueOffset) { if (LoadSDNode *LD = dyn_cast(N)) { Ptr = LD->getBasePtr(); - Size = MVT::getSizeInBits(LD->getMemoryVT()) >> 3; + Size = LD->getMemoryVT().getSizeInBits() >> 3; SrcValue = LD->getSrcValue(); SrcValueOffset = LD->getSrcValueOffset(); return true; } else if (StoreSDNode *ST = dyn_cast(N)) { Ptr = ST->getBasePtr(); - Size = MVT::getSizeInBits(ST->getMemoryVT()) >> 3; + Size = ST->getMemoryVT().getSizeInBits() >> 3; SrcValue = ST->getSrcValue(); SrcValueOffset = ST->getSrcValueOffset(); } else { Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Jun 6 07:08:01 2008 @@ -128,13 +128,13 @@ /// getTypeAction - Return how we should legalize values of this type, either /// it is already legal or we need to expand it into multiple registers of /// smaller integer type, or we need to promote it to a larger type. - LegalizeAction getTypeAction(MVT::ValueType VT) const { + LegalizeAction getTypeAction(MVT VT) const { return (LegalizeAction)ValueTypeActions.getTypeAction(VT); } /// isTypeLegal - Return true if this type is legal on this target. /// - bool isTypeLegal(MVT::ValueType VT) const { + bool isTypeLegal(MVT VT) const { return getTypeAction(VT) == Legal; } @@ -196,7 +196,7 @@ /// /// If this is a legal shuffle, this method returns the (possibly promoted) /// build_vector Mask. If it's not a legal shuffle, it returns null. - SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const; + SDNode *isShuffleLegal(MVT VT, SDOperand Mask) const; bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, SmallPtrSet &NodesLeadingTo); @@ -205,20 +205,14 @@ SDOperand ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned, SDOperand &Hi); - SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, - SDOperand Source); + SDOperand ExpandIntToFP(bool isSigned, MVT DestTy, SDOperand Source); - SDOperand EmitStackConvert(SDOperand SrcOp, MVT::ValueType SlotVT, - MVT::ValueType DestVT); + SDOperand EmitStackConvert(SDOperand SrcOp, MVT SlotVT, MVT DestVT); SDOperand ExpandBUILD_VECTOR(SDNode *Node); SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node); - SDOperand ExpandLegalINT_TO_FP(bool isSigned, - SDOperand LegalOp, - MVT::ValueType DestVT); - SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT, - bool isSigned); - SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT, - bool isSigned); + SDOperand ExpandLegalINT_TO_FP(bool isSigned, SDOperand LegalOp, MVT DestVT); + SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT DestVT, bool isSigned); + SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT DestVT, bool isSigned); SDOperand ExpandBSWAP(SDOperand Op); SDOperand ExpandBitCount(unsigned Opc, SDOperand Op); @@ -238,8 +232,7 @@ /// /// Note that this will also return true for shuffles that are promoted to a /// different type. -SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT, - SDOperand Mask) const { +SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDOperand Mask) const { switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) { default: return 0; case TargetLowering::Legal: @@ -248,11 +241,11 @@ case TargetLowering::Promote: { // If this is promoted to a different type, convert the shuffle mask and // ask if it is legal in the promoted type! - MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT); + MVT NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT); // If we changed # elements, change the shuffle mask. unsigned NumEltsGrowth = - MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT); + NVT.getVectorNumElements() / VT.getVectorNumElements(); assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); if (NumEltsGrowth > 1) { // Renumber the elements. @@ -458,20 +451,20 @@ /// HandleOp - Legalize, Promote, or Expand the specified operand as /// appropriate for its type. void SelectionDAGLegalize::HandleOp(SDOperand Op) { - MVT::ValueType VT = Op.getValueType(); + MVT VT = Op.getValueType(); switch (getTypeAction(VT)) { default: assert(0 && "Bad type action!"); case Legal: (void)LegalizeOp(Op); break; case Promote: (void)PromoteOp(Op); break; case Expand: - if (!MVT::isVector(VT)) { + if (!VT.isVector()) { // If this is an illegal scalar, expand it into its two component // pieces. SDOperand X, Y; if (Op.getOpcode() == ISD::TargetConstant) break; // Allow illegal target nodes. ExpandOp(Op, X, Y); - } else if (MVT::getVectorNumElements(VT) == 1) { + } else if (VT.getVectorNumElements() == 1) { // If this is an illegal single element vector, convert it to a // scalar operation. (void)ScalarizeVectorOp(Op); @@ -497,7 +490,7 @@ // double. This shrinks FP constants and canonicalizes them for targets where // an FP extending load is the same cost as a normal load (such as on the x87 // fp stack or PPC FP unit). - MVT::ValueType VT = CFP->getValueType(0); + MVT VT = CFP->getValueType(0); ConstantFP *LLVMC = ConstantFP::get(CFP->getValueAPF()); if (!UseCP) { if (VT!=MVT::f64 && VT!=MVT::f32) @@ -506,16 +499,16 @@ (VT == MVT::f64) ? MVT::i64 : MVT::i32); } - MVT::ValueType OrigVT = VT; - MVT::ValueType SVT = VT; + MVT OrigVT = VT; + MVT SVT = VT; while (SVT != MVT::f32) { - SVT = (unsigned)SVT - 1; + SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1); if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) && // Only do this if the target has a native EXTLOAD instruction from // smaller type. TLI.isLoadXLegal(ISD::EXTLOAD, SVT) && TLI.ShouldShrinkFPConstant(OrigVT)) { - const Type *SType = MVT::getTypeForValueType(SVT); + const Type *SType = SVT.getTypeForMVT(); LLVMC = cast(ConstantExpr::getFPTrunc(LLVMC, SType)); VT = SVT; Extend = true; @@ -535,13 +528,13 @@ /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise /// operations. static -SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT, +SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT, SelectionDAG &DAG, TargetLowering &TLI) { - MVT::ValueType VT = Node->getValueType(0); - MVT::ValueType SrcVT = Node->getOperand(1).getValueType(); + MVT VT = Node->getValueType(0); + MVT SrcVT = Node->getOperand(1).getValueType(); assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) && "fcopysign expansion only supported for f32 and f64"); - MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32; + MVT SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32; // First get the sign bit of second operand. SDOperand Mask1 = (SrcVT == MVT::f64) @@ -551,7 +544,7 @@ SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1)); SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1); // Shift right or sign-extend it if the two operands have different types. - int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT); + int SizeDiff = SrcNVT.getSizeInBits() - NVT.getSizeInBits(); if (SizeDiff > 0) { SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit, DAG.getConstant(SizeDiff, TLI.getShiftAmountTy())); @@ -579,17 +572,17 @@ SDOperand Chain = ST->getChain(); SDOperand Ptr = ST->getBasePtr(); SDOperand Val = ST->getValue(); - MVT::ValueType VT = Val.getValueType(); + MVT VT = Val.getValueType(); int Alignment = ST->getAlignment(); int SVOffset = ST->getSrcValueOffset(); - if (MVT::isFloatingPoint(ST->getMemoryVT()) || - MVT::isVector(ST->getMemoryVT())) { + if (ST->getMemoryVT().isFloatingPoint() || + ST->getMemoryVT().isVector()) { // Expand to a bitconvert of the value to the integer type of the // same size, then a (misaligned) int store. - MVT::ValueType intVT; - if (MVT::is128BitVector(VT) || VT == MVT::ppcf128 || VT == MVT::f128) + MVT intVT; + if (VT.is128BitVector() || VT == MVT::ppcf128 || VT == MVT::f128) intVT = MVT::i128; - else if (MVT::is64BitVector(VT) || VT==MVT::f64) + else if (VT.is64BitVector() || VT==MVT::f64) intVT = MVT::i64; else if (VT==MVT::f32) intVT = MVT::i32; @@ -600,12 +593,13 @@ return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(), SVOffset, ST->isVolatile(), Alignment); } - assert(MVT::isInteger(ST->getMemoryVT()) && - !MVT::isVector(ST->getMemoryVT()) && + assert(ST->getMemoryVT().isInteger() && + !ST->getMemoryVT().isVector() && "Unaligned store of unknown type."); // Get the half-size VT - MVT::ValueType NewStoredVT = ST->getMemoryVT() - 1; - int NumBits = MVT::getSizeInBits(NewStoredVT); + MVT NewStoredVT = + (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1); + int NumBits = NewStoredVT.getSizeInBits(); int IncrementSize = NumBits / 8; // Divide the stored value in two parts. @@ -635,16 +629,16 @@ int SVOffset = LD->getSrcValueOffset(); SDOperand Chain = LD->getChain(); SDOperand Ptr = LD->getBasePtr(); - MVT::ValueType VT = LD->getValueType(0); - MVT::ValueType LoadedVT = LD->getMemoryVT(); - if (MVT::isFloatingPoint(VT) || MVT::isVector(VT)) { + MVT VT = LD->getValueType(0); + MVT LoadedVT = LD->getMemoryVT(); + if (VT.isFloatingPoint() || VT.isVector()) { // Expand to a (misaligned) integer load of the same size, // then bitconvert to floating point or vector. - MVT::ValueType intVT; - if (MVT::is128BitVector(LoadedVT) || + MVT intVT; + if (LoadedVT.is128BitVector() || LoadedVT == MVT::ppcf128 || LoadedVT == MVT::f128) intVT = MVT::i128; - else if (MVT::is64BitVector(LoadedVT) || LoadedVT == MVT::f64) + else if (LoadedVT.is64BitVector() || LoadedVT == MVT::f64) intVT = MVT::i64; else if (LoadedVT == MVT::f32) intVT = MVT::i32; @@ -655,21 +649,21 @@ SVOffset, LD->isVolatile(), LD->getAlignment()); SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad); - if (MVT::isFloatingPoint(VT) && LoadedVT != VT) + if (VT.isFloatingPoint() && LoadedVT != VT) Result = DAG.getNode(ISD::FP_EXTEND, VT, Result); SDOperand Ops[] = { Result, Chain }; return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2); } - assert(MVT::isInteger(LoadedVT) && !MVT::isVector(LoadedVT) && + assert(LoadedVT.isInteger() && !LoadedVT.isVector() && "Unaligned load of unsupported type."); // Compute the new VT that is half the size of the old one. This is an // integer MVT. - unsigned NumBits = MVT::getSizeInBits(LoadedVT); - MVT::ValueType NewLoadedVT; - NewLoadedVT = MVT::getIntegerType(NumBits/2); + unsigned NumBits = LoadedVT.getSizeInBits(); + MVT NewLoadedVT; + NewLoadedVT = MVT::getIntegerVT(NumBits/2); NumBits >>= 1; unsigned Alignment = LD->getAlignment(); @@ -717,23 +711,23 @@ /// no way of lowering. "Unroll" the vector, splitting out the scalars and /// operating on each element individually. SDOperand SelectionDAGLegalize::UnrollVectorOp(SDOperand Op) { - MVT::ValueType VT = Op.getValueType(); + MVT VT = Op.getValueType(); assert(isTypeLegal(VT) && "Caller should expand or promote operands that are not legal!"); assert(Op.Val->getNumValues() == 1 && "Can't unroll a vector with multiple results!"); - unsigned NE = MVT::getVectorNumElements(VT); - MVT::ValueType EltVT = MVT::getVectorElementType(VT); + unsigned NE = VT.getVectorNumElements(); + MVT EltVT = VT.getVectorElementType(); SmallVector Scalars; SmallVector Operands(Op.getNumOperands()); for (unsigned i = 0; i != NE; ++i) { for (unsigned j = 0; j != Op.getNumOperands(); ++j) { SDOperand Operand = Op.getOperand(j); - MVT::ValueType OperandVT = Operand.getValueType(); - if (MVT::isVector(OperandVT)) { + MVT OperandVT = Operand.getValueType(); + if (OperandVT.isVector()) { // A vector operand; extract a single element. - MVT::ValueType OperandEltVT = MVT::getVectorElementType(OperandVT); + MVT OperandEltVT = OperandVT.getVectorElementType(); Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, OperandEltVT, Operand, @@ -751,7 +745,7 @@ } /// GetFPLibCall - Return the right libcall for the given floating point type. -static RTLIB::Libcall GetFPLibCall(MVT::ValueType VT, +static RTLIB::Libcall GetFPLibCall(MVT VT, RTLIB::Libcall Call_F32, RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80, @@ -780,10 +774,10 @@ // with a "move to register" or "extload into register" instruction, then // permute it into place, if the idx is a constant and if the idx is // supported by the target. - MVT::ValueType VT = Tmp1.getValueType(); - MVT::ValueType EltVT = MVT::getVectorElementType(VT); - MVT::ValueType IdxVT = Tmp3.getValueType(); - MVT::ValueType PtrVT = TLI.getPointerTy(); + MVT VT = Tmp1.getValueType(); + MVT EltVT = VT.getVectorElementType(); + MVT IdxVT = Tmp3.getValueType(); + MVT PtrVT = TLI.getPointerTy(); SDOperand StackPtr = DAG.CreateStackTemporary(VT); FrameIndexSDNode *StackPtrFI = cast(StackPtr.Val); @@ -798,7 +792,7 @@ unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3); // Add the offset to the index. - unsigned EltSize = MVT::getSizeInBits(EltVT)/8; + unsigned EltSize = EltVT.getSizeInBits()/8; Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr); // Store the scalar value. @@ -911,7 +905,7 @@ Result = DAG.getConstant(0, TLI.getPointerTy()); break; case ISD::FRAME_TO_ARGS_OFFSET: { - MVT::ValueType VT = Node->getValueType(0); + MVT VT = Node->getValueType(0); switch (TLI.getOperationAction(Node->getOpcode(), VT)) { default: assert(0 && "This action is not supported yet!"); case TargetLowering::Custom: @@ -926,7 +920,7 @@ break; case ISD::EXCEPTIONADDR: { Tmp1 = LegalizeOp(Node->getOperand(0)); - MVT::ValueType VT = Node->getValueType(0); + MVT VT = Node->getValueType(0); switch (TLI.getOperationAction(Node->getOpcode(), VT)) { default: assert(0 && "This action is not supported yet!"); case TargetLowering::Expand: { @@ -961,7 +955,7 @@ case ISD::EHSELECTION: { Tmp1 = LegalizeOp(Node->getOperand(0)); Tmp2 = LegalizeOp(Node->getOperand(1)); - MVT::ValueType VT = Node->getValueType(0); + MVT VT = Node->getValueType(0); switch (TLI.getOperationAction(Node->getOpcode(), VT)) { default: assert(0 && "This action is not supported yet!"); case TargetLowering::Expand: { @@ -994,7 +988,7 @@ AddLegalizedOperand(Op.getValue(1), Tmp2); return Op.ResNo ? Tmp2 : Tmp1; case ISD::EH_RETURN: { - MVT::ValueType VT = Node->getValueType(0); + MVT VT = Node->getValueType(0); // The only "good" option for this node is to custom lower it. switch (TLI.getOperationAction(Node->getOpcode(), VT)) { default: assert(0 && "This action is not supported at all!"); @@ -1039,14 +1033,14 @@ AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); return Result.getValue(Op.ResNo); case ISD::UNDEF: { - MVT::ValueType VT = Op.getValueType(); + MVT VT = Op.getValueType(); switch (TLI.getOperationAction(ISD::UNDEF, VT)) { default: assert(0 && "This action is not supported yet!"); case TargetLowering::Expand: - if (MVT::isInteger(VT)) + if (VT.isInteger()) Result = DAG.getConstant(0, VT); - else if (MVT::isFloatingPoint(VT)) - Result = DAG.getConstantFP(APFloat(APInt(MVT::getSizeInBits(VT), 0)), + else if (VT.isFloatingPoint()) + Result = DAG.getConstantFP(APFloat(APInt(VT.getSizeInBits(), 0)), VT); else assert(0 && "Unknown value type!"); @@ -1454,13 +1448,14 @@ // SCALAR_TO_VECTOR requires that the type of the value being inserted // match the element type of the vector being created. if (Tmp2.getValueType() == - MVT::getVectorElementType(Op.getValueType())) { + Op.getValueType().getVectorElementType()) { SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, Tmp1.getValueType(), Tmp2); - unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType()); - MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts); - MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT); + unsigned NumElts = Tmp1.getValueType().getVectorNumElements(); + MVT ShufMaskVT = + MVT::getIntVectorWithNumElements(NumElts); + MVT ShufMaskEltVT = ShufMaskVT.getVectorElementType(); // We generate a shuffle of InVec and ScVec, so the shuffle mask // should be 0,1,2,3,4,5... with the appropriate element replaced with @@ -1531,9 +1526,9 @@ } // FALLTHROUGH case TargetLowering::Expand: { - MVT::ValueType VT = Node->getValueType(0); - MVT::ValueType EltVT = MVT::getVectorElementType(VT); - MVT::ValueType PtrVT = TLI.getPointerTy(); + MVT VT = Node->getValueType(0); + MVT EltVT = VT.getVectorElementType(); + MVT PtrVT = TLI.getPointerTy(); SDOperand Mask = Node->getOperand(2); unsigned NumElems = Mask.getNumOperands(); SmallVector Ops; @@ -1557,8 +1552,8 @@ } case TargetLowering::Promote: { // Change base type to a different vector type. - MVT::ValueType OVT = Node->getValueType(0); - MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); + MVT OVT = Node->getValueType(0); + MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); // Cast the two input vectors. Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); @@ -1679,7 +1674,7 @@ AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); return Result.getValue(Op.ResNo); case ISD::DYNAMIC_STACKALLOC: { - MVT::ValueType VT = Node->getValueType(0); + MVT VT = Node->getValueType(0); Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. @@ -1820,7 +1815,7 @@ SDOperand Table = Result.getOperand(1); SDOperand Index = Result.getOperand(2); - MVT::ValueType PTy = TLI.getPointerTy(); + MVT PTy = TLI.getPointerTy(); MachineFunction &MF = DAG.getMachineFunction(); unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize(); Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy)); @@ -1939,7 +1934,7 @@ ISD::LoadExtType ExtType = LD->getExtensionType(); if (ExtType == ISD::NON_EXTLOAD) { - MVT::ValueType VT = Node->getValueType(0); + MVT VT = Node->getValueType(0); Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); Tmp3 = Result.getValue(0); Tmp4 = Result.getValue(1); @@ -1951,7 +1946,7 @@ // expand it. if (!TLI.allowsUnalignedMemoryAccesses()) { unsigned ABIAlignment = TLI.getTargetData()-> - getABITypeAlignment(MVT::getTypeForValueType(LD->getMemoryVT())); + getABITypeAlignment(LD->getMemoryVT().getTypeForMVT()); if (LD->getAlignment() < ABIAlignment){ Result = ExpandUnalignedLoad(cast(Result.Val), DAG, TLI); @@ -1971,9 +1966,9 @@ break; case TargetLowering::Promote: { // Only promote a load of vector type to another. - assert(MVT::isVector(VT) && "Cannot promote this load!"); + assert(VT.isVector() && "Cannot promote this load!"); // Change base type to a different vector type. - MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); + MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(), LD->getSrcValueOffset(), @@ -1989,13 +1984,13 @@ AddLegalizedOperand(SDOperand(Node, 1), Tmp4); return Op.ResNo ? Tmp4 : Tmp3; } else { - MVT::ValueType SrcVT = LD->getMemoryVT(); - unsigned SrcWidth = MVT::getSizeInBits(SrcVT); + MVT SrcVT = LD->getMemoryVT(); + unsigned SrcWidth = SrcVT.getSizeInBits(); int SVOffset = LD->getSrcValueOffset(); unsigned Alignment = LD->getAlignment(); bool isVolatile = LD->isVolatile(); - if (SrcWidth != MVT::getStoreSizeInBits(SrcVT) && + if (SrcWidth != SrcVT.getStoreSizeInBits() && // Some targets pretend to have an i1 loading operation, and actually // load an i8. This trick is correct for ZEXTLOAD because the top 7 // bits are guaranteed to be zero; it helps the optimizers understand @@ -2007,8 +2002,8 @@ TLI.getLoadXAction(ExtType, MVT::i1) == TargetLowering::Promote)) { // Promote to a byte-sized load if not loading an integral number of // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24. - unsigned NewWidth = MVT::getStoreSizeInBits(SrcVT); - MVT::ValueType NVT = MVT::getIntegerType(NewWidth); + unsigned NewWidth = SrcVT.getStoreSizeInBits(); + MVT NVT = MVT::getIntegerVT(NewWidth); SDOperand Ch; // The extra bits are guaranteed to be zero, since we stored them that @@ -2036,7 +2031,7 @@ Tmp2 = LegalizeOp(Ch); } else if (SrcWidth & (SrcWidth - 1)) { // If not loading a power-of-2 number of bits, expand as two loads. - assert(MVT::isExtendedVT(SrcVT) && !MVT::isVector(SrcVT) && + assert(SrcVT.isExtended() && !SrcVT.isVector() && "Unsupported extload!"); unsigned RoundWidth = 1 << Log2_32(SrcWidth); assert(RoundWidth < SrcWidth); @@ -2044,8 +2039,8 @@ assert(ExtraWidth < RoundWidth); assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && "Load size not an integral number of bytes!"); - MVT::ValueType RoundVT = MVT::getIntegerType(RoundWidth); - MVT::ValueType ExtraVT = MVT::getIntegerType(ExtraWidth); + MVT RoundVT = MVT::getIntegerVT(RoundWidth); + MVT ExtraVT = MVT::getIntegerVT(ExtraWidth); SDOperand Lo, Hi, Ch; unsigned IncrementSize; @@ -2130,7 +2125,7 @@ // expand it. if (!TLI.allowsUnalignedMemoryAccesses()) { unsigned ABIAlignment = TLI.getTargetData()-> - getABITypeAlignment(MVT::getTypeForValueType(LD->getMemoryVT())); + getABITypeAlignment(LD->getMemoryVT().getTypeForMVT()); if (LD->getAlignment() < ABIAlignment){ Result = ExpandUnalignedLoad(cast(Result.Val), DAG, TLI); @@ -2180,14 +2175,14 @@ } } case ISD::EXTRACT_ELEMENT: { - MVT::ValueType OpTy = Node->getOperand(0).getValueType(); + MVT OpTy = Node->getOperand(0).getValueType(); switch (getTypeAction(OpTy)) { default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); case Legal: if (cast(Node->getOperand(1))->getValue()) { // 1 -> Hi Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), - DAG.getConstant(MVT::getSizeInBits(OpTy)/2, + DAG.getConstant(OpTy.getSizeInBits()/2, TLI.getShiftAmountTy())); Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); } else { @@ -2252,7 +2247,7 @@ Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3); break; case Expand: - if (!MVT::isVector(Tmp2.getValueType())) { + if (!Tmp2.getValueType().isVector()) { SDOperand Lo, Hi; ExpandOp(Tmp2, Lo, Hi); @@ -2268,12 +2263,12 @@ } else { SDNode *InVal = Tmp2.Val; int InIx = Tmp2.ResNo; - unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx)); - MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx)); + unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements(); + MVT EVT = InVal->getValueType(InIx).getVectorElementType(); // Figure out if there is a simple type corresponding to this Vector // type. If so, convert to the vector type. - MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); + MVT TVT = MVT::getVectorVT(EVT, NumElems); if (TLI.isTypeLegal(TVT)) { // Turn this into a return of the vector type. Tmp2 = LegalizeOp(Tmp2); @@ -2321,7 +2316,7 @@ break; case Expand: { SDOperand Lo, Hi; - assert(!MVT::isExtendedVT(Node->getOperand(i).getValueType()) && + assert(!Node->getOperand(i).getValueType().isExtended() && "FIXME: TODO: implement returning non-legal vector types!"); ExpandOp(Node->getOperand(i), Lo, Hi); NewValues.push_back(Lo); @@ -2417,7 +2412,7 @@ Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, ST->getOffset()); - MVT::ValueType VT = Tmp3.getValueType(); + MVT VT = Tmp3.getValueType(); switch (TLI.getOperationAction(ISD::STORE, VT)) { default: assert(0 && "This action is not supported yet!"); case TargetLowering::Legal: @@ -2425,7 +2420,7 @@ // expand it. if (!TLI.allowsUnalignedMemoryAccesses()) { unsigned ABIAlignment = TLI.getTargetData()-> - getABITypeAlignment(MVT::getTypeForValueType(ST->getMemoryVT())); + getABITypeAlignment(ST->getMemoryVT().getTypeForMVT()); if (ST->getAlignment() < ABIAlignment) Result = ExpandUnalignedStore(cast(Result.Val), DAG, TLI); @@ -2436,7 +2431,7 @@ if (Tmp1.Val) Result = Tmp1; break; case TargetLowering::Promote: - assert(MVT::isVector(VT) && "Unknown legal promote case!"); + assert(VT.isVector() && "Unknown legal promote case!"); Tmp3 = DAG.getNode(ISD::BIT_CONVERT, TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); Result = DAG.getStore(Tmp1, Tmp3, Tmp2, @@ -2461,16 +2456,16 @@ // If this is a vector type, then we have to calculate the increment as // the product of the element size in bytes, and the number of elements // in the high half of the vector. - if (MVT::isVector(ST->getValue().getValueType())) { + if (ST->getValue().getValueType().isVector()) { SDNode *InVal = ST->getValue().Val; int InIx = ST->getValue().ResNo; - MVT::ValueType InVT = InVal->getValueType(InIx); - unsigned NumElems = MVT::getVectorNumElements(InVT); - MVT::ValueType EVT = MVT::getVectorElementType(InVT); + MVT InVT = InVal->getValueType(InIx); + unsigned NumElems = InVT.getVectorNumElements(); + MVT EVT = InVT.getVectorElementType(); // Figure out if there is a simple type corresponding to this Vector // type. If so, convert to the vector type. - MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); + MVT TVT = MVT::getVectorVT(EVT, NumElems); if (TLI.isTypeLegal(TVT)) { // Turn this into a normal store of the vector type. Tmp3 = LegalizeOp(ST->getValue()); @@ -2489,12 +2484,12 @@ break; } else { SplitVectorOp(ST->getValue(), Lo, Hi); - IncrementSize = MVT::getVectorNumElements(Lo.Val->getValueType(0)) * - MVT::getSizeInBits(EVT)/8; + IncrementSize = Lo.Val->getValueType(0).getVectorNumElements() * + EVT.getSizeInBits()/8; } } else { ExpandOp(ST->getValue(), Lo, Hi); - IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0; + IncrementSize = Hi.Val ? Hi.getValueType().getSizeInBits()/8 : 0; if (TLI.isBigEndian()) std::swap(Lo, Hi); @@ -2537,20 +2532,20 @@ SVOffset, MVT::i8, isVolatile, Alignment); } - MVT::ValueType StVT = ST->getMemoryVT(); - unsigned StWidth = MVT::getSizeInBits(StVT); + MVT StVT = ST->getMemoryVT(); + unsigned StWidth = StVT.getSizeInBits(); - if (StWidth != MVT::getStoreSizeInBits(StVT)) { + if (StWidth != StVT.getStoreSizeInBits()) { // Promote to a byte-sized store with upper bits zero if not // storing an integral number of bytes. For example, promote // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) - MVT::ValueType NVT = MVT::getIntegerType(MVT::getStoreSizeInBits(StVT)); + MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits()); Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT); Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset, NVT, isVolatile, Alignment); } else if (StWidth & (StWidth - 1)) { // If not storing a power-of-2 number of bits, expand as two stores. - assert(MVT::isExtendedVT(StVT) && !MVT::isVector(StVT) && + assert(StVT.isExtended() && !StVT.isVector() && "Unsupported truncstore!"); unsigned RoundWidth = 1 << Log2_32(StWidth); assert(RoundWidth < StWidth); @@ -2558,8 +2553,8 @@ assert(ExtraWidth < RoundWidth); assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && "Store size not an integral number of bytes!"); - MVT::ValueType RoundVT = MVT::getIntegerType(RoundWidth); - MVT::ValueType ExtraVT = MVT::getIntegerType(ExtraWidth); + MVT RoundVT = MVT::getIntegerVT(RoundWidth); + MVT ExtraVT = MVT::getIntegerVT(ExtraWidth); SDOperand Lo, Hi; unsigned IncrementSize; @@ -2612,7 +2607,7 @@ // expand it. if (!TLI.allowsUnalignedMemoryAccesses()) { unsigned ABIAlignment = TLI.getTargetData()-> - getABITypeAlignment(MVT::getTypeForValueType(ST->getMemoryVT())); + getABITypeAlignment(ST->getMemoryVT().getTypeForMVT()); if (ST->getAlignment() < ABIAlignment) Result = ExpandUnalignedStore(cast(Result.Val), DAG, TLI); @@ -2761,13 +2756,13 @@ } break; case TargetLowering::Promote: { - MVT::ValueType NVT = + MVT NVT = TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); unsigned ExtOp, TruncOp; - if (MVT::isVector(Tmp2.getValueType())) { + if (Tmp2.getValueType().isVector()) { ExtOp = ISD::BIT_CONVERT; TruncOp = ISD::BIT_CONVERT; - } else if (MVT::isInteger(Tmp2.getValueType())) { + } else if (Tmp2.getValueType().isInteger()) { ExtOp = ISD::ANY_EXTEND; TruncOp = ISD::TRUNCATE; } else { @@ -2847,23 +2842,23 @@ // First step, figure out the appropriate operation to use. // Allow SETCC to not be supported for all legal data types // Mostly this targets FP - MVT::ValueType NewInTy = Node->getOperand(0).getValueType(); - MVT::ValueType OldVT = NewInTy; OldVT = OldVT; + MVT NewInTy = Node->getOperand(0).getValueType(); + MVT OldVT = NewInTy; OldVT = OldVT; // Scan for the appropriate larger type to use. while (1) { - NewInTy = (MVT::ValueType)(NewInTy+1); + NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1); - assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) && + assert(NewInTy.isInteger() == OldVT.isInteger() && "Fell off of the edge of the integer world"); - assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) && + assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() && "Fell off of the edge of the floating point world"); // If the target supports SETCC of this type, use it. if (TLI.isOperationLegal(ISD::SETCC, NewInTy)) break; } - if (MVT::isInteger(NewInTy)) + if (NewInTy.isInteger()) assert(0 && "Cannot promote Legal Integer SETCC yet"); else { Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1); @@ -2878,7 +2873,7 @@ case TargetLowering::Expand: // Expand a setcc node into a select_cc of the same condition, lhs, and // rhs that selects between const 1 (true) and const 0 (false). - MVT::ValueType VT = Node->getValueType(0); + MVT VT = Node->getValueType(0); Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3); @@ -2983,7 +2978,7 @@ if (Tmp1.Val) Result = Tmp1; break; case TargetLowering::Expand: { - MVT::ValueType VT = Op.getValueType(); + MVT VT = Op.getValueType(); // See if multiply or divide can be lowered using two-result operations. SDVTList VTs = DAG.getVTList(VT, VT); @@ -3056,7 +3051,7 @@ break; } - assert(MVT::isVector(Node->getValueType(0)) && + assert(Node->getValueType(0).isVector() && "Cannot expand this binary operator!"); // Expand the operation into a bunch of nasty scalar code. Result = LegalizeOp(UnrollVectorOp(Op)); @@ -3068,9 +3063,9 @@ case ISD::AND: case ISD::OR: case ISD::XOR: { - MVT::ValueType OVT = Node->getValueType(0); - MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); - assert(MVT::isVector(OVT) && "Cannot promote this BinOp!"); + MVT OVT = Node->getValueType(0); + MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); + assert(OVT.isVector() && "Cannot promote this BinOp!"); // Bit convert each of the values to the new type. Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); @@ -3128,7 +3123,7 @@ TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) == TargetLowering::Legal) { // Get the sign bit of the RHS. - MVT::ValueType IVT = + MVT IVT = Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64; SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2); SignBit = DAG.getSetCC(TLI.getSetCCResultType(SignBit), @@ -3146,7 +3141,7 @@ } // Otherwise, do bitwise ops! - MVT::ValueType NVT = + MVT NVT = Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64; Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result); @@ -3180,7 +3175,7 @@ return Result; case ISD::BUILD_PAIR: { - MVT::ValueType PairTy = Node->getValueType(0); + MVT PairTy = Node->getValueType(0); // TODO: handle the case where the Lo and Hi operands are not of legal type Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi @@ -3196,7 +3191,7 @@ Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, - DAG.getConstant(MVT::getSizeInBits(PairTy)/2, + DAG.getConstant(PairTy.getSizeInBits()/2, TLI.getShiftAmountTy())); Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2); break; @@ -3225,7 +3220,7 @@ case TargetLowering::Expand: { unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; bool isSigned = DivOpc == ISD::SDIV; - MVT::ValueType VT = Node->getValueType(0); + MVT VT = Node->getValueType(0); // See if remainder can be lowered using two-result operations. SDVTList VTs = DAG.getVTList(VT, VT); @@ -3240,14 +3235,14 @@ break; } - if (MVT::isInteger(VT)) { + if (VT.isInteger()) { if (TLI.getOperationAction(DivOpc, VT) == TargetLowering::Legal) { // X % Y -> X-X/Y*Y Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2); Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); - } else if (MVT::isVector(VT)) { + } else if (VT.isVector()) { Result = LegalizeOp(UnrollVectorOp(Op)); } else { assert(VT == MVT::i32 && @@ -3258,9 +3253,9 @@ Result = ExpandLibCall(LC, Node, isSigned, Dummy); } } else { - assert(MVT::isFloatingPoint(VT) && + assert(VT.isFloatingPoint() && "remainder op must have integer or floating-point type"); - if (MVT::isVector(VT)) { + if (VT.isVector()) { Result = LegalizeOp(UnrollVectorOp(Op)); } else { // Floating point mod -> fmod libcall. @@ -3278,7 +3273,7 @@ Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. - MVT::ValueType VT = Node->getValueType(0); + MVT VT = Node->getValueType(0); switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { default: assert(0 && "This action is not supported yet!"); case TargetLowering::Custom: @@ -3302,7 +3297,7 @@ SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0); // Increment the pointer, VAList, to the next vaarg Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, - DAG.getConstant(MVT::getSizeInBits(VT)/8, + DAG.getConstant(VT.getSizeInBits()/8, TLI.getPointerTy())); // Store the incremented VAList to the legalized pointer Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0); @@ -3420,9 +3415,9 @@ Result = DAG.UpdateNodeOperands(Result, Tmp1); break; case TargetLowering::Promote: { - MVT::ValueType OVT = Tmp1.getValueType(); - MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); - unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT); + MVT OVT = Tmp1.getValueType(); + MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); + unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); @@ -3453,8 +3448,8 @@ } break; case TargetLowering::Promote: { - MVT::ValueType OVT = Tmp1.getValueType(); - MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); + MVT OVT = Tmp1.getValueType(); + MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); // Zero extend the argument. Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); @@ -3467,16 +3462,16 @@ case ISD::CTTZ: //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, - DAG.getConstant(MVT::getSizeInBits(NVT), NVT), + DAG.getConstant(NVT.getSizeInBits(), NVT), ISD::SETEQ); Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, - DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1); + DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1); break; case ISD::CTLZ: // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) Result = DAG.getNode(ISD::SUB, NVT, Tmp1, - DAG.getConstant(MVT::getSizeInBits(NVT) - - MVT::getSizeInBits(OVT), NVT)); + DAG.getConstant(NVT.getSizeInBits() - + OVT.getSizeInBits(), NVT)); break; } break; @@ -3516,7 +3511,7 @@ break; case ISD::FABS: { // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). - MVT::ValueType VT = Node->getValueType(0); + MVT VT = Node->getValueType(0); Tmp2 = DAG.getConstantFP(0.0, VT); Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2, ISD::SETUGT); @@ -3527,10 +3522,10 @@ case ISD::FSQRT: case ISD::FSIN: case ISD::FCOS: { - MVT::ValueType VT = Node->getValueType(0); + MVT VT = Node->getValueType(0); // Expand unsupported unary vector operators by unrolling them. - if (MVT::isVector(VT)) { + if (VT.isVector()) { Result = LegalizeOp(UnrollVectorOp(Op)); break; } @@ -3560,10 +3555,10 @@ } break; case ISD::FPOWI: { - MVT::ValueType VT = Node->getValueType(0); + MVT VT = Node->getValueType(0); // Expand unsupported unary vector operators by unrolling them. - if (MVT::isVector(VT)) { + if (VT.isVector()) { Result = LegalizeOp(UnrollVectorOp(Op)); break; } @@ -3579,17 +3574,17 @@ if (!isTypeLegal(Node->getOperand(0).getValueType())) { Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), Node->getValueType(0)); - } else if (MVT::isVector(Op.getOperand(0).getValueType())) { + } else if (Op.getOperand(0).getValueType().isVector()) { // The input has to be a vector type, we have to either scalarize it, pack // it, or convert it based on whether the input vector type is legal. SDNode *InVal = Node->getOperand(0).Val; int InIx = Node->getOperand(0).ResNo; - unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx)); - MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx)); + unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements(); + MVT EVT = InVal->getValueType(InIx).getVectorElementType(); // Figure out if there is a simple type corresponding to this Vector // type. If so, convert to the vector type. - MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); + MVT TVT = MVT::getVectorVT(EVT, NumElems); if (TLI.isTypeLegal(TVT)) { // Turn this into a bit convert of the vector input. Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), @@ -3716,11 +3711,11 @@ case TargetLowering::Expand: if (Node->getOpcode() == ISD::FP_TO_UINT) { SDOperand True, False; - MVT::ValueType VT = Node->getOperand(0).getValueType(); - MVT::ValueType NVT = Node->getValueType(0); + MVT VT = Node->getOperand(0).getValueType(); + MVT NVT = Node->getValueType(0); const uint64_t zero[] = {0, 0}; - APFloat apf = APFloat(APInt(MVT::getSizeInBits(VT), 2, zero)); - APInt x = APInt::getSignBit(MVT::getSizeInBits(NVT)); + APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero)); + APInt x = APInt::getSignBit(NVT.getSizeInBits()); (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven); Tmp2 = DAG.getConstantFP(apf, VT); Tmp3 = DAG.getSetCC(TLI.getSetCCResultType(Node->getOperand(0)), @@ -3740,8 +3735,8 @@ } break; case Expand: { - MVT::ValueType VT = Op.getValueType(); - MVT::ValueType OVT = Node->getOperand(0).getValueType(); + MVT VT = Op.getValueType(); + MVT OVT = Node->getOperand(0).getValueType(); // Convert ppcf128 to i32 if (OVT == MVT::ppcf128 && VT == MVT::i32) { if (Node->getOpcode() == ISD::FP_TO_SINT) { @@ -3858,8 +3853,8 @@ break; case ISD::FP_EXTEND: { - MVT::ValueType DstVT = Op.getValueType(); - MVT::ValueType SrcVT = Op.getOperand(0).getValueType(); + MVT DstVT = Op.getValueType(); + MVT SrcVT = Op.getOperand(0).getValueType(); if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) { // The only other way we can lower this is to turn it into a STORE, // LOAD pair, targetting a temporary location (a stack slot). @@ -3880,8 +3875,8 @@ break; } case ISD::FP_ROUND: { - MVT::ValueType DstVT = Op.getValueType(); - MVT::ValueType SrcVT = Op.getOperand(0).getValueType(); + MVT DstVT = Op.getValueType(); + MVT SrcVT = Op.getOperand(0).getValueType(); if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) { if (SrcVT == MVT::ppcf128) { SDOperand Lo; @@ -3949,7 +3944,7 @@ case ISD::FP_ROUND_INREG: case ISD::SIGN_EXTEND_INREG: { Tmp1 = LegalizeOp(Node->getOperand(0)); - MVT::ValueType ExtraVT = cast(Node->getOperand(1))->getVT(); + MVT ExtraVT = cast(Node->getOperand(1))->getVT(); // If this operation is not supported, convert it to a shl/shr or load/store // pair. @@ -3963,8 +3958,8 @@ if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { // NOTE: we could fall back on load/store here too for targets without // SAR. However, it is doubtful that any exist. - unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) - - MVT::getSizeInBits(ExtraVT); + unsigned BitsDiff = Node->getValueType(0).getSizeInBits() - + ExtraVT.getSizeInBits(); SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); Result = DAG.getNode(ISD::SHL, Node->getValueType(0), Node->getOperand(0), ShiftCst); @@ -4004,7 +3999,7 @@ return Op.ResNo ? Tmp1 : Result; } case ISD::FLT_ROUNDS_: { - MVT::ValueType VT = Node->getValueType(0); + MVT VT = Node->getValueType(0); switch (TLI.getOperationAction(Node->getOpcode(), VT)) { default: assert(0 && "This action not supported for this op yet!"); case TargetLowering::Custom: @@ -4019,7 +4014,7 @@ break; } case ISD::TRAP: { - MVT::ValueType VT = Node->getValueType(0); + MVT VT = Node->getValueType(0); switch (TLI.getOperationAction(Node->getOpcode(), VT)) { default: assert(0 && "This action not supported for this op yet!"); case TargetLowering::Legal: @@ -4064,11 +4059,11 @@ /// have the correct bits for the low portion of the register, but no guarantee /// is made about the top bits: it may be zero, sign-extended, or garbage. SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { - MVT::ValueType VT = Op.getValueType(); - MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); + MVT VT = Op.getValueType(); + MVT NVT = TLI.getTypeToTransformTo(VT); assert(getTypeAction(VT) == Promote && "Caller should expand or legalize operands that are not promotable!"); - assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) && + assert(NVT > VT && NVT.isInteger() == VT.isInteger() && "Cannot promote to smaller type!"); SDOperand Tmp1, Tmp2, Tmp3; @@ -4341,7 +4336,7 @@ // These operators require that their input be sign extended. Tmp1 = PromoteOp(Node->getOperand(0)); Tmp2 = PromoteOp(Node->getOperand(1)); - if (MVT::isInteger(NVT)) { + if (NVT.isInteger()) { Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, DAG.getValueType(VT)); Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, @@ -4350,7 +4345,7 @@ Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); // Perform FP_ROUND: this is probably overly pessimistic. - if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) + if (NVT.isFloatingPoint() && NoExcessFPPrecision) Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, DAG.getValueType(VT)); break; @@ -4381,7 +4376,7 @@ // These operators require that their input be zero extended. Tmp1 = PromoteOp(Node->getOperand(0)); Tmp2 = PromoteOp(Node->getOperand(1)); - assert(MVT::isInteger(NVT) && "Operators don't apply to FP!"); + assert(NVT.isInteger() && "Operators don't apply to FP!"); Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); @@ -4416,7 +4411,7 @@ SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0); // Increment the pointer, VAList, to the next vaarg Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, - DAG.getConstant(MVT::getSizeInBits(VT)/8, + DAG.getConstant(VT.getSizeInBits()/8, TLI.getPointerTy())); // Store the incremented VAList to the legalized pointer Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0); @@ -4445,7 +4440,7 @@ Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 - unsigned VT2 = Tmp2.getValueType(); + MVT VT2 = Tmp2.getValueType(); assert(VT2 == Tmp3.getValueType() && "PromoteOp SELECT: Operands 2 and 3 ValueTypes don't match"); // Ensure that the resulting node is at least the same size as the operands' @@ -4465,8 +4460,8 @@ Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); Result = DAG.getNode(ISD::SRL, NVT, Tmp1, - DAG.getConstant(MVT::getSizeInBits(NVT) - - MVT::getSizeInBits(VT), + DAG.getConstant(NVT.getSizeInBits() - + VT.getSizeInBits(), TLI.getShiftAmountTy())); break; case ISD::CTPOP: @@ -4483,16 +4478,16 @@ case ISD::CTTZ: // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, - DAG.getConstant(MVT::getSizeInBits(NVT), NVT), + DAG.getConstant(NVT.getSizeInBits(), NVT), ISD::SETEQ); Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, - DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1); + DAG.getConstant(VT.getSizeInBits(), NVT), Tmp1); break; case ISD::CTLZ: //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) Result = DAG.getNode(ISD::SUB, NVT, Tmp1, - DAG.getConstant(MVT::getSizeInBits(NVT) - - MVT::getSizeInBits(VT), NVT)); + DAG.getConstant(NVT.getSizeInBits() - + VT.getSizeInBits(), NVT)); break; } break; @@ -4525,8 +4520,8 @@ SDOperand Vec = Op.getOperand(0); SDOperand Idx = Op.getOperand(1); - MVT::ValueType TVT = Vec.getValueType(); - unsigned NumElems = MVT::getVectorNumElements(TVT); + MVT TVT = Vec.getValueType(); + unsigned NumElems = TVT.getVectorNumElements(); switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) { default: assert(0 && "This action is not supported yet!"); @@ -4575,12 +4570,11 @@ SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0); // Add the offset to the index. - unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8; + unsigned EltSize = Op.getValueType().getSizeInBits()/8; Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx, DAG.getConstant(EltSize, Idx.getValueType())); - if (MVT::getSizeInBits(Idx.getValueType()) > - MVT::getSizeInBits(TLI.getPointerTy())) + if (Idx.getValueType().getSizeInBits() > TLI.getPointerTy().getSizeInBits()) Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx); else Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx); @@ -4600,9 +4594,9 @@ SDOperand Vec = Op.getOperand(0); SDOperand Idx = LegalizeOp(Op.getOperand(1)); - unsigned NumElems = MVT::getVectorNumElements(Vec.getValueType()); + unsigned NumElems = Vec.getValueType().getVectorNumElements(); - if (NumElems == MVT::getVectorNumElements(Op.getValueType())) { + if (NumElems == Op.getValueType().getVectorNumElements()) { // This must be an access of the desired vector length. Return it. return Vec; } @@ -4643,9 +4637,9 @@ Tmp2 = PromoteOp(RHS); // RHS // If this is an FP compare, the operands have already been extended. - if (MVT::isInteger(LHS.getValueType())) { - MVT::ValueType VT = LHS.getValueType(); - MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); + if (LHS.getValueType().isInteger()) { + MVT VT = LHS.getValueType(); + MVT NVT = TLI.getTypeToTransformTo(VT); // Otherwise, we have to insert explicit sign or zero extends. Note // that we could insert sign extends for ALL conditions, but zero extend @@ -4678,7 +4672,7 @@ } break; case Expand: { - MVT::ValueType VT = LHS.getValueType(); + MVT VT = LHS.getValueType(); if (VT == MVT::f32 || VT == MVT::f64) { // Expand into one or more soft-fp libcall(s). RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL; @@ -4881,17 +4875,17 @@ /// a load from the stack slot to DestVT, extending it if needed. /// The resultant code need not be legal. SDOperand SelectionDAGLegalize::EmitStackConvert(SDOperand SrcOp, - MVT::ValueType SlotVT, - MVT::ValueType DestVT) { + MVT SlotVT, + MVT DestVT) { // Create the stack frame object. SDOperand FIPtr = DAG.CreateStackTemporary(SlotVT); FrameIndexSDNode *StackPtrFI = cast(FIPtr); int SPFI = StackPtrFI->getIndex(); - unsigned SrcSize = MVT::getSizeInBits(SrcOp.getValueType()); - unsigned SlotSize = MVT::getSizeInBits(SlotVT); - unsigned DestSize = MVT::getSizeInBits(DestVT); + unsigned SrcSize = SrcOp.getValueType().getSizeInBits(); + unsigned SlotSize = SlotVT.getSizeInBits(); + unsigned DestSize = DestVT.getSizeInBits(); // Emit a store to the stack slot. Use a truncstore if the input value is // later than DestVT. @@ -4904,7 +4898,7 @@ assert(SrcSize == SlotSize && "Invalid store"); Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, PseudoSourceValue::getFixedStack(), - SPFI, SlotVT); + SPFI); } // Result is a load from the stack slot. @@ -4975,7 +4969,7 @@ // If all elements are constants, create a load from the constant pool. if (isConstant) { - MVT::ValueType VT = Node->getValueType(0); + MVT VT = Node->getValueType(0); std::vector CV; for (unsigned i = 0, e = NumElems; i != e; ++i) { if (ConstantFPSDNode *V = @@ -4987,7 +4981,7 @@ } else { assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); const Type *OpNTy = - MVT::getTypeForValueType(Node->getOperand(0).getValueType()); + Node->getOperand(0).getValueType().getTypeForMVT(); CV.push_back(UndefValue::get(OpNTy)); } } @@ -4999,9 +4993,8 @@ if (SplatValue.Val) { // Splat of one value? // Build the shuffle constant vector: <0, 0, 0, 0> - MVT::ValueType MaskVT = - MVT::getIntVectorWithNumElements(NumElems); - SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT)); + MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); + SDOperand Zero = DAG.getConstant(0, MaskVT.getVectorElementType()); std::vector ZeroVec(NumElems, Zero); SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &ZeroVec[0], ZeroVec.size()); @@ -5037,8 +5030,8 @@ std::swap(Val1, Val2); // Build the shuffle constant vector: e.g. <0, 4, 0, 4> - MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems); - MVT::ValueType MaskEltVT = MVT::getVectorElementType(MaskVT); + MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); + MVT MaskEltVT = MaskVT.getVectorElementType(); std::vector MaskVec(NumElems); // Set elements of the shuffle mask for Val1. @@ -5072,14 +5065,13 @@ // Otherwise, we can't handle this case efficiently. Allocate a sufficiently // aligned object on the stack, store each element into it, then load // the result as a vector. - MVT::ValueType VT = Node->getValueType(0); + MVT VT = Node->getValueType(0); // Create the stack frame object. SDOperand FIPtr = DAG.CreateStackTemporary(VT); // Emit a store of each element to the stack slot. SmallVector Stores; - unsigned TypeByteSize = - MVT::getSizeInBits(Node->getOperand(0).getValueType())/8; + unsigned TypeByteSize = Node->getOperand(0).getValueType().getSizeInBits()/8; // Store (in the right endianness) the elements to memory. for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { // Ignore undef elements. @@ -5113,7 +5105,7 @@ ExpandOp(Op, LHSL, LHSH); SDOperand Ops[] = { LHSL, LHSH, Amt }; - MVT::ValueType VT = LHSL.getValueType(); + MVT VT = LHSL.getValueType(); Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); Hi = Lo.getValue(1); } @@ -5128,12 +5120,12 @@ assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && "This is not a shift!"); - MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType()); + MVT NVT = TLI.getTypeToTransformTo(Op.getValueType()); SDOperand ShAmt = LegalizeOp(Amt); - MVT::ValueType ShTy = ShAmt.getValueType(); - unsigned ShBits = MVT::getSizeInBits(ShTy); - unsigned VTBits = MVT::getSizeInBits(Op.getValueType()); - unsigned NVTBits = MVT::getSizeInBits(NVT); + MVT ShTy = ShAmt.getValueType(); + unsigned ShBits = ShTy.getSizeInBits(); + unsigned VTBits = Op.getValueType().getSizeInBits(); + unsigned NVTBits = NVT.getSizeInBits(); // Handle the case when Amt is an immediate. if (ConstantSDNode *CN = dyn_cast(Amt.Val)) { @@ -5284,8 +5276,8 @@ TargetLowering::ArgListTy Args; TargetLowering::ArgListEntry Entry; for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { - MVT::ValueType ArgVT = Node->getOperand(i).getValueType(); - const Type *ArgTy = MVT::getTypeForValueType(ArgVT); + MVT ArgVT = Node->getOperand(i).getValueType(); + const Type *ArgTy = ArgVT.getTypeForMVT(); Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; Entry.isSExt = isSigned; Entry.isZExt = !isSigned; @@ -5295,7 +5287,7 @@ TLI.getPointerTy()); // Splice the libcall in wherever FindInputOutputChains tells us to. - const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0)); + const Type *RetTy = Node->getValueType(0).getTypeForMVT(); std::pair CallInfo = TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, CallingConv::C, false, Callee, Args, DAG); @@ -5321,8 +5313,8 @@ /// ExpandIntToFP - Expand a [US]INT_TO_FP operation. /// SDOperand SelectionDAGLegalize:: -ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { - MVT::ValueType SourceVT = Source.getValueType(); +ExpandIntToFP(bool isSigned, MVT DestTy, SDOperand Source) { + MVT SourceVT = Source.getValueType(); bool ExpandSource = getTypeAction(SourceVT) == Expand; // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc. @@ -5360,7 +5352,7 @@ if (DestTy == MVT::f32) FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, PseudoSourceValue::getConstantPool(), 0); - else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32)) + else if (DestTy.getSizeInBits() > MVT(MVT::f32).getSizeInBits()) // FIXME: Avoid the extend by construction the right constantpool? FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(), CPIdx, @@ -5369,12 +5361,12 @@ else assert(0 && "Unexpected conversion"); - MVT::ValueType SCVT = SignedConv.getValueType(); + MVT SCVT = SignedConv.getValueType(); if (SCVT != DestTy) { // Destination type needs to be expanded as well. The FADD now we are // constructing will be expanded into a libcall. - if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) { - assert(MVT::getSizeInBits(SCVT) * 2 == MVT::getSizeInBits(DestTy)); + if (SCVT.getSizeInBits() != DestTy.getSizeInBits()) { + assert(SCVT.getSizeInBits() * 2 == DestTy.getSizeInBits()); SignedConv = DAG.getNode(ISD::BUILD_PAIR, DestTy, SignedConv, SignedConv.getValue(1)); } @@ -5455,7 +5447,7 @@ /// legal for the target. SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, SDOperand Op0, - MVT::ValueType DestVT) { + MVT DestVT) { if (Op0.getValueType() == MVT::i32) { // simple 32-bit [signed|unsigned] integer to float/double expansion @@ -5501,10 +5493,12 @@ if (DestVT == MVT::f64) { // do nothing Result = Sub; - } else if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(MVT::f64)) { + } else if (DestVT.getSizeInBits() < + MVT(MVT::f64).getSizeInBits()) { Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub, DAG.getIntPtrConstant(0)); - } else if (MVT::getSizeInBits(DestVT) > MVT::getSizeInBits(MVT::f64)) { + } else if (DestVT.getSizeInBits() > + MVT(MVT::f64).getSizeInBits()) { Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub); } return Result; @@ -5523,7 +5517,7 @@ // as a negative number. To counteract this, the dynamic code adds an // offset depending on the data type. uint64_t FF; - switch (Op0.getValueType()) { + switch (Op0.getValueType().getSimpleVT()) { default: assert(0 && "Unsupported integer type!"); case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) @@ -5556,17 +5550,17 @@ /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP /// operation that takes a larger input. SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp, - MVT::ValueType DestVT, + MVT DestVT, bool isSigned) { // First step, figure out the appropriate *INT_TO_FP operation to use. - MVT::ValueType NewInTy = LegalOp.getValueType(); + MVT NewInTy = LegalOp.getValueType(); unsigned OpToUse = 0; // Scan for the appropriate larger type to use. while (1) { - NewInTy = (MVT::ValueType)(NewInTy+1); - assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!"); + NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1); + assert(NewInTy.isInteger() && "Ran out of possibilities!"); // If the target supports SINT_TO_FP of this type, use it. switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { @@ -5611,17 +5605,17 @@ /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT /// operation that returns a larger result. SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp, - MVT::ValueType DestVT, + MVT DestVT, bool isSigned) { // First step, figure out the appropriate FP_TO*INT operation to use. - MVT::ValueType NewOutTy = DestVT; + MVT NewOutTy = DestVT; unsigned OpToUse = 0; // Scan for the appropriate larger type to use. while (1) { - NewOutTy = (MVT::ValueType)(NewOutTy+1); - assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!"); + NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1); + assert(NewOutTy.isInteger() && "Ran out of possibilities!"); // If the target supports FP_TO_SINT returning this type, use it. switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { @@ -5672,10 +5666,10 @@ /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. /// SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) { - MVT::ValueType VT = Op.getValueType(); - MVT::ValueType SHVT = TLI.getShiftAmountTy(); + MVT VT = Op.getValueType(); + MVT SHVT = TLI.getShiftAmountTy(); SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; - switch (VT) { + switch (VT.getSimpleVT()) { default: assert(0 && "Unhandled Expand type in BSWAP!"); abort(); case MVT::i16: Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); @@ -5727,9 +5721,9 @@ 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL }; - MVT::ValueType VT = Op.getValueType(); - MVT::ValueType ShVT = TLI.getShiftAmountTy(); - unsigned len = MVT::getSizeInBits(VT); + MVT VT = Op.getValueType(); + MVT ShVT = TLI.getShiftAmountTy(); + unsigned len = VT.getSizeInBits(); for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) SDOperand Tmp2 = DAG.getConstant(mask[i], VT); @@ -5750,9 +5744,9 @@ // return popcount(~x); // // but see also: http://www.hackersdelight.org/HDcode/nlz.cc - MVT::ValueType VT = Op.getValueType(); - MVT::ValueType ShVT = TLI.getShiftAmountTy(); - unsigned len = MVT::getSizeInBits(VT); + MVT VT = Op.getValueType(); + MVT ShVT = TLI.getShiftAmountTy(); + unsigned len = VT.getSizeInBits(); for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3)); @@ -5765,7 +5759,7 @@ // unless the target has ctlz but not ctpop, in which case we use: // { return 32 - nlz(~x & (x-1)); } // see also http://www.hackersdelight.org/HDcode/ntz.cc - MVT::ValueType VT = Op.getValueType(); + MVT VT = Op.getValueType(); SDOperand Tmp2 = DAG.getConstant(~0ULL, VT); SDOperand Tmp3 = DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::XOR, VT, Op, Tmp2), @@ -5774,7 +5768,7 @@ if (!TLI.isOperationLegal(ISD::CTPOP, VT) && TLI.isOperationLegal(ISD::CTLZ, VT)) return DAG.getNode(ISD::SUB, VT, - DAG.getConstant(MVT::getSizeInBits(VT), VT), + DAG.getConstant(VT.getSizeInBits(), VT), DAG.getNode(ISD::CTLZ, VT, Tmp3)); return DAG.getNode(ISD::CTPOP, VT, Tmp3); } @@ -5787,13 +5781,12 @@ /// ExpandedNodes map is filled in for any results that are expanded, and the /// Lo/Hi values are returned. void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ - MVT::ValueType VT = Op.getValueType(); - MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); + MVT VT = Op.getValueType(); + MVT NVT = TLI.getTypeToTransformTo(VT); SDNode *Node = Op.Val; assert(getTypeAction(VT) == Expand && "Not an expanded type!"); - assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) || - MVT::isVector(VT)) && - "Cannot expand to FP value or to larger int value!"); + assert(((NVT.isInteger() && NVT < VT) || VT.isFloatingPoint() || + VT.isVector()) && "Cannot expand to FP value or to larger int value!"); // See if we already expanded it. DenseMap >::iterator I @@ -5844,7 +5837,7 @@ Hi = DAG.getNode(ISD::UNDEF, NVT); break; case ISD::Constant: { - unsigned NVTBits = MVT::getSizeInBits(NVT); + unsigned NVTBits = NVT.getSizeInBits(); const APInt &Cst = cast(Node)->getAPIntValue(); Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT); Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT); @@ -5893,7 +5886,7 @@ // The high part gets the sign extension from the lo-part. This handles // things like sextinreg V:i64 from i8. Hi = DAG.getNode(ISD::SRA, NVT, Lo, - DAG.getConstant(MVT::getSizeInBits(NVT)-1, + DAG.getConstant(NVT.getSizeInBits()-1, TLI.getShiftAmountTy())); break; @@ -5916,7 +5909,7 @@ case ISD::CTLZ: { // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) ExpandOp(Node->getOperand(0), Lo, Hi); - SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); + SDOperand BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT); SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(HLZ), HLZ, BitsC, ISD::SETNE); @@ -5931,7 +5924,7 @@ case ISD::CTTZ: { // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) ExpandOp(Node->getOperand(0), Lo, Hi); - SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); + SDOperand BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT); SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(LTZ), LTZ, BitsC, ISD::SETNE); @@ -5980,7 +5973,7 @@ } // Increment the pointer to the other half. - unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; + unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8; Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, DAG.getIntPtrConstant(IncrementSize)); SVOffset += IncrementSize; @@ -5998,7 +5991,7 @@ if (TLI.isBigEndian()) std::swap(Lo, Hi); } else { - MVT::ValueType EVT = LD->getMemoryVT(); + MVT EVT = LD->getMemoryVT(); if ((VT == MVT::f64 && EVT == MVT::f32) || (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) { @@ -6025,7 +6018,7 @@ if (ExtType == ISD::SEXTLOAD) { // The high part is obtained by SRA'ing all but one of the bits of the // lo part. - unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); + unsigned LoSize = Lo.getValueType().getSizeInBits(); Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); } else if (ExtType == ISD::ZEXTLOAD) { @@ -6085,7 +6078,7 @@ // The high part is obtained by SRA'ing all but one of the bits of the lo // part. - unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); + unsigned LoSize = Lo.getValueType().getSizeInBits(); Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); break; @@ -6134,7 +6127,7 @@ // If source operand will be expanded to the same type as VT, i.e. // i64 <- f64, i32 <- f32, expand the source operand instead. - MVT::ValueType VT0 = Node->getOperand(0).getValueType(); + MVT VT0 = Node->getOperand(0).getValueType(); if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) { ExpandOp(Node->getOperand(0), Lo, Hi); break; @@ -6668,7 +6661,7 @@ case ISD::SINT_TO_FP: case ISD::UINT_TO_FP: { bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; - MVT::ValueType SrcVT = Node->getOperand(0).getValueType(); + MVT SrcVT = Node->getOperand(0).getValueType(); // Promote the operand if needed. Do this before checking for // ppcf128 so conversions of i16 and i8 work. @@ -6753,18 +6746,18 @@ /// two smaller values, still of vector type. void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi) { - assert(MVT::isVector(Op.getValueType()) && "Cannot split non-vector type!"); + assert(Op.getValueType().isVector() && "Cannot split non-vector type!"); SDNode *Node = Op.Val; - unsigned NumElements = MVT::getVectorNumElements(Op.getValueType()); + unsigned NumElements = Op.getValueType().getVectorNumElements(); assert(NumElements > 1 && "Cannot split a single element vector!"); - MVT::ValueType NewEltVT = MVT::getVectorElementType(Op.getValueType()); + MVT NewEltVT = Op.getValueType().getVectorElementType(); unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1); unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo; - MVT::ValueType NewVT_Lo = MVT::getVectorType(NewEltVT, NewNumElts_Lo); - MVT::ValueType NewVT_Hi = MVT::getVectorType(NewEltVT, NewNumElts_Hi); + MVT NewVT_Lo = MVT::getVectorVT(NewEltVT, NewNumElts_Lo); + MVT NewVT_Hi = MVT::getVectorVT(NewEltVT, NewNumElts_Hi); // See if we already split it. std::map >::iterator I @@ -6812,7 +6805,7 @@ // Build the low part. SDOperand Mask = Node->getOperand(2); SmallVector Ops; - MVT::ValueType PtrVT = TLI.getPointerTy(); + MVT PtrVT = TLI.getPointerTy(); // Insert all of the elements from the input that are needed. We use // buildvector of extractelement here because the input vectors will have @@ -6887,7 +6880,7 @@ SplitVectorOp(Node->getOperand(1), LL, LH); SplitVectorOp(Node->getOperand(2), RL, RH); - if (MVT::isVector(Cond.getValueType())) { + if (Cond.getValueType().isVector()) { // Handle a vector merge. SDOperand CL, CH; SplitVectorOp(Cond, CL, CH); @@ -6969,7 +6962,7 @@ bool isVolatile = LD->isVolatile(); Lo = DAG.getLoad(NewVT_Lo, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); - unsigned IncrementSize = NewNumElts_Lo * MVT::getSizeInBits(NewEltVT)/8; + unsigned IncrementSize = NewNumElts_Lo * NewEltVT.getSizeInBits()/8; Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, DAG.getIntPtrConstant(IncrementSize)); SVOffset += IncrementSize; @@ -6989,8 +6982,8 @@ // We know the result is a vector. The input may be either a vector or a // scalar value. SDOperand InOp = Node->getOperand(0); - if (!MVT::isVector(InOp.getValueType()) || - MVT::getVectorNumElements(InOp.getValueType()) == 1) { + if (!InOp.getValueType().isVector() || + InOp.getValueType().getVectorNumElements() == 1) { // The input is a scalar or single-element vector. // Lower to a store/load so that it can be split. // FIXME: this could be improved probably. @@ -7024,11 +7017,10 @@ /// (e.g. v1f32), convert it into the equivalent operation that returns a /// scalar (e.g. f32) value. SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) { - assert(MVT::isVector(Op.getValueType()) && - "Bad ScalarizeVectorOp invocation!"); + assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!"); SDNode *Node = Op.Val; - MVT::ValueType NewVT = MVT::getVectorElementType(Op.getValueType()); - assert(MVT::getVectorNumElements(Op.getValueType()) == 1); + MVT NewVT = Op.getValueType().getVectorElementType(); + assert(Op.getValueType().getVectorNumElements() == 1); // See if we already scalarized it. std::map::iterator I = ScalarizedNodes.find(Op); @@ -7118,7 +7110,7 @@ break; case ISD::BIT_CONVERT: { SDOperand Op0 = Op.getOperand(0); - if (MVT::getVectorNumElements(Op0.getValueType()) == 1) + if (Op0.getValueType().getVectorNumElements() == 1) Op0 = ScalarizeVectorOp(Op0); Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op0); break; Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp Fri Jun 6 07:08:01 2008 @@ -68,7 +68,7 @@ unsigned i = 0; unsigned NumResults = N->getNumValues(); do { - MVT::ValueType ResultVT = N->getValueType(i); + MVT ResultVT = N->getValueType(i); switch (getTypeAction(ResultVT)) { default: assert(false && "Unknown action!"); @@ -98,7 +98,7 @@ unsigned NumOperands = N->getNumOperands(); bool NeedsRevisit = false; for (i = 0; i != NumOperands; ++i) { - MVT::ValueType OpVT = N->getOperand(i).getValueType(); + MVT OpVT = N->getOperand(i).getValueType(); switch (getTypeAction(OpVT)) { default: assert(false && "Unknown action!"); @@ -472,13 +472,12 @@ /// BitConvertToInteger - Convert to an integer of the same size. SDOperand DAGTypeLegalizer::BitConvertToInteger(SDOperand Op) { - return DAG.getNode(ISD::BIT_CONVERT, - MVT::getIntegerType(MVT::getSizeInBits(Op.getValueType())), - Op); + unsigned BitWidth = Op.getValueType().getSizeInBits(); + return DAG.getNode(ISD::BIT_CONVERT, MVT::getIntegerVT(BitWidth), Op); } SDOperand DAGTypeLegalizer::CreateStackStoreLoad(SDOperand Op, - MVT::ValueType DestVT) { + MVT DestVT) { // Create the stack frame object. SDOperand FIPtr = DAG.CreateStackTemporary(DestVT); @@ -490,14 +489,13 @@ /// JoinIntegers - Build an integer with low bits Lo and high bits Hi. SDOperand DAGTypeLegalizer::JoinIntegers(SDOperand Lo, SDOperand Hi) { - MVT::ValueType LVT = Lo.getValueType(); - MVT::ValueType HVT = Hi.getValueType(); - MVT::ValueType NVT = MVT::getIntegerType(MVT::getSizeInBits(LVT) + - MVT::getSizeInBits(HVT)); + MVT LVT = Lo.getValueType(); + MVT HVT = Hi.getValueType(); + MVT NVT = MVT::getIntegerVT(LVT.getSizeInBits() + HVT.getSizeInBits()); Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Lo); Hi = DAG.getNode(ISD::ANY_EXTEND, NVT, Hi); - Hi = DAG.getNode(ISD::SHL, NVT, Hi, DAG.getConstant(MVT::getSizeInBits(LVT), + Hi = DAG.getNode(ISD::SHL, NVT, Hi, DAG.getConstant(LVT.getSizeInBits(), TLI.getShiftAmountTy())); return DAG.getNode(ISD::OR, NVT, Lo, Hi); } @@ -505,13 +503,13 @@ /// SplitInteger - Return the lower LoVT bits of Op in Lo and the upper HiVT /// bits in Hi. void DAGTypeLegalizer::SplitInteger(SDOperand Op, - MVT::ValueType LoVT, MVT::ValueType HiVT, + MVT LoVT, MVT HiVT, SDOperand &Lo, SDOperand &Hi) { - assert(MVT::getSizeInBits(LoVT) + MVT::getSizeInBits(HiVT) == - MVT::getSizeInBits(Op.getValueType()) && "Invalid integer splitting!"); + assert(LoVT.getSizeInBits() + HiVT.getSizeInBits() == + Op.getValueType().getSizeInBits() && "Invalid integer splitting!"); Lo = DAG.getNode(ISD::TRUNCATE, LoVT, Op); Hi = DAG.getNode(ISD::SRL, Op.getValueType(), Op, - DAG.getConstant(MVT::getSizeInBits(LoVT), + DAG.getConstant(LoVT.getSizeInBits(), TLI.getShiftAmountTy())); Hi = DAG.getNode(ISD::TRUNCATE, HiVT, Hi); } @@ -520,14 +518,13 @@ /// half the size of Op's. void DAGTypeLegalizer::SplitInteger(SDOperand Op, SDOperand &Lo, SDOperand &Hi) { - MVT::ValueType HalfVT = - MVT::getIntegerType(MVT::getSizeInBits(Op.getValueType())/2); + MVT HalfVT = MVT::getIntegerVT(Op.getValueType().getSizeInBits()/2); SplitInteger(Op, HalfVT, HalfVT, Lo, Hi); } /// MakeLibCall - Generate a libcall taking the given operands as arguments and /// returning a result of type RetVT. -SDOperand DAGTypeLegalizer::MakeLibCall(RTLIB::Libcall LC, MVT::ValueType RetVT, +SDOperand DAGTypeLegalizer::MakeLibCall(RTLIB::Libcall LC, MVT RetVT, const SDOperand *Ops, unsigned NumOps, bool isSigned) { TargetLowering::ArgListTy Args; @@ -536,7 +533,7 @@ TargetLowering::ArgListEntry Entry; for (unsigned i = 0; i != NumOps; ++i) { Entry.Node = Ops[i]; - Entry.Ty = MVT::getTypeForValueType(Entry.Node.getValueType()); + Entry.Ty = Entry.Node.getValueType().getTypeForMVT(); Entry.isSExt = isSigned; Entry.isZExt = !isSigned; Args.push_back(Entry); @@ -544,7 +541,7 @@ SDOperand Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), TLI.getPointerTy()); - const Type *RetTy = MVT::getTypeForValueType(RetVT); + const Type *RetTy = RetVT.getTypeForMVT(); std::pair CallInfo = TLI.LowerCallTo(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false, CallingConv::C, false, Callee, Args, DAG); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Fri Jun 6 07:08:01 2008 @@ -77,7 +77,7 @@ /// we need to expand it into multiple registers of a smaller integer type, or /// we need to scalarize a one-element vector type into the element type, or /// we need to split a vector type into smaller vector types. - LegalizeAction getTypeAction(MVT::ValueType VT) const { + LegalizeAction getTypeAction(MVT VT) const { switch (ValueTypeActions.getTypeAction(VT)) { default: assert(false && "Unknown legalize action!"); @@ -89,13 +89,12 @@ // Expand can mean // 1) split scalar in half, 2) convert a float to an integer, // 3) scalarize a single-element vector, 4) split a vector in two. - if (!MVT::isVector(VT)) { - if (MVT::getSizeInBits(VT) == - MVT::getSizeInBits(TLI.getTypeToTransformTo(VT))) + if (!VT.isVector()) { + if (VT.getSizeInBits() == TLI.getTypeToTransformTo(VT).getSizeInBits()) return FloatToInt; else return Expand; - } else if (MVT::getVectorNumElements(VT) == 1) { + } else if (VT.getVectorNumElements() == 1) { return Scalarize; } else { return Split; @@ -104,7 +103,7 @@ } /// isTypeLegal - Return true if this type is legal on this target. - bool isTypeLegal(MVT::ValueType VT) const { + bool isTypeLegal(MVT VT) const { return ValueTypeActions.getTypeAction(VT) == TargetLowering::Legal; } @@ -164,12 +163,12 @@ // Common routines. SDOperand BitConvertToInteger(SDOperand Op); - SDOperand CreateStackStoreLoad(SDOperand Op, MVT::ValueType DestVT); + SDOperand CreateStackStoreLoad(SDOperand Op, MVT DestVT); SDOperand JoinIntegers(SDOperand Lo, SDOperand Hi); void SplitInteger(SDOperand Op, SDOperand &Lo, SDOperand &Hi); - void SplitInteger(SDOperand Op, MVT::ValueType LoVT, MVT::ValueType HiVT, + void SplitInteger(SDOperand Op, MVT LoVT, MVT HiVT, SDOperand &Lo, SDOperand &Hi); - SDOperand MakeLibCall(RTLIB::Libcall LC, MVT::ValueType RetVT, + SDOperand MakeLibCall(RTLIB::Libcall LC, MVT RetVT, const SDOperand *Ops, unsigned NumOps, bool isSigned); //===--------------------------------------------------------------------===// @@ -187,7 +186,7 @@ /// GetPromotedZExtOp - Get a promoted operand and zero extend it to the final /// size. SDOperand GetPromotedZExtOp(SDOperand Op) { - MVT::ValueType OldVT = Op.getValueType(); + MVT OldVT = Op.getValueType(); Op = GetPromotedOp(Op); return DAG.getZeroExtendInReg(Op, OldVT); } @@ -292,10 +291,10 @@ SDOperand ExpandOperand_BUILD_VECTOR(SDNode *N); SDOperand ExpandOperand_EXTRACT_ELEMENT(SDNode *N); SDOperand ExpandOperand_SETCC(SDNode *N); - SDOperand ExpandOperand_SINT_TO_FP(SDOperand Source, MVT::ValueType DestTy); + SDOperand ExpandOperand_SINT_TO_FP(SDOperand Source, MVT DestTy); SDOperand ExpandOperand_STORE(StoreSDNode *N, unsigned OpNo); SDOperand ExpandOperand_TRUNCATE(SDNode *N); - SDOperand ExpandOperand_UINT_TO_FP(SDOperand Source, MVT::ValueType DestTy); + SDOperand ExpandOperand_UINT_TO_FP(SDOperand Source, MVT DestTy); void ExpandSetCCOperands(SDOperand &NewLHS, SDOperand &NewRHS, ISD::CondCode &CCCode); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp Fri Jun 6 07:08:01 2008 @@ -105,14 +105,14 @@ void DAGTypeLegalizer::ExpandResult_UNDEF(SDNode *N, SDOperand &Lo, SDOperand &Hi) { - MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); Lo = Hi = DAG.getNode(ISD::UNDEF, NVT); } void DAGTypeLegalizer::ExpandResult_Constant(SDNode *N, SDOperand &Lo, SDOperand &Hi) { - MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0)); - unsigned NBitWidth = MVT::getSizeInBits(NVT); + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + unsigned NBitWidth = NVT.getSizeInBits(); const APInt &Cst = cast(N)->getAPIntValue(); Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT); Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT); @@ -148,9 +148,9 @@ void DAGTypeLegalizer::ExpandResult_ANY_EXTEND(SDNode *N, SDOperand &Lo, SDOperand &Hi) { - MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDOperand Op = N->getOperand(0); - if (MVT::getSizeInBits(Op.getValueType()) <= MVT::getSizeInBits(NVT)) { + if (Op.getValueType().getSizeInBits() <= NVT.getSizeInBits()) { // The low part is any extension of the input (which degenerates to a copy). Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Op); Hi = DAG.getNode(ISD::UNDEF, NVT); // The high part is undefined. @@ -169,9 +169,9 @@ void DAGTypeLegalizer::ExpandResult_ZERO_EXTEND(SDNode *N, SDOperand &Lo, SDOperand &Hi) { - MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDOperand Op = N->getOperand(0); - if (MVT::getSizeInBits(Op.getValueType()) <= MVT::getSizeInBits(NVT)) { + if (Op.getValueType().getSizeInBits() <= NVT.getSizeInBits()) { // The low part is zero extension of the input (which degenerates to a copy). Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, N->getOperand(0)); Hi = DAG.getConstant(0, NVT); // The high part is just a zero. @@ -186,20 +186,20 @@ // Split the promoted operand. This will simplify when it is expanded. SplitInteger(Res, Lo, Hi); unsigned ExcessBits = - MVT::getSizeInBits(Op.getValueType()) - MVT::getSizeInBits(NVT); - Hi = DAG.getZeroExtendInReg(Hi, MVT::getIntegerType(ExcessBits)); + Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); + Hi = DAG.getZeroExtendInReg(Hi, MVT::getIntegerVT(ExcessBits)); } } void DAGTypeLegalizer::ExpandResult_SIGN_EXTEND(SDNode *N, SDOperand &Lo, SDOperand &Hi) { - MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDOperand Op = N->getOperand(0); - if (MVT::getSizeInBits(Op.getValueType()) <= MVT::getSizeInBits(NVT)) { + if (Op.getValueType().getSizeInBits() <= NVT.getSizeInBits()) { // The low part is sign extension of the input (which degenerates to a copy). Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, N->getOperand(0)); // The high part is obtained by SRA'ing all but one of the bits of low part. - unsigned LoSize = MVT::getSizeInBits(NVT); + unsigned LoSize = NVT.getSizeInBits(); Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); } else { @@ -213,23 +213,23 @@ // Split the promoted operand. This will simplify when it is expanded. SplitInteger(Res, Lo, Hi); unsigned ExcessBits = - MVT::getSizeInBits(Op.getValueType()) - MVT::getSizeInBits(NVT); + Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi, - DAG.getValueType(MVT::getIntegerType(ExcessBits))); + DAG.getValueType(MVT::getIntegerVT(ExcessBits))); } } void DAGTypeLegalizer::ExpandResult_AssertZext(SDNode *N, SDOperand &Lo, SDOperand &Hi) { GetExpandedOp(N->getOperand(0), Lo, Hi); - MVT::ValueType NVT = Lo.getValueType(); - MVT::ValueType EVT = cast(N->getOperand(1))->getVT(); - unsigned NVTBits = MVT::getSizeInBits(NVT); - unsigned EVTBits = MVT::getSizeInBits(EVT); + MVT NVT = Lo.getValueType(); + MVT EVT = cast(N->getOperand(1))->getVT(); + unsigned NVTBits = NVT.getSizeInBits(); + unsigned EVTBits = EVT.getSizeInBits(); if (NVTBits < EVTBits) { Hi = DAG.getNode(ISD::AssertZext, NVT, Hi, - DAG.getValueType(MVT::getIntegerType(EVTBits - NVTBits))); + DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits))); } else { Lo = DAG.getNode(ISD::AssertZext, NVT, Lo, DAG.getValueType(EVT)); // The high part must be zero, make it explicit. @@ -239,19 +239,19 @@ void DAGTypeLegalizer::ExpandResult_TRUNCATE(SDNode *N, SDOperand &Lo, SDOperand &Hi) { - MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); Lo = DAG.getNode(ISD::TRUNCATE, NVT, N->getOperand(0)); Hi = DAG.getNode(ISD::SRL, N->getOperand(0).getValueType(), N->getOperand(0), - DAG.getConstant(MVT::getSizeInBits(NVT), + DAG.getConstant(NVT.getSizeInBits(), TLI.getShiftAmountTy())); Hi = DAG.getNode(ISD::TRUNCATE, NVT, Hi); } void DAGTypeLegalizer::ExpandResult_BIT_CONVERT(SDNode *N, SDOperand &Lo, SDOperand &Hi) { - MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDOperand InOp = N->getOperand(0); - MVT::ValueType InVT = InOp.getValueType(); + MVT InVT = InOp.getValueType(); // Handle some special cases efficiently. switch (getTypeAction(InVT)) { @@ -299,9 +299,9 @@ void DAGTypeLegalizer:: ExpandResult_SIGN_EXTEND_INREG(SDNode *N, SDOperand &Lo, SDOperand &Hi) { GetExpandedOp(N->getOperand(0), Lo, Hi); - MVT::ValueType EVT = cast(N->getOperand(1))->getVT(); + MVT EVT = cast(N->getOperand(1))->getVT(); - if (MVT::getSizeInBits(EVT) <= MVT::getSizeInBits(Lo.getValueType())) { + if (EVT.getSizeInBits() <= Lo.getValueType().getSizeInBits()) { // sext_inreg the low part if needed. Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, Lo.getValueType(), Lo, N->getOperand(1)); @@ -309,21 +309,21 @@ // The high part gets the sign extension from the lo-part. This handles // things like sextinreg V:i64 from i8. Hi = DAG.getNode(ISD::SRA, Hi.getValueType(), Lo, - DAG.getConstant(MVT::getSizeInBits(Hi.getValueType())-1, + DAG.getConstant(Hi.getValueType().getSizeInBits()-1, TLI.getShiftAmountTy())); } else { // For example, extension of an i48 to an i64. Leave the low part alone, // sext_inreg the high part. unsigned ExcessBits = - MVT::getSizeInBits(EVT) - MVT::getSizeInBits(Lo.getValueType()); + EVT.getSizeInBits() - Lo.getValueType().getSizeInBits(); Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi, - DAG.getValueType(MVT::getIntegerType(ExcessBits))); + DAG.getValueType(MVT::getIntegerVT(ExcessBits))); } } void DAGTypeLegalizer::ExpandResult_FP_TO_SINT(SDNode *N, SDOperand &Lo, SDOperand &Hi) { - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); SDOperand Op = N->getOperand(0); RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; if (VT == MVT::i64) { @@ -352,7 +352,7 @@ void DAGTypeLegalizer::ExpandResult_FP_TO_UINT(SDNode *N, SDOperand &Lo, SDOperand &Hi) { - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); SDOperand Op = N->getOperand(0); RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; if (VT == MVT::i64) { @@ -382,8 +382,8 @@ void DAGTypeLegalizer::ExpandResult_LOAD(LoadSDNode *N, SDOperand &Lo, SDOperand &Hi) { // FIXME: Add support for indexed loads. - MVT::ValueType VT = N->getValueType(0); - MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); + MVT VT = N->getValueType(0); + MVT NVT = TLI.getTypeToTransformTo(VT); SDOperand Ch = N->getChain(); // Legalize the chain. SDOperand Ptr = N->getBasePtr(); // Legalize the pointer. ISD::LoadExtType ExtType = N->getExtensionType(); @@ -391,13 +391,13 @@ unsigned Alignment = N->getAlignment(); bool isVolatile = N->isVolatile(); - assert(!(MVT::getSizeInBits(NVT) & 7) && "Expanded type not byte sized!"); + assert(!(NVT.getSizeInBits() & 7) && "Expanded type not byte sized!"); if (ExtType == ISD::NON_EXTLOAD) { Lo = DAG.getLoad(NVT, Ch, Ptr, N->getSrcValue(), SVOffset, isVolatile, Alignment); // Increment the pointer to the other half. - unsigned IncrementSize = MVT::getSizeInBits(NVT)/8; + unsigned IncrementSize = NVT.getSizeInBits()/8; Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, DAG.getIntPtrConstant(IncrementSize)); Hi = DAG.getLoad(NVT, Ch, Ptr, N->getSrcValue(), SVOffset+IncrementSize, @@ -411,8 +411,8 @@ // Handle endianness of the load. if (TLI.isBigEndian()) std::swap(Lo, Hi); - } else if (MVT::getSizeInBits(N->getMemoryVT()) <= MVT::getSizeInBits(NVT)) { - MVT::ValueType EVT = N->getMemoryVT(); + } else if (N->getMemoryVT().getSizeInBits() <= NVT.getSizeInBits()) { + MVT EVT = N->getMemoryVT(); Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, EVT, isVolatile, Alignment); @@ -423,7 +423,7 @@ if (ExtType == ISD::SEXTLOAD) { // The high part is obtained by SRA'ing all but one of the bits of the // lo part. - unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); + unsigned LoSize = Lo.getValueType().getSizeInBits(); Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); } else if (ExtType == ISD::ZEXTLOAD) { @@ -440,11 +440,11 @@ isVolatile, Alignment); unsigned ExcessBits = - MVT::getSizeInBits(N->getMemoryVT()) - MVT::getSizeInBits(NVT); - MVT::ValueType NEVT = MVT::getIntegerType(ExcessBits); + N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); + MVT NEVT = MVT::getIntegerVT(ExcessBits); // Increment the pointer to the other half. - unsigned IncrementSize = MVT::getSizeInBits(NVT)/8; + unsigned IncrementSize = NVT.getSizeInBits()/8; Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, DAG.getIntPtrConstant(IncrementSize)); Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), @@ -458,14 +458,14 @@ } else { // Big-endian - high bits are at low addresses. Favor aligned loads at // the cost of some bit-fiddling. - MVT::ValueType EVT = N->getMemoryVT(); - unsigned EBytes = MVT::getStoreSizeInBits(EVT)/8; - unsigned IncrementSize = MVT::getSizeInBits(NVT)/8; + MVT EVT = N->getMemoryVT(); + unsigned EBytes = EVT.getStoreSizeInBits()/8; + unsigned IncrementSize = NVT.getSizeInBits()/8; unsigned ExcessBits = (EBytes - IncrementSize)*8; // Load both the high bits and maybe some of the low bits. Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, - MVT::getIntegerType(MVT::getSizeInBits(EVT)-ExcessBits), + MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits), isVolatile, Alignment); // Increment the pointer to the other half. @@ -473,7 +473,8 @@ DAG.getIntPtrConstant(IncrementSize)); // Load the rest of the low bits. Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Ch, Ptr, N->getSrcValue(), - SVOffset+IncrementSize, MVT::getIntegerType(ExcessBits), + SVOffset+IncrementSize, + MVT::getIntegerVT(ExcessBits), isVolatile, MinAlign(Alignment, IncrementSize)); // Build a factor node to remember that this load is independent of the @@ -481,7 +482,7 @@ Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), Hi.getValue(1)); - if (ExcessBits < MVT::getSizeInBits(NVT)) { + if (ExcessBits < NVT.getSizeInBits()) { // Transfer low bits from the bottom of Hi to the top of Lo. Lo = DAG.getNode(ISD::OR, NVT, Lo, DAG.getNode(ISD::SHL, NVT, Hi, @@ -489,7 +490,7 @@ TLI.getShiftAmountTy()))); // Move high bits to the right position in Hi. Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, NVT, Hi, - DAG.getConstant(MVT::getSizeInBits(NVT) - ExcessBits, + DAG.getConstant(NVT.getSizeInBits() - ExcessBits, TLI.getShiftAmountTy())); } } @@ -602,8 +603,8 @@ void DAGTypeLegalizer::ExpandResult_MUL(SDNode *N, SDOperand &Lo, SDOperand &Hi) { - MVT::ValueType VT = N->getValueType(0); - MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); + MVT VT = N->getValueType(0); + MVT NVT = TLI.getTypeToTransformTo(VT); bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT); bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT); @@ -613,8 +614,8 @@ SDOperand LL, LH, RL, RH; GetExpandedOp(N->getOperand(0), LL, LH); GetExpandedOp(N->getOperand(1), RL, RH); - unsigned OuterBitSize = MVT::getSizeInBits(VT); - unsigned BitSize = MVT::getSizeInBits(NVT); + unsigned OuterBitSize = VT.getSizeInBits(); + unsigned BitSize = NVT.getSizeInBits(); unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0)); unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1)); @@ -705,7 +706,7 @@ void DAGTypeLegalizer::ExpandResult_Shift(SDNode *N, SDOperand &Lo, SDOperand &Hi) { - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // If we can emit an efficient shift operation, do so now. Check to see if // the RHS is a constant. @@ -730,7 +731,7 @@ // Next check to see if the target supports this SHL_PARTS operation or if it // will custom expand it. - MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); + MVT NVT = TLI.getTypeToTransformTo(VT); TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT); if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || Action == TargetLowering::Custom) { @@ -739,7 +740,7 @@ GetExpandedOp(N->getOperand(0), LHSL, LHSH); SDOperand Ops[] = { LHSL, LHSH, N->getOperand(1) }; - MVT::ValueType VT = LHSL.getValueType(); + MVT VT = LHSL.getValueType(); Lo = DAG.getNode(PartsOpc, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); Hi = Lo.getValue(1); return; @@ -770,7 +771,7 @@ SDOperand &Lo, SDOperand &Hi) { // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32) GetExpandedOp(N->getOperand(0), Lo, Hi); - MVT::ValueType NVT = Lo.getValueType(); + MVT NVT = Lo.getValueType(); SDOperand HiNotZero = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi, DAG.getConstant(0, NVT), ISD::SETNE); @@ -780,7 +781,7 @@ Lo = DAG.getNode(ISD::SELECT, NVT, HiNotZero, HiLZ, DAG.getNode(ISD::ADD, NVT, LoLZ, - DAG.getConstant(MVT::getSizeInBits(NVT), NVT))); + DAG.getConstant(NVT.getSizeInBits(), NVT))); Hi = DAG.getConstant(0, NVT); } @@ -788,7 +789,7 @@ SDOperand &Lo, SDOperand &Hi) { // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo) GetExpandedOp(N->getOperand(0), Lo, Hi); - MVT::ValueType NVT = Lo.getValueType(); + MVT NVT = Lo.getValueType(); Lo = DAG.getNode(ISD::ADD, NVT, DAG.getNode(ISD::CTPOP, NVT, Lo), DAG.getNode(ISD::CTPOP, NVT, Hi)); Hi = DAG.getConstant(0, NVT); @@ -798,7 +799,7 @@ SDOperand &Lo, SDOperand &Hi) { // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32) GetExpandedOp(N->getOperand(0), Lo, Hi); - MVT::ValueType NVT = Lo.getValueType(); + MVT NVT = Lo.getValueType(); SDOperand LoNotZero = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo, DAG.getConstant(0, NVT), ISD::SETNE); @@ -808,7 +809,7 @@ Lo = DAG.getNode(ISD::SELECT, NVT, LoNotZero, LoLZ, DAG.getNode(ISD::ADD, NVT, HiLZ, - DAG.getConstant(MVT::getSizeInBits(NVT), NVT))); + DAG.getConstant(NVT.getSizeInBits(), NVT))); Hi = DAG.getConstant(0, NVT); } @@ -816,25 +817,24 @@ SDOperand &Lo, SDOperand &Hi) { SDOperand OldVec = N->getOperand(0); - unsigned OldElts = MVT::getVectorNumElements(OldVec.getValueType()); + unsigned OldElts = OldVec.getValueType().getVectorNumElements(); // Convert to a vector of the expanded element type, for example // <2 x i64> -> <4 x i32>. - MVT::ValueType OldVT = N->getValueType(0); - MVT::ValueType NewVT = TLI.getTypeToTransformTo(OldVT); - assert(MVT::getSizeInBits(OldVT) == 2 * MVT::getSizeInBits(NewVT) && + MVT OldVT = N->getValueType(0); + MVT NewVT = TLI.getTypeToTransformTo(OldVT); + assert(OldVT.getSizeInBits() == 2 * NewVT.getSizeInBits() && "Do not know how to handle this expansion!"); SDOperand NewVec = DAG.getNode(ISD::BIT_CONVERT, - MVT::getVectorType(NewVT, 2 * OldElts), + MVT::getVectorVT(NewVT, 2*OldElts), OldVec); // Extract the elements at 2 * Idx and 2 * Idx + 1 from the new vector. SDOperand Idx = N->getOperand(1); // Make sure the type of Idx is big enough to hold the new values. - if (MVT::getSizeInBits(Idx.getValueType()) < - MVT::getSizeInBits(TLI.getPointerTy())) + if (Idx.getValueType().getSizeInBits() < TLI.getPointerTy().getSizeInBits()) Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx); Idx = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, Idx); @@ -856,10 +856,10 @@ SDOperand InL, InH; GetExpandedOp(N->getOperand(0), InL, InH); - MVT::ValueType NVT = InL.getValueType(); - unsigned VTBits = MVT::getSizeInBits(N->getValueType(0)); - unsigned NVTBits = MVT::getSizeInBits(NVT); - MVT::ValueType ShTy = N->getOperand(1).getValueType(); + MVT NVT = InL.getValueType(); + unsigned VTBits = N->getValueType(0).getSizeInBits(); + unsigned NVTBits = NVT.getSizeInBits(); + MVT ShTy = N->getOperand(1).getValueType(); if (N->getOpcode() == ISD::SHL) { if (Amt > VTBits) { @@ -932,10 +932,10 @@ bool DAGTypeLegalizer:: ExpandShiftWithKnownAmountBit(SDNode *N, SDOperand &Lo, SDOperand &Hi) { SDOperand Amt = N->getOperand(1); - MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0)); - MVT::ValueType ShTy = Amt.getValueType(); - MVT::ValueType ShBits = MVT::getSizeInBits(ShTy); - unsigned NVTBits = MVT::getSizeInBits(NVT); + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + MVT ShTy = Amt.getValueType(); + unsigned ShBits = ShTy.getSizeInBits(); + unsigned NVTBits = NVT.getSizeInBits(); assert(isPowerOf2_32(NVTBits) && "Expanded integer type size not a power of two!"); @@ -1077,14 +1077,14 @@ } SDOperand DAGTypeLegalizer::ExpandOperand_BIT_CONVERT(SDNode *N) { - if (MVT::isVector(N->getValueType(0))) { + if (N->getValueType(0).isVector()) { // An illegal integer type is being converted to a legal vector type. // Make a two element vector out of the expanded parts and convert that // instead, but only if the new vector type is legal (otherwise there // is no point, and it might create expansion loops). For example, on // x86 this turns v1i64 = BIT_CONVERT i64 into v1i64 = BIT_CONVERT v2i32. - MVT::ValueType OVT = N->getOperand(0).getValueType(); - MVT::ValueType NVT = MVT::getVectorType(TLI.getTypeToTransformTo(OVT), 2); + MVT OVT = N->getOperand(0).getValueType(); + MVT NVT = MVT::getVectorVT(TLI.getTypeToTransformTo(OVT), 2); if (isTypeLegal(NVT)) { SDOperand Parts[2]; @@ -1103,9 +1103,9 @@ } SDOperand DAGTypeLegalizer::ExpandOperand_SINT_TO_FP(SDOperand Source, - MVT::ValueType DestTy) { + MVT DestTy) { // We know the destination is legal, but that the input needs to be expanded. - MVT::ValueType SourceVT = Source.getValueType(); + MVT SourceVT = Source.getValueType(); // Check to see if the target has a custom way to lower this. If so, use it. switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) { @@ -1149,7 +1149,7 @@ } SDOperand DAGTypeLegalizer::ExpandOperand_UINT_TO_FP(SDOperand Source, - MVT::ValueType DestTy) { + MVT DestTy) { // We know the destination is legal, but that the input needs to be expanded. assert(getTypeAction(Source.getValueType()) == Expand && "This is not an expansion!"); @@ -1179,7 +1179,7 @@ SDOperand FudgeInReg; if (DestTy == MVT::f32) FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0); - else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32)) + else if (DestTy.getSizeInBits() > MVT(MVT::f32).getSizeInBits()) // FIXME: Avoid the extend by construction the right constantpool? FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(), CPIdx, NULL, 0, MVT::f32); @@ -1234,7 +1234,7 @@ GetExpandedOp(NewLHS, LHSLo, LHSHi); GetExpandedOp(NewRHS, RHSLo, RHSHi); - MVT::ValueType VT = NewLHS.getValueType(); + MVT VT = NewLHS.getValueType(); if (VT == MVT::ppcf128) { // FIXME: This generated code sucks. We want to generate // FCMP crN, hi1, hi2 @@ -1343,8 +1343,8 @@ // FIXME: Add support for indexed stores. assert(OpNo == 1 && "Can only expand the stored value so far"); - MVT::ValueType VT = N->getOperand(1).getValueType(); - MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); + MVT VT = N->getOperand(1).getValueType(); + MVT NVT = TLI.getTypeToTransformTo(VT); SDOperand Ch = N->getChain(); SDOperand Ptr = N->getBasePtr(); int SVOffset = N->getSrcValueOffset(); @@ -1352,12 +1352,12 @@ bool isVolatile = N->isVolatile(); SDOperand Lo, Hi; - assert(!(MVT::getSizeInBits(NVT) & 7) && "Expanded type not byte sized!"); + assert(!(NVT.getSizeInBits() & 7) && "Expanded type not byte sized!"); if (!N->isTruncatingStore()) { unsigned IncrementSize = 0; GetExpandedOp(N->getValue(), Lo, Hi); - IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8; + IncrementSize = Hi.getValueType().getSizeInBits()/8; if (TLI.isBigEndian()) std::swap(Lo, Hi); @@ -1371,7 +1371,7 @@ Hi = DAG.getStore(Ch, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize, isVolatile, MinAlign(Alignment, IncrementSize)); return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); - } else if (MVT::getSizeInBits(N->getMemoryVT()) <= MVT::getSizeInBits(NVT)) { + } else if (N->getMemoryVT().getSizeInBits() <= NVT.getSizeInBits()) { GetExpandedOp(N->getValue(), Lo, Hi); return DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset, N->getMemoryVT(), isVolatile, Alignment); @@ -1383,11 +1383,11 @@ isVolatile, Alignment); unsigned ExcessBits = - MVT::getSizeInBits(N->getMemoryVT()) - MVT::getSizeInBits(NVT); - MVT::ValueType NEVT = MVT::getIntegerType(ExcessBits); + N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); + MVT NEVT = MVT::getIntegerVT(ExcessBits); // Increment the pointer to the other half. - unsigned IncrementSize = MVT::getSizeInBits(NVT)/8; + unsigned IncrementSize = NVT.getSizeInBits()/8; Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, DAG.getIntPtrConstant(IncrementSize)); Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(), @@ -1399,17 +1399,16 @@ // the cost of some bit-fiddling. GetExpandedOp(N->getValue(), Lo, Hi); - MVT::ValueType EVT = N->getMemoryVT(); - unsigned EBytes = MVT::getStoreSizeInBits(EVT)/8; - unsigned IncrementSize = MVT::getSizeInBits(NVT)/8; + MVT EVT = N->getMemoryVT(); + unsigned EBytes = EVT.getStoreSizeInBits()/8; + unsigned IncrementSize = NVT.getSizeInBits()/8; unsigned ExcessBits = (EBytes - IncrementSize)*8; - MVT::ValueType HiVT = - MVT::getIntegerType(MVT::getSizeInBits(EVT)-ExcessBits); + MVT HiVT = MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits); - if (ExcessBits < MVT::getSizeInBits(NVT)) { + if (ExcessBits < NVT.getSizeInBits()) { // Transfer high bits from the top of Lo to the bottom of Hi. Hi = DAG.getNode(ISD::SHL, NVT, Hi, - DAG.getConstant(MVT::getSizeInBits(NVT) - ExcessBits, + DAG.getConstant(NVT.getSizeInBits() - ExcessBits, TLI.getShiftAmountTy())); Hi = DAG.getNode(ISD::OR, NVT, Hi, DAG.getNode(ISD::SRL, NVT, Lo, @@ -1427,7 +1426,7 @@ // Store the lowest ExcessBits bits in the second half. Lo = DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset+IncrementSize, - MVT::getIntegerType(ExcessBits), + MVT::getIntegerVT(ExcessBits), isVolatile, MinAlign(Alignment, IncrementSize)); return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); } @@ -1435,12 +1434,12 @@ SDOperand DAGTypeLegalizer::ExpandOperand_BUILD_VECTOR(SDNode *N) { // The vector type is legal but the element type needs expansion. - MVT::ValueType VecVT = N->getValueType(0); - unsigned NumElts = MVT::getVectorNumElements(VecVT); - MVT::ValueType OldVT = N->getOperand(0).getValueType(); - MVT::ValueType NewVT = TLI.getTypeToTransformTo(OldVT); + MVT VecVT = N->getValueType(0); + unsigned NumElts = VecVT.getVectorNumElements(); + MVT OldVT = N->getOperand(0).getValueType(); + MVT NewVT = TLI.getTypeToTransformTo(OldVT); - assert(MVT::getSizeInBits(OldVT) == 2 * MVT::getSizeInBits(NewVT) && + assert(OldVT.getSizeInBits() == 2 * NewVT.getSizeInBits() && "Do not know how to expand this operand!"); // Build a vector of twice the length out of the expanded elements. @@ -1458,7 +1457,7 @@ } SDOperand NewVec = DAG.getNode(ISD::BUILD_VECTOR, - MVT::getVectorType(NewVT, NewElts.size()), + MVT::getVectorVT(NewVT, NewElts.size()), &NewElts[0], NewElts.size()); // Convert the new vector to the old vector type. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesFloatToInt.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesFloatToInt.cpp?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesFloatToInt.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesFloatToInt.cpp Fri Jun 6 07:08:01 2008 @@ -21,7 +21,7 @@ using namespace llvm; /// GetFPLibCall - Return the right libcall for the given floating point type. -static RTLIB::Libcall GetFPLibCall(MVT::ValueType VT, +static RTLIB::Libcall GetFPLibCall(MVT VT, RTLIB::Libcall Call_F32, RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80, @@ -105,7 +105,7 @@ } SDOperand DAGTypeLegalizer::FloatToIntRes_FADD(SDNode *N) { - MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDOperand Ops[2] = { GetIntegerOp(N->getOperand(0)), GetIntegerOp(N->getOperand(1)) }; return MakeLibCall(GetFPLibCall(N->getValueType(0), @@ -120,11 +120,11 @@ SDOperand LHS = GetIntegerOp(N->getOperand(0)); SDOperand RHS = BitConvertToInteger(N->getOperand(1)); - MVT::ValueType LVT = LHS.getValueType(); - MVT::ValueType RVT = RHS.getValueType(); + MVT LVT = LHS.getValueType(); + MVT RVT = RHS.getValueType(); - unsigned LSize = MVT::getSizeInBits(LVT); - unsigned RSize = MVT::getSizeInBits(RVT); + unsigned LSize = LVT.getSizeInBits(); + unsigned RSize = RVT.getSizeInBits(); // First get the sign bit of second operand. SDOperand SignBit = DAG.getNode(ISD::SHL, RVT, DAG.getConstant(1, RVT), @@ -133,7 +133,7 @@ SignBit = DAG.getNode(ISD::AND, RVT, RHS, SignBit); // Shift right or sign-extend it if the two operands have different types. - int SizeDiff = MVT::getSizeInBits(RVT) - MVT::getSizeInBits(LVT); + int SizeDiff = RVT.getSizeInBits() - LVT.getSizeInBits(); if (SizeDiff > 0) { SignBit = DAG.getNode(ISD::SRL, RVT, SignBit, DAG.getConstant(SizeDiff, TLI.getShiftAmountTy())); @@ -156,7 +156,7 @@ } SDOperand DAGTypeLegalizer::FloatToIntRes_FMUL(SDNode *N) { - MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDOperand Ops[2] = { GetIntegerOp(N->getOperand(0)), GetIntegerOp(N->getOperand(1)) }; return MakeLibCall(GetFPLibCall(N->getValueType(0), @@ -168,7 +168,7 @@ } SDOperand DAGTypeLegalizer::FloatToIntRes_FSUB(SDNode *N) { - MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDOperand Ops[2] = { GetIntegerOp(N->getOperand(0)), GetIntegerOp(N->getOperand(1)) }; return MakeLibCall(GetFPLibCall(N->getValueType(0), @@ -181,8 +181,8 @@ SDOperand DAGTypeLegalizer::FloatToIntRes_LOAD(SDNode *N) { LoadSDNode *L = cast(N); - MVT::ValueType VT = N->getValueType(0); - MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); + MVT VT = N->getValueType(0); + MVT NVT = TLI.getTypeToTransformTo(VT); if (L->getExtensionType() == ISD::NON_EXTLOAD) return DAG.getLoad(L->getAddressingMode(), L->getExtensionType(), @@ -202,7 +202,7 @@ SDOperand DAGTypeLegalizer::FloatToIntRes_XINT_TO_FP(SDNode *N) { bool isSigned = N->getOpcode() == ISD::SINT_TO_FP; - MVT::ValueType DestVT = N->getValueType(0); + MVT DestVT = N->getValueType(0); SDOperand Op = N->getOperand(0); if (Op.getValueType() == MVT::i32) { @@ -212,8 +212,9 @@ SDOperand StackSlot = DAG.CreateStackTemporary(MVT::f64); // word offset constant for Hi/Lo address computation - SDOperand Offset = DAG.getConstant(MVT::getSizeInBits(MVT::i32) / 8, - TLI.getPointerTy()); + SDOperand Offset = + DAG.getConstant(MVT(MVT::i32).getSizeInBits() / 8, + TLI.getPointerTy()); // set up Hi and Lo (into buffer) address based on endian SDOperand Hi = StackSlot; SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, Offset); @@ -251,10 +252,12 @@ if (DestVT == MVT::f64) { // do nothing Result = Sub; - } else if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(MVT::f64)) { + } else if (DestVT.getSizeInBits() < + MVT(MVT::f64).getSizeInBits()) { Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub, DAG.getIntPtrConstant(0)); - } else if (MVT::getSizeInBits(DestVT) > MVT::getSizeInBits(MVT::f64)) { + } else if (DestVT.getSizeInBits() > + MVT(MVT::f64).getSizeInBits()) { Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub); } return BitConvertToInteger(Result); @@ -273,7 +276,7 @@ // as a negative number. To counteract this, the dynamic code adds an // offset depending on the data type. uint64_t FF; - switch (Op.getValueType()) { + switch (Op.getValueType().getSimpleVT()) { default: assert(0 && "Unsupported integer type!"); case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp Fri Jun 6 07:08:01 2008 @@ -91,7 +91,7 @@ } SDOperand DAGTypeLegalizer::PromoteResult_Constant(SDNode *N) { - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // Zero extend things like i1, sign extend everything else. It shouldn't // matter in theory which one we pick, but this tends to give better code? unsigned Opc = VT != MVT::i1 ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; @@ -115,8 +115,8 @@ break; } - MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0)); - assert(MVT::getSizeInBits(Res.getValueType()) >= MVT::getSizeInBits(NVT) && + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + assert(Res.getValueType().getSizeInBits() >= NVT.getSizeInBits() && "Truncation doesn't make sense!"); if (Res.getValueType() == NVT) return Res; @@ -126,11 +126,11 @@ } SDOperand DAGTypeLegalizer::PromoteResult_INT_EXTEND(SDNode *N) { - MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); if (getTypeAction(N->getOperand(0).getValueType()) == Promote) { SDOperand Res = GetPromotedOp(N->getOperand(0)); - assert(MVT::getSizeInBits(Res.getValueType()) <= MVT::getSizeInBits(NVT) && + assert(Res.getValueType().getSizeInBits() <= NVT.getSizeInBits() && "Extension doesn't make sense!"); // If the result and operand types are the same after promotion, simplify @@ -168,7 +168,7 @@ Op = GetPromotedOp(Op); unsigned NewOpc = N->getOpcode(); - MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); // If we're promoting a UINT to a larger size, check to see if the new node // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since @@ -194,7 +194,7 @@ SDOperand DAGTypeLegalizer::PromoteResult_LOAD(LoadSDNode *N) { // FIXME: Add support for indexed loads. - MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType(); SDOperand Res = DAG.getExtLoad(ExtType, NVT, N->getChain(), N->getBasePtr(), @@ -218,9 +218,9 @@ SDOperand DAGTypeLegalizer::PromoteResult_BIT_CONVERT(SDNode *N) { SDOperand InOp = N->getOperand(0); - MVT::ValueType InVT = InOp.getValueType(); - MVT::ValueType NInVT = TLI.getTypeToTransformTo(InVT); - MVT::ValueType OutVT = TLI.getTypeToTransformTo(N->getValueType(0)); + MVT InVT = InOp.getValueType(); + MVT NInVT = TLI.getTypeToTransformTo(InVT); + MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0)); switch (getTypeAction(InVT)) { default: @@ -229,7 +229,7 @@ case Legal: break; case Promote: - if (MVT::getSizeInBits(OutVT) == MVT::getSizeInBits(NInVT)) + if (OutVT.getSizeInBits() == NInVT.getSizeInBits()) // The input promotes to the same size. Convert the promoted value. return DAG.getNode(ISD::BIT_CONVERT, OutVT, GetPromotedOp(InOp)); break; @@ -254,7 +254,7 @@ std::swap(Lo, Hi); InOp = DAG.getNode(ISD::ANY_EXTEND, - MVT::getIntegerType(MVT::getSizeInBits(OutVT)), + MVT::getIntegerVT(OutVT.getSizeInBits()), JoinIntegers(Lo, Hi)); return DAG.getNode(ISD::BIT_CONVERT, OutVT, InOp); } @@ -278,7 +278,7 @@ // Sign extend the input. SDOperand LHS = GetPromotedOp(N->getOperand(0)); SDOperand RHS = GetPromotedOp(N->getOperand(1)); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); LHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, LHS.getValueType(), LHS, DAG.getValueType(VT)); RHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, RHS.getValueType(), RHS, @@ -291,7 +291,7 @@ // Zero extend the input. SDOperand LHS = GetPromotedOp(N->getOperand(0)); SDOperand RHS = GetPromotedOp(N->getOperand(1)); - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); LHS = DAG.getZeroExtendInReg(LHS, VT); RHS = DAG.getZeroExtendInReg(RHS, VT); @@ -305,8 +305,8 @@ SDOperand DAGTypeLegalizer::PromoteResult_SRA(SDNode *N) { // The input value must be properly sign extended. - MVT::ValueType VT = N->getValueType(0); - MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); + MVT VT = N->getValueType(0); + MVT NVT = TLI.getTypeToTransformTo(VT); SDOperand Res = GetPromotedOp(N->getOperand(0)); Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res, DAG.getValueType(VT)); return DAG.getNode(ISD::SRA, NVT, Res, N->getOperand(1)); @@ -314,8 +314,8 @@ SDOperand DAGTypeLegalizer::PromoteResult_SRL(SDNode *N) { // The input value must be properly zero extended. - MVT::ValueType VT = N->getValueType(0); - MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); + MVT VT = N->getValueType(0); + MVT NVT = TLI.getTypeToTransformTo(VT); SDOperand Res = GetPromotedZExtOp(N->getOperand(0)); return DAG.getNode(ISD::SRL, NVT, Res, N->getOperand(1)); } @@ -335,41 +335,41 @@ SDOperand DAGTypeLegalizer::PromoteResult_CTLZ(SDNode *N) { SDOperand Op = GetPromotedOp(N->getOperand(0)); - MVT::ValueType OVT = N->getValueType(0); - MVT::ValueType NVT = Op.getValueType(); + MVT OVT = N->getValueType(0); + MVT NVT = Op.getValueType(); // Zero extend to the promoted type and do the count there. Op = DAG.getNode(ISD::CTLZ, NVT, DAG.getZeroExtendInReg(Op, OVT)); // Subtract off the extra leading bits in the bigger type. return DAG.getNode(ISD::SUB, NVT, Op, - DAG.getConstant(MVT::getSizeInBits(NVT) - - MVT::getSizeInBits(OVT), NVT)); + DAG.getConstant(NVT.getSizeInBits() - + OVT.getSizeInBits(), NVT)); } SDOperand DAGTypeLegalizer::PromoteResult_CTPOP(SDNode *N) { SDOperand Op = GetPromotedOp(N->getOperand(0)); - MVT::ValueType OVT = N->getValueType(0); - MVT::ValueType NVT = Op.getValueType(); + MVT OVT = N->getValueType(0); + MVT NVT = Op.getValueType(); // Zero extend to the promoted type and do the count there. return DAG.getNode(ISD::CTPOP, NVT, DAG.getZeroExtendInReg(Op, OVT)); } SDOperand DAGTypeLegalizer::PromoteResult_CTTZ(SDNode *N) { SDOperand Op = GetPromotedOp(N->getOperand(0)); - MVT::ValueType OVT = N->getValueType(0); - MVT::ValueType NVT = Op.getValueType(); + MVT OVT = N->getValueType(0); + MVT NVT = Op.getValueType(); // The count is the same in the promoted type except if the original // value was zero. This can be handled by setting the bit just off // the top of the original type. Op = DAG.getNode(ISD::OR, NVT, Op, // FIXME: Do this using an APINT constant. - DAG.getConstant(1UL << MVT::getSizeInBits(OVT), NVT)); + DAG.getConstant(1UL << OVT.getSizeInBits(), NVT)); return DAG.getNode(ISD::CTTZ, NVT, Op); } SDOperand DAGTypeLegalizer::PromoteResult_EXTRACT_VECTOR_ELT(SDNode *N) { - MVT::ValueType OldVT = N->getValueType(0); + MVT OldVT = N->getValueType(0); SDOperand OldVec = N->getOperand(0); - unsigned OldElts = MVT::getVectorNumElements(OldVec.getValueType()); + unsigned OldElts = OldVec.getValueType().getVectorNumElements(); if (OldElts == 1) { assert(!isTypeLegal(OldVec.getValueType()) && @@ -384,11 +384,11 @@ // Convert to a vector half as long with an element type of twice the width, // for example <4 x i16> -> <2 x i32>. assert(!(OldElts & 1) && "Odd length vectors not supported!"); - MVT::ValueType NewVT = MVT::getIntegerType(2 * MVT::getSizeInBits(OldVT)); - assert(!MVT::isExtendedVT(OldVT) && !MVT::isExtendedVT(NewVT)); + MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits()); + assert(OldVT.isSimple() && NewVT.isSimple()); SDOperand NewVec = DAG.getNode(ISD::BIT_CONVERT, - MVT::getVectorType(NewVT, OldElts / 2), + MVT::getVectorVT(NewVT, OldElts / 2), OldVec); // Extract the element at OldIdx / 2 from the new vector. @@ -401,7 +401,7 @@ // Hi if it was odd. SDOperand Lo = Elt; SDOperand Hi = DAG.getNode(ISD::SRL, NewVT, Elt, - DAG.getConstant(MVT::getSizeInBits(OldVT), + DAG.getConstant(OldVT.getSizeInBits(), TLI.getShiftAmountTy())); if (TLI.isBigEndian()) std::swap(Lo, Hi); @@ -513,7 +513,7 @@ SDOperand DAGTypeLegalizer::PromoteOperand_INT_TO_FP(SDNode *N) { SDOperand In = GetPromotedOp(N->getOperand(0)); - MVT::ValueType OpVT = N->getOperand(0).getValueType(); + MVT OpVT = N->getOperand(0).getValueType(); if (N->getOpcode() == ISD::UINT_TO_FP) In = DAG.getZeroExtendInReg(In, OpVT); else @@ -525,14 +525,14 @@ SDOperand DAGTypeLegalizer::PromoteOperand_BUILD_PAIR(SDNode *N) { // Since the result type is legal, the operands must promote to it. - MVT::ValueType OVT = N->getOperand(0).getValueType(); + MVT OVT = N->getOperand(0).getValueType(); SDOperand Lo = GetPromotedOp(N->getOperand(0)); SDOperand Hi = GetPromotedOp(N->getOperand(1)); assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?"); Lo = DAG.getZeroExtendInReg(Lo, OVT); Hi = DAG.getNode(ISD::SHL, N->getValueType(0), Hi, - DAG.getConstant(MVT::getSizeInBits(OVT), + DAG.getConstant(OVT.getSizeInBits(), TLI.getShiftAmountTy())); return DAG.getNode(ISD::OR, N->getValueType(0), Lo, Hi); } @@ -597,14 +597,14 @@ /// shared among BR_CC, SELECT_CC, and SETCC handlers. void DAGTypeLegalizer::PromoteSetCCOperands(SDOperand &NewLHS,SDOperand &NewRHS, ISD::CondCode CCCode) { - MVT::ValueType VT = NewLHS.getValueType(); + MVT VT = NewLHS.getValueType(); // Get the promoted values. NewLHS = GetPromotedOp(NewLHS); NewRHS = GetPromotedOp(NewRHS); // If this is an FP compare, the operands have already been extended. - if (!MVT::isInteger(NewLHS.getValueType())) + if (!NewLHS.getValueType().isInteger()) return; // Otherwise, we have to insert explicit sign or zero extends. Note @@ -658,15 +658,15 @@ // The vector type is legal but the element type is not. This implies // that the vector is a power-of-two in length and that the element // type does not have a strange size (eg: it is not i1). - MVT::ValueType VecVT = N->getValueType(0); - unsigned NumElts = MVT::getVectorNumElements(VecVT); + MVT VecVT = N->getValueType(0); + unsigned NumElts = VecVT.getVectorNumElements(); assert(!(NumElts & 1) && "Legal vector of one illegal element?"); // Build a vector of half the length out of elements of twice the bitwidth. // For example <4 x i16> -> <2 x i32>. - MVT::ValueType OldVT = N->getOperand(0).getValueType(); - MVT::ValueType NewVT = MVT::getIntegerType(2 * MVT::getSizeInBits(OldVT)); - assert(!MVT::isExtendedVT(OldVT) && !MVT::isExtendedVT(NewVT)); + MVT OldVT = N->getOperand(0).getValueType(); + MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits()); + assert(OldVT.isSimple() && NewVT.isSimple()); std::vector NewElts; NewElts.reserve(NumElts/2); @@ -681,7 +681,7 @@ } SDOperand NewVec = DAG.getNode(ISD::BUILD_VECTOR, - MVT::getVectorType(NewVT, NewElts.size()), + MVT::getVectorVT(NewVT, NewElts.size()), &NewElts[0], NewElts.size()); // Convert the new vector to the old vector type. @@ -695,8 +695,8 @@ // have to match the vector element type. // Check that any extra bits introduced will be truncated away. - assert(MVT::getSizeInBits(N->getOperand(1).getValueType()) >= - MVT::getSizeInBits(MVT::getVectorElementType(N->getValueType(0))) && + assert(N->getOperand(1).getValueType().getSizeInBits() >= + N->getValueType(0).getVectorElementType().getSizeInBits() && "Type of inserted value narrower than vector element type!"); return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0), GetPromotedOp(N->getOperand(1)), Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesScalarize.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesScalarize.cpp?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesScalarize.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesScalarize.cpp Fri Jun 6 07:08:01 2008 @@ -89,12 +89,12 @@ } SDOperand DAGTypeLegalizer::ScalarizeRes_UNDEF(SDNode *N) { - return DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(N->getValueType(0))); + return DAG.getNode(ISD::UNDEF, N->getValueType(0).getVectorElementType()); } SDOperand DAGTypeLegalizer::ScalarizeRes_LOAD(LoadSDNode *N) { // FIXME: Add support for indexed loads. - SDOperand Result = DAG.getLoad(MVT::getVectorElementType(N->getValueType(0)), + SDOperand Result = DAG.getLoad(N->getValueType(0).getVectorElementType(), N->getChain(), N->getBasePtr(), N->getSrcValue(), N->getSrcValueOffset(), N->isVolatile(), N->getAlignment()); @@ -125,8 +125,8 @@ // The value to insert may have a wider type than the vector element type, // so be sure to truncate it to the element type if necessary. SDOperand Op = N->getOperand(1); - MVT::ValueType EltVT = MVT::getVectorElementType(N->getValueType(0)); - if (MVT::getSizeInBits(Op.getValueType()) > MVT::getSizeInBits(EltVT)) + MVT EltVT = N->getValueType(0).getVectorElementType(); + if (Op.getValueType().getSizeInBits() > EltVT.getSizeInBits()) Op = DAG.getNode(ISD::TRUNCATE, EltVT, Op); assert(Op.getValueType() == EltVT && "Invalid type for inserted value!"); return Op; @@ -140,7 +140,7 @@ } SDOperand DAGTypeLegalizer::ScalarizeRes_BIT_CONVERT(SDNode *N) { - MVT::ValueType NewVT = MVT::getVectorElementType(N->getValueType(0)); + MVT NewVT = N->getValueType(0).getVectorElementType(); return DAG.getNode(ISD::BIT_CONVERT, NewVT, N->getOperand(0)); } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesSplit.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesSplit.cpp?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesSplit.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesSplit.cpp Fri Jun 6 07:08:01 2008 @@ -19,18 +19,17 @@ /// GetSplitDestVTs - Compute the VTs needed for the low/hi parts of a vector /// type that needs to be split. This handles non-power of two vectors. -static void GetSplitDestVTs(MVT::ValueType InVT, - MVT::ValueType &Lo, MVT::ValueType &Hi) { - MVT::ValueType NewEltVT = MVT::getVectorElementType(InVT); - unsigned NumElements = MVT::getVectorNumElements(InVT); +static void GetSplitDestVTs(MVT InVT, MVT &Lo, MVT &Hi) { + MVT NewEltVT = InVT.getVectorElementType(); + unsigned NumElements = InVT.getVectorNumElements(); if ((NumElements & (NumElements-1)) == 0) { // Simple power of two vector. NumElements >>= 1; - Lo = Hi = MVT::getVectorType(NewEltVT, NumElements); + Lo = Hi = MVT::getVectorVT(NewEltVT, NumElements); } else { // Non-power-of-two vectors. unsigned NewNumElts_Lo = 1 << Log2_32(NumElements); unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo; - Lo = MVT::getVectorType(NewEltVT, NewNumElts_Lo); - Hi = MVT::getVectorType(NewEltVT, NewNumElts_Hi); + Lo = MVT::getVectorVT(NewEltVT, NewNumElts_Lo); + Hi = MVT::getVectorVT(NewEltVT, NewNumElts_Hi); } } @@ -117,7 +116,7 @@ } void DAGTypeLegalizer::SplitRes_UNDEF(SDNode *N, SDOperand &Lo, SDOperand &Hi) { - MVT::ValueType LoVT, HiVT; + MVT LoVT, HiVT; GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); Lo = DAG.getNode(ISD::UNDEF, LoVT); @@ -127,7 +126,7 @@ void DAGTypeLegalizer::SplitRes_LOAD(LoadSDNode *LD, SDOperand &Lo, SDOperand &Hi) { // FIXME: Add support for indexed loads. - MVT::ValueType LoVT, HiVT; + MVT LoVT, HiVT; GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT); SDOperand Ch = LD->getChain(); @@ -138,7 +137,7 @@ bool isVolatile = LD->isVolatile(); Lo = DAG.getLoad(LoVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); - unsigned IncrementSize = MVT::getSizeInBits(LoVT)/8; + unsigned IncrementSize = LoVT.getSizeInBits()/8; Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, DAG.getIntPtrConstant(IncrementSize)); SVOffset += IncrementSize; @@ -166,7 +165,7 @@ GetSplitOp(N->getOperand(0), Lo, Hi); unsigned Index = cast(N->getOperand(2))->getValue(); SDOperand ScalarOp = N->getOperand(1); - unsigned LoNumElts = MVT::getVectorNumElements(Lo.getValueType()); + unsigned LoNumElts = Lo.getValueType().getVectorNumElements(); if (Index < LoNumElts) Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, Lo.getValueType(), Lo, ScalarOp, N->getOperand(2)); @@ -180,10 +179,10 @@ // Build the low part. SDOperand Mask = N->getOperand(2); SmallVector Ops; - MVT::ValueType LoVT, HiVT; + MVT LoVT, HiVT; GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); - MVT::ValueType EltVT = MVT::getVectorElementType(LoVT); - unsigned LoNumElts = MVT::getVectorNumElements(LoVT); + MVT EltVT = LoVT.getVectorElementType(); + unsigned LoNumElts = LoVT.getVectorNumElements(); unsigned NumElements = Mask.getNumOperands(); // Insert all of the elements from the input that are needed. We use @@ -217,9 +216,9 @@ void DAGTypeLegalizer::SplitRes_BUILD_VECTOR(SDNode *N, SDOperand &Lo, SDOperand &Hi) { - MVT::ValueType LoVT, HiVT; + MVT LoVT, HiVT; GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); - unsigned LoNumElts = MVT::getVectorNumElements(LoVT); + unsigned LoNumElts = LoVT.getVectorNumElements(); SmallVector LoOps(N->op_begin(), N->op_begin()+LoNumElts); Lo = DAG.getNode(ISD::BUILD_VECTOR, LoVT, &LoOps[0], LoOps.size()); @@ -237,7 +236,7 @@ return; } - MVT::ValueType LoVT, HiVT; + MVT LoVT, HiVT; GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); SmallVector LoOps(N->op_begin(), N->op_begin()+NumSubvectors); @@ -251,11 +250,11 @@ SDOperand &Lo, SDOperand &Hi) { // We know the result is a vector. The input may be either a vector or a // scalar value. - MVT::ValueType LoVT, HiVT; + MVT LoVT, HiVT; GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); SDOperand InOp = N->getOperand(0); - MVT::ValueType InVT = InOp.getValueType(); + MVT InVT = InOp.getValueType(); // Handle some special cases efficiently. switch (getTypeAction(InVT)) { @@ -289,8 +288,8 @@ } // In the general case, convert the input to an integer and split it by hand. - MVT::ValueType LoIntVT = MVT::getIntegerType(MVT::getSizeInBits(LoVT)); - MVT::ValueType HiIntVT = MVT::getIntegerType(MVT::getSizeInBits(HiVT)); + MVT LoIntVT = MVT::getIntegerVT(LoVT.getSizeInBits()); + MVT HiIntVT = MVT::getIntegerVT(HiVT.getSizeInBits()); if (TLI.isBigEndian()) std::swap(LoIntVT, HiIntVT); @@ -314,7 +313,7 @@ void DAGTypeLegalizer::SplitRes_UnOp(SDNode *N, SDOperand &Lo, SDOperand &Hi) { // Get the dest types. This doesn't always match input types, e.g. int_to_fp. - MVT::ValueType LoVT, HiVT; + MVT LoVT, HiVT; GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); GetSplitOp(N->getOperand(0), Lo, Hi); @@ -410,7 +409,7 @@ SDOperand Lo, Hi; GetSplitOp(N->getOperand(1), Lo, Hi); - unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; + unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8; Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset, isVol, Alignment); @@ -455,17 +454,16 @@ SDOperand DAGTypeLegalizer::SplitOp_EXTRACT_VECTOR_ELT(SDNode *N) { SDOperand Vec = N->getOperand(0); SDOperand Idx = N->getOperand(1); - MVT::ValueType VecVT = Vec.getValueType(); + MVT VecVT = Vec.getValueType(); if (isa(Idx)) { uint64_t IdxVal = cast(Idx)->getValue(); - assert(IdxVal < MVT::getVectorNumElements(VecVT) && - "Invalid vector index!"); + assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!"); SDOperand Lo, Hi; GetSplitOp(Vec, Lo, Hi); - uint64_t LoElts = MVT::getVectorNumElements(Lo.getValueType()); + uint64_t LoElts = Lo.getValueType().getVectorNumElements(); if (IdxVal < LoElts) return DAG.UpdateNodeOperands(SDOperand(N, 0), Lo, Idx); @@ -480,13 +478,12 @@ SDOperand Store = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0); // Add the offset to the index. - MVT::ValueType EltVT = MVT::getVectorElementType(VecVT); - unsigned EltSize = MVT::getSizeInBits(EltVT)/8; // FIXME: should be ABI size. + MVT EltVT = VecVT.getVectorElementType(); + unsigned EltSize = EltVT.getSizeInBits()/8; // FIXME: should be ABI size. Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx, DAG.getConstant(EltSize, Idx.getValueType())); - if (MVT::getSizeInBits(Idx.getValueType()) > - MVT::getSizeInBits(TLI.getPointerTy())) + if (Idx.getValueType().getSizeInBits() > TLI.getPointerTy().getSizeInBits()) Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx); else Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx); @@ -498,16 +495,16 @@ SDOperand DAGTypeLegalizer::SplitOp_EXTRACT_SUBVECTOR(SDNode *N) { // We know that the extracted result type is legal. For now, assume the index // is a constant. - MVT::ValueType SubVT = N->getValueType(0); + MVT SubVT = N->getValueType(0); SDOperand Idx = N->getOperand(1); SDOperand Lo, Hi; GetSplitOp(N->getOperand(0), Lo, Hi); - uint64_t LoElts = MVT::getVectorNumElements(Lo.getValueType()); + uint64_t LoElts = Lo.getValueType().getVectorNumElements(); uint64_t IdxVal = cast(Idx)->getValue(); if (IdxVal < LoElts) { - assert(IdxVal + MVT::getVectorNumElements(SubVT) <= LoElts && + assert(IdxVal + SubVT.getVectorNumElements() <= LoElts && "Extracted subvector crosses vector split!"); return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SubVT, Lo, Idx); } else { @@ -519,7 +516,7 @@ SDOperand DAGTypeLegalizer::SplitOp_VECTOR_SHUFFLE(SDNode *N, unsigned OpNo) { assert(OpNo == 2 && "Shuffle source type differs from result type?"); SDOperand Mask = N->getOperand(2); - unsigned MaskLength = MVT::getVectorNumElements(Mask.getValueType()); + unsigned MaskLength = Mask.getValueType().getVectorNumElements(); unsigned LargestMaskEntryPlusOne = 2 * MaskLength; unsigned MinimumBitWidth = Log2_32_Ceil(LargestMaskEntryPlusOne); @@ -532,12 +529,12 @@ EltVT = MVT::SimpleValueType(EltVT + 1)) { // Is the element type big enough to hold the values? - if (MVT::getSizeInBits(EltVT) < MinimumBitWidth) + if (MVT(EltVT).getSizeInBits() < MinimumBitWidth) // Nope. continue; // Is the vector type legal? - MVT::ValueType VecVT = MVT::getVectorType(EltVT, MaskLength); + MVT VecVT = MVT::getVectorVT(EltVT, MaskLength); if (!isTypeLegal(VecVT)) // Nope. continue; Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Fri Jun 6 07:08:01 2008 @@ -191,7 +191,7 @@ assert(OpSU && "Node has no SUnit!"); if (OpSU == SU) continue; // In the same group. - MVT::ValueType OpVT = N->getOperand(i).getValueType(); + MVT OpVT = N->getOperand(i).getValueType(); assert(OpVT != MVT::Flag && "Flagged nodes should be in same sunit!"); bool isChain = OpVT == MVT::Other; @@ -433,7 +433,7 @@ SDOperand Op = Use->getOperand(i); if (Op.Val != Node || Op.ResNo != ResNo) continue; - MVT::ValueType VT = Node->getValueType(Op.ResNo); + MVT VT = Node->getValueType(Op.ResNo); if (VT != MVT::Other && VT != MVT::Flag) Match = false; } @@ -677,7 +677,7 @@ static const TargetRegisterClass *getSuperregRegisterClass( const TargetRegisterClass *TRC, unsigned SubIdx, - MVT::ValueType VT) { + MVT VT) { // Pick the register class of the superegister for this type for (TargetRegisterInfo::regclass_iterator I = TRC->superregclasses_begin(), E = TRC->superregclasses_end(); I != E; ++I) Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Fri Jun 6 07:08:01 2008 @@ -646,7 +646,7 @@ SUnit *NewSU; bool TryUnfold = false; for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) { - MVT::ValueType VT = N->getValueType(i); + MVT VT = N->getValueType(i); if (VT == MVT::Flag) return NULL; else if (VT == MVT::Other) @@ -654,7 +654,7 @@ } for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { const SDOperand &Op = N->getOperand(i); - MVT::ValueType VT = Op.Val->getValueType(Op.ResNo); + MVT VT = Op.Val->getValueType(Op.ResNo); if (VT == MVT::Flag) return NULL; } @@ -872,8 +872,8 @@ /// getPhysicalRegisterVT - Returns the ValueType of the physical register /// definition of the specified node. /// FIXME: Move to SelectionDAG? -static MVT::ValueType getPhysicalRegisterVT(SDNode *N, unsigned Reg, - const TargetInstrInfo *TII) { +static MVT getPhysicalRegisterVT(SDNode *N, unsigned Reg, + const TargetInstrInfo *TII) { const TargetInstrDesc &TID = TII->get(N->getTargetOpcode()); assert(TID.ImplicitDefs && "Physical reg def must be in implicit def list!"); unsigned NumRes = TID.getNumDefs(); @@ -1022,7 +1022,7 @@ SUnit *NewDef = CopyAndMoveSuccessors(LRDef); if (!NewDef) { // Issue expensive cross register class copies. - MVT::ValueType VT = getPhysicalRegisterVT(LRDef->Node, Reg, TII); + MVT VT = getPhysicalRegisterVT(LRDef->Node, Reg, TII); const TargetRegisterClass *RC = TRI->getPhysicalRegisterRegClass(Reg, VT); const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC); @@ -1599,7 +1599,7 @@ if (!SUImpDefs) return false; for (unsigned i = NumDefs, e = N->getNumValues(); i != e; ++i) { - MVT::ValueType VT = N->getValueType(i); + MVT VT = N->getValueType(i); if (VT == MVT::Flag || VT == MVT::Other) continue; unsigned Reg = ImpDefs[i - NumDefs]; Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Fri Jun 6 07:08:01 2008 @@ -40,13 +40,13 @@ /// makeVTList - Return an instance of the SDVTList struct initialized with the /// specified members. -static SDVTList makeVTList(const MVT::ValueType *VTs, unsigned NumVTs) { +static SDVTList makeVTList(const MVT *VTs, unsigned NumVTs) { SDVTList Res = {VTs, NumVTs}; return Res; } -static const fltSemantics *MVTToAPFloatSemantics(MVT::ValueType VT) { - switch (VT) { +static const fltSemantics *MVTToAPFloatSemantics(MVT VT) { + switch (VT.getSimpleVT()) { default: assert(0 && "Unknown FP format"); case MVT::f32: return &APFloat::IEEEsingle; case MVT::f64: return &APFloat::IEEEdouble; @@ -70,9 +70,9 @@ return Value.bitwiseIsEqual(V); } -bool ConstantFPSDNode::isValueValidForType(MVT::ValueType VT, +bool ConstantFPSDNode::isValueValidForType(MVT VT, const APFloat& Val) { - assert(MVT::isFloatingPoint(VT) && "Can only convert between FP types"); + assert(VT.isFloatingPoint() && "Can only convert between FP types"); // PPC long double cannot be converted to any other type. if (VT == MVT::ppcf128 || @@ -416,7 +416,7 @@ LoadSDNode *LD = cast(N); ID.AddInteger(LD->getAddressingMode()); ID.AddInteger(LD->getExtensionType()); - ID.AddInteger((unsigned int)(LD->getMemoryVT())); + ID.AddInteger(LD->getMemoryVT().V); ID.AddInteger(LD->getAlignment()); ID.AddInteger(LD->isVolatile()); break; @@ -425,7 +425,7 @@ StoreSDNode *ST = cast(N); ID.AddInteger(ST->getAddressingMode()); ID.AddInteger(ST->isTruncatingStore()); - ID.AddInteger((unsigned int)(ST->getMemoryVT())); + ID.AddInteger(ST->getMemoryVT().V); ID.AddInteger(ST->getAlignment()); ID.AddInteger(ST->isVolatile()); break; @@ -574,12 +574,12 @@ TargetExternalSymbols.erase(cast(N)->getSymbol()); break; case ISD::VALUETYPE: { - MVT::ValueType VT = cast(N)->getVT(); - if (MVT::isExtendedVT(VT)) { + MVT VT = cast(N)->getVT(); + if (VT.isExtended()) { Erased = ExtendedValueTypeNodes.erase(VT); } else { - Erased = ValueTypeNodes[VT] != 0; - ValueTypeNodes[VT] = 0; + Erased = ValueTypeNodes[VT.getSimpleVT()] != 0; + ValueTypeNodes[VT.getSimpleVT()] = 0; } break; } @@ -684,13 +684,13 @@ if (const LoadSDNode *LD = dyn_cast(N)) { ID.AddInteger(LD->getAddressingMode()); ID.AddInteger(LD->getExtensionType()); - ID.AddInteger((unsigned int)(LD->getMemoryVT())); + ID.AddInteger(LD->getMemoryVT().V); ID.AddInteger(LD->getAlignment()); ID.AddInteger(LD->isVolatile()); } else if (const StoreSDNode *ST = dyn_cast(N)) { ID.AddInteger(ST->getAddressingMode()); ID.AddInteger(ST->isTruncatingStore()); - ID.AddInteger((unsigned int)(ST->getMemoryVT())); + ID.AddInteger(ST->getMemoryVT().V); ID.AddInteger(ST->getAlignment()); ID.AddInteger(ST->isVolatile()); } @@ -712,10 +712,10 @@ } } -SDOperand SelectionDAG::getZeroExtendInReg(SDOperand Op, MVT::ValueType VT) { +SDOperand SelectionDAG::getZeroExtendInReg(SDOperand Op, MVT VT) { if (Op.getValueType() == VT) return Op; APInt Imm = APInt::getLowBitsSet(Op.getValueSizeInBits(), - MVT::getSizeInBits(VT)); + VT.getSizeInBits()); return getNode(ISD::AND, Op.getValueType(), Op, getConstant(Imm, Op.getValueType())); } @@ -729,20 +729,20 @@ return SDOperand(N, 0); } -SDOperand SelectionDAG::getConstant(uint64_t Val, MVT::ValueType VT, bool isT) { - MVT::ValueType EltVT = - MVT::isVector(VT) ? MVT::getVectorElementType(VT) : VT; +SDOperand SelectionDAG::getConstant(uint64_t Val, MVT VT, bool isT) { + MVT EltVT = + VT.isVector() ? VT.getVectorElementType() : VT; - return getConstant(APInt(MVT::getSizeInBits(EltVT), Val), VT, isT); + return getConstant(APInt(EltVT.getSizeInBits(), Val), VT, isT); } -SDOperand SelectionDAG::getConstant(const APInt &Val, MVT::ValueType VT, bool isT) { - assert(MVT::isInteger(VT) && "Cannot create FP integer constant!"); +SDOperand SelectionDAG::getConstant(const APInt &Val, MVT VT, bool isT) { + assert(VT.isInteger() && "Cannot create FP integer constant!"); - MVT::ValueType EltVT = - MVT::isVector(VT) ? MVT::getVectorElementType(VT) : VT; + MVT EltVT = + VT.isVector() ? VT.getVectorElementType() : VT; - assert(Val.getBitWidth() == MVT::getSizeInBits(EltVT) && + assert(Val.getBitWidth() == EltVT.getSizeInBits() && "APInt size does not match type size!"); unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant; @@ -752,7 +752,7 @@ void *IP = 0; SDNode *N = NULL; if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) - if (!MVT::isVector(VT)) + if (!VT.isVector()) return SDOperand(N, 0); if (!N) { N = new ConstantSDNode(isT, Val, EltVT); @@ -761,9 +761,9 @@ } SDOperand Result(N, 0); - if (MVT::isVector(VT)) { + if (VT.isVector()) { SmallVector Ops; - Ops.assign(MVT::getVectorNumElements(VT), Result); + Ops.assign(VT.getVectorNumElements(), Result); Result = getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); } return Result; @@ -774,12 +774,11 @@ } -SDOperand SelectionDAG::getConstantFP(const APFloat& V, MVT::ValueType VT, - bool isTarget) { - assert(MVT::isFloatingPoint(VT) && "Cannot create integer FP constant!"); +SDOperand SelectionDAG::getConstantFP(const APFloat& V, MVT VT, bool isTarget) { + assert(VT.isFloatingPoint() && "Cannot create integer FP constant!"); - MVT::ValueType EltVT = - MVT::isVector(VT) ? MVT::getVectorElementType(VT) : VT; + MVT EltVT = + VT.isVector() ? VT.getVectorElementType() : VT; // Do the map lookup using the actual bit pattern for the floating point // value, so that we don't have problems with 0.0 comparing equal to -0.0, and @@ -791,7 +790,7 @@ void *IP = 0; SDNode *N = NULL; if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) - if (!MVT::isVector(VT)) + if (!VT.isVector()) return SDOperand(N, 0); if (!N) { N = new ConstantFPSDNode(isTarget, V, EltVT); @@ -800,18 +799,17 @@ } SDOperand Result(N, 0); - if (MVT::isVector(VT)) { + if (VT.isVector()) { SmallVector Ops; - Ops.assign(MVT::getVectorNumElements(VT), Result); + Ops.assign(VT.getVectorNumElements(), Result); Result = getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); } return Result; } -SDOperand SelectionDAG::getConstantFP(double Val, MVT::ValueType VT, - bool isTarget) { - MVT::ValueType EltVT = - MVT::isVector(VT) ? MVT::getVectorElementType(VT) : VT; +SDOperand SelectionDAG::getConstantFP(double Val, MVT VT, bool isTarget) { + MVT EltVT = + VT.isVector() ? VT.getVectorElementType() : VT; if (EltVT==MVT::f32) return getConstantFP(APFloat((float)Val), VT, isTarget); else @@ -819,7 +817,7 @@ } SDOperand SelectionDAG::getGlobalAddress(const GlobalValue *GV, - MVT::ValueType VT, int Offset, + MVT VT, int Offset, bool isTargetGA) { unsigned Opc; @@ -848,8 +846,7 @@ return SDOperand(N, 0); } -SDOperand SelectionDAG::getFrameIndex(int FI, MVT::ValueType VT, - bool isTarget) { +SDOperand SelectionDAG::getFrameIndex(int FI, MVT VT, bool isTarget) { unsigned Opc = isTarget ? ISD::TargetFrameIndex : ISD::FrameIndex; FoldingSetNodeID ID; AddNodeIDNode(ID, Opc, getVTList(VT), (SDOperand*)0, 0); @@ -863,7 +860,7 @@ return SDOperand(N, 0); } -SDOperand SelectionDAG::getJumpTable(int JTI, MVT::ValueType VT, bool isTarget){ +SDOperand SelectionDAG::getJumpTable(int JTI, MVT VT, bool isTarget){ unsigned Opc = isTarget ? ISD::TargetJumpTable : ISD::JumpTable; FoldingSetNodeID ID; AddNodeIDNode(ID, Opc, getVTList(VT), (SDOperand*)0, 0); @@ -877,7 +874,7 @@ return SDOperand(N, 0); } -SDOperand SelectionDAG::getConstantPool(Constant *C, MVT::ValueType VT, +SDOperand SelectionDAG::getConstantPool(Constant *C, MVT VT, unsigned Alignment, int Offset, bool isTarget) { unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; @@ -896,8 +893,7 @@ } -SDOperand SelectionDAG::getConstantPool(MachineConstantPoolValue *C, - MVT::ValueType VT, +SDOperand SelectionDAG::getConstantPool(MachineConstantPoolValue *C, MVT VT, unsigned Alignment, int Offset, bool isTarget) { unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; @@ -942,12 +938,12 @@ return SDOperand(N, 0); } -SDOperand SelectionDAG::getValueType(MVT::ValueType VT) { - if (!MVT::isExtendedVT(VT) && (unsigned)VT >= ValueTypeNodes.size()) - ValueTypeNodes.resize(VT+1); +SDOperand SelectionDAG::getValueType(MVT VT) { + if (VT.isSimple() && (unsigned)VT.getSimpleVT() >= ValueTypeNodes.size()) + ValueTypeNodes.resize(VT.getSimpleVT()+1); - SDNode *&N = MVT::isExtendedVT(VT) ? - ExtendedValueTypeNodes[VT] : ValueTypeNodes[VT]; + SDNode *&N = VT.isExtended() ? + ExtendedValueTypeNodes[VT] : ValueTypeNodes[VT.getSimpleVT()]; if (N) return SDOperand(N, 0); N = new VTSDNode(VT); @@ -955,7 +951,7 @@ return SDOperand(N, 0); } -SDOperand SelectionDAG::getExternalSymbol(const char *Sym, MVT::ValueType VT) { +SDOperand SelectionDAG::getExternalSymbol(const char *Sym, MVT VT) { SDNode *&N = ExternalSymbols[Sym]; if (N) return SDOperand(N, 0); N = new ExternalSymbolSDNode(false, Sym, VT); @@ -963,8 +959,7 @@ return SDOperand(N, 0); } -SDOperand SelectionDAG::getTargetExternalSymbol(const char *Sym, - MVT::ValueType VT) { +SDOperand SelectionDAG::getTargetExternalSymbol(const char *Sym, MVT VT) { SDNode *&N = TargetExternalSymbols[Sym]; if (N) return SDOperand(N, 0); N = new ExternalSymbolSDNode(true, Sym, VT); @@ -975,7 +970,7 @@ SDOperand SelectionDAG::getCondCode(ISD::CondCode Cond) { if ((unsigned)Cond >= CondCodeNodes.size()) CondCodeNodes.resize(Cond+1); - + if (CondCodeNodes[Cond] == 0) { CondCodeNodes[Cond] = new CondCodeSDNode(Cond); AllNodes.push_back(CondCodeNodes[Cond]); @@ -983,7 +978,7 @@ return SDOperand(CondCodeNodes[Cond], 0); } -SDOperand SelectionDAG::getRegister(unsigned RegNo, MVT::ValueType VT) { +SDOperand SelectionDAG::getRegister(unsigned RegNo, MVT VT) { FoldingSetNodeID ID; AddNodeIDNode(ID, ISD::Register, getVTList(VT), (SDOperand*)0, 0); ID.AddInteger(RegNo); @@ -1039,17 +1034,17 @@ /// CreateStackTemporary - Create a stack temporary, suitable for holding the /// specified value type. -SDOperand SelectionDAG::CreateStackTemporary(MVT::ValueType VT) { +SDOperand SelectionDAG::CreateStackTemporary(MVT VT) { MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo(); - unsigned ByteSize = MVT::getSizeInBits(VT)/8; - const Type *Ty = MVT::getTypeForValueType(VT); + unsigned ByteSize = VT.getSizeInBits()/8; + const Type *Ty = VT.getTypeForMVT(); unsigned StackAlign = (unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty); int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign); return getFrameIndex(FrameIdx, TLI.getPointerTy()); } -SDOperand SelectionDAG::FoldSetCC(MVT::ValueType VT, SDOperand N1, +SDOperand SelectionDAG::FoldSetCC(MVT VT, SDOperand N1, SDOperand N2, ISD::CondCode Cond) { // These setcc operations always fold. switch (Cond) { @@ -1069,7 +1064,7 @@ case ISD::SETUO: case ISD::SETUEQ: case ISD::SETUNE: - assert(!MVT::isInteger(N1.getValueType()) && "Illegal setcc for integer!"); + assert(!N1.getValueType().isInteger() && "Illegal setcc for integer!"); break; } @@ -1177,7 +1172,7 @@ APInt &KnownZero, APInt &KnownOne, unsigned Depth) const { unsigned BitWidth = Mask.getBitWidth(); - assert(BitWidth == MVT::getSizeInBits(Op.getValueType()) && + assert(BitWidth == Op.getValueType().getSizeInBits() && "Mask size mismatches value type size!"); KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything. @@ -1372,8 +1367,8 @@ } return; case ISD::SIGN_EXTEND_INREG: { - MVT::ValueType EVT = cast(Op.getOperand(1))->getVT(); - unsigned EBits = MVT::getSizeInBits(EVT); + MVT EVT = cast(Op.getOperand(1))->getVT(); + unsigned EBits = EVT.getSizeInBits(); // Sign extension. Compute the demanded bits in the result that are not // present in the input. @@ -1417,15 +1412,15 @@ case ISD::LOAD: { if (ISD::isZEXTLoad(Op.Val)) { LoadSDNode *LD = cast(Op); - MVT::ValueType VT = LD->getMemoryVT(); - unsigned MemBits = MVT::getSizeInBits(VT); + MVT VT = LD->getMemoryVT(); + unsigned MemBits = VT.getSizeInBits(); KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits) & Mask; } return; } case ISD::ZERO_EXTEND: { - MVT::ValueType InVT = Op.getOperand(0).getValueType(); - unsigned InBits = MVT::getSizeInBits(InVT); + MVT InVT = Op.getOperand(0).getValueType(); + unsigned InBits = InVT.getSizeInBits(); APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; APInt InMask = Mask; InMask.trunc(InBits); @@ -1438,8 +1433,8 @@ return; } case ISD::SIGN_EXTEND: { - MVT::ValueType InVT = Op.getOperand(0).getValueType(); - unsigned InBits = MVT::getSizeInBits(InVT); + MVT InVT = Op.getOperand(0).getValueType(); + unsigned InBits = InVT.getSizeInBits(); APInt InSignBit = APInt::getSignBit(InBits); APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; APInt InMask = Mask; @@ -1479,8 +1474,8 @@ return; } case ISD::ANY_EXTEND: { - MVT::ValueType InVT = Op.getOperand(0).getValueType(); - unsigned InBits = MVT::getSizeInBits(InVT); + MVT InVT = Op.getOperand(0).getValueType(); + unsigned InBits = InVT.getSizeInBits(); APInt InMask = Mask; InMask.trunc(InBits); KnownZero.trunc(InBits); @@ -1491,8 +1486,8 @@ return; } case ISD::TRUNCATE: { - MVT::ValueType InVT = Op.getOperand(0).getValueType(); - unsigned InBits = MVT::getSizeInBits(InVT); + MVT InVT = Op.getOperand(0).getValueType(); + unsigned InBits = InVT.getSizeInBits(); APInt InMask = Mask; InMask.zext(InBits); KnownZero.zext(InBits); @@ -1504,8 +1499,8 @@ break; } case ISD::AssertZext: { - MVT::ValueType VT = cast(Op.getOperand(1))->getVT(); - APInt InMask = APInt::getLowBitsSet(BitWidth, MVT::getSizeInBits(VT)); + MVT VT = cast(Op.getOperand(1))->getVT(); + APInt InMask = APInt::getLowBitsSet(BitWidth, VT.getSizeInBits()); ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero, KnownOne, Depth+1); KnownZero |= (~InMask) & Mask; @@ -1624,9 +1619,9 @@ /// information. For example, immediately after an "SRA X, 2", we know that /// the top 3 bits are all equal to each other, so we return 3. unsigned SelectionDAG::ComputeNumSignBits(SDOperand Op, unsigned Depth) const{ - MVT::ValueType VT = Op.getValueType(); - assert(MVT::isInteger(VT) && "Invalid VT!"); - unsigned VTBits = MVT::getSizeInBits(VT); + MVT VT = Op.getValueType(); + assert(VT.isInteger() && "Invalid VT!"); + unsigned VTBits = VT.getSizeInBits(); unsigned Tmp, Tmp2; unsigned FirstAnswer = 1; @@ -1636,10 +1631,10 @@ switch (Op.getOpcode()) { default: break; case ISD::AssertSext: - Tmp = MVT::getSizeInBits(cast(Op.getOperand(1))->getVT()); + Tmp = cast(Op.getOperand(1))->getVT().getSizeInBits(); return VTBits-Tmp+1; case ISD::AssertZext: - Tmp = MVT::getSizeInBits(cast(Op.getOperand(1))->getVT()); + Tmp = cast(Op.getOperand(1))->getVT().getSizeInBits(); return VTBits-Tmp; case ISD::Constant: { @@ -1653,12 +1648,12 @@ } case ISD::SIGN_EXTEND: - Tmp = VTBits-MVT::getSizeInBits(Op.getOperand(0).getValueType()); + Tmp = VTBits-Op.getOperand(0).getValueType().getSizeInBits(); return ComputeNumSignBits(Op.getOperand(0), Depth+1) + Tmp; case ISD::SIGN_EXTEND_INREG: // Max of the input and what this extends. - Tmp = MVT::getSizeInBits(cast(Op.getOperand(1))->getVT()); + Tmp = cast(Op.getOperand(1))->getVT().getSizeInBits(); Tmp = VTBits-Tmp+1; Tmp2 = ComputeNumSignBits(Op.getOperand(0), Depth+1); @@ -1793,10 +1788,10 @@ switch (ExtType) { default: break; case ISD::SEXTLOAD: // '17' bits known - Tmp = MVT::getSizeInBits(LD->getMemoryVT()); + Tmp = LD->getMemoryVT().getSizeInBits(); return VTBits-Tmp+1; case ISD::ZEXTLOAD: // '16' bits known - Tmp = MVT::getSizeInBits(LD->getMemoryVT()); + Tmp = LD->getMemoryVT().getSizeInBits(); return VTBits-Tmp; } } @@ -1848,7 +1843,7 @@ /// getShuffleScalarElt - Returns the scalar element that will make up the ith /// element of the result of the vector shuffle. SDOperand SelectionDAG::getShuffleScalarElt(const SDNode *N, unsigned Idx) { - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); SDOperand PermMask = N->getOperand(2); unsigned NumElems = PermMask.getNumOperands(); SDOperand V = (Idx < NumElems) ? N->getOperand(0) : N->getOperand(1); @@ -1856,18 +1851,18 @@ if (V.getOpcode() == ISD::BIT_CONVERT) { V = V.getOperand(0); - if (MVT::getVectorNumElements(V.getValueType()) != NumElems) + if (V.getValueType().getVectorNumElements() != NumElems) return SDOperand(); } if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) return (Idx == 0) ? V.getOperand(0) - : getNode(ISD::UNDEF, MVT::getVectorElementType(VT)); + : getNode(ISD::UNDEF, VT.getVectorElementType()); if (V.getOpcode() == ISD::BUILD_VECTOR) return V.getOperand(Idx); if (V.getOpcode() == ISD::VECTOR_SHUFFLE) { SDOperand Elt = PermMask.getOperand(Idx); if (Elt.getOpcode() == ISD::UNDEF) - return getNode(ISD::UNDEF, MVT::getVectorElementType(VT)); + return getNode(ISD::UNDEF, VT.getVectorElementType()); return getShuffleScalarElt(V.Val,cast(Elt)->getValue()); } return SDOperand(); @@ -1876,7 +1871,7 @@ /// getNode - Gets or creates the specified node. /// -SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT) { +SDOperand SelectionDAG::getNode(unsigned Opcode, MVT VT) { FoldingSetNodeID ID; AddNodeIDNode(ID, Opcode, getVTList(VT), (SDOperand*)0, 0); void *IP = 0; @@ -1889,12 +1884,11 @@ return SDOperand(N, 0); } -SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, - SDOperand Operand) { +SDOperand SelectionDAG::getNode(unsigned Opcode, MVT VT, SDOperand Operand) { // Constant fold unary operations with an integer constant operand. if (ConstantSDNode *C = dyn_cast(Operand.Val)) { const APInt &Val = C->getAPIntValue(); - unsigned BitWidth = MVT::getSizeInBits(VT); + unsigned BitWidth = VT.getSizeInBits(); switch (Opcode) { default: break; case ISD::SIGN_EXTEND: @@ -1979,56 +1973,56 @@ return Operand; // Factor or merge of one node? No need. case ISD::FP_ROUND: assert(0 && "Invalid method to make FP_ROUND node"); case ISD::FP_EXTEND: - assert(MVT::isFloatingPoint(VT) && - MVT::isFloatingPoint(Operand.getValueType()) && "Invalid FP cast!"); + assert(VT.isFloatingPoint() && + Operand.getValueType().isFloatingPoint() && "Invalid FP cast!"); if (Operand.getValueType() == VT) return Operand; // noop conversion. if (Operand.getOpcode() == ISD::UNDEF) return getNode(ISD::UNDEF, VT); break; case ISD::SIGN_EXTEND: - assert(MVT::isInteger(VT) && MVT::isInteger(Operand.getValueType()) && + assert(VT.isInteger() && Operand.getValueType().isInteger() && "Invalid SIGN_EXTEND!"); if (Operand.getValueType() == VT) return Operand; // noop extension - assert(MVT::getSizeInBits(Operand.getValueType()) < MVT::getSizeInBits(VT) + assert(Operand.getValueType().getSizeInBits() < VT.getSizeInBits() && "Invalid sext node, dst < src!"); if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) return getNode(OpOpcode, VT, Operand.Val->getOperand(0)); break; case ISD::ZERO_EXTEND: - assert(MVT::isInteger(VT) && MVT::isInteger(Operand.getValueType()) && + assert(VT.isInteger() && Operand.getValueType().isInteger() && "Invalid ZERO_EXTEND!"); if (Operand.getValueType() == VT) return Operand; // noop extension - assert(MVT::getSizeInBits(Operand.getValueType()) < MVT::getSizeInBits(VT) + assert(Operand.getValueType().getSizeInBits() < VT.getSizeInBits() && "Invalid zext node, dst < src!"); if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x) return getNode(ISD::ZERO_EXTEND, VT, Operand.Val->getOperand(0)); break; case ISD::ANY_EXTEND: - assert(MVT::isInteger(VT) && MVT::isInteger(Operand.getValueType()) && + assert(VT.isInteger() && Operand.getValueType().isInteger() && "Invalid ANY_EXTEND!"); if (Operand.getValueType() == VT) return Operand; // noop extension - assert(MVT::getSizeInBits(Operand.getValueType()) < MVT::getSizeInBits(VT) + assert(Operand.getValueType().getSizeInBits() < VT.getSizeInBits() && "Invalid anyext node, dst < src!"); if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND) // (ext (zext x)) -> (zext x) and (ext (sext x)) -> (sext x) return getNode(OpOpcode, VT, Operand.Val->getOperand(0)); break; case ISD::TRUNCATE: - assert(MVT::isInteger(VT) && MVT::isInteger(Operand.getValueType()) && + assert(VT.isInteger() && Operand.getValueType().isInteger() && "Invalid TRUNCATE!"); if (Operand.getValueType() == VT) return Operand; // noop truncate - assert(MVT::getSizeInBits(Operand.getValueType()) > MVT::getSizeInBits(VT) + assert(Operand.getValueType().getSizeInBits() > VT.getSizeInBits() && "Invalid truncate node, src < dst!"); if (OpOpcode == ISD::TRUNCATE) return getNode(ISD::TRUNCATE, VT, Operand.Val->getOperand(0)); else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ANY_EXTEND) { // If the source is smaller than the dest, we still need an extend. - if (MVT::getSizeInBits(Operand.Val->getOperand(0).getValueType()) - < MVT::getSizeInBits(VT)) + if (Operand.Val->getOperand(0).getValueType().getSizeInBits() + < VT.getSizeInBits()) return getNode(OpOpcode, VT, Operand.Val->getOperand(0)); - else if (MVT::getSizeInBits(Operand.Val->getOperand(0).getValueType()) - > MVT::getSizeInBits(VT)) + else if (Operand.Val->getOperand(0).getValueType().getSizeInBits() + > VT.getSizeInBits()) return getNode(ISD::TRUNCATE, VT, Operand.Val->getOperand(0)); else return Operand.Val->getOperand(0); @@ -2036,7 +2030,7 @@ break; case ISD::BIT_CONVERT: // Basic sanity checking. - assert(MVT::getSizeInBits(VT) == MVT::getSizeInBits(Operand.getValueType()) + assert(VT.getSizeInBits() == Operand.getValueType().getSizeInBits() && "Cannot BIT_CONVERT between types of different sizes!"); if (VT == Operand.getValueType()) return Operand; // noop conversion. if (OpOpcode == ISD::BIT_CONVERT) // bitconv(bitconv(x)) -> bitconv(x) @@ -2045,8 +2039,8 @@ return getNode(ISD::UNDEF, VT); break; case ISD::SCALAR_TO_VECTOR: - assert(MVT::isVector(VT) && !MVT::isVector(Operand.getValueType()) && - MVT::getVectorElementType(VT) == Operand.getValueType() && + assert(VT.isVector() && !Operand.getValueType().isVector() && + VT.getVectorElementType() == Operand.getValueType() && "Illegal SCALAR_TO_VECTOR node!"); if (OpOpcode == ISD::UNDEF) return getNode(ISD::UNDEF, VT); @@ -2090,7 +2084,7 @@ -SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, +SDOperand SelectionDAG::getNode(unsigned Opcode, MVT VT, SDOperand N1, SDOperand N2) { ConstantSDNode *N1C = dyn_cast(N1.Val); ConstantSDNode *N2C = dyn_cast(N2.Val); @@ -2104,7 +2098,7 @@ if (N2.getOpcode() == ISD::EntryToken) return N1; break; case ISD::AND: - assert(MVT::isInteger(VT) && N1.getValueType() == N2.getValueType() && + assert(VT.isInteger() && N1.getValueType() == N2.getValueType() && N1.getValueType() == VT && "Binary operator types must match!"); // (X & 0) -> 0. This commonly occurs when legalizing i64 values, so it's // worth handling here. @@ -2117,7 +2111,7 @@ case ISD::XOR: case ISD::ADD: case ISD::SUB: - assert(MVT::isInteger(VT) && N1.getValueType() == N2.getValueType() && + assert(VT.isInteger() && N1.getValueType() == N2.getValueType() && N1.getValueType() == VT && "Binary operator types must match!"); // (X ^|+- 0) -> X. This commonly occurs when legalizing i64 values, so // it's worth handling here. @@ -2128,7 +2122,7 @@ case ISD::UREM: case ISD::MULHU: case ISD::MULHS: - assert(MVT::isInteger(VT) && "This operator does not apply to FP types!"); + assert(VT.isInteger() && "This operator does not apply to FP types!"); // fall through case ISD::MUL: case ISD::SDIV: @@ -2143,8 +2137,8 @@ break; case ISD::FCOPYSIGN: // N1 and result must match. N1/N2 need not match. assert(N1.getValueType() == VT && - MVT::isFloatingPoint(N1.getValueType()) && - MVT::isFloatingPoint(N2.getValueType()) && + N1.getValueType().isFloatingPoint() && + N2.getValueType().isFloatingPoint() && "Invalid FCOPYSIGN!"); break; case ISD::SHL: @@ -2154,49 +2148,49 @@ case ISD::ROTR: assert(VT == N1.getValueType() && "Shift operators return type must be the same as their first arg"); - assert(MVT::isInteger(VT) && MVT::isInteger(N2.getValueType()) && + assert(VT.isInteger() && N2.getValueType().isInteger() && VT != MVT::i1 && "Shifts only work on integers"); break; case ISD::FP_ROUND_INREG: { - MVT::ValueType EVT = cast(N2)->getVT(); + MVT EVT = cast(N2)->getVT(); assert(VT == N1.getValueType() && "Not an inreg round!"); - assert(MVT::isFloatingPoint(VT) && MVT::isFloatingPoint(EVT) && + assert(VT.isFloatingPoint() && EVT.isFloatingPoint() && "Cannot FP_ROUND_INREG integer types"); - assert(MVT::getSizeInBits(EVT) <= MVT::getSizeInBits(VT) && + assert(EVT.getSizeInBits() <= VT.getSizeInBits() && "Not rounding down!"); if (cast(N2)->getVT() == VT) return N1; // Not actually rounding. break; } case ISD::FP_ROUND: - assert(MVT::isFloatingPoint(VT) && - MVT::isFloatingPoint(N1.getValueType()) && - MVT::getSizeInBits(VT) <= MVT::getSizeInBits(N1.getValueType()) && + assert(VT.isFloatingPoint() && + N1.getValueType().isFloatingPoint() && + VT.getSizeInBits() <= N1.getValueType().getSizeInBits() && isa(N2) && "Invalid FP_ROUND!"); if (N1.getValueType() == VT) return N1; // noop conversion. break; case ISD::AssertSext: case ISD::AssertZext: { - MVT::ValueType EVT = cast(N2)->getVT(); + MVT EVT = cast(N2)->getVT(); assert(VT == N1.getValueType() && "Not an inreg extend!"); - assert(MVT::isInteger(VT) && MVT::isInteger(EVT) && + assert(VT.isInteger() && EVT.isInteger() && "Cannot *_EXTEND_INREG FP types"); - assert(MVT::getSizeInBits(EVT) <= MVT::getSizeInBits(VT) && + assert(EVT.getSizeInBits() <= VT.getSizeInBits() && "Not extending!"); if (VT == EVT) return N1; // noop assertion. break; } case ISD::SIGN_EXTEND_INREG: { - MVT::ValueType EVT = cast(N2)->getVT(); + MVT EVT = cast(N2)->getVT(); assert(VT == N1.getValueType() && "Not an inreg extend!"); - assert(MVT::isInteger(VT) && MVT::isInteger(EVT) && + assert(VT.isInteger() && EVT.isInteger() && "Cannot *_EXTEND_INREG FP types"); - assert(MVT::getSizeInBits(EVT) <= MVT::getSizeInBits(VT) && + assert(EVT.getSizeInBits() <= VT.getSizeInBits() && "Not extending!"); if (EVT == VT) return N1; // Not actually extending if (N1C) { APInt Val = N1C->getAPIntValue(); - unsigned FromBits = MVT::getSizeInBits(cast(N2)->getVT()); + unsigned FromBits = cast(N2)->getVT().getSizeInBits(); Val <<= Val.getBitWidth()-FromBits; Val = Val.ashr(Val.getBitWidth()-FromBits); return getConstant(Val, VT); @@ -2215,7 +2209,7 @@ if (N1.getOpcode() == ISD::CONCAT_VECTORS && N1.getNumOperands() > 0) { unsigned Factor = - MVT::getVectorNumElements(N1.getOperand(0).getValueType()); + N1.getOperand(0).getValueType().getVectorNumElements(); return getNode(ISD::EXTRACT_VECTOR_ELT, VT, N1.getOperand(N2C->getValue() / Factor), getConstant(N2C->getValue() % Factor, N2.getValueType())); @@ -2238,9 +2232,9 @@ break; case ISD::EXTRACT_ELEMENT: assert(N2C && (unsigned)N2C->getValue() < 2 && "Bad EXTRACT_ELEMENT!"); - assert(!MVT::isVector(N1.getValueType()) && - MVT::isInteger(N1.getValueType()) && - !MVT::isVector(VT) && MVT::isInteger(VT) && + assert(!N1.getValueType().isVector() && + N1.getValueType().isInteger() && + !VT.isVector() && VT.isInteger() && "EXTRACT_ELEMENT only applies to integers!"); // EXTRACT_ELEMENT of BUILD_PAIR is often formed while legalize is expanding @@ -2251,7 +2245,7 @@ // EXTRACT_ELEMENT of a constant int is also very common. if (ConstantSDNode *C = dyn_cast(N1)) { - unsigned ElementSize = MVT::getSizeInBits(VT); + unsigned ElementSize = VT.getSizeInBits(); unsigned Shift = ElementSize * N2C->getValue(); APInt ShiftedVal = C->getAPIntValue().lshr(Shift); return getConstant(ShiftedVal.trunc(ElementSize), VT); @@ -2365,7 +2359,7 @@ case ISD::SREM: case ISD::SRL: case ISD::SHL: - if (!MVT::isVector(VT)) + if (!VT.isVector()) return getConstant(0, VT); // fold op(undef, arg2) -> 0 // For vectors, we can't easily build an all zero vector, just return // the LHS. @@ -2401,14 +2395,14 @@ case ISD::AND: case ISD::SRL: case ISD::SHL: - if (!MVT::isVector(VT)) + if (!VT.isVector()) return getConstant(0, VT); // fold op(arg1, undef) -> 0 // For vectors, we can't easily build an all zero vector, just return // the LHS. return N1; case ISD::OR: - if (!MVT::isVector(VT)) - return getConstant(MVT::getIntVTBitMask(VT), VT); + if (!VT.isVector()) + return getConstant(VT.getIntegerVTBitMask(), VT); // For vectors, we can't easily build an all one vector, just return // the LHS. return N1; @@ -2437,7 +2431,7 @@ return SDOperand(N, 0); } -SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, +SDOperand SelectionDAG::getNode(unsigned Opcode, MVT VT, SDOperand N1, SDOperand N2, SDOperand N3) { // Perform various simplifications. ConstantSDNode *N1C = dyn_cast(N1.Val); @@ -2469,9 +2463,9 @@ break; case ISD::VECTOR_SHUFFLE: assert(VT == N1.getValueType() && VT == N2.getValueType() && - MVT::isVector(VT) && MVT::isVector(N3.getValueType()) && + VT.isVector() && N3.getValueType().isVector() && N3.getOpcode() == ISD::BUILD_VECTOR && - MVT::getVectorNumElements(VT) == N3.getNumOperands() && + VT.getVectorNumElements() == N3.getNumOperands() && "Illegal VECTOR_SHUFFLE node!"); break; case ISD::BIT_CONVERT: @@ -2500,14 +2494,14 @@ return SDOperand(N, 0); } -SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, +SDOperand SelectionDAG::getNode(unsigned Opcode, MVT VT, SDOperand N1, SDOperand N2, SDOperand N3, SDOperand N4) { SDOperand Ops[] = { N1, N2, N3, N4 }; return getNode(Opcode, VT, Ops, 4); } -SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, +SDOperand SelectionDAG::getNode(unsigned Opcode, MVT VT, SDOperand N1, SDOperand N2, SDOperand N3, SDOperand N4, SDOperand N5) { SDOperand Ops[] = { N1, N2, N3, N4, N5 }; @@ -2516,10 +2510,9 @@ /// getMemsetValue - Vectorized representation of the memset value /// operand. -static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT, - SelectionDAG &DAG) { - unsigned NumBits = MVT::isVector(VT) ? - MVT::getSizeInBits(MVT::getVectorElementType(VT)) : MVT::getSizeInBits(VT); +static SDOperand getMemsetValue(SDOperand Value, MVT VT, SelectionDAG &DAG) { + unsigned NumBits = VT.isVector() ? + VT.getVectorElementType().getSizeInBits() : VT.getSizeInBits(); if (ConstantSDNode *C = dyn_cast(Value)) { APInt Val = APInt(NumBits, C->getValue() & 255); unsigned Shift = 8; @@ -2527,7 +2520,7 @@ Val = (Val << Shift) | Val; Shift <<= 1; } - if (MVT::isInteger(VT)) + if (VT.isInteger()) return DAG.getConstant(Val, VT); return DAG.getConstantFP(APFloat(Val), VT); } @@ -2547,11 +2540,11 @@ /// getMemsetStringVal - Similar to getMemsetValue. Except this is only /// used when a memcpy is turned into a memset when the source is a constant /// string ptr. -static SDOperand getMemsetStringVal(MVT::ValueType VT, SelectionDAG &DAG, +static SDOperand getMemsetStringVal(MVT VT, SelectionDAG &DAG, const TargetLowering &TLI, std::string &Str, unsigned Offset) { - assert(!MVT::isVector(VT) && "Can't handle vector type here!"); - unsigned NumBits = MVT::getSizeInBits(VT); + assert(!VT.isVector() && "Can't handle vector type here!"); + unsigned NumBits = VT.getSizeInBits(); unsigned MSB = NumBits / 8; uint64_t Val = 0; if (TLI.isLittleEndian()) @@ -2567,7 +2560,7 @@ /// static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset, SelectionDAG &DAG) { - MVT::ValueType VT = Base.getValueType(); + MVT VT = Base.getValueType(); return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT)); } @@ -2604,7 +2597,7 @@ /// to replace the memset / memcpy is below the threshold. It also returns the /// types of the sequence of memory ops to perform memset / memcpy. static -bool MeetsMaxMemopRequirement(std::vector &MemOps, +bool MeetsMaxMemopRequirement(std::vector &MemOps, SDOperand Dst, SDOperand Src, unsigned Limit, uint64_t Size, unsigned &Align, SelectionDAG &DAG, @@ -2615,10 +2608,10 @@ uint64_t SrcOff = 0; bool isSrcStr = isMemSrcFromString(Src, Str, SrcOff); bool isSrcConst = isa(Src); - MVT::ValueType VT= TLI.getOptimalMemOpType(Size, Align, isSrcConst, isSrcStr); + MVT VT= TLI.getOptimalMemOpType(Size, Align, isSrcConst, isSrcStr); if (VT != MVT::iAny) { unsigned NewAlign = (unsigned) - TLI.getTargetData()->getABITypeAlignment(MVT::getTypeForValueType(VT)); + TLI.getTargetData()->getABITypeAlignment(VT.getTypeForMVT()); // If source is a string constant, this will require an unaligned load. if (NewAlign > Align && (isSrcConst || AllowUnalign)) { if (Dst.getOpcode() != ISD::FrameIndex) { @@ -2654,10 +2647,10 @@ } } - MVT::ValueType LVT = MVT::i64; + MVT LVT = MVT::i64; while (!TLI.isTypeLegal(LVT)) - LVT = (MVT::ValueType)((unsigned)LVT - 1); - assert(MVT::isInteger(LVT)); + LVT = (MVT::SimpleValueType)(LVT.getSimpleVT() - 1); + assert(LVT.isInteger()); if (VT > LVT) VT = LVT; @@ -2665,16 +2658,16 @@ unsigned NumMemOps = 0; while (Size != 0) { - unsigned VTSize = MVT::getSizeInBits(VT) / 8; + unsigned VTSize = VT.getSizeInBits() / 8; while (VTSize > Size) { // For now, only use non-vector load / store's for the left-over pieces. - if (MVT::isVector(VT)) { + if (VT.isVector()) { VT = MVT::i64; while (!TLI.isTypeLegal(VT)) - VT = (MVT::ValueType)((unsigned)VT - 1); - VTSize = MVT::getSizeInBits(VT) / 8; + VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); + VTSize = VT.getSizeInBits() / 8; } else { - VT = (MVT::ValueType)((unsigned)VT - 1); + VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); VTSize >>= 1; } } @@ -2698,7 +2691,7 @@ // Expand memcpy to a series of load and store ops if the size operand falls // below a certain threshold. - std::vector MemOps; + std::vector MemOps; uint64_t Limit = -1; if (!AlwaysInline) Limit = TLI.getMaxStoresPerMemcpy(); @@ -2714,11 +2707,11 @@ SmallVector OutChains; unsigned NumMemOps = MemOps.size(); for (unsigned i = 0; i < NumMemOps; i++) { - MVT::ValueType VT = MemOps[i]; - unsigned VTSize = MVT::getSizeInBits(VT) / 8; + MVT VT = MemOps[i]; + unsigned VTSize = VT.getSizeInBits() / 8; SDOperand Value, Store; - if (CopyFromStr && !MVT::isVector(VT)) { + if (CopyFromStr && !VT.isVector()) { // It's unlikely a store of a vector immediate can be done in a single // instruction. It would require a load from a constantpool first. // FIXME: Handle cases where store of vector immediate is done in a @@ -2754,7 +2747,7 @@ // Expand memmove to a series of load and store ops if the size operand falls // below a certain threshold. - std::vector MemOps; + std::vector MemOps; uint64_t Limit = -1; if (!AlwaysInline) Limit = TLI.getMaxStoresPerMemmove(); @@ -2770,8 +2763,8 @@ SmallVector OutChains; unsigned NumMemOps = MemOps.size(); for (unsigned i = 0; i < NumMemOps; i++) { - MVT::ValueType VT = MemOps[i]; - unsigned VTSize = MVT::getSizeInBits(VT) / 8; + MVT VT = MemOps[i]; + unsigned VTSize = VT.getSizeInBits() / 8; SDOperand Value, Store; Value = DAG.getLoad(VT, Chain, @@ -2785,8 +2778,8 @@ &LoadChains[0], LoadChains.size()); OutChains.clear(); for (unsigned i = 0; i < NumMemOps; i++) { - MVT::ValueType VT = MemOps[i]; - unsigned VTSize = MVT::getSizeInBits(VT) / 8; + MVT VT = MemOps[i]; + unsigned VTSize = VT.getSizeInBits() / 8; SDOperand Value, Store; Store = DAG.getStore(Chain, LoadValues[i], @@ -2809,7 +2802,7 @@ // Expand memset to a series of load/store ops if the size operand // falls below a certain threshold. - std::vector MemOps; + std::vector MemOps; if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, TLI.getMaxStoresPerMemset(), Size, Align, DAG, TLI)) return SDOperand(); @@ -2819,8 +2812,8 @@ unsigned NumMemOps = MemOps.size(); for (unsigned i = 0; i < NumMemOps; i++) { - MVT::ValueType VT = MemOps[i]; - unsigned VTSize = MVT::getSizeInBits(VT) / 8; + MVT VT = MemOps[i]; + unsigned VTSize = VT.getSizeInBits() / 8; SDOperand Value = getMemsetValue(Src, VT, DAG); SDOperand Store = DAG.getStore(Chain, Value, getMemBasePlusOffset(Dst, DstOff, DAG), @@ -2984,14 +2977,14 @@ SDOperand SelectionDAG::getAtomic(unsigned Opcode, SDOperand Chain, SDOperand Ptr, SDOperand Cmp, - SDOperand Swp, MVT::ValueType VT) { + SDOperand Swp, MVT VT) { assert(Opcode == ISD::ATOMIC_LCS && "Invalid Atomic Op"); assert(Cmp.getValueType() == Swp.getValueType() && "Invalid Atomic Op Types"); SDVTList VTs = getVTList(Cmp.getValueType(), MVT::Other); FoldingSetNodeID ID; SDOperand Ops[] = {Chain, Ptr, Cmp, Swp}; AddNodeIDNode(ID, Opcode, VTs, Ops, 4); - ID.AddInteger((unsigned int)VT); + ID.AddInteger(VT.V); void* IP = 0; if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) return SDOperand(E, 0); @@ -3003,7 +2996,7 @@ SDOperand SelectionDAG::getAtomic(unsigned Opcode, SDOperand Chain, SDOperand Ptr, SDOperand Val, - MVT::ValueType VT) { + MVT VT) { assert(( Opcode == ISD::ATOMIC_LAS || Opcode == ISD::ATOMIC_LSS || Opcode == ISD::ATOMIC_SWAP || Opcode == ISD::ATOMIC_LOAD_AND || Opcode == ISD::ATOMIC_LOAD_OR || Opcode == ISD::ATOMIC_LOAD_XOR @@ -3014,7 +3007,7 @@ FoldingSetNodeID ID; SDOperand Ops[] = {Chain, Ptr, Val}; AddNodeIDNode(ID, Opcode, VTs, Ops, 3); - ID.AddInteger((unsigned int)VT); + ID.AddInteger(VT.V); void* IP = 0; if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) return SDOperand(E, 0); @@ -3026,14 +3019,14 @@ SDOperand SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, - MVT::ValueType VT, SDOperand Chain, + MVT VT, SDOperand Chain, SDOperand Ptr, SDOperand Offset, - const Value *SV, int SVOffset, MVT::ValueType EVT, + const Value *SV, int SVOffset, MVT EVT, bool isVolatile, unsigned Alignment) { if (Alignment == 0) { // Ensure that codegen never sees alignment 0 const Type *Ty = 0; if (VT != MVT::iPTR) { - Ty = MVT::getTypeForValueType(VT); + Ty = VT.getTypeForMVT(); } else if (SV) { const PointerType *PT = dyn_cast(SV->getType()); assert(PT && "Value for load must be a pointer"); @@ -3049,14 +3042,14 @@ assert(VT == EVT && "Non-extending load from different memory type!"); } else { // Extending load. - if (MVT::isVector(VT)) - assert(EVT == MVT::getVectorElementType(VT) && "Invalid vector extload!"); + if (VT.isVector()) + assert(EVT == VT.getVectorElementType() && "Invalid vector extload!"); else - assert(MVT::getSizeInBits(EVT) < MVT::getSizeInBits(VT) && + assert(EVT.getSizeInBits() < VT.getSizeInBits() && "Should only be an extending load, not truncating!"); - assert((ExtType == ISD::EXTLOAD || MVT::isInteger(VT)) && + assert((ExtType == ISD::EXTLOAD || VT.isInteger()) && "Cannot sign/zero extend a FP/Vector load!"); - assert(MVT::isInteger(VT) == MVT::isInteger(EVT) && + assert(VT.isInteger() == EVT.isInteger() && "Cannot convert from FP to Int or Int -> FP!"); } @@ -3071,7 +3064,7 @@ AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3); ID.AddInteger(AM); ID.AddInteger(ExtType); - ID.AddInteger((unsigned int)EVT); + ID.AddInteger(EVT.V); ID.AddInteger(Alignment); ID.AddInteger(isVolatile); void *IP = 0; @@ -3084,7 +3077,7 @@ return SDOperand(N, 0); } -SDOperand SelectionDAG::getLoad(MVT::ValueType VT, +SDOperand SelectionDAG::getLoad(MVT VT, SDOperand Chain, SDOperand Ptr, const Value *SV, int SVOffset, bool isVolatile, unsigned Alignment) { @@ -3093,10 +3086,10 @@ SV, SVOffset, VT, isVolatile, Alignment); } -SDOperand SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, MVT::ValueType VT, +SDOperand SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, MVT VT, SDOperand Chain, SDOperand Ptr, const Value *SV, - int SVOffset, MVT::ValueType EVT, + int SVOffset, MVT EVT, bool isVolatile, unsigned Alignment) { SDOperand Undef = getNode(ISD::UNDEF, Ptr.getValueType()); return getLoad(ISD::UNINDEXED, ExtType, VT, Chain, Ptr, Undef, @@ -3118,12 +3111,12 @@ SDOperand SelectionDAG::getStore(SDOperand Chain, SDOperand Val, SDOperand Ptr, const Value *SV, int SVOffset, bool isVolatile, unsigned Alignment) { - MVT::ValueType VT = Val.getValueType(); + MVT VT = Val.getValueType(); if (Alignment == 0) { // Ensure that codegen never sees alignment 0 const Type *Ty = 0; if (VT != MVT::iPTR) { - Ty = MVT::getTypeForValueType(VT); + Ty = VT.getTypeForMVT(); } else if (SV) { const PointerType *PT = dyn_cast(SV->getType()); assert(PT && "Value for store must be a pointer"); @@ -3139,7 +3132,7 @@ AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); ID.AddInteger(ISD::UNINDEXED); ID.AddInteger(false); - ID.AddInteger((unsigned int)VT); + ID.AddInteger(VT.V); ID.AddInteger(Alignment); ID.AddInteger(isVolatile); void *IP = 0; @@ -3154,22 +3147,22 @@ SDOperand SelectionDAG::getTruncStore(SDOperand Chain, SDOperand Val, SDOperand Ptr, const Value *SV, - int SVOffset, MVT::ValueType SVT, + int SVOffset, MVT SVT, bool isVolatile, unsigned Alignment) { - MVT::ValueType VT = Val.getValueType(); + MVT VT = Val.getValueType(); if (VT == SVT) return getStore(Chain, Val, Ptr, SV, SVOffset, isVolatile, Alignment); - assert(MVT::getSizeInBits(VT) > MVT::getSizeInBits(SVT) && + assert(VT.getSizeInBits() > SVT.getSizeInBits() && "Not a truncation?"); - assert(MVT::isInteger(VT) == MVT::isInteger(SVT) && + assert(VT.isInteger() == SVT.isInteger() && "Can't do FP-INT conversion!"); if (Alignment == 0) { // Ensure that codegen never sees alignment 0 const Type *Ty = 0; if (VT != MVT::iPTR) { - Ty = MVT::getTypeForValueType(VT); + Ty = VT.getTypeForMVT(); } else if (SV) { const PointerType *PT = dyn_cast(SV->getType()); assert(PT && "Value for store must be a pointer"); @@ -3185,7 +3178,7 @@ AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); ID.AddInteger(ISD::UNINDEXED); ID.AddInteger(1); - ID.AddInteger((unsigned int)SVT); + ID.AddInteger(SVT.V); ID.AddInteger(Alignment); ID.AddInteger(isVolatile); void *IP = 0; @@ -3210,7 +3203,7 @@ AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); ID.AddInteger(AM); ID.AddInteger(ST->isTruncatingStore()); - ID.AddInteger((unsigned int)(ST->getMemoryVT())); + ID.AddInteger(ST->getMemoryVT().V); ID.AddInteger(ST->getAlignment()); ID.AddInteger(ST->isVolatile()); void *IP = 0; @@ -3225,14 +3218,14 @@ return SDOperand(N, 0); } -SDOperand SelectionDAG::getVAArg(MVT::ValueType VT, +SDOperand SelectionDAG::getVAArg(MVT VT, SDOperand Chain, SDOperand Ptr, SDOperand SV) { SDOperand Ops[] = { Chain, Ptr, SV }; return getNode(ISD::VAARG, getVTList(VT, MVT::Other), Ops, 3); } -SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, +SDOperand SelectionDAG::getNode(unsigned Opcode, MVT VT, SDOperandPtr Ops, unsigned NumOps) { switch (NumOps) { case 0: return getNode(Opcode, VT); @@ -3281,14 +3274,14 @@ } SDOperand SelectionDAG::getNode(unsigned Opcode, - std::vector &ResultTys, + std::vector &ResultTys, SDOperandPtr Ops, unsigned NumOps) { return getNode(Opcode, getNodeValueTypes(ResultTys), ResultTys.size(), Ops, NumOps); } SDOperand SelectionDAG::getNode(unsigned Opcode, - const MVT::ValueType *VTs, unsigned NumVTs, + const MVT *VTs, unsigned NumVTs, SDOperandPtr Ops, unsigned NumOps) { if (NumVTs == 1) return getNode(Opcode, VTs[0], Ops, NumOps); @@ -3315,7 +3308,7 @@ if (ConstantSDNode *AndRHS = dyn_cast(N3.getOperand(1))) { // If the and is only masking out bits that cannot effect the shift, // eliminate the and. - unsigned NumBits = MVT::getSizeInBits(VT)*2; + unsigned NumBits = VT.getSizeInBits()*2; if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); } @@ -3390,31 +3383,31 @@ return getNode(Opcode, VTList, Ops, 5); } -SDVTList SelectionDAG::getVTList(MVT::ValueType VT) { +SDVTList SelectionDAG::getVTList(MVT VT) { return makeVTList(SDNode::getValueTypeList(VT), 1); } -SDVTList SelectionDAG::getVTList(MVT::ValueType VT1, MVT::ValueType VT2) { - for (std::list >::iterator I = VTList.begin(), +SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2) { + for (std::list >::iterator I = VTList.begin(), E = VTList.end(); I != E; ++I) { if (I->size() == 2 && (*I)[0] == VT1 && (*I)[1] == VT2) return makeVTList(&(*I)[0], 2); } - std::vector V; + std::vector V; V.push_back(VT1); V.push_back(VT2); VTList.push_front(V); return makeVTList(&(*VTList.begin())[0], 2); } -SDVTList SelectionDAG::getVTList(MVT::ValueType VT1, MVT::ValueType VT2, - MVT::ValueType VT3) { - for (std::list >::iterator I = VTList.begin(), +SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, + MVT VT3) { + for (std::list >::iterator I = VTList.begin(), E = VTList.end(); I != E; ++I) { if (I->size() == 3 && (*I)[0] == VT1 && (*I)[1] == VT2 && (*I)[2] == VT3) return makeVTList(&(*I)[0], 3); } - std::vector V; + std::vector V; V.push_back(VT1); V.push_back(VT2); V.push_back(VT3); @@ -3422,7 +3415,7 @@ return makeVTList(&(*VTList.begin())[0], 3); } -SDVTList SelectionDAG::getVTList(const MVT::ValueType *VTs, unsigned NumVTs) { +SDVTList SelectionDAG::getVTList(const MVT *VTs, unsigned NumVTs) { switch (NumVTs) { case 0: assert(0 && "Cannot have nodes without results!"); case 1: return getVTList(VTs[0]); @@ -3431,7 +3424,7 @@ default: break; } - for (std::list >::iterator I = VTList.begin(), + for (std::list >::iterator I = VTList.begin(), E = VTList.end(); I != E; ++I) { if (I->size() != NumVTs || VTs[0] != (*I)[0] || VTs[1] != (*I)[1]) continue; @@ -3445,7 +3438,7 @@ return makeVTList(&*I->begin(), NumVTs); } - VTList.push_front(std::vector(VTs, VTs+NumVTs)); + VTList.push_front(std::vector(VTs, VTs+NumVTs)); return makeVTList(&*VTList.begin()->begin(), NumVTs); } @@ -3628,7 +3621,7 @@ /// node of the specified opcode and operands, it returns that node instead of /// the current one. SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc, - MVT::ValueType VT) { + MVT VT) { SDVTList VTs = getVTList(VT); FoldingSetNodeID ID; AddNodeIDNode(ID, ISD::BUILTIN_OP_END+TargetOpc, VTs, (SDOperand*)0, 0); @@ -3645,7 +3638,7 @@ } SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc, - MVT::ValueType VT, SDOperand Op1) { + MVT VT, SDOperand Op1) { // If an identical node already exists, use it. SDVTList VTs = getVTList(VT); SDOperand Ops[] = { Op1 }; @@ -3663,7 +3656,7 @@ } SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc, - MVT::ValueType VT, SDOperand Op1, + MVT VT, SDOperand Op1, SDOperand Op2) { // If an identical node already exists, use it. SDVTList VTs = getVTList(VT); @@ -3684,7 +3677,7 @@ } SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc, - MVT::ValueType VT, SDOperand Op1, + MVT VT, SDOperand Op1, SDOperand Op2, SDOperand Op3) { // If an identical node already exists, use it. SDVTList VTs = getVTList(VT); @@ -3704,7 +3697,7 @@ } SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc, - MVT::ValueType VT, SDOperandPtr Ops, + MVT VT, SDOperandPtr Ops, unsigned NumOps) { // If an identical node already exists, use it. SDVTList VTs = getVTList(VT); @@ -3722,7 +3715,7 @@ } SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc, - MVT::ValueType VT1, MVT::ValueType VT2, + MVT VT1, MVT VT2, SDOperand Op1, SDOperand Op2) { SDVTList VTs = getVTList(VT1, VT2); FoldingSetNodeID ID; @@ -3739,7 +3732,7 @@ } SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc, - MVT::ValueType VT1, MVT::ValueType VT2, + MVT VT1, MVT VT2, SDOperand Op1, SDOperand Op2, SDOperand Op3) { // If an identical node already exists, use it. @@ -3765,94 +3758,87 @@ /// Note that getTargetNode returns the resultant node. If there is already a /// node of the specified opcode and operands, it returns that node instead of /// the current one. -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT) { +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT) { return getNode(ISD::BUILTIN_OP_END+Opcode, VT).Val; } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT, - SDOperand Op1) { +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, SDOperand Op1) { return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Op1).Val; } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT, +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, SDOperand Op1, SDOperand Op2) { return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Op1, Op2).Val; } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT, +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, SDOperand Op1, SDOperand Op2, SDOperand Op3) { return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Op1, Op2, Op3).Val; } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT, +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, SDOperandPtr Ops, unsigned NumOps) { return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Ops, NumOps).Val; } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1, - MVT::ValueType VT2) { - const MVT::ValueType *VTs = getNodeValueTypes(VT1, VT2); +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2) { + const MVT *VTs = getNodeValueTypes(VT1, VT2); SDOperand Op; return getNode(ISD::BUILTIN_OP_END+Opcode, VTs, 2, &Op, 0).Val; } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1, - MVT::ValueType VT2, SDOperand Op1) { - const MVT::ValueType *VTs = getNodeValueTypes(VT1, VT2); +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, + MVT VT2, SDOperand Op1) { + const MVT *VTs = getNodeValueTypes(VT1, VT2); return getNode(ISD::BUILTIN_OP_END+Opcode, VTs, 2, &Op1, 1).Val; } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1, - MVT::ValueType VT2, SDOperand Op1, +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, + MVT VT2, SDOperand Op1, SDOperand Op2) { - const MVT::ValueType *VTs = getNodeValueTypes(VT1, VT2); + const MVT *VTs = getNodeValueTypes(VT1, VT2); SDOperand Ops[] = { Op1, Op2 }; return getNode(ISD::BUILTIN_OP_END+Opcode, VTs, 2, Ops, 2).Val; } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1, - MVT::ValueType VT2, SDOperand Op1, +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, + MVT VT2, SDOperand Op1, SDOperand Op2, SDOperand Op3) { - const MVT::ValueType *VTs = getNodeValueTypes(VT1, VT2); + const MVT *VTs = getNodeValueTypes(VT1, VT2); SDOperand Ops[] = { Op1, Op2, Op3 }; return getNode(ISD::BUILTIN_OP_END+Opcode, VTs, 2, Ops, 3).Val; } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1, - MVT::ValueType VT2, +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, SDOperandPtr Ops, unsigned NumOps) { - const MVT::ValueType *VTs = getNodeValueTypes(VT1, VT2); + const MVT *VTs = getNodeValueTypes(VT1, VT2); return getNode(ISD::BUILTIN_OP_END+Opcode, VTs, 2, Ops, NumOps).Val; } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1, - MVT::ValueType VT2, MVT::ValueType VT3, +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, SDOperand Op1, SDOperand Op2) { - const MVT::ValueType *VTs = getNodeValueTypes(VT1, VT2, VT3); + const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); SDOperand Ops[] = { Op1, Op2 }; return getNode(ISD::BUILTIN_OP_END+Opcode, VTs, 3, Ops, 2).Val; } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1, - MVT::ValueType VT2, MVT::ValueType VT3, +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, SDOperand Op1, SDOperand Op2, SDOperand Op3) { - const MVT::ValueType *VTs = getNodeValueTypes(VT1, VT2, VT3); + const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); SDOperand Ops[] = { Op1, Op2, Op3 }; return getNode(ISD::BUILTIN_OP_END+Opcode, VTs, 3, Ops, 3).Val; } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1, - MVT::ValueType VT2, MVT::ValueType VT3, +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, SDOperandPtr Ops, unsigned NumOps) { - const MVT::ValueType *VTs = getNodeValueTypes(VT1, VT2, VT3); + const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); return getNode(ISD::BUILTIN_OP_END+Opcode, VTs, 3, Ops, NumOps).Val; } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1, - MVT::ValueType VT2, MVT::ValueType VT3, - MVT::ValueType VT4, +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, + MVT VT2, MVT VT3, MVT VT4, SDOperandPtr Ops, unsigned NumOps) { - std::vector VTList; + std::vector VTList; VTList.push_back(VT1); VTList.push_back(VT2); VTList.push_back(VT3); VTList.push_back(VT4); - const MVT::ValueType *VTs = getNodeValueTypes(VTList); + const MVT *VTs = getNodeValueTypes(VTList); return getNode(ISD::BUILTIN_OP_END+Opcode, VTs, 4, Ops, NumOps).Val; } SDNode *SelectionDAG::getTargetNode(unsigned Opcode, - std::vector &ResultTys, + std::vector &ResultTys, SDOperandPtr Ops, unsigned NumOps) { - const MVT::ValueType *VTs = getNodeValueTypes(ResultTys); + const MVT *VTs = getNodeValueTypes(ResultTys); return getNode(ISD::BUILTIN_OP_END+Opcode, VTs, ResultTys.size(), Ops, NumOps).Val; } @@ -4200,7 +4186,7 @@ } GlobalAddressSDNode::GlobalAddressSDNode(bool isTarget, const GlobalValue *GA, - MVT::ValueType VT, int o) + MVT VT, int o) : SDNode(isa(GA) && cast(GA)->isThreadLocal() ? // Thread Local @@ -4214,7 +4200,7 @@ /// getMemOperand - Return a MachineMemOperand object describing the memory /// reference performed by this load or store. MachineMemOperand LSBaseSDNode::getMemOperand() const { - int Size = (MVT::getSizeInBits(getMemoryVT()) + 7) >> 3; + int Size = (getMemoryVT().getSizeInBits() + 7) >> 3; int Flags = getOpcode() == ISD::LOAD ? MachineMemOperand::MOLoad : MachineMemOperand::MOStore; @@ -4240,14 +4226,14 @@ /// getValueTypeList - Return a pointer to the specified value type. /// -const MVT::ValueType *SDNode::getValueTypeList(MVT::ValueType VT) { - if (MVT::isExtendedVT(VT)) { - static std::set EVTs; +const MVT *SDNode::getValueTypeList(MVT VT) { + if (VT.isExtended()) { + static std::set EVTs; return &(*EVTs.insert(VT).first); } else { - static MVT::ValueType VTs[MVT::LAST_VALUETYPE]; - VTs[VT] = VT; - return &VTs[VT]; + static MVT VTs[MVT::LAST_VALUETYPE]; + VTs[VT.getSimpleVT()] = VT; + return &VTs[VT.getSimpleVT()]; } } @@ -4684,7 +4670,7 @@ if (getValueType(i) == MVT::Other) cerr << "ch"; else - cerr << MVT::getValueTypeString(getValueType(i)); + cerr << getValueType(i).getMVTString(); } cerr << " = " << getOperationName(G); @@ -4773,7 +4759,7 @@ } else if (const ARG_FLAGSSDNode *N = dyn_cast(this)) { cerr << N->getArgFlags().getArgFlagsString(); } else if (const VTSDNode *N = dyn_cast(this)) { - cerr << ":" << MVT::getValueTypeString(N->getVT()); + cerr << ":" << N->getVT().getMVTString(); } else if (const LoadSDNode *LD = dyn_cast(this)) { const Value *SrcValue = LD->getSrcValue(); int SrcOffset = LD->getSrcValueOffset(); @@ -4798,7 +4784,7 @@ break; } if (doExt) - cerr << MVT::getValueTypeString(LD->getMemoryVT()) << ">"; + cerr << LD->getMemoryVT().getMVTString() << ">"; const char *AM = getIndexedModeName(LD->getAddressingMode()); if (*AM) @@ -4818,7 +4804,7 @@ if (ST->isTruncatingStore()) cerr << " getMemoryVT()) << ">"; + << ST->getMemoryVT().getMVTString() << ">"; const char *AM = getIndexedModeName(ST->getAddressingMode()); if (*AM) Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Fri Jun 6 07:08:01 2008 @@ -88,10 +88,10 @@ namespace { struct SDISelAsmOperandInfo; } /// ComputeValueVTs - Given an LLVM IR type, compute a sequence of -/// MVT::ValueTypes that represent all the individual underlying +/// MVTs that represent all the individual underlying /// non-aggregate types that comprise it. static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty, - SmallVectorImpl &ValueVTs) { + SmallVectorImpl &ValueVTs) { // Given a struct type, recursively traverse the elements. if (const StructType *STy = dyn_cast(Ty)) { for (StructType::element_iterator EI = STy->element_begin(), @@ -107,7 +107,7 @@ ComputeValueVTs(TLI, EltTy, ValueVTs); return; } - // Base case: we can get an MVT::ValueType for this LLVM IR type. + // Base case: we can get an MVT for this LLVM IR type. ValueVTs.push_back(TLI.getValueType(Ty)); } @@ -129,7 +129,7 @@ /// ValueVTs - The value types of the values, which may not be legal, and /// may need be promoted or synthesized from one or more registers. /// - SmallVector ValueVTs; + SmallVector ValueVTs; /// RegVTs - The value types of the registers. This is the same size as /// ValueVTs and it records, for each value, what the type of the assigned @@ -140,7 +140,7 @@ /// getRegisterType member function, however when with physical registers /// it is necessary to have a separate record of the types. /// - SmallVector RegVTs; + SmallVector RegVTs; /// Regs - This list holds the registers assigned to the values. /// Each legal or promoted value requires one register, and each @@ -152,21 +152,21 @@ RegsForValue(const TargetLowering &tli, const SmallVector ®s, - MVT::ValueType regvt, MVT::ValueType valuevt) + MVT regvt, MVT valuevt) : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} RegsForValue(const TargetLowering &tli, const SmallVector ®s, - const SmallVector ®vts, - const SmallVector &valuevts) + const SmallVector ®vts, + const SmallVector &valuevts) : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {} RegsForValue(const TargetLowering &tli, unsigned Reg, const Type *Ty) : TLI(&tli) { ComputeValueVTs(tli, Ty, ValueVTs); for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { - MVT::ValueType ValueVT = ValueVTs[Value]; + MVT ValueVT = ValueVTs[Value]; unsigned NumRegs = TLI->getNumRegisters(ValueVT); - MVT::ValueType RegisterVT = TLI->getRegisterType(ValueVT); + MVT RegisterVT = TLI->getRegisterType(ValueVT); for (unsigned i = 0; i != NumRegs; ++i) Regs.push_back(Reg + i); RegVTs.push_back(RegisterVT); @@ -254,7 +254,7 @@ SmallSet CatchInfoFound; #endif - unsigned MakeReg(MVT::ValueType VT) { + unsigned MakeReg(MVT VT) { return RegInfo.createVirtualRegister(TLI.getRegClassFor(VT)); } @@ -359,7 +359,7 @@ for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast(I)); ++I){ if (PN->use_empty()) continue; - MVT::ValueType VT = TLI.getValueType(PN->getType()); + MVT VT = TLI.getValueType(PN->getType()); unsigned NumRegisters = TLI.getNumRegisters(VT); unsigned PHIReg = ValueMap[PN]; assert(PHIReg && "PHI node does not have an assigned virtual register!"); @@ -378,13 +378,13 @@ /// will assign registers for each member or element. /// unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) { - SmallVector ValueVTs; + SmallVector ValueVTs; ComputeValueVTs(TLI, V->getType(), ValueVTs); unsigned FirstReg = 0; for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { - MVT::ValueType ValueVT = ValueVTs[Value]; - MVT::ValueType RegisterVT = TLI.getRegisterType(ValueVT); + MVT ValueVT = ValueVTs[Value]; + MVT RegisterVT = TLI.getRegisterType(ValueVT); unsigned NumRegs = TLI.getNumRegisters(ValueVT); for (unsigned i = 0; i != NumRegs; ++i) { @@ -751,8 +751,8 @@ static SDOperand getCopyFromParts(SelectionDAG &DAG, const SDOperand *Parts, unsigned NumParts, - MVT::ValueType PartVT, - MVT::ValueType ValueVT, + MVT PartVT, + MVT ValueVT, ISD::NodeType AssertOp = ISD::DELETED_NODE) { assert(NumParts > 0 && "No parts to assemble!"); TargetLowering &TLI = DAG.getTargetLoweringInfo(); @@ -760,20 +760,20 @@ if (NumParts > 1) { // Assemble the value from multiple parts. - if (!MVT::isVector(ValueVT)) { - unsigned PartBits = MVT::getSizeInBits(PartVT); - unsigned ValueBits = MVT::getSizeInBits(ValueVT); + if (!ValueVT.isVector()) { + unsigned PartBits = PartVT.getSizeInBits(); + unsigned ValueBits = ValueVT.getSizeInBits(); // Assemble the power of 2 part. unsigned RoundParts = NumParts & (NumParts - 1) ? 1 << Log2_32(NumParts) : NumParts; unsigned RoundBits = PartBits * RoundParts; - MVT::ValueType RoundVT = RoundBits == ValueBits ? - ValueVT : MVT::getIntegerType(RoundBits); + MVT RoundVT = RoundBits == ValueBits ? + ValueVT : MVT::getIntegerVT(RoundBits); SDOperand Lo, Hi; if (RoundParts > 2) { - MVT::ValueType HalfVT = MVT::getIntegerType(RoundBits/2); + MVT HalfVT = MVT::getIntegerVT(RoundBits/2); Lo = getCopyFromParts(DAG, Parts, RoundParts/2, PartVT, HalfVT); Hi = getCopyFromParts(DAG, Parts+RoundParts/2, RoundParts/2, PartVT, HalfVT); @@ -788,24 +788,24 @@ if (RoundParts < NumParts) { // Assemble the trailing non-power-of-2 part. unsigned OddParts = NumParts - RoundParts; - MVT::ValueType OddVT = MVT::getIntegerType(OddParts * PartBits); + MVT OddVT = MVT::getIntegerVT(OddParts * PartBits); Hi = getCopyFromParts(DAG, Parts+RoundParts, OddParts, PartVT, OddVT); // Combine the round and odd parts. Lo = Val; if (TLI.isBigEndian()) std::swap(Lo, Hi); - MVT::ValueType TotalVT = MVT::getIntegerType(NumParts * PartBits); + MVT TotalVT = MVT::getIntegerVT(NumParts * PartBits); Hi = DAG.getNode(ISD::ANY_EXTEND, TotalVT, Hi); Hi = DAG.getNode(ISD::SHL, TotalVT, Hi, - DAG.getConstant(MVT::getSizeInBits(Lo.getValueType()), + DAG.getConstant(Lo.getValueType().getSizeInBits(), TLI.getShiftAmountTy())); Lo = DAG.getNode(ISD::ZERO_EXTEND, TotalVT, Lo); Val = DAG.getNode(ISD::OR, TotalVT, Lo, Hi); } } else { // Handle a multi-element vector. - MVT::ValueType IntermediateVT, RegisterVT; + MVT IntermediateVT, RegisterVT; unsigned NumIntermediates; unsigned NumRegs = TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates, @@ -837,7 +837,7 @@ // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate // operands. - Val = DAG.getNode(MVT::isVector(IntermediateVT) ? + Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, ValueVT, &Ops[0], NumIntermediates); } @@ -849,21 +849,21 @@ if (PartVT == ValueVT) return Val; - if (MVT::isVector(PartVT)) { - assert(MVT::isVector(ValueVT) && "Unknown vector conversion!"); + if (PartVT.isVector()) { + assert(ValueVT.isVector() && "Unknown vector conversion!"); return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val); } - if (MVT::isVector(ValueVT)) { - assert(MVT::getVectorElementType(ValueVT) == PartVT && - MVT::getVectorNumElements(ValueVT) == 1 && + if (ValueVT.isVector()) { + assert(ValueVT.getVectorElementType() == PartVT && + ValueVT.getVectorNumElements() == 1 && "Only trivial scalar-to-vector conversions should get here!"); return DAG.getNode(ISD::BUILD_VECTOR, ValueVT, Val); } - if (MVT::isInteger(PartVT) && - MVT::isInteger(ValueVT)) { - if (MVT::getSizeInBits(ValueVT) < MVT::getSizeInBits(PartVT)) { + if (PartVT.isInteger() && + ValueVT.isInteger()) { + if (ValueVT.getSizeInBits() < PartVT.getSizeInBits()) { // For a truncate, see if we have any information to // indicate whether the truncated bits will always be // zero or sign-extension. @@ -876,7 +876,7 @@ } } - if (MVT::isFloatingPoint(PartVT) && MVT::isFloatingPoint(ValueVT)) { + if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { if (ValueVT < Val.getValueType()) // FP_ROUND's are always exact here. return DAG.getNode(ISD::FP_ROUND, ValueVT, Val, @@ -884,7 +884,7 @@ return DAG.getNode(ISD::FP_EXTEND, ValueVT, Val); } - if (MVT::getSizeInBits(PartVT) == MVT::getSizeInBits(ValueVT)) + if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val); assert(0 && "Unknown mismatch!"); @@ -898,43 +898,43 @@ SDOperand Val, SDOperand *Parts, unsigned NumParts, - MVT::ValueType PartVT, + MVT PartVT, ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { TargetLowering &TLI = DAG.getTargetLoweringInfo(); - MVT::ValueType PtrVT = TLI.getPointerTy(); - MVT::ValueType ValueVT = Val.getValueType(); - unsigned PartBits = MVT::getSizeInBits(PartVT); + MVT PtrVT = TLI.getPointerTy(); + MVT ValueVT = Val.getValueType(); + unsigned PartBits = PartVT.getSizeInBits(); assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!"); if (!NumParts) return; - if (!MVT::isVector(ValueVT)) { + if (!ValueVT.isVector()) { if (PartVT == ValueVT) { assert(NumParts == 1 && "No-op copy with multiple parts!"); Parts[0] = Val; return; } - if (NumParts * PartBits > MVT::getSizeInBits(ValueVT)) { + if (NumParts * PartBits > ValueVT.getSizeInBits()) { // If the parts cover more bits than the value has, promote the value. - if (MVT::isFloatingPoint(PartVT) && MVT::isFloatingPoint(ValueVT)) { + if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { assert(NumParts == 1 && "Do not know what to promote to!"); Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val); - } else if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) { - ValueVT = MVT::getIntegerType(NumParts * PartBits); + } else if (PartVT.isInteger() && ValueVT.isInteger()) { + ValueVT = MVT::getIntegerVT(NumParts * PartBits); Val = DAG.getNode(ExtendKind, ValueVT, Val); } else { assert(0 && "Unknown mismatch!"); } - } else if (PartBits == MVT::getSizeInBits(ValueVT)) { + } else if (PartBits == ValueVT.getSizeInBits()) { // Different types of the same size. assert(NumParts == 1 && PartVT != ValueVT); Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val); - } else if (NumParts * PartBits < MVT::getSizeInBits(ValueVT)) { + } else if (NumParts * PartBits < ValueVT.getSizeInBits()) { // If the parts cover less bits than value has, truncate the value. - if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) { - ValueVT = MVT::getIntegerType(NumParts * PartBits); + if (PartVT.isInteger() && ValueVT.isInteger()) { + ValueVT = MVT::getIntegerVT(NumParts * PartBits); Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val); } else { assert(0 && "Unknown mismatch!"); @@ -943,7 +943,7 @@ // The value may have changed - recompute ValueVT. ValueVT = Val.getValueType(); - assert(NumParts * PartBits == MVT::getSizeInBits(ValueVT) && + assert(NumParts * PartBits == ValueVT.getSizeInBits() && "Failed to tile the value with PartVT!"); if (NumParts == 1) { @@ -955,7 +955,7 @@ // Expand the value into multiple parts. if (NumParts & (NumParts - 1)) { // The number of parts is not a power of 2. Split off and copy the tail. - assert(MVT::isInteger(PartVT) && MVT::isInteger(ValueVT) && + assert(PartVT.isInteger() && ValueVT.isInteger() && "Do not know what to expand to!"); unsigned RoundParts = 1 << Log2_32(NumParts); unsigned RoundBits = RoundParts * PartBits; @@ -968,19 +968,19 @@ // The odd parts were reversed by getCopyToParts - unreverse them. std::reverse(Parts + RoundParts, Parts + NumParts); NumParts = RoundParts; - ValueVT = MVT::getIntegerType(NumParts * PartBits); + ValueVT = MVT::getIntegerVT(NumParts * PartBits); Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val); } // The number of parts is a power of 2. Repeatedly bisect the value using // EXTRACT_ELEMENT. Parts[0] = DAG.getNode(ISD::BIT_CONVERT, - MVT::getIntegerType(MVT::getSizeInBits(ValueVT)), + MVT::getIntegerVT(ValueVT.getSizeInBits()), Val); for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { for (unsigned i = 0; i < NumParts; i += StepSize) { unsigned ThisBits = StepSize * PartBits / 2; - MVT::ValueType ThisVT = MVT::getIntegerType (ThisBits); + MVT ThisVT = MVT::getIntegerVT (ThisBits); SDOperand &Part0 = Parts[i]; SDOperand &Part1 = Parts[i+StepSize/2]; @@ -1005,11 +1005,11 @@ // Vector ValueVT. if (NumParts == 1) { if (PartVT != ValueVT) { - if (MVT::isVector(PartVT)) { + if (PartVT.isVector()) { Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val); } else { - assert(MVT::getVectorElementType(ValueVT) == PartVT && - MVT::getVectorNumElements(ValueVT) == 1 && + assert(ValueVT.getVectorElementType() == PartVT && + ValueVT.getVectorNumElements() == 1 && "Only trivial vector-to-scalar conversions should get here!"); Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, PartVT, Val, DAG.getConstant(0, PtrVT)); @@ -1021,13 +1021,13 @@ } // Handle a multi-element vector. - MVT::ValueType IntermediateVT, RegisterVT; + MVT IntermediateVT, RegisterVT; unsigned NumIntermediates; unsigned NumRegs = DAG.getTargetLoweringInfo() .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates, RegisterVT); - unsigned NumElements = MVT::getVectorNumElements(ValueVT); + unsigned NumElements = ValueVT.getVectorNumElements(); assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); NumParts = NumRegs; // Silence a compiler warning. @@ -1036,7 +1036,7 @@ // Split the vector into intermediate operands. SmallVector Ops(NumIntermediates); for (unsigned i = 0; i != NumIntermediates; ++i) - if (MVT::isVector(IntermediateVT)) + if (IntermediateVT.isVector()) Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, IntermediateVT, Val, DAG.getConstant(i * (NumElements / NumIntermediates), @@ -1069,7 +1069,7 @@ if (N.Val) return N; if (Constant *C = const_cast(dyn_cast(V))) { - MVT::ValueType VT = TLI.getValueType(V->getType(), true); + MVT VT = TLI.getValueType(V->getType(), true); if (ConstantInt *CI = dyn_cast(C)) return N = DAG.getConstant(CI->getValue(), VT); @@ -1105,12 +1105,12 @@ } else { assert((isa(C) || isa(C)) && "Unknown vector constant!"); - MVT::ValueType EltVT = TLI.getValueType(VecTy->getElementType()); + MVT EltVT = TLI.getValueType(VecTy->getElementType()); SDOperand Op; if (isa(C)) Op = DAG.getNode(ISD::UNDEF, EltVT); - else if (MVT::isFloatingPoint(EltVT)) + else if (EltVT.isFloatingPoint()) Op = DAG.getConstantFP(0, EltVT); else Op = DAG.getConstant(0, EltVT); @@ -1149,18 +1149,18 @@ NewValues.push_back(getControlRoot()); for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) { SDOperand RetOp = getValue(I.getOperand(i)); - MVT::ValueType VT = RetOp.getValueType(); + MVT VT = RetOp.getValueType(); // FIXME: C calling convention requires the return type to be promoted to // at least 32-bit. But this is not necessary for non-C calling conventions. - if (MVT::isInteger(VT)) { - MVT::ValueType MinVT = TLI.getRegisterType(MVT::i32); - if (MVT::getSizeInBits(VT) < MVT::getSizeInBits(MinVT)) + if (VT.isInteger()) { + MVT MinVT = TLI.getRegisterType(MVT::i32); + if (VT.getSizeInBits() < MinVT.getSizeInBits()) VT = MinVT; } unsigned NumParts = TLI.getNumRegisters(VT); - MVT::ValueType PartVT = TLI.getRegisterType(VT); + MVT PartVT = TLI.getRegisterType(VT); SmallVector Parts(NumParts); ISD::NodeType ExtendKind = ISD::ANY_EXTEND; @@ -1475,7 +1475,7 @@ uint64_t High = cast(CB.CmpRHS)->getSExtValue(); SDOperand CmpOp = getValue(CB.CmpMHS); - MVT::ValueType VT = CmpOp.getValueType(); + MVT VT = CmpOp.getValueType(); if (cast(CB.CmpLHS)->isMinValue(true)) { Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE); @@ -1517,7 +1517,7 @@ void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) { // Emit the code for the jump table assert(JT.Reg != -1U && "Should lower JT Header first!"); - MVT::ValueType PTy = TLI.getPointerTy(); + MVT PTy = TLI.getPointerTy(); SDOperand Index = DAG.getCopyFromReg(getControlRoot(), JT.Reg, PTy); SDOperand Table = DAG.getJumpTable(JT.JTI, PTy); DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1), @@ -1533,7 +1533,7 @@ // and conditional branch to default mbb if the result is greater than the // difference between smallest and largest cases. SDOperand SwitchOp = getValue(JTH.SValue); - MVT::ValueType VT = SwitchOp.getValueType(); + MVT VT = SwitchOp.getValueType(); SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp, DAG.getConstant(JTH.First, VT)); @@ -1542,7 +1542,7 @@ // register so it can be used as an index into the jump table in a // subsequent basic block. This value may be smaller or larger than the // target's pointer type, and therefore require extension or truncating. - if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy())) + if (VT.getSizeInBits() > TLI.getPointerTy().getSizeInBits()) SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB); else SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB); @@ -1582,7 +1582,7 @@ void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) { // Subtract the minimum value SDOperand SwitchOp = getValue(B.SValue); - MVT::ValueType VT = SwitchOp.getValueType(); + MVT VT = SwitchOp.getValueType(); SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp, DAG.getConstant(B.First, VT)); @@ -1592,7 +1592,7 @@ ISD::SETUGT); SDOperand ShiftOp; - if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getShiftAmountTy())) + if (VT.getSizeInBits() > TLI.getShiftAmountTy().getSizeInBits()) ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB); else ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB); @@ -2005,7 +2005,7 @@ CaseRecVector& WorkList, Value* SV, MachineBasicBlock* Default){ - unsigned IntPtrBits = MVT::getSizeInBits(TLI.getPointerTy()); + unsigned IntPtrBits = TLI.getPointerTy().getSizeInBits(); Case& FrontCase = *CR.Range.first; Case& BackCase = *(CR.Range.second-1); @@ -2271,8 +2271,8 @@ SDOperand Op1 = getValue(I.getOperand(0)); SDOperand Op2 = getValue(I.getOperand(1)); - if (MVT::getSizeInBits(TLI.getShiftAmountTy()) < - MVT::getSizeInBits(Op2.getValueType())) + if (TLI.getShiftAmountTy().getSizeInBits() < + Op2.getValueType().getSizeInBits()) Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2); else if (TLI.getShiftAmountTy() > Op2.getValueType()) Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2); @@ -2410,7 +2410,7 @@ else Condition = FPC; - MVT::ValueType DestVT = TLI.getValueType(I.getType()); + MVT DestVT = TLI.getValueType(I.getType()); setValue(&I, DAG.getVSetCC(DestVT, Op1, Op2, Condition)); } @@ -2427,7 +2427,7 @@ void SelectionDAGLowering::visitTrunc(User &I) { // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). SDOperand N = getValue(I.getOperand(0)); - MVT::ValueType DestVT = TLI.getValueType(I.getType()); + MVT DestVT = TLI.getValueType(I.getType()); setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); } @@ -2435,7 +2435,7 @@ // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). // ZExt also can't be a cast to bool for same reason. So, nothing much to do SDOperand N = getValue(I.getOperand(0)); - MVT::ValueType DestVT = TLI.getValueType(I.getType()); + MVT DestVT = TLI.getValueType(I.getType()); setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N)); } @@ -2443,49 +2443,49 @@ // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). // SExt also can't be a cast to bool for same reason. So, nothing much to do SDOperand N = getValue(I.getOperand(0)); - MVT::ValueType DestVT = TLI.getValueType(I.getType()); + MVT DestVT = TLI.getValueType(I.getType()); setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N)); } void SelectionDAGLowering::visitFPTrunc(User &I) { // FPTrunc is never a no-op cast, no need to check SDOperand N = getValue(I.getOperand(0)); - MVT::ValueType DestVT = TLI.getValueType(I.getType()); + MVT DestVT = TLI.getValueType(I.getType()); setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N, DAG.getIntPtrConstant(0))); } void SelectionDAGLowering::visitFPExt(User &I){ // FPTrunc is never a no-op cast, no need to check SDOperand N = getValue(I.getOperand(0)); - MVT::ValueType DestVT = TLI.getValueType(I.getType()); + MVT DestVT = TLI.getValueType(I.getType()); setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N)); } void SelectionDAGLowering::visitFPToUI(User &I) { // FPToUI is never a no-op cast, no need to check SDOperand N = getValue(I.getOperand(0)); - MVT::ValueType DestVT = TLI.getValueType(I.getType()); + MVT DestVT = TLI.getValueType(I.getType()); setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N)); } void SelectionDAGLowering::visitFPToSI(User &I) { // FPToSI is never a no-op cast, no need to check SDOperand N = getValue(I.getOperand(0)); - MVT::ValueType DestVT = TLI.getValueType(I.getType()); + MVT DestVT = TLI.getValueType(I.getType()); setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N)); } void SelectionDAGLowering::visitUIToFP(User &I) { // UIToFP is never a no-op cast, no need to check SDOperand N = getValue(I.getOperand(0)); - MVT::ValueType DestVT = TLI.getValueType(I.getType()); + MVT DestVT = TLI.getValueType(I.getType()); setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N)); } void SelectionDAGLowering::visitSIToFP(User &I){ // UIToFP is never a no-op cast, no need to check SDOperand N = getValue(I.getOperand(0)); - MVT::ValueType DestVT = TLI.getValueType(I.getType()); + MVT DestVT = TLI.getValueType(I.getType()); setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N)); } @@ -2493,10 +2493,10 @@ // What to do depends on the size of the integer and the size of the pointer. // We can either truncate, zero extend, or no-op, accordingly. SDOperand N = getValue(I.getOperand(0)); - MVT::ValueType SrcVT = N.getValueType(); - MVT::ValueType DestVT = TLI.getValueType(I.getType()); + MVT SrcVT = N.getValueType(); + MVT DestVT = TLI.getValueType(I.getType()); SDOperand Result; - if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT)) + if (DestVT.getSizeInBits() < SrcVT.getSizeInBits()) Result = DAG.getNode(ISD::TRUNCATE, DestVT, N); else // Note: ZERO_EXTEND can handle cases where the sizes are equal too @@ -2508,9 +2508,9 @@ // What to do depends on the size of the integer and the size of the pointer. // We can either truncate, zero extend, or no-op, accordingly. SDOperand N = getValue(I.getOperand(0)); - MVT::ValueType SrcVT = N.getValueType(); - MVT::ValueType DestVT = TLI.getValueType(I.getType()); - if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT)) + MVT SrcVT = N.getValueType(); + MVT DestVT = TLI.getValueType(I.getType()); + if (DestVT.getSizeInBits() < SrcVT.getSizeInBits()) setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); else // Note: ZERO_EXTEND can handle cases where the sizes are equal too @@ -2519,7 +2519,7 @@ void SelectionDAGLowering::visitBitCast(User &I) { SDOperand N = getValue(I.getOperand(0)); - MVT::ValueType DestVT = TLI.getValueType(I.getType()); + MVT DestVT = TLI.getValueType(I.getType()); // BitCast assures us that source and destination are the same size so this // is either a BIT_CONVERT or a no-op. @@ -2640,7 +2640,7 @@ I.getAlignment()); SDOperand AllocSize = getValue(I.getArraySize()); - MVT::ValueType IntPtr = TLI.getPointerTy(); + MVT IntPtr = TLI.getPointerTy(); if (IntPtr < AllocSize.getValueType()) AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize); else if (IntPtr > AllocSize.getValueType()) @@ -2666,7 +2666,7 @@ DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); SDOperand Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; - const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(), + const MVT *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(), MVT::Other); SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3); setValue(&I, DSA); @@ -2746,14 +2746,14 @@ Ops.push_back(Op); } - std::vector VTs; + std::vector VTs; if (I.getType() != Type::VoidTy) { - MVT::ValueType VT = TLI.getValueType(I.getType()); - if (MVT::isVector(VT)) { + MVT VT = TLI.getValueType(I.getType()); + if (VT.isVector()) { const VectorType *DestTy = cast(I.getType()); - MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType()); + MVT EltVT = TLI.getValueType(DestTy->getElementType()); - VT = MVT::getVectorType(EltVT, DestTy->getNumElements()); + VT = MVT::getVectorVT(EltVT, DestTy->getNumElements()); assert(VT != MVT::Other && "Intrinsic uses a non-legal type?"); } @@ -2763,7 +2763,7 @@ if (HasChain) VTs.push_back(MVT::Other); - const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs); + const MVT *VTList = DAG.getNodeValueTypes(VTs); // Create the node. SDOperand Result; @@ -2786,7 +2786,7 @@ } if (I.getType() != Type::VoidTy) { if (const VectorType *PTy = dyn_cast(I.getType())) { - MVT::ValueType VT = TLI.getValueType(PTy); + MVT VT = TLI.getValueType(PTy); Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result); } setValue(&I, Result); @@ -3038,7 +3038,7 @@ case Intrinsic::eh_selector_i32: case Intrinsic::eh_selector_i64: { MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); - MVT::ValueType VT = (Intrinsic == Intrinsic::eh_selector_i32 ? + MVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ? MVT::i32 : MVT::i64); if (MMI) { @@ -3071,7 +3071,7 @@ case Intrinsic::eh_typeid_for_i32: case Intrinsic::eh_typeid_for_i64: { MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); - MVT::ValueType VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ? + MVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ? MVT::i32 : MVT::i64); if (MMI) { @@ -3114,9 +3114,9 @@ } case Intrinsic::eh_dwarf_cfa: { - MVT::ValueType VT = getValue(I.getOperand(1)).getValueType(); + MVT VT = getValue(I.getOperand(1)).getValueType(); SDOperand CfaArg; - if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy())) + if (VT.getSizeInBits() > TLI.getPointerTy().getSizeInBits()) CfaArg = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), getValue(I.getOperand(1))); else @@ -3196,21 +3196,21 @@ return 0; case Intrinsic::cttz: { SDOperand Arg = getValue(I.getOperand(1)); - MVT::ValueType Ty = Arg.getValueType(); + MVT Ty = Arg.getValueType(); SDOperand result = DAG.getNode(ISD::CTTZ, Ty, Arg); setValue(&I, result); return 0; } case Intrinsic::ctlz: { SDOperand Arg = getValue(I.getOperand(1)); - MVT::ValueType Ty = Arg.getValueType(); + MVT Ty = Arg.getValueType(); SDOperand result = DAG.getNode(ISD::CTLZ, Ty, Arg); setValue(&I, result); return 0; } case Intrinsic::ctpop: { SDOperand Arg = getValue(I.getOperand(1)); - MVT::ValueType Ty = Arg.getValueType(); + MVT Ty = Arg.getValueType(); SDOperand result = DAG.getNode(ISD::CTPOP, Ty, Arg); setValue(&I, result); return 0; @@ -3503,9 +3503,9 @@ SmallVector Parts; for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { // Copy the legal parts from the registers. - MVT::ValueType ValueVT = ValueVTs[Value]; + MVT ValueVT = ValueVTs[Value]; unsigned NumRegs = TLI->getNumRegisters(ValueVT); - MVT::ValueType RegisterVT = RegVTs[Value]; + MVT RegisterVT = RegVTs[Value]; Parts.resize(NumRegs); for (unsigned i = 0; i != NumRegs; ++i) { @@ -3543,9 +3543,9 @@ unsigned NumRegs = Regs.size(); SmallVector Parts(NumRegs); for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { - MVT::ValueType ValueVT = ValueVTs[Value]; + MVT ValueVT = ValueVTs[Value]; unsigned NumParts = TLI->getNumRegisters(ValueVT); - MVT::ValueType RegisterVT = RegVTs[Value]; + MVT RegisterVT = RegVTs[Value]; getCopyToParts(DAG, Val.getValue(Val.ResNo + Value), &Parts[Part], NumParts, RegisterVT); @@ -3586,11 +3586,11 @@ /// values added into it. void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, std::vector &Ops) const { - MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy(); + MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy(); Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy)); for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { unsigned NumRegs = TLI->getNumRegisters(ValueVTs[Value]); - MVT::ValueType RegisterVT = RegVTs[Value]; + MVT RegisterVT = RegVTs[Value]; for (unsigned i = 0; i != NumRegs; ++i) Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT)); } @@ -3603,11 +3603,11 @@ isAllocatableRegister(unsigned Reg, MachineFunction &MF, const TargetLowering &TLI, const TargetRegisterInfo *TRI) { - MVT::ValueType FoundVT = MVT::Other; + MVT FoundVT = MVT::Other; const TargetRegisterClass *FoundRC = 0; for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(), E = TRI->regclass_end(); RCI != E; ++RCI) { - MVT::ValueType ThisVT = MVT::Other; + MVT ThisVT = MVT::Other; const TargetRegisterClass *RC = *RCI; // If none of the the value types for this register class are valid, we @@ -3619,7 +3619,7 @@ // choose the one with the largest VT specified. For example, on // PowerPC, we favor f64 register classes over f32. if (FoundVT == MVT::Other || - MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) { + FoundVT.getSizeInBits() < (*I).getSizeInBits()) { ThisVT = *I; break; } @@ -3745,8 +3745,8 @@ unsigned NumRegs = 1; if (OpInfo.ConstraintVT != MVT::Other) NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT); - MVT::ValueType RegVT; - MVT::ValueType ValueVT = OpInfo.ConstraintVT; + MVT RegVT; + MVT ValueVT = OpInfo.ConstraintVT; // If this is a constraint for a specific physical register, like {r17}, @@ -3895,7 +3895,7 @@ ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i])); SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); - MVT::ValueType OpVT = MVT::Other; + MVT OpVT = MVT::Other; // Compute the value type for each operand. switch (OpInfo.Type) { @@ -4227,12 +4227,12 @@ // bit_convert. if (const StructType *ResSTy = dyn_cast(CS.getType())) { for (unsigned i = 0, e = ResSTy->getNumElements(); i != e; ++i) { - if (MVT::isVector(Val.Val->getValueType(i))) + if (Val.Val->getValueType(i).isVector()) Val = DAG.getNode(ISD::BIT_CONVERT, TLI.getValueType(ResSTy->getElementType(i)), Val); } } else { - if (MVT::isVector(Val.getValueType())) + if (Val.getValueType().isVector()) Val = DAG.getNode(ISD::BIT_CONVERT, TLI.getValueType(CS.getType()), Val); } @@ -4267,7 +4267,7 @@ void SelectionDAGLowering::visitMalloc(MallocInst &I) { SDOperand Src = getValue(I.getOperand(0)); - MVT::ValueType IntPtr = TLI.getPointerTy(); + MVT IntPtr = TLI.getPointerTy(); if (IntPtr < Src.getValueType()) Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src); @@ -4298,7 +4298,7 @@ Entry.Node = getValue(I.getOperand(0)); Entry.Ty = TLI.getTargetData()->getIntPtrType(); Args.push_back(Entry); - MVT::ValueType IntPtr = TLI.getPointerTy(); + MVT IntPtr = TLI.getPointerTy(); std::pair Result = TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false, CallingConv::C, true, @@ -4361,11 +4361,11 @@ Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy())); // Add one result value for each formal argument. - std::vector RetVals; + std::vector RetVals; unsigned j = 1; for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I, ++j) { - MVT::ValueType VT = getValueType(I->getType()); + MVT VT = getValueType(I->getType()); ISD::ArgFlagsTy Flags; unsigned OriginalAlignment = getTargetData()->getABITypeAlignment(I->getType()); @@ -4395,7 +4395,7 @@ Flags.setNest(); Flags.setOrigAlign(OriginalAlignment); - MVT::ValueType RegisterVT = getRegisterType(VT); + MVT RegisterVT = getRegisterType(VT); unsigned NumRegs = getNumRegisters(VT); for (unsigned i = 0; i != NumRegs; ++i) { RetVals.push_back(RegisterVT); @@ -4438,8 +4438,8 @@ unsigned Idx = 1; for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I, ++Idx) { - MVT::ValueType VT = getValueType(I->getType()); - MVT::ValueType PartVT = getRegisterType(VT); + MVT VT = getValueType(I->getType()); + MVT PartVT = getRegisterType(VT); unsigned NumParts = getNumRegisters(VT); SmallVector Parts(NumParts); @@ -4479,7 +4479,7 @@ // Handle all of the outgoing arguments. for (unsigned i = 0, e = Args.size(); i != e; ++i) { - MVT::ValueType VT = getValueType(Args[i].Ty); + MVT VT = getValueType(Args[i].Ty); SDOperand Op = Args[i].Node; ISD::ArgFlagsTy Flags; unsigned OriginalAlignment = @@ -4510,7 +4510,7 @@ Flags.setNest(); Flags.setOrigAlign(OriginalAlignment); - MVT::ValueType PartVT = getRegisterType(VT); + MVT PartVT = getRegisterType(VT); unsigned NumParts = getNumRegisters(VT); SmallVector Parts(NumParts); ISD::NodeType ExtendKind = ISD::ANY_EXTEND; @@ -4537,14 +4537,14 @@ // Figure out the result value types. We start by making a list of // the potentially illegal return value types. - SmallVector LoweredRetTys; - SmallVector RetTys; + SmallVector LoweredRetTys; + SmallVector RetTys; ComputeValueVTs(*this, RetTy, RetTys); // Then we translate that to a list of legal types. for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { - MVT::ValueType VT = RetTys[I]; - MVT::ValueType RegisterVT = getRegisterType(VT); + MVT VT = RetTys[I]; + MVT RegisterVT = getRegisterType(VT); unsigned NumRegs = getNumRegisters(VT); for (unsigned i = 0; i != NumRegs; ++i) LoweredRetTys.push_back(RegisterVT); @@ -4571,8 +4571,8 @@ SmallVector ReturnValues; unsigned RegNo = 0; for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { - MVT::ValueType VT = RetTys[I]; - MVT::ValueType RegisterVT = getRegisterType(VT); + MVT VT = RetTys[I]; + MVT RegisterVT = getRegisterType(VT); unsigned NumRegs = getNumRegisters(VT); unsigned RegNoEnd = NumRegs + RegNo; SmallVector Results; @@ -4609,7 +4609,7 @@ // SelectionDAGISel code //===----------------------------------------------------------------------===// -unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) { +unsigned SelectionDAGISel::MakeReg(MVT VT) { return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT)); } @@ -4798,7 +4798,7 @@ MachineFrameInfo *MFI = MF.getFrameInfo(); if (!isByVal && IsPossiblyOverwrittenArgumentOfTailCall(Arg, MFI)) { - MVT::ValueType VT = Arg.getValueType(); + MVT VT = Arg.getValueType(); unsigned VReg = MF.getRegInfo(). createVirtualRegister(TLI.getRegClassFor(VT)); Chain = DAG.getCopyToReg(Chain, VReg, Arg, InFlag); @@ -4951,7 +4951,7 @@ // Remember that this register needs to added to the machine PHI node as // the input for this MBB. - MVT::ValueType VT = TLI.getValueType(PN->getType()); + MVT VT = TLI.getValueType(PN->getType()); unsigned NumRegisters = TLI.getNumRegisters(VT); for (unsigned i = 0, e = NumRegisters; i != e; ++i) PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); @@ -5356,7 +5356,7 @@ } // Add this to the output node. - MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy(); + MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy(); Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3), IntPtrTy)); Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp Fri Jun 6 07:08:01 2008 @@ -48,7 +48,7 @@ template static std::string getEdgeAttributes(const void *Node, EdgeIter EI) { SDOperand Op = EI.getNode()->getOperand(EI.getOperand()); - MVT::ValueType VT = Op.getValueType(); + MVT VT = Op.getValueType(); if (VT == MVT::Flag) return "color=red,style=bold"; else if (VT == MVT::Other) @@ -90,7 +90,7 @@ if (Node->getValueType(i) == MVT::Other) Op += ":ch"; else - Op = Op + ":" + MVT::getValueTypeString(Node->getValueType(i)); + Op = Op + ":" + Node->getValueType(i).getMVTString(); if (const ConstantSDNode *CSDN = dyn_cast(Node)) { Op += ": " + utostr(CSDN->getValue()); @@ -154,7 +154,7 @@ } else if (const ARG_FLAGSSDNode *N = dyn_cast(Node)) { Op = Op + " AF=" + N->getArgFlags().getArgFlagsString(); } else if (const VTSDNode *N = dyn_cast(Node)) { - Op = Op + " VT=" + MVT::getValueTypeString(N->getVT()); + Op = Op + " VT=" + N->getVT().getMVTString(); } else if (const StringSDNode *N = dyn_cast(Node)) { Op = Op + "\"" + N->getValue() + "\""; } else if (const LoadSDNode *LD = dyn_cast(Node)) { @@ -172,7 +172,7 @@ break; } if (doExt) - Op += MVT::getValueTypeString(LD->getMemoryVT()) + ">"; + Op += LD->getMemoryVT().getMVTString() + ">"; if (LD->isVolatile()) Op += ""; Op += LD->getIndexedModeName(LD->getAddressingMode()); @@ -180,7 +180,7 @@ Op += " A=" + utostr(LD->getAlignment()); } else if (const StoreSDNode *ST = dyn_cast(Node)) { if (ST->isTruncatingStore()) - Op += "getMemoryVT()) + ">"; + Op += "getMemoryVT().getMVTString() + ">"; if (ST->isVolatile()) Op += ""; Op += ST->getIndexedModeName(ST->getAddressingMode()); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Fri Jun 6 07:08:01 2008 @@ -180,12 +180,12 @@ // Default all indexed load / store to expand. for (unsigned IM = (unsigned)ISD::PRE_INC; IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { - setIndexedLoadAction(IM, (MVT::ValueType)VT, Expand); - setIndexedStoreAction(IM, (MVT::ValueType)VT, Expand); + setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand); + setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand); } // These operations default to expand. - setOperationAction(ISD::FGETSIGN, (MVT::ValueType)VT, Expand); + setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand); } // Most targets ignore the @llvm.prefetch intrinsic. @@ -244,7 +244,7 @@ // Everything defaults to needing one register. for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { NumRegistersForVT[i] = 1; - RegisterTypeForVT[i] = TransformToType[i] = i; + RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; } // ...except isVoid, which doesn't need any registers. NumRegistersForVT[MVT::isVoid] = 0; @@ -256,24 +256,28 @@ // Every integer value type larger than this largest register takes twice as // many registers to represent as the previous ValueType. - for (MVT::ValueType ExpandedReg = LargestIntReg + 1; - MVT::isInteger(ExpandedReg); ++ExpandedReg) { + for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) { + MVT EVT = (MVT::SimpleValueType)ExpandedReg; + if (!EVT.isInteger()) + break; NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; - RegisterTypeForVT[ExpandedReg] = LargestIntReg; - TransformToType[ExpandedReg] = ExpandedReg - 1; - ValueTypeActions.setTypeAction(ExpandedReg, Expand); + RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; + TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); + ValueTypeActions.setTypeAction(EVT, Expand); } // Inspect all of the ValueType's smaller than the largest integer // register to see which ones need promotion. - MVT::ValueType LegalIntReg = LargestIntReg; - for (MVT::ValueType IntReg = LargestIntReg - 1; - IntReg >= MVT::i1; --IntReg) { - if (isTypeLegal(IntReg)) { + unsigned LegalIntReg = LargestIntReg; + for (unsigned IntReg = LargestIntReg - 1; + IntReg >= (unsigned)MVT::i1; --IntReg) { + MVT IVT = (MVT::SimpleValueType)IntReg; + if (isTypeLegal(IVT)) { LegalIntReg = IntReg; } else { - RegisterTypeForVT[IntReg] = TransformToType[IntReg] = LegalIntReg; - ValueTypeActions.setTypeAction(IntReg, Promote); + RegisterTypeForVT[IntReg] = TransformToType[IntReg] = + (MVT::SimpleValueType)LegalIntReg; + ValueTypeActions.setTypeAction(IVT, Promote); } } @@ -311,18 +315,19 @@ } // Loop over all of the vector value types to see which need transformations. - for (MVT::ValueType i = MVT::FIRST_VECTOR_VALUETYPE; - i <= MVT::LAST_VECTOR_VALUETYPE; ++i) { - if (!isTypeLegal(i)) { - MVT::ValueType IntermediateVT, RegisterVT; + for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; + i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { + MVT VT = (MVT::SimpleValueType)i; + if (!isTypeLegal(VT)) { + MVT IntermediateVT, RegisterVT; unsigned NumIntermediates; NumRegistersForVT[i] = - getVectorTypeBreakdown(i, + getVectorTypeBreakdown(VT, IntermediateVT, NumIntermediates, RegisterVT); RegisterTypeForVT[i] = RegisterVT; TransformToType[i] = MVT::Other; // this isn't actually used - ValueTypeActions.setTypeAction(i, Expand); + ValueTypeActions.setTypeAction(VT, Expand); } } } @@ -332,8 +337,7 @@ } -MVT::ValueType -TargetLowering::getSetCCResultType(const SDOperand &) const { +MVT TargetLowering::getSetCCResultType(const SDOperand &) const { return getValueType(TD->getIntPtrType()); } @@ -347,13 +351,13 @@ /// register. It also returns the VT and quantity of the intermediate values /// before they are promoted/expanded. /// -unsigned TargetLowering::getVectorTypeBreakdown(MVT::ValueType VT, - MVT::ValueType &IntermediateVT, +unsigned TargetLowering::getVectorTypeBreakdown(MVT VT, + MVT &IntermediateVT, unsigned &NumIntermediates, - MVT::ValueType &RegisterVT) const { + MVT &RegisterVT) const { // Figure out the right, legal destination reg to copy into. - unsigned NumElts = MVT::getVectorNumElements(VT); - MVT::ValueType EltTy = MVT::getVectorElementType(VT); + unsigned NumElts = VT.getVectorNumElements(); + MVT EltTy = VT.getVectorElementType(); unsigned NumVectorRegs = 1; @@ -366,24 +370,23 @@ // Divide the input until we get to a supported size. This will always // end with a scalar if the target doesn't support vectors. - while (NumElts > 1 && - !isTypeLegal(MVT::getVectorType(EltTy, NumElts))) { + while (NumElts > 1 && !isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { NumElts >>= 1; NumVectorRegs <<= 1; } NumIntermediates = NumVectorRegs; - MVT::ValueType NewVT = MVT::getVectorType(EltTy, NumElts); + MVT NewVT = MVT::getVectorVT(EltTy, NumElts); if (!isTypeLegal(NewVT)) NewVT = EltTy; IntermediateVT = NewVT; - MVT::ValueType DestVT = getTypeToTransformTo(NewVT); + MVT DestVT = getTypeToTransformTo(NewVT); RegisterVT = DestVT; if (DestVT < NewVT) { // Value is expanded, e.g. i64 -> i16. - return NumVectorRegs*(MVT::getSizeInBits(NewVT)/MVT::getSizeInBits(DestVT)); + return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); } else { // Otherwise, promotion or legal types use the same number of registers as // the vector decimated to the appropriate level. @@ -425,7 +428,7 @@ case ISD::XOR: if (ConstantSDNode *C = dyn_cast(Op.getOperand(1))) if (C->getAPIntValue().intersects(~Demanded)) { - MVT::ValueType VT = Op.getValueType(); + MVT VT = Op.getValueType(); SDOperand New = DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0), DAG.getConstant(Demanded & C->getAPIntValue(), @@ -597,7 +600,7 @@ // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known if ((KnownOne & KnownOne2) == KnownOne) { - MVT::ValueType VT = Op.getValueType(); + MVT VT = Op.getValueType(); SDOperand ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT); return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, VT, Op.getOperand(0), ANDC)); @@ -612,7 +615,7 @@ // if we can expand it to have all bits set, do it if (Expanded.isAllOnesValue()) { if (Expanded != C->getAPIntValue()) { - MVT::ValueType VT = Op.getValueType(); + MVT VT = Op.getValueType(); SDOperand New = TLO.DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0), TLO.DAG.getConstant(Expanded, VT)); return TLO.CombineTo(Op, New); @@ -688,7 +691,7 @@ SDOperand NewSA = TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); - MVT::ValueType VT = Op.getValueType(); + MVT VT = Op.getValueType(); return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT, InOp.getOperand(0), NewSA)); } @@ -705,9 +708,9 @@ break; case ISD::SRL: if (ConstantSDNode *SA = dyn_cast(Op.getOperand(1))) { - MVT::ValueType VT = Op.getValueType(); + MVT VT = Op.getValueType(); unsigned ShAmt = SA->getValue(); - unsigned VTSize = MVT::getSizeInBits(VT); + unsigned VTSize = VT.getSizeInBits(); SDOperand InOp = Op.getOperand(0); // If the shift count is an invalid immediate, don't do anything. @@ -749,7 +752,7 @@ break; case ISD::SRA: if (ConstantSDNode *SA = dyn_cast(Op.getOperand(1))) { - MVT::ValueType VT = Op.getValueType(); + MVT VT = Op.getValueType(); unsigned ShAmt = SA->getValue(); // If the shift count is an invalid immediate, don't do anything. @@ -762,7 +765,7 @@ // demand the input sign bit. APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); if (HighBits.intersects(NewMask)) - InDemandedMask |= APInt::getSignBit(MVT::getSizeInBits(VT)); + InDemandedMask |= APInt::getSignBit(VT.getSizeInBits()); if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, KnownZero, KnownOne, TLO, Depth+1)) @@ -785,22 +788,22 @@ } break; case ISD::SIGN_EXTEND_INREG: { - MVT::ValueType EVT = cast(Op.getOperand(1))->getVT(); + MVT EVT = cast(Op.getOperand(1))->getVT(); // Sign extension. Compute the demanded bits in the result that are not // present in the input. APInt NewBits = APInt::getHighBitsSet(BitWidth, - BitWidth - MVT::getSizeInBits(EVT)) & + BitWidth - EVT.getSizeInBits()) & NewMask; // If none of the extended bits are demanded, eliminate the sextinreg. if (NewBits == 0) return TLO.CombineTo(Op, Op.getOperand(0)); - APInt InSignBit = APInt::getSignBit(MVT::getSizeInBits(EVT)); + APInt InSignBit = APInt::getSignBit(EVT.getSizeInBits()); InSignBit.zext(BitWidth); APInt InputDemandedBits = APInt::getLowBitsSet(BitWidth, - MVT::getSizeInBits(EVT)) & + EVT.getSizeInBits()) & NewMask; // Since the sign extended bits are demanded, we know that the sign @@ -852,8 +855,8 @@ break; } case ISD::SIGN_EXTEND: { - MVT::ValueType InVT = Op.getOperand(0).getValueType(); - unsigned InBits = MVT::getSizeInBits(InVT); + MVT InVT = Op.getOperand(0).getValueType(); + unsigned InBits = InVT.getSizeInBits(); APInt InMask = APInt::getLowBitsSet(BitWidth, InBits); APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits); APInt NewBits = ~InMask & NewMask; @@ -948,9 +951,9 @@ break; } case ISD::AssertZext: { - MVT::ValueType VT = cast(Op.getOperand(1))->getVT(); + MVT VT = cast(Op.getOperand(1))->getVT(); APInt InMask = APInt::getLowBitsSet(BitWidth, - MVT::getSizeInBits(VT)); + VT.getSizeInBits()); if (SimplifyDemandedBits(Op.getOperand(0), InMask & NewMask, KnownZero, KnownOne, TLO, Depth+1)) return true; @@ -962,7 +965,7 @@ #if 0 // If this is an FP->Int bitcast and if the sign bit is the only thing that // is demanded, turn this into a FGETSIGN. - if (NewMask == MVT::getIntVTSignBit(Op.getValueType()) && + if (NewMask == MVT::getIntegerVTSignBit(Op.getValueType()) && MVT::isFloatingPoint(Op.getOperand(0).getValueType()) && !MVT::isVector(Op.getOperand(0).getValueType())) { // Only do this xform if FGETSIGN is valid or if before legalize. @@ -972,7 +975,7 @@ // place. We expect the SHL to be eliminated by other optimizations. SDOperand Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(), Op.getOperand(0)); - unsigned ShVal = MVT::getSizeInBits(Op.getValueType())-1; + unsigned ShVal = Op.getValueType().getSizeInBits()-1; SDOperand ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy()); return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(), Sign, ShAmt)); @@ -1030,7 +1033,7 @@ /// SimplifySetCC - Try to simplify a setcc built with the specified operands /// and cc. If it is unable to simplify it, return a null SDOperand. SDOperand -TargetLowering::SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, +TargetLowering::SimplifySetCC(MVT VT, SDOperand N0, SDOperand N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI) const { SelectionDAG &DAG = DCI.DAG; @@ -1057,7 +1060,7 @@ N0.getOperand(1).getOpcode() == ISD::Constant) { unsigned ShAmt = cast(N0.getOperand(1))->getValue(); if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && - ShAmt == Log2_32(MVT::getSizeInBits(N0.getValueType()))) { + ShAmt == Log2_32(N0.getValueType().getSizeInBits())) { if ((C1 == 0) == (Cond == ISD::SETEQ)) { // (srl (ctlz x), 5) == 0 -> X != 0 // (srl (ctlz x), 5) != 1 -> X != 0 @@ -1075,7 +1078,7 @@ // If the LHS is a ZERO_EXTEND, perform the comparison on the input. if (N0.getOpcode() == ISD::ZERO_EXTEND) { - unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType()); + unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits(); // If the comparison constant has bits in the upper part, the // zero-extended value could never match. @@ -1118,10 +1121,10 @@ } } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { - MVT::ValueType ExtSrcTy = cast(N0.getOperand(1))->getVT(); - unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy); - MVT::ValueType ExtDstTy = N0.getValueType(); - unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy); + MVT ExtSrcTy = cast(N0.getOperand(1))->getVT(); + unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits(); + MVT ExtDstTy = N0.getValueType(); + unsigned ExtDstTyBits = ExtDstTy.getSizeInBits(); // If the extended part has any inconsistent bits, it cannot ever // compare equal. In other words, they have to be all ones or all @@ -1132,7 +1135,7 @@ return DAG.getConstant(Cond == ISD::SETNE, VT); SDOperand ZextOp; - MVT::ValueType Op0Ty = N0.getOperand(0).getValueType(); + MVT Op0Ty = N0.getOperand(0).getValueType(); if (Op0Ty == ExtSrcTy) { ZextOp = N0.getOperand(0); } else { @@ -1161,7 +1164,7 @@ // Invert the condition. ISD::CondCode CC = cast(N0.getOperand(2))->get(); CC = ISD::getSetCCInverse(CC, - MVT::isInteger(N0.getOperand(0).getValueType())); + N0.getOperand(0).getValueType().isInteger()); return DAG.getSetCC(VT, N0.getOperand(0), N0.getOperand(1), CC); } @@ -1196,7 +1199,7 @@ } APInt MinVal, MaxVal; - unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0)); + unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits(); if (ISD::isSignedIntSetCC(Cond)) { MinVal = APInt::getSignedMinValue(OperandBitSize); MaxVal = APInt::getSignedMaxValue(OperandBitSize); @@ -1313,7 +1316,7 @@ if (N0 == N1) { // We can always fold X == X for integer setcc's. - if (MVT::isInteger(N0.getValueType())) + if (N0.getValueType().isInteger()) return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); unsigned UOF = ISD::getUnorderedFlavor(Cond); if (UOF == 2) // FP operators that are undefined on NaNs. @@ -1328,7 +1331,7 @@ } if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && - MVT::isInteger(N0.getValueType())) { + N0.getValueType().isInteger()) { if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || N0.getOpcode() == ISD::XOR) { // Simplify (X+Y) == (X+Z) --> Y == Z @@ -1517,8 +1520,8 @@ const MachineFrameInfo *MFI) const { if (LD->getOperand(0).Val != Base->getOperand(0).Val) return false; - MVT::ValueType VT = LD->getValueType(0); - if (MVT::getSizeInBits(VT) / 8 != Bytes) + MVT VT = LD->getValueType(0); + if (VT.getSizeInBits() / 8 != Bytes) return false; SDOperand Loc = LD->getOperand(1); @@ -1593,10 +1596,10 @@ /// LowerXConstraint - try to replace an X constraint, which matches anything, /// with another that has more specific requirements based on the type of the /// corresponding operand. -const char *TargetLowering::LowerXConstraint(MVT::ValueType ConstraintVT) const{ - if (MVT::isInteger(ConstraintVT)) +const char *TargetLowering::LowerXConstraint(MVT ConstraintVT) const{ + if (ConstraintVT.isInteger()) return "r"; - if (MVT::isFloatingPoint(ConstraintVT)) + if (ConstraintVT.isFloatingPoint()) return "f"; // works for many targets return 0; } @@ -1661,14 +1664,14 @@ std::vector TargetLowering:: getRegClassForInlineAsmConstraint(const std::string &Constraint, - MVT::ValueType VT) const { + MVT VT) const { return std::vector(); } std::pair TargetLowering:: getRegForInlineAsmConstraint(const std::string &Constraint, - MVT::ValueType VT) const { + MVT VT) const { if (Constraint[0] != '{') return std::pair(0, 0); assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); @@ -2039,7 +2042,7 @@ /// SDOperand TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, std::vector* Created) const { - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // Check to see if we can do this. if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) @@ -2080,7 +2083,7 @@ } // Extract the sign bit and add it to the quotient SDOperand T = - DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(MVT::getSizeInBits(VT)-1, + DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(VT.getSizeInBits()-1, getShiftAmountTy())); if (Created) Created->push_back(T.Val); @@ -2093,7 +2096,7 @@ /// SDOperand TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, std::vector* Created) const { - MVT::ValueType VT = N->getValueType(0); + MVT VT = N->getValueType(0); // Check to see if we can do this. if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Fri Jun 6 07:08:01 2008 @@ -660,7 +660,7 @@ case ISD::LOAD: { LoadSDNode *LD = cast(Op); ISD::MemIndexedMode AM = LD->getAddressingMode(); - MVT::ValueType LoadedVT = LD->getMemoryVT(); + MVT LoadedVT = LD->getMemoryVT(); if (AM != ISD::UNINDEXED) { SDOperand Offset, AMOpc; bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); @@ -741,7 +741,7 @@ } case ARMISD::CMOV: { bool isThumb = Subtarget->isThumb(); - MVT::ValueType VT = Op.getValueType(); + MVT VT = Op.getValueType(); SDOperand N0 = Op.getOperand(0); SDOperand N1 = Op.getOperand(1); SDOperand N2 = Op.getOperand(2); @@ -805,7 +805,7 @@ cast(N2)->getValue()), MVT::i32); SDOperand Ops[] = { N0, N1, Tmp2, N3, InFlag }; unsigned Opc = 0; - switch (VT) { + switch (VT.getSimpleVT()) { default: assert(false && "Illegal conditional move type!"); break; case MVT::i32: @@ -821,7 +821,7 @@ return CurDAG->SelectNodeTo(Op.Val, Opc, VT, Ops, 5); } case ARMISD::CNEG: { - MVT::ValueType VT = Op.getValueType(); + MVT VT = Op.getValueType(); SDOperand N0 = Op.getOperand(0); SDOperand N1 = Op.getOperand(1); SDOperand N2 = Op.getOperand(2); @@ -837,7 +837,7 @@ cast(N2)->getValue()), MVT::i32); SDOperand Ops[] = { N0, N1, Tmp2, N3, InFlag }; unsigned Opc = 0; - switch (VT) { + switch (VT.getSimpleVT()) { default: assert(false && "Illegal conditional move type!"); break; case MVT::f32: Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Fri Jun 6 07:08:01 2008 @@ -363,7 +363,7 @@ } static void -HowToPassArgument(MVT::ValueType ObjectVT, unsigned NumGPRs, +HowToPassArgument(MVT ObjectVT, unsigned NumGPRs, unsigned StackOffset, unsigned &NeededGPRs, unsigned &NeededStackSize, unsigned &GPRPad, unsigned &StackPad, ISD::ArgFlagsTy Flags) { @@ -375,7 +375,7 @@ GPRPad = NumGPRs % ((align + 3)/4); StackPad = StackOffset % align; unsigned firstGPR = NumGPRs + GPRPad; - switch (ObjectVT) { + switch (ObjectVT.getSimpleVT()) { default: assert(0 && "Unhandled argument type!"); case MVT::i32: case MVT::f32: @@ -400,7 +400,7 @@ /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter /// nodes. SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) { - MVT::ValueType RetVT= Op.Val->getValueType(0); + MVT RetVT= Op.Val->getValueType(0); SDOperand Chain = Op.getOperand(0); unsigned CallConv = cast(Op.getOperand(1))->getValue(); assert((CallConv == CallingConv::C || @@ -419,7 +419,7 @@ unsigned ObjGPRs; unsigned StackPad; unsigned GPRPad; - MVT::ValueType ObjectVT = Op.getOperand(5+2*i).getValueType(); + MVT ObjectVT = Op.getOperand(5+2*i).getValueType(); ISD::ArgFlagsTy Flags = cast(Op.getOperand(5+2*i+1))->getArgFlags(); HowToPassArgument(ObjectVT, NumGPRs, NumBytes, ObjGPRs, ObjSize, @@ -446,7 +446,7 @@ SDOperand Arg = Op.getOperand(5+2*i); ISD::ArgFlagsTy Flags = cast(Op.getOperand(5+2*i+1))->getArgFlags(); - MVT::ValueType ArgVT = Arg.getValueType(); + MVT ArgVT = Arg.getValueType(); unsigned ObjSize; unsigned ObjGPRs; @@ -457,7 +457,7 @@ NumGPRs += GPRPad; ArgOffset += StackPad; if (ObjGPRs > 0) { - switch (ArgVT) { + switch (ArgVT.getSimpleVT()) { default: assert(0 && "Unexpected ValueType for argument!"); case MVT::i32: RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Arg)); @@ -587,7 +587,7 @@ InFlag = Chain.getValue(1); } - std::vector NodeTys; + std::vector NodeTys; NodeTys.push_back(MVT::Other); // Returns a chain NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. @@ -617,7 +617,7 @@ NodeTys.clear(); // If the call has results, copy the values out of the ret val registers. - switch (RetVT) { + switch (RetVT.getSimpleVT()) { default: assert(0 && "Unexpected ret value!"); case MVT::Other: break; @@ -708,7 +708,7 @@ // be used to form addressing mode. These wrapped nodes will be selected // into MOVi. static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) { - MVT::ValueType PtrVT = Op.getValueType(); + MVT PtrVT = Op.getValueType(); ConstantPoolSDNode *CP = cast(Op); SDOperand Res; if (CP->isMachineConstantPoolEntry()) @@ -724,7 +724,7 @@ SDOperand ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) { - MVT::ValueType PtrVT = getPointerTy(); + MVT PtrVT = getPointerTy(); unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue, @@ -758,7 +758,7 @@ GlobalValue *GV = GA->getGlobal(); SDOperand Offset; SDOperand Chain = DAG.getEntryNode(); - MVT::ValueType PtrVT = getPointerTy(); + MVT PtrVT = getPointerTy(); // Get the Thread Pointer SDOperand ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, PtrVT); @@ -807,7 +807,7 @@ SDOperand ARMTargetLowering::LowerGlobalAddressELF(SDOperand Op, SelectionDAG &DAG) { - MVT::ValueType PtrVT = getPointerTy(); + MVT PtrVT = getPointerTy(); GlobalValue *GV = cast(Op)->getGlobal(); Reloc::Model RelocM = getTargetMachine().getRelocationModel(); if (RelocM == Reloc::PIC_) { @@ -840,7 +840,7 @@ SDOperand ARMTargetLowering::LowerGlobalAddressDarwin(SDOperand Op, SelectionDAG &DAG) { - MVT::ValueType PtrVT = getPointerTy(); + MVT PtrVT = getPointerTy(); GlobalValue *GV = cast(Op)->getGlobal(); Reloc::Model RelocM = getTargetMachine().getRelocationModel(); bool IsIndirect = GVIsIndirectSymbol(GV, RelocM); @@ -875,7 +875,7 @@ SelectionDAG &DAG){ assert(Subtarget->isTargetELF() && "GLOBAL OFFSET TABLE not implemented for non-ELF targets"); - MVT::ValueType PtrVT = getPointerTy(); + MVT PtrVT = getPointerTy(); unsigned PCAdj = Subtarget->isThumb() ? 4 : 8; ARMConstantPoolValue *CPV = new ARMConstantPoolValue("_GLOBAL_OFFSET_TABLE_", ARMPCLabelIndex, @@ -888,7 +888,7 @@ } static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) { - MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); unsigned IntNo = cast(Op.getOperand(0))->getValue(); switch (IntNo) { default: return SDOperand(); // Don't custom lower most intrinsics. @@ -901,7 +901,7 @@ unsigned VarArgsFrameIndex) { // vastart just stores the address of the VarArgsFrameIndex slot into the // memory location argument. - MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); const Value *SV = cast(Op.getOperand(2))->getValue(); return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0); @@ -911,7 +911,7 @@ unsigned ArgNo, unsigned &NumGPRs, unsigned &ArgOffset) { MachineFunction &MF = DAG.getMachineFunction(); - MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType(); + MVT ObjectVT = Op.getValue(ArgNo).getValueType(); SDOperand Root = Op.getOperand(0); std::vector ArgValues; MachineRegisterInfo &RegInfo = MF.getRegInfo(); @@ -1025,7 +1025,7 @@ ArgValues.push_back(Root); // Return the new list of results. - std::vector RetVT(Op.Val->value_begin(), + std::vector RetVT(Op.Val->value_begin(), Op.Val->value_end()); return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size()); } @@ -1123,7 +1123,7 @@ static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG, const ARMSubtarget *ST) { - MVT::ValueType VT = Op.getValueType(); + MVT VT = Op.getValueType(); SDOperand LHS = Op.getOperand(0); SDOperand RHS = Op.getOperand(1); ISD::CondCode CC = cast(Op.getOperand(4))->get(); @@ -1195,7 +1195,7 @@ SDOperand Table = Op.getOperand(1); SDOperand Index = Op.getOperand(2); - MVT::ValueType PTy = getPointerTy(); + MVT PTy = getPointerTy(); JumpTableSDNode *JT = cast(Table); ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo(); SDOperand UId = DAG.getConstant(AFI->createJumpTableUId(), PTy); @@ -1204,7 +1204,7 @@ Index = DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(4, PTy)); SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table); bool isPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; - Addr = DAG.getLoad(isPIC ? (MVT::ValueType)MVT::i32 : PTy, + Addr = DAG.getLoad(isPIC ? (MVT)MVT::i32 : PTy, Chain, Addr, NULL, 0); Chain = Addr.getValue(1); if (isPIC) @@ -1220,7 +1220,7 @@ } static SDOperand LowerINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { - MVT::ValueType VT = Op.getValueType(); + MVT VT = Op.getValueType(); unsigned Opc = Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF; @@ -1232,8 +1232,8 @@ // Implement fcopysign with a fabs and a conditional fneg. SDOperand Tmp0 = Op.getOperand(0); SDOperand Tmp1 = Op.getOperand(1); - MVT::ValueType VT = Op.getValueType(); - MVT::ValueType SrcVT = Tmp1.getValueType(); + MVT VT = Op.getValueType(); + MVT SrcVT = Tmp1.getValueType(); SDOperand AbsVal = DAG.getNode(ISD::FABS, VT, Tmp0); SDOperand Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG); SDOperand ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32); @@ -1265,7 +1265,7 @@ unsigned BytesLeft = SizeVal & 3; unsigned NumMemOps = SizeVal >> 2; unsigned EmittedNumMemOps = 0; - MVT::ValueType VT = MVT::i32; + MVT VT = MVT::i32; unsigned VTSize = 4; unsigned i = 0; const unsigned MAX_LOADS_IN_LDM = 6; @@ -1536,7 +1536,7 @@ /// isLegalAddressImmediate - Return true if the integer value can be used /// as the offset of the target addressing mode for load / store of the /// given type. -static bool isLegalAddressImmediate(int64_t V, MVT::ValueType VT, +static bool isLegalAddressImmediate(int64_t V, MVT VT, const ARMSubtarget *Subtarget) { if (V == 0) return true; @@ -1546,7 +1546,7 @@ return false; unsigned Scale = 1; - switch (VT) { + switch (VT.getSimpleVT()) { default: return false; case MVT::i1: case MVT::i8: @@ -1570,7 +1570,7 @@ if (V < 0) V = - V; - switch (VT) { + switch (VT.getSimpleVT()) { default: return false; case MVT::i1: case MVT::i8: @@ -1615,7 +1615,7 @@ return false; int Scale = AM.Scale; - switch (getValueType(Ty)) { + switch (getValueType(Ty).getSimpleVT()) { default: return false; case MVT::i1: case MVT::i8: @@ -1650,7 +1650,7 @@ } -static bool getIndexedAddressParts(SDNode *Ptr, MVT::ValueType VT, +static bool getIndexedAddressParts(SDNode *Ptr, MVT VT, bool isSEXTLoad, SDOperand &Base, SDOperand &Offset, bool &isInc, SelectionDAG &DAG) { @@ -1717,7 +1717,7 @@ if (Subtarget->isThumb()) return false; - MVT::ValueType VT; + MVT VT; SDOperand Ptr; bool isSEXTLoad = false; if (LoadSDNode *LD = dyn_cast(N)) { @@ -1751,7 +1751,7 @@ if (Subtarget->isThumb()) return false; - MVT::ValueType VT; + MVT VT; SDOperand Ptr; bool isSEXTLoad = false; if (LoadSDNode *LD = dyn_cast(N)) { @@ -1816,7 +1816,7 @@ std::pair ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, - MVT::ValueType VT) const { + MVT VT) const { if (Constraint.size() == 1) { // GCC RS6000 Constraint Letters switch (Constraint[0]) { @@ -1838,7 +1838,7 @@ std::vector ARMTargetLowering:: getRegClassForInlineAsmConstraint(const std::string &Constraint, - MVT::ValueType VT) const { + MVT VT) const { if (Constraint.size() != 1) return std::vector(); Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Fri Jun 6 07:08:01 2008 @@ -114,10 +114,10 @@ ConstraintType getConstraintType(const std::string &Constraint) const; std::pair getRegForInlineAsmConstraint(const std::string &Constraint, - MVT::ValueType VT) const; + MVT VT) const; std::vector getRegClassForInlineAsmConstraint(const std::string &Constraint, - MVT::ValueType VT) const; + MVT VT) const; virtual const ARMSubtarget* getSubtarget() { return Subtarget; Modified: llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp Fri Jun 6 07:08:01 2008 @@ -334,7 +334,7 @@ case ISD::TargetConstantFP: { ConstantFPSDNode *CN = cast(N); bool isDouble = N->getValueType(0) == MVT::f64; - MVT::ValueType T = isDouble ? MVT::f64 : MVT::f32; + MVT T = isDouble ? MVT::f64 : MVT::f32; if (CN->getValueAPF().isPosZero()) { return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS, T, CurDAG->getRegister(Alpha::F31, T), @@ -350,7 +350,7 @@ } case ISD::SETCC: - if (MVT::isFloatingPoint(N->getOperand(0).Val->getValueType(0))) { + if (N->getOperand(0).Val->getValueType(0).isFloatingPoint()) { ISD::CondCode CC = cast(N->getOperand(2))->get(); unsigned Opc = Alpha::WTF; @@ -404,9 +404,9 @@ break; case ISD::SELECT: - if (MVT::isFloatingPoint(N->getValueType(0)) && + if (N->getValueType(0).isFloatingPoint() && (N->getOperand(0).getOpcode() != ISD::SETCC || - !MVT::isFloatingPoint(N->getOperand(0).getOperand(1).getValueType()))) { + !N->getOperand(0).getOperand(1).getValueType().isFloatingPoint())) { //This should be the condition not covered by the Patterns //FIXME: Don't have SelectCode die, but rather return something testable // so that things like this can be caught in fall though code @@ -472,7 +472,7 @@ AddToISelQueue(Chain); std::vector CallOperands; - std::vector TypeOperands; + std::vector TypeOperands; //grab the arguments for(int i = 2, e = N->getNumOperands(); i < e; ++i) { @@ -489,7 +489,7 @@ for (int i = 6; i < count; ++i) { unsigned Opc = Alpha::WTF; - if (MVT::isInteger(TypeOperands[i])) { + if (TypeOperands[i].isInteger()) { Opc = Alpha::STQ; } else if (TypeOperands[i] == MVT::f32) { Opc = Alpha::STS; @@ -504,7 +504,7 @@ Chain = SDOperand(CurDAG->getTargetNode(Opc, MVT::Other, Ops, 4), 0); } for (int i = 0; i < std::min(6, count); ++i) { - if (MVT::isInteger(TypeOperands[i])) { + if (TypeOperands[i].isInteger()) { Chain = CurDAG->getCopyToReg(Chain, args_int[i], CallOperands[i], InFlag); InFlag = Chain.getValue(1); } else if (TypeOperands[i] == MVT::f32 || TypeOperands[i] == MVT::f64) { @@ -533,7 +533,7 @@ std::vector CallResults; - switch (N->getValueType(0)) { + switch (N->getValueType(0).getSimpleVT()) { default: assert(0 && "Unexpected ret value!"); case MVT::Other: break; case MVT::i64: Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp Fri Jun 6 07:08:01 2008 @@ -145,8 +145,7 @@ computeRegisterProperties(); } -MVT::ValueType -AlphaTargetLowering::getSetCCResultType(const SDOperand &) const { +MVT AlphaTargetLowering::getSetCCResultType(const SDOperand &) const { return MVT::i64; } @@ -169,7 +168,7 @@ } static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) { - MVT::ValueType PtrVT = Op.getValueType(); + MVT PtrVT = Op.getValueType(); JumpTableSDNode *JT = cast(Op); SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); SDOperand Zero = DAG.getConstant(0, PtrVT); @@ -217,14 +216,13 @@ for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) { SDOperand argt; - MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType(); + MVT ObjectVT = Op.getValue(ArgNo).getValueType(); SDOperand ArgVal; if (ArgNo < 6) { - switch (ObjectVT) { + switch (ObjectVT.getSimpleVT()) { default: - cerr << "Unknown Type " << ObjectVT << "\n"; - abort(); + assert(false && "Invalid value type!"); case MVT::f64: args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo], &Alpha::F8RCRegClass); @@ -282,7 +280,7 @@ ArgValues.push_back(Root); // Return the new list of results. - std::vector RetVT(Op.Val->value_begin(), + std::vector RetVT(Op.Val->value_begin(), Op.Val->value_end()); return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size()); } @@ -300,12 +298,12 @@ break; //return SDOperand(); // ret void is legal case 3: { - MVT::ValueType ArgVT = Op.getOperand(1).getValueType(); + MVT ArgVT = Op.getOperand(1).getValueType(); unsigned ArgReg; - if (MVT::isInteger(ArgVT)) + if (ArgVT.isInteger()) ArgReg = Alpha::R0; else { - assert(MVT::isFloatingPoint(ArgVT)); + assert(ArgVT.isFloatingPoint()); ArgReg = Alpha::F0; } Copy = DAG.getCopyToReg(Copy, ArgReg, Op.getOperand(1), Copy.getValue(1)); @@ -332,7 +330,7 @@ std::vector args_to_use; for (unsigned i = 0, e = Args.size(); i != e; ++i) { - switch (getValueType(Args[i].Ty)) { + switch (getValueType(Args[i].Ty).getSimpleVT()) { default: assert(0 && "Unexpected ValueType for argument!"); case MVT::i1: case MVT::i8: @@ -355,9 +353,9 @@ args_to_use.push_back(Args[i].Node); } - std::vector RetVals; - MVT::ValueType RetTyVT = getValueType(RetTy); - MVT::ValueType ActualRetTyVT = RetTyVT; + std::vector RetVals; + MVT RetTyVT = getValueType(RetTy); + MVT ActualRetTyVT = RetTyVT; if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i32) ActualRetTyVT = MVT::i64; @@ -407,17 +405,17 @@ case ISD::JumpTable: return LowerJumpTable(Op, DAG); case ISD::SINT_TO_FP: { - assert(MVT::i64 == Op.getOperand(0).getValueType() && + assert(Op.getOperand(0).getValueType() == MVT::i64 && "Unhandled SINT_TO_FP type in custom expander!"); SDOperand LD; - bool isDouble = MVT::f64 == Op.getValueType(); + bool isDouble = Op.getValueType() == MVT::f64; LD = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0)); SDOperand FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_, isDouble?MVT::f64:MVT::f32, LD); return FP; } case ISD::FP_TO_SINT: { - bool isDouble = MVT::f64 == Op.getOperand(0).getValueType(); + bool isDouble = Op.getOperand(0).getValueType() == MVT::f64; SDOperand src = Op.getOperand(0); if (!isDouble) //Promote @@ -465,7 +463,7 @@ case ISD::SREM: //Expand only on constant case if (Op.getOperand(1).getOpcode() == ISD::Constant) { - MVT::ValueType VT = Op.Val->getValueType(0); + MVT VT = Op.Val->getValueType(0); SDOperand Tmp1 = Op.Val->getOpcode() == ISD::UREM ? BuildUDIV(Op.Val, DAG, NULL) : BuildSDIV(Op.Val, DAG, NULL); @@ -476,7 +474,7 @@ //fall through case ISD::SDIV: case ISD::UDIV: - if (MVT::isInteger(Op.getValueType())) { + if (Op.getValueType().isInteger()) { if (Op.getOperand(1).getOpcode() == ISD::Constant) return Op.getOpcode() == ISD::SDIV ? BuildSDIV(Op.Val, DAG, NULL) : BuildUDIV(Op.Val, DAG, NULL); @@ -505,7 +503,7 @@ SDOperand Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1), Tmp, NULL, 0, MVT::i32); SDOperand DataPtr = DAG.getNode(ISD::ADD, MVT::i64, Base, Offset); - if (MVT::isFloatingPoint(Op.getValueType())) + if (Op.getValueType().isFloatingPoint()) { //if fp && Offset < 6*8, then subtract 6*8 from DataPtr SDOperand FPDataPtr = DAG.getNode(ISD::SUB, MVT::i64, DataPtr, @@ -596,7 +594,7 @@ std::vector AlphaTargetLowering:: getRegClassForInlineAsmConstraint(const std::string &Constraint, - MVT::ValueType VT) const { + MVT VT) const { if (Constraint.size() == 1) { switch (Constraint[0]) { default: break; // Unknown constriant letter Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelLowering.h?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaISelLowering.h (original) +++ llvm/trunk/lib/Target/Alpha/AlphaISelLowering.h Fri Jun 6 07:08:01 2008 @@ -67,7 +67,7 @@ explicit AlphaTargetLowering(TargetMachine &TM); /// getSetCCResultType - Get the SETCC result ValueType - virtual MVT::ValueType getSetCCResultType(const SDOperand &) const; + virtual MVT getSetCCResultType(const SDOperand &) const; /// LowerOperation - Provide custom lowering hooks for some operations. /// @@ -88,7 +88,7 @@ std::vector getRegClassForInlineAsmConstraint(const std::string &Constraint, - MVT::ValueType VT) const; + MVT VT) const; bool hasITOF() { return useITOF; } Modified: llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp Fri Jun 6 07:08:01 2008 @@ -110,7 +110,7 @@ bool isIntS16Immediate(ConstantSDNode *CN, short &Imm) { - MVT::ValueType vt = CN->getValueType(0); + MVT vt = CN->getValueType(0); Imm = (short) CN->getValue(); if (vt >= MVT::i1 && vt <= MVT::i16) { return true; @@ -139,7 +139,7 @@ static bool isFPS16Immediate(ConstantFPSDNode *FPN, short &Imm) { - MVT::ValueType vt = FPN->getValueType(0); + MVT vt = FPN->getValueType(0); if (vt == MVT::f32) { int val = FloatToBits(FPN->getValueAPF().convertToFloat()); int sval = (int) ((val << 16) >> 16); @@ -161,10 +161,10 @@ } //===------------------------------------------------------------------===// - //! MVT::ValueType to "useful stuff" mapping structure: + //! MVT to "useful stuff" mapping structure: struct valtype_map_s { - MVT::ValueType VT; + MVT VT; unsigned ldresult_ins; /// LDRESULT instruction (0 = undefined) bool ldresult_imm; /// LDRESULT instruction requires immediate? int prefslot_byte; /// Byte offset of the "preferred" slot @@ -189,7 +189,7 @@ const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]); - const valtype_map_s *getValueTypeMapEntry(MVT::ValueType VT) + const valtype_map_s *getValueTypeMapEntry(MVT VT) { const valtype_map_s *retval = 0; for (size_t i = 0; i < n_valtype_map; ++i) { @@ -203,7 +203,7 @@ #ifndef NDEBUG if (retval == 0) { cerr << "SPUISelDAGToDAG.cpp: getValueTypeMapEntry returns NULL for " - << MVT::getValueTypeString(VT) + << VT.getMVTString() << "\n"; abort(); } @@ -364,7 +364,7 @@ SPUDAGToDAGISel::SelectAFormAddr(SDOperand Op, SDOperand N, SDOperand &Base, SDOperand &Index) { // These match the addr256k operand type: - MVT::ValueType OffsVT = MVT::i16; + MVT OffsVT = MVT::i16; SDOperand Zero = CurDAG->getTargetConstant(0, OffsVT); switch (N.getOpcode()) { @@ -446,7 +446,7 @@ SDOperand &Index, int minOffset, int maxOffset) { unsigned Opc = N.getOpcode(); - unsigned PtrTy = SPUtli.getPointerTy(); + MVT PtrTy = SPUtli.getPointerTy(); if (Opc == ISD::FrameIndex) { // Stack frame index must be less than 512 (divided by 16): @@ -587,7 +587,7 @@ unsigned Opc = N->getOpcode(); int n_ops = -1; unsigned NewOpc; - MVT::ValueType OpVT = Op.getValueType(); + MVT OpVT = Op.getValueType(); SDOperand Ops[8]; if (Opc >= ISD::BUILTIN_OP_END && Opc < SPUISD::FIRST_NUMBER) { @@ -596,7 +596,7 @@ // Selects to (add $sp, FI * stackSlotSize) int FI = SPUFrameInfo::FItoStackOffset(cast(N)->getIndex()); - MVT::ValueType PtrVT = SPUtli.getPointerTy(); + MVT PtrVT = SPUtli.getPointerTy(); // Adjust stack slot to actual offset in frame: if (isS10Constant(FI)) { @@ -636,7 +636,7 @@ } } else if (Opc == SPUISD::LDRESULT) { // Custom select instructions for LDRESULT - unsigned VT = N->getValueType(0); + MVT VT = N->getValueType(0); SDOperand Arg = N->getOperand(0); SDOperand Chain = N->getOperand(1); SDNode *Result; @@ -644,7 +644,7 @@ if (vtm->ldresult_ins == 0) { cerr << "LDRESULT for unsupported type: " - << MVT::getValueTypeString(VT) + << VT.getMVTString() << "\n"; abort(); } @@ -670,7 +670,7 @@ /* || Op0.getOpcode() == SPUISD::AFormAddr) */ // (IndirectAddr (LDRESULT, imm)) SDOperand Op1 = Op.getOperand(1); - MVT::ValueType VT = Op.getValueType(); + MVT VT = Op.getValueType(); DEBUG(cerr << "CellSPU: IndirectAddr(LDRESULT, imm):\nOp0 = "); DEBUG(Op.getOperand(0).Val->dump(CurDAG)); Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Fri Jun 6 07:08:01 2008 @@ -38,9 +38,9 @@ namespace { std::map node_names; - //! MVT::ValueType mapping to useful data for Cell SPU + //! MVT mapping to useful data for Cell SPU struct valtype_map_s { - const MVT::ValueType valtype; + const MVT valtype; const int prefslot_byte; }; @@ -57,7 +57,7 @@ const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]); - const valtype_map_s *getValueTypeMapEntry(MVT::ValueType VT) { + const valtype_map_s *getValueTypeMapEntry(MVT VT) { const valtype_map_s *retval = 0; for (size_t i = 0; i < n_valtype_map; ++i) { @@ -70,7 +70,7 @@ #ifndef NDEBUG if (retval == 0) { cerr << "getValueTypeMapEntry returns NULL for " - << MVT::getValueTypeString(VT) + << VT.getMVTString() << "\n"; abort(); } @@ -162,8 +162,10 @@ // SPU's loads and stores have to be custom lowered: for (unsigned sctype = (unsigned) MVT::i1; sctype < (unsigned) MVT::f128; ++sctype) { - setOperationAction(ISD::LOAD, sctype, Custom); - setOperationAction(ISD::STORE, sctype, Custom); + MVT VT = (MVT::SimpleValueType)sctype; + + setOperationAction(ISD::LOAD, VT, Custom); + setOperationAction(ISD::STORE, VT, Custom); } // Custom lower BRCOND for i1, i8 to "promote" the result to @@ -296,9 +298,11 @@ // appropriate instructions to materialize the address. for (unsigned sctype = (unsigned) MVT::i1; sctype < (unsigned) MVT::f128; ++sctype) { - setOperationAction(ISD::GlobalAddress, sctype, Custom); - setOperationAction(ISD::ConstantPool, sctype, Custom); - setOperationAction(ISD::JumpTable, sctype, Custom); + MVT VT = (MVT::SimpleValueType)sctype; + + setOperationAction(ISD::GlobalAddress, VT, Custom); + setOperationAction(ISD::ConstantPool, VT, Custom); + setOperationAction(ISD::JumpTable, VT, Custom); } // RET must be custom lowered, to meet ABI requirements @@ -335,36 +339,38 @@ addRegisterClass(MVT::v4f32, SPU::VECREGRegisterClass); addRegisterClass(MVT::v2f64, SPU::VECREGRegisterClass); - for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; - VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { + for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; + i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { + MVT VT = (MVT::SimpleValueType)i; + // add/sub are legal for all supported vector VT's. - setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal); - setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal); + setOperationAction(ISD::ADD , VT, Legal); + setOperationAction(ISD::SUB , VT, Legal); // mul has to be custom lowered. - setOperationAction(ISD::MUL , (MVT::ValueType)VT, Custom); + setOperationAction(ISD::MUL , VT, Custom); - setOperationAction(ISD::AND , (MVT::ValueType)VT, Legal); - setOperationAction(ISD::OR , (MVT::ValueType)VT, Legal); - setOperationAction(ISD::XOR , (MVT::ValueType)VT, Legal); - setOperationAction(ISD::LOAD , (MVT::ValueType)VT, Legal); - setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Legal); - setOperationAction(ISD::STORE, (MVT::ValueType)VT, Legal); + setOperationAction(ISD::AND , VT, Legal); + setOperationAction(ISD::OR , VT, Legal); + setOperationAction(ISD::XOR , VT, Legal); + setOperationAction(ISD::LOAD , VT, Legal); + setOperationAction(ISD::SELECT, VT, Legal); + setOperationAction(ISD::STORE, VT, Legal); // These operations need to be expanded: - setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Custom); + setOperationAction(ISD::SDIV, VT, Expand); + setOperationAction(ISD::SREM, VT, Expand); + setOperationAction(ISD::UDIV, VT, Expand); + setOperationAction(ISD::UREM, VT, Expand); + setOperationAction(ISD::FDIV, VT, Custom); // Custom lower build_vector, constant pool spills, insert and // extract vector elements: - setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Custom); - setOperationAction(ISD::ConstantPool, (MVT::ValueType)VT, Custom); - setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Custom); - setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Custom); - setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Custom); - setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Custom); + setOperationAction(ISD::BUILD_VECTOR, VT, Custom); + setOperationAction(ISD::ConstantPool, VT, Custom); + setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom); + setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); + setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); + setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); } setOperationAction(ISD::MUL, MVT::v16i8, Custom); @@ -447,10 +453,9 @@ return ((i != node_names.end()) ? i->second : 0); } -MVT::ValueType -SPUTargetLowering::getSetCCResultType(const SDOperand &Op) const { - MVT::ValueType VT = Op.getValueType(); - if (MVT::isInteger(VT)) +MVT SPUTargetLowering::getSetCCResultType(const SDOperand &Op) const { + MVT VT = Op.getValueType(); + if (VT.isInteger()) return VT; else return MVT::i32; @@ -490,9 +495,9 @@ AlignedLoad(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST, LSBaseSDNode *LSN, unsigned &alignment, int &alignOffs, int &prefSlotOffs, - MVT::ValueType &VT, bool &was16aligned) + MVT &VT, bool &was16aligned) { - MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); const valtype_map_s *vtm = getValueTypeMapEntry(VT); SDOperand basePtr = LSN->getBasePtr(); SDOperand chain = LSN->getChain(); @@ -573,8 +578,8 @@ LowerLOAD(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) { LoadSDNode *LN = cast(Op); SDOperand the_chain = LN->getChain(); - MVT::ValueType VT = LN->getMemoryVT(); - MVT::ValueType OpVT = Op.Val->getValueType(0); + MVT VT = LN->getMemoryVT(); + MVT OpVT = Op.Val->getValueType(0); ISD::LoadExtType ExtType = LN->getExtensionType(); unsigned alignment = LN->getAlignment(); SDOperand Ops[8]; @@ -601,7 +606,7 @@ if (was16aligned) { Ops[2] = DAG.getConstant(rotamt, MVT::i16); } else { - MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); LoadSDNode *LN1 = cast(result); Ops[2] = DAG.getNode(ISD::ADD, PtrVT, LN1->getBasePtr(), DAG.getConstant(rotamt, PtrVT)); @@ -613,15 +618,15 @@ if (VT == OpVT || ExtType == ISD::EXTLOAD) { SDVTList scalarvts; - MVT::ValueType vecVT = MVT::v16i8; + MVT vecVT = MVT::v16i8; // Convert the loaded v16i8 vector to the appropriate vector type // specified by the operand: if (OpVT == VT) { if (VT != MVT::i1) - vecVT = MVT::getVectorType(VT, (128 / MVT::getSizeInBits(VT))); + vecVT = MVT::getVectorVT(VT, (128 / VT.getSizeInBits())); } else - vecVT = MVT::getVectorType(OpVT, (128 / MVT::getSizeInBits(OpVT))); + vecVT = MVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits())); Ops[0] = the_chain; Ops[1] = DAG.getNode(ISD::BIT_CONVERT, vecVT, result); @@ -681,9 +686,9 @@ LowerSTORE(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) { StoreSDNode *SN = cast(Op); SDOperand Value = SN->getValue(); - MVT::ValueType VT = Value.getValueType(); - MVT::ValueType StVT = (!SN->isTruncatingStore() ? VT : SN->getMemoryVT()); - MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + MVT VT = Value.getValueType(); + MVT StVT = (!SN->isTruncatingStore() ? VT : SN->getMemoryVT()); + MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); unsigned alignment = SN->getAlignment(); switch (SN->getAddressingMode()) { @@ -693,11 +698,11 @@ // The vector type we really want to load from the 16-byte chunk, except // in the case of MVT::i1, which has to be v16i8. - unsigned vecVT, stVecVT = MVT::v16i8; + MVT vecVT, stVecVT = MVT::v16i8; if (StVT != MVT::i1) - stVecVT = MVT::getVectorType(StVT, (128 / MVT::getSizeInBits(StVT))); - vecVT = MVT::getVectorType(VT, (128 / MVT::getSizeInBits(VT))); + stVecVT = MVT::getVectorVT(StVT, (128 / StVT.getSizeInBits())); + vecVT = MVT::getVectorVT(VT, (128 / VT.getSizeInBits())); SDOperand alignLoadVec = AlignedLoad(Op, DAG, ST, SN, alignment, @@ -773,7 +778,7 @@ /// Generate the address of a constant pool entry. static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) { - MVT::ValueType PtrVT = Op.getValueType(); + MVT PtrVT = Op.getValueType(); ConstantPoolSDNode *CP = cast(Op); Constant *C = CP->getConstVal(); SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment()); @@ -798,7 +803,7 @@ static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) { - MVT::ValueType PtrVT = Op.getValueType(); + MVT PtrVT = Op.getValueType(); JumpTableSDNode *JT = cast(Op); SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); SDOperand Zero = DAG.getConstant(0, PtrVT); @@ -821,7 +826,7 @@ static SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) { - MVT::ValueType PtrVT = Op.getValueType(); + MVT PtrVT = Op.getValueType(); GlobalAddressSDNode *GSDN = cast(Op); GlobalValue *GV = GSDN->getGlobal(); SDOperand GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset()); @@ -853,7 +858,7 @@ */ static SDOperand LowerConstant(SDOperand Op, SelectionDAG &DAG) { - unsigned VT = Op.getValueType(); + MVT VT = Op.getValueType(); ConstantSDNode *CN = cast(Op.Val); if (VT == MVT::i64) { @@ -862,7 +867,7 @@ DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i64, T, T)); } else { cerr << "LowerConstant: unhandled constant type " - << MVT::getValueTypeString(VT) + << VT.getMVTString() << "\n"; abort(); /*NOTREACHED*/ @@ -874,7 +879,7 @@ //! Custom lower double precision floating point constants static SDOperand LowerConstantFP(SDOperand Op, SelectionDAG &DAG) { - unsigned VT = Op.getValueType(); + MVT VT = Op.getValueType(); ConstantFPSDNode *FP = cast(Op.Val); assert((FP != 0) && @@ -894,8 +899,8 @@ LowerBRCOND(SDOperand Op, SelectionDAG &DAG) { SDOperand Cond = Op.getOperand(1); - MVT::ValueType CondVT = Cond.getValueType(); - MVT::ValueType CondNVT; + MVT CondVT = Cond.getValueType(); + MVT CondNVT; if (CondVT == MVT::i1 || CondVT == MVT::i8) { CondNVT = (CondVT == MVT::i1 ? MVT::i32 : MVT::i16); @@ -924,19 +929,19 @@ unsigned ArgRegIdx = 0; unsigned StackSlotSize = SPUFrameInfo::stackSlotSize(); - MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); // Add DAG nodes to load the arguments or copy them out of registers. for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) { SDOperand ArgVal; bool needsLoad = false; - MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType(); - unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8; + MVT ObjectVT = Op.getValue(ArgNo).getValueType(); + unsigned ObjSize = ObjectVT.getSizeInBits()/8; - switch (ObjectVT) { + switch (ObjectVT.getSimpleVT()) { default: { cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: " - << MVT::getValueTypeString(ObjectVT) + << ObjectVT.getMVTString() << "\n"; abort(); } @@ -1032,7 +1037,7 @@ // If the function takes variable number of arguments, make a frame index for // the start of the first vararg value... for expansion of llvm.va_start. if (isVarArg) { - VarArgsFrameIndex = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8, + VarArgsFrameIndex = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8, ArgOffset); SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); // If this function is vararg, store any remaining integer argument regs to @@ -1046,7 +1051,7 @@ SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); MemOps.push_back(Store); // Increment the address by four for the next argument to store - SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT); + SDOperand PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT); FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); } if (!MemOps.empty()) @@ -1056,7 +1061,7 @@ ArgValues.push_back(Root); // Return the new list of results. - std::vector RetVT(Op.Val->value_begin(), + std::vector RetVT(Op.Val->value_begin(), Op.Val->value_end()); return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size()); } @@ -1090,7 +1095,7 @@ const unsigned NumArgRegs = SPURegisterInfo::getNumArgRegs(); // Handy pointer type - MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); // Accumulate how many bytes are to be pushed on the stack, including the // linkage area, and parameter passing area. According to the SPU ABI, @@ -1120,7 +1125,7 @@ SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff); - switch (Arg.getValueType()) { + switch (Arg.getValueType().getSimpleVT()) { default: assert(0 && "Unexpected ValueType for argument!"); case MVT::i32: case MVT::i64: @@ -1174,7 +1179,7 @@ InFlag = Chain.getValue(1); } - std::vector NodeTys; + std::vector NodeTys; NodeTys.push_back(MVT::Other); // Returns a chain NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. @@ -1186,7 +1191,7 @@ // node so that legalize doesn't hack it. if (GlobalAddressSDNode *G = dyn_cast(Callee)) { GlobalValue *GV = G->getGlobal(); - unsigned CalleeVT = Callee.getValueType(); + MVT CalleeVT = Callee.getValueType(); SDOperand Zero = DAG.getConstant(0, PtrVT); SDOperand GA = DAG.getTargetGlobalAddress(GV, CalleeVT); @@ -1243,7 +1248,7 @@ NodeTys.clear(); // If the call has results, copy the values out of the ret val registers. - switch (Op.Val->getValueType(0)) { + switch (Op.Val->getValueType(0).getSimpleVT()) { default: assert(0 && "Unexpected ret value!"); case MVT::Other: break; case MVT::i32: @@ -1365,7 +1370,7 @@ /// and the value fits into an unsigned 18-bit constant, and if so, return the /// constant SDOperand SPU::get_vec_u18imm(SDNode *N, SelectionDAG &DAG, - MVT::ValueType ValueType) { + MVT ValueType) { if (ConstantSDNode *CN = getVecImm(N)) { uint64_t Value = CN->getValue(); if (ValueType == MVT::i64) { @@ -1387,7 +1392,7 @@ /// and the value fits into a signed 16-bit constant, and if so, return the /// constant SDOperand SPU::get_vec_i16imm(SDNode *N, SelectionDAG &DAG, - MVT::ValueType ValueType) { + MVT ValueType) { if (ConstantSDNode *CN = getVecImm(N)) { int64_t Value = CN->getSignExtended(); if (ValueType == MVT::i64) { @@ -1410,7 +1415,7 @@ /// and the value fits into a signed 10-bit constant, and if so, return the /// constant SDOperand SPU::get_vec_i10imm(SDNode *N, SelectionDAG &DAG, - MVT::ValueType ValueType) { + MVT ValueType) { if (ConstantSDNode *CN = getVecImm(N)) { int64_t Value = CN->getSignExtended(); if (ValueType == MVT::i64) { @@ -1436,7 +1441,7 @@ /// constant vectors. Thus, we test to see if the upper and lower bytes are the /// same value. SDOperand SPU::get_vec_i8imm(SDNode *N, SelectionDAG &DAG, - MVT::ValueType ValueType) { + MVT ValueType) { if (ConstantSDNode *CN = getVecImm(N)) { int Value = (int) CN->getValue(); if (ValueType == MVT::i16 @@ -1455,7 +1460,7 @@ /// and the value fits into a signed 16-bit constant, and if so, return the /// constant SDOperand SPU::get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG, - MVT::ValueType ValueType) { + MVT ValueType) { if (ConstantSDNode *CN = getVecImm(N)) { uint64_t Value = CN->getValue(); if ((ValueType == MVT::i32 @@ -1495,7 +1500,7 @@ // Start with zero'd results. VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0; - unsigned EltBitSize = MVT::getSizeInBits(BV->getOperand(0).getValueType()); + unsigned EltBitSize = BV->getOperand(0).getValueType().getSizeInBits(); for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { SDOperand OpVal = BV->getOperand(i); @@ -1597,7 +1602,7 @@ // this case more efficiently than a constant pool load, lower it to the // sequence of ops that should be used. static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) { - MVT::ValueType VT = Op.getValueType(); + MVT VT = Op.getValueType(); // If this is a vector of constants or undefs, get the bits. A bit in // UndefBits is set if the corresponding element of the vector is an // ISD::UNDEF value. For undefs, the corresponding VectorBits values are @@ -1608,11 +1613,11 @@ int SplatSize; if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits) || !isConstantSplat(VectorBits, UndefBits, - MVT::getSizeInBits(MVT::getVectorElementType(VT)), + VT.getVectorElementType().getSizeInBits(), SplatBits, SplatUndef, SplatSize)) return SDOperand(); // Not a constant vector, not a splat. - switch (VT) { + switch (VT.getSimpleVT()) { default: case MVT::v4f32: { uint32_t Value32 = SplatBits; @@ -1649,14 +1654,14 @@ Value16 = (unsigned short) (SplatBits & 0xffff); else Value16 = (unsigned short) (SplatBits | (SplatBits << 8)); - SDOperand T = DAG.getConstant(Value16, MVT::getVectorElementType(VT)); + SDOperand T = DAG.getConstant(Value16, VT.getVectorElementType()); SDOperand Ops[8]; for (int i = 0; i < 8; ++i) Ops[i] = T; return DAG.getNode(ISD::BUILD_VECTOR, VT, Ops, 8); } case MVT::v4i32: { unsigned int Value = SplatBits; - SDOperand T = DAG.getConstant(Value, MVT::getVectorElementType(VT)); + SDOperand T = DAG.getConstant(Value, VT.getVectorElementType()); return DAG.getNode(ISD::BUILD_VECTOR, VT, T, T, T, T); } case MVT::v2i64: { @@ -1772,7 +1777,7 @@ // If we have a single element being moved from V1 to V2, this can be handled // using the C*[DX] compute mask instructions, but the vector elements have // to be monotonically increasing with one exception element. - MVT::ValueType EltVT = MVT::getVectorElementType(V1.getValueType()); + MVT EltVT = V1.getValueType().getVectorElementType(); unsigned EltsFromV2 = 0; unsigned V2Elt = 0; unsigned V2EltIdx0 = 0; @@ -1811,7 +1816,7 @@ MachineFunction &MF = DAG.getMachineFunction(); MachineRegisterInfo &RegInfo = MF.getRegInfo(); unsigned VReg = RegInfo.createVirtualRegister(&SPU::R32CRegClass); - MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); // Initialize temporary register to 0 SDOperand InitTempReg = DAG.getCopyToReg(DAG.getEntryNode(), VReg, DAG.getConstant(0, PtrVT)); @@ -1824,7 +1829,7 @@ return DAG.getNode(SPUISD::SHUFB, V1.getValueType(), V2, V1, ShufMaskOp); } else { // Convert the SHUFFLE_VECTOR mask's input element units to the actual bytes. - unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8; + unsigned BytesPerElement = EltVT.getSizeInBits()/8; SmallVector ResultMask; for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) { @@ -1855,11 +1860,11 @@ ConstantSDNode *CN = cast(Op0.Val); SmallVector ConstVecValues; - MVT::ValueType VT; + MVT VT; size_t n_copies; // Create a constant vector: - switch (Op.getValueType()) { + switch (Op.getValueType().getSimpleVT()) { default: assert(0 && "Unexpected constant value type in " "LowerSCALAR_TO_VECTOR"); case MVT::v16i8: n_copies = 16; VT = MVT::i8; break; @@ -1878,7 +1883,7 @@ &ConstVecValues[0], ConstVecValues.size()); } else { // Otherwise, copy the value from one register to another: - switch (Op0.getValueType()) { + switch (Op0.getValueType().getSimpleVT()) { default: assert(0 && "Unexpected value type in LowerSCALAR_TO_VECTOR"); case MVT::i8: case MVT::i16: @@ -1894,7 +1899,14 @@ } static SDOperand LowerVectorMUL(SDOperand Op, SelectionDAG &DAG) { - switch (Op.getValueType()) { + switch (Op.getValueType().getSimpleVT()) { + default: + cerr << "CellSPU: Unknown vector multiplication, got " + << Op.getValueType().getMVTString() + << "\n"; + abort(); + /*NOTREACHED*/ + case MVT::v4i32: { SDOperand rA = Op.getOperand(0); SDOperand rB = Op.getOperand(1); @@ -2020,13 +2032,6 @@ DAG.getNode(ISD::OR, MVT::v4i32, LoProd, HiProd)); } - - default: - cerr << "CellSPU: Unknown vector multiplication, got " - << MVT::getValueTypeString(Op.getValueType()) - << "\n"; - abort(); - /*NOTREACHED*/ } return SDOperand(); @@ -2038,7 +2043,7 @@ SDOperand A = Op.getOperand(0); SDOperand B = Op.getOperand(1); - unsigned VT = Op.getValueType(); + MVT VT = Op.getValueType(); unsigned VRegBR, VRegC; @@ -2077,7 +2082,7 @@ } static SDOperand LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) { - unsigned VT = Op.getValueType(); + MVT VT = Op.getValueType(); SDOperand N = Op.getOperand(0); SDOperand Elt = Op.getOperand(1); SDOperand ShufMask[16]; @@ -2104,9 +2109,11 @@ // Need to generate shuffle mask and extract: int prefslot_begin = -1, prefslot_end = -1; - int elt_byte = EltNo * MVT::getSizeInBits(VT) / 8; + int elt_byte = EltNo * VT.getSizeInBits() / 8; - switch (VT) { + switch (VT.getSimpleVT()) { + default: + assert(false && "Invalid value type!"); case MVT::i8: { prefslot_begin = prefslot_end = 3; break; @@ -2159,12 +2166,12 @@ SDOperand VecOp = Op.getOperand(0); SDOperand ValOp = Op.getOperand(1); SDOperand IdxOp = Op.getOperand(2); - MVT::ValueType VT = Op.getValueType(); + MVT VT = Op.getValueType(); ConstantSDNode *CN = cast(IdxOp); assert(CN != 0 && "LowerINSERT_VECTOR_ELT: Index is not constant!"); - MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); // Use $2 because it's always 16-byte aligned and it's available: SDOperand PtrBase = DAG.getRegister(SPU::R2, PtrVT); @@ -2270,9 +2277,8 @@ static SDOperand LowerI64Math(SDOperand Op, SelectionDAG &DAG, unsigned Opc) { - MVT::ValueType VT = Op.getValueType(); - unsigned VecVT = - MVT::getVectorType(VT, (128 / MVT::getSizeInBits(VT))); + MVT VT = Op.getValueType(); + MVT VecVT = MVT::getVectorVT(VT, (128 / VT.getSizeInBits())); SDOperand Op0 = Op.getOperand(0); @@ -2280,9 +2286,8 @@ case ISD::ZERO_EXTEND: case ISD::SIGN_EXTEND: case ISD::ANY_EXTEND: { - MVT::ValueType Op0VT = Op0.getValueType(); - unsigned Op0VecVT = - MVT::getVectorType(Op0VT, (128 / MVT::getSizeInBits(Op0VT))); + MVT Op0VT = Op0.getValueType(); + MVT Op0VecVT = MVT::getVectorVT(Op0VT, (128 / Op0VT.getSizeInBits())); assert(Op0VT == MVT::i32 && "CellSPU: Zero/sign extending something other than i32"); @@ -2361,7 +2366,7 @@ case ISD::SHL: { SDOperand ShiftAmt = Op.getOperand(1); - unsigned ShiftAmtVT = unsigned(ShiftAmt.getValueType()); + MVT ShiftAmtVT = ShiftAmt.getValueType(); SDOperand Op0Vec = DAG.getNode(SPUISD::PROMOTE_SCALAR, VecVT, Op0); SDOperand MaskLower = DAG.getNode(SPUISD::SELB, VecVT, @@ -2386,9 +2391,9 @@ } case ISD::SRL: { - unsigned VT = unsigned(Op.getValueType()); + MVT VT = Op.getValueType(); SDOperand ShiftAmt = Op.getOperand(1); - unsigned ShiftAmtVT = unsigned(ShiftAmt.getValueType()); + MVT ShiftAmtVT = ShiftAmt.getValueType(); SDOperand ShiftAmtBytes = DAG.getNode(ISD::SRL, ShiftAmtVT, ShiftAmt, @@ -2409,7 +2414,7 @@ SDOperand Op0 = DAG.getNode(SPUISD::PROMOTE_SCALAR, MVT::v2i64, Op.getOperand(0)); SDOperand ShiftAmt = Op.getOperand(1); - unsigned ShiftVT = ShiftAmt.getValueType(); + MVT ShiftVT = ShiftAmt.getValueType(); // Negate variable shift amounts if (!isa(ShiftAmt)) { @@ -2450,7 +2455,7 @@ LowerByteImmed(SDOperand Op, SelectionDAG &DAG) { SDOperand ConstVec; SDOperand Arg; - MVT::ValueType VT = Op.getValueType(); + MVT VT = Op.getValueType(); ConstVec = Op.getOperand(0); Arg = Op.getOperand(1); @@ -2474,7 +2479,7 @@ if (!GetConstantBuildVectorBits(ConstVec.Val, VectorBits, UndefBits) && isConstantSplat(VectorBits, UndefBits, - MVT::getSizeInBits(MVT::getVectorElementType(VT)), + VT.getVectorElementType().getSizeInBits(), SplatBits, SplatUndef, SplatSize)) { SDOperand tcVec[16]; SDOperand tc = DAG.getTargetConstant(SplatBits & 0xff, MVT::i8); @@ -2493,12 +2498,12 @@ } //! Lower i32 multiplication -static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG, unsigned VT, +static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG, MVT VT, unsigned Opc) { - switch (VT) { + switch (VT.getSimpleVT()) { default: cerr << "CellSPU: Unknown LowerMUL value type, got " - << MVT::getValueTypeString(Op.getValueType()) + << Op.getValueType().getMVTString() << "\n"; abort(); /*NOTREACHED*/ @@ -2525,10 +2530,12 @@ ones per byte, which then have to be accumulated. */ static SDOperand LowerCTPOP(SDOperand Op, SelectionDAG &DAG) { - unsigned VT = Op.getValueType(); - unsigned vecVT = MVT::getVectorType(VT, (128 / MVT::getSizeInBits(VT))); + MVT VT = Op.getValueType(); + MVT vecVT = MVT::getVectorVT(VT, (128 / VT.getSizeInBits())); - switch (VT) { + switch (VT.getSimpleVT()) { + default: + assert(false && "Invalid value type!"); case MVT::i8: { SDOperand N = Op.getOperand(0); SDOperand Elt0 = DAG.getConstant(0, MVT::i32); @@ -2630,7 +2637,7 @@ SPUTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { unsigned Opc = (unsigned) Op.getOpcode(); - unsigned VT = (unsigned) Op.getValueType(); + MVT VT = Op.getValueType(); switch (Opc) { default: { @@ -2704,7 +2711,7 @@ // Vector and i8 multiply: case ISD::MUL: - if (MVT::isVector(VT)) + if (VT.isVector()) return LowerVectorMUL(Op, DAG); else if (VT == MVT::i8) return LowerI8Math(Op, DAG, Opc); @@ -2911,7 +2918,7 @@ std::pair SPUTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, - MVT::ValueType VT) const + MVT VT) const { if (Constraint.size() == 1) { // GCC RS6000 Constraint Letters @@ -2961,9 +2968,9 @@ case SPUISD::PROMOTE_SCALAR: { SDOperand Op0 = Op.getOperand(0); - MVT::ValueType Op0VT = Op0.getValueType(); - unsigned Op0VTBits = MVT::getSizeInBits(Op0VT); - uint64_t InMask = MVT::getIntVTBitMask(Op0VT); + MVT Op0VT = Op0.getValueType(); + unsigned Op0VTBits = Op0VT.getSizeInBits(); + uint64_t InMask = Op0VT.getIntegerVTBitMask(); KnownZero |= APInt(Op0VTBits, ~InMask, false); KnownOne |= APInt(Op0VTBits, InMask, false); break; @@ -2972,9 +2979,9 @@ case SPUISD::LDRESULT: case SPUISD::EXTRACT_ELT0: case SPUISD::EXTRACT_ELT0_CHAINED: { - MVT::ValueType OpVT = Op.getValueType(); - unsigned OpVTBits = MVT::getSizeInBits(OpVT); - uint64_t InMask = MVT::getIntVTBitMask(OpVT); + MVT OpVT = Op.getValueType(); + unsigned OpVTBits = OpVT.getSizeInBits(); + uint64_t InMask = OpVT.getIntegerVTBitMask(); KnownZero |= APInt(OpVTBits, ~InMask, false); KnownOne |= APInt(OpVTBits, InMask, false); break; Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h (original) +++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h Fri Jun 6 07:08:01 2008 @@ -79,15 +79,15 @@ /// Predicates that are used for node matching: namespace SPU { SDOperand get_vec_u18imm(SDNode *N, SelectionDAG &DAG, - MVT::ValueType ValueType); + MVT ValueType); SDOperand get_vec_i16imm(SDNode *N, SelectionDAG &DAG, - MVT::ValueType ValueType); + MVT ValueType); SDOperand get_vec_i10imm(SDNode *N, SelectionDAG &DAG, - MVT::ValueType ValueType); + MVT ValueType); SDOperand get_vec_i8imm(SDNode *N, SelectionDAG &DAG, - MVT::ValueType ValueType); + MVT ValueType); SDOperand get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG, - MVT::ValueType ValueType); + MVT ValueType); SDOperand get_v4i32_imm(SDNode *N, SelectionDAG &DAG); SDOperand get_v2i64_imm(SDNode *N, SelectionDAG &DAG); } @@ -109,7 +109,7 @@ virtual const char *getTargetNodeName(unsigned Opcode) const; /// getSetCCResultType - Return the ValueType for ISD::SETCC - virtual MVT::ValueType getSetCCResultType(const SDOperand &) const; + virtual MVT getSetCCResultType(const SDOperand &) const; /// LowerOperation - Provide custom lowering hooks for some operations. /// @@ -128,7 +128,7 @@ std::pair getRegForInlineAsmConstraint(const std::string &Constraint, - MVT::ValueType VT) const; + MVT VT) const; void LowerAsmOperandForConstraint(SDOperand Op, char ConstraintLetter, std::vector &Ops, Modified: llvm/trunk/lib/Target/IA64/IA64ISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64ISelDAGToDAG.cpp?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/lib/Target/IA64/IA64ISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/IA64/IA64ISelDAGToDAG.cpp Fri Jun 6 07:08:01 2008 @@ -119,7 +119,7 @@ bool isFP=false; - if(MVT::isFloatingPoint(Tmp1.getValueType())) + if(Tmp1.getValueType().isFloatingPoint()) isFP=true; bool isModulus=false; // is it a division or a modulus? @@ -469,9 +469,9 @@ AddToISelQueue(Chain); AddToISelQueue(Address); - MVT::ValueType TypeBeingLoaded = LD->getMemoryVT(); + MVT TypeBeingLoaded = LD->getMemoryVT(); unsigned Opc; - switch (TypeBeingLoaded) { + switch (TypeBeingLoaded.getSimpleVT()) { default: #ifndef NDEBUG N->dump(CurDAG); @@ -511,7 +511,7 @@ unsigned Opc; if (ISD::isNON_TRUNCStore(N)) { - switch (N->getOperand(1).getValueType()) { + switch (N->getOperand(1).getValueType().getSimpleVT()) { default: assert(0 && "unknown type in store"); case MVT::i1: { // this is a bool Opc = IA64::ST1; // we store either 0 or 1 as a byte @@ -531,7 +531,7 @@ case MVT::f64: Opc = IA64::STF8; break; } } else { // Truncating store - switch(ST->getMemoryVT()) { + switch(ST->getMemoryVT().getSimpleVT()) { default: assert(0 && "unknown type in truncstore"); case MVT::i8: Opc = IA64::ST1; break; case MVT::i16: Opc = IA64::ST2; break; Modified: llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp Fri Jun 6 07:08:01 2008 @@ -139,8 +139,7 @@ } } -MVT::ValueType -IA64TargetLowering::getSetCCResultType(const SDOperand &) const { +MVT IA64TargetLowering::getSetCCResultType(const SDOperand &) const { return MVT::i1; } @@ -181,7 +180,7 @@ SDOperand newroot, argt; if(count < 8) { // need to fix this logic? maybe. - switch (getValueType(I->getType())) { + switch (getValueType(I->getType()).getSimpleVT()) { default: assert(0 && "ERROR in LowerArgs: can't lower this type of arg.\n"); case MVT::f32: @@ -286,7 +285,7 @@ // Finally, inform the code generator which regs we return values in. // (see the ISD::RET: case in the instruction selector) - switch (getValueType(F.getReturnType())) { + switch (getValueType(F.getReturnType()).getSimpleVT()) { default: assert(0 && "i have no idea where to return this type!"); case MVT::isVoid: break; case MVT::i1: @@ -347,10 +346,10 @@ for (unsigned i = 0, e = Args.size(); i != e; ++i) { SDOperand Val = Args[i].Node; - MVT::ValueType ObjectVT = Val.getValueType(); + MVT ObjectVT = Val.getValueType(); SDOperand ValToStore(0, 0), ValToConvert(0, 0); unsigned ObjSize=8; - switch (ObjectVT) { + switch (ObjectVT.getSimpleVT()) { default: assert(0 && "unexpected argument type!"); case MVT::i1: case MVT::i8: @@ -442,7 +441,7 @@ // flagged for now, but shouldn't have to be (TODO) unsigned seenConverts = 0; for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) { - if(MVT::isFloatingPoint(RegValuesToPass[i].getValueType())) { + if(RegValuesToPass[i].getValueType().isFloatingPoint()) { Chain = DAG.getCopyToReg(Chain, IntArgRegs[i], Converts[seenConverts++], InFlag); InFlag = Chain.getValue(1); @@ -453,7 +452,7 @@ unsigned usedFPArgs = 0; for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) { Chain = DAG.getCopyToReg(Chain, - MVT::isInteger(RegValuesToPass[i].getValueType()) ? + RegValuesToPass[i].getValueType().isInteger() ? IntArgRegs[i] : FPArgRegs[usedFPArgs++], RegValuesToPass[i], InFlag); InFlag = Chain.getValue(1); } @@ -466,7 +465,7 @@ } */ - std::vector NodeTys; + std::vector NodeTys; std::vector CallOperands; NodeTys.push_back(MVT::Other); // Returns a chain NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. @@ -492,14 +491,14 @@ Chain = DAG.getCopyToReg(Chain, IA64::rp, RPBeforeCall, InFlag); InFlag = Chain.getValue(1); - std::vector RetVals; + std::vector RetVals; RetVals.push_back(MVT::Other); RetVals.push_back(MVT::Flag); - MVT::ValueType RetTyVT = getValueType(RetTy); + MVT RetTyVT = getValueType(RetTy); SDOperand RetVal; if (RetTyVT != MVT::isVoid) { - switch (RetTyVT) { + switch (RetTyVT.getSimpleVT()) { default: assert(0 && "Unknown value type to return!"); case MVT::i1: { // bools are just like other integers (returned in r8) // we *could* fall through to the truncate below, but this saves a @@ -573,8 +572,8 @@ return DAG.getNode(IA64ISD::RET_FLAG, MVT::Other, AR_PFSVal); case 3: { // Copy the result into the output register & restore ar.pfs - MVT::ValueType ArgVT = Op.getOperand(1).getValueType(); - unsigned ArgReg = MVT::isInteger(ArgVT) ? IA64::r8 : IA64::F8; + MVT ArgVT = Op.getOperand(1).getValueType(); + unsigned ArgReg = ArgVT.isInteger() ? IA64::r8 : IA64::F8; AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), VirtGPR, MVT::i64); Copy = DAG.getCopyToReg(AR_PFSVal.getValue(1), ArgReg, Op.getOperand(1), @@ -588,13 +587,13 @@ return SDOperand(); } case ISD::VAARG: { - MVT::ValueType VT = getPointerTy(); + MVT VT = getPointerTy(); const Value *SV = cast(Op.getOperand(2))->getValue(); SDOperand VAList = DAG.getLoad(VT, Op.getOperand(0), Op.getOperand(1), SV, 0); // Increment the pointer, VAList, to the next vaarg SDOperand VAIncr = DAG.getNode(ISD::ADD, VT, VAList, - DAG.getConstant(MVT::getSizeInBits(VT)/8, + DAG.getConstant(VT.getSizeInBits()/8, VT)); // Store the incremented VAList to the legalized pointer VAIncr = DAG.getStore(VAList.getValue(1), VAIncr, Modified: llvm/trunk/lib/Target/IA64/IA64ISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64ISelLowering.h?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/lib/Target/IA64/IA64ISelLowering.h (original) +++ llvm/trunk/lib/Target/IA64/IA64ISelLowering.h Fri Jun 6 07:08:01 2008 @@ -49,7 +49,7 @@ const char *getTargetNodeName(unsigned Opcode) const; /// getSetCCResultType: return ISD::SETCC's result type. - virtual MVT::ValueType getSetCCResultType(const SDOperand &) const; + virtual MVT getSetCCResultType(const SDOperand &) const; /// LowerArguments - This hook must be implemented to indicate how we should /// lower the arguments for the specified function, into the specified DAG. Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Fri Jun 6 07:08:01 2008 @@ -250,7 +250,7 @@ AddToISelQueue(LHS); AddToISelQueue(RHS); - MVT::ValueType VT = LHS.getValueType(); + MVT VT = LHS.getValueType(); SDNode *Carry = CurDAG->getTargetNode(Mips::SLTu, VT, Ops, 2); SDNode *AddCarry = CurDAG->getTargetNode(Mips::ADDu, VT, SDOperand(Carry,0), RHS); Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Fri Jun 6 07:08:01 2008 @@ -108,8 +108,7 @@ } -MVT::ValueType -MipsTargetLowering::getSetCCResultType(const SDOperand &) const { +MVT MipsTargetLowering::getSetCCResultType(const SDOperand &) const { return MVT::i32; } @@ -223,7 +222,7 @@ SDOperand HiPart; if (!isPIC) { - const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::i32); + const MVT *VTs = DAG.getNodeValueTypes(MVT::i32); SDOperand Ops[] = { GA }; HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1); } else // Emit Load from Global Pointer @@ -256,7 +255,7 @@ SDOperand False = Op.getOperand(3); SDOperand CC = Op.getOperand(4); - const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::i32); + const MVT *VTs = DAG.getNodeValueTypes(MVT::i32); SDOperand Ops[] = { LHS, RHS, CC }; SDOperand SetCCRes = DAG.getNode(ISD::SETCC, VTs, 1, Ops, 3); @@ -270,12 +269,12 @@ SDOperand ResNode; SDOperand HiPart; - MVT::ValueType PtrVT = Op.getValueType(); + MVT PtrVT = Op.getValueType(); JumpTableSDNode *JT = cast(Op); SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { - const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::i32); + const MVT *VTs = DAG.getNodeValueTypes(MVT::i32); SDOperand Ops[] = { JTI }; HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1); } else // Emit Load from Global Pointer @@ -341,7 +340,7 @@ // To meet ABI, Mips must always allocate 16 bytes on // the stack (even if less than 4 are used as arguments) - int VTsize = MVT::getSizeInBits(MVT::i32)/8; + int VTsize = MVT(MVT::i32).getSizeInBits()/8; MFI->CreateFixedObject(VTsize, (VTsize*3)); CCInfo.AnalyzeCallOperands(Op.Val, CC_Mips); @@ -391,7 +390,7 @@ // This guarantees that when allocating Local Area the firsts // 16 bytes which are alwayes reserved won't be overwritten. LastStackLoc = (16 + VA.getLocMemOffset()); - int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8, + int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8, LastStackLoc); SDOperand PtrOff = DAG.getFrameIndex(FI,getPointerTy()); @@ -575,7 +574,7 @@ // Arguments stored on registers if (VA.isRegLoc()) { - MVT::ValueType RegVT = VA.getLocVT(); + MVT RegVT = VA.getLocVT(); TargetRegisterClass *RC; if (RegVT == MVT::i32) @@ -738,8 +737,7 @@ } std::pair MipsTargetLowering:: -getRegForInlineAsmConstraint(const std::string &Constraint, - MVT::ValueType VT) const +getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const { if (Constraint.size() == 1) { switch (Constraint[0]) { @@ -753,7 +751,7 @@ std::vector MipsTargetLowering:: getRegClassForInlineAsmConstraint(const std::string &Constraint, - MVT::ValueType VT) const + MVT VT) const { if (Constraint.size() != 1) return std::vector(); Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.h?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.h (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.h Fri Jun 6 07:08:01 2008 @@ -66,7 +66,7 @@ virtual const char *getTargetNodeName(unsigned Opcode) const; /// getSetCCResultType - get the ISD::SETCC result ValueType - MVT::ValueType getSetCCResultType(const SDOperand &) const; + MVT getSetCCResultType(const SDOperand &) const; private: // Lower Operand helpers @@ -93,11 +93,11 @@ std::pair getRegForInlineAsmConstraint(const std::string &Constraint, - MVT::ValueType VT) const; + MVT VT) const; std::vector getRegClassForInlineAsmConstraint(const std::string &Constraint, - MVT::ValueType VT) const; + MVT VT) const; }; } Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp Fri Jun 6 07:08:01 2008 @@ -204,7 +204,7 @@ SDOperand PIC16TargetLowering::LowerBR_CC(SDOperand Op, SelectionDAG &DAG) { - MVT::ValueType VT = Op.getValueType(); + MVT VT = Op.getValueType(); SDOperand Chain = Op.getOperand(0); ISD::CondCode CC = cast(Op.getOperand(1))->get(); SDOperand LHS = Op.getOperand(2); @@ -278,7 +278,7 @@ SDOperand PIC16TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) { - MVT::ValueType PtrVT = getPointerTy(); + MVT PtrVT = getPointerTy(); GlobalAddressSDNode *GSDN = cast(Op); GlobalValue *GV = GSDN->getGlobal(); @@ -626,7 +626,10 @@ return Stores[0]; } - switch(Src.getValueType()) { + switch(Src.getValueType().getSimpleVT()) { + default: + assert(false && "Invalid value type!"); + case MVT::i8: break; Modified: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Fri Jun 6 07:08:01 2008 @@ -921,7 +921,7 @@ case ISD::LOAD: { // Handle preincrement loads. LoadSDNode *LD = cast(Op); - MVT::ValueType LoadedVT = LD->getMemoryVT(); + MVT LoadedVT = LD->getMemoryVT(); // Normal loads are handled by code generated from the .td file. if (LD->getAddressingMode() != ISD::PRE_INC) @@ -936,7 +936,7 @@ if (LD->getValueType(0) != MVT::i64) { // Handle PPC32 integer and normal FP loads. assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); - switch (LoadedVT) { + switch (LoadedVT.getSimpleVT()) { default: assert(0 && "Invalid PPC load type!"); case MVT::f64: Opcode = PPC::LFDU; break; case MVT::f32: Opcode = PPC::LFSU; break; @@ -948,7 +948,7 @@ } else { assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!"); assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); - switch (LoadedVT) { + switch (LoadedVT.getSimpleVT()) { default: assert(0 && "Invalid PPC load type!"); case MVT::i64: Opcode = PPC::LDU; break; case MVT::i32: Opcode = PPC::LWZU8; break; Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Fri Jun 6 07:08:01 2008 @@ -256,50 +256,52 @@ if (TM.getSubtarget().hasAltivec()) { // First set operation action for all vector types to expand. Then we // will selectively turn on ones that can be effectively codegen'd. - for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; - VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { + for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; + i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { + MVT VT = (MVT::SimpleValueType)i; + // add/sub are legal for all supported vector VT's. - setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal); - setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal); + setOperationAction(ISD::ADD , VT, Legal); + setOperationAction(ISD::SUB , VT, Legal); // We promote all shuffles to v16i8. - setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote); - AddPromotedToType (ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8); + setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote); + AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8); // We promote all non-typed operations to v4i32. - setOperationAction(ISD::AND , (MVT::ValueType)VT, Promote); - AddPromotedToType (ISD::AND , (MVT::ValueType)VT, MVT::v4i32); - setOperationAction(ISD::OR , (MVT::ValueType)VT, Promote); - AddPromotedToType (ISD::OR , (MVT::ValueType)VT, MVT::v4i32); - setOperationAction(ISD::XOR , (MVT::ValueType)VT, Promote); - AddPromotedToType (ISD::XOR , (MVT::ValueType)VT, MVT::v4i32); - setOperationAction(ISD::LOAD , (MVT::ValueType)VT, Promote); - AddPromotedToType (ISD::LOAD , (MVT::ValueType)VT, MVT::v4i32); - setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote); - AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v4i32); - setOperationAction(ISD::STORE, (MVT::ValueType)VT, Promote); - AddPromotedToType (ISD::STORE, (MVT::ValueType)VT, MVT::v4i32); + setOperationAction(ISD::AND , VT, Promote); + AddPromotedToType (ISD::AND , VT, MVT::v4i32); + setOperationAction(ISD::OR , VT, Promote); + AddPromotedToType (ISD::OR , VT, MVT::v4i32); + setOperationAction(ISD::XOR , VT, Promote); + AddPromotedToType (ISD::XOR , VT, MVT::v4i32); + setOperationAction(ISD::LOAD , VT, Promote); + AddPromotedToType (ISD::LOAD , VT, MVT::v4i32); + setOperationAction(ISD::SELECT, VT, Promote); + AddPromotedToType (ISD::SELECT, VT, MVT::v4i32); + setOperationAction(ISD::STORE, VT, Promote); + AddPromotedToType (ISD::STORE, VT, MVT::v4i32); // No other operations are legal. - setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand); - setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::FNEG, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::UMUL_LOHI, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::SMUL_LOHI, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::UDIVREM, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::SDIVREM, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::FPOW, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::CTPOP, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::CTLZ, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::CTTZ, (MVT::ValueType)VT, Expand); + setOperationAction(ISD::MUL , VT, Expand); + setOperationAction(ISD::SDIV, VT, Expand); + setOperationAction(ISD::SREM, VT, Expand); + setOperationAction(ISD::UDIV, VT, Expand); + setOperationAction(ISD::UREM, VT, Expand); + setOperationAction(ISD::FDIV, VT, Expand); + setOperationAction(ISD::FNEG, VT, Expand); + setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand); + setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand); + setOperationAction(ISD::BUILD_VECTOR, VT, Expand); + setOperationAction(ISD::UMUL_LOHI, VT, Expand); + setOperationAction(ISD::SMUL_LOHI, VT, Expand); + setOperationAction(ISD::UDIVREM, VT, Expand); + setOperationAction(ISD::SDIVREM, VT, Expand); + setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand); + setOperationAction(ISD::FPOW, VT, Expand); + setOperationAction(ISD::CTPOP, VT, Expand); + setOperationAction(ISD::CTLZ, VT, Expand); + setOperationAction(ISD::CTTZ, VT, Expand); } // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle @@ -420,8 +422,7 @@ } -MVT::ValueType -PPCTargetLowering::getSetCCResultType(const SDOperand &) const { +MVT PPCTargetLowering::getSetCCResultType(const SDOperand &) const { return MVT::i32; } @@ -690,7 +691,7 @@ uint64_t Value = 0; if (ConstantSDNode *CN = dyn_cast(OpVal)) { Value = CN->getValue(); - ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8; + ValSizeInBytes = CN->getValueType(0).getSizeInBits()/8; } else if (ConstantFPSDNode *CN = dyn_cast(OpVal)) { assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!"); Value = FloatToBits(CN->getValueAPF().convertToFloat()); @@ -1007,7 +1008,7 @@ if (!EnablePPCPreinc) return false; SDOperand Ptr; - MVT::ValueType VT; + MVT VT; if (LoadSDNode *LD = dyn_cast(N)) { Ptr = LD->getBasePtr(); VT = LD->getMemoryVT(); @@ -1020,7 +1021,7 @@ return false; // PowerPC doesn't have preinc load/store instructions for vectors. - if (MVT::isVector(VT)) + if (VT.isVector()) return false; // TODO: Check reg+reg first. @@ -1055,7 +1056,7 @@ SDOperand PPCTargetLowering::LowerConstantPool(SDOperand Op, SelectionDAG &DAG) { - MVT::ValueType PtrVT = Op.getValueType(); + MVT PtrVT = Op.getValueType(); ConstantPoolSDNode *CP = cast(Op); Constant *C = CP->getConstVal(); SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment()); @@ -1086,7 +1087,7 @@ } SDOperand PPCTargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) { - MVT::ValueType PtrVT = Op.getValueType(); + MVT PtrVT = Op.getValueType(); JumpTableSDNode *JT = cast(Op); SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); SDOperand Zero = DAG.getConstant(0, PtrVT); @@ -1123,7 +1124,7 @@ SDOperand PPCTargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) { - MVT::ValueType PtrVT = Op.getValueType(); + MVT PtrVT = Op.getValueType(); GlobalAddressSDNode *GSDN = cast(Op); GlobalValue *GV = GSDN->getGlobal(); SDOperand GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset()); @@ -1170,13 +1171,13 @@ // fold the new nodes. if (ConstantSDNode *C = dyn_cast(Op.getOperand(1))) { if (C->isNullValue() && CC == ISD::SETEQ) { - MVT::ValueType VT = Op.getOperand(0).getValueType(); + MVT VT = Op.getOperand(0).getValueType(); SDOperand Zext = Op.getOperand(0); if (VT < MVT::i32) { VT = MVT::i32; Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0)); } - unsigned Log2b = Log2_32(MVT::getSizeInBits(VT)); + unsigned Log2b = Log2_32(VT.getSizeInBits()); SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext); SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz, DAG.getConstant(Log2b, MVT::i32)); @@ -1194,9 +1195,9 @@ // condition register, reading it back out, and masking the correct bit. The // normal approach here uses sub to do this instead of xor. Using xor exposes // the result to other bit-twiddling opportunities. - MVT::ValueType LHSVT = Op.getOperand(0).getValueType(); - if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) { - MVT::ValueType VT = Op.getValueType(); + MVT LHSVT = Op.getOperand(0).getValueType(); + if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) { + MVT VT = Op.getValueType(); SDOperand Sub = DAG.getNode(ISD::XOR, LHSVT, Op.getOperand(0), Op.getOperand(1)); return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC); @@ -1225,7 +1226,7 @@ if (Subtarget.isMachoABI()) { // vastart just stores the address of the VarArgsFrameIndex slot into the // memory location argument. - MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); const Value *SV = cast(Op.getOperand(2))->getValue(); return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0); @@ -1260,15 +1261,15 @@ SDOperand ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i8); - MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); SDOperand StackOffsetFI = DAG.getFrameIndex(VarArgsStackOffset, PtrVT); SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); - uint64_t FrameOffset = MVT::getSizeInBits(PtrVT)/8; + uint64_t FrameOffset = PtrVT.getSizeInBits()/8; SDOperand ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT); - uint64_t StackOffset = MVT::getSizeInBits(PtrVT)/8 - 1; + uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1; SDOperand ConstStackOffset = DAG.getConstant(StackOffset, PtrVT); uint64_t FPROffset = 1; @@ -1325,9 +1326,9 @@ /// the stack. static unsigned CalculateStackSlotSize(SDOperand Arg, SDOperand Flag, bool isVarArg, unsigned PtrByteSize) { - MVT::ValueType ArgVT = Arg.getValueType(); + MVT ArgVT = Arg.getValueType(); ISD::ArgFlagsTy Flags = cast(Flag)->getArgFlags(); - unsigned ArgSize =MVT::getSizeInBits(ArgVT)/8; + unsigned ArgSize =ArgVT.getSizeInBits()/8; if (Flags.isByVal()) ArgSize = Flags.getByValSize(); ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; @@ -1352,7 +1353,7 @@ SDOperand Root = Op.getOperand(0); bool isVarArg = cast(Op.getOperand(2))->getValue() != 0; - MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); bool isPPC64 = PtrVT == MVT::i64; bool isMachoABI = Subtarget.isMachoABI(); bool isELF32_ABI = Subtarget.isELF32_ABI(); @@ -1402,8 +1403,8 @@ if (!isVarArg && !isPPC64) { for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) { - MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType(); - unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8; + MVT ObjectVT = Op.getValue(ArgNo).getValueType(); + unsigned ObjSize = ObjectVT.getSizeInBits()/8; ISD::ArgFlagsTy Flags = cast(Op.getOperand(ArgNo+3))->getArgFlags(); @@ -1416,7 +1417,7 @@ continue; } - switch(ObjectVT) { + switch(ObjectVT.getSimpleVT()) { default: assert(0 && "Unhandled argument type!"); case MVT::i32: case MVT::f32: @@ -1453,8 +1454,8 @@ for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) { SDOperand ArgVal; bool needsLoad = false; - MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType(); - unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8; + MVT ObjectVT = Op.getValue(ArgNo).getValueType(); + unsigned ObjSize = ObjectVT.getSizeInBits()/8; unsigned ArgSize = ObjSize; ISD::ArgFlagsTy Flags = cast(Op.getOperand(ArgNo+3))->getArgFlags(); @@ -1535,7 +1536,7 @@ continue; } - switch (ObjectVT) { + switch (ObjectVT.getSimpleVT()) { default: assert(0 && "Unhandled argument type!"); case MVT::i32: if (!isPPC64) { @@ -1693,18 +1694,18 @@ // Make room for Num_GPR_Regs, Num_FPR_Regs and for a possible frame // pointer. - depth = -(Num_GPR_Regs * MVT::getSizeInBits(PtrVT)/8 + - Num_FPR_Regs * MVT::getSizeInBits(MVT::f64)/8 + - MVT::getSizeInBits(PtrVT)/8); + depth = -(Num_GPR_Regs * PtrVT.getSizeInBits()/8 + + Num_FPR_Regs * MVT(MVT::f64).getSizeInBits()/8 + + PtrVT.getSizeInBits()/8); - VarArgsStackOffset = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8, + VarArgsStackOffset = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8, ArgOffset); } else depth = ArgOffset; - VarArgsFrameIndex = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8, + VarArgsFrameIndex = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8, depth); SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); @@ -1716,7 +1717,7 @@ SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0); MemOps.push_back(Store); // Increment the address by four for the next argument to store - SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT); + SDOperand PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT); FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); } } @@ -1736,7 +1737,7 @@ SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); MemOps.push_back(Store); // Increment the address by four for the next argument to store - SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT); + SDOperand PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT); FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); } @@ -1748,7 +1749,7 @@ SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0); MemOps.push_back(Store); // Increment the address by eight for the next argument to store - SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(MVT::f64)/8, + SDOperand PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8, PtrVT); FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); } @@ -1762,7 +1763,7 @@ SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); MemOps.push_back(Store); // Increment the address by eight for the next argument to store - SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(MVT::f64)/8, + SDOperand PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8, PtrVT); FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); } @@ -1775,7 +1776,7 @@ ArgValues.push_back(Root); // Return the new list of results. - std::vector RetVT(Op.Val->value_begin(), + std::vector RetVT(Op.Val->value_begin(), Op.Val->value_end()); return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size()); } @@ -1807,7 +1808,7 @@ for (unsigned i = 0; i != NumOps; ++i) { SDOperand Arg = Call.getOperand(5+2*i); SDOperand Flag = Call.getOperand(5+2*i+1); - MVT::ValueType ArgVT = Arg.getValueType(); + MVT ArgVT = Arg.getValueType(); // Varargs Altivec parameters are padded to a 16 byte boundary. if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 || ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) { @@ -1970,7 +1971,7 @@ isMachoABI); int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc); - MVT::ValueType VT = isPPC64 ? MVT::i64 : MVT::i32; + MVT VT = isPPC64 ? MVT::i64 : MVT::i32; SDOperand NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT); Chain = DAG.getStore(Chain, OldRetAddr, NewRetAddrFrIdx, PseudoSourceValue::getFixedStack(), NewRetAddr); @@ -1988,9 +1989,9 @@ SDOperand Arg, int SPDiff, unsigned ArgOffset, SmallVector& TailCallArguments) { int Offset = ArgOffset + SPDiff; - uint32_t OpSize = (MVT::getSizeInBits(Arg.getValueType())+7)/8; + uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8; int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset); - MVT::ValueType VT = isPPC64 ? MVT::i64 : MVT::i32; + MVT VT = isPPC64 ? MVT::i64 : MVT::i32; SDOperand FIN = DAG.getFrameIndex(FI, VT); TailCallArgumentInfo Info; Info.Arg = Arg; @@ -2009,7 +2010,7 @@ SDOperand &FPOpOut) { if (SPDiff) { // Load the LR and FP stack slot for later adjusting. - MVT::ValueType VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32; + MVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32; LROpOut = getReturnAddrFrameIndex(DAG); LROpOut = DAG.getLoad(VT, Chain, LROpOut, NULL, 0); Chain = SDOperand(LROpOut.Val, 1); @@ -2043,7 +2044,7 @@ unsigned ArgOffset, bool isPPC64, bool isTailCall, bool isVector, SmallVector &MemOpChains, SmallVector& TailCallArguments) { - MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); if (!isTailCall) { if (isVector) { SDOperand StackPtr; @@ -2074,7 +2075,7 @@ bool isMachoABI = Subtarget.isMachoABI(); bool isELF32_ABI = Subtarget.isELF32_ABI(); - MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); bool isPPC64 = PtrVT == MVT::i64; unsigned PtrByteSize = isPPC64 ? 8 : 4; @@ -2192,7 +2193,7 @@ if (Size==1 || Size==2) { // Very small objects are passed right-justified. // Everything else is passed left-justified. - MVT::ValueType VT = (Size==1) ? MVT::i8 : MVT::i16; + MVT VT = (Size==1) ? MVT::i8 : MVT::i16; if (GPR_idx != NumGPRs) { SDOperand Load = DAG.getExtLoad(ISD::EXTLOAD, PtrVT, Chain, Arg, NULL, 0, VT); @@ -2244,7 +2245,7 @@ continue; } - switch (Arg.getValueType()) { + switch (Arg.getValueType().getSimpleVT()) { default: assert(0 && "Unexpected ValueType for argument!"); case MVT::i32: case MVT::i64: @@ -2384,7 +2385,7 @@ ArgOffset += 12*16; for (unsigned i = 0; i != NumOps; ++i) { SDOperand Arg = Op.getOperand(5+2*i); - MVT::ValueType ArgType = Arg.getValueType(); + MVT ArgType = Arg.getValueType(); if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 || ArgType==MVT::v8i16 || ArgType==MVT::v16i8) { if (++j > NumVRs) { @@ -2450,7 +2451,7 @@ InFlag = Chain.getValue(1); } - std::vector NodeTys; + std::vector NodeTys; NodeTys.push_back(MVT::Other); // Returns a chain NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. @@ -2544,7 +2545,7 @@ // Copy all of the result registers out of their specified physreg. for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { CCValAssign &VA = RVLocs[i]; - MVT::ValueType VT = VA.getValVT(); + MVT VT = VA.getValVT(); assert(VA.isRegLoc() && "Can only return in registers!"); Chain = DAG.getCopyFromReg(Chain, VA.getLocReg(), VT, InFlag).getValue(1); ResultVals.push_back(Chain.getValue(0)); @@ -2629,7 +2630,7 @@ // When we pop the dynamic allocation we need to restore the SP link. // Get the corect type for pointers. - MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); // Construct the stack pointer operand. bool IsPPC64 = Subtarget.isPPC64(); @@ -2657,7 +2658,7 @@ MachineFunction &MF = DAG.getMachineFunction(); bool IsPPC64 = PPCSubTarget.isPPC64(); bool isMachoABI = PPCSubTarget.isMachoABI(); - MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); // Get current frame pointer save index. The users of this index will be // primarily DYNALLOC instructions. @@ -2681,7 +2682,7 @@ MachineFunction &MF = DAG.getMachineFunction(); bool IsPPC64 = PPCSubTarget.isPPC64(); bool isMachoABI = PPCSubTarget.isMachoABI(); - MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); // Get current frame pointer save index. The users of this index will be // primarily DYNALLOC instructions. @@ -2709,7 +2710,7 @@ SDOperand Size = Op.getOperand(1); // Get the corect type for pointers. - MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); // Negate the size. SDOperand NegSize = DAG.getNode(ISD::SUB, PtrVT, DAG.getConstant(0, PtrVT), Size); @@ -2722,13 +2723,13 @@ } SDOperand PPCTargetLowering::LowerAtomicLAS(SDOperand Op, SelectionDAG &DAG) { - MVT::ValueType VT = Op.Val->getValueType(0); + MVT VT = Op.Val->getValueType(0); SDOperand Chain = Op.getOperand(0); SDOperand Ptr = Op.getOperand(1); SDOperand Incr = Op.getOperand(2); // Issue a "load and reserve". - std::vector VTs; + std::vector VTs; VTs.push_back(VT); VTs.push_back(MVT::Other); @@ -2758,14 +2759,14 @@ } SDOperand PPCTargetLowering::LowerAtomicLCS(SDOperand Op, SelectionDAG &DAG) { - MVT::ValueType VT = Op.Val->getValueType(0); + MVT VT = Op.Val->getValueType(0); SDOperand Chain = Op.getOperand(0); SDOperand Ptr = Op.getOperand(1); SDOperand NewVal = Op.getOperand(2); SDOperand OldVal = Op.getOperand(3); // Issue a "load and reserve". - std::vector VTs; + std::vector VTs; VTs.push_back(VT); VTs.push_back(MVT::Other); @@ -2801,13 +2802,13 @@ } SDOperand PPCTargetLowering::LowerAtomicSWAP(SDOperand Op, SelectionDAG &DAG) { - MVT::ValueType VT = Op.Val->getValueType(0); + MVT VT = Op.Val->getValueType(0); SDOperand Chain = Op.getOperand(0); SDOperand Ptr = Op.getOperand(1); SDOperand NewVal = Op.getOperand(2); // Issue a "load and reserve". - std::vector VTs; + std::vector VTs; VTs.push_back(VT); VTs.push_back(MVT::Other); @@ -2837,8 +2838,8 @@ /// possible. SDOperand PPCTargetLowering::LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) { // Not FP? Not a fsel. - if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) || - !MVT::isFloatingPoint(Op.getOperand(2).getValueType())) + if (!Op.getOperand(0).getValueType().isFloatingPoint() || + !Op.getOperand(2).getValueType().isFloatingPoint()) return SDOperand(); ISD::CondCode CC = cast(Op.getOperand(4))->get(); @@ -2846,8 +2847,8 @@ // Cannot handle SETEQ/SETNE. if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDOperand(); - MVT::ValueType ResVT = Op.getValueType(); - MVT::ValueType CmpVT = Op.getOperand(0).getValueType(); + MVT ResVT = Op.getValueType(); + MVT CmpVT = Op.getOperand(0).getValueType(); SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3); @@ -2916,13 +2917,13 @@ // FIXME: Split this code up when LegalizeDAGTypes lands. SDOperand PPCTargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) { - assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType())); + assert(Op.getOperand(0).getValueType().isFloatingPoint()); SDOperand Src = Op.getOperand(0); if (Src.getValueType() == MVT::f32) Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src); SDOperand Tmp; - switch (Op.getValueType()) { + switch (Op.getValueType().getSimpleVT()) { default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!"); case MVT::i32: Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src); @@ -2958,7 +2959,7 @@ // This sequence changes FPSCR to do round-to-zero, adds the two halves // of the long double, and puts FPSCR back the way it was. We do not // actually model FPSCR. - std::vector NodeTys; + std::vector NodeTys; SDOperand Ops[4], Result, MFFSreg, InFlag, FPreg; NodeTys.push_back(MVT::f64); // Return register @@ -3026,7 +3027,7 @@ // then lfd it and fcfid it. MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); int FrameIdx = FrameInfo->CreateStackObject(8, 8); - MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32, @@ -3069,9 +3070,9 @@ */ MachineFunction &MF = DAG.getMachineFunction(); - MVT::ValueType VT = Op.getValueType(); - MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); - std::vector NodeTys; + MVT VT = Op.getValueType(); + MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + std::vector NodeTys; SDOperand MFFSreg, InFlag; // Save FP Control Word to register @@ -3105,13 +3106,13 @@ SDOperand RetVal = DAG.getNode(ISD::XOR, MVT::i32, CWD1, CWD2); - return DAG.getNode((MVT::getSizeInBits(VT) < 16 ? + return DAG.getNode((VT.getSizeInBits() < 16 ? ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal); } SDOperand PPCTargetLowering::LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG) { - MVT::ValueType VT = Op.getValueType(); - unsigned BitWidth = MVT::getSizeInBits(VT); + MVT VT = Op.getValueType(); + unsigned BitWidth = VT.getSizeInBits(); assert(Op.getNumOperands() == 3 && VT == Op.getOperand(1).getValueType() && "Unexpected SHL!"); @@ -3121,7 +3122,7 @@ SDOperand Lo = Op.getOperand(0); SDOperand Hi = Op.getOperand(1); SDOperand Amt = Op.getOperand(2); - MVT::ValueType AmtVT = Amt.getValueType(); + MVT AmtVT = Amt.getValueType(); SDOperand Tmp1 = DAG.getNode(ISD::SUB, AmtVT, DAG.getConstant(BitWidth, AmtVT), Amt); @@ -3139,8 +3140,8 @@ } SDOperand PPCTargetLowering::LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) { - MVT::ValueType VT = Op.getValueType(); - unsigned BitWidth = MVT::getSizeInBits(VT); + MVT VT = Op.getValueType(); + unsigned BitWidth = VT.getSizeInBits(); assert(Op.getNumOperands() == 3 && VT == Op.getOperand(1).getValueType() && "Unexpected SRL!"); @@ -3150,7 +3151,7 @@ SDOperand Lo = Op.getOperand(0); SDOperand Hi = Op.getOperand(1); SDOperand Amt = Op.getOperand(2); - MVT::ValueType AmtVT = Amt.getValueType(); + MVT AmtVT = Amt.getValueType(); SDOperand Tmp1 = DAG.getNode(ISD::SUB, AmtVT, DAG.getConstant(BitWidth, AmtVT), Amt); @@ -3168,8 +3169,8 @@ } SDOperand PPCTargetLowering::LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG) { - MVT::ValueType VT = Op.getValueType(); - unsigned BitWidth = MVT::getSizeInBits(VT); + MVT VT = Op.getValueType(); + unsigned BitWidth = VT.getSizeInBits(); assert(Op.getNumOperands() == 3 && VT == Op.getOperand(1).getValueType() && "Unexpected SRA!"); @@ -3178,7 +3179,7 @@ SDOperand Lo = Op.getOperand(0); SDOperand Hi = Op.getOperand(1); SDOperand Amt = Op.getOperand(2); - MVT::ValueType AmtVT = Amt.getValueType(); + MVT AmtVT = Amt.getValueType(); SDOperand Tmp1 = DAG.getNode(ISD::SUB, AmtVT, DAG.getConstant(BitWidth, AmtVT), Amt); @@ -3210,7 +3211,7 @@ // Start with zero'd results. VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0; - unsigned EltBitSize = MVT::getSizeInBits(BV->getOperand(0).getValueType()); + unsigned EltBitSize = BV->getOperand(0).getValueType().getSizeInBits(); for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { SDOperand OpVal = BV->getOperand(i); @@ -3296,26 +3297,26 @@ /// BuildSplatI - Build a canonical splati of Val with an element size of /// SplatSize. Cast the result to VT. -static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT::ValueType VT, +static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT VT, SelectionDAG &DAG) { assert(Val >= -16 && Val <= 15 && "vsplti is out of range!"); - static const MVT::ValueType VTys[] = { // canonical VT to use for each size. + static const MVT VTys[] = { // canonical VT to use for each size. MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32 }; - MVT::ValueType ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1]; + MVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1]; // Force vspltis[hw] -1 to vspltisb -1 to canonicalize. if (Val == -1) SplatSize = 1; - MVT::ValueType CanonicalVT = VTys[SplatSize-1]; + MVT CanonicalVT = VTys[SplatSize-1]; // Build a canonical splat for this value. - SDOperand Elt = DAG.getConstant(Val, MVT::getVectorElementType(CanonicalVT)); + SDOperand Elt = DAG.getConstant(Val, CanonicalVT.getVectorElementType()); SmallVector Ops; - Ops.assign(MVT::getVectorNumElements(CanonicalVT), Elt); + Ops.assign(CanonicalVT.getVectorNumElements(), Elt); SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT, &Ops[0], Ops.size()); return DAG.getNode(ISD::BIT_CONVERT, ReqVT, Res); @@ -3325,7 +3326,7 @@ /// specified intrinsic ID. static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand LHS, SDOperand RHS, SelectionDAG &DAG, - MVT::ValueType DestVT = MVT::Other) { + MVT DestVT = MVT::Other) { if (DestVT == MVT::Other) DestVT = LHS.getValueType(); return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT, DAG.getConstant(IID, MVT::i32), LHS, RHS); @@ -3335,7 +3336,7 @@ /// specified intrinsic ID. static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand Op0, SDOperand Op1, SDOperand Op2, SelectionDAG &DAG, - MVT::ValueType DestVT = MVT::Other) { + MVT DestVT = MVT::Other) { if (DestVT == MVT::Other) DestVT = Op0.getValueType(); return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT, DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2); @@ -3345,7 +3346,7 @@ /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified /// amount. The result has the specified value type. static SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt, - MVT::ValueType VT, SelectionDAG &DAG) { + MVT VT, SelectionDAG &DAG) { // Force LHS/RHS to be the right type. LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS); RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS); @@ -3705,8 +3706,8 @@ // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except // that it is in input element units, not in bytes. Convert now. - MVT::ValueType EltVT = MVT::getVectorElementType(V1.getValueType()); - unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8; + MVT EltVT = V1.getValueType().getVectorElementType(); + unsigned BytesPerElement = EltVT.getSizeInBits()/8; SmallVector ResultMask; for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) { @@ -3794,7 +3795,7 @@ Op.getOperand(3), // RHS DAG.getConstant(CompareOpc, MVT::i32) }; - std::vector VTs; + std::vector VTs; VTs.push_back(Op.getOperand(2).getValueType()); VTs.push_back(MVT::Flag); SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3); @@ -3843,7 +3844,7 @@ // Create a stack slot that is 16-byte aligned. MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); int FrameIdx = FrameInfo->CreateStackObject(16, 16); - MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); // Store the input value into Value#0 of the stack slot. @@ -4154,7 +4155,7 @@ SDOperand Load = N->getOperand(0); LoadSDNode *LD = cast(Load); // Create the byte-swapping load. - std::vector VTs; + std::vector VTs; VTs.push_back(MVT::i32); VTs.push_back(MVT::Other); SDOperand MO = DAG.getMemOperand(LD->getMemOperand()); @@ -4264,7 +4265,7 @@ bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0); // Create the PPCISD altivec 'dot' comparison node. - std::vector VTs; + std::vector VTs; SDOperand Ops[] = { LHS.getOperand(2), // LHS of compare LHS.getOperand(3), // RHS of compare @@ -4367,7 +4368,7 @@ std::pair PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, - MVT::ValueType VT) const { + MVT VT) const { if (Constraint.size() == 1) { // GCC RS6000 Constraint Letters switch (Constraint[0]) { @@ -4527,7 +4528,7 @@ if (cast(Op.getOperand(0))->getValue() > 0) return SDOperand(); - MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); bool isPPC64 = PtrVT == MVT::i64; MachineFunction &MF = DAG.getMachineFunction(); Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h Fri Jun 6 07:08:01 2008 @@ -235,7 +235,7 @@ virtual const char *getTargetNodeName(unsigned Opcode) const; /// getSetCCResultType - Return the ISD::SETCC ValueType - virtual MVT::ValueType getSetCCResultType(const SDOperand &) const; + virtual MVT getSetCCResultType(const SDOperand &) const; /// getPreIndexedAddressParts - returns true by value, base pointer and /// offset pointer and addressing mode by reference if the node's address @@ -290,7 +290,7 @@ ConstraintType getConstraintType(const std::string &Constraint) const; std::pair getRegForInlineAsmConstraint(const std::string &Constraint, - MVT::ValueType VT) const; + MVT VT) const; /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate /// function arguments in the caller parameter area. This is the actual Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Fri Jun 6 07:08:01 2008 @@ -91,9 +91,9 @@ std::vector OutChains; for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { - MVT::ValueType ObjectVT = getValueType(I->getType()); + MVT ObjectVT = getValueType(I->getType()); - switch (ObjectVT) { + switch (ObjectVT.getSimpleVT()) { default: assert(0 && "Unhandled argument type!"); case MVT::i1: case MVT::i8: @@ -123,7 +123,7 @@ ISD::LoadExtType LoadOp = ISD::SEXTLOAD; // Sparc is big endian, so add an offset based on the ObjectVT. - unsigned Offset = 4-std::max(1U, MVT::getSizeInBits(ObjectVT)/8); + unsigned Offset = 4-std::max(1U, ObjectVT.getSizeInBits()/8); FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr, DAG.getConstant(Offset, MVT::i32)); Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr, @@ -246,7 +246,7 @@ // Count the size of the outgoing arguments. unsigned ArgsSize = 0; for (unsigned i = 5, e = Op.getNumOperands(); i != e; i += 2) { - switch (Op.getOperand(i).getValueType()) { + switch (Op.getOperand(i).getValueType().getSimpleVT()) { default: assert(0 && "Unknown value type!"); case MVT::i1: case MVT::i8: @@ -323,10 +323,10 @@ for (unsigned i = 5, e = Op.getNumOperands(); i != e; i += 2) { SDOperand Val = Op.getOperand(i); - MVT::ValueType ObjectVT = Val.getValueType(); + MVT ObjectVT = Val.getValueType(); SDOperand ValToStore(0, 0); unsigned ObjSize; - switch (ObjectVT) { + switch (ObjectVT.getSimpleVT()) { default: assert(0 && "Unhandled argument type!"); case MVT::i32: ObjSize = 4; @@ -414,7 +414,7 @@ else if (ExternalSymbolSDNode *E = dyn_cast(Callee)) Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32); - std::vector NodeTys; + std::vector NodeTys; NodeTys.push_back(MVT::Other); // Returns a chain NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. SDOperand Ops[] = { Chain, Callee, InFlag }; @@ -744,7 +744,7 @@ // Get the condition flag. SDOperand CompareFlag; if (LHS.getValueType() == MVT::i32) { - std::vector VTs; + std::vector VTs; VTs.push_back(MVT::i32); VTs.push_back(MVT::Flag); SDOperand Ops[2] = { LHS, RHS }; @@ -774,7 +774,7 @@ SDOperand CompareFlag; if (LHS.getValueType() == MVT::i32) { - std::vector VTs; + std::vector VTs; VTs.push_back(LHS.getValueType()); // subcc returns a value VTs.push_back(MVT::Flag); SDOperand Ops[2] = { LHS, RHS }; @@ -804,14 +804,14 @@ static SDOperand LowerVAARG(SDOperand Op, SelectionDAG &DAG) { SDNode *Node = Op.Val; - MVT::ValueType VT = Node->getValueType(0); + MVT VT = Node->getValueType(0); SDOperand InChain = Node->getOperand(0); SDOperand VAListPtr = Node->getOperand(1); const Value *SV = cast(Node->getOperand(2))->getValue(); SDOperand VAList = DAG.getLoad(MVT::i32, InChain, VAListPtr, SV, 0); // Increment the pointer, VAList, to the next vaarg SDOperand NextPtr = DAG.getNode(ISD::ADD, MVT::i32, VAList, - DAG.getConstant(MVT::getSizeInBits(VT)/8, + DAG.getConstant(VT.getSizeInBits()/8, MVT::i32)); // Store the incremented VAList to the legalized pointer InChain = DAG.getStore(VAList.getValue(1), NextPtr, @@ -846,7 +846,7 @@ // to provide a register spill area. SDOperand NewVal = DAG.getNode(ISD::ADD, MVT::i32, NewSP, DAG.getConstant(96, MVT::i32)); - std::vector Tys; + std::vector Tys; Tys.push_back(MVT::i32); Tys.push_back(MVT::Other); SDOperand Ops[2] = { NewVal, Chain }; Modified: llvm/trunk/lib/Target/TargetRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetRegisterInfo.cpp?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/TargetRegisterInfo.cpp Fri Jun 6 07:08:01 2008 @@ -48,8 +48,7 @@ /// register of the given type. If type is MVT::Other, then just return any /// register class the register belongs to. const TargetRegisterClass * -TargetRegisterInfo::getPhysicalRegisterRegClass(unsigned reg, - MVT::ValueType VT) const { +TargetRegisterInfo::getPhysicalRegisterRegClass(unsigned reg, MVT VT) const { assert(isPhysicalRegister(reg) && "reg must be a physical register"); // Pick the register class of the right type that contains this physreg. Modified: llvm/trunk/lib/Target/TargetSelectionDAG.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetSelectionDAG.td?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetSelectionDAG.td (original) +++ llvm/trunk/lib/Target/TargetSelectionDAG.td Fri Jun 6 07:08:01 2008 @@ -53,8 +53,8 @@ /// SDTCisIntVectorOfSameSize - This indicates that ThisOp and OtherOp are /// vector types, and that ThisOp is the result of -/// MVT::getIntVectorWithNumElements with the number of elements that ThisOp -/// has. +/// MVT::getIntVectorWithNumElements with the number of elements +/// that ThisOp has. class SDTCisIntVectorOfSameSize : SDTypeConstraint { int OtherOpNum = OtherOp; @@ -467,8 +467,8 @@ // Leaf fragments. -def vtInt : PatLeaf<(vt), [{ return MVT::isInteger(N->getVT()); }]>; -def vtFP : PatLeaf<(vt), [{ return MVT::isFloatingPoint(N->getVT()); }]>; +def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>; +def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>; def immAllOnes : PatLeaf<(imm), [{ return N->isAllOnesValue(); }]>; def immAllOnesV: PatLeaf<(build_vector), [{ Modified: llvm/trunk/lib/Target/X86/X86ATTAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ATTAsmPrinter.cpp?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ATTAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ATTAsmPrinter.cpp Fri Jun 6 07:08:01 2008 @@ -215,7 +215,7 @@ O << '%'; unsigned Reg = MO.getReg(); if (Modifier && strncmp(Modifier, "subreg", strlen("subreg")) == 0) { - MVT::ValueType VT = (strcmp(Modifier+6,"64") == 0) ? + MVT VT = (strcmp(Modifier+6,"64") == 0) ? MVT::i64 : ((strcmp(Modifier+6, "32") == 0) ? MVT::i32 : ((strcmp(Modifier+6,"16") == 0) ? MVT::i16 : MVT::i8)); Reg = getX86SubSuperRegister(Reg, VT); Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Fri Jun 6 07:08:01 2008 @@ -215,7 +215,7 @@ /// getTruncate - return an SDNode that implements a subreg based truncate /// of the specified operand to the the specified value type. - SDNode *getTruncate(SDOperand N0, MVT::ValueType VT); + SDNode *getTruncate(SDOperand N0, MVT VT); #ifndef NDEBUG unsigned Indent; @@ -329,7 +329,7 @@ // NU), then TF is a predecessor of FU and a successor of NU. But since // NU and FU are flagged together, this effectively creates a cycle. bool HasFlagUse = false; - MVT::ValueType VT = Root->getValueType(Root->getNumValues()-1); + MVT VT = Root->getValueType(Root->getNumValues()-1); while ((VT == MVT::Flag && !Root->use_empty())) { SDNode *FU = findFlagUse(Root); if (FU == NULL) @@ -440,8 +440,8 @@ SDOperand N1 = I->getOperand(1); SDOperand N2 = I->getOperand(2); - if ((MVT::isFloatingPoint(N1.getValueType()) && - !MVT::isVector(N1.getValueType())) || + if ((N1.getValueType().isFloatingPoint() && + !N1.getValueType().isVector()) || !N1.hasOneUse()) continue; @@ -505,8 +505,8 @@ // If the source and destination are SSE registers, then this is a legal // conversion that should not be lowered. - MVT::ValueType SrcVT = N->getOperand(0).getValueType(); - MVT::ValueType DstVT = N->getValueType(0); + MVT SrcVT = N->getOperand(0).getValueType(); + MVT DstVT = N->getValueType(0); bool SrcIsSSE = X86Lowering.isScalarFPTypeInSSEReg(SrcVT); bool DstIsSSE = X86Lowering.isScalarFPTypeInSSEReg(DstVT); if (SrcIsSSE && DstIsSSE) @@ -524,7 +524,7 @@ // Here we could have an FP stack truncation or an FPStack <-> SSE convert. // FPStack has extload and truncstore. SSE can fold direct loads into other // operations. Based on this, decide what we want to do. - MVT::ValueType MemVT; + MVT MemVT; if (N->getOpcode() == ISD::FP_ROUND) MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'. else @@ -942,7 +942,7 @@ if (MatchAddress(N, AM)) return false; - MVT::ValueType VT = N.getValueType(); + MVT VT = N.getValueType(); if (AM.BaseType == X86ISelAddressMode::RegBase) { if (!AM.Base.Reg.Val) AM.Base.Reg = CurDAG->getRegister(0, VT); @@ -1016,7 +1016,7 @@ if (MatchAddress(N, AM)) return false; - MVT::ValueType VT = N.getValueType(); + MVT VT = N.getValueType(); unsigned Complexity = 0; if (AM.BaseType == X86ISelAddressMode::RegBase) if (AM.Base.Reg.Val) @@ -1110,16 +1110,17 @@ return FindCallStartFromCall(Node->getOperand(0).Val); } -SDNode *X86DAGToDAGISel::getTruncate(SDOperand N0, MVT::ValueType VT) { +SDNode *X86DAGToDAGISel::getTruncate(SDOperand N0, MVT VT) { SDOperand SRIdx; - switch (VT) { + switch (VT.getSimpleVT()) { + default: assert(0 && "Unknown truncate!"); case MVT::i8: SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1 // Ensure that the source register has an 8-bit subreg on 32-bit targets if (!Subtarget->is64Bit()) { unsigned Opc; - MVT::ValueType VT; - switch (N0.getValueType()) { + MVT VT; + switch (N0.getValueType().getSimpleVT()) { default: assert(0 && "Unknown truncate!"); case MVT::i16: Opc = X86::MOV16to16_; @@ -1141,7 +1142,6 @@ case MVT::i32: SRIdx = CurDAG->getTargetConstant(3, MVT::i32); // SubRegSet 3 break; - default: assert(0 && "Unknown truncate!"); break; } return CurDAG->getTargetNode(X86::EXTRACT_SUBREG, VT, N0, SRIdx); } @@ -1149,7 +1149,7 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) { SDNode *Node = N.Val; - MVT::ValueType NVT = Node->getValueType(0); + MVT NVT = Node->getValueType(0); unsigned Opc, MOpc; unsigned Opcode = Node->getOpcode(); @@ -1183,7 +1183,7 @@ // RIP-relative addressing. if (TM.getCodeModel() != CodeModel::Small) break; - MVT::ValueType PtrVT = TLI.getPointerTy(); + MVT PtrVT = TLI.getPointerTy(); SDOperand N0 = N.getOperand(0); SDOperand N1 = N.getOperand(1); if (N.Val->getValueType(0) == PtrVT && @@ -1224,7 +1224,7 @@ bool isSigned = Opcode == ISD::SMUL_LOHI; if (!isSigned) - switch (NVT) { + switch (NVT.getSimpleVT()) { default: assert(0 && "Unsupported VT!"); case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break; case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break; @@ -1232,7 +1232,7 @@ case MVT::i64: Opc = X86::MUL64r; MOpc = X86::MUL64m; break; } else - switch (NVT) { + switch (NVT.getSimpleVT()) { default: assert(0 && "Unsupported VT!"); case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break; case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break; @@ -1241,7 +1241,7 @@ } unsigned LoReg, HiReg; - switch (NVT) { + switch (NVT.getSimpleVT()) { default: assert(0 && "Unsupported VT!"); case MVT::i8: LoReg = X86::AL; HiReg = X86::AH; break; case MVT::i16: LoReg = X86::AX; HiReg = X86::DX; break; @@ -1334,7 +1334,7 @@ bool isSigned = Opcode == ISD::SDIVREM; if (!isSigned) - switch (NVT) { + switch (NVT.getSimpleVT()) { default: assert(0 && "Unsupported VT!"); case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break; case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break; @@ -1342,7 +1342,7 @@ case MVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break; } else - switch (NVT) { + switch (NVT.getSimpleVT()) { default: assert(0 && "Unsupported VT!"); case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break; case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break; @@ -1352,7 +1352,7 @@ unsigned LoReg, HiReg; unsigned ClrOpcode, SExtOpcode; - switch (NVT) { + switch (NVT.getSimpleVT()) { default: assert(0 && "Unsupported VT!"); case MVT::i8: LoReg = X86::AL; HiReg = X86::AH; @@ -1493,7 +1493,7 @@ SDOperand N0 = Node->getOperand(0); // Get the subregsiter index for the type to extend. - MVT::ValueType N0VT = N0.getValueType(); + MVT N0VT = N0.getValueType(); unsigned Idx = (N0VT == MVT::i32) ? X86::SUBREG_32BIT : (N0VT == MVT::i16) ? X86::SUBREG_16BIT : (Subtarget->is64Bit()) ? X86::SUBREG_8BIT : 0; @@ -1523,30 +1523,30 @@ SDOperand N0 = Node->getOperand(0); AddToISelQueue(N0); - MVT::ValueType SVT = cast(Node->getOperand(1))->getVT(); + MVT SVT = cast(Node->getOperand(1))->getVT(); SDOperand TruncOp = SDOperand(getTruncate(N0, SVT), 0); unsigned Opc = 0; - switch (NVT) { + switch (NVT.getSimpleVT()) { + default: assert(0 && "Unknown sign_extend_inreg!"); case MVT::i16: if (SVT == MVT::i8) Opc = X86::MOVSX16rr8; else assert(0 && "Unknown sign_extend_inreg!"); break; case MVT::i32: - switch (SVT) { + switch (SVT.getSimpleVT()) { + default: assert(0 && "Unknown sign_extend_inreg!"); case MVT::i8: Opc = X86::MOVSX32rr8; break; case MVT::i16: Opc = X86::MOVSX32rr16; break; - default: assert(0 && "Unknown sign_extend_inreg!"); } break; case MVT::i64: - switch (SVT) { + switch (SVT.getSimpleVT()) { + default: assert(0 && "Unknown sign_extend_inreg!"); case MVT::i8: Opc = X86::MOVSX64rr8; break; case MVT::i16: Opc = X86::MOVSX64rr16; break; case MVT::i32: Opc = X86::MOVSX64rr32; break; - default: assert(0 && "Unknown sign_extend_inreg!"); } break; - default: assert(0 && "Unknown sign_extend_inreg!"); } SDNode *ResNode = CurDAG->getTargetNode(Opc, NVT, TruncOp); Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Jun 6 07:08:01 2008 @@ -493,44 +493,44 @@ // will selectively turn on ones that can be effectively codegen'd. for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { - setOperationAction(ISD::ADD , (MVT::ValueType)VT, Expand); - setOperationAction(ISD::SUB , (MVT::ValueType)VT, Expand); - setOperationAction(ISD::FADD, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::FNEG, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::FSUB, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand); - setOperationAction(ISD::FMUL, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::FABS, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::FSIN, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::FCOS, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::FREM, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::FPOWI, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::FSQRT, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::FCOPYSIGN, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::SMUL_LOHI, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::UMUL_LOHI, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::SDIVREM, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::UDIVREM, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::FPOW, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::CTPOP, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::CTTZ, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::CTLZ, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::SHL, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::SRA, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::SRL, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::ROTL, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::ROTR, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::BSWAP, (MVT::ValueType)VT, Expand); - setOperationAction(ISD::VSETCC, (MVT::ValueType)VT, Expand); + setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand); } if (Subtarget->hasMMX()) { @@ -654,13 +654,14 @@ setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); // Custom lower build_vector, vector_shuffle, and extract_vector_elt. - for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) { + for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) { + MVT VT = (MVT::SimpleValueType)i; // Do not attempt to custom lower non-power-of-2 vectors - if (!isPowerOf2_32(MVT::getVectorNumElements(VT))) + if (!isPowerOf2_32(VT.getVectorNumElements())) continue; - setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Custom); - setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Custom); - setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Custom); + setOperationAction(ISD::BUILD_VECTOR, VT, Custom); + setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); + setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); } setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); @@ -675,16 +676,16 @@ // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) { - setOperationAction(ISD::AND, (MVT::ValueType)VT, Promote); - AddPromotedToType (ISD::AND, (MVT::ValueType)VT, MVT::v2i64); - setOperationAction(ISD::OR, (MVT::ValueType)VT, Promote); - AddPromotedToType (ISD::OR, (MVT::ValueType)VT, MVT::v2i64); - setOperationAction(ISD::XOR, (MVT::ValueType)VT, Promote); - AddPromotedToType (ISD::XOR, (MVT::ValueType)VT, MVT::v2i64); - setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Promote); - AddPromotedToType (ISD::LOAD, (MVT::ValueType)VT, MVT::v2i64); - setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote); - AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v2i64); + setOperationAction(ISD::AND, (MVT::SimpleValueType)VT, Promote); + AddPromotedToType (ISD::AND, (MVT::SimpleValueType)VT, MVT::v2i64); + setOperationAction(ISD::OR, (MVT::SimpleValueType)VT, Promote); + AddPromotedToType (ISD::OR, (MVT::SimpleValueType)VT, MVT::v2i64); + setOperationAction(ISD::XOR, (MVT::SimpleValueType)VT, Promote); + AddPromotedToType (ISD::XOR, (MVT::SimpleValueType)VT, MVT::v2i64); + setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Promote); + AddPromotedToType (ISD::LOAD, (MVT::SimpleValueType)VT, MVT::v2i64); + setOperationAction(ISD::SELECT, (MVT::SimpleValueType)VT, Promote); + AddPromotedToType (ISD::SELECT, (MVT::SimpleValueType)VT, MVT::v2i64); } setTruncStoreAction(MVT::f64, MVT::f32, Expand); @@ -743,8 +744,7 @@ } -MVT::ValueType -X86TargetLowering::getSetCCResultType(const SDOperand &) const { +MVT X86TargetLowering::getSetCCResultType(const SDOperand &) const { return MVT::i8; } @@ -792,7 +792,7 @@ /// and store operations as a result of memset, memcpy, and memmove /// lowering. It returns MVT::iAny if SelectionDAG should be responsible for /// determining it. -MVT::ValueType +MVT X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align, bool isSrcConst, bool isSrcStr) const { if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16) @@ -948,7 +948,7 @@ // Copy all of the result registers out of their specified physreg. for (unsigned i = 0; i != RVLocs.size(); ++i) { - MVT::ValueType CopyVT = RVLocs[i].getValVT(); + MVT CopyVT = RVLocs[i].getValVT(); // If this is a call to a function that returns an fp value on the floating // point stack, but where we prefer to use the value in xmm registers, copy @@ -1123,7 +1123,7 @@ // changed with more analysis. // In case of tail call optimization mark all arguments mutable. Since they // could be overwritten by lowering of arguments in case of a tail call. - int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8, + int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8, VA.getLocMemOffset(), isImmutable); SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy()); if (Flags.isByVal()) @@ -1172,7 +1172,7 @@ LastVal = VA.getValNo(); if (VA.isRegLoc()) { - MVT::ValueType RegVT = VA.getLocVT(); + MVT RegVT = VA.getLocVT(); TargetRegisterClass *RC; if (RegVT == MVT::i32) RC = X86::GR32RegisterClass; @@ -1182,10 +1182,10 @@ RC = X86::FR32RegisterClass; else if (RegVT == MVT::f64) RC = X86::FR64RegisterClass; - else if (MVT::isVector(RegVT) && MVT::getSizeInBits(RegVT) == 128) + else if (RegVT.isVector() && RegVT.getSizeInBits() == 128) RC = X86::VR128RegisterClass; - else if (MVT::isVector(RegVT)) { - assert(MVT::getSizeInBits(RegVT) == 64); + else if (RegVT.isVector()) { + assert(RegVT.getSizeInBits() == 64); if (!Is64Bit) RC = X86::VR64RegisterClass; // MMX values are passed in MMXs. else { @@ -1221,7 +1221,7 @@ // Handle MMX values passed in GPRs. if (Is64Bit && RegVT != VA.getLocVT()) { - if (MVT::getSizeInBits(RegVT) == 64 && RC == X86::GR64RegisterClass) + if (RegVT.getSizeInBits() == 64 && RC == X86::GR64RegisterClass) ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue); else if (RC == X86::VR128RegisterClass) { ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i64, ArgValue, @@ -1408,7 +1408,7 @@ if (!IsTailCall || FPDiff==0) return Chain; // Adjust the Return address stack slot. - MVT::ValueType VT = getPointerTy(); + MVT VT = getPointerTy(); OutRetAddr = getReturnAddressFrameIndex(DAG); // Load the "old" Return address. OutRetAddr = DAG.getLoad(VT, Chain,OutRetAddr, NULL, 0); @@ -1427,7 +1427,7 @@ int SlotSize = Is64Bit ? 8 : 4; int NewReturnAddrFI = MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize); - MVT::ValueType VT = Is64Bit ? MVT::i64 : MVT::i32; + MVT VT = Is64Bit ? MVT::i64 : MVT::i32; SDOperand NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT); Chain = DAG.getStore(Chain, RetAddrFrIdx, NewRetAddrFrIdx, PseudoSourceValue::getFixedStack(), NewReturnAddrFI); @@ -1514,8 +1514,8 @@ if (VA.isRegLoc()) { if (Is64Bit) { - MVT::ValueType RegVT = VA.getLocVT(); - if (MVT::isVector(RegVT) && MVT::getSizeInBits(RegVT) == 64) + MVT RegVT = VA.getLocVT(); + if (RegVT.isVector() && RegVT.getSizeInBits() == 64) switch (VA.getLocReg()) { default: break; @@ -1630,7 +1630,7 @@ cast(FlagsOp)->getArgFlags(); // Create frame index. int32_t Offset = VA.getLocMemOffset()+FPDiff; - uint32_t OpSize = (MVT::getSizeInBits(VA.getLocVT())+7)/8; + uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset); FIN = DAG.getFrameIndex(FI, getPointerTy()); @@ -2567,9 +2567,9 @@ static SDOperand CommuteVectorShuffle(SDOperand Op, SDOperand &V1, SDOperand &V2, SDOperand &Mask, SelectionDAG &DAG) { - MVT::ValueType VT = Op.getValueType(); - MVT::ValueType MaskVT = Mask.getValueType(); - MVT::ValueType EltVT = MVT::getVectorElementType(MaskVT); + MVT VT = Op.getValueType(); + MVT MaskVT = Mask.getValueType(); + MVT EltVT = MaskVT.getVectorElementType(); unsigned NumElems = Mask.getNumOperands(); SmallVector MaskVec; @@ -2596,8 +2596,8 @@ /// the two vector operands have swapped position. static SDOperand CommuteVectorShuffleMask(SDOperand Mask, SelectionDAG &DAG) { - MVT::ValueType MaskVT = Mask.getValueType(); - MVT::ValueType EltVT = MVT::getVectorElementType(MaskVT); + MVT MaskVT = Mask.getValueType(); + MVT EltVT = MaskVT.getVectorElementType(); unsigned NumElems = Mask.getNumOperands(); SmallVector MaskVec; for (unsigned i = 0; i != NumElems; ++i) { @@ -2756,14 +2756,13 @@ /// getZeroVector - Returns a vector of specified type with all zero elements. /// -static SDOperand getZeroVector(MVT::ValueType VT, bool HasSSE2, - SelectionDAG &DAG) { - assert(MVT::isVector(VT) && "Expected a vector type"); +static SDOperand getZeroVector(MVT VT, bool HasSSE2, SelectionDAG &DAG) { + assert(VT.isVector() && "Expected a vector type"); // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest // type. This ensures they get CSE'd. SDOperand Vec; - if (MVT::getSizeInBits(VT) == 64) { // MMX + if (VT.getSizeInBits() == 64) { // MMX SDOperand Cst = DAG.getTargetConstant(0, MVT::i32); Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst); } else if (HasSSE2) { // SSE2 @@ -2778,14 +2777,14 @@ /// getOnesVector - Returns a vector of specified type with all bits set. /// -static SDOperand getOnesVector(MVT::ValueType VT, SelectionDAG &DAG) { - assert(MVT::isVector(VT) && "Expected a vector type"); +static SDOperand getOnesVector(MVT VT, SelectionDAG &DAG) { + assert(VT.isVector() && "Expected a vector type"); // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest // type. This ensures they get CSE'd. SDOperand Cst = DAG.getTargetConstant(~0U, MVT::i32); SDOperand Vec; - if (MVT::getSizeInBits(VT) == 64) // MMX + if (VT.getSizeInBits() == 64) // MMX Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst); else // SSE Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst); @@ -2822,8 +2821,8 @@ /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd /// operation of specified width. static SDOperand getMOVLMask(unsigned NumElems, SelectionDAG &DAG) { - MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems); - MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT); + MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); + MVT BaseVT = MaskVT.getVectorElementType(); SmallVector MaskVec; MaskVec.push_back(DAG.getConstant(NumElems, BaseVT)); @@ -2835,8 +2834,8 @@ /// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation /// of specified width. static SDOperand getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) { - MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems); - MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT); + MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); + MVT BaseVT = MaskVT.getVectorElementType(); SmallVector MaskVec; for (unsigned i = 0, e = NumElems/2; i != e; ++i) { MaskVec.push_back(DAG.getConstant(i, BaseVT)); @@ -2848,8 +2847,8 @@ /// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation /// of specified width. static SDOperand getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) { - MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems); - MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT); + MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); + MVT BaseVT = MaskVT.getVectorElementType(); unsigned Half = NumElems/2; SmallVector MaskVec; for (unsigned i = 0; i != Half; ++i) { @@ -2864,8 +2863,8 @@ /// elements in place. static SDOperand getSwapEltZeroMask(unsigned NumElems, unsigned DestElt, SelectionDAG &DAG) { - MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems); - MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT); + MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); + MVT BaseVT = MaskVT.getVectorElementType(); SmallVector MaskVec; // Element #0 of the result gets the elt we are replacing. MaskVec.push_back(DAG.getConstant(DestElt, BaseVT)); @@ -2876,8 +2875,8 @@ /// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32. static SDOperand PromoteSplat(SDOperand Op, SelectionDAG &DAG, bool HasSSE2) { - MVT::ValueType PVT = HasSSE2 ? MVT::v4i32 : MVT::v4f32; - MVT::ValueType VT = Op.getValueType(); + MVT PVT = HasSSE2 ? MVT::v4i32 : MVT::v4f32; + MVT VT = Op.getValueType(); if (PVT == VT) return Op; SDOperand V1 = Op.getOperand(0); @@ -2906,12 +2905,12 @@ static SDOperand getShuffleVectorZeroOrUndef(SDOperand V2, unsigned Idx, bool isZero, bool HasSSE2, SelectionDAG &DAG) { - MVT::ValueType VT = V2.getValueType(); + MVT VT = V2.getValueType(); SDOperand V1 = isZero ? getZeroVector(VT, HasSSE2, DAG) : DAG.getNode(ISD::UNDEF, VT); - unsigned NumElems = MVT::getVectorNumElements(V2.getValueType()); - MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems); - MVT::ValueType EVT = MVT::getVectorElementType(MaskVT); + unsigned NumElems = V2.getValueType().getVectorNumElements(); + MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); + MVT EVT = MaskVT.getVectorElementType(); SmallVector MaskVec; for (unsigned i = 0; i != NumElems; ++i) if (i == Idx) // If this is the insertion idx, put the low elt of V2 here. @@ -3061,11 +3060,11 @@ /// getVShift - Return a vector logical shift node. /// -static SDOperand getVShift(bool isLeft, MVT::ValueType VT, SDOperand SrcOp, +static SDOperand getVShift(bool isLeft, MVT VT, SDOperand SrcOp, unsigned NumBits, SelectionDAG &DAG, const TargetLowering &TLI) { - bool isMMX = MVT::getSizeInBits(VT) == 64; - MVT::ValueType ShVT = isMMX ? MVT::v1i64 : MVT::v2i64; + bool isMMX = VT.getSizeInBits() == 64; + MVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64; unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL; SrcOp = DAG.getNode(ISD::BIT_CONVERT, ShVT, SrcOp); return DAG.getNode(ISD::BIT_CONVERT, VT, @@ -3088,9 +3087,9 @@ return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG); } - MVT::ValueType VT = Op.getValueType(); - MVT::ValueType EVT = MVT::getVectorElementType(VT); - unsigned EVTBits = MVT::getSizeInBits(EVT); + MVT VT = Op.getValueType(); + MVT EVT = VT.getVectorElementType(); + unsigned EVTBits = EVT.getSizeInBits(); unsigned NumElems = Op.getNumOperands(); unsigned NumZero = 0; @@ -3133,8 +3132,8 @@ (!IsAllConstants || Idx == 0)) { if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) { // Handle MMX and SSE both. - MVT::ValueType VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32; - MVT::ValueType VecElts = VT == MVT::v2i64 ? 4 : 2; + MVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32; + unsigned VecElts = VT == MVT::v2i64 ? 4 : 2; // Truncate the value (which may itself be a constant) to i32, and // convert it to a vector with movd (S2V+shuffle to zero extend). @@ -3173,7 +3172,7 @@ // Is it a vector logical left shift? if (NumElems == 2 && Idx == 1 && isZeroNode(Op.getOperand(0)) && !isZeroNode(Op.getOperand(1))) { - unsigned NumBits = MVT::getSizeInBits(VT); + unsigned NumBits = VT.getSizeInBits(); return getVShift(true, VT, DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(1)), NumBits/2, DAG, *this); @@ -3193,8 +3192,8 @@ // Turn it into a shuffle of zero and zero-extended scalar to vector. Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget->hasSSE2(), DAG); - MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems); - MVT::ValueType MaskEVT = MVT::getVectorElementType(MaskVT); + MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); + MVT MaskEVT = MaskVT.getVectorElementType(); SmallVector MaskVec; for (unsigned i = 0; i < NumElems; i++) MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT)); @@ -3273,8 +3272,8 @@ } } - MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems); - MVT::ValueType EVT = MVT::getVectorElementType(MaskVT); + MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); + MVT EVT = MaskVT.getVectorElementType(); SmallVector MaskVec; bool Reverse = (NonZeros & 0x3) == 2; for (unsigned i = 0; i < 2; ++i) @@ -3320,9 +3319,9 @@ SDOperand PermMask, SelectionDAG &DAG, TargetLowering &TLI) { SDOperand NewV; - MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(8); - MVT::ValueType MaskEVT = MVT::getVectorElementType(MaskVT); - MVT::ValueType PtrVT = TLI.getPointerTy(); + MVT MaskVT = MVT::getIntVectorWithNumElements(8); + MVT MaskEVT = MaskVT.getVectorElementType(); + MVT PtrVT = TLI.getPointerTy(); SmallVector MaskElts(PermMask.Val->op_begin(), PermMask.Val->op_end()); @@ -3562,23 +3561,23 @@ /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15> static SDOperand RewriteAsNarrowerShuffle(SDOperand V1, SDOperand V2, - MVT::ValueType VT, + MVT VT, SDOperand PermMask, SelectionDAG &DAG, TargetLowering &TLI) { unsigned NumElems = PermMask.getNumOperands(); unsigned NewWidth = (NumElems == 4) ? 2 : 4; - MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NewWidth); - MVT::ValueType NewVT = MaskVT; - switch (VT) { + MVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth); + MVT NewVT = MaskVT; + switch (VT.getSimpleVT()) { + default: assert(false && "Unexpected!"); case MVT::v4f32: NewVT = MVT::v2f64; break; case MVT::v4i32: NewVT = MVT::v2i64; break; case MVT::v8i16: NewVT = MVT::v4i32; break; case MVT::v16i8: NewVT = MVT::v4i32; break; - default: assert(false && "Unexpected!"); } if (NewWidth == 2) { - if (MVT::isInteger(VT)) + if (VT.isInteger()) NewVT = MVT::v2i64; else NewVT = MVT::v2f64; @@ -3612,9 +3611,9 @@ /// getVZextMovL - Return a zero-extending vector move low node. /// -static SDOperand getVZextMovL(MVT::ValueType VT, MVT::ValueType OpVT, - SDOperand SrcOp, SelectionDAG &DAG, - const X86Subtarget *Subtarget) { +static SDOperand getVZextMovL(MVT VT, MVT OpVT, + SDOperand SrcOp, SelectionDAG &DAG, + const X86Subtarget *Subtarget) { if (VT == MVT::v2f64 || VT == MVT::v4f32) { LoadSDNode *LD = NULL; if (!isScalarLoadToVector(SrcOp.Val, &LD)) @@ -3622,7 +3621,7 @@ if (!LD) { // movssrr and movsdrr do not clear top bits. Try to use movd, movq // instead. - MVT::ValueType EVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; + MVT EVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; if ((EVT != MVT::i64 || Subtarget->is64Bit()) && SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR && SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT && @@ -3647,9 +3646,9 @@ SDOperand V1 = Op.getOperand(0); SDOperand V2 = Op.getOperand(1); SDOperand PermMask = Op.getOperand(2); - MVT::ValueType VT = Op.getValueType(); + MVT VT = Op.getValueType(); unsigned NumElems = PermMask.getNumOperands(); - bool isMMX = MVT::getSizeInBits(VT) == 64; + bool isMMX = VT.getSizeInBits() == 64; bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; bool V1IsSplat = false; @@ -3710,8 +3709,8 @@ if (isShift && ShVal.hasOneUse()) { // If the shifted value has multiple uses, it may be cheaper to use // v_set0 + movlhps or movhlps, etc. - MVT::ValueType EVT = MVT::getVectorElementType(VT); - ShAmt *= MVT::getSizeInBits(EVT); + MVT EVT = VT.getVectorElementType(); + ShAmt *= EVT.getSizeInBits(); return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this); } @@ -3736,8 +3735,8 @@ if (isShift) { // No better options. Use a vshl / vsrl. - MVT::ValueType EVT = MVT::getVectorElementType(VT); - ShAmt *= MVT::getSizeInBits(EVT); + MVT EVT = VT.getVectorElementType(); + ShAmt *= EVT.getSizeInBits(); return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this); } @@ -3821,7 +3820,7 @@ (X86::isPSHUFDMask(PermMask.Val) || X86::isPSHUFHWMask(PermMask.Val) || X86::isPSHUFLWMask(PermMask.Val))) { - MVT::ValueType RVT = VT; + MVT RVT = VT; if (VT == MVT::v4f32) { RVT = MVT::v4i32; Op = DAG.getNode(ISD::VECTOR_SHUFFLE, RVT, @@ -3851,8 +3850,8 @@ // Handle all 4 wide cases with a number of shuffles. if (NumElems == 4 && !isMMX) { // Don't do this for MMX. - MVT::ValueType MaskVT = PermMask.getValueType(); - MVT::ValueType MaskEVT = MVT::getVectorElementType(MaskVT); + MVT MaskVT = PermMask.getValueType(); + MVT MaskEVT = MaskVT.getVectorElementType(); SmallVector, 8> Locs; Locs.reserve(NumElems); SmallVector Mask1(NumElems, @@ -3959,14 +3958,14 @@ SDOperand X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDOperand Op, SelectionDAG &DAG) { - MVT::ValueType VT = Op.getValueType(); - if (MVT::getSizeInBits(VT) == 8) { + MVT VT = Op.getValueType(); + if (VT.getSizeInBits() == 8) { SDOperand Extract = DAG.getNode(X86ISD::PEXTRB, MVT::i32, Op.getOperand(0), Op.getOperand(1)); SDOperand Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract, DAG.getValueType(VT)); return DAG.getNode(ISD::TRUNCATE, VT, Assert); - } else if (MVT::getSizeInBits(VT) == 16) { + } else if (VT.getSizeInBits() == 16) { SDOperand Extract = DAG.getNode(X86ISD::PEXTRW, MVT::i32, Op.getOperand(0), Op.getOperand(1)); SDOperand Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract, @@ -4003,9 +4002,9 @@ return Res; } - MVT::ValueType VT = Op.getValueType(); + MVT VT = Op.getValueType(); // TODO: handle v16i8. - if (MVT::getSizeInBits(VT) == 16) { + if (VT.getSizeInBits() == 16) { SDOperand Vec = Op.getOperand(0); unsigned Idx = cast(Op.getOperand(1))->getValue(); if (Idx == 0) @@ -4014,27 +4013,27 @@ DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Vec), Op.getOperand(1))); // Transform it so it match pextrw which produces a 32-bit result. - MVT::ValueType EVT = (MVT::ValueType)(VT+1); + MVT EVT = (MVT::SimpleValueType)(VT.getSimpleVT()+1); SDOperand Extract = DAG.getNode(X86ISD::PEXTRW, EVT, Op.getOperand(0), Op.getOperand(1)); SDOperand Assert = DAG.getNode(ISD::AssertZext, EVT, Extract, DAG.getValueType(VT)); return DAG.getNode(ISD::TRUNCATE, VT, Assert); - } else if (MVT::getSizeInBits(VT) == 32) { + } else if (VT.getSizeInBits() == 32) { unsigned Idx = cast(Op.getOperand(1))->getValue(); if (Idx == 0) return Op; // SHUFPS the element to the lowest double word, then movss. - MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4); + MVT MaskVT = MVT::getIntVectorWithNumElements(4); SmallVector IdxVec; IdxVec. - push_back(DAG.getConstant(Idx, MVT::getVectorElementType(MaskVT))); + push_back(DAG.getConstant(Idx, MaskVT.getVectorElementType())); IdxVec. - push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT))); + push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType())); IdxVec. - push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT))); + push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType())); IdxVec. - push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT))); + push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType())); SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &IdxVec[0], IdxVec.size()); SDOperand Vec = Op.getOperand(0); @@ -4042,7 +4041,7 @@ Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask); return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec, DAG.getIntPtrConstant(0)); - } else if (MVT::getSizeInBits(VT) == 64) { + } else if (VT.getSizeInBits() == 64) { // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught // to match extract_elt for f64. @@ -4053,11 +4052,11 @@ // UNPCKHPD the element to the lowest double word, then movsd. // Note if the lower 64 bits of the result of the UNPCKHPD is then stored // to a f64mem, the whole operation is folded into a single MOVHPDmr. - MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4); + MVT MaskVT = MVT::getIntVectorWithNumElements(4); SmallVector IdxVec; - IdxVec.push_back(DAG.getConstant(1, MVT::getVectorElementType(MaskVT))); + IdxVec.push_back(DAG.getConstant(1, MaskVT.getVectorElementType())); IdxVec. - push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT))); + push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType())); SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &IdxVec[0], IdxVec.size()); SDOperand Vec = Op.getOperand(0); @@ -4072,15 +4071,15 @@ SDOperand X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDOperand Op, SelectionDAG &DAG){ - MVT::ValueType VT = Op.getValueType(); - MVT::ValueType EVT = MVT::getVectorElementType(VT); + MVT VT = Op.getValueType(); + MVT EVT = VT.getVectorElementType(); SDOperand N0 = Op.getOperand(0); SDOperand N1 = Op.getOperand(1); SDOperand N2 = Op.getOperand(2); - if ((MVT::getSizeInBits(EVT) == 8) || (MVT::getSizeInBits(EVT) == 16)) { - unsigned Opc = (MVT::getSizeInBits(EVT) == 8) ? X86ISD::PINSRB + if ((EVT.getSizeInBits() == 8) || (EVT.getSizeInBits() == 16)) { + unsigned Opc = (EVT.getSizeInBits() == 8) ? X86ISD::PINSRB : X86ISD::PINSRW; // Transform it so it match pinsr{b,w} which expects a GR32 as its second // argument. @@ -4106,8 +4105,8 @@ SDOperand X86TargetLowering::LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) { - MVT::ValueType VT = Op.getValueType(); - MVT::ValueType EVT = MVT::getVectorElementType(VT); + MVT VT = Op.getValueType(); + MVT EVT = VT.getVectorElementType(); if (Subtarget->hasSSE41()) return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG); @@ -4119,7 +4118,7 @@ SDOperand N1 = Op.getOperand(1); SDOperand N2 = Op.getOperand(2); - if (MVT::getSizeInBits(EVT) == 16) { + if (EVT.getSizeInBits() == 16) { // Transform it so it match pinsrw which expects a 16-bit value in a GR32 // as its second argument. if (N1.getValueType() != MVT::i32) @@ -4134,8 +4133,8 @@ SDOperand X86TargetLowering::LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) { SDOperand AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0)); - MVT::ValueType VT = MVT::v2i32; - switch (Op.getValueType()) { + MVT VT = MVT::v2i32; + switch (Op.getValueType().getSimpleVT()) { default: break; case MVT::v16i8: case MVT::v8i16: @@ -4201,7 +4200,7 @@ // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit static SDOperand LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, - const MVT::ValueType PtrVT) { + const MVT PtrVT) { SDOperand InFlag; SDOperand Chain = DAG.getCopyToReg(DAG.getEntryNode(), X86::EBX, DAG.getNode(X86ISD::GlobalBaseReg, @@ -4239,7 +4238,7 @@ // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit static SDOperand LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, - const MVT::ValueType PtrVT) { + const MVT PtrVT) { SDOperand InFlag, Chain; // emit leaq symbol at TLSGD(%rip), %rdi @@ -4271,9 +4270,8 @@ // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or // "local exec" model. -static SDOperand -LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, - const MVT::ValueType PtrVT) { +static SDOperand LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, + const MVT PtrVT) { // Get the Thread Pointer SDOperand ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER, PtrVT); // emit "addl x at ntpoff,%eax" (local exec) or "addl x at indntpoff,%eax" (initial @@ -4346,8 +4344,8 @@ /// take a 2 x i32 value to shift plus a shift amount. SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) { assert(Op.getNumOperands() == 3 && "Not a double-shift!"); - MVT::ValueType VT = Op.getValueType(); - unsigned VTBits = MVT::getSizeInBits(VT); + MVT VT = Op.getValueType(); + unsigned VTBits = VT.getSizeInBits(); bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; SDOperand ShOpLo = Op.getOperand(0); SDOperand ShOpHi = Op.getOperand(1); @@ -4365,7 +4363,7 @@ Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, VT, ShOpHi, ShAmt); } - const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag); + const MVT *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag); SDOperand AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt, DAG.getConstant(VTBits, MVT::i8)); SDOperand Cond = DAG.getNode(X86ISD::CMP, VT, @@ -4411,7 +4409,7 @@ } SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { - MVT::ValueType SrcVT = Op.getOperand(0).getValueType(); + MVT SrcVT = Op.getOperand(0).getValueType(); assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 && "Unknown SINT_TO_FP to lower!"); @@ -4422,7 +4420,7 @@ Subtarget->is64Bit()) return SDOperand(); - unsigned Size = MVT::getSizeInBits(SrcVT)/8; + unsigned Size = SrcVT.getSizeInBits()/8; MachineFunction &MF = DAG.getMachineFunction(); int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size); SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); @@ -4487,11 +4485,11 @@ // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary // stack slot. MachineFunction &MF = DAG.getMachineFunction(); - unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8; + unsigned MemSize = Op.getValueType().getSizeInBits()/8; int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize); SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); unsigned Opc; - switch (Op.getValueType()) { + switch (Op.getValueType().getSimpleVT()) { default: assert(0 && "Invalid FP_TO_SINT to lower!"); case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; @@ -4543,10 +4541,10 @@ } SDOperand X86TargetLowering::LowerFABS(SDOperand Op, SelectionDAG &DAG) { - MVT::ValueType VT = Op.getValueType(); - MVT::ValueType EltVT = VT; - if (MVT::isVector(VT)) - EltVT = MVT::getVectorElementType(VT); + MVT VT = Op.getValueType(); + MVT EltVT = VT; + if (VT.isVector()) + EltVT = VT.getVectorElementType(); std::vector CV; if (EltVT == MVT::f64) { Constant *C = ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63)))); @@ -4568,12 +4566,12 @@ } SDOperand X86TargetLowering::LowerFNEG(SDOperand Op, SelectionDAG &DAG) { - MVT::ValueType VT = Op.getValueType(); - MVT::ValueType EltVT = VT; + MVT VT = Op.getValueType(); + MVT EltVT = VT; unsigned EltNum = 1; - if (MVT::isVector(VT)) { - EltVT = MVT::getVectorElementType(VT); - EltNum = MVT::getVectorNumElements(VT); + if (VT.isVector()) { + EltVT = VT.getVectorElementType(); + EltNum = VT.getVectorNumElements(); } std::vector CV; if (EltVT == MVT::f64) { @@ -4592,7 +4590,7 @@ SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, PseudoSourceValue::getConstantPool(), 0, false, 16); - if (MVT::isVector(VT)) { + if (VT.isVector()) { return DAG.getNode(ISD::BIT_CONVERT, VT, DAG.getNode(ISD::XOR, MVT::v2i64, DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Op.getOperand(0)), @@ -4605,16 +4603,16 @@ SDOperand X86TargetLowering::LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) { SDOperand Op0 = Op.getOperand(0); SDOperand Op1 = Op.getOperand(1); - MVT::ValueType VT = Op.getValueType(); - MVT::ValueType SrcVT = Op1.getValueType(); + MVT VT = Op.getValueType(); + MVT SrcVT = Op1.getValueType(); // If second operand is smaller, extend it first. - if (MVT::getSizeInBits(SrcVT) < MVT::getSizeInBits(VT)) { + if (SrcVT.getSizeInBits() < VT.getSizeInBits()) { Op1 = DAG.getNode(ISD::FP_EXTEND, VT, Op1); SrcVT = VT; } // And if it is bigger, shrink it first. - if (MVT::getSizeInBits(SrcVT) > MVT::getSizeInBits(VT)) { + if (SrcVT.getSizeInBits() > VT.getSizeInBits()) { Op1 = DAG.getNode(ISD::FP_ROUND, VT, Op1, DAG.getIntPtrConstant(1)); SrcVT = VT; } @@ -4641,7 +4639,7 @@ SDOperand SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1); // Shift sign bit right or left if the two operands have different types. - if (MVT::getSizeInBits(SrcVT) > MVT::getSizeInBits(VT)) { + if (SrcVT.getSizeInBits() > VT.getSizeInBits()) { // Op0 is MVT::f32, Op1 is MVT::f64. SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2f64, SignBit); SignBit = DAG.getNode(X86ISD::FSRL, MVT::v2f64, SignBit, @@ -4680,7 +4678,7 @@ SDOperand Op1 = Op.getOperand(1); SDOperand CC = Op.getOperand(2); ISD::CondCode SetCCOpcode = cast(CC)->get(); - bool isFP = MVT::isFloatingPoint(Op.getOperand(1).getValueType()); + bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); unsigned X86CC; if (translateX86CC(cast(CC)->get(), isFP, X86CC, @@ -4728,10 +4726,10 @@ SDOperand Cmp = Cond.getOperand(1); unsigned Opc = Cmp.getOpcode(); - MVT::ValueType VT = Op.getValueType(); + MVT VT = Op.getValueType(); bool IllegalFPCMov = false; - if (MVT::isFloatingPoint(VT) && !MVT::isVector(VT) && + if (VT.isFloatingPoint() && !VT.isVector() && !isScalarFPTypeInSSEReg(VT)) // FPStack? IllegalFPCMov = !hasFPCMov(cast(CC)->getSignExtended()); @@ -4748,7 +4746,7 @@ Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8)); } - const MVT::ValueType *VTs = DAG.getNodeValueTypes(Op.getValueType(), + const MVT *VTs = DAG.getNodeValueTypes(Op.getValueType(), MVT::Flag); SmallVector Ops; // X86ISD::CMOV means set the result (which is operand 1) to the RHS if @@ -4812,8 +4810,8 @@ SDOperand Flag; - MVT::ValueType IntPtr = getPointerTy(); - MVT::ValueType SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32; + MVT IntPtr = getPointerTy(); + MVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32; Chain = DAG.getCopyToReg(Chain, X86::EAX, Size, Flag); Flag = Chain.getValue(1); @@ -4828,7 +4826,7 @@ Chain = DAG.getCopyFromReg(Chain, X86StackPtr, SPTy).getValue(1); - std::vector Tys; + std::vector Tys; Tys.push_back(SPTy); Tys.push_back(MVT::Other); SDOperand Ops1[2] = { Chain.getValue(0), Chain }; @@ -4855,7 +4853,7 @@ ConstantSDNode *V = dyn_cast(Src); if (const char *bzeroEntry = V && V->isNullValue() ? Subtarget->getBZeroEntry() : 0) { - MVT::ValueType IntPtr = getPointerTy(); + MVT IntPtr = getPointerTy(); const Type *IntPtrTy = getTargetData()->getIntPtrType(); TargetLowering::ArgListTy Args; TargetLowering::ArgListEntry Entry; @@ -4877,7 +4875,7 @@ uint64_t SizeVal = ConstantSize->getValue(); SDOperand InFlag(0, 0); - MVT::ValueType AVT; + MVT AVT; SDOperand Count; ConstantSDNode *ValC = dyn_cast(Src); unsigned BytesLeft = 0; @@ -4912,7 +4910,7 @@ } if (AVT > MVT::i8) { - unsigned UBytes = MVT::getSizeInBits(AVT) / 8; + unsigned UBytes = AVT.getSizeInBits() / 8; Count = DAG.getIntPtrConstant(SizeVal / UBytes); BytesLeft = SizeVal % UBytes; } @@ -4944,7 +4942,7 @@ if (TwoRepStos) { InFlag = Chain.getValue(1); Count = Size; - MVT::ValueType CVT = Count.getValueType(); + MVT CVT = Count.getValueType(); SDOperand Left = DAG.getNode(ISD::AND, CVT, Count, DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT)); Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX, @@ -4959,8 +4957,8 @@ } else if (BytesLeft) { // Handle the last 1 - 7 bytes. unsigned Offset = SizeVal - BytesLeft; - MVT::ValueType AddrVT = Dst.getValueType(); - MVT::ValueType SizeVT = Size.getValueType(); + MVT AddrVT = Dst.getValueType(); + MVT SizeVT = Size.getValueType(); Chain = DAG.getMemset(Chain, DAG.getNode(ISD::ADD, AddrVT, Dst, @@ -4992,7 +4990,7 @@ if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold()) return SDOperand(); - MVT::ValueType AVT; + MVT AVT; unsigned BytesLeft = 0; if (Align >= 8 && Subtarget->is64Bit()) AVT = MVT::i64; @@ -5003,7 +5001,7 @@ else AVT = MVT::i8; - unsigned UBytes = MVT::getSizeInBits(AVT) / 8; + unsigned UBytes = AVT.getSizeInBits() / 8; unsigned CountVal = SizeVal / UBytes; SDOperand Count = DAG.getIntPtrConstant(CountVal); BytesLeft = SizeVal % UBytes; @@ -5031,9 +5029,9 @@ if (BytesLeft) { // Handle the last 1 - 7 bytes. unsigned Offset = SizeVal - BytesLeft; - MVT::ValueType DstVT = Dst.getValueType(); - MVT::ValueType SrcVT = Src.getValueType(); - MVT::ValueType SizeVT = Size.getValueType(); + MVT DstVT = Dst.getValueType(); + MVT SrcVT = Src.getValueType(); + MVT SizeVT = Size.getValueType(); Results.push_back(DAG.getMemcpy(Chain, DAG.getNode(ISD::ADD, DstVT, Dst, DAG.getConstant(Offset, DstVT)), @@ -5280,7 +5278,7 @@ return SDOperand(); unsigned NewIntNo = 0; - MVT::ValueType ShAmtVT = MVT::v4i32; + MVT ShAmtVT = MVT::v4i32; switch (IntNo) { case Intrinsic::x86_sse2_pslli_w: NewIntNo = Intrinsic::x86_sse2_psll_w; @@ -5338,7 +5336,7 @@ break; } } - MVT::ValueType VT = Op.getValueType(); + MVT VT = Op.getValueType(); ShAmt = DAG.getNode(ISD::BIT_CONVERT, VT, DAG.getNode(ISD::SCALAR_TO_VECTOR, ShAmtVT, ShAmt)); return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT, @@ -5554,7 +5552,7 @@ const TargetMachine &TM = MF.getTarget(); const TargetFrameInfo &TFI = *TM.getFrameInfo(); unsigned StackAlignment = TFI.getStackAlignment(); - MVT::ValueType VT = Op.getValueType(); + MVT VT = Op.getValueType(); // Save FP Control Word to stack slot int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment); @@ -5586,14 +5584,14 @@ DAG.getConstant(3, MVT::i16)); - return DAG.getNode((MVT::getSizeInBits(VT) < 16 ? + return DAG.getNode((VT.getSizeInBits() < 16 ? ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal); } SDOperand X86TargetLowering::LowerCTLZ(SDOperand Op, SelectionDAG &DAG) { - MVT::ValueType VT = Op.getValueType(); - MVT::ValueType OpVT = VT; - unsigned NumBits = MVT::getSizeInBits(VT); + MVT VT = Op.getValueType(); + MVT OpVT = VT; + unsigned NumBits = VT.getSizeInBits(); Op = Op.getOperand(0); if (VT == MVT::i8) { @@ -5623,9 +5621,9 @@ } SDOperand X86TargetLowering::LowerCTTZ(SDOperand Op, SelectionDAG &DAG) { - MVT::ValueType VT = Op.getValueType(); - MVT::ValueType OpVT = VT; - unsigned NumBits = MVT::getSizeInBits(VT); + MVT VT = Op.getValueType(); + MVT OpVT = VT; + unsigned NumBits = VT.getSizeInBits(); Op = Op.getOperand(0); if (VT == MVT::i8) { @@ -5651,10 +5649,12 @@ } SDOperand X86TargetLowering::LowerLCS(SDOperand Op, SelectionDAG &DAG) { - MVT::ValueType T = cast(Op.Val)->getVT(); + MVT T = cast(Op.Val)->getVT(); unsigned Reg = 0; unsigned size = 0; - switch(T) { + switch(T.getSimpleVT()) { + default: + assert(false && "Invalid value type!"); case MVT::i8: Reg = X86::AL; size = 1; break; case MVT::i16: Reg = X86::AX; size = 2; break; case MVT::i32: Reg = X86::EAX; size = 4; break; @@ -5680,7 +5680,7 @@ } SDNode* X86TargetLowering::ExpandATOMIC_LCS(SDNode* Op, SelectionDAG &DAG) { - MVT::ValueType T = cast(Op)->getVT(); + MVT T = cast(Op)->getVT(); assert (T == MVT::i64 && "Only know how to expand i64 CAS"); SDOperand cpInL, cpInH; cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(3), @@ -5716,7 +5716,7 @@ } SDNode* X86TargetLowering::ExpandATOMIC_LSS(SDNode* Op, SelectionDAG &DAG) { - MVT::ValueType T = cast(Op)->getVT(); + MVT T = cast(Op)->getVT(); assert (T == MVT::i32 && "Only know how to expand i32 LSS"); SDOperand negOp = DAG.getNode(ISD::SUB, T, DAG.getConstant(0, T), Op->getOperand(2)); @@ -5900,12 +5900,11 @@ return Subtarget->is64Bit() || NumBits1 < 64; } -bool X86TargetLowering::isTruncateFree(MVT::ValueType VT1, - MVT::ValueType VT2) const { - if (!MVT::isInteger(VT1) || !MVT::isInteger(VT2)) +bool X86TargetLowering::isTruncateFree(MVT VT1, MVT VT2) const { + if (!VT1.isInteger() || !VT2.isInteger()) return false; - unsigned NumBits1 = MVT::getSizeInBits(VT1); - unsigned NumBits2 = MVT::getSizeInBits(VT2); + unsigned NumBits1 = VT1.getSizeInBits(); + unsigned NumBits2 = VT2.getSizeInBits(); if (NumBits1 <= NumBits2) return false; return Subtarget->is64Bit() || NumBits1 < 64; @@ -5916,9 +5915,9 @@ /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values /// are assumed to be legal. bool -X86TargetLowering::isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const { +X86TargetLowering::isShuffleMaskLegal(SDOperand Mask, MVT VT) const { // Only do shuffles on 128-bit vector types for now. - if (MVT::getSizeInBits(VT) == 64) return false; + if (VT.getSizeInBits() == 64) return false; return (Mask.Val->getNumOperands() <= 4 || isIdentityMask(Mask.Val) || isIdentityMask(Mask.Val, true) || @@ -5932,11 +5931,10 @@ bool X86TargetLowering::isVectorClearMaskLegal(const std::vector &BVOps, - MVT::ValueType EVT, - SelectionDAG &DAG) const { + MVT EVT, SelectionDAG &DAG) const { unsigned NumElts = BVOps.size(); // Only do shuffles on 128-bit vector types for now. - if (MVT::getSizeInBits(EVT) * NumElts == 64) return false; + if (EVT.getSizeInBits() * NumElts == 64) return false; if (NumElts == 2) return true; if (NumElts == 4) { return (isMOVLMask(&BVOps[0], 4) || @@ -6342,7 +6340,7 @@ } static bool EltsFromConsecutiveLoads(SDNode *N, SDOperand PermMask, - unsigned NumElems, MVT::ValueType EVT, + unsigned NumElems, MVT EVT, SDNode *&Base, SelectionDAG &DAG, MachineFrameInfo *MFI, const TargetLowering &TLI) { @@ -6370,7 +6368,7 @@ continue; if (!TLI.isConsecutiveLoad(Elt.Val, Base, - MVT::getSizeInBits(EVT)/8, i, MFI)) + EVT.getSizeInBits()/8, i, MFI)) return false; } return true; @@ -6383,8 +6381,8 @@ static SDOperand PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, const TargetLowering &TLI) { MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); - MVT::ValueType VT = N->getValueType(0); - MVT::ValueType EVT = MVT::getVectorElementType(VT); + MVT VT = N->getValueType(0); + MVT EVT = VT.getVectorElementType(); SDOperand PermMask = N->getOperand(2); unsigned NumElems = PermMask.getNumOperands(); SDNode *Base = NULL; @@ -6411,8 +6409,8 @@ if (NumOps == 1) return SDOperand(); - MVT::ValueType VT = N->getValueType(0); - MVT::ValueType EVT = MVT::getVectorElementType(VT); + MVT VT = N->getValueType(0); + MVT EVT = VT.getVectorElementType(); if ((EVT != MVT::i64 && EVT != MVT::f64) || Subtarget->is64Bit()) // We are looking for load i64 and zero extend. We want to transform // it before legalizer has a chance to expand it. Also look for i64 @@ -6523,8 +6521,8 @@ // A preferable solution to the general problem is to figure out the right // places to insert EMMS. This qualifies as a quick hack. StoreSDNode *St = cast(N); - if (MVT::isVector(St->getValue().getValueType()) && - MVT::getSizeInBits(St->getValue().getValueType()) == 64 && + if (St->getValue().getValueType().isVector() && + St->getValue().getValueType().getSizeInBits() == 64 && isa(St->getValue()) && !cast(St->getValue())->isVolatile() && St->getChain().hasOneUse() && !St->isVolatile()) { @@ -6569,7 +6567,7 @@ // Otherwise, lower to two 32-bit copies. SDOperand LoAddr = Ld->getBasePtr(); SDOperand HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr, - DAG.getConstant(MVT::i32, 4)); + DAG.getConstant(4, MVT::i32)); SDOperand LoLd = DAG.getLoad(MVT::i32, Ld->getChain(), LoAddr, Ld->getSrcValue(), Ld->getSrcValueOffset(), @@ -6589,7 +6587,7 @@ LoAddr = St->getBasePtr(); HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr, - DAG.getConstant(MVT::i32, 4)); + DAG.getConstant(4, MVT::i32)); SDOperand LoSt = DAG.getStore(NewChain, LoLd, LoAddr, St->getSrcValue(), St->getSrcValueOffset(), @@ -6683,10 +6681,10 @@ /// with another that has more specific requirements based on the type of the /// corresponding operand. const char *X86TargetLowering:: -LowerXConstraint(MVT::ValueType ConstraintVT) const { +LowerXConstraint(MVT ConstraintVT) const { // FP X constraints get lowered to SSE1/2 registers if available, otherwise // 'f' like normal targets. - if (MVT::isFloatingPoint(ConstraintVT)) { + if (ConstraintVT.isFloatingPoint()) { if (Subtarget->hasSSE2()) return "Y"; if (Subtarget->hasSSE1()) @@ -6779,7 +6777,7 @@ std::vector X86TargetLowering:: getRegClassForInlineAsmConstraint(const std::string &Constraint, - MVT::ValueType VT) const { + MVT VT) const { if (Constraint.size() == 1) { // FIXME: not handling fp-stack yet! switch (Constraint[0]) { // GCC X86 Constraint Letters @@ -6807,7 +6805,7 @@ std::pair X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, - MVT::ValueType VT) const { + MVT VT) const { // First, see if this is a constraint that directly corresponds to an LLVM // register class. if (Constraint.size() == 1) { @@ -6843,8 +6841,8 @@ // FALL THROUGH. case 'x': // SSE_REGS if SSE1 allowed if (!Subtarget->hasSSE1()) break; - - switch (VT) { + + switch (VT.getSimpleVT()) { default: break; // Scalar SSE types. case MVT::f32: Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Fri Jun 6 07:08:01 2008 @@ -345,8 +345,8 @@ /// lowering. It returns MVT::iAny if SelectionDAG should be responsible for /// determining it. virtual - MVT::ValueType getOptimalMemOpType(uint64_t Size, unsigned Align, - bool isSrcConst, bool isSrcStr) const; + MVT getOptimalMemOpType(uint64_t Size, unsigned Align, + bool isSrcConst, bool isSrcStr) const; /// LowerOperation - Provide custom lowering hooks for some operations. /// @@ -369,7 +369,7 @@ virtual const char *getTargetNodeName(unsigned Opcode) const; /// getSetCCResultType - Return the ISD::SETCC ValueType - virtual MVT::ValueType getSetCCResultType(const SDOperand &) const; + virtual MVT getSetCCResultType(const SDOperand &) const; /// computeMaskedBitsForTargetNode - Determine which of the bits specified /// in Mask are known to be either zero or one and return them in the @@ -390,9 +390,9 @@ std::vector getRegClassForInlineAsmConstraint(const std::string &Constraint, - MVT::ValueType VT) const; + MVT VT) const; - virtual const char *LowerXConstraint(MVT::ValueType ConstraintVT) const; + virtual const char *LowerXConstraint(MVT ConstraintVT) const; /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops /// vector. If it is invalid, don't add anything to Ops. @@ -407,7 +407,7 @@ /// error, this returns a register number of 0. std::pair getRegForInlineAsmConstraint(const std::string &Constraint, - MVT::ValueType VT) const; + MVT VT) const; /// isLegalAddressingMode - Return true if the addressing mode represented /// by AM is legal for this target, for a load/store of the specified type. @@ -417,26 +417,25 @@ /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in /// register EAX to i16 by referencing its sub-register AX. virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const; - virtual bool isTruncateFree(MVT::ValueType VT1, MVT::ValueType VT2) const; + virtual bool isTruncateFree(MVT VT1, MVT VT2) const; /// isShuffleMaskLegal - Targets can use this to indicate that they only /// support *some* VECTOR_SHUFFLE operations, those with specific masks. /// By default, if a target supports the VECTOR_SHUFFLE node, all mask /// values are assumed to be legal. - virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const; + virtual bool isShuffleMaskLegal(SDOperand Mask, MVT VT) const; /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is /// used by Targets can use this to indicate if there is a suitable /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant /// pool entry. virtual bool isVectorClearMaskLegal(const std::vector &BVOps, - MVT::ValueType EVT, - SelectionDAG &DAG) const; + MVT EVT, SelectionDAG &DAG) const; /// ShouldShrinkFPConstant - If true, then instruction selection should /// seek to shrink the FP constant of the specified type to a smaller type /// in order to save space and / or reduce runtime. - virtual bool ShouldShrinkFPConstant(MVT::ValueType VT) const { + virtual bool ShouldShrinkFPConstant(MVT VT) const { // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more // expensive than a straight movsd. On the other hand, it's important to // shrink long double fp constant since fldt is very slow. @@ -456,7 +455,7 @@ /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is /// computed in an SSE register, not on the X87 floating point stack. - bool isScalarFPTypeInSSEReg(MVT::ValueType VT) const { + bool isScalarFPTypeInSSEReg(MVT VT) const { return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1 } Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Fri Jun 6 07:08:01 2008 @@ -2193,14 +2193,14 @@ // Emit the load instruction. SDNode *Load = 0; if (FoldedLoad) { - MVT::ValueType VT = *RC->vt_begin(); + MVT VT = *RC->vt_begin(); Load = DAG.getTargetNode(getLoadRegOpcode(RC, RI.getStackAlignment()), VT, MVT::Other, &AddrOps[0], AddrOps.size()); NewNodes.push_back(Load); } // Emit the data processing instruction. - std::vector VTs; + std::vector VTs; const TargetRegisterClass *DstRC = 0; if (TID.getNumDefs() > 0) { const TargetOperandInfo &DstTOI = TID.OpInfo[0]; @@ -2209,7 +2209,7 @@ VTs.push_back(*DstRC->vt_begin()); } for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) { - MVT::ValueType VT = N->getValueType(i); + MVT VT = N->getValueType(i); if (VT != MVT::Other && i >= (unsigned)TID.getNumDefs()) VTs.push_back(VT); } Modified: llvm/trunk/lib/Target/X86/X86IntelAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86IntelAsmPrinter.cpp?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86IntelAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/X86/X86IntelAsmPrinter.cpp Fri Jun 6 07:08:01 2008 @@ -120,7 +120,7 @@ if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) { unsigned Reg = MO.getReg(); if (Modifier && strncmp(Modifier, "subreg", strlen("subreg")) == 0) { - MVT::ValueType VT = (strcmp(Modifier,"subreg64") == 0) ? + MVT VT = (strcmp(Modifier,"subreg64") == 0) ? MVT::i64 : ((strcmp(Modifier, "subreg32") == 0) ? MVT::i32 : ((strcmp(Modifier,"subreg16") == 0) ? MVT::i16 :MVT::i8)); Reg = getX86SubSuperRegister(Reg, VT); Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Fri Jun 6 07:08:01 2008 @@ -946,8 +946,8 @@ } namespace llvm { -unsigned getX86SubSuperRegister(unsigned Reg, MVT::ValueType VT, bool High) { - switch (VT) { +unsigned getX86SubSuperRegister(unsigned Reg, MVT VT, bool High) { + switch (VT.getSimpleVT()) { default: return Reg; case MVT::i8: if (High) { Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.h?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86RegisterInfo.h (original) +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.h Fri Jun 6 07:08:01 2008 @@ -150,7 +150,7 @@ // getX86SubSuperRegister - X86 utility function. It returns the sub or super // register of a specific X86 register. // e.g. getX86SubSuperRegister(X86::EAX, MVT::i16) return X86:AX -unsigned getX86SubSuperRegister(unsigned, MVT::ValueType, bool High=false); +unsigned getX86SubSuperRegister(unsigned, MVT, bool High=false); } // End llvm namespace Modified: llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp Fri Jun 6 07:08:01 2008 @@ -333,11 +333,11 @@ /// Return true if any changes are made. static bool OptimizeNoopCopyExpression(CastInst *CI, const TargetLowering &TLI){ // If this is a noop copy, - MVT::ValueType SrcVT = TLI.getValueType(CI->getOperand(0)->getType()); - MVT::ValueType DstVT = TLI.getValueType(CI->getType()); + MVT SrcVT = TLI.getValueType(CI->getOperand(0)->getType()); + MVT DstVT = TLI.getValueType(CI->getType()); // This is an fp<->int conversion? - if (MVT::isInteger(SrcVT) != MVT::isInteger(DstVT)) + if (SrcVT.isInteger() != DstVT.isInteger()) return false; // If this is an extension, it will be a zero or sign extension, which Modified: llvm/trunk/lib/VMCore/Function.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Function.cpp?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Function.cpp (original) +++ llvm/trunk/lib/VMCore/Function.cpp Fri Jun 6 07:08:01 2008 @@ -336,7 +336,7 @@ std::string Result(Table[id]); for (unsigned i = 0; i < numTys; ++i) if (Tys[i]) - Result += "." + MVT::getValueTypeString(MVT::getValueType(Tys[i])); + Result += "." + MVT::getMVT(Tys[i]).getMVTString(); return Result; } Modified: llvm/trunk/lib/VMCore/ValueTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/ValueTypes.cpp?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/ValueTypes.cpp (original) +++ llvm/trunk/lib/VMCore/ValueTypes.cpp Fri Jun 6 07:08:01 2008 @@ -1,4 +1,4 @@ -//===-- ValueTypes.cpp - Implementation of MVT::ValueType methods ---------===// +//===----------- ValueTypes.cpp - Implementation of MVT methods -----------===// // // The LLVM Compiler Infrastructure // @@ -17,17 +17,17 @@ #include "llvm/DerivedTypes.h" using namespace llvm; -/// MVT::getValueTypeString - This function returns value type as a string, -/// e.g. "i32". -std::string MVT::getValueTypeString(MVT::ValueType VT) { - switch (VT) { +/// getMVTString - This function returns value type as a string, e.g. "i32". +std::string MVT::getMVTString() const { + switch (V) { default: - if (isVector(VT)) - return "v" + utostr(getVectorNumElements(VT)) + - getValueTypeString(getVectorElementType(VT)); - if (isInteger(VT)) - return "i" + utostr(getSizeInBits(VT)); - assert(0 && "Invalid ValueType!"); + if (isVector()) + return "v" + utostr(getVectorNumElements()) + + getVectorElementType().getMVTString(); + if (isInteger()) + return "i" + utostr(getSizeInBits()); + assert(0 && "Invalid MVT!"); + return "?"; case MVT::i1: return "i1"; case MVT::i8: return "i8"; case MVT::i16: return "i16"; @@ -58,19 +58,20 @@ } } -/// MVT::getTypeForValueType - This method returns an LLVM type corresponding -/// to the specified ValueType. Note that this will abort for types that cannot -/// be represented. -const Type *MVT::getTypeForValueType(MVT::ValueType VT) { - switch (VT) { +/// getTypeForMVT - This method returns an LLVM type corresponding to the +/// specified MVT. For integer types, this returns an unsigned type. Note +/// that this will abort for types that cannot be represented. +const Type *MVT::getTypeForMVT() const { + switch (V) { default: - if (isVector(VT)) - return VectorType::get(getTypeForValueType(getVectorElementType(VT)), - getVectorNumElements(VT)); - if (isInteger(VT)) - return IntegerType::get(getSizeInBits(VT)); - assert(0 && "ValueType does not correspond to LLVM type!"); - case MVT::isVoid:return Type::VoidTy; + if (isVector()) + return VectorType::get(getVectorElementType().getTypeForMVT(), + getVectorNumElements()); + if (isInteger()) + return IntegerType::get(getSizeInBits()); + assert(0 && "MVT does not correspond to LLVM type!"); + return Type::VoidTy; + case MVT::isVoid: return Type::VoidTy; case MVT::i1: return Type::Int1Ty; case MVT::i8: return Type::Int8Ty; case MVT::i16: return Type::Int16Ty; @@ -98,18 +99,19 @@ } } -/// MVT::getValueType - Return the value type corresponding to the specified -/// type. This returns all pointers as MVT::iPTR. If HandleUnknown is true, -/// unknown types are returned as Other, otherwise they are invalid. -MVT::ValueType MVT::getValueType(const Type *Ty, bool HandleUnknown) { +/// getMVT - Return the value type corresponding to the specified type. This +/// returns all pointers as MVT::iPTR. If HandleUnknown is true, unknown types +/// are returned as Other, otherwise they are invalid. +MVT MVT::getMVT(const Type *Ty, bool HandleUnknown){ switch (Ty->getTypeID()) { default: if (HandleUnknown) return MVT::Other; assert(0 && "Unknown type!"); + return MVT::isVoid; case Type::VoidTyID: return MVT::isVoid; case Type::IntegerTyID: - return getIntegerType(cast(Ty)->getBitWidth()); + return getIntegerVT(cast(Ty)->getBitWidth()); case Type::FloatTyID: return MVT::f32; case Type::DoubleTyID: return MVT::f64; case Type::X86_FP80TyID: return MVT::f80; @@ -118,8 +120,8 @@ case Type::PointerTyID: return MVT::iPTR; case Type::VectorTyID: { const VectorType *VTy = cast(Ty); - return getVectorType(getValueType(VTy->getElementType(), false), - VTy->getNumElements()); + return getVectorVT(getMVT(VTy->getElementType(), false), + VTy->getNumElements()); } } } Modified: llvm/trunk/lib/VMCore/Verifier.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Verifier.cpp?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Verifier.cpp (original) +++ llvm/trunk/lib/VMCore/Verifier.cpp Fri Jun 6 07:08:01 2008 @@ -1331,7 +1331,7 @@ // Note that "arg#0" is the return type. for (unsigned ArgNo = 0; ArgNo < Count; ++ArgNo) { - MVT::ValueType VT = va_arg(VA, MVT::ValueType); + int VT = va_arg(VA, int); // An MVT::SimpleValueType when non-negative. if (VT == MVT::isVoid && ArgNo > 0) { if (!FTy->isVarArg()) @@ -1351,8 +1351,8 @@ EltTy = VTy->getElementType(); NumElts = VTy->getNumElements(); } - - if ((int)VT < 0) { + + if (VT < 0) { int Match = ~VT; if (Match == 0) { if (Ty != FTy->getReturnType()) { @@ -1403,7 +1403,7 @@ Suffix += "."; if (EltTy != Ty) Suffix += "v" + utostr(NumElts); - Suffix += MVT::getValueTypeString(MVT::getValueType(EltTy)); + Suffix += MVT::getMVT(EltTy).getMVTString(); } else if (VT == MVT::iPTR) { if (!isa(Ty)) { if (ArgNo == 0) @@ -1414,19 +1414,20 @@ "pointer and a pointer is required.", F); break; } - } else if (MVT::isVector(VT)) { + } else if (MVT((MVT::SimpleValueType)VT).isVector()) { + MVT VVT = MVT((MVT::SimpleValueType)VT); // If this is a vector argument, verify the number and type of elements. - if (MVT::getVectorElementType(VT) != MVT::getValueType(EltTy)) { + if (VVT.getVectorElementType() != MVT::getMVT(EltTy)) { CheckFailed("Intrinsic prototype has incorrect vector element type!", F); break; } - if (MVT::getVectorNumElements(VT) != NumElts) { + if (VVT.getVectorNumElements() != NumElts) { CheckFailed("Intrinsic prototype has incorrect number of " "vector elements!",F); break; } - } else if (MVT::getTypeForValueType(VT) != EltTy) { + } else if (MVT((MVT::SimpleValueType)VT).getTypeForMVT() != EltTy) { if (ArgNo == 0) CheckFailed("Intrinsic prototype has incorrect result type!", F); else Modified: llvm/trunk/utils/TableGen/CallingConvEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CallingConvEmitter.cpp?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CallingConvEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/CallingConvEmitter.cpp Fri Jun 6 07:08:01 2008 @@ -26,9 +26,9 @@ // other. for (unsigned i = 0, e = CCs.size(); i != e; ++i) { O << "static bool " << CCs[i]->getName() - << "(unsigned ValNo, MVT::ValueType ValVT,\n" + << "(unsigned ValNo, MVT ValVT,\n" << std::string(CCs[i]->getName().size()+13, ' ') - << "MVT::ValueType LocVT, CCValAssign::LocInfo LocInfo,\n" + << "MVT LocVT, CCValAssign::LocInfo LocInfo,\n" << std::string(CCs[i]->getName().size()+13, ' ') << "ISD::ArgFlagsTy ArgFlags, CCState &State);\n"; } @@ -44,9 +44,9 @@ Counter = 0; O << "\n\nstatic bool " << CC->getName() - << "(unsigned ValNo, MVT::ValueType ValVT,\n" + << "(unsigned ValNo, MVT ValVT,\n" << std::string(CC->getName().size()+13, ' ') - << "MVT::ValueType LocVT, CCValAssign::LocInfo LocInfo,\n" + << "MVT LocVT, CCValAssign::LocInfo LocInfo,\n" << std::string(CC->getName().size()+13, ' ') << "ISD::ArgFlagsTy ArgFlags, CCState &State) {\n"; // Emit all of the actions, in order. @@ -163,12 +163,12 @@ O << Size << ", "; else O << "\n" << IndentStr << " State.getTarget().getTargetData()" - "->getABITypeSize(MVT::getTypeForValueType(LocVT)), "; + "->getABITypeSize(LocVT.getTypeForMVT()), "; if (Align) O << Align; else O << "\n" << IndentStr << " State.getTarget().getTargetData()" - "->getABITypeAlignment(MVT::getTypeForValueType(LocVT))"; + "->getABITypeAlignment(LocVT.getTypeForMVT())"; O << ");\n" << IndentStr << "State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset" << Counter << ", LocVT, LocInfo));\n"; Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp (original) +++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp Fri Jun 6 07:08:01 2008 @@ -27,9 +27,9 @@ /// FilterVTs - Filter a list of VT's according to a predicate. /// template -static std::vector -FilterVTs(const std::vector &InVTs, T Filter) { - std::vector Result; +static std::vector +FilterVTs(const std::vector &InVTs, T Filter) { + std::vector Result; for (unsigned i = 0, e = InVTs.size(); i != e; ++i) if (Filter(InVTs[i])) Result.push_back(InVTs[i]); @@ -41,19 +41,31 @@ FilterEVTs(const std::vector &InVTs, T Filter) { std::vector Result; for (unsigned i = 0, e = InVTs.size(); i != e; ++i) - if (Filter((MVT::ValueType)InVTs[i])) + if (Filter((MVT::SimpleValueType)InVTs[i])) Result.push_back(InVTs[i]); return Result; } static std::vector -ConvertVTs(const std::vector &InVTs) { +ConvertVTs(const std::vector &InVTs) { std::vector Result; for (unsigned i = 0, e = InVTs.size(); i != e; ++i) Result.push_back(InVTs[i]); return Result; } +static inline bool isInteger(MVT::SimpleValueType VT) { + return MVT(VT).isInteger(); +} + +static inline bool isFloatingPoint(MVT::SimpleValueType VT) { + return MVT(VT).isFloatingPoint(); +} + +static inline bool isVector(MVT::SimpleValueType VT) { + return MVT(VT).isVector(); +} + static bool LHSIsSubsetOfRHS(const std::vector &LHS, const std::vector &RHS) { if (LHS.size() > RHS.size()) return false; @@ -66,7 +78,7 @@ /// isExtIntegerVT - Return true if the specified extended value type vector /// contains isInt or an integer value type. namespace llvm { -namespace MVT { +namespace EMVT { bool isExtIntegerInVTs(const std::vector &EVTs) { assert(!EVTs.empty() && "Cannot check for integer in empty ExtVT list!"); return EVTs[0] == isInt || !(FilterEVTs(EVTs, isInteger).empty()); @@ -78,7 +90,7 @@ assert(!EVTs.empty() && "Cannot check for integer in empty ExtVT list!"); return EVTs[0] == isFP || !(FilterEVTs(EVTs, isFloatingPoint).empty()); } -} // end namespace MVT. +} // end namespace EMVT. } // end namespace llvm. @@ -223,23 +235,23 @@ } case SDTCisInt: { // If there is only one integer type supported, this must be it. - std::vector IntVTs = - FilterVTs(CGT.getLegalValueTypes(), MVT::isInteger); + std::vector IntVTs = + FilterVTs(CGT.getLegalValueTypes(), isInteger); // If we found exactly one supported integer type, apply it. if (IntVTs.size() == 1) return NodeToApply->UpdateNodeType(IntVTs[0], TP); - return NodeToApply->UpdateNodeType(MVT::isInt, TP); + return NodeToApply->UpdateNodeType(EMVT::isInt, TP); } case SDTCisFP: { // If there is only one FP type supported, this must be it. - std::vector FPVTs = - FilterVTs(CGT.getLegalValueTypes(), MVT::isFloatingPoint); + std::vector FPVTs = + FilterVTs(CGT.getLegalValueTypes(), isFloatingPoint); // If we found exactly one supported FP type, apply it. if (FPVTs.size() == 1) return NodeToApply->UpdateNodeType(FPVTs[0], TP); - return NodeToApply->UpdateNodeType(MVT::isFP, TP); + return NodeToApply->UpdateNodeType(EMVT::isFP, TP); } case SDTCisSameAs: { TreePatternNode *OtherNode = @@ -255,9 +267,9 @@ !static_cast(NodeToApply->getLeafValue())->getDef() ->isSubClassOf("ValueType")) TP.error(N->getOperator()->getName() + " expects a VT operand!"); - MVT::ValueType VT = + MVT::SimpleValueType VT = getValueType(static_cast(NodeToApply->getLeafValue())->getDef()); - if (!MVT::isInteger(VT)) + if (!isInteger(VT)) TP.error(N->getOperator()->getName() + " VT operand must be integer!"); TreePatternNode *OtherNode = @@ -265,7 +277,7 @@ // It must be integer. bool MadeChange = false; - MadeChange |= OtherNode->UpdateNodeType(MVT::isInt, TP); + MadeChange |= OtherNode->UpdateNodeType(EMVT::isInt, TP); // This code only handles nodes that have one type set. Assert here so // that we can change this if we ever need to deal with multiple value @@ -285,26 +297,26 @@ // This code does not currently handle nodes which have multiple types, // where some types are integer, and some are fp. Assert that this is not // the case. - assert(!(MVT::isExtIntegerInVTs(NodeToApply->getExtTypes()) && - MVT::isExtFloatingPointInVTs(NodeToApply->getExtTypes())) && - !(MVT::isExtIntegerInVTs(BigOperand->getExtTypes()) && - MVT::isExtFloatingPointInVTs(BigOperand->getExtTypes())) && + assert(!(EMVT::isExtIntegerInVTs(NodeToApply->getExtTypes()) && + EMVT::isExtFloatingPointInVTs(NodeToApply->getExtTypes())) && + !(EMVT::isExtIntegerInVTs(BigOperand->getExtTypes()) && + EMVT::isExtFloatingPointInVTs(BigOperand->getExtTypes())) && "SDTCisOpSmallerThanOp does not handle mixed int/fp types!"); - if (MVT::isExtIntegerInVTs(NodeToApply->getExtTypes())) - MadeChange |= BigOperand->UpdateNodeType(MVT::isInt, TP); - else if (MVT::isExtFloatingPointInVTs(NodeToApply->getExtTypes())) - MadeChange |= BigOperand->UpdateNodeType(MVT::isFP, TP); - if (MVT::isExtIntegerInVTs(BigOperand->getExtTypes())) - MadeChange |= NodeToApply->UpdateNodeType(MVT::isInt, TP); - else if (MVT::isExtFloatingPointInVTs(BigOperand->getExtTypes())) - MadeChange |= NodeToApply->UpdateNodeType(MVT::isFP, TP); - - std::vector VTs = CGT.getLegalValueTypes(); - - if (MVT::isExtIntegerInVTs(NodeToApply->getExtTypes())) { - VTs = FilterVTs(VTs, MVT::isInteger); - } else if (MVT::isExtFloatingPointInVTs(NodeToApply->getExtTypes())) { - VTs = FilterVTs(VTs, MVT::isFloatingPoint); + if (EMVT::isExtIntegerInVTs(NodeToApply->getExtTypes())) + MadeChange |= BigOperand->UpdateNodeType(EMVT::isInt, TP); + else if (EMVT::isExtFloatingPointInVTs(NodeToApply->getExtTypes())) + MadeChange |= BigOperand->UpdateNodeType(EMVT::isFP, TP); + if (EMVT::isExtIntegerInVTs(BigOperand->getExtTypes())) + MadeChange |= NodeToApply->UpdateNodeType(EMVT::isInt, TP); + else if (EMVT::isExtFloatingPointInVTs(BigOperand->getExtTypes())) + MadeChange |= NodeToApply->UpdateNodeType(EMVT::isFP, TP); + + std::vector VTs = CGT.getLegalValueTypes(); + + if (EMVT::isExtIntegerInVTs(NodeToApply->getExtTypes())) { + VTs = FilterVTs(VTs, isInteger); + } else if (EMVT::isExtFloatingPointInVTs(NodeToApply->getExtTypes())) { + VTs = FilterVTs(VTs, isFloatingPoint); } else { VTs.clear(); } @@ -331,11 +343,12 @@ getOperandNum(x.SDTCisIntVectorOfSameSize_Info.OtherOperandNum, N, NumResults); if (OtherOperand->hasTypeSet()) { - if (!MVT::isVector(OtherOperand->getTypeNum(0))) + if (!isVector(OtherOperand->getTypeNum(0))) TP.error(N->getOperator()->getName() + " VT operand must be a vector!"); - MVT::ValueType IVT = OtherOperand->getTypeNum(0); - IVT = MVT::getIntVectorWithNumElements(MVT::getVectorNumElements(IVT)); - return NodeToApply->UpdateNodeType(IVT, TP); + MVT IVT = OtherOperand->getTypeNum(0); + unsigned NumElements = IVT.getVectorNumElements(); + IVT = MVT::getIntVectorWithNumElements(NumElements); + return NodeToApply->UpdateNodeType(IVT.getSimpleVT(), TP); } return false; } @@ -344,11 +357,11 @@ getOperandNum(x.SDTCisIntVectorOfSameSize_Info.OtherOperandNum, N, NumResults); if (OtherOperand->hasTypeSet()) { - if (!MVT::isVector(OtherOperand->getTypeNum(0))) + if (!isVector(OtherOperand->getTypeNum(0))) TP.error(N->getOperator()->getName() + " VT operand must be a vector!"); - MVT::ValueType IVT = OtherOperand->getTypeNum(0); - IVT = MVT::getVectorElementType(IVT); - return NodeToApply->UpdateNodeType(IVT, TP); + MVT IVT = OtherOperand->getTypeNum(0); + IVT = IVT.getVectorElementType(); + return NodeToApply->UpdateNodeType(IVT.getSimpleVT(), TP); } return false; } @@ -421,7 +434,7 @@ TreePattern &TP) { assert(!ExtVTs.empty() && "Cannot update node type with empty type vector!"); - if (ExtVTs[0] == MVT::isUnknown || LHSIsSubsetOfRHS(getExtTypes(), ExtVTs)) + if (ExtVTs[0] == EMVT::isUnknown || LHSIsSubsetOfRHS(getExtTypes(), ExtVTs)) return false; if (isTypeCompletelyUnknown() || LHSIsSubsetOfRHS(ExtVTs, getExtTypes())) { setTypes(ExtVTs); @@ -429,10 +442,10 @@ } if (getExtTypeNum(0) == MVT::iPTR) { - if (ExtVTs[0] == MVT::iPTR || ExtVTs[0] == MVT::isInt) + if (ExtVTs[0] == MVT::iPTR || ExtVTs[0] == EMVT::isInt) return false; - if (MVT::isExtIntegerInVTs(ExtVTs)) { - std::vector FVTs = FilterEVTs(ExtVTs, MVT::isInteger); + if (EMVT::isExtIntegerInVTs(ExtVTs)) { + std::vector FVTs = FilterEVTs(ExtVTs, isInteger); if (FVTs.size()) { setTypes(ExtVTs); return true; @@ -440,17 +453,17 @@ } } - if (ExtVTs[0] == MVT::isInt && MVT::isExtIntegerInVTs(getExtTypes())) { + if (ExtVTs[0] == EMVT::isInt && EMVT::isExtIntegerInVTs(getExtTypes())) { assert(hasTypeSet() && "should be handled above!"); - std::vector FVTs = FilterEVTs(getExtTypes(), MVT::isInteger); + std::vector FVTs = FilterEVTs(getExtTypes(), isInteger); if (getExtTypes() == FVTs) return false; setTypes(FVTs); return true; } - if (ExtVTs[0] == MVT::iPTR && MVT::isExtIntegerInVTs(getExtTypes())) { + if (ExtVTs[0] == MVT::iPTR && EMVT::isExtIntegerInVTs(getExtTypes())) { //assert(hasTypeSet() && "should be handled above!"); - std::vector FVTs = FilterEVTs(getExtTypes(), MVT::isInteger); + std::vector FVTs = FilterEVTs(getExtTypes(), isInteger); if (getExtTypes() == FVTs) return false; if (FVTs.size()) { @@ -458,10 +471,10 @@ return true; } } - if (ExtVTs[0] == MVT::isFP && MVT::isExtFloatingPointInVTs(getExtTypes())) { + if (ExtVTs[0] == EMVT::isFP && EMVT::isExtFloatingPointInVTs(getExtTypes())) { assert(hasTypeSet() && "should be handled above!"); std::vector FVTs = - FilterEVTs(getExtTypes(), MVT::isFloatingPoint); + FilterEVTs(getExtTypes(), isFloatingPoint); if (getExtTypes() == FVTs) return false; setTypes(FVTs); @@ -473,12 +486,14 @@ // // Similarly, we should probably set the type here to the intersection of // {isInt|isFP} and ExtVTs - if ((getExtTypeNum(0) == MVT::isInt && MVT::isExtIntegerInVTs(ExtVTs)) || - (getExtTypeNum(0) == MVT::isFP && MVT::isExtFloatingPointInVTs(ExtVTs))){ + if ((getExtTypeNum(0) == EMVT::isInt && + EMVT::isExtIntegerInVTs(ExtVTs)) || + (getExtTypeNum(0) == EMVT::isFP && + EMVT::isExtFloatingPointInVTs(ExtVTs))) { setTypes(ExtVTs); return true; } - if (getExtTypeNum(0) == MVT::isInt && ExtVTs[0] == MVT::iPTR) { + if (getExtTypeNum(0) == EMVT::isInt && ExtVTs[0] == MVT::iPTR) { setTypes(ExtVTs); return true; } @@ -506,9 +521,9 @@ // nodes that are multiply typed. switch (getExtTypeNum(0)) { case MVT::Other: OS << ":Other"; break; - case MVT::isInt: OS << ":isInt"; break; - case MVT::isFP : OS << ":isFP"; break; - case MVT::isUnknown: ; /*OS << ":?";*/ break; + case EMVT::isInt: OS << ":isInt"; break; + case EMVT::isFP : OS << ":isFP"; break; + case EMVT::isUnknown: ; /*OS << ":?";*/ break; case MVT::iPTR: OS << ":iPTR"; break; default: { std::string VTName = llvm::getName(getTypeNum(0)); @@ -672,7 +687,7 @@ static std::vector getImplicitType(Record *R, bool NotRegisters, TreePattern &TP) { // Some common return values - std::vector Unknown(1, MVT::isUnknown); + std::vector Unknown(1, EMVT::isUnknown); std::vector Other(1, MVT::Other); // Check to see if this is a register or a register class... @@ -740,27 +755,29 @@ return UpdateNodeType(getImplicitType(DI->getDef(), NotRegisters, TP),TP); } else if (IntInit *II = dynamic_cast(getLeafValue())) { // Int inits are always integers. :) - bool MadeChange = UpdateNodeType(MVT::isInt, TP); + bool MadeChange = UpdateNodeType(EMVT::isInt, TP); if (hasTypeSet()) { // At some point, it may make sense for this tree pattern to have // multiple types. Assert here that it does not, so we revisit this // code when appropriate. assert(getExtTypes().size() >= 1 && "TreePattern doesn't have a type!"); - MVT::ValueType VT = getTypeNum(0); + MVT::SimpleValueType VT = getTypeNum(0); for (unsigned i = 1, e = getExtTypes().size(); i != e; ++i) assert(getTypeNum(i) == VT && "TreePattern has too many types!"); VT = getTypeNum(0); if (VT != MVT::iPTR) { - unsigned Size = MVT::getSizeInBits(VT); + unsigned Size = MVT(VT).getSizeInBits(); // Make sure that the value is representable for this type. if (Size < 32) { int Val = (II->getValue() << (32-Size)) >> (32-Size); if (Val != II->getValue()) { // If sign-extended doesn't fit, does it fit as unsigned? - unsigned ValueMask = unsigned(MVT::getIntVTBitMask(VT)); - unsigned UnsignedVal = unsigned(II->getValue()); + unsigned ValueMask; + unsigned UnsignedVal; + ValueMask = unsigned(MVT(VT).getIntegerVTBitMask()); + UnsignedVal = unsigned(II->getValue()); if ((ValueMask & UnsignedVal) != UnsignedVal) { TP.error("Integer value '" + itostr(II->getValue())+ @@ -803,10 +820,10 @@ return MadeChange; } else if (const CodeGenIntrinsic *Int = getIntrinsicInfo(CDP)) { bool MadeChange = false; - + // Apply the result type to the node. MadeChange = UpdateNodeType(Int->ArgVTs[0], TP); - + if (getNumChildren() != Int->ArgVTs.size()) TP.error("Intrinsic '" + Int->Name + "' expects " + utostr(Int->ArgVTs.size()-1) + " operands, not " + @@ -816,7 +833,7 @@ MadeChange |= getChild(0)->UpdateNodeType(MVT::iPTR, TP); for (unsigned i = 1, e = getNumChildren(); i != e; ++i) { - MVT::ValueType OpVT = Int->ArgVTs[i]; + MVT::SimpleValueType OpVT = Int->ArgVTs[i]; MadeChange |= getChild(i)->UpdateNodeType(OpVT, TP); MadeChange |= getChild(i)->ApplyTypeConstraints(TP, NotRegisters); } @@ -838,11 +855,11 @@ if (getOperator()->getName() == "vector_shuffle" && getChild(2)->getOperator()->getName() == "build_vector") { TreePatternNode *BV = getChild(2); - const std::vector &LegalVTs + const std::vector &LegalVTs = CDP.getTargetInfo().getLegalValueTypes(); - MVT::ValueType LegalIntVT = MVT::Other; + MVT::SimpleValueType LegalIntVT = MVT::Other; for (unsigned i = 0, e = LegalVTs.size(); i != e; ++i) - if (MVT::isInteger(LegalVTs[i]) && !MVT::isVector(LegalVTs[i])) { + if (isInteger(LegalVTs[i]) && !isVector(LegalVTs[i])) { LegalIntVT = LegalVTs[i]; break; } @@ -874,7 +891,7 @@ MadeChange = UpdateNodeType(VT, TP); } else if (ResultNode->getName() == "unknown") { std::vector VT; - VT.push_back(MVT::isUnknown); + VT.push_back(EMVT::isUnknown); MadeChange = UpdateNodeType(VT, TP); } else { assert(ResultNode->isSubClassOf("RegisterClass") && @@ -903,7 +920,7 @@ TP.error("Instruction '" + getOperator()->getName() + "' expects more operands than were provided."); - MVT::ValueType VT; + MVT::SimpleValueType VT; TreePatternNode *Child = getChild(ChildNo++); if (OperandNode->isSubClassOf("RegisterClass")) { const CodeGenRegisterClass &RC = @@ -915,7 +932,7 @@ } else if (OperandNode->getName() == "ptr_rc") { MadeChange |= Child->UpdateNodeType(MVT::iPTR, TP); } else if (OperandNode->getName() == "unknown") { - MadeChange |= Child->UpdateNodeType(MVT::isUnknown, TP); + MadeChange |= Child->UpdateNodeType(EMVT::isUnknown, TP); } else { assert(0 && "Unknown operand type!"); abort(); Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h (original) +++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h Fri Jun 6 07:08:01 2008 @@ -31,15 +31,15 @@ class CodeGenDAGPatterns; class ComplexPattern; -/// MVT::DAGISelGenValueType - These are some extended forms of MVT::ValueType -/// that we use as lattice values during type inferrence. -namespace MVT { +/// EMVT::DAGISelGenValueType - These are some extended forms of +/// MVT::SimpleValueType that we use as lattice values during type inference. +namespace EMVT { enum DAGISelGenValueType { isFP = MVT::LAST_VALUETYPE, isInt, isUnknown }; - + /// isExtIntegerVT - Return true if the specified extended value type vector /// contains isInt or an integer value type. bool isExtIntegerInVTs(const std::vector &EVTs); @@ -66,7 +66,7 @@ union { // The discriminated union. struct { - MVT::ValueType VT; + unsigned char VT; } SDTCisVT_Info; struct { unsigned OtherOperandNum; @@ -142,7 +142,7 @@ /// patterns), and as such should be ref counted. We currently just leak all /// TreePatternNode objects! class TreePatternNode { - /// The inferred type for this node, or MVT::isUnknown if it hasn't + /// The inferred type for this node, or EMVT::isUnknown if it hasn't /// been determined yet. std::vector Types; @@ -170,10 +170,10 @@ public: TreePatternNode(Record *Op, const std::vector &Ch) : Types(), Operator(Op), Val(0), TransformFn(0), - Children(Ch) { Types.push_back(MVT::isUnknown); } + Children(Ch) { Types.push_back(EMVT::isUnknown); } TreePatternNode(Init *val) // leaf ctor : Types(), Operator(0), Val(val), TransformFn(0) { - Types.push_back(MVT::isUnknown); + Types.push_back(EMVT::isUnknown); } ~TreePatternNode(); @@ -185,15 +185,15 @@ return (Types[0] < MVT::LAST_VALUETYPE) || (Types[0] == MVT::iPTR); } bool isTypeCompletelyUnknown() const { - return Types[0] == MVT::isUnknown; + return Types[0] == EMVT::isUnknown; } bool isTypeDynamicallyResolved() const { return Types[0] == MVT::iPTR; } - MVT::ValueType getTypeNum(unsigned Num) const { + MVT::SimpleValueType getTypeNum(unsigned Num) const { assert(hasTypeSet() && "Doesn't have a type yet!"); assert(Types.size() > Num && "Type num out of range!"); - return (MVT::ValueType)Types[Num]; + return (MVT::SimpleValueType)Types[Num]; } unsigned char getExtTypeNum(unsigned Num) const { assert(Types.size() > Num && "Extended type num out of range!"); @@ -201,7 +201,7 @@ } const std::vector &getExtTypes() const { return Types; } void setTypes(const std::vector &T) { Types = T; } - void removeTypes() { Types = std::vector(1,MVT::isUnknown); } + void removeTypes() { Types = std::vector(1, EMVT::isUnknown); } Init *getLeafValue() const { assert(isLeaf()); return Val; } Record *getOperator() const { assert(!isLeaf()); return Operator; } Modified: llvm/trunk/utils/TableGen/CodeGenIntrinsics.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenIntrinsics.h?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenIntrinsics.h (original) +++ llvm/trunk/utils/TableGen/CodeGenIntrinsics.h Fri Jun 6 07:08:01 2008 @@ -29,13 +29,13 @@ std::string EnumName; // The name of the enum "bswap_i32" std::string GCCBuiltinName;// Name of the corresponding GCC builtin, or "". std::string TargetPrefix; // Target prefix, e.g. "ppc" for t-s intrinsics. - - /// ArgVTs - The MVT::ValueType for each argument type. Note that this list - /// is only populated when in the context of a target .td file. When - /// building Intrinsics.td, this isn't available, because we don't know the - /// target pointer size. - std::vector ArgVTs; - + + /// ArgVTs - The MVT::SimpleValueType for each argument type. Note that + /// this list is only populated when in the context of a target .td file. + /// When building Intrinsics.td, this isn't available, because we don't know + /// the target pointer size. + std::vector ArgVTs; + /// ArgTypeDefs - The records for each argument type. /// std::vector ArgTypeDefs; Modified: llvm/trunk/utils/TableGen/CodeGenRegisters.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenRegisters.h?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenRegisters.h (original) +++ llvm/trunk/utils/TableGen/CodeGenRegisters.h Fri Jun 6 07:08:01 2008 @@ -36,7 +36,7 @@ Record *TheDef; std::string Namespace; std::vector Elements; - std::vector VTs; + std::vector VTs; unsigned SpillSize; unsigned SpillAlignment; int CopyCost; @@ -44,10 +44,10 @@ std::string MethodProtos, MethodBodies; const std::string &getName() const; - const std::vector &getValueTypes() const { return VTs; } + const std::vector &getValueTypes() const {return VTs;} unsigned getNumValueTypes() const { return VTs.size(); } - MVT::ValueType getValueTypeNum(unsigned VTNum) const { + MVT::SimpleValueType getValueTypeNum(unsigned VTNum) const { if (VTNum < VTs.size()) return VTs[VTNum]; assert(0 && "VTNum greater than number of ValueTypes in RegClass!"); Modified: llvm/trunk/utils/TableGen/CodeGenTarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.cpp?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenTarget.cpp (original) +++ llvm/trunk/utils/TableGen/CodeGenTarget.cpp Fri Jun 6 07:08:01 2008 @@ -27,13 +27,13 @@ AsmWriterNum("asmwriternum", cl::init(0), cl::desc("Make -gen-asm-writer emit assembly writer #N")); -/// getValueType - Return the MCV::ValueType that the specified TableGen record -/// corresponds to. -MVT::ValueType llvm::getValueType(Record *Rec) { - return (MVT::ValueType)Rec->getValueAsInt("Value"); +/// getValueType - Return the MVT::SimpleValueType that the specified TableGen +/// record corresponds to. +MVT::SimpleValueType llvm::getValueType(Record *Rec) { + return (MVT::SimpleValueType)Rec->getValueAsInt("Value"); } -std::string llvm::getName(MVT::ValueType T) { +std::string llvm::getName(MVT::SimpleValueType T) { switch (T) { case MVT::Other: return "UNKNOWN"; case MVT::i1: return "MVT::i1"; @@ -69,7 +69,7 @@ } } -std::string llvm::getEnumName(MVT::ValueType T) { +std::string llvm::getEnumName(MVT::SimpleValueType T) { switch (T) { case MVT::Other: return "MVT::Other"; case MVT::i1: return "MVT::i1"; @@ -181,7 +181,7 @@ const CodeGenRegisterClass &RC = RegisterClasses[i]; for (unsigned ei = 0, ee = RC.Elements.size(); ei != ee; ++ei) { if (R == RC.Elements[ei]) { - const std::vector &InVTs = RC.getValueTypes(); + const std::vector &InVTs = RC.getValueTypes(); for (unsigned i = 0, e = InVTs.size(); i != e; ++i) Result.push_back(InVTs[i]); } @@ -231,7 +231,7 @@ unsigned Size = R->getValueAsInt("Size"); Namespace = R->getValueAsString("Namespace"); - SpillSize = Size ? Size : MVT::getSizeInBits(VTs[0]); + SpillSize = Size ? Size : MVT(VTs[0]).getSizeInBits(); SpillAlignment = R->getValueAsInt("Alignment"); CopyCost = R->getValueAsInt("CopyCost"); MethodBodies = R->getValueAsCode("MethodBodies"); @@ -443,7 +443,7 @@ for (unsigned i = 0, e = TypeList->getSize(); i != e; ++i) { Record *TyEl = TypeList->getElementAsRecord(i); assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); - MVT::ValueType VT = getValueType(TyEl->getValueAsDef("VT")); + MVT::SimpleValueType VT = getValueType(TyEl->getValueAsDef("VT")); isOverloaded |= VT == MVT::iAny || VT == MVT::fAny; ArgVTs.push_back(VT); ArgTypeDefs.push_back(TyEl); Modified: llvm/trunk/utils/TableGen/CodeGenTarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.h?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenTarget.h (original) +++ llvm/trunk/utils/TableGen/CodeGenTarget.h Fri Jun 6 07:08:01 2008 @@ -45,12 +45,12 @@ // ComplexPattern attributes. enum CPAttr { CPAttrParentAsRoot }; -/// getValueType - Return the MVT::ValueType that the specified TableGen record -/// corresponds to. -MVT::ValueType getValueType(Record *Rec); +/// getValueType - Return the MVT::SimpleValueType that the specified TableGen +/// record corresponds to. +MVT::SimpleValueType getValueType(Record *Rec); -std::string getName(MVT::ValueType T); -std::string getEnumName(MVT::ValueType T); +std::string getName(MVT::SimpleValueType T); +std::string getEnumName(MVT::SimpleValueType T); /// getQualifiedName - Return the name of the specified record, with a /// namespace qualifier if the record contains one. @@ -64,7 +64,7 @@ mutable std::map Instructions; mutable std::vector Registers; mutable std::vector RegisterClasses; - mutable std::vector LegalValueTypes; + mutable std::vector LegalValueTypes; void ReadRegisters() const; void ReadRegisterClasses() const; void ReadInstructions() const; @@ -121,19 +121,19 @@ return FoundRC; } - /// getRegisterVTs - Find the union of all possible ValueTypes for the + /// getRegisterVTs - Find the union of all possible SimpleValueTypes for the /// specified physical register. std::vector getRegisterVTs(Record *R) const; - const std::vector &getLegalValueTypes() const { + const std::vector &getLegalValueTypes() const { if (LegalValueTypes.empty()) ReadLegalValueTypes(); return LegalValueTypes; } /// isLegalValueType - Return true if the specified value type is natively /// supported by the target (i.e. there are registers that directly hold it). - bool isLegalValueType(MVT::ValueType VT) const { - const std::vector &LegalVTs = getLegalValueTypes(); + bool isLegalValueType(MVT::SimpleValueType VT) const { + const std::vector &LegalVTs = getLegalValueTypes(); for (unsigned i = 0, e = LegalVTs.size(); i != e; ++i) if (LegalVTs[i] == VT) return true; return false; @@ -175,7 +175,7 @@ /// ComplexPattern - ComplexPattern info, corresponding to the ComplexPattern /// tablegen class in TargetSelectionDAG.td class ComplexPattern { - MVT::ValueType Ty; + MVT::SimpleValueType Ty; unsigned NumOperands; std::string SelectFunc; std::vector RootNodes; @@ -185,7 +185,7 @@ ComplexPattern() : NumOperands(0) {}; ComplexPattern(Record *R); - MVT::ValueType getValueType() const { return Ty; } + MVT::SimpleValueType getValueType() const { return Ty; } unsigned getNumOperands() const { return NumOperands; } const std::string &getSelectFunc() const { return SelectFunc; } const std::vector &getRootNodes() const { Modified: llvm/trunk/utils/TableGen/DAGISelEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelEmitter.cpp?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/DAGISelEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Fri Jun 6 07:08:01 2008 @@ -51,8 +51,8 @@ /// patterns before small ones. This is used to determine the size of a /// pattern. static unsigned getPatternSize(TreePatternNode *P, CodeGenDAGPatterns &CGP) { - assert((MVT::isExtIntegerInVTs(P->getExtTypes()) || - MVT::isExtFloatingPointInVTs(P->getExtTypes()) || + assert((EMVT::isExtIntegerInVTs(P->getExtTypes()) || + EMVT::isExtFloatingPointInVTs(P->getExtTypes()) || P->getExtTypeNum(0) == MVT::isVoid || P->getExtTypeNum(0) == MVT::Flag || P->getExtTypeNum(0) == MVT::iPTR) && @@ -160,7 +160,7 @@ /// getRegisterValueType - Look up and return the first ValueType of specified /// RegisterClass record -static MVT::ValueType getRegisterValueType(Record *R, const CodeGenTarget &T) { +static MVT::SimpleValueType getRegisterValueType(Record *R, const CodeGenTarget &T) { if (const CodeGenRegisterClass *RC = T.getRegisterClassForRegister(R)) return RC->getValueTypeNum(0); return MVT::Other; @@ -932,7 +932,7 @@ // How many results is this pattern expected to produce? unsigned NumPatResults = 0; for (unsigned i = 0, e = Pattern->getExtTypes().size(); i != e; i++) { - MVT::ValueType VT = Pattern->getTypeNum(i); + MVT::SimpleValueType VT = Pattern->getTypeNum(i); if (VT != MVT::isVoid && VT != MVT::Flag) NumPatResults++; } @@ -1045,7 +1045,7 @@ for (unsigned i = 0; i < NumDstRegs; i++) { Record *RR = DstRegs[i]; if (RR->isSubClassOf("Register")) { - MVT::ValueType RVT = getRegisterValueType(RR, CGT); + MVT::SimpleValueType RVT = getRegisterValueType(RR, CGT); Code += ", " + getEnumName(RVT); } } @@ -1311,7 +1311,7 @@ Record *RR = DI->getDef(); if (RR->isSubClassOf("Register")) { - MVT::ValueType RVT = getRegisterValueType(RR, T); + MVT::SimpleValueType RVT = getRegisterValueType(RR, T); if (RVT == MVT::Flag) { if (!InFlagDecled) { emitCode("SDOperand InFlag = " + RootName + utostr(OpNo) + ";"); @@ -1634,12 +1634,13 @@ PatternSortingPredicate(CGP)); // Split them into groups by type. - std::map >PatternsByType; + std::map > PatternsByType; for (unsigned i = 0, e = PatternsOfOp.size(); i != e; ++i) { const PatternToMatch *Pat = PatternsOfOp[i]; TreePatternNode *SrcPat = Pat->getSrcPattern(); - MVT::ValueType VT = SrcPat->getTypeNum(0); - std::mapgetTypeNum(0); + std::map >::iterator TI = PatternsByType.find(VT); if (TI != PatternsByType.end()) @@ -1651,10 +1652,11 @@ } } - for (std::map >::iterator + for (std::map >::iterator II = PatternsByType.begin(), EE = PatternsByType.end(); II != EE; ++II) { - MVT::ValueType OpVT = II->first; + MVT::SimpleValueType OpVT = II->first; std::vector &Patterns = II->second; typedef std::vector > CodeList; typedef std::vector >::iterator CodeListI; @@ -1734,7 +1736,7 @@ CallerCode += ", " + TargetOpcodes[j]; } for (unsigned j = 0, e = TargetVTs.size(); j != e; ++j) { - CalleeCode += ", MVT::ValueType VT" + utostr(j); + CalleeCode += ", MVT VT" + utostr(j); CallerCode += ", " + TargetVTs[j]; } for (std::set::iterator @@ -1852,7 +1854,7 @@ << " for (unsigned j = 0, e = Ops.size(); j != e; ++j)\n" << " AddToISelQueue(Ops[j]);\n\n" - << " std::vector VTs;\n" + << " std::vector VTs;\n" << " VTs.push_back(MVT::Other);\n" << " VTs.push_back(MVT::Flag);\n" << " SDOperand New = CurDAG->getNode(ISD::INLINEASM, VTs, &Ops[0], " @@ -1931,7 +1933,7 @@ << "INSTRUCTION_LIST_END)) {\n" << " return NULL; // Already selected.\n" << " }\n\n" - << " MVT::ValueType NVT = N.Val->getValueType(0);\n" + << " MVT::SimpleValueType NVT = N.Val->getValueType(0).getSimpleVT();\n" << " switch (N.getOpcode()) {\n" << " default: break;\n" << " case ISD::EntryToken: // These leaves remain the same.\n" @@ -2008,7 +2010,7 @@ // If there is an iPTR result version of this pattern, emit it here. if (HasPtrPattern) { - OS << " if (NVT == TLI.getPointerTy())\n"; + OS << " if (TLI.getPointerTy() == NVT)\n"; OS << " return Select_" << getLegalCName(OpName) <<"_iPTR(N);\n"; } if (HasDefaultPattern) { Modified: llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp Fri Jun 6 07:08:01 2008 @@ -114,9 +114,9 @@ OS << "#endif\n\n"; } -static void EmitTypeForValueType(std::ostream &OS, MVT::ValueType VT) { - if (MVT::isInteger(VT)) { - unsigned BitWidth = MVT::getSizeInBits(VT); +static void EmitTypeForValueType(std::ostream &OS, MVT::SimpleValueType VT) { + if (MVT(VT).isInteger()) { + unsigned BitWidth = MVT(VT).getSizeInBits(); OS << "IntegerType::get(" << BitWidth << ")"; } else if (VT == MVT::Other) { // MVT::OtherVT is used to mean the empty struct type here. @@ -140,7 +140,7 @@ static void EmitTypeGenerate(std::ostream &OS, Record *ArgType, unsigned &ArgNo) { - MVT::ValueType VT = getValueType(ArgType->getValueAsDef("VT")); + MVT::SimpleValueType VT = getValueType(ArgType->getValueAsDef("VT")); if (ArgType->isSubClassOf("LLVMMatchType")) { unsigned Number = ArgType->getValueAsInt("Number"); @@ -153,10 +153,11 @@ // increment it when we actually hit an overloaded type. Getting this wrong // leads to very subtle bugs! OS << "Tys[" << ArgNo++ << "]"; - } else if (MVT::isVector(VT)) { + } else if (MVT(VT).isVector()) { + MVT VVT = VT; OS << "VectorType::get("; - EmitTypeForValueType(OS, MVT::getVectorElementType(VT)); - OS << ", " << MVT::getVectorNumElements(VT) << ")"; + EmitTypeForValueType(OS, VVT.getVectorElementType().getSimpleVT()); + OS << ", " << VVT.getVectorNumElements() << ")"; } else if (VT == MVT::iPTR) { OS << "PointerType::getUnqual("; EmitTypeGenerate(OS, ArgType->getValueAsDef("ElTy"), ArgNo); @@ -225,7 +226,7 @@ assert(Number < j && "Invalid matching number!"); OS << "~" << Number; } else { - MVT::ValueType VT = getValueType(ArgType->getValueAsDef("VT")); + MVT::SimpleValueType VT = getValueType(ArgType->getValueAsDef("VT")); OS << getEnumName(VT); if (VT == MVT::isVoid && j != 0 && j != ArgTypes.size()-1) throw "Var arg type not last argument"; Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=52044&r1=52043&r2=52044&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Fri Jun 6 07:08:01 2008 @@ -221,7 +221,7 @@ // Emit the register list now. OS << " // " << Name << " Register Class Value Types...\n" - << " static const MVT::ValueType " << Name + << " static const MVT " << Name << "[] = {\n "; for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i) OS << getEnumName(RC.VTs[i]) << ", "; From baldrick at free.fr Fri Jun 6 07:49:32 2008 From: baldrick at free.fr (Duncan Sands) Date: Fri, 06 Jun 2008 12:49:32 -0000 Subject: [llvm-commits] [llvm] r52045 - in /llvm/trunk: include/llvm/CodeGen/ValueTypes.h lib/CodeGen/SelectionDAG/SelectionDAG.cpp Message-ID: <200806061249.m56CnWhK025959@zion.cs.uiuc.edu> Author: baldrick Date: Fri Jun 6 07:49:32 2008 New Revision: 52045 URL: http://llvm.org/viewvc/llvm-project?rev=52045&view=rev Log: Tighten up the abstraction slightly. Modified: llvm/trunk/include/llvm/CodeGen/ValueTypes.h llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Modified: llvm/trunk/include/llvm/CodeGen/ValueTypes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ValueTypes.h?rev=52045&r1=52044&r2=52045&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/ValueTypes.h (original) +++ llvm/trunk/include/llvm/CodeGen/ValueTypes.h Fri Jun 6 07:49:32 2008 @@ -25,6 +25,7 @@ class Type; struct MVT { // MVT = Machine Value Type + public: enum SimpleValueType { // If you change this numbering, you must change the values in @@ -107,6 +108,8 @@ /// | | Vector element | /// + private: + static const int SimpleTypeBits = 8; static const int PrecisionBits = 8; static const int VectorBits = 32 - SimpleTypeBits - PrecisionBits; @@ -125,6 +128,8 @@ uint32_t V; + public: + MVT() {} MVT(SimpleValueType S) { V = S; } inline bool operator== (const MVT VT) const { return V == VT.V; } @@ -194,9 +199,8 @@ if (NumElements == 2) return v2f64; break; } - // Set the length with the top bit forced to zero (needed by the verifier). MVT Result; - Result.V = VT.V | (((NumElements + 1) << (33 - VectorBits)) >> 1); + Result.V = VT.V | ((NumElements + 1) << (32 - VectorBits)); assert(Result.getVectorElementType() == VT && "Bad vector element type!"); assert(Result.getVectorNumElements() == NumElements && @@ -406,6 +410,9 @@ /// This returns all pointers as iPTR. If HandleUnknown is true, unknown /// types are returned as Other, otherwise they are invalid. static MVT getMVT(const Type *Ty, bool HandleUnknown = false); + + /// getRawBits - Represent the type as a bunch of bits. + uint32_t getRawBits() const { return V; } }; } // End llvm namespace Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=52045&r1=52044&r2=52045&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Fri Jun 6 07:49:32 2008 @@ -416,7 +416,7 @@ LoadSDNode *LD = cast(N); ID.AddInteger(LD->getAddressingMode()); ID.AddInteger(LD->getExtensionType()); - ID.AddInteger(LD->getMemoryVT().V); + ID.AddInteger(LD->getMemoryVT().getRawBits()); ID.AddInteger(LD->getAlignment()); ID.AddInteger(LD->isVolatile()); break; @@ -425,7 +425,7 @@ StoreSDNode *ST = cast(N); ID.AddInteger(ST->getAddressingMode()); ID.AddInteger(ST->isTruncatingStore()); - ID.AddInteger(ST->getMemoryVT().V); + ID.AddInteger(ST->getMemoryVT().getRawBits()); ID.AddInteger(ST->getAlignment()); ID.AddInteger(ST->isVolatile()); break; @@ -684,13 +684,13 @@ if (const LoadSDNode *LD = dyn_cast(N)) { ID.AddInteger(LD->getAddressingMode()); ID.AddInteger(LD->getExtensionType()); - ID.AddInteger(LD->getMemoryVT().V); + ID.AddInteger(LD->getMemoryVT().getRawBits()); ID.AddInteger(LD->getAlignment()); ID.AddInteger(LD->isVolatile()); } else if (const StoreSDNode *ST = dyn_cast(N)) { ID.AddInteger(ST->getAddressingMode()); ID.AddInteger(ST->isTruncatingStore()); - ID.AddInteger(ST->getMemoryVT().V); + ID.AddInteger(ST->getMemoryVT().getRawBits()); ID.AddInteger(ST->getAlignment()); ID.AddInteger(ST->isVolatile()); } @@ -2984,7 +2984,7 @@ FoldingSetNodeID ID; SDOperand Ops[] = {Chain, Ptr, Cmp, Swp}; AddNodeIDNode(ID, Opcode, VTs, Ops, 4); - ID.AddInteger(VT.V); + ID.AddInteger(VT.getRawBits()); void* IP = 0; if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) return SDOperand(E, 0); @@ -3007,7 +3007,7 @@ FoldingSetNodeID ID; SDOperand Ops[] = {Chain, Ptr, Val}; AddNodeIDNode(ID, Opcode, VTs, Ops, 3); - ID.AddInteger(VT.V); + ID.AddInteger(VT.getRawBits()); void* IP = 0; if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) return SDOperand(E, 0); @@ -3064,7 +3064,7 @@ AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3); ID.AddInteger(AM); ID.AddInteger(ExtType); - ID.AddInteger(EVT.V); + ID.AddInteger(EVT.getRawBits()); ID.AddInteger(Alignment); ID.AddInteger(isVolatile); void *IP = 0; @@ -3132,7 +3132,7 @@ AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); ID.AddInteger(ISD::UNINDEXED); ID.AddInteger(false); - ID.AddInteger(VT.V); + ID.AddInteger(VT.getRawBits()); ID.AddInteger(Alignment); ID.AddInteger(isVolatile); void *IP = 0; @@ -3178,7 +3178,7 @@ AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); ID.AddInteger(ISD::UNINDEXED); ID.AddInteger(1); - ID.AddInteger(SVT.V); + ID.AddInteger(SVT.getRawBits()); ID.AddInteger(Alignment); ID.AddInteger(isVolatile); void *IP = 0; @@ -3203,7 +3203,7 @@ AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); ID.AddInteger(AM); ID.AddInteger(ST->isTruncatingStore()); - ID.AddInteger(ST->getMemoryVT().V); + ID.AddInteger(ST->getMemoryVT().getRawBits()); ID.AddInteger(ST->getAlignment()); ID.AddInteger(ST->isVolatile()); void *IP = 0; From asl at math.spbu.ru Fri Jun 6 11:08:27 2008 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Fri, 06 Jun 2008 16:08:27 -0000 Subject: [llvm-commits] [llvm] r52046 - /llvm/trunk/lib/Target/CBackend/CBackend.cpp Message-ID: <200806061608.m56G8ReF032045@zion.cs.uiuc.edu> Author: asl Date: Fri Jun 6 11:08:26 2008 New Revision: 52046 URL: http://llvm.org/viewvc/llvm-project?rev=52046&view=rev Log: Handle assembler identifiers specially in CBE. This fixes PR2418. Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CBackend.cpp?rev=52046&r1=52045&r2=52046&view=diff ============================================================================== --- llvm/trunk/lib/Target/CBackend/CBackend.cpp (original) +++ llvm/trunk/lib/Target/CBackend/CBackend.cpp Fri Jun 6 11:08:26 2008 @@ -1224,6 +1224,10 @@ Name = "llvm_cbe_" + VarName; } else { Name = Mang->getValueName(Operand); + + // Check, if operand has assembler identifier and handle it separately + if (Operand->getNameStart()[0] == 1) + Name = "llvm_cbe_asmname_" + Name; } return Name; @@ -1652,6 +1656,11 @@ if (I->hasExternalWeakLinkage()) Out << " __EXTERNAL_WEAK__"; + + // Special handling for assembler identifiers + if (I->getNameStart()[0] == 1) + Out << " LLVM_ASM(\"" << I->getName().c_str()+1 << "\")"; + Out << ";\n"; } } @@ -1661,7 +1670,7 @@ Out << "double fmod(double, double);\n"; // Support for FP rem Out << "float fmodf(float, float);\n"; Out << "long double fmodl(long double, long double);\n"; - + for (Module::iterator I = M.begin(), E = M.end(); I != E; ++I) { // Don't print declarations for intrinsic functions. if (!I->isIntrinsic() && I->getName() != "setjmp" && @@ -1669,7 +1678,7 @@ if (I->hasExternalWeakLinkage()) Out << "extern "; printFunctionSignature(I, true); - if (I->hasWeakLinkage() || I->hasLinkOnceLinkage()) + if (I->hasWeakLinkage() || I->hasLinkOnceLinkage()) Out << " __ATTRIBUTE_WEAK__"; if (I->hasExternalWeakLinkage()) Out << " __EXTERNAL_WEAK__"; @@ -1679,10 +1688,11 @@ Out << " __ATTRIBUTE_DTOR__"; if (I->hasHiddenVisibility()) Out << " __HIDDEN__"; - - if (I->hasName() && I->getName()[0] == 1) + + // Special handling for assembler identifiers + if (I->getNameStart()[0] == 1) Out << " LLVM_ASM(\"" << I->getName().c_str()+1 << "\")"; - + Out << ";\n"; } } @@ -1719,6 +1729,11 @@ Out << " __EXTERNAL_WEAK__"; if (I->hasHiddenVisibility()) Out << " __HIDDEN__"; + + // Special handling for assembler identifiers + if (I->getNameStart()[0] == 1) + Out << " LLVM_ASM(\"" << I->getName().c_str()+1 << "\")"; + Out << ";\n"; } } @@ -1726,7 +1741,7 @@ // Output the global variable definitions and contents... if (!M.global_empty()) { Out << "\n\n/* Global Variable Definitions and Initialization */\n"; - for (Module::global_iterator I = M.global_begin(), E = M.global_end(); + for (Module::global_iterator I = M.global_begin(), E = M.global_end(); I != E; ++I) if (!I->isDeclaration()) { // Ignore special globals, such as debug info. From asl at math.spbu.ru Fri Jun 6 11:08:56 2008 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Fri, 06 Jun 2008 16:08:56 -0000 Subject: [llvm-commits] [llvm] r52047 - /llvm/trunk/test/CodeGen/CBackend/2008-06-06-AssemblerNames.ll Message-ID: <200806061608.m56G8uPX032096@zion.cs.uiuc.edu> Author: asl Date: Fri Jun 6 11:08:56 2008 New Revision: 52047 URL: http://llvm.org/viewvc/llvm-project?rev=52047&view=rev Log: Testcase for PR2418 Added: llvm/trunk/test/CodeGen/CBackend/2008-06-06-AssemblerNames.ll Added: llvm/trunk/test/CodeGen/CBackend/2008-06-06-AssemblerNames.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CBackend/2008-06-06-AssemblerNames.ll?rev=52047&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/CBackend/2008-06-06-AssemblerNames.ll (added) +++ llvm/trunk/test/CodeGen/CBackend/2008-06-06-AssemblerNames.ll Fri Jun 6 11:08:56 2008 @@ -0,0 +1,141 @@ +; RUN: llvm-as < %s | llc -march=c | grep llvm_cbe_asmname | count 36 +; PR2418 + +; ModuleID = 'main.bc' +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" +target triple = "i686-apple-darwin8" +module asm "\09.lazy_reference .objc_class_name_MyClass" +module asm "\09.lazy_reference .objc_class_name_Object" + %struct.MyClass = type { %struct.Object } + %struct.Object = type { %struct.objc_class* } + %struct.Protocol = type opaque + %struct._objc__method_prototype_list = type opaque + %struct._objc_class = type { %struct._objc_class*, %struct._objc_class*, i8*, i32, i32, i32, %struct._objc_ivar_list*, %struct._objc_method_list*, %struct.objc_cache*, %struct._objc_protocol**, i8*, %struct._objc_class_ext* } + %struct._objc_class_ext = type opaque + %struct._objc_ivar_list = type opaque + %struct._objc_method = type { %struct.objc_selector*, i8*, i8* } + %struct._objc_method_list = type opaque + %struct._objc_module = type { i32, i32, i8*, %struct._objc_symtab* } + %struct._objc_protocol = type { %struct._objc_protocol_extension*, i8*, %struct._objc_protocol**, %struct._objc__method_prototype_list*, %struct._objc__method_prototype_list* } + %struct._objc_protocol_extension = type opaque + %struct._objc_symtab = type { i32, %struct.objc_selector**, i16, i16, [1 x i8*] } + %struct.anon = type { %struct._objc__method_prototype_list*, i32, [1 x %struct._objc_method] } + %struct.objc_cache = type { i32, i32, [1 x %struct.objc_method*] } + %struct.objc_class = type { %struct.objc_class*, %struct.objc_class*, i8*, i32, i32, i32, %struct.objc_ivar_list*, %struct.objc_method_list**, %struct.objc_cache*, %struct.objc_protocol_list* } + %struct.objc_ivar = type { i8*, i8*, i32 } + %struct.objc_ivar_list = type { i32, [1 x %struct.objc_ivar] } + %struct.objc_method = type { %struct.objc_selector*, i8*, %struct.Object* (%struct.Object*, %struct.objc_selector*, ...)* } + %struct.objc_method_list = type { %struct.objc_method_list*, i32, [1 x %struct.objc_method] } + %struct.objc_object = type { %struct.objc_class* } + %struct.objc_protocol_list = type { %struct.objc_protocol_list*, i32, [1 x %struct.Protocol*] } + %struct.objc_selector = type opaque + at .str = internal constant [13 x i8] c"Hello world!\00" ; <[13 x i8]*> [#uses=1] +@"\01L_OBJC_CLASS_REFERENCES_0" = internal global %struct.objc_class* bitcast ([8 x i8]* @"\01L_OBJC_CLASS_NAME_0" to %struct.objc_class*), section "__OBJC,__cls_refs,literal_pointers,no_dead_strip" ; <%struct.objc_class**> [#uses=2] +@"\01L_OBJC_SELECTOR_REFERENCES_0" = internal global %struct.objc_selector* bitcast ([6 x i8]* @"\01L_OBJC_METH_VAR_NAME_1" to %struct.objc_selector*), section "__OBJC,__message_refs,literal_pointers,no_dead_strip" ; <%struct.objc_selector**> [#uses=2] +@"\01L_OBJC_SELECTOR_REFERENCES_1" = internal global %struct.objc_selector* bitcast ([9 x i8]* @"\01L_OBJC_METH_VAR_NAME_0" to %struct.objc_selector*), section "__OBJC,__message_refs,literal_pointers,no_dead_strip" ; <%struct.objc_selector**> [#uses=2] +@"\01L_OBJC_CLASS_MyClass" = internal global %struct._objc_class { + %struct._objc_class* @"\01L_OBJC_METACLASS_MyClass", + %struct._objc_class* bitcast ([7 x i8]* @"\01L_OBJC_CLASS_NAME_1" to %struct._objc_class*), + i8* getelementptr ([8 x i8]* @"\01L_OBJC_CLASS_NAME_0", i32 0, i32 0), + i32 0, + i32 1, + i32 4, + %struct._objc_ivar_list* null, + %struct._objc_method_list* bitcast ({ i32, i32, [1 x %struct._objc_method] }* @"\01L_OBJC_INSTANCE_METHODS_MyClass" to %struct._objc_method_list*), + %struct.objc_cache* null, + %struct._objc_protocol** null, + i8* null, + %struct._objc_class_ext* null }, section "__OBJC,__class,regular,no_dead_strip", align 32 ; <%struct._objc_class*> [#uses=2] +@"\01L_OBJC_SYMBOLS" = internal global { i32, %struct.objc_selector**, i16, i16, [1 x %struct._objc_class*] } { + i32 0, + %struct.objc_selector** null, + i16 1, + i16 0, + [1 x %struct._objc_class*] [ %struct._objc_class* @"\01L_OBJC_CLASS_MyClass" ] }, section "__OBJC,__symbols,regular,no_dead_strip" ; <{ i32, %struct.objc_selector**, i16, i16, [1 x %struct._objc_class*] }*> [#uses=2] + at L_OBJC_METH_VAR_NAME_0 = internal global [9 x i8] c"sayHello\00", section "__TEXT,__cstring,cstring_literals" ; <[9 x i8]*> [#uses=0] + at L_OBJC_METH_VAR_TYPE_0 = internal global [7 x i8] c"v8 at 0:4\00", section "__TEXT,__cstring,cstring_literals" ; <[7 x i8]*> [#uses=0] +@"\01L_OBJC_METH_VAR_NAME_0" = internal global [9 x i8] c"sayHello\00", section "__TEXT,__cstring,cstring_literals" ; <[9 x i8]*> [#uses=2] +@"\01L_OBJC_METH_VAR_TYPE_0" = internal global [7 x i8] c"v8 at 0:4\00", section "__TEXT,__cstring,cstring_literals" ; <[7 x i8]*> [#uses=1] +@"\01L_OBJC_INSTANCE_METHODS_MyClass" = internal global { i32, i32, [1 x %struct._objc_method] } { + i32 0, + i32 1, + [1 x %struct._objc_method] [ %struct._objc_method { + %struct.objc_selector* bitcast ([9 x i8]* @"\01L_OBJC_METH_VAR_NAME_0" to %struct.objc_selector*), + i8* getelementptr ([7 x i8]* @"\01L_OBJC_METH_VAR_TYPE_0", i32 0, i32 0), + i8* bitcast (void (%struct.MyClass*, %struct.objc_selector*)* @"-[MyClass sayHello]" to i8*) } ] }, section "__OBJC,__inst_meth,regular,no_dead_strip" ; <{ i32, i32, [1 x %struct._objc_method] }*> [#uses=2] + at L_OBJC_CLASS_NAME_0 = internal global [8 x i8] c"MyClass\00", section "__TEXT,__cstring,cstring_literals" ; <[8 x i8]*> [#uses=0] + at L_OBJC_CLASS_NAME_1 = internal global [7 x i8] c"Object\00", section "__TEXT,__cstring,cstring_literals" ; <[7 x i8]*> [#uses=0] +@"\01L_OBJC_METACLASS_MyClass" = internal global %struct._objc_class { + %struct._objc_class* bitcast ([7 x i8]* @"\01L_OBJC_CLASS_NAME_1" to %struct._objc_class*), + %struct._objc_class* bitcast ([7 x i8]* @"\01L_OBJC_CLASS_NAME_1" to %struct._objc_class*), + i8* getelementptr ([8 x i8]* @"\01L_OBJC_CLASS_NAME_0", i32 0, i32 0), + i32 0, + i32 2, + i32 48, + %struct._objc_ivar_list* null, + %struct._objc_method_list* null, + %struct.objc_cache* null, + %struct._objc_protocol** null, + i8* null, + %struct._objc_class_ext* null }, section "__OBJC,__meta_class,regular,no_dead_strip", align 32 ; <%struct._objc_class*> [#uses=2] +@"\01L_OBJC_CLASS_NAME_1" = internal global [7 x i8] c"Object\00", section "__TEXT,__cstring,cstring_literals" ; <[7 x i8]*> [#uses=2] +@"\01L_OBJC_CLASS_NAME_0" = internal global [8 x i8] c"MyClass\00", section "__TEXT,__cstring,cstring_literals" ; <[8 x i8]*> [#uses=2] + at L_OBJC_METH_VAR_NAME_1 = internal global [6 x i8] c"alloc\00", section "__TEXT,__cstring,cstring_literals" ; <[6 x i8]*> [#uses=0] +@"\01L_OBJC_METH_VAR_NAME_1" = internal global [6 x i8] c"alloc\00", section "__TEXT,__cstring,cstring_literals" ; <[6 x i8]*> [#uses=2] +@"\01L_OBJC_IMAGE_INFO" = internal constant [2 x i32] zeroinitializer, section "__OBJC,__image_info,regular" ; <[2 x i32]*> [#uses=1] + at L_OBJC_CLASS_NAME_2 = internal global [1 x i8] zeroinitializer, section "__TEXT,__cstring,cstring_literals" ; <[1 x i8]*> [#uses=0] +@"\01L_OBJC_MODULES" = internal global %struct._objc_module { + i32 7, + i32 16, + i8* getelementptr ([1 x i8]* @"\01L_OBJC_CLASS_NAME_2", i32 0, i32 0), + %struct._objc_symtab* bitcast ({ i32, %struct.objc_selector**, i16, i16, [1 x %struct._objc_class*] }* @"\01L_OBJC_SYMBOLS" to %struct._objc_symtab*) }, section "__OBJC,__module_info,regular,no_dead_strip" ; <%struct._objc_module*> [#uses=1] +@"\01L_OBJC_CLASS_NAME_2" = internal global [1 x i8] zeroinitializer, section "__TEXT,__cstring,cstring_literals" ; <[1 x i8]*> [#uses=1] +@"\01.objc_class_name_MyClass" = constant i32 0 ; [#uses=1] + at llvm.used = appending global [16 x i8*] [ i8* bitcast (%struct.objc_class** @"\01L_OBJC_CLASS_REFERENCES_0" to i8*), i8* bitcast (%struct.objc_selector** @"\01L_OBJC_SELECTOR_REFERENCES_0" to i8*), i8* bitcast (%struct.objc_selector** @"\01L_OBJC_SELECTOR_REFERENCES_1" to i8*), i8* bitcast (%struct._objc_class* @"\01L_OBJC_CLASS_MyClass" to i8*), i8* bitcast ({ i32, %struct.objc_selector**, i16, i16, [1 x %struct._objc_class*] }* @"\01L_OBJC_SYMBOLS" to i8*), i8* getelementptr ([9 x i8]* @"\01L_OBJC_METH_VAR_NAME_0", i32 0, i32 0), i8* getelementptr ([7 x i8]* @"\01L_OBJC_METH_VAR_TYPE_0", i32 0, i32 0), i8* bitcast ({ i32, i32, [1 x %struct._objc_method] }* @"\01L_OBJC_INSTANCE_METHODS_MyClass" to i8*), i8* getelementptr ([7 x i8]* @"\01L_OBJC_CLASS_NAME_1", i32 0, i32 0), i8* getelementptr ([8 x i8]* @"\01L_OBJC_CLASS_NAME_0", i32 0, i32 0), i8* bitcast (%struct._objc_class* @"\01L_OBJC_METACLASS_MyClass" to i8*), i8* getelementptr ([6 x i8]* @"\01L_OBJC_METH_VAR_NAME_1"! , i32 0, i32 0), i8* bitcast ([2 x i32]* @"\01L_OBJC_IMAGE_INFO" to i8*), i8* getelementptr ([1 x i8]* @"\01L_OBJC_CLASS_NAME_2", i32 0, i32 0), i8* bitcast (%struct._objc_module* @"\01L_OBJC_MODULES" to i8*), i8* bitcast (i32* @"\01.objc_class_name_MyClass" to i8*) ], section "llvm.metadata" ; <[16 x i8*]*> [#uses=0] + +define internal void @"-[MyClass sayHello]"(%struct.MyClass* %self, %struct.objc_selector* %_cmd) { +entry: + %self_addr = alloca %struct.MyClass* ; <%struct.MyClass**> [#uses=1] + %_cmd_addr = alloca %struct.objc_selector* ; <%struct.objc_selector**> [#uses=1] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + store %struct.MyClass* %self, %struct.MyClass** %self_addr + store %struct.objc_selector* %_cmd, %struct.objc_selector** %_cmd_addr + %tmp = getelementptr [13 x i8]* @.str, i32 0, i32 0 ; [#uses=1] + %tmp1 = call i32 @puts( i8* %tmp ) nounwind ; [#uses=0] + br label %return + +return: ; preds = %entry + ret void +} + +declare i32 @puts(i8*) + +define i32 @main() { +entry: + %retval = alloca i32 ; [#uses=1] + %anObject = alloca %struct.MyClass* ; <%struct.MyClass**> [#uses=2] + %anObject.4 = alloca %struct.Object* ; <%struct.Object**> [#uses=2] + %L_OBJC_CLASS_REFERENCES_0.2 = alloca %struct.Object* ; <%struct.Object**> [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + %tmp = load %struct.objc_class** @"\01L_OBJC_CLASS_REFERENCES_0", align 4 ; <%struct.objc_class*> [#uses=1] + %tmp1 = bitcast %struct.objc_class* %tmp to %struct.Object* ; <%struct.Object*> [#uses=1] + store %struct.Object* %tmp1, %struct.Object** %L_OBJC_CLASS_REFERENCES_0.2, align 4 + %tmp2 = load %struct.objc_selector** @"\01L_OBJC_SELECTOR_REFERENCES_0", align 4 ; <%struct.objc_selector*> [#uses=1] + %tmp3 = load %struct.Object** %L_OBJC_CLASS_REFERENCES_0.2, align 4 ; <%struct.Object*> [#uses=1] + %tmp4 = call %struct.Object* bitcast (%struct.Object* (%struct.Object*, %struct.objc_selector*, ...)* @objc_msgSend to %struct.Object* (%struct.Object*, %struct.objc_selector*)*)( %struct.Object* %tmp3, %struct.objc_selector* %tmp2 ) nounwind ; <%struct.Object*> [#uses=1] + %tmp45 = bitcast %struct.Object* %tmp4 to %struct.MyClass* ; <%struct.MyClass*> [#uses=1] + store %struct.MyClass* %tmp45, %struct.MyClass** %anObject, align 4 + %tmp6 = load %struct.MyClass** %anObject, align 4 ; <%struct.MyClass*> [#uses=1] + %tmp67 = bitcast %struct.MyClass* %tmp6 to %struct.Object* ; <%struct.Object*> [#uses=1] + store %struct.Object* %tmp67, %struct.Object** %anObject.4, align 4 + %tmp8 = load %struct.objc_selector** @"\01L_OBJC_SELECTOR_REFERENCES_1", align 4 ; <%struct.objc_selector*> [#uses=1] + %tmp9 = load %struct.Object** %anObject.4, align 4 ; <%struct.Object*> [#uses=1] + call void bitcast (%struct.Object* (%struct.Object*, %struct.objc_selector*, ...)* @objc_msgSend to void (%struct.Object*, %struct.objc_selector*)*)( %struct.Object* %tmp9, %struct.objc_selector* %tmp8 ) nounwind + br label %return + +return: ; preds = %entry + %retval10 = load i32* %retval ; [#uses=1] + ret i32 %retval10 +} + +declare %struct.Object* @objc_msgSend(%struct.Object*, %struct.objc_selector*, ...) From resistor at mac.com Fri Jun 6 11:23:16 2008 From: resistor at mac.com (Owen Anderson) Date: Fri, 06 Jun 2008 16:23:16 -0000 Subject: [llvm-commits] [llvm] r52048 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <200806061623.m56GNGNn032641@zion.cs.uiuc.edu> Author: resistor Date: Fri Jun 6 11:23:15 2008 New Revision: 52048 URL: http://llvm.org/viewvc/llvm-project?rev=52048&view=rev Log: Include loop deletion and the ADCE rewrite in the release notes. Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=52048&r1=52047&r2=52048&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Fri Jun 6 11:23:15 2008 @@ -240,6 +240,11 @@ stores and merges them into memcpys where profitable.

            • Alignment detection for vector memory references and for memcpy and memset is now more aggressive.
              • + +
            • The aggressive dead code elimination (ADCE) optimization has been rewritten to make +it both faster and safer in the presence of code containing infinite loops. +Some of its prior functionality has been factored out into the loop deletion +pass, which is safe for infinite loops.
            From dpatel at apple.com Fri Jun 6 12:50:37 2008 From: dpatel at apple.com (Devang Patel) Date: Fri, 06 Jun 2008 17:50:37 -0000 Subject: [llvm-commits] [llvm] r52052 - /llvm/trunk/lib/VMCore/PassManager.cpp Message-ID: <200806061750.m56HobtO002786@zion.cs.uiuc.edu> Author: dpatel Date: Fri Jun 6 12:50:36 2008 New Revision: 52052 URL: http://llvm.org/viewvc/llvm-project?rev=52052&view=rev Log: Print debug message only if there are dead passes. Modified: llvm/trunk/lib/VMCore/PassManager.cpp Modified: llvm/trunk/lib/VMCore/PassManager.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/PassManager.cpp?rev=52052&r1=52051&r2=52052&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/PassManager.cpp (original) +++ llvm/trunk/lib/VMCore/PassManager.cpp Fri Jun 6 12:50:36 2008 @@ -665,9 +665,10 @@ TPM->collectLastUses(DeadPasses, P); - if (PassDebugging >= Details) { + if (PassDebugging >= Details && !DeadPasses.empty()) { cerr << " -*- " << P->getPassName(); - cerr << " is the last users of following passes. Free them\n"; + cerr << " is the last user of following pass instances."; + cerr << " Free these instances\n"; } for (SmallVector::iterator I = DeadPasses.begin(), From dpatel at apple.com Fri Jun 6 12:50:59 2008 From: dpatel at apple.com (Devang Patel) Date: Fri, 06 Jun 2008 17:50:59 -0000 Subject: [llvm-commits] [llvm] r52053 - /llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp Message-ID: <200806061750.m56Hox72002807@zion.cs.uiuc.edu> Author: dpatel Date: Fri Jun 6 12:50:58 2008 New Revision: 52053 URL: http://llvm.org/viewvc/llvm-project?rev=52053&view=rev Log: LoopSimplify preserves AA. Modified: llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp Modified: llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp?rev=52053&r1=52052&r2=52053&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp Fri Jun 6 12:50:58 2008 @@ -73,6 +73,7 @@ AU.addPreserved(); AU.addPreserved(); AU.addPreserved(); + AU.addPreserved(); AU.addPreservedID(BreakCriticalEdgesID); // No critical edges added. } @@ -252,9 +253,10 @@ for (BasicBlock::iterator I = L->getHeader()->begin(); (PN = dyn_cast(I++)); ) if (Value *V = PN->hasConstantValue()) { - PN->replaceAllUsesWith(V); - PN->eraseFromParent(); - } + if (AA) AA->deleteValue(PN); + PN->replaceAllUsesWith(V); + PN->eraseFromParent(); + } return Changed; } From gabor at mac.com Fri Jun 6 13:13:43 2008 From: gabor at mac.com (Gabor Greif) Date: Fri, 06 Jun 2008 20:13:43 +0200 Subject: [llvm-commits] [PATCH] ExtractValueInst < UnaryInstruction Message-ID: This patch makes a slight change to the inheritance graph, by deriving ExtractValueInst from UnaryInstruction. Dan, Mathiijs, OK to commit? The only thing that could be improved on this is the elimination of the name argument to init(). Cheers, Gabor Index: include/llvm/Instructions.h =================================================================== --- include/llvm/Instructions.h (Revision 52051) +++ include/llvm/Instructions.h (Arbeitskopie) @@ -1453,7 +1453,7 @@ /// ExtractValueInst - This instruction extracts a struct member or array /// element value from an aggregate value. /// -class ExtractValueInst : public Instruction { +class ExtractValueInst : public UnaryInstruction { SmallVector Indices; ExtractValueInst(const ExtractValueInst &EVI); @@ -1526,12 +1526,13 @@ Instruction *InsertBefore = 0); ExtractValueInst(Value *Agg, unsigned Idx, const std::string &Name, BasicBlock *InsertAtEnd); -public: + // allocate space for exactly one operand void *operator new(size_t s) { return User::operator new(s, 1); } +public: template static ExtractValueInst *Create(Value *Agg, InputIterator IdxBegin, InputIterator IdxEnd, @@ -1629,10 +1630,9 @@ InputIterator IdxEnd, const std::string &Name, Instruction *InsertBefore) - : Instruction(checkType(getIndexedType(Agg->getType(), IdxBegin, IdxEnd)), - ExtractValue, - OperandTraits::op_begin(this), - 1, InsertBefore) { + : UnaryInstruction(checkType(getIndexedType(Agg->getType(), + IdxBegin, IdxEnd)), + ExtractValue, Agg, InsertBefore) { init(Agg, IdxBegin, IdxEnd, Name, typename std::iterator_traits::iterator_category()); } @@ -1642,10 +1642,9 @@ InputIterator IdxEnd, const std::string &Name, BasicBlock *InsertAtEnd) - : Instruction(checkType(getIndexedType(Agg->getType(), IdxBegin, IdxEnd)), - ExtractValue, - OperandTraits::op_begin(this), - 1, InsertAtEnd) { + : UnaryInstruction(checkType(getIndexedType(Agg->getType(), + IdxBegin, IdxEnd)), + ExtractValue, Agg, InsertAtEnd) { init(Agg, IdxBegin, IdxEnd, Name, typename std::iterator_traits::iterator_category()); } Index: lib/VMCore/Instructions.cpp =================================================================== --- lib/VMCore/Instructions.cpp (Revision 52051) +++ lib/VMCore/Instructions.cpp (Arbeitskopie) @@ -999,7 +999,8 @@ return cast(Val->getType())->getAddressSpace(); } -void GetElementPtrInst::init(Value *Ptr, Value* const *Idx, unsigned NumIdx, const std::string &Name) { +void GetElementPtrInst::init(Value *Ptr, Value* const *Idx, unsigned NumIdx, + const std::string &Name) { assert(NumOperands == 1+NumIdx && "NumOperands not initialized?"); Use *OL = OperandList; OL[0] = Ptr; @@ -1411,7 +1412,8 @@ // ExtractValueInst Class // ===--------------------------------------------------------------------- -===// -void ExtractValueInst::init(Value *Agg, const unsigned *Idx, unsigned NumIdx, const std::string &Name) { +void ExtractValueInst::init(Value *Agg, const unsigned *Idx, unsigned NumIdx, + const std::string &Name) { assert(NumOperands == 1 && "NumOperands not initialized?"); Op<0>() = Agg; @@ -1428,8 +1430,7 @@ } ExtractValueInst::ExtractValueInst(const ExtractValueInst &EVI) - : Instruction(reinterpret_cast(EVI.getType()), ExtractValue, - OperandTraits::op_begin(this), 1), + : UnaryInstruction(EVI.getType(), ExtractValue, EVI.getOperand(0)), Indices(EVI.Indices) { } @@ -1464,10 +1465,8 @@ unsigned Idx, const std::string &Name, BasicBlock *InsertAtEnd) - : Instruction(checkType(getIndexedType(Agg->getType(), &Idx, 1)), - ExtractValue, - OperandTraits::op_begin(this), - 1, InsertAtEnd) { + : UnaryInstruction(checkType(getIndexedType(Agg->getType(), &Idx, 1)), + ExtractValue, Agg, InsertAtEnd) { init(Agg, Idx, Name); } @@ -1475,10 +1474,8 @@ unsigned Idx, const std::string &Name, Instruction *InsertBefore) - : Instruction(checkType(getIndexedType(Agg->getType(), &Idx, 1)), - ExtractValue, - OperandTraits::op_begin(this), - 1, InsertBefore) { + : UnaryInstruction(checkType(getIndexedType(Agg->getType(), &Idx, 1)), + ExtractValue, Agg, InsertBefore) { init(Agg, Idx, Name); } From gohman at apple.com Fri Jun 6 13:41:34 2008 From: gohman at apple.com (Dan Gohman) Date: Fri, 06 Jun 2008 11:41:34 -0700 Subject: [llvm-commits] [PATCH] ExtractValueInst < UnaryInstruction In-Reply-To: References: Message-ID: <1212777695.6230.8.camel@dgohman1> On Fri, 2008-06-06 at 20:13 +0200, Gabor Greif wrote: > This patch makes a slight change to the inheritance > graph, by deriving ExtractValueInst from UnaryInstruction. > > Dan, Mathiijs, OK to commit? Looks good to me. ?Please also update UnaryInstruction's classof to reflect that ExtractValueInst isa UnaryInstruction. Does this patch make this code: template <> struct OperandTraits : FixedNumOperandTraits<1> { }; in Instructions.h redundant? If so, please remove it. And one more question below... > Index: include/llvm/Instructions.h > =================================================================== > --- include/llvm/Instructions.h (Revision 52051) > +++ include/llvm/Instructions.h (Arbeitskopie) > @@ -1453,7 +1453,7 @@ > /// ExtractValueInst - This instruction extracts a struct member or > array > /// element value from an aggregate value. > /// > -class ExtractValueInst : public Instruction { > +class ExtractValueInst : public UnaryInstruction { > SmallVector Indices; > > ExtractValueInst(const ExtractValueInst &EVI); > @@ -1526,12 +1526,13 @@ > Instruction *InsertBefore = 0); > ExtractValueInst(Value *Agg, unsigned Idx, > const std::string &Name, BasicBlock *InsertAtEnd); > -public: > + > // allocate space for exactly one operand > void *operator new(size_t s) { > return User::operator new(s, 1); > } > > +public: With ExtractValueInst being a UnaryInstruction, can we just get rid of this operator new, and just use the one inherited from UnaryInstruction? Dan From evan.cheng at apple.com Fri Jun 6 14:50:47 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 06 Jun 2008 19:50:47 -0000 Subject: [llvm-commits] [llvm] r52056 - /llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Message-ID: <200806061950.m56Jol6n009735@zion.cs.uiuc.edu> Author: evancheng Date: Fri Jun 6 14:50:46 2008 New Revision: 52056 URL: http://llvm.org/viewvc/llvm-project?rev=52056&view=rev Log: PPC preferred loop alignment is 16. Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=52056&r1=52055&r2=52056&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Fri Jun 6 14:50:46 2008 @@ -363,6 +363,9 @@ } computeRegisterProperties(); + + // Perferred loop alignment is 16. + setPrefLoopAlignment(16); } /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate From evan.cheng at apple.com Fri Jun 6 14:52:44 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 06 Jun 2008 19:52:44 -0000 Subject: [llvm-commits] [llvm] r52057 - in /llvm/trunk/lib/CodeGen: LLVMTargetMachine.cpp README.txt Message-ID: <200806061952.m56Jqioj009902@zion.cs.uiuc.edu> Author: evancheng Date: Fri Jun 6 14:52:44 2008 New Revision: 52057 URL: http://llvm.org/viewvc/llvm-project?rev=52057&view=rev Log: Enable stack coloring by default. Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp llvm/trunk/lib/CodeGen/README.txt Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=52057&r1=52056&r2=52057&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original) +++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Fri Jun 6 14:52:44 2008 @@ -38,10 +38,6 @@ EnableSinking("enable-sinking", cl::init(false), cl::Hidden, cl::desc("Perform sinking on machine code")); static cl::opt -EnableStackColoring("stack-coloring", - cl::init(false), cl::Hidden, - cl::desc("Perform stack slot coloring")); -static cl::opt EnableLICM("machine-licm", cl::init(false), cl::Hidden, cl::desc("Perform loop-invariant code motion on machine code")); @@ -103,8 +99,7 @@ PM.add(createRegisterAllocator()); // Perform stack slot coloring. - if (EnableStackColoring) - PM.add(createStackSlotColoringPass()); + PM.add(createStackSlotColoringPass()); if (PrintMachineCode) // Print the register-allocated code PM.add(createMachineFunctionPrinterPass(cerr)); @@ -240,8 +235,7 @@ PM.add(createRegisterAllocator()); // Perform stack slot coloring. - if (EnableStackColoring) - PM.add(createStackSlotColoringPass()); + PM.add(createStackSlotColoringPass()); if (PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); Modified: llvm/trunk/lib/CodeGen/README.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/README.txt?rev=52057&r1=52056&r2=52057&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/README.txt (original) +++ llvm/trunk/lib/CodeGen/README.txt Fri Jun 6 14:52:44 2008 @@ -197,3 +197,12 @@ which would eliminate a bunch of explicit predicates on them (e.g. no side effects). Once this is in place, it would be even better to have tblgen synthesize the various copy insertion/inspection methods in TargetInstrInfo. + +//===---------------------------------------------------------------------===// + +Stack coloring improvments: + +1. Do proper LiveStackAnalysis on all stack objects including those which are + not spill slots. +2. Reorder objects to fill in gaps between objects. + e.g. 4, 1, , 4, 1, 1, 1, , 4 => 4, 1, 1, 1, 1, 4, 4 From dalej at apple.com Fri Jun 6 14:56:42 2008 From: dalej at apple.com (Dale Johannesen) Date: Fri, 06 Jun 2008 19:56:42 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r52058 - in /llvm-gcc-4.2/trunk/gcc: config/i386/llvm-i386.cpp llvm-abi.h Message-ID: <200806061956.m56Jugd3010223@zion.cs.uiuc.edu> Author: johannes Date: Fri Jun 6 14:56:41 2008 New Revision: 52058 URL: http://llvm.org/viewvc/llvm-project?rev=52058&view=rev Log: X86-64 ABI: add handling for zero-length structs in C++. These are padded to 1 byte, but are not passed the same as normal 1-byte structs, nor as C zero-length structs. Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp llvm-gcc-4.2/trunk/gcc/llvm-abi.h Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp?rev=52058&r1=52057&r2=52058&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp Fri Jun 6 14:56:41 2008 @@ -554,7 +554,12 @@ enum machine_mode Mode){ int IntRegs, SSERegs; /* If ix86_HowToPassArgument return 0, then it's passed byval in memory.*/ - return !ix86_HowToPassArgument(Mode, TreeType, 0, &IntRegs, &SSERegs); + int ret = ix86_HowToPassArgument(Mode, TreeType, 0, &IntRegs, &SSERegs); + if (ret==0) + return true; + if (ret==1 && IntRegs==0 && SSERegs==0) // zero-sized struct + return true; + return false; } /* Returns true if all elements of the type are integer types. */ Modified: llvm-gcc-4.2/trunk/gcc/llvm-abi.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-abi.h?rev=52058&r1=52057&r2=52058&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-abi.h (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-abi.h Fri Jun 6 14:56:41 2008 @@ -449,12 +449,22 @@ } else if (TREE_CODE(type) == RECORD_TYPE) { for (tree Field = TYPE_FIELDS(type); Field; Field = TREE_CHAIN(Field)) if (TREE_CODE(Field) == FIELD_DECL) { + const tree Ftype = getDeclaredType(Field); + const Type *FTy = ConvertType(Ftype); unsigned FNo = GetFieldIndex(Field); assert(FNo != ~0U && "Case not handled yet!"); - - C.EnterField(FNo, Ty); - HandleArgument(getDeclaredType(Field), ScalarElts); - C.ExitField(); + + // Currently, a bvyal type inside a non-byval struct is a zero-length + // object inside a bigger object on x86-64. This type should be + // skipped (but only when it is inside a bigger object). + // (We know there currently are no other such cases active because + // they would hit the assert in FunctionPrologArgumentConversion:: + // HandleByValArgument.) + if (!LLVM_SHOULD_PASS_AGGREGATE_USING_BYVAL_ATTR(Ftype, FTy)) { + C.EnterField(FNo, Ty); + HandleArgument(getDeclaredType(Field), ScalarElts); + C.ExitField(); + } } } else if (TREE_CODE(type) == COMPLEX_TYPE) { C.EnterField(0, Ty); From gabor at mac.com Fri Jun 6 15:02:06 2008 From: gabor at mac.com (Gabor Greif) Date: Fri, 06 Jun 2008 22:02:06 +0200 Subject: [llvm-commits] [PATCH] ExtractValueInst < UnaryInstruction Message-ID: Dan wrote: > On Fri, 2008-06-06 at 20:13 +0200, Gabor Greif wrote: > > This patch makes a slight change to the inheritance > > graph, by deriving ExtractValueInst from UnaryInstruction. > > > > Dan, Mathiijs, OK to commit? > > Looks good to me. Please also update UnaryInstruction's classof to > reflect that ExtractValueInst isa UnaryInstruction. Okay. > > Does this patch make this code: > > template <> > struct OperandTraits : FixedNumOperandTraits<1> { > }; > > in Instructions.h redundant? If so, please remove it. It does. > > And one more question below... > > > Index: include/llvm/Instructions.h > > =================================================================== > > --- include/llvm/Instructions.h (Revision 52051) > > +++ include/llvm/Instructions.h (Arbeitskopie) > > @@ -1453,7 +1453,7 @@ > > /// ExtractValueInst - This instruction extracts a struct > member or > > array > > /// element value from an aggregate value. > > /// > > -class ExtractValueInst : public Instruction { > > +class ExtractValueInst : public UnaryInstruction { > > SmallVector Indices; > > > > ExtractValueInst(const ExtractValueInst &EVI); > > @@ -1526,12 +1526,13 @@ > > Instruction *InsertBefore = 0); > > ExtractValueInst(Value *Agg, unsigned Idx, > > const std::string &Name, BasicBlock > *InsertAtEnd); > > -public: > > + > > // allocate space for exactly one operand > > void *operator new(size_t s) { > > return User::operator new(s, 1); > > } > > > > +public: > > With ExtractValueInst being a UnaryInstruction, can we just get rid > of this operator new, and just use the one inherited from > UnaryInstruction? Unfortunately, no. The reason is that UnaryInstruction::new is public, while we do not want ExtractValueInst::new to be invoked by clients. ExtractValueInst::Create is the way to go. This is the reason for making ExtractValueInst::new private. Maybe we can use "private: using UnaryInstruction::new;", though :-) I'll check in with above changes made. Thanks for the review! Cheers, Gabor > > Dan > From gohman at apple.com Fri Jun 6 15:16:07 2008 From: gohman at apple.com (Dan Gohman) Date: Fri, 06 Jun 2008 13:16:07 -0700 Subject: [llvm-commits] [PATCH] ExtractValueInst < UnaryInstruction In-Reply-To: References: Message-ID: <1212783367.6230.26.camel@dgohman1> On Fri, 2008-06-06 at 22:02 +0200, Gabor Greif wrote: > > > Index: include/llvm/Instructions.h > > > =================================================================== > > > --- include/llvm/Instructions.h (Revision 52051) > > > +++ include/llvm/Instructions.h (Arbeitskopie) > > > @@ -1453,7 +1453,7 @@ > > > /// ExtractValueInst - This instruction extracts a struct > > member or > > > array > > > /// element value from an aggregate value. > > > /// > > > -class ExtractValueInst : public Instruction { > > > +class ExtractValueInst : public UnaryInstruction { > > > SmallVector Indices; > > > > > > ExtractValueInst(const ExtractValueInst &EVI); > > > @@ -1526,12 +1526,13 @@ > > > Instruction *InsertBefore = 0); > > > ExtractValueInst(Value *Agg, unsigned Idx, > > > const std::string &Name, BasicBlock > > *InsertAtEnd); > > > -public: > > > + > > > // allocate space for exactly one operand > > > void *operator new(size_t s) { > > > return User::operator new(s, 1); > > > } > > > > > > +public: > > > > With ExtractValueInst being a UnaryInstruction, can we just get rid > > of this operator new, and just use the one inherited from > > UnaryInstruction? > > Unfortunately, no. The reason is that UnaryInstruction::new is public, > while we do not want ExtractValueInst::new to be invoked > by clients. ExtractValueInst::Create is the way to go. This is > the reason for making ExtractValueInst::new private. > Maybe we can use "private: using UnaryInstruction::new;", though :-) Why is UnaryInstruction's operator new public? If it were protected, it seems like we wouldn't have to require all the child classes to have their own operator new just to make it non-public. Thanks, Dan From ggreif at gmail.com Fri Jun 6 15:28:13 2008 From: ggreif at gmail.com (Gabor Greif) Date: Fri, 06 Jun 2008 20:28:13 -0000 Subject: [llvm-commits] [llvm] r52061 - in /llvm/trunk: include/llvm/InstrTypes.h include/llvm/Instructions.h lib/VMCore/Instructions.cpp Message-ID: <200806062028.m56KSDbI012579@zion.cs.uiuc.edu> Author: ggreif Date: Fri Jun 6 15:28:12 2008 New Revision: 52061 URL: http://llvm.org/viewvc/llvm-project?rev=52061&view=rev Log: make ExtractValueInst derived from UnaryInstruction Modified: llvm/trunk/include/llvm/InstrTypes.h llvm/trunk/include/llvm/Instructions.h llvm/trunk/lib/VMCore/Instructions.cpp Modified: llvm/trunk/include/llvm/InstrTypes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/InstrTypes.h?rev=52061&r1=52060&r2=52061&view=diff ============================================================================== --- llvm/trunk/include/llvm/InstrTypes.h (original) +++ llvm/trunk/include/llvm/InstrTypes.h Fri Jun 6 15:28:12 2008 @@ -118,6 +118,7 @@ I->getOpcode() == Instruction::Load || I->getOpcode() == Instruction::VAArg || I->getOpcode() == Instruction::GetResult || + I->getOpcode() == Instruction::ExtractValue || (I->getOpcode() >= CastOpsBegin && I->getOpcode() < CastOpsEnd); } static inline bool classof(const Value *V) { Modified: llvm/trunk/include/llvm/Instructions.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructions.h?rev=52061&r1=52060&r2=52061&view=diff ============================================================================== --- llvm/trunk/include/llvm/Instructions.h (original) +++ llvm/trunk/include/llvm/Instructions.h Fri Jun 6 15:28:12 2008 @@ -1453,7 +1453,7 @@ /// ExtractValueInst - This instruction extracts a struct member or array /// element value from an aggregate value. /// -class ExtractValueInst : public Instruction { +class ExtractValueInst : public UnaryInstruction { SmallVector Indices; ExtractValueInst(const ExtractValueInst &EVI); @@ -1526,12 +1526,13 @@ Instruction *InsertBefore = 0); ExtractValueInst(Value *Agg, unsigned Idx, const std::string &Name, BasicBlock *InsertAtEnd); -public: + // allocate space for exactly one operand void *operator new(size_t s) { return User::operator new(s, 1); } +public: template static ExtractValueInst *Create(Value *Agg, InputIterator IdxBegin, InputIterator IdxEnd, @@ -1564,9 +1565,6 @@ virtual ExtractValueInst *clone() const; - /// Transparently provide more efficient getOperand methods. - DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value); - // getType - Overload to return most specific pointer type... const PointerType *getType() const { return reinterpret_cast(Instruction::getType()); @@ -1619,20 +1617,15 @@ } }; -template <> -struct OperandTraits : FixedNumOperandTraits<1> { -}; - template ExtractValueInst::ExtractValueInst(Value *Agg, InputIterator IdxBegin, InputIterator IdxEnd, const std::string &Name, Instruction *InsertBefore) - : Instruction(checkType(getIndexedType(Agg->getType(), IdxBegin, IdxEnd)), - ExtractValue, - OperandTraits::op_begin(this), - 1, InsertBefore) { + : UnaryInstruction(checkType(getIndexedType(Agg->getType(), + IdxBegin, IdxEnd)), + ExtractValue, Agg, InsertBefore) { init(Agg, IdxBegin, IdxEnd, Name, typename std::iterator_traits::iterator_category()); } @@ -1642,16 +1635,13 @@ InputIterator IdxEnd, const std::string &Name, BasicBlock *InsertAtEnd) - : Instruction(checkType(getIndexedType(Agg->getType(), IdxBegin, IdxEnd)), - ExtractValue, - OperandTraits::op_begin(this), - 1, InsertAtEnd) { + : UnaryInstruction(checkType(getIndexedType(Agg->getType(), + IdxBegin, IdxEnd)), + ExtractValue, Agg, InsertAtEnd) { init(Agg, IdxBegin, IdxEnd, Name, typename std::iterator_traits::iterator_category()); } -DEFINE_TRANSPARENT_OPERAND_ACCESSORS(ExtractValueInst, Value) - //===----------------------------------------------------------------------===// // InsertValueInst Class Modified: llvm/trunk/lib/VMCore/Instructions.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instructions.cpp?rev=52061&r1=52060&r2=52061&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Instructions.cpp (original) +++ llvm/trunk/lib/VMCore/Instructions.cpp Fri Jun 6 15:28:12 2008 @@ -999,7 +999,8 @@ return cast(Val->getType())->getAddressSpace(); } -void GetElementPtrInst::init(Value *Ptr, Value* const *Idx, unsigned NumIdx, const std::string &Name) { +void GetElementPtrInst::init(Value *Ptr, Value* const *Idx, unsigned NumIdx, + const std::string &Name) { assert(NumOperands == 1+NumIdx && "NumOperands not initialized?"); Use *OL = OperandList; OL[0] = Ptr; @@ -1411,7 +1412,8 @@ // ExtractValueInst Class //===----------------------------------------------------------------------===// -void ExtractValueInst::init(Value *Agg, const unsigned *Idx, unsigned NumIdx, const std::string &Name) { +void ExtractValueInst::init(Value *Agg, const unsigned *Idx, unsigned NumIdx, + const std::string &Name) { assert(NumOperands == 1 && "NumOperands not initialized?"); Op<0>() = Agg; @@ -1428,8 +1430,7 @@ } ExtractValueInst::ExtractValueInst(const ExtractValueInst &EVI) - : Instruction(reinterpret_cast(EVI.getType()), ExtractValue, - OperandTraits::op_begin(this), 1), + : UnaryInstruction(EVI.getType(), ExtractValue, EVI.getOperand(0)), Indices(EVI.Indices) { } @@ -1464,10 +1465,8 @@ unsigned Idx, const std::string &Name, BasicBlock *InsertAtEnd) - : Instruction(checkType(getIndexedType(Agg->getType(), &Idx, 1)), - ExtractValue, - OperandTraits::op_begin(this), - 1, InsertAtEnd) { + : UnaryInstruction(checkType(getIndexedType(Agg->getType(), &Idx, 1)), + ExtractValue, Agg, InsertAtEnd) { init(Agg, Idx, Name); } @@ -1475,10 +1474,8 @@ unsigned Idx, const std::string &Name, Instruction *InsertBefore) - : Instruction(checkType(getIndexedType(Agg->getType(), &Idx, 1)), - ExtractValue, - OperandTraits::op_begin(this), - 1, InsertBefore) { + : UnaryInstruction(checkType(getIndexedType(Agg->getType(), &Idx, 1)), + ExtractValue, Agg, InsertBefore) { init(Agg, Idx, Name); } From evan.cheng at apple.com Fri Jun 6 16:00:10 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 06 Jun 2008 21:00:10 -0000 Subject: [llvm-commits] [llvm] r52062 - /llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Message-ID: <200806062100.m56L0Ahu013527@zion.cs.uiuc.edu> Author: evancheng Date: Fri Jun 6 16:00:10 2008 New Revision: 52062 URL: http://llvm.org/viewvc/llvm-project?rev=52062&view=rev Log: Typo. Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=52062&r1=52061&r2=52062&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Fri Jun 6 16:00:10 2008 @@ -364,7 +364,7 @@ computeRegisterProperties(); - // Perferred loop alignment is 16. + // Preferred loop alignment is 16. setPrefLoopAlignment(16); } From ggreif at gmail.com Fri Jun 6 16:06:32 2008 From: ggreif at gmail.com (Gabor Greif) Date: Fri, 06 Jun 2008 21:06:32 -0000 Subject: [llvm-commits] [llvm] r52064 - in /llvm/trunk: include/llvm/Instructions.h lib/VMCore/Instructions.cpp Message-ID: <200806062106.m56L6WZe013733@zion.cs.uiuc.edu> Author: ggreif Date: Fri Jun 6 16:06:32 2008 New Revision: 52064 URL: http://llvm.org/viewvc/llvm-project?rev=52064&view=rev Log: get rid of ExtractValueInst::init's Value argument, it is already passed to the UnaryInstruction ctor Modified: llvm/trunk/include/llvm/Instructions.h llvm/trunk/lib/VMCore/Instructions.cpp Modified: llvm/trunk/include/llvm/Instructions.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructions.h?rev=52064&r1=52063&r2=52064&view=diff ============================================================================== --- llvm/trunk/include/llvm/Instructions.h (original) +++ llvm/trunk/include/llvm/Instructions.h Fri Jun 6 16:06:32 2008 @@ -1457,12 +1457,12 @@ SmallVector Indices; ExtractValueInst(const ExtractValueInst &EVI); - void init(Value *Agg, const unsigned *Idx, unsigned NumIdx, + void init(const unsigned *Idx, unsigned NumIdx, const std::string &Name); - void init(Value *Agg, unsigned Idx, const std::string &Name); + void init(unsigned Idx, const std::string &Name); template - void init(Value *Agg, InputIterator IdxBegin, InputIterator IdxEnd, + void init(InputIterator IdxBegin, InputIterator IdxEnd, const std::string &Name, // This argument ensures that we have an iterator we can // do arithmetic on in constant time @@ -1476,7 +1476,7 @@ assert(NumIdx > 0 && "ExtractValueInst must have at least one index"); // This requires that the iterator points to contiguous memory. - init(Agg, &*IdxBegin, NumIdx, Name); // FIXME: for the general case + init(&*IdxBegin, NumIdx, Name); // FIXME: for the general case // we have to build an array here } @@ -1626,7 +1626,7 @@ : UnaryInstruction(checkType(getIndexedType(Agg->getType(), IdxBegin, IdxEnd)), ExtractValue, Agg, InsertBefore) { - init(Agg, IdxBegin, IdxEnd, Name, + init(IdxBegin, IdxEnd, Name, typename std::iterator_traits::iterator_category()); } template @@ -1638,7 +1638,7 @@ : UnaryInstruction(checkType(getIndexedType(Agg->getType(), IdxBegin, IdxEnd)), ExtractValue, Agg, InsertAtEnd) { - init(Agg, IdxBegin, IdxEnd, Name, + init(IdxBegin, IdxEnd, Name, typename std::iterator_traits::iterator_category()); } Modified: llvm/trunk/lib/VMCore/Instructions.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instructions.cpp?rev=52064&r1=52063&r2=52064&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Instructions.cpp (original) +++ llvm/trunk/lib/VMCore/Instructions.cpp Fri Jun 6 16:06:32 2008 @@ -1412,18 +1412,16 @@ // ExtractValueInst Class //===----------------------------------------------------------------------===// -void ExtractValueInst::init(Value *Agg, const unsigned *Idx, unsigned NumIdx, +void ExtractValueInst::init(const unsigned *Idx, unsigned NumIdx, const std::string &Name) { assert(NumOperands == 1 && "NumOperands not initialized?"); - Op<0>() = Agg; Indices.insert(Indices.end(), Idx, Idx + NumIdx); setName(Name); } -void ExtractValueInst::init(Value *Agg, unsigned Idx, const std::string &Name) { +void ExtractValueInst::init(unsigned Idx, const std::string &Name) { assert(NumOperands == 1 && "NumOperands not initialized?"); - Op<0>() = Agg; Indices.push_back(Idx); setName(Name); @@ -1467,7 +1465,7 @@ BasicBlock *InsertAtEnd) : UnaryInstruction(checkType(getIndexedType(Agg->getType(), &Idx, 1)), ExtractValue, Agg, InsertAtEnd) { - init(Agg, Idx, Name); + init(Idx, Name); } ExtractValueInst::ExtractValueInst(Value *Agg, @@ -1476,7 +1474,7 @@ Instruction *InsertBefore) : UnaryInstruction(checkType(getIndexedType(Agg->getType(), &Idx, 1)), ExtractValue, Agg, InsertBefore) { - init(Agg, Idx, Name); + init(Idx, Name); } //===----------------------------------------------------------------------===// From tonic at nondot.org Fri Jun 6 16:44:17 2008 From: tonic at nondot.org (Tanya Lattner) Date: Fri, 6 Jun 2008 16:44:17 -0500 Subject: [llvm-commits] CVS: llvm-www/devmtg/index.php Message-ID: <200806062144.m56LiHtM014984@zion.cs.uiuc.edu> Changes in directory llvm-www/devmtg: index.php updated: 1.11 -> 1.12 --- Log message: Hotel room block information. --- Diffs of the changes: (+8 -2) index.php | 10 ++++++++-- 1 files changed, 8 insertions(+), 2 deletions(-) Index: llvm-www/devmtg/index.php diff -u llvm-www/devmtg/index.php:1.11 llvm-www/devmtg/index.php:1.12 --- llvm-www/devmtg/index.php:1.11 Thu May 22 18:24:30 2008 +++ llvm-www/devmtg/index.php Fri Jun 6 16:43:39 2008 @@ -137,8 +137,14 @@
            Lodging
            -

            We will be securing a special rate and hotel room block. We will post this here and on the -mailing list.

            +

            We have secured a special rate and room block for the Cupertino Inn which +is just blocks from the Apple Campus. Here is the information:

            +

            +Cut off Date: July 20, 2008.
            +Group Block Code: 100014
            +Rate: $134/night
            +24 hour cancellation policy
            +

            The following hotels are within walking distance of the Apple Campus:

            From tonic at nondot.org Fri Jun 6 16:46:02 2008 From: tonic at nondot.org (Tanya Lattner) Date: Fri, 6 Jun 2008 16:46:02 -0500 Subject: [llvm-commits] CVS: llvm-www/devmtg/index.php Message-ID: <200806062146.m56Lk2UD015059@zion.cs.uiuc.edu> Changes in directory llvm-www/devmtg: index.php updated: 1.12 -> 1.13 --- Log message: Put cut off date in bold. --- Diffs of the changes: (+1 -1) index.php | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm-www/devmtg/index.php diff -u llvm-www/devmtg/index.php:1.12 llvm-www/devmtg/index.php:1.13 --- llvm-www/devmtg/index.php:1.12 Fri Jun 6 16:43:39 2008 +++ llvm-www/devmtg/index.php Fri Jun 6 16:45:44 2008 @@ -140,7 +140,7 @@

            We have secured a special rate and room block for the Cupertino Inn which is just blocks from the Apple Campus. Here is the information:

            -Cut off Date: July 20, 2008.
            +Cut Off Date: July 20, 2008
            Group Block Code: 100014
            Rate: $134/night
            24 hour cancellation policy
            From resistor at mac.com Fri Jun 6 19:00:23 2008 From: resistor at mac.com (Owen Anderson) Date: Sat, 07 Jun 2008 00:00:23 -0000 Subject: [llvm-commits] [llvm] r52067 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Message-ID: <200806070000.m5700NDf018790@zion.cs.uiuc.edu> Author: resistor Date: Fri Jun 6 19:00:23 2008 New Revision: 52067 URL: http://llvm.org/viewvc/llvm-project?rev=52067&view=rev Log: Connect successors before creating the DAG node for the branch. This has no visible functionality change, but enables a future patch where node creation will update the CFG if it decides to create an unconditional rather than a conditional branch. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=52067&r1=52066&r2=52067&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Fri Jun 6 19:00:23 2008 @@ -1381,13 +1381,13 @@ NextBlock = BBI; if (I.isUnconditional()) { + // Update machine-CFG edges. + CurMBB->addSuccessor(Succ0MBB); + // If this is not a fall-through branch, emit the branch. if (Succ0MBB != NextBlock) DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(), DAG.getBasicBlock(Succ0MBB))); - - // Update machine-CFG edges. - CurMBB->addSuccessor(Succ0MBB); return; } @@ -1484,9 +1484,12 @@ Cond = DAG.getSetCC(MVT::i1, SUB, DAG.getConstant(High-Low, VT), ISD::SETULE); } - } + // Update successor info + CurMBB->addSuccessor(CB.TrueBB); + CurMBB->addSuccessor(CB.FalseBB); + // Set NextBlock to be the MBB immediately after the current one, if any. // This is used to avoid emitting unnecessary branches to the next block. MachineBasicBlock *NextBlock = 0; @@ -1508,9 +1511,6 @@ else DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond, DAG.getBasicBlock(CB.FalseBB))); - // Update successor info - CurMBB->addSuccessor(CB.TrueBB); - CurMBB->addSuccessor(CB.FalseBB); } /// visitJumpTable - Emit JumpTable node in the current MBB @@ -1606,9 +1606,6 @@ SDOperand CopyTo = DAG.getCopyToReg(getControlRoot(), SwitchReg, SwitchVal); B.Reg = SwitchReg; - SDOperand BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp, - DAG.getBasicBlock(B.Default)); - // Set NextBlock to be the MBB immediately after the current one, if any. // This is used to avoid emitting unnecessary branches to the next block. MachineBasicBlock *NextBlock = 0; @@ -1617,15 +1614,19 @@ NextBlock = BBI; MachineBasicBlock* MBB = B.Cases[0].ThisBB; + + CurMBB->addSuccessor(B.Default); + CurMBB->addSuccessor(MBB); + + SDOperand BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp, + DAG.getBasicBlock(B.Default)); + if (MBB == NextBlock) DAG.setRoot(BrRange); else DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo, DAG.getBasicBlock(MBB))); - CurMBB->addSuccessor(B.Default); - CurMBB->addSuccessor(MBB); - return; } @@ -1643,6 +1644,10 @@ SDOperand AndCmp = DAG.getSetCC(TLI.getSetCCResultType(AndOp), AndOp, DAG.getConstant(0, TLI.getPointerTy()), ISD::SETNE); + + CurMBB->addSuccessor(B.TargetBB); + CurMBB->addSuccessor(NextMBB); + SDOperand BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(), AndCmp, DAG.getBasicBlock(B.TargetBB)); @@ -1659,9 +1664,6 @@ DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd, DAG.getBasicBlock(NextMBB))); - CurMBB->addSuccessor(B.TargetBB); - CurMBB->addSuccessor(NextMBB); - return; } @@ -1683,13 +1685,13 @@ CopyValueToVirtualRegister(&I, VMI->second); } - // Drop into normal successor. - DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(), - DAG.getBasicBlock(Return))); - // Update successor info CurMBB->addSuccessor(Return); CurMBB->addSuccessor(LandingPad); + + // Drop into normal successor. + DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(), + DAG.getBasicBlock(Return))); } void SelectionDAGLowering::visitUnwind(UnwindInst &I) { @@ -2178,11 +2180,11 @@ // Update machine-CFG edges. // If this is not a fall-through branch, emit the branch. + CurMBB->addSuccessor(Default); if (Default != NextBlock) DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(), DAG.getBasicBlock(Default))); - - CurMBB->addSuccessor(Default); + return; } From dalej at apple.com Fri Jun 6 20:19:34 2008 From: dalej at apple.com (Dale Johannesen) Date: Sat, 07 Jun 2008 01:19:34 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r52068 - in /llvm-gcc-4.2/trunk/gcc/config/i386: llvm-i386-target.h llvm-i386.cpp Message-ID: <200806070119.m571JYNa020799@zion.cs.uiuc.edu> Author: johannes Date: Fri Jun 6 20:19:33 2008 New Revision: 52068 URL: http://llvm.org/viewvc/llvm-project?rev=52068&view=rev Log: MMX vectors return in XMM0 on darwin x86-64. (Maybe linux too? but not win64). Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h?rev=52068&r1=52067&r2=52068&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h (original) +++ llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h Fri Jun 6 20:19:33 2008 @@ -91,12 +91,15 @@ (TARGET_64BIT ? 0 : \ TARGET_SSE && contains_128bit_aligned_vector_p(T) ? 16 : 4) +extern tree llvm_x86_should_return_selt_struct_as_scalar(tree); + /* Structs containing a single data field plus zero-length fields are - considered as if they were the type of the data field. */ -#ifndef LLVM_SHOULD_RETURN_SELT_STRUCT_AS_SCALAR + considered as if they were the type of the data field. On x86-64, + if the element type is an MMX vector, return it as double (which will + get it into XMM0). */ + #define LLVM_SHOULD_RETURN_SELT_STRUCT_AS_SCALAR(X) \ - isSingleElementStructOrArray(X, true, false) -#endif + llvm_x86_should_return_selt_struct_as_scalar((X)) extern bool llvm_x86_should_pass_aggregate_in_integer_regs(tree, unsigned*, bool*); Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp?rev=52068&r1=52067&r2=52068&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp Fri Jun 6 20:19:33 2008 @@ -872,6 +872,22 @@ return 0; } +/* MMX vectors are returned in XMM0 on x86-64 Darwin. The easiest way to + communicate this is pretend they're doubles. + Judging from comments, this would not be right for Win64. Don't know + about Linux. */ +tree llvm_x86_should_return_selt_struct_as_scalar(tree type) { + tree retType = isSingleElementStructOrArray(type, true, false); + if (!retType || !TARGET_64BIT || !TARGET_MACHO) + return retType; + if (TREE_CODE(retType) == VECTOR_TYPE && + TYPE_SIZE(retType) && + TREE_CODE(TYPE_SIZE(retType))==INTEGER_CST && + TREE_INT_CST_LOW(TYPE_SIZE(retType))==64) + return double_type_node; + return retType; +} + /* MMX vectors v2i32, v4i16, v8i8, v2f32 are returned using sret on Darwin 32-bit. Vectors bigger than 128 are returned using sret. */ bool llvm_x86_should_return_vector_as_shadow(tree type, bool isBuiltin) { From gohman at apple.com Fri Jun 6 21:02:36 2008 From: gohman at apple.com (Dan Gohman) Date: Sat, 07 Jun 2008 02:02:36 -0000 Subject: [llvm-commits] [llvm] r52069 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Message-ID: <200806070202.m5722aom022003@zion.cs.uiuc.edu> Author: djg Date: Fri Jun 6 21:02:36 2008 New Revision: 52069 URL: http://llvm.org/viewvc/llvm-project?rev=52069&view=rev Log: CodeGen support for insertvalue and extractvalue, and for loads and stores of aggregate values. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=52069&r1=52068&r2=52069&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Fri Jun 6 21:02:36 2008 @@ -87,28 +87,83 @@ namespace { struct SDISelAsmOperandInfo; } +/// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence +/// insertvalue or extractvalue indices that identify a member, return +/// the linearized index of the start of the member. +/// +static unsigned ComputeLinearIndex(const TargetLowering &TLI, const Type *Ty, + const unsigned *Indices, + const unsigned *IndicesEnd, + unsigned CurIndex = 0) { + // Base case: We're done. + if (Indices == IndicesEnd) + return CurIndex; + + // Otherwise we need to recurse. A non-negative value is used to + // indicate the final result value; a negative value carries the + // complemented position to continue the search. + CurIndex = ~CurIndex; + + // Given a struct type, recursively traverse the elements. + if (const StructType *STy = dyn_cast(Ty)) { + for (StructType::element_iterator EI = STy->element_begin(), + EE = STy->element_end(); + EI != EE; ++EI) { + CurIndex = ComputeLinearIndex(TLI, *EI, Indices+1, IndicesEnd, + ~CurIndex); + if ((int)CurIndex >= 0) + return CurIndex; + } + } + // Given an array type, recursively traverse the elements. + else if (const ArrayType *ATy = dyn_cast(Ty)) { + const Type *EltTy = ATy->getElementType(); + for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) { + CurIndex = ComputeLinearIndex(TLI, EltTy, Indices+1, IndicesEnd, + ~CurIndex); + if ((int)CurIndex >= 0) + return CurIndex; + } + } + // We haven't found the type we're looking for, so keep searching. + return CurIndex; +} + /// ComputeValueVTs - Given an LLVM IR type, compute a sequence of /// MVTs that represent all the individual underlying /// non-aggregate types that comprise it. +/// +/// If Offsets is non-null, it points to a vector to be filled in +/// with the in-memory offsets of each of the individual values. +/// static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty, - SmallVectorImpl &ValueVTs) { + SmallVectorImpl &ValueVTs, + SmallVectorImpl *Offsets = 0, + uint64_t StartingOffset = 0) { // Given a struct type, recursively traverse the elements. if (const StructType *STy = dyn_cast(Ty)) { - for (StructType::element_iterator EI = STy->element_begin(), - EB = STy->element_end(); - EI != EB; ++EI) - ComputeValueVTs(TLI, *EI, ValueVTs); + const StructLayout *SL = TLI.getTargetData()->getStructLayout(STy); + for (StructType::element_iterator EB = STy->element_begin(), + EI = EB, + EE = STy->element_end(); + EI != EE; ++EI) + ComputeValueVTs(TLI, *EI, ValueVTs, Offsets, + StartingOffset + SL->getElementOffset(EI - EB)); return; } // Given an array type, recursively traverse the elements. if (const ArrayType *ATy = dyn_cast(Ty)) { const Type *EltTy = ATy->getElementType(); + uint64_t EltSize = TLI.getTargetData()->getABITypeSize(EltTy); for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) - ComputeValueVTs(TLI, EltTy, ValueVTs); + ComputeValueVTs(TLI, EltTy, ValueVTs, Offsets, + StartingOffset + i * EltSize); return; } // Base case: we can get an MVT for this LLVM IR type. ValueVTs.push_back(TLI.getValueType(Ty)); + if (Offsets) + Offsets->push_back(StartingOffset); } namespace { @@ -703,8 +758,8 @@ void visitInsertElement(User &I); void visitShuffleVector(User &I); - void visitExtractValue(User &I); - void visitInsertValue(User &I); + void visitExtractValue(ExtractValueInst &I); + void visitInsertValue(InsertValueInst &I); void visitGetElementPtr(User &I); void visitSelect(User &I); @@ -1083,7 +1138,8 @@ if (ConstantFP *CFP = dyn_cast(C)) return N = DAG.getConstantFP(CFP->getValueAPF(), VT); - if (isa(C) && !isa(V->getType())) + if (isa(C) && !isa(V->getType()) && + !V->getType()->isAggregateType()) return N = DAG.getNode(ISD::UNDEF, VT); if (ConstantExpr *CE = dyn_cast(C)) { @@ -1093,6 +1149,63 @@ return N1; } + if (isa(C) || isa(C)) { + SmallVector Constants; + SmallVector ValueVTs; + for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end(); + OI != OE; ++OI) { + SDNode *Val = getValue(*OI).Val; + for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) { + Constants.push_back(SDOperand(Val, i)); + ValueVTs.push_back(Val->getValueType(i)); + } + } + return DAG.getNode(ISD::MERGE_VALUES, + DAG.getVTList(&ValueVTs[0], ValueVTs.size()), + &Constants[0], Constants.size()); + } + + if (const ArrayType *ATy = dyn_cast(C->getType())) { + assert((isa(C) || isa(C)) && + "Unknown array constant!"); + unsigned NumElts = ATy->getNumElements(); + MVT EltVT = TLI.getValueType(ATy->getElementType()); + SmallVector Constants(NumElts); + SmallVector ValueVTs(NumElts, EltVT); + for (unsigned i = 0, e = NumElts; i != e; ++i) { + if (isa(C)) + Constants[i] = DAG.getNode(ISD::UNDEF, EltVT); + else if (EltVT.isFloatingPoint()) + Constants[i] = DAG.getConstantFP(0, EltVT); + else + Constants[i] = DAG.getConstant(0, EltVT); + } + return DAG.getNode(ISD::MERGE_VALUES, + DAG.getVTList(&ValueVTs[0], ValueVTs.size()), + &Constants[0], Constants.size()); + } + + if (const StructType *STy = dyn_cast(C->getType())) { + assert((isa(C) || isa(C)) && + "Unknown struct constant!"); + unsigned NumElts = STy->getNumElements(); + SmallVector Constants(NumElts); + SmallVector ValueVTs(NumElts); + for (unsigned i = 0, e = NumElts; i != e; ++i) { + MVT EltVT = TLI.getValueType(STy->getElementType(i)); + ValueVTs[i] = EltVT; + if (isa(C)) + Constants[i] = DAG.getNode(ISD::UNDEF, EltVT); + else if (EltVT.isFloatingPoint()) + Constants[i] = DAG.getConstantFP(0, EltVT); + else + Constants[i] = DAG.getConstant(0, EltVT); + } + return DAG.getNode(ISD::MERGE_VALUES, + DAG.getVTList(&ValueVTs[0], ValueVTs.size()), + &Constants[0], Constants.size()); + } + const VectorType *VecTy = cast(V->getType()); unsigned NumElements = VecTy->getNumElements(); @@ -2560,14 +2673,72 @@ V1, V2, Mask)); } -void SelectionDAGLowering::visitInsertValue(User &I) { - assert(0 && "insertvalue instruction not implemented"); - abort(); -} +void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) { + const Value *Op0 = I.getOperand(0); + const Value *Op1 = I.getOperand(1); + const Type *AggTy = I.getType(); + const Type *ValTy = Op1->getType(); + bool IntoUndef = isa(Op0); + bool FromUndef = isa(Op1); + + unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy, + I.idx_begin(), I.idx_end()); + + SmallVector AggValueVTs; + ComputeValueVTs(TLI, AggTy, AggValueVTs); + SmallVector ValValueVTs; + ComputeValueVTs(TLI, ValTy, ValValueVTs); + + unsigned NumAggValues = AggValueVTs.size(); + unsigned NumValValues = ValValueVTs.size(); + SmallVector Values(NumAggValues); -void SelectionDAGLowering::visitExtractValue(User &I) { - assert(0 && "extractvalue instruction not implemented"); - abort(); + SDOperand Agg = getValue(Op0); + SDOperand Val = getValue(Op1); + unsigned i = 0; + // Copy the beginning value(s) from the original aggregate. + for (; i != LinearIndex; ++i) + Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) : + SDOperand(Agg.Val, Agg.ResNo + i); + // Copy values from the inserted value(s). + for (; i != LinearIndex + NumValValues; ++i) + Values[i] = FromUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) : + SDOperand(Val.Val, Val.ResNo + i - LinearIndex); + // Copy remaining value(s) from the original aggregate. + for (; i != NumAggValues; ++i) + Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) : + SDOperand(Agg.Val, Agg.ResNo + i); + + setValue(&I, DAG.getNode(ISD::MERGE_VALUES, + DAG.getVTList(&AggValueVTs[0], NumAggValues), + &Values[0], NumAggValues)); +} + +void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) { + const Value *Op0 = I.getOperand(0); + const Type *AggTy = Op0->getType(); + const Type *ValTy = I.getType(); + bool OutOfUndef = isa(Op0); + + unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy, + I.idx_begin(), I.idx_end()); + + SmallVector ValValueVTs; + ComputeValueVTs(TLI, ValTy, ValValueVTs); + + unsigned NumValValues = ValValueVTs.size(); + SmallVector Values(NumValValues); + + SDOperand Agg = getValue(Op0); + // Copy out the selected value(s). + for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i) + Values[i - LinearIndex] = + OutOfUndef ? DAG.getNode(ISD::UNDEF, Agg.Val->getValueType(i)) : + SDOperand(Agg.Val, Agg.ResNo + i - LinearIndex); + + setValue(&I, DAG.getNode(ISD::MERGE_VALUES, + DAG.getVTList(&ValValueVTs[0], NumValValues), + &Values[0], NumValValues)); } @@ -2698,25 +2869,61 @@ const Value *SV, SDOperand Root, bool isVolatile, unsigned Alignment) { - SDOperand L = - DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SV, 0, - isVolatile, Alignment); - + SmallVector ValueVTs; + SmallVector Offsets; + ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets); + unsigned NumValues = ValueVTs.size(); + + SmallVector Values(NumValues); + SmallVector Chains(NumValues); + MVT PtrVT = Ptr.getValueType(); + for (unsigned i = 0; i != NumValues; ++i) { + SDOperand L = DAG.getLoad(ValueVTs[i], Root, + DAG.getNode(ISD::ADD, PtrVT, Ptr, + DAG.getConstant(Offsets[i], PtrVT)), + SV, Offsets[i], + isVolatile, Alignment); + Values[i] = L; + Chains[i] = L.getValue(1); + } + + SDOperand Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, + &Chains[0], NumValues); if (isVolatile) - DAG.setRoot(L.getValue(1)); + DAG.setRoot(Chain); else - PendingLoads.push_back(L.getValue(1)); - - return L; + PendingLoads.push_back(Chain); + + return DAG.getNode(ISD::MERGE_VALUES, + DAG.getVTList(&ValueVTs[0], NumValues), + &Values[0], NumValues); } void SelectionDAGLowering::visitStore(StoreInst &I) { Value *SrcV = I.getOperand(0); SDOperand Src = getValue(SrcV); - SDOperand Ptr = getValue(I.getOperand(1)); - DAG.setRoot(DAG.getStore(getRoot(), Src, Ptr, I.getOperand(1), 0, - I.isVolatile(), I.getAlignment())); + Value *PtrV = I.getOperand(1); + SDOperand Ptr = getValue(PtrV); + + SmallVector ValueVTs; + SmallVector Offsets; + ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets); + unsigned NumValues = ValueVTs.size(); + + SDOperand Root = getRoot(); + SmallVector Chains(NumValues); + MVT PtrVT = Ptr.getValueType(); + bool isVolatile = I.isVolatile(); + unsigned Alignment = I.getAlignment(); + for (unsigned i = 0; i != NumValues; ++i) + Chains[i] = DAG.getStore(Root, SDOperand(Src.Val, Src.ResNo + i), + DAG.getNode(ISD::ADD, PtrVT, Ptr, + DAG.getConstant(Offsets[i], PtrVT)), + PtrV, Offsets[i], + isVolatile, Alignment); + + DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumValues)); } /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC From evan.cheng at apple.com Sat Jun 7 02:49:58 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Sat, 7 Jun 2008 00:49:58 -0700 Subject: [llvm-commits] [llvm] r52046 - /llvm/trunk/lib/Target/CBackend/CBackend.cpp In-Reply-To: <200806061608.m56G8ReF032045@zion.cs.uiuc.edu> References: <200806061608.m56G8ReF032045@zion.cs.uiuc.edu> Message-ID: <48F00711-ADDA-45AC-A783-2B1759BC3E9A@apple.com> Hi Anton, This breaks cbe on x86 Mac OS X pretty badly. Lots of tests are failing with this: gcc Output/cfrac.cbe.c -o Output/cfrac.cbe -lm -O3 -fno-strict- aliasing -fno-inline -mdynamic-no-pic -fomit-frame-pointer Output/cfrac.cbe.c:380: warning: conflicting types for built-in function 'malloc' Output/cfrac.cbe.c:385: warning: conflicting types for built-in function 'sqrtl' Output/cfrac.cbe.c: In function 'main': Output/cfrac.cbe.c:2978: warning: return type of 'main' is not 'int' /var/tmp//ccU4O5JJ.s:8875:FATAL:Symbol LC1 already defined. make[1]: [Output/cfrac.cbe] Error 1 (ignored) I'll back it out for now. Please fix. Thanks, Evan On Jun 6, 2008, at 9:08 AM, Anton Korobeynikov wrote: > Author: asl > Date: Fri Jun 6 11:08:26 2008 > New Revision: 52046 > > URL: http://llvm.org/viewvc/llvm-project?rev=52046&view=rev > Log: > Handle assembler identifiers specially in CBE. This fixes PR2418. > > Modified: > llvm/trunk/lib/Target/CBackend/CBackend.cpp > > Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CBackend.cpp?rev=52046&r1=52045&r2=52046&view=diff > > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/Target/CBackend/CBackend.cpp (original) > +++ llvm/trunk/lib/Target/CBackend/CBackend.cpp Fri Jun 6 11:08:26 > 2008 > @@ -1224,6 +1224,10 @@ > Name = "llvm_cbe_" + VarName; > } else { > Name = Mang->getValueName(Operand); > + > + // Check, if operand has assembler identifier and handle it > separately > + if (Operand->getNameStart()[0] == 1) > + Name = "llvm_cbe_asmname_" + Name; > } > > return Name; > @@ -1652,6 +1656,11 @@ > > if (I->hasExternalWeakLinkage()) > Out << " __EXTERNAL_WEAK__"; > + > + // Special handling for assembler identifiers > + if (I->getNameStart()[0] == 1) > + Out << " LLVM_ASM(\"" << I->getName().c_str()+1 << "\")"; > + > Out << ";\n"; > } > } > @@ -1661,7 +1670,7 @@ > Out << "double fmod(double, double);\n"; // Support for FP rem > Out << "float fmodf(float, float);\n"; > Out << "long double fmodl(long double, long double);\n"; > - > + > for (Module::iterator I = M.begin(), E = M.end(); I != E; ++I) { > // Don't print declarations for intrinsic functions. > if (!I->isIntrinsic() && I->getName() != "setjmp" && > @@ -1669,7 +1678,7 @@ > if (I->hasExternalWeakLinkage()) > Out << "extern "; > printFunctionSignature(I, true); > - if (I->hasWeakLinkage() || I->hasLinkOnceLinkage()) > + if (I->hasWeakLinkage() || I->hasLinkOnceLinkage()) > Out << " __ATTRIBUTE_WEAK__"; > if (I->hasExternalWeakLinkage()) > Out << " __EXTERNAL_WEAK__"; > @@ -1679,10 +1688,11 @@ > Out << " __ATTRIBUTE_DTOR__"; > if (I->hasHiddenVisibility()) > Out << " __HIDDEN__"; > - > - if (I->hasName() && I->getName()[0] == 1) > + > + // Special handling for assembler identifiers > + if (I->getNameStart()[0] == 1) > Out << " LLVM_ASM(\"" << I->getName().c_str()+1 << "\")"; > - > + > Out << ";\n"; > } > } > @@ -1719,6 +1729,11 @@ > Out << " __EXTERNAL_WEAK__"; > if (I->hasHiddenVisibility()) > Out << " __HIDDEN__"; > + > + // Special handling for assembler identifiers > + if (I->getNameStart()[0] == 1) > + Out << " LLVM_ASM(\"" << I->getName().c_str()+1 << "\")"; > + > Out << ";\n"; > } > } > @@ -1726,7 +1741,7 @@ > // Output the global variable definitions and contents... > if (!M.global_empty()) { > Out << "\n\n/* Global Variable Definitions and Initialization */ > \n"; > - for (Module::global_iterator I = M.global_begin(), E = > M.global_end(); > + for (Module::global_iterator I = M.global_begin(), E = > M.global_end(); > I != E; ++I) > if (!I->isDeclaration()) { > // Ignore special globals, such as debug info. > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From evan.cheng at apple.com Sat Jun 7 02:50:29 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Sat, 07 Jun 2008 07:50:29 -0000 Subject: [llvm-commits] [llvm] r52071 - /llvm/trunk/lib/Target/CBackend/CBackend.cpp Message-ID: <200806070750.m577oTEh006989@zion.cs.uiuc.edu> Author: evancheng Date: Sat Jun 7 02:50:29 2008 New Revision: 52071 URL: http://llvm.org/viewvc/llvm-project?rev=52071&view=rev Log: Revert r52046. It broke cbe on x86 / Mac OS X. Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CBackend.cpp?rev=52071&r1=52070&r2=52071&view=diff ============================================================================== --- llvm/trunk/lib/Target/CBackend/CBackend.cpp (original) +++ llvm/trunk/lib/Target/CBackend/CBackend.cpp Sat Jun 7 02:50:29 2008 @@ -1224,10 +1224,6 @@ Name = "llvm_cbe_" + VarName; } else { Name = Mang->getValueName(Operand); - - // Check, if operand has assembler identifier and handle it separately - if (Operand->getNameStart()[0] == 1) - Name = "llvm_cbe_asmname_" + Name; } return Name; @@ -1656,11 +1652,6 @@ if (I->hasExternalWeakLinkage()) Out << " __EXTERNAL_WEAK__"; - - // Special handling for assembler identifiers - if (I->getNameStart()[0] == 1) - Out << " LLVM_ASM(\"" << I->getName().c_str()+1 << "\")"; - Out << ";\n"; } } @@ -1670,7 +1661,7 @@ Out << "double fmod(double, double);\n"; // Support for FP rem Out << "float fmodf(float, float);\n"; Out << "long double fmodl(long double, long double);\n"; - + for (Module::iterator I = M.begin(), E = M.end(); I != E; ++I) { // Don't print declarations for intrinsic functions. if (!I->isIntrinsic() && I->getName() != "setjmp" && @@ -1678,7 +1669,7 @@ if (I->hasExternalWeakLinkage()) Out << "extern "; printFunctionSignature(I, true); - if (I->hasWeakLinkage() || I->hasLinkOnceLinkage()) + if (I->hasWeakLinkage() || I->hasLinkOnceLinkage()) Out << " __ATTRIBUTE_WEAK__"; if (I->hasExternalWeakLinkage()) Out << " __EXTERNAL_WEAK__"; @@ -1688,11 +1679,10 @@ Out << " __ATTRIBUTE_DTOR__"; if (I->hasHiddenVisibility()) Out << " __HIDDEN__"; - - // Special handling for assembler identifiers - if (I->getNameStart()[0] == 1) + + if (I->hasName() && I->getName()[0] == 1) Out << " LLVM_ASM(\"" << I->getName().c_str()+1 << "\")"; - + Out << ";\n"; } } @@ -1729,11 +1719,6 @@ Out << " __EXTERNAL_WEAK__"; if (I->hasHiddenVisibility()) Out << " __HIDDEN__"; - - // Special handling for assembler identifiers - if (I->getNameStart()[0] == 1) - Out << " LLVM_ASM(\"" << I->getName().c_str()+1 << "\")"; - Out << ";\n"; } } @@ -1741,7 +1726,7 @@ // Output the global variable definitions and contents... if (!M.global_empty()) { Out << "\n\n/* Global Variable Definitions and Initialization */\n"; - for (Module::global_iterator I = M.global_begin(), E = M.global_end(); + for (Module::global_iterator I = M.global_begin(), E = M.global_end(); I != E; ++I) if (!I->isDeclaration()) { // Ignore special globals, such as debug info. From evan.cheng at apple.com Sat Jun 7 03:40:16 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Sat, 07 Jun 2008 08:40:16 -0000 Subject: [llvm-commits] [llvm] r52072 - /llvm/trunk/test/Transforms/SimplifyCFG/branch-fold-test.ll Message-ID: <200806070840.m578eGZq008265@zion.cs.uiuc.edu> Author: evancheng Date: Sat Jun 7 03:40:16 2008 New Revision: 52072 URL: http://llvm.org/viewvc/llvm-project?rev=52072&view=rev Log: Fix run line. Modified: llvm/trunk/test/Transforms/SimplifyCFG/branch-fold-test.ll Modified: llvm/trunk/test/Transforms/SimplifyCFG/branch-fold-test.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/branch-fold-test.ll?rev=52072&r1=52071&r2=52072&view=diff ============================================================================== --- llvm/trunk/test/Transforms/SimplifyCFG/branch-fold-test.ll (original) +++ llvm/trunk/test/Transforms/SimplifyCFG/branch-fold-test.ll Sat Jun 7 03:40:16 2008 @@ -1,7 +1,7 @@ ; This test ensures that the simplifycfg pass continues to constant fold ; terminator instructions. -; RUN: llvm-as < %s | opt -simplifycfg | not grep br +; RUN: llvm-as < %s | opt -simplifycfg | llvm-dis | not grep br define i32 @test(i32 %A, i32 %B) { J: From evan.cheng at apple.com Sat Jun 7 03:52:29 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Sat, 07 Jun 2008 08:52:29 -0000 Subject: [llvm-commits] [llvm] r52073 - in /llvm/trunk: lib/Transforms/Utils/SimplifyCFG.cpp test/Transforms/SimplifyCFG/SpeculativeExec.ll Message-ID: <200806070852.m578qTpD008596@zion.cs.uiuc.edu> Author: evancheng Date: Sat Jun 7 03:52:29 2008 New Revision: 52073 URL: http://llvm.org/viewvc/llvm-project?rev=52073&view=rev Log: Speculatively execute a block when the the block is the then part of a triangle shape and it contains a single, side effect free, cheap instruction. The branch is eliminated by adding a select instruction. i.e. Turn BB: %t1 = icmp br i1 %t1, label %BB1, label %BB2 BB1: %t3 = add %t2, c br label BB2 BB2: => BB: %t1 = icmp %t4 = add %t2, c %t3 = select i1 %t1, %t2, %t3 Added: llvm/trunk/test/Transforms/SimplifyCFG/SpeculativeExec.ll Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=52073&r1=52072&r2=52073&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Sat Jun 7 03:52:29 2008 @@ -955,6 +955,109 @@ return true; } +/// SpeculativelyExecuteBB - Given a conditional branch that goes to BB1 +/// and an BB2 and the only successor of BB1 is BB2, hoist simple code +/// (for now, restricted to a single instruction that's side effect free) from +/// the BB1 into the branch block to speculatively execute it. +static bool SpeculativelyExecuteBB(BranchInst *BI, BasicBlock *BB1) { + // Only speculatively execution a single instruction (not counting the + // terminator) for now. + if (BB1->size() != 2) + return false; + + // If BB1 is actually on the false edge of the conditional branch, remember + // to swap the select operands later. + bool Invert = false; + if (BB1 != BI->getSuccessor(0)) { + assert(BB1 == BI->getSuccessor(1) && "No edge from 'if' block?"); + Invert = true; + } + + // Turn + // BB: + // %t1 = icmp + // br i1 %t1, label %BB1, label %BB2 + // BB1: + // %t3 = add %t2, c + // br label BB2 + // BB2: + // => + // BB: + // %t1 = icmp + // %t4 = add %t2, c + // %t3 = select i1 %t1, %t2, %t3 + Instruction *I = BB1->begin(); + switch (I->getOpcode()) { + default: return false; // Not safe / profitable to hoist. + case Instruction::Add: + case Instruction::Sub: + case Instruction::And: + case Instruction::Or: + case Instruction::Xor: + case Instruction::Shl: + case Instruction::LShr: + case Instruction::AShr: + if (I->getOperand(0)->getType()->isFPOrFPVector()) + return false; // FP arithmetic might trap. + break; // These are all cheap and non-trapping instructions. + } + + // Can we speculatively execute the instruction? And what is the value + // if the condition is false? Consider the phi uses, if the incoming value + // from the "if" block are all the same V, then V is the value of the + // select if the condition is false. + BasicBlock *BIParent = BI->getParent(); + SmallVector PHIUses; + Value *FalseV = NULL; + for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); + UI != E; ++UI) { + PHINode *PN = dyn_cast(UI); + if (!PN) + continue; + PHIUses.push_back(PN); + Value *PHIV = PN->getIncomingValueForBlock(BIParent); + if (!FalseV) + FalseV = PHIV; + else if (FalseV != PHIV) + return false; // Don't know the value when condition is false. + } + if (!FalseV) // Can this happen? + return false; + + // If we get here, we can hoist the instruction. Try to place it before the + // icmp / fcmp instruction preceeding the conditional branch. + BasicBlock::iterator InsertPos = BI; + if (InsertPos != BIParent->begin()) + --InsertPos; + if (InsertPos->getOpcode() == Instruction::ICmp || + InsertPos->getOpcode() == Instruction::FCmp) + BIParent->getInstList().splice(InsertPos, BB1->getInstList(), I); + else + BIParent->getInstList().splice(BI, BB1->getInstList(), I); + + // Create a select whose true value is the speculatively executed value and + // false value is the previously determined FalseV. + SelectInst *SI; + if (Invert) + SI = SelectInst::Create(BI->getCondition(), FalseV, I, + FalseV->getName() + "." + I->getName(), BI); + else + SI = SelectInst::Create(BI->getCondition(), I, FalseV, + I->getName() + "." + FalseV->getName(), BI); + + // Make the PHI node use the select for all incoming values for "then" and + // "if" blocks. + for (unsigned i = 0, e = PHIUses.size(); i != e; ++i) { + PHINode *PN = PHIUses[i]; + for (unsigned j = 0, ee = PN->getNumIncomingValues(); j != ee; ++j) + if (PN->getIncomingBlock(j) == BB1 || + PN->getIncomingBlock(j) == BIParent) + PN->setIncomingValue(j, SI); + } + + return true; +} + /// BlockIsSimpleEnoughToThreadThrough - Return true if we can thread a branch /// across this block. static bool BlockIsSimpleEnoughToThreadThrough(BasicBlock *BB) { @@ -1928,6 +2031,24 @@ // so see if there is any identical code in the "then" and "else" // blocks. If so, we can hoist it up to the branching block. Changed |= HoistThenElseCodeToIf(BI); + } else { + OnlySucc = NULL; + for (succ_iterator SI = succ_begin(BB), SE = succ_end(BB); + SI != SE; ++SI) { + if (!OnlySucc) + OnlySucc = *SI; + else if (*SI != OnlySucc) { + OnlySucc = 0; // There are multiple distinct successors! + break; + } + } + + if (OnlySucc == OtherBB) { + // If BB's only successor is the other successor of the predecessor, + // i.e. a triangle, see if we can hoist any code from this block up + // to the "if" block. + Changed |= SpeculativelyExecuteBB(BI, BB); + } } } Added: llvm/trunk/test/Transforms/SimplifyCFG/SpeculativeExec.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/SpeculativeExec.ll?rev=52073&view=auto ============================================================================== --- llvm/trunk/test/Transforms/SimplifyCFG/SpeculativeExec.ll (added) +++ llvm/trunk/test/Transforms/SimplifyCFG/SpeculativeExec.ll Sat Jun 7 03:52:29 2008 @@ -0,0 +1,21 @@ +; RUN: llvm-as < %s | opt -simplifycfg | llvm-dis | grep select +; RUN: llvm-as < %s | opt -simplifycfg | llvm-dis | grep br | count 2 + +define i32 @t2(i32 %a, i32 %b, i32 %c) nounwind { +entry: + %tmp1 = icmp eq i32 %b, 0 + br i1 %tmp1, label %bb1, label %bb3 + +bb1: ; preds = %entry + %tmp2 = icmp sgt i32 %c, 1 + br i1 %tmp2, label %bb2, label %bb3 + +bb2: ; preds = bb1 + %tmp3 = add i32 %a, 1 + br label %bb3 + +bb3: ; preds = %bb2, %entry + %tmp4 = phi i32 [ %b, %entry ], [ %a, %bb1 ], [ %tmp3, %bb2 ] + %tmp5 = sub i32 %tmp4, 1 + ret i32 %tmp5 +} From sabre at nondot.org Sat Jun 7 14:33:54 2008 From: sabre at nondot.org (Chris Lattner) Date: Sat, 07 Jun 2008 19:33:54 -0000 Subject: [llvm-commits] [llvm] r52077 - in /llvm/trunk/win32: Analysis/Analysis.vcproj CodeGen/CodeGen.vcproj Message-ID: <200806071933.m57JXsCV026375@zion.cs.uiuc.edu> Author: lattner Date: Sat Jun 7 14:33:54 2008 New Revision: 52077 URL: http://llvm.org/viewvc/llvm-project?rev=52077&view=rev Log: Update VC project files, patch by C?dric Venet! Modified: llvm/trunk/win32/Analysis/Analysis.vcproj llvm/trunk/win32/CodeGen/CodeGen.vcproj Modified: llvm/trunk/win32/Analysis/Analysis.vcproj URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/win32/Analysis/Analysis.vcproj?rev=52077&r1=52076&r2=52077&view=diff ============================================================================== --- llvm/trunk/win32/Analysis/Analysis.vcproj (original) +++ llvm/trunk/win32/Analysis/Analysis.vcproj Sat Jun 7 14:33:54 2008 @@ -408,6 +408,10 @@ RelativePath="..\..\lib\Analysis\ValueNumbering.cpp" > + + Modified: llvm/trunk/win32/CodeGen/CodeGen.vcproj URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/win32/CodeGen/CodeGen.vcproj?rev=52077&r1=52076&r2=52077&view=diff ============================================================================== --- llvm/trunk/win32/CodeGen/CodeGen.vcproj (original) +++ llvm/trunk/win32/CodeGen/CodeGen.vcproj Sat Jun 7 14:33:54 2008 @@ -353,6 +353,10 @@ > + + @@ -473,6 +477,10 @@ > + + From bruno.cardoso at gmail.com Sat Jun 7 16:32:41 2008 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Sat, 07 Jun 2008 21:32:41 -0000 Subject: [llvm-commits] [llvm] r52079 - /llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td Message-ID: <200806072132.m57LWfrE029532@zion.cs.uiuc.edu> Author: bruno Date: Sat Jun 7 16:32:41 2008 New Revision: 52079 URL: http://llvm.org/viewvc/llvm-project?rev=52079&view=rev Log: Added support for FP Registers Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td?rev=52079&r1=52078&r2=52079&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td (original) +++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td Sat Jun 7 16:32:41 2008 @@ -17,6 +17,10 @@ let Namespace = "Mips"; } +//===----------------------------------------------------------------------===// +// General Purpose Registers +//===----------------------------------------------------------------------===// + // Mips CPU Registers class MipsGPRReg num, string n> : MipsReg { let Num = num; @@ -24,37 +28,37 @@ // CPU GPR Registers def ZERO : MipsGPRReg< 0, "ZERO">, DwarfRegNum<[0]>; -def AT : MipsGPRReg< 1, "AT">, DwarfRegNum<[1]>; -def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>; -def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>; -def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[5]>; -def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>; -def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>; -def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>; -def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>; -def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>; -def T2 : MipsGPRReg< 10, "10">, DwarfRegNum<[10]>; -def T3 : MipsGPRReg< 11, "11">, DwarfRegNum<[11]>; -def T4 : MipsGPRReg< 12, "12">, DwarfRegNum<[12]>; -def T5 : MipsGPRReg< 13, "13">, DwarfRegNum<[13]>; -def T6 : MipsGPRReg< 14, "14">, DwarfRegNum<[14]>; -def T7 : MipsGPRReg< 15, "15">, DwarfRegNum<[15]>; -def S0 : MipsGPRReg< 16, "16">, DwarfRegNum<[16]>; -def S1 : MipsGPRReg< 17, "17">, DwarfRegNum<[17]>; -def S2 : MipsGPRReg< 18, "18">, DwarfRegNum<[18]>; -def S3 : MipsGPRReg< 19, "19">, DwarfRegNum<[19]>; -def S4 : MipsGPRReg< 20, "20">, DwarfRegNum<[20]>; -def S5 : MipsGPRReg< 21, "21">, DwarfRegNum<[21]>; -def S6 : MipsGPRReg< 22, "22">, DwarfRegNum<[22]>; -def S7 : MipsGPRReg< 23, "23">, DwarfRegNum<[23]>; -def T8 : MipsGPRReg< 24, "24">, DwarfRegNum<[24]>; -def T9 : MipsGPRReg< 25, "25">, DwarfRegNum<[25]>; -def K0 : MipsGPRReg< 26, "26">, DwarfRegNum<[26]>; -def K1 : MipsGPRReg< 27, "27">, DwarfRegNum<[27]>; -def GP : MipsGPRReg< 28, "GP">, DwarfRegNum<[28]>; -def SP : MipsGPRReg< 29, "SP">, DwarfRegNum<[29]>; -def FP : MipsGPRReg< 30, "FP">, DwarfRegNum<[30]>; -def RA : MipsGPRReg< 31, "RA">, DwarfRegNum<[31]>; +def AT : MipsGPRReg< 1, "AT">, DwarfRegNum<[1]>; +def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>; +def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>; +def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[5]>; +def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>; +def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>; +def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>; +def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>; +def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>; +def T2 : MipsGPRReg< 10, "10">, DwarfRegNum<[10]>; +def T3 : MipsGPRReg< 11, "11">, DwarfRegNum<[11]>; +def T4 : MipsGPRReg< 12, "12">, DwarfRegNum<[12]>; +def T5 : MipsGPRReg< 13, "13">, DwarfRegNum<[13]>; +def T6 : MipsGPRReg< 14, "14">, DwarfRegNum<[14]>; +def T7 : MipsGPRReg< 15, "15">, DwarfRegNum<[15]>; +def S0 : MipsGPRReg< 16, "16">, DwarfRegNum<[16]>; +def S1 : MipsGPRReg< 17, "17">, DwarfRegNum<[17]>; +def S2 : MipsGPRReg< 18, "18">, DwarfRegNum<[18]>; +def S3 : MipsGPRReg< 19, "19">, DwarfRegNum<[19]>; +def S4 : MipsGPRReg< 20, "20">, DwarfRegNum<[20]>; +def S5 : MipsGPRReg< 21, "21">, DwarfRegNum<[21]>; +def S6 : MipsGPRReg< 22, "22">, DwarfRegNum<[22]>; +def S7 : MipsGPRReg< 23, "23">, DwarfRegNum<[23]>; +def T8 : MipsGPRReg< 24, "24">, DwarfRegNum<[24]>; +def T9 : MipsGPRReg< 25, "25">, DwarfRegNum<[25]>; +def K0 : MipsGPRReg< 26, "26">, DwarfRegNum<[26]>; +def K1 : MipsGPRReg< 27, "27">, DwarfRegNum<[27]>; +def GP : MipsGPRReg< 28, "GP">, DwarfRegNum<[28]>; +def SP : MipsGPRReg< 29, "SP">, DwarfRegNum<[29]>; +def FP : MipsGPRReg< 30, "FP">, DwarfRegNum<[30]>; +def RA : MipsGPRReg< 31, "RA">, DwarfRegNum<[31]>; // CPU Registers Class def CPURegs : RegisterClass<"Mips", [i32], 32, @@ -78,3 +82,121 @@ } }]; } + +//===----------------------------------------------------------------------===// +// Floating Point Unit Registers (Single Precision) +//===----------------------------------------------------------------------===// + +/// Mips Single point precision FPU Register Format +class MipsFPUReg num, string n> : MipsReg { + let Num = num; +} + +/// Mips Single point precision FPU Registers +def F0 : MipsFPUReg< 0, "F0">, DwarfRegNum<[32]>; +def F1 : MipsFPUReg< 1, "F1">, DwarfRegNum<[33]>; +def F2 : MipsFPUReg< 2, "F2">, DwarfRegNum<[34]>; +def F3 : MipsFPUReg< 3, "F3">, DwarfRegNum<[35]>; +def F4 : MipsFPUReg< 4, "F4">, DwarfRegNum<[36]>; +def F5 : MipsFPUReg< 5, "F5">, DwarfRegNum<[37]>; +def F6 : MipsFPUReg< 6, "F6">, DwarfRegNum<[38]>; +def F7 : MipsFPUReg< 7, "F7">, DwarfRegNum<[39]>; +def F8 : MipsFPUReg< 8, "F8">, DwarfRegNum<[40]>; +def F9 : MipsFPUReg< 9, "F9">, DwarfRegNum<[41]>; +def F10 : MipsFPUReg<10, "F10">, DwarfRegNum<[42]>; +def F11 : MipsFPUReg<11, "F11">, DwarfRegNum<[43]>; +def F12 : MipsFPUReg<12, "F12">, DwarfRegNum<[44]>; +def F13 : MipsFPUReg<13, "F13">, DwarfRegNum<[45]>; +def F14 : MipsFPUReg<14, "F14">, DwarfRegNum<[46]>; +def F15 : MipsFPUReg<15, "F15">, DwarfRegNum<[47]>; +def F16 : MipsFPUReg<16, "F16">, DwarfRegNum<[48]>; +def F17 : MipsFPUReg<17, "F17">, DwarfRegNum<[49]>; +def F18 : MipsFPUReg<18, "F18">, DwarfRegNum<[50]>; +def F19 : MipsFPUReg<19, "F19">, DwarfRegNum<[51]>; +def F20 : MipsFPUReg<20, "F20">, DwarfRegNum<[52]>; +def F21 : MipsFPUReg<21, "F21">, DwarfRegNum<[53]>; +def F22 : MipsFPUReg<22, "F22">, DwarfRegNum<[54]>; +def F23 : MipsFPUReg<23, "F23">, DwarfRegNum<[55]>; +def F24 : MipsFPUReg<24, "F24">, DwarfRegNum<[56]>; +def F25 : MipsFPUReg<25, "F25">, DwarfRegNum<[57]>; +def F26 : MipsFPUReg<26, "F26">, DwarfRegNum<[58]>; +def F27 : MipsFPUReg<27, "F27">, DwarfRegNum<[59]>; +def F28 : MipsFPUReg<28, "F28">, DwarfRegNum<[60]>; +def F29 : MipsFPUReg<29, "F29">, DwarfRegNum<[61]>; +def F30 : MipsFPUReg<30, "F30">, DwarfRegNum<[62]>; +def F31 : MipsFPUReg<31, "F31">, DwarfRegNum<[63]>; + +/// FPU Single Point Precision Registers Class +def FPUDRegs : RegisterClass<"Mips", [f32], 32, + // Return Values and Arguments + [F0, F1, F2, F3, F12, F13, F14, F15, + // Not preserved across procedure calls + F4, F5, F6, F7, F8, F9, F10, F11, F16, F17, F18, F19, + // Callee save + F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30, + // Reserved + F31]> +{ + let MethodProtos = [{ + iterator allocation_order_end(const MachineFunction &MF) const; + }]; + let MethodBodies = [{ + FPUDRegsClass::iterator + FPUDRegsClass::allocation_order_end(const MachineFunction &MF) const { + // The last register on the list above is reserved + return end()-1; + } + }]; +} + +//===----------------------------------------------------------------------===// +// Floating Point Unit Registers (Double Precision) +//===----------------------------------------------------------------------===// + +/// Mips Double point precision FPU Register Format +class MipsFPUDReg num, string n, list aliases> : MipsReg { + let Num = num; + let Aliases = aliases; +} + +/// Mips Double point precision FPU Registers (aliased +/// with the single precision to hold 64 bit values) +def D0 : MipsFPUDReg< 0, "F0", [F0, F1]>, DwarfRegNum<[32]>; +def D1 : MipsFPUDReg< 2, "F2", [F2, F3]>, DwarfRegNum<[34]>; +def D2 : MipsFPUDReg< 4, "F4", [F4, F5]>, DwarfRegNum<[36]>; +def D3 : MipsFPUDReg< 6, "F6", [F6, F7]>, DwarfRegNum<[38]>; +def D4 : MipsFPUDReg< 8, "F8", [F8, F9]>, DwarfRegNum<[40]>; +def D5 : MipsFPUDReg<10, "F10", [F10, F11]>, DwarfRegNum<[42]>; +def D6 : MipsFPUDReg<12, "F12", [F12, F13]>, DwarfRegNum<[44]>; +def D7 : MipsFPUDReg<14, "F14", [F14, F15]>, DwarfRegNum<[46]>; +def D8 : MipsFPUDReg<16, "F16", [F16, F17]>, DwarfRegNum<[48]>; +def D9 : MipsFPUDReg<18, "F18", [F18, F19]>, DwarfRegNum<[50]>; +def D10 : MipsFPUDReg<20, "F20", [F20, F21]>, DwarfRegNum<[52]>; +def D11 : MipsFPUDReg<22, "F22", [F22, F23]>, DwarfRegNum<[54]>; +def D12 : MipsFPUDReg<24, "F24", [F24, F25]>, DwarfRegNum<[56]>; +def D13 : MipsFPUDReg<26, "F26", [F26, F27]>, DwarfRegNum<[58]>; +def D14 : MipsFPUDReg<28, "F28", [F28, F29]>, DwarfRegNum<[60]>; +def D15 : MipsFPUDReg<30, "F30", [F30, F31]>, DwarfRegNum<[62]>; + +/// FPU Single Point Precision Registers Class +def FPURegs : RegisterClass<"Mips", [f32], 32, + // Return Values and Arguments + [D0, D1, D6, D7, + // Not preserved across procedure calls + D2, D3, D4, D5, D8, D9, + // Callee save + D10, D11, D12, D13, D14, + // Reserved + D15]> +{ + let MethodProtos = [{ + iterator allocation_order_end(const MachineFunction &MF) const; + }]; + let MethodBodies = [{ + FPURegsClass::iterator + FPURegsClass::allocation_order_end(const MachineFunction &MF) const { + // The last register on the list above is reserved + return end()-1; + } + }]; +} From isanbard at gmail.com Sat Jun 7 20:36:24 2008 From: isanbard at gmail.com (Bill Wendling) Date: Sun, 08 Jun 2008 01:36:24 -0000 Subject: [llvm-commits] [llvm] r52085 - /llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Message-ID: <200806080136.m581aOvo003853@zion.cs.uiuc.edu> Author: void Date: Sat Jun 7 20:36:24 2008 New Revision: 52085 URL: http://llvm.org/viewvc/llvm-project?rev=52085&view=rev Log: Temporarily reverting r52056. It's causing PPC to fail to bootstrap. Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=52085&r1=52084&r2=52085&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Sat Jun 7 20:36:24 2008 @@ -363,9 +363,6 @@ } computeRegisterProperties(); - - // Preferred loop alignment is 16. - setPrefLoopAlignment(16); } /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate From bruno.cardoso at gmail.com Sat Jun 7 20:39:37 2008 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Sun, 08 Jun 2008 01:39:37 -0000 Subject: [llvm-commits] [llvm] r52086 - /llvm/trunk/lib/Target/Mips/MipsInstrFormats.td Message-ID: <200806080139.m581dbTi003998@zion.cs.uiuc.edu> Author: bruno Date: Sat Jun 7 20:39:36 2008 New Revision: 52086 URL: http://llvm.org/viewvc/llvm-project?rev=52086&view=rev Log: Added FP instruction formats. Modified: llvm/trunk/lib/Target/Mips/MipsInstrFormats.td Modified: llvm/trunk/lib/Target/Mips/MipsInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFormats.td?rev=52086&r1=52085&r2=52086&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrFormats.td (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrFormats.td Sat Jun 7 20:39:36 2008 @@ -10,7 +10,7 @@ //===----------------------------------------------------------------------===// // Describe MIPS instructions format // -// All the possible Mips fields are: +// CPU INSTRUCTION FORMATS // // opcode - operation code. // rs - src reg. @@ -102,3 +102,60 @@ let Inst{25-0} = addr; } +//===----------------------------------------------------------------------===// +// +// FLOAT POINT INSTRUCTION FORMATS +// +// opcode - operation code. +// fs - src reg. +// ft - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr). +// fd - dst reg, only used on 3 regs instr. +// fmt - double or single precision. +// funct - combined with opcode field give us an operation code. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Format FR instruction class in Mips : <|opcode|fmt|ft|fs|fd|funct|> +//===----------------------------------------------------------------------===// + +class FFR op, bits<6> _funct, bits<5> _fmt, dag outs, dag ins, + string asmstr, list pattern, InstrItinClass itin> : + MipsInst +{ + bits<5> fd; + bits<5> fs; + bits<5> ft; + bits<5> fmt; + bits<6> funct; + + let opcode = op; + let funct = _funct; + let fmt = _fmt; + + let Inst{25-21} = fmt; + let Inst{20-16} = ft; + let Inst{15-11} = fs; + let Inst{10-6} = fd; + let Inst{5-0} = funct; +} + +//===----------------------------------------------------------------------===// +// Format FI instruction class in Mips : <|opcode|fmt|ft|immediate|> +//===----------------------------------------------------------------------===// + +class FFI op, bits<5> _fmt, dag outs, dag ins, string asmstr, + list pattern, InstrItinClass itin>: + MipsInst +{ + bits<5> ft; + bits<5> fmt; + bits<16> imm16; + + let opcode = op; + let fmt = _fmt; + + let Inst{25-21} = fmt; + let Inst{20-16} = ft; + let Inst{15-0} = imm16; +} From evan at fallingsnow.net Sat Jun 7 17:50:59 2008 From: evan at fallingsnow.net (Evan Phoenix) Date: Sat, 7 Jun 2008 15:50:59 -0700 Subject: [llvm-commits] [PATCH] add StandardPasses.h Message-ID: <2F9B2296-72E6-4F7C-824D-7DA7777B595C@fallingsnow.net> I've refactored opt's AddStandardPasses function into a header so that others can easily use it as well. I didn't replace opt's version though, since it still contains the ability to run the verifier after each pass as well. - Evan Phoenix // evan at fallingsnow.net -------------- next part -------------- A non-text attachment was scrubbed... Name: llvm-patch-standardpasses.diff Type: application/octet-stream Size: 3925 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20080607/846b837e/attachment.obj -------------- next part -------------- From sabre at nondot.org Sat Jun 7 21:45:07 2008 From: sabre at nondot.org (Chris Lattner) Date: Sun, 08 Jun 2008 02:45:07 -0000 Subject: [llvm-commits] [llvm] r52087 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <200806080245.m582j7FY005762@zion.cs.uiuc.edu> Author: lattner Date: Sat Jun 7 21:45:07 2008 New Revision: 52087 URL: http://llvm.org/viewvc/llvm-project?rev=52087&view=rev Log: add some notes. Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=52087&r1=52086&r2=52087&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Sat Jun 7 21:45:07 2008 @@ -84,9 +84,22 @@ LLVM release to do this. One nice impact of this is that the LLVM regression test suite no longer depends on llvm-upgrade, which makes it run faster.

            -

            LLVM 2.3 renames the LLVMBuilder and LLVMFoldingBuilder classes to - IRBuilder.

            +

            LLVM API Changes:

            +
              +
            • Several core LLVM IR classes have migrated to use 'FOOCLASS::Create(...)' + instead of 'new FOOCLASS(...)' (e.g. where FOOCLASS=BasicBlock). We hope to + standardize on FOOCLASS::Create for all IR classes in the future, but not + all of them have been moved over yet.
              • +
            • LLVM 2.3 renames the LLVMBuilder and LLVMFoldingBuilder classes to + IRBuilder.
              • +
            • MRegisterInfo was renamed to TargetRegisterInfo.
              • +
            • The MappedFile class is gone, please use MemoryBuffer instead.
              • +
            • The '-enable-eh' flag to LLC has been removed. Now code should encode + whether it is safe to not generate unwind information for a function by + tagging the Function object with the 'nounwind' attribute.
              • + +
            @@ -172,7 +185,8 @@ Common linkage? -Atomic operation support, Alpha, X86, X86-64, PowerPC. "__sync_synchronize" +Atomic operation support, Alpha, X86, X86-64, PowerPC. "__sync_synchronize", +"__sync_val_compare_and_swap", etc"
            • The C and Ocaml bindings have received additional improvements. The @@ -184,31 +198,6 @@
              -Code Generator Improvements -
              - -
              - -

              We put a significant amount of work into the code generator infrastructure, -which allows us to implement more aggressive algorithms and make it run -faster:

              - -
                -
              • MemOperand in the code generator: describe me!.
                • -
              • The target-independent code generator infrastructure now uses LLVM's APInt - class to handle integer values, which allows it to support integer types - larger than 64 bits. Note that support for such types is also dependent on - target-specific support. Use of APInt is also a step toward support for - non-power-of-2 integer sizes.
                • -
              • Several compile time speedups for code with large basic blocks.
                • -
              • Several improvements which make llc's --view-sunit-dags - visualization of scheduling dependency graphs easier to understand.
                • -
              - -
              - - -
              Optimizer Improvements
              @@ -234,17 +223,69 @@ LOOP_BODY
              • -
            • LLVM includes a new memcpy optimization pass which optimizes out dead -memcpy calls, unneeded copies of aggregates, and handles the return slot -optimization. The LLVM optimizer now notices long sequences of consequtive -stores and merges them into memcpys where profitable.
              • + +
            • LLVM includes a new memcpy optimization pass which optimizes out +dead memcpy calls, unneeded copies of aggregates, and handles the +return slot optimization. The LLVM optimizer now notices long sequences of +consequtive stores and merges them into memcpys where profitable.
              • +
            • Alignment detection for vector memory references and for memcpy and memset is now more aggressive.
              • -
            • The aggressive dead code elimination (ADCE) optimization has been rewritten to make -it both faster and safer in the presence of code containing infinite loops. -Some of its prior functionality has been factored out into the loop deletion -pass, which is safe for infinite loops.
              • +
            • The aggressive dead code elimination (ADCE) optimization has been rewritten +to make it both faster and safer in the presence of code containing infinite +loops. Some of its prior functionality has been factored out into the loop +deletion pass, which is safe for infinite loops.
              • + +
            • Several optimizations have been sped up, leading to faster code generation + with the same code quality.
              • + +
            • The 'SimplifyLibCalls' pass, which optimizes calls to libc and libm + functions for C-based languages, has been rewritten to be a FunctionPass + instead a ModulePass. This allows it to be run more often and to be + included at -O1 in llvm-gcc. It was also extended to include more + optimizations and several corner case bugs are fixed.
              • + +
            • LLVM now includes a simple 'Jump Threading' pass, which attemps to simplify + the conditional branches with information about predecessor blocks. This + simplifies the control flow graph. This pass is pretty basic at this point, + but catches some important cases and provides a foundation to build off + of.
              • +
            + + + + +
            +Code Generator Improvements +
            + +
            + +

            We put a significant amount of work into the code generator infrastructure, +which allows us to implement more aggressive algorithms and make it run +faster:

            + +
              +
            • MemOperand in the code generator: describe me!.
              • + +
            • The target-independent code generator infrastructure now uses LLVM's APInt + class to handle integer values, which allows it to support integer types + larger than 64 bits. Note that support for such types is also dependent on + target-specific support. Use of APInt is also a step toward support for + non-power-of-2 integer sizes.
              • + +
            • Several compile time speedups for code with large basic blocks.
              • + +
            • Several improvements which make llc's --view-sunit-dags + visualization of scheduling dependency graphs easier to understand.
              • + +
            • The code generator allows targets to write patterns that generate subreg + references directly in .td files now.
              • + +
            • memcpy lowering in the backend is more aggressive, particularly for + memcpy calls introduced by the code generator when handling + pass-by-value structure argument copies.
            @@ -265,7 +306,11 @@ now interoperates very well on X86-64 systems with other compilers.
          • The LLVM X86 backend now supports the support SSE 4.1 instruction set, and - the llvm-gcc 4.2 front-end supports the SSE 4.1 compiler builtins.
            • + the llvm-gcc 4.2 front-end supports the SSE 4.1 compiler builtins. Various + generic vector operations (insert/extract/shuffle) are much more efficient + when SSE 4.1 is enabled. The JIT automatically takes advantage of these + instructions, but llvm-gcc must be explicitly told to use them, e.g. with + -march=penryn.
          • The X86 backend now does a number of optimizations that aim to avoid converting numbers back and forth from SSE registers to the X87 floating @@ -286,6 +331,8 @@
          • 128-bit integers are now supported on x86-64 targets.
            • +
          • The register allocator can now rematerialize PIC-base computations.
            • +
          @@ -320,7 +367,8 @@
          • LLVM now builds with GCC 4.3.
            • -
          • llvm2cpp tool has been folded into llc, use llc -march=cpp
            • +
          • llvm2cpp tool has been folded into llc, use + llc -march=cpp
          From evan.cheng at apple.com Sat Jun 7 22:35:31 2008 From: evan.cheng at apple.com (Evan Cheng) Date: Sun, 08 Jun 2008 03:35:31 -0000 Subject: [llvm-commits] [test-suite] r52088 - /test-suite/trunk/Makefile.programs Message-ID: <200806080335.m583ZVbf007082@zion.cs.uiuc.edu> Author: evancheng Date: Sat Jun 7 22:35:30 2008 New Revision: 52088 URL: http://llvm.org/viewvc/llvm-project?rev=52088&view=rev Log: Switch llcbeta to -enable-sinking. Modified: test-suite/trunk/Makefile.programs Modified: test-suite/trunk/Makefile.programs URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/Makefile.programs?rev=52088&r1=52087&r2=52088&view=diff ============================================================================== --- test-suite/trunk/Makefile.programs (original) +++ test-suite/trunk/Makefile.programs Sat Jun 7 22:35:30 2008 @@ -219,9 +219,8 @@ LLCBETAOPTION := -sched=simple endif ifeq ($(ARCH),x86) -LLCBETAOPTION := -stack-coloring +LLCBETAOPTION := -enable-sinking #-schedule-livein-copies -#-enable-sinking #-machine-licm #-new-coalescer-heuristic=true #-tailcallopt @@ -233,9 +232,8 @@ LLCBETAOPTION := -enable-sparc-v9-insts endif ifeq ($(ARCH),ARM) -LLCBETAOPTION := -stack-coloring +LLCBETAOPTION := -enable-sinking #-schedule-livein-copies -#-enable-sinking #-new-coalescer-heuristic=true #-march=thumb endif From asl at math.spbu.ru Sun Jun 8 05:23:57 2008 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Sun, 08 Jun 2008 10:23:57 -0000 Subject: [llvm-commits] [llvm] r52090 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <200806081023.m58ANxZ8018454@zion.cs.uiuc.edu> Author: asl Date: Sun Jun 8 05:23:46 2008 New Revision: 52090 URL: http://llvm.org/viewvc/llvm-project?rev=52090&view=rev Log: This was fixed Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=52090&r1=52089&r2=52090&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Sun Jun 8 05:23:46 2008 @@ -1,3 +1,4 @@ + @@ -186,7 +187,7 @@ Common linkage? Atomic operation support, Alpha, X86, X86-64, PowerPC. "__sync_synchronize", -"__sync_val_compare_and_swap", etc" +"__sync_val_compare_and_swap", etc
          • The C and Ocaml bindings have received additional improvements. The @@ -648,21 +649,6 @@
          - -
          - Known problems with the llvm-gcc Fortran front-end -
          - -
          - - -
          - - -
          Additional Information From asl at math.spbu.ru Sun Jun 8 05:24:14 2008 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Sun, 08 Jun 2008 10:24:14 -0000 Subject: [llvm-commits] [llvm] r52091 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <200806081024.m58AOEPj018482@zion.cs.uiuc.edu> Author: asl Date: Sun Jun 8 05:24:13 2008 New Revision: 52091 URL: http://llvm.org/viewvc/llvm-project?rev=52091&view=rev Log: Add win64 Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=52091&r1=52090&r2=52091&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Sun Jun 8 05:24:13 2008 @@ -306,17 +306,20 @@ area of passing and returning structures by value. llvm-gcc compiled code now interoperates very well on X86-64 systems with other compilers.
          • +
        • Support for Win64 was added. This includes codegeneration itself, JIT + support and necessary changes to llvm-gcc.
          • +
        • The LLVM X86 backend now supports the support SSE 4.1 instruction set, and the llvm-gcc 4.2 front-end supports the SSE 4.1 compiler builtins. Various generic vector operations (insert/extract/shuffle) are much more efficient when SSE 4.1 is enabled. The JIT automatically takes advantage of these instructions, but llvm-gcc must be explicitly told to use them, e.g. with -march=penryn.
          • - +
        • The X86 backend now does a number of optimizations that aim to avoid converting numbers back and forth from SSE registers to the X87 floating point stack.
          • - +
        • The X86 backend supports stack realignment, which is particularly useful for vector code on OS's without 16-byte aligned stacks.
          • @@ -326,7 +329,7 @@
        • Trampolines (taking the address of a nested function) now work on Linux/x86-64.
          • - +
        • __builtin_prefetch is now compiled into the appropriate prefetch instructions instead of being ignored.
          • @@ -450,11 +453,17 @@
            -
          • The X86 backend does not yet support all inline assembly that uses the X86 floating - point stack. It supports the 'f' and 't' constraints, but not 'u'.
            • -
          • The X86 backend generates inefficient floating point code when configured to +
          • The X86 backend does not yet support + all inline assembly that uses the X86 + floating point stack. It supports the 'f' and 't' constraints, but not + 'u'.
            • +
          • The X86 backend generates inefficient floating point code when configured to generate code for systems that don't have SSE2.
            • +
          • Win64 codegeneration wasn't widely tested. Everything should work, but we + expect small issues to happen. Also, llvm-gcc cannot build mingw64 runtime + currently due + to several + bugs in FP stackifier
          From asl at math.spbu.ru Sun Jun 8 11:59:10 2008 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Sun, 08 Jun 2008 16:59:10 -0000 Subject: [llvm-commits] [llvm] r52093 - /llvm/trunk/test/CodeGen/CBackend/2008-06-06-AssemblerNames.ll Message-ID: <200806081659.m58GxA3s029002@zion.cs.uiuc.edu> Author: asl Date: Sun Jun 8 11:59:10 2008 New Revision: 52093 URL: http://llvm.org/viewvc/llvm-project?rev=52093&view=rev Log: Remove invalid test Removed: llvm/trunk/test/CodeGen/CBackend/2008-06-06-AssemblerNames.ll Removed: llvm/trunk/test/CodeGen/CBackend/2008-06-06-AssemblerNames.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CBackend/2008-06-06-AssemblerNames.ll?rev=52092&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/CBackend/2008-06-06-AssemblerNames.ll (original) +++ llvm/trunk/test/CodeGen/CBackend/2008-06-06-AssemblerNames.ll (removed) @@ -1,141 +0,0 @@ -; RUN: llvm-as < %s | llc -march=c | grep llvm_cbe_asmname | count 36 -; PR2418 - -; ModuleID = 'main.bc' -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" -target triple = "i686-apple-darwin8" -module asm "\09.lazy_reference .objc_class_name_MyClass" -module asm "\09.lazy_reference .objc_class_name_Object" - %struct.MyClass = type { %struct.Object } - %struct.Object = type { %struct.objc_class* } - %struct.Protocol = type opaque - %struct._objc__method_prototype_list = type opaque - %struct._objc_class = type { %struct._objc_class*, %struct._objc_class*, i8*, i32, i32, i32, %struct._objc_ivar_list*, %struct._objc_method_list*, %struct.objc_cache*, %struct._objc_protocol**, i8*, %struct._objc_class_ext* } - %struct._objc_class_ext = type opaque - %struct._objc_ivar_list = type opaque - %struct._objc_method = type { %struct.objc_selector*, i8*, i8* } - %struct._objc_method_list = type opaque - %struct._objc_module = type { i32, i32, i8*, %struct._objc_symtab* } - %struct._objc_protocol = type { %struct._objc_protocol_extension*, i8*, %struct._objc_protocol**, %struct._objc__method_prototype_list*, %struct._objc__method_prototype_list* } - %struct._objc_protocol_extension = type opaque - %struct._objc_symtab = type { i32, %struct.objc_selector**, i16, i16, [1 x i8*] } - %struct.anon = type { %struct._objc__method_prototype_list*, i32, [1 x %struct._objc_method] } - %struct.objc_cache = type { i32, i32, [1 x %struct.objc_method*] } - %struct.objc_class = type { %struct.objc_class*, %struct.objc_class*, i8*, i32, i32, i32, %struct.objc_ivar_list*, %struct.objc_method_list**, %struct.objc_cache*, %struct.objc_protocol_list* } - %struct.objc_ivar = type { i8*, i8*, i32 } - %struct.objc_ivar_list = type { i32, [1 x %struct.objc_ivar] } - %struct.objc_method = type { %struct.objc_selector*, i8*, %struct.Object* (%struct.Object*, %struct.objc_selector*, ...)* } - %struct.objc_method_list = type { %struct.objc_method_list*, i32, [1 x %struct.objc_method] } - %struct.objc_object = type { %struct.objc_class* } - %struct.objc_protocol_list = type { %struct.objc_protocol_list*, i32, [1 x %struct.Protocol*] } - %struct.objc_selector = type opaque - at .str = internal constant [13 x i8] c"Hello world!\00" ; <[13 x i8]*> [#uses=1] -@"\01L_OBJC_CLASS_REFERENCES_0" = internal global %struct.objc_class* bitcast ([8 x i8]* @"\01L_OBJC_CLASS_NAME_0" to %struct.objc_class*), section "__OBJC,__cls_refs,literal_pointers,no_dead_strip" ; <%struct.objc_class**> [#uses=2] -@"\01L_OBJC_SELECTOR_REFERENCES_0" = internal global %struct.objc_selector* bitcast ([6 x i8]* @"\01L_OBJC_METH_VAR_NAME_1" to %struct.objc_selector*), section "__OBJC,__message_refs,literal_pointers,no_dead_strip" ; <%struct.objc_selector**> [#uses=2] -@"\01L_OBJC_SELECTOR_REFERENCES_1" = internal global %struct.objc_selector* bitcast ([9 x i8]* @"\01L_OBJC_METH_VAR_NAME_0" to %struct.objc_selector*), section "__OBJC,__message_refs,literal_pointers,no_dead_strip" ; <%struct.objc_selector**> [#uses=2] -@"\01L_OBJC_CLASS_MyClass" = internal global %struct._objc_class { - %struct._objc_class* @"\01L_OBJC_METACLASS_MyClass", - %struct._objc_class* bitcast ([7 x i8]* @"\01L_OBJC_CLASS_NAME_1" to %struct._objc_class*), - i8* getelementptr ([8 x i8]* @"\01L_OBJC_CLASS_NAME_0", i32 0, i32 0), - i32 0, - i32 1, - i32 4, - %struct._objc_ivar_list* null, - %struct._objc_method_list* bitcast ({ i32, i32, [1 x %struct._objc_method] }* @"\01L_OBJC_INSTANCE_METHODS_MyClass" to %struct._objc_method_list*), - %struct.objc_cache* null, - %struct._objc_protocol** null, - i8* null, - %struct._objc_class_ext* null }, section "__OBJC,__class,regular,no_dead_strip", align 32 ; <%struct._objc_class*> [#uses=2] -@"\01L_OBJC_SYMBOLS" = internal global { i32, %struct.objc_selector**, i16, i16, [1 x %struct._objc_class*] } { - i32 0, - %struct.objc_selector** null, - i16 1, - i16 0, - [1 x %struct._objc_class*] [ %struct._objc_class* @"\01L_OBJC_CLASS_MyClass" ] }, section "__OBJC,__symbols,regular,no_dead_strip" ; <{ i32, %struct.objc_selector**, i16, i16, [1 x %struct._objc_class*] }*> [#uses=2] - at L_OBJC_METH_VAR_NAME_0 = internal global [9 x i8] c"sayHello\00", section "__TEXT,__cstring,cstring_literals" ; <[9 x i8]*> [#uses=0] - at L_OBJC_METH_VAR_TYPE_0 = internal global [7 x i8] c"v8 at 0:4\00", section "__TEXT,__cstring,cstring_literals" ; <[7 x i8]*> [#uses=0] -@"\01L_OBJC_METH_VAR_NAME_0" = internal global [9 x i8] c"sayHello\00", section "__TEXT,__cstring,cstring_literals" ; <[9 x i8]*> [#uses=2] -@"\01L_OBJC_METH_VAR_TYPE_0" = internal global [7 x i8] c"v8 at 0:4\00", section "__TEXT,__cstring,cstring_literals" ; <[7 x i8]*> [#uses=1] -@"\01L_OBJC_INSTANCE_METHODS_MyClass" = internal global { i32, i32, [1 x %struct._objc_method] } { - i32 0, - i32 1, - [1 x %struct._objc_method] [ %struct._objc_method { - %struct.objc_selector* bitcast ([9 x i8]* @"\01L_OBJC_METH_VAR_NAME_0" to %struct.objc_selector*), - i8* getelementptr ([7 x i8]* @"\01L_OBJC_METH_VAR_TYPE_0", i32 0, i32 0), - i8* bitcast (void (%struct.MyClass*, %struct.objc_selector*)* @"-[MyClass sayHello]" to i8*) } ] }, section "__OBJC,__inst_meth,regular,no_dead_strip" ; <{ i32, i32, [1 x %struct._objc_method] }*> [#uses=2] - at L_OBJC_CLASS_NAME_0 = internal global [8 x i8] c"MyClass\00", section "__TEXT,__cstring,cstring_literals" ; <[8 x i8]*> [#uses=0] - at L_OBJC_CLASS_NAME_1 = internal global [7 x i8] c"Object\00", section "__TEXT,__cstring,cstring_literals" ; <[7 x i8]*> [#uses=0] -@"\01L_OBJC_METACLASS_MyClass" = internal global %struct._objc_class { - %struct._objc_class* bitcast ([7 x i8]* @"\01L_OBJC_CLASS_NAME_1" to %struct._objc_class*), - %struct._objc_class* bitcast ([7 x i8]* @"\01L_OBJC_CLASS_NAME_1" to %struct._objc_class*), - i8* getelementptr ([8 x i8]* @"\01L_OBJC_CLASS_NAME_0", i32 0, i32 0), - i32 0, - i32 2, - i32 48, - %struct._objc_ivar_list* null, - %struct._objc_method_list* null, - %struct.objc_cache* null, - %struct._objc_protocol** null, - i8* null, - %struct._objc_class_ext* null }, section "__OBJC,__meta_class,regular,no_dead_strip", align 32 ; <%struct._objc_class*> [#uses=2] -@"\01L_OBJC_CLASS_NAME_1" = internal global [7 x i8] c"Object\00", section "__TEXT,__cstring,cstring_literals" ; <[7 x i8]*> [#uses=2] -@"\01L_OBJC_CLASS_NAME_0" = internal global [8 x i8] c"MyClass\00", section "__TEXT,__cstring,cstring_literals" ; <[8 x i8]*> [#uses=2] - at L_OBJC_METH_VAR_NAME_1 = internal global [6 x i8] c"alloc\00", section "__TEXT,__cstring,cstring_literals" ; <[6 x i8]*> [#uses=0] -@"\01L_OBJC_METH_VAR_NAME_1" = internal global [6 x i8] c"alloc\00", section "__TEXT,__cstring,cstring_literals" ; <[6 x i8]*> [#uses=2] -@"\01L_OBJC_IMAGE_INFO" = internal constant [2 x i32] zeroinitializer, section "__OBJC,__image_info,regular" ; <[2 x i32]*> [#uses=1] - at L_OBJC_CLASS_NAME_2 = internal global [1 x i8] zeroinitializer, section "__TEXT,__cstring,cstring_literals" ; <[1 x i8]*> [#uses=0] -@"\01L_OBJC_MODULES" = internal global %struct._objc_module { - i32 7, - i32 16, - i8* getelementptr ([1 x i8]* @"\01L_OBJC_CLASS_NAME_2", i32 0, i32 0), - %struct._objc_symtab* bitcast ({ i32, %struct.objc_selector**, i16, i16, [1 x %struct._objc_class*] }* @"\01L_OBJC_SYMBOLS" to %struct._objc_symtab*) }, section "__OBJC,__module_info,regular,no_dead_strip" ; <%struct._objc_module*> [#uses=1] -@"\01L_OBJC_CLASS_NAME_2" = internal global [1 x i8] zeroinitializer, section "__TEXT,__cstring,cstring_literals" ; <[1 x i8]*> [#uses=1] -@"\01.objc_class_name_MyClass" = constant i32 0 ; [#uses=1] - at llvm.used = appending global [16 x i8*] [ i8* bitcast (%struct.objc_class** @"\01L_OBJC_CLASS_REFERENCES_0" to i8*), i8* bitcast (%struct.objc_selector** @"\01L_OBJC_SELECTOR_REFERENCES_0" to i8*), i8* bitcast (%struct.objc_selector** @"\01L_OBJC_SELECTOR_REFERENCES_1" to i8*), i8* bitcast (%struct._objc_class* @"\01L_OBJC_CLASS_MyClass" to i8*), i8* bitcast ({ i32, %struct.objc_selector**, i16, i16, [1 x %struct._objc_class*] }* @"\01L_OBJC_SYMBOLS" to i8*), i8* getelementptr ([9 x i8]* @"\01L_OBJC_METH_VAR_NAME_0", i32 0, i32 0), i8* getelementptr ([7 x i8]* @"\01L_OBJC_METH_VAR_TYPE_0", i32 0, i32 0), i8* bitcast ({ i32, i32, [1 x %struct._objc_method] }* @"\01L_OBJC_INSTANCE_METHODS_MyClass" to i8*), i8* getelementptr ([7 x i8]* @"\01L_OBJC_CLASS_NAME_1", i32 0, i32 0), i8* getelementptr ([8 x i8]* @"\01L_OBJC_CLASS_NAME_0", i32 0, i32 0), i8* bitcast (%struct._objc_class* @"\01L_OBJC_METACLASS_MyClass" to i8*), i8* getelementptr ([6 x i8]* @"\01L_OBJC_METH_VAR_NAME_1"! , i32 0, i32 0), i8* bitcast ([2 x i32]* @"\01L_OBJC_IMAGE_INFO" to i8*), i8* getelementptr ([1 x i8]* @"\01L_OBJC_CLASS_NAME_2", i32 0, i32 0), i8* bitcast (%struct._objc_module* @"\01L_OBJC_MODULES" to i8*), i8* bitcast (i32* @"\01.objc_class_name_MyClass" to i8*) ], section "llvm.metadata" ; <[16 x i8*]*> [#uses=0] - -define internal void @"-[MyClass sayHello]"(%struct.MyClass* %self, %struct.objc_selector* %_cmd) { -entry: - %self_addr = alloca %struct.MyClass* ; <%struct.MyClass**> [#uses=1] - %_cmd_addr = alloca %struct.objc_selector* ; <%struct.objc_selector**> [#uses=1] - %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] - store %struct.MyClass* %self, %struct.MyClass** %self_addr - store %struct.objc_selector* %_cmd, %struct.objc_selector** %_cmd_addr - %tmp = getelementptr [13 x i8]* @.str, i32 0, i32 0 ; [#uses=1] - %tmp1 = call i32 @puts( i8* %tmp ) nounwind ; [#uses=0] - br label %return - -return: ; preds = %entry - ret void -} - -declare i32 @puts(i8*) - -define i32 @main() { -entry: - %retval = alloca i32 ; [#uses=1] - %anObject = alloca %struct.MyClass* ; <%struct.MyClass**> [#uses=2] - %anObject.4 = alloca %struct.Object* ; <%struct.Object**> [#uses=2] - %L_OBJC_CLASS_REFERENCES_0.2 = alloca %struct.Object* ; <%struct.Object**> [#uses=2] - %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] - %tmp = load %struct.objc_class** @"\01L_OBJC_CLASS_REFERENCES_0", align 4 ; <%struct.objc_class*> [#uses=1] - %tmp1 = bitcast %struct.objc_class* %tmp to %struct.Object* ; <%struct.Object*> [#uses=1] - store %struct.Object* %tmp1, %struct.Object** %L_OBJC_CLASS_REFERENCES_0.2, align 4 - %tmp2 = load %struct.objc_selector** @"\01L_OBJC_SELECTOR_REFERENCES_0", align 4 ; <%struct.objc_selector*> [#uses=1] - %tmp3 = load %struct.Object** %L_OBJC_CLASS_REFERENCES_0.2, align 4 ; <%struct.Object*> [#uses=1] - %tmp4 = call %struct.Object* bitcast (%struct.Object* (%struct.Object*, %struct.objc_selector*, ...)* @objc_msgSend to %struct.Object* (%struct.Object*, %struct.objc_selector*)*)( %struct.Object* %tmp3, %struct.objc_selector* %tmp2 ) nounwind ; <%struct.Object*> [#uses=1] - %tmp45 = bitcast %struct.Object* %tmp4 to %struct.MyClass* ; <%struct.MyClass*> [#uses=1] - store %struct.MyClass* %tmp45, %struct.MyClass** %anObject, align 4 - %tmp6 = load %struct.MyClass** %anObject, align 4 ; <%struct.MyClass*> [#uses=1] - %tmp67 = bitcast %struct.MyClass* %tmp6 to %struct.Object* ; <%struct.Object*> [#uses=1] - store %struct.Object* %tmp67, %struct.Object** %anObject.4, align 4 - %tmp8 = load %struct.objc_selector** @"\01L_OBJC_SELECTOR_REFERENCES_1", align 4 ; <%struct.objc_selector*> [#uses=1] - %tmp9 = load %struct.Object** %anObject.4, align 4 ; <%struct.Object*> [#uses=1] - call void bitcast (%struct.Object* (%struct.Object*, %struct.objc_selector*, ...)* @objc_msgSend to void (%struct.Object*, %struct.objc_selector*)*)( %struct.Object* %tmp9, %struct.objc_selector* %tmp8 ) nounwind - br label %return - -return: ; preds = %entry - %retval10 = load i32* %retval ; [#uses=1] - ret i32 %retval10 -} - -declare %struct.Object* @objc_msgSend(%struct.Object*, %struct.objc_selector*, ...) From baldrick at free.fr Sun Jun 8 14:38:44 2008 From: baldrick at free.fr (Duncan Sands) Date: Sun, 08 Jun 2008 19:38:44 -0000 Subject: [llvm-commits] [llvm] r52094 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <200806081938.m58JcivJ001980@zion.cs.uiuc.edu> Author: baldrick Date: Sun Jun 8 14:38:43 2008 New Revision: 52094 URL: http://llvm.org/viewvc/llvm-project?rev=52094&view=rev Log: Fix spelling. Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=52094&r1=52093&r2=52094&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Sun Jun 8 14:38:43 2008 @@ -128,7 +128,7 @@
        • Flexible (and extensible) rules for defining different tools.
        • The different intermediate steps performed by tools are represented as edges in the abstract graph.
          • -
        • The 'language' for driver behaviour definition is tablegen and thus +
        • The 'language' for driver behavior definition is tablegen and thus it's relatively easy to add new features.
        • The definition of driver is transformed into set of C++ classes, thus no runtime interpretation is needed.
          • @@ -228,7 +228,7 @@
        • LLVM includes a new memcpy optimization pass which optimizes out dead memcpy calls, unneeded copies of aggregates, and handles the return slot optimization. The LLVM optimizer now notices long sequences of -consequtive stores and merges them into memcpys where profitable.
          • +consecutive stores and merges them into memcpys where profitable.
        • Alignment detection for vector memory references and for memcpy and memset is now more aggressive.
          • @@ -247,7 +247,7 @@ included at -O1 in llvm-gcc. It was also extended to include more optimizations and several corner case bugs are fixed. -
        • LLVM now includes a simple 'Jump Threading' pass, which attemps to simplify +
        • LLVM now includes a simple 'Jump Threading' pass, which attempts to simplify the conditional branches with information about predecessor blocks. This simplifies the control flow graph. This pass is pretty basic at this point, but catches some important cases and provides a foundation to build off @@ -306,7 +306,7 @@ area of passing and returning structures by value. llvm-gcc compiled code now interoperates very well on X86-64 systems with other compilers.
          • -
        • Support for Win64 was added. This includes codegeneration itself, JIT +
        • Support for Win64 was added. This includes code generation itself, JIT support and necessary changes to llvm-gcc.
        • The LLVM X86 backend now supports the support SSE 4.1 instruction set, and @@ -459,7 +459,7 @@ 'u'.
        • The X86 backend generates inefficient floating point code when configured to generate code for systems that don't have SSE2.
          • -
        • Win64 codegeneration wasn't widely tested. Everything should work, but we +
        • Win64 code generation wasn't widely tested. Everything should work, but we expect small issues to happen. Also, llvm-gcc cannot build mingw64 runtime currently due to several @@ -554,7 +554,7 @@ output with code built with other compilers, particularly for floating-point programs.
          • -
        • Defining vararg functions is not supported (but calling them is ok).
          • +
        • Defining vararg functions is not supported (but calling them is OK).
        • The Itanium backend has bitrotted somewhat.
        From baldrick at free.fr Sun Jun 8 15:18:35 2008 From: baldrick at free.fr (Duncan Sands) Date: Sun, 08 Jun 2008 20:18:35 -0000 Subject: [llvm-commits] [llvm] r52095 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <200806082018.m58KIZFH003428@zion.cs.uiuc.edu> Author: baldrick Date: Sun Jun 8 15:18:35 2008 New Revision: 52095 URL: http://llvm.org/viewvc/llvm-project?rev=52095&view=rev Log: Using llc always rather than sometimes using LLC. Try to improve language in various places. Use X86 always rather than sometimes using x86. Add some minor Ada info. Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=52095&r1=52094&r2=52095&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Sun Jun 8 15:18:35 2008 @@ -96,7 +96,7 @@ IRBuilder.
      • MRegisterInfo was renamed to TargetRegisterInfo.
      • The MappedFile class is gone, please use MemoryBuffer instead.
        • -
      • The '-enable-eh' flag to LLC has been removed. Now code should encode +
      • The '-enable-eh' flag to llc has been removed. Now code should encode whether it is safe to not generate unwind information for a function by tagging the Function object with the 'nounwind' attribute.
        • @@ -113,12 +113,12 @@

        LLVM 2.3 includes several major new capabilities:

          -
        • Multiple Return Value Support
          • +
        • Multiple Return Value Support.

        • LLVM 2.3 includes a complete reimplementation of the "llvmc" tool. It is -designed to overcome several problems of the original llvmc and to provide a -superset of the features as the 'gcc' driver.

          +designed to overcome several problems with the original llvmc and to provide a +superset of the features of the 'gcc' driver.

          The main features of llvmc2 is:

          @@ -140,7 +140,7 @@ C.
          • -
        • kaleidoscope tutorial in ocaml.
          • +
        • Kaleidoscope tutorial in Ocaml.
        @@ -154,7 +154,7 @@
        -

        LLVM 2.3 fully supports llvm-gcc 4.2 front-end.

        +

        LLVM 2.3 fully supports the llvm-gcc 4.2 front-end.

        llvm-gcc 4.2 includes numerous fixes to better support the Objective-C front-end. Objective-C now works very well on Mac OS/X.

        @@ -225,10 +225,10 @@ -
      • LLVM includes a new memcpy optimization pass which optimizes out -dead memcpy calls, unneeded copies of aggregates, and handles the +
      • LLVM includes a new memcpy optimization pass removes +dead memcpy calls, unneeded copies of aggregates, and performs return slot optimization. The LLVM optimizer now notices long sequences of -consecutive stores and merges them into memcpys where profitable.
        • +consecutive stores and merges them into memcpy's where profitable.
      • Alignment detection for vector memory references and for memcpy and memset is now more aggressive.
        • @@ -245,13 +245,12 @@ functions for C-based languages, has been rewritten to be a FunctionPass instead a ModulePass. This allows it to be run more often and to be included at -O1 in llvm-gcc. It was also extended to include more - optimizations and several corner case bugs are fixed. + optimizations and several corner case bugs were fixed.
      • LLVM now includes a simple 'Jump Threading' pass, which attempts to simplify - the conditional branches with information about predecessor blocks. This - simplifies the control flow graph. This pass is pretty basic at this point, - but catches some important cases and provides a foundation to build off - of.
        • + conditional branches using information about predecessor blocks, simplifying + the control flow graph. This pass is pretty basic at this point, but catches + some important cases and provides a foundation to build on.
      @@ -328,12 +327,12 @@ registers.
    • Trampolines (taking the address of a nested function) now work on - Linux/x86-64.
      • + Linux/X86-64.
    • __builtin_prefetch is now compiled into the appropriate prefetch instructions instead of being ignored.
      • -
    • 128-bit integers are now supported on x86-64 targets.
      • +
    • 128-bit integers are now supported on X86-64 targets.
    • The register allocator can now rematerialize PIC-base computations.
      • @@ -439,7 +438,7 @@
      • The MSIL, IA64, Alpha, SPU, and MIPS backends are experimental.
        • -
      • The LLC "-filetype=asm" (the default) is the only supported +
      • The llc "-filetype=asm" (the default) is the only supported value for this option.
      @@ -573,7 +572,7 @@ inline assembly code.
    • The C backend violates the ABI of common C++ programs, preventing intermixing between C++ compiled by the CBE and - C++ code compiled with LLC or native compilers.
      • + C++ code compiled with llc or native compilers.
    • The C backend does not support all exception handling constructs.
    @@ -597,8 +596,8 @@

    The only major language feature of GCC not supported by llvm-gcc is the __builtin_apply family of builtins. However, some extensions are only supported on some targets. For example, trampolines are only - supported on some targets, which are used when you take the address of a - nested function.

    + supported on some targets (these are used when you take the address of a + nested function).

    If you run into GCC extensions which are not supported, please let us know.

    @@ -618,8 +617,8 @@
    • Exception handling works well on the X86 and PowerPC targets, including -x86-64 darwin. This works when linking to a libstdc++ compiled by GCC. It is -supported on x86-64 linux, but that is disabled by default in this release.
      • +X86-64 darwin. This works when linking to a libstdc++ compiled by GCC. It is +supported on X86-64 linux, but that is disabled by default in this release.
    @@ -634,15 +633,17 @@ The llvm-gcc 4.2 Ada compiler works fairly well, however this is not a mature technology and problems should be expected.
      -
    • The Ada front-end currently only builds on x86-32. This is mainly due +
    • The Ada front-end currently only builds on X86-32. This is mainly due to lack of trampoline support (pointers to nested functions) on other platforms, -however it also fails to build on x86-64 +however it also fails to build on X86-64 which does support trampolines.
    • The Ada front-end fails to bootstrap. Workaround: configure with --disable-bootstrap.
    • The c380004 and c393010 ACATS tests -fail (c380004 also fails with gcc-4.2 mainline).
      • -
    • Many gcc specific Ada tests continue to crash the compiler.
      • +fail (c380004 also fails with gcc-4.2 mainline). When built at -O3, the +cxg2021 ACATS test also fails. +
    • Some gcc specific Ada tests continue to crash the compiler. The testsuite +reports most tests as having failed even though they pass.
    • The -E binder option (exception backtraces) does not work and will result in programs crashing if an exception is raised. Workaround: do not use -E.
      • From sabre at nondot.org Sun Jun 8 15:25:30 2008 From: sabre at nondot.org (Chris Lattner) Date: Sun, 08 Jun 2008 20:25:30 -0000 Subject: [llvm-commits] [llvm] r52096 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <200806082025.m58KPU4T003734@zion.cs.uiuc.edu> Author: lattner Date: Sun Jun 8 15:25:30 2008 New Revision: 52096 URL: http://llvm.org/viewvc/llvm-project?rev=52096&view=rev Log: add some html escapes Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=52096&r1=52095&r2=52096&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Sun Jun 8 15:25:30 2008 @@ -213,14 +213,14 @@ This transformation hoists conditions from loop bodies and reduces loop's iteration space to improve performance. For example, 

      -for (i = LB; i < UB; ++i)
-  if (i <= NV)
+for (i = LB; i < UB; ++i)
+  if (i <= NV)
     LOOP_BODY
      is transformed into 
       NUB = min(NV+1, UB)
-for (i = LB; i < NUB; ++i)
+for (i = LB; i < NUB; ++i)
   LOOP_BODY
      From sabre at nondot.org Sun Jun 8 15:52:11 2008 From: sabre at nondot.org (Chris Lattner) Date: Sun, 08 Jun 2008 20:52:11 -0000 Subject: [llvm-commits] [llvm] r52097 - in /llvm/trunk: lib/Transforms/Scalar/InstructionCombining.cpp test/Transforms/InstCombine/2008-06-08-ICmpPHI.ll Message-ID: <200806082052.m58KqBpW004457@zion.cs.uiuc.edu> Author: lattner Date: Sun Jun 8 15:52:11 2008 New Revision: 52097 URL: http://llvm.org/viewvc/llvm-project?rev=52097&view=rev Log: Limit the icmp+phi merging optimization to the cases where it is profitable: don't make i1 phis when it won't be possible to eliminate them. Added: llvm/trunk/test/Transforms/InstCombine/2008-06-08-ICmpPHI.ll Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp?rev=52097&r1=52096&r2=52097&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Sun Jun 8 15:52:11 2008 @@ -5043,8 +5043,12 @@ if (Instruction *LHSI = dyn_cast(Op0)) switch (LHSI->getOpcode()) { case Instruction::PHI: - if (Instruction *NV = FoldOpIntoPhi(I)) - return NV; + // Only fold fcmp into the PHI if the phi and fcmp are in the same + // block. If in the same block, we're encouraging jump threading. If + // not, we are just pessimizing the code by making an i1 phi. + if (LHSI->getParent() == I.getParent()) + if (Instruction *NV = FoldOpIntoPhi(I)) + return NV; break; case Instruction::SIToFP: case Instruction::UIToFP: @@ -5348,8 +5352,12 @@ break; case Instruction::PHI: - if (Instruction *NV = FoldOpIntoPhi(I)) - return NV; + // Only fold icmp into the PHI if the phi and fcmp are in the same + // block. If in the same block, we're encouraging jump threading. If + // not, we are just pessimizing the code by making an i1 phi. + if (LHSI->getParent() == I.getParent()) + if (Instruction *NV = FoldOpIntoPhi(I)) + return NV; break; case Instruction::Select: { // If either operand of the select is a constant, we can fold the Added: llvm/trunk/test/Transforms/InstCombine/2008-06-08-ICmpPHI.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/2008-06-08-ICmpPHI.ll?rev=52097&view=auto ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/2008-06-08-ICmpPHI.ll (added) +++ llvm/trunk/test/Transforms/InstCombine/2008-06-08-ICmpPHI.ll Sun Jun 8 15:52:11 2008 @@ -0,0 +1,49 @@ +; RUN: llvm-as < %s | opt -instcombine | llvm-dis | grep {phi i32} | count 2 +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" +target triple = "i386-apple-darwin8" + +define void @test() nounwind { +entry: + br label %bb + +bb: ; preds = %bb16, %entry + %i.0 = phi i32 [ 0, %entry ], [ %indvar.next, %somebb ] ; [#uses=1] + %x.0 = phi i32 [ 37, %entry ], [ %tmp17, %somebb ] ; [#uses=1] + %tmp = tail call i32 (...)* @bork( ) nounwind ; [#uses=0] + %tmp1 = tail call i32 (...)* @bork( ) nounwind ; [#uses=0] + %tmp2 = tail call i32 (...)* @bork( ) nounwind ; [#uses=1] + %tmp3 = icmp eq i32 %tmp2, 0 ; [#uses=1] + br i1 %tmp3, label %bb7, label %bb5 + +bb5: ; preds = %bb + %tmp6 = tail call i32 (...)* @bork( ) nounwind ; [#uses=0] + br label %bb7 + +bb7: ; preds = %bb5, %bb + %tmp8 = tail call i32 (...)* @bork( ) nounwind ; [#uses=0] + %tmp9 = tail call i32 (...)* @bork( ) nounwind ; [#uses=0] + %tmp11 = icmp eq i32 %x.0, 37 ; [#uses=1] + br i1 %tmp11, label %bb14, label %bb16 + +bb14: ; preds = %bb7 + %tmp15 = tail call i32 (...)* @bar( ) nounwind ; [#uses=0] + br label %bb16 + +bb16: ; preds = %bb14, %bb7 + %tmp17 = tail call i32 (...)* @zap( ) nounwind ; [#uses=1] + %indvar.next = add i32 %i.0, 1 ; [#uses=2] + %exitcond = icmp eq i32 %indvar.next, 42 ; [#uses=1] + br i1 %exitcond, label %return, label %somebb + +somebb: + br label %bb + +return: ; preds = %bb16 + ret void +} + +declare i32 @bork(...) + +declare i32 @bar(...) + +declare i32 @zap(...) From baldrick at free.fr Sun Jun 8 15:54:56 2008 From: baldrick at free.fr (Duncan Sands) Date: Sun, 08 Jun 2008 20:54:56 -0000 Subject: [llvm-commits] [llvm] r52098 - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/SelectionDAG/ lib/Target/Alpha/ lib/Target/CellSPU/ lib/Target/PowerPC/ lib/Target/X86/ lib/Transforms/Scalar/ Message-ID: <200806082054.m58KsvVv004570@zion.cs.uiuc.edu> Author: baldrick Date: Sun Jun 8 15:54:56 2008 New Revision: 52098 URL: http://llvm.org/viewvc/llvm-project?rev=52098&view=rev Log: Remove comparison methods for MVT. The main cause of apint codegen failure is the DAG combiner doing the wrong thing because it was comparing MVT's using < rather than comparing the number of bits. Removing the < method makes this mistake impossible to commit. Instead, add helper methods for comparing bits and use them. Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h llvm/trunk/include/llvm/CodeGen/ValueTypes.h llvm/trunk/include/llvm/Target/TargetLowering.h llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesFloatToInt.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesScalarize.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesSplit.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=52098&r1=52097&r2=52098&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Sun Jun 8 15:54:56 2008 @@ -610,7 +610,7 @@ std::vector CondCodeNodes; std::vector ValueTypeNodes; - std::map ExtendedValueTypeNodes; + std::map ExtendedValueTypeNodes; std::map ExternalSymbols; std::map TargetExternalSymbols; std::map StringNodes; Modified: llvm/trunk/include/llvm/CodeGen/ValueTypes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ValueTypes.h?rev=52098&r1=52097&r2=52098&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/ValueTypes.h (original) +++ llvm/trunk/include/llvm/CodeGen/ValueTypes.h Sun Jun 8 15:54:56 2008 @@ -132,16 +132,10 @@ MVT() {} MVT(SimpleValueType S) { V = S; } + inline bool operator== (const MVT VT) const { return V == VT.V; } inline bool operator!= (const MVT VT) const { return V != VT.V; } - /// FIXME: The following comparison methods are bogus - they are only here - /// to ease the transition to a struct type. - inline bool operator< (const MVT VT) const { return V < VT.V; } - inline bool operator<= (const MVT VT) const { return V <= VT.V; } - inline bool operator> (const MVT VT) const { return V > VT.V; } - inline bool operator>= (const MVT VT) const { return V >= VT.V; } - /// getIntegerVT - Returns the MVT that represents an integer with the given /// number of bits. static inline MVT getIntegerVT(unsigned BitWidth) { @@ -268,6 +262,27 @@ } + /// bitsGT - Return true if this has more bits than VT. + inline bool bitsGT(MVT VT) const { + return getSizeInBits() > VT.getSizeInBits(); + } + + /// bitsGE - Return true if this has no less bits than VT. + inline bool bitsGE(MVT VT) const { + return getSizeInBits() >= VT.getSizeInBits(); + } + + /// bitsLT - Return true if this has less bits than VT. + inline bool bitsLT(MVT VT) const { + return getSizeInBits() < VT.getSizeInBits(); + } + + /// bitsLE - Return true if this has no more bits than VT. + inline bool bitsLE(MVT VT) const { + return getSizeInBits() <= VT.getSizeInBits(); + } + + /// getSimpleVT - Return the SimpleValueType held in the specified /// simple MVT. inline SimpleValueType getSimpleVT() const { @@ -413,6 +428,14 @@ /// getRawBits - Represent the type as a bunch of bits. uint32_t getRawBits() const { return V; } + + /// compareRawBits - A meaningless but well-behaved order, useful for + /// constructing containers. + struct compareRawBits { + bool operator()(MVT L, MVT R) const { + return L.getRawBits() < R.getRawBits(); + } + }; }; } // End llvm namespace Modified: llvm/trunk/include/llvm/Target/TargetLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=52098&r1=52097&r2=52098&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetLowering.h (original) +++ llvm/trunk/include/llvm/Target/TargetLowering.h Sun Jun 8 15:54:56 2008 @@ -406,9 +406,9 @@ "This operation isn't promoted!"); // See if this has an explicit type specified. - std::map, - MVT>::const_iterator PTTI = - PromoteToType.find(std::make_pair(Op, VT)); + std::map, + MVT::SimpleValueType>::const_iterator PTTI = + PromoteToType.find(std::make_pair(Op, VT.getSimpleVT())); if (PTTI != PromoteToType.end()) return PTTI->second; assert((VT.isInteger() || VT.isFloatingPoint()) && @@ -898,7 +898,8 @@ /// one that works. If that default is insufficient, this method can be used /// by the target to override the default. void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { - PromoteToType[std::make_pair(Opc, OrigVT)] = DestVT; + PromoteToType[std::make_pair(Opc, OrigVT.getSimpleVT())] = + DestVT.getSimpleVT(); } /// addLegalFPImmediate - Indicate that this target can instruction select @@ -1427,7 +1428,8 @@ /// /// Targets add entries to this map with AddPromotedToType(..), clients access /// this with getTypeToPromoteTo(..). - std::map, MVT> PromoteToType; + std::map, MVT::SimpleValueType> + PromoteToType; /// LibcallRoutineNames - Stores the name each libcall. /// Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=52098&r1=52097&r2=52098&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sun Jun 8 15:54:56 2008 @@ -1786,7 +1786,7 @@ EVT = MVT::Other; LoadedVT = LN0->getMemoryVT(); - if (EVT != MVT::Other && LoadedVT > EVT && + if (EVT != MVT::Other && LoadedVT.bitsGT(EVT) && (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { MVT PtrType = N0.getOperand(1).getValueType(); // For big endian targets, we need to add an offset to the pointer to @@ -2393,7 +2393,7 @@ case 16: EVT = MVT::i16; break; case 32: EVT = MVT::i32; break; } - if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)) + if (EVT != MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)) return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), DAG.getValueType(EVT)); } @@ -2609,7 +2609,7 @@ if (VT == VT0) return XORNode; AddToWorkList(XORNode.Val); - if (VT.getSizeInBits() > VT0.getSizeInBits()) + if (VT.bitsGT(VT0)) return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode); return DAG.getNode(ISD::TRUNCATE, VT, XORNode); } @@ -2816,9 +2816,9 @@ // fold (sext (truncate x)) -> (sextinreg x). if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, N0.getValueType())) { - if (Op.getValueType() < VT) + if (Op.getValueType().bitsLT(VT)) Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); - else if (Op.getValueType() > VT) + else if (Op.getValueType().bitsGT(VT)) Op = DAG.getNode(ISD::TRUNCATE, VT, Op); return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op, DAG.getValueType(N0.getValueType())); @@ -2925,9 +2925,9 @@ if (N0.getOpcode() == ISD::TRUNCATE && (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) { SDOperand Op = N0.getOperand(0); - if (Op.getValueType() < VT) { + if (Op.getValueType().bitsLT(VT)) { Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); - } else if (Op.getValueType() > VT) { + } else if (Op.getValueType().bitsGT(VT)) { Op = DAG.getNode(ISD::TRUNCATE, VT, Op); } return DAG.getZeroExtendInReg(Op, N0.getValueType()); @@ -2938,9 +2938,9 @@ N0.getOperand(0).getOpcode() == ISD::TRUNCATE && N0.getOperand(1).getOpcode() == ISD::Constant) { SDOperand X = N0.getOperand(0).getOperand(0); - if (X.getValueType() < VT) { + if (X.getValueType().bitsLT(VT)) { X = DAG.getNode(ISD::ANY_EXTEND, VT, X); - } else if (X.getValueType() > VT) { + } else if (X.getValueType().bitsGT(VT)) { X = DAG.getNode(ISD::TRUNCATE, VT, X); } APInt Mask = cast(N0.getOperand(1))->getAPIntValue(); @@ -3045,7 +3045,7 @@ SDOperand TruncOp = N0.getOperand(0); if (TruncOp.getValueType() == VT) return TruncOp; // x iff x size == zext size. - if (TruncOp.getValueType() > VT) + if (TruncOp.getValueType().bitsGT(VT)) return DAG.getNode(ISD::TRUNCATE, VT, TruncOp); return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp); } @@ -3055,9 +3055,9 @@ N0.getOperand(0).getOpcode() == ISD::TRUNCATE && N0.getOperand(1).getOpcode() == ISD::Constant) { SDOperand X = N0.getOperand(0).getOperand(0); - if (X.getValueType() < VT) { + if (X.getValueType().bitsLT(VT)) { X = DAG.getNode(ISD::ANY_EXTEND, VT, X); - } else if (X.getValueType() > VT) { + } else if (X.getValueType().bitsGT(VT)) { X = DAG.getNode(ISD::TRUNCATE, VT, X); } APInt Mask = cast(N0.getOperand(1))->getAPIntValue(); @@ -3251,7 +3251,7 @@ // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && - EVT < cast(N0.getOperand(1))->getVT()) { + EVT.bitsLT(cast(N0.getOperand(1))->getVT())) { return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); } @@ -3333,10 +3333,10 @@ // fold (truncate (ext x)) -> (ext x) or (truncate x) or x if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| N0.getOpcode() == ISD::ANY_EXTEND) { - if (N0.getOperand(0).getValueType() < VT) + if (N0.getOperand(0).getValueType().bitsLT(VT)) // if the source is smaller than the dest, we still need an extend return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); - else if (N0.getOperand(0).getValueType() > VT) + else if (N0.getOperand(0).getValueType().bitsGT(VT)) // if the source is larger than the dest, than we just need the truncate return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); else @@ -3946,7 +3946,7 @@ if (N0.getOpcode() == ISD::FP_ROUND && N0.Val->getConstantOperandVal(1) == 1){ SDOperand In = N0.getOperand(0); if (In.getValueType() == VT) return In; - if (VT < In.getValueType()) + if (VT.bitsLT(In.getValueType())) return DAG.getNode(ISD::FP_ROUND, VT, In, N0.getOperand(1)); return DAG.getNode(ISD::FP_EXTEND, VT, In); } @@ -4700,9 +4700,7 @@ MVT LVT = EVT; if (InVec.getOpcode() == ISD::BIT_CONVERT) { MVT BCVT = InVec.getOperand(0).getValueType(); - if (!BCVT.isVector() - || (EVT.getSizeInBits() > - BCVT.getVectorElementType().getSizeInBits())) + if (!BCVT.isVector() || EVT.bitsGT(BCVT.getVectorElementType())) return SDOperand(); InVec = InVec.getOperand(0); EVT = BCVT.getVectorElementType(); @@ -5261,7 +5259,7 @@ (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 MVT XType = N0.getValueType(); MVT AType = N2.getValueType(); - if (XType >= AType) { + if (XType.bitsGE(AType)) { // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a // single-bit constant. if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { @@ -5270,7 +5268,7 @@ SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); AddToWorkList(Shift.Val); - if (XType > AType) { + if (XType.bitsGT(AType)) { Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); AddToWorkList(Shift.Val); } @@ -5280,7 +5278,7 @@ DAG.getConstant(XType.getSizeInBits()-1, TLI.getShiftAmountTy())); AddToWorkList(Shift.Val); - if (XType > AType) { + if (XType.bitsGT(AType)) { Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); AddToWorkList(Shift.Val); } @@ -5304,7 +5302,7 @@ // cast from setcc result type to select result type if (AfterLegalize) { SCC = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC); - if (N2.getValueType() < SCC.getValueType()) + if (N2.getValueType().bitsLT(SCC.getValueType())) Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); else Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=52098&r1=52097&r2=52098&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sun Jun 8 15:54:56 2008 @@ -789,7 +789,7 @@ SPFI); // Truncate or zero extend offset to target pointer type. - unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; + unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3); // Add the offset to the index. unsigned EltSize = EltVT.getSizeInBits()/8; @@ -4063,7 +4063,7 @@ MVT NVT = TLI.getTypeToTransformTo(VT); assert(getTypeAction(VT) == Promote && "Caller should expand or legalize operands that are not promotable!"); - assert(NVT > VT && NVT.isInteger() == VT.isInteger() && + assert(NVT.bitsGT(VT) && NVT.isInteger() == VT.isInteger() && "Cannot promote to smaller type!"); SDOperand Tmp1, Tmp2, Tmp3; @@ -4110,9 +4110,9 @@ switch (getTypeAction(Node->getOperand(0).getValueType())) { case Legal: Result = LegalizeOp(Node->getOperand(0)); - assert(Result.getValueType() >= NVT && + assert(Result.getValueType().bitsGE(NVT) && "This truncation doesn't make sense!"); - if (Result.getValueType() > NVT) // Truncate to NVT instead of VT + if (Result.getValueType().bitsGT(NVT)) // Truncate to NVT instead of VT Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); break; case Promote: @@ -4574,7 +4574,7 @@ Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx, DAG.getConstant(EltSize, Idx.getValueType())); - if (Idx.getValueType().getSizeInBits() > TLI.getPointerTy().getSizeInBits()) + if (Idx.getValueType().bitsGT(TLI.getPointerTy())) Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx); else Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx); @@ -5352,7 +5352,7 @@ if (DestTy == MVT::f32) FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, PseudoSourceValue::getConstantPool(), 0); - else if (DestTy.getSizeInBits() > MVT(MVT::f32).getSizeInBits()) + else if (DestTy.bitsGT(MVT::f32)) // FIXME: Avoid the extend by construction the right constantpool? FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(), CPIdx, @@ -5493,12 +5493,10 @@ if (DestVT == MVT::f64) { // do nothing Result = Sub; - } else if (DestVT.getSizeInBits() < - MVT(MVT::f64).getSizeInBits()) { + } else if (DestVT.bitsLT(MVT::f64)) { Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub, DAG.getIntPtrConstant(0)); - } else if (DestVT.getSizeInBits() > - MVT(MVT::f64).getSizeInBits()) { + } else if (DestVT.bitsGT(MVT::f64)) { Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub); } return Result; @@ -5785,7 +5783,7 @@ MVT NVT = TLI.getTypeToTransformTo(VT); SDNode *Node = Op.Val; assert(getTypeAction(VT) == Expand && "Not an expanded type!"); - assert(((NVT.isInteger() && NVT < VT) || VT.isFloatingPoint() || + assert(((NVT.isInteger() && NVT.bitsLT(VT)) || VT.isFloatingPoint() || VT.isVector()) && "Cannot expand to FP value or to larger int value!"); // See if we already expanded it. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp?rev=52098&r1=52097&r2=52098&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp Sun Jun 8 15:54:56 2008 @@ -150,7 +150,7 @@ SDOperand &Lo, SDOperand &Hi) { MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDOperand Op = N->getOperand(0); - if (Op.getValueType().getSizeInBits() <= NVT.getSizeInBits()) { + if (Op.getValueType().bitsLE(NVT)) { // The low part is any extension of the input (which degenerates to a copy). Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Op); Hi = DAG.getNode(ISD::UNDEF, NVT); // The high part is undefined. @@ -171,7 +171,7 @@ SDOperand &Lo, SDOperand &Hi) { MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDOperand Op = N->getOperand(0); - if (Op.getValueType().getSizeInBits() <= NVT.getSizeInBits()) { + if (Op.getValueType().bitsLE(NVT)) { // The low part is zero extension of the input (which degenerates to a copy). Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, N->getOperand(0)); Hi = DAG.getConstant(0, NVT); // The high part is just a zero. @@ -195,7 +195,7 @@ SDOperand &Lo, SDOperand &Hi) { MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDOperand Op = N->getOperand(0); - if (Op.getValueType().getSizeInBits() <= NVT.getSizeInBits()) { + if (Op.getValueType().bitsLE(NVT)) { // The low part is sign extension of the input (which degenerates to a copy). Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, N->getOperand(0)); // The high part is obtained by SRA'ing all but one of the bits of low part. @@ -301,7 +301,7 @@ GetExpandedOp(N->getOperand(0), Lo, Hi); MVT EVT = cast(N->getOperand(1))->getVT(); - if (EVT.getSizeInBits() <= Lo.getValueType().getSizeInBits()) { + if (EVT.bitsLE(Lo.getValueType())) { // sext_inreg the low part if needed. Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, Lo.getValueType(), Lo, N->getOperand(1)); @@ -411,7 +411,7 @@ // Handle endianness of the load. if (TLI.isBigEndian()) std::swap(Lo, Hi); - } else if (N->getMemoryVT().getSizeInBits() <= NVT.getSizeInBits()) { + } else if (N->getMemoryVT().bitsLE(NVT)) { MVT EVT = N->getMemoryVT(); Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, EVT, @@ -834,7 +834,7 @@ SDOperand Idx = N->getOperand(1); // Make sure the type of Idx is big enough to hold the new values. - if (Idx.getValueType().getSizeInBits() < TLI.getPointerTy().getSizeInBits()) + if (Idx.getValueType().bitsLT(TLI.getPointerTy())) Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx); Idx = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, Idx); @@ -1179,7 +1179,7 @@ SDOperand FudgeInReg; if (DestTy == MVT::f32) FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0); - else if (DestTy.getSizeInBits() > MVT(MVT::f32).getSizeInBits()) + else if (DestTy.bitsGT(MVT::f32)) // FIXME: Avoid the extend by construction the right constantpool? FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(), CPIdx, NULL, 0, MVT::f32); @@ -1371,7 +1371,7 @@ Hi = DAG.getStore(Ch, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize, isVolatile, MinAlign(Alignment, IncrementSize)); return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); - } else if (N->getMemoryVT().getSizeInBits() <= NVT.getSizeInBits()) { + } else if (N->getMemoryVT().bitsLE(NVT)) { GetExpandedOp(N->getValue(), Lo, Hi); return DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset, N->getMemoryVT(), isVolatile, Alignment); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesFloatToInt.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesFloatToInt.cpp?rev=52098&r1=52097&r2=52098&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesFloatToInt.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesFloatToInt.cpp Sun Jun 8 15:54:56 2008 @@ -252,12 +252,10 @@ if (DestVT == MVT::f64) { // do nothing Result = Sub; - } else if (DestVT.getSizeInBits() < - MVT(MVT::f64).getSizeInBits()) { + } else if (DestVT.bitsLT(MVT::f64)) { Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub, DAG.getIntPtrConstant(0)); - } else if (DestVT.getSizeInBits() > - MVT(MVT::f64).getSizeInBits()) { + } else if (DestVT.bitsGT(MVT::f64)) { Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub); } return BitConvertToInteger(Result); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesScalarize.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesScalarize.cpp?rev=52098&r1=52097&r2=52098&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesScalarize.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesScalarize.cpp Sun Jun 8 15:54:56 2008 @@ -126,7 +126,7 @@ // so be sure to truncate it to the element type if necessary. SDOperand Op = N->getOperand(1); MVT EltVT = N->getValueType(0).getVectorElementType(); - if (Op.getValueType().getSizeInBits() > EltVT.getSizeInBits()) + if (Op.getValueType().bitsGT(EltVT)) Op = DAG.getNode(ISD::TRUNCATE, EltVT, Op); assert(Op.getValueType() == EltVT && "Invalid type for inserted value!"); return Op; Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesSplit.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesSplit.cpp?rev=52098&r1=52097&r2=52098&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesSplit.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesSplit.cpp Sun Jun 8 15:54:56 2008 @@ -483,7 +483,7 @@ Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx, DAG.getConstant(EltSize, Idx.getValueType())); - if (Idx.getValueType().getSizeInBits() > TLI.getPointerTy().getSizeInBits()) + if (Idx.getValueType().bitsGT(TLI.getPointerTy())) Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx); else Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=52098&r1=52097&r2=52098&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Sun Jun 8 15:54:56 2008 @@ -1983,7 +1983,7 @@ assert(VT.isInteger() && Operand.getValueType().isInteger() && "Invalid SIGN_EXTEND!"); if (Operand.getValueType() == VT) return Operand; // noop extension - assert(Operand.getValueType().getSizeInBits() < VT.getSizeInBits() + assert(Operand.getValueType().bitsLT(VT) && "Invalid sext node, dst < src!"); if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) return getNode(OpOpcode, VT, Operand.Val->getOperand(0)); @@ -1992,7 +1992,7 @@ assert(VT.isInteger() && Operand.getValueType().isInteger() && "Invalid ZERO_EXTEND!"); if (Operand.getValueType() == VT) return Operand; // noop extension - assert(Operand.getValueType().getSizeInBits() < VT.getSizeInBits() + assert(Operand.getValueType().bitsLT(VT) && "Invalid zext node, dst < src!"); if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x) return getNode(ISD::ZERO_EXTEND, VT, Operand.Val->getOperand(0)); @@ -2001,7 +2001,7 @@ assert(VT.isInteger() && Operand.getValueType().isInteger() && "Invalid ANY_EXTEND!"); if (Operand.getValueType() == VT) return Operand; // noop extension - assert(Operand.getValueType().getSizeInBits() < VT.getSizeInBits() + assert(Operand.getValueType().bitsLT(VT) && "Invalid anyext node, dst < src!"); if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND) // (ext (zext x)) -> (zext x) and (ext (sext x)) -> (sext x) @@ -2011,18 +2011,16 @@ assert(VT.isInteger() && Operand.getValueType().isInteger() && "Invalid TRUNCATE!"); if (Operand.getValueType() == VT) return Operand; // noop truncate - assert(Operand.getValueType().getSizeInBits() > VT.getSizeInBits() + assert(Operand.getValueType().bitsGT(VT) && "Invalid truncate node, src < dst!"); if (OpOpcode == ISD::TRUNCATE) return getNode(ISD::TRUNCATE, VT, Operand.Val->getOperand(0)); else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ANY_EXTEND) { // If the source is smaller than the dest, we still need an extend. - if (Operand.Val->getOperand(0).getValueType().getSizeInBits() - < VT.getSizeInBits()) + if (Operand.Val->getOperand(0).getValueType().bitsLT(VT)) return getNode(OpOpcode, VT, Operand.Val->getOperand(0)); - else if (Operand.Val->getOperand(0).getValueType().getSizeInBits() - > VT.getSizeInBits()) + else if (Operand.Val->getOperand(0).getValueType().bitsGT(VT)) return getNode(ISD::TRUNCATE, VT, Operand.Val->getOperand(0)); else return Operand.Val->getOperand(0); @@ -2156,15 +2154,14 @@ assert(VT == N1.getValueType() && "Not an inreg round!"); assert(VT.isFloatingPoint() && EVT.isFloatingPoint() && "Cannot FP_ROUND_INREG integer types"); - assert(EVT.getSizeInBits() <= VT.getSizeInBits() && - "Not rounding down!"); + assert(EVT.bitsLE(VT) && "Not rounding down!"); if (cast(N2)->getVT() == VT) return N1; // Not actually rounding. break; } case ISD::FP_ROUND: assert(VT.isFloatingPoint() && N1.getValueType().isFloatingPoint() && - VT.getSizeInBits() <= N1.getValueType().getSizeInBits() && + VT.bitsLE(N1.getValueType()) && isa(N2) && "Invalid FP_ROUND!"); if (N1.getValueType() == VT) return N1; // noop conversion. break; @@ -2174,8 +2171,7 @@ assert(VT == N1.getValueType() && "Not an inreg extend!"); assert(VT.isInteger() && EVT.isInteger() && "Cannot *_EXTEND_INREG FP types"); - assert(EVT.getSizeInBits() <= VT.getSizeInBits() && - "Not extending!"); + assert(EVT.bitsLE(VT) && "Not extending!"); if (VT == EVT) return N1; // noop assertion. break; } @@ -2184,8 +2180,7 @@ assert(VT == N1.getValueType() && "Not an inreg extend!"); assert(VT.isInteger() && EVT.isInteger() && "Cannot *_EXTEND_INREG FP types"); - assert(EVT.getSizeInBits() <= VT.getSizeInBits() && - "Not extending!"); + assert(EVT.bitsLE(VT) && "Not extending!"); if (EVT == VT) return N1; // Not actually extending if (N1C) { @@ -2652,7 +2647,7 @@ LVT = (MVT::SimpleValueType)(LVT.getSimpleVT() - 1); assert(LVT.isInteger()); - if (VT > LVT) + if (VT.bitsGT(LVT)) VT = LVT; } @@ -2959,7 +2954,7 @@ Entry.Node = Dst; Entry.Ty = IntPtrTy; Args.push_back(Entry); // Extend or truncate the argument to be an i32 value for the call. - if (Src.getValueType() > MVT::i32) + if (Src.getValueType().bitsGT(MVT::i32)) Src = getNode(ISD::TRUNCATE, MVT::i32, Src); else Src = getNode(ISD::ZERO_EXTEND, MVT::i32, Src); @@ -3045,7 +3040,7 @@ if (VT.isVector()) assert(EVT == VT.getVectorElementType() && "Invalid vector extload!"); else - assert(EVT.getSizeInBits() < VT.getSizeInBits() && + assert(EVT.bitsLT(VT) && "Should only be an extending load, not truncating!"); assert((ExtType == ISD::EXTLOAD || VT.isInteger()) && "Cannot sign/zero extend a FP/Vector load!"); @@ -3154,8 +3149,7 @@ if (VT == SVT) return getStore(Chain, Val, Ptr, SV, SVOffset, isVolatile, Alignment); - assert(VT.getSizeInBits() > SVT.getSizeInBits() && - "Not a truncation?"); + assert(VT.bitsGT(SVT) && "Not a truncation?"); assert(VT.isInteger() == SVT.isInteger() && "Can't do FP-INT conversion!"); @@ -4228,7 +4222,7 @@ /// const MVT *SDNode::getValueTypeList(MVT VT) { if (VT.isExtended()) { - static std::set EVTs; + static std::set EVTs; return &(*EVTs.insert(VT).first); } else { static MVT VTs[MVT::LAST_VALUETYPE]; Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=52098&r1=52097&r2=52098&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sun Jun 8 15:54:56 2008 @@ -918,7 +918,7 @@ if (PartVT.isInteger() && ValueVT.isInteger()) { - if (ValueVT.getSizeInBits() < PartVT.getSizeInBits()) { + if (ValueVT.bitsLT(PartVT)) { // For a truncate, see if we have any information to // indicate whether the truncated bits will always be // zero or sign-extension. @@ -932,7 +932,7 @@ } if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { - if (ValueVT < Val.getValueType()) + if (ValueVT.bitsLT(Val.getValueType())) // FP_ROUND's are always exact here. return DAG.getNode(ISD::FP_ROUND, ValueVT, Val, DAG.getIntPtrConstant(1)); @@ -1268,7 +1268,7 @@ // at least 32-bit. But this is not necessary for non-C calling conventions. if (VT.isInteger()) { MVT MinVT = TLI.getRegisterType(MVT::i32); - if (VT.getSizeInBits() < MinVT.getSizeInBits()) + if (VT.bitsLT(MinVT)) VT = MinVT; } @@ -1655,7 +1655,7 @@ // register so it can be used as an index into the jump table in a // subsequent basic block. This value may be smaller or larger than the // target's pointer type, and therefore require extension or truncating. - if (VT.getSizeInBits() > TLI.getPointerTy().getSizeInBits()) + if (VT.bitsGT(TLI.getPointerTy())) SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB); else SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB); @@ -1705,7 +1705,7 @@ ISD::SETUGT); SDOperand ShiftOp; - if (VT.getSizeInBits() > TLI.getShiftAmountTy().getSizeInBits()) + if (VT.bitsGT(TLI.getShiftAmountTy())) ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB); else ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB); @@ -2386,10 +2386,9 @@ SDOperand Op1 = getValue(I.getOperand(0)); SDOperand Op2 = getValue(I.getOperand(1)); - if (TLI.getShiftAmountTy().getSizeInBits() < - Op2.getValueType().getSizeInBits()) + if (TLI.getShiftAmountTy().bitsLT(Op2.getValueType())) Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2); - else if (TLI.getShiftAmountTy() > Op2.getValueType()) + else if (TLI.getShiftAmountTy().bitsGT(Op2.getValueType())) Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2); setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2)); @@ -2611,7 +2610,7 @@ MVT SrcVT = N.getValueType(); MVT DestVT = TLI.getValueType(I.getType()); SDOperand Result; - if (DestVT.getSizeInBits() < SrcVT.getSizeInBits()) + if (DestVT.bitsLT(SrcVT)) Result = DAG.getNode(ISD::TRUNCATE, DestVT, N); else // Note: ZERO_EXTEND can handle cases where the sizes are equal too @@ -2625,7 +2624,7 @@ SDOperand N = getValue(I.getOperand(0)); MVT SrcVT = N.getValueType(); MVT DestVT = TLI.getValueType(I.getType()); - if (DestVT.getSizeInBits() < SrcVT.getSizeInBits()) + if (DestVT.bitsLT(SrcVT)) setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); else // Note: ZERO_EXTEND can handle cases where the sizes are equal too @@ -2777,9 +2776,9 @@ // If the index is smaller or larger than intptr_t, truncate or extend // it. - if (IdxN.getValueType() < N.getValueType()) { + if (IdxN.getValueType().bitsLT(N.getValueType())) { IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN); - } else if (IdxN.getValueType() > N.getValueType()) + } else if (IdxN.getValueType().bitsGT(N.getValueType())) IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN); // If this is a multiply by a power of two, turn it into a shl @@ -2814,9 +2813,9 @@ SDOperand AllocSize = getValue(I.getArraySize()); MVT IntPtr = TLI.getPointerTy(); - if (IntPtr < AllocSize.getValueType()) + if (IntPtr.bitsLT(AllocSize.getValueType())) AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize); - else if (IntPtr > AllocSize.getValueType()) + else if (IntPtr.bitsGT(AllocSize.getValueType())) AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize); AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize, @@ -3325,7 +3324,7 @@ case Intrinsic::eh_dwarf_cfa: { MVT VT = getValue(I.getOperand(1)).getValueType(); SDOperand CfaArg; - if (VT.getSizeInBits() > TLI.getPointerTy().getSizeInBits()) + if (VT.bitsGT(TLI.getPointerTy())) CfaArg = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), getValue(I.getOperand(1))); else @@ -3827,8 +3826,7 @@ // If we have already found this register in a different register class, // choose the one with the largest VT specified. For example, on // PowerPC, we favor f64 register classes over f32. - if (FoundVT == MVT::Other || - FoundVT.getSizeInBits() < (*I).getSizeInBits()) { + if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) { ThisVT = *I; break; } @@ -4478,9 +4476,9 @@ MVT IntPtr = TLI.getPointerTy(); - if (IntPtr < Src.getValueType()) + if (IntPtr.bitsLT(Src.getValueType())) Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src); - else if (IntPtr > Src.getValueType()) + else if (IntPtr.bitsGT(Src.getValueType())) Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src); // Scale the source by the type size. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=52098&r1=52097&r2=52098&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Sun Jun 8 15:54:56 2008 @@ -384,7 +384,7 @@ MVT DestVT = getTypeToTransformTo(NewVT); RegisterVT = DestVT; - if (DestVT < NewVT) { + if (DestVT.bitsLT(NewVT)) { // Value is expanded, e.g. i64 -> i16. return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); } else { Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp?rev=52098&r1=52097&r2=52098&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp Sun Jun 8 15:54:56 2008 @@ -356,7 +356,7 @@ std::vector RetVals; MVT RetTyVT = getValueType(RetTy); MVT ActualRetTyVT = RetTyVT; - if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i32) + if (RetTyVT.getSimpleVT() >= MVT::i1 && RetTyVT.getSimpleVT() <= MVT::i32) ActualRetTyVT = MVT::i64; if (RetTyVT != MVT::isVoid) Modified: llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp?rev=52098&r1=52097&r2=52098&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp Sun Jun 8 15:54:56 2008 @@ -112,7 +112,7 @@ { MVT vt = CN->getValueType(0); Imm = (short) CN->getValue(); - if (vt >= MVT::i1 && vt <= MVT::i16) { + if (vt.getSimpleVT() >= MVT::i1 && vt.getSimpleVT() <= MVT::i16) { return true; } else if (vt == MVT::i32) { int32_t i_val = (int32_t) CN->getValue(); Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=52098&r1=52097&r2=52098&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Sun Jun 8 15:54:56 2008 @@ -2218,7 +2218,7 @@ N0 = (N0.getOpcode() != ISD::Constant ? DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, N0) : DAG.getConstant(cast(N0)->getValue(), MVT::i16)); - N1Opc = (N1.getValueType() < MVT::i16 ? ISD::ZERO_EXTEND : ISD::TRUNCATE); + N1Opc = N1.getValueType().bitsLT(MVT::i16) ? ISD::ZERO_EXTEND : ISD::TRUNCATE; N1 = (N1.getOpcode() != ISD::Constant ? DAG.getNode(N1Opc, MVT::i16, N1) : DAG.getConstant(cast(N1)->getValue(), MVT::i16)); @@ -2236,7 +2236,7 @@ N0 = (N0.getOpcode() != ISD::Constant ? DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, N0) : DAG.getConstant(cast(N0)->getValue(), MVT::i16)); - N1Opc = (N1.getValueType() < MVT::i16 ? ISD::ZERO_EXTEND : ISD::TRUNCATE); + N1Opc = N1.getValueType().bitsLT(MVT::i16) ? ISD::ZERO_EXTEND : ISD::TRUNCATE; N1 = (N1.getOpcode() != ISD::Constant ? DAG.getNode(N1Opc, MVT::i16, N1) : DAG.getConstant(cast(N1)->getValue(), MVT::i16)); @@ -2249,7 +2249,7 @@ N0 = (N0.getOpcode() != ISD::Constant ? DAG.getNode(ISD::SIGN_EXTEND, MVT::i16, N0) : DAG.getConstant(cast(N0)->getValue(), MVT::i16)); - N1Opc = (N1.getValueType() < MVT::i16 ? ISD::SIGN_EXTEND : ISD::TRUNCATE); + N1Opc = N1.getValueType().bitsLT(MVT::i16) ? ISD::SIGN_EXTEND : ISD::TRUNCATE; N1 = (N1.getOpcode() != ISD::Constant ? DAG.getNode(N1Opc, MVT::i16, N1) : DAG.getConstant(cast(N1)->getValue(), MVT::i16)); @@ -2262,7 +2262,7 @@ N0 = (N0.getOpcode() != ISD::Constant ? DAG.getNode(ISD::SIGN_EXTEND, MVT::i16, N0) : DAG.getConstant(cast(N0)->getValue(), MVT::i16)); - N1Opc = (N1.getValueType() < MVT::i16 ? ISD::SIGN_EXTEND : ISD::TRUNCATE); + N1Opc = N1.getValueType().bitsLT(MVT::i16) ? ISD::SIGN_EXTEND : ISD::TRUNCATE; N1 = (N1.getOpcode() != ISD::Constant ? DAG.getNode(N1Opc, MVT::i16, N1) : DAG.getConstant(cast(N1)->getValue(), MVT::i16)); Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=52098&r1=52097&r2=52098&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Sun Jun 8 15:54:56 2008 @@ -1173,7 +1173,7 @@ if (C->isNullValue() && CC == ISD::SETEQ) { MVT VT = Op.getOperand(0).getValueType(); SDOperand Zext = Op.getOperand(0); - if (VT < MVT::i32) { + if (VT.bitsLT(MVT::i32)) { VT = MVT::i32; Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0)); } Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=52098&r1=52097&r2=52098&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sun Jun 8 15:54:56 2008 @@ -4410,7 +4410,7 @@ SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { MVT SrcVT = Op.getOperand(0).getValueType(); - assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 && + assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 && "Unknown SINT_TO_FP to lower!"); // These are really Legal; caller falls through into that case. @@ -4470,7 +4470,8 @@ std::pair X86TargetLowering:: FP_TO_SINTHelper(SDOperand Op, SelectionDAG &DAG) { - assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 && + assert(Op.getValueType().getSimpleVT() <= MVT::i64 && + Op.getValueType().getSimpleVT() >= MVT::i16 && "Unknown FP_TO_SINT to lower!"); // These are really Legal. @@ -4607,12 +4608,12 @@ MVT SrcVT = Op1.getValueType(); // If second operand is smaller, extend it first. - if (SrcVT.getSizeInBits() < VT.getSizeInBits()) { + if (SrcVT.bitsLT(VT)) { Op1 = DAG.getNode(ISD::FP_EXTEND, VT, Op1); SrcVT = VT; } // And if it is bigger, shrink it first. - if (SrcVT.getSizeInBits() > VT.getSizeInBits()) { + if (SrcVT.bitsGT(VT)) { Op1 = DAG.getNode(ISD::FP_ROUND, VT, Op1, DAG.getIntPtrConstant(1)); SrcVT = VT; } @@ -4639,7 +4640,7 @@ SDOperand SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1); // Shift sign bit right or left if the two operands have different types. - if (SrcVT.getSizeInBits() > VT.getSizeInBits()) { + if (SrcVT.bitsGT(VT)) { // Op0 is MVT::f32, Op1 is MVT::f64. SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2f64, SignBit); SignBit = DAG.getNode(X86ISD::FSRL, MVT::v2f64, SignBit, @@ -4909,7 +4910,7 @@ break; } - if (AVT > MVT::i8) { + if (AVT.bitsGT(MVT::i8)) { unsigned UBytes = AVT.getSizeInBits() / 8; Count = DAG.getIntPtrConstant(SizeVal / UBytes); BytesLeft = SizeVal % UBytes; Modified: llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp?rev=52098&r1=52097&r2=52098&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp Sun Jun 8 15:54:56 2008 @@ -339,10 +339,10 @@ // This is an fp<->int conversion? if (SrcVT.isInteger() != DstVT.isInteger()) return false; - + // If this is an extension, it will be a zero or sign extension, which // isn't a noop. - if (SrcVT < DstVT) return false; + if (SrcVT.bitsLT(DstVT)) return false; // If these values will be promoted, find out what they will be promoted // to. This helps us consider truncates on PPC as noop copies when they From sabre at nondot.org Sun Jun 8 16:19:09 2008 From: sabre at nondot.org (Chris Lattner) Date: Sun, 08 Jun 2008 21:19:09 -0000 Subject: [llvm-commits] [llvm] r52099 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <200806082119.m58LJ9bJ005268@zion.cs.uiuc.edu> Author: lattner Date: Sun Jun 8 16:19:07 2008 New Revision: 52099 URL: http://llvm.org/viewvc/llvm-project?rev=52099&view=rev Log: add more notes. Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=52099&r1=52098&r2=52099&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Sun Jun 8 16:19:07 2008 @@ -85,6 +85,9 @@ LLVM release to do this. One nice impact of this is that the LLVM regression test suite no longer depends on llvm-upgrade, which makes it run faster.

      +

      llvm2cpp tool has been folded into llc, use + llc -march=cpp instead of llvm2cpp.

      +

      LLVM API Changes:

        @@ -249,8 +252,11 @@
      • LLVM now includes a simple 'Jump Threading' pass, which attempts to simplify conditional branches using information about predecessor blocks, simplifying - the control flow graph. This pass is pretty basic at this point, but catches - some important cases and provides a foundation to build on.
        • + the control flow graph. This pass is pretty basic at this point, but + catches some important cases and provides a foundation to build on. + +
      • Several corner case bugs which could lead to deleting volatile memory + accesses have been fixed.
      @@ -275,7 +281,9 @@ target-specific support. Use of APInt is also a step toward support for non-power-of-2 integer sizes. -
    • Several compile time speedups for code with large basic blocks.
      • +
    • LLVM 2.3 includes several compile time speedups for code with large basic + blocks, particular in the instruction selection phase, register allocation, + scheduling, and tail merging/jump threading.
    • Several improvements which make llc's --view-sunit-dags visualization of scheduling dependency graphs easier to understand.
      • @@ -286,6 +294,16 @@
    • memcpy lowering in the backend is more aggressive, particularly for memcpy calls introduced by the code generator when handling pass-by-value structure argument copies.
      • + +
    • Inline assembly with multiple register results now returns those results + directly in the appropriate registers, rather than going through memory. + Inline assembly that uses constraints like "ir" with immediates now use the + 'i' form when possible instead of always loading the value in a register. + This saves an instruction and reduces register use.
      • + +
    • Added support for PIC/GOT style tail calls on x86/32 and initial support + for tail calls on PowerPC 32 (it may also work on ppc64 but not + thoroughly tested).
    @@ -336,6 +354,9 @@
  • The register allocator can now rematerialize PIC-base computations.
    • +
  • The "t" and "f" inline assembly constraints for the X87 floating point stack + now work. However, the "u" constraint is still not fully supported.
    • + @@ -351,8 +372,6 @@
    • The LLVM C backend now supports vector code.
      • - -
    @@ -370,8 +389,9 @@
    • LLVM now builds with GCC 4.3.
      • -
    • llvm2cpp tool has been folded into llc, use - llc -march=cpp
      • +
    • Bugpoint now supports running custom scripts (with the -run-custom + option) to determine how to execute the command and whether it is making + forward process.
    @@ -456,8 +476,8 @@ all inline assembly that uses the X86 floating point stack. It supports the 'f' and 't' constraints, but not 'u'. -
  • The X86 backend generates inefficient floating point code when configured to - generate code for systems that don't have SSE2.
    • +
  • The X86 backend generates inefficient floating point code when configured + to generate code for systems that don't have SSE2.
  • Win64 code generation wasn't widely tested. Everything should work, but we expect small issues to happen. Also, llvm-gcc cannot build mingw64 runtime currently due @@ -494,7 +514,8 @@ results (PR1388).
  • Compilation for ARM Linux OABI (old ABI) is supported, but not fully tested.
    • -
  • There is a bug in QEMU-ARM (<= 0.9.0) which causes it to incorrectly execute +
  • There is a bug in QEMU-ARM (<= 0.9.0) which causes it to incorrectly + execute programs compiled with LLVM. Please use more recent versions of QEMU.
    • @@ -651,11 +672,12 @@ or finish at a non-byte offset in a record. Workaround: do not pack records or use representation clauses that result in a field of a non-discrete type starting or finishing in the middle of a byte. -
  • The lli interpreter considers 'main' -as generated by the Ada binder to be invalid. -Workaround: hand edit the file to use pointers for argv and envp rather than -integers.
    • -
  • The -fstack-check option is ignored.
    • +
  • The lli interpreter considers +'main' as generated by the Ada binder to be invalid. +Workaround: hand edit the file to use pointers for argv and +envp rather than integers.
    • +
  • The -fstack-check option is +ignored.
    • From sabre at nondot.org Sun Jun 8 16:34:41 2008 From: sabre at nondot.org (Chris Lattner) Date: Sun, 08 Jun 2008 21:34:41 -0000 Subject: [llvm-commits] [llvm] r52100 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <200806082134.m58LYfof005717@zion.cs.uiuc.edu> Author: lattner Date: Sun Jun 8 16:34:41 2008 New Revision: 52100 URL: http://llvm.org/viewvc/llvm-project?rev=52100&view=rev Log: start edits. Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=52100&r1=52099&r2=52100&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Sun Jun 8 16:34:41 2008 @@ -79,71 +79,114 @@
    -

    LLVM 2.2 was the last LLVM release to support llvm-gcc 4.0 and llvm-upgrade. -llvm-gcc 4.0 has been replaced with llvm-gcc 4.2. llvm-upgrade was useful for -upgrading LLVM 1.9 files to LLVM 2.x syntax, but you can always use a previous -LLVM release to do this. One nice impact of this is that the LLVM regression -test suite no longer depends on llvm-upgrade, which makes it run faster.

    +

    LLVM 2.3 no longer supports llvm-gcc 4.0, it has been replaced with + llvm-gcc 4.2.

    -

    llvm2cpp tool has been folded into llc, use +

    LLVM 2.3 no longer includes the llvm-upgrade tool. It was useful + for upgrading LLVM 1.9 files to LLVM 2.x syntax, but you can always use a + previous LLVM release to do this. One nice impact of this is that the LLVM + regression test suite no longer depends on llvm-upgrade, which makes it run + faster.

    + +

    The llvm2cpp tool has been folded into llc, use llc -march=cpp instead of llvm2cpp.

    LLVM API Changes:

      -
    • Several core LLVM IR classes have migrated to use 'FOOCLASS::Create(...)' - instead of 'new FOOCLASS(...)' (e.g. where FOOCLASS=BasicBlock). We hope to - standardize on FOOCLASS::Create for all IR classes in the future, but not - all of them have been moved over yet.
      • +
    • Several core LLVM IR classes have migrated to use the + 'FOOCLASS::Create(...)' pattern instead of 'new + FOOCLASS(...)' (e.g. where FOOCLASS=BasicBlock). We hope to + standardize on FOOCLASS::Create for all IR classes in the future, + but not all of them have been moved over yet.
    • LLVM 2.3 renames the LLVMBuilder and LLVMFoldingBuilder classes to IRBuilder.
    • MRegisterInfo was renamed to TargetRegisterInfo.
    • The MappedFile class is gone, please use MemoryBuffer instead.
      • -
    • The '-enable-eh' flag to llc has been removed. Now code should encode - whether it is safe to not generate unwind information for a function by - tagging the Function object with the 'nounwind' attribute.
      • +
    • The '-enable-eh' flag to llc has been removed. Now code should + encode whether it is safe to omit unwind information for a function by + tagging the Function object with the 'nounwind' attribute.
    -Major New Features +Other LLVM Sub-Projects
    -

    LLVM 2.3 includes several major new capabilities:

    - -
      -
    • Multiple Return Value Support.
      • - +

      +

      The clang project is an effort to build +a set of new 'llvm native' front-end technologies for the LLVM optimizer +and code generator. Currently, its C and Objective-C support is maturing +nicely, and it has advanced source-to-source analysis and transformation +capabilities. If you are interested in building source-level tools for C and +Objective-C (and eventually C++), you should take a look. However, note that +clang is not an official part of the LLVM 2.3 release. If you are interested in +this project, please see its web site.

      -

    • LLVM 2.3 includes a complete reimplementation of the "llvmc" tool. It is -designed to overcome several problems with the original llvmc and to provide a -superset of the features of the 'gcc' driver.

      -

      The main features of llvmc2 is:

      +

      -
        -
      • Extended handling of command line options and smart rules for -dispatching them to different tools.
        • -
      • Flexible (and extensible) rules for defining different tools.
        • -
      • The different intermediate steps performed by tools are represented -as edges in the abstract graph.
        • -
      • The 'language' for driver behavior definition is tablegen and thus -it's relatively easy to add new features.
        • -
      • The definition of driver is transformed into set of C++ classes, thus -no runtime interpretation is needed.
        • -
      -
      • +
    + +
    +Major New Features +
    -
  • Reimplemented LTO interface in - C.
    • +
    +

    LLVM 2.3 includes several major new capabilities:

    -
  • Kaleidoscope tutorial in Ocaml.
    • +
      +

    • The biggest change in LLVM 2.3 is Multiple Return Value (MRV) support. + MRVs allow LLVM IR to directly represent functions that return multiple + values without having to pass them "by reference" in the LLVM IR. This + allows a front-end to generate more efficient code, as MRVs are generally + returned in registers if a target supports them. See the LLVM IR Reference for more details.

      + +

      MRVs are fully supported in the LLVM IR, but are not yet fully supported in + on all targets. However, it is generally safe to return up to 2 values from + a function: most targets should be able to handle at least that. MRV + support is a critical requirement for X86-64 ABI support, as X86-64 requires + the ability to return multiple registers from functions, and we use MRVs to + accomplish this in a direct way.

      • + + +

    • LLVM 2.3 includes a complete reimplementation of the "llvmc" + tool. It is designed to overcome several problems with the original + llvmc and to provide a superset of the features of the + 'gcc' driver.

      + +

      The main features of llvmc2 are: +

        +
      • Extended handling of command line options and smart rules for + dispatching them to different tools.
        • +
      • Flexible (and extensible) rules for defining different tools.
        • +
      • The different intermediate steps performed by tools are represented + as edges in the abstract graph.
        • +
      • The 'language' for driver behavior definition is tablegen and thus + it's relatively easy to add new features.
        • +
      • The definition of driver is transformed into set of C++ classes, thus + no runtime interpretation is needed.
        • +

      +
      • + + +

    • LLVM 2.3 includes a completely rewritten interface for Link Time Optimization. This interface + is written in C, which allows for easier integration with C code bases, and + incorporates improvements we learned about from the first incarnation of the + interface.

      • + +

    • The Kaleidoscope tutorial now + includes a "port" of the tutorial that uses the Ocaml bindings to implement + the Kaleidoscope language.

    @@ -152,7 +195,7 @@
    -llvm-gcc 4.2 Improvements and Clang +llvm-gcc 4.2 Improvements
    @@ -165,15 +208,6 @@

    llvm-gcc 4.2 includes many other fixes which improve conformance with the relevant parts of the GCC testsuite.

    -

    The clang project is an effort to build -a set of new 'llvm native' front-end technologies for the LLVM optimizer -and code generator. Currently, its C and Objective-C support is maturing -nicely, and it has advanced source-to-source analysis and transformation -capabilities. If you are interested in building source-level tools for C and -Objective-C (and eventually C++), you should take a look. However, note that -clang is not an official part of the LLVM 2.3 release. If you are interested in -this project, please see its web site.

    -
    From sabre at nondot.org Sun Jun 8 16:58:17 2008 From: sabre at nondot.org (Chris Lattner) Date: Sun, 08 Jun 2008 21:58:17 -0000 Subject: [llvm-commits] [llvm] r52102 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <200806082158.m58LwHOo006345@zion.cs.uiuc.edu> Author: lattner Date: Sun Jun 8 16:58:17 2008 New Revision: 52102 URL: http://llvm.org/viewvc/llvm-project?rev=52102&view=rev Log: add vmkit and rewrite clang section Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=52102&r1=52101&r2=52102&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Sun Jun 8 16:58:17 2008 @@ -13,6 +13,7 @@
    1. Introduction
      2. +
    2. Major Changes and Sub-project Status
    3. What's New?
    4. Installation Instructions
    5. Portability and Supported Platforms
      6. @@ -55,7 +56,7 @@
      - What's New? + Major Changes and Sub-project Status
      @@ -116,23 +117,80 @@
    -

    -

    The clang project is an effort to build -a set of new 'llvm native' front-end technologies for the LLVM optimizer -and code generator. Currently, its C and Objective-C support is maturing -nicely, and it has advanced source-to-source analysis and transformation -capabilities. If you are interested in building source-level tools for C and -Objective-C (and eventually C++), you should take a look. However, note that -clang is not an official part of the LLVM 2.3 release. If you are interested in -this project, please see its web site.

    +The core LLVM 2.3 distribution currently consists of code from the core LLVM +repository (which roughly contains the LLVM optimizer, code generators and +supporting tools) and the llvm-gcc repository. In addition to this code, the +LLVM Project includes other sub-projects that are in development. The two which +are the most actively developed are the new vmkit Project +and the Clang Project. +

    +
    + +
    +vmkit +
    +
    +

    +The "vmkit" project is a new addition to the LLVM family. It is an +implementation of a JVM and a CLI Virtual Machines (Microsoft .NET is an +implementation of the CLI) using the Just-In-Time compiler of LLVM.

    + +

    The JVM, called JnJVM, executes real-world applications such as Apache +projects (e.g. Felix and Tomcat) and the SpecJVM98 benchmark. It uses the GNU +Classpath project for the base classes. The CLI implementation, called N3, is +its in early stages but can execute simple applications and the "pnetmark" +benchmark. It uses the pnetlib project as its core library.

    + +

    The 'vmkit' VMs compare in performance with industrial and top open-source +VMs on scientific applications. Besides the JIT, the VMs use many features of +the LLVM framework, including the standard set of optimizations, atomic +operations, custom function provider and memory manager for JITed methods, and +specific virtual machine optimizations. vmkit is not an official part of LLVM +2.3 release. It is publicly available under the LLVM license and can be +downloaded from: +

    + +

    +svn co http://llvm.org/svn/llvm-project/vmkit/trunk vmkit

    +
    +Clang +
    + +
    + +

    The Clang project is an effort to build +a set of new 'LLVM native' front-end technologies for the LLVM optimizer +and code generator. Clang is continuing to make major strides forward in all +areas. Its C and Objective-C parsing support is very solid, and the code +generation support is far enough along to build many C applications. While not +yet production quality, it is progressing very nicely. In addition, C++ +front-end work has started to make significant progress.

    + +

    At this point, Clang is most useful if you are interested in source-to-source +transformations (such as refactoring) and other source-level tools for C and +Objective-C. Clang now also includes tools for turning C code into pretty HTML, +and includes a new static +analysis tool in development. This tool is automatically focused on finding +bugs in C and Objective-C code.

    + +
    + + + +
    + What's New? +
    + + +
    Major New Features
    @@ -156,7 +214,6 @@ the ability to return multiple registers from functions, and we use MRVs to accomplish this in a direct way.

    -

  • LLVM 2.3 includes a complete reimplementation of the "llvmc" tool. It is designed to overcome several problems with the original llvmc and to provide a superset of the features of the @@ -176,7 +233,6 @@

    • -

  • LLVM 2.3 includes a completely rewritten interface for Link Time Optimization. This interface is written in C, which allows for easier integration with C code bases, and @@ -205,6 +261,8 @@

    llvm-gcc 4.2 includes numerous fixes to better support the Objective-C front-end. Objective-C now works very well on Mac OS/X.

    +

    Fortran EQUIVALENCEs are now supported by the gfortran front-end.

    +

    llvm-gcc 4.2 includes many other fixes which improve conformance with the relevant parts of the GCC testsuite.

    From gordonhenriksen at mac.com Sun Jun 8 17:05:11 2008 From: gordonhenriksen at mac.com (Gordon Henriksen) Date: Sun, 08 Jun 2008 22:05:11 -0000 Subject: [llvm-commits] [llvm] r52103 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <200806082205.m58M5BCg006545@zion.cs.uiuc.edu> Author: gordon Date: Sun Jun 8 17:05:11 2008 New Revision: 52103 URL: http://llvm.org/viewvc/llvm-project?rev=52103&view=rev Log: Revert a bad edit from r52095. Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=52103&r1=52102&r2=52103&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Sun Jun 8 17:05:11 2008 @@ -320,7 +320,7 @@
    • -
  • LLVM includes a new memcpy optimization pass removes +
  • LLVM includes a new memcpy optimization pass which removes dead memcpy calls, unneeded copies of aggregates, and performs return slot optimization. The LLVM optimizer now notices long sequences of consecutive stores and merges them into memcpy's where profitable.
    • From gohman at apple.com Sun Jun 8 17:44:44 2008 From: gohman at apple.com (Dan Gohman) Date: Sun, 08 Jun 2008 22:44:44 -0000 Subject: [llvm-commits] [llvm] r52104 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <200806082244.m58Miihw007653@zion.cs.uiuc.edu> Author: djg Date: Sun Jun 8 17:44:43 2008 New Revision: 52104 URL: http://llvm.org/viewvc/llvm-project?rev=52104&view=rev Log: Fix a grammero. Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=52104&r1=52103&r2=52104&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Sun Jun 8 17:44:43 2008 @@ -374,8 +374,8 @@ non-power-of-2 integer sizes.
  • LLVM 2.3 includes several compile time speedups for code with large basic - blocks, particular in the instruction selection phase, register allocation, - scheduling, and tail merging/jump threading.
    • + blocks, particularly in the instruction selection phase, register + allocation, scheduling, and tail merging/jump threading.
  • Several improvements which make llc's --view-sunit-dags visualization of scheduling dependency graphs easier to understand.
    • From gohman at apple.com Sun Jun 8 17:49:27 2008 From: gohman at apple.com (Dan Gohman) Date: Sun, 08 Jun 2008 22:49:27 -0000 Subject: [llvm-commits] [llvm] r52105 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <200806082249.m58MnR9W007951@zion.cs.uiuc.edu> Author: djg Date: Sun Jun 8 17:49:27 2008 New Revision: 52105 URL: http://llvm.org/viewvc/llvm-project?rev=52105&view=rev Log: Describe MachineMemOperands. Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=52105&r1=52104&r2=52105&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Sun Jun 8 17:49:27 2008 @@ -365,7 +365,12 @@ faster:

      -
    • MemOperand in the code generator: describe me!.
      • +
    • The code generator now has support for carrying information about memory + references throughout the entire code generation process, via the + + MachineMemOperand class. In the future this will be used to improve + both pre-pass and post-pass scheduling, and to improve compiler-debugging + output.
    • The target-independent code generator infrastructure now uses LLVM's APInt class to handle integer values, which allows it to support integer types From gohman at apple.com Sun Jun 8 17:57:59 2008 From: gohman at apple.com (Dan Gohman) Date: Sun, 08 Jun 2008 22:57:59 -0000 Subject: [llvm-commits] [llvm] r52106 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <200806082257.m58Mvxa4008387@zion.cs.uiuc.edu> Author: djg Date: Sun Jun 8 17:57:59 2008 New Revision: 52106 URL: http://llvm.org/viewvc/llvm-project?rev=52106&view=rev Log: Add some links to doxygen documentation. Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=52106&r1=52105&r2=52106&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Sun Jun 8 17:57:59 2008 @@ -101,9 +101,14 @@ standardize on FOOCLASS::Create for all IR classes in the future, but not all of them have been moved over yet.
    • LLVM 2.3 renames the LLVMBuilder and LLVMFoldingBuilder classes to - IRBuilder.
      • -
    • MRegisterInfo was renamed to TargetRegisterInfo.
      • -
    • The MappedFile class is gone, please use MemoryBuffer instead.
      • + IRBuilder. + +
    • MRegisterInfo was renamed to + + TargetRegisterInfo.
      • +
    • The MappedFile class is gone, please use + + MemoryBuffer instead.
    • The '-enable-eh' flag to llc has been removed. Now code should encode whether it is safe to omit unwind information for a function by tagging the Function object with the 'nounwind' attribute.
      • @@ -372,7 +377,8 @@ both pre-pass and post-pass scheduling, and to improve compiler-debugging output. -
    • The target-independent code generator infrastructure now uses LLVM's APInt +
    • The target-independent code generator infrastructure now uses LLVM's + APInt class to handle integer values, which allows it to support integer types larger than 64 bits. Note that support for such types is also dependent on target-specific support. Use of APInt is also a step toward support for From sabre at nondot.org Sun Jun 8 17:59:35 2008 From: sabre at nondot.org (Chris Lattner) Date: Sun, 08 Jun 2008 22:59:35 -0000 Subject: [llvm-commits] [llvm] r52107 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <200806082259.m58MxZ8K008495@zion.cs.uiuc.edu> Author: lattner Date: Sun Jun 8 17:59:35 2008 New Revision: 52107 URL: http://llvm.org/viewvc/llvm-project?rev=52107&view=rev Log: several edits Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=52107&r1=52106&r2=52107&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Sun Jun 8 17:59:35 2008 @@ -195,6 +195,14 @@ +
      + +

      LLVM 2.3 includes a huge number of bug fixes, performance tweaks and minor +improvements. Some of the major improvements and new features are listed in +this section. +

      +
      +
      Major New Features @@ -261,15 +269,20 @@
      -

      LLVM 2.3 fully supports the llvm-gcc 4.2 front-end.

      +

      LLVM 2.3 fully supports the llvm-gcc 4.2 front-end, and includes support +for the C, C++, Objective-C, Ada, and Fortran front-ends.

      -

      llvm-gcc 4.2 includes numerous fixes to better support the Objective-C -front-end. Objective-C now works very well on Mac OS/X.

      +

      +

        +
      • llvm-gcc 4.2 includes numerous fixes to better support the Objective-C +front-end. Objective-C now works very well on Mac OS/X.
        • -

        Fortran EQUIVALENCEs are now supported by the gfortran front-end.

        +
      • Fortran EQUIVALENCEs are now supported by the gfortran front-end.
        • -

        llvm-gcc 4.2 includes many other fixes which improve conformance with the -relevant parts of the GCC testsuite.

        +
      • llvm-gcc 4.2 includes many other fixes which improve conformance with the +relevant parts of the GCC testsuite.
        • + +

      @@ -283,16 +296,18 @@

      New features include:

      - -Common linkage? - -Atomic operation support, Alpha, X86, X86-64, PowerPC. "__sync_synchronize", -"__sync_val_compare_and_swap", etc -
        -
      • The C and Ocaml bindings have received additional improvements. The -bindings now cover pass managers, several transformation passes, iteration -over the LLVM IR, target data, and parameter attribute lists.
        • +
      • LLVM IR now directly represents "common" linkage, instead of representing it +as a form of weak linkage.
        • + +
      • LLVM IR now has support for atomic operations, and this functionality can +be accessed through the llvm-gcc "__sync_synchronize", +"__sync_val_compare_and_swap", and related builtins. Support for atomics are +available in the Alpha, X86, X86-64, and PowerPC backends.
        • + +
      • The C and Ocaml bindings have extended to cover pass managers, several +transformation passes, iteration over the LLVM IR, target data, and parameter +attribute lists.
      @@ -309,15 +324,18 @@
        -
      • Loop index set splitting on by default.

        -This transformation hoists conditions from loop bodies and reduces loop's -iteration space to improve performance. For example,

        +

      • Loop index set splitting on by default. +This transformation hoists conditions from loop bodies and reduces a loop's +iteration space to improve performance. For example,

        + 
         for (i = LB; i < UB; ++i)
   if (i <= NV)
     LOOP_BODY
        -is transformed into + +

        is transformed into:

        + 
         NUB = min(NV+1, UB)
 for (i = LB; i < NUB; ++i)
@@ -325,7 +343,7 @@
        • -
      • LLVM includes a new memcpy optimization pass which removes +
      • LLVM now includes a new memcpy optimization pass which removes dead memcpy calls, unneeded copies of aggregates, and performs return slot optimization. The LLVM optimizer now notices long sequences of consecutive stores and merges them into memcpy's where profitable.
        • @@ -333,14 +351,12 @@
      • Alignment detection for vector memory references and for memcpy and memset is now more aggressive.
        • -
      • The aggressive dead code elimination (ADCE) optimization has been rewritten +
      • The Aggressive Dead Code Elimination (ADCE) optimization has been rewritten to make it both faster and safer in the presence of code containing infinite loops. Some of its prior functionality has been factored out into the loop -deletion pass, which is safe for infinite loops.
        • +deletion pass, which is safe for infinite loops. The new ADCE pass is +no longer based on control dependence, making it run faster. -
      • Several optimizations have been sped up, leading to faster code generation - with the same code quality.
        • -
      • The 'SimplifyLibCalls' pass, which optimizes calls to libc and libm functions for C-based languages, has been rewritten to be a FunctionPass instead a ModulePass. This allows it to be run more often and to be @@ -354,6 +370,10 @@
      • Several corner case bugs which could lead to deleting volatile memory accesses have been fixed.
        • + +
      • Several optimizations have been sped up, leading to faster code generation + with the same code quality.
        • +
      From gohman at apple.com Sun Jun 8 18:05:12 2008 From: gohman at apple.com (Dan Gohman) Date: Sun, 08 Jun 2008 23:05:12 -0000 Subject: [llvm-commits] [llvm] r52108 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <200806082305.m58N5CuJ008761@zion.cs.uiuc.edu> Author: djg Date: Sun Jun 8 18:05:11 2008 New Revision: 52108 URL: http://llvm.org/viewvc/llvm-project?rev=52108&view=rev Log: Add notes about two known X86-64 limitations. Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=52108&r1=52107&r2=52108&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Sun Jun 8 18:05:11 2008 @@ -606,6 +606,11 @@ currently due to several bugs in FP stackifier +
    • The X86-64 backend does not yet support position-independent code (PIC) + generation on Linux targets.
      • +
    • The X86-64 backend does not yet support the LLVM IR instruction + va_arg. Currently, the llvm-gcc front-end supports variadic + argument constructs on X86-64 by lowering them manually.
    From sabre at nondot.org Sun Jun 8 18:06:47 2008 From: sabre at nondot.org (Chris Lattner) Date: Sun, 08 Jun 2008 23:06:47 -0000 Subject: [llvm-commits] [llvm] r52109 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <200806082306.m58N6lX0008812@zion.cs.uiuc.edu> Author: lattner Date: Sun Jun 8 18:06:47 2008 New Revision: 52109 URL: http://llvm.org/viewvc/llvm-project?rev=52109&view=rev Log: more edits Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=52109&r1=52108&r2=52109&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Sun Jun 8 18:06:47 2008 @@ -400,16 +400,17 @@
  • The target-independent code generator infrastructure now uses LLVM's APInt class to handle integer values, which allows it to support integer types - larger than 64 bits. Note that support for such types is also dependent on - target-specific support. Use of APInt is also a step toward support for - non-power-of-2 integer sizes.
    • + larger than 64 bits (for example i128). Note that support for such types is + also dependent on target-specific support. Use of APInt is also a step + toward support for non-power-of-2 integer sizes.
  • LLVM 2.3 includes several compile time speedups for code with large basic blocks, particularly in the instruction selection phase, register allocation, scheduling, and tail merging/jump threading.
    • -
  • Several improvements which make llc's --view-sunit-dags - visualization of scheduling dependency graphs easier to understand.
    • +
  • LLVM 2.3 includes several improvements which make llc's + --view-sunit-dags visualization of scheduling dependency graphs + easier to understand.
  • The code generator allows targets to write patterns that generate subreg references directly in .td files now.
    • @@ -447,7 +448,7 @@ now interoperates very well on X86-64 systems with other compilers.
  • Support for Win64 was added. This includes code generation itself, JIT - support and necessary changes to llvm-gcc.
    • + support, and necessary changes to llvm-gcc.
  • The LLVM X86 backend now supports the support SSE 4.1 instruction set, and the llvm-gcc 4.2 front-end supports the SSE 4.1 compiler builtins. Various @@ -458,10 +459,13 @@
  • The X86 backend now does a number of optimizations that aim to avoid converting numbers back and forth from SSE registers to the X87 floating - point stack.
    • + point stack. This is important because most X86 ABIs require return values + to be on the X87 Floating Point stack, but most CPUs prefer computation in + the SSE units.
  • The X86 backend supports stack realignment, which is particularly useful for - vector code on OS's without 16-byte aligned stacks.
    • + vector code on OS's without 16-byte aligned stacks, such as Linux and + Windows.
  • The X86 backend now supports the "sseregparm" options in GCC, which allow functions to be tagged as passing floating point values in SSE @@ -473,9 +477,11 @@
  • __builtin_prefetch is now compiled into the appropriate prefetch instructions instead of being ignored.
    • -
  • 128-bit integers are now supported on X86-64 targets.
    • +
  • 128-bit integers are now supported on X86-64 targets. This can be used + through __attribute__((TImode)) in llvm-gcc.
    • -
  • The register allocator can now rematerialize PIC-base computations.
    • +
  • The register allocator can now rematerialize PIC-base computations, which is + an important optimization for register use.
  • The "t" and "f" inline assembly constraints for the X87 floating point stack now work. However, the "u" constraint is still not fully supported.
    • @@ -495,6 +501,8 @@
    • The LLVM C backend now supports vector code.
      • +
    • The Cell SPU backend includes a number of improvements. It generates better + code and its stability/completeness is improving.
    From sabre at nondot.org Sun Jun 8 18:12:47 2008 From: sabre at nondot.org (Chris Lattner) Date: Sun, 08 Jun 2008 23:12:47 -0000 Subject: [llvm-commits] [llvm] r52110 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <200806082312.m58NCld1009001@zion.cs.uiuc.edu> Author: lattner Date: Sun Jun 8 18:12:47 2008 New Revision: 52110 URL: http://llvm.org/viewvc/llvm-project?rev=52110&view=rev Log: final edits from me, simplify the ia64 section. Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=52110&r1=52109&r2=52110&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Sun Jun 8 18:12:47 2008 @@ -613,7 +613,8 @@ expect small issues to happen. Also, llvm-gcc cannot build mingw64 runtime currently due to several - bugs in FP stackifier + bugs due to lack of support for the + 'u' inline assembly constraint and X87 floating point inline assembly.
  • The X86-64 backend does not yet support position-independent code (PIC) generation on Linux targets.
  • The X86-64 backend does not yet support the LLVM IR instruction @@ -694,25 +695,9 @@
      - -
    • C++ programs are likely to fail on IA64, as calls to setjmp are -made where the argument is not 16-byte aligned, as required on IA64. (Strictly -speaking this is not a bug in the IA64 back-end; it will also be encountered -when building C++ programs using the C back-end.)
      • - -
    • The C++ front-end does not use IA64 -ABI compliant layout of v-tables. In particular, it just stores function -pointers instead of function descriptors in the vtable. This bug prevents -mixing C++ code compiled with LLVM with C++ objects compiled by other C++ -compilers.
      • - -
    • There are a few ABI violations which will lead to problems when mixing LLVM -output with code built with other compilers, particularly for floating-point -programs.
      • - -
    • Defining vararg functions is not supported (but calling them is OK).
      • - -
    • The Itanium backend has bitrotted somewhat.
      • +
    • The Itanium backend is highly experimental, and has a number of known + issues. We are looking for a maintainer for the Itanium backend. If you + are interested, please contact the llvmdev mailing list.
    @@ -741,9 +726,6 @@ Known problems with the llvm-gcc C front-end - -
    Bugs
    -

    llvm-gcc does not currently support Link-Time From sabre at nondot.org Sun Jun 8 18:40:40 2008 From: sabre at nondot.org (Chris Lattner) Date: Sun, 08 Jun 2008 23:40:40 -0000 Subject: [llvm-commits] [llvm] r52111 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <200806082340.m58Neesh009753@zion.cs.uiuc.edu> Author: lattner Date: Sun Jun 8 18:40:40 2008 New Revision: 52111 URL: http://llvm.org/viewvc/llvm-project?rev=52111&view=rev Log: grammaro Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=52111&r1=52110&r2=52111&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Sun Jun 8 18:40:40 2008 @@ -183,7 +183,7 @@ transformations (such as refactoring) and other source-level tools for C and Objective-C. Clang now also includes tools for turning C code into pretty HTML, and includes a new static -analysis tool in development. This tool is automatically focused on finding +analysis tool in development. This tool focuses on automatically finding bugs in C and Objective-C code.

    From sabre at nondot.org Sun Jun 8 19:42:10 2008 From: sabre at nondot.org (Chris Lattner) Date: Mon, 09 Jun 2008 00:42:10 -0000 Subject: [llvm-commits] [llvm] r52112 - /llvm/trunk/include/llvm/ADT/ScopedHashTable.h Message-ID: <200806090042.m590gAjH011376@zion.cs.uiuc.edu> Author: lattner Date: Sun Jun 8 19:42:10 2008 New Revision: 52112 URL: http://llvm.org/viewvc/llvm-project?rev=52112&view=rev Log: Add a simple, but efficient, generic scoped hash table Added: llvm/trunk/include/llvm/ADT/ScopedHashTable.h Added: llvm/trunk/include/llvm/ADT/ScopedHashTable.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/ScopedHashTable.h?rev=52112&view=auto ============================================================================== --- llvm/trunk/include/llvm/ADT/ScopedHashTable.h (added) +++ llvm/trunk/include/llvm/ADT/ScopedHashTable.h Sun Jun 8 19:42:10 2008 @@ -0,0 +1,193 @@ +//===- ScopedHashTable.h - A simple scoped hash table ---------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file implements an efficient scoped hash table, which is useful for +// things like dominator-based optimizations. This allows clients to do things +// like this: +// +// ScopedHashTable HT; +// { +// ScopedHashTableScope Scope1(HT); +// HT.insert(0, 0); +// HT.insert(1, 1); +// { +// ScopedHashTableScope Scope2(HT); +// HT.insert(0, 42); +// } +// } +// +// Looking up the value for "0" in the Scope2 block will return 42. Looking +// up the value for 0 before 42 is inserted or after Scope2 is popped will +// return 0. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_ADT_SCOPEDHASHTABLE_H +#define LLVM_ADT_SCOPEDHASHTABLE_H + +#include +#include "llvm/ADT/DenseMap.h" + +namespace llvm { + +template +class ScopedHashTable; + +template +class ScopedHashTableVal { + ScopedHashTableVal *NextInScope; + ScopedHashTableVal *NextForKey; + K Key; + V Val; +public: + ScopedHashTableVal(ScopedHashTableVal *nextInScope, + ScopedHashTableVal *nextForKey, const K &key, const V &val) + : NextInScope(nextInScope), NextForKey(nextForKey), Key(key), Val(val) { + } + + const K &getKey() const { return Key; } + const V &getValue() const { return Val; } + V &getValue() { return Val; } + + ScopedHashTableVal *getNextForKey() { return NextForKey; } + const ScopedHashTableVal *getNextForKey() const { return NextForKey; } +public: + ScopedHashTableVal *getNextInScope() { return NextInScope; } +}; + +template +class ScopedHashTableScope { + /// HT - The hashtable that we are active for. + ScopedHashTable &HT; + + /// PrevScope - This is the scope that we are shadowing in HT. + ScopedHashTableScope *PrevScope; + + /// LastValInScope - This is the last value that was inserted for this scope + /// or null if none have been inserted yet. + ScopedHashTableVal *LastValInScope; + void operator=(ScopedHashTableScope&); // DO NOT IMPLEMENT + ScopedHashTableScope(ScopedHashTableScope&); // DO NOT IMPLEMENT +public: + ScopedHashTableScope(ScopedHashTable &HT); + ~ScopedHashTableScope(); + +private: + friend class ScopedHashTable; + ScopedHashTableVal *getLastValInScope() { return LastValInScope; } + void setLastValInScope(ScopedHashTableVal *Val) { LastValInScope = Val; } +}; + + +template +class ScopedHashTableIterator { + ScopedHashTableVal *Node; +public: + ScopedHashTableIterator(ScopedHashTableVal *node) : Node(node){} + + V &operator*() const { + assert(Node && "Dereference end()"); + return Node->getValue(); + } + V *operator->() const { + return &Node->getValue(); + } + + bool operator==(const ScopedHashTableIterator &RHS) const { + return Node == RHS.Node; + } + bool operator!=(const ScopedHashTableIterator &RHS) const { + return Node != RHS.Node; + } + + inline ScopedHashTableIterator& operator++() { // Preincrement + assert(Node && "incrementing past end()"); + Node = Node->getNextForKey(); + return *this; + } + ScopedHashTableIterator operator++(int) { // Postincrement + ScopedHashTableIterator tmp = *this; ++*this; return tmp; + } +}; + + +template +class ScopedHashTable { + DenseMap*> TopLevelMap; + ScopedHashTableScope *CurScope; + ScopedHashTable(const ScopedHashTable&); // NOT YET IMPLEMENTED + void operator=(const ScopedHashTable&); // NOT YET IMPLEMENTED + friend class ScopedHashTableScope; +public: + ScopedHashTable() : CurScope(0) {} + ~ScopedHashTable() { + assert(CurScope == 0 && TopLevelMap.empty() && "Scope imbalance!"); + } + + void insert(const K &Key, const V &Val) { + assert(CurScope && "No scope active!"); + + ScopedHashTableVal *&KeyEntry = TopLevelMap[Key]; + + KeyEntry = new ScopedHashTableVal(CurScope->getLastValInScope(), + KeyEntry, Key, Val); + CurScope->setLastValInScope(KeyEntry); + } + + typedef ScopedHashTableIterator iterator; + + iterator end() { return iterator(0); } + + iterator begin(const K &Key) { + typename DenseMap*>::iterator I = + TopLevelMap.find(Key); + if (I == TopLevelMap.end()) return end(); + return iterator(I->second); + } +}; + +/// ScopedHashTableScope ctor - Install this as the current scope for the hash +/// table. +template +ScopedHashTableScope::ScopedHashTableScope(ScopedHashTable &ht) + : HT(ht) { + PrevScope = HT.CurScope; + HT.CurScope = this; + LastValInScope = 0; +} + +template +ScopedHashTableScope::~ScopedHashTableScope() { + assert(HT.CurScope == this && "Scope imbalance!"); + HT.CurScope = PrevScope; + + // Pop and delete all values corresponding to this scope. + while (ScopedHashTableVal *ThisEntry = LastValInScope) { + // Pop this value out of the TopLevelMap. + if (ThisEntry->getNextForKey() == 0) { + assert(HT.TopLevelMap[ThisEntry->getKey()] == ThisEntry && + "Scope imbalance!"); + HT.TopLevelMap.erase(ThisEntry->getKey()); + } else { + ScopedHashTableVal *&KeyEntry = HT.TopLevelMap[ThisEntry->getKey()]; + assert(KeyEntry == ThisEntry && "Scope imbalance!"); + KeyEntry = ThisEntry->getNextForKey(); + } + + // Pop this value out of the scope. + LastValInScope = ThisEntry->getNextInScope(); + + // Delete this entry. + delete ThisEntry; + } +} + +} // end namespace llvm + +#endif From sabre at nondot.org Sun Jun 8 23:00:08 2008 From: sabre at nondot.org (Chris Lattner) Date: Mon, 09 Jun 2008 04:00:08 -0000 Subject: [llvm-commits] [llvm] r52114 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <200806090400.m594083r016684@zion.cs.uiuc.edu> Author: lattner Date: Sun Jun 8 23:00:08 2008 New Revision: 52114 URL: http://llvm.org/viewvc/llvm-project?rev=52114&view=rev Log: linkify, this requires pulling CodeGenerator.html into 2.3. Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=52114&r1=52113&r2=52114&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Sun Jun 8 23:00:08 2008 @@ -425,9 +425,10 @@ 'i' form when possible instead of always loading the value in a register. This saves an instruction and reduces register use.
    • -
  • Added support for PIC/GOT style tail calls on x86/32 and initial support - for tail calls on PowerPC 32 (it may also work on ppc64 but not - thoroughly tested).
    • +
  • Added support for PIC/GOT style tail calls on X86/32 and initial + support for tail calls on PowerPC 32 (it may also work on PowerPC 64 but is + not thoroughly tested).
    • From asl at math.spbu.ru Sun Jun 8 23:15:49 2008 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Mon, 09 Jun 2008 04:15:49 -0000 Subject: [llvm-commits] [llvm] r52115 - /llvm/trunk/docs/CompilerDriver.html Message-ID: <200806090415.m594Fomf017082@zion.cs.uiuc.edu> Author: asl Date: Sun Jun 8 23:15:49 2008 New Revision: 52115 URL: http://llvm.org/viewvc/llvm-project?rev=52115&view=rev Log: Remove obsolete CompilerDriver.html and provie a new one, based on autogenerated file form LLVMC-Reference.rst Modified: llvm/trunk/docs/CompilerDriver.html Modified: llvm/trunk/docs/CompilerDriver.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CompilerDriver.html?rev=52115&r1=52114&r2=52115&view=diff ============================================================================== --- llvm/trunk/docs/CompilerDriver.html (original) +++ llvm/trunk/docs/CompilerDriver.html Sun Jun 8 23:15:49 2008 @@ -1,823 +1,411 @@ - - + + + - - The LLVM Compiler Driver (llvmc) - - - + + +Customizing LLVMC: Reference Manual + -
    The LLVM Compiler Driver (llvmc)
    -

    NOTE: This document is a work in progress!

    -
      -
    1. Abstract
      2. -
    2. Introduction -
        -
      1. Purpose
        2. -
      2. Operation
        3. -
      3. Phases
        4. -
      4. Actions
        5. -
      -
      3. -
    3. Configuration -
        -
      1. Overview
        2. -
      2. Configuration Files
        3. -
      3. Syntax
        4. -
      4. Substitutions
        5. -
      5. Sample Config File
        6. -
      -
    4. Glossary -
    -
    -

    Written by Reid Spencer -

    -
    - - -
    Abstract
    - -
    -

    This document describes the requirements, design, and configuration of the - LLVM compiler driver, llvmc. The compiler driver knows about LLVM's - tool set and can be configured to know about a variety of compilers for - source languages. It uses this knowledge to execute the tools necessary - to accomplish general compilation, optimization, and linking tasks. The main - purpose of llvmc is to provide a simple and consistent interface to - all compilation tasks. This reduces the burden on the end user who can just - learn to use llvmc instead of the entire LLVM tool set and all the - source language compilers compatible with LLVM.

    -
    - -
    Introduction
    - -
    -

    The llvmc tool is a configurable compiler - driver. As such, it isn't a compiler, optimizer, - or a linker itself but it drives (invokes) other software that perform those - tasks. If you are familiar with the GNU Compiler Collection's gcc - tool, llvmc is very similar.

    -

    The following introductory sections will help you understand why this tool - is necessary and what it does.

    -
    - - -
    Purpose
    -
    -

    llvmc was invented to make compilation of user programs with - LLVM-based tools easier. To accomplish this, llvmc strives to:

    -
      -
    • Be the single point of access to most of the LLVM tool set.
      • -
    • Hide the complexities of the LLVM tools through a single interface.
      • -
    • Provide a consistent interface for compiling all languages.
      • -
    -

    Additionally, llvmc makes it easier to write a compiler for use - with LLVM, because it:

    -
      -
    • Makes integration of existing non-LLVM tools simple.
      • -
    • Extends the capabilities of minimal compiler tools by optimizing their - output.
      • -
    • Reduces the number of interfaces a compiler writer must know about - before a working compiler can be completed (essentially only the VMCore - interfaces need to be understood).
      • -
    • Supports source language translator invocation via both dynamically - loadable shared objects and invocation of an executable.
      • -
    -
    - - -
    Operation
    -
    -

    At a high level, llvmc operation is very simple. The basic action - taken by llvmc is to simply invoke some tool or set of tools to fill - the user's request for compilation. Every execution of llvmctakes the - following sequence of steps:

    -
    -
    Collect Command Line Options
    -
    The command line options provide the marching orders to llvmc - on what actions it should perform. This is the request the user is making - of llvmc and it is interpreted first. See the llvmc - manual page for details on the - options.
    -
    Read Configuration Files
    -
    Based on the options and the suffixes of the filenames presented, a set - of configuration files are read to configure the actions llvmc will - take. Configuration files are provided by either LLVM or the - compiler tools that llvmc invokes. These files determine what - actions llvmc will take in response to the user's request. See - the section on configuration for more details. -
    -
    Determine Phases To Execute
    -
    Based on the command line options and configuration files, - llvmc determines the compilation phases that - must be executed by the user's request. This is the primary work of - llvmc.
    -
    Determine Actions To Execute
    -
    Each phase to be executed can result in the - invocation of one or more actions. An action is - either a whole program or a function in a dynamically linked shared library. - In this step, llvmc determines the sequence of actions that must be - executed. Actions will always be executed in a deterministic order.
    -
    Execute Actions
    -
    The actions necessary to support the user's - original request are executed sequentially and deterministically. All - actions result in either the invocation of a whole program to perform the - action or the loading of a dynamically linkable shared library and invocation - of a standard interface function within that library.
    -
    Termination
    -
    If any action fails (returns a non-zero result code), llvmc - also fails and returns the result code from the failing action. If - everything succeeds, llvmc will return a zero result code.
    -
    -

    llvmc's operation must be simple, regular and predictable. - Developers need to be able to rely on it to take a consistent approach to - compilation. For example, the invocation:

    - - llvmc -O2 x.c y.c z.c -o xyz -

    must produce exactly the same results as:

    - 
    
-    llvmc -O2 x.c -o x.o
-    llvmc -O2 y.c -o y.o
-    llvmc -O2 z.c -o z.o
-    llvmc -O2 x.o y.o z.o -o xyz
    -

    To accomplish this, llvmc uses a very simple goal oriented - procedure to do its work. The overall goal is to produce a functioning - executable. To accomplish this, llvmc always attempts to execute a - series of compilation phases in the same sequence. - However, the user's options to llvmc can cause the sequence of phases - to start in the middle or finish early.

    -
    - - -
    Phases
    -
    -

    llvmc breaks every compilation task into the following five - distinct phases:

    -
    Preprocessing
    Not all languages support preprocessing; - but for those that do, this phase can be invoked. This phase is for - languages that provide combining, filtering, or otherwise altering with the - source language input before the translator parses it. Although C and C++ - are the most common users of this phase, other languages may provide their - own preprocessor (whether its the C pre-processor or not).
    -
    -
    Translation
    The translation phase converts the source - language input into something that LLVM can interpret and use for - downstream phases. The translation is essentially from "non-LLVM form" to - "LLVM form".
    -
    -
    Optimization
    Once an LLVM Module has been obtained from - the translation phase, the program enters the optimization phase. This phase - attempts to optimize all of the input provided on the command line according - to the options provided.
    -
    -
    Linking
    The inputs are combined to form a complete - program.
    -
    -

    The following table shows the inputs, outputs, and command line options - applicable to each phase.

    - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
    PhaseInputsOutputsOptions
    Preprocessing
    • Source Language File
    • Source Language File
    -
    -E
    -
    Stops the compilation after preprocessing
    -
    Translation
      -
    • Source Language File
      • -
      -
    • LLVM Assembly
      • -
    • LLVM Bitcode
      • -
    • LLVM C++ IR
      • -
    -
    -c
    -
    Stops the compilation after translation so that optimization and - linking are not done.
    -
    -S
    -
    Stops the compilation before object code is written so that only - assembly code remains.
    -
    Optimization
      -
    • LLVM Assembly
      • -
    • LLVM Bitcode
      • -
      -
    • LLVM Bitcode
      • -
    -
    -Ox -
    This group of options controls the amount of optimization - performed.
    -
    Linking
      -
    • LLVM Bitcode
      • -
    • Native Object Code
      • -
    • LLVM Library
      • -
    • Native Library
      • -
      -
    • LLVM Bitcode Executable
      • -
    • Native Executable
      • -
    -
    -L
    Specifies a path for library search.
    -
    -l
    Specifies a library to link in.
    -
    -
    - - -
    Actions
    -
    -

    An action, with regard to llvmc is a basic operation that it takes - in order to fulfill the user's request. Each phase of compilation will invoke - zero or more actions in order to accomplish that phase.

    -

    Actions come in two forms:

    -
      -
    • Invokable Executables
      • -
    • Functions in a shared library
      • -
    -
    - - -
    Configuration
    - -
    -

    This section of the document describes the configuration files used by - llvmc. Configuration information is relatively static for a - given release of LLVM and a compiler tool. However, the details may - change from release to release of either. Users are encouraged to simply use - the various options of the llvmc command and ignore the configuration - of the tool. These configuration files are for compiler writers and LLVM - developers. Those wishing to simply use llvmc don't need to understand - this section but it may be instructive on how the tool works.

    -
    - - -
    Overview
    -
    -

    llvmc is highly configurable both on the command line and in -configuration files. The options it understands are generic, consistent and -simple by design. Furthermore, the llvmc options apply to the -compilation of any LLVM enabled programming language. To be enabled as a -supported source language compiler, a compiler writer must provide a -configuration file that tells llvmc how to invoke the compiler -and what its capabilities are. The purpose of the configuration files then -is to allow compiler writers to specify to llvmc how the compiler -should be invoked. Users may but are not advised to alter the compiler's -llvmc configuration.

    - -

    Because llvmc just invokes other programs, it must deal with the -available command line options for those programs regardless of whether they -were written for LLVM or not. Furthermore, not all compiler tools will -have the same capabilities. Some compiler tools will simply generate LLVM assembly -code, others will be able to generate fully optimized bitcode. In general, -llvmc doesn't make any assumptions about the capabilities or command -line options of a sub-tool. It simply uses the details found in the -configuration files and leaves it to the compiler writer to specify the -configuration correctly.

    - -

    This approach means that new compiler tools can be up and working very -quickly. As a first cut, a tool can simply compile its source to raw -(unoptimized) bitcode or LLVM assembly and llvmc can be configured -to pick up the slack (translate LLVM assembly to bitcode, optimize the -bitcode, generate native assembly, link, etc.). In fact, the compiler tools -need not use any LLVM libraries, and it could be written in any language -(instead of C++). The configuration data will allow the full range of -optimization, assembly, and linking capabilities that LLVM provides to be added -to these kinds of tools. Enabling the rapid development of front-ends is one -of the primary goals of llvmc.

    - -

    As a compiler tool matures, it may utilize the LLVM libraries and tools -to more efficiently produce optimized bitcode directly in a single compilation -and optimization program. In these cases, multiple tools would not be needed -and the configuration data for the compiler would change.

    - -

    Configuring llvmc to the needs and capabilities of a source language -compiler is relatively straight-forward. A compiler writer must provide a -definition of what to do for each of the five compilation phases for each of -the optimization levels. The specification consists simply of prototypical -command lines into which llvmc can substitute command line -arguments and file names. Note that any given phase can be completely blank if -the source language's compiler combines multiple phases into a single program. -For example, quite often pre-processing, translation, and optimization are -combined into a single program. The specification for such a compiler would have -blank entries for pre-processing and translation but a full command line for -optimization.

    -
    - - -
    Configuration Files
    -
    File Contents
    -
    -

    Each configuration file provides the details for a single source language - that is to be compiled. This configuration information tells llvmc - how to invoke the language's pre-processor, translator, optimizer, assembler - and linker. Note that a given source language needn't provide all these tools - as many of them exist in llvm currently.

    -
    - - -
    Directory Search
    -
    -

    llvmc always looks for files of a specific name. It uses the - first file with the name its looking for by searching directories in the - following order:
    -

      -
    1. Any directory specified by the -config-dir option will be - checked first.
      2. -
    2. If the environment variable LLVM_CONFIG_DIR is set, and it contains - the name of a valid directory, that directory will be searched next.
      3. -
    3. If the user's home directory (typically /home/user contains - a sub-directory named .llvm and that directory contains a - sub-directory named etc then that directory will be tried - next.
      4. -
    4. If the LLVM installation directory (typically /usr/local/llvm - contains a sub-directory named etc then that directory will be - tried last.
      5. -
    5. A standard "system" directory will be searched next. This is typically - /etc/llvm on UNIX™ and C:\WINNT on Microsoft - Windows™.
      6. -
    6. If the configuration file sought still can't be found, llvmc - will print an error message and exit.
      7. -
    -

    The first file found in this search will be used. Other files with the - same name will be ignored even if they exist in one of the subsequent search - locations.

    -
    - -
    File Names
    -
    -

    In the directories searched, each configuration file is given a specific - name to foster faster lookup (so llvmc doesn't have to do directory searches). - The name of a given language specific configuration file is simply the same - as the suffix used to identify files containing source in that language. - For example, a configuration file for C++ source might be named - cpp, C, or cxx. For languages that support multiple - file suffixes, multiple (probably identical) files (or symbolic links) will - need to be provided.

    -
    +
    -
    What Gets Read
    -
    -

    Which configuration files are read depends on the command line options and - the suffixes of the file names provided on llvmc's command line. Note - that the -x LANGUAGE option alters the language that llvmc - uses for the subsequent files on the command line. Only the configuration - files actually needed to complete llvmc's task are read. Other - language specific files will be ignored.

    -
    +
    Customizing LLVMC: Reference Manual
    - -
    Syntax
    -
    -

    The syntax of the configuration files is very simple and somewhat - compatible with Java's property files. Here are the syntax rules:

    -
      -
    • The file encoding is ASCII.
      • -
    • The file is line oriented. There should be one configuration definition - per line. Lines are terminated by the newline (0x0A) and/or carriage return - characters (0x0D)
      • -
    • A backslash (\) before a newline causes the newline to be - ignored. This is useful for line continuation of long definitions. A - backslash anywhere else is recognized as a backslash.
      • -
    • A configuration item consists of a name, an = and a value.
      • -
    • A name consists of a sequence of identifiers separated by period.
      • -
    • An identifier consists of specific keywords made up of only lower case - and upper case letters (e.g. lang.name).
      • -
    • Values come in four flavors: booleans, integers, commands and - strings.
      • -
    • Valid "false" boolean values are false False FALSE no No NO - off Off and OFF.
      • -
    • Valid "true" boolean values are true True TRUE yes Yes YES - on On and ON.
      • -
    • Integers are simply sequences of digits.
      • -
    • Commands start with a program name and are followed by a sequence of - words that are passed to that program as command line arguments. Program - arguments that begin and end with the % sign will have their value - substituted. Program names beginning with / are considered to be - absolute. Otherwise the PATH will be applied to find the program to - execute.
      • -
    • Strings are composed of multiple sequences of characters from the - character class [-A-Za-z0-9_:%+/\\|,] separated by white - space.
      • -
    • White space on a line is folded. Multiple blanks or tabs will be - reduced to a single blank.
      • -
    • White space before the configuration item's name is ignored.
      • -
    • White space on either side of the = is ignored.
      • -
    • White space in a string value is used to separate the individual - components of the string value but otherwise ignored.
      • -
    • Comments are introduced by the # character. Everything after a - # and before the end of line is ignored.
      • -
    +
    +

    Note: This document is a work-in-progress. Additions and clarifications + are welcome.

    +
    + +

    LLVMC is a generic compiler driver, designed to be customizable and +extensible. It plays the same role for LLVM as the gcc program +does for GCC - LLVMC's job is essentially to transform a set of input +files into a set of targets depending on configuration rules and user +options. What makes LLVMC different is that these transformation rules +are completely customizable - in fact, LLVMC knows nothing about the +specifics of transformation (even the command-line options are mostly +not hard-coded) and regards the transformation structure as an +abstract graph. This makes it possible to adapt LLVMC for other +purposes - for example, as a build tool for game resources.

    +

    Because LLVMC employs TableGen [1] as its configuration language, you +need to be familiar with it to customize LLVMC.

    +
    + +
    + +
    Written by Mikhail Glushenkov
    + +
    +
    Compiling with LLVMC
    +

    LLVMC tries hard to be as compatible with gcc as possible, +although there are some small differences. Most of the time, however, +you shouldn't be able to notice them:

    +
    +$ # This works as expected:
+$ llvmc2 -O3 -Wall hello.cpp
+$ ./a.out
+hello
+
    +

    One nice feature of LLVMC is that one doesn't have to distinguish +between different compilers for different languages (think g++ and +gcc) - the right toolchain is chosen automatically based on input +language names (which are, in turn, determined from file +extensions). If you want to force files ending with ".c" to compile as +C++, use the -x option, just like you would do it with gcc:

    +
    +$ llvmc2 -x c hello.cpp
+$ # hello.cpp is really a C file
+$ ./a.out
+hello
+
    +

    On the other hand, when using LLVMC as a linker to combine several C++ +object files you should provide the --linker option since it's +impossible for LLVMC to choose the right linker in that case:

    +
    +$ llvmc2 -c hello.cpp
+$ llvmc2 hello.o
+[A lot of link-time errors skipped]
+$ llvmc2 --linker=c++ hello.o
+$ ./a.out
+hello
+
    +
    +
    +
    Predefined options
    +

    LLVMC has some built-in options that can't be overridden in the +configuration files:

    +
      +
    • -o FILE - Output file name.
      • +
    • -x LANGUAGE - Specify the language of the following input files +until the next -x option.
      • +
    • -v - Enable verbose mode, i.e. print out all executed commands.
      • +
    • --view-graph - Show a graphical representation of the compilation +graph. Requires that you have dot and gv commands +installed. Hidden option, useful for debugging.
      • +
    • --write-graph - Write a compilation-graph.dot file in the +current directory with the compilation graph description in the +Graphviz format. Hidden option, useful for debugging.
      • +
    • --save-temps - Write temporary files to the current directory +and do not delete them on exit. Hidden option, useful for debugging.
      • +
    • --help, --help-hidden, --version - These options have +their standard meaning.
      • +
    +
    +
    +
    Customizing LLVMC: the compilation graph
    +

    At the time of writing LLVMC does not support on-the-fly reloading of +configuration, so to customize LLVMC you'll have to recompile the +source code (which lives under $LLVM_DIR/tools/llvmc2). The +default configuration files are Common.td (contains common +definitions, don't forget to include it in your configuration +files), Tools.td (tool descriptions) and Graph.td (compilation +graph definition).

    +

    To compile LLVMC with your own configuration file (say,``MyGraph.td``), +run make like this:

    +
    +$ cd $LLVM_DIR/tools/llvmc2
+$ make GRAPH=MyGraph.td TOOLNAME=my_llvmc
+
    +

    This will build an executable named my_llvmc. There are also +several sample configuration files in the llvmc2/examples +subdirectory that should help to get you started.

    +

    Internally, LLVMC stores information about possible source +transformations in form of a graph. Nodes in this graph represent +tools, and edges between two nodes represent a transformation path. A +special "root" node is used to mark entry points for the +transformations. LLVMC also assigns a weight to each edge (more on +this later) to choose between several alternative edges.

    +

    The definition of the compilation graph (see file Graph.td) is +just a list of edges:

    +
    +def CompilationGraph : CompilationGraph<[
+    Edge<root, llvm_gcc_c>,
+    Edge<root, llvm_gcc_assembler>,
+    ...
+
+    Edge<llvm_gcc_c, llc>,
+    Edge<llvm_gcc_cpp, llc>,
+    ...
+
+    OptionalEdge<llvm_gcc_c, opt, [(switch_on "opt")]>,
+    OptionalEdge<llvm_gcc_cpp, opt, [(switch_on "opt")]>,
+    ...
+
+    OptionalEdge<llvm_gcc_assembler, llvm_gcc_cpp_linker,
+        (case (input_languages_contain "c++"), (inc_weight),
+              (or (parameter_equals "linker", "g++"),
+                  (parameter_equals "linker", "c++")), (inc_weight))>,
+    ...
+
+    ]>;
+
    +

    As you can see, the edges can be either default or optional, where +optional edges are differentiated by sporting a case expression +used to calculate the edge's weight.

    +

    The default edges are assigned a weight of 1, and optional edges get a +weight of 0 + 2*N where N is the number of tests that evaluated to +true in the case expression. It is also possible to provide an +integer parameter to inc_weight and dec_weight - in this case, +the weight is increased (or decreased) by the provided value instead +of the default 2.

    +

    When passing an input file through the graph, LLVMC picks the edge +with the maximum weight. To avoid ambiguity, there should be only one +default edge between two nodes (with the exception of the root node, +which gets a special treatment - there you are allowed to specify one +default edge per language).

    +

    To get a visual representation of the compilation graph (useful for +debugging), run llvmc2 --view-graph. You will need dot and +gsview installed for this to work properly.

    +
    +
    +
    Writing a tool description
    +

    As was said earlier, nodes in the compilation graph represent tools, +which are described separately. A tool definition looks like this +(taken from the Tools.td file):

    +
    +def llvm_gcc_cpp : Tool<[
+    (in_language "c++"),
+    (out_language "llvm-assembler"),
+    (output_suffix "bc"),
+    (cmd_line "llvm-g++ -c $INFILE -o $OUTFILE -emit-llvm"),
+    (sink)
+    ]>;
+
    +

    This defines a new tool called llvm_gcc_cpp, which is an alias for +llvm-g++. As you can see, a tool definition is just a list of +properties; most of them should be self-explanatory. The sink +property means that this tool should be passed all command-line +options that lack explicit descriptions.

    +

    The complete list of the currently implemented tool properties follows:

    +
      +
    • Possible tool properties:
        +
      • in_language - input language name.
        • +
      • out_language - output language name.
        • +
      • output_suffix - output file suffix.
        • +
      • cmd_line - the actual command used to run the tool. You can +use $INFILE and $OUTFILE variables, output redirection +with >, hook invocations ($CALL), environment variables +(via $ENV) and the case construct (more on this below).
        • +
      • join - this tool is a "join node" in the graph, i.e. it gets a +list of input files and joins them together. Used for linkers.
        • +
      • sink - all command-line options that are not handled by other +tools are passed to this tool.
        • +
      +
      • +
    +

    The next tool definition is slightly more complex:

    +
    +def llvm_gcc_linker : Tool<[
+    (in_language "object-code"),
+    (out_language "executable"),
+    (output_suffix "out"),
+    (cmd_line "llvm-gcc $INFILE -o $OUTFILE"),
+    (join),
+    (prefix_list_option "L", (forward),
+                        (help "add a directory to link path")),
+    (prefix_list_option "l", (forward),
+                        (help "search a library when linking")),
+    (prefix_list_option "Wl", (unpack_values),
+                        (help "pass options to linker"))
+    ]>;
+
    +

    This tool has a "join" property, which means that it behaves like a +linker. This tool also defines several command-line options: -l, +-L and -Wl which have their usual meaning. An option has two +attributes: a name and a (possibly empty) list of properties. All +currently implemented option types and properties are described below:

    +
      +

    • Possible option types:

      +
      +
        +
      • switch_option - a simple boolean switch, for example -time.
        • +
      • parameter_option - option that takes an argument, for example +-std=c99;
        • +
      • parameter_list_option - same as the above, but more than one +occurence of the option is allowed.
        • +
      • prefix_option - same as the parameter_option, but the option name +and parameter value are not separated.
        • +
      • prefix_list_option - same as the above, but more than one +occurence of the option is allowed; example: -lm -lpthread.
        • +
      • alias_option - a special option type for creating +aliases. Unlike other option types, aliases are not allowed to +have any properties besides the aliased option name. Usage +example: (alias_option "preprocess", "E")
        • +
      +
      +
      • +

    • Possible option properties:

      +
      +
        +
      • append_cmd - append a string to the tool invocation command.
        • +
      • forward - forward this option unchanged.
        • +
      • output_suffix - modify the output suffix of this +tool. Example : (switch "E", (output_suffix "i").
        • +
      • stop_compilation - stop compilation after this phase.
        • +
      • unpack_values - used for for splitting and forwarding +comma-separated lists of options, e.g. -Wa,-foo=bar,-baz is +converted to -foo=bar -baz and appended to the tool invocation +command.
        • +
      • help - help string associated with this option. Used for +--help output.
        • +
      • required - this option is obligatory.
        • +
      +
      +
      • +
    +
    +
    +
    Option list - specifying all options in a single place
    +

    It can be handy to have all information about options gathered in a +single place to provide an overview. This can be achieved by using a +so-called OptionList:

    +
    +def Options : OptionList<[
+(switch_option "E", (help "Help string")),
+(alias_option "quiet", "q")
+...
+]>;
+
    +

    OptionList is also a good place to specify option aliases.

    +

    Tool-specific option properties like append_cmd have (obviously) +no meaning in the context of OptionList, so the only properties +allowed there are help and required.

    +

    Option lists are used at the file scope. See file +examples/Clang.td for an example of OptionList usage.

    +
    +
    +
    Using hooks and environment variables in the cmd_line property
    +

    Normally, LLVMC executes programs from the system PATH. Sometimes, +this is not sufficient: for example, we may want to specify tool names +in the configuration file. This can be achieved via the mechanism of +hooks - to compile LLVMC with your hooks, just drop a .cpp file into +tools/llvmc2 directory. Hooks should live in the hooks +namespace and have the signature std::string hooks::MyHookName +(void). They can be used from the cmd_line tool property:

    +
    +(cmd_line "$CALL(MyHook)/path/to/file -o $CALL(AnotherHook)")
+
    +

    It is also possible to use environment variables in the same manner:

    +
    +(cmd_line "$ENV(VAR1)/path/to/file -o $ENV(VAR2)")
+
    +

    To change the command line string based on user-provided options use +the case expression (documented below):

    +
    +(cmd_line
+  (case
+    (switch_on "E"),
+       "llvm-g++ -E -x c $INFILE -o $OUTFILE",
+    (default),
+       "llvm-g++ -c -x c $INFILE -o $OUTFILE -emit-llvm"))
+
    +
    +
    +
    Conditional evaluation: the case expression
    +

    The 'case' construct can be used to calculate weights of the optional +edges and to choose between several alternative command line strings +in the cmd_line tool property. It is designed after the +similarly-named construct in functional languages and takes the form +(case (test_1), statement_1, (test_2), statement_2, ... (test_N), +statement_N). The statements are evaluated only if the corresponding +tests evaluate to true.

    +

    Examples:

    +
    +// Increases edge weight by 5 if "-A" is provided on the
+// command-line, and by 5 more if "-B" is also provided.
+(case
+    (switch_on "A"), (inc_weight 5),
+    (switch_on "B"), (inc_weight 5))
+
+// Evaluates to "cmdline1" if option "-A" is provided on the
+// command line, otherwise to "cmdline2"
+(case
+    (switch_on "A"), "cmdline1",
+    (switch_on "B"), "cmdline2",
+    (default), "cmdline3")
+
    +

    Note the slight difference in 'case' expression handling in contexts +of edge weights and command line specification - in the second example +the value of the "B" switch is never checked when switch "A" is +enabled, and the whole expression always evaluates to "cmdline1" in +that case.

    +

    Case expressions can also be nested, i.e. the following is legal:

    +
    +(case (switch_on "E"), (case (switch_on "o"), ..., (default), ...)
+      (default), ...)
+
    +

    You should, however, try to avoid doing that because it hurts +readability. It is usually better to split tool descriptions and/or +use TableGen inheritance instead.

    +
      +
    • Possible tests are:
        +
      • switch_on - Returns true if a given command-line option is +provided by the user. Example: (switch_on "opt"). Note that +you have to define all possible command-line options separately in +the tool descriptions. See the next doc_text for the discussion of +different kinds of command-line options.
        • +
      • parameter_equals - Returns true if a command-line parameter equals +a given value. Example: (parameter_equals "W", "all").
        • +
      • element_in_list - Returns true if a command-line parameter list +includes a given value. Example: (parameter_in_list "l", "pthread").
        • +
      • input_languages_contain - Returns true if a given language +belongs to the current input language set. Example: +`(input_languages_contain "c++").
        • +
      • in_language - Evaluates to true if the language of the input +file equals to the argument. Valid only when using case +expression in a cmd_line tool property. Example: +`(in_language "c++").
        • +
      • not_empty - Returns true if a given option (which should be +either a parameter or a parameter list) is set by the +user. Example: `(not_empty "o").
        • +
      • default - Always evaluates to true. Should always be the last +test in the case expression.
        • +
      • and - A standard logical combinator that returns true iff all +of its arguments return true. Used like this: (and (test1), +(test2), ... (testN)). Nesting of and and or is allowed, +but not encouraged.
        • +
      • or - Another logical combinator that returns true only if any +one of its arguments returns true. Example: (or (test1), +(test2), ... (testN)).
        • +
      +
      • +
    +
    +
    +
    Language map
    +

    One last thing that you will need to modify when adding support for a +new language to LLVMC is the language map, which defines mappings from +file extensions to language names. It is used to choose the proper +toolchain(s) for a given input file set. Language map definition is +located in the file Tools.td and looks like this:

    +
    +def LanguageMap : LanguageMap<
+    [LangToSuffixes<"c++", ["cc", "cp", "cxx", "cpp", "CPP", "c++", "C"]>,
+     LangToSuffixes<"c", ["c"]>,
+     ...
+    ]>;
+
    +
    +
    +
    References
    + + + + + +
    [1]TableGen Fundamentals +http://llvm.cs.uiuc.edu/docs/TableGenFundamentals.html
    - - -
    Configuration Items
    -
    -

    The table below provides definitions of the allowed configuration items - that may appear in a configuration file. Every item has a default value and - does not need to appear in the configuration file. Missing items will have the - default value. Each identifier may appear as all lower case, first letter - capitalized or all upper case.

    - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
    NameValue TypeDescriptionDefault

    LLVMC ITEMS

    versionstringProvides the version string for the contents of this - configuration file. What is accepted as a legal configuration file - will change over time and this item tells llvmc which version - should be expected.b

    LANG ITEMS

    lang.namestringProvides the common name for a language definition. - For example "C++", "Pascal", "FORTRAN", etc.blank
    lang.opt1stringSpecifies the parameters to give the optimizer when - -O1 is specified on the llvmc command line.-simplifycfg -instcombine -mem2reg
    lang.opt2stringSpecifies the parameters to give the optimizer when - -O2 is specified on the llvmc command line.TBD
    lang.opt3stringSpecifies the parameters to give the optimizer when - -O3 is specified on the llvmc command line.TBD
    lang.opt4stringSpecifies the parameters to give the optimizer when - -O4 is specified on the llvmc command line.TBD
    lang.opt5stringSpecifies the parameters to give the optimizer when - -O5 is specified on the llvmc command line.TBD

    PREPROCESSOR ITEMS

    preprocessor.commandcommandThis provides the command prototype that will be used - to run the preprocessor. This is generally only used with the - -E option.<blank>
    preprocessor.requiredbooleanThis item specifies whether the pre-processing phase - is required by the language. If the value is true, then the - preprocessor.command value must not be blank. With this option, - llvmc will always run the preprocessor as it assumes that the - translation and optimization phases don't know how to pre-process their - input.false

    TRANSLATOR ITEMS

    translator.commandcommandThis provides the command prototype that will be used - to run the translator. Valid substitutions are %in% for the - input file and %out% for the output file.<blank>
    translator.outputbitcode or assemblyThis item specifies the kind of output the language's - translator generates.bitcode
    translator.preprocessesbooleanIndicates that the translator also preprocesses. If - this is true, then llvmc will skip the pre-processing phase - whenever the final phase is not pre-processing.false

    OPTIMIZER ITEMS

    optimizer.commandcommandThis provides the command prototype that will be used - to run the optimizer. Valid substitutions are %in% for the - input file and %out% for the output file.<blank>
    optimizer.outputbitcode or assemblyThis item specifies the kind of output the language's - optimizer generates. Valid values are "assembly" and "bitcode"bitcode
    optimizer.preprocessesbooleanIndicates that the optimizer also preprocesses. If - this is true, then llvmc will skip the pre-processing phase - whenever the final phase is optimization or later.false
    optimizer.translatesbooleanIndicates that the optimizer also translates. If - this is true, then llvmc will skip the translation phase - whenever the final phase is optimization or later.false

    ASSEMBLER ITEMS

    assembler.commandcommandThis provides the command prototype that will be used - to run the assembler. Valid substitutions are %in% for the - input file and %out% for the output file.<blank>
    -
    - - -
    Substitutions
    -
    -

    On any configuration item that ends in command, you must - specify substitution tokens. Substitution tokens begin and end with a percent - sign (%) and are replaced by the corresponding text. Any substitution - token may be given on any command line but some are more useful than - others. In particular each command should have both an %in% - and an %out% substitution. The table below provides definitions of - each of the allowed substitution tokens.

    - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
    Substitution TokenReplacement Description
    %args%Replaced with all the tool-specific arguments given - to llvmc via the -T set of options. This just allows - you to place these arguments in the correct place on the command line. - If the %args% option does not appear on your command line, - then you are explicitly disallowing the -T option for your - tool. -
    %force%Replaced with the -f option if it was - specified on the llvmc command line. This is intended to tell - the compiler tool to force the overwrite of output files. -
    %in%Replaced with the full path of the input file. You - needn't worry about the cascading of file names. llvmc will - create temporary files and ensure that the output of one phase is the - input to the next phase.
    %opt%Replaced with the optimization options for the - tool. If the tool understands the -O options then that will - be passed. Otherwise, the lang.optN series of configuration - items will specify which arguments are to be given.
    %out%Replaced with the full path of the output file. - Note that this is not necessarily the output file specified with the - -o option on llvmc's command line. It might be a - temporary file that will be passed to a subsequent phase's input. -
    %stats%If your command accepts the -stats option, - use this substitution token. If the user requested -stats - from the llvmc command line then this token will be replaced - with -stats, otherwise it will be ignored. -
    %target%Replaced with the name of the target "machine" for - which code should be generated. The value used here is taken from the - llvmc option -march. -
    %time%If your command accepts the -time-passes - option, use this substitution token. If the user requested - -time-passes from the llvmc command line then this - token will be replaced with -time-passes, otherwise it will - be ignored. -
    - - -
    Sample Config File
    -
    -

    Since an example is always instructive, here's how the Stacker language - configuration file looks.

    - 
    
-# Stacker Configuration File For llvmc
-
-##########################################################
-# Language definitions
-##########################################################
-  lang.name=Stacker 
-  lang.opt1=-simplifycfg -instcombine -mem2reg
-  lang.opt2=-simplifycfg -instcombine -mem2reg -load-vn \
-    -gcse -dse -scalarrepl -sccp 
-  lang.opt3=-simplifycfg -instcombine -mem2reg -load-vn \
-    -gcse -dse -scalarrepl -sccp -branch-combine -adce \
-    -globaldce -inline -licm 
-  lang.opt4=-simplifycfg -instcombine -mem2reg -load-vn \
-    -gcse -dse -scalarrepl -sccp -ipconstprop \
-    -branch-combine -adce -globaldce -inline -licm 
-  lang.opt5=-simplifycfg -instcombine -mem2reg --load-vn \
-    -gcse -dse scalarrepl -sccp -ipconstprop \
-    -branch-combine -adce -globaldce -inline -licm \
-    -block-placement
-
-##########################################################
-# Pre-processor definitions
-##########################################################
-
-  # Stacker doesn't have a preprocessor but the following
-  # allows the -E option to be supported
-  preprocessor.command=cp %in% %out%
-  preprocessor.required=false
-
-##########################################################
-# Translator definitions
-##########################################################
-
-  # To compile stacker source, we just run the stacker
-  # compiler with a default stack size of 2048 entries.
-  translator.command=stkrc -s 2048 %in% -o %out% %time% \
-    %stats% %force% %args%
-
-  # stkrc doesn't preprocess but we set this to true so
-  # that we don't run the cp command by default.
-  translator.preprocesses=true
-
-  # The translator is required to run.
-  translator.required=true
-
-  # stkrc doesn't handle the -On options
-  translator.output=bitcode
-
-##########################################################
-# Optimizer definitions
-##########################################################
-  
-  # For optimization, we use the LLVM "opt" program
-  optimizer.command=opt %in% -o %out% %opt% %time% %stats% \
-    %force% %args%
-
-  optimizer.required = true
-
-  # opt doesn't translate
-  optimizer.translates = no
-
-  # opt doesn't preprocess
-  optimizer.preprocesses=no
-
-  # opt produces bitcode
-  optimizer.output = bc
-
-##########################################################
-# Assembler definitions
-##########################################################
-  assembler.command=llc %in% -o %out% %target% %time% %stats%
-
    -
    - - -
    Glossary
    - -
    -

    This document uses precise terms in reference to the various artifacts and - concepts related to compilation. The terms used throughout this document are - defined below.

    -
    -
    assembly
    -
    A compilation phase in which LLVM bitcode or - LLVM assembly code is assembled to a native code format (either target - specific aseembly language or the platform's native object file format). -
    - -
    compiler
    -
    Refers to any program that can be invoked by llvmc to accomplish - the work of one or more compilation phases.
    - -
    driver
    -
    Refers to llvmc itself.
    - -
    linking
    -
    A compilation phase in which LLVM bitcode files - and (optionally) native system libraries are combined to form a complete - executable program.
    - -
    optimization
    -
    A compilation phase in which LLVM bitcode is - optimized.
    - -
    phase
    -
    Refers to any one of the five compilation phases that that - llvmc supports. The five phases are: - preprocessing, - translation, - optimization, - assembly, - linking.
    - -
    source language
    -
    Any common programming language (e.g. C, C++, Java, Stacker, ML, - FORTRAN). These languages are distinguished from any of the lower level - languages (such as LLVM or native assembly), by the fact that a - translation phase - is required before LLVM can be applied.
    - -
    tool
    -
    Refers to any program in the LLVM tool set.
    - -
    translation
    -
    A compilation phase in which - source language code is translated into - either LLVM assembly language or LLVM bitcode.
    -
    -
    - -
    -
    Valid CSS!Valid HTML 4.01!Reid Spencer
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    From asl at math.spbu.ru Sun Jun 8 23:21:50 2008 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Mon, 09 Jun 2008 04:21:50 -0000 Subject: [llvm-commits] [llvm] r52118 - /llvm/trunk/docs/CompilerDriver.html Message-ID: <200806090421.m594LoTD017293@zion.cs.uiuc.edu> Author: asl Date: Sun Jun 8 23:21:50 2008 New Revision: 52118 URL: http://llvm.org/viewvc/llvm-project?rev=52118&view=rev Log: Use proper icon :) Modified: llvm/trunk/docs/CompilerDriver.html Modified: llvm/trunk/docs/CompilerDriver.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CompilerDriver.html?rev=52118&r1=52117&r2=52118&view=diff ============================================================================== --- llvm/trunk/docs/CompilerDriver.html (original) +++ llvm/trunk/docs/CompilerDriver.html Sun Jun 8 23:21:50 2008 @@ -412,7 +412,7 @@ Valid CSS! Valid HTML 4.01! + src="http://www.w3.org/Icons/valid-xhtml10" alt="Valid XHTML 1.0!" /> The LLVM Compiler Infrastructure
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    From gohman at apple.com Sun Jun 8 23:36:34 2008 From: gohman at apple.com (Dan Gohman) Date: Mon, 09 Jun 2008 04:36:34 -0000 Subject: [llvm-commits] [llvm] r52119 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <200806090436.m594aY8u017686@zion.cs.uiuc.edu> Author: djg Date: Sun Jun 8 23:36:34 2008 New Revision: 52119 URL: http://llvm.org/viewvc/llvm-project?rev=52119&view=rev Log: Add a note in the API Changes section about the ConstantFP::get change. Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=52119&r1=52118&r2=52119&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Sun Jun 8 23:36:34 2008 @@ -112,6 +112,9 @@
  • The '-enable-eh' flag to llc has been removed. Now code should encode whether it is safe to omit unwind information for a function by tagging the Function object with the 'nounwind' attribute.
    • +
  • The ConstantFP::get method that uses APFloat now takes one argument + instead of two. The type argument has been removed, and the type is + now inferred from the size of the given APFloat value.